1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t AVRRegDiffLists[] = {
12 /* 0 */ -2, 0,
13 /* 2 */ 2, -1, 0,
14 /* 5 */ -32, 1, 0,
15 /* 8 */ -31, 1, 0,
16 /* 11 */ -30, 1, 0,
17 /* 14 */ -29, 1, 0,
18 /* 17 */ -28, 1, 0,
19 /* 20 */ -27, 1, 0,
20 /* 23 */ -26, 1, 0,
21 /* 26 */ 27, 1, 0,
22 /* 29 */ 25, 0,
23 /* 31 */ 26, 0,
24 /* 33 */ 27, 0,
25 /* 35 */ 28, 0,
26 /* 37 */ 29, 0,
27 /* 39 */ 30, 0,
28 /* 41 */ 31, 0,
29 /* 43 */ 32, 0,
30};
31
32extern const LaneBitmask AVRLaneMaskLists[] = {
33 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
34 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
35};
36
37extern const uint16_t AVRSubRegIdxLists[] = {
38 /* 0 */ 2, 1,
39};
40
41
42#ifdef __GNUC__
43#pragma GCC diagnostic push
44#pragma GCC diagnostic ignored "-Woverlength-strings"
45#endif
46extern const char AVRRegStrings[] = {
47 /* 0 */ "R11R10\000"
48 /* 7 */ "R21R20\000"
49 /* 14 */ "R31R30\000"
50 /* 21 */ "R1R0\000"
51 /* 26 */ "R12R11\000"
52 /* 33 */ "R22R21\000"
53 /* 40 */ "R31\000"
54 /* 44 */ "R1\000"
55 /* 47 */ "R13R12\000"
56 /* 54 */ "R23R22\000"
57 /* 61 */ "R3R2\000"
58 /* 66 */ "R14R13\000"
59 /* 73 */ "R24R23\000"
60 /* 80 */ "R3\000"
61 /* 83 */ "R15R14\000"
62 /* 90 */ "R25R24\000"
63 /* 97 */ "R5R4\000"
64 /* 102 */ "R16R15\000"
65 /* 109 */ "R26R25\000"
66 /* 116 */ "R5\000"
67 /* 119 */ "R17R16\000"
68 /* 126 */ "R27R26\000"
69 /* 133 */ "R7R6\000"
70 /* 138 */ "R18R17\000"
71 /* 145 */ "R27\000"
72 /* 149 */ "R7\000"
73 /* 152 */ "R19R18\000"
74 /* 159 */ "R29R28\000"
75 /* 166 */ "R9R8\000"
76 /* 171 */ "R20R19\000"
77 /* 178 */ "R29\000"
78 /* 182 */ "R10R9\000"
79 /* 188 */ "SREG\000"
80 /* 193 */ "SPH\000"
81 /* 197 */ "SPL\000"
82 /* 201 */ "SP\000"
83};
84#ifdef __GNUC__
85#pragma GCC diagnostic pop
86#endif
87
88extern const MCRegisterDesc AVRRegDesc[] = { // Descriptors
89 { .Name: 6, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
90 { .Name: 201, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24576, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
91 { .Name: 193, .SubRegs: 1, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 4097, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
92 { .Name: 197, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 2, .RegUnits: 4096, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
93 { .Name: 188, .SubRegs: 1, .SuperRegs: 1, .SubRegIndices: 2, .RegUnits: 4098, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
94 { .Name: 23, .SubRegs: 1, .SuperRegs: 43, .SubRegIndices: 2, .RegUnits: 4099, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
95 { .Name: 44, .SubRegs: 1, .SuperRegs: 41, .SubRegIndices: 2, .RegUnits: 4100, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
96 { .Name: 63, .SubRegs: 1, .SuperRegs: 41, .SubRegIndices: 2, .RegUnits: 4101, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
97 { .Name: 80, .SubRegs: 1, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 4102, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
98 { .Name: 99, .SubRegs: 1, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 4103, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
99 { .Name: 116, .SubRegs: 1, .SuperRegs: 37, .SubRegIndices: 2, .RegUnits: 4104, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
100 { .Name: 135, .SubRegs: 1, .SuperRegs: 37, .SubRegIndices: 2, .RegUnits: 4105, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
101 { .Name: 149, .SubRegs: 1, .SuperRegs: 35, .SubRegIndices: 2, .RegUnits: 4106, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
102 { .Name: 168, .SubRegs: 1, .SuperRegs: 35, .SubRegIndices: 2, .RegUnits: 4107, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
103 { .Name: 185, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4108, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
104 { .Name: 3, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4109, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
105 { .Name: 29, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4110, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
106 { .Name: 50, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4111, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
107 { .Name: 69, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4112, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
108 { .Name: 86, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4113, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
109 { .Name: 105, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4114, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
110 { .Name: 122, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4115, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
111 { .Name: 141, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4116, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
112 { .Name: 155, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4117, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
113 { .Name: 174, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4118, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
114 { .Name: 10, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4119, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
115 { .Name: 36, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4120, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
116 { .Name: 57, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4121, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
117 { .Name: 76, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4122, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
118 { .Name: 93, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4123, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
119 { .Name: 112, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4124, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
120 { .Name: 129, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4125, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
121 { .Name: 145, .SubRegs: 1, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 4126, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
122 { .Name: 162, .SubRegs: 1, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 4127, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
123 { .Name: 178, .SubRegs: 1, .SuperRegs: 31, .SubRegIndices: 2, .RegUnits: 4128, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
124 { .Name: 17, .SubRegs: 1, .SuperRegs: 31, .SubRegIndices: 2, .RegUnits: 4129, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
125 { .Name: 40, .SubRegs: 1, .SuperRegs: 29, .SubRegIndices: 2, .RegUnits: 4130, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
126 { .Name: 21, .SubRegs: 5, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24579, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
127 { .Name: 61, .SubRegs: 8, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24581, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
128 { .Name: 97, .SubRegs: 11, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24583, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
129 { .Name: 133, .SubRegs: 14, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24585, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
130 { .Name: 166, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24587, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
131 { .Name: 182, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24588, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
132 { .Name: 0, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24589, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
133 { .Name: 26, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24590, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
134 { .Name: 47, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24591, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
135 { .Name: 66, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24592, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
136 { .Name: 83, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24593, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
137 { .Name: 102, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24594, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
138 { .Name: 119, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24595, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
139 { .Name: 138, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24596, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
140 { .Name: 152, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24597, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
141 { .Name: 171, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24598, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
142 { .Name: 7, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24599, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
143 { .Name: 33, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24600, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
144 { .Name: 54, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24601, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
145 { .Name: 73, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24602, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
146 { .Name: 90, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24603, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
147 { .Name: 109, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24604, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
148 { .Name: 126, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24605, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
149 { .Name: 159, .SubRegs: 20, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24607, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
150 { .Name: 14, .SubRegs: 23, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24609, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
151};
152
153extern const MCPhysReg AVRRegUnitRoots[][2] = {
154 { AVR::SPL },
155 { AVR::SPH },
156 { AVR::SREG },
157 { AVR::R0 },
158 { AVR::R1 },
159 { AVR::R2 },
160 { AVR::R3 },
161 { AVR::R4 },
162 { AVR::R5 },
163 { AVR::R6 },
164 { AVR::R7 },
165 { AVR::R8 },
166 { AVR::R9 },
167 { AVR::R10 },
168 { AVR::R11 },
169 { AVR::R12 },
170 { AVR::R13 },
171 { AVR::R14 },
172 { AVR::R15 },
173 { AVR::R16 },
174 { AVR::R17 },
175 { AVR::R18 },
176 { AVR::R19 },
177 { AVR::R20 },
178 { AVR::R21 },
179 { AVR::R22 },
180 { AVR::R23 },
181 { AVR::R24 },
182 { AVR::R25 },
183 { AVR::R26 },
184 { AVR::R27 },
185 { AVR::R28 },
186 { AVR::R29 },
187 { AVR::R30 },
188 { AVR::R31 },
189};
190
191// Register classes...
192
193#ifdef __GNUC__
194#pragma GCC diagnostic push
195#pragma GCC diagnostic ignored "-Woverlength-strings"
196#endif
197extern const char AVRRegClassStrings[] = {
198 /* 0 */ "GPR8NOZ_and_LD8\000"
199 /* 16 */ "DREGSNOZ_and_DREGS_with_sub_hi_in_LD8\000"
200 /* 54 */ "DREGSNOZ_and_DREGS_with_sub_lo_in_LD8\000"
201 /* 92 */ "DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8\000"
202 /* 148 */ "GPR8\000"
203 /* 153 */ "ZREG\000"
204 /* 158 */ "GPRSP\000"
205 /* 164 */ "CCR\000"
206 /* 168 */ "DLDREGS\000"
207 /* 176 */ "DREGSNOZ_and_PTRDISPREGS\000"
208 /* 201 */ "DREGSNOZ_and_PTRREGS\000"
209 /* 222 */ "DREGSNOZ_and_IWREGS\000"
210 /* 242 */ "DREGSMOVW\000"
211 /* 252 */ "GPR8NOZ\000"
212 /* 260 */ "DLDREGS_and_DREGSNOZ\000"
213 /* 281 */ "DREGSMOVW_and_DREGSNOZ\000"
214 /* 304 */ "DREGSLD8lo\000"
215 /* 315 */ "DREGS_with_sub_hi_in_LD8lo\000"
216 /* 342 */ "DREGS_with_sub_lo_in_LD8lo\000"
217 /* 369 */ "DREGS_with_sub_hi_in_GPR8lo\000"
218 /* 397 */ "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo\000"
219 /* 454 */ "DREGSlo\000"
220};
221#ifdef __GNUC__
222#pragma GCC diagnostic pop
223#endif
224
225using AVRRegisterClassStorage = MCRegisterClassStorage<33, 340, 61, 90, 3, 153>;
226extern const MCRegisterClassStorage<33, 340, 61, 90, 3, 153> AVRMCRegisterClassStorage = {
227 .Classes: {
228 {
229 offsetof(AVRRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
230 offsetof(AVRRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
231 .NameIdx: 148,
232 .RegSizeInBits: 8,
233 .RegsSize: 32,
234 .RegSetBegin: 5, /* MinRegVal */
235 .RegSetSize: 32, /* RegSetSize */
236 .ID: AVR::GPR8RegClassID,
237 .CopyCost: 1, /* CopyCost */
238 .Allocatable: true, /* Allocatable */
239 .BaseClass: false,
240 offsetof(AVRRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
241 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
242 .LaneMask: LaneBitmask(0x0000000000000001),
243 .AllocationPriority: 0,
244 .GlobalPriority: false,
245 .TSFlags: 0x00, /* TSFlags */
246 .SpillStackID: 0, /* SpillStackID */
247 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
248 .CoveredBySubRegs: false, /* CoveredBySubRegs */
249 offsetof(AVRRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
250 .SuperClassesSize: 0
251 },
252 {
253 offsetof(AVRRegisterClassStorage, Regs[32]) - 1 * sizeof(MCRegisterClass),
254 offsetof(AVRRegisterClassStorage, BitSets[4]) - 1 * sizeof(MCRegisterClass),
255 .NameIdx: 252,
256 .RegSizeInBits: 8,
257 .RegsSize: 30,
258 .RegSetBegin: 5, /* MinRegVal */
259 .RegSetSize: 30, /* RegSetSize */
260 .ID: AVR::GPR8NOZRegClassID,
261 .CopyCost: 1, /* CopyCost */
262 .Allocatable: true, /* Allocatable */
263 .BaseClass: false,
264 offsetof(AVRRegisterClassStorage, SubClassMasks[6]) - 1 * sizeof(MCRegisterClass),
265 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 1 * sizeof(MCRegisterClass),
266 .LaneMask: LaneBitmask(0x0000000000000001),
267 .AllocationPriority: 0,
268 .GlobalPriority: false,
269 .TSFlags: 0x00, /* TSFlags */
270 .SpillStackID: 0, /* SpillStackID */
271 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
272 .CoveredBySubRegs: false, /* CoveredBySubRegs */
273 offsetof(AVRRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
274 .SuperClassesSize: 1
275 },
276 {
277 offsetof(AVRRegisterClassStorage, Regs[62]) - 2 * sizeof(MCRegisterClass),
278 offsetof(AVRRegisterClassStorage, BitSets[8]) - 2 * sizeof(MCRegisterClass),
279 .NameIdx: 390,
280 .RegSizeInBits: 8,
281 .RegsSize: 16,
282 .RegSetBegin: 5, /* MinRegVal */
283 .RegSetSize: 16, /* RegSetSize */
284 .ID: AVR::GPR8loRegClassID,
285 .CopyCost: 1, /* CopyCost */
286 .Allocatable: true, /* Allocatable */
287 .BaseClass: false,
288 offsetof(AVRRegisterClassStorage, SubClassMasks[12]) - 2 * sizeof(MCRegisterClass),
289 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 2 * sizeof(MCRegisterClass),
290 .LaneMask: LaneBitmask(0x0000000000000001),
291 .AllocationPriority: 0,
292 .GlobalPriority: false,
293 .TSFlags: 0x00, /* TSFlags */
294 .SpillStackID: 0, /* SpillStackID */
295 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
296 .CoveredBySubRegs: false, /* CoveredBySubRegs */
297 offsetof(AVRRegisterClassStorage, SuperClasses[1]) - 2 * sizeof(MCRegisterClass),
298 .SuperClassesSize: 2
299 },
300 {
301 offsetof(AVRRegisterClassStorage, Regs[78]) - 3 * sizeof(MCRegisterClass),
302 offsetof(AVRRegisterClassStorage, BitSets[10]) - 3 * sizeof(MCRegisterClass),
303 .NameIdx: 12,
304 .RegSizeInBits: 8,
305 .RegsSize: 16,
306 .RegSetBegin: 21, /* MinRegVal */
307 .RegSetSize: 16, /* RegSetSize */
308 .ID: AVR::LD8RegClassID,
309 .CopyCost: 1, /* CopyCost */
310 .Allocatable: true, /* Allocatable */
311 .BaseClass: false,
312 offsetof(AVRRegisterClassStorage, SubClassMasks[18]) - 3 * sizeof(MCRegisterClass),
313 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 3 * sizeof(MCRegisterClass),
314 .LaneMask: LaneBitmask(0x0000000000000001),
315 .AllocationPriority: 0,
316 .GlobalPriority: false,
317 .TSFlags: 0x00, /* TSFlags */
318 .SpillStackID: 0, /* SpillStackID */
319 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
320 .CoveredBySubRegs: false, /* CoveredBySubRegs */
321 offsetof(AVRRegisterClassStorage, SuperClasses[3]) - 3 * sizeof(MCRegisterClass),
322 .SuperClassesSize: 1
323 },
324 {
325 offsetof(AVRRegisterClassStorage, Regs[94]) - 4 * sizeof(MCRegisterClass),
326 offsetof(AVRRegisterClassStorage, BitSets[12]) - 4 * sizeof(MCRegisterClass),
327 .NameIdx: 0,
328 .RegSizeInBits: 8,
329 .RegsSize: 14,
330 .RegSetBegin: 21, /* MinRegVal */
331 .RegSetSize: 14, /* RegSetSize */
332 .ID: AVR::GPR8NOZ_and_LD8RegClassID,
333 .CopyCost: 1, /* CopyCost */
334 .Allocatable: true, /* Allocatable */
335 .BaseClass: false,
336 offsetof(AVRRegisterClassStorage, SubClassMasks[24]) - 4 * sizeof(MCRegisterClass),
337 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 4 * sizeof(MCRegisterClass),
338 .LaneMask: LaneBitmask(0x0000000000000001),
339 .AllocationPriority: 0,
340 .GlobalPriority: false,
341 .TSFlags: 0x00, /* TSFlags */
342 .SpillStackID: 0, /* SpillStackID */
343 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
344 .CoveredBySubRegs: false, /* CoveredBySubRegs */
345 offsetof(AVRRegisterClassStorage, SuperClasses[4]) - 4 * sizeof(MCRegisterClass),
346 .SuperClassesSize: 3
347 },
348 {
349 offsetof(AVRRegisterClassStorage, Regs[108]) - 5 * sizeof(MCRegisterClass),
350 offsetof(AVRRegisterClassStorage, BitSets[14]) - 5 * sizeof(MCRegisterClass),
351 .NameIdx: 309,
352 .RegSizeInBits: 8,
353 .RegsSize: 8,
354 .RegSetBegin: 21, /* MinRegVal */
355 .RegSetSize: 8, /* RegSetSize */
356 .ID: AVR::LD8loRegClassID,
357 .CopyCost: 1, /* CopyCost */
358 .Allocatable: true, /* Allocatable */
359 .BaseClass: false,
360 offsetof(AVRRegisterClassStorage, SubClassMasks[30]) - 5 * sizeof(MCRegisterClass),
361 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass),
362 .LaneMask: LaneBitmask(0x0000000000000001),
363 .AllocationPriority: 0,
364 .GlobalPriority: false,
365 .TSFlags: 0x00, /* TSFlags */
366 .SpillStackID: 0, /* SpillStackID */
367 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
368 .CoveredBySubRegs: false, /* CoveredBySubRegs */
369 offsetof(AVRRegisterClassStorage, SuperClasses[7]) - 5 * sizeof(MCRegisterClass),
370 .SuperClassesSize: 4
371 },
372 {
373 offsetof(AVRRegisterClassStorage, Regs[116]) - 6 * sizeof(MCRegisterClass),
374 offsetof(AVRRegisterClassStorage, BitSets[15]) - 6 * sizeof(MCRegisterClass),
375 .NameIdx: 164,
376 .RegSizeInBits: 8,
377 .RegsSize: 1,
378 .RegSetBegin: 4, /* MinRegVal */
379 .RegSetSize: 1, /* RegSetSize */
380 .ID: AVR::CCRRegClassID,
381 .CopyCost: 255, /* CopyCost */
382 .Allocatable: true, /* Allocatable */
383 .BaseClass: false,
384 offsetof(AVRRegisterClassStorage, SubClassMasks[36]) - 6 * sizeof(MCRegisterClass),
385 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 6 * sizeof(MCRegisterClass),
386 .LaneMask: LaneBitmask(0x0000000000000001),
387 .AllocationPriority: 0,
388 .GlobalPriority: false,
389 .TSFlags: 0x00, /* TSFlags */
390 .SpillStackID: 0, /* SpillStackID */
391 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
392 .CoveredBySubRegs: false, /* CoveredBySubRegs */
393 offsetof(AVRRegisterClassStorage, SuperClasses[11]) - 6 * sizeof(MCRegisterClass),
394 .SuperClassesSize: 0
395 },
396 {
397 offsetof(AVRRegisterClassStorage, Regs[117]) - 7 * sizeof(MCRegisterClass),
398 offsetof(AVRRegisterClassStorage, BitSets[16]) - 7 * sizeof(MCRegisterClass),
399 .NameIdx: 170,
400 .RegSizeInBits: 16,
401 .RegsSize: 25,
402 .RegSetBegin: 37, /* MinRegVal */
403 .RegSetSize: 25, /* RegSetSize */
404 .ID: AVR::DREGSRegClassID,
405 .CopyCost: 1, /* CopyCost */
406 .Allocatable: true, /* Allocatable */
407 .BaseClass: false,
408 offsetof(AVRRegisterClassStorage, SubClassMasks[38]) - 7 * sizeof(MCRegisterClass),
409 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 7 * sizeof(MCRegisterClass),
410 .LaneMask: LaneBitmask(0x0000000000000003),
411 .AllocationPriority: 0,
412 .GlobalPriority: false,
413 .TSFlags: 0x00, /* TSFlags */
414 .SpillStackID: 0, /* SpillStackID */
415 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
416 .CoveredBySubRegs: true, /* CoveredBySubRegs */
417 offsetof(AVRRegisterClassStorage, SuperClasses[11]) - 7 * sizeof(MCRegisterClass),
418 .SuperClassesSize: 0
419 },
420 {
421 offsetof(AVRRegisterClassStorage, Regs[142]) - 8 * sizeof(MCRegisterClass),
422 offsetof(AVRRegisterClassStorage, BitSets[20]) - 8 * sizeof(MCRegisterClass),
423 .NameIdx: 272,
424 .RegSizeInBits: 16,
425 .RegsSize: 24,
426 .RegSetBegin: 37, /* MinRegVal */
427 .RegSetSize: 24, /* RegSetSize */
428 .ID: AVR::DREGSNOZRegClassID,
429 .CopyCost: 1, /* CopyCost */
430 .Allocatable: true, /* Allocatable */
431 .BaseClass: false,
432 offsetof(AVRRegisterClassStorage, SubClassMasks[40]) - 8 * sizeof(MCRegisterClass),
433 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 8 * sizeof(MCRegisterClass),
434 .LaneMask: LaneBitmask(0x0000000000000003),
435 .AllocationPriority: 0,
436 .GlobalPriority: false,
437 .TSFlags: 0x00, /* TSFlags */
438 .SpillStackID: 0, /* SpillStackID */
439 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
440 .CoveredBySubRegs: true, /* CoveredBySubRegs */
441 offsetof(AVRRegisterClassStorage, SuperClasses[11]) - 8 * sizeof(MCRegisterClass),
442 .SuperClassesSize: 1
443 },
444 {
445 offsetof(AVRRegisterClassStorage, Regs[166]) - 9 * sizeof(MCRegisterClass),
446 offsetof(AVRRegisterClassStorage, BitSets[23]) - 9 * sizeof(MCRegisterClass),
447 .NameIdx: 242,
448 .RegSizeInBits: 16,
449 .RegsSize: 16,
450 .RegSetBegin: 37, /* MinRegVal */
451 .RegSetSize: 25, /* RegSetSize */
452 .ID: AVR::DREGSMOVWRegClassID,
453 .CopyCost: 1, /* CopyCost */
454 .Allocatable: true, /* Allocatable */
455 .BaseClass: false,
456 offsetof(AVRRegisterClassStorage, SubClassMasks[42]) - 9 * sizeof(MCRegisterClass),
457 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 9 * sizeof(MCRegisterClass),
458 .LaneMask: LaneBitmask(0x0000000000000003),
459 .AllocationPriority: 0,
460 .GlobalPriority: false,
461 .TSFlags: 0x00, /* TSFlags */
462 .SpillStackID: 0, /* SpillStackID */
463 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
464 .CoveredBySubRegs: true, /* CoveredBySubRegs */
465 offsetof(AVRRegisterClassStorage, SuperClasses[12]) - 9 * sizeof(MCRegisterClass),
466 .SuperClassesSize: 1
467 },
468 {
469 offsetof(AVRRegisterClassStorage, Regs[182]) - 10 * sizeof(MCRegisterClass),
470 offsetof(AVRRegisterClassStorage, BitSets[27]) - 10 * sizeof(MCRegisterClass),
471 .NameIdx: 281,
472 .RegSizeInBits: 16,
473 .RegsSize: 15,
474 .RegSetBegin: 37, /* MinRegVal */
475 .RegSetSize: 24, /* RegSetSize */
476 .ID: AVR::DREGSMOVW_and_DREGSNOZRegClassID,
477 .CopyCost: 1, /* CopyCost */
478 .Allocatable: true, /* Allocatable */
479 .BaseClass: false,
480 offsetof(AVRRegisterClassStorage, SubClassMasks[44]) - 10 * sizeof(MCRegisterClass),
481 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 10 * sizeof(MCRegisterClass),
482 .LaneMask: LaneBitmask(0x0000000000000003),
483 .AllocationPriority: 0,
484 .GlobalPriority: false,
485 .TSFlags: 0x00, /* TSFlags */
486 .SpillStackID: 0, /* SpillStackID */
487 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
488 .CoveredBySubRegs: true, /* CoveredBySubRegs */
489 offsetof(AVRRegisterClassStorage, SuperClasses[13]) - 10 * sizeof(MCRegisterClass),
490 .SuperClassesSize: 3
491 },
492 {
493 offsetof(AVRRegisterClassStorage, Regs[197]) - 11 * sizeof(MCRegisterClass),
494 offsetof(AVRRegisterClassStorage, BitSets[30]) - 11 * sizeof(MCRegisterClass),
495 .NameIdx: 29,
496 .RegSizeInBits: 16,
497 .RegsSize: 14,
498 .RegSetBegin: 48, /* MinRegVal */
499 .RegSetSize: 14, /* RegSetSize */
500 .ID: AVR::DREGS_with_sub_hi_in_LD8RegClassID,
501 .CopyCost: 1, /* CopyCost */
502 .Allocatable: true, /* Allocatable */
503 .BaseClass: false,
504 offsetof(AVRRegisterClassStorage, SubClassMasks[46]) - 11 * sizeof(MCRegisterClass),
505 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 11 * sizeof(MCRegisterClass),
506 .LaneMask: LaneBitmask(0x0000000000000003),
507 .AllocationPriority: 0,
508 .GlobalPriority: false,
509 .TSFlags: 0x00, /* TSFlags */
510 .SpillStackID: 0, /* SpillStackID */
511 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
512 .CoveredBySubRegs: true, /* CoveredBySubRegs */
513 offsetof(AVRRegisterClassStorage, SuperClasses[16]) - 11 * sizeof(MCRegisterClass),
514 .SuperClassesSize: 1
515 },
516 {
517 offsetof(AVRRegisterClassStorage, Regs[211]) - 12 * sizeof(MCRegisterClass),
518 offsetof(AVRRegisterClassStorage, BitSets[32]) - 12 * sizeof(MCRegisterClass),
519 .NameIdx: 16,
520 .RegSizeInBits: 16,
521 .RegsSize: 13,
522 .RegSetBegin: 48, /* MinRegVal */
523 .RegSetSize: 13, /* RegSetSize */
524 .ID: AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
525 .CopyCost: 1, /* CopyCost */
526 .Allocatable: true, /* Allocatable */
527 .BaseClass: false,
528 offsetof(AVRRegisterClassStorage, SubClassMasks[48]) - 12 * sizeof(MCRegisterClass),
529 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 12 * sizeof(MCRegisterClass),
530 .LaneMask: LaneBitmask(0x0000000000000003),
531 .AllocationPriority: 0,
532 .GlobalPriority: false,
533 .TSFlags: 0x00, /* TSFlags */
534 .SpillStackID: 0, /* SpillStackID */
535 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
536 .CoveredBySubRegs: true, /* CoveredBySubRegs */
537 offsetof(AVRRegisterClassStorage, SuperClasses[17]) - 12 * sizeof(MCRegisterClass),
538 .SuperClassesSize: 3
539 },
540 {
541 offsetof(AVRRegisterClassStorage, Regs[224]) - 13 * sizeof(MCRegisterClass),
542 offsetof(AVRRegisterClassStorage, BitSets[34]) - 13 * sizeof(MCRegisterClass),
543 .NameIdx: 67,
544 .RegSizeInBits: 16,
545 .RegsSize: 13,
546 .RegSetBegin: 49, /* MinRegVal */
547 .RegSetSize: 13, /* RegSetSize */
548 .ID: AVR::DREGS_with_sub_lo_in_LD8RegClassID,
549 .CopyCost: 1, /* CopyCost */
550 .Allocatable: true, /* Allocatable */
551 .BaseClass: false,
552 offsetof(AVRRegisterClassStorage, SubClassMasks[50]) - 13 * sizeof(MCRegisterClass),
553 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 13 * sizeof(MCRegisterClass),
554 .LaneMask: LaneBitmask(0x0000000000000003),
555 .AllocationPriority: 0,
556 .GlobalPriority: false,
557 .TSFlags: 0x00, /* TSFlags */
558 .SpillStackID: 0, /* SpillStackID */
559 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
560 .CoveredBySubRegs: true, /* CoveredBySubRegs */
561 offsetof(AVRRegisterClassStorage, SuperClasses[20]) - 13 * sizeof(MCRegisterClass),
562 .SuperClassesSize: 2
563 },
564 {
565 offsetof(AVRRegisterClassStorage, Regs[237]) - 14 * sizeof(MCRegisterClass),
566 offsetof(AVRRegisterClassStorage, BitSets[36]) - 14 * sizeof(MCRegisterClass),
567 .NameIdx: 54,
568 .RegSizeInBits: 16,
569 .RegsSize: 12,
570 .RegSetBegin: 49, /* MinRegVal */
571 .RegSetSize: 12, /* RegSetSize */
572 .ID: AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
573 .CopyCost: 1, /* CopyCost */
574 .Allocatable: true, /* Allocatable */
575 .BaseClass: false,
576 offsetof(AVRRegisterClassStorage, SubClassMasks[52]) - 14 * sizeof(MCRegisterClass),
577 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 14 * sizeof(MCRegisterClass),
578 .LaneMask: LaneBitmask(0x0000000000000003),
579 .AllocationPriority: 0,
580 .GlobalPriority: false,
581 .TSFlags: 0x00, /* TSFlags */
582 .SpillStackID: 0, /* SpillStackID */
583 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
584 .CoveredBySubRegs: true, /* CoveredBySubRegs */
585 offsetof(AVRRegisterClassStorage, SuperClasses[22]) - 14 * sizeof(MCRegisterClass),
586 .SuperClassesSize: 5
587 },
588 {
589 offsetof(AVRRegisterClassStorage, Regs[249]) - 15 * sizeof(MCRegisterClass),
590 offsetof(AVRRegisterClassStorage, BitSets[38]) - 15 * sizeof(MCRegisterClass),
591 .NameIdx: 426,
592 .RegSizeInBits: 16,
593 .RegsSize: 12,
594 .RegSetBegin: 37, /* MinRegVal */
595 .RegSetSize: 12, /* RegSetSize */
596 .ID: AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
597 .CopyCost: 1, /* CopyCost */
598 .Allocatable: true, /* Allocatable */
599 .BaseClass: false,
600 offsetof(AVRRegisterClassStorage, SubClassMasks[54]) - 15 * sizeof(MCRegisterClass),
601 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 15 * sizeof(MCRegisterClass),
602 .LaneMask: LaneBitmask(0x0000000000000003),
603 .AllocationPriority: 0,
604 .GlobalPriority: false,
605 .TSFlags: 0x00, /* TSFlags */
606 .SpillStackID: 0, /* SpillStackID */
607 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
608 .CoveredBySubRegs: true, /* CoveredBySubRegs */
609 offsetof(AVRRegisterClassStorage, SuperClasses[27]) - 15 * sizeof(MCRegisterClass),
610 .SuperClassesSize: 2
611 },
612 {
613 offsetof(AVRRegisterClassStorage, Regs[261]) - 16 * sizeof(MCRegisterClass),
614 offsetof(AVRRegisterClassStorage, BitSets[40]) - 16 * sizeof(MCRegisterClass),
615 .NameIdx: 369,
616 .RegSizeInBits: 16,
617 .RegsSize: 11,
618 .RegSetBegin: 37, /* MinRegVal */
619 .RegSetSize: 11, /* RegSetSize */
620 .ID: AVR::DREGS_with_sub_hi_in_GPR8loRegClassID,
621 .CopyCost: 1, /* CopyCost */
622 .Allocatable: true, /* Allocatable */
623 .BaseClass: false,
624 offsetof(AVRRegisterClassStorage, SubClassMasks[56]) - 16 * sizeof(MCRegisterClass),
625 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 16 * sizeof(MCRegisterClass),
626 .LaneMask: LaneBitmask(0x0000000000000003),
627 .AllocationPriority: 0,
628 .GlobalPriority: false,
629 .TSFlags: 0x00, /* TSFlags */
630 .SpillStackID: 0, /* SpillStackID */
631 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
632 .CoveredBySubRegs: true, /* CoveredBySubRegs */
633 offsetof(AVRRegisterClassStorage, SuperClasses[29]) - 16 * sizeof(MCRegisterClass),
634 .SuperClassesSize: 3
635 },
636 {
637 offsetof(AVRRegisterClassStorage, Regs[272]) - 17 * sizeof(MCRegisterClass),
638 offsetof(AVRRegisterClassStorage, BitSets[42]) - 17 * sizeof(MCRegisterClass),
639 .NameIdx: 168,
640 .RegSizeInBits: 16,
641 .RegsSize: 8,
642 .RegSetBegin: 49, /* MinRegVal */
643 .RegSetSize: 13, /* RegSetSize */
644 .ID: AVR::DLDREGSRegClassID,
645 .CopyCost: 1, /* CopyCost */
646 .Allocatable: true, /* Allocatable */
647 .BaseClass: false,
648 offsetof(AVRRegisterClassStorage, SubClassMasks[58]) - 17 * sizeof(MCRegisterClass),
649 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 17 * sizeof(MCRegisterClass),
650 .LaneMask: LaneBitmask(0x0000000000000003),
651 .AllocationPriority: 0,
652 .GlobalPriority: false,
653 .TSFlags: 0x00, /* TSFlags */
654 .SpillStackID: 0, /* SpillStackID */
655 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
656 .CoveredBySubRegs: true, /* CoveredBySubRegs */
657 offsetof(AVRRegisterClassStorage, SuperClasses[32]) - 17 * sizeof(MCRegisterClass),
658 .SuperClassesSize: 4
659 },
660 {
661 offsetof(AVRRegisterClassStorage, Regs[280]) - 18 * sizeof(MCRegisterClass),
662 offsetof(AVRRegisterClassStorage, BitSets[44]) - 18 * sizeof(MCRegisterClass),
663 .NameIdx: 315,
664 .RegSizeInBits: 16,
665 .RegsSize: 8,
666 .RegSetBegin: 48, /* MinRegVal */
667 .RegSetSize: 8, /* RegSetSize */
668 .ID: AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
669 .CopyCost: 1, /* CopyCost */
670 .Allocatable: true, /* Allocatable */
671 .BaseClass: false,
672 offsetof(AVRRegisterClassStorage, SubClassMasks[60]) - 18 * sizeof(MCRegisterClass),
673 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 18 * sizeof(MCRegisterClass),
674 .LaneMask: LaneBitmask(0x0000000000000003),
675 .AllocationPriority: 0,
676 .GlobalPriority: false,
677 .TSFlags: 0x00, /* TSFlags */
678 .SpillStackID: 0, /* SpillStackID */
679 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
680 .CoveredBySubRegs: true, /* CoveredBySubRegs */
681 offsetof(AVRRegisterClassStorage, SuperClasses[36]) - 18 * sizeof(MCRegisterClass),
682 .SuperClassesSize: 4
683 },
684 {
685 offsetof(AVRRegisterClassStorage, Regs[288]) - 19 * sizeof(MCRegisterClass),
686 offsetof(AVRRegisterClassStorage, BitSets[45]) - 19 * sizeof(MCRegisterClass),
687 .NameIdx: 342,
688 .RegSizeInBits: 16,
689 .RegsSize: 8,
690 .RegSetBegin: 49, /* MinRegVal */
691 .RegSetSize: 8, /* RegSetSize */
692 .ID: AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
693 .CopyCost: 1, /* CopyCost */
694 .Allocatable: true, /* Allocatable */
695 .BaseClass: false,
696 offsetof(AVRRegisterClassStorage, SubClassMasks[62]) - 19 * sizeof(MCRegisterClass),
697 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 19 * sizeof(MCRegisterClass),
698 .LaneMask: LaneBitmask(0x0000000000000003),
699 .AllocationPriority: 0,
700 .GlobalPriority: false,
701 .TSFlags: 0x00, /* TSFlags */
702 .SpillStackID: 0, /* SpillStackID */
703 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
704 .CoveredBySubRegs: true, /* CoveredBySubRegs */
705 offsetof(AVRRegisterClassStorage, SuperClasses[40]) - 19 * sizeof(MCRegisterClass),
706 .SuperClassesSize: 6
707 },
708 {
709 offsetof(AVRRegisterClassStorage, Regs[296]) - 20 * sizeof(MCRegisterClass),
710 offsetof(AVRRegisterClassStorage, BitSets[46]) - 20 * sizeof(MCRegisterClass),
711 .NameIdx: 454,
712 .RegSizeInBits: 16,
713 .RegsSize: 8,
714 .RegSetBegin: 37, /* MinRegVal */
715 .RegSetSize: 11, /* RegSetSize */
716 .ID: AVR::DREGSloRegClassID,
717 .CopyCost: 1, /* CopyCost */
718 .Allocatable: true, /* Allocatable */
719 .BaseClass: false,
720 offsetof(AVRRegisterClassStorage, SubClassMasks[64]) - 20 * sizeof(MCRegisterClass),
721 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 20 * sizeof(MCRegisterClass),
722 .LaneMask: LaneBitmask(0x0000000000000003),
723 .AllocationPriority: 0,
724 .GlobalPriority: false,
725 .TSFlags: 0x00, /* TSFlags */
726 .SpillStackID: 0, /* SpillStackID */
727 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
728 .CoveredBySubRegs: true, /* CoveredBySubRegs */
729 offsetof(AVRRegisterClassStorage, SuperClasses[46]) - 20 * sizeof(MCRegisterClass),
730 .SuperClassesSize: 6
731 },
732 {
733 offsetof(AVRRegisterClassStorage, Regs[304]) - 21 * sizeof(MCRegisterClass),
734 offsetof(AVRRegisterClassStorage, BitSets[48]) - 21 * sizeof(MCRegisterClass),
735 .NameIdx: 260,
736 .RegSizeInBits: 16,
737 .RegsSize: 7,
738 .RegSetBegin: 49, /* MinRegVal */
739 .RegSetSize: 12, /* RegSetSize */
740 .ID: AVR::DLDREGS_and_DREGSNOZRegClassID,
741 .CopyCost: 1, /* CopyCost */
742 .Allocatable: true, /* Allocatable */
743 .BaseClass: false,
744 offsetof(AVRRegisterClassStorage, SubClassMasks[66]) - 21 * sizeof(MCRegisterClass),
745 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 21 * sizeof(MCRegisterClass),
746 .LaneMask: LaneBitmask(0x0000000000000003),
747 .AllocationPriority: 0,
748 .GlobalPriority: false,
749 .TSFlags: 0x00, /* TSFlags */
750 .SpillStackID: 0, /* SpillStackID */
751 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
752 .CoveredBySubRegs: true, /* CoveredBySubRegs */
753 offsetof(AVRRegisterClassStorage, SuperClasses[52]) - 21 * sizeof(MCRegisterClass),
754 .SuperClassesSize: 9
755 },
756 {
757 offsetof(AVRRegisterClassStorage, Regs[311]) - 22 * sizeof(MCRegisterClass),
758 offsetof(AVRRegisterClassStorage, BitSets[50]) - 22 * sizeof(MCRegisterClass),
759 .NameIdx: 92,
760 .RegSizeInBits: 16,
761 .RegsSize: 7,
762 .RegSetBegin: 49, /* MinRegVal */
763 .RegSetSize: 7, /* RegSetSize */
764 .ID: AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID,
765 .CopyCost: 1, /* CopyCost */
766 .Allocatable: true, /* Allocatable */
767 .BaseClass: false,
768 offsetof(AVRRegisterClassStorage, SubClassMasks[68]) - 22 * sizeof(MCRegisterClass),
769 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 22 * sizeof(MCRegisterClass),
770 .LaneMask: LaneBitmask(0x0000000000000003),
771 .AllocationPriority: 0,
772 .GlobalPriority: false,
773 .TSFlags: 0x00, /* TSFlags */
774 .SpillStackID: 0, /* SpillStackID */
775 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
776 .CoveredBySubRegs: true, /* CoveredBySubRegs */
777 offsetof(AVRRegisterClassStorage, SuperClasses[61]) - 22 * sizeof(MCRegisterClass),
778 .SuperClassesSize: 8
779 },
780 {
781 offsetof(AVRRegisterClassStorage, Regs[318]) - 23 * sizeof(MCRegisterClass),
782 offsetof(AVRRegisterClassStorage, BitSets[51]) - 23 * sizeof(MCRegisterClass),
783 .NameIdx: 304,
784 .RegSizeInBits: 16,
785 .RegsSize: 4,
786 .RegSetBegin: 49, /* MinRegVal */
787 .RegSetSize: 7, /* RegSetSize */
788 .ID: AVR::DREGSLD8loRegClassID,
789 .CopyCost: 1, /* CopyCost */
790 .Allocatable: true, /* Allocatable */
791 .BaseClass: false,
792 offsetof(AVRRegisterClassStorage, SubClassMasks[70]) - 23 * sizeof(MCRegisterClass),
793 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 23 * sizeof(MCRegisterClass),
794 .LaneMask: LaneBitmask(0x0000000000000003),
795 .AllocationPriority: 0,
796 .GlobalPriority: false,
797 .TSFlags: 0x00, /* TSFlags */
798 .SpillStackID: 0, /* SpillStackID */
799 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
800 .CoveredBySubRegs: true, /* CoveredBySubRegs */
801 offsetof(AVRRegisterClassStorage, SuperClasses[69]) - 23 * sizeof(MCRegisterClass),
802 .SuperClassesSize: 13
803 },
804 {
805 offsetof(AVRRegisterClassStorage, Regs[322]) - 24 * sizeof(MCRegisterClass),
806 offsetof(AVRRegisterClassStorage, BitSets[52]) - 24 * sizeof(MCRegisterClass),
807 .NameIdx: 235,
808 .RegSizeInBits: 16,
809 .RegsSize: 4,
810 .RegSetBegin: 57, /* MinRegVal */
811 .RegSetSize: 5, /* RegSetSize */
812 .ID: AVR::IWREGSRegClassID,
813 .CopyCost: 1, /* CopyCost */
814 .Allocatable: true, /* Allocatable */
815 .BaseClass: false,
816 offsetof(AVRRegisterClassStorage, SubClassMasks[72]) - 24 * sizeof(MCRegisterClass),
817 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 24 * sizeof(MCRegisterClass),
818 .LaneMask: LaneBitmask(0x0000000000000003),
819 .AllocationPriority: 0,
820 .GlobalPriority: false,
821 .TSFlags: 0x00, /* TSFlags */
822 .SpillStackID: 0, /* SpillStackID */
823 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
824 .CoveredBySubRegs: true, /* CoveredBySubRegs */
825 offsetof(AVRRegisterClassStorage, SuperClasses[82]) - 24 * sizeof(MCRegisterClass),
826 .SuperClassesSize: 5
827 },
828 {
829 offsetof(AVRRegisterClassStorage, Regs[326]) - 25 * sizeof(MCRegisterClass),
830 offsetof(AVRRegisterClassStorage, BitSets[53]) - 25 * sizeof(MCRegisterClass),
831 .NameIdx: 222,
832 .RegSizeInBits: 16,
833 .RegsSize: 3,
834 .RegSetBegin: 57, /* MinRegVal */
835 .RegSetSize: 4, /* RegSetSize */
836 .ID: AVR::DREGSNOZ_and_IWREGSRegClassID,
837 .CopyCost: 1, /* CopyCost */
838 .Allocatable: true, /* Allocatable */
839 .BaseClass: false,
840 offsetof(AVRRegisterClassStorage, SubClassMasks[74]) - 25 * sizeof(MCRegisterClass),
841 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 25 * sizeof(MCRegisterClass),
842 .LaneMask: LaneBitmask(0x0000000000000003),
843 .AllocationPriority: 0,
844 .GlobalPriority: false,
845 .TSFlags: 0x00, /* TSFlags */
846 .SpillStackID: 0, /* SpillStackID */
847 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
848 .CoveredBySubRegs: true, /* CoveredBySubRegs */
849 offsetof(AVRRegisterClassStorage, SuperClasses[87]) - 25 * sizeof(MCRegisterClass),
850 .SuperClassesSize: 11
851 },
852 {
853 offsetof(AVRRegisterClassStorage, Regs[329]) - 26 * sizeof(MCRegisterClass),
854 offsetof(AVRRegisterClassStorage, BitSets[54]) - 26 * sizeof(MCRegisterClass),
855 .NameIdx: 214,
856 .RegSizeInBits: 16,
857 .RegsSize: 3,
858 .RegSetBegin: 59, /* MinRegVal */
859 .RegSetSize: 3, /* RegSetSize */
860 .ID: AVR::PTRREGSRegClassID,
861 .CopyCost: 1, /* CopyCost */
862 .Allocatable: true, /* Allocatable */
863 .BaseClass: false,
864 offsetof(AVRRegisterClassStorage, SubClassMasks[76]) - 26 * sizeof(MCRegisterClass),
865 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 26 * sizeof(MCRegisterClass),
866 .LaneMask: LaneBitmask(0x0000000000000003),
867 .AllocationPriority: 0,
868 .GlobalPriority: false,
869 .TSFlags: 0x00, /* TSFlags */
870 .SpillStackID: 0, /* SpillStackID */
871 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
872 .CoveredBySubRegs: true, /* CoveredBySubRegs */
873 offsetof(AVRRegisterClassStorage, SuperClasses[98]) - 26 * sizeof(MCRegisterClass),
874 .SuperClassesSize: 6
875 },
876 {
877 offsetof(AVRRegisterClassStorage, Regs[332]) - 27 * sizeof(MCRegisterClass),
878 offsetof(AVRRegisterClassStorage, BitSets[55]) - 27 * sizeof(MCRegisterClass),
879 .NameIdx: 201,
880 .RegSizeInBits: 16,
881 .RegsSize: 2,
882 .RegSetBegin: 59, /* MinRegVal */
883 .RegSetSize: 2, /* RegSetSize */
884 .ID: AVR::DREGSNOZ_and_PTRREGSRegClassID,
885 .CopyCost: 1, /* CopyCost */
886 .Allocatable: true, /* Allocatable */
887 .BaseClass: false,
888 offsetof(AVRRegisterClassStorage, SubClassMasks[78]) - 27 * sizeof(MCRegisterClass),
889 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 27 * sizeof(MCRegisterClass),
890 .LaneMask: LaneBitmask(0x0000000000000003),
891 .AllocationPriority: 0,
892 .GlobalPriority: false,
893 .TSFlags: 0x00, /* TSFlags */
894 .SpillStackID: 0, /* SpillStackID */
895 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
896 .CoveredBySubRegs: true, /* CoveredBySubRegs */
897 offsetof(AVRRegisterClassStorage, SuperClasses[104]) - 27 * sizeof(MCRegisterClass),
898 .SuperClassesSize: 13
899 },
900 {
901 offsetof(AVRRegisterClassStorage, Regs[334]) - 28 * sizeof(MCRegisterClass),
902 offsetof(AVRRegisterClassStorage, BitSets[56]) - 28 * sizeof(MCRegisterClass),
903 .NameIdx: 189,
904 .RegSizeInBits: 16,
905 .RegsSize: 2,
906 .RegSetBegin: 60, /* MinRegVal */
907 .RegSetSize: 2, /* RegSetSize */
908 .ID: AVR::PTRDISPREGSRegClassID,
909 .CopyCost: 1, /* CopyCost */
910 .Allocatable: true, /* Allocatable */
911 .BaseClass: false,
912 offsetof(AVRRegisterClassStorage, SubClassMasks[80]) - 28 * sizeof(MCRegisterClass),
913 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 28 * sizeof(MCRegisterClass),
914 .LaneMask: LaneBitmask(0x0000000000000003),
915 .AllocationPriority: 0,
916 .GlobalPriority: false,
917 .TSFlags: 0x00, /* TSFlags */
918 .SpillStackID: 0, /* SpillStackID */
919 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
920 .CoveredBySubRegs: true, /* CoveredBySubRegs */
921 offsetof(AVRRegisterClassStorage, SuperClasses[117]) - 28 * sizeof(MCRegisterClass),
922 .SuperClassesSize: 7
923 },
924 {
925 offsetof(AVRRegisterClassStorage, Regs[336]) - 29 * sizeof(MCRegisterClass),
926 offsetof(AVRRegisterClassStorage, BitSets[57]) - 29 * sizeof(MCRegisterClass),
927 .NameIdx: 176,
928 .RegSizeInBits: 16,
929 .RegsSize: 1,
930 .RegSetBegin: 60, /* MinRegVal */
931 .RegSetSize: 1, /* RegSetSize */
932 .ID: AVR::DREGSNOZ_and_PTRDISPREGSRegClassID,
933 .CopyCost: 1, /* CopyCost */
934 .Allocatable: true, /* Allocatable */
935 .BaseClass: false,
936 offsetof(AVRRegisterClassStorage, SubClassMasks[82]) - 29 * sizeof(MCRegisterClass),
937 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 29 * sizeof(MCRegisterClass),
938 .LaneMask: LaneBitmask(0x0000000000000003),
939 .AllocationPriority: 0,
940 .GlobalPriority: false,
941 .TSFlags: 0x00, /* TSFlags */
942 .SpillStackID: 0, /* SpillStackID */
943 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
944 .CoveredBySubRegs: true, /* CoveredBySubRegs */
945 offsetof(AVRRegisterClassStorage, SuperClasses[124]) - 29 * sizeof(MCRegisterClass),
946 .SuperClassesSize: 15
947 },
948 {
949 offsetof(AVRRegisterClassStorage, Regs[337]) - 30 * sizeof(MCRegisterClass),
950 offsetof(AVRRegisterClassStorage, BitSets[58]) - 30 * sizeof(MCRegisterClass),
951 .NameIdx: 397,
952 .RegSizeInBits: 16,
953 .RegsSize: 1,
954 .RegSetBegin: 48, /* MinRegVal */
955 .RegSetSize: 1, /* RegSetSize */
956 .ID: AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID,
957 .CopyCost: 1, /* CopyCost */
958 .Allocatable: true, /* Allocatable */
959 .BaseClass: false,
960 offsetof(AVRRegisterClassStorage, SubClassMasks[84]) - 30 * sizeof(MCRegisterClass),
961 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 30 * sizeof(MCRegisterClass),
962 .LaneMask: LaneBitmask(0x0000000000000003),
963 .AllocationPriority: 0,
964 .GlobalPriority: false,
965 .TSFlags: 0x00, /* TSFlags */
966 .SpillStackID: 0, /* SpillStackID */
967 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
968 .CoveredBySubRegs: true, /* CoveredBySubRegs */
969 offsetof(AVRRegisterClassStorage, SuperClasses[139]) - 30 * sizeof(MCRegisterClass),
970 .SuperClassesSize: 6
971 },
972 {
973 offsetof(AVRRegisterClassStorage, Regs[338]) - 31 * sizeof(MCRegisterClass),
974 offsetof(AVRRegisterClassStorage, BitSets[59]) - 31 * sizeof(MCRegisterClass),
975 .NameIdx: 158,
976 .RegSizeInBits: 16,
977 .RegsSize: 1,
978 .RegSetBegin: 1, /* MinRegVal */
979 .RegSetSize: 1, /* RegSetSize */
980 .ID: AVR::GPRSPRegClassID,
981 .CopyCost: 1, /* CopyCost */
982 .Allocatable: true, /* Allocatable */
983 .BaseClass: false,
984 offsetof(AVRRegisterClassStorage, SubClassMasks[86]) - 31 * sizeof(MCRegisterClass),
985 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 31 * sizeof(MCRegisterClass),
986 .LaneMask: LaneBitmask(0x0000000000000003),
987 .AllocationPriority: 0,
988 .GlobalPriority: false,
989 .TSFlags: 0x00, /* TSFlags */
990 .SpillStackID: 0, /* SpillStackID */
991 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
992 .CoveredBySubRegs: true, /* CoveredBySubRegs */
993 offsetof(AVRRegisterClassStorage, SuperClasses[145]) - 31 * sizeof(MCRegisterClass),
994 .SuperClassesSize: 0
995 },
996 {
997 offsetof(AVRRegisterClassStorage, Regs[339]) - 32 * sizeof(MCRegisterClass),
998 offsetof(AVRRegisterClassStorage, BitSets[60]) - 32 * sizeof(MCRegisterClass),
999 .NameIdx: 153,
1000 .RegSizeInBits: 16,
1001 .RegsSize: 1,
1002 .RegSetBegin: 61, /* MinRegVal */
1003 .RegSetSize: 1, /* RegSetSize */
1004 .ID: AVR::ZREGRegClassID,
1005 .CopyCost: 1, /* CopyCost */
1006 .Allocatable: true, /* Allocatable */
1007 .BaseClass: false,
1008 offsetof(AVRRegisterClassStorage, SubClassMasks[88]) - 32 * sizeof(MCRegisterClass),
1009 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 32 * sizeof(MCRegisterClass),
1010 .LaneMask: LaneBitmask(0x0000000000000003),
1011 .AllocationPriority: 0,
1012 .GlobalPriority: false,
1013 .TSFlags: 0x00, /* TSFlags */
1014 .SpillStackID: 0, /* SpillStackID */
1015 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1016 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1017 offsetof(AVRRegisterClassStorage, SuperClasses[145]) - 32 * sizeof(MCRegisterClass),
1018 .SuperClassesSize: 8
1019 },
1020 },
1021 .Regs: {
1022 /* 0 */ AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
1023 /* 32 */ AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
1024 /* 62 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
1025 /* 78 */ AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
1026 /* 94 */ AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
1027 /* 108 */ AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16,
1028 /* 116 */ AVR::SREG,
1029 /* 117 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
1030 /* 142 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
1031 /* 166 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
1032 /* 182 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
1033 /* 197 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
1034 /* 211 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
1035 /* 224 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
1036 /* 237 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
1037 /* 249 */ AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
1038 /* 261 */ AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R14R13, AVR::R12R11, AVR::R10R9,
1039 /* 272 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16,
1040 /* 280 */ AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
1041 /* 288 */ AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
1042 /* 296 */ AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
1043 /* 304 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16,
1044 /* 311 */ AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17,
1045 /* 318 */ AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16,
1046 /* 322 */ AVR::R25R24, AVR::R31R30, AVR::R27R26, AVR::R29R28,
1047 /* 326 */ AVR::R25R24, AVR::R27R26, AVR::R29R28,
1048 /* 329 */ AVR::R27R26, AVR::R29R28, AVR::R31R30,
1049 /* 332 */ AVR::R27R26, AVR::R29R28,
1050 /* 334 */ AVR::R31R30, AVR::R29R28,
1051 /* 336 */ AVR::R29R28,
1052 /* 337 */ AVR::R16R15,
1053 /* 338 */ AVR::SP,
1054 /* 339 */ AVR::R31R30,
1055 },
1056 .BitSets: {
1057 /* 0 */ 0xff, 0xff, 0xff, 0xff,
1058 /* 4 */ 0xff, 0xff, 0xff, 0x3f,
1059 /* 8 */ 0xff, 0xff,
1060 /* 10 */ 0xff, 0xff,
1061 /* 12 */ 0xff, 0x3f,
1062 /* 14 */ 0xff,
1063 /* 15 */ 0x01,
1064 /* 16 */ 0xff, 0xff, 0xff, 0x01,
1065 /* 20 */ 0xff, 0xff, 0xff,
1066 /* 23 */ 0x5f, 0x55, 0xd5, 0x01,
1067 /* 27 */ 0x5f, 0x55, 0xd5,
1068 /* 30 */ 0xff, 0x3f,
1069 /* 32 */ 0xff, 0x1f,
1070 /* 34 */ 0xff, 0x1f,
1071 /* 36 */ 0xff, 0x0f,
1072 /* 38 */ 0xff, 0x0f,
1073 /* 40 */ 0xff, 0x07,
1074 /* 42 */ 0x55, 0x1d,
1075 /* 44 */ 0xff,
1076 /* 45 */ 0xff,
1077 /* 46 */ 0x5f, 0x05,
1078 /* 48 */ 0x55, 0x0d,
1079 /* 50 */ 0x7f,
1080 /* 51 */ 0x55,
1081 /* 52 */ 0x1d,
1082 /* 53 */ 0x0d,
1083 /* 54 */ 0x07,
1084 /* 55 */ 0x03,
1085 /* 56 */ 0x03,
1086 /* 57 */ 0x01,
1087 /* 58 */ 0x01,
1088 /* 59 */ 0x01,
1089 /* 60 */ 0x01,
1090 },
1091 .SubClassMasks: {
1092 // 0 GPR8
1093 0x0000003f, 0x00000000,
1094 0x7fffff80, 0x00000001, // sub_hi
1095 0x7fffff80, 0x00000001, // sub_lo
1096 // 6 GPR8NOZ
1097 0x00000036, 0x00000000,
1098 0x6afdd500, 0x00000000, // sub_hi
1099 0x6afdd500, 0x00000000, // sub_lo
1100 // 12 GPR8lo
1101 0x00000004, 0x00000000,
1102 0x00110000, 0x00000000, // sub_hi
1103 0x40118000, 0x00000000, // sub_lo
1104 // 18 LD8
1105 0x00000038, 0x00000000,
1106 0x7fee7800, 0x00000001, // sub_hi
1107 0x3fea6000, 0x00000001, // sub_lo
1108 // 24 GPR8NOZ_and_LD8
1109 0x00000030, 0x00000000,
1110 0x6aec5000, 0x00000000, // sub_hi
1111 0x2ae84000, 0x00000000, // sub_lo
1112 // 30 LD8lo
1113 0x00000020, 0x00000000,
1114 0x40c40000, 0x00000000, // sub_hi
1115 0x00c80000, 0x00000000, // sub_lo
1116 // 36 CCR
1117 0x00000040, 0x00000000,
1118 // 38 DREGS
1119 0x7fffff80, 0x00000001,
1120 // 40 DREGSNOZ
1121 0x6afdd500, 0x00000000,
1122 // 42 DREGSMOVW
1123 0x3fb20600, 0x00000001,
1124 // 44 DREGSMOVW_and_DREGSNOZ
1125 0x2ab00400, 0x00000000,
1126 // 46 DREGS_with_sub_hi_in_LD8
1127 0x7fee7800, 0x00000001,
1128 // 48 DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1129 0x6aec5000, 0x00000000,
1130 // 50 DREGS_with_sub_lo_in_LD8
1131 0x3fea6000, 0x00000001,
1132 // 52 DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1133 0x2ae84000, 0x00000000,
1134 // 54 DREGS_with_sub_lo_in_GPR8lo
1135 0x40118000, 0x00000000,
1136 // 56 DREGS_with_sub_hi_in_GPR8lo
1137 0x00110000, 0x00000000,
1138 // 58 DLDREGS
1139 0x3fa20000, 0x00000001,
1140 // 60 DREGS_with_sub_hi_in_LD8lo
1141 0x40c40000, 0x00000000,
1142 // 62 DREGS_with_sub_lo_in_LD8lo
1143 0x00c80000, 0x00000000,
1144 // 64 DREGSlo
1145 0x00100000, 0x00000000,
1146 // 66 DLDREGS_and_DREGSNOZ
1147 0x2aa00000, 0x00000000,
1148 // 68 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1149 0x00c00000, 0x00000000,
1150 // 70 DREGSLD8lo
1151 0x00800000, 0x00000000,
1152 // 72 IWREGS
1153 0x3f000000, 0x00000001,
1154 // 74 DREGSNOZ_and_IWREGS
1155 0x2a000000, 0x00000000,
1156 // 76 PTRREGS
1157 0x3c000000, 0x00000001,
1158 // 78 DREGSNOZ_and_PTRREGS
1159 0x28000000, 0x00000000,
1160 // 80 PTRDISPREGS
1161 0x30000000, 0x00000001,
1162 // 82 DREGSNOZ_and_PTRDISPREGS
1163 0x20000000, 0x00000000,
1164 // 84 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1165 0x40000000, 0x00000000,
1166 // 86 GPRSP
1167 0x80000000, 0x00000000,
1168 // 88 ZREG
1169 0x00000000, 0x00000001,
1170 },
1171 .SuperRegIdxSeqs: {
1172 /* 0 */ 1, 2, 0,
1173 },
1174 .SuperClasses: {
1175 /* 0 GPR8 */
1176 /* 0 GPR8NOZ */ AVR::GPR8RegClassID,
1177 /* 1 GPR8lo */ AVR::GPR8RegClassID, AVR::GPR8NOZRegClassID,
1178 /* 3 LD8 */ AVR::GPR8RegClassID,
1179 /* 4 GPR8NOZ_and_LD8 */ AVR::GPR8RegClassID, AVR::GPR8NOZRegClassID, AVR::LD8RegClassID,
1180 /* 7 LD8lo */ AVR::GPR8RegClassID, AVR::GPR8NOZRegClassID, AVR::LD8RegClassID, AVR::GPR8NOZ_and_LD8RegClassID,
1181 /* 11 CCR */
1182 /* 11 DREGS */
1183 /* 11 DREGSNOZ */ AVR::DREGSRegClassID,
1184 /* 12 DREGSMOVW */ AVR::DREGSRegClassID,
1185 /* 13 DREGSMOVW_and_DREGSNOZ */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID,
1186 /* 16 DREGS_with_sub_hi_in_LD8 */ AVR::DREGSRegClassID,
1187 /* 17 DREGSNOZ_and_DREGS_with_sub_hi_in_LD8 */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1188 /* 20 DREGS_with_sub_lo_in_LD8 */ AVR::DREGSRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1189 /* 22 DREGSNOZ_and_DREGS_with_sub_lo_in_LD8 */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1190 /* 27 DREGS_with_sub_lo_in_GPR8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID,
1191 /* 29 DREGS_with_sub_hi_in_GPR8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
1192 /* 32 DLDREGS */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1193 /* 36 DREGS_with_sub_hi_in_LD8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
1194 /* 40 DREGS_with_sub_lo_in_LD8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
1195 /* 46 DREGSlo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, AVR::DREGS_with_sub_hi_in_GPR8loRegClassID,
1196 /* 52 DLDREGS_and_DREGSNOZ */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID,
1197 /* 61 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGS_with_sub_hi_in_LD8loRegClassID, AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
1198 /* 69 DREGSLD8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::DREGS_with_sub_hi_in_LD8loRegClassID, AVR::DREGS_with_sub_lo_in_LD8loRegClassID, AVR::DLDREGS_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID,
1199 /* 82 IWREGS */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID,
1200 /* 87 DREGSNOZ_and_IWREGS */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::DLDREGS_and_DREGSNOZRegClassID, AVR::IWREGSRegClassID,
1201 /* 98 PTRREGS */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::IWREGSRegClassID,
1202 /* 104 DREGSNOZ_and_PTRREGS */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::DLDREGS_and_DREGSNOZRegClassID, AVR::IWREGSRegClassID, AVR::DREGSNOZ_and_IWREGSRegClassID, AVR::PTRREGSRegClassID,
1203 /* 117 PTRDISPREGS */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::IWREGSRegClassID, AVR::PTRREGSRegClassID,
1204 /* 124 DREGSNOZ_and_PTRDISPREGS */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::DLDREGS_and_DREGSNOZRegClassID, AVR::IWREGSRegClassID, AVR::DREGSNOZ_and_IWREGSRegClassID, AVR::PTRREGSRegClassID, AVR::DREGSNOZ_and_PTRREGSRegClassID, AVR::PTRDISPREGSRegClassID,
1205 /* 139 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
1206 /* 145 GPRSP */
1207 /* 145 ZREG */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::IWREGSRegClassID, AVR::PTRREGSRegClassID, AVR::PTRDISPREGSRegClassID,
1208 }
1209};
1210
1211const MCRegisterClass &getAVRMCRegisterClass(unsigned RC) {
1212 return AVRMCRegisterClassStorage.Classes[RC];
1213}
1214
1215// AVR Dwarf<->LLVM register mappings.
1216extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
1217 { .FromReg: 0U, .ToReg: AVR::R1R0 },
1218 { .FromReg: 1U, .ToReg: AVR::R1 },
1219 { .FromReg: 2U, .ToReg: AVR::R3R2 },
1220 { .FromReg: 3U, .ToReg: AVR::R3 },
1221 { .FromReg: 4U, .ToReg: AVR::R5R4 },
1222 { .FromReg: 5U, .ToReg: AVR::R5 },
1223 { .FromReg: 6U, .ToReg: AVR::R7R6 },
1224 { .FromReg: 7U, .ToReg: AVR::R7 },
1225 { .FromReg: 8U, .ToReg: AVR::R9R8 },
1226 { .FromReg: 9U, .ToReg: AVR::R10R9 },
1227 { .FromReg: 10U, .ToReg: AVR::R11R10 },
1228 { .FromReg: 11U, .ToReg: AVR::R12R11 },
1229 { .FromReg: 12U, .ToReg: AVR::R13R12 },
1230 { .FromReg: 13U, .ToReg: AVR::R14R13 },
1231 { .FromReg: 14U, .ToReg: AVR::R15R14 },
1232 { .FromReg: 15U, .ToReg: AVR::R16R15 },
1233 { .FromReg: 16U, .ToReg: AVR::R17R16 },
1234 { .FromReg: 17U, .ToReg: AVR::R18R17 },
1235 { .FromReg: 18U, .ToReg: AVR::R19R18 },
1236 { .FromReg: 19U, .ToReg: AVR::R20R19 },
1237 { .FromReg: 20U, .ToReg: AVR::R21R20 },
1238 { .FromReg: 21U, .ToReg: AVR::R22R21 },
1239 { .FromReg: 22U, .ToReg: AVR::R23R22 },
1240 { .FromReg: 23U, .ToReg: AVR::R24R23 },
1241 { .FromReg: 24U, .ToReg: AVR::R25R24 },
1242 { .FromReg: 25U, .ToReg: AVR::R26R25 },
1243 { .FromReg: 26U, .ToReg: AVR::R27R26 },
1244 { .FromReg: 27U, .ToReg: AVR::R27 },
1245 { .FromReg: 28U, .ToReg: AVR::R29R28 },
1246 { .FromReg: 29U, .ToReg: AVR::R29 },
1247 { .FromReg: 30U, .ToReg: AVR::R31R30 },
1248 { .FromReg: 31U, .ToReg: AVR::R31 },
1249 { .FromReg: 32U, .ToReg: AVR::SPL },
1250 { .FromReg: 33U, .ToReg: AVR::SPH },
1251 { .FromReg: 88U, .ToReg: AVR::SREG },
1252};
1253extern const unsigned AVRDwarfFlavour0Dwarf2LSize = std::size(AVRDwarfFlavour0Dwarf2L);
1254
1255extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
1256 { .FromReg: 0U, .ToReg: AVR::R1R0 },
1257 { .FromReg: 1U, .ToReg: AVR::R1 },
1258 { .FromReg: 2U, .ToReg: AVR::R3R2 },
1259 { .FromReg: 3U, .ToReg: AVR::R3 },
1260 { .FromReg: 4U, .ToReg: AVR::R5R4 },
1261 { .FromReg: 5U, .ToReg: AVR::R5 },
1262 { .FromReg: 6U, .ToReg: AVR::R7R6 },
1263 { .FromReg: 7U, .ToReg: AVR::R7 },
1264 { .FromReg: 8U, .ToReg: AVR::R9R8 },
1265 { .FromReg: 9U, .ToReg: AVR::R10R9 },
1266 { .FromReg: 10U, .ToReg: AVR::R11R10 },
1267 { .FromReg: 11U, .ToReg: AVR::R12R11 },
1268 { .FromReg: 12U, .ToReg: AVR::R13R12 },
1269 { .FromReg: 13U, .ToReg: AVR::R14R13 },
1270 { .FromReg: 14U, .ToReg: AVR::R15R14 },
1271 { .FromReg: 15U, .ToReg: AVR::R16R15 },
1272 { .FromReg: 16U, .ToReg: AVR::R17R16 },
1273 { .FromReg: 17U, .ToReg: AVR::R18R17 },
1274 { .FromReg: 18U, .ToReg: AVR::R19R18 },
1275 { .FromReg: 19U, .ToReg: AVR::R20R19 },
1276 { .FromReg: 20U, .ToReg: AVR::R21R20 },
1277 { .FromReg: 21U, .ToReg: AVR::R22R21 },
1278 { .FromReg: 22U, .ToReg: AVR::R23R22 },
1279 { .FromReg: 23U, .ToReg: AVR::R24R23 },
1280 { .FromReg: 24U, .ToReg: AVR::R25R24 },
1281 { .FromReg: 25U, .ToReg: AVR::R26R25 },
1282 { .FromReg: 26U, .ToReg: AVR::R27R26 },
1283 { .FromReg: 27U, .ToReg: AVR::R27 },
1284 { .FromReg: 28U, .ToReg: AVR::R29R28 },
1285 { .FromReg: 29U, .ToReg: AVR::R29 },
1286 { .FromReg: 30U, .ToReg: AVR::R31R30 },
1287 { .FromReg: 31U, .ToReg: AVR::R31 },
1288 { .FromReg: 32U, .ToReg: AVR::SPL },
1289 { .FromReg: 33U, .ToReg: AVR::SPH },
1290 { .FromReg: 88U, .ToReg: AVR::SREG },
1291};
1292extern const unsigned AVREHFlavour0Dwarf2LSize = std::size(AVREHFlavour0Dwarf2L);
1293
1294extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
1295 { .FromReg: AVR::SP, .ToReg: 32U },
1296 { .FromReg: AVR::SPH, .ToReg: 33U },
1297 { .FromReg: AVR::SPL, .ToReg: 32U },
1298 { .FromReg: AVR::SREG, .ToReg: 88U },
1299 { .FromReg: AVR::R0, .ToReg: 0U },
1300 { .FromReg: AVR::R1, .ToReg: 1U },
1301 { .FromReg: AVR::R2, .ToReg: 2U },
1302 { .FromReg: AVR::R3, .ToReg: 3U },
1303 { .FromReg: AVR::R4, .ToReg: 4U },
1304 { .FromReg: AVR::R5, .ToReg: 5U },
1305 { .FromReg: AVR::R6, .ToReg: 6U },
1306 { .FromReg: AVR::R7, .ToReg: 7U },
1307 { .FromReg: AVR::R8, .ToReg: 8U },
1308 { .FromReg: AVR::R9, .ToReg: 9U },
1309 { .FromReg: AVR::R10, .ToReg: 10U },
1310 { .FromReg: AVR::R11, .ToReg: 11U },
1311 { .FromReg: AVR::R12, .ToReg: 12U },
1312 { .FromReg: AVR::R13, .ToReg: 13U },
1313 { .FromReg: AVR::R14, .ToReg: 14U },
1314 { .FromReg: AVR::R15, .ToReg: 15U },
1315 { .FromReg: AVR::R16, .ToReg: 16U },
1316 { .FromReg: AVR::R17, .ToReg: 17U },
1317 { .FromReg: AVR::R18, .ToReg: 18U },
1318 { .FromReg: AVR::R19, .ToReg: 19U },
1319 { .FromReg: AVR::R20, .ToReg: 20U },
1320 { .FromReg: AVR::R21, .ToReg: 21U },
1321 { .FromReg: AVR::R22, .ToReg: 22U },
1322 { .FromReg: AVR::R23, .ToReg: 23U },
1323 { .FromReg: AVR::R24, .ToReg: 24U },
1324 { .FromReg: AVR::R25, .ToReg: 25U },
1325 { .FromReg: AVR::R26, .ToReg: 26U },
1326 { .FromReg: AVR::R27, .ToReg: 27U },
1327 { .FromReg: AVR::R28, .ToReg: 28U },
1328 { .FromReg: AVR::R29, .ToReg: 29U },
1329 { .FromReg: AVR::R30, .ToReg: 30U },
1330 { .FromReg: AVR::R31, .ToReg: 31U },
1331 { .FromReg: AVR::R1R0, .ToReg: 0U },
1332 { .FromReg: AVR::R3R2, .ToReg: 2U },
1333 { .FromReg: AVR::R5R4, .ToReg: 4U },
1334 { .FromReg: AVR::R7R6, .ToReg: 6U },
1335 { .FromReg: AVR::R9R8, .ToReg: 8U },
1336 { .FromReg: AVR::R10R9, .ToReg: 9U },
1337 { .FromReg: AVR::R11R10, .ToReg: 10U },
1338 { .FromReg: AVR::R12R11, .ToReg: 11U },
1339 { .FromReg: AVR::R13R12, .ToReg: 12U },
1340 { .FromReg: AVR::R14R13, .ToReg: 13U },
1341 { .FromReg: AVR::R15R14, .ToReg: 14U },
1342 { .FromReg: AVR::R16R15, .ToReg: 15U },
1343 { .FromReg: AVR::R17R16, .ToReg: 16U },
1344 { .FromReg: AVR::R18R17, .ToReg: 17U },
1345 { .FromReg: AVR::R19R18, .ToReg: 18U },
1346 { .FromReg: AVR::R20R19, .ToReg: 19U },
1347 { .FromReg: AVR::R21R20, .ToReg: 20U },
1348 { .FromReg: AVR::R22R21, .ToReg: 21U },
1349 { .FromReg: AVR::R23R22, .ToReg: 22U },
1350 { .FromReg: AVR::R24R23, .ToReg: 23U },
1351 { .FromReg: AVR::R25R24, .ToReg: 24U },
1352 { .FromReg: AVR::R26R25, .ToReg: 25U },
1353 { .FromReg: AVR::R27R26, .ToReg: 26U },
1354 { .FromReg: AVR::R29R28, .ToReg: 28U },
1355 { .FromReg: AVR::R31R30, .ToReg: 30U },
1356};
1357extern const unsigned AVRDwarfFlavour0L2DwarfSize = std::size(AVRDwarfFlavour0L2Dwarf);
1358
1359extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
1360 { .FromReg: AVR::SP, .ToReg: 32U },
1361 { .FromReg: AVR::SPH, .ToReg: 33U },
1362 { .FromReg: AVR::SPL, .ToReg: 32U },
1363 { .FromReg: AVR::SREG, .ToReg: 88U },
1364 { .FromReg: AVR::R0, .ToReg: 0U },
1365 { .FromReg: AVR::R1, .ToReg: 1U },
1366 { .FromReg: AVR::R2, .ToReg: 2U },
1367 { .FromReg: AVR::R3, .ToReg: 3U },
1368 { .FromReg: AVR::R4, .ToReg: 4U },
1369 { .FromReg: AVR::R5, .ToReg: 5U },
1370 { .FromReg: AVR::R6, .ToReg: 6U },
1371 { .FromReg: AVR::R7, .ToReg: 7U },
1372 { .FromReg: AVR::R8, .ToReg: 8U },
1373 { .FromReg: AVR::R9, .ToReg: 9U },
1374 { .FromReg: AVR::R10, .ToReg: 10U },
1375 { .FromReg: AVR::R11, .ToReg: 11U },
1376 { .FromReg: AVR::R12, .ToReg: 12U },
1377 { .FromReg: AVR::R13, .ToReg: 13U },
1378 { .FromReg: AVR::R14, .ToReg: 14U },
1379 { .FromReg: AVR::R15, .ToReg: 15U },
1380 { .FromReg: AVR::R16, .ToReg: 16U },
1381 { .FromReg: AVR::R17, .ToReg: 17U },
1382 { .FromReg: AVR::R18, .ToReg: 18U },
1383 { .FromReg: AVR::R19, .ToReg: 19U },
1384 { .FromReg: AVR::R20, .ToReg: 20U },
1385 { .FromReg: AVR::R21, .ToReg: 21U },
1386 { .FromReg: AVR::R22, .ToReg: 22U },
1387 { .FromReg: AVR::R23, .ToReg: 23U },
1388 { .FromReg: AVR::R24, .ToReg: 24U },
1389 { .FromReg: AVR::R25, .ToReg: 25U },
1390 { .FromReg: AVR::R26, .ToReg: 26U },
1391 { .FromReg: AVR::R27, .ToReg: 27U },
1392 { .FromReg: AVR::R28, .ToReg: 28U },
1393 { .FromReg: AVR::R29, .ToReg: 29U },
1394 { .FromReg: AVR::R30, .ToReg: 30U },
1395 { .FromReg: AVR::R31, .ToReg: 31U },
1396 { .FromReg: AVR::R1R0, .ToReg: 0U },
1397 { .FromReg: AVR::R3R2, .ToReg: 2U },
1398 { .FromReg: AVR::R5R4, .ToReg: 4U },
1399 { .FromReg: AVR::R7R6, .ToReg: 6U },
1400 { .FromReg: AVR::R9R8, .ToReg: 8U },
1401 { .FromReg: AVR::R10R9, .ToReg: 9U },
1402 { .FromReg: AVR::R11R10, .ToReg: 10U },
1403 { .FromReg: AVR::R12R11, .ToReg: 11U },
1404 { .FromReg: AVR::R13R12, .ToReg: 12U },
1405 { .FromReg: AVR::R14R13, .ToReg: 13U },
1406 { .FromReg: AVR::R15R14, .ToReg: 14U },
1407 { .FromReg: AVR::R16R15, .ToReg: 15U },
1408 { .FromReg: AVR::R17R16, .ToReg: 16U },
1409 { .FromReg: AVR::R18R17, .ToReg: 17U },
1410 { .FromReg: AVR::R19R18, .ToReg: 18U },
1411 { .FromReg: AVR::R20R19, .ToReg: 19U },
1412 { .FromReg: AVR::R21R20, .ToReg: 20U },
1413 { .FromReg: AVR::R22R21, .ToReg: 21U },
1414 { .FromReg: AVR::R23R22, .ToReg: 22U },
1415 { .FromReg: AVR::R24R23, .ToReg: 23U },
1416 { .FromReg: AVR::R25R24, .ToReg: 24U },
1417 { .FromReg: AVR::R26R25, .ToReg: 25U },
1418 { .FromReg: AVR::R27R26, .ToReg: 26U },
1419 { .FromReg: AVR::R29R28, .ToReg: 28U },
1420 { .FromReg: AVR::R31R30, .ToReg: 30U },
1421};
1422extern const unsigned AVREHFlavour0L2DwarfSize = std::size(AVREHFlavour0L2Dwarf);
1423
1424extern const uint16_t AVRRegEncodingTable[] = {
1425 0,
1426 16,
1427 33,
1428 32,
1429 14,
1430 0,
1431 1,
1432 2,
1433 3,
1434 4,
1435 5,
1436 6,
1437 7,
1438 8,
1439 9,
1440 10,
1441 11,
1442 12,
1443 13,
1444 14,
1445 15,
1446 16,
1447 17,
1448 18,
1449 19,
1450 20,
1451 21,
1452 22,
1453 23,
1454 24,
1455 25,
1456 26,
1457 27,
1458 28,
1459 29,
1460 30,
1461 31,
1462 0,
1463 1,
1464 2,
1465 3,
1466 4,
1467 9,
1468 5,
1469 11,
1470 6,
1471 13,
1472 7,
1473 15,
1474 8,
1475 17,
1476 9,
1477 19,
1478 10,
1479 21,
1480 11,
1481 23,
1482 12,
1483 25,
1484 13,
1485 14,
1486 15,
1487};
1488static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1489 RI->InitMCRegisterInfo(D: AVRRegDesc, NR: 62, RA, PC, C: AVRMCRegisterClassStorage.Classes, NC: 33, RURoots: AVRRegUnitRoots, NRU: 35, DL: AVRRegDiffLists, RUMS: AVRLaneMaskLists, Strings: AVRRegStrings, ClassStrings: AVRRegClassStrings, SubIndices: AVRSubRegIdxLists, NumIndices: 3,
1490RET: AVRRegEncodingTable, RUI: nullptr);
1491
1492 switch (DwarfFlavour) {
1493 default:
1494 llvm_unreachable("Unknown DWARF flavour");
1495 case 0:
1496 RI->mapDwarfRegsToLLVMRegs(Map: AVRDwarfFlavour0Dwarf2L, Size: AVRDwarfFlavour0Dwarf2LSize, isEH: false);
1497 break;
1498 }
1499 switch (EHFlavour) {
1500 default:
1501 llvm_unreachable("Unknown DWARF flavour");
1502 case 0:
1503 RI->mapDwarfRegsToLLVMRegs(Map: AVREHFlavour0Dwarf2L, Size: AVREHFlavour0Dwarf2LSize, isEH: true);
1504 break;
1505 }
1506 switch (DwarfFlavour) {
1507 default:
1508 llvm_unreachable("Unknown DWARF flavour");
1509 case 0:
1510 RI->mapLLVMRegsToDwarfRegs(Map: AVRDwarfFlavour0L2Dwarf, Size: AVRDwarfFlavour0L2DwarfSize, isEH: false);
1511 break;
1512 }
1513 switch (EHFlavour) {
1514 default:
1515 llvm_unreachable("Unknown DWARF flavour");
1516 case 0:
1517 RI->mapLLVMRegsToDwarfRegs(Map: AVREHFlavour0L2Dwarf, Size: AVREHFlavour0L2DwarfSize, isEH: true);
1518 break;
1519 }
1520}
1521
1522
1523} // namespace llvm
1524