1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t AVRRegDiffLists[] = {
12 /* 0 */ -2, 0,
13 /* 2 */ 2, -1, 0,
14 /* 5 */ -32, 1, 0,
15 /* 8 */ -31, 1, 0,
16 /* 11 */ -30, 1, 0,
17 /* 14 */ -29, 1, 0,
18 /* 17 */ -28, 1, 0,
19 /* 20 */ -27, 1, 0,
20 /* 23 */ -26, 1, 0,
21 /* 26 */ 27, 1, 0,
22 /* 29 */ 25, 0,
23 /* 31 */ 26, 0,
24 /* 33 */ 27, 0,
25 /* 35 */ 28, 0,
26 /* 37 */ 29, 0,
27 /* 39 */ 30, 0,
28 /* 41 */ 31, 0,
29 /* 43 */ 32, 0,
30};
31
32extern const LaneBitmask AVRLaneMaskLists[] = {
33 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
34 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
35};
36
37extern const uint16_t AVRSubRegIdxLists[] = {
38 /* 0 */ 2, 1,
39};
40
41
42#ifdef __GNUC__
43#pragma GCC diagnostic push
44#pragma GCC diagnostic ignored "-Woverlength-strings"
45#endif
46extern const char AVRRegStrings[] = {
47 /* 0 */ "R11R10\000"
48 /* 7 */ "R21R20\000"
49 /* 14 */ "R31R30\000"
50 /* 21 */ "R1R0\000"
51 /* 26 */ "R12R11\000"
52 /* 33 */ "R22R21\000"
53 /* 40 */ "R31\000"
54 /* 44 */ "R1\000"
55 /* 47 */ "R13R12\000"
56 /* 54 */ "R23R22\000"
57 /* 61 */ "R3R2\000"
58 /* 66 */ "R14R13\000"
59 /* 73 */ "R24R23\000"
60 /* 80 */ "R3\000"
61 /* 83 */ "R15R14\000"
62 /* 90 */ "R25R24\000"
63 /* 97 */ "R5R4\000"
64 /* 102 */ "R16R15\000"
65 /* 109 */ "R26R25\000"
66 /* 116 */ "R5\000"
67 /* 119 */ "R17R16\000"
68 /* 126 */ "R27R26\000"
69 /* 133 */ "R7R6\000"
70 /* 138 */ "R18R17\000"
71 /* 145 */ "R27\000"
72 /* 149 */ "R7\000"
73 /* 152 */ "R19R18\000"
74 /* 159 */ "R29R28\000"
75 /* 166 */ "R9R8\000"
76 /* 171 */ "R20R19\000"
77 /* 178 */ "R29\000"
78 /* 182 */ "R10R9\000"
79 /* 188 */ "SREG\000"
80 /* 193 */ "SPH\000"
81 /* 197 */ "SPL\000"
82 /* 201 */ "SP\000"
83};
84#ifdef __GNUC__
85#pragma GCC diagnostic pop
86#endif
87
88extern const MCRegisterDesc AVRRegDesc[] = { // Descriptors
89 { .Name: 6, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
90 { .Name: 201, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24576, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
91 { .Name: 193, .SubRegs: 1, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 4097, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
92 { .Name: 197, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 2, .RegUnits: 4096, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
93 { .Name: 188, .SubRegs: 1, .SuperRegs: 1, .SubRegIndices: 2, .RegUnits: 4098, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
94 { .Name: 23, .SubRegs: 1, .SuperRegs: 43, .SubRegIndices: 2, .RegUnits: 4099, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
95 { .Name: 44, .SubRegs: 1, .SuperRegs: 41, .SubRegIndices: 2, .RegUnits: 4100, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
96 { .Name: 63, .SubRegs: 1, .SuperRegs: 41, .SubRegIndices: 2, .RegUnits: 4101, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
97 { .Name: 80, .SubRegs: 1, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 4102, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
98 { .Name: 99, .SubRegs: 1, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 4103, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
99 { .Name: 116, .SubRegs: 1, .SuperRegs: 37, .SubRegIndices: 2, .RegUnits: 4104, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
100 { .Name: 135, .SubRegs: 1, .SuperRegs: 37, .SubRegIndices: 2, .RegUnits: 4105, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
101 { .Name: 149, .SubRegs: 1, .SuperRegs: 35, .SubRegIndices: 2, .RegUnits: 4106, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
102 { .Name: 168, .SubRegs: 1, .SuperRegs: 35, .SubRegIndices: 2, .RegUnits: 4107, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
103 { .Name: 185, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4108, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
104 { .Name: 3, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4109, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
105 { .Name: 29, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4110, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
106 { .Name: 50, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4111, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
107 { .Name: 69, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4112, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
108 { .Name: 86, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4113, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
109 { .Name: 105, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4114, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
110 { .Name: 122, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4115, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
111 { .Name: 141, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4116, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
112 { .Name: 155, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4117, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
113 { .Name: 174, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4118, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
114 { .Name: 10, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4119, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
115 { .Name: 36, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4120, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
116 { .Name: 57, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4121, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
117 { .Name: 76, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4122, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
118 { .Name: 93, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4123, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
119 { .Name: 112, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4124, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
120 { .Name: 129, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4125, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
121 { .Name: 145, .SubRegs: 1, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 4126, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
122 { .Name: 162, .SubRegs: 1, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 4127, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
123 { .Name: 178, .SubRegs: 1, .SuperRegs: 31, .SubRegIndices: 2, .RegUnits: 4128, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
124 { .Name: 17, .SubRegs: 1, .SuperRegs: 31, .SubRegIndices: 2, .RegUnits: 4129, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
125 { .Name: 40, .SubRegs: 1, .SuperRegs: 29, .SubRegIndices: 2, .RegUnits: 4130, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
126 { .Name: 21, .SubRegs: 5, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24579, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
127 { .Name: 61, .SubRegs: 8, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24581, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
128 { .Name: 97, .SubRegs: 11, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24583, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
129 { .Name: 133, .SubRegs: 14, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24585, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
130 { .Name: 166, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24587, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
131 { .Name: 182, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24588, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
132 { .Name: 0, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24589, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
133 { .Name: 26, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24590, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
134 { .Name: 47, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24591, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
135 { .Name: 66, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24592, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
136 { .Name: 83, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24593, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
137 { .Name: 102, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24594, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
138 { .Name: 119, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24595, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
139 { .Name: 138, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24596, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
140 { .Name: 152, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24597, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
141 { .Name: 171, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24598, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
142 { .Name: 7, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24599, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
143 { .Name: 33, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24600, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
144 { .Name: 54, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24601, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
145 { .Name: 73, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24602, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
146 { .Name: 90, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24603, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
147 { .Name: 109, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24604, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
148 { .Name: 126, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24605, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
149 { .Name: 159, .SubRegs: 20, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24607, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
150 { .Name: 14, .SubRegs: 23, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24609, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
151};
152
153extern const MCPhysReg AVRRegUnitRoots[][2] = {
154 { AVR::SPL },
155 { AVR::SPH },
156 { AVR::SREG },
157 { AVR::R0 },
158 { AVR::R1 },
159 { AVR::R2 },
160 { AVR::R3 },
161 { AVR::R4 },
162 { AVR::R5 },
163 { AVR::R6 },
164 { AVR::R7 },
165 { AVR::R8 },
166 { AVR::R9 },
167 { AVR::R10 },
168 { AVR::R11 },
169 { AVR::R12 },
170 { AVR::R13 },
171 { AVR::R14 },
172 { AVR::R15 },
173 { AVR::R16 },
174 { AVR::R17 },
175 { AVR::R18 },
176 { AVR::R19 },
177 { AVR::R20 },
178 { AVR::R21 },
179 { AVR::R22 },
180 { AVR::R23 },
181 { AVR::R24 },
182 { AVR::R25 },
183 { AVR::R26 },
184 { AVR::R27 },
185 { AVR::R28 },
186 { AVR::R29 },
187 { AVR::R30 },
188 { AVR::R31 },
189};
190
191// Register classes...
192
193#ifdef __GNUC__
194#pragma GCC diagnostic push
195#pragma GCC diagnostic ignored "-Woverlength-strings"
196#endif
197extern const char AVRRegClassStrings[] = {
198 /* 0 */ "GPR8NOZ_and_LD8\000"
199 /* 16 */ "DREGSNOZ_and_DREGS_with_sub_hi_in_LD8\000"
200 /* 54 */ "DREGSNOZ_and_DREGS_with_sub_lo_in_LD8\000"
201 /* 92 */ "DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8\000"
202 /* 148 */ "GPR8\000"
203 /* 153 */ "ZREG\000"
204 /* 158 */ "GPRSP\000"
205 /* 164 */ "CCR\000"
206 /* 168 */ "DLDREGS\000"
207 /* 176 */ "DREGSNOZ_and_PTRDISPREGS\000"
208 /* 201 */ "DREGSNOZ_and_PTRREGS\000"
209 /* 222 */ "DREGSNOZ_and_IWREGS\000"
210 /* 242 */ "DREGSMOVW\000"
211 /* 252 */ "GPR8NOZ\000"
212 /* 260 */ "DLDREGS_and_DREGSNOZ\000"
213 /* 281 */ "DREGSMOVW_and_DREGSNOZ\000"
214 /* 304 */ "DREGSLD8lo\000"
215 /* 315 */ "DREGS_with_sub_hi_in_LD8lo\000"
216 /* 342 */ "DREGS_with_sub_lo_in_LD8lo\000"
217 /* 369 */ "DREGS_with_sub_hi_in_GPR8lo\000"
218 /* 397 */ "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo\000"
219 /* 454 */ "DREGSlo\000"
220};
221#ifdef __GNUC__
222#pragma GCC diagnostic pop
223#endif
224
225using AVRRegisterClassStorage = MCRegisterClassStorage<33, 340, 220, 90, 3, 153>;
226extern const MCRegisterClassStorage<33, 340, 220, 90, 3, 153> AVRMCRegisterClassStorage = {
227 .Classes: {
228 {
229 offsetof(AVRRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
230 offsetof(AVRRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
231 .NameIdx: 148,
232 .RegSizeInBits: 8,
233 .RegsSize: 32,
234 .RegSetSize: 5,
235 .ID: AVR::GPR8RegClassID,
236 .CopyCost: 1, /* CopyCost */
237 .Allocatable: true, /* Allocatable */
238 .BaseClass: false,
239 offsetof(AVRRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
240 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
241 .LaneMask: LaneBitmask(0x0000000000000001),
242 .AllocationPriority: 0,
243 .GlobalPriority: false,
244 .TSFlags: 0x00, /* TSFlags */
245 .SpillStackID: 0, /* SpillStackID */
246 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
247 .CoveredBySubRegs: false, /* CoveredBySubRegs */
248 offsetof(AVRRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
249 .SuperClassesSize: 0
250 },
251 {
252 offsetof(AVRRegisterClassStorage, Regs[32]) - 1 * sizeof(MCRegisterClass),
253 offsetof(AVRRegisterClassStorage, BitSets[5]) - 1 * sizeof(MCRegisterClass),
254 .NameIdx: 252,
255 .RegSizeInBits: 8,
256 .RegsSize: 30,
257 .RegSetSize: 5,
258 .ID: AVR::GPR8NOZRegClassID,
259 .CopyCost: 1, /* CopyCost */
260 .Allocatable: true, /* Allocatable */
261 .BaseClass: false,
262 offsetof(AVRRegisterClassStorage, SubClassMasks[6]) - 1 * sizeof(MCRegisterClass),
263 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 1 * sizeof(MCRegisterClass),
264 .LaneMask: LaneBitmask(0x0000000000000001),
265 .AllocationPriority: 0,
266 .GlobalPriority: false,
267 .TSFlags: 0x00, /* TSFlags */
268 .SpillStackID: 0, /* SpillStackID */
269 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
270 .CoveredBySubRegs: false, /* CoveredBySubRegs */
271 offsetof(AVRRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
272 .SuperClassesSize: 1
273 },
274 {
275 offsetof(AVRRegisterClassStorage, Regs[62]) - 2 * sizeof(MCRegisterClass),
276 offsetof(AVRRegisterClassStorage, BitSets[10]) - 2 * sizeof(MCRegisterClass),
277 .NameIdx: 390,
278 .RegSizeInBits: 8,
279 .RegsSize: 16,
280 .RegSetSize: 3,
281 .ID: AVR::GPR8loRegClassID,
282 .CopyCost: 1, /* CopyCost */
283 .Allocatable: true, /* Allocatable */
284 .BaseClass: false,
285 offsetof(AVRRegisterClassStorage, SubClassMasks[12]) - 2 * sizeof(MCRegisterClass),
286 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 2 * sizeof(MCRegisterClass),
287 .LaneMask: LaneBitmask(0x0000000000000001),
288 .AllocationPriority: 0,
289 .GlobalPriority: false,
290 .TSFlags: 0x00, /* TSFlags */
291 .SpillStackID: 0, /* SpillStackID */
292 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
293 .CoveredBySubRegs: false, /* CoveredBySubRegs */
294 offsetof(AVRRegisterClassStorage, SuperClasses[1]) - 2 * sizeof(MCRegisterClass),
295 .SuperClassesSize: 2
296 },
297 {
298 offsetof(AVRRegisterClassStorage, Regs[78]) - 3 * sizeof(MCRegisterClass),
299 offsetof(AVRRegisterClassStorage, BitSets[13]) - 3 * sizeof(MCRegisterClass),
300 .NameIdx: 12,
301 .RegSizeInBits: 8,
302 .RegsSize: 16,
303 .RegSetSize: 5,
304 .ID: AVR::LD8RegClassID,
305 .CopyCost: 1, /* CopyCost */
306 .Allocatable: true, /* Allocatable */
307 .BaseClass: false,
308 offsetof(AVRRegisterClassStorage, SubClassMasks[18]) - 3 * sizeof(MCRegisterClass),
309 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 3 * sizeof(MCRegisterClass),
310 .LaneMask: LaneBitmask(0x0000000000000001),
311 .AllocationPriority: 0,
312 .GlobalPriority: false,
313 .TSFlags: 0x00, /* TSFlags */
314 .SpillStackID: 0, /* SpillStackID */
315 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
316 .CoveredBySubRegs: false, /* CoveredBySubRegs */
317 offsetof(AVRRegisterClassStorage, SuperClasses[3]) - 3 * sizeof(MCRegisterClass),
318 .SuperClassesSize: 1
319 },
320 {
321 offsetof(AVRRegisterClassStorage, Regs[94]) - 4 * sizeof(MCRegisterClass),
322 offsetof(AVRRegisterClassStorage, BitSets[18]) - 4 * sizeof(MCRegisterClass),
323 .NameIdx: 0,
324 .RegSizeInBits: 8,
325 .RegsSize: 14,
326 .RegSetSize: 5,
327 .ID: AVR::GPR8NOZ_and_LD8RegClassID,
328 .CopyCost: 1, /* CopyCost */
329 .Allocatable: true, /* Allocatable */
330 .BaseClass: false,
331 offsetof(AVRRegisterClassStorage, SubClassMasks[24]) - 4 * sizeof(MCRegisterClass),
332 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 4 * sizeof(MCRegisterClass),
333 .LaneMask: LaneBitmask(0x0000000000000001),
334 .AllocationPriority: 0,
335 .GlobalPriority: false,
336 .TSFlags: 0x00, /* TSFlags */
337 .SpillStackID: 0, /* SpillStackID */
338 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
339 .CoveredBySubRegs: false, /* CoveredBySubRegs */
340 offsetof(AVRRegisterClassStorage, SuperClasses[4]) - 4 * sizeof(MCRegisterClass),
341 .SuperClassesSize: 3
342 },
343 {
344 offsetof(AVRRegisterClassStorage, Regs[108]) - 5 * sizeof(MCRegisterClass),
345 offsetof(AVRRegisterClassStorage, BitSets[23]) - 5 * sizeof(MCRegisterClass),
346 .NameIdx: 309,
347 .RegSizeInBits: 8,
348 .RegsSize: 8,
349 .RegSetSize: 4,
350 .ID: AVR::LD8loRegClassID,
351 .CopyCost: 1, /* CopyCost */
352 .Allocatable: true, /* Allocatable */
353 .BaseClass: false,
354 offsetof(AVRRegisterClassStorage, SubClassMasks[30]) - 5 * sizeof(MCRegisterClass),
355 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass),
356 .LaneMask: LaneBitmask(0x0000000000000001),
357 .AllocationPriority: 0,
358 .GlobalPriority: false,
359 .TSFlags: 0x00, /* TSFlags */
360 .SpillStackID: 0, /* SpillStackID */
361 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
362 .CoveredBySubRegs: false, /* CoveredBySubRegs */
363 offsetof(AVRRegisterClassStorage, SuperClasses[7]) - 5 * sizeof(MCRegisterClass),
364 .SuperClassesSize: 4
365 },
366 {
367 offsetof(AVRRegisterClassStorage, Regs[116]) - 6 * sizeof(MCRegisterClass),
368 offsetof(AVRRegisterClassStorage, BitSets[27]) - 6 * sizeof(MCRegisterClass),
369 .NameIdx: 164,
370 .RegSizeInBits: 8,
371 .RegsSize: 1,
372 .RegSetSize: 1,
373 .ID: AVR::CCRRegClassID,
374 .CopyCost: 255, /* CopyCost */
375 .Allocatable: true, /* Allocatable */
376 .BaseClass: false,
377 offsetof(AVRRegisterClassStorage, SubClassMasks[36]) - 6 * sizeof(MCRegisterClass),
378 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 6 * sizeof(MCRegisterClass),
379 .LaneMask: LaneBitmask(0x0000000000000001),
380 .AllocationPriority: 0,
381 .GlobalPriority: false,
382 .TSFlags: 0x00, /* TSFlags */
383 .SpillStackID: 0, /* SpillStackID */
384 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
385 .CoveredBySubRegs: false, /* CoveredBySubRegs */
386 offsetof(AVRRegisterClassStorage, SuperClasses[11]) - 6 * sizeof(MCRegisterClass),
387 .SuperClassesSize: 0
388 },
389 {
390 offsetof(AVRRegisterClassStorage, Regs[117]) - 7 * sizeof(MCRegisterClass),
391 offsetof(AVRRegisterClassStorage, BitSets[28]) - 7 * sizeof(MCRegisterClass),
392 .NameIdx: 170,
393 .RegSizeInBits: 16,
394 .RegsSize: 25,
395 .RegSetSize: 8,
396 .ID: AVR::DREGSRegClassID,
397 .CopyCost: 1, /* CopyCost */
398 .Allocatable: true, /* Allocatable */
399 .BaseClass: false,
400 offsetof(AVRRegisterClassStorage, SubClassMasks[38]) - 7 * sizeof(MCRegisterClass),
401 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 7 * sizeof(MCRegisterClass),
402 .LaneMask: LaneBitmask(0x0000000000000003),
403 .AllocationPriority: 0,
404 .GlobalPriority: false,
405 .TSFlags: 0x00, /* TSFlags */
406 .SpillStackID: 0, /* SpillStackID */
407 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
408 .CoveredBySubRegs: true, /* CoveredBySubRegs */
409 offsetof(AVRRegisterClassStorage, SuperClasses[11]) - 7 * sizeof(MCRegisterClass),
410 .SuperClassesSize: 0
411 },
412 {
413 offsetof(AVRRegisterClassStorage, Regs[142]) - 8 * sizeof(MCRegisterClass),
414 offsetof(AVRRegisterClassStorage, BitSets[36]) - 8 * sizeof(MCRegisterClass),
415 .NameIdx: 272,
416 .RegSizeInBits: 16,
417 .RegsSize: 24,
418 .RegSetSize: 8,
419 .ID: AVR::DREGSNOZRegClassID,
420 .CopyCost: 1, /* CopyCost */
421 .Allocatable: true, /* Allocatable */
422 .BaseClass: false,
423 offsetof(AVRRegisterClassStorage, SubClassMasks[40]) - 8 * sizeof(MCRegisterClass),
424 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 8 * sizeof(MCRegisterClass),
425 .LaneMask: LaneBitmask(0x0000000000000003),
426 .AllocationPriority: 0,
427 .GlobalPriority: false,
428 .TSFlags: 0x00, /* TSFlags */
429 .SpillStackID: 0, /* SpillStackID */
430 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
431 .CoveredBySubRegs: true, /* CoveredBySubRegs */
432 offsetof(AVRRegisterClassStorage, SuperClasses[11]) - 8 * sizeof(MCRegisterClass),
433 .SuperClassesSize: 1
434 },
435 {
436 offsetof(AVRRegisterClassStorage, Regs[166]) - 9 * sizeof(MCRegisterClass),
437 offsetof(AVRRegisterClassStorage, BitSets[44]) - 9 * sizeof(MCRegisterClass),
438 .NameIdx: 242,
439 .RegSizeInBits: 16,
440 .RegsSize: 16,
441 .RegSetSize: 8,
442 .ID: AVR::DREGSMOVWRegClassID,
443 .CopyCost: 1, /* CopyCost */
444 .Allocatable: true, /* Allocatable */
445 .BaseClass: false,
446 offsetof(AVRRegisterClassStorage, SubClassMasks[42]) - 9 * sizeof(MCRegisterClass),
447 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 9 * sizeof(MCRegisterClass),
448 .LaneMask: LaneBitmask(0x0000000000000003),
449 .AllocationPriority: 0,
450 .GlobalPriority: false,
451 .TSFlags: 0x00, /* TSFlags */
452 .SpillStackID: 0, /* SpillStackID */
453 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
454 .CoveredBySubRegs: true, /* CoveredBySubRegs */
455 offsetof(AVRRegisterClassStorage, SuperClasses[12]) - 9 * sizeof(MCRegisterClass),
456 .SuperClassesSize: 1
457 },
458 {
459 offsetof(AVRRegisterClassStorage, Regs[182]) - 10 * sizeof(MCRegisterClass),
460 offsetof(AVRRegisterClassStorage, BitSets[52]) - 10 * sizeof(MCRegisterClass),
461 .NameIdx: 281,
462 .RegSizeInBits: 16,
463 .RegsSize: 15,
464 .RegSetSize: 8,
465 .ID: AVR::DREGSMOVW_and_DREGSNOZRegClassID,
466 .CopyCost: 1, /* CopyCost */
467 .Allocatable: true, /* Allocatable */
468 .BaseClass: false,
469 offsetof(AVRRegisterClassStorage, SubClassMasks[44]) - 10 * sizeof(MCRegisterClass),
470 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 10 * sizeof(MCRegisterClass),
471 .LaneMask: LaneBitmask(0x0000000000000003),
472 .AllocationPriority: 0,
473 .GlobalPriority: false,
474 .TSFlags: 0x00, /* TSFlags */
475 .SpillStackID: 0, /* SpillStackID */
476 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
477 .CoveredBySubRegs: true, /* CoveredBySubRegs */
478 offsetof(AVRRegisterClassStorage, SuperClasses[13]) - 10 * sizeof(MCRegisterClass),
479 .SuperClassesSize: 3
480 },
481 {
482 offsetof(AVRRegisterClassStorage, Regs[197]) - 11 * sizeof(MCRegisterClass),
483 offsetof(AVRRegisterClassStorage, BitSets[60]) - 11 * sizeof(MCRegisterClass),
484 .NameIdx: 29,
485 .RegSizeInBits: 16,
486 .RegsSize: 14,
487 .RegSetSize: 8,
488 .ID: AVR::DREGS_with_sub_hi_in_LD8RegClassID,
489 .CopyCost: 1, /* CopyCost */
490 .Allocatable: true, /* Allocatable */
491 .BaseClass: false,
492 offsetof(AVRRegisterClassStorage, SubClassMasks[46]) - 11 * sizeof(MCRegisterClass),
493 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 11 * sizeof(MCRegisterClass),
494 .LaneMask: LaneBitmask(0x0000000000000003),
495 .AllocationPriority: 0,
496 .GlobalPriority: false,
497 .TSFlags: 0x00, /* TSFlags */
498 .SpillStackID: 0, /* SpillStackID */
499 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
500 .CoveredBySubRegs: true, /* CoveredBySubRegs */
501 offsetof(AVRRegisterClassStorage, SuperClasses[16]) - 11 * sizeof(MCRegisterClass),
502 .SuperClassesSize: 1
503 },
504 {
505 offsetof(AVRRegisterClassStorage, Regs[211]) - 12 * sizeof(MCRegisterClass),
506 offsetof(AVRRegisterClassStorage, BitSets[68]) - 12 * sizeof(MCRegisterClass),
507 .NameIdx: 16,
508 .RegSizeInBits: 16,
509 .RegsSize: 13,
510 .RegSetSize: 8,
511 .ID: AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
512 .CopyCost: 1, /* CopyCost */
513 .Allocatable: true, /* Allocatable */
514 .BaseClass: false,
515 offsetof(AVRRegisterClassStorage, SubClassMasks[48]) - 12 * sizeof(MCRegisterClass),
516 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 12 * sizeof(MCRegisterClass),
517 .LaneMask: LaneBitmask(0x0000000000000003),
518 .AllocationPriority: 0,
519 .GlobalPriority: false,
520 .TSFlags: 0x00, /* TSFlags */
521 .SpillStackID: 0, /* SpillStackID */
522 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
523 .CoveredBySubRegs: true, /* CoveredBySubRegs */
524 offsetof(AVRRegisterClassStorage, SuperClasses[17]) - 12 * sizeof(MCRegisterClass),
525 .SuperClassesSize: 3
526 },
527 {
528 offsetof(AVRRegisterClassStorage, Regs[224]) - 13 * sizeof(MCRegisterClass),
529 offsetof(AVRRegisterClassStorage, BitSets[76]) - 13 * sizeof(MCRegisterClass),
530 .NameIdx: 67,
531 .RegSizeInBits: 16,
532 .RegsSize: 13,
533 .RegSetSize: 8,
534 .ID: AVR::DREGS_with_sub_lo_in_LD8RegClassID,
535 .CopyCost: 1, /* CopyCost */
536 .Allocatable: true, /* Allocatable */
537 .BaseClass: false,
538 offsetof(AVRRegisterClassStorage, SubClassMasks[50]) - 13 * sizeof(MCRegisterClass),
539 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 13 * sizeof(MCRegisterClass),
540 .LaneMask: LaneBitmask(0x0000000000000003),
541 .AllocationPriority: 0,
542 .GlobalPriority: false,
543 .TSFlags: 0x00, /* TSFlags */
544 .SpillStackID: 0, /* SpillStackID */
545 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
546 .CoveredBySubRegs: true, /* CoveredBySubRegs */
547 offsetof(AVRRegisterClassStorage, SuperClasses[20]) - 13 * sizeof(MCRegisterClass),
548 .SuperClassesSize: 2
549 },
550 {
551 offsetof(AVRRegisterClassStorage, Regs[237]) - 14 * sizeof(MCRegisterClass),
552 offsetof(AVRRegisterClassStorage, BitSets[84]) - 14 * sizeof(MCRegisterClass),
553 .NameIdx: 54,
554 .RegSizeInBits: 16,
555 .RegsSize: 12,
556 .RegSetSize: 8,
557 .ID: AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
558 .CopyCost: 1, /* CopyCost */
559 .Allocatable: true, /* Allocatable */
560 .BaseClass: false,
561 offsetof(AVRRegisterClassStorage, SubClassMasks[52]) - 14 * sizeof(MCRegisterClass),
562 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 14 * sizeof(MCRegisterClass),
563 .LaneMask: LaneBitmask(0x0000000000000003),
564 .AllocationPriority: 0,
565 .GlobalPriority: false,
566 .TSFlags: 0x00, /* TSFlags */
567 .SpillStackID: 0, /* SpillStackID */
568 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
569 .CoveredBySubRegs: true, /* CoveredBySubRegs */
570 offsetof(AVRRegisterClassStorage, SuperClasses[22]) - 14 * sizeof(MCRegisterClass),
571 .SuperClassesSize: 5
572 },
573 {
574 offsetof(AVRRegisterClassStorage, Regs[249]) - 15 * sizeof(MCRegisterClass),
575 offsetof(AVRRegisterClassStorage, BitSets[92]) - 15 * sizeof(MCRegisterClass),
576 .NameIdx: 426,
577 .RegSizeInBits: 16,
578 .RegsSize: 12,
579 .RegSetSize: 7,
580 .ID: AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
581 .CopyCost: 1, /* CopyCost */
582 .Allocatable: true, /* Allocatable */
583 .BaseClass: false,
584 offsetof(AVRRegisterClassStorage, SubClassMasks[54]) - 15 * sizeof(MCRegisterClass),
585 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 15 * sizeof(MCRegisterClass),
586 .LaneMask: LaneBitmask(0x0000000000000003),
587 .AllocationPriority: 0,
588 .GlobalPriority: false,
589 .TSFlags: 0x00, /* TSFlags */
590 .SpillStackID: 0, /* SpillStackID */
591 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
592 .CoveredBySubRegs: true, /* CoveredBySubRegs */
593 offsetof(AVRRegisterClassStorage, SuperClasses[27]) - 15 * sizeof(MCRegisterClass),
594 .SuperClassesSize: 2
595 },
596 {
597 offsetof(AVRRegisterClassStorage, Regs[261]) - 16 * sizeof(MCRegisterClass),
598 offsetof(AVRRegisterClassStorage, BitSets[99]) - 16 * sizeof(MCRegisterClass),
599 .NameIdx: 369,
600 .RegSizeInBits: 16,
601 .RegsSize: 11,
602 .RegSetSize: 6,
603 .ID: AVR::DREGS_with_sub_hi_in_GPR8loRegClassID,
604 .CopyCost: 1, /* CopyCost */
605 .Allocatable: true, /* Allocatable */
606 .BaseClass: false,
607 offsetof(AVRRegisterClassStorage, SubClassMasks[56]) - 16 * sizeof(MCRegisterClass),
608 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 16 * sizeof(MCRegisterClass),
609 .LaneMask: LaneBitmask(0x0000000000000003),
610 .AllocationPriority: 0,
611 .GlobalPriority: false,
612 .TSFlags: 0x00, /* TSFlags */
613 .SpillStackID: 0, /* SpillStackID */
614 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
615 .CoveredBySubRegs: true, /* CoveredBySubRegs */
616 offsetof(AVRRegisterClassStorage, SuperClasses[29]) - 16 * sizeof(MCRegisterClass),
617 .SuperClassesSize: 3
618 },
619 {
620 offsetof(AVRRegisterClassStorage, Regs[272]) - 17 * sizeof(MCRegisterClass),
621 offsetof(AVRRegisterClassStorage, BitSets[105]) - 17 * sizeof(MCRegisterClass),
622 .NameIdx: 168,
623 .RegSizeInBits: 16,
624 .RegsSize: 8,
625 .RegSetSize: 8,
626 .ID: AVR::DLDREGSRegClassID,
627 .CopyCost: 1, /* CopyCost */
628 .Allocatable: true, /* Allocatable */
629 .BaseClass: false,
630 offsetof(AVRRegisterClassStorage, SubClassMasks[58]) - 17 * sizeof(MCRegisterClass),
631 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 17 * sizeof(MCRegisterClass),
632 .LaneMask: LaneBitmask(0x0000000000000003),
633 .AllocationPriority: 0,
634 .GlobalPriority: false,
635 .TSFlags: 0x00, /* TSFlags */
636 .SpillStackID: 0, /* SpillStackID */
637 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
638 .CoveredBySubRegs: true, /* CoveredBySubRegs */
639 offsetof(AVRRegisterClassStorage, SuperClasses[32]) - 17 * sizeof(MCRegisterClass),
640 .SuperClassesSize: 4
641 },
642 {
643 offsetof(AVRRegisterClassStorage, Regs[280]) - 18 * sizeof(MCRegisterClass),
644 offsetof(AVRRegisterClassStorage, BitSets[113]) - 18 * sizeof(MCRegisterClass),
645 .NameIdx: 315,
646 .RegSizeInBits: 16,
647 .RegsSize: 8,
648 .RegSetSize: 7,
649 .ID: AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
650 .CopyCost: 1, /* CopyCost */
651 .Allocatable: true, /* Allocatable */
652 .BaseClass: false,
653 offsetof(AVRRegisterClassStorage, SubClassMasks[60]) - 18 * sizeof(MCRegisterClass),
654 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 18 * sizeof(MCRegisterClass),
655 .LaneMask: LaneBitmask(0x0000000000000003),
656 .AllocationPriority: 0,
657 .GlobalPriority: false,
658 .TSFlags: 0x00, /* TSFlags */
659 .SpillStackID: 0, /* SpillStackID */
660 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
661 .CoveredBySubRegs: true, /* CoveredBySubRegs */
662 offsetof(AVRRegisterClassStorage, SuperClasses[36]) - 18 * sizeof(MCRegisterClass),
663 .SuperClassesSize: 4
664 },
665 {
666 offsetof(AVRRegisterClassStorage, Regs[288]) - 19 * sizeof(MCRegisterClass),
667 offsetof(AVRRegisterClassStorage, BitSets[120]) - 19 * sizeof(MCRegisterClass),
668 .NameIdx: 342,
669 .RegSizeInBits: 16,
670 .RegsSize: 8,
671 .RegSetSize: 8,
672 .ID: AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
673 .CopyCost: 1, /* CopyCost */
674 .Allocatable: true, /* Allocatable */
675 .BaseClass: false,
676 offsetof(AVRRegisterClassStorage, SubClassMasks[62]) - 19 * sizeof(MCRegisterClass),
677 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 19 * sizeof(MCRegisterClass),
678 .LaneMask: LaneBitmask(0x0000000000000003),
679 .AllocationPriority: 0,
680 .GlobalPriority: false,
681 .TSFlags: 0x00, /* TSFlags */
682 .SpillStackID: 0, /* SpillStackID */
683 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
684 .CoveredBySubRegs: true, /* CoveredBySubRegs */
685 offsetof(AVRRegisterClassStorage, SuperClasses[40]) - 19 * sizeof(MCRegisterClass),
686 .SuperClassesSize: 6
687 },
688 {
689 offsetof(AVRRegisterClassStorage, Regs[296]) - 20 * sizeof(MCRegisterClass),
690 offsetof(AVRRegisterClassStorage, BitSets[128]) - 20 * sizeof(MCRegisterClass),
691 .NameIdx: 454,
692 .RegSizeInBits: 16,
693 .RegsSize: 8,
694 .RegSetSize: 6,
695 .ID: AVR::DREGSloRegClassID,
696 .CopyCost: 1, /* CopyCost */
697 .Allocatable: true, /* Allocatable */
698 .BaseClass: false,
699 offsetof(AVRRegisterClassStorage, SubClassMasks[64]) - 20 * sizeof(MCRegisterClass),
700 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 20 * sizeof(MCRegisterClass),
701 .LaneMask: LaneBitmask(0x0000000000000003),
702 .AllocationPriority: 0,
703 .GlobalPriority: false,
704 .TSFlags: 0x00, /* TSFlags */
705 .SpillStackID: 0, /* SpillStackID */
706 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
707 .CoveredBySubRegs: true, /* CoveredBySubRegs */
708 offsetof(AVRRegisterClassStorage, SuperClasses[46]) - 20 * sizeof(MCRegisterClass),
709 .SuperClassesSize: 6
710 },
711 {
712 offsetof(AVRRegisterClassStorage, Regs[304]) - 21 * sizeof(MCRegisterClass),
713 offsetof(AVRRegisterClassStorage, BitSets[134]) - 21 * sizeof(MCRegisterClass),
714 .NameIdx: 260,
715 .RegSizeInBits: 16,
716 .RegsSize: 7,
717 .RegSetSize: 8,
718 .ID: AVR::DLDREGS_and_DREGSNOZRegClassID,
719 .CopyCost: 1, /* CopyCost */
720 .Allocatable: true, /* Allocatable */
721 .BaseClass: false,
722 offsetof(AVRRegisterClassStorage, SubClassMasks[66]) - 21 * sizeof(MCRegisterClass),
723 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 21 * sizeof(MCRegisterClass),
724 .LaneMask: LaneBitmask(0x0000000000000003),
725 .AllocationPriority: 0,
726 .GlobalPriority: false,
727 .TSFlags: 0x00, /* TSFlags */
728 .SpillStackID: 0, /* SpillStackID */
729 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
730 .CoveredBySubRegs: true, /* CoveredBySubRegs */
731 offsetof(AVRRegisterClassStorage, SuperClasses[52]) - 21 * sizeof(MCRegisterClass),
732 .SuperClassesSize: 9
733 },
734 {
735 offsetof(AVRRegisterClassStorage, Regs[311]) - 22 * sizeof(MCRegisterClass),
736 offsetof(AVRRegisterClassStorage, BitSets[142]) - 22 * sizeof(MCRegisterClass),
737 .NameIdx: 92,
738 .RegSizeInBits: 16,
739 .RegsSize: 7,
740 .RegSetSize: 7,
741 .ID: AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID,
742 .CopyCost: 1, /* CopyCost */
743 .Allocatable: true, /* Allocatable */
744 .BaseClass: false,
745 offsetof(AVRRegisterClassStorage, SubClassMasks[68]) - 22 * sizeof(MCRegisterClass),
746 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 22 * sizeof(MCRegisterClass),
747 .LaneMask: LaneBitmask(0x0000000000000003),
748 .AllocationPriority: 0,
749 .GlobalPriority: false,
750 .TSFlags: 0x00, /* TSFlags */
751 .SpillStackID: 0, /* SpillStackID */
752 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
753 .CoveredBySubRegs: true, /* CoveredBySubRegs */
754 offsetof(AVRRegisterClassStorage, SuperClasses[61]) - 22 * sizeof(MCRegisterClass),
755 .SuperClassesSize: 8
756 },
757 {
758 offsetof(AVRRegisterClassStorage, Regs[318]) - 23 * sizeof(MCRegisterClass),
759 offsetof(AVRRegisterClassStorage, BitSets[149]) - 23 * sizeof(MCRegisterClass),
760 .NameIdx: 304,
761 .RegSizeInBits: 16,
762 .RegsSize: 4,
763 .RegSetSize: 7,
764 .ID: AVR::DREGSLD8loRegClassID,
765 .CopyCost: 1, /* CopyCost */
766 .Allocatable: true, /* Allocatable */
767 .BaseClass: false,
768 offsetof(AVRRegisterClassStorage, SubClassMasks[70]) - 23 * sizeof(MCRegisterClass),
769 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 23 * sizeof(MCRegisterClass),
770 .LaneMask: LaneBitmask(0x0000000000000003),
771 .AllocationPriority: 0,
772 .GlobalPriority: false,
773 .TSFlags: 0x00, /* TSFlags */
774 .SpillStackID: 0, /* SpillStackID */
775 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
776 .CoveredBySubRegs: true, /* CoveredBySubRegs */
777 offsetof(AVRRegisterClassStorage, SuperClasses[69]) - 23 * sizeof(MCRegisterClass),
778 .SuperClassesSize: 13
779 },
780 {
781 offsetof(AVRRegisterClassStorage, Regs[322]) - 24 * sizeof(MCRegisterClass),
782 offsetof(AVRRegisterClassStorage, BitSets[156]) - 24 * sizeof(MCRegisterClass),
783 .NameIdx: 235,
784 .RegSizeInBits: 16,
785 .RegsSize: 4,
786 .RegSetSize: 8,
787 .ID: AVR::IWREGSRegClassID,
788 .CopyCost: 1, /* CopyCost */
789 .Allocatable: true, /* Allocatable */
790 .BaseClass: false,
791 offsetof(AVRRegisterClassStorage, SubClassMasks[72]) - 24 * sizeof(MCRegisterClass),
792 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 24 * sizeof(MCRegisterClass),
793 .LaneMask: LaneBitmask(0x0000000000000003),
794 .AllocationPriority: 0,
795 .GlobalPriority: false,
796 .TSFlags: 0x00, /* TSFlags */
797 .SpillStackID: 0, /* SpillStackID */
798 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
799 .CoveredBySubRegs: true, /* CoveredBySubRegs */
800 offsetof(AVRRegisterClassStorage, SuperClasses[82]) - 24 * sizeof(MCRegisterClass),
801 .SuperClassesSize: 5
802 },
803 {
804 offsetof(AVRRegisterClassStorage, Regs[326]) - 25 * sizeof(MCRegisterClass),
805 offsetof(AVRRegisterClassStorage, BitSets[164]) - 25 * sizeof(MCRegisterClass),
806 .NameIdx: 222,
807 .RegSizeInBits: 16,
808 .RegsSize: 3,
809 .RegSetSize: 8,
810 .ID: AVR::DREGSNOZ_and_IWREGSRegClassID,
811 .CopyCost: 1, /* CopyCost */
812 .Allocatable: true, /* Allocatable */
813 .BaseClass: false,
814 offsetof(AVRRegisterClassStorage, SubClassMasks[74]) - 25 * sizeof(MCRegisterClass),
815 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 25 * sizeof(MCRegisterClass),
816 .LaneMask: LaneBitmask(0x0000000000000003),
817 .AllocationPriority: 0,
818 .GlobalPriority: false,
819 .TSFlags: 0x00, /* TSFlags */
820 .SpillStackID: 0, /* SpillStackID */
821 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
822 .CoveredBySubRegs: true, /* CoveredBySubRegs */
823 offsetof(AVRRegisterClassStorage, SuperClasses[87]) - 25 * sizeof(MCRegisterClass),
824 .SuperClassesSize: 11
825 },
826 {
827 offsetof(AVRRegisterClassStorage, Regs[329]) - 26 * sizeof(MCRegisterClass),
828 offsetof(AVRRegisterClassStorage, BitSets[172]) - 26 * sizeof(MCRegisterClass),
829 .NameIdx: 214,
830 .RegSizeInBits: 16,
831 .RegsSize: 3,
832 .RegSetSize: 8,
833 .ID: AVR::PTRREGSRegClassID,
834 .CopyCost: 1, /* CopyCost */
835 .Allocatable: true, /* Allocatable */
836 .BaseClass: false,
837 offsetof(AVRRegisterClassStorage, SubClassMasks[76]) - 26 * sizeof(MCRegisterClass),
838 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 26 * sizeof(MCRegisterClass),
839 .LaneMask: LaneBitmask(0x0000000000000003),
840 .AllocationPriority: 0,
841 .GlobalPriority: false,
842 .TSFlags: 0x00, /* TSFlags */
843 .SpillStackID: 0, /* SpillStackID */
844 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
845 .CoveredBySubRegs: true, /* CoveredBySubRegs */
846 offsetof(AVRRegisterClassStorage, SuperClasses[98]) - 26 * sizeof(MCRegisterClass),
847 .SuperClassesSize: 6
848 },
849 {
850 offsetof(AVRRegisterClassStorage, Regs[332]) - 27 * sizeof(MCRegisterClass),
851 offsetof(AVRRegisterClassStorage, BitSets[180]) - 27 * sizeof(MCRegisterClass),
852 .NameIdx: 201,
853 .RegSizeInBits: 16,
854 .RegsSize: 2,
855 .RegSetSize: 8,
856 .ID: AVR::DREGSNOZ_and_PTRREGSRegClassID,
857 .CopyCost: 1, /* CopyCost */
858 .Allocatable: true, /* Allocatable */
859 .BaseClass: false,
860 offsetof(AVRRegisterClassStorage, SubClassMasks[78]) - 27 * sizeof(MCRegisterClass),
861 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 27 * sizeof(MCRegisterClass),
862 .LaneMask: LaneBitmask(0x0000000000000003),
863 .AllocationPriority: 0,
864 .GlobalPriority: false,
865 .TSFlags: 0x00, /* TSFlags */
866 .SpillStackID: 0, /* SpillStackID */
867 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
868 .CoveredBySubRegs: true, /* CoveredBySubRegs */
869 offsetof(AVRRegisterClassStorage, SuperClasses[104]) - 27 * sizeof(MCRegisterClass),
870 .SuperClassesSize: 13
871 },
872 {
873 offsetof(AVRRegisterClassStorage, Regs[334]) - 28 * sizeof(MCRegisterClass),
874 offsetof(AVRRegisterClassStorage, BitSets[188]) - 28 * sizeof(MCRegisterClass),
875 .NameIdx: 189,
876 .RegSizeInBits: 16,
877 .RegsSize: 2,
878 .RegSetSize: 8,
879 .ID: AVR::PTRDISPREGSRegClassID,
880 .CopyCost: 1, /* CopyCost */
881 .Allocatable: true, /* Allocatable */
882 .BaseClass: false,
883 offsetof(AVRRegisterClassStorage, SubClassMasks[80]) - 28 * sizeof(MCRegisterClass),
884 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 28 * sizeof(MCRegisterClass),
885 .LaneMask: LaneBitmask(0x0000000000000003),
886 .AllocationPriority: 0,
887 .GlobalPriority: false,
888 .TSFlags: 0x00, /* TSFlags */
889 .SpillStackID: 0, /* SpillStackID */
890 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
891 .CoveredBySubRegs: true, /* CoveredBySubRegs */
892 offsetof(AVRRegisterClassStorage, SuperClasses[117]) - 28 * sizeof(MCRegisterClass),
893 .SuperClassesSize: 7
894 },
895 {
896 offsetof(AVRRegisterClassStorage, Regs[336]) - 29 * sizeof(MCRegisterClass),
897 offsetof(AVRRegisterClassStorage, BitSets[196]) - 29 * sizeof(MCRegisterClass),
898 .NameIdx: 176,
899 .RegSizeInBits: 16,
900 .RegsSize: 1,
901 .RegSetSize: 8,
902 .ID: AVR::DREGSNOZ_and_PTRDISPREGSRegClassID,
903 .CopyCost: 1, /* CopyCost */
904 .Allocatable: true, /* Allocatable */
905 .BaseClass: false,
906 offsetof(AVRRegisterClassStorage, SubClassMasks[82]) - 29 * sizeof(MCRegisterClass),
907 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 29 * sizeof(MCRegisterClass),
908 .LaneMask: LaneBitmask(0x0000000000000003),
909 .AllocationPriority: 0,
910 .GlobalPriority: false,
911 .TSFlags: 0x00, /* TSFlags */
912 .SpillStackID: 0, /* SpillStackID */
913 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
914 .CoveredBySubRegs: true, /* CoveredBySubRegs */
915 offsetof(AVRRegisterClassStorage, SuperClasses[124]) - 29 * sizeof(MCRegisterClass),
916 .SuperClassesSize: 15
917 },
918 {
919 offsetof(AVRRegisterClassStorage, Regs[337]) - 30 * sizeof(MCRegisterClass),
920 offsetof(AVRRegisterClassStorage, BitSets[204]) - 30 * sizeof(MCRegisterClass),
921 .NameIdx: 397,
922 .RegSizeInBits: 16,
923 .RegsSize: 1,
924 .RegSetSize: 7,
925 .ID: AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID,
926 .CopyCost: 1, /* CopyCost */
927 .Allocatable: true, /* Allocatable */
928 .BaseClass: false,
929 offsetof(AVRRegisterClassStorage, SubClassMasks[84]) - 30 * sizeof(MCRegisterClass),
930 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 30 * sizeof(MCRegisterClass),
931 .LaneMask: LaneBitmask(0x0000000000000003),
932 .AllocationPriority: 0,
933 .GlobalPriority: false,
934 .TSFlags: 0x00, /* TSFlags */
935 .SpillStackID: 0, /* SpillStackID */
936 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
937 .CoveredBySubRegs: true, /* CoveredBySubRegs */
938 offsetof(AVRRegisterClassStorage, SuperClasses[139]) - 30 * sizeof(MCRegisterClass),
939 .SuperClassesSize: 6
940 },
941 {
942 offsetof(AVRRegisterClassStorage, Regs[338]) - 31 * sizeof(MCRegisterClass),
943 offsetof(AVRRegisterClassStorage, BitSets[211]) - 31 * sizeof(MCRegisterClass),
944 .NameIdx: 158,
945 .RegSizeInBits: 16,
946 .RegsSize: 1,
947 .RegSetSize: 1,
948 .ID: AVR::GPRSPRegClassID,
949 .CopyCost: 1, /* CopyCost */
950 .Allocatable: true, /* Allocatable */
951 .BaseClass: false,
952 offsetof(AVRRegisterClassStorage, SubClassMasks[86]) - 31 * sizeof(MCRegisterClass),
953 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 31 * sizeof(MCRegisterClass),
954 .LaneMask: LaneBitmask(0x0000000000000003),
955 .AllocationPriority: 0,
956 .GlobalPriority: false,
957 .TSFlags: 0x00, /* TSFlags */
958 .SpillStackID: 0, /* SpillStackID */
959 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
960 .CoveredBySubRegs: true, /* CoveredBySubRegs */
961 offsetof(AVRRegisterClassStorage, SuperClasses[145]) - 31 * sizeof(MCRegisterClass),
962 .SuperClassesSize: 0
963 },
964 {
965 offsetof(AVRRegisterClassStorage, Regs[339]) - 32 * sizeof(MCRegisterClass),
966 offsetof(AVRRegisterClassStorage, BitSets[212]) - 32 * sizeof(MCRegisterClass),
967 .NameIdx: 153,
968 .RegSizeInBits: 16,
969 .RegsSize: 1,
970 .RegSetSize: 8,
971 .ID: AVR::ZREGRegClassID,
972 .CopyCost: 1, /* CopyCost */
973 .Allocatable: true, /* Allocatable */
974 .BaseClass: false,
975 offsetof(AVRRegisterClassStorage, SubClassMasks[88]) - 32 * sizeof(MCRegisterClass),
976 offsetof(AVRRegisterClassStorage, SuperRegIdxSeqs[2]) - 32 * sizeof(MCRegisterClass),
977 .LaneMask: LaneBitmask(0x0000000000000003),
978 .AllocationPriority: 0,
979 .GlobalPriority: false,
980 .TSFlags: 0x00, /* TSFlags */
981 .SpillStackID: 0, /* SpillStackID */
982 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
983 .CoveredBySubRegs: true, /* CoveredBySubRegs */
984 offsetof(AVRRegisterClassStorage, SuperClasses[145]) - 32 * sizeof(MCRegisterClass),
985 .SuperClassesSize: 8
986 },
987 },
988 .Regs: {
989 /* 0 */ AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
990 /* 32 */ AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
991 /* 62 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
992 /* 78 */ AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
993 /* 94 */ AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
994 /* 108 */ AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16,
995 /* 116 */ AVR::SREG,
996 /* 117 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
997 /* 142 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
998 /* 166 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
999 /* 182 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
1000 /* 197 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
1001 /* 211 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
1002 /* 224 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
1003 /* 237 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
1004 /* 249 */ AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
1005 /* 261 */ AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R14R13, AVR::R12R11, AVR::R10R9,
1006 /* 272 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16,
1007 /* 280 */ AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
1008 /* 288 */ AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
1009 /* 296 */ AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
1010 /* 304 */ AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16,
1011 /* 311 */ AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17,
1012 /* 318 */ AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16,
1013 /* 322 */ AVR::R25R24, AVR::R31R30, AVR::R27R26, AVR::R29R28,
1014 /* 326 */ AVR::R25R24, AVR::R27R26, AVR::R29R28,
1015 /* 329 */ AVR::R27R26, AVR::R29R28, AVR::R31R30,
1016 /* 332 */ AVR::R27R26, AVR::R29R28,
1017 /* 334 */ AVR::R31R30, AVR::R29R28,
1018 /* 336 */ AVR::R29R28,
1019 /* 337 */ AVR::R16R15,
1020 /* 338 */ AVR::SP,
1021 /* 339 */ AVR::R31R30,
1022 },
1023 .BitSets: {
1024 /* 0 */ 0xe0, 0xff, 0xff, 0xff, 0x1f,
1025 /* 5 */ 0xe0, 0xff, 0xff, 0xff, 0x07,
1026 /* 10 */ 0xe0, 0xff, 0x1f,
1027 /* 13 */ 0x00, 0x00, 0xe0, 0xff, 0x1f,
1028 /* 18 */ 0x00, 0x00, 0xe0, 0xff, 0x07,
1029 /* 23 */ 0x00, 0x00, 0xe0, 0x1f,
1030 /* 27 */ 0x10,
1031 /* 28 */ 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x3f,
1032 /* 36 */ 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x1f,
1033 /* 44 */ 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x3a,
1034 /* 52 */ 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x1a,
1035 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
1036 /* 68 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f,
1037 /* 76 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
1038 /* 84 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f,
1039 /* 92 */ 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01,
1040 /* 99 */ 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff,
1041 /* 105 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x3a,
1042 /* 113 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1043 /* 120 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
1044 /* 128 */ 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab,
1045 /* 134 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x1a,
1046 /* 142 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1047 /* 149 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
1048 /* 156 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a,
1049 /* 164 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,
1050 /* 172 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
1051 /* 180 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
1052 /* 188 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
1053 /* 196 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1054 /* 204 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1055 /* 211 */ 0x02,
1056 /* 212 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1057 },
1058 .SubClassMasks: {
1059 // 0 GPR8
1060 0x0000003f, 0x00000000,
1061 0x7fffff80, 0x00000001, // sub_hi
1062 0x7fffff80, 0x00000001, // sub_lo
1063 // 6 GPR8NOZ
1064 0x00000036, 0x00000000,
1065 0x6afdd500, 0x00000000, // sub_hi
1066 0x6afdd500, 0x00000000, // sub_lo
1067 // 12 GPR8lo
1068 0x00000004, 0x00000000,
1069 0x00110000, 0x00000000, // sub_hi
1070 0x40118000, 0x00000000, // sub_lo
1071 // 18 LD8
1072 0x00000038, 0x00000000,
1073 0x7fee7800, 0x00000001, // sub_hi
1074 0x3fea6000, 0x00000001, // sub_lo
1075 // 24 GPR8NOZ_and_LD8
1076 0x00000030, 0x00000000,
1077 0x6aec5000, 0x00000000, // sub_hi
1078 0x2ae84000, 0x00000000, // sub_lo
1079 // 30 LD8lo
1080 0x00000020, 0x00000000,
1081 0x40c40000, 0x00000000, // sub_hi
1082 0x00c80000, 0x00000000, // sub_lo
1083 // 36 CCR
1084 0x00000040, 0x00000000,
1085 // 38 DREGS
1086 0x7fffff80, 0x00000001,
1087 // 40 DREGSNOZ
1088 0x6afdd500, 0x00000000,
1089 // 42 DREGSMOVW
1090 0x3fb20600, 0x00000001,
1091 // 44 DREGSMOVW_and_DREGSNOZ
1092 0x2ab00400, 0x00000000,
1093 // 46 DREGS_with_sub_hi_in_LD8
1094 0x7fee7800, 0x00000001,
1095 // 48 DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1096 0x6aec5000, 0x00000000,
1097 // 50 DREGS_with_sub_lo_in_LD8
1098 0x3fea6000, 0x00000001,
1099 // 52 DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1100 0x2ae84000, 0x00000000,
1101 // 54 DREGS_with_sub_lo_in_GPR8lo
1102 0x40118000, 0x00000000,
1103 // 56 DREGS_with_sub_hi_in_GPR8lo
1104 0x00110000, 0x00000000,
1105 // 58 DLDREGS
1106 0x3fa20000, 0x00000001,
1107 // 60 DREGS_with_sub_hi_in_LD8lo
1108 0x40c40000, 0x00000000,
1109 // 62 DREGS_with_sub_lo_in_LD8lo
1110 0x00c80000, 0x00000000,
1111 // 64 DREGSlo
1112 0x00100000, 0x00000000,
1113 // 66 DLDREGS_and_DREGSNOZ
1114 0x2aa00000, 0x00000000,
1115 // 68 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1116 0x00c00000, 0x00000000,
1117 // 70 DREGSLD8lo
1118 0x00800000, 0x00000000,
1119 // 72 IWREGS
1120 0x3f000000, 0x00000001,
1121 // 74 DREGSNOZ_and_IWREGS
1122 0x2a000000, 0x00000000,
1123 // 76 PTRREGS
1124 0x3c000000, 0x00000001,
1125 // 78 DREGSNOZ_and_PTRREGS
1126 0x28000000, 0x00000000,
1127 // 80 PTRDISPREGS
1128 0x30000000, 0x00000001,
1129 // 82 DREGSNOZ_and_PTRDISPREGS
1130 0x20000000, 0x00000000,
1131 // 84 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1132 0x40000000, 0x00000000,
1133 // 86 GPRSP
1134 0x80000000, 0x00000000,
1135 // 88 ZREG
1136 0x00000000, 0x00000001,
1137 },
1138 .SuperRegIdxSeqs: {
1139 /* 0 */ 1, 2, 0,
1140 },
1141 .SuperClasses: {
1142 /* 0 GPR8 */
1143 /* 0 GPR8NOZ */ AVR::GPR8RegClassID,
1144 /* 1 GPR8lo */ AVR::GPR8RegClassID, AVR::GPR8NOZRegClassID,
1145 /* 3 LD8 */ AVR::GPR8RegClassID,
1146 /* 4 GPR8NOZ_and_LD8 */ AVR::GPR8RegClassID, AVR::GPR8NOZRegClassID, AVR::LD8RegClassID,
1147 /* 7 LD8lo */ AVR::GPR8RegClassID, AVR::GPR8NOZRegClassID, AVR::LD8RegClassID, AVR::GPR8NOZ_and_LD8RegClassID,
1148 /* 11 CCR */
1149 /* 11 DREGS */
1150 /* 11 DREGSNOZ */ AVR::DREGSRegClassID,
1151 /* 12 DREGSMOVW */ AVR::DREGSRegClassID,
1152 /* 13 DREGSMOVW_and_DREGSNOZ */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID,
1153 /* 16 DREGS_with_sub_hi_in_LD8 */ AVR::DREGSRegClassID,
1154 /* 17 DREGSNOZ_and_DREGS_with_sub_hi_in_LD8 */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1155 /* 20 DREGS_with_sub_lo_in_LD8 */ AVR::DREGSRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1156 /* 22 DREGSNOZ_and_DREGS_with_sub_lo_in_LD8 */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1157 /* 27 DREGS_with_sub_lo_in_GPR8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID,
1158 /* 29 DREGS_with_sub_hi_in_GPR8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
1159 /* 32 DLDREGS */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1160 /* 36 DREGS_with_sub_hi_in_LD8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
1161 /* 40 DREGS_with_sub_lo_in_LD8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
1162 /* 46 DREGSlo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, AVR::DREGS_with_sub_hi_in_GPR8loRegClassID,
1163 /* 52 DLDREGS_and_DREGSNOZ */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID,
1164 /* 61 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGS_with_sub_hi_in_LD8loRegClassID, AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
1165 /* 69 DREGSLD8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::DREGS_with_sub_hi_in_LD8loRegClassID, AVR::DREGS_with_sub_lo_in_LD8loRegClassID, AVR::DLDREGS_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID,
1166 /* 82 IWREGS */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID,
1167 /* 87 DREGSNOZ_and_IWREGS */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::DLDREGS_and_DREGSNOZRegClassID, AVR::IWREGSRegClassID,
1168 /* 98 PTRREGS */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::IWREGSRegClassID,
1169 /* 104 DREGSNOZ_and_PTRREGS */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::DLDREGS_and_DREGSNOZRegClassID, AVR::IWREGSRegClassID, AVR::DREGSNOZ_and_IWREGSRegClassID, AVR::PTRREGSRegClassID,
1170 /* 117 PTRDISPREGS */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::IWREGSRegClassID, AVR::PTRREGSRegClassID,
1171 /* 124 DREGSNOZ_and_PTRDISPREGS */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGSMOVW_and_DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::DLDREGS_and_DREGSNOZRegClassID, AVR::IWREGSRegClassID, AVR::DREGSNOZ_and_IWREGSRegClassID, AVR::PTRREGSRegClassID, AVR::DREGSNOZ_and_PTRREGSRegClassID, AVR::PTRDISPREGSRegClassID,
1172 /* 139 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo */ AVR::DREGSRegClassID, AVR::DREGSNOZRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
1173 /* 145 GPRSP */
1174 /* 145 ZREG */ AVR::DREGSRegClassID, AVR::DREGSMOVWRegClassID, AVR::DREGS_with_sub_hi_in_LD8RegClassID, AVR::DREGS_with_sub_lo_in_LD8RegClassID, AVR::DLDREGSRegClassID, AVR::IWREGSRegClassID, AVR::PTRREGSRegClassID, AVR::PTRDISPREGSRegClassID,
1175 }
1176};
1177
1178const MCRegisterClass &getAVRMCRegisterClass(unsigned RC) {
1179 return AVRMCRegisterClassStorage.Classes[RC];
1180}
1181
1182// AVR Dwarf<->LLVM register mappings.
1183extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
1184 { .FromReg: 0U, .ToReg: AVR::R1R0 },
1185 { .FromReg: 1U, .ToReg: AVR::R1 },
1186 { .FromReg: 2U, .ToReg: AVR::R3R2 },
1187 { .FromReg: 3U, .ToReg: AVR::R3 },
1188 { .FromReg: 4U, .ToReg: AVR::R5R4 },
1189 { .FromReg: 5U, .ToReg: AVR::R5 },
1190 { .FromReg: 6U, .ToReg: AVR::R7R6 },
1191 { .FromReg: 7U, .ToReg: AVR::R7 },
1192 { .FromReg: 8U, .ToReg: AVR::R9R8 },
1193 { .FromReg: 9U, .ToReg: AVR::R10R9 },
1194 { .FromReg: 10U, .ToReg: AVR::R11R10 },
1195 { .FromReg: 11U, .ToReg: AVR::R12R11 },
1196 { .FromReg: 12U, .ToReg: AVR::R13R12 },
1197 { .FromReg: 13U, .ToReg: AVR::R14R13 },
1198 { .FromReg: 14U, .ToReg: AVR::R15R14 },
1199 { .FromReg: 15U, .ToReg: AVR::R16R15 },
1200 { .FromReg: 16U, .ToReg: AVR::R17R16 },
1201 { .FromReg: 17U, .ToReg: AVR::R18R17 },
1202 { .FromReg: 18U, .ToReg: AVR::R19R18 },
1203 { .FromReg: 19U, .ToReg: AVR::R20R19 },
1204 { .FromReg: 20U, .ToReg: AVR::R21R20 },
1205 { .FromReg: 21U, .ToReg: AVR::R22R21 },
1206 { .FromReg: 22U, .ToReg: AVR::R23R22 },
1207 { .FromReg: 23U, .ToReg: AVR::R24R23 },
1208 { .FromReg: 24U, .ToReg: AVR::R25R24 },
1209 { .FromReg: 25U, .ToReg: AVR::R26R25 },
1210 { .FromReg: 26U, .ToReg: AVR::R27R26 },
1211 { .FromReg: 27U, .ToReg: AVR::R27 },
1212 { .FromReg: 28U, .ToReg: AVR::R29R28 },
1213 { .FromReg: 29U, .ToReg: AVR::R29 },
1214 { .FromReg: 30U, .ToReg: AVR::R31R30 },
1215 { .FromReg: 31U, .ToReg: AVR::R31 },
1216 { .FromReg: 32U, .ToReg: AVR::SPL },
1217 { .FromReg: 33U, .ToReg: AVR::SPH },
1218 { .FromReg: 88U, .ToReg: AVR::SREG },
1219};
1220extern const unsigned AVRDwarfFlavour0Dwarf2LSize = std::size(AVRDwarfFlavour0Dwarf2L);
1221
1222extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
1223 { .FromReg: 0U, .ToReg: AVR::R1R0 },
1224 { .FromReg: 1U, .ToReg: AVR::R1 },
1225 { .FromReg: 2U, .ToReg: AVR::R3R2 },
1226 { .FromReg: 3U, .ToReg: AVR::R3 },
1227 { .FromReg: 4U, .ToReg: AVR::R5R4 },
1228 { .FromReg: 5U, .ToReg: AVR::R5 },
1229 { .FromReg: 6U, .ToReg: AVR::R7R6 },
1230 { .FromReg: 7U, .ToReg: AVR::R7 },
1231 { .FromReg: 8U, .ToReg: AVR::R9R8 },
1232 { .FromReg: 9U, .ToReg: AVR::R10R9 },
1233 { .FromReg: 10U, .ToReg: AVR::R11R10 },
1234 { .FromReg: 11U, .ToReg: AVR::R12R11 },
1235 { .FromReg: 12U, .ToReg: AVR::R13R12 },
1236 { .FromReg: 13U, .ToReg: AVR::R14R13 },
1237 { .FromReg: 14U, .ToReg: AVR::R15R14 },
1238 { .FromReg: 15U, .ToReg: AVR::R16R15 },
1239 { .FromReg: 16U, .ToReg: AVR::R17R16 },
1240 { .FromReg: 17U, .ToReg: AVR::R18R17 },
1241 { .FromReg: 18U, .ToReg: AVR::R19R18 },
1242 { .FromReg: 19U, .ToReg: AVR::R20R19 },
1243 { .FromReg: 20U, .ToReg: AVR::R21R20 },
1244 { .FromReg: 21U, .ToReg: AVR::R22R21 },
1245 { .FromReg: 22U, .ToReg: AVR::R23R22 },
1246 { .FromReg: 23U, .ToReg: AVR::R24R23 },
1247 { .FromReg: 24U, .ToReg: AVR::R25R24 },
1248 { .FromReg: 25U, .ToReg: AVR::R26R25 },
1249 { .FromReg: 26U, .ToReg: AVR::R27R26 },
1250 { .FromReg: 27U, .ToReg: AVR::R27 },
1251 { .FromReg: 28U, .ToReg: AVR::R29R28 },
1252 { .FromReg: 29U, .ToReg: AVR::R29 },
1253 { .FromReg: 30U, .ToReg: AVR::R31R30 },
1254 { .FromReg: 31U, .ToReg: AVR::R31 },
1255 { .FromReg: 32U, .ToReg: AVR::SPL },
1256 { .FromReg: 33U, .ToReg: AVR::SPH },
1257 { .FromReg: 88U, .ToReg: AVR::SREG },
1258};
1259extern const unsigned AVREHFlavour0Dwarf2LSize = std::size(AVREHFlavour0Dwarf2L);
1260
1261extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
1262 { .FromReg: AVR::SP, .ToReg: 32U },
1263 { .FromReg: AVR::SPH, .ToReg: 33U },
1264 { .FromReg: AVR::SPL, .ToReg: 32U },
1265 { .FromReg: AVR::SREG, .ToReg: 88U },
1266 { .FromReg: AVR::R0, .ToReg: 0U },
1267 { .FromReg: AVR::R1, .ToReg: 1U },
1268 { .FromReg: AVR::R2, .ToReg: 2U },
1269 { .FromReg: AVR::R3, .ToReg: 3U },
1270 { .FromReg: AVR::R4, .ToReg: 4U },
1271 { .FromReg: AVR::R5, .ToReg: 5U },
1272 { .FromReg: AVR::R6, .ToReg: 6U },
1273 { .FromReg: AVR::R7, .ToReg: 7U },
1274 { .FromReg: AVR::R8, .ToReg: 8U },
1275 { .FromReg: AVR::R9, .ToReg: 9U },
1276 { .FromReg: AVR::R10, .ToReg: 10U },
1277 { .FromReg: AVR::R11, .ToReg: 11U },
1278 { .FromReg: AVR::R12, .ToReg: 12U },
1279 { .FromReg: AVR::R13, .ToReg: 13U },
1280 { .FromReg: AVR::R14, .ToReg: 14U },
1281 { .FromReg: AVR::R15, .ToReg: 15U },
1282 { .FromReg: AVR::R16, .ToReg: 16U },
1283 { .FromReg: AVR::R17, .ToReg: 17U },
1284 { .FromReg: AVR::R18, .ToReg: 18U },
1285 { .FromReg: AVR::R19, .ToReg: 19U },
1286 { .FromReg: AVR::R20, .ToReg: 20U },
1287 { .FromReg: AVR::R21, .ToReg: 21U },
1288 { .FromReg: AVR::R22, .ToReg: 22U },
1289 { .FromReg: AVR::R23, .ToReg: 23U },
1290 { .FromReg: AVR::R24, .ToReg: 24U },
1291 { .FromReg: AVR::R25, .ToReg: 25U },
1292 { .FromReg: AVR::R26, .ToReg: 26U },
1293 { .FromReg: AVR::R27, .ToReg: 27U },
1294 { .FromReg: AVR::R28, .ToReg: 28U },
1295 { .FromReg: AVR::R29, .ToReg: 29U },
1296 { .FromReg: AVR::R30, .ToReg: 30U },
1297 { .FromReg: AVR::R31, .ToReg: 31U },
1298 { .FromReg: AVR::R1R0, .ToReg: 0U },
1299 { .FromReg: AVR::R3R2, .ToReg: 2U },
1300 { .FromReg: AVR::R5R4, .ToReg: 4U },
1301 { .FromReg: AVR::R7R6, .ToReg: 6U },
1302 { .FromReg: AVR::R9R8, .ToReg: 8U },
1303 { .FromReg: AVR::R10R9, .ToReg: 9U },
1304 { .FromReg: AVR::R11R10, .ToReg: 10U },
1305 { .FromReg: AVR::R12R11, .ToReg: 11U },
1306 { .FromReg: AVR::R13R12, .ToReg: 12U },
1307 { .FromReg: AVR::R14R13, .ToReg: 13U },
1308 { .FromReg: AVR::R15R14, .ToReg: 14U },
1309 { .FromReg: AVR::R16R15, .ToReg: 15U },
1310 { .FromReg: AVR::R17R16, .ToReg: 16U },
1311 { .FromReg: AVR::R18R17, .ToReg: 17U },
1312 { .FromReg: AVR::R19R18, .ToReg: 18U },
1313 { .FromReg: AVR::R20R19, .ToReg: 19U },
1314 { .FromReg: AVR::R21R20, .ToReg: 20U },
1315 { .FromReg: AVR::R22R21, .ToReg: 21U },
1316 { .FromReg: AVR::R23R22, .ToReg: 22U },
1317 { .FromReg: AVR::R24R23, .ToReg: 23U },
1318 { .FromReg: AVR::R25R24, .ToReg: 24U },
1319 { .FromReg: AVR::R26R25, .ToReg: 25U },
1320 { .FromReg: AVR::R27R26, .ToReg: 26U },
1321 { .FromReg: AVR::R29R28, .ToReg: 28U },
1322 { .FromReg: AVR::R31R30, .ToReg: 30U },
1323};
1324extern const unsigned AVRDwarfFlavour0L2DwarfSize = std::size(AVRDwarfFlavour0L2Dwarf);
1325
1326extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
1327 { .FromReg: AVR::SP, .ToReg: 32U },
1328 { .FromReg: AVR::SPH, .ToReg: 33U },
1329 { .FromReg: AVR::SPL, .ToReg: 32U },
1330 { .FromReg: AVR::SREG, .ToReg: 88U },
1331 { .FromReg: AVR::R0, .ToReg: 0U },
1332 { .FromReg: AVR::R1, .ToReg: 1U },
1333 { .FromReg: AVR::R2, .ToReg: 2U },
1334 { .FromReg: AVR::R3, .ToReg: 3U },
1335 { .FromReg: AVR::R4, .ToReg: 4U },
1336 { .FromReg: AVR::R5, .ToReg: 5U },
1337 { .FromReg: AVR::R6, .ToReg: 6U },
1338 { .FromReg: AVR::R7, .ToReg: 7U },
1339 { .FromReg: AVR::R8, .ToReg: 8U },
1340 { .FromReg: AVR::R9, .ToReg: 9U },
1341 { .FromReg: AVR::R10, .ToReg: 10U },
1342 { .FromReg: AVR::R11, .ToReg: 11U },
1343 { .FromReg: AVR::R12, .ToReg: 12U },
1344 { .FromReg: AVR::R13, .ToReg: 13U },
1345 { .FromReg: AVR::R14, .ToReg: 14U },
1346 { .FromReg: AVR::R15, .ToReg: 15U },
1347 { .FromReg: AVR::R16, .ToReg: 16U },
1348 { .FromReg: AVR::R17, .ToReg: 17U },
1349 { .FromReg: AVR::R18, .ToReg: 18U },
1350 { .FromReg: AVR::R19, .ToReg: 19U },
1351 { .FromReg: AVR::R20, .ToReg: 20U },
1352 { .FromReg: AVR::R21, .ToReg: 21U },
1353 { .FromReg: AVR::R22, .ToReg: 22U },
1354 { .FromReg: AVR::R23, .ToReg: 23U },
1355 { .FromReg: AVR::R24, .ToReg: 24U },
1356 { .FromReg: AVR::R25, .ToReg: 25U },
1357 { .FromReg: AVR::R26, .ToReg: 26U },
1358 { .FromReg: AVR::R27, .ToReg: 27U },
1359 { .FromReg: AVR::R28, .ToReg: 28U },
1360 { .FromReg: AVR::R29, .ToReg: 29U },
1361 { .FromReg: AVR::R30, .ToReg: 30U },
1362 { .FromReg: AVR::R31, .ToReg: 31U },
1363 { .FromReg: AVR::R1R0, .ToReg: 0U },
1364 { .FromReg: AVR::R3R2, .ToReg: 2U },
1365 { .FromReg: AVR::R5R4, .ToReg: 4U },
1366 { .FromReg: AVR::R7R6, .ToReg: 6U },
1367 { .FromReg: AVR::R9R8, .ToReg: 8U },
1368 { .FromReg: AVR::R10R9, .ToReg: 9U },
1369 { .FromReg: AVR::R11R10, .ToReg: 10U },
1370 { .FromReg: AVR::R12R11, .ToReg: 11U },
1371 { .FromReg: AVR::R13R12, .ToReg: 12U },
1372 { .FromReg: AVR::R14R13, .ToReg: 13U },
1373 { .FromReg: AVR::R15R14, .ToReg: 14U },
1374 { .FromReg: AVR::R16R15, .ToReg: 15U },
1375 { .FromReg: AVR::R17R16, .ToReg: 16U },
1376 { .FromReg: AVR::R18R17, .ToReg: 17U },
1377 { .FromReg: AVR::R19R18, .ToReg: 18U },
1378 { .FromReg: AVR::R20R19, .ToReg: 19U },
1379 { .FromReg: AVR::R21R20, .ToReg: 20U },
1380 { .FromReg: AVR::R22R21, .ToReg: 21U },
1381 { .FromReg: AVR::R23R22, .ToReg: 22U },
1382 { .FromReg: AVR::R24R23, .ToReg: 23U },
1383 { .FromReg: AVR::R25R24, .ToReg: 24U },
1384 { .FromReg: AVR::R26R25, .ToReg: 25U },
1385 { .FromReg: AVR::R27R26, .ToReg: 26U },
1386 { .FromReg: AVR::R29R28, .ToReg: 28U },
1387 { .FromReg: AVR::R31R30, .ToReg: 30U },
1388};
1389extern const unsigned AVREHFlavour0L2DwarfSize = std::size(AVREHFlavour0L2Dwarf);
1390
1391extern const uint16_t AVRRegEncodingTable[] = {
1392 0,
1393 16,
1394 33,
1395 32,
1396 14,
1397 0,
1398 1,
1399 2,
1400 3,
1401 4,
1402 5,
1403 6,
1404 7,
1405 8,
1406 9,
1407 10,
1408 11,
1409 12,
1410 13,
1411 14,
1412 15,
1413 16,
1414 17,
1415 18,
1416 19,
1417 20,
1418 21,
1419 22,
1420 23,
1421 24,
1422 25,
1423 26,
1424 27,
1425 28,
1426 29,
1427 30,
1428 31,
1429 0,
1430 1,
1431 2,
1432 3,
1433 4,
1434 9,
1435 5,
1436 11,
1437 6,
1438 13,
1439 7,
1440 15,
1441 8,
1442 17,
1443 9,
1444 19,
1445 10,
1446 21,
1447 11,
1448 23,
1449 12,
1450 25,
1451 13,
1452 14,
1453 15,
1454};
1455static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1456 RI->InitMCRegisterInfo(D: AVRRegDesc, NR: 62, RA, PC, C: AVRMCRegisterClassStorage.Classes, NC: 33, RURoots: AVRRegUnitRoots, NRU: 35, DL: AVRRegDiffLists, RUMS: AVRLaneMaskLists, Strings: AVRRegStrings, ClassStrings: AVRRegClassStrings, SubIndices: AVRSubRegIdxLists, NumIndices: 3,
1457RET: AVRRegEncodingTable, RUI: nullptr);
1458
1459 switch (DwarfFlavour) {
1460 default:
1461 llvm_unreachable("Unknown DWARF flavour");
1462 case 0:
1463 RI->mapDwarfRegsToLLVMRegs(Map: AVRDwarfFlavour0Dwarf2L, Size: AVRDwarfFlavour0Dwarf2LSize, isEH: false);
1464 break;
1465 }
1466 switch (EHFlavour) {
1467 default:
1468 llvm_unreachable("Unknown DWARF flavour");
1469 case 0:
1470 RI->mapDwarfRegsToLLVMRegs(Map: AVREHFlavour0Dwarf2L, Size: AVREHFlavour0Dwarf2LSize, isEH: true);
1471 break;
1472 }
1473 switch (DwarfFlavour) {
1474 default:
1475 llvm_unreachable("Unknown DWARF flavour");
1476 case 0:
1477 RI->mapLLVMRegsToDwarfRegs(Map: AVRDwarfFlavour0L2Dwarf, Size: AVRDwarfFlavour0L2DwarfSize, isEH: false);
1478 break;
1479 }
1480 switch (EHFlavour) {
1481 default:
1482 llvm_unreachable("Unknown DWARF flavour");
1483 case 0:
1484 RI->mapLLVMRegsToDwarfRegs(Map: AVREHFlavour0L2Dwarf, Size: AVREHFlavour0L2DwarfSize, isEH: true);
1485 break;
1486 }
1487}
1488
1489
1490} // namespace llvm
1491