1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t AVRRegDiffLists[] = {
12 /* 0 */ -2, 0,
13 /* 2 */ 2, -1, 0,
14 /* 5 */ -32, 1, 0,
15 /* 8 */ -31, 1, 0,
16 /* 11 */ -30, 1, 0,
17 /* 14 */ -29, 1, 0,
18 /* 17 */ -28, 1, 0,
19 /* 20 */ -27, 1, 0,
20 /* 23 */ -26, 1, 0,
21 /* 26 */ 27, 1, 0,
22 /* 29 */ 25, 0,
23 /* 31 */ 26, 0,
24 /* 33 */ 27, 0,
25 /* 35 */ 28, 0,
26 /* 37 */ 29, 0,
27 /* 39 */ 30, 0,
28 /* 41 */ 31, 0,
29 /* 43 */ 32, 0,
30};
31
32extern const LaneBitmask AVRLaneMaskLists[] = {
33 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
34 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
35};
36
37extern const uint16_t AVRSubRegIdxLists[] = {
38 /* 0 */ 2, 1,
39};
40
41
42#ifdef __GNUC__
43#pragma GCC diagnostic push
44#pragma GCC diagnostic ignored "-Woverlength-strings"
45#endif
46extern const char AVRRegStrings[] = {
47 /* 0 */ "R11R10\000"
48 /* 7 */ "R21R20\000"
49 /* 14 */ "R31R30\000"
50 /* 21 */ "R1R0\000"
51 /* 26 */ "R12R11\000"
52 /* 33 */ "R22R21\000"
53 /* 40 */ "R31\000"
54 /* 44 */ "R1\000"
55 /* 47 */ "R13R12\000"
56 /* 54 */ "R23R22\000"
57 /* 61 */ "R3R2\000"
58 /* 66 */ "R14R13\000"
59 /* 73 */ "R24R23\000"
60 /* 80 */ "R3\000"
61 /* 83 */ "R15R14\000"
62 /* 90 */ "R25R24\000"
63 /* 97 */ "R5R4\000"
64 /* 102 */ "R16R15\000"
65 /* 109 */ "R26R25\000"
66 /* 116 */ "R5\000"
67 /* 119 */ "R17R16\000"
68 /* 126 */ "R27R26\000"
69 /* 133 */ "R7R6\000"
70 /* 138 */ "R18R17\000"
71 /* 145 */ "R27\000"
72 /* 149 */ "R7\000"
73 /* 152 */ "R19R18\000"
74 /* 159 */ "R29R28\000"
75 /* 166 */ "R9R8\000"
76 /* 171 */ "R20R19\000"
77 /* 178 */ "R29\000"
78 /* 182 */ "R10R9\000"
79 /* 188 */ "SREG\000"
80 /* 193 */ "SPH\000"
81 /* 197 */ "SPL\000"
82 /* 201 */ "SP\000"
83};
84#ifdef __GNUC__
85#pragma GCC diagnostic pop
86#endif
87
88extern const MCRegisterDesc AVRRegDesc[] = { // Descriptors
89 { .Name: 6, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
90 { .Name: 201, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24576, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
91 { .Name: 193, .SubRegs: 1, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 4097, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
92 { .Name: 197, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 2, .RegUnits: 4096, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
93 { .Name: 188, .SubRegs: 1, .SuperRegs: 1, .SubRegIndices: 2, .RegUnits: 4098, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
94 { .Name: 23, .SubRegs: 1, .SuperRegs: 43, .SubRegIndices: 2, .RegUnits: 4099, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
95 { .Name: 44, .SubRegs: 1, .SuperRegs: 41, .SubRegIndices: 2, .RegUnits: 4100, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
96 { .Name: 63, .SubRegs: 1, .SuperRegs: 41, .SubRegIndices: 2, .RegUnits: 4101, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
97 { .Name: 80, .SubRegs: 1, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 4102, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
98 { .Name: 99, .SubRegs: 1, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 4103, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
99 { .Name: 116, .SubRegs: 1, .SuperRegs: 37, .SubRegIndices: 2, .RegUnits: 4104, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
100 { .Name: 135, .SubRegs: 1, .SuperRegs: 37, .SubRegIndices: 2, .RegUnits: 4105, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
101 { .Name: 149, .SubRegs: 1, .SuperRegs: 35, .SubRegIndices: 2, .RegUnits: 4106, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
102 { .Name: 168, .SubRegs: 1, .SuperRegs: 35, .SubRegIndices: 2, .RegUnits: 4107, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
103 { .Name: 185, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4108, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
104 { .Name: 3, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4109, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
105 { .Name: 29, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4110, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
106 { .Name: 50, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4111, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
107 { .Name: 69, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4112, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
108 { .Name: 86, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4113, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
109 { .Name: 105, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4114, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
110 { .Name: 122, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4115, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
111 { .Name: 141, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4116, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
112 { .Name: 155, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4117, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
113 { .Name: 174, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4118, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
114 { .Name: 10, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4119, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
115 { .Name: 36, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4120, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
116 { .Name: 57, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4121, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
117 { .Name: 76, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4122, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
118 { .Name: 93, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4123, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
119 { .Name: 112, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4124, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
120 { .Name: 129, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4125, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
121 { .Name: 145, .SubRegs: 1, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 4126, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
122 { .Name: 162, .SubRegs: 1, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 4127, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
123 { .Name: 178, .SubRegs: 1, .SuperRegs: 31, .SubRegIndices: 2, .RegUnits: 4128, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
124 { .Name: 17, .SubRegs: 1, .SuperRegs: 31, .SubRegIndices: 2, .RegUnits: 4129, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
125 { .Name: 40, .SubRegs: 1, .SuperRegs: 29, .SubRegIndices: 2, .RegUnits: 4130, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
126 { .Name: 21, .SubRegs: 5, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24579, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
127 { .Name: 61, .SubRegs: 8, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24581, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
128 { .Name: 97, .SubRegs: 11, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24583, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
129 { .Name: 133, .SubRegs: 14, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24585, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
130 { .Name: 166, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24587, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
131 { .Name: 182, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24588, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
132 { .Name: 0, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24589, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
133 { .Name: 26, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24590, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
134 { .Name: 47, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24591, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
135 { .Name: 66, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24592, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
136 { .Name: 83, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24593, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
137 { .Name: 102, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24594, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
138 { .Name: 119, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24595, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
139 { .Name: 138, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24596, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
140 { .Name: 152, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24597, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
141 { .Name: 171, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24598, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
142 { .Name: 7, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24599, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
143 { .Name: 33, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24600, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
144 { .Name: 54, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24601, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
145 { .Name: 73, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24602, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
146 { .Name: 90, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24603, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
147 { .Name: 109, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24604, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
148 { .Name: 126, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24605, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
149 { .Name: 159, .SubRegs: 20, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24607, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
150 { .Name: 14, .SubRegs: 23, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24609, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
151};
152
153extern const MCPhysReg AVRRegUnitRoots[][2] = {
154 { AVR::SPL },
155 { AVR::SPH },
156 { AVR::SREG },
157 { AVR::R0 },
158 { AVR::R1 },
159 { AVR::R2 },
160 { AVR::R3 },
161 { AVR::R4 },
162 { AVR::R5 },
163 { AVR::R6 },
164 { AVR::R7 },
165 { AVR::R8 },
166 { AVR::R9 },
167 { AVR::R10 },
168 { AVR::R11 },
169 { AVR::R12 },
170 { AVR::R13 },
171 { AVR::R14 },
172 { AVR::R15 },
173 { AVR::R16 },
174 { AVR::R17 },
175 { AVR::R18 },
176 { AVR::R19 },
177 { AVR::R20 },
178 { AVR::R21 },
179 { AVR::R22 },
180 { AVR::R23 },
181 { AVR::R24 },
182 { AVR::R25 },
183 { AVR::R26 },
184 { AVR::R27 },
185 { AVR::R28 },
186 { AVR::R29 },
187 { AVR::R30 },
188 { AVR::R31 },
189};
190
191namespace { // Register classes...
192 // GPR8 Register Class...
193 const MCPhysReg GPR8[] = {
194 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
195 };
196
197 // GPR8 Bit set.
198 const uint8_t GPR8Bits[] = {
199 0xe0, 0xff, 0xff, 0xff, 0x1f,
200 };
201
202 // GPR8NOZ Register Class...
203 const MCPhysReg GPR8NOZ[] = {
204 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
205 };
206
207 // GPR8NOZ Bit set.
208 const uint8_t GPR8NOZBits[] = {
209 0xe0, 0xff, 0xff, 0xff, 0x07,
210 };
211
212 // GPR8lo Register Class...
213 const MCPhysReg GPR8lo[] = {
214 AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
215 };
216
217 // GPR8lo Bit set.
218 const uint8_t GPR8loBits[] = {
219 0xe0, 0xff, 0x1f,
220 };
221
222 // LD8 Register Class...
223 const MCPhysReg LD8[] = {
224 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
225 };
226
227 // LD8 Bit set.
228 const uint8_t LD8Bits[] = {
229 0x00, 0x00, 0xe0, 0xff, 0x1f,
230 };
231
232 // GPR8NOZ_and_LD8 Register Class...
233 const MCPhysReg GPR8NOZ_and_LD8[] = {
234 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
235 };
236
237 // GPR8NOZ_and_LD8 Bit set.
238 const uint8_t GPR8NOZ_and_LD8Bits[] = {
239 0x00, 0x00, 0xe0, 0xff, 0x07,
240 };
241
242 // LD8lo Register Class...
243 const MCPhysReg LD8lo[] = {
244 AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16,
245 };
246
247 // LD8lo Bit set.
248 const uint8_t LD8loBits[] = {
249 0x00, 0x00, 0xe0, 0x1f,
250 };
251
252 // CCR Register Class...
253 const MCPhysReg CCR[] = {
254 AVR::SREG,
255 };
256
257 // CCR Bit set.
258 const uint8_t CCRBits[] = {
259 0x10,
260 };
261
262 // DREGS Register Class...
263 const MCPhysReg DREGS[] = {
264 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
265 };
266
267 // DREGS Bit set.
268 const uint8_t DREGSBits[] = {
269 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x3f,
270 };
271
272 // DREGSNOZ Register Class...
273 const MCPhysReg DREGSNOZ[] = {
274 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
275 };
276
277 // DREGSNOZ Bit set.
278 const uint8_t DREGSNOZBits[] = {
279 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x1f,
280 };
281
282 // DREGSMOVW Register Class...
283 const MCPhysReg DREGSMOVW[] = {
284 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
285 };
286
287 // DREGSMOVW Bit set.
288 const uint8_t DREGSMOVWBits[] = {
289 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x3a,
290 };
291
292 // DREGSMOVW_and_DREGSNOZ Register Class...
293 const MCPhysReg DREGSMOVW_and_DREGSNOZ[] = {
294 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
295 };
296
297 // DREGSMOVW_and_DREGSNOZ Bit set.
298 const uint8_t DREGSMOVW_and_DREGSNOZBits[] = {
299 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x1a,
300 };
301
302 // DREGS_with_sub_hi_in_LD8 Register Class...
303 const MCPhysReg DREGS_with_sub_hi_in_LD8[] = {
304 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
305 };
306
307 // DREGS_with_sub_hi_in_LD8 Bit set.
308 const uint8_t DREGS_with_sub_hi_in_LD8Bits[] = {
309 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
310 };
311
312 // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8 Register Class...
313 const MCPhysReg DREGSNOZ_and_DREGS_with_sub_hi_in_LD8[] = {
314 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
315 };
316
317 // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8 Bit set.
318 const uint8_t DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits[] = {
319 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f,
320 };
321
322 // DREGS_with_sub_lo_in_LD8 Register Class...
323 const MCPhysReg DREGS_with_sub_lo_in_LD8[] = {
324 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
325 };
326
327 // DREGS_with_sub_lo_in_LD8 Bit set.
328 const uint8_t DREGS_with_sub_lo_in_LD8Bits[] = {
329 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
330 };
331
332 // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8 Register Class...
333 const MCPhysReg DREGSNOZ_and_DREGS_with_sub_lo_in_LD8[] = {
334 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
335 };
336
337 // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8 Bit set.
338 const uint8_t DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits[] = {
339 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f,
340 };
341
342 // DREGS_with_sub_lo_in_GPR8lo Register Class...
343 const MCPhysReg DREGS_with_sub_lo_in_GPR8lo[] = {
344 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
345 };
346
347 // DREGS_with_sub_lo_in_GPR8lo Bit set.
348 const uint8_t DREGS_with_sub_lo_in_GPR8loBits[] = {
349 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01,
350 };
351
352 // DREGS_with_sub_hi_in_GPR8lo Register Class...
353 const MCPhysReg DREGS_with_sub_hi_in_GPR8lo[] = {
354 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R14R13, AVR::R12R11, AVR::R10R9,
355 };
356
357 // DREGS_with_sub_hi_in_GPR8lo Bit set.
358 const uint8_t DREGS_with_sub_hi_in_GPR8loBits[] = {
359 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff,
360 };
361
362 // DLDREGS Register Class...
363 const MCPhysReg DLDREGS[] = {
364 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16,
365 };
366
367 // DLDREGS Bit set.
368 const uint8_t DLDREGSBits[] = {
369 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x3a,
370 };
371
372 // DREGS_with_sub_hi_in_LD8lo Register Class...
373 const MCPhysReg DREGS_with_sub_hi_in_LD8lo[] = {
374 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
375 };
376
377 // DREGS_with_sub_hi_in_LD8lo Bit set.
378 const uint8_t DREGS_with_sub_hi_in_LD8loBits[] = {
379 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
380 };
381
382 // DREGS_with_sub_lo_in_LD8lo Register Class...
383 const MCPhysReg DREGS_with_sub_lo_in_LD8lo[] = {
384 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
385 };
386
387 // DREGS_with_sub_lo_in_LD8lo Bit set.
388 const uint8_t DREGS_with_sub_lo_in_LD8loBits[] = {
389 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
390 };
391
392 // DREGSlo Register Class...
393 const MCPhysReg DREGSlo[] = {
394 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
395 };
396
397 // DREGSlo Bit set.
398 const uint8_t DREGSloBits[] = {
399 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab,
400 };
401
402 // DLDREGS_and_DREGSNOZ Register Class...
403 const MCPhysReg DLDREGS_and_DREGSNOZ[] = {
404 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16,
405 };
406
407 // DLDREGS_and_DREGSNOZ Bit set.
408 const uint8_t DLDREGS_and_DREGSNOZBits[] = {
409 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x1a,
410 };
411
412 // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Register Class...
413 const MCPhysReg DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8[] = {
414 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17,
415 };
416
417 // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Bit set.
418 const uint8_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits[] = {
419 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
420 };
421
422 // DREGSLD8lo Register Class...
423 const MCPhysReg DREGSLD8lo[] = {
424 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16,
425 };
426
427 // DREGSLD8lo Bit set.
428 const uint8_t DREGSLD8loBits[] = {
429 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
430 };
431
432 // IWREGS Register Class...
433 const MCPhysReg IWREGS[] = {
434 AVR::R25R24, AVR::R31R30, AVR::R27R26, AVR::R29R28,
435 };
436
437 // IWREGS Bit set.
438 const uint8_t IWREGSBits[] = {
439 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a,
440 };
441
442 // DREGSNOZ_and_IWREGS Register Class...
443 const MCPhysReg DREGSNOZ_and_IWREGS[] = {
444 AVR::R25R24, AVR::R27R26, AVR::R29R28,
445 };
446
447 // DREGSNOZ_and_IWREGS Bit set.
448 const uint8_t DREGSNOZ_and_IWREGSBits[] = {
449 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,
450 };
451
452 // PTRREGS Register Class...
453 const MCPhysReg PTRREGS[] = {
454 AVR::R27R26, AVR::R29R28, AVR::R31R30,
455 };
456
457 // PTRREGS Bit set.
458 const uint8_t PTRREGSBits[] = {
459 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
460 };
461
462 // DREGSNOZ_and_PTRREGS Register Class...
463 const MCPhysReg DREGSNOZ_and_PTRREGS[] = {
464 AVR::R27R26, AVR::R29R28,
465 };
466
467 // DREGSNOZ_and_PTRREGS Bit set.
468 const uint8_t DREGSNOZ_and_PTRREGSBits[] = {
469 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
470 };
471
472 // PTRDISPREGS Register Class...
473 const MCPhysReg PTRDISPREGS[] = {
474 AVR::R31R30, AVR::R29R28,
475 };
476
477 // PTRDISPREGS Bit set.
478 const uint8_t PTRDISPREGSBits[] = {
479 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
480 };
481
482 // DREGSNOZ_and_PTRDISPREGS Register Class...
483 const MCPhysReg DREGSNOZ_and_PTRDISPREGS[] = {
484 AVR::R29R28,
485 };
486
487 // DREGSNOZ_and_PTRDISPREGS Bit set.
488 const uint8_t DREGSNOZ_and_PTRDISPREGSBits[] = {
489 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
490 };
491
492 // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Register Class...
493 const MCPhysReg DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo[] = {
494 AVR::R16R15,
495 };
496
497 // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Bit set.
498 const uint8_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits[] = {
499 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
500 };
501
502 // GPRSP Register Class...
503 const MCPhysReg GPRSP[] = {
504 AVR::SP,
505 };
506
507 // GPRSP Bit set.
508 const uint8_t GPRSPBits[] = {
509 0x02,
510 };
511
512 // ZREG Register Class...
513 const MCPhysReg ZREG[] = {
514 AVR::R31R30,
515 };
516
517 // ZREG Bit set.
518 const uint8_t ZREGBits[] = {
519 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
520 };
521
522} // end anonymous namespace
523
524
525#ifdef __GNUC__
526#pragma GCC diagnostic push
527#pragma GCC diagnostic ignored "-Woverlength-strings"
528#endif
529extern const char AVRRegClassStrings[] = {
530 /* 0 */ "GPR8NOZ_and_LD8\000"
531 /* 16 */ "DREGSNOZ_and_DREGS_with_sub_hi_in_LD8\000"
532 /* 54 */ "DREGSNOZ_and_DREGS_with_sub_lo_in_LD8\000"
533 /* 92 */ "DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8\000"
534 /* 148 */ "GPR8\000"
535 /* 153 */ "ZREG\000"
536 /* 158 */ "GPRSP\000"
537 /* 164 */ "CCR\000"
538 /* 168 */ "DLDREGS\000"
539 /* 176 */ "DREGSNOZ_and_PTRDISPREGS\000"
540 /* 201 */ "DREGSNOZ_and_PTRREGS\000"
541 /* 222 */ "DREGSNOZ_and_IWREGS\000"
542 /* 242 */ "DREGSMOVW\000"
543 /* 252 */ "GPR8NOZ\000"
544 /* 260 */ "DLDREGS_and_DREGSNOZ\000"
545 /* 281 */ "DREGSMOVW_and_DREGSNOZ\000"
546 /* 304 */ "DREGSLD8lo\000"
547 /* 315 */ "DREGS_with_sub_hi_in_LD8lo\000"
548 /* 342 */ "DREGS_with_sub_lo_in_LD8lo\000"
549 /* 369 */ "DREGS_with_sub_hi_in_GPR8lo\000"
550 /* 397 */ "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo\000"
551 /* 454 */ "DREGSlo\000"
552};
553#ifdef __GNUC__
554#pragma GCC diagnostic pop
555#endif
556
557extern const MCRegisterClass AVRMCRegisterClasses[] = {
558 { .RegsBegin: GPR8, .RegSet: GPR8Bits, .NameIdx: 148, .RegsSize: 32, .RegSetSize: sizeof(GPR8Bits), .ID: AVR::GPR8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
559 { .RegsBegin: GPR8NOZ, .RegSet: GPR8NOZBits, .NameIdx: 252, .RegsSize: 30, .RegSetSize: sizeof(GPR8NOZBits), .ID: AVR::GPR8NOZRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
560 { .RegsBegin: GPR8lo, .RegSet: GPR8loBits, .NameIdx: 390, .RegsSize: 16, .RegSetSize: sizeof(GPR8loBits), .ID: AVR::GPR8loRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
561 { .RegsBegin: LD8, .RegSet: LD8Bits, .NameIdx: 12, .RegsSize: 16, .RegSetSize: sizeof(LD8Bits), .ID: AVR::LD8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
562 { .RegsBegin: GPR8NOZ_and_LD8, .RegSet: GPR8NOZ_and_LD8Bits, .NameIdx: 0, .RegsSize: 14, .RegSetSize: sizeof(GPR8NOZ_and_LD8Bits), .ID: AVR::GPR8NOZ_and_LD8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
563 { .RegsBegin: LD8lo, .RegSet: LD8loBits, .NameIdx: 309, .RegsSize: 8, .RegSetSize: sizeof(LD8loBits), .ID: AVR::LD8loRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
564 { .RegsBegin: CCR, .RegSet: CCRBits, .NameIdx: 164, .RegsSize: 1, .RegSetSize: sizeof(CCRBits), .ID: AVR::CCRRegClassID, .RegSizeInBits: 8, .CopyCost: 255, .Allocatable: true, .BaseClass: false },
565 { .RegsBegin: DREGS, .RegSet: DREGSBits, .NameIdx: 170, .RegsSize: 25, .RegSetSize: sizeof(DREGSBits), .ID: AVR::DREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
566 { .RegsBegin: DREGSNOZ, .RegSet: DREGSNOZBits, .NameIdx: 272, .RegsSize: 24, .RegSetSize: sizeof(DREGSNOZBits), .ID: AVR::DREGSNOZRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
567 { .RegsBegin: DREGSMOVW, .RegSet: DREGSMOVWBits, .NameIdx: 242, .RegsSize: 16, .RegSetSize: sizeof(DREGSMOVWBits), .ID: AVR::DREGSMOVWRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
568 { .RegsBegin: DREGSMOVW_and_DREGSNOZ, .RegSet: DREGSMOVW_and_DREGSNOZBits, .NameIdx: 281, .RegsSize: 15, .RegSetSize: sizeof(DREGSMOVW_and_DREGSNOZBits), .ID: AVR::DREGSMOVW_and_DREGSNOZRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
569 { .RegsBegin: DREGS_with_sub_hi_in_LD8, .RegSet: DREGS_with_sub_hi_in_LD8Bits, .NameIdx: 29, .RegsSize: 14, .RegSetSize: sizeof(DREGS_with_sub_hi_in_LD8Bits), .ID: AVR::DREGS_with_sub_hi_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
570 { .RegsBegin: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8, .RegSet: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits, .NameIdx: 16, .RegsSize: 13, .RegSetSize: sizeof(DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits), .ID: AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
571 { .RegsBegin: DREGS_with_sub_lo_in_LD8, .RegSet: DREGS_with_sub_lo_in_LD8Bits, .NameIdx: 67, .RegsSize: 13, .RegSetSize: sizeof(DREGS_with_sub_lo_in_LD8Bits), .ID: AVR::DREGS_with_sub_lo_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
572 { .RegsBegin: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8, .RegSet: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits, .NameIdx: 54, .RegsSize: 12, .RegSetSize: sizeof(DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits), .ID: AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
573 { .RegsBegin: DREGS_with_sub_lo_in_GPR8lo, .RegSet: DREGS_with_sub_lo_in_GPR8loBits, .NameIdx: 426, .RegsSize: 12, .RegSetSize: sizeof(DREGS_with_sub_lo_in_GPR8loBits), .ID: AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
574 { .RegsBegin: DREGS_with_sub_hi_in_GPR8lo, .RegSet: DREGS_with_sub_hi_in_GPR8loBits, .NameIdx: 369, .RegsSize: 11, .RegSetSize: sizeof(DREGS_with_sub_hi_in_GPR8loBits), .ID: AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
575 { .RegsBegin: DLDREGS, .RegSet: DLDREGSBits, .NameIdx: 168, .RegsSize: 8, .RegSetSize: sizeof(DLDREGSBits), .ID: AVR::DLDREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
576 { .RegsBegin: DREGS_with_sub_hi_in_LD8lo, .RegSet: DREGS_with_sub_hi_in_LD8loBits, .NameIdx: 315, .RegsSize: 8, .RegSetSize: sizeof(DREGS_with_sub_hi_in_LD8loBits), .ID: AVR::DREGS_with_sub_hi_in_LD8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
577 { .RegsBegin: DREGS_with_sub_lo_in_LD8lo, .RegSet: DREGS_with_sub_lo_in_LD8loBits, .NameIdx: 342, .RegsSize: 8, .RegSetSize: sizeof(DREGS_with_sub_lo_in_LD8loBits), .ID: AVR::DREGS_with_sub_lo_in_LD8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
578 { .RegsBegin: DREGSlo, .RegSet: DREGSloBits, .NameIdx: 454, .RegsSize: 8, .RegSetSize: sizeof(DREGSloBits), .ID: AVR::DREGSloRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
579 { .RegsBegin: DLDREGS_and_DREGSNOZ, .RegSet: DLDREGS_and_DREGSNOZBits, .NameIdx: 260, .RegsSize: 7, .RegSetSize: sizeof(DLDREGS_and_DREGSNOZBits), .ID: AVR::DLDREGS_and_DREGSNOZRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
580 { .RegsBegin: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8, .RegSet: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits, .NameIdx: 92, .RegsSize: 7, .RegSetSize: sizeof(DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits), .ID: AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
581 { .RegsBegin: DREGSLD8lo, .RegSet: DREGSLD8loBits, .NameIdx: 304, .RegsSize: 4, .RegSetSize: sizeof(DREGSLD8loBits), .ID: AVR::DREGSLD8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
582 { .RegsBegin: IWREGS, .RegSet: IWREGSBits, .NameIdx: 235, .RegsSize: 4, .RegSetSize: sizeof(IWREGSBits), .ID: AVR::IWREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
583 { .RegsBegin: DREGSNOZ_and_IWREGS, .RegSet: DREGSNOZ_and_IWREGSBits, .NameIdx: 222, .RegsSize: 3, .RegSetSize: sizeof(DREGSNOZ_and_IWREGSBits), .ID: AVR::DREGSNOZ_and_IWREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
584 { .RegsBegin: PTRREGS, .RegSet: PTRREGSBits, .NameIdx: 214, .RegsSize: 3, .RegSetSize: sizeof(PTRREGSBits), .ID: AVR::PTRREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
585 { .RegsBegin: DREGSNOZ_and_PTRREGS, .RegSet: DREGSNOZ_and_PTRREGSBits, .NameIdx: 201, .RegsSize: 2, .RegSetSize: sizeof(DREGSNOZ_and_PTRREGSBits), .ID: AVR::DREGSNOZ_and_PTRREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
586 { .RegsBegin: PTRDISPREGS, .RegSet: PTRDISPREGSBits, .NameIdx: 189, .RegsSize: 2, .RegSetSize: sizeof(PTRDISPREGSBits), .ID: AVR::PTRDISPREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
587 { .RegsBegin: DREGSNOZ_and_PTRDISPREGS, .RegSet: DREGSNOZ_and_PTRDISPREGSBits, .NameIdx: 176, .RegsSize: 1, .RegSetSize: sizeof(DREGSNOZ_and_PTRDISPREGSBits), .ID: AVR::DREGSNOZ_and_PTRDISPREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
588 { .RegsBegin: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo, .RegSet: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits, .NameIdx: 397, .RegsSize: 1, .RegSetSize: sizeof(DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits), .ID: AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
589 { .RegsBegin: GPRSP, .RegSet: GPRSPBits, .NameIdx: 158, .RegsSize: 1, .RegSetSize: sizeof(GPRSPBits), .ID: AVR::GPRSPRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
590 { .RegsBegin: ZREG, .RegSet: ZREGBits, .NameIdx: 153, .RegsSize: 1, .RegSetSize: sizeof(ZREGBits), .ID: AVR::ZREGRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
591};
592
593// AVR Dwarf<->LLVM register mappings.
594extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
595 { .FromReg: 0U, .ToReg: AVR::R1R0 },
596 { .FromReg: 1U, .ToReg: AVR::R1 },
597 { .FromReg: 2U, .ToReg: AVR::R3R2 },
598 { .FromReg: 3U, .ToReg: AVR::R3 },
599 { .FromReg: 4U, .ToReg: AVR::R5R4 },
600 { .FromReg: 5U, .ToReg: AVR::R5 },
601 { .FromReg: 6U, .ToReg: AVR::R7R6 },
602 { .FromReg: 7U, .ToReg: AVR::R7 },
603 { .FromReg: 8U, .ToReg: AVR::R9R8 },
604 { .FromReg: 9U, .ToReg: AVR::R10R9 },
605 { .FromReg: 10U, .ToReg: AVR::R11R10 },
606 { .FromReg: 11U, .ToReg: AVR::R12R11 },
607 { .FromReg: 12U, .ToReg: AVR::R13R12 },
608 { .FromReg: 13U, .ToReg: AVR::R14R13 },
609 { .FromReg: 14U, .ToReg: AVR::R15R14 },
610 { .FromReg: 15U, .ToReg: AVR::R16R15 },
611 { .FromReg: 16U, .ToReg: AVR::R17R16 },
612 { .FromReg: 17U, .ToReg: AVR::R18R17 },
613 { .FromReg: 18U, .ToReg: AVR::R19R18 },
614 { .FromReg: 19U, .ToReg: AVR::R20R19 },
615 { .FromReg: 20U, .ToReg: AVR::R21R20 },
616 { .FromReg: 21U, .ToReg: AVR::R22R21 },
617 { .FromReg: 22U, .ToReg: AVR::R23R22 },
618 { .FromReg: 23U, .ToReg: AVR::R24R23 },
619 { .FromReg: 24U, .ToReg: AVR::R25R24 },
620 { .FromReg: 25U, .ToReg: AVR::R26R25 },
621 { .FromReg: 26U, .ToReg: AVR::R27R26 },
622 { .FromReg: 27U, .ToReg: AVR::R27 },
623 { .FromReg: 28U, .ToReg: AVR::R29R28 },
624 { .FromReg: 29U, .ToReg: AVR::R29 },
625 { .FromReg: 30U, .ToReg: AVR::R31R30 },
626 { .FromReg: 31U, .ToReg: AVR::R31 },
627 { .FromReg: 32U, .ToReg: AVR::SPL },
628 { .FromReg: 33U, .ToReg: AVR::SPH },
629 { .FromReg: 88U, .ToReg: AVR::SREG },
630};
631extern const unsigned AVRDwarfFlavour0Dwarf2LSize = std::size(AVRDwarfFlavour0Dwarf2L);
632
633extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
634 { .FromReg: 0U, .ToReg: AVR::R1R0 },
635 { .FromReg: 1U, .ToReg: AVR::R1 },
636 { .FromReg: 2U, .ToReg: AVR::R3R2 },
637 { .FromReg: 3U, .ToReg: AVR::R3 },
638 { .FromReg: 4U, .ToReg: AVR::R5R4 },
639 { .FromReg: 5U, .ToReg: AVR::R5 },
640 { .FromReg: 6U, .ToReg: AVR::R7R6 },
641 { .FromReg: 7U, .ToReg: AVR::R7 },
642 { .FromReg: 8U, .ToReg: AVR::R9R8 },
643 { .FromReg: 9U, .ToReg: AVR::R10R9 },
644 { .FromReg: 10U, .ToReg: AVR::R11R10 },
645 { .FromReg: 11U, .ToReg: AVR::R12R11 },
646 { .FromReg: 12U, .ToReg: AVR::R13R12 },
647 { .FromReg: 13U, .ToReg: AVR::R14R13 },
648 { .FromReg: 14U, .ToReg: AVR::R15R14 },
649 { .FromReg: 15U, .ToReg: AVR::R16R15 },
650 { .FromReg: 16U, .ToReg: AVR::R17R16 },
651 { .FromReg: 17U, .ToReg: AVR::R18R17 },
652 { .FromReg: 18U, .ToReg: AVR::R19R18 },
653 { .FromReg: 19U, .ToReg: AVR::R20R19 },
654 { .FromReg: 20U, .ToReg: AVR::R21R20 },
655 { .FromReg: 21U, .ToReg: AVR::R22R21 },
656 { .FromReg: 22U, .ToReg: AVR::R23R22 },
657 { .FromReg: 23U, .ToReg: AVR::R24R23 },
658 { .FromReg: 24U, .ToReg: AVR::R25R24 },
659 { .FromReg: 25U, .ToReg: AVR::R26R25 },
660 { .FromReg: 26U, .ToReg: AVR::R27R26 },
661 { .FromReg: 27U, .ToReg: AVR::R27 },
662 { .FromReg: 28U, .ToReg: AVR::R29R28 },
663 { .FromReg: 29U, .ToReg: AVR::R29 },
664 { .FromReg: 30U, .ToReg: AVR::R31R30 },
665 { .FromReg: 31U, .ToReg: AVR::R31 },
666 { .FromReg: 32U, .ToReg: AVR::SPL },
667 { .FromReg: 33U, .ToReg: AVR::SPH },
668 { .FromReg: 88U, .ToReg: AVR::SREG },
669};
670extern const unsigned AVREHFlavour0Dwarf2LSize = std::size(AVREHFlavour0Dwarf2L);
671
672extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
673 { .FromReg: AVR::SP, .ToReg: 32U },
674 { .FromReg: AVR::SPH, .ToReg: 33U },
675 { .FromReg: AVR::SPL, .ToReg: 32U },
676 { .FromReg: AVR::SREG, .ToReg: 88U },
677 { .FromReg: AVR::R0, .ToReg: 0U },
678 { .FromReg: AVR::R1, .ToReg: 1U },
679 { .FromReg: AVR::R2, .ToReg: 2U },
680 { .FromReg: AVR::R3, .ToReg: 3U },
681 { .FromReg: AVR::R4, .ToReg: 4U },
682 { .FromReg: AVR::R5, .ToReg: 5U },
683 { .FromReg: AVR::R6, .ToReg: 6U },
684 { .FromReg: AVR::R7, .ToReg: 7U },
685 { .FromReg: AVR::R8, .ToReg: 8U },
686 { .FromReg: AVR::R9, .ToReg: 9U },
687 { .FromReg: AVR::R10, .ToReg: 10U },
688 { .FromReg: AVR::R11, .ToReg: 11U },
689 { .FromReg: AVR::R12, .ToReg: 12U },
690 { .FromReg: AVR::R13, .ToReg: 13U },
691 { .FromReg: AVR::R14, .ToReg: 14U },
692 { .FromReg: AVR::R15, .ToReg: 15U },
693 { .FromReg: AVR::R16, .ToReg: 16U },
694 { .FromReg: AVR::R17, .ToReg: 17U },
695 { .FromReg: AVR::R18, .ToReg: 18U },
696 { .FromReg: AVR::R19, .ToReg: 19U },
697 { .FromReg: AVR::R20, .ToReg: 20U },
698 { .FromReg: AVR::R21, .ToReg: 21U },
699 { .FromReg: AVR::R22, .ToReg: 22U },
700 { .FromReg: AVR::R23, .ToReg: 23U },
701 { .FromReg: AVR::R24, .ToReg: 24U },
702 { .FromReg: AVR::R25, .ToReg: 25U },
703 { .FromReg: AVR::R26, .ToReg: 26U },
704 { .FromReg: AVR::R27, .ToReg: 27U },
705 { .FromReg: AVR::R28, .ToReg: 28U },
706 { .FromReg: AVR::R29, .ToReg: 29U },
707 { .FromReg: AVR::R30, .ToReg: 30U },
708 { .FromReg: AVR::R31, .ToReg: 31U },
709 { .FromReg: AVR::R1R0, .ToReg: 0U },
710 { .FromReg: AVR::R3R2, .ToReg: 2U },
711 { .FromReg: AVR::R5R4, .ToReg: 4U },
712 { .FromReg: AVR::R7R6, .ToReg: 6U },
713 { .FromReg: AVR::R9R8, .ToReg: 8U },
714 { .FromReg: AVR::R10R9, .ToReg: 9U },
715 { .FromReg: AVR::R11R10, .ToReg: 10U },
716 { .FromReg: AVR::R12R11, .ToReg: 11U },
717 { .FromReg: AVR::R13R12, .ToReg: 12U },
718 { .FromReg: AVR::R14R13, .ToReg: 13U },
719 { .FromReg: AVR::R15R14, .ToReg: 14U },
720 { .FromReg: AVR::R16R15, .ToReg: 15U },
721 { .FromReg: AVR::R17R16, .ToReg: 16U },
722 { .FromReg: AVR::R18R17, .ToReg: 17U },
723 { .FromReg: AVR::R19R18, .ToReg: 18U },
724 { .FromReg: AVR::R20R19, .ToReg: 19U },
725 { .FromReg: AVR::R21R20, .ToReg: 20U },
726 { .FromReg: AVR::R22R21, .ToReg: 21U },
727 { .FromReg: AVR::R23R22, .ToReg: 22U },
728 { .FromReg: AVR::R24R23, .ToReg: 23U },
729 { .FromReg: AVR::R25R24, .ToReg: 24U },
730 { .FromReg: AVR::R26R25, .ToReg: 25U },
731 { .FromReg: AVR::R27R26, .ToReg: 26U },
732 { .FromReg: AVR::R29R28, .ToReg: 28U },
733 { .FromReg: AVR::R31R30, .ToReg: 30U },
734};
735extern const unsigned AVRDwarfFlavour0L2DwarfSize = std::size(AVRDwarfFlavour0L2Dwarf);
736
737extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
738 { .FromReg: AVR::SP, .ToReg: 32U },
739 { .FromReg: AVR::SPH, .ToReg: 33U },
740 { .FromReg: AVR::SPL, .ToReg: 32U },
741 { .FromReg: AVR::SREG, .ToReg: 88U },
742 { .FromReg: AVR::R0, .ToReg: 0U },
743 { .FromReg: AVR::R1, .ToReg: 1U },
744 { .FromReg: AVR::R2, .ToReg: 2U },
745 { .FromReg: AVR::R3, .ToReg: 3U },
746 { .FromReg: AVR::R4, .ToReg: 4U },
747 { .FromReg: AVR::R5, .ToReg: 5U },
748 { .FromReg: AVR::R6, .ToReg: 6U },
749 { .FromReg: AVR::R7, .ToReg: 7U },
750 { .FromReg: AVR::R8, .ToReg: 8U },
751 { .FromReg: AVR::R9, .ToReg: 9U },
752 { .FromReg: AVR::R10, .ToReg: 10U },
753 { .FromReg: AVR::R11, .ToReg: 11U },
754 { .FromReg: AVR::R12, .ToReg: 12U },
755 { .FromReg: AVR::R13, .ToReg: 13U },
756 { .FromReg: AVR::R14, .ToReg: 14U },
757 { .FromReg: AVR::R15, .ToReg: 15U },
758 { .FromReg: AVR::R16, .ToReg: 16U },
759 { .FromReg: AVR::R17, .ToReg: 17U },
760 { .FromReg: AVR::R18, .ToReg: 18U },
761 { .FromReg: AVR::R19, .ToReg: 19U },
762 { .FromReg: AVR::R20, .ToReg: 20U },
763 { .FromReg: AVR::R21, .ToReg: 21U },
764 { .FromReg: AVR::R22, .ToReg: 22U },
765 { .FromReg: AVR::R23, .ToReg: 23U },
766 { .FromReg: AVR::R24, .ToReg: 24U },
767 { .FromReg: AVR::R25, .ToReg: 25U },
768 { .FromReg: AVR::R26, .ToReg: 26U },
769 { .FromReg: AVR::R27, .ToReg: 27U },
770 { .FromReg: AVR::R28, .ToReg: 28U },
771 { .FromReg: AVR::R29, .ToReg: 29U },
772 { .FromReg: AVR::R30, .ToReg: 30U },
773 { .FromReg: AVR::R31, .ToReg: 31U },
774 { .FromReg: AVR::R1R0, .ToReg: 0U },
775 { .FromReg: AVR::R3R2, .ToReg: 2U },
776 { .FromReg: AVR::R5R4, .ToReg: 4U },
777 { .FromReg: AVR::R7R6, .ToReg: 6U },
778 { .FromReg: AVR::R9R8, .ToReg: 8U },
779 { .FromReg: AVR::R10R9, .ToReg: 9U },
780 { .FromReg: AVR::R11R10, .ToReg: 10U },
781 { .FromReg: AVR::R12R11, .ToReg: 11U },
782 { .FromReg: AVR::R13R12, .ToReg: 12U },
783 { .FromReg: AVR::R14R13, .ToReg: 13U },
784 { .FromReg: AVR::R15R14, .ToReg: 14U },
785 { .FromReg: AVR::R16R15, .ToReg: 15U },
786 { .FromReg: AVR::R17R16, .ToReg: 16U },
787 { .FromReg: AVR::R18R17, .ToReg: 17U },
788 { .FromReg: AVR::R19R18, .ToReg: 18U },
789 { .FromReg: AVR::R20R19, .ToReg: 19U },
790 { .FromReg: AVR::R21R20, .ToReg: 20U },
791 { .FromReg: AVR::R22R21, .ToReg: 21U },
792 { .FromReg: AVR::R23R22, .ToReg: 22U },
793 { .FromReg: AVR::R24R23, .ToReg: 23U },
794 { .FromReg: AVR::R25R24, .ToReg: 24U },
795 { .FromReg: AVR::R26R25, .ToReg: 25U },
796 { .FromReg: AVR::R27R26, .ToReg: 26U },
797 { .FromReg: AVR::R29R28, .ToReg: 28U },
798 { .FromReg: AVR::R31R30, .ToReg: 30U },
799};
800extern const unsigned AVREHFlavour0L2DwarfSize = std::size(AVREHFlavour0L2Dwarf);
801
802extern const uint16_t AVRRegEncodingTable[] = {
803 0,
804 16,
805 33,
806 32,
807 14,
808 0,
809 1,
810 2,
811 3,
812 4,
813 5,
814 6,
815 7,
816 8,
817 9,
818 10,
819 11,
820 12,
821 13,
822 14,
823 15,
824 16,
825 17,
826 18,
827 19,
828 20,
829 21,
830 22,
831 23,
832 24,
833 25,
834 26,
835 27,
836 28,
837 29,
838 30,
839 31,
840 0,
841 1,
842 2,
843 3,
844 4,
845 9,
846 5,
847 11,
848 6,
849 13,
850 7,
851 15,
852 8,
853 17,
854 9,
855 19,
856 10,
857 21,
858 11,
859 23,
860 12,
861 25,
862 13,
863 14,
864 15,
865};
866static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
867 RI->InitMCRegisterInfo(D: AVRRegDesc, NR: 62, RA, PC, C: AVRMCRegisterClasses, NC: 33, RURoots: AVRRegUnitRoots, NRU: 35, DL: AVRRegDiffLists, RUMS: AVRLaneMaskLists, Strings: AVRRegStrings, ClassStrings: AVRRegClassStrings, SubIndices: AVRSubRegIdxLists, NumIndices: 3,
868RET: AVRRegEncodingTable);
869
870 switch (DwarfFlavour) {
871 default:
872 llvm_unreachable("Unknown DWARF flavour");
873 case 0:
874 RI->mapDwarfRegsToLLVMRegs(Map: AVRDwarfFlavour0Dwarf2L, Size: AVRDwarfFlavour0Dwarf2LSize, isEH: false);
875 break;
876 }
877 switch (EHFlavour) {
878 default:
879 llvm_unreachable("Unknown DWARF flavour");
880 case 0:
881 RI->mapDwarfRegsToLLVMRegs(Map: AVREHFlavour0Dwarf2L, Size: AVREHFlavour0Dwarf2LSize, isEH: true);
882 break;
883 }
884 switch (DwarfFlavour) {
885 default:
886 llvm_unreachable("Unknown DWARF flavour");
887 case 0:
888 RI->mapLLVMRegsToDwarfRegs(Map: AVRDwarfFlavour0L2Dwarf, Size: AVRDwarfFlavour0L2DwarfSize, isEH: false);
889 break;
890 }
891 switch (EHFlavour) {
892 default:
893 llvm_unreachable("Unknown DWARF flavour");
894 case 0:
895 RI->mapLLVMRegsToDwarfRegs(Map: AVREHFlavour0L2Dwarf, Size: AVREHFlavour0L2DwarfSize, isEH: true);
896 break;
897 }
898}
899
900} // end namespace llvm
901
902