1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t AVRRegDiffLists[] = {
12 /* 0 */ -2, 0,
13 /* 2 */ 2, -1, 0,
14 /* 5 */ -32, 1, 0,
15 /* 8 */ -31, 1, 0,
16 /* 11 */ -30, 1, 0,
17 /* 14 */ -29, 1, 0,
18 /* 17 */ -28, 1, 0,
19 /* 20 */ -27, 1, 0,
20 /* 23 */ -26, 1, 0,
21 /* 26 */ 27, 1, 0,
22 /* 29 */ 25, 0,
23 /* 31 */ 26, 0,
24 /* 33 */ 27, 0,
25 /* 35 */ 28, 0,
26 /* 37 */ 29, 0,
27 /* 39 */ 30, 0,
28 /* 41 */ 31, 0,
29 /* 43 */ 32, 0,
30};
31
32extern const LaneBitmask AVRLaneMaskLists[] = {
33 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
34 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
35};
36
37extern const uint16_t AVRSubRegIdxLists[] = {
38 /* 0 */ 2, 1,
39};
40
41
42#ifdef __GNUC__
43#pragma GCC diagnostic push
44#pragma GCC diagnostic ignored "-Woverlength-strings"
45#endif
46extern const char AVRRegStrings[] = {
47 /* 0 */ "R11R10\000"
48 /* 7 */ "R21R20\000"
49 /* 14 */ "R31R30\000"
50 /* 21 */ "R1R0\000"
51 /* 26 */ "R12R11\000"
52 /* 33 */ "R22R21\000"
53 /* 40 */ "R31\000"
54 /* 44 */ "R1\000"
55 /* 47 */ "R13R12\000"
56 /* 54 */ "R23R22\000"
57 /* 61 */ "R3R2\000"
58 /* 66 */ "R14R13\000"
59 /* 73 */ "R24R23\000"
60 /* 80 */ "R3\000"
61 /* 83 */ "R15R14\000"
62 /* 90 */ "R25R24\000"
63 /* 97 */ "R5R4\000"
64 /* 102 */ "R16R15\000"
65 /* 109 */ "R26R25\000"
66 /* 116 */ "R5\000"
67 /* 119 */ "R17R16\000"
68 /* 126 */ "R27R26\000"
69 /* 133 */ "R7R6\000"
70 /* 138 */ "R18R17\000"
71 /* 145 */ "R27\000"
72 /* 149 */ "R7\000"
73 /* 152 */ "R19R18\000"
74 /* 159 */ "R29R28\000"
75 /* 166 */ "R9R8\000"
76 /* 171 */ "R20R19\000"
77 /* 178 */ "R29\000"
78 /* 182 */ "R10R9\000"
79 /* 188 */ "SREG\000"
80 /* 193 */ "SPH\000"
81 /* 197 */ "SPL\000"
82 /* 201 */ "SP\000"
83};
84#ifdef __GNUC__
85#pragma GCC diagnostic pop
86#endif
87
88extern const MCRegisterDesc AVRRegDesc[] = { // Descriptors
89 { .Name: 6, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
90 { .Name: 201, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24576, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
91 { .Name: 193, .SubRegs: 1, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 4097, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
92 { .Name: 197, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 2, .RegUnits: 4096, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
93 { .Name: 188, .SubRegs: 1, .SuperRegs: 1, .SubRegIndices: 2, .RegUnits: 4098, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
94 { .Name: 23, .SubRegs: 1, .SuperRegs: 43, .SubRegIndices: 2, .RegUnits: 4099, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
95 { .Name: 44, .SubRegs: 1, .SuperRegs: 41, .SubRegIndices: 2, .RegUnits: 4100, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
96 { .Name: 63, .SubRegs: 1, .SuperRegs: 41, .SubRegIndices: 2, .RegUnits: 4101, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
97 { .Name: 80, .SubRegs: 1, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 4102, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
98 { .Name: 99, .SubRegs: 1, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 4103, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
99 { .Name: 116, .SubRegs: 1, .SuperRegs: 37, .SubRegIndices: 2, .RegUnits: 4104, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
100 { .Name: 135, .SubRegs: 1, .SuperRegs: 37, .SubRegIndices: 2, .RegUnits: 4105, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
101 { .Name: 149, .SubRegs: 1, .SuperRegs: 35, .SubRegIndices: 2, .RegUnits: 4106, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
102 { .Name: 168, .SubRegs: 1, .SuperRegs: 35, .SubRegIndices: 2, .RegUnits: 4107, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
103 { .Name: 185, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4108, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
104 { .Name: 3, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4109, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
105 { .Name: 29, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4110, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
106 { .Name: 50, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4111, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
107 { .Name: 69, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4112, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
108 { .Name: 86, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4113, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
109 { .Name: 105, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4114, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
110 { .Name: 122, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4115, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
111 { .Name: 141, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4116, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
112 { .Name: 155, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4117, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
113 { .Name: 174, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4118, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
114 { .Name: 10, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4119, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
115 { .Name: 36, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4120, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
116 { .Name: 57, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4121, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
117 { .Name: 76, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4122, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
118 { .Name: 93, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4123, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
119 { .Name: 112, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4124, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
120 { .Name: 129, .SubRegs: 1, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 4125, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
121 { .Name: 145, .SubRegs: 1, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 4126, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
122 { .Name: 162, .SubRegs: 1, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 4127, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
123 { .Name: 178, .SubRegs: 1, .SuperRegs: 31, .SubRegIndices: 2, .RegUnits: 4128, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
124 { .Name: 17, .SubRegs: 1, .SuperRegs: 31, .SubRegIndices: 2, .RegUnits: 4129, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
125 { .Name: 40, .SubRegs: 1, .SuperRegs: 29, .SubRegIndices: 2, .RegUnits: 4130, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
126 { .Name: 21, .SubRegs: 5, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24579, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
127 { .Name: 61, .SubRegs: 8, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24581, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
128 { .Name: 97, .SubRegs: 11, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24583, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
129 { .Name: 133, .SubRegs: 14, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24585, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
130 { .Name: 166, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24587, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
131 { .Name: 182, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24588, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
132 { .Name: 0, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24589, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
133 { .Name: 26, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24590, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
134 { .Name: 47, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24591, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
135 { .Name: 66, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24592, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
136 { .Name: 83, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24593, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
137 { .Name: 102, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24594, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
138 { .Name: 119, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24595, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
139 { .Name: 138, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24596, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
140 { .Name: 152, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24597, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
141 { .Name: 171, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24598, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
142 { .Name: 7, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24599, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
143 { .Name: 33, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24600, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
144 { .Name: 54, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24601, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
145 { .Name: 73, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24602, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
146 { .Name: 90, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24603, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
147 { .Name: 109, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24604, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
148 { .Name: 126, .SubRegs: 17, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24605, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
149 { .Name: 159, .SubRegs: 20, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24607, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
150 { .Name: 14, .SubRegs: 23, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 24609, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
151};
152
153extern const MCPhysReg AVRRegUnitRoots[][2] = {
154 { AVR::SPL },
155 { AVR::SPH },
156 { AVR::SREG },
157 { AVR::R0 },
158 { AVR::R1 },
159 { AVR::R2 },
160 { AVR::R3 },
161 { AVR::R4 },
162 { AVR::R5 },
163 { AVR::R6 },
164 { AVR::R7 },
165 { AVR::R8 },
166 { AVR::R9 },
167 { AVR::R10 },
168 { AVR::R11 },
169 { AVR::R12 },
170 { AVR::R13 },
171 { AVR::R14 },
172 { AVR::R15 },
173 { AVR::R16 },
174 { AVR::R17 },
175 { AVR::R18 },
176 { AVR::R19 },
177 { AVR::R20 },
178 { AVR::R21 },
179 { AVR::R22 },
180 { AVR::R23 },
181 { AVR::R24 },
182 { AVR::R25 },
183 { AVR::R26 },
184 { AVR::R27 },
185 { AVR::R28 },
186 { AVR::R29 },
187 { AVR::R30 },
188 { AVR::R31 },
189};
190
191namespace {
192
193// Register classes...
194 // GPR8 Register Class...
195 const MCPhysReg GPR8[] = {
196 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
197 };
198
199 // GPR8 Bit set.
200 const uint8_t GPR8Bits[] = {
201 0xe0, 0xff, 0xff, 0xff, 0x1f,
202 };
203
204 // GPR8NOZ Register Class...
205 const MCPhysReg GPR8NOZ[] = {
206 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
207 };
208
209 // GPR8NOZ Bit set.
210 const uint8_t GPR8NOZBits[] = {
211 0xe0, 0xff, 0xff, 0xff, 0x07,
212 };
213
214 // GPR8lo Register Class...
215 const MCPhysReg GPR8lo[] = {
216 AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
217 };
218
219 // GPR8lo Bit set.
220 const uint8_t GPR8loBits[] = {
221 0xe0, 0xff, 0x1f,
222 };
223
224 // LD8 Register Class...
225 const MCPhysReg LD8[] = {
226 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
227 };
228
229 // LD8 Bit set.
230 const uint8_t LD8Bits[] = {
231 0x00, 0x00, 0xe0, 0xff, 0x1f,
232 };
233
234 // GPR8NOZ_and_LD8 Register Class...
235 const MCPhysReg GPR8NOZ_and_LD8[] = {
236 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
237 };
238
239 // GPR8NOZ_and_LD8 Bit set.
240 const uint8_t GPR8NOZ_and_LD8Bits[] = {
241 0x00, 0x00, 0xe0, 0xff, 0x07,
242 };
243
244 // LD8lo Register Class...
245 const MCPhysReg LD8lo[] = {
246 AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16,
247 };
248
249 // LD8lo Bit set.
250 const uint8_t LD8loBits[] = {
251 0x00, 0x00, 0xe0, 0x1f,
252 };
253
254 // CCR Register Class...
255 const MCPhysReg CCR[] = {
256 AVR::SREG,
257 };
258
259 // CCR Bit set.
260 const uint8_t CCRBits[] = {
261 0x10,
262 };
263
264 // DREGS Register Class...
265 const MCPhysReg DREGS[] = {
266 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
267 };
268
269 // DREGS Bit set.
270 const uint8_t DREGSBits[] = {
271 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x3f,
272 };
273
274 // DREGSNOZ Register Class...
275 const MCPhysReg DREGSNOZ[] = {
276 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
277 };
278
279 // DREGSNOZ Bit set.
280 const uint8_t DREGSNOZBits[] = {
281 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x1f,
282 };
283
284 // DREGSMOVW Register Class...
285 const MCPhysReg DREGSMOVW[] = {
286 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
287 };
288
289 // DREGSMOVW Bit set.
290 const uint8_t DREGSMOVWBits[] = {
291 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x3a,
292 };
293
294 // DREGSMOVW_and_DREGSNOZ Register Class...
295 const MCPhysReg DREGSMOVW_and_DREGSNOZ[] = {
296 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
297 };
298
299 // DREGSMOVW_and_DREGSNOZ Bit set.
300 const uint8_t DREGSMOVW_and_DREGSNOZBits[] = {
301 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x1a,
302 };
303
304 // DREGS_with_sub_hi_in_LD8 Register Class...
305 const MCPhysReg DREGS_with_sub_hi_in_LD8[] = {
306 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
307 };
308
309 // DREGS_with_sub_hi_in_LD8 Bit set.
310 const uint8_t DREGS_with_sub_hi_in_LD8Bits[] = {
311 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
312 };
313
314 // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8 Register Class...
315 const MCPhysReg DREGSNOZ_and_DREGS_with_sub_hi_in_LD8[] = {
316 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
317 };
318
319 // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8 Bit set.
320 const uint8_t DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits[] = {
321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f,
322 };
323
324 // DREGS_with_sub_lo_in_LD8 Register Class...
325 const MCPhysReg DREGS_with_sub_lo_in_LD8[] = {
326 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
327 };
328
329 // DREGS_with_sub_lo_in_LD8 Bit set.
330 const uint8_t DREGS_with_sub_lo_in_LD8Bits[] = {
331 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
332 };
333
334 // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8 Register Class...
335 const MCPhysReg DREGSNOZ_and_DREGS_with_sub_lo_in_LD8[] = {
336 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
337 };
338
339 // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8 Bit set.
340 const uint8_t DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits[] = {
341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f,
342 };
343
344 // DREGS_with_sub_lo_in_GPR8lo Register Class...
345 const MCPhysReg DREGS_with_sub_lo_in_GPR8lo[] = {
346 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
347 };
348
349 // DREGS_with_sub_lo_in_GPR8lo Bit set.
350 const uint8_t DREGS_with_sub_lo_in_GPR8loBits[] = {
351 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01,
352 };
353
354 // DREGS_with_sub_hi_in_GPR8lo Register Class...
355 const MCPhysReg DREGS_with_sub_hi_in_GPR8lo[] = {
356 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R14R13, AVR::R12R11, AVR::R10R9,
357 };
358
359 // DREGS_with_sub_hi_in_GPR8lo Bit set.
360 const uint8_t DREGS_with_sub_hi_in_GPR8loBits[] = {
361 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff,
362 };
363
364 // DLDREGS Register Class...
365 const MCPhysReg DLDREGS[] = {
366 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16,
367 };
368
369 // DLDREGS Bit set.
370 const uint8_t DLDREGSBits[] = {
371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x3a,
372 };
373
374 // DREGS_with_sub_hi_in_LD8lo Register Class...
375 const MCPhysReg DREGS_with_sub_hi_in_LD8lo[] = {
376 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
377 };
378
379 // DREGS_with_sub_hi_in_LD8lo Bit set.
380 const uint8_t DREGS_with_sub_hi_in_LD8loBits[] = {
381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
382 };
383
384 // DREGS_with_sub_lo_in_LD8lo Register Class...
385 const MCPhysReg DREGS_with_sub_lo_in_LD8lo[] = {
386 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
387 };
388
389 // DREGS_with_sub_lo_in_LD8lo Bit set.
390 const uint8_t DREGS_with_sub_lo_in_LD8loBits[] = {
391 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
392 };
393
394 // DREGSlo Register Class...
395 const MCPhysReg DREGSlo[] = {
396 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
397 };
398
399 // DREGSlo Bit set.
400 const uint8_t DREGSloBits[] = {
401 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab,
402 };
403
404 // DLDREGS_and_DREGSNOZ Register Class...
405 const MCPhysReg DLDREGS_and_DREGSNOZ[] = {
406 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16,
407 };
408
409 // DLDREGS_and_DREGSNOZ Bit set.
410 const uint8_t DLDREGS_and_DREGSNOZBits[] = {
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x1a,
412 };
413
414 // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Register Class...
415 const MCPhysReg DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8[] = {
416 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17,
417 };
418
419 // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Bit set.
420 const uint8_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits[] = {
421 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
422 };
423
424 // DREGSLD8lo Register Class...
425 const MCPhysReg DREGSLD8lo[] = {
426 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16,
427 };
428
429 // DREGSLD8lo Bit set.
430 const uint8_t DREGSLD8loBits[] = {
431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
432 };
433
434 // IWREGS Register Class...
435 const MCPhysReg IWREGS[] = {
436 AVR::R25R24, AVR::R31R30, AVR::R27R26, AVR::R29R28,
437 };
438
439 // IWREGS Bit set.
440 const uint8_t IWREGSBits[] = {
441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a,
442 };
443
444 // DREGSNOZ_and_IWREGS Register Class...
445 const MCPhysReg DREGSNOZ_and_IWREGS[] = {
446 AVR::R25R24, AVR::R27R26, AVR::R29R28,
447 };
448
449 // DREGSNOZ_and_IWREGS Bit set.
450 const uint8_t DREGSNOZ_and_IWREGSBits[] = {
451 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,
452 };
453
454 // PTRREGS Register Class...
455 const MCPhysReg PTRREGS[] = {
456 AVR::R27R26, AVR::R29R28, AVR::R31R30,
457 };
458
459 // PTRREGS Bit set.
460 const uint8_t PTRREGSBits[] = {
461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
462 };
463
464 // DREGSNOZ_and_PTRREGS Register Class...
465 const MCPhysReg DREGSNOZ_and_PTRREGS[] = {
466 AVR::R27R26, AVR::R29R28,
467 };
468
469 // DREGSNOZ_and_PTRREGS Bit set.
470 const uint8_t DREGSNOZ_and_PTRREGSBits[] = {
471 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
472 };
473
474 // PTRDISPREGS Register Class...
475 const MCPhysReg PTRDISPREGS[] = {
476 AVR::R31R30, AVR::R29R28,
477 };
478
479 // PTRDISPREGS Bit set.
480 const uint8_t PTRDISPREGSBits[] = {
481 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
482 };
483
484 // DREGSNOZ_and_PTRDISPREGS Register Class...
485 const MCPhysReg DREGSNOZ_and_PTRDISPREGS[] = {
486 AVR::R29R28,
487 };
488
489 // DREGSNOZ_and_PTRDISPREGS Bit set.
490 const uint8_t DREGSNOZ_and_PTRDISPREGSBits[] = {
491 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
492 };
493
494 // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Register Class...
495 const MCPhysReg DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo[] = {
496 AVR::R16R15,
497 };
498
499 // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Bit set.
500 const uint8_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits[] = {
501 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
502 };
503
504 // GPRSP Register Class...
505 const MCPhysReg GPRSP[] = {
506 AVR::SP,
507 };
508
509 // GPRSP Bit set.
510 const uint8_t GPRSPBits[] = {
511 0x02,
512 };
513
514 // ZREG Register Class...
515 const MCPhysReg ZREG[] = {
516 AVR::R31R30,
517 };
518
519 // ZREG Bit set.
520 const uint8_t ZREGBits[] = {
521 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
522 };
523
524} // namespace
525
526#ifdef __GNUC__
527#pragma GCC diagnostic push
528#pragma GCC diagnostic ignored "-Woverlength-strings"
529#endif
530extern const char AVRRegClassStrings[] = {
531 /* 0 */ "GPR8NOZ_and_LD8\000"
532 /* 16 */ "DREGSNOZ_and_DREGS_with_sub_hi_in_LD8\000"
533 /* 54 */ "DREGSNOZ_and_DREGS_with_sub_lo_in_LD8\000"
534 /* 92 */ "DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8\000"
535 /* 148 */ "GPR8\000"
536 /* 153 */ "ZREG\000"
537 /* 158 */ "GPRSP\000"
538 /* 164 */ "CCR\000"
539 /* 168 */ "DLDREGS\000"
540 /* 176 */ "DREGSNOZ_and_PTRDISPREGS\000"
541 /* 201 */ "DREGSNOZ_and_PTRREGS\000"
542 /* 222 */ "DREGSNOZ_and_IWREGS\000"
543 /* 242 */ "DREGSMOVW\000"
544 /* 252 */ "GPR8NOZ\000"
545 /* 260 */ "DLDREGS_and_DREGSNOZ\000"
546 /* 281 */ "DREGSMOVW_and_DREGSNOZ\000"
547 /* 304 */ "DREGSLD8lo\000"
548 /* 315 */ "DREGS_with_sub_hi_in_LD8lo\000"
549 /* 342 */ "DREGS_with_sub_lo_in_LD8lo\000"
550 /* 369 */ "DREGS_with_sub_hi_in_GPR8lo\000"
551 /* 397 */ "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo\000"
552 /* 454 */ "DREGSlo\000"
553};
554#ifdef __GNUC__
555#pragma GCC diagnostic pop
556#endif
557
558extern const MCRegisterClass AVRMCRegisterClasses[] = {
559 { .RegsBegin: GPR8, .RegSet: GPR8Bits, .NameIdx: 148, .RegsSize: 32, .RegSetSize: sizeof(GPR8Bits), .ID: AVR::GPR8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
560 { .RegsBegin: GPR8NOZ, .RegSet: GPR8NOZBits, .NameIdx: 252, .RegsSize: 30, .RegSetSize: sizeof(GPR8NOZBits), .ID: AVR::GPR8NOZRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
561 { .RegsBegin: GPR8lo, .RegSet: GPR8loBits, .NameIdx: 390, .RegsSize: 16, .RegSetSize: sizeof(GPR8loBits), .ID: AVR::GPR8loRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
562 { .RegsBegin: LD8, .RegSet: LD8Bits, .NameIdx: 12, .RegsSize: 16, .RegSetSize: sizeof(LD8Bits), .ID: AVR::LD8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
563 { .RegsBegin: GPR8NOZ_and_LD8, .RegSet: GPR8NOZ_and_LD8Bits, .NameIdx: 0, .RegsSize: 14, .RegSetSize: sizeof(GPR8NOZ_and_LD8Bits), .ID: AVR::GPR8NOZ_and_LD8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
564 { .RegsBegin: LD8lo, .RegSet: LD8loBits, .NameIdx: 309, .RegsSize: 8, .RegSetSize: sizeof(LD8loBits), .ID: AVR::LD8loRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
565 { .RegsBegin: CCR, .RegSet: CCRBits, .NameIdx: 164, .RegsSize: 1, .RegSetSize: sizeof(CCRBits), .ID: AVR::CCRRegClassID, .RegSizeInBits: 8, .CopyCost: 255, .Allocatable: true, .BaseClass: false },
566 { .RegsBegin: DREGS, .RegSet: DREGSBits, .NameIdx: 170, .RegsSize: 25, .RegSetSize: sizeof(DREGSBits), .ID: AVR::DREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
567 { .RegsBegin: DREGSNOZ, .RegSet: DREGSNOZBits, .NameIdx: 272, .RegsSize: 24, .RegSetSize: sizeof(DREGSNOZBits), .ID: AVR::DREGSNOZRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
568 { .RegsBegin: DREGSMOVW, .RegSet: DREGSMOVWBits, .NameIdx: 242, .RegsSize: 16, .RegSetSize: sizeof(DREGSMOVWBits), .ID: AVR::DREGSMOVWRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
569 { .RegsBegin: DREGSMOVW_and_DREGSNOZ, .RegSet: DREGSMOVW_and_DREGSNOZBits, .NameIdx: 281, .RegsSize: 15, .RegSetSize: sizeof(DREGSMOVW_and_DREGSNOZBits), .ID: AVR::DREGSMOVW_and_DREGSNOZRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
570 { .RegsBegin: DREGS_with_sub_hi_in_LD8, .RegSet: DREGS_with_sub_hi_in_LD8Bits, .NameIdx: 29, .RegsSize: 14, .RegSetSize: sizeof(DREGS_with_sub_hi_in_LD8Bits), .ID: AVR::DREGS_with_sub_hi_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
571 { .RegsBegin: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8, .RegSet: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits, .NameIdx: 16, .RegsSize: 13, .RegSetSize: sizeof(DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits), .ID: AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
572 { .RegsBegin: DREGS_with_sub_lo_in_LD8, .RegSet: DREGS_with_sub_lo_in_LD8Bits, .NameIdx: 67, .RegsSize: 13, .RegSetSize: sizeof(DREGS_with_sub_lo_in_LD8Bits), .ID: AVR::DREGS_with_sub_lo_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
573 { .RegsBegin: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8, .RegSet: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits, .NameIdx: 54, .RegsSize: 12, .RegSetSize: sizeof(DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits), .ID: AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
574 { .RegsBegin: DREGS_with_sub_lo_in_GPR8lo, .RegSet: DREGS_with_sub_lo_in_GPR8loBits, .NameIdx: 426, .RegsSize: 12, .RegSetSize: sizeof(DREGS_with_sub_lo_in_GPR8loBits), .ID: AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
575 { .RegsBegin: DREGS_with_sub_hi_in_GPR8lo, .RegSet: DREGS_with_sub_hi_in_GPR8loBits, .NameIdx: 369, .RegsSize: 11, .RegSetSize: sizeof(DREGS_with_sub_hi_in_GPR8loBits), .ID: AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
576 { .RegsBegin: DLDREGS, .RegSet: DLDREGSBits, .NameIdx: 168, .RegsSize: 8, .RegSetSize: sizeof(DLDREGSBits), .ID: AVR::DLDREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
577 { .RegsBegin: DREGS_with_sub_hi_in_LD8lo, .RegSet: DREGS_with_sub_hi_in_LD8loBits, .NameIdx: 315, .RegsSize: 8, .RegSetSize: sizeof(DREGS_with_sub_hi_in_LD8loBits), .ID: AVR::DREGS_with_sub_hi_in_LD8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
578 { .RegsBegin: DREGS_with_sub_lo_in_LD8lo, .RegSet: DREGS_with_sub_lo_in_LD8loBits, .NameIdx: 342, .RegsSize: 8, .RegSetSize: sizeof(DREGS_with_sub_lo_in_LD8loBits), .ID: AVR::DREGS_with_sub_lo_in_LD8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
579 { .RegsBegin: DREGSlo, .RegSet: DREGSloBits, .NameIdx: 454, .RegsSize: 8, .RegSetSize: sizeof(DREGSloBits), .ID: AVR::DREGSloRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
580 { .RegsBegin: DLDREGS_and_DREGSNOZ, .RegSet: DLDREGS_and_DREGSNOZBits, .NameIdx: 260, .RegsSize: 7, .RegSetSize: sizeof(DLDREGS_and_DREGSNOZBits), .ID: AVR::DLDREGS_and_DREGSNOZRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
581 { .RegsBegin: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8, .RegSet: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits, .NameIdx: 92, .RegsSize: 7, .RegSetSize: sizeof(DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits), .ID: AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
582 { .RegsBegin: DREGSLD8lo, .RegSet: DREGSLD8loBits, .NameIdx: 304, .RegsSize: 4, .RegSetSize: sizeof(DREGSLD8loBits), .ID: AVR::DREGSLD8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
583 { .RegsBegin: IWREGS, .RegSet: IWREGSBits, .NameIdx: 235, .RegsSize: 4, .RegSetSize: sizeof(IWREGSBits), .ID: AVR::IWREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
584 { .RegsBegin: DREGSNOZ_and_IWREGS, .RegSet: DREGSNOZ_and_IWREGSBits, .NameIdx: 222, .RegsSize: 3, .RegSetSize: sizeof(DREGSNOZ_and_IWREGSBits), .ID: AVR::DREGSNOZ_and_IWREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
585 { .RegsBegin: PTRREGS, .RegSet: PTRREGSBits, .NameIdx: 214, .RegsSize: 3, .RegSetSize: sizeof(PTRREGSBits), .ID: AVR::PTRREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
586 { .RegsBegin: DREGSNOZ_and_PTRREGS, .RegSet: DREGSNOZ_and_PTRREGSBits, .NameIdx: 201, .RegsSize: 2, .RegSetSize: sizeof(DREGSNOZ_and_PTRREGSBits), .ID: AVR::DREGSNOZ_and_PTRREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
587 { .RegsBegin: PTRDISPREGS, .RegSet: PTRDISPREGSBits, .NameIdx: 189, .RegsSize: 2, .RegSetSize: sizeof(PTRDISPREGSBits), .ID: AVR::PTRDISPREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
588 { .RegsBegin: DREGSNOZ_and_PTRDISPREGS, .RegSet: DREGSNOZ_and_PTRDISPREGSBits, .NameIdx: 176, .RegsSize: 1, .RegSetSize: sizeof(DREGSNOZ_and_PTRDISPREGSBits), .ID: AVR::DREGSNOZ_and_PTRDISPREGSRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
589 { .RegsBegin: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo, .RegSet: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits, .NameIdx: 397, .RegsSize: 1, .RegSetSize: sizeof(DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits), .ID: AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
590 { .RegsBegin: GPRSP, .RegSet: GPRSPBits, .NameIdx: 158, .RegsSize: 1, .RegSetSize: sizeof(GPRSPBits), .ID: AVR::GPRSPRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
591 { .RegsBegin: ZREG, .RegSet: ZREGBits, .NameIdx: 153, .RegsSize: 1, .RegSetSize: sizeof(ZREGBits), .ID: AVR::ZREGRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
592};
593
594// AVR Dwarf<->LLVM register mappings.
595extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
596 { .FromReg: 0U, .ToReg: AVR::R1R0 },
597 { .FromReg: 1U, .ToReg: AVR::R1 },
598 { .FromReg: 2U, .ToReg: AVR::R3R2 },
599 { .FromReg: 3U, .ToReg: AVR::R3 },
600 { .FromReg: 4U, .ToReg: AVR::R5R4 },
601 { .FromReg: 5U, .ToReg: AVR::R5 },
602 { .FromReg: 6U, .ToReg: AVR::R7R6 },
603 { .FromReg: 7U, .ToReg: AVR::R7 },
604 { .FromReg: 8U, .ToReg: AVR::R9R8 },
605 { .FromReg: 9U, .ToReg: AVR::R10R9 },
606 { .FromReg: 10U, .ToReg: AVR::R11R10 },
607 { .FromReg: 11U, .ToReg: AVR::R12R11 },
608 { .FromReg: 12U, .ToReg: AVR::R13R12 },
609 { .FromReg: 13U, .ToReg: AVR::R14R13 },
610 { .FromReg: 14U, .ToReg: AVR::R15R14 },
611 { .FromReg: 15U, .ToReg: AVR::R16R15 },
612 { .FromReg: 16U, .ToReg: AVR::R17R16 },
613 { .FromReg: 17U, .ToReg: AVR::R18R17 },
614 { .FromReg: 18U, .ToReg: AVR::R19R18 },
615 { .FromReg: 19U, .ToReg: AVR::R20R19 },
616 { .FromReg: 20U, .ToReg: AVR::R21R20 },
617 { .FromReg: 21U, .ToReg: AVR::R22R21 },
618 { .FromReg: 22U, .ToReg: AVR::R23R22 },
619 { .FromReg: 23U, .ToReg: AVR::R24R23 },
620 { .FromReg: 24U, .ToReg: AVR::R25R24 },
621 { .FromReg: 25U, .ToReg: AVR::R26R25 },
622 { .FromReg: 26U, .ToReg: AVR::R27R26 },
623 { .FromReg: 27U, .ToReg: AVR::R27 },
624 { .FromReg: 28U, .ToReg: AVR::R29R28 },
625 { .FromReg: 29U, .ToReg: AVR::R29 },
626 { .FromReg: 30U, .ToReg: AVR::R31R30 },
627 { .FromReg: 31U, .ToReg: AVR::R31 },
628 { .FromReg: 32U, .ToReg: AVR::SPL },
629 { .FromReg: 33U, .ToReg: AVR::SPH },
630 { .FromReg: 88U, .ToReg: AVR::SREG },
631};
632extern const unsigned AVRDwarfFlavour0Dwarf2LSize = std::size(AVRDwarfFlavour0Dwarf2L);
633
634extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
635 { .FromReg: 0U, .ToReg: AVR::R1R0 },
636 { .FromReg: 1U, .ToReg: AVR::R1 },
637 { .FromReg: 2U, .ToReg: AVR::R3R2 },
638 { .FromReg: 3U, .ToReg: AVR::R3 },
639 { .FromReg: 4U, .ToReg: AVR::R5R4 },
640 { .FromReg: 5U, .ToReg: AVR::R5 },
641 { .FromReg: 6U, .ToReg: AVR::R7R6 },
642 { .FromReg: 7U, .ToReg: AVR::R7 },
643 { .FromReg: 8U, .ToReg: AVR::R9R8 },
644 { .FromReg: 9U, .ToReg: AVR::R10R9 },
645 { .FromReg: 10U, .ToReg: AVR::R11R10 },
646 { .FromReg: 11U, .ToReg: AVR::R12R11 },
647 { .FromReg: 12U, .ToReg: AVR::R13R12 },
648 { .FromReg: 13U, .ToReg: AVR::R14R13 },
649 { .FromReg: 14U, .ToReg: AVR::R15R14 },
650 { .FromReg: 15U, .ToReg: AVR::R16R15 },
651 { .FromReg: 16U, .ToReg: AVR::R17R16 },
652 { .FromReg: 17U, .ToReg: AVR::R18R17 },
653 { .FromReg: 18U, .ToReg: AVR::R19R18 },
654 { .FromReg: 19U, .ToReg: AVR::R20R19 },
655 { .FromReg: 20U, .ToReg: AVR::R21R20 },
656 { .FromReg: 21U, .ToReg: AVR::R22R21 },
657 { .FromReg: 22U, .ToReg: AVR::R23R22 },
658 { .FromReg: 23U, .ToReg: AVR::R24R23 },
659 { .FromReg: 24U, .ToReg: AVR::R25R24 },
660 { .FromReg: 25U, .ToReg: AVR::R26R25 },
661 { .FromReg: 26U, .ToReg: AVR::R27R26 },
662 { .FromReg: 27U, .ToReg: AVR::R27 },
663 { .FromReg: 28U, .ToReg: AVR::R29R28 },
664 { .FromReg: 29U, .ToReg: AVR::R29 },
665 { .FromReg: 30U, .ToReg: AVR::R31R30 },
666 { .FromReg: 31U, .ToReg: AVR::R31 },
667 { .FromReg: 32U, .ToReg: AVR::SPL },
668 { .FromReg: 33U, .ToReg: AVR::SPH },
669 { .FromReg: 88U, .ToReg: AVR::SREG },
670};
671extern const unsigned AVREHFlavour0Dwarf2LSize = std::size(AVREHFlavour0Dwarf2L);
672
673extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
674 { .FromReg: AVR::SP, .ToReg: 32U },
675 { .FromReg: AVR::SPH, .ToReg: 33U },
676 { .FromReg: AVR::SPL, .ToReg: 32U },
677 { .FromReg: AVR::SREG, .ToReg: 88U },
678 { .FromReg: AVR::R0, .ToReg: 0U },
679 { .FromReg: AVR::R1, .ToReg: 1U },
680 { .FromReg: AVR::R2, .ToReg: 2U },
681 { .FromReg: AVR::R3, .ToReg: 3U },
682 { .FromReg: AVR::R4, .ToReg: 4U },
683 { .FromReg: AVR::R5, .ToReg: 5U },
684 { .FromReg: AVR::R6, .ToReg: 6U },
685 { .FromReg: AVR::R7, .ToReg: 7U },
686 { .FromReg: AVR::R8, .ToReg: 8U },
687 { .FromReg: AVR::R9, .ToReg: 9U },
688 { .FromReg: AVR::R10, .ToReg: 10U },
689 { .FromReg: AVR::R11, .ToReg: 11U },
690 { .FromReg: AVR::R12, .ToReg: 12U },
691 { .FromReg: AVR::R13, .ToReg: 13U },
692 { .FromReg: AVR::R14, .ToReg: 14U },
693 { .FromReg: AVR::R15, .ToReg: 15U },
694 { .FromReg: AVR::R16, .ToReg: 16U },
695 { .FromReg: AVR::R17, .ToReg: 17U },
696 { .FromReg: AVR::R18, .ToReg: 18U },
697 { .FromReg: AVR::R19, .ToReg: 19U },
698 { .FromReg: AVR::R20, .ToReg: 20U },
699 { .FromReg: AVR::R21, .ToReg: 21U },
700 { .FromReg: AVR::R22, .ToReg: 22U },
701 { .FromReg: AVR::R23, .ToReg: 23U },
702 { .FromReg: AVR::R24, .ToReg: 24U },
703 { .FromReg: AVR::R25, .ToReg: 25U },
704 { .FromReg: AVR::R26, .ToReg: 26U },
705 { .FromReg: AVR::R27, .ToReg: 27U },
706 { .FromReg: AVR::R28, .ToReg: 28U },
707 { .FromReg: AVR::R29, .ToReg: 29U },
708 { .FromReg: AVR::R30, .ToReg: 30U },
709 { .FromReg: AVR::R31, .ToReg: 31U },
710 { .FromReg: AVR::R1R0, .ToReg: 0U },
711 { .FromReg: AVR::R3R2, .ToReg: 2U },
712 { .FromReg: AVR::R5R4, .ToReg: 4U },
713 { .FromReg: AVR::R7R6, .ToReg: 6U },
714 { .FromReg: AVR::R9R8, .ToReg: 8U },
715 { .FromReg: AVR::R10R9, .ToReg: 9U },
716 { .FromReg: AVR::R11R10, .ToReg: 10U },
717 { .FromReg: AVR::R12R11, .ToReg: 11U },
718 { .FromReg: AVR::R13R12, .ToReg: 12U },
719 { .FromReg: AVR::R14R13, .ToReg: 13U },
720 { .FromReg: AVR::R15R14, .ToReg: 14U },
721 { .FromReg: AVR::R16R15, .ToReg: 15U },
722 { .FromReg: AVR::R17R16, .ToReg: 16U },
723 { .FromReg: AVR::R18R17, .ToReg: 17U },
724 { .FromReg: AVR::R19R18, .ToReg: 18U },
725 { .FromReg: AVR::R20R19, .ToReg: 19U },
726 { .FromReg: AVR::R21R20, .ToReg: 20U },
727 { .FromReg: AVR::R22R21, .ToReg: 21U },
728 { .FromReg: AVR::R23R22, .ToReg: 22U },
729 { .FromReg: AVR::R24R23, .ToReg: 23U },
730 { .FromReg: AVR::R25R24, .ToReg: 24U },
731 { .FromReg: AVR::R26R25, .ToReg: 25U },
732 { .FromReg: AVR::R27R26, .ToReg: 26U },
733 { .FromReg: AVR::R29R28, .ToReg: 28U },
734 { .FromReg: AVR::R31R30, .ToReg: 30U },
735};
736extern const unsigned AVRDwarfFlavour0L2DwarfSize = std::size(AVRDwarfFlavour0L2Dwarf);
737
738extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
739 { .FromReg: AVR::SP, .ToReg: 32U },
740 { .FromReg: AVR::SPH, .ToReg: 33U },
741 { .FromReg: AVR::SPL, .ToReg: 32U },
742 { .FromReg: AVR::SREG, .ToReg: 88U },
743 { .FromReg: AVR::R0, .ToReg: 0U },
744 { .FromReg: AVR::R1, .ToReg: 1U },
745 { .FromReg: AVR::R2, .ToReg: 2U },
746 { .FromReg: AVR::R3, .ToReg: 3U },
747 { .FromReg: AVR::R4, .ToReg: 4U },
748 { .FromReg: AVR::R5, .ToReg: 5U },
749 { .FromReg: AVR::R6, .ToReg: 6U },
750 { .FromReg: AVR::R7, .ToReg: 7U },
751 { .FromReg: AVR::R8, .ToReg: 8U },
752 { .FromReg: AVR::R9, .ToReg: 9U },
753 { .FromReg: AVR::R10, .ToReg: 10U },
754 { .FromReg: AVR::R11, .ToReg: 11U },
755 { .FromReg: AVR::R12, .ToReg: 12U },
756 { .FromReg: AVR::R13, .ToReg: 13U },
757 { .FromReg: AVR::R14, .ToReg: 14U },
758 { .FromReg: AVR::R15, .ToReg: 15U },
759 { .FromReg: AVR::R16, .ToReg: 16U },
760 { .FromReg: AVR::R17, .ToReg: 17U },
761 { .FromReg: AVR::R18, .ToReg: 18U },
762 { .FromReg: AVR::R19, .ToReg: 19U },
763 { .FromReg: AVR::R20, .ToReg: 20U },
764 { .FromReg: AVR::R21, .ToReg: 21U },
765 { .FromReg: AVR::R22, .ToReg: 22U },
766 { .FromReg: AVR::R23, .ToReg: 23U },
767 { .FromReg: AVR::R24, .ToReg: 24U },
768 { .FromReg: AVR::R25, .ToReg: 25U },
769 { .FromReg: AVR::R26, .ToReg: 26U },
770 { .FromReg: AVR::R27, .ToReg: 27U },
771 { .FromReg: AVR::R28, .ToReg: 28U },
772 { .FromReg: AVR::R29, .ToReg: 29U },
773 { .FromReg: AVR::R30, .ToReg: 30U },
774 { .FromReg: AVR::R31, .ToReg: 31U },
775 { .FromReg: AVR::R1R0, .ToReg: 0U },
776 { .FromReg: AVR::R3R2, .ToReg: 2U },
777 { .FromReg: AVR::R5R4, .ToReg: 4U },
778 { .FromReg: AVR::R7R6, .ToReg: 6U },
779 { .FromReg: AVR::R9R8, .ToReg: 8U },
780 { .FromReg: AVR::R10R9, .ToReg: 9U },
781 { .FromReg: AVR::R11R10, .ToReg: 10U },
782 { .FromReg: AVR::R12R11, .ToReg: 11U },
783 { .FromReg: AVR::R13R12, .ToReg: 12U },
784 { .FromReg: AVR::R14R13, .ToReg: 13U },
785 { .FromReg: AVR::R15R14, .ToReg: 14U },
786 { .FromReg: AVR::R16R15, .ToReg: 15U },
787 { .FromReg: AVR::R17R16, .ToReg: 16U },
788 { .FromReg: AVR::R18R17, .ToReg: 17U },
789 { .FromReg: AVR::R19R18, .ToReg: 18U },
790 { .FromReg: AVR::R20R19, .ToReg: 19U },
791 { .FromReg: AVR::R21R20, .ToReg: 20U },
792 { .FromReg: AVR::R22R21, .ToReg: 21U },
793 { .FromReg: AVR::R23R22, .ToReg: 22U },
794 { .FromReg: AVR::R24R23, .ToReg: 23U },
795 { .FromReg: AVR::R25R24, .ToReg: 24U },
796 { .FromReg: AVR::R26R25, .ToReg: 25U },
797 { .FromReg: AVR::R27R26, .ToReg: 26U },
798 { .FromReg: AVR::R29R28, .ToReg: 28U },
799 { .FromReg: AVR::R31R30, .ToReg: 30U },
800};
801extern const unsigned AVREHFlavour0L2DwarfSize = std::size(AVREHFlavour0L2Dwarf);
802
803extern const uint16_t AVRRegEncodingTable[] = {
804 0,
805 16,
806 33,
807 32,
808 14,
809 0,
810 1,
811 2,
812 3,
813 4,
814 5,
815 6,
816 7,
817 8,
818 9,
819 10,
820 11,
821 12,
822 13,
823 14,
824 15,
825 16,
826 17,
827 18,
828 19,
829 20,
830 21,
831 22,
832 23,
833 24,
834 25,
835 26,
836 27,
837 28,
838 29,
839 30,
840 31,
841 0,
842 1,
843 2,
844 3,
845 4,
846 9,
847 5,
848 11,
849 6,
850 13,
851 7,
852 15,
853 8,
854 17,
855 9,
856 19,
857 10,
858 21,
859 11,
860 23,
861 12,
862 25,
863 13,
864 14,
865 15,
866};
867static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
868 RI->InitMCRegisterInfo(D: AVRRegDesc, NR: 62, RA, PC, C: AVRMCRegisterClasses, NC: 33, RURoots: AVRRegUnitRoots, NRU: 35, DL: AVRRegDiffLists, RUMS: AVRLaneMaskLists, Strings: AVRRegStrings, ClassStrings: AVRRegClassStrings, SubIndices: AVRSubRegIdxLists, NumIndices: 3,
869RET: AVRRegEncodingTable, RUI: nullptr);
870
871 switch (DwarfFlavour) {
872 default:
873 llvm_unreachable("Unknown DWARF flavour");
874 case 0:
875 RI->mapDwarfRegsToLLVMRegs(Map: AVRDwarfFlavour0Dwarf2L, Size: AVRDwarfFlavour0Dwarf2LSize, isEH: false);
876 break;
877 }
878 switch (EHFlavour) {
879 default:
880 llvm_unreachable("Unknown DWARF flavour");
881 case 0:
882 RI->mapDwarfRegsToLLVMRegs(Map: AVREHFlavour0Dwarf2L, Size: AVREHFlavour0Dwarf2LSize, isEH: true);
883 break;
884 }
885 switch (DwarfFlavour) {
886 default:
887 llvm_unreachable("Unknown DWARF flavour");
888 case 0:
889 RI->mapLLVMRegsToDwarfRegs(Map: AVRDwarfFlavour0L2Dwarf, Size: AVRDwarfFlavour0L2DwarfSize, isEH: false);
890 break;
891 }
892 switch (EHFlavour) {
893 default:
894 llvm_unreachable("Unknown DWARF flavour");
895 case 0:
896 RI->mapLLVMRegsToDwarfRegs(Map: AVREHFlavour0L2Dwarf, Size: AVREHFlavour0L2DwarfSize, isEH: true);
897 break;
898 }
899}
900
901
902} // namespace llvm
903