1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass AVRMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18static const char *SubRegIndexNameTable[] = { "sub_hi", "sub_lo", "" };
19
20static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
21 { .Offset: 65535, .Size: 65535 },
22 { .Offset: 8, .Size: 8 }, // sub_hi
23 { .Offset: 0, .Size: 8 }, // sub_lo
24};
25
26
27static const LaneBitmask SubRegIndexLaneMaskTable[] = {
28 LaneBitmask::getAll(),
29 LaneBitmask(0x0000000000000001), // sub_hi
30 LaneBitmask(0x0000000000000002), // sub_lo
31 };
32
33
34
35static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
36 // Mode = 0 (Default)
37 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GPR8
38 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GPR8NOZ
39 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GPR8lo
40 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // LD8
41 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GPR8NOZ_and_LD8
42 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // LD8lo
43 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // CCR
44 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS
45 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ
46 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSMOVW
47 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSMOVW_and_DREGSNOZ
48 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8
49 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
50 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_LD8
51 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
52 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_GPR8lo
53 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_GPR8lo
54 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DLDREGS
55 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8lo
56 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_LD8lo
57 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSlo
58 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DLDREGS_and_DREGSNOZ
59 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
60 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSLD8lo
61 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // IWREGS
62 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_IWREGS
63 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // PTRREGS
64 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_PTRREGS
65 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // PTRDISPREGS
66 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_PTRDISPREGS
67 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
68 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // GPRSP
69 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // ZREG
70};
71static const uint32_t GPR8SubClassMask[] = {
72 0x0000003f, 0x00000000,
73 0x7fffff80, 0x00000001, // sub_hi
74 0x7fffff80, 0x00000001, // sub_lo
75};
76
77static const uint32_t GPR8NOZSubClassMask[] = {
78 0x00000036, 0x00000000,
79 0x6afdd500, 0x00000000, // sub_hi
80 0x6afdd500, 0x00000000, // sub_lo
81};
82
83static const uint32_t GPR8loSubClassMask[] = {
84 0x00000004, 0x00000000,
85 0x00110000, 0x00000000, // sub_hi
86 0x40118000, 0x00000000, // sub_lo
87};
88
89static const uint32_t LD8SubClassMask[] = {
90 0x00000038, 0x00000000,
91 0x7fee7800, 0x00000001, // sub_hi
92 0x3fea6000, 0x00000001, // sub_lo
93};
94
95static const uint32_t GPR8NOZ_and_LD8SubClassMask[] = {
96 0x00000030, 0x00000000,
97 0x6aec5000, 0x00000000, // sub_hi
98 0x2ae84000, 0x00000000, // sub_lo
99};
100
101static const uint32_t LD8loSubClassMask[] = {
102 0x00000020, 0x00000000,
103 0x40c40000, 0x00000000, // sub_hi
104 0x00c80000, 0x00000000, // sub_lo
105};
106
107static const uint32_t CCRSubClassMask[] = {
108 0x00000040, 0x00000000,
109};
110
111static const uint32_t DREGSSubClassMask[] = {
112 0x7fffff80, 0x00000001,
113};
114
115static const uint32_t DREGSNOZSubClassMask[] = {
116 0x6afdd500, 0x00000000,
117};
118
119static const uint32_t DREGSMOVWSubClassMask[] = {
120 0x3fb20600, 0x00000001,
121};
122
123static const uint32_t DREGSMOVW_and_DREGSNOZSubClassMask[] = {
124 0x2ab00400, 0x00000000,
125};
126
127static const uint32_t DREGS_with_sub_hi_in_LD8SubClassMask[] = {
128 0x7fee7800, 0x00000001,
129};
130
131static const uint32_t DREGSNOZ_and_DREGS_with_sub_hi_in_LD8SubClassMask[] = {
132 0x6aec5000, 0x00000000,
133};
134
135static const uint32_t DREGS_with_sub_lo_in_LD8SubClassMask[] = {
136 0x3fea6000, 0x00000001,
137};
138
139static const uint32_t DREGSNOZ_and_DREGS_with_sub_lo_in_LD8SubClassMask[] = {
140 0x2ae84000, 0x00000000,
141};
142
143static const uint32_t DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
144 0x40118000, 0x00000000,
145};
146
147static const uint32_t DREGS_with_sub_hi_in_GPR8loSubClassMask[] = {
148 0x00110000, 0x00000000,
149};
150
151static const uint32_t DLDREGSSubClassMask[] = {
152 0x3fa20000, 0x00000001,
153};
154
155static const uint32_t DREGS_with_sub_hi_in_LD8loSubClassMask[] = {
156 0x40c40000, 0x00000000,
157};
158
159static const uint32_t DREGS_with_sub_lo_in_LD8loSubClassMask[] = {
160 0x00c80000, 0x00000000,
161};
162
163static const uint32_t DREGSloSubClassMask[] = {
164 0x00100000, 0x00000000,
165};
166
167static const uint32_t DLDREGS_and_DREGSNOZSubClassMask[] = {
168 0x2aa00000, 0x00000000,
169};
170
171static const uint32_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask[] = {
172 0x00c00000, 0x00000000,
173};
174
175static const uint32_t DREGSLD8loSubClassMask[] = {
176 0x00800000, 0x00000000,
177};
178
179static const uint32_t IWREGSSubClassMask[] = {
180 0x3f000000, 0x00000001,
181};
182
183static const uint32_t DREGSNOZ_and_IWREGSSubClassMask[] = {
184 0x2a000000, 0x00000000,
185};
186
187static const uint32_t PTRREGSSubClassMask[] = {
188 0x3c000000, 0x00000001,
189};
190
191static const uint32_t DREGSNOZ_and_PTRREGSSubClassMask[] = {
192 0x28000000, 0x00000000,
193};
194
195static const uint32_t PTRDISPREGSSubClassMask[] = {
196 0x30000000, 0x00000001,
197};
198
199static const uint32_t DREGSNOZ_and_PTRDISPREGSSubClassMask[] = {
200 0x20000000, 0x00000000,
201};
202
203static const uint32_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
204 0x40000000, 0x00000000,
205};
206
207static const uint32_t GPRSPSubClassMask[] = {
208 0x80000000, 0x00000000,
209};
210
211static const uint32_t ZREGSubClassMask[] = {
212 0x00000000, 0x00000001,
213};
214
215static const uint16_t SuperRegIdxSeqs[] = {
216 /* 0 */ 1, 2, 0,
217};
218
219static unsigned const GPR8NOZSuperclasses[] = {
220 AVR::GPR8RegClassID,
221};
222
223static unsigned const GPR8loSuperclasses[] = {
224 AVR::GPR8RegClassID,
225 AVR::GPR8NOZRegClassID,
226};
227
228static unsigned const LD8Superclasses[] = {
229 AVR::GPR8RegClassID,
230};
231
232static unsigned const GPR8NOZ_and_LD8Superclasses[] = {
233 AVR::GPR8RegClassID,
234 AVR::GPR8NOZRegClassID,
235 AVR::LD8RegClassID,
236};
237
238static unsigned const LD8loSuperclasses[] = {
239 AVR::GPR8RegClassID,
240 AVR::GPR8NOZRegClassID,
241 AVR::LD8RegClassID,
242 AVR::GPR8NOZ_and_LD8RegClassID,
243};
244
245static unsigned const DREGSNOZSuperclasses[] = {
246 AVR::DREGSRegClassID,
247};
248
249static unsigned const DREGSMOVWSuperclasses[] = {
250 AVR::DREGSRegClassID,
251};
252
253static unsigned const DREGSMOVW_and_DREGSNOZSuperclasses[] = {
254 AVR::DREGSRegClassID,
255 AVR::DREGSNOZRegClassID,
256 AVR::DREGSMOVWRegClassID,
257};
258
259static unsigned const DREGS_with_sub_hi_in_LD8Superclasses[] = {
260 AVR::DREGSRegClassID,
261};
262
263static unsigned const DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Superclasses[] = {
264 AVR::DREGSRegClassID,
265 AVR::DREGSNOZRegClassID,
266 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
267};
268
269static unsigned const DREGS_with_sub_lo_in_LD8Superclasses[] = {
270 AVR::DREGSRegClassID,
271 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
272};
273
274static unsigned const DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Superclasses[] = {
275 AVR::DREGSRegClassID,
276 AVR::DREGSNOZRegClassID,
277 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
278 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
279 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
280};
281
282static unsigned const DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
283 AVR::DREGSRegClassID,
284 AVR::DREGSNOZRegClassID,
285};
286
287static unsigned const DREGS_with_sub_hi_in_GPR8loSuperclasses[] = {
288 AVR::DREGSRegClassID,
289 AVR::DREGSNOZRegClassID,
290 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
291};
292
293static unsigned const DLDREGSSuperclasses[] = {
294 AVR::DREGSRegClassID,
295 AVR::DREGSMOVWRegClassID,
296 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
297 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
298};
299
300static unsigned const DREGS_with_sub_hi_in_LD8loSuperclasses[] = {
301 AVR::DREGSRegClassID,
302 AVR::DREGSNOZRegClassID,
303 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
304 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
305};
306
307static unsigned const DREGS_with_sub_lo_in_LD8loSuperclasses[] = {
308 AVR::DREGSRegClassID,
309 AVR::DREGSNOZRegClassID,
310 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
311 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
312 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
313 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
314};
315
316static unsigned const DREGSloSuperclasses[] = {
317 AVR::DREGSRegClassID,
318 AVR::DREGSNOZRegClassID,
319 AVR::DREGSMOVWRegClassID,
320 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
321 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
322 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID,
323};
324
325static unsigned const DLDREGS_and_DREGSNOZSuperclasses[] = {
326 AVR::DREGSRegClassID,
327 AVR::DREGSNOZRegClassID,
328 AVR::DREGSMOVWRegClassID,
329 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
330 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
331 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
332 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
333 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
334 AVR::DLDREGSRegClassID,
335};
336
337static unsigned const DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses[] = {
338 AVR::DREGSRegClassID,
339 AVR::DREGSNOZRegClassID,
340 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
341 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
342 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
343 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
344 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
345 AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
346};
347
348static unsigned const DREGSLD8loSuperclasses[] = {
349 AVR::DREGSRegClassID,
350 AVR::DREGSNOZRegClassID,
351 AVR::DREGSMOVWRegClassID,
352 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
353 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
354 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
355 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
356 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
357 AVR::DLDREGSRegClassID,
358 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
359 AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
360 AVR::DLDREGS_and_DREGSNOZRegClassID,
361 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID,
362};
363
364static unsigned const IWREGSSuperclasses[] = {
365 AVR::DREGSRegClassID,
366 AVR::DREGSMOVWRegClassID,
367 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
368 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
369 AVR::DLDREGSRegClassID,
370};
371
372static unsigned const DREGSNOZ_and_IWREGSSuperclasses[] = {
373 AVR::DREGSRegClassID,
374 AVR::DREGSNOZRegClassID,
375 AVR::DREGSMOVWRegClassID,
376 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
377 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
378 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
379 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
380 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
381 AVR::DLDREGSRegClassID,
382 AVR::DLDREGS_and_DREGSNOZRegClassID,
383 AVR::IWREGSRegClassID,
384};
385
386static unsigned const PTRREGSSuperclasses[] = {
387 AVR::DREGSRegClassID,
388 AVR::DREGSMOVWRegClassID,
389 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
390 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
391 AVR::DLDREGSRegClassID,
392 AVR::IWREGSRegClassID,
393};
394
395static unsigned const DREGSNOZ_and_PTRREGSSuperclasses[] = {
396 AVR::DREGSRegClassID,
397 AVR::DREGSNOZRegClassID,
398 AVR::DREGSMOVWRegClassID,
399 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
400 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
401 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
402 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
403 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
404 AVR::DLDREGSRegClassID,
405 AVR::DLDREGS_and_DREGSNOZRegClassID,
406 AVR::IWREGSRegClassID,
407 AVR::DREGSNOZ_and_IWREGSRegClassID,
408 AVR::PTRREGSRegClassID,
409};
410
411static unsigned const PTRDISPREGSSuperclasses[] = {
412 AVR::DREGSRegClassID,
413 AVR::DREGSMOVWRegClassID,
414 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
415 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
416 AVR::DLDREGSRegClassID,
417 AVR::IWREGSRegClassID,
418 AVR::PTRREGSRegClassID,
419};
420
421static unsigned const DREGSNOZ_and_PTRDISPREGSSuperclasses[] = {
422 AVR::DREGSRegClassID,
423 AVR::DREGSNOZRegClassID,
424 AVR::DREGSMOVWRegClassID,
425 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
426 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
427 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
428 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
429 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
430 AVR::DLDREGSRegClassID,
431 AVR::DLDREGS_and_DREGSNOZRegClassID,
432 AVR::IWREGSRegClassID,
433 AVR::DREGSNOZ_and_IWREGSRegClassID,
434 AVR::PTRREGSRegClassID,
435 AVR::DREGSNOZ_and_PTRREGSRegClassID,
436 AVR::PTRDISPREGSRegClassID,
437};
438
439static unsigned const DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
440 AVR::DREGSRegClassID,
441 AVR::DREGSNOZRegClassID,
442 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
443 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
444 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
445 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
446};
447
448static unsigned const ZREGSuperclasses[] = {
449 AVR::DREGSRegClassID,
450 AVR::DREGSMOVWRegClassID,
451 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
452 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
453 AVR::DLDREGSRegClassID,
454 AVR::IWREGSRegClassID,
455 AVR::PTRREGSRegClassID,
456 AVR::PTRDISPREGSRegClassID,
457};
458
459
460namespace AVR { // Register class instances
461 extern const TargetRegisterClass GPR8RegClass = {
462 .MC: &AVRMCRegisterClasses[GPR8RegClassID],
463 .SubClassMask: GPR8SubClassMask,
464 .SuperRegIndices: SuperRegIdxSeqs + 0,
465 .LaneMask: LaneBitmask(0x0000000000000001),
466 .AllocationPriority: 0,
467 .GlobalPriority: false,
468 .TSFlags: 0x00, /* TSFlags */
469 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
470 .CoveredBySubRegs: false, /* CoveredBySubRegs */
471 .SuperClasses: nullptr, .SuperClassesSize: 0,
472 .OrderFunc: nullptr
473 };
474
475 extern const TargetRegisterClass GPR8NOZRegClass = {
476 .MC: &AVRMCRegisterClasses[GPR8NOZRegClassID],
477 .SubClassMask: GPR8NOZSubClassMask,
478 .SuperRegIndices: SuperRegIdxSeqs + 0,
479 .LaneMask: LaneBitmask(0x0000000000000001),
480 .AllocationPriority: 0,
481 .GlobalPriority: false,
482 .TSFlags: 0x00, /* TSFlags */
483 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
484 .CoveredBySubRegs: false, /* CoveredBySubRegs */
485 .SuperClasses: GPR8NOZSuperclasses, .SuperClassesSize: 1,
486 .OrderFunc: nullptr
487 };
488
489 extern const TargetRegisterClass GPR8loRegClass = {
490 .MC: &AVRMCRegisterClasses[GPR8loRegClassID],
491 .SubClassMask: GPR8loSubClassMask,
492 .SuperRegIndices: SuperRegIdxSeqs + 0,
493 .LaneMask: LaneBitmask(0x0000000000000001),
494 .AllocationPriority: 0,
495 .GlobalPriority: false,
496 .TSFlags: 0x00, /* TSFlags */
497 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
498 .CoveredBySubRegs: false, /* CoveredBySubRegs */
499 .SuperClasses: GPR8loSuperclasses, .SuperClassesSize: 2,
500 .OrderFunc: nullptr
501 };
502
503 extern const TargetRegisterClass LD8RegClass = {
504 .MC: &AVRMCRegisterClasses[LD8RegClassID],
505 .SubClassMask: LD8SubClassMask,
506 .SuperRegIndices: SuperRegIdxSeqs + 0,
507 .LaneMask: LaneBitmask(0x0000000000000001),
508 .AllocationPriority: 0,
509 .GlobalPriority: false,
510 .TSFlags: 0x00, /* TSFlags */
511 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
512 .CoveredBySubRegs: false, /* CoveredBySubRegs */
513 .SuperClasses: LD8Superclasses, .SuperClassesSize: 1,
514 .OrderFunc: nullptr
515 };
516
517 extern const TargetRegisterClass GPR8NOZ_and_LD8RegClass = {
518 .MC: &AVRMCRegisterClasses[GPR8NOZ_and_LD8RegClassID],
519 .SubClassMask: GPR8NOZ_and_LD8SubClassMask,
520 .SuperRegIndices: SuperRegIdxSeqs + 0,
521 .LaneMask: LaneBitmask(0x0000000000000001),
522 .AllocationPriority: 0,
523 .GlobalPriority: false,
524 .TSFlags: 0x00, /* TSFlags */
525 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
526 .CoveredBySubRegs: false, /* CoveredBySubRegs */
527 .SuperClasses: GPR8NOZ_and_LD8Superclasses, .SuperClassesSize: 3,
528 .OrderFunc: nullptr
529 };
530
531 extern const TargetRegisterClass LD8loRegClass = {
532 .MC: &AVRMCRegisterClasses[LD8loRegClassID],
533 .SubClassMask: LD8loSubClassMask,
534 .SuperRegIndices: SuperRegIdxSeqs + 0,
535 .LaneMask: LaneBitmask(0x0000000000000001),
536 .AllocationPriority: 0,
537 .GlobalPriority: false,
538 .TSFlags: 0x00, /* TSFlags */
539 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
540 .CoveredBySubRegs: false, /* CoveredBySubRegs */
541 .SuperClasses: LD8loSuperclasses, .SuperClassesSize: 4,
542 .OrderFunc: nullptr
543 };
544
545 extern const TargetRegisterClass CCRRegClass = {
546 .MC: &AVRMCRegisterClasses[CCRRegClassID],
547 .SubClassMask: CCRSubClassMask,
548 .SuperRegIndices: SuperRegIdxSeqs + 2,
549 .LaneMask: LaneBitmask(0x0000000000000001),
550 .AllocationPriority: 0,
551 .GlobalPriority: false,
552 .TSFlags: 0x00, /* TSFlags */
553 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
554 .CoveredBySubRegs: false, /* CoveredBySubRegs */
555 .SuperClasses: nullptr, .SuperClassesSize: 0,
556 .OrderFunc: nullptr
557 };
558
559 extern const TargetRegisterClass DREGSRegClass = {
560 .MC: &AVRMCRegisterClasses[DREGSRegClassID],
561 .SubClassMask: DREGSSubClassMask,
562 .SuperRegIndices: SuperRegIdxSeqs + 2,
563 .LaneMask: LaneBitmask(0x0000000000000003),
564 .AllocationPriority: 0,
565 .GlobalPriority: false,
566 .TSFlags: 0x00, /* TSFlags */
567 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
568 .CoveredBySubRegs: true, /* CoveredBySubRegs */
569 .SuperClasses: nullptr, .SuperClassesSize: 0,
570 .OrderFunc: nullptr
571 };
572
573 extern const TargetRegisterClass DREGSNOZRegClass = {
574 .MC: &AVRMCRegisterClasses[DREGSNOZRegClassID],
575 .SubClassMask: DREGSNOZSubClassMask,
576 .SuperRegIndices: SuperRegIdxSeqs + 2,
577 .LaneMask: LaneBitmask(0x0000000000000003),
578 .AllocationPriority: 0,
579 .GlobalPriority: false,
580 .TSFlags: 0x00, /* TSFlags */
581 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
582 .CoveredBySubRegs: true, /* CoveredBySubRegs */
583 .SuperClasses: DREGSNOZSuperclasses, .SuperClassesSize: 1,
584 .OrderFunc: nullptr
585 };
586
587 extern const TargetRegisterClass DREGSMOVWRegClass = {
588 .MC: &AVRMCRegisterClasses[DREGSMOVWRegClassID],
589 .SubClassMask: DREGSMOVWSubClassMask,
590 .SuperRegIndices: SuperRegIdxSeqs + 2,
591 .LaneMask: LaneBitmask(0x0000000000000003),
592 .AllocationPriority: 0,
593 .GlobalPriority: false,
594 .TSFlags: 0x00, /* TSFlags */
595 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
596 .CoveredBySubRegs: true, /* CoveredBySubRegs */
597 .SuperClasses: DREGSMOVWSuperclasses, .SuperClassesSize: 1,
598 .OrderFunc: nullptr
599 };
600
601 extern const TargetRegisterClass DREGSMOVW_and_DREGSNOZRegClass = {
602 .MC: &AVRMCRegisterClasses[DREGSMOVW_and_DREGSNOZRegClassID],
603 .SubClassMask: DREGSMOVW_and_DREGSNOZSubClassMask,
604 .SuperRegIndices: SuperRegIdxSeqs + 2,
605 .LaneMask: LaneBitmask(0x0000000000000003),
606 .AllocationPriority: 0,
607 .GlobalPriority: false,
608 .TSFlags: 0x00, /* TSFlags */
609 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
610 .CoveredBySubRegs: true, /* CoveredBySubRegs */
611 .SuperClasses: DREGSMOVW_and_DREGSNOZSuperclasses, .SuperClassesSize: 3,
612 .OrderFunc: nullptr
613 };
614
615 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8RegClass = {
616 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8RegClassID],
617 .SubClassMask: DREGS_with_sub_hi_in_LD8SubClassMask,
618 .SuperRegIndices: SuperRegIdxSeqs + 2,
619 .LaneMask: LaneBitmask(0x0000000000000003),
620 .AllocationPriority: 0,
621 .GlobalPriority: false,
622 .TSFlags: 0x00, /* TSFlags */
623 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
624 .CoveredBySubRegs: true, /* CoveredBySubRegs */
625 .SuperClasses: DREGS_with_sub_hi_in_LD8Superclasses, .SuperClassesSize: 1,
626 .OrderFunc: nullptr
627 };
628
629 extern const TargetRegisterClass DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClass = {
630 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID],
631 .SubClassMask: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8SubClassMask,
632 .SuperRegIndices: SuperRegIdxSeqs + 2,
633 .LaneMask: LaneBitmask(0x0000000000000003),
634 .AllocationPriority: 0,
635 .GlobalPriority: false,
636 .TSFlags: 0x00, /* TSFlags */
637 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
638 .CoveredBySubRegs: true, /* CoveredBySubRegs */
639 .SuperClasses: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Superclasses, .SuperClassesSize: 3,
640 .OrderFunc: nullptr
641 };
642
643 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8RegClass = {
644 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8RegClassID],
645 .SubClassMask: DREGS_with_sub_lo_in_LD8SubClassMask,
646 .SuperRegIndices: SuperRegIdxSeqs + 2,
647 .LaneMask: LaneBitmask(0x0000000000000003),
648 .AllocationPriority: 0,
649 .GlobalPriority: false,
650 .TSFlags: 0x00, /* TSFlags */
651 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
652 .CoveredBySubRegs: true, /* CoveredBySubRegs */
653 .SuperClasses: DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 2,
654 .OrderFunc: nullptr
655 };
656
657 extern const TargetRegisterClass DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClass = {
658 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID],
659 .SubClassMask: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8SubClassMask,
660 .SuperRegIndices: SuperRegIdxSeqs + 2,
661 .LaneMask: LaneBitmask(0x0000000000000003),
662 .AllocationPriority: 0,
663 .GlobalPriority: false,
664 .TSFlags: 0x00, /* TSFlags */
665 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
666 .CoveredBySubRegs: true, /* CoveredBySubRegs */
667 .SuperClasses: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 5,
668 .OrderFunc: nullptr
669 };
670
671 extern const TargetRegisterClass DREGS_with_sub_lo_in_GPR8loRegClass = {
672 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_GPR8loRegClassID],
673 .SubClassMask: DREGS_with_sub_lo_in_GPR8loSubClassMask,
674 .SuperRegIndices: SuperRegIdxSeqs + 2,
675 .LaneMask: LaneBitmask(0x0000000000000003),
676 .AllocationPriority: 0,
677 .GlobalPriority: false,
678 .TSFlags: 0x00, /* TSFlags */
679 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
680 .CoveredBySubRegs: true, /* CoveredBySubRegs */
681 .SuperClasses: DREGS_with_sub_lo_in_GPR8loSuperclasses, .SuperClassesSize: 2,
682 .OrderFunc: nullptr
683 };
684
685 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass = {
686 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_GPR8loRegClassID],
687 .SubClassMask: DREGS_with_sub_hi_in_GPR8loSubClassMask,
688 .SuperRegIndices: SuperRegIdxSeqs + 2,
689 .LaneMask: LaneBitmask(0x0000000000000003),
690 .AllocationPriority: 0,
691 .GlobalPriority: false,
692 .TSFlags: 0x00, /* TSFlags */
693 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
694 .CoveredBySubRegs: true, /* CoveredBySubRegs */
695 .SuperClasses: DREGS_with_sub_hi_in_GPR8loSuperclasses, .SuperClassesSize: 3,
696 .OrderFunc: nullptr
697 };
698
699 extern const TargetRegisterClass DLDREGSRegClass = {
700 .MC: &AVRMCRegisterClasses[DLDREGSRegClassID],
701 .SubClassMask: DLDREGSSubClassMask,
702 .SuperRegIndices: SuperRegIdxSeqs + 2,
703 .LaneMask: LaneBitmask(0x0000000000000003),
704 .AllocationPriority: 0,
705 .GlobalPriority: false,
706 .TSFlags: 0x00, /* TSFlags */
707 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
708 .CoveredBySubRegs: true, /* CoveredBySubRegs */
709 .SuperClasses: DLDREGSSuperclasses, .SuperClassesSize: 4,
710 .OrderFunc: nullptr
711 };
712
713 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8loRegClass = {
714 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8loRegClassID],
715 .SubClassMask: DREGS_with_sub_hi_in_LD8loSubClassMask,
716 .SuperRegIndices: SuperRegIdxSeqs + 2,
717 .LaneMask: LaneBitmask(0x0000000000000003),
718 .AllocationPriority: 0,
719 .GlobalPriority: false,
720 .TSFlags: 0x00, /* TSFlags */
721 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
722 .CoveredBySubRegs: true, /* CoveredBySubRegs */
723 .SuperClasses: DREGS_with_sub_hi_in_LD8loSuperclasses, .SuperClassesSize: 4,
724 .OrderFunc: nullptr
725 };
726
727 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8loRegClass = {
728 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8loRegClassID],
729 .SubClassMask: DREGS_with_sub_lo_in_LD8loSubClassMask,
730 .SuperRegIndices: SuperRegIdxSeqs + 2,
731 .LaneMask: LaneBitmask(0x0000000000000003),
732 .AllocationPriority: 0,
733 .GlobalPriority: false,
734 .TSFlags: 0x00, /* TSFlags */
735 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
736 .CoveredBySubRegs: true, /* CoveredBySubRegs */
737 .SuperClasses: DREGS_with_sub_lo_in_LD8loSuperclasses, .SuperClassesSize: 6,
738 .OrderFunc: nullptr
739 };
740
741 extern const TargetRegisterClass DREGSloRegClass = {
742 .MC: &AVRMCRegisterClasses[DREGSloRegClassID],
743 .SubClassMask: DREGSloSubClassMask,
744 .SuperRegIndices: SuperRegIdxSeqs + 2,
745 .LaneMask: LaneBitmask(0x0000000000000003),
746 .AllocationPriority: 0,
747 .GlobalPriority: false,
748 .TSFlags: 0x00, /* TSFlags */
749 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
750 .CoveredBySubRegs: true, /* CoveredBySubRegs */
751 .SuperClasses: DREGSloSuperclasses, .SuperClassesSize: 6,
752 .OrderFunc: nullptr
753 };
754
755 extern const TargetRegisterClass DLDREGS_and_DREGSNOZRegClass = {
756 .MC: &AVRMCRegisterClasses[DLDREGS_and_DREGSNOZRegClassID],
757 .SubClassMask: DLDREGS_and_DREGSNOZSubClassMask,
758 .SuperRegIndices: SuperRegIdxSeqs + 2,
759 .LaneMask: LaneBitmask(0x0000000000000003),
760 .AllocationPriority: 0,
761 .GlobalPriority: false,
762 .TSFlags: 0x00, /* TSFlags */
763 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
764 .CoveredBySubRegs: true, /* CoveredBySubRegs */
765 .SuperClasses: DLDREGS_and_DREGSNOZSuperclasses, .SuperClassesSize: 9,
766 .OrderFunc: nullptr
767 };
768
769 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass = {
770 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID],
771 .SubClassMask: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask,
772 .SuperRegIndices: SuperRegIdxSeqs + 2,
773 .LaneMask: LaneBitmask(0x0000000000000003),
774 .AllocationPriority: 0,
775 .GlobalPriority: false,
776 .TSFlags: 0x00, /* TSFlags */
777 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
778 .CoveredBySubRegs: true, /* CoveredBySubRegs */
779 .SuperClasses: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 8,
780 .OrderFunc: nullptr
781 };
782
783 extern const TargetRegisterClass DREGSLD8loRegClass = {
784 .MC: &AVRMCRegisterClasses[DREGSLD8loRegClassID],
785 .SubClassMask: DREGSLD8loSubClassMask,
786 .SuperRegIndices: SuperRegIdxSeqs + 2,
787 .LaneMask: LaneBitmask(0x0000000000000003),
788 .AllocationPriority: 0,
789 .GlobalPriority: false,
790 .TSFlags: 0x00, /* TSFlags */
791 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
792 .CoveredBySubRegs: true, /* CoveredBySubRegs */
793 .SuperClasses: DREGSLD8loSuperclasses, .SuperClassesSize: 13,
794 .OrderFunc: nullptr
795 };
796
797 extern const TargetRegisterClass IWREGSRegClass = {
798 .MC: &AVRMCRegisterClasses[IWREGSRegClassID],
799 .SubClassMask: IWREGSSubClassMask,
800 .SuperRegIndices: SuperRegIdxSeqs + 2,
801 .LaneMask: LaneBitmask(0x0000000000000003),
802 .AllocationPriority: 0,
803 .GlobalPriority: false,
804 .TSFlags: 0x00, /* TSFlags */
805 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
806 .CoveredBySubRegs: true, /* CoveredBySubRegs */
807 .SuperClasses: IWREGSSuperclasses, .SuperClassesSize: 5,
808 .OrderFunc: nullptr
809 };
810
811 extern const TargetRegisterClass DREGSNOZ_and_IWREGSRegClass = {
812 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_IWREGSRegClassID],
813 .SubClassMask: DREGSNOZ_and_IWREGSSubClassMask,
814 .SuperRegIndices: SuperRegIdxSeqs + 2,
815 .LaneMask: LaneBitmask(0x0000000000000003),
816 .AllocationPriority: 0,
817 .GlobalPriority: false,
818 .TSFlags: 0x00, /* TSFlags */
819 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
820 .CoveredBySubRegs: true, /* CoveredBySubRegs */
821 .SuperClasses: DREGSNOZ_and_IWREGSSuperclasses, .SuperClassesSize: 11,
822 .OrderFunc: nullptr
823 };
824
825 extern const TargetRegisterClass PTRREGSRegClass = {
826 .MC: &AVRMCRegisterClasses[PTRREGSRegClassID],
827 .SubClassMask: PTRREGSSubClassMask,
828 .SuperRegIndices: SuperRegIdxSeqs + 2,
829 .LaneMask: LaneBitmask(0x0000000000000003),
830 .AllocationPriority: 0,
831 .GlobalPriority: false,
832 .TSFlags: 0x00, /* TSFlags */
833 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
834 .CoveredBySubRegs: true, /* CoveredBySubRegs */
835 .SuperClasses: PTRREGSSuperclasses, .SuperClassesSize: 6,
836 .OrderFunc: nullptr
837 };
838
839 extern const TargetRegisterClass DREGSNOZ_and_PTRREGSRegClass = {
840 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_PTRREGSRegClassID],
841 .SubClassMask: DREGSNOZ_and_PTRREGSSubClassMask,
842 .SuperRegIndices: SuperRegIdxSeqs + 2,
843 .LaneMask: LaneBitmask(0x0000000000000003),
844 .AllocationPriority: 0,
845 .GlobalPriority: false,
846 .TSFlags: 0x00, /* TSFlags */
847 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
848 .CoveredBySubRegs: true, /* CoveredBySubRegs */
849 .SuperClasses: DREGSNOZ_and_PTRREGSSuperclasses, .SuperClassesSize: 13,
850 .OrderFunc: nullptr
851 };
852
853 extern const TargetRegisterClass PTRDISPREGSRegClass = {
854 .MC: &AVRMCRegisterClasses[PTRDISPREGSRegClassID],
855 .SubClassMask: PTRDISPREGSSubClassMask,
856 .SuperRegIndices: SuperRegIdxSeqs + 2,
857 .LaneMask: LaneBitmask(0x0000000000000003),
858 .AllocationPriority: 0,
859 .GlobalPriority: false,
860 .TSFlags: 0x00, /* TSFlags */
861 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
862 .CoveredBySubRegs: true, /* CoveredBySubRegs */
863 .SuperClasses: PTRDISPREGSSuperclasses, .SuperClassesSize: 7,
864 .OrderFunc: nullptr
865 };
866
867 extern const TargetRegisterClass DREGSNOZ_and_PTRDISPREGSRegClass = {
868 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_PTRDISPREGSRegClassID],
869 .SubClassMask: DREGSNOZ_and_PTRDISPREGSSubClassMask,
870 .SuperRegIndices: SuperRegIdxSeqs + 2,
871 .LaneMask: LaneBitmask(0x0000000000000003),
872 .AllocationPriority: 0,
873 .GlobalPriority: false,
874 .TSFlags: 0x00, /* TSFlags */
875 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
876 .CoveredBySubRegs: true, /* CoveredBySubRegs */
877 .SuperClasses: DREGSNOZ_and_PTRDISPREGSSuperclasses, .SuperClassesSize: 15,
878 .OrderFunc: nullptr
879 };
880
881 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass = {
882 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID],
883 .SubClassMask: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask,
884 .SuperRegIndices: SuperRegIdxSeqs + 2,
885 .LaneMask: LaneBitmask(0x0000000000000003),
886 .AllocationPriority: 0,
887 .GlobalPriority: false,
888 .TSFlags: 0x00, /* TSFlags */
889 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
890 .CoveredBySubRegs: true, /* CoveredBySubRegs */
891 .SuperClasses: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses, .SuperClassesSize: 6,
892 .OrderFunc: nullptr
893 };
894
895 extern const TargetRegisterClass GPRSPRegClass = {
896 .MC: &AVRMCRegisterClasses[GPRSPRegClassID],
897 .SubClassMask: GPRSPSubClassMask,
898 .SuperRegIndices: SuperRegIdxSeqs + 2,
899 .LaneMask: LaneBitmask(0x0000000000000003),
900 .AllocationPriority: 0,
901 .GlobalPriority: false,
902 .TSFlags: 0x00, /* TSFlags */
903 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
904 .CoveredBySubRegs: true, /* CoveredBySubRegs */
905 .SuperClasses: nullptr, .SuperClassesSize: 0,
906 .OrderFunc: nullptr
907 };
908
909 extern const TargetRegisterClass ZREGRegClass = {
910 .MC: &AVRMCRegisterClasses[ZREGRegClassID],
911 .SubClassMask: ZREGSubClassMask,
912 .SuperRegIndices: SuperRegIdxSeqs + 2,
913 .LaneMask: LaneBitmask(0x0000000000000003),
914 .AllocationPriority: 0,
915 .GlobalPriority: false,
916 .TSFlags: 0x00, /* TSFlags */
917 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
918 .CoveredBySubRegs: true, /* CoveredBySubRegs */
919 .SuperClasses: ZREGSuperclasses, .SuperClassesSize: 8,
920 .OrderFunc: nullptr
921 };
922
923} // end namespace AVR
924
925namespace {
926 const TargetRegisterClass *const RegisterClasses[] = {
927 &AVR::GPR8RegClass,
928 &AVR::GPR8NOZRegClass,
929 &AVR::GPR8loRegClass,
930 &AVR::LD8RegClass,
931 &AVR::GPR8NOZ_and_LD8RegClass,
932 &AVR::LD8loRegClass,
933 &AVR::CCRRegClass,
934 &AVR::DREGSRegClass,
935 &AVR::DREGSNOZRegClass,
936 &AVR::DREGSMOVWRegClass,
937 &AVR::DREGSMOVW_and_DREGSNOZRegClass,
938 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
939 &AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClass,
940 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
941 &AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClass,
942 &AVR::DREGS_with_sub_lo_in_GPR8loRegClass,
943 &AVR::DREGS_with_sub_hi_in_GPR8loRegClass,
944 &AVR::DLDREGSRegClass,
945 &AVR::DREGS_with_sub_hi_in_LD8loRegClass,
946 &AVR::DREGS_with_sub_lo_in_LD8loRegClass,
947 &AVR::DREGSloRegClass,
948 &AVR::DLDREGS_and_DREGSNOZRegClass,
949 &AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass,
950 &AVR::DREGSLD8loRegClass,
951 &AVR::IWREGSRegClass,
952 &AVR::DREGSNOZ_and_IWREGSRegClass,
953 &AVR::PTRREGSRegClass,
954 &AVR::DREGSNOZ_and_PTRREGSRegClass,
955 &AVR::PTRDISPREGSRegClass,
956 &AVR::DREGSNOZ_and_PTRDISPREGSRegClass,
957 &AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass,
958 &AVR::GPRSPRegClass,
959 &AVR::ZREGRegClass,
960 };
961} // end anonymous namespace
962
963static const uint8_t CostPerUseTable[] = {
9640, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
965
966
967static const bool InAllocatableClassTable[] = {
968false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
969
970
971static const TargetRegisterInfoDesc AVRRegInfoDesc = { // Extra Descriptors
972.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
973
974unsigned AVRGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
975 static const uint8_t Rows[1][2] = {
976 { 0, 0, },
977 };
978
979 --IdxA; assert(IdxA < 2); (void) IdxA;
980 --IdxB; assert(IdxB < 2);
981 return Rows[0][IdxB];
982}
983
984unsigned AVRGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
985 static const uint8_t Table[2][2] = {
986 { 0, 0, },
987 { 0, 0, },
988 };
989
990 --IdxA; assert(IdxA < 2);
991 --IdxB; assert(IdxB < 2);
992 return Table[IdxA][IdxB];
993 }
994
995 struct MaskRolOp {
996 LaneBitmask Mask;
997 uint8_t RotateLeft;
998 };
999 static const MaskRolOp LaneMaskComposeSequences[] = {
1000 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
1001 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 2
1002 };
1003 static const uint8_t CompositeSequences[] = {
1004 0, // to sub_hi
1005 2 // to sub_lo
1006 };
1007
1008LaneBitmask AVRGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1009 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1010 LaneBitmask Result;
1011 for (const MaskRolOp *Ops =
1012 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1013 Ops->Mask.any(); ++Ops) {
1014 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1015 if (unsigned S = Ops->RotateLeft)
1016 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1017 else
1018 Result |= LaneBitmask(M);
1019 }
1020 return Result;
1021}
1022
1023LaneBitmask AVRGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1024 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
1025 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1026 LaneBitmask Result;
1027 for (const MaskRolOp *Ops =
1028 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1029 Ops->Mask.any(); ++Ops) {
1030 LaneBitmask::Type M = LaneMask.getAsInteger();
1031 if (unsigned S = Ops->RotateLeft)
1032 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1033 else
1034 Result |= LaneBitmask(M);
1035 }
1036 return Result;
1037}
1038
1039const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1040 static const uint8_t Table[33][2] = {
1041 { // GPR8
1042 0, // sub_hi
1043 0, // sub_lo
1044 },
1045 { // GPR8NOZ
1046 0, // sub_hi
1047 0, // sub_lo
1048 },
1049 { // GPR8lo
1050 0, // sub_hi
1051 0, // sub_lo
1052 },
1053 { // LD8
1054 0, // sub_hi
1055 0, // sub_lo
1056 },
1057 { // GPR8NOZ_and_LD8
1058 0, // sub_hi
1059 0, // sub_lo
1060 },
1061 { // LD8lo
1062 0, // sub_hi
1063 0, // sub_lo
1064 },
1065 { // CCR
1066 0, // sub_hi
1067 0, // sub_lo
1068 },
1069 { // DREGS
1070 8, // sub_hi -> DREGS
1071 8, // sub_lo -> DREGS
1072 },
1073 { // DREGSNOZ
1074 9, // sub_hi -> DREGSNOZ
1075 9, // sub_lo -> DREGSNOZ
1076 },
1077 { // DREGSMOVW
1078 10, // sub_hi -> DREGSMOVW
1079 10, // sub_lo -> DREGSMOVW
1080 },
1081 { // DREGSMOVW_and_DREGSNOZ
1082 11, // sub_hi -> DREGSMOVW_and_DREGSNOZ
1083 11, // sub_lo -> DREGSMOVW_and_DREGSNOZ
1084 },
1085 { // DREGS_with_sub_hi_in_LD8
1086 12, // sub_hi -> DREGS_with_sub_hi_in_LD8
1087 12, // sub_lo -> DREGS_with_sub_hi_in_LD8
1088 },
1089 { // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1090 13, // sub_hi -> DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1091 13, // sub_lo -> DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1092 },
1093 { // DREGS_with_sub_lo_in_LD8
1094 14, // sub_hi -> DREGS_with_sub_lo_in_LD8
1095 14, // sub_lo -> DREGS_with_sub_lo_in_LD8
1096 },
1097 { // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1098 15, // sub_hi -> DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1099 15, // sub_lo -> DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1100 },
1101 { // DREGS_with_sub_lo_in_GPR8lo
1102 16, // sub_hi -> DREGS_with_sub_lo_in_GPR8lo
1103 16, // sub_lo -> DREGS_with_sub_lo_in_GPR8lo
1104 },
1105 { // DREGS_with_sub_hi_in_GPR8lo
1106 17, // sub_hi -> DREGS_with_sub_hi_in_GPR8lo
1107 17, // sub_lo -> DREGS_with_sub_hi_in_GPR8lo
1108 },
1109 { // DLDREGS
1110 18, // sub_hi -> DLDREGS
1111 18, // sub_lo -> DLDREGS
1112 },
1113 { // DREGS_with_sub_hi_in_LD8lo
1114 19, // sub_hi -> DREGS_with_sub_hi_in_LD8lo
1115 19, // sub_lo -> DREGS_with_sub_hi_in_LD8lo
1116 },
1117 { // DREGS_with_sub_lo_in_LD8lo
1118 20, // sub_hi -> DREGS_with_sub_lo_in_LD8lo
1119 20, // sub_lo -> DREGS_with_sub_lo_in_LD8lo
1120 },
1121 { // DREGSlo
1122 21, // sub_hi -> DREGSlo
1123 21, // sub_lo -> DREGSlo
1124 },
1125 { // DLDREGS_and_DREGSNOZ
1126 22, // sub_hi -> DLDREGS_and_DREGSNOZ
1127 22, // sub_lo -> DLDREGS_and_DREGSNOZ
1128 },
1129 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1130 23, // sub_hi -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1131 23, // sub_lo -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1132 },
1133 { // DREGSLD8lo
1134 24, // sub_hi -> DREGSLD8lo
1135 24, // sub_lo -> DREGSLD8lo
1136 },
1137 { // IWREGS
1138 25, // sub_hi -> IWREGS
1139 25, // sub_lo -> IWREGS
1140 },
1141 { // DREGSNOZ_and_IWREGS
1142 26, // sub_hi -> DREGSNOZ_and_IWREGS
1143 26, // sub_lo -> DREGSNOZ_and_IWREGS
1144 },
1145 { // PTRREGS
1146 27, // sub_hi -> PTRREGS
1147 27, // sub_lo -> PTRREGS
1148 },
1149 { // DREGSNOZ_and_PTRREGS
1150 28, // sub_hi -> DREGSNOZ_and_PTRREGS
1151 28, // sub_lo -> DREGSNOZ_and_PTRREGS
1152 },
1153 { // PTRDISPREGS
1154 29, // sub_hi -> PTRDISPREGS
1155 29, // sub_lo -> PTRDISPREGS
1156 },
1157 { // DREGSNOZ_and_PTRDISPREGS
1158 30, // sub_hi -> DREGSNOZ_and_PTRDISPREGS
1159 30, // sub_lo -> DREGSNOZ_and_PTRDISPREGS
1160 },
1161 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1162 31, // sub_hi -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1163 31, // sub_lo -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1164 },
1165 { // GPRSP
1166 32, // sub_hi -> GPRSP
1167 32, // sub_lo -> GPRSP
1168 },
1169 { // ZREG
1170 33, // sub_hi -> ZREG
1171 33, // sub_lo -> ZREG
1172 },
1173 };
1174 assert(RC && "Missing regclass");
1175 if (!Idx) return RC;
1176 --Idx;
1177 assert(Idx < 2 && "Bad subreg");
1178 unsigned TV = Table[RC->getID()][Idx];
1179 return TV ? getRegClass(i: TV - 1) : nullptr;
1180}
1181
1182const TargetRegisterClass *AVRGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1183 static const uint8_t Table[33][2] = {
1184 { // GPR8
1185 0, // GPR8:sub_hi
1186 0, // GPR8:sub_lo
1187 },
1188 { // GPR8NOZ
1189 0, // GPR8NOZ:sub_hi
1190 0, // GPR8NOZ:sub_lo
1191 },
1192 { // GPR8lo
1193 0, // GPR8lo:sub_hi
1194 0, // GPR8lo:sub_lo
1195 },
1196 { // LD8
1197 0, // LD8:sub_hi
1198 0, // LD8:sub_lo
1199 },
1200 { // GPR8NOZ_and_LD8
1201 0, // GPR8NOZ_and_LD8:sub_hi
1202 0, // GPR8NOZ_and_LD8:sub_lo
1203 },
1204 { // LD8lo
1205 0, // LD8lo:sub_hi
1206 0, // LD8lo:sub_lo
1207 },
1208 { // CCR
1209 0, // CCR:sub_hi
1210 0, // CCR:sub_lo
1211 },
1212 { // DREGS
1213 1, // DREGS:sub_hi -> GPR8
1214 1, // DREGS:sub_lo -> GPR8
1215 },
1216 { // DREGSNOZ
1217 2, // DREGSNOZ:sub_hi -> GPR8NOZ
1218 2, // DREGSNOZ:sub_lo -> GPR8NOZ
1219 },
1220 { // DREGSMOVW
1221 1, // DREGSMOVW:sub_hi -> GPR8
1222 1, // DREGSMOVW:sub_lo -> GPR8
1223 },
1224 { // DREGSMOVW_and_DREGSNOZ
1225 2, // DREGSMOVW_and_DREGSNOZ:sub_hi -> GPR8NOZ
1226 2, // DREGSMOVW_and_DREGSNOZ:sub_lo -> GPR8NOZ
1227 },
1228 { // DREGS_with_sub_hi_in_LD8
1229 4, // DREGS_with_sub_hi_in_LD8:sub_hi -> LD8
1230 1, // DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8
1231 },
1232 { // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1233 5, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8:sub_hi -> GPR8NOZ_and_LD8
1234 2, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8NOZ
1235 },
1236 { // DREGS_with_sub_lo_in_LD8
1237 4, // DREGS_with_sub_lo_in_LD8:sub_hi -> LD8
1238 4, // DREGS_with_sub_lo_in_LD8:sub_lo -> LD8
1239 },
1240 { // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1241 5, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8:sub_hi -> GPR8NOZ_and_LD8
1242 5, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8:sub_lo -> GPR8NOZ_and_LD8
1243 },
1244 { // DREGS_with_sub_lo_in_GPR8lo
1245 2, // DREGS_with_sub_lo_in_GPR8lo:sub_hi -> GPR8NOZ
1246 3, // DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1247 },
1248 { // DREGS_with_sub_hi_in_GPR8lo
1249 3, // DREGS_with_sub_hi_in_GPR8lo:sub_hi -> GPR8lo
1250 3, // DREGS_with_sub_hi_in_GPR8lo:sub_lo -> GPR8lo
1251 },
1252 { // DLDREGS
1253 4, // DLDREGS:sub_hi -> LD8
1254 4, // DLDREGS:sub_lo -> LD8
1255 },
1256 { // DREGS_with_sub_hi_in_LD8lo
1257 6, // DREGS_with_sub_hi_in_LD8lo:sub_hi -> LD8lo
1258 2, // DREGS_with_sub_hi_in_LD8lo:sub_lo -> GPR8NOZ
1259 },
1260 { // DREGS_with_sub_lo_in_LD8lo
1261 5, // DREGS_with_sub_lo_in_LD8lo:sub_hi -> GPR8NOZ_and_LD8
1262 6, // DREGS_with_sub_lo_in_LD8lo:sub_lo -> LD8lo
1263 },
1264 { // DREGSlo
1265 3, // DREGSlo:sub_hi -> GPR8lo
1266 3, // DREGSlo:sub_lo -> GPR8lo
1267 },
1268 { // DLDREGS_and_DREGSNOZ
1269 5, // DLDREGS_and_DREGSNOZ:sub_hi -> GPR8NOZ_and_LD8
1270 5, // DLDREGS_and_DREGSNOZ:sub_lo -> GPR8NOZ_and_LD8
1271 },
1272 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1273 6, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_hi -> LD8lo
1274 6, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_lo -> LD8lo
1275 },
1276 { // DREGSLD8lo
1277 6, // DREGSLD8lo:sub_hi -> LD8lo
1278 6, // DREGSLD8lo:sub_lo -> LD8lo
1279 },
1280 { // IWREGS
1281 4, // IWREGS:sub_hi -> LD8
1282 4, // IWREGS:sub_lo -> LD8
1283 },
1284 { // DREGSNOZ_and_IWREGS
1285 5, // DREGSNOZ_and_IWREGS:sub_hi -> GPR8NOZ_and_LD8
1286 5, // DREGSNOZ_and_IWREGS:sub_lo -> GPR8NOZ_and_LD8
1287 },
1288 { // PTRREGS
1289 4, // PTRREGS:sub_hi -> LD8
1290 4, // PTRREGS:sub_lo -> LD8
1291 },
1292 { // DREGSNOZ_and_PTRREGS
1293 5, // DREGSNOZ_and_PTRREGS:sub_hi -> GPR8NOZ_and_LD8
1294 5, // DREGSNOZ_and_PTRREGS:sub_lo -> GPR8NOZ_and_LD8
1295 },
1296 { // PTRDISPREGS
1297 4, // PTRDISPREGS:sub_hi -> LD8
1298 4, // PTRDISPREGS:sub_lo -> LD8
1299 },
1300 { // DREGSNOZ_and_PTRDISPREGS
1301 5, // DREGSNOZ_and_PTRDISPREGS:sub_hi -> GPR8NOZ_and_LD8
1302 5, // DREGSNOZ_and_PTRDISPREGS:sub_lo -> GPR8NOZ_and_LD8
1303 },
1304 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1305 6, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_hi -> LD8lo
1306 3, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1307 },
1308 { // GPRSP
1309 0, // GPRSP:sub_hi
1310 0, // GPRSP:sub_lo
1311 },
1312 { // ZREG
1313 4, // ZREG:sub_hi -> LD8
1314 4, // ZREG:sub_lo -> LD8
1315 },
1316 };
1317 assert(RC && "Missing regclass");
1318 if (!Idx) return RC;
1319 --Idx;
1320 assert(Idx < 2 && "Bad subreg");
1321 unsigned TV = Table[RC->getID()][Idx];
1322 return TV ? getRegClass(i: TV - 1) : nullptr;
1323}
1324
1325/// Get the weight in units of pressure for this register class.
1326const RegClassWeight &AVRGenRegisterInfo::
1327getRegClassWeight(const TargetRegisterClass *RC) const {
1328 static const RegClassWeight RCWeightTable[] = {
1329 {.RegWeight: 1, .WeightLimit: 32}, // GPR8
1330 {.RegWeight: 1, .WeightLimit: 30}, // GPR8NOZ
1331 {.RegWeight: 1, .WeightLimit: 16}, // GPR8lo
1332 {.RegWeight: 1, .WeightLimit: 16}, // LD8
1333 {.RegWeight: 1, .WeightLimit: 14}, // GPR8NOZ_and_LD8
1334 {.RegWeight: 1, .WeightLimit: 8}, // LD8lo
1335 {.RegWeight: 1, .WeightLimit: 1}, // CCR
1336 {.RegWeight: 2, .WeightLimit: 32}, // DREGS
1337 {.RegWeight: 2, .WeightLimit: 30}, // DREGSNOZ
1338 {.RegWeight: 2, .WeightLimit: 32}, // DREGSMOVW
1339 {.RegWeight: 2, .WeightLimit: 30}, // DREGSMOVW_and_DREGSNOZ
1340 {.RegWeight: 2, .WeightLimit: 17}, // DREGS_with_sub_hi_in_LD8
1341 {.RegWeight: 2, .WeightLimit: 15}, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1342 {.RegWeight: 2, .WeightLimit: 16}, // DREGS_with_sub_lo_in_LD8
1343 {.RegWeight: 2, .WeightLimit: 14}, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1344 {.RegWeight: 2, .WeightLimit: 17}, // DREGS_with_sub_lo_in_GPR8lo
1345 {.RegWeight: 2, .WeightLimit: 16}, // DREGS_with_sub_hi_in_GPR8lo
1346 {.RegWeight: 2, .WeightLimit: 16}, // DLDREGS
1347 {.RegWeight: 2, .WeightLimit: 9}, // DREGS_with_sub_hi_in_LD8lo
1348 {.RegWeight: 2, .WeightLimit: 9}, // DREGS_with_sub_lo_in_LD8lo
1349 {.RegWeight: 2, .WeightLimit: 16}, // DREGSlo
1350 {.RegWeight: 2, .WeightLimit: 14}, // DLDREGS_and_DREGSNOZ
1351 {.RegWeight: 2, .WeightLimit: 8}, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1352 {.RegWeight: 2, .WeightLimit: 8}, // DREGSLD8lo
1353 {.RegWeight: 2, .WeightLimit: 8}, // IWREGS
1354 {.RegWeight: 2, .WeightLimit: 6}, // DREGSNOZ_and_IWREGS
1355 {.RegWeight: 2, .WeightLimit: 6}, // PTRREGS
1356 {.RegWeight: 2, .WeightLimit: 4}, // DREGSNOZ_and_PTRREGS
1357 {.RegWeight: 2, .WeightLimit: 4}, // PTRDISPREGS
1358 {.RegWeight: 2, .WeightLimit: 2}, // DREGSNOZ_and_PTRDISPREGS
1359 {.RegWeight: 2, .WeightLimit: 2}, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1360 {.RegWeight: 2, .WeightLimit: 2}, // GPRSP
1361 {.RegWeight: 2, .WeightLimit: 2}, // ZREG
1362 };
1363 return RCWeightTable[RC->getID()];
1364}
1365
1366/// Get the weight in units of pressure for this register unit.
1367unsigned AVRGenRegisterInfo::
1368getRegUnitWeight(MCRegUnit RegUnit) const {
1369 assert(static_cast<unsigned>(RegUnit) < 35 && "invalid register unit");
1370 // All register units have unit weight.
1371 return 1;
1372}
1373
1374
1375// Get the number of dimensions of register pressure.
1376unsigned AVRGenRegisterInfo::getNumRegPressureSets() const {
1377 return 9;
1378}
1379
1380// Get the name of this register unit pressure set.
1381const char *AVRGenRegisterInfo::
1382getRegPressureSetName(unsigned Idx) const {
1383 static const char *PressureNameTable[] = {
1384 "CCR",
1385 "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo",
1386 "GPRSP",
1387 "IWREGS",
1388 "LD8lo",
1389 "LD8",
1390 "GPR8lo",
1391 "GPR8lo_with_LD8lo",
1392 "GPR8",
1393 };
1394 return PressureNameTable[Idx];
1395}
1396
1397// Get the register unit pressure limit for this dimension.
1398// This limit must be adjusted dynamically for reserved registers.
1399unsigned AVRGenRegisterInfo::
1400getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1401 static const uint8_t PressureLimitTable[] = {
1402 1, // 0: CCR
1403 2, // 1: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1404 2, // 2: GPRSP
1405 8, // 3: IWREGS
1406 10, // 4: LD8lo
1407 17, // 5: LD8
1408 17, // 6: GPR8lo
1409 25, // 7: GPR8lo_with_LD8lo
1410 32, // 8: GPR8
1411 };
1412 return PressureLimitTable[Idx];
1413}
1414
1415/// Table of pressure sets per register class or unit.
1416static const int RCSetsTable[] = {
1417 /* 0 */ 0, -1,
1418 /* 2 */ 2, -1,
1419 /* 4 */ 3, 5, 8, -1,
1420 /* 8 */ 3, 4, 5, 7, 8, -1,
1421 /* 14 */ 1, 4, 5, 6, 7, 8, -1,
1422};
1423
1424/// Get the dimensions of register pressure impacted by this register class.
1425/// Returns a -1 terminated array of pressure set IDs
1426const int *AVRGenRegisterInfo::
1427getRegClassPressureSets(const TargetRegisterClass *RC) const {
1428 static const uint8_t RCSetStartTable[] = {
1429 6,6,17,5,5,9,0,6,6,6,6,5,5,5,5,17,17,5,9,9,17,5,9,9,4,4,4,4,4,4,14,2,4,};
1430 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1431}
1432
1433/// Get the dimensions of register pressure impacted by this register unit.
1434/// Returns a -1 terminated array of pressure set IDs
1435const int *AVRGenRegisterInfo::
1436getRegUnitPressureSets(MCRegUnit RegUnit) const {
1437 assert(static_cast<unsigned>(RegUnit) < 35 && "invalid register unit");
1438 static const uint8_t RUSetStartTable[] = {
1439 2,2,0,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,14,14,9,9,9,9,9,9,9,8,4,4,4,4,4,4,4,};
1440 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1441}
1442
1443extern const MCRegisterDesc AVRRegDesc[];
1444extern const int16_t AVRRegDiffLists[];
1445extern const LaneBitmask AVRLaneMaskLists[];
1446extern const char AVRRegStrings[];
1447extern const char AVRRegClassStrings[];
1448extern const MCPhysReg AVRRegUnitRoots[][2];
1449extern const uint16_t AVRSubRegIdxLists[];
1450extern const uint16_t AVRRegEncodingTable[];
1451// AVR Dwarf<->LLVM register mappings.
1452extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[];
1453extern const unsigned AVRDwarfFlavour0Dwarf2LSize;
1454
1455extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[];
1456extern const unsigned AVREHFlavour0Dwarf2LSize;
1457
1458extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[];
1459extern const unsigned AVRDwarfFlavour0L2DwarfSize;
1460
1461extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[];
1462extern const unsigned AVREHFlavour0L2DwarfSize;
1463
1464AVRGenRegisterInfo::
1465AVRGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1466 unsigned PC, unsigned HwMode)
1467 : TargetRegisterInfo(&AVRRegInfoDesc, RegisterClasses, RegisterClasses+33,
1468 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1469 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
1470 InitMCRegisterInfo(D: AVRRegDesc, NR: 62, RA, PC,
1471 C: AVRMCRegisterClasses, NC: 33,
1472 RURoots: AVRRegUnitRoots,
1473 NRU: 35,
1474 DL: AVRRegDiffLists,
1475 RUMS: AVRLaneMaskLists,
1476 Strings: AVRRegStrings,
1477 ClassStrings: AVRRegClassStrings,
1478 SubIndices: AVRSubRegIdxLists,
1479 NumIndices: 3,
1480 RET: AVRRegEncodingTable);
1481
1482 switch (DwarfFlavour) {
1483 default:
1484 llvm_unreachable("Unknown DWARF flavour");
1485 case 0:
1486 mapDwarfRegsToLLVMRegs(Map: AVRDwarfFlavour0Dwarf2L, Size: AVRDwarfFlavour0Dwarf2LSize, isEH: false);
1487 break;
1488 }
1489 switch (EHFlavour) {
1490 default:
1491 llvm_unreachable("Unknown DWARF flavour");
1492 case 0:
1493 mapDwarfRegsToLLVMRegs(Map: AVREHFlavour0Dwarf2L, Size: AVREHFlavour0Dwarf2LSize, isEH: true);
1494 break;
1495 }
1496 switch (DwarfFlavour) {
1497 default:
1498 llvm_unreachable("Unknown DWARF flavour");
1499 case 0:
1500 mapLLVMRegsToDwarfRegs(Map: AVRDwarfFlavour0L2Dwarf, Size: AVRDwarfFlavour0L2DwarfSize, isEH: false);
1501 break;
1502 }
1503 switch (EHFlavour) {
1504 default:
1505 llvm_unreachable("Unknown DWARF flavour");
1506 case 0:
1507 mapLLVMRegsToDwarfRegs(Map: AVREHFlavour0L2Dwarf, Size: AVREHFlavour0L2DwarfSize, isEH: true);
1508 break;
1509 }
1510}
1511
1512static const MCPhysReg CSR_Interrupts_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
1513static const uint32_t CSR_Interrupts_RegMask[] = { 0xffffff80, 0x3fffffdf, };
1514static const MCPhysReg CSR_InterruptsTiny_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, 0 };
1515static const uint32_t CSR_InterruptsTiny_RegMask[] = { 0xff800000, 0x3ff8001f, };
1516static const MCPhysReg CSR_Normal_SaveList[] = { AVR::R29, AVR::R28, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
1517static const uint32_t CSR_Normal_RegMask[] = { 0x007fff80, 0x1003ffc6, };
1518static const MCPhysReg CSR_NormalTiny_SaveList[] = { AVR::R29, AVR::R28, AVR::R19, AVR::R18, 0 };
1519static const uint32_t CSR_NormalTiny_RegMask[] = { 0x01800000, 0x10080006, };
1520
1521
1522ArrayRef<const uint32_t *> AVRGenRegisterInfo::getRegMasks() const {
1523 static const uint32_t *const Masks[] = {
1524 CSR_Interrupts_RegMask,
1525 CSR_InterruptsTiny_RegMask,
1526 CSR_Normal_RegMask,
1527 CSR_NormalTiny_RegMask,
1528 };
1529 return ArrayRef(Masks);
1530}
1531
1532bool AVRGenRegisterInfo::
1533isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1534 return
1535 false;
1536}
1537
1538bool AVRGenRegisterInfo::
1539isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1540 return
1541 false;
1542}
1543
1544bool AVRGenRegisterInfo::
1545isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1546 return
1547 false;
1548}
1549
1550bool AVRGenRegisterInfo::
1551isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1552 return
1553 false;
1554}
1555
1556bool AVRGenRegisterInfo::
1557isConstantPhysReg(MCRegister PhysReg) const {
1558 return
1559 false;
1560}
1561
1562ArrayRef<const char *> AVRGenRegisterInfo::getRegMaskNames() const {
1563 static const char *Names[] = {
1564 "CSR_Interrupts",
1565 "CSR_InterruptsTiny",
1566 "CSR_Normal",
1567 "CSR_NormalTiny",
1568 };
1569 return ArrayRef(Names);
1570}
1571
1572const AVRFrameLowering *
1573AVRGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1574 return static_cast<const AVRFrameLowering *>(
1575 MF.getSubtarget().getFrameLowering());
1576}
1577
1578} // end namespace llvm
1579
1580