1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass AVRMCRegisterClasses[];
12
13static const MVT::SimpleValueType AVRVTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char AVRSubRegIndexStrings[] = {
23 /* 0 */ "sub_hi\000"
24 /* 7 */ "sub_lo\000"
25};
26#ifdef __GNUC__
27#pragma GCC diagnostic pop
28#endif
29
30
31static constexpr uint32_t AVRSubRegIndexNameOffsets[] = {
32 0,
33 7,
34};
35
36static const TargetRegisterInfo::SubRegCoveredBits AVRSubRegIdxRangeTable[] = {
37 { .Offset: 4294967295, .Size: 4294967295 },
38 { .Offset: 8, .Size: 8 }, // sub_hi
39 { .Offset: 0, .Size: 8 }, // sub_lo
40};
41
42
43static const LaneBitmask AVRSubRegIndexLaneMaskTable[] = {
44 LaneBitmask::getAll(),
45 LaneBitmask(0x0000000000000001), // sub_hi
46 LaneBitmask(0x0000000000000002), // sub_lo
47 };
48
49
50
51static const TargetRegisterInfo::RegClassInfo AVRRegClassInfos[] = {
52 // Mode = 0 (DefaultMode)
53 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // GPR8
54 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // GPR8NOZ
55 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // GPR8lo
56 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // LD8
57 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // GPR8NOZ_and_LD8
58 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // LD8lo
59 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // CCR
60 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS
61 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ
62 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSMOVW
63 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSMOVW_and_DREGSNOZ
64 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8
65 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
66 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_LD8
67 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
68 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_GPR8lo
69 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_GPR8lo
70 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DLDREGS
71 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8lo
72 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_LD8lo
73 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSlo
74 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DLDREGS_and_DREGSNOZ
75 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
76 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSLD8lo
77 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // IWREGS
78 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_IWREGS
79 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // PTRREGS
80 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_PTRREGS
81 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // PTRDISPREGS
82 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_PTRDISPREGS
83 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
84 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // GPRSP
85 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // ZREG
86};
87static const uint32_t GPR8SubClassMask[] = {
88 0x0000003f, 0x00000000,
89 0x7fffff80, 0x00000001, // sub_hi
90 0x7fffff80, 0x00000001, // sub_lo
91};
92
93static const uint32_t GPR8NOZSubClassMask[] = {
94 0x00000036, 0x00000000,
95 0x6afdd500, 0x00000000, // sub_hi
96 0x6afdd500, 0x00000000, // sub_lo
97};
98
99static const uint32_t GPR8loSubClassMask[] = {
100 0x00000004, 0x00000000,
101 0x00110000, 0x00000000, // sub_hi
102 0x40118000, 0x00000000, // sub_lo
103};
104
105static const uint32_t LD8SubClassMask[] = {
106 0x00000038, 0x00000000,
107 0x7fee7800, 0x00000001, // sub_hi
108 0x3fea6000, 0x00000001, // sub_lo
109};
110
111static const uint32_t GPR8NOZ_and_LD8SubClassMask[] = {
112 0x00000030, 0x00000000,
113 0x6aec5000, 0x00000000, // sub_hi
114 0x2ae84000, 0x00000000, // sub_lo
115};
116
117static const uint32_t LD8loSubClassMask[] = {
118 0x00000020, 0x00000000,
119 0x40c40000, 0x00000000, // sub_hi
120 0x00c80000, 0x00000000, // sub_lo
121};
122
123static const uint32_t CCRSubClassMask[] = {
124 0x00000040, 0x00000000,
125};
126
127static const uint32_t DREGSSubClassMask[] = {
128 0x7fffff80, 0x00000001,
129};
130
131static const uint32_t DREGSNOZSubClassMask[] = {
132 0x6afdd500, 0x00000000,
133};
134
135static const uint32_t DREGSMOVWSubClassMask[] = {
136 0x3fb20600, 0x00000001,
137};
138
139static const uint32_t DREGSMOVW_and_DREGSNOZSubClassMask[] = {
140 0x2ab00400, 0x00000000,
141};
142
143static const uint32_t DREGS_with_sub_hi_in_LD8SubClassMask[] = {
144 0x7fee7800, 0x00000001,
145};
146
147static const uint32_t DREGSNOZ_and_DREGS_with_sub_hi_in_LD8SubClassMask[] = {
148 0x6aec5000, 0x00000000,
149};
150
151static const uint32_t DREGS_with_sub_lo_in_LD8SubClassMask[] = {
152 0x3fea6000, 0x00000001,
153};
154
155static const uint32_t DREGSNOZ_and_DREGS_with_sub_lo_in_LD8SubClassMask[] = {
156 0x2ae84000, 0x00000000,
157};
158
159static const uint32_t DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
160 0x40118000, 0x00000000,
161};
162
163static const uint32_t DREGS_with_sub_hi_in_GPR8loSubClassMask[] = {
164 0x00110000, 0x00000000,
165};
166
167static const uint32_t DLDREGSSubClassMask[] = {
168 0x3fa20000, 0x00000001,
169};
170
171static const uint32_t DREGS_with_sub_hi_in_LD8loSubClassMask[] = {
172 0x40c40000, 0x00000000,
173};
174
175static const uint32_t DREGS_with_sub_lo_in_LD8loSubClassMask[] = {
176 0x00c80000, 0x00000000,
177};
178
179static const uint32_t DREGSloSubClassMask[] = {
180 0x00100000, 0x00000000,
181};
182
183static const uint32_t DLDREGS_and_DREGSNOZSubClassMask[] = {
184 0x2aa00000, 0x00000000,
185};
186
187static const uint32_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask[] = {
188 0x00c00000, 0x00000000,
189};
190
191static const uint32_t DREGSLD8loSubClassMask[] = {
192 0x00800000, 0x00000000,
193};
194
195static const uint32_t IWREGSSubClassMask[] = {
196 0x3f000000, 0x00000001,
197};
198
199static const uint32_t DREGSNOZ_and_IWREGSSubClassMask[] = {
200 0x2a000000, 0x00000000,
201};
202
203static const uint32_t PTRREGSSubClassMask[] = {
204 0x3c000000, 0x00000001,
205};
206
207static const uint32_t DREGSNOZ_and_PTRREGSSubClassMask[] = {
208 0x28000000, 0x00000000,
209};
210
211static const uint32_t PTRDISPREGSSubClassMask[] = {
212 0x30000000, 0x00000001,
213};
214
215static const uint32_t DREGSNOZ_and_PTRDISPREGSSubClassMask[] = {
216 0x20000000, 0x00000000,
217};
218
219static const uint32_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
220 0x40000000, 0x00000000,
221};
222
223static const uint32_t GPRSPSubClassMask[] = {
224 0x80000000, 0x00000000,
225};
226
227static const uint32_t ZREGSubClassMask[] = {
228 0x00000000, 0x00000001,
229};
230
231static const uint16_t SuperRegIdxSeqs[] = {
232 /* 0 */ 1, 2, 0,
233};
234
235static unsigned const GPR8NOZSuperclasses[] = {
236 AVR::GPR8RegClassID,
237};
238
239static unsigned const GPR8loSuperclasses[] = {
240 AVR::GPR8RegClassID,
241 AVR::GPR8NOZRegClassID,
242};
243
244static unsigned const LD8Superclasses[] = {
245 AVR::GPR8RegClassID,
246};
247
248static unsigned const GPR8NOZ_and_LD8Superclasses[] = {
249 AVR::GPR8RegClassID,
250 AVR::GPR8NOZRegClassID,
251 AVR::LD8RegClassID,
252};
253
254static unsigned const LD8loSuperclasses[] = {
255 AVR::GPR8RegClassID,
256 AVR::GPR8NOZRegClassID,
257 AVR::LD8RegClassID,
258 AVR::GPR8NOZ_and_LD8RegClassID,
259};
260
261static unsigned const DREGSNOZSuperclasses[] = {
262 AVR::DREGSRegClassID,
263};
264
265static unsigned const DREGSMOVWSuperclasses[] = {
266 AVR::DREGSRegClassID,
267};
268
269static unsigned const DREGSMOVW_and_DREGSNOZSuperclasses[] = {
270 AVR::DREGSRegClassID,
271 AVR::DREGSNOZRegClassID,
272 AVR::DREGSMOVWRegClassID,
273};
274
275static unsigned const DREGS_with_sub_hi_in_LD8Superclasses[] = {
276 AVR::DREGSRegClassID,
277};
278
279static unsigned const DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Superclasses[] = {
280 AVR::DREGSRegClassID,
281 AVR::DREGSNOZRegClassID,
282 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
283};
284
285static unsigned const DREGS_with_sub_lo_in_LD8Superclasses[] = {
286 AVR::DREGSRegClassID,
287 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
288};
289
290static unsigned const DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Superclasses[] = {
291 AVR::DREGSRegClassID,
292 AVR::DREGSNOZRegClassID,
293 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
294 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
295 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
296};
297
298static unsigned const DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
299 AVR::DREGSRegClassID,
300 AVR::DREGSNOZRegClassID,
301};
302
303static unsigned const DREGS_with_sub_hi_in_GPR8loSuperclasses[] = {
304 AVR::DREGSRegClassID,
305 AVR::DREGSNOZRegClassID,
306 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
307};
308
309static unsigned const DLDREGSSuperclasses[] = {
310 AVR::DREGSRegClassID,
311 AVR::DREGSMOVWRegClassID,
312 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
313 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
314};
315
316static unsigned const DREGS_with_sub_hi_in_LD8loSuperclasses[] = {
317 AVR::DREGSRegClassID,
318 AVR::DREGSNOZRegClassID,
319 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
320 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
321};
322
323static unsigned const DREGS_with_sub_lo_in_LD8loSuperclasses[] = {
324 AVR::DREGSRegClassID,
325 AVR::DREGSNOZRegClassID,
326 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
327 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
328 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
329 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
330};
331
332static unsigned const DREGSloSuperclasses[] = {
333 AVR::DREGSRegClassID,
334 AVR::DREGSNOZRegClassID,
335 AVR::DREGSMOVWRegClassID,
336 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
337 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
338 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID,
339};
340
341static unsigned const DLDREGS_and_DREGSNOZSuperclasses[] = {
342 AVR::DREGSRegClassID,
343 AVR::DREGSNOZRegClassID,
344 AVR::DREGSMOVWRegClassID,
345 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
346 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
347 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
348 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
349 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
350 AVR::DLDREGSRegClassID,
351};
352
353static unsigned const DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses[] = {
354 AVR::DREGSRegClassID,
355 AVR::DREGSNOZRegClassID,
356 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
357 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
358 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
359 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
360 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
361 AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
362};
363
364static unsigned const DREGSLD8loSuperclasses[] = {
365 AVR::DREGSRegClassID,
366 AVR::DREGSNOZRegClassID,
367 AVR::DREGSMOVWRegClassID,
368 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
369 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
370 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
371 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
372 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
373 AVR::DLDREGSRegClassID,
374 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
375 AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
376 AVR::DLDREGS_and_DREGSNOZRegClassID,
377 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID,
378};
379
380static unsigned const IWREGSSuperclasses[] = {
381 AVR::DREGSRegClassID,
382 AVR::DREGSMOVWRegClassID,
383 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
384 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
385 AVR::DLDREGSRegClassID,
386};
387
388static unsigned const DREGSNOZ_and_IWREGSSuperclasses[] = {
389 AVR::DREGSRegClassID,
390 AVR::DREGSNOZRegClassID,
391 AVR::DREGSMOVWRegClassID,
392 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
393 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
394 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
395 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
396 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
397 AVR::DLDREGSRegClassID,
398 AVR::DLDREGS_and_DREGSNOZRegClassID,
399 AVR::IWREGSRegClassID,
400};
401
402static unsigned const PTRREGSSuperclasses[] = {
403 AVR::DREGSRegClassID,
404 AVR::DREGSMOVWRegClassID,
405 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
406 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
407 AVR::DLDREGSRegClassID,
408 AVR::IWREGSRegClassID,
409};
410
411static unsigned const DREGSNOZ_and_PTRREGSSuperclasses[] = {
412 AVR::DREGSRegClassID,
413 AVR::DREGSNOZRegClassID,
414 AVR::DREGSMOVWRegClassID,
415 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
416 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
417 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
418 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
419 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
420 AVR::DLDREGSRegClassID,
421 AVR::DLDREGS_and_DREGSNOZRegClassID,
422 AVR::IWREGSRegClassID,
423 AVR::DREGSNOZ_and_IWREGSRegClassID,
424 AVR::PTRREGSRegClassID,
425};
426
427static unsigned const PTRDISPREGSSuperclasses[] = {
428 AVR::DREGSRegClassID,
429 AVR::DREGSMOVWRegClassID,
430 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
431 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
432 AVR::DLDREGSRegClassID,
433 AVR::IWREGSRegClassID,
434 AVR::PTRREGSRegClassID,
435};
436
437static unsigned const DREGSNOZ_and_PTRDISPREGSSuperclasses[] = {
438 AVR::DREGSRegClassID,
439 AVR::DREGSNOZRegClassID,
440 AVR::DREGSMOVWRegClassID,
441 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
442 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
443 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
444 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
445 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
446 AVR::DLDREGSRegClassID,
447 AVR::DLDREGS_and_DREGSNOZRegClassID,
448 AVR::IWREGSRegClassID,
449 AVR::DREGSNOZ_and_IWREGSRegClassID,
450 AVR::PTRREGSRegClassID,
451 AVR::DREGSNOZ_and_PTRREGSRegClassID,
452 AVR::PTRDISPREGSRegClassID,
453};
454
455static unsigned const DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
456 AVR::DREGSRegClassID,
457 AVR::DREGSNOZRegClassID,
458 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
459 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
460 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
461 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
462};
463
464static unsigned const ZREGSuperclasses[] = {
465 AVR::DREGSRegClassID,
466 AVR::DREGSMOVWRegClassID,
467 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
468 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
469 AVR::DLDREGSRegClassID,
470 AVR::IWREGSRegClassID,
471 AVR::PTRREGSRegClassID,
472 AVR::PTRDISPREGSRegClassID,
473};
474
475namespace AVR {
476
477// Register class instances.
478 extern const TargetRegisterClass GPR8RegClass = {
479 .MC: &AVRMCRegisterClasses[GPR8RegClassID],
480 .SubClassMask: GPR8SubClassMask,
481 .SuperRegIndices: SuperRegIdxSeqs + 0,
482 .LaneMask: LaneBitmask(0x0000000000000001),
483 .AllocationPriority: 0,
484 .GlobalPriority: false,
485 .TSFlags: 0x00, /* TSFlags */
486 .SpillStackID: 0, /* SpillStackID */
487 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
488 .CoveredBySubRegs: false, /* CoveredBySubRegs */
489 .SuperClasses: nullptr, .SuperClassesSize: 0,
490 .OrderFunc: nullptr
491 };
492
493 extern const TargetRegisterClass GPR8NOZRegClass = {
494 .MC: &AVRMCRegisterClasses[GPR8NOZRegClassID],
495 .SubClassMask: GPR8NOZSubClassMask,
496 .SuperRegIndices: SuperRegIdxSeqs + 0,
497 .LaneMask: LaneBitmask(0x0000000000000001),
498 .AllocationPriority: 0,
499 .GlobalPriority: false,
500 .TSFlags: 0x00, /* TSFlags */
501 .SpillStackID: 0, /* SpillStackID */
502 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
503 .CoveredBySubRegs: false, /* CoveredBySubRegs */
504 .SuperClasses: GPR8NOZSuperclasses, .SuperClassesSize: 1,
505 .OrderFunc: nullptr
506 };
507
508 extern const TargetRegisterClass GPR8loRegClass = {
509 .MC: &AVRMCRegisterClasses[GPR8loRegClassID],
510 .SubClassMask: GPR8loSubClassMask,
511 .SuperRegIndices: SuperRegIdxSeqs + 0,
512 .LaneMask: LaneBitmask(0x0000000000000001),
513 .AllocationPriority: 0,
514 .GlobalPriority: false,
515 .TSFlags: 0x00, /* TSFlags */
516 .SpillStackID: 0, /* SpillStackID */
517 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
518 .CoveredBySubRegs: false, /* CoveredBySubRegs */
519 .SuperClasses: GPR8loSuperclasses, .SuperClassesSize: 2,
520 .OrderFunc: nullptr
521 };
522
523 extern const TargetRegisterClass LD8RegClass = {
524 .MC: &AVRMCRegisterClasses[LD8RegClassID],
525 .SubClassMask: LD8SubClassMask,
526 .SuperRegIndices: SuperRegIdxSeqs + 0,
527 .LaneMask: LaneBitmask(0x0000000000000001),
528 .AllocationPriority: 0,
529 .GlobalPriority: false,
530 .TSFlags: 0x00, /* TSFlags */
531 .SpillStackID: 0, /* SpillStackID */
532 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
533 .CoveredBySubRegs: false, /* CoveredBySubRegs */
534 .SuperClasses: LD8Superclasses, .SuperClassesSize: 1,
535 .OrderFunc: nullptr
536 };
537
538 extern const TargetRegisterClass GPR8NOZ_and_LD8RegClass = {
539 .MC: &AVRMCRegisterClasses[GPR8NOZ_and_LD8RegClassID],
540 .SubClassMask: GPR8NOZ_and_LD8SubClassMask,
541 .SuperRegIndices: SuperRegIdxSeqs + 0,
542 .LaneMask: LaneBitmask(0x0000000000000001),
543 .AllocationPriority: 0,
544 .GlobalPriority: false,
545 .TSFlags: 0x00, /* TSFlags */
546 .SpillStackID: 0, /* SpillStackID */
547 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
548 .CoveredBySubRegs: false, /* CoveredBySubRegs */
549 .SuperClasses: GPR8NOZ_and_LD8Superclasses, .SuperClassesSize: 3,
550 .OrderFunc: nullptr
551 };
552
553 extern const TargetRegisterClass LD8loRegClass = {
554 .MC: &AVRMCRegisterClasses[LD8loRegClassID],
555 .SubClassMask: LD8loSubClassMask,
556 .SuperRegIndices: SuperRegIdxSeqs + 0,
557 .LaneMask: LaneBitmask(0x0000000000000001),
558 .AllocationPriority: 0,
559 .GlobalPriority: false,
560 .TSFlags: 0x00, /* TSFlags */
561 .SpillStackID: 0, /* SpillStackID */
562 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
563 .CoveredBySubRegs: false, /* CoveredBySubRegs */
564 .SuperClasses: LD8loSuperclasses, .SuperClassesSize: 4,
565 .OrderFunc: nullptr
566 };
567
568 extern const TargetRegisterClass CCRRegClass = {
569 .MC: &AVRMCRegisterClasses[CCRRegClassID],
570 .SubClassMask: CCRSubClassMask,
571 .SuperRegIndices: SuperRegIdxSeqs + 2,
572 .LaneMask: LaneBitmask(0x0000000000000001),
573 .AllocationPriority: 0,
574 .GlobalPriority: false,
575 .TSFlags: 0x00, /* TSFlags */
576 .SpillStackID: 0, /* SpillStackID */
577 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
578 .CoveredBySubRegs: false, /* CoveredBySubRegs */
579 .SuperClasses: nullptr, .SuperClassesSize: 0,
580 .OrderFunc: nullptr
581 };
582
583 extern const TargetRegisterClass DREGSRegClass = {
584 .MC: &AVRMCRegisterClasses[DREGSRegClassID],
585 .SubClassMask: DREGSSubClassMask,
586 .SuperRegIndices: SuperRegIdxSeqs + 2,
587 .LaneMask: LaneBitmask(0x0000000000000003),
588 .AllocationPriority: 0,
589 .GlobalPriority: false,
590 .TSFlags: 0x00, /* TSFlags */
591 .SpillStackID: 0, /* SpillStackID */
592 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
593 .CoveredBySubRegs: true, /* CoveredBySubRegs */
594 .SuperClasses: nullptr, .SuperClassesSize: 0,
595 .OrderFunc: nullptr
596 };
597
598 extern const TargetRegisterClass DREGSNOZRegClass = {
599 .MC: &AVRMCRegisterClasses[DREGSNOZRegClassID],
600 .SubClassMask: DREGSNOZSubClassMask,
601 .SuperRegIndices: SuperRegIdxSeqs + 2,
602 .LaneMask: LaneBitmask(0x0000000000000003),
603 .AllocationPriority: 0,
604 .GlobalPriority: false,
605 .TSFlags: 0x00, /* TSFlags */
606 .SpillStackID: 0, /* SpillStackID */
607 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
608 .CoveredBySubRegs: true, /* CoveredBySubRegs */
609 .SuperClasses: DREGSNOZSuperclasses, .SuperClassesSize: 1,
610 .OrderFunc: nullptr
611 };
612
613 extern const TargetRegisterClass DREGSMOVWRegClass = {
614 .MC: &AVRMCRegisterClasses[DREGSMOVWRegClassID],
615 .SubClassMask: DREGSMOVWSubClassMask,
616 .SuperRegIndices: SuperRegIdxSeqs + 2,
617 .LaneMask: LaneBitmask(0x0000000000000003),
618 .AllocationPriority: 0,
619 .GlobalPriority: false,
620 .TSFlags: 0x00, /* TSFlags */
621 .SpillStackID: 0, /* SpillStackID */
622 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
623 .CoveredBySubRegs: true, /* CoveredBySubRegs */
624 .SuperClasses: DREGSMOVWSuperclasses, .SuperClassesSize: 1,
625 .OrderFunc: nullptr
626 };
627
628 extern const TargetRegisterClass DREGSMOVW_and_DREGSNOZRegClass = {
629 .MC: &AVRMCRegisterClasses[DREGSMOVW_and_DREGSNOZRegClassID],
630 .SubClassMask: DREGSMOVW_and_DREGSNOZSubClassMask,
631 .SuperRegIndices: SuperRegIdxSeqs + 2,
632 .LaneMask: LaneBitmask(0x0000000000000003),
633 .AllocationPriority: 0,
634 .GlobalPriority: false,
635 .TSFlags: 0x00, /* TSFlags */
636 .SpillStackID: 0, /* SpillStackID */
637 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
638 .CoveredBySubRegs: true, /* CoveredBySubRegs */
639 .SuperClasses: DREGSMOVW_and_DREGSNOZSuperclasses, .SuperClassesSize: 3,
640 .OrderFunc: nullptr
641 };
642
643 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8RegClass = {
644 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8RegClassID],
645 .SubClassMask: DREGS_with_sub_hi_in_LD8SubClassMask,
646 .SuperRegIndices: SuperRegIdxSeqs + 2,
647 .LaneMask: LaneBitmask(0x0000000000000003),
648 .AllocationPriority: 0,
649 .GlobalPriority: false,
650 .TSFlags: 0x00, /* TSFlags */
651 .SpillStackID: 0, /* SpillStackID */
652 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
653 .CoveredBySubRegs: true, /* CoveredBySubRegs */
654 .SuperClasses: DREGS_with_sub_hi_in_LD8Superclasses, .SuperClassesSize: 1,
655 .OrderFunc: nullptr
656 };
657
658 extern const TargetRegisterClass DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClass = {
659 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID],
660 .SubClassMask: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8SubClassMask,
661 .SuperRegIndices: SuperRegIdxSeqs + 2,
662 .LaneMask: LaneBitmask(0x0000000000000003),
663 .AllocationPriority: 0,
664 .GlobalPriority: false,
665 .TSFlags: 0x00, /* TSFlags */
666 .SpillStackID: 0, /* SpillStackID */
667 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
668 .CoveredBySubRegs: true, /* CoveredBySubRegs */
669 .SuperClasses: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Superclasses, .SuperClassesSize: 3,
670 .OrderFunc: nullptr
671 };
672
673 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8RegClass = {
674 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8RegClassID],
675 .SubClassMask: DREGS_with_sub_lo_in_LD8SubClassMask,
676 .SuperRegIndices: SuperRegIdxSeqs + 2,
677 .LaneMask: LaneBitmask(0x0000000000000003),
678 .AllocationPriority: 0,
679 .GlobalPriority: false,
680 .TSFlags: 0x00, /* TSFlags */
681 .SpillStackID: 0, /* SpillStackID */
682 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
683 .CoveredBySubRegs: true, /* CoveredBySubRegs */
684 .SuperClasses: DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 2,
685 .OrderFunc: nullptr
686 };
687
688 extern const TargetRegisterClass DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClass = {
689 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID],
690 .SubClassMask: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8SubClassMask,
691 .SuperRegIndices: SuperRegIdxSeqs + 2,
692 .LaneMask: LaneBitmask(0x0000000000000003),
693 .AllocationPriority: 0,
694 .GlobalPriority: false,
695 .TSFlags: 0x00, /* TSFlags */
696 .SpillStackID: 0, /* SpillStackID */
697 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
698 .CoveredBySubRegs: true, /* CoveredBySubRegs */
699 .SuperClasses: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 5,
700 .OrderFunc: nullptr
701 };
702
703 extern const TargetRegisterClass DREGS_with_sub_lo_in_GPR8loRegClass = {
704 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_GPR8loRegClassID],
705 .SubClassMask: DREGS_with_sub_lo_in_GPR8loSubClassMask,
706 .SuperRegIndices: SuperRegIdxSeqs + 2,
707 .LaneMask: LaneBitmask(0x0000000000000003),
708 .AllocationPriority: 0,
709 .GlobalPriority: false,
710 .TSFlags: 0x00, /* TSFlags */
711 .SpillStackID: 0, /* SpillStackID */
712 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
713 .CoveredBySubRegs: true, /* CoveredBySubRegs */
714 .SuperClasses: DREGS_with_sub_lo_in_GPR8loSuperclasses, .SuperClassesSize: 2,
715 .OrderFunc: nullptr
716 };
717
718 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass = {
719 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_GPR8loRegClassID],
720 .SubClassMask: DREGS_with_sub_hi_in_GPR8loSubClassMask,
721 .SuperRegIndices: SuperRegIdxSeqs + 2,
722 .LaneMask: LaneBitmask(0x0000000000000003),
723 .AllocationPriority: 0,
724 .GlobalPriority: false,
725 .TSFlags: 0x00, /* TSFlags */
726 .SpillStackID: 0, /* SpillStackID */
727 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
728 .CoveredBySubRegs: true, /* CoveredBySubRegs */
729 .SuperClasses: DREGS_with_sub_hi_in_GPR8loSuperclasses, .SuperClassesSize: 3,
730 .OrderFunc: nullptr
731 };
732
733 extern const TargetRegisterClass DLDREGSRegClass = {
734 .MC: &AVRMCRegisterClasses[DLDREGSRegClassID],
735 .SubClassMask: DLDREGSSubClassMask,
736 .SuperRegIndices: SuperRegIdxSeqs + 2,
737 .LaneMask: LaneBitmask(0x0000000000000003),
738 .AllocationPriority: 0,
739 .GlobalPriority: false,
740 .TSFlags: 0x00, /* TSFlags */
741 .SpillStackID: 0, /* SpillStackID */
742 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
743 .CoveredBySubRegs: true, /* CoveredBySubRegs */
744 .SuperClasses: DLDREGSSuperclasses, .SuperClassesSize: 4,
745 .OrderFunc: nullptr
746 };
747
748 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8loRegClass = {
749 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8loRegClassID],
750 .SubClassMask: DREGS_with_sub_hi_in_LD8loSubClassMask,
751 .SuperRegIndices: SuperRegIdxSeqs + 2,
752 .LaneMask: LaneBitmask(0x0000000000000003),
753 .AllocationPriority: 0,
754 .GlobalPriority: false,
755 .TSFlags: 0x00, /* TSFlags */
756 .SpillStackID: 0, /* SpillStackID */
757 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
758 .CoveredBySubRegs: true, /* CoveredBySubRegs */
759 .SuperClasses: DREGS_with_sub_hi_in_LD8loSuperclasses, .SuperClassesSize: 4,
760 .OrderFunc: nullptr
761 };
762
763 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8loRegClass = {
764 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8loRegClassID],
765 .SubClassMask: DREGS_with_sub_lo_in_LD8loSubClassMask,
766 .SuperRegIndices: SuperRegIdxSeqs + 2,
767 .LaneMask: LaneBitmask(0x0000000000000003),
768 .AllocationPriority: 0,
769 .GlobalPriority: false,
770 .TSFlags: 0x00, /* TSFlags */
771 .SpillStackID: 0, /* SpillStackID */
772 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
773 .CoveredBySubRegs: true, /* CoveredBySubRegs */
774 .SuperClasses: DREGS_with_sub_lo_in_LD8loSuperclasses, .SuperClassesSize: 6,
775 .OrderFunc: nullptr
776 };
777
778 extern const TargetRegisterClass DREGSloRegClass = {
779 .MC: &AVRMCRegisterClasses[DREGSloRegClassID],
780 .SubClassMask: DREGSloSubClassMask,
781 .SuperRegIndices: SuperRegIdxSeqs + 2,
782 .LaneMask: LaneBitmask(0x0000000000000003),
783 .AllocationPriority: 0,
784 .GlobalPriority: false,
785 .TSFlags: 0x00, /* TSFlags */
786 .SpillStackID: 0, /* SpillStackID */
787 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
788 .CoveredBySubRegs: true, /* CoveredBySubRegs */
789 .SuperClasses: DREGSloSuperclasses, .SuperClassesSize: 6,
790 .OrderFunc: nullptr
791 };
792
793 extern const TargetRegisterClass DLDREGS_and_DREGSNOZRegClass = {
794 .MC: &AVRMCRegisterClasses[DLDREGS_and_DREGSNOZRegClassID],
795 .SubClassMask: DLDREGS_and_DREGSNOZSubClassMask,
796 .SuperRegIndices: SuperRegIdxSeqs + 2,
797 .LaneMask: LaneBitmask(0x0000000000000003),
798 .AllocationPriority: 0,
799 .GlobalPriority: false,
800 .TSFlags: 0x00, /* TSFlags */
801 .SpillStackID: 0, /* SpillStackID */
802 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
803 .CoveredBySubRegs: true, /* CoveredBySubRegs */
804 .SuperClasses: DLDREGS_and_DREGSNOZSuperclasses, .SuperClassesSize: 9,
805 .OrderFunc: nullptr
806 };
807
808 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass = {
809 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID],
810 .SubClassMask: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask,
811 .SuperRegIndices: SuperRegIdxSeqs + 2,
812 .LaneMask: LaneBitmask(0x0000000000000003),
813 .AllocationPriority: 0,
814 .GlobalPriority: false,
815 .TSFlags: 0x00, /* TSFlags */
816 .SpillStackID: 0, /* SpillStackID */
817 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
818 .CoveredBySubRegs: true, /* CoveredBySubRegs */
819 .SuperClasses: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 8,
820 .OrderFunc: nullptr
821 };
822
823 extern const TargetRegisterClass DREGSLD8loRegClass = {
824 .MC: &AVRMCRegisterClasses[DREGSLD8loRegClassID],
825 .SubClassMask: DREGSLD8loSubClassMask,
826 .SuperRegIndices: SuperRegIdxSeqs + 2,
827 .LaneMask: LaneBitmask(0x0000000000000003),
828 .AllocationPriority: 0,
829 .GlobalPriority: false,
830 .TSFlags: 0x00, /* TSFlags */
831 .SpillStackID: 0, /* SpillStackID */
832 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
833 .CoveredBySubRegs: true, /* CoveredBySubRegs */
834 .SuperClasses: DREGSLD8loSuperclasses, .SuperClassesSize: 13,
835 .OrderFunc: nullptr
836 };
837
838 extern const TargetRegisterClass IWREGSRegClass = {
839 .MC: &AVRMCRegisterClasses[IWREGSRegClassID],
840 .SubClassMask: IWREGSSubClassMask,
841 .SuperRegIndices: SuperRegIdxSeqs + 2,
842 .LaneMask: LaneBitmask(0x0000000000000003),
843 .AllocationPriority: 0,
844 .GlobalPriority: false,
845 .TSFlags: 0x00, /* TSFlags */
846 .SpillStackID: 0, /* SpillStackID */
847 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
848 .CoveredBySubRegs: true, /* CoveredBySubRegs */
849 .SuperClasses: IWREGSSuperclasses, .SuperClassesSize: 5,
850 .OrderFunc: nullptr
851 };
852
853 extern const TargetRegisterClass DREGSNOZ_and_IWREGSRegClass = {
854 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_IWREGSRegClassID],
855 .SubClassMask: DREGSNOZ_and_IWREGSSubClassMask,
856 .SuperRegIndices: SuperRegIdxSeqs + 2,
857 .LaneMask: LaneBitmask(0x0000000000000003),
858 .AllocationPriority: 0,
859 .GlobalPriority: false,
860 .TSFlags: 0x00, /* TSFlags */
861 .SpillStackID: 0, /* SpillStackID */
862 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
863 .CoveredBySubRegs: true, /* CoveredBySubRegs */
864 .SuperClasses: DREGSNOZ_and_IWREGSSuperclasses, .SuperClassesSize: 11,
865 .OrderFunc: nullptr
866 };
867
868 extern const TargetRegisterClass PTRREGSRegClass = {
869 .MC: &AVRMCRegisterClasses[PTRREGSRegClassID],
870 .SubClassMask: PTRREGSSubClassMask,
871 .SuperRegIndices: SuperRegIdxSeqs + 2,
872 .LaneMask: LaneBitmask(0x0000000000000003),
873 .AllocationPriority: 0,
874 .GlobalPriority: false,
875 .TSFlags: 0x00, /* TSFlags */
876 .SpillStackID: 0, /* SpillStackID */
877 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
878 .CoveredBySubRegs: true, /* CoveredBySubRegs */
879 .SuperClasses: PTRREGSSuperclasses, .SuperClassesSize: 6,
880 .OrderFunc: nullptr
881 };
882
883 extern const TargetRegisterClass DREGSNOZ_and_PTRREGSRegClass = {
884 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_PTRREGSRegClassID],
885 .SubClassMask: DREGSNOZ_and_PTRREGSSubClassMask,
886 .SuperRegIndices: SuperRegIdxSeqs + 2,
887 .LaneMask: LaneBitmask(0x0000000000000003),
888 .AllocationPriority: 0,
889 .GlobalPriority: false,
890 .TSFlags: 0x00, /* TSFlags */
891 .SpillStackID: 0, /* SpillStackID */
892 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
893 .CoveredBySubRegs: true, /* CoveredBySubRegs */
894 .SuperClasses: DREGSNOZ_and_PTRREGSSuperclasses, .SuperClassesSize: 13,
895 .OrderFunc: nullptr
896 };
897
898 extern const TargetRegisterClass PTRDISPREGSRegClass = {
899 .MC: &AVRMCRegisterClasses[PTRDISPREGSRegClassID],
900 .SubClassMask: PTRDISPREGSSubClassMask,
901 .SuperRegIndices: SuperRegIdxSeqs + 2,
902 .LaneMask: LaneBitmask(0x0000000000000003),
903 .AllocationPriority: 0,
904 .GlobalPriority: false,
905 .TSFlags: 0x00, /* TSFlags */
906 .SpillStackID: 0, /* SpillStackID */
907 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
908 .CoveredBySubRegs: true, /* CoveredBySubRegs */
909 .SuperClasses: PTRDISPREGSSuperclasses, .SuperClassesSize: 7,
910 .OrderFunc: nullptr
911 };
912
913 extern const TargetRegisterClass DREGSNOZ_and_PTRDISPREGSRegClass = {
914 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_PTRDISPREGSRegClassID],
915 .SubClassMask: DREGSNOZ_and_PTRDISPREGSSubClassMask,
916 .SuperRegIndices: SuperRegIdxSeqs + 2,
917 .LaneMask: LaneBitmask(0x0000000000000003),
918 .AllocationPriority: 0,
919 .GlobalPriority: false,
920 .TSFlags: 0x00, /* TSFlags */
921 .SpillStackID: 0, /* SpillStackID */
922 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
923 .CoveredBySubRegs: true, /* CoveredBySubRegs */
924 .SuperClasses: DREGSNOZ_and_PTRDISPREGSSuperclasses, .SuperClassesSize: 15,
925 .OrderFunc: nullptr
926 };
927
928 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass = {
929 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID],
930 .SubClassMask: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask,
931 .SuperRegIndices: SuperRegIdxSeqs + 2,
932 .LaneMask: LaneBitmask(0x0000000000000003),
933 .AllocationPriority: 0,
934 .GlobalPriority: false,
935 .TSFlags: 0x00, /* TSFlags */
936 .SpillStackID: 0, /* SpillStackID */
937 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
938 .CoveredBySubRegs: true, /* CoveredBySubRegs */
939 .SuperClasses: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses, .SuperClassesSize: 6,
940 .OrderFunc: nullptr
941 };
942
943 extern const TargetRegisterClass GPRSPRegClass = {
944 .MC: &AVRMCRegisterClasses[GPRSPRegClassID],
945 .SubClassMask: GPRSPSubClassMask,
946 .SuperRegIndices: SuperRegIdxSeqs + 2,
947 .LaneMask: LaneBitmask(0x0000000000000003),
948 .AllocationPriority: 0,
949 .GlobalPriority: false,
950 .TSFlags: 0x00, /* TSFlags */
951 .SpillStackID: 0, /* SpillStackID */
952 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
953 .CoveredBySubRegs: true, /* CoveredBySubRegs */
954 .SuperClasses: nullptr, .SuperClassesSize: 0,
955 .OrderFunc: nullptr
956 };
957
958 extern const TargetRegisterClass ZREGRegClass = {
959 .MC: &AVRMCRegisterClasses[ZREGRegClassID],
960 .SubClassMask: ZREGSubClassMask,
961 .SuperRegIndices: SuperRegIdxSeqs + 2,
962 .LaneMask: LaneBitmask(0x0000000000000003),
963 .AllocationPriority: 0,
964 .GlobalPriority: false,
965 .TSFlags: 0x00, /* TSFlags */
966 .SpillStackID: 0, /* SpillStackID */
967 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
968 .CoveredBySubRegs: true, /* CoveredBySubRegs */
969 .SuperClasses: ZREGSuperclasses, .SuperClassesSize: 8,
970 .OrderFunc: nullptr
971 };
972
973
974} // namespace AVR
975static const TargetRegisterClass *const AVRRegisterClasses[] = {
976 &AVR::GPR8RegClass,
977 &AVR::GPR8NOZRegClass,
978 &AVR::GPR8loRegClass,
979 &AVR::LD8RegClass,
980 &AVR::GPR8NOZ_and_LD8RegClass,
981 &AVR::LD8loRegClass,
982 &AVR::CCRRegClass,
983 &AVR::DREGSRegClass,
984 &AVR::DREGSNOZRegClass,
985 &AVR::DREGSMOVWRegClass,
986 &AVR::DREGSMOVW_and_DREGSNOZRegClass,
987 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
988 &AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClass,
989 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
990 &AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClass,
991 &AVR::DREGS_with_sub_lo_in_GPR8loRegClass,
992 &AVR::DREGS_with_sub_hi_in_GPR8loRegClass,
993 &AVR::DLDREGSRegClass,
994 &AVR::DREGS_with_sub_hi_in_LD8loRegClass,
995 &AVR::DREGS_with_sub_lo_in_LD8loRegClass,
996 &AVR::DREGSloRegClass,
997 &AVR::DLDREGS_and_DREGSNOZRegClass,
998 &AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass,
999 &AVR::DREGSLD8loRegClass,
1000 &AVR::IWREGSRegClass,
1001 &AVR::DREGSNOZ_and_IWREGSRegClass,
1002 &AVR::PTRREGSRegClass,
1003 &AVR::DREGSNOZ_and_PTRREGSRegClass,
1004 &AVR::PTRDISPREGSRegClass,
1005 &AVR::DREGSNOZ_and_PTRDISPREGSRegClass,
1006 &AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass,
1007 &AVR::GPRSPRegClass,
1008 &AVR::ZREGRegClass,
1009 };
1010
1011static const uint8_t AVRCostPerUseTable[] = {
10120, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1013
1014
1015static const bool AVRInAllocatableClassTable[] = {
1016false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1017
1018
1019static const TargetRegisterInfoDesc AVRRegInfoDesc = { // Extra Descriptors
1020.CostPerUse: AVRCostPerUseTable, .NumCosts: 1, .InAllocatableClass: AVRInAllocatableClassTable};
1021
1022unsigned AVRGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1023 static const uint8_t Rows[1][2] = {
1024 { 0, 0, },
1025 };
1026
1027 --IdxA; assert(IdxA < 2); (void) IdxA;
1028 --IdxB; assert(IdxB < 2);
1029 return Rows[0][IdxB];
1030}
1031
1032unsigned AVRGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1033 static const uint8_t Table[2][2] = {
1034 { 0, 0, },
1035 { 0, 0, },
1036 };
1037
1038 --IdxA; assert(IdxA < 2);
1039 --IdxB; assert(IdxB < 2);
1040 return Table[IdxA][IdxB];
1041 }
1042
1043 struct MaskRolOp {
1044 LaneBitmask Mask;
1045 uint8_t RotateLeft;
1046 };
1047 static const MaskRolOp LaneMaskComposeSequences[] = {
1048 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
1049 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 2
1050 };
1051 static const uint8_t CompositeSequences[] = {
1052 0, // to sub_hi
1053 2 // to sub_lo
1054 };
1055
1056LaneBitmask AVRGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1057 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1058 LaneBitmask Result;
1059 for (const MaskRolOp *Ops =
1060 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1061 Ops->Mask.any(); ++Ops) {
1062 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1063 if (unsigned S = Ops->RotateLeft)
1064 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1065 else
1066 Result |= LaneBitmask(M);
1067 }
1068 return Result;
1069}
1070
1071LaneBitmask AVRGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1072 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
1073 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1074 LaneBitmask Result;
1075 for (const MaskRolOp *Ops =
1076 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1077 Ops->Mask.any(); ++Ops) {
1078 LaneBitmask::Type M = LaneMask.getAsInteger();
1079 if (unsigned S = Ops->RotateLeft)
1080 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1081 else
1082 Result |= LaneBitmask(M);
1083 }
1084 return Result;
1085}
1086
1087const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1088 static constexpr uint8_t Table[33][2] = {
1089 { // GPR8
1090 0, // sub_hi
1091 0, // sub_lo
1092 },
1093 { // GPR8NOZ
1094 0, // sub_hi
1095 0, // sub_lo
1096 },
1097 { // GPR8lo
1098 0, // sub_hi
1099 0, // sub_lo
1100 },
1101 { // LD8
1102 0, // sub_hi
1103 0, // sub_lo
1104 },
1105 { // GPR8NOZ_and_LD8
1106 0, // sub_hi
1107 0, // sub_lo
1108 },
1109 { // LD8lo
1110 0, // sub_hi
1111 0, // sub_lo
1112 },
1113 { // CCR
1114 0, // sub_hi
1115 0, // sub_lo
1116 },
1117 { // DREGS
1118 8, // sub_hi -> DREGS
1119 8, // sub_lo -> DREGS
1120 },
1121 { // DREGSNOZ
1122 9, // sub_hi -> DREGSNOZ
1123 9, // sub_lo -> DREGSNOZ
1124 },
1125 { // DREGSMOVW
1126 10, // sub_hi -> DREGSMOVW
1127 10, // sub_lo -> DREGSMOVW
1128 },
1129 { // DREGSMOVW_and_DREGSNOZ
1130 11, // sub_hi -> DREGSMOVW_and_DREGSNOZ
1131 11, // sub_lo -> DREGSMOVW_and_DREGSNOZ
1132 },
1133 { // DREGS_with_sub_hi_in_LD8
1134 12, // sub_hi -> DREGS_with_sub_hi_in_LD8
1135 12, // sub_lo -> DREGS_with_sub_hi_in_LD8
1136 },
1137 { // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1138 13, // sub_hi -> DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1139 13, // sub_lo -> DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1140 },
1141 { // DREGS_with_sub_lo_in_LD8
1142 14, // sub_hi -> DREGS_with_sub_lo_in_LD8
1143 14, // sub_lo -> DREGS_with_sub_lo_in_LD8
1144 },
1145 { // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1146 15, // sub_hi -> DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1147 15, // sub_lo -> DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1148 },
1149 { // DREGS_with_sub_lo_in_GPR8lo
1150 16, // sub_hi -> DREGS_with_sub_lo_in_GPR8lo
1151 16, // sub_lo -> DREGS_with_sub_lo_in_GPR8lo
1152 },
1153 { // DREGS_with_sub_hi_in_GPR8lo
1154 17, // sub_hi -> DREGS_with_sub_hi_in_GPR8lo
1155 17, // sub_lo -> DREGS_with_sub_hi_in_GPR8lo
1156 },
1157 { // DLDREGS
1158 18, // sub_hi -> DLDREGS
1159 18, // sub_lo -> DLDREGS
1160 },
1161 { // DREGS_with_sub_hi_in_LD8lo
1162 19, // sub_hi -> DREGS_with_sub_hi_in_LD8lo
1163 19, // sub_lo -> DREGS_with_sub_hi_in_LD8lo
1164 },
1165 { // DREGS_with_sub_lo_in_LD8lo
1166 20, // sub_hi -> DREGS_with_sub_lo_in_LD8lo
1167 20, // sub_lo -> DREGS_with_sub_lo_in_LD8lo
1168 },
1169 { // DREGSlo
1170 21, // sub_hi -> DREGSlo
1171 21, // sub_lo -> DREGSlo
1172 },
1173 { // DLDREGS_and_DREGSNOZ
1174 22, // sub_hi -> DLDREGS_and_DREGSNOZ
1175 22, // sub_lo -> DLDREGS_and_DREGSNOZ
1176 },
1177 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1178 23, // sub_hi -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1179 23, // sub_lo -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1180 },
1181 { // DREGSLD8lo
1182 24, // sub_hi -> DREGSLD8lo
1183 24, // sub_lo -> DREGSLD8lo
1184 },
1185 { // IWREGS
1186 25, // sub_hi -> IWREGS
1187 25, // sub_lo -> IWREGS
1188 },
1189 { // DREGSNOZ_and_IWREGS
1190 26, // sub_hi -> DREGSNOZ_and_IWREGS
1191 26, // sub_lo -> DREGSNOZ_and_IWREGS
1192 },
1193 { // PTRREGS
1194 27, // sub_hi -> PTRREGS
1195 27, // sub_lo -> PTRREGS
1196 },
1197 { // DREGSNOZ_and_PTRREGS
1198 28, // sub_hi -> DREGSNOZ_and_PTRREGS
1199 28, // sub_lo -> DREGSNOZ_and_PTRREGS
1200 },
1201 { // PTRDISPREGS
1202 29, // sub_hi -> PTRDISPREGS
1203 29, // sub_lo -> PTRDISPREGS
1204 },
1205 { // DREGSNOZ_and_PTRDISPREGS
1206 30, // sub_hi -> DREGSNOZ_and_PTRDISPREGS
1207 30, // sub_lo -> DREGSNOZ_and_PTRDISPREGS
1208 },
1209 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1210 31, // sub_hi -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1211 31, // sub_lo -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1212 },
1213 { // GPRSP
1214 32, // sub_hi -> GPRSP
1215 32, // sub_lo -> GPRSP
1216 },
1217 { // ZREG
1218 33, // sub_hi -> ZREG
1219 33, // sub_lo -> ZREG
1220 },
1221
1222 };
1223 assert(RC && "Missing regclass");
1224 if (!Idx) return RC;
1225 --Idx;
1226 assert(Idx < 2 && "Bad subreg");
1227 unsigned TV = Table[RC->getID()][Idx];
1228 return TV ? getRegClass(i: TV - 1) : nullptr;
1229}const TargetRegisterClass *AVRGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1230 static constexpr uint8_t Table[33][2] = {
1231 { // GPR8
1232 0, // GPR8:sub_hi
1233 0, // GPR8:sub_lo
1234 },
1235 { // GPR8NOZ
1236 0, // GPR8NOZ:sub_hi
1237 0, // GPR8NOZ:sub_lo
1238 },
1239 { // GPR8lo
1240 0, // GPR8lo:sub_hi
1241 0, // GPR8lo:sub_lo
1242 },
1243 { // LD8
1244 0, // LD8:sub_hi
1245 0, // LD8:sub_lo
1246 },
1247 { // GPR8NOZ_and_LD8
1248 0, // GPR8NOZ_and_LD8:sub_hi
1249 0, // GPR8NOZ_and_LD8:sub_lo
1250 },
1251 { // LD8lo
1252 0, // LD8lo:sub_hi
1253 0, // LD8lo:sub_lo
1254 },
1255 { // CCR
1256 0, // CCR:sub_hi
1257 0, // CCR:sub_lo
1258 },
1259 { // DREGS
1260 1, // DREGS:sub_hi -> GPR8
1261 1, // DREGS:sub_lo -> GPR8
1262 },
1263 { // DREGSNOZ
1264 2, // DREGSNOZ:sub_hi -> GPR8NOZ
1265 2, // DREGSNOZ:sub_lo -> GPR8NOZ
1266 },
1267 { // DREGSMOVW
1268 1, // DREGSMOVW:sub_hi -> GPR8
1269 1, // DREGSMOVW:sub_lo -> GPR8
1270 },
1271 { // DREGSMOVW_and_DREGSNOZ
1272 2, // DREGSMOVW_and_DREGSNOZ:sub_hi -> GPR8NOZ
1273 2, // DREGSMOVW_and_DREGSNOZ:sub_lo -> GPR8NOZ
1274 },
1275 { // DREGS_with_sub_hi_in_LD8
1276 4, // DREGS_with_sub_hi_in_LD8:sub_hi -> LD8
1277 1, // DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8
1278 },
1279 { // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1280 5, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8:sub_hi -> GPR8NOZ_and_LD8
1281 2, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8NOZ
1282 },
1283 { // DREGS_with_sub_lo_in_LD8
1284 4, // DREGS_with_sub_lo_in_LD8:sub_hi -> LD8
1285 4, // DREGS_with_sub_lo_in_LD8:sub_lo -> LD8
1286 },
1287 { // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1288 5, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8:sub_hi -> GPR8NOZ_and_LD8
1289 5, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8:sub_lo -> GPR8NOZ_and_LD8
1290 },
1291 { // DREGS_with_sub_lo_in_GPR8lo
1292 2, // DREGS_with_sub_lo_in_GPR8lo:sub_hi -> GPR8NOZ
1293 3, // DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1294 },
1295 { // DREGS_with_sub_hi_in_GPR8lo
1296 3, // DREGS_with_sub_hi_in_GPR8lo:sub_hi -> GPR8lo
1297 3, // DREGS_with_sub_hi_in_GPR8lo:sub_lo -> GPR8lo
1298 },
1299 { // DLDREGS
1300 4, // DLDREGS:sub_hi -> LD8
1301 4, // DLDREGS:sub_lo -> LD8
1302 },
1303 { // DREGS_with_sub_hi_in_LD8lo
1304 6, // DREGS_with_sub_hi_in_LD8lo:sub_hi -> LD8lo
1305 2, // DREGS_with_sub_hi_in_LD8lo:sub_lo -> GPR8NOZ
1306 },
1307 { // DREGS_with_sub_lo_in_LD8lo
1308 5, // DREGS_with_sub_lo_in_LD8lo:sub_hi -> GPR8NOZ_and_LD8
1309 6, // DREGS_with_sub_lo_in_LD8lo:sub_lo -> LD8lo
1310 },
1311 { // DREGSlo
1312 3, // DREGSlo:sub_hi -> GPR8lo
1313 3, // DREGSlo:sub_lo -> GPR8lo
1314 },
1315 { // DLDREGS_and_DREGSNOZ
1316 5, // DLDREGS_and_DREGSNOZ:sub_hi -> GPR8NOZ_and_LD8
1317 5, // DLDREGS_and_DREGSNOZ:sub_lo -> GPR8NOZ_and_LD8
1318 },
1319 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1320 6, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_hi -> LD8lo
1321 6, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_lo -> LD8lo
1322 },
1323 { // DREGSLD8lo
1324 6, // DREGSLD8lo:sub_hi -> LD8lo
1325 6, // DREGSLD8lo:sub_lo -> LD8lo
1326 },
1327 { // IWREGS
1328 4, // IWREGS:sub_hi -> LD8
1329 4, // IWREGS:sub_lo -> LD8
1330 },
1331 { // DREGSNOZ_and_IWREGS
1332 5, // DREGSNOZ_and_IWREGS:sub_hi -> GPR8NOZ_and_LD8
1333 5, // DREGSNOZ_and_IWREGS:sub_lo -> GPR8NOZ_and_LD8
1334 },
1335 { // PTRREGS
1336 4, // PTRREGS:sub_hi -> LD8
1337 4, // PTRREGS:sub_lo -> LD8
1338 },
1339 { // DREGSNOZ_and_PTRREGS
1340 5, // DREGSNOZ_and_PTRREGS:sub_hi -> GPR8NOZ_and_LD8
1341 5, // DREGSNOZ_and_PTRREGS:sub_lo -> GPR8NOZ_and_LD8
1342 },
1343 { // PTRDISPREGS
1344 4, // PTRDISPREGS:sub_hi -> LD8
1345 4, // PTRDISPREGS:sub_lo -> LD8
1346 },
1347 { // DREGSNOZ_and_PTRDISPREGS
1348 5, // DREGSNOZ_and_PTRDISPREGS:sub_hi -> GPR8NOZ_and_LD8
1349 5, // DREGSNOZ_and_PTRDISPREGS:sub_lo -> GPR8NOZ_and_LD8
1350 },
1351 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1352 6, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_hi -> LD8lo
1353 3, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1354 },
1355 { // GPRSP
1356 0, // GPRSP:sub_hi
1357 0, // GPRSP:sub_lo
1358 },
1359 { // ZREG
1360 4, // ZREG:sub_hi -> LD8
1361 4, // ZREG:sub_lo -> LD8
1362 },
1363
1364 };
1365 assert(RC && "Missing regclass");
1366 if (!Idx) return RC;
1367 --Idx;
1368 assert(Idx < 2 && "Bad subreg");
1369 unsigned TV = Table[RC->getID()][Idx];
1370 return TV ? getRegClass(i: TV - 1) : nullptr;
1371}/// Get the weight in units of pressure for this register class.
1372const RegClassWeight &AVRGenRegisterInfo::
1373getRegClassWeight(const TargetRegisterClass *RC) const {
1374 static const RegClassWeight RCWeightTable[] = {
1375 {.RegWeight: 1, .WeightLimit: 32}, // GPR8
1376 {.RegWeight: 1, .WeightLimit: 30}, // GPR8NOZ
1377 {.RegWeight: 1, .WeightLimit: 16}, // GPR8lo
1378 {.RegWeight: 1, .WeightLimit: 16}, // LD8
1379 {.RegWeight: 1, .WeightLimit: 14}, // GPR8NOZ_and_LD8
1380 {.RegWeight: 1, .WeightLimit: 8}, // LD8lo
1381 {.RegWeight: 1, .WeightLimit: 1}, // CCR
1382 {.RegWeight: 2, .WeightLimit: 32}, // DREGS
1383 {.RegWeight: 2, .WeightLimit: 30}, // DREGSNOZ
1384 {.RegWeight: 2, .WeightLimit: 32}, // DREGSMOVW
1385 {.RegWeight: 2, .WeightLimit: 30}, // DREGSMOVW_and_DREGSNOZ
1386 {.RegWeight: 2, .WeightLimit: 17}, // DREGS_with_sub_hi_in_LD8
1387 {.RegWeight: 2, .WeightLimit: 15}, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1388 {.RegWeight: 2, .WeightLimit: 16}, // DREGS_with_sub_lo_in_LD8
1389 {.RegWeight: 2, .WeightLimit: 14}, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1390 {.RegWeight: 2, .WeightLimit: 17}, // DREGS_with_sub_lo_in_GPR8lo
1391 {.RegWeight: 2, .WeightLimit: 16}, // DREGS_with_sub_hi_in_GPR8lo
1392 {.RegWeight: 2, .WeightLimit: 16}, // DLDREGS
1393 {.RegWeight: 2, .WeightLimit: 9}, // DREGS_with_sub_hi_in_LD8lo
1394 {.RegWeight: 2, .WeightLimit: 9}, // DREGS_with_sub_lo_in_LD8lo
1395 {.RegWeight: 2, .WeightLimit: 16}, // DREGSlo
1396 {.RegWeight: 2, .WeightLimit: 14}, // DLDREGS_and_DREGSNOZ
1397 {.RegWeight: 2, .WeightLimit: 8}, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1398 {.RegWeight: 2, .WeightLimit: 8}, // DREGSLD8lo
1399 {.RegWeight: 2, .WeightLimit: 8}, // IWREGS
1400 {.RegWeight: 2, .WeightLimit: 6}, // DREGSNOZ_and_IWREGS
1401 {.RegWeight: 2, .WeightLimit: 6}, // PTRREGS
1402 {.RegWeight: 2, .WeightLimit: 4}, // DREGSNOZ_and_PTRREGS
1403 {.RegWeight: 2, .WeightLimit: 4}, // PTRDISPREGS
1404 {.RegWeight: 2, .WeightLimit: 2}, // DREGSNOZ_and_PTRDISPREGS
1405 {.RegWeight: 2, .WeightLimit: 2}, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1406 {.RegWeight: 2, .WeightLimit: 2}, // GPRSP
1407 {.RegWeight: 2, .WeightLimit: 2}, // ZREG
1408 };
1409 return RCWeightTable[RC->getID()];
1410}
1411
1412/// Get the weight in units of pressure for this register unit.
1413unsigned AVRGenRegisterInfo::
1414getRegUnitWeight(MCRegUnit RegUnit) const {
1415 assert(static_cast<unsigned>(RegUnit) < 35 && "invalid register unit");
1416 // All register units have unit weight.
1417 return 1;
1418}
1419
1420
1421// Get the number of dimensions of register pressure.
1422unsigned AVRGenRegisterInfo::getNumRegPressureSets() const {
1423 return 9;
1424}
1425
1426// Get the name of this register unit pressure set.
1427const char *AVRGenRegisterInfo::
1428getRegPressureSetName(unsigned Idx) const {
1429 static const char *PressureNameTable[] = {
1430 "CCR",
1431 "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo",
1432 "GPRSP",
1433 "IWREGS",
1434 "LD8lo",
1435 "LD8",
1436 "GPR8lo",
1437 "GPR8lo_with_LD8lo",
1438 "GPR8",
1439 };
1440 return PressureNameTable[Idx];
1441}
1442
1443// Get the register unit pressure limit for this dimension.
1444// This limit must be adjusted dynamically for reserved registers.
1445unsigned AVRGenRegisterInfo::
1446getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1447 static const uint8_t PressureLimitTable[] = {
1448 1, // 0: CCR
1449 2, // 1: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1450 2, // 2: GPRSP
1451 8, // 3: IWREGS
1452 10, // 4: LD8lo
1453 17, // 5: LD8
1454 17, // 6: GPR8lo
1455 25, // 7: GPR8lo_with_LD8lo
1456 32, // 8: GPR8
1457 };
1458 return PressureLimitTable[Idx];
1459}
1460
1461/// Table of pressure sets per register class or unit.
1462static const int RCSetsTable[] = {
1463 /* 0 */ 0, -1,
1464 /* 2 */ 2, -1,
1465 /* 4 */ 3, 5, 8, -1,
1466 /* 8 */ 3, 4, 5, 7, 8, -1,
1467 /* 14 */ 1, 4, 5, 6, 7, 8, -1,
1468};
1469
1470/// Get the dimensions of register pressure impacted by this register class.
1471/// Returns a -1 terminated array of pressure set IDs
1472const int *AVRGenRegisterInfo::
1473getRegClassPressureSets(const TargetRegisterClass *RC) const {
1474 static const uint8_t RCSetStartTable[] = {
1475 6,6,17,5,5,9,0,6,6,6,6,5,5,5,5,17,17,5,9,9,17,5,9,9,4,4,4,4,4,4,14,2,4,};
1476 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1477}
1478
1479/// Get the dimensions of register pressure impacted by this register unit.
1480/// Returns a -1 terminated array of pressure set IDs
1481const int *AVRGenRegisterInfo::
1482getRegUnitPressureSets(MCRegUnit RegUnit) const {
1483 assert(static_cast<unsigned>(RegUnit) < 35 && "invalid register unit");
1484 static const uint8_t RUSetStartTable[] = {
1485 2,2,0,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,14,14,9,9,9,9,9,9,9,8,4,4,4,4,4,4,4,};
1486 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1487}
1488
1489
1490// Register to minimal register class mapping
1491
1492const TargetRegisterClass *AVRGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
1493 static const uint16_t InvalidRegClassID = UINT16_MAX;
1494
1495 static const uint16_t Mapping[62] = {
1496 InvalidRegClassID, // NoRegister
1497 AVR::GPRSPRegClassID, // SP
1498 InvalidRegClassID, // SPH
1499 InvalidRegClassID, // SPL
1500 AVR::CCRRegClassID, // SREG
1501 AVR::GPR8loRegClassID, // R0
1502 AVR::GPR8loRegClassID, // R1
1503 AVR::GPR8loRegClassID, // R2
1504 AVR::GPR8loRegClassID, // R3
1505 AVR::GPR8loRegClassID, // R4
1506 AVR::GPR8loRegClassID, // R5
1507 AVR::GPR8loRegClassID, // R6
1508 AVR::GPR8loRegClassID, // R7
1509 AVR::GPR8loRegClassID, // R8
1510 AVR::GPR8loRegClassID, // R9
1511 AVR::GPR8loRegClassID, // R10
1512 AVR::GPR8loRegClassID, // R11
1513 AVR::GPR8loRegClassID, // R12
1514 AVR::GPR8loRegClassID, // R13
1515 AVR::GPR8loRegClassID, // R14
1516 AVR::GPR8loRegClassID, // R15
1517 AVR::LD8loRegClassID, // R16
1518 AVR::LD8loRegClassID, // R17
1519 AVR::LD8loRegClassID, // R18
1520 AVR::LD8loRegClassID, // R19
1521 AVR::LD8loRegClassID, // R20
1522 AVR::LD8loRegClassID, // R21
1523 AVR::LD8loRegClassID, // R22
1524 AVR::LD8loRegClassID, // R23
1525 AVR::GPR8NOZ_and_LD8RegClassID, // R24
1526 AVR::GPR8NOZ_and_LD8RegClassID, // R25
1527 AVR::GPR8NOZ_and_LD8RegClassID, // R26
1528 AVR::GPR8NOZ_and_LD8RegClassID, // R27
1529 AVR::GPR8NOZ_and_LD8RegClassID, // R28
1530 AVR::GPR8NOZ_and_LD8RegClassID, // R29
1531 AVR::LD8RegClassID, // R30
1532 AVR::LD8RegClassID, // R31
1533 AVR::DREGSloRegClassID, // R1R0
1534 AVR::DREGSloRegClassID, // R3R2
1535 AVR::DREGSloRegClassID, // R5R4
1536 AVR::DREGSloRegClassID, // R7R6
1537 AVR::DREGSloRegClassID, // R9R8
1538 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, // R10R9
1539 AVR::DREGSloRegClassID, // R11R10
1540 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, // R12R11
1541 AVR::DREGSloRegClassID, // R13R12
1542 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, // R14R13
1543 AVR::DREGSloRegClassID, // R15R14
1544 AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID, // R16R15
1545 AVR::DREGSLD8loRegClassID, // R17R16
1546 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, // R18R17
1547 AVR::DREGSLD8loRegClassID, // R19R18
1548 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, // R20R19
1549 AVR::DREGSLD8loRegClassID, // R21R20
1550 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, // R22R21
1551 AVR::DREGSLD8loRegClassID, // R23R22
1552 AVR::DREGS_with_sub_lo_in_LD8loRegClassID, // R24R23
1553 AVR::DREGSNOZ_and_IWREGSRegClassID, // R25R24
1554 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, // R26R25
1555 AVR::DREGSNOZ_and_PTRREGSRegClassID, // R27R26
1556 AVR::DREGSNOZ_and_PTRDISPREGSRegClassID, // R29R28
1557 AVR::ZREGRegClassID, // R31R30
1558 };
1559
1560 assert(Reg < ArrayRef(Mapping).size());
1561 unsigned RCID = Mapping[Reg.id()];
1562 if (RCID == InvalidRegClassID)
1563 return nullptr;
1564 return AVRRegisterClasses[RCID];
1565}
1566extern const MCRegisterDesc AVRRegDesc[];
1567extern const int16_t AVRRegDiffLists[];
1568extern const LaneBitmask AVRLaneMaskLists[];
1569extern const char AVRRegStrings[];
1570extern const char AVRRegClassStrings[];
1571extern const MCPhysReg AVRRegUnitRoots[][2];
1572extern const uint16_t AVRSubRegIdxLists[];
1573extern const uint16_t AVRRegEncodingTable[];
1574// AVR Dwarf<->LLVM register mappings.
1575extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[];
1576extern const unsigned AVRDwarfFlavour0Dwarf2LSize;
1577
1578extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[];
1579extern const unsigned AVREHFlavour0Dwarf2LSize;
1580
1581extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[];
1582extern const unsigned AVRDwarfFlavour0L2DwarfSize;
1583
1584extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[];
1585extern const unsigned AVREHFlavour0L2DwarfSize;
1586
1587
1588AVRGenRegisterInfo::
1589AVRGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1590 unsigned PC, unsigned HwMode)
1591 : TargetRegisterInfo(&AVRRegInfoDesc, AVRRegisterClasses,
1592 AVRSubRegIndexStrings, AVRSubRegIndexNameOffsets,
1593 AVRSubRegIdxRangeTable, AVRSubRegIndexLaneMaskTable,
1594
1595 LaneBitmask(0xFFFFFFFFFFFFFFFF), AVRRegClassInfos, AVRVTLists, HwMode) {
1596 InitMCRegisterInfo(D: AVRRegDesc, NR: 62, RA, PC,
1597 C: AVRMCRegisterClasses, NC: 33, RURoots: AVRRegUnitRoots, NRU: 35, DL: AVRRegDiffLists,
1598 RUMS: AVRLaneMaskLists, Strings: AVRRegStrings, ClassStrings: AVRRegClassStrings, SubIndices: AVRSubRegIdxLists, NumIndices: 3,
1599 RET: AVRRegEncodingTable, RUI: nullptr);
1600
1601 switch (DwarfFlavour) {
1602 default:
1603 llvm_unreachable("Unknown DWARF flavour");
1604 case 0:
1605 mapDwarfRegsToLLVMRegs(Map: AVRDwarfFlavour0Dwarf2L, Size: AVRDwarfFlavour0Dwarf2LSize, isEH: false);
1606 break;
1607 }
1608 switch (EHFlavour) {
1609 default:
1610 llvm_unreachable("Unknown DWARF flavour");
1611 case 0:
1612 mapDwarfRegsToLLVMRegs(Map: AVREHFlavour0Dwarf2L, Size: AVREHFlavour0Dwarf2LSize, isEH: true);
1613 break;
1614 }
1615 switch (DwarfFlavour) {
1616 default:
1617 llvm_unreachable("Unknown DWARF flavour");
1618 case 0:
1619 mapLLVMRegsToDwarfRegs(Map: AVRDwarfFlavour0L2Dwarf, Size: AVRDwarfFlavour0L2DwarfSize, isEH: false);
1620 break;
1621 }
1622 switch (EHFlavour) {
1623 default:
1624 llvm_unreachable("Unknown DWARF flavour");
1625 case 0:
1626 mapLLVMRegsToDwarfRegs(Map: AVREHFlavour0L2Dwarf, Size: AVREHFlavour0L2DwarfSize, isEH: true);
1627 break;
1628 }
1629}
1630
1631static const MCPhysReg CSR_Interrupts_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
1632static const uint32_t CSR_Interrupts_RegMask[] = { 0xffffff80, 0x3fffffdf, };
1633static const MCPhysReg CSR_InterruptsTiny_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, 0 };
1634static const uint32_t CSR_InterruptsTiny_RegMask[] = { 0xff800000, 0x3ff8001f, };
1635static const MCPhysReg CSR_Normal_SaveList[] = { AVR::R29, AVR::R28, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
1636static const uint32_t CSR_Normal_RegMask[] = { 0x007fff80, 0x1003ffc6, };
1637static const MCPhysReg CSR_NormalTiny_SaveList[] = { AVR::R29, AVR::R28, AVR::R19, AVR::R18, 0 };
1638static const uint32_t CSR_NormalTiny_RegMask[] = { 0x01800000, 0x10080006, };
1639
1640
1641ArrayRef<const uint32_t *> AVRGenRegisterInfo::getRegMasks() const {
1642 static const uint32_t *const Masks[] = {
1643 CSR_Interrupts_RegMask,
1644 CSR_InterruptsTiny_RegMask,
1645 CSR_Normal_RegMask,
1646 CSR_NormalTiny_RegMask,
1647 };
1648 return ArrayRef(Masks);
1649}
1650
1651bool AVRGenRegisterInfo::
1652isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1653 return
1654 false;
1655}
1656
1657bool AVRGenRegisterInfo::
1658isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1659 return
1660 false;
1661}
1662
1663bool AVRGenRegisterInfo::
1664isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1665 return
1666 false;
1667}
1668
1669bool AVRGenRegisterInfo::
1670isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1671 return
1672 false;
1673}
1674
1675bool AVRGenRegisterInfo::
1676isConstantPhysReg(MCRegister PhysReg) const {
1677 return
1678 false;
1679}
1680
1681ArrayRef<const char *> AVRGenRegisterInfo::getRegMaskNames() const {
1682 static const char *Names[] = {
1683 "CSR_Interrupts",
1684 "CSR_InterruptsTiny",
1685 "CSR_Normal",
1686 "CSR_NormalTiny",
1687 };
1688 return ArrayRef(Names);
1689}
1690
1691const AVRFrameLowering *
1692AVRGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1693 return static_cast<const AVRFrameLowering *>(
1694 MF.getSubtarget().getFrameLowering());
1695}
1696
1697
1698} // namespace llvm
1699