1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<33, 340, 220, 90, 3, 153> AVRMCRegisterClassStorage;
12
13static const MVT::SimpleValueType AVRVTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char AVRSubRegIndexStrings[] = {
23 /* 0 */ "sub_hi\000"
24 /* 7 */ "sub_lo\000"
25};
26#ifdef __GNUC__
27#pragma GCC diagnostic pop
28#endif
29
30
31static constexpr uint32_t AVRSubRegIndexNameOffsets[] = {
32 0,
33 7,
34};
35
36static const TargetRegisterInfo::SubRegCoveredBits AVRSubRegIdxRangeTable[] = {
37 { .Offset: 4294967295, .Size: 4294967295 },
38 { .Offset: 8, .Size: 8 }, // sub_hi
39 { .Offset: 0, .Size: 8 }, // sub_lo
40};
41
42
43static const LaneBitmask AVRSubRegIndexLaneMaskTable[] = {
44 LaneBitmask::getAll(),
45 LaneBitmask(0x0000000000000001), // sub_hi
46 LaneBitmask(0x0000000000000002), // sub_lo
47 };
48
49
50
51static const TargetRegisterInfo::RegClassInfo AVRRegClassInfos[] = {
52 // Mode = 0 (DefaultMode)
53 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // GPR8
54 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // GPR8NOZ
55 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // GPR8lo
56 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // LD8
57 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // GPR8NOZ_and_LD8
58 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // LD8lo
59 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 0 }, // CCR
60 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS
61 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ
62 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSMOVW
63 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSMOVW_and_DREGSNOZ
64 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8
65 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
66 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_LD8
67 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
68 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_GPR8lo
69 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_GPR8lo
70 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DLDREGS
71 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8lo
72 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_LD8lo
73 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSlo
74 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DLDREGS_and_DREGSNOZ
75 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
76 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSLD8lo
77 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // IWREGS
78 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_IWREGS
79 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // PTRREGS
80 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_PTRREGS
81 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // PTRDISPREGS
82 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_PTRDISPREGS
83 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
84 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // GPRSP
85 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*AVRVTLists+*/.VTListOffset: 2 }, // ZREG
86};
87
88static const uint8_t AVRCostPerUseTable[] = {
890, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
90
91
92static const bool AVRInAllocatableClassTable[] = {
93false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
94
95
96static const TargetRegisterInfoDesc AVRRegInfoDesc = { // Extra Descriptors
97.CostPerUse: AVRCostPerUseTable, .NumCosts: 1, .InAllocatableClass: AVRInAllocatableClassTable};
98
99unsigned AVRGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
100 static const uint8_t Rows[1][2] = {
101 { 0, 0, },
102 };
103
104 --IdxA; assert(IdxA < 2); (void) IdxA;
105 --IdxB; assert(IdxB < 2);
106 return Rows[0][IdxB];
107}
108
109unsigned AVRGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
110 static const uint8_t Table[2][2] = {
111 { 0, 0, },
112 { 0, 0, },
113 };
114
115 --IdxA; assert(IdxA < 2);
116 --IdxB; assert(IdxB < 2);
117 return Table[IdxA][IdxB];
118 }
119
120 struct MaskRolOp {
121 LaneBitmask Mask;
122 uint8_t RotateLeft;
123 };
124 static const MaskRolOp LaneMaskComposeSequences[] = {
125 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
126 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 2
127 };
128 static const uint8_t CompositeSequences[] = {
129 0, // to sub_hi
130 2 // to sub_lo
131 };
132
133LaneBitmask AVRGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
134 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
135 LaneBitmask Result;
136 for (const MaskRolOp *Ops =
137 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
138 Ops->Mask.any(); ++Ops) {
139 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
140 if (unsigned S = Ops->RotateLeft)
141 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
142 else
143 Result |= LaneBitmask(M);
144 }
145 return Result;
146}
147
148LaneBitmask AVRGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
149 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
150 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
151 LaneBitmask Result;
152 for (const MaskRolOp *Ops =
153 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
154 Ops->Mask.any(); ++Ops) {
155 LaneBitmask::Type M = LaneMask.getAsInteger();
156 if (unsigned S = Ops->RotateLeft)
157 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
158 else
159 Result |= LaneBitmask(M);
160 }
161 return Result;
162}
163
164const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
165 static constexpr uint8_t Table[33][2] = {
166 { // GPR8
167 0, // sub_hi
168 0, // sub_lo
169 },
170 { // GPR8NOZ
171 0, // sub_hi
172 0, // sub_lo
173 },
174 { // GPR8lo
175 0, // sub_hi
176 0, // sub_lo
177 },
178 { // LD8
179 0, // sub_hi
180 0, // sub_lo
181 },
182 { // GPR8NOZ_and_LD8
183 0, // sub_hi
184 0, // sub_lo
185 },
186 { // LD8lo
187 0, // sub_hi
188 0, // sub_lo
189 },
190 { // CCR
191 0, // sub_hi
192 0, // sub_lo
193 },
194 { // DREGS
195 8, // sub_hi -> DREGS
196 8, // sub_lo -> DREGS
197 },
198 { // DREGSNOZ
199 9, // sub_hi -> DREGSNOZ
200 9, // sub_lo -> DREGSNOZ
201 },
202 { // DREGSMOVW
203 10, // sub_hi -> DREGSMOVW
204 10, // sub_lo -> DREGSMOVW
205 },
206 { // DREGSMOVW_and_DREGSNOZ
207 11, // sub_hi -> DREGSMOVW_and_DREGSNOZ
208 11, // sub_lo -> DREGSMOVW_and_DREGSNOZ
209 },
210 { // DREGS_with_sub_hi_in_LD8
211 12, // sub_hi -> DREGS_with_sub_hi_in_LD8
212 12, // sub_lo -> DREGS_with_sub_hi_in_LD8
213 },
214 { // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
215 13, // sub_hi -> DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
216 13, // sub_lo -> DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
217 },
218 { // DREGS_with_sub_lo_in_LD8
219 14, // sub_hi -> DREGS_with_sub_lo_in_LD8
220 14, // sub_lo -> DREGS_with_sub_lo_in_LD8
221 },
222 { // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
223 15, // sub_hi -> DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
224 15, // sub_lo -> DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
225 },
226 { // DREGS_with_sub_lo_in_GPR8lo
227 16, // sub_hi -> DREGS_with_sub_lo_in_GPR8lo
228 16, // sub_lo -> DREGS_with_sub_lo_in_GPR8lo
229 },
230 { // DREGS_with_sub_hi_in_GPR8lo
231 17, // sub_hi -> DREGS_with_sub_hi_in_GPR8lo
232 17, // sub_lo -> DREGS_with_sub_hi_in_GPR8lo
233 },
234 { // DLDREGS
235 18, // sub_hi -> DLDREGS
236 18, // sub_lo -> DLDREGS
237 },
238 { // DREGS_with_sub_hi_in_LD8lo
239 19, // sub_hi -> DREGS_with_sub_hi_in_LD8lo
240 19, // sub_lo -> DREGS_with_sub_hi_in_LD8lo
241 },
242 { // DREGS_with_sub_lo_in_LD8lo
243 20, // sub_hi -> DREGS_with_sub_lo_in_LD8lo
244 20, // sub_lo -> DREGS_with_sub_lo_in_LD8lo
245 },
246 { // DREGSlo
247 21, // sub_hi -> DREGSlo
248 21, // sub_lo -> DREGSlo
249 },
250 { // DLDREGS_and_DREGSNOZ
251 22, // sub_hi -> DLDREGS_and_DREGSNOZ
252 22, // sub_lo -> DLDREGS_and_DREGSNOZ
253 },
254 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
255 23, // sub_hi -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
256 23, // sub_lo -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
257 },
258 { // DREGSLD8lo
259 24, // sub_hi -> DREGSLD8lo
260 24, // sub_lo -> DREGSLD8lo
261 },
262 { // IWREGS
263 25, // sub_hi -> IWREGS
264 25, // sub_lo -> IWREGS
265 },
266 { // DREGSNOZ_and_IWREGS
267 26, // sub_hi -> DREGSNOZ_and_IWREGS
268 26, // sub_lo -> DREGSNOZ_and_IWREGS
269 },
270 { // PTRREGS
271 27, // sub_hi -> PTRREGS
272 27, // sub_lo -> PTRREGS
273 },
274 { // DREGSNOZ_and_PTRREGS
275 28, // sub_hi -> DREGSNOZ_and_PTRREGS
276 28, // sub_lo -> DREGSNOZ_and_PTRREGS
277 },
278 { // PTRDISPREGS
279 29, // sub_hi -> PTRDISPREGS
280 29, // sub_lo -> PTRDISPREGS
281 },
282 { // DREGSNOZ_and_PTRDISPREGS
283 30, // sub_hi -> DREGSNOZ_and_PTRDISPREGS
284 30, // sub_lo -> DREGSNOZ_and_PTRDISPREGS
285 },
286 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
287 31, // sub_hi -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
288 31, // sub_lo -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
289 },
290 { // GPRSP
291 32, // sub_hi -> GPRSP
292 32, // sub_lo -> GPRSP
293 },
294 { // ZREG
295 33, // sub_hi -> ZREG
296 33, // sub_lo -> ZREG
297 },
298
299 };
300 assert(RC && "Missing regclass");
301 if (!Idx) return RC;
302 --Idx;
303 assert(Idx < 2 && "Bad subreg");
304 unsigned TV = Table[RC->getID()][Idx];
305 return TV ? getRegClass(i: TV - 1) : nullptr;
306}const TargetRegisterClass *AVRGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
307 static constexpr uint8_t Table[33][2] = {
308 { // GPR8
309 0, // GPR8:sub_hi
310 0, // GPR8:sub_lo
311 },
312 { // GPR8NOZ
313 0, // GPR8NOZ:sub_hi
314 0, // GPR8NOZ:sub_lo
315 },
316 { // GPR8lo
317 0, // GPR8lo:sub_hi
318 0, // GPR8lo:sub_lo
319 },
320 { // LD8
321 0, // LD8:sub_hi
322 0, // LD8:sub_lo
323 },
324 { // GPR8NOZ_and_LD8
325 0, // GPR8NOZ_and_LD8:sub_hi
326 0, // GPR8NOZ_and_LD8:sub_lo
327 },
328 { // LD8lo
329 0, // LD8lo:sub_hi
330 0, // LD8lo:sub_lo
331 },
332 { // CCR
333 0, // CCR:sub_hi
334 0, // CCR:sub_lo
335 },
336 { // DREGS
337 1, // DREGS:sub_hi -> GPR8
338 1, // DREGS:sub_lo -> GPR8
339 },
340 { // DREGSNOZ
341 2, // DREGSNOZ:sub_hi -> GPR8NOZ
342 2, // DREGSNOZ:sub_lo -> GPR8NOZ
343 },
344 { // DREGSMOVW
345 1, // DREGSMOVW:sub_hi -> GPR8
346 1, // DREGSMOVW:sub_lo -> GPR8
347 },
348 { // DREGSMOVW_and_DREGSNOZ
349 2, // DREGSMOVW_and_DREGSNOZ:sub_hi -> GPR8NOZ
350 2, // DREGSMOVW_and_DREGSNOZ:sub_lo -> GPR8NOZ
351 },
352 { // DREGS_with_sub_hi_in_LD8
353 4, // DREGS_with_sub_hi_in_LD8:sub_hi -> LD8
354 1, // DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8
355 },
356 { // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
357 5, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8:sub_hi -> GPR8NOZ_and_LD8
358 2, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8NOZ
359 },
360 { // DREGS_with_sub_lo_in_LD8
361 4, // DREGS_with_sub_lo_in_LD8:sub_hi -> LD8
362 4, // DREGS_with_sub_lo_in_LD8:sub_lo -> LD8
363 },
364 { // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
365 5, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8:sub_hi -> GPR8NOZ_and_LD8
366 5, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8:sub_lo -> GPR8NOZ_and_LD8
367 },
368 { // DREGS_with_sub_lo_in_GPR8lo
369 2, // DREGS_with_sub_lo_in_GPR8lo:sub_hi -> GPR8NOZ
370 3, // DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
371 },
372 { // DREGS_with_sub_hi_in_GPR8lo
373 3, // DREGS_with_sub_hi_in_GPR8lo:sub_hi -> GPR8lo
374 3, // DREGS_with_sub_hi_in_GPR8lo:sub_lo -> GPR8lo
375 },
376 { // DLDREGS
377 4, // DLDREGS:sub_hi -> LD8
378 4, // DLDREGS:sub_lo -> LD8
379 },
380 { // DREGS_with_sub_hi_in_LD8lo
381 6, // DREGS_with_sub_hi_in_LD8lo:sub_hi -> LD8lo
382 2, // DREGS_with_sub_hi_in_LD8lo:sub_lo -> GPR8NOZ
383 },
384 { // DREGS_with_sub_lo_in_LD8lo
385 5, // DREGS_with_sub_lo_in_LD8lo:sub_hi -> GPR8NOZ_and_LD8
386 6, // DREGS_with_sub_lo_in_LD8lo:sub_lo -> LD8lo
387 },
388 { // DREGSlo
389 3, // DREGSlo:sub_hi -> GPR8lo
390 3, // DREGSlo:sub_lo -> GPR8lo
391 },
392 { // DLDREGS_and_DREGSNOZ
393 5, // DLDREGS_and_DREGSNOZ:sub_hi -> GPR8NOZ_and_LD8
394 5, // DLDREGS_and_DREGSNOZ:sub_lo -> GPR8NOZ_and_LD8
395 },
396 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
397 6, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_hi -> LD8lo
398 6, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_lo -> LD8lo
399 },
400 { // DREGSLD8lo
401 6, // DREGSLD8lo:sub_hi -> LD8lo
402 6, // DREGSLD8lo:sub_lo -> LD8lo
403 },
404 { // IWREGS
405 4, // IWREGS:sub_hi -> LD8
406 4, // IWREGS:sub_lo -> LD8
407 },
408 { // DREGSNOZ_and_IWREGS
409 5, // DREGSNOZ_and_IWREGS:sub_hi -> GPR8NOZ_and_LD8
410 5, // DREGSNOZ_and_IWREGS:sub_lo -> GPR8NOZ_and_LD8
411 },
412 { // PTRREGS
413 4, // PTRREGS:sub_hi -> LD8
414 4, // PTRREGS:sub_lo -> LD8
415 },
416 { // DREGSNOZ_and_PTRREGS
417 5, // DREGSNOZ_and_PTRREGS:sub_hi -> GPR8NOZ_and_LD8
418 5, // DREGSNOZ_and_PTRREGS:sub_lo -> GPR8NOZ_and_LD8
419 },
420 { // PTRDISPREGS
421 4, // PTRDISPREGS:sub_hi -> LD8
422 4, // PTRDISPREGS:sub_lo -> LD8
423 },
424 { // DREGSNOZ_and_PTRDISPREGS
425 5, // DREGSNOZ_and_PTRDISPREGS:sub_hi -> GPR8NOZ_and_LD8
426 5, // DREGSNOZ_and_PTRDISPREGS:sub_lo -> GPR8NOZ_and_LD8
427 },
428 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
429 6, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_hi -> LD8lo
430 3, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
431 },
432 { // GPRSP
433 0, // GPRSP:sub_hi
434 0, // GPRSP:sub_lo
435 },
436 { // ZREG
437 4, // ZREG:sub_hi -> LD8
438 4, // ZREG:sub_lo -> LD8
439 },
440
441 };
442 assert(RC && "Missing regclass");
443 if (!Idx) return RC;
444 --Idx;
445 assert(Idx < 2 && "Bad subreg");
446 unsigned TV = Table[RC->getID()][Idx];
447 return TV ? getRegClass(i: TV - 1) : nullptr;
448}/// Get the weight in units of pressure for this register class.
449const RegClassWeight &AVRGenRegisterInfo::
450getRegClassWeight(const TargetRegisterClass *RC) const {
451 static const RegClassWeight RCWeightTable[] = {
452 {.RegWeight: 1, .WeightLimit: 32}, // GPR8
453 {.RegWeight: 1, .WeightLimit: 30}, // GPR8NOZ
454 {.RegWeight: 1, .WeightLimit: 16}, // GPR8lo
455 {.RegWeight: 1, .WeightLimit: 16}, // LD8
456 {.RegWeight: 1, .WeightLimit: 14}, // GPR8NOZ_and_LD8
457 {.RegWeight: 1, .WeightLimit: 8}, // LD8lo
458 {.RegWeight: 1, .WeightLimit: 1}, // CCR
459 {.RegWeight: 2, .WeightLimit: 32}, // DREGS
460 {.RegWeight: 2, .WeightLimit: 30}, // DREGSNOZ
461 {.RegWeight: 2, .WeightLimit: 32}, // DREGSMOVW
462 {.RegWeight: 2, .WeightLimit: 30}, // DREGSMOVW_and_DREGSNOZ
463 {.RegWeight: 2, .WeightLimit: 17}, // DREGS_with_sub_hi_in_LD8
464 {.RegWeight: 2, .WeightLimit: 15}, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
465 {.RegWeight: 2, .WeightLimit: 16}, // DREGS_with_sub_lo_in_LD8
466 {.RegWeight: 2, .WeightLimit: 14}, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
467 {.RegWeight: 2, .WeightLimit: 17}, // DREGS_with_sub_lo_in_GPR8lo
468 {.RegWeight: 2, .WeightLimit: 16}, // DREGS_with_sub_hi_in_GPR8lo
469 {.RegWeight: 2, .WeightLimit: 16}, // DLDREGS
470 {.RegWeight: 2, .WeightLimit: 9}, // DREGS_with_sub_hi_in_LD8lo
471 {.RegWeight: 2, .WeightLimit: 9}, // DREGS_with_sub_lo_in_LD8lo
472 {.RegWeight: 2, .WeightLimit: 16}, // DREGSlo
473 {.RegWeight: 2, .WeightLimit: 14}, // DLDREGS_and_DREGSNOZ
474 {.RegWeight: 2, .WeightLimit: 8}, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
475 {.RegWeight: 2, .WeightLimit: 8}, // DREGSLD8lo
476 {.RegWeight: 2, .WeightLimit: 8}, // IWREGS
477 {.RegWeight: 2, .WeightLimit: 6}, // DREGSNOZ_and_IWREGS
478 {.RegWeight: 2, .WeightLimit: 6}, // PTRREGS
479 {.RegWeight: 2, .WeightLimit: 4}, // DREGSNOZ_and_PTRREGS
480 {.RegWeight: 2, .WeightLimit: 4}, // PTRDISPREGS
481 {.RegWeight: 2, .WeightLimit: 2}, // DREGSNOZ_and_PTRDISPREGS
482 {.RegWeight: 2, .WeightLimit: 2}, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
483 {.RegWeight: 2, .WeightLimit: 2}, // GPRSP
484 {.RegWeight: 2, .WeightLimit: 2}, // ZREG
485 };
486 return RCWeightTable[RC->getID()];
487}
488
489/// Get the weight in units of pressure for this register unit.
490unsigned AVRGenRegisterInfo::
491getRegUnitWeight(MCRegUnit RegUnit) const {
492 assert(static_cast<unsigned>(RegUnit) < 35 && "invalid register unit");
493 // All register units have unit weight.
494 return 1;
495}
496
497
498// Get the number of dimensions of register pressure.
499unsigned AVRGenRegisterInfo::getNumRegPressureSets() const {
500 return 9;
501}
502
503// Get the name of this register unit pressure set.
504const char *AVRGenRegisterInfo::
505getRegPressureSetName(unsigned Idx) const {
506 static const char *PressureNameTable[] = {
507 "CCR",
508 "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo",
509 "GPRSP",
510 "IWREGS",
511 "LD8lo",
512 "LD8",
513 "GPR8lo",
514 "GPR8lo_with_LD8lo",
515 "GPR8",
516 };
517 return PressureNameTable[Idx];
518}
519
520// Get the register unit pressure limit for this dimension.
521// This limit must be adjusted dynamically for reserved registers.
522unsigned AVRGenRegisterInfo::
523getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
524 static const uint8_t PressureLimitTable[] = {
525 1, // 0: CCR
526 2, // 1: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
527 2, // 2: GPRSP
528 8, // 3: IWREGS
529 10, // 4: LD8lo
530 17, // 5: LD8
531 17, // 6: GPR8lo
532 25, // 7: GPR8lo_with_LD8lo
533 32, // 8: GPR8
534 };
535 return PressureLimitTable[Idx];
536}
537
538/// Table of pressure sets per register class or unit.
539static const int RCSetsTable[] = {
540 /* 0 */ 0, -1,
541 /* 2 */ 2, -1,
542 /* 4 */ 3, 5, 8, -1,
543 /* 8 */ 3, 4, 5, 7, 8, -1,
544 /* 14 */ 1, 4, 5, 6, 7, 8, -1,
545};
546
547/// Get the dimensions of register pressure impacted by this register class.
548/// Returns a -1 terminated array of pressure set IDs
549const int *AVRGenRegisterInfo::
550getRegClassPressureSets(const TargetRegisterClass *RC) const {
551 static const uint8_t RCSetStartTable[] = {
552 6,6,17,5,5,9,0,6,6,6,6,5,5,5,5,17,17,5,9,9,17,5,9,9,4,4,4,4,4,4,14,2,4,};
553 return &RCSetsTable[RCSetStartTable[RC->getID()]];
554}
555
556/// Get the dimensions of register pressure impacted by this register unit.
557/// Returns a -1 terminated array of pressure set IDs
558const int *AVRGenRegisterInfo::
559getRegUnitPressureSets(MCRegUnit RegUnit) const {
560 assert(static_cast<unsigned>(RegUnit) < 35 && "invalid register unit");
561 static const uint8_t RUSetStartTable[] = {
562 2,2,0,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,14,14,9,9,9,9,9,9,9,8,4,4,4,4,4,4,4,};
563 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
564}
565
566
567// Register to minimal register class mapping
568
569const TargetRegisterClass *AVRGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
570 static const uint16_t InvalidRegClassID = UINT16_MAX;
571
572 static const uint16_t Mapping[62] = {
573 InvalidRegClassID, // NoRegister
574 AVR::GPRSPRegClassID, // SP
575 InvalidRegClassID, // SPH
576 InvalidRegClassID, // SPL
577 AVR::CCRRegClassID, // SREG
578 AVR::GPR8loRegClassID, // R0
579 AVR::GPR8loRegClassID, // R1
580 AVR::GPR8loRegClassID, // R2
581 AVR::GPR8loRegClassID, // R3
582 AVR::GPR8loRegClassID, // R4
583 AVR::GPR8loRegClassID, // R5
584 AVR::GPR8loRegClassID, // R6
585 AVR::GPR8loRegClassID, // R7
586 AVR::GPR8loRegClassID, // R8
587 AVR::GPR8loRegClassID, // R9
588 AVR::GPR8loRegClassID, // R10
589 AVR::GPR8loRegClassID, // R11
590 AVR::GPR8loRegClassID, // R12
591 AVR::GPR8loRegClassID, // R13
592 AVR::GPR8loRegClassID, // R14
593 AVR::GPR8loRegClassID, // R15
594 AVR::LD8loRegClassID, // R16
595 AVR::LD8loRegClassID, // R17
596 AVR::LD8loRegClassID, // R18
597 AVR::LD8loRegClassID, // R19
598 AVR::LD8loRegClassID, // R20
599 AVR::LD8loRegClassID, // R21
600 AVR::LD8loRegClassID, // R22
601 AVR::LD8loRegClassID, // R23
602 AVR::GPR8NOZ_and_LD8RegClassID, // R24
603 AVR::GPR8NOZ_and_LD8RegClassID, // R25
604 AVR::GPR8NOZ_and_LD8RegClassID, // R26
605 AVR::GPR8NOZ_and_LD8RegClassID, // R27
606 AVR::GPR8NOZ_and_LD8RegClassID, // R28
607 AVR::GPR8NOZ_and_LD8RegClassID, // R29
608 AVR::LD8RegClassID, // R30
609 AVR::LD8RegClassID, // R31
610 AVR::DREGSloRegClassID, // R1R0
611 AVR::DREGSloRegClassID, // R3R2
612 AVR::DREGSloRegClassID, // R5R4
613 AVR::DREGSloRegClassID, // R7R6
614 AVR::DREGSloRegClassID, // R9R8
615 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, // R10R9
616 AVR::DREGSloRegClassID, // R11R10
617 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, // R12R11
618 AVR::DREGSloRegClassID, // R13R12
619 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, // R14R13
620 AVR::DREGSloRegClassID, // R15R14
621 AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID, // R16R15
622 AVR::DREGSLD8loRegClassID, // R17R16
623 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, // R18R17
624 AVR::DREGSLD8loRegClassID, // R19R18
625 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, // R20R19
626 AVR::DREGSLD8loRegClassID, // R21R20
627 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, // R22R21
628 AVR::DREGSLD8loRegClassID, // R23R22
629 AVR::DREGS_with_sub_lo_in_LD8loRegClassID, // R24R23
630 AVR::DREGSNOZ_and_IWREGSRegClassID, // R25R24
631 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, // R26R25
632 AVR::DREGSNOZ_and_PTRREGSRegClassID, // R27R26
633 AVR::DREGSNOZ_and_PTRDISPREGSRegClassID, // R29R28
634 AVR::ZREGRegClassID, // R31R30
635 };
636
637 assert(Reg < ArrayRef(Mapping).size());
638 unsigned RCID = Mapping[Reg.id()];
639 if (RCID == InvalidRegClassID)
640 return nullptr;
641 return &AVRMCRegisterClassStorage.Classes[RCID];
642}
643extern const MCRegisterDesc AVRRegDesc[];
644extern const int16_t AVRRegDiffLists[];
645extern const LaneBitmask AVRLaneMaskLists[];
646extern const char AVRRegStrings[];
647extern const char AVRRegClassStrings[];
648extern const MCPhysReg AVRRegUnitRoots[][2];
649extern const uint16_t AVRSubRegIdxLists[];
650extern const uint16_t AVRRegEncodingTable[];
651// AVR Dwarf<->LLVM register mappings.
652extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[];
653extern const unsigned AVRDwarfFlavour0Dwarf2LSize;
654
655extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[];
656extern const unsigned AVREHFlavour0Dwarf2LSize;
657
658extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[];
659extern const unsigned AVRDwarfFlavour0L2DwarfSize;
660
661extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[];
662extern const unsigned AVREHFlavour0L2DwarfSize;
663
664
665AVRGenRegisterInfo::
666AVRGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
667 unsigned PC, unsigned HwMode)
668 : TargetRegisterInfo(&AVRRegInfoDesc,
669 AVRSubRegIndexStrings, AVRSubRegIndexNameOffsets,
670 AVRSubRegIdxRangeTable, AVRSubRegIndexLaneMaskTable,
671
672 LaneBitmask(0xFFFFFFFFFFFFFFFF), AVRRegClassInfos, AVRVTLists, HwMode) {
673 InitMCRegisterInfo(D: AVRRegDesc, NR: 62, RA, PC,
674 C: &getAVRMCRegisterClass(RC: 0), NC: 33, RURoots: AVRRegUnitRoots, NRU: 35, DL: AVRRegDiffLists,
675 RUMS: AVRLaneMaskLists, Strings: AVRRegStrings, ClassStrings: AVRRegClassStrings, SubIndices: AVRSubRegIdxLists, NumIndices: 3,
676 RET: AVRRegEncodingTable, RUI: nullptr);
677
678 switch (DwarfFlavour) {
679 default:
680 llvm_unreachable("Unknown DWARF flavour");
681 case 0:
682 mapDwarfRegsToLLVMRegs(Map: AVRDwarfFlavour0Dwarf2L, Size: AVRDwarfFlavour0Dwarf2LSize, isEH: false);
683 break;
684 }
685 switch (EHFlavour) {
686 default:
687 llvm_unreachable("Unknown DWARF flavour");
688 case 0:
689 mapDwarfRegsToLLVMRegs(Map: AVREHFlavour0Dwarf2L, Size: AVREHFlavour0Dwarf2LSize, isEH: true);
690 break;
691 }
692 switch (DwarfFlavour) {
693 default:
694 llvm_unreachable("Unknown DWARF flavour");
695 case 0:
696 mapLLVMRegsToDwarfRegs(Map: AVRDwarfFlavour0L2Dwarf, Size: AVRDwarfFlavour0L2DwarfSize, isEH: false);
697 break;
698 }
699 switch (EHFlavour) {
700 default:
701 llvm_unreachable("Unknown DWARF flavour");
702 case 0:
703 mapLLVMRegsToDwarfRegs(Map: AVREHFlavour0L2Dwarf, Size: AVREHFlavour0L2DwarfSize, isEH: true);
704 break;
705 }
706}
707
708static const MCPhysReg CSR_Interrupts_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
709static const uint32_t CSR_Interrupts_RegMask[] = { 0xffffff80, 0x3fffffdf, };
710static const MCPhysReg CSR_InterruptsTiny_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, 0 };
711static const uint32_t CSR_InterruptsTiny_RegMask[] = { 0xff800000, 0x3ff8001f, };
712static const MCPhysReg CSR_Normal_SaveList[] = { AVR::R29, AVR::R28, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
713static const uint32_t CSR_Normal_RegMask[] = { 0x007fff80, 0x1003ffc6, };
714static const MCPhysReg CSR_NormalTiny_SaveList[] = { AVR::R29, AVR::R28, AVR::R19, AVR::R18, 0 };
715static const uint32_t CSR_NormalTiny_RegMask[] = { 0x01800000, 0x10080006, };
716
717
718ArrayRef<const uint32_t *> AVRGenRegisterInfo::getRegMasks() const {
719 static const uint32_t *const Masks[] = {
720 CSR_Interrupts_RegMask,
721 CSR_InterruptsTiny_RegMask,
722 CSR_Normal_RegMask,
723 CSR_NormalTiny_RegMask,
724 };
725 return ArrayRef(Masks);
726}
727
728bool AVRGenRegisterInfo::
729isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
730 return
731 false;
732}
733
734bool AVRGenRegisterInfo::
735isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
736 return
737 false;
738}
739
740bool AVRGenRegisterInfo::
741isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
742 return
743 false;
744}
745
746bool AVRGenRegisterInfo::
747isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
748 return
749 false;
750}
751
752bool AVRGenRegisterInfo::
753isConstantPhysReg(MCRegister PhysReg) const {
754 return
755 false;
756}
757
758ArrayRef<const char *> AVRGenRegisterInfo::getRegMaskNames() const {
759 static const char *Names[] = {
760 "CSR_Interrupts",
761 "CSR_InterruptsTiny",
762 "CSR_Normal",
763 "CSR_NormalTiny",
764 };
765 return ArrayRef(Names);
766}
767
768const AVRFrameLowering *
769AVRGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
770 return static_cast<const AVRFrameLowering *>(
771 MF.getSubtarget().getFrameLowering());
772}
773
774
775} // namespace llvm
776