1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass AVRMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char AVRSubRegIndexStrings[] = {
23 /* 0 */ "sub_hi\000"
24 /* 7 */ "sub_lo\000"
25};
26#ifdef __GNUC__
27#pragma GCC diagnostic pop
28#endif
29
30
31static constexpr uint32_t AVRSubRegIndexNameOffsets[] = {
32 0,
33 7,
34};
35
36static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
37 { .Offset: 65535, .Size: 65535 },
38 { .Offset: 8, .Size: 8 }, // sub_hi
39 { .Offset: 0, .Size: 8 }, // sub_lo
40};
41
42
43static const LaneBitmask SubRegIndexLaneMaskTable[] = {
44 LaneBitmask::getAll(),
45 LaneBitmask(0x0000000000000001), // sub_hi
46 LaneBitmask(0x0000000000000002), // sub_lo
47 };
48
49
50
51static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
52 // Mode = 0 (DefaultMode)
53 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GPR8
54 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GPR8NOZ
55 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GPR8lo
56 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // LD8
57 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GPR8NOZ_and_LD8
58 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // LD8lo
59 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // CCR
60 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS
61 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ
62 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSMOVW
63 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSMOVW_and_DREGSNOZ
64 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8
65 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
66 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_LD8
67 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
68 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_GPR8lo
69 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_GPR8lo
70 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DLDREGS
71 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8lo
72 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_lo_in_LD8lo
73 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSlo
74 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DLDREGS_and_DREGSNOZ
75 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
76 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSLD8lo
77 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // IWREGS
78 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_IWREGS
79 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // PTRREGS
80 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_PTRREGS
81 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // PTRDISPREGS
82 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGSNOZ_and_PTRDISPREGS
83 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
84 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // GPRSP
85 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 2 }, // ZREG
86};
87static const uint32_t GPR8SubClassMask[] = {
88 0x0000003f, 0x00000000,
89 0x7fffff80, 0x00000001, // sub_hi
90 0x7fffff80, 0x00000001, // sub_lo
91};
92
93static const uint32_t GPR8NOZSubClassMask[] = {
94 0x00000036, 0x00000000,
95 0x6afdd500, 0x00000000, // sub_hi
96 0x6afdd500, 0x00000000, // sub_lo
97};
98
99static const uint32_t GPR8loSubClassMask[] = {
100 0x00000004, 0x00000000,
101 0x00110000, 0x00000000, // sub_hi
102 0x40118000, 0x00000000, // sub_lo
103};
104
105static const uint32_t LD8SubClassMask[] = {
106 0x00000038, 0x00000000,
107 0x7fee7800, 0x00000001, // sub_hi
108 0x3fea6000, 0x00000001, // sub_lo
109};
110
111static const uint32_t GPR8NOZ_and_LD8SubClassMask[] = {
112 0x00000030, 0x00000000,
113 0x6aec5000, 0x00000000, // sub_hi
114 0x2ae84000, 0x00000000, // sub_lo
115};
116
117static const uint32_t LD8loSubClassMask[] = {
118 0x00000020, 0x00000000,
119 0x40c40000, 0x00000000, // sub_hi
120 0x00c80000, 0x00000000, // sub_lo
121};
122
123static const uint32_t CCRSubClassMask[] = {
124 0x00000040, 0x00000000,
125};
126
127static const uint32_t DREGSSubClassMask[] = {
128 0x7fffff80, 0x00000001,
129};
130
131static const uint32_t DREGSNOZSubClassMask[] = {
132 0x6afdd500, 0x00000000,
133};
134
135static const uint32_t DREGSMOVWSubClassMask[] = {
136 0x3fb20600, 0x00000001,
137};
138
139static const uint32_t DREGSMOVW_and_DREGSNOZSubClassMask[] = {
140 0x2ab00400, 0x00000000,
141};
142
143static const uint32_t DREGS_with_sub_hi_in_LD8SubClassMask[] = {
144 0x7fee7800, 0x00000001,
145};
146
147static const uint32_t DREGSNOZ_and_DREGS_with_sub_hi_in_LD8SubClassMask[] = {
148 0x6aec5000, 0x00000000,
149};
150
151static const uint32_t DREGS_with_sub_lo_in_LD8SubClassMask[] = {
152 0x3fea6000, 0x00000001,
153};
154
155static const uint32_t DREGSNOZ_and_DREGS_with_sub_lo_in_LD8SubClassMask[] = {
156 0x2ae84000, 0x00000000,
157};
158
159static const uint32_t DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
160 0x40118000, 0x00000000,
161};
162
163static const uint32_t DREGS_with_sub_hi_in_GPR8loSubClassMask[] = {
164 0x00110000, 0x00000000,
165};
166
167static const uint32_t DLDREGSSubClassMask[] = {
168 0x3fa20000, 0x00000001,
169};
170
171static const uint32_t DREGS_with_sub_hi_in_LD8loSubClassMask[] = {
172 0x40c40000, 0x00000000,
173};
174
175static const uint32_t DREGS_with_sub_lo_in_LD8loSubClassMask[] = {
176 0x00c80000, 0x00000000,
177};
178
179static const uint32_t DREGSloSubClassMask[] = {
180 0x00100000, 0x00000000,
181};
182
183static const uint32_t DLDREGS_and_DREGSNOZSubClassMask[] = {
184 0x2aa00000, 0x00000000,
185};
186
187static const uint32_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask[] = {
188 0x00c00000, 0x00000000,
189};
190
191static const uint32_t DREGSLD8loSubClassMask[] = {
192 0x00800000, 0x00000000,
193};
194
195static const uint32_t IWREGSSubClassMask[] = {
196 0x3f000000, 0x00000001,
197};
198
199static const uint32_t DREGSNOZ_and_IWREGSSubClassMask[] = {
200 0x2a000000, 0x00000000,
201};
202
203static const uint32_t PTRREGSSubClassMask[] = {
204 0x3c000000, 0x00000001,
205};
206
207static const uint32_t DREGSNOZ_and_PTRREGSSubClassMask[] = {
208 0x28000000, 0x00000000,
209};
210
211static const uint32_t PTRDISPREGSSubClassMask[] = {
212 0x30000000, 0x00000001,
213};
214
215static const uint32_t DREGSNOZ_and_PTRDISPREGSSubClassMask[] = {
216 0x20000000, 0x00000000,
217};
218
219static const uint32_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
220 0x40000000, 0x00000000,
221};
222
223static const uint32_t GPRSPSubClassMask[] = {
224 0x80000000, 0x00000000,
225};
226
227static const uint32_t ZREGSubClassMask[] = {
228 0x00000000, 0x00000001,
229};
230
231static const uint16_t SuperRegIdxSeqs[] = {
232 /* 0 */ 1, 2, 0,
233};
234
235static unsigned const GPR8NOZSuperclasses[] = {
236 AVR::GPR8RegClassID,
237};
238
239static unsigned const GPR8loSuperclasses[] = {
240 AVR::GPR8RegClassID,
241 AVR::GPR8NOZRegClassID,
242};
243
244static unsigned const LD8Superclasses[] = {
245 AVR::GPR8RegClassID,
246};
247
248static unsigned const GPR8NOZ_and_LD8Superclasses[] = {
249 AVR::GPR8RegClassID,
250 AVR::GPR8NOZRegClassID,
251 AVR::LD8RegClassID,
252};
253
254static unsigned const LD8loSuperclasses[] = {
255 AVR::GPR8RegClassID,
256 AVR::GPR8NOZRegClassID,
257 AVR::LD8RegClassID,
258 AVR::GPR8NOZ_and_LD8RegClassID,
259};
260
261static unsigned const DREGSNOZSuperclasses[] = {
262 AVR::DREGSRegClassID,
263};
264
265static unsigned const DREGSMOVWSuperclasses[] = {
266 AVR::DREGSRegClassID,
267};
268
269static unsigned const DREGSMOVW_and_DREGSNOZSuperclasses[] = {
270 AVR::DREGSRegClassID,
271 AVR::DREGSNOZRegClassID,
272 AVR::DREGSMOVWRegClassID,
273};
274
275static unsigned const DREGS_with_sub_hi_in_LD8Superclasses[] = {
276 AVR::DREGSRegClassID,
277};
278
279static unsigned const DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Superclasses[] = {
280 AVR::DREGSRegClassID,
281 AVR::DREGSNOZRegClassID,
282 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
283};
284
285static unsigned const DREGS_with_sub_lo_in_LD8Superclasses[] = {
286 AVR::DREGSRegClassID,
287 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
288};
289
290static unsigned const DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Superclasses[] = {
291 AVR::DREGSRegClassID,
292 AVR::DREGSNOZRegClassID,
293 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
294 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
295 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
296};
297
298static unsigned const DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
299 AVR::DREGSRegClassID,
300 AVR::DREGSNOZRegClassID,
301};
302
303static unsigned const DREGS_with_sub_hi_in_GPR8loSuperclasses[] = {
304 AVR::DREGSRegClassID,
305 AVR::DREGSNOZRegClassID,
306 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
307};
308
309static unsigned const DLDREGSSuperclasses[] = {
310 AVR::DREGSRegClassID,
311 AVR::DREGSMOVWRegClassID,
312 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
313 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
314};
315
316static unsigned const DREGS_with_sub_hi_in_LD8loSuperclasses[] = {
317 AVR::DREGSRegClassID,
318 AVR::DREGSNOZRegClassID,
319 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
320 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
321};
322
323static unsigned const DREGS_with_sub_lo_in_LD8loSuperclasses[] = {
324 AVR::DREGSRegClassID,
325 AVR::DREGSNOZRegClassID,
326 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
327 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
328 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
329 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
330};
331
332static unsigned const DREGSloSuperclasses[] = {
333 AVR::DREGSRegClassID,
334 AVR::DREGSNOZRegClassID,
335 AVR::DREGSMOVWRegClassID,
336 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
337 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
338 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID,
339};
340
341static unsigned const DLDREGS_and_DREGSNOZSuperclasses[] = {
342 AVR::DREGSRegClassID,
343 AVR::DREGSNOZRegClassID,
344 AVR::DREGSMOVWRegClassID,
345 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
346 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
347 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
348 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
349 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
350 AVR::DLDREGSRegClassID,
351};
352
353static unsigned const DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses[] = {
354 AVR::DREGSRegClassID,
355 AVR::DREGSNOZRegClassID,
356 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
357 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
358 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
359 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
360 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
361 AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
362};
363
364static unsigned const DREGSLD8loSuperclasses[] = {
365 AVR::DREGSRegClassID,
366 AVR::DREGSNOZRegClassID,
367 AVR::DREGSMOVWRegClassID,
368 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
369 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
370 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
371 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
372 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
373 AVR::DLDREGSRegClassID,
374 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
375 AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
376 AVR::DLDREGS_and_DREGSNOZRegClassID,
377 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID,
378};
379
380static unsigned const IWREGSSuperclasses[] = {
381 AVR::DREGSRegClassID,
382 AVR::DREGSMOVWRegClassID,
383 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
384 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
385 AVR::DLDREGSRegClassID,
386};
387
388static unsigned const DREGSNOZ_and_IWREGSSuperclasses[] = {
389 AVR::DREGSRegClassID,
390 AVR::DREGSNOZRegClassID,
391 AVR::DREGSMOVWRegClassID,
392 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
393 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
394 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
395 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
396 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
397 AVR::DLDREGSRegClassID,
398 AVR::DLDREGS_and_DREGSNOZRegClassID,
399 AVR::IWREGSRegClassID,
400};
401
402static unsigned const PTRREGSSuperclasses[] = {
403 AVR::DREGSRegClassID,
404 AVR::DREGSMOVWRegClassID,
405 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
406 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
407 AVR::DLDREGSRegClassID,
408 AVR::IWREGSRegClassID,
409};
410
411static unsigned const DREGSNOZ_and_PTRREGSSuperclasses[] = {
412 AVR::DREGSRegClassID,
413 AVR::DREGSNOZRegClassID,
414 AVR::DREGSMOVWRegClassID,
415 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
416 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
417 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
418 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
419 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
420 AVR::DLDREGSRegClassID,
421 AVR::DLDREGS_and_DREGSNOZRegClassID,
422 AVR::IWREGSRegClassID,
423 AVR::DREGSNOZ_and_IWREGSRegClassID,
424 AVR::PTRREGSRegClassID,
425};
426
427static unsigned const PTRDISPREGSSuperclasses[] = {
428 AVR::DREGSRegClassID,
429 AVR::DREGSMOVWRegClassID,
430 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
431 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
432 AVR::DLDREGSRegClassID,
433 AVR::IWREGSRegClassID,
434 AVR::PTRREGSRegClassID,
435};
436
437static unsigned const DREGSNOZ_and_PTRDISPREGSSuperclasses[] = {
438 AVR::DREGSRegClassID,
439 AVR::DREGSNOZRegClassID,
440 AVR::DREGSMOVWRegClassID,
441 AVR::DREGSMOVW_and_DREGSNOZRegClassID,
442 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
443 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
444 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
445 AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID,
446 AVR::DLDREGSRegClassID,
447 AVR::DLDREGS_and_DREGSNOZRegClassID,
448 AVR::IWREGSRegClassID,
449 AVR::DREGSNOZ_and_IWREGSRegClassID,
450 AVR::PTRREGSRegClassID,
451 AVR::DREGSNOZ_and_PTRREGSRegClassID,
452 AVR::PTRDISPREGSRegClassID,
453};
454
455static unsigned const DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
456 AVR::DREGSRegClassID,
457 AVR::DREGSNOZRegClassID,
458 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
459 AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID,
460 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
461 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
462};
463
464static unsigned const ZREGSuperclasses[] = {
465 AVR::DREGSRegClassID,
466 AVR::DREGSMOVWRegClassID,
467 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
468 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
469 AVR::DLDREGSRegClassID,
470 AVR::IWREGSRegClassID,
471 AVR::PTRREGSRegClassID,
472 AVR::PTRDISPREGSRegClassID,
473};
474
475namespace AVR {
476
477// Register class instances
478 extern const TargetRegisterClass GPR8RegClass = {
479 .MC: &AVRMCRegisterClasses[GPR8RegClassID],
480 .SubClassMask: GPR8SubClassMask,
481 .SuperRegIndices: SuperRegIdxSeqs + 0,
482 .LaneMask: LaneBitmask(0x0000000000000001),
483 .AllocationPriority: 0,
484 .GlobalPriority: false,
485 .TSFlags: 0x00, /* TSFlags */
486 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
487 .CoveredBySubRegs: false, /* CoveredBySubRegs */
488 .SuperClasses: nullptr, .SuperClassesSize: 0,
489 .OrderFunc: nullptr
490 };
491
492 extern const TargetRegisterClass GPR8NOZRegClass = {
493 .MC: &AVRMCRegisterClasses[GPR8NOZRegClassID],
494 .SubClassMask: GPR8NOZSubClassMask,
495 .SuperRegIndices: SuperRegIdxSeqs + 0,
496 .LaneMask: LaneBitmask(0x0000000000000001),
497 .AllocationPriority: 0,
498 .GlobalPriority: false,
499 .TSFlags: 0x00, /* TSFlags */
500 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
501 .CoveredBySubRegs: false, /* CoveredBySubRegs */
502 .SuperClasses: GPR8NOZSuperclasses, .SuperClassesSize: 1,
503 .OrderFunc: nullptr
504 };
505
506 extern const TargetRegisterClass GPR8loRegClass = {
507 .MC: &AVRMCRegisterClasses[GPR8loRegClassID],
508 .SubClassMask: GPR8loSubClassMask,
509 .SuperRegIndices: SuperRegIdxSeqs + 0,
510 .LaneMask: LaneBitmask(0x0000000000000001),
511 .AllocationPriority: 0,
512 .GlobalPriority: false,
513 .TSFlags: 0x00, /* TSFlags */
514 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
515 .CoveredBySubRegs: false, /* CoveredBySubRegs */
516 .SuperClasses: GPR8loSuperclasses, .SuperClassesSize: 2,
517 .OrderFunc: nullptr
518 };
519
520 extern const TargetRegisterClass LD8RegClass = {
521 .MC: &AVRMCRegisterClasses[LD8RegClassID],
522 .SubClassMask: LD8SubClassMask,
523 .SuperRegIndices: SuperRegIdxSeqs + 0,
524 .LaneMask: LaneBitmask(0x0000000000000001),
525 .AllocationPriority: 0,
526 .GlobalPriority: false,
527 .TSFlags: 0x00, /* TSFlags */
528 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
529 .CoveredBySubRegs: false, /* CoveredBySubRegs */
530 .SuperClasses: LD8Superclasses, .SuperClassesSize: 1,
531 .OrderFunc: nullptr
532 };
533
534 extern const TargetRegisterClass GPR8NOZ_and_LD8RegClass = {
535 .MC: &AVRMCRegisterClasses[GPR8NOZ_and_LD8RegClassID],
536 .SubClassMask: GPR8NOZ_and_LD8SubClassMask,
537 .SuperRegIndices: SuperRegIdxSeqs + 0,
538 .LaneMask: LaneBitmask(0x0000000000000001),
539 .AllocationPriority: 0,
540 .GlobalPriority: false,
541 .TSFlags: 0x00, /* TSFlags */
542 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
543 .CoveredBySubRegs: false, /* CoveredBySubRegs */
544 .SuperClasses: GPR8NOZ_and_LD8Superclasses, .SuperClassesSize: 3,
545 .OrderFunc: nullptr
546 };
547
548 extern const TargetRegisterClass LD8loRegClass = {
549 .MC: &AVRMCRegisterClasses[LD8loRegClassID],
550 .SubClassMask: LD8loSubClassMask,
551 .SuperRegIndices: SuperRegIdxSeqs + 0,
552 .LaneMask: LaneBitmask(0x0000000000000001),
553 .AllocationPriority: 0,
554 .GlobalPriority: false,
555 .TSFlags: 0x00, /* TSFlags */
556 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
557 .CoveredBySubRegs: false, /* CoveredBySubRegs */
558 .SuperClasses: LD8loSuperclasses, .SuperClassesSize: 4,
559 .OrderFunc: nullptr
560 };
561
562 extern const TargetRegisterClass CCRRegClass = {
563 .MC: &AVRMCRegisterClasses[CCRRegClassID],
564 .SubClassMask: CCRSubClassMask,
565 .SuperRegIndices: SuperRegIdxSeqs + 2,
566 .LaneMask: LaneBitmask(0x0000000000000001),
567 .AllocationPriority: 0,
568 .GlobalPriority: false,
569 .TSFlags: 0x00, /* TSFlags */
570 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
571 .CoveredBySubRegs: false, /* CoveredBySubRegs */
572 .SuperClasses: nullptr, .SuperClassesSize: 0,
573 .OrderFunc: nullptr
574 };
575
576 extern const TargetRegisterClass DREGSRegClass = {
577 .MC: &AVRMCRegisterClasses[DREGSRegClassID],
578 .SubClassMask: DREGSSubClassMask,
579 .SuperRegIndices: SuperRegIdxSeqs + 2,
580 .LaneMask: LaneBitmask(0x0000000000000003),
581 .AllocationPriority: 0,
582 .GlobalPriority: false,
583 .TSFlags: 0x00, /* TSFlags */
584 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
585 .CoveredBySubRegs: true, /* CoveredBySubRegs */
586 .SuperClasses: nullptr, .SuperClassesSize: 0,
587 .OrderFunc: nullptr
588 };
589
590 extern const TargetRegisterClass DREGSNOZRegClass = {
591 .MC: &AVRMCRegisterClasses[DREGSNOZRegClassID],
592 .SubClassMask: DREGSNOZSubClassMask,
593 .SuperRegIndices: SuperRegIdxSeqs + 2,
594 .LaneMask: LaneBitmask(0x0000000000000003),
595 .AllocationPriority: 0,
596 .GlobalPriority: false,
597 .TSFlags: 0x00, /* TSFlags */
598 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
599 .CoveredBySubRegs: true, /* CoveredBySubRegs */
600 .SuperClasses: DREGSNOZSuperclasses, .SuperClassesSize: 1,
601 .OrderFunc: nullptr
602 };
603
604 extern const TargetRegisterClass DREGSMOVWRegClass = {
605 .MC: &AVRMCRegisterClasses[DREGSMOVWRegClassID],
606 .SubClassMask: DREGSMOVWSubClassMask,
607 .SuperRegIndices: SuperRegIdxSeqs + 2,
608 .LaneMask: LaneBitmask(0x0000000000000003),
609 .AllocationPriority: 0,
610 .GlobalPriority: false,
611 .TSFlags: 0x00, /* TSFlags */
612 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
613 .CoveredBySubRegs: true, /* CoveredBySubRegs */
614 .SuperClasses: DREGSMOVWSuperclasses, .SuperClassesSize: 1,
615 .OrderFunc: nullptr
616 };
617
618 extern const TargetRegisterClass DREGSMOVW_and_DREGSNOZRegClass = {
619 .MC: &AVRMCRegisterClasses[DREGSMOVW_and_DREGSNOZRegClassID],
620 .SubClassMask: DREGSMOVW_and_DREGSNOZSubClassMask,
621 .SuperRegIndices: SuperRegIdxSeqs + 2,
622 .LaneMask: LaneBitmask(0x0000000000000003),
623 .AllocationPriority: 0,
624 .GlobalPriority: false,
625 .TSFlags: 0x00, /* TSFlags */
626 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
627 .CoveredBySubRegs: true, /* CoveredBySubRegs */
628 .SuperClasses: DREGSMOVW_and_DREGSNOZSuperclasses, .SuperClassesSize: 3,
629 .OrderFunc: nullptr
630 };
631
632 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8RegClass = {
633 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8RegClassID],
634 .SubClassMask: DREGS_with_sub_hi_in_LD8SubClassMask,
635 .SuperRegIndices: SuperRegIdxSeqs + 2,
636 .LaneMask: LaneBitmask(0x0000000000000003),
637 .AllocationPriority: 0,
638 .GlobalPriority: false,
639 .TSFlags: 0x00, /* TSFlags */
640 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
641 .CoveredBySubRegs: true, /* CoveredBySubRegs */
642 .SuperClasses: DREGS_with_sub_hi_in_LD8Superclasses, .SuperClassesSize: 1,
643 .OrderFunc: nullptr
644 };
645
646 extern const TargetRegisterClass DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClass = {
647 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID],
648 .SubClassMask: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8SubClassMask,
649 .SuperRegIndices: SuperRegIdxSeqs + 2,
650 .LaneMask: LaneBitmask(0x0000000000000003),
651 .AllocationPriority: 0,
652 .GlobalPriority: false,
653 .TSFlags: 0x00, /* TSFlags */
654 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
655 .CoveredBySubRegs: true, /* CoveredBySubRegs */
656 .SuperClasses: DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Superclasses, .SuperClassesSize: 3,
657 .OrderFunc: nullptr
658 };
659
660 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8RegClass = {
661 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8RegClassID],
662 .SubClassMask: DREGS_with_sub_lo_in_LD8SubClassMask,
663 .SuperRegIndices: SuperRegIdxSeqs + 2,
664 .LaneMask: LaneBitmask(0x0000000000000003),
665 .AllocationPriority: 0,
666 .GlobalPriority: false,
667 .TSFlags: 0x00, /* TSFlags */
668 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
669 .CoveredBySubRegs: true, /* CoveredBySubRegs */
670 .SuperClasses: DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 2,
671 .OrderFunc: nullptr
672 };
673
674 extern const TargetRegisterClass DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClass = {
675 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID],
676 .SubClassMask: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8SubClassMask,
677 .SuperRegIndices: SuperRegIdxSeqs + 2,
678 .LaneMask: LaneBitmask(0x0000000000000003),
679 .AllocationPriority: 0,
680 .GlobalPriority: false,
681 .TSFlags: 0x00, /* TSFlags */
682 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
683 .CoveredBySubRegs: true, /* CoveredBySubRegs */
684 .SuperClasses: DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 5,
685 .OrderFunc: nullptr
686 };
687
688 extern const TargetRegisterClass DREGS_with_sub_lo_in_GPR8loRegClass = {
689 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_GPR8loRegClassID],
690 .SubClassMask: DREGS_with_sub_lo_in_GPR8loSubClassMask,
691 .SuperRegIndices: SuperRegIdxSeqs + 2,
692 .LaneMask: LaneBitmask(0x0000000000000003),
693 .AllocationPriority: 0,
694 .GlobalPriority: false,
695 .TSFlags: 0x00, /* TSFlags */
696 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
697 .CoveredBySubRegs: true, /* CoveredBySubRegs */
698 .SuperClasses: DREGS_with_sub_lo_in_GPR8loSuperclasses, .SuperClassesSize: 2,
699 .OrderFunc: nullptr
700 };
701
702 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass = {
703 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_GPR8loRegClassID],
704 .SubClassMask: DREGS_with_sub_hi_in_GPR8loSubClassMask,
705 .SuperRegIndices: SuperRegIdxSeqs + 2,
706 .LaneMask: LaneBitmask(0x0000000000000003),
707 .AllocationPriority: 0,
708 .GlobalPriority: false,
709 .TSFlags: 0x00, /* TSFlags */
710 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
711 .CoveredBySubRegs: true, /* CoveredBySubRegs */
712 .SuperClasses: DREGS_with_sub_hi_in_GPR8loSuperclasses, .SuperClassesSize: 3,
713 .OrderFunc: nullptr
714 };
715
716 extern const TargetRegisterClass DLDREGSRegClass = {
717 .MC: &AVRMCRegisterClasses[DLDREGSRegClassID],
718 .SubClassMask: DLDREGSSubClassMask,
719 .SuperRegIndices: SuperRegIdxSeqs + 2,
720 .LaneMask: LaneBitmask(0x0000000000000003),
721 .AllocationPriority: 0,
722 .GlobalPriority: false,
723 .TSFlags: 0x00, /* TSFlags */
724 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
725 .CoveredBySubRegs: true, /* CoveredBySubRegs */
726 .SuperClasses: DLDREGSSuperclasses, .SuperClassesSize: 4,
727 .OrderFunc: nullptr
728 };
729
730 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8loRegClass = {
731 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8loRegClassID],
732 .SubClassMask: DREGS_with_sub_hi_in_LD8loSubClassMask,
733 .SuperRegIndices: SuperRegIdxSeqs + 2,
734 .LaneMask: LaneBitmask(0x0000000000000003),
735 .AllocationPriority: 0,
736 .GlobalPriority: false,
737 .TSFlags: 0x00, /* TSFlags */
738 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
739 .CoveredBySubRegs: true, /* CoveredBySubRegs */
740 .SuperClasses: DREGS_with_sub_hi_in_LD8loSuperclasses, .SuperClassesSize: 4,
741 .OrderFunc: nullptr
742 };
743
744 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8loRegClass = {
745 .MC: &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8loRegClassID],
746 .SubClassMask: DREGS_with_sub_lo_in_LD8loSubClassMask,
747 .SuperRegIndices: SuperRegIdxSeqs + 2,
748 .LaneMask: LaneBitmask(0x0000000000000003),
749 .AllocationPriority: 0,
750 .GlobalPriority: false,
751 .TSFlags: 0x00, /* TSFlags */
752 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
753 .CoveredBySubRegs: true, /* CoveredBySubRegs */
754 .SuperClasses: DREGS_with_sub_lo_in_LD8loSuperclasses, .SuperClassesSize: 6,
755 .OrderFunc: nullptr
756 };
757
758 extern const TargetRegisterClass DREGSloRegClass = {
759 .MC: &AVRMCRegisterClasses[DREGSloRegClassID],
760 .SubClassMask: DREGSloSubClassMask,
761 .SuperRegIndices: SuperRegIdxSeqs + 2,
762 .LaneMask: LaneBitmask(0x0000000000000003),
763 .AllocationPriority: 0,
764 .GlobalPriority: false,
765 .TSFlags: 0x00, /* TSFlags */
766 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
767 .CoveredBySubRegs: true, /* CoveredBySubRegs */
768 .SuperClasses: DREGSloSuperclasses, .SuperClassesSize: 6,
769 .OrderFunc: nullptr
770 };
771
772 extern const TargetRegisterClass DLDREGS_and_DREGSNOZRegClass = {
773 .MC: &AVRMCRegisterClasses[DLDREGS_and_DREGSNOZRegClassID],
774 .SubClassMask: DLDREGS_and_DREGSNOZSubClassMask,
775 .SuperRegIndices: SuperRegIdxSeqs + 2,
776 .LaneMask: LaneBitmask(0x0000000000000003),
777 .AllocationPriority: 0,
778 .GlobalPriority: false,
779 .TSFlags: 0x00, /* TSFlags */
780 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
781 .CoveredBySubRegs: true, /* CoveredBySubRegs */
782 .SuperClasses: DLDREGS_and_DREGSNOZSuperclasses, .SuperClassesSize: 9,
783 .OrderFunc: nullptr
784 };
785
786 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass = {
787 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID],
788 .SubClassMask: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask,
789 .SuperRegIndices: SuperRegIdxSeqs + 2,
790 .LaneMask: LaneBitmask(0x0000000000000003),
791 .AllocationPriority: 0,
792 .GlobalPriority: false,
793 .TSFlags: 0x00, /* TSFlags */
794 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
795 .CoveredBySubRegs: true, /* CoveredBySubRegs */
796 .SuperClasses: DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses, .SuperClassesSize: 8,
797 .OrderFunc: nullptr
798 };
799
800 extern const TargetRegisterClass DREGSLD8loRegClass = {
801 .MC: &AVRMCRegisterClasses[DREGSLD8loRegClassID],
802 .SubClassMask: DREGSLD8loSubClassMask,
803 .SuperRegIndices: SuperRegIdxSeqs + 2,
804 .LaneMask: LaneBitmask(0x0000000000000003),
805 .AllocationPriority: 0,
806 .GlobalPriority: false,
807 .TSFlags: 0x00, /* TSFlags */
808 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
809 .CoveredBySubRegs: true, /* CoveredBySubRegs */
810 .SuperClasses: DREGSLD8loSuperclasses, .SuperClassesSize: 13,
811 .OrderFunc: nullptr
812 };
813
814 extern const TargetRegisterClass IWREGSRegClass = {
815 .MC: &AVRMCRegisterClasses[IWREGSRegClassID],
816 .SubClassMask: IWREGSSubClassMask,
817 .SuperRegIndices: SuperRegIdxSeqs + 2,
818 .LaneMask: LaneBitmask(0x0000000000000003),
819 .AllocationPriority: 0,
820 .GlobalPriority: false,
821 .TSFlags: 0x00, /* TSFlags */
822 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
823 .CoveredBySubRegs: true, /* CoveredBySubRegs */
824 .SuperClasses: IWREGSSuperclasses, .SuperClassesSize: 5,
825 .OrderFunc: nullptr
826 };
827
828 extern const TargetRegisterClass DREGSNOZ_and_IWREGSRegClass = {
829 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_IWREGSRegClassID],
830 .SubClassMask: DREGSNOZ_and_IWREGSSubClassMask,
831 .SuperRegIndices: SuperRegIdxSeqs + 2,
832 .LaneMask: LaneBitmask(0x0000000000000003),
833 .AllocationPriority: 0,
834 .GlobalPriority: false,
835 .TSFlags: 0x00, /* TSFlags */
836 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
837 .CoveredBySubRegs: true, /* CoveredBySubRegs */
838 .SuperClasses: DREGSNOZ_and_IWREGSSuperclasses, .SuperClassesSize: 11,
839 .OrderFunc: nullptr
840 };
841
842 extern const TargetRegisterClass PTRREGSRegClass = {
843 .MC: &AVRMCRegisterClasses[PTRREGSRegClassID],
844 .SubClassMask: PTRREGSSubClassMask,
845 .SuperRegIndices: SuperRegIdxSeqs + 2,
846 .LaneMask: LaneBitmask(0x0000000000000003),
847 .AllocationPriority: 0,
848 .GlobalPriority: false,
849 .TSFlags: 0x00, /* TSFlags */
850 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
851 .CoveredBySubRegs: true, /* CoveredBySubRegs */
852 .SuperClasses: PTRREGSSuperclasses, .SuperClassesSize: 6,
853 .OrderFunc: nullptr
854 };
855
856 extern const TargetRegisterClass DREGSNOZ_and_PTRREGSRegClass = {
857 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_PTRREGSRegClassID],
858 .SubClassMask: DREGSNOZ_and_PTRREGSSubClassMask,
859 .SuperRegIndices: SuperRegIdxSeqs + 2,
860 .LaneMask: LaneBitmask(0x0000000000000003),
861 .AllocationPriority: 0,
862 .GlobalPriority: false,
863 .TSFlags: 0x00, /* TSFlags */
864 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
865 .CoveredBySubRegs: true, /* CoveredBySubRegs */
866 .SuperClasses: DREGSNOZ_and_PTRREGSSuperclasses, .SuperClassesSize: 13,
867 .OrderFunc: nullptr
868 };
869
870 extern const TargetRegisterClass PTRDISPREGSRegClass = {
871 .MC: &AVRMCRegisterClasses[PTRDISPREGSRegClassID],
872 .SubClassMask: PTRDISPREGSSubClassMask,
873 .SuperRegIndices: SuperRegIdxSeqs + 2,
874 .LaneMask: LaneBitmask(0x0000000000000003),
875 .AllocationPriority: 0,
876 .GlobalPriority: false,
877 .TSFlags: 0x00, /* TSFlags */
878 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
879 .CoveredBySubRegs: true, /* CoveredBySubRegs */
880 .SuperClasses: PTRDISPREGSSuperclasses, .SuperClassesSize: 7,
881 .OrderFunc: nullptr
882 };
883
884 extern const TargetRegisterClass DREGSNOZ_and_PTRDISPREGSRegClass = {
885 .MC: &AVRMCRegisterClasses[DREGSNOZ_and_PTRDISPREGSRegClassID],
886 .SubClassMask: DREGSNOZ_and_PTRDISPREGSSubClassMask,
887 .SuperRegIndices: SuperRegIdxSeqs + 2,
888 .LaneMask: LaneBitmask(0x0000000000000003),
889 .AllocationPriority: 0,
890 .GlobalPriority: false,
891 .TSFlags: 0x00, /* TSFlags */
892 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
893 .CoveredBySubRegs: true, /* CoveredBySubRegs */
894 .SuperClasses: DREGSNOZ_and_PTRDISPREGSSuperclasses, .SuperClassesSize: 15,
895 .OrderFunc: nullptr
896 };
897
898 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass = {
899 .MC: &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID],
900 .SubClassMask: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask,
901 .SuperRegIndices: SuperRegIdxSeqs + 2,
902 .LaneMask: LaneBitmask(0x0000000000000003),
903 .AllocationPriority: 0,
904 .GlobalPriority: false,
905 .TSFlags: 0x00, /* TSFlags */
906 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
907 .CoveredBySubRegs: true, /* CoveredBySubRegs */
908 .SuperClasses: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses, .SuperClassesSize: 6,
909 .OrderFunc: nullptr
910 };
911
912 extern const TargetRegisterClass GPRSPRegClass = {
913 .MC: &AVRMCRegisterClasses[GPRSPRegClassID],
914 .SubClassMask: GPRSPSubClassMask,
915 .SuperRegIndices: SuperRegIdxSeqs + 2,
916 .LaneMask: LaneBitmask(0x0000000000000003),
917 .AllocationPriority: 0,
918 .GlobalPriority: false,
919 .TSFlags: 0x00, /* TSFlags */
920 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
921 .CoveredBySubRegs: true, /* CoveredBySubRegs */
922 .SuperClasses: nullptr, .SuperClassesSize: 0,
923 .OrderFunc: nullptr
924 };
925
926 extern const TargetRegisterClass ZREGRegClass = {
927 .MC: &AVRMCRegisterClasses[ZREGRegClassID],
928 .SubClassMask: ZREGSubClassMask,
929 .SuperRegIndices: SuperRegIdxSeqs + 2,
930 .LaneMask: LaneBitmask(0x0000000000000003),
931 .AllocationPriority: 0,
932 .GlobalPriority: false,
933 .TSFlags: 0x00, /* TSFlags */
934 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
935 .CoveredBySubRegs: true, /* CoveredBySubRegs */
936 .SuperClasses: ZREGSuperclasses, .SuperClassesSize: 8,
937 .OrderFunc: nullptr
938 };
939
940
941} // namespace AVR
942namespace {
943
944 const TargetRegisterClass *const RegisterClasses[] = {
945 &AVR::GPR8RegClass,
946 &AVR::GPR8NOZRegClass,
947 &AVR::GPR8loRegClass,
948 &AVR::LD8RegClass,
949 &AVR::GPR8NOZ_and_LD8RegClass,
950 &AVR::LD8loRegClass,
951 &AVR::CCRRegClass,
952 &AVR::DREGSRegClass,
953 &AVR::DREGSNOZRegClass,
954 &AVR::DREGSMOVWRegClass,
955 &AVR::DREGSMOVW_and_DREGSNOZRegClass,
956 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
957 &AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClass,
958 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
959 &AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClass,
960 &AVR::DREGS_with_sub_lo_in_GPR8loRegClass,
961 &AVR::DREGS_with_sub_hi_in_GPR8loRegClass,
962 &AVR::DLDREGSRegClass,
963 &AVR::DREGS_with_sub_hi_in_LD8loRegClass,
964 &AVR::DREGS_with_sub_lo_in_LD8loRegClass,
965 &AVR::DREGSloRegClass,
966 &AVR::DLDREGS_and_DREGSNOZRegClass,
967 &AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass,
968 &AVR::DREGSLD8loRegClass,
969 &AVR::IWREGSRegClass,
970 &AVR::DREGSNOZ_and_IWREGSRegClass,
971 &AVR::PTRREGSRegClass,
972 &AVR::DREGSNOZ_and_PTRREGSRegClass,
973 &AVR::PTRDISPREGSRegClass,
974 &AVR::DREGSNOZ_and_PTRDISPREGSRegClass,
975 &AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass,
976 &AVR::GPRSPRegClass,
977 &AVR::ZREGRegClass,
978 };
979} // namespace
980
981static const uint8_t CostPerUseTable[] = {
9820, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
983
984
985static const bool InAllocatableClassTable[] = {
986false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
987
988
989static const TargetRegisterInfoDesc AVRRegInfoDesc = { // Extra Descriptors
990.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
991
992unsigned AVRGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
993 static const uint8_t Rows[1][2] = {
994 { 0, 0, },
995 };
996
997 --IdxA; assert(IdxA < 2); (void) IdxA;
998 --IdxB; assert(IdxB < 2);
999 return Rows[0][IdxB];
1000}
1001
1002unsigned AVRGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1003 static const uint8_t Table[2][2] = {
1004 { 0, 0, },
1005 { 0, 0, },
1006 };
1007
1008 --IdxA; assert(IdxA < 2);
1009 --IdxB; assert(IdxB < 2);
1010 return Table[IdxA][IdxB];
1011 }
1012
1013 struct MaskRolOp {
1014 LaneBitmask Mask;
1015 uint8_t RotateLeft;
1016 };
1017 static const MaskRolOp LaneMaskComposeSequences[] = {
1018 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
1019 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 2
1020 };
1021 static const uint8_t CompositeSequences[] = {
1022 0, // to sub_hi
1023 2 // to sub_lo
1024 };
1025
1026LaneBitmask AVRGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1027 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1028 LaneBitmask Result;
1029 for (const MaskRolOp *Ops =
1030 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1031 Ops->Mask.any(); ++Ops) {
1032 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1033 if (unsigned S = Ops->RotateLeft)
1034 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1035 else
1036 Result |= LaneBitmask(M);
1037 }
1038 return Result;
1039}
1040
1041LaneBitmask AVRGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1042 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
1043 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1044 LaneBitmask Result;
1045 for (const MaskRolOp *Ops =
1046 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1047 Ops->Mask.any(); ++Ops) {
1048 LaneBitmask::Type M = LaneMask.getAsInteger();
1049 if (unsigned S = Ops->RotateLeft)
1050 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1051 else
1052 Result |= LaneBitmask(M);
1053 }
1054 return Result;
1055}
1056
1057const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1058 static constexpr uint8_t Table[33][2] = {
1059 { // GPR8
1060 0, // sub_hi
1061 0, // sub_lo
1062 },
1063 { // GPR8NOZ
1064 0, // sub_hi
1065 0, // sub_lo
1066 },
1067 { // GPR8lo
1068 0, // sub_hi
1069 0, // sub_lo
1070 },
1071 { // LD8
1072 0, // sub_hi
1073 0, // sub_lo
1074 },
1075 { // GPR8NOZ_and_LD8
1076 0, // sub_hi
1077 0, // sub_lo
1078 },
1079 { // LD8lo
1080 0, // sub_hi
1081 0, // sub_lo
1082 },
1083 { // CCR
1084 0, // sub_hi
1085 0, // sub_lo
1086 },
1087 { // DREGS
1088 8, // sub_hi -> DREGS
1089 8, // sub_lo -> DREGS
1090 },
1091 { // DREGSNOZ
1092 9, // sub_hi -> DREGSNOZ
1093 9, // sub_lo -> DREGSNOZ
1094 },
1095 { // DREGSMOVW
1096 10, // sub_hi -> DREGSMOVW
1097 10, // sub_lo -> DREGSMOVW
1098 },
1099 { // DREGSMOVW_and_DREGSNOZ
1100 11, // sub_hi -> DREGSMOVW_and_DREGSNOZ
1101 11, // sub_lo -> DREGSMOVW_and_DREGSNOZ
1102 },
1103 { // DREGS_with_sub_hi_in_LD8
1104 12, // sub_hi -> DREGS_with_sub_hi_in_LD8
1105 12, // sub_lo -> DREGS_with_sub_hi_in_LD8
1106 },
1107 { // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1108 13, // sub_hi -> DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1109 13, // sub_lo -> DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1110 },
1111 { // DREGS_with_sub_lo_in_LD8
1112 14, // sub_hi -> DREGS_with_sub_lo_in_LD8
1113 14, // sub_lo -> DREGS_with_sub_lo_in_LD8
1114 },
1115 { // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1116 15, // sub_hi -> DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1117 15, // sub_lo -> DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1118 },
1119 { // DREGS_with_sub_lo_in_GPR8lo
1120 16, // sub_hi -> DREGS_with_sub_lo_in_GPR8lo
1121 16, // sub_lo -> DREGS_with_sub_lo_in_GPR8lo
1122 },
1123 { // DREGS_with_sub_hi_in_GPR8lo
1124 17, // sub_hi -> DREGS_with_sub_hi_in_GPR8lo
1125 17, // sub_lo -> DREGS_with_sub_hi_in_GPR8lo
1126 },
1127 { // DLDREGS
1128 18, // sub_hi -> DLDREGS
1129 18, // sub_lo -> DLDREGS
1130 },
1131 { // DREGS_with_sub_hi_in_LD8lo
1132 19, // sub_hi -> DREGS_with_sub_hi_in_LD8lo
1133 19, // sub_lo -> DREGS_with_sub_hi_in_LD8lo
1134 },
1135 { // DREGS_with_sub_lo_in_LD8lo
1136 20, // sub_hi -> DREGS_with_sub_lo_in_LD8lo
1137 20, // sub_lo -> DREGS_with_sub_lo_in_LD8lo
1138 },
1139 { // DREGSlo
1140 21, // sub_hi -> DREGSlo
1141 21, // sub_lo -> DREGSlo
1142 },
1143 { // DLDREGS_and_DREGSNOZ
1144 22, // sub_hi -> DLDREGS_and_DREGSNOZ
1145 22, // sub_lo -> DLDREGS_and_DREGSNOZ
1146 },
1147 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1148 23, // sub_hi -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1149 23, // sub_lo -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1150 },
1151 { // DREGSLD8lo
1152 24, // sub_hi -> DREGSLD8lo
1153 24, // sub_lo -> DREGSLD8lo
1154 },
1155 { // IWREGS
1156 25, // sub_hi -> IWREGS
1157 25, // sub_lo -> IWREGS
1158 },
1159 { // DREGSNOZ_and_IWREGS
1160 26, // sub_hi -> DREGSNOZ_and_IWREGS
1161 26, // sub_lo -> DREGSNOZ_and_IWREGS
1162 },
1163 { // PTRREGS
1164 27, // sub_hi -> PTRREGS
1165 27, // sub_lo -> PTRREGS
1166 },
1167 { // DREGSNOZ_and_PTRREGS
1168 28, // sub_hi -> DREGSNOZ_and_PTRREGS
1169 28, // sub_lo -> DREGSNOZ_and_PTRREGS
1170 },
1171 { // PTRDISPREGS
1172 29, // sub_hi -> PTRDISPREGS
1173 29, // sub_lo -> PTRDISPREGS
1174 },
1175 { // DREGSNOZ_and_PTRDISPREGS
1176 30, // sub_hi -> DREGSNOZ_and_PTRDISPREGS
1177 30, // sub_lo -> DREGSNOZ_and_PTRDISPREGS
1178 },
1179 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1180 31, // sub_hi -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1181 31, // sub_lo -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1182 },
1183 { // GPRSP
1184 32, // sub_hi -> GPRSP
1185 32, // sub_lo -> GPRSP
1186 },
1187 { // ZREG
1188 33, // sub_hi -> ZREG
1189 33, // sub_lo -> ZREG
1190 },
1191
1192 };
1193 assert(RC && "Missing regclass");
1194 if (!Idx) return RC;
1195 --Idx;
1196 assert(Idx < 2 && "Bad subreg");
1197 unsigned TV = Table[RC->getID()][Idx];
1198 return TV ? getRegClass(i: TV - 1) : nullptr;
1199}const TargetRegisterClass *AVRGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1200 static constexpr uint8_t Table[33][2] = {
1201 { // GPR8
1202 0, // GPR8:sub_hi
1203 0, // GPR8:sub_lo
1204 },
1205 { // GPR8NOZ
1206 0, // GPR8NOZ:sub_hi
1207 0, // GPR8NOZ:sub_lo
1208 },
1209 { // GPR8lo
1210 0, // GPR8lo:sub_hi
1211 0, // GPR8lo:sub_lo
1212 },
1213 { // LD8
1214 0, // LD8:sub_hi
1215 0, // LD8:sub_lo
1216 },
1217 { // GPR8NOZ_and_LD8
1218 0, // GPR8NOZ_and_LD8:sub_hi
1219 0, // GPR8NOZ_and_LD8:sub_lo
1220 },
1221 { // LD8lo
1222 0, // LD8lo:sub_hi
1223 0, // LD8lo:sub_lo
1224 },
1225 { // CCR
1226 0, // CCR:sub_hi
1227 0, // CCR:sub_lo
1228 },
1229 { // DREGS
1230 1, // DREGS:sub_hi -> GPR8
1231 1, // DREGS:sub_lo -> GPR8
1232 },
1233 { // DREGSNOZ
1234 2, // DREGSNOZ:sub_hi -> GPR8NOZ
1235 2, // DREGSNOZ:sub_lo -> GPR8NOZ
1236 },
1237 { // DREGSMOVW
1238 1, // DREGSMOVW:sub_hi -> GPR8
1239 1, // DREGSMOVW:sub_lo -> GPR8
1240 },
1241 { // DREGSMOVW_and_DREGSNOZ
1242 2, // DREGSMOVW_and_DREGSNOZ:sub_hi -> GPR8NOZ
1243 2, // DREGSMOVW_and_DREGSNOZ:sub_lo -> GPR8NOZ
1244 },
1245 { // DREGS_with_sub_hi_in_LD8
1246 4, // DREGS_with_sub_hi_in_LD8:sub_hi -> LD8
1247 1, // DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8
1248 },
1249 { // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1250 5, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8:sub_hi -> GPR8NOZ_and_LD8
1251 2, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8NOZ
1252 },
1253 { // DREGS_with_sub_lo_in_LD8
1254 4, // DREGS_with_sub_lo_in_LD8:sub_hi -> LD8
1255 4, // DREGS_with_sub_lo_in_LD8:sub_lo -> LD8
1256 },
1257 { // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1258 5, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8:sub_hi -> GPR8NOZ_and_LD8
1259 5, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8:sub_lo -> GPR8NOZ_and_LD8
1260 },
1261 { // DREGS_with_sub_lo_in_GPR8lo
1262 2, // DREGS_with_sub_lo_in_GPR8lo:sub_hi -> GPR8NOZ
1263 3, // DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1264 },
1265 { // DREGS_with_sub_hi_in_GPR8lo
1266 3, // DREGS_with_sub_hi_in_GPR8lo:sub_hi -> GPR8lo
1267 3, // DREGS_with_sub_hi_in_GPR8lo:sub_lo -> GPR8lo
1268 },
1269 { // DLDREGS
1270 4, // DLDREGS:sub_hi -> LD8
1271 4, // DLDREGS:sub_lo -> LD8
1272 },
1273 { // DREGS_with_sub_hi_in_LD8lo
1274 6, // DREGS_with_sub_hi_in_LD8lo:sub_hi -> LD8lo
1275 2, // DREGS_with_sub_hi_in_LD8lo:sub_lo -> GPR8NOZ
1276 },
1277 { // DREGS_with_sub_lo_in_LD8lo
1278 5, // DREGS_with_sub_lo_in_LD8lo:sub_hi -> GPR8NOZ_and_LD8
1279 6, // DREGS_with_sub_lo_in_LD8lo:sub_lo -> LD8lo
1280 },
1281 { // DREGSlo
1282 3, // DREGSlo:sub_hi -> GPR8lo
1283 3, // DREGSlo:sub_lo -> GPR8lo
1284 },
1285 { // DLDREGS_and_DREGSNOZ
1286 5, // DLDREGS_and_DREGSNOZ:sub_hi -> GPR8NOZ_and_LD8
1287 5, // DLDREGS_and_DREGSNOZ:sub_lo -> GPR8NOZ_and_LD8
1288 },
1289 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1290 6, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_hi -> LD8lo
1291 6, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_lo -> LD8lo
1292 },
1293 { // DREGSLD8lo
1294 6, // DREGSLD8lo:sub_hi -> LD8lo
1295 6, // DREGSLD8lo:sub_lo -> LD8lo
1296 },
1297 { // IWREGS
1298 4, // IWREGS:sub_hi -> LD8
1299 4, // IWREGS:sub_lo -> LD8
1300 },
1301 { // DREGSNOZ_and_IWREGS
1302 5, // DREGSNOZ_and_IWREGS:sub_hi -> GPR8NOZ_and_LD8
1303 5, // DREGSNOZ_and_IWREGS:sub_lo -> GPR8NOZ_and_LD8
1304 },
1305 { // PTRREGS
1306 4, // PTRREGS:sub_hi -> LD8
1307 4, // PTRREGS:sub_lo -> LD8
1308 },
1309 { // DREGSNOZ_and_PTRREGS
1310 5, // DREGSNOZ_and_PTRREGS:sub_hi -> GPR8NOZ_and_LD8
1311 5, // DREGSNOZ_and_PTRREGS:sub_lo -> GPR8NOZ_and_LD8
1312 },
1313 { // PTRDISPREGS
1314 4, // PTRDISPREGS:sub_hi -> LD8
1315 4, // PTRDISPREGS:sub_lo -> LD8
1316 },
1317 { // DREGSNOZ_and_PTRDISPREGS
1318 5, // DREGSNOZ_and_PTRDISPREGS:sub_hi -> GPR8NOZ_and_LD8
1319 5, // DREGSNOZ_and_PTRDISPREGS:sub_lo -> GPR8NOZ_and_LD8
1320 },
1321 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1322 6, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_hi -> LD8lo
1323 3, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1324 },
1325 { // GPRSP
1326 0, // GPRSP:sub_hi
1327 0, // GPRSP:sub_lo
1328 },
1329 { // ZREG
1330 4, // ZREG:sub_hi -> LD8
1331 4, // ZREG:sub_lo -> LD8
1332 },
1333
1334 };
1335 assert(RC && "Missing regclass");
1336 if (!Idx) return RC;
1337 --Idx;
1338 assert(Idx < 2 && "Bad subreg");
1339 unsigned TV = Table[RC->getID()][Idx];
1340 return TV ? getRegClass(i: TV - 1) : nullptr;
1341}/// Get the weight in units of pressure for this register class.
1342const RegClassWeight &AVRGenRegisterInfo::
1343getRegClassWeight(const TargetRegisterClass *RC) const {
1344 static const RegClassWeight RCWeightTable[] = {
1345 {.RegWeight: 1, .WeightLimit: 32}, // GPR8
1346 {.RegWeight: 1, .WeightLimit: 30}, // GPR8NOZ
1347 {.RegWeight: 1, .WeightLimit: 16}, // GPR8lo
1348 {.RegWeight: 1, .WeightLimit: 16}, // LD8
1349 {.RegWeight: 1, .WeightLimit: 14}, // GPR8NOZ_and_LD8
1350 {.RegWeight: 1, .WeightLimit: 8}, // LD8lo
1351 {.RegWeight: 1, .WeightLimit: 1}, // CCR
1352 {.RegWeight: 2, .WeightLimit: 32}, // DREGS
1353 {.RegWeight: 2, .WeightLimit: 30}, // DREGSNOZ
1354 {.RegWeight: 2, .WeightLimit: 32}, // DREGSMOVW
1355 {.RegWeight: 2, .WeightLimit: 30}, // DREGSMOVW_and_DREGSNOZ
1356 {.RegWeight: 2, .WeightLimit: 17}, // DREGS_with_sub_hi_in_LD8
1357 {.RegWeight: 2, .WeightLimit: 15}, // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8
1358 {.RegWeight: 2, .WeightLimit: 16}, // DREGS_with_sub_lo_in_LD8
1359 {.RegWeight: 2, .WeightLimit: 14}, // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8
1360 {.RegWeight: 2, .WeightLimit: 17}, // DREGS_with_sub_lo_in_GPR8lo
1361 {.RegWeight: 2, .WeightLimit: 16}, // DREGS_with_sub_hi_in_GPR8lo
1362 {.RegWeight: 2, .WeightLimit: 16}, // DLDREGS
1363 {.RegWeight: 2, .WeightLimit: 9}, // DREGS_with_sub_hi_in_LD8lo
1364 {.RegWeight: 2, .WeightLimit: 9}, // DREGS_with_sub_lo_in_LD8lo
1365 {.RegWeight: 2, .WeightLimit: 16}, // DREGSlo
1366 {.RegWeight: 2, .WeightLimit: 14}, // DLDREGS_and_DREGSNOZ
1367 {.RegWeight: 2, .WeightLimit: 8}, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1368 {.RegWeight: 2, .WeightLimit: 8}, // DREGSLD8lo
1369 {.RegWeight: 2, .WeightLimit: 8}, // IWREGS
1370 {.RegWeight: 2, .WeightLimit: 6}, // DREGSNOZ_and_IWREGS
1371 {.RegWeight: 2, .WeightLimit: 6}, // PTRREGS
1372 {.RegWeight: 2, .WeightLimit: 4}, // DREGSNOZ_and_PTRREGS
1373 {.RegWeight: 2, .WeightLimit: 4}, // PTRDISPREGS
1374 {.RegWeight: 2, .WeightLimit: 2}, // DREGSNOZ_and_PTRDISPREGS
1375 {.RegWeight: 2, .WeightLimit: 2}, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1376 {.RegWeight: 2, .WeightLimit: 2}, // GPRSP
1377 {.RegWeight: 2, .WeightLimit: 2}, // ZREG
1378 };
1379 return RCWeightTable[RC->getID()];
1380}
1381
1382/// Get the weight in units of pressure for this register unit.
1383unsigned AVRGenRegisterInfo::
1384getRegUnitWeight(MCRegUnit RegUnit) const {
1385 assert(static_cast<unsigned>(RegUnit) < 35 && "invalid register unit");
1386 // All register units have unit weight.
1387 return 1;
1388}
1389
1390
1391// Get the number of dimensions of register pressure.
1392unsigned AVRGenRegisterInfo::getNumRegPressureSets() const {
1393 return 9;
1394}
1395
1396// Get the name of this register unit pressure set.
1397const char *AVRGenRegisterInfo::
1398getRegPressureSetName(unsigned Idx) const {
1399 static const char *PressureNameTable[] = {
1400 "CCR",
1401 "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo",
1402 "GPRSP",
1403 "IWREGS",
1404 "LD8lo",
1405 "LD8",
1406 "GPR8lo",
1407 "GPR8lo_with_LD8lo",
1408 "GPR8",
1409 };
1410 return PressureNameTable[Idx];
1411}
1412
1413// Get the register unit pressure limit for this dimension.
1414// This limit must be adjusted dynamically for reserved registers.
1415unsigned AVRGenRegisterInfo::
1416getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1417 static const uint8_t PressureLimitTable[] = {
1418 1, // 0: CCR
1419 2, // 1: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1420 2, // 2: GPRSP
1421 8, // 3: IWREGS
1422 10, // 4: LD8lo
1423 17, // 5: LD8
1424 17, // 6: GPR8lo
1425 25, // 7: GPR8lo_with_LD8lo
1426 32, // 8: GPR8
1427 };
1428 return PressureLimitTable[Idx];
1429}
1430
1431/// Table of pressure sets per register class or unit.
1432static const int RCSetsTable[] = {
1433 /* 0 */ 0, -1,
1434 /* 2 */ 2, -1,
1435 /* 4 */ 3, 5, 8, -1,
1436 /* 8 */ 3, 4, 5, 7, 8, -1,
1437 /* 14 */ 1, 4, 5, 6, 7, 8, -1,
1438};
1439
1440/// Get the dimensions of register pressure impacted by this register class.
1441/// Returns a -1 terminated array of pressure set IDs
1442const int *AVRGenRegisterInfo::
1443getRegClassPressureSets(const TargetRegisterClass *RC) const {
1444 static const uint8_t RCSetStartTable[] = {
1445 6,6,17,5,5,9,0,6,6,6,6,5,5,5,5,17,17,5,9,9,17,5,9,9,4,4,4,4,4,4,14,2,4,};
1446 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1447}
1448
1449/// Get the dimensions of register pressure impacted by this register unit.
1450/// Returns a -1 terminated array of pressure set IDs
1451const int *AVRGenRegisterInfo::
1452getRegUnitPressureSets(MCRegUnit RegUnit) const {
1453 assert(static_cast<unsigned>(RegUnit) < 35 && "invalid register unit");
1454 static const uint8_t RUSetStartTable[] = {
1455 2,2,0,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,14,14,9,9,9,9,9,9,9,8,4,4,4,4,4,4,4,};
1456 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1457}
1458
1459extern const MCRegisterDesc AVRRegDesc[];
1460extern const int16_t AVRRegDiffLists[];
1461extern const LaneBitmask AVRLaneMaskLists[];
1462extern const char AVRRegStrings[];
1463extern const char AVRRegClassStrings[];
1464extern const MCPhysReg AVRRegUnitRoots[][2];
1465extern const uint16_t AVRSubRegIdxLists[];
1466extern const uint16_t AVRRegEncodingTable[];
1467// AVR Dwarf<->LLVM register mappings.
1468extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[];
1469extern const unsigned AVRDwarfFlavour0Dwarf2LSize;
1470
1471extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[];
1472extern const unsigned AVREHFlavour0Dwarf2LSize;
1473
1474extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[];
1475extern const unsigned AVRDwarfFlavour0L2DwarfSize;
1476
1477extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[];
1478extern const unsigned AVREHFlavour0L2DwarfSize;
1479
1480
1481AVRGenRegisterInfo::
1482AVRGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1483 unsigned PC, unsigned HwMode)
1484 : TargetRegisterInfo(&AVRRegInfoDesc, RegisterClasses, RegisterClasses+33,
1485 AVRSubRegIndexStrings, AVRSubRegIndexNameOffsets,
1486 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1487
1488 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
1489 InitMCRegisterInfo(D: AVRRegDesc, NR: 62, RA, PC,
1490 C: AVRMCRegisterClasses, NC: 33,
1491 RURoots: AVRRegUnitRoots,
1492 NRU: 35,
1493 DL: AVRRegDiffLists,
1494 RUMS: AVRLaneMaskLists,
1495 Strings: AVRRegStrings,
1496 ClassStrings: AVRRegClassStrings,
1497 SubIndices: AVRSubRegIdxLists,
1498 NumIndices: 3,
1499 RET: AVRRegEncodingTable,
1500 RUI: nullptr);
1501
1502 switch (DwarfFlavour) {
1503 default:
1504 llvm_unreachable("Unknown DWARF flavour");
1505 case 0:
1506 mapDwarfRegsToLLVMRegs(Map: AVRDwarfFlavour0Dwarf2L, Size: AVRDwarfFlavour0Dwarf2LSize, isEH: false);
1507 break;
1508 }
1509 switch (EHFlavour) {
1510 default:
1511 llvm_unreachable("Unknown DWARF flavour");
1512 case 0:
1513 mapDwarfRegsToLLVMRegs(Map: AVREHFlavour0Dwarf2L, Size: AVREHFlavour0Dwarf2LSize, isEH: true);
1514 break;
1515 }
1516 switch (DwarfFlavour) {
1517 default:
1518 llvm_unreachable("Unknown DWARF flavour");
1519 case 0:
1520 mapLLVMRegsToDwarfRegs(Map: AVRDwarfFlavour0L2Dwarf, Size: AVRDwarfFlavour0L2DwarfSize, isEH: false);
1521 break;
1522 }
1523 switch (EHFlavour) {
1524 default:
1525 llvm_unreachable("Unknown DWARF flavour");
1526 case 0:
1527 mapLLVMRegsToDwarfRegs(Map: AVREHFlavour0L2Dwarf, Size: AVREHFlavour0L2DwarfSize, isEH: true);
1528 break;
1529 }
1530}
1531
1532static const MCPhysReg CSR_Interrupts_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
1533static const uint32_t CSR_Interrupts_RegMask[] = { 0xffffff80, 0x3fffffdf, };
1534static const MCPhysReg CSR_InterruptsTiny_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, 0 };
1535static const uint32_t CSR_InterruptsTiny_RegMask[] = { 0xff800000, 0x3ff8001f, };
1536static const MCPhysReg CSR_Normal_SaveList[] = { AVR::R29, AVR::R28, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
1537static const uint32_t CSR_Normal_RegMask[] = { 0x007fff80, 0x1003ffc6, };
1538static const MCPhysReg CSR_NormalTiny_SaveList[] = { AVR::R29, AVR::R28, AVR::R19, AVR::R18, 0 };
1539static const uint32_t CSR_NormalTiny_RegMask[] = { 0x01800000, 0x10080006, };
1540
1541
1542ArrayRef<const uint32_t *> AVRGenRegisterInfo::getRegMasks() const {
1543 static const uint32_t *const Masks[] = {
1544 CSR_Interrupts_RegMask,
1545 CSR_InterruptsTiny_RegMask,
1546 CSR_Normal_RegMask,
1547 CSR_NormalTiny_RegMask,
1548 };
1549 return ArrayRef(Masks);
1550}
1551
1552bool AVRGenRegisterInfo::
1553isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1554 return
1555 false;
1556}
1557
1558bool AVRGenRegisterInfo::
1559isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1560 return
1561 false;
1562}
1563
1564bool AVRGenRegisterInfo::
1565isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1566 return
1567 false;
1568}
1569
1570bool AVRGenRegisterInfo::
1571isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1572 return
1573 false;
1574}
1575
1576bool AVRGenRegisterInfo::
1577isConstantPhysReg(MCRegister PhysReg) const {
1578 return
1579 false;
1580}
1581
1582ArrayRef<const char *> AVRGenRegisterInfo::getRegMaskNames() const {
1583 static const char *Names[] = {
1584 "CSR_Interrupts",
1585 "CSR_InterruptsTiny",
1586 "CSR_Normal",
1587 "CSR_NormalTiny",
1588 };
1589 return ArrayRef(Names);
1590}
1591
1592const AVRFrameLowering *
1593AVRGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1594 return static_cast<const AVRFrameLowering *>(
1595 MF.getSubtarget().getFrameLowering());
1596}
1597
1598
1599} // namespace llvm
1600