1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<1, 1, 1, 1, 1, 0> DirectXMCRegisterClassStorage;
12
13static const MVT::SimpleValueType DirectXVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16static constexpr char DirectXSubRegIndexStrings[] = {
17 /* dummy */ 0
18};
19
20
21static constexpr uint32_t DirectXSubRegIndexNameOffsets[] = {
22 /* dummy */ 0
23};
24
25static const TargetRegisterInfo::SubRegCoveredBits DirectXSubRegIdxRangeTable[] = {
26 { .Offset: 4294967295, .Size: 4294967295 },
27};
28
29
30static const LaneBitmask DirectXSubRegIndexLaneMaskTable[] = {
31 LaneBitmask::getAll(),
32 };
33
34
35
36static const TargetRegisterInfo::RegClassInfo DirectXRegClassInfos[] = {
37 // Mode = 0 (DefaultMode)
38 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*DirectXVTLists+*/.VTListOffset: 0 }, // DXILClass
39};
40
41static const uint8_t DirectXCostPerUseTable[] = {
420, 0, };
43
44
45static const bool DirectXInAllocatableClassTable[] = {
46false, true, };
47
48
49static const TargetRegisterInfoDesc DirectXRegInfoDesc = { // Extra Descriptors
50.CostPerUse: DirectXCostPerUseTable, .NumCosts: 1, .InAllocatableClass: DirectXInAllocatableClassTable};
51
52/// Get the weight in units of pressure for this register class.
53const RegClassWeight &DirectXGenRegisterInfo::
54getRegClassWeight(const TargetRegisterClass *RC) const {
55 static const RegClassWeight RCWeightTable[] = {
56 {.RegWeight: 1, .WeightLimit: 1}, // DXILClass
57 };
58 return RCWeightTable[RC->getID()];
59}
60
61/// Get the weight in units of pressure for this register unit.
62unsigned DirectXGenRegisterInfo::
63getRegUnitWeight(MCRegUnit RegUnit) const {
64 assert(static_cast<unsigned>(RegUnit) < 1 && "invalid register unit");
65 // All register units have unit weight.
66 return 1;
67}
68
69
70// Get the number of dimensions of register pressure.
71unsigned DirectXGenRegisterInfo::getNumRegPressureSets() const {
72 return 1;
73}
74
75// Get the name of this register unit pressure set.
76const char *DirectXGenRegisterInfo::
77getRegPressureSetName(unsigned Idx) const {
78 static const char *PressureNameTable[] = {
79 "DXILClass",
80 };
81 return PressureNameTable[Idx];
82}
83
84// Get the register unit pressure limit for this dimension.
85// This limit must be adjusted dynamically for reserved registers.
86unsigned DirectXGenRegisterInfo::
87getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
88 static const uint8_t PressureLimitTable[] = {
89 1, // 0: DXILClass
90 };
91 return PressureLimitTable[Idx];
92}
93
94/// Get the register class for this pressure set with the largest
95/// `RegClassWeight::WeightLimit`.
96const TargetRegisterClass *DirectXGenRegisterInfo::
97getLargestRegClassForRegPressureSet(unsigned Idx) const {
98 static const uint8_t PSetRegClassTable[] = {
99 dxil::DXILClassRegClassID, // 0: DXILClass
100 };
101 return getRegClass(i: PSetRegClassTable[Idx]);
102}
103
104/// Table of pressure sets per register class or unit.
105static const int RCSetsTable[] = {
106 /* 0 */ 0, -1,
107};
108
109/// Get the dimensions of register pressure impacted by this register class.
110/// Returns a -1 terminated array of pressure set IDs
111const int *DirectXGenRegisterInfo::
112getRegClassPressureSets(const TargetRegisterClass *RC) const {
113 static const uint8_t RCSetStartTable[] = {
114 0,};
115 return &RCSetsTable[RCSetStartTable[RC->getID()]];
116}
117
118/// Get the dimensions of register pressure impacted by this register unit.
119/// Returns a -1 terminated array of pressure set IDs
120const int *DirectXGenRegisterInfo::
121getRegUnitPressureSets(MCRegUnit RegUnit) const {
122 assert(static_cast<unsigned>(RegUnit) < 1 && "invalid register unit");
123 static const uint8_t RUSetStartTable[] = {
124 0,};
125 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
126}
127
128
129// Register to minimal register class mapping
130
131const TargetRegisterClass *DirectXGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
132 static const uint16_t InvalidRegClassID = UINT16_MAX;
133
134 static const uint16_t Mapping[2] = {
135 InvalidRegClassID, // NoRegister
136 dxil::DXILClassRegClassID, // DXIL
137 };
138
139 assert(Reg < ArrayRef(Mapping).size());
140 unsigned RCID = Mapping[Reg.id()];
141 if (RCID == InvalidRegClassID)
142 return nullptr;
143 return &DirectXMCRegisterClassStorage.Classes[RCID];
144}
145extern const MCRegisterDesc DirectXRegDesc[];
146extern const int16_t DirectXRegDiffLists[];
147extern const LaneBitmask DirectXLaneMaskLists[];
148extern const char DirectXRegStrings[];
149extern const char DirectXRegClassStrings[];
150extern const MCPhysReg DirectXRegUnitRoots[][2];
151extern const uint16_t DirectXSubRegIdxLists[];
152extern const uint16_t DirectXRegEncodingTable[];
153
154DirectXGenRegisterInfo::
155DirectXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
156 unsigned PC, unsigned HwMode)
157 : TargetRegisterInfo(&DirectXRegInfoDesc,
158 DirectXSubRegIndexStrings, DirectXSubRegIndexNameOffsets,
159 DirectXSubRegIdxRangeTable, DirectXSubRegIndexLaneMaskTable,
160
161 LaneBitmask(0xFFFFFFFFFFFFFFFF), DirectXRegClassInfos, DirectXVTLists, HwMode) {
162 InitMCRegisterInfo(D: DirectXRegDesc, NR: 2, RA, PC,
163 C: &getDirectXMCRegisterClass(RC: 0), NC: 1, RURoots: DirectXRegUnitRoots, NRU: 1, DL: DirectXRegDiffLists,
164 RUMS: DirectXLaneMaskLists, Strings: DirectXRegStrings, ClassStrings: DirectXRegClassStrings, SubIndices: DirectXSubRegIdxLists, NumIndices: 1,
165 RET: DirectXRegEncodingTable, RUI: nullptr);
166
167}
168
169
170
171ArrayRef<const uint32_t *> DirectXGenRegisterInfo::getRegMasks() const {
172 return {};
173}
174
175bool DirectXGenRegisterInfo::
176isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
177 return
178 false;
179}
180
181bool DirectXGenRegisterInfo::
182isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
183 return
184 false;
185}
186
187bool DirectXGenRegisterInfo::
188isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
189 return
190 false;
191}
192
193bool DirectXGenRegisterInfo::
194isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
195 return
196 false;
197}
198
199bool DirectXGenRegisterInfo::
200isConstantPhysReg(MCRegister PhysReg) const {
201 return
202 false;
203}
204
205ArrayRef<const char *> DirectXGenRegisterInfo::getRegMaskNames() const {
206 return {};
207}
208
209const DirectXFrameLowering *
210DirectXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
211 return static_cast<const DirectXFrameLowering *>(
212 MF.getSubtarget().getFrameLowering());
213}
214
215
216} // namespace llvm
217