| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* MC Register Information *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | namespace llvm { |
| 10 | |
| 11 | extern const int16_t HexagonRegDiffLists[] = { |
| 12 | /* 0 */ 21, -304, 0, |
| 13 | /* 3 */ -209, -158, 0, |
| 14 | /* 6 */ -211, -111, 0, |
| 15 | /* 9 */ -140, -92, 0, |
| 16 | /* 12 */ -77, 0, |
| 17 | /* 14 */ -76, 0, |
| 18 | /* 16 */ -75, 0, |
| 19 | /* 18 */ -74, 0, |
| 20 | /* 20 */ -73, 0, |
| 21 | /* 22 */ -72, 0, |
| 22 | /* 24 */ -71, 0, |
| 23 | /* 26 */ -70, 0, |
| 24 | /* 28 */ -69, 0, |
| 25 | /* 30 */ -68, 0, |
| 26 | /* 32 */ -67, 0, |
| 27 | /* 34 */ -66, 0, |
| 28 | /* 36 */ -65, 0, |
| 29 | /* 38 */ -64, 0, |
| 30 | /* 40 */ -63, 0, |
| 31 | /* 42 */ -62, 0, |
| 32 | /* 44 */ -61, 0, |
| 33 | /* 46 */ -52, 0, |
| 34 | /* 48 */ -51, 0, |
| 35 | /* 50 */ -327, -31, 0, |
| 36 | /* 53 */ -284, -30, 0, |
| 37 | /* 56 */ -324, -28, 0, |
| 38 | /* 59 */ -303, -24, 0, |
| 39 | /* 62 */ -21, 0, |
| 40 | /* 64 */ -345, -15, 0, |
| 41 | /* 67 */ -324, -2, 0, |
| 42 | /* 70 */ -352, -1, 0, |
| 43 | /* 73 */ -346, -1, 0, |
| 44 | /* 76 */ -339, -1, 0, |
| 45 | /* 79 */ -331, -1, 0, |
| 46 | /* 82 */ -205, -1, 0, |
| 47 | /* 85 */ -204, -1, 0, |
| 48 | /* 88 */ 2, -1, 0, |
| 49 | /* 91 */ -360, 1, 0, |
| 50 | /* 94 */ -357, 1, 0, |
| 51 | /* 97 */ -312, 1, 0, |
| 52 | /* 100 */ -271, 1, 0, |
| 53 | /* 103 */ -270, 1, 0, |
| 54 | /* 106 */ -269, 1, 0, |
| 55 | /* 109 */ -268, 1, 0, |
| 56 | /* 112 */ -267, 1, 0, |
| 57 | /* 115 */ -266, 1, 0, |
| 58 | /* 118 */ -265, 1, 0, |
| 59 | /* 121 */ -264, 1, 0, |
| 60 | /* 124 */ -262, 1, 0, |
| 61 | /* 127 */ -261, 1, 0, |
| 62 | /* 130 */ -253, 1, 0, |
| 63 | /* 133 */ -252, 1, 0, |
| 64 | /* 136 */ -233, 1, 0, |
| 65 | /* 139 */ -217, 1, 0, |
| 66 | /* 142 */ -216, 1, 0, |
| 67 | /* 145 */ -215, 1, 0, |
| 68 | /* 148 */ -214, 1, 0, |
| 69 | /* 151 */ -213, 1, 0, |
| 70 | /* 154 */ -212, 1, 0, |
| 71 | /* 157 */ -211, 1, 0, |
| 72 | /* 160 */ -210, 1, 0, |
| 73 | /* 163 */ -209, 1, 0, |
| 74 | /* 166 */ -208, 1, 0, |
| 75 | /* 169 */ -207, 1, 0, |
| 76 | /* 172 */ -201, 1, 0, |
| 77 | /* 175 */ -104, 1, 0, |
| 78 | /* 178 */ 8, -104, 1, 104, -103, 1, 0, |
| 79 | /* 185 */ -102, 1, 0, |
| 80 | /* 188 */ 9, -102, 1, 102, -101, 1, 0, |
| 81 | /* 195 */ -100, 1, 0, |
| 82 | /* 198 */ 10, -100, 1, 100, -99, 1, 0, |
| 83 | /* 205 */ -98, 1, 0, |
| 84 | /* 208 */ 11, -98, 1, 98, -97, 1, 0, |
| 85 | /* 215 */ -96, 1, 0, |
| 86 | /* 218 */ 12, -96, 1, 96, -95, 1, 0, |
| 87 | /* 225 */ -94, 1, 0, |
| 88 | /* 228 */ 13, -94, 1, 94, -93, 1, 0, |
| 89 | /* 235 */ -92, 1, 0, |
| 90 | /* 238 */ 14, -92, 1, 92, -91, 1, 0, |
| 91 | /* 245 */ -90, 1, 0, |
| 92 | /* 248 */ 15, -90, 1, 90, -89, 1, 0, |
| 93 | /* 255 */ 1, 1, 1, 0, |
| 94 | /* 259 */ 51, 1, 0, |
| 95 | /* 262 */ 61, 1, 0, |
| 96 | /* 265 */ 62, 1, 0, |
| 97 | /* 268 */ 63, 1, 0, |
| 98 | /* 271 */ 64, 1, 0, |
| 99 | /* 274 */ 65, 1, 0, |
| 100 | /* 277 */ 66, 1, 0, |
| 101 | /* 280 */ 67, 1, 0, |
| 102 | /* 283 */ 68, 1, 0, |
| 103 | /* 286 */ 69, 1, 0, |
| 104 | /* 289 */ 70, 1, 0, |
| 105 | /* 292 */ 71, 1, 0, |
| 106 | /* 295 */ 72, 1, 0, |
| 107 | /* 298 */ 73, 1, 0, |
| 108 | /* 301 */ 74, 1, 0, |
| 109 | /* 304 */ 75, 1, 0, |
| 110 | /* 307 */ 76, 1, 0, |
| 111 | /* 310 */ 2, 0, |
| 112 | /* 312 */ -331, 5, 0, |
| 113 | /* 315 */ 15, 12, 0, |
| 114 | /* 318 */ -358, 16, 0, |
| 115 | /* 321 */ 23, 0, |
| 116 | /* 323 */ 103, -8, 24, 0, |
| 117 | /* 327 */ 104, -8, 24, 0, |
| 118 | /* 331 */ 101, -9, 25, 0, |
| 119 | /* 335 */ 102, -9, 25, 0, |
| 120 | /* 339 */ 103, -9, 25, 0, |
| 121 | /* 343 */ 99, -10, 26, 0, |
| 122 | /* 347 */ 100, -10, 26, 0, |
| 123 | /* 351 */ 101, -10, 26, 0, |
| 124 | /* 355 */ -366, 27, 0, |
| 125 | /* 358 */ 97, -11, 27, 0, |
| 126 | /* 362 */ 98, -11, 27, 0, |
| 127 | /* 366 */ 99, -11, 27, 0, |
| 128 | /* 370 */ 95, -12, 28, 0, |
| 129 | /* 374 */ 96, -12, 28, 0, |
| 130 | /* 378 */ 97, -12, 28, 0, |
| 131 | /* 382 */ 93, -13, 29, 0, |
| 132 | /* 386 */ 94, -13, 29, 0, |
| 133 | /* 390 */ 95, -13, 29, 0, |
| 134 | /* 394 */ 91, -14, 30, 0, |
| 135 | /* 398 */ 92, -14, 30, 0, |
| 136 | /* 402 */ 93, -14, 30, 0, |
| 137 | /* 406 */ 89, -15, 31, 0, |
| 138 | /* 410 */ 90, -15, 31, 0, |
| 139 | /* 414 */ 91, -15, 31, 0, |
| 140 | /* 418 */ 88, -16, 32, 0, |
| 141 | /* 422 */ 89, -16, 32, 0, |
| 142 | /* 426 */ 33, 0, |
| 143 | /* 428 */ -105, 1, 48, 40, 0, |
| 144 | /* 433 */ -106, 1, 49, 40, 0, |
| 145 | /* 438 */ -107, 1, 50, 40, 0, |
| 146 | /* 443 */ -108, 1, 51, 40, 0, |
| 147 | /* 448 */ -109, 1, 52, 40, 0, |
| 148 | /* 453 */ -110, 1, 53, 40, 0, |
| 149 | /* 458 */ -111, 1, 54, 40, 0, |
| 150 | /* 463 */ -112, 1, 55, 40, 0, |
| 151 | /* 468 */ -113, 1, 56, 40, 0, |
| 152 | /* 473 */ -114, 1, 57, 40, 0, |
| 153 | /* 478 */ -115, 1, 58, 40, 0, |
| 154 | /* 483 */ -116, 1, 59, 40, 0, |
| 155 | /* 488 */ -117, 1, 60, 40, 0, |
| 156 | /* 493 */ -118, 1, 61, 40, 0, |
| 157 | /* 498 */ -119, 1, 62, 40, 0, |
| 158 | /* 503 */ -120, 1, 63, 40, 0, |
| 159 | /* 508 */ 1, 48, 0, |
| 160 | /* 511 */ 1, 49, 0, |
| 161 | /* 514 */ 1, 50, 0, |
| 162 | /* 517 */ 1, 51, 0, |
| 163 | /* 520 */ 1, 52, 0, |
| 164 | /* 523 */ 1, 53, 0, |
| 165 | /* 526 */ 1, 54, 0, |
| 166 | /* 529 */ 1, 55, 0, |
| 167 | /* 532 */ 1, 56, 0, |
| 168 | /* 535 */ 1, 57, 0, |
| 169 | /* 538 */ 1, 58, 0, |
| 170 | /* 541 */ 1, 59, 0, |
| 171 | /* 544 */ 1, 60, 0, |
| 172 | /* 547 */ -273, 61, 0, |
| 173 | /* 550 */ 1, 61, 0, |
| 174 | /* 553 */ -331, 62, 0, |
| 175 | /* 556 */ 1, 62, 0, |
| 176 | /* 559 */ 1, 63, 0, |
| 177 | /* 562 */ 64, 0, |
| 178 | /* 564 */ 73, 0, |
| 179 | /* 566 */ -351, 78, 0, |
| 180 | /* 569 */ 89, 0, |
| 181 | /* 571 */ 97, 0, |
| 182 | /* 573 */ 104, 0, |
| 183 | /* 575 */ 116, 0, |
| 184 | /* 577 */ -331, 120, 0, |
| 185 | /* 580 */ -345, 133, 0, |
| 186 | /* 583 */ 140, 0, |
| 187 | /* 585 */ 142, 0, |
| 188 | /* 587 */ 68, 2, 2, 2, 153, 0, |
| 189 | /* 593 */ 200, 0, |
| 190 | /* 595 */ 201, 0, |
| 191 | /* 597 */ 204, 0, |
| 192 | /* 599 */ 205, 0, |
| 193 | /* 601 */ 206, 0, |
| 194 | /* 603 */ 207, 0, |
| 195 | /* 605 */ 208, 0, |
| 196 | /* 607 */ 209, 0, |
| 197 | /* 609 */ 210, 0, |
| 198 | /* 611 */ 211, 0, |
| 199 | /* 613 */ 212, 0, |
| 200 | /* 615 */ 213, 0, |
| 201 | /* 617 */ 214, 0, |
| 202 | /* 619 */ 215, 0, |
| 203 | /* 621 */ 216, 0, |
| 204 | /* 623 */ 217, 0, |
| 205 | /* 625 */ 232, 0, |
| 206 | /* 627 */ 233, 0, |
| 207 | /* 629 */ 251, 0, |
| 208 | /* 631 */ 252, 0, |
| 209 | /* 633 */ 253, 0, |
| 210 | /* 635 */ 260, 0, |
| 211 | /* 637 */ 261, 0, |
| 212 | /* 639 */ 262, 0, |
| 213 | /* 641 */ 263, 0, |
| 214 | /* 643 */ 264, 0, |
| 215 | /* 645 */ 265, 0, |
| 216 | /* 647 */ 266, 0, |
| 217 | /* 649 */ 267, 0, |
| 218 | /* 651 */ 268, 0, |
| 219 | /* 653 */ 269, 0, |
| 220 | /* 655 */ 270, 0, |
| 221 | /* 657 */ 271, 0, |
| 222 | /* 659 */ 273, 0, |
| 223 | /* 661 */ 283, 0, |
| 224 | /* 663 */ 284, 0, |
| 225 | /* 665 */ 303, 0, |
| 226 | /* 667 */ 311, 0, |
| 227 | /* 669 */ 312, 0, |
| 228 | /* 671 */ 314, 0, |
| 229 | /* 673 */ 322, 0, |
| 230 | /* 675 */ 324, 0, |
| 231 | /* 677 */ 326, 0, |
| 232 | /* 679 */ 327, 0, |
| 233 | /* 681 */ 331, 0, |
| 234 | /* 683 */ 332, 0, |
| 235 | /* 685 */ 339, 0, |
| 236 | /* 687 */ 340, 0, |
| 237 | /* 689 */ 342, 0, |
| 238 | /* 691 */ 345, 0, |
| 239 | /* 693 */ 346, 0, |
| 240 | /* 695 */ 347, 0, |
| 241 | /* 697 */ 351, 0, |
| 242 | /* 699 */ 352, 0, |
| 243 | /* 701 */ 353, 0, |
| 244 | /* 703 */ 356, 0, |
| 245 | /* 705 */ 357, 0, |
| 246 | /* 707 */ 358, 0, |
| 247 | /* 709 */ 359, 0, |
| 248 | /* 711 */ 360, 0, |
| 249 | /* 713 */ 366, 0, |
| 250 | /* 715 */ 367, 0, |
| 251 | }; |
| 252 | |
| 253 | extern const LaneBitmask HexagonLaneMaskLists[] = { |
| 254 | /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), |
| 255 | /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), |
| 256 | /* 4 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), |
| 257 | /* 7 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), |
| 258 | /* 13 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000008), |
| 259 | /* 16 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), |
| 260 | /* 18 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000040), |
| 261 | /* 22 */ LaneBitmask(0x0000000000000004), LaneBitmask(0xFFFFFFFFFFFFFFFF), |
| 262 | /* 24 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), |
| 263 | }; |
| 264 | |
| 265 | extern const uint16_t HexagonSubRegIdxLists[] = { |
| 266 | /* 0 */ 2, 1, |
| 267 | /* 2 */ 3, |
| 268 | /* 3 */ 6, 5, |
| 269 | /* 5 */ 6, 5, 4, 8, |
| 270 | /* 9 */ 8, 6, 5, 7, 10, 9, |
| 271 | }; |
| 272 | |
| 273 | |
| 274 | #ifdef __GNUC__ |
| 275 | #pragma GCC diagnostic push |
| 276 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 277 | #endif |
| 278 | extern const char HexagonRegStrings[] = { |
| 279 | /* 0 */ "D10\000" |
| 280 | /* 4 */ "VF10\000" |
| 281 | /* 9 */ "G10\000" |
| 282 | /* 13 */ "VFR10\000" |
| 283 | /* 19 */ "WR10\000" |
| 284 | /* 24 */ "V10\000" |
| 285 | /* 28 */ "W10\000" |
| 286 | /* 32 */ "C11_10\000" |
| 287 | /* 39 */ "G11_10\000" |
| 288 | /* 46 */ "S11_10\000" |
| 289 | /* 53 */ "VF20\000" |
| 290 | /* 58 */ "G20\000" |
| 291 | /* 62 */ "VFR20\000" |
| 292 | /* 68 */ "S20\000" |
| 293 | /* 72 */ "V20\000" |
| 294 | /* 76 */ "G21_20\000" |
| 295 | /* 83 */ "S21_20\000" |
| 296 | /* 90 */ "VF30\000" |
| 297 | /* 95 */ "G30\000" |
| 298 | /* 99 */ "VFR30\000" |
| 299 | /* 105 */ "V30\000" |
| 300 | /* 109 */ "G31_30\000" |
| 301 | /* 116 */ "S31_30\000" |
| 302 | /* 123 */ "S41_40\000" |
| 303 | /* 130 */ "S51_50\000" |
| 304 | /* 137 */ "S60\000" |
| 305 | /* 141 */ "S61_60\000" |
| 306 | /* 148 */ "S70\000" |
| 307 | /* 152 */ "S71_70\000" |
| 308 | /* 159 */ "S80\000" |
| 309 | /* 163 */ "SA0\000" |
| 310 | /* 167 */ "BADVA0\000" |
| 311 | /* 174 */ "LC0\000" |
| 312 | /* 178 */ "BRKPTPC0\000" |
| 313 | /* 187 */ "D0\000" |
| 314 | /* 190 */ "VF0\000" |
| 315 | /* 194 */ "ISDBCFG0\000" |
| 316 | /* 203 */ "BRKPTCFG0\000" |
| 317 | /* 213 */ "M0\000" |
| 318 | /* 216 */ "SGP0\000" |
| 319 | /* 221 */ "VQ0\000" |
| 320 | /* 225 */ "VFR0\000" |
| 321 | /* 230 */ "WR0\000" |
| 322 | /* 234 */ "CS0\000" |
| 323 | /* 238 */ "GPMUCNT0\000" |
| 324 | /* 247 */ "V0\000" |
| 325 | /* 250 */ "W0\000" |
| 326 | /* 253 */ "C1_0\000" |
| 327 | /* 258 */ "G1_0\000" |
| 328 | /* 263 */ "SGP1_0\000" |
| 329 | /* 270 */ "P3_0\000" |
| 330 | /* 275 */ "D11\000" |
| 331 | /* 279 */ "VF11\000" |
| 332 | /* 284 */ "G11\000" |
| 333 | /* 288 */ "VFR11\000" |
| 334 | /* 294 */ "WR11\000" |
| 335 | /* 299 */ "S11\000" |
| 336 | /* 303 */ "V11\000" |
| 337 | /* 307 */ "W11\000" |
| 338 | /* 311 */ "VF21\000" |
| 339 | /* 316 */ "G21\000" |
| 340 | /* 320 */ "VFR21\000" |
| 341 | /* 326 */ "V21\000" |
| 342 | /* 330 */ "VF31\000" |
| 343 | /* 335 */ "G31\000" |
| 344 | /* 339 */ "VFR31\000" |
| 345 | /* 345 */ "V31\000" |
| 346 | /* 349 */ "S61\000" |
| 347 | /* 353 */ "S71\000" |
| 348 | /* 357 */ "SA1\000" |
| 349 | /* 361 */ "BADVA1\000" |
| 350 | /* 368 */ "LC1\000" |
| 351 | /* 372 */ "BRKPTPC1\000" |
| 352 | /* 381 */ "D1\000" |
| 353 | /* 384 */ "VF1\000" |
| 354 | /* 388 */ "ISDBCFG1\000" |
| 355 | /* 397 */ "BRKPTCFG1\000" |
| 356 | /* 407 */ "M1\000" |
| 357 | /* 410 */ "SGP1\000" |
| 358 | /* 415 */ "VQ1\000" |
| 359 | /* 419 */ "VFR1\000" |
| 360 | /* 424 */ "WR1\000" |
| 361 | /* 428 */ "CS1\000" |
| 362 | /* 432 */ "GPMUCNT1\000" |
| 363 | /* 441 */ "V1\000" |
| 364 | /* 444 */ "W1\000" |
| 365 | /* 447 */ "D12\000" |
| 366 | /* 451 */ "VF12\000" |
| 367 | /* 456 */ "G12\000" |
| 368 | /* 460 */ "VFR12\000" |
| 369 | /* 466 */ "WR12\000" |
| 370 | /* 471 */ "S12\000" |
| 371 | /* 475 */ "V12\000" |
| 372 | /* 479 */ "W12\000" |
| 373 | /* 483 */ "G13_12\000" |
| 374 | /* 490 */ "S13_12\000" |
| 375 | /* 497 */ "VF22\000" |
| 376 | /* 502 */ "G22\000" |
| 377 | /* 506 */ "VFR22\000" |
| 378 | /* 512 */ "S22\000" |
| 379 | /* 516 */ "V22\000" |
| 380 | /* 520 */ "G23_22\000" |
| 381 | /* 527 */ "S23_22\000" |
| 382 | /* 534 */ "S33_32\000" |
| 383 | /* 541 */ "S43_42\000" |
| 384 | /* 548 */ "S53_52\000" |
| 385 | /* 555 */ "S62\000" |
| 386 | /* 559 */ "S63_62\000" |
| 387 | /* 566 */ "S72\000" |
| 388 | /* 570 */ "S73_72\000" |
| 389 | /* 577 */ "D2\000" |
| 390 | /* 580 */ "VF2\000" |
| 391 | /* 584 */ "P2\000" |
| 392 | /* 587 */ "VQ2\000" |
| 393 | /* 591 */ "VFR2\000" |
| 394 | /* 596 */ "WR2\000" |
| 395 | /* 600 */ "GPMUCNT2\000" |
| 396 | /* 609 */ "V2\000" |
| 397 | /* 612 */ "W2\000" |
| 398 | /* 615 */ "C3_2\000" |
| 399 | /* 620 */ "G3_2\000" |
| 400 | /* 625 */ "S3_2\000" |
| 401 | /* 630 */ "D13\000" |
| 402 | /* 634 */ "VF13\000" |
| 403 | /* 639 */ "G13\000" |
| 404 | /* 643 */ "VFR13\000" |
| 405 | /* 649 */ "WR13\000" |
| 406 | /* 654 */ "S13\000" |
| 407 | /* 658 */ "V13\000" |
| 408 | /* 662 */ "W13\000" |
| 409 | /* 666 */ "VF23\000" |
| 410 | /* 671 */ "G23\000" |
| 411 | /* 675 */ "VFR23\000" |
| 412 | /* 681 */ "S23\000" |
| 413 | /* 685 */ "V23\000" |
| 414 | /* 689 */ "S63\000" |
| 415 | /* 693 */ "S73\000" |
| 416 | /* 697 */ "D3\000" |
| 417 | /* 700 */ "VF3\000" |
| 418 | /* 704 */ "G3\000" |
| 419 | /* 707 */ "P3\000" |
| 420 | /* 710 */ "VQ3\000" |
| 421 | /* 714 */ "VFR3\000" |
| 422 | /* 719 */ "WR3\000" |
| 423 | /* 723 */ "GPMUCNT3\000" |
| 424 | /* 732 */ "V3\000" |
| 425 | /* 735 */ "W3\000" |
| 426 | /* 738 */ "D14\000" |
| 427 | /* 742 */ "VF14\000" |
| 428 | /* 747 */ "G14\000" |
| 429 | /* 751 */ "VFR14\000" |
| 430 | /* 757 */ "WR14\000" |
| 431 | /* 762 */ "S14\000" |
| 432 | /* 766 */ "V14\000" |
| 433 | /* 770 */ "W14\000" |
| 434 | /* 774 */ "G15_14\000" |
| 435 | /* 781 */ "S15_14\000" |
| 436 | /* 788 */ "VF24\000" |
| 437 | /* 793 */ "VFR24\000" |
| 438 | /* 799 */ "S24\000" |
| 439 | /* 803 */ "V24\000" |
| 440 | /* 807 */ "G25_24\000" |
| 441 | /* 814 */ "S25_24\000" |
| 442 | /* 821 */ "S35_34\000" |
| 443 | /* 828 */ "S44\000" |
| 444 | /* 832 */ "S45_44\000" |
| 445 | /* 839 */ "S54\000" |
| 446 | /* 843 */ "S55_54\000" |
| 447 | /* 850 */ "S64\000" |
| 448 | /* 854 */ "S65_64\000" |
| 449 | /* 861 */ "S74\000" |
| 450 | /* 865 */ "S75_74\000" |
| 451 | /* 872 */ "D4\000" |
| 452 | /* 875 */ "VF4\000" |
| 453 | /* 879 */ "G4\000" |
| 454 | /* 882 */ "VQ4\000" |
| 455 | /* 886 */ "VFR4\000" |
| 456 | /* 891 */ "WR4\000" |
| 457 | /* 895 */ "GPMUCNT4\000" |
| 458 | /* 904 */ "V4\000" |
| 459 | /* 907 */ "W4\000" |
| 460 | /* 910 */ "C5_4\000" |
| 461 | /* 915 */ "G5_4\000" |
| 462 | /* 920 */ "S5_4\000" |
| 463 | /* 925 */ "D15\000" |
| 464 | /* 929 */ "VF15\000" |
| 465 | /* 934 */ "G15\000" |
| 466 | /* 938 */ "VFR15\000" |
| 467 | /* 944 */ "WR15\000" |
| 468 | /* 949 */ "S15\000" |
| 469 | /* 953 */ "V15\000" |
| 470 | /* 957 */ "W15\000" |
| 471 | /* 961 */ "VF25\000" |
| 472 | /* 966 */ "VFR25\000" |
| 473 | /* 972 */ "S25\000" |
| 474 | /* 976 */ "V25\000" |
| 475 | /* 980 */ "S35\000" |
| 476 | /* 984 */ "S45\000" |
| 477 | /* 988 */ "S55\000" |
| 478 | /* 992 */ "S65\000" |
| 479 | /* 996 */ "S75\000" |
| 480 | /* 1000 */ "C5\000" |
| 481 | /* 1003 */ "D5\000" |
| 482 | /* 1006 */ "VF5\000" |
| 483 | /* 1010 */ "G5\000" |
| 484 | /* 1013 */ "VQ5\000" |
| 485 | /* 1017 */ "VFR5\000" |
| 486 | /* 1022 */ "WR5\000" |
| 487 | /* 1026 */ "GPMUCNT5\000" |
| 488 | /* 1035 */ "V5\000" |
| 489 | /* 1038 */ "W5\000" |
| 490 | /* 1041 */ "VF16\000" |
| 491 | /* 1046 */ "VFR16\000" |
| 492 | /* 1052 */ "V16\000" |
| 493 | /* 1056 */ "C17_16\000" |
| 494 | /* 1063 */ "G17_16\000" |
| 495 | /* 1070 */ "S17_16\000" |
| 496 | /* 1077 */ "VF26\000" |
| 497 | /* 1082 */ "VFR26\000" |
| 498 | /* 1088 */ "S26\000" |
| 499 | /* 1092 */ "V26\000" |
| 500 | /* 1096 */ "G27_26\000" |
| 501 | /* 1103 */ "S27_26\000" |
| 502 | /* 1110 */ "S37_36\000" |
| 503 | /* 1117 */ "S46\000" |
| 504 | /* 1121 */ "S47_46\000" |
| 505 | /* 1128 */ "S56\000" |
| 506 | /* 1132 */ "S57_56\000" |
| 507 | /* 1139 */ "S66\000" |
| 508 | /* 1143 */ "S67_66\000" |
| 509 | /* 1150 */ "S76\000" |
| 510 | /* 1154 */ "S77_76\000" |
| 511 | /* 1161 */ "D6\000" |
| 512 | /* 1164 */ "VF6\000" |
| 513 | /* 1168 */ "G6\000" |
| 514 | /* 1171 */ "VQ6\000" |
| 515 | /* 1175 */ "VFR6\000" |
| 516 | /* 1180 */ "WR6\000" |
| 517 | /* 1184 */ "GPMUCNT6\000" |
| 518 | /* 1193 */ "V6\000" |
| 519 | /* 1196 */ "W6\000" |
| 520 | /* 1199 */ "C7_6\000" |
| 521 | /* 1204 */ "G7_6\000" |
| 522 | /* 1209 */ "S7_6\000" |
| 523 | /* 1214 */ "VF17\000" |
| 524 | /* 1219 */ "VFR17\000" |
| 525 | /* 1225 */ "V17\000" |
| 526 | /* 1229 */ "VF27\000" |
| 527 | /* 1234 */ "VFR27\000" |
| 528 | /* 1240 */ "V27\000" |
| 529 | /* 1244 */ "S47\000" |
| 530 | /* 1248 */ "S57\000" |
| 531 | /* 1252 */ "S67\000" |
| 532 | /* 1256 */ "S77\000" |
| 533 | /* 1260 */ "D7\000" |
| 534 | /* 1263 */ "VF7\000" |
| 535 | /* 1267 */ "G7\000" |
| 536 | /* 1270 */ "VQ7\000" |
| 537 | /* 1274 */ "VFR7\000" |
| 538 | /* 1279 */ "WR7\000" |
| 539 | /* 1283 */ "GPMUCNT7\000" |
| 540 | /* 1292 */ "V7\000" |
| 541 | /* 1295 */ "W7\000" |
| 542 | /* 1298 */ "VF18\000" |
| 543 | /* 1303 */ "VFR18\000" |
| 544 | /* 1309 */ "V18\000" |
| 545 | /* 1313 */ "G19_18\000" |
| 546 | /* 1320 */ "S19_18\000" |
| 547 | /* 1327 */ "VF28\000" |
| 548 | /* 1332 */ "VFR28\000" |
| 549 | /* 1338 */ "V28\000" |
| 550 | /* 1342 */ "G29_28\000" |
| 551 | /* 1349 */ "S29_28\000" |
| 552 | /* 1356 */ "S39_38\000" |
| 553 | /* 1363 */ "S49_48\000" |
| 554 | /* 1370 */ "S58\000" |
| 555 | /* 1374 */ "S59_58\000" |
| 556 | /* 1381 */ "S68\000" |
| 557 | /* 1385 */ "S69_68\000" |
| 558 | /* 1392 */ "S78\000" |
| 559 | /* 1396 */ "S79_78\000" |
| 560 | /* 1403 */ "C8\000" |
| 561 | /* 1406 */ "D8\000" |
| 562 | /* 1409 */ "VF8\000" |
| 563 | /* 1413 */ "G8\000" |
| 564 | /* 1416 */ "VFR8\000" |
| 565 | /* 1421 */ "WR8\000" |
| 566 | /* 1425 */ "V8\000" |
| 567 | /* 1428 */ "W8\000" |
| 568 | /* 1431 */ "C9_8\000" |
| 569 | /* 1436 */ "G9_8\000" |
| 570 | /* 1441 */ "S9_8\000" |
| 571 | /* 1446 */ "VF19\000" |
| 572 | /* 1451 */ "VFR19\000" |
| 573 | /* 1457 */ "S19\000" |
| 574 | /* 1461 */ "V19\000" |
| 575 | /* 1465 */ "VF29\000" |
| 576 | /* 1470 */ "VFR29\000" |
| 577 | /* 1476 */ "V29\000" |
| 578 | /* 1480 */ "S59\000" |
| 579 | /* 1484 */ "S69\000" |
| 580 | /* 1488 */ "S79\000" |
| 581 | /* 1492 */ "D9\000" |
| 582 | /* 1495 */ "VF9\000" |
| 583 | /* 1499 */ "G9\000" |
| 584 | /* 1502 */ "VFR9\000" |
| 585 | /* 1507 */ "WR9\000" |
| 586 | /* 1511 */ "V9\000" |
| 587 | /* 1514 */ "W9\000" |
| 588 | /* 1517 */ "BADVA\000" |
| 589 | /* 1523 */ "EVB\000" |
| 590 | /* 1527 */ "PC\000" |
| 591 | /* 1530 */ "HTID\000" |
| 592 | /* 1535 */ "STID\000" |
| 593 | /* 1540 */ "VID\000" |
| 594 | /* 1544 */ "UPCYCLE\000" |
| 595 | /* 1552 */ "CFGBASE\000" |
| 596 | /* 1560 */ "USR_OVF\000" |
| 597 | /* 1568 */ "DIAG\000" |
| 598 | /* 1573 */ "SYSCFG\000" |
| 599 | /* 1580 */ "PMUEVTCFG\000" |
| 600 | /* 1590 */ "PMUCFG\000" |
| 601 | /* 1597 */ "GPCYCLEHI\000" |
| 602 | /* 1607 */ "UPCYCLEHI\000" |
| 603 | /* 1617 */ "UTIMERHI\000" |
| 604 | /* 1626 */ "PKTCOUNTHI\000" |
| 605 | /* 1637 */ "IMASK\000" |
| 606 | /* 1643 */ "MODECTL\000" |
| 607 | /* 1651 */ "ISDBEN\000" |
| 608 | /* 1658 */ "ISDBMBXIN\000" |
| 609 | /* 1668 */ "GPCYCLELO\000" |
| 610 | /* 1678 */ "UPCYCLELO\000" |
| 611 | /* 1688 */ "UTIMERLO\000" |
| 612 | /* 1697 */ "PKTCOUNTLO\000" |
| 613 | /* 1708 */ "UGP\000" |
| 614 | /* 1712 */ "VTMP\000" |
| 615 | /* 1717 */ "GOSP\000" |
| 616 | /* 1722 */ "CCR\000" |
| 617 | /* 1726 */ "UTIMER\000" |
| 618 | /* 1733 */ "GELR\000" |
| 619 | /* 1738 */ "ISDBGPR\000" |
| 620 | /* 1746 */ "GSR\000" |
| 621 | /* 1750 */ "SSR\000" |
| 622 | /* 1754 */ "USR\000" |
| 623 | /* 1758 */ "CS\000" |
| 624 | /* 1761 */ "FRAMELIMIT\000" |
| 625 | /* 1772 */ "PKTCOUNT\000" |
| 626 | /* 1781 */ "ISDBST\000" |
| 627 | /* 1788 */ "ISDBMBXOUT\000" |
| 628 | /* 1799 */ "REV\000" |
| 629 | /* 1803 */ "FRAMEKEY\000" |
| 630 | }; |
| 631 | #ifdef __GNUC__ |
| 632 | #pragma GCC diagnostic pop |
| 633 | #endif |
| 634 | |
| 635 | extern const MCRegisterDesc HexagonRegDesc[] = { // Descriptors |
| 636 | { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 637 | { .Name: 1517, .SubRegs: 2, .SuperRegs: 711, .SubRegIndices: 2, .RegUnits: 8192, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 638 | { .Name: 1722, .SubRegs: 2, .SuperRegs: 707, .SubRegIndices: 2, .RegUnits: 8193, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 639 | { .Name: 1552, .SubRegs: 2, .SuperRegs: 715, .SubRegIndices: 2, .RegUnits: 8194, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 640 | { .Name: 1758, .SubRegs: 259, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376835, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 641 | { .Name: 1568, .SubRegs: 2, .SuperRegs: 713, .SubRegIndices: 2, .RegUnits: 8197, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 642 | { .Name: 1734, .SubRegs: 2, .SuperRegs: 699, .SubRegIndices: 2, .RegUnits: 8198, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 643 | { .Name: 1523, .SubRegs: 2, .SuperRegs: 707, .SubRegIndices: 2, .RegUnits: 8199, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 644 | { .Name: 1803, .SubRegs: 2, .SuperRegs: 683, .SubRegIndices: 2, .RegUnits: 8200, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 645 | { .Name: 1761, .SubRegs: 2, .SuperRegs: 681, .SubRegIndices: 2, .RegUnits: 8201, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 646 | { .Name: 1733, .SubRegs: 2, .SuperRegs: 681, .SubRegIndices: 2, .RegUnits: 8202, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 647 | { .Name: 1717, .SubRegs: 2, .SuperRegs: 681, .SubRegIndices: 2, .RegUnits: 8203, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 648 | { .Name: 1709, .SubRegs: 2, .SuperRegs: 679, .SubRegIndices: 2, .RegUnits: 8204, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 649 | { .Name: 1597, .SubRegs: 2, .SuperRegs: 687, .SubRegIndices: 2, .RegUnits: 8205, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 650 | { .Name: 1668, .SubRegs: 2, .SuperRegs: 685, .SubRegIndices: 2, .RegUnits: 8206, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 651 | { .Name: 1746, .SubRegs: 2, .SuperRegs: 677, .SubRegIndices: 2, .RegUnits: 8207, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 652 | { .Name: 1530, .SubRegs: 2, .SuperRegs: 691, .SubRegIndices: 2, .RegUnits: 8208, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 653 | { .Name: 1637, .SubRegs: 2, .SuperRegs: 691, .SubRegIndices: 2, .RegUnits: 8209, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 654 | { .Name: 1651, .SubRegs: 2, .SuperRegs: 711, .SubRegIndices: 2, .RegUnits: 8210, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 655 | { .Name: 1738, .SubRegs: 2, .SuperRegs: 709, .SubRegIndices: 2, .RegUnits: 8211, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 656 | { .Name: 1658, .SubRegs: 2, .SuperRegs: 705, .SubRegIndices: 2, .RegUnits: 8212, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 657 | { .Name: 1788, .SubRegs: 2, .SuperRegs: 703, .SubRegIndices: 2, .RegUnits: 8213, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 658 | { .Name: 1781, .SubRegs: 2, .SuperRegs: 697, .SubRegIndices: 2, .RegUnits: 8214, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 659 | { .Name: 1643, .SubRegs: 2, .SuperRegs: 689, .SubRegIndices: 2, .RegUnits: 8215, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 660 | { .Name: 1527, .SubRegs: 2, .SuperRegs: 671, .SubRegIndices: 2, .RegUnits: 8216, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 661 | { .Name: 1598, .SubRegs: 2, .SuperRegs: 695, .SubRegIndices: 2, .RegUnits: 8217, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 662 | { .Name: 1669, .SubRegs: 2, .SuperRegs: 693, .SubRegIndices: 2, .RegUnits: 8218, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 663 | { .Name: 1772, .SubRegs: 88, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376859, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 664 | { .Name: 1626, .SubRegs: 2, .SuperRegs: 71, .SubRegIndices: 2, .RegUnits: 8220, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 665 | { .Name: 1697, .SubRegs: 2, .SuperRegs: 68, .SubRegIndices: 2, .RegUnits: 8219, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 666 | { .Name: 1590, .SubRegs: 2, .SuperRegs: 701, .SubRegIndices: 2, .RegUnits: 8221, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 667 | { .Name: 1580, .SubRegs: 2, .SuperRegs: 699, .SubRegIndices: 2, .RegUnits: 8222, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 668 | { .Name: 1799, .SubRegs: 2, .SuperRegs: 685, .SubRegIndices: 2, .RegUnits: 8223, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 669 | { .Name: 1750, .SubRegs: 2, .SuperRegs: 679, .SubRegIndices: 2, .RegUnits: 8224, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 670 | { .Name: 1535, .SubRegs: 2, .SuperRegs: 675, .SubRegIndices: 2, .RegUnits: 8225, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 671 | { .Name: 1573, .SubRegs: 2, .SuperRegs: 681, .SubRegIndices: 2, .RegUnits: 8226, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 672 | { .Name: 1708, .SubRegs: 2, .SuperRegs: 665, .SubRegIndices: 2, .RegUnits: 8227, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 673 | { .Name: 1544, .SubRegs: 88, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376868, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 674 | { .Name: 1607, .SubRegs: 2, .SuperRegs: 71, .SubRegIndices: 2, .RegUnits: 8229, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 675 | { .Name: 1678, .SubRegs: 2, .SuperRegs: 68, .SubRegIndices: 2, .RegUnits: 8228, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 676 | { .Name: 1754, .SubRegs: 92, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 376870, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 677 | { .Name: 1560, .SubRegs: 2, .SuperRegs: 71, .SubRegIndices: 2, .RegUnits: 8230, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 678 | { .Name: 1726, .SubRegs: 88, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376872, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 679 | { .Name: 1617, .SubRegs: 2, .SuperRegs: 71, .SubRegIndices: 2, .RegUnits: 8233, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 680 | { .Name: 1688, .SubRegs: 2, .SuperRegs: 68, .SubRegIndices: 2, .RegUnits: 8232, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 681 | { .Name: 1540, .SubRegs: 2, .SuperRegs: 673, .SubRegIndices: 2, .RegUnits: 8234, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 682 | { .Name: 1712, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8235, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 683 | { .Name: 167, .SubRegs: 2, .SuperRegs: 669, .SubRegIndices: 2, .RegUnits: 8236, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 684 | { .Name: 361, .SubRegs: 2, .SuperRegs: 667, .SubRegIndices: 2, .RegUnits: 8237, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 685 | { .Name: 203, .SubRegs: 2, .SuperRegs: 677, .SubRegIndices: 2, .RegUnits: 8238, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 686 | { .Name: 397, .SubRegs: 2, .SuperRegs: 677, .SubRegIndices: 2, .RegUnits: 8239, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 687 | { .Name: 178, .SubRegs: 2, .SuperRegs: 675, .SubRegIndices: 2, .RegUnits: 8240, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 688 | { .Name: 372, .SubRegs: 2, .SuperRegs: 675, .SubRegIndices: 2, .RegUnits: 8241, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 689 | { .Name: 1000, .SubRegs: 2, .SuperRegs: 661, .SubRegIndices: 2, .RegUnits: 8242, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 690 | { .Name: 1403, .SubRegs: 2, .SuperRegs: 663, .SubRegIndices: 2, .RegUnits: 1294375, .RegUnitLaneMasks: 27, .IsConstant: 0, .IsArtificial: 0 }, |
| 691 | { .Name: 234, .SubRegs: 2, .SuperRegs: 48, .SubRegIndices: 2, .RegUnits: 8195, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 692 | { .Name: 428, .SubRegs: 2, .SuperRegs: 46, .SubRegIndices: 2, .RegUnits: 8196, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 693 | { .Name: 187, .SubRegs: 262, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376884, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 694 | { .Name: 381, .SubRegs: 265, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376886, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 695 | { .Name: 577, .SubRegs: 268, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376888, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 696 | { .Name: 697, .SubRegs: 271, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376890, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 697 | { .Name: 872, .SubRegs: 274, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376892, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 698 | { .Name: 1003, .SubRegs: 277, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376894, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 699 | { .Name: 1161, .SubRegs: 280, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376896, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 700 | { .Name: 1260, .SubRegs: 283, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376898, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 701 | { .Name: 1406, .SubRegs: 286, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376900, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 702 | { .Name: 1492, .SubRegs: 289, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376902, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 703 | { .Name: 0, .SubRegs: 292, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376904, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 704 | { .Name: 275, .SubRegs: 295, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376906, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 705 | { .Name: 447, .SubRegs: 298, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376908, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 706 | { .Name: 630, .SubRegs: 301, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376910, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 707 | { .Name: 738, .SubRegs: 304, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376912, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 708 | { .Name: 925, .SubRegs: 307, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376914, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 709 | { .Name: 704, .SubRegs: 2, .SuperRegs: 653, .SubRegIndices: 2, .RegUnits: 8276, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 710 | { .Name: 879, .SubRegs: 2, .SuperRegs: 653, .SubRegIndices: 2, .RegUnits: 8277, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 711 | { .Name: 1010, .SubRegs: 2, .SuperRegs: 651, .SubRegIndices: 2, .RegUnits: 8278, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 712 | { .Name: 1168, .SubRegs: 2, .SuperRegs: 651, .SubRegIndices: 2, .RegUnits: 8279, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 713 | { .Name: 1267, .SubRegs: 2, .SuperRegs: 649, .SubRegIndices: 2, .RegUnits: 8280, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 714 | { .Name: 1413, .SubRegs: 2, .SuperRegs: 649, .SubRegIndices: 2, .RegUnits: 8281, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 715 | { .Name: 1499, .SubRegs: 2, .SuperRegs: 647, .SubRegIndices: 2, .RegUnits: 8282, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 716 | { .Name: 9, .SubRegs: 2, .SuperRegs: 647, .SubRegIndices: 2, .RegUnits: 8283, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 717 | { .Name: 284, .SubRegs: 2, .SuperRegs: 645, .SubRegIndices: 2, .RegUnits: 8284, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 718 | { .Name: 456, .SubRegs: 2, .SuperRegs: 645, .SubRegIndices: 2, .RegUnits: 8285, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 719 | { .Name: 639, .SubRegs: 2, .SuperRegs: 643, .SubRegIndices: 2, .RegUnits: 8286, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 720 | { .Name: 747, .SubRegs: 2, .SuperRegs: 643, .SubRegIndices: 2, .RegUnits: 8287, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 721 | { .Name: 934, .SubRegs: 2, .SuperRegs: 641, .SubRegIndices: 2, .RegUnits: 8288, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 722 | { .Name: 58, .SubRegs: 2, .SuperRegs: 645, .SubRegIndices: 2, .RegUnits: 8289, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 723 | { .Name: 316, .SubRegs: 2, .SuperRegs: 643, .SubRegIndices: 2, .RegUnits: 8290, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 724 | { .Name: 502, .SubRegs: 2, .SuperRegs: 643, .SubRegIndices: 2, .RegUnits: 8291, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 725 | { .Name: 671, .SubRegs: 2, .SuperRegs: 641, .SubRegIndices: 2, .RegUnits: 8292, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 726 | { .Name: 95, .SubRegs: 2, .SuperRegs: 647, .SubRegIndices: 2, .RegUnits: 8293, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 727 | { .Name: 335, .SubRegs: 2, .SuperRegs: 645, .SubRegIndices: 2, .RegUnits: 8294, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 728 | { .Name: 238, .SubRegs: 2, .SuperRegs: 639, .SubRegIndices: 2, .RegUnits: 8295, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 729 | { .Name: 432, .SubRegs: 2, .SuperRegs: 637, .SubRegIndices: 2, .RegUnits: 8296, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 730 | { .Name: 600, .SubRegs: 2, .SuperRegs: 637, .SubRegIndices: 2, .RegUnits: 8297, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 731 | { .Name: 723, .SubRegs: 2, .SuperRegs: 635, .SubRegIndices: 2, .RegUnits: 8298, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 732 | { .Name: 895, .SubRegs: 2, .SuperRegs: 633, .SubRegIndices: 2, .RegUnits: 8299, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 733 | { .Name: 1026, .SubRegs: 2, .SuperRegs: 631, .SubRegIndices: 2, .RegUnits: 8300, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 734 | { .Name: 1184, .SubRegs: 2, .SuperRegs: 631, .SubRegIndices: 2, .RegUnits: 8301, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 735 | { .Name: 1283, .SubRegs: 2, .SuperRegs: 629, .SubRegIndices: 2, .RegUnits: 8302, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 736 | { .Name: 194, .SubRegs: 2, .SuperRegs: 659, .SubRegIndices: 2, .RegUnits: 8303, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 737 | { .Name: 388, .SubRegs: 2, .SuperRegs: 659, .SubRegIndices: 2, .RegUnits: 8304, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 738 | { .Name: 174, .SubRegs: 2, .SuperRegs: 625, .SubRegIndices: 2, .RegUnits: 8305, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 739 | { .Name: 368, .SubRegs: 2, .SuperRegs: 625, .SubRegIndices: 2, .RegUnits: 8306, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 740 | { .Name: 213, .SubRegs: 2, .SuperRegs: 627, .SubRegIndices: 2, .RegUnits: 8307, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 741 | { .Name: 407, .SubRegs: 2, .SuperRegs: 625, .SubRegIndices: 2, .RegUnits: 8308, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 742 | { .Name: 218, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 376949, .RegUnitLaneMasks: 27, .IsConstant: 0, .IsArtificial: 0 }, |
| 743 | { .Name: 412, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 376951, .RegUnitLaneMasks: 27, .IsConstant: 0, .IsArtificial: 0 }, |
| 744 | { .Name: 584, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 376953, .RegUnitLaneMasks: 27, .IsConstant: 0, .IsArtificial: 0 }, |
| 745 | { .Name: 707, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 376955, .RegUnitLaneMasks: 27, .IsConstant: 0, .IsArtificial: 0 }, |
| 746 | { .Name: 239, .SubRegs: 2, .SuperRegs: 657, .SubRegIndices: 2, .RegUnits: 8317, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 747 | { .Name: 433, .SubRegs: 2, .SuperRegs: 655, .SubRegIndices: 2, .RegUnits: 8318, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 748 | { .Name: 601, .SubRegs: 2, .SuperRegs: 655, .SubRegIndices: 2, .RegUnits: 8319, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 749 | { .Name: 724, .SubRegs: 2, .SuperRegs: 653, .SubRegIndices: 2, .RegUnits: 8320, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 750 | { .Name: 222, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8321, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 751 | { .Name: 416, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8322, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 752 | { .Name: 588, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8323, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 753 | { .Name: 711, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8324, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 754 | { .Name: 227, .SubRegs: 2, .SuperRegs: 44, .SubRegIndices: 2, .RegUnits: 8244, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 755 | { .Name: 421, .SubRegs: 2, .SuperRegs: 42, .SubRegIndices: 2, .RegUnits: 8245, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 756 | { .Name: 593, .SubRegs: 2, .SuperRegs: 42, .SubRegIndices: 2, .RegUnits: 8246, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 757 | { .Name: 716, .SubRegs: 2, .SuperRegs: 40, .SubRegIndices: 2, .RegUnits: 8247, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 758 | { .Name: 888, .SubRegs: 2, .SuperRegs: 40, .SubRegIndices: 2, .RegUnits: 8248, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 759 | { .Name: 1019, .SubRegs: 2, .SuperRegs: 38, .SubRegIndices: 2, .RegUnits: 8249, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 760 | { .Name: 1177, .SubRegs: 2, .SuperRegs: 38, .SubRegIndices: 2, .RegUnits: 8250, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 761 | { .Name: 1276, .SubRegs: 2, .SuperRegs: 36, .SubRegIndices: 2, .RegUnits: 8251, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 762 | { .Name: 1418, .SubRegs: 2, .SuperRegs: 36, .SubRegIndices: 2, .RegUnits: 8252, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 763 | { .Name: 1504, .SubRegs: 2, .SuperRegs: 34, .SubRegIndices: 2, .RegUnits: 8253, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 764 | { .Name: 15, .SubRegs: 2, .SuperRegs: 34, .SubRegIndices: 2, .RegUnits: 8254, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 765 | { .Name: 290, .SubRegs: 2, .SuperRegs: 32, .SubRegIndices: 2, .RegUnits: 8255, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 766 | { .Name: 462, .SubRegs: 2, .SuperRegs: 32, .SubRegIndices: 2, .RegUnits: 8256, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 767 | { .Name: 645, .SubRegs: 2, .SuperRegs: 30, .SubRegIndices: 2, .RegUnits: 8257, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 768 | { .Name: 753, .SubRegs: 2, .SuperRegs: 30, .SubRegIndices: 2, .RegUnits: 8258, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 769 | { .Name: 940, .SubRegs: 2, .SuperRegs: 28, .SubRegIndices: 2, .RegUnits: 8259, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 770 | { .Name: 1048, .SubRegs: 2, .SuperRegs: 28, .SubRegIndices: 2, .RegUnits: 8260, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 771 | { .Name: 1221, .SubRegs: 2, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 8261, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 772 | { .Name: 1305, .SubRegs: 2, .SuperRegs: 26, .SubRegIndices: 2, .RegUnits: 8262, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 773 | { .Name: 1453, .SubRegs: 2, .SuperRegs: 24, .SubRegIndices: 2, .RegUnits: 8263, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 774 | { .Name: 64, .SubRegs: 2, .SuperRegs: 24, .SubRegIndices: 2, .RegUnits: 8264, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 775 | { .Name: 322, .SubRegs: 2, .SuperRegs: 22, .SubRegIndices: 2, .RegUnits: 8265, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 776 | { .Name: 508, .SubRegs: 2, .SuperRegs: 22, .SubRegIndices: 2, .RegUnits: 8266, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 777 | { .Name: 677, .SubRegs: 2, .SuperRegs: 20, .SubRegIndices: 2, .RegUnits: 8267, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 778 | { .Name: 795, .SubRegs: 2, .SuperRegs: 20, .SubRegIndices: 2, .RegUnits: 8268, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 779 | { .Name: 968, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8269, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 780 | { .Name: 1084, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8270, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 781 | { .Name: 1236, .SubRegs: 2, .SuperRegs: 16, .SubRegIndices: 2, .RegUnits: 8271, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 782 | { .Name: 1334, .SubRegs: 2, .SuperRegs: 16, .SubRegIndices: 2, .RegUnits: 8272, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 783 | { .Name: 1472, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8273, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 784 | { .Name: 101, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8274, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 785 | { .Name: 341, .SubRegs: 2, .SuperRegs: 12, .SubRegIndices: 2, .RegUnits: 8275, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 786 | { .Name: 299, .SubRegs: 2, .SuperRegs: 613, .SubRegIndices: 2, .RegUnits: 8325, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 787 | { .Name: 471, .SubRegs: 2, .SuperRegs: 613, .SubRegIndices: 2, .RegUnits: 8326, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 788 | { .Name: 654, .SubRegs: 2, .SuperRegs: 611, .SubRegIndices: 2, .RegUnits: 8327, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 789 | { .Name: 762, .SubRegs: 2, .SuperRegs: 611, .SubRegIndices: 2, .RegUnits: 8328, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 790 | { .Name: 949, .SubRegs: 2, .SuperRegs: 609, .SubRegIndices: 2, .RegUnits: 8329, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 791 | { .Name: 1457, .SubRegs: 2, .SuperRegs: 611, .SubRegIndices: 2, .RegUnits: 8330, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 792 | { .Name: 68, .SubRegs: 2, .SuperRegs: 611, .SubRegIndices: 2, .RegUnits: 8331, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 793 | { .Name: 512, .SubRegs: 2, .SuperRegs: 611, .SubRegIndices: 2, .RegUnits: 8332, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 794 | { .Name: 681, .SubRegs: 2, .SuperRegs: 609, .SubRegIndices: 2, .RegUnits: 8333, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 795 | { .Name: 799, .SubRegs: 2, .SuperRegs: 609, .SubRegIndices: 2, .RegUnits: 8334, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 796 | { .Name: 972, .SubRegs: 2, .SuperRegs: 607, .SubRegIndices: 2, .RegUnits: 8335, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 797 | { .Name: 1088, .SubRegs: 2, .SuperRegs: 607, .SubRegIndices: 2, .RegUnits: 8336, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 798 | { .Name: 980, .SubRegs: 2, .SuperRegs: 613, .SubRegIndices: 2, .RegUnits: 8337, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 799 | { .Name: 828, .SubRegs: 2, .SuperRegs: 621, .SubRegIndices: 2, .RegUnits: 8338, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 800 | { .Name: 984, .SubRegs: 2, .SuperRegs: 619, .SubRegIndices: 2, .RegUnits: 8339, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 801 | { .Name: 1117, .SubRegs: 2, .SuperRegs: 619, .SubRegIndices: 2, .RegUnits: 8340, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 802 | { .Name: 1244, .SubRegs: 2, .SuperRegs: 617, .SubRegIndices: 2, .RegUnits: 8341, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 803 | { .Name: 839, .SubRegs: 2, .SuperRegs: 623, .SubRegIndices: 2, .RegUnits: 8342, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 804 | { .Name: 988, .SubRegs: 2, .SuperRegs: 621, .SubRegIndices: 2, .RegUnits: 8343, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 805 | { .Name: 1128, .SubRegs: 2, .SuperRegs: 621, .SubRegIndices: 2, .RegUnits: 8344, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 806 | { .Name: 1248, .SubRegs: 2, .SuperRegs: 619, .SubRegIndices: 2, .RegUnits: 8345, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 807 | { .Name: 1370, .SubRegs: 2, .SuperRegs: 619, .SubRegIndices: 2, .RegUnits: 8346, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 808 | { .Name: 1480, .SubRegs: 2, .SuperRegs: 617, .SubRegIndices: 2, .RegUnits: 8347, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 809 | { .Name: 137, .SubRegs: 2, .SuperRegs: 617, .SubRegIndices: 2, .RegUnits: 8348, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 810 | { .Name: 349, .SubRegs: 2, .SuperRegs: 615, .SubRegIndices: 2, .RegUnits: 8349, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 811 | { .Name: 555, .SubRegs: 2, .SuperRegs: 615, .SubRegIndices: 2, .RegUnits: 8350, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 812 | { .Name: 689, .SubRegs: 2, .SuperRegs: 613, .SubRegIndices: 2, .RegUnits: 8351, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 813 | { .Name: 850, .SubRegs: 2, .SuperRegs: 613, .SubRegIndices: 2, .RegUnits: 8352, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 814 | { .Name: 992, .SubRegs: 2, .SuperRegs: 611, .SubRegIndices: 2, .RegUnits: 8353, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 815 | { .Name: 1139, .SubRegs: 2, .SuperRegs: 611, .SubRegIndices: 2, .RegUnits: 8354, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 816 | { .Name: 1252, .SubRegs: 2, .SuperRegs: 609, .SubRegIndices: 2, .RegUnits: 8355, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 817 | { .Name: 1381, .SubRegs: 2, .SuperRegs: 609, .SubRegIndices: 2, .RegUnits: 8356, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 818 | { .Name: 1484, .SubRegs: 2, .SuperRegs: 607, .SubRegIndices: 2, .RegUnits: 8357, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 819 | { .Name: 148, .SubRegs: 2, .SuperRegs: 607, .SubRegIndices: 2, .RegUnits: 8358, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 820 | { .Name: 353, .SubRegs: 2, .SuperRegs: 605, .SubRegIndices: 2, .RegUnits: 8359, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 821 | { .Name: 566, .SubRegs: 2, .SuperRegs: 605, .SubRegIndices: 2, .RegUnits: 8360, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 822 | { .Name: 693, .SubRegs: 2, .SuperRegs: 603, .SubRegIndices: 2, .RegUnits: 8361, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 823 | { .Name: 861, .SubRegs: 2, .SuperRegs: 603, .SubRegIndices: 2, .RegUnits: 8362, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 824 | { .Name: 996, .SubRegs: 2, .SuperRegs: 601, .SubRegIndices: 2, .RegUnits: 8363, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 825 | { .Name: 1150, .SubRegs: 2, .SuperRegs: 601, .SubRegIndices: 2, .RegUnits: 8364, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 826 | { .Name: 1256, .SubRegs: 2, .SuperRegs: 599, .SubRegIndices: 2, .RegUnits: 8365, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 827 | { .Name: 1392, .SubRegs: 2, .SuperRegs: 599, .SubRegIndices: 2, .RegUnits: 8366, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 828 | { .Name: 1488, .SubRegs: 2, .SuperRegs: 597, .SubRegIndices: 2, .RegUnits: 8367, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 829 | { .Name: 159, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8368, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 830 | { .Name: 163, .SubRegs: 2, .SuperRegs: 583, .SubRegIndices: 2, .RegUnits: 8369, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 831 | { .Name: 357, .SubRegs: 2, .SuperRegs: 583, .SubRegIndices: 2, .RegUnits: 8370, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 832 | { .Name: 216, .SubRegs: 2, .SuperRegs: 595, .SubRegIndices: 2, .RegUnits: 8371, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 833 | { .Name: 410, .SubRegs: 2, .SuperRegs: 593, .SubRegIndices: 2, .RegUnits: 8372, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 834 | { .Name: 247, .SubRegs: 2, .SuperRegs: 327, .SubRegIndices: 2, .RegUnits: 8373, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 835 | { .Name: 441, .SubRegs: 2, .SuperRegs: 323, .SubRegIndices: 2, .RegUnits: 8374, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 836 | { .Name: 609, .SubRegs: 2, .SuperRegs: 339, .SubRegIndices: 2, .RegUnits: 8375, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 837 | { .Name: 732, .SubRegs: 2, .SuperRegs: 335, .SubRegIndices: 2, .RegUnits: 8376, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 838 | { .Name: 904, .SubRegs: 2, .SuperRegs: 335, .SubRegIndices: 2, .RegUnits: 8377, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 839 | { .Name: 1035, .SubRegs: 2, .SuperRegs: 331, .SubRegIndices: 2, .RegUnits: 8378, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 840 | { .Name: 1193, .SubRegs: 2, .SuperRegs: 351, .SubRegIndices: 2, .RegUnits: 8379, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 841 | { .Name: 1292, .SubRegs: 2, .SuperRegs: 347, .SubRegIndices: 2, .RegUnits: 8380, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 842 | { .Name: 1425, .SubRegs: 2, .SuperRegs: 347, .SubRegIndices: 2, .RegUnits: 8381, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 843 | { .Name: 1511, .SubRegs: 2, .SuperRegs: 343, .SubRegIndices: 2, .RegUnits: 8382, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 844 | { .Name: 24, .SubRegs: 2, .SuperRegs: 366, .SubRegIndices: 2, .RegUnits: 8383, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 845 | { .Name: 303, .SubRegs: 2, .SuperRegs: 362, .SubRegIndices: 2, .RegUnits: 8384, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 846 | { .Name: 475, .SubRegs: 2, .SuperRegs: 362, .SubRegIndices: 2, .RegUnits: 8385, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 847 | { .Name: 658, .SubRegs: 2, .SuperRegs: 358, .SubRegIndices: 2, .RegUnits: 8386, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 848 | { .Name: 766, .SubRegs: 2, .SuperRegs: 378, .SubRegIndices: 2, .RegUnits: 8387, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 849 | { .Name: 953, .SubRegs: 2, .SuperRegs: 374, .SubRegIndices: 2, .RegUnits: 8388, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 850 | { .Name: 1052, .SubRegs: 2, .SuperRegs: 374, .SubRegIndices: 2, .RegUnits: 8389, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 851 | { .Name: 1225, .SubRegs: 2, .SuperRegs: 370, .SubRegIndices: 2, .RegUnits: 8390, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 852 | { .Name: 1309, .SubRegs: 2, .SuperRegs: 390, .SubRegIndices: 2, .RegUnits: 8391, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 853 | { .Name: 1461, .SubRegs: 2, .SuperRegs: 386, .SubRegIndices: 2, .RegUnits: 8392, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 854 | { .Name: 72, .SubRegs: 2, .SuperRegs: 386, .SubRegIndices: 2, .RegUnits: 8393, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 855 | { .Name: 326, .SubRegs: 2, .SuperRegs: 382, .SubRegIndices: 2, .RegUnits: 8394, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 856 | { .Name: 516, .SubRegs: 2, .SuperRegs: 402, .SubRegIndices: 2, .RegUnits: 8395, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 857 | { .Name: 685, .SubRegs: 2, .SuperRegs: 398, .SubRegIndices: 2, .RegUnits: 8396, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 858 | { .Name: 803, .SubRegs: 2, .SuperRegs: 398, .SubRegIndices: 2, .RegUnits: 8397, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 859 | { .Name: 976, .SubRegs: 2, .SuperRegs: 394, .SubRegIndices: 2, .RegUnits: 8398, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 860 | { .Name: 1092, .SubRegs: 2, .SuperRegs: 414, .SubRegIndices: 2, .RegUnits: 8399, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 861 | { .Name: 1240, .SubRegs: 2, .SuperRegs: 410, .SubRegIndices: 2, .RegUnits: 8400, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 862 | { .Name: 1338, .SubRegs: 2, .SuperRegs: 410, .SubRegIndices: 2, .RegUnits: 8401, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 863 | { .Name: 1476, .SubRegs: 2, .SuperRegs: 406, .SubRegIndices: 2, .RegUnits: 8402, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 864 | { .Name: 105, .SubRegs: 2, .SuperRegs: 422, .SubRegIndices: 2, .RegUnits: 8403, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 865 | { .Name: 345, .SubRegs: 2, .SuperRegs: 418, .SubRegIndices: 2, .RegUnits: 8404, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 0 }, |
| 866 | { .Name: 190, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8405, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 867 | { .Name: 384, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8406, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 868 | { .Name: 580, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8407, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 869 | { .Name: 700, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8408, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 870 | { .Name: 875, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8409, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 871 | { .Name: 1006, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8410, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 872 | { .Name: 1164, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8411, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 873 | { .Name: 1263, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8412, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 874 | { .Name: 1409, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8413, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 875 | { .Name: 1495, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8414, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 876 | { .Name: 4, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8415, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 877 | { .Name: 279, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8416, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 878 | { .Name: 451, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8417, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 879 | { .Name: 634, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8418, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 880 | { .Name: 742, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8419, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 881 | { .Name: 929, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8420, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 882 | { .Name: 1041, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8421, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 883 | { .Name: 1214, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8422, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 884 | { .Name: 1298, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8423, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 885 | { .Name: 1446, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8424, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 886 | { .Name: 53, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8425, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 887 | { .Name: 311, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8426, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 888 | { .Name: 497, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8427, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 889 | { .Name: 666, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8428, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 890 | { .Name: 788, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8429, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 891 | { .Name: 961, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8430, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 892 | { .Name: 1077, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8431, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 893 | { .Name: 1229, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8432, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 894 | { .Name: 1327, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8433, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 895 | { .Name: 1465, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8434, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 896 | { .Name: 90, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8435, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 897 | { .Name: 330, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8436, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 898 | { .Name: 225, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8437, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 899 | { .Name: 419, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8438, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 900 | { .Name: 591, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8439, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 901 | { .Name: 714, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8440, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 902 | { .Name: 886, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8441, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 903 | { .Name: 1017, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8442, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 904 | { .Name: 1175, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8443, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 905 | { .Name: 1274, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8444, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 906 | { .Name: 1416, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8445, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 907 | { .Name: 1502, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8446, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 908 | { .Name: 13, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8447, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 909 | { .Name: 288, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8448, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 910 | { .Name: 460, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8449, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 911 | { .Name: 643, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8450, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 912 | { .Name: 751, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8451, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 913 | { .Name: 938, .SubRegs: 2, .SuperRegs: 533, .SubRegIndices: 2, .RegUnits: 8452, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 914 | { .Name: 1046, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8453, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 915 | { .Name: 1219, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8454, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 916 | { .Name: 1303, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8455, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 917 | { .Name: 1451, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8456, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 918 | { .Name: 62, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8457, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 919 | { .Name: 320, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8458, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 920 | { .Name: 506, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8459, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 921 | { .Name: 675, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8460, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 922 | { .Name: 793, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8461, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 923 | { .Name: 966, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8462, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 924 | { .Name: 1082, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8463, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 925 | { .Name: 1234, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8464, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 926 | { .Name: 1332, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8465, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 927 | { .Name: 1470, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8466, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 928 | { .Name: 99, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8467, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 929 | { .Name: 339, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8468, .RegUnitLaneMasks: 23, .IsConstant: 0, .IsArtificial: 1 }, |
| 930 | { .Name: 221, .SubRegs: 178, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 1044661, .RegUnitLaneMasks: 18, .IsConstant: 0, .IsArtificial: 0 }, |
| 931 | { .Name: 415, .SubRegs: 188, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 1044665, .RegUnitLaneMasks: 18, .IsConstant: 0, .IsArtificial: 0 }, |
| 932 | { .Name: 587, .SubRegs: 198, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 1044669, .RegUnitLaneMasks: 18, .IsConstant: 0, .IsArtificial: 0 }, |
| 933 | { .Name: 710, .SubRegs: 208, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 1044673, .RegUnitLaneMasks: 18, .IsConstant: 0, .IsArtificial: 0 }, |
| 934 | { .Name: 882, .SubRegs: 218, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 1044677, .RegUnitLaneMasks: 18, .IsConstant: 0, .IsArtificial: 0 }, |
| 935 | { .Name: 1013, .SubRegs: 228, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 1044681, .RegUnitLaneMasks: 18, .IsConstant: 0, .IsArtificial: 0 }, |
| 936 | { .Name: 1171, .SubRegs: 238, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 1044685, .RegUnitLaneMasks: 18, .IsConstant: 0, .IsArtificial: 0 }, |
| 937 | { .Name: 1270, .SubRegs: 248, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 1044689, .RegUnitLaneMasks: 18, .IsConstant: 0, .IsArtificial: 0 }, |
| 938 | { .Name: 250, .SubRegs: 175, .SuperRegs: 324, .SubRegIndices: 3, .RegUnits: 377013, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 939 | { .Name: 444, .SubRegs: 182, .SuperRegs: 332, .SubRegIndices: 3, .RegUnits: 377015, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 940 | { .Name: 612, .SubRegs: 185, .SuperRegs: 332, .SubRegIndices: 3, .RegUnits: 377017, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 941 | { .Name: 735, .SubRegs: 192, .SuperRegs: 344, .SubRegIndices: 3, .RegUnits: 377019, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 942 | { .Name: 907, .SubRegs: 195, .SuperRegs: 344, .SubRegIndices: 3, .RegUnits: 377021, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 943 | { .Name: 1038, .SubRegs: 202, .SuperRegs: 359, .SubRegIndices: 3, .RegUnits: 377023, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 944 | { .Name: 1196, .SubRegs: 205, .SuperRegs: 359, .SubRegIndices: 3, .RegUnits: 377025, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 945 | { .Name: 1295, .SubRegs: 212, .SuperRegs: 371, .SubRegIndices: 3, .RegUnits: 377027, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 946 | { .Name: 1428, .SubRegs: 215, .SuperRegs: 371, .SubRegIndices: 3, .RegUnits: 377029, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 947 | { .Name: 1514, .SubRegs: 222, .SuperRegs: 383, .SubRegIndices: 3, .RegUnits: 377031, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 948 | { .Name: 28, .SubRegs: 225, .SuperRegs: 383, .SubRegIndices: 3, .RegUnits: 377033, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 949 | { .Name: 307, .SubRegs: 232, .SuperRegs: 395, .SubRegIndices: 3, .RegUnits: 377035, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 950 | { .Name: 479, .SubRegs: 235, .SuperRegs: 395, .SubRegIndices: 3, .RegUnits: 377037, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 951 | { .Name: 662, .SubRegs: 242, .SuperRegs: 407, .SubRegIndices: 3, .RegUnits: 377039, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 952 | { .Name: 770, .SubRegs: 245, .SuperRegs: 407, .SubRegIndices: 3, .RegUnits: 377041, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 953 | { .Name: 957, .SubRegs: 252, .SuperRegs: 419, .SubRegIndices: 3, .RegUnits: 377043, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 954 | { .Name: 230, .SubRegs: 503, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2289845, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 955 | { .Name: 424, .SubRegs: 498, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2277559, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 956 | { .Name: 596, .SubRegs: 493, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2252985, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 957 | { .Name: 719, .SubRegs: 488, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2228411, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 958 | { .Name: 891, .SubRegs: 483, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2216125, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 959 | { .Name: 1022, .SubRegs: 478, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2203839, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 960 | { .Name: 1180, .SubRegs: 473, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2191553, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 961 | { .Name: 1279, .SubRegs: 468, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2179267, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 962 | { .Name: 1421, .SubRegs: 463, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2166981, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 963 | { .Name: 1507, .SubRegs: 458, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2154695, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 964 | { .Name: 19, .SubRegs: 453, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2142409, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 965 | { .Name: 294, .SubRegs: 448, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2130123, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 966 | { .Name: 466, .SubRegs: 443, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2117837, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 967 | { .Name: 649, .SubRegs: 438, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2105551, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 968 | { .Name: 757, .SubRegs: 433, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2093265, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 969 | { .Name: 944, .SubRegs: 428, .SuperRegs: 2, .SubRegIndices: 5, .RegUnits: 2080979, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 }, |
| 970 | { .Name: 253, .SubRegs: 9, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2302065, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 971 | { .Name: 615, .SubRegs: 9, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2302066, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 972 | { .Name: 910, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2404402, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 973 | { .Name: 1199, .SubRegs: 136, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376947, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 974 | { .Name: 1431, .SubRegs: 53, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1290264, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 975 | { .Name: 32, .SubRegs: 59, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1314828, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 976 | { .Name: 1056, .SubRegs: 79, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376840, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 977 | { .Name: 258, .SubRegs: 312, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1282058, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 978 | { .Name: 620, .SubRegs: 553, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2310155, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 979 | { .Name: 915, .SubRegs: 106, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376917, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 980 | { .Name: 1204, .SubRegs: 109, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376919, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 981 | { .Name: 1436, .SubRegs: 112, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376921, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 982 | { .Name: 39, .SubRegs: 115, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376923, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 983 | { .Name: 483, .SubRegs: 118, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376925, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 984 | { .Name: 774, .SubRegs: 121, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376927, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 985 | { .Name: 1063, .SubRegs: 130, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376939, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 986 | { .Name: 1313, .SubRegs: 133, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376941, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 987 | { .Name: 76, .SubRegs: 118, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376929, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 988 | { .Name: 520, .SubRegs: 121, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376931, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 989 | { .Name: 807, .SubRegs: 76, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376845, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 990 | { .Name: 1096, .SubRegs: 124, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376935, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 991 | { .Name: 1342, .SubRegs: 127, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376937, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 992 | { .Name: 109, .SubRegs: 115, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376933, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 993 | { .Name: 270, .SubRegs: 2, .SuperRegs: 62, .SubRegIndices: 2, .RegUnits: 2408566, .RegUnitLaneMasks: 24, .IsConstant: 0, .IsArtificial: 0 }, |
| 994 | { .Name: 625, .SubRegs: 56, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1458182, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 995 | { .Name: 920, .SubRegs: 97, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376876, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 996 | { .Name: 1209, .SubRegs: 50, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1671169, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 997 | { .Name: 1441, .SubRegs: 64, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1306624, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 998 | { .Name: 46, .SubRegs: 580, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2355217, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 999 | { .Name: 490, .SubRegs: 154, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376966, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1000 | { .Name: 781, .SubRegs: 157, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376968, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1001 | { .Name: 1070, .SubRegs: 318, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1306631, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1002 | { .Name: 1320, .SubRegs: 577, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2347042, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1003 | { .Name: 83, .SubRegs: 6, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2338858, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1004 | { .Name: 527, .SubRegs: 157, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376972, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1005 | { .Name: 814, .SubRegs: 160, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376974, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1006 | { .Name: 1103, .SubRegs: 3, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2396162, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1007 | { .Name: 1349, .SubRegs: 355, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1413125, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1008 | { .Name: 116, .SubRegs: 73, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376857, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1009 | { .Name: 534, .SubRegs: 566, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 2330646, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1010 | { .Name: 821, .SubRegs: 547, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1745008, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1011 | { .Name: 1110, .SubRegs: 67, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1269806, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1012 | { .Name: 1356, .SubRegs: 67, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 1269807, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1013 | { .Name: 123, .SubRegs: 94, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376852, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1014 | { .Name: 541, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376850, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1015 | { .Name: 832, .SubRegs: 142, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376978, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1016 | { .Name: 1121, .SubRegs: 145, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376980, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1017 | { .Name: 1363, .SubRegs: 100, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376957, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1018 | { .Name: 130, .SubRegs: 103, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376959, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1019 | { .Name: 548, .SubRegs: 70, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376861, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1020 | { .Name: 843, .SubRegs: 139, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376982, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1021 | { .Name: 1132, .SubRegs: 142, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376984, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1022 | { .Name: 1374, .SubRegs: 145, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376986, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1023 | { .Name: 141, .SubRegs: 148, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376988, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1024 | { .Name: 559, .SubRegs: 151, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376990, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1025 | { .Name: 854, .SubRegs: 154, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376992, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1026 | { .Name: 1143, .SubRegs: 157, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376994, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1027 | { .Name: 1385, .SubRegs: 160, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376996, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1028 | { .Name: 152, .SubRegs: 163, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 376998, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1029 | { .Name: 570, .SubRegs: 166, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 377000, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1030 | { .Name: 865, .SubRegs: 169, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 377002, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1031 | { .Name: 1154, .SubRegs: 82, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 377004, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1032 | { .Name: 1396, .SubRegs: 85, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 377006, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1033 | { .Name: 263, .SubRegs: 172, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 377011, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1034 | }; |
| 1035 | |
| 1036 | extern const MCPhysReg HexagonRegUnitRoots[][2] = { |
| 1037 | { Hexagon::BADVA }, |
| 1038 | { Hexagon::CCR }, |
| 1039 | { Hexagon::CFGBASE }, |
| 1040 | { Hexagon::CS0 }, |
| 1041 | { Hexagon::CS1 }, |
| 1042 | { Hexagon::DIAG }, |
| 1043 | { Hexagon::ELR }, |
| 1044 | { Hexagon::EVB }, |
| 1045 | { Hexagon::FRAMEKEY }, |
| 1046 | { Hexagon::FRAMELIMIT }, |
| 1047 | { Hexagon::GELR }, |
| 1048 | { Hexagon::GOSP }, |
| 1049 | { Hexagon::GP }, |
| 1050 | { Hexagon::GPCYCLEHI }, |
| 1051 | { Hexagon::GPCYCLELO }, |
| 1052 | { Hexagon::GSR }, |
| 1053 | { Hexagon::HTID }, |
| 1054 | { Hexagon::IMASK }, |
| 1055 | { Hexagon::ISDBEN }, |
| 1056 | { Hexagon::ISDBGPR }, |
| 1057 | { Hexagon::ISDBMBXIN }, |
| 1058 | { Hexagon::ISDBMBXOUT }, |
| 1059 | { Hexagon::ISDBST }, |
| 1060 | { Hexagon::MODECTL }, |
| 1061 | { Hexagon::PC }, |
| 1062 | { Hexagon::PCYCLEHI }, |
| 1063 | { Hexagon::PCYCLELO }, |
| 1064 | { Hexagon::PKTCOUNTLO }, |
| 1065 | { Hexagon::PKTCOUNTHI }, |
| 1066 | { Hexagon::PMUCFG }, |
| 1067 | { Hexagon::PMUEVTCFG }, |
| 1068 | { Hexagon::REV }, |
| 1069 | { Hexagon::SSR }, |
| 1070 | { Hexagon::STID }, |
| 1071 | { Hexagon::SYSCFG }, |
| 1072 | { Hexagon::UGP }, |
| 1073 | { Hexagon::UPCYCLELO }, |
| 1074 | { Hexagon::UPCYCLEHI }, |
| 1075 | { Hexagon::USR_OVF }, |
| 1076 | { Hexagon::USR, Hexagon::C8 }, |
| 1077 | { Hexagon::UTIMERLO }, |
| 1078 | { Hexagon::UTIMERHI }, |
| 1079 | { Hexagon::VID }, |
| 1080 | { Hexagon::VTMP }, |
| 1081 | { Hexagon::BADVA0 }, |
| 1082 | { Hexagon::BADVA1 }, |
| 1083 | { Hexagon::BRKPTCFG0 }, |
| 1084 | { Hexagon::BRKPTCFG1 }, |
| 1085 | { Hexagon::BRKPTPC0 }, |
| 1086 | { Hexagon::BRKPTPC1 }, |
| 1087 | { Hexagon::C5 }, |
| 1088 | { Hexagon::C8 }, |
| 1089 | { Hexagon::R0 }, |
| 1090 | { Hexagon::R1 }, |
| 1091 | { Hexagon::R2 }, |
| 1092 | { Hexagon::R3 }, |
| 1093 | { Hexagon::R4 }, |
| 1094 | { Hexagon::R5 }, |
| 1095 | { Hexagon::R6 }, |
| 1096 | { Hexagon::R7 }, |
| 1097 | { Hexagon::R8 }, |
| 1098 | { Hexagon::R9 }, |
| 1099 | { Hexagon::R10 }, |
| 1100 | { Hexagon::R11 }, |
| 1101 | { Hexagon::R12 }, |
| 1102 | { Hexagon::R13 }, |
| 1103 | { Hexagon::R14 }, |
| 1104 | { Hexagon::R15 }, |
| 1105 | { Hexagon::R16 }, |
| 1106 | { Hexagon::R17 }, |
| 1107 | { Hexagon::R18 }, |
| 1108 | { Hexagon::R19 }, |
| 1109 | { Hexagon::R20 }, |
| 1110 | { Hexagon::R21 }, |
| 1111 | { Hexagon::R22 }, |
| 1112 | { Hexagon::R23 }, |
| 1113 | { Hexagon::R24 }, |
| 1114 | { Hexagon::R25 }, |
| 1115 | { Hexagon::R26 }, |
| 1116 | { Hexagon::R27 }, |
| 1117 | { Hexagon::R28 }, |
| 1118 | { Hexagon::R29 }, |
| 1119 | { Hexagon::R30 }, |
| 1120 | { Hexagon::R31 }, |
| 1121 | { Hexagon::G3 }, |
| 1122 | { Hexagon::G4 }, |
| 1123 | { Hexagon::G5 }, |
| 1124 | { Hexagon::G6 }, |
| 1125 | { Hexagon::G7 }, |
| 1126 | { Hexagon::G8 }, |
| 1127 | { Hexagon::G9 }, |
| 1128 | { Hexagon::G10 }, |
| 1129 | { Hexagon::G11 }, |
| 1130 | { Hexagon::G12 }, |
| 1131 | { Hexagon::G13 }, |
| 1132 | { Hexagon::G14 }, |
| 1133 | { Hexagon::G15 }, |
| 1134 | { Hexagon::G20 }, |
| 1135 | { Hexagon::G21 }, |
| 1136 | { Hexagon::G22 }, |
| 1137 | { Hexagon::G23 }, |
| 1138 | { Hexagon::G30 }, |
| 1139 | { Hexagon::G31 }, |
| 1140 | { Hexagon::GPMUCNT0 }, |
| 1141 | { Hexagon::GPMUCNT1 }, |
| 1142 | { Hexagon::GPMUCNT2 }, |
| 1143 | { Hexagon::GPMUCNT3 }, |
| 1144 | { Hexagon::GPMUCNT4 }, |
| 1145 | { Hexagon::GPMUCNT5 }, |
| 1146 | { Hexagon::GPMUCNT6 }, |
| 1147 | { Hexagon::GPMUCNT7 }, |
| 1148 | { Hexagon::ISDBCFG0 }, |
| 1149 | { Hexagon::ISDBCFG1 }, |
| 1150 | { Hexagon::LC0 }, |
| 1151 | { Hexagon::LC1 }, |
| 1152 | { Hexagon::M0 }, |
| 1153 | { Hexagon::M1 }, |
| 1154 | { Hexagon::P0 }, |
| 1155 | { Hexagon::P0, Hexagon::P3_0 }, |
| 1156 | { Hexagon::P1 }, |
| 1157 | { Hexagon::P1, Hexagon::P3_0 }, |
| 1158 | { Hexagon::P2 }, |
| 1159 | { Hexagon::P2, Hexagon::P3_0 }, |
| 1160 | { Hexagon::P3 }, |
| 1161 | { Hexagon::P3, Hexagon::P3_0 }, |
| 1162 | { Hexagon::PMUCNT0 }, |
| 1163 | { Hexagon::PMUCNT1 }, |
| 1164 | { Hexagon::PMUCNT2 }, |
| 1165 | { Hexagon::PMUCNT3 }, |
| 1166 | { Hexagon::Q0 }, |
| 1167 | { Hexagon::Q1 }, |
| 1168 | { Hexagon::Q2 }, |
| 1169 | { Hexagon::Q3 }, |
| 1170 | { Hexagon::S11 }, |
| 1171 | { Hexagon::S12 }, |
| 1172 | { Hexagon::S13 }, |
| 1173 | { Hexagon::S14 }, |
| 1174 | { Hexagon::S15 }, |
| 1175 | { Hexagon::S19 }, |
| 1176 | { Hexagon::S20 }, |
| 1177 | { Hexagon::S22 }, |
| 1178 | { Hexagon::S23 }, |
| 1179 | { Hexagon::S24 }, |
| 1180 | { Hexagon::S25 }, |
| 1181 | { Hexagon::S26 }, |
| 1182 | { Hexagon::S35 }, |
| 1183 | { Hexagon::S44 }, |
| 1184 | { Hexagon::S45 }, |
| 1185 | { Hexagon::S46 }, |
| 1186 | { Hexagon::S47 }, |
| 1187 | { Hexagon::S54 }, |
| 1188 | { Hexagon::S55 }, |
| 1189 | { Hexagon::S56 }, |
| 1190 | { Hexagon::S57 }, |
| 1191 | { Hexagon::S58 }, |
| 1192 | { Hexagon::S59 }, |
| 1193 | { Hexagon::S60 }, |
| 1194 | { Hexagon::S61 }, |
| 1195 | { Hexagon::S62 }, |
| 1196 | { Hexagon::S63 }, |
| 1197 | { Hexagon::S64 }, |
| 1198 | { Hexagon::S65 }, |
| 1199 | { Hexagon::S66 }, |
| 1200 | { Hexagon::S67 }, |
| 1201 | { Hexagon::S68 }, |
| 1202 | { Hexagon::S69 }, |
| 1203 | { Hexagon::S70 }, |
| 1204 | { Hexagon::S71 }, |
| 1205 | { Hexagon::S72 }, |
| 1206 | { Hexagon::S73 }, |
| 1207 | { Hexagon::S74 }, |
| 1208 | { Hexagon::S75 }, |
| 1209 | { Hexagon::S76 }, |
| 1210 | { Hexagon::S77 }, |
| 1211 | { Hexagon::S78 }, |
| 1212 | { Hexagon::S79 }, |
| 1213 | { Hexagon::S80 }, |
| 1214 | { Hexagon::SA0 }, |
| 1215 | { Hexagon::SA1 }, |
| 1216 | { Hexagon::SGP0 }, |
| 1217 | { Hexagon::SGP1 }, |
| 1218 | { Hexagon::V0 }, |
| 1219 | { Hexagon::V1 }, |
| 1220 | { Hexagon::V2 }, |
| 1221 | { Hexagon::V3 }, |
| 1222 | { Hexagon::V4 }, |
| 1223 | { Hexagon::V5 }, |
| 1224 | { Hexagon::V6 }, |
| 1225 | { Hexagon::V7 }, |
| 1226 | { Hexagon::V8 }, |
| 1227 | { Hexagon::V9 }, |
| 1228 | { Hexagon::V10 }, |
| 1229 | { Hexagon::V11 }, |
| 1230 | { Hexagon::V12 }, |
| 1231 | { Hexagon::V13 }, |
| 1232 | { Hexagon::V14 }, |
| 1233 | { Hexagon::V15 }, |
| 1234 | { Hexagon::V16 }, |
| 1235 | { Hexagon::V17 }, |
| 1236 | { Hexagon::V18 }, |
| 1237 | { Hexagon::V19 }, |
| 1238 | { Hexagon::V20 }, |
| 1239 | { Hexagon::V21 }, |
| 1240 | { Hexagon::V22 }, |
| 1241 | { Hexagon::V23 }, |
| 1242 | { Hexagon::V24 }, |
| 1243 | { Hexagon::V25 }, |
| 1244 | { Hexagon::V26 }, |
| 1245 | { Hexagon::V27 }, |
| 1246 | { Hexagon::V28 }, |
| 1247 | { Hexagon::V29 }, |
| 1248 | { Hexagon::V30 }, |
| 1249 | { Hexagon::V31 }, |
| 1250 | { Hexagon::VF0 }, |
| 1251 | { Hexagon::VF1 }, |
| 1252 | { Hexagon::VF2 }, |
| 1253 | { Hexagon::VF3 }, |
| 1254 | { Hexagon::VF4 }, |
| 1255 | { Hexagon::VF5 }, |
| 1256 | { Hexagon::VF6 }, |
| 1257 | { Hexagon::VF7 }, |
| 1258 | { Hexagon::VF8 }, |
| 1259 | { Hexagon::VF9 }, |
| 1260 | { Hexagon::VF10 }, |
| 1261 | { Hexagon::VF11 }, |
| 1262 | { Hexagon::VF12 }, |
| 1263 | { Hexagon::VF13 }, |
| 1264 | { Hexagon::VF14 }, |
| 1265 | { Hexagon::VF15 }, |
| 1266 | { Hexagon::VF16 }, |
| 1267 | { Hexagon::VF17 }, |
| 1268 | { Hexagon::VF18 }, |
| 1269 | { Hexagon::VF19 }, |
| 1270 | { Hexagon::VF20 }, |
| 1271 | { Hexagon::VF21 }, |
| 1272 | { Hexagon::VF22 }, |
| 1273 | { Hexagon::VF23 }, |
| 1274 | { Hexagon::VF24 }, |
| 1275 | { Hexagon::VF25 }, |
| 1276 | { Hexagon::VF26 }, |
| 1277 | { Hexagon::VF27 }, |
| 1278 | { Hexagon::VF28 }, |
| 1279 | { Hexagon::VF29 }, |
| 1280 | { Hexagon::VF30 }, |
| 1281 | { Hexagon::VF31 }, |
| 1282 | { Hexagon::VFR0 }, |
| 1283 | { Hexagon::VFR1 }, |
| 1284 | { Hexagon::VFR2 }, |
| 1285 | { Hexagon::VFR3 }, |
| 1286 | { Hexagon::VFR4 }, |
| 1287 | { Hexagon::VFR5 }, |
| 1288 | { Hexagon::VFR6 }, |
| 1289 | { Hexagon::VFR7 }, |
| 1290 | { Hexagon::VFR8 }, |
| 1291 | { Hexagon::VFR9 }, |
| 1292 | { Hexagon::VFR10 }, |
| 1293 | { Hexagon::VFR11 }, |
| 1294 | { Hexagon::VFR12 }, |
| 1295 | { Hexagon::VFR13 }, |
| 1296 | { Hexagon::VFR14 }, |
| 1297 | { Hexagon::VFR15 }, |
| 1298 | { Hexagon::VFR16 }, |
| 1299 | { Hexagon::VFR17 }, |
| 1300 | { Hexagon::VFR18 }, |
| 1301 | { Hexagon::VFR19 }, |
| 1302 | { Hexagon::VFR20 }, |
| 1303 | { Hexagon::VFR21 }, |
| 1304 | { Hexagon::VFR22 }, |
| 1305 | { Hexagon::VFR23 }, |
| 1306 | { Hexagon::VFR24 }, |
| 1307 | { Hexagon::VFR25 }, |
| 1308 | { Hexagon::VFR26 }, |
| 1309 | { Hexagon::VFR27 }, |
| 1310 | { Hexagon::VFR28 }, |
| 1311 | { Hexagon::VFR29 }, |
| 1312 | { Hexagon::VFR30 }, |
| 1313 | { Hexagon::VFR31 }, |
| 1314 | { Hexagon::P3_0 }, |
| 1315 | }; |
| 1316 | |
| 1317 | // Register classes... |
| 1318 | |
| 1319 | #ifdef __GNUC__ |
| 1320 | #pragma GCC diagnostic push |
| 1321 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 1322 | #endif |
| 1323 | extern const char HexagonRegClassStrings[] = { |
| 1324 | /* 0 */ "CtrRegs64\000" |
| 1325 | /* 10 */ "SysRegs64\000" |
| 1326 | /* 20 */ "GuestRegs64\000" |
| 1327 | /* 32 */ "DoubleRegs_with_isub_hi_in_IntRegsLow8\000" |
| 1328 | /* 71 */ "HvxVQR\000" |
| 1329 | /* 78 */ "HvxQR\000" |
| 1330 | /* 84 */ "HvxVR\000" |
| 1331 | /* 90 */ "HvxWR\000" |
| 1332 | /* 96 */ "V62Regs_with_isub_hi\000" |
| 1333 | /* 117 */ "HvxWR_with_wsub_lo\000" |
| 1334 | /* 136 */ "CtrRegs64_and_V62Regs\000" |
| 1335 | /* 158 */ "CtrRegs_and_V62Regs\000" |
| 1336 | /* 178 */ "HvxVR_and_V65Regs\000" |
| 1337 | /* 196 */ "GeneralDoubleLow8Regs\000" |
| 1338 | /* 218 */ "GeneralSubRegs\000" |
| 1339 | /* 233 */ "PredRegs\000" |
| 1340 | /* 242 */ "CtrRegs64_with_isub_hi_in_ModRegs\000" |
| 1341 | /* 276 */ "DoubleRegs\000" |
| 1342 | /* 287 */ "CtrRegs\000" |
| 1343 | /* 295 */ "SysRegs\000" |
| 1344 | /* 303 */ "IntRegs\000" |
| 1345 | /* 311 */ "GuestRegs\000" |
| 1346 | /* 321 */ "UsrBits\000" |
| 1347 | /* 329 */ "VectRegRev\000" |
| 1348 | /* 340 */ "CtrRegs_with_subreg_overflow\000" |
| 1349 | }; |
| 1350 | #ifdef __GNUC__ |
| 1351 | #pragma GCC diagnostic pop |
| 1352 | #endif |
| 1353 | |
| 1354 | using HexagonRegisterClassStorage = MCRegisterClassStorage<29, 428, 739, 54, 13, 19>; |
| 1355 | extern const MCRegisterClassStorage<29, 428, 739, 54, 13, 19> HexagonMCRegisterClassStorage = { |
| 1356 | .Classes: { |
| 1357 | { |
| 1358 | offsetof(HexagonRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass), |
| 1359 | offsetof(HexagonRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass), |
| 1360 | .NameIdx: 321, |
| 1361 | .RegSizeInBits: 1, |
| 1362 | .RegsSize: 1, |
| 1363 | .RegSetSize: 6, |
| 1364 | .ID: Hexagon::UsrBitsRegClassID, |
| 1365 | .CopyCost: 1, /* CopyCost */ |
| 1366 | .Allocatable: false, /* Allocatable */ |
| 1367 | .BaseClass: false, |
| 1368 | offsetof(HexagonRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass), |
| 1369 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[3]) - 0 * sizeof(MCRegisterClass), |
| 1370 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1371 | .AllocationPriority: 0, |
| 1372 | .GlobalPriority: false, |
| 1373 | .TSFlags: 0x00, /* TSFlags */ |
| 1374 | .SpillStackID: 0, /* SpillStackID */ |
| 1375 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1376 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1377 | offsetof(HexagonRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass), |
| 1378 | .SuperClassesSize: 0 |
| 1379 | }, |
| 1380 | { |
| 1381 | offsetof(HexagonRegisterClassStorage, Regs[1]) - 1 * sizeof(MCRegisterClass), |
| 1382 | offsetof(HexagonRegisterClassStorage, BitSets[6]) - 1 * sizeof(MCRegisterClass), |
| 1383 | .NameIdx: 295, |
| 1384 | .RegSizeInBits: 32, |
| 1385 | .RegsSize: 81, |
| 1386 | .RegSetSize: 25, |
| 1387 | .ID: Hexagon::SysRegsRegClassID, |
| 1388 | .CopyCost: 1, /* CopyCost */ |
| 1389 | .Allocatable: false, /* Allocatable */ |
| 1390 | .BaseClass: false, |
| 1391 | offsetof(HexagonRegisterClassStorage, SubClassMasks[2]) - 1 * sizeof(MCRegisterClass), |
| 1392 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 1 * sizeof(MCRegisterClass), |
| 1393 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1394 | .AllocationPriority: 0, |
| 1395 | .GlobalPriority: false, |
| 1396 | .TSFlags: 0x00, /* TSFlags */ |
| 1397 | .SpillStackID: 0, /* SpillStackID */ |
| 1398 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1399 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1400 | offsetof(HexagonRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass), |
| 1401 | .SuperClassesSize: 0 |
| 1402 | }, |
| 1403 | { |
| 1404 | offsetof(HexagonRegisterClassStorage, Regs[82]) - 2 * sizeof(MCRegisterClass), |
| 1405 | offsetof(HexagonRegisterClassStorage, BitSets[31]) - 2 * sizeof(MCRegisterClass), |
| 1406 | .NameIdx: 311, |
| 1407 | .RegSizeInBits: 32, |
| 1408 | .RegsSize: 32, |
| 1409 | .RegSetSize: 13, |
| 1410 | .ID: Hexagon::GuestRegsRegClassID, |
| 1411 | .CopyCost: 1, /* CopyCost */ |
| 1412 | .Allocatable: false, /* Allocatable */ |
| 1413 | .BaseClass: false, |
| 1414 | offsetof(HexagonRegisterClassStorage, SubClassMasks[5]) - 2 * sizeof(MCRegisterClass), |
| 1415 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 2 * sizeof(MCRegisterClass), |
| 1416 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1417 | .AllocationPriority: 0, |
| 1418 | .GlobalPriority: false, |
| 1419 | .TSFlags: 0x00, /* TSFlags */ |
| 1420 | .SpillStackID: 0, /* SpillStackID */ |
| 1421 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1422 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1423 | offsetof(HexagonRegisterClassStorage, SuperClasses[0]) - 2 * sizeof(MCRegisterClass), |
| 1424 | .SuperClassesSize: 0 |
| 1425 | }, |
| 1426 | { |
| 1427 | offsetof(HexagonRegisterClassStorage, Regs[114]) - 3 * sizeof(MCRegisterClass), |
| 1428 | offsetof(HexagonRegisterClassStorage, BitSets[44]) - 3 * sizeof(MCRegisterClass), |
| 1429 | .NameIdx: 303, |
| 1430 | .RegSizeInBits: 32, |
| 1431 | .RegsSize: 32, |
| 1432 | .RegSetSize: 19, |
| 1433 | .ID: Hexagon::IntRegsRegClassID, |
| 1434 | .CopyCost: 1, /* CopyCost */ |
| 1435 | .Allocatable: true, /* Allocatable */ |
| 1436 | .BaseClass: false, |
| 1437 | offsetof(HexagonRegisterClassStorage, SubClassMasks[8]) - 3 * sizeof(MCRegisterClass), |
| 1438 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 3 * sizeof(MCRegisterClass), |
| 1439 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1440 | .AllocationPriority: 0, |
| 1441 | .GlobalPriority: false, |
| 1442 | .TSFlags: 0x00, /* TSFlags */ |
| 1443 | .SpillStackID: 0, /* SpillStackID */ |
| 1444 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1445 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1446 | offsetof(HexagonRegisterClassStorage, SuperClasses[0]) - 3 * sizeof(MCRegisterClass), |
| 1447 | .SuperClassesSize: 0 |
| 1448 | }, |
| 1449 | { |
| 1450 | offsetof(HexagonRegisterClassStorage, Regs[146]) - 4 * sizeof(MCRegisterClass), |
| 1451 | offsetof(HexagonRegisterClassStorage, BitSets[63]) - 4 * sizeof(MCRegisterClass), |
| 1452 | .NameIdx: 287, |
| 1453 | .RegSizeInBits: 32, |
| 1454 | .RegsSize: 23, |
| 1455 | .RegSetSize: 45, |
| 1456 | .ID: Hexagon::CtrRegsRegClassID, |
| 1457 | .CopyCost: 1, /* CopyCost */ |
| 1458 | .Allocatable: false, /* Allocatable */ |
| 1459 | .BaseClass: false, |
| 1460 | offsetof(HexagonRegisterClassStorage, SubClassMasks[11]) - 4 * sizeof(MCRegisterClass), |
| 1461 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 4 * sizeof(MCRegisterClass), |
| 1462 | .LaneMask: LaneBitmask(0x0000000000000004), |
| 1463 | .AllocationPriority: 0, |
| 1464 | .GlobalPriority: false, |
| 1465 | .TSFlags: 0x00, /* TSFlags */ |
| 1466 | .SpillStackID: 0, /* SpillStackID */ |
| 1467 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1468 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1469 | offsetof(HexagonRegisterClassStorage, SuperClasses[0]) - 4 * sizeof(MCRegisterClass), |
| 1470 | .SuperClassesSize: 0 |
| 1471 | }, |
| 1472 | { |
| 1473 | offsetof(HexagonRegisterClassStorage, Regs[169]) - 5 * sizeof(MCRegisterClass), |
| 1474 | offsetof(HexagonRegisterClassStorage, BitSets[108]) - 5 * sizeof(MCRegisterClass), |
| 1475 | .NameIdx: 218, |
| 1476 | .RegSizeInBits: 32, |
| 1477 | .RegsSize: 16, |
| 1478 | .RegSetSize: 18, |
| 1479 | .ID: Hexagon::GeneralSubRegsRegClassID, |
| 1480 | .CopyCost: 1, /* CopyCost */ |
| 1481 | .Allocatable: true, /* Allocatable */ |
| 1482 | .BaseClass: false, |
| 1483 | offsetof(HexagonRegisterClassStorage, SubClassMasks[14]) - 5 * sizeof(MCRegisterClass), |
| 1484 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass), |
| 1485 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1486 | .AllocationPriority: 0, |
| 1487 | .GlobalPriority: false, |
| 1488 | .TSFlags: 0x00, /* TSFlags */ |
| 1489 | .SpillStackID: 0, /* SpillStackID */ |
| 1490 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1491 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1492 | offsetof(HexagonRegisterClassStorage, SuperClasses[0]) - 5 * sizeof(MCRegisterClass), |
| 1493 | .SuperClassesSize: 1 |
| 1494 | }, |
| 1495 | { |
| 1496 | offsetof(HexagonRegisterClassStorage, Regs[185]) - 6 * sizeof(MCRegisterClass), |
| 1497 | offsetof(HexagonRegisterClassStorage, BitSets[126]) - 6 * sizeof(MCRegisterClass), |
| 1498 | .NameIdx: 150, |
| 1499 | .RegSizeInBits: 32, |
| 1500 | .RegsSize: 9, |
| 1501 | .RegSetSize: 43, |
| 1502 | .ID: Hexagon::V62RegsRegClassID, |
| 1503 | .CopyCost: 1, /* CopyCost */ |
| 1504 | .Allocatable: false, /* Allocatable */ |
| 1505 | .BaseClass: false, |
| 1506 | offsetof(HexagonRegisterClassStorage, SubClassMasks[17]) - 6 * sizeof(MCRegisterClass), |
| 1507 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 6 * sizeof(MCRegisterClass), |
| 1508 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1509 | .AllocationPriority: 0, |
| 1510 | .GlobalPriority: false, |
| 1511 | .TSFlags: 0x00, /* TSFlags */ |
| 1512 | .SpillStackID: 0, /* SpillStackID */ |
| 1513 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1514 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1515 | offsetof(HexagonRegisterClassStorage, SuperClasses[1]) - 6 * sizeof(MCRegisterClass), |
| 1516 | .SuperClassesSize: 0 |
| 1517 | }, |
| 1518 | { |
| 1519 | offsetof(HexagonRegisterClassStorage, Regs[194]) - 7 * sizeof(MCRegisterClass), |
| 1520 | offsetof(HexagonRegisterClassStorage, BitSets[169]) - 7 * sizeof(MCRegisterClass), |
| 1521 | .NameIdx: 59, |
| 1522 | .RegSizeInBits: 32, |
| 1523 | .RegsSize: 8, |
| 1524 | .RegSetSize: 16, |
| 1525 | .ID: Hexagon::IntRegsLow8RegClassID, |
| 1526 | .CopyCost: 1, /* CopyCost */ |
| 1527 | .Allocatable: true, /* Allocatable */ |
| 1528 | .BaseClass: false, |
| 1529 | offsetof(HexagonRegisterClassStorage, SubClassMasks[20]) - 7 * sizeof(MCRegisterClass), |
| 1530 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 7 * sizeof(MCRegisterClass), |
| 1531 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1532 | .AllocationPriority: 0, |
| 1533 | .GlobalPriority: false, |
| 1534 | .TSFlags: 0x00, /* TSFlags */ |
| 1535 | .SpillStackID: 0, /* SpillStackID */ |
| 1536 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1537 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1538 | offsetof(HexagonRegisterClassStorage, SuperClasses[1]) - 7 * sizeof(MCRegisterClass), |
| 1539 | .SuperClassesSize: 2 |
| 1540 | }, |
| 1541 | { |
| 1542 | offsetof(HexagonRegisterClassStorage, Regs[202]) - 8 * sizeof(MCRegisterClass), |
| 1543 | offsetof(HexagonRegisterClassStorage, BitSets[185]) - 8 * sizeof(MCRegisterClass), |
| 1544 | .NameIdx: 158, |
| 1545 | .RegSizeInBits: 32, |
| 1546 | .RegsSize: 6, |
| 1547 | .RegSetSize: 6, |
| 1548 | .ID: Hexagon::CtrRegs_and_V62RegsRegClassID, |
| 1549 | .CopyCost: 1, /* CopyCost */ |
| 1550 | .Allocatable: false, /* Allocatable */ |
| 1551 | .BaseClass: false, |
| 1552 | offsetof(HexagonRegisterClassStorage, SubClassMasks[23]) - 8 * sizeof(MCRegisterClass), |
| 1553 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 8 * sizeof(MCRegisterClass), |
| 1554 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1555 | .AllocationPriority: 0, |
| 1556 | .GlobalPriority: false, |
| 1557 | .TSFlags: 0x00, /* TSFlags */ |
| 1558 | .SpillStackID: 0, /* SpillStackID */ |
| 1559 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1560 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1561 | offsetof(HexagonRegisterClassStorage, SuperClasses[3]) - 8 * sizeof(MCRegisterClass), |
| 1562 | .SuperClassesSize: 2 |
| 1563 | }, |
| 1564 | { |
| 1565 | offsetof(HexagonRegisterClassStorage, Regs[208]) - 9 * sizeof(MCRegisterClass), |
| 1566 | offsetof(HexagonRegisterClassStorage, BitSets[191]) - 9 * sizeof(MCRegisterClass), |
| 1567 | .NameIdx: 233, |
| 1568 | .RegSizeInBits: 32, |
| 1569 | .RegsSize: 4, |
| 1570 | .RegSetSize: 14, |
| 1571 | .ID: Hexagon::PredRegsRegClassID, |
| 1572 | .CopyCost: 1, /* CopyCost */ |
| 1573 | .Allocatable: true, /* Allocatable */ |
| 1574 | .BaseClass: false, |
| 1575 | offsetof(HexagonRegisterClassStorage, SubClassMasks[26]) - 9 * sizeof(MCRegisterClass), |
| 1576 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 9 * sizeof(MCRegisterClass), |
| 1577 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1578 | .AllocationPriority: 0, |
| 1579 | .GlobalPriority: false, |
| 1580 | .TSFlags: 0x00, /* TSFlags */ |
| 1581 | .SpillStackID: 0, /* SpillStackID */ |
| 1582 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1583 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1584 | offsetof(HexagonRegisterClassStorage, SuperClasses[5]) - 9 * sizeof(MCRegisterClass), |
| 1585 | .SuperClassesSize: 0 |
| 1586 | }, |
| 1587 | { |
| 1588 | offsetof(HexagonRegisterClassStorage, Regs[212]) - 10 * sizeof(MCRegisterClass), |
| 1589 | offsetof(HexagonRegisterClassStorage, BitSets[205]) - 10 * sizeof(MCRegisterClass), |
| 1590 | .NameIdx: 96, |
| 1591 | .RegSizeInBits: 32, |
| 1592 | .RegsSize: 3, |
| 1593 | .RegSetSize: 43, |
| 1594 | .ID: Hexagon::V62Regs_with_isub_hiRegClassID, |
| 1595 | .CopyCost: 1, /* CopyCost */ |
| 1596 | .Allocatable: false, /* Allocatable */ |
| 1597 | .BaseClass: false, |
| 1598 | offsetof(HexagonRegisterClassStorage, SubClassMasks[27]) - 10 * sizeof(MCRegisterClass), |
| 1599 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 10 * sizeof(MCRegisterClass), |
| 1600 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1601 | .AllocationPriority: 0, |
| 1602 | .GlobalPriority: false, |
| 1603 | .TSFlags: 0x00, /* TSFlags */ |
| 1604 | .SpillStackID: 0, /* SpillStackID */ |
| 1605 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1606 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1607 | offsetof(HexagonRegisterClassStorage, SuperClasses[5]) - 10 * sizeof(MCRegisterClass), |
| 1608 | .SuperClassesSize: 1 |
| 1609 | }, |
| 1610 | { |
| 1611 | offsetof(HexagonRegisterClassStorage, Regs[215]) - 11 * sizeof(MCRegisterClass), |
| 1612 | offsetof(HexagonRegisterClassStorage, BitSets[248]) - 11 * sizeof(MCRegisterClass), |
| 1613 | .NameIdx: 268, |
| 1614 | .RegSizeInBits: 32, |
| 1615 | .RegsSize: 2, |
| 1616 | .RegSetSize: 14, |
| 1617 | .ID: Hexagon::ModRegsRegClassID, |
| 1618 | .CopyCost: 1, /* CopyCost */ |
| 1619 | .Allocatable: true, /* Allocatable */ |
| 1620 | .BaseClass: false, |
| 1621 | offsetof(HexagonRegisterClassStorage, SubClassMasks[28]) - 11 * sizeof(MCRegisterClass), |
| 1622 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[0]) - 11 * sizeof(MCRegisterClass), |
| 1623 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1624 | .AllocationPriority: 0, |
| 1625 | .GlobalPriority: false, |
| 1626 | .TSFlags: 0x00, /* TSFlags */ |
| 1627 | .SpillStackID: 0, /* SpillStackID */ |
| 1628 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1629 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1630 | offsetof(HexagonRegisterClassStorage, SuperClasses[6]) - 11 * sizeof(MCRegisterClass), |
| 1631 | .SuperClassesSize: 1 |
| 1632 | }, |
| 1633 | { |
| 1634 | offsetof(HexagonRegisterClassStorage, Regs[217]) - 12 * sizeof(MCRegisterClass), |
| 1635 | offsetof(HexagonRegisterClassStorage, BitSets[262]) - 12 * sizeof(MCRegisterClass), |
| 1636 | .NameIdx: 340, |
| 1637 | .RegSizeInBits: 32, |
| 1638 | .RegsSize: 1, |
| 1639 | .RegSetSize: 6, |
| 1640 | .ID: Hexagon::CtrRegs_with_subreg_overflowRegClassID, |
| 1641 | .CopyCost: 1, /* CopyCost */ |
| 1642 | .Allocatable: false, /* Allocatable */ |
| 1643 | .BaseClass: false, |
| 1644 | offsetof(HexagonRegisterClassStorage, SubClassMasks[31]) - 12 * sizeof(MCRegisterClass), |
| 1645 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 12 * sizeof(MCRegisterClass), |
| 1646 | .LaneMask: LaneBitmask(0x0000000000000004), |
| 1647 | .AllocationPriority: 0, |
| 1648 | .GlobalPriority: false, |
| 1649 | .TSFlags: 0x00, /* TSFlags */ |
| 1650 | .SpillStackID: 0, /* SpillStackID */ |
| 1651 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1652 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1653 | offsetof(HexagonRegisterClassStorage, SuperClasses[7]) - 12 * sizeof(MCRegisterClass), |
| 1654 | .SuperClassesSize: 1 |
| 1655 | }, |
| 1656 | { |
| 1657 | offsetof(HexagonRegisterClassStorage, Regs[218]) - 13 * sizeof(MCRegisterClass), |
| 1658 | offsetof(HexagonRegisterClassStorage, BitSets[268]) - 13 * sizeof(MCRegisterClass), |
| 1659 | .NameIdx: 188, |
| 1660 | .RegSizeInBits: 32, |
| 1661 | .RegsSize: 1, |
| 1662 | .RegSetSize: 6, |
| 1663 | .ID: Hexagon::V65RegsRegClassID, |
| 1664 | .CopyCost: 1, /* CopyCost */ |
| 1665 | .Allocatable: false, /* Allocatable */ |
| 1666 | .BaseClass: false, |
| 1667 | offsetof(HexagonRegisterClassStorage, SubClassMasks[32]) - 13 * sizeof(MCRegisterClass), |
| 1668 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 13 * sizeof(MCRegisterClass), |
| 1669 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1670 | .AllocationPriority: 0, |
| 1671 | .GlobalPriority: false, |
| 1672 | .TSFlags: 0x00, /* TSFlags */ |
| 1673 | .SpillStackID: 0, /* SpillStackID */ |
| 1674 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1675 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1676 | offsetof(HexagonRegisterClassStorage, SuperClasses[8]) - 13 * sizeof(MCRegisterClass), |
| 1677 | .SuperClassesSize: 0 |
| 1678 | }, |
| 1679 | { |
| 1680 | offsetof(HexagonRegisterClassStorage, Regs[219]) - 14 * sizeof(MCRegisterClass), |
| 1681 | offsetof(HexagonRegisterClassStorage, BitSets[274]) - 14 * sizeof(MCRegisterClass), |
| 1682 | .NameIdx: 10, |
| 1683 | .RegSizeInBits: 64, |
| 1684 | .RegsSize: 40, |
| 1685 | .RegSetSize: 50, |
| 1686 | .ID: Hexagon::SysRegs64RegClassID, |
| 1687 | .CopyCost: 1, /* CopyCost */ |
| 1688 | .Allocatable: false, /* Allocatable */ |
| 1689 | .BaseClass: false, |
| 1690 | offsetof(HexagonRegisterClassStorage, SubClassMasks[33]) - 14 * sizeof(MCRegisterClass), |
| 1691 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 14 * sizeof(MCRegisterClass), |
| 1692 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1693 | .AllocationPriority: 0, |
| 1694 | .GlobalPriority: false, |
| 1695 | .TSFlags: 0x00, /* TSFlags */ |
| 1696 | .SpillStackID: 0, /* SpillStackID */ |
| 1697 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1698 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1699 | offsetof(HexagonRegisterClassStorage, SuperClasses[8]) - 14 * sizeof(MCRegisterClass), |
| 1700 | .SuperClassesSize: 0 |
| 1701 | }, |
| 1702 | { |
| 1703 | offsetof(HexagonRegisterClassStorage, Regs[259]) - 15 * sizeof(MCRegisterClass), |
| 1704 | offsetof(HexagonRegisterClassStorage, BitSets[324]) - 15 * sizeof(MCRegisterClass), |
| 1705 | .NameIdx: 276, |
| 1706 | .RegSizeInBits: 64, |
| 1707 | .RegsSize: 16, |
| 1708 | .RegSetSize: 10, |
| 1709 | .ID: Hexagon::DoubleRegsRegClassID, |
| 1710 | .CopyCost: 1, /* CopyCost */ |
| 1711 | .Allocatable: true, /* Allocatable */ |
| 1712 | .BaseClass: false, |
| 1713 | offsetof(HexagonRegisterClassStorage, SubClassMasks[34]) - 15 * sizeof(MCRegisterClass), |
| 1714 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 15 * sizeof(MCRegisterClass), |
| 1715 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1716 | .AllocationPriority: 0, |
| 1717 | .GlobalPriority: false, |
| 1718 | .TSFlags: 0x00, /* TSFlags */ |
| 1719 | .SpillStackID: 0, /* SpillStackID */ |
| 1720 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1721 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1722 | offsetof(HexagonRegisterClassStorage, SuperClasses[8]) - 15 * sizeof(MCRegisterClass), |
| 1723 | .SuperClassesSize: 0 |
| 1724 | }, |
| 1725 | { |
| 1726 | offsetof(HexagonRegisterClassStorage, Regs[275]) - 16 * sizeof(MCRegisterClass), |
| 1727 | offsetof(HexagonRegisterClassStorage, BitSets[334]) - 16 * sizeof(MCRegisterClass), |
| 1728 | .NameIdx: 20, |
| 1729 | .RegSizeInBits: 64, |
| 1730 | .RegsSize: 16, |
| 1731 | .RegSetSize: 45, |
| 1732 | .ID: Hexagon::GuestRegs64RegClassID, |
| 1733 | .CopyCost: 1, /* CopyCost */ |
| 1734 | .Allocatable: false, /* Allocatable */ |
| 1735 | .BaseClass: false, |
| 1736 | offsetof(HexagonRegisterClassStorage, SubClassMasks[35]) - 16 * sizeof(MCRegisterClass), |
| 1737 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 16 * sizeof(MCRegisterClass), |
| 1738 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1739 | .AllocationPriority: 0, |
| 1740 | .GlobalPriority: false, |
| 1741 | .TSFlags: 0x00, /* TSFlags */ |
| 1742 | .SpillStackID: 0, /* SpillStackID */ |
| 1743 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1744 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1745 | offsetof(HexagonRegisterClassStorage, SuperClasses[8]) - 16 * sizeof(MCRegisterClass), |
| 1746 | .SuperClassesSize: 0 |
| 1747 | }, |
| 1748 | { |
| 1749 | offsetof(HexagonRegisterClassStorage, Regs[291]) - 17 * sizeof(MCRegisterClass), |
| 1750 | offsetof(HexagonRegisterClassStorage, BitSets[379]) - 17 * sizeof(MCRegisterClass), |
| 1751 | .NameIdx: 329, |
| 1752 | .RegSizeInBits: 64, |
| 1753 | .RegsSize: 16, |
| 1754 | .RegSetSize: 42, |
| 1755 | .ID: Hexagon::VectRegRevRegClassID, |
| 1756 | .CopyCost: 1, /* CopyCost */ |
| 1757 | .Allocatable: true, /* Allocatable */ |
| 1758 | .BaseClass: false, |
| 1759 | offsetof(HexagonRegisterClassStorage, SubClassMasks[36]) - 17 * sizeof(MCRegisterClass), |
| 1760 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 17 * sizeof(MCRegisterClass), |
| 1761 | .LaneMask: LaneBitmask(0x0000000000000038), |
| 1762 | .AllocationPriority: 0, |
| 1763 | .GlobalPriority: false, |
| 1764 | .TSFlags: 0x00, /* TSFlags */ |
| 1765 | .SpillStackID: 0, /* SpillStackID */ |
| 1766 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1767 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1768 | offsetof(HexagonRegisterClassStorage, SuperClasses[8]) - 17 * sizeof(MCRegisterClass), |
| 1769 | .SuperClassesSize: 0 |
| 1770 | }, |
| 1771 | { |
| 1772 | offsetof(HexagonRegisterClassStorage, Regs[307]) - 18 * sizeof(MCRegisterClass), |
| 1773 | offsetof(HexagonRegisterClassStorage, BitSets[421]) - 18 * sizeof(MCRegisterClass), |
| 1774 | .NameIdx: 0, |
| 1775 | .RegSizeInBits: 64, |
| 1776 | .RegsSize: 11, |
| 1777 | .RegSetSize: 43, |
| 1778 | .ID: Hexagon::CtrRegs64RegClassID, |
| 1779 | .CopyCost: 1, /* CopyCost */ |
| 1780 | .Allocatable: false, /* Allocatable */ |
| 1781 | .BaseClass: false, |
| 1782 | offsetof(HexagonRegisterClassStorage, SubClassMasks[37]) - 18 * sizeof(MCRegisterClass), |
| 1783 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 18 * sizeof(MCRegisterClass), |
| 1784 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1785 | .AllocationPriority: 0, |
| 1786 | .GlobalPriority: false, |
| 1787 | .TSFlags: 0x00, /* TSFlags */ |
| 1788 | .SpillStackID: 0, /* SpillStackID */ |
| 1789 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1790 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1791 | offsetof(HexagonRegisterClassStorage, SuperClasses[8]) - 18 * sizeof(MCRegisterClass), |
| 1792 | .SuperClassesSize: 0 |
| 1793 | }, |
| 1794 | { |
| 1795 | offsetof(HexagonRegisterClassStorage, Regs[318]) - 19 * sizeof(MCRegisterClass), |
| 1796 | offsetof(HexagonRegisterClassStorage, BitSets[464]) - 19 * sizeof(MCRegisterClass), |
| 1797 | .NameIdx: 196, |
| 1798 | .RegSizeInBits: 64, |
| 1799 | .RegsSize: 8, |
| 1800 | .RegSetSize: 9, |
| 1801 | .ID: Hexagon::GeneralDoubleLow8RegsRegClassID, |
| 1802 | .CopyCost: 1, /* CopyCost */ |
| 1803 | .Allocatable: true, /* Allocatable */ |
| 1804 | .BaseClass: false, |
| 1805 | offsetof(HexagonRegisterClassStorage, SubClassMasks[38]) - 19 * sizeof(MCRegisterClass), |
| 1806 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 19 * sizeof(MCRegisterClass), |
| 1807 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1808 | .AllocationPriority: 0, |
| 1809 | .GlobalPriority: false, |
| 1810 | .TSFlags: 0x00, /* TSFlags */ |
| 1811 | .SpillStackID: 0, /* SpillStackID */ |
| 1812 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1813 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1814 | offsetof(HexagonRegisterClassStorage, SuperClasses[8]) - 19 * sizeof(MCRegisterClass), |
| 1815 | .SuperClassesSize: 1 |
| 1816 | }, |
| 1817 | { |
| 1818 | offsetof(HexagonRegisterClassStorage, Regs[326]) - 20 * sizeof(MCRegisterClass), |
| 1819 | offsetof(HexagonRegisterClassStorage, BitSets[473]) - 20 * sizeof(MCRegisterClass), |
| 1820 | .NameIdx: 32, |
| 1821 | .RegSizeInBits: 64, |
| 1822 | .RegsSize: 4, |
| 1823 | .RegSetSize: 8, |
| 1824 | .ID: Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, |
| 1825 | .CopyCost: 1, /* CopyCost */ |
| 1826 | .Allocatable: true, /* Allocatable */ |
| 1827 | .BaseClass: false, |
| 1828 | offsetof(HexagonRegisterClassStorage, SubClassMasks[39]) - 20 * sizeof(MCRegisterClass), |
| 1829 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 20 * sizeof(MCRegisterClass), |
| 1830 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1831 | .AllocationPriority: 0, |
| 1832 | .GlobalPriority: false, |
| 1833 | .TSFlags: 0x00, /* TSFlags */ |
| 1834 | .SpillStackID: 0, /* SpillStackID */ |
| 1835 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1836 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1837 | offsetof(HexagonRegisterClassStorage, SuperClasses[9]) - 20 * sizeof(MCRegisterClass), |
| 1838 | .SuperClassesSize: 2 |
| 1839 | }, |
| 1840 | { |
| 1841 | offsetof(HexagonRegisterClassStorage, Regs[330]) - 21 * sizeof(MCRegisterClass), |
| 1842 | offsetof(HexagonRegisterClassStorage, BitSets[481]) - 21 * sizeof(MCRegisterClass), |
| 1843 | .NameIdx: 136, |
| 1844 | .RegSizeInBits: 64, |
| 1845 | .RegsSize: 3, |
| 1846 | .RegSetSize: 43, |
| 1847 | .ID: Hexagon::CtrRegs64_and_V62RegsRegClassID, |
| 1848 | .CopyCost: 1, /* CopyCost */ |
| 1849 | .Allocatable: false, /* Allocatable */ |
| 1850 | .BaseClass: false, |
| 1851 | offsetof(HexagonRegisterClassStorage, SubClassMasks[40]) - 21 * sizeof(MCRegisterClass), |
| 1852 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 21 * sizeof(MCRegisterClass), |
| 1853 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1854 | .AllocationPriority: 0, |
| 1855 | .GlobalPriority: false, |
| 1856 | .TSFlags: 0x00, /* TSFlags */ |
| 1857 | .SpillStackID: 0, /* SpillStackID */ |
| 1858 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1859 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1860 | offsetof(HexagonRegisterClassStorage, SuperClasses[11]) - 21 * sizeof(MCRegisterClass), |
| 1861 | .SuperClassesSize: 3 |
| 1862 | }, |
| 1863 | { |
| 1864 | offsetof(HexagonRegisterClassStorage, Regs[333]) - 22 * sizeof(MCRegisterClass), |
| 1865 | offsetof(HexagonRegisterClassStorage, BitSets[524]) - 22 * sizeof(MCRegisterClass), |
| 1866 | .NameIdx: 242, |
| 1867 | .RegSizeInBits: 64, |
| 1868 | .RegsSize: 1, |
| 1869 | .RegSetSize: 43, |
| 1870 | .ID: Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClassID, |
| 1871 | .CopyCost: 1, /* CopyCost */ |
| 1872 | .Allocatable: false, /* Allocatable */ |
| 1873 | .BaseClass: false, |
| 1874 | offsetof(HexagonRegisterClassStorage, SubClassMasks[41]) - 22 * sizeof(MCRegisterClass), |
| 1875 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 22 * sizeof(MCRegisterClass), |
| 1876 | .LaneMask: LaneBitmask(0x0000000000000003), |
| 1877 | .AllocationPriority: 0, |
| 1878 | .GlobalPriority: false, |
| 1879 | .TSFlags: 0x00, /* TSFlags */ |
| 1880 | .SpillStackID: 0, /* SpillStackID */ |
| 1881 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1882 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1883 | offsetof(HexagonRegisterClassStorage, SuperClasses[14]) - 22 * sizeof(MCRegisterClass), |
| 1884 | .SuperClassesSize: 1 |
| 1885 | }, |
| 1886 | { |
| 1887 | offsetof(HexagonRegisterClassStorage, Regs[334]) - 23 * sizeof(MCRegisterClass), |
| 1888 | offsetof(HexagonRegisterClassStorage, BitSets[567]) - 23 * sizeof(MCRegisterClass), |
| 1889 | .NameIdx: 78, |
| 1890 | .RegSizeInBits: 0, |
| 1891 | .RegsSize: 4, |
| 1892 | .RegSetSize: 15, |
| 1893 | .ID: Hexagon::HvxQRRegClassID, |
| 1894 | .CopyCost: 1, /* CopyCost */ |
| 1895 | .Allocatable: true, /* Allocatable */ |
| 1896 | .BaseClass: false, |
| 1897 | offsetof(HexagonRegisterClassStorage, SubClassMasks[42]) - 23 * sizeof(MCRegisterClass), |
| 1898 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 23 * sizeof(MCRegisterClass), |
| 1899 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1900 | .AllocationPriority: 0, |
| 1901 | .GlobalPriority: false, |
| 1902 | .TSFlags: 0x00, /* TSFlags */ |
| 1903 | .SpillStackID: 0, /* SpillStackID */ |
| 1904 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1905 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1906 | offsetof(HexagonRegisterClassStorage, SuperClasses[15]) - 23 * sizeof(MCRegisterClass), |
| 1907 | .SuperClassesSize: 0 |
| 1908 | }, |
| 1909 | { |
| 1910 | offsetof(HexagonRegisterClassStorage, Regs[338]) - 24 * sizeof(MCRegisterClass), |
| 1911 | offsetof(HexagonRegisterClassStorage, BitSets[582]) - 24 * sizeof(MCRegisterClass), |
| 1912 | .NameIdx: 84, |
| 1913 | .RegSizeInBits: 0, |
| 1914 | .RegsSize: 33, |
| 1915 | .RegSetSize: 29, |
| 1916 | .ID: Hexagon::HvxVRRegClassID, |
| 1917 | .CopyCost: 1, /* CopyCost */ |
| 1918 | .Allocatable: true, /* Allocatable */ |
| 1919 | .BaseClass: false, |
| 1920 | offsetof(HexagonRegisterClassStorage, SubClassMasks[43]) - 24 * sizeof(MCRegisterClass), |
| 1921 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[8]) - 24 * sizeof(MCRegisterClass), |
| 1922 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1923 | .AllocationPriority: 0, |
| 1924 | .GlobalPriority: false, |
| 1925 | .TSFlags: 0x00, /* TSFlags */ |
| 1926 | .SpillStackID: 0, /* SpillStackID */ |
| 1927 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1928 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1929 | offsetof(HexagonRegisterClassStorage, SuperClasses[15]) - 24 * sizeof(MCRegisterClass), |
| 1930 | .SuperClassesSize: 0 |
| 1931 | }, |
| 1932 | { |
| 1933 | offsetof(HexagonRegisterClassStorage, Regs[371]) - 25 * sizeof(MCRegisterClass), |
| 1934 | offsetof(HexagonRegisterClassStorage, BitSets[611]) - 25 * sizeof(MCRegisterClass), |
| 1935 | .NameIdx: 178, |
| 1936 | .RegSizeInBits: 0, |
| 1937 | .RegsSize: 1, |
| 1938 | .RegSetSize: 6, |
| 1939 | .ID: Hexagon::HvxVR_and_V65RegsRegClassID, |
| 1940 | .CopyCost: 1, /* CopyCost */ |
| 1941 | .Allocatable: true, /* Allocatable */ |
| 1942 | .BaseClass: false, |
| 1943 | offsetof(HexagonRegisterClassStorage, SubClassMasks[48]) - 25 * sizeof(MCRegisterClass), |
| 1944 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 25 * sizeof(MCRegisterClass), |
| 1945 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1946 | .AllocationPriority: 0, |
| 1947 | .GlobalPriority: false, |
| 1948 | .TSFlags: 0x00, /* TSFlags */ |
| 1949 | .SpillStackID: 0, /* SpillStackID */ |
| 1950 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1951 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1952 | offsetof(HexagonRegisterClassStorage, SuperClasses[15]) - 25 * sizeof(MCRegisterClass), |
| 1953 | .SuperClassesSize: 2 |
| 1954 | }, |
| 1955 | { |
| 1956 | offsetof(HexagonRegisterClassStorage, Regs[372]) - 26 * sizeof(MCRegisterClass), |
| 1957 | offsetof(HexagonRegisterClassStorage, BitSets[617]) - 26 * sizeof(MCRegisterClass), |
| 1958 | .NameIdx: 90, |
| 1959 | .RegSizeInBits: 0, |
| 1960 | .RegsSize: 32, |
| 1961 | .RegSetSize: 42, |
| 1962 | .ID: Hexagon::HvxWRRegClassID, |
| 1963 | .CopyCost: 1, /* CopyCost */ |
| 1964 | .Allocatable: true, /* Allocatable */ |
| 1965 | .BaseClass: false, |
| 1966 | offsetof(HexagonRegisterClassStorage, SubClassMasks[49]) - 26 * sizeof(MCRegisterClass), |
| 1967 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[5]) - 26 * sizeof(MCRegisterClass), |
| 1968 | .LaneMask: LaneBitmask(0x0000000000000030), |
| 1969 | .AllocationPriority: 0, |
| 1970 | .GlobalPriority: false, |
| 1971 | .TSFlags: 0x00, /* TSFlags */ |
| 1972 | .SpillStackID: 0, /* SpillStackID */ |
| 1973 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1974 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1975 | offsetof(HexagonRegisterClassStorage, SuperClasses[17]) - 26 * sizeof(MCRegisterClass), |
| 1976 | .SuperClassesSize: 0 |
| 1977 | }, |
| 1978 | { |
| 1979 | offsetof(HexagonRegisterClassStorage, Regs[404]) - 27 * sizeof(MCRegisterClass), |
| 1980 | offsetof(HexagonRegisterClassStorage, BitSets[659]) - 27 * sizeof(MCRegisterClass), |
| 1981 | .NameIdx: 117, |
| 1982 | .RegSizeInBits: 0, |
| 1983 | .RegsSize: 16, |
| 1984 | .RegSetSize: 42, |
| 1985 | .ID: Hexagon::HvxWR_with_wsub_loRegClassID, |
| 1986 | .CopyCost: 1, /* CopyCost */ |
| 1987 | .Allocatable: true, /* Allocatable */ |
| 1988 | .BaseClass: false, |
| 1989 | offsetof(HexagonRegisterClassStorage, SubClassMasks[52]) - 27 * sizeof(MCRegisterClass), |
| 1990 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 27 * sizeof(MCRegisterClass), |
| 1991 | .LaneMask: LaneBitmask(0x0000000000000038), |
| 1992 | .AllocationPriority: 0, |
| 1993 | .GlobalPriority: false, |
| 1994 | .TSFlags: 0x00, /* TSFlags */ |
| 1995 | .SpillStackID: 0, /* SpillStackID */ |
| 1996 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 1997 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 1998 | offsetof(HexagonRegisterClassStorage, SuperClasses[17]) - 27 * sizeof(MCRegisterClass), |
| 1999 | .SuperClassesSize: 2 |
| 2000 | }, |
| 2001 | { |
| 2002 | offsetof(HexagonRegisterClassStorage, Regs[420]) - 28 * sizeof(MCRegisterClass), |
| 2003 | offsetof(HexagonRegisterClassStorage, BitSets[701]) - 28 * sizeof(MCRegisterClass), |
| 2004 | .NameIdx: 71, |
| 2005 | .RegSizeInBits: 0, |
| 2006 | .RegsSize: 8, |
| 2007 | .RegSetSize: 38, |
| 2008 | .ID: Hexagon::HvxVQRRegClassID, |
| 2009 | .CopyCost: 1, /* CopyCost */ |
| 2010 | .Allocatable: true, /* Allocatable */ |
| 2011 | .BaseClass: false, |
| 2012 | offsetof(HexagonRegisterClassStorage, SubClassMasks[53]) - 28 * sizeof(MCRegisterClass), |
| 2013 | offsetof(HexagonRegisterClassStorage, SuperRegIdxSeqs[2]) - 28 * sizeof(MCRegisterClass), |
| 2014 | .LaneMask: LaneBitmask(0x00000000000000F0), |
| 2015 | .AllocationPriority: 0, |
| 2016 | .GlobalPriority: false, |
| 2017 | .TSFlags: 0x00, /* TSFlags */ |
| 2018 | .SpillStackID: 0, /* SpillStackID */ |
| 2019 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2020 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2021 | offsetof(HexagonRegisterClassStorage, SuperClasses[19]) - 28 * sizeof(MCRegisterClass), |
| 2022 | .SuperClassesSize: 0 |
| 2023 | }, |
| 2024 | }, |
| 2025 | .Regs: { |
| 2026 | /* 0 */ Hexagon::USR_OVF, |
| 2027 | /* 1 */ Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID, Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1, Hexagon::SSR, Hexagon::CCR, Hexagon::HTID, Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11, Hexagon::S12, Hexagon::S13, Hexagon::S14, Hexagon::S15, Hexagon::S19, Hexagon::S23, Hexagon::S25, Hexagon::EVB, Hexagon::MODECTL, Hexagon::SYSCFG, Hexagon::S20, Hexagon::VID, Hexagon::S22, Hexagon::S24, Hexagon::S26, Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV, Hexagon::PCYCLEHI, Hexagon::PCYCLELO, Hexagon::ISDBST, Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35, Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1, Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT, Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44, Hexagon::S45, Hexagon::S46, Hexagon::S47, Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2, Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG, Hexagon::S54, Hexagon::S55, Hexagon::S56, Hexagon::S57, Hexagon::S58, Hexagon::S59, Hexagon::S60, Hexagon::S61, Hexagon::S62, Hexagon::S63, Hexagon::S64, Hexagon::S65, Hexagon::S66, Hexagon::S67, Hexagon::S68, Hexagon::S69, Hexagon::S70, Hexagon::S71, Hexagon::S72, Hexagon::S73, Hexagon::S74, Hexagon::S75, Hexagon::S76, Hexagon::S77, Hexagon::S78, Hexagon::S79, Hexagon::S80, |
| 2028 | /* 82 */ Hexagon::GELR, Hexagon::GSR, Hexagon::GOSP, Hexagon::G3, Hexagon::G4, Hexagon::G5, Hexagon::G6, Hexagon::G7, Hexagon::G8, Hexagon::G9, Hexagon::G10, Hexagon::G11, Hexagon::G12, Hexagon::G13, Hexagon::G14, Hexagon::G15, Hexagon::GPMUCNT4, Hexagon::GPMUCNT5, Hexagon::GPMUCNT6, Hexagon::GPMUCNT7, Hexagon::G20, Hexagon::G21, Hexagon::G22, Hexagon::G23, Hexagon::GPCYCLELO, Hexagon::GPCYCLEHI, Hexagon::GPMUCNT0, Hexagon::GPMUCNT1, Hexagon::GPMUCNT2, Hexagon::GPMUCNT3, Hexagon::G30, Hexagon::G31, |
| 2029 | /* 114 */ Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R10, Hexagon::R11, Hexagon::R29, Hexagon::R30, Hexagon::R31, |
| 2030 | /* 146 */ Hexagon::LC0, Hexagon::SA0, Hexagon::LC1, Hexagon::SA1, Hexagon::P3_0, Hexagon::C5, Hexagon::C8, Hexagon::PC, Hexagon::UGP, Hexagon::GP, Hexagon::CS0, Hexagon::CS1, Hexagon::UPCYCLELO, Hexagon::UPCYCLEHI, Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::M0, Hexagon::M1, Hexagon::USR, |
| 2031 | /* 169 */ Hexagon::R23, Hexagon::R22, Hexagon::R21, Hexagon::R20, Hexagon::R19, Hexagon::R18, Hexagon::R17, Hexagon::R16, Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0, |
| 2032 | /* 185 */ Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::C17_16, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::PKTCOUNT, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::UTIMER, |
| 2033 | /* 194 */ Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0, |
| 2034 | /* 202 */ Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, |
| 2035 | /* 208 */ Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3, |
| 2036 | /* 212 */ Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, |
| 2037 | /* 215 */ Hexagon::M0, Hexagon::M1, |
| 2038 | /* 217 */ Hexagon::USR, |
| 2039 | /* 218 */ Hexagon::VTMP, |
| 2040 | /* 219 */ Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6, Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14, Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22, Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30, Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38, Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46, Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54, Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62, Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70, Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78, |
| 2041 | /* 259 */ Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D6, Hexagon::D7, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::D5, Hexagon::D14, Hexagon::D15, |
| 2042 | /* 275 */ Hexagon::G1_0, Hexagon::G3_2, Hexagon::G5_4, Hexagon::G7_6, Hexagon::G9_8, Hexagon::G11_10, Hexagon::G13_12, Hexagon::G15_14, Hexagon::G17_16, Hexagon::G19_18, Hexagon::G21_20, Hexagon::G23_22, Hexagon::G25_24, Hexagon::G27_26, Hexagon::G29_28, Hexagon::G31_30, |
| 2043 | /* 291 */ Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15, |
| 2044 | /* 307 */ Hexagon::C1_0, Hexagon::C3_2, Hexagon::C5_4, Hexagon::C7_6, Hexagon::C9_8, Hexagon::C11_10, Hexagon::CS, Hexagon::UPCYCLE, Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, |
| 2045 | /* 318 */ Hexagon::D11, Hexagon::D10, Hexagon::D9, Hexagon::D8, Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0, |
| 2046 | /* 326 */ Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0, |
| 2047 | /* 330 */ Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, |
| 2048 | /* 333 */ Hexagon::C7_6, |
| 2049 | /* 334 */ Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3, |
| 2050 | /* 338 */ Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31, Hexagon::VTMP, |
| 2051 | /* 371 */ Hexagon::VTMP, |
| 2052 | /* 372 */ Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15, Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15, |
| 2053 | /* 404 */ Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15, |
| 2054 | /* 420 */ Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7, |
| 2055 | }, |
| 2056 | .BitSets: { |
| 2057 | /* 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, |
| 2058 | /* 6 */ 0xee, 0x00, 0xff, 0xc6, 0x0f, 0xa0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xc0, 0x03, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x33, |
| 2059 | /* 31 */ 0x00, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x0f, |
| 2060 | /* 44 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 2061 | /* 63 */ 0x00, 0x13, 0x00, 0x31, 0xd0, 0x19, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| 2062 | /* 108 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0xc0, 0x3f, |
| 2063 | /* 126 */ 0x00, 0x03, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 2064 | /* 169 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, |
| 2065 | /* 185 */ 0x00, 0x03, 0x00, 0x30, 0x00, 0x18, |
| 2066 | /* 191 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, |
| 2067 | /* 205 */ 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 2068 | /* 248 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, |
| 2069 | /* 262 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, |
| 2070 | /* 268 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| 2071 | /* 274 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0x3f, |
| 2072 | /* 324 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, |
| 2073 | /* 334 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, |
| 2074 | /* 379 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 2075 | /* 421 */ 0x10, 0x00, 0x00, 0x08, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, |
| 2076 | /* 464 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e, |
| 2077 | /* 473 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, |
| 2078 | /* 481 */ 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 2079 | /* 524 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, |
| 2080 | /* 567 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, |
| 2081 | /* 582 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 2082 | /* 611 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| 2083 | /* 617 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 2084 | /* 659 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 2085 | /* 701 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, |
| 2086 | }, |
| 2087 | .SubClassMasks: { |
| 2088 | // 0 UsrBits |
| 2089 | 0x00000001, |
| 2090 | 0x00001000, // subreg_overflow |
| 2091 | // 2 SysRegs |
| 2092 | 0x00000002, |
| 2093 | 0x00004000, // isub_hi |
| 2094 | 0x00004000, // isub_lo |
| 2095 | // 5 GuestRegs |
| 2096 | 0x00000004, |
| 2097 | 0x00010000, // isub_hi |
| 2098 | 0x00010000, // isub_lo |
| 2099 | // 8 IntRegs |
| 2100 | 0x000000a8, |
| 2101 | 0x00188000, // isub_hi |
| 2102 | 0x00188000, // isub_lo |
| 2103 | // 11 CtrRegs |
| 2104 | 0x00001910, |
| 2105 | 0x00640400, // isub_hi |
| 2106 | 0x00640400, // isub_lo |
| 2107 | // 14 GeneralSubRegs |
| 2108 | 0x000000a0, |
| 2109 | 0x00180000, // isub_hi |
| 2110 | 0x00180000, // isub_lo |
| 2111 | // 17 V62Regs |
| 2112 | 0x00200540, |
| 2113 | 0x00200400, // isub_hi |
| 2114 | 0x00200400, // isub_lo |
| 2115 | // 20 IntRegsLow8 |
| 2116 | 0x00000080, |
| 2117 | 0x00100000, // isub_hi |
| 2118 | 0x00100000, // isub_lo |
| 2119 | // 23 CtrRegs_and_V62Regs |
| 2120 | 0x00000100, |
| 2121 | 0x00200400, // isub_hi |
| 2122 | 0x00200400, // isub_lo |
| 2123 | // 26 PredRegs |
| 2124 | 0x00000200, |
| 2125 | // 27 V62Regs_with_isub_hi |
| 2126 | 0x00200400, |
| 2127 | // 28 ModRegs |
| 2128 | 0x00000800, |
| 2129 | 0x00400000, // isub_hi |
| 2130 | 0x00400000, // isub_lo |
| 2131 | // 31 CtrRegs_with_subreg_overflow |
| 2132 | 0x00001000, |
| 2133 | // 32 V65Regs |
| 2134 | 0x02002000, |
| 2135 | // 33 SysRegs64 |
| 2136 | 0x00004000, |
| 2137 | // 34 DoubleRegs |
| 2138 | 0x00188000, |
| 2139 | // 35 GuestRegs64 |
| 2140 | 0x00010000, |
| 2141 | // 36 VectRegRev |
| 2142 | 0x08020000, |
| 2143 | // 37 CtrRegs64 |
| 2144 | 0x00640000, |
| 2145 | // 38 GeneralDoubleLow8Regs |
| 2146 | 0x00180000, |
| 2147 | // 39 DoubleRegs_with_isub_hi_in_IntRegsLow8 |
| 2148 | 0x00100000, |
| 2149 | // 40 CtrRegs64_and_V62Regs |
| 2150 | 0x00200000, |
| 2151 | // 41 CtrRegs64_with_isub_hi_in_ModRegs |
| 2152 | 0x00400000, |
| 2153 | // 42 HvxQR |
| 2154 | 0x00800000, |
| 2155 | // 43 HvxVR |
| 2156 | 0x03000000, |
| 2157 | 0x1c020000, // vsub_hi |
| 2158 | 0x1c020000, // vsub_lo |
| 2159 | 0x10000000, // wsub_hi_then_vsub_hi |
| 2160 | 0x10000000, // wsub_hi_then_vsub_lo |
| 2161 | // 48 HvxVR_and_V65Regs |
| 2162 | 0x02000000, |
| 2163 | // 49 HvxWR |
| 2164 | 0x0c000000, |
| 2165 | 0x10000000, // wsub_hi |
| 2166 | 0x18020000, // wsub_lo |
| 2167 | // 52 HvxWR_with_wsub_lo |
| 2168 | 0x08000000, |
| 2169 | // 53 HvxVQR |
| 2170 | 0x10000000, |
| 2171 | }, |
| 2172 | .SuperRegIdxSeqs: { |
| 2173 | /* 0 */ 1, 2, 0, |
| 2174 | /* 3 */ 3, 0, |
| 2175 | /* 5 */ 7, 8, 0, |
| 2176 | /* 8 */ 5, 6, 9, 10, 0, |
| 2177 | }, |
| 2178 | .SuperClasses: { |
| 2179 | /* 0 UsrBits */ |
| 2180 | /* 0 SysRegs */ |
| 2181 | /* 0 GuestRegs */ |
| 2182 | /* 0 IntRegs */ |
| 2183 | /* 0 CtrRegs */ |
| 2184 | /* 0 GeneralSubRegs */ Hexagon::IntRegsRegClassID, |
| 2185 | /* 1 V62Regs */ |
| 2186 | /* 1 IntRegsLow8 */ Hexagon::IntRegsRegClassID, Hexagon::GeneralSubRegsRegClassID, |
| 2187 | /* 3 CtrRegs_and_V62Regs */ Hexagon::CtrRegsRegClassID, Hexagon::V62RegsRegClassID, |
| 2188 | /* 5 PredRegs */ |
| 2189 | /* 5 V62Regs_with_isub_hi */ Hexagon::V62RegsRegClassID, |
| 2190 | /* 6 ModRegs */ Hexagon::CtrRegsRegClassID, |
| 2191 | /* 7 CtrRegs_with_subreg_overflow */ Hexagon::CtrRegsRegClassID, |
| 2192 | /* 8 V65Regs */ |
| 2193 | /* 8 SysRegs64 */ |
| 2194 | /* 8 DoubleRegs */ |
| 2195 | /* 8 GuestRegs64 */ |
| 2196 | /* 8 VectRegRev */ |
| 2197 | /* 8 CtrRegs64 */ |
| 2198 | /* 8 GeneralDoubleLow8Regs */ Hexagon::DoubleRegsRegClassID, |
| 2199 | /* 9 DoubleRegs_with_isub_hi_in_IntRegsLow8 */ Hexagon::DoubleRegsRegClassID, Hexagon::GeneralDoubleLow8RegsRegClassID, |
| 2200 | /* 11 CtrRegs64_and_V62Regs */ Hexagon::V62RegsRegClassID, Hexagon::V62Regs_with_isub_hiRegClassID, Hexagon::CtrRegs64RegClassID, |
| 2201 | /* 14 CtrRegs64_with_isub_hi_in_ModRegs */ Hexagon::CtrRegs64RegClassID, |
| 2202 | /* 15 HvxQR */ |
| 2203 | /* 15 HvxVR */ |
| 2204 | /* 15 HvxVR_and_V65Regs */ Hexagon::V65RegsRegClassID, Hexagon::HvxVRRegClassID, |
| 2205 | /* 17 HvxWR */ |
| 2206 | /* 17 HvxWR_with_wsub_lo */ Hexagon::VectRegRevRegClassID, Hexagon::HvxWRRegClassID, |
| 2207 | /* 19 HvxVQR */ |
| 2208 | } |
| 2209 | }; |
| 2210 | |
| 2211 | const MCRegisterClass &getHexagonMCRegisterClass(unsigned RC) { |
| 2212 | return HexagonMCRegisterClassStorage.Classes[RC]; |
| 2213 | } |
| 2214 | |
| 2215 | // Hexagon Dwarf<->LLVM register mappings. |
| 2216 | extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[] = { |
| 2217 | { .FromReg: 0U, .ToReg: Hexagon::R0 }, |
| 2218 | { .FromReg: 1U, .ToReg: Hexagon::R1 }, |
| 2219 | { .FromReg: 2U, .ToReg: Hexagon::R2 }, |
| 2220 | { .FromReg: 3U, .ToReg: Hexagon::R3 }, |
| 2221 | { .FromReg: 4U, .ToReg: Hexagon::R4 }, |
| 2222 | { .FromReg: 5U, .ToReg: Hexagon::R5 }, |
| 2223 | { .FromReg: 6U, .ToReg: Hexagon::R6 }, |
| 2224 | { .FromReg: 7U, .ToReg: Hexagon::R7 }, |
| 2225 | { .FromReg: 8U, .ToReg: Hexagon::R8 }, |
| 2226 | { .FromReg: 9U, .ToReg: Hexagon::R9 }, |
| 2227 | { .FromReg: 10U, .ToReg: Hexagon::R10 }, |
| 2228 | { .FromReg: 11U, .ToReg: Hexagon::R11 }, |
| 2229 | { .FromReg: 12U, .ToReg: Hexagon::R12 }, |
| 2230 | { .FromReg: 13U, .ToReg: Hexagon::R13 }, |
| 2231 | { .FromReg: 14U, .ToReg: Hexagon::R14 }, |
| 2232 | { .FromReg: 15U, .ToReg: Hexagon::R15 }, |
| 2233 | { .FromReg: 16U, .ToReg: Hexagon::R16 }, |
| 2234 | { .FromReg: 17U, .ToReg: Hexagon::R17 }, |
| 2235 | { .FromReg: 18U, .ToReg: Hexagon::R18 }, |
| 2236 | { .FromReg: 19U, .ToReg: Hexagon::R19 }, |
| 2237 | { .FromReg: 20U, .ToReg: Hexagon::R20 }, |
| 2238 | { .FromReg: 21U, .ToReg: Hexagon::R21 }, |
| 2239 | { .FromReg: 22U, .ToReg: Hexagon::R22 }, |
| 2240 | { .FromReg: 23U, .ToReg: Hexagon::R23 }, |
| 2241 | { .FromReg: 24U, .ToReg: Hexagon::R24 }, |
| 2242 | { .FromReg: 25U, .ToReg: Hexagon::R25 }, |
| 2243 | { .FromReg: 26U, .ToReg: Hexagon::R26 }, |
| 2244 | { .FromReg: 27U, .ToReg: Hexagon::R27 }, |
| 2245 | { .FromReg: 28U, .ToReg: Hexagon::R28 }, |
| 2246 | { .FromReg: 29U, .ToReg: Hexagon::R29 }, |
| 2247 | { .FromReg: 30U, .ToReg: Hexagon::R30 }, |
| 2248 | { .FromReg: 31U, .ToReg: Hexagon::R31 }, |
| 2249 | { .FromReg: 32U, .ToReg: Hexagon::D0 }, |
| 2250 | { .FromReg: 34U, .ToReg: Hexagon::D1 }, |
| 2251 | { .FromReg: 36U, .ToReg: Hexagon::D2 }, |
| 2252 | { .FromReg: 38U, .ToReg: Hexagon::D3 }, |
| 2253 | { .FromReg: 40U, .ToReg: Hexagon::D4 }, |
| 2254 | { .FromReg: 42U, .ToReg: Hexagon::D5 }, |
| 2255 | { .FromReg: 44U, .ToReg: Hexagon::D6 }, |
| 2256 | { .FromReg: 46U, .ToReg: Hexagon::D7 }, |
| 2257 | { .FromReg: 48U, .ToReg: Hexagon::D8 }, |
| 2258 | { .FromReg: 50U, .ToReg: Hexagon::D9 }, |
| 2259 | { .FromReg: 52U, .ToReg: Hexagon::D10 }, |
| 2260 | { .FromReg: 54U, .ToReg: Hexagon::D11 }, |
| 2261 | { .FromReg: 56U, .ToReg: Hexagon::D12 }, |
| 2262 | { .FromReg: 58U, .ToReg: Hexagon::D13 }, |
| 2263 | { .FromReg: 60U, .ToReg: Hexagon::D14 }, |
| 2264 | { .FromReg: 62U, .ToReg: Hexagon::D15 }, |
| 2265 | { .FromReg: 63U, .ToReg: Hexagon::P0 }, |
| 2266 | { .FromReg: 64U, .ToReg: Hexagon::P1 }, |
| 2267 | { .FromReg: 65U, .ToReg: Hexagon::P2 }, |
| 2268 | { .FromReg: 66U, .ToReg: Hexagon::P3 }, |
| 2269 | { .FromReg: 67U, .ToReg: Hexagon::C1_0 }, |
| 2270 | { .FromReg: 68U, .ToReg: Hexagon::LC0 }, |
| 2271 | { .FromReg: 69U, .ToReg: Hexagon::C3_2 }, |
| 2272 | { .FromReg: 70U, .ToReg: Hexagon::LC1 }, |
| 2273 | { .FromReg: 71U, .ToReg: Hexagon::P3_0 }, |
| 2274 | { .FromReg: 72U, .ToReg: Hexagon::C7_6 }, |
| 2275 | { .FromReg: 73U, .ToReg: Hexagon::M0 }, |
| 2276 | { .FromReg: 74U, .ToReg: Hexagon::C9_8 }, |
| 2277 | { .FromReg: 75U, .ToReg: Hexagon::C8 }, |
| 2278 | { .FromReg: 76U, .ToReg: Hexagon::C11_10 }, |
| 2279 | { .FromReg: 77U, .ToReg: Hexagon::UGP }, |
| 2280 | { .FromReg: 78U, .ToReg: Hexagon::GP }, |
| 2281 | { .FromReg: 79U, .ToReg: Hexagon::CS0 }, |
| 2282 | { .FromReg: 80U, .ToReg: Hexagon::CS1 }, |
| 2283 | { .FromReg: 81U, .ToReg: Hexagon::UPCYCLELO }, |
| 2284 | { .FromReg: 82U, .ToReg: Hexagon::UPCYCLEHI }, |
| 2285 | { .FromReg: 83U, .ToReg: Hexagon::C17_16 }, |
| 2286 | { .FromReg: 84U, .ToReg: Hexagon::FRAMEKEY }, |
| 2287 | { .FromReg: 85U, .ToReg: Hexagon::PKTCOUNTLO }, |
| 2288 | { .FromReg: 86U, .ToReg: Hexagon::PKTCOUNTHI }, |
| 2289 | { .FromReg: 97U, .ToReg: Hexagon::UTIMERLO }, |
| 2290 | { .FromReg: 98U, .ToReg: Hexagon::UTIMERHI }, |
| 2291 | { .FromReg: 99U, .ToReg: Hexagon::W0 }, |
| 2292 | { .FromReg: 100U, .ToReg: Hexagon::V1 }, |
| 2293 | { .FromReg: 101U, .ToReg: Hexagon::W1 }, |
| 2294 | { .FromReg: 102U, .ToReg: Hexagon::V3 }, |
| 2295 | { .FromReg: 103U, .ToReg: Hexagon::W2 }, |
| 2296 | { .FromReg: 104U, .ToReg: Hexagon::V5 }, |
| 2297 | { .FromReg: 105U, .ToReg: Hexagon::W3 }, |
| 2298 | { .FromReg: 106U, .ToReg: Hexagon::V7 }, |
| 2299 | { .FromReg: 107U, .ToReg: Hexagon::W4 }, |
| 2300 | { .FromReg: 108U, .ToReg: Hexagon::V9 }, |
| 2301 | { .FromReg: 109U, .ToReg: Hexagon::W5 }, |
| 2302 | { .FromReg: 110U, .ToReg: Hexagon::V11 }, |
| 2303 | { .FromReg: 111U, .ToReg: Hexagon::W6 }, |
| 2304 | { .FromReg: 112U, .ToReg: Hexagon::V13 }, |
| 2305 | { .FromReg: 113U, .ToReg: Hexagon::W7 }, |
| 2306 | { .FromReg: 114U, .ToReg: Hexagon::V15 }, |
| 2307 | { .FromReg: 115U, .ToReg: Hexagon::W8 }, |
| 2308 | { .FromReg: 116U, .ToReg: Hexagon::V17 }, |
| 2309 | { .FromReg: 117U, .ToReg: Hexagon::W9 }, |
| 2310 | { .FromReg: 118U, .ToReg: Hexagon::V19 }, |
| 2311 | { .FromReg: 119U, .ToReg: Hexagon::W10 }, |
| 2312 | { .FromReg: 120U, .ToReg: Hexagon::V21 }, |
| 2313 | { .FromReg: 121U, .ToReg: Hexagon::W11 }, |
| 2314 | { .FromReg: 122U, .ToReg: Hexagon::V23 }, |
| 2315 | { .FromReg: 123U, .ToReg: Hexagon::W12 }, |
| 2316 | { .FromReg: 124U, .ToReg: Hexagon::V25 }, |
| 2317 | { .FromReg: 125U, .ToReg: Hexagon::W13 }, |
| 2318 | { .FromReg: 126U, .ToReg: Hexagon::V27 }, |
| 2319 | { .FromReg: 127U, .ToReg: Hexagon::W14 }, |
| 2320 | { .FromReg: 128U, .ToReg: Hexagon::V29 }, |
| 2321 | { .FromReg: 129U, .ToReg: Hexagon::W15 }, |
| 2322 | { .FromReg: 130U, .ToReg: Hexagon::V31 }, |
| 2323 | { .FromReg: 131U, .ToReg: Hexagon::Q0 }, |
| 2324 | { .FromReg: 132U, .ToReg: Hexagon::Q1 }, |
| 2325 | { .FromReg: 133U, .ToReg: Hexagon::Q2 }, |
| 2326 | { .FromReg: 134U, .ToReg: Hexagon::Q3 }, |
| 2327 | { .FromReg: 144U, .ToReg: Hexagon::SGP1_0 }, |
| 2328 | { .FromReg: 145U, .ToReg: Hexagon::SGP1 }, |
| 2329 | { .FromReg: 146U, .ToReg: Hexagon::S3_2 }, |
| 2330 | { .FromReg: 147U, .ToReg: Hexagon::ELR }, |
| 2331 | { .FromReg: 148U, .ToReg: Hexagon::S5_4 }, |
| 2332 | { .FromReg: 149U, .ToReg: Hexagon::BADVA1 }, |
| 2333 | { .FromReg: 150U, .ToReg: Hexagon::S7_6 }, |
| 2334 | { .FromReg: 151U, .ToReg: Hexagon::CCR }, |
| 2335 | { .FromReg: 152U, .ToReg: Hexagon::S9_8 }, |
| 2336 | { .FromReg: 153U, .ToReg: Hexagon::BADVA }, |
| 2337 | { .FromReg: 154U, .ToReg: Hexagon::S11_10 }, |
| 2338 | { .FromReg: 155U, .ToReg: Hexagon::S11 }, |
| 2339 | { .FromReg: 156U, .ToReg: Hexagon::S13_12 }, |
| 2340 | { .FromReg: 157U, .ToReg: Hexagon::S13 }, |
| 2341 | { .FromReg: 158U, .ToReg: Hexagon::S15_14 }, |
| 2342 | { .FromReg: 159U, .ToReg: Hexagon::S15 }, |
| 2343 | { .FromReg: 160U, .ToReg: Hexagon::S17_16 }, |
| 2344 | { .FromReg: 161U, .ToReg: Hexagon::WR0 }, |
| 2345 | { .FromReg: 162U, .ToReg: Hexagon::S19_18 }, |
| 2346 | { .FromReg: 163U, .ToReg: Hexagon::WR2 }, |
| 2347 | { .FromReg: 164U, .ToReg: Hexagon::S21_20 }, |
| 2348 | { .FromReg: 165U, .ToReg: Hexagon::WR4 }, |
| 2349 | { .FromReg: 166U, .ToReg: Hexagon::S23_22 }, |
| 2350 | { .FromReg: 167U, .ToReg: Hexagon::WR6 }, |
| 2351 | { .FromReg: 168U, .ToReg: Hexagon::S25_24 }, |
| 2352 | { .FromReg: 169U, .ToReg: Hexagon::WR8 }, |
| 2353 | { .FromReg: 170U, .ToReg: Hexagon::S27_26 }, |
| 2354 | { .FromReg: 171U, .ToReg: Hexagon::WR10 }, |
| 2355 | { .FromReg: 172U, .ToReg: Hexagon::S29_28 }, |
| 2356 | { .FromReg: 173U, .ToReg: Hexagon::WR12 }, |
| 2357 | { .FromReg: 174U, .ToReg: Hexagon::S31_30 }, |
| 2358 | { .FromReg: 175U, .ToReg: Hexagon::WR14 }, |
| 2359 | { .FromReg: 176U, .ToReg: Hexagon::S33_32 }, |
| 2360 | { .FromReg: 177U, .ToReg: Hexagon::ISDBCFG0 }, |
| 2361 | { .FromReg: 178U, .ToReg: Hexagon::S35_34 }, |
| 2362 | { .FromReg: 179U, .ToReg: Hexagon::S35 }, |
| 2363 | { .FromReg: 180U, .ToReg: Hexagon::S37_36 }, |
| 2364 | { .FromReg: 181U, .ToReg: Hexagon::BRKPTCFG0 }, |
| 2365 | { .FromReg: 182U, .ToReg: Hexagon::S39_38 }, |
| 2366 | { .FromReg: 183U, .ToReg: Hexagon::BRKPTCFG1 }, |
| 2367 | { .FromReg: 184U, .ToReg: Hexagon::S41_40 }, |
| 2368 | { .FromReg: 185U, .ToReg: Hexagon::ISDBMBXOUT }, |
| 2369 | { .FromReg: 186U, .ToReg: Hexagon::S43_42 }, |
| 2370 | { .FromReg: 187U, .ToReg: Hexagon::ISDBGPR }, |
| 2371 | { .FromReg: 188U, .ToReg: Hexagon::S45_44 }, |
| 2372 | { .FromReg: 189U, .ToReg: Hexagon::S45 }, |
| 2373 | { .FromReg: 190U, .ToReg: Hexagon::S47_46 }, |
| 2374 | { .FromReg: 191U, .ToReg: Hexagon::S47 }, |
| 2375 | { .FromReg: 192U, .ToReg: Hexagon::S49_48 }, |
| 2376 | { .FromReg: 193U, .ToReg: Hexagon::PMUCNT1 }, |
| 2377 | { .FromReg: 194U, .ToReg: Hexagon::S51_50 }, |
| 2378 | { .FromReg: 195U, .ToReg: Hexagon::PMUCNT3 }, |
| 2379 | { .FromReg: 196U, .ToReg: Hexagon::S53_52 }, |
| 2380 | { .FromReg: 197U, .ToReg: Hexagon::PMUCFG }, |
| 2381 | { .FromReg: 198U, .ToReg: Hexagon::S55_54 }, |
| 2382 | { .FromReg: 199U, .ToReg: Hexagon::S55 }, |
| 2383 | { .FromReg: 200U, .ToReg: Hexagon::S57_56 }, |
| 2384 | { .FromReg: 201U, .ToReg: Hexagon::S57 }, |
| 2385 | { .FromReg: 202U, .ToReg: Hexagon::S59_58 }, |
| 2386 | { .FromReg: 203U, .ToReg: Hexagon::S59 }, |
| 2387 | { .FromReg: 204U, .ToReg: Hexagon::S61_60 }, |
| 2388 | { .FromReg: 205U, .ToReg: Hexagon::S61 }, |
| 2389 | { .FromReg: 206U, .ToReg: Hexagon::S63_62 }, |
| 2390 | { .FromReg: 207U, .ToReg: Hexagon::S63 }, |
| 2391 | { .FromReg: 208U, .ToReg: Hexagon::S65_64 }, |
| 2392 | { .FromReg: 209U, .ToReg: Hexagon::S65 }, |
| 2393 | { .FromReg: 210U, .ToReg: Hexagon::S67_66 }, |
| 2394 | { .FromReg: 211U, .ToReg: Hexagon::S67 }, |
| 2395 | { .FromReg: 212U, .ToReg: Hexagon::S69_68 }, |
| 2396 | { .FromReg: 213U, .ToReg: Hexagon::S69 }, |
| 2397 | { .FromReg: 214U, .ToReg: Hexagon::S71_70 }, |
| 2398 | { .FromReg: 215U, .ToReg: Hexagon::S71 }, |
| 2399 | { .FromReg: 216U, .ToReg: Hexagon::S73_72 }, |
| 2400 | { .FromReg: 217U, .ToReg: Hexagon::S73 }, |
| 2401 | { .FromReg: 218U, .ToReg: Hexagon::S75_74 }, |
| 2402 | { .FromReg: 219U, .ToReg: Hexagon::S77_76 }, |
| 2403 | { .FromReg: 220U, .ToReg: Hexagon::S79_78 }, |
| 2404 | { .FromReg: 221U, .ToReg: Hexagon::S77 }, |
| 2405 | { .FromReg: 222U, .ToReg: Hexagon::G3_2 }, |
| 2406 | { .FromReg: 223U, .ToReg: Hexagon::S79 }, |
| 2407 | { .FromReg: 224U, .ToReg: Hexagon::G5_4 }, |
| 2408 | { .FromReg: 225U, .ToReg: Hexagon::G5 }, |
| 2409 | { .FromReg: 226U, .ToReg: Hexagon::G7_6 }, |
| 2410 | { .FromReg: 227U, .ToReg: Hexagon::G7 }, |
| 2411 | { .FromReg: 228U, .ToReg: Hexagon::G9_8 }, |
| 2412 | { .FromReg: 229U, .ToReg: Hexagon::G9 }, |
| 2413 | { .FromReg: 230U, .ToReg: Hexagon::G11_10 }, |
| 2414 | { .FromReg: 231U, .ToReg: Hexagon::G11 }, |
| 2415 | { .FromReg: 232U, .ToReg: Hexagon::G13_12 }, |
| 2416 | { .FromReg: 233U, .ToReg: Hexagon::G13 }, |
| 2417 | { .FromReg: 234U, .ToReg: Hexagon::G15_14 }, |
| 2418 | { .FromReg: 235U, .ToReg: Hexagon::G15 }, |
| 2419 | { .FromReg: 236U, .ToReg: Hexagon::G17_16 }, |
| 2420 | { .FromReg: 237U, .ToReg: Hexagon::GPMUCNT5 }, |
| 2421 | { .FromReg: 238U, .ToReg: Hexagon::G19_18 }, |
| 2422 | { .FromReg: 239U, .ToReg: Hexagon::GPMUCNT7 }, |
| 2423 | { .FromReg: 240U, .ToReg: Hexagon::G21_20 }, |
| 2424 | { .FromReg: 241U, .ToReg: Hexagon::G21 }, |
| 2425 | { .FromReg: 242U, .ToReg: Hexagon::G23_22 }, |
| 2426 | { .FromReg: 243U, .ToReg: Hexagon::G23 }, |
| 2427 | { .FromReg: 244U, .ToReg: Hexagon::G25_24 }, |
| 2428 | { .FromReg: 245U, .ToReg: Hexagon::GPCYCLEHI }, |
| 2429 | { .FromReg: 246U, .ToReg: Hexagon::G27_26 }, |
| 2430 | { .FromReg: 247U, .ToReg: Hexagon::GPMUCNT1 }, |
| 2431 | { .FromReg: 248U, .ToReg: Hexagon::G29_28 }, |
| 2432 | { .FromReg: 249U, .ToReg: Hexagon::GPMUCNT3 }, |
| 2433 | { .FromReg: 250U, .ToReg: Hexagon::G31_30 }, |
| 2434 | { .FromReg: 251U, .ToReg: Hexagon::G31 }, |
| 2435 | { .FromReg: 252U, .ToReg: Hexagon::VQ0 }, |
| 2436 | { .FromReg: 253U, .ToReg: Hexagon::VQ1 }, |
| 2437 | { .FromReg: 254U, .ToReg: Hexagon::VQ2 }, |
| 2438 | { .FromReg: 255U, .ToReg: Hexagon::VQ3 }, |
| 2439 | { .FromReg: 256U, .ToReg: Hexagon::VQ4 }, |
| 2440 | { .FromReg: 257U, .ToReg: Hexagon::VQ5 }, |
| 2441 | { .FromReg: 258U, .ToReg: Hexagon::VQ6 }, |
| 2442 | { .FromReg: 259U, .ToReg: Hexagon::VQ7 }, |
| 2443 | { .FromReg: 999999U, .ToReg: Hexagon::VF0 }, |
| 2444 | { .FromReg: 1000000U, .ToReg: Hexagon::VF1 }, |
| 2445 | { .FromReg: 1000001U, .ToReg: Hexagon::VF2 }, |
| 2446 | { .FromReg: 1000002U, .ToReg: Hexagon::VF3 }, |
| 2447 | { .FromReg: 1000003U, .ToReg: Hexagon::VF4 }, |
| 2448 | { .FromReg: 1000004U, .ToReg: Hexagon::VF5 }, |
| 2449 | { .FromReg: 1000005U, .ToReg: Hexagon::VF6 }, |
| 2450 | { .FromReg: 1000006U, .ToReg: Hexagon::VF7 }, |
| 2451 | { .FromReg: 1000007U, .ToReg: Hexagon::VF8 }, |
| 2452 | { .FromReg: 1000008U, .ToReg: Hexagon::VF9 }, |
| 2453 | { .FromReg: 1000009U, .ToReg: Hexagon::VF10 }, |
| 2454 | { .FromReg: 1000010U, .ToReg: Hexagon::VF11 }, |
| 2455 | { .FromReg: 1000011U, .ToReg: Hexagon::VF12 }, |
| 2456 | { .FromReg: 1000012U, .ToReg: Hexagon::VF13 }, |
| 2457 | { .FromReg: 1000013U, .ToReg: Hexagon::VF14 }, |
| 2458 | { .FromReg: 1000014U, .ToReg: Hexagon::VF15 }, |
| 2459 | { .FromReg: 1000015U, .ToReg: Hexagon::VF16 }, |
| 2460 | { .FromReg: 1000016U, .ToReg: Hexagon::VF17 }, |
| 2461 | { .FromReg: 1000017U, .ToReg: Hexagon::VF18 }, |
| 2462 | { .FromReg: 1000018U, .ToReg: Hexagon::VF19 }, |
| 2463 | { .FromReg: 1000019U, .ToReg: Hexagon::VF20 }, |
| 2464 | { .FromReg: 1000020U, .ToReg: Hexagon::VF21 }, |
| 2465 | { .FromReg: 1000021U, .ToReg: Hexagon::VF22 }, |
| 2466 | { .FromReg: 1000022U, .ToReg: Hexagon::VF23 }, |
| 2467 | { .FromReg: 1000023U, .ToReg: Hexagon::VF24 }, |
| 2468 | { .FromReg: 1000024U, .ToReg: Hexagon::VF25 }, |
| 2469 | { .FromReg: 1000025U, .ToReg: Hexagon::VF26 }, |
| 2470 | { .FromReg: 1000026U, .ToReg: Hexagon::VF27 }, |
| 2471 | { .FromReg: 1000027U, .ToReg: Hexagon::VF28 }, |
| 2472 | { .FromReg: 1000028U, .ToReg: Hexagon::VF29 }, |
| 2473 | { .FromReg: 1000029U, .ToReg: Hexagon::VF30 }, |
| 2474 | { .FromReg: 1000030U, .ToReg: Hexagon::VF31 }, |
| 2475 | { .FromReg: 9999999U, .ToReg: Hexagon::VFR0 }, |
| 2476 | { .FromReg: 10000000U, .ToReg: Hexagon::VFR1 }, |
| 2477 | { .FromReg: 10000001U, .ToReg: Hexagon::VFR2 }, |
| 2478 | { .FromReg: 10000002U, .ToReg: Hexagon::VFR3 }, |
| 2479 | { .FromReg: 10000003U, .ToReg: Hexagon::VFR4 }, |
| 2480 | { .FromReg: 10000004U, .ToReg: Hexagon::VFR5 }, |
| 2481 | { .FromReg: 10000005U, .ToReg: Hexagon::VFR6 }, |
| 2482 | { .FromReg: 10000006U, .ToReg: Hexagon::VFR7 }, |
| 2483 | { .FromReg: 10000007U, .ToReg: Hexagon::VFR8 }, |
| 2484 | { .FromReg: 10000008U, .ToReg: Hexagon::VFR9 }, |
| 2485 | { .FromReg: 10000009U, .ToReg: Hexagon::VFR10 }, |
| 2486 | { .FromReg: 10000010U, .ToReg: Hexagon::VFR11 }, |
| 2487 | { .FromReg: 10000011U, .ToReg: Hexagon::VFR12 }, |
| 2488 | { .FromReg: 10000012U, .ToReg: Hexagon::VFR13 }, |
| 2489 | { .FromReg: 10000013U, .ToReg: Hexagon::VFR14 }, |
| 2490 | { .FromReg: 10000014U, .ToReg: Hexagon::VFR15 }, |
| 2491 | { .FromReg: 10000015U, .ToReg: Hexagon::VFR16 }, |
| 2492 | { .FromReg: 10000016U, .ToReg: Hexagon::VFR17 }, |
| 2493 | { .FromReg: 10000017U, .ToReg: Hexagon::VFR18 }, |
| 2494 | { .FromReg: 10000018U, .ToReg: Hexagon::VFR19 }, |
| 2495 | { .FromReg: 10000019U, .ToReg: Hexagon::VFR20 }, |
| 2496 | { .FromReg: 10000020U, .ToReg: Hexagon::VFR21 }, |
| 2497 | { .FromReg: 10000021U, .ToReg: Hexagon::VFR22 }, |
| 2498 | { .FromReg: 10000022U, .ToReg: Hexagon::VFR23 }, |
| 2499 | { .FromReg: 10000023U, .ToReg: Hexagon::VFR24 }, |
| 2500 | { .FromReg: 10000024U, .ToReg: Hexagon::VFR25 }, |
| 2501 | { .FromReg: 10000025U, .ToReg: Hexagon::VFR26 }, |
| 2502 | { .FromReg: 10000026U, .ToReg: Hexagon::VFR27 }, |
| 2503 | { .FromReg: 10000027U, .ToReg: Hexagon::VFR28 }, |
| 2504 | { .FromReg: 10000028U, .ToReg: Hexagon::VFR29 }, |
| 2505 | { .FromReg: 10000029U, .ToReg: Hexagon::VFR30 }, |
| 2506 | { .FromReg: 10000030U, .ToReg: Hexagon::VFR31 }, |
| 2507 | }; |
| 2508 | extern const unsigned HexagonDwarfFlavour0Dwarf2LSize = std::size(HexagonDwarfFlavour0Dwarf2L); |
| 2509 | |
| 2510 | extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[] = { |
| 2511 | { .FromReg: 0U, .ToReg: Hexagon::R0 }, |
| 2512 | { .FromReg: 1U, .ToReg: Hexagon::R1 }, |
| 2513 | { .FromReg: 2U, .ToReg: Hexagon::R2 }, |
| 2514 | { .FromReg: 3U, .ToReg: Hexagon::R3 }, |
| 2515 | { .FromReg: 4U, .ToReg: Hexagon::R4 }, |
| 2516 | { .FromReg: 5U, .ToReg: Hexagon::R5 }, |
| 2517 | { .FromReg: 6U, .ToReg: Hexagon::R6 }, |
| 2518 | { .FromReg: 7U, .ToReg: Hexagon::R7 }, |
| 2519 | { .FromReg: 8U, .ToReg: Hexagon::R8 }, |
| 2520 | { .FromReg: 9U, .ToReg: Hexagon::R9 }, |
| 2521 | { .FromReg: 10U, .ToReg: Hexagon::R10 }, |
| 2522 | { .FromReg: 11U, .ToReg: Hexagon::R11 }, |
| 2523 | { .FromReg: 12U, .ToReg: Hexagon::R12 }, |
| 2524 | { .FromReg: 13U, .ToReg: Hexagon::R13 }, |
| 2525 | { .FromReg: 14U, .ToReg: Hexagon::R14 }, |
| 2526 | { .FromReg: 15U, .ToReg: Hexagon::R15 }, |
| 2527 | { .FromReg: 16U, .ToReg: Hexagon::R16 }, |
| 2528 | { .FromReg: 17U, .ToReg: Hexagon::R17 }, |
| 2529 | { .FromReg: 18U, .ToReg: Hexagon::R18 }, |
| 2530 | { .FromReg: 19U, .ToReg: Hexagon::R19 }, |
| 2531 | { .FromReg: 20U, .ToReg: Hexagon::R20 }, |
| 2532 | { .FromReg: 21U, .ToReg: Hexagon::R21 }, |
| 2533 | { .FromReg: 22U, .ToReg: Hexagon::R22 }, |
| 2534 | { .FromReg: 23U, .ToReg: Hexagon::R23 }, |
| 2535 | { .FromReg: 24U, .ToReg: Hexagon::R24 }, |
| 2536 | { .FromReg: 25U, .ToReg: Hexagon::R25 }, |
| 2537 | { .FromReg: 26U, .ToReg: Hexagon::R26 }, |
| 2538 | { .FromReg: 27U, .ToReg: Hexagon::R27 }, |
| 2539 | { .FromReg: 28U, .ToReg: Hexagon::R28 }, |
| 2540 | { .FromReg: 29U, .ToReg: Hexagon::R29 }, |
| 2541 | { .FromReg: 30U, .ToReg: Hexagon::R30 }, |
| 2542 | { .FromReg: 31U, .ToReg: Hexagon::R31 }, |
| 2543 | { .FromReg: 32U, .ToReg: Hexagon::D0 }, |
| 2544 | { .FromReg: 34U, .ToReg: Hexagon::D1 }, |
| 2545 | { .FromReg: 36U, .ToReg: Hexagon::D2 }, |
| 2546 | { .FromReg: 38U, .ToReg: Hexagon::D3 }, |
| 2547 | { .FromReg: 40U, .ToReg: Hexagon::D4 }, |
| 2548 | { .FromReg: 42U, .ToReg: Hexagon::D5 }, |
| 2549 | { .FromReg: 44U, .ToReg: Hexagon::D6 }, |
| 2550 | { .FromReg: 46U, .ToReg: Hexagon::D7 }, |
| 2551 | { .FromReg: 48U, .ToReg: Hexagon::D8 }, |
| 2552 | { .FromReg: 50U, .ToReg: Hexagon::D9 }, |
| 2553 | { .FromReg: 52U, .ToReg: Hexagon::D10 }, |
| 2554 | { .FromReg: 54U, .ToReg: Hexagon::D11 }, |
| 2555 | { .FromReg: 56U, .ToReg: Hexagon::D12 }, |
| 2556 | { .FromReg: 58U, .ToReg: Hexagon::D13 }, |
| 2557 | { .FromReg: 60U, .ToReg: Hexagon::D14 }, |
| 2558 | { .FromReg: 62U, .ToReg: Hexagon::D15 }, |
| 2559 | { .FromReg: 63U, .ToReg: Hexagon::P0 }, |
| 2560 | { .FromReg: 64U, .ToReg: Hexagon::P1 }, |
| 2561 | { .FromReg: 65U, .ToReg: Hexagon::P2 }, |
| 2562 | { .FromReg: 66U, .ToReg: Hexagon::P3 }, |
| 2563 | { .FromReg: 67U, .ToReg: Hexagon::C1_0 }, |
| 2564 | { .FromReg: 68U, .ToReg: Hexagon::LC0 }, |
| 2565 | { .FromReg: 69U, .ToReg: Hexagon::C3_2 }, |
| 2566 | { .FromReg: 70U, .ToReg: Hexagon::LC1 }, |
| 2567 | { .FromReg: 71U, .ToReg: Hexagon::P3_0 }, |
| 2568 | { .FromReg: 72U, .ToReg: Hexagon::C7_6 }, |
| 2569 | { .FromReg: 73U, .ToReg: Hexagon::M0 }, |
| 2570 | { .FromReg: 74U, .ToReg: Hexagon::C9_8 }, |
| 2571 | { .FromReg: 75U, .ToReg: Hexagon::C8 }, |
| 2572 | { .FromReg: 76U, .ToReg: Hexagon::C11_10 }, |
| 2573 | { .FromReg: 77U, .ToReg: Hexagon::UGP }, |
| 2574 | { .FromReg: 78U, .ToReg: Hexagon::GP }, |
| 2575 | { .FromReg: 79U, .ToReg: Hexagon::CS0 }, |
| 2576 | { .FromReg: 80U, .ToReg: Hexagon::CS1 }, |
| 2577 | { .FromReg: 81U, .ToReg: Hexagon::UPCYCLELO }, |
| 2578 | { .FromReg: 82U, .ToReg: Hexagon::UPCYCLEHI }, |
| 2579 | { .FromReg: 83U, .ToReg: Hexagon::C17_16 }, |
| 2580 | { .FromReg: 84U, .ToReg: Hexagon::FRAMEKEY }, |
| 2581 | { .FromReg: 85U, .ToReg: Hexagon::PKTCOUNTLO }, |
| 2582 | { .FromReg: 86U, .ToReg: Hexagon::PKTCOUNTHI }, |
| 2583 | { .FromReg: 97U, .ToReg: Hexagon::UTIMERLO }, |
| 2584 | { .FromReg: 98U, .ToReg: Hexagon::UTIMERHI }, |
| 2585 | { .FromReg: 99U, .ToReg: Hexagon::W0 }, |
| 2586 | { .FromReg: 100U, .ToReg: Hexagon::V1 }, |
| 2587 | { .FromReg: 101U, .ToReg: Hexagon::W1 }, |
| 2588 | { .FromReg: 102U, .ToReg: Hexagon::V3 }, |
| 2589 | { .FromReg: 103U, .ToReg: Hexagon::W2 }, |
| 2590 | { .FromReg: 104U, .ToReg: Hexagon::V5 }, |
| 2591 | { .FromReg: 105U, .ToReg: Hexagon::W3 }, |
| 2592 | { .FromReg: 106U, .ToReg: Hexagon::V7 }, |
| 2593 | { .FromReg: 107U, .ToReg: Hexagon::W4 }, |
| 2594 | { .FromReg: 108U, .ToReg: Hexagon::V9 }, |
| 2595 | { .FromReg: 109U, .ToReg: Hexagon::W5 }, |
| 2596 | { .FromReg: 110U, .ToReg: Hexagon::V11 }, |
| 2597 | { .FromReg: 111U, .ToReg: Hexagon::W6 }, |
| 2598 | { .FromReg: 112U, .ToReg: Hexagon::V13 }, |
| 2599 | { .FromReg: 113U, .ToReg: Hexagon::W7 }, |
| 2600 | { .FromReg: 114U, .ToReg: Hexagon::V15 }, |
| 2601 | { .FromReg: 115U, .ToReg: Hexagon::W8 }, |
| 2602 | { .FromReg: 116U, .ToReg: Hexagon::V17 }, |
| 2603 | { .FromReg: 117U, .ToReg: Hexagon::W9 }, |
| 2604 | { .FromReg: 118U, .ToReg: Hexagon::V19 }, |
| 2605 | { .FromReg: 119U, .ToReg: Hexagon::W10 }, |
| 2606 | { .FromReg: 120U, .ToReg: Hexagon::V21 }, |
| 2607 | { .FromReg: 121U, .ToReg: Hexagon::W11 }, |
| 2608 | { .FromReg: 122U, .ToReg: Hexagon::V23 }, |
| 2609 | { .FromReg: 123U, .ToReg: Hexagon::W12 }, |
| 2610 | { .FromReg: 124U, .ToReg: Hexagon::V25 }, |
| 2611 | { .FromReg: 125U, .ToReg: Hexagon::W13 }, |
| 2612 | { .FromReg: 126U, .ToReg: Hexagon::V27 }, |
| 2613 | { .FromReg: 127U, .ToReg: Hexagon::W14 }, |
| 2614 | { .FromReg: 128U, .ToReg: Hexagon::V29 }, |
| 2615 | { .FromReg: 129U, .ToReg: Hexagon::W15 }, |
| 2616 | { .FromReg: 130U, .ToReg: Hexagon::V31 }, |
| 2617 | { .FromReg: 131U, .ToReg: Hexagon::Q0 }, |
| 2618 | { .FromReg: 132U, .ToReg: Hexagon::Q1 }, |
| 2619 | { .FromReg: 133U, .ToReg: Hexagon::Q2 }, |
| 2620 | { .FromReg: 134U, .ToReg: Hexagon::Q3 }, |
| 2621 | { .FromReg: 144U, .ToReg: Hexagon::SGP1_0 }, |
| 2622 | { .FromReg: 145U, .ToReg: Hexagon::SGP1 }, |
| 2623 | { .FromReg: 146U, .ToReg: Hexagon::S3_2 }, |
| 2624 | { .FromReg: 147U, .ToReg: Hexagon::ELR }, |
| 2625 | { .FromReg: 148U, .ToReg: Hexagon::S5_4 }, |
| 2626 | { .FromReg: 149U, .ToReg: Hexagon::BADVA1 }, |
| 2627 | { .FromReg: 150U, .ToReg: Hexagon::S7_6 }, |
| 2628 | { .FromReg: 151U, .ToReg: Hexagon::CCR }, |
| 2629 | { .FromReg: 152U, .ToReg: Hexagon::S9_8 }, |
| 2630 | { .FromReg: 153U, .ToReg: Hexagon::BADVA }, |
| 2631 | { .FromReg: 154U, .ToReg: Hexagon::S11_10 }, |
| 2632 | { .FromReg: 155U, .ToReg: Hexagon::S11 }, |
| 2633 | { .FromReg: 156U, .ToReg: Hexagon::S13_12 }, |
| 2634 | { .FromReg: 157U, .ToReg: Hexagon::S13 }, |
| 2635 | { .FromReg: 158U, .ToReg: Hexagon::S15_14 }, |
| 2636 | { .FromReg: 159U, .ToReg: Hexagon::S15 }, |
| 2637 | { .FromReg: 160U, .ToReg: Hexagon::S17_16 }, |
| 2638 | { .FromReg: 161U, .ToReg: Hexagon::WR0 }, |
| 2639 | { .FromReg: 162U, .ToReg: Hexagon::S19_18 }, |
| 2640 | { .FromReg: 163U, .ToReg: Hexagon::WR2 }, |
| 2641 | { .FromReg: 164U, .ToReg: Hexagon::S21_20 }, |
| 2642 | { .FromReg: 165U, .ToReg: Hexagon::WR4 }, |
| 2643 | { .FromReg: 166U, .ToReg: Hexagon::S23_22 }, |
| 2644 | { .FromReg: 167U, .ToReg: Hexagon::WR6 }, |
| 2645 | { .FromReg: 168U, .ToReg: Hexagon::S25_24 }, |
| 2646 | { .FromReg: 169U, .ToReg: Hexagon::WR8 }, |
| 2647 | { .FromReg: 170U, .ToReg: Hexagon::S27_26 }, |
| 2648 | { .FromReg: 171U, .ToReg: Hexagon::WR10 }, |
| 2649 | { .FromReg: 172U, .ToReg: Hexagon::S29_28 }, |
| 2650 | { .FromReg: 173U, .ToReg: Hexagon::WR12 }, |
| 2651 | { .FromReg: 174U, .ToReg: Hexagon::S31_30 }, |
| 2652 | { .FromReg: 175U, .ToReg: Hexagon::WR14 }, |
| 2653 | { .FromReg: 176U, .ToReg: Hexagon::S33_32 }, |
| 2654 | { .FromReg: 177U, .ToReg: Hexagon::ISDBCFG0 }, |
| 2655 | { .FromReg: 178U, .ToReg: Hexagon::S35_34 }, |
| 2656 | { .FromReg: 179U, .ToReg: Hexagon::S35 }, |
| 2657 | { .FromReg: 180U, .ToReg: Hexagon::S37_36 }, |
| 2658 | { .FromReg: 181U, .ToReg: Hexagon::BRKPTCFG0 }, |
| 2659 | { .FromReg: 182U, .ToReg: Hexagon::S39_38 }, |
| 2660 | { .FromReg: 183U, .ToReg: Hexagon::BRKPTCFG1 }, |
| 2661 | { .FromReg: 184U, .ToReg: Hexagon::S41_40 }, |
| 2662 | { .FromReg: 185U, .ToReg: Hexagon::ISDBMBXOUT }, |
| 2663 | { .FromReg: 186U, .ToReg: Hexagon::S43_42 }, |
| 2664 | { .FromReg: 187U, .ToReg: Hexagon::ISDBGPR }, |
| 2665 | { .FromReg: 188U, .ToReg: Hexagon::S45_44 }, |
| 2666 | { .FromReg: 189U, .ToReg: Hexagon::S45 }, |
| 2667 | { .FromReg: 190U, .ToReg: Hexagon::S47_46 }, |
| 2668 | { .FromReg: 191U, .ToReg: Hexagon::S47 }, |
| 2669 | { .FromReg: 192U, .ToReg: Hexagon::S49_48 }, |
| 2670 | { .FromReg: 193U, .ToReg: Hexagon::PMUCNT1 }, |
| 2671 | { .FromReg: 194U, .ToReg: Hexagon::S51_50 }, |
| 2672 | { .FromReg: 195U, .ToReg: Hexagon::PMUCNT3 }, |
| 2673 | { .FromReg: 196U, .ToReg: Hexagon::S53_52 }, |
| 2674 | { .FromReg: 197U, .ToReg: Hexagon::PMUCFG }, |
| 2675 | { .FromReg: 198U, .ToReg: Hexagon::S55_54 }, |
| 2676 | { .FromReg: 199U, .ToReg: Hexagon::S55 }, |
| 2677 | { .FromReg: 200U, .ToReg: Hexagon::S57_56 }, |
| 2678 | { .FromReg: 201U, .ToReg: Hexagon::S57 }, |
| 2679 | { .FromReg: 202U, .ToReg: Hexagon::S59_58 }, |
| 2680 | { .FromReg: 203U, .ToReg: Hexagon::S59 }, |
| 2681 | { .FromReg: 204U, .ToReg: Hexagon::S61_60 }, |
| 2682 | { .FromReg: 205U, .ToReg: Hexagon::S61 }, |
| 2683 | { .FromReg: 206U, .ToReg: Hexagon::S63_62 }, |
| 2684 | { .FromReg: 207U, .ToReg: Hexagon::S63 }, |
| 2685 | { .FromReg: 208U, .ToReg: Hexagon::S65_64 }, |
| 2686 | { .FromReg: 209U, .ToReg: Hexagon::S65 }, |
| 2687 | { .FromReg: 210U, .ToReg: Hexagon::S67_66 }, |
| 2688 | { .FromReg: 211U, .ToReg: Hexagon::S67 }, |
| 2689 | { .FromReg: 212U, .ToReg: Hexagon::S69_68 }, |
| 2690 | { .FromReg: 213U, .ToReg: Hexagon::S69 }, |
| 2691 | { .FromReg: 214U, .ToReg: Hexagon::S71_70 }, |
| 2692 | { .FromReg: 215U, .ToReg: Hexagon::S71 }, |
| 2693 | { .FromReg: 216U, .ToReg: Hexagon::S73_72 }, |
| 2694 | { .FromReg: 217U, .ToReg: Hexagon::S73 }, |
| 2695 | { .FromReg: 218U, .ToReg: Hexagon::S75_74 }, |
| 2696 | { .FromReg: 219U, .ToReg: Hexagon::S77_76 }, |
| 2697 | { .FromReg: 220U, .ToReg: Hexagon::S79_78 }, |
| 2698 | { .FromReg: 221U, .ToReg: Hexagon::S77 }, |
| 2699 | { .FromReg: 222U, .ToReg: Hexagon::G3_2 }, |
| 2700 | { .FromReg: 223U, .ToReg: Hexagon::S79 }, |
| 2701 | { .FromReg: 224U, .ToReg: Hexagon::G5_4 }, |
| 2702 | { .FromReg: 225U, .ToReg: Hexagon::G5 }, |
| 2703 | { .FromReg: 226U, .ToReg: Hexagon::G7_6 }, |
| 2704 | { .FromReg: 227U, .ToReg: Hexagon::G7 }, |
| 2705 | { .FromReg: 228U, .ToReg: Hexagon::G9_8 }, |
| 2706 | { .FromReg: 229U, .ToReg: Hexagon::G9 }, |
| 2707 | { .FromReg: 230U, .ToReg: Hexagon::G11_10 }, |
| 2708 | { .FromReg: 231U, .ToReg: Hexagon::G11 }, |
| 2709 | { .FromReg: 232U, .ToReg: Hexagon::G13_12 }, |
| 2710 | { .FromReg: 233U, .ToReg: Hexagon::G13 }, |
| 2711 | { .FromReg: 234U, .ToReg: Hexagon::G15_14 }, |
| 2712 | { .FromReg: 235U, .ToReg: Hexagon::G15 }, |
| 2713 | { .FromReg: 236U, .ToReg: Hexagon::G17_16 }, |
| 2714 | { .FromReg: 237U, .ToReg: Hexagon::GPMUCNT5 }, |
| 2715 | { .FromReg: 238U, .ToReg: Hexagon::G19_18 }, |
| 2716 | { .FromReg: 239U, .ToReg: Hexagon::GPMUCNT7 }, |
| 2717 | { .FromReg: 240U, .ToReg: Hexagon::G21_20 }, |
| 2718 | { .FromReg: 241U, .ToReg: Hexagon::G21 }, |
| 2719 | { .FromReg: 242U, .ToReg: Hexagon::G23_22 }, |
| 2720 | { .FromReg: 243U, .ToReg: Hexagon::G23 }, |
| 2721 | { .FromReg: 244U, .ToReg: Hexagon::G25_24 }, |
| 2722 | { .FromReg: 245U, .ToReg: Hexagon::GPCYCLEHI }, |
| 2723 | { .FromReg: 246U, .ToReg: Hexagon::G27_26 }, |
| 2724 | { .FromReg: 247U, .ToReg: Hexagon::GPMUCNT1 }, |
| 2725 | { .FromReg: 248U, .ToReg: Hexagon::G29_28 }, |
| 2726 | { .FromReg: 249U, .ToReg: Hexagon::GPMUCNT3 }, |
| 2727 | { .FromReg: 250U, .ToReg: Hexagon::G31_30 }, |
| 2728 | { .FromReg: 251U, .ToReg: Hexagon::G31 }, |
| 2729 | { .FromReg: 252U, .ToReg: Hexagon::VQ0 }, |
| 2730 | { .FromReg: 253U, .ToReg: Hexagon::VQ1 }, |
| 2731 | { .FromReg: 254U, .ToReg: Hexagon::VQ2 }, |
| 2732 | { .FromReg: 255U, .ToReg: Hexagon::VQ3 }, |
| 2733 | { .FromReg: 256U, .ToReg: Hexagon::VQ4 }, |
| 2734 | { .FromReg: 257U, .ToReg: Hexagon::VQ5 }, |
| 2735 | { .FromReg: 258U, .ToReg: Hexagon::VQ6 }, |
| 2736 | { .FromReg: 259U, .ToReg: Hexagon::VQ7 }, |
| 2737 | { .FromReg: 999999U, .ToReg: Hexagon::VF0 }, |
| 2738 | { .FromReg: 1000000U, .ToReg: Hexagon::VF1 }, |
| 2739 | { .FromReg: 1000001U, .ToReg: Hexagon::VF2 }, |
| 2740 | { .FromReg: 1000002U, .ToReg: Hexagon::VF3 }, |
| 2741 | { .FromReg: 1000003U, .ToReg: Hexagon::VF4 }, |
| 2742 | { .FromReg: 1000004U, .ToReg: Hexagon::VF5 }, |
| 2743 | { .FromReg: 1000005U, .ToReg: Hexagon::VF6 }, |
| 2744 | { .FromReg: 1000006U, .ToReg: Hexagon::VF7 }, |
| 2745 | { .FromReg: 1000007U, .ToReg: Hexagon::VF8 }, |
| 2746 | { .FromReg: 1000008U, .ToReg: Hexagon::VF9 }, |
| 2747 | { .FromReg: 1000009U, .ToReg: Hexagon::VF10 }, |
| 2748 | { .FromReg: 1000010U, .ToReg: Hexagon::VF11 }, |
| 2749 | { .FromReg: 1000011U, .ToReg: Hexagon::VF12 }, |
| 2750 | { .FromReg: 1000012U, .ToReg: Hexagon::VF13 }, |
| 2751 | { .FromReg: 1000013U, .ToReg: Hexagon::VF14 }, |
| 2752 | { .FromReg: 1000014U, .ToReg: Hexagon::VF15 }, |
| 2753 | { .FromReg: 1000015U, .ToReg: Hexagon::VF16 }, |
| 2754 | { .FromReg: 1000016U, .ToReg: Hexagon::VF17 }, |
| 2755 | { .FromReg: 1000017U, .ToReg: Hexagon::VF18 }, |
| 2756 | { .FromReg: 1000018U, .ToReg: Hexagon::VF19 }, |
| 2757 | { .FromReg: 1000019U, .ToReg: Hexagon::VF20 }, |
| 2758 | { .FromReg: 1000020U, .ToReg: Hexagon::VF21 }, |
| 2759 | { .FromReg: 1000021U, .ToReg: Hexagon::VF22 }, |
| 2760 | { .FromReg: 1000022U, .ToReg: Hexagon::VF23 }, |
| 2761 | { .FromReg: 1000023U, .ToReg: Hexagon::VF24 }, |
| 2762 | { .FromReg: 1000024U, .ToReg: Hexagon::VF25 }, |
| 2763 | { .FromReg: 1000025U, .ToReg: Hexagon::VF26 }, |
| 2764 | { .FromReg: 1000026U, .ToReg: Hexagon::VF27 }, |
| 2765 | { .FromReg: 1000027U, .ToReg: Hexagon::VF28 }, |
| 2766 | { .FromReg: 1000028U, .ToReg: Hexagon::VF29 }, |
| 2767 | { .FromReg: 1000029U, .ToReg: Hexagon::VF30 }, |
| 2768 | { .FromReg: 1000030U, .ToReg: Hexagon::VF31 }, |
| 2769 | { .FromReg: 9999999U, .ToReg: Hexagon::VFR0 }, |
| 2770 | { .FromReg: 10000000U, .ToReg: Hexagon::VFR1 }, |
| 2771 | { .FromReg: 10000001U, .ToReg: Hexagon::VFR2 }, |
| 2772 | { .FromReg: 10000002U, .ToReg: Hexagon::VFR3 }, |
| 2773 | { .FromReg: 10000003U, .ToReg: Hexagon::VFR4 }, |
| 2774 | { .FromReg: 10000004U, .ToReg: Hexagon::VFR5 }, |
| 2775 | { .FromReg: 10000005U, .ToReg: Hexagon::VFR6 }, |
| 2776 | { .FromReg: 10000006U, .ToReg: Hexagon::VFR7 }, |
| 2777 | { .FromReg: 10000007U, .ToReg: Hexagon::VFR8 }, |
| 2778 | { .FromReg: 10000008U, .ToReg: Hexagon::VFR9 }, |
| 2779 | { .FromReg: 10000009U, .ToReg: Hexagon::VFR10 }, |
| 2780 | { .FromReg: 10000010U, .ToReg: Hexagon::VFR11 }, |
| 2781 | { .FromReg: 10000011U, .ToReg: Hexagon::VFR12 }, |
| 2782 | { .FromReg: 10000012U, .ToReg: Hexagon::VFR13 }, |
| 2783 | { .FromReg: 10000013U, .ToReg: Hexagon::VFR14 }, |
| 2784 | { .FromReg: 10000014U, .ToReg: Hexagon::VFR15 }, |
| 2785 | { .FromReg: 10000015U, .ToReg: Hexagon::VFR16 }, |
| 2786 | { .FromReg: 10000016U, .ToReg: Hexagon::VFR17 }, |
| 2787 | { .FromReg: 10000017U, .ToReg: Hexagon::VFR18 }, |
| 2788 | { .FromReg: 10000018U, .ToReg: Hexagon::VFR19 }, |
| 2789 | { .FromReg: 10000019U, .ToReg: Hexagon::VFR20 }, |
| 2790 | { .FromReg: 10000020U, .ToReg: Hexagon::VFR21 }, |
| 2791 | { .FromReg: 10000021U, .ToReg: Hexagon::VFR22 }, |
| 2792 | { .FromReg: 10000022U, .ToReg: Hexagon::VFR23 }, |
| 2793 | { .FromReg: 10000023U, .ToReg: Hexagon::VFR24 }, |
| 2794 | { .FromReg: 10000024U, .ToReg: Hexagon::VFR25 }, |
| 2795 | { .FromReg: 10000025U, .ToReg: Hexagon::VFR26 }, |
| 2796 | { .FromReg: 10000026U, .ToReg: Hexagon::VFR27 }, |
| 2797 | { .FromReg: 10000027U, .ToReg: Hexagon::VFR28 }, |
| 2798 | { .FromReg: 10000028U, .ToReg: Hexagon::VFR29 }, |
| 2799 | { .FromReg: 10000029U, .ToReg: Hexagon::VFR30 }, |
| 2800 | { .FromReg: 10000030U, .ToReg: Hexagon::VFR31 }, |
| 2801 | }; |
| 2802 | extern const unsigned HexagonEHFlavour0Dwarf2LSize = std::size(HexagonEHFlavour0Dwarf2L); |
| 2803 | |
| 2804 | extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[] = { |
| 2805 | { .FromReg: Hexagon::BADVA, .ToReg: 153U }, |
| 2806 | { .FromReg: Hexagon::CCR, .ToReg: 151U }, |
| 2807 | { .FromReg: Hexagon::CFGBASE, .ToReg: 171U }, |
| 2808 | { .FromReg: Hexagon::CS, .ToReg: 78U }, |
| 2809 | { .FromReg: Hexagon::DIAG, .ToReg: 172U }, |
| 2810 | { .FromReg: Hexagon::ELR, .ToReg: 147U }, |
| 2811 | { .FromReg: Hexagon::EVB, .ToReg: 160U }, |
| 2812 | { .FromReg: Hexagon::FRAMEKEY, .ToReg: 84U }, |
| 2813 | { .FromReg: Hexagon::FRAMELIMIT, .ToReg: 83U }, |
| 2814 | { .FromReg: Hexagon::GELR, .ToReg: 220U }, |
| 2815 | { .FromReg: Hexagon::GOSP, .ToReg: 222U }, |
| 2816 | { .FromReg: Hexagon::GP, .ToReg: 78U }, |
| 2817 | { .FromReg: Hexagon::GPCYCLEHI, .ToReg: 245U }, |
| 2818 | { .FromReg: Hexagon::GPCYCLELO, .ToReg: 244U }, |
| 2819 | { .FromReg: Hexagon::GSR, .ToReg: 221U }, |
| 2820 | { .FromReg: Hexagon::HTID, .ToReg: 152U }, |
| 2821 | { .FromReg: Hexagon::IMASK, .ToReg: 154U }, |
| 2822 | { .FromReg: Hexagon::ISDBEN, .ToReg: 186U }, |
| 2823 | { .FromReg: Hexagon::ISDBGPR, .ToReg: 187U }, |
| 2824 | { .FromReg: Hexagon::ISDBMBXIN, .ToReg: 184U }, |
| 2825 | { .FromReg: Hexagon::ISDBMBXOUT, .ToReg: 185U }, |
| 2826 | { .FromReg: Hexagon::ISDBST, .ToReg: 176U }, |
| 2827 | { .FromReg: Hexagon::MODECTL, .ToReg: 161U }, |
| 2828 | { .FromReg: Hexagon::PC, .ToReg: 76U }, |
| 2829 | { .FromReg: Hexagon::PCYCLEHI, .ToReg: 175U }, |
| 2830 | { .FromReg: Hexagon::PCYCLELO, .ToReg: 174U }, |
| 2831 | { .FromReg: Hexagon::PKTCOUNT, .ToReg: 85U }, |
| 2832 | { .FromReg: Hexagon::PKTCOUNTHI, .ToReg: 86U }, |
| 2833 | { .FromReg: Hexagon::PKTCOUNTLO, .ToReg: 85U }, |
| 2834 | { .FromReg: Hexagon::PMUCFG, .ToReg: 197U }, |
| 2835 | { .FromReg: Hexagon::PMUEVTCFG, .ToReg: 196U }, |
| 2836 | { .FromReg: Hexagon::REV, .ToReg: 173U }, |
| 2837 | { .FromReg: Hexagon::SSR, .ToReg: 150U }, |
| 2838 | { .FromReg: Hexagon::STID, .ToReg: 146U }, |
| 2839 | { .FromReg: Hexagon::SYSCFG, .ToReg: 162U }, |
| 2840 | { .FromReg: Hexagon::UGP, .ToReg: 77U }, |
| 2841 | { .FromReg: Hexagon::UPCYCLE, .ToReg: 80U }, |
| 2842 | { .FromReg: Hexagon::UPCYCLEHI, .ToReg: 82U }, |
| 2843 | { .FromReg: Hexagon::UPCYCLELO, .ToReg: 81U }, |
| 2844 | { .FromReg: Hexagon::USR, .ToReg: 75U }, |
| 2845 | { .FromReg: Hexagon::UTIMER, .ToReg: 97U }, |
| 2846 | { .FromReg: Hexagon::UTIMERHI, .ToReg: 98U }, |
| 2847 | { .FromReg: Hexagon::UTIMERLO, .ToReg: 97U }, |
| 2848 | { .FromReg: Hexagon::VID, .ToReg: 165U }, |
| 2849 | { .FromReg: Hexagon::VTMP, .ToReg: 131U }, |
| 2850 | { .FromReg: Hexagon::BADVA0, .ToReg: 148U }, |
| 2851 | { .FromReg: Hexagon::BADVA1, .ToReg: 149U }, |
| 2852 | { .FromReg: Hexagon::BRKPTCFG0, .ToReg: 181U }, |
| 2853 | { .FromReg: Hexagon::BRKPTCFG1, .ToReg: 183U }, |
| 2854 | { .FromReg: Hexagon::BRKPTPC0, .ToReg: 180U }, |
| 2855 | { .FromReg: Hexagon::BRKPTPC1, .ToReg: 182U }, |
| 2856 | { .FromReg: Hexagon::C5, .ToReg: 72U }, |
| 2857 | { .FromReg: Hexagon::C8, .ToReg: 75U }, |
| 2858 | { .FromReg: Hexagon::CS0, .ToReg: 79U }, |
| 2859 | { .FromReg: Hexagon::CS1, .ToReg: 80U }, |
| 2860 | { .FromReg: Hexagon::D0, .ToReg: 32U }, |
| 2861 | { .FromReg: Hexagon::D1, .ToReg: 34U }, |
| 2862 | { .FromReg: Hexagon::D2, .ToReg: 36U }, |
| 2863 | { .FromReg: Hexagon::D3, .ToReg: 38U }, |
| 2864 | { .FromReg: Hexagon::D4, .ToReg: 40U }, |
| 2865 | { .FromReg: Hexagon::D5, .ToReg: 42U }, |
| 2866 | { .FromReg: Hexagon::D6, .ToReg: 44U }, |
| 2867 | { .FromReg: Hexagon::D7, .ToReg: 46U }, |
| 2868 | { .FromReg: Hexagon::D8, .ToReg: 48U }, |
| 2869 | { .FromReg: Hexagon::D9, .ToReg: 50U }, |
| 2870 | { .FromReg: Hexagon::D10, .ToReg: 52U }, |
| 2871 | { .FromReg: Hexagon::D11, .ToReg: 54U }, |
| 2872 | { .FromReg: Hexagon::D12, .ToReg: 56U }, |
| 2873 | { .FromReg: Hexagon::D13, .ToReg: 58U }, |
| 2874 | { .FromReg: Hexagon::D14, .ToReg: 60U }, |
| 2875 | { .FromReg: Hexagon::D15, .ToReg: 62U }, |
| 2876 | { .FromReg: Hexagon::G3, .ToReg: 223U }, |
| 2877 | { .FromReg: Hexagon::G4, .ToReg: 224U }, |
| 2878 | { .FromReg: Hexagon::G5, .ToReg: 225U }, |
| 2879 | { .FromReg: Hexagon::G6, .ToReg: 226U }, |
| 2880 | { .FromReg: Hexagon::G7, .ToReg: 227U }, |
| 2881 | { .FromReg: Hexagon::G8, .ToReg: 228U }, |
| 2882 | { .FromReg: Hexagon::G9, .ToReg: 229U }, |
| 2883 | { .FromReg: Hexagon::G10, .ToReg: 230U }, |
| 2884 | { .FromReg: Hexagon::G11, .ToReg: 231U }, |
| 2885 | { .FromReg: Hexagon::G12, .ToReg: 232U }, |
| 2886 | { .FromReg: Hexagon::G13, .ToReg: 233U }, |
| 2887 | { .FromReg: Hexagon::G14, .ToReg: 234U }, |
| 2888 | { .FromReg: Hexagon::G15, .ToReg: 235U }, |
| 2889 | { .FromReg: Hexagon::G20, .ToReg: 240U }, |
| 2890 | { .FromReg: Hexagon::G21, .ToReg: 241U }, |
| 2891 | { .FromReg: Hexagon::G22, .ToReg: 242U }, |
| 2892 | { .FromReg: Hexagon::G23, .ToReg: 243U }, |
| 2893 | { .FromReg: Hexagon::G30, .ToReg: 250U }, |
| 2894 | { .FromReg: Hexagon::G31, .ToReg: 251U }, |
| 2895 | { .FromReg: Hexagon::GPMUCNT0, .ToReg: 246U }, |
| 2896 | { .FromReg: Hexagon::GPMUCNT1, .ToReg: 247U }, |
| 2897 | { .FromReg: Hexagon::GPMUCNT2, .ToReg: 248U }, |
| 2898 | { .FromReg: Hexagon::GPMUCNT3, .ToReg: 249U }, |
| 2899 | { .FromReg: Hexagon::GPMUCNT4, .ToReg: 236U }, |
| 2900 | { .FromReg: Hexagon::GPMUCNT5, .ToReg: 237U }, |
| 2901 | { .FromReg: Hexagon::GPMUCNT6, .ToReg: 238U }, |
| 2902 | { .FromReg: Hexagon::GPMUCNT7, .ToReg: 239U }, |
| 2903 | { .FromReg: Hexagon::ISDBCFG0, .ToReg: 177U }, |
| 2904 | { .FromReg: Hexagon::ISDBCFG1, .ToReg: 178U }, |
| 2905 | { .FromReg: Hexagon::LC0, .ToReg: 68U }, |
| 2906 | { .FromReg: Hexagon::LC1, .ToReg: 70U }, |
| 2907 | { .FromReg: Hexagon::M0, .ToReg: 73U }, |
| 2908 | { .FromReg: Hexagon::M1, .ToReg: 74U }, |
| 2909 | { .FromReg: Hexagon::P0, .ToReg: 63U }, |
| 2910 | { .FromReg: Hexagon::P1, .ToReg: 64U }, |
| 2911 | { .FromReg: Hexagon::P2, .ToReg: 65U }, |
| 2912 | { .FromReg: Hexagon::P3, .ToReg: 66U }, |
| 2913 | { .FromReg: Hexagon::PMUCNT0, .ToReg: 192U }, |
| 2914 | { .FromReg: Hexagon::PMUCNT1, .ToReg: 193U }, |
| 2915 | { .FromReg: Hexagon::PMUCNT2, .ToReg: 194U }, |
| 2916 | { .FromReg: Hexagon::PMUCNT3, .ToReg: 195U }, |
| 2917 | { .FromReg: Hexagon::Q0, .ToReg: 131U }, |
| 2918 | { .FromReg: Hexagon::Q1, .ToReg: 132U }, |
| 2919 | { .FromReg: Hexagon::Q2, .ToReg: 133U }, |
| 2920 | { .FromReg: Hexagon::Q3, .ToReg: 134U }, |
| 2921 | { .FromReg: Hexagon::R0, .ToReg: 0U }, |
| 2922 | { .FromReg: Hexagon::R1, .ToReg: 1U }, |
| 2923 | { .FromReg: Hexagon::R2, .ToReg: 2U }, |
| 2924 | { .FromReg: Hexagon::R3, .ToReg: 3U }, |
| 2925 | { .FromReg: Hexagon::R4, .ToReg: 4U }, |
| 2926 | { .FromReg: Hexagon::R5, .ToReg: 5U }, |
| 2927 | { .FromReg: Hexagon::R6, .ToReg: 6U }, |
| 2928 | { .FromReg: Hexagon::R7, .ToReg: 7U }, |
| 2929 | { .FromReg: Hexagon::R8, .ToReg: 8U }, |
| 2930 | { .FromReg: Hexagon::R9, .ToReg: 9U }, |
| 2931 | { .FromReg: Hexagon::R10, .ToReg: 10U }, |
| 2932 | { .FromReg: Hexagon::R11, .ToReg: 11U }, |
| 2933 | { .FromReg: Hexagon::R12, .ToReg: 12U }, |
| 2934 | { .FromReg: Hexagon::R13, .ToReg: 13U }, |
| 2935 | { .FromReg: Hexagon::R14, .ToReg: 14U }, |
| 2936 | { .FromReg: Hexagon::R15, .ToReg: 15U }, |
| 2937 | { .FromReg: Hexagon::R16, .ToReg: 16U }, |
| 2938 | { .FromReg: Hexagon::R17, .ToReg: 17U }, |
| 2939 | { .FromReg: Hexagon::R18, .ToReg: 18U }, |
| 2940 | { .FromReg: Hexagon::R19, .ToReg: 19U }, |
| 2941 | { .FromReg: Hexagon::R20, .ToReg: 20U }, |
| 2942 | { .FromReg: Hexagon::R21, .ToReg: 21U }, |
| 2943 | { .FromReg: Hexagon::R22, .ToReg: 22U }, |
| 2944 | { .FromReg: Hexagon::R23, .ToReg: 23U }, |
| 2945 | { .FromReg: Hexagon::R24, .ToReg: 24U }, |
| 2946 | { .FromReg: Hexagon::R25, .ToReg: 25U }, |
| 2947 | { .FromReg: Hexagon::R26, .ToReg: 26U }, |
| 2948 | { .FromReg: Hexagon::R27, .ToReg: 27U }, |
| 2949 | { .FromReg: Hexagon::R28, .ToReg: 28U }, |
| 2950 | { .FromReg: Hexagon::R29, .ToReg: 29U }, |
| 2951 | { .FromReg: Hexagon::R30, .ToReg: 30U }, |
| 2952 | { .FromReg: Hexagon::R31, .ToReg: 31U }, |
| 2953 | { .FromReg: Hexagon::S11, .ToReg: 155U }, |
| 2954 | { .FromReg: Hexagon::S12, .ToReg: 156U }, |
| 2955 | { .FromReg: Hexagon::S13, .ToReg: 157U }, |
| 2956 | { .FromReg: Hexagon::S14, .ToReg: 158U }, |
| 2957 | { .FromReg: Hexagon::S15, .ToReg: 159U }, |
| 2958 | { .FromReg: Hexagon::S19, .ToReg: 163U }, |
| 2959 | { .FromReg: Hexagon::S20, .ToReg: 164U }, |
| 2960 | { .FromReg: Hexagon::S22, .ToReg: 166U }, |
| 2961 | { .FromReg: Hexagon::S23, .ToReg: 167U }, |
| 2962 | { .FromReg: Hexagon::S24, .ToReg: 168U }, |
| 2963 | { .FromReg: Hexagon::S25, .ToReg: 169U }, |
| 2964 | { .FromReg: Hexagon::S26, .ToReg: 170U }, |
| 2965 | { .FromReg: Hexagon::S35, .ToReg: 179U }, |
| 2966 | { .FromReg: Hexagon::S44, .ToReg: 188U }, |
| 2967 | { .FromReg: Hexagon::S45, .ToReg: 189U }, |
| 2968 | { .FromReg: Hexagon::S46, .ToReg: 190U }, |
| 2969 | { .FromReg: Hexagon::S47, .ToReg: 191U }, |
| 2970 | { .FromReg: Hexagon::S54, .ToReg: 198U }, |
| 2971 | { .FromReg: Hexagon::S55, .ToReg: 199U }, |
| 2972 | { .FromReg: Hexagon::S56, .ToReg: 200U }, |
| 2973 | { .FromReg: Hexagon::S57, .ToReg: 201U }, |
| 2974 | { .FromReg: Hexagon::S58, .ToReg: 202U }, |
| 2975 | { .FromReg: Hexagon::S59, .ToReg: 203U }, |
| 2976 | { .FromReg: Hexagon::S60, .ToReg: 204U }, |
| 2977 | { .FromReg: Hexagon::S61, .ToReg: 205U }, |
| 2978 | { .FromReg: Hexagon::S62, .ToReg: 206U }, |
| 2979 | { .FromReg: Hexagon::S63, .ToReg: 207U }, |
| 2980 | { .FromReg: Hexagon::S64, .ToReg: 208U }, |
| 2981 | { .FromReg: Hexagon::S65, .ToReg: 209U }, |
| 2982 | { .FromReg: Hexagon::S66, .ToReg: 210U }, |
| 2983 | { .FromReg: Hexagon::S67, .ToReg: 211U }, |
| 2984 | { .FromReg: Hexagon::S68, .ToReg: 212U }, |
| 2985 | { .FromReg: Hexagon::S69, .ToReg: 213U }, |
| 2986 | { .FromReg: Hexagon::S70, .ToReg: 214U }, |
| 2987 | { .FromReg: Hexagon::S71, .ToReg: 215U }, |
| 2988 | { .FromReg: Hexagon::S72, .ToReg: 216U }, |
| 2989 | { .FromReg: Hexagon::S73, .ToReg: 217U }, |
| 2990 | { .FromReg: Hexagon::S74, .ToReg: 218U }, |
| 2991 | { .FromReg: Hexagon::S75, .ToReg: 219U }, |
| 2992 | { .FromReg: Hexagon::S76, .ToReg: 220U }, |
| 2993 | { .FromReg: Hexagon::S77, .ToReg: 221U }, |
| 2994 | { .FromReg: Hexagon::S78, .ToReg: 222U }, |
| 2995 | { .FromReg: Hexagon::S79, .ToReg: 223U }, |
| 2996 | { .FromReg: Hexagon::S80, .ToReg: 224U }, |
| 2997 | { .FromReg: Hexagon::SA0, .ToReg: 67U }, |
| 2998 | { .FromReg: Hexagon::SA1, .ToReg: 69U }, |
| 2999 | { .FromReg: Hexagon::SGP0, .ToReg: 144U }, |
| 3000 | { .FromReg: Hexagon::SGP1, .ToReg: 145U }, |
| 3001 | { .FromReg: Hexagon::V0, .ToReg: 99U }, |
| 3002 | { .FromReg: Hexagon::V1, .ToReg: 100U }, |
| 3003 | { .FromReg: Hexagon::V2, .ToReg: 101U }, |
| 3004 | { .FromReg: Hexagon::V3, .ToReg: 102U }, |
| 3005 | { .FromReg: Hexagon::V4, .ToReg: 103U }, |
| 3006 | { .FromReg: Hexagon::V5, .ToReg: 104U }, |
| 3007 | { .FromReg: Hexagon::V6, .ToReg: 105U }, |
| 3008 | { .FromReg: Hexagon::V7, .ToReg: 106U }, |
| 3009 | { .FromReg: Hexagon::V8, .ToReg: 107U }, |
| 3010 | { .FromReg: Hexagon::V9, .ToReg: 108U }, |
| 3011 | { .FromReg: Hexagon::V10, .ToReg: 109U }, |
| 3012 | { .FromReg: Hexagon::V11, .ToReg: 110U }, |
| 3013 | { .FromReg: Hexagon::V12, .ToReg: 111U }, |
| 3014 | { .FromReg: Hexagon::V13, .ToReg: 112U }, |
| 3015 | { .FromReg: Hexagon::V14, .ToReg: 113U }, |
| 3016 | { .FromReg: Hexagon::V15, .ToReg: 114U }, |
| 3017 | { .FromReg: Hexagon::V16, .ToReg: 115U }, |
| 3018 | { .FromReg: Hexagon::V17, .ToReg: 116U }, |
| 3019 | { .FromReg: Hexagon::V18, .ToReg: 117U }, |
| 3020 | { .FromReg: Hexagon::V19, .ToReg: 118U }, |
| 3021 | { .FromReg: Hexagon::V20, .ToReg: 119U }, |
| 3022 | { .FromReg: Hexagon::V21, .ToReg: 120U }, |
| 3023 | { .FromReg: Hexagon::V22, .ToReg: 121U }, |
| 3024 | { .FromReg: Hexagon::V23, .ToReg: 122U }, |
| 3025 | { .FromReg: Hexagon::V24, .ToReg: 123U }, |
| 3026 | { .FromReg: Hexagon::V25, .ToReg: 124U }, |
| 3027 | { .FromReg: Hexagon::V26, .ToReg: 125U }, |
| 3028 | { .FromReg: Hexagon::V27, .ToReg: 126U }, |
| 3029 | { .FromReg: Hexagon::V28, .ToReg: 127U }, |
| 3030 | { .FromReg: Hexagon::V29, .ToReg: 128U }, |
| 3031 | { .FromReg: Hexagon::V30, .ToReg: 129U }, |
| 3032 | { .FromReg: Hexagon::V31, .ToReg: 130U }, |
| 3033 | { .FromReg: Hexagon::VF0, .ToReg: 999999U }, |
| 3034 | { .FromReg: Hexagon::VF1, .ToReg: 1000000U }, |
| 3035 | { .FromReg: Hexagon::VF2, .ToReg: 1000001U }, |
| 3036 | { .FromReg: Hexagon::VF3, .ToReg: 1000002U }, |
| 3037 | { .FromReg: Hexagon::VF4, .ToReg: 1000003U }, |
| 3038 | { .FromReg: Hexagon::VF5, .ToReg: 1000004U }, |
| 3039 | { .FromReg: Hexagon::VF6, .ToReg: 1000005U }, |
| 3040 | { .FromReg: Hexagon::VF7, .ToReg: 1000006U }, |
| 3041 | { .FromReg: Hexagon::VF8, .ToReg: 1000007U }, |
| 3042 | { .FromReg: Hexagon::VF9, .ToReg: 1000008U }, |
| 3043 | { .FromReg: Hexagon::VF10, .ToReg: 1000009U }, |
| 3044 | { .FromReg: Hexagon::VF11, .ToReg: 1000010U }, |
| 3045 | { .FromReg: Hexagon::VF12, .ToReg: 1000011U }, |
| 3046 | { .FromReg: Hexagon::VF13, .ToReg: 1000012U }, |
| 3047 | { .FromReg: Hexagon::VF14, .ToReg: 1000013U }, |
| 3048 | { .FromReg: Hexagon::VF15, .ToReg: 1000014U }, |
| 3049 | { .FromReg: Hexagon::VF16, .ToReg: 1000015U }, |
| 3050 | { .FromReg: Hexagon::VF17, .ToReg: 1000016U }, |
| 3051 | { .FromReg: Hexagon::VF18, .ToReg: 1000017U }, |
| 3052 | { .FromReg: Hexagon::VF19, .ToReg: 1000018U }, |
| 3053 | { .FromReg: Hexagon::VF20, .ToReg: 1000019U }, |
| 3054 | { .FromReg: Hexagon::VF21, .ToReg: 1000020U }, |
| 3055 | { .FromReg: Hexagon::VF22, .ToReg: 1000021U }, |
| 3056 | { .FromReg: Hexagon::VF23, .ToReg: 1000022U }, |
| 3057 | { .FromReg: Hexagon::VF24, .ToReg: 1000023U }, |
| 3058 | { .FromReg: Hexagon::VF25, .ToReg: 1000024U }, |
| 3059 | { .FromReg: Hexagon::VF26, .ToReg: 1000025U }, |
| 3060 | { .FromReg: Hexagon::VF27, .ToReg: 1000026U }, |
| 3061 | { .FromReg: Hexagon::VF28, .ToReg: 1000027U }, |
| 3062 | { .FromReg: Hexagon::VF29, .ToReg: 1000028U }, |
| 3063 | { .FromReg: Hexagon::VF30, .ToReg: 1000029U }, |
| 3064 | { .FromReg: Hexagon::VF31, .ToReg: 1000030U }, |
| 3065 | { .FromReg: Hexagon::VFR0, .ToReg: 9999999U }, |
| 3066 | { .FromReg: Hexagon::VFR1, .ToReg: 10000000U }, |
| 3067 | { .FromReg: Hexagon::VFR2, .ToReg: 10000001U }, |
| 3068 | { .FromReg: Hexagon::VFR3, .ToReg: 10000002U }, |
| 3069 | { .FromReg: Hexagon::VFR4, .ToReg: 10000003U }, |
| 3070 | { .FromReg: Hexagon::VFR5, .ToReg: 10000004U }, |
| 3071 | { .FromReg: Hexagon::VFR6, .ToReg: 10000005U }, |
| 3072 | { .FromReg: Hexagon::VFR7, .ToReg: 10000006U }, |
| 3073 | { .FromReg: Hexagon::VFR8, .ToReg: 10000007U }, |
| 3074 | { .FromReg: Hexagon::VFR9, .ToReg: 10000008U }, |
| 3075 | { .FromReg: Hexagon::VFR10, .ToReg: 10000009U }, |
| 3076 | { .FromReg: Hexagon::VFR11, .ToReg: 10000010U }, |
| 3077 | { .FromReg: Hexagon::VFR12, .ToReg: 10000011U }, |
| 3078 | { .FromReg: Hexagon::VFR13, .ToReg: 10000012U }, |
| 3079 | { .FromReg: Hexagon::VFR14, .ToReg: 10000013U }, |
| 3080 | { .FromReg: Hexagon::VFR15, .ToReg: 10000014U }, |
| 3081 | { .FromReg: Hexagon::VFR16, .ToReg: 10000015U }, |
| 3082 | { .FromReg: Hexagon::VFR17, .ToReg: 10000016U }, |
| 3083 | { .FromReg: Hexagon::VFR18, .ToReg: 10000017U }, |
| 3084 | { .FromReg: Hexagon::VFR19, .ToReg: 10000018U }, |
| 3085 | { .FromReg: Hexagon::VFR20, .ToReg: 10000019U }, |
| 3086 | { .FromReg: Hexagon::VFR21, .ToReg: 10000020U }, |
| 3087 | { .FromReg: Hexagon::VFR22, .ToReg: 10000021U }, |
| 3088 | { .FromReg: Hexagon::VFR23, .ToReg: 10000022U }, |
| 3089 | { .FromReg: Hexagon::VFR24, .ToReg: 10000023U }, |
| 3090 | { .FromReg: Hexagon::VFR25, .ToReg: 10000024U }, |
| 3091 | { .FromReg: Hexagon::VFR26, .ToReg: 10000025U }, |
| 3092 | { .FromReg: Hexagon::VFR27, .ToReg: 10000026U }, |
| 3093 | { .FromReg: Hexagon::VFR28, .ToReg: 10000027U }, |
| 3094 | { .FromReg: Hexagon::VFR29, .ToReg: 10000028U }, |
| 3095 | { .FromReg: Hexagon::VFR30, .ToReg: 10000029U }, |
| 3096 | { .FromReg: Hexagon::VFR31, .ToReg: 10000030U }, |
| 3097 | { .FromReg: Hexagon::VQ0, .ToReg: 252U }, |
| 3098 | { .FromReg: Hexagon::VQ1, .ToReg: 253U }, |
| 3099 | { .FromReg: Hexagon::VQ2, .ToReg: 254U }, |
| 3100 | { .FromReg: Hexagon::VQ3, .ToReg: 255U }, |
| 3101 | { .FromReg: Hexagon::VQ4, .ToReg: 256U }, |
| 3102 | { .FromReg: Hexagon::VQ5, .ToReg: 257U }, |
| 3103 | { .FromReg: Hexagon::VQ6, .ToReg: 258U }, |
| 3104 | { .FromReg: Hexagon::VQ7, .ToReg: 259U }, |
| 3105 | { .FromReg: Hexagon::W0, .ToReg: 99U }, |
| 3106 | { .FromReg: Hexagon::W1, .ToReg: 101U }, |
| 3107 | { .FromReg: Hexagon::W2, .ToReg: 103U }, |
| 3108 | { .FromReg: Hexagon::W3, .ToReg: 105U }, |
| 3109 | { .FromReg: Hexagon::W4, .ToReg: 107U }, |
| 3110 | { .FromReg: Hexagon::W5, .ToReg: 109U }, |
| 3111 | { .FromReg: Hexagon::W6, .ToReg: 111U }, |
| 3112 | { .FromReg: Hexagon::W7, .ToReg: 113U }, |
| 3113 | { .FromReg: Hexagon::W8, .ToReg: 115U }, |
| 3114 | { .FromReg: Hexagon::W9, .ToReg: 117U }, |
| 3115 | { .FromReg: Hexagon::W10, .ToReg: 119U }, |
| 3116 | { .FromReg: Hexagon::W11, .ToReg: 121U }, |
| 3117 | { .FromReg: Hexagon::W12, .ToReg: 123U }, |
| 3118 | { .FromReg: Hexagon::W13, .ToReg: 125U }, |
| 3119 | { .FromReg: Hexagon::W14, .ToReg: 127U }, |
| 3120 | { .FromReg: Hexagon::W15, .ToReg: 129U }, |
| 3121 | { .FromReg: Hexagon::WR0, .ToReg: 161U }, |
| 3122 | { .FromReg: Hexagon::WR1, .ToReg: 162U }, |
| 3123 | { .FromReg: Hexagon::WR2, .ToReg: 163U }, |
| 3124 | { .FromReg: Hexagon::WR3, .ToReg: 164U }, |
| 3125 | { .FromReg: Hexagon::WR4, .ToReg: 165U }, |
| 3126 | { .FromReg: Hexagon::WR5, .ToReg: 166U }, |
| 3127 | { .FromReg: Hexagon::WR6, .ToReg: 167U }, |
| 3128 | { .FromReg: Hexagon::WR7, .ToReg: 168U }, |
| 3129 | { .FromReg: Hexagon::WR8, .ToReg: 169U }, |
| 3130 | { .FromReg: Hexagon::WR9, .ToReg: 170U }, |
| 3131 | { .FromReg: Hexagon::WR10, .ToReg: 171U }, |
| 3132 | { .FromReg: Hexagon::WR11, .ToReg: 172U }, |
| 3133 | { .FromReg: Hexagon::WR12, .ToReg: 173U }, |
| 3134 | { .FromReg: Hexagon::WR13, .ToReg: 174U }, |
| 3135 | { .FromReg: Hexagon::WR14, .ToReg: 175U }, |
| 3136 | { .FromReg: Hexagon::WR15, .ToReg: 176U }, |
| 3137 | { .FromReg: Hexagon::C1_0, .ToReg: 67U }, |
| 3138 | { .FromReg: Hexagon::C3_2, .ToReg: 69U }, |
| 3139 | { .FromReg: Hexagon::C5_4, .ToReg: 71U }, |
| 3140 | { .FromReg: Hexagon::C7_6, .ToReg: 72U }, |
| 3141 | { .FromReg: Hexagon::C9_8, .ToReg: 74U }, |
| 3142 | { .FromReg: Hexagon::C11_10, .ToReg: 76U }, |
| 3143 | { .FromReg: Hexagon::C17_16, .ToReg: 83U }, |
| 3144 | { .FromReg: Hexagon::G1_0, .ToReg: 220U }, |
| 3145 | { .FromReg: Hexagon::G3_2, .ToReg: 222U }, |
| 3146 | { .FromReg: Hexagon::G5_4, .ToReg: 224U }, |
| 3147 | { .FromReg: Hexagon::G7_6, .ToReg: 226U }, |
| 3148 | { .FromReg: Hexagon::G9_8, .ToReg: 228U }, |
| 3149 | { .FromReg: Hexagon::G11_10, .ToReg: 230U }, |
| 3150 | { .FromReg: Hexagon::G13_12, .ToReg: 232U }, |
| 3151 | { .FromReg: Hexagon::G15_14, .ToReg: 234U }, |
| 3152 | { .FromReg: Hexagon::G17_16, .ToReg: 236U }, |
| 3153 | { .FromReg: Hexagon::G19_18, .ToReg: 238U }, |
| 3154 | { .FromReg: Hexagon::G21_20, .ToReg: 240U }, |
| 3155 | { .FromReg: Hexagon::G23_22, .ToReg: 242U }, |
| 3156 | { .FromReg: Hexagon::G25_24, .ToReg: 244U }, |
| 3157 | { .FromReg: Hexagon::G27_26, .ToReg: 246U }, |
| 3158 | { .FromReg: Hexagon::G29_28, .ToReg: 248U }, |
| 3159 | { .FromReg: Hexagon::G31_30, .ToReg: 250U }, |
| 3160 | { .FromReg: Hexagon::P3_0, .ToReg: 71U }, |
| 3161 | { .FromReg: Hexagon::S3_2, .ToReg: 146U }, |
| 3162 | { .FromReg: Hexagon::S5_4, .ToReg: 148U }, |
| 3163 | { .FromReg: Hexagon::S7_6, .ToReg: 150U }, |
| 3164 | { .FromReg: Hexagon::S9_8, .ToReg: 152U }, |
| 3165 | { .FromReg: Hexagon::S11_10, .ToReg: 154U }, |
| 3166 | { .FromReg: Hexagon::S13_12, .ToReg: 156U }, |
| 3167 | { .FromReg: Hexagon::S15_14, .ToReg: 158U }, |
| 3168 | { .FromReg: Hexagon::S17_16, .ToReg: 160U }, |
| 3169 | { .FromReg: Hexagon::S19_18, .ToReg: 162U }, |
| 3170 | { .FromReg: Hexagon::S21_20, .ToReg: 164U }, |
| 3171 | { .FromReg: Hexagon::S23_22, .ToReg: 166U }, |
| 3172 | { .FromReg: Hexagon::S25_24, .ToReg: 168U }, |
| 3173 | { .FromReg: Hexagon::S27_26, .ToReg: 170U }, |
| 3174 | { .FromReg: Hexagon::S29_28, .ToReg: 172U }, |
| 3175 | { .FromReg: Hexagon::S31_30, .ToReg: 174U }, |
| 3176 | { .FromReg: Hexagon::S33_32, .ToReg: 176U }, |
| 3177 | { .FromReg: Hexagon::S35_34, .ToReg: 178U }, |
| 3178 | { .FromReg: Hexagon::S37_36, .ToReg: 180U }, |
| 3179 | { .FromReg: Hexagon::S39_38, .ToReg: 182U }, |
| 3180 | { .FromReg: Hexagon::S41_40, .ToReg: 184U }, |
| 3181 | { .FromReg: Hexagon::S43_42, .ToReg: 186U }, |
| 3182 | { .FromReg: Hexagon::S45_44, .ToReg: 188U }, |
| 3183 | { .FromReg: Hexagon::S47_46, .ToReg: 190U }, |
| 3184 | { .FromReg: Hexagon::S49_48, .ToReg: 192U }, |
| 3185 | { .FromReg: Hexagon::S51_50, .ToReg: 194U }, |
| 3186 | { .FromReg: Hexagon::S53_52, .ToReg: 196U }, |
| 3187 | { .FromReg: Hexagon::S55_54, .ToReg: 198U }, |
| 3188 | { .FromReg: Hexagon::S57_56, .ToReg: 200U }, |
| 3189 | { .FromReg: Hexagon::S59_58, .ToReg: 202U }, |
| 3190 | { .FromReg: Hexagon::S61_60, .ToReg: 204U }, |
| 3191 | { .FromReg: Hexagon::S63_62, .ToReg: 206U }, |
| 3192 | { .FromReg: Hexagon::S65_64, .ToReg: 208U }, |
| 3193 | { .FromReg: Hexagon::S67_66, .ToReg: 210U }, |
| 3194 | { .FromReg: Hexagon::S69_68, .ToReg: 212U }, |
| 3195 | { .FromReg: Hexagon::S71_70, .ToReg: 214U }, |
| 3196 | { .FromReg: Hexagon::S73_72, .ToReg: 216U }, |
| 3197 | { .FromReg: Hexagon::S75_74, .ToReg: 218U }, |
| 3198 | { .FromReg: Hexagon::S77_76, .ToReg: 219U }, |
| 3199 | { .FromReg: Hexagon::S79_78, .ToReg: 220U }, |
| 3200 | { .FromReg: Hexagon::SGP1_0, .ToReg: 144U }, |
| 3201 | }; |
| 3202 | extern const unsigned HexagonDwarfFlavour0L2DwarfSize = std::size(HexagonDwarfFlavour0L2Dwarf); |
| 3203 | |
| 3204 | extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[] = { |
| 3205 | { .FromReg: Hexagon::BADVA, .ToReg: 153U }, |
| 3206 | { .FromReg: Hexagon::CCR, .ToReg: 151U }, |
| 3207 | { .FromReg: Hexagon::CFGBASE, .ToReg: 171U }, |
| 3208 | { .FromReg: Hexagon::CS, .ToReg: 78U }, |
| 3209 | { .FromReg: Hexagon::DIAG, .ToReg: 172U }, |
| 3210 | { .FromReg: Hexagon::ELR, .ToReg: 147U }, |
| 3211 | { .FromReg: Hexagon::EVB, .ToReg: 160U }, |
| 3212 | { .FromReg: Hexagon::FRAMEKEY, .ToReg: 84U }, |
| 3213 | { .FromReg: Hexagon::FRAMELIMIT, .ToReg: 83U }, |
| 3214 | { .FromReg: Hexagon::GELR, .ToReg: 220U }, |
| 3215 | { .FromReg: Hexagon::GOSP, .ToReg: 222U }, |
| 3216 | { .FromReg: Hexagon::GP, .ToReg: 78U }, |
| 3217 | { .FromReg: Hexagon::GPCYCLEHI, .ToReg: 245U }, |
| 3218 | { .FromReg: Hexagon::GPCYCLELO, .ToReg: 244U }, |
| 3219 | { .FromReg: Hexagon::GSR, .ToReg: 221U }, |
| 3220 | { .FromReg: Hexagon::HTID, .ToReg: 152U }, |
| 3221 | { .FromReg: Hexagon::IMASK, .ToReg: 154U }, |
| 3222 | { .FromReg: Hexagon::ISDBEN, .ToReg: 186U }, |
| 3223 | { .FromReg: Hexagon::ISDBGPR, .ToReg: 187U }, |
| 3224 | { .FromReg: Hexagon::ISDBMBXIN, .ToReg: 184U }, |
| 3225 | { .FromReg: Hexagon::ISDBMBXOUT, .ToReg: 185U }, |
| 3226 | { .FromReg: Hexagon::ISDBST, .ToReg: 176U }, |
| 3227 | { .FromReg: Hexagon::MODECTL, .ToReg: 161U }, |
| 3228 | { .FromReg: Hexagon::PC, .ToReg: 76U }, |
| 3229 | { .FromReg: Hexagon::PCYCLEHI, .ToReg: 175U }, |
| 3230 | { .FromReg: Hexagon::PCYCLELO, .ToReg: 174U }, |
| 3231 | { .FromReg: Hexagon::PKTCOUNT, .ToReg: 85U }, |
| 3232 | { .FromReg: Hexagon::PKTCOUNTHI, .ToReg: 86U }, |
| 3233 | { .FromReg: Hexagon::PKTCOUNTLO, .ToReg: 85U }, |
| 3234 | { .FromReg: Hexagon::PMUCFG, .ToReg: 197U }, |
| 3235 | { .FromReg: Hexagon::PMUEVTCFG, .ToReg: 196U }, |
| 3236 | { .FromReg: Hexagon::REV, .ToReg: 173U }, |
| 3237 | { .FromReg: Hexagon::SSR, .ToReg: 150U }, |
| 3238 | { .FromReg: Hexagon::STID, .ToReg: 146U }, |
| 3239 | { .FromReg: Hexagon::SYSCFG, .ToReg: 162U }, |
| 3240 | { .FromReg: Hexagon::UGP, .ToReg: 77U }, |
| 3241 | { .FromReg: Hexagon::UPCYCLE, .ToReg: 80U }, |
| 3242 | { .FromReg: Hexagon::UPCYCLEHI, .ToReg: 82U }, |
| 3243 | { .FromReg: Hexagon::UPCYCLELO, .ToReg: 81U }, |
| 3244 | { .FromReg: Hexagon::USR, .ToReg: 75U }, |
| 3245 | { .FromReg: Hexagon::UTIMER, .ToReg: 97U }, |
| 3246 | { .FromReg: Hexagon::UTIMERHI, .ToReg: 98U }, |
| 3247 | { .FromReg: Hexagon::UTIMERLO, .ToReg: 97U }, |
| 3248 | { .FromReg: Hexagon::VID, .ToReg: 165U }, |
| 3249 | { .FromReg: Hexagon::VTMP, .ToReg: 131U }, |
| 3250 | { .FromReg: Hexagon::BADVA0, .ToReg: 148U }, |
| 3251 | { .FromReg: Hexagon::BADVA1, .ToReg: 149U }, |
| 3252 | { .FromReg: Hexagon::BRKPTCFG0, .ToReg: 181U }, |
| 3253 | { .FromReg: Hexagon::BRKPTCFG1, .ToReg: 183U }, |
| 3254 | { .FromReg: Hexagon::BRKPTPC0, .ToReg: 180U }, |
| 3255 | { .FromReg: Hexagon::BRKPTPC1, .ToReg: 182U }, |
| 3256 | { .FromReg: Hexagon::C5, .ToReg: 72U }, |
| 3257 | { .FromReg: Hexagon::C8, .ToReg: 75U }, |
| 3258 | { .FromReg: Hexagon::CS0, .ToReg: 79U }, |
| 3259 | { .FromReg: Hexagon::CS1, .ToReg: 80U }, |
| 3260 | { .FromReg: Hexagon::D0, .ToReg: 32U }, |
| 3261 | { .FromReg: Hexagon::D1, .ToReg: 34U }, |
| 3262 | { .FromReg: Hexagon::D2, .ToReg: 36U }, |
| 3263 | { .FromReg: Hexagon::D3, .ToReg: 38U }, |
| 3264 | { .FromReg: Hexagon::D4, .ToReg: 40U }, |
| 3265 | { .FromReg: Hexagon::D5, .ToReg: 42U }, |
| 3266 | { .FromReg: Hexagon::D6, .ToReg: 44U }, |
| 3267 | { .FromReg: Hexagon::D7, .ToReg: 46U }, |
| 3268 | { .FromReg: Hexagon::D8, .ToReg: 48U }, |
| 3269 | { .FromReg: Hexagon::D9, .ToReg: 50U }, |
| 3270 | { .FromReg: Hexagon::D10, .ToReg: 52U }, |
| 3271 | { .FromReg: Hexagon::D11, .ToReg: 54U }, |
| 3272 | { .FromReg: Hexagon::D12, .ToReg: 56U }, |
| 3273 | { .FromReg: Hexagon::D13, .ToReg: 58U }, |
| 3274 | { .FromReg: Hexagon::D14, .ToReg: 60U }, |
| 3275 | { .FromReg: Hexagon::D15, .ToReg: 62U }, |
| 3276 | { .FromReg: Hexagon::G3, .ToReg: 223U }, |
| 3277 | { .FromReg: Hexagon::G4, .ToReg: 224U }, |
| 3278 | { .FromReg: Hexagon::G5, .ToReg: 225U }, |
| 3279 | { .FromReg: Hexagon::G6, .ToReg: 226U }, |
| 3280 | { .FromReg: Hexagon::G7, .ToReg: 227U }, |
| 3281 | { .FromReg: Hexagon::G8, .ToReg: 228U }, |
| 3282 | { .FromReg: Hexagon::G9, .ToReg: 229U }, |
| 3283 | { .FromReg: Hexagon::G10, .ToReg: 230U }, |
| 3284 | { .FromReg: Hexagon::G11, .ToReg: 231U }, |
| 3285 | { .FromReg: Hexagon::G12, .ToReg: 232U }, |
| 3286 | { .FromReg: Hexagon::G13, .ToReg: 233U }, |
| 3287 | { .FromReg: Hexagon::G14, .ToReg: 234U }, |
| 3288 | { .FromReg: Hexagon::G15, .ToReg: 235U }, |
| 3289 | { .FromReg: Hexagon::G20, .ToReg: 240U }, |
| 3290 | { .FromReg: Hexagon::G21, .ToReg: 241U }, |
| 3291 | { .FromReg: Hexagon::G22, .ToReg: 242U }, |
| 3292 | { .FromReg: Hexagon::G23, .ToReg: 243U }, |
| 3293 | { .FromReg: Hexagon::G30, .ToReg: 250U }, |
| 3294 | { .FromReg: Hexagon::G31, .ToReg: 251U }, |
| 3295 | { .FromReg: Hexagon::GPMUCNT0, .ToReg: 246U }, |
| 3296 | { .FromReg: Hexagon::GPMUCNT1, .ToReg: 247U }, |
| 3297 | { .FromReg: Hexagon::GPMUCNT2, .ToReg: 248U }, |
| 3298 | { .FromReg: Hexagon::GPMUCNT3, .ToReg: 249U }, |
| 3299 | { .FromReg: Hexagon::GPMUCNT4, .ToReg: 236U }, |
| 3300 | { .FromReg: Hexagon::GPMUCNT5, .ToReg: 237U }, |
| 3301 | { .FromReg: Hexagon::GPMUCNT6, .ToReg: 238U }, |
| 3302 | { .FromReg: Hexagon::GPMUCNT7, .ToReg: 239U }, |
| 3303 | { .FromReg: Hexagon::ISDBCFG0, .ToReg: 177U }, |
| 3304 | { .FromReg: Hexagon::ISDBCFG1, .ToReg: 178U }, |
| 3305 | { .FromReg: Hexagon::LC0, .ToReg: 68U }, |
| 3306 | { .FromReg: Hexagon::LC1, .ToReg: 70U }, |
| 3307 | { .FromReg: Hexagon::M0, .ToReg: 73U }, |
| 3308 | { .FromReg: Hexagon::M1, .ToReg: 74U }, |
| 3309 | { .FromReg: Hexagon::P0, .ToReg: 63U }, |
| 3310 | { .FromReg: Hexagon::P1, .ToReg: 64U }, |
| 3311 | { .FromReg: Hexagon::P2, .ToReg: 65U }, |
| 3312 | { .FromReg: Hexagon::P3, .ToReg: 66U }, |
| 3313 | { .FromReg: Hexagon::PMUCNT0, .ToReg: 192U }, |
| 3314 | { .FromReg: Hexagon::PMUCNT1, .ToReg: 193U }, |
| 3315 | { .FromReg: Hexagon::PMUCNT2, .ToReg: 194U }, |
| 3316 | { .FromReg: Hexagon::PMUCNT3, .ToReg: 195U }, |
| 3317 | { .FromReg: Hexagon::Q0, .ToReg: 131U }, |
| 3318 | { .FromReg: Hexagon::Q1, .ToReg: 132U }, |
| 3319 | { .FromReg: Hexagon::Q2, .ToReg: 133U }, |
| 3320 | { .FromReg: Hexagon::Q3, .ToReg: 134U }, |
| 3321 | { .FromReg: Hexagon::R0, .ToReg: 0U }, |
| 3322 | { .FromReg: Hexagon::R1, .ToReg: 1U }, |
| 3323 | { .FromReg: Hexagon::R2, .ToReg: 2U }, |
| 3324 | { .FromReg: Hexagon::R3, .ToReg: 3U }, |
| 3325 | { .FromReg: Hexagon::R4, .ToReg: 4U }, |
| 3326 | { .FromReg: Hexagon::R5, .ToReg: 5U }, |
| 3327 | { .FromReg: Hexagon::R6, .ToReg: 6U }, |
| 3328 | { .FromReg: Hexagon::R7, .ToReg: 7U }, |
| 3329 | { .FromReg: Hexagon::R8, .ToReg: 8U }, |
| 3330 | { .FromReg: Hexagon::R9, .ToReg: 9U }, |
| 3331 | { .FromReg: Hexagon::R10, .ToReg: 10U }, |
| 3332 | { .FromReg: Hexagon::R11, .ToReg: 11U }, |
| 3333 | { .FromReg: Hexagon::R12, .ToReg: 12U }, |
| 3334 | { .FromReg: Hexagon::R13, .ToReg: 13U }, |
| 3335 | { .FromReg: Hexagon::R14, .ToReg: 14U }, |
| 3336 | { .FromReg: Hexagon::R15, .ToReg: 15U }, |
| 3337 | { .FromReg: Hexagon::R16, .ToReg: 16U }, |
| 3338 | { .FromReg: Hexagon::R17, .ToReg: 17U }, |
| 3339 | { .FromReg: Hexagon::R18, .ToReg: 18U }, |
| 3340 | { .FromReg: Hexagon::R19, .ToReg: 19U }, |
| 3341 | { .FromReg: Hexagon::R20, .ToReg: 20U }, |
| 3342 | { .FromReg: Hexagon::R21, .ToReg: 21U }, |
| 3343 | { .FromReg: Hexagon::R22, .ToReg: 22U }, |
| 3344 | { .FromReg: Hexagon::R23, .ToReg: 23U }, |
| 3345 | { .FromReg: Hexagon::R24, .ToReg: 24U }, |
| 3346 | { .FromReg: Hexagon::R25, .ToReg: 25U }, |
| 3347 | { .FromReg: Hexagon::R26, .ToReg: 26U }, |
| 3348 | { .FromReg: Hexagon::R27, .ToReg: 27U }, |
| 3349 | { .FromReg: Hexagon::R28, .ToReg: 28U }, |
| 3350 | { .FromReg: Hexagon::R29, .ToReg: 29U }, |
| 3351 | { .FromReg: Hexagon::R30, .ToReg: 30U }, |
| 3352 | { .FromReg: Hexagon::R31, .ToReg: 31U }, |
| 3353 | { .FromReg: Hexagon::S11, .ToReg: 155U }, |
| 3354 | { .FromReg: Hexagon::S12, .ToReg: 156U }, |
| 3355 | { .FromReg: Hexagon::S13, .ToReg: 157U }, |
| 3356 | { .FromReg: Hexagon::S14, .ToReg: 158U }, |
| 3357 | { .FromReg: Hexagon::S15, .ToReg: 159U }, |
| 3358 | { .FromReg: Hexagon::S19, .ToReg: 163U }, |
| 3359 | { .FromReg: Hexagon::S20, .ToReg: 164U }, |
| 3360 | { .FromReg: Hexagon::S22, .ToReg: 166U }, |
| 3361 | { .FromReg: Hexagon::S23, .ToReg: 167U }, |
| 3362 | { .FromReg: Hexagon::S24, .ToReg: 168U }, |
| 3363 | { .FromReg: Hexagon::S25, .ToReg: 169U }, |
| 3364 | { .FromReg: Hexagon::S26, .ToReg: 170U }, |
| 3365 | { .FromReg: Hexagon::S35, .ToReg: 179U }, |
| 3366 | { .FromReg: Hexagon::S44, .ToReg: 188U }, |
| 3367 | { .FromReg: Hexagon::S45, .ToReg: 189U }, |
| 3368 | { .FromReg: Hexagon::S46, .ToReg: 190U }, |
| 3369 | { .FromReg: Hexagon::S47, .ToReg: 191U }, |
| 3370 | { .FromReg: Hexagon::S54, .ToReg: 198U }, |
| 3371 | { .FromReg: Hexagon::S55, .ToReg: 199U }, |
| 3372 | { .FromReg: Hexagon::S56, .ToReg: 200U }, |
| 3373 | { .FromReg: Hexagon::S57, .ToReg: 201U }, |
| 3374 | { .FromReg: Hexagon::S58, .ToReg: 202U }, |
| 3375 | { .FromReg: Hexagon::S59, .ToReg: 203U }, |
| 3376 | { .FromReg: Hexagon::S60, .ToReg: 204U }, |
| 3377 | { .FromReg: Hexagon::S61, .ToReg: 205U }, |
| 3378 | { .FromReg: Hexagon::S62, .ToReg: 206U }, |
| 3379 | { .FromReg: Hexagon::S63, .ToReg: 207U }, |
| 3380 | { .FromReg: Hexagon::S64, .ToReg: 208U }, |
| 3381 | { .FromReg: Hexagon::S65, .ToReg: 209U }, |
| 3382 | { .FromReg: Hexagon::S66, .ToReg: 210U }, |
| 3383 | { .FromReg: Hexagon::S67, .ToReg: 211U }, |
| 3384 | { .FromReg: Hexagon::S68, .ToReg: 212U }, |
| 3385 | { .FromReg: Hexagon::S69, .ToReg: 213U }, |
| 3386 | { .FromReg: Hexagon::S70, .ToReg: 214U }, |
| 3387 | { .FromReg: Hexagon::S71, .ToReg: 215U }, |
| 3388 | { .FromReg: Hexagon::S72, .ToReg: 216U }, |
| 3389 | { .FromReg: Hexagon::S73, .ToReg: 217U }, |
| 3390 | { .FromReg: Hexagon::S74, .ToReg: 218U }, |
| 3391 | { .FromReg: Hexagon::S75, .ToReg: 219U }, |
| 3392 | { .FromReg: Hexagon::S76, .ToReg: 220U }, |
| 3393 | { .FromReg: Hexagon::S77, .ToReg: 221U }, |
| 3394 | { .FromReg: Hexagon::S78, .ToReg: 222U }, |
| 3395 | { .FromReg: Hexagon::S79, .ToReg: 223U }, |
| 3396 | { .FromReg: Hexagon::S80, .ToReg: 224U }, |
| 3397 | { .FromReg: Hexagon::SA0, .ToReg: 67U }, |
| 3398 | { .FromReg: Hexagon::SA1, .ToReg: 69U }, |
| 3399 | { .FromReg: Hexagon::SGP0, .ToReg: 144U }, |
| 3400 | { .FromReg: Hexagon::SGP1, .ToReg: 145U }, |
| 3401 | { .FromReg: Hexagon::V0, .ToReg: 99U }, |
| 3402 | { .FromReg: Hexagon::V1, .ToReg: 100U }, |
| 3403 | { .FromReg: Hexagon::V2, .ToReg: 101U }, |
| 3404 | { .FromReg: Hexagon::V3, .ToReg: 102U }, |
| 3405 | { .FromReg: Hexagon::V4, .ToReg: 103U }, |
| 3406 | { .FromReg: Hexagon::V5, .ToReg: 104U }, |
| 3407 | { .FromReg: Hexagon::V6, .ToReg: 105U }, |
| 3408 | { .FromReg: Hexagon::V7, .ToReg: 106U }, |
| 3409 | { .FromReg: Hexagon::V8, .ToReg: 107U }, |
| 3410 | { .FromReg: Hexagon::V9, .ToReg: 108U }, |
| 3411 | { .FromReg: Hexagon::V10, .ToReg: 109U }, |
| 3412 | { .FromReg: Hexagon::V11, .ToReg: 110U }, |
| 3413 | { .FromReg: Hexagon::V12, .ToReg: 111U }, |
| 3414 | { .FromReg: Hexagon::V13, .ToReg: 112U }, |
| 3415 | { .FromReg: Hexagon::V14, .ToReg: 113U }, |
| 3416 | { .FromReg: Hexagon::V15, .ToReg: 114U }, |
| 3417 | { .FromReg: Hexagon::V16, .ToReg: 115U }, |
| 3418 | { .FromReg: Hexagon::V17, .ToReg: 116U }, |
| 3419 | { .FromReg: Hexagon::V18, .ToReg: 117U }, |
| 3420 | { .FromReg: Hexagon::V19, .ToReg: 118U }, |
| 3421 | { .FromReg: Hexagon::V20, .ToReg: 119U }, |
| 3422 | { .FromReg: Hexagon::V21, .ToReg: 120U }, |
| 3423 | { .FromReg: Hexagon::V22, .ToReg: 121U }, |
| 3424 | { .FromReg: Hexagon::V23, .ToReg: 122U }, |
| 3425 | { .FromReg: Hexagon::V24, .ToReg: 123U }, |
| 3426 | { .FromReg: Hexagon::V25, .ToReg: 124U }, |
| 3427 | { .FromReg: Hexagon::V26, .ToReg: 125U }, |
| 3428 | { .FromReg: Hexagon::V27, .ToReg: 126U }, |
| 3429 | { .FromReg: Hexagon::V28, .ToReg: 127U }, |
| 3430 | { .FromReg: Hexagon::V29, .ToReg: 128U }, |
| 3431 | { .FromReg: Hexagon::V30, .ToReg: 129U }, |
| 3432 | { .FromReg: Hexagon::V31, .ToReg: 130U }, |
| 3433 | { .FromReg: Hexagon::VF0, .ToReg: 999999U }, |
| 3434 | { .FromReg: Hexagon::VF1, .ToReg: 1000000U }, |
| 3435 | { .FromReg: Hexagon::VF2, .ToReg: 1000001U }, |
| 3436 | { .FromReg: Hexagon::VF3, .ToReg: 1000002U }, |
| 3437 | { .FromReg: Hexagon::VF4, .ToReg: 1000003U }, |
| 3438 | { .FromReg: Hexagon::VF5, .ToReg: 1000004U }, |
| 3439 | { .FromReg: Hexagon::VF6, .ToReg: 1000005U }, |
| 3440 | { .FromReg: Hexagon::VF7, .ToReg: 1000006U }, |
| 3441 | { .FromReg: Hexagon::VF8, .ToReg: 1000007U }, |
| 3442 | { .FromReg: Hexagon::VF9, .ToReg: 1000008U }, |
| 3443 | { .FromReg: Hexagon::VF10, .ToReg: 1000009U }, |
| 3444 | { .FromReg: Hexagon::VF11, .ToReg: 1000010U }, |
| 3445 | { .FromReg: Hexagon::VF12, .ToReg: 1000011U }, |
| 3446 | { .FromReg: Hexagon::VF13, .ToReg: 1000012U }, |
| 3447 | { .FromReg: Hexagon::VF14, .ToReg: 1000013U }, |
| 3448 | { .FromReg: Hexagon::VF15, .ToReg: 1000014U }, |
| 3449 | { .FromReg: Hexagon::VF16, .ToReg: 1000015U }, |
| 3450 | { .FromReg: Hexagon::VF17, .ToReg: 1000016U }, |
| 3451 | { .FromReg: Hexagon::VF18, .ToReg: 1000017U }, |
| 3452 | { .FromReg: Hexagon::VF19, .ToReg: 1000018U }, |
| 3453 | { .FromReg: Hexagon::VF20, .ToReg: 1000019U }, |
| 3454 | { .FromReg: Hexagon::VF21, .ToReg: 1000020U }, |
| 3455 | { .FromReg: Hexagon::VF22, .ToReg: 1000021U }, |
| 3456 | { .FromReg: Hexagon::VF23, .ToReg: 1000022U }, |
| 3457 | { .FromReg: Hexagon::VF24, .ToReg: 1000023U }, |
| 3458 | { .FromReg: Hexagon::VF25, .ToReg: 1000024U }, |
| 3459 | { .FromReg: Hexagon::VF26, .ToReg: 1000025U }, |
| 3460 | { .FromReg: Hexagon::VF27, .ToReg: 1000026U }, |
| 3461 | { .FromReg: Hexagon::VF28, .ToReg: 1000027U }, |
| 3462 | { .FromReg: Hexagon::VF29, .ToReg: 1000028U }, |
| 3463 | { .FromReg: Hexagon::VF30, .ToReg: 1000029U }, |
| 3464 | { .FromReg: Hexagon::VF31, .ToReg: 1000030U }, |
| 3465 | { .FromReg: Hexagon::VFR0, .ToReg: 9999999U }, |
| 3466 | { .FromReg: Hexagon::VFR1, .ToReg: 10000000U }, |
| 3467 | { .FromReg: Hexagon::VFR2, .ToReg: 10000001U }, |
| 3468 | { .FromReg: Hexagon::VFR3, .ToReg: 10000002U }, |
| 3469 | { .FromReg: Hexagon::VFR4, .ToReg: 10000003U }, |
| 3470 | { .FromReg: Hexagon::VFR5, .ToReg: 10000004U }, |
| 3471 | { .FromReg: Hexagon::VFR6, .ToReg: 10000005U }, |
| 3472 | { .FromReg: Hexagon::VFR7, .ToReg: 10000006U }, |
| 3473 | { .FromReg: Hexagon::VFR8, .ToReg: 10000007U }, |
| 3474 | { .FromReg: Hexagon::VFR9, .ToReg: 10000008U }, |
| 3475 | { .FromReg: Hexagon::VFR10, .ToReg: 10000009U }, |
| 3476 | { .FromReg: Hexagon::VFR11, .ToReg: 10000010U }, |
| 3477 | { .FromReg: Hexagon::VFR12, .ToReg: 10000011U }, |
| 3478 | { .FromReg: Hexagon::VFR13, .ToReg: 10000012U }, |
| 3479 | { .FromReg: Hexagon::VFR14, .ToReg: 10000013U }, |
| 3480 | { .FromReg: Hexagon::VFR15, .ToReg: 10000014U }, |
| 3481 | { .FromReg: Hexagon::VFR16, .ToReg: 10000015U }, |
| 3482 | { .FromReg: Hexagon::VFR17, .ToReg: 10000016U }, |
| 3483 | { .FromReg: Hexagon::VFR18, .ToReg: 10000017U }, |
| 3484 | { .FromReg: Hexagon::VFR19, .ToReg: 10000018U }, |
| 3485 | { .FromReg: Hexagon::VFR20, .ToReg: 10000019U }, |
| 3486 | { .FromReg: Hexagon::VFR21, .ToReg: 10000020U }, |
| 3487 | { .FromReg: Hexagon::VFR22, .ToReg: 10000021U }, |
| 3488 | { .FromReg: Hexagon::VFR23, .ToReg: 10000022U }, |
| 3489 | { .FromReg: Hexagon::VFR24, .ToReg: 10000023U }, |
| 3490 | { .FromReg: Hexagon::VFR25, .ToReg: 10000024U }, |
| 3491 | { .FromReg: Hexagon::VFR26, .ToReg: 10000025U }, |
| 3492 | { .FromReg: Hexagon::VFR27, .ToReg: 10000026U }, |
| 3493 | { .FromReg: Hexagon::VFR28, .ToReg: 10000027U }, |
| 3494 | { .FromReg: Hexagon::VFR29, .ToReg: 10000028U }, |
| 3495 | { .FromReg: Hexagon::VFR30, .ToReg: 10000029U }, |
| 3496 | { .FromReg: Hexagon::VFR31, .ToReg: 10000030U }, |
| 3497 | { .FromReg: Hexagon::VQ0, .ToReg: 252U }, |
| 3498 | { .FromReg: Hexagon::VQ1, .ToReg: 253U }, |
| 3499 | { .FromReg: Hexagon::VQ2, .ToReg: 254U }, |
| 3500 | { .FromReg: Hexagon::VQ3, .ToReg: 255U }, |
| 3501 | { .FromReg: Hexagon::VQ4, .ToReg: 256U }, |
| 3502 | { .FromReg: Hexagon::VQ5, .ToReg: 257U }, |
| 3503 | { .FromReg: Hexagon::VQ6, .ToReg: 258U }, |
| 3504 | { .FromReg: Hexagon::VQ7, .ToReg: 259U }, |
| 3505 | { .FromReg: Hexagon::W0, .ToReg: 99U }, |
| 3506 | { .FromReg: Hexagon::W1, .ToReg: 101U }, |
| 3507 | { .FromReg: Hexagon::W2, .ToReg: 103U }, |
| 3508 | { .FromReg: Hexagon::W3, .ToReg: 105U }, |
| 3509 | { .FromReg: Hexagon::W4, .ToReg: 107U }, |
| 3510 | { .FromReg: Hexagon::W5, .ToReg: 109U }, |
| 3511 | { .FromReg: Hexagon::W6, .ToReg: 111U }, |
| 3512 | { .FromReg: Hexagon::W7, .ToReg: 113U }, |
| 3513 | { .FromReg: Hexagon::W8, .ToReg: 115U }, |
| 3514 | { .FromReg: Hexagon::W9, .ToReg: 117U }, |
| 3515 | { .FromReg: Hexagon::W10, .ToReg: 119U }, |
| 3516 | { .FromReg: Hexagon::W11, .ToReg: 121U }, |
| 3517 | { .FromReg: Hexagon::W12, .ToReg: 123U }, |
| 3518 | { .FromReg: Hexagon::W13, .ToReg: 125U }, |
| 3519 | { .FromReg: Hexagon::W14, .ToReg: 127U }, |
| 3520 | { .FromReg: Hexagon::W15, .ToReg: 129U }, |
| 3521 | { .FromReg: Hexagon::WR0, .ToReg: 161U }, |
| 3522 | { .FromReg: Hexagon::WR1, .ToReg: 162U }, |
| 3523 | { .FromReg: Hexagon::WR2, .ToReg: 163U }, |
| 3524 | { .FromReg: Hexagon::WR3, .ToReg: 164U }, |
| 3525 | { .FromReg: Hexagon::WR4, .ToReg: 165U }, |
| 3526 | { .FromReg: Hexagon::WR5, .ToReg: 166U }, |
| 3527 | { .FromReg: Hexagon::WR6, .ToReg: 167U }, |
| 3528 | { .FromReg: Hexagon::WR7, .ToReg: 168U }, |
| 3529 | { .FromReg: Hexagon::WR8, .ToReg: 169U }, |
| 3530 | { .FromReg: Hexagon::WR9, .ToReg: 170U }, |
| 3531 | { .FromReg: Hexagon::WR10, .ToReg: 171U }, |
| 3532 | { .FromReg: Hexagon::WR11, .ToReg: 172U }, |
| 3533 | { .FromReg: Hexagon::WR12, .ToReg: 173U }, |
| 3534 | { .FromReg: Hexagon::WR13, .ToReg: 174U }, |
| 3535 | { .FromReg: Hexagon::WR14, .ToReg: 175U }, |
| 3536 | { .FromReg: Hexagon::WR15, .ToReg: 176U }, |
| 3537 | { .FromReg: Hexagon::C1_0, .ToReg: 67U }, |
| 3538 | { .FromReg: Hexagon::C3_2, .ToReg: 69U }, |
| 3539 | { .FromReg: Hexagon::C5_4, .ToReg: 71U }, |
| 3540 | { .FromReg: Hexagon::C7_6, .ToReg: 72U }, |
| 3541 | { .FromReg: Hexagon::C9_8, .ToReg: 74U }, |
| 3542 | { .FromReg: Hexagon::C11_10, .ToReg: 76U }, |
| 3543 | { .FromReg: Hexagon::C17_16, .ToReg: 83U }, |
| 3544 | { .FromReg: Hexagon::G1_0, .ToReg: 220U }, |
| 3545 | { .FromReg: Hexagon::G3_2, .ToReg: 222U }, |
| 3546 | { .FromReg: Hexagon::G5_4, .ToReg: 224U }, |
| 3547 | { .FromReg: Hexagon::G7_6, .ToReg: 226U }, |
| 3548 | { .FromReg: Hexagon::G9_8, .ToReg: 228U }, |
| 3549 | { .FromReg: Hexagon::G11_10, .ToReg: 230U }, |
| 3550 | { .FromReg: Hexagon::G13_12, .ToReg: 232U }, |
| 3551 | { .FromReg: Hexagon::G15_14, .ToReg: 234U }, |
| 3552 | { .FromReg: Hexagon::G17_16, .ToReg: 236U }, |
| 3553 | { .FromReg: Hexagon::G19_18, .ToReg: 238U }, |
| 3554 | { .FromReg: Hexagon::G21_20, .ToReg: 240U }, |
| 3555 | { .FromReg: Hexagon::G23_22, .ToReg: 242U }, |
| 3556 | { .FromReg: Hexagon::G25_24, .ToReg: 244U }, |
| 3557 | { .FromReg: Hexagon::G27_26, .ToReg: 246U }, |
| 3558 | { .FromReg: Hexagon::G29_28, .ToReg: 248U }, |
| 3559 | { .FromReg: Hexagon::G31_30, .ToReg: 250U }, |
| 3560 | { .FromReg: Hexagon::P3_0, .ToReg: 71U }, |
| 3561 | { .FromReg: Hexagon::S3_2, .ToReg: 146U }, |
| 3562 | { .FromReg: Hexagon::S5_4, .ToReg: 148U }, |
| 3563 | { .FromReg: Hexagon::S7_6, .ToReg: 150U }, |
| 3564 | { .FromReg: Hexagon::S9_8, .ToReg: 152U }, |
| 3565 | { .FromReg: Hexagon::S11_10, .ToReg: 154U }, |
| 3566 | { .FromReg: Hexagon::S13_12, .ToReg: 156U }, |
| 3567 | { .FromReg: Hexagon::S15_14, .ToReg: 158U }, |
| 3568 | { .FromReg: Hexagon::S17_16, .ToReg: 160U }, |
| 3569 | { .FromReg: Hexagon::S19_18, .ToReg: 162U }, |
| 3570 | { .FromReg: Hexagon::S21_20, .ToReg: 164U }, |
| 3571 | { .FromReg: Hexagon::S23_22, .ToReg: 166U }, |
| 3572 | { .FromReg: Hexagon::S25_24, .ToReg: 168U }, |
| 3573 | { .FromReg: Hexagon::S27_26, .ToReg: 170U }, |
| 3574 | { .FromReg: Hexagon::S29_28, .ToReg: 172U }, |
| 3575 | { .FromReg: Hexagon::S31_30, .ToReg: 174U }, |
| 3576 | { .FromReg: Hexagon::S33_32, .ToReg: 176U }, |
| 3577 | { .FromReg: Hexagon::S35_34, .ToReg: 178U }, |
| 3578 | { .FromReg: Hexagon::S37_36, .ToReg: 180U }, |
| 3579 | { .FromReg: Hexagon::S39_38, .ToReg: 182U }, |
| 3580 | { .FromReg: Hexagon::S41_40, .ToReg: 184U }, |
| 3581 | { .FromReg: Hexagon::S43_42, .ToReg: 186U }, |
| 3582 | { .FromReg: Hexagon::S45_44, .ToReg: 188U }, |
| 3583 | { .FromReg: Hexagon::S47_46, .ToReg: 190U }, |
| 3584 | { .FromReg: Hexagon::S49_48, .ToReg: 192U }, |
| 3585 | { .FromReg: Hexagon::S51_50, .ToReg: 194U }, |
| 3586 | { .FromReg: Hexagon::S53_52, .ToReg: 196U }, |
| 3587 | { .FromReg: Hexagon::S55_54, .ToReg: 198U }, |
| 3588 | { .FromReg: Hexagon::S57_56, .ToReg: 200U }, |
| 3589 | { .FromReg: Hexagon::S59_58, .ToReg: 202U }, |
| 3590 | { .FromReg: Hexagon::S61_60, .ToReg: 204U }, |
| 3591 | { .FromReg: Hexagon::S63_62, .ToReg: 206U }, |
| 3592 | { .FromReg: Hexagon::S65_64, .ToReg: 208U }, |
| 3593 | { .FromReg: Hexagon::S67_66, .ToReg: 210U }, |
| 3594 | { .FromReg: Hexagon::S69_68, .ToReg: 212U }, |
| 3595 | { .FromReg: Hexagon::S71_70, .ToReg: 214U }, |
| 3596 | { .FromReg: Hexagon::S73_72, .ToReg: 216U }, |
| 3597 | { .FromReg: Hexagon::S75_74, .ToReg: 218U }, |
| 3598 | { .FromReg: Hexagon::S77_76, .ToReg: 219U }, |
| 3599 | { .FromReg: Hexagon::S79_78, .ToReg: 220U }, |
| 3600 | { .FromReg: Hexagon::SGP1_0, .ToReg: 144U }, |
| 3601 | }; |
| 3602 | extern const unsigned HexagonEHFlavour0L2DwarfSize = std::size(HexagonEHFlavour0L2Dwarf); |
| 3603 | |
| 3604 | extern const uint16_t HexagonRegEncodingTable[] = { |
| 3605 | 0, |
| 3606 | 9, |
| 3607 | 7, |
| 3608 | 27, |
| 3609 | 12, |
| 3610 | 28, |
| 3611 | 3, |
| 3612 | 16, |
| 3613 | 17, |
| 3614 | 16, |
| 3615 | 0, |
| 3616 | 2, |
| 3617 | 11, |
| 3618 | 25, |
| 3619 | 24, |
| 3620 | 1, |
| 3621 | 8, |
| 3622 | 10, |
| 3623 | 42, |
| 3624 | 43, |
| 3625 | 40, |
| 3626 | 41, |
| 3627 | 32, |
| 3628 | 17, |
| 3629 | 9, |
| 3630 | 31, |
| 3631 | 30, |
| 3632 | 18, |
| 3633 | 19, |
| 3634 | 18, |
| 3635 | 53, |
| 3636 | 52, |
| 3637 | 29, |
| 3638 | 6, |
| 3639 | 2, |
| 3640 | 18, |
| 3641 | 10, |
| 3642 | 14, |
| 3643 | 15, |
| 3644 | 14, |
| 3645 | 8, |
| 3646 | 0, |
| 3647 | 30, |
| 3648 | 31, |
| 3649 | 30, |
| 3650 | 21, |
| 3651 | 0, |
| 3652 | 4, |
| 3653 | 5, |
| 3654 | 37, |
| 3655 | 39, |
| 3656 | 36, |
| 3657 | 38, |
| 3658 | 5, |
| 3659 | 8, |
| 3660 | 12, |
| 3661 | 13, |
| 3662 | 0, |
| 3663 | 2, |
| 3664 | 4, |
| 3665 | 6, |
| 3666 | 8, |
| 3667 | 10, |
| 3668 | 12, |
| 3669 | 14, |
| 3670 | 16, |
| 3671 | 18, |
| 3672 | 20, |
| 3673 | 22, |
| 3674 | 24, |
| 3675 | 26, |
| 3676 | 28, |
| 3677 | 30, |
| 3678 | 3, |
| 3679 | 4, |
| 3680 | 5, |
| 3681 | 6, |
| 3682 | 7, |
| 3683 | 8, |
| 3684 | 9, |
| 3685 | 10, |
| 3686 | 11, |
| 3687 | 12, |
| 3688 | 13, |
| 3689 | 14, |
| 3690 | 15, |
| 3691 | 20, |
| 3692 | 21, |
| 3693 | 22, |
| 3694 | 23, |
| 3695 | 30, |
| 3696 | 31, |
| 3697 | 26, |
| 3698 | 27, |
| 3699 | 28, |
| 3700 | 29, |
| 3701 | 16, |
| 3702 | 17, |
| 3703 | 18, |
| 3704 | 19, |
| 3705 | 33, |
| 3706 | 34, |
| 3707 | 1, |
| 3708 | 3, |
| 3709 | 6, |
| 3710 | 7, |
| 3711 | 0, |
| 3712 | 1, |
| 3713 | 2, |
| 3714 | 3, |
| 3715 | 48, |
| 3716 | 49, |
| 3717 | 50, |
| 3718 | 51, |
| 3719 | 0, |
| 3720 | 1, |
| 3721 | 2, |
| 3722 | 3, |
| 3723 | 0, |
| 3724 | 1, |
| 3725 | 2, |
| 3726 | 3, |
| 3727 | 4, |
| 3728 | 5, |
| 3729 | 6, |
| 3730 | 7, |
| 3731 | 8, |
| 3732 | 9, |
| 3733 | 10, |
| 3734 | 11, |
| 3735 | 12, |
| 3736 | 13, |
| 3737 | 14, |
| 3738 | 15, |
| 3739 | 16, |
| 3740 | 17, |
| 3741 | 18, |
| 3742 | 19, |
| 3743 | 20, |
| 3744 | 21, |
| 3745 | 22, |
| 3746 | 23, |
| 3747 | 24, |
| 3748 | 25, |
| 3749 | 26, |
| 3750 | 27, |
| 3751 | 28, |
| 3752 | 29, |
| 3753 | 30, |
| 3754 | 31, |
| 3755 | 11, |
| 3756 | 12, |
| 3757 | 13, |
| 3758 | 14, |
| 3759 | 15, |
| 3760 | 19, |
| 3761 | 20, |
| 3762 | 22, |
| 3763 | 23, |
| 3764 | 24, |
| 3765 | 25, |
| 3766 | 26, |
| 3767 | 35, |
| 3768 | 44, |
| 3769 | 45, |
| 3770 | 46, |
| 3771 | 47, |
| 3772 | 54, |
| 3773 | 55, |
| 3774 | 56, |
| 3775 | 57, |
| 3776 | 58, |
| 3777 | 59, |
| 3778 | 60, |
| 3779 | 61, |
| 3780 | 62, |
| 3781 | 63, |
| 3782 | 64, |
| 3783 | 65, |
| 3784 | 66, |
| 3785 | 67, |
| 3786 | 68, |
| 3787 | 69, |
| 3788 | 70, |
| 3789 | 71, |
| 3790 | 72, |
| 3791 | 73, |
| 3792 | 74, |
| 3793 | 75, |
| 3794 | 76, |
| 3795 | 77, |
| 3796 | 78, |
| 3797 | 79, |
| 3798 | 80, |
| 3799 | 0, |
| 3800 | 2, |
| 3801 | 0, |
| 3802 | 1, |
| 3803 | 0, |
| 3804 | 1, |
| 3805 | 2, |
| 3806 | 3, |
| 3807 | 4, |
| 3808 | 5, |
| 3809 | 6, |
| 3810 | 7, |
| 3811 | 8, |
| 3812 | 9, |
| 3813 | 10, |
| 3814 | 11, |
| 3815 | 12, |
| 3816 | 13, |
| 3817 | 14, |
| 3818 | 15, |
| 3819 | 16, |
| 3820 | 17, |
| 3821 | 18, |
| 3822 | 19, |
| 3823 | 20, |
| 3824 | 21, |
| 3825 | 22, |
| 3826 | 23, |
| 3827 | 24, |
| 3828 | 25, |
| 3829 | 26, |
| 3830 | 27, |
| 3831 | 28, |
| 3832 | 29, |
| 3833 | 30, |
| 3834 | 31, |
| 3835 | 0, |
| 3836 | 0, |
| 3837 | 0, |
| 3838 | 0, |
| 3839 | 0, |
| 3840 | 0, |
| 3841 | 0, |
| 3842 | 0, |
| 3843 | 0, |
| 3844 | 0, |
| 3845 | 0, |
| 3846 | 0, |
| 3847 | 0, |
| 3848 | 0, |
| 3849 | 0, |
| 3850 | 0, |
| 3851 | 0, |
| 3852 | 0, |
| 3853 | 0, |
| 3854 | 0, |
| 3855 | 0, |
| 3856 | 0, |
| 3857 | 0, |
| 3858 | 0, |
| 3859 | 0, |
| 3860 | 0, |
| 3861 | 0, |
| 3862 | 0, |
| 3863 | 0, |
| 3864 | 0, |
| 3865 | 0, |
| 3866 | 0, |
| 3867 | 0, |
| 3868 | 0, |
| 3869 | 0, |
| 3870 | 0, |
| 3871 | 0, |
| 3872 | 0, |
| 3873 | 0, |
| 3874 | 0, |
| 3875 | 0, |
| 3876 | 0, |
| 3877 | 0, |
| 3878 | 0, |
| 3879 | 0, |
| 3880 | 0, |
| 3881 | 0, |
| 3882 | 0, |
| 3883 | 0, |
| 3884 | 0, |
| 3885 | 0, |
| 3886 | 0, |
| 3887 | 0, |
| 3888 | 0, |
| 3889 | 0, |
| 3890 | 0, |
| 3891 | 0, |
| 3892 | 0, |
| 3893 | 0, |
| 3894 | 0, |
| 3895 | 0, |
| 3896 | 0, |
| 3897 | 0, |
| 3898 | 0, |
| 3899 | 0, |
| 3900 | 4, |
| 3901 | 8, |
| 3902 | 12, |
| 3903 | 16, |
| 3904 | 20, |
| 3905 | 24, |
| 3906 | 28, |
| 3907 | 0, |
| 3908 | 2, |
| 3909 | 4, |
| 3910 | 6, |
| 3911 | 8, |
| 3912 | 10, |
| 3913 | 12, |
| 3914 | 14, |
| 3915 | 16, |
| 3916 | 18, |
| 3917 | 20, |
| 3918 | 22, |
| 3919 | 24, |
| 3920 | 26, |
| 3921 | 28, |
| 3922 | 30, |
| 3923 | 1, |
| 3924 | 3, |
| 3925 | 5, |
| 3926 | 7, |
| 3927 | 9, |
| 3928 | 11, |
| 3929 | 13, |
| 3930 | 15, |
| 3931 | 17, |
| 3932 | 19, |
| 3933 | 21, |
| 3934 | 23, |
| 3935 | 25, |
| 3936 | 27, |
| 3937 | 29, |
| 3938 | 31, |
| 3939 | 0, |
| 3940 | 2, |
| 3941 | 4, |
| 3942 | 6, |
| 3943 | 8, |
| 3944 | 10, |
| 3945 | 16, |
| 3946 | 0, |
| 3947 | 2, |
| 3948 | 4, |
| 3949 | 6, |
| 3950 | 8, |
| 3951 | 10, |
| 3952 | 12, |
| 3953 | 14, |
| 3954 | 16, |
| 3955 | 18, |
| 3956 | 20, |
| 3957 | 22, |
| 3958 | 24, |
| 3959 | 26, |
| 3960 | 28, |
| 3961 | 30, |
| 3962 | 4, |
| 3963 | 2, |
| 3964 | 4, |
| 3965 | 6, |
| 3966 | 8, |
| 3967 | 10, |
| 3968 | 12, |
| 3969 | 14, |
| 3970 | 16, |
| 3971 | 18, |
| 3972 | 20, |
| 3973 | 22, |
| 3974 | 24, |
| 3975 | 26, |
| 3976 | 28, |
| 3977 | 30, |
| 3978 | 32, |
| 3979 | 34, |
| 3980 | 36, |
| 3981 | 38, |
| 3982 | 40, |
| 3983 | 42, |
| 3984 | 44, |
| 3985 | 46, |
| 3986 | 48, |
| 3987 | 50, |
| 3988 | 52, |
| 3989 | 54, |
| 3990 | 56, |
| 3991 | 58, |
| 3992 | 60, |
| 3993 | 62, |
| 3994 | 64, |
| 3995 | 66, |
| 3996 | 68, |
| 3997 | 70, |
| 3998 | 72, |
| 3999 | 74, |
| 4000 | 76, |
| 4001 | 78, |
| 4002 | 0, |
| 4003 | }; |
| 4004 | static inline void InitHexagonMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
| 4005 | RI->InitMCRegisterInfo(D: HexagonRegDesc, NR: 398, RA, PC, C: HexagonMCRegisterClassStorage.Classes, NC: 29, RURoots: HexagonRegUnitRoots, NRU: 278, DL: HexagonRegDiffLists, RUMS: HexagonLaneMaskLists, Strings: HexagonRegStrings, ClassStrings: HexagonRegClassStrings, SubIndices: HexagonSubRegIdxLists, NumIndices: 11, |
| 4006 | RET: HexagonRegEncodingTable, RUI: nullptr); |
| 4007 | |
| 4008 | switch (DwarfFlavour) { |
| 4009 | default: |
| 4010 | llvm_unreachable("Unknown DWARF flavour" ); |
| 4011 | case 0: |
| 4012 | RI->mapDwarfRegsToLLVMRegs(Map: HexagonDwarfFlavour0Dwarf2L, Size: HexagonDwarfFlavour0Dwarf2LSize, isEH: false); |
| 4013 | break; |
| 4014 | } |
| 4015 | switch (EHFlavour) { |
| 4016 | default: |
| 4017 | llvm_unreachable("Unknown DWARF flavour" ); |
| 4018 | case 0: |
| 4019 | RI->mapDwarfRegsToLLVMRegs(Map: HexagonEHFlavour0Dwarf2L, Size: HexagonEHFlavour0Dwarf2LSize, isEH: true); |
| 4020 | break; |
| 4021 | } |
| 4022 | switch (DwarfFlavour) { |
| 4023 | default: |
| 4024 | llvm_unreachable("Unknown DWARF flavour" ); |
| 4025 | case 0: |
| 4026 | RI->mapLLVMRegsToDwarfRegs(Map: HexagonDwarfFlavour0L2Dwarf, Size: HexagonDwarfFlavour0L2DwarfSize, isEH: false); |
| 4027 | break; |
| 4028 | } |
| 4029 | switch (EHFlavour) { |
| 4030 | default: |
| 4031 | llvm_unreachable("Unknown DWARF flavour" ); |
| 4032 | case 0: |
| 4033 | RI->mapLLVMRegsToDwarfRegs(Map: HexagonEHFlavour0L2Dwarf, Size: HexagonEHFlavour0L2DwarfSize, isEH: true); |
| 4034 | break; |
| 4035 | } |
| 4036 | } |
| 4037 | |
| 4038 | |
| 4039 | } // namespace llvm |
| 4040 | |