1//===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Hexagon specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/HexagonMCTargetDesc.h"
14#include "HexagonDepArch.h"
15#include "HexagonTargetStreamer.h"
16#include "MCTargetDesc/HexagonInstPrinter.h"
17#include "MCTargetDesc/HexagonMCAsmInfo.h"
18#include "MCTargetDesc/HexagonMCELFStreamer.h"
19#include "MCTargetDesc/HexagonMCInstrInfo.h"
20#include "TargetInfo/HexagonTargetInfo.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/StringMap.h"
23#include "llvm/ADT/StringRef.h"
24#include "llvm/BinaryFormat/ELF.h"
25#include "llvm/MC/MCAsmBackend.h"
26#include "llvm/MC/MCAssembler.h"
27#include "llvm/MC/MCCodeEmitter.h"
28#include "llvm/MC/MCContext.h"
29#include "llvm/MC/MCDwarf.h"
30#include "llvm/MC/MCELFObjectWriter.h"
31#include "llvm/MC/MCELFStreamer.h"
32#include "llvm/MC/MCInstrAnalysis.h"
33#include "llvm/MC/MCInstrInfo.h"
34#include "llvm/MC/MCRegisterInfo.h"
35#include "llvm/MC/MCStreamer.h"
36#include "llvm/MC/MCSubtargetInfo.h"
37#include "llvm/MC/TargetRegistry.h"
38#include "llvm/Support/Compiler.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/HexagonAttributes.h"
41#include "llvm/Support/raw_ostream.h"
42#include <cassert>
43#include <cstdint>
44#include <mutex>
45#include <new>
46#include <string>
47
48using namespace llvm;
49
50#define GET_INSTRINFO_MC_DESC
51#define ENABLE_INSTR_PREDICATE_VERIFIER
52#include "HexagonGenInstrInfo.inc"
53
54#define GET_SUBTARGETINFO_MC_DESC
55#include "HexagonGenSubtargetInfo.inc"
56
57#define GET_REGINFO_MC_DESC
58#include "HexagonGenRegisterInfo.inc"
59
60cl::opt<bool> llvm::HexagonDisableCompound
61 ("mno-compound",
62 cl::desc("Disable looking for compound instructions for Hexagon"));
63
64cl::opt<bool> llvm::HexagonDisableDuplex
65 ("mno-pairing",
66 cl::desc("Disable looking for duplex instructions for Hexagon"));
67
68namespace { // These flags are to be deprecated
69cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
70 cl::init(Val: false));
71cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
72 cl::init(Val: false));
73cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
74 cl::init(Val: false));
75cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
76 cl::init(Val: false));
77cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
78 cl::init(Val: false));
79cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
80 cl::init(Val: false));
81cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
82 cl::init(Val: false));
83cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
84 cl::init(Val: false));
85cl::opt<bool> MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"),
86 cl::init(Val: false));
87cl::opt<bool> MV69("mv69", cl::Hidden, cl::desc("Build for Hexagon V69"),
88 cl::init(Val: false));
89cl::opt<bool> MV71("mv71", cl::Hidden, cl::desc("Build for Hexagon V71"),
90 cl::init(Val: false));
91cl::opt<bool> MV71T("mv71t", cl::Hidden, cl::desc("Build for Hexagon V71T"),
92 cl::init(Val: false));
93cl::opt<bool> MV73("mv73", cl::Hidden, cl::desc("Build for Hexagon V73"),
94 cl::init(Val: false));
95cl::opt<bool> MV75("mv75", cl::Hidden, cl::desc("Build for Hexagon V75"),
96 cl::init(Val: false));
97cl::opt<bool> MV79("mv79", cl::Hidden, cl::desc("Build for Hexagon V79"),
98 cl::init(Val: false));
99cl::opt<bool> MV81("mv81", cl::Hidden, cl::desc("Build for Hexagon V81"),
100 cl::init(Val: false));
101} // namespace
102
103static cl::opt<Hexagon::ArchEnum> EnableHVX(
104 "mhvx", cl::desc("Enable Hexagon Vector eXtensions"),
105 cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
106 clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
107 clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
108 clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
109 clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
110 clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
111 clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"),
112 clEnumValN(Hexagon::ArchEnum::V71, "v71", "Build for HVX v71"),
113 clEnumValN(Hexagon::ArchEnum::V73, "v73", "Build for HVX v73"),
114 clEnumValN(Hexagon::ArchEnum::V75, "v75", "Build for HVX v75"),
115 clEnumValN(Hexagon::ArchEnum::V79, "v79", "Build for HVX v79"),
116 clEnumValN(Hexagon::ArchEnum::V81, "v81", "Build for HVX v81"),
117 // Sentinel for no value specified.
118 clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
119 // Sentinel for flag not present.
120 cl::init(Val: Hexagon::ArchEnum::NoArch), cl::ValueOptional);
121
122static cl::opt<bool>
123 DisableHVX("mno-hvx", cl::Hidden,
124 cl::desc("Disable Hexagon Vector eXtensions"));
125
126static cl::opt<bool>
127 EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden,
128 cl::desc("Enable HVX IEEE floating point extensions"));
129static cl::opt<bool> EnableHexagonCabac
130 ("mcabac", cl::desc("tbd"), cl::init(Val: false));
131
132static constexpr StringRef DefaultArch = "hexagonv68";
133
134static StringRef HexagonGetArchVariant() {
135 if (MV5)
136 return "hexagonv5";
137 if (MV55)
138 return "hexagonv55";
139 if (MV60)
140 return "hexagonv60";
141 if (MV62)
142 return "hexagonv62";
143 if (MV65)
144 return "hexagonv65";
145 if (MV66)
146 return "hexagonv66";
147 if (MV67)
148 return "hexagonv67";
149 if (MV67T)
150 return "hexagonv67t";
151 if (MV68)
152 return "hexagonv68";
153 if (MV69)
154 return "hexagonv69";
155 if (MV71)
156 return "hexagonv71";
157 if (MV71T)
158 return "hexagonv71t";
159 if (MV73)
160 return "hexagonv73";
161 if (MV75)
162 return "hexagonv75";
163 if (MV79)
164 return "hexagonv79";
165 if (MV81)
166 return "hexagonv81";
167
168 return "";
169}
170
171StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
172 StringRef ArchV = HexagonGetArchVariant();
173 if (!ArchV.empty() && !CPU.empty()) {
174 // Tiny cores have a "t" suffix that is discarded when creating a secondary
175 // non-tiny subtarget. See: addArchSubtarget
176 std::pair<StringRef, StringRef> ArchP = ArchV.split(Separator: 't');
177 std::pair<StringRef, StringRef> CPUP = CPU.split(Separator: 't');
178 if (ArchP.first != CPUP.first)
179 report_fatal_error(reason: "conflicting architectures specified.");
180 return CPU;
181 }
182 if (ArchV.empty()) {
183 if (CPU.empty())
184 CPU = DefaultArch;
185 return CPU;
186 }
187 return ArchV;
188}
189
190unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
191
192unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
193 enum {
194 CVI_NONE = 0,
195 CVI_XLANE = 1 << 0,
196 CVI_SHIFT = 1 << 1,
197 CVI_MPY0 = 1 << 2,
198 CVI_MPY1 = 1 << 3,
199 CVI_ZW = 1 << 4
200 };
201
202 if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
203 ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
204 return (*Lanes = 4, CVI_XLANE);
205 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
206 ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
207 return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
208 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
209 return (*Lanes = 2, CVI_MPY0);
210 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
211 return (*Lanes = 2, CVI_XLANE);
212 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
213 ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
214 ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
215 ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
216 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
217 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
218 ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
219 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
220 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
221 ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
222 return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
223 else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
224 return (*Lanes = 1, CVI_ZW);
225 else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
226 return (*Lanes = 1, CVI_XLANE);
227 else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
228 return (*Lanes = 1, CVI_SHIFT);
229
230 return (*Lanes = 0, CVI_NONE);
231}
232
233
234namespace llvm {
235namespace HexagonFUnits {
236bool isSlot0Only(unsigned units) {
237 return HexagonItinerariesV62FU::SLOT0 == units;
238}
239} // namespace HexagonFUnits
240} // namespace llvm
241
242namespace {
243
244class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
245 formatted_raw_ostream &OS;
246
247public:
248 HexagonTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS,
249 MCInstPrinter &IP)
250 : HexagonTargetStreamer(S), OS(OS) {}
251
252 void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
253 const MCInst &Inst, const MCSubtargetInfo &STI,
254 raw_ostream &OS) override {
255 assert(HexagonMCInstrInfo::isBundle(Inst));
256 assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
257 std::string Buffer;
258 {
259 raw_string_ostream TempStream(Buffer);
260 for (auto &I : HexagonMCInstrInfo::bundleInstructions(MCI: Inst)) {
261 InstPrinter.printInst(MI: I.getInst(), Address, Annot: "", STI, OS&: TempStream);
262 TempStream << "\n";
263 }
264 }
265
266 std::string LoopString = "";
267 bool IsLoop0 = HexagonMCInstrInfo::isInnerLoop(MCI: Inst);
268 bool IsLoop1 = HexagonMCInstrInfo::isOuterLoop(MCI: Inst);
269 if (IsLoop0) {
270 LoopString += (IsLoop1 ? " :endloop01" : " :endloop0");
271 } else if (IsLoop1) {
272 LoopString += " :endloop1";
273 }
274
275 StringRef Contents(Buffer);
276 auto PacketBundle = Contents.rsplit(Separator: '\n');
277 auto HeadTail = PacketBundle.first.split(Separator: '\n');
278 StringRef Separator = "\n";
279 StringRef Indent = "\t";
280 OS << "\t{\n";
281 while (!HeadTail.first.empty()) {
282 StringRef InstTxt;
283 auto Duplex = HeadTail.first.split(Separator: '\v');
284 if (!Duplex.second.empty()) {
285 OS << Indent << Duplex.first << Separator;
286 InstTxt = Duplex.second;
287 } else if (!HeadTail.first.trim().starts_with(Prefix: "immext")) {
288 InstTxt = Duplex.first;
289 }
290 if (!InstTxt.empty())
291 OS << Indent << InstTxt << Separator;
292 HeadTail = HeadTail.second.split(Separator: '\n');
293 }
294
295 if (HexagonMCInstrInfo::isMemReorderDisabled(MCI: Inst))
296 OS << "\n\t} :mem_noshuf" << LoopString;
297 else
298 OS << "\t}" << LoopString;
299 }
300
301 void finish() override { finishAttributeSection(); }
302
303 void finishAttributeSection() override {}
304
305 void emitAttribute(unsigned Attribute, unsigned Value) override {
306 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value);
307 if (getStreamer().isVerboseAsm()) {
308 StringRef Name = ELFAttrs::attrTypeAsString(
309 attr: Attribute, tagNameMap: HexagonAttrs::getHexagonAttributeTags());
310 if (!Name.empty())
311 OS << "\t// " << Name;
312 }
313 OS << "\n";
314 }
315};
316
317class HexagonTargetELFStreamer : public HexagonTargetStreamer {
318public:
319 MCELFStreamer &getStreamer() {
320 return static_cast<MCELFStreamer &>(Streamer);
321 }
322 HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
323 : HexagonTargetStreamer(S) {
324 getStreamer().getWriter().setELFHeaderEFlags(Hexagon_MC::GetELFFlags(STI));
325 }
326
327 void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
328 unsigned ByteAlignment,
329 unsigned AccessSize) override {
330 HexagonMCELFStreamer &HexagonELFStreamer =
331 static_cast<HexagonMCELFStreamer &>(getStreamer());
332 HexagonELFStreamer.HexagonMCEmitCommonSymbol(
333 Symbol, Size, ByteAlignment: Align(ByteAlignment), AccessSize);
334 }
335
336 void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
337 unsigned ByteAlignment,
338 unsigned AccessSize) override {
339 HexagonMCELFStreamer &HexagonELFStreamer =
340 static_cast<HexagonMCELFStreamer &>(getStreamer());
341 HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
342 Symbol, Size, ByteAlignment: Align(ByteAlignment), AccessSize);
343 }
344
345 void finish() override { finishAttributeSection(); }
346
347 void reset() override { AttributeSection = nullptr; }
348
349private:
350 MCSection *AttributeSection = nullptr;
351
352 void finishAttributeSection() override {
353 MCELFStreamer &S = getStreamer();
354 if (S.Contents.empty())
355 return;
356
357 S.emitAttributesSection(Vendor: "hexagon", Section: ".hexagon.attributes",
358 Type: ELF::SHT_HEXAGON_ATTRIBUTES, AttributeSection);
359 }
360
361 void emitAttribute(uint32_t Attribute, uint32_t Value) override {
362 getStreamer().setAttributeItem(Attribute, Value,
363 /*OverwriteExisting=*/true);
364 }
365};
366
367} // end anonymous namespace
368
369llvm::MCInstrInfo *llvm::createHexagonMCInstrInfo() {
370 MCInstrInfo *X = new MCInstrInfo();
371 InitHexagonMCInstrInfo(II: X);
372 return X;
373}
374
375static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
376 MCRegisterInfo *X = new MCRegisterInfo();
377 InitHexagonMCRegisterInfo(RI: X, RA: Hexagon::R31, /*DwarfFlavour=*/0,
378 /*EHFlavour=*/0, /*PC=*/Hexagon::PC);
379 return X;
380}
381
382static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
383 const Triple &TT,
384 const MCTargetOptions &Options) {
385 MCAsmInfo *MAI = new HexagonMCAsmInfo(TT, Options);
386
387 // VirtualFP = (R30 + #0).
388 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
389 L: nullptr, Register: MRI.getDwarfRegNum(Reg: Hexagon::R30, isEH: true), Offset: 0);
390 MAI->addInitialFrameState(Inst);
391
392 return MAI;
393}
394
395static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
396 unsigned SyntaxVariant,
397 const MCAsmInfo &MAI,
398 const MCInstrInfo &MII,
399 const MCRegisterInfo &MRI)
400{
401 if (SyntaxVariant == 0)
402 return new HexagonInstPrinter(MAI, MII, MRI);
403 else
404 return nullptr;
405}
406
407static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S,
408 formatted_raw_ostream &OS,
409 MCInstPrinter *IP) {
410 return new HexagonTargetAsmStreamer(S, OS, *IP);
411}
412
413static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
414 std::unique_ptr<MCAsmBackend> &&MAB,
415 std::unique_ptr<MCObjectWriter> &&OW,
416 std::unique_ptr<MCCodeEmitter> &&Emitter) {
417 return createHexagonELFStreamer(TT: T, Context, MAB: std::move(MAB), OW: std::move(OW),
418 CE: std::move(Emitter));
419}
420
421static MCTargetStreamer *
422createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
423 return new HexagonTargetELFStreamer(S, STI);
424}
425
426static MCTargetStreamer *createHexagonNullTargetStreamer(MCStreamer &S) {
427 return new HexagonTargetStreamer(S);
428}
429
430[[maybe_unused]] static void clearFeature(MCSubtargetInfo *STI, uint64_t F) {
431 if (STI->hasFeature(Feature: F))
432 STI->ToggleFeature(FB: F);
433}
434
435[[maybe_unused]] static bool checkFeature(MCSubtargetInfo *STI, uint64_t F) {
436 return STI->hasFeature(Feature: F);
437}
438
439namespace {
440std::string selectHexagonFS(StringRef CPU, StringRef FS) {
441 SmallVector<StringRef, 3> Result;
442 if (!FS.empty())
443 Result.push_back(Elt: FS);
444
445 switch (EnableHVX) {
446 case Hexagon::ArchEnum::V5:
447 case Hexagon::ArchEnum::V55:
448 break;
449 case Hexagon::ArchEnum::V60:
450 Result.push_back(Elt: "+hvxv60");
451 break;
452 case Hexagon::ArchEnum::V62:
453 Result.push_back(Elt: "+hvxv62");
454 break;
455 case Hexagon::ArchEnum::V65:
456 Result.push_back(Elt: "+hvxv65");
457 break;
458 case Hexagon::ArchEnum::V66:
459 Result.push_back(Elt: "+hvxv66");
460 break;
461 case Hexagon::ArchEnum::V67:
462 Result.push_back(Elt: "+hvxv67");
463 break;
464 case Hexagon::ArchEnum::V68:
465 Result.push_back(Elt: "+hvxv68");
466 break;
467 case Hexagon::ArchEnum::V69:
468 Result.push_back(Elt: "+hvxv69");
469 break;
470 case Hexagon::ArchEnum::V71:
471 Result.push_back(Elt: "+hvxv71");
472 break;
473 case Hexagon::ArchEnum::V73:
474 Result.push_back(Elt: "+hvxv73");
475 break;
476 case Hexagon::ArchEnum::V75:
477 Result.push_back(Elt: "+hvxv75");
478 break;
479 case Hexagon::ArchEnum::V79:
480 Result.push_back(Elt: "+hvxv79");
481 break;
482 case Hexagon::ArchEnum::V81:
483 Result.push_back(Elt: "+hvxv81");
484 break;
485
486 case Hexagon::ArchEnum::Generic: {
487 Result.push_back(Elt: StringSwitch<StringRef>(CPU)
488 .Case(S: "hexagonv60", Value: "+hvxv60")
489 .Case(S: "hexagonv62", Value: "+hvxv62")
490 .Case(S: "hexagonv65", Value: "+hvxv65")
491 .Case(S: "hexagonv66", Value: "+hvxv66")
492 .Case(S: "hexagonv67", Value: "+hvxv67")
493 .Case(S: "hexagonv67t", Value: "+hvxv67")
494 .Case(S: "hexagonv68", Value: "+hvxv68")
495 .Case(S: "hexagonv69", Value: "+hvxv69")
496 .Case(S: "hexagonv71", Value: "+hvxv71")
497 .Case(S: "hexagonv71t", Value: "+hvxv71")
498 .Case(S: "hexagonv73", Value: "+hvxv73")
499 .Case(S: "hexagonv75", Value: "+hvxv75")
500 .Case(S: "hexagonv79", Value: "+hvxv79")
501 .Case(S: "hexagonv81", Value: "+hvxv81"));
502 break;
503 }
504 case Hexagon::ArchEnum::NoArch:
505 // Sentinel if -mhvx isn't specified
506 break;
507 }
508 if (EnableHvxIeeeFp)
509 Result.push_back(Elt: "+hvx-ieee-fp");
510 if (EnableHexagonCabac)
511 Result.push_back(Elt: "+cabac");
512
513 return join(Begin: Result.begin(), End: Result.end(), Separator: ",");
514}
515}
516
517static bool isCPUValid(StringRef CPU) {
518 return Hexagon::getCpu(CPU).has_value();
519}
520
521namespace {
522std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
523 StringRef FS) {
524 std::pair<std::string, std::string> Result;
525 Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
526 Result.second = selectHexagonFS(CPU: Result.first, FS);
527 return Result;
528}
529std::mutex ArchSubtargetMutex;
530StringMap<std::unique_ptr<MCSubtargetInfo const>> ArchSubtarget;
531} // namespace
532
533MCSubtargetInfo const *
534Hexagon_MC::getArchSubtarget(MCSubtargetInfo const *STI) {
535 std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
536 auto Existing = ArchSubtarget.find(Key: STI->getCPU());
537 if (Existing == ArchSubtarget.end())
538 return nullptr;
539 return Existing->second.get();
540}
541
542FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
543 using namespace Hexagon;
544 // Make sure that +hvx-length turns hvx on, and that "hvx" alone
545 // turns on hvxvNN, corresponding to the existing ArchVNN.
546 FeatureBitset FB = S;
547 unsigned CpuArch = ArchV5;
548 for (unsigned F :
549 {ArchV81, ArchV79, ArchV75, ArchV73, ArchV71, ArchV69, ArchV68, ArchV67,
550 ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
551 if (!FB.test(I: F))
552 continue;
553 CpuArch = F;
554 break;
555 }
556 bool UseHvx = false;
557 for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
558 if (!FB.test(I: F))
559 continue;
560 UseHvx = true;
561 break;
562 }
563 bool HasHvxVer = false;
564 for (unsigned F :
565 {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
566 ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
567 ExtensionHVXV73, ExtensionHVXV75, ExtensionHVXV79, ExtensionHVXV81}) {
568 if (!FB.test(I: F))
569 continue;
570 HasHvxVer = true;
571 UseHvx = true;
572 break;
573 }
574
575 if (!UseHvx || HasHvxVer)
576 return FB;
577
578 // HasHvxVer is false, and UseHvx is true.
579 switch (CpuArch) {
580 case ArchV81:
581 FB.set(ExtensionHVXV81);
582 [[fallthrough]];
583 case ArchV79:
584 FB.set(ExtensionHVXV79);
585 [[fallthrough]];
586 case ArchV75:
587 FB.set(ExtensionHVXV75);
588 [[fallthrough]];
589 case ArchV73:
590 FB.set(ExtensionHVXV73);
591 [[fallthrough]];
592 case ArchV71:
593 FB.set(ExtensionHVXV71);
594 [[fallthrough]];
595 case ArchV69:
596 FB.set(ExtensionHVXV69);
597 [[fallthrough]];
598 case ArchV68:
599 FB.set(ExtensionHVXV68);
600 [[fallthrough]];
601 case ArchV67:
602 FB.set(ExtensionHVXV67);
603 [[fallthrough]];
604 case ArchV66:
605 FB.set(ExtensionHVXV66);
606 [[fallthrough]];
607 case ArchV65:
608 FB.set(ExtensionHVXV65);
609 [[fallthrough]];
610 case ArchV62:
611 FB.set(ExtensionHVXV62);
612 [[fallthrough]];
613 case ArchV60:
614 FB.set(ExtensionHVXV60);
615 break;
616 }
617 return FB;
618}
619
620MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
621 StringRef CPU,
622 StringRef FS) {
623 std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
624 StringRef CPUName = Features.first;
625 StringRef ArchFS = Features.second;
626
627 MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
628 TT, CPU: CPUName, /*TuneCPU*/ CPUName, FS: ArchFS);
629 if (X != nullptr && (CPUName == "hexagonv67t" || CPUName == "hexagon71t"))
630 addArchSubtarget(STI: X, FS: ArchFS);
631
632 if (CPU == "help")
633 exit(status: 0);
634
635 if (!isCPUValid(CPU: CPUName.str())) {
636 errs() << "error: invalid CPU \"" << CPUName.str().c_str()
637 << "\" specified\n";
638 return nullptr;
639 }
640
641 // Add qfloat subtarget feature by default to v68 and above
642 // unless explicitly disabled
643 if (checkFeature(STI: X, F: Hexagon::ExtensionHVXV68) &&
644 !ArchFS.contains(Other: "-hvx-qfloat")) {
645 llvm::FeatureBitset Features = X->getFeatureBits();
646 X->setFeatureBits(Features.set(Hexagon::ExtensionHVXQFloat));
647 }
648
649 if (HexagonDisableDuplex) {
650 llvm::FeatureBitset Features = X->getFeatureBits();
651 X->setFeatureBits(Features.reset(I: Hexagon::FeatureDuplex));
652 }
653
654 X->setFeatureBits(completeHVXFeatures(S: X->getFeatureBits()));
655
656 // The Z-buffer instructions are grandfathered in for current
657 // architectures but omitted for new ones. Future instruction
658 // sets may introduce new/conflicting z-buffer instructions.
659 const bool ZRegOnDefault =
660 (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
661 if (ZRegOnDefault) {
662 llvm::FeatureBitset Features = X->getFeatureBits();
663 X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
664 }
665
666 return X;
667}
668
669void Hexagon_MC::addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS) {
670 assert(STI != nullptr);
671 if (STI->getCPU().contains(Other: "t")) {
672 auto ArchSTI = createHexagonMCSubtargetInfo(TT: STI->getTargetTriple(),
673 CPU: STI->getCPU().drop_back(), FS);
674 std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
675 ArchSubtarget[STI->getCPU()] =
676 std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
677 }
678}
679
680std::optional<unsigned>
681Hexagon_MC::getHVXVersion(const FeatureBitset &Features) {
682 for (auto Arch : {Hexagon::ExtensionHVXV81, Hexagon::ExtensionHVXV79,
683 Hexagon::ExtensionHVXV75, Hexagon::ExtensionHVXV73,
684 Hexagon::ExtensionHVXV71, Hexagon::ExtensionHVXV69,
685 Hexagon::ExtensionHVXV68, Hexagon::ExtensionHVXV67,
686 Hexagon::ExtensionHVXV66, Hexagon::ExtensionHVXV65,
687 Hexagon::ExtensionHVXV62, Hexagon::ExtensionHVXV60})
688 if (Features.test(I: Arch))
689 return Arch;
690 return {};
691}
692
693unsigned Hexagon_MC::getArchVersion(const FeatureBitset &Features) {
694 for (auto Arch :
695 {Hexagon::ArchV81, Hexagon::ArchV79, Hexagon::ArchV75, Hexagon::ArchV73,
696 Hexagon::ArchV71, Hexagon::ArchV69, Hexagon::ArchV68, Hexagon::ArchV67,
697 Hexagon::ArchV66, Hexagon::ArchV65, Hexagon::ArchV62, Hexagon::ArchV60,
698 Hexagon::ArchV55, Hexagon::ArchV5})
699 if (Features.test(I: Arch))
700 return Arch;
701 llvm_unreachable("Expected arch v5-v81");
702 return 0;
703}
704
705unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
706 return StringSwitch<unsigned>(STI.getCPU())
707 .Case(S: "generic", Value: llvm::ELF::EF_HEXAGON_MACH_V5)
708 .Case(S: "hexagonv5", Value: llvm::ELF::EF_HEXAGON_MACH_V5)
709 .Case(S: "hexagonv55", Value: llvm::ELF::EF_HEXAGON_MACH_V55)
710 .Case(S: "hexagonv60", Value: llvm::ELF::EF_HEXAGON_MACH_V60)
711 .Case(S: "hexagonv62", Value: llvm::ELF::EF_HEXAGON_MACH_V62)
712 .Case(S: "hexagonv65", Value: llvm::ELF::EF_HEXAGON_MACH_V65)
713 .Case(S: "hexagonv66", Value: llvm::ELF::EF_HEXAGON_MACH_V66)
714 .Case(S: "hexagonv67", Value: llvm::ELF::EF_HEXAGON_MACH_V67)
715 .Case(S: "hexagonv67t", Value: llvm::ELF::EF_HEXAGON_MACH_V67T)
716 .Case(S: "hexagonv68", Value: llvm::ELF::EF_HEXAGON_MACH_V68)
717 .Case(S: "hexagonv69", Value: llvm::ELF::EF_HEXAGON_MACH_V69)
718 .Case(S: "hexagonv71", Value: llvm::ELF::EF_HEXAGON_MACH_V71)
719 .Case(S: "hexagonv71t", Value: llvm::ELF::EF_HEXAGON_MACH_V71T)
720 .Case(S: "hexagonv73", Value: llvm::ELF::EF_HEXAGON_MACH_V73)
721 .Case(S: "hexagonv75", Value: llvm::ELF::EF_HEXAGON_MACH_V75)
722 .Case(S: "hexagonv79", Value: llvm::ELF::EF_HEXAGON_MACH_V79)
723 .Case(S: "hexagonv81", Value: llvm::ELF::EF_HEXAGON_MACH_V81);
724}
725
726llvm::ArrayRef<MCPhysReg> Hexagon_MC::GetVectRegRev() {
727 return ArrayRef(VectRegRev);
728}
729
730namespace {
731class HexagonMCInstrAnalysis : public MCInstrAnalysis {
732public:
733 HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
734
735 bool isUnconditionalBranch(MCInst const &Inst) const override {
736 //assert(!HexagonMCInstrInfo::isBundle(Inst));
737 return MCInstrAnalysis::isUnconditionalBranch(Inst);
738 }
739
740 bool isConditionalBranch(MCInst const &Inst) const override {
741 //assert(!HexagonMCInstrInfo::isBundle(Inst));
742 return MCInstrAnalysis::isConditionalBranch(Inst);
743 }
744
745 bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
746 uint64_t Size, uint64_t &Target) const override {
747 if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
748 isConditionalBranch(Inst)))
749 return false;
750
751 //assert(!HexagonMCInstrInfo::isBundle(Inst));
752 if (!HexagonMCInstrInfo::isExtendable(MCII: *Info, MCI: Inst))
753 return false;
754 auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(MCII: *Info, MCI: Inst));
755 assert(Extended.isExpr());
756 int64_t Value;
757 if (!Extended.getExpr()->evaluateAsAbsolute(Res&: Value))
758 return false;
759 Target = Value;
760 return true;
761 }
762
763 uint32_t getValueFromMask(uint32_t Instruction, uint32_t Mask) const {
764 uint32_t Result = 0;
765 uint32_t Offset = 0;
766 while (Mask) {
767 if (Instruction & (Mask & -Mask))
768 Result |= (1 << Offset);
769 Mask &= (Mask - 1);
770 ++Offset;
771 }
772 return Result;
773 }
774
775 std::vector<std::pair<uint64_t, uint64_t>>
776 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
777 const MCSubtargetInfo &STI) const override {
778 // Do a lightweight parsing of PLT entries.
779 std::vector<std::pair<uint64_t, uint64_t>> Result;
780 for (uint64_t Byte = 0x0, End = PltContents.size(); Byte < End; Byte += 4) {
781 // Recognize immext(##gotpltn)
782 uint32_t ImmExt = support::endian::read32le(P: PltContents.data() + Byte);
783 if ((ImmExt & 0x00004000) != 0x00004000)
784 continue;
785 uint32_t LoadGotPlt =
786 support::endian::read32le(P: PltContents.data() + Byte + 4);
787 if ((LoadGotPlt & 0x6a49c00c) != 0x6a49c00c)
788 continue;
789 uint32_t Address = (getValueFromMask(Instruction: ImmExt, Mask: 0xfff3fff) << 6) +
790 getValueFromMask(Instruction: LoadGotPlt, Mask: 0x1f80) + PltSectionVA +
791 Byte;
792 Result.emplace_back(args: PltSectionVA + Byte, args&: Address);
793 }
794 return Result;
795 }
796};
797} // namespace
798
799static MCInstrAnalysis *createHexagonMCInstrAnalysis(const MCInstrInfo *Info) {
800 return new HexagonMCInstrAnalysis(Info);
801}
802
803// Force static initialization.
804extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
805LLVMInitializeHexagonTargetMC() {
806 // Register the MC asm info.
807 RegisterMCAsmInfoFn X(getTheHexagonTarget(), createHexagonMCAsmInfo);
808
809 // Register the MC instruction info.
810 TargetRegistry::RegisterMCInstrInfo(T&: getTheHexagonTarget(),
811 Fn: createHexagonMCInstrInfo);
812
813 // Register the MC register info.
814 TargetRegistry::RegisterMCRegInfo(T&: getTheHexagonTarget(),
815 Fn: createHexagonMCRegisterInfo);
816
817 // Register the MC subtarget info.
818 TargetRegistry::RegisterMCSubtargetInfo(
819 T&: getTheHexagonTarget(), Fn: Hexagon_MC::createHexagonMCSubtargetInfo);
820
821 // Register the MC Code Emitter
822 TargetRegistry::RegisterMCCodeEmitter(T&: getTheHexagonTarget(),
823 Fn: createHexagonMCCodeEmitter);
824
825 // Register the asm backend
826 TargetRegistry::RegisterMCAsmBackend(T&: getTheHexagonTarget(),
827 Fn: createHexagonAsmBackend);
828
829 // Register the MC instruction analyzer.
830 TargetRegistry::RegisterMCInstrAnalysis(T&: getTheHexagonTarget(),
831 Fn: createHexagonMCInstrAnalysis);
832
833 // Register the obj streamer
834 TargetRegistry::RegisterELFStreamer(T&: getTheHexagonTarget(), Fn: createMCStreamer);
835
836 // Register the obj target streamer
837 TargetRegistry::RegisterObjectTargetStreamer(
838 T&: getTheHexagonTarget(), Fn: createHexagonObjectTargetStreamer);
839
840 // Register the asm streamer
841 TargetRegistry::RegisterAsmTargetStreamer(T&: getTheHexagonTarget(),
842 Fn: createMCAsmTargetStreamer);
843
844 // Register the null streamer
845 TargetRegistry::RegisterNullTargetStreamer(T&: getTheHexagonTarget(),
846 Fn: createHexagonNullTargetStreamer);
847
848 // Register the MC Inst Printer
849 TargetRegistry::RegisterMCInstPrinter(T&: getTheHexagonTarget(),
850 Fn: createHexagonMCInstPrinter);
851}
852