1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_CALLING_CONV_IMPL
10#undef GET_CALLING_CONV_IMPL
11
12static bool CC_Lanai32(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
14 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
15static bool CC_Lanai32_Fast(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
17 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
18static bool RetCC_Lanai32(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
20 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
21
22
23static bool CC_Lanai32(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
26
27 if (LocVT == MVT::i8 ||
28 LocVT == MVT::i16) {
29 LocVT = MVT::i32;
30 if (ArgFlags.isSExt())
31 LocInfo = CCValAssign::SExt;
32 else if (ArgFlags.isZExt())
33 LocInfo = CCValAssign::ZExt;
34 else
35 LocInfo = CCValAssign::AExt;
36 }
37
38 if (!State.isVarArg()) {
39 if (ArgFlags.isInReg()) {
40 if (LocVT == MVT::i32) {
41 static const MCPhysReg RegList1[] = {
42 Lanai::R6, Lanai::R7, Lanai::R18, Lanai::R19
43 };
44 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
45 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
46 return false;
47 }
48 }
49 }
50 }
51
52 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
53 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
54 return false;
55
56 return true; // CC didn't match.
57}
58
59
60static bool CC_Lanai32_Fast(unsigned ValNo, MVT ValVT,
61 MVT LocVT, CCValAssign::LocInfo LocInfo,
62 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
63
64 if (LocVT == MVT::i8 ||
65 LocVT == MVT::i16) {
66 LocVT = MVT::i32;
67 if (ArgFlags.isSExt())
68 LocInfo = CCValAssign::SExt;
69 else if (ArgFlags.isZExt())
70 LocInfo = CCValAssign::ZExt;
71 else
72 LocInfo = CCValAssign::AExt;
73 }
74
75 if (!State.isVarArg()) {
76 if (LocVT == MVT::i32) {
77 static const MCPhysReg RegList1[] = {
78 Lanai::R6, Lanai::R7, Lanai::R18, Lanai::R19
79 };
80 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
81 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
82 return false;
83 }
84 }
85 }
86
87 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
88 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
89 return false;
90
91 return true; // CC didn't match.
92}
93
94
95static bool RetCC_Lanai32(unsigned ValNo, MVT ValVT,
96 MVT LocVT, CCValAssign::LocInfo LocInfo,
97 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
98
99 if (LocVT == MVT::i32) {
100 static const MCPhysReg RegList1[] = {
101 Lanai::RV, Lanai::R9
102 };
103 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
104 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
105 return false;
106 }
107 }
108
109 return true; // CC didn't match.
110}
111
112#endif // GET_CALLING_CONV_IMPL
113
114#ifdef GET_CC_REGISTER_LISTS
115#undef GET_CC_REGISTER_LISTS
116
117const MCRegister CC_Lanai32_ArgRegs[] = { Lanai::R18, Lanai::R19, Lanai::R6, Lanai::R7 };
118const MCRegister CC_Lanai32_Fast_ArgRegs[] = { Lanai::R18, Lanai::R19, Lanai::R6, Lanai::R7 };
119const MCRegister RetCC_Lanai32_ArgRegs[] = { Lanai::R9, Lanai::RV };
120
121#endif // GET_CC_REGISTER_LISTS
122
123