1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass LanaiMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16
17#ifdef __GNUC__
18#pragma GCC diagnostic push
19#pragma GCC diagnostic ignored "-Woverlength-strings"
20#endif
21static constexpr char LanaiSubRegIndexStrings[] = {
22 /* 0 */ "sub_32\000"
23};
24#ifdef __GNUC__
25#pragma GCC diagnostic pop
26#endif
27
28
29static constexpr uint32_t LanaiSubRegIndexNameOffsets[] = {
30 0,
31};
32
33static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
34 { .Offset: 65535, .Size: 65535 },
35 { .Offset: 0, .Size: 32 }, // sub_32
36};
37
38
39static const LaneBitmask SubRegIndexLaneMaskTable[] = {
40 LaneBitmask::getAll(),
41 LaneBitmask(0x0000000000000001), // sub_32
42 };
43
44
45
46static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
47 // Mode = 0 (DefaultMode)
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GPR
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GPR_with_sub_32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // CCR
51};
52static const uint32_t GPRSubClassMask[] = {
53 0x00000003,
54 0x00000002, // sub_32
55};
56
57static const uint32_t GPR_with_sub_32SubClassMask[] = {
58 0x00000002,
59};
60
61static const uint32_t CCRSubClassMask[] = {
62 0x00000004,
63};
64
65static const uint16_t SuperRegIdxSeqs[] = {
66 /* 0 */ 1, 0,
67};
68
69static unsigned const GPR_with_sub_32Superclasses[] = {
70 Lanai::GPRRegClassID,
71};
72
73namespace Lanai {
74
75// Register class instances
76 extern const TargetRegisterClass GPRRegClass = {
77 .MC: &LanaiMCRegisterClasses[GPRRegClassID],
78 .SubClassMask: GPRSubClassMask,
79 .SuperRegIndices: SuperRegIdxSeqs + 0,
80 .LaneMask: LaneBitmask(0x0000000000000001),
81 .AllocationPriority: 0,
82 .GlobalPriority: false,
83 .TSFlags: 0x00, /* TSFlags */
84 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
85 .CoveredBySubRegs: false, /* CoveredBySubRegs */
86 .SuperClasses: nullptr, .SuperClassesSize: 0,
87 .OrderFunc: nullptr
88 };
89
90 extern const TargetRegisterClass GPR_with_sub_32RegClass = {
91 .MC: &LanaiMCRegisterClasses[GPR_with_sub_32RegClassID],
92 .SubClassMask: GPR_with_sub_32SubClassMask,
93 .SuperRegIndices: SuperRegIdxSeqs + 1,
94 .LaneMask: LaneBitmask(0x0000000000000001),
95 .AllocationPriority: 0,
96 .GlobalPriority: false,
97 .TSFlags: 0x00, /* TSFlags */
98 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
99 .CoveredBySubRegs: false, /* CoveredBySubRegs */
100 .SuperClasses: GPR_with_sub_32Superclasses, .SuperClassesSize: 1,
101 .OrderFunc: nullptr
102 };
103
104 extern const TargetRegisterClass CCRRegClass = {
105 .MC: &LanaiMCRegisterClasses[CCRRegClassID],
106 .SubClassMask: CCRSubClassMask,
107 .SuperRegIndices: SuperRegIdxSeqs + 1,
108 .LaneMask: LaneBitmask(0x0000000000000001),
109 .AllocationPriority: 0,
110 .GlobalPriority: false,
111 .TSFlags: 0x00, /* TSFlags */
112 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
113 .CoveredBySubRegs: false, /* CoveredBySubRegs */
114 .SuperClasses: nullptr, .SuperClassesSize: 0,
115 .OrderFunc: nullptr
116 };
117
118
119} // namespace Lanai
120namespace {
121
122 const TargetRegisterClass *const RegisterClasses[] = {
123 &Lanai::GPRRegClass,
124 &Lanai::GPR_with_sub_32RegClass,
125 &Lanai::CCRRegClass,
126 };
127} // namespace
128
129static const uint8_t CostPerUseTable[] = {
1300, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
131
132
133static const bool InAllocatableClassTable[] = {
134false, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
135
136
137static const TargetRegisterInfoDesc LanaiRegInfoDesc = { // Extra Descriptors
138.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
139
140unsigned LanaiGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
141 static const uint8_t Rows[1][1] = {
142 { 0, },
143 };
144
145 --IdxA; assert(IdxA < 1); (void) IdxA;
146 --IdxB; assert(IdxB < 1);
147 return Rows[0][IdxB];
148}
149
150unsigned LanaiGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
151 static const uint8_t Table[1][1] = {
152 { 0, },
153 };
154
155 --IdxA; assert(IdxA < 1);
156 --IdxB; assert(IdxB < 1);
157 return Table[IdxA][IdxB];
158 }
159
160 struct MaskRolOp {
161 LaneBitmask Mask;
162 uint8_t RotateLeft;
163 };
164 static const MaskRolOp LaneMaskComposeSequences[] = {
165 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
166 };
167 static const uint8_t CompositeSequences[] = {
168 0 // to sub_32
169 };
170
171LaneBitmask LanaiGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
172 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
173 LaneBitmask Result;
174 for (const MaskRolOp *Ops =
175 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
176 Ops->Mask.any(); ++Ops) {
177 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
178 if (unsigned S = Ops->RotateLeft)
179 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
180 else
181 Result |= LaneBitmask(M);
182 }
183 return Result;
184}
185
186LaneBitmask LanaiGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
187 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
188 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
189 LaneBitmask Result;
190 for (const MaskRolOp *Ops =
191 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
192 Ops->Mask.any(); ++Ops) {
193 LaneBitmask::Type M = LaneMask.getAsInteger();
194 if (unsigned S = Ops->RotateLeft)
195 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
196 else
197 Result |= LaneBitmask(M);
198 }
199 return Result;
200}
201
202const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
203 static constexpr uint8_t Table[3][1] = {
204 { // GPR
205 2, // sub_32 -> GPR_with_sub_32
206 },
207 { // GPR_with_sub_32
208 2, // sub_32 -> GPR_with_sub_32
209 },
210 { // CCR
211 0, // sub_32
212 },
213
214 };
215 assert(RC && "Missing regclass");
216 if (!Idx) return RC;
217 --Idx;
218 assert(Idx < 1 && "Bad subreg");
219 unsigned TV = Table[RC->getID()][Idx];
220 return TV ? getRegClass(i: TV - 1) : nullptr;
221}const TargetRegisterClass *LanaiGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
222 static constexpr uint8_t Table[3][1] = {
223 { // GPR
224 1, // GPR:sub_32 -> GPR
225 },
226 { // GPR_with_sub_32
227 1, // GPR_with_sub_32:sub_32 -> GPR
228 },
229 { // CCR
230 0, // CCR:sub_32
231 },
232
233 };
234 assert(RC && "Missing regclass");
235 if (!Idx) return RC;
236 --Idx;
237 assert(Idx < 1 && "Bad subreg");
238 unsigned TV = Table[RC->getID()][Idx];
239 return TV ? getRegClass(i: TV - 1) : nullptr;
240}/// Get the weight in units of pressure for this register class.
241const RegClassWeight &LanaiGenRegisterInfo::
242getRegClassWeight(const TargetRegisterClass *RC) const {
243 static const RegClassWeight RCWeightTable[] = {
244 {.RegWeight: 1, .WeightLimit: 32}, // GPR
245 {.RegWeight: 1, .WeightLimit: 7}, // GPR_with_sub_32
246 {.RegWeight: 0, .WeightLimit: 0}, // CCR
247 };
248 return RCWeightTable[RC->getID()];
249}
250
251/// Get the weight in units of pressure for this register unit.
252unsigned LanaiGenRegisterInfo::
253getRegUnitWeight(MCRegUnit RegUnit) const {
254 assert(static_cast<unsigned>(RegUnit) < 33 && "invalid register unit");
255 // All register units have unit weight.
256 return 1;
257}
258
259
260// Get the number of dimensions of register pressure.
261unsigned LanaiGenRegisterInfo::getNumRegPressureSets() const {
262 return 2;
263}
264
265// Get the name of this register unit pressure set.
266const char *LanaiGenRegisterInfo::
267getRegPressureSetName(unsigned Idx) const {
268 static const char *PressureNameTable[] = {
269 "GPR_with_sub_32",
270 "GPR",
271 };
272 return PressureNameTable[Idx];
273}
274
275// Get the register unit pressure limit for this dimension.
276// This limit must be adjusted dynamically for reserved registers.
277unsigned LanaiGenRegisterInfo::
278getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
279 static const uint8_t PressureLimitTable[] = {
280 7, // 0: GPR_with_sub_32
281 32, // 1: GPR
282 };
283 return PressureLimitTable[Idx];
284}
285
286/// Table of pressure sets per register class or unit.
287static const int RCSetsTable[] = {
288 /* 0 */ 0, 1, -1,
289};
290
291/// Get the dimensions of register pressure impacted by this register class.
292/// Returns a -1 terminated array of pressure set IDs
293const int *LanaiGenRegisterInfo::
294getRegClassPressureSets(const TargetRegisterClass *RC) const {
295 static const uint8_t RCSetStartTable[] = {
296 1,0,2,};
297 return &RCSetsTable[RCSetStartTable[RC->getID()]];
298}
299
300/// Get the dimensions of register pressure impacted by this register unit.
301/// Returns a -1 terminated array of pressure set IDs
302const int *LanaiGenRegisterInfo::
303getRegUnitPressureSets(MCRegUnit RegUnit) const {
304 assert(static_cast<unsigned>(RegUnit) < 33 && "invalid register unit");
305 static const uint8_t RUSetStartTable[] = {
306 0,0,0,0,0,2,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
307 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
308}
309
310extern const MCRegisterDesc LanaiRegDesc[];
311extern const int16_t LanaiRegDiffLists[];
312extern const LaneBitmask LanaiLaneMaskLists[];
313extern const char LanaiRegStrings[];
314extern const char LanaiRegClassStrings[];
315extern const MCPhysReg LanaiRegUnitRoots[][2];
316extern const uint16_t LanaiSubRegIdxLists[];
317extern const uint16_t LanaiRegEncodingTable[];
318// Lanai Dwarf<->LLVM register mappings.
319extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[];
320extern const unsigned LanaiDwarfFlavour0Dwarf2LSize;
321
322extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[];
323extern const unsigned LanaiEHFlavour0Dwarf2LSize;
324
325extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[];
326extern const unsigned LanaiDwarfFlavour0L2DwarfSize;
327
328extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[];
329extern const unsigned LanaiEHFlavour0L2DwarfSize;
330
331
332LanaiGenRegisterInfo::
333LanaiGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
334 unsigned PC, unsigned HwMode)
335 : TargetRegisterInfo(&LanaiRegInfoDesc, RegisterClasses, RegisterClasses+3,
336 LanaiSubRegIndexStrings, LanaiSubRegIndexNameOffsets,
337 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
338
339 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
340 InitMCRegisterInfo(D: LanaiRegDesc, NR: 41, RA, PC,
341 C: LanaiMCRegisterClasses, NC: 3,
342 RURoots: LanaiRegUnitRoots,
343 NRU: 33,
344 DL: LanaiRegDiffLists,
345 RUMS: LanaiLaneMaskLists,
346 Strings: LanaiRegStrings,
347 ClassStrings: LanaiRegClassStrings,
348 SubIndices: LanaiSubRegIdxLists,
349 NumIndices: 2,
350 RET: LanaiRegEncodingTable,
351 RUI: nullptr);
352
353 switch (DwarfFlavour) {
354 default:
355 llvm_unreachable("Unknown DWARF flavour");
356 case 0:
357 mapDwarfRegsToLLVMRegs(Map: LanaiDwarfFlavour0Dwarf2L, Size: LanaiDwarfFlavour0Dwarf2LSize, isEH: false);
358 break;
359 }
360 switch (EHFlavour) {
361 default:
362 llvm_unreachable("Unknown DWARF flavour");
363 case 0:
364 mapDwarfRegsToLLVMRegs(Map: LanaiEHFlavour0Dwarf2L, Size: LanaiEHFlavour0Dwarf2LSize, isEH: true);
365 break;
366 }
367 switch (DwarfFlavour) {
368 default:
369 llvm_unreachable("Unknown DWARF flavour");
370 case 0:
371 mapLLVMRegsToDwarfRegs(Map: LanaiDwarfFlavour0L2Dwarf, Size: LanaiDwarfFlavour0L2DwarfSize, isEH: false);
372 break;
373 }
374 switch (EHFlavour) {
375 default:
376 llvm_unreachable("Unknown DWARF flavour");
377 case 0:
378 mapLLVMRegsToDwarfRegs(Map: LanaiEHFlavour0L2Dwarf, Size: LanaiEHFlavour0L2DwarfSize, isEH: true);
379 break;
380 }
381}
382
383static const MCPhysReg CSR_SaveList[] = { 0 };
384static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, };
385
386
387ArrayRef<const uint32_t *> LanaiGenRegisterInfo::getRegMasks() const {
388 static const uint32_t *const Masks[] = {
389 CSR_RegMask,
390 };
391 return ArrayRef(Masks);
392}
393
394bool LanaiGenRegisterInfo::
395isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
396 return
397 false;
398}
399
400bool LanaiGenRegisterInfo::
401isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
402 return
403 false;
404}
405
406bool LanaiGenRegisterInfo::
407isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
408 return
409 false;
410}
411
412bool LanaiGenRegisterInfo::
413isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
414 return
415 false;
416}
417
418bool LanaiGenRegisterInfo::
419isConstantPhysReg(MCRegister PhysReg) const {
420 return
421 false;
422}
423
424ArrayRef<const char *> LanaiGenRegisterInfo::getRegMaskNames() const {
425 static const char *Names[] = {
426 "CSR",
427 };
428 return ArrayRef(Names);
429}
430
431const LanaiFrameLowering *
432LanaiGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
433 return static_cast<const LanaiFrameLowering *>(
434 MF.getSubtarget().getFrameLowering());
435}
436
437
438} // namespace llvm
439