1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass LanaiMCRegisterClasses[];
12
13static const MVT::SimpleValueType LanaiVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16
17#ifdef __GNUC__
18#pragma GCC diagnostic push
19#pragma GCC diagnostic ignored "-Woverlength-strings"
20#endif
21static constexpr char LanaiSubRegIndexStrings[] = {
22 /* 0 */ "sub_32\000"
23};
24#ifdef __GNUC__
25#pragma GCC diagnostic pop
26#endif
27
28
29static constexpr uint32_t LanaiSubRegIndexNameOffsets[] = {
30 0,
31};
32
33static const TargetRegisterInfo::SubRegCoveredBits LanaiSubRegIdxRangeTable[] = {
34 { .Offset: 65535, .Size: 65535 },
35 { .Offset: 0, .Size: 32 }, // sub_32
36};
37
38
39static const LaneBitmask LanaiSubRegIndexLaneMaskTable[] = {
40 LaneBitmask::getAll(),
41 LaneBitmask(0x0000000000000001), // sub_32
42 };
43
44
45
46static const TargetRegisterInfo::RegClassInfo LanaiRegClassInfos[] = {
47 // Mode = 0 (DefaultMode)
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LanaiVTLists+*/.VTListOffset: 0 }, // GPR
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LanaiVTLists+*/.VTListOffset: 0 }, // GPR_with_sub_32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LanaiVTLists+*/.VTListOffset: 0 }, // CCR
51};
52static const uint32_t GPRSubClassMask[] = {
53 0x00000003,
54 0x00000002, // sub_32
55};
56
57static const uint32_t GPR_with_sub_32SubClassMask[] = {
58 0x00000002,
59};
60
61static const uint32_t CCRSubClassMask[] = {
62 0x00000004,
63};
64
65static const uint16_t SuperRegIdxSeqs[] = {
66 /* 0 */ 1, 0,
67};
68
69static unsigned const GPR_with_sub_32Superclasses[] = {
70 Lanai::GPRRegClassID,
71};
72
73namespace Lanai {
74
75// Register class instances.
76 extern const TargetRegisterClass GPRRegClass = {
77 .MC: &LanaiMCRegisterClasses[GPRRegClassID],
78 .SubClassMask: GPRSubClassMask,
79 .SuperRegIndices: SuperRegIdxSeqs + 0,
80 .LaneMask: LaneBitmask(0x0000000000000001),
81 .AllocationPriority: 0,
82 .GlobalPriority: false,
83 .TSFlags: 0x00, /* TSFlags */
84 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
85 .CoveredBySubRegs: false, /* CoveredBySubRegs */
86 .SuperClasses: nullptr, .SuperClassesSize: 0,
87 .OrderFunc: nullptr
88 };
89
90 extern const TargetRegisterClass GPR_with_sub_32RegClass = {
91 .MC: &LanaiMCRegisterClasses[GPR_with_sub_32RegClassID],
92 .SubClassMask: GPR_with_sub_32SubClassMask,
93 .SuperRegIndices: SuperRegIdxSeqs + 1,
94 .LaneMask: LaneBitmask(0x0000000000000001),
95 .AllocationPriority: 0,
96 .GlobalPriority: false,
97 .TSFlags: 0x00, /* TSFlags */
98 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
99 .CoveredBySubRegs: false, /* CoveredBySubRegs */
100 .SuperClasses: GPR_with_sub_32Superclasses, .SuperClassesSize: 1,
101 .OrderFunc: nullptr
102 };
103
104 extern const TargetRegisterClass CCRRegClass = {
105 .MC: &LanaiMCRegisterClasses[CCRRegClassID],
106 .SubClassMask: CCRSubClassMask,
107 .SuperRegIndices: SuperRegIdxSeqs + 1,
108 .LaneMask: LaneBitmask(0x0000000000000001),
109 .AllocationPriority: 0,
110 .GlobalPriority: false,
111 .TSFlags: 0x00, /* TSFlags */
112 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
113 .CoveredBySubRegs: false, /* CoveredBySubRegs */
114 .SuperClasses: nullptr, .SuperClassesSize: 0,
115 .OrderFunc: nullptr
116 };
117
118
119} // namespace Lanai
120static const TargetRegisterClass *const LanaiRegisterClasses[] = {
121 &Lanai::GPRRegClass,
122 &Lanai::GPR_with_sub_32RegClass,
123 &Lanai::CCRRegClass,
124 };
125
126static const uint8_t LanaiCostPerUseTable[] = {
1270, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
128
129
130static const bool LanaiInAllocatableClassTable[] = {
131false, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
132
133
134static const TargetRegisterInfoDesc LanaiRegInfoDesc = { // Extra Descriptors
135.CostPerUse: LanaiCostPerUseTable, .NumCosts: 1, .InAllocatableClass: LanaiInAllocatableClassTable};
136
137unsigned LanaiGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
138 static const uint8_t Rows[1][1] = {
139 { 0, },
140 };
141
142 --IdxA; assert(IdxA < 1); (void) IdxA;
143 --IdxB; assert(IdxB < 1);
144 return Rows[0][IdxB];
145}
146
147unsigned LanaiGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
148 static const uint8_t Table[1][1] = {
149 { 0, },
150 };
151
152 --IdxA; assert(IdxA < 1);
153 --IdxB; assert(IdxB < 1);
154 return Table[IdxA][IdxB];
155 }
156
157 struct MaskRolOp {
158 LaneBitmask Mask;
159 uint8_t RotateLeft;
160 };
161 static const MaskRolOp LaneMaskComposeSequences[] = {
162 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
163 };
164 static const uint8_t CompositeSequences[] = {
165 0 // to sub_32
166 };
167
168LaneBitmask LanaiGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
169 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
170 LaneBitmask Result;
171 for (const MaskRolOp *Ops =
172 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
173 Ops->Mask.any(); ++Ops) {
174 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
175 if (unsigned S = Ops->RotateLeft)
176 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
177 else
178 Result |= LaneBitmask(M);
179 }
180 return Result;
181}
182
183LaneBitmask LanaiGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
184 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
185 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
186 LaneBitmask Result;
187 for (const MaskRolOp *Ops =
188 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
189 Ops->Mask.any(); ++Ops) {
190 LaneBitmask::Type M = LaneMask.getAsInteger();
191 if (unsigned S = Ops->RotateLeft)
192 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
193 else
194 Result |= LaneBitmask(M);
195 }
196 return Result;
197}
198
199const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
200 static constexpr uint8_t Table[3][1] = {
201 { // GPR
202 2, // sub_32 -> GPR_with_sub_32
203 },
204 { // GPR_with_sub_32
205 2, // sub_32 -> GPR_with_sub_32
206 },
207 { // CCR
208 0, // sub_32
209 },
210
211 };
212 assert(RC && "Missing regclass");
213 if (!Idx) return RC;
214 --Idx;
215 assert(Idx < 1 && "Bad subreg");
216 unsigned TV = Table[RC->getID()][Idx];
217 return TV ? getRegClass(i: TV - 1) : nullptr;
218}const TargetRegisterClass *LanaiGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
219 static constexpr uint8_t Table[3][1] = {
220 { // GPR
221 1, // GPR:sub_32 -> GPR
222 },
223 { // GPR_with_sub_32
224 1, // GPR_with_sub_32:sub_32 -> GPR
225 },
226 { // CCR
227 0, // CCR:sub_32
228 },
229
230 };
231 assert(RC && "Missing regclass");
232 if (!Idx) return RC;
233 --Idx;
234 assert(Idx < 1 && "Bad subreg");
235 unsigned TV = Table[RC->getID()][Idx];
236 return TV ? getRegClass(i: TV - 1) : nullptr;
237}/// Get the weight in units of pressure for this register class.
238const RegClassWeight &LanaiGenRegisterInfo::
239getRegClassWeight(const TargetRegisterClass *RC) const {
240 static const RegClassWeight RCWeightTable[] = {
241 {.RegWeight: 1, .WeightLimit: 32}, // GPR
242 {.RegWeight: 1, .WeightLimit: 7}, // GPR_with_sub_32
243 {.RegWeight: 0, .WeightLimit: 0}, // CCR
244 };
245 return RCWeightTable[RC->getID()];
246}
247
248/// Get the weight in units of pressure for this register unit.
249unsigned LanaiGenRegisterInfo::
250getRegUnitWeight(MCRegUnit RegUnit) const {
251 assert(static_cast<unsigned>(RegUnit) < 33 && "invalid register unit");
252 // All register units have unit weight.
253 return 1;
254}
255
256
257// Get the number of dimensions of register pressure.
258unsigned LanaiGenRegisterInfo::getNumRegPressureSets() const {
259 return 2;
260}
261
262// Get the name of this register unit pressure set.
263const char *LanaiGenRegisterInfo::
264getRegPressureSetName(unsigned Idx) const {
265 static const char *PressureNameTable[] = {
266 "GPR_with_sub_32",
267 "GPR",
268 };
269 return PressureNameTable[Idx];
270}
271
272// Get the register unit pressure limit for this dimension.
273// This limit must be adjusted dynamically for reserved registers.
274unsigned LanaiGenRegisterInfo::
275getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
276 static const uint8_t PressureLimitTable[] = {
277 7, // 0: GPR_with_sub_32
278 32, // 1: GPR
279 };
280 return PressureLimitTable[Idx];
281}
282
283/// Table of pressure sets per register class or unit.
284static const int RCSetsTable[] = {
285 /* 0 */ 0, 1, -1,
286};
287
288/// Get the dimensions of register pressure impacted by this register class.
289/// Returns a -1 terminated array of pressure set IDs
290const int *LanaiGenRegisterInfo::
291getRegClassPressureSets(const TargetRegisterClass *RC) const {
292 static const uint8_t RCSetStartTable[] = {
293 1,0,2,};
294 return &RCSetsTable[RCSetStartTable[RC->getID()]];
295}
296
297/// Get the dimensions of register pressure impacted by this register unit.
298/// Returns a -1 terminated array of pressure set IDs
299const int *LanaiGenRegisterInfo::
300getRegUnitPressureSets(MCRegUnit RegUnit) const {
301 assert(static_cast<unsigned>(RegUnit) < 33 && "invalid register unit");
302 static const uint8_t RUSetStartTable[] = {
303 0,0,0,0,0,2,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
304 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
305}
306
307extern const MCRegisterDesc LanaiRegDesc[];
308extern const int16_t LanaiRegDiffLists[];
309extern const LaneBitmask LanaiLaneMaskLists[];
310extern const char LanaiRegStrings[];
311extern const char LanaiRegClassStrings[];
312extern const MCPhysReg LanaiRegUnitRoots[][2];
313extern const uint16_t LanaiSubRegIdxLists[];
314extern const uint16_t LanaiRegEncodingTable[];
315// Lanai Dwarf<->LLVM register mappings.
316extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[];
317extern const unsigned LanaiDwarfFlavour0Dwarf2LSize;
318
319extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[];
320extern const unsigned LanaiEHFlavour0Dwarf2LSize;
321
322extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[];
323extern const unsigned LanaiDwarfFlavour0L2DwarfSize;
324
325extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[];
326extern const unsigned LanaiEHFlavour0L2DwarfSize;
327
328
329LanaiGenRegisterInfo::
330LanaiGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
331 unsigned PC, unsigned HwMode)
332 : TargetRegisterInfo(&LanaiRegInfoDesc, LanaiRegisterClasses,
333 LanaiSubRegIndexStrings, LanaiSubRegIndexNameOffsets,
334 LanaiSubRegIdxRangeTable, LanaiSubRegIndexLaneMaskTable,
335
336 LaneBitmask(0xFFFFFFFFFFFFFFFE), LanaiRegClassInfos, LanaiVTLists, HwMode) {
337 InitMCRegisterInfo(D: LanaiRegDesc, NR: 41, RA, PC,
338 C: LanaiMCRegisterClasses, NC: 3, RURoots: LanaiRegUnitRoots, NRU: 33, DL: LanaiRegDiffLists,
339 RUMS: LanaiLaneMaskLists, Strings: LanaiRegStrings, ClassStrings: LanaiRegClassStrings, SubIndices: LanaiSubRegIdxLists, NumIndices: 2,
340 RET: LanaiRegEncodingTable, RUI: nullptr);
341
342 switch (DwarfFlavour) {
343 default:
344 llvm_unreachable("Unknown DWARF flavour");
345 case 0:
346 mapDwarfRegsToLLVMRegs(Map: LanaiDwarfFlavour0Dwarf2L, Size: LanaiDwarfFlavour0Dwarf2LSize, isEH: false);
347 break;
348 }
349 switch (EHFlavour) {
350 default:
351 llvm_unreachable("Unknown DWARF flavour");
352 case 0:
353 mapDwarfRegsToLLVMRegs(Map: LanaiEHFlavour0Dwarf2L, Size: LanaiEHFlavour0Dwarf2LSize, isEH: true);
354 break;
355 }
356 switch (DwarfFlavour) {
357 default:
358 llvm_unreachable("Unknown DWARF flavour");
359 case 0:
360 mapLLVMRegsToDwarfRegs(Map: LanaiDwarfFlavour0L2Dwarf, Size: LanaiDwarfFlavour0L2DwarfSize, isEH: false);
361 break;
362 }
363 switch (EHFlavour) {
364 default:
365 llvm_unreachable("Unknown DWARF flavour");
366 case 0:
367 mapLLVMRegsToDwarfRegs(Map: LanaiEHFlavour0L2Dwarf, Size: LanaiEHFlavour0L2DwarfSize, isEH: true);
368 break;
369 }
370}
371
372static const MCPhysReg CSR_SaveList[] = { 0 };
373static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, };
374
375
376ArrayRef<const uint32_t *> LanaiGenRegisterInfo::getRegMasks() const {
377 static const uint32_t *const Masks[] = {
378 CSR_RegMask,
379 };
380 return ArrayRef(Masks);
381}
382
383bool LanaiGenRegisterInfo::
384isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
385 return
386 false;
387}
388
389bool LanaiGenRegisterInfo::
390isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
391 return
392 false;
393}
394
395bool LanaiGenRegisterInfo::
396isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
397 return
398 false;
399}
400
401bool LanaiGenRegisterInfo::
402isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
403 return
404 false;
405}
406
407bool LanaiGenRegisterInfo::
408isConstantPhysReg(MCRegister PhysReg) const {
409 return
410 false;
411}
412
413ArrayRef<const char *> LanaiGenRegisterInfo::getRegMaskNames() const {
414 static const char *Names[] = {
415 "CSR",
416 };
417 return ArrayRef(Names);
418}
419
420const LanaiFrameLowering *
421LanaiGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
422 return static_cast<const LanaiFrameLowering *>(
423 MF.getSubtarget().getFrameLowering());
424}
425
426
427} // namespace llvm
428