1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass LanaiMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16
17static const char *SubRegIndexNameTable[] = { "sub_32", "" };
18
19static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
20 { .Offset: 65535, .Size: 65535 },
21 { .Offset: 0, .Size: 32 }, // sub_32
22};
23
24
25static const LaneBitmask SubRegIndexLaneMaskTable[] = {
26 LaneBitmask::getAll(),
27 LaneBitmask(0x0000000000000001), // sub_32
28 };
29
30
31
32static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
33 // Mode = 0 (Default)
34 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GPR
35 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GPR_with_sub_32
36 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // CCR
37};
38static const uint32_t GPRSubClassMask[] = {
39 0x00000003,
40 0x00000002, // sub_32
41};
42
43static const uint32_t GPR_with_sub_32SubClassMask[] = {
44 0x00000002,
45};
46
47static const uint32_t CCRSubClassMask[] = {
48 0x00000004,
49};
50
51static const uint16_t SuperRegIdxSeqs[] = {
52 /* 0 */ 1, 0,
53};
54
55static unsigned const GPR_with_sub_32Superclasses[] = {
56 Lanai::GPRRegClassID,
57};
58
59
60namespace Lanai { // Register class instances
61 extern const TargetRegisterClass GPRRegClass = {
62 .MC: &LanaiMCRegisterClasses[GPRRegClassID],
63 .SubClassMask: GPRSubClassMask,
64 .SuperRegIndices: SuperRegIdxSeqs + 0,
65 .LaneMask: LaneBitmask(0x0000000000000001),
66 .AllocationPriority: 0,
67 .GlobalPriority: false,
68 .TSFlags: 0x00, /* TSFlags */
69 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
70 .CoveredBySubRegs: false, /* CoveredBySubRegs */
71 .SuperClasses: nullptr, .SuperClassesSize: 0,
72 .OrderFunc: nullptr
73 };
74
75 extern const TargetRegisterClass GPR_with_sub_32RegClass = {
76 .MC: &LanaiMCRegisterClasses[GPR_with_sub_32RegClassID],
77 .SubClassMask: GPR_with_sub_32SubClassMask,
78 .SuperRegIndices: SuperRegIdxSeqs + 1,
79 .LaneMask: LaneBitmask(0x0000000000000001),
80 .AllocationPriority: 0,
81 .GlobalPriority: false,
82 .TSFlags: 0x00, /* TSFlags */
83 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
84 .CoveredBySubRegs: false, /* CoveredBySubRegs */
85 .SuperClasses: GPR_with_sub_32Superclasses, .SuperClassesSize: 1,
86 .OrderFunc: nullptr
87 };
88
89 extern const TargetRegisterClass CCRRegClass = {
90 .MC: &LanaiMCRegisterClasses[CCRRegClassID],
91 .SubClassMask: CCRSubClassMask,
92 .SuperRegIndices: SuperRegIdxSeqs + 1,
93 .LaneMask: LaneBitmask(0x0000000000000001),
94 .AllocationPriority: 0,
95 .GlobalPriority: false,
96 .TSFlags: 0x00, /* TSFlags */
97 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
98 .CoveredBySubRegs: false, /* CoveredBySubRegs */
99 .SuperClasses: nullptr, .SuperClassesSize: 0,
100 .OrderFunc: nullptr
101 };
102
103} // end namespace Lanai
104
105namespace {
106 const TargetRegisterClass *const RegisterClasses[] = {
107 &Lanai::GPRRegClass,
108 &Lanai::GPR_with_sub_32RegClass,
109 &Lanai::CCRRegClass,
110 };
111} // end anonymous namespace
112
113static const uint8_t CostPerUseTable[] = {
1140, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
115
116
117static const bool InAllocatableClassTable[] = {
118false, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
119
120
121static const TargetRegisterInfoDesc LanaiRegInfoDesc = { // Extra Descriptors
122.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
123
124unsigned LanaiGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
125 static const uint8_t Rows[1][1] = {
126 { 0, },
127 };
128
129 --IdxA; assert(IdxA < 1); (void) IdxA;
130 --IdxB; assert(IdxB < 1);
131 return Rows[0][IdxB];
132}
133
134unsigned LanaiGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
135 static const uint8_t Table[1][1] = {
136 { 0, },
137 };
138
139 --IdxA; assert(IdxA < 1);
140 --IdxB; assert(IdxB < 1);
141 return Table[IdxA][IdxB];
142 }
143
144 struct MaskRolOp {
145 LaneBitmask Mask;
146 uint8_t RotateLeft;
147 };
148 static const MaskRolOp LaneMaskComposeSequences[] = {
149 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
150 };
151 static const uint8_t CompositeSequences[] = {
152 0 // to sub_32
153 };
154
155LaneBitmask LanaiGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
156 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
157 LaneBitmask Result;
158 for (const MaskRolOp *Ops =
159 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
160 Ops->Mask.any(); ++Ops) {
161 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
162 if (unsigned S = Ops->RotateLeft)
163 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
164 else
165 Result |= LaneBitmask(M);
166 }
167 return Result;
168}
169
170LaneBitmask LanaiGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
171 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
172 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
173 LaneBitmask Result;
174 for (const MaskRolOp *Ops =
175 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
176 Ops->Mask.any(); ++Ops) {
177 LaneBitmask::Type M = LaneMask.getAsInteger();
178 if (unsigned S = Ops->RotateLeft)
179 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
180 else
181 Result |= LaneBitmask(M);
182 }
183 return Result;
184}
185
186const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
187 static const uint8_t Table[3][1] = {
188 { // GPR
189 2, // sub_32 -> GPR_with_sub_32
190 },
191 { // GPR_with_sub_32
192 2, // sub_32 -> GPR_with_sub_32
193 },
194 { // CCR
195 0, // sub_32
196 },
197 };
198 assert(RC && "Missing regclass");
199 if (!Idx) return RC;
200 --Idx;
201 assert(Idx < 1 && "Bad subreg");
202 unsigned TV = Table[RC->getID()][Idx];
203 return TV ? getRegClass(i: TV - 1) : nullptr;
204}
205
206const TargetRegisterClass *LanaiGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
207 static const uint8_t Table[3][1] = {
208 { // GPR
209 1, // GPR:sub_32 -> GPR
210 },
211 { // GPR_with_sub_32
212 1, // GPR_with_sub_32:sub_32 -> GPR
213 },
214 { // CCR
215 0, // CCR:sub_32
216 },
217 };
218 assert(RC && "Missing regclass");
219 if (!Idx) return RC;
220 --Idx;
221 assert(Idx < 1 && "Bad subreg");
222 unsigned TV = Table[RC->getID()][Idx];
223 return TV ? getRegClass(i: TV - 1) : nullptr;
224}
225
226/// Get the weight in units of pressure for this register class.
227const RegClassWeight &LanaiGenRegisterInfo::
228getRegClassWeight(const TargetRegisterClass *RC) const {
229 static const RegClassWeight RCWeightTable[] = {
230 {.RegWeight: 1, .WeightLimit: 32}, // GPR
231 {.RegWeight: 1, .WeightLimit: 7}, // GPR_with_sub_32
232 {.RegWeight: 0, .WeightLimit: 0}, // CCR
233 };
234 return RCWeightTable[RC->getID()];
235}
236
237/// Get the weight in units of pressure for this register unit.
238unsigned LanaiGenRegisterInfo::
239getRegUnitWeight(MCRegUnit RegUnit) const {
240 assert(static_cast<unsigned>(RegUnit) < 33 && "invalid register unit");
241 // All register units have unit weight.
242 return 1;
243}
244
245
246// Get the number of dimensions of register pressure.
247unsigned LanaiGenRegisterInfo::getNumRegPressureSets() const {
248 return 2;
249}
250
251// Get the name of this register unit pressure set.
252const char *LanaiGenRegisterInfo::
253getRegPressureSetName(unsigned Idx) const {
254 static const char *PressureNameTable[] = {
255 "GPR_with_sub_32",
256 "GPR",
257 };
258 return PressureNameTable[Idx];
259}
260
261// Get the register unit pressure limit for this dimension.
262// This limit must be adjusted dynamically for reserved registers.
263unsigned LanaiGenRegisterInfo::
264getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
265 static const uint8_t PressureLimitTable[] = {
266 7, // 0: GPR_with_sub_32
267 32, // 1: GPR
268 };
269 return PressureLimitTable[Idx];
270}
271
272/// Table of pressure sets per register class or unit.
273static const int RCSetsTable[] = {
274 /* 0 */ 0, 1, -1,
275};
276
277/// Get the dimensions of register pressure impacted by this register class.
278/// Returns a -1 terminated array of pressure set IDs
279const int *LanaiGenRegisterInfo::
280getRegClassPressureSets(const TargetRegisterClass *RC) const {
281 static const uint8_t RCSetStartTable[] = {
282 1,0,2,};
283 return &RCSetsTable[RCSetStartTable[RC->getID()]];
284}
285
286/// Get the dimensions of register pressure impacted by this register unit.
287/// Returns a -1 terminated array of pressure set IDs
288const int *LanaiGenRegisterInfo::
289getRegUnitPressureSets(MCRegUnit RegUnit) const {
290 assert(static_cast<unsigned>(RegUnit) < 33 && "invalid register unit");
291 static const uint8_t RUSetStartTable[] = {
292 0,0,0,0,0,2,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
293 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
294}
295
296extern const MCRegisterDesc LanaiRegDesc[];
297extern const int16_t LanaiRegDiffLists[];
298extern const LaneBitmask LanaiLaneMaskLists[];
299extern const char LanaiRegStrings[];
300extern const char LanaiRegClassStrings[];
301extern const MCPhysReg LanaiRegUnitRoots[][2];
302extern const uint16_t LanaiSubRegIdxLists[];
303extern const uint16_t LanaiRegEncodingTable[];
304// Lanai Dwarf<->LLVM register mappings.
305extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[];
306extern const unsigned LanaiDwarfFlavour0Dwarf2LSize;
307
308extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[];
309extern const unsigned LanaiEHFlavour0Dwarf2LSize;
310
311extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[];
312extern const unsigned LanaiDwarfFlavour0L2DwarfSize;
313
314extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[];
315extern const unsigned LanaiEHFlavour0L2DwarfSize;
316
317LanaiGenRegisterInfo::
318LanaiGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
319 unsigned PC, unsigned HwMode)
320 : TargetRegisterInfo(&LanaiRegInfoDesc, RegisterClasses, RegisterClasses+3,
321 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
322 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
323 InitMCRegisterInfo(D: LanaiRegDesc, NR: 41, RA, PC,
324 C: LanaiMCRegisterClasses, NC: 3,
325 RURoots: LanaiRegUnitRoots,
326 NRU: 33,
327 DL: LanaiRegDiffLists,
328 RUMS: LanaiLaneMaskLists,
329 Strings: LanaiRegStrings,
330 ClassStrings: LanaiRegClassStrings,
331 SubIndices: LanaiSubRegIdxLists,
332 NumIndices: 2,
333 RET: LanaiRegEncodingTable);
334
335 switch (DwarfFlavour) {
336 default:
337 llvm_unreachable("Unknown DWARF flavour");
338 case 0:
339 mapDwarfRegsToLLVMRegs(Map: LanaiDwarfFlavour0Dwarf2L, Size: LanaiDwarfFlavour0Dwarf2LSize, isEH: false);
340 break;
341 }
342 switch (EHFlavour) {
343 default:
344 llvm_unreachable("Unknown DWARF flavour");
345 case 0:
346 mapDwarfRegsToLLVMRegs(Map: LanaiEHFlavour0Dwarf2L, Size: LanaiEHFlavour0Dwarf2LSize, isEH: true);
347 break;
348 }
349 switch (DwarfFlavour) {
350 default:
351 llvm_unreachable("Unknown DWARF flavour");
352 case 0:
353 mapLLVMRegsToDwarfRegs(Map: LanaiDwarfFlavour0L2Dwarf, Size: LanaiDwarfFlavour0L2DwarfSize, isEH: false);
354 break;
355 }
356 switch (EHFlavour) {
357 default:
358 llvm_unreachable("Unknown DWARF flavour");
359 case 0:
360 mapLLVMRegsToDwarfRegs(Map: LanaiEHFlavour0L2Dwarf, Size: LanaiEHFlavour0L2DwarfSize, isEH: true);
361 break;
362 }
363}
364
365static const MCPhysReg CSR_SaveList[] = { 0 };
366static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, };
367
368
369ArrayRef<const uint32_t *> LanaiGenRegisterInfo::getRegMasks() const {
370 static const uint32_t *const Masks[] = {
371 CSR_RegMask,
372 };
373 return ArrayRef(Masks);
374}
375
376bool LanaiGenRegisterInfo::
377isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
378 return
379 false;
380}
381
382bool LanaiGenRegisterInfo::
383isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
384 return
385 false;
386}
387
388bool LanaiGenRegisterInfo::
389isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
390 return
391 false;
392}
393
394bool LanaiGenRegisterInfo::
395isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
396 return
397 false;
398}
399
400bool LanaiGenRegisterInfo::
401isConstantPhysReg(MCRegister PhysReg) const {
402 return
403 false;
404}
405
406ArrayRef<const char *> LanaiGenRegisterInfo::getRegMaskNames() const {
407 static const char *Names[] = {
408 "CSR",
409 };
410 return ArrayRef(Names);
411}
412
413const LanaiFrameLowering *
414LanaiGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
415 return static_cast<const LanaiFrameLowering *>(
416 MF.getSubtarget().getFrameLowering());
417}
418
419} // end namespace llvm
420
421