1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<3, 47, 11, 4, 2, 1> LanaiMCRegisterClassStorage;
12
13static const MVT::SimpleValueType LanaiVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16
17#ifdef __GNUC__
18#pragma GCC diagnostic push
19#pragma GCC diagnostic ignored "-Woverlength-strings"
20#endif
21static constexpr char LanaiSubRegIndexStrings[] = {
22 /* 0 */ "sub_32\000"
23};
24#ifdef __GNUC__
25#pragma GCC diagnostic pop
26#endif
27
28
29static constexpr uint32_t LanaiSubRegIndexNameOffsets[] = {
30 0,
31};
32
33static const TargetRegisterInfo::SubRegCoveredBits LanaiSubRegIdxRangeTable[] = {
34 { .Offset: 4294967295, .Size: 4294967295 },
35 { .Offset: 0, .Size: 32 }, // sub_32
36};
37
38
39static const LaneBitmask LanaiSubRegIndexLaneMaskTable[] = {
40 LaneBitmask::getAll(),
41 LaneBitmask(0x0000000000000001), // sub_32
42 };
43
44
45
46static const TargetRegisterInfo::RegClassInfo LanaiRegClassInfos[] = {
47 // Mode = 0 (DefaultMode)
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LanaiVTLists+*/.VTListOffset: 0 }, // GPR
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LanaiVTLists+*/.VTListOffset: 0 }, // GPR_with_sub_32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LanaiVTLists+*/.VTListOffset: 0 }, // CCR
51};
52
53static const uint8_t LanaiCostPerUseTable[] = {
540, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
55
56
57static const bool LanaiInAllocatableClassTable[] = {
58false, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
59
60
61static const TargetRegisterInfoDesc LanaiRegInfoDesc = { // Extra Descriptors
62.CostPerUse: LanaiCostPerUseTable, .NumCosts: 1, .InAllocatableClass: LanaiInAllocatableClassTable};
63
64unsigned LanaiGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
65 static const uint8_t Rows[1][1] = {
66 { 0, },
67 };
68
69 --IdxA; assert(IdxA < 1); (void) IdxA;
70 --IdxB; assert(IdxB < 1);
71 return Rows[0][IdxB];
72}
73
74unsigned LanaiGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
75 static const uint8_t Table[1][1] = {
76 { 0, },
77 };
78
79 --IdxA; assert(IdxA < 1);
80 --IdxB; assert(IdxB < 1);
81 return Table[IdxA][IdxB];
82 }
83
84 struct MaskRolOp {
85 LaneBitmask Mask;
86 uint8_t RotateLeft;
87 };
88 static const MaskRolOp LaneMaskComposeSequences[] = {
89 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
90 };
91 static const uint8_t CompositeSequences[] = {
92 0 // to sub_32
93 };
94
95LaneBitmask LanaiGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
96 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
97 LaneBitmask Result;
98 for (const MaskRolOp *Ops =
99 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
100 Ops->Mask.any(); ++Ops) {
101 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
102 if (unsigned S = Ops->RotateLeft)
103 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
104 else
105 Result |= LaneBitmask(M);
106 }
107 return Result;
108}
109
110LaneBitmask LanaiGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
111 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
112 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
113 LaneBitmask Result;
114 for (const MaskRolOp *Ops =
115 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
116 Ops->Mask.any(); ++Ops) {
117 LaneBitmask::Type M = LaneMask.getAsInteger();
118 if (unsigned S = Ops->RotateLeft)
119 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
120 else
121 Result |= LaneBitmask(M);
122 }
123 return Result;
124}
125
126const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
127 static constexpr uint8_t Table[3][1] = {
128 { // GPR
129 2, // sub_32 -> GPR_with_sub_32
130 },
131 { // GPR_with_sub_32
132 2, // sub_32 -> GPR_with_sub_32
133 },
134 { // CCR
135 0, // sub_32
136 },
137
138 };
139 assert(RC && "Missing regclass");
140 if (!Idx) return RC;
141 --Idx;
142 assert(Idx < 1 && "Bad subreg");
143 unsigned TV = Table[RC->getID()][Idx];
144 return TV ? getRegClass(i: TV - 1) : nullptr;
145}const TargetRegisterClass *LanaiGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
146 static constexpr uint8_t Table[3][1] = {
147 { // GPR
148 1, // GPR:sub_32 -> GPR
149 },
150 { // GPR_with_sub_32
151 1, // GPR_with_sub_32:sub_32 -> GPR
152 },
153 { // CCR
154 0, // CCR:sub_32
155 },
156
157 };
158 assert(RC && "Missing regclass");
159 if (!Idx) return RC;
160 --Idx;
161 assert(Idx < 1 && "Bad subreg");
162 unsigned TV = Table[RC->getID()][Idx];
163 return TV ? getRegClass(i: TV - 1) : nullptr;
164}/// Get the weight in units of pressure for this register class.
165const RegClassWeight &LanaiGenRegisterInfo::
166getRegClassWeight(const TargetRegisterClass *RC) const {
167 static const RegClassWeight RCWeightTable[] = {
168 {.RegWeight: 1, .WeightLimit: 32}, // GPR
169 {.RegWeight: 1, .WeightLimit: 7}, // GPR_with_sub_32
170 {.RegWeight: 0, .WeightLimit: 0}, // CCR
171 };
172 return RCWeightTable[RC->getID()];
173}
174
175/// Get the weight in units of pressure for this register unit.
176unsigned LanaiGenRegisterInfo::
177getRegUnitWeight(MCRegUnit RegUnit) const {
178 assert(static_cast<unsigned>(RegUnit) < 33 && "invalid register unit");
179 // All register units have unit weight.
180 return 1;
181}
182
183
184// Get the number of dimensions of register pressure.
185unsigned LanaiGenRegisterInfo::getNumRegPressureSets() const {
186 return 2;
187}
188
189// Get the name of this register unit pressure set.
190const char *LanaiGenRegisterInfo::
191getRegPressureSetName(unsigned Idx) const {
192 static const char *PressureNameTable[] = {
193 "GPR_with_sub_32",
194 "GPR",
195 };
196 return PressureNameTable[Idx];
197}
198
199// Get the register unit pressure limit for this dimension.
200// This limit must be adjusted dynamically for reserved registers.
201unsigned LanaiGenRegisterInfo::
202getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
203 static const uint8_t PressureLimitTable[] = {
204 7, // 0: GPR_with_sub_32
205 32, // 1: GPR
206 };
207 return PressureLimitTable[Idx];
208}
209
210/// Get the register class for this pressure set with the largest
211/// `RegClassWeight::WeightLimit`.
212const TargetRegisterClass *LanaiGenRegisterInfo::
213getLargestRegClassForRegPressureSet(unsigned Idx) const {
214 static const uint8_t PSetRegClassTable[] = {
215 Lanai::GPR_with_sub_32RegClassID, // 0: GPR_with_sub_32
216 Lanai::GPRRegClassID, // 1: GPR
217 };
218 return getRegClass(i: PSetRegClassTable[Idx]);
219}
220
221/// Table of pressure sets per register class or unit.
222static const int RCSetsTable[] = {
223 /* 0 */ 0, 1, -1,
224};
225
226/// Get the dimensions of register pressure impacted by this register class.
227/// Returns a -1 terminated array of pressure set IDs
228const int *LanaiGenRegisterInfo::
229getRegClassPressureSets(const TargetRegisterClass *RC) const {
230 static const uint8_t RCSetStartTable[] = {
231 1,0,2,};
232 return &RCSetsTable[RCSetStartTable[RC->getID()]];
233}
234
235/// Get the dimensions of register pressure impacted by this register unit.
236/// Returns a -1 terminated array of pressure set IDs
237const int *LanaiGenRegisterInfo::
238getRegUnitPressureSets(MCRegUnit RegUnit) const {
239 assert(static_cast<unsigned>(RegUnit) < 33 && "invalid register unit");
240 static const uint8_t RUSetStartTable[] = {
241 0,0,0,0,0,2,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
242 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
243}
244
245
246// Register to minimal register class mapping
247
248const TargetRegisterClass *LanaiGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
249 static const uint16_t InvalidRegClassID = UINT16_MAX;
250
251 static const uint16_t Mapping[41] = {
252 InvalidRegClassID, // NoRegister
253 Lanai::GPR_with_sub_32RegClassID, // FP
254 Lanai::GPR_with_sub_32RegClassID, // PC
255 Lanai::GPR_with_sub_32RegClassID, // RCA
256 Lanai::GPR_with_sub_32RegClassID, // RV
257 Lanai::GPR_with_sub_32RegClassID, // SP
258 Lanai::CCRRegClassID, // SR
259 Lanai::GPRRegClassID, // R0
260 Lanai::GPRRegClassID, // R1
261 Lanai::GPRRegClassID, // R2
262 Lanai::GPRRegClassID, // R3
263 Lanai::GPRRegClassID, // R4
264 Lanai::GPRRegClassID, // R5
265 Lanai::GPRRegClassID, // R6
266 Lanai::GPRRegClassID, // R7
267 Lanai::GPRRegClassID, // R8
268 Lanai::GPRRegClassID, // R9
269 Lanai::GPRRegClassID, // R10
270 Lanai::GPRRegClassID, // R11
271 Lanai::GPRRegClassID, // R12
272 Lanai::GPRRegClassID, // R13
273 Lanai::GPRRegClassID, // R14
274 Lanai::GPRRegClassID, // R15
275 Lanai::GPRRegClassID, // R16
276 Lanai::GPRRegClassID, // R17
277 Lanai::GPRRegClassID, // R18
278 Lanai::GPRRegClassID, // R19
279 Lanai::GPRRegClassID, // R20
280 Lanai::GPRRegClassID, // R21
281 Lanai::GPRRegClassID, // R22
282 Lanai::GPRRegClassID, // R23
283 Lanai::GPRRegClassID, // R24
284 Lanai::GPRRegClassID, // R25
285 Lanai::GPRRegClassID, // R26
286 Lanai::GPRRegClassID, // R27
287 Lanai::GPRRegClassID, // R28
288 Lanai::GPRRegClassID, // R29
289 Lanai::GPRRegClassID, // R30
290 Lanai::GPRRegClassID, // R31
291 Lanai::GPR_with_sub_32RegClassID, // RR1
292 Lanai::GPR_with_sub_32RegClassID, // RR2
293 };
294
295 assert(Reg < ArrayRef(Mapping).size());
296 unsigned RCID = Mapping[Reg.id()];
297 if (RCID == InvalidRegClassID)
298 return nullptr;
299 return &LanaiMCRegisterClassStorage.Classes[RCID];
300}
301extern const MCRegisterDesc LanaiRegDesc[];
302extern const int16_t LanaiRegDiffLists[];
303extern const LaneBitmask LanaiLaneMaskLists[];
304extern const char LanaiRegStrings[];
305extern const char LanaiRegClassStrings[];
306extern const MCPhysReg LanaiRegUnitRoots[][2];
307extern const uint16_t LanaiSubRegIdxLists[];
308extern const uint16_t LanaiRegEncodingTable[];
309// Lanai Dwarf<->LLVM register mappings.
310extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[];
311extern const unsigned LanaiDwarfFlavour0Dwarf2LSize;
312
313extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[];
314extern const unsigned LanaiEHFlavour0Dwarf2LSize;
315
316extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[];
317extern const unsigned LanaiDwarfFlavour0L2DwarfSize;
318
319extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[];
320extern const unsigned LanaiEHFlavour0L2DwarfSize;
321
322
323LanaiGenRegisterInfo::
324LanaiGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
325 unsigned PC, unsigned HwMode)
326 : TargetRegisterInfo(&LanaiRegInfoDesc,
327 LanaiSubRegIndexStrings, LanaiSubRegIndexNameOffsets,
328 LanaiSubRegIdxRangeTable, LanaiSubRegIndexLaneMaskTable,
329
330 LaneBitmask(0xFFFFFFFFFFFFFFFE), LanaiRegClassInfos, LanaiVTLists, HwMode) {
331 InitMCRegisterInfo(D: LanaiRegDesc, NR: 41, RA, PC,
332 C: &getLanaiMCRegisterClass(RC: 0), NC: 3, RURoots: LanaiRegUnitRoots, NRU: 33, DL: LanaiRegDiffLists,
333 RUMS: LanaiLaneMaskLists, Strings: LanaiRegStrings, ClassStrings: LanaiRegClassStrings, SubIndices: LanaiSubRegIdxLists, NumIndices: 2,
334 RET: LanaiRegEncodingTable, RUI: nullptr);
335
336 switch (DwarfFlavour) {
337 default:
338 llvm_unreachable("Unknown DWARF flavour");
339 case 0:
340 mapDwarfRegsToLLVMRegs(Map: LanaiDwarfFlavour0Dwarf2L, Size: LanaiDwarfFlavour0Dwarf2LSize, isEH: false);
341 break;
342 }
343 switch (EHFlavour) {
344 default:
345 llvm_unreachable("Unknown DWARF flavour");
346 case 0:
347 mapDwarfRegsToLLVMRegs(Map: LanaiEHFlavour0Dwarf2L, Size: LanaiEHFlavour0Dwarf2LSize, isEH: true);
348 break;
349 }
350 switch (DwarfFlavour) {
351 default:
352 llvm_unreachable("Unknown DWARF flavour");
353 case 0:
354 mapLLVMRegsToDwarfRegs(Map: LanaiDwarfFlavour0L2Dwarf, Size: LanaiDwarfFlavour0L2DwarfSize, isEH: false);
355 break;
356 }
357 switch (EHFlavour) {
358 default:
359 llvm_unreachable("Unknown DWARF flavour");
360 case 0:
361 mapLLVMRegsToDwarfRegs(Map: LanaiEHFlavour0L2Dwarf, Size: LanaiEHFlavour0L2DwarfSize, isEH: true);
362 break;
363 }
364}
365
366static const MCPhysReg CSR_SaveList[] = { 0 };
367static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, };
368
369
370ArrayRef<const uint32_t *> LanaiGenRegisterInfo::getRegMasks() const {
371 static const uint32_t *const Masks[] = {
372 CSR_RegMask,
373 };
374 return ArrayRef(Masks);
375}
376
377bool LanaiGenRegisterInfo::
378isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
379 return
380 false;
381}
382
383bool LanaiGenRegisterInfo::
384isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
385 return
386 false;
387}
388
389bool LanaiGenRegisterInfo::
390isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
391 return
392 false;
393}
394
395bool LanaiGenRegisterInfo::
396isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
397 return
398 false;
399}
400
401bool LanaiGenRegisterInfo::
402isConstantPhysReg(MCRegister PhysReg) const {
403 return
404 false;
405}
406
407ArrayRef<const char *> LanaiGenRegisterInfo::getRegMaskNames() const {
408 static const char *Names[] = {
409 "CSR",
410 };
411 return ArrayRef(Names);
412}
413
414const LanaiFrameLowering *
415LanaiGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
416 return static_cast<const LanaiFrameLowering *>(
417 MF.getSubtarget().getFrameLowering());
418}
419
420
421} // namespace llvm
422