| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* * LoongArch Disassembler *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | |
| 10 | #include "llvm/MC/MCInst.h" |
| 11 | #include "llvm/MC/MCSubtargetInfo.h" |
| 12 | #include "llvm/Support/DataTypes.h" |
| 13 | #include "llvm/Support/Debug.h" |
| 14 | #include "llvm/Support/LEB128.h" |
| 15 | #include "llvm/Support/raw_ostream.h" |
| 16 | #include "llvm/TargetParser/SubtargetFeature.h" |
| 17 | #include <assert.h> |
| 18 | |
| 19 | namespace { |
| 20 | |
| 21 | // InsnBitWidth is essentially a type trait used by the decoder emitter to query |
| 22 | // the supported bitwidth for a given type. But default, the value is 0, making |
| 23 | // it an invalid type for use as `InsnType` when instantiating the decoder. |
| 24 | // Individual targets are expected to provide specializations for these based |
| 25 | // on their usage. |
| 26 | template <typename T> constexpr uint32_t InsnBitWidth = 0; |
| 27 | |
| 28 | static const uint8_t DecoderTable32[16024] = { |
| 29 | OPC_SwitchField, 26, 6, // 0: switch Inst[31:26] { |
| 30 | 0, 218, 21, // 3: case 0x0: { |
| 31 | OPC_SwitchField, 22, 4, // 6: switch Inst[25:22] { |
| 32 | 0, 225, 12, // 9: case 0x0: { |
| 33 | OPC_SwitchField, 18, 4, // 12: switch Inst[21:18] { |
| 34 | 0, 252, 2, // 15: case 0x0: { |
| 35 | OPC_SwitchField, 15, 3, // 18: switch Inst[17:15] { |
| 36 | 0, 227, 1, // 21: case 0x0: { |
| 37 | OPC_SwitchField, 10, 5, // 24: switch Inst[14:10] { |
| 38 | 2, 8, // 27: case 0x2: { |
| 39 | OPC_CheckField, 2, 3, 0, // 29: check Inst[4:2] == 0x0 |
| 40 | OPC_Decode, 169, 6, 0, // 33: decode to MOVGR2SCR using decoder 0 |
| 41 | // 33: } |
| 42 | 3, 8, // 37: case 0x3: { |
| 43 | OPC_CheckField, 7, 3, 0, // 39: check Inst[9:7] == 0x0 |
| 44 | OPC_Decode, 170, 6, 1, // 43: decode to MOVSCR2GR using decoder 1 |
| 45 | // 43: } |
| 46 | 4, 4, // 47: case 0x4: { |
| 47 | OPC_Decode, 180, 4, 2, // 49: decode to CLO_W using decoder 2 |
| 48 | // 49: } |
| 49 | 5, 4, // 53: case 0x5: { |
| 50 | OPC_Decode, 182, 4, 2, // 55: decode to CLZ_W using decoder 2 |
| 51 | // 55: } |
| 52 | 6, 4, // 59: case 0x6: { |
| 53 | OPC_Decode, 196, 4, 2, // 61: decode to CTO_W using decoder 2 |
| 54 | // 61: } |
| 55 | 7, 4, // 65: case 0x7: { |
| 56 | OPC_Decode, 198, 4, 2, // 67: decode to CTZ_W using decoder 2 |
| 57 | // 67: } |
| 58 | 8, 6, // 71: case 0x8: { |
| 59 | OPC_CheckPredicate, 0, // 73: check predicate 0 |
| 60 | OPC_Decode, 179, 4, 2, // 75: decode to CLO_D using decoder 2 |
| 61 | // 75: } |
| 62 | 9, 6, // 79: case 0x9: { |
| 63 | OPC_CheckPredicate, 0, // 81: check predicate 0 |
| 64 | OPC_Decode, 181, 4, 2, // 83: decode to CLZ_D using decoder 2 |
| 65 | // 83: } |
| 66 | 10, 6, // 87: case 0xa: { |
| 67 | OPC_CheckPredicate, 0, // 89: check predicate 0 |
| 68 | OPC_Decode, 195, 4, 2, // 91: decode to CTO_D using decoder 2 |
| 69 | // 91: } |
| 70 | 11, 6, // 95: case 0xb: { |
| 71 | OPC_CheckPredicate, 0, // 97: check predicate 0 |
| 72 | OPC_Decode, 197, 4, 2, // 99: decode to CTZ_D using decoder 2 |
| 73 | // 99: } |
| 74 | 12, 4, // 103: case 0xc: { |
| 75 | OPC_Decode, 200, 6, 2, // 105: decode to REVB_2H using decoder 2 |
| 76 | // 105: } |
| 77 | 13, 6, // 109: case 0xd: { |
| 78 | OPC_CheckPredicate, 0, // 111: check predicate 0 |
| 79 | OPC_Decode, 202, 6, 2, // 113: decode to REVB_4H using decoder 2 |
| 80 | // 113: } |
| 81 | 14, 6, // 117: case 0xe: { |
| 82 | OPC_CheckPredicate, 0, // 119: check predicate 0 |
| 83 | OPC_Decode, 201, 6, 2, // 121: decode to REVB_2W using decoder 2 |
| 84 | // 121: } |
| 85 | 15, 6, // 125: case 0xf: { |
| 86 | OPC_CheckPredicate, 0, // 127: check predicate 0 |
| 87 | OPC_Decode, 203, 6, 2, // 129: decode to REVB_D using decoder 2 |
| 88 | // 129: } |
| 89 | 16, 6, // 133: case 0x10: { |
| 90 | OPC_CheckPredicate, 0, // 135: check predicate 0 |
| 91 | OPC_Decode, 204, 6, 2, // 137: decode to REVH_2W using decoder 2 |
| 92 | // 137: } |
| 93 | 17, 6, // 141: case 0x11: { |
| 94 | OPC_CheckPredicate, 0, // 143: check predicate 0 |
| 95 | OPC_Decode, 205, 6, 2, // 145: decode to REVH_D using decoder 2 |
| 96 | // 145: } |
| 97 | 18, 4, // 149: case 0x12: { |
| 98 | OPC_Decode, 162, 4, 2, // 151: decode to BITREV_4B using decoder 2 |
| 99 | // 151: } |
| 100 | 19, 6, // 155: case 0x13: { |
| 101 | OPC_CheckPredicate, 0, // 157: check predicate 0 |
| 102 | OPC_Decode, 163, 4, 2, // 159: decode to BITREV_8B using decoder 2 |
| 103 | // 159: } |
| 104 | 20, 4, // 163: case 0x14: { |
| 105 | OPC_Decode, 165, 4, 2, // 165: decode to BITREV_W using decoder 2 |
| 106 | // 165: } |
| 107 | 21, 6, // 169: case 0x15: { |
| 108 | OPC_CheckPredicate, 0, // 171: check predicate 0 |
| 109 | OPC_Decode, 164, 4, 2, // 173: decode to BITREV_D using decoder 2 |
| 110 | // 173: } |
| 111 | 22, 4, // 177: case 0x16: { |
| 112 | OPC_Decode, 207, 4, 2, // 179: decode to EXT_W_H using decoder 2 |
| 113 | // 179: } |
| 114 | 23, 4, // 183: case 0x17: { |
| 115 | OPC_Decode, 206, 4, 2, // 185: decode to EXT_W_B using decoder 2 |
| 116 | // 185: } |
| 117 | 24, 4, // 189: case 0x18: { |
| 118 | OPC_Decode, 198, 6, 2, // 191: decode to RDTIMEL_W using decoder 2 |
| 119 | // 191: } |
| 120 | 25, 4, // 195: case 0x19: { |
| 121 | OPC_Decode, 197, 6, 2, // 197: decode to RDTIMEH_W using decoder 2 |
| 122 | // 197: } |
| 123 | 26, 6, // 201: case 0x1a: { |
| 124 | OPC_CheckPredicate, 0, // 203: check predicate 0 |
| 125 | OPC_Decode, 199, 6, 2, // 205: decode to RDTIME_D using decoder 2 |
| 126 | // 205: } |
| 127 | 27, 4, // 209: case 0x1b: { |
| 128 | OPC_Decode, 183, 4, 2, // 211: decode to CPUCFG using decoder 2 |
| 129 | // 211: } |
| 130 | 28, 12, // 215: case 0x1c: { |
| 131 | OPC_CheckField, 8, 2, 0, // 217: check Inst[9:8] == 0x0 |
| 132 | OPC_CheckField, 0, 5, 0, // 221: check Inst[4:0] == 0x0 |
| 133 | OPC_Decode, 137, 13, 3, // 225: decode to X86MTTOP using decoder 3 |
| 134 | // 225: } |
| 135 | 29, 8, // 229: case 0x1d: { |
| 136 | OPC_CheckField, 5, 5, 0, // 231: check Inst[9:5] == 0x0 |
| 137 | OPC_Decode, 135, 13, 4, // 235: decode to X86MFTOP using decoder 4 |
| 138 | // 235: } |
| 139 | 30, 4, // 239: case 0x1e: { |
| 140 | OPC_Decode, 225, 6, 2, // 241: decode to SETX86LOOPE using decoder 2 |
| 141 | // 241: } |
| 142 | 31, 0, // 245: case 0x1f: { |
| 143 | OPC_Decode, 226, 6, 2, // 247: decode to SETX86LOOPNE using decoder 2 |
| 144 | // 247: } |
| 145 | // 247: } // switch Inst[14:10] |
| 146 | // 247: } |
| 147 | 1, 121, // 251: case 0x1: { |
| 148 | OPC_SwitchField, 0, 5, // 253: switch Inst[4:0] { |
| 149 | 0, 8, // 256: case 0x0: { |
| 150 | OPC_CheckField, 10, 5, 0, // 258: check Inst[14:10] == 0x0 |
| 151 | OPC_Decode, 130, 13, 5, // 262: decode to X86INC_B using decoder 5 |
| 152 | // 262: } |
| 153 | 1, 8, // 266: case 0x1: { |
| 154 | OPC_CheckField, 10, 5, 0, // 268: check Inst[14:10] == 0x0 |
| 155 | OPC_Decode, 132, 13, 5, // 272: decode to X86INC_H using decoder 5 |
| 156 | // 272: } |
| 157 | 2, 8, // 276: case 0x2: { |
| 158 | OPC_CheckField, 10, 5, 0, // 278: check Inst[14:10] == 0x0 |
| 159 | OPC_Decode, 133, 13, 5, // 282: decode to X86INC_W using decoder 5 |
| 160 | // 282: } |
| 161 | 3, 10, // 286: case 0x3: { |
| 162 | OPC_CheckPredicate, 0, // 288: check predicate 0 |
| 163 | OPC_CheckField, 10, 5, 0, // 290: check Inst[14:10] == 0x0 |
| 164 | OPC_Decode, 131, 13, 5, // 294: decode to X86INC_D using decoder 5 |
| 165 | // 294: } |
| 166 | 4, 8, // 298: case 0x4: { |
| 167 | OPC_CheckField, 10, 5, 0, // 300: check Inst[14:10] == 0x0 |
| 168 | OPC_Decode, 253, 12, 5, // 304: decode to X86DEC_B using decoder 5 |
| 169 | // 304: } |
| 170 | 5, 8, // 308: case 0x5: { |
| 171 | OPC_CheckField, 10, 5, 0, // 310: check Inst[14:10] == 0x0 |
| 172 | OPC_Decode, 255, 12, 5, // 314: decode to X86DEC_H using decoder 5 |
| 173 | // 314: } |
| 174 | 6, 8, // 318: case 0x6: { |
| 175 | OPC_CheckField, 10, 5, 0, // 320: check Inst[14:10] == 0x0 |
| 176 | OPC_Decode, 128, 13, 5, // 324: decode to X86DEC_W using decoder 5 |
| 177 | // 324: } |
| 178 | 7, 10, // 328: case 0x7: { |
| 179 | OPC_CheckPredicate, 0, // 330: check predicate 0 |
| 180 | OPC_CheckField, 10, 5, 0, // 332: check Inst[14:10] == 0x0 |
| 181 | OPC_Decode, 254, 12, 5, // 336: decode to X86DEC_D using decoder 5 |
| 182 | // 336: } |
| 183 | 8, 15, // 340: case 0x8: { |
| 184 | OPC_SwitchField, 5, 10, // 342: switch Inst[14:5] { |
| 185 | 0, 4, // 345: case 0x0: { |
| 186 | OPC_Decode, 187, 13, 6, // 347: decode to X86SETTM using decoder 6 |
| 187 | // 347: } |
| 188 | 1, 0, // 351: case 0x1: { |
| 189 | OPC_Decode, 251, 12, 6, // 353: decode to X86CLRTM using decoder 6 |
| 190 | // 353: } |
| 191 | // 353: } // switch Inst[14:5] |
| 192 | // 353: } |
| 193 | 9, 0, // 357: case 0x9: { |
| 194 | OPC_SwitchField, 5, 10, // 359: switch Inst[14:5] { |
| 195 | 0, 4, // 362: case 0x0: { |
| 196 | OPC_Decode, 129, 13, 6, // 364: decode to X86INCTOP using decoder 6 |
| 197 | // 364: } |
| 198 | 1, 0, // 368: case 0x1: { |
| 199 | OPC_Decode, 252, 12, 6, // 370: decode to X86DECTOP using decoder 6 |
| 200 | // 370: } |
| 201 | // 370: } // switch Inst[14:5] |
| 202 | // 370: } |
| 203 | // 370: } // switch Inst[4:0] |
| 204 | // 370: } |
| 205 | 2, 10, // 374: case 0x2: { |
| 206 | OPC_CheckPredicate, 0, // 376: check predicate 0 |
| 207 | OPC_CheckField, 0, 5, 0, // 378: check Inst[4:0] == 0x0 |
| 208 | OPC_Decode, 154, 4, 7, // 382: decode to ASRTLE_D using decoder 7 |
| 209 | // 382: } |
| 210 | 3, 0, // 386: case 0x3: { |
| 211 | OPC_CheckPredicate, 0, // 388: check predicate 0 |
| 212 | OPC_CheckField, 0, 5, 0, // 390: check Inst[4:0] == 0x0 |
| 213 | OPC_Decode, 153, 4, 7, // 394: decode to ASRTGT_D using decoder 7 |
| 214 | // 394: } |
| 215 | // 394: } // switch Inst[17:15] |
| 216 | // 394: } |
| 217 | 1, 17, // 398: case 0x1: { |
| 218 | OPC_SwitchField, 17, 1, // 400: switch Inst[17] { |
| 219 | 0, 4, // 403: case 0x0: { |
| 220 | OPC_Decode, 202, 3, 8, // 405: decode to ALSL_W using decoder 8 |
| 221 | // 405: } |
| 222 | 1, 0, // 409: case 0x1: { |
| 223 | OPC_CheckPredicate, 0, // 411: check predicate 0 |
| 224 | OPC_Decode, 203, 3, 8, // 413: decode to ALSL_WU using decoder 8 |
| 225 | // 413: } |
| 226 | // 413: } // switch Inst[17] |
| 227 | // 413: } |
| 228 | 2, 8, // 417: case 0x2: { |
| 229 | OPC_CheckField, 17, 1, 0, // 419: check Inst[17] == 0x0 |
| 230 | OPC_Decode, 177, 4, 9, // 423: decode to BYTEPICK_W using decoder 9 |
| 231 | // 423: } |
| 232 | 3, 6, // 427: case 0x3: { |
| 233 | OPC_CheckPredicate, 0, // 429: check predicate 0 |
| 234 | OPC_Decode, 176, 4, 10, // 431: decode to BYTEPICK_D using decoder 10 |
| 235 | // 431: } |
| 236 | 4, 55, // 435: case 0x4: { |
| 237 | OPC_SwitchField, 15, 3, // 437: switch Inst[17:15] { |
| 238 | 0, 4, // 440: case 0x0: { |
| 239 | OPC_Decode, 200, 3, 11, // 442: decode to ADD_W using decoder 11 |
| 240 | // 442: } |
| 241 | 1, 6, // 446: case 0x1: { |
| 242 | OPC_CheckPredicate, 0, // 448: check predicate 0 |
| 243 | OPC_Decode, 199, 3, 11, // 450: decode to ADD_D using decoder 11 |
| 244 | // 450: } |
| 245 | 2, 4, // 454: case 0x2: { |
| 246 | OPC_Decode, 140, 7, 11, // 456: decode to SUB_W using decoder 11 |
| 247 | // 456: } |
| 248 | 3, 6, // 460: case 0x3: { |
| 249 | OPC_CheckPredicate, 0, // 462: check predicate 0 |
| 250 | OPC_Decode, 139, 7, 11, // 464: decode to SUB_D using decoder 11 |
| 251 | // 464: } |
| 252 | 4, 4, // 468: case 0x4: { |
| 253 | OPC_Decode, 233, 6, 11, // 470: decode to SLT using decoder 11 |
| 254 | // 470: } |
| 255 | 5, 4, // 474: case 0x5: { |
| 256 | OPC_Decode, 235, 6, 11, // 476: decode to SLTU using decoder 11 |
| 257 | // 476: } |
| 258 | 6, 4, // 480: case 0x6: { |
| 259 | OPC_Decode, 149, 6, 11, // 482: decode to MASKEQZ using decoder 11 |
| 260 | // 482: } |
| 261 | 7, 0, // 486: case 0x7: { |
| 262 | OPC_Decode, 150, 6, 11, // 488: decode to MASKNEZ using decoder 11 |
| 263 | // 488: } |
| 264 | // 488: } // switch Inst[17:15] |
| 265 | // 488: } |
| 266 | 5, 51, // 492: case 0x5: { |
| 267 | OPC_SwitchField, 15, 3, // 494: switch Inst[17:15] { |
| 268 | 0, 4, // 497: case 0x0: { |
| 269 | OPC_Decode, 179, 6, 11, // 499: decode to NOR using decoder 11 |
| 270 | // 499: } |
| 271 | 1, 4, // 503: case 0x1: { |
| 272 | OPC_Decode, 128, 4, 11, // 505: decode to AND using decoder 11 |
| 273 | // 505: } |
| 274 | 2, 4, // 509: case 0x2: { |
| 275 | OPC_Decode, 180, 6, 11, // 511: decode to OR using decoder 11 |
| 276 | // 511: } |
| 277 | 3, 4, // 515: case 0x3: { |
| 278 | OPC_Decode, 222, 13, 11, // 517: decode to XOR using decoder 11 |
| 279 | // 517: } |
| 280 | 4, 4, // 521: case 0x4: { |
| 281 | OPC_Decode, 182, 6, 11, // 523: decode to ORN using decoder 11 |
| 282 | // 523: } |
| 283 | 5, 4, // 527: case 0x5: { |
| 284 | OPC_Decode, 130, 4, 11, // 529: decode to ANDN using decoder 11 |
| 285 | // 529: } |
| 286 | 6, 4, // 533: case 0x6: { |
| 287 | OPC_Decode, 232, 6, 11, // 535: decode to SLL_W using decoder 11 |
| 288 | // 535: } |
| 289 | 7, 0, // 539: case 0x7: { |
| 290 | OPC_Decode, 244, 6, 11, // 541: decode to SRL_W using decoder 11 |
| 291 | // 541: } |
| 292 | // 541: } // switch Inst[17:15] |
| 293 | // 541: } |
| 294 | 6, 59, // 545: case 0x6: { |
| 295 | OPC_SwitchField, 15, 3, // 547: switch Inst[17:15] { |
| 296 | 0, 4, // 550: case 0x0: { |
| 297 | OPC_Decode, 240, 6, 11, // 552: decode to SRA_W using decoder 11 |
| 298 | // 552: } |
| 299 | 1, 6, // 556: case 0x1: { |
| 300 | OPC_CheckPredicate, 0, // 558: check predicate 0 |
| 301 | OPC_Decode, 231, 6, 11, // 560: decode to SLL_D using decoder 11 |
| 302 | // 560: } |
| 303 | 2, 6, // 564: case 0x2: { |
| 304 | OPC_CheckPredicate, 0, // 566: check predicate 0 |
| 305 | OPC_Decode, 243, 6, 11, // 568: decode to SRL_D using decoder 11 |
| 306 | // 568: } |
| 307 | 3, 6, // 572: case 0x3: { |
| 308 | OPC_CheckPredicate, 0, // 574: check predicate 0 |
| 309 | OPC_Decode, 239, 6, 11, // 576: decode to SRA_D using decoder 11 |
| 310 | // 576: } |
| 311 | 4, 4, // 580: case 0x4: { |
| 312 | OPC_Decode, 210, 6, 11, // 582: decode to ROTR_B using decoder 11 |
| 313 | // 582: } |
| 314 | 5, 4, // 586: case 0x5: { |
| 315 | OPC_Decode, 212, 6, 11, // 588: decode to ROTR_H using decoder 11 |
| 316 | // 588: } |
| 317 | 6, 4, // 592: case 0x6: { |
| 318 | OPC_Decode, 213, 6, 11, // 594: decode to ROTR_W using decoder 11 |
| 319 | // 594: } |
| 320 | 7, 0, // 598: case 0x7: { |
| 321 | OPC_CheckPredicate, 0, // 600: check predicate 0 |
| 322 | OPC_Decode, 211, 6, 11, // 602: decode to ROTR_D using decoder 11 |
| 323 | // 602: } |
| 324 | // 602: } // switch Inst[17:15] |
| 325 | // 602: } |
| 326 | 7, 61, // 606: case 0x7: { |
| 327 | OPC_SwitchField, 15, 3, // 608: switch Inst[17:15] { |
| 328 | 0, 4, // 611: case 0x0: { |
| 329 | OPC_Decode, 178, 6, 11, // 613: decode to MUL_W using decoder 11 |
| 330 | // 613: } |
| 331 | 1, 4, // 617: case 0x1: { |
| 332 | OPC_Decode, 173, 6, 11, // 619: decode to MULH_W using decoder 11 |
| 333 | // 619: } |
| 334 | 2, 4, // 623: case 0x2: { |
| 335 | OPC_Decode, 174, 6, 11, // 625: decode to MULH_WU using decoder 11 |
| 336 | // 625: } |
| 337 | 3, 6, // 629: case 0x3: { |
| 338 | OPC_CheckPredicate, 0, // 631: check predicate 0 |
| 339 | OPC_Decode, 177, 6, 11, // 633: decode to MUL_D using decoder 11 |
| 340 | // 633: } |
| 341 | 4, 6, // 637: case 0x4: { |
| 342 | OPC_CheckPredicate, 0, // 639: check predicate 0 |
| 343 | OPC_Decode, 171, 6, 11, // 641: decode to MULH_D using decoder 11 |
| 344 | // 641: } |
| 345 | 5, 6, // 645: case 0x5: { |
| 346 | OPC_CheckPredicate, 0, // 647: check predicate 0 |
| 347 | OPC_Decode, 172, 6, 11, // 649: decode to MULH_DU using decoder 11 |
| 348 | // 649: } |
| 349 | 6, 6, // 653: case 0x6: { |
| 350 | OPC_CheckPredicate, 0, // 655: check predicate 0 |
| 351 | OPC_Decode, 175, 6, 11, // 657: decode to MULW_D_W using decoder 11 |
| 352 | // 657: } |
| 353 | 7, 0, // 661: case 0x7: { |
| 354 | OPC_CheckPredicate, 0, // 663: check predicate 0 |
| 355 | OPC_Decode, 176, 6, 11, // 665: decode to MULW_D_WU using decoder 11 |
| 356 | // 665: } |
| 357 | // 665: } // switch Inst[17:15] |
| 358 | // 665: } |
| 359 | 8, 59, // 669: case 0x8: { |
| 360 | OPC_SwitchField, 15, 3, // 671: switch Inst[17:15] { |
| 361 | 0, 4, // 674: case 0x0: { |
| 362 | OPC_Decode, 203, 4, 11, // 676: decode to DIV_W using decoder 11 |
| 363 | // 676: } |
| 364 | 1, 4, // 680: case 0x1: { |
| 365 | OPC_Decode, 153, 6, 11, // 682: decode to MOD_W using decoder 11 |
| 366 | // 682: } |
| 367 | 2, 4, // 686: case 0x2: { |
| 368 | OPC_Decode, 204, 4, 11, // 688: decode to DIV_WU using decoder 11 |
| 369 | // 688: } |
| 370 | 3, 4, // 692: case 0x3: { |
| 371 | OPC_Decode, 154, 6, 11, // 694: decode to MOD_WU using decoder 11 |
| 372 | // 694: } |
| 373 | 4, 6, // 698: case 0x4: { |
| 374 | OPC_CheckPredicate, 0, // 700: check predicate 0 |
| 375 | OPC_Decode, 201, 4, 11, // 702: decode to DIV_D using decoder 11 |
| 376 | // 702: } |
| 377 | 5, 6, // 706: case 0x5: { |
| 378 | OPC_CheckPredicate, 0, // 708: check predicate 0 |
| 379 | OPC_Decode, 151, 6, 11, // 710: decode to MOD_D using decoder 11 |
| 380 | // 710: } |
| 381 | 6, 6, // 714: case 0x6: { |
| 382 | OPC_CheckPredicate, 0, // 716: check predicate 0 |
| 383 | OPC_Decode, 202, 4, 11, // 718: decode to DIV_DU using decoder 11 |
| 384 | // 718: } |
| 385 | 7, 0, // 722: case 0x7: { |
| 386 | OPC_CheckPredicate, 0, // 724: check predicate 0 |
| 387 | OPC_Decode, 152, 6, 11, // 726: decode to MOD_DU using decoder 11 |
| 388 | // 726: } |
| 389 | // 726: } // switch Inst[17:15] |
| 390 | // 726: } |
| 391 | 9, 67, // 730: case 0x9: { |
| 392 | OPC_SwitchField, 15, 3, // 732: switch Inst[17:15] { |
| 393 | 0, 6, // 735: case 0x0: { |
| 394 | OPC_CheckPredicate, 0, // 737: check predicate 0 |
| 395 | OPC_Decode, 188, 4, 11, // 739: decode to CRC_W_B_W using decoder 11 |
| 396 | // 739: } |
| 397 | 1, 6, // 743: case 0x1: { |
| 398 | OPC_CheckPredicate, 0, // 745: check predicate 0 |
| 399 | OPC_Decode, 190, 4, 11, // 747: decode to CRC_W_H_W using decoder 11 |
| 400 | // 747: } |
| 401 | 2, 6, // 751: case 0x2: { |
| 402 | OPC_CheckPredicate, 0, // 753: check predicate 0 |
| 403 | OPC_Decode, 191, 4, 11, // 755: decode to CRC_W_W_W using decoder 11 |
| 404 | // 755: } |
| 405 | 3, 6, // 759: case 0x3: { |
| 406 | OPC_CheckPredicate, 0, // 761: check predicate 0 |
| 407 | OPC_Decode, 189, 4, 11, // 763: decode to CRC_W_D_W using decoder 11 |
| 408 | // 763: } |
| 409 | 4, 6, // 767: case 0x4: { |
| 410 | OPC_CheckPredicate, 0, // 769: check predicate 0 |
| 411 | OPC_Decode, 184, 4, 11, // 771: decode to CRCC_W_B_W using decoder 11 |
| 412 | // 771: } |
| 413 | 5, 6, // 775: case 0x5: { |
| 414 | OPC_CheckPredicate, 0, // 777: check predicate 0 |
| 415 | OPC_Decode, 186, 4, 11, // 779: decode to CRCC_W_H_W using decoder 11 |
| 416 | // 779: } |
| 417 | 6, 6, // 783: case 0x6: { |
| 418 | OPC_CheckPredicate, 0, // 785: check predicate 0 |
| 419 | OPC_Decode, 187, 4, 11, // 787: decode to CRCC_W_W_W using decoder 11 |
| 420 | // 787: } |
| 421 | 7, 0, // 791: case 0x7: { |
| 422 | OPC_CheckPredicate, 0, // 793: check predicate 0 |
| 423 | OPC_Decode, 185, 4, 11, // 795: decode to CRCC_W_D_W using decoder 11 |
| 424 | // 795: } |
| 425 | // 795: } // switch Inst[17:15] |
| 426 | // 795: } |
| 427 | 10, 41, // 799: case 0xa: { |
| 428 | OPC_SwitchField, 15, 3, // 801: switch Inst[17:15] { |
| 429 | 2, 4, // 804: case 0x2: { |
| 430 | OPC_Decode, 197, 3, 12, // 806: decode to ADDU12I_W using decoder 12 |
| 431 | // 806: } |
| 432 | 3, 6, // 810: case 0x3: { |
| 433 | OPC_CheckPredicate, 0, // 812: check predicate 0 |
| 434 | OPC_Decode, 196, 3, 12, // 814: decode to ADDU12I_D using decoder 12 |
| 435 | // 814: } |
| 436 | 4, 4, // 818: case 0x4: { |
| 437 | OPC_Decode, 171, 4, 13, // 820: decode to BREAK using decoder 13 |
| 438 | // 820: } |
| 439 | 5, 4, // 824: case 0x5: { |
| 440 | OPC_Decode, 200, 4, 13, // 826: decode to DBCL using decoder 13 |
| 441 | // 826: } |
| 442 | 6, 4, // 830: case 0x6: { |
| 443 | OPC_Decode, 141, 7, 13, // 832: decode to SYSCALL using decoder 13 |
| 444 | // 832: } |
| 445 | 7, 0, // 836: case 0x7: { |
| 446 | OPC_Decode, 225, 5, 13, // 838: decode to HVCL using decoder 13 |
| 447 | // 838: } |
| 448 | // 838: } // switch Inst[17:15] |
| 449 | // 838: } |
| 450 | 11, 10, // 842: case 0xb: { |
| 451 | OPC_CheckPredicate, 0, // 844: check predicate 0 |
| 452 | OPC_CheckField, 17, 1, 0, // 846: check Inst[17] == 0x0 |
| 453 | OPC_Decode, 201, 3, 8, // 850: decode to ALSL_D using decoder 8 |
| 454 | // 850: } |
| 455 | 12, 55, // 854: case 0xc: { |
| 456 | OPC_SwitchField, 15, 3, // 856: switch Inst[17:15] { |
| 457 | 0, 4, // 859: case 0x0: { |
| 458 | OPC_Decode, 190, 3, 11, // 861: decode to ADC_B using decoder 11 |
| 459 | // 861: } |
| 460 | 1, 4, // 865: case 0x1: { |
| 461 | OPC_Decode, 192, 3, 11, // 867: decode to ADC_H using decoder 11 |
| 462 | // 867: } |
| 463 | 2, 4, // 871: case 0x2: { |
| 464 | OPC_Decode, 193, 3, 11, // 873: decode to ADC_W using decoder 11 |
| 465 | // 873: } |
| 466 | 3, 6, // 877: case 0x3: { |
| 467 | OPC_CheckPredicate, 0, // 879: check predicate 0 |
| 468 | OPC_Decode, 191, 3, 11, // 881: decode to ADC_D using decoder 11 |
| 469 | // 881: } |
| 470 | 4, 4, // 885: case 0x4: { |
| 471 | OPC_Decode, 214, 6, 11, // 887: decode to SBC_B using decoder 11 |
| 472 | // 887: } |
| 473 | 5, 4, // 891: case 0x5: { |
| 474 | OPC_Decode, 216, 6, 11, // 893: decode to SBC_H using decoder 11 |
| 475 | // 893: } |
| 476 | 6, 4, // 897: case 0x6: { |
| 477 | OPC_Decode, 217, 6, 11, // 899: decode to SBC_W using decoder 11 |
| 478 | // 899: } |
| 479 | 7, 0, // 903: case 0x7: { |
| 480 | OPC_CheckPredicate, 0, // 905: check predicate 0 |
| 481 | OPC_Decode, 215, 6, 11, // 907: decode to SBC_D using decoder 11 |
| 482 | // 907: } |
| 483 | // 907: } // switch Inst[17:15] |
| 484 | // 907: } |
| 485 | 13, 84, // 911: case 0xd: { |
| 486 | OPC_SwitchField, 15, 3, // 913: switch Inst[17:15] { |
| 487 | 0, 4, // 916: case 0x0: { |
| 488 | OPC_Decode, 193, 6, 11, // 918: decode to RCR_B using decoder 11 |
| 489 | // 918: } |
| 490 | 1, 4, // 922: case 0x1: { |
| 491 | OPC_Decode, 195, 6, 11, // 924: decode to RCR_H using decoder 11 |
| 492 | // 924: } |
| 493 | 2, 4, // 928: case 0x2: { |
| 494 | OPC_Decode, 196, 6, 11, // 930: decode to RCR_W using decoder 11 |
| 495 | // 930: } |
| 496 | 3, 6, // 934: case 0x3: { |
| 497 | OPC_CheckPredicate, 0, // 936: check predicate 0 |
| 498 | OPC_Decode, 194, 6, 11, // 938: decode to RCR_D using decoder 11 |
| 499 | // 938: } |
| 500 | 4, 8, // 942: case 0x4: { |
| 501 | OPC_CheckField, 14, 1, 1, // 944: check Inst[14] == 0x1 |
| 502 | OPC_Decode, 135, 4, 14, // 948: decode to ARMMOVE using decoder 14 |
| 503 | // 948: } |
| 504 | 5, 23, // 952: case 0x5: { |
| 505 | OPC_SwitchField, 14, 1, // 954: switch Inst[14] { |
| 506 | 0, 8, // 957: case 0x0: { |
| 507 | OPC_CheckField, 5, 5, 0, // 959: check Inst[9:5] == 0x0 |
| 508 | OPC_Decode, 224, 6, 15, // 963: decode to SETX86J using decoder 15 |
| 509 | // 963: } |
| 510 | 1, 0, // 967: case 0x1: { |
| 511 | OPC_CheckField, 5, 5, 0, // 969: check Inst[9:5] == 0x0 |
| 512 | OPC_Decode, 223, 6, 15, // 973: decode to SETARMJ using decoder 15 |
| 513 | // 973: } |
| 514 | // 973: } // switch Inst[14] |
| 515 | // 973: } |
| 516 | 6, 8, // 977: case 0x6: { |
| 517 | OPC_CheckField, 4, 1, 1, // 979: check Inst[4] == 0x1 |
| 518 | OPC_Decode, 132, 4, 16, // 983: decode to ARMADD_W using decoder 16 |
| 519 | // 983: } |
| 520 | 7, 0, // 987: case 0x7: { |
| 521 | OPC_CheckField, 4, 1, 1, // 989: check Inst[4] == 0x1 |
| 522 | OPC_Decode, 151, 4, 16, // 993: decode to ARMSUB_W using decoder 16 |
| 523 | // 993: } |
| 524 | // 993: } // switch Inst[17:15] |
| 525 | // 993: } |
| 526 | 14, 83, // 997: case 0xe: { |
| 527 | OPC_SwitchField, 15, 3, // 999: switch Inst[17:15] { |
| 528 | 0, 8, // 1002: case 0x0: { |
| 529 | OPC_CheckField, 4, 1, 1, // 1004: check Inst[4] == 0x1 |
| 530 | OPC_Decode, 131, 4, 16, // 1008: decode to ARMADC_W using decoder 16 |
| 531 | // 1008: } |
| 532 | 1, 8, // 1012: case 0x1: { |
| 533 | OPC_CheckField, 4, 1, 1, // 1014: check Inst[4] == 0x1 |
| 534 | OPC_Decode, 144, 4, 16, // 1018: decode to ARMSBC_W using decoder 16 |
| 535 | // 1018: } |
| 536 | 2, 8, // 1022: case 0x2: { |
| 537 | OPC_CheckField, 4, 1, 1, // 1024: check Inst[4] == 0x1 |
| 538 | OPC_Decode, 133, 4, 16, // 1028: decode to ARMAND_W using decoder 16 |
| 539 | // 1028: } |
| 540 | 3, 8, // 1032: case 0x3: { |
| 541 | OPC_CheckField, 4, 1, 1, // 1034: check Inst[4] == 0x1 |
| 542 | OPC_Decode, 140, 4, 16, // 1038: decode to ARMOR_W using decoder 16 |
| 543 | // 1038: } |
| 544 | 4, 8, // 1042: case 0x4: { |
| 545 | OPC_CheckField, 4, 1, 1, // 1044: check Inst[4] == 0x1 |
| 546 | OPC_Decode, 152, 4, 16, // 1048: decode to ARMXOR_W using decoder 16 |
| 547 | // 1048: } |
| 548 | 5, 8, // 1052: case 0x5: { |
| 549 | OPC_CheckField, 4, 1, 1, // 1054: check Inst[4] == 0x1 |
| 550 | OPC_Decode, 146, 4, 16, // 1058: decode to ARMSLL_W using decoder 16 |
| 551 | // 1058: } |
| 552 | 6, 8, // 1062: case 0x6: { |
| 553 | OPC_CheckField, 4, 1, 1, // 1064: check Inst[4] == 0x1 |
| 554 | OPC_Decode, 150, 4, 16, // 1068: decode to ARMSRL_W using decoder 16 |
| 555 | // 1068: } |
| 556 | 7, 0, // 1072: case 0x7: { |
| 557 | OPC_CheckField, 4, 1, 1, // 1074: check Inst[4] == 0x1 |
| 558 | OPC_Decode, 148, 4, 16, // 1078: decode to ARMSRA_W using decoder 16 |
| 559 | // 1078: } |
| 560 | // 1078: } // switch Inst[17:15] |
| 561 | // 1078: } |
| 562 | 15, 0, // 1082: case 0xf: { |
| 563 | OPC_SwitchField, 15, 3, // 1084: switch Inst[17:15] { |
| 564 | 0, 8, // 1087: case 0x0: { |
| 565 | OPC_CheckField, 4, 1, 1, // 1089: check Inst[4] == 0x1 |
| 566 | OPC_Decode, 142, 4, 16, // 1093: decode to ARMROTR_W using decoder 16 |
| 567 | // 1093: } |
| 568 | 1, 8, // 1097: case 0x1: { |
| 569 | OPC_CheckField, 4, 1, 1, // 1099: check Inst[4] == 0x1 |
| 570 | OPC_Decode, 145, 4, 17, // 1103: decode to ARMSLLI_W using decoder 17 |
| 571 | // 1103: } |
| 572 | 2, 8, // 1107: case 0x2: { |
| 573 | OPC_CheckField, 4, 1, 1, // 1109: check Inst[4] == 0x1 |
| 574 | OPC_Decode, 149, 4, 17, // 1113: decode to ARMSRLI_W using decoder 17 |
| 575 | // 1113: } |
| 576 | 3, 8, // 1117: case 0x3: { |
| 577 | OPC_CheckField, 4, 1, 1, // 1119: check Inst[4] == 0x1 |
| 578 | OPC_Decode, 147, 4, 17, // 1123: decode to ARMSRAI_W using decoder 17 |
| 579 | // 1123: } |
| 580 | 4, 8, // 1127: case 0x4: { |
| 581 | OPC_CheckField, 4, 1, 1, // 1129: check Inst[4] == 0x1 |
| 582 | OPC_Decode, 141, 4, 17, // 1133: decode to ARMROTRI_W using decoder 17 |
| 583 | // 1133: } |
| 584 | 5, 57, // 1137: case 0x5: { |
| 585 | OPC_SwitchField, 0, 5, // 1139: switch Inst[4:0] { |
| 586 | 0, 4, // 1142: case 0x0: { |
| 587 | OPC_Decode, 138, 13, 7, // 1144: decode to X86MUL_B using decoder 7 |
| 588 | // 1144: } |
| 589 | 1, 4, // 1148: case 0x1: { |
| 590 | OPC_Decode, 142, 13, 7, // 1150: decode to X86MUL_H using decoder 7 |
| 591 | // 1150: } |
| 592 | 2, 4, // 1154: case 0x2: { |
| 593 | OPC_Decode, 144, 13, 7, // 1156: decode to X86MUL_W using decoder 7 |
| 594 | // 1156: } |
| 595 | 3, 6, // 1160: case 0x3: { |
| 596 | OPC_CheckPredicate, 0, // 1162: check predicate 0 |
| 597 | OPC_Decode, 140, 13, 7, // 1164: decode to X86MUL_D using decoder 7 |
| 598 | // 1164: } |
| 599 | 4, 4, // 1168: case 0x4: { |
| 600 | OPC_Decode, 139, 13, 7, // 1170: decode to X86MUL_BU using decoder 7 |
| 601 | // 1170: } |
| 602 | 5, 4, // 1174: case 0x5: { |
| 603 | OPC_Decode, 143, 13, 7, // 1176: decode to X86MUL_HU using decoder 7 |
| 604 | // 1176: } |
| 605 | 6, 6, // 1180: case 0x6: { |
| 606 | OPC_CheckPredicate, 0, // 1182: check predicate 0 |
| 607 | OPC_Decode, 145, 13, 7, // 1184: decode to X86MUL_WU using decoder 7 |
| 608 | // 1184: } |
| 609 | 7, 0, // 1188: case 0x7: { |
| 610 | OPC_CheckPredicate, 0, // 1190: check predicate 0 |
| 611 | OPC_Decode, 141, 13, 7, // 1192: decode to X86MUL_DU using decoder 7 |
| 612 | // 1192: } |
| 613 | // 1192: } // switch Inst[4:0] |
| 614 | // 1192: } |
| 615 | 6, 217, 1, // 1196: case 0x6: { |
| 616 | OPC_SwitchField, 0, 5, // 1199: switch Inst[4:0] { |
| 617 | 0, 6, // 1202: case 0x0: { |
| 618 | OPC_CheckPredicate, 0, // 1204: check predicate 0 |
| 619 | OPC_Decode, 246, 12, 7, // 1206: decode to X86ADD_WU using decoder 7 |
| 620 | // 1206: } |
| 621 | 1, 6, // 1210: case 0x1: { |
| 622 | OPC_CheckPredicate, 0, // 1212: check predicate 0 |
| 623 | OPC_Decode, 243, 12, 7, // 1214: decode to X86ADD_DU using decoder 7 |
| 624 | // 1214: } |
| 625 | 2, 6, // 1218: case 0x2: { |
| 626 | OPC_CheckPredicate, 0, // 1220: check predicate 0 |
| 627 | OPC_Decode, 217, 13, 7, // 1222: decode to X86SUB_WU using decoder 7 |
| 628 | // 1222: } |
| 629 | 3, 6, // 1226: case 0x3: { |
| 630 | OPC_CheckPredicate, 0, // 1228: check predicate 0 |
| 631 | OPC_Decode, 214, 13, 7, // 1230: decode to X86SUB_DU using decoder 7 |
| 632 | // 1230: } |
| 633 | 4, 4, // 1234: case 0x4: { |
| 634 | OPC_Decode, 241, 12, 7, // 1236: decode to X86ADD_B using decoder 7 |
| 635 | // 1236: } |
| 636 | 5, 4, // 1240: case 0x5: { |
| 637 | OPC_Decode, 244, 12, 7, // 1242: decode to X86ADD_H using decoder 7 |
| 638 | // 1242: } |
| 639 | 6, 4, // 1246: case 0x6: { |
| 640 | OPC_Decode, 245, 12, 7, // 1248: decode to X86ADD_W using decoder 7 |
| 641 | // 1248: } |
| 642 | 7, 6, // 1252: case 0x7: { |
| 643 | OPC_CheckPredicate, 0, // 1254: check predicate 0 |
| 644 | OPC_Decode, 242, 12, 7, // 1256: decode to X86ADD_D using decoder 7 |
| 645 | // 1256: } |
| 646 | 8, 4, // 1260: case 0x8: { |
| 647 | OPC_Decode, 212, 13, 7, // 1262: decode to X86SUB_B using decoder 7 |
| 648 | // 1262: } |
| 649 | 9, 4, // 1266: case 0x9: { |
| 650 | OPC_Decode, 215, 13, 7, // 1268: decode to X86SUB_H using decoder 7 |
| 651 | // 1268: } |
| 652 | 10, 4, // 1272: case 0xa: { |
| 653 | OPC_Decode, 216, 13, 7, // 1274: decode to X86SUB_W using decoder 7 |
| 654 | // 1274: } |
| 655 | 11, 6, // 1278: case 0xb: { |
| 656 | OPC_CheckPredicate, 0, // 1280: check predicate 0 |
| 657 | OPC_Decode, 213, 13, 7, // 1282: decode to X86SUB_D using decoder 7 |
| 658 | // 1282: } |
| 659 | 12, 4, // 1286: case 0xc: { |
| 660 | OPC_Decode, 237, 12, 7, // 1288: decode to X86ADC_B using decoder 7 |
| 661 | // 1288: } |
| 662 | 13, 4, // 1292: case 0xd: { |
| 663 | OPC_Decode, 239, 12, 7, // 1294: decode to X86ADC_H using decoder 7 |
| 664 | // 1294: } |
| 665 | 14, 4, // 1298: case 0xe: { |
| 666 | OPC_Decode, 240, 12, 7, // 1300: decode to X86ADC_W using decoder 7 |
| 667 | // 1300: } |
| 668 | 15, 6, // 1304: case 0xf: { |
| 669 | OPC_CheckPredicate, 0, // 1306: check predicate 0 |
| 670 | OPC_Decode, 238, 12, 7, // 1308: decode to X86ADC_D using decoder 7 |
| 671 | // 1308: } |
| 672 | 16, 4, // 1312: case 0x10: { |
| 673 | OPC_Decode, 182, 13, 7, // 1314: decode to X86SBC_B using decoder 7 |
| 674 | // 1314: } |
| 675 | 17, 4, // 1318: case 0x11: { |
| 676 | OPC_Decode, 184, 13, 7, // 1320: decode to X86SBC_H using decoder 7 |
| 677 | // 1320: } |
| 678 | 18, 4, // 1324: case 0x12: { |
| 679 | OPC_Decode, 185, 13, 7, // 1326: decode to X86SBC_W using decoder 7 |
| 680 | // 1326: } |
| 681 | 19, 6, // 1330: case 0x13: { |
| 682 | OPC_CheckPredicate, 0, // 1332: check predicate 0 |
| 683 | OPC_Decode, 183, 13, 7, // 1334: decode to X86SBC_D using decoder 7 |
| 684 | // 1334: } |
| 685 | 20, 4, // 1338: case 0x14: { |
| 686 | OPC_Decode, 192, 13, 7, // 1340: decode to X86SLL_B using decoder 7 |
| 687 | // 1340: } |
| 688 | 21, 4, // 1344: case 0x15: { |
| 689 | OPC_Decode, 194, 13, 7, // 1346: decode to X86SLL_H using decoder 7 |
| 690 | // 1346: } |
| 691 | 22, 4, // 1350: case 0x16: { |
| 692 | OPC_Decode, 195, 13, 7, // 1352: decode to X86SLL_W using decoder 7 |
| 693 | // 1352: } |
| 694 | 23, 6, // 1356: case 0x17: { |
| 695 | OPC_CheckPredicate, 0, // 1358: check predicate 0 |
| 696 | OPC_Decode, 193, 13, 7, // 1360: decode to X86SLL_D using decoder 7 |
| 697 | // 1360: } |
| 698 | 24, 4, // 1364: case 0x18: { |
| 699 | OPC_Decode, 208, 13, 7, // 1366: decode to X86SRL_B using decoder 7 |
| 700 | // 1366: } |
| 701 | 25, 4, // 1370: case 0x19: { |
| 702 | OPC_Decode, 210, 13, 7, // 1372: decode to X86SRL_H using decoder 7 |
| 703 | // 1372: } |
| 704 | 26, 4, // 1376: case 0x1a: { |
| 705 | OPC_Decode, 211, 13, 7, // 1378: decode to X86SRL_W using decoder 7 |
| 706 | // 1378: } |
| 707 | 27, 6, // 1382: case 0x1b: { |
| 708 | OPC_CheckPredicate, 0, // 1384: check predicate 0 |
| 709 | OPC_Decode, 209, 13, 7, // 1386: decode to X86SRL_D using decoder 7 |
| 710 | // 1386: } |
| 711 | 28, 4, // 1390: case 0x1c: { |
| 712 | OPC_Decode, 200, 13, 7, // 1392: decode to X86SRA_B using decoder 7 |
| 713 | // 1392: } |
| 714 | 29, 4, // 1396: case 0x1d: { |
| 715 | OPC_Decode, 202, 13, 7, // 1398: decode to X86SRA_H using decoder 7 |
| 716 | // 1398: } |
| 717 | 30, 4, // 1402: case 0x1e: { |
| 718 | OPC_Decode, 203, 13, 7, // 1404: decode to X86SRA_W using decoder 7 |
| 719 | // 1404: } |
| 720 | 31, 0, // 1408: case 0x1f: { |
| 721 | OPC_CheckPredicate, 0, // 1410: check predicate 0 |
| 722 | OPC_Decode, 201, 13, 7, // 1412: decode to X86SRA_D using decoder 7 |
| 723 | // 1412: } |
| 724 | // 1412: } // switch Inst[4:0] |
| 725 | // 1412: } |
| 726 | 7, 0, // 1416: case 0x7: { |
| 727 | OPC_SwitchField, 0, 5, // 1418: switch Inst[4:0] { |
| 728 | 0, 4, // 1421: case 0x0: { |
| 729 | OPC_Decode, 178, 13, 7, // 1423: decode to X86ROTR_B using decoder 7 |
| 730 | // 1423: } |
| 731 | 1, 4, // 1427: case 0x1: { |
| 732 | OPC_Decode, 180, 13, 7, // 1429: decode to X86ROTR_H using decoder 7 |
| 733 | // 1429: } |
| 734 | 2, 6, // 1433: case 0x2: { |
| 735 | OPC_CheckPredicate, 0, // 1435: check predicate 0 |
| 736 | OPC_Decode, 179, 13, 7, // 1437: decode to X86ROTR_D using decoder 7 |
| 737 | // 1437: } |
| 738 | 3, 4, // 1441: case 0x3: { |
| 739 | OPC_Decode, 181, 13, 7, // 1443: decode to X86ROTR_W using decoder 7 |
| 740 | // 1443: } |
| 741 | 4, 4, // 1447: case 0x4: { |
| 742 | OPC_Decode, 170, 13, 7, // 1449: decode to X86ROTL_B using decoder 7 |
| 743 | // 1449: } |
| 744 | 5, 4, // 1453: case 0x5: { |
| 745 | OPC_Decode, 172, 13, 7, // 1455: decode to X86ROTL_H using decoder 7 |
| 746 | // 1455: } |
| 747 | 6, 4, // 1459: case 0x6: { |
| 748 | OPC_Decode, 173, 13, 7, // 1461: decode to X86ROTL_W using decoder 7 |
| 749 | // 1461: } |
| 750 | 7, 6, // 1465: case 0x7: { |
| 751 | OPC_CheckPredicate, 0, // 1467: check predicate 0 |
| 752 | OPC_Decode, 171, 13, 7, // 1469: decode to X86ROTL_D using decoder 7 |
| 753 | // 1469: } |
| 754 | 8, 4, // 1473: case 0x8: { |
| 755 | OPC_Decode, 162, 13, 7, // 1475: decode to X86RCR_B using decoder 7 |
| 756 | // 1475: } |
| 757 | 9, 4, // 1479: case 0x9: { |
| 758 | OPC_Decode, 164, 13, 7, // 1481: decode to X86RCR_H using decoder 7 |
| 759 | // 1481: } |
| 760 | 10, 4, // 1485: case 0xa: { |
| 761 | OPC_Decode, 165, 13, 7, // 1487: decode to X86RCR_W using decoder 7 |
| 762 | // 1487: } |
| 763 | 11, 6, // 1491: case 0xb: { |
| 764 | OPC_CheckPredicate, 0, // 1493: check predicate 0 |
| 765 | OPC_Decode, 163, 13, 7, // 1495: decode to X86RCR_D using decoder 7 |
| 766 | // 1495: } |
| 767 | 12, 4, // 1499: case 0xc: { |
| 768 | OPC_Decode, 154, 13, 7, // 1501: decode to X86RCL_B using decoder 7 |
| 769 | // 1501: } |
| 770 | 13, 4, // 1505: case 0xd: { |
| 771 | OPC_Decode, 156, 13, 7, // 1507: decode to X86RCL_H using decoder 7 |
| 772 | // 1507: } |
| 773 | 14, 4, // 1511: case 0xe: { |
| 774 | OPC_Decode, 157, 13, 7, // 1513: decode to X86RCL_W using decoder 7 |
| 775 | // 1513: } |
| 776 | 15, 6, // 1517: case 0xf: { |
| 777 | OPC_CheckPredicate, 0, // 1519: check predicate 0 |
| 778 | OPC_Decode, 155, 13, 7, // 1521: decode to X86RCL_D using decoder 7 |
| 779 | // 1521: } |
| 780 | 16, 4, // 1525: case 0x10: { |
| 781 | OPC_Decode, 247, 12, 7, // 1527: decode to X86AND_B using decoder 7 |
| 782 | // 1527: } |
| 783 | 17, 4, // 1531: case 0x11: { |
| 784 | OPC_Decode, 249, 12, 7, // 1533: decode to X86AND_H using decoder 7 |
| 785 | // 1533: } |
| 786 | 18, 4, // 1537: case 0x12: { |
| 787 | OPC_Decode, 250, 12, 7, // 1539: decode to X86AND_W using decoder 7 |
| 788 | // 1539: } |
| 789 | 19, 6, // 1543: case 0x13: { |
| 790 | OPC_CheckPredicate, 0, // 1545: check predicate 0 |
| 791 | OPC_Decode, 248, 12, 7, // 1547: decode to X86AND_D using decoder 7 |
| 792 | // 1547: } |
| 793 | 20, 4, // 1551: case 0x14: { |
| 794 | OPC_Decode, 146, 13, 7, // 1553: decode to X86OR_B using decoder 7 |
| 795 | // 1553: } |
| 796 | 21, 4, // 1557: case 0x15: { |
| 797 | OPC_Decode, 148, 13, 7, // 1559: decode to X86OR_H using decoder 7 |
| 798 | // 1559: } |
| 799 | 22, 4, // 1563: case 0x16: { |
| 800 | OPC_Decode, 149, 13, 7, // 1565: decode to X86OR_W using decoder 7 |
| 801 | // 1565: } |
| 802 | 23, 6, // 1569: case 0x17: { |
| 803 | OPC_CheckPredicate, 0, // 1571: check predicate 0 |
| 804 | OPC_Decode, 147, 13, 7, // 1573: decode to X86OR_D using decoder 7 |
| 805 | // 1573: } |
| 806 | 24, 4, // 1577: case 0x18: { |
| 807 | OPC_Decode, 218, 13, 7, // 1579: decode to X86XOR_B using decoder 7 |
| 808 | // 1579: } |
| 809 | 25, 4, // 1583: case 0x19: { |
| 810 | OPC_Decode, 220, 13, 7, // 1585: decode to X86XOR_H using decoder 7 |
| 811 | // 1585: } |
| 812 | 26, 4, // 1589: case 0x1a: { |
| 813 | OPC_Decode, 221, 13, 7, // 1591: decode to X86XOR_W using decoder 7 |
| 814 | // 1591: } |
| 815 | 27, 6, // 1595: case 0x1b: { |
| 816 | OPC_CheckPredicate, 0, // 1597: check predicate 0 |
| 817 | OPC_Decode, 219, 13, 7, // 1599: decode to X86XOR_D using decoder 7 |
| 818 | // 1599: } |
| 819 | 28, 8, // 1603: case 0x1c: { |
| 820 | OPC_CheckField, 14, 1, 1, // 1605: check Inst[14] == 0x1 |
| 821 | OPC_Decode, 139, 4, 18, // 1609: decode to ARMNOT_W using decoder 18 |
| 822 | // 1609: } |
| 823 | 29, 8, // 1613: case 0x1d: { |
| 824 | OPC_CheckField, 14, 1, 1, // 1615: check Inst[14] == 0x1 |
| 825 | OPC_Decode, 137, 4, 18, // 1619: decode to ARMMOV_W using decoder 18 |
| 826 | // 1619: } |
| 827 | 30, 10, // 1623: case 0x1e: { |
| 828 | OPC_CheckPredicate, 0, // 1625: check predicate 0 |
| 829 | OPC_CheckField, 14, 1, 1, // 1627: check Inst[14] == 0x1 |
| 830 | OPC_Decode, 136, 4, 18, // 1631: decode to ARMMOV_D using decoder 18 |
| 831 | // 1631: } |
| 832 | 31, 0, // 1635: case 0x1f: { |
| 833 | OPC_CheckField, 14, 1, 1, // 1637: check Inst[14] == 0x1 |
| 834 | OPC_Decode, 143, 4, 18, // 1641: decode to ARMRRX_W using decoder 18 |
| 835 | // 1641: } |
| 836 | // 1641: } // switch Inst[4:0] |
| 837 | // 1641: } |
| 838 | // 1641: } // switch Inst[17:15] |
| 839 | // 1641: } |
| 840 | // 1641: } // switch Inst[21:18] |
| 841 | // 1641: } |
| 842 | 1, 136, 4, // 1645: case 0x1: { |
| 843 | OPC_SwitchField, 21, 1, // 1648: switch Inst[21] { |
| 844 | 0, 241, 3, // 1651: case 0x0: { |
| 845 | OPC_SwitchField, 18, 3, // 1654: switch Inst[20:18] { |
| 846 | 0, 21, // 1657: case 0x0: { |
| 847 | OPC_SwitchField, 16, 2, // 1659: switch Inst[17:16] { |
| 848 | 0, 8, // 1662: case 0x0: { |
| 849 | OPC_CheckField, 15, 1, 1, // 1664: check Inst[15] == 0x1 |
| 850 | OPC_Decode, 230, 6, 19, // 1668: decode to SLLI_W using decoder 19 |
| 851 | // 1668: } |
| 852 | 1, 0, // 1672: case 0x1: { |
| 853 | OPC_CheckPredicate, 0, // 1674: check predicate 0 |
| 854 | OPC_Decode, 229, 6, 20, // 1676: decode to SLLI_D using decoder 20 |
| 855 | // 1676: } |
| 856 | // 1676: } // switch Inst[17:16] |
| 857 | // 1676: } |
| 858 | 1, 21, // 1680: case 0x1: { |
| 859 | OPC_SwitchField, 16, 2, // 1682: switch Inst[17:16] { |
| 860 | 0, 8, // 1685: case 0x0: { |
| 861 | OPC_CheckField, 15, 1, 1, // 1687: check Inst[15] == 0x1 |
| 862 | OPC_Decode, 242, 6, 19, // 1691: decode to SRLI_W using decoder 19 |
| 863 | // 1691: } |
| 864 | 1, 0, // 1695: case 0x1: { |
| 865 | OPC_CheckPredicate, 0, // 1697: check predicate 0 |
| 866 | OPC_Decode, 241, 6, 20, // 1699: decode to SRLI_D using decoder 20 |
| 867 | // 1699: } |
| 868 | // 1699: } // switch Inst[17:16] |
| 869 | // 1699: } |
| 870 | 2, 21, // 1703: case 0x2: { |
| 871 | OPC_SwitchField, 16, 2, // 1705: switch Inst[17:16] { |
| 872 | 0, 8, // 1708: case 0x0: { |
| 873 | OPC_CheckField, 15, 1, 1, // 1710: check Inst[15] == 0x1 |
| 874 | OPC_Decode, 238, 6, 19, // 1714: decode to SRAI_W using decoder 19 |
| 875 | // 1714: } |
| 876 | 1, 0, // 1718: case 0x1: { |
| 877 | OPC_CheckPredicate, 0, // 1720: check predicate 0 |
| 878 | OPC_Decode, 237, 6, 20, // 1722: decode to SRAI_D using decoder 20 |
| 879 | // 1722: } |
| 880 | // 1722: } // switch Inst[17:16] |
| 881 | // 1722: } |
| 882 | 3, 43, // 1726: case 0x3: { |
| 883 | OPC_SwitchField, 16, 2, // 1728: switch Inst[17:16] { |
| 884 | 0, 30, // 1731: case 0x0: { |
| 885 | OPC_SwitchField, 15, 1, // 1733: switch Inst[15] { |
| 886 | 0, 19, // 1736: case 0x0: { |
| 887 | OPC_SwitchField, 14, 1, // 1738: switch Inst[14] { |
| 888 | 0, 8, // 1741: case 0x0: { |
| 889 | OPC_CheckField, 13, 1, 1, // 1743: check Inst[13] == 0x1 |
| 890 | OPC_Decode, 206, 6, 21, // 1747: decode to ROTRI_B using decoder 21 |
| 891 | // 1747: } |
| 892 | 1, 0, // 1751: case 0x1: { |
| 893 | OPC_Decode, 208, 6, 14, // 1753: decode to ROTRI_H using decoder 14 |
| 894 | // 1753: } |
| 895 | // 1753: } // switch Inst[14] |
| 896 | // 1753: } |
| 897 | 1, 0, // 1757: case 0x1: { |
| 898 | OPC_Decode, 209, 6, 19, // 1759: decode to ROTRI_W using decoder 19 |
| 899 | // 1759: } |
| 900 | // 1759: } // switch Inst[15] |
| 901 | // 1759: } |
| 902 | 1, 0, // 1763: case 0x1: { |
| 903 | OPC_CheckPredicate, 0, // 1765: check predicate 0 |
| 904 | OPC_Decode, 207, 6, 20, // 1767: decode to ROTRI_D using decoder 20 |
| 905 | // 1767: } |
| 906 | // 1767: } // switch Inst[17:16] |
| 907 | // 1767: } |
| 908 | 4, 43, // 1771: case 0x4: { |
| 909 | OPC_SwitchField, 16, 2, // 1773: switch Inst[17:16] { |
| 910 | 0, 30, // 1776: case 0x0: { |
| 911 | OPC_SwitchField, 15, 1, // 1778: switch Inst[15] { |
| 912 | 0, 19, // 1781: case 0x0: { |
| 913 | OPC_SwitchField, 14, 1, // 1783: switch Inst[14] { |
| 914 | 0, 8, // 1786: case 0x0: { |
| 915 | OPC_CheckField, 13, 1, 1, // 1788: check Inst[13] == 0x1 |
| 916 | OPC_Decode, 189, 6, 21, // 1792: decode to RCRI_B using decoder 21 |
| 917 | // 1792: } |
| 918 | 1, 0, // 1796: case 0x1: { |
| 919 | OPC_Decode, 191, 6, 14, // 1798: decode to RCRI_H using decoder 14 |
| 920 | // 1798: } |
| 921 | // 1798: } // switch Inst[14] |
| 922 | // 1798: } |
| 923 | 1, 0, // 1802: case 0x1: { |
| 924 | OPC_Decode, 192, 6, 19, // 1804: decode to RCRI_W using decoder 19 |
| 925 | // 1804: } |
| 926 | // 1804: } // switch Inst[15] |
| 927 | // 1804: } |
| 928 | 1, 0, // 1808: case 0x1: { |
| 929 | OPC_CheckPredicate, 0, // 1810: check predicate 0 |
| 930 | OPC_Decode, 190, 6, 20, // 1812: decode to RCRI_D using decoder 20 |
| 931 | // 1812: } |
| 932 | // 1812: } // switch Inst[17:16] |
| 933 | // 1812: } |
| 934 | 5, 169, 2, // 1816: case 0x5: { |
| 935 | OPC_SwitchField, 0, 5, // 1819: switch Inst[4:0] { |
| 936 | 0, 8, // 1822: case 0x0: { |
| 937 | OPC_CheckField, 13, 5, 1, // 1824: check Inst[17:13] == 0x1 |
| 938 | OPC_Decode, 188, 13, 22, // 1828: decode to X86SLLI_B using decoder 22 |
| 939 | // 1828: } |
| 940 | 1, 8, // 1832: case 0x1: { |
| 941 | OPC_CheckField, 14, 4, 1, // 1834: check Inst[17:14] == 0x1 |
| 942 | OPC_Decode, 190, 13, 18, // 1838: decode to X86SLLI_H using decoder 18 |
| 943 | // 1838: } |
| 944 | 2, 8, // 1842: case 0x2: { |
| 945 | OPC_CheckField, 15, 3, 1, // 1844: check Inst[17:15] == 0x1 |
| 946 | OPC_Decode, 191, 13, 23, // 1848: decode to X86SLLI_W using decoder 23 |
| 947 | // 1848: } |
| 948 | 3, 10, // 1852: case 0x3: { |
| 949 | OPC_CheckPredicate, 0, // 1854: check predicate 0 |
| 950 | OPC_CheckField, 16, 2, 1, // 1856: check Inst[17:16] == 0x1 |
| 951 | OPC_Decode, 189, 13, 24, // 1860: decode to X86SLLI_D using decoder 24 |
| 952 | // 1860: } |
| 953 | 4, 8, // 1864: case 0x4: { |
| 954 | OPC_CheckField, 13, 5, 1, // 1866: check Inst[17:13] == 0x1 |
| 955 | OPC_Decode, 204, 13, 22, // 1870: decode to X86SRLI_B using decoder 22 |
| 956 | // 1870: } |
| 957 | 5, 8, // 1874: case 0x5: { |
| 958 | OPC_CheckField, 14, 4, 1, // 1876: check Inst[17:14] == 0x1 |
| 959 | OPC_Decode, 206, 13, 18, // 1880: decode to X86SRLI_H using decoder 18 |
| 960 | // 1880: } |
| 961 | 6, 8, // 1884: case 0x6: { |
| 962 | OPC_CheckField, 15, 3, 1, // 1886: check Inst[17:15] == 0x1 |
| 963 | OPC_Decode, 207, 13, 23, // 1890: decode to X86SRLI_W using decoder 23 |
| 964 | // 1890: } |
| 965 | 7, 10, // 1894: case 0x7: { |
| 966 | OPC_CheckPredicate, 0, // 1896: check predicate 0 |
| 967 | OPC_CheckField, 16, 2, 1, // 1898: check Inst[17:16] == 0x1 |
| 968 | OPC_Decode, 205, 13, 24, // 1902: decode to X86SRLI_D using decoder 24 |
| 969 | // 1902: } |
| 970 | 8, 8, // 1906: case 0x8: { |
| 971 | OPC_CheckField, 13, 5, 1, // 1908: check Inst[17:13] == 0x1 |
| 972 | OPC_Decode, 196, 13, 22, // 1912: decode to X86SRAI_B using decoder 22 |
| 973 | // 1912: } |
| 974 | 9, 8, // 1916: case 0x9: { |
| 975 | OPC_CheckField, 14, 4, 1, // 1918: check Inst[17:14] == 0x1 |
| 976 | OPC_Decode, 198, 13, 18, // 1922: decode to X86SRAI_H using decoder 18 |
| 977 | // 1922: } |
| 978 | 10, 8, // 1926: case 0xa: { |
| 979 | OPC_CheckField, 15, 3, 1, // 1928: check Inst[17:15] == 0x1 |
| 980 | OPC_Decode, 199, 13, 23, // 1932: decode to X86SRAI_W using decoder 23 |
| 981 | // 1932: } |
| 982 | 11, 10, // 1936: case 0xb: { |
| 983 | OPC_CheckPredicate, 0, // 1938: check predicate 0 |
| 984 | OPC_CheckField, 16, 2, 1, // 1940: check Inst[17:16] == 0x1 |
| 985 | OPC_Decode, 197, 13, 24, // 1944: decode to X86SRAI_D using decoder 24 |
| 986 | // 1944: } |
| 987 | 12, 8, // 1948: case 0xc: { |
| 988 | OPC_CheckField, 13, 5, 1, // 1950: check Inst[17:13] == 0x1 |
| 989 | OPC_Decode, 174, 13, 22, // 1954: decode to X86ROTRI_B using decoder 22 |
| 990 | // 1954: } |
| 991 | 13, 8, // 1958: case 0xd: { |
| 992 | OPC_CheckField, 14, 4, 1, // 1960: check Inst[17:14] == 0x1 |
| 993 | OPC_Decode, 176, 13, 18, // 1964: decode to X86ROTRI_H using decoder 18 |
| 994 | // 1964: } |
| 995 | 14, 8, // 1968: case 0xe: { |
| 996 | OPC_CheckField, 15, 3, 1, // 1970: check Inst[17:15] == 0x1 |
| 997 | OPC_Decode, 177, 13, 23, // 1974: decode to X86ROTRI_W using decoder 23 |
| 998 | // 1974: } |
| 999 | 15, 10, // 1978: case 0xf: { |
| 1000 | OPC_CheckPredicate, 0, // 1980: check predicate 0 |
| 1001 | OPC_CheckField, 16, 2, 1, // 1982: check Inst[17:16] == 0x1 |
| 1002 | OPC_Decode, 175, 13, 24, // 1986: decode to X86ROTRI_D using decoder 24 |
| 1003 | // 1986: } |
| 1004 | 16, 8, // 1990: case 0x10: { |
| 1005 | OPC_CheckField, 13, 5, 1, // 1992: check Inst[17:13] == 0x1 |
| 1006 | OPC_Decode, 158, 13, 22, // 1996: decode to X86RCRI_B using decoder 22 |
| 1007 | // 1996: } |
| 1008 | 17, 8, // 2000: case 0x11: { |
| 1009 | OPC_CheckField, 14, 4, 1, // 2002: check Inst[17:14] == 0x1 |
| 1010 | OPC_Decode, 160, 13, 18, // 2006: decode to X86RCRI_H using decoder 18 |
| 1011 | // 2006: } |
| 1012 | 18, 8, // 2010: case 0x12: { |
| 1013 | OPC_CheckField, 15, 3, 1, // 2012: check Inst[17:15] == 0x1 |
| 1014 | OPC_Decode, 161, 13, 23, // 2016: decode to X86RCRI_W using decoder 23 |
| 1015 | // 2016: } |
| 1016 | 19, 10, // 2020: case 0x13: { |
| 1017 | OPC_CheckPredicate, 0, // 2022: check predicate 0 |
| 1018 | OPC_CheckField, 16, 2, 1, // 2024: check Inst[17:16] == 0x1 |
| 1019 | OPC_Decode, 159, 13, 24, // 2028: decode to X86RCRI_D using decoder 24 |
| 1020 | // 2028: } |
| 1021 | 20, 8, // 2032: case 0x14: { |
| 1022 | OPC_CheckField, 13, 5, 1, // 2034: check Inst[17:13] == 0x1 |
| 1023 | OPC_Decode, 166, 13, 22, // 2038: decode to X86ROTLI_B using decoder 22 |
| 1024 | // 2038: } |
| 1025 | 21, 8, // 2042: case 0x15: { |
| 1026 | OPC_CheckField, 14, 4, 1, // 2044: check Inst[17:14] == 0x1 |
| 1027 | OPC_Decode, 168, 13, 18, // 2048: decode to X86ROTLI_H using decoder 18 |
| 1028 | // 2048: } |
| 1029 | 22, 8, // 2052: case 0x16: { |
| 1030 | OPC_CheckField, 15, 3, 1, // 2054: check Inst[17:15] == 0x1 |
| 1031 | OPC_Decode, 169, 13, 23, // 2058: decode to X86ROTLI_W using decoder 23 |
| 1032 | // 2058: } |
| 1033 | 23, 10, // 2062: case 0x17: { |
| 1034 | OPC_CheckPredicate, 0, // 2064: check predicate 0 |
| 1035 | OPC_CheckField, 16, 2, 1, // 2066: check Inst[17:16] == 0x1 |
| 1036 | OPC_Decode, 167, 13, 24, // 2070: decode to X86ROTLI_D using decoder 24 |
| 1037 | // 2070: } |
| 1038 | 24, 8, // 2074: case 0x18: { |
| 1039 | OPC_CheckField, 13, 5, 1, // 2076: check Inst[17:13] == 0x1 |
| 1040 | OPC_Decode, 150, 13, 22, // 2080: decode to X86RCLI_B using decoder 22 |
| 1041 | // 2080: } |
| 1042 | 25, 8, // 2084: case 0x19: { |
| 1043 | OPC_CheckField, 14, 4, 1, // 2086: check Inst[17:14] == 0x1 |
| 1044 | OPC_Decode, 152, 13, 18, // 2090: decode to X86RCLI_H using decoder 18 |
| 1045 | // 2090: } |
| 1046 | 26, 8, // 2094: case 0x1a: { |
| 1047 | OPC_CheckField, 15, 3, 1, // 2096: check Inst[17:15] == 0x1 |
| 1048 | OPC_Decode, 153, 13, 23, // 2100: decode to X86RCLI_W using decoder 23 |
| 1049 | // 2100: } |
| 1050 | 27, 0, // 2104: case 0x1b: { |
| 1051 | OPC_CheckPredicate, 0, // 2106: check predicate 0 |
| 1052 | OPC_CheckField, 16, 2, 1, // 2108: check Inst[17:16] == 0x1 |
| 1053 | OPC_Decode, 151, 13, 24, // 2112: decode to X86RCLI_D using decoder 24 |
| 1054 | // 2112: } |
| 1055 | // 2112: } // switch Inst[4:0] |
| 1056 | // 2112: } |
| 1057 | 6, 4, // 2116: case 0x6: { |
| 1058 | OPC_Decode, 186, 13, 25, // 2118: decode to X86SETTAG using decoder 25 |
| 1059 | // 2118: } |
| 1060 | 7, 0, // 2122: case 0x7: { |
| 1061 | OPC_SwitchField, 5, 5, // 2124: switch Inst[9:5] { |
| 1062 | 0, 4, // 2127: case 0x0: { |
| 1063 | OPC_Decode, 134, 13, 26, // 2129: decode to X86MFFLAG using decoder 26 |
| 1064 | // 2129: } |
| 1065 | 1, 4, // 2133: case 0x1: { |
| 1066 | OPC_Decode, 136, 13, 26, // 2135: decode to X86MTFLAG using decoder 26 |
| 1067 | // 2135: } |
| 1068 | 2, 4, // 2139: case 0x2: { |
| 1069 | OPC_Decode, 134, 4, 26, // 2141: decode to ARMMFFLAG using decoder 26 |
| 1070 | // 2141: } |
| 1071 | 3, 0, // 2145: case 0x3: { |
| 1072 | OPC_Decode, 138, 4, 26, // 2147: decode to ARMMTFLAG using decoder 26 |
| 1073 | // 2147: } |
| 1074 | // 2147: } // switch Inst[9:5] |
| 1075 | // 2147: } |
| 1076 | // 2147: } // switch Inst[20:18] |
| 1077 | // 2147: } |
| 1078 | 1, 0, // 2151: case 0x1: { |
| 1079 | OPC_SwitchField, 15, 1, // 2153: switch Inst[15] { |
| 1080 | 0, 4, // 2156: case 0x0: { |
| 1081 | OPC_Decode, 173, 4, 27, // 2158: decode to BSTRINS_W using decoder 27 |
| 1082 | // 2158: } |
| 1083 | 1, 0, // 2162: case 0x1: { |
| 1084 | OPC_Decode, 175, 4, 28, // 2164: decode to BSTRPICK_W using decoder 28 |
| 1085 | // 2164: } |
| 1086 | // 2164: } // switch Inst[15] |
| 1087 | // 2164: } |
| 1088 | // 2164: } // switch Inst[21] |
| 1089 | // 2164: } |
| 1090 | 2, 6, // 2168: case 0x2: { |
| 1091 | OPC_CheckPredicate, 0, // 2170: check predicate 0 |
| 1092 | OPC_Decode, 172, 4, 29, // 2172: decode to BSTRINS_D using decoder 29 |
| 1093 | // 2172: } |
| 1094 | 3, 6, // 2176: case 0x3: { |
| 1095 | OPC_CheckPredicate, 0, // 2178: check predicate 0 |
| 1096 | OPC_Decode, 174, 4, 30, // 2180: decode to BSTRPICK_D using decoder 30 |
| 1097 | // 2180: } |
| 1098 | 4, 161, 4, // 2184: case 0x4: { |
| 1099 | OPC_SwitchField, 15, 7, // 2187: switch Inst[21:15] { |
| 1100 | 1, 4, // 2190: case 0x1: { |
| 1101 | OPC_Decode, 211, 4, 31, // 2192: decode to FADD_S using decoder 31 |
| 1102 | // 2192: } |
| 1103 | 2, 4, // 2196: case 0x2: { |
| 1104 | OPC_Decode, 210, 4, 32, // 2198: decode to FADD_D using decoder 32 |
| 1105 | // 2198: } |
| 1106 | 5, 4, // 2202: case 0x5: { |
| 1107 | OPC_Decode, 200, 5, 31, // 2204: decode to FSUB_S using decoder 31 |
| 1108 | // 2204: } |
| 1109 | 6, 4, // 2208: case 0x6: { |
| 1110 | OPC_Decode, 199, 5, 32, // 2210: decode to FSUB_D using decoder 32 |
| 1111 | // 2210: } |
| 1112 | 9, 4, // 2214: case 0x9: { |
| 1113 | OPC_Decode, 168, 5, 31, // 2216: decode to FMUL_S using decoder 31 |
| 1114 | // 2216: } |
| 1115 | 10, 4, // 2220: case 0xa: { |
| 1116 | OPC_Decode, 167, 5, 32, // 2222: decode to FMUL_D using decoder 32 |
| 1117 | // 2222: } |
| 1118 | 13, 4, // 2226: case 0xd: { |
| 1119 | OPC_Decode, 138, 5, 31, // 2228: decode to FDIV_S using decoder 31 |
| 1120 | // 2228: } |
| 1121 | 14, 4, // 2232: case 0xe: { |
| 1122 | OPC_Decode, 137, 5, 32, // 2234: decode to FDIV_D using decoder 32 |
| 1123 | // 2234: } |
| 1124 | 17, 4, // 2238: case 0x11: { |
| 1125 | OPC_Decode, 158, 5, 31, // 2240: decode to FMAX_S using decoder 31 |
| 1126 | // 2240: } |
| 1127 | 18, 4, // 2244: case 0x12: { |
| 1128 | OPC_Decode, 157, 5, 32, // 2246: decode to FMAX_D using decoder 32 |
| 1129 | // 2246: } |
| 1130 | 21, 4, // 2250: case 0x15: { |
| 1131 | OPC_Decode, 162, 5, 31, // 2252: decode to FMIN_S using decoder 31 |
| 1132 | // 2252: } |
| 1133 | 22, 4, // 2256: case 0x16: { |
| 1134 | OPC_Decode, 161, 5, 32, // 2258: decode to FMIN_D using decoder 32 |
| 1135 | // 2258: } |
| 1136 | 25, 4, // 2262: case 0x19: { |
| 1137 | OPC_Decode, 156, 5, 31, // 2264: decode to FMAXA_S using decoder 31 |
| 1138 | // 2264: } |
| 1139 | 26, 4, // 2268: case 0x1a: { |
| 1140 | OPC_Decode, 155, 5, 32, // 2270: decode to FMAXA_D using decoder 32 |
| 1141 | // 2270: } |
| 1142 | 29, 4, // 2274: case 0x1d: { |
| 1143 | OPC_Decode, 160, 5, 31, // 2276: decode to FMINA_S using decoder 31 |
| 1144 | // 2276: } |
| 1145 | 30, 4, // 2280: case 0x1e: { |
| 1146 | OPC_Decode, 159, 5, 32, // 2282: decode to FMINA_D using decoder 32 |
| 1147 | // 2282: } |
| 1148 | 33, 4, // 2286: case 0x21: { |
| 1149 | OPC_Decode, 186, 5, 31, // 2288: decode to FSCALEB_S using decoder 31 |
| 1150 | // 2288: } |
| 1151 | 34, 4, // 2292: case 0x22: { |
| 1152 | OPC_Decode, 185, 5, 32, // 2294: decode to FSCALEB_D using decoder 32 |
| 1153 | // 2294: } |
| 1154 | 37, 4, // 2298: case 0x25: { |
| 1155 | OPC_Decode, 131, 5, 31, // 2300: decode to FCOPYSIGN_S using decoder 31 |
| 1156 | // 2300: } |
| 1157 | 38, 4, // 2304: case 0x26: { |
| 1158 | OPC_Decode, 130, 5, 32, // 2306: decode to FCOPYSIGN_D using decoder 32 |
| 1159 | // 2306: } |
| 1160 | 40, 99, // 2310: case 0x28: { |
| 1161 | OPC_SwitchField, 10, 5, // 2312: switch Inst[14:10] { |
| 1162 | 1, 4, // 2315: case 0x1: { |
| 1163 | OPC_Decode, 209, 4, 33, // 2317: decode to FABS_S using decoder 33 |
| 1164 | // 2317: } |
| 1165 | 2, 4, // 2321: case 0x2: { |
| 1166 | OPC_Decode, 208, 4, 34, // 2323: decode to FABS_D using decoder 34 |
| 1167 | // 2323: } |
| 1168 | 5, 4, // 2327: case 0x5: { |
| 1169 | OPC_Decode, 170, 5, 33, // 2329: decode to FNEG_S using decoder 33 |
| 1170 | // 2329: } |
| 1171 | 6, 4, // 2333: case 0x6: { |
| 1172 | OPC_Decode, 169, 5, 34, // 2335: decode to FNEG_D using decoder 34 |
| 1173 | // 2335: } |
| 1174 | 9, 4, // 2339: case 0x9: { |
| 1175 | OPC_Decode, 152, 5, 33, // 2341: decode to FLOGB_S using decoder 33 |
| 1176 | // 2341: } |
| 1177 | 10, 4, // 2345: case 0xa: { |
| 1178 | OPC_Decode, 151, 5, 34, // 2347: decode to FLOGB_D using decoder 34 |
| 1179 | // 2347: } |
| 1180 | 13, 4, // 2351: case 0xd: { |
| 1181 | OPC_Decode, 213, 4, 33, // 2353: decode to FCLASS_S using decoder 33 |
| 1182 | // 2353: } |
| 1183 | 14, 4, // 2357: case 0xe: { |
| 1184 | OPC_Decode, 212, 4, 34, // 2359: decode to FCLASS_D using decoder 34 |
| 1185 | // 2359: } |
| 1186 | 17, 4, // 2363: case 0x11: { |
| 1187 | OPC_Decode, 190, 5, 33, // 2365: decode to FSQRT_S using decoder 33 |
| 1188 | // 2365: } |
| 1189 | 18, 4, // 2369: case 0x12: { |
| 1190 | OPC_Decode, 189, 5, 34, // 2371: decode to FSQRT_D using decoder 34 |
| 1191 | // 2371: } |
| 1192 | 21, 4, // 2375: case 0x15: { |
| 1193 | OPC_Decode, 178, 5, 33, // 2377: decode to FRECIP_S using decoder 33 |
| 1194 | // 2377: } |
| 1195 | 22, 4, // 2381: case 0x16: { |
| 1196 | OPC_Decode, 177, 5, 34, // 2383: decode to FRECIP_D using decoder 34 |
| 1197 | // 2383: } |
| 1198 | 25, 4, // 2387: case 0x19: { |
| 1199 | OPC_Decode, 184, 5, 33, // 2389: decode to FRSQRT_S using decoder 33 |
| 1200 | // 2389: } |
| 1201 | 26, 4, // 2393: case 0x1a: { |
| 1202 | OPC_Decode, 183, 5, 34, // 2395: decode to FRSQRT_D using decoder 34 |
| 1203 | // 2395: } |
| 1204 | 29, 4, // 2399: case 0x1d: { |
| 1205 | OPC_Decode, 176, 5, 33, // 2401: decode to FRECIPE_S using decoder 33 |
| 1206 | // 2401: } |
| 1207 | 30, 0, // 2405: case 0x1e: { |
| 1208 | OPC_Decode, 175, 5, 34, // 2407: decode to FRECIPE_D using decoder 34 |
| 1209 | // 2407: } |
| 1210 | // 2407: } // switch Inst[14:10] |
| 1211 | // 2407: } |
| 1212 | 41, 115, // 2411: case 0x29: { |
| 1213 | OPC_SwitchField, 10, 5, // 2413: switch Inst[14:10] { |
| 1214 | 1, 4, // 2416: case 0x1: { |
| 1215 | OPC_Decode, 182, 5, 33, // 2418: decode to FRSQRTE_S using decoder 33 |
| 1216 | // 2418: } |
| 1217 | 2, 4, // 2422: case 0x2: { |
| 1218 | OPC_Decode, 181, 5, 34, // 2424: decode to FRSQRTE_D using decoder 34 |
| 1219 | // 2424: } |
| 1220 | 5, 4, // 2428: case 0x5: { |
| 1221 | OPC_Decode, 164, 5, 33, // 2430: decode to FMOV_S using decoder 33 |
| 1222 | // 2430: } |
| 1223 | 6, 4, // 2434: case 0x6: { |
| 1224 | OPC_Decode, 163, 5, 34, // 2436: decode to FMOV_D using decoder 34 |
| 1225 | // 2436: } |
| 1226 | 9, 4, // 2440: case 0x9: { |
| 1227 | OPC_Decode, 167, 6, 35, // 2442: decode to MOVGR2FR_W using decoder 35 |
| 1228 | // 2442: } |
| 1229 | 10, 6, // 2446: case 0xa: { |
| 1230 | OPC_CheckPredicate, 0, // 2448: check predicate 0 |
| 1231 | OPC_Decode, 166, 6, 36, // 2450: decode to MOVGR2FR_D using decoder 36 |
| 1232 | // 2450: } |
| 1233 | 11, 4, // 2454: case 0xb: { |
| 1234 | OPC_Decode, 165, 6, 37, // 2456: decode to MOVGR2FRH_W using decoder 37 |
| 1235 | // 2456: } |
| 1236 | 13, 4, // 2460: case 0xd: { |
| 1237 | OPC_Decode, 160, 6, 38, // 2462: decode to MOVFR2GR_S using decoder 38 |
| 1238 | // 2462: } |
| 1239 | 14, 6, // 2466: case 0xe: { |
| 1240 | OPC_CheckPredicate, 0, // 2468: check predicate 0 |
| 1241 | OPC_Decode, 159, 6, 39, // 2470: decode to MOVFR2GR_D using decoder 39 |
| 1242 | // 2470: } |
| 1243 | 15, 4, // 2474: case 0xf: { |
| 1244 | OPC_Decode, 162, 6, 39, // 2476: decode to MOVFRH2GR_S using decoder 39 |
| 1245 | // 2476: } |
| 1246 | 16, 4, // 2480: case 0x10: { |
| 1247 | OPC_Decode, 164, 6, 40, // 2482: decode to MOVGR2FCSR using decoder 40 |
| 1248 | // 2482: } |
| 1249 | 18, 4, // 2486: case 0x12: { |
| 1250 | OPC_Decode, 157, 6, 41, // 2488: decode to MOVFCSR2GR using decoder 41 |
| 1251 | // 2488: } |
| 1252 | 20, 4, // 2492: case 0x14: { |
| 1253 | OPC_Decode, 158, 6, 42, // 2494: decode to MOVFR2CF_xS using decoder 42 |
| 1254 | // 2494: } |
| 1255 | 21, 4, // 2498: case 0x15: { |
| 1256 | OPC_Decode, 155, 6, 43, // 2500: decode to MOVCF2FR_xS using decoder 43 |
| 1257 | // 2500: } |
| 1258 | 22, 4, // 2504: case 0x16: { |
| 1259 | OPC_Decode, 163, 6, 44, // 2506: decode to MOVGR2CF using decoder 44 |
| 1260 | // 2506: } |
| 1261 | 23, 4, // 2510: case 0x17: { |
| 1262 | OPC_Decode, 156, 6, 45, // 2512: decode to MOVCF2GR using decoder 45 |
| 1263 | // 2512: } |
| 1264 | 24, 4, // 2516: case 0x18: { |
| 1265 | OPC_Decode, 134, 5, 33, // 2518: decode to FCVT_LD_D using decoder 33 |
| 1266 | // 2518: } |
| 1267 | 25, 0, // 2522: case 0x19: { |
| 1268 | OPC_Decode, 136, 5, 33, // 2524: decode to FCVT_UD_D using decoder 33 |
| 1269 | // 2524: } |
| 1270 | // 2524: } // switch Inst[14:10] |
| 1271 | // 2524: } |
| 1272 | 42, 4, // 2528: case 0x2a: { |
| 1273 | OPC_Decode, 132, 5, 31, // 2530: decode to FCVT_D_LD using decoder 31 |
| 1274 | // 2530: } |
| 1275 | 50, 15, // 2534: case 0x32: { |
| 1276 | OPC_SwitchField, 10, 5, // 2536: switch Inst[14:10] { |
| 1277 | 6, 4, // 2539: case 0x6: { |
| 1278 | OPC_Decode, 135, 5, 46, // 2541: decode to FCVT_S_D using decoder 46 |
| 1279 | // 2541: } |
| 1280 | 9, 0, // 2545: case 0x9: { |
| 1281 | OPC_Decode, 133, 5, 47, // 2547: decode to FCVT_D_S using decoder 47 |
| 1282 | // 2547: } |
| 1283 | // 2547: } // switch Inst[14:10] |
| 1284 | // 2547: } |
| 1285 | 52, 51, // 2551: case 0x34: { |
| 1286 | OPC_SwitchField, 10, 5, // 2553: switch Inst[14:10] { |
| 1287 | 1, 4, // 2556: case 0x1: { |
| 1288 | OPC_Decode, 204, 5, 33, // 2558: decode to FTINTRM_W_S using decoder 33 |
| 1289 | // 2558: } |
| 1290 | 2, 4, // 2562: case 0x2: { |
| 1291 | OPC_Decode, 203, 5, 46, // 2564: decode to FTINTRM_W_D using decoder 46 |
| 1292 | // 2564: } |
| 1293 | 9, 4, // 2568: case 0x9: { |
| 1294 | OPC_Decode, 202, 5, 47, // 2570: decode to FTINTRM_L_S using decoder 47 |
| 1295 | // 2570: } |
| 1296 | 10, 4, // 2574: case 0xa: { |
| 1297 | OPC_Decode, 201, 5, 34, // 2576: decode to FTINTRM_L_D using decoder 34 |
| 1298 | // 2576: } |
| 1299 | 17, 4, // 2580: case 0x11: { |
| 1300 | OPC_Decode, 212, 5, 33, // 2582: decode to FTINTRP_W_S using decoder 33 |
| 1301 | // 2582: } |
| 1302 | 18, 4, // 2586: case 0x12: { |
| 1303 | OPC_Decode, 211, 5, 46, // 2588: decode to FTINTRP_W_D using decoder 46 |
| 1304 | // 2588: } |
| 1305 | 25, 4, // 2592: case 0x19: { |
| 1306 | OPC_Decode, 210, 5, 47, // 2594: decode to FTINTRP_L_S using decoder 47 |
| 1307 | // 2594: } |
| 1308 | 26, 0, // 2598: case 0x1a: { |
| 1309 | OPC_Decode, 209, 5, 34, // 2600: decode to FTINTRP_L_D using decoder 34 |
| 1310 | // 2600: } |
| 1311 | // 2600: } // switch Inst[14:10] |
| 1312 | // 2600: } |
| 1313 | 53, 51, // 2604: case 0x35: { |
| 1314 | OPC_SwitchField, 10, 5, // 2606: switch Inst[14:10] { |
| 1315 | 1, 4, // 2609: case 0x1: { |
| 1316 | OPC_Decode, 216, 5, 33, // 2611: decode to FTINTRZ_W_S using decoder 33 |
| 1317 | // 2611: } |
| 1318 | 2, 4, // 2615: case 0x2: { |
| 1319 | OPC_Decode, 215, 5, 46, // 2617: decode to FTINTRZ_W_D using decoder 46 |
| 1320 | // 2617: } |
| 1321 | 9, 4, // 2621: case 0x9: { |
| 1322 | OPC_Decode, 214, 5, 47, // 2623: decode to FTINTRZ_L_S using decoder 47 |
| 1323 | // 2623: } |
| 1324 | 10, 4, // 2627: case 0xa: { |
| 1325 | OPC_Decode, 213, 5, 34, // 2629: decode to FTINTRZ_L_D using decoder 34 |
| 1326 | // 2629: } |
| 1327 | 17, 4, // 2633: case 0x11: { |
| 1328 | OPC_Decode, 208, 5, 33, // 2635: decode to FTINTRNE_W_S using decoder 33 |
| 1329 | // 2635: } |
| 1330 | 18, 4, // 2639: case 0x12: { |
| 1331 | OPC_Decode, 207, 5, 46, // 2641: decode to FTINTRNE_W_D using decoder 46 |
| 1332 | // 2641: } |
| 1333 | 25, 4, // 2645: case 0x19: { |
| 1334 | OPC_Decode, 206, 5, 47, // 2647: decode to FTINTRNE_L_S using decoder 47 |
| 1335 | // 2647: } |
| 1336 | 26, 0, // 2651: case 0x1a: { |
| 1337 | OPC_Decode, 205, 5, 34, // 2653: decode to FTINTRNE_L_D using decoder 34 |
| 1338 | // 2653: } |
| 1339 | // 2653: } // switch Inst[14:10] |
| 1340 | // 2653: } |
| 1341 | 54, 27, // 2657: case 0x36: { |
| 1342 | OPC_SwitchField, 10, 5, // 2659: switch Inst[14:10] { |
| 1343 | 1, 4, // 2662: case 0x1: { |
| 1344 | OPC_Decode, 220, 5, 33, // 2664: decode to FTINT_W_S using decoder 33 |
| 1345 | // 2664: } |
| 1346 | 2, 4, // 2668: case 0x2: { |
| 1347 | OPC_Decode, 219, 5, 46, // 2670: decode to FTINT_W_D using decoder 46 |
| 1348 | // 2670: } |
| 1349 | 9, 4, // 2674: case 0x9: { |
| 1350 | OPC_Decode, 218, 5, 47, // 2676: decode to FTINT_L_S using decoder 47 |
| 1351 | // 2676: } |
| 1352 | 10, 0, // 2680: case 0xa: { |
| 1353 | OPC_Decode, 217, 5, 34, // 2682: decode to FTINT_L_D using decoder 34 |
| 1354 | // 2682: } |
| 1355 | // 2682: } // switch Inst[14:10] |
| 1356 | // 2682: } |
| 1357 | 58, 27, // 2686: case 0x3a: { |
| 1358 | OPC_SwitchField, 10, 5, // 2688: switch Inst[14:10] { |
| 1359 | 4, 4, // 2691: case 0x4: { |
| 1360 | OPC_Decode, 142, 5, 33, // 2693: decode to FFINT_S_W using decoder 33 |
| 1361 | // 2693: } |
| 1362 | 6, 4, // 2697: case 0x6: { |
| 1363 | OPC_Decode, 141, 5, 46, // 2699: decode to FFINT_S_L using decoder 46 |
| 1364 | // 2699: } |
| 1365 | 8, 4, // 2703: case 0x8: { |
| 1366 | OPC_Decode, 140, 5, 47, // 2705: decode to FFINT_D_W using decoder 47 |
| 1367 | // 2705: } |
| 1368 | 10, 0, // 2709: case 0xa: { |
| 1369 | OPC_Decode, 139, 5, 34, // 2711: decode to FFINT_D_L using decoder 34 |
| 1370 | // 2711: } |
| 1371 | // 2711: } // switch Inst[14:10] |
| 1372 | // 2711: } |
| 1373 | 60, 0, // 2715: case 0x3c: { |
| 1374 | OPC_SwitchField, 10, 5, // 2717: switch Inst[14:10] { |
| 1375 | 17, 4, // 2720: case 0x11: { |
| 1376 | OPC_Decode, 180, 5, 33, // 2722: decode to FRINT_S using decoder 33 |
| 1377 | // 2722: } |
| 1378 | 18, 0, // 2726: case 0x12: { |
| 1379 | OPC_Decode, 179, 5, 34, // 2728: decode to FRINT_D using decoder 34 |
| 1380 | // 2728: } |
| 1381 | // 2728: } // switch Inst[14:10] |
| 1382 | // 2728: } |
| 1383 | // 2728: } // switch Inst[21:15] |
| 1384 | // 2728: } |
| 1385 | 8, 4, // 2732: case 0x8: { |
| 1386 | OPC_Decode, 234, 6, 48, // 2734: decode to SLTI using decoder 48 |
| 1387 | // 2734: } |
| 1388 | 9, 4, // 2738: case 0x9: { |
| 1389 | OPC_Decode, 236, 6, 48, // 2740: decode to SLTUI using decoder 48 |
| 1390 | // 2740: } |
| 1391 | 10, 4, // 2744: case 0xa: { |
| 1392 | OPC_Decode, 195, 3, 48, // 2746: decode to ADDI_W using decoder 48 |
| 1393 | // 2746: } |
| 1394 | 11, 6, // 2750: case 0xb: { |
| 1395 | OPC_CheckPredicate, 0, // 2752: check predicate 0 |
| 1396 | OPC_Decode, 194, 3, 48, // 2754: decode to ADDI_D using decoder 48 |
| 1397 | // 2754: } |
| 1398 | 12, 6, // 2758: case 0xc: { |
| 1399 | OPC_CheckPredicate, 0, // 2760: check predicate 0 |
| 1400 | OPC_Decode, 148, 6, 48, // 2762: decode to LU52I_D using decoder 48 |
| 1401 | // 2762: } |
| 1402 | 13, 4, // 2766: case 0xd: { |
| 1403 | OPC_Decode, 129, 4, 49, // 2768: decode to ANDI using decoder 49 |
| 1404 | // 2768: } |
| 1405 | 14, 4, // 2772: case 0xe: { |
| 1406 | OPC_Decode, 181, 6, 49, // 2774: decode to ORI using decoder 49 |
| 1407 | // 2774: } |
| 1408 | 15, 0, // 2778: case 0xf: { |
| 1409 | OPC_Decode, 223, 13, 49, // 2780: decode to XORI using decoder 49 |
| 1410 | // 2780: } |
| 1411 | // 2780: } // switch Inst[25:22] |
| 1412 | // 2780: } |
| 1413 | 1, 233, 1, // 2784: case 0x1: { |
| 1414 | OPC_SwitchField, 24, 2, // 2787: switch Inst[25:24] { |
| 1415 | 0, 21, // 2790: case 0x0: { |
| 1416 | OPC_Scope, 15, // 2792: try { |
| 1417 | OPC_SwitchField, 5, 5, // 2794: switch Inst[9:5] { |
| 1418 | 0, 4, // 2797: case 0x0: { |
| 1419 | OPC_Decode, 192, 4, 50, // 2799: decode to CSRRD using decoder 50 |
| 1420 | // 2799: } |
| 1421 | 1, 0, // 2803: case 0x1: { |
| 1422 | OPC_Decode, 193, 4, 51, // 2805: decode to CSRWR using decoder 51 |
| 1423 | // 2805: } |
| 1424 | // 2805: } // switch Inst[9:5] |
| 1425 | // 2805: } else try { |
| 1426 | OPC_Decode, 194, 4, 52, // 2809: decode to CSRXCHG using decoder 52 |
| 1427 | // 2809: } |
| 1428 | // 2809: } |
| 1429 | 1, 21, // 2813: case 0x1: { |
| 1430 | OPC_Scope, 15, // 2815: try { |
| 1431 | OPC_SwitchField, 5, 5, // 2817: switch Inst[9:5] { |
| 1432 | 0, 4, // 2820: case 0x0: { |
| 1433 | OPC_Decode, 221, 5, 50, // 2822: decode to GCSRRD using decoder 50 |
| 1434 | // 2822: } |
| 1435 | 1, 0, // 2826: case 0x1: { |
| 1436 | OPC_Decode, 222, 5, 51, // 2828: decode to GCSRWR using decoder 51 |
| 1437 | // 2828: } |
| 1438 | // 2828: } // switch Inst[9:5] |
| 1439 | // 2828: } else try { |
| 1440 | OPC_Decode, 223, 5, 52, // 2832: decode to GCSRXCHG using decoder 52 |
| 1441 | // 2832: } |
| 1442 | // 2832: } |
| 1443 | 2, 0, // 2836: case 0x2: { |
| 1444 | OPC_SwitchField, 22, 2, // 2838: switch Inst[23:22] { |
| 1445 | 0, 4, // 2841: case 0x0: { |
| 1446 | OPC_Decode, 178, 4, 53, // 2843: decode to CACOP using decoder 53 |
| 1447 | // 2843: } |
| 1448 | 1, 0, // 2847: case 0x1: { |
| 1449 | OPC_SwitchField, 18, 4, // 2849: switch Inst[21:18] { |
| 1450 | 0, 4, // 2852: case 0x0: { |
| 1451 | OPC_Decode, 240, 5, 54, // 2854: decode to LDDIR using decoder 54 |
| 1452 | // 2854: } |
| 1453 | 1, 8, // 2858: case 0x1: { |
| 1454 | OPC_CheckField, 0, 5, 0, // 2860: check Inst[4:0] == 0x0 |
| 1455 | OPC_Decode, 251, 5, 55, // 2864: decode to LDPTE using decoder 55 |
| 1456 | // 2864: } |
| 1457 | 2, 0, // 2868: case 0x2: { |
| 1458 | OPC_SwitchField, 15, 3, // 2870: switch Inst[17:15] { |
| 1459 | 0, 132, 1, // 2873: case 0x0: { |
| 1460 | OPC_SwitchField, 10, 5, // 2876: switch Inst[14:10] { |
| 1461 | 0, 4, // 2879: case 0x0: { |
| 1462 | OPC_Decode, 229, 5, 2, // 2881: decode to IOCSRRD_B using decoder 2 |
| 1463 | // 2881: } |
| 1464 | 1, 4, // 2885: case 0x1: { |
| 1465 | OPC_Decode, 231, 5, 2, // 2887: decode to IOCSRRD_H using decoder 2 |
| 1466 | // 2887: } |
| 1467 | 2, 4, // 2891: case 0x2: { |
| 1468 | OPC_Decode, 232, 5, 2, // 2893: decode to IOCSRRD_W using decoder 2 |
| 1469 | // 2893: } |
| 1470 | 3, 6, // 2897: case 0x3: { |
| 1471 | OPC_CheckPredicate, 0, // 2899: check predicate 0 |
| 1472 | OPC_Decode, 230, 5, 2, // 2901: decode to IOCSRRD_D using decoder 2 |
| 1473 | // 2901: } |
| 1474 | 4, 4, // 2905: case 0x4: { |
| 1475 | OPC_Decode, 233, 5, 2, // 2907: decode to IOCSRWR_B using decoder 2 |
| 1476 | // 2907: } |
| 1477 | 5, 4, // 2911: case 0x5: { |
| 1478 | OPC_Decode, 235, 5, 2, // 2913: decode to IOCSRWR_H using decoder 2 |
| 1479 | // 2913: } |
| 1480 | 6, 4, // 2917: case 0x6: { |
| 1481 | OPC_Decode, 236, 5, 2, // 2919: decode to IOCSRWR_W using decoder 2 |
| 1482 | // 2919: } |
| 1483 | 7, 6, // 2923: case 0x7: { |
| 1484 | OPC_CheckPredicate, 0, // 2925: check predicate 0 |
| 1485 | OPC_Decode, 234, 5, 2, // 2927: decode to IOCSRWR_D using decoder 2 |
| 1486 | // 2927: } |
| 1487 | 8, 8, // 2931: case 0x8: { |
| 1488 | OPC_CheckField, 0, 10, 0, // 2933: check Inst[9:0] == 0x0 |
| 1489 | OPC_Decode, 142, 7, 6, // 2937: decode to TLBCLR using decoder 6 |
| 1490 | // 2937: } |
| 1491 | 9, 15, // 2941: case 0x9: { |
| 1492 | OPC_SwitchField, 0, 10, // 2943: switch Inst[9:0] { |
| 1493 | 0, 4, // 2946: case 0x0: { |
| 1494 | OPC_Decode, 144, 7, 6, // 2948: decode to TLBFLUSH using decoder 6 |
| 1495 | // 2948: } |
| 1496 | 1, 0, // 2952: case 0x1: { |
| 1497 | OPC_Decode, 224, 5, 6, // 2954: decode to GTLBFLUSH using decoder 6 |
| 1498 | // 2954: } |
| 1499 | // 2954: } // switch Inst[9:0] |
| 1500 | // 2954: } |
| 1501 | 10, 8, // 2958: case 0xa: { |
| 1502 | OPC_CheckField, 0, 10, 0, // 2960: check Inst[9:0] == 0x0 |
| 1503 | OPC_Decode, 146, 7, 6, // 2964: decode to TLBSRCH using decoder 6 |
| 1504 | // 2964: } |
| 1505 | 11, 8, // 2968: case 0xb: { |
| 1506 | OPC_CheckField, 0, 10, 0, // 2970: check Inst[9:0] == 0x0 |
| 1507 | OPC_Decode, 145, 7, 6, // 2974: decode to TLBRD using decoder 6 |
| 1508 | // 2974: } |
| 1509 | 12, 8, // 2978: case 0xc: { |
| 1510 | OPC_CheckField, 0, 10, 0, // 2980: check Inst[9:0] == 0x0 |
| 1511 | OPC_Decode, 147, 7, 6, // 2984: decode to TLBWR using decoder 6 |
| 1512 | // 2984: } |
| 1513 | 13, 8, // 2988: case 0xd: { |
| 1514 | OPC_CheckField, 0, 10, 0, // 2990: check Inst[9:0] == 0x0 |
| 1515 | OPC_Decode, 143, 7, 6, // 2994: decode to TLBFILL using decoder 6 |
| 1516 | // 2994: } |
| 1517 | 14, 0, // 2998: case 0xe: { |
| 1518 | OPC_CheckField, 0, 10, 0, // 3000: check Inst[9:0] == 0x0 |
| 1519 | OPC_Decode, 205, 4, 6, // 3004: decode to ERTN using decoder 6 |
| 1520 | // 3004: } |
| 1521 | // 3004: } // switch Inst[14:10] |
| 1522 | // 3004: } |
| 1523 | 1, 4, // 3008: case 0x1: { |
| 1524 | OPC_Decode, 227, 5, 13, // 3010: decode to IDLE using decoder 13 |
| 1525 | // 3010: } |
| 1526 | 3, 0, // 3014: case 0x3: { |
| 1527 | OPC_Decode, 228, 5, 56, // 3016: decode to INVTLB using decoder 56 |
| 1528 | // 3016: } |
| 1529 | // 3016: } // switch Inst[17:15] |
| 1530 | // 3016: } |
| 1531 | // 3016: } // switch Inst[21:18] |
| 1532 | // 3016: } |
| 1533 | // 3016: } // switch Inst[23:22] |
| 1534 | // 3016: } |
| 1535 | // 3016: } // switch Inst[25:24] |
| 1536 | // 3016: } |
| 1537 | 2, 147, 1, // 3020: case 0x2: { |
| 1538 | OPC_SwitchField, 20, 6, // 3023: switch Inst[25:20] { |
| 1539 | 1, 4, // 3026: case 0x1: { |
| 1540 | OPC_Decode, 154, 5, 57, // 3028: decode to FMADD_S using decoder 57 |
| 1541 | // 3028: } |
| 1542 | 2, 4, // 3032: case 0x2: { |
| 1543 | OPC_Decode, 153, 5, 58, // 3034: decode to FMADD_D using decoder 58 |
| 1544 | // 3034: } |
| 1545 | 5, 4, // 3038: case 0x5: { |
| 1546 | OPC_Decode, 166, 5, 57, // 3040: decode to FMSUB_S using decoder 57 |
| 1547 | // 3040: } |
| 1548 | 6, 4, // 3044: case 0x6: { |
| 1549 | OPC_Decode, 165, 5, 58, // 3046: decode to FMSUB_D using decoder 58 |
| 1550 | // 3046: } |
| 1551 | 9, 4, // 3050: case 0x9: { |
| 1552 | OPC_Decode, 172, 5, 57, // 3052: decode to FNMADD_S using decoder 57 |
| 1553 | // 3052: } |
| 1554 | 10, 4, // 3056: case 0xa: { |
| 1555 | OPC_Decode, 171, 5, 58, // 3058: decode to FNMADD_D using decoder 58 |
| 1556 | // 3058: } |
| 1557 | 13, 4, // 3062: case 0xd: { |
| 1558 | OPC_Decode, 174, 5, 57, // 3064: decode to FNMSUB_S using decoder 57 |
| 1559 | // 3064: } |
| 1560 | 14, 4, // 3068: case 0xe: { |
| 1561 | OPC_Decode, 173, 5, 58, // 3070: decode to FNMSUB_D using decoder 58 |
| 1562 | // 3070: } |
| 1563 | 17, 4, // 3074: case 0x11: { |
| 1564 | OPC_Decode, 221, 8, 59, // 3076: decode to VFMADD_S using decoder 59 |
| 1565 | // 3076: } |
| 1566 | 18, 4, // 3080: case 0x12: { |
| 1567 | OPC_Decode, 220, 8, 59, // 3082: decode to VFMADD_D using decoder 59 |
| 1568 | // 3082: } |
| 1569 | 21, 4, // 3086: case 0x15: { |
| 1570 | OPC_Decode, 231, 8, 59, // 3088: decode to VFMSUB_S using decoder 59 |
| 1571 | // 3088: } |
| 1572 | 22, 4, // 3092: case 0x16: { |
| 1573 | OPC_Decode, 230, 8, 59, // 3094: decode to VFMSUB_D using decoder 59 |
| 1574 | // 3094: } |
| 1575 | 25, 4, // 3098: case 0x19: { |
| 1576 | OPC_Decode, 235, 8, 59, // 3100: decode to VFNMADD_S using decoder 59 |
| 1577 | // 3100: } |
| 1578 | 26, 4, // 3104: case 0x1a: { |
| 1579 | OPC_Decode, 234, 8, 59, // 3106: decode to VFNMADD_D using decoder 59 |
| 1580 | // 3106: } |
| 1581 | 29, 4, // 3110: case 0x1d: { |
| 1582 | OPC_Decode, 237, 8, 59, // 3112: decode to VFNMSUB_S using decoder 59 |
| 1583 | // 3112: } |
| 1584 | 30, 4, // 3116: case 0x1e: { |
| 1585 | OPC_Decode, 236, 8, 59, // 3118: decode to VFNMSUB_D using decoder 59 |
| 1586 | // 3118: } |
| 1587 | 33, 4, // 3122: case 0x21: { |
| 1588 | OPC_Decode, 156, 15, 60, // 3124: decode to XVFMADD_S using decoder 60 |
| 1589 | // 3124: } |
| 1590 | 34, 4, // 3128: case 0x22: { |
| 1591 | OPC_Decode, 155, 15, 60, // 3130: decode to XVFMADD_D using decoder 60 |
| 1592 | // 3130: } |
| 1593 | 37, 4, // 3134: case 0x25: { |
| 1594 | OPC_Decode, 166, 15, 60, // 3136: decode to XVFMSUB_S using decoder 60 |
| 1595 | // 3136: } |
| 1596 | 38, 4, // 3140: case 0x26: { |
| 1597 | OPC_Decode, 165, 15, 60, // 3142: decode to XVFMSUB_D using decoder 60 |
| 1598 | // 3142: } |
| 1599 | 41, 4, // 3146: case 0x29: { |
| 1600 | OPC_Decode, 170, 15, 60, // 3148: decode to XVFNMADD_S using decoder 60 |
| 1601 | // 3148: } |
| 1602 | 42, 4, // 3152: case 0x2a: { |
| 1603 | OPC_Decode, 169, 15, 60, // 3154: decode to XVFNMADD_D using decoder 60 |
| 1604 | // 3154: } |
| 1605 | 45, 4, // 3158: case 0x2d: { |
| 1606 | OPC_Decode, 172, 15, 60, // 3160: decode to XVFNMSUB_S using decoder 60 |
| 1607 | // 3160: } |
| 1608 | 46, 0, // 3164: case 0x2e: { |
| 1609 | OPC_Decode, 171, 15, 60, // 3166: decode to XVFNMSUB_D using decoder 60 |
| 1610 | // 3166: } |
| 1611 | // 3166: } // switch Inst[25:20] |
| 1612 | // 3166: } |
| 1613 | 3, 145, 8, // 3170: case 0x3: { |
| 1614 | OPC_SwitchField, 20, 6, // 3173: switch Inst[25:20] { |
| 1615 | 1, 223, 1, // 3176: case 0x1: { |
| 1616 | OPC_SwitchField, 15, 5, // 3179: switch Inst[19:15] { |
| 1617 | 0, 8, // 3182: case 0x0: { |
| 1618 | OPC_CheckField, 3, 2, 0, // 3184: check Inst[4:3] == 0x0 |
| 1619 | OPC_Decode, 215, 4, 61, // 3188: decode to FCMP_CAF_S using decoder 61 |
| 1620 | // 3188: } |
| 1621 | 1, 8, // 3192: case 0x1: { |
| 1622 | OPC_CheckField, 3, 2, 0, // 3194: check Inst[4:3] == 0x0 |
| 1623 | OPC_Decode, 237, 4, 61, // 3198: decode to FCMP_SAF_S using decoder 61 |
| 1624 | // 3198: } |
| 1625 | 2, 8, // 3202: case 0x2: { |
| 1626 | OPC_CheckField, 3, 2, 0, // 3204: check Inst[4:3] == 0x0 |
| 1627 | OPC_Decode, 221, 4, 61, // 3208: decode to FCMP_CLT_S using decoder 61 |
| 1628 | // 3208: } |
| 1629 | 3, 8, // 3212: case 0x3: { |
| 1630 | OPC_CheckField, 3, 2, 0, // 3214: check Inst[4:3] == 0x0 |
| 1631 | OPC_Decode, 243, 4, 61, // 3218: decode to FCMP_SLT_S using decoder 61 |
| 1632 | // 3218: } |
| 1633 | 4, 8, // 3222: case 0x4: { |
| 1634 | OPC_CheckField, 3, 2, 0, // 3224: check Inst[4:3] == 0x0 |
| 1635 | OPC_Decode, 217, 4, 61, // 3228: decode to FCMP_CEQ_S using decoder 61 |
| 1636 | // 3228: } |
| 1637 | 5, 8, // 3232: case 0x5: { |
| 1638 | OPC_CheckField, 3, 2, 0, // 3234: check Inst[4:3] == 0x0 |
| 1639 | OPC_Decode, 239, 4, 61, // 3238: decode to FCMP_SEQ_S using decoder 61 |
| 1640 | // 3238: } |
| 1641 | 6, 8, // 3242: case 0x6: { |
| 1642 | OPC_CheckField, 3, 2, 0, // 3244: check Inst[4:3] == 0x0 |
| 1643 | OPC_Decode, 219, 4, 61, // 3248: decode to FCMP_CLE_S using decoder 61 |
| 1644 | // 3248: } |
| 1645 | 7, 8, // 3252: case 0x7: { |
| 1646 | OPC_CheckField, 3, 2, 0, // 3254: check Inst[4:3] == 0x0 |
| 1647 | OPC_Decode, 241, 4, 61, // 3258: decode to FCMP_SLE_S using decoder 61 |
| 1648 | // 3258: } |
| 1649 | 8, 8, // 3262: case 0x8: { |
| 1650 | OPC_CheckField, 3, 2, 0, // 3264: check Inst[4:3] == 0x0 |
| 1651 | OPC_Decode, 235, 4, 61, // 3268: decode to FCMP_CUN_S using decoder 61 |
| 1652 | // 3268: } |
| 1653 | 9, 8, // 3272: case 0x9: { |
| 1654 | OPC_CheckField, 3, 2, 0, // 3274: check Inst[4:3] == 0x0 |
| 1655 | OPC_Decode, 129, 5, 61, // 3278: decode to FCMP_SUN_S using decoder 61 |
| 1656 | // 3278: } |
| 1657 | 10, 8, // 3282: case 0xa: { |
| 1658 | OPC_CheckField, 3, 2, 0, // 3284: check Inst[4:3] == 0x0 |
| 1659 | OPC_Decode, 231, 4, 61, // 3288: decode to FCMP_CULT_S using decoder 61 |
| 1660 | // 3288: } |
| 1661 | 11, 8, // 3292: case 0xb: { |
| 1662 | OPC_CheckField, 3, 2, 0, // 3294: check Inst[4:3] == 0x0 |
| 1663 | OPC_Decode, 253, 4, 61, // 3298: decode to FCMP_SULT_S using decoder 61 |
| 1664 | // 3298: } |
| 1665 | 12, 8, // 3302: case 0xc: { |
| 1666 | OPC_CheckField, 3, 2, 0, // 3304: check Inst[4:3] == 0x0 |
| 1667 | OPC_Decode, 227, 4, 61, // 3308: decode to FCMP_CUEQ_S using decoder 61 |
| 1668 | // 3308: } |
| 1669 | 13, 8, // 3312: case 0xd: { |
| 1670 | OPC_CheckField, 3, 2, 0, // 3314: check Inst[4:3] == 0x0 |
| 1671 | OPC_Decode, 249, 4, 61, // 3318: decode to FCMP_SUEQ_S using decoder 61 |
| 1672 | // 3318: } |
| 1673 | 14, 8, // 3322: case 0xe: { |
| 1674 | OPC_CheckField, 3, 2, 0, // 3324: check Inst[4:3] == 0x0 |
| 1675 | OPC_Decode, 229, 4, 61, // 3328: decode to FCMP_CULE_S using decoder 61 |
| 1676 | // 3328: } |
| 1677 | 15, 8, // 3332: case 0xf: { |
| 1678 | OPC_CheckField, 3, 2, 0, // 3334: check Inst[4:3] == 0x0 |
| 1679 | OPC_Decode, 251, 4, 61, // 3338: decode to FCMP_SULE_S using decoder 61 |
| 1680 | // 3338: } |
| 1681 | 16, 8, // 3342: case 0x10: { |
| 1682 | OPC_CheckField, 3, 2, 0, // 3344: check Inst[4:3] == 0x0 |
| 1683 | OPC_Decode, 223, 4, 61, // 3348: decode to FCMP_CNE_S using decoder 61 |
| 1684 | // 3348: } |
| 1685 | 17, 8, // 3352: case 0x11: { |
| 1686 | OPC_CheckField, 3, 2, 0, // 3354: check Inst[4:3] == 0x0 |
| 1687 | OPC_Decode, 245, 4, 61, // 3358: decode to FCMP_SNE_S using decoder 61 |
| 1688 | // 3358: } |
| 1689 | 20, 8, // 3362: case 0x14: { |
| 1690 | OPC_CheckField, 3, 2, 0, // 3364: check Inst[4:3] == 0x0 |
| 1691 | OPC_Decode, 225, 4, 61, // 3368: decode to FCMP_COR_S using decoder 61 |
| 1692 | // 3368: } |
| 1693 | 21, 8, // 3372: case 0x15: { |
| 1694 | OPC_CheckField, 3, 2, 0, // 3374: check Inst[4:3] == 0x0 |
| 1695 | OPC_Decode, 247, 4, 61, // 3378: decode to FCMP_SOR_S using decoder 61 |
| 1696 | // 3378: } |
| 1697 | 24, 8, // 3382: case 0x18: { |
| 1698 | OPC_CheckField, 3, 2, 0, // 3384: check Inst[4:3] == 0x0 |
| 1699 | OPC_Decode, 233, 4, 61, // 3388: decode to FCMP_CUNE_S using decoder 61 |
| 1700 | // 3388: } |
| 1701 | 25, 0, // 3392: case 0x19: { |
| 1702 | OPC_CheckField, 3, 2, 0, // 3394: check Inst[4:3] == 0x0 |
| 1703 | OPC_Decode, 255, 4, 61, // 3398: decode to FCMP_SUNE_S using decoder 61 |
| 1704 | // 3398: } |
| 1705 | // 3398: } // switch Inst[19:15] |
| 1706 | // 3398: } |
| 1707 | 2, 223, 1, // 3402: case 0x2: { |
| 1708 | OPC_SwitchField, 15, 5, // 3405: switch Inst[19:15] { |
| 1709 | 0, 8, // 3408: case 0x0: { |
| 1710 | OPC_CheckField, 3, 2, 0, // 3410: check Inst[4:3] == 0x0 |
| 1711 | OPC_Decode, 214, 4, 62, // 3414: decode to FCMP_CAF_D using decoder 62 |
| 1712 | // 3414: } |
| 1713 | 1, 8, // 3418: case 0x1: { |
| 1714 | OPC_CheckField, 3, 2, 0, // 3420: check Inst[4:3] == 0x0 |
| 1715 | OPC_Decode, 236, 4, 62, // 3424: decode to FCMP_SAF_D using decoder 62 |
| 1716 | // 3424: } |
| 1717 | 2, 8, // 3428: case 0x2: { |
| 1718 | OPC_CheckField, 3, 2, 0, // 3430: check Inst[4:3] == 0x0 |
| 1719 | OPC_Decode, 220, 4, 62, // 3434: decode to FCMP_CLT_D using decoder 62 |
| 1720 | // 3434: } |
| 1721 | 3, 8, // 3438: case 0x3: { |
| 1722 | OPC_CheckField, 3, 2, 0, // 3440: check Inst[4:3] == 0x0 |
| 1723 | OPC_Decode, 242, 4, 62, // 3444: decode to FCMP_SLT_D using decoder 62 |
| 1724 | // 3444: } |
| 1725 | 4, 8, // 3448: case 0x4: { |
| 1726 | OPC_CheckField, 3, 2, 0, // 3450: check Inst[4:3] == 0x0 |
| 1727 | OPC_Decode, 216, 4, 62, // 3454: decode to FCMP_CEQ_D using decoder 62 |
| 1728 | // 3454: } |
| 1729 | 5, 8, // 3458: case 0x5: { |
| 1730 | OPC_CheckField, 3, 2, 0, // 3460: check Inst[4:3] == 0x0 |
| 1731 | OPC_Decode, 238, 4, 62, // 3464: decode to FCMP_SEQ_D using decoder 62 |
| 1732 | // 3464: } |
| 1733 | 6, 8, // 3468: case 0x6: { |
| 1734 | OPC_CheckField, 3, 2, 0, // 3470: check Inst[4:3] == 0x0 |
| 1735 | OPC_Decode, 218, 4, 62, // 3474: decode to FCMP_CLE_D using decoder 62 |
| 1736 | // 3474: } |
| 1737 | 7, 8, // 3478: case 0x7: { |
| 1738 | OPC_CheckField, 3, 2, 0, // 3480: check Inst[4:3] == 0x0 |
| 1739 | OPC_Decode, 240, 4, 62, // 3484: decode to FCMP_SLE_D using decoder 62 |
| 1740 | // 3484: } |
| 1741 | 8, 8, // 3488: case 0x8: { |
| 1742 | OPC_CheckField, 3, 2, 0, // 3490: check Inst[4:3] == 0x0 |
| 1743 | OPC_Decode, 234, 4, 62, // 3494: decode to FCMP_CUN_D using decoder 62 |
| 1744 | // 3494: } |
| 1745 | 9, 8, // 3498: case 0x9: { |
| 1746 | OPC_CheckField, 3, 2, 0, // 3500: check Inst[4:3] == 0x0 |
| 1747 | OPC_Decode, 128, 5, 62, // 3504: decode to FCMP_SUN_D using decoder 62 |
| 1748 | // 3504: } |
| 1749 | 10, 8, // 3508: case 0xa: { |
| 1750 | OPC_CheckField, 3, 2, 0, // 3510: check Inst[4:3] == 0x0 |
| 1751 | OPC_Decode, 230, 4, 62, // 3514: decode to FCMP_CULT_D using decoder 62 |
| 1752 | // 3514: } |
| 1753 | 11, 8, // 3518: case 0xb: { |
| 1754 | OPC_CheckField, 3, 2, 0, // 3520: check Inst[4:3] == 0x0 |
| 1755 | OPC_Decode, 252, 4, 62, // 3524: decode to FCMP_SULT_D using decoder 62 |
| 1756 | // 3524: } |
| 1757 | 12, 8, // 3528: case 0xc: { |
| 1758 | OPC_CheckField, 3, 2, 0, // 3530: check Inst[4:3] == 0x0 |
| 1759 | OPC_Decode, 226, 4, 62, // 3534: decode to FCMP_CUEQ_D using decoder 62 |
| 1760 | // 3534: } |
| 1761 | 13, 8, // 3538: case 0xd: { |
| 1762 | OPC_CheckField, 3, 2, 0, // 3540: check Inst[4:3] == 0x0 |
| 1763 | OPC_Decode, 248, 4, 62, // 3544: decode to FCMP_SUEQ_D using decoder 62 |
| 1764 | // 3544: } |
| 1765 | 14, 8, // 3548: case 0xe: { |
| 1766 | OPC_CheckField, 3, 2, 0, // 3550: check Inst[4:3] == 0x0 |
| 1767 | OPC_Decode, 228, 4, 62, // 3554: decode to FCMP_CULE_D using decoder 62 |
| 1768 | // 3554: } |
| 1769 | 15, 8, // 3558: case 0xf: { |
| 1770 | OPC_CheckField, 3, 2, 0, // 3560: check Inst[4:3] == 0x0 |
| 1771 | OPC_Decode, 250, 4, 62, // 3564: decode to FCMP_SULE_D using decoder 62 |
| 1772 | // 3564: } |
| 1773 | 16, 8, // 3568: case 0x10: { |
| 1774 | OPC_CheckField, 3, 2, 0, // 3570: check Inst[4:3] == 0x0 |
| 1775 | OPC_Decode, 222, 4, 62, // 3574: decode to FCMP_CNE_D using decoder 62 |
| 1776 | // 3574: } |
| 1777 | 17, 8, // 3578: case 0x11: { |
| 1778 | OPC_CheckField, 3, 2, 0, // 3580: check Inst[4:3] == 0x0 |
| 1779 | OPC_Decode, 244, 4, 62, // 3584: decode to FCMP_SNE_D using decoder 62 |
| 1780 | // 3584: } |
| 1781 | 20, 8, // 3588: case 0x14: { |
| 1782 | OPC_CheckField, 3, 2, 0, // 3590: check Inst[4:3] == 0x0 |
| 1783 | OPC_Decode, 224, 4, 62, // 3594: decode to FCMP_COR_D using decoder 62 |
| 1784 | // 3594: } |
| 1785 | 21, 8, // 3598: case 0x15: { |
| 1786 | OPC_CheckField, 3, 2, 0, // 3600: check Inst[4:3] == 0x0 |
| 1787 | OPC_Decode, 246, 4, 62, // 3604: decode to FCMP_SOR_D using decoder 62 |
| 1788 | // 3604: } |
| 1789 | 24, 8, // 3608: case 0x18: { |
| 1790 | OPC_CheckField, 3, 2, 0, // 3610: check Inst[4:3] == 0x0 |
| 1791 | OPC_Decode, 232, 4, 62, // 3614: decode to FCMP_CUNE_D using decoder 62 |
| 1792 | // 3614: } |
| 1793 | 25, 0, // 3618: case 0x19: { |
| 1794 | OPC_CheckField, 3, 2, 0, // 3620: check Inst[4:3] == 0x0 |
| 1795 | OPC_Decode, 254, 4, 62, // 3624: decode to FCMP_SUNE_D using decoder 62 |
| 1796 | // 3624: } |
| 1797 | // 3624: } // switch Inst[19:15] |
| 1798 | // 3624: } |
| 1799 | 5, 135, 1, // 3628: case 0x5: { |
| 1800 | OPC_SwitchField, 15, 5, // 3631: switch Inst[19:15] { |
| 1801 | 0, 4, // 3634: case 0x0: { |
| 1802 | OPC_Decode, 160, 8, 63, // 3636: decode to VFCMP_CAF_S using decoder 63 |
| 1803 | // 3636: } |
| 1804 | 1, 4, // 3640: case 0x1: { |
| 1805 | OPC_Decode, 182, 8, 63, // 3642: decode to VFCMP_SAF_S using decoder 63 |
| 1806 | // 3642: } |
| 1807 | 2, 4, // 3646: case 0x2: { |
| 1808 | OPC_Decode, 166, 8, 63, // 3648: decode to VFCMP_CLT_S using decoder 63 |
| 1809 | // 3648: } |
| 1810 | 3, 4, // 3652: case 0x3: { |
| 1811 | OPC_Decode, 188, 8, 63, // 3654: decode to VFCMP_SLT_S using decoder 63 |
| 1812 | // 3654: } |
| 1813 | 4, 4, // 3658: case 0x4: { |
| 1814 | OPC_Decode, 162, 8, 63, // 3660: decode to VFCMP_CEQ_S using decoder 63 |
| 1815 | // 3660: } |
| 1816 | 5, 4, // 3664: case 0x5: { |
| 1817 | OPC_Decode, 184, 8, 63, // 3666: decode to VFCMP_SEQ_S using decoder 63 |
| 1818 | // 3666: } |
| 1819 | 6, 4, // 3670: case 0x6: { |
| 1820 | OPC_Decode, 164, 8, 63, // 3672: decode to VFCMP_CLE_S using decoder 63 |
| 1821 | // 3672: } |
| 1822 | 7, 4, // 3676: case 0x7: { |
| 1823 | OPC_Decode, 186, 8, 63, // 3678: decode to VFCMP_SLE_S using decoder 63 |
| 1824 | // 3678: } |
| 1825 | 8, 4, // 3682: case 0x8: { |
| 1826 | OPC_Decode, 180, 8, 63, // 3684: decode to VFCMP_CUN_S using decoder 63 |
| 1827 | // 3684: } |
| 1828 | 9, 4, // 3688: case 0x9: { |
| 1829 | OPC_Decode, 202, 8, 63, // 3690: decode to VFCMP_SUN_S using decoder 63 |
| 1830 | // 3690: } |
| 1831 | 10, 4, // 3694: case 0xa: { |
| 1832 | OPC_Decode, 176, 8, 63, // 3696: decode to VFCMP_CULT_S using decoder 63 |
| 1833 | // 3696: } |
| 1834 | 11, 4, // 3700: case 0xb: { |
| 1835 | OPC_Decode, 198, 8, 63, // 3702: decode to VFCMP_SULT_S using decoder 63 |
| 1836 | // 3702: } |
| 1837 | 12, 4, // 3706: case 0xc: { |
| 1838 | OPC_Decode, 172, 8, 63, // 3708: decode to VFCMP_CUEQ_S using decoder 63 |
| 1839 | // 3708: } |
| 1840 | 13, 4, // 3712: case 0xd: { |
| 1841 | OPC_Decode, 194, 8, 63, // 3714: decode to VFCMP_SUEQ_S using decoder 63 |
| 1842 | // 3714: } |
| 1843 | 14, 4, // 3718: case 0xe: { |
| 1844 | OPC_Decode, 174, 8, 63, // 3720: decode to VFCMP_CULE_S using decoder 63 |
| 1845 | // 3720: } |
| 1846 | 15, 4, // 3724: case 0xf: { |
| 1847 | OPC_Decode, 196, 8, 63, // 3726: decode to VFCMP_SULE_S using decoder 63 |
| 1848 | // 3726: } |
| 1849 | 16, 4, // 3730: case 0x10: { |
| 1850 | OPC_Decode, 168, 8, 63, // 3732: decode to VFCMP_CNE_S using decoder 63 |
| 1851 | // 3732: } |
| 1852 | 17, 4, // 3736: case 0x11: { |
| 1853 | OPC_Decode, 190, 8, 63, // 3738: decode to VFCMP_SNE_S using decoder 63 |
| 1854 | // 3738: } |
| 1855 | 20, 4, // 3742: case 0x14: { |
| 1856 | OPC_Decode, 170, 8, 63, // 3744: decode to VFCMP_COR_S using decoder 63 |
| 1857 | // 3744: } |
| 1858 | 21, 4, // 3748: case 0x15: { |
| 1859 | OPC_Decode, 192, 8, 63, // 3750: decode to VFCMP_SOR_S using decoder 63 |
| 1860 | // 3750: } |
| 1861 | 24, 4, // 3754: case 0x18: { |
| 1862 | OPC_Decode, 178, 8, 63, // 3756: decode to VFCMP_CUNE_S using decoder 63 |
| 1863 | // 3756: } |
| 1864 | 25, 0, // 3760: case 0x19: { |
| 1865 | OPC_Decode, 200, 8, 63, // 3762: decode to VFCMP_SUNE_S using decoder 63 |
| 1866 | // 3762: } |
| 1867 | // 3762: } // switch Inst[19:15] |
| 1868 | // 3762: } |
| 1869 | 6, 135, 1, // 3766: case 0x6: { |
| 1870 | OPC_SwitchField, 15, 5, // 3769: switch Inst[19:15] { |
| 1871 | 0, 4, // 3772: case 0x0: { |
| 1872 | OPC_Decode, 159, 8, 63, // 3774: decode to VFCMP_CAF_D using decoder 63 |
| 1873 | // 3774: } |
| 1874 | 1, 4, // 3778: case 0x1: { |
| 1875 | OPC_Decode, 181, 8, 63, // 3780: decode to VFCMP_SAF_D using decoder 63 |
| 1876 | // 3780: } |
| 1877 | 2, 4, // 3784: case 0x2: { |
| 1878 | OPC_Decode, 165, 8, 63, // 3786: decode to VFCMP_CLT_D using decoder 63 |
| 1879 | // 3786: } |
| 1880 | 3, 4, // 3790: case 0x3: { |
| 1881 | OPC_Decode, 187, 8, 63, // 3792: decode to VFCMP_SLT_D using decoder 63 |
| 1882 | // 3792: } |
| 1883 | 4, 4, // 3796: case 0x4: { |
| 1884 | OPC_Decode, 161, 8, 63, // 3798: decode to VFCMP_CEQ_D using decoder 63 |
| 1885 | // 3798: } |
| 1886 | 5, 4, // 3802: case 0x5: { |
| 1887 | OPC_Decode, 183, 8, 63, // 3804: decode to VFCMP_SEQ_D using decoder 63 |
| 1888 | // 3804: } |
| 1889 | 6, 4, // 3808: case 0x6: { |
| 1890 | OPC_Decode, 163, 8, 63, // 3810: decode to VFCMP_CLE_D using decoder 63 |
| 1891 | // 3810: } |
| 1892 | 7, 4, // 3814: case 0x7: { |
| 1893 | OPC_Decode, 185, 8, 63, // 3816: decode to VFCMP_SLE_D using decoder 63 |
| 1894 | // 3816: } |
| 1895 | 8, 4, // 3820: case 0x8: { |
| 1896 | OPC_Decode, 179, 8, 63, // 3822: decode to VFCMP_CUN_D using decoder 63 |
| 1897 | // 3822: } |
| 1898 | 9, 4, // 3826: case 0x9: { |
| 1899 | OPC_Decode, 201, 8, 63, // 3828: decode to VFCMP_SUN_D using decoder 63 |
| 1900 | // 3828: } |
| 1901 | 10, 4, // 3832: case 0xa: { |
| 1902 | OPC_Decode, 175, 8, 63, // 3834: decode to VFCMP_CULT_D using decoder 63 |
| 1903 | // 3834: } |
| 1904 | 11, 4, // 3838: case 0xb: { |
| 1905 | OPC_Decode, 197, 8, 63, // 3840: decode to VFCMP_SULT_D using decoder 63 |
| 1906 | // 3840: } |
| 1907 | 12, 4, // 3844: case 0xc: { |
| 1908 | OPC_Decode, 171, 8, 63, // 3846: decode to VFCMP_CUEQ_D using decoder 63 |
| 1909 | // 3846: } |
| 1910 | 13, 4, // 3850: case 0xd: { |
| 1911 | OPC_Decode, 193, 8, 63, // 3852: decode to VFCMP_SUEQ_D using decoder 63 |
| 1912 | // 3852: } |
| 1913 | 14, 4, // 3856: case 0xe: { |
| 1914 | OPC_Decode, 173, 8, 63, // 3858: decode to VFCMP_CULE_D using decoder 63 |
| 1915 | // 3858: } |
| 1916 | 15, 4, // 3862: case 0xf: { |
| 1917 | OPC_Decode, 195, 8, 63, // 3864: decode to VFCMP_SULE_D using decoder 63 |
| 1918 | // 3864: } |
| 1919 | 16, 4, // 3868: case 0x10: { |
| 1920 | OPC_Decode, 167, 8, 63, // 3870: decode to VFCMP_CNE_D using decoder 63 |
| 1921 | // 3870: } |
| 1922 | 17, 4, // 3874: case 0x11: { |
| 1923 | OPC_Decode, 189, 8, 63, // 3876: decode to VFCMP_SNE_D using decoder 63 |
| 1924 | // 3876: } |
| 1925 | 20, 4, // 3880: case 0x14: { |
| 1926 | OPC_Decode, 169, 8, 63, // 3882: decode to VFCMP_COR_D using decoder 63 |
| 1927 | // 3882: } |
| 1928 | 21, 4, // 3886: case 0x15: { |
| 1929 | OPC_Decode, 191, 8, 63, // 3888: decode to VFCMP_SOR_D using decoder 63 |
| 1930 | // 3888: } |
| 1931 | 24, 4, // 3892: case 0x18: { |
| 1932 | OPC_Decode, 177, 8, 63, // 3894: decode to VFCMP_CUNE_D using decoder 63 |
| 1933 | // 3894: } |
| 1934 | 25, 0, // 3898: case 0x19: { |
| 1935 | OPC_Decode, 199, 8, 63, // 3900: decode to VFCMP_SUNE_D using decoder 63 |
| 1936 | // 3900: } |
| 1937 | // 3900: } // switch Inst[19:15] |
| 1938 | // 3900: } |
| 1939 | 9, 135, 1, // 3904: case 0x9: { |
| 1940 | OPC_SwitchField, 15, 5, // 3907: switch Inst[19:15] { |
| 1941 | 0, 4, // 3910: case 0x0: { |
| 1942 | OPC_Decode, 223, 14, 64, // 3912: decode to XVFCMP_CAF_S using decoder 64 |
| 1943 | // 3912: } |
| 1944 | 1, 4, // 3916: case 0x1: { |
| 1945 | OPC_Decode, 245, 14, 64, // 3918: decode to XVFCMP_SAF_S using decoder 64 |
| 1946 | // 3918: } |
| 1947 | 2, 4, // 3922: case 0x2: { |
| 1948 | OPC_Decode, 229, 14, 64, // 3924: decode to XVFCMP_CLT_S using decoder 64 |
| 1949 | // 3924: } |
| 1950 | 3, 4, // 3928: case 0x3: { |
| 1951 | OPC_Decode, 251, 14, 64, // 3930: decode to XVFCMP_SLT_S using decoder 64 |
| 1952 | // 3930: } |
| 1953 | 4, 4, // 3934: case 0x4: { |
| 1954 | OPC_Decode, 225, 14, 64, // 3936: decode to XVFCMP_CEQ_S using decoder 64 |
| 1955 | // 3936: } |
| 1956 | 5, 4, // 3940: case 0x5: { |
| 1957 | OPC_Decode, 247, 14, 64, // 3942: decode to XVFCMP_SEQ_S using decoder 64 |
| 1958 | // 3942: } |
| 1959 | 6, 4, // 3946: case 0x6: { |
| 1960 | OPC_Decode, 227, 14, 64, // 3948: decode to XVFCMP_CLE_S using decoder 64 |
| 1961 | // 3948: } |
| 1962 | 7, 4, // 3952: case 0x7: { |
| 1963 | OPC_Decode, 249, 14, 64, // 3954: decode to XVFCMP_SLE_S using decoder 64 |
| 1964 | // 3954: } |
| 1965 | 8, 4, // 3958: case 0x8: { |
| 1966 | OPC_Decode, 243, 14, 64, // 3960: decode to XVFCMP_CUN_S using decoder 64 |
| 1967 | // 3960: } |
| 1968 | 9, 4, // 3964: case 0x9: { |
| 1969 | OPC_Decode, 137, 15, 64, // 3966: decode to XVFCMP_SUN_S using decoder 64 |
| 1970 | // 3966: } |
| 1971 | 10, 4, // 3970: case 0xa: { |
| 1972 | OPC_Decode, 239, 14, 64, // 3972: decode to XVFCMP_CULT_S using decoder 64 |
| 1973 | // 3972: } |
| 1974 | 11, 4, // 3976: case 0xb: { |
| 1975 | OPC_Decode, 133, 15, 64, // 3978: decode to XVFCMP_SULT_S using decoder 64 |
| 1976 | // 3978: } |
| 1977 | 12, 4, // 3982: case 0xc: { |
| 1978 | OPC_Decode, 235, 14, 64, // 3984: decode to XVFCMP_CUEQ_S using decoder 64 |
| 1979 | // 3984: } |
| 1980 | 13, 4, // 3988: case 0xd: { |
| 1981 | OPC_Decode, 129, 15, 64, // 3990: decode to XVFCMP_SUEQ_S using decoder 64 |
| 1982 | // 3990: } |
| 1983 | 14, 4, // 3994: case 0xe: { |
| 1984 | OPC_Decode, 237, 14, 64, // 3996: decode to XVFCMP_CULE_S using decoder 64 |
| 1985 | // 3996: } |
| 1986 | 15, 4, // 4000: case 0xf: { |
| 1987 | OPC_Decode, 131, 15, 64, // 4002: decode to XVFCMP_SULE_S using decoder 64 |
| 1988 | // 4002: } |
| 1989 | 16, 4, // 4006: case 0x10: { |
| 1990 | OPC_Decode, 231, 14, 64, // 4008: decode to XVFCMP_CNE_S using decoder 64 |
| 1991 | // 4008: } |
| 1992 | 17, 4, // 4012: case 0x11: { |
| 1993 | OPC_Decode, 253, 14, 64, // 4014: decode to XVFCMP_SNE_S using decoder 64 |
| 1994 | // 4014: } |
| 1995 | 20, 4, // 4018: case 0x14: { |
| 1996 | OPC_Decode, 233, 14, 64, // 4020: decode to XVFCMP_COR_S using decoder 64 |
| 1997 | // 4020: } |
| 1998 | 21, 4, // 4024: case 0x15: { |
| 1999 | OPC_Decode, 255, 14, 64, // 4026: decode to XVFCMP_SOR_S using decoder 64 |
| 2000 | // 4026: } |
| 2001 | 24, 4, // 4030: case 0x18: { |
| 2002 | OPC_Decode, 241, 14, 64, // 4032: decode to XVFCMP_CUNE_S using decoder 64 |
| 2003 | // 4032: } |
| 2004 | 25, 0, // 4036: case 0x19: { |
| 2005 | OPC_Decode, 135, 15, 64, // 4038: decode to XVFCMP_SUNE_S using decoder 64 |
| 2006 | // 4038: } |
| 2007 | // 4038: } // switch Inst[19:15] |
| 2008 | // 4038: } |
| 2009 | 10, 135, 1, // 4042: case 0xa: { |
| 2010 | OPC_SwitchField, 15, 5, // 4045: switch Inst[19:15] { |
| 2011 | 0, 4, // 4048: case 0x0: { |
| 2012 | OPC_Decode, 222, 14, 64, // 4050: decode to XVFCMP_CAF_D using decoder 64 |
| 2013 | // 4050: } |
| 2014 | 1, 4, // 4054: case 0x1: { |
| 2015 | OPC_Decode, 244, 14, 64, // 4056: decode to XVFCMP_SAF_D using decoder 64 |
| 2016 | // 4056: } |
| 2017 | 2, 4, // 4060: case 0x2: { |
| 2018 | OPC_Decode, 228, 14, 64, // 4062: decode to XVFCMP_CLT_D using decoder 64 |
| 2019 | // 4062: } |
| 2020 | 3, 4, // 4066: case 0x3: { |
| 2021 | OPC_Decode, 250, 14, 64, // 4068: decode to XVFCMP_SLT_D using decoder 64 |
| 2022 | // 4068: } |
| 2023 | 4, 4, // 4072: case 0x4: { |
| 2024 | OPC_Decode, 224, 14, 64, // 4074: decode to XVFCMP_CEQ_D using decoder 64 |
| 2025 | // 4074: } |
| 2026 | 5, 4, // 4078: case 0x5: { |
| 2027 | OPC_Decode, 246, 14, 64, // 4080: decode to XVFCMP_SEQ_D using decoder 64 |
| 2028 | // 4080: } |
| 2029 | 6, 4, // 4084: case 0x6: { |
| 2030 | OPC_Decode, 226, 14, 64, // 4086: decode to XVFCMP_CLE_D using decoder 64 |
| 2031 | // 4086: } |
| 2032 | 7, 4, // 4090: case 0x7: { |
| 2033 | OPC_Decode, 248, 14, 64, // 4092: decode to XVFCMP_SLE_D using decoder 64 |
| 2034 | // 4092: } |
| 2035 | 8, 4, // 4096: case 0x8: { |
| 2036 | OPC_Decode, 242, 14, 64, // 4098: decode to XVFCMP_CUN_D using decoder 64 |
| 2037 | // 4098: } |
| 2038 | 9, 4, // 4102: case 0x9: { |
| 2039 | OPC_Decode, 136, 15, 64, // 4104: decode to XVFCMP_SUN_D using decoder 64 |
| 2040 | // 4104: } |
| 2041 | 10, 4, // 4108: case 0xa: { |
| 2042 | OPC_Decode, 238, 14, 64, // 4110: decode to XVFCMP_CULT_D using decoder 64 |
| 2043 | // 4110: } |
| 2044 | 11, 4, // 4114: case 0xb: { |
| 2045 | OPC_Decode, 132, 15, 64, // 4116: decode to XVFCMP_SULT_D using decoder 64 |
| 2046 | // 4116: } |
| 2047 | 12, 4, // 4120: case 0xc: { |
| 2048 | OPC_Decode, 234, 14, 64, // 4122: decode to XVFCMP_CUEQ_D using decoder 64 |
| 2049 | // 4122: } |
| 2050 | 13, 4, // 4126: case 0xd: { |
| 2051 | OPC_Decode, 128, 15, 64, // 4128: decode to XVFCMP_SUEQ_D using decoder 64 |
| 2052 | // 4128: } |
| 2053 | 14, 4, // 4132: case 0xe: { |
| 2054 | OPC_Decode, 236, 14, 64, // 4134: decode to XVFCMP_CULE_D using decoder 64 |
| 2055 | // 4134: } |
| 2056 | 15, 4, // 4138: case 0xf: { |
| 2057 | OPC_Decode, 130, 15, 64, // 4140: decode to XVFCMP_SULE_D using decoder 64 |
| 2058 | // 4140: } |
| 2059 | 16, 4, // 4144: case 0x10: { |
| 2060 | OPC_Decode, 230, 14, 64, // 4146: decode to XVFCMP_CNE_D using decoder 64 |
| 2061 | // 4146: } |
| 2062 | 17, 4, // 4150: case 0x11: { |
| 2063 | OPC_Decode, 252, 14, 64, // 4152: decode to XVFCMP_SNE_D using decoder 64 |
| 2064 | // 4152: } |
| 2065 | 20, 4, // 4156: case 0x14: { |
| 2066 | OPC_Decode, 232, 14, 64, // 4158: decode to XVFCMP_COR_D using decoder 64 |
| 2067 | // 4158: } |
| 2068 | 21, 4, // 4162: case 0x15: { |
| 2069 | OPC_Decode, 254, 14, 64, // 4164: decode to XVFCMP_SOR_D using decoder 64 |
| 2070 | // 4164: } |
| 2071 | 24, 4, // 4168: case 0x18: { |
| 2072 | OPC_Decode, 240, 14, 64, // 4170: decode to XVFCMP_CUNE_D using decoder 64 |
| 2073 | // 4170: } |
| 2074 | 25, 0, // 4174: case 0x19: { |
| 2075 | OPC_Decode, 134, 15, 64, // 4176: decode to XVFCMP_SUNE_D using decoder 64 |
| 2076 | // 4176: } |
| 2077 | // 4176: } // switch Inst[19:15] |
| 2078 | // 4176: } |
| 2079 | 16, 8, // 4180: case 0x10: { |
| 2080 | OPC_CheckField, 18, 2, 0, // 4182: check Inst[19:18] == 0x0 |
| 2081 | OPC_Decode, 188, 5, 65, // 4186: decode to FSEL_xS using decoder 65 |
| 2082 | // 4186: } |
| 2083 | 17, 4, // 4190: case 0x11: { |
| 2084 | OPC_Decode, 230, 7, 59, // 4192: decode to VBITSEL_V using decoder 59 |
| 2085 | // 4192: } |
| 2086 | 18, 4, // 4196: case 0x12: { |
| 2087 | OPC_Decode, 177, 14, 60, // 4198: decode to XVBITSEL_V using decoder 60 |
| 2088 | // 4198: } |
| 2089 | 21, 4, // 4202: case 0x15: { |
| 2090 | OPC_Decode, 154, 11, 59, // 4204: decode to VSHUF_B using decoder 59 |
| 2091 | // 4204: } |
| 2092 | 22, 0, // 4208: case 0x16: { |
| 2093 | OPC_Decode, 224, 17, 60, // 4210: decode to XVSHUF_B using decoder 60 |
| 2094 | // 4210: } |
| 2095 | // 4210: } // switch Inst[25:20] |
| 2096 | // 4210: } |
| 2097 | 4, 6, // 4214: case 0x4: { |
| 2098 | OPC_CheckPredicate, 0, // 4216: check predicate 0 |
| 2099 | OPC_Decode, 198, 3, 66, // 4218: decode to ADDU16I_D using decoder 66 |
| 2100 | // 4218: } |
| 2101 | 5, 17, // 4222: case 0x5: { |
| 2102 | OPC_SwitchField, 25, 1, // 4224: switch Inst[25] { |
| 2103 | 0, 4, // 4227: case 0x0: { |
| 2104 | OPC_Decode, 146, 6, 67, // 4229: decode to LU12I_W using decoder 67 |
| 2105 | // 4229: } |
| 2106 | 1, 0, // 4233: case 0x1: { |
| 2107 | OPC_CheckPredicate, 0, // 4235: check predicate 0 |
| 2108 | OPC_Decode, 147, 6, 68, // 4237: decode to LU32I_D using decoder 68 |
| 2109 | // 4237: } |
| 2110 | // 4237: } // switch Inst[25] |
| 2111 | // 4237: } |
| 2112 | 6, 15, // 4241: case 0x6: { |
| 2113 | OPC_SwitchField, 25, 1, // 4243: switch Inst[25] { |
| 2114 | 0, 4, // 4246: case 0x0: { |
| 2115 | OPC_Decode, 183, 6, 67, // 4248: decode to PCADDI using decoder 67 |
| 2116 | // 4248: } |
| 2117 | 1, 0, // 4252: case 0x1: { |
| 2118 | OPC_Decode, 186, 6, 67, // 4254: decode to PCALAU12I using decoder 67 |
| 2119 | // 4254: } |
| 2120 | // 4254: } // switch Inst[25] |
| 2121 | // 4254: } |
| 2122 | 7, 17, // 4258: case 0x7: { |
| 2123 | OPC_SwitchField, 25, 1, // 4260: switch Inst[25] { |
| 2124 | 0, 4, // 4263: case 0x0: { |
| 2125 | OPC_Decode, 184, 6, 67, // 4265: decode to PCADDU12I using decoder 67 |
| 2126 | // 4265: } |
| 2127 | 1, 0, // 4269: case 0x1: { |
| 2128 | OPC_CheckPredicate, 0, // 4271: check predicate 0 |
| 2129 | OPC_Decode, 185, 6, 67, // 4273: decode to PCADDU18I using decoder 67 |
| 2130 | // 4273: } |
| 2131 | // 4273: } // switch Inst[25] |
| 2132 | // 4273: } |
| 2133 | 8, 31, // 4277: case 0x8: { |
| 2134 | OPC_SwitchField, 24, 2, // 4279: switch Inst[25:24] { |
| 2135 | 0, 4, // 4282: case 0x0: { |
| 2136 | OPC_Decode, 145, 6, 69, // 4284: decode to LL_W using decoder 69 |
| 2137 | // 4284: } |
| 2138 | 1, 4, // 4288: case 0x1: { |
| 2139 | OPC_Decode, 222, 6, 70, // 4290: decode to SC_W using decoder 70 |
| 2140 | // 4290: } |
| 2141 | 2, 6, // 4294: case 0x2: { |
| 2142 | OPC_CheckPredicate, 0, // 4296: check predicate 0 |
| 2143 | OPC_Decode, 144, 6, 69, // 4298: decode to LL_D using decoder 69 |
| 2144 | // 4298: } |
| 2145 | 3, 0, // 4302: case 0x3: { |
| 2146 | OPC_CheckPredicate, 0, // 4304: check predicate 0 |
| 2147 | OPC_Decode, 220, 6, 70, // 4306: decode to SC_D using decoder 70 |
| 2148 | // 4306: } |
| 2149 | // 4306: } // switch Inst[25:24] |
| 2150 | // 4306: } |
| 2151 | 9, 35, // 4310: case 0x9: { |
| 2152 | OPC_SwitchField, 24, 2, // 4312: switch Inst[25:24] { |
| 2153 | 0, 6, // 4315: case 0x0: { |
| 2154 | OPC_CheckPredicate, 0, // 4317: check predicate 0 |
| 2155 | OPC_Decode, 253, 5, 69, // 4319: decode to LDPTR_W using decoder 69 |
| 2156 | // 4319: } |
| 2157 | 1, 6, // 4323: case 0x1: { |
| 2158 | OPC_CheckPredicate, 0, // 4325: check predicate 0 |
| 2159 | OPC_Decode, 128, 7, 69, // 4327: decode to STPTR_W using decoder 69 |
| 2160 | // 4327: } |
| 2161 | 2, 6, // 4331: case 0x2: { |
| 2162 | OPC_CheckPredicate, 0, // 4333: check predicate 0 |
| 2163 | OPC_Decode, 252, 5, 69, // 4335: decode to LDPTR_D using decoder 69 |
| 2164 | // 4335: } |
| 2165 | 3, 0, // 4339: case 0x3: { |
| 2166 | OPC_CheckPredicate, 0, // 4341: check predicate 0 |
| 2167 | OPC_Decode, 255, 6, 69, // 4343: decode to STPTR_D using decoder 69 |
| 2168 | // 4343: } |
| 2169 | // 4343: } // switch Inst[25:24] |
| 2170 | // 4343: } |
| 2171 | 10, 105, // 4347: case 0xa: { |
| 2172 | OPC_SwitchField, 22, 4, // 4349: switch Inst[25:22] { |
| 2173 | 0, 4, // 4352: case 0x0: { |
| 2174 | OPC_Decode, 135, 6, 48, // 4354: decode to LD_B using decoder 48 |
| 2175 | // 4354: } |
| 2176 | 1, 4, // 4358: case 0x1: { |
| 2177 | OPC_Decode, 138, 6, 48, // 4360: decode to LD_H using decoder 48 |
| 2178 | // 4360: } |
| 2179 | 2, 4, // 4364: case 0x2: { |
| 2180 | OPC_Decode, 140, 6, 48, // 4366: decode to LD_W using decoder 48 |
| 2181 | // 4366: } |
| 2182 | 3, 6, // 4370: case 0x3: { |
| 2183 | OPC_CheckPredicate, 0, // 4372: check predicate 0 |
| 2184 | OPC_Decode, 137, 6, 48, // 4374: decode to LD_D using decoder 48 |
| 2185 | // 4374: } |
| 2186 | 4, 4, // 4378: case 0x4: { |
| 2187 | OPC_Decode, 135, 7, 48, // 4380: decode to ST_B using decoder 48 |
| 2188 | // 4380: } |
| 2189 | 5, 4, // 4384: case 0x5: { |
| 2190 | OPC_Decode, 137, 7, 48, // 4386: decode to ST_H using decoder 48 |
| 2191 | // 4386: } |
| 2192 | 6, 4, // 4390: case 0x6: { |
| 2193 | OPC_Decode, 138, 7, 48, // 4392: decode to ST_W using decoder 48 |
| 2194 | // 4392: } |
| 2195 | 7, 6, // 4396: case 0x7: { |
| 2196 | OPC_CheckPredicate, 0, // 4398: check predicate 0 |
| 2197 | OPC_Decode, 136, 7, 48, // 4400: decode to ST_D using decoder 48 |
| 2198 | // 4400: } |
| 2199 | 8, 4, // 4404: case 0x8: { |
| 2200 | OPC_Decode, 136, 6, 48, // 4406: decode to LD_BU using decoder 48 |
| 2201 | // 4406: } |
| 2202 | 9, 4, // 4410: case 0x9: { |
| 2203 | OPC_Decode, 139, 6, 48, // 4412: decode to LD_HU using decoder 48 |
| 2204 | // 4412: } |
| 2205 | 10, 6, // 4416: case 0xa: { |
| 2206 | OPC_CheckPredicate, 0, // 4418: check predicate 0 |
| 2207 | OPC_Decode, 141, 6, 48, // 4420: decode to LD_WU using decoder 48 |
| 2208 | // 4420: } |
| 2209 | 11, 4, // 4424: case 0xb: { |
| 2210 | OPC_Decode, 187, 6, 53, // 4426: decode to PRELD using decoder 53 |
| 2211 | // 4426: } |
| 2212 | 12, 4, // 4430: case 0xc: { |
| 2213 | OPC_Decode, 150, 5, 71, // 4432: decode to FLD_S using decoder 71 |
| 2214 | // 4432: } |
| 2215 | 13, 4, // 4436: case 0xd: { |
| 2216 | OPC_Decode, 198, 5, 71, // 4438: decode to FST_S using decoder 71 |
| 2217 | // 4438: } |
| 2218 | 14, 4, // 4442: case 0xe: { |
| 2219 | OPC_Decode, 149, 5, 72, // 4444: decode to FLD_D using decoder 72 |
| 2220 | // 4444: } |
| 2221 | 15, 0, // 4448: case 0xf: { |
| 2222 | OPC_Decode, 197, 5, 72, // 4450: decode to FST_D using decoder 72 |
| 2223 | // 4450: } |
| 2224 | // 4450: } // switch Inst[25:22] |
| 2225 | // 4450: } |
| 2226 | 11, 83, // 4454: case 0xb: { |
| 2227 | OPC_SwitchField, 22, 4, // 4456: switch Inst[25:22] { |
| 2228 | 0, 4, // 4459: case 0x0: { |
| 2229 | OPC_Decode, 193, 9, 73, // 4461: decode to VLD using decoder 73 |
| 2230 | // 4461: } |
| 2231 | 1, 4, // 4465: case 0x1: { |
| 2232 | OPC_Decode, 204, 12, 73, // 4467: decode to VST using decoder 73 |
| 2233 | // 4467: } |
| 2234 | 2, 4, // 4471: case 0x2: { |
| 2235 | OPC_Decode, 129, 16, 74, // 4473: decode to XVLD using decoder 74 |
| 2236 | // 4473: } |
| 2237 | 3, 4, // 4477: case 0x3: { |
| 2238 | OPC_Decode, 146, 19, 74, // 4479: decode to XVST using decoder 74 |
| 2239 | // 4479: } |
| 2240 | 8, 4, // 4483: case 0x8: { |
| 2241 | OPC_Decode, 250, 5, 48, // 4485: decode to LDL_W using decoder 48 |
| 2242 | // 4485: } |
| 2243 | 9, 4, // 4489: case 0x9: { |
| 2244 | OPC_Decode, 255, 5, 48, // 4491: decode to LDR_W using decoder 48 |
| 2245 | // 4491: } |
| 2246 | 10, 6, // 4495: case 0xa: { |
| 2247 | OPC_CheckPredicate, 0, // 4497: check predicate 0 |
| 2248 | OPC_Decode, 249, 5, 48, // 4499: decode to LDL_D using decoder 48 |
| 2249 | // 4499: } |
| 2250 | 11, 6, // 4503: case 0xb: { |
| 2251 | OPC_CheckPredicate, 0, // 4505: check predicate 0 |
| 2252 | OPC_Decode, 254, 5, 48, // 4507: decode to LDR_D using decoder 48 |
| 2253 | // 4507: } |
| 2254 | 12, 4, // 4511: case 0xc: { |
| 2255 | OPC_Decode, 254, 6, 48, // 4513: decode to STL_W using decoder 48 |
| 2256 | // 4513: } |
| 2257 | 13, 4, // 4517: case 0xd: { |
| 2258 | OPC_Decode, 130, 7, 48, // 4519: decode to STR_W using decoder 48 |
| 2259 | // 4519: } |
| 2260 | 14, 6, // 4523: case 0xe: { |
| 2261 | OPC_CheckPredicate, 0, // 4525: check predicate 0 |
| 2262 | OPC_Decode, 253, 6, 48, // 4527: decode to STL_D using decoder 48 |
| 2263 | // 4527: } |
| 2264 | 15, 0, // 4531: case 0xf: { |
| 2265 | OPC_CheckPredicate, 0, // 4533: check predicate 0 |
| 2266 | OPC_Decode, 129, 7, 48, // 4535: decode to STR_D using decoder 48 |
| 2267 | // 4535: } |
| 2268 | // 4535: } // switch Inst[25:22] |
| 2269 | // 4535: } |
| 2270 | 12, 164, 1, // 4539: case 0xc: { |
| 2271 | OPC_SwitchField, 23, 3, // 4542: switch Inst[25:23] { |
| 2272 | 0, 29, // 4545: case 0x0: { |
| 2273 | OPC_SwitchField, 21, 2, // 4547: switch Inst[22:21] { |
| 2274 | 0, 8, // 4550: case 0x0: { |
| 2275 | OPC_CheckField, 19, 2, 2, // 4552: check Inst[20:19] == 0x2 |
| 2276 | OPC_Decode, 196, 9, 75, // 4556: decode to VLDREPL_D using decoder 75 |
| 2277 | // 4556: } |
| 2278 | 1, 8, // 4560: case 0x1: { |
| 2279 | OPC_CheckField, 20, 1, 0, // 4562: check Inst[20] == 0x0 |
| 2280 | OPC_Decode, 198, 9, 76, // 4566: decode to VLDREPL_W using decoder 76 |
| 2281 | // 4566: } |
| 2282 | 2, 0, // 4570: case 0x2: { |
| 2283 | OPC_Decode, 197, 9, 77, // 4572: decode to VLDREPL_H using decoder 77 |
| 2284 | // 4572: } |
| 2285 | // 4572: } // switch Inst[22:21] |
| 2286 | // 4572: } |
| 2287 | 1, 8, // 4576: case 0x1: { |
| 2288 | OPC_CheckField, 22, 1, 0, // 4578: check Inst[22] == 0x0 |
| 2289 | OPC_Decode, 195, 9, 73, // 4582: decode to VLDREPL_B using decoder 73 |
| 2290 | // 4582: } |
| 2291 | 2, 29, // 4586: case 0x2: { |
| 2292 | OPC_SwitchField, 21, 2, // 4588: switch Inst[22:21] { |
| 2293 | 0, 8, // 4591: case 0x0: { |
| 2294 | OPC_CheckField, 19, 2, 2, // 4593: check Inst[20:19] == 0x2 |
| 2295 | OPC_Decode, 206, 12, 78, // 4597: decode to VSTELM_D using decoder 78 |
| 2296 | // 4597: } |
| 2297 | 1, 8, // 4601: case 0x1: { |
| 2298 | OPC_CheckField, 20, 1, 0, // 4603: check Inst[20] == 0x0 |
| 2299 | OPC_Decode, 208, 12, 79, // 4607: decode to VSTELM_W using decoder 79 |
| 2300 | // 4607: } |
| 2301 | 2, 0, // 4611: case 0x2: { |
| 2302 | OPC_Decode, 207, 12, 80, // 4613: decode to VSTELM_H using decoder 80 |
| 2303 | // 4613: } |
| 2304 | // 4613: } // switch Inst[22:21] |
| 2305 | // 4613: } |
| 2306 | 3, 8, // 4617: case 0x3: { |
| 2307 | OPC_CheckField, 22, 1, 0, // 4619: check Inst[22] == 0x0 |
| 2308 | OPC_Decode, 205, 12, 81, // 4623: decode to VSTELM_B using decoder 81 |
| 2309 | // 4623: } |
| 2310 | 4, 29, // 4627: case 0x4: { |
| 2311 | OPC_SwitchField, 21, 2, // 4629: switch Inst[22:21] { |
| 2312 | 0, 8, // 4632: case 0x0: { |
| 2313 | OPC_CheckField, 19, 2, 2, // 4634: check Inst[20:19] == 0x2 |
| 2314 | OPC_Decode, 132, 16, 82, // 4638: decode to XVLDREPL_D using decoder 82 |
| 2315 | // 4638: } |
| 2316 | 1, 8, // 4642: case 0x1: { |
| 2317 | OPC_CheckField, 20, 1, 0, // 4644: check Inst[20] == 0x0 |
| 2318 | OPC_Decode, 134, 16, 83, // 4648: decode to XVLDREPL_W using decoder 83 |
| 2319 | // 4648: } |
| 2320 | 2, 0, // 4652: case 0x2: { |
| 2321 | OPC_Decode, 133, 16, 84, // 4654: decode to XVLDREPL_H using decoder 84 |
| 2322 | // 4654: } |
| 2323 | // 4654: } // switch Inst[22:21] |
| 2324 | // 4654: } |
| 2325 | 5, 8, // 4658: case 0x5: { |
| 2326 | OPC_CheckField, 22, 1, 0, // 4660: check Inst[22] == 0x0 |
| 2327 | OPC_Decode, 131, 16, 74, // 4664: decode to XVLDREPL_B using decoder 74 |
| 2328 | // 4664: } |
| 2329 | 6, 30, // 4668: case 0x6: { |
| 2330 | OPC_SwitchField, 22, 1, // 4670: switch Inst[22] { |
| 2331 | 0, 19, // 4673: case 0x0: { |
| 2332 | OPC_SwitchField, 21, 1, // 4675: switch Inst[21] { |
| 2333 | 0, 8, // 4678: case 0x0: { |
| 2334 | OPC_CheckField, 20, 1, 1, // 4680: check Inst[20] == 0x1 |
| 2335 | OPC_Decode, 148, 19, 85, // 4684: decode to XVSTELM_D using decoder 85 |
| 2336 | // 4684: } |
| 2337 | 1, 0, // 4688: case 0x1: { |
| 2338 | OPC_Decode, 150, 19, 86, // 4690: decode to XVSTELM_W using decoder 86 |
| 2339 | // 4690: } |
| 2340 | // 4690: } // switch Inst[21] |
| 2341 | // 4690: } |
| 2342 | 1, 0, // 4694: case 0x1: { |
| 2343 | OPC_Decode, 149, 19, 87, // 4696: decode to XVSTELM_H using decoder 87 |
| 2344 | // 4696: } |
| 2345 | // 4696: } // switch Inst[22] |
| 2346 | // 4696: } |
| 2347 | 7, 0, // 4700: case 0x7: { |
| 2348 | OPC_Decode, 147, 19, 88, // 4702: decode to XVSTELM_B using decoder 88 |
| 2349 | // 4702: } |
| 2350 | // 4702: } // switch Inst[25:23] |
| 2351 | // 4702: } |
| 2352 | 14, 250, 6, // 4706: case 0xe: { |
| 2353 | OPC_SwitchField, 15, 11, // 4709: switch Inst[25:15] { |
| 2354 | 0, 6, // 4712: case 0x0: { |
| 2355 | OPC_CheckPredicate, 0, // 4714: check predicate 0 |
| 2356 | OPC_Decode, 128, 6, 11, // 4716: decode to LDX_B using decoder 11 |
| 2357 | // 4716: } |
| 2358 | 8, 6, // 4720: case 0x8: { |
| 2359 | OPC_CheckPredicate, 0, // 4722: check predicate 0 |
| 2360 | OPC_Decode, 131, 6, 11, // 4724: decode to LDX_H using decoder 11 |
| 2361 | // 4724: } |
| 2362 | 16, 6, // 4728: case 0x10: { |
| 2363 | OPC_CheckPredicate, 0, // 4730: check predicate 0 |
| 2364 | OPC_Decode, 133, 6, 11, // 4732: decode to LDX_W using decoder 11 |
| 2365 | // 4732: } |
| 2366 | 24, 6, // 4736: case 0x18: { |
| 2367 | OPC_CheckPredicate, 0, // 4738: check predicate 0 |
| 2368 | OPC_Decode, 130, 6, 11, // 4740: decode to LDX_D using decoder 11 |
| 2369 | // 4740: } |
| 2370 | 32, 6, // 4744: case 0x20: { |
| 2371 | OPC_CheckPredicate, 0, // 4746: check predicate 0 |
| 2372 | OPC_Decode, 131, 7, 11, // 4748: decode to STX_B using decoder 11 |
| 2373 | // 4748: } |
| 2374 | 40, 6, // 4752: case 0x28: { |
| 2375 | OPC_CheckPredicate, 0, // 4754: check predicate 0 |
| 2376 | OPC_Decode, 133, 7, 11, // 4756: decode to STX_H using decoder 11 |
| 2377 | // 4756: } |
| 2378 | 48, 6, // 4760: case 0x30: { |
| 2379 | OPC_CheckPredicate, 0, // 4762: check predicate 0 |
| 2380 | OPC_Decode, 134, 7, 11, // 4764: decode to STX_W using decoder 11 |
| 2381 | // 4764: } |
| 2382 | 56, 6, // 4768: case 0x38: { |
| 2383 | OPC_CheckPredicate, 0, // 4770: check predicate 0 |
| 2384 | OPC_Decode, 132, 7, 11, // 4772: decode to STX_D using decoder 11 |
| 2385 | // 4772: } |
| 2386 | 64, 6, // 4776: case 0x40: { |
| 2387 | OPC_CheckPredicate, 0, // 4778: check predicate 0 |
| 2388 | OPC_Decode, 129, 6, 11, // 4780: decode to LDX_BU using decoder 11 |
| 2389 | // 4780: } |
| 2390 | 72, 6, // 4784: case 0x48: { |
| 2391 | OPC_CheckPredicate, 0, // 4786: check predicate 0 |
| 2392 | OPC_Decode, 132, 6, 11, // 4788: decode to LDX_HU using decoder 11 |
| 2393 | // 4788: } |
| 2394 | 80, 6, // 4792: case 0x50: { |
| 2395 | OPC_CheckPredicate, 0, // 4794: check predicate 0 |
| 2396 | OPC_Decode, 134, 6, 11, // 4796: decode to LDX_WU using decoder 11 |
| 2397 | // 4796: } |
| 2398 | 88, 6, // 4800: case 0x58: { |
| 2399 | OPC_CheckPredicate, 0, // 4802: check predicate 0 |
| 2400 | OPC_Decode, 188, 6, 89, // 4804: decode to PRELDX using decoder 89 |
| 2401 | // 4804: } |
| 2402 | 96, 4, // 4808: case 0x60: { |
| 2403 | OPC_Decode, 148, 5, 90, // 4810: decode to FLDX_S using decoder 90 |
| 2404 | // 4810: } |
| 2405 | 104, 4, // 4814: case 0x68: { |
| 2406 | OPC_Decode, 147, 5, 91, // 4816: decode to FLDX_D using decoder 91 |
| 2407 | // 4816: } |
| 2408 | 112, 4, // 4820: case 0x70: { |
| 2409 | OPC_Decode, 196, 5, 90, // 4822: decode to FSTX_S using decoder 90 |
| 2410 | // 4822: } |
| 2411 | 120, 4, // 4826: case 0x78: { |
| 2412 | OPC_Decode, 195, 5, 91, // 4828: decode to FSTX_D using decoder 91 |
| 2413 | // 4828: } |
| 2414 | 128, 1, 4, // 4832: case 0x80: { |
| 2415 | OPC_Decode, 199, 9, 92, // 4835: decode to VLDX using decoder 92 |
| 2416 | // 4835: } |
| 2417 | 136, 1, 4, // 4839: case 0x88: { |
| 2418 | OPC_Decode, 209, 12, 92, // 4842: decode to VSTX using decoder 92 |
| 2419 | // 4842: } |
| 2420 | 144, 1, 4, // 4846: case 0x90: { |
| 2421 | OPC_Decode, 135, 16, 93, // 4849: decode to XVLDX using decoder 93 |
| 2422 | // 4849: } |
| 2423 | 152, 1, 4, // 4853: case 0x98: { |
| 2424 | OPC_Decode, 151, 19, 93, // 4856: decode to XVSTX using decoder 93 |
| 2425 | // 4856: } |
| 2426 | 174, 1, 6, // 4860: case 0xae: { |
| 2427 | OPC_CheckPredicate, 0, // 4863: check predicate 0 |
| 2428 | OPC_Decode, 221, 6, 94, // 4865: decode to SC_Q using decoder 94 |
| 2429 | // 4865: } |
| 2430 | 175, 1, 35, // 4869: case 0xaf: { |
| 2431 | OPC_SwitchField, 10, 5, // 4872: switch Inst[14:10] { |
| 2432 | 0, 6, // 4875: case 0x0: { |
| 2433 | OPC_CheckPredicate, 0, // 4877: check predicate 0 |
| 2434 | OPC_Decode, 143, 6, 2, // 4879: decode to LLACQ_W using decoder 2 |
| 2435 | // 4879: } |
| 2436 | 1, 6, // 4883: case 0x1: { |
| 2437 | OPC_CheckPredicate, 0, // 4885: check predicate 0 |
| 2438 | OPC_Decode, 219, 6, 95, // 4887: decode to SCREL_W using decoder 95 |
| 2439 | // 4887: } |
| 2440 | 2, 6, // 4891: case 0x2: { |
| 2441 | OPC_CheckPredicate, 0, // 4893: check predicate 0 |
| 2442 | OPC_Decode, 142, 6, 2, // 4895: decode to LLACQ_D using decoder 2 |
| 2443 | // 4895: } |
| 2444 | 3, 0, // 4899: case 0x3: { |
| 2445 | OPC_CheckPredicate, 0, // 4901: check predicate 0 |
| 2446 | OPC_Decode, 218, 6, 95, // 4903: decode to SCREL_D using decoder 95 |
| 2447 | // 4903: } |
| 2448 | // 4903: } // switch Inst[14:10] |
| 2449 | // 4903: } |
| 2450 | 176, 1, 6, // 4907: case 0xb0: { |
| 2451 | OPC_CheckPredicate, 0, // 4910: check predicate 0 |
| 2452 | OPC_Decode, 216, 3, 94, // 4912: decode to AMCAS_B using decoder 94 |
| 2453 | // 4912: } |
| 2454 | 177, 1, 6, // 4916: case 0xb1: { |
| 2455 | OPC_CheckPredicate, 0, // 4919: check predicate 0 |
| 2456 | OPC_Decode, 218, 3, 94, // 4921: decode to AMCAS_H using decoder 94 |
| 2457 | // 4921: } |
| 2458 | 178, 1, 6, // 4925: case 0xb2: { |
| 2459 | OPC_CheckPredicate, 0, // 4928: check predicate 0 |
| 2460 | OPC_Decode, 219, 3, 94, // 4930: decode to AMCAS_W using decoder 94 |
| 2461 | // 4930: } |
| 2462 | 179, 1, 6, // 4934: case 0xb3: { |
| 2463 | OPC_CheckPredicate, 0, // 4937: check predicate 0 |
| 2464 | OPC_Decode, 217, 3, 94, // 4939: decode to AMCAS_D using decoder 94 |
| 2465 | // 4939: } |
| 2466 | 180, 1, 6, // 4943: case 0xb4: { |
| 2467 | OPC_CheckPredicate, 0, // 4946: check predicate 0 |
| 2468 | OPC_Decode, 220, 3, 94, // 4948: decode to AMCAS__DB_B using decoder 94 |
| 2469 | // 4948: } |
| 2470 | 181, 1, 6, // 4952: case 0xb5: { |
| 2471 | OPC_CheckPredicate, 0, // 4955: check predicate 0 |
| 2472 | OPC_Decode, 222, 3, 94, // 4957: decode to AMCAS__DB_H using decoder 94 |
| 2473 | // 4957: } |
| 2474 | 182, 1, 6, // 4961: case 0xb6: { |
| 2475 | OPC_CheckPredicate, 0, // 4964: check predicate 0 |
| 2476 | OPC_Decode, 223, 3, 94, // 4966: decode to AMCAS__DB_W using decoder 94 |
| 2477 | // 4966: } |
| 2478 | 183, 1, 6, // 4970: case 0xb7: { |
| 2479 | OPC_CheckPredicate, 0, // 4973: check predicate 0 |
| 2480 | OPC_Decode, 221, 3, 94, // 4975: decode to AMCAS__DB_D using decoder 94 |
| 2481 | // 4975: } |
| 2482 | 184, 1, 6, // 4979: case 0xb8: { |
| 2483 | OPC_CheckPredicate, 0, // 4982: check predicate 0 |
| 2484 | OPC_Decode, 244, 3, 96, // 4984: decode to AMSWAP_B using decoder 96 |
| 2485 | // 4984: } |
| 2486 | 185, 1, 6, // 4988: case 0xb9: { |
| 2487 | OPC_CheckPredicate, 0, // 4991: check predicate 0 |
| 2488 | OPC_Decode, 246, 3, 96, // 4993: decode to AMSWAP_H using decoder 96 |
| 2489 | // 4993: } |
| 2490 | 186, 1, 6, // 4997: case 0xba: { |
| 2491 | OPC_CheckPredicate, 0, // 5000: check predicate 0 |
| 2492 | OPC_Decode, 204, 3, 96, // 5002: decode to AMADD_B using decoder 96 |
| 2493 | // 5002: } |
| 2494 | 187, 1, 6, // 5006: case 0xbb: { |
| 2495 | OPC_CheckPredicate, 0, // 5009: check predicate 0 |
| 2496 | OPC_Decode, 206, 3, 96, // 5011: decode to AMADD_H using decoder 96 |
| 2497 | // 5011: } |
| 2498 | 188, 1, 6, // 5015: case 0xbc: { |
| 2499 | OPC_CheckPredicate, 0, // 5018: check predicate 0 |
| 2500 | OPC_Decode, 248, 3, 96, // 5020: decode to AMSWAP__DB_B using decoder 96 |
| 2501 | // 5020: } |
| 2502 | 189, 1, 6, // 5024: case 0xbd: { |
| 2503 | OPC_CheckPredicate, 0, // 5027: check predicate 0 |
| 2504 | OPC_Decode, 250, 3, 96, // 5029: decode to AMSWAP__DB_H using decoder 96 |
| 2505 | // 5029: } |
| 2506 | 190, 1, 6, // 5033: case 0xbe: { |
| 2507 | OPC_CheckPredicate, 0, // 5036: check predicate 0 |
| 2508 | OPC_Decode, 208, 3, 96, // 5038: decode to AMADD__DB_B using decoder 96 |
| 2509 | // 5038: } |
| 2510 | 191, 1, 6, // 5042: case 0xbf: { |
| 2511 | OPC_CheckPredicate, 0, // 5045: check predicate 0 |
| 2512 | OPC_Decode, 210, 3, 96, // 5047: decode to AMADD__DB_H using decoder 96 |
| 2513 | // 5047: } |
| 2514 | 192, 1, 16, // 5051: case 0xc0: { |
| 2515 | OPC_Scope, 8, // 5054: try { |
| 2516 | OPC_CheckField, 10, 5, 1, // 5056: check Inst[14:10] == 0x1 |
| 2517 | OPC_Decode, 148, 7, 97, // 5060: decode to UD using decoder 97 |
| 2518 | // 5060: } else try { |
| 2519 | OPC_CheckPredicate, 0, // 5064: check predicate 0 |
| 2520 | OPC_Decode, 247, 3, 97, // 5066: decode to AMSWAP_W using decoder 97 |
| 2521 | // 5066: } |
| 2522 | // 5066: } |
| 2523 | 193, 1, 6, // 5070: case 0xc1: { |
| 2524 | OPC_CheckPredicate, 0, // 5073: check predicate 0 |
| 2525 | OPC_Decode, 245, 3, 96, // 5075: decode to AMSWAP_D using decoder 96 |
| 2526 | // 5075: } |
| 2527 | 194, 1, 6, // 5079: case 0xc2: { |
| 2528 | OPC_CheckPredicate, 0, // 5082: check predicate 0 |
| 2529 | OPC_Decode, 207, 3, 96, // 5084: decode to AMADD_W using decoder 96 |
| 2530 | // 5084: } |
| 2531 | 195, 1, 6, // 5088: case 0xc3: { |
| 2532 | OPC_CheckPredicate, 0, // 5091: check predicate 0 |
| 2533 | OPC_Decode, 205, 3, 96, // 5093: decode to AMADD_D using decoder 96 |
| 2534 | // 5093: } |
| 2535 | 196, 1, 6, // 5097: case 0xc4: { |
| 2536 | OPC_CheckPredicate, 0, // 5100: check predicate 0 |
| 2537 | OPC_Decode, 213, 3, 96, // 5102: decode to AMAND_W using decoder 96 |
| 2538 | // 5102: } |
| 2539 | 197, 1, 6, // 5106: case 0xc5: { |
| 2540 | OPC_CheckPredicate, 0, // 5109: check predicate 0 |
| 2541 | OPC_Decode, 212, 3, 96, // 5111: decode to AMAND_D using decoder 96 |
| 2542 | // 5111: } |
| 2543 | 198, 1, 6, // 5115: case 0xc6: { |
| 2544 | OPC_CheckPredicate, 0, // 5118: check predicate 0 |
| 2545 | OPC_Decode, 241, 3, 96, // 5120: decode to AMOR_W using decoder 96 |
| 2546 | // 5120: } |
| 2547 | 199, 1, 6, // 5124: case 0xc7: { |
| 2548 | OPC_CheckPredicate, 0, // 5127: check predicate 0 |
| 2549 | OPC_Decode, 240, 3, 96, // 5129: decode to AMOR_D using decoder 96 |
| 2550 | // 5129: } |
| 2551 | 200, 1, 6, // 5133: case 0xc8: { |
| 2552 | OPC_CheckPredicate, 0, // 5136: check predicate 0 |
| 2553 | OPC_Decode, 253, 3, 96, // 5138: decode to AMXOR_W using decoder 96 |
| 2554 | // 5138: } |
| 2555 | 201, 1, 6, // 5142: case 0xc9: { |
| 2556 | OPC_CheckPredicate, 0, // 5145: check predicate 0 |
| 2557 | OPC_Decode, 252, 3, 96, // 5147: decode to AMXOR_D using decoder 96 |
| 2558 | // 5147: } |
| 2559 | 202, 1, 6, // 5151: case 0xca: { |
| 2560 | OPC_CheckPredicate, 0, // 5154: check predicate 0 |
| 2561 | OPC_Decode, 226, 3, 96, // 5156: decode to AMMAX_W using decoder 96 |
| 2562 | // 5156: } |
| 2563 | 203, 1, 6, // 5160: case 0xcb: { |
| 2564 | OPC_CheckPredicate, 0, // 5163: check predicate 0 |
| 2565 | OPC_Decode, 224, 3, 96, // 5165: decode to AMMAX_D using decoder 96 |
| 2566 | // 5165: } |
| 2567 | 204, 1, 6, // 5169: case 0xcc: { |
| 2568 | OPC_CheckPredicate, 0, // 5172: check predicate 0 |
| 2569 | OPC_Decode, 234, 3, 96, // 5174: decode to AMMIN_W using decoder 96 |
| 2570 | // 5174: } |
| 2571 | 205, 1, 6, // 5178: case 0xcd: { |
| 2572 | OPC_CheckPredicate, 0, // 5181: check predicate 0 |
| 2573 | OPC_Decode, 232, 3, 96, // 5183: decode to AMMIN_D using decoder 96 |
| 2574 | // 5183: } |
| 2575 | 206, 1, 6, // 5187: case 0xce: { |
| 2576 | OPC_CheckPredicate, 0, // 5190: check predicate 0 |
| 2577 | OPC_Decode, 227, 3, 96, // 5192: decode to AMMAX_WU using decoder 96 |
| 2578 | // 5192: } |
| 2579 | 207, 1, 6, // 5196: case 0xcf: { |
| 2580 | OPC_CheckPredicate, 0, // 5199: check predicate 0 |
| 2581 | OPC_Decode, 225, 3, 96, // 5201: decode to AMMAX_DU using decoder 96 |
| 2582 | // 5201: } |
| 2583 | 208, 1, 6, // 5205: case 0xd0: { |
| 2584 | OPC_CheckPredicate, 0, // 5208: check predicate 0 |
| 2585 | OPC_Decode, 235, 3, 96, // 5210: decode to AMMIN_WU using decoder 96 |
| 2586 | // 5210: } |
| 2587 | 209, 1, 6, // 5214: case 0xd1: { |
| 2588 | OPC_CheckPredicate, 0, // 5217: check predicate 0 |
| 2589 | OPC_Decode, 233, 3, 96, // 5219: decode to AMMIN_DU using decoder 96 |
| 2590 | // 5219: } |
| 2591 | 210, 1, 6, // 5223: case 0xd2: { |
| 2592 | OPC_CheckPredicate, 0, // 5226: check predicate 0 |
| 2593 | OPC_Decode, 251, 3, 96, // 5228: decode to AMSWAP__DB_W using decoder 96 |
| 2594 | // 5228: } |
| 2595 | 211, 1, 6, // 5232: case 0xd3: { |
| 2596 | OPC_CheckPredicate, 0, // 5235: check predicate 0 |
| 2597 | OPC_Decode, 249, 3, 96, // 5237: decode to AMSWAP__DB_D using decoder 96 |
| 2598 | // 5237: } |
| 2599 | 212, 1, 6, // 5241: case 0xd4: { |
| 2600 | OPC_CheckPredicate, 0, // 5244: check predicate 0 |
| 2601 | OPC_Decode, 211, 3, 96, // 5246: decode to AMADD__DB_W using decoder 96 |
| 2602 | // 5246: } |
| 2603 | 213, 1, 6, // 5250: case 0xd5: { |
| 2604 | OPC_CheckPredicate, 0, // 5253: check predicate 0 |
| 2605 | OPC_Decode, 209, 3, 96, // 5255: decode to AMADD__DB_D using decoder 96 |
| 2606 | // 5255: } |
| 2607 | 214, 1, 6, // 5259: case 0xd6: { |
| 2608 | OPC_CheckPredicate, 0, // 5262: check predicate 0 |
| 2609 | OPC_Decode, 215, 3, 96, // 5264: decode to AMAND__DB_W using decoder 96 |
| 2610 | // 5264: } |
| 2611 | 215, 1, 6, // 5268: case 0xd7: { |
| 2612 | OPC_CheckPredicate, 0, // 5271: check predicate 0 |
| 2613 | OPC_Decode, 214, 3, 96, // 5273: decode to AMAND__DB_D using decoder 96 |
| 2614 | // 5273: } |
| 2615 | 216, 1, 6, // 5277: case 0xd8: { |
| 2616 | OPC_CheckPredicate, 0, // 5280: check predicate 0 |
| 2617 | OPC_Decode, 243, 3, 96, // 5282: decode to AMOR__DB_W using decoder 96 |
| 2618 | // 5282: } |
| 2619 | 217, 1, 6, // 5286: case 0xd9: { |
| 2620 | OPC_CheckPredicate, 0, // 5289: check predicate 0 |
| 2621 | OPC_Decode, 242, 3, 96, // 5291: decode to AMOR__DB_D using decoder 96 |
| 2622 | // 5291: } |
| 2623 | 218, 1, 6, // 5295: case 0xda: { |
| 2624 | OPC_CheckPredicate, 0, // 5298: check predicate 0 |
| 2625 | OPC_Decode, 255, 3, 96, // 5300: decode to AMXOR__DB_W using decoder 96 |
| 2626 | // 5300: } |
| 2627 | 219, 1, 6, // 5304: case 0xdb: { |
| 2628 | OPC_CheckPredicate, 0, // 5307: check predicate 0 |
| 2629 | OPC_Decode, 254, 3, 96, // 5309: decode to AMXOR__DB_D using decoder 96 |
| 2630 | // 5309: } |
| 2631 | 220, 1, 6, // 5313: case 0xdc: { |
| 2632 | OPC_CheckPredicate, 0, // 5316: check predicate 0 |
| 2633 | OPC_Decode, 230, 3, 96, // 5318: decode to AMMAX__DB_W using decoder 96 |
| 2634 | // 5318: } |
| 2635 | 221, 1, 6, // 5322: case 0xdd: { |
| 2636 | OPC_CheckPredicate, 0, // 5325: check predicate 0 |
| 2637 | OPC_Decode, 228, 3, 96, // 5327: decode to AMMAX__DB_D using decoder 96 |
| 2638 | // 5327: } |
| 2639 | 222, 1, 6, // 5331: case 0xde: { |
| 2640 | OPC_CheckPredicate, 0, // 5334: check predicate 0 |
| 2641 | OPC_Decode, 238, 3, 96, // 5336: decode to AMMIN__DB_W using decoder 96 |
| 2642 | // 5336: } |
| 2643 | 223, 1, 6, // 5340: case 0xdf: { |
| 2644 | OPC_CheckPredicate, 0, // 5343: check predicate 0 |
| 2645 | OPC_Decode, 236, 3, 96, // 5345: decode to AMMIN__DB_D using decoder 96 |
| 2646 | // 5345: } |
| 2647 | 224, 1, 6, // 5349: case 0xe0: { |
| 2648 | OPC_CheckPredicate, 0, // 5352: check predicate 0 |
| 2649 | OPC_Decode, 231, 3, 96, // 5354: decode to AMMAX__DB_WU using decoder 96 |
| 2650 | // 5354: } |
| 2651 | 225, 1, 6, // 5358: case 0xe1: { |
| 2652 | OPC_CheckPredicate, 0, // 5361: check predicate 0 |
| 2653 | OPC_Decode, 229, 3, 96, // 5363: decode to AMMAX__DB_DU using decoder 96 |
| 2654 | // 5363: } |
| 2655 | 226, 1, 6, // 5367: case 0xe2: { |
| 2656 | OPC_CheckPredicate, 0, // 5370: check predicate 0 |
| 2657 | OPC_Decode, 239, 3, 96, // 5372: decode to AMMIN__DB_WU using decoder 96 |
| 2658 | // 5372: } |
| 2659 | 227, 1, 6, // 5376: case 0xe3: { |
| 2660 | OPC_CheckPredicate, 0, // 5379: check predicate 0 |
| 2661 | OPC_Decode, 237, 3, 96, // 5381: decode to AMMIN__DB_DU using decoder 96 |
| 2662 | // 5381: } |
| 2663 | 228, 1, 4, // 5385: case 0xe4: { |
| 2664 | OPC_Decode, 199, 4, 13, // 5388: decode to DBAR using decoder 13 |
| 2665 | // 5388: } |
| 2666 | 229, 1, 4, // 5392: case 0xe5: { |
| 2667 | OPC_Decode, 226, 5, 13, // 5395: decode to IBAR using decoder 13 |
| 2668 | // 5395: } |
| 2669 | 232, 1, 4, // 5399: case 0xe8: { |
| 2670 | OPC_Decode, 144, 5, 90, // 5402: decode to FLDGT_S using decoder 90 |
| 2671 | // 5402: } |
| 2672 | 233, 1, 4, // 5406: case 0xe9: { |
| 2673 | OPC_Decode, 143, 5, 91, // 5409: decode to FLDGT_D using decoder 91 |
| 2674 | // 5409: } |
| 2675 | 234, 1, 4, // 5413: case 0xea: { |
| 2676 | OPC_Decode, 146, 5, 90, // 5416: decode to FLDLE_S using decoder 90 |
| 2677 | // 5416: } |
| 2678 | 235, 1, 4, // 5420: case 0xeb: { |
| 2679 | OPC_Decode, 145, 5, 91, // 5423: decode to FLDLE_D using decoder 91 |
| 2680 | // 5423: } |
| 2681 | 236, 1, 4, // 5427: case 0xec: { |
| 2682 | OPC_Decode, 192, 5, 90, // 5430: decode to FSTGT_S using decoder 90 |
| 2683 | // 5430: } |
| 2684 | 237, 1, 4, // 5434: case 0xed: { |
| 2685 | OPC_Decode, 191, 5, 91, // 5437: decode to FSTGT_D using decoder 91 |
| 2686 | // 5437: } |
| 2687 | 238, 1, 4, // 5441: case 0xee: { |
| 2688 | OPC_Decode, 194, 5, 90, // 5444: decode to FSTLE_S using decoder 90 |
| 2689 | // 5444: } |
| 2690 | 239, 1, 4, // 5448: case 0xef: { |
| 2691 | OPC_Decode, 193, 5, 91, // 5451: decode to FSTLE_D using decoder 91 |
| 2692 | // 5451: } |
| 2693 | 240, 1, 6, // 5455: case 0xf0: { |
| 2694 | OPC_CheckPredicate, 0, // 5458: check predicate 0 |
| 2695 | OPC_Decode, 241, 5, 11, // 5460: decode to LDGT_B using decoder 11 |
| 2696 | // 5460: } |
| 2697 | 241, 1, 6, // 5464: case 0xf1: { |
| 2698 | OPC_CheckPredicate, 0, // 5467: check predicate 0 |
| 2699 | OPC_Decode, 243, 5, 11, // 5469: decode to LDGT_H using decoder 11 |
| 2700 | // 5469: } |
| 2701 | 242, 1, 6, // 5473: case 0xf2: { |
| 2702 | OPC_CheckPredicate, 0, // 5476: check predicate 0 |
| 2703 | OPC_Decode, 244, 5, 11, // 5478: decode to LDGT_W using decoder 11 |
| 2704 | // 5478: } |
| 2705 | 243, 1, 6, // 5482: case 0xf3: { |
| 2706 | OPC_CheckPredicate, 0, // 5485: check predicate 0 |
| 2707 | OPC_Decode, 242, 5, 11, // 5487: decode to LDGT_D using decoder 11 |
| 2708 | // 5487: } |
| 2709 | 244, 1, 6, // 5491: case 0xf4: { |
| 2710 | OPC_CheckPredicate, 0, // 5494: check predicate 0 |
| 2711 | OPC_Decode, 245, 5, 11, // 5496: decode to LDLE_B using decoder 11 |
| 2712 | // 5496: } |
| 2713 | 245, 1, 6, // 5500: case 0xf5: { |
| 2714 | OPC_CheckPredicate, 0, // 5503: check predicate 0 |
| 2715 | OPC_Decode, 247, 5, 11, // 5505: decode to LDLE_H using decoder 11 |
| 2716 | // 5505: } |
| 2717 | 246, 1, 6, // 5509: case 0xf6: { |
| 2718 | OPC_CheckPredicate, 0, // 5512: check predicate 0 |
| 2719 | OPC_Decode, 248, 5, 11, // 5514: decode to LDLE_W using decoder 11 |
| 2720 | // 5514: } |
| 2721 | 247, 1, 6, // 5518: case 0xf7: { |
| 2722 | OPC_CheckPredicate, 0, // 5521: check predicate 0 |
| 2723 | OPC_Decode, 246, 5, 11, // 5523: decode to LDLE_D using decoder 11 |
| 2724 | // 5523: } |
| 2725 | 248, 1, 6, // 5527: case 0xf8: { |
| 2726 | OPC_CheckPredicate, 0, // 5530: check predicate 0 |
| 2727 | OPC_Decode, 245, 6, 11, // 5532: decode to STGT_B using decoder 11 |
| 2728 | // 5532: } |
| 2729 | 249, 1, 6, // 5536: case 0xf9: { |
| 2730 | OPC_CheckPredicate, 0, // 5539: check predicate 0 |
| 2731 | OPC_Decode, 247, 6, 11, // 5541: decode to STGT_H using decoder 11 |
| 2732 | // 5541: } |
| 2733 | 250, 1, 6, // 5545: case 0xfa: { |
| 2734 | OPC_CheckPredicate, 0, // 5548: check predicate 0 |
| 2735 | OPC_Decode, 248, 6, 11, // 5550: decode to STGT_W using decoder 11 |
| 2736 | // 5550: } |
| 2737 | 251, 1, 6, // 5554: case 0xfb: { |
| 2738 | OPC_CheckPredicate, 0, // 5557: check predicate 0 |
| 2739 | OPC_Decode, 246, 6, 11, // 5559: decode to STGT_D using decoder 11 |
| 2740 | // 5559: } |
| 2741 | 252, 1, 6, // 5563: case 0xfc: { |
| 2742 | OPC_CheckPredicate, 0, // 5566: check predicate 0 |
| 2743 | OPC_Decode, 249, 6, 11, // 5568: decode to STLE_B using decoder 11 |
| 2744 | // 5568: } |
| 2745 | 253, 1, 6, // 5572: case 0xfd: { |
| 2746 | OPC_CheckPredicate, 0, // 5575: check predicate 0 |
| 2747 | OPC_Decode, 251, 6, 11, // 5577: decode to STLE_H using decoder 11 |
| 2748 | // 5577: } |
| 2749 | 254, 1, 6, // 5581: case 0xfe: { |
| 2750 | OPC_CheckPredicate, 0, // 5584: check predicate 0 |
| 2751 | OPC_Decode, 252, 6, 11, // 5586: decode to STLE_W using decoder 11 |
| 2752 | // 5586: } |
| 2753 | 255, 1, 0, // 5590: case 0xff: { |
| 2754 | OPC_CheckPredicate, 0, // 5593: check predicate 0 |
| 2755 | OPC_Decode, 250, 6, 11, // 5595: decode to STLE_D using decoder 11 |
| 2756 | // 5595: } |
| 2757 | // 5595: } // switch Inst[25:15] |
| 2758 | // 5595: } |
| 2759 | 16, 4, // 5599: case 0x10: { |
| 2760 | OPC_Decode, 159, 4, 98, // 5601: decode to BEQZ using decoder 98 |
| 2761 | // 5601: } |
| 2762 | 17, 4, // 5605: case 0x11: { |
| 2763 | OPC_Decode, 170, 4, 98, // 5607: decode to BNEZ using decoder 98 |
| 2764 | // 5607: } |
| 2765 | 18, 35, // 5611: case 0x12: { |
| 2766 | OPC_SwitchField, 8, 2, // 5613: switch Inst[9:8] { |
| 2767 | 0, 4, // 5616: case 0x0: { |
| 2768 | OPC_Decode, 156, 4, 99, // 5618: decode to BCEQZ using decoder 99 |
| 2769 | // 5618: } |
| 2770 | 1, 4, // 5622: case 0x1: { |
| 2771 | OPC_Decode, 157, 4, 99, // 5624: decode to BCNEZ using decoder 99 |
| 2772 | // 5624: } |
| 2773 | 2, 8, // 5628: case 0x2: { |
| 2774 | OPC_CheckField, 5, 3, 0, // 5630: check Inst[7:5] == 0x0 |
| 2775 | OPC_Decode, 238, 5, 100, // 5634: decode to JISCR0 using decoder 100 |
| 2776 | // 5634: } |
| 2777 | 3, 0, // 5638: case 0x3: { |
| 2778 | OPC_CheckField, 5, 3, 0, // 5640: check Inst[7:5] == 0x0 |
| 2779 | OPC_Decode, 239, 5, 100, // 5644: decode to JISCR1 using decoder 100 |
| 2780 | // 5644: } |
| 2781 | // 5644: } // switch Inst[9:8] |
| 2782 | // 5644: } |
| 2783 | 19, 4, // 5648: case 0x13: { |
| 2784 | OPC_Decode, 237, 5, 101, // 5650: decode to JIRL using decoder 101 |
| 2785 | // 5650: } |
| 2786 | 20, 4, // 5654: case 0x14: { |
| 2787 | OPC_Decode, 155, 4, 102, // 5656: decode to B using decoder 102 |
| 2788 | // 5656: } |
| 2789 | 21, 4, // 5660: case 0x15: { |
| 2790 | OPC_Decode, 166, 4, 102, // 5662: decode to BL using decoder 102 |
| 2791 | // 5662: } |
| 2792 | 22, 4, // 5666: case 0x16: { |
| 2793 | OPC_Decode, 158, 4, 103, // 5668: decode to BEQ using decoder 103 |
| 2794 | // 5668: } |
| 2795 | 23, 4, // 5672: case 0x17: { |
| 2796 | OPC_Decode, 169, 4, 103, // 5674: decode to BNE using decoder 103 |
| 2797 | // 5674: } |
| 2798 | 24, 4, // 5678: case 0x18: { |
| 2799 | OPC_Decode, 167, 4, 103, // 5680: decode to BLT using decoder 103 |
| 2800 | // 5680: } |
| 2801 | 25, 4, // 5684: case 0x19: { |
| 2802 | OPC_Decode, 160, 4, 103, // 5686: decode to BGE using decoder 103 |
| 2803 | // 5686: } |
| 2804 | 26, 4, // 5690: case 0x1a: { |
| 2805 | OPC_Decode, 168, 4, 103, // 5692: decode to BLTU using decoder 103 |
| 2806 | // 5692: } |
| 2807 | 27, 4, // 5696: case 0x1b: { |
| 2808 | OPC_Decode, 161, 4, 103, // 5698: decode to BGEU using decoder 103 |
| 2809 | // 5698: } |
| 2810 | 28, 201, 38, // 5702: case 0x1c: { |
| 2811 | OPC_SwitchField, 18, 8, // 5705: switch Inst[25:18] { |
| 2812 | 0, 51, // 5708: case 0x0: { |
| 2813 | OPC_SwitchField, 15, 3, // 5710: switch Inst[17:15] { |
| 2814 | 0, 4, // 5713: case 0x0: { |
| 2815 | OPC_Decode, 136, 11, 63, // 5715: decode to VSEQ_B using decoder 63 |
| 2816 | // 5715: } |
| 2817 | 1, 4, // 5719: case 0x1: { |
| 2818 | OPC_Decode, 138, 11, 63, // 5721: decode to VSEQ_H using decoder 63 |
| 2819 | // 5721: } |
| 2820 | 2, 4, // 5725: case 0x2: { |
| 2821 | OPC_Decode, 139, 11, 63, // 5727: decode to VSEQ_W using decoder 63 |
| 2822 | // 5727: } |
| 2823 | 3, 4, // 5731: case 0x3: { |
| 2824 | OPC_Decode, 137, 11, 63, // 5733: decode to VSEQ_D using decoder 63 |
| 2825 | // 5733: } |
| 2826 | 4, 4, // 5737: case 0x4: { |
| 2827 | OPC_Decode, 170, 11, 63, // 5739: decode to VSLE_B using decoder 63 |
| 2828 | // 5739: } |
| 2829 | 5, 4, // 5743: case 0x5: { |
| 2830 | OPC_Decode, 174, 11, 63, // 5745: decode to VSLE_H using decoder 63 |
| 2831 | // 5745: } |
| 2832 | 6, 4, // 5749: case 0x6: { |
| 2833 | OPC_Decode, 176, 11, 63, // 5751: decode to VSLE_W using decoder 63 |
| 2834 | // 5751: } |
| 2835 | 7, 0, // 5755: case 0x7: { |
| 2836 | OPC_Decode, 172, 11, 63, // 5757: decode to VSLE_D using decoder 63 |
| 2837 | // 5757: } |
| 2838 | // 5757: } // switch Inst[17:15] |
| 2839 | // 5757: } |
| 2840 | 1, 51, // 5761: case 0x1: { |
| 2841 | OPC_SwitchField, 15, 3, // 5763: switch Inst[17:15] { |
| 2842 | 0, 4, // 5766: case 0x0: { |
| 2843 | OPC_Decode, 171, 11, 63, // 5768: decode to VSLE_BU using decoder 63 |
| 2844 | // 5768: } |
| 2845 | 1, 4, // 5772: case 0x1: { |
| 2846 | OPC_Decode, 175, 11, 63, // 5774: decode to VSLE_HU using decoder 63 |
| 2847 | // 5774: } |
| 2848 | 2, 4, // 5778: case 0x2: { |
| 2849 | OPC_Decode, 177, 11, 63, // 5780: decode to VSLE_WU using decoder 63 |
| 2850 | // 5780: } |
| 2851 | 3, 4, // 5784: case 0x3: { |
| 2852 | OPC_Decode, 173, 11, 63, // 5786: decode to VSLE_DU using decoder 63 |
| 2853 | // 5786: } |
| 2854 | 4, 4, // 5790: case 0x4: { |
| 2855 | OPC_Decode, 200, 11, 63, // 5792: decode to VSLT_B using decoder 63 |
| 2856 | // 5792: } |
| 2857 | 5, 4, // 5796: case 0x5: { |
| 2858 | OPC_Decode, 204, 11, 63, // 5798: decode to VSLT_H using decoder 63 |
| 2859 | // 5798: } |
| 2860 | 6, 4, // 5802: case 0x6: { |
| 2861 | OPC_Decode, 206, 11, 63, // 5804: decode to VSLT_W using decoder 63 |
| 2862 | // 5804: } |
| 2863 | 7, 0, // 5808: case 0x7: { |
| 2864 | OPC_Decode, 202, 11, 63, // 5810: decode to VSLT_D using decoder 63 |
| 2865 | // 5810: } |
| 2866 | // 5810: } // switch Inst[17:15] |
| 2867 | // 5810: } |
| 2868 | 2, 51, // 5814: case 0x2: { |
| 2869 | OPC_SwitchField, 15, 3, // 5816: switch Inst[17:15] { |
| 2870 | 0, 4, // 5819: case 0x0: { |
| 2871 | OPC_Decode, 201, 11, 63, // 5821: decode to VSLT_BU using decoder 63 |
| 2872 | // 5821: } |
| 2873 | 1, 4, // 5825: case 0x1: { |
| 2874 | OPC_Decode, 205, 11, 63, // 5827: decode to VSLT_HU using decoder 63 |
| 2875 | // 5827: } |
| 2876 | 2, 4, // 5831: case 0x2: { |
| 2877 | OPC_Decode, 207, 11, 63, // 5833: decode to VSLT_WU using decoder 63 |
| 2878 | // 5833: } |
| 2879 | 3, 4, // 5837: case 0x3: { |
| 2880 | OPC_Decode, 203, 11, 63, // 5839: decode to VSLT_DU using decoder 63 |
| 2881 | // 5839: } |
| 2882 | 4, 4, // 5843: case 0x4: { |
| 2883 | OPC_Decode, 189, 7, 63, // 5845: decode to VADD_B using decoder 63 |
| 2884 | // 5845: } |
| 2885 | 5, 4, // 5849: case 0x5: { |
| 2886 | OPC_Decode, 191, 7, 63, // 5851: decode to VADD_H using decoder 63 |
| 2887 | // 5851: } |
| 2888 | 6, 4, // 5855: case 0x6: { |
| 2889 | OPC_Decode, 193, 7, 63, // 5857: decode to VADD_W using decoder 63 |
| 2890 | // 5857: } |
| 2891 | 7, 0, // 5861: case 0x7: { |
| 2892 | OPC_Decode, 190, 7, 63, // 5863: decode to VADD_D using decoder 63 |
| 2893 | // 5863: } |
| 2894 | // 5863: } // switch Inst[17:15] |
| 2895 | // 5863: } |
| 2896 | 3, 27, // 5867: case 0x3: { |
| 2897 | OPC_SwitchField, 15, 3, // 5869: switch Inst[17:15] { |
| 2898 | 0, 4, // 5872: case 0x0: { |
| 2899 | OPC_Decode, 230, 12, 63, // 5874: decode to VSUB_B using decoder 63 |
| 2900 | // 5874: } |
| 2901 | 1, 4, // 5878: case 0x1: { |
| 2902 | OPC_Decode, 232, 12, 63, // 5880: decode to VSUB_H using decoder 63 |
| 2903 | // 5880: } |
| 2904 | 2, 4, // 5884: case 0x2: { |
| 2905 | OPC_Decode, 234, 12, 63, // 5886: decode to VSUB_W using decoder 63 |
| 2906 | // 5886: } |
| 2907 | 3, 0, // 5890: case 0x3: { |
| 2908 | OPC_Decode, 231, 12, 63, // 5892: decode to VSUB_D using decoder 63 |
| 2909 | // 5892: } |
| 2910 | // 5892: } // switch Inst[17:15] |
| 2911 | // 5892: } |
| 2912 | 7, 27, // 5896: case 0x7: { |
| 2913 | OPC_SwitchField, 15, 3, // 5898: switch Inst[17:15] { |
| 2914 | 4, 4, // 5901: case 0x4: { |
| 2915 | OPC_Decode, 168, 7, 63, // 5903: decode to VADDWEV_H_B using decoder 63 |
| 2916 | // 5903: } |
| 2917 | 5, 4, // 5907: case 0x5: { |
| 2918 | OPC_Decode, 174, 7, 63, // 5909: decode to VADDWEV_W_H using decoder 63 |
| 2919 | // 5909: } |
| 2920 | 6, 4, // 5913: case 0x6: { |
| 2921 | OPC_Decode, 165, 7, 63, // 5915: decode to VADDWEV_D_W using decoder 63 |
| 2922 | // 5915: } |
| 2923 | 7, 0, // 5919: case 0x7: { |
| 2924 | OPC_Decode, 171, 7, 63, // 5921: decode to VADDWEV_Q_D using decoder 63 |
| 2925 | // 5921: } |
| 2926 | // 5921: } // switch Inst[17:15] |
| 2927 | // 5921: } |
| 2928 | 8, 51, // 5925: case 0x8: { |
| 2929 | OPC_SwitchField, 15, 3, // 5927: switch Inst[17:15] { |
| 2930 | 0, 4, // 5930: case 0x0: { |
| 2931 | OPC_Decode, 216, 12, 63, // 5932: decode to VSUBWEV_H_B using decoder 63 |
| 2932 | // 5932: } |
| 2933 | 1, 4, // 5936: case 0x1: { |
| 2934 | OPC_Decode, 220, 12, 63, // 5938: decode to VSUBWEV_W_H using decoder 63 |
| 2935 | // 5938: } |
| 2936 | 2, 4, // 5942: case 0x2: { |
| 2937 | OPC_Decode, 214, 12, 63, // 5944: decode to VSUBWEV_D_W using decoder 63 |
| 2938 | // 5944: } |
| 2939 | 3, 4, // 5948: case 0x3: { |
| 2940 | OPC_Decode, 218, 12, 63, // 5950: decode to VSUBWEV_Q_D using decoder 63 |
| 2941 | // 5950: } |
| 2942 | 4, 4, // 5954: case 0x4: { |
| 2943 | OPC_Decode, 180, 7, 63, // 5956: decode to VADDWOD_H_B using decoder 63 |
| 2944 | // 5956: } |
| 2945 | 5, 4, // 5960: case 0x5: { |
| 2946 | OPC_Decode, 186, 7, 63, // 5962: decode to VADDWOD_W_H using decoder 63 |
| 2947 | // 5962: } |
| 2948 | 6, 4, // 5966: case 0x6: { |
| 2949 | OPC_Decode, 177, 7, 63, // 5968: decode to VADDWOD_D_W using decoder 63 |
| 2950 | // 5968: } |
| 2951 | 7, 0, // 5972: case 0x7: { |
| 2952 | OPC_Decode, 183, 7, 63, // 5974: decode to VADDWOD_Q_D using decoder 63 |
| 2953 | // 5974: } |
| 2954 | // 5974: } // switch Inst[17:15] |
| 2955 | // 5974: } |
| 2956 | 9, 27, // 5978: case 0x9: { |
| 2957 | OPC_SwitchField, 15, 3, // 5980: switch Inst[17:15] { |
| 2958 | 0, 4, // 5983: case 0x0: { |
| 2959 | OPC_Decode, 224, 12, 63, // 5985: decode to VSUBWOD_H_B using decoder 63 |
| 2960 | // 5985: } |
| 2961 | 1, 4, // 5989: case 0x1: { |
| 2962 | OPC_Decode, 228, 12, 63, // 5991: decode to VSUBWOD_W_H using decoder 63 |
| 2963 | // 5991: } |
| 2964 | 2, 4, // 5995: case 0x2: { |
| 2965 | OPC_Decode, 222, 12, 63, // 5997: decode to VSUBWOD_D_W using decoder 63 |
| 2966 | // 5997: } |
| 2967 | 3, 0, // 6001: case 0x3: { |
| 2968 | OPC_Decode, 226, 12, 63, // 6003: decode to VSUBWOD_Q_D using decoder 63 |
| 2969 | // 6003: } |
| 2970 | // 6003: } // switch Inst[17:15] |
| 2971 | // 6003: } |
| 2972 | 11, 27, // 6007: case 0xb: { |
| 2973 | OPC_SwitchField, 15, 3, // 6009: switch Inst[17:15] { |
| 2974 | 4, 4, // 6012: case 0x4: { |
| 2975 | OPC_Decode, 169, 7, 63, // 6014: decode to VADDWEV_H_BU using decoder 63 |
| 2976 | // 6014: } |
| 2977 | 5, 4, // 6018: case 0x5: { |
| 2978 | OPC_Decode, 175, 7, 63, // 6020: decode to VADDWEV_W_HU using decoder 63 |
| 2979 | // 6020: } |
| 2980 | 6, 4, // 6024: case 0x6: { |
| 2981 | OPC_Decode, 166, 7, 63, // 6026: decode to VADDWEV_D_WU using decoder 63 |
| 2982 | // 6026: } |
| 2983 | 7, 0, // 6030: case 0x7: { |
| 2984 | OPC_Decode, 172, 7, 63, // 6032: decode to VADDWEV_Q_DU using decoder 63 |
| 2985 | // 6032: } |
| 2986 | // 6032: } // switch Inst[17:15] |
| 2987 | // 6032: } |
| 2988 | 12, 51, // 6036: case 0xc: { |
| 2989 | OPC_SwitchField, 15, 3, // 6038: switch Inst[17:15] { |
| 2990 | 0, 4, // 6041: case 0x0: { |
| 2991 | OPC_Decode, 217, 12, 63, // 6043: decode to VSUBWEV_H_BU using decoder 63 |
| 2992 | // 6043: } |
| 2993 | 1, 4, // 6047: case 0x1: { |
| 2994 | OPC_Decode, 221, 12, 63, // 6049: decode to VSUBWEV_W_HU using decoder 63 |
| 2995 | // 6049: } |
| 2996 | 2, 4, // 6053: case 0x2: { |
| 2997 | OPC_Decode, 215, 12, 63, // 6055: decode to VSUBWEV_D_WU using decoder 63 |
| 2998 | // 6055: } |
| 2999 | 3, 4, // 6059: case 0x3: { |
| 3000 | OPC_Decode, 219, 12, 63, // 6061: decode to VSUBWEV_Q_DU using decoder 63 |
| 3001 | // 6061: } |
| 3002 | 4, 4, // 6065: case 0x4: { |
| 3003 | OPC_Decode, 181, 7, 63, // 6067: decode to VADDWOD_H_BU using decoder 63 |
| 3004 | // 6067: } |
| 3005 | 5, 4, // 6071: case 0x5: { |
| 3006 | OPC_Decode, 187, 7, 63, // 6073: decode to VADDWOD_W_HU using decoder 63 |
| 3007 | // 6073: } |
| 3008 | 6, 4, // 6077: case 0x6: { |
| 3009 | OPC_Decode, 178, 7, 63, // 6079: decode to VADDWOD_D_WU using decoder 63 |
| 3010 | // 6079: } |
| 3011 | 7, 0, // 6083: case 0x7: { |
| 3012 | OPC_Decode, 184, 7, 63, // 6085: decode to VADDWOD_Q_DU using decoder 63 |
| 3013 | // 6085: } |
| 3014 | // 6085: } // switch Inst[17:15] |
| 3015 | // 6085: } |
| 3016 | 13, 27, // 6089: case 0xd: { |
| 3017 | OPC_SwitchField, 15, 3, // 6091: switch Inst[17:15] { |
| 3018 | 0, 4, // 6094: case 0x0: { |
| 3019 | OPC_Decode, 225, 12, 63, // 6096: decode to VSUBWOD_H_BU using decoder 63 |
| 3020 | // 6096: } |
| 3021 | 1, 4, // 6100: case 0x1: { |
| 3022 | OPC_Decode, 229, 12, 63, // 6102: decode to VSUBWOD_W_HU using decoder 63 |
| 3023 | // 6102: } |
| 3024 | 2, 4, // 6106: case 0x2: { |
| 3025 | OPC_Decode, 223, 12, 63, // 6108: decode to VSUBWOD_D_WU using decoder 63 |
| 3026 | // 6108: } |
| 3027 | 3, 0, // 6112: case 0x3: { |
| 3028 | OPC_Decode, 227, 12, 63, // 6114: decode to VSUBWOD_Q_DU using decoder 63 |
| 3029 | // 6114: } |
| 3030 | // 6114: } // switch Inst[17:15] |
| 3031 | // 6114: } |
| 3032 | 15, 27, // 6118: case 0xf: { |
| 3033 | OPC_SwitchField, 15, 3, // 6120: switch Inst[17:15] { |
| 3034 | 4, 4, // 6123: case 0x4: { |
| 3035 | OPC_Decode, 170, 7, 63, // 6125: decode to VADDWEV_H_BU_B using decoder 63 |
| 3036 | // 6125: } |
| 3037 | 5, 4, // 6129: case 0x5: { |
| 3038 | OPC_Decode, 176, 7, 63, // 6131: decode to VADDWEV_W_HU_H using decoder 63 |
| 3039 | // 6131: } |
| 3040 | 6, 4, // 6135: case 0x6: { |
| 3041 | OPC_Decode, 167, 7, 63, // 6137: decode to VADDWEV_D_WU_W using decoder 63 |
| 3042 | // 6137: } |
| 3043 | 7, 0, // 6141: case 0x7: { |
| 3044 | OPC_Decode, 173, 7, 63, // 6143: decode to VADDWEV_Q_DU_D using decoder 63 |
| 3045 | // 6143: } |
| 3046 | // 6143: } // switch Inst[17:15] |
| 3047 | // 6143: } |
| 3048 | 16, 27, // 6147: case 0x10: { |
| 3049 | OPC_SwitchField, 15, 3, // 6149: switch Inst[17:15] { |
| 3050 | 0, 4, // 6152: case 0x0: { |
| 3051 | OPC_Decode, 182, 7, 63, // 6154: decode to VADDWOD_H_BU_B using decoder 63 |
| 3052 | // 6154: } |
| 3053 | 1, 4, // 6158: case 0x1: { |
| 3054 | OPC_Decode, 188, 7, 63, // 6160: decode to VADDWOD_W_HU_H using decoder 63 |
| 3055 | // 6160: } |
| 3056 | 2, 4, // 6164: case 0x2: { |
| 3057 | OPC_Decode, 179, 7, 63, // 6166: decode to VADDWOD_D_WU_W using decoder 63 |
| 3058 | // 6166: } |
| 3059 | 3, 0, // 6170: case 0x3: { |
| 3060 | OPC_Decode, 185, 7, 63, // 6172: decode to VADDWOD_Q_DU_D using decoder 63 |
| 3061 | // 6172: } |
| 3062 | // 6172: } // switch Inst[17:15] |
| 3063 | // 6172: } |
| 3064 | 17, 27, // 6176: case 0x11: { |
| 3065 | OPC_SwitchField, 15, 3, // 6178: switch Inst[17:15] { |
| 3066 | 4, 4, // 6181: case 0x4: { |
| 3067 | OPC_Decode, 244, 10, 63, // 6183: decode to VSADD_B using decoder 63 |
| 3068 | // 6183: } |
| 3069 | 5, 4, // 6187: case 0x5: { |
| 3070 | OPC_Decode, 248, 10, 63, // 6189: decode to VSADD_H using decoder 63 |
| 3071 | // 6189: } |
| 3072 | 6, 4, // 6193: case 0x6: { |
| 3073 | OPC_Decode, 250, 10, 63, // 6195: decode to VSADD_W using decoder 63 |
| 3074 | // 6195: } |
| 3075 | 7, 0, // 6199: case 0x7: { |
| 3076 | OPC_Decode, 246, 10, 63, // 6201: decode to VSADD_D using decoder 63 |
| 3077 | // 6201: } |
| 3078 | // 6201: } // switch Inst[17:15] |
| 3079 | // 6201: } |
| 3080 | 18, 51, // 6205: case 0x12: { |
| 3081 | OPC_SwitchField, 15, 3, // 6207: switch Inst[17:15] { |
| 3082 | 0, 4, // 6210: case 0x0: { |
| 3083 | OPC_Decode, 196, 12, 63, // 6212: decode to VSSUB_B using decoder 63 |
| 3084 | // 6212: } |
| 3085 | 1, 4, // 6216: case 0x1: { |
| 3086 | OPC_Decode, 200, 12, 63, // 6218: decode to VSSUB_H using decoder 63 |
| 3087 | // 6218: } |
| 3088 | 2, 4, // 6222: case 0x2: { |
| 3089 | OPC_Decode, 202, 12, 63, // 6224: decode to VSSUB_W using decoder 63 |
| 3090 | // 6224: } |
| 3091 | 3, 4, // 6228: case 0x3: { |
| 3092 | OPC_Decode, 198, 12, 63, // 6230: decode to VSSUB_D using decoder 63 |
| 3093 | // 6230: } |
| 3094 | 4, 4, // 6234: case 0x4: { |
| 3095 | OPC_Decode, 245, 10, 63, // 6236: decode to VSADD_BU using decoder 63 |
| 3096 | // 6236: } |
| 3097 | 5, 4, // 6240: case 0x5: { |
| 3098 | OPC_Decode, 249, 10, 63, // 6242: decode to VSADD_HU using decoder 63 |
| 3099 | // 6242: } |
| 3100 | 6, 4, // 6246: case 0x6: { |
| 3101 | OPC_Decode, 251, 10, 63, // 6248: decode to VSADD_WU using decoder 63 |
| 3102 | // 6248: } |
| 3103 | 7, 0, // 6252: case 0x7: { |
| 3104 | OPC_Decode, 247, 10, 63, // 6254: decode to VSADD_DU using decoder 63 |
| 3105 | // 6254: } |
| 3106 | // 6254: } // switch Inst[17:15] |
| 3107 | // 6254: } |
| 3108 | 19, 27, // 6258: case 0x13: { |
| 3109 | OPC_SwitchField, 15, 3, // 6260: switch Inst[17:15] { |
| 3110 | 0, 4, // 6263: case 0x0: { |
| 3111 | OPC_Decode, 197, 12, 63, // 6265: decode to VSSUB_BU using decoder 63 |
| 3112 | // 6265: } |
| 3113 | 1, 4, // 6269: case 0x1: { |
| 3114 | OPC_Decode, 201, 12, 63, // 6271: decode to VSSUB_HU using decoder 63 |
| 3115 | // 6271: } |
| 3116 | 2, 4, // 6275: case 0x2: { |
| 3117 | OPC_Decode, 203, 12, 63, // 6277: decode to VSSUB_WU using decoder 63 |
| 3118 | // 6277: } |
| 3119 | 3, 0, // 6281: case 0x3: { |
| 3120 | OPC_Decode, 199, 12, 63, // 6283: decode to VSSUB_DU using decoder 63 |
| 3121 | // 6283: } |
| 3122 | // 6283: } // switch Inst[17:15] |
| 3123 | // 6283: } |
| 3124 | 21, 51, // 6287: case 0x15: { |
| 3125 | OPC_SwitchField, 15, 3, // 6289: switch Inst[17:15] { |
| 3126 | 0, 4, // 6292: case 0x0: { |
| 3127 | OPC_Decode, 168, 9, 63, // 6294: decode to VHADDW_H_B using decoder 63 |
| 3128 | // 6294: } |
| 3129 | 1, 4, // 6298: case 0x1: { |
| 3130 | OPC_Decode, 172, 9, 63, // 6300: decode to VHADDW_W_H using decoder 63 |
| 3131 | // 6300: } |
| 3132 | 2, 4, // 6304: case 0x2: { |
| 3133 | OPC_Decode, 166, 9, 63, // 6306: decode to VHADDW_D_W using decoder 63 |
| 3134 | // 6306: } |
| 3135 | 3, 4, // 6310: case 0x3: { |
| 3136 | OPC_Decode, 170, 9, 63, // 6312: decode to VHADDW_Q_D using decoder 63 |
| 3137 | // 6312: } |
| 3138 | 4, 4, // 6316: case 0x4: { |
| 3139 | OPC_Decode, 176, 9, 63, // 6318: decode to VHSUBW_H_B using decoder 63 |
| 3140 | // 6318: } |
| 3141 | 5, 4, // 6322: case 0x5: { |
| 3142 | OPC_Decode, 180, 9, 63, // 6324: decode to VHSUBW_W_H using decoder 63 |
| 3143 | // 6324: } |
| 3144 | 6, 4, // 6328: case 0x6: { |
| 3145 | OPC_Decode, 174, 9, 63, // 6330: decode to VHSUBW_D_W using decoder 63 |
| 3146 | // 6330: } |
| 3147 | 7, 0, // 6334: case 0x7: { |
| 3148 | OPC_Decode, 178, 9, 63, // 6336: decode to VHSUBW_Q_D using decoder 63 |
| 3149 | // 6336: } |
| 3150 | // 6336: } // switch Inst[17:15] |
| 3151 | // 6336: } |
| 3152 | 22, 51, // 6340: case 0x16: { |
| 3153 | OPC_SwitchField, 15, 3, // 6342: switch Inst[17:15] { |
| 3154 | 0, 4, // 6345: case 0x0: { |
| 3155 | OPC_Decode, 167, 9, 63, // 6347: decode to VHADDW_HU_BU using decoder 63 |
| 3156 | // 6347: } |
| 3157 | 1, 4, // 6351: case 0x1: { |
| 3158 | OPC_Decode, 171, 9, 63, // 6353: decode to VHADDW_WU_HU using decoder 63 |
| 3159 | // 6353: } |
| 3160 | 2, 4, // 6357: case 0x2: { |
| 3161 | OPC_Decode, 165, 9, 63, // 6359: decode to VHADDW_DU_WU using decoder 63 |
| 3162 | // 6359: } |
| 3163 | 3, 4, // 6363: case 0x3: { |
| 3164 | OPC_Decode, 169, 9, 63, // 6365: decode to VHADDW_QU_DU using decoder 63 |
| 3165 | // 6365: } |
| 3166 | 4, 4, // 6369: case 0x4: { |
| 3167 | OPC_Decode, 175, 9, 63, // 6371: decode to VHSUBW_HU_BU using decoder 63 |
| 3168 | // 6371: } |
| 3169 | 5, 4, // 6375: case 0x5: { |
| 3170 | OPC_Decode, 179, 9, 63, // 6377: decode to VHSUBW_WU_HU using decoder 63 |
| 3171 | // 6377: } |
| 3172 | 6, 4, // 6381: case 0x6: { |
| 3173 | OPC_Decode, 173, 9, 63, // 6383: decode to VHSUBW_DU_WU using decoder 63 |
| 3174 | // 6383: } |
| 3175 | 7, 0, // 6387: case 0x7: { |
| 3176 | OPC_Decode, 177, 9, 63, // 6389: decode to VHSUBW_QU_DU using decoder 63 |
| 3177 | // 6389: } |
| 3178 | // 6389: } // switch Inst[17:15] |
| 3179 | // 6389: } |
| 3180 | 23, 27, // 6393: case 0x17: { |
| 3181 | OPC_SwitchField, 15, 3, // 6395: switch Inst[17:15] { |
| 3182 | 0, 4, // 6398: case 0x0: { |
| 3183 | OPC_Decode, 157, 7, 63, // 6400: decode to VADDA_B using decoder 63 |
| 3184 | // 6400: } |
| 3185 | 1, 4, // 6404: case 0x1: { |
| 3186 | OPC_Decode, 159, 7, 63, // 6406: decode to VADDA_H using decoder 63 |
| 3187 | // 6406: } |
| 3188 | 2, 4, // 6410: case 0x2: { |
| 3189 | OPC_Decode, 160, 7, 63, // 6412: decode to VADDA_W using decoder 63 |
| 3190 | // 6412: } |
| 3191 | 3, 0, // 6416: case 0x3: { |
| 3192 | OPC_Decode, 158, 7, 63, // 6418: decode to VADDA_D using decoder 63 |
| 3193 | // 6418: } |
| 3194 | // 6418: } // switch Inst[17:15] |
| 3195 | // 6418: } |
| 3196 | 24, 51, // 6422: case 0x18: { |
| 3197 | OPC_SwitchField, 15, 3, // 6424: switch Inst[17:15] { |
| 3198 | 0, 4, // 6427: case 0x0: { |
| 3199 | OPC_Decode, 149, 7, 63, // 6429: decode to VABSD_B using decoder 63 |
| 3200 | // 6429: } |
| 3201 | 1, 4, // 6433: case 0x1: { |
| 3202 | OPC_Decode, 153, 7, 63, // 6435: decode to VABSD_H using decoder 63 |
| 3203 | // 6435: } |
| 3204 | 2, 4, // 6439: case 0x2: { |
| 3205 | OPC_Decode, 155, 7, 63, // 6441: decode to VABSD_W using decoder 63 |
| 3206 | // 6441: } |
| 3207 | 3, 4, // 6445: case 0x3: { |
| 3208 | OPC_Decode, 151, 7, 63, // 6447: decode to VABSD_D using decoder 63 |
| 3209 | // 6447: } |
| 3210 | 4, 4, // 6451: case 0x4: { |
| 3211 | OPC_Decode, 150, 7, 63, // 6453: decode to VABSD_BU using decoder 63 |
| 3212 | // 6453: } |
| 3213 | 5, 4, // 6457: case 0x5: { |
| 3214 | OPC_Decode, 154, 7, 63, // 6459: decode to VABSD_HU using decoder 63 |
| 3215 | // 6459: } |
| 3216 | 6, 4, // 6463: case 0x6: { |
| 3217 | OPC_Decode, 156, 7, 63, // 6465: decode to VABSD_WU using decoder 63 |
| 3218 | // 6465: } |
| 3219 | 7, 0, // 6469: case 0x7: { |
| 3220 | OPC_Decode, 152, 7, 63, // 6471: decode to VABSD_DU using decoder 63 |
| 3221 | // 6471: } |
| 3222 | // 6471: } // switch Inst[17:15] |
| 3223 | // 6471: } |
| 3224 | 25, 51, // 6475: case 0x19: { |
| 3225 | OPC_SwitchField, 15, 3, // 6477: switch Inst[17:15] { |
| 3226 | 0, 4, // 6480: case 0x0: { |
| 3227 | OPC_Decode, 205, 7, 63, // 6482: decode to VAVG_B using decoder 63 |
| 3228 | // 6482: } |
| 3229 | 1, 4, // 6486: case 0x1: { |
| 3230 | OPC_Decode, 209, 7, 63, // 6488: decode to VAVG_H using decoder 63 |
| 3231 | // 6488: } |
| 3232 | 2, 4, // 6492: case 0x2: { |
| 3233 | OPC_Decode, 211, 7, 63, // 6494: decode to VAVG_W using decoder 63 |
| 3234 | // 6494: } |
| 3235 | 3, 4, // 6498: case 0x3: { |
| 3236 | OPC_Decode, 207, 7, 63, // 6500: decode to VAVG_D using decoder 63 |
| 3237 | // 6500: } |
| 3238 | 4, 4, // 6504: case 0x4: { |
| 3239 | OPC_Decode, 206, 7, 63, // 6506: decode to VAVG_BU using decoder 63 |
| 3240 | // 6506: } |
| 3241 | 5, 4, // 6510: case 0x5: { |
| 3242 | OPC_Decode, 210, 7, 63, // 6512: decode to VAVG_HU using decoder 63 |
| 3243 | // 6512: } |
| 3244 | 6, 4, // 6516: case 0x6: { |
| 3245 | OPC_Decode, 212, 7, 63, // 6518: decode to VAVG_WU using decoder 63 |
| 3246 | // 6518: } |
| 3247 | 7, 0, // 6522: case 0x7: { |
| 3248 | OPC_Decode, 208, 7, 63, // 6524: decode to VAVG_DU using decoder 63 |
| 3249 | // 6524: } |
| 3250 | // 6524: } // switch Inst[17:15] |
| 3251 | // 6524: } |
| 3252 | 26, 51, // 6528: case 0x1a: { |
| 3253 | OPC_SwitchField, 15, 3, // 6530: switch Inst[17:15] { |
| 3254 | 0, 4, // 6533: case 0x0: { |
| 3255 | OPC_Decode, 197, 7, 63, // 6535: decode to VAVGR_B using decoder 63 |
| 3256 | // 6535: } |
| 3257 | 1, 4, // 6539: case 0x1: { |
| 3258 | OPC_Decode, 201, 7, 63, // 6541: decode to VAVGR_H using decoder 63 |
| 3259 | // 6541: } |
| 3260 | 2, 4, // 6545: case 0x2: { |
| 3261 | OPC_Decode, 203, 7, 63, // 6547: decode to VAVGR_W using decoder 63 |
| 3262 | // 6547: } |
| 3263 | 3, 4, // 6551: case 0x3: { |
| 3264 | OPC_Decode, 199, 7, 63, // 6553: decode to VAVGR_D using decoder 63 |
| 3265 | // 6553: } |
| 3266 | 4, 4, // 6557: case 0x4: { |
| 3267 | OPC_Decode, 198, 7, 63, // 6559: decode to VAVGR_BU using decoder 63 |
| 3268 | // 6559: } |
| 3269 | 5, 4, // 6563: case 0x5: { |
| 3270 | OPC_Decode, 202, 7, 63, // 6565: decode to VAVGR_HU using decoder 63 |
| 3271 | // 6565: } |
| 3272 | 6, 4, // 6569: case 0x6: { |
| 3273 | OPC_Decode, 204, 7, 63, // 6571: decode to VAVGR_WU using decoder 63 |
| 3274 | // 6571: } |
| 3275 | 7, 0, // 6575: case 0x7: { |
| 3276 | OPC_Decode, 200, 7, 63, // 6577: decode to VAVGR_DU using decoder 63 |
| 3277 | // 6577: } |
| 3278 | // 6577: } // switch Inst[17:15] |
| 3279 | // 6577: } |
| 3280 | 28, 51, // 6581: case 0x1c: { |
| 3281 | OPC_SwitchField, 15, 3, // 6583: switch Inst[17:15] { |
| 3282 | 0, 4, // 6586: case 0x0: { |
| 3283 | OPC_Decode, 236, 9, 63, // 6588: decode to VMAX_B using decoder 63 |
| 3284 | // 6588: } |
| 3285 | 1, 4, // 6592: case 0x1: { |
| 3286 | OPC_Decode, 240, 9, 63, // 6594: decode to VMAX_H using decoder 63 |
| 3287 | // 6594: } |
| 3288 | 2, 4, // 6598: case 0x2: { |
| 3289 | OPC_Decode, 242, 9, 63, // 6600: decode to VMAX_W using decoder 63 |
| 3290 | // 6600: } |
| 3291 | 3, 4, // 6604: case 0x3: { |
| 3292 | OPC_Decode, 238, 9, 63, // 6606: decode to VMAX_D using decoder 63 |
| 3293 | // 6606: } |
| 3294 | 4, 4, // 6610: case 0x4: { |
| 3295 | OPC_Decode, 252, 9, 63, // 6612: decode to VMIN_B using decoder 63 |
| 3296 | // 6612: } |
| 3297 | 5, 4, // 6616: case 0x5: { |
| 3298 | OPC_Decode, 128, 10, 63, // 6618: decode to VMIN_H using decoder 63 |
| 3299 | // 6618: } |
| 3300 | 6, 4, // 6622: case 0x6: { |
| 3301 | OPC_Decode, 130, 10, 63, // 6624: decode to VMIN_W using decoder 63 |
| 3302 | // 6624: } |
| 3303 | 7, 0, // 6628: case 0x7: { |
| 3304 | OPC_Decode, 254, 9, 63, // 6630: decode to VMIN_D using decoder 63 |
| 3305 | // 6630: } |
| 3306 | // 6630: } // switch Inst[17:15] |
| 3307 | // 6630: } |
| 3308 | 29, 51, // 6634: case 0x1d: { |
| 3309 | OPC_SwitchField, 15, 3, // 6636: switch Inst[17:15] { |
| 3310 | 0, 4, // 6639: case 0x0: { |
| 3311 | OPC_Decode, 237, 9, 63, // 6641: decode to VMAX_BU using decoder 63 |
| 3312 | // 6641: } |
| 3313 | 1, 4, // 6645: case 0x1: { |
| 3314 | OPC_Decode, 241, 9, 63, // 6647: decode to VMAX_HU using decoder 63 |
| 3315 | // 6647: } |
| 3316 | 2, 4, // 6651: case 0x2: { |
| 3317 | OPC_Decode, 243, 9, 63, // 6653: decode to VMAX_WU using decoder 63 |
| 3318 | // 6653: } |
| 3319 | 3, 4, // 6657: case 0x3: { |
| 3320 | OPC_Decode, 239, 9, 63, // 6659: decode to VMAX_DU using decoder 63 |
| 3321 | // 6659: } |
| 3322 | 4, 4, // 6663: case 0x4: { |
| 3323 | OPC_Decode, 253, 9, 63, // 6665: decode to VMIN_BU using decoder 63 |
| 3324 | // 6665: } |
| 3325 | 5, 4, // 6669: case 0x5: { |
| 3326 | OPC_Decode, 129, 10, 63, // 6671: decode to VMIN_HU using decoder 63 |
| 3327 | // 6671: } |
| 3328 | 6, 4, // 6675: case 0x6: { |
| 3329 | OPC_Decode, 131, 10, 63, // 6677: decode to VMIN_WU using decoder 63 |
| 3330 | // 6677: } |
| 3331 | 7, 0, // 6681: case 0x7: { |
| 3332 | OPC_Decode, 255, 9, 63, // 6683: decode to VMIN_DU using decoder 63 |
| 3333 | // 6683: } |
| 3334 | // 6683: } // switch Inst[17:15] |
| 3335 | // 6683: } |
| 3336 | 33, 51, // 6687: case 0x21: { |
| 3337 | OPC_SwitchField, 15, 3, // 6689: switch Inst[17:15] { |
| 3338 | 0, 4, // 6692: case 0x0: { |
| 3339 | OPC_Decode, 182, 10, 63, // 6694: decode to VMUL_B using decoder 63 |
| 3340 | // 6694: } |
| 3341 | 1, 4, // 6698: case 0x1: { |
| 3342 | OPC_Decode, 184, 10, 63, // 6700: decode to VMUL_H using decoder 63 |
| 3343 | // 6700: } |
| 3344 | 2, 4, // 6704: case 0x2: { |
| 3345 | OPC_Decode, 185, 10, 63, // 6706: decode to VMUL_W using decoder 63 |
| 3346 | // 6706: } |
| 3347 | 3, 4, // 6710: case 0x3: { |
| 3348 | OPC_Decode, 183, 10, 63, // 6712: decode to VMUL_D using decoder 63 |
| 3349 | // 6712: } |
| 3350 | 4, 4, // 6716: case 0x4: { |
| 3351 | OPC_Decode, 150, 10, 63, // 6718: decode to VMUH_B using decoder 63 |
| 3352 | // 6718: } |
| 3353 | 5, 4, // 6722: case 0x5: { |
| 3354 | OPC_Decode, 154, 10, 63, // 6724: decode to VMUH_H using decoder 63 |
| 3355 | // 6724: } |
| 3356 | 6, 4, // 6728: case 0x6: { |
| 3357 | OPC_Decode, 156, 10, 63, // 6730: decode to VMUH_W using decoder 63 |
| 3358 | // 6730: } |
| 3359 | 7, 0, // 6734: case 0x7: { |
| 3360 | OPC_Decode, 152, 10, 63, // 6736: decode to VMUH_D using decoder 63 |
| 3361 | // 6736: } |
| 3362 | // 6736: } // switch Inst[17:15] |
| 3363 | // 6736: } |
| 3364 | 34, 27, // 6740: case 0x22: { |
| 3365 | OPC_SwitchField, 15, 3, // 6742: switch Inst[17:15] { |
| 3366 | 0, 4, // 6745: case 0x0: { |
| 3367 | OPC_Decode, 151, 10, 63, // 6747: decode to VMUH_BU using decoder 63 |
| 3368 | // 6747: } |
| 3369 | 1, 4, // 6751: case 0x1: { |
| 3370 | OPC_Decode, 155, 10, 63, // 6753: decode to VMUH_HU using decoder 63 |
| 3371 | // 6753: } |
| 3372 | 2, 4, // 6757: case 0x2: { |
| 3373 | OPC_Decode, 157, 10, 63, // 6759: decode to VMUH_WU using decoder 63 |
| 3374 | // 6759: } |
| 3375 | 3, 0, // 6763: case 0x3: { |
| 3376 | OPC_Decode, 153, 10, 63, // 6765: decode to VMUH_DU using decoder 63 |
| 3377 | // 6765: } |
| 3378 | // 6765: } // switch Inst[17:15] |
| 3379 | // 6765: } |
| 3380 | 36, 51, // 6769: case 0x24: { |
| 3381 | OPC_SwitchField, 15, 3, // 6771: switch Inst[17:15] { |
| 3382 | 0, 4, // 6774: case 0x0: { |
| 3383 | OPC_Decode, 161, 10, 63, // 6776: decode to VMULWEV_H_B using decoder 63 |
| 3384 | // 6776: } |
| 3385 | 1, 4, // 6780: case 0x1: { |
| 3386 | OPC_Decode, 167, 10, 63, // 6782: decode to VMULWEV_W_H using decoder 63 |
| 3387 | // 6782: } |
| 3388 | 2, 4, // 6786: case 0x2: { |
| 3389 | OPC_Decode, 158, 10, 63, // 6788: decode to VMULWEV_D_W using decoder 63 |
| 3390 | // 6788: } |
| 3391 | 3, 4, // 6792: case 0x3: { |
| 3392 | OPC_Decode, 164, 10, 63, // 6794: decode to VMULWEV_Q_D using decoder 63 |
| 3393 | // 6794: } |
| 3394 | 4, 4, // 6798: case 0x4: { |
| 3395 | OPC_Decode, 173, 10, 63, // 6800: decode to VMULWOD_H_B using decoder 63 |
| 3396 | // 6800: } |
| 3397 | 5, 4, // 6804: case 0x5: { |
| 3398 | OPC_Decode, 179, 10, 63, // 6806: decode to VMULWOD_W_H using decoder 63 |
| 3399 | // 6806: } |
| 3400 | 6, 4, // 6810: case 0x6: { |
| 3401 | OPC_Decode, 170, 10, 63, // 6812: decode to VMULWOD_D_W using decoder 63 |
| 3402 | // 6812: } |
| 3403 | 7, 0, // 6816: case 0x7: { |
| 3404 | OPC_Decode, 176, 10, 63, // 6818: decode to VMULWOD_Q_D using decoder 63 |
| 3405 | // 6818: } |
| 3406 | // 6818: } // switch Inst[17:15] |
| 3407 | // 6818: } |
| 3408 | 38, 51, // 6822: case 0x26: { |
| 3409 | OPC_SwitchField, 15, 3, // 6824: switch Inst[17:15] { |
| 3410 | 0, 4, // 6827: case 0x0: { |
| 3411 | OPC_Decode, 162, 10, 63, // 6829: decode to VMULWEV_H_BU using decoder 63 |
| 3412 | // 6829: } |
| 3413 | 1, 4, // 6833: case 0x1: { |
| 3414 | OPC_Decode, 168, 10, 63, // 6835: decode to VMULWEV_W_HU using decoder 63 |
| 3415 | // 6835: } |
| 3416 | 2, 4, // 6839: case 0x2: { |
| 3417 | OPC_Decode, 159, 10, 63, // 6841: decode to VMULWEV_D_WU using decoder 63 |
| 3418 | // 6841: } |
| 3419 | 3, 4, // 6845: case 0x3: { |
| 3420 | OPC_Decode, 165, 10, 63, // 6847: decode to VMULWEV_Q_DU using decoder 63 |
| 3421 | // 6847: } |
| 3422 | 4, 4, // 6851: case 0x4: { |
| 3423 | OPC_Decode, 174, 10, 63, // 6853: decode to VMULWOD_H_BU using decoder 63 |
| 3424 | // 6853: } |
| 3425 | 5, 4, // 6857: case 0x5: { |
| 3426 | OPC_Decode, 180, 10, 63, // 6859: decode to VMULWOD_W_HU using decoder 63 |
| 3427 | // 6859: } |
| 3428 | 6, 4, // 6863: case 0x6: { |
| 3429 | OPC_Decode, 171, 10, 63, // 6865: decode to VMULWOD_D_WU using decoder 63 |
| 3430 | // 6865: } |
| 3431 | 7, 0, // 6869: case 0x7: { |
| 3432 | OPC_Decode, 177, 10, 63, // 6871: decode to VMULWOD_Q_DU using decoder 63 |
| 3433 | // 6871: } |
| 3434 | // 6871: } // switch Inst[17:15] |
| 3435 | // 6871: } |
| 3436 | 40, 51, // 6875: case 0x28: { |
| 3437 | OPC_SwitchField, 15, 3, // 6877: switch Inst[17:15] { |
| 3438 | 0, 4, // 6880: case 0x0: { |
| 3439 | OPC_Decode, 163, 10, 63, // 6882: decode to VMULWEV_H_BU_B using decoder 63 |
| 3440 | // 6882: } |
| 3441 | 1, 4, // 6886: case 0x1: { |
| 3442 | OPC_Decode, 169, 10, 63, // 6888: decode to VMULWEV_W_HU_H using decoder 63 |
| 3443 | // 6888: } |
| 3444 | 2, 4, // 6892: case 0x2: { |
| 3445 | OPC_Decode, 160, 10, 63, // 6894: decode to VMULWEV_D_WU_W using decoder 63 |
| 3446 | // 6894: } |
| 3447 | 3, 4, // 6898: case 0x3: { |
| 3448 | OPC_Decode, 166, 10, 63, // 6900: decode to VMULWEV_Q_DU_D using decoder 63 |
| 3449 | // 6900: } |
| 3450 | 4, 4, // 6904: case 0x4: { |
| 3451 | OPC_Decode, 175, 10, 63, // 6906: decode to VMULWOD_H_BU_B using decoder 63 |
| 3452 | // 6906: } |
| 3453 | 5, 4, // 6910: case 0x5: { |
| 3454 | OPC_Decode, 181, 10, 63, // 6912: decode to VMULWOD_W_HU_H using decoder 63 |
| 3455 | // 6912: } |
| 3456 | 6, 4, // 6916: case 0x6: { |
| 3457 | OPC_Decode, 172, 10, 63, // 6918: decode to VMULWOD_D_WU_W using decoder 63 |
| 3458 | // 6918: } |
| 3459 | 7, 0, // 6922: case 0x7: { |
| 3460 | OPC_Decode, 178, 10, 63, // 6924: decode to VMULWOD_Q_DU_D using decoder 63 |
| 3461 | // 6924: } |
| 3462 | // 6924: } // switch Inst[17:15] |
| 3463 | // 6924: } |
| 3464 | 42, 51, // 6928: case 0x2a: { |
| 3465 | OPC_SwitchField, 15, 3, // 6930: switch Inst[17:15] { |
| 3466 | 0, 4, // 6933: case 0x0: { |
| 3467 | OPC_Decode, 224, 9, 104, // 6935: decode to VMADD_B using decoder 104 |
| 3468 | // 6935: } |
| 3469 | 1, 4, // 6939: case 0x1: { |
| 3470 | OPC_Decode, 226, 9, 104, // 6941: decode to VMADD_H using decoder 104 |
| 3471 | // 6941: } |
| 3472 | 2, 4, // 6945: case 0x2: { |
| 3473 | OPC_Decode, 227, 9, 104, // 6947: decode to VMADD_W using decoder 104 |
| 3474 | // 6947: } |
| 3475 | 3, 4, // 6951: case 0x3: { |
| 3476 | OPC_Decode, 225, 9, 104, // 6953: decode to VMADD_D using decoder 104 |
| 3477 | // 6953: } |
| 3478 | 4, 4, // 6957: case 0x4: { |
| 3479 | OPC_Decode, 146, 10, 104, // 6959: decode to VMSUB_B using decoder 104 |
| 3480 | // 6959: } |
| 3481 | 5, 4, // 6963: case 0x5: { |
| 3482 | OPC_Decode, 148, 10, 104, // 6965: decode to VMSUB_H using decoder 104 |
| 3483 | // 6965: } |
| 3484 | 6, 4, // 6969: case 0x6: { |
| 3485 | OPC_Decode, 149, 10, 104, // 6971: decode to VMSUB_W using decoder 104 |
| 3486 | // 6971: } |
| 3487 | 7, 0, // 6975: case 0x7: { |
| 3488 | OPC_Decode, 147, 10, 104, // 6977: decode to VMSUB_D using decoder 104 |
| 3489 | // 6977: } |
| 3490 | // 6977: } // switch Inst[17:15] |
| 3491 | // 6977: } |
| 3492 | 43, 51, // 6981: case 0x2b: { |
| 3493 | OPC_SwitchField, 15, 3, // 6983: switch Inst[17:15] { |
| 3494 | 0, 4, // 6986: case 0x0: { |
| 3495 | OPC_Decode, 203, 9, 104, // 6988: decode to VMADDWEV_H_B using decoder 104 |
| 3496 | // 6988: } |
| 3497 | 1, 4, // 6992: case 0x1: { |
| 3498 | OPC_Decode, 209, 9, 104, // 6994: decode to VMADDWEV_W_H using decoder 104 |
| 3499 | // 6994: } |
| 3500 | 2, 4, // 6998: case 0x2: { |
| 3501 | OPC_Decode, 200, 9, 104, // 7000: decode to VMADDWEV_D_W using decoder 104 |
| 3502 | // 7000: } |
| 3503 | 3, 4, // 7004: case 0x3: { |
| 3504 | OPC_Decode, 206, 9, 104, // 7006: decode to VMADDWEV_Q_D using decoder 104 |
| 3505 | // 7006: } |
| 3506 | 4, 4, // 7010: case 0x4: { |
| 3507 | OPC_Decode, 215, 9, 104, // 7012: decode to VMADDWOD_H_B using decoder 104 |
| 3508 | // 7012: } |
| 3509 | 5, 4, // 7016: case 0x5: { |
| 3510 | OPC_Decode, 221, 9, 104, // 7018: decode to VMADDWOD_W_H using decoder 104 |
| 3511 | // 7018: } |
| 3512 | 6, 4, // 7022: case 0x6: { |
| 3513 | OPC_Decode, 212, 9, 104, // 7024: decode to VMADDWOD_D_W using decoder 104 |
| 3514 | // 7024: } |
| 3515 | 7, 0, // 7028: case 0x7: { |
| 3516 | OPC_Decode, 218, 9, 104, // 7030: decode to VMADDWOD_Q_D using decoder 104 |
| 3517 | // 7030: } |
| 3518 | // 7030: } // switch Inst[17:15] |
| 3519 | // 7030: } |
| 3520 | 45, 51, // 7034: case 0x2d: { |
| 3521 | OPC_SwitchField, 15, 3, // 7036: switch Inst[17:15] { |
| 3522 | 0, 4, // 7039: case 0x0: { |
| 3523 | OPC_Decode, 204, 9, 104, // 7041: decode to VMADDWEV_H_BU using decoder 104 |
| 3524 | // 7041: } |
| 3525 | 1, 4, // 7045: case 0x1: { |
| 3526 | OPC_Decode, 210, 9, 104, // 7047: decode to VMADDWEV_W_HU using decoder 104 |
| 3527 | // 7047: } |
| 3528 | 2, 4, // 7051: case 0x2: { |
| 3529 | OPC_Decode, 201, 9, 104, // 7053: decode to VMADDWEV_D_WU using decoder 104 |
| 3530 | // 7053: } |
| 3531 | 3, 4, // 7057: case 0x3: { |
| 3532 | OPC_Decode, 207, 9, 104, // 7059: decode to VMADDWEV_Q_DU using decoder 104 |
| 3533 | // 7059: } |
| 3534 | 4, 4, // 7063: case 0x4: { |
| 3535 | OPC_Decode, 216, 9, 104, // 7065: decode to VMADDWOD_H_BU using decoder 104 |
| 3536 | // 7065: } |
| 3537 | 5, 4, // 7069: case 0x5: { |
| 3538 | OPC_Decode, 222, 9, 104, // 7071: decode to VMADDWOD_W_HU using decoder 104 |
| 3539 | // 7071: } |
| 3540 | 6, 4, // 7075: case 0x6: { |
| 3541 | OPC_Decode, 213, 9, 104, // 7077: decode to VMADDWOD_D_WU using decoder 104 |
| 3542 | // 7077: } |
| 3543 | 7, 0, // 7081: case 0x7: { |
| 3544 | OPC_Decode, 219, 9, 104, // 7083: decode to VMADDWOD_Q_DU using decoder 104 |
| 3545 | // 7083: } |
| 3546 | // 7083: } // switch Inst[17:15] |
| 3547 | // 7083: } |
| 3548 | 47, 51, // 7087: case 0x2f: { |
| 3549 | OPC_SwitchField, 15, 3, // 7089: switch Inst[17:15] { |
| 3550 | 0, 4, // 7092: case 0x0: { |
| 3551 | OPC_Decode, 205, 9, 104, // 7094: decode to VMADDWEV_H_BU_B using decoder 104 |
| 3552 | // 7094: } |
| 3553 | 1, 4, // 7098: case 0x1: { |
| 3554 | OPC_Decode, 211, 9, 104, // 7100: decode to VMADDWEV_W_HU_H using decoder 104 |
| 3555 | // 7100: } |
| 3556 | 2, 4, // 7104: case 0x2: { |
| 3557 | OPC_Decode, 202, 9, 104, // 7106: decode to VMADDWEV_D_WU_W using decoder 104 |
| 3558 | // 7106: } |
| 3559 | 3, 4, // 7110: case 0x3: { |
| 3560 | OPC_Decode, 208, 9, 104, // 7112: decode to VMADDWEV_Q_DU_D using decoder 104 |
| 3561 | // 7112: } |
| 3562 | 4, 4, // 7116: case 0x4: { |
| 3563 | OPC_Decode, 217, 9, 104, // 7118: decode to VMADDWOD_H_BU_B using decoder 104 |
| 3564 | // 7118: } |
| 3565 | 5, 4, // 7122: case 0x5: { |
| 3566 | OPC_Decode, 223, 9, 104, // 7124: decode to VMADDWOD_W_HU_H using decoder 104 |
| 3567 | // 7124: } |
| 3568 | 6, 4, // 7128: case 0x6: { |
| 3569 | OPC_Decode, 214, 9, 104, // 7130: decode to VMADDWOD_D_WU_W using decoder 104 |
| 3570 | // 7130: } |
| 3571 | 7, 0, // 7134: case 0x7: { |
| 3572 | OPC_Decode, 220, 9, 104, // 7136: decode to VMADDWOD_Q_DU_D using decoder 104 |
| 3573 | // 7136: } |
| 3574 | // 7136: } // switch Inst[17:15] |
| 3575 | // 7136: } |
| 3576 | 56, 51, // 7140: case 0x38: { |
| 3577 | OPC_SwitchField, 15, 3, // 7142: switch Inst[17:15] { |
| 3578 | 0, 4, // 7145: case 0x0: { |
| 3579 | OPC_Decode, 249, 7, 63, // 7147: decode to VDIV_B using decoder 63 |
| 3580 | // 7147: } |
| 3581 | 1, 4, // 7151: case 0x1: { |
| 3582 | OPC_Decode, 253, 7, 63, // 7153: decode to VDIV_H using decoder 63 |
| 3583 | // 7153: } |
| 3584 | 2, 4, // 7157: case 0x2: { |
| 3585 | OPC_Decode, 255, 7, 63, // 7159: decode to VDIV_W using decoder 63 |
| 3586 | // 7159: } |
| 3587 | 3, 4, // 7163: case 0x3: { |
| 3588 | OPC_Decode, 251, 7, 63, // 7165: decode to VDIV_D using decoder 63 |
| 3589 | // 7165: } |
| 3590 | 4, 4, // 7169: case 0x4: { |
| 3591 | OPC_Decode, 132, 10, 63, // 7171: decode to VMOD_B using decoder 63 |
| 3592 | // 7171: } |
| 3593 | 5, 4, // 7175: case 0x5: { |
| 3594 | OPC_Decode, 136, 10, 63, // 7177: decode to VMOD_H using decoder 63 |
| 3595 | // 7177: } |
| 3596 | 6, 4, // 7181: case 0x6: { |
| 3597 | OPC_Decode, 138, 10, 63, // 7183: decode to VMOD_W using decoder 63 |
| 3598 | // 7183: } |
| 3599 | 7, 0, // 7187: case 0x7: { |
| 3600 | OPC_Decode, 134, 10, 63, // 7189: decode to VMOD_D using decoder 63 |
| 3601 | // 7189: } |
| 3602 | // 7189: } // switch Inst[17:15] |
| 3603 | // 7189: } |
| 3604 | 57, 51, // 7193: case 0x39: { |
| 3605 | OPC_SwitchField, 15, 3, // 7195: switch Inst[17:15] { |
| 3606 | 0, 4, // 7198: case 0x0: { |
| 3607 | OPC_Decode, 250, 7, 63, // 7200: decode to VDIV_BU using decoder 63 |
| 3608 | // 7200: } |
| 3609 | 1, 4, // 7204: case 0x1: { |
| 3610 | OPC_Decode, 254, 7, 63, // 7206: decode to VDIV_HU using decoder 63 |
| 3611 | // 7206: } |
| 3612 | 2, 4, // 7210: case 0x2: { |
| 3613 | OPC_Decode, 128, 8, 63, // 7212: decode to VDIV_WU using decoder 63 |
| 3614 | // 7212: } |
| 3615 | 3, 4, // 7216: case 0x3: { |
| 3616 | OPC_Decode, 252, 7, 63, // 7218: decode to VDIV_DU using decoder 63 |
| 3617 | // 7218: } |
| 3618 | 4, 4, // 7222: case 0x4: { |
| 3619 | OPC_Decode, 133, 10, 63, // 7224: decode to VMOD_BU using decoder 63 |
| 3620 | // 7224: } |
| 3621 | 5, 4, // 7228: case 0x5: { |
| 3622 | OPC_Decode, 137, 10, 63, // 7230: decode to VMOD_HU using decoder 63 |
| 3623 | // 7230: } |
| 3624 | 6, 4, // 7234: case 0x6: { |
| 3625 | OPC_Decode, 139, 10, 63, // 7236: decode to VMOD_WU using decoder 63 |
| 3626 | // 7236: } |
| 3627 | 7, 0, // 7240: case 0x7: { |
| 3628 | OPC_Decode, 135, 10, 63, // 7242: decode to VMOD_DU using decoder 63 |
| 3629 | // 7242: } |
| 3630 | // 7242: } // switch Inst[17:15] |
| 3631 | // 7242: } |
| 3632 | 58, 51, // 7246: case 0x3a: { |
| 3633 | OPC_SwitchField, 15, 3, // 7248: switch Inst[17:15] { |
| 3634 | 0, 4, // 7251: case 0x0: { |
| 3635 | OPC_Decode, 188, 11, 63, // 7253: decode to VSLL_B using decoder 63 |
| 3636 | // 7253: } |
| 3637 | 1, 4, // 7257: case 0x1: { |
| 3638 | OPC_Decode, 190, 11, 63, // 7259: decode to VSLL_H using decoder 63 |
| 3639 | // 7259: } |
| 3640 | 2, 4, // 7263: case 0x2: { |
| 3641 | OPC_Decode, 191, 11, 63, // 7265: decode to VSLL_W using decoder 63 |
| 3642 | // 7265: } |
| 3643 | 3, 4, // 7269: case 0x3: { |
| 3644 | OPC_Decode, 189, 11, 63, // 7271: decode to VSLL_D using decoder 63 |
| 3645 | // 7271: } |
| 3646 | 4, 4, // 7275: case 0x4: { |
| 3647 | OPC_Decode, 136, 12, 63, // 7277: decode to VSRL_B using decoder 63 |
| 3648 | // 7277: } |
| 3649 | 5, 4, // 7281: case 0x5: { |
| 3650 | OPC_Decode, 138, 12, 63, // 7283: decode to VSRL_H using decoder 63 |
| 3651 | // 7283: } |
| 3652 | 6, 4, // 7287: case 0x6: { |
| 3653 | OPC_Decode, 139, 12, 63, // 7289: decode to VSRL_W using decoder 63 |
| 3654 | // 7289: } |
| 3655 | 7, 0, // 7293: case 0x7: { |
| 3656 | OPC_Decode, 137, 12, 63, // 7295: decode to VSRL_D using decoder 63 |
| 3657 | // 7295: } |
| 3658 | // 7295: } // switch Inst[17:15] |
| 3659 | // 7295: } |
| 3660 | 59, 51, // 7299: case 0x3b: { |
| 3661 | OPC_SwitchField, 15, 3, // 7301: switch Inst[17:15] { |
| 3662 | 0, 4, // 7304: case 0x0: { |
| 3663 | OPC_Decode, 234, 11, 63, // 7306: decode to VSRA_B using decoder 63 |
| 3664 | // 7306: } |
| 3665 | 1, 4, // 7310: case 0x1: { |
| 3666 | OPC_Decode, 236, 11, 63, // 7312: decode to VSRA_H using decoder 63 |
| 3667 | // 7312: } |
| 3668 | 2, 4, // 7316: case 0x2: { |
| 3669 | OPC_Decode, 237, 11, 63, // 7318: decode to VSRA_W using decoder 63 |
| 3670 | // 7318: } |
| 3671 | 3, 4, // 7322: case 0x3: { |
| 3672 | OPC_Decode, 235, 11, 63, // 7324: decode to VSRA_D using decoder 63 |
| 3673 | // 7324: } |
| 3674 | 4, 4, // 7328: case 0x4: { |
| 3675 | OPC_Decode, 240, 10, 63, // 7330: decode to VROTR_B using decoder 63 |
| 3676 | // 7330: } |
| 3677 | 5, 4, // 7334: case 0x5: { |
| 3678 | OPC_Decode, 242, 10, 63, // 7336: decode to VROTR_H using decoder 63 |
| 3679 | // 7336: } |
| 3680 | 6, 4, // 7340: case 0x6: { |
| 3681 | OPC_Decode, 243, 10, 63, // 7342: decode to VROTR_W using decoder 63 |
| 3682 | // 7342: } |
| 3683 | 7, 0, // 7346: case 0x7: { |
| 3684 | OPC_Decode, 241, 10, 63, // 7348: decode to VROTR_D using decoder 63 |
| 3685 | // 7348: } |
| 3686 | // 7348: } // switch Inst[17:15] |
| 3687 | // 7348: } |
| 3688 | 60, 51, // 7352: case 0x3c: { |
| 3689 | OPC_SwitchField, 15, 3, // 7354: switch Inst[17:15] { |
| 3690 | 0, 4, // 7357: case 0x0: { |
| 3691 | OPC_Decode, 132, 12, 63, // 7359: decode to VSRLR_B using decoder 63 |
| 3692 | // 7359: } |
| 3693 | 1, 4, // 7363: case 0x1: { |
| 3694 | OPC_Decode, 134, 12, 63, // 7365: decode to VSRLR_H using decoder 63 |
| 3695 | // 7365: } |
| 3696 | 2, 4, // 7369: case 0x2: { |
| 3697 | OPC_Decode, 135, 12, 63, // 7371: decode to VSRLR_W using decoder 63 |
| 3698 | // 7371: } |
| 3699 | 3, 4, // 7375: case 0x3: { |
| 3700 | OPC_Decode, 133, 12, 63, // 7377: decode to VSRLR_D using decoder 63 |
| 3701 | // 7377: } |
| 3702 | 4, 4, // 7381: case 0x4: { |
| 3703 | OPC_Decode, 230, 11, 63, // 7383: decode to VSRAR_B using decoder 63 |
| 3704 | // 7383: } |
| 3705 | 5, 4, // 7387: case 0x5: { |
| 3706 | OPC_Decode, 232, 11, 63, // 7389: decode to VSRAR_H using decoder 63 |
| 3707 | // 7389: } |
| 3708 | 6, 4, // 7393: case 0x6: { |
| 3709 | OPC_Decode, 233, 11, 63, // 7395: decode to VSRAR_W using decoder 63 |
| 3710 | // 7395: } |
| 3711 | 7, 0, // 7399: case 0x7: { |
| 3712 | OPC_Decode, 231, 11, 63, // 7401: decode to VSRAR_D using decoder 63 |
| 3713 | // 7401: } |
| 3714 | // 7401: } // switch Inst[17:15] |
| 3715 | // 7401: } |
| 3716 | 61, 39, // 7405: case 0x3d: { |
| 3717 | OPC_SwitchField, 15, 3, // 7407: switch Inst[17:15] { |
| 3718 | 1, 4, // 7410: case 0x1: { |
| 3719 | OPC_Decode, 246, 11, 63, // 7412: decode to VSRLN_B_H using decoder 63 |
| 3720 | // 7412: } |
| 3721 | 2, 4, // 7416: case 0x2: { |
| 3722 | OPC_Decode, 247, 11, 63, // 7418: decode to VSRLN_H_W using decoder 63 |
| 3723 | // 7418: } |
| 3724 | 3, 4, // 7422: case 0x3: { |
| 3725 | OPC_Decode, 248, 11, 63, // 7424: decode to VSRLN_W_D using decoder 63 |
| 3726 | // 7424: } |
| 3727 | 5, 4, // 7428: case 0x5: { |
| 3728 | OPC_Decode, 216, 11, 63, // 7430: decode to VSRAN_B_H using decoder 63 |
| 3729 | // 7430: } |
| 3730 | 6, 4, // 7434: case 0x6: { |
| 3731 | OPC_Decode, 217, 11, 63, // 7436: decode to VSRAN_H_W using decoder 63 |
| 3732 | // 7436: } |
| 3733 | 7, 0, // 7440: case 0x7: { |
| 3734 | OPC_Decode, 218, 11, 63, // 7442: decode to VSRAN_W_D using decoder 63 |
| 3735 | // 7442: } |
| 3736 | // 7442: } // switch Inst[17:15] |
| 3737 | // 7442: } |
| 3738 | 62, 39, // 7446: case 0x3e: { |
| 3739 | OPC_SwitchField, 15, 3, // 7448: switch Inst[17:15] { |
| 3740 | 1, 4, // 7451: case 0x1: { |
| 3741 | OPC_Decode, 129, 12, 63, // 7453: decode to VSRLRN_B_H using decoder 63 |
| 3742 | // 7453: } |
| 3743 | 2, 4, // 7457: case 0x2: { |
| 3744 | OPC_Decode, 130, 12, 63, // 7459: decode to VSRLRN_H_W using decoder 63 |
| 3745 | // 7459: } |
| 3746 | 3, 4, // 7463: case 0x3: { |
| 3747 | OPC_Decode, 131, 12, 63, // 7465: decode to VSRLRN_W_D using decoder 63 |
| 3748 | // 7465: } |
| 3749 | 5, 4, // 7469: case 0x5: { |
| 3750 | OPC_Decode, 227, 11, 63, // 7471: decode to VSRARN_B_H using decoder 63 |
| 3751 | // 7471: } |
| 3752 | 6, 4, // 7475: case 0x6: { |
| 3753 | OPC_Decode, 228, 11, 63, // 7477: decode to VSRARN_H_W using decoder 63 |
| 3754 | // 7477: } |
| 3755 | 7, 0, // 7481: case 0x7: { |
| 3756 | OPC_Decode, 229, 11, 63, // 7483: decode to VSRARN_W_D using decoder 63 |
| 3757 | // 7483: } |
| 3758 | // 7483: } // switch Inst[17:15] |
| 3759 | // 7483: } |
| 3760 | 63, 39, // 7487: case 0x3f: { |
| 3761 | OPC_SwitchField, 15, 3, // 7489: switch Inst[17:15] { |
| 3762 | 1, 4, // 7492: case 0x1: { |
| 3763 | OPC_Decode, 177, 12, 63, // 7494: decode to VSSRLN_B_H using decoder 63 |
| 3764 | // 7494: } |
| 3765 | 2, 4, // 7498: case 0x2: { |
| 3766 | OPC_Decode, 179, 12, 63, // 7500: decode to VSSRLN_H_W using decoder 63 |
| 3767 | // 7500: } |
| 3768 | 3, 4, // 7504: case 0x3: { |
| 3769 | OPC_Decode, 181, 12, 63, // 7506: decode to VSSRLN_W_D using decoder 63 |
| 3770 | // 7506: } |
| 3771 | 5, 4, // 7510: case 0x5: { |
| 3772 | OPC_Decode, 149, 12, 63, // 7512: decode to VSSRAN_B_H using decoder 63 |
| 3773 | // 7512: } |
| 3774 | 6, 4, // 7516: case 0x6: { |
| 3775 | OPC_Decode, 151, 12, 63, // 7518: decode to VSSRAN_H_W using decoder 63 |
| 3776 | // 7518: } |
| 3777 | 7, 0, // 7522: case 0x7: { |
| 3778 | OPC_Decode, 153, 12, 63, // 7524: decode to VSSRAN_W_D using decoder 63 |
| 3779 | // 7524: } |
| 3780 | // 7524: } // switch Inst[17:15] |
| 3781 | // 7524: } |
| 3782 | 64, 39, // 7528: case 0x40: { |
| 3783 | OPC_SwitchField, 15, 3, // 7530: switch Inst[17:15] { |
| 3784 | 1, 4, // 7533: case 0x1: { |
| 3785 | OPC_Decode, 191, 12, 63, // 7535: decode to VSSRLRN_B_H using decoder 63 |
| 3786 | // 7535: } |
| 3787 | 2, 4, // 7539: case 0x2: { |
| 3788 | OPC_Decode, 193, 12, 63, // 7541: decode to VSSRLRN_H_W using decoder 63 |
| 3789 | // 7541: } |
| 3790 | 3, 4, // 7545: case 0x3: { |
| 3791 | OPC_Decode, 195, 12, 63, // 7547: decode to VSSRLRN_W_D using decoder 63 |
| 3792 | // 7547: } |
| 3793 | 5, 4, // 7551: case 0x5: { |
| 3794 | OPC_Decode, 163, 12, 63, // 7553: decode to VSSRARN_B_H using decoder 63 |
| 3795 | // 7553: } |
| 3796 | 6, 4, // 7557: case 0x6: { |
| 3797 | OPC_Decode, 165, 12, 63, // 7559: decode to VSSRARN_H_W using decoder 63 |
| 3798 | // 7559: } |
| 3799 | 7, 0, // 7563: case 0x7: { |
| 3800 | OPC_Decode, 167, 12, 63, // 7565: decode to VSSRARN_W_D using decoder 63 |
| 3801 | // 7565: } |
| 3802 | // 7565: } // switch Inst[17:15] |
| 3803 | // 7565: } |
| 3804 | 65, 39, // 7569: case 0x41: { |
| 3805 | OPC_SwitchField, 15, 3, // 7571: switch Inst[17:15] { |
| 3806 | 1, 4, // 7574: case 0x1: { |
| 3807 | OPC_Decode, 176, 12, 63, // 7576: decode to VSSRLN_BU_H using decoder 63 |
| 3808 | // 7576: } |
| 3809 | 2, 4, // 7580: case 0x2: { |
| 3810 | OPC_Decode, 178, 12, 63, // 7582: decode to VSSRLN_HU_W using decoder 63 |
| 3811 | // 7582: } |
| 3812 | 3, 4, // 7586: case 0x3: { |
| 3813 | OPC_Decode, 180, 12, 63, // 7588: decode to VSSRLN_WU_D using decoder 63 |
| 3814 | // 7588: } |
| 3815 | 5, 4, // 7592: case 0x5: { |
| 3816 | OPC_Decode, 148, 12, 63, // 7594: decode to VSSRAN_BU_H using decoder 63 |
| 3817 | // 7594: } |
| 3818 | 6, 4, // 7598: case 0x6: { |
| 3819 | OPC_Decode, 150, 12, 63, // 7600: decode to VSSRAN_HU_W using decoder 63 |
| 3820 | // 7600: } |
| 3821 | 7, 0, // 7604: case 0x7: { |
| 3822 | OPC_Decode, 152, 12, 63, // 7606: decode to VSSRAN_WU_D using decoder 63 |
| 3823 | // 7606: } |
| 3824 | // 7606: } // switch Inst[17:15] |
| 3825 | // 7606: } |
| 3826 | 66, 39, // 7610: case 0x42: { |
| 3827 | OPC_SwitchField, 15, 3, // 7612: switch Inst[17:15] { |
| 3828 | 1, 4, // 7615: case 0x1: { |
| 3829 | OPC_Decode, 190, 12, 63, // 7617: decode to VSSRLRN_BU_H using decoder 63 |
| 3830 | // 7617: } |
| 3831 | 2, 4, // 7621: case 0x2: { |
| 3832 | OPC_Decode, 192, 12, 63, // 7623: decode to VSSRLRN_HU_W using decoder 63 |
| 3833 | // 7623: } |
| 3834 | 3, 4, // 7627: case 0x3: { |
| 3835 | OPC_Decode, 194, 12, 63, // 7629: decode to VSSRLRN_WU_D using decoder 63 |
| 3836 | // 7629: } |
| 3837 | 5, 4, // 7633: case 0x5: { |
| 3838 | OPC_Decode, 162, 12, 63, // 7635: decode to VSSRARN_BU_H using decoder 63 |
| 3839 | // 7635: } |
| 3840 | 6, 4, // 7639: case 0x6: { |
| 3841 | OPC_Decode, 164, 12, 63, // 7641: decode to VSSRARN_HU_W using decoder 63 |
| 3842 | // 7641: } |
| 3843 | 7, 0, // 7645: case 0x7: { |
| 3844 | OPC_Decode, 166, 12, 63, // 7647: decode to VSSRARN_WU_D using decoder 63 |
| 3845 | // 7647: } |
| 3846 | // 7647: } // switch Inst[17:15] |
| 3847 | // 7647: } |
| 3848 | 67, 51, // 7651: case 0x43: { |
| 3849 | OPC_SwitchField, 15, 3, // 7653: switch Inst[17:15] { |
| 3850 | 0, 4, // 7656: case 0x0: { |
| 3851 | OPC_Decode, 217, 7, 63, // 7658: decode to VBITCLR_B using decoder 63 |
| 3852 | // 7658: } |
| 3853 | 1, 4, // 7662: case 0x1: { |
| 3854 | OPC_Decode, 219, 7, 63, // 7664: decode to VBITCLR_H using decoder 63 |
| 3855 | // 7664: } |
| 3856 | 2, 4, // 7668: case 0x2: { |
| 3857 | OPC_Decode, 220, 7, 63, // 7670: decode to VBITCLR_W using decoder 63 |
| 3858 | // 7670: } |
| 3859 | 3, 4, // 7674: case 0x3: { |
| 3860 | OPC_Decode, 218, 7, 63, // 7676: decode to VBITCLR_D using decoder 63 |
| 3861 | // 7676: } |
| 3862 | 4, 4, // 7680: case 0x4: { |
| 3863 | OPC_Decode, 235, 7, 63, // 7682: decode to VBITSET_B using decoder 63 |
| 3864 | // 7682: } |
| 3865 | 5, 4, // 7686: case 0x5: { |
| 3866 | OPC_Decode, 237, 7, 63, // 7688: decode to VBITSET_H using decoder 63 |
| 3867 | // 7688: } |
| 3868 | 6, 4, // 7692: case 0x6: { |
| 3869 | OPC_Decode, 238, 7, 63, // 7694: decode to VBITSET_W using decoder 63 |
| 3870 | // 7694: } |
| 3871 | 7, 0, // 7698: case 0x7: { |
| 3872 | OPC_Decode, 236, 7, 63, // 7700: decode to VBITSET_D using decoder 63 |
| 3873 | // 7700: } |
| 3874 | // 7700: } // switch Inst[17:15] |
| 3875 | // 7700: } |
| 3876 | 68, 27, // 7704: case 0x44: { |
| 3877 | OPC_SwitchField, 15, 3, // 7706: switch Inst[17:15] { |
| 3878 | 0, 4, // 7709: case 0x0: { |
| 3879 | OPC_Decode, 225, 7, 63, // 7711: decode to VBITREV_B using decoder 63 |
| 3880 | // 7711: } |
| 3881 | 1, 4, // 7715: case 0x1: { |
| 3882 | OPC_Decode, 227, 7, 63, // 7717: decode to VBITREV_H using decoder 63 |
| 3883 | // 7717: } |
| 3884 | 2, 4, // 7721: case 0x2: { |
| 3885 | OPC_Decode, 228, 7, 63, // 7723: decode to VBITREV_W using decoder 63 |
| 3886 | // 7723: } |
| 3887 | 3, 0, // 7727: case 0x3: { |
| 3888 | OPC_Decode, 226, 7, 63, // 7729: decode to VBITREV_D using decoder 63 |
| 3889 | // 7729: } |
| 3890 | // 7729: } // switch Inst[17:15] |
| 3891 | // 7729: } |
| 3892 | 69, 27, // 7733: case 0x45: { |
| 3893 | OPC_SwitchField, 15, 3, // 7735: switch Inst[17:15] { |
| 3894 | 4, 4, // 7738: case 0x4: { |
| 3895 | OPC_Decode, 195, 10, 63, // 7740: decode to VPACKEV_B using decoder 63 |
| 3896 | // 7740: } |
| 3897 | 5, 4, // 7744: case 0x5: { |
| 3898 | OPC_Decode, 197, 10, 63, // 7746: decode to VPACKEV_H using decoder 63 |
| 3899 | // 7746: } |
| 3900 | 6, 4, // 7750: case 0x6: { |
| 3901 | OPC_Decode, 198, 10, 63, // 7752: decode to VPACKEV_W using decoder 63 |
| 3902 | // 7752: } |
| 3903 | 7, 0, // 7756: case 0x7: { |
| 3904 | OPC_Decode, 196, 10, 63, // 7758: decode to VPACKEV_D using decoder 63 |
| 3905 | // 7758: } |
| 3906 | // 7758: } // switch Inst[17:15] |
| 3907 | // 7758: } |
| 3908 | 70, 51, // 7762: case 0x46: { |
| 3909 | OPC_SwitchField, 15, 3, // 7764: switch Inst[17:15] { |
| 3910 | 0, 4, // 7767: case 0x0: { |
| 3911 | OPC_Decode, 199, 10, 63, // 7769: decode to VPACKOD_B using decoder 63 |
| 3912 | // 7769: } |
| 3913 | 1, 4, // 7773: case 0x1: { |
| 3914 | OPC_Decode, 201, 10, 63, // 7775: decode to VPACKOD_H using decoder 63 |
| 3915 | // 7775: } |
| 3916 | 2, 4, // 7779: case 0x2: { |
| 3917 | OPC_Decode, 202, 10, 63, // 7781: decode to VPACKOD_W using decoder 63 |
| 3918 | // 7781: } |
| 3919 | 3, 4, // 7785: case 0x3: { |
| 3920 | OPC_Decode, 200, 10, 63, // 7787: decode to VPACKOD_D using decoder 63 |
| 3921 | // 7787: } |
| 3922 | 4, 4, // 7791: case 0x4: { |
| 3923 | OPC_Decode, 185, 9, 63, // 7793: decode to VILVL_B using decoder 63 |
| 3924 | // 7793: } |
| 3925 | 5, 4, // 7797: case 0x5: { |
| 3926 | OPC_Decode, 187, 9, 63, // 7799: decode to VILVL_H using decoder 63 |
| 3927 | // 7799: } |
| 3928 | 6, 4, // 7803: case 0x6: { |
| 3929 | OPC_Decode, 188, 9, 63, // 7805: decode to VILVL_W using decoder 63 |
| 3930 | // 7805: } |
| 3931 | 7, 0, // 7809: case 0x7: { |
| 3932 | OPC_Decode, 186, 9, 63, // 7811: decode to VILVL_D using decoder 63 |
| 3933 | // 7811: } |
| 3934 | // 7811: } // switch Inst[17:15] |
| 3935 | // 7811: } |
| 3936 | 71, 51, // 7815: case 0x47: { |
| 3937 | OPC_SwitchField, 15, 3, // 7817: switch Inst[17:15] { |
| 3938 | 0, 4, // 7820: case 0x0: { |
| 3939 | OPC_Decode, 181, 9, 63, // 7822: decode to VILVH_B using decoder 63 |
| 3940 | // 7822: } |
| 3941 | 1, 4, // 7826: case 0x1: { |
| 3942 | OPC_Decode, 183, 9, 63, // 7828: decode to VILVH_H using decoder 63 |
| 3943 | // 7828: } |
| 3944 | 2, 4, // 7832: case 0x2: { |
| 3945 | OPC_Decode, 184, 9, 63, // 7834: decode to VILVH_W using decoder 63 |
| 3946 | // 7834: } |
| 3947 | 3, 4, // 7838: case 0x3: { |
| 3948 | OPC_Decode, 182, 9, 63, // 7840: decode to VILVH_D using decoder 63 |
| 3949 | // 7840: } |
| 3950 | 4, 4, // 7844: case 0x4: { |
| 3951 | OPC_Decode, 208, 10, 63, // 7846: decode to VPICKEV_B using decoder 63 |
| 3952 | // 7846: } |
| 3953 | 5, 4, // 7850: case 0x5: { |
| 3954 | OPC_Decode, 210, 10, 63, // 7852: decode to VPICKEV_H using decoder 63 |
| 3955 | // 7852: } |
| 3956 | 6, 4, // 7856: case 0x6: { |
| 3957 | OPC_Decode, 211, 10, 63, // 7858: decode to VPICKEV_W using decoder 63 |
| 3958 | // 7858: } |
| 3959 | 7, 0, // 7862: case 0x7: { |
| 3960 | OPC_Decode, 209, 10, 63, // 7864: decode to VPICKEV_D using decoder 63 |
| 3961 | // 7864: } |
| 3962 | // 7864: } // switch Inst[17:15] |
| 3963 | // 7864: } |
| 3964 | 72, 51, // 7868: case 0x48: { |
| 3965 | OPC_SwitchField, 15, 3, // 7870: switch Inst[17:15] { |
| 3966 | 0, 4, // 7873: case 0x0: { |
| 3967 | OPC_Decode, 212, 10, 63, // 7875: decode to VPICKOD_B using decoder 63 |
| 3968 | // 7875: } |
| 3969 | 1, 4, // 7879: case 0x1: { |
| 3970 | OPC_Decode, 214, 10, 63, // 7881: decode to VPICKOD_H using decoder 63 |
| 3971 | // 7881: } |
| 3972 | 2, 4, // 7885: case 0x2: { |
| 3973 | OPC_Decode, 215, 10, 63, // 7887: decode to VPICKOD_W using decoder 63 |
| 3974 | // 7887: } |
| 3975 | 3, 4, // 7891: case 0x3: { |
| 3976 | OPC_Decode, 213, 10, 63, // 7893: decode to VPICKOD_D using decoder 63 |
| 3977 | // 7893: } |
| 3978 | 4, 4, // 7897: case 0x4: { |
| 3979 | OPC_Decode, 232, 10, 105, // 7899: decode to VREPLVE_B using decoder 105 |
| 3980 | // 7899: } |
| 3981 | 5, 4, // 7903: case 0x5: { |
| 3982 | OPC_Decode, 234, 10, 105, // 7905: decode to VREPLVE_H using decoder 105 |
| 3983 | // 7905: } |
| 3984 | 6, 4, // 7909: case 0x6: { |
| 3985 | OPC_Decode, 235, 10, 105, // 7911: decode to VREPLVE_W using decoder 105 |
| 3986 | // 7911: } |
| 3987 | 7, 0, // 7915: case 0x7: { |
| 3988 | OPC_Decode, 233, 10, 105, // 7917: decode to VREPLVE_D using decoder 105 |
| 3989 | // 7917: } |
| 3990 | // 7917: } // switch Inst[17:15] |
| 3991 | // 7917: } |
| 3992 | 73, 27, // 7921: case 0x49: { |
| 3993 | OPC_SwitchField, 15, 3, // 7923: switch Inst[17:15] { |
| 3994 | 4, 4, // 7926: case 0x4: { |
| 3995 | OPC_Decode, 196, 7, 63, // 7928: decode to VAND_V using decoder 63 |
| 3996 | // 7928: } |
| 3997 | 5, 4, // 7932: case 0x5: { |
| 3998 | OPC_Decode, 194, 10, 63, // 7934: decode to VOR_V using decoder 63 |
| 3999 | // 7934: } |
| 4000 | 6, 4, // 7938: case 0x6: { |
| 4001 | OPC_Decode, 236, 12, 63, // 7940: decode to VXOR_V using decoder 63 |
| 4002 | // 7940: } |
| 4003 | 7, 0, // 7944: case 0x7: { |
| 4004 | OPC_Decode, 191, 10, 63, // 7946: decode to VNOR_V using decoder 63 |
| 4005 | // 7946: } |
| 4006 | // 7946: } // switch Inst[17:15] |
| 4007 | // 7946: } |
| 4008 | 74, 27, // 7950: case 0x4a: { |
| 4009 | OPC_SwitchField, 15, 3, // 7952: switch Inst[17:15] { |
| 4010 | 0, 4, // 7955: case 0x0: { |
| 4011 | OPC_Decode, 195, 7, 63, // 7957: decode to VANDN_V using decoder 63 |
| 4012 | // 7957: } |
| 4013 | 1, 4, // 7961: case 0x1: { |
| 4014 | OPC_Decode, 193, 10, 63, // 7963: decode to VORN_V using decoder 63 |
| 4015 | // 7963: } |
| 4016 | 6, 4, // 7967: case 0x6: { |
| 4017 | OPC_Decode, 130, 9, 104, // 7969: decode to VFRSTP_B using decoder 104 |
| 4018 | // 7969: } |
| 4019 | 7, 0, // 7973: case 0x7: { |
| 4020 | OPC_Decode, 131, 9, 104, // 7975: decode to VFRSTP_H using decoder 104 |
| 4021 | // 7975: } |
| 4022 | // 7975: } // switch Inst[17:15] |
| 4023 | // 7975: } |
| 4024 | 75, 39, // 7979: case 0x4b: { |
| 4025 | OPC_SwitchField, 15, 3, // 7981: switch Inst[17:15] { |
| 4026 | 2, 4, // 7984: case 0x2: { |
| 4027 | OPC_Decode, 192, 7, 63, // 7986: decode to VADD_Q using decoder 63 |
| 4028 | // 7986: } |
| 4029 | 3, 4, // 7990: case 0x3: { |
| 4030 | OPC_Decode, 233, 12, 63, // 7992: decode to VSUB_Q using decoder 63 |
| 4031 | // 7992: } |
| 4032 | 4, 4, // 7996: case 0x4: { |
| 4033 | OPC_Decode, 158, 11, 63, // 7998: decode to VSIGNCOV_B using decoder 63 |
| 4034 | // 7998: } |
| 4035 | 5, 4, // 8002: case 0x5: { |
| 4036 | OPC_Decode, 160, 11, 63, // 8004: decode to VSIGNCOV_H using decoder 63 |
| 4037 | // 8004: } |
| 4038 | 6, 4, // 8008: case 0x6: { |
| 4039 | OPC_Decode, 161, 11, 63, // 8010: decode to VSIGNCOV_W using decoder 63 |
| 4040 | // 8010: } |
| 4041 | 7, 0, // 8014: case 0x7: { |
| 4042 | OPC_Decode, 159, 11, 63, // 8016: decode to VSIGNCOV_D using decoder 63 |
| 4043 | // 8016: } |
| 4044 | // 8016: } // switch Inst[17:15] |
| 4045 | // 8016: } |
| 4046 | 76, 27, // 8020: case 0x4c: { |
| 4047 | OPC_SwitchField, 15, 3, // 8022: switch Inst[17:15] { |
| 4048 | 1, 4, // 8025: case 0x1: { |
| 4049 | OPC_Decode, 156, 8, 63, // 8027: decode to VFADD_S using decoder 63 |
| 4050 | // 8027: } |
| 4051 | 2, 4, // 8031: case 0x2: { |
| 4052 | OPC_Decode, 155, 8, 63, // 8033: decode to VFADD_D using decoder 63 |
| 4053 | // 8033: } |
| 4054 | 5, 4, // 8037: case 0x5: { |
| 4055 | OPC_Decode, 135, 9, 63, // 8039: decode to VFSUB_S using decoder 63 |
| 4056 | // 8039: } |
| 4057 | 6, 0, // 8043: case 0x6: { |
| 4058 | OPC_Decode, 134, 9, 63, // 8045: decode to VFSUB_D using decoder 63 |
| 4059 | // 8045: } |
| 4060 | // 8045: } // switch Inst[17:15] |
| 4061 | // 8045: } |
| 4062 | 78, 27, // 8049: case 0x4e: { |
| 4063 | OPC_SwitchField, 15, 3, // 8051: switch Inst[17:15] { |
| 4064 | 1, 4, // 8054: case 0x1: { |
| 4065 | OPC_Decode, 233, 8, 63, // 8056: decode to VFMUL_S using decoder 63 |
| 4066 | // 8056: } |
| 4067 | 2, 4, // 8060: case 0x2: { |
| 4068 | OPC_Decode, 232, 8, 63, // 8062: decode to VFMUL_D using decoder 63 |
| 4069 | // 8062: } |
| 4070 | 5, 4, // 8066: case 0x5: { |
| 4071 | OPC_Decode, 210, 8, 63, // 8068: decode to VFDIV_S using decoder 63 |
| 4072 | // 8068: } |
| 4073 | 6, 0, // 8072: case 0x6: { |
| 4074 | OPC_Decode, 209, 8, 63, // 8074: decode to VFDIV_D using decoder 63 |
| 4075 | // 8074: } |
| 4076 | // 8074: } // switch Inst[17:15] |
| 4077 | // 8074: } |
| 4078 | 79, 27, // 8078: case 0x4f: { |
| 4079 | OPC_SwitchField, 15, 3, // 8080: switch Inst[17:15] { |
| 4080 | 1, 4, // 8083: case 0x1: { |
| 4081 | OPC_Decode, 225, 8, 63, // 8085: decode to VFMAX_S using decoder 63 |
| 4082 | // 8085: } |
| 4083 | 2, 4, // 8089: case 0x2: { |
| 4084 | OPC_Decode, 224, 8, 63, // 8091: decode to VFMAX_D using decoder 63 |
| 4085 | // 8091: } |
| 4086 | 5, 4, // 8095: case 0x5: { |
| 4087 | OPC_Decode, 229, 8, 63, // 8097: decode to VFMIN_S using decoder 63 |
| 4088 | // 8097: } |
| 4089 | 6, 0, // 8101: case 0x6: { |
| 4090 | OPC_Decode, 228, 8, 63, // 8103: decode to VFMIN_D using decoder 63 |
| 4091 | // 8103: } |
| 4092 | // 8103: } // switch Inst[17:15] |
| 4093 | // 8103: } |
| 4094 | 80, 27, // 8107: case 0x50: { |
| 4095 | OPC_SwitchField, 15, 3, // 8109: switch Inst[17:15] { |
| 4096 | 1, 4, // 8112: case 0x1: { |
| 4097 | OPC_Decode, 223, 8, 63, // 8114: decode to VFMAXA_S using decoder 63 |
| 4098 | // 8114: } |
| 4099 | 2, 4, // 8118: case 0x2: { |
| 4100 | OPC_Decode, 222, 8, 63, // 8120: decode to VFMAXA_D using decoder 63 |
| 4101 | // 8120: } |
| 4102 | 5, 4, // 8124: case 0x5: { |
| 4103 | OPC_Decode, 227, 8, 63, // 8126: decode to VFMINA_S using decoder 63 |
| 4104 | // 8126: } |
| 4105 | 6, 0, // 8130: case 0x6: { |
| 4106 | OPC_Decode, 226, 8, 63, // 8132: decode to VFMINA_D using decoder 63 |
| 4107 | // 8132: } |
| 4108 | // 8132: } // switch Inst[17:15] |
| 4109 | // 8132: } |
| 4110 | 81, 15, // 8136: case 0x51: { |
| 4111 | OPC_SwitchField, 15, 3, // 8138: switch Inst[17:15] { |
| 4112 | 4, 4, // 8141: case 0x4: { |
| 4113 | OPC_Decode, 207, 8, 63, // 8143: decode to VFCVT_H_S using decoder 63 |
| 4114 | // 8143: } |
| 4115 | 5, 0, // 8147: case 0x5: { |
| 4116 | OPC_Decode, 208, 8, 63, // 8149: decode to VFCVT_S_D using decoder 63 |
| 4117 | // 8149: } |
| 4118 | // 8149: } // switch Inst[17:15] |
| 4119 | // 8149: } |
| 4120 | 82, 39, // 8153: case 0x52: { |
| 4121 | OPC_SwitchField, 15, 3, // 8155: switch Inst[17:15] { |
| 4122 | 0, 4, // 8158: case 0x0: { |
| 4123 | OPC_Decode, 215, 8, 63, // 8160: decode to VFFINT_S_L using decoder 63 |
| 4124 | // 8160: } |
| 4125 | 3, 4, // 8164: case 0x3: { |
| 4126 | OPC_Decode, 163, 9, 63, // 8166: decode to VFTINT_W_D using decoder 63 |
| 4127 | // 8166: } |
| 4128 | 4, 4, // 8170: case 0x4: { |
| 4129 | OPC_Decode, 141, 9, 63, // 8172: decode to VFTINTRM_W_D using decoder 63 |
| 4130 | // 8172: } |
| 4131 | 5, 4, // 8176: case 0x5: { |
| 4132 | OPC_Decode, 151, 9, 63, // 8178: decode to VFTINTRP_W_D using decoder 63 |
| 4133 | // 8178: } |
| 4134 | 6, 4, // 8182: case 0x6: { |
| 4135 | OPC_Decode, 158, 9, 63, // 8184: decode to VFTINTRZ_W_D using decoder 63 |
| 4136 | // 8184: } |
| 4137 | 7, 0, // 8188: case 0x7: { |
| 4138 | OPC_Decode, 146, 9, 63, // 8190: decode to VFTINTRNE_W_D using decoder 63 |
| 4139 | // 8190: } |
| 4140 | // 8190: } // switch Inst[17:15] |
| 4141 | // 8190: } |
| 4142 | 94, 21, // 8194: case 0x5e: { |
| 4143 | OPC_SwitchField, 15, 3, // 8196: switch Inst[17:15] { |
| 4144 | 5, 4, // 8199: case 0x5: { |
| 4145 | OPC_Decode, 156, 11, 104, // 8201: decode to VSHUF_H using decoder 104 |
| 4146 | // 8201: } |
| 4147 | 6, 4, // 8205: case 0x6: { |
| 4148 | OPC_Decode, 157, 11, 104, // 8207: decode to VSHUF_W using decoder 104 |
| 4149 | // 8207: } |
| 4150 | 7, 0, // 8211: case 0x7: { |
| 4151 | OPC_Decode, 155, 11, 104, // 8213: decode to VSHUF_D using decoder 104 |
| 4152 | // 8213: } |
| 4153 | // 8213: } // switch Inst[17:15] |
| 4154 | // 8213: } |
| 4155 | 160, 1, 51, // 8217: case 0xa0: { |
| 4156 | OPC_SwitchField, 15, 3, // 8220: switch Inst[17:15] { |
| 4157 | 0, 4, // 8223: case 0x0: { |
| 4158 | OPC_Decode, 132, 11, 106, // 8225: decode to VSEQI_B using decoder 106 |
| 4159 | // 8225: } |
| 4160 | 1, 4, // 8229: case 0x1: { |
| 4161 | OPC_Decode, 134, 11, 106, // 8231: decode to VSEQI_H using decoder 106 |
| 4162 | // 8231: } |
| 4163 | 2, 4, // 8235: case 0x2: { |
| 4164 | OPC_Decode, 135, 11, 106, // 8237: decode to VSEQI_W using decoder 106 |
| 4165 | // 8237: } |
| 4166 | 3, 4, // 8241: case 0x3: { |
| 4167 | OPC_Decode, 133, 11, 106, // 8243: decode to VSEQI_D using decoder 106 |
| 4168 | // 8243: } |
| 4169 | 4, 4, // 8247: case 0x4: { |
| 4170 | OPC_Decode, 162, 11, 106, // 8249: decode to VSLEI_B using decoder 106 |
| 4171 | // 8249: } |
| 4172 | 5, 4, // 8253: case 0x5: { |
| 4173 | OPC_Decode, 166, 11, 106, // 8255: decode to VSLEI_H using decoder 106 |
| 4174 | // 8255: } |
| 4175 | 6, 4, // 8259: case 0x6: { |
| 4176 | OPC_Decode, 168, 11, 106, // 8261: decode to VSLEI_W using decoder 106 |
| 4177 | // 8261: } |
| 4178 | 7, 0, // 8265: case 0x7: { |
| 4179 | OPC_Decode, 164, 11, 106, // 8267: decode to VSLEI_D using decoder 106 |
| 4180 | // 8267: } |
| 4181 | // 8267: } // switch Inst[17:15] |
| 4182 | // 8267: } |
| 4183 | 161, 1, 51, // 8271: case 0xa1: { |
| 4184 | OPC_SwitchField, 15, 3, // 8274: switch Inst[17:15] { |
| 4185 | 0, 4, // 8277: case 0x0: { |
| 4186 | OPC_Decode, 163, 11, 107, // 8279: decode to VSLEI_BU using decoder 107 |
| 4187 | // 8279: } |
| 4188 | 1, 4, // 8283: case 0x1: { |
| 4189 | OPC_Decode, 167, 11, 107, // 8285: decode to VSLEI_HU using decoder 107 |
| 4190 | // 8285: } |
| 4191 | 2, 4, // 8289: case 0x2: { |
| 4192 | OPC_Decode, 169, 11, 107, // 8291: decode to VSLEI_WU using decoder 107 |
| 4193 | // 8291: } |
| 4194 | 3, 4, // 8295: case 0x3: { |
| 4195 | OPC_Decode, 165, 11, 107, // 8297: decode to VSLEI_DU using decoder 107 |
| 4196 | // 8297: } |
| 4197 | 4, 4, // 8301: case 0x4: { |
| 4198 | OPC_Decode, 192, 11, 106, // 8303: decode to VSLTI_B using decoder 106 |
| 4199 | // 8303: } |
| 4200 | 5, 4, // 8307: case 0x5: { |
| 4201 | OPC_Decode, 196, 11, 106, // 8309: decode to VSLTI_H using decoder 106 |
| 4202 | // 8309: } |
| 4203 | 6, 4, // 8313: case 0x6: { |
| 4204 | OPC_Decode, 198, 11, 106, // 8315: decode to VSLTI_W using decoder 106 |
| 4205 | // 8315: } |
| 4206 | 7, 0, // 8319: case 0x7: { |
| 4207 | OPC_Decode, 194, 11, 106, // 8321: decode to VSLTI_D using decoder 106 |
| 4208 | // 8321: } |
| 4209 | // 8321: } // switch Inst[17:15] |
| 4210 | // 8321: } |
| 4211 | 162, 1, 51, // 8325: case 0xa2: { |
| 4212 | OPC_SwitchField, 15, 3, // 8328: switch Inst[17:15] { |
| 4213 | 0, 4, // 8331: case 0x0: { |
| 4214 | OPC_Decode, 193, 11, 107, // 8333: decode to VSLTI_BU using decoder 107 |
| 4215 | // 8333: } |
| 4216 | 1, 4, // 8337: case 0x1: { |
| 4217 | OPC_Decode, 197, 11, 107, // 8339: decode to VSLTI_HU using decoder 107 |
| 4218 | // 8339: } |
| 4219 | 2, 4, // 8343: case 0x2: { |
| 4220 | OPC_Decode, 199, 11, 107, // 8345: decode to VSLTI_WU using decoder 107 |
| 4221 | // 8345: } |
| 4222 | 3, 4, // 8349: case 0x3: { |
| 4223 | OPC_Decode, 195, 11, 107, // 8351: decode to VSLTI_DU using decoder 107 |
| 4224 | // 8351: } |
| 4225 | 4, 4, // 8355: case 0x4: { |
| 4226 | OPC_Decode, 161, 7, 107, // 8357: decode to VADDI_BU using decoder 107 |
| 4227 | // 8357: } |
| 4228 | 5, 4, // 8361: case 0x5: { |
| 4229 | OPC_Decode, 163, 7, 107, // 8363: decode to VADDI_HU using decoder 107 |
| 4230 | // 8363: } |
| 4231 | 6, 4, // 8367: case 0x6: { |
| 4232 | OPC_Decode, 164, 7, 107, // 8369: decode to VADDI_WU using decoder 107 |
| 4233 | // 8369: } |
| 4234 | 7, 0, // 8373: case 0x7: { |
| 4235 | OPC_Decode, 162, 7, 107, // 8375: decode to VADDI_DU using decoder 107 |
| 4236 | // 8375: } |
| 4237 | // 8375: } // switch Inst[17:15] |
| 4238 | // 8375: } |
| 4239 | 163, 1, 39, // 8379: case 0xa3: { |
| 4240 | OPC_SwitchField, 15, 3, // 8382: switch Inst[17:15] { |
| 4241 | 0, 4, // 8385: case 0x0: { |
| 4242 | OPC_Decode, 210, 12, 107, // 8387: decode to VSUBI_BU using decoder 107 |
| 4243 | // 8387: } |
| 4244 | 1, 4, // 8391: case 0x1: { |
| 4245 | OPC_Decode, 212, 12, 107, // 8393: decode to VSUBI_HU using decoder 107 |
| 4246 | // 8393: } |
| 4247 | 2, 4, // 8397: case 0x2: { |
| 4248 | OPC_Decode, 213, 12, 107, // 8399: decode to VSUBI_WU using decoder 107 |
| 4249 | // 8399: } |
| 4250 | 3, 4, // 8403: case 0x3: { |
| 4251 | OPC_Decode, 211, 12, 107, // 8405: decode to VSUBI_DU using decoder 107 |
| 4252 | // 8405: } |
| 4253 | 4, 4, // 8409: case 0x4: { |
| 4254 | OPC_Decode, 239, 7, 107, // 8411: decode to VBSLL_V using decoder 107 |
| 4255 | // 8411: } |
| 4256 | 5, 0, // 8415: case 0x5: { |
| 4257 | OPC_Decode, 240, 7, 107, // 8417: decode to VBSRL_V using decoder 107 |
| 4258 | // 8417: } |
| 4259 | // 8417: } // switch Inst[17:15] |
| 4260 | // 8417: } |
| 4261 | 164, 1, 51, // 8421: case 0xa4: { |
| 4262 | OPC_SwitchField, 15, 3, // 8424: switch Inst[17:15] { |
| 4263 | 0, 4, // 8427: case 0x0: { |
| 4264 | OPC_Decode, 228, 9, 106, // 8429: decode to VMAXI_B using decoder 106 |
| 4265 | // 8429: } |
| 4266 | 1, 4, // 8433: case 0x1: { |
| 4267 | OPC_Decode, 232, 9, 106, // 8435: decode to VMAXI_H using decoder 106 |
| 4268 | // 8435: } |
| 4269 | 2, 4, // 8439: case 0x2: { |
| 4270 | OPC_Decode, 234, 9, 106, // 8441: decode to VMAXI_W using decoder 106 |
| 4271 | // 8441: } |
| 4272 | 3, 4, // 8445: case 0x3: { |
| 4273 | OPC_Decode, 230, 9, 106, // 8447: decode to VMAXI_D using decoder 106 |
| 4274 | // 8447: } |
| 4275 | 4, 4, // 8451: case 0x4: { |
| 4276 | OPC_Decode, 244, 9, 106, // 8453: decode to VMINI_B using decoder 106 |
| 4277 | // 8453: } |
| 4278 | 5, 4, // 8457: case 0x5: { |
| 4279 | OPC_Decode, 248, 9, 106, // 8459: decode to VMINI_H using decoder 106 |
| 4280 | // 8459: } |
| 4281 | 6, 4, // 8463: case 0x6: { |
| 4282 | OPC_Decode, 250, 9, 106, // 8465: decode to VMINI_W using decoder 106 |
| 4283 | // 8465: } |
| 4284 | 7, 0, // 8469: case 0x7: { |
| 4285 | OPC_Decode, 246, 9, 106, // 8471: decode to VMINI_D using decoder 106 |
| 4286 | // 8471: } |
| 4287 | // 8471: } // switch Inst[17:15] |
| 4288 | // 8471: } |
| 4289 | 165, 1, 51, // 8475: case 0xa5: { |
| 4290 | OPC_SwitchField, 15, 3, // 8478: switch Inst[17:15] { |
| 4291 | 0, 4, // 8481: case 0x0: { |
| 4292 | OPC_Decode, 229, 9, 107, // 8483: decode to VMAXI_BU using decoder 107 |
| 4293 | // 8483: } |
| 4294 | 1, 4, // 8487: case 0x1: { |
| 4295 | OPC_Decode, 233, 9, 107, // 8489: decode to VMAXI_HU using decoder 107 |
| 4296 | // 8489: } |
| 4297 | 2, 4, // 8493: case 0x2: { |
| 4298 | OPC_Decode, 235, 9, 107, // 8495: decode to VMAXI_WU using decoder 107 |
| 4299 | // 8495: } |
| 4300 | 3, 4, // 8499: case 0x3: { |
| 4301 | OPC_Decode, 231, 9, 107, // 8501: decode to VMAXI_DU using decoder 107 |
| 4302 | // 8501: } |
| 4303 | 4, 4, // 8505: case 0x4: { |
| 4304 | OPC_Decode, 245, 9, 107, // 8507: decode to VMINI_BU using decoder 107 |
| 4305 | // 8507: } |
| 4306 | 5, 4, // 8511: case 0x5: { |
| 4307 | OPC_Decode, 249, 9, 107, // 8513: decode to VMINI_HU using decoder 107 |
| 4308 | // 8513: } |
| 4309 | 6, 4, // 8517: case 0x6: { |
| 4310 | OPC_Decode, 251, 9, 107, // 8519: decode to VMINI_WU using decoder 107 |
| 4311 | // 8519: } |
| 4312 | 7, 0, // 8523: case 0x7: { |
| 4313 | OPC_Decode, 247, 9, 107, // 8525: decode to VMINI_DU using decoder 107 |
| 4314 | // 8525: } |
| 4315 | // 8525: } // switch Inst[17:15] |
| 4316 | // 8525: } |
| 4317 | 166, 1, 15, // 8529: case 0xa6: { |
| 4318 | OPC_SwitchField, 15, 3, // 8532: switch Inst[17:15] { |
| 4319 | 4, 4, // 8535: case 0x4: { |
| 4320 | OPC_Decode, 128, 9, 108, // 8537: decode to VFRSTPI_B using decoder 108 |
| 4321 | // 8537: } |
| 4322 | 5, 0, // 8541: case 0x5: { |
| 4323 | OPC_Decode, 129, 9, 108, // 8543: decode to VFRSTPI_H using decoder 108 |
| 4324 | // 8543: } |
| 4325 | // 8543: } // switch Inst[17:15] |
| 4326 | // 8543: } |
| 4327 | 167, 1, 185, 5, // 8547: case 0xa7: { |
| 4328 | OPC_SwitchField, 10, 8, // 8551: switch Inst[17:10] { |
| 4329 | 0, 4, // 8554: case 0x0: { |
| 4330 | OPC_Decode, 241, 7, 109, // 8556: decode to VCLO_B using decoder 109 |
| 4331 | // 8556: } |
| 4332 | 1, 4, // 8560: case 0x1: { |
| 4333 | OPC_Decode, 243, 7, 109, // 8562: decode to VCLO_H using decoder 109 |
| 4334 | // 8562: } |
| 4335 | 2, 4, // 8566: case 0x2: { |
| 4336 | OPC_Decode, 244, 7, 109, // 8568: decode to VCLO_W using decoder 109 |
| 4337 | // 8568: } |
| 4338 | 3, 4, // 8572: case 0x3: { |
| 4339 | OPC_Decode, 242, 7, 109, // 8574: decode to VCLO_D using decoder 109 |
| 4340 | // 8574: } |
| 4341 | 4, 4, // 8578: case 0x4: { |
| 4342 | OPC_Decode, 245, 7, 109, // 8580: decode to VCLZ_B using decoder 109 |
| 4343 | // 8580: } |
| 4344 | 5, 4, // 8584: case 0x5: { |
| 4345 | OPC_Decode, 247, 7, 109, // 8586: decode to VCLZ_H using decoder 109 |
| 4346 | // 8586: } |
| 4347 | 6, 4, // 8590: case 0x6: { |
| 4348 | OPC_Decode, 248, 7, 109, // 8592: decode to VCLZ_W using decoder 109 |
| 4349 | // 8592: } |
| 4350 | 7, 4, // 8596: case 0x7: { |
| 4351 | OPC_Decode, 246, 7, 109, // 8598: decode to VCLZ_D using decoder 109 |
| 4352 | // 8598: } |
| 4353 | 8, 4, // 8602: case 0x8: { |
| 4354 | OPC_Decode, 203, 10, 109, // 8604: decode to VPCNT_B using decoder 109 |
| 4355 | // 8604: } |
| 4356 | 9, 4, // 8608: case 0x9: { |
| 4357 | OPC_Decode, 205, 10, 109, // 8610: decode to VPCNT_H using decoder 109 |
| 4358 | // 8610: } |
| 4359 | 10, 4, // 8614: case 0xa: { |
| 4360 | OPC_Decode, 206, 10, 109, // 8616: decode to VPCNT_W using decoder 109 |
| 4361 | // 8616: } |
| 4362 | 11, 4, // 8620: case 0xb: { |
| 4363 | OPC_Decode, 204, 10, 109, // 8622: decode to VPCNT_D using decoder 109 |
| 4364 | // 8622: } |
| 4365 | 12, 4, // 8626: case 0xc: { |
| 4366 | OPC_Decode, 186, 10, 109, // 8628: decode to VNEG_B using decoder 109 |
| 4367 | // 8628: } |
| 4368 | 13, 4, // 8632: case 0xd: { |
| 4369 | OPC_Decode, 188, 10, 109, // 8634: decode to VNEG_H using decoder 109 |
| 4370 | // 8634: } |
| 4371 | 14, 4, // 8638: case 0xe: { |
| 4372 | OPC_Decode, 189, 10, 109, // 8640: decode to VNEG_W using decoder 109 |
| 4373 | // 8640: } |
| 4374 | 15, 4, // 8644: case 0xf: { |
| 4375 | OPC_Decode, 187, 10, 109, // 8646: decode to VNEG_D using decoder 109 |
| 4376 | // 8646: } |
| 4377 | 16, 4, // 8650: case 0x10: { |
| 4378 | OPC_Decode, 141, 10, 109, // 8652: decode to VMSKLTZ_B using decoder 109 |
| 4379 | // 8652: } |
| 4380 | 17, 4, // 8656: case 0x11: { |
| 4381 | OPC_Decode, 143, 10, 109, // 8658: decode to VMSKLTZ_H using decoder 109 |
| 4382 | // 8658: } |
| 4383 | 18, 4, // 8662: case 0x12: { |
| 4384 | OPC_Decode, 144, 10, 109, // 8664: decode to VMSKLTZ_W using decoder 109 |
| 4385 | // 8664: } |
| 4386 | 19, 4, // 8668: case 0x13: { |
| 4387 | OPC_Decode, 142, 10, 109, // 8670: decode to VMSKLTZ_D using decoder 109 |
| 4388 | // 8670: } |
| 4389 | 20, 4, // 8674: case 0x14: { |
| 4390 | OPC_Decode, 140, 10, 109, // 8676: decode to VMSKGEZ_B using decoder 109 |
| 4391 | // 8676: } |
| 4392 | 24, 4, // 8680: case 0x18: { |
| 4393 | OPC_Decode, 145, 10, 109, // 8682: decode to VMSKNZ_B using decoder 109 |
| 4394 | // 8682: } |
| 4395 | 38, 8, // 8686: case 0x26: { |
| 4396 | OPC_CheckField, 3, 2, 0, // 8688: check Inst[4:3] == 0x0 |
| 4397 | OPC_Decode, 148, 11, 110, // 8692: decode to VSETEQZ_V using decoder 110 |
| 4398 | // 8692: } |
| 4399 | 39, 8, // 8696: case 0x27: { |
| 4400 | OPC_CheckField, 3, 2, 0, // 8698: check Inst[4:3] == 0x0 |
| 4401 | OPC_Decode, 149, 11, 110, // 8702: decode to VSETNEZ_V using decoder 110 |
| 4402 | // 8702: } |
| 4403 | 40, 8, // 8706: case 0x28: { |
| 4404 | OPC_CheckField, 3, 2, 0, // 8708: check Inst[4:3] == 0x0 |
| 4405 | OPC_Decode, 144, 11, 110, // 8712: decode to VSETANYEQZ_B using decoder 110 |
| 4406 | // 8712: } |
| 4407 | 41, 8, // 8716: case 0x29: { |
| 4408 | OPC_CheckField, 3, 2, 0, // 8718: check Inst[4:3] == 0x0 |
| 4409 | OPC_Decode, 146, 11, 110, // 8722: decode to VSETANYEQZ_H using decoder 110 |
| 4410 | // 8722: } |
| 4411 | 42, 8, // 8726: case 0x2a: { |
| 4412 | OPC_CheckField, 3, 2, 0, // 8728: check Inst[4:3] == 0x0 |
| 4413 | OPC_Decode, 147, 11, 110, // 8732: decode to VSETANYEQZ_W using decoder 110 |
| 4414 | // 8732: } |
| 4415 | 43, 8, // 8736: case 0x2b: { |
| 4416 | OPC_CheckField, 3, 2, 0, // 8738: check Inst[4:3] == 0x0 |
| 4417 | OPC_Decode, 145, 11, 110, // 8742: decode to VSETANYEQZ_D using decoder 110 |
| 4418 | // 8742: } |
| 4419 | 44, 8, // 8746: case 0x2c: { |
| 4420 | OPC_CheckField, 3, 2, 0, // 8748: check Inst[4:3] == 0x0 |
| 4421 | OPC_Decode, 140, 11, 110, // 8752: decode to VSETALLNEZ_B using decoder 110 |
| 4422 | // 8752: } |
| 4423 | 45, 8, // 8756: case 0x2d: { |
| 4424 | OPC_CheckField, 3, 2, 0, // 8758: check Inst[4:3] == 0x0 |
| 4425 | OPC_Decode, 142, 11, 110, // 8762: decode to VSETALLNEZ_H using decoder 110 |
| 4426 | // 8762: } |
| 4427 | 46, 8, // 8766: case 0x2e: { |
| 4428 | OPC_CheckField, 3, 2, 0, // 8768: check Inst[4:3] == 0x0 |
| 4429 | OPC_Decode, 143, 11, 110, // 8772: decode to VSETALLNEZ_W using decoder 110 |
| 4430 | // 8772: } |
| 4431 | 47, 8, // 8776: case 0x2f: { |
| 4432 | OPC_CheckField, 3, 2, 0, // 8778: check Inst[4:3] == 0x0 |
| 4433 | OPC_Decode, 141, 11, 110, // 8782: decode to VSETALLNEZ_D using decoder 110 |
| 4434 | // 8782: } |
| 4435 | 49, 4, // 8786: case 0x31: { |
| 4436 | OPC_Decode, 219, 8, 109, // 8788: decode to VFLOGB_S using decoder 109 |
| 4437 | // 8788: } |
| 4438 | 50, 4, // 8792: case 0x32: { |
| 4439 | OPC_Decode, 218, 8, 109, // 8794: decode to VFLOGB_D using decoder 109 |
| 4440 | // 8794: } |
| 4441 | 53, 4, // 8798: case 0x35: { |
| 4442 | OPC_Decode, 158, 8, 109, // 8800: decode to VFCLASS_S using decoder 109 |
| 4443 | // 8800: } |
| 4444 | 54, 4, // 8804: case 0x36: { |
| 4445 | OPC_Decode, 157, 8, 109, // 8806: decode to VFCLASS_D using decoder 109 |
| 4446 | // 8806: } |
| 4447 | 57, 4, // 8810: case 0x39: { |
| 4448 | OPC_Decode, 133, 9, 109, // 8812: decode to VFSQRT_S using decoder 109 |
| 4449 | // 8812: } |
| 4450 | 58, 4, // 8816: case 0x3a: { |
| 4451 | OPC_Decode, 132, 9, 109, // 8818: decode to VFSQRT_D using decoder 109 |
| 4452 | // 8818: } |
| 4453 | 61, 4, // 8822: case 0x3d: { |
| 4454 | OPC_Decode, 241, 8, 109, // 8824: decode to VFRECIP_S using decoder 109 |
| 4455 | // 8824: } |
| 4456 | 62, 4, // 8828: case 0x3e: { |
| 4457 | OPC_Decode, 240, 8, 109, // 8830: decode to VFRECIP_D using decoder 109 |
| 4458 | // 8830: } |
| 4459 | 65, 4, // 8834: case 0x41: { |
| 4460 | OPC_Decode, 255, 8, 109, // 8836: decode to VFRSQRT_S using decoder 109 |
| 4461 | // 8836: } |
| 4462 | 66, 4, // 8840: case 0x42: { |
| 4463 | OPC_Decode, 254, 8, 109, // 8842: decode to VFRSQRT_D using decoder 109 |
| 4464 | // 8842: } |
| 4465 | 69, 4, // 8846: case 0x45: { |
| 4466 | OPC_Decode, 239, 8, 109, // 8848: decode to VFRECIPE_S using decoder 109 |
| 4467 | // 8848: } |
| 4468 | 70, 4, // 8852: case 0x46: { |
| 4469 | OPC_Decode, 238, 8, 109, // 8854: decode to VFRECIPE_D using decoder 109 |
| 4470 | // 8854: } |
| 4471 | 73, 4, // 8858: case 0x49: { |
| 4472 | OPC_Decode, 253, 8, 109, // 8860: decode to VFRSQRTE_S using decoder 109 |
| 4473 | // 8860: } |
| 4474 | 74, 4, // 8864: case 0x4a: { |
| 4475 | OPC_Decode, 252, 8, 109, // 8866: decode to VFRSQRTE_D using decoder 109 |
| 4476 | // 8866: } |
| 4477 | 77, 4, // 8870: case 0x4d: { |
| 4478 | OPC_Decode, 251, 8, 109, // 8872: decode to VFRINT_S using decoder 109 |
| 4479 | // 8872: } |
| 4480 | 78, 4, // 8876: case 0x4e: { |
| 4481 | OPC_Decode, 250, 8, 109, // 8878: decode to VFRINT_D using decoder 109 |
| 4482 | // 8878: } |
| 4483 | 81, 4, // 8882: case 0x51: { |
| 4484 | OPC_Decode, 243, 8, 109, // 8884: decode to VFRINTRM_S using decoder 109 |
| 4485 | // 8884: } |
| 4486 | 82, 4, // 8888: case 0x52: { |
| 4487 | OPC_Decode, 242, 8, 109, // 8890: decode to VFRINTRM_D using decoder 109 |
| 4488 | // 8890: } |
| 4489 | 85, 4, // 8894: case 0x55: { |
| 4490 | OPC_Decode, 247, 8, 109, // 8896: decode to VFRINTRP_S using decoder 109 |
| 4491 | // 8896: } |
| 4492 | 86, 4, // 8900: case 0x56: { |
| 4493 | OPC_Decode, 246, 8, 109, // 8902: decode to VFRINTRP_D using decoder 109 |
| 4494 | // 8902: } |
| 4495 | 89, 4, // 8906: case 0x59: { |
| 4496 | OPC_Decode, 249, 8, 109, // 8908: decode to VFRINTRZ_S using decoder 109 |
| 4497 | // 8908: } |
| 4498 | 90, 4, // 8912: case 0x5a: { |
| 4499 | OPC_Decode, 248, 8, 109, // 8914: decode to VFRINTRZ_D using decoder 109 |
| 4500 | // 8914: } |
| 4501 | 93, 4, // 8918: case 0x5d: { |
| 4502 | OPC_Decode, 245, 8, 109, // 8920: decode to VFRINTRNE_S using decoder 109 |
| 4503 | // 8920: } |
| 4504 | 94, 4, // 8924: case 0x5e: { |
| 4505 | OPC_Decode, 244, 8, 109, // 8926: decode to VFRINTRNE_D using decoder 109 |
| 4506 | // 8926: } |
| 4507 | 122, 4, // 8930: case 0x7a: { |
| 4508 | OPC_Decode, 206, 8, 109, // 8932: decode to VFCVTL_S_H using decoder 109 |
| 4509 | // 8932: } |
| 4510 | 123, 4, // 8936: case 0x7b: { |
| 4511 | OPC_Decode, 204, 8, 109, // 8938: decode to VFCVTH_S_H using decoder 109 |
| 4512 | // 8938: } |
| 4513 | 124, 4, // 8942: case 0x7c: { |
| 4514 | OPC_Decode, 205, 8, 109, // 8944: decode to VFCVTL_D_S using decoder 109 |
| 4515 | // 8944: } |
| 4516 | 125, 4, // 8948: case 0x7d: { |
| 4517 | OPC_Decode, 203, 8, 109, // 8950: decode to VFCVTH_D_S using decoder 109 |
| 4518 | // 8950: } |
| 4519 | 128, 1, 4, // 8954: case 0x80: { |
| 4520 | OPC_Decode, 216, 8, 109, // 8957: decode to VFFINT_S_W using decoder 109 |
| 4521 | // 8957: } |
| 4522 | 129, 1, 4, // 8961: case 0x81: { |
| 4523 | OPC_Decode, 217, 8, 109, // 8964: decode to VFFINT_S_WU using decoder 109 |
| 4524 | // 8964: } |
| 4525 | 130, 1, 4, // 8968: case 0x82: { |
| 4526 | OPC_Decode, 213, 8, 109, // 8971: decode to VFFINT_D_L using decoder 109 |
| 4527 | // 8971: } |
| 4528 | 131, 1, 4, // 8975: case 0x83: { |
| 4529 | OPC_Decode, 214, 8, 109, // 8978: decode to VFFINT_D_LU using decoder 109 |
| 4530 | // 8978: } |
| 4531 | 132, 1, 4, // 8982: case 0x84: { |
| 4532 | OPC_Decode, 212, 8, 109, // 8985: decode to VFFINTL_D_W using decoder 109 |
| 4533 | // 8985: } |
| 4534 | 133, 1, 4, // 8989: case 0x85: { |
| 4535 | OPC_Decode, 211, 8, 109, // 8992: decode to VFFINTH_D_W using decoder 109 |
| 4536 | // 8992: } |
| 4537 | 140, 1, 4, // 8996: case 0x8c: { |
| 4538 | OPC_Decode, 164, 9, 109, // 8999: decode to VFTINT_W_S using decoder 109 |
| 4539 | // 8999: } |
| 4540 | 141, 1, 4, // 9003: case 0x8d: { |
| 4541 | OPC_Decode, 161, 9, 109, // 9006: decode to VFTINT_L_D using decoder 109 |
| 4542 | // 9006: } |
| 4543 | 142, 1, 4, // 9010: case 0x8e: { |
| 4544 | OPC_Decode, 142, 9, 109, // 9013: decode to VFTINTRM_W_S using decoder 109 |
| 4545 | // 9013: } |
| 4546 | 143, 1, 4, // 9017: case 0x8f: { |
| 4547 | OPC_Decode, 140, 9, 109, // 9020: decode to VFTINTRM_L_D using decoder 109 |
| 4548 | // 9020: } |
| 4549 | 144, 1, 4, // 9024: case 0x90: { |
| 4550 | OPC_Decode, 152, 9, 109, // 9027: decode to VFTINTRP_W_S using decoder 109 |
| 4551 | // 9027: } |
| 4552 | 145, 1, 4, // 9031: case 0x91: { |
| 4553 | OPC_Decode, 150, 9, 109, // 9034: decode to VFTINTRP_L_D using decoder 109 |
| 4554 | // 9034: } |
| 4555 | 146, 1, 4, // 9038: case 0x92: { |
| 4556 | OPC_Decode, 159, 9, 109, // 9041: decode to VFTINTRZ_W_S using decoder 109 |
| 4557 | // 9041: } |
| 4558 | 147, 1, 4, // 9045: case 0x93: { |
| 4559 | OPC_Decode, 156, 9, 109, // 9048: decode to VFTINTRZ_L_D using decoder 109 |
| 4560 | // 9048: } |
| 4561 | 148, 1, 4, // 9052: case 0x94: { |
| 4562 | OPC_Decode, 147, 9, 109, // 9055: decode to VFTINTRNE_W_S using decoder 109 |
| 4563 | // 9055: } |
| 4564 | 149, 1, 4, // 9059: case 0x95: { |
| 4565 | OPC_Decode, 145, 9, 109, // 9062: decode to VFTINTRNE_L_D using decoder 109 |
| 4566 | // 9062: } |
| 4567 | 150, 1, 4, // 9066: case 0x96: { |
| 4568 | OPC_Decode, 162, 9, 109, // 9069: decode to VFTINT_WU_S using decoder 109 |
| 4569 | // 9069: } |
| 4570 | 151, 1, 4, // 9073: case 0x97: { |
| 4571 | OPC_Decode, 160, 9, 109, // 9076: decode to VFTINT_LU_D using decoder 109 |
| 4572 | // 9076: } |
| 4573 | 156, 1, 4, // 9080: case 0x9c: { |
| 4574 | OPC_Decode, 157, 9, 109, // 9083: decode to VFTINTRZ_WU_S using decoder 109 |
| 4575 | // 9083: } |
| 4576 | 157, 1, 4, // 9087: case 0x9d: { |
| 4577 | OPC_Decode, 155, 9, 109, // 9090: decode to VFTINTRZ_LU_D using decoder 109 |
| 4578 | // 9090: } |
| 4579 | 160, 1, 4, // 9094: case 0xa0: { |
| 4580 | OPC_Decode, 137, 9, 109, // 9097: decode to VFTINTL_L_S using decoder 109 |
| 4581 | // 9097: } |
| 4582 | 161, 1, 4, // 9101: case 0xa1: { |
| 4583 | OPC_Decode, 136, 9, 109, // 9104: decode to VFTINTH_L_S using decoder 109 |
| 4584 | // 9104: } |
| 4585 | 162, 1, 4, // 9108: case 0xa2: { |
| 4586 | OPC_Decode, 139, 9, 109, // 9111: decode to VFTINTRML_L_S using decoder 109 |
| 4587 | // 9111: } |
| 4588 | 163, 1, 4, // 9115: case 0xa3: { |
| 4589 | OPC_Decode, 138, 9, 109, // 9118: decode to VFTINTRMH_L_S using decoder 109 |
| 4590 | // 9118: } |
| 4591 | 164, 1, 4, // 9122: case 0xa4: { |
| 4592 | OPC_Decode, 149, 9, 109, // 9125: decode to VFTINTRPL_L_S using decoder 109 |
| 4593 | // 9125: } |
| 4594 | 165, 1, 4, // 9129: case 0xa5: { |
| 4595 | OPC_Decode, 148, 9, 109, // 9132: decode to VFTINTRPH_L_S using decoder 109 |
| 4596 | // 9132: } |
| 4597 | 166, 1, 4, // 9136: case 0xa6: { |
| 4598 | OPC_Decode, 154, 9, 109, // 9139: decode to VFTINTRZL_L_S using decoder 109 |
| 4599 | // 9139: } |
| 4600 | 167, 1, 4, // 9143: case 0xa7: { |
| 4601 | OPC_Decode, 153, 9, 109, // 9146: decode to VFTINTRZH_L_S using decoder 109 |
| 4602 | // 9146: } |
| 4603 | 168, 1, 4, // 9150: case 0xa8: { |
| 4604 | OPC_Decode, 144, 9, 109, // 9153: decode to VFTINTRNEL_L_S using decoder 109 |
| 4605 | // 9153: } |
| 4606 | 169, 1, 4, // 9157: case 0xa9: { |
| 4607 | OPC_Decode, 143, 9, 109, // 9160: decode to VFTINTRNEH_L_S using decoder 109 |
| 4608 | // 9160: } |
| 4609 | 184, 1, 4, // 9164: case 0xb8: { |
| 4610 | OPC_Decode, 144, 8, 109, // 9167: decode to VEXTH_H_B using decoder 109 |
| 4611 | // 9167: } |
| 4612 | 185, 1, 4, // 9171: case 0xb9: { |
| 4613 | OPC_Decode, 148, 8, 109, // 9174: decode to VEXTH_W_H using decoder 109 |
| 4614 | // 9174: } |
| 4615 | 186, 1, 4, // 9178: case 0xba: { |
| 4616 | OPC_Decode, 142, 8, 109, // 9181: decode to VEXTH_D_W using decoder 109 |
| 4617 | // 9181: } |
| 4618 | 187, 1, 4, // 9185: case 0xbb: { |
| 4619 | OPC_Decode, 146, 8, 109, // 9188: decode to VEXTH_Q_D using decoder 109 |
| 4620 | // 9188: } |
| 4621 | 188, 1, 4, // 9192: case 0xbc: { |
| 4622 | OPC_Decode, 143, 8, 109, // 9195: decode to VEXTH_HU_BU using decoder 109 |
| 4623 | // 9195: } |
| 4624 | 189, 1, 4, // 9199: case 0xbd: { |
| 4625 | OPC_Decode, 147, 8, 109, // 9202: decode to VEXTH_WU_HU using decoder 109 |
| 4626 | // 9202: } |
| 4627 | 190, 1, 4, // 9206: case 0xbe: { |
| 4628 | OPC_Decode, 141, 8, 109, // 9209: decode to VEXTH_DU_WU using decoder 109 |
| 4629 | // 9209: } |
| 4630 | 191, 1, 4, // 9213: case 0xbf: { |
| 4631 | OPC_Decode, 145, 8, 109, // 9216: decode to VEXTH_QU_DU using decoder 109 |
| 4632 | // 9216: } |
| 4633 | 192, 1, 4, // 9220: case 0xc0: { |
| 4634 | OPC_Decode, 224, 10, 111, // 9223: decode to VREPLGR2VR_B using decoder 111 |
| 4635 | // 9223: } |
| 4636 | 193, 1, 4, // 9227: case 0xc1: { |
| 4637 | OPC_Decode, 226, 10, 111, // 9230: decode to VREPLGR2VR_H using decoder 111 |
| 4638 | // 9230: } |
| 4639 | 194, 1, 4, // 9234: case 0xc2: { |
| 4640 | OPC_Decode, 227, 10, 111, // 9237: decode to VREPLGR2VR_W using decoder 111 |
| 4641 | // 9237: } |
| 4642 | 195, 1, 0, // 9241: case 0xc3: { |
| 4643 | OPC_Decode, 225, 10, 111, // 9244: decode to VREPLGR2VR_D using decoder 111 |
| 4644 | // 9244: } |
| 4645 | // 9244: } // switch Inst[17:10] |
| 4646 | // 9244: } |
| 4647 | 168, 1, 41, // 9248: case 0xa8: { |
| 4648 | OPC_SwitchField, 16, 2, // 9251: switch Inst[17:16] { |
| 4649 | 0, 30, // 9254: case 0x0: { |
| 4650 | OPC_SwitchField, 15, 1, // 9256: switch Inst[15] { |
| 4651 | 0, 19, // 9259: case 0x0: { |
| 4652 | OPC_SwitchField, 14, 1, // 9261: switch Inst[14] { |
| 4653 | 0, 8, // 9264: case 0x0: { |
| 4654 | OPC_CheckField, 13, 1, 1, // 9266: check Inst[13] == 0x1 |
| 4655 | OPC_Decode, 236, 10, 112, // 9270: decode to VROTRI_B using decoder 112 |
| 4656 | // 9270: } |
| 4657 | 1, 0, // 9274: case 0x1: { |
| 4658 | OPC_Decode, 238, 10, 113, // 9276: decode to VROTRI_H using decoder 113 |
| 4659 | // 9276: } |
| 4660 | // 9276: } // switch Inst[14] |
| 4661 | // 9276: } |
| 4662 | 1, 0, // 9280: case 0x1: { |
| 4663 | OPC_Decode, 239, 10, 107, // 9282: decode to VROTRI_W using decoder 107 |
| 4664 | // 9282: } |
| 4665 | // 9282: } // switch Inst[15] |
| 4666 | // 9282: } |
| 4667 | 1, 0, // 9286: case 0x1: { |
| 4668 | OPC_Decode, 237, 10, 114, // 9288: decode to VROTRI_D using decoder 114 |
| 4669 | // 9288: } |
| 4670 | // 9288: } // switch Inst[17:16] |
| 4671 | // 9288: } |
| 4672 | 169, 1, 41, // 9292: case 0xa9: { |
| 4673 | OPC_SwitchField, 16, 2, // 9295: switch Inst[17:16] { |
| 4674 | 0, 30, // 9298: case 0x0: { |
| 4675 | OPC_SwitchField, 15, 1, // 9300: switch Inst[15] { |
| 4676 | 0, 19, // 9303: case 0x0: { |
| 4677 | OPC_SwitchField, 14, 1, // 9305: switch Inst[14] { |
| 4678 | 0, 8, // 9308: case 0x0: { |
| 4679 | OPC_CheckField, 13, 1, 1, // 9310: check Inst[13] == 0x1 |
| 4680 | OPC_Decode, 249, 11, 112, // 9314: decode to VSRLRI_B using decoder 112 |
| 4681 | // 9314: } |
| 4682 | 1, 0, // 9318: case 0x1: { |
| 4683 | OPC_Decode, 251, 11, 113, // 9320: decode to VSRLRI_H using decoder 113 |
| 4684 | // 9320: } |
| 4685 | // 9320: } // switch Inst[14] |
| 4686 | // 9320: } |
| 4687 | 1, 0, // 9324: case 0x1: { |
| 4688 | OPC_Decode, 252, 11, 107, // 9326: decode to VSRLRI_W using decoder 107 |
| 4689 | // 9326: } |
| 4690 | // 9326: } // switch Inst[15] |
| 4691 | // 9326: } |
| 4692 | 1, 0, // 9330: case 0x1: { |
| 4693 | OPC_Decode, 250, 11, 114, // 9332: decode to VSRLRI_D using decoder 114 |
| 4694 | // 9332: } |
| 4695 | // 9332: } // switch Inst[17:16] |
| 4696 | // 9332: } |
| 4697 | 170, 1, 41, // 9336: case 0xaa: { |
| 4698 | OPC_SwitchField, 16, 2, // 9339: switch Inst[17:16] { |
| 4699 | 0, 30, // 9342: case 0x0: { |
| 4700 | OPC_SwitchField, 15, 1, // 9344: switch Inst[15] { |
| 4701 | 0, 19, // 9347: case 0x0: { |
| 4702 | OPC_SwitchField, 14, 1, // 9349: switch Inst[14] { |
| 4703 | 0, 8, // 9352: case 0x0: { |
| 4704 | OPC_CheckField, 13, 1, 1, // 9354: check Inst[13] == 0x1 |
| 4705 | OPC_Decode, 219, 11, 112, // 9358: decode to VSRARI_B using decoder 112 |
| 4706 | // 9358: } |
| 4707 | 1, 0, // 9362: case 0x1: { |
| 4708 | OPC_Decode, 221, 11, 113, // 9364: decode to VSRARI_H using decoder 113 |
| 4709 | // 9364: } |
| 4710 | // 9364: } // switch Inst[14] |
| 4711 | // 9364: } |
| 4712 | 1, 0, // 9368: case 0x1: { |
| 4713 | OPC_Decode, 222, 11, 107, // 9370: decode to VSRARI_W using decoder 107 |
| 4714 | // 9370: } |
| 4715 | // 9370: } // switch Inst[15] |
| 4716 | // 9370: } |
| 4717 | 1, 0, // 9374: case 0x1: { |
| 4718 | OPC_Decode, 220, 11, 114, // 9376: decode to VSRARI_D using decoder 114 |
| 4719 | // 9376: } |
| 4720 | // 9376: } // switch Inst[17:16] |
| 4721 | // 9376: } |
| 4722 | 186, 1, 41, // 9380: case 0xba: { |
| 4723 | OPC_SwitchField, 14, 4, // 9383: switch Inst[17:14] { |
| 4724 | 14, 4, // 9386: case 0xe: { |
| 4725 | OPC_Decode, 189, 9, 115, // 9388: decode to VINSGR2VR_B using decoder 115 |
| 4726 | // 9388: } |
| 4727 | 15, 0, // 9392: case 0xf: { |
| 4728 | OPC_SwitchField, 13, 1, // 9394: switch Inst[13] { |
| 4729 | 0, 4, // 9397: case 0x0: { |
| 4730 | OPC_Decode, 191, 9, 116, // 9399: decode to VINSGR2VR_H using decoder 116 |
| 4731 | // 9399: } |
| 4732 | 1, 0, // 9403: case 0x1: { |
| 4733 | OPC_SwitchField, 12, 1, // 9405: switch Inst[12] { |
| 4734 | 0, 4, // 9408: case 0x0: { |
| 4735 | OPC_Decode, 192, 9, 117, // 9410: decode to VINSGR2VR_W using decoder 117 |
| 4736 | // 9410: } |
| 4737 | 1, 0, // 9414: case 0x1: { |
| 4738 | OPC_CheckField, 11, 1, 0, // 9416: check Inst[11] == 0x0 |
| 4739 | OPC_Decode, 190, 9, 118, // 9420: decode to VINSGR2VR_D using decoder 118 |
| 4740 | // 9420: } |
| 4741 | // 9420: } // switch Inst[12] |
| 4742 | // 9420: } |
| 4743 | // 9420: } // switch Inst[13] |
| 4744 | // 9420: } |
| 4745 | // 9420: } // switch Inst[17:14] |
| 4746 | // 9420: } |
| 4747 | 187, 1, 41, // 9424: case 0xbb: { |
| 4748 | OPC_SwitchField, 14, 4, // 9427: switch Inst[17:14] { |
| 4749 | 14, 4, // 9430: case 0xe: { |
| 4750 | OPC_Decode, 216, 10, 119, // 9432: decode to VPICKVE2GR_B using decoder 119 |
| 4751 | // 9432: } |
| 4752 | 15, 0, // 9436: case 0xf: { |
| 4753 | OPC_SwitchField, 13, 1, // 9438: switch Inst[13] { |
| 4754 | 0, 4, // 9441: case 0x0: { |
| 4755 | OPC_Decode, 220, 10, 120, // 9443: decode to VPICKVE2GR_H using decoder 120 |
| 4756 | // 9443: } |
| 4757 | 1, 0, // 9447: case 0x1: { |
| 4758 | OPC_SwitchField, 12, 1, // 9449: switch Inst[12] { |
| 4759 | 0, 4, // 9452: case 0x0: { |
| 4760 | OPC_Decode, 222, 10, 121, // 9454: decode to VPICKVE2GR_W using decoder 121 |
| 4761 | // 9454: } |
| 4762 | 1, 0, // 9458: case 0x1: { |
| 4763 | OPC_CheckField, 11, 1, 0, // 9460: check Inst[11] == 0x0 |
| 4764 | OPC_Decode, 218, 10, 122, // 9464: decode to VPICKVE2GR_D using decoder 122 |
| 4765 | // 9464: } |
| 4766 | // 9464: } // switch Inst[12] |
| 4767 | // 9464: } |
| 4768 | // 9464: } // switch Inst[13] |
| 4769 | // 9464: } |
| 4770 | // 9464: } // switch Inst[17:14] |
| 4771 | // 9464: } |
| 4772 | 188, 1, 41, // 9468: case 0xbc: { |
| 4773 | OPC_SwitchField, 14, 4, // 9471: switch Inst[17:14] { |
| 4774 | 14, 4, // 9474: case 0xe: { |
| 4775 | OPC_Decode, 217, 10, 119, // 9476: decode to VPICKVE2GR_BU using decoder 119 |
| 4776 | // 9476: } |
| 4777 | 15, 0, // 9480: case 0xf: { |
| 4778 | OPC_SwitchField, 13, 1, // 9482: switch Inst[13] { |
| 4779 | 0, 4, // 9485: case 0x0: { |
| 4780 | OPC_Decode, 221, 10, 120, // 9487: decode to VPICKVE2GR_HU using decoder 120 |
| 4781 | // 9487: } |
| 4782 | 1, 0, // 9491: case 0x1: { |
| 4783 | OPC_SwitchField, 12, 1, // 9493: switch Inst[12] { |
| 4784 | 0, 4, // 9496: case 0x0: { |
| 4785 | OPC_Decode, 223, 10, 121, // 9498: decode to VPICKVE2GR_WU using decoder 121 |
| 4786 | // 9498: } |
| 4787 | 1, 0, // 9502: case 0x1: { |
| 4788 | OPC_CheckField, 11, 1, 0, // 9504: check Inst[11] == 0x0 |
| 4789 | OPC_Decode, 219, 10, 122, // 9508: decode to VPICKVE2GR_DU using decoder 122 |
| 4790 | // 9508: } |
| 4791 | // 9508: } // switch Inst[12] |
| 4792 | // 9508: } |
| 4793 | // 9508: } // switch Inst[13] |
| 4794 | // 9508: } |
| 4795 | // 9508: } // switch Inst[17:14] |
| 4796 | // 9508: } |
| 4797 | 189, 1, 41, // 9512: case 0xbd: { |
| 4798 | OPC_SwitchField, 14, 4, // 9515: switch Inst[17:14] { |
| 4799 | 14, 4, // 9518: case 0xe: { |
| 4800 | OPC_Decode, 228, 10, 113, // 9520: decode to VREPLVEI_B using decoder 113 |
| 4801 | // 9520: } |
| 4802 | 15, 0, // 9524: case 0xf: { |
| 4803 | OPC_SwitchField, 13, 1, // 9526: switch Inst[13] { |
| 4804 | 0, 4, // 9529: case 0x0: { |
| 4805 | OPC_Decode, 230, 10, 112, // 9531: decode to VREPLVEI_H using decoder 112 |
| 4806 | // 9531: } |
| 4807 | 1, 0, // 9535: case 0x1: { |
| 4808 | OPC_SwitchField, 12, 1, // 9537: switch Inst[12] { |
| 4809 | 0, 4, // 9540: case 0x0: { |
| 4810 | OPC_Decode, 231, 10, 123, // 9542: decode to VREPLVEI_W using decoder 123 |
| 4811 | // 9542: } |
| 4812 | 1, 0, // 9546: case 0x1: { |
| 4813 | OPC_CheckField, 11, 1, 0, // 9548: check Inst[11] == 0x0 |
| 4814 | OPC_Decode, 229, 10, 124, // 9552: decode to VREPLVEI_D using decoder 124 |
| 4815 | // 9552: } |
| 4816 | // 9552: } // switch Inst[12] |
| 4817 | // 9552: } |
| 4818 | // 9552: } // switch Inst[13] |
| 4819 | // 9552: } |
| 4820 | // 9552: } // switch Inst[17:14] |
| 4821 | // 9552: } |
| 4822 | 194, 1, 40, // 9556: case 0xc2: { |
| 4823 | OPC_SwitchField, 15, 3, // 9559: switch Inst[17:15] { |
| 4824 | 0, 19, // 9562: case 0x0: { |
| 4825 | OPC_SwitchField, 14, 1, // 9564: switch Inst[14] { |
| 4826 | 0, 8, // 9567: case 0x0: { |
| 4827 | OPC_CheckField, 13, 1, 1, // 9569: check Inst[13] == 0x1 |
| 4828 | OPC_Decode, 185, 11, 112, // 9573: decode to VSLLWIL_H_B using decoder 112 |
| 4829 | // 9573: } |
| 4830 | 1, 0, // 9577: case 0x1: { |
| 4831 | OPC_Decode, 187, 11, 113, // 9579: decode to VSLLWIL_W_H using decoder 113 |
| 4832 | // 9579: } |
| 4833 | // 9579: } // switch Inst[14] |
| 4834 | // 9579: } |
| 4835 | 1, 4, // 9583: case 0x1: { |
| 4836 | OPC_Decode, 183, 11, 107, // 9585: decode to VSLLWIL_D_W using decoder 107 |
| 4837 | // 9585: } |
| 4838 | 2, 0, // 9589: case 0x2: { |
| 4839 | OPC_CheckField, 10, 5, 0, // 9591: check Inst[14:10] == 0x0 |
| 4840 | OPC_Decode, 150, 8, 109, // 9595: decode to VEXTL_Q_D using decoder 109 |
| 4841 | // 9595: } |
| 4842 | // 9595: } // switch Inst[17:15] |
| 4843 | // 9595: } |
| 4844 | 195, 1, 40, // 9599: case 0xc3: { |
| 4845 | OPC_SwitchField, 15, 3, // 9602: switch Inst[17:15] { |
| 4846 | 0, 19, // 9605: case 0x0: { |
| 4847 | OPC_SwitchField, 14, 1, // 9607: switch Inst[14] { |
| 4848 | 0, 8, // 9610: case 0x0: { |
| 4849 | OPC_CheckField, 13, 1, 1, // 9612: check Inst[13] == 0x1 |
| 4850 | OPC_Decode, 184, 11, 112, // 9616: decode to VSLLWIL_HU_BU using decoder 112 |
| 4851 | // 9616: } |
| 4852 | 1, 0, // 9620: case 0x1: { |
| 4853 | OPC_Decode, 186, 11, 113, // 9622: decode to VSLLWIL_WU_HU using decoder 113 |
| 4854 | // 9622: } |
| 4855 | // 9622: } // switch Inst[14] |
| 4856 | // 9622: } |
| 4857 | 1, 4, // 9626: case 0x1: { |
| 4858 | OPC_Decode, 182, 11, 107, // 9628: decode to VSLLWIL_DU_WU using decoder 107 |
| 4859 | // 9628: } |
| 4860 | 2, 0, // 9632: case 0x2: { |
| 4861 | OPC_CheckField, 10, 5, 0, // 9634: check Inst[14:10] == 0x0 |
| 4862 | OPC_Decode, 149, 8, 109, // 9638: decode to VEXTL_QU_DU using decoder 109 |
| 4863 | // 9638: } |
| 4864 | // 9638: } // switch Inst[17:15] |
| 4865 | // 9638: } |
| 4866 | 196, 1, 41, // 9642: case 0xc4: { |
| 4867 | OPC_SwitchField, 16, 2, // 9645: switch Inst[17:16] { |
| 4868 | 0, 30, // 9648: case 0x0: { |
| 4869 | OPC_SwitchField, 15, 1, // 9650: switch Inst[15] { |
| 4870 | 0, 19, // 9653: case 0x0: { |
| 4871 | OPC_SwitchField, 14, 1, // 9655: switch Inst[14] { |
| 4872 | 0, 8, // 9658: case 0x0: { |
| 4873 | OPC_CheckField, 13, 1, 1, // 9660: check Inst[13] == 0x1 |
| 4874 | OPC_Decode, 213, 7, 112, // 9664: decode to VBITCLRI_B using decoder 112 |
| 4875 | // 9664: } |
| 4876 | 1, 0, // 9668: case 0x1: { |
| 4877 | OPC_Decode, 215, 7, 113, // 9670: decode to VBITCLRI_H using decoder 113 |
| 4878 | // 9670: } |
| 4879 | // 9670: } // switch Inst[14] |
| 4880 | // 9670: } |
| 4881 | 1, 0, // 9674: case 0x1: { |
| 4882 | OPC_Decode, 216, 7, 107, // 9676: decode to VBITCLRI_W using decoder 107 |
| 4883 | // 9676: } |
| 4884 | // 9676: } // switch Inst[15] |
| 4885 | // 9676: } |
| 4886 | 1, 0, // 9680: case 0x1: { |
| 4887 | OPC_Decode, 214, 7, 114, // 9682: decode to VBITCLRI_D using decoder 114 |
| 4888 | // 9682: } |
| 4889 | // 9682: } // switch Inst[17:16] |
| 4890 | // 9682: } |
| 4891 | 197, 1, 41, // 9686: case 0xc5: { |
| 4892 | OPC_SwitchField, 16, 2, // 9689: switch Inst[17:16] { |
| 4893 | 0, 30, // 9692: case 0x0: { |
| 4894 | OPC_SwitchField, 15, 1, // 9694: switch Inst[15] { |
| 4895 | 0, 19, // 9697: case 0x0: { |
| 4896 | OPC_SwitchField, 14, 1, // 9699: switch Inst[14] { |
| 4897 | 0, 8, // 9702: case 0x0: { |
| 4898 | OPC_CheckField, 13, 1, 1, // 9704: check Inst[13] == 0x1 |
| 4899 | OPC_Decode, 231, 7, 112, // 9708: decode to VBITSETI_B using decoder 112 |
| 4900 | // 9708: } |
| 4901 | 1, 0, // 9712: case 0x1: { |
| 4902 | OPC_Decode, 233, 7, 113, // 9714: decode to VBITSETI_H using decoder 113 |
| 4903 | // 9714: } |
| 4904 | // 9714: } // switch Inst[14] |
| 4905 | // 9714: } |
| 4906 | 1, 0, // 9718: case 0x1: { |
| 4907 | OPC_Decode, 234, 7, 107, // 9720: decode to VBITSETI_W using decoder 107 |
| 4908 | // 9720: } |
| 4909 | // 9720: } // switch Inst[15] |
| 4910 | // 9720: } |
| 4911 | 1, 0, // 9724: case 0x1: { |
| 4912 | OPC_Decode, 232, 7, 114, // 9726: decode to VBITSETI_D using decoder 114 |
| 4913 | // 9726: } |
| 4914 | // 9726: } // switch Inst[17:16] |
| 4915 | // 9726: } |
| 4916 | 198, 1, 41, // 9730: case 0xc6: { |
| 4917 | OPC_SwitchField, 16, 2, // 9733: switch Inst[17:16] { |
| 4918 | 0, 30, // 9736: case 0x0: { |
| 4919 | OPC_SwitchField, 15, 1, // 9738: switch Inst[15] { |
| 4920 | 0, 19, // 9741: case 0x0: { |
| 4921 | OPC_SwitchField, 14, 1, // 9743: switch Inst[14] { |
| 4922 | 0, 8, // 9746: case 0x0: { |
| 4923 | OPC_CheckField, 13, 1, 1, // 9748: check Inst[13] == 0x1 |
| 4924 | OPC_Decode, 221, 7, 112, // 9752: decode to VBITREVI_B using decoder 112 |
| 4925 | // 9752: } |
| 4926 | 1, 0, // 9756: case 0x1: { |
| 4927 | OPC_Decode, 223, 7, 113, // 9758: decode to VBITREVI_H using decoder 113 |
| 4928 | // 9758: } |
| 4929 | // 9758: } // switch Inst[14] |
| 4930 | // 9758: } |
| 4931 | 1, 0, // 9762: case 0x1: { |
| 4932 | OPC_Decode, 224, 7, 107, // 9764: decode to VBITREVI_W using decoder 107 |
| 4933 | // 9764: } |
| 4934 | // 9764: } // switch Inst[15] |
| 4935 | // 9764: } |
| 4936 | 1, 0, // 9768: case 0x1: { |
| 4937 | OPC_Decode, 222, 7, 114, // 9770: decode to VBITREVI_D using decoder 114 |
| 4938 | // 9770: } |
| 4939 | // 9770: } // switch Inst[17:16] |
| 4940 | // 9770: } |
| 4941 | 201, 1, 41, // 9774: case 0xc9: { |
| 4942 | OPC_SwitchField, 16, 2, // 9777: switch Inst[17:16] { |
| 4943 | 0, 30, // 9780: case 0x0: { |
| 4944 | OPC_SwitchField, 15, 1, // 9782: switch Inst[15] { |
| 4945 | 0, 19, // 9785: case 0x0: { |
| 4946 | OPC_SwitchField, 14, 1, // 9787: switch Inst[14] { |
| 4947 | 0, 8, // 9790: case 0x0: { |
| 4948 | OPC_CheckField, 13, 1, 1, // 9792: check Inst[13] == 0x1 |
| 4949 | OPC_Decode, 252, 10, 112, // 9796: decode to VSAT_B using decoder 112 |
| 4950 | // 9796: } |
| 4951 | 1, 0, // 9800: case 0x1: { |
| 4952 | OPC_Decode, 128, 11, 113, // 9802: decode to VSAT_H using decoder 113 |
| 4953 | // 9802: } |
| 4954 | // 9802: } // switch Inst[14] |
| 4955 | // 9802: } |
| 4956 | 1, 0, // 9806: case 0x1: { |
| 4957 | OPC_Decode, 130, 11, 107, // 9808: decode to VSAT_W using decoder 107 |
| 4958 | // 9808: } |
| 4959 | // 9808: } // switch Inst[15] |
| 4960 | // 9808: } |
| 4961 | 1, 0, // 9812: case 0x1: { |
| 4962 | OPC_Decode, 254, 10, 114, // 9814: decode to VSAT_D using decoder 114 |
| 4963 | // 9814: } |
| 4964 | // 9814: } // switch Inst[17:16] |
| 4965 | // 9814: } |
| 4966 | 202, 1, 41, // 9818: case 0xca: { |
| 4967 | OPC_SwitchField, 16, 2, // 9821: switch Inst[17:16] { |
| 4968 | 0, 30, // 9824: case 0x0: { |
| 4969 | OPC_SwitchField, 15, 1, // 9826: switch Inst[15] { |
| 4970 | 0, 19, // 9829: case 0x0: { |
| 4971 | OPC_SwitchField, 14, 1, // 9831: switch Inst[14] { |
| 4972 | 0, 8, // 9834: case 0x0: { |
| 4973 | OPC_CheckField, 13, 1, 1, // 9836: check Inst[13] == 0x1 |
| 4974 | OPC_Decode, 253, 10, 112, // 9840: decode to VSAT_BU using decoder 112 |
| 4975 | // 9840: } |
| 4976 | 1, 0, // 9844: case 0x1: { |
| 4977 | OPC_Decode, 129, 11, 113, // 9846: decode to VSAT_HU using decoder 113 |
| 4978 | // 9846: } |
| 4979 | // 9846: } // switch Inst[14] |
| 4980 | // 9846: } |
| 4981 | 1, 0, // 9850: case 0x1: { |
| 4982 | OPC_Decode, 131, 11, 107, // 9852: decode to VSAT_WU using decoder 107 |
| 4983 | // 9852: } |
| 4984 | // 9852: } // switch Inst[15] |
| 4985 | // 9852: } |
| 4986 | 1, 0, // 9856: case 0x1: { |
| 4987 | OPC_Decode, 255, 10, 114, // 9858: decode to VSAT_DU using decoder 114 |
| 4988 | // 9858: } |
| 4989 | // 9858: } // switch Inst[17:16] |
| 4990 | // 9858: } |
| 4991 | 203, 1, 41, // 9862: case 0xcb: { |
| 4992 | OPC_SwitchField, 16, 2, // 9865: switch Inst[17:16] { |
| 4993 | 0, 30, // 9868: case 0x0: { |
| 4994 | OPC_SwitchField, 15, 1, // 9870: switch Inst[15] { |
| 4995 | 0, 19, // 9873: case 0x0: { |
| 4996 | OPC_SwitchField, 14, 1, // 9875: switch Inst[14] { |
| 4997 | 0, 8, // 9878: case 0x0: { |
| 4998 | OPC_CheckField, 13, 1, 1, // 9880: check Inst[13] == 0x1 |
| 4999 | OPC_Decode, 178, 11, 112, // 9884: decode to VSLLI_B using decoder 112 |
| 5000 | // 9884: } |
| 5001 | 1, 0, // 9888: case 0x1: { |
| 5002 | OPC_Decode, 180, 11, 113, // 9890: decode to VSLLI_H using decoder 113 |
| 5003 | // 9890: } |
| 5004 | // 9890: } // switch Inst[14] |
| 5005 | // 9890: } |
| 5006 | 1, 0, // 9894: case 0x1: { |
| 5007 | OPC_Decode, 181, 11, 107, // 9896: decode to VSLLI_W using decoder 107 |
| 5008 | // 9896: } |
| 5009 | // 9896: } // switch Inst[15] |
| 5010 | // 9896: } |
| 5011 | 1, 0, // 9900: case 0x1: { |
| 5012 | OPC_Decode, 179, 11, 114, // 9902: decode to VSLLI_D using decoder 114 |
| 5013 | // 9902: } |
| 5014 | // 9902: } // switch Inst[17:16] |
| 5015 | // 9902: } |
| 5016 | 204, 1, 41, // 9906: case 0xcc: { |
| 5017 | OPC_SwitchField, 16, 2, // 9909: switch Inst[17:16] { |
| 5018 | 0, 30, // 9912: case 0x0: { |
| 5019 | OPC_SwitchField, 15, 1, // 9914: switch Inst[15] { |
| 5020 | 0, 19, // 9917: case 0x0: { |
| 5021 | OPC_SwitchField, 14, 1, // 9919: switch Inst[14] { |
| 5022 | 0, 8, // 9922: case 0x0: { |
| 5023 | OPC_CheckField, 13, 1, 1, // 9924: check Inst[13] == 0x1 |
| 5024 | OPC_Decode, 238, 11, 112, // 9928: decode to VSRLI_B using decoder 112 |
| 5025 | // 9928: } |
| 5026 | 1, 0, // 9932: case 0x1: { |
| 5027 | OPC_Decode, 240, 11, 113, // 9934: decode to VSRLI_H using decoder 113 |
| 5028 | // 9934: } |
| 5029 | // 9934: } // switch Inst[14] |
| 5030 | // 9934: } |
| 5031 | 1, 0, // 9938: case 0x1: { |
| 5032 | OPC_Decode, 241, 11, 107, // 9940: decode to VSRLI_W using decoder 107 |
| 5033 | // 9940: } |
| 5034 | // 9940: } // switch Inst[15] |
| 5035 | // 9940: } |
| 5036 | 1, 0, // 9944: case 0x1: { |
| 5037 | OPC_Decode, 239, 11, 114, // 9946: decode to VSRLI_D using decoder 114 |
| 5038 | // 9946: } |
| 5039 | // 9946: } // switch Inst[17:16] |
| 5040 | // 9946: } |
| 5041 | 205, 1, 41, // 9950: case 0xcd: { |
| 5042 | OPC_SwitchField, 16, 2, // 9953: switch Inst[17:16] { |
| 5043 | 0, 30, // 9956: case 0x0: { |
| 5044 | OPC_SwitchField, 15, 1, // 9958: switch Inst[15] { |
| 5045 | 0, 19, // 9961: case 0x0: { |
| 5046 | OPC_SwitchField, 14, 1, // 9963: switch Inst[14] { |
| 5047 | 0, 8, // 9966: case 0x0: { |
| 5048 | OPC_CheckField, 13, 1, 1, // 9968: check Inst[13] == 0x1 |
| 5049 | OPC_Decode, 208, 11, 112, // 9972: decode to VSRAI_B using decoder 112 |
| 5050 | // 9972: } |
| 5051 | 1, 0, // 9976: case 0x1: { |
| 5052 | OPC_Decode, 210, 11, 113, // 9978: decode to VSRAI_H using decoder 113 |
| 5053 | // 9978: } |
| 5054 | // 9978: } // switch Inst[14] |
| 5055 | // 9978: } |
| 5056 | 1, 0, // 9982: case 0x1: { |
| 5057 | OPC_Decode, 211, 11, 107, // 9984: decode to VSRAI_W using decoder 107 |
| 5058 | // 9984: } |
| 5059 | // 9984: } // switch Inst[15] |
| 5060 | // 9984: } |
| 5061 | 1, 0, // 9988: case 0x1: { |
| 5062 | OPC_Decode, 209, 11, 114, // 9990: decode to VSRAI_D using decoder 114 |
| 5063 | // 9990: } |
| 5064 | // 9990: } // switch Inst[17:16] |
| 5065 | // 9990: } |
| 5066 | 208, 1, 41, // 9994: case 0xd0: { |
| 5067 | OPC_SwitchField, 17, 1, // 9997: switch Inst[17] { |
| 5068 | 0, 30, // 10000: case 0x0: { |
| 5069 | OPC_SwitchField, 16, 1, // 10002: switch Inst[16] { |
| 5070 | 0, 19, // 10005: case 0x0: { |
| 5071 | OPC_SwitchField, 15, 1, // 10007: switch Inst[15] { |
| 5072 | 0, 8, // 10010: case 0x0: { |
| 5073 | OPC_CheckField, 14, 1, 1, // 10012: check Inst[14] == 0x1 |
| 5074 | OPC_Decode, 242, 11, 125, // 10016: decode to VSRLNI_B_H using decoder 125 |
| 5075 | // 10016: } |
| 5076 | 1, 0, // 10020: case 0x1: { |
| 5077 | OPC_Decode, 244, 11, 108, // 10022: decode to VSRLNI_H_W using decoder 108 |
| 5078 | // 10022: } |
| 5079 | // 10022: } // switch Inst[15] |
| 5080 | // 10022: } |
| 5081 | 1, 0, // 10026: case 0x1: { |
| 5082 | OPC_Decode, 245, 11, 126, // 10028: decode to VSRLNI_W_D using decoder 126 |
| 5083 | // 10028: } |
| 5084 | // 10028: } // switch Inst[16] |
| 5085 | // 10028: } |
| 5086 | 1, 0, // 10032: case 0x1: { |
| 5087 | OPC_Decode, 243, 11, 127, // 10034: decode to VSRLNI_D_Q using decoder 127 |
| 5088 | // 10034: } |
| 5089 | // 10034: } // switch Inst[17] |
| 5090 | // 10034: } |
| 5091 | 209, 1, 41, // 10038: case 0xd1: { |
| 5092 | OPC_SwitchField, 17, 1, // 10041: switch Inst[17] { |
| 5093 | 0, 30, // 10044: case 0x0: { |
| 5094 | OPC_SwitchField, 16, 1, // 10046: switch Inst[16] { |
| 5095 | 0, 19, // 10049: case 0x0: { |
| 5096 | OPC_SwitchField, 15, 1, // 10051: switch Inst[15] { |
| 5097 | 0, 8, // 10054: case 0x0: { |
| 5098 | OPC_CheckField, 14, 1, 1, // 10056: check Inst[14] == 0x1 |
| 5099 | OPC_Decode, 253, 11, 125, // 10060: decode to VSRLRNI_B_H using decoder 125 |
| 5100 | // 10060: } |
| 5101 | 1, 0, // 10064: case 0x1: { |
| 5102 | OPC_Decode, 255, 11, 108, // 10066: decode to VSRLRNI_H_W using decoder 108 |
| 5103 | // 10066: } |
| 5104 | // 10066: } // switch Inst[15] |
| 5105 | // 10066: } |
| 5106 | 1, 0, // 10070: case 0x1: { |
| 5107 | OPC_Decode, 128, 12, 126, // 10072: decode to VSRLRNI_W_D using decoder 126 |
| 5108 | // 10072: } |
| 5109 | // 10072: } // switch Inst[16] |
| 5110 | // 10072: } |
| 5111 | 1, 0, // 10076: case 0x1: { |
| 5112 | OPC_Decode, 254, 11, 127, // 10078: decode to VSRLRNI_D_Q using decoder 127 |
| 5113 | // 10078: } |
| 5114 | // 10078: } // switch Inst[17] |
| 5115 | // 10078: } |
| 5116 | 210, 1, 41, // 10082: case 0xd2: { |
| 5117 | OPC_SwitchField, 17, 1, // 10085: switch Inst[17] { |
| 5118 | 0, 30, // 10088: case 0x0: { |
| 5119 | OPC_SwitchField, 16, 1, // 10090: switch Inst[16] { |
| 5120 | 0, 19, // 10093: case 0x0: { |
| 5121 | OPC_SwitchField, 15, 1, // 10095: switch Inst[15] { |
| 5122 | 0, 8, // 10098: case 0x0: { |
| 5123 | OPC_CheckField, 14, 1, 1, // 10100: check Inst[14] == 0x1 |
| 5124 | OPC_Decode, 169, 12, 125, // 10104: decode to VSSRLNI_B_H using decoder 125 |
| 5125 | // 10104: } |
| 5126 | 1, 0, // 10108: case 0x1: { |
| 5127 | OPC_Decode, 173, 12, 108, // 10110: decode to VSSRLNI_H_W using decoder 108 |
| 5128 | // 10110: } |
| 5129 | // 10110: } // switch Inst[15] |
| 5130 | // 10110: } |
| 5131 | 1, 0, // 10114: case 0x1: { |
| 5132 | OPC_Decode, 175, 12, 126, // 10116: decode to VSSRLNI_W_D using decoder 126 |
| 5133 | // 10116: } |
| 5134 | // 10116: } // switch Inst[16] |
| 5135 | // 10116: } |
| 5136 | 1, 0, // 10120: case 0x1: { |
| 5137 | OPC_Decode, 171, 12, 127, // 10122: decode to VSSRLNI_D_Q using decoder 127 |
| 5138 | // 10122: } |
| 5139 | // 10122: } // switch Inst[17] |
| 5140 | // 10122: } |
| 5141 | 211, 1, 41, // 10126: case 0xd3: { |
| 5142 | OPC_SwitchField, 17, 1, // 10129: switch Inst[17] { |
| 5143 | 0, 30, // 10132: case 0x0: { |
| 5144 | OPC_SwitchField, 16, 1, // 10134: switch Inst[16] { |
| 5145 | 0, 19, // 10137: case 0x0: { |
| 5146 | OPC_SwitchField, 15, 1, // 10139: switch Inst[15] { |
| 5147 | 0, 8, // 10142: case 0x0: { |
| 5148 | OPC_CheckField, 14, 1, 1, // 10144: check Inst[14] == 0x1 |
| 5149 | OPC_Decode, 168, 12, 125, // 10148: decode to VSSRLNI_BU_H using decoder 125 |
| 5150 | // 10148: } |
| 5151 | 1, 0, // 10152: case 0x1: { |
| 5152 | OPC_Decode, 172, 12, 108, // 10154: decode to VSSRLNI_HU_W using decoder 108 |
| 5153 | // 10154: } |
| 5154 | // 10154: } // switch Inst[15] |
| 5155 | // 10154: } |
| 5156 | 1, 0, // 10158: case 0x1: { |
| 5157 | OPC_Decode, 174, 12, 126, // 10160: decode to VSSRLNI_WU_D using decoder 126 |
| 5158 | // 10160: } |
| 5159 | // 10160: } // switch Inst[16] |
| 5160 | // 10160: } |
| 5161 | 1, 0, // 10164: case 0x1: { |
| 5162 | OPC_Decode, 170, 12, 127, // 10166: decode to VSSRLNI_DU_Q using decoder 127 |
| 5163 | // 10166: } |
| 5164 | // 10166: } // switch Inst[17] |
| 5165 | // 10166: } |
| 5166 | 212, 1, 41, // 10170: case 0xd4: { |
| 5167 | OPC_SwitchField, 17, 1, // 10173: switch Inst[17] { |
| 5168 | 0, 30, // 10176: case 0x0: { |
| 5169 | OPC_SwitchField, 16, 1, // 10178: switch Inst[16] { |
| 5170 | 0, 19, // 10181: case 0x0: { |
| 5171 | OPC_SwitchField, 15, 1, // 10183: switch Inst[15] { |
| 5172 | 0, 8, // 10186: case 0x0: { |
| 5173 | OPC_CheckField, 14, 1, 1, // 10188: check Inst[14] == 0x1 |
| 5174 | OPC_Decode, 183, 12, 125, // 10192: decode to VSSRLRNI_B_H using decoder 125 |
| 5175 | // 10192: } |
| 5176 | 1, 0, // 10196: case 0x1: { |
| 5177 | OPC_Decode, 187, 12, 108, // 10198: decode to VSSRLRNI_H_W using decoder 108 |
| 5178 | // 10198: } |
| 5179 | // 10198: } // switch Inst[15] |
| 5180 | // 10198: } |
| 5181 | 1, 0, // 10202: case 0x1: { |
| 5182 | OPC_Decode, 189, 12, 126, // 10204: decode to VSSRLRNI_W_D using decoder 126 |
| 5183 | // 10204: } |
| 5184 | // 10204: } // switch Inst[16] |
| 5185 | // 10204: } |
| 5186 | 1, 0, // 10208: case 0x1: { |
| 5187 | OPC_Decode, 185, 12, 127, // 10210: decode to VSSRLRNI_D_Q using decoder 127 |
| 5188 | // 10210: } |
| 5189 | // 10210: } // switch Inst[17] |
| 5190 | // 10210: } |
| 5191 | 213, 1, 41, // 10214: case 0xd5: { |
| 5192 | OPC_SwitchField, 17, 1, // 10217: switch Inst[17] { |
| 5193 | 0, 30, // 10220: case 0x0: { |
| 5194 | OPC_SwitchField, 16, 1, // 10222: switch Inst[16] { |
| 5195 | 0, 19, // 10225: case 0x0: { |
| 5196 | OPC_SwitchField, 15, 1, // 10227: switch Inst[15] { |
| 5197 | 0, 8, // 10230: case 0x0: { |
| 5198 | OPC_CheckField, 14, 1, 1, // 10232: check Inst[14] == 0x1 |
| 5199 | OPC_Decode, 182, 12, 125, // 10236: decode to VSSRLRNI_BU_H using decoder 125 |
| 5200 | // 10236: } |
| 5201 | 1, 0, // 10240: case 0x1: { |
| 5202 | OPC_Decode, 186, 12, 108, // 10242: decode to VSSRLRNI_HU_W using decoder 108 |
| 5203 | // 10242: } |
| 5204 | // 10242: } // switch Inst[15] |
| 5205 | // 10242: } |
| 5206 | 1, 0, // 10246: case 0x1: { |
| 5207 | OPC_Decode, 188, 12, 126, // 10248: decode to VSSRLRNI_WU_D using decoder 126 |
| 5208 | // 10248: } |
| 5209 | // 10248: } // switch Inst[16] |
| 5210 | // 10248: } |
| 5211 | 1, 0, // 10252: case 0x1: { |
| 5212 | OPC_Decode, 184, 12, 127, // 10254: decode to VSSRLRNI_DU_Q using decoder 127 |
| 5213 | // 10254: } |
| 5214 | // 10254: } // switch Inst[17] |
| 5215 | // 10254: } |
| 5216 | 214, 1, 41, // 10258: case 0xd6: { |
| 5217 | OPC_SwitchField, 17, 1, // 10261: switch Inst[17] { |
| 5218 | 0, 30, // 10264: case 0x0: { |
| 5219 | OPC_SwitchField, 16, 1, // 10266: switch Inst[16] { |
| 5220 | 0, 19, // 10269: case 0x0: { |
| 5221 | OPC_SwitchField, 15, 1, // 10271: switch Inst[15] { |
| 5222 | 0, 8, // 10274: case 0x0: { |
| 5223 | OPC_CheckField, 14, 1, 1, // 10276: check Inst[14] == 0x1 |
| 5224 | OPC_Decode, 212, 11, 125, // 10280: decode to VSRANI_B_H using decoder 125 |
| 5225 | // 10280: } |
| 5226 | 1, 0, // 10284: case 0x1: { |
| 5227 | OPC_Decode, 214, 11, 108, // 10286: decode to VSRANI_H_W using decoder 108 |
| 5228 | // 10286: } |
| 5229 | // 10286: } // switch Inst[15] |
| 5230 | // 10286: } |
| 5231 | 1, 0, // 10290: case 0x1: { |
| 5232 | OPC_Decode, 215, 11, 126, // 10292: decode to VSRANI_W_D using decoder 126 |
| 5233 | // 10292: } |
| 5234 | // 10292: } // switch Inst[16] |
| 5235 | // 10292: } |
| 5236 | 1, 0, // 10296: case 0x1: { |
| 5237 | OPC_Decode, 213, 11, 127, // 10298: decode to VSRANI_D_Q using decoder 127 |
| 5238 | // 10298: } |
| 5239 | // 10298: } // switch Inst[17] |
| 5240 | // 10298: } |
| 5241 | 215, 1, 41, // 10302: case 0xd7: { |
| 5242 | OPC_SwitchField, 17, 1, // 10305: switch Inst[17] { |
| 5243 | 0, 30, // 10308: case 0x0: { |
| 5244 | OPC_SwitchField, 16, 1, // 10310: switch Inst[16] { |
| 5245 | 0, 19, // 10313: case 0x0: { |
| 5246 | OPC_SwitchField, 15, 1, // 10315: switch Inst[15] { |
| 5247 | 0, 8, // 10318: case 0x0: { |
| 5248 | OPC_CheckField, 14, 1, 1, // 10320: check Inst[14] == 0x1 |
| 5249 | OPC_Decode, 223, 11, 125, // 10324: decode to VSRARNI_B_H using decoder 125 |
| 5250 | // 10324: } |
| 5251 | 1, 0, // 10328: case 0x1: { |
| 5252 | OPC_Decode, 225, 11, 108, // 10330: decode to VSRARNI_H_W using decoder 108 |
| 5253 | // 10330: } |
| 5254 | // 10330: } // switch Inst[15] |
| 5255 | // 10330: } |
| 5256 | 1, 0, // 10334: case 0x1: { |
| 5257 | OPC_Decode, 226, 11, 126, // 10336: decode to VSRARNI_W_D using decoder 126 |
| 5258 | // 10336: } |
| 5259 | // 10336: } // switch Inst[16] |
| 5260 | // 10336: } |
| 5261 | 1, 0, // 10340: case 0x1: { |
| 5262 | OPC_Decode, 224, 11, 127, // 10342: decode to VSRARNI_D_Q using decoder 127 |
| 5263 | // 10342: } |
| 5264 | // 10342: } // switch Inst[17] |
| 5265 | // 10342: } |
| 5266 | 216, 1, 41, // 10346: case 0xd8: { |
| 5267 | OPC_SwitchField, 17, 1, // 10349: switch Inst[17] { |
| 5268 | 0, 30, // 10352: case 0x0: { |
| 5269 | OPC_SwitchField, 16, 1, // 10354: switch Inst[16] { |
| 5270 | 0, 19, // 10357: case 0x0: { |
| 5271 | OPC_SwitchField, 15, 1, // 10359: switch Inst[15] { |
| 5272 | 0, 8, // 10362: case 0x0: { |
| 5273 | OPC_CheckField, 14, 1, 1, // 10364: check Inst[14] == 0x1 |
| 5274 | OPC_Decode, 141, 12, 125, // 10368: decode to VSSRANI_B_H using decoder 125 |
| 5275 | // 10368: } |
| 5276 | 1, 0, // 10372: case 0x1: { |
| 5277 | OPC_Decode, 145, 12, 108, // 10374: decode to VSSRANI_H_W using decoder 108 |
| 5278 | // 10374: } |
| 5279 | // 10374: } // switch Inst[15] |
| 5280 | // 10374: } |
| 5281 | 1, 0, // 10378: case 0x1: { |
| 5282 | OPC_Decode, 147, 12, 126, // 10380: decode to VSSRANI_W_D using decoder 126 |
| 5283 | // 10380: } |
| 5284 | // 10380: } // switch Inst[16] |
| 5285 | // 10380: } |
| 5286 | 1, 0, // 10384: case 0x1: { |
| 5287 | OPC_Decode, 143, 12, 127, // 10386: decode to VSSRANI_D_Q using decoder 127 |
| 5288 | // 10386: } |
| 5289 | // 10386: } // switch Inst[17] |
| 5290 | // 10386: } |
| 5291 | 217, 1, 41, // 10390: case 0xd9: { |
| 5292 | OPC_SwitchField, 17, 1, // 10393: switch Inst[17] { |
| 5293 | 0, 30, // 10396: case 0x0: { |
| 5294 | OPC_SwitchField, 16, 1, // 10398: switch Inst[16] { |
| 5295 | 0, 19, // 10401: case 0x0: { |
| 5296 | OPC_SwitchField, 15, 1, // 10403: switch Inst[15] { |
| 5297 | 0, 8, // 10406: case 0x0: { |
| 5298 | OPC_CheckField, 14, 1, 1, // 10408: check Inst[14] == 0x1 |
| 5299 | OPC_Decode, 140, 12, 125, // 10412: decode to VSSRANI_BU_H using decoder 125 |
| 5300 | // 10412: } |
| 5301 | 1, 0, // 10416: case 0x1: { |
| 5302 | OPC_Decode, 144, 12, 108, // 10418: decode to VSSRANI_HU_W using decoder 108 |
| 5303 | // 10418: } |
| 5304 | // 10418: } // switch Inst[15] |
| 5305 | // 10418: } |
| 5306 | 1, 0, // 10422: case 0x1: { |
| 5307 | OPC_Decode, 146, 12, 126, // 10424: decode to VSSRANI_WU_D using decoder 126 |
| 5308 | // 10424: } |
| 5309 | // 10424: } // switch Inst[16] |
| 5310 | // 10424: } |
| 5311 | 1, 0, // 10428: case 0x1: { |
| 5312 | OPC_Decode, 142, 12, 127, // 10430: decode to VSSRANI_DU_Q using decoder 127 |
| 5313 | // 10430: } |
| 5314 | // 10430: } // switch Inst[17] |
| 5315 | // 10430: } |
| 5316 | 218, 1, 41, // 10434: case 0xda: { |
| 5317 | OPC_SwitchField, 17, 1, // 10437: switch Inst[17] { |
| 5318 | 0, 30, // 10440: case 0x0: { |
| 5319 | OPC_SwitchField, 16, 1, // 10442: switch Inst[16] { |
| 5320 | 0, 19, // 10445: case 0x0: { |
| 5321 | OPC_SwitchField, 15, 1, // 10447: switch Inst[15] { |
| 5322 | 0, 8, // 10450: case 0x0: { |
| 5323 | OPC_CheckField, 14, 1, 1, // 10452: check Inst[14] == 0x1 |
| 5324 | OPC_Decode, 155, 12, 125, // 10456: decode to VSSRARNI_B_H using decoder 125 |
| 5325 | // 10456: } |
| 5326 | 1, 0, // 10460: case 0x1: { |
| 5327 | OPC_Decode, 159, 12, 108, // 10462: decode to VSSRARNI_H_W using decoder 108 |
| 5328 | // 10462: } |
| 5329 | // 10462: } // switch Inst[15] |
| 5330 | // 10462: } |
| 5331 | 1, 0, // 10466: case 0x1: { |
| 5332 | OPC_Decode, 161, 12, 126, // 10468: decode to VSSRARNI_W_D using decoder 126 |
| 5333 | // 10468: } |
| 5334 | // 10468: } // switch Inst[16] |
| 5335 | // 10468: } |
| 5336 | 1, 0, // 10472: case 0x1: { |
| 5337 | OPC_Decode, 157, 12, 127, // 10474: decode to VSSRARNI_D_Q using decoder 127 |
| 5338 | // 10474: } |
| 5339 | // 10474: } // switch Inst[17] |
| 5340 | // 10474: } |
| 5341 | 219, 1, 41, // 10478: case 0xdb: { |
| 5342 | OPC_SwitchField, 17, 1, // 10481: switch Inst[17] { |
| 5343 | 0, 30, // 10484: case 0x0: { |
| 5344 | OPC_SwitchField, 16, 1, // 10486: switch Inst[16] { |
| 5345 | 0, 19, // 10489: case 0x0: { |
| 5346 | OPC_SwitchField, 15, 1, // 10491: switch Inst[15] { |
| 5347 | 0, 8, // 10494: case 0x0: { |
| 5348 | OPC_CheckField, 14, 1, 1, // 10496: check Inst[14] == 0x1 |
| 5349 | OPC_Decode, 154, 12, 125, // 10500: decode to VSSRARNI_BU_H using decoder 125 |
| 5350 | // 10500: } |
| 5351 | 1, 0, // 10504: case 0x1: { |
| 5352 | OPC_Decode, 158, 12, 108, // 10506: decode to VSSRARNI_HU_W using decoder 108 |
| 5353 | // 10506: } |
| 5354 | // 10506: } // switch Inst[15] |
| 5355 | // 10506: } |
| 5356 | 1, 0, // 10510: case 0x1: { |
| 5357 | OPC_Decode, 160, 12, 126, // 10512: decode to VSSRARNI_WU_D using decoder 126 |
| 5358 | // 10512: } |
| 5359 | // 10512: } // switch Inst[16] |
| 5360 | // 10512: } |
| 5361 | 1, 0, // 10516: case 0x1: { |
| 5362 | OPC_Decode, 156, 12, 127, // 10518: decode to VSSRARNI_DU_Q using decoder 127 |
| 5363 | // 10518: } |
| 5364 | // 10518: } // switch Inst[17] |
| 5365 | // 10518: } |
| 5366 | 224, 1, 5, // 10522: case 0xe0: { |
| 5367 | OPC_Decode, 152, 8, 128, 1, // 10525: decode to VEXTRINS_D using decoder 128 |
| 5368 | // 10525: } |
| 5369 | 225, 1, 5, // 10530: case 0xe1: { |
| 5370 | OPC_Decode, 154, 8, 128, 1, // 10533: decode to VEXTRINS_W using decoder 128 |
| 5371 | // 10533: } |
| 5372 | 226, 1, 5, // 10538: case 0xe2: { |
| 5373 | OPC_Decode, 153, 8, 128, 1, // 10541: decode to VEXTRINS_H using decoder 128 |
| 5374 | // 10541: } |
| 5375 | 227, 1, 5, // 10546: case 0xe3: { |
| 5376 | OPC_Decode, 151, 8, 128, 1, // 10549: decode to VEXTRINS_B using decoder 128 |
| 5377 | // 10549: } |
| 5378 | 228, 1, 5, // 10554: case 0xe4: { |
| 5379 | OPC_Decode, 150, 11, 129, 1, // 10557: decode to VSHUF4I_B using decoder 129 |
| 5380 | // 10557: } |
| 5381 | 229, 1, 5, // 10562: case 0xe5: { |
| 5382 | OPC_Decode, 152, 11, 129, 1, // 10565: decode to VSHUF4I_H using decoder 129 |
| 5383 | // 10565: } |
| 5384 | 230, 1, 5, // 10570: case 0xe6: { |
| 5385 | OPC_Decode, 153, 11, 129, 1, // 10573: decode to VSHUF4I_W using decoder 129 |
| 5386 | // 10573: } |
| 5387 | 231, 1, 5, // 10578: case 0xe7: { |
| 5388 | OPC_Decode, 151, 11, 128, 1, // 10581: decode to VSHUF4I_D using decoder 128 |
| 5389 | // 10581: } |
| 5390 | 241, 1, 5, // 10586: case 0xf1: { |
| 5391 | OPC_Decode, 229, 7, 128, 1, // 10589: decode to VBITSELI_B using decoder 128 |
| 5392 | // 10589: } |
| 5393 | 244, 1, 5, // 10594: case 0xf4: { |
| 5394 | OPC_Decode, 194, 7, 129, 1, // 10597: decode to VANDI_B using decoder 129 |
| 5395 | // 10597: } |
| 5396 | 245, 1, 5, // 10602: case 0xf5: { |
| 5397 | OPC_Decode, 192, 10, 129, 1, // 10605: decode to VORI_B using decoder 129 |
| 5398 | // 10605: } |
| 5399 | 246, 1, 5, // 10610: case 0xf6: { |
| 5400 | OPC_Decode, 235, 12, 129, 1, // 10613: decode to VXORI_B using decoder 129 |
| 5401 | // 10613: } |
| 5402 | 247, 1, 5, // 10618: case 0xf7: { |
| 5403 | OPC_Decode, 190, 10, 129, 1, // 10621: decode to VNORI_B using decoder 129 |
| 5404 | // 10621: } |
| 5405 | 248, 1, 5, // 10626: case 0xf8: { |
| 5406 | OPC_Decode, 194, 9, 130, 1, // 10629: decode to VLDI using decoder 130 |
| 5407 | // 10629: } |
| 5408 | 249, 1, 0, // 10634: case 0xf9: { |
| 5409 | OPC_Decode, 207, 10, 128, 1, // 10637: decode to VPERMI_W using decoder 128 |
| 5410 | // 10637: } |
| 5411 | // 10637: } // switch Inst[25:18] |
| 5412 | // 10637: } |
| 5413 | 29, 0, // 10642: case 0x1d: { |
| 5414 | OPC_SwitchField, 18, 8, // 10644: switch Inst[25:18] { |
| 5415 | 0, 51, // 10647: case 0x0: { |
| 5416 | OPC_SwitchField, 15, 3, // 10649: switch Inst[17:15] { |
| 5417 | 0, 4, // 10652: case 0x0: { |
| 5418 | OPC_Decode, 206, 17, 64, // 10654: decode to XVSEQ_B using decoder 64 |
| 5419 | // 10654: } |
| 5420 | 1, 4, // 10658: case 0x1: { |
| 5421 | OPC_Decode, 208, 17, 64, // 10660: decode to XVSEQ_H using decoder 64 |
| 5422 | // 10660: } |
| 5423 | 2, 4, // 10664: case 0x2: { |
| 5424 | OPC_Decode, 209, 17, 64, // 10666: decode to XVSEQ_W using decoder 64 |
| 5425 | // 10666: } |
| 5426 | 3, 4, // 10670: case 0x3: { |
| 5427 | OPC_Decode, 207, 17, 64, // 10672: decode to XVSEQ_D using decoder 64 |
| 5428 | // 10672: } |
| 5429 | 4, 4, // 10676: case 0x4: { |
| 5430 | OPC_Decode, 240, 17, 64, // 10678: decode to XVSLE_B using decoder 64 |
| 5431 | // 10678: } |
| 5432 | 5, 4, // 10682: case 0x5: { |
| 5433 | OPC_Decode, 244, 17, 64, // 10684: decode to XVSLE_H using decoder 64 |
| 5434 | // 10684: } |
| 5435 | 6, 4, // 10688: case 0x6: { |
| 5436 | OPC_Decode, 246, 17, 64, // 10690: decode to XVSLE_W using decoder 64 |
| 5437 | // 10690: } |
| 5438 | 7, 0, // 10694: case 0x7: { |
| 5439 | OPC_Decode, 242, 17, 64, // 10696: decode to XVSLE_D using decoder 64 |
| 5440 | // 10696: } |
| 5441 | // 10696: } // switch Inst[17:15] |
| 5442 | // 10696: } |
| 5443 | 1, 51, // 10700: case 0x1: { |
| 5444 | OPC_SwitchField, 15, 3, // 10702: switch Inst[17:15] { |
| 5445 | 0, 4, // 10705: case 0x0: { |
| 5446 | OPC_Decode, 241, 17, 64, // 10707: decode to XVSLE_BU using decoder 64 |
| 5447 | // 10707: } |
| 5448 | 1, 4, // 10711: case 0x1: { |
| 5449 | OPC_Decode, 245, 17, 64, // 10713: decode to XVSLE_HU using decoder 64 |
| 5450 | // 10713: } |
| 5451 | 2, 4, // 10717: case 0x2: { |
| 5452 | OPC_Decode, 247, 17, 64, // 10719: decode to XVSLE_WU using decoder 64 |
| 5453 | // 10719: } |
| 5454 | 3, 4, // 10723: case 0x3: { |
| 5455 | OPC_Decode, 243, 17, 64, // 10725: decode to XVSLE_DU using decoder 64 |
| 5456 | // 10725: } |
| 5457 | 4, 4, // 10729: case 0x4: { |
| 5458 | OPC_Decode, 142, 18, 64, // 10731: decode to XVSLT_B using decoder 64 |
| 5459 | // 10731: } |
| 5460 | 5, 4, // 10735: case 0x5: { |
| 5461 | OPC_Decode, 146, 18, 64, // 10737: decode to XVSLT_H using decoder 64 |
| 5462 | // 10737: } |
| 5463 | 6, 4, // 10741: case 0x6: { |
| 5464 | OPC_Decode, 148, 18, 64, // 10743: decode to XVSLT_W using decoder 64 |
| 5465 | // 10743: } |
| 5466 | 7, 0, // 10747: case 0x7: { |
| 5467 | OPC_Decode, 144, 18, 64, // 10749: decode to XVSLT_D using decoder 64 |
| 5468 | // 10749: } |
| 5469 | // 10749: } // switch Inst[17:15] |
| 5470 | // 10749: } |
| 5471 | 2, 51, // 10753: case 0x2: { |
| 5472 | OPC_SwitchField, 15, 3, // 10755: switch Inst[17:15] { |
| 5473 | 0, 4, // 10758: case 0x0: { |
| 5474 | OPC_Decode, 143, 18, 64, // 10760: decode to XVSLT_BU using decoder 64 |
| 5475 | // 10760: } |
| 5476 | 1, 4, // 10764: case 0x1: { |
| 5477 | OPC_Decode, 147, 18, 64, // 10766: decode to XVSLT_HU using decoder 64 |
| 5478 | // 10766: } |
| 5479 | 2, 4, // 10770: case 0x2: { |
| 5480 | OPC_Decode, 149, 18, 64, // 10772: decode to XVSLT_WU using decoder 64 |
| 5481 | // 10772: } |
| 5482 | 3, 4, // 10776: case 0x3: { |
| 5483 | OPC_Decode, 145, 18, 64, // 10778: decode to XVSLT_DU using decoder 64 |
| 5484 | // 10778: } |
| 5485 | 4, 4, // 10782: case 0x4: { |
| 5486 | OPC_Decode, 136, 14, 64, // 10784: decode to XVADD_B using decoder 64 |
| 5487 | // 10784: } |
| 5488 | 5, 4, // 10788: case 0x5: { |
| 5489 | OPC_Decode, 138, 14, 64, // 10790: decode to XVADD_H using decoder 64 |
| 5490 | // 10790: } |
| 5491 | 6, 4, // 10794: case 0x6: { |
| 5492 | OPC_Decode, 140, 14, 64, // 10796: decode to XVADD_W using decoder 64 |
| 5493 | // 10796: } |
| 5494 | 7, 0, // 10800: case 0x7: { |
| 5495 | OPC_Decode, 137, 14, 64, // 10802: decode to XVADD_D using decoder 64 |
| 5496 | // 10802: } |
| 5497 | // 10802: } // switch Inst[17:15] |
| 5498 | // 10802: } |
| 5499 | 3, 27, // 10806: case 0x3: { |
| 5500 | OPC_SwitchField, 15, 3, // 10808: switch Inst[17:15] { |
| 5501 | 0, 4, // 10811: case 0x0: { |
| 5502 | OPC_Decode, 172, 19, 64, // 10813: decode to XVSUB_B using decoder 64 |
| 5503 | // 10813: } |
| 5504 | 1, 4, // 10817: case 0x1: { |
| 5505 | OPC_Decode, 174, 19, 64, // 10819: decode to XVSUB_H using decoder 64 |
| 5506 | // 10819: } |
| 5507 | 2, 4, // 10823: case 0x2: { |
| 5508 | OPC_Decode, 176, 19, 64, // 10825: decode to XVSUB_W using decoder 64 |
| 5509 | // 10825: } |
| 5510 | 3, 0, // 10829: case 0x3: { |
| 5511 | OPC_Decode, 173, 19, 64, // 10831: decode to XVSUB_D using decoder 64 |
| 5512 | // 10831: } |
| 5513 | // 10831: } // switch Inst[17:15] |
| 5514 | // 10831: } |
| 5515 | 7, 27, // 10835: case 0x7: { |
| 5516 | OPC_SwitchField, 15, 3, // 10837: switch Inst[17:15] { |
| 5517 | 4, 4, // 10840: case 0x4: { |
| 5518 | OPC_Decode, 243, 13, 64, // 10842: decode to XVADDWEV_H_B using decoder 64 |
| 5519 | // 10842: } |
| 5520 | 5, 4, // 10846: case 0x5: { |
| 5521 | OPC_Decode, 249, 13, 64, // 10848: decode to XVADDWEV_W_H using decoder 64 |
| 5522 | // 10848: } |
| 5523 | 6, 4, // 10852: case 0x6: { |
| 5524 | OPC_Decode, 240, 13, 64, // 10854: decode to XVADDWEV_D_W using decoder 64 |
| 5525 | // 10854: } |
| 5526 | 7, 0, // 10858: case 0x7: { |
| 5527 | OPC_Decode, 246, 13, 64, // 10860: decode to XVADDWEV_Q_D using decoder 64 |
| 5528 | // 10860: } |
| 5529 | // 10860: } // switch Inst[17:15] |
| 5530 | // 10860: } |
| 5531 | 8, 51, // 10864: case 0x8: { |
| 5532 | OPC_SwitchField, 15, 3, // 10866: switch Inst[17:15] { |
| 5533 | 0, 4, // 10869: case 0x0: { |
| 5534 | OPC_Decode, 158, 19, 64, // 10871: decode to XVSUBWEV_H_B using decoder 64 |
| 5535 | // 10871: } |
| 5536 | 1, 4, // 10875: case 0x1: { |
| 5537 | OPC_Decode, 162, 19, 64, // 10877: decode to XVSUBWEV_W_H using decoder 64 |
| 5538 | // 10877: } |
| 5539 | 2, 4, // 10881: case 0x2: { |
| 5540 | OPC_Decode, 156, 19, 64, // 10883: decode to XVSUBWEV_D_W using decoder 64 |
| 5541 | // 10883: } |
| 5542 | 3, 4, // 10887: case 0x3: { |
| 5543 | OPC_Decode, 160, 19, 64, // 10889: decode to XVSUBWEV_Q_D using decoder 64 |
| 5544 | // 10889: } |
| 5545 | 4, 4, // 10893: case 0x4: { |
| 5546 | OPC_Decode, 255, 13, 64, // 10895: decode to XVADDWOD_H_B using decoder 64 |
| 5547 | // 10895: } |
| 5548 | 5, 4, // 10899: case 0x5: { |
| 5549 | OPC_Decode, 133, 14, 64, // 10901: decode to XVADDWOD_W_H using decoder 64 |
| 5550 | // 10901: } |
| 5551 | 6, 4, // 10905: case 0x6: { |
| 5552 | OPC_Decode, 252, 13, 64, // 10907: decode to XVADDWOD_D_W using decoder 64 |
| 5553 | // 10907: } |
| 5554 | 7, 0, // 10911: case 0x7: { |
| 5555 | OPC_Decode, 130, 14, 64, // 10913: decode to XVADDWOD_Q_D using decoder 64 |
| 5556 | // 10913: } |
| 5557 | // 10913: } // switch Inst[17:15] |
| 5558 | // 10913: } |
| 5559 | 9, 27, // 10917: case 0x9: { |
| 5560 | OPC_SwitchField, 15, 3, // 10919: switch Inst[17:15] { |
| 5561 | 0, 4, // 10922: case 0x0: { |
| 5562 | OPC_Decode, 166, 19, 64, // 10924: decode to XVSUBWOD_H_B using decoder 64 |
| 5563 | // 10924: } |
| 5564 | 1, 4, // 10928: case 0x1: { |
| 5565 | OPC_Decode, 170, 19, 64, // 10930: decode to XVSUBWOD_W_H using decoder 64 |
| 5566 | // 10930: } |
| 5567 | 2, 4, // 10934: case 0x2: { |
| 5568 | OPC_Decode, 164, 19, 64, // 10936: decode to XVSUBWOD_D_W using decoder 64 |
| 5569 | // 10936: } |
| 5570 | 3, 0, // 10940: case 0x3: { |
| 5571 | OPC_Decode, 168, 19, 64, // 10942: decode to XVSUBWOD_Q_D using decoder 64 |
| 5572 | // 10942: } |
| 5573 | // 10942: } // switch Inst[17:15] |
| 5574 | // 10942: } |
| 5575 | 11, 27, // 10946: case 0xb: { |
| 5576 | OPC_SwitchField, 15, 3, // 10948: switch Inst[17:15] { |
| 5577 | 4, 4, // 10951: case 0x4: { |
| 5578 | OPC_Decode, 244, 13, 64, // 10953: decode to XVADDWEV_H_BU using decoder 64 |
| 5579 | // 10953: } |
| 5580 | 5, 4, // 10957: case 0x5: { |
| 5581 | OPC_Decode, 250, 13, 64, // 10959: decode to XVADDWEV_W_HU using decoder 64 |
| 5582 | // 10959: } |
| 5583 | 6, 4, // 10963: case 0x6: { |
| 5584 | OPC_Decode, 241, 13, 64, // 10965: decode to XVADDWEV_D_WU using decoder 64 |
| 5585 | // 10965: } |
| 5586 | 7, 0, // 10969: case 0x7: { |
| 5587 | OPC_Decode, 247, 13, 64, // 10971: decode to XVADDWEV_Q_DU using decoder 64 |
| 5588 | // 10971: } |
| 5589 | // 10971: } // switch Inst[17:15] |
| 5590 | // 10971: } |
| 5591 | 12, 51, // 10975: case 0xc: { |
| 5592 | OPC_SwitchField, 15, 3, // 10977: switch Inst[17:15] { |
| 5593 | 0, 4, // 10980: case 0x0: { |
| 5594 | OPC_Decode, 159, 19, 64, // 10982: decode to XVSUBWEV_H_BU using decoder 64 |
| 5595 | // 10982: } |
| 5596 | 1, 4, // 10986: case 0x1: { |
| 5597 | OPC_Decode, 163, 19, 64, // 10988: decode to XVSUBWEV_W_HU using decoder 64 |
| 5598 | // 10988: } |
| 5599 | 2, 4, // 10992: case 0x2: { |
| 5600 | OPC_Decode, 157, 19, 64, // 10994: decode to XVSUBWEV_D_WU using decoder 64 |
| 5601 | // 10994: } |
| 5602 | 3, 4, // 10998: case 0x3: { |
| 5603 | OPC_Decode, 161, 19, 64, // 11000: decode to XVSUBWEV_Q_DU using decoder 64 |
| 5604 | // 11000: } |
| 5605 | 4, 4, // 11004: case 0x4: { |
| 5606 | OPC_Decode, 128, 14, 64, // 11006: decode to XVADDWOD_H_BU using decoder 64 |
| 5607 | // 11006: } |
| 5608 | 5, 4, // 11010: case 0x5: { |
| 5609 | OPC_Decode, 134, 14, 64, // 11012: decode to XVADDWOD_W_HU using decoder 64 |
| 5610 | // 11012: } |
| 5611 | 6, 4, // 11016: case 0x6: { |
| 5612 | OPC_Decode, 253, 13, 64, // 11018: decode to XVADDWOD_D_WU using decoder 64 |
| 5613 | // 11018: } |
| 5614 | 7, 0, // 11022: case 0x7: { |
| 5615 | OPC_Decode, 131, 14, 64, // 11024: decode to XVADDWOD_Q_DU using decoder 64 |
| 5616 | // 11024: } |
| 5617 | // 11024: } // switch Inst[17:15] |
| 5618 | // 11024: } |
| 5619 | 13, 27, // 11028: case 0xd: { |
| 5620 | OPC_SwitchField, 15, 3, // 11030: switch Inst[17:15] { |
| 5621 | 0, 4, // 11033: case 0x0: { |
| 5622 | OPC_Decode, 167, 19, 64, // 11035: decode to XVSUBWOD_H_BU using decoder 64 |
| 5623 | // 11035: } |
| 5624 | 1, 4, // 11039: case 0x1: { |
| 5625 | OPC_Decode, 171, 19, 64, // 11041: decode to XVSUBWOD_W_HU using decoder 64 |
| 5626 | // 11041: } |
| 5627 | 2, 4, // 11045: case 0x2: { |
| 5628 | OPC_Decode, 165, 19, 64, // 11047: decode to XVSUBWOD_D_WU using decoder 64 |
| 5629 | // 11047: } |
| 5630 | 3, 0, // 11051: case 0x3: { |
| 5631 | OPC_Decode, 169, 19, 64, // 11053: decode to XVSUBWOD_Q_DU using decoder 64 |
| 5632 | // 11053: } |
| 5633 | // 11053: } // switch Inst[17:15] |
| 5634 | // 11053: } |
| 5635 | 15, 27, // 11057: case 0xf: { |
| 5636 | OPC_SwitchField, 15, 3, // 11059: switch Inst[17:15] { |
| 5637 | 4, 4, // 11062: case 0x4: { |
| 5638 | OPC_Decode, 245, 13, 64, // 11064: decode to XVADDWEV_H_BU_B using decoder 64 |
| 5639 | // 11064: } |
| 5640 | 5, 4, // 11068: case 0x5: { |
| 5641 | OPC_Decode, 251, 13, 64, // 11070: decode to XVADDWEV_W_HU_H using decoder 64 |
| 5642 | // 11070: } |
| 5643 | 6, 4, // 11074: case 0x6: { |
| 5644 | OPC_Decode, 242, 13, 64, // 11076: decode to XVADDWEV_D_WU_W using decoder 64 |
| 5645 | // 11076: } |
| 5646 | 7, 0, // 11080: case 0x7: { |
| 5647 | OPC_Decode, 248, 13, 64, // 11082: decode to XVADDWEV_Q_DU_D using decoder 64 |
| 5648 | // 11082: } |
| 5649 | // 11082: } // switch Inst[17:15] |
| 5650 | // 11082: } |
| 5651 | 16, 27, // 11086: case 0x10: { |
| 5652 | OPC_SwitchField, 15, 3, // 11088: switch Inst[17:15] { |
| 5653 | 0, 4, // 11091: case 0x0: { |
| 5654 | OPC_Decode, 129, 14, 64, // 11093: decode to XVADDWOD_H_BU_B using decoder 64 |
| 5655 | // 11093: } |
| 5656 | 1, 4, // 11097: case 0x1: { |
| 5657 | OPC_Decode, 135, 14, 64, // 11099: decode to XVADDWOD_W_HU_H using decoder 64 |
| 5658 | // 11099: } |
| 5659 | 2, 4, // 11103: case 0x2: { |
| 5660 | OPC_Decode, 254, 13, 64, // 11105: decode to XVADDWOD_D_WU_W using decoder 64 |
| 5661 | // 11105: } |
| 5662 | 3, 0, // 11109: case 0x3: { |
| 5663 | OPC_Decode, 132, 14, 64, // 11111: decode to XVADDWOD_Q_DU_D using decoder 64 |
| 5664 | // 11111: } |
| 5665 | // 11111: } // switch Inst[17:15] |
| 5666 | // 11111: } |
| 5667 | 17, 27, // 11115: case 0x11: { |
| 5668 | OPC_SwitchField, 15, 3, // 11117: switch Inst[17:15] { |
| 5669 | 4, 4, // 11120: case 0x4: { |
| 5670 | OPC_Decode, 186, 17, 64, // 11122: decode to XVSADD_B using decoder 64 |
| 5671 | // 11122: } |
| 5672 | 5, 4, // 11126: case 0x5: { |
| 5673 | OPC_Decode, 190, 17, 64, // 11128: decode to XVSADD_H using decoder 64 |
| 5674 | // 11128: } |
| 5675 | 6, 4, // 11132: case 0x6: { |
| 5676 | OPC_Decode, 192, 17, 64, // 11134: decode to XVSADD_W using decoder 64 |
| 5677 | // 11134: } |
| 5678 | 7, 0, // 11138: case 0x7: { |
| 5679 | OPC_Decode, 188, 17, 64, // 11140: decode to XVSADD_D using decoder 64 |
| 5680 | // 11140: } |
| 5681 | // 11140: } // switch Inst[17:15] |
| 5682 | // 11140: } |
| 5683 | 18, 51, // 11144: case 0x12: { |
| 5684 | OPC_SwitchField, 15, 3, // 11146: switch Inst[17:15] { |
| 5685 | 0, 4, // 11149: case 0x0: { |
| 5686 | OPC_Decode, 138, 19, 64, // 11151: decode to XVSSUB_B using decoder 64 |
| 5687 | // 11151: } |
| 5688 | 1, 4, // 11155: case 0x1: { |
| 5689 | OPC_Decode, 142, 19, 64, // 11157: decode to XVSSUB_H using decoder 64 |
| 5690 | // 11157: } |
| 5691 | 2, 4, // 11161: case 0x2: { |
| 5692 | OPC_Decode, 144, 19, 64, // 11163: decode to XVSSUB_W using decoder 64 |
| 5693 | // 11163: } |
| 5694 | 3, 4, // 11167: case 0x3: { |
| 5695 | OPC_Decode, 140, 19, 64, // 11169: decode to XVSSUB_D using decoder 64 |
| 5696 | // 11169: } |
| 5697 | 4, 4, // 11173: case 0x4: { |
| 5698 | OPC_Decode, 187, 17, 64, // 11175: decode to XVSADD_BU using decoder 64 |
| 5699 | // 11175: } |
| 5700 | 5, 4, // 11179: case 0x5: { |
| 5701 | OPC_Decode, 191, 17, 64, // 11181: decode to XVSADD_HU using decoder 64 |
| 5702 | // 11181: } |
| 5703 | 6, 4, // 11185: case 0x6: { |
| 5704 | OPC_Decode, 193, 17, 64, // 11187: decode to XVSADD_WU using decoder 64 |
| 5705 | // 11187: } |
| 5706 | 7, 0, // 11191: case 0x7: { |
| 5707 | OPC_Decode, 189, 17, 64, // 11193: decode to XVSADD_DU using decoder 64 |
| 5708 | // 11193: } |
| 5709 | // 11193: } // switch Inst[17:15] |
| 5710 | // 11193: } |
| 5711 | 19, 27, // 11197: case 0x13: { |
| 5712 | OPC_SwitchField, 15, 3, // 11199: switch Inst[17:15] { |
| 5713 | 0, 4, // 11202: case 0x0: { |
| 5714 | OPC_Decode, 139, 19, 64, // 11204: decode to XVSSUB_BU using decoder 64 |
| 5715 | // 11204: } |
| 5716 | 1, 4, // 11208: case 0x1: { |
| 5717 | OPC_Decode, 143, 19, 64, // 11210: decode to XVSSUB_HU using decoder 64 |
| 5718 | // 11210: } |
| 5719 | 2, 4, // 11214: case 0x2: { |
| 5720 | OPC_Decode, 145, 19, 64, // 11216: decode to XVSSUB_WU using decoder 64 |
| 5721 | // 11216: } |
| 5722 | 3, 0, // 11220: case 0x3: { |
| 5723 | OPC_Decode, 141, 19, 64, // 11222: decode to XVSSUB_DU using decoder 64 |
| 5724 | // 11222: } |
| 5725 | // 11222: } // switch Inst[17:15] |
| 5726 | // 11222: } |
| 5727 | 21, 51, // 11226: case 0x15: { |
| 5728 | OPC_SwitchField, 15, 3, // 11228: switch Inst[17:15] { |
| 5729 | 0, 4, // 11231: case 0x0: { |
| 5730 | OPC_Decode, 231, 15, 64, // 11233: decode to XVHADDW_H_B using decoder 64 |
| 5731 | // 11233: } |
| 5732 | 1, 4, // 11237: case 0x1: { |
| 5733 | OPC_Decode, 235, 15, 64, // 11239: decode to XVHADDW_W_H using decoder 64 |
| 5734 | // 11239: } |
| 5735 | 2, 4, // 11243: case 0x2: { |
| 5736 | OPC_Decode, 229, 15, 64, // 11245: decode to XVHADDW_D_W using decoder 64 |
| 5737 | // 11245: } |
| 5738 | 3, 4, // 11249: case 0x3: { |
| 5739 | OPC_Decode, 233, 15, 64, // 11251: decode to XVHADDW_Q_D using decoder 64 |
| 5740 | // 11251: } |
| 5741 | 4, 4, // 11255: case 0x4: { |
| 5742 | OPC_Decode, 240, 15, 64, // 11257: decode to XVHSUBW_H_B using decoder 64 |
| 5743 | // 11257: } |
| 5744 | 5, 4, // 11261: case 0x5: { |
| 5745 | OPC_Decode, 244, 15, 64, // 11263: decode to XVHSUBW_W_H using decoder 64 |
| 5746 | // 11263: } |
| 5747 | 6, 4, // 11267: case 0x6: { |
| 5748 | OPC_Decode, 238, 15, 64, // 11269: decode to XVHSUBW_D_W using decoder 64 |
| 5749 | // 11269: } |
| 5750 | 7, 0, // 11273: case 0x7: { |
| 5751 | OPC_Decode, 242, 15, 64, // 11275: decode to XVHSUBW_Q_D using decoder 64 |
| 5752 | // 11275: } |
| 5753 | // 11275: } // switch Inst[17:15] |
| 5754 | // 11275: } |
| 5755 | 22, 51, // 11279: case 0x16: { |
| 5756 | OPC_SwitchField, 15, 3, // 11281: switch Inst[17:15] { |
| 5757 | 0, 4, // 11284: case 0x0: { |
| 5758 | OPC_Decode, 230, 15, 64, // 11286: decode to XVHADDW_HU_BU using decoder 64 |
| 5759 | // 11286: } |
| 5760 | 1, 4, // 11290: case 0x1: { |
| 5761 | OPC_Decode, 234, 15, 64, // 11292: decode to XVHADDW_WU_HU using decoder 64 |
| 5762 | // 11292: } |
| 5763 | 2, 4, // 11296: case 0x2: { |
| 5764 | OPC_Decode, 228, 15, 64, // 11298: decode to XVHADDW_DU_WU using decoder 64 |
| 5765 | // 11298: } |
| 5766 | 3, 4, // 11302: case 0x3: { |
| 5767 | OPC_Decode, 232, 15, 64, // 11304: decode to XVHADDW_QU_DU using decoder 64 |
| 5768 | // 11304: } |
| 5769 | 4, 4, // 11308: case 0x4: { |
| 5770 | OPC_Decode, 239, 15, 64, // 11310: decode to XVHSUBW_HU_BU using decoder 64 |
| 5771 | // 11310: } |
| 5772 | 5, 4, // 11314: case 0x5: { |
| 5773 | OPC_Decode, 243, 15, 64, // 11316: decode to XVHSUBW_WU_HU using decoder 64 |
| 5774 | // 11316: } |
| 5775 | 6, 4, // 11320: case 0x6: { |
| 5776 | OPC_Decode, 237, 15, 64, // 11322: decode to XVHSUBW_DU_WU using decoder 64 |
| 5777 | // 11322: } |
| 5778 | 7, 0, // 11326: case 0x7: { |
| 5779 | OPC_Decode, 241, 15, 64, // 11328: decode to XVHSUBW_QU_DU using decoder 64 |
| 5780 | // 11328: } |
| 5781 | // 11328: } // switch Inst[17:15] |
| 5782 | // 11328: } |
| 5783 | 23, 27, // 11332: case 0x17: { |
| 5784 | OPC_SwitchField, 15, 3, // 11334: switch Inst[17:15] { |
| 5785 | 0, 4, // 11337: case 0x0: { |
| 5786 | OPC_Decode, 232, 13, 64, // 11339: decode to XVADDA_B using decoder 64 |
| 5787 | // 11339: } |
| 5788 | 1, 4, // 11343: case 0x1: { |
| 5789 | OPC_Decode, 234, 13, 64, // 11345: decode to XVADDA_H using decoder 64 |
| 5790 | // 11345: } |
| 5791 | 2, 4, // 11349: case 0x2: { |
| 5792 | OPC_Decode, 235, 13, 64, // 11351: decode to XVADDA_W using decoder 64 |
| 5793 | // 11351: } |
| 5794 | 3, 0, // 11355: case 0x3: { |
| 5795 | OPC_Decode, 233, 13, 64, // 11357: decode to XVADDA_D using decoder 64 |
| 5796 | // 11357: } |
| 5797 | // 11357: } // switch Inst[17:15] |
| 5798 | // 11357: } |
| 5799 | 24, 51, // 11361: case 0x18: { |
| 5800 | OPC_SwitchField, 15, 3, // 11363: switch Inst[17:15] { |
| 5801 | 0, 4, // 11366: case 0x0: { |
| 5802 | OPC_Decode, 224, 13, 64, // 11368: decode to XVABSD_B using decoder 64 |
| 5803 | // 11368: } |
| 5804 | 1, 4, // 11372: case 0x1: { |
| 5805 | OPC_Decode, 228, 13, 64, // 11374: decode to XVABSD_H using decoder 64 |
| 5806 | // 11374: } |
| 5807 | 2, 4, // 11378: case 0x2: { |
| 5808 | OPC_Decode, 230, 13, 64, // 11380: decode to XVABSD_W using decoder 64 |
| 5809 | // 11380: } |
| 5810 | 3, 4, // 11384: case 0x3: { |
| 5811 | OPC_Decode, 226, 13, 64, // 11386: decode to XVABSD_D using decoder 64 |
| 5812 | // 11386: } |
| 5813 | 4, 4, // 11390: case 0x4: { |
| 5814 | OPC_Decode, 225, 13, 64, // 11392: decode to XVABSD_BU using decoder 64 |
| 5815 | // 11392: } |
| 5816 | 5, 4, // 11396: case 0x5: { |
| 5817 | OPC_Decode, 229, 13, 64, // 11398: decode to XVABSD_HU using decoder 64 |
| 5818 | // 11398: } |
| 5819 | 6, 4, // 11402: case 0x6: { |
| 5820 | OPC_Decode, 231, 13, 64, // 11404: decode to XVABSD_WU using decoder 64 |
| 5821 | // 11404: } |
| 5822 | 7, 0, // 11408: case 0x7: { |
| 5823 | OPC_Decode, 227, 13, 64, // 11410: decode to XVABSD_DU using decoder 64 |
| 5824 | // 11410: } |
| 5825 | // 11410: } // switch Inst[17:15] |
| 5826 | // 11410: } |
| 5827 | 25, 51, // 11414: case 0x19: { |
| 5828 | OPC_SwitchField, 15, 3, // 11416: switch Inst[17:15] { |
| 5829 | 0, 4, // 11419: case 0x0: { |
| 5830 | OPC_Decode, 152, 14, 64, // 11421: decode to XVAVG_B using decoder 64 |
| 5831 | // 11421: } |
| 5832 | 1, 4, // 11425: case 0x1: { |
| 5833 | OPC_Decode, 156, 14, 64, // 11427: decode to XVAVG_H using decoder 64 |
| 5834 | // 11427: } |
| 5835 | 2, 4, // 11431: case 0x2: { |
| 5836 | OPC_Decode, 158, 14, 64, // 11433: decode to XVAVG_W using decoder 64 |
| 5837 | // 11433: } |
| 5838 | 3, 4, // 11437: case 0x3: { |
| 5839 | OPC_Decode, 154, 14, 64, // 11439: decode to XVAVG_D using decoder 64 |
| 5840 | // 11439: } |
| 5841 | 4, 4, // 11443: case 0x4: { |
| 5842 | OPC_Decode, 153, 14, 64, // 11445: decode to XVAVG_BU using decoder 64 |
| 5843 | // 11445: } |
| 5844 | 5, 4, // 11449: case 0x5: { |
| 5845 | OPC_Decode, 157, 14, 64, // 11451: decode to XVAVG_HU using decoder 64 |
| 5846 | // 11451: } |
| 5847 | 6, 4, // 11455: case 0x6: { |
| 5848 | OPC_Decode, 159, 14, 64, // 11457: decode to XVAVG_WU using decoder 64 |
| 5849 | // 11457: } |
| 5850 | 7, 0, // 11461: case 0x7: { |
| 5851 | OPC_Decode, 155, 14, 64, // 11463: decode to XVAVG_DU using decoder 64 |
| 5852 | // 11463: } |
| 5853 | // 11463: } // switch Inst[17:15] |
| 5854 | // 11463: } |
| 5855 | 26, 51, // 11467: case 0x1a: { |
| 5856 | OPC_SwitchField, 15, 3, // 11469: switch Inst[17:15] { |
| 5857 | 0, 4, // 11472: case 0x0: { |
| 5858 | OPC_Decode, 144, 14, 64, // 11474: decode to XVAVGR_B using decoder 64 |
| 5859 | // 11474: } |
| 5860 | 1, 4, // 11478: case 0x1: { |
| 5861 | OPC_Decode, 148, 14, 64, // 11480: decode to XVAVGR_H using decoder 64 |
| 5862 | // 11480: } |
| 5863 | 2, 4, // 11484: case 0x2: { |
| 5864 | OPC_Decode, 150, 14, 64, // 11486: decode to XVAVGR_W using decoder 64 |
| 5865 | // 11486: } |
| 5866 | 3, 4, // 11490: case 0x3: { |
| 5867 | OPC_Decode, 146, 14, 64, // 11492: decode to XVAVGR_D using decoder 64 |
| 5868 | // 11492: } |
| 5869 | 4, 4, // 11496: case 0x4: { |
| 5870 | OPC_Decode, 145, 14, 64, // 11498: decode to XVAVGR_BU using decoder 64 |
| 5871 | // 11498: } |
| 5872 | 5, 4, // 11502: case 0x5: { |
| 5873 | OPC_Decode, 149, 14, 64, // 11504: decode to XVAVGR_HU using decoder 64 |
| 5874 | // 11504: } |
| 5875 | 6, 4, // 11508: case 0x6: { |
| 5876 | OPC_Decode, 151, 14, 64, // 11510: decode to XVAVGR_WU using decoder 64 |
| 5877 | // 11510: } |
| 5878 | 7, 0, // 11514: case 0x7: { |
| 5879 | OPC_Decode, 147, 14, 64, // 11516: decode to XVAVGR_DU using decoder 64 |
| 5880 | // 11516: } |
| 5881 | // 11516: } // switch Inst[17:15] |
| 5882 | // 11516: } |
| 5883 | 28, 51, // 11520: case 0x1c: { |
| 5884 | OPC_SwitchField, 15, 3, // 11522: switch Inst[17:15] { |
| 5885 | 0, 4, // 11525: case 0x0: { |
| 5886 | OPC_Decode, 172, 16, 64, // 11527: decode to XVMAX_B using decoder 64 |
| 5887 | // 11527: } |
| 5888 | 1, 4, // 11531: case 0x1: { |
| 5889 | OPC_Decode, 176, 16, 64, // 11533: decode to XVMAX_H using decoder 64 |
| 5890 | // 11533: } |
| 5891 | 2, 4, // 11537: case 0x2: { |
| 5892 | OPC_Decode, 178, 16, 64, // 11539: decode to XVMAX_W using decoder 64 |
| 5893 | // 11539: } |
| 5894 | 3, 4, // 11543: case 0x3: { |
| 5895 | OPC_Decode, 174, 16, 64, // 11545: decode to XVMAX_D using decoder 64 |
| 5896 | // 11545: } |
| 5897 | 4, 4, // 11549: case 0x4: { |
| 5898 | OPC_Decode, 188, 16, 64, // 11551: decode to XVMIN_B using decoder 64 |
| 5899 | // 11551: } |
| 5900 | 5, 4, // 11555: case 0x5: { |
| 5901 | OPC_Decode, 192, 16, 64, // 11557: decode to XVMIN_H using decoder 64 |
| 5902 | // 11557: } |
| 5903 | 6, 4, // 11561: case 0x6: { |
| 5904 | OPC_Decode, 194, 16, 64, // 11563: decode to XVMIN_W using decoder 64 |
| 5905 | // 11563: } |
| 5906 | 7, 0, // 11567: case 0x7: { |
| 5907 | OPC_Decode, 190, 16, 64, // 11569: decode to XVMIN_D using decoder 64 |
| 5908 | // 11569: } |
| 5909 | // 11569: } // switch Inst[17:15] |
| 5910 | // 11569: } |
| 5911 | 29, 51, // 11573: case 0x1d: { |
| 5912 | OPC_SwitchField, 15, 3, // 11575: switch Inst[17:15] { |
| 5913 | 0, 4, // 11578: case 0x0: { |
| 5914 | OPC_Decode, 173, 16, 64, // 11580: decode to XVMAX_BU using decoder 64 |
| 5915 | // 11580: } |
| 5916 | 1, 4, // 11584: case 0x1: { |
| 5917 | OPC_Decode, 177, 16, 64, // 11586: decode to XVMAX_HU using decoder 64 |
| 5918 | // 11586: } |
| 5919 | 2, 4, // 11590: case 0x2: { |
| 5920 | OPC_Decode, 179, 16, 64, // 11592: decode to XVMAX_WU using decoder 64 |
| 5921 | // 11592: } |
| 5922 | 3, 4, // 11596: case 0x3: { |
| 5923 | OPC_Decode, 175, 16, 64, // 11598: decode to XVMAX_DU using decoder 64 |
| 5924 | // 11598: } |
| 5925 | 4, 4, // 11602: case 0x4: { |
| 5926 | OPC_Decode, 189, 16, 64, // 11604: decode to XVMIN_BU using decoder 64 |
| 5927 | // 11604: } |
| 5928 | 5, 4, // 11608: case 0x5: { |
| 5929 | OPC_Decode, 193, 16, 64, // 11610: decode to XVMIN_HU using decoder 64 |
| 5930 | // 11610: } |
| 5931 | 6, 4, // 11614: case 0x6: { |
| 5932 | OPC_Decode, 195, 16, 64, // 11616: decode to XVMIN_WU using decoder 64 |
| 5933 | // 11616: } |
| 5934 | 7, 0, // 11620: case 0x7: { |
| 5935 | OPC_Decode, 191, 16, 64, // 11622: decode to XVMIN_DU using decoder 64 |
| 5936 | // 11622: } |
| 5937 | // 11622: } // switch Inst[17:15] |
| 5938 | // 11622: } |
| 5939 | 33, 51, // 11626: case 0x21: { |
| 5940 | OPC_SwitchField, 15, 3, // 11628: switch Inst[17:15] { |
| 5941 | 0, 4, // 11631: case 0x0: { |
| 5942 | OPC_Decode, 246, 16, 64, // 11633: decode to XVMUL_B using decoder 64 |
| 5943 | // 11633: } |
| 5944 | 1, 4, // 11637: case 0x1: { |
| 5945 | OPC_Decode, 248, 16, 64, // 11639: decode to XVMUL_H using decoder 64 |
| 5946 | // 11639: } |
| 5947 | 2, 4, // 11643: case 0x2: { |
| 5948 | OPC_Decode, 249, 16, 64, // 11645: decode to XVMUL_W using decoder 64 |
| 5949 | // 11645: } |
| 5950 | 3, 4, // 11649: case 0x3: { |
| 5951 | OPC_Decode, 247, 16, 64, // 11651: decode to XVMUL_D using decoder 64 |
| 5952 | // 11651: } |
| 5953 | 4, 4, // 11655: case 0x4: { |
| 5954 | OPC_Decode, 214, 16, 64, // 11657: decode to XVMUH_B using decoder 64 |
| 5955 | // 11657: } |
| 5956 | 5, 4, // 11661: case 0x5: { |
| 5957 | OPC_Decode, 218, 16, 64, // 11663: decode to XVMUH_H using decoder 64 |
| 5958 | // 11663: } |
| 5959 | 6, 4, // 11667: case 0x6: { |
| 5960 | OPC_Decode, 220, 16, 64, // 11669: decode to XVMUH_W using decoder 64 |
| 5961 | // 11669: } |
| 5962 | 7, 0, // 11673: case 0x7: { |
| 5963 | OPC_Decode, 216, 16, 64, // 11675: decode to XVMUH_D using decoder 64 |
| 5964 | // 11675: } |
| 5965 | // 11675: } // switch Inst[17:15] |
| 5966 | // 11675: } |
| 5967 | 34, 27, // 11679: case 0x22: { |
| 5968 | OPC_SwitchField, 15, 3, // 11681: switch Inst[17:15] { |
| 5969 | 0, 4, // 11684: case 0x0: { |
| 5970 | OPC_Decode, 215, 16, 64, // 11686: decode to XVMUH_BU using decoder 64 |
| 5971 | // 11686: } |
| 5972 | 1, 4, // 11690: case 0x1: { |
| 5973 | OPC_Decode, 219, 16, 64, // 11692: decode to XVMUH_HU using decoder 64 |
| 5974 | // 11692: } |
| 5975 | 2, 4, // 11696: case 0x2: { |
| 5976 | OPC_Decode, 221, 16, 64, // 11698: decode to XVMUH_WU using decoder 64 |
| 5977 | // 11698: } |
| 5978 | 3, 0, // 11702: case 0x3: { |
| 5979 | OPC_Decode, 217, 16, 64, // 11704: decode to XVMUH_DU using decoder 64 |
| 5980 | // 11704: } |
| 5981 | // 11704: } // switch Inst[17:15] |
| 5982 | // 11704: } |
| 5983 | 36, 51, // 11708: case 0x24: { |
| 5984 | OPC_SwitchField, 15, 3, // 11710: switch Inst[17:15] { |
| 5985 | 0, 4, // 11713: case 0x0: { |
| 5986 | OPC_Decode, 225, 16, 64, // 11715: decode to XVMULWEV_H_B using decoder 64 |
| 5987 | // 11715: } |
| 5988 | 1, 4, // 11719: case 0x1: { |
| 5989 | OPC_Decode, 231, 16, 64, // 11721: decode to XVMULWEV_W_H using decoder 64 |
| 5990 | // 11721: } |
| 5991 | 2, 4, // 11725: case 0x2: { |
| 5992 | OPC_Decode, 222, 16, 64, // 11727: decode to XVMULWEV_D_W using decoder 64 |
| 5993 | // 11727: } |
| 5994 | 3, 4, // 11731: case 0x3: { |
| 5995 | OPC_Decode, 228, 16, 64, // 11733: decode to XVMULWEV_Q_D using decoder 64 |
| 5996 | // 11733: } |
| 5997 | 4, 4, // 11737: case 0x4: { |
| 5998 | OPC_Decode, 237, 16, 64, // 11739: decode to XVMULWOD_H_B using decoder 64 |
| 5999 | // 11739: } |
| 6000 | 5, 4, // 11743: case 0x5: { |
| 6001 | OPC_Decode, 243, 16, 64, // 11745: decode to XVMULWOD_W_H using decoder 64 |
| 6002 | // 11745: } |
| 6003 | 6, 4, // 11749: case 0x6: { |
| 6004 | OPC_Decode, 234, 16, 64, // 11751: decode to XVMULWOD_D_W using decoder 64 |
| 6005 | // 11751: } |
| 6006 | 7, 0, // 11755: case 0x7: { |
| 6007 | OPC_Decode, 240, 16, 64, // 11757: decode to XVMULWOD_Q_D using decoder 64 |
| 6008 | // 11757: } |
| 6009 | // 11757: } // switch Inst[17:15] |
| 6010 | // 11757: } |
| 6011 | 38, 51, // 11761: case 0x26: { |
| 6012 | OPC_SwitchField, 15, 3, // 11763: switch Inst[17:15] { |
| 6013 | 0, 4, // 11766: case 0x0: { |
| 6014 | OPC_Decode, 226, 16, 64, // 11768: decode to XVMULWEV_H_BU using decoder 64 |
| 6015 | // 11768: } |
| 6016 | 1, 4, // 11772: case 0x1: { |
| 6017 | OPC_Decode, 232, 16, 64, // 11774: decode to XVMULWEV_W_HU using decoder 64 |
| 6018 | // 11774: } |
| 6019 | 2, 4, // 11778: case 0x2: { |
| 6020 | OPC_Decode, 223, 16, 64, // 11780: decode to XVMULWEV_D_WU using decoder 64 |
| 6021 | // 11780: } |
| 6022 | 3, 4, // 11784: case 0x3: { |
| 6023 | OPC_Decode, 229, 16, 64, // 11786: decode to XVMULWEV_Q_DU using decoder 64 |
| 6024 | // 11786: } |
| 6025 | 4, 4, // 11790: case 0x4: { |
| 6026 | OPC_Decode, 238, 16, 64, // 11792: decode to XVMULWOD_H_BU using decoder 64 |
| 6027 | // 11792: } |
| 6028 | 5, 4, // 11796: case 0x5: { |
| 6029 | OPC_Decode, 244, 16, 64, // 11798: decode to XVMULWOD_W_HU using decoder 64 |
| 6030 | // 11798: } |
| 6031 | 6, 4, // 11802: case 0x6: { |
| 6032 | OPC_Decode, 235, 16, 64, // 11804: decode to XVMULWOD_D_WU using decoder 64 |
| 6033 | // 11804: } |
| 6034 | 7, 0, // 11808: case 0x7: { |
| 6035 | OPC_Decode, 241, 16, 64, // 11810: decode to XVMULWOD_Q_DU using decoder 64 |
| 6036 | // 11810: } |
| 6037 | // 11810: } // switch Inst[17:15] |
| 6038 | // 11810: } |
| 6039 | 40, 51, // 11814: case 0x28: { |
| 6040 | OPC_SwitchField, 15, 3, // 11816: switch Inst[17:15] { |
| 6041 | 0, 4, // 11819: case 0x0: { |
| 6042 | OPC_Decode, 227, 16, 64, // 11821: decode to XVMULWEV_H_BU_B using decoder 64 |
| 6043 | // 11821: } |
| 6044 | 1, 4, // 11825: case 0x1: { |
| 6045 | OPC_Decode, 233, 16, 64, // 11827: decode to XVMULWEV_W_HU_H using decoder 64 |
| 6046 | // 11827: } |
| 6047 | 2, 4, // 11831: case 0x2: { |
| 6048 | OPC_Decode, 224, 16, 64, // 11833: decode to XVMULWEV_D_WU_W using decoder 64 |
| 6049 | // 11833: } |
| 6050 | 3, 4, // 11837: case 0x3: { |
| 6051 | OPC_Decode, 230, 16, 64, // 11839: decode to XVMULWEV_Q_DU_D using decoder 64 |
| 6052 | // 11839: } |
| 6053 | 4, 4, // 11843: case 0x4: { |
| 6054 | OPC_Decode, 239, 16, 64, // 11845: decode to XVMULWOD_H_BU_B using decoder 64 |
| 6055 | // 11845: } |
| 6056 | 5, 4, // 11849: case 0x5: { |
| 6057 | OPC_Decode, 245, 16, 64, // 11851: decode to XVMULWOD_W_HU_H using decoder 64 |
| 6058 | // 11851: } |
| 6059 | 6, 4, // 11855: case 0x6: { |
| 6060 | OPC_Decode, 236, 16, 64, // 11857: decode to XVMULWOD_D_WU_W using decoder 64 |
| 6061 | // 11857: } |
| 6062 | 7, 0, // 11861: case 0x7: { |
| 6063 | OPC_Decode, 242, 16, 64, // 11863: decode to XVMULWOD_Q_DU_D using decoder 64 |
| 6064 | // 11863: } |
| 6065 | // 11863: } // switch Inst[17:15] |
| 6066 | // 11863: } |
| 6067 | 42, 59, // 11867: case 0x2a: { |
| 6068 | OPC_SwitchField, 15, 3, // 11869: switch Inst[17:15] { |
| 6069 | 0, 5, // 11872: case 0x0: { |
| 6070 | OPC_Decode, 160, 16, 131, 1, // 11874: decode to XVMADD_B using decoder 131 |
| 6071 | // 11874: } |
| 6072 | 1, 5, // 11879: case 0x1: { |
| 6073 | OPC_Decode, 162, 16, 131, 1, // 11881: decode to XVMADD_H using decoder 131 |
| 6074 | // 11881: } |
| 6075 | 2, 5, // 11886: case 0x2: { |
| 6076 | OPC_Decode, 163, 16, 131, 1, // 11888: decode to XVMADD_W using decoder 131 |
| 6077 | // 11888: } |
| 6078 | 3, 5, // 11893: case 0x3: { |
| 6079 | OPC_Decode, 161, 16, 131, 1, // 11895: decode to XVMADD_D using decoder 131 |
| 6080 | // 11895: } |
| 6081 | 4, 5, // 11900: case 0x4: { |
| 6082 | OPC_Decode, 210, 16, 131, 1, // 11902: decode to XVMSUB_B using decoder 131 |
| 6083 | // 11902: } |
| 6084 | 5, 5, // 11907: case 0x5: { |
| 6085 | OPC_Decode, 212, 16, 131, 1, // 11909: decode to XVMSUB_H using decoder 131 |
| 6086 | // 11909: } |
| 6087 | 6, 5, // 11914: case 0x6: { |
| 6088 | OPC_Decode, 213, 16, 131, 1, // 11916: decode to XVMSUB_W using decoder 131 |
| 6089 | // 11916: } |
| 6090 | 7, 0, // 11921: case 0x7: { |
| 6091 | OPC_Decode, 211, 16, 131, 1, // 11923: decode to XVMSUB_D using decoder 131 |
| 6092 | // 11923: } |
| 6093 | // 11923: } // switch Inst[17:15] |
| 6094 | // 11923: } |
| 6095 | 43, 59, // 11928: case 0x2b: { |
| 6096 | OPC_SwitchField, 15, 3, // 11930: switch Inst[17:15] { |
| 6097 | 0, 5, // 11933: case 0x0: { |
| 6098 | OPC_Decode, 139, 16, 131, 1, // 11935: decode to XVMADDWEV_H_B using decoder 131 |
| 6099 | // 11935: } |
| 6100 | 1, 5, // 11940: case 0x1: { |
| 6101 | OPC_Decode, 145, 16, 131, 1, // 11942: decode to XVMADDWEV_W_H using decoder 131 |
| 6102 | // 11942: } |
| 6103 | 2, 5, // 11947: case 0x2: { |
| 6104 | OPC_Decode, 136, 16, 131, 1, // 11949: decode to XVMADDWEV_D_W using decoder 131 |
| 6105 | // 11949: } |
| 6106 | 3, 5, // 11954: case 0x3: { |
| 6107 | OPC_Decode, 142, 16, 131, 1, // 11956: decode to XVMADDWEV_Q_D using decoder 131 |
| 6108 | // 11956: } |
| 6109 | 4, 5, // 11961: case 0x4: { |
| 6110 | OPC_Decode, 151, 16, 131, 1, // 11963: decode to XVMADDWOD_H_B using decoder 131 |
| 6111 | // 11963: } |
| 6112 | 5, 5, // 11968: case 0x5: { |
| 6113 | OPC_Decode, 157, 16, 131, 1, // 11970: decode to XVMADDWOD_W_H using decoder 131 |
| 6114 | // 11970: } |
| 6115 | 6, 5, // 11975: case 0x6: { |
| 6116 | OPC_Decode, 148, 16, 131, 1, // 11977: decode to XVMADDWOD_D_W using decoder 131 |
| 6117 | // 11977: } |
| 6118 | 7, 0, // 11982: case 0x7: { |
| 6119 | OPC_Decode, 154, 16, 131, 1, // 11984: decode to XVMADDWOD_Q_D using decoder 131 |
| 6120 | // 11984: } |
| 6121 | // 11984: } // switch Inst[17:15] |
| 6122 | // 11984: } |
| 6123 | 45, 59, // 11989: case 0x2d: { |
| 6124 | OPC_SwitchField, 15, 3, // 11991: switch Inst[17:15] { |
| 6125 | 0, 5, // 11994: case 0x0: { |
| 6126 | OPC_Decode, 140, 16, 131, 1, // 11996: decode to XVMADDWEV_H_BU using decoder 131 |
| 6127 | // 11996: } |
| 6128 | 1, 5, // 12001: case 0x1: { |
| 6129 | OPC_Decode, 146, 16, 131, 1, // 12003: decode to XVMADDWEV_W_HU using decoder 131 |
| 6130 | // 12003: } |
| 6131 | 2, 5, // 12008: case 0x2: { |
| 6132 | OPC_Decode, 137, 16, 131, 1, // 12010: decode to XVMADDWEV_D_WU using decoder 131 |
| 6133 | // 12010: } |
| 6134 | 3, 5, // 12015: case 0x3: { |
| 6135 | OPC_Decode, 143, 16, 131, 1, // 12017: decode to XVMADDWEV_Q_DU using decoder 131 |
| 6136 | // 12017: } |
| 6137 | 4, 5, // 12022: case 0x4: { |
| 6138 | OPC_Decode, 152, 16, 131, 1, // 12024: decode to XVMADDWOD_H_BU using decoder 131 |
| 6139 | // 12024: } |
| 6140 | 5, 5, // 12029: case 0x5: { |
| 6141 | OPC_Decode, 158, 16, 131, 1, // 12031: decode to XVMADDWOD_W_HU using decoder 131 |
| 6142 | // 12031: } |
| 6143 | 6, 5, // 12036: case 0x6: { |
| 6144 | OPC_Decode, 149, 16, 131, 1, // 12038: decode to XVMADDWOD_D_WU using decoder 131 |
| 6145 | // 12038: } |
| 6146 | 7, 0, // 12043: case 0x7: { |
| 6147 | OPC_Decode, 155, 16, 131, 1, // 12045: decode to XVMADDWOD_Q_DU using decoder 131 |
| 6148 | // 12045: } |
| 6149 | // 12045: } // switch Inst[17:15] |
| 6150 | // 12045: } |
| 6151 | 47, 59, // 12050: case 0x2f: { |
| 6152 | OPC_SwitchField, 15, 3, // 12052: switch Inst[17:15] { |
| 6153 | 0, 5, // 12055: case 0x0: { |
| 6154 | OPC_Decode, 141, 16, 131, 1, // 12057: decode to XVMADDWEV_H_BU_B using decoder 131 |
| 6155 | // 12057: } |
| 6156 | 1, 5, // 12062: case 0x1: { |
| 6157 | OPC_Decode, 147, 16, 131, 1, // 12064: decode to XVMADDWEV_W_HU_H using decoder 131 |
| 6158 | // 12064: } |
| 6159 | 2, 5, // 12069: case 0x2: { |
| 6160 | OPC_Decode, 138, 16, 131, 1, // 12071: decode to XVMADDWEV_D_WU_W using decoder 131 |
| 6161 | // 12071: } |
| 6162 | 3, 5, // 12076: case 0x3: { |
| 6163 | OPC_Decode, 144, 16, 131, 1, // 12078: decode to XVMADDWEV_Q_DU_D using decoder 131 |
| 6164 | // 12078: } |
| 6165 | 4, 5, // 12083: case 0x4: { |
| 6166 | OPC_Decode, 153, 16, 131, 1, // 12085: decode to XVMADDWOD_H_BU_B using decoder 131 |
| 6167 | // 12085: } |
| 6168 | 5, 5, // 12090: case 0x5: { |
| 6169 | OPC_Decode, 159, 16, 131, 1, // 12092: decode to XVMADDWOD_W_HU_H using decoder 131 |
| 6170 | // 12092: } |
| 6171 | 6, 5, // 12097: case 0x6: { |
| 6172 | OPC_Decode, 150, 16, 131, 1, // 12099: decode to XVMADDWOD_D_WU_W using decoder 131 |
| 6173 | // 12099: } |
| 6174 | 7, 0, // 12104: case 0x7: { |
| 6175 | OPC_Decode, 156, 16, 131, 1, // 12106: decode to XVMADDWOD_Q_DU_D using decoder 131 |
| 6176 | // 12106: } |
| 6177 | // 12106: } // switch Inst[17:15] |
| 6178 | // 12106: } |
| 6179 | 56, 51, // 12111: case 0x38: { |
| 6180 | OPC_SwitchField, 15, 3, // 12113: switch Inst[17:15] { |
| 6181 | 0, 4, // 12116: case 0x0: { |
| 6182 | OPC_Decode, 196, 14, 64, // 12118: decode to XVDIV_B using decoder 64 |
| 6183 | // 12118: } |
| 6184 | 1, 4, // 12122: case 0x1: { |
| 6185 | OPC_Decode, 200, 14, 64, // 12124: decode to XVDIV_H using decoder 64 |
| 6186 | // 12124: } |
| 6187 | 2, 4, // 12128: case 0x2: { |
| 6188 | OPC_Decode, 202, 14, 64, // 12130: decode to XVDIV_W using decoder 64 |
| 6189 | // 12130: } |
| 6190 | 3, 4, // 12134: case 0x3: { |
| 6191 | OPC_Decode, 198, 14, 64, // 12136: decode to XVDIV_D using decoder 64 |
| 6192 | // 12136: } |
| 6193 | 4, 4, // 12140: case 0x4: { |
| 6194 | OPC_Decode, 196, 16, 64, // 12142: decode to XVMOD_B using decoder 64 |
| 6195 | // 12142: } |
| 6196 | 5, 4, // 12146: case 0x5: { |
| 6197 | OPC_Decode, 200, 16, 64, // 12148: decode to XVMOD_H using decoder 64 |
| 6198 | // 12148: } |
| 6199 | 6, 4, // 12152: case 0x6: { |
| 6200 | OPC_Decode, 202, 16, 64, // 12154: decode to XVMOD_W using decoder 64 |
| 6201 | // 12154: } |
| 6202 | 7, 0, // 12158: case 0x7: { |
| 6203 | OPC_Decode, 198, 16, 64, // 12160: decode to XVMOD_D using decoder 64 |
| 6204 | // 12160: } |
| 6205 | // 12160: } // switch Inst[17:15] |
| 6206 | // 12160: } |
| 6207 | 57, 51, // 12164: case 0x39: { |
| 6208 | OPC_SwitchField, 15, 3, // 12166: switch Inst[17:15] { |
| 6209 | 0, 4, // 12169: case 0x0: { |
| 6210 | OPC_Decode, 197, 14, 64, // 12171: decode to XVDIV_BU using decoder 64 |
| 6211 | // 12171: } |
| 6212 | 1, 4, // 12175: case 0x1: { |
| 6213 | OPC_Decode, 201, 14, 64, // 12177: decode to XVDIV_HU using decoder 64 |
| 6214 | // 12177: } |
| 6215 | 2, 4, // 12181: case 0x2: { |
| 6216 | OPC_Decode, 203, 14, 64, // 12183: decode to XVDIV_WU using decoder 64 |
| 6217 | // 12183: } |
| 6218 | 3, 4, // 12187: case 0x3: { |
| 6219 | OPC_Decode, 199, 14, 64, // 12189: decode to XVDIV_DU using decoder 64 |
| 6220 | // 12189: } |
| 6221 | 4, 4, // 12193: case 0x4: { |
| 6222 | OPC_Decode, 197, 16, 64, // 12195: decode to XVMOD_BU using decoder 64 |
| 6223 | // 12195: } |
| 6224 | 5, 4, // 12199: case 0x5: { |
| 6225 | OPC_Decode, 201, 16, 64, // 12201: decode to XVMOD_HU using decoder 64 |
| 6226 | // 12201: } |
| 6227 | 6, 4, // 12205: case 0x6: { |
| 6228 | OPC_Decode, 203, 16, 64, // 12207: decode to XVMOD_WU using decoder 64 |
| 6229 | // 12207: } |
| 6230 | 7, 0, // 12211: case 0x7: { |
| 6231 | OPC_Decode, 199, 16, 64, // 12213: decode to XVMOD_DU using decoder 64 |
| 6232 | // 12213: } |
| 6233 | // 12213: } // switch Inst[17:15] |
| 6234 | // 12213: } |
| 6235 | 58, 51, // 12217: case 0x3a: { |
| 6236 | OPC_SwitchField, 15, 3, // 12219: switch Inst[17:15] { |
| 6237 | 0, 4, // 12222: case 0x0: { |
| 6238 | OPC_Decode, 130, 18, 64, // 12224: decode to XVSLL_B using decoder 64 |
| 6239 | // 12224: } |
| 6240 | 1, 4, // 12228: case 0x1: { |
| 6241 | OPC_Decode, 132, 18, 64, // 12230: decode to XVSLL_H using decoder 64 |
| 6242 | // 12230: } |
| 6243 | 2, 4, // 12234: case 0x2: { |
| 6244 | OPC_Decode, 133, 18, 64, // 12236: decode to XVSLL_W using decoder 64 |
| 6245 | // 12236: } |
| 6246 | 3, 4, // 12240: case 0x3: { |
| 6247 | OPC_Decode, 131, 18, 64, // 12242: decode to XVSLL_D using decoder 64 |
| 6248 | // 12242: } |
| 6249 | 4, 4, // 12246: case 0x4: { |
| 6250 | OPC_Decode, 206, 18, 64, // 12248: decode to XVSRL_B using decoder 64 |
| 6251 | // 12248: } |
| 6252 | 5, 4, // 12252: case 0x5: { |
| 6253 | OPC_Decode, 208, 18, 64, // 12254: decode to XVSRL_H using decoder 64 |
| 6254 | // 12254: } |
| 6255 | 6, 4, // 12258: case 0x6: { |
| 6256 | OPC_Decode, 209, 18, 64, // 12260: decode to XVSRL_W using decoder 64 |
| 6257 | // 12260: } |
| 6258 | 7, 0, // 12264: case 0x7: { |
| 6259 | OPC_Decode, 207, 18, 64, // 12266: decode to XVSRL_D using decoder 64 |
| 6260 | // 12266: } |
| 6261 | // 12266: } // switch Inst[17:15] |
| 6262 | // 12266: } |
| 6263 | 59, 51, // 12270: case 0x3b: { |
| 6264 | OPC_SwitchField, 15, 3, // 12272: switch Inst[17:15] { |
| 6265 | 0, 4, // 12275: case 0x0: { |
| 6266 | OPC_Decode, 176, 18, 64, // 12277: decode to XVSRA_B using decoder 64 |
| 6267 | // 12277: } |
| 6268 | 1, 4, // 12281: case 0x1: { |
| 6269 | OPC_Decode, 178, 18, 64, // 12283: decode to XVSRA_H using decoder 64 |
| 6270 | // 12283: } |
| 6271 | 2, 4, // 12287: case 0x2: { |
| 6272 | OPC_Decode, 179, 18, 64, // 12289: decode to XVSRA_W using decoder 64 |
| 6273 | // 12289: } |
| 6274 | 3, 4, // 12293: case 0x3: { |
| 6275 | OPC_Decode, 177, 18, 64, // 12295: decode to XVSRA_D using decoder 64 |
| 6276 | // 12295: } |
| 6277 | 4, 4, // 12299: case 0x4: { |
| 6278 | OPC_Decode, 182, 17, 64, // 12301: decode to XVROTR_B using decoder 64 |
| 6279 | // 12301: } |
| 6280 | 5, 4, // 12305: case 0x5: { |
| 6281 | OPC_Decode, 184, 17, 64, // 12307: decode to XVROTR_H using decoder 64 |
| 6282 | // 12307: } |
| 6283 | 6, 4, // 12311: case 0x6: { |
| 6284 | OPC_Decode, 185, 17, 64, // 12313: decode to XVROTR_W using decoder 64 |
| 6285 | // 12313: } |
| 6286 | 7, 0, // 12317: case 0x7: { |
| 6287 | OPC_Decode, 183, 17, 64, // 12319: decode to XVROTR_D using decoder 64 |
| 6288 | // 12319: } |
| 6289 | // 12319: } // switch Inst[17:15] |
| 6290 | // 12319: } |
| 6291 | 60, 51, // 12323: case 0x3c: { |
| 6292 | OPC_SwitchField, 15, 3, // 12325: switch Inst[17:15] { |
| 6293 | 0, 4, // 12328: case 0x0: { |
| 6294 | OPC_Decode, 202, 18, 64, // 12330: decode to XVSRLR_B using decoder 64 |
| 6295 | // 12330: } |
| 6296 | 1, 4, // 12334: case 0x1: { |
| 6297 | OPC_Decode, 204, 18, 64, // 12336: decode to XVSRLR_H using decoder 64 |
| 6298 | // 12336: } |
| 6299 | 2, 4, // 12340: case 0x2: { |
| 6300 | OPC_Decode, 205, 18, 64, // 12342: decode to XVSRLR_W using decoder 64 |
| 6301 | // 12342: } |
| 6302 | 3, 4, // 12346: case 0x3: { |
| 6303 | OPC_Decode, 203, 18, 64, // 12348: decode to XVSRLR_D using decoder 64 |
| 6304 | // 12348: } |
| 6305 | 4, 4, // 12352: case 0x4: { |
| 6306 | OPC_Decode, 172, 18, 64, // 12354: decode to XVSRAR_B using decoder 64 |
| 6307 | // 12354: } |
| 6308 | 5, 4, // 12358: case 0x5: { |
| 6309 | OPC_Decode, 174, 18, 64, // 12360: decode to XVSRAR_H using decoder 64 |
| 6310 | // 12360: } |
| 6311 | 6, 4, // 12364: case 0x6: { |
| 6312 | OPC_Decode, 175, 18, 64, // 12366: decode to XVSRAR_W using decoder 64 |
| 6313 | // 12366: } |
| 6314 | 7, 0, // 12370: case 0x7: { |
| 6315 | OPC_Decode, 173, 18, 64, // 12372: decode to XVSRAR_D using decoder 64 |
| 6316 | // 12372: } |
| 6317 | // 12372: } // switch Inst[17:15] |
| 6318 | // 12372: } |
| 6319 | 61, 39, // 12376: case 0x3d: { |
| 6320 | OPC_SwitchField, 15, 3, // 12378: switch Inst[17:15] { |
| 6321 | 1, 4, // 12381: case 0x1: { |
| 6322 | OPC_Decode, 188, 18, 64, // 12383: decode to XVSRLN_B_H using decoder 64 |
| 6323 | // 12383: } |
| 6324 | 2, 4, // 12387: case 0x2: { |
| 6325 | OPC_Decode, 189, 18, 64, // 12389: decode to XVSRLN_H_W using decoder 64 |
| 6326 | // 12389: } |
| 6327 | 3, 4, // 12393: case 0x3: { |
| 6328 | OPC_Decode, 190, 18, 64, // 12395: decode to XVSRLN_W_D using decoder 64 |
| 6329 | // 12395: } |
| 6330 | 5, 4, // 12399: case 0x5: { |
| 6331 | OPC_Decode, 158, 18, 64, // 12401: decode to XVSRAN_B_H using decoder 64 |
| 6332 | // 12401: } |
| 6333 | 6, 4, // 12405: case 0x6: { |
| 6334 | OPC_Decode, 159, 18, 64, // 12407: decode to XVSRAN_H_W using decoder 64 |
| 6335 | // 12407: } |
| 6336 | 7, 0, // 12411: case 0x7: { |
| 6337 | OPC_Decode, 160, 18, 64, // 12413: decode to XVSRAN_W_D using decoder 64 |
| 6338 | // 12413: } |
| 6339 | // 12413: } // switch Inst[17:15] |
| 6340 | // 12413: } |
| 6341 | 62, 39, // 12417: case 0x3e: { |
| 6342 | OPC_SwitchField, 15, 3, // 12419: switch Inst[17:15] { |
| 6343 | 1, 4, // 12422: case 0x1: { |
| 6344 | OPC_Decode, 199, 18, 64, // 12424: decode to XVSRLRN_B_H using decoder 64 |
| 6345 | // 12424: } |
| 6346 | 2, 4, // 12428: case 0x2: { |
| 6347 | OPC_Decode, 200, 18, 64, // 12430: decode to XVSRLRN_H_W using decoder 64 |
| 6348 | // 12430: } |
| 6349 | 3, 4, // 12434: case 0x3: { |
| 6350 | OPC_Decode, 201, 18, 64, // 12436: decode to XVSRLRN_W_D using decoder 64 |
| 6351 | // 12436: } |
| 6352 | 5, 4, // 12440: case 0x5: { |
| 6353 | OPC_Decode, 169, 18, 64, // 12442: decode to XVSRARN_B_H using decoder 64 |
| 6354 | // 12442: } |
| 6355 | 6, 4, // 12446: case 0x6: { |
| 6356 | OPC_Decode, 170, 18, 64, // 12448: decode to XVSRARN_H_W using decoder 64 |
| 6357 | // 12448: } |
| 6358 | 7, 0, // 12452: case 0x7: { |
| 6359 | OPC_Decode, 171, 18, 64, // 12454: decode to XVSRARN_W_D using decoder 64 |
| 6360 | // 12454: } |
| 6361 | // 12454: } // switch Inst[17:15] |
| 6362 | // 12454: } |
| 6363 | 63, 39, // 12458: case 0x3f: { |
| 6364 | OPC_SwitchField, 15, 3, // 12460: switch Inst[17:15] { |
| 6365 | 1, 4, // 12463: case 0x1: { |
| 6366 | OPC_Decode, 247, 18, 64, // 12465: decode to XVSSRLN_B_H using decoder 64 |
| 6367 | // 12465: } |
| 6368 | 2, 4, // 12469: case 0x2: { |
| 6369 | OPC_Decode, 249, 18, 64, // 12471: decode to XVSSRLN_H_W using decoder 64 |
| 6370 | // 12471: } |
| 6371 | 3, 4, // 12475: case 0x3: { |
| 6372 | OPC_Decode, 251, 18, 64, // 12477: decode to XVSSRLN_W_D using decoder 64 |
| 6373 | // 12477: } |
| 6374 | 5, 4, // 12481: case 0x5: { |
| 6375 | OPC_Decode, 219, 18, 64, // 12483: decode to XVSSRAN_B_H using decoder 64 |
| 6376 | // 12483: } |
| 6377 | 6, 4, // 12487: case 0x6: { |
| 6378 | OPC_Decode, 221, 18, 64, // 12489: decode to XVSSRAN_H_W using decoder 64 |
| 6379 | // 12489: } |
| 6380 | 7, 0, // 12493: case 0x7: { |
| 6381 | OPC_Decode, 223, 18, 64, // 12495: decode to XVSSRAN_W_D using decoder 64 |
| 6382 | // 12495: } |
| 6383 | // 12495: } // switch Inst[17:15] |
| 6384 | // 12495: } |
| 6385 | 64, 39, // 12499: case 0x40: { |
| 6386 | OPC_SwitchField, 15, 3, // 12501: switch Inst[17:15] { |
| 6387 | 1, 4, // 12504: case 0x1: { |
| 6388 | OPC_Decode, 133, 19, 64, // 12506: decode to XVSSRLRN_B_H using decoder 64 |
| 6389 | // 12506: } |
| 6390 | 2, 4, // 12510: case 0x2: { |
| 6391 | OPC_Decode, 135, 19, 64, // 12512: decode to XVSSRLRN_H_W using decoder 64 |
| 6392 | // 12512: } |
| 6393 | 3, 4, // 12516: case 0x3: { |
| 6394 | OPC_Decode, 137, 19, 64, // 12518: decode to XVSSRLRN_W_D using decoder 64 |
| 6395 | // 12518: } |
| 6396 | 5, 4, // 12522: case 0x5: { |
| 6397 | OPC_Decode, 233, 18, 64, // 12524: decode to XVSSRARN_B_H using decoder 64 |
| 6398 | // 12524: } |
| 6399 | 6, 4, // 12528: case 0x6: { |
| 6400 | OPC_Decode, 235, 18, 64, // 12530: decode to XVSSRARN_H_W using decoder 64 |
| 6401 | // 12530: } |
| 6402 | 7, 0, // 12534: case 0x7: { |
| 6403 | OPC_Decode, 237, 18, 64, // 12536: decode to XVSSRARN_W_D using decoder 64 |
| 6404 | // 12536: } |
| 6405 | // 12536: } // switch Inst[17:15] |
| 6406 | // 12536: } |
| 6407 | 65, 39, // 12540: case 0x41: { |
| 6408 | OPC_SwitchField, 15, 3, // 12542: switch Inst[17:15] { |
| 6409 | 1, 4, // 12545: case 0x1: { |
| 6410 | OPC_Decode, 246, 18, 64, // 12547: decode to XVSSRLN_BU_H using decoder 64 |
| 6411 | // 12547: } |
| 6412 | 2, 4, // 12551: case 0x2: { |
| 6413 | OPC_Decode, 248, 18, 64, // 12553: decode to XVSSRLN_HU_W using decoder 64 |
| 6414 | // 12553: } |
| 6415 | 3, 4, // 12557: case 0x3: { |
| 6416 | OPC_Decode, 250, 18, 64, // 12559: decode to XVSSRLN_WU_D using decoder 64 |
| 6417 | // 12559: } |
| 6418 | 5, 4, // 12563: case 0x5: { |
| 6419 | OPC_Decode, 218, 18, 64, // 12565: decode to XVSSRAN_BU_H using decoder 64 |
| 6420 | // 12565: } |
| 6421 | 6, 4, // 12569: case 0x6: { |
| 6422 | OPC_Decode, 220, 18, 64, // 12571: decode to XVSSRAN_HU_W using decoder 64 |
| 6423 | // 12571: } |
| 6424 | 7, 0, // 12575: case 0x7: { |
| 6425 | OPC_Decode, 222, 18, 64, // 12577: decode to XVSSRAN_WU_D using decoder 64 |
| 6426 | // 12577: } |
| 6427 | // 12577: } // switch Inst[17:15] |
| 6428 | // 12577: } |
| 6429 | 66, 39, // 12581: case 0x42: { |
| 6430 | OPC_SwitchField, 15, 3, // 12583: switch Inst[17:15] { |
| 6431 | 1, 4, // 12586: case 0x1: { |
| 6432 | OPC_Decode, 132, 19, 64, // 12588: decode to XVSSRLRN_BU_H using decoder 64 |
| 6433 | // 12588: } |
| 6434 | 2, 4, // 12592: case 0x2: { |
| 6435 | OPC_Decode, 134, 19, 64, // 12594: decode to XVSSRLRN_HU_W using decoder 64 |
| 6436 | // 12594: } |
| 6437 | 3, 4, // 12598: case 0x3: { |
| 6438 | OPC_Decode, 136, 19, 64, // 12600: decode to XVSSRLRN_WU_D using decoder 64 |
| 6439 | // 12600: } |
| 6440 | 5, 4, // 12604: case 0x5: { |
| 6441 | OPC_Decode, 232, 18, 64, // 12606: decode to XVSSRARN_BU_H using decoder 64 |
| 6442 | // 12606: } |
| 6443 | 6, 4, // 12610: case 0x6: { |
| 6444 | OPC_Decode, 234, 18, 64, // 12612: decode to XVSSRARN_HU_W using decoder 64 |
| 6445 | // 12612: } |
| 6446 | 7, 0, // 12616: case 0x7: { |
| 6447 | OPC_Decode, 236, 18, 64, // 12618: decode to XVSSRARN_WU_D using decoder 64 |
| 6448 | // 12618: } |
| 6449 | // 12618: } // switch Inst[17:15] |
| 6450 | // 12618: } |
| 6451 | 67, 51, // 12622: case 0x43: { |
| 6452 | OPC_SwitchField, 15, 3, // 12624: switch Inst[17:15] { |
| 6453 | 0, 4, // 12627: case 0x0: { |
| 6454 | OPC_Decode, 164, 14, 64, // 12629: decode to XVBITCLR_B using decoder 64 |
| 6455 | // 12629: } |
| 6456 | 1, 4, // 12633: case 0x1: { |
| 6457 | OPC_Decode, 166, 14, 64, // 12635: decode to XVBITCLR_H using decoder 64 |
| 6458 | // 12635: } |
| 6459 | 2, 4, // 12639: case 0x2: { |
| 6460 | OPC_Decode, 167, 14, 64, // 12641: decode to XVBITCLR_W using decoder 64 |
| 6461 | // 12641: } |
| 6462 | 3, 4, // 12645: case 0x3: { |
| 6463 | OPC_Decode, 165, 14, 64, // 12647: decode to XVBITCLR_D using decoder 64 |
| 6464 | // 12647: } |
| 6465 | 4, 4, // 12651: case 0x4: { |
| 6466 | OPC_Decode, 182, 14, 64, // 12653: decode to XVBITSET_B using decoder 64 |
| 6467 | // 12653: } |
| 6468 | 5, 4, // 12657: case 0x5: { |
| 6469 | OPC_Decode, 184, 14, 64, // 12659: decode to XVBITSET_H using decoder 64 |
| 6470 | // 12659: } |
| 6471 | 6, 4, // 12663: case 0x6: { |
| 6472 | OPC_Decode, 185, 14, 64, // 12665: decode to XVBITSET_W using decoder 64 |
| 6473 | // 12665: } |
| 6474 | 7, 0, // 12669: case 0x7: { |
| 6475 | OPC_Decode, 183, 14, 64, // 12671: decode to XVBITSET_D using decoder 64 |
| 6476 | // 12671: } |
| 6477 | // 12671: } // switch Inst[17:15] |
| 6478 | // 12671: } |
| 6479 | 68, 27, // 12675: case 0x44: { |
| 6480 | OPC_SwitchField, 15, 3, // 12677: switch Inst[17:15] { |
| 6481 | 0, 4, // 12680: case 0x0: { |
| 6482 | OPC_Decode, 172, 14, 64, // 12682: decode to XVBITREV_B using decoder 64 |
| 6483 | // 12682: } |
| 6484 | 1, 4, // 12686: case 0x1: { |
| 6485 | OPC_Decode, 174, 14, 64, // 12688: decode to XVBITREV_H using decoder 64 |
| 6486 | // 12688: } |
| 6487 | 2, 4, // 12692: case 0x2: { |
| 6488 | OPC_Decode, 175, 14, 64, // 12694: decode to XVBITREV_W using decoder 64 |
| 6489 | // 12694: } |
| 6490 | 3, 0, // 12698: case 0x3: { |
| 6491 | OPC_Decode, 173, 14, 64, // 12700: decode to XVBITREV_D using decoder 64 |
| 6492 | // 12700: } |
| 6493 | // 12700: } // switch Inst[17:15] |
| 6494 | // 12700: } |
| 6495 | 69, 27, // 12704: case 0x45: { |
| 6496 | OPC_SwitchField, 15, 3, // 12706: switch Inst[17:15] { |
| 6497 | 4, 4, // 12709: case 0x4: { |
| 6498 | OPC_Decode, 131, 17, 64, // 12711: decode to XVPACKEV_B using decoder 64 |
| 6499 | // 12711: } |
| 6500 | 5, 4, // 12715: case 0x5: { |
| 6501 | OPC_Decode, 133, 17, 64, // 12717: decode to XVPACKEV_H using decoder 64 |
| 6502 | // 12717: } |
| 6503 | 6, 4, // 12721: case 0x6: { |
| 6504 | OPC_Decode, 134, 17, 64, // 12723: decode to XVPACKEV_W using decoder 64 |
| 6505 | // 12723: } |
| 6506 | 7, 0, // 12727: case 0x7: { |
| 6507 | OPC_Decode, 132, 17, 64, // 12729: decode to XVPACKEV_D using decoder 64 |
| 6508 | // 12729: } |
| 6509 | // 12729: } // switch Inst[17:15] |
| 6510 | // 12729: } |
| 6511 | 70, 51, // 12733: case 0x46: { |
| 6512 | OPC_SwitchField, 15, 3, // 12735: switch Inst[17:15] { |
| 6513 | 0, 4, // 12738: case 0x0: { |
| 6514 | OPC_Decode, 135, 17, 64, // 12740: decode to XVPACKOD_B using decoder 64 |
| 6515 | // 12740: } |
| 6516 | 1, 4, // 12744: case 0x1: { |
| 6517 | OPC_Decode, 137, 17, 64, // 12746: decode to XVPACKOD_H using decoder 64 |
| 6518 | // 12746: } |
| 6519 | 2, 4, // 12750: case 0x2: { |
| 6520 | OPC_Decode, 138, 17, 64, // 12752: decode to XVPACKOD_W using decoder 64 |
| 6521 | // 12752: } |
| 6522 | 3, 4, // 12756: case 0x3: { |
| 6523 | OPC_Decode, 136, 17, 64, // 12758: decode to XVPACKOD_D using decoder 64 |
| 6524 | // 12758: } |
| 6525 | 4, 4, // 12762: case 0x4: { |
| 6526 | OPC_Decode, 249, 15, 64, // 12764: decode to XVILVL_B using decoder 64 |
| 6527 | // 12764: } |
| 6528 | 5, 4, // 12768: case 0x5: { |
| 6529 | OPC_Decode, 251, 15, 64, // 12770: decode to XVILVL_H using decoder 64 |
| 6530 | // 12770: } |
| 6531 | 6, 4, // 12774: case 0x6: { |
| 6532 | OPC_Decode, 252, 15, 64, // 12776: decode to XVILVL_W using decoder 64 |
| 6533 | // 12776: } |
| 6534 | 7, 0, // 12780: case 0x7: { |
| 6535 | OPC_Decode, 250, 15, 64, // 12782: decode to XVILVL_D using decoder 64 |
| 6536 | // 12782: } |
| 6537 | // 12782: } // switch Inst[17:15] |
| 6538 | // 12782: } |
| 6539 | 71, 51, // 12786: case 0x47: { |
| 6540 | OPC_SwitchField, 15, 3, // 12788: switch Inst[17:15] { |
| 6541 | 0, 4, // 12791: case 0x0: { |
| 6542 | OPC_Decode, 245, 15, 64, // 12793: decode to XVILVH_B using decoder 64 |
| 6543 | // 12793: } |
| 6544 | 1, 4, // 12797: case 0x1: { |
| 6545 | OPC_Decode, 247, 15, 64, // 12799: decode to XVILVH_H using decoder 64 |
| 6546 | // 12799: } |
| 6547 | 2, 4, // 12803: case 0x2: { |
| 6548 | OPC_Decode, 248, 15, 64, // 12805: decode to XVILVH_W using decoder 64 |
| 6549 | // 12805: } |
| 6550 | 3, 4, // 12809: case 0x3: { |
| 6551 | OPC_Decode, 246, 15, 64, // 12811: decode to XVILVH_D using decoder 64 |
| 6552 | // 12811: } |
| 6553 | 4, 4, // 12815: case 0x4: { |
| 6554 | OPC_Decode, 147, 17, 64, // 12817: decode to XVPICKEV_B using decoder 64 |
| 6555 | // 12817: } |
| 6556 | 5, 4, // 12821: case 0x5: { |
| 6557 | OPC_Decode, 149, 17, 64, // 12823: decode to XVPICKEV_H using decoder 64 |
| 6558 | // 12823: } |
| 6559 | 6, 4, // 12827: case 0x6: { |
| 6560 | OPC_Decode, 150, 17, 64, // 12829: decode to XVPICKEV_W using decoder 64 |
| 6561 | // 12829: } |
| 6562 | 7, 0, // 12833: case 0x7: { |
| 6563 | OPC_Decode, 148, 17, 64, // 12835: decode to XVPICKEV_D using decoder 64 |
| 6564 | // 12835: } |
| 6565 | // 12835: } // switch Inst[17:15] |
| 6566 | // 12835: } |
| 6567 | 72, 55, // 12839: case 0x48: { |
| 6568 | OPC_SwitchField, 15, 3, // 12841: switch Inst[17:15] { |
| 6569 | 0, 4, // 12844: case 0x0: { |
| 6570 | OPC_Decode, 151, 17, 64, // 12846: decode to XVPICKOD_B using decoder 64 |
| 6571 | // 12846: } |
| 6572 | 1, 4, // 12850: case 0x1: { |
| 6573 | OPC_Decode, 153, 17, 64, // 12852: decode to XVPICKOD_H using decoder 64 |
| 6574 | // 12852: } |
| 6575 | 2, 4, // 12856: case 0x2: { |
| 6576 | OPC_Decode, 154, 17, 64, // 12858: decode to XVPICKOD_W using decoder 64 |
| 6577 | // 12858: } |
| 6578 | 3, 4, // 12862: case 0x3: { |
| 6579 | OPC_Decode, 152, 17, 64, // 12864: decode to XVPICKOD_D using decoder 64 |
| 6580 | // 12864: } |
| 6581 | 4, 5, // 12868: case 0x4: { |
| 6582 | OPC_Decode, 174, 17, 132, 1, // 12870: decode to XVREPLVE_B using decoder 132 |
| 6583 | // 12870: } |
| 6584 | 5, 5, // 12875: case 0x5: { |
| 6585 | OPC_Decode, 176, 17, 132, 1, // 12877: decode to XVREPLVE_H using decoder 132 |
| 6586 | // 12877: } |
| 6587 | 6, 5, // 12882: case 0x6: { |
| 6588 | OPC_Decode, 177, 17, 132, 1, // 12884: decode to XVREPLVE_W using decoder 132 |
| 6589 | // 12884: } |
| 6590 | 7, 0, // 12889: case 0x7: { |
| 6591 | OPC_Decode, 175, 17, 132, 1, // 12891: decode to XVREPLVE_D using decoder 132 |
| 6592 | // 12891: } |
| 6593 | // 12891: } // switch Inst[17:15] |
| 6594 | // 12891: } |
| 6595 | 73, 27, // 12896: case 0x49: { |
| 6596 | OPC_SwitchField, 15, 3, // 12898: switch Inst[17:15] { |
| 6597 | 4, 4, // 12901: case 0x4: { |
| 6598 | OPC_Decode, 143, 14, 64, // 12903: decode to XVAND_V using decoder 64 |
| 6599 | // 12903: } |
| 6600 | 5, 4, // 12907: case 0x5: { |
| 6601 | OPC_Decode, 130, 17, 64, // 12909: decode to XVOR_V using decoder 64 |
| 6602 | // 12909: } |
| 6603 | 6, 4, // 12913: case 0x6: { |
| 6604 | OPC_Decode, 178, 19, 64, // 12915: decode to XVXOR_V using decoder 64 |
| 6605 | // 12915: } |
| 6606 | 7, 0, // 12919: case 0x7: { |
| 6607 | OPC_Decode, 255, 16, 64, // 12921: decode to XVNOR_V using decoder 64 |
| 6608 | // 12921: } |
| 6609 | // 12921: } // switch Inst[17:15] |
| 6610 | // 12921: } |
| 6611 | 74, 29, // 12925: case 0x4a: { |
| 6612 | OPC_SwitchField, 15, 3, // 12927: switch Inst[17:15] { |
| 6613 | 0, 4, // 12930: case 0x0: { |
| 6614 | OPC_Decode, 142, 14, 64, // 12932: decode to XVANDN_V using decoder 64 |
| 6615 | // 12932: } |
| 6616 | 1, 4, // 12936: case 0x1: { |
| 6617 | OPC_Decode, 129, 17, 64, // 12938: decode to XVORN_V using decoder 64 |
| 6618 | // 12938: } |
| 6619 | 6, 5, // 12942: case 0x6: { |
| 6620 | OPC_Decode, 193, 15, 131, 1, // 12944: decode to XVFRSTP_B using decoder 131 |
| 6621 | // 12944: } |
| 6622 | 7, 0, // 12949: case 0x7: { |
| 6623 | OPC_Decode, 194, 15, 131, 1, // 12951: decode to XVFRSTP_H using decoder 131 |
| 6624 | // 12951: } |
| 6625 | // 12951: } // switch Inst[17:15] |
| 6626 | // 12951: } |
| 6627 | 75, 39, // 12956: case 0x4b: { |
| 6628 | OPC_SwitchField, 15, 3, // 12958: switch Inst[17:15] { |
| 6629 | 2, 4, // 12961: case 0x2: { |
| 6630 | OPC_Decode, 139, 14, 64, // 12963: decode to XVADD_Q using decoder 64 |
| 6631 | // 12963: } |
| 6632 | 3, 4, // 12967: case 0x3: { |
| 6633 | OPC_Decode, 175, 19, 64, // 12969: decode to XVSUB_Q using decoder 64 |
| 6634 | // 12969: } |
| 6635 | 4, 4, // 12973: case 0x4: { |
| 6636 | OPC_Decode, 228, 17, 64, // 12975: decode to XVSIGNCOV_B using decoder 64 |
| 6637 | // 12975: } |
| 6638 | 5, 4, // 12979: case 0x5: { |
| 6639 | OPC_Decode, 230, 17, 64, // 12981: decode to XVSIGNCOV_H using decoder 64 |
| 6640 | // 12981: } |
| 6641 | 6, 4, // 12985: case 0x6: { |
| 6642 | OPC_Decode, 231, 17, 64, // 12987: decode to XVSIGNCOV_W using decoder 64 |
| 6643 | // 12987: } |
| 6644 | 7, 0, // 12991: case 0x7: { |
| 6645 | OPC_Decode, 229, 17, 64, // 12993: decode to XVSIGNCOV_D using decoder 64 |
| 6646 | // 12993: } |
| 6647 | // 12993: } // switch Inst[17:15] |
| 6648 | // 12993: } |
| 6649 | 76, 27, // 12997: case 0x4c: { |
| 6650 | OPC_SwitchField, 15, 3, // 12999: switch Inst[17:15] { |
| 6651 | 1, 4, // 13002: case 0x1: { |
| 6652 | OPC_Decode, 219, 14, 64, // 13004: decode to XVFADD_S using decoder 64 |
| 6653 | // 13004: } |
| 6654 | 2, 4, // 13008: case 0x2: { |
| 6655 | OPC_Decode, 218, 14, 64, // 13010: decode to XVFADD_D using decoder 64 |
| 6656 | // 13010: } |
| 6657 | 5, 4, // 13014: case 0x5: { |
| 6658 | OPC_Decode, 198, 15, 64, // 13016: decode to XVFSUB_S using decoder 64 |
| 6659 | // 13016: } |
| 6660 | 6, 0, // 13020: case 0x6: { |
| 6661 | OPC_Decode, 197, 15, 64, // 13022: decode to XVFSUB_D using decoder 64 |
| 6662 | // 13022: } |
| 6663 | // 13022: } // switch Inst[17:15] |
| 6664 | // 13022: } |
| 6665 | 78, 27, // 13026: case 0x4e: { |
| 6666 | OPC_SwitchField, 15, 3, // 13028: switch Inst[17:15] { |
| 6667 | 1, 4, // 13031: case 0x1: { |
| 6668 | OPC_Decode, 168, 15, 64, // 13033: decode to XVFMUL_S using decoder 64 |
| 6669 | // 13033: } |
| 6670 | 2, 4, // 13037: case 0x2: { |
| 6671 | OPC_Decode, 167, 15, 64, // 13039: decode to XVFMUL_D using decoder 64 |
| 6672 | // 13039: } |
| 6673 | 5, 4, // 13043: case 0x5: { |
| 6674 | OPC_Decode, 145, 15, 64, // 13045: decode to XVFDIV_S using decoder 64 |
| 6675 | // 13045: } |
| 6676 | 6, 0, // 13049: case 0x6: { |
| 6677 | OPC_Decode, 144, 15, 64, // 13051: decode to XVFDIV_D using decoder 64 |
| 6678 | // 13051: } |
| 6679 | // 13051: } // switch Inst[17:15] |
| 6680 | // 13051: } |
| 6681 | 79, 27, // 13055: case 0x4f: { |
| 6682 | OPC_SwitchField, 15, 3, // 13057: switch Inst[17:15] { |
| 6683 | 1, 4, // 13060: case 0x1: { |
| 6684 | OPC_Decode, 160, 15, 64, // 13062: decode to XVFMAX_S using decoder 64 |
| 6685 | // 13062: } |
| 6686 | 2, 4, // 13066: case 0x2: { |
| 6687 | OPC_Decode, 159, 15, 64, // 13068: decode to XVFMAX_D using decoder 64 |
| 6688 | // 13068: } |
| 6689 | 5, 4, // 13072: case 0x5: { |
| 6690 | OPC_Decode, 164, 15, 64, // 13074: decode to XVFMIN_S using decoder 64 |
| 6691 | // 13074: } |
| 6692 | 6, 0, // 13078: case 0x6: { |
| 6693 | OPC_Decode, 163, 15, 64, // 13080: decode to XVFMIN_D using decoder 64 |
| 6694 | // 13080: } |
| 6695 | // 13080: } // switch Inst[17:15] |
| 6696 | // 13080: } |
| 6697 | 80, 27, // 13084: case 0x50: { |
| 6698 | OPC_SwitchField, 15, 3, // 13086: switch Inst[17:15] { |
| 6699 | 1, 4, // 13089: case 0x1: { |
| 6700 | OPC_Decode, 158, 15, 64, // 13091: decode to XVFMAXA_S using decoder 64 |
| 6701 | // 13091: } |
| 6702 | 2, 4, // 13095: case 0x2: { |
| 6703 | OPC_Decode, 157, 15, 64, // 13097: decode to XVFMAXA_D using decoder 64 |
| 6704 | // 13097: } |
| 6705 | 5, 4, // 13101: case 0x5: { |
| 6706 | OPC_Decode, 162, 15, 64, // 13103: decode to XVFMINA_S using decoder 64 |
| 6707 | // 13103: } |
| 6708 | 6, 0, // 13107: case 0x6: { |
| 6709 | OPC_Decode, 161, 15, 64, // 13109: decode to XVFMINA_D using decoder 64 |
| 6710 | // 13109: } |
| 6711 | // 13109: } // switch Inst[17:15] |
| 6712 | // 13109: } |
| 6713 | 81, 15, // 13113: case 0x51: { |
| 6714 | OPC_SwitchField, 15, 3, // 13115: switch Inst[17:15] { |
| 6715 | 4, 4, // 13118: case 0x4: { |
| 6716 | OPC_Decode, 142, 15, 64, // 13120: decode to XVFCVT_H_S using decoder 64 |
| 6717 | // 13120: } |
| 6718 | 5, 0, // 13124: case 0x5: { |
| 6719 | OPC_Decode, 143, 15, 64, // 13126: decode to XVFCVT_S_D using decoder 64 |
| 6720 | // 13126: } |
| 6721 | // 13126: } // switch Inst[17:15] |
| 6722 | // 13126: } |
| 6723 | 82, 39, // 13130: case 0x52: { |
| 6724 | OPC_SwitchField, 15, 3, // 13132: switch Inst[17:15] { |
| 6725 | 0, 4, // 13135: case 0x0: { |
| 6726 | OPC_Decode, 150, 15, 64, // 13137: decode to XVFFINT_S_L using decoder 64 |
| 6727 | // 13137: } |
| 6728 | 3, 4, // 13141: case 0x3: { |
| 6729 | OPC_Decode, 226, 15, 64, // 13143: decode to XVFTINT_W_D using decoder 64 |
| 6730 | // 13143: } |
| 6731 | 4, 4, // 13147: case 0x4: { |
| 6732 | OPC_Decode, 204, 15, 64, // 13149: decode to XVFTINTRM_W_D using decoder 64 |
| 6733 | // 13149: } |
| 6734 | 5, 4, // 13153: case 0x5: { |
| 6735 | OPC_Decode, 214, 15, 64, // 13155: decode to XVFTINTRP_W_D using decoder 64 |
| 6736 | // 13155: } |
| 6737 | 6, 4, // 13159: case 0x6: { |
| 6738 | OPC_Decode, 221, 15, 64, // 13161: decode to XVFTINTRZ_W_D using decoder 64 |
| 6739 | // 13161: } |
| 6740 | 7, 0, // 13165: case 0x7: { |
| 6741 | OPC_Decode, 209, 15, 64, // 13167: decode to XVFTINTRNE_W_D using decoder 64 |
| 6742 | // 13167: } |
| 6743 | // 13167: } // switch Inst[17:15] |
| 6744 | // 13167: } |
| 6745 | 94, 24, // 13171: case 0x5e: { |
| 6746 | OPC_SwitchField, 15, 3, // 13173: switch Inst[17:15] { |
| 6747 | 5, 5, // 13176: case 0x5: { |
| 6748 | OPC_Decode, 226, 17, 131, 1, // 13178: decode to XVSHUF_H using decoder 131 |
| 6749 | // 13178: } |
| 6750 | 6, 5, // 13183: case 0x6: { |
| 6751 | OPC_Decode, 227, 17, 131, 1, // 13185: decode to XVSHUF_W using decoder 131 |
| 6752 | // 13185: } |
| 6753 | 7, 0, // 13190: case 0x7: { |
| 6754 | OPC_Decode, 225, 17, 131, 1, // 13192: decode to XVSHUF_D using decoder 131 |
| 6755 | // 13192: } |
| 6756 | // 13192: } // switch Inst[17:15] |
| 6757 | // 13192: } |
| 6758 | 95, 8, // 13197: case 0x5f: { |
| 6759 | OPC_CheckField, 15, 3, 2, // 13199: check Inst[17:15] == 0x2 |
| 6760 | OPC_Decode, 146, 17, 64, // 13203: decode to XVPERM_W using decoder 64 |
| 6761 | // 13203: } |
| 6762 | 160, 1, 59, // 13207: case 0xa0: { |
| 6763 | OPC_SwitchField, 15, 3, // 13210: switch Inst[17:15] { |
| 6764 | 0, 5, // 13213: case 0x0: { |
| 6765 | OPC_Decode, 202, 17, 133, 1, // 13215: decode to XVSEQI_B using decoder 133 |
| 6766 | // 13215: } |
| 6767 | 1, 5, // 13220: case 0x1: { |
| 6768 | OPC_Decode, 204, 17, 133, 1, // 13222: decode to XVSEQI_H using decoder 133 |
| 6769 | // 13222: } |
| 6770 | 2, 5, // 13227: case 0x2: { |
| 6771 | OPC_Decode, 205, 17, 133, 1, // 13229: decode to XVSEQI_W using decoder 133 |
| 6772 | // 13229: } |
| 6773 | 3, 5, // 13234: case 0x3: { |
| 6774 | OPC_Decode, 203, 17, 133, 1, // 13236: decode to XVSEQI_D using decoder 133 |
| 6775 | // 13236: } |
| 6776 | 4, 5, // 13241: case 0x4: { |
| 6777 | OPC_Decode, 232, 17, 133, 1, // 13243: decode to XVSLEI_B using decoder 133 |
| 6778 | // 13243: } |
| 6779 | 5, 5, // 13248: case 0x5: { |
| 6780 | OPC_Decode, 236, 17, 133, 1, // 13250: decode to XVSLEI_H using decoder 133 |
| 6781 | // 13250: } |
| 6782 | 6, 5, // 13255: case 0x6: { |
| 6783 | OPC_Decode, 238, 17, 133, 1, // 13257: decode to XVSLEI_W using decoder 133 |
| 6784 | // 13257: } |
| 6785 | 7, 0, // 13262: case 0x7: { |
| 6786 | OPC_Decode, 234, 17, 133, 1, // 13264: decode to XVSLEI_D using decoder 133 |
| 6787 | // 13264: } |
| 6788 | // 13264: } // switch Inst[17:15] |
| 6789 | // 13264: } |
| 6790 | 161, 1, 59, // 13269: case 0xa1: { |
| 6791 | OPC_SwitchField, 15, 3, // 13272: switch Inst[17:15] { |
| 6792 | 0, 5, // 13275: case 0x0: { |
| 6793 | OPC_Decode, 233, 17, 134, 1, // 13277: decode to XVSLEI_BU using decoder 134 |
| 6794 | // 13277: } |
| 6795 | 1, 5, // 13282: case 0x1: { |
| 6796 | OPC_Decode, 237, 17, 134, 1, // 13284: decode to XVSLEI_HU using decoder 134 |
| 6797 | // 13284: } |
| 6798 | 2, 5, // 13289: case 0x2: { |
| 6799 | OPC_Decode, 239, 17, 134, 1, // 13291: decode to XVSLEI_WU using decoder 134 |
| 6800 | // 13291: } |
| 6801 | 3, 5, // 13296: case 0x3: { |
| 6802 | OPC_Decode, 235, 17, 134, 1, // 13298: decode to XVSLEI_DU using decoder 134 |
| 6803 | // 13298: } |
| 6804 | 4, 5, // 13303: case 0x4: { |
| 6805 | OPC_Decode, 134, 18, 133, 1, // 13305: decode to XVSLTI_B using decoder 133 |
| 6806 | // 13305: } |
| 6807 | 5, 5, // 13310: case 0x5: { |
| 6808 | OPC_Decode, 138, 18, 133, 1, // 13312: decode to XVSLTI_H using decoder 133 |
| 6809 | // 13312: } |
| 6810 | 6, 5, // 13317: case 0x6: { |
| 6811 | OPC_Decode, 140, 18, 133, 1, // 13319: decode to XVSLTI_W using decoder 133 |
| 6812 | // 13319: } |
| 6813 | 7, 0, // 13324: case 0x7: { |
| 6814 | OPC_Decode, 136, 18, 133, 1, // 13326: decode to XVSLTI_D using decoder 133 |
| 6815 | // 13326: } |
| 6816 | // 13326: } // switch Inst[17:15] |
| 6817 | // 13326: } |
| 6818 | 162, 1, 59, // 13331: case 0xa2: { |
| 6819 | OPC_SwitchField, 15, 3, // 13334: switch Inst[17:15] { |
| 6820 | 0, 5, // 13337: case 0x0: { |
| 6821 | OPC_Decode, 135, 18, 134, 1, // 13339: decode to XVSLTI_BU using decoder 134 |
| 6822 | // 13339: } |
| 6823 | 1, 5, // 13344: case 0x1: { |
| 6824 | OPC_Decode, 139, 18, 134, 1, // 13346: decode to XVSLTI_HU using decoder 134 |
| 6825 | // 13346: } |
| 6826 | 2, 5, // 13351: case 0x2: { |
| 6827 | OPC_Decode, 141, 18, 134, 1, // 13353: decode to XVSLTI_WU using decoder 134 |
| 6828 | // 13353: } |
| 6829 | 3, 5, // 13358: case 0x3: { |
| 6830 | OPC_Decode, 137, 18, 134, 1, // 13360: decode to XVSLTI_DU using decoder 134 |
| 6831 | // 13360: } |
| 6832 | 4, 5, // 13365: case 0x4: { |
| 6833 | OPC_Decode, 236, 13, 134, 1, // 13367: decode to XVADDI_BU using decoder 134 |
| 6834 | // 13367: } |
| 6835 | 5, 5, // 13372: case 0x5: { |
| 6836 | OPC_Decode, 238, 13, 134, 1, // 13374: decode to XVADDI_HU using decoder 134 |
| 6837 | // 13374: } |
| 6838 | 6, 5, // 13379: case 0x6: { |
| 6839 | OPC_Decode, 239, 13, 134, 1, // 13381: decode to XVADDI_WU using decoder 134 |
| 6840 | // 13381: } |
| 6841 | 7, 0, // 13386: case 0x7: { |
| 6842 | OPC_Decode, 237, 13, 134, 1, // 13388: decode to XVADDI_DU using decoder 134 |
| 6843 | // 13388: } |
| 6844 | // 13388: } // switch Inst[17:15] |
| 6845 | // 13388: } |
| 6846 | 163, 1, 45, // 13393: case 0xa3: { |
| 6847 | OPC_SwitchField, 15, 3, // 13396: switch Inst[17:15] { |
| 6848 | 0, 5, // 13399: case 0x0: { |
| 6849 | OPC_Decode, 152, 19, 134, 1, // 13401: decode to XVSUBI_BU using decoder 134 |
| 6850 | // 13401: } |
| 6851 | 1, 5, // 13406: case 0x1: { |
| 6852 | OPC_Decode, 154, 19, 134, 1, // 13408: decode to XVSUBI_HU using decoder 134 |
| 6853 | // 13408: } |
| 6854 | 2, 5, // 13413: case 0x2: { |
| 6855 | OPC_Decode, 155, 19, 134, 1, // 13415: decode to XVSUBI_WU using decoder 134 |
| 6856 | // 13415: } |
| 6857 | 3, 5, // 13420: case 0x3: { |
| 6858 | OPC_Decode, 153, 19, 134, 1, // 13422: decode to XVSUBI_DU using decoder 134 |
| 6859 | // 13422: } |
| 6860 | 4, 5, // 13427: case 0x4: { |
| 6861 | OPC_Decode, 186, 14, 134, 1, // 13429: decode to XVBSLL_V using decoder 134 |
| 6862 | // 13429: } |
| 6863 | 5, 0, // 13434: case 0x5: { |
| 6864 | OPC_Decode, 187, 14, 134, 1, // 13436: decode to XVBSRL_V using decoder 134 |
| 6865 | // 13436: } |
| 6866 | // 13436: } // switch Inst[17:15] |
| 6867 | // 13436: } |
| 6868 | 164, 1, 59, // 13441: case 0xa4: { |
| 6869 | OPC_SwitchField, 15, 3, // 13444: switch Inst[17:15] { |
| 6870 | 0, 5, // 13447: case 0x0: { |
| 6871 | OPC_Decode, 164, 16, 133, 1, // 13449: decode to XVMAXI_B using decoder 133 |
| 6872 | // 13449: } |
| 6873 | 1, 5, // 13454: case 0x1: { |
| 6874 | OPC_Decode, 168, 16, 133, 1, // 13456: decode to XVMAXI_H using decoder 133 |
| 6875 | // 13456: } |
| 6876 | 2, 5, // 13461: case 0x2: { |
| 6877 | OPC_Decode, 170, 16, 133, 1, // 13463: decode to XVMAXI_W using decoder 133 |
| 6878 | // 13463: } |
| 6879 | 3, 5, // 13468: case 0x3: { |
| 6880 | OPC_Decode, 166, 16, 133, 1, // 13470: decode to XVMAXI_D using decoder 133 |
| 6881 | // 13470: } |
| 6882 | 4, 5, // 13475: case 0x4: { |
| 6883 | OPC_Decode, 180, 16, 133, 1, // 13477: decode to XVMINI_B using decoder 133 |
| 6884 | // 13477: } |
| 6885 | 5, 5, // 13482: case 0x5: { |
| 6886 | OPC_Decode, 184, 16, 133, 1, // 13484: decode to XVMINI_H using decoder 133 |
| 6887 | // 13484: } |
| 6888 | 6, 5, // 13489: case 0x6: { |
| 6889 | OPC_Decode, 186, 16, 133, 1, // 13491: decode to XVMINI_W using decoder 133 |
| 6890 | // 13491: } |
| 6891 | 7, 0, // 13496: case 0x7: { |
| 6892 | OPC_Decode, 182, 16, 133, 1, // 13498: decode to XVMINI_D using decoder 133 |
| 6893 | // 13498: } |
| 6894 | // 13498: } // switch Inst[17:15] |
| 6895 | // 13498: } |
| 6896 | 165, 1, 59, // 13503: case 0xa5: { |
| 6897 | OPC_SwitchField, 15, 3, // 13506: switch Inst[17:15] { |
| 6898 | 0, 5, // 13509: case 0x0: { |
| 6899 | OPC_Decode, 165, 16, 134, 1, // 13511: decode to XVMAXI_BU using decoder 134 |
| 6900 | // 13511: } |
| 6901 | 1, 5, // 13516: case 0x1: { |
| 6902 | OPC_Decode, 169, 16, 134, 1, // 13518: decode to XVMAXI_HU using decoder 134 |
| 6903 | // 13518: } |
| 6904 | 2, 5, // 13523: case 0x2: { |
| 6905 | OPC_Decode, 171, 16, 134, 1, // 13525: decode to XVMAXI_WU using decoder 134 |
| 6906 | // 13525: } |
| 6907 | 3, 5, // 13530: case 0x3: { |
| 6908 | OPC_Decode, 167, 16, 134, 1, // 13532: decode to XVMAXI_DU using decoder 134 |
| 6909 | // 13532: } |
| 6910 | 4, 5, // 13537: case 0x4: { |
| 6911 | OPC_Decode, 181, 16, 134, 1, // 13539: decode to XVMINI_BU using decoder 134 |
| 6912 | // 13539: } |
| 6913 | 5, 5, // 13544: case 0x5: { |
| 6914 | OPC_Decode, 185, 16, 134, 1, // 13546: decode to XVMINI_HU using decoder 134 |
| 6915 | // 13546: } |
| 6916 | 6, 5, // 13551: case 0x6: { |
| 6917 | OPC_Decode, 187, 16, 134, 1, // 13553: decode to XVMINI_WU using decoder 134 |
| 6918 | // 13553: } |
| 6919 | 7, 0, // 13558: case 0x7: { |
| 6920 | OPC_Decode, 183, 16, 134, 1, // 13560: decode to XVMINI_DU using decoder 134 |
| 6921 | // 13560: } |
| 6922 | // 13560: } // switch Inst[17:15] |
| 6923 | // 13560: } |
| 6924 | 166, 1, 17, // 13565: case 0xa6: { |
| 6925 | OPC_SwitchField, 15, 3, // 13568: switch Inst[17:15] { |
| 6926 | 4, 5, // 13571: case 0x4: { |
| 6927 | OPC_Decode, 191, 15, 135, 1, // 13573: decode to XVFRSTPI_B using decoder 135 |
| 6928 | // 13573: } |
| 6929 | 5, 0, // 13578: case 0x5: { |
| 6930 | OPC_Decode, 192, 15, 135, 1, // 13580: decode to XVFRSTPI_H using decoder 135 |
| 6931 | // 13580: } |
| 6932 | // 13580: } // switch Inst[17:15] |
| 6933 | // 13580: } |
| 6934 | 167, 1, 247, 6, // 13585: case 0xa7: { |
| 6935 | OPC_SwitchField, 15, 3, // 13589: switch Inst[17:15] { |
| 6936 | 0, 157, 1, // 13592: case 0x0: { |
| 6937 | OPC_SwitchField, 10, 5, // 13595: switch Inst[14:10] { |
| 6938 | 0, 5, // 13598: case 0x0: { |
| 6939 | OPC_Decode, 188, 14, 136, 1, // 13600: decode to XVCLO_B using decoder 136 |
| 6940 | // 13600: } |
| 6941 | 1, 5, // 13605: case 0x1: { |
| 6942 | OPC_Decode, 190, 14, 136, 1, // 13607: decode to XVCLO_H using decoder 136 |
| 6943 | // 13607: } |
| 6944 | 2, 5, // 13612: case 0x2: { |
| 6945 | OPC_Decode, 191, 14, 136, 1, // 13614: decode to XVCLO_W using decoder 136 |
| 6946 | // 13614: } |
| 6947 | 3, 5, // 13619: case 0x3: { |
| 6948 | OPC_Decode, 189, 14, 136, 1, // 13621: decode to XVCLO_D using decoder 136 |
| 6949 | // 13621: } |
| 6950 | 4, 5, // 13626: case 0x4: { |
| 6951 | OPC_Decode, 192, 14, 136, 1, // 13628: decode to XVCLZ_B using decoder 136 |
| 6952 | // 13628: } |
| 6953 | 5, 5, // 13633: case 0x5: { |
| 6954 | OPC_Decode, 194, 14, 136, 1, // 13635: decode to XVCLZ_H using decoder 136 |
| 6955 | // 13635: } |
| 6956 | 6, 5, // 13640: case 0x6: { |
| 6957 | OPC_Decode, 195, 14, 136, 1, // 13642: decode to XVCLZ_W using decoder 136 |
| 6958 | // 13642: } |
| 6959 | 7, 5, // 13647: case 0x7: { |
| 6960 | OPC_Decode, 193, 14, 136, 1, // 13649: decode to XVCLZ_D using decoder 136 |
| 6961 | // 13649: } |
| 6962 | 8, 5, // 13654: case 0x8: { |
| 6963 | OPC_Decode, 139, 17, 136, 1, // 13656: decode to XVPCNT_B using decoder 136 |
| 6964 | // 13656: } |
| 6965 | 9, 5, // 13661: case 0x9: { |
| 6966 | OPC_Decode, 141, 17, 136, 1, // 13663: decode to XVPCNT_H using decoder 136 |
| 6967 | // 13663: } |
| 6968 | 10, 5, // 13668: case 0xa: { |
| 6969 | OPC_Decode, 142, 17, 136, 1, // 13670: decode to XVPCNT_W using decoder 136 |
| 6970 | // 13670: } |
| 6971 | 11, 5, // 13675: case 0xb: { |
| 6972 | OPC_Decode, 140, 17, 136, 1, // 13677: decode to XVPCNT_D using decoder 136 |
| 6973 | // 13677: } |
| 6974 | 12, 5, // 13682: case 0xc: { |
| 6975 | OPC_Decode, 250, 16, 136, 1, // 13684: decode to XVNEG_B using decoder 136 |
| 6976 | // 13684: } |
| 6977 | 13, 5, // 13689: case 0xd: { |
| 6978 | OPC_Decode, 252, 16, 136, 1, // 13691: decode to XVNEG_H using decoder 136 |
| 6979 | // 13691: } |
| 6980 | 14, 5, // 13696: case 0xe: { |
| 6981 | OPC_Decode, 253, 16, 136, 1, // 13698: decode to XVNEG_W using decoder 136 |
| 6982 | // 13698: } |
| 6983 | 15, 5, // 13703: case 0xf: { |
| 6984 | OPC_Decode, 251, 16, 136, 1, // 13705: decode to XVNEG_D using decoder 136 |
| 6985 | // 13705: } |
| 6986 | 16, 5, // 13710: case 0x10: { |
| 6987 | OPC_Decode, 205, 16, 136, 1, // 13712: decode to XVMSKLTZ_B using decoder 136 |
| 6988 | // 13712: } |
| 6989 | 17, 5, // 13717: case 0x11: { |
| 6990 | OPC_Decode, 207, 16, 136, 1, // 13719: decode to XVMSKLTZ_H using decoder 136 |
| 6991 | // 13719: } |
| 6992 | 18, 5, // 13724: case 0x12: { |
| 6993 | OPC_Decode, 208, 16, 136, 1, // 13726: decode to XVMSKLTZ_W using decoder 136 |
| 6994 | // 13726: } |
| 6995 | 19, 5, // 13731: case 0x13: { |
| 6996 | OPC_Decode, 206, 16, 136, 1, // 13733: decode to XVMSKLTZ_D using decoder 136 |
| 6997 | // 13733: } |
| 6998 | 20, 5, // 13738: case 0x14: { |
| 6999 | OPC_Decode, 204, 16, 136, 1, // 13740: decode to XVMSKGEZ_B using decoder 136 |
| 7000 | // 13740: } |
| 7001 | 24, 0, // 13745: case 0x18: { |
| 7002 | OPC_Decode, 209, 16, 136, 1, // 13747: decode to XVMSKNZ_B using decoder 136 |
| 7003 | // 13747: } |
| 7004 | // 13747: } // switch Inst[14:10] |
| 7005 | // 13747: } |
| 7006 | 1, 169, 1, // 13752: case 0x1: { |
| 7007 | OPC_SwitchField, 10, 5, // 13755: switch Inst[14:10] { |
| 7008 | 6, 9, // 13758: case 0x6: { |
| 7009 | OPC_CheckField, 3, 2, 0, // 13760: check Inst[4:3] == 0x0 |
| 7010 | OPC_Decode, 218, 17, 137, 1, // 13764: decode to XVSETEQZ_V using decoder 137 |
| 7011 | // 13764: } |
| 7012 | 7, 9, // 13769: case 0x7: { |
| 7013 | OPC_CheckField, 3, 2, 0, // 13771: check Inst[4:3] == 0x0 |
| 7014 | OPC_Decode, 219, 17, 137, 1, // 13775: decode to XVSETNEZ_V using decoder 137 |
| 7015 | // 13775: } |
| 7016 | 8, 9, // 13780: case 0x8: { |
| 7017 | OPC_CheckField, 3, 2, 0, // 13782: check Inst[4:3] == 0x0 |
| 7018 | OPC_Decode, 214, 17, 137, 1, // 13786: decode to XVSETANYEQZ_B using decoder 137 |
| 7019 | // 13786: } |
| 7020 | 9, 9, // 13791: case 0x9: { |
| 7021 | OPC_CheckField, 3, 2, 0, // 13793: check Inst[4:3] == 0x0 |
| 7022 | OPC_Decode, 216, 17, 137, 1, // 13797: decode to XVSETANYEQZ_H using decoder 137 |
| 7023 | // 13797: } |
| 7024 | 10, 9, // 13802: case 0xa: { |
| 7025 | OPC_CheckField, 3, 2, 0, // 13804: check Inst[4:3] == 0x0 |
| 7026 | OPC_Decode, 217, 17, 137, 1, // 13808: decode to XVSETANYEQZ_W using decoder 137 |
| 7027 | // 13808: } |
| 7028 | 11, 9, // 13813: case 0xb: { |
| 7029 | OPC_CheckField, 3, 2, 0, // 13815: check Inst[4:3] == 0x0 |
| 7030 | OPC_Decode, 215, 17, 137, 1, // 13819: decode to XVSETANYEQZ_D using decoder 137 |
| 7031 | // 13819: } |
| 7032 | 12, 9, // 13824: case 0xc: { |
| 7033 | OPC_CheckField, 3, 2, 0, // 13826: check Inst[4:3] == 0x0 |
| 7034 | OPC_Decode, 210, 17, 137, 1, // 13830: decode to XVSETALLNEZ_B using decoder 137 |
| 7035 | // 13830: } |
| 7036 | 13, 9, // 13835: case 0xd: { |
| 7037 | OPC_CheckField, 3, 2, 0, // 13837: check Inst[4:3] == 0x0 |
| 7038 | OPC_Decode, 212, 17, 137, 1, // 13841: decode to XVSETALLNEZ_H using decoder 137 |
| 7039 | // 13841: } |
| 7040 | 14, 9, // 13846: case 0xe: { |
| 7041 | OPC_CheckField, 3, 2, 0, // 13848: check Inst[4:3] == 0x0 |
| 7042 | OPC_Decode, 213, 17, 137, 1, // 13852: decode to XVSETALLNEZ_W using decoder 137 |
| 7043 | // 13852: } |
| 7044 | 15, 9, // 13857: case 0xf: { |
| 7045 | OPC_CheckField, 3, 2, 0, // 13859: check Inst[4:3] == 0x0 |
| 7046 | OPC_Decode, 211, 17, 137, 1, // 13863: decode to XVSETALLNEZ_D using decoder 137 |
| 7047 | // 13863: } |
| 7048 | 17, 5, // 13868: case 0x11: { |
| 7049 | OPC_Decode, 154, 15, 136, 1, // 13870: decode to XVFLOGB_S using decoder 136 |
| 7050 | // 13870: } |
| 7051 | 18, 5, // 13875: case 0x12: { |
| 7052 | OPC_Decode, 153, 15, 136, 1, // 13877: decode to XVFLOGB_D using decoder 136 |
| 7053 | // 13877: } |
| 7054 | 21, 5, // 13882: case 0x15: { |
| 7055 | OPC_Decode, 221, 14, 136, 1, // 13884: decode to XVFCLASS_S using decoder 136 |
| 7056 | // 13884: } |
| 7057 | 22, 5, // 13889: case 0x16: { |
| 7058 | OPC_Decode, 220, 14, 136, 1, // 13891: decode to XVFCLASS_D using decoder 136 |
| 7059 | // 13891: } |
| 7060 | 25, 5, // 13896: case 0x19: { |
| 7061 | OPC_Decode, 196, 15, 136, 1, // 13898: decode to XVFSQRT_S using decoder 136 |
| 7062 | // 13898: } |
| 7063 | 26, 5, // 13903: case 0x1a: { |
| 7064 | OPC_Decode, 195, 15, 136, 1, // 13905: decode to XVFSQRT_D using decoder 136 |
| 7065 | // 13905: } |
| 7066 | 29, 5, // 13910: case 0x1d: { |
| 7067 | OPC_Decode, 176, 15, 136, 1, // 13912: decode to XVFRECIP_S using decoder 136 |
| 7068 | // 13912: } |
| 7069 | 30, 0, // 13917: case 0x1e: { |
| 7070 | OPC_Decode, 175, 15, 136, 1, // 13919: decode to XVFRECIP_D using decoder 136 |
| 7071 | // 13919: } |
| 7072 | // 13919: } // switch Inst[14:10] |
| 7073 | // 13919: } |
| 7074 | 2, 115, // 13924: case 0x2: { |
| 7075 | OPC_SwitchField, 10, 5, // 13926: switch Inst[14:10] { |
| 7076 | 1, 5, // 13929: case 0x1: { |
| 7077 | OPC_Decode, 190, 15, 136, 1, // 13931: decode to XVFRSQRT_S using decoder 136 |
| 7078 | // 13931: } |
| 7079 | 2, 5, // 13936: case 0x2: { |
| 7080 | OPC_Decode, 189, 15, 136, 1, // 13938: decode to XVFRSQRT_D using decoder 136 |
| 7081 | // 13938: } |
| 7082 | 5, 5, // 13943: case 0x5: { |
| 7083 | OPC_Decode, 174, 15, 136, 1, // 13945: decode to XVFRECIPE_S using decoder 136 |
| 7084 | // 13945: } |
| 7085 | 6, 5, // 13950: case 0x6: { |
| 7086 | OPC_Decode, 173, 15, 136, 1, // 13952: decode to XVFRECIPE_D using decoder 136 |
| 7087 | // 13952: } |
| 7088 | 9, 5, // 13957: case 0x9: { |
| 7089 | OPC_Decode, 188, 15, 136, 1, // 13959: decode to XVFRSQRTE_S using decoder 136 |
| 7090 | // 13959: } |
| 7091 | 10, 5, // 13964: case 0xa: { |
| 7092 | OPC_Decode, 187, 15, 136, 1, // 13966: decode to XVFRSQRTE_D using decoder 136 |
| 7093 | // 13966: } |
| 7094 | 13, 5, // 13971: case 0xd: { |
| 7095 | OPC_Decode, 186, 15, 136, 1, // 13973: decode to XVFRINT_S using decoder 136 |
| 7096 | // 13973: } |
| 7097 | 14, 5, // 13978: case 0xe: { |
| 7098 | OPC_Decode, 185, 15, 136, 1, // 13980: decode to XVFRINT_D using decoder 136 |
| 7099 | // 13980: } |
| 7100 | 17, 5, // 13985: case 0x11: { |
| 7101 | OPC_Decode, 178, 15, 136, 1, // 13987: decode to XVFRINTRM_S using decoder 136 |
| 7102 | // 13987: } |
| 7103 | 18, 5, // 13992: case 0x12: { |
| 7104 | OPC_Decode, 177, 15, 136, 1, // 13994: decode to XVFRINTRM_D using decoder 136 |
| 7105 | // 13994: } |
| 7106 | 21, 5, // 13999: case 0x15: { |
| 7107 | OPC_Decode, 182, 15, 136, 1, // 14001: decode to XVFRINTRP_S using decoder 136 |
| 7108 | // 14001: } |
| 7109 | 22, 5, // 14006: case 0x16: { |
| 7110 | OPC_Decode, 181, 15, 136, 1, // 14008: decode to XVFRINTRP_D using decoder 136 |
| 7111 | // 14008: } |
| 7112 | 25, 5, // 14013: case 0x19: { |
| 7113 | OPC_Decode, 184, 15, 136, 1, // 14015: decode to XVFRINTRZ_S using decoder 136 |
| 7114 | // 14015: } |
| 7115 | 26, 5, // 14020: case 0x1a: { |
| 7116 | OPC_Decode, 183, 15, 136, 1, // 14022: decode to XVFRINTRZ_D using decoder 136 |
| 7117 | // 14022: } |
| 7118 | 29, 5, // 14027: case 0x1d: { |
| 7119 | OPC_Decode, 180, 15, 136, 1, // 14029: decode to XVFRINTRNE_S using decoder 136 |
| 7120 | // 14029: } |
| 7121 | 30, 0, // 14034: case 0x1e: { |
| 7122 | OPC_Decode, 179, 15, 136, 1, // 14036: decode to XVFRINTRNE_D using decoder 136 |
| 7123 | // 14036: } |
| 7124 | // 14036: } // switch Inst[14:10] |
| 7125 | // 14036: } |
| 7126 | 3, 31, // 14041: case 0x3: { |
| 7127 | OPC_SwitchField, 10, 5, // 14043: switch Inst[14:10] { |
| 7128 | 26, 5, // 14046: case 0x1a: { |
| 7129 | OPC_Decode, 141, 15, 136, 1, // 14048: decode to XVFCVTL_S_H using decoder 136 |
| 7130 | // 14048: } |
| 7131 | 27, 5, // 14053: case 0x1b: { |
| 7132 | OPC_Decode, 139, 15, 136, 1, // 14055: decode to XVFCVTH_S_H using decoder 136 |
| 7133 | // 14055: } |
| 7134 | 28, 5, // 14060: case 0x1c: { |
| 7135 | OPC_Decode, 140, 15, 136, 1, // 14062: decode to XVFCVTL_D_S using decoder 136 |
| 7136 | // 14062: } |
| 7137 | 29, 0, // 14067: case 0x1d: { |
| 7138 | OPC_Decode, 138, 15, 136, 1, // 14069: decode to XVFCVTH_D_S using decoder 136 |
| 7139 | // 14069: } |
| 7140 | // 14069: } // switch Inst[14:10] |
| 7141 | // 14069: } |
| 7142 | 4, 143, 1, // 14074: case 0x4: { |
| 7143 | OPC_SwitchField, 10, 5, // 14077: switch Inst[14:10] { |
| 7144 | 0, 5, // 14080: case 0x0: { |
| 7145 | OPC_Decode, 151, 15, 136, 1, // 14082: decode to XVFFINT_S_W using decoder 136 |
| 7146 | // 14082: } |
| 7147 | 1, 5, // 14087: case 0x1: { |
| 7148 | OPC_Decode, 152, 15, 136, 1, // 14089: decode to XVFFINT_S_WU using decoder 136 |
| 7149 | // 14089: } |
| 7150 | 2, 5, // 14094: case 0x2: { |
| 7151 | OPC_Decode, 148, 15, 136, 1, // 14096: decode to XVFFINT_D_L using decoder 136 |
| 7152 | // 14096: } |
| 7153 | 3, 5, // 14101: case 0x3: { |
| 7154 | OPC_Decode, 149, 15, 136, 1, // 14103: decode to XVFFINT_D_LU using decoder 136 |
| 7155 | // 14103: } |
| 7156 | 4, 5, // 14108: case 0x4: { |
| 7157 | OPC_Decode, 147, 15, 136, 1, // 14110: decode to XVFFINTL_D_W using decoder 136 |
| 7158 | // 14110: } |
| 7159 | 5, 5, // 14115: case 0x5: { |
| 7160 | OPC_Decode, 146, 15, 136, 1, // 14117: decode to XVFFINTH_D_W using decoder 136 |
| 7161 | // 14117: } |
| 7162 | 12, 5, // 14122: case 0xc: { |
| 7163 | OPC_Decode, 227, 15, 136, 1, // 14124: decode to XVFTINT_W_S using decoder 136 |
| 7164 | // 14124: } |
| 7165 | 13, 5, // 14129: case 0xd: { |
| 7166 | OPC_Decode, 224, 15, 136, 1, // 14131: decode to XVFTINT_L_D using decoder 136 |
| 7167 | // 14131: } |
| 7168 | 14, 5, // 14136: case 0xe: { |
| 7169 | OPC_Decode, 205, 15, 136, 1, // 14138: decode to XVFTINTRM_W_S using decoder 136 |
| 7170 | // 14138: } |
| 7171 | 15, 5, // 14143: case 0xf: { |
| 7172 | OPC_Decode, 203, 15, 136, 1, // 14145: decode to XVFTINTRM_L_D using decoder 136 |
| 7173 | // 14145: } |
| 7174 | 16, 5, // 14150: case 0x10: { |
| 7175 | OPC_Decode, 215, 15, 136, 1, // 14152: decode to XVFTINTRP_W_S using decoder 136 |
| 7176 | // 14152: } |
| 7177 | 17, 5, // 14157: case 0x11: { |
| 7178 | OPC_Decode, 213, 15, 136, 1, // 14159: decode to XVFTINTRP_L_D using decoder 136 |
| 7179 | // 14159: } |
| 7180 | 18, 5, // 14164: case 0x12: { |
| 7181 | OPC_Decode, 222, 15, 136, 1, // 14166: decode to XVFTINTRZ_W_S using decoder 136 |
| 7182 | // 14166: } |
| 7183 | 19, 5, // 14171: case 0x13: { |
| 7184 | OPC_Decode, 219, 15, 136, 1, // 14173: decode to XVFTINTRZ_L_D using decoder 136 |
| 7185 | // 14173: } |
| 7186 | 20, 5, // 14178: case 0x14: { |
| 7187 | OPC_Decode, 210, 15, 136, 1, // 14180: decode to XVFTINTRNE_W_S using decoder 136 |
| 7188 | // 14180: } |
| 7189 | 21, 5, // 14185: case 0x15: { |
| 7190 | OPC_Decode, 208, 15, 136, 1, // 14187: decode to XVFTINTRNE_L_D using decoder 136 |
| 7191 | // 14187: } |
| 7192 | 22, 5, // 14192: case 0x16: { |
| 7193 | OPC_Decode, 225, 15, 136, 1, // 14194: decode to XVFTINT_WU_S using decoder 136 |
| 7194 | // 14194: } |
| 7195 | 23, 5, // 14199: case 0x17: { |
| 7196 | OPC_Decode, 223, 15, 136, 1, // 14201: decode to XVFTINT_LU_D using decoder 136 |
| 7197 | // 14201: } |
| 7198 | 28, 5, // 14206: case 0x1c: { |
| 7199 | OPC_Decode, 220, 15, 136, 1, // 14208: decode to XVFTINTRZ_WU_S using decoder 136 |
| 7200 | // 14208: } |
| 7201 | 29, 0, // 14213: case 0x1d: { |
| 7202 | OPC_Decode, 218, 15, 136, 1, // 14215: decode to XVFTINTRZ_LU_D using decoder 136 |
| 7203 | // 14215: } |
| 7204 | // 14215: } // switch Inst[14:10] |
| 7205 | // 14215: } |
| 7206 | 5, 129, 1, // 14220: case 0x5: { |
| 7207 | OPC_SwitchField, 10, 5, // 14223: switch Inst[14:10] { |
| 7208 | 0, 5, // 14226: case 0x0: { |
| 7209 | OPC_Decode, 200, 15, 136, 1, // 14228: decode to XVFTINTL_L_S using decoder 136 |
| 7210 | // 14228: } |
| 7211 | 1, 5, // 14233: case 0x1: { |
| 7212 | OPC_Decode, 199, 15, 136, 1, // 14235: decode to XVFTINTH_L_S using decoder 136 |
| 7213 | // 14235: } |
| 7214 | 2, 5, // 14240: case 0x2: { |
| 7215 | OPC_Decode, 202, 15, 136, 1, // 14242: decode to XVFTINTRML_L_S using decoder 136 |
| 7216 | // 14242: } |
| 7217 | 3, 5, // 14247: case 0x3: { |
| 7218 | OPC_Decode, 201, 15, 136, 1, // 14249: decode to XVFTINTRMH_L_S using decoder 136 |
| 7219 | // 14249: } |
| 7220 | 4, 5, // 14254: case 0x4: { |
| 7221 | OPC_Decode, 212, 15, 136, 1, // 14256: decode to XVFTINTRPL_L_S using decoder 136 |
| 7222 | // 14256: } |
| 7223 | 5, 5, // 14261: case 0x5: { |
| 7224 | OPC_Decode, 211, 15, 136, 1, // 14263: decode to XVFTINTRPH_L_S using decoder 136 |
| 7225 | // 14263: } |
| 7226 | 6, 5, // 14268: case 0x6: { |
| 7227 | OPC_Decode, 217, 15, 136, 1, // 14270: decode to XVFTINTRZL_L_S using decoder 136 |
| 7228 | // 14270: } |
| 7229 | 7, 5, // 14275: case 0x7: { |
| 7230 | OPC_Decode, 216, 15, 136, 1, // 14277: decode to XVFTINTRZH_L_S using decoder 136 |
| 7231 | // 14277: } |
| 7232 | 8, 5, // 14282: case 0x8: { |
| 7233 | OPC_Decode, 207, 15, 136, 1, // 14284: decode to XVFTINTRNEL_L_S using decoder 136 |
| 7234 | // 14284: } |
| 7235 | 9, 5, // 14289: case 0x9: { |
| 7236 | OPC_Decode, 206, 15, 136, 1, // 14291: decode to XVFTINTRNEH_L_S using decoder 136 |
| 7237 | // 14291: } |
| 7238 | 24, 5, // 14296: case 0x18: { |
| 7239 | OPC_Decode, 207, 14, 136, 1, // 14298: decode to XVEXTH_H_B using decoder 136 |
| 7240 | // 14298: } |
| 7241 | 25, 5, // 14303: case 0x19: { |
| 7242 | OPC_Decode, 211, 14, 136, 1, // 14305: decode to XVEXTH_W_H using decoder 136 |
| 7243 | // 14305: } |
| 7244 | 26, 5, // 14310: case 0x1a: { |
| 7245 | OPC_Decode, 205, 14, 136, 1, // 14312: decode to XVEXTH_D_W using decoder 136 |
| 7246 | // 14312: } |
| 7247 | 27, 5, // 14317: case 0x1b: { |
| 7248 | OPC_Decode, 209, 14, 136, 1, // 14319: decode to XVEXTH_Q_D using decoder 136 |
| 7249 | // 14319: } |
| 7250 | 28, 5, // 14324: case 0x1c: { |
| 7251 | OPC_Decode, 206, 14, 136, 1, // 14326: decode to XVEXTH_HU_BU using decoder 136 |
| 7252 | // 14326: } |
| 7253 | 29, 5, // 14331: case 0x1d: { |
| 7254 | OPC_Decode, 210, 14, 136, 1, // 14333: decode to XVEXTH_WU_HU using decoder 136 |
| 7255 | // 14333: } |
| 7256 | 30, 5, // 14338: case 0x1e: { |
| 7257 | OPC_Decode, 204, 14, 136, 1, // 14340: decode to XVEXTH_DU_WU using decoder 136 |
| 7258 | // 14340: } |
| 7259 | 31, 0, // 14345: case 0x1f: { |
| 7260 | OPC_Decode, 208, 14, 136, 1, // 14347: decode to XVEXTH_QU_DU using decoder 136 |
| 7261 | // 14347: } |
| 7262 | // 14347: } // switch Inst[14:10] |
| 7263 | // 14347: } |
| 7264 | 6, 115, // 14352: case 0x6: { |
| 7265 | OPC_SwitchField, 10, 5, // 14354: switch Inst[14:10] { |
| 7266 | 0, 5, // 14357: case 0x0: { |
| 7267 | OPC_Decode, 165, 17, 138, 1, // 14359: decode to XVREPLGR2VR_B using decoder 138 |
| 7268 | // 14359: } |
| 7269 | 1, 5, // 14364: case 0x1: { |
| 7270 | OPC_Decode, 167, 17, 138, 1, // 14366: decode to XVREPLGR2VR_H using decoder 138 |
| 7271 | // 14366: } |
| 7272 | 2, 5, // 14371: case 0x2: { |
| 7273 | OPC_Decode, 168, 17, 138, 1, // 14373: decode to XVREPLGR2VR_W using decoder 138 |
| 7274 | // 14373: } |
| 7275 | 3, 5, // 14378: case 0x3: { |
| 7276 | OPC_Decode, 166, 17, 138, 1, // 14380: decode to XVREPLGR2VR_D using decoder 138 |
| 7277 | // 14380: } |
| 7278 | 4, 5, // 14385: case 0x4: { |
| 7279 | OPC_Decode, 136, 8, 136, 1, // 14387: decode to VEXT2XV_H_B using decoder 136 |
| 7280 | // 14387: } |
| 7281 | 5, 5, // 14392: case 0x5: { |
| 7282 | OPC_Decode, 139, 8, 136, 1, // 14394: decode to VEXT2XV_W_B using decoder 136 |
| 7283 | // 14394: } |
| 7284 | 6, 5, // 14399: case 0x6: { |
| 7285 | OPC_Decode, 132, 8, 136, 1, // 14401: decode to VEXT2XV_D_B using decoder 136 |
| 7286 | // 14401: } |
| 7287 | 7, 5, // 14406: case 0x7: { |
| 7288 | OPC_Decode, 140, 8, 136, 1, // 14408: decode to VEXT2XV_W_H using decoder 136 |
| 7289 | // 14408: } |
| 7290 | 8, 5, // 14413: case 0x8: { |
| 7291 | OPC_Decode, 133, 8, 136, 1, // 14415: decode to VEXT2XV_D_H using decoder 136 |
| 7292 | // 14415: } |
| 7293 | 9, 5, // 14420: case 0x9: { |
| 7294 | OPC_Decode, 134, 8, 136, 1, // 14422: decode to VEXT2XV_D_W using decoder 136 |
| 7295 | // 14422: } |
| 7296 | 10, 5, // 14427: case 0xa: { |
| 7297 | OPC_Decode, 135, 8, 136, 1, // 14429: decode to VEXT2XV_HU_BU using decoder 136 |
| 7298 | // 14429: } |
| 7299 | 11, 5, // 14434: case 0xb: { |
| 7300 | OPC_Decode, 137, 8, 136, 1, // 14436: decode to VEXT2XV_WU_BU using decoder 136 |
| 7301 | // 14436: } |
| 7302 | 12, 5, // 14441: case 0xc: { |
| 7303 | OPC_Decode, 129, 8, 136, 1, // 14443: decode to VEXT2XV_DU_BU using decoder 136 |
| 7304 | // 14443: } |
| 7305 | 13, 5, // 14448: case 0xd: { |
| 7306 | OPC_Decode, 138, 8, 136, 1, // 14450: decode to VEXT2XV_WU_HU using decoder 136 |
| 7307 | // 14450: } |
| 7308 | 14, 5, // 14455: case 0xe: { |
| 7309 | OPC_Decode, 130, 8, 136, 1, // 14457: decode to VEXT2XV_DU_HU using decoder 136 |
| 7310 | // 14457: } |
| 7311 | 15, 0, // 14462: case 0xf: { |
| 7312 | OPC_Decode, 131, 8, 136, 1, // 14464: decode to VEXT2XV_DU_WU using decoder 136 |
| 7313 | // 14464: } |
| 7314 | // 14464: } // switch Inst[14:10] |
| 7315 | // 14464: } |
| 7316 | 7, 0, // 14469: case 0x7: { |
| 7317 | OPC_Decode, 236, 15, 134, 1, // 14471: decode to XVHSELI_D using decoder 134 |
| 7318 | // 14471: } |
| 7319 | // 14471: } // switch Inst[17:15] |
| 7320 | // 14471: } |
| 7321 | 168, 1, 45, // 14476: case 0xa8: { |
| 7322 | OPC_SwitchField, 16, 2, // 14479: switch Inst[17:16] { |
| 7323 | 0, 33, // 14482: case 0x0: { |
| 7324 | OPC_SwitchField, 15, 1, // 14484: switch Inst[15] { |
| 7325 | 0, 21, // 14487: case 0x0: { |
| 7326 | OPC_SwitchField, 14, 1, // 14489: switch Inst[14] { |
| 7327 | 0, 9, // 14492: case 0x0: { |
| 7328 | OPC_CheckField, 13, 1, 1, // 14494: check Inst[13] == 0x1 |
| 7329 | OPC_Decode, 178, 17, 139, 1, // 14498: decode to XVROTRI_B using decoder 139 |
| 7330 | // 14498: } |
| 7331 | 1, 0, // 14503: case 0x1: { |
| 7332 | OPC_Decode, 180, 17, 140, 1, // 14505: decode to XVROTRI_H using decoder 140 |
| 7333 | // 14505: } |
| 7334 | // 14505: } // switch Inst[14] |
| 7335 | // 14505: } |
| 7336 | 1, 0, // 14510: case 0x1: { |
| 7337 | OPC_Decode, 181, 17, 134, 1, // 14512: decode to XVROTRI_W using decoder 134 |
| 7338 | // 14512: } |
| 7339 | // 14512: } // switch Inst[15] |
| 7340 | // 14512: } |
| 7341 | 1, 0, // 14517: case 0x1: { |
| 7342 | OPC_Decode, 179, 17, 141, 1, // 14519: decode to XVROTRI_D using decoder 141 |
| 7343 | // 14519: } |
| 7344 | // 14519: } // switch Inst[17:16] |
| 7345 | // 14519: } |
| 7346 | 169, 1, 45, // 14524: case 0xa9: { |
| 7347 | OPC_SwitchField, 16, 2, // 14527: switch Inst[17:16] { |
| 7348 | 0, 33, // 14530: case 0x0: { |
| 7349 | OPC_SwitchField, 15, 1, // 14532: switch Inst[15] { |
| 7350 | 0, 21, // 14535: case 0x0: { |
| 7351 | OPC_SwitchField, 14, 1, // 14537: switch Inst[14] { |
| 7352 | 0, 9, // 14540: case 0x0: { |
| 7353 | OPC_CheckField, 13, 1, 1, // 14542: check Inst[13] == 0x1 |
| 7354 | OPC_Decode, 191, 18, 139, 1, // 14546: decode to XVSRLRI_B using decoder 139 |
| 7355 | // 14546: } |
| 7356 | 1, 0, // 14551: case 0x1: { |
| 7357 | OPC_Decode, 193, 18, 140, 1, // 14553: decode to XVSRLRI_H using decoder 140 |
| 7358 | // 14553: } |
| 7359 | // 14553: } // switch Inst[14] |
| 7360 | // 14553: } |
| 7361 | 1, 0, // 14558: case 0x1: { |
| 7362 | OPC_Decode, 194, 18, 134, 1, // 14560: decode to XVSRLRI_W using decoder 134 |
| 7363 | // 14560: } |
| 7364 | // 14560: } // switch Inst[15] |
| 7365 | // 14560: } |
| 7366 | 1, 0, // 14565: case 0x1: { |
| 7367 | OPC_Decode, 192, 18, 141, 1, // 14567: decode to XVSRLRI_D using decoder 141 |
| 7368 | // 14567: } |
| 7369 | // 14567: } // switch Inst[17:16] |
| 7370 | // 14567: } |
| 7371 | 170, 1, 45, // 14572: case 0xaa: { |
| 7372 | OPC_SwitchField, 16, 2, // 14575: switch Inst[17:16] { |
| 7373 | 0, 33, // 14578: case 0x0: { |
| 7374 | OPC_SwitchField, 15, 1, // 14580: switch Inst[15] { |
| 7375 | 0, 21, // 14583: case 0x0: { |
| 7376 | OPC_SwitchField, 14, 1, // 14585: switch Inst[14] { |
| 7377 | 0, 9, // 14588: case 0x0: { |
| 7378 | OPC_CheckField, 13, 1, 1, // 14590: check Inst[13] == 0x1 |
| 7379 | OPC_Decode, 161, 18, 139, 1, // 14594: decode to XVSRARI_B using decoder 139 |
| 7380 | // 14594: } |
| 7381 | 1, 0, // 14599: case 0x1: { |
| 7382 | OPC_Decode, 163, 18, 140, 1, // 14601: decode to XVSRARI_H using decoder 140 |
| 7383 | // 14601: } |
| 7384 | // 14601: } // switch Inst[14] |
| 7385 | // 14601: } |
| 7386 | 1, 0, // 14606: case 0x1: { |
| 7387 | OPC_Decode, 164, 18, 134, 1, // 14608: decode to XVSRARI_W using decoder 134 |
| 7388 | // 14608: } |
| 7389 | // 14608: } // switch Inst[15] |
| 7390 | // 14608: } |
| 7391 | 1, 0, // 14613: case 0x1: { |
| 7392 | OPC_Decode, 162, 18, 141, 1, // 14615: decode to XVSRARI_D using decoder 141 |
| 7393 | // 14615: } |
| 7394 | // 14615: } // switch Inst[17:16] |
| 7395 | // 14615: } |
| 7396 | 186, 1, 21, // 14620: case 0xba: { |
| 7397 | OPC_SwitchField, 13, 5, // 14623: switch Inst[17:13] { |
| 7398 | 30, 5, // 14626: case 0x1e: { |
| 7399 | OPC_Decode, 254, 15, 142, 1, // 14628: decode to XVINSGR2VR_W using decoder 142 |
| 7400 | // 14628: } |
| 7401 | 31, 0, // 14633: case 0x1f: { |
| 7402 | OPC_CheckField, 12, 1, 0, // 14635: check Inst[12] == 0x0 |
| 7403 | OPC_Decode, 253, 15, 143, 1, // 14639: decode to XVINSGR2VR_D using decoder 143 |
| 7404 | // 14639: } |
| 7405 | // 14639: } // switch Inst[17:13] |
| 7406 | // 14639: } |
| 7407 | 187, 1, 21, // 14644: case 0xbb: { |
| 7408 | OPC_SwitchField, 13, 5, // 14647: switch Inst[17:13] { |
| 7409 | 30, 5, // 14650: case 0x1e: { |
| 7410 | OPC_Decode, 157, 17, 144, 1, // 14652: decode to XVPICKVE2GR_W using decoder 144 |
| 7411 | // 14652: } |
| 7412 | 31, 0, // 14657: case 0x1f: { |
| 7413 | OPC_CheckField, 12, 1, 0, // 14659: check Inst[12] == 0x0 |
| 7414 | OPC_Decode, 155, 17, 145, 1, // 14663: decode to XVPICKVE2GR_D using decoder 145 |
| 7415 | // 14663: } |
| 7416 | // 14663: } // switch Inst[17:13] |
| 7417 | // 14663: } |
| 7418 | 188, 1, 21, // 14668: case 0xbc: { |
| 7419 | OPC_SwitchField, 13, 5, // 14671: switch Inst[17:13] { |
| 7420 | 30, 5, // 14674: case 0x1e: { |
| 7421 | OPC_Decode, 158, 17, 144, 1, // 14676: decode to XVPICKVE2GR_WU using decoder 144 |
| 7422 | // 14676: } |
| 7423 | 31, 0, // 14681: case 0x1f: { |
| 7424 | OPC_CheckField, 12, 1, 0, // 14683: check Inst[12] == 0x0 |
| 7425 | OPC_Decode, 156, 17, 145, 1, // 14687: decode to XVPICKVE2GR_DU using decoder 145 |
| 7426 | // 14687: } |
| 7427 | // 14687: } // switch Inst[17:13] |
| 7428 | // 14687: } |
| 7429 | 189, 1, 45, // 14692: case 0xbd: { |
| 7430 | OPC_SwitchField, 14, 4, // 14695: switch Inst[17:14] { |
| 7431 | 14, 5, // 14698: case 0xe: { |
| 7432 | OPC_Decode, 161, 17, 140, 1, // 14700: decode to XVREPL128VEI_B using decoder 140 |
| 7433 | // 14700: } |
| 7434 | 15, 0, // 14705: case 0xf: { |
| 7435 | OPC_SwitchField, 13, 1, // 14707: switch Inst[13] { |
| 7436 | 0, 5, // 14710: case 0x0: { |
| 7437 | OPC_Decode, 163, 17, 139, 1, // 14712: decode to XVREPL128VEI_H using decoder 139 |
| 7438 | // 14712: } |
| 7439 | 1, 0, // 14717: case 0x1: { |
| 7440 | OPC_SwitchField, 12, 1, // 14719: switch Inst[12] { |
| 7441 | 0, 5, // 14722: case 0x0: { |
| 7442 | OPC_Decode, 164, 17, 146, 1, // 14724: decode to XVREPL128VEI_W using decoder 146 |
| 7443 | // 14724: } |
| 7444 | 1, 0, // 14729: case 0x1: { |
| 7445 | OPC_CheckField, 11, 1, 0, // 14731: check Inst[11] == 0x0 |
| 7446 | OPC_Decode, 162, 17, 147, 1, // 14735: decode to XVREPL128VEI_D using decoder 147 |
| 7447 | // 14735: } |
| 7448 | // 14735: } // switch Inst[12] |
| 7449 | // 14735: } |
| 7450 | // 14735: } // switch Inst[13] |
| 7451 | // 14735: } |
| 7452 | // 14735: } // switch Inst[17:14] |
| 7453 | // 14735: } |
| 7454 | 191, 1, 21, // 14740: case 0xbf: { |
| 7455 | OPC_SwitchField, 13, 5, // 14743: switch Inst[17:13] { |
| 7456 | 30, 5, // 14746: case 0x1e: { |
| 7457 | OPC_Decode, 128, 16, 148, 1, // 14748: decode to XVINSVE0_W using decoder 148 |
| 7458 | // 14748: } |
| 7459 | 31, 0, // 14753: case 0x1f: { |
| 7460 | OPC_CheckField, 12, 1, 0, // 14755: check Inst[12] == 0x0 |
| 7461 | OPC_Decode, 255, 15, 149, 1, // 14759: decode to XVINSVE0_D using decoder 149 |
| 7462 | // 14759: } |
| 7463 | // 14759: } // switch Inst[17:13] |
| 7464 | // 14759: } |
| 7465 | 192, 1, 21, // 14764: case 0xc0: { |
| 7466 | OPC_SwitchField, 13, 5, // 14767: switch Inst[17:13] { |
| 7467 | 30, 5, // 14770: case 0x1e: { |
| 7468 | OPC_Decode, 160, 17, 139, 1, // 14772: decode to XVPICKVE_W using decoder 139 |
| 7469 | // 14772: } |
| 7470 | 31, 0, // 14777: case 0x1f: { |
| 7471 | OPC_CheckField, 12, 1, 0, // 14779: check Inst[12] == 0x0 |
| 7472 | OPC_Decode, 159, 17, 146, 1, // 14783: decode to XVPICKVE_D using decoder 146 |
| 7473 | // 14783: } |
| 7474 | // 14783: } // switch Inst[17:13] |
| 7475 | // 14783: } |
| 7476 | 193, 1, 43, // 14788: case 0xc1: { |
| 7477 | OPC_SwitchField, 10, 8, // 14791: switch Inst[17:10] { |
| 7478 | 192, 1, 5, // 14794: case 0xc0: { |
| 7479 | OPC_Decode, 169, 17, 136, 1, // 14797: decode to XVREPLVE0_B using decoder 136 |
| 7480 | // 14797: } |
| 7481 | 224, 1, 5, // 14802: case 0xe0: { |
| 7482 | OPC_Decode, 171, 17, 136, 1, // 14805: decode to XVREPLVE0_H using decoder 136 |
| 7483 | // 14805: } |
| 7484 | 240, 1, 5, // 14810: case 0xf0: { |
| 7485 | OPC_Decode, 173, 17, 136, 1, // 14813: decode to XVREPLVE0_W using decoder 136 |
| 7486 | // 14813: } |
| 7487 | 248, 1, 5, // 14818: case 0xf8: { |
| 7488 | OPC_Decode, 170, 17, 136, 1, // 14821: decode to XVREPLVE0_D using decoder 136 |
| 7489 | // 14821: } |
| 7490 | 252, 1, 0, // 14826: case 0xfc: { |
| 7491 | OPC_Decode, 172, 17, 136, 1, // 14829: decode to XVREPLVE0_Q using decoder 136 |
| 7492 | // 14829: } |
| 7493 | // 14829: } // switch Inst[17:10] |
| 7494 | // 14829: } |
| 7495 | 194, 1, 44, // 14834: case 0xc2: { |
| 7496 | OPC_SwitchField, 15, 3, // 14837: switch Inst[17:15] { |
| 7497 | 0, 21, // 14840: case 0x0: { |
| 7498 | OPC_SwitchField, 14, 1, // 14842: switch Inst[14] { |
| 7499 | 0, 9, // 14845: case 0x0: { |
| 7500 | OPC_CheckField, 13, 1, 1, // 14847: check Inst[13] == 0x1 |
| 7501 | OPC_Decode, 255, 17, 139, 1, // 14851: decode to XVSLLWIL_H_B using decoder 139 |
| 7502 | // 14851: } |
| 7503 | 1, 0, // 14856: case 0x1: { |
| 7504 | OPC_Decode, 129, 18, 140, 1, // 14858: decode to XVSLLWIL_W_H using decoder 140 |
| 7505 | // 14858: } |
| 7506 | // 14858: } // switch Inst[14] |
| 7507 | // 14858: } |
| 7508 | 1, 5, // 14863: case 0x1: { |
| 7509 | OPC_Decode, 253, 17, 134, 1, // 14865: decode to XVSLLWIL_D_W using decoder 134 |
| 7510 | // 14865: } |
| 7511 | 2, 0, // 14870: case 0x2: { |
| 7512 | OPC_CheckField, 10, 5, 0, // 14872: check Inst[14:10] == 0x0 |
| 7513 | OPC_Decode, 213, 14, 136, 1, // 14876: decode to XVEXTL_Q_D using decoder 136 |
| 7514 | // 14876: } |
| 7515 | // 14876: } // switch Inst[17:15] |
| 7516 | // 14876: } |
| 7517 | 195, 1, 44, // 14881: case 0xc3: { |
| 7518 | OPC_SwitchField, 15, 3, // 14884: switch Inst[17:15] { |
| 7519 | 0, 21, // 14887: case 0x0: { |
| 7520 | OPC_SwitchField, 14, 1, // 14889: switch Inst[14] { |
| 7521 | 0, 9, // 14892: case 0x0: { |
| 7522 | OPC_CheckField, 13, 1, 1, // 14894: check Inst[13] == 0x1 |
| 7523 | OPC_Decode, 254, 17, 139, 1, // 14898: decode to XVSLLWIL_HU_BU using decoder 139 |
| 7524 | // 14898: } |
| 7525 | 1, 0, // 14903: case 0x1: { |
| 7526 | OPC_Decode, 128, 18, 140, 1, // 14905: decode to XVSLLWIL_WU_HU using decoder 140 |
| 7527 | // 14905: } |
| 7528 | // 14905: } // switch Inst[14] |
| 7529 | // 14905: } |
| 7530 | 1, 5, // 14910: case 0x1: { |
| 7531 | OPC_Decode, 252, 17, 134, 1, // 14912: decode to XVSLLWIL_DU_WU using decoder 134 |
| 7532 | // 14912: } |
| 7533 | 2, 0, // 14917: case 0x2: { |
| 7534 | OPC_CheckField, 10, 5, 0, // 14919: check Inst[14:10] == 0x0 |
| 7535 | OPC_Decode, 212, 14, 136, 1, // 14923: decode to XVEXTL_QU_DU using decoder 136 |
| 7536 | // 14923: } |
| 7537 | // 14923: } // switch Inst[17:15] |
| 7538 | // 14923: } |
| 7539 | 196, 1, 45, // 14928: case 0xc4: { |
| 7540 | OPC_SwitchField, 16, 2, // 14931: switch Inst[17:16] { |
| 7541 | 0, 33, // 14934: case 0x0: { |
| 7542 | OPC_SwitchField, 15, 1, // 14936: switch Inst[15] { |
| 7543 | 0, 21, // 14939: case 0x0: { |
| 7544 | OPC_SwitchField, 14, 1, // 14941: switch Inst[14] { |
| 7545 | 0, 9, // 14944: case 0x0: { |
| 7546 | OPC_CheckField, 13, 1, 1, // 14946: check Inst[13] == 0x1 |
| 7547 | OPC_Decode, 160, 14, 139, 1, // 14950: decode to XVBITCLRI_B using decoder 139 |
| 7548 | // 14950: } |
| 7549 | 1, 0, // 14955: case 0x1: { |
| 7550 | OPC_Decode, 162, 14, 140, 1, // 14957: decode to XVBITCLRI_H using decoder 140 |
| 7551 | // 14957: } |
| 7552 | // 14957: } // switch Inst[14] |
| 7553 | // 14957: } |
| 7554 | 1, 0, // 14962: case 0x1: { |
| 7555 | OPC_Decode, 163, 14, 134, 1, // 14964: decode to XVBITCLRI_W using decoder 134 |
| 7556 | // 14964: } |
| 7557 | // 14964: } // switch Inst[15] |
| 7558 | // 14964: } |
| 7559 | 1, 0, // 14969: case 0x1: { |
| 7560 | OPC_Decode, 161, 14, 141, 1, // 14971: decode to XVBITCLRI_D using decoder 141 |
| 7561 | // 14971: } |
| 7562 | // 14971: } // switch Inst[17:16] |
| 7563 | // 14971: } |
| 7564 | 197, 1, 45, // 14976: case 0xc5: { |
| 7565 | OPC_SwitchField, 16, 2, // 14979: switch Inst[17:16] { |
| 7566 | 0, 33, // 14982: case 0x0: { |
| 7567 | OPC_SwitchField, 15, 1, // 14984: switch Inst[15] { |
| 7568 | 0, 21, // 14987: case 0x0: { |
| 7569 | OPC_SwitchField, 14, 1, // 14989: switch Inst[14] { |
| 7570 | 0, 9, // 14992: case 0x0: { |
| 7571 | OPC_CheckField, 13, 1, 1, // 14994: check Inst[13] == 0x1 |
| 7572 | OPC_Decode, 178, 14, 139, 1, // 14998: decode to XVBITSETI_B using decoder 139 |
| 7573 | // 14998: } |
| 7574 | 1, 0, // 15003: case 0x1: { |
| 7575 | OPC_Decode, 180, 14, 140, 1, // 15005: decode to XVBITSETI_H using decoder 140 |
| 7576 | // 15005: } |
| 7577 | // 15005: } // switch Inst[14] |
| 7578 | // 15005: } |
| 7579 | 1, 0, // 15010: case 0x1: { |
| 7580 | OPC_Decode, 181, 14, 134, 1, // 15012: decode to XVBITSETI_W using decoder 134 |
| 7581 | // 15012: } |
| 7582 | // 15012: } // switch Inst[15] |
| 7583 | // 15012: } |
| 7584 | 1, 0, // 15017: case 0x1: { |
| 7585 | OPC_Decode, 179, 14, 141, 1, // 15019: decode to XVBITSETI_D using decoder 141 |
| 7586 | // 15019: } |
| 7587 | // 15019: } // switch Inst[17:16] |
| 7588 | // 15019: } |
| 7589 | 198, 1, 45, // 15024: case 0xc6: { |
| 7590 | OPC_SwitchField, 16, 2, // 15027: switch Inst[17:16] { |
| 7591 | 0, 33, // 15030: case 0x0: { |
| 7592 | OPC_SwitchField, 15, 1, // 15032: switch Inst[15] { |
| 7593 | 0, 21, // 15035: case 0x0: { |
| 7594 | OPC_SwitchField, 14, 1, // 15037: switch Inst[14] { |
| 7595 | 0, 9, // 15040: case 0x0: { |
| 7596 | OPC_CheckField, 13, 1, 1, // 15042: check Inst[13] == 0x1 |
| 7597 | OPC_Decode, 168, 14, 139, 1, // 15046: decode to XVBITREVI_B using decoder 139 |
| 7598 | // 15046: } |
| 7599 | 1, 0, // 15051: case 0x1: { |
| 7600 | OPC_Decode, 170, 14, 140, 1, // 15053: decode to XVBITREVI_H using decoder 140 |
| 7601 | // 15053: } |
| 7602 | // 15053: } // switch Inst[14] |
| 7603 | // 15053: } |
| 7604 | 1, 0, // 15058: case 0x1: { |
| 7605 | OPC_Decode, 171, 14, 134, 1, // 15060: decode to XVBITREVI_W using decoder 134 |
| 7606 | // 15060: } |
| 7607 | // 15060: } // switch Inst[15] |
| 7608 | // 15060: } |
| 7609 | 1, 0, // 15065: case 0x1: { |
| 7610 | OPC_Decode, 169, 14, 141, 1, // 15067: decode to XVBITREVI_D using decoder 141 |
| 7611 | // 15067: } |
| 7612 | // 15067: } // switch Inst[17:16] |
| 7613 | // 15067: } |
| 7614 | 201, 1, 45, // 15072: case 0xc9: { |
| 7615 | OPC_SwitchField, 16, 2, // 15075: switch Inst[17:16] { |
| 7616 | 0, 33, // 15078: case 0x0: { |
| 7617 | OPC_SwitchField, 15, 1, // 15080: switch Inst[15] { |
| 7618 | 0, 21, // 15083: case 0x0: { |
| 7619 | OPC_SwitchField, 14, 1, // 15085: switch Inst[14] { |
| 7620 | 0, 9, // 15088: case 0x0: { |
| 7621 | OPC_CheckField, 13, 1, 1, // 15090: check Inst[13] == 0x1 |
| 7622 | OPC_Decode, 194, 17, 139, 1, // 15094: decode to XVSAT_B using decoder 139 |
| 7623 | // 15094: } |
| 7624 | 1, 0, // 15099: case 0x1: { |
| 7625 | OPC_Decode, 198, 17, 140, 1, // 15101: decode to XVSAT_H using decoder 140 |
| 7626 | // 15101: } |
| 7627 | // 15101: } // switch Inst[14] |
| 7628 | // 15101: } |
| 7629 | 1, 0, // 15106: case 0x1: { |
| 7630 | OPC_Decode, 200, 17, 134, 1, // 15108: decode to XVSAT_W using decoder 134 |
| 7631 | // 15108: } |
| 7632 | // 15108: } // switch Inst[15] |
| 7633 | // 15108: } |
| 7634 | 1, 0, // 15113: case 0x1: { |
| 7635 | OPC_Decode, 196, 17, 141, 1, // 15115: decode to XVSAT_D using decoder 141 |
| 7636 | // 15115: } |
| 7637 | // 15115: } // switch Inst[17:16] |
| 7638 | // 15115: } |
| 7639 | 202, 1, 45, // 15120: case 0xca: { |
| 7640 | OPC_SwitchField, 16, 2, // 15123: switch Inst[17:16] { |
| 7641 | 0, 33, // 15126: case 0x0: { |
| 7642 | OPC_SwitchField, 15, 1, // 15128: switch Inst[15] { |
| 7643 | 0, 21, // 15131: case 0x0: { |
| 7644 | OPC_SwitchField, 14, 1, // 15133: switch Inst[14] { |
| 7645 | 0, 9, // 15136: case 0x0: { |
| 7646 | OPC_CheckField, 13, 1, 1, // 15138: check Inst[13] == 0x1 |
| 7647 | OPC_Decode, 195, 17, 139, 1, // 15142: decode to XVSAT_BU using decoder 139 |
| 7648 | // 15142: } |
| 7649 | 1, 0, // 15147: case 0x1: { |
| 7650 | OPC_Decode, 199, 17, 140, 1, // 15149: decode to XVSAT_HU using decoder 140 |
| 7651 | // 15149: } |
| 7652 | // 15149: } // switch Inst[14] |
| 7653 | // 15149: } |
| 7654 | 1, 0, // 15154: case 0x1: { |
| 7655 | OPC_Decode, 201, 17, 134, 1, // 15156: decode to XVSAT_WU using decoder 134 |
| 7656 | // 15156: } |
| 7657 | // 15156: } // switch Inst[15] |
| 7658 | // 15156: } |
| 7659 | 1, 0, // 15161: case 0x1: { |
| 7660 | OPC_Decode, 197, 17, 141, 1, // 15163: decode to XVSAT_DU using decoder 141 |
| 7661 | // 15163: } |
| 7662 | // 15163: } // switch Inst[17:16] |
| 7663 | // 15163: } |
| 7664 | 203, 1, 45, // 15168: case 0xcb: { |
| 7665 | OPC_SwitchField, 16, 2, // 15171: switch Inst[17:16] { |
| 7666 | 0, 33, // 15174: case 0x0: { |
| 7667 | OPC_SwitchField, 15, 1, // 15176: switch Inst[15] { |
| 7668 | 0, 21, // 15179: case 0x0: { |
| 7669 | OPC_SwitchField, 14, 1, // 15181: switch Inst[14] { |
| 7670 | 0, 9, // 15184: case 0x0: { |
| 7671 | OPC_CheckField, 13, 1, 1, // 15186: check Inst[13] == 0x1 |
| 7672 | OPC_Decode, 248, 17, 139, 1, // 15190: decode to XVSLLI_B using decoder 139 |
| 7673 | // 15190: } |
| 7674 | 1, 0, // 15195: case 0x1: { |
| 7675 | OPC_Decode, 250, 17, 140, 1, // 15197: decode to XVSLLI_H using decoder 140 |
| 7676 | // 15197: } |
| 7677 | // 15197: } // switch Inst[14] |
| 7678 | // 15197: } |
| 7679 | 1, 0, // 15202: case 0x1: { |
| 7680 | OPC_Decode, 251, 17, 134, 1, // 15204: decode to XVSLLI_W using decoder 134 |
| 7681 | // 15204: } |
| 7682 | // 15204: } // switch Inst[15] |
| 7683 | // 15204: } |
| 7684 | 1, 0, // 15209: case 0x1: { |
| 7685 | OPC_Decode, 249, 17, 141, 1, // 15211: decode to XVSLLI_D using decoder 141 |
| 7686 | // 15211: } |
| 7687 | // 15211: } // switch Inst[17:16] |
| 7688 | // 15211: } |
| 7689 | 204, 1, 45, // 15216: case 0xcc: { |
| 7690 | OPC_SwitchField, 16, 2, // 15219: switch Inst[17:16] { |
| 7691 | 0, 33, // 15222: case 0x0: { |
| 7692 | OPC_SwitchField, 15, 1, // 15224: switch Inst[15] { |
| 7693 | 0, 21, // 15227: case 0x0: { |
| 7694 | OPC_SwitchField, 14, 1, // 15229: switch Inst[14] { |
| 7695 | 0, 9, // 15232: case 0x0: { |
| 7696 | OPC_CheckField, 13, 1, 1, // 15234: check Inst[13] == 0x1 |
| 7697 | OPC_Decode, 180, 18, 139, 1, // 15238: decode to XVSRLI_B using decoder 139 |
| 7698 | // 15238: } |
| 7699 | 1, 0, // 15243: case 0x1: { |
| 7700 | OPC_Decode, 182, 18, 140, 1, // 15245: decode to XVSRLI_H using decoder 140 |
| 7701 | // 15245: } |
| 7702 | // 15245: } // switch Inst[14] |
| 7703 | // 15245: } |
| 7704 | 1, 0, // 15250: case 0x1: { |
| 7705 | OPC_Decode, 183, 18, 134, 1, // 15252: decode to XVSRLI_W using decoder 134 |
| 7706 | // 15252: } |
| 7707 | // 15252: } // switch Inst[15] |
| 7708 | // 15252: } |
| 7709 | 1, 0, // 15257: case 0x1: { |
| 7710 | OPC_Decode, 181, 18, 141, 1, // 15259: decode to XVSRLI_D using decoder 141 |
| 7711 | // 15259: } |
| 7712 | // 15259: } // switch Inst[17:16] |
| 7713 | // 15259: } |
| 7714 | 205, 1, 45, // 15264: case 0xcd: { |
| 7715 | OPC_SwitchField, 16, 2, // 15267: switch Inst[17:16] { |
| 7716 | 0, 33, // 15270: case 0x0: { |
| 7717 | OPC_SwitchField, 15, 1, // 15272: switch Inst[15] { |
| 7718 | 0, 21, // 15275: case 0x0: { |
| 7719 | OPC_SwitchField, 14, 1, // 15277: switch Inst[14] { |
| 7720 | 0, 9, // 15280: case 0x0: { |
| 7721 | OPC_CheckField, 13, 1, 1, // 15282: check Inst[13] == 0x1 |
| 7722 | OPC_Decode, 150, 18, 139, 1, // 15286: decode to XVSRAI_B using decoder 139 |
| 7723 | // 15286: } |
| 7724 | 1, 0, // 15291: case 0x1: { |
| 7725 | OPC_Decode, 152, 18, 140, 1, // 15293: decode to XVSRAI_H using decoder 140 |
| 7726 | // 15293: } |
| 7727 | // 15293: } // switch Inst[14] |
| 7728 | // 15293: } |
| 7729 | 1, 0, // 15298: case 0x1: { |
| 7730 | OPC_Decode, 153, 18, 134, 1, // 15300: decode to XVSRAI_W using decoder 134 |
| 7731 | // 15300: } |
| 7732 | // 15300: } // switch Inst[15] |
| 7733 | // 15300: } |
| 7734 | 1, 0, // 15305: case 0x1: { |
| 7735 | OPC_Decode, 151, 18, 141, 1, // 15307: decode to XVSRAI_D using decoder 141 |
| 7736 | // 15307: } |
| 7737 | // 15307: } // switch Inst[17:16] |
| 7738 | // 15307: } |
| 7739 | 208, 1, 45, // 15312: case 0xd0: { |
| 7740 | OPC_SwitchField, 17, 1, // 15315: switch Inst[17] { |
| 7741 | 0, 33, // 15318: case 0x0: { |
| 7742 | OPC_SwitchField, 16, 1, // 15320: switch Inst[16] { |
| 7743 | 0, 21, // 15323: case 0x0: { |
| 7744 | OPC_SwitchField, 15, 1, // 15325: switch Inst[15] { |
| 7745 | 0, 9, // 15328: case 0x0: { |
| 7746 | OPC_CheckField, 14, 1, 1, // 15330: check Inst[14] == 0x1 |
| 7747 | OPC_Decode, 184, 18, 150, 1, // 15334: decode to XVSRLNI_B_H using decoder 150 |
| 7748 | // 15334: } |
| 7749 | 1, 0, // 15339: case 0x1: { |
| 7750 | OPC_Decode, 186, 18, 135, 1, // 15341: decode to XVSRLNI_H_W using decoder 135 |
| 7751 | // 15341: } |
| 7752 | // 15341: } // switch Inst[15] |
| 7753 | // 15341: } |
| 7754 | 1, 0, // 15346: case 0x1: { |
| 7755 | OPC_Decode, 187, 18, 151, 1, // 15348: decode to XVSRLNI_W_D using decoder 151 |
| 7756 | // 15348: } |
| 7757 | // 15348: } // switch Inst[16] |
| 7758 | // 15348: } |
| 7759 | 1, 0, // 15353: case 0x1: { |
| 7760 | OPC_Decode, 185, 18, 152, 1, // 15355: decode to XVSRLNI_D_Q using decoder 152 |
| 7761 | // 15355: } |
| 7762 | // 15355: } // switch Inst[17] |
| 7763 | // 15355: } |
| 7764 | 209, 1, 45, // 15360: case 0xd1: { |
| 7765 | OPC_SwitchField, 17, 1, // 15363: switch Inst[17] { |
| 7766 | 0, 33, // 15366: case 0x0: { |
| 7767 | OPC_SwitchField, 16, 1, // 15368: switch Inst[16] { |
| 7768 | 0, 21, // 15371: case 0x0: { |
| 7769 | OPC_SwitchField, 15, 1, // 15373: switch Inst[15] { |
| 7770 | 0, 9, // 15376: case 0x0: { |
| 7771 | OPC_CheckField, 14, 1, 1, // 15378: check Inst[14] == 0x1 |
| 7772 | OPC_Decode, 195, 18, 150, 1, // 15382: decode to XVSRLRNI_B_H using decoder 150 |
| 7773 | // 15382: } |
| 7774 | 1, 0, // 15387: case 0x1: { |
| 7775 | OPC_Decode, 197, 18, 135, 1, // 15389: decode to XVSRLRNI_H_W using decoder 135 |
| 7776 | // 15389: } |
| 7777 | // 15389: } // switch Inst[15] |
| 7778 | // 15389: } |
| 7779 | 1, 0, // 15394: case 0x1: { |
| 7780 | OPC_Decode, 198, 18, 151, 1, // 15396: decode to XVSRLRNI_W_D using decoder 151 |
| 7781 | // 15396: } |
| 7782 | // 15396: } // switch Inst[16] |
| 7783 | // 15396: } |
| 7784 | 1, 0, // 15401: case 0x1: { |
| 7785 | OPC_Decode, 196, 18, 152, 1, // 15403: decode to XVSRLRNI_D_Q using decoder 152 |
| 7786 | // 15403: } |
| 7787 | // 15403: } // switch Inst[17] |
| 7788 | // 15403: } |
| 7789 | 210, 1, 45, // 15408: case 0xd2: { |
| 7790 | OPC_SwitchField, 17, 1, // 15411: switch Inst[17] { |
| 7791 | 0, 33, // 15414: case 0x0: { |
| 7792 | OPC_SwitchField, 16, 1, // 15416: switch Inst[16] { |
| 7793 | 0, 21, // 15419: case 0x0: { |
| 7794 | OPC_SwitchField, 15, 1, // 15421: switch Inst[15] { |
| 7795 | 0, 9, // 15424: case 0x0: { |
| 7796 | OPC_CheckField, 14, 1, 1, // 15426: check Inst[14] == 0x1 |
| 7797 | OPC_Decode, 239, 18, 150, 1, // 15430: decode to XVSSRLNI_B_H using decoder 150 |
| 7798 | // 15430: } |
| 7799 | 1, 0, // 15435: case 0x1: { |
| 7800 | OPC_Decode, 243, 18, 135, 1, // 15437: decode to XVSSRLNI_H_W using decoder 135 |
| 7801 | // 15437: } |
| 7802 | // 15437: } // switch Inst[15] |
| 7803 | // 15437: } |
| 7804 | 1, 0, // 15442: case 0x1: { |
| 7805 | OPC_Decode, 245, 18, 151, 1, // 15444: decode to XVSSRLNI_W_D using decoder 151 |
| 7806 | // 15444: } |
| 7807 | // 15444: } // switch Inst[16] |
| 7808 | // 15444: } |
| 7809 | 1, 0, // 15449: case 0x1: { |
| 7810 | OPC_Decode, 241, 18, 152, 1, // 15451: decode to XVSSRLNI_D_Q using decoder 152 |
| 7811 | // 15451: } |
| 7812 | // 15451: } // switch Inst[17] |
| 7813 | // 15451: } |
| 7814 | 211, 1, 45, // 15456: case 0xd3: { |
| 7815 | OPC_SwitchField, 17, 1, // 15459: switch Inst[17] { |
| 7816 | 0, 33, // 15462: case 0x0: { |
| 7817 | OPC_SwitchField, 16, 1, // 15464: switch Inst[16] { |
| 7818 | 0, 21, // 15467: case 0x0: { |
| 7819 | OPC_SwitchField, 15, 1, // 15469: switch Inst[15] { |
| 7820 | 0, 9, // 15472: case 0x0: { |
| 7821 | OPC_CheckField, 14, 1, 1, // 15474: check Inst[14] == 0x1 |
| 7822 | OPC_Decode, 238, 18, 150, 1, // 15478: decode to XVSSRLNI_BU_H using decoder 150 |
| 7823 | // 15478: } |
| 7824 | 1, 0, // 15483: case 0x1: { |
| 7825 | OPC_Decode, 242, 18, 135, 1, // 15485: decode to XVSSRLNI_HU_W using decoder 135 |
| 7826 | // 15485: } |
| 7827 | // 15485: } // switch Inst[15] |
| 7828 | // 15485: } |
| 7829 | 1, 0, // 15490: case 0x1: { |
| 7830 | OPC_Decode, 244, 18, 151, 1, // 15492: decode to XVSSRLNI_WU_D using decoder 151 |
| 7831 | // 15492: } |
| 7832 | // 15492: } // switch Inst[16] |
| 7833 | // 15492: } |
| 7834 | 1, 0, // 15497: case 0x1: { |
| 7835 | OPC_Decode, 240, 18, 152, 1, // 15499: decode to XVSSRLNI_DU_Q using decoder 152 |
| 7836 | // 15499: } |
| 7837 | // 15499: } // switch Inst[17] |
| 7838 | // 15499: } |
| 7839 | 212, 1, 45, // 15504: case 0xd4: { |
| 7840 | OPC_SwitchField, 17, 1, // 15507: switch Inst[17] { |
| 7841 | 0, 33, // 15510: case 0x0: { |
| 7842 | OPC_SwitchField, 16, 1, // 15512: switch Inst[16] { |
| 7843 | 0, 21, // 15515: case 0x0: { |
| 7844 | OPC_SwitchField, 15, 1, // 15517: switch Inst[15] { |
| 7845 | 0, 9, // 15520: case 0x0: { |
| 7846 | OPC_CheckField, 14, 1, 1, // 15522: check Inst[14] == 0x1 |
| 7847 | OPC_Decode, 253, 18, 150, 1, // 15526: decode to XVSSRLRNI_B_H using decoder 150 |
| 7848 | // 15526: } |
| 7849 | 1, 0, // 15531: case 0x1: { |
| 7850 | OPC_Decode, 129, 19, 135, 1, // 15533: decode to XVSSRLRNI_H_W using decoder 135 |
| 7851 | // 15533: } |
| 7852 | // 15533: } // switch Inst[15] |
| 7853 | // 15533: } |
| 7854 | 1, 0, // 15538: case 0x1: { |
| 7855 | OPC_Decode, 131, 19, 151, 1, // 15540: decode to XVSSRLRNI_W_D using decoder 151 |
| 7856 | // 15540: } |
| 7857 | // 15540: } // switch Inst[16] |
| 7858 | // 15540: } |
| 7859 | 1, 0, // 15545: case 0x1: { |
| 7860 | OPC_Decode, 255, 18, 152, 1, // 15547: decode to XVSSRLRNI_D_Q using decoder 152 |
| 7861 | // 15547: } |
| 7862 | // 15547: } // switch Inst[17] |
| 7863 | // 15547: } |
| 7864 | 213, 1, 45, // 15552: case 0xd5: { |
| 7865 | OPC_SwitchField, 17, 1, // 15555: switch Inst[17] { |
| 7866 | 0, 33, // 15558: case 0x0: { |
| 7867 | OPC_SwitchField, 16, 1, // 15560: switch Inst[16] { |
| 7868 | 0, 21, // 15563: case 0x0: { |
| 7869 | OPC_SwitchField, 15, 1, // 15565: switch Inst[15] { |
| 7870 | 0, 9, // 15568: case 0x0: { |
| 7871 | OPC_CheckField, 14, 1, 1, // 15570: check Inst[14] == 0x1 |
| 7872 | OPC_Decode, 252, 18, 150, 1, // 15574: decode to XVSSRLRNI_BU_H using decoder 150 |
| 7873 | // 15574: } |
| 7874 | 1, 0, // 15579: case 0x1: { |
| 7875 | OPC_Decode, 128, 19, 135, 1, // 15581: decode to XVSSRLRNI_HU_W using decoder 135 |
| 7876 | // 15581: } |
| 7877 | // 15581: } // switch Inst[15] |
| 7878 | // 15581: } |
| 7879 | 1, 0, // 15586: case 0x1: { |
| 7880 | OPC_Decode, 130, 19, 151, 1, // 15588: decode to XVSSRLRNI_WU_D using decoder 151 |
| 7881 | // 15588: } |
| 7882 | // 15588: } // switch Inst[16] |
| 7883 | // 15588: } |
| 7884 | 1, 0, // 15593: case 0x1: { |
| 7885 | OPC_Decode, 254, 18, 152, 1, // 15595: decode to XVSSRLRNI_DU_Q using decoder 152 |
| 7886 | // 15595: } |
| 7887 | // 15595: } // switch Inst[17] |
| 7888 | // 15595: } |
| 7889 | 214, 1, 45, // 15600: case 0xd6: { |
| 7890 | OPC_SwitchField, 17, 1, // 15603: switch Inst[17] { |
| 7891 | 0, 33, // 15606: case 0x0: { |
| 7892 | OPC_SwitchField, 16, 1, // 15608: switch Inst[16] { |
| 7893 | 0, 21, // 15611: case 0x0: { |
| 7894 | OPC_SwitchField, 15, 1, // 15613: switch Inst[15] { |
| 7895 | 0, 9, // 15616: case 0x0: { |
| 7896 | OPC_CheckField, 14, 1, 1, // 15618: check Inst[14] == 0x1 |
| 7897 | OPC_Decode, 154, 18, 150, 1, // 15622: decode to XVSRANI_B_H using decoder 150 |
| 7898 | // 15622: } |
| 7899 | 1, 0, // 15627: case 0x1: { |
| 7900 | OPC_Decode, 156, 18, 135, 1, // 15629: decode to XVSRANI_H_W using decoder 135 |
| 7901 | // 15629: } |
| 7902 | // 15629: } // switch Inst[15] |
| 7903 | // 15629: } |
| 7904 | 1, 0, // 15634: case 0x1: { |
| 7905 | OPC_Decode, 157, 18, 151, 1, // 15636: decode to XVSRANI_W_D using decoder 151 |
| 7906 | // 15636: } |
| 7907 | // 15636: } // switch Inst[16] |
| 7908 | // 15636: } |
| 7909 | 1, 0, // 15641: case 0x1: { |
| 7910 | OPC_Decode, 155, 18, 152, 1, // 15643: decode to XVSRANI_D_Q using decoder 152 |
| 7911 | // 15643: } |
| 7912 | // 15643: } // switch Inst[17] |
| 7913 | // 15643: } |
| 7914 | 215, 1, 45, // 15648: case 0xd7: { |
| 7915 | OPC_SwitchField, 17, 1, // 15651: switch Inst[17] { |
| 7916 | 0, 33, // 15654: case 0x0: { |
| 7917 | OPC_SwitchField, 16, 1, // 15656: switch Inst[16] { |
| 7918 | 0, 21, // 15659: case 0x0: { |
| 7919 | OPC_SwitchField, 15, 1, // 15661: switch Inst[15] { |
| 7920 | 0, 9, // 15664: case 0x0: { |
| 7921 | OPC_CheckField, 14, 1, 1, // 15666: check Inst[14] == 0x1 |
| 7922 | OPC_Decode, 165, 18, 150, 1, // 15670: decode to XVSRARNI_B_H using decoder 150 |
| 7923 | // 15670: } |
| 7924 | 1, 0, // 15675: case 0x1: { |
| 7925 | OPC_Decode, 167, 18, 135, 1, // 15677: decode to XVSRARNI_H_W using decoder 135 |
| 7926 | // 15677: } |
| 7927 | // 15677: } // switch Inst[15] |
| 7928 | // 15677: } |
| 7929 | 1, 0, // 15682: case 0x1: { |
| 7930 | OPC_Decode, 168, 18, 151, 1, // 15684: decode to XVSRARNI_W_D using decoder 151 |
| 7931 | // 15684: } |
| 7932 | // 15684: } // switch Inst[16] |
| 7933 | // 15684: } |
| 7934 | 1, 0, // 15689: case 0x1: { |
| 7935 | OPC_Decode, 166, 18, 152, 1, // 15691: decode to XVSRARNI_D_Q using decoder 152 |
| 7936 | // 15691: } |
| 7937 | // 15691: } // switch Inst[17] |
| 7938 | // 15691: } |
| 7939 | 216, 1, 45, // 15696: case 0xd8: { |
| 7940 | OPC_SwitchField, 17, 1, // 15699: switch Inst[17] { |
| 7941 | 0, 33, // 15702: case 0x0: { |
| 7942 | OPC_SwitchField, 16, 1, // 15704: switch Inst[16] { |
| 7943 | 0, 21, // 15707: case 0x0: { |
| 7944 | OPC_SwitchField, 15, 1, // 15709: switch Inst[15] { |
| 7945 | 0, 9, // 15712: case 0x0: { |
| 7946 | OPC_CheckField, 14, 1, 1, // 15714: check Inst[14] == 0x1 |
| 7947 | OPC_Decode, 211, 18, 150, 1, // 15718: decode to XVSSRANI_B_H using decoder 150 |
| 7948 | // 15718: } |
| 7949 | 1, 0, // 15723: case 0x1: { |
| 7950 | OPC_Decode, 215, 18, 135, 1, // 15725: decode to XVSSRANI_H_W using decoder 135 |
| 7951 | // 15725: } |
| 7952 | // 15725: } // switch Inst[15] |
| 7953 | // 15725: } |
| 7954 | 1, 0, // 15730: case 0x1: { |
| 7955 | OPC_Decode, 217, 18, 151, 1, // 15732: decode to XVSSRANI_W_D using decoder 151 |
| 7956 | // 15732: } |
| 7957 | // 15732: } // switch Inst[16] |
| 7958 | // 15732: } |
| 7959 | 1, 0, // 15737: case 0x1: { |
| 7960 | OPC_Decode, 213, 18, 152, 1, // 15739: decode to XVSSRANI_D_Q using decoder 152 |
| 7961 | // 15739: } |
| 7962 | // 15739: } // switch Inst[17] |
| 7963 | // 15739: } |
| 7964 | 217, 1, 45, // 15744: case 0xd9: { |
| 7965 | OPC_SwitchField, 17, 1, // 15747: switch Inst[17] { |
| 7966 | 0, 33, // 15750: case 0x0: { |
| 7967 | OPC_SwitchField, 16, 1, // 15752: switch Inst[16] { |
| 7968 | 0, 21, // 15755: case 0x0: { |
| 7969 | OPC_SwitchField, 15, 1, // 15757: switch Inst[15] { |
| 7970 | 0, 9, // 15760: case 0x0: { |
| 7971 | OPC_CheckField, 14, 1, 1, // 15762: check Inst[14] == 0x1 |
| 7972 | OPC_Decode, 210, 18, 150, 1, // 15766: decode to XVSSRANI_BU_H using decoder 150 |
| 7973 | // 15766: } |
| 7974 | 1, 0, // 15771: case 0x1: { |
| 7975 | OPC_Decode, 214, 18, 135, 1, // 15773: decode to XVSSRANI_HU_W using decoder 135 |
| 7976 | // 15773: } |
| 7977 | // 15773: } // switch Inst[15] |
| 7978 | // 15773: } |
| 7979 | 1, 0, // 15778: case 0x1: { |
| 7980 | OPC_Decode, 216, 18, 151, 1, // 15780: decode to XVSSRANI_WU_D using decoder 151 |
| 7981 | // 15780: } |
| 7982 | // 15780: } // switch Inst[16] |
| 7983 | // 15780: } |
| 7984 | 1, 0, // 15785: case 0x1: { |
| 7985 | OPC_Decode, 212, 18, 152, 1, // 15787: decode to XVSSRANI_DU_Q using decoder 152 |
| 7986 | // 15787: } |
| 7987 | // 15787: } // switch Inst[17] |
| 7988 | // 15787: } |
| 7989 | 218, 1, 45, // 15792: case 0xda: { |
| 7990 | OPC_SwitchField, 17, 1, // 15795: switch Inst[17] { |
| 7991 | 0, 33, // 15798: case 0x0: { |
| 7992 | OPC_SwitchField, 16, 1, // 15800: switch Inst[16] { |
| 7993 | 0, 21, // 15803: case 0x0: { |
| 7994 | OPC_SwitchField, 15, 1, // 15805: switch Inst[15] { |
| 7995 | 0, 9, // 15808: case 0x0: { |
| 7996 | OPC_CheckField, 14, 1, 1, // 15810: check Inst[14] == 0x1 |
| 7997 | OPC_Decode, 225, 18, 150, 1, // 15814: decode to XVSSRARNI_B_H using decoder 150 |
| 7998 | // 15814: } |
| 7999 | 1, 0, // 15819: case 0x1: { |
| 8000 | OPC_Decode, 229, 18, 135, 1, // 15821: decode to XVSSRARNI_H_W using decoder 135 |
| 8001 | // 15821: } |
| 8002 | // 15821: } // switch Inst[15] |
| 8003 | // 15821: } |
| 8004 | 1, 0, // 15826: case 0x1: { |
| 8005 | OPC_Decode, 231, 18, 151, 1, // 15828: decode to XVSSRARNI_W_D using decoder 151 |
| 8006 | // 15828: } |
| 8007 | // 15828: } // switch Inst[16] |
| 8008 | // 15828: } |
| 8009 | 1, 0, // 15833: case 0x1: { |
| 8010 | OPC_Decode, 227, 18, 152, 1, // 15835: decode to XVSSRARNI_D_Q using decoder 152 |
| 8011 | // 15835: } |
| 8012 | // 15835: } // switch Inst[17] |
| 8013 | // 15835: } |
| 8014 | 219, 1, 45, // 15840: case 0xdb: { |
| 8015 | OPC_SwitchField, 17, 1, // 15843: switch Inst[17] { |
| 8016 | 0, 33, // 15846: case 0x0: { |
| 8017 | OPC_SwitchField, 16, 1, // 15848: switch Inst[16] { |
| 8018 | 0, 21, // 15851: case 0x0: { |
| 8019 | OPC_SwitchField, 15, 1, // 15853: switch Inst[15] { |
| 8020 | 0, 9, // 15856: case 0x0: { |
| 8021 | OPC_CheckField, 14, 1, 1, // 15858: check Inst[14] == 0x1 |
| 8022 | OPC_Decode, 224, 18, 150, 1, // 15862: decode to XVSSRARNI_BU_H using decoder 150 |
| 8023 | // 15862: } |
| 8024 | 1, 0, // 15867: case 0x1: { |
| 8025 | OPC_Decode, 228, 18, 135, 1, // 15869: decode to XVSSRARNI_HU_W using decoder 135 |
| 8026 | // 15869: } |
| 8027 | // 15869: } // switch Inst[15] |
| 8028 | // 15869: } |
| 8029 | 1, 0, // 15874: case 0x1: { |
| 8030 | OPC_Decode, 230, 18, 151, 1, // 15876: decode to XVSSRARNI_WU_D using decoder 151 |
| 8031 | // 15876: } |
| 8032 | // 15876: } // switch Inst[16] |
| 8033 | // 15876: } |
| 8034 | 1, 0, // 15881: case 0x1: { |
| 8035 | OPC_Decode, 226, 18, 152, 1, // 15883: decode to XVSSRARNI_DU_Q using decoder 152 |
| 8036 | // 15883: } |
| 8037 | // 15883: } // switch Inst[17] |
| 8038 | // 15883: } |
| 8039 | 224, 1, 5, // 15888: case 0xe0: { |
| 8040 | OPC_Decode, 215, 14, 153, 1, // 15891: decode to XVEXTRINS_D using decoder 153 |
| 8041 | // 15891: } |
| 8042 | 225, 1, 5, // 15896: case 0xe1: { |
| 8043 | OPC_Decode, 217, 14, 153, 1, // 15899: decode to XVEXTRINS_W using decoder 153 |
| 8044 | // 15899: } |
| 8045 | 226, 1, 5, // 15904: case 0xe2: { |
| 8046 | OPC_Decode, 216, 14, 153, 1, // 15907: decode to XVEXTRINS_H using decoder 153 |
| 8047 | // 15907: } |
| 8048 | 227, 1, 5, // 15912: case 0xe3: { |
| 8049 | OPC_Decode, 214, 14, 153, 1, // 15915: decode to XVEXTRINS_B using decoder 153 |
| 8050 | // 15915: } |
| 8051 | 228, 1, 5, // 15920: case 0xe4: { |
| 8052 | OPC_Decode, 220, 17, 154, 1, // 15923: decode to XVSHUF4I_B using decoder 154 |
| 8053 | // 15923: } |
| 8054 | 229, 1, 5, // 15928: case 0xe5: { |
| 8055 | OPC_Decode, 222, 17, 154, 1, // 15931: decode to XVSHUF4I_H using decoder 154 |
| 8056 | // 15931: } |
| 8057 | 230, 1, 5, // 15936: case 0xe6: { |
| 8058 | OPC_Decode, 223, 17, 154, 1, // 15939: decode to XVSHUF4I_W using decoder 154 |
| 8059 | // 15939: } |
| 8060 | 231, 1, 5, // 15944: case 0xe7: { |
| 8061 | OPC_Decode, 221, 17, 153, 1, // 15947: decode to XVSHUF4I_D using decoder 153 |
| 8062 | // 15947: } |
| 8063 | 241, 1, 5, // 15952: case 0xf1: { |
| 8064 | OPC_Decode, 176, 14, 153, 1, // 15955: decode to XVBITSELI_B using decoder 153 |
| 8065 | // 15955: } |
| 8066 | 244, 1, 5, // 15960: case 0xf4: { |
| 8067 | OPC_Decode, 141, 14, 154, 1, // 15963: decode to XVANDI_B using decoder 154 |
| 8068 | // 15963: } |
| 8069 | 245, 1, 5, // 15968: case 0xf5: { |
| 8070 | OPC_Decode, 128, 17, 154, 1, // 15971: decode to XVORI_B using decoder 154 |
| 8071 | // 15971: } |
| 8072 | 246, 1, 5, // 15976: case 0xf6: { |
| 8073 | OPC_Decode, 177, 19, 154, 1, // 15979: decode to XVXORI_B using decoder 154 |
| 8074 | // 15979: } |
| 8075 | 247, 1, 5, // 15984: case 0xf7: { |
| 8076 | OPC_Decode, 254, 16, 154, 1, // 15987: decode to XVNORI_B using decoder 154 |
| 8077 | // 15987: } |
| 8078 | 248, 1, 5, // 15992: case 0xf8: { |
| 8079 | OPC_Decode, 130, 16, 155, 1, // 15995: decode to XVLDI using decoder 155 |
| 8080 | // 15995: } |
| 8081 | 249, 1, 5, // 16000: case 0xf9: { |
| 8082 | OPC_Decode, 145, 17, 153, 1, // 16003: decode to XVPERMI_W using decoder 153 |
| 8083 | // 16003: } |
| 8084 | 250, 1, 5, // 16008: case 0xfa: { |
| 8085 | OPC_Decode, 143, 17, 154, 1, // 16011: decode to XVPERMI_D using decoder 154 |
| 8086 | // 16011: } |
| 8087 | 251, 1, 0, // 16016: case 0xfb: { |
| 8088 | OPC_Decode, 144, 17, 153, 1, // 16019: decode to XVPERMI_Q using decoder 153 |
| 8089 | // 16019: } |
| 8090 | // 16019: } // switch Inst[25:18] |
| 8091 | // 16019: } |
| 8092 | // 16019: } // switch Inst[31:26] |
| 8093 | }; |
| 8094 | // Handling 156 cases. |
| 8095 | template <typename InsnType> |
| 8096 | static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) { |
| 8097 | DecodeComplete = true; |
| 8098 | using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>; |
| 8099 | TmpType tmp; |
| 8100 | switch (Idx) { |
| 8101 | default: llvm_unreachable("Invalid decoder index!"); |
| 8102 | case 0: |
| 8103 | tmp = fieldFromInstruction(insn, 0, 2); |
| 8104 | if (!Check(S, DecodeSCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8105 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8106 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8107 | return S; |
| 8108 | case 1: |
| 8109 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8110 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8111 | tmp = fieldFromInstruction(insn, 5, 2); |
| 8112 | if (!Check(S, DecodeSCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8113 | return S; |
| 8114 | case 2: |
| 8115 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8116 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8117 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8118 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8119 | return S; |
| 8120 | case 3: |
| 8121 | tmp = fieldFromInstruction(insn, 5, 3); |
| 8122 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8123 | return S; |
| 8124 | case 4: |
| 8125 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8126 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8127 | return S; |
| 8128 | case 5: |
| 8129 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8130 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8131 | return S; |
| 8132 | case 6: |
| 8133 | return S; |
| 8134 | case 7: |
| 8135 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8136 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8137 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8138 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8139 | return S; |
| 8140 | case 8: |
| 8141 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8142 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8143 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8144 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8145 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8146 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8147 | tmp = fieldFromInstruction(insn, 15, 2); |
| 8148 | if (!Check(S, decodeUImmOperand<2, 1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8149 | return S; |
| 8150 | case 9: |
| 8151 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8152 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8153 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8154 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8155 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8156 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8157 | tmp = fieldFromInstruction(insn, 15, 2); |
| 8158 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8159 | return S; |
| 8160 | case 10: |
| 8161 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8162 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8163 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8164 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8165 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8166 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8167 | tmp = fieldFromInstruction(insn, 15, 3); |
| 8168 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8169 | return S; |
| 8170 | case 11: |
| 8171 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8172 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8173 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8174 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8175 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8176 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8177 | return S; |
| 8178 | case 12: |
| 8179 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8180 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8181 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8182 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8183 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8184 | if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8185 | return S; |
| 8186 | case 13: |
| 8187 | tmp = fieldFromInstruction(insn, 0, 15); |
| 8188 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8189 | return S; |
| 8190 | case 14: |
| 8191 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8192 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8193 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8194 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8195 | tmp = fieldFromInstruction(insn, 10, 4); |
| 8196 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8197 | return S; |
| 8198 | case 15: |
| 8199 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8200 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8201 | tmp = fieldFromInstruction(insn, 10, 4); |
| 8202 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8203 | return S; |
| 8204 | case 16: |
| 8205 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8206 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8207 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8208 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8209 | tmp = fieldFromInstruction(insn, 0, 4); |
| 8210 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8211 | return S; |
| 8212 | case 17: |
| 8213 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8214 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8215 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8216 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8217 | tmp = fieldFromInstruction(insn, 0, 4); |
| 8218 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8219 | return S; |
| 8220 | case 18: |
| 8221 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8222 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8223 | tmp = fieldFromInstruction(insn, 10, 4); |
| 8224 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8225 | return S; |
| 8226 | case 19: |
| 8227 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8228 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8229 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8230 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8231 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8232 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8233 | return S; |
| 8234 | case 20: |
| 8235 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8236 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8237 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8238 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8239 | tmp = fieldFromInstruction(insn, 10, 6); |
| 8240 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8241 | return S; |
| 8242 | case 21: |
| 8243 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8244 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8245 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8246 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8247 | tmp = fieldFromInstruction(insn, 10, 3); |
| 8248 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8249 | return S; |
| 8250 | case 22: |
| 8251 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8252 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8253 | tmp = fieldFromInstruction(insn, 10, 3); |
| 8254 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8255 | return S; |
| 8256 | case 23: |
| 8257 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8258 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8259 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8260 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8261 | return S; |
| 8262 | case 24: |
| 8263 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8264 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8265 | tmp = fieldFromInstruction(insn, 10, 6); |
| 8266 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8267 | return S; |
| 8268 | case 25: |
| 8269 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8270 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8271 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8272 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8273 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8274 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8275 | return S; |
| 8276 | case 26: |
| 8277 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8278 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8279 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8280 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8281 | return S; |
| 8282 | case 27: |
| 8283 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8284 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8285 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8286 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8287 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8288 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8289 | tmp = fieldFromInstruction(insn, 16, 5); |
| 8290 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8291 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8292 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8293 | return S; |
| 8294 | case 28: |
| 8295 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8296 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8297 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8298 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8299 | tmp = fieldFromInstruction(insn, 16, 5); |
| 8300 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8301 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8302 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8303 | return S; |
| 8304 | case 29: |
| 8305 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8306 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8307 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8308 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8309 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8310 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8311 | tmp = fieldFromInstruction(insn, 16, 6); |
| 8312 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8313 | tmp = fieldFromInstruction(insn, 10, 6); |
| 8314 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8315 | return S; |
| 8316 | case 30: |
| 8317 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8318 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8319 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8320 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8321 | tmp = fieldFromInstruction(insn, 16, 6); |
| 8322 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8323 | tmp = fieldFromInstruction(insn, 10, 6); |
| 8324 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8325 | return S; |
| 8326 | case 31: |
| 8327 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8328 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8329 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8330 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8331 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8332 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8333 | return S; |
| 8334 | case 32: |
| 8335 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8336 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8337 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8338 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8339 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8340 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8341 | return S; |
| 8342 | case 33: |
| 8343 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8344 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8345 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8346 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8347 | return S; |
| 8348 | case 34: |
| 8349 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8350 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8351 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8352 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8353 | return S; |
| 8354 | case 35: |
| 8355 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8356 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8357 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8358 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8359 | return S; |
| 8360 | case 36: |
| 8361 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8362 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8363 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8364 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8365 | return S; |
| 8366 | case 37: |
| 8367 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8368 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8369 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8370 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8371 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8372 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8373 | return S; |
| 8374 | case 38: |
| 8375 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8376 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8377 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8378 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8379 | return S; |
| 8380 | case 39: |
| 8381 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8382 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8383 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8384 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8385 | return S; |
| 8386 | case 40: |
| 8387 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8388 | if (!Check(S, DecodeFCSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8389 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8390 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8391 | return S; |
| 8392 | case 41: |
| 8393 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8394 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8395 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8396 | if (!Check(S, DecodeFCSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8397 | return S; |
| 8398 | case 42: |
| 8399 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8400 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8401 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8402 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8403 | return S; |
| 8404 | case 43: |
| 8405 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8406 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8407 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8408 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8409 | return S; |
| 8410 | case 44: |
| 8411 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8412 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8413 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8414 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8415 | return S; |
| 8416 | case 45: |
| 8417 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8418 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8419 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8420 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8421 | return S; |
| 8422 | case 46: |
| 8423 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8424 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8425 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8426 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8427 | return S; |
| 8428 | case 47: |
| 8429 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8430 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8431 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8432 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8433 | return S; |
| 8434 | case 48: |
| 8435 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8436 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8437 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8438 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8439 | tmp = fieldFromInstruction(insn, 10, 12); |
| 8440 | if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8441 | return S; |
| 8442 | case 49: |
| 8443 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8444 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8445 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8446 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8447 | tmp = fieldFromInstruction(insn, 10, 12); |
| 8448 | if (!Check(S, decodeUImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8449 | return S; |
| 8450 | case 50: |
| 8451 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8452 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8453 | tmp = fieldFromInstruction(insn, 10, 14); |
| 8454 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8455 | return S; |
| 8456 | case 51: |
| 8457 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8458 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8459 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8460 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8461 | tmp = fieldFromInstruction(insn, 10, 14); |
| 8462 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8463 | return S; |
| 8464 | case 52: |
| 8465 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8466 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8467 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8468 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8469 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8470 | if (!Check(S, DecodeGPRNoR0R1RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8471 | tmp = fieldFromInstruction(insn, 10, 14); |
| 8472 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8473 | return S; |
| 8474 | case 53: |
| 8475 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8476 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8477 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8478 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8479 | tmp = fieldFromInstruction(insn, 10, 12); |
| 8480 | if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8481 | return S; |
| 8482 | case 54: |
| 8483 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8484 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8485 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8486 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8487 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8488 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8489 | return S; |
| 8490 | case 55: |
| 8491 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8492 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8493 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8494 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8495 | return S; |
| 8496 | case 56: |
| 8497 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8498 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8499 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8500 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8501 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8502 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8503 | return S; |
| 8504 | case 57: |
| 8505 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8506 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8507 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8508 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8509 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8510 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8511 | tmp = fieldFromInstruction(insn, 15, 5); |
| 8512 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8513 | return S; |
| 8514 | case 58: |
| 8515 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8516 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8517 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8518 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8519 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8520 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8521 | tmp = fieldFromInstruction(insn, 15, 5); |
| 8522 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8523 | return S; |
| 8524 | case 59: |
| 8525 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8526 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8527 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8528 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8529 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8530 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8531 | tmp = fieldFromInstruction(insn, 15, 5); |
| 8532 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8533 | return S; |
| 8534 | case 60: |
| 8535 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8536 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8537 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8538 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8539 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8540 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8541 | tmp = fieldFromInstruction(insn, 15, 5); |
| 8542 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8543 | return S; |
| 8544 | case 61: |
| 8545 | tmp = fieldFromInstruction(insn, 0, 3); |
| 8546 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8547 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8548 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8549 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8550 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8551 | return S; |
| 8552 | case 62: |
| 8553 | tmp = fieldFromInstruction(insn, 0, 3); |
| 8554 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8555 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8556 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8557 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8558 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8559 | return S; |
| 8560 | case 63: |
| 8561 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8562 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8563 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8564 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8565 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8566 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8567 | return S; |
| 8568 | case 64: |
| 8569 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8570 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8571 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8572 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8573 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8574 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8575 | return S; |
| 8576 | case 65: |
| 8577 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8578 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8579 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8580 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8581 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8582 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8583 | tmp = fieldFromInstruction(insn, 15, 3); |
| 8584 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8585 | return S; |
| 8586 | case 66: |
| 8587 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8588 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8589 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8590 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8591 | tmp = fieldFromInstruction(insn, 10, 16); |
| 8592 | if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8593 | return S; |
| 8594 | case 67: |
| 8595 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8596 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8597 | tmp = fieldFromInstruction(insn, 5, 20); |
| 8598 | if (!Check(S, decodeSImmOperand<20>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8599 | return S; |
| 8600 | case 68: |
| 8601 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8602 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8603 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8604 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8605 | tmp = fieldFromInstruction(insn, 5, 20); |
| 8606 | if (!Check(S, decodeSImmOperand<20>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8607 | return S; |
| 8608 | case 69: |
| 8609 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8610 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8611 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8612 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8613 | tmp = fieldFromInstruction(insn, 10, 14); |
| 8614 | if (!Check(S, decodeSImmOperand<14, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8615 | return S; |
| 8616 | case 70: |
| 8617 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8618 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8619 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8620 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8621 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8622 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8623 | tmp = fieldFromInstruction(insn, 10, 14); |
| 8624 | if (!Check(S, decodeSImmOperand<14, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8625 | return S; |
| 8626 | case 71: |
| 8627 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8628 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8629 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8630 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8631 | tmp = fieldFromInstruction(insn, 10, 12); |
| 8632 | if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8633 | return S; |
| 8634 | case 72: |
| 8635 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8636 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8637 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8638 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8639 | tmp = fieldFromInstruction(insn, 10, 12); |
| 8640 | if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8641 | return S; |
| 8642 | case 73: |
| 8643 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8644 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8645 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8646 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8647 | tmp = fieldFromInstruction(insn, 10, 12); |
| 8648 | if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8649 | return S; |
| 8650 | case 74: |
| 8651 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8652 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8653 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8654 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8655 | tmp = fieldFromInstruction(insn, 10, 12); |
| 8656 | if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8657 | return S; |
| 8658 | case 75: |
| 8659 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8660 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8661 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8662 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8663 | tmp = fieldFromInstruction(insn, 10, 9); |
| 8664 | if (!Check(S, decodeSImmOperand<9, 3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8665 | return S; |
| 8666 | case 76: |
| 8667 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8668 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8669 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8670 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8671 | tmp = fieldFromInstruction(insn, 10, 10); |
| 8672 | if (!Check(S, decodeSImmOperand<10, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8673 | return S; |
| 8674 | case 77: |
| 8675 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8676 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8677 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8678 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8679 | tmp = fieldFromInstruction(insn, 10, 11); |
| 8680 | if (!Check(S, decodeSImmOperand<11, 1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8681 | return S; |
| 8682 | case 78: |
| 8683 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8684 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8685 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8686 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8687 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8688 | if (!Check(S, decodeSImmOperand<8, 3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8689 | tmp = fieldFromInstruction(insn, 18, 1); |
| 8690 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8691 | return S; |
| 8692 | case 79: |
| 8693 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8694 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8695 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8696 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8697 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8698 | if (!Check(S, decodeSImmOperand<8, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8699 | tmp = fieldFromInstruction(insn, 18, 2); |
| 8700 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8701 | return S; |
| 8702 | case 80: |
| 8703 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8704 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8705 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8706 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8707 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8708 | if (!Check(S, decodeSImmOperand<8, 1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8709 | tmp = fieldFromInstruction(insn, 18, 3); |
| 8710 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8711 | return S; |
| 8712 | case 81: |
| 8713 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8714 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8715 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8716 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8717 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8718 | if (!Check(S, decodeSImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8719 | tmp = fieldFromInstruction(insn, 18, 4); |
| 8720 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8721 | return S; |
| 8722 | case 82: |
| 8723 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8724 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8725 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8726 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8727 | tmp = fieldFromInstruction(insn, 10, 9); |
| 8728 | if (!Check(S, decodeSImmOperand<9, 3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8729 | return S; |
| 8730 | case 83: |
| 8731 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8732 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8733 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8734 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8735 | tmp = fieldFromInstruction(insn, 10, 10); |
| 8736 | if (!Check(S, decodeSImmOperand<10, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8737 | return S; |
| 8738 | case 84: |
| 8739 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8740 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8741 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8742 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8743 | tmp = fieldFromInstruction(insn, 10, 11); |
| 8744 | if (!Check(S, decodeSImmOperand<11, 1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8745 | return S; |
| 8746 | case 85: |
| 8747 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8748 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8749 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8750 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8751 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8752 | if (!Check(S, decodeSImmOperand<8, 3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8753 | tmp = fieldFromInstruction(insn, 18, 2); |
| 8754 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8755 | return S; |
| 8756 | case 86: |
| 8757 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8758 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8759 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8760 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8761 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8762 | if (!Check(S, decodeSImmOperand<8, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8763 | tmp = fieldFromInstruction(insn, 18, 3); |
| 8764 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8765 | return S; |
| 8766 | case 87: |
| 8767 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8768 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8769 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8770 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8771 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8772 | if (!Check(S, decodeSImmOperand<8, 1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8773 | tmp = fieldFromInstruction(insn, 18, 4); |
| 8774 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8775 | return S; |
| 8776 | case 88: |
| 8777 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8778 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8779 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8780 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8781 | tmp = fieldFromInstruction(insn, 10, 8); |
| 8782 | if (!Check(S, decodeSImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8783 | tmp = fieldFromInstruction(insn, 18, 5); |
| 8784 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8785 | return S; |
| 8786 | case 89: |
| 8787 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8788 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8789 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8790 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8791 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8792 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8793 | return S; |
| 8794 | case 90: |
| 8795 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8796 | if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8797 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8798 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8799 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8800 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8801 | return S; |
| 8802 | case 91: |
| 8803 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8804 | if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8805 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8806 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8807 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8808 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8809 | return S; |
| 8810 | case 92: |
| 8811 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8812 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8813 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8814 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8815 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8816 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8817 | return S; |
| 8818 | case 93: |
| 8819 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8820 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8821 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8822 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8823 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8824 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8825 | return S; |
| 8826 | case 94: |
| 8827 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8828 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8829 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8830 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8831 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8832 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8833 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8834 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8835 | return S; |
| 8836 | case 95: |
| 8837 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8838 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8839 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8840 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8841 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8842 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8843 | return S; |
| 8844 | case 96: |
| 8845 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8846 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8847 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8848 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8849 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8850 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8851 | return S; |
| 8852 | case 97: |
| 8853 | if (!Check(S, DecodeAMOrUDInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8854 | return S; |
| 8855 | case 98: |
| 8856 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8857 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8858 | tmp = 0x0; |
| 8859 | tmp |= fieldFromInstruction(insn, 0, 5) << 16; |
| 8860 | tmp |= fieldFromInstruction(insn, 10, 16); |
| 8861 | if (!Check(S, decodeSImmOperand<21, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8862 | return S; |
| 8863 | case 99: |
| 8864 | tmp = fieldFromInstruction(insn, 5, 3); |
| 8865 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8866 | tmp = 0x0; |
| 8867 | tmp |= fieldFromInstruction(insn, 0, 5) << 16; |
| 8868 | tmp |= fieldFromInstruction(insn, 10, 16); |
| 8869 | if (!Check(S, decodeSImmOperand<21, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8870 | return S; |
| 8871 | case 100: |
| 8872 | tmp = 0x0; |
| 8873 | tmp |= fieldFromInstruction(insn, 0, 5) << 16; |
| 8874 | tmp |= fieldFromInstruction(insn, 10, 16); |
| 8875 | if (!Check(S, decodeSImmOperand<21, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8876 | return S; |
| 8877 | case 101: |
| 8878 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8879 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8880 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8881 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8882 | tmp = fieldFromInstruction(insn, 10, 16); |
| 8883 | if (!Check(S, decodeSImmOperand<16, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8884 | return S; |
| 8885 | case 102: |
| 8886 | tmp = 0x0; |
| 8887 | tmp |= fieldFromInstruction(insn, 0, 10) << 16; |
| 8888 | tmp |= fieldFromInstruction(insn, 10, 16); |
| 8889 | if (!Check(S, decodeSImmOperand<26, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8890 | return S; |
| 8891 | case 103: |
| 8892 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8893 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8894 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8895 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8896 | tmp = fieldFromInstruction(insn, 10, 16); |
| 8897 | if (!Check(S, decodeSImmOperand<16, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8898 | return S; |
| 8899 | case 104: |
| 8900 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8901 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8902 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8903 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8904 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8905 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8906 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8907 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8908 | return S; |
| 8909 | case 105: |
| 8910 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8911 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8912 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8913 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8914 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8915 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8916 | return S; |
| 8917 | case 106: |
| 8918 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8919 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8920 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8921 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8922 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8923 | if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8924 | return S; |
| 8925 | case 107: |
| 8926 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8927 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8928 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8929 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8930 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8931 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8932 | return S; |
| 8933 | case 108: |
| 8934 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8935 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8936 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8937 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8938 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8939 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8940 | tmp = fieldFromInstruction(insn, 10, 5); |
| 8941 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8942 | return S; |
| 8943 | case 109: |
| 8944 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8945 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8946 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8947 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8948 | return S; |
| 8949 | case 110: |
| 8950 | tmp = fieldFromInstruction(insn, 0, 3); |
| 8951 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8952 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8953 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8954 | return S; |
| 8955 | case 111: |
| 8956 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8957 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8958 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8959 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8960 | return S; |
| 8961 | case 112: |
| 8962 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8963 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8964 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8965 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8966 | tmp = fieldFromInstruction(insn, 10, 3); |
| 8967 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8968 | return S; |
| 8969 | case 113: |
| 8970 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8971 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8972 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8973 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8974 | tmp = fieldFromInstruction(insn, 10, 4); |
| 8975 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8976 | return S; |
| 8977 | case 114: |
| 8978 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8979 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8980 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8981 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8982 | tmp = fieldFromInstruction(insn, 10, 6); |
| 8983 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8984 | return S; |
| 8985 | case 115: |
| 8986 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8987 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8988 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8989 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8990 | tmp = fieldFromInstruction(insn, 5, 5); |
| 8991 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8992 | tmp = fieldFromInstruction(insn, 10, 4); |
| 8993 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 8994 | return S; |
| 8995 | case 116: |
| 8996 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8997 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 8998 | tmp = fieldFromInstruction(insn, 0, 5); |
| 8999 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9000 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9001 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9002 | tmp = fieldFromInstruction(insn, 10, 3); |
| 9003 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9004 | return S; |
| 9005 | case 117: |
| 9006 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9007 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9008 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9009 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9010 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9011 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9012 | tmp = fieldFromInstruction(insn, 10, 2); |
| 9013 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9014 | return S; |
| 9015 | case 118: |
| 9016 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9017 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9018 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9019 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9020 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9021 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9022 | tmp = fieldFromInstruction(insn, 10, 1); |
| 9023 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9024 | return S; |
| 9025 | case 119: |
| 9026 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9027 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9028 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9029 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9030 | tmp = fieldFromInstruction(insn, 10, 4); |
| 9031 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9032 | return S; |
| 9033 | case 120: |
| 9034 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9035 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9036 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9037 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9038 | tmp = fieldFromInstruction(insn, 10, 3); |
| 9039 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9040 | return S; |
| 9041 | case 121: |
| 9042 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9043 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9044 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9045 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9046 | tmp = fieldFromInstruction(insn, 10, 2); |
| 9047 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9048 | return S; |
| 9049 | case 122: |
| 9050 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9051 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9052 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9053 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9054 | tmp = fieldFromInstruction(insn, 10, 1); |
| 9055 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9056 | return S; |
| 9057 | case 123: |
| 9058 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9059 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9060 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9061 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9062 | tmp = fieldFromInstruction(insn, 10, 2); |
| 9063 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9064 | return S; |
| 9065 | case 124: |
| 9066 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9067 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9068 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9069 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9070 | tmp = fieldFromInstruction(insn, 10, 1); |
| 9071 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9072 | return S; |
| 9073 | case 125: |
| 9074 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9075 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9076 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9077 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9078 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9079 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9080 | tmp = fieldFromInstruction(insn, 10, 4); |
| 9081 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9082 | return S; |
| 9083 | case 126: |
| 9084 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9085 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9086 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9087 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9088 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9089 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9090 | tmp = fieldFromInstruction(insn, 10, 6); |
| 9091 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9092 | return S; |
| 9093 | case 127: |
| 9094 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9095 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9096 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9097 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9098 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9099 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9100 | tmp = fieldFromInstruction(insn, 10, 7); |
| 9101 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9102 | return S; |
| 9103 | case 128: |
| 9104 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9105 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9106 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9107 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9108 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9109 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9110 | tmp = fieldFromInstruction(insn, 10, 8); |
| 9111 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9112 | return S; |
| 9113 | case 129: |
| 9114 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9115 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9116 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9117 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9118 | tmp = fieldFromInstruction(insn, 10, 8); |
| 9119 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9120 | return S; |
| 9121 | case 130: |
| 9122 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9123 | if (!Check(S, DecodeLSX128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9124 | tmp = fieldFromInstruction(insn, 5, 13); |
| 9125 | if (!Check(S, decodeSImmOperand<13>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9126 | return S; |
| 9127 | case 131: |
| 9128 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9129 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9130 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9131 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9132 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9133 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9134 | tmp = fieldFromInstruction(insn, 10, 5); |
| 9135 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9136 | return S; |
| 9137 | case 132: |
| 9138 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9139 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9140 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9141 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9142 | tmp = fieldFromInstruction(insn, 10, 5); |
| 9143 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9144 | return S; |
| 9145 | case 133: |
| 9146 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9147 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9148 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9149 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9150 | tmp = fieldFromInstruction(insn, 10, 5); |
| 9151 | if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9152 | return S; |
| 9153 | case 134: |
| 9154 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9155 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9156 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9157 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9158 | tmp = fieldFromInstruction(insn, 10, 5); |
| 9159 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9160 | return S; |
| 9161 | case 135: |
| 9162 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9163 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9164 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9165 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9166 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9167 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9168 | tmp = fieldFromInstruction(insn, 10, 5); |
| 9169 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9170 | return S; |
| 9171 | case 136: |
| 9172 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9173 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9174 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9175 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9176 | return S; |
| 9177 | case 137: |
| 9178 | tmp = fieldFromInstruction(insn, 0, 3); |
| 9179 | if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9180 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9181 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9182 | return S; |
| 9183 | case 138: |
| 9184 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9185 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9186 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9187 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9188 | return S; |
| 9189 | case 139: |
| 9190 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9191 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9192 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9193 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9194 | tmp = fieldFromInstruction(insn, 10, 3); |
| 9195 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9196 | return S; |
| 9197 | case 140: |
| 9198 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9199 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9200 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9201 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9202 | tmp = fieldFromInstruction(insn, 10, 4); |
| 9203 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9204 | return S; |
| 9205 | case 141: |
| 9206 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9207 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9208 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9209 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9210 | tmp = fieldFromInstruction(insn, 10, 6); |
| 9211 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9212 | return S; |
| 9213 | case 142: |
| 9214 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9215 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9216 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9217 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9218 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9219 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9220 | tmp = fieldFromInstruction(insn, 10, 3); |
| 9221 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9222 | return S; |
| 9223 | case 143: |
| 9224 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9225 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9226 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9227 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9228 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9229 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9230 | tmp = fieldFromInstruction(insn, 10, 2); |
| 9231 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9232 | return S; |
| 9233 | case 144: |
| 9234 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9235 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9236 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9237 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9238 | tmp = fieldFromInstruction(insn, 10, 3); |
| 9239 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9240 | return S; |
| 9241 | case 145: |
| 9242 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9243 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9244 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9245 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9246 | tmp = fieldFromInstruction(insn, 10, 2); |
| 9247 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9248 | return S; |
| 9249 | case 146: |
| 9250 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9251 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9252 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9253 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9254 | tmp = fieldFromInstruction(insn, 10, 2); |
| 9255 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9256 | return S; |
| 9257 | case 147: |
| 9258 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9259 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9260 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9261 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9262 | tmp = fieldFromInstruction(insn, 10, 1); |
| 9263 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9264 | return S; |
| 9265 | case 148: |
| 9266 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9267 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9268 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9269 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9270 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9271 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9272 | tmp = fieldFromInstruction(insn, 10, 3); |
| 9273 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9274 | return S; |
| 9275 | case 149: |
| 9276 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9277 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9278 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9279 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9280 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9281 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9282 | tmp = fieldFromInstruction(insn, 10, 2); |
| 9283 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9284 | return S; |
| 9285 | case 150: |
| 9286 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9287 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9288 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9289 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9290 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9291 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9292 | tmp = fieldFromInstruction(insn, 10, 4); |
| 9293 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9294 | return S; |
| 9295 | case 151: |
| 9296 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9297 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9298 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9299 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9300 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9301 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9302 | tmp = fieldFromInstruction(insn, 10, 6); |
| 9303 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9304 | return S; |
| 9305 | case 152: |
| 9306 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9307 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9308 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9309 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9310 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9311 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9312 | tmp = fieldFromInstruction(insn, 10, 7); |
| 9313 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9314 | return S; |
| 9315 | case 153: |
| 9316 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9317 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9318 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9319 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9320 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9321 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9322 | tmp = fieldFromInstruction(insn, 10, 8); |
| 9323 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9324 | return S; |
| 9325 | case 154: |
| 9326 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9327 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9328 | tmp = fieldFromInstruction(insn, 5, 5); |
| 9329 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9330 | tmp = fieldFromInstruction(insn, 10, 8); |
| 9331 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 9332 | return S; |
| 9333 | case 155: |
| 9334 | tmp = fieldFromInstruction(insn, 0, 5); |
| 9335 | if (!Check(S, DecodeLASX256RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9336 | tmp = fieldFromInstruction(insn, 5, 13); |
| 9337 | if (!Check(S, decodeSImmOperand<13>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 9338 | return S; |
| 9339 | } |
| 9340 | } |
| 9341 | static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset &FB) { |
| 9342 | switch (Idx) { |
| 9343 | default: llvm_unreachable("Invalid index!"); |
| 9344 | case 0: |
| 9345 | return FB[LoongArch::Feature64Bit]; |
| 9346 | } |
| 9347 | } |
| 9348 | |
| 9349 | |
| 9350 | template <typename InsnType> |
| 9351 | static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, |
| 9352 | InsnType insn, uint64_t Address, |
| 9353 | const MCDisassembler *DisAsm, |
| 9354 | const MCSubtargetInfo &STI) { |
| 9355 | const FeatureBitset &Bits = STI.getFeatureBits(); |
| 9356 | const uint8_t *Ptr = DecodeTable; |
| 9357 | |
| 9358 | SmallVector<const uint8_t *, 8> ScopeStack; |
| 9359 | DecodeStatus S = MCDisassembler::Success; |
| 9360 | while (true) { |
| 9361 | ptrdiff_t Loc = Ptr - DecodeTable; |
| 9362 | const uint8_t DecoderOp = *Ptr++; |
| 9363 | switch (DecoderOp) { |
| 9364 | default: |
| 9365 | errs() << Loc << ": Unexpected decode table opcode: " |
| 9366 | << (int)DecoderOp << '\n'; |
| 9367 | return MCDisassembler::Fail; |
| 9368 | case OPC_Scope: { |
| 9369 | unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 9370 | const uint8_t *SkipTo = Ptr + NumToSkip; |
| 9371 | ScopeStack.push_back(Elt: SkipTo); |
| 9372 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope("<< SkipTo - DecodeTable |
| 9373 | << ")\n"); |
| 9374 | continue; |
| 9375 | } |
| 9376 | case OPC_SwitchField: { |
| 9377 | // Decode the start value. |
| 9378 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 9379 | unsigned Len = *Ptr++; |
| 9380 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 9381 | uint64_t CaseValue; |
| 9382 | unsigned CaseSize; |
| 9383 | while (true) { |
| 9384 | CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 9385 | CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 9386 | if (FieldValue == CaseValue || !CaseSize) |
| 9387 | break; |
| 9388 | Ptr += CaseSize; |
| 9389 | } |
| 9390 | if (FieldValue == CaseValue) { |
| 9391 | LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField("<< Start << ", "<< Len |
| 9392 | << "): "<< FieldValue << '\n'); |
| 9393 | continue; |
| 9394 | } |
| 9395 | break; |
| 9396 | } |
| 9397 | case OPC_CheckField: { |
| 9398 | // Decode the start value. |
| 9399 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 9400 | unsigned Len = *Ptr; |
| 9401 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 9402 | // Decode the field value. |
| 9403 | unsigned PtrLen = 0; |
| 9404 | uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen); |
| 9405 | Ptr += PtrLen; |
| 9406 | bool Failed = ExpectedValue != FieldValue; |
| 9407 | |
| 9408 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField("<< Start << ", "<< Len |
| 9409 | << ", "<< ExpectedValue << "): FieldValue = " |
| 9410 | << FieldValue << ", ExpectedValue = "<< ExpectedValue |
| 9411 | << ": "<< (Failed ? "FAIL, ": "PASS\n");); |
| 9412 | if (!Failed) |
| 9413 | continue; |
| 9414 | break; |
| 9415 | } |
| 9416 | case OPC_CheckPredicate: { |
| 9417 | // Decode the Predicate Index value. |
| 9418 | unsigned PIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 9419 | // Check the predicate. |
| 9420 | bool Failed = !checkDecoderPredicate(Idx: PIdx, FB: Bits); |
| 9421 | |
| 9422 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate("<< PIdx << "): " |
| 9423 | << (Failed ? "FAIL, ": "PASS\n");); |
| 9424 | if (!Failed) |
| 9425 | continue; |
| 9426 | break; |
| 9427 | } |
| 9428 | case OPC_Decode: { |
| 9429 | // Decode the Opcode value. |
| 9430 | unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 9431 | unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 9432 | |
| 9433 | MI.clear(); |
| 9434 | MI.setOpcode(Opc); |
| 9435 | bool DecodeComplete; |
| 9436 | S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm, |
| 9437 | DecodeComplete); |
| 9438 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode "<< Opc |
| 9439 | << ", using decoder "<< DecodeIdx << ": " |
| 9440 | << (S ? "PASS, ": "FAIL, ")); |
| 9441 | |
| 9442 | if (DecodeComplete) { |
| 9443 | LLVM_DEBUG(dbgs() << "decoding complete\n"); |
| 9444 | return S; |
| 9445 | } |
| 9446 | assert(S == MCDisassembler::Fail); |
| 9447 | // Reset decode status. This also drops a SoftFail status that could be |
| 9448 | // set before the decode attempt. |
| 9449 | S = MCDisassembler::Success; |
| 9450 | break; |
| 9451 | } |
| 9452 | } |
| 9453 | if (ScopeStack.empty()) { |
| 9454 | LLVM_DEBUG(dbgs() << "returning Fail\n"); |
| 9455 | return MCDisassembler::Fail; |
| 9456 | } |
| 9457 | Ptr = ScopeStack.pop_back_val(); |
| 9458 | LLVM_DEBUG(dbgs() << "continuing at "<< Ptr - DecodeTable << '\n'); |
| 9459 | } |
| 9460 | llvm_unreachable("bogosity detected in disassembler state machine!"); |
| 9461 | } |
| 9462 | |
| 9463 | |
| 9464 | } // namespace |
| 9465 |
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