| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t LoongArchMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(3145728), // ADC_B |
| 14 | UINT64_C(3244032), // ADC_D |
| 15 | UINT64_C(3178496), // ADC_H |
| 16 | UINT64_C(3211264), // ADC_W |
| 17 | UINT64_C(46137344), // ADDI_D |
| 18 | UINT64_C(41943040), // ADDI_W |
| 19 | UINT64_C(2719744), // ADDU12I_D |
| 20 | UINT64_C(2686976), // ADDU12I_W |
| 21 | UINT64_C(268435456), // ADDU16I_D |
| 22 | UINT64_C(1081344), // ADD_D |
| 23 | UINT64_C(1048576), // ADD_W |
| 24 | UINT64_C(2883584), // ALSL_D |
| 25 | UINT64_C(262144), // ALSL_W |
| 26 | UINT64_C(393216), // ALSL_WU |
| 27 | UINT64_C(945618944), // AMADD_B |
| 28 | UINT64_C(945913856), // AMADD_D |
| 29 | UINT64_C(945651712), // AMADD_H |
| 30 | UINT64_C(945881088), // AMADD_W |
| 31 | UINT64_C(945750016), // AMADD__DB_B |
| 32 | UINT64_C(946503680), // AMADD__DB_D |
| 33 | UINT64_C(945782784), // AMADD__DB_H |
| 34 | UINT64_C(946470912), // AMADD__DB_W |
| 35 | UINT64_C(945979392), // AMAND_D |
| 36 | UINT64_C(945946624), // AMAND_W |
| 37 | UINT64_C(946569216), // AMAND__DB_D |
| 38 | UINT64_C(946536448), // AMAND__DB_W |
| 39 | UINT64_C(945291264), // AMCAS_B |
| 40 | UINT64_C(945389568), // AMCAS_D |
| 41 | UINT64_C(945324032), // AMCAS_H |
| 42 | UINT64_C(945356800), // AMCAS_W |
| 43 | UINT64_C(945422336), // AMCAS__DB_B |
| 44 | UINT64_C(945520640), // AMCAS__DB_D |
| 45 | UINT64_C(945455104), // AMCAS__DB_H |
| 46 | UINT64_C(945487872), // AMCAS__DB_W |
| 47 | UINT64_C(946176000), // AMMAX_D |
| 48 | UINT64_C(946307072), // AMMAX_DU |
| 49 | UINT64_C(946143232), // AMMAX_W |
| 50 | UINT64_C(946274304), // AMMAX_WU |
| 51 | UINT64_C(946765824), // AMMAX__DB_D |
| 52 | UINT64_C(946896896), // AMMAX__DB_DU |
| 53 | UINT64_C(946733056), // AMMAX__DB_W |
| 54 | UINT64_C(946864128), // AMMAX__DB_WU |
| 55 | UINT64_C(946241536), // AMMIN_D |
| 56 | UINT64_C(946372608), // AMMIN_DU |
| 57 | UINT64_C(946208768), // AMMIN_W |
| 58 | UINT64_C(946339840), // AMMIN_WU |
| 59 | UINT64_C(946831360), // AMMIN__DB_D |
| 60 | UINT64_C(946962432), // AMMIN__DB_DU |
| 61 | UINT64_C(946798592), // AMMIN__DB_W |
| 62 | UINT64_C(946929664), // AMMIN__DB_WU |
| 63 | UINT64_C(946044928), // AMOR_D |
| 64 | UINT64_C(946012160), // AMOR_W |
| 65 | UINT64_C(946634752), // AMOR__DB_D |
| 66 | UINT64_C(946601984), // AMOR__DB_W |
| 67 | UINT64_C(945553408), // AMSWAP_B |
| 68 | UINT64_C(945848320), // AMSWAP_D |
| 69 | UINT64_C(945586176), // AMSWAP_H |
| 70 | UINT64_C(945815552), // AMSWAP_W |
| 71 | UINT64_C(945684480), // AMSWAP__DB_B |
| 72 | UINT64_C(946438144), // AMSWAP__DB_D |
| 73 | UINT64_C(945717248), // AMSWAP__DB_H |
| 74 | UINT64_C(946405376), // AMSWAP__DB_W |
| 75 | UINT64_C(946110464), // AMXOR_D |
| 76 | UINT64_C(946077696), // AMXOR_W |
| 77 | UINT64_C(946700288), // AMXOR__DB_D |
| 78 | UINT64_C(946667520), // AMXOR__DB_W |
| 79 | UINT64_C(1343488), // AND |
| 80 | UINT64_C(54525952), // ANDI |
| 81 | UINT64_C(1474560), // ANDN |
| 82 | UINT64_C(3670032), // ARMADC_W |
| 83 | UINT64_C(3604496), // ARMADD_W |
| 84 | UINT64_C(3735568), // ARMAND_W |
| 85 | UINT64_C(6029376), // ARMMFFLAG |
| 86 | UINT64_C(3555328), // ARMMOVE |
| 87 | UINT64_C(4177950), // ARMMOV_D |
| 88 | UINT64_C(4177949), // ARMMOV_W |
| 89 | UINT64_C(6029408), // ARMMTFLAG |
| 90 | UINT64_C(4177948), // ARMNOT_W |
| 91 | UINT64_C(3768336), // ARMOR_W |
| 92 | UINT64_C(4063248), // ARMROTRI_W |
| 93 | UINT64_C(3932176), // ARMROTR_W |
| 94 | UINT64_C(4177951), // ARMRRX_W |
| 95 | UINT64_C(3702800), // ARMSBC_W |
| 96 | UINT64_C(3964944), // ARMSLLI_W |
| 97 | UINT64_C(3833872), // ARMSLL_W |
| 98 | UINT64_C(4030480), // ARMSRAI_W |
| 99 | UINT64_C(3899408), // ARMSRA_W |
| 100 | UINT64_C(3997712), // ARMSRLI_W |
| 101 | UINT64_C(3866640), // ARMSRL_W |
| 102 | UINT64_C(3637264), // ARMSUB_W |
| 103 | UINT64_C(3801104), // ARMXOR_W |
| 104 | UINT64_C(98304), // ASRTGT_D |
| 105 | UINT64_C(65536), // ASRTLE_D |
| 106 | UINT64_C(1342177280), // B |
| 107 | UINT64_C(1207959552), // BCEQZ |
| 108 | UINT64_C(1207959808), // BCNEZ |
| 109 | UINT64_C(1476395008), // BEQ |
| 110 | UINT64_C(1073741824), // BEQZ |
| 111 | UINT64_C(1677721600), // BGE |
| 112 | UINT64_C(1811939328), // BGEU |
| 113 | UINT64_C(18432), // BITREV_4B |
| 114 | UINT64_C(19456), // BITREV_8B |
| 115 | UINT64_C(21504), // BITREV_D |
| 116 | UINT64_C(20480), // BITREV_W |
| 117 | UINT64_C(1409286144), // BL |
| 118 | UINT64_C(1610612736), // BLT |
| 119 | UINT64_C(1744830464), // BLTU |
| 120 | UINT64_C(1543503872), // BNE |
| 121 | UINT64_C(1140850688), // BNEZ |
| 122 | UINT64_C(2752512), // BREAK |
| 123 | UINT64_C(8388608), // BSTRINS_D |
| 124 | UINT64_C(6291456), // BSTRINS_W |
| 125 | UINT64_C(12582912), // BSTRPICK_D |
| 126 | UINT64_C(6324224), // BSTRPICK_W |
| 127 | UINT64_C(786432), // BYTEPICK_D |
| 128 | UINT64_C(524288), // BYTEPICK_W |
| 129 | UINT64_C(100663296), // CACOP |
| 130 | UINT64_C(8192), // CLO_D |
| 131 | UINT64_C(4096), // CLO_W |
| 132 | UINT64_C(9216), // CLZ_D |
| 133 | UINT64_C(5120), // CLZ_W |
| 134 | UINT64_C(27648), // CPUCFG |
| 135 | UINT64_C(2490368), // CRCC_W_B_W |
| 136 | UINT64_C(2588672), // CRCC_W_D_W |
| 137 | UINT64_C(2523136), // CRCC_W_H_W |
| 138 | UINT64_C(2555904), // CRCC_W_W_W |
| 139 | UINT64_C(2359296), // CRC_W_B_W |
| 140 | UINT64_C(2457600), // CRC_W_D_W |
| 141 | UINT64_C(2392064), // CRC_W_H_W |
| 142 | UINT64_C(2424832), // CRC_W_W_W |
| 143 | UINT64_C(67108864), // CSRRD |
| 144 | UINT64_C(67108896), // CSRWR |
| 145 | UINT64_C(67108864), // CSRXCHG |
| 146 | UINT64_C(10240), // CTO_D |
| 147 | UINT64_C(6144), // CTO_W |
| 148 | UINT64_C(11264), // CTZ_D |
| 149 | UINT64_C(7168), // CTZ_W |
| 150 | UINT64_C(946995200), // DBAR |
| 151 | UINT64_C(2785280), // DBCL |
| 152 | UINT64_C(2228224), // DIV_D |
| 153 | UINT64_C(2293760), // DIV_DU |
| 154 | UINT64_C(2097152), // DIV_W |
| 155 | UINT64_C(2162688), // DIV_WU |
| 156 | UINT64_C(105396224), // ERTN |
| 157 | UINT64_C(23552), // EXT_W_B |
| 158 | UINT64_C(22528), // EXT_W_H |
| 159 | UINT64_C(18089984), // FABS_D |
| 160 | UINT64_C(18088960), // FABS_S |
| 161 | UINT64_C(16842752), // FADD_D |
| 162 | UINT64_C(16809984), // FADD_S |
| 163 | UINT64_C(18102272), // FCLASS_D |
| 164 | UINT64_C(18101248), // FCLASS_S |
| 165 | UINT64_C(203423744), // FCMP_CAF_D |
| 166 | UINT64_C(202375168), // FCMP_CAF_S |
| 167 | UINT64_C(203554816), // FCMP_CEQ_D |
| 168 | UINT64_C(202506240), // FCMP_CEQ_S |
| 169 | UINT64_C(203620352), // FCMP_CLE_D |
| 170 | UINT64_C(202571776), // FCMP_CLE_S |
| 171 | UINT64_C(203489280), // FCMP_CLT_D |
| 172 | UINT64_C(202440704), // FCMP_CLT_S |
| 173 | UINT64_C(203948032), // FCMP_CNE_D |
| 174 | UINT64_C(202899456), // FCMP_CNE_S |
| 175 | UINT64_C(204079104), // FCMP_COR_D |
| 176 | UINT64_C(203030528), // FCMP_COR_S |
| 177 | UINT64_C(203816960), // FCMP_CUEQ_D |
| 178 | UINT64_C(202768384), // FCMP_CUEQ_S |
| 179 | UINT64_C(203882496), // FCMP_CULE_D |
| 180 | UINT64_C(202833920), // FCMP_CULE_S |
| 181 | UINT64_C(203751424), // FCMP_CULT_D |
| 182 | UINT64_C(202702848), // FCMP_CULT_S |
| 183 | UINT64_C(204210176), // FCMP_CUNE_D |
| 184 | UINT64_C(203161600), // FCMP_CUNE_S |
| 185 | UINT64_C(203685888), // FCMP_CUN_D |
| 186 | UINT64_C(202637312), // FCMP_CUN_S |
| 187 | UINT64_C(203456512), // FCMP_SAF_D |
| 188 | UINT64_C(202407936), // FCMP_SAF_S |
| 189 | UINT64_C(203587584), // FCMP_SEQ_D |
| 190 | UINT64_C(202539008), // FCMP_SEQ_S |
| 191 | UINT64_C(203653120), // FCMP_SLE_D |
| 192 | UINT64_C(202604544), // FCMP_SLE_S |
| 193 | UINT64_C(203522048), // FCMP_SLT_D |
| 194 | UINT64_C(202473472), // FCMP_SLT_S |
| 195 | UINT64_C(203980800), // FCMP_SNE_D |
| 196 | UINT64_C(202932224), // FCMP_SNE_S |
| 197 | UINT64_C(204111872), // FCMP_SOR_D |
| 198 | UINT64_C(203063296), // FCMP_SOR_S |
| 199 | UINT64_C(203849728), // FCMP_SUEQ_D |
| 200 | UINT64_C(202801152), // FCMP_SUEQ_S |
| 201 | UINT64_C(203915264), // FCMP_SULE_D |
| 202 | UINT64_C(202866688), // FCMP_SULE_S |
| 203 | UINT64_C(203784192), // FCMP_SULT_D |
| 204 | UINT64_C(202735616), // FCMP_SULT_S |
| 205 | UINT64_C(204242944), // FCMP_SUNE_D |
| 206 | UINT64_C(203194368), // FCMP_SUNE_S |
| 207 | UINT64_C(203718656), // FCMP_SUN_D |
| 208 | UINT64_C(202670080), // FCMP_SUN_S |
| 209 | UINT64_C(18022400), // FCOPYSIGN_D |
| 210 | UINT64_C(17989632), // FCOPYSIGN_S |
| 211 | UINT64_C(18153472), // FCVT_D_LD |
| 212 | UINT64_C(18424832), // FCVT_D_S |
| 213 | UINT64_C(18145280), // FCVT_LD_D |
| 214 | UINT64_C(18421760), // FCVT_S_D |
| 215 | UINT64_C(18146304), // FCVT_UD_D |
| 216 | UINT64_C(17235968), // FDIV_D |
| 217 | UINT64_C(17203200), // FDIV_S |
| 218 | UINT64_C(18688000), // FFINT_D_L |
| 219 | UINT64_C(18685952), // FFINT_D_W |
| 220 | UINT64_C(18683904), // FFINT_S_L |
| 221 | UINT64_C(18681856), // FFINT_S_W |
| 222 | UINT64_C(947159040), // FLDGT_D |
| 223 | UINT64_C(947126272), // FLDGT_S |
| 224 | UINT64_C(947224576), // FLDLE_D |
| 225 | UINT64_C(947191808), // FLDLE_S |
| 226 | UINT64_C(942931968), // FLDX_D |
| 227 | UINT64_C(942669824), // FLDX_S |
| 228 | UINT64_C(729808896), // FLD_D |
| 229 | UINT64_C(721420288), // FLD_S |
| 230 | UINT64_C(18098176), // FLOGB_D |
| 231 | UINT64_C(18097152), // FLOGB_S |
| 232 | UINT64_C(136314880), // FMADD_D |
| 233 | UINT64_C(135266304), // FMADD_S |
| 234 | UINT64_C(17629184), // FMAXA_D |
| 235 | UINT64_C(17596416), // FMAXA_S |
| 236 | UINT64_C(17367040), // FMAX_D |
| 237 | UINT64_C(17334272), // FMAX_S |
| 238 | UINT64_C(17760256), // FMINA_D |
| 239 | UINT64_C(17727488), // FMINA_S |
| 240 | UINT64_C(17498112), // FMIN_D |
| 241 | UINT64_C(17465344), // FMIN_S |
| 242 | UINT64_C(18126848), // FMOV_D |
| 243 | UINT64_C(18125824), // FMOV_S |
| 244 | UINT64_C(140509184), // FMSUB_D |
| 245 | UINT64_C(139460608), // FMSUB_S |
| 246 | UINT64_C(17104896), // FMUL_D |
| 247 | UINT64_C(17072128), // FMUL_S |
| 248 | UINT64_C(18094080), // FNEG_D |
| 249 | UINT64_C(18093056), // FNEG_S |
| 250 | UINT64_C(144703488), // FNMADD_D |
| 251 | UINT64_C(143654912), // FNMADD_S |
| 252 | UINT64_C(148897792), // FNMSUB_D |
| 253 | UINT64_C(147849216), // FNMSUB_S |
| 254 | UINT64_C(18118656), // FRECIPE_D |
| 255 | UINT64_C(18117632), // FRECIPE_S |
| 256 | UINT64_C(18110464), // FRECIP_D |
| 257 | UINT64_C(18109440), // FRECIP_S |
| 258 | UINT64_C(18761728), // FRINT_D |
| 259 | UINT64_C(18760704), // FRINT_S |
| 260 | UINT64_C(18122752), // FRSQRTE_D |
| 261 | UINT64_C(18121728), // FRSQRTE_S |
| 262 | UINT64_C(18114560), // FRSQRT_D |
| 263 | UINT64_C(18113536), // FRSQRT_S |
| 264 | UINT64_C(17891328), // FSCALEB_D |
| 265 | UINT64_C(17858560), // FSCALEB_S |
| 266 | UINT64_C(218103808), // FSEL_xD |
| 267 | UINT64_C(218103808), // FSEL_xS |
| 268 | UINT64_C(18106368), // FSQRT_D |
| 269 | UINT64_C(18105344), // FSQRT_S |
| 270 | UINT64_C(947290112), // FSTGT_D |
| 271 | UINT64_C(947257344), // FSTGT_S |
| 272 | UINT64_C(947355648), // FSTLE_D |
| 273 | UINT64_C(947322880), // FSTLE_S |
| 274 | UINT64_C(943456256), // FSTX_D |
| 275 | UINT64_C(943194112), // FSTX_S |
| 276 | UINT64_C(734003200), // FST_D |
| 277 | UINT64_C(725614592), // FST_S |
| 278 | UINT64_C(16973824), // FSUB_D |
| 279 | UINT64_C(16941056), // FSUB_S |
| 280 | UINT64_C(18491392), // FTINTRM_L_D |
| 281 | UINT64_C(18490368), // FTINTRM_L_S |
| 282 | UINT64_C(18483200), // FTINTRM_W_D |
| 283 | UINT64_C(18482176), // FTINTRM_W_S |
| 284 | UINT64_C(18540544), // FTINTRNE_L_D |
| 285 | UINT64_C(18539520), // FTINTRNE_L_S |
| 286 | UINT64_C(18532352), // FTINTRNE_W_D |
| 287 | UINT64_C(18531328), // FTINTRNE_W_S |
| 288 | UINT64_C(18507776), // FTINTRP_L_D |
| 289 | UINT64_C(18506752), // FTINTRP_L_S |
| 290 | UINT64_C(18499584), // FTINTRP_W_D |
| 291 | UINT64_C(18498560), // FTINTRP_W_S |
| 292 | UINT64_C(18524160), // FTINTRZ_L_D |
| 293 | UINT64_C(18523136), // FTINTRZ_L_S |
| 294 | UINT64_C(18515968), // FTINTRZ_W_D |
| 295 | UINT64_C(18514944), // FTINTRZ_W_S |
| 296 | UINT64_C(18556928), // FTINT_L_D |
| 297 | UINT64_C(18555904), // FTINT_L_S |
| 298 | UINT64_C(18548736), // FTINT_W_D |
| 299 | UINT64_C(18547712), // FTINT_W_S |
| 300 | UINT64_C(83886080), // GCSRRD |
| 301 | UINT64_C(83886112), // GCSRWR |
| 302 | UINT64_C(83886080), // GCSRXCHG |
| 303 | UINT64_C(105391105), // GTLBFLUSH |
| 304 | UINT64_C(2850816), // HVCL |
| 305 | UINT64_C(947027968), // IBAR |
| 306 | UINT64_C(105414656), // IDLE |
| 307 | UINT64_C(105480192), // INVTLB |
| 308 | UINT64_C(105381888), // IOCSRRD_B |
| 309 | UINT64_C(105384960), // IOCSRRD_D |
| 310 | UINT64_C(105382912), // IOCSRRD_H |
| 311 | UINT64_C(105383936), // IOCSRRD_W |
| 312 | UINT64_C(105385984), // IOCSRWR_B |
| 313 | UINT64_C(105389056), // IOCSRWR_D |
| 314 | UINT64_C(105387008), // IOCSRWR_H |
| 315 | UINT64_C(105388032), // IOCSRWR_W |
| 316 | UINT64_C(1275068416), // JIRL |
| 317 | UINT64_C(1207960064), // JISCR0 |
| 318 | UINT64_C(1207960320), // JISCR1 |
| 319 | UINT64_C(104857600), // LDDIR |
| 320 | UINT64_C(947388416), // LDGT_B |
| 321 | UINT64_C(947486720), // LDGT_D |
| 322 | UINT64_C(947421184), // LDGT_H |
| 323 | UINT64_C(947453952), // LDGT_W |
| 324 | UINT64_C(947519488), // LDLE_B |
| 325 | UINT64_C(947617792), // LDLE_D |
| 326 | UINT64_C(947552256), // LDLE_H |
| 327 | UINT64_C(947585024), // LDLE_W |
| 328 | UINT64_C(780140544), // LDL_D |
| 329 | UINT64_C(771751936), // LDL_W |
| 330 | UINT64_C(105119744), // LDPTE |
| 331 | UINT64_C(637534208), // LDPTR_D |
| 332 | UINT64_C(603979776), // LDPTR_W |
| 333 | UINT64_C(784334848), // LDR_D |
| 334 | UINT64_C(775946240), // LDR_W |
| 335 | UINT64_C(939524096), // LDX_B |
| 336 | UINT64_C(941621248), // LDX_BU |
| 337 | UINT64_C(940310528), // LDX_D |
| 338 | UINT64_C(939786240), // LDX_H |
| 339 | UINT64_C(941883392), // LDX_HU |
| 340 | UINT64_C(940048384), // LDX_W |
| 341 | UINT64_C(942145536), // LDX_WU |
| 342 | UINT64_C(671088640), // LD_B |
| 343 | UINT64_C(704643072), // LD_BU |
| 344 | UINT64_C(683671552), // LD_D |
| 345 | UINT64_C(675282944), // LD_H |
| 346 | UINT64_C(708837376), // LD_HU |
| 347 | UINT64_C(679477248), // LD_W |
| 348 | UINT64_C(713031680), // LD_WU |
| 349 | UINT64_C(945260544), // LLACQ_D |
| 350 | UINT64_C(945258496), // LLACQ_W |
| 351 | UINT64_C(570425344), // LL_D |
| 352 | UINT64_C(536870912), // LL_W |
| 353 | UINT64_C(335544320), // LU12I_W |
| 354 | UINT64_C(369098752), // LU32I_D |
| 355 | UINT64_C(50331648), // LU52I_D |
| 356 | UINT64_C(1245184), // MASKEQZ |
| 357 | UINT64_C(1277952), // MASKNEZ |
| 358 | UINT64_C(2260992), // MOD_D |
| 359 | UINT64_C(2326528), // MOD_DU |
| 360 | UINT64_C(2129920), // MOD_W |
| 361 | UINT64_C(2195456), // MOD_WU |
| 362 | UINT64_C(18142208), // MOVCF2FR_xS |
| 363 | UINT64_C(18144256), // MOVCF2GR |
| 364 | UINT64_C(18139136), // MOVFCSR2GR |
| 365 | UINT64_C(18141184), // MOVFR2CF_xS |
| 366 | UINT64_C(18135040), // MOVFR2GR_D |
| 367 | UINT64_C(18134016), // MOVFR2GR_S |
| 368 | UINT64_C(18134016), // MOVFR2GR_S_64 |
| 369 | UINT64_C(18136064), // MOVFRH2GR_S |
| 370 | UINT64_C(18143232), // MOVGR2CF |
| 371 | UINT64_C(18137088), // MOVGR2FCSR |
| 372 | UINT64_C(18131968), // MOVGR2FRH_W |
| 373 | UINT64_C(18130944), // MOVGR2FR_D |
| 374 | UINT64_C(18129920), // MOVGR2FR_W |
| 375 | UINT64_C(18129920), // MOVGR2FR_W_64 |
| 376 | UINT64_C(2048), // MOVGR2SCR |
| 377 | UINT64_C(3072), // MOVSCR2GR |
| 378 | UINT64_C(1966080), // MULH_D |
| 379 | UINT64_C(1998848), // MULH_DU |
| 380 | UINT64_C(1867776), // MULH_W |
| 381 | UINT64_C(1900544), // MULH_WU |
| 382 | UINT64_C(2031616), // MULW_D_W |
| 383 | UINT64_C(2064384), // MULW_D_WU |
| 384 | UINT64_C(1933312), // MUL_D |
| 385 | UINT64_C(1835008), // MUL_W |
| 386 | UINT64_C(1310720), // NOR |
| 387 | UINT64_C(1376256), // OR |
| 388 | UINT64_C(58720256), // ORI |
| 389 | UINT64_C(1441792), // ORN |
| 390 | UINT64_C(402653184), // PCADDI |
| 391 | UINT64_C(469762048), // PCADDU12I |
| 392 | UINT64_C(503316480), // PCADDU18I |
| 393 | UINT64_C(436207616), // PCALAU12I |
| 394 | UINT64_C(717225984), // PRELD |
| 395 | UINT64_C(942407680), // PRELDX |
| 396 | UINT64_C(5251072), // RCRI_B |
| 397 | UINT64_C(5308416), // RCRI_D |
| 398 | UINT64_C(5259264), // RCRI_H |
| 399 | UINT64_C(5275648), // RCRI_W |
| 400 | UINT64_C(3407872), // RCR_B |
| 401 | UINT64_C(3506176), // RCR_D |
| 402 | UINT64_C(3440640), // RCR_H |
| 403 | UINT64_C(3473408), // RCR_W |
| 404 | UINT64_C(25600), // RDTIMEH_W |
| 405 | UINT64_C(24576), // RDTIMEL_W |
| 406 | UINT64_C(26624), // RDTIME_D |
| 407 | UINT64_C(12288), // REVB_2H |
| 408 | UINT64_C(14336), // REVB_2W |
| 409 | UINT64_C(13312), // REVB_4H |
| 410 | UINT64_C(15360), // REVB_D |
| 411 | UINT64_C(16384), // REVH_2W |
| 412 | UINT64_C(17408), // REVH_D |
| 413 | UINT64_C(4988928), // ROTRI_B |
| 414 | UINT64_C(5046272), // ROTRI_D |
| 415 | UINT64_C(4997120), // ROTRI_H |
| 416 | UINT64_C(5013504), // ROTRI_W |
| 417 | UINT64_C(1703936), // ROTR_B |
| 418 | UINT64_C(1802240), // ROTR_D |
| 419 | UINT64_C(1736704), // ROTR_H |
| 420 | UINT64_C(1769472), // ROTR_W |
| 421 | UINT64_C(3276800), // SBC_B |
| 422 | UINT64_C(3375104), // SBC_D |
| 423 | UINT64_C(3309568), // SBC_H |
| 424 | UINT64_C(3342336), // SBC_W |
| 425 | UINT64_C(945261568), // SCREL_D |
| 426 | UINT64_C(945259520), // SCREL_W |
| 427 | UINT64_C(587202560), // SC_D |
| 428 | UINT64_C(945225728), // SC_Q |
| 429 | UINT64_C(553648128), // SC_W |
| 430 | UINT64_C(3588096), // SETARMJ |
| 431 | UINT64_C(3571712), // SETX86J |
| 432 | UINT64_C(30720), // SETX86LOOPE |
| 433 | UINT64_C(31744), // SETX86LOOPNE |
| 434 | UINT64_C(202375168), // SET_CFR_FALSE |
| 435 | UINT64_C(202768384), // SET_CFR_TRUE |
| 436 | UINT64_C(4259840), // SLLI_D |
| 437 | UINT64_C(4227072), // SLLI_W |
| 438 | UINT64_C(1605632), // SLL_D |
| 439 | UINT64_C(1507328), // SLL_W |
| 440 | UINT64_C(1179648), // SLT |
| 441 | UINT64_C(33554432), // SLTI |
| 442 | UINT64_C(1212416), // SLTU |
| 443 | UINT64_C(37748736), // SLTUI |
| 444 | UINT64_C(4784128), // SRAI_D |
| 445 | UINT64_C(4751360), // SRAI_W |
| 446 | UINT64_C(1671168), // SRA_D |
| 447 | UINT64_C(1572864), // SRA_W |
| 448 | UINT64_C(4521984), // SRLI_D |
| 449 | UINT64_C(4489216), // SRLI_W |
| 450 | UINT64_C(1638400), // SRL_D |
| 451 | UINT64_C(1540096), // SRL_W |
| 452 | UINT64_C(947650560), // STGT_B |
| 453 | UINT64_C(947748864), // STGT_D |
| 454 | UINT64_C(947683328), // STGT_H |
| 455 | UINT64_C(947716096), // STGT_W |
| 456 | UINT64_C(947781632), // STLE_B |
| 457 | UINT64_C(947879936), // STLE_D |
| 458 | UINT64_C(947814400), // STLE_H |
| 459 | UINT64_C(947847168), // STLE_W |
| 460 | UINT64_C(796917760), // STL_D |
| 461 | UINT64_C(788529152), // STL_W |
| 462 | UINT64_C(654311424), // STPTR_D |
| 463 | UINT64_C(620756992), // STPTR_W |
| 464 | UINT64_C(801112064), // STR_D |
| 465 | UINT64_C(792723456), // STR_W |
| 466 | UINT64_C(940572672), // STX_B |
| 467 | UINT64_C(941359104), // STX_D |
| 468 | UINT64_C(940834816), // STX_H |
| 469 | UINT64_C(941096960), // STX_W |
| 470 | UINT64_C(687865856), // ST_B |
| 471 | UINT64_C(700448768), // ST_D |
| 472 | UINT64_C(692060160), // ST_H |
| 473 | UINT64_C(696254464), // ST_W |
| 474 | UINT64_C(1146880), // SUB_D |
| 475 | UINT64_C(1114112), // SUB_W |
| 476 | UINT64_C(2818048), // SYSCALL |
| 477 | UINT64_C(105390080), // TLBCLR |
| 478 | UINT64_C(105395200), // TLBFILL |
| 479 | UINT64_C(105391104), // TLBFLUSH |
| 480 | UINT64_C(105393152), // TLBRD |
| 481 | UINT64_C(105392128), // TLBSRCH |
| 482 | UINT64_C(105394176), // TLBWR |
| 483 | UINT64_C(945816576), // UD |
| 484 | UINT64_C(1885339648), // VABSD_B |
| 485 | UINT64_C(1885470720), // VABSD_BU |
| 486 | UINT64_C(1885437952), // VABSD_D |
| 487 | UINT64_C(1885569024), // VABSD_DU |
| 488 | UINT64_C(1885372416), // VABSD_H |
| 489 | UINT64_C(1885503488), // VABSD_HU |
| 490 | UINT64_C(1885405184), // VABSD_W |
| 491 | UINT64_C(1885536256), // VABSD_WU |
| 492 | UINT64_C(1885077504), // VADDA_B |
| 493 | UINT64_C(1885175808), // VADDA_D |
| 494 | UINT64_C(1885110272), // VADDA_H |
| 495 | UINT64_C(1885143040), // VADDA_W |
| 496 | UINT64_C(1921646592), // VADDI_BU |
| 497 | UINT64_C(1921744896), // VADDI_DU |
| 498 | UINT64_C(1921679360), // VADDI_HU |
| 499 | UINT64_C(1921712128), // VADDI_WU |
| 500 | UINT64_C(1881079808), // VADDWEV_D_W |
| 501 | UINT64_C(1882128384), // VADDWEV_D_WU |
| 502 | UINT64_C(1883176960), // VADDWEV_D_WU_W |
| 503 | UINT64_C(1881014272), // VADDWEV_H_B |
| 504 | UINT64_C(1882062848), // VADDWEV_H_BU |
| 505 | UINT64_C(1883111424), // VADDWEV_H_BU_B |
| 506 | UINT64_C(1881112576), // VADDWEV_Q_D |
| 507 | UINT64_C(1882161152), // VADDWEV_Q_DU |
| 508 | UINT64_C(1883209728), // VADDWEV_Q_DU_D |
| 509 | UINT64_C(1881047040), // VADDWEV_W_H |
| 510 | UINT64_C(1882095616), // VADDWEV_W_HU |
| 511 | UINT64_C(1883144192), // VADDWEV_W_HU_H |
| 512 | UINT64_C(1881341952), // VADDWOD_D_W |
| 513 | UINT64_C(1882390528), // VADDWOD_D_WU |
| 514 | UINT64_C(1883308032), // VADDWOD_D_WU_W |
| 515 | UINT64_C(1881276416), // VADDWOD_H_B |
| 516 | UINT64_C(1882324992), // VADDWOD_H_BU |
| 517 | UINT64_C(1883242496), // VADDWOD_H_BU_B |
| 518 | UINT64_C(1881374720), // VADDWOD_Q_D |
| 519 | UINT64_C(1882423296), // VADDWOD_Q_DU |
| 520 | UINT64_C(1883340800), // VADDWOD_Q_DU_D |
| 521 | UINT64_C(1881309184), // VADDWOD_W_H |
| 522 | UINT64_C(1882357760), // VADDWOD_W_HU |
| 523 | UINT64_C(1883275264), // VADDWOD_W_HU_H |
| 524 | UINT64_C(1879703552), // VADD_B |
| 525 | UINT64_C(1879801856), // VADD_D |
| 526 | UINT64_C(1879736320), // VADD_H |
| 527 | UINT64_C(1898774528), // VADD_Q |
| 528 | UINT64_C(1879769088), // VADD_W |
| 529 | UINT64_C(1943011328), // VANDI_B |
| 530 | UINT64_C(1898446848), // VANDN_V |
| 531 | UINT64_C(1898315776), // VAND_V |
| 532 | UINT64_C(1885863936), // VAVGR_B |
| 533 | UINT64_C(1885995008), // VAVGR_BU |
| 534 | UINT64_C(1885962240), // VAVGR_D |
| 535 | UINT64_C(1886093312), // VAVGR_DU |
| 536 | UINT64_C(1885896704), // VAVGR_H |
| 537 | UINT64_C(1886027776), // VAVGR_HU |
| 538 | UINT64_C(1885929472), // VAVGR_W |
| 539 | UINT64_C(1886060544), // VAVGR_WU |
| 540 | UINT64_C(1885601792), // VAVG_B |
| 541 | UINT64_C(1885732864), // VAVG_BU |
| 542 | UINT64_C(1885700096), // VAVG_D |
| 543 | UINT64_C(1885831168), // VAVG_DU |
| 544 | UINT64_C(1885634560), // VAVG_H |
| 545 | UINT64_C(1885765632), // VAVG_HU |
| 546 | UINT64_C(1885667328), // VAVG_W |
| 547 | UINT64_C(1885798400), // VAVG_WU |
| 548 | UINT64_C(1930436608), // VBITCLRI_B |
| 549 | UINT64_C(1930493952), // VBITCLRI_D |
| 550 | UINT64_C(1930444800), // VBITCLRI_H |
| 551 | UINT64_C(1930461184), // VBITCLRI_W |
| 552 | UINT64_C(1896611840), // VBITCLR_B |
| 553 | UINT64_C(1896710144), // VBITCLR_D |
| 554 | UINT64_C(1896644608), // VBITCLR_H |
| 555 | UINT64_C(1896677376), // VBITCLR_W |
| 556 | UINT64_C(1930960896), // VBITREVI_B |
| 557 | UINT64_C(1931018240), // VBITREVI_D |
| 558 | UINT64_C(1930969088), // VBITREVI_H |
| 559 | UINT64_C(1930985472), // VBITREVI_W |
| 560 | UINT64_C(1896873984), // VBITREV_B |
| 561 | UINT64_C(1896972288), // VBITREV_D |
| 562 | UINT64_C(1896906752), // VBITREV_H |
| 563 | UINT64_C(1896939520), // VBITREV_W |
| 564 | UINT64_C(1942224896), // VBITSELI_B |
| 565 | UINT64_C(219152384), // VBITSEL_V |
| 566 | UINT64_C(1930698752), // VBITSETI_B |
| 567 | UINT64_C(1930756096), // VBITSETI_D |
| 568 | UINT64_C(1930706944), // VBITSETI_H |
| 569 | UINT64_C(1930723328), // VBITSETI_W |
| 570 | UINT64_C(1896742912), // VBITSET_B |
| 571 | UINT64_C(1896841216), // VBITSET_D |
| 572 | UINT64_C(1896775680), // VBITSET_H |
| 573 | UINT64_C(1896808448), // VBITSET_W |
| 574 | UINT64_C(1921908736), // VBSLL_V |
| 575 | UINT64_C(1921941504), // VBSRL_V |
| 576 | UINT64_C(1922826240), // VCLO_B |
| 577 | UINT64_C(1922829312), // VCLO_D |
| 578 | UINT64_C(1922827264), // VCLO_H |
| 579 | UINT64_C(1922828288), // VCLO_W |
| 580 | UINT64_C(1922830336), // VCLZ_B |
| 581 | UINT64_C(1922833408), // VCLZ_D |
| 582 | UINT64_C(1922831360), // VCLZ_H |
| 583 | UINT64_C(1922832384), // VCLZ_W |
| 584 | UINT64_C(1893728256), // VDIV_B |
| 585 | UINT64_C(1893990400), // VDIV_BU |
| 586 | UINT64_C(1893826560), // VDIV_D |
| 587 | UINT64_C(1894088704), // VDIV_DU |
| 588 | UINT64_C(1893761024), // VDIV_H |
| 589 | UINT64_C(1894023168), // VDIV_HU |
| 590 | UINT64_C(1893793792), // VDIV_W |
| 591 | UINT64_C(1894055936), // VDIV_WU |
| 592 | UINT64_C(1990144000), // VEXT2XV_DU_BU |
| 593 | UINT64_C(1990146048), // VEXT2XV_DU_HU |
| 594 | UINT64_C(1990147072), // VEXT2XV_DU_WU |
| 595 | UINT64_C(1990137856), // VEXT2XV_D_B |
| 596 | UINT64_C(1990139904), // VEXT2XV_D_H |
| 597 | UINT64_C(1990140928), // VEXT2XV_D_W |
| 598 | UINT64_C(1990141952), // VEXT2XV_HU_BU |
| 599 | UINT64_C(1990135808), // VEXT2XV_H_B |
| 600 | UINT64_C(1990142976), // VEXT2XV_WU_BU |
| 601 | UINT64_C(1990145024), // VEXT2XV_WU_HU |
| 602 | UINT64_C(1990136832), // VEXT2XV_W_B |
| 603 | UINT64_C(1990138880), // VEXT2XV_W_H |
| 604 | UINT64_C(1923020800), // VEXTH_DU_WU |
| 605 | UINT64_C(1923016704), // VEXTH_D_W |
| 606 | UINT64_C(1923018752), // VEXTH_HU_BU |
| 607 | UINT64_C(1923014656), // VEXTH_H_B |
| 608 | UINT64_C(1923021824), // VEXTH_QU_DU |
| 609 | UINT64_C(1923017728), // VEXTH_Q_D |
| 610 | UINT64_C(1923019776), // VEXTH_WU_HU |
| 611 | UINT64_C(1923015680), // VEXTH_W_H |
| 612 | UINT64_C(1930231808), // VEXTL_QU_DU |
| 613 | UINT64_C(1929969664), // VEXTL_Q_D |
| 614 | UINT64_C(1938554880), // VEXTRINS_B |
| 615 | UINT64_C(1937768448), // VEXTRINS_D |
| 616 | UINT64_C(1938292736), // VEXTRINS_H |
| 617 | UINT64_C(1938030592), // VEXTRINS_W |
| 618 | UINT64_C(1899036672), // VFADD_D |
| 619 | UINT64_C(1899003904), // VFADD_S |
| 620 | UINT64_C(1922881536), // VFCLASS_D |
| 621 | UINT64_C(1922880512), // VFCLASS_S |
| 622 | UINT64_C(207618048), // VFCMP_CAF_D |
| 623 | UINT64_C(206569472), // VFCMP_CAF_S |
| 624 | UINT64_C(207749120), // VFCMP_CEQ_D |
| 625 | UINT64_C(206700544), // VFCMP_CEQ_S |
| 626 | UINT64_C(207814656), // VFCMP_CLE_D |
| 627 | UINT64_C(206766080), // VFCMP_CLE_S |
| 628 | UINT64_C(207683584), // VFCMP_CLT_D |
| 629 | UINT64_C(206635008), // VFCMP_CLT_S |
| 630 | UINT64_C(208142336), // VFCMP_CNE_D |
| 631 | UINT64_C(207093760), // VFCMP_CNE_S |
| 632 | UINT64_C(208273408), // VFCMP_COR_D |
| 633 | UINT64_C(207224832), // VFCMP_COR_S |
| 634 | UINT64_C(208011264), // VFCMP_CUEQ_D |
| 635 | UINT64_C(206962688), // VFCMP_CUEQ_S |
| 636 | UINT64_C(208076800), // VFCMP_CULE_D |
| 637 | UINT64_C(207028224), // VFCMP_CULE_S |
| 638 | UINT64_C(207945728), // VFCMP_CULT_D |
| 639 | UINT64_C(206897152), // VFCMP_CULT_S |
| 640 | UINT64_C(208404480), // VFCMP_CUNE_D |
| 641 | UINT64_C(207355904), // VFCMP_CUNE_S |
| 642 | UINT64_C(207880192), // VFCMP_CUN_D |
| 643 | UINT64_C(206831616), // VFCMP_CUN_S |
| 644 | UINT64_C(207650816), // VFCMP_SAF_D |
| 645 | UINT64_C(206602240), // VFCMP_SAF_S |
| 646 | UINT64_C(207781888), // VFCMP_SEQ_D |
| 647 | UINT64_C(206733312), // VFCMP_SEQ_S |
| 648 | UINT64_C(207847424), // VFCMP_SLE_D |
| 649 | UINT64_C(206798848), // VFCMP_SLE_S |
| 650 | UINT64_C(207716352), // VFCMP_SLT_D |
| 651 | UINT64_C(206667776), // VFCMP_SLT_S |
| 652 | UINT64_C(208175104), // VFCMP_SNE_D |
| 653 | UINT64_C(207126528), // VFCMP_SNE_S |
| 654 | UINT64_C(208306176), // VFCMP_SOR_D |
| 655 | UINT64_C(207257600), // VFCMP_SOR_S |
| 656 | UINT64_C(208044032), // VFCMP_SUEQ_D |
| 657 | UINT64_C(206995456), // VFCMP_SUEQ_S |
| 658 | UINT64_C(208109568), // VFCMP_SULE_D |
| 659 | UINT64_C(207060992), // VFCMP_SULE_S |
| 660 | UINT64_C(207978496), // VFCMP_SULT_D |
| 661 | UINT64_C(206929920), // VFCMP_SULT_S |
| 662 | UINT64_C(208437248), // VFCMP_SUNE_D |
| 663 | UINT64_C(207388672), // VFCMP_SUNE_S |
| 664 | UINT64_C(207912960), // VFCMP_SUN_D |
| 665 | UINT64_C(206864384), // VFCMP_SUN_S |
| 666 | UINT64_C(1922954240), // VFCVTH_D_S |
| 667 | UINT64_C(1922952192), // VFCVTH_S_H |
| 668 | UINT64_C(1922953216), // VFCVTL_D_S |
| 669 | UINT64_C(1922951168), // VFCVTL_S_H |
| 670 | UINT64_C(1900412928), // VFCVT_H_S |
| 671 | UINT64_C(1900445696), // VFCVT_S_D |
| 672 | UINT64_C(1899692032), // VFDIV_D |
| 673 | UINT64_C(1899659264), // VFDIV_S |
| 674 | UINT64_C(1922962432), // VFFINTH_D_W |
| 675 | UINT64_C(1922961408), // VFFINTL_D_W |
| 676 | UINT64_C(1922959360), // VFFINT_D_L |
| 677 | UINT64_C(1922960384), // VFFINT_D_LU |
| 678 | UINT64_C(1900544000), // VFFINT_S_L |
| 679 | UINT64_C(1922957312), // VFFINT_S_W |
| 680 | UINT64_C(1922958336), // VFFINT_S_WU |
| 681 | UINT64_C(1922877440), // VFLOGB_D |
| 682 | UINT64_C(1922876416), // VFLOGB_S |
| 683 | UINT64_C(153092096), // VFMADD_D |
| 684 | UINT64_C(152043520), // VFMADD_S |
| 685 | UINT64_C(1900085248), // VFMAXA_D |
| 686 | UINT64_C(1900052480), // VFMAXA_S |
| 687 | UINT64_C(1899823104), // VFMAX_D |
| 688 | UINT64_C(1899790336), // VFMAX_S |
| 689 | UINT64_C(1900216320), // VFMINA_D |
| 690 | UINT64_C(1900183552), // VFMINA_S |
| 691 | UINT64_C(1899954176), // VFMIN_D |
| 692 | UINT64_C(1899921408), // VFMIN_S |
| 693 | UINT64_C(157286400), // VFMSUB_D |
| 694 | UINT64_C(156237824), // VFMSUB_S |
| 695 | UINT64_C(1899560960), // VFMUL_D |
| 696 | UINT64_C(1899528192), // VFMUL_S |
| 697 | UINT64_C(161480704), // VFNMADD_D |
| 698 | UINT64_C(160432128), // VFNMADD_S |
| 699 | UINT64_C(165675008), // VFNMSUB_D |
| 700 | UINT64_C(164626432), // VFNMSUB_S |
| 701 | UINT64_C(1922897920), // VFRECIPE_D |
| 702 | UINT64_C(1922896896), // VFRECIPE_S |
| 703 | UINT64_C(1922889728), // VFRECIP_D |
| 704 | UINT64_C(1922888704), // VFRECIP_S |
| 705 | UINT64_C(1922910208), // VFRINTRM_D |
| 706 | UINT64_C(1922909184), // VFRINTRM_S |
| 707 | UINT64_C(1922922496), // VFRINTRNE_D |
| 708 | UINT64_C(1922921472), // VFRINTRNE_S |
| 709 | UINT64_C(1922914304), // VFRINTRP_D |
| 710 | UINT64_C(1922913280), // VFRINTRP_S |
| 711 | UINT64_C(1922918400), // VFRINTRZ_D |
| 712 | UINT64_C(1922917376), // VFRINTRZ_S |
| 713 | UINT64_C(1922906112), // VFRINT_D |
| 714 | UINT64_C(1922905088), // VFRINT_S |
| 715 | UINT64_C(1922902016), // VFRSQRTE_D |
| 716 | UINT64_C(1922900992), // VFRSQRTE_S |
| 717 | UINT64_C(1922893824), // VFRSQRT_D |
| 718 | UINT64_C(1922892800), // VFRSQRT_S |
| 719 | UINT64_C(1922695168), // VFRSTPI_B |
| 720 | UINT64_C(1922727936), // VFRSTPI_H |
| 721 | UINT64_C(1898643456), // VFRSTP_B |
| 722 | UINT64_C(1898676224), // VFRSTP_H |
| 723 | UINT64_C(1922885632), // VFSQRT_D |
| 724 | UINT64_C(1922884608), // VFSQRT_S |
| 725 | UINT64_C(1899167744), // VFSUB_D |
| 726 | UINT64_C(1899134976), // VFSUB_S |
| 727 | UINT64_C(1922991104), // VFTINTH_L_S |
| 728 | UINT64_C(1922990080), // VFTINTL_L_S |
| 729 | UINT64_C(1922993152), // VFTINTRMH_L_S |
| 730 | UINT64_C(1922992128), // VFTINTRML_L_S |
| 731 | UINT64_C(1922972672), // VFTINTRM_L_D |
| 732 | UINT64_C(1900675072), // VFTINTRM_W_D |
| 733 | UINT64_C(1922971648), // VFTINTRM_W_S |
| 734 | UINT64_C(1922999296), // VFTINTRNEH_L_S |
| 735 | UINT64_C(1922998272), // VFTINTRNEL_L_S |
| 736 | UINT64_C(1922978816), // VFTINTRNE_L_D |
| 737 | UINT64_C(1900773376), // VFTINTRNE_W_D |
| 738 | UINT64_C(1922977792), // VFTINTRNE_W_S |
| 739 | UINT64_C(1922995200), // VFTINTRPH_L_S |
| 740 | UINT64_C(1922994176), // VFTINTRPL_L_S |
| 741 | UINT64_C(1922974720), // VFTINTRP_L_D |
| 742 | UINT64_C(1900707840), // VFTINTRP_W_D |
| 743 | UINT64_C(1922973696), // VFTINTRP_W_S |
| 744 | UINT64_C(1922997248), // VFTINTRZH_L_S |
| 745 | UINT64_C(1922996224), // VFTINTRZL_L_S |
| 746 | UINT64_C(1922987008), // VFTINTRZ_LU_D |
| 747 | UINT64_C(1922976768), // VFTINTRZ_L_D |
| 748 | UINT64_C(1922985984), // VFTINTRZ_WU_S |
| 749 | UINT64_C(1900740608), // VFTINTRZ_W_D |
| 750 | UINT64_C(1922975744), // VFTINTRZ_W_S |
| 751 | UINT64_C(1922980864), // VFTINT_LU_D |
| 752 | UINT64_C(1922970624), // VFTINT_L_D |
| 753 | UINT64_C(1922979840), // VFTINT_WU_S |
| 754 | UINT64_C(1900642304), // VFTINT_W_D |
| 755 | UINT64_C(1922969600), // VFTINT_W_S |
| 756 | UINT64_C(1884880896), // VHADDW_DU_WU |
| 757 | UINT64_C(1884618752), // VHADDW_D_W |
| 758 | UINT64_C(1884815360), // VHADDW_HU_BU |
| 759 | UINT64_C(1884553216), // VHADDW_H_B |
| 760 | UINT64_C(1884913664), // VHADDW_QU_DU |
| 761 | UINT64_C(1884651520), // VHADDW_Q_D |
| 762 | UINT64_C(1884848128), // VHADDW_WU_HU |
| 763 | UINT64_C(1884585984), // VHADDW_W_H |
| 764 | UINT64_C(1885011968), // VHSUBW_DU_WU |
| 765 | UINT64_C(1884749824), // VHSUBW_D_W |
| 766 | UINT64_C(1884946432), // VHSUBW_HU_BU |
| 767 | UINT64_C(1884684288), // VHSUBW_H_B |
| 768 | UINT64_C(1885044736), // VHSUBW_QU_DU |
| 769 | UINT64_C(1884782592), // VHSUBW_Q_D |
| 770 | UINT64_C(1884979200), // VHSUBW_WU_HU |
| 771 | UINT64_C(1884717056), // VHSUBW_W_H |
| 772 | UINT64_C(1897660416), // VILVH_B |
| 773 | UINT64_C(1897758720), // VILVH_D |
| 774 | UINT64_C(1897693184), // VILVH_H |
| 775 | UINT64_C(1897725952), // VILVH_W |
| 776 | UINT64_C(1897529344), // VILVL_B |
| 777 | UINT64_C(1897627648), // VILVL_D |
| 778 | UINT64_C(1897562112), // VILVL_H |
| 779 | UINT64_C(1897594880), // VILVL_W |
| 780 | UINT64_C(1928036352), // VINSGR2VR_B |
| 781 | UINT64_C(1928065024), // VINSGR2VR_D |
| 782 | UINT64_C(1928052736), // VINSGR2VR_H |
| 783 | UINT64_C(1928060928), // VINSGR2VR_W |
| 784 | UINT64_C(738197504), // VLD |
| 785 | UINT64_C(1944059904), // VLDI |
| 786 | UINT64_C(813694976), // VLDREPL_B |
| 787 | UINT64_C(806354944), // VLDREPL_D |
| 788 | UINT64_C(809500672), // VLDREPL_H |
| 789 | UINT64_C(807403520), // VLDREPL_W |
| 790 | UINT64_C(943718400), // VLDX |
| 791 | UINT64_C(1890385920), // VMADDWEV_D_W |
| 792 | UINT64_C(1890910208), // VMADDWEV_D_WU |
| 793 | UINT64_C(1891434496), // VMADDWEV_D_WU_W |
| 794 | UINT64_C(1890320384), // VMADDWEV_H_B |
| 795 | UINT64_C(1890844672), // VMADDWEV_H_BU |
| 796 | UINT64_C(1891368960), // VMADDWEV_H_BU_B |
| 797 | UINT64_C(1890418688), // VMADDWEV_Q_D |
| 798 | UINT64_C(1890942976), // VMADDWEV_Q_DU |
| 799 | UINT64_C(1891467264), // VMADDWEV_Q_DU_D |
| 800 | UINT64_C(1890353152), // VMADDWEV_W_H |
| 801 | UINT64_C(1890877440), // VMADDWEV_W_HU |
| 802 | UINT64_C(1891401728), // VMADDWEV_W_HU_H |
| 803 | UINT64_C(1890516992), // VMADDWOD_D_W |
| 804 | UINT64_C(1891041280), // VMADDWOD_D_WU |
| 805 | UINT64_C(1891565568), // VMADDWOD_D_WU_W |
| 806 | UINT64_C(1890451456), // VMADDWOD_H_B |
| 807 | UINT64_C(1890975744), // VMADDWOD_H_BU |
| 808 | UINT64_C(1891500032), // VMADDWOD_H_BU_B |
| 809 | UINT64_C(1890549760), // VMADDWOD_Q_D |
| 810 | UINT64_C(1891074048), // VMADDWOD_Q_DU |
| 811 | UINT64_C(1891598336), // VMADDWOD_Q_DU_D |
| 812 | UINT64_C(1890484224), // VMADDWOD_W_H |
| 813 | UINT64_C(1891008512), // VMADDWOD_W_HU |
| 814 | UINT64_C(1891532800), // VMADDWOD_W_HU_H |
| 815 | UINT64_C(1890058240), // VMADD_B |
| 816 | UINT64_C(1890156544), // VMADD_D |
| 817 | UINT64_C(1890091008), // VMADD_H |
| 818 | UINT64_C(1890123776), // VMADD_W |
| 819 | UINT64_C(1922039808), // VMAXI_B |
| 820 | UINT64_C(1922301952), // VMAXI_BU |
| 821 | UINT64_C(1922138112), // VMAXI_D |
| 822 | UINT64_C(1922400256), // VMAXI_DU |
| 823 | UINT64_C(1922072576), // VMAXI_H |
| 824 | UINT64_C(1922334720), // VMAXI_HU |
| 825 | UINT64_C(1922105344), // VMAXI_W |
| 826 | UINT64_C(1922367488), // VMAXI_WU |
| 827 | UINT64_C(1886388224), // VMAX_B |
| 828 | UINT64_C(1886650368), // VMAX_BU |
| 829 | UINT64_C(1886486528), // VMAX_D |
| 830 | UINT64_C(1886748672), // VMAX_DU |
| 831 | UINT64_C(1886420992), // VMAX_H |
| 832 | UINT64_C(1886683136), // VMAX_HU |
| 833 | UINT64_C(1886453760), // VMAX_W |
| 834 | UINT64_C(1886715904), // VMAX_WU |
| 835 | UINT64_C(1922170880), // VMINI_B |
| 836 | UINT64_C(1922433024), // VMINI_BU |
| 837 | UINT64_C(1922269184), // VMINI_D |
| 838 | UINT64_C(1922531328), // VMINI_DU |
| 839 | UINT64_C(1922203648), // VMINI_H |
| 840 | UINT64_C(1922465792), // VMINI_HU |
| 841 | UINT64_C(1922236416), // VMINI_W |
| 842 | UINT64_C(1922498560), // VMINI_WU |
| 843 | UINT64_C(1886519296), // VMIN_B |
| 844 | UINT64_C(1886781440), // VMIN_BU |
| 845 | UINT64_C(1886617600), // VMIN_D |
| 846 | UINT64_C(1886879744), // VMIN_DU |
| 847 | UINT64_C(1886552064), // VMIN_H |
| 848 | UINT64_C(1886814208), // VMIN_HU |
| 849 | UINT64_C(1886584832), // VMIN_W |
| 850 | UINT64_C(1886846976), // VMIN_WU |
| 851 | UINT64_C(1893859328), // VMOD_B |
| 852 | UINT64_C(1894121472), // VMOD_BU |
| 853 | UINT64_C(1893957632), // VMOD_D |
| 854 | UINT64_C(1894219776), // VMOD_DU |
| 855 | UINT64_C(1893892096), // VMOD_H |
| 856 | UINT64_C(1894154240), // VMOD_HU |
| 857 | UINT64_C(1893924864), // VMOD_W |
| 858 | UINT64_C(1894187008), // VMOD_WU |
| 859 | UINT64_C(1922846720), // VMSKGEZ_B |
| 860 | UINT64_C(1922842624), // VMSKLTZ_B |
| 861 | UINT64_C(1922845696), // VMSKLTZ_D |
| 862 | UINT64_C(1922843648), // VMSKLTZ_H |
| 863 | UINT64_C(1922844672), // VMSKLTZ_W |
| 864 | UINT64_C(1922850816), // VMSKNZ_B |
| 865 | UINT64_C(1890189312), // VMSUB_B |
| 866 | UINT64_C(1890287616), // VMSUB_D |
| 867 | UINT64_C(1890222080), // VMSUB_H |
| 868 | UINT64_C(1890254848), // VMSUB_W |
| 869 | UINT64_C(1887830016), // VMUH_B |
| 870 | UINT64_C(1887961088), // VMUH_BU |
| 871 | UINT64_C(1887928320), // VMUH_D |
| 872 | UINT64_C(1888059392), // VMUH_DU |
| 873 | UINT64_C(1887862784), // VMUH_H |
| 874 | UINT64_C(1887993856), // VMUH_HU |
| 875 | UINT64_C(1887895552), // VMUH_W |
| 876 | UINT64_C(1888026624), // VMUH_WU |
| 877 | UINT64_C(1888550912), // VMULWEV_D_W |
| 878 | UINT64_C(1889075200), // VMULWEV_D_WU |
| 879 | UINT64_C(1889599488), // VMULWEV_D_WU_W |
| 880 | UINT64_C(1888485376), // VMULWEV_H_B |
| 881 | UINT64_C(1889009664), // VMULWEV_H_BU |
| 882 | UINT64_C(1889533952), // VMULWEV_H_BU_B |
| 883 | UINT64_C(1888583680), // VMULWEV_Q_D |
| 884 | UINT64_C(1889107968), // VMULWEV_Q_DU |
| 885 | UINT64_C(1889632256), // VMULWEV_Q_DU_D |
| 886 | UINT64_C(1888518144), // VMULWEV_W_H |
| 887 | UINT64_C(1889042432), // VMULWEV_W_HU |
| 888 | UINT64_C(1889566720), // VMULWEV_W_HU_H |
| 889 | UINT64_C(1888681984), // VMULWOD_D_W |
| 890 | UINT64_C(1889206272), // VMULWOD_D_WU |
| 891 | UINT64_C(1889730560), // VMULWOD_D_WU_W |
| 892 | UINT64_C(1888616448), // VMULWOD_H_B |
| 893 | UINT64_C(1889140736), // VMULWOD_H_BU |
| 894 | UINT64_C(1889665024), // VMULWOD_H_BU_B |
| 895 | UINT64_C(1888714752), // VMULWOD_Q_D |
| 896 | UINT64_C(1889239040), // VMULWOD_Q_DU |
| 897 | UINT64_C(1889763328), // VMULWOD_Q_DU_D |
| 898 | UINT64_C(1888649216), // VMULWOD_W_H |
| 899 | UINT64_C(1889173504), // VMULWOD_W_HU |
| 900 | UINT64_C(1889697792), // VMULWOD_W_HU_H |
| 901 | UINT64_C(1887698944), // VMUL_B |
| 902 | UINT64_C(1887797248), // VMUL_D |
| 903 | UINT64_C(1887731712), // VMUL_H |
| 904 | UINT64_C(1887764480), // VMUL_W |
| 905 | UINT64_C(1922838528), // VNEG_B |
| 906 | UINT64_C(1922841600), // VNEG_D |
| 907 | UINT64_C(1922839552), // VNEG_H |
| 908 | UINT64_C(1922840576), // VNEG_W |
| 909 | UINT64_C(1943797760), // VNORI_B |
| 910 | UINT64_C(1898414080), // VNOR_V |
| 911 | UINT64_C(1943273472), // VORI_B |
| 912 | UINT64_C(1898479616), // VORN_V |
| 913 | UINT64_C(1898348544), // VOR_V |
| 914 | UINT64_C(1897267200), // VPACKEV_B |
| 915 | UINT64_C(1897365504), // VPACKEV_D |
| 916 | UINT64_C(1897299968), // VPACKEV_H |
| 917 | UINT64_C(1897332736), // VPACKEV_W |
| 918 | UINT64_C(1897398272), // VPACKOD_B |
| 919 | UINT64_C(1897496576), // VPACKOD_D |
| 920 | UINT64_C(1897431040), // VPACKOD_H |
| 921 | UINT64_C(1897463808), // VPACKOD_W |
| 922 | UINT64_C(1922834432), // VPCNT_B |
| 923 | UINT64_C(1922837504), // VPCNT_D |
| 924 | UINT64_C(1922835456), // VPCNT_H |
| 925 | UINT64_C(1922836480), // VPCNT_W |
| 926 | UINT64_C(1944322048), // VPERMI_W |
| 927 | UINT64_C(1897791488), // VPICKEV_B |
| 928 | UINT64_C(1897889792), // VPICKEV_D |
| 929 | UINT64_C(1897824256), // VPICKEV_H |
| 930 | UINT64_C(1897857024), // VPICKEV_W |
| 931 | UINT64_C(1897922560), // VPICKOD_B |
| 932 | UINT64_C(1898020864), // VPICKOD_D |
| 933 | UINT64_C(1897955328), // VPICKOD_H |
| 934 | UINT64_C(1897988096), // VPICKOD_W |
| 935 | UINT64_C(1928298496), // VPICKVE2GR_B |
| 936 | UINT64_C(1928560640), // VPICKVE2GR_BU |
| 937 | UINT64_C(1928327168), // VPICKVE2GR_D |
| 938 | UINT64_C(1928589312), // VPICKVE2GR_DU |
| 939 | UINT64_C(1928314880), // VPICKVE2GR_H |
| 940 | UINT64_C(1928577024), // VPICKVE2GR_HU |
| 941 | UINT64_C(1928323072), // VPICKVE2GR_W |
| 942 | UINT64_C(1928585216), // VPICKVE2GR_WU |
| 943 | UINT64_C(1923022848), // VREPLGR2VR_B |
| 944 | UINT64_C(1923025920), // VREPLGR2VR_D |
| 945 | UINT64_C(1923023872), // VREPLGR2VR_H |
| 946 | UINT64_C(1923024896), // VREPLGR2VR_W |
| 947 | UINT64_C(1928822784), // VREPLVEI_B |
| 948 | UINT64_C(1928851456), // VREPLVEI_D |
| 949 | UINT64_C(1928839168), // VREPLVEI_H |
| 950 | UINT64_C(1928847360), // VREPLVEI_W |
| 951 | UINT64_C(1898053632), // VREPLVE_B |
| 952 | UINT64_C(1898151936), // VREPLVE_D |
| 953 | UINT64_C(1898086400), // VREPLVE_H |
| 954 | UINT64_C(1898119168), // VREPLVE_W |
| 955 | UINT64_C(1923096576), // VROTRI_B |
| 956 | UINT64_C(1923153920), // VROTRI_D |
| 957 | UINT64_C(1923104768), // VROTRI_H |
| 958 | UINT64_C(1923121152), // VROTRI_W |
| 959 | UINT64_C(1894645760), // VROTR_B |
| 960 | UINT64_C(1894744064), // VROTR_D |
| 961 | UINT64_C(1894678528), // VROTR_H |
| 962 | UINT64_C(1894711296), // VROTR_W |
| 963 | UINT64_C(1883635712), // VSADD_B |
| 964 | UINT64_C(1883897856), // VSADD_BU |
| 965 | UINT64_C(1883734016), // VSADD_D |
| 966 | UINT64_C(1883996160), // VSADD_DU |
| 967 | UINT64_C(1883668480), // VSADD_H |
| 968 | UINT64_C(1883930624), // VSADD_HU |
| 969 | UINT64_C(1883701248), // VSADD_W |
| 970 | UINT64_C(1883963392), // VSADD_WU |
| 971 | UINT64_C(1931747328), // VSAT_B |
| 972 | UINT64_C(1932009472), // VSAT_BU |
| 973 | UINT64_C(1931804672), // VSAT_D |
| 974 | UINT64_C(1932066816), // VSAT_DU |
| 975 | UINT64_C(1931755520), // VSAT_H |
| 976 | UINT64_C(1932017664), // VSAT_HU |
| 977 | UINT64_C(1931771904), // VSAT_W |
| 978 | UINT64_C(1932034048), // VSAT_WU |
| 979 | UINT64_C(1920991232), // VSEQI_B |
| 980 | UINT64_C(1921089536), // VSEQI_D |
| 981 | UINT64_C(1921024000), // VSEQI_H |
| 982 | UINT64_C(1921056768), // VSEQI_W |
| 983 | UINT64_C(1879048192), // VSEQ_B |
| 984 | UINT64_C(1879146496), // VSEQ_D |
| 985 | UINT64_C(1879080960), // VSEQ_H |
| 986 | UINT64_C(1879113728), // VSEQ_W |
| 987 | UINT64_C(1922871296), // VSETALLNEZ_B |
| 988 | UINT64_C(1922874368), // VSETALLNEZ_D |
| 989 | UINT64_C(1922872320), // VSETALLNEZ_H |
| 990 | UINT64_C(1922873344), // VSETALLNEZ_W |
| 991 | UINT64_C(1922867200), // VSETANYEQZ_B |
| 992 | UINT64_C(1922870272), // VSETANYEQZ_D |
| 993 | UINT64_C(1922868224), // VSETANYEQZ_H |
| 994 | UINT64_C(1922869248), // VSETANYEQZ_W |
| 995 | UINT64_C(1922865152), // VSETEQZ_V |
| 996 | UINT64_C(1922866176), // VSETNEZ_V |
| 997 | UINT64_C(1938817024), // VSHUF4I_B |
| 998 | UINT64_C(1939603456), // VSHUF4I_D |
| 999 | UINT64_C(1939079168), // VSHUF4I_H |
| 1000 | UINT64_C(1939341312), // VSHUF4I_W |
| 1001 | UINT64_C(223346688), // VSHUF_B |
| 1002 | UINT64_C(1903919104), // VSHUF_D |
| 1003 | UINT64_C(1903853568), // VSHUF_H |
| 1004 | UINT64_C(1903886336), // VSHUF_W |
| 1005 | UINT64_C(1898840064), // VSIGNCOV_B |
| 1006 | UINT64_C(1898938368), // VSIGNCOV_D |
| 1007 | UINT64_C(1898872832), // VSIGNCOV_H |
| 1008 | UINT64_C(1898905600), // VSIGNCOV_W |
| 1009 | UINT64_C(1921122304), // VSLEI_B |
| 1010 | UINT64_C(1921253376), // VSLEI_BU |
| 1011 | UINT64_C(1921220608), // VSLEI_D |
| 1012 | UINT64_C(1921351680), // VSLEI_DU |
| 1013 | UINT64_C(1921155072), // VSLEI_H |
| 1014 | UINT64_C(1921286144), // VSLEI_HU |
| 1015 | UINT64_C(1921187840), // VSLEI_W |
| 1016 | UINT64_C(1921318912), // VSLEI_WU |
| 1017 | UINT64_C(1879179264), // VSLE_B |
| 1018 | UINT64_C(1879310336), // VSLE_BU |
| 1019 | UINT64_C(1879277568), // VSLE_D |
| 1020 | UINT64_C(1879408640), // VSLE_DU |
| 1021 | UINT64_C(1879212032), // VSLE_H |
| 1022 | UINT64_C(1879343104), // VSLE_HU |
| 1023 | UINT64_C(1879244800), // VSLE_W |
| 1024 | UINT64_C(1879375872), // VSLE_WU |
| 1025 | UINT64_C(1932271616), // VSLLI_B |
| 1026 | UINT64_C(1932328960), // VSLLI_D |
| 1027 | UINT64_C(1932279808), // VSLLI_H |
| 1028 | UINT64_C(1932296192), // VSLLI_W |
| 1029 | UINT64_C(1930199040), // VSLLWIL_DU_WU |
| 1030 | UINT64_C(1929936896), // VSLLWIL_D_W |
| 1031 | UINT64_C(1930174464), // VSLLWIL_HU_BU |
| 1032 | UINT64_C(1929912320), // VSLLWIL_H_B |
| 1033 | UINT64_C(1930182656), // VSLLWIL_WU_HU |
| 1034 | UINT64_C(1929920512), // VSLLWIL_W_H |
| 1035 | UINT64_C(1894252544), // VSLL_B |
| 1036 | UINT64_C(1894350848), // VSLL_D |
| 1037 | UINT64_C(1894285312), // VSLL_H |
| 1038 | UINT64_C(1894318080), // VSLL_W |
| 1039 | UINT64_C(1921384448), // VSLTI_B |
| 1040 | UINT64_C(1921515520), // VSLTI_BU |
| 1041 | UINT64_C(1921482752), // VSLTI_D |
| 1042 | UINT64_C(1921613824), // VSLTI_DU |
| 1043 | UINT64_C(1921417216), // VSLTI_H |
| 1044 | UINT64_C(1921548288), // VSLTI_HU |
| 1045 | UINT64_C(1921449984), // VSLTI_W |
| 1046 | UINT64_C(1921581056), // VSLTI_WU |
| 1047 | UINT64_C(1879441408), // VSLT_B |
| 1048 | UINT64_C(1879572480), // VSLT_BU |
| 1049 | UINT64_C(1879539712), // VSLT_D |
| 1050 | UINT64_C(1879670784), // VSLT_DU |
| 1051 | UINT64_C(1879474176), // VSLT_H |
| 1052 | UINT64_C(1879605248), // VSLT_HU |
| 1053 | UINT64_C(1879506944), // VSLT_W |
| 1054 | UINT64_C(1879638016), // VSLT_WU |
| 1055 | UINT64_C(1932795904), // VSRAI_B |
| 1056 | UINT64_C(1932853248), // VSRAI_D |
| 1057 | UINT64_C(1932804096), // VSRAI_H |
| 1058 | UINT64_C(1932820480), // VSRAI_W |
| 1059 | UINT64_C(1935163392), // VSRANI_B_H |
| 1060 | UINT64_C(1935278080), // VSRANI_D_Q |
| 1061 | UINT64_C(1935179776), // VSRANI_H_W |
| 1062 | UINT64_C(1935212544), // VSRANI_W_D |
| 1063 | UINT64_C(1895202816), // VSRAN_B_H |
| 1064 | UINT64_C(1895235584), // VSRAN_H_W |
| 1065 | UINT64_C(1895268352), // VSRAN_W_D |
| 1066 | UINT64_C(1923620864), // VSRARI_B |
| 1067 | UINT64_C(1923678208), // VSRARI_D |
| 1068 | UINT64_C(1923629056), // VSRARI_H |
| 1069 | UINT64_C(1923645440), // VSRARI_W |
| 1070 | UINT64_C(1935425536), // VSRARNI_B_H |
| 1071 | UINT64_C(1935540224), // VSRARNI_D_Q |
| 1072 | UINT64_C(1935441920), // VSRARNI_H_W |
| 1073 | UINT64_C(1935474688), // VSRARNI_W_D |
| 1074 | UINT64_C(1895464960), // VSRARN_B_H |
| 1075 | UINT64_C(1895497728), // VSRARN_H_W |
| 1076 | UINT64_C(1895530496), // VSRARN_W_D |
| 1077 | UINT64_C(1894907904), // VSRAR_B |
| 1078 | UINT64_C(1895006208), // VSRAR_D |
| 1079 | UINT64_C(1894940672), // VSRAR_H |
| 1080 | UINT64_C(1894973440), // VSRAR_W |
| 1081 | UINT64_C(1894514688), // VSRA_B |
| 1082 | UINT64_C(1894612992), // VSRA_D |
| 1083 | UINT64_C(1894547456), // VSRA_H |
| 1084 | UINT64_C(1894580224), // VSRA_W |
| 1085 | UINT64_C(1932533760), // VSRLI_B |
| 1086 | UINT64_C(1932591104), // VSRLI_D |
| 1087 | UINT64_C(1932541952), // VSRLI_H |
| 1088 | UINT64_C(1932558336), // VSRLI_W |
| 1089 | UINT64_C(1933590528), // VSRLNI_B_H |
| 1090 | UINT64_C(1933705216), // VSRLNI_D_Q |
| 1091 | UINT64_C(1933606912), // VSRLNI_H_W |
| 1092 | UINT64_C(1933639680), // VSRLNI_W_D |
| 1093 | UINT64_C(1895071744), // VSRLN_B_H |
| 1094 | UINT64_C(1895104512), // VSRLN_H_W |
| 1095 | UINT64_C(1895137280), // VSRLN_W_D |
| 1096 | UINT64_C(1923358720), // VSRLRI_B |
| 1097 | UINT64_C(1923416064), // VSRLRI_D |
| 1098 | UINT64_C(1923366912), // VSRLRI_H |
| 1099 | UINT64_C(1923383296), // VSRLRI_W |
| 1100 | UINT64_C(1933852672), // VSRLRNI_B_H |
| 1101 | UINT64_C(1933967360), // VSRLRNI_D_Q |
| 1102 | UINT64_C(1933869056), // VSRLRNI_H_W |
| 1103 | UINT64_C(1933901824), // VSRLRNI_W_D |
| 1104 | UINT64_C(1895333888), // VSRLRN_B_H |
| 1105 | UINT64_C(1895366656), // VSRLRN_H_W |
| 1106 | UINT64_C(1895399424), // VSRLRN_W_D |
| 1107 | UINT64_C(1894776832), // VSRLR_B |
| 1108 | UINT64_C(1894875136), // VSRLR_D |
| 1109 | UINT64_C(1894809600), // VSRLR_H |
| 1110 | UINT64_C(1894842368), // VSRLR_W |
| 1111 | UINT64_C(1894383616), // VSRL_B |
| 1112 | UINT64_C(1894481920), // VSRL_D |
| 1113 | UINT64_C(1894416384), // VSRL_H |
| 1114 | UINT64_C(1894449152), // VSRL_W |
| 1115 | UINT64_C(1935949824), // VSSRANI_BU_H |
| 1116 | UINT64_C(1935687680), // VSSRANI_B_H |
| 1117 | UINT64_C(1936064512), // VSSRANI_DU_Q |
| 1118 | UINT64_C(1935802368), // VSSRANI_D_Q |
| 1119 | UINT64_C(1935966208), // VSSRANI_HU_W |
| 1120 | UINT64_C(1935704064), // VSSRANI_H_W |
| 1121 | UINT64_C(1935998976), // VSSRANI_WU_D |
| 1122 | UINT64_C(1935736832), // VSSRANI_W_D |
| 1123 | UINT64_C(1896251392), // VSSRAN_BU_H |
| 1124 | UINT64_C(1895727104), // VSSRAN_B_H |
| 1125 | UINT64_C(1896284160), // VSSRAN_HU_W |
| 1126 | UINT64_C(1895759872), // VSSRAN_H_W |
| 1127 | UINT64_C(1896316928), // VSSRAN_WU_D |
| 1128 | UINT64_C(1895792640), // VSSRAN_W_D |
| 1129 | UINT64_C(1936474112), // VSSRARNI_BU_H |
| 1130 | UINT64_C(1936211968), // VSSRARNI_B_H |
| 1131 | UINT64_C(1936588800), // VSSRARNI_DU_Q |
| 1132 | UINT64_C(1936326656), // VSSRARNI_D_Q |
| 1133 | UINT64_C(1936490496), // VSSRARNI_HU_W |
| 1134 | UINT64_C(1936228352), // VSSRARNI_H_W |
| 1135 | UINT64_C(1936523264), // VSSRARNI_WU_D |
| 1136 | UINT64_C(1936261120), // VSSRARNI_W_D |
| 1137 | UINT64_C(1896513536), // VSSRARN_BU_H |
| 1138 | UINT64_C(1895989248), // VSSRARN_B_H |
| 1139 | UINT64_C(1896546304), // VSSRARN_HU_W |
| 1140 | UINT64_C(1896022016), // VSSRARN_H_W |
| 1141 | UINT64_C(1896579072), // VSSRARN_WU_D |
| 1142 | UINT64_C(1896054784), // VSSRARN_W_D |
| 1143 | UINT64_C(1934376960), // VSSRLNI_BU_H |
| 1144 | UINT64_C(1934114816), // VSSRLNI_B_H |
| 1145 | UINT64_C(1934491648), // VSSRLNI_DU_Q |
| 1146 | UINT64_C(1934229504), // VSSRLNI_D_Q |
| 1147 | UINT64_C(1934393344), // VSSRLNI_HU_W |
| 1148 | UINT64_C(1934131200), // VSSRLNI_H_W |
| 1149 | UINT64_C(1934426112), // VSSRLNI_WU_D |
| 1150 | UINT64_C(1934163968), // VSSRLNI_W_D |
| 1151 | UINT64_C(1896120320), // VSSRLN_BU_H |
| 1152 | UINT64_C(1895596032), // VSSRLN_B_H |
| 1153 | UINT64_C(1896153088), // VSSRLN_HU_W |
| 1154 | UINT64_C(1895628800), // VSSRLN_H_W |
| 1155 | UINT64_C(1896185856), // VSSRLN_WU_D |
| 1156 | UINT64_C(1895661568), // VSSRLN_W_D |
| 1157 | UINT64_C(1934901248), // VSSRLRNI_BU_H |
| 1158 | UINT64_C(1934639104), // VSSRLRNI_B_H |
| 1159 | UINT64_C(1935015936), // VSSRLRNI_DU_Q |
| 1160 | UINT64_C(1934753792), // VSSRLRNI_D_Q |
| 1161 | UINT64_C(1934917632), // VSSRLRNI_HU_W |
| 1162 | UINT64_C(1934655488), // VSSRLRNI_H_W |
| 1163 | UINT64_C(1934950400), // VSSRLRNI_WU_D |
| 1164 | UINT64_C(1934688256), // VSSRLRNI_W_D |
| 1165 | UINT64_C(1896382464), // VSSRLRN_BU_H |
| 1166 | UINT64_C(1895858176), // VSSRLRN_B_H |
| 1167 | UINT64_C(1896415232), // VSSRLRN_HU_W |
| 1168 | UINT64_C(1895890944), // VSSRLRN_H_W |
| 1169 | UINT64_C(1896448000), // VSSRLRN_WU_D |
| 1170 | UINT64_C(1895923712), // VSSRLRN_W_D |
| 1171 | UINT64_C(1883766784), // VSSUB_B |
| 1172 | UINT64_C(1884028928), // VSSUB_BU |
| 1173 | UINT64_C(1883865088), // VSSUB_D |
| 1174 | UINT64_C(1884127232), // VSSUB_DU |
| 1175 | UINT64_C(1883799552), // VSSUB_H |
| 1176 | UINT64_C(1884061696), // VSSUB_HU |
| 1177 | UINT64_C(1883832320), // VSSUB_W |
| 1178 | UINT64_C(1884094464), // VSSUB_WU |
| 1179 | UINT64_C(742391808), // VST |
| 1180 | UINT64_C(830472192), // VSTELM_B |
| 1181 | UINT64_C(823132160), // VSTELM_D |
| 1182 | UINT64_C(826277888), // VSTELM_H |
| 1183 | UINT64_C(824180736), // VSTELM_W |
| 1184 | UINT64_C(943980544), // VSTX |
| 1185 | UINT64_C(1921777664), // VSUBI_BU |
| 1186 | UINT64_C(1921875968), // VSUBI_DU |
| 1187 | UINT64_C(1921810432), // VSUBI_HU |
| 1188 | UINT64_C(1921843200), // VSUBI_WU |
| 1189 | UINT64_C(1881210880), // VSUBWEV_D_W |
| 1190 | UINT64_C(1882259456), // VSUBWEV_D_WU |
| 1191 | UINT64_C(1881145344), // VSUBWEV_H_B |
| 1192 | UINT64_C(1882193920), // VSUBWEV_H_BU |
| 1193 | UINT64_C(1881243648), // VSUBWEV_Q_D |
| 1194 | UINT64_C(1882292224), // VSUBWEV_Q_DU |
| 1195 | UINT64_C(1881178112), // VSUBWEV_W_H |
| 1196 | UINT64_C(1882226688), // VSUBWEV_W_HU |
| 1197 | UINT64_C(1881473024), // VSUBWOD_D_W |
| 1198 | UINT64_C(1882521600), // VSUBWOD_D_WU |
| 1199 | UINT64_C(1881407488), // VSUBWOD_H_B |
| 1200 | UINT64_C(1882456064), // VSUBWOD_H_BU |
| 1201 | UINT64_C(1881505792), // VSUBWOD_Q_D |
| 1202 | UINT64_C(1882554368), // VSUBWOD_Q_DU |
| 1203 | UINT64_C(1881440256), // VSUBWOD_W_H |
| 1204 | UINT64_C(1882488832), // VSUBWOD_W_HU |
| 1205 | UINT64_C(1879834624), // VSUB_B |
| 1206 | UINT64_C(1879932928), // VSUB_D |
| 1207 | UINT64_C(1879867392), // VSUB_H |
| 1208 | UINT64_C(1898807296), // VSUB_Q |
| 1209 | UINT64_C(1879900160), // VSUB_W |
| 1210 | UINT64_C(1943535616), // VXORI_B |
| 1211 | UINT64_C(1898381312), // VXOR_V |
| 1212 | UINT64_C(4128780), // X86ADC_B |
| 1213 | UINT64_C(4128783), // X86ADC_D |
| 1214 | UINT64_C(4128781), // X86ADC_H |
| 1215 | UINT64_C(4128782), // X86ADC_W |
| 1216 | UINT64_C(4128772), // X86ADD_B |
| 1217 | UINT64_C(4128775), // X86ADD_D |
| 1218 | UINT64_C(4128769), // X86ADD_DU |
| 1219 | UINT64_C(4128773), // X86ADD_H |
| 1220 | UINT64_C(4128774), // X86ADD_W |
| 1221 | UINT64_C(4128768), // X86ADD_WU |
| 1222 | UINT64_C(4161552), // X86AND_B |
| 1223 | UINT64_C(4161555), // X86AND_D |
| 1224 | UINT64_C(4161553), // X86AND_H |
| 1225 | UINT64_C(4161554), // X86AND_W |
| 1226 | UINT64_C(32808), // X86CLRTM |
| 1227 | UINT64_C(32809), // X86DECTOP |
| 1228 | UINT64_C(32772), // X86DEC_B |
| 1229 | UINT64_C(32775), // X86DEC_D |
| 1230 | UINT64_C(32773), // X86DEC_H |
| 1231 | UINT64_C(32774), // X86DEC_W |
| 1232 | UINT64_C(32777), // X86INCTOP |
| 1233 | UINT64_C(32768), // X86INC_B |
| 1234 | UINT64_C(32771), // X86INC_D |
| 1235 | UINT64_C(32769), // X86INC_H |
| 1236 | UINT64_C(32770), // X86INC_W |
| 1237 | UINT64_C(6029312), // X86MFFLAG |
| 1238 | UINT64_C(29696), // X86MFTOP |
| 1239 | UINT64_C(6029344), // X86MTFLAG |
| 1240 | UINT64_C(28672), // X86MTTOP |
| 1241 | UINT64_C(4096000), // X86MUL_B |
| 1242 | UINT64_C(4096004), // X86MUL_BU |
| 1243 | UINT64_C(4096003), // X86MUL_D |
| 1244 | UINT64_C(4096007), // X86MUL_DU |
| 1245 | UINT64_C(4096001), // X86MUL_H |
| 1246 | UINT64_C(4096005), // X86MUL_HU |
| 1247 | UINT64_C(4096002), // X86MUL_W |
| 1248 | UINT64_C(4096006), // X86MUL_WU |
| 1249 | UINT64_C(4161556), // X86OR_B |
| 1250 | UINT64_C(4161559), // X86OR_D |
| 1251 | UINT64_C(4161557), // X86OR_H |
| 1252 | UINT64_C(4161558), // X86OR_W |
| 1253 | UINT64_C(5513240), // X86RCLI_B |
| 1254 | UINT64_C(5570587), // X86RCLI_D |
| 1255 | UINT64_C(5521433), // X86RCLI_H |
| 1256 | UINT64_C(5537818), // X86RCLI_W |
| 1257 | UINT64_C(4161548), // X86RCL_B |
| 1258 | UINT64_C(4161551), // X86RCL_D |
| 1259 | UINT64_C(4161549), // X86RCL_H |
| 1260 | UINT64_C(4161550), // X86RCL_W |
| 1261 | UINT64_C(5513232), // X86RCRI_B |
| 1262 | UINT64_C(5570579), // X86RCRI_D |
| 1263 | UINT64_C(5521425), // X86RCRI_H |
| 1264 | UINT64_C(5537810), // X86RCRI_W |
| 1265 | UINT64_C(4161544), // X86RCR_B |
| 1266 | UINT64_C(4161547), // X86RCR_D |
| 1267 | UINT64_C(4161545), // X86RCR_H |
| 1268 | UINT64_C(4161546), // X86RCR_W |
| 1269 | UINT64_C(5513236), // X86ROTLI_B |
| 1270 | UINT64_C(5570583), // X86ROTLI_D |
| 1271 | UINT64_C(5521429), // X86ROTLI_H |
| 1272 | UINT64_C(5537814), // X86ROTLI_W |
| 1273 | UINT64_C(4161540), // X86ROTL_B |
| 1274 | UINT64_C(4161543), // X86ROTL_D |
| 1275 | UINT64_C(4161541), // X86ROTL_H |
| 1276 | UINT64_C(4161542), // X86ROTL_W |
| 1277 | UINT64_C(5513228), // X86ROTRI_B |
| 1278 | UINT64_C(5570575), // X86ROTRI_D |
| 1279 | UINT64_C(5521421), // X86ROTRI_H |
| 1280 | UINT64_C(5537806), // X86ROTRI_W |
| 1281 | UINT64_C(4161536), // X86ROTR_B |
| 1282 | UINT64_C(4161538), // X86ROTR_D |
| 1283 | UINT64_C(4161537), // X86ROTR_H |
| 1284 | UINT64_C(4161539), // X86ROTR_W |
| 1285 | UINT64_C(4128784), // X86SBC_B |
| 1286 | UINT64_C(4128787), // X86SBC_D |
| 1287 | UINT64_C(4128785), // X86SBC_H |
| 1288 | UINT64_C(4128786), // X86SBC_W |
| 1289 | UINT64_C(5767168), // X86SETTAG |
| 1290 | UINT64_C(32776), // X86SETTM |
| 1291 | UINT64_C(5513216), // X86SLLI_B |
| 1292 | UINT64_C(5570563), // X86SLLI_D |
| 1293 | UINT64_C(5521409), // X86SLLI_H |
| 1294 | UINT64_C(5537794), // X86SLLI_W |
| 1295 | UINT64_C(4128788), // X86SLL_B |
| 1296 | UINT64_C(4128791), // X86SLL_D |
| 1297 | UINT64_C(4128789), // X86SLL_H |
| 1298 | UINT64_C(4128790), // X86SLL_W |
| 1299 | UINT64_C(5513224), // X86SRAI_B |
| 1300 | UINT64_C(5570571), // X86SRAI_D |
| 1301 | UINT64_C(5521417), // X86SRAI_H |
| 1302 | UINT64_C(5537802), // X86SRAI_W |
| 1303 | UINT64_C(4128796), // X86SRA_B |
| 1304 | UINT64_C(4128799), // X86SRA_D |
| 1305 | UINT64_C(4128797), // X86SRA_H |
| 1306 | UINT64_C(4128798), // X86SRA_W |
| 1307 | UINT64_C(5513220), // X86SRLI_B |
| 1308 | UINT64_C(5570567), // X86SRLI_D |
| 1309 | UINT64_C(5521413), // X86SRLI_H |
| 1310 | UINT64_C(5537798), // X86SRLI_W |
| 1311 | UINT64_C(4128792), // X86SRL_B |
| 1312 | UINT64_C(4128795), // X86SRL_D |
| 1313 | UINT64_C(4128793), // X86SRL_H |
| 1314 | UINT64_C(4128794), // X86SRL_W |
| 1315 | UINT64_C(4128776), // X86SUB_B |
| 1316 | UINT64_C(4128779), // X86SUB_D |
| 1317 | UINT64_C(4128771), // X86SUB_DU |
| 1318 | UINT64_C(4128777), // X86SUB_H |
| 1319 | UINT64_C(4128778), // X86SUB_W |
| 1320 | UINT64_C(4128770), // X86SUB_WU |
| 1321 | UINT64_C(4161560), // X86XOR_B |
| 1322 | UINT64_C(4161563), // X86XOR_D |
| 1323 | UINT64_C(4161561), // X86XOR_H |
| 1324 | UINT64_C(4161562), // X86XOR_W |
| 1325 | UINT64_C(1409024), // XOR |
| 1326 | UINT64_C(62914560), // XORI |
| 1327 | UINT64_C(1952448512), // XVABSD_B |
| 1328 | UINT64_C(1952579584), // XVABSD_BU |
| 1329 | UINT64_C(1952546816), // XVABSD_D |
| 1330 | UINT64_C(1952677888), // XVABSD_DU |
| 1331 | UINT64_C(1952481280), // XVABSD_H |
| 1332 | UINT64_C(1952612352), // XVABSD_HU |
| 1333 | UINT64_C(1952514048), // XVABSD_W |
| 1334 | UINT64_C(1952645120), // XVABSD_WU |
| 1335 | UINT64_C(1952186368), // XVADDA_B |
| 1336 | UINT64_C(1952284672), // XVADDA_D |
| 1337 | UINT64_C(1952219136), // XVADDA_H |
| 1338 | UINT64_C(1952251904), // XVADDA_W |
| 1339 | UINT64_C(1988755456), // XVADDI_BU |
| 1340 | UINT64_C(1988853760), // XVADDI_DU |
| 1341 | UINT64_C(1988788224), // XVADDI_HU |
| 1342 | UINT64_C(1988820992), // XVADDI_WU |
| 1343 | UINT64_C(1948188672), // XVADDWEV_D_W |
| 1344 | UINT64_C(1949237248), // XVADDWEV_D_WU |
| 1345 | UINT64_C(1950285824), // XVADDWEV_D_WU_W |
| 1346 | UINT64_C(1948123136), // XVADDWEV_H_B |
| 1347 | UINT64_C(1949171712), // XVADDWEV_H_BU |
| 1348 | UINT64_C(1950220288), // XVADDWEV_H_BU_B |
| 1349 | UINT64_C(1948221440), // XVADDWEV_Q_D |
| 1350 | UINT64_C(1949270016), // XVADDWEV_Q_DU |
| 1351 | UINT64_C(1950318592), // XVADDWEV_Q_DU_D |
| 1352 | UINT64_C(1948155904), // XVADDWEV_W_H |
| 1353 | UINT64_C(1949204480), // XVADDWEV_W_HU |
| 1354 | UINT64_C(1950253056), // XVADDWEV_W_HU_H |
| 1355 | UINT64_C(1948450816), // XVADDWOD_D_W |
| 1356 | UINT64_C(1949499392), // XVADDWOD_D_WU |
| 1357 | UINT64_C(1950416896), // XVADDWOD_D_WU_W |
| 1358 | UINT64_C(1948385280), // XVADDWOD_H_B |
| 1359 | UINT64_C(1949433856), // XVADDWOD_H_BU |
| 1360 | UINT64_C(1950351360), // XVADDWOD_H_BU_B |
| 1361 | UINT64_C(1948483584), // XVADDWOD_Q_D |
| 1362 | UINT64_C(1949532160), // XVADDWOD_Q_DU |
| 1363 | UINT64_C(1950449664), // XVADDWOD_Q_DU_D |
| 1364 | UINT64_C(1948418048), // XVADDWOD_W_H |
| 1365 | UINT64_C(1949466624), // XVADDWOD_W_HU |
| 1366 | UINT64_C(1950384128), // XVADDWOD_W_HU_H |
| 1367 | UINT64_C(1946812416), // XVADD_B |
| 1368 | UINT64_C(1946910720), // XVADD_D |
| 1369 | UINT64_C(1946845184), // XVADD_H |
| 1370 | UINT64_C(1965883392), // XVADD_Q |
| 1371 | UINT64_C(1946877952), // XVADD_W |
| 1372 | UINT64_C(2010120192), // XVANDI_B |
| 1373 | UINT64_C(1965555712), // XVANDN_V |
| 1374 | UINT64_C(1965424640), // XVAND_V |
| 1375 | UINT64_C(1952972800), // XVAVGR_B |
| 1376 | UINT64_C(1953103872), // XVAVGR_BU |
| 1377 | UINT64_C(1953071104), // XVAVGR_D |
| 1378 | UINT64_C(1953202176), // XVAVGR_DU |
| 1379 | UINT64_C(1953005568), // XVAVGR_H |
| 1380 | UINT64_C(1953136640), // XVAVGR_HU |
| 1381 | UINT64_C(1953038336), // XVAVGR_W |
| 1382 | UINT64_C(1953169408), // XVAVGR_WU |
| 1383 | UINT64_C(1952710656), // XVAVG_B |
| 1384 | UINT64_C(1952841728), // XVAVG_BU |
| 1385 | UINT64_C(1952808960), // XVAVG_D |
| 1386 | UINT64_C(1952940032), // XVAVG_DU |
| 1387 | UINT64_C(1952743424), // XVAVG_H |
| 1388 | UINT64_C(1952874496), // XVAVG_HU |
| 1389 | UINT64_C(1952776192), // XVAVG_W |
| 1390 | UINT64_C(1952907264), // XVAVG_WU |
| 1391 | UINT64_C(1997545472), // XVBITCLRI_B |
| 1392 | UINT64_C(1997602816), // XVBITCLRI_D |
| 1393 | UINT64_C(1997553664), // XVBITCLRI_H |
| 1394 | UINT64_C(1997570048), // XVBITCLRI_W |
| 1395 | UINT64_C(1963720704), // XVBITCLR_B |
| 1396 | UINT64_C(1963819008), // XVBITCLR_D |
| 1397 | UINT64_C(1963753472), // XVBITCLR_H |
| 1398 | UINT64_C(1963786240), // XVBITCLR_W |
| 1399 | UINT64_C(1998069760), // XVBITREVI_B |
| 1400 | UINT64_C(1998127104), // XVBITREVI_D |
| 1401 | UINT64_C(1998077952), // XVBITREVI_H |
| 1402 | UINT64_C(1998094336), // XVBITREVI_W |
| 1403 | UINT64_C(1963982848), // XVBITREV_B |
| 1404 | UINT64_C(1964081152), // XVBITREV_D |
| 1405 | UINT64_C(1964015616), // XVBITREV_H |
| 1406 | UINT64_C(1964048384), // XVBITREV_W |
| 1407 | UINT64_C(2009333760), // XVBITSELI_B |
| 1408 | UINT64_C(220200960), // XVBITSEL_V |
| 1409 | UINT64_C(1997807616), // XVBITSETI_B |
| 1410 | UINT64_C(1997864960), // XVBITSETI_D |
| 1411 | UINT64_C(1997815808), // XVBITSETI_H |
| 1412 | UINT64_C(1997832192), // XVBITSETI_W |
| 1413 | UINT64_C(1963851776), // XVBITSET_B |
| 1414 | UINT64_C(1963950080), // XVBITSET_D |
| 1415 | UINT64_C(1963884544), // XVBITSET_H |
| 1416 | UINT64_C(1963917312), // XVBITSET_W |
| 1417 | UINT64_C(1989017600), // XVBSLL_V |
| 1418 | UINT64_C(1989050368), // XVBSRL_V |
| 1419 | UINT64_C(1989935104), // XVCLO_B |
| 1420 | UINT64_C(1989938176), // XVCLO_D |
| 1421 | UINT64_C(1989936128), // XVCLO_H |
| 1422 | UINT64_C(1989937152), // XVCLO_W |
| 1423 | UINT64_C(1989939200), // XVCLZ_B |
| 1424 | UINT64_C(1989942272), // XVCLZ_D |
| 1425 | UINT64_C(1989940224), // XVCLZ_H |
| 1426 | UINT64_C(1989941248), // XVCLZ_W |
| 1427 | UINT64_C(1960837120), // XVDIV_B |
| 1428 | UINT64_C(1961099264), // XVDIV_BU |
| 1429 | UINT64_C(1960935424), // XVDIV_D |
| 1430 | UINT64_C(1961197568), // XVDIV_DU |
| 1431 | UINT64_C(1960869888), // XVDIV_H |
| 1432 | UINT64_C(1961132032), // XVDIV_HU |
| 1433 | UINT64_C(1960902656), // XVDIV_W |
| 1434 | UINT64_C(1961164800), // XVDIV_WU |
| 1435 | UINT64_C(1990129664), // XVEXTH_DU_WU |
| 1436 | UINT64_C(1990125568), // XVEXTH_D_W |
| 1437 | UINT64_C(1990127616), // XVEXTH_HU_BU |
| 1438 | UINT64_C(1990123520), // XVEXTH_H_B |
| 1439 | UINT64_C(1990130688), // XVEXTH_QU_DU |
| 1440 | UINT64_C(1990126592), // XVEXTH_Q_D |
| 1441 | UINT64_C(1990128640), // XVEXTH_WU_HU |
| 1442 | UINT64_C(1990124544), // XVEXTH_W_H |
| 1443 | UINT64_C(1997340672), // XVEXTL_QU_DU |
| 1444 | UINT64_C(1997078528), // XVEXTL_Q_D |
| 1445 | UINT64_C(2005663744), // XVEXTRINS_B |
| 1446 | UINT64_C(2004877312), // XVEXTRINS_D |
| 1447 | UINT64_C(2005401600), // XVEXTRINS_H |
| 1448 | UINT64_C(2005139456), // XVEXTRINS_W |
| 1449 | UINT64_C(1966145536), // XVFADD_D |
| 1450 | UINT64_C(1966112768), // XVFADD_S |
| 1451 | UINT64_C(1989990400), // XVFCLASS_D |
| 1452 | UINT64_C(1989989376), // XVFCLASS_S |
| 1453 | UINT64_C(211812352), // XVFCMP_CAF_D |
| 1454 | UINT64_C(210763776), // XVFCMP_CAF_S |
| 1455 | UINT64_C(211943424), // XVFCMP_CEQ_D |
| 1456 | UINT64_C(210894848), // XVFCMP_CEQ_S |
| 1457 | UINT64_C(212008960), // XVFCMP_CLE_D |
| 1458 | UINT64_C(210960384), // XVFCMP_CLE_S |
| 1459 | UINT64_C(211877888), // XVFCMP_CLT_D |
| 1460 | UINT64_C(210829312), // XVFCMP_CLT_S |
| 1461 | UINT64_C(212336640), // XVFCMP_CNE_D |
| 1462 | UINT64_C(211288064), // XVFCMP_CNE_S |
| 1463 | UINT64_C(212467712), // XVFCMP_COR_D |
| 1464 | UINT64_C(211419136), // XVFCMP_COR_S |
| 1465 | UINT64_C(212205568), // XVFCMP_CUEQ_D |
| 1466 | UINT64_C(211156992), // XVFCMP_CUEQ_S |
| 1467 | UINT64_C(212271104), // XVFCMP_CULE_D |
| 1468 | UINT64_C(211222528), // XVFCMP_CULE_S |
| 1469 | UINT64_C(212140032), // XVFCMP_CULT_D |
| 1470 | UINT64_C(211091456), // XVFCMP_CULT_S |
| 1471 | UINT64_C(212598784), // XVFCMP_CUNE_D |
| 1472 | UINT64_C(211550208), // XVFCMP_CUNE_S |
| 1473 | UINT64_C(212074496), // XVFCMP_CUN_D |
| 1474 | UINT64_C(211025920), // XVFCMP_CUN_S |
| 1475 | UINT64_C(211845120), // XVFCMP_SAF_D |
| 1476 | UINT64_C(210796544), // XVFCMP_SAF_S |
| 1477 | UINT64_C(211976192), // XVFCMP_SEQ_D |
| 1478 | UINT64_C(210927616), // XVFCMP_SEQ_S |
| 1479 | UINT64_C(212041728), // XVFCMP_SLE_D |
| 1480 | UINT64_C(210993152), // XVFCMP_SLE_S |
| 1481 | UINT64_C(211910656), // XVFCMP_SLT_D |
| 1482 | UINT64_C(210862080), // XVFCMP_SLT_S |
| 1483 | UINT64_C(212369408), // XVFCMP_SNE_D |
| 1484 | UINT64_C(211320832), // XVFCMP_SNE_S |
| 1485 | UINT64_C(212500480), // XVFCMP_SOR_D |
| 1486 | UINT64_C(211451904), // XVFCMP_SOR_S |
| 1487 | UINT64_C(212238336), // XVFCMP_SUEQ_D |
| 1488 | UINT64_C(211189760), // XVFCMP_SUEQ_S |
| 1489 | UINT64_C(212303872), // XVFCMP_SULE_D |
| 1490 | UINT64_C(211255296), // XVFCMP_SULE_S |
| 1491 | UINT64_C(212172800), // XVFCMP_SULT_D |
| 1492 | UINT64_C(211124224), // XVFCMP_SULT_S |
| 1493 | UINT64_C(212631552), // XVFCMP_SUNE_D |
| 1494 | UINT64_C(211582976), // XVFCMP_SUNE_S |
| 1495 | UINT64_C(212107264), // XVFCMP_SUN_D |
| 1496 | UINT64_C(211058688), // XVFCMP_SUN_S |
| 1497 | UINT64_C(1990063104), // XVFCVTH_D_S |
| 1498 | UINT64_C(1990061056), // XVFCVTH_S_H |
| 1499 | UINT64_C(1990062080), // XVFCVTL_D_S |
| 1500 | UINT64_C(1990060032), // XVFCVTL_S_H |
| 1501 | UINT64_C(1967521792), // XVFCVT_H_S |
| 1502 | UINT64_C(1967554560), // XVFCVT_S_D |
| 1503 | UINT64_C(1966800896), // XVFDIV_D |
| 1504 | UINT64_C(1966768128), // XVFDIV_S |
| 1505 | UINT64_C(1990071296), // XVFFINTH_D_W |
| 1506 | UINT64_C(1990070272), // XVFFINTL_D_W |
| 1507 | UINT64_C(1990068224), // XVFFINT_D_L |
| 1508 | UINT64_C(1990069248), // XVFFINT_D_LU |
| 1509 | UINT64_C(1967652864), // XVFFINT_S_L |
| 1510 | UINT64_C(1990066176), // XVFFINT_S_W |
| 1511 | UINT64_C(1990067200), // XVFFINT_S_WU |
| 1512 | UINT64_C(1989986304), // XVFLOGB_D |
| 1513 | UINT64_C(1989985280), // XVFLOGB_S |
| 1514 | UINT64_C(169869312), // XVFMADD_D |
| 1515 | UINT64_C(168820736), // XVFMADD_S |
| 1516 | UINT64_C(1967194112), // XVFMAXA_D |
| 1517 | UINT64_C(1967161344), // XVFMAXA_S |
| 1518 | UINT64_C(1966931968), // XVFMAX_D |
| 1519 | UINT64_C(1966899200), // XVFMAX_S |
| 1520 | UINT64_C(1967325184), // XVFMINA_D |
| 1521 | UINT64_C(1967292416), // XVFMINA_S |
| 1522 | UINT64_C(1967063040), // XVFMIN_D |
| 1523 | UINT64_C(1967030272), // XVFMIN_S |
| 1524 | UINT64_C(174063616), // XVFMSUB_D |
| 1525 | UINT64_C(173015040), // XVFMSUB_S |
| 1526 | UINT64_C(1966669824), // XVFMUL_D |
| 1527 | UINT64_C(1966637056), // XVFMUL_S |
| 1528 | UINT64_C(178257920), // XVFNMADD_D |
| 1529 | UINT64_C(177209344), // XVFNMADD_S |
| 1530 | UINT64_C(182452224), // XVFNMSUB_D |
| 1531 | UINT64_C(181403648), // XVFNMSUB_S |
| 1532 | UINT64_C(1990006784), // XVFRECIPE_D |
| 1533 | UINT64_C(1990005760), // XVFRECIPE_S |
| 1534 | UINT64_C(1989998592), // XVFRECIP_D |
| 1535 | UINT64_C(1989997568), // XVFRECIP_S |
| 1536 | UINT64_C(1990019072), // XVFRINTRM_D |
| 1537 | UINT64_C(1990018048), // XVFRINTRM_S |
| 1538 | UINT64_C(1990031360), // XVFRINTRNE_D |
| 1539 | UINT64_C(1990030336), // XVFRINTRNE_S |
| 1540 | UINT64_C(1990023168), // XVFRINTRP_D |
| 1541 | UINT64_C(1990022144), // XVFRINTRP_S |
| 1542 | UINT64_C(1990027264), // XVFRINTRZ_D |
| 1543 | UINT64_C(1990026240), // XVFRINTRZ_S |
| 1544 | UINT64_C(1990014976), // XVFRINT_D |
| 1545 | UINT64_C(1990013952), // XVFRINT_S |
| 1546 | UINT64_C(1990010880), // XVFRSQRTE_D |
| 1547 | UINT64_C(1990009856), // XVFRSQRTE_S |
| 1548 | UINT64_C(1990002688), // XVFRSQRT_D |
| 1549 | UINT64_C(1990001664), // XVFRSQRT_S |
| 1550 | UINT64_C(1989804032), // XVFRSTPI_B |
| 1551 | UINT64_C(1989836800), // XVFRSTPI_H |
| 1552 | UINT64_C(1965752320), // XVFRSTP_B |
| 1553 | UINT64_C(1965785088), // XVFRSTP_H |
| 1554 | UINT64_C(1989994496), // XVFSQRT_D |
| 1555 | UINT64_C(1989993472), // XVFSQRT_S |
| 1556 | UINT64_C(1966276608), // XVFSUB_D |
| 1557 | UINT64_C(1966243840), // XVFSUB_S |
| 1558 | UINT64_C(1990099968), // XVFTINTH_L_S |
| 1559 | UINT64_C(1990098944), // XVFTINTL_L_S |
| 1560 | UINT64_C(1990102016), // XVFTINTRMH_L_S |
| 1561 | UINT64_C(1990100992), // XVFTINTRML_L_S |
| 1562 | UINT64_C(1990081536), // XVFTINTRM_L_D |
| 1563 | UINT64_C(1967783936), // XVFTINTRM_W_D |
| 1564 | UINT64_C(1990080512), // XVFTINTRM_W_S |
| 1565 | UINT64_C(1990108160), // XVFTINTRNEH_L_S |
| 1566 | UINT64_C(1990107136), // XVFTINTRNEL_L_S |
| 1567 | UINT64_C(1990087680), // XVFTINTRNE_L_D |
| 1568 | UINT64_C(1967882240), // XVFTINTRNE_W_D |
| 1569 | UINT64_C(1990086656), // XVFTINTRNE_W_S |
| 1570 | UINT64_C(1990104064), // XVFTINTRPH_L_S |
| 1571 | UINT64_C(1990103040), // XVFTINTRPL_L_S |
| 1572 | UINT64_C(1990083584), // XVFTINTRP_L_D |
| 1573 | UINT64_C(1967816704), // XVFTINTRP_W_D |
| 1574 | UINT64_C(1990082560), // XVFTINTRP_W_S |
| 1575 | UINT64_C(1990106112), // XVFTINTRZH_L_S |
| 1576 | UINT64_C(1990105088), // XVFTINTRZL_L_S |
| 1577 | UINT64_C(1990095872), // XVFTINTRZ_LU_D |
| 1578 | UINT64_C(1990085632), // XVFTINTRZ_L_D |
| 1579 | UINT64_C(1990094848), // XVFTINTRZ_WU_S |
| 1580 | UINT64_C(1967849472), // XVFTINTRZ_W_D |
| 1581 | UINT64_C(1990084608), // XVFTINTRZ_W_S |
| 1582 | UINT64_C(1990089728), // XVFTINT_LU_D |
| 1583 | UINT64_C(1990079488), // XVFTINT_L_D |
| 1584 | UINT64_C(1990088704), // XVFTINT_WU_S |
| 1585 | UINT64_C(1967751168), // XVFTINT_W_D |
| 1586 | UINT64_C(1990078464), // XVFTINT_W_S |
| 1587 | UINT64_C(1951989760), // XVHADDW_DU_WU |
| 1588 | UINT64_C(1951727616), // XVHADDW_D_W |
| 1589 | UINT64_C(1951924224), // XVHADDW_HU_BU |
| 1590 | UINT64_C(1951662080), // XVHADDW_H_B |
| 1591 | UINT64_C(1952022528), // XVHADDW_QU_DU |
| 1592 | UINT64_C(1951760384), // XVHADDW_Q_D |
| 1593 | UINT64_C(1951956992), // XVHADDW_WU_HU |
| 1594 | UINT64_C(1951694848), // XVHADDW_W_H |
| 1595 | UINT64_C(1990164480), // XVHSELI_D |
| 1596 | UINT64_C(1952120832), // XVHSUBW_DU_WU |
| 1597 | UINT64_C(1951858688), // XVHSUBW_D_W |
| 1598 | UINT64_C(1952055296), // XVHSUBW_HU_BU |
| 1599 | UINT64_C(1951793152), // XVHSUBW_H_B |
| 1600 | UINT64_C(1952153600), // XVHSUBW_QU_DU |
| 1601 | UINT64_C(1951891456), // XVHSUBW_Q_D |
| 1602 | UINT64_C(1952088064), // XVHSUBW_WU_HU |
| 1603 | UINT64_C(1951825920), // XVHSUBW_W_H |
| 1604 | UINT64_C(1964769280), // XVILVH_B |
| 1605 | UINT64_C(1964867584), // XVILVH_D |
| 1606 | UINT64_C(1964802048), // XVILVH_H |
| 1607 | UINT64_C(1964834816), // XVILVH_W |
| 1608 | UINT64_C(1964638208), // XVILVL_B |
| 1609 | UINT64_C(1964736512), // XVILVL_D |
| 1610 | UINT64_C(1964670976), // XVILVL_H |
| 1611 | UINT64_C(1964703744), // XVILVL_W |
| 1612 | UINT64_C(1995169792), // XVINSGR2VR_D |
| 1613 | UINT64_C(1995161600), // XVINSGR2VR_W |
| 1614 | UINT64_C(1996480512), // XVINSVE0_D |
| 1615 | UINT64_C(1996472320), // XVINSVE0_W |
| 1616 | UINT64_C(746586112), // XVLD |
| 1617 | UINT64_C(2011168768), // XVLDI |
| 1618 | UINT64_C(847249408), // XVLDREPL_B |
| 1619 | UINT64_C(839909376), // XVLDREPL_D |
| 1620 | UINT64_C(843055104), // XVLDREPL_H |
| 1621 | UINT64_C(840957952), // XVLDREPL_W |
| 1622 | UINT64_C(944242688), // XVLDX |
| 1623 | UINT64_C(1957494784), // XVMADDWEV_D_W |
| 1624 | UINT64_C(1958019072), // XVMADDWEV_D_WU |
| 1625 | UINT64_C(1958543360), // XVMADDWEV_D_WU_W |
| 1626 | UINT64_C(1957429248), // XVMADDWEV_H_B |
| 1627 | UINT64_C(1957953536), // XVMADDWEV_H_BU |
| 1628 | UINT64_C(1958477824), // XVMADDWEV_H_BU_B |
| 1629 | UINT64_C(1957527552), // XVMADDWEV_Q_D |
| 1630 | UINT64_C(1958051840), // XVMADDWEV_Q_DU |
| 1631 | UINT64_C(1958576128), // XVMADDWEV_Q_DU_D |
| 1632 | UINT64_C(1957462016), // XVMADDWEV_W_H |
| 1633 | UINT64_C(1957986304), // XVMADDWEV_W_HU |
| 1634 | UINT64_C(1958510592), // XVMADDWEV_W_HU_H |
| 1635 | UINT64_C(1957625856), // XVMADDWOD_D_W |
| 1636 | UINT64_C(1958150144), // XVMADDWOD_D_WU |
| 1637 | UINT64_C(1958674432), // XVMADDWOD_D_WU_W |
| 1638 | UINT64_C(1957560320), // XVMADDWOD_H_B |
| 1639 | UINT64_C(1958084608), // XVMADDWOD_H_BU |
| 1640 | UINT64_C(1958608896), // XVMADDWOD_H_BU_B |
| 1641 | UINT64_C(1957658624), // XVMADDWOD_Q_D |
| 1642 | UINT64_C(1958182912), // XVMADDWOD_Q_DU |
| 1643 | UINT64_C(1958707200), // XVMADDWOD_Q_DU_D |
| 1644 | UINT64_C(1957593088), // XVMADDWOD_W_H |
| 1645 | UINT64_C(1958117376), // XVMADDWOD_W_HU |
| 1646 | UINT64_C(1958641664), // XVMADDWOD_W_HU_H |
| 1647 | UINT64_C(1957167104), // XVMADD_B |
| 1648 | UINT64_C(1957265408), // XVMADD_D |
| 1649 | UINT64_C(1957199872), // XVMADD_H |
| 1650 | UINT64_C(1957232640), // XVMADD_W |
| 1651 | UINT64_C(1989148672), // XVMAXI_B |
| 1652 | UINT64_C(1989410816), // XVMAXI_BU |
| 1653 | UINT64_C(1989246976), // XVMAXI_D |
| 1654 | UINT64_C(1989509120), // XVMAXI_DU |
| 1655 | UINT64_C(1989181440), // XVMAXI_H |
| 1656 | UINT64_C(1989443584), // XVMAXI_HU |
| 1657 | UINT64_C(1989214208), // XVMAXI_W |
| 1658 | UINT64_C(1989476352), // XVMAXI_WU |
| 1659 | UINT64_C(1953497088), // XVMAX_B |
| 1660 | UINT64_C(1953759232), // XVMAX_BU |
| 1661 | UINT64_C(1953595392), // XVMAX_D |
| 1662 | UINT64_C(1953857536), // XVMAX_DU |
| 1663 | UINT64_C(1953529856), // XVMAX_H |
| 1664 | UINT64_C(1953792000), // XVMAX_HU |
| 1665 | UINT64_C(1953562624), // XVMAX_W |
| 1666 | UINT64_C(1953824768), // XVMAX_WU |
| 1667 | UINT64_C(1989279744), // XVMINI_B |
| 1668 | UINT64_C(1989541888), // XVMINI_BU |
| 1669 | UINT64_C(1989378048), // XVMINI_D |
| 1670 | UINT64_C(1989640192), // XVMINI_DU |
| 1671 | UINT64_C(1989312512), // XVMINI_H |
| 1672 | UINT64_C(1989574656), // XVMINI_HU |
| 1673 | UINT64_C(1989345280), // XVMINI_W |
| 1674 | UINT64_C(1989607424), // XVMINI_WU |
| 1675 | UINT64_C(1953628160), // XVMIN_B |
| 1676 | UINT64_C(1953890304), // XVMIN_BU |
| 1677 | UINT64_C(1953726464), // XVMIN_D |
| 1678 | UINT64_C(1953988608), // XVMIN_DU |
| 1679 | UINT64_C(1953660928), // XVMIN_H |
| 1680 | UINT64_C(1953923072), // XVMIN_HU |
| 1681 | UINT64_C(1953693696), // XVMIN_W |
| 1682 | UINT64_C(1953955840), // XVMIN_WU |
| 1683 | UINT64_C(1960968192), // XVMOD_B |
| 1684 | UINT64_C(1961230336), // XVMOD_BU |
| 1685 | UINT64_C(1961066496), // XVMOD_D |
| 1686 | UINT64_C(1961328640), // XVMOD_DU |
| 1687 | UINT64_C(1961000960), // XVMOD_H |
| 1688 | UINT64_C(1961263104), // XVMOD_HU |
| 1689 | UINT64_C(1961033728), // XVMOD_W |
| 1690 | UINT64_C(1961295872), // XVMOD_WU |
| 1691 | UINT64_C(1989955584), // XVMSKGEZ_B |
| 1692 | UINT64_C(1989951488), // XVMSKLTZ_B |
| 1693 | UINT64_C(1989954560), // XVMSKLTZ_D |
| 1694 | UINT64_C(1989952512), // XVMSKLTZ_H |
| 1695 | UINT64_C(1989953536), // XVMSKLTZ_W |
| 1696 | UINT64_C(1989959680), // XVMSKNZ_B |
| 1697 | UINT64_C(1957298176), // XVMSUB_B |
| 1698 | UINT64_C(1957396480), // XVMSUB_D |
| 1699 | UINT64_C(1957330944), // XVMSUB_H |
| 1700 | UINT64_C(1957363712), // XVMSUB_W |
| 1701 | UINT64_C(1954938880), // XVMUH_B |
| 1702 | UINT64_C(1955069952), // XVMUH_BU |
| 1703 | UINT64_C(1955037184), // XVMUH_D |
| 1704 | UINT64_C(1955168256), // XVMUH_DU |
| 1705 | UINT64_C(1954971648), // XVMUH_H |
| 1706 | UINT64_C(1955102720), // XVMUH_HU |
| 1707 | UINT64_C(1955004416), // XVMUH_W |
| 1708 | UINT64_C(1955135488), // XVMUH_WU |
| 1709 | UINT64_C(1955659776), // XVMULWEV_D_W |
| 1710 | UINT64_C(1956184064), // XVMULWEV_D_WU |
| 1711 | UINT64_C(1956708352), // XVMULWEV_D_WU_W |
| 1712 | UINT64_C(1955594240), // XVMULWEV_H_B |
| 1713 | UINT64_C(1956118528), // XVMULWEV_H_BU |
| 1714 | UINT64_C(1956642816), // XVMULWEV_H_BU_B |
| 1715 | UINT64_C(1955692544), // XVMULWEV_Q_D |
| 1716 | UINT64_C(1956216832), // XVMULWEV_Q_DU |
| 1717 | UINT64_C(1956741120), // XVMULWEV_Q_DU_D |
| 1718 | UINT64_C(1955627008), // XVMULWEV_W_H |
| 1719 | UINT64_C(1956151296), // XVMULWEV_W_HU |
| 1720 | UINT64_C(1956675584), // XVMULWEV_W_HU_H |
| 1721 | UINT64_C(1955790848), // XVMULWOD_D_W |
| 1722 | UINT64_C(1956315136), // XVMULWOD_D_WU |
| 1723 | UINT64_C(1956839424), // XVMULWOD_D_WU_W |
| 1724 | UINT64_C(1955725312), // XVMULWOD_H_B |
| 1725 | UINT64_C(1956249600), // XVMULWOD_H_BU |
| 1726 | UINT64_C(1956773888), // XVMULWOD_H_BU_B |
| 1727 | UINT64_C(1955823616), // XVMULWOD_Q_D |
| 1728 | UINT64_C(1956347904), // XVMULWOD_Q_DU |
| 1729 | UINT64_C(1956872192), // XVMULWOD_Q_DU_D |
| 1730 | UINT64_C(1955758080), // XVMULWOD_W_H |
| 1731 | UINT64_C(1956282368), // XVMULWOD_W_HU |
| 1732 | UINT64_C(1956806656), // XVMULWOD_W_HU_H |
| 1733 | UINT64_C(1954807808), // XVMUL_B |
| 1734 | UINT64_C(1954906112), // XVMUL_D |
| 1735 | UINT64_C(1954840576), // XVMUL_H |
| 1736 | UINT64_C(1954873344), // XVMUL_W |
| 1737 | UINT64_C(1989947392), // XVNEG_B |
| 1738 | UINT64_C(1989950464), // XVNEG_D |
| 1739 | UINT64_C(1989948416), // XVNEG_H |
| 1740 | UINT64_C(1989949440), // XVNEG_W |
| 1741 | UINT64_C(2010906624), // XVNORI_B |
| 1742 | UINT64_C(1965522944), // XVNOR_V |
| 1743 | UINT64_C(2010382336), // XVORI_B |
| 1744 | UINT64_C(1965588480), // XVORN_V |
| 1745 | UINT64_C(1965457408), // XVOR_V |
| 1746 | UINT64_C(1964376064), // XVPACKEV_B |
| 1747 | UINT64_C(1964474368), // XVPACKEV_D |
| 1748 | UINT64_C(1964408832), // XVPACKEV_H |
| 1749 | UINT64_C(1964441600), // XVPACKEV_W |
| 1750 | UINT64_C(1964507136), // XVPACKOD_B |
| 1751 | UINT64_C(1964605440), // XVPACKOD_D |
| 1752 | UINT64_C(1964539904), // XVPACKOD_H |
| 1753 | UINT64_C(1964572672), // XVPACKOD_W |
| 1754 | UINT64_C(1989943296), // XVPCNT_B |
| 1755 | UINT64_C(1989946368), // XVPCNT_D |
| 1756 | UINT64_C(1989944320), // XVPCNT_H |
| 1757 | UINT64_C(1989945344), // XVPCNT_W |
| 1758 | UINT64_C(2011693056), // XVPERMI_D |
| 1759 | UINT64_C(2011955200), // XVPERMI_Q |
| 1760 | UINT64_C(2011430912), // XVPERMI_W |
| 1761 | UINT64_C(1971126272), // XVPERM_W |
| 1762 | UINT64_C(1964900352), // XVPICKEV_B |
| 1763 | UINT64_C(1964998656), // XVPICKEV_D |
| 1764 | UINT64_C(1964933120), // XVPICKEV_H |
| 1765 | UINT64_C(1964965888), // XVPICKEV_W |
| 1766 | UINT64_C(1965031424), // XVPICKOD_B |
| 1767 | UINT64_C(1965129728), // XVPICKOD_D |
| 1768 | UINT64_C(1965064192), // XVPICKOD_H |
| 1769 | UINT64_C(1965096960), // XVPICKOD_W |
| 1770 | UINT64_C(1995431936), // XVPICKVE2GR_D |
| 1771 | UINT64_C(1995694080), // XVPICKVE2GR_DU |
| 1772 | UINT64_C(1995423744), // XVPICKVE2GR_W |
| 1773 | UINT64_C(1995685888), // XVPICKVE2GR_WU |
| 1774 | UINT64_C(1996742656), // XVPICKVE_D |
| 1775 | UINT64_C(1996734464), // XVPICKVE_W |
| 1776 | UINT64_C(1995931648), // XVREPL128VEI_B |
| 1777 | UINT64_C(1995960320), // XVREPL128VEI_D |
| 1778 | UINT64_C(1995948032), // XVREPL128VEI_H |
| 1779 | UINT64_C(1995956224), // XVREPL128VEI_W |
| 1780 | UINT64_C(1990131712), // XVREPLGR2VR_B |
| 1781 | UINT64_C(1990134784), // XVREPLGR2VR_D |
| 1782 | UINT64_C(1990132736), // XVREPLGR2VR_H |
| 1783 | UINT64_C(1990133760), // XVREPLGR2VR_W |
| 1784 | UINT64_C(1996947456), // XVREPLVE0_B |
| 1785 | UINT64_C(1997004800), // XVREPLVE0_D |
| 1786 | UINT64_C(1996980224), // XVREPLVE0_H |
| 1787 | UINT64_C(1997008896), // XVREPLVE0_Q |
| 1788 | UINT64_C(1996996608), // XVREPLVE0_W |
| 1789 | UINT64_C(1965162496), // XVREPLVE_B |
| 1790 | UINT64_C(1965260800), // XVREPLVE_D |
| 1791 | UINT64_C(1965195264), // XVREPLVE_H |
| 1792 | UINT64_C(1965228032), // XVREPLVE_W |
| 1793 | UINT64_C(1990205440), // XVROTRI_B |
| 1794 | UINT64_C(1990262784), // XVROTRI_D |
| 1795 | UINT64_C(1990213632), // XVROTRI_H |
| 1796 | UINT64_C(1990230016), // XVROTRI_W |
| 1797 | UINT64_C(1961754624), // XVROTR_B |
| 1798 | UINT64_C(1961852928), // XVROTR_D |
| 1799 | UINT64_C(1961787392), // XVROTR_H |
| 1800 | UINT64_C(1961820160), // XVROTR_W |
| 1801 | UINT64_C(1950744576), // XVSADD_B |
| 1802 | UINT64_C(1951006720), // XVSADD_BU |
| 1803 | UINT64_C(1950842880), // XVSADD_D |
| 1804 | UINT64_C(1951105024), // XVSADD_DU |
| 1805 | UINT64_C(1950777344), // XVSADD_H |
| 1806 | UINT64_C(1951039488), // XVSADD_HU |
| 1807 | UINT64_C(1950810112), // XVSADD_W |
| 1808 | UINT64_C(1951072256), // XVSADD_WU |
| 1809 | UINT64_C(1998856192), // XVSAT_B |
| 1810 | UINT64_C(1999118336), // XVSAT_BU |
| 1811 | UINT64_C(1998913536), // XVSAT_D |
| 1812 | UINT64_C(1999175680), // XVSAT_DU |
| 1813 | UINT64_C(1998864384), // XVSAT_H |
| 1814 | UINT64_C(1999126528), // XVSAT_HU |
| 1815 | UINT64_C(1998880768), // XVSAT_W |
| 1816 | UINT64_C(1999142912), // XVSAT_WU |
| 1817 | UINT64_C(1988100096), // XVSEQI_B |
| 1818 | UINT64_C(1988198400), // XVSEQI_D |
| 1819 | UINT64_C(1988132864), // XVSEQI_H |
| 1820 | UINT64_C(1988165632), // XVSEQI_W |
| 1821 | UINT64_C(1946157056), // XVSEQ_B |
| 1822 | UINT64_C(1946255360), // XVSEQ_D |
| 1823 | UINT64_C(1946189824), // XVSEQ_H |
| 1824 | UINT64_C(1946222592), // XVSEQ_W |
| 1825 | UINT64_C(1989980160), // XVSETALLNEZ_B |
| 1826 | UINT64_C(1989983232), // XVSETALLNEZ_D |
| 1827 | UINT64_C(1989981184), // XVSETALLNEZ_H |
| 1828 | UINT64_C(1989982208), // XVSETALLNEZ_W |
| 1829 | UINT64_C(1989976064), // XVSETANYEQZ_B |
| 1830 | UINT64_C(1989979136), // XVSETANYEQZ_D |
| 1831 | UINT64_C(1989977088), // XVSETANYEQZ_H |
| 1832 | UINT64_C(1989978112), // XVSETANYEQZ_W |
| 1833 | UINT64_C(1989974016), // XVSETEQZ_V |
| 1834 | UINT64_C(1989975040), // XVSETNEZ_V |
| 1835 | UINT64_C(2005925888), // XVSHUF4I_B |
| 1836 | UINT64_C(2006712320), // XVSHUF4I_D |
| 1837 | UINT64_C(2006188032), // XVSHUF4I_H |
| 1838 | UINT64_C(2006450176), // XVSHUF4I_W |
| 1839 | UINT64_C(224395264), // XVSHUF_B |
| 1840 | UINT64_C(1971027968), // XVSHUF_D |
| 1841 | UINT64_C(1970962432), // XVSHUF_H |
| 1842 | UINT64_C(1970995200), // XVSHUF_W |
| 1843 | UINT64_C(1965948928), // XVSIGNCOV_B |
| 1844 | UINT64_C(1966047232), // XVSIGNCOV_D |
| 1845 | UINT64_C(1965981696), // XVSIGNCOV_H |
| 1846 | UINT64_C(1966014464), // XVSIGNCOV_W |
| 1847 | UINT64_C(1988231168), // XVSLEI_B |
| 1848 | UINT64_C(1988362240), // XVSLEI_BU |
| 1849 | UINT64_C(1988329472), // XVSLEI_D |
| 1850 | UINT64_C(1988460544), // XVSLEI_DU |
| 1851 | UINT64_C(1988263936), // XVSLEI_H |
| 1852 | UINT64_C(1988395008), // XVSLEI_HU |
| 1853 | UINT64_C(1988296704), // XVSLEI_W |
| 1854 | UINT64_C(1988427776), // XVSLEI_WU |
| 1855 | UINT64_C(1946288128), // XVSLE_B |
| 1856 | UINT64_C(1946419200), // XVSLE_BU |
| 1857 | UINT64_C(1946386432), // XVSLE_D |
| 1858 | UINT64_C(1946517504), // XVSLE_DU |
| 1859 | UINT64_C(1946320896), // XVSLE_H |
| 1860 | UINT64_C(1946451968), // XVSLE_HU |
| 1861 | UINT64_C(1946353664), // XVSLE_W |
| 1862 | UINT64_C(1946484736), // XVSLE_WU |
| 1863 | UINT64_C(1999380480), // XVSLLI_B |
| 1864 | UINT64_C(1999437824), // XVSLLI_D |
| 1865 | UINT64_C(1999388672), // XVSLLI_H |
| 1866 | UINT64_C(1999405056), // XVSLLI_W |
| 1867 | UINT64_C(1997307904), // XVSLLWIL_DU_WU |
| 1868 | UINT64_C(1997045760), // XVSLLWIL_D_W |
| 1869 | UINT64_C(1997283328), // XVSLLWIL_HU_BU |
| 1870 | UINT64_C(1997021184), // XVSLLWIL_H_B |
| 1871 | UINT64_C(1997291520), // XVSLLWIL_WU_HU |
| 1872 | UINT64_C(1997029376), // XVSLLWIL_W_H |
| 1873 | UINT64_C(1961361408), // XVSLL_B |
| 1874 | UINT64_C(1961459712), // XVSLL_D |
| 1875 | UINT64_C(1961394176), // XVSLL_H |
| 1876 | UINT64_C(1961426944), // XVSLL_W |
| 1877 | UINT64_C(1988493312), // XVSLTI_B |
| 1878 | UINT64_C(1988624384), // XVSLTI_BU |
| 1879 | UINT64_C(1988591616), // XVSLTI_D |
| 1880 | UINT64_C(1988722688), // XVSLTI_DU |
| 1881 | UINT64_C(1988526080), // XVSLTI_H |
| 1882 | UINT64_C(1988657152), // XVSLTI_HU |
| 1883 | UINT64_C(1988558848), // XVSLTI_W |
| 1884 | UINT64_C(1988689920), // XVSLTI_WU |
| 1885 | UINT64_C(1946550272), // XVSLT_B |
| 1886 | UINT64_C(1946681344), // XVSLT_BU |
| 1887 | UINT64_C(1946648576), // XVSLT_D |
| 1888 | UINT64_C(1946779648), // XVSLT_DU |
| 1889 | UINT64_C(1946583040), // XVSLT_H |
| 1890 | UINT64_C(1946714112), // XVSLT_HU |
| 1891 | UINT64_C(1946615808), // XVSLT_W |
| 1892 | UINT64_C(1946746880), // XVSLT_WU |
| 1893 | UINT64_C(1999904768), // XVSRAI_B |
| 1894 | UINT64_C(1999962112), // XVSRAI_D |
| 1895 | UINT64_C(1999912960), // XVSRAI_H |
| 1896 | UINT64_C(1999929344), // XVSRAI_W |
| 1897 | UINT64_C(2002272256), // XVSRANI_B_H |
| 1898 | UINT64_C(2002386944), // XVSRANI_D_Q |
| 1899 | UINT64_C(2002288640), // XVSRANI_H_W |
| 1900 | UINT64_C(2002321408), // XVSRANI_W_D |
| 1901 | UINT64_C(1962311680), // XVSRAN_B_H |
| 1902 | UINT64_C(1962344448), // XVSRAN_H_W |
| 1903 | UINT64_C(1962377216), // XVSRAN_W_D |
| 1904 | UINT64_C(1990729728), // XVSRARI_B |
| 1905 | UINT64_C(1990787072), // XVSRARI_D |
| 1906 | UINT64_C(1990737920), // XVSRARI_H |
| 1907 | UINT64_C(1990754304), // XVSRARI_W |
| 1908 | UINT64_C(2002534400), // XVSRARNI_B_H |
| 1909 | UINT64_C(2002649088), // XVSRARNI_D_Q |
| 1910 | UINT64_C(2002550784), // XVSRARNI_H_W |
| 1911 | UINT64_C(2002583552), // XVSRARNI_W_D |
| 1912 | UINT64_C(1962573824), // XVSRARN_B_H |
| 1913 | UINT64_C(1962606592), // XVSRARN_H_W |
| 1914 | UINT64_C(1962639360), // XVSRARN_W_D |
| 1915 | UINT64_C(1962016768), // XVSRAR_B |
| 1916 | UINT64_C(1962115072), // XVSRAR_D |
| 1917 | UINT64_C(1962049536), // XVSRAR_H |
| 1918 | UINT64_C(1962082304), // XVSRAR_W |
| 1919 | UINT64_C(1961623552), // XVSRA_B |
| 1920 | UINT64_C(1961721856), // XVSRA_D |
| 1921 | UINT64_C(1961656320), // XVSRA_H |
| 1922 | UINT64_C(1961689088), // XVSRA_W |
| 1923 | UINT64_C(1999642624), // XVSRLI_B |
| 1924 | UINT64_C(1999699968), // XVSRLI_D |
| 1925 | UINT64_C(1999650816), // XVSRLI_H |
| 1926 | UINT64_C(1999667200), // XVSRLI_W |
| 1927 | UINT64_C(2000699392), // XVSRLNI_B_H |
| 1928 | UINT64_C(2000814080), // XVSRLNI_D_Q |
| 1929 | UINT64_C(2000715776), // XVSRLNI_H_W |
| 1930 | UINT64_C(2000748544), // XVSRLNI_W_D |
| 1931 | UINT64_C(1962180608), // XVSRLN_B_H |
| 1932 | UINT64_C(1962213376), // XVSRLN_H_W |
| 1933 | UINT64_C(1962246144), // XVSRLN_W_D |
| 1934 | UINT64_C(1990467584), // XVSRLRI_B |
| 1935 | UINT64_C(1990524928), // XVSRLRI_D |
| 1936 | UINT64_C(1990475776), // XVSRLRI_H |
| 1937 | UINT64_C(1990492160), // XVSRLRI_W |
| 1938 | UINT64_C(2000961536), // XVSRLRNI_B_H |
| 1939 | UINT64_C(2001076224), // XVSRLRNI_D_Q |
| 1940 | UINT64_C(2000977920), // XVSRLRNI_H_W |
| 1941 | UINT64_C(2001010688), // XVSRLRNI_W_D |
| 1942 | UINT64_C(1962442752), // XVSRLRN_B_H |
| 1943 | UINT64_C(1962475520), // XVSRLRN_H_W |
| 1944 | UINT64_C(1962508288), // XVSRLRN_W_D |
| 1945 | UINT64_C(1961885696), // XVSRLR_B |
| 1946 | UINT64_C(1961984000), // XVSRLR_D |
| 1947 | UINT64_C(1961918464), // XVSRLR_H |
| 1948 | UINT64_C(1961951232), // XVSRLR_W |
| 1949 | UINT64_C(1961492480), // XVSRL_B |
| 1950 | UINT64_C(1961590784), // XVSRL_D |
| 1951 | UINT64_C(1961525248), // XVSRL_H |
| 1952 | UINT64_C(1961558016), // XVSRL_W |
| 1953 | UINT64_C(2003058688), // XVSSRANI_BU_H |
| 1954 | UINT64_C(2002796544), // XVSSRANI_B_H |
| 1955 | UINT64_C(2003173376), // XVSSRANI_DU_Q |
| 1956 | UINT64_C(2002911232), // XVSSRANI_D_Q |
| 1957 | UINT64_C(2003075072), // XVSSRANI_HU_W |
| 1958 | UINT64_C(2002812928), // XVSSRANI_H_W |
| 1959 | UINT64_C(2003107840), // XVSSRANI_WU_D |
| 1960 | UINT64_C(2002845696), // XVSSRANI_W_D |
| 1961 | UINT64_C(1963360256), // XVSSRAN_BU_H |
| 1962 | UINT64_C(1962835968), // XVSSRAN_B_H |
| 1963 | UINT64_C(1963393024), // XVSSRAN_HU_W |
| 1964 | UINT64_C(1962868736), // XVSSRAN_H_W |
| 1965 | UINT64_C(1963425792), // XVSSRAN_WU_D |
| 1966 | UINT64_C(1962901504), // XVSSRAN_W_D |
| 1967 | UINT64_C(2003582976), // XVSSRARNI_BU_H |
| 1968 | UINT64_C(2003320832), // XVSSRARNI_B_H |
| 1969 | UINT64_C(2003697664), // XVSSRARNI_DU_Q |
| 1970 | UINT64_C(2003435520), // XVSSRARNI_D_Q |
| 1971 | UINT64_C(2003599360), // XVSSRARNI_HU_W |
| 1972 | UINT64_C(2003337216), // XVSSRARNI_H_W |
| 1973 | UINT64_C(2003632128), // XVSSRARNI_WU_D |
| 1974 | UINT64_C(2003369984), // XVSSRARNI_W_D |
| 1975 | UINT64_C(1963622400), // XVSSRARN_BU_H |
| 1976 | UINT64_C(1963098112), // XVSSRARN_B_H |
| 1977 | UINT64_C(1963655168), // XVSSRARN_HU_W |
| 1978 | UINT64_C(1963130880), // XVSSRARN_H_W |
| 1979 | UINT64_C(1963687936), // XVSSRARN_WU_D |
| 1980 | UINT64_C(1963163648), // XVSSRARN_W_D |
| 1981 | UINT64_C(2001485824), // XVSSRLNI_BU_H |
| 1982 | UINT64_C(2001223680), // XVSSRLNI_B_H |
| 1983 | UINT64_C(2001600512), // XVSSRLNI_DU_Q |
| 1984 | UINT64_C(2001338368), // XVSSRLNI_D_Q |
| 1985 | UINT64_C(2001502208), // XVSSRLNI_HU_W |
| 1986 | UINT64_C(2001240064), // XVSSRLNI_H_W |
| 1987 | UINT64_C(2001534976), // XVSSRLNI_WU_D |
| 1988 | UINT64_C(2001272832), // XVSSRLNI_W_D |
| 1989 | UINT64_C(1963229184), // XVSSRLN_BU_H |
| 1990 | UINT64_C(1962704896), // XVSSRLN_B_H |
| 1991 | UINT64_C(1963261952), // XVSSRLN_HU_W |
| 1992 | UINT64_C(1962737664), // XVSSRLN_H_W |
| 1993 | UINT64_C(1963294720), // XVSSRLN_WU_D |
| 1994 | UINT64_C(1962770432), // XVSSRLN_W_D |
| 1995 | UINT64_C(2002010112), // XVSSRLRNI_BU_H |
| 1996 | UINT64_C(2001747968), // XVSSRLRNI_B_H |
| 1997 | UINT64_C(2002124800), // XVSSRLRNI_DU_Q |
| 1998 | UINT64_C(2001862656), // XVSSRLRNI_D_Q |
| 1999 | UINT64_C(2002026496), // XVSSRLRNI_HU_W |
| 2000 | UINT64_C(2001764352), // XVSSRLRNI_H_W |
| 2001 | UINT64_C(2002059264), // XVSSRLRNI_WU_D |
| 2002 | UINT64_C(2001797120), // XVSSRLRNI_W_D |
| 2003 | UINT64_C(1963491328), // XVSSRLRN_BU_H |
| 2004 | UINT64_C(1962967040), // XVSSRLRN_B_H |
| 2005 | UINT64_C(1963524096), // XVSSRLRN_HU_W |
| 2006 | UINT64_C(1962999808), // XVSSRLRN_H_W |
| 2007 | UINT64_C(1963556864), // XVSSRLRN_WU_D |
| 2008 | UINT64_C(1963032576), // XVSSRLRN_W_D |
| 2009 | UINT64_C(1950875648), // XVSSUB_B |
| 2010 | UINT64_C(1951137792), // XVSSUB_BU |
| 2011 | UINT64_C(1950973952), // XVSSUB_D |
| 2012 | UINT64_C(1951236096), // XVSSUB_DU |
| 2013 | UINT64_C(1950908416), // XVSSUB_H |
| 2014 | UINT64_C(1951170560), // XVSSUB_HU |
| 2015 | UINT64_C(1950941184), // XVSSUB_W |
| 2016 | UINT64_C(1951203328), // XVSSUB_WU |
| 2017 | UINT64_C(750780416), // XVST |
| 2018 | UINT64_C(864026624), // XVSTELM_B |
| 2019 | UINT64_C(856686592), // XVSTELM_D |
| 2020 | UINT64_C(859832320), // XVSTELM_H |
| 2021 | UINT64_C(857735168), // XVSTELM_W |
| 2022 | UINT64_C(944504832), // XVSTX |
| 2023 | UINT64_C(1988886528), // XVSUBI_BU |
| 2024 | UINT64_C(1988984832), // XVSUBI_DU |
| 2025 | UINT64_C(1988919296), // XVSUBI_HU |
| 2026 | UINT64_C(1988952064), // XVSUBI_WU |
| 2027 | UINT64_C(1948319744), // XVSUBWEV_D_W |
| 2028 | UINT64_C(1949368320), // XVSUBWEV_D_WU |
| 2029 | UINT64_C(1948254208), // XVSUBWEV_H_B |
| 2030 | UINT64_C(1949302784), // XVSUBWEV_H_BU |
| 2031 | UINT64_C(1948352512), // XVSUBWEV_Q_D |
| 2032 | UINT64_C(1949401088), // XVSUBWEV_Q_DU |
| 2033 | UINT64_C(1948286976), // XVSUBWEV_W_H |
| 2034 | UINT64_C(1949335552), // XVSUBWEV_W_HU |
| 2035 | UINT64_C(1948581888), // XVSUBWOD_D_W |
| 2036 | UINT64_C(1949630464), // XVSUBWOD_D_WU |
| 2037 | UINT64_C(1948516352), // XVSUBWOD_H_B |
| 2038 | UINT64_C(1949564928), // XVSUBWOD_H_BU |
| 2039 | UINT64_C(1948614656), // XVSUBWOD_Q_D |
| 2040 | UINT64_C(1949663232), // XVSUBWOD_Q_DU |
| 2041 | UINT64_C(1948549120), // XVSUBWOD_W_H |
| 2042 | UINT64_C(1949597696), // XVSUBWOD_W_HU |
| 2043 | UINT64_C(1946943488), // XVSUB_B |
| 2044 | UINT64_C(1947041792), // XVSUB_D |
| 2045 | UINT64_C(1946976256), // XVSUB_H |
| 2046 | UINT64_C(1965916160), // XVSUB_Q |
| 2047 | UINT64_C(1947009024), // XVSUB_W |
| 2048 | UINT64_C(2010644480), // XVXORI_B |
| 2049 | UINT64_C(1965490176), // XVXOR_V |
| 2050 | }; |
| 2051 | constexpr unsigned FirstSupportedOpcode = 446; |
| 2052 | |
| 2053 | const unsigned opcode = MI.getOpcode(); |
| 2054 | if (opcode < FirstSupportedOpcode) |
| 2055 | reportUnsupportedInst(Inst: MI); |
| 2056 | unsigned TableIndex = opcode - FirstSupportedOpcode; |
| 2057 | uint64_t Value = InstBits[TableIndex]; |
| 2058 | uint64_t op = 0; |
| 2059 | (void)op; // suppress warning |
| 2060 | switch (opcode) { |
| 2061 | case LoongArch::ERTN: |
| 2062 | case LoongArch::GTLBFLUSH: |
| 2063 | case LoongArch::TLBCLR: |
| 2064 | case LoongArch::TLBFILL: |
| 2065 | case LoongArch::TLBFLUSH: |
| 2066 | case LoongArch::TLBRD: |
| 2067 | case LoongArch::TLBSRCH: |
| 2068 | case LoongArch::TLBWR: |
| 2069 | case LoongArch::X86CLRTM: |
| 2070 | case LoongArch::X86DECTOP: |
| 2071 | case LoongArch::X86INCTOP: |
| 2072 | case LoongArch::X86SETTM: { |
| 2073 | break; |
| 2074 | } |
| 2075 | case LoongArch::FSEL_xD: |
| 2076 | case LoongArch::FSEL_xS: { |
| 2077 | // op: ca |
| 2078 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2079 | Value |= (op & 0x7) << 15; |
| 2080 | // op: fk |
| 2081 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2082 | Value |= (op & 0x1f) << 10; |
| 2083 | // op: fj |
| 2084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2085 | Value |= (op & 0x1f) << 5; |
| 2086 | // op: fd |
| 2087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2088 | Value |= (op & 0x1f); |
| 2089 | break; |
| 2090 | } |
| 2091 | case LoongArch::SET_CFR_FALSE: |
| 2092 | case LoongArch::SET_CFR_TRUE: { |
| 2093 | // op: cd |
| 2094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2095 | Value |= (op & 0x7); |
| 2096 | break; |
| 2097 | } |
| 2098 | case LoongArch::CSRRD: |
| 2099 | case LoongArch::GCSRRD: { |
| 2100 | // op: csr_num |
| 2101 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2102 | Value |= (op & 0x3fff) << 10; |
| 2103 | // op: rd |
| 2104 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2105 | Value |= (op & 0x1f); |
| 2106 | break; |
| 2107 | } |
| 2108 | case LoongArch::CSRWR: |
| 2109 | case LoongArch::GCSRWR: { |
| 2110 | // op: csr_num |
| 2111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2112 | Value |= (op & 0x3fff) << 10; |
| 2113 | // op: rd |
| 2114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2115 | Value |= (op & 0x1f); |
| 2116 | break; |
| 2117 | } |
| 2118 | case LoongArch::CSRXCHG: |
| 2119 | case LoongArch::GCSRXCHG: { |
| 2120 | // op: csr_num |
| 2121 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2122 | Value |= (op & 0x3fff) << 10; |
| 2123 | // op: rj |
| 2124 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2125 | Value |= (op & 0x1f) << 5; |
| 2126 | // op: rd |
| 2127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2128 | Value |= (op & 0x1f); |
| 2129 | break; |
| 2130 | } |
| 2131 | case LoongArch::FMADD_D: |
| 2132 | case LoongArch::FMADD_S: |
| 2133 | case LoongArch::FMSUB_D: |
| 2134 | case LoongArch::FMSUB_S: |
| 2135 | case LoongArch::FNMADD_D: |
| 2136 | case LoongArch::FNMADD_S: |
| 2137 | case LoongArch::FNMSUB_D: |
| 2138 | case LoongArch::FNMSUB_S: { |
| 2139 | // op: fa |
| 2140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2141 | Value |= (op & 0x1f) << 15; |
| 2142 | // op: fk |
| 2143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2144 | Value |= (op & 0x1f) << 10; |
| 2145 | // op: fj |
| 2146 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2147 | Value |= (op & 0x1f) << 5; |
| 2148 | // op: fd |
| 2149 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2150 | Value |= (op & 0x1f); |
| 2151 | break; |
| 2152 | } |
| 2153 | case LoongArch::FABS_D: |
| 2154 | case LoongArch::FABS_S: |
| 2155 | case LoongArch::FCLASS_D: |
| 2156 | case LoongArch::FCLASS_S: |
| 2157 | case LoongArch::FCVT_D_S: |
| 2158 | case LoongArch::FCVT_LD_D: |
| 2159 | case LoongArch::FCVT_S_D: |
| 2160 | case LoongArch::FCVT_UD_D: |
| 2161 | case LoongArch::FFINT_D_L: |
| 2162 | case LoongArch::FFINT_D_W: |
| 2163 | case LoongArch::FFINT_S_L: |
| 2164 | case LoongArch::FFINT_S_W: |
| 2165 | case LoongArch::FLOGB_D: |
| 2166 | case LoongArch::FLOGB_S: |
| 2167 | case LoongArch::FNEG_D: |
| 2168 | case LoongArch::FNEG_S: |
| 2169 | case LoongArch::FRECIPE_D: |
| 2170 | case LoongArch::FRECIPE_S: |
| 2171 | case LoongArch::FRECIP_D: |
| 2172 | case LoongArch::FRECIP_S: |
| 2173 | case LoongArch::FRINT_D: |
| 2174 | case LoongArch::FRINT_S: |
| 2175 | case LoongArch::FRSQRTE_D: |
| 2176 | case LoongArch::FRSQRTE_S: |
| 2177 | case LoongArch::FRSQRT_D: |
| 2178 | case LoongArch::FRSQRT_S: |
| 2179 | case LoongArch::FSQRT_D: |
| 2180 | case LoongArch::FSQRT_S: |
| 2181 | case LoongArch::FTINTRM_L_D: |
| 2182 | case LoongArch::FTINTRM_L_S: |
| 2183 | case LoongArch::FTINTRM_W_D: |
| 2184 | case LoongArch::FTINTRM_W_S: |
| 2185 | case LoongArch::FTINTRNE_L_D: |
| 2186 | case LoongArch::FTINTRNE_L_S: |
| 2187 | case LoongArch::FTINTRNE_W_D: |
| 2188 | case LoongArch::FTINTRNE_W_S: |
| 2189 | case LoongArch::FTINTRP_L_D: |
| 2190 | case LoongArch::FTINTRP_L_S: |
| 2191 | case LoongArch::FTINTRP_W_D: |
| 2192 | case LoongArch::FTINTRP_W_S: |
| 2193 | case LoongArch::FTINTRZ_L_D: |
| 2194 | case LoongArch::FTINTRZ_L_S: |
| 2195 | case LoongArch::FTINTRZ_W_D: |
| 2196 | case LoongArch::FTINTRZ_W_S: |
| 2197 | case LoongArch::FTINT_L_D: |
| 2198 | case LoongArch::FTINT_L_S: |
| 2199 | case LoongArch::FTINT_W_D: |
| 2200 | case LoongArch::FTINT_W_S: { |
| 2201 | // op: fj |
| 2202 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2203 | Value |= (op & 0x1f) << 5; |
| 2204 | // op: fd |
| 2205 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2206 | Value |= (op & 0x1f); |
| 2207 | break; |
| 2208 | } |
| 2209 | case LoongArch::FCMP_CAF_D: |
| 2210 | case LoongArch::FCMP_CAF_S: |
| 2211 | case LoongArch::FCMP_CEQ_D: |
| 2212 | case LoongArch::FCMP_CEQ_S: |
| 2213 | case LoongArch::FCMP_CLE_D: |
| 2214 | case LoongArch::FCMP_CLE_S: |
| 2215 | case LoongArch::FCMP_CLT_D: |
| 2216 | case LoongArch::FCMP_CLT_S: |
| 2217 | case LoongArch::FCMP_CNE_D: |
| 2218 | case LoongArch::FCMP_CNE_S: |
| 2219 | case LoongArch::FCMP_COR_D: |
| 2220 | case LoongArch::FCMP_COR_S: |
| 2221 | case LoongArch::FCMP_CUEQ_D: |
| 2222 | case LoongArch::FCMP_CUEQ_S: |
| 2223 | case LoongArch::FCMP_CULE_D: |
| 2224 | case LoongArch::FCMP_CULE_S: |
| 2225 | case LoongArch::FCMP_CULT_D: |
| 2226 | case LoongArch::FCMP_CULT_S: |
| 2227 | case LoongArch::FCMP_CUNE_D: |
| 2228 | case LoongArch::FCMP_CUNE_S: |
| 2229 | case LoongArch::FCMP_CUN_D: |
| 2230 | case LoongArch::FCMP_CUN_S: |
| 2231 | case LoongArch::FCMP_SAF_D: |
| 2232 | case LoongArch::FCMP_SAF_S: |
| 2233 | case LoongArch::FCMP_SEQ_D: |
| 2234 | case LoongArch::FCMP_SEQ_S: |
| 2235 | case LoongArch::FCMP_SLE_D: |
| 2236 | case LoongArch::FCMP_SLE_S: |
| 2237 | case LoongArch::FCMP_SLT_D: |
| 2238 | case LoongArch::FCMP_SLT_S: |
| 2239 | case LoongArch::FCMP_SNE_D: |
| 2240 | case LoongArch::FCMP_SNE_S: |
| 2241 | case LoongArch::FCMP_SOR_D: |
| 2242 | case LoongArch::FCMP_SOR_S: |
| 2243 | case LoongArch::FCMP_SUEQ_D: |
| 2244 | case LoongArch::FCMP_SUEQ_S: |
| 2245 | case LoongArch::FCMP_SULE_D: |
| 2246 | case LoongArch::FCMP_SULE_S: |
| 2247 | case LoongArch::FCMP_SULT_D: |
| 2248 | case LoongArch::FCMP_SULT_S: |
| 2249 | case LoongArch::FCMP_SUNE_D: |
| 2250 | case LoongArch::FCMP_SUNE_S: |
| 2251 | case LoongArch::FCMP_SUN_D: |
| 2252 | case LoongArch::FCMP_SUN_S: { |
| 2253 | // op: fk |
| 2254 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2255 | Value |= (op & 0x1f) << 10; |
| 2256 | // op: fj |
| 2257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2258 | Value |= (op & 0x1f) << 5; |
| 2259 | // op: cd |
| 2260 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2261 | Value |= (op & 0x7); |
| 2262 | break; |
| 2263 | } |
| 2264 | case LoongArch::FADD_D: |
| 2265 | case LoongArch::FADD_S: |
| 2266 | case LoongArch::FCOPYSIGN_D: |
| 2267 | case LoongArch::FCOPYSIGN_S: |
| 2268 | case LoongArch::FCVT_D_LD: |
| 2269 | case LoongArch::FDIV_D: |
| 2270 | case LoongArch::FDIV_S: |
| 2271 | case LoongArch::FMAXA_D: |
| 2272 | case LoongArch::FMAXA_S: |
| 2273 | case LoongArch::FMAX_D: |
| 2274 | case LoongArch::FMAX_S: |
| 2275 | case LoongArch::FMINA_D: |
| 2276 | case LoongArch::FMINA_S: |
| 2277 | case LoongArch::FMIN_D: |
| 2278 | case LoongArch::FMIN_S: |
| 2279 | case LoongArch::FMUL_D: |
| 2280 | case LoongArch::FMUL_S: |
| 2281 | case LoongArch::FSCALEB_D: |
| 2282 | case LoongArch::FSCALEB_S: |
| 2283 | case LoongArch::FSUB_D: |
| 2284 | case LoongArch::FSUB_S: { |
| 2285 | // op: fk |
| 2286 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2287 | Value |= (op & 0x1f) << 10; |
| 2288 | // op: fj |
| 2289 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2290 | Value |= (op & 0x1f) << 5; |
| 2291 | // op: fd |
| 2292 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2293 | Value |= (op & 0x1f); |
| 2294 | break; |
| 2295 | } |
| 2296 | case LoongArch::VPICKVE2GR_D: |
| 2297 | case LoongArch::VPICKVE2GR_DU: { |
| 2298 | // op: imm1 |
| 2299 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2300 | Value |= (op & 0x1) << 10; |
| 2301 | // op: vj |
| 2302 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2303 | Value |= (op & 0x1f) << 5; |
| 2304 | // op: rd |
| 2305 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2306 | Value |= (op & 0x1f); |
| 2307 | break; |
| 2308 | } |
| 2309 | case LoongArch::VREPLVEI_D: { |
| 2310 | // op: imm1 |
| 2311 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2312 | Value |= (op & 0x1) << 10; |
| 2313 | // op: vj |
| 2314 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2315 | Value |= (op & 0x1f) << 5; |
| 2316 | // op: vd |
| 2317 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2318 | Value |= (op & 0x1f); |
| 2319 | break; |
| 2320 | } |
| 2321 | case LoongArch::XVREPL128VEI_D: { |
| 2322 | // op: imm1 |
| 2323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2324 | Value |= (op & 0x1) << 10; |
| 2325 | // op: xj |
| 2326 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2327 | Value |= (op & 0x1f) << 5; |
| 2328 | // op: xd |
| 2329 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2330 | Value |= (op & 0x1f); |
| 2331 | break; |
| 2332 | } |
| 2333 | case LoongArch::VINSGR2VR_D: { |
| 2334 | // op: imm1 |
| 2335 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2336 | Value |= (op & 0x1) << 10; |
| 2337 | // op: rj |
| 2338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2339 | Value |= (op & 0x1f) << 5; |
| 2340 | // op: vd |
| 2341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2342 | Value |= (op & 0x1f); |
| 2343 | break; |
| 2344 | } |
| 2345 | case LoongArch::VSTELM_D: { |
| 2346 | // op: imm1 |
| 2347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2348 | Value |= (op & 0x1) << 18; |
| 2349 | // op: imm8 |
| 2350 | op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI); |
| 2351 | Value |= (op & 0xff) << 10; |
| 2352 | // op: rj |
| 2353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2354 | Value |= (op & 0x1f) << 5; |
| 2355 | // op: vd |
| 2356 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2357 | Value |= (op & 0x1f); |
| 2358 | break; |
| 2359 | } |
| 2360 | case LoongArch::VLDREPL_W: { |
| 2361 | // op: imm10 |
| 2362 | op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI); |
| 2363 | Value |= (op & 0x3ff) << 10; |
| 2364 | // op: rj |
| 2365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2366 | Value |= (op & 0x1f) << 5; |
| 2367 | // op: vd |
| 2368 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2369 | Value |= (op & 0x1f); |
| 2370 | break; |
| 2371 | } |
| 2372 | case LoongArch::XVLDREPL_W: { |
| 2373 | // op: imm10 |
| 2374 | op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI); |
| 2375 | Value |= (op & 0x3ff) << 10; |
| 2376 | // op: rj |
| 2377 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2378 | Value |= (op & 0x1f) << 5; |
| 2379 | // op: xd |
| 2380 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2381 | Value |= (op & 0x1f); |
| 2382 | break; |
| 2383 | } |
| 2384 | case LoongArch::VLDREPL_H: { |
| 2385 | // op: imm11 |
| 2386 | op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI); |
| 2387 | Value |= (op & 0x7ff) << 10; |
| 2388 | // op: rj |
| 2389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2390 | Value |= (op & 0x1f) << 5; |
| 2391 | // op: vd |
| 2392 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2393 | Value |= (op & 0x1f); |
| 2394 | break; |
| 2395 | } |
| 2396 | case LoongArch::XVLDREPL_H: { |
| 2397 | // op: imm11 |
| 2398 | op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI); |
| 2399 | Value |= (op & 0x7ff) << 10; |
| 2400 | // op: rj |
| 2401 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2402 | Value |= (op & 0x1f) << 5; |
| 2403 | // op: xd |
| 2404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2405 | Value |= (op & 0x1f); |
| 2406 | break; |
| 2407 | } |
| 2408 | case LoongArch::FLD_D: |
| 2409 | case LoongArch::FLD_S: |
| 2410 | case LoongArch::FST_D: |
| 2411 | case LoongArch::FST_S: { |
| 2412 | // op: imm12 |
| 2413 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2414 | Value |= (op & 0xfff) << 10; |
| 2415 | // op: rj |
| 2416 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2417 | Value |= (op & 0x1f) << 5; |
| 2418 | // op: fd |
| 2419 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2420 | Value |= (op & 0x1f); |
| 2421 | break; |
| 2422 | } |
| 2423 | case LoongArch::PRELD: { |
| 2424 | // op: imm12 |
| 2425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2426 | Value |= (op & 0xfff) << 10; |
| 2427 | // op: rj |
| 2428 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2429 | Value |= (op & 0x1f) << 5; |
| 2430 | // op: imm5 |
| 2431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2432 | Value |= (op & 0x1f); |
| 2433 | break; |
| 2434 | } |
| 2435 | case LoongArch::CACOP: { |
| 2436 | // op: imm12 |
| 2437 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2438 | Value |= (op & 0xfff) << 10; |
| 2439 | // op: rj |
| 2440 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2441 | Value |= (op & 0x1f) << 5; |
| 2442 | // op: op |
| 2443 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2444 | Value |= (op & 0x1f); |
| 2445 | break; |
| 2446 | } |
| 2447 | case LoongArch::ADDI_D: |
| 2448 | case LoongArch::ADDI_W: |
| 2449 | case LoongArch::ANDI: |
| 2450 | case LoongArch::LDL_D: |
| 2451 | case LoongArch::LDL_W: |
| 2452 | case LoongArch::LDR_D: |
| 2453 | case LoongArch::LDR_W: |
| 2454 | case LoongArch::LD_B: |
| 2455 | case LoongArch::LD_BU: |
| 2456 | case LoongArch::LD_D: |
| 2457 | case LoongArch::LD_H: |
| 2458 | case LoongArch::LD_HU: |
| 2459 | case LoongArch::LD_W: |
| 2460 | case LoongArch::LD_WU: |
| 2461 | case LoongArch::LU52I_D: |
| 2462 | case LoongArch::ORI: |
| 2463 | case LoongArch::SLTI: |
| 2464 | case LoongArch::SLTUI: |
| 2465 | case LoongArch::STL_D: |
| 2466 | case LoongArch::STL_W: |
| 2467 | case LoongArch::STR_D: |
| 2468 | case LoongArch::STR_W: |
| 2469 | case LoongArch::ST_B: |
| 2470 | case LoongArch::ST_D: |
| 2471 | case LoongArch::ST_H: |
| 2472 | case LoongArch::ST_W: |
| 2473 | case LoongArch::XORI: { |
| 2474 | // op: imm12 |
| 2475 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2476 | Value |= (op & 0xfff) << 10; |
| 2477 | // op: rj |
| 2478 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2479 | Value |= (op & 0x1f) << 5; |
| 2480 | // op: rd |
| 2481 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2482 | Value |= (op & 0x1f); |
| 2483 | break; |
| 2484 | } |
| 2485 | case LoongArch::VLD: |
| 2486 | case LoongArch::VLDREPL_B: |
| 2487 | case LoongArch::VST: { |
| 2488 | // op: imm12 |
| 2489 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2490 | Value |= (op & 0xfff) << 10; |
| 2491 | // op: rj |
| 2492 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2493 | Value |= (op & 0x1f) << 5; |
| 2494 | // op: vd |
| 2495 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2496 | Value |= (op & 0x1f); |
| 2497 | break; |
| 2498 | } |
| 2499 | case LoongArch::XVLD: |
| 2500 | case LoongArch::XVLDREPL_B: |
| 2501 | case LoongArch::XVST: { |
| 2502 | // op: imm12 |
| 2503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2504 | Value |= (op & 0xfff) << 10; |
| 2505 | // op: rj |
| 2506 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2507 | Value |= (op & 0x1f) << 5; |
| 2508 | // op: xd |
| 2509 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2510 | Value |= (op & 0x1f); |
| 2511 | break; |
| 2512 | } |
| 2513 | case LoongArch::VLDI: { |
| 2514 | // op: imm13 |
| 2515 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2516 | Value |= (op & 0x1fff) << 5; |
| 2517 | // op: vd |
| 2518 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2519 | Value |= (op & 0x1f); |
| 2520 | break; |
| 2521 | } |
| 2522 | case LoongArch::XVLDI: { |
| 2523 | // op: imm13 |
| 2524 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2525 | Value |= (op & 0x1fff) << 5; |
| 2526 | // op: xd |
| 2527 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2528 | Value |= (op & 0x1f); |
| 2529 | break; |
| 2530 | } |
| 2531 | case LoongArch::LDPTR_D: |
| 2532 | case LoongArch::LDPTR_W: |
| 2533 | case LoongArch::LL_D: |
| 2534 | case LoongArch::LL_W: |
| 2535 | case LoongArch::STPTR_D: |
| 2536 | case LoongArch::STPTR_W: { |
| 2537 | // op: imm14 |
| 2538 | op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI); |
| 2539 | Value |= (op & 0x3fff) << 10; |
| 2540 | // op: rj |
| 2541 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2542 | Value |= (op & 0x1f) << 5; |
| 2543 | // op: rd |
| 2544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2545 | Value |= (op & 0x1f); |
| 2546 | break; |
| 2547 | } |
| 2548 | case LoongArch::SC_D: |
| 2549 | case LoongArch::SC_W: { |
| 2550 | // op: imm14 |
| 2551 | op = getImmOpValueAsr<2>(MI, OpNo: 3, Fixups, STI); |
| 2552 | Value |= (op & 0x3fff) << 10; |
| 2553 | // op: rj |
| 2554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2555 | Value |= (op & 0x1f) << 5; |
| 2556 | // op: rd |
| 2557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2558 | Value |= (op & 0x1f); |
| 2559 | break; |
| 2560 | } |
| 2561 | case LoongArch::BREAK: |
| 2562 | case LoongArch::DBAR: |
| 2563 | case LoongArch::DBCL: |
| 2564 | case LoongArch::HVCL: |
| 2565 | case LoongArch::IBAR: |
| 2566 | case LoongArch::IDLE: |
| 2567 | case LoongArch::SYSCALL: { |
| 2568 | // op: imm15 |
| 2569 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2570 | Value |= (op & 0x7fff); |
| 2571 | break; |
| 2572 | } |
| 2573 | case LoongArch::BEQ: |
| 2574 | case LoongArch::BGE: |
| 2575 | case LoongArch::BGEU: |
| 2576 | case LoongArch::BLT: |
| 2577 | case LoongArch::BLTU: |
| 2578 | case LoongArch::BNE: { |
| 2579 | // op: imm16 |
| 2580 | op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI); |
| 2581 | Value |= (op & 0xffff) << 10; |
| 2582 | // op: rj |
| 2583 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2584 | Value |= (op & 0x1f) << 5; |
| 2585 | // op: rd |
| 2586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2587 | Value |= (op & 0x1f); |
| 2588 | break; |
| 2589 | } |
| 2590 | case LoongArch::JIRL: { |
| 2591 | // op: imm16 |
| 2592 | op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI); |
| 2593 | Value |= (op & 0xffff) << 10; |
| 2594 | // op: rj |
| 2595 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2596 | Value |= (op & 0x1f) << 5; |
| 2597 | // op: rd |
| 2598 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2599 | Value |= (op & 0x1f); |
| 2600 | break; |
| 2601 | } |
| 2602 | case LoongArch::ADDU16I_D: { |
| 2603 | // op: imm16 |
| 2604 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2605 | Value |= (op & 0xffff) << 10; |
| 2606 | // op: rj |
| 2607 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2608 | Value |= (op & 0x1f) << 5; |
| 2609 | // op: rd |
| 2610 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2611 | Value |= (op & 0x1f); |
| 2612 | break; |
| 2613 | } |
| 2614 | case LoongArch::ALSL_D: |
| 2615 | case LoongArch::ALSL_W: |
| 2616 | case LoongArch::ALSL_WU: { |
| 2617 | // op: imm2 |
| 2618 | op = getImmOpValueSub1(MI, OpNo: 3, Fixups, STI); |
| 2619 | Value |= (op & 0x3) << 15; |
| 2620 | // op: rk |
| 2621 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2622 | Value |= (op & 0x1f) << 10; |
| 2623 | // op: rj |
| 2624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2625 | Value |= (op & 0x1f) << 5; |
| 2626 | // op: rd |
| 2627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2628 | Value |= (op & 0x1f); |
| 2629 | break; |
| 2630 | } |
| 2631 | case LoongArch::VPICKVE2GR_W: |
| 2632 | case LoongArch::VPICKVE2GR_WU: { |
| 2633 | // op: imm2 |
| 2634 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2635 | Value |= (op & 0x3) << 10; |
| 2636 | // op: vj |
| 2637 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2638 | Value |= (op & 0x1f) << 5; |
| 2639 | // op: rd |
| 2640 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2641 | Value |= (op & 0x1f); |
| 2642 | break; |
| 2643 | } |
| 2644 | case LoongArch::VREPLVEI_W: { |
| 2645 | // op: imm2 |
| 2646 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2647 | Value |= (op & 0x3) << 10; |
| 2648 | // op: vj |
| 2649 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2650 | Value |= (op & 0x1f) << 5; |
| 2651 | // op: vd |
| 2652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2653 | Value |= (op & 0x1f); |
| 2654 | break; |
| 2655 | } |
| 2656 | case LoongArch::XVPICKVE2GR_D: |
| 2657 | case LoongArch::XVPICKVE2GR_DU: { |
| 2658 | // op: imm2 |
| 2659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2660 | Value |= (op & 0x3) << 10; |
| 2661 | // op: xj |
| 2662 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2663 | Value |= (op & 0x1f) << 5; |
| 2664 | // op: rd |
| 2665 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2666 | Value |= (op & 0x1f); |
| 2667 | break; |
| 2668 | } |
| 2669 | case LoongArch::XVPICKVE_D: |
| 2670 | case LoongArch::XVREPL128VEI_W: { |
| 2671 | // op: imm2 |
| 2672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2673 | Value |= (op & 0x3) << 10; |
| 2674 | // op: xj |
| 2675 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2676 | Value |= (op & 0x1f) << 5; |
| 2677 | // op: xd |
| 2678 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2679 | Value |= (op & 0x1f); |
| 2680 | break; |
| 2681 | } |
| 2682 | case LoongArch::VINSGR2VR_W: { |
| 2683 | // op: imm2 |
| 2684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2685 | Value |= (op & 0x3) << 10; |
| 2686 | // op: rj |
| 2687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2688 | Value |= (op & 0x1f) << 5; |
| 2689 | // op: vd |
| 2690 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2691 | Value |= (op & 0x1f); |
| 2692 | break; |
| 2693 | } |
| 2694 | case LoongArch::XVINSGR2VR_D: { |
| 2695 | // op: imm2 |
| 2696 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2697 | Value |= (op & 0x3) << 10; |
| 2698 | // op: rj |
| 2699 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2700 | Value |= (op & 0x1f) << 5; |
| 2701 | // op: xd |
| 2702 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2703 | Value |= (op & 0x1f); |
| 2704 | break; |
| 2705 | } |
| 2706 | case LoongArch::XVINSVE0_D: { |
| 2707 | // op: imm2 |
| 2708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2709 | Value |= (op & 0x3) << 10; |
| 2710 | // op: xj |
| 2711 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2712 | Value |= (op & 0x1f) << 5; |
| 2713 | // op: xd |
| 2714 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2715 | Value |= (op & 0x1f); |
| 2716 | break; |
| 2717 | } |
| 2718 | case LoongArch::BYTEPICK_W: { |
| 2719 | // op: imm2 |
| 2720 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2721 | Value |= (op & 0x3) << 15; |
| 2722 | // op: rk |
| 2723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2724 | Value |= (op & 0x1f) << 10; |
| 2725 | // op: rj |
| 2726 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2727 | Value |= (op & 0x1f) << 5; |
| 2728 | // op: rd |
| 2729 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2730 | Value |= (op & 0x1f); |
| 2731 | break; |
| 2732 | } |
| 2733 | case LoongArch::VSTELM_W: { |
| 2734 | // op: imm2 |
| 2735 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2736 | Value |= (op & 0x3) << 18; |
| 2737 | // op: imm8 |
| 2738 | op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI); |
| 2739 | Value |= (op & 0xff) << 10; |
| 2740 | // op: rj |
| 2741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2742 | Value |= (op & 0x1f) << 5; |
| 2743 | // op: vd |
| 2744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2745 | Value |= (op & 0x1f); |
| 2746 | break; |
| 2747 | } |
| 2748 | case LoongArch::XVSTELM_D: { |
| 2749 | // op: imm2 |
| 2750 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2751 | Value |= (op & 0x3) << 18; |
| 2752 | // op: imm8 |
| 2753 | op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI); |
| 2754 | Value |= (op & 0xff) << 10; |
| 2755 | // op: rj |
| 2756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2757 | Value |= (op & 0x1f) << 5; |
| 2758 | // op: xd |
| 2759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2760 | Value |= (op & 0x1f); |
| 2761 | break; |
| 2762 | } |
| 2763 | case LoongArch::LU12I_W: |
| 2764 | case LoongArch::PCADDI: |
| 2765 | case LoongArch::PCADDU12I: |
| 2766 | case LoongArch::PCADDU18I: |
| 2767 | case LoongArch::PCALAU12I: { |
| 2768 | // op: imm20 |
| 2769 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2770 | Value |= (op & 0xfffff) << 5; |
| 2771 | // op: rd |
| 2772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2773 | Value |= (op & 0x1f); |
| 2774 | break; |
| 2775 | } |
| 2776 | case LoongArch::LU32I_D: { |
| 2777 | // op: imm20 |
| 2778 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2779 | Value |= (op & 0xfffff) << 5; |
| 2780 | // op: rd |
| 2781 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2782 | Value |= (op & 0x1f); |
| 2783 | break; |
| 2784 | } |
| 2785 | case LoongArch::JISCR0: |
| 2786 | case LoongArch::JISCR1: { |
| 2787 | // op: imm21 |
| 2788 | op = getImmOpValueAsr<2>(MI, OpNo: 0, Fixups, STI); |
| 2789 | Value |= (op & 0xffff) << 10; |
| 2790 | Value |= (op & 0x1f0000) >> 16; |
| 2791 | break; |
| 2792 | } |
| 2793 | case LoongArch::BCEQZ: |
| 2794 | case LoongArch::BCNEZ: { |
| 2795 | // op: imm21 |
| 2796 | op = getImmOpValueAsr<2>(MI, OpNo: 1, Fixups, STI); |
| 2797 | Value |= (op & 0xffff) << 10; |
| 2798 | Value |= (op & 0x1f0000) >> 16; |
| 2799 | // op: cj |
| 2800 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2801 | Value |= (op & 0x7) << 5; |
| 2802 | break; |
| 2803 | } |
| 2804 | case LoongArch::BEQZ: |
| 2805 | case LoongArch::BNEZ: { |
| 2806 | // op: imm21 |
| 2807 | op = getImmOpValueAsr<2>(MI, OpNo: 1, Fixups, STI); |
| 2808 | Value |= (op & 0xffff) << 10; |
| 2809 | Value |= (op & 0x1f0000) >> 16; |
| 2810 | // op: rj |
| 2811 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2812 | Value |= (op & 0x1f) << 5; |
| 2813 | break; |
| 2814 | } |
| 2815 | case LoongArch::B: |
| 2816 | case LoongArch::BL: { |
| 2817 | // op: imm26 |
| 2818 | op = getImmOpValueAsr<2>(MI, OpNo: 0, Fixups, STI); |
| 2819 | Value |= (op & 0xffff) << 10; |
| 2820 | Value |= (op & 0x3ff0000) >> 16; |
| 2821 | break; |
| 2822 | } |
| 2823 | case LoongArch::X86RCLI_B: |
| 2824 | case LoongArch::X86RCRI_B: |
| 2825 | case LoongArch::X86ROTLI_B: |
| 2826 | case LoongArch::X86ROTRI_B: |
| 2827 | case LoongArch::X86SLLI_B: |
| 2828 | case LoongArch::X86SRAI_B: |
| 2829 | case LoongArch::X86SRLI_B: { |
| 2830 | // op: imm3 |
| 2831 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2832 | Value |= (op & 0x7) << 10; |
| 2833 | // op: rj |
| 2834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2835 | Value |= (op & 0x1f) << 5; |
| 2836 | break; |
| 2837 | } |
| 2838 | case LoongArch::RCRI_B: |
| 2839 | case LoongArch::ROTRI_B: { |
| 2840 | // op: imm3 |
| 2841 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2842 | Value |= (op & 0x7) << 10; |
| 2843 | // op: rj |
| 2844 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2845 | Value |= (op & 0x1f) << 5; |
| 2846 | // op: rd |
| 2847 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2848 | Value |= (op & 0x1f); |
| 2849 | break; |
| 2850 | } |
| 2851 | case LoongArch::VPICKVE2GR_H: |
| 2852 | case LoongArch::VPICKVE2GR_HU: { |
| 2853 | // op: imm3 |
| 2854 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2855 | Value |= (op & 0x7) << 10; |
| 2856 | // op: vj |
| 2857 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2858 | Value |= (op & 0x1f) << 5; |
| 2859 | // op: rd |
| 2860 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2861 | Value |= (op & 0x1f); |
| 2862 | break; |
| 2863 | } |
| 2864 | case LoongArch::VBITCLRI_B: |
| 2865 | case LoongArch::VBITREVI_B: |
| 2866 | case LoongArch::VBITSETI_B: |
| 2867 | case LoongArch::VREPLVEI_H: |
| 2868 | case LoongArch::VROTRI_B: |
| 2869 | case LoongArch::VSAT_B: |
| 2870 | case LoongArch::VSAT_BU: |
| 2871 | case LoongArch::VSLLI_B: |
| 2872 | case LoongArch::VSLLWIL_HU_BU: |
| 2873 | case LoongArch::VSLLWIL_H_B: |
| 2874 | case LoongArch::VSRAI_B: |
| 2875 | case LoongArch::VSRARI_B: |
| 2876 | case LoongArch::VSRLI_B: |
| 2877 | case LoongArch::VSRLRI_B: { |
| 2878 | // op: imm3 |
| 2879 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2880 | Value |= (op & 0x7) << 10; |
| 2881 | // op: vj |
| 2882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2883 | Value |= (op & 0x1f) << 5; |
| 2884 | // op: vd |
| 2885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2886 | Value |= (op & 0x1f); |
| 2887 | break; |
| 2888 | } |
| 2889 | case LoongArch::XVPICKVE2GR_W: |
| 2890 | case LoongArch::XVPICKVE2GR_WU: { |
| 2891 | // op: imm3 |
| 2892 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2893 | Value |= (op & 0x7) << 10; |
| 2894 | // op: xj |
| 2895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2896 | Value |= (op & 0x1f) << 5; |
| 2897 | // op: rd |
| 2898 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2899 | Value |= (op & 0x1f); |
| 2900 | break; |
| 2901 | } |
| 2902 | case LoongArch::XVBITCLRI_B: |
| 2903 | case LoongArch::XVBITREVI_B: |
| 2904 | case LoongArch::XVBITSETI_B: |
| 2905 | case LoongArch::XVPICKVE_W: |
| 2906 | case LoongArch::XVREPL128VEI_H: |
| 2907 | case LoongArch::XVROTRI_B: |
| 2908 | case LoongArch::XVSAT_B: |
| 2909 | case LoongArch::XVSAT_BU: |
| 2910 | case LoongArch::XVSLLI_B: |
| 2911 | case LoongArch::XVSLLWIL_HU_BU: |
| 2912 | case LoongArch::XVSLLWIL_H_B: |
| 2913 | case LoongArch::XVSRAI_B: |
| 2914 | case LoongArch::XVSRARI_B: |
| 2915 | case LoongArch::XVSRLI_B: |
| 2916 | case LoongArch::XVSRLRI_B: { |
| 2917 | // op: imm3 |
| 2918 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2919 | Value |= (op & 0x7) << 10; |
| 2920 | // op: xj |
| 2921 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2922 | Value |= (op & 0x1f) << 5; |
| 2923 | // op: xd |
| 2924 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2925 | Value |= (op & 0x1f); |
| 2926 | break; |
| 2927 | } |
| 2928 | case LoongArch::VINSGR2VR_H: { |
| 2929 | // op: imm3 |
| 2930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2931 | Value |= (op & 0x7) << 10; |
| 2932 | // op: rj |
| 2933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2934 | Value |= (op & 0x1f) << 5; |
| 2935 | // op: vd |
| 2936 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2937 | Value |= (op & 0x1f); |
| 2938 | break; |
| 2939 | } |
| 2940 | case LoongArch::XVINSGR2VR_W: { |
| 2941 | // op: imm3 |
| 2942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2943 | Value |= (op & 0x7) << 10; |
| 2944 | // op: rj |
| 2945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2946 | Value |= (op & 0x1f) << 5; |
| 2947 | // op: xd |
| 2948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2949 | Value |= (op & 0x1f); |
| 2950 | break; |
| 2951 | } |
| 2952 | case LoongArch::XVINSVE0_W: { |
| 2953 | // op: imm3 |
| 2954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2955 | Value |= (op & 0x7) << 10; |
| 2956 | // op: xj |
| 2957 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2958 | Value |= (op & 0x1f) << 5; |
| 2959 | // op: xd |
| 2960 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2961 | Value |= (op & 0x1f); |
| 2962 | break; |
| 2963 | } |
| 2964 | case LoongArch::BYTEPICK_D: { |
| 2965 | // op: imm3 |
| 2966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2967 | Value |= (op & 0x7) << 15; |
| 2968 | // op: rk |
| 2969 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2970 | Value |= (op & 0x1f) << 10; |
| 2971 | // op: rj |
| 2972 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2973 | Value |= (op & 0x1f) << 5; |
| 2974 | // op: rd |
| 2975 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2976 | Value |= (op & 0x1f); |
| 2977 | break; |
| 2978 | } |
| 2979 | case LoongArch::VSTELM_H: { |
| 2980 | // op: imm3 |
| 2981 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2982 | Value |= (op & 0x7) << 18; |
| 2983 | // op: imm8 |
| 2984 | op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI); |
| 2985 | Value |= (op & 0xff) << 10; |
| 2986 | // op: rj |
| 2987 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2988 | Value |= (op & 0x1f) << 5; |
| 2989 | // op: vd |
| 2990 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2991 | Value |= (op & 0x1f); |
| 2992 | break; |
| 2993 | } |
| 2994 | case LoongArch::XVSTELM_W: { |
| 2995 | // op: imm3 |
| 2996 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2997 | Value |= (op & 0x7) << 18; |
| 2998 | // op: imm8 |
| 2999 | op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI); |
| 3000 | Value |= (op & 0xff) << 10; |
| 3001 | // op: rj |
| 3002 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3003 | Value |= (op & 0x1f) << 5; |
| 3004 | // op: xd |
| 3005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3006 | Value |= (op & 0x1f); |
| 3007 | break; |
| 3008 | } |
| 3009 | case LoongArch::SETARMJ: |
| 3010 | case LoongArch::SETX86J: { |
| 3011 | // op: imm4 |
| 3012 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3013 | Value |= (op & 0xf) << 10; |
| 3014 | // op: rd |
| 3015 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3016 | Value |= (op & 0x1f); |
| 3017 | break; |
| 3018 | } |
| 3019 | case LoongArch::ARMMOV_D: |
| 3020 | case LoongArch::ARMMOV_W: |
| 3021 | case LoongArch::ARMNOT_W: |
| 3022 | case LoongArch::ARMRRX_W: |
| 3023 | case LoongArch::X86RCLI_H: |
| 3024 | case LoongArch::X86RCRI_H: |
| 3025 | case LoongArch::X86ROTLI_H: |
| 3026 | case LoongArch::X86ROTRI_H: |
| 3027 | case LoongArch::X86SLLI_H: |
| 3028 | case LoongArch::X86SRAI_H: |
| 3029 | case LoongArch::X86SRLI_H: { |
| 3030 | // op: imm4 |
| 3031 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3032 | Value |= (op & 0xf) << 10; |
| 3033 | // op: rj |
| 3034 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3035 | Value |= (op & 0x1f) << 5; |
| 3036 | break; |
| 3037 | } |
| 3038 | case LoongArch::ARMMOVE: |
| 3039 | case LoongArch::RCRI_H: |
| 3040 | case LoongArch::ROTRI_H: { |
| 3041 | // op: imm4 |
| 3042 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3043 | Value |= (op & 0xf) << 10; |
| 3044 | // op: rj |
| 3045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3046 | Value |= (op & 0x1f) << 5; |
| 3047 | // op: rd |
| 3048 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3049 | Value |= (op & 0x1f); |
| 3050 | break; |
| 3051 | } |
| 3052 | case LoongArch::VPICKVE2GR_B: |
| 3053 | case LoongArch::VPICKVE2GR_BU: { |
| 3054 | // op: imm4 |
| 3055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3056 | Value |= (op & 0xf) << 10; |
| 3057 | // op: vj |
| 3058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3059 | Value |= (op & 0x1f) << 5; |
| 3060 | // op: rd |
| 3061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3062 | Value |= (op & 0x1f); |
| 3063 | break; |
| 3064 | } |
| 3065 | case LoongArch::VBITCLRI_H: |
| 3066 | case LoongArch::VBITREVI_H: |
| 3067 | case LoongArch::VBITSETI_H: |
| 3068 | case LoongArch::VREPLVEI_B: |
| 3069 | case LoongArch::VROTRI_H: |
| 3070 | case LoongArch::VSAT_H: |
| 3071 | case LoongArch::VSAT_HU: |
| 3072 | case LoongArch::VSLLI_H: |
| 3073 | case LoongArch::VSLLWIL_WU_HU: |
| 3074 | case LoongArch::VSLLWIL_W_H: |
| 3075 | case LoongArch::VSRAI_H: |
| 3076 | case LoongArch::VSRARI_H: |
| 3077 | case LoongArch::VSRLI_H: |
| 3078 | case LoongArch::VSRLRI_H: { |
| 3079 | // op: imm4 |
| 3080 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3081 | Value |= (op & 0xf) << 10; |
| 3082 | // op: vj |
| 3083 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3084 | Value |= (op & 0x1f) << 5; |
| 3085 | // op: vd |
| 3086 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3087 | Value |= (op & 0x1f); |
| 3088 | break; |
| 3089 | } |
| 3090 | case LoongArch::XVBITCLRI_H: |
| 3091 | case LoongArch::XVBITREVI_H: |
| 3092 | case LoongArch::XVBITSETI_H: |
| 3093 | case LoongArch::XVREPL128VEI_B: |
| 3094 | case LoongArch::XVROTRI_H: |
| 3095 | case LoongArch::XVSAT_H: |
| 3096 | case LoongArch::XVSAT_HU: |
| 3097 | case LoongArch::XVSLLI_H: |
| 3098 | case LoongArch::XVSLLWIL_WU_HU: |
| 3099 | case LoongArch::XVSLLWIL_W_H: |
| 3100 | case LoongArch::XVSRAI_H: |
| 3101 | case LoongArch::XVSRARI_H: |
| 3102 | case LoongArch::XVSRLI_H: |
| 3103 | case LoongArch::XVSRLRI_H: { |
| 3104 | // op: imm4 |
| 3105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3106 | Value |= (op & 0xf) << 10; |
| 3107 | // op: xj |
| 3108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3109 | Value |= (op & 0x1f) << 5; |
| 3110 | // op: xd |
| 3111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3112 | Value |= (op & 0x1f); |
| 3113 | break; |
| 3114 | } |
| 3115 | case LoongArch::ARMADC_W: |
| 3116 | case LoongArch::ARMADD_W: |
| 3117 | case LoongArch::ARMAND_W: |
| 3118 | case LoongArch::ARMOR_W: |
| 3119 | case LoongArch::ARMROTR_W: |
| 3120 | case LoongArch::ARMSBC_W: |
| 3121 | case LoongArch::ARMSLL_W: |
| 3122 | case LoongArch::ARMSRA_W: |
| 3123 | case LoongArch::ARMSRL_W: |
| 3124 | case LoongArch::ARMSUB_W: |
| 3125 | case LoongArch::ARMXOR_W: { |
| 3126 | // op: imm4 |
| 3127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3128 | Value |= (op & 0xf); |
| 3129 | // op: rk |
| 3130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3131 | Value |= (op & 0x1f) << 10; |
| 3132 | // op: rj |
| 3133 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3134 | Value |= (op & 0x1f) << 5; |
| 3135 | break; |
| 3136 | } |
| 3137 | case LoongArch::VINSGR2VR_B: { |
| 3138 | // op: imm4 |
| 3139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3140 | Value |= (op & 0xf) << 10; |
| 3141 | // op: rj |
| 3142 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3143 | Value |= (op & 0x1f) << 5; |
| 3144 | // op: vd |
| 3145 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3146 | Value |= (op & 0x1f); |
| 3147 | break; |
| 3148 | } |
| 3149 | case LoongArch::VSRANI_B_H: |
| 3150 | case LoongArch::VSRARNI_B_H: |
| 3151 | case LoongArch::VSRLNI_B_H: |
| 3152 | case LoongArch::VSRLRNI_B_H: |
| 3153 | case LoongArch::VSSRANI_BU_H: |
| 3154 | case LoongArch::VSSRANI_B_H: |
| 3155 | case LoongArch::VSSRARNI_BU_H: |
| 3156 | case LoongArch::VSSRARNI_B_H: |
| 3157 | case LoongArch::VSSRLNI_BU_H: |
| 3158 | case LoongArch::VSSRLNI_B_H: |
| 3159 | case LoongArch::VSSRLRNI_BU_H: |
| 3160 | case LoongArch::VSSRLRNI_B_H: { |
| 3161 | // op: imm4 |
| 3162 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3163 | Value |= (op & 0xf) << 10; |
| 3164 | // op: vj |
| 3165 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3166 | Value |= (op & 0x1f) << 5; |
| 3167 | // op: vd |
| 3168 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3169 | Value |= (op & 0x1f); |
| 3170 | break; |
| 3171 | } |
| 3172 | case LoongArch::XVSRANI_B_H: |
| 3173 | case LoongArch::XVSRARNI_B_H: |
| 3174 | case LoongArch::XVSRLNI_B_H: |
| 3175 | case LoongArch::XVSRLRNI_B_H: |
| 3176 | case LoongArch::XVSSRANI_BU_H: |
| 3177 | case LoongArch::XVSSRANI_B_H: |
| 3178 | case LoongArch::XVSSRARNI_BU_H: |
| 3179 | case LoongArch::XVSSRARNI_B_H: |
| 3180 | case LoongArch::XVSSRLNI_BU_H: |
| 3181 | case LoongArch::XVSSRLNI_B_H: |
| 3182 | case LoongArch::XVSSRLRNI_BU_H: |
| 3183 | case LoongArch::XVSSRLRNI_B_H: { |
| 3184 | // op: imm4 |
| 3185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3186 | Value |= (op & 0xf) << 10; |
| 3187 | // op: xj |
| 3188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3189 | Value |= (op & 0x1f) << 5; |
| 3190 | // op: xd |
| 3191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3192 | Value |= (op & 0x1f); |
| 3193 | break; |
| 3194 | } |
| 3195 | case LoongArch::XVSTELM_H: { |
| 3196 | // op: imm4 |
| 3197 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3198 | Value |= (op & 0xf) << 18; |
| 3199 | // op: imm8 |
| 3200 | op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI); |
| 3201 | Value |= (op & 0xff) << 10; |
| 3202 | // op: rj |
| 3203 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3204 | Value |= (op & 0x1f) << 5; |
| 3205 | // op: xd |
| 3206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3207 | Value |= (op & 0x1f); |
| 3208 | break; |
| 3209 | } |
| 3210 | case LoongArch::VSTELM_B: { |
| 3211 | // op: imm4 |
| 3212 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3213 | Value |= (op & 0xf) << 18; |
| 3214 | // op: imm8 |
| 3215 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3216 | Value |= (op & 0xff) << 10; |
| 3217 | // op: rj |
| 3218 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3219 | Value |= (op & 0x1f) << 5; |
| 3220 | // op: vd |
| 3221 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3222 | Value |= (op & 0x1f); |
| 3223 | break; |
| 3224 | } |
| 3225 | case LoongArch::UD: { |
| 3226 | // op: imm5 |
| 3227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3228 | Value |= (op & 0x1f) << 5; |
| 3229 | Value |= (op & 0x1f); |
| 3230 | break; |
| 3231 | } |
| 3232 | case LoongArch::X86RCLI_W: |
| 3233 | case LoongArch::X86RCRI_W: |
| 3234 | case LoongArch::X86ROTLI_W: |
| 3235 | case LoongArch::X86ROTRI_W: |
| 3236 | case LoongArch::X86SLLI_W: |
| 3237 | case LoongArch::X86SRAI_W: |
| 3238 | case LoongArch::X86SRLI_W: { |
| 3239 | // op: imm5 |
| 3240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3241 | Value |= (op & 0x1f) << 10; |
| 3242 | // op: rj |
| 3243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3244 | Value |= (op & 0x1f) << 5; |
| 3245 | break; |
| 3246 | } |
| 3247 | case LoongArch::ARMROTRI_W: |
| 3248 | case LoongArch::ARMSLLI_W: |
| 3249 | case LoongArch::ARMSRAI_W: |
| 3250 | case LoongArch::ARMSRLI_W: { |
| 3251 | // op: imm5 |
| 3252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3253 | Value |= (op & 0x1f) << 10; |
| 3254 | // op: rj |
| 3255 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3256 | Value |= (op & 0x1f) << 5; |
| 3257 | // op: imm4 |
| 3258 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3259 | Value |= (op & 0xf); |
| 3260 | break; |
| 3261 | } |
| 3262 | case LoongArch::ADDU12I_D: |
| 3263 | case LoongArch::ADDU12I_W: |
| 3264 | case LoongArch::RCRI_W: |
| 3265 | case LoongArch::ROTRI_W: |
| 3266 | case LoongArch::SLLI_W: |
| 3267 | case LoongArch::SRAI_W: |
| 3268 | case LoongArch::SRLI_W: { |
| 3269 | // op: imm5 |
| 3270 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3271 | Value |= (op & 0x1f) << 10; |
| 3272 | // op: rj |
| 3273 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3274 | Value |= (op & 0x1f) << 5; |
| 3275 | // op: rd |
| 3276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3277 | Value |= (op & 0x1f); |
| 3278 | break; |
| 3279 | } |
| 3280 | case LoongArch::VADDI_BU: |
| 3281 | case LoongArch::VADDI_DU: |
| 3282 | case LoongArch::VADDI_HU: |
| 3283 | case LoongArch::VADDI_WU: |
| 3284 | case LoongArch::VBITCLRI_W: |
| 3285 | case LoongArch::VBITREVI_W: |
| 3286 | case LoongArch::VBITSETI_W: |
| 3287 | case LoongArch::VBSLL_V: |
| 3288 | case LoongArch::VBSRL_V: |
| 3289 | case LoongArch::VMAXI_B: |
| 3290 | case LoongArch::VMAXI_BU: |
| 3291 | case LoongArch::VMAXI_D: |
| 3292 | case LoongArch::VMAXI_DU: |
| 3293 | case LoongArch::VMAXI_H: |
| 3294 | case LoongArch::VMAXI_HU: |
| 3295 | case LoongArch::VMAXI_W: |
| 3296 | case LoongArch::VMAXI_WU: |
| 3297 | case LoongArch::VMINI_B: |
| 3298 | case LoongArch::VMINI_BU: |
| 3299 | case LoongArch::VMINI_D: |
| 3300 | case LoongArch::VMINI_DU: |
| 3301 | case LoongArch::VMINI_H: |
| 3302 | case LoongArch::VMINI_HU: |
| 3303 | case LoongArch::VMINI_W: |
| 3304 | case LoongArch::VMINI_WU: |
| 3305 | case LoongArch::VROTRI_W: |
| 3306 | case LoongArch::VSAT_W: |
| 3307 | case LoongArch::VSAT_WU: |
| 3308 | case LoongArch::VSEQI_B: |
| 3309 | case LoongArch::VSEQI_D: |
| 3310 | case LoongArch::VSEQI_H: |
| 3311 | case LoongArch::VSEQI_W: |
| 3312 | case LoongArch::VSLEI_B: |
| 3313 | case LoongArch::VSLEI_BU: |
| 3314 | case LoongArch::VSLEI_D: |
| 3315 | case LoongArch::VSLEI_DU: |
| 3316 | case LoongArch::VSLEI_H: |
| 3317 | case LoongArch::VSLEI_HU: |
| 3318 | case LoongArch::VSLEI_W: |
| 3319 | case LoongArch::VSLEI_WU: |
| 3320 | case LoongArch::VSLLI_W: |
| 3321 | case LoongArch::VSLLWIL_DU_WU: |
| 3322 | case LoongArch::VSLLWIL_D_W: |
| 3323 | case LoongArch::VSLTI_B: |
| 3324 | case LoongArch::VSLTI_BU: |
| 3325 | case LoongArch::VSLTI_D: |
| 3326 | case LoongArch::VSLTI_DU: |
| 3327 | case LoongArch::VSLTI_H: |
| 3328 | case LoongArch::VSLTI_HU: |
| 3329 | case LoongArch::VSLTI_W: |
| 3330 | case LoongArch::VSLTI_WU: |
| 3331 | case LoongArch::VSRAI_W: |
| 3332 | case LoongArch::VSRARI_W: |
| 3333 | case LoongArch::VSRLI_W: |
| 3334 | case LoongArch::VSRLRI_W: |
| 3335 | case LoongArch::VSUBI_BU: |
| 3336 | case LoongArch::VSUBI_DU: |
| 3337 | case LoongArch::VSUBI_HU: |
| 3338 | case LoongArch::VSUBI_WU: { |
| 3339 | // op: imm5 |
| 3340 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3341 | Value |= (op & 0x1f) << 10; |
| 3342 | // op: vj |
| 3343 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3344 | Value |= (op & 0x1f) << 5; |
| 3345 | // op: vd |
| 3346 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3347 | Value |= (op & 0x1f); |
| 3348 | break; |
| 3349 | } |
| 3350 | case LoongArch::XVADDI_BU: |
| 3351 | case LoongArch::XVADDI_DU: |
| 3352 | case LoongArch::XVADDI_HU: |
| 3353 | case LoongArch::XVADDI_WU: |
| 3354 | case LoongArch::XVBITCLRI_W: |
| 3355 | case LoongArch::XVBITREVI_W: |
| 3356 | case LoongArch::XVBITSETI_W: |
| 3357 | case LoongArch::XVBSLL_V: |
| 3358 | case LoongArch::XVBSRL_V: |
| 3359 | case LoongArch::XVHSELI_D: |
| 3360 | case LoongArch::XVMAXI_B: |
| 3361 | case LoongArch::XVMAXI_BU: |
| 3362 | case LoongArch::XVMAXI_D: |
| 3363 | case LoongArch::XVMAXI_DU: |
| 3364 | case LoongArch::XVMAXI_H: |
| 3365 | case LoongArch::XVMAXI_HU: |
| 3366 | case LoongArch::XVMAXI_W: |
| 3367 | case LoongArch::XVMAXI_WU: |
| 3368 | case LoongArch::XVMINI_B: |
| 3369 | case LoongArch::XVMINI_BU: |
| 3370 | case LoongArch::XVMINI_D: |
| 3371 | case LoongArch::XVMINI_DU: |
| 3372 | case LoongArch::XVMINI_H: |
| 3373 | case LoongArch::XVMINI_HU: |
| 3374 | case LoongArch::XVMINI_W: |
| 3375 | case LoongArch::XVMINI_WU: |
| 3376 | case LoongArch::XVROTRI_W: |
| 3377 | case LoongArch::XVSAT_W: |
| 3378 | case LoongArch::XVSAT_WU: |
| 3379 | case LoongArch::XVSEQI_B: |
| 3380 | case LoongArch::XVSEQI_D: |
| 3381 | case LoongArch::XVSEQI_H: |
| 3382 | case LoongArch::XVSEQI_W: |
| 3383 | case LoongArch::XVSLEI_B: |
| 3384 | case LoongArch::XVSLEI_BU: |
| 3385 | case LoongArch::XVSLEI_D: |
| 3386 | case LoongArch::XVSLEI_DU: |
| 3387 | case LoongArch::XVSLEI_H: |
| 3388 | case LoongArch::XVSLEI_HU: |
| 3389 | case LoongArch::XVSLEI_W: |
| 3390 | case LoongArch::XVSLEI_WU: |
| 3391 | case LoongArch::XVSLLI_W: |
| 3392 | case LoongArch::XVSLLWIL_DU_WU: |
| 3393 | case LoongArch::XVSLLWIL_D_W: |
| 3394 | case LoongArch::XVSLTI_B: |
| 3395 | case LoongArch::XVSLTI_BU: |
| 3396 | case LoongArch::XVSLTI_D: |
| 3397 | case LoongArch::XVSLTI_DU: |
| 3398 | case LoongArch::XVSLTI_H: |
| 3399 | case LoongArch::XVSLTI_HU: |
| 3400 | case LoongArch::XVSLTI_W: |
| 3401 | case LoongArch::XVSLTI_WU: |
| 3402 | case LoongArch::XVSRAI_W: |
| 3403 | case LoongArch::XVSRARI_W: |
| 3404 | case LoongArch::XVSRLI_W: |
| 3405 | case LoongArch::XVSRLRI_W: |
| 3406 | case LoongArch::XVSUBI_BU: |
| 3407 | case LoongArch::XVSUBI_DU: |
| 3408 | case LoongArch::XVSUBI_HU: |
| 3409 | case LoongArch::XVSUBI_WU: { |
| 3410 | // op: imm5 |
| 3411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3412 | Value |= (op & 0x1f) << 10; |
| 3413 | // op: xj |
| 3414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3415 | Value |= (op & 0x1f) << 5; |
| 3416 | // op: xd |
| 3417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3418 | Value |= (op & 0x1f); |
| 3419 | break; |
| 3420 | } |
| 3421 | case LoongArch::VFRSTPI_B: |
| 3422 | case LoongArch::VFRSTPI_H: |
| 3423 | case LoongArch::VSRANI_H_W: |
| 3424 | case LoongArch::VSRARNI_H_W: |
| 3425 | case LoongArch::VSRLNI_H_W: |
| 3426 | case LoongArch::VSRLRNI_H_W: |
| 3427 | case LoongArch::VSSRANI_HU_W: |
| 3428 | case LoongArch::VSSRANI_H_W: |
| 3429 | case LoongArch::VSSRARNI_HU_W: |
| 3430 | case LoongArch::VSSRARNI_H_W: |
| 3431 | case LoongArch::VSSRLNI_HU_W: |
| 3432 | case LoongArch::VSSRLNI_H_W: |
| 3433 | case LoongArch::VSSRLRNI_HU_W: |
| 3434 | case LoongArch::VSSRLRNI_H_W: { |
| 3435 | // op: imm5 |
| 3436 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3437 | Value |= (op & 0x1f) << 10; |
| 3438 | // op: vj |
| 3439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3440 | Value |= (op & 0x1f) << 5; |
| 3441 | // op: vd |
| 3442 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3443 | Value |= (op & 0x1f); |
| 3444 | break; |
| 3445 | } |
| 3446 | case LoongArch::XVFRSTPI_B: |
| 3447 | case LoongArch::XVFRSTPI_H: |
| 3448 | case LoongArch::XVSRANI_H_W: |
| 3449 | case LoongArch::XVSRARNI_H_W: |
| 3450 | case LoongArch::XVSRLNI_H_W: |
| 3451 | case LoongArch::XVSRLRNI_H_W: |
| 3452 | case LoongArch::XVSSRANI_HU_W: |
| 3453 | case LoongArch::XVSSRANI_H_W: |
| 3454 | case LoongArch::XVSSRARNI_HU_W: |
| 3455 | case LoongArch::XVSSRARNI_H_W: |
| 3456 | case LoongArch::XVSSRLNI_HU_W: |
| 3457 | case LoongArch::XVSSRLNI_H_W: |
| 3458 | case LoongArch::XVSSRLRNI_HU_W: |
| 3459 | case LoongArch::XVSSRLRNI_H_W: { |
| 3460 | // op: imm5 |
| 3461 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3462 | Value |= (op & 0x1f) << 10; |
| 3463 | // op: xj |
| 3464 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3465 | Value |= (op & 0x1f) << 5; |
| 3466 | // op: xd |
| 3467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3468 | Value |= (op & 0x1f); |
| 3469 | break; |
| 3470 | } |
| 3471 | case LoongArch::XVSTELM_B: { |
| 3472 | // op: imm5 |
| 3473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3474 | Value |= (op & 0x1f) << 18; |
| 3475 | // op: imm8 |
| 3476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3477 | Value |= (op & 0xff) << 10; |
| 3478 | // op: rj |
| 3479 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3480 | Value |= (op & 0x1f) << 5; |
| 3481 | // op: xd |
| 3482 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3483 | Value |= (op & 0x1f); |
| 3484 | break; |
| 3485 | } |
| 3486 | case LoongArch::X86RCLI_D: |
| 3487 | case LoongArch::X86RCRI_D: |
| 3488 | case LoongArch::X86ROTLI_D: |
| 3489 | case LoongArch::X86ROTRI_D: |
| 3490 | case LoongArch::X86SLLI_D: |
| 3491 | case LoongArch::X86SRAI_D: |
| 3492 | case LoongArch::X86SRLI_D: { |
| 3493 | // op: imm6 |
| 3494 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3495 | Value |= (op & 0x3f) << 10; |
| 3496 | // op: rj |
| 3497 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3498 | Value |= (op & 0x1f) << 5; |
| 3499 | break; |
| 3500 | } |
| 3501 | case LoongArch::RCRI_D: |
| 3502 | case LoongArch::ROTRI_D: |
| 3503 | case LoongArch::SLLI_D: |
| 3504 | case LoongArch::SRAI_D: |
| 3505 | case LoongArch::SRLI_D: { |
| 3506 | // op: imm6 |
| 3507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3508 | Value |= (op & 0x3f) << 10; |
| 3509 | // op: rj |
| 3510 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3511 | Value |= (op & 0x1f) << 5; |
| 3512 | // op: rd |
| 3513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3514 | Value |= (op & 0x1f); |
| 3515 | break; |
| 3516 | } |
| 3517 | case LoongArch::VBITCLRI_D: |
| 3518 | case LoongArch::VBITREVI_D: |
| 3519 | case LoongArch::VBITSETI_D: |
| 3520 | case LoongArch::VROTRI_D: |
| 3521 | case LoongArch::VSAT_D: |
| 3522 | case LoongArch::VSAT_DU: |
| 3523 | case LoongArch::VSLLI_D: |
| 3524 | case LoongArch::VSRAI_D: |
| 3525 | case LoongArch::VSRARI_D: |
| 3526 | case LoongArch::VSRLI_D: |
| 3527 | case LoongArch::VSRLRI_D: { |
| 3528 | // op: imm6 |
| 3529 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3530 | Value |= (op & 0x3f) << 10; |
| 3531 | // op: vj |
| 3532 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3533 | Value |= (op & 0x1f) << 5; |
| 3534 | // op: vd |
| 3535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3536 | Value |= (op & 0x1f); |
| 3537 | break; |
| 3538 | } |
| 3539 | case LoongArch::XVBITCLRI_D: |
| 3540 | case LoongArch::XVBITREVI_D: |
| 3541 | case LoongArch::XVBITSETI_D: |
| 3542 | case LoongArch::XVROTRI_D: |
| 3543 | case LoongArch::XVSAT_D: |
| 3544 | case LoongArch::XVSAT_DU: |
| 3545 | case LoongArch::XVSLLI_D: |
| 3546 | case LoongArch::XVSRAI_D: |
| 3547 | case LoongArch::XVSRARI_D: |
| 3548 | case LoongArch::XVSRLI_D: |
| 3549 | case LoongArch::XVSRLRI_D: { |
| 3550 | // op: imm6 |
| 3551 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3552 | Value |= (op & 0x3f) << 10; |
| 3553 | // op: xj |
| 3554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3555 | Value |= (op & 0x1f) << 5; |
| 3556 | // op: xd |
| 3557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3558 | Value |= (op & 0x1f); |
| 3559 | break; |
| 3560 | } |
| 3561 | case LoongArch::VSRANI_W_D: |
| 3562 | case LoongArch::VSRARNI_W_D: |
| 3563 | case LoongArch::VSRLNI_W_D: |
| 3564 | case LoongArch::VSRLRNI_W_D: |
| 3565 | case LoongArch::VSSRANI_WU_D: |
| 3566 | case LoongArch::VSSRANI_W_D: |
| 3567 | case LoongArch::VSSRARNI_WU_D: |
| 3568 | case LoongArch::VSSRARNI_W_D: |
| 3569 | case LoongArch::VSSRLNI_WU_D: |
| 3570 | case LoongArch::VSSRLNI_W_D: |
| 3571 | case LoongArch::VSSRLRNI_WU_D: |
| 3572 | case LoongArch::VSSRLRNI_W_D: { |
| 3573 | // op: imm6 |
| 3574 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3575 | Value |= (op & 0x3f) << 10; |
| 3576 | // op: vj |
| 3577 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3578 | Value |= (op & 0x1f) << 5; |
| 3579 | // op: vd |
| 3580 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3581 | Value |= (op & 0x1f); |
| 3582 | break; |
| 3583 | } |
| 3584 | case LoongArch::XVSRANI_W_D: |
| 3585 | case LoongArch::XVSRARNI_W_D: |
| 3586 | case LoongArch::XVSRLNI_W_D: |
| 3587 | case LoongArch::XVSRLRNI_W_D: |
| 3588 | case LoongArch::XVSSRANI_WU_D: |
| 3589 | case LoongArch::XVSSRANI_W_D: |
| 3590 | case LoongArch::XVSSRARNI_WU_D: |
| 3591 | case LoongArch::XVSSRARNI_W_D: |
| 3592 | case LoongArch::XVSSRLNI_WU_D: |
| 3593 | case LoongArch::XVSSRLNI_W_D: |
| 3594 | case LoongArch::XVSSRLRNI_WU_D: |
| 3595 | case LoongArch::XVSSRLRNI_W_D: { |
| 3596 | // op: imm6 |
| 3597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3598 | Value |= (op & 0x3f) << 10; |
| 3599 | // op: xj |
| 3600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3601 | Value |= (op & 0x1f) << 5; |
| 3602 | // op: xd |
| 3603 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3604 | Value |= (op & 0x1f); |
| 3605 | break; |
| 3606 | } |
| 3607 | case LoongArch::VSRANI_D_Q: |
| 3608 | case LoongArch::VSRARNI_D_Q: |
| 3609 | case LoongArch::VSRLNI_D_Q: |
| 3610 | case LoongArch::VSRLRNI_D_Q: |
| 3611 | case LoongArch::VSSRANI_DU_Q: |
| 3612 | case LoongArch::VSSRANI_D_Q: |
| 3613 | case LoongArch::VSSRARNI_DU_Q: |
| 3614 | case LoongArch::VSSRARNI_D_Q: |
| 3615 | case LoongArch::VSSRLNI_DU_Q: |
| 3616 | case LoongArch::VSSRLNI_D_Q: |
| 3617 | case LoongArch::VSSRLRNI_DU_Q: |
| 3618 | case LoongArch::VSSRLRNI_D_Q: { |
| 3619 | // op: imm7 |
| 3620 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3621 | Value |= (op & 0x7f) << 10; |
| 3622 | // op: vj |
| 3623 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3624 | Value |= (op & 0x1f) << 5; |
| 3625 | // op: vd |
| 3626 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3627 | Value |= (op & 0x1f); |
| 3628 | break; |
| 3629 | } |
| 3630 | case LoongArch::XVSRANI_D_Q: |
| 3631 | case LoongArch::XVSRARNI_D_Q: |
| 3632 | case LoongArch::XVSRLNI_D_Q: |
| 3633 | case LoongArch::XVSRLRNI_D_Q: |
| 3634 | case LoongArch::XVSSRANI_DU_Q: |
| 3635 | case LoongArch::XVSSRANI_D_Q: |
| 3636 | case LoongArch::XVSSRARNI_DU_Q: |
| 3637 | case LoongArch::XVSSRARNI_D_Q: |
| 3638 | case LoongArch::XVSSRLNI_DU_Q: |
| 3639 | case LoongArch::XVSSRLNI_D_Q: |
| 3640 | case LoongArch::XVSSRLRNI_DU_Q: |
| 3641 | case LoongArch::XVSSRLRNI_D_Q: { |
| 3642 | // op: imm7 |
| 3643 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3644 | Value |= (op & 0x7f) << 10; |
| 3645 | // op: xj |
| 3646 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3647 | Value |= (op & 0x1f) << 5; |
| 3648 | // op: xd |
| 3649 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3650 | Value |= (op & 0x1f); |
| 3651 | break; |
| 3652 | } |
| 3653 | case LoongArch::ARMMFFLAG: |
| 3654 | case LoongArch::ARMMTFLAG: |
| 3655 | case LoongArch::X86MFFLAG: |
| 3656 | case LoongArch::X86MTFLAG: { |
| 3657 | // op: imm8 |
| 3658 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3659 | Value |= (op & 0xff) << 10; |
| 3660 | // op: rd |
| 3661 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3662 | Value |= (op & 0x1f); |
| 3663 | break; |
| 3664 | } |
| 3665 | case LoongArch::X86SETTAG: { |
| 3666 | // op: imm8 |
| 3667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3668 | Value |= (op & 0xff) << 10; |
| 3669 | // op: imm5 |
| 3670 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3671 | Value |= (op & 0x1f) << 5; |
| 3672 | // op: rd |
| 3673 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3674 | Value |= (op & 0x1f); |
| 3675 | break; |
| 3676 | } |
| 3677 | case LoongArch::LDDIR: { |
| 3678 | // op: imm8 |
| 3679 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3680 | Value |= (op & 0xff) << 10; |
| 3681 | // op: rj |
| 3682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3683 | Value |= (op & 0x1f) << 5; |
| 3684 | // op: rd |
| 3685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3686 | Value |= (op & 0x1f); |
| 3687 | break; |
| 3688 | } |
| 3689 | case LoongArch::VANDI_B: |
| 3690 | case LoongArch::VNORI_B: |
| 3691 | case LoongArch::VORI_B: |
| 3692 | case LoongArch::VSHUF4I_B: |
| 3693 | case LoongArch::VSHUF4I_H: |
| 3694 | case LoongArch::VSHUF4I_W: |
| 3695 | case LoongArch::VXORI_B: { |
| 3696 | // op: imm8 |
| 3697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3698 | Value |= (op & 0xff) << 10; |
| 3699 | // op: vj |
| 3700 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3701 | Value |= (op & 0x1f) << 5; |
| 3702 | // op: vd |
| 3703 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3704 | Value |= (op & 0x1f); |
| 3705 | break; |
| 3706 | } |
| 3707 | case LoongArch::XVANDI_B: |
| 3708 | case LoongArch::XVNORI_B: |
| 3709 | case LoongArch::XVORI_B: |
| 3710 | case LoongArch::XVPERMI_D: |
| 3711 | case LoongArch::XVSHUF4I_B: |
| 3712 | case LoongArch::XVSHUF4I_H: |
| 3713 | case LoongArch::XVSHUF4I_W: |
| 3714 | case LoongArch::XVXORI_B: { |
| 3715 | // op: imm8 |
| 3716 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3717 | Value |= (op & 0xff) << 10; |
| 3718 | // op: xj |
| 3719 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3720 | Value |= (op & 0x1f) << 5; |
| 3721 | // op: xd |
| 3722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3723 | Value |= (op & 0x1f); |
| 3724 | break; |
| 3725 | } |
| 3726 | case LoongArch::VBITSELI_B: |
| 3727 | case LoongArch::VEXTRINS_B: |
| 3728 | case LoongArch::VEXTRINS_D: |
| 3729 | case LoongArch::VEXTRINS_H: |
| 3730 | case LoongArch::VEXTRINS_W: |
| 3731 | case LoongArch::VPERMI_W: |
| 3732 | case LoongArch::VSHUF4I_D: { |
| 3733 | // op: imm8 |
| 3734 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3735 | Value |= (op & 0xff) << 10; |
| 3736 | // op: vj |
| 3737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3738 | Value |= (op & 0x1f) << 5; |
| 3739 | // op: vd |
| 3740 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3741 | Value |= (op & 0x1f); |
| 3742 | break; |
| 3743 | } |
| 3744 | case LoongArch::XVBITSELI_B: |
| 3745 | case LoongArch::XVEXTRINS_B: |
| 3746 | case LoongArch::XVEXTRINS_D: |
| 3747 | case LoongArch::XVEXTRINS_H: |
| 3748 | case LoongArch::XVEXTRINS_W: |
| 3749 | case LoongArch::XVPERMI_Q: |
| 3750 | case LoongArch::XVPERMI_W: |
| 3751 | case LoongArch::XVSHUF4I_D: { |
| 3752 | // op: imm8 |
| 3753 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3754 | Value |= (op & 0xff) << 10; |
| 3755 | // op: xj |
| 3756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3757 | Value |= (op & 0x1f) << 5; |
| 3758 | // op: xd |
| 3759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3760 | Value |= (op & 0x1f); |
| 3761 | break; |
| 3762 | } |
| 3763 | case LoongArch::VLDREPL_D: { |
| 3764 | // op: imm9 |
| 3765 | op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI); |
| 3766 | Value |= (op & 0x1ff) << 10; |
| 3767 | // op: rj |
| 3768 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3769 | Value |= (op & 0x1f) << 5; |
| 3770 | // op: vd |
| 3771 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3772 | Value |= (op & 0x1f); |
| 3773 | break; |
| 3774 | } |
| 3775 | case LoongArch::XVLDREPL_D: { |
| 3776 | // op: imm9 |
| 3777 | op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI); |
| 3778 | Value |= (op & 0x1ff) << 10; |
| 3779 | // op: rj |
| 3780 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3781 | Value |= (op & 0x1f) << 5; |
| 3782 | // op: xd |
| 3783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3784 | Value |= (op & 0x1f); |
| 3785 | break; |
| 3786 | } |
| 3787 | case LoongArch::BSTRPICK_D: { |
| 3788 | // op: msbd |
| 3789 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3790 | Value |= (op & 0x3f) << 16; |
| 3791 | // op: lsbd |
| 3792 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3793 | Value |= (op & 0x3f) << 10; |
| 3794 | // op: rj |
| 3795 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3796 | Value |= (op & 0x1f) << 5; |
| 3797 | // op: rd |
| 3798 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3799 | Value |= (op & 0x1f); |
| 3800 | break; |
| 3801 | } |
| 3802 | case LoongArch::BSTRINS_D: { |
| 3803 | // op: msbd |
| 3804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3805 | Value |= (op & 0x3f) << 16; |
| 3806 | // op: lsbd |
| 3807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3808 | Value |= (op & 0x3f) << 10; |
| 3809 | // op: rj |
| 3810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3811 | Value |= (op & 0x1f) << 5; |
| 3812 | // op: rd |
| 3813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3814 | Value |= (op & 0x1f); |
| 3815 | break; |
| 3816 | } |
| 3817 | case LoongArch::BSTRPICK_W: { |
| 3818 | // op: msbw |
| 3819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3820 | Value |= (op & 0x1f) << 16; |
| 3821 | // op: lsbw |
| 3822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3823 | Value |= (op & 0x1f) << 10; |
| 3824 | // op: rj |
| 3825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3826 | Value |= (op & 0x1f) << 5; |
| 3827 | // op: rd |
| 3828 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3829 | Value |= (op & 0x1f); |
| 3830 | break; |
| 3831 | } |
| 3832 | case LoongArch::BSTRINS_W: { |
| 3833 | // op: msbw |
| 3834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3835 | Value |= (op & 0x1f) << 16; |
| 3836 | // op: lsbw |
| 3837 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3838 | Value |= (op & 0x1f) << 10; |
| 3839 | // op: rj |
| 3840 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3841 | Value |= (op & 0x1f) << 5; |
| 3842 | // op: rd |
| 3843 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3844 | Value |= (op & 0x1f); |
| 3845 | break; |
| 3846 | } |
| 3847 | case LoongArch::X86MTTOP: { |
| 3848 | // op: ptr |
| 3849 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3850 | Value |= (op & 0x7) << 5; |
| 3851 | break; |
| 3852 | } |
| 3853 | case LoongArch::X86MFTOP: { |
| 3854 | // op: rd |
| 3855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3856 | Value |= (op & 0x1f); |
| 3857 | break; |
| 3858 | } |
| 3859 | case LoongArch::X86DEC_B: |
| 3860 | case LoongArch::X86DEC_D: |
| 3861 | case LoongArch::X86DEC_H: |
| 3862 | case LoongArch::X86DEC_W: |
| 3863 | case LoongArch::X86INC_B: |
| 3864 | case LoongArch::X86INC_D: |
| 3865 | case LoongArch::X86INC_H: |
| 3866 | case LoongArch::X86INC_W: { |
| 3867 | // op: rj |
| 3868 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3869 | Value |= (op & 0x1f) << 5; |
| 3870 | break; |
| 3871 | } |
| 3872 | case LoongArch::BITREV_4B: |
| 3873 | case LoongArch::BITREV_8B: |
| 3874 | case LoongArch::BITREV_D: |
| 3875 | case LoongArch::BITREV_W: |
| 3876 | case LoongArch::CLO_D: |
| 3877 | case LoongArch::CLO_W: |
| 3878 | case LoongArch::CLZ_D: |
| 3879 | case LoongArch::CLZ_W: |
| 3880 | case LoongArch::CPUCFG: |
| 3881 | case LoongArch::CTO_D: |
| 3882 | case LoongArch::CTO_W: |
| 3883 | case LoongArch::CTZ_D: |
| 3884 | case LoongArch::CTZ_W: |
| 3885 | case LoongArch::EXT_W_B: |
| 3886 | case LoongArch::EXT_W_H: |
| 3887 | case LoongArch::IOCSRRD_B: |
| 3888 | case LoongArch::IOCSRRD_D: |
| 3889 | case LoongArch::IOCSRRD_H: |
| 3890 | case LoongArch::IOCSRRD_W: |
| 3891 | case LoongArch::IOCSRWR_B: |
| 3892 | case LoongArch::IOCSRWR_D: |
| 3893 | case LoongArch::IOCSRWR_H: |
| 3894 | case LoongArch::IOCSRWR_W: |
| 3895 | case LoongArch::LLACQ_D: |
| 3896 | case LoongArch::LLACQ_W: |
| 3897 | case LoongArch::RDTIMEH_W: |
| 3898 | case LoongArch::RDTIMEL_W: |
| 3899 | case LoongArch::RDTIME_D: |
| 3900 | case LoongArch::REVB_2H: |
| 3901 | case LoongArch::REVB_2W: |
| 3902 | case LoongArch::REVB_4H: |
| 3903 | case LoongArch::REVB_D: |
| 3904 | case LoongArch::REVH_2W: |
| 3905 | case LoongArch::REVH_D: |
| 3906 | case LoongArch::SETX86LOOPE: |
| 3907 | case LoongArch::SETX86LOOPNE: { |
| 3908 | // op: rj |
| 3909 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3910 | Value |= (op & 0x1f) << 5; |
| 3911 | // op: rd |
| 3912 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3913 | Value |= (op & 0x1f); |
| 3914 | break; |
| 3915 | } |
| 3916 | case LoongArch::MOVGR2SCR: { |
| 3917 | // op: rj |
| 3918 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3919 | Value |= (op & 0x1f) << 5; |
| 3920 | // op: sd |
| 3921 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3922 | Value |= (op & 0x3); |
| 3923 | break; |
| 3924 | } |
| 3925 | case LoongArch::VREPLGR2VR_B: |
| 3926 | case LoongArch::VREPLGR2VR_D: |
| 3927 | case LoongArch::VREPLGR2VR_H: |
| 3928 | case LoongArch::VREPLGR2VR_W: { |
| 3929 | // op: rj |
| 3930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3931 | Value |= (op & 0x1f) << 5; |
| 3932 | // op: vd |
| 3933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3934 | Value |= (op & 0x1f); |
| 3935 | break; |
| 3936 | } |
| 3937 | case LoongArch::XVREPLGR2VR_B: |
| 3938 | case LoongArch::XVREPLGR2VR_D: |
| 3939 | case LoongArch::XVREPLGR2VR_H: |
| 3940 | case LoongArch::XVREPLGR2VR_W: { |
| 3941 | // op: rj |
| 3942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3943 | Value |= (op & 0x1f) << 5; |
| 3944 | // op: xd |
| 3945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3946 | Value |= (op & 0x1f); |
| 3947 | break; |
| 3948 | } |
| 3949 | case LoongArch::SCREL_D: |
| 3950 | case LoongArch::SCREL_W: { |
| 3951 | // op: rj |
| 3952 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3953 | Value |= (op & 0x1f) << 5; |
| 3954 | // op: rd |
| 3955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3956 | Value |= (op & 0x1f); |
| 3957 | break; |
| 3958 | } |
| 3959 | case LoongArch::INVTLB: { |
| 3960 | // op: rk |
| 3961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3962 | Value |= (op & 0x1f) << 10; |
| 3963 | // op: rj |
| 3964 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3965 | Value |= (op & 0x1f) << 5; |
| 3966 | // op: op |
| 3967 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3968 | Value |= (op & 0x1f); |
| 3969 | break; |
| 3970 | } |
| 3971 | case LoongArch::ASRTGT_D: |
| 3972 | case LoongArch::ASRTLE_D: |
| 3973 | case LoongArch::X86ADC_B: |
| 3974 | case LoongArch::X86ADC_D: |
| 3975 | case LoongArch::X86ADC_H: |
| 3976 | case LoongArch::X86ADC_W: |
| 3977 | case LoongArch::X86ADD_B: |
| 3978 | case LoongArch::X86ADD_D: |
| 3979 | case LoongArch::X86ADD_DU: |
| 3980 | case LoongArch::X86ADD_H: |
| 3981 | case LoongArch::X86ADD_W: |
| 3982 | case LoongArch::X86ADD_WU: |
| 3983 | case LoongArch::X86AND_B: |
| 3984 | case LoongArch::X86AND_D: |
| 3985 | case LoongArch::X86AND_H: |
| 3986 | case LoongArch::X86AND_W: |
| 3987 | case LoongArch::X86MUL_B: |
| 3988 | case LoongArch::X86MUL_BU: |
| 3989 | case LoongArch::X86MUL_D: |
| 3990 | case LoongArch::X86MUL_DU: |
| 3991 | case LoongArch::X86MUL_H: |
| 3992 | case LoongArch::X86MUL_HU: |
| 3993 | case LoongArch::X86MUL_W: |
| 3994 | case LoongArch::X86MUL_WU: |
| 3995 | case LoongArch::X86OR_B: |
| 3996 | case LoongArch::X86OR_D: |
| 3997 | case LoongArch::X86OR_H: |
| 3998 | case LoongArch::X86OR_W: |
| 3999 | case LoongArch::X86RCL_B: |
| 4000 | case LoongArch::X86RCL_D: |
| 4001 | case LoongArch::X86RCL_H: |
| 4002 | case LoongArch::X86RCL_W: |
| 4003 | case LoongArch::X86RCR_B: |
| 4004 | case LoongArch::X86RCR_D: |
| 4005 | case LoongArch::X86RCR_H: |
| 4006 | case LoongArch::X86RCR_W: |
| 4007 | case LoongArch::X86ROTL_B: |
| 4008 | case LoongArch::X86ROTL_D: |
| 4009 | case LoongArch::X86ROTL_H: |
| 4010 | case LoongArch::X86ROTL_W: |
| 4011 | case LoongArch::X86ROTR_B: |
| 4012 | case LoongArch::X86ROTR_D: |
| 4013 | case LoongArch::X86ROTR_H: |
| 4014 | case LoongArch::X86ROTR_W: |
| 4015 | case LoongArch::X86SBC_B: |
| 4016 | case LoongArch::X86SBC_D: |
| 4017 | case LoongArch::X86SBC_H: |
| 4018 | case LoongArch::X86SBC_W: |
| 4019 | case LoongArch::X86SLL_B: |
| 4020 | case LoongArch::X86SLL_D: |
| 4021 | case LoongArch::X86SLL_H: |
| 4022 | case LoongArch::X86SLL_W: |
| 4023 | case LoongArch::X86SRA_B: |
| 4024 | case LoongArch::X86SRA_D: |
| 4025 | case LoongArch::X86SRA_H: |
| 4026 | case LoongArch::X86SRA_W: |
| 4027 | case LoongArch::X86SRL_B: |
| 4028 | case LoongArch::X86SRL_D: |
| 4029 | case LoongArch::X86SRL_H: |
| 4030 | case LoongArch::X86SRL_W: |
| 4031 | case LoongArch::X86SUB_B: |
| 4032 | case LoongArch::X86SUB_D: |
| 4033 | case LoongArch::X86SUB_DU: |
| 4034 | case LoongArch::X86SUB_H: |
| 4035 | case LoongArch::X86SUB_W: |
| 4036 | case LoongArch::X86SUB_WU: |
| 4037 | case LoongArch::X86XOR_B: |
| 4038 | case LoongArch::X86XOR_D: |
| 4039 | case LoongArch::X86XOR_H: |
| 4040 | case LoongArch::X86XOR_W: { |
| 4041 | // op: rk |
| 4042 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4043 | Value |= (op & 0x1f) << 10; |
| 4044 | // op: rj |
| 4045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4046 | Value |= (op & 0x1f) << 5; |
| 4047 | break; |
| 4048 | } |
| 4049 | case LoongArch::AMADD_B: |
| 4050 | case LoongArch::AMADD_D: |
| 4051 | case LoongArch::AMADD_H: |
| 4052 | case LoongArch::AMADD_W: |
| 4053 | case LoongArch::AMADD__DB_B: |
| 4054 | case LoongArch::AMADD__DB_D: |
| 4055 | case LoongArch::AMADD__DB_H: |
| 4056 | case LoongArch::AMADD__DB_W: |
| 4057 | case LoongArch::AMAND_D: |
| 4058 | case LoongArch::AMAND_W: |
| 4059 | case LoongArch::AMAND__DB_D: |
| 4060 | case LoongArch::AMAND__DB_W: |
| 4061 | case LoongArch::AMMAX_D: |
| 4062 | case LoongArch::AMMAX_DU: |
| 4063 | case LoongArch::AMMAX_W: |
| 4064 | case LoongArch::AMMAX_WU: |
| 4065 | case LoongArch::AMMAX__DB_D: |
| 4066 | case LoongArch::AMMAX__DB_DU: |
| 4067 | case LoongArch::AMMAX__DB_W: |
| 4068 | case LoongArch::AMMAX__DB_WU: |
| 4069 | case LoongArch::AMMIN_D: |
| 4070 | case LoongArch::AMMIN_DU: |
| 4071 | case LoongArch::AMMIN_W: |
| 4072 | case LoongArch::AMMIN_WU: |
| 4073 | case LoongArch::AMMIN__DB_D: |
| 4074 | case LoongArch::AMMIN__DB_DU: |
| 4075 | case LoongArch::AMMIN__DB_W: |
| 4076 | case LoongArch::AMMIN__DB_WU: |
| 4077 | case LoongArch::AMOR_D: |
| 4078 | case LoongArch::AMOR_W: |
| 4079 | case LoongArch::AMOR__DB_D: |
| 4080 | case LoongArch::AMOR__DB_W: |
| 4081 | case LoongArch::AMSWAP_B: |
| 4082 | case LoongArch::AMSWAP_D: |
| 4083 | case LoongArch::AMSWAP_H: |
| 4084 | case LoongArch::AMSWAP_W: |
| 4085 | case LoongArch::AMSWAP__DB_B: |
| 4086 | case LoongArch::AMSWAP__DB_D: |
| 4087 | case LoongArch::AMSWAP__DB_H: |
| 4088 | case LoongArch::AMSWAP__DB_W: |
| 4089 | case LoongArch::AMXOR_D: |
| 4090 | case LoongArch::AMXOR_W: |
| 4091 | case LoongArch::AMXOR__DB_D: |
| 4092 | case LoongArch::AMXOR__DB_W: { |
| 4093 | // op: rk |
| 4094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4095 | Value |= (op & 0x1f) << 10; |
| 4096 | // op: rj |
| 4097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4098 | Value |= (op & 0x1f) << 5; |
| 4099 | // op: rd |
| 4100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4101 | Value |= (op & 0x1f); |
| 4102 | break; |
| 4103 | } |
| 4104 | case LoongArch::FLDGT_D: |
| 4105 | case LoongArch::FLDGT_S: |
| 4106 | case LoongArch::FLDLE_D: |
| 4107 | case LoongArch::FLDLE_S: |
| 4108 | case LoongArch::FLDX_D: |
| 4109 | case LoongArch::FLDX_S: |
| 4110 | case LoongArch::FSTGT_D: |
| 4111 | case LoongArch::FSTGT_S: |
| 4112 | case LoongArch::FSTLE_D: |
| 4113 | case LoongArch::FSTLE_S: |
| 4114 | case LoongArch::FSTX_D: |
| 4115 | case LoongArch::FSTX_S: { |
| 4116 | // op: rk |
| 4117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4118 | Value |= (op & 0x1f) << 10; |
| 4119 | // op: rj |
| 4120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4121 | Value |= (op & 0x1f) << 5; |
| 4122 | // op: fd |
| 4123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4124 | Value |= (op & 0x1f); |
| 4125 | break; |
| 4126 | } |
| 4127 | case LoongArch::PRELDX: { |
| 4128 | // op: rk |
| 4129 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4130 | Value |= (op & 0x1f) << 10; |
| 4131 | // op: rj |
| 4132 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4133 | Value |= (op & 0x1f) << 5; |
| 4134 | // op: imm5 |
| 4135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4136 | Value |= (op & 0x1f); |
| 4137 | break; |
| 4138 | } |
| 4139 | case LoongArch::ADC_B: |
| 4140 | case LoongArch::ADC_D: |
| 4141 | case LoongArch::ADC_H: |
| 4142 | case LoongArch::ADC_W: |
| 4143 | case LoongArch::ADD_D: |
| 4144 | case LoongArch::ADD_W: |
| 4145 | case LoongArch::AND: |
| 4146 | case LoongArch::ANDN: |
| 4147 | case LoongArch::CRCC_W_B_W: |
| 4148 | case LoongArch::CRCC_W_D_W: |
| 4149 | case LoongArch::CRCC_W_H_W: |
| 4150 | case LoongArch::CRCC_W_W_W: |
| 4151 | case LoongArch::CRC_W_B_W: |
| 4152 | case LoongArch::CRC_W_D_W: |
| 4153 | case LoongArch::CRC_W_H_W: |
| 4154 | case LoongArch::CRC_W_W_W: |
| 4155 | case LoongArch::DIV_D: |
| 4156 | case LoongArch::DIV_DU: |
| 4157 | case LoongArch::DIV_W: |
| 4158 | case LoongArch::DIV_WU: |
| 4159 | case LoongArch::LDGT_B: |
| 4160 | case LoongArch::LDGT_D: |
| 4161 | case LoongArch::LDGT_H: |
| 4162 | case LoongArch::LDGT_W: |
| 4163 | case LoongArch::LDLE_B: |
| 4164 | case LoongArch::LDLE_D: |
| 4165 | case LoongArch::LDLE_H: |
| 4166 | case LoongArch::LDLE_W: |
| 4167 | case LoongArch::LDX_B: |
| 4168 | case LoongArch::LDX_BU: |
| 4169 | case LoongArch::LDX_D: |
| 4170 | case LoongArch::LDX_H: |
| 4171 | case LoongArch::LDX_HU: |
| 4172 | case LoongArch::LDX_W: |
| 4173 | case LoongArch::LDX_WU: |
| 4174 | case LoongArch::MASKEQZ: |
| 4175 | case LoongArch::MASKNEZ: |
| 4176 | case LoongArch::MOD_D: |
| 4177 | case LoongArch::MOD_DU: |
| 4178 | case LoongArch::MOD_W: |
| 4179 | case LoongArch::MOD_WU: |
| 4180 | case LoongArch::MULH_D: |
| 4181 | case LoongArch::MULH_DU: |
| 4182 | case LoongArch::MULH_W: |
| 4183 | case LoongArch::MULH_WU: |
| 4184 | case LoongArch::MULW_D_W: |
| 4185 | case LoongArch::MULW_D_WU: |
| 4186 | case LoongArch::MUL_D: |
| 4187 | case LoongArch::MUL_W: |
| 4188 | case LoongArch::NOR: |
| 4189 | case LoongArch::OR: |
| 4190 | case LoongArch::ORN: |
| 4191 | case LoongArch::RCR_B: |
| 4192 | case LoongArch::RCR_D: |
| 4193 | case LoongArch::RCR_H: |
| 4194 | case LoongArch::RCR_W: |
| 4195 | case LoongArch::ROTR_B: |
| 4196 | case LoongArch::ROTR_D: |
| 4197 | case LoongArch::ROTR_H: |
| 4198 | case LoongArch::ROTR_W: |
| 4199 | case LoongArch::SBC_B: |
| 4200 | case LoongArch::SBC_D: |
| 4201 | case LoongArch::SBC_H: |
| 4202 | case LoongArch::SBC_W: |
| 4203 | case LoongArch::SLL_D: |
| 4204 | case LoongArch::SLL_W: |
| 4205 | case LoongArch::SLT: |
| 4206 | case LoongArch::SLTU: |
| 4207 | case LoongArch::SRA_D: |
| 4208 | case LoongArch::SRA_W: |
| 4209 | case LoongArch::SRL_D: |
| 4210 | case LoongArch::SRL_W: |
| 4211 | case LoongArch::STGT_B: |
| 4212 | case LoongArch::STGT_D: |
| 4213 | case LoongArch::STGT_H: |
| 4214 | case LoongArch::STGT_W: |
| 4215 | case LoongArch::STLE_B: |
| 4216 | case LoongArch::STLE_D: |
| 4217 | case LoongArch::STLE_H: |
| 4218 | case LoongArch::STLE_W: |
| 4219 | case LoongArch::STX_B: |
| 4220 | case LoongArch::STX_D: |
| 4221 | case LoongArch::STX_H: |
| 4222 | case LoongArch::STX_W: |
| 4223 | case LoongArch::SUB_D: |
| 4224 | case LoongArch::SUB_W: |
| 4225 | case LoongArch::XOR: { |
| 4226 | // op: rk |
| 4227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4228 | Value |= (op & 0x1f) << 10; |
| 4229 | // op: rj |
| 4230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4231 | Value |= (op & 0x1f) << 5; |
| 4232 | // op: rd |
| 4233 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4234 | Value |= (op & 0x1f); |
| 4235 | break; |
| 4236 | } |
| 4237 | case LoongArch::VLDX: |
| 4238 | case LoongArch::VSTX: { |
| 4239 | // op: rk |
| 4240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4241 | Value |= (op & 0x1f) << 10; |
| 4242 | // op: rj |
| 4243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4244 | Value |= (op & 0x1f) << 5; |
| 4245 | // op: vd |
| 4246 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4247 | Value |= (op & 0x1f); |
| 4248 | break; |
| 4249 | } |
| 4250 | case LoongArch::XVLDX: |
| 4251 | case LoongArch::XVSTX: { |
| 4252 | // op: rk |
| 4253 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4254 | Value |= (op & 0x1f) << 10; |
| 4255 | // op: rj |
| 4256 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4257 | Value |= (op & 0x1f) << 5; |
| 4258 | // op: xd |
| 4259 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4260 | Value |= (op & 0x1f); |
| 4261 | break; |
| 4262 | } |
| 4263 | case LoongArch::AMCAS_B: |
| 4264 | case LoongArch::AMCAS_D: |
| 4265 | case LoongArch::AMCAS_H: |
| 4266 | case LoongArch::AMCAS_W: |
| 4267 | case LoongArch::AMCAS__DB_B: |
| 4268 | case LoongArch::AMCAS__DB_D: |
| 4269 | case LoongArch::AMCAS__DB_H: |
| 4270 | case LoongArch::AMCAS__DB_W: |
| 4271 | case LoongArch::SC_Q: { |
| 4272 | // op: rk |
| 4273 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4274 | Value |= (op & 0x1f) << 10; |
| 4275 | // op: rj |
| 4276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4277 | Value |= (op & 0x1f) << 5; |
| 4278 | // op: rd |
| 4279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4280 | Value |= (op & 0x1f); |
| 4281 | break; |
| 4282 | } |
| 4283 | case LoongArch::VREPLVE_B: |
| 4284 | case LoongArch::VREPLVE_D: |
| 4285 | case LoongArch::VREPLVE_H: |
| 4286 | case LoongArch::VREPLVE_W: { |
| 4287 | // op: rk |
| 4288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4289 | Value |= (op & 0x1f) << 10; |
| 4290 | // op: vj |
| 4291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4292 | Value |= (op & 0x1f) << 5; |
| 4293 | // op: vd |
| 4294 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4295 | Value |= (op & 0x1f); |
| 4296 | break; |
| 4297 | } |
| 4298 | case LoongArch::XVREPLVE_B: |
| 4299 | case LoongArch::XVREPLVE_D: |
| 4300 | case LoongArch::XVREPLVE_H: |
| 4301 | case LoongArch::XVREPLVE_W: { |
| 4302 | // op: rk |
| 4303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4304 | Value |= (op & 0x1f) << 10; |
| 4305 | // op: xj |
| 4306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4307 | Value |= (op & 0x1f) << 5; |
| 4308 | // op: xd |
| 4309 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4310 | Value |= (op & 0x1f); |
| 4311 | break; |
| 4312 | } |
| 4313 | case LoongArch::LDPTE: { |
| 4314 | // op: seq |
| 4315 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4316 | Value |= (op & 0xff) << 10; |
| 4317 | // op: rj |
| 4318 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4319 | Value |= (op & 0x1f) << 5; |
| 4320 | break; |
| 4321 | } |
| 4322 | case LoongArch::MOVSCR2GR: { |
| 4323 | // op: sj |
| 4324 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4325 | Value |= (op & 0x3) << 5; |
| 4326 | // op: rd |
| 4327 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4328 | Value |= (op & 0x1f); |
| 4329 | break; |
| 4330 | } |
| 4331 | case LoongArch::FMOV_D: |
| 4332 | case LoongArch::FMOV_S: |
| 4333 | case LoongArch::MOVCF2FR_xS: |
| 4334 | case LoongArch::MOVCF2GR: |
| 4335 | case LoongArch::MOVFCSR2GR: |
| 4336 | case LoongArch::MOVFR2CF_xS: |
| 4337 | case LoongArch::MOVFR2GR_D: |
| 4338 | case LoongArch::MOVFR2GR_S: |
| 4339 | case LoongArch::MOVFR2GR_S_64: |
| 4340 | case LoongArch::MOVFRH2GR_S: |
| 4341 | case LoongArch::MOVGR2CF: |
| 4342 | case LoongArch::MOVGR2FCSR: |
| 4343 | case LoongArch::MOVGR2FR_D: |
| 4344 | case LoongArch::MOVGR2FR_W: |
| 4345 | case LoongArch::MOVGR2FR_W_64: { |
| 4346 | // op: src |
| 4347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4348 | Value |= (op & 0x1f) << 5; |
| 4349 | // op: dst |
| 4350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4351 | Value |= (op & 0x1f); |
| 4352 | break; |
| 4353 | } |
| 4354 | case LoongArch::MOVGR2FRH_W: { |
| 4355 | // op: src |
| 4356 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4357 | Value |= (op & 0x1f) << 5; |
| 4358 | // op: dst |
| 4359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4360 | Value |= (op & 0x1f); |
| 4361 | break; |
| 4362 | } |
| 4363 | case LoongArch::VBITSEL_V: |
| 4364 | case LoongArch::VFMADD_D: |
| 4365 | case LoongArch::VFMADD_S: |
| 4366 | case LoongArch::VFMSUB_D: |
| 4367 | case LoongArch::VFMSUB_S: |
| 4368 | case LoongArch::VFNMADD_D: |
| 4369 | case LoongArch::VFNMADD_S: |
| 4370 | case LoongArch::VFNMSUB_D: |
| 4371 | case LoongArch::VFNMSUB_S: |
| 4372 | case LoongArch::VSHUF_B: { |
| 4373 | // op: va |
| 4374 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4375 | Value |= (op & 0x1f) << 15; |
| 4376 | // op: vk |
| 4377 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4378 | Value |= (op & 0x1f) << 10; |
| 4379 | // op: vj |
| 4380 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4381 | Value |= (op & 0x1f) << 5; |
| 4382 | // op: vd |
| 4383 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4384 | Value |= (op & 0x1f); |
| 4385 | break; |
| 4386 | } |
| 4387 | case LoongArch::VSETALLNEZ_B: |
| 4388 | case LoongArch::VSETALLNEZ_D: |
| 4389 | case LoongArch::VSETALLNEZ_H: |
| 4390 | case LoongArch::VSETALLNEZ_W: |
| 4391 | case LoongArch::VSETANYEQZ_B: |
| 4392 | case LoongArch::VSETANYEQZ_D: |
| 4393 | case LoongArch::VSETANYEQZ_H: |
| 4394 | case LoongArch::VSETANYEQZ_W: |
| 4395 | case LoongArch::VSETEQZ_V: |
| 4396 | case LoongArch::VSETNEZ_V: { |
| 4397 | // op: vj |
| 4398 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4399 | Value |= (op & 0x1f) << 5; |
| 4400 | // op: cd |
| 4401 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4402 | Value |= (op & 0x7); |
| 4403 | break; |
| 4404 | } |
| 4405 | case LoongArch::VCLO_B: |
| 4406 | case LoongArch::VCLO_D: |
| 4407 | case LoongArch::VCLO_H: |
| 4408 | case LoongArch::VCLO_W: |
| 4409 | case LoongArch::VCLZ_B: |
| 4410 | case LoongArch::VCLZ_D: |
| 4411 | case LoongArch::VCLZ_H: |
| 4412 | case LoongArch::VCLZ_W: |
| 4413 | case LoongArch::VEXTH_DU_WU: |
| 4414 | case LoongArch::VEXTH_D_W: |
| 4415 | case LoongArch::VEXTH_HU_BU: |
| 4416 | case LoongArch::VEXTH_H_B: |
| 4417 | case LoongArch::VEXTH_QU_DU: |
| 4418 | case LoongArch::VEXTH_Q_D: |
| 4419 | case LoongArch::VEXTH_WU_HU: |
| 4420 | case LoongArch::VEXTH_W_H: |
| 4421 | case LoongArch::VEXTL_QU_DU: |
| 4422 | case LoongArch::VEXTL_Q_D: |
| 4423 | case LoongArch::VFCLASS_D: |
| 4424 | case LoongArch::VFCLASS_S: |
| 4425 | case LoongArch::VFCVTH_D_S: |
| 4426 | case LoongArch::VFCVTH_S_H: |
| 4427 | case LoongArch::VFCVTL_D_S: |
| 4428 | case LoongArch::VFCVTL_S_H: |
| 4429 | case LoongArch::VFFINTH_D_W: |
| 4430 | case LoongArch::VFFINTL_D_W: |
| 4431 | case LoongArch::VFFINT_D_L: |
| 4432 | case LoongArch::VFFINT_D_LU: |
| 4433 | case LoongArch::VFFINT_S_W: |
| 4434 | case LoongArch::VFFINT_S_WU: |
| 4435 | case LoongArch::VFLOGB_D: |
| 4436 | case LoongArch::VFLOGB_S: |
| 4437 | case LoongArch::VFRECIPE_D: |
| 4438 | case LoongArch::VFRECIPE_S: |
| 4439 | case LoongArch::VFRECIP_D: |
| 4440 | case LoongArch::VFRECIP_S: |
| 4441 | case LoongArch::VFRINTRM_D: |
| 4442 | case LoongArch::VFRINTRM_S: |
| 4443 | case LoongArch::VFRINTRNE_D: |
| 4444 | case LoongArch::VFRINTRNE_S: |
| 4445 | case LoongArch::VFRINTRP_D: |
| 4446 | case LoongArch::VFRINTRP_S: |
| 4447 | case LoongArch::VFRINTRZ_D: |
| 4448 | case LoongArch::VFRINTRZ_S: |
| 4449 | case LoongArch::VFRINT_D: |
| 4450 | case LoongArch::VFRINT_S: |
| 4451 | case LoongArch::VFRSQRTE_D: |
| 4452 | case LoongArch::VFRSQRTE_S: |
| 4453 | case LoongArch::VFRSQRT_D: |
| 4454 | case LoongArch::VFRSQRT_S: |
| 4455 | case LoongArch::VFSQRT_D: |
| 4456 | case LoongArch::VFSQRT_S: |
| 4457 | case LoongArch::VFTINTH_L_S: |
| 4458 | case LoongArch::VFTINTL_L_S: |
| 4459 | case LoongArch::VFTINTRMH_L_S: |
| 4460 | case LoongArch::VFTINTRML_L_S: |
| 4461 | case LoongArch::VFTINTRM_L_D: |
| 4462 | case LoongArch::VFTINTRM_W_S: |
| 4463 | case LoongArch::VFTINTRNEH_L_S: |
| 4464 | case LoongArch::VFTINTRNEL_L_S: |
| 4465 | case LoongArch::VFTINTRNE_L_D: |
| 4466 | case LoongArch::VFTINTRNE_W_S: |
| 4467 | case LoongArch::VFTINTRPH_L_S: |
| 4468 | case LoongArch::VFTINTRPL_L_S: |
| 4469 | case LoongArch::VFTINTRP_L_D: |
| 4470 | case LoongArch::VFTINTRP_W_S: |
| 4471 | case LoongArch::VFTINTRZH_L_S: |
| 4472 | case LoongArch::VFTINTRZL_L_S: |
| 4473 | case LoongArch::VFTINTRZ_LU_D: |
| 4474 | case LoongArch::VFTINTRZ_L_D: |
| 4475 | case LoongArch::VFTINTRZ_WU_S: |
| 4476 | case LoongArch::VFTINTRZ_W_S: |
| 4477 | case LoongArch::VFTINT_LU_D: |
| 4478 | case LoongArch::VFTINT_L_D: |
| 4479 | case LoongArch::VFTINT_WU_S: |
| 4480 | case LoongArch::VFTINT_W_S: |
| 4481 | case LoongArch::VMSKGEZ_B: |
| 4482 | case LoongArch::VMSKLTZ_B: |
| 4483 | case LoongArch::VMSKLTZ_D: |
| 4484 | case LoongArch::VMSKLTZ_H: |
| 4485 | case LoongArch::VMSKLTZ_W: |
| 4486 | case LoongArch::VMSKNZ_B: |
| 4487 | case LoongArch::VNEG_B: |
| 4488 | case LoongArch::VNEG_D: |
| 4489 | case LoongArch::VNEG_H: |
| 4490 | case LoongArch::VNEG_W: |
| 4491 | case LoongArch::VPCNT_B: |
| 4492 | case LoongArch::VPCNT_D: |
| 4493 | case LoongArch::VPCNT_H: |
| 4494 | case LoongArch::VPCNT_W: { |
| 4495 | // op: vj |
| 4496 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4497 | Value |= (op & 0x1f) << 5; |
| 4498 | // op: vd |
| 4499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4500 | Value |= (op & 0x1f); |
| 4501 | break; |
| 4502 | } |
| 4503 | case LoongArch::VABSD_B: |
| 4504 | case LoongArch::VABSD_BU: |
| 4505 | case LoongArch::VABSD_D: |
| 4506 | case LoongArch::VABSD_DU: |
| 4507 | case LoongArch::VABSD_H: |
| 4508 | case LoongArch::VABSD_HU: |
| 4509 | case LoongArch::VABSD_W: |
| 4510 | case LoongArch::VABSD_WU: |
| 4511 | case LoongArch::VADDA_B: |
| 4512 | case LoongArch::VADDA_D: |
| 4513 | case LoongArch::VADDA_H: |
| 4514 | case LoongArch::VADDA_W: |
| 4515 | case LoongArch::VADDWEV_D_W: |
| 4516 | case LoongArch::VADDWEV_D_WU: |
| 4517 | case LoongArch::VADDWEV_D_WU_W: |
| 4518 | case LoongArch::VADDWEV_H_B: |
| 4519 | case LoongArch::VADDWEV_H_BU: |
| 4520 | case LoongArch::VADDWEV_H_BU_B: |
| 4521 | case LoongArch::VADDWEV_Q_D: |
| 4522 | case LoongArch::VADDWEV_Q_DU: |
| 4523 | case LoongArch::VADDWEV_Q_DU_D: |
| 4524 | case LoongArch::VADDWEV_W_H: |
| 4525 | case LoongArch::VADDWEV_W_HU: |
| 4526 | case LoongArch::VADDWEV_W_HU_H: |
| 4527 | case LoongArch::VADDWOD_D_W: |
| 4528 | case LoongArch::VADDWOD_D_WU: |
| 4529 | case LoongArch::VADDWOD_D_WU_W: |
| 4530 | case LoongArch::VADDWOD_H_B: |
| 4531 | case LoongArch::VADDWOD_H_BU: |
| 4532 | case LoongArch::VADDWOD_H_BU_B: |
| 4533 | case LoongArch::VADDWOD_Q_D: |
| 4534 | case LoongArch::VADDWOD_Q_DU: |
| 4535 | case LoongArch::VADDWOD_Q_DU_D: |
| 4536 | case LoongArch::VADDWOD_W_H: |
| 4537 | case LoongArch::VADDWOD_W_HU: |
| 4538 | case LoongArch::VADDWOD_W_HU_H: |
| 4539 | case LoongArch::VADD_B: |
| 4540 | case LoongArch::VADD_D: |
| 4541 | case LoongArch::VADD_H: |
| 4542 | case LoongArch::VADD_Q: |
| 4543 | case LoongArch::VADD_W: |
| 4544 | case LoongArch::VANDN_V: |
| 4545 | case LoongArch::VAND_V: |
| 4546 | case LoongArch::VAVGR_B: |
| 4547 | case LoongArch::VAVGR_BU: |
| 4548 | case LoongArch::VAVGR_D: |
| 4549 | case LoongArch::VAVGR_DU: |
| 4550 | case LoongArch::VAVGR_H: |
| 4551 | case LoongArch::VAVGR_HU: |
| 4552 | case LoongArch::VAVGR_W: |
| 4553 | case LoongArch::VAVGR_WU: |
| 4554 | case LoongArch::VAVG_B: |
| 4555 | case LoongArch::VAVG_BU: |
| 4556 | case LoongArch::VAVG_D: |
| 4557 | case LoongArch::VAVG_DU: |
| 4558 | case LoongArch::VAVG_H: |
| 4559 | case LoongArch::VAVG_HU: |
| 4560 | case LoongArch::VAVG_W: |
| 4561 | case LoongArch::VAVG_WU: |
| 4562 | case LoongArch::VBITCLR_B: |
| 4563 | case LoongArch::VBITCLR_D: |
| 4564 | case LoongArch::VBITCLR_H: |
| 4565 | case LoongArch::VBITCLR_W: |
| 4566 | case LoongArch::VBITREV_B: |
| 4567 | case LoongArch::VBITREV_D: |
| 4568 | case LoongArch::VBITREV_H: |
| 4569 | case LoongArch::VBITREV_W: |
| 4570 | case LoongArch::VBITSET_B: |
| 4571 | case LoongArch::VBITSET_D: |
| 4572 | case LoongArch::VBITSET_H: |
| 4573 | case LoongArch::VBITSET_W: |
| 4574 | case LoongArch::VDIV_B: |
| 4575 | case LoongArch::VDIV_BU: |
| 4576 | case LoongArch::VDIV_D: |
| 4577 | case LoongArch::VDIV_DU: |
| 4578 | case LoongArch::VDIV_H: |
| 4579 | case LoongArch::VDIV_HU: |
| 4580 | case LoongArch::VDIV_W: |
| 4581 | case LoongArch::VDIV_WU: |
| 4582 | case LoongArch::VFADD_D: |
| 4583 | case LoongArch::VFADD_S: |
| 4584 | case LoongArch::VFCMP_CAF_D: |
| 4585 | case LoongArch::VFCMP_CAF_S: |
| 4586 | case LoongArch::VFCMP_CEQ_D: |
| 4587 | case LoongArch::VFCMP_CEQ_S: |
| 4588 | case LoongArch::VFCMP_CLE_D: |
| 4589 | case LoongArch::VFCMP_CLE_S: |
| 4590 | case LoongArch::VFCMP_CLT_D: |
| 4591 | case LoongArch::VFCMP_CLT_S: |
| 4592 | case LoongArch::VFCMP_CNE_D: |
| 4593 | case LoongArch::VFCMP_CNE_S: |
| 4594 | case LoongArch::VFCMP_COR_D: |
| 4595 | case LoongArch::VFCMP_COR_S: |
| 4596 | case LoongArch::VFCMP_CUEQ_D: |
| 4597 | case LoongArch::VFCMP_CUEQ_S: |
| 4598 | case LoongArch::VFCMP_CULE_D: |
| 4599 | case LoongArch::VFCMP_CULE_S: |
| 4600 | case LoongArch::VFCMP_CULT_D: |
| 4601 | case LoongArch::VFCMP_CULT_S: |
| 4602 | case LoongArch::VFCMP_CUNE_D: |
| 4603 | case LoongArch::VFCMP_CUNE_S: |
| 4604 | case LoongArch::VFCMP_CUN_D: |
| 4605 | case LoongArch::VFCMP_CUN_S: |
| 4606 | case LoongArch::VFCMP_SAF_D: |
| 4607 | case LoongArch::VFCMP_SAF_S: |
| 4608 | case LoongArch::VFCMP_SEQ_D: |
| 4609 | case LoongArch::VFCMP_SEQ_S: |
| 4610 | case LoongArch::VFCMP_SLE_D: |
| 4611 | case LoongArch::VFCMP_SLE_S: |
| 4612 | case LoongArch::VFCMP_SLT_D: |
| 4613 | case LoongArch::VFCMP_SLT_S: |
| 4614 | case LoongArch::VFCMP_SNE_D: |
| 4615 | case LoongArch::VFCMP_SNE_S: |
| 4616 | case LoongArch::VFCMP_SOR_D: |
| 4617 | case LoongArch::VFCMP_SOR_S: |
| 4618 | case LoongArch::VFCMP_SUEQ_D: |
| 4619 | case LoongArch::VFCMP_SUEQ_S: |
| 4620 | case LoongArch::VFCMP_SULE_D: |
| 4621 | case LoongArch::VFCMP_SULE_S: |
| 4622 | case LoongArch::VFCMP_SULT_D: |
| 4623 | case LoongArch::VFCMP_SULT_S: |
| 4624 | case LoongArch::VFCMP_SUNE_D: |
| 4625 | case LoongArch::VFCMP_SUNE_S: |
| 4626 | case LoongArch::VFCMP_SUN_D: |
| 4627 | case LoongArch::VFCMP_SUN_S: |
| 4628 | case LoongArch::VFCVT_H_S: |
| 4629 | case LoongArch::VFCVT_S_D: |
| 4630 | case LoongArch::VFDIV_D: |
| 4631 | case LoongArch::VFDIV_S: |
| 4632 | case LoongArch::VFFINT_S_L: |
| 4633 | case LoongArch::VFMAXA_D: |
| 4634 | case LoongArch::VFMAXA_S: |
| 4635 | case LoongArch::VFMAX_D: |
| 4636 | case LoongArch::VFMAX_S: |
| 4637 | case LoongArch::VFMINA_D: |
| 4638 | case LoongArch::VFMINA_S: |
| 4639 | case LoongArch::VFMIN_D: |
| 4640 | case LoongArch::VFMIN_S: |
| 4641 | case LoongArch::VFMUL_D: |
| 4642 | case LoongArch::VFMUL_S: |
| 4643 | case LoongArch::VFSUB_D: |
| 4644 | case LoongArch::VFSUB_S: |
| 4645 | case LoongArch::VFTINTRM_W_D: |
| 4646 | case LoongArch::VFTINTRNE_W_D: |
| 4647 | case LoongArch::VFTINTRP_W_D: |
| 4648 | case LoongArch::VFTINTRZ_W_D: |
| 4649 | case LoongArch::VFTINT_W_D: |
| 4650 | case LoongArch::VHADDW_DU_WU: |
| 4651 | case LoongArch::VHADDW_D_W: |
| 4652 | case LoongArch::VHADDW_HU_BU: |
| 4653 | case LoongArch::VHADDW_H_B: |
| 4654 | case LoongArch::VHADDW_QU_DU: |
| 4655 | case LoongArch::VHADDW_Q_D: |
| 4656 | case LoongArch::VHADDW_WU_HU: |
| 4657 | case LoongArch::VHADDW_W_H: |
| 4658 | case LoongArch::VHSUBW_DU_WU: |
| 4659 | case LoongArch::VHSUBW_D_W: |
| 4660 | case LoongArch::VHSUBW_HU_BU: |
| 4661 | case LoongArch::VHSUBW_H_B: |
| 4662 | case LoongArch::VHSUBW_QU_DU: |
| 4663 | case LoongArch::VHSUBW_Q_D: |
| 4664 | case LoongArch::VHSUBW_WU_HU: |
| 4665 | case LoongArch::VHSUBW_W_H: |
| 4666 | case LoongArch::VILVH_B: |
| 4667 | case LoongArch::VILVH_D: |
| 4668 | case LoongArch::VILVH_H: |
| 4669 | case LoongArch::VILVH_W: |
| 4670 | case LoongArch::VILVL_B: |
| 4671 | case LoongArch::VILVL_D: |
| 4672 | case LoongArch::VILVL_H: |
| 4673 | case LoongArch::VILVL_W: |
| 4674 | case LoongArch::VMAX_B: |
| 4675 | case LoongArch::VMAX_BU: |
| 4676 | case LoongArch::VMAX_D: |
| 4677 | case LoongArch::VMAX_DU: |
| 4678 | case LoongArch::VMAX_H: |
| 4679 | case LoongArch::VMAX_HU: |
| 4680 | case LoongArch::VMAX_W: |
| 4681 | case LoongArch::VMAX_WU: |
| 4682 | case LoongArch::VMIN_B: |
| 4683 | case LoongArch::VMIN_BU: |
| 4684 | case LoongArch::VMIN_D: |
| 4685 | case LoongArch::VMIN_DU: |
| 4686 | case LoongArch::VMIN_H: |
| 4687 | case LoongArch::VMIN_HU: |
| 4688 | case LoongArch::VMIN_W: |
| 4689 | case LoongArch::VMIN_WU: |
| 4690 | case LoongArch::VMOD_B: |
| 4691 | case LoongArch::VMOD_BU: |
| 4692 | case LoongArch::VMOD_D: |
| 4693 | case LoongArch::VMOD_DU: |
| 4694 | case LoongArch::VMOD_H: |
| 4695 | case LoongArch::VMOD_HU: |
| 4696 | case LoongArch::VMOD_W: |
| 4697 | case LoongArch::VMOD_WU: |
| 4698 | case LoongArch::VMUH_B: |
| 4699 | case LoongArch::VMUH_BU: |
| 4700 | case LoongArch::VMUH_D: |
| 4701 | case LoongArch::VMUH_DU: |
| 4702 | case LoongArch::VMUH_H: |
| 4703 | case LoongArch::VMUH_HU: |
| 4704 | case LoongArch::VMUH_W: |
| 4705 | case LoongArch::VMUH_WU: |
| 4706 | case LoongArch::VMULWEV_D_W: |
| 4707 | case LoongArch::VMULWEV_D_WU: |
| 4708 | case LoongArch::VMULWEV_D_WU_W: |
| 4709 | case LoongArch::VMULWEV_H_B: |
| 4710 | case LoongArch::VMULWEV_H_BU: |
| 4711 | case LoongArch::VMULWEV_H_BU_B: |
| 4712 | case LoongArch::VMULWEV_Q_D: |
| 4713 | case LoongArch::VMULWEV_Q_DU: |
| 4714 | case LoongArch::VMULWEV_Q_DU_D: |
| 4715 | case LoongArch::VMULWEV_W_H: |
| 4716 | case LoongArch::VMULWEV_W_HU: |
| 4717 | case LoongArch::VMULWEV_W_HU_H: |
| 4718 | case LoongArch::VMULWOD_D_W: |
| 4719 | case LoongArch::VMULWOD_D_WU: |
| 4720 | case LoongArch::VMULWOD_D_WU_W: |
| 4721 | case LoongArch::VMULWOD_H_B: |
| 4722 | case LoongArch::VMULWOD_H_BU: |
| 4723 | case LoongArch::VMULWOD_H_BU_B: |
| 4724 | case LoongArch::VMULWOD_Q_D: |
| 4725 | case LoongArch::VMULWOD_Q_DU: |
| 4726 | case LoongArch::VMULWOD_Q_DU_D: |
| 4727 | case LoongArch::VMULWOD_W_H: |
| 4728 | case LoongArch::VMULWOD_W_HU: |
| 4729 | case LoongArch::VMULWOD_W_HU_H: |
| 4730 | case LoongArch::VMUL_B: |
| 4731 | case LoongArch::VMUL_D: |
| 4732 | case LoongArch::VMUL_H: |
| 4733 | case LoongArch::VMUL_W: |
| 4734 | case LoongArch::VNOR_V: |
| 4735 | case LoongArch::VORN_V: |
| 4736 | case LoongArch::VOR_V: |
| 4737 | case LoongArch::VPACKEV_B: |
| 4738 | case LoongArch::VPACKEV_D: |
| 4739 | case LoongArch::VPACKEV_H: |
| 4740 | case LoongArch::VPACKEV_W: |
| 4741 | case LoongArch::VPACKOD_B: |
| 4742 | case LoongArch::VPACKOD_D: |
| 4743 | case LoongArch::VPACKOD_H: |
| 4744 | case LoongArch::VPACKOD_W: |
| 4745 | case LoongArch::VPICKEV_B: |
| 4746 | case LoongArch::VPICKEV_D: |
| 4747 | case LoongArch::VPICKEV_H: |
| 4748 | case LoongArch::VPICKEV_W: |
| 4749 | case LoongArch::VPICKOD_B: |
| 4750 | case LoongArch::VPICKOD_D: |
| 4751 | case LoongArch::VPICKOD_H: |
| 4752 | case LoongArch::VPICKOD_W: |
| 4753 | case LoongArch::VROTR_B: |
| 4754 | case LoongArch::VROTR_D: |
| 4755 | case LoongArch::VROTR_H: |
| 4756 | case LoongArch::VROTR_W: |
| 4757 | case LoongArch::VSADD_B: |
| 4758 | case LoongArch::VSADD_BU: |
| 4759 | case LoongArch::VSADD_D: |
| 4760 | case LoongArch::VSADD_DU: |
| 4761 | case LoongArch::VSADD_H: |
| 4762 | case LoongArch::VSADD_HU: |
| 4763 | case LoongArch::VSADD_W: |
| 4764 | case LoongArch::VSADD_WU: |
| 4765 | case LoongArch::VSEQ_B: |
| 4766 | case LoongArch::VSEQ_D: |
| 4767 | case LoongArch::VSEQ_H: |
| 4768 | case LoongArch::VSEQ_W: |
| 4769 | case LoongArch::VSIGNCOV_B: |
| 4770 | case LoongArch::VSIGNCOV_D: |
| 4771 | case LoongArch::VSIGNCOV_H: |
| 4772 | case LoongArch::VSIGNCOV_W: |
| 4773 | case LoongArch::VSLE_B: |
| 4774 | case LoongArch::VSLE_BU: |
| 4775 | case LoongArch::VSLE_D: |
| 4776 | case LoongArch::VSLE_DU: |
| 4777 | case LoongArch::VSLE_H: |
| 4778 | case LoongArch::VSLE_HU: |
| 4779 | case LoongArch::VSLE_W: |
| 4780 | case LoongArch::VSLE_WU: |
| 4781 | case LoongArch::VSLL_B: |
| 4782 | case LoongArch::VSLL_D: |
| 4783 | case LoongArch::VSLL_H: |
| 4784 | case LoongArch::VSLL_W: |
| 4785 | case LoongArch::VSLT_B: |
| 4786 | case LoongArch::VSLT_BU: |
| 4787 | case LoongArch::VSLT_D: |
| 4788 | case LoongArch::VSLT_DU: |
| 4789 | case LoongArch::VSLT_H: |
| 4790 | case LoongArch::VSLT_HU: |
| 4791 | case LoongArch::VSLT_W: |
| 4792 | case LoongArch::VSLT_WU: |
| 4793 | case LoongArch::VSRAN_B_H: |
| 4794 | case LoongArch::VSRAN_H_W: |
| 4795 | case LoongArch::VSRAN_W_D: |
| 4796 | case LoongArch::VSRARN_B_H: |
| 4797 | case LoongArch::VSRARN_H_W: |
| 4798 | case LoongArch::VSRARN_W_D: |
| 4799 | case LoongArch::VSRAR_B: |
| 4800 | case LoongArch::VSRAR_D: |
| 4801 | case LoongArch::VSRAR_H: |
| 4802 | case LoongArch::VSRAR_W: |
| 4803 | case LoongArch::VSRA_B: |
| 4804 | case LoongArch::VSRA_D: |
| 4805 | case LoongArch::VSRA_H: |
| 4806 | case LoongArch::VSRA_W: |
| 4807 | case LoongArch::VSRLN_B_H: |
| 4808 | case LoongArch::VSRLN_H_W: |
| 4809 | case LoongArch::VSRLN_W_D: |
| 4810 | case LoongArch::VSRLRN_B_H: |
| 4811 | case LoongArch::VSRLRN_H_W: |
| 4812 | case LoongArch::VSRLRN_W_D: |
| 4813 | case LoongArch::VSRLR_B: |
| 4814 | case LoongArch::VSRLR_D: |
| 4815 | case LoongArch::VSRLR_H: |
| 4816 | case LoongArch::VSRLR_W: |
| 4817 | case LoongArch::VSRL_B: |
| 4818 | case LoongArch::VSRL_D: |
| 4819 | case LoongArch::VSRL_H: |
| 4820 | case LoongArch::VSRL_W: |
| 4821 | case LoongArch::VSSRAN_BU_H: |
| 4822 | case LoongArch::VSSRAN_B_H: |
| 4823 | case LoongArch::VSSRAN_HU_W: |
| 4824 | case LoongArch::VSSRAN_H_W: |
| 4825 | case LoongArch::VSSRAN_WU_D: |
| 4826 | case LoongArch::VSSRAN_W_D: |
| 4827 | case LoongArch::VSSRARN_BU_H: |
| 4828 | case LoongArch::VSSRARN_B_H: |
| 4829 | case LoongArch::VSSRARN_HU_W: |
| 4830 | case LoongArch::VSSRARN_H_W: |
| 4831 | case LoongArch::VSSRARN_WU_D: |
| 4832 | case LoongArch::VSSRARN_W_D: |
| 4833 | case LoongArch::VSSRLN_BU_H: |
| 4834 | case LoongArch::VSSRLN_B_H: |
| 4835 | case LoongArch::VSSRLN_HU_W: |
| 4836 | case LoongArch::VSSRLN_H_W: |
| 4837 | case LoongArch::VSSRLN_WU_D: |
| 4838 | case LoongArch::VSSRLN_W_D: |
| 4839 | case LoongArch::VSSRLRN_BU_H: |
| 4840 | case LoongArch::VSSRLRN_B_H: |
| 4841 | case LoongArch::VSSRLRN_HU_W: |
| 4842 | case LoongArch::VSSRLRN_H_W: |
| 4843 | case LoongArch::VSSRLRN_WU_D: |
| 4844 | case LoongArch::VSSRLRN_W_D: |
| 4845 | case LoongArch::VSSUB_B: |
| 4846 | case LoongArch::VSSUB_BU: |
| 4847 | case LoongArch::VSSUB_D: |
| 4848 | case LoongArch::VSSUB_DU: |
| 4849 | case LoongArch::VSSUB_H: |
| 4850 | case LoongArch::VSSUB_HU: |
| 4851 | case LoongArch::VSSUB_W: |
| 4852 | case LoongArch::VSSUB_WU: |
| 4853 | case LoongArch::VSUBWEV_D_W: |
| 4854 | case LoongArch::VSUBWEV_D_WU: |
| 4855 | case LoongArch::VSUBWEV_H_B: |
| 4856 | case LoongArch::VSUBWEV_H_BU: |
| 4857 | case LoongArch::VSUBWEV_Q_D: |
| 4858 | case LoongArch::VSUBWEV_Q_DU: |
| 4859 | case LoongArch::VSUBWEV_W_H: |
| 4860 | case LoongArch::VSUBWEV_W_HU: |
| 4861 | case LoongArch::VSUBWOD_D_W: |
| 4862 | case LoongArch::VSUBWOD_D_WU: |
| 4863 | case LoongArch::VSUBWOD_H_B: |
| 4864 | case LoongArch::VSUBWOD_H_BU: |
| 4865 | case LoongArch::VSUBWOD_Q_D: |
| 4866 | case LoongArch::VSUBWOD_Q_DU: |
| 4867 | case LoongArch::VSUBWOD_W_H: |
| 4868 | case LoongArch::VSUBWOD_W_HU: |
| 4869 | case LoongArch::VSUB_B: |
| 4870 | case LoongArch::VSUB_D: |
| 4871 | case LoongArch::VSUB_H: |
| 4872 | case LoongArch::VSUB_Q: |
| 4873 | case LoongArch::VSUB_W: |
| 4874 | case LoongArch::VXOR_V: { |
| 4875 | // op: vk |
| 4876 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4877 | Value |= (op & 0x1f) << 10; |
| 4878 | // op: vj |
| 4879 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4880 | Value |= (op & 0x1f) << 5; |
| 4881 | // op: vd |
| 4882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4883 | Value |= (op & 0x1f); |
| 4884 | break; |
| 4885 | } |
| 4886 | case LoongArch::VFRSTP_B: |
| 4887 | case LoongArch::VFRSTP_H: |
| 4888 | case LoongArch::VMADDWEV_D_W: |
| 4889 | case LoongArch::VMADDWEV_D_WU: |
| 4890 | case LoongArch::VMADDWEV_D_WU_W: |
| 4891 | case LoongArch::VMADDWEV_H_B: |
| 4892 | case LoongArch::VMADDWEV_H_BU: |
| 4893 | case LoongArch::VMADDWEV_H_BU_B: |
| 4894 | case LoongArch::VMADDWEV_Q_D: |
| 4895 | case LoongArch::VMADDWEV_Q_DU: |
| 4896 | case LoongArch::VMADDWEV_Q_DU_D: |
| 4897 | case LoongArch::VMADDWEV_W_H: |
| 4898 | case LoongArch::VMADDWEV_W_HU: |
| 4899 | case LoongArch::VMADDWEV_W_HU_H: |
| 4900 | case LoongArch::VMADDWOD_D_W: |
| 4901 | case LoongArch::VMADDWOD_D_WU: |
| 4902 | case LoongArch::VMADDWOD_D_WU_W: |
| 4903 | case LoongArch::VMADDWOD_H_B: |
| 4904 | case LoongArch::VMADDWOD_H_BU: |
| 4905 | case LoongArch::VMADDWOD_H_BU_B: |
| 4906 | case LoongArch::VMADDWOD_Q_D: |
| 4907 | case LoongArch::VMADDWOD_Q_DU: |
| 4908 | case LoongArch::VMADDWOD_Q_DU_D: |
| 4909 | case LoongArch::VMADDWOD_W_H: |
| 4910 | case LoongArch::VMADDWOD_W_HU: |
| 4911 | case LoongArch::VMADDWOD_W_HU_H: |
| 4912 | case LoongArch::VMADD_B: |
| 4913 | case LoongArch::VMADD_D: |
| 4914 | case LoongArch::VMADD_H: |
| 4915 | case LoongArch::VMADD_W: |
| 4916 | case LoongArch::VMSUB_B: |
| 4917 | case LoongArch::VMSUB_D: |
| 4918 | case LoongArch::VMSUB_H: |
| 4919 | case LoongArch::VMSUB_W: |
| 4920 | case LoongArch::VSHUF_D: |
| 4921 | case LoongArch::VSHUF_H: |
| 4922 | case LoongArch::VSHUF_W: { |
| 4923 | // op: vk |
| 4924 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4925 | Value |= (op & 0x1f) << 10; |
| 4926 | // op: vj |
| 4927 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4928 | Value |= (op & 0x1f) << 5; |
| 4929 | // op: vd |
| 4930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4931 | Value |= (op & 0x1f); |
| 4932 | break; |
| 4933 | } |
| 4934 | case LoongArch::XVBITSEL_V: |
| 4935 | case LoongArch::XVFMADD_D: |
| 4936 | case LoongArch::XVFMADD_S: |
| 4937 | case LoongArch::XVFMSUB_D: |
| 4938 | case LoongArch::XVFMSUB_S: |
| 4939 | case LoongArch::XVFNMADD_D: |
| 4940 | case LoongArch::XVFNMADD_S: |
| 4941 | case LoongArch::XVFNMSUB_D: |
| 4942 | case LoongArch::XVFNMSUB_S: |
| 4943 | case LoongArch::XVSHUF_B: { |
| 4944 | // op: xa |
| 4945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4946 | Value |= (op & 0x1f) << 15; |
| 4947 | // op: xk |
| 4948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4949 | Value |= (op & 0x1f) << 10; |
| 4950 | // op: xj |
| 4951 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4952 | Value |= (op & 0x1f) << 5; |
| 4953 | // op: xd |
| 4954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4955 | Value |= (op & 0x1f); |
| 4956 | break; |
| 4957 | } |
| 4958 | case LoongArch::XVSETALLNEZ_B: |
| 4959 | case LoongArch::XVSETALLNEZ_D: |
| 4960 | case LoongArch::XVSETALLNEZ_H: |
| 4961 | case LoongArch::XVSETALLNEZ_W: |
| 4962 | case LoongArch::XVSETANYEQZ_B: |
| 4963 | case LoongArch::XVSETANYEQZ_D: |
| 4964 | case LoongArch::XVSETANYEQZ_H: |
| 4965 | case LoongArch::XVSETANYEQZ_W: |
| 4966 | case LoongArch::XVSETEQZ_V: |
| 4967 | case LoongArch::XVSETNEZ_V: { |
| 4968 | // op: xj |
| 4969 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4970 | Value |= (op & 0x1f) << 5; |
| 4971 | // op: cd |
| 4972 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4973 | Value |= (op & 0x7); |
| 4974 | break; |
| 4975 | } |
| 4976 | case LoongArch::VEXT2XV_DU_BU: |
| 4977 | case LoongArch::VEXT2XV_DU_HU: |
| 4978 | case LoongArch::VEXT2XV_DU_WU: |
| 4979 | case LoongArch::VEXT2XV_D_B: |
| 4980 | case LoongArch::VEXT2XV_D_H: |
| 4981 | case LoongArch::VEXT2XV_D_W: |
| 4982 | case LoongArch::VEXT2XV_HU_BU: |
| 4983 | case LoongArch::VEXT2XV_H_B: |
| 4984 | case LoongArch::VEXT2XV_WU_BU: |
| 4985 | case LoongArch::VEXT2XV_WU_HU: |
| 4986 | case LoongArch::VEXT2XV_W_B: |
| 4987 | case LoongArch::VEXT2XV_W_H: |
| 4988 | case LoongArch::XVCLO_B: |
| 4989 | case LoongArch::XVCLO_D: |
| 4990 | case LoongArch::XVCLO_H: |
| 4991 | case LoongArch::XVCLO_W: |
| 4992 | case LoongArch::XVCLZ_B: |
| 4993 | case LoongArch::XVCLZ_D: |
| 4994 | case LoongArch::XVCLZ_H: |
| 4995 | case LoongArch::XVCLZ_W: |
| 4996 | case LoongArch::XVEXTH_DU_WU: |
| 4997 | case LoongArch::XVEXTH_D_W: |
| 4998 | case LoongArch::XVEXTH_HU_BU: |
| 4999 | case LoongArch::XVEXTH_H_B: |
| 5000 | case LoongArch::XVEXTH_QU_DU: |
| 5001 | case LoongArch::XVEXTH_Q_D: |
| 5002 | case LoongArch::XVEXTH_WU_HU: |
| 5003 | case LoongArch::XVEXTH_W_H: |
| 5004 | case LoongArch::XVEXTL_QU_DU: |
| 5005 | case LoongArch::XVEXTL_Q_D: |
| 5006 | case LoongArch::XVFCLASS_D: |
| 5007 | case LoongArch::XVFCLASS_S: |
| 5008 | case LoongArch::XVFCVTH_D_S: |
| 5009 | case LoongArch::XVFCVTH_S_H: |
| 5010 | case LoongArch::XVFCVTL_D_S: |
| 5011 | case LoongArch::XVFCVTL_S_H: |
| 5012 | case LoongArch::XVFFINTH_D_W: |
| 5013 | case LoongArch::XVFFINTL_D_W: |
| 5014 | case LoongArch::XVFFINT_D_L: |
| 5015 | case LoongArch::XVFFINT_D_LU: |
| 5016 | case LoongArch::XVFFINT_S_W: |
| 5017 | case LoongArch::XVFFINT_S_WU: |
| 5018 | case LoongArch::XVFLOGB_D: |
| 5019 | case LoongArch::XVFLOGB_S: |
| 5020 | case LoongArch::XVFRECIPE_D: |
| 5021 | case LoongArch::XVFRECIPE_S: |
| 5022 | case LoongArch::XVFRECIP_D: |
| 5023 | case LoongArch::XVFRECIP_S: |
| 5024 | case LoongArch::XVFRINTRM_D: |
| 5025 | case LoongArch::XVFRINTRM_S: |
| 5026 | case LoongArch::XVFRINTRNE_D: |
| 5027 | case LoongArch::XVFRINTRNE_S: |
| 5028 | case LoongArch::XVFRINTRP_D: |
| 5029 | case LoongArch::XVFRINTRP_S: |
| 5030 | case LoongArch::XVFRINTRZ_D: |
| 5031 | case LoongArch::XVFRINTRZ_S: |
| 5032 | case LoongArch::XVFRINT_D: |
| 5033 | case LoongArch::XVFRINT_S: |
| 5034 | case LoongArch::XVFRSQRTE_D: |
| 5035 | case LoongArch::XVFRSQRTE_S: |
| 5036 | case LoongArch::XVFRSQRT_D: |
| 5037 | case LoongArch::XVFRSQRT_S: |
| 5038 | case LoongArch::XVFSQRT_D: |
| 5039 | case LoongArch::XVFSQRT_S: |
| 5040 | case LoongArch::XVFTINTH_L_S: |
| 5041 | case LoongArch::XVFTINTL_L_S: |
| 5042 | case LoongArch::XVFTINTRMH_L_S: |
| 5043 | case LoongArch::XVFTINTRML_L_S: |
| 5044 | case LoongArch::XVFTINTRM_L_D: |
| 5045 | case LoongArch::XVFTINTRM_W_S: |
| 5046 | case LoongArch::XVFTINTRNEH_L_S: |
| 5047 | case LoongArch::XVFTINTRNEL_L_S: |
| 5048 | case LoongArch::XVFTINTRNE_L_D: |
| 5049 | case LoongArch::XVFTINTRNE_W_S: |
| 5050 | case LoongArch::XVFTINTRPH_L_S: |
| 5051 | case LoongArch::XVFTINTRPL_L_S: |
| 5052 | case LoongArch::XVFTINTRP_L_D: |
| 5053 | case LoongArch::XVFTINTRP_W_S: |
| 5054 | case LoongArch::XVFTINTRZH_L_S: |
| 5055 | case LoongArch::XVFTINTRZL_L_S: |
| 5056 | case LoongArch::XVFTINTRZ_LU_D: |
| 5057 | case LoongArch::XVFTINTRZ_L_D: |
| 5058 | case LoongArch::XVFTINTRZ_WU_S: |
| 5059 | case LoongArch::XVFTINTRZ_W_S: |
| 5060 | case LoongArch::XVFTINT_LU_D: |
| 5061 | case LoongArch::XVFTINT_L_D: |
| 5062 | case LoongArch::XVFTINT_WU_S: |
| 5063 | case LoongArch::XVFTINT_W_S: |
| 5064 | case LoongArch::XVMSKGEZ_B: |
| 5065 | case LoongArch::XVMSKLTZ_B: |
| 5066 | case LoongArch::XVMSKLTZ_D: |
| 5067 | case LoongArch::XVMSKLTZ_H: |
| 5068 | case LoongArch::XVMSKLTZ_W: |
| 5069 | case LoongArch::XVMSKNZ_B: |
| 5070 | case LoongArch::XVNEG_B: |
| 5071 | case LoongArch::XVNEG_D: |
| 5072 | case LoongArch::XVNEG_H: |
| 5073 | case LoongArch::XVNEG_W: |
| 5074 | case LoongArch::XVPCNT_B: |
| 5075 | case LoongArch::XVPCNT_D: |
| 5076 | case LoongArch::XVPCNT_H: |
| 5077 | case LoongArch::XVPCNT_W: |
| 5078 | case LoongArch::XVREPLVE0_B: |
| 5079 | case LoongArch::XVREPLVE0_D: |
| 5080 | case LoongArch::XVREPLVE0_H: |
| 5081 | case LoongArch::XVREPLVE0_Q: |
| 5082 | case LoongArch::XVREPLVE0_W: { |
| 5083 | // op: xj |
| 5084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5085 | Value |= (op & 0x1f) << 5; |
| 5086 | // op: xd |
| 5087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5088 | Value |= (op & 0x1f); |
| 5089 | break; |
| 5090 | } |
| 5091 | case LoongArch::XVABSD_B: |
| 5092 | case LoongArch::XVABSD_BU: |
| 5093 | case LoongArch::XVABSD_D: |
| 5094 | case LoongArch::XVABSD_DU: |
| 5095 | case LoongArch::XVABSD_H: |
| 5096 | case LoongArch::XVABSD_HU: |
| 5097 | case LoongArch::XVABSD_W: |
| 5098 | case LoongArch::XVABSD_WU: |
| 5099 | case LoongArch::XVADDA_B: |
| 5100 | case LoongArch::XVADDA_D: |
| 5101 | case LoongArch::XVADDA_H: |
| 5102 | case LoongArch::XVADDA_W: |
| 5103 | case LoongArch::XVADDWEV_D_W: |
| 5104 | case LoongArch::XVADDWEV_D_WU: |
| 5105 | case LoongArch::XVADDWEV_D_WU_W: |
| 5106 | case LoongArch::XVADDWEV_H_B: |
| 5107 | case LoongArch::XVADDWEV_H_BU: |
| 5108 | case LoongArch::XVADDWEV_H_BU_B: |
| 5109 | case LoongArch::XVADDWEV_Q_D: |
| 5110 | case LoongArch::XVADDWEV_Q_DU: |
| 5111 | case LoongArch::XVADDWEV_Q_DU_D: |
| 5112 | case LoongArch::XVADDWEV_W_H: |
| 5113 | case LoongArch::XVADDWEV_W_HU: |
| 5114 | case LoongArch::XVADDWEV_W_HU_H: |
| 5115 | case LoongArch::XVADDWOD_D_W: |
| 5116 | case LoongArch::XVADDWOD_D_WU: |
| 5117 | case LoongArch::XVADDWOD_D_WU_W: |
| 5118 | case LoongArch::XVADDWOD_H_B: |
| 5119 | case LoongArch::XVADDWOD_H_BU: |
| 5120 | case LoongArch::XVADDWOD_H_BU_B: |
| 5121 | case LoongArch::XVADDWOD_Q_D: |
| 5122 | case LoongArch::XVADDWOD_Q_DU: |
| 5123 | case LoongArch::XVADDWOD_Q_DU_D: |
| 5124 | case LoongArch::XVADDWOD_W_H: |
| 5125 | case LoongArch::XVADDWOD_W_HU: |
| 5126 | case LoongArch::XVADDWOD_W_HU_H: |
| 5127 | case LoongArch::XVADD_B: |
| 5128 | case LoongArch::XVADD_D: |
| 5129 | case LoongArch::XVADD_H: |
| 5130 | case LoongArch::XVADD_Q: |
| 5131 | case LoongArch::XVADD_W: |
| 5132 | case LoongArch::XVANDN_V: |
| 5133 | case LoongArch::XVAND_V: |
| 5134 | case LoongArch::XVAVGR_B: |
| 5135 | case LoongArch::XVAVGR_BU: |
| 5136 | case LoongArch::XVAVGR_D: |
| 5137 | case LoongArch::XVAVGR_DU: |
| 5138 | case LoongArch::XVAVGR_H: |
| 5139 | case LoongArch::XVAVGR_HU: |
| 5140 | case LoongArch::XVAVGR_W: |
| 5141 | case LoongArch::XVAVGR_WU: |
| 5142 | case LoongArch::XVAVG_B: |
| 5143 | case LoongArch::XVAVG_BU: |
| 5144 | case LoongArch::XVAVG_D: |
| 5145 | case LoongArch::XVAVG_DU: |
| 5146 | case LoongArch::XVAVG_H: |
| 5147 | case LoongArch::XVAVG_HU: |
| 5148 | case LoongArch::XVAVG_W: |
| 5149 | case LoongArch::XVAVG_WU: |
| 5150 | case LoongArch::XVBITCLR_B: |
| 5151 | case LoongArch::XVBITCLR_D: |
| 5152 | case LoongArch::XVBITCLR_H: |
| 5153 | case LoongArch::XVBITCLR_W: |
| 5154 | case LoongArch::XVBITREV_B: |
| 5155 | case LoongArch::XVBITREV_D: |
| 5156 | case LoongArch::XVBITREV_H: |
| 5157 | case LoongArch::XVBITREV_W: |
| 5158 | case LoongArch::XVBITSET_B: |
| 5159 | case LoongArch::XVBITSET_D: |
| 5160 | case LoongArch::XVBITSET_H: |
| 5161 | case LoongArch::XVBITSET_W: |
| 5162 | case LoongArch::XVDIV_B: |
| 5163 | case LoongArch::XVDIV_BU: |
| 5164 | case LoongArch::XVDIV_D: |
| 5165 | case LoongArch::XVDIV_DU: |
| 5166 | case LoongArch::XVDIV_H: |
| 5167 | case LoongArch::XVDIV_HU: |
| 5168 | case LoongArch::XVDIV_W: |
| 5169 | case LoongArch::XVDIV_WU: |
| 5170 | case LoongArch::XVFADD_D: |
| 5171 | case LoongArch::XVFADD_S: |
| 5172 | case LoongArch::XVFCMP_CAF_D: |
| 5173 | case LoongArch::XVFCMP_CAF_S: |
| 5174 | case LoongArch::XVFCMP_CEQ_D: |
| 5175 | case LoongArch::XVFCMP_CEQ_S: |
| 5176 | case LoongArch::XVFCMP_CLE_D: |
| 5177 | case LoongArch::XVFCMP_CLE_S: |
| 5178 | case LoongArch::XVFCMP_CLT_D: |
| 5179 | case LoongArch::XVFCMP_CLT_S: |
| 5180 | case LoongArch::XVFCMP_CNE_D: |
| 5181 | case LoongArch::XVFCMP_CNE_S: |
| 5182 | case LoongArch::XVFCMP_COR_D: |
| 5183 | case LoongArch::XVFCMP_COR_S: |
| 5184 | case LoongArch::XVFCMP_CUEQ_D: |
| 5185 | case LoongArch::XVFCMP_CUEQ_S: |
| 5186 | case LoongArch::XVFCMP_CULE_D: |
| 5187 | case LoongArch::XVFCMP_CULE_S: |
| 5188 | case LoongArch::XVFCMP_CULT_D: |
| 5189 | case LoongArch::XVFCMP_CULT_S: |
| 5190 | case LoongArch::XVFCMP_CUNE_D: |
| 5191 | case LoongArch::XVFCMP_CUNE_S: |
| 5192 | case LoongArch::XVFCMP_CUN_D: |
| 5193 | case LoongArch::XVFCMP_CUN_S: |
| 5194 | case LoongArch::XVFCMP_SAF_D: |
| 5195 | case LoongArch::XVFCMP_SAF_S: |
| 5196 | case LoongArch::XVFCMP_SEQ_D: |
| 5197 | case LoongArch::XVFCMP_SEQ_S: |
| 5198 | case LoongArch::XVFCMP_SLE_D: |
| 5199 | case LoongArch::XVFCMP_SLE_S: |
| 5200 | case LoongArch::XVFCMP_SLT_D: |
| 5201 | case LoongArch::XVFCMP_SLT_S: |
| 5202 | case LoongArch::XVFCMP_SNE_D: |
| 5203 | case LoongArch::XVFCMP_SNE_S: |
| 5204 | case LoongArch::XVFCMP_SOR_D: |
| 5205 | case LoongArch::XVFCMP_SOR_S: |
| 5206 | case LoongArch::XVFCMP_SUEQ_D: |
| 5207 | case LoongArch::XVFCMP_SUEQ_S: |
| 5208 | case LoongArch::XVFCMP_SULE_D: |
| 5209 | case LoongArch::XVFCMP_SULE_S: |
| 5210 | case LoongArch::XVFCMP_SULT_D: |
| 5211 | case LoongArch::XVFCMP_SULT_S: |
| 5212 | case LoongArch::XVFCMP_SUNE_D: |
| 5213 | case LoongArch::XVFCMP_SUNE_S: |
| 5214 | case LoongArch::XVFCMP_SUN_D: |
| 5215 | case LoongArch::XVFCMP_SUN_S: |
| 5216 | case LoongArch::XVFCVT_H_S: |
| 5217 | case LoongArch::XVFCVT_S_D: |
| 5218 | case LoongArch::XVFDIV_D: |
| 5219 | case LoongArch::XVFDIV_S: |
| 5220 | case LoongArch::XVFFINT_S_L: |
| 5221 | case LoongArch::XVFMAXA_D: |
| 5222 | case LoongArch::XVFMAXA_S: |
| 5223 | case LoongArch::XVFMAX_D: |
| 5224 | case LoongArch::XVFMAX_S: |
| 5225 | case LoongArch::XVFMINA_D: |
| 5226 | case LoongArch::XVFMINA_S: |
| 5227 | case LoongArch::XVFMIN_D: |
| 5228 | case LoongArch::XVFMIN_S: |
| 5229 | case LoongArch::XVFMUL_D: |
| 5230 | case LoongArch::XVFMUL_S: |
| 5231 | case LoongArch::XVFSUB_D: |
| 5232 | case LoongArch::XVFSUB_S: |
| 5233 | case LoongArch::XVFTINTRM_W_D: |
| 5234 | case LoongArch::XVFTINTRNE_W_D: |
| 5235 | case LoongArch::XVFTINTRP_W_D: |
| 5236 | case LoongArch::XVFTINTRZ_W_D: |
| 5237 | case LoongArch::XVFTINT_W_D: |
| 5238 | case LoongArch::XVHADDW_DU_WU: |
| 5239 | case LoongArch::XVHADDW_D_W: |
| 5240 | case LoongArch::XVHADDW_HU_BU: |
| 5241 | case LoongArch::XVHADDW_H_B: |
| 5242 | case LoongArch::XVHADDW_QU_DU: |
| 5243 | case LoongArch::XVHADDW_Q_D: |
| 5244 | case LoongArch::XVHADDW_WU_HU: |
| 5245 | case LoongArch::XVHADDW_W_H: |
| 5246 | case LoongArch::XVHSUBW_DU_WU: |
| 5247 | case LoongArch::XVHSUBW_D_W: |
| 5248 | case LoongArch::XVHSUBW_HU_BU: |
| 5249 | case LoongArch::XVHSUBW_H_B: |
| 5250 | case LoongArch::XVHSUBW_QU_DU: |
| 5251 | case LoongArch::XVHSUBW_Q_D: |
| 5252 | case LoongArch::XVHSUBW_WU_HU: |
| 5253 | case LoongArch::XVHSUBW_W_H: |
| 5254 | case LoongArch::XVILVH_B: |
| 5255 | case LoongArch::XVILVH_D: |
| 5256 | case LoongArch::XVILVH_H: |
| 5257 | case LoongArch::XVILVH_W: |
| 5258 | case LoongArch::XVILVL_B: |
| 5259 | case LoongArch::XVILVL_D: |
| 5260 | case LoongArch::XVILVL_H: |
| 5261 | case LoongArch::XVILVL_W: |
| 5262 | case LoongArch::XVMAX_B: |
| 5263 | case LoongArch::XVMAX_BU: |
| 5264 | case LoongArch::XVMAX_D: |
| 5265 | case LoongArch::XVMAX_DU: |
| 5266 | case LoongArch::XVMAX_H: |
| 5267 | case LoongArch::XVMAX_HU: |
| 5268 | case LoongArch::XVMAX_W: |
| 5269 | case LoongArch::XVMAX_WU: |
| 5270 | case LoongArch::XVMIN_B: |
| 5271 | case LoongArch::XVMIN_BU: |
| 5272 | case LoongArch::XVMIN_D: |
| 5273 | case LoongArch::XVMIN_DU: |
| 5274 | case LoongArch::XVMIN_H: |
| 5275 | case LoongArch::XVMIN_HU: |
| 5276 | case LoongArch::XVMIN_W: |
| 5277 | case LoongArch::XVMIN_WU: |
| 5278 | case LoongArch::XVMOD_B: |
| 5279 | case LoongArch::XVMOD_BU: |
| 5280 | case LoongArch::XVMOD_D: |
| 5281 | case LoongArch::XVMOD_DU: |
| 5282 | case LoongArch::XVMOD_H: |
| 5283 | case LoongArch::XVMOD_HU: |
| 5284 | case LoongArch::XVMOD_W: |
| 5285 | case LoongArch::XVMOD_WU: |
| 5286 | case LoongArch::XVMUH_B: |
| 5287 | case LoongArch::XVMUH_BU: |
| 5288 | case LoongArch::XVMUH_D: |
| 5289 | case LoongArch::XVMUH_DU: |
| 5290 | case LoongArch::XVMUH_H: |
| 5291 | case LoongArch::XVMUH_HU: |
| 5292 | case LoongArch::XVMUH_W: |
| 5293 | case LoongArch::XVMUH_WU: |
| 5294 | case LoongArch::XVMULWEV_D_W: |
| 5295 | case LoongArch::XVMULWEV_D_WU: |
| 5296 | case LoongArch::XVMULWEV_D_WU_W: |
| 5297 | case LoongArch::XVMULWEV_H_B: |
| 5298 | case LoongArch::XVMULWEV_H_BU: |
| 5299 | case LoongArch::XVMULWEV_H_BU_B: |
| 5300 | case LoongArch::XVMULWEV_Q_D: |
| 5301 | case LoongArch::XVMULWEV_Q_DU: |
| 5302 | case LoongArch::XVMULWEV_Q_DU_D: |
| 5303 | case LoongArch::XVMULWEV_W_H: |
| 5304 | case LoongArch::XVMULWEV_W_HU: |
| 5305 | case LoongArch::XVMULWEV_W_HU_H: |
| 5306 | case LoongArch::XVMULWOD_D_W: |
| 5307 | case LoongArch::XVMULWOD_D_WU: |
| 5308 | case LoongArch::XVMULWOD_D_WU_W: |
| 5309 | case LoongArch::XVMULWOD_H_B: |
| 5310 | case LoongArch::XVMULWOD_H_BU: |
| 5311 | case LoongArch::XVMULWOD_H_BU_B: |
| 5312 | case LoongArch::XVMULWOD_Q_D: |
| 5313 | case LoongArch::XVMULWOD_Q_DU: |
| 5314 | case LoongArch::XVMULWOD_Q_DU_D: |
| 5315 | case LoongArch::XVMULWOD_W_H: |
| 5316 | case LoongArch::XVMULWOD_W_HU: |
| 5317 | case LoongArch::XVMULWOD_W_HU_H: |
| 5318 | case LoongArch::XVMUL_B: |
| 5319 | case LoongArch::XVMUL_D: |
| 5320 | case LoongArch::XVMUL_H: |
| 5321 | case LoongArch::XVMUL_W: |
| 5322 | case LoongArch::XVNOR_V: |
| 5323 | case LoongArch::XVORN_V: |
| 5324 | case LoongArch::XVOR_V: |
| 5325 | case LoongArch::XVPACKEV_B: |
| 5326 | case LoongArch::XVPACKEV_D: |
| 5327 | case LoongArch::XVPACKEV_H: |
| 5328 | case LoongArch::XVPACKEV_W: |
| 5329 | case LoongArch::XVPACKOD_B: |
| 5330 | case LoongArch::XVPACKOD_D: |
| 5331 | case LoongArch::XVPACKOD_H: |
| 5332 | case LoongArch::XVPACKOD_W: |
| 5333 | case LoongArch::XVPERM_W: |
| 5334 | case LoongArch::XVPICKEV_B: |
| 5335 | case LoongArch::XVPICKEV_D: |
| 5336 | case LoongArch::XVPICKEV_H: |
| 5337 | case LoongArch::XVPICKEV_W: |
| 5338 | case LoongArch::XVPICKOD_B: |
| 5339 | case LoongArch::XVPICKOD_D: |
| 5340 | case LoongArch::XVPICKOD_H: |
| 5341 | case LoongArch::XVPICKOD_W: |
| 5342 | case LoongArch::XVROTR_B: |
| 5343 | case LoongArch::XVROTR_D: |
| 5344 | case LoongArch::XVROTR_H: |
| 5345 | case LoongArch::XVROTR_W: |
| 5346 | case LoongArch::XVSADD_B: |
| 5347 | case LoongArch::XVSADD_BU: |
| 5348 | case LoongArch::XVSADD_D: |
| 5349 | case LoongArch::XVSADD_DU: |
| 5350 | case LoongArch::XVSADD_H: |
| 5351 | case LoongArch::XVSADD_HU: |
| 5352 | case LoongArch::XVSADD_W: |
| 5353 | case LoongArch::XVSADD_WU: |
| 5354 | case LoongArch::XVSEQ_B: |
| 5355 | case LoongArch::XVSEQ_D: |
| 5356 | case LoongArch::XVSEQ_H: |
| 5357 | case LoongArch::XVSEQ_W: |
| 5358 | case LoongArch::XVSIGNCOV_B: |
| 5359 | case LoongArch::XVSIGNCOV_D: |
| 5360 | case LoongArch::XVSIGNCOV_H: |
| 5361 | case LoongArch::XVSIGNCOV_W: |
| 5362 | case LoongArch::XVSLE_B: |
| 5363 | case LoongArch::XVSLE_BU: |
| 5364 | case LoongArch::XVSLE_D: |
| 5365 | case LoongArch::XVSLE_DU: |
| 5366 | case LoongArch::XVSLE_H: |
| 5367 | case LoongArch::XVSLE_HU: |
| 5368 | case LoongArch::XVSLE_W: |
| 5369 | case LoongArch::XVSLE_WU: |
| 5370 | case LoongArch::XVSLL_B: |
| 5371 | case LoongArch::XVSLL_D: |
| 5372 | case LoongArch::XVSLL_H: |
| 5373 | case LoongArch::XVSLL_W: |
| 5374 | case LoongArch::XVSLT_B: |
| 5375 | case LoongArch::XVSLT_BU: |
| 5376 | case LoongArch::XVSLT_D: |
| 5377 | case LoongArch::XVSLT_DU: |
| 5378 | case LoongArch::XVSLT_H: |
| 5379 | case LoongArch::XVSLT_HU: |
| 5380 | case LoongArch::XVSLT_W: |
| 5381 | case LoongArch::XVSLT_WU: |
| 5382 | case LoongArch::XVSRAN_B_H: |
| 5383 | case LoongArch::XVSRAN_H_W: |
| 5384 | case LoongArch::XVSRAN_W_D: |
| 5385 | case LoongArch::XVSRARN_B_H: |
| 5386 | case LoongArch::XVSRARN_H_W: |
| 5387 | case LoongArch::XVSRARN_W_D: |
| 5388 | case LoongArch::XVSRAR_B: |
| 5389 | case LoongArch::XVSRAR_D: |
| 5390 | case LoongArch::XVSRAR_H: |
| 5391 | case LoongArch::XVSRAR_W: |
| 5392 | case LoongArch::XVSRA_B: |
| 5393 | case LoongArch::XVSRA_D: |
| 5394 | case LoongArch::XVSRA_H: |
| 5395 | case LoongArch::XVSRA_W: |
| 5396 | case LoongArch::XVSRLN_B_H: |
| 5397 | case LoongArch::XVSRLN_H_W: |
| 5398 | case LoongArch::XVSRLN_W_D: |
| 5399 | case LoongArch::XVSRLRN_B_H: |
| 5400 | case LoongArch::XVSRLRN_H_W: |
| 5401 | case LoongArch::XVSRLRN_W_D: |
| 5402 | case LoongArch::XVSRLR_B: |
| 5403 | case LoongArch::XVSRLR_D: |
| 5404 | case LoongArch::XVSRLR_H: |
| 5405 | case LoongArch::XVSRLR_W: |
| 5406 | case LoongArch::XVSRL_B: |
| 5407 | case LoongArch::XVSRL_D: |
| 5408 | case LoongArch::XVSRL_H: |
| 5409 | case LoongArch::XVSRL_W: |
| 5410 | case LoongArch::XVSSRAN_BU_H: |
| 5411 | case LoongArch::XVSSRAN_B_H: |
| 5412 | case LoongArch::XVSSRAN_HU_W: |
| 5413 | case LoongArch::XVSSRAN_H_W: |
| 5414 | case LoongArch::XVSSRAN_WU_D: |
| 5415 | case LoongArch::XVSSRAN_W_D: |
| 5416 | case LoongArch::XVSSRARN_BU_H: |
| 5417 | case LoongArch::XVSSRARN_B_H: |
| 5418 | case LoongArch::XVSSRARN_HU_W: |
| 5419 | case LoongArch::XVSSRARN_H_W: |
| 5420 | case LoongArch::XVSSRARN_WU_D: |
| 5421 | case LoongArch::XVSSRARN_W_D: |
| 5422 | case LoongArch::XVSSRLN_BU_H: |
| 5423 | case LoongArch::XVSSRLN_B_H: |
| 5424 | case LoongArch::XVSSRLN_HU_W: |
| 5425 | case LoongArch::XVSSRLN_H_W: |
| 5426 | case LoongArch::XVSSRLN_WU_D: |
| 5427 | case LoongArch::XVSSRLN_W_D: |
| 5428 | case LoongArch::XVSSRLRN_BU_H: |
| 5429 | case LoongArch::XVSSRLRN_B_H: |
| 5430 | case LoongArch::XVSSRLRN_HU_W: |
| 5431 | case LoongArch::XVSSRLRN_H_W: |
| 5432 | case LoongArch::XVSSRLRN_WU_D: |
| 5433 | case LoongArch::XVSSRLRN_W_D: |
| 5434 | case LoongArch::XVSSUB_B: |
| 5435 | case LoongArch::XVSSUB_BU: |
| 5436 | case LoongArch::XVSSUB_D: |
| 5437 | case LoongArch::XVSSUB_DU: |
| 5438 | case LoongArch::XVSSUB_H: |
| 5439 | case LoongArch::XVSSUB_HU: |
| 5440 | case LoongArch::XVSSUB_W: |
| 5441 | case LoongArch::XVSSUB_WU: |
| 5442 | case LoongArch::XVSUBWEV_D_W: |
| 5443 | case LoongArch::XVSUBWEV_D_WU: |
| 5444 | case LoongArch::XVSUBWEV_H_B: |
| 5445 | case LoongArch::XVSUBWEV_H_BU: |
| 5446 | case LoongArch::XVSUBWEV_Q_D: |
| 5447 | case LoongArch::XVSUBWEV_Q_DU: |
| 5448 | case LoongArch::XVSUBWEV_W_H: |
| 5449 | case LoongArch::XVSUBWEV_W_HU: |
| 5450 | case LoongArch::XVSUBWOD_D_W: |
| 5451 | case LoongArch::XVSUBWOD_D_WU: |
| 5452 | case LoongArch::XVSUBWOD_H_B: |
| 5453 | case LoongArch::XVSUBWOD_H_BU: |
| 5454 | case LoongArch::XVSUBWOD_Q_D: |
| 5455 | case LoongArch::XVSUBWOD_Q_DU: |
| 5456 | case LoongArch::XVSUBWOD_W_H: |
| 5457 | case LoongArch::XVSUBWOD_W_HU: |
| 5458 | case LoongArch::XVSUB_B: |
| 5459 | case LoongArch::XVSUB_D: |
| 5460 | case LoongArch::XVSUB_H: |
| 5461 | case LoongArch::XVSUB_Q: |
| 5462 | case LoongArch::XVSUB_W: |
| 5463 | case LoongArch::XVXOR_V: { |
| 5464 | // op: xk |
| 5465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5466 | Value |= (op & 0x1f) << 10; |
| 5467 | // op: xj |
| 5468 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5469 | Value |= (op & 0x1f) << 5; |
| 5470 | // op: xd |
| 5471 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5472 | Value |= (op & 0x1f); |
| 5473 | break; |
| 5474 | } |
| 5475 | case LoongArch::XVFRSTP_B: |
| 5476 | case LoongArch::XVFRSTP_H: |
| 5477 | case LoongArch::XVMADDWEV_D_W: |
| 5478 | case LoongArch::XVMADDWEV_D_WU: |
| 5479 | case LoongArch::XVMADDWEV_D_WU_W: |
| 5480 | case LoongArch::XVMADDWEV_H_B: |
| 5481 | case LoongArch::XVMADDWEV_H_BU: |
| 5482 | case LoongArch::XVMADDWEV_H_BU_B: |
| 5483 | case LoongArch::XVMADDWEV_Q_D: |
| 5484 | case LoongArch::XVMADDWEV_Q_DU: |
| 5485 | case LoongArch::XVMADDWEV_Q_DU_D: |
| 5486 | case LoongArch::XVMADDWEV_W_H: |
| 5487 | case LoongArch::XVMADDWEV_W_HU: |
| 5488 | case LoongArch::XVMADDWEV_W_HU_H: |
| 5489 | case LoongArch::XVMADDWOD_D_W: |
| 5490 | case LoongArch::XVMADDWOD_D_WU: |
| 5491 | case LoongArch::XVMADDWOD_D_WU_W: |
| 5492 | case LoongArch::XVMADDWOD_H_B: |
| 5493 | case LoongArch::XVMADDWOD_H_BU: |
| 5494 | case LoongArch::XVMADDWOD_H_BU_B: |
| 5495 | case LoongArch::XVMADDWOD_Q_D: |
| 5496 | case LoongArch::XVMADDWOD_Q_DU: |
| 5497 | case LoongArch::XVMADDWOD_Q_DU_D: |
| 5498 | case LoongArch::XVMADDWOD_W_H: |
| 5499 | case LoongArch::XVMADDWOD_W_HU: |
| 5500 | case LoongArch::XVMADDWOD_W_HU_H: |
| 5501 | case LoongArch::XVMADD_B: |
| 5502 | case LoongArch::XVMADD_D: |
| 5503 | case LoongArch::XVMADD_H: |
| 5504 | case LoongArch::XVMADD_W: |
| 5505 | case LoongArch::XVMSUB_B: |
| 5506 | case LoongArch::XVMSUB_D: |
| 5507 | case LoongArch::XVMSUB_H: |
| 5508 | case LoongArch::XVMSUB_W: |
| 5509 | case LoongArch::XVSHUF_D: |
| 5510 | case LoongArch::XVSHUF_H: |
| 5511 | case LoongArch::XVSHUF_W: { |
| 5512 | // op: xk |
| 5513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5514 | Value |= (op & 0x1f) << 10; |
| 5515 | // op: xj |
| 5516 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5517 | Value |= (op & 0x1f) << 5; |
| 5518 | // op: xd |
| 5519 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5520 | Value |= (op & 0x1f); |
| 5521 | break; |
| 5522 | } |
| 5523 | default: |
| 5524 | reportUnsupportedInst(Inst: MI); |
| 5525 | } |
| 5526 | return Value; |
| 5527 | } |
| 5528 | |
| 5529 | #ifdef GET_OPERAND_BIT_OFFSET |
| 5530 | #undef GET_OPERAND_BIT_OFFSET |
| 5531 | |
| 5532 | uint32_t LoongArchMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
| 5533 | unsigned OpNum, |
| 5534 | const MCSubtargetInfo &STI) const { |
| 5535 | switch (MI.getOpcode()) { |
| 5536 | case LoongArch::ERTN: |
| 5537 | case LoongArch::GTLBFLUSH: |
| 5538 | case LoongArch::TLBCLR: |
| 5539 | case LoongArch::TLBFILL: |
| 5540 | case LoongArch::TLBFLUSH: |
| 5541 | case LoongArch::TLBRD: |
| 5542 | case LoongArch::TLBSRCH: |
| 5543 | case LoongArch::TLBWR: |
| 5544 | case LoongArch::X86CLRTM: |
| 5545 | case LoongArch::X86DECTOP: |
| 5546 | case LoongArch::X86INCTOP: |
| 5547 | case LoongArch::X86SETTM: { |
| 5548 | break; |
| 5549 | } |
| 5550 | case LoongArch::SET_CFR_FALSE: |
| 5551 | case LoongArch::SET_CFR_TRUE: { |
| 5552 | switch (OpNum) { |
| 5553 | case 0: |
| 5554 | // op: cd |
| 5555 | return 0; |
| 5556 | } |
| 5557 | break; |
| 5558 | } |
| 5559 | case LoongArch::BREAK: |
| 5560 | case LoongArch::DBAR: |
| 5561 | case LoongArch::DBCL: |
| 5562 | case LoongArch::HVCL: |
| 5563 | case LoongArch::IBAR: |
| 5564 | case LoongArch::IDLE: |
| 5565 | case LoongArch::SYSCALL: { |
| 5566 | switch (OpNum) { |
| 5567 | case 0: |
| 5568 | // op: imm15 |
| 5569 | return 0; |
| 5570 | } |
| 5571 | break; |
| 5572 | } |
| 5573 | case LoongArch::JISCR0: |
| 5574 | case LoongArch::JISCR1: { |
| 5575 | switch (OpNum) { |
| 5576 | case 0: |
| 5577 | // op: imm21 |
| 5578 | return 0; |
| 5579 | } |
| 5580 | break; |
| 5581 | } |
| 5582 | case LoongArch::B: |
| 5583 | case LoongArch::BL: { |
| 5584 | switch (OpNum) { |
| 5585 | case 0: |
| 5586 | // op: imm26 |
| 5587 | return 0; |
| 5588 | } |
| 5589 | break; |
| 5590 | } |
| 5591 | case LoongArch::UD: { |
| 5592 | switch (OpNum) { |
| 5593 | case 0: |
| 5594 | // op: imm5 |
| 5595 | return 0; |
| 5596 | } |
| 5597 | break; |
| 5598 | } |
| 5599 | case LoongArch::X86MTTOP: { |
| 5600 | switch (OpNum) { |
| 5601 | case 0: |
| 5602 | // op: ptr |
| 5603 | return 5; |
| 5604 | } |
| 5605 | break; |
| 5606 | } |
| 5607 | case LoongArch::X86MFTOP: { |
| 5608 | switch (OpNum) { |
| 5609 | case 0: |
| 5610 | // op: rd |
| 5611 | return 0; |
| 5612 | } |
| 5613 | break; |
| 5614 | } |
| 5615 | case LoongArch::X86DEC_B: |
| 5616 | case LoongArch::X86DEC_D: |
| 5617 | case LoongArch::X86DEC_H: |
| 5618 | case LoongArch::X86DEC_W: |
| 5619 | case LoongArch::X86INC_B: |
| 5620 | case LoongArch::X86INC_D: |
| 5621 | case LoongArch::X86INC_H: |
| 5622 | case LoongArch::X86INC_W: { |
| 5623 | switch (OpNum) { |
| 5624 | case 0: |
| 5625 | // op: rj |
| 5626 | return 5; |
| 5627 | } |
| 5628 | break; |
| 5629 | } |
| 5630 | case LoongArch::INVTLB: { |
| 5631 | switch (OpNum) { |
| 5632 | case 0: |
| 5633 | // op: rk |
| 5634 | return 10; |
| 5635 | case 1: |
| 5636 | // op: rj |
| 5637 | return 5; |
| 5638 | case 2: |
| 5639 | // op: op |
| 5640 | return 0; |
| 5641 | } |
| 5642 | break; |
| 5643 | } |
| 5644 | case LoongArch::CSRRD: |
| 5645 | case LoongArch::GCSRRD: { |
| 5646 | switch (OpNum) { |
| 5647 | case 1: |
| 5648 | // op: csr_num |
| 5649 | return 10; |
| 5650 | case 0: |
| 5651 | // op: rd |
| 5652 | return 0; |
| 5653 | } |
| 5654 | break; |
| 5655 | } |
| 5656 | case LoongArch::FABS_D: |
| 5657 | case LoongArch::FABS_S: |
| 5658 | case LoongArch::FCLASS_D: |
| 5659 | case LoongArch::FCLASS_S: |
| 5660 | case LoongArch::FCVT_D_S: |
| 5661 | case LoongArch::FCVT_LD_D: |
| 5662 | case LoongArch::FCVT_S_D: |
| 5663 | case LoongArch::FCVT_UD_D: |
| 5664 | case LoongArch::FFINT_D_L: |
| 5665 | case LoongArch::FFINT_D_W: |
| 5666 | case LoongArch::FFINT_S_L: |
| 5667 | case LoongArch::FFINT_S_W: |
| 5668 | case LoongArch::FLOGB_D: |
| 5669 | case LoongArch::FLOGB_S: |
| 5670 | case LoongArch::FNEG_D: |
| 5671 | case LoongArch::FNEG_S: |
| 5672 | case LoongArch::FRECIPE_D: |
| 5673 | case LoongArch::FRECIPE_S: |
| 5674 | case LoongArch::FRECIP_D: |
| 5675 | case LoongArch::FRECIP_S: |
| 5676 | case LoongArch::FRINT_D: |
| 5677 | case LoongArch::FRINT_S: |
| 5678 | case LoongArch::FRSQRTE_D: |
| 5679 | case LoongArch::FRSQRTE_S: |
| 5680 | case LoongArch::FRSQRT_D: |
| 5681 | case LoongArch::FRSQRT_S: |
| 5682 | case LoongArch::FSQRT_D: |
| 5683 | case LoongArch::FSQRT_S: |
| 5684 | case LoongArch::FTINTRM_L_D: |
| 5685 | case LoongArch::FTINTRM_L_S: |
| 5686 | case LoongArch::FTINTRM_W_D: |
| 5687 | case LoongArch::FTINTRM_W_S: |
| 5688 | case LoongArch::FTINTRNE_L_D: |
| 5689 | case LoongArch::FTINTRNE_L_S: |
| 5690 | case LoongArch::FTINTRNE_W_D: |
| 5691 | case LoongArch::FTINTRNE_W_S: |
| 5692 | case LoongArch::FTINTRP_L_D: |
| 5693 | case LoongArch::FTINTRP_L_S: |
| 5694 | case LoongArch::FTINTRP_W_D: |
| 5695 | case LoongArch::FTINTRP_W_S: |
| 5696 | case LoongArch::FTINTRZ_L_D: |
| 5697 | case LoongArch::FTINTRZ_L_S: |
| 5698 | case LoongArch::FTINTRZ_W_D: |
| 5699 | case LoongArch::FTINTRZ_W_S: |
| 5700 | case LoongArch::FTINT_L_D: |
| 5701 | case LoongArch::FTINT_L_S: |
| 5702 | case LoongArch::FTINT_W_D: |
| 5703 | case LoongArch::FTINT_W_S: { |
| 5704 | switch (OpNum) { |
| 5705 | case 1: |
| 5706 | // op: fj |
| 5707 | return 5; |
| 5708 | case 0: |
| 5709 | // op: fd |
| 5710 | return 0; |
| 5711 | } |
| 5712 | break; |
| 5713 | } |
| 5714 | case LoongArch::VLDI: { |
| 5715 | switch (OpNum) { |
| 5716 | case 1: |
| 5717 | // op: imm13 |
| 5718 | return 5; |
| 5719 | case 0: |
| 5720 | // op: vd |
| 5721 | return 0; |
| 5722 | } |
| 5723 | break; |
| 5724 | } |
| 5725 | case LoongArch::XVLDI: { |
| 5726 | switch (OpNum) { |
| 5727 | case 1: |
| 5728 | // op: imm13 |
| 5729 | return 5; |
| 5730 | case 0: |
| 5731 | // op: xd |
| 5732 | return 0; |
| 5733 | } |
| 5734 | break; |
| 5735 | } |
| 5736 | case LoongArch::LU12I_W: |
| 5737 | case LoongArch::PCADDI: |
| 5738 | case LoongArch::PCADDU12I: |
| 5739 | case LoongArch::PCADDU18I: |
| 5740 | case LoongArch::PCALAU12I: { |
| 5741 | switch (OpNum) { |
| 5742 | case 1: |
| 5743 | // op: imm20 |
| 5744 | return 5; |
| 5745 | case 0: |
| 5746 | // op: rd |
| 5747 | return 0; |
| 5748 | } |
| 5749 | break; |
| 5750 | } |
| 5751 | case LoongArch::BCEQZ: |
| 5752 | case LoongArch::BCNEZ: { |
| 5753 | switch (OpNum) { |
| 5754 | case 1: |
| 5755 | // op: imm21 |
| 5756 | return 0; |
| 5757 | case 0: |
| 5758 | // op: cj |
| 5759 | return 5; |
| 5760 | } |
| 5761 | break; |
| 5762 | } |
| 5763 | case LoongArch::BEQZ: |
| 5764 | case LoongArch::BNEZ: { |
| 5765 | switch (OpNum) { |
| 5766 | case 1: |
| 5767 | // op: imm21 |
| 5768 | return 0; |
| 5769 | case 0: |
| 5770 | // op: rj |
| 5771 | return 5; |
| 5772 | } |
| 5773 | break; |
| 5774 | } |
| 5775 | case LoongArch::X86RCLI_B: |
| 5776 | case LoongArch::X86RCRI_B: |
| 5777 | case LoongArch::X86ROTLI_B: |
| 5778 | case LoongArch::X86ROTRI_B: |
| 5779 | case LoongArch::X86SLLI_B: |
| 5780 | case LoongArch::X86SRAI_B: |
| 5781 | case LoongArch::X86SRLI_B: { |
| 5782 | switch (OpNum) { |
| 5783 | case 1: |
| 5784 | // op: imm3 |
| 5785 | return 10; |
| 5786 | case 0: |
| 5787 | // op: rj |
| 5788 | return 5; |
| 5789 | } |
| 5790 | break; |
| 5791 | } |
| 5792 | case LoongArch::SETARMJ: |
| 5793 | case LoongArch::SETX86J: { |
| 5794 | switch (OpNum) { |
| 5795 | case 1: |
| 5796 | // op: imm4 |
| 5797 | return 10; |
| 5798 | case 0: |
| 5799 | // op: rd |
| 5800 | return 0; |
| 5801 | } |
| 5802 | break; |
| 5803 | } |
| 5804 | case LoongArch::ARMMOV_D: |
| 5805 | case LoongArch::ARMMOV_W: |
| 5806 | case LoongArch::ARMNOT_W: |
| 5807 | case LoongArch::ARMRRX_W: |
| 5808 | case LoongArch::X86RCLI_H: |
| 5809 | case LoongArch::X86RCRI_H: |
| 5810 | case LoongArch::X86ROTLI_H: |
| 5811 | case LoongArch::X86ROTRI_H: |
| 5812 | case LoongArch::X86SLLI_H: |
| 5813 | case LoongArch::X86SRAI_H: |
| 5814 | case LoongArch::X86SRLI_H: { |
| 5815 | switch (OpNum) { |
| 5816 | case 1: |
| 5817 | // op: imm4 |
| 5818 | return 10; |
| 5819 | case 0: |
| 5820 | // op: rj |
| 5821 | return 5; |
| 5822 | } |
| 5823 | break; |
| 5824 | } |
| 5825 | case LoongArch::ARMROTRI_W: |
| 5826 | case LoongArch::ARMSLLI_W: |
| 5827 | case LoongArch::ARMSRAI_W: |
| 5828 | case LoongArch::ARMSRLI_W: { |
| 5829 | switch (OpNum) { |
| 5830 | case 1: |
| 5831 | // op: imm5 |
| 5832 | return 10; |
| 5833 | case 0: |
| 5834 | // op: rj |
| 5835 | return 5; |
| 5836 | case 2: |
| 5837 | // op: imm4 |
| 5838 | return 0; |
| 5839 | } |
| 5840 | break; |
| 5841 | } |
| 5842 | case LoongArch::X86RCLI_W: |
| 5843 | case LoongArch::X86RCRI_W: |
| 5844 | case LoongArch::X86ROTLI_W: |
| 5845 | case LoongArch::X86ROTRI_W: |
| 5846 | case LoongArch::X86SLLI_W: |
| 5847 | case LoongArch::X86SRAI_W: |
| 5848 | case LoongArch::X86SRLI_W: { |
| 5849 | switch (OpNum) { |
| 5850 | case 1: |
| 5851 | // op: imm5 |
| 5852 | return 10; |
| 5853 | case 0: |
| 5854 | // op: rj |
| 5855 | return 5; |
| 5856 | } |
| 5857 | break; |
| 5858 | } |
| 5859 | case LoongArch::X86RCLI_D: |
| 5860 | case LoongArch::X86RCRI_D: |
| 5861 | case LoongArch::X86ROTLI_D: |
| 5862 | case LoongArch::X86ROTRI_D: |
| 5863 | case LoongArch::X86SLLI_D: |
| 5864 | case LoongArch::X86SRAI_D: |
| 5865 | case LoongArch::X86SRLI_D: { |
| 5866 | switch (OpNum) { |
| 5867 | case 1: |
| 5868 | // op: imm6 |
| 5869 | return 10; |
| 5870 | case 0: |
| 5871 | // op: rj |
| 5872 | return 5; |
| 5873 | } |
| 5874 | break; |
| 5875 | } |
| 5876 | case LoongArch::ARMMFFLAG: |
| 5877 | case LoongArch::ARMMTFLAG: |
| 5878 | case LoongArch::X86MFFLAG: |
| 5879 | case LoongArch::X86MTFLAG: { |
| 5880 | switch (OpNum) { |
| 5881 | case 1: |
| 5882 | // op: imm8 |
| 5883 | return 10; |
| 5884 | case 0: |
| 5885 | // op: rd |
| 5886 | return 0; |
| 5887 | } |
| 5888 | break; |
| 5889 | } |
| 5890 | case LoongArch::BITREV_4B: |
| 5891 | case LoongArch::BITREV_8B: |
| 5892 | case LoongArch::BITREV_D: |
| 5893 | case LoongArch::BITREV_W: |
| 5894 | case LoongArch::CLO_D: |
| 5895 | case LoongArch::CLO_W: |
| 5896 | case LoongArch::CLZ_D: |
| 5897 | case LoongArch::CLZ_W: |
| 5898 | case LoongArch::CPUCFG: |
| 5899 | case LoongArch::CTO_D: |
| 5900 | case LoongArch::CTO_W: |
| 5901 | case LoongArch::CTZ_D: |
| 5902 | case LoongArch::CTZ_W: |
| 5903 | case LoongArch::EXT_W_B: |
| 5904 | case LoongArch::EXT_W_H: |
| 5905 | case LoongArch::IOCSRRD_B: |
| 5906 | case LoongArch::IOCSRRD_D: |
| 5907 | case LoongArch::IOCSRRD_H: |
| 5908 | case LoongArch::IOCSRRD_W: |
| 5909 | case LoongArch::IOCSRWR_B: |
| 5910 | case LoongArch::IOCSRWR_D: |
| 5911 | case LoongArch::IOCSRWR_H: |
| 5912 | case LoongArch::IOCSRWR_W: |
| 5913 | case LoongArch::LLACQ_D: |
| 5914 | case LoongArch::LLACQ_W: |
| 5915 | case LoongArch::RDTIMEH_W: |
| 5916 | case LoongArch::RDTIMEL_W: |
| 5917 | case LoongArch::RDTIME_D: |
| 5918 | case LoongArch::REVB_2H: |
| 5919 | case LoongArch::REVB_2W: |
| 5920 | case LoongArch::REVB_4H: |
| 5921 | case LoongArch::REVB_D: |
| 5922 | case LoongArch::REVH_2W: |
| 5923 | case LoongArch::REVH_D: |
| 5924 | case LoongArch::SETX86LOOPE: |
| 5925 | case LoongArch::SETX86LOOPNE: { |
| 5926 | switch (OpNum) { |
| 5927 | case 1: |
| 5928 | // op: rj |
| 5929 | return 5; |
| 5930 | case 0: |
| 5931 | // op: rd |
| 5932 | return 0; |
| 5933 | } |
| 5934 | break; |
| 5935 | } |
| 5936 | case LoongArch::MOVGR2SCR: { |
| 5937 | switch (OpNum) { |
| 5938 | case 1: |
| 5939 | // op: rj |
| 5940 | return 5; |
| 5941 | case 0: |
| 5942 | // op: sd |
| 5943 | return 0; |
| 5944 | } |
| 5945 | break; |
| 5946 | } |
| 5947 | case LoongArch::VREPLGR2VR_B: |
| 5948 | case LoongArch::VREPLGR2VR_D: |
| 5949 | case LoongArch::VREPLGR2VR_H: |
| 5950 | case LoongArch::VREPLGR2VR_W: { |
| 5951 | switch (OpNum) { |
| 5952 | case 1: |
| 5953 | // op: rj |
| 5954 | return 5; |
| 5955 | case 0: |
| 5956 | // op: vd |
| 5957 | return 0; |
| 5958 | } |
| 5959 | break; |
| 5960 | } |
| 5961 | case LoongArch::XVREPLGR2VR_B: |
| 5962 | case LoongArch::XVREPLGR2VR_D: |
| 5963 | case LoongArch::XVREPLGR2VR_H: |
| 5964 | case LoongArch::XVREPLGR2VR_W: { |
| 5965 | switch (OpNum) { |
| 5966 | case 1: |
| 5967 | // op: rj |
| 5968 | return 5; |
| 5969 | case 0: |
| 5970 | // op: xd |
| 5971 | return 0; |
| 5972 | } |
| 5973 | break; |
| 5974 | } |
| 5975 | case LoongArch::ASRTGT_D: |
| 5976 | case LoongArch::ASRTLE_D: |
| 5977 | case LoongArch::X86ADC_B: |
| 5978 | case LoongArch::X86ADC_D: |
| 5979 | case LoongArch::X86ADC_H: |
| 5980 | case LoongArch::X86ADC_W: |
| 5981 | case LoongArch::X86ADD_B: |
| 5982 | case LoongArch::X86ADD_D: |
| 5983 | case LoongArch::X86ADD_DU: |
| 5984 | case LoongArch::X86ADD_H: |
| 5985 | case LoongArch::X86ADD_W: |
| 5986 | case LoongArch::X86ADD_WU: |
| 5987 | case LoongArch::X86AND_B: |
| 5988 | case LoongArch::X86AND_D: |
| 5989 | case LoongArch::X86AND_H: |
| 5990 | case LoongArch::X86AND_W: |
| 5991 | case LoongArch::X86MUL_B: |
| 5992 | case LoongArch::X86MUL_BU: |
| 5993 | case LoongArch::X86MUL_D: |
| 5994 | case LoongArch::X86MUL_DU: |
| 5995 | case LoongArch::X86MUL_H: |
| 5996 | case LoongArch::X86MUL_HU: |
| 5997 | case LoongArch::X86MUL_W: |
| 5998 | case LoongArch::X86MUL_WU: |
| 5999 | case LoongArch::X86OR_B: |
| 6000 | case LoongArch::X86OR_D: |
| 6001 | case LoongArch::X86OR_H: |
| 6002 | case LoongArch::X86OR_W: |
| 6003 | case LoongArch::X86RCL_B: |
| 6004 | case LoongArch::X86RCL_D: |
| 6005 | case LoongArch::X86RCL_H: |
| 6006 | case LoongArch::X86RCL_W: |
| 6007 | case LoongArch::X86RCR_B: |
| 6008 | case LoongArch::X86RCR_D: |
| 6009 | case LoongArch::X86RCR_H: |
| 6010 | case LoongArch::X86RCR_W: |
| 6011 | case LoongArch::X86ROTL_B: |
| 6012 | case LoongArch::X86ROTL_D: |
| 6013 | case LoongArch::X86ROTL_H: |
| 6014 | case LoongArch::X86ROTL_W: |
| 6015 | case LoongArch::X86ROTR_B: |
| 6016 | case LoongArch::X86ROTR_D: |
| 6017 | case LoongArch::X86ROTR_H: |
| 6018 | case LoongArch::X86ROTR_W: |
| 6019 | case LoongArch::X86SBC_B: |
| 6020 | case LoongArch::X86SBC_D: |
| 6021 | case LoongArch::X86SBC_H: |
| 6022 | case LoongArch::X86SBC_W: |
| 6023 | case LoongArch::X86SLL_B: |
| 6024 | case LoongArch::X86SLL_D: |
| 6025 | case LoongArch::X86SLL_H: |
| 6026 | case LoongArch::X86SLL_W: |
| 6027 | case LoongArch::X86SRA_B: |
| 6028 | case LoongArch::X86SRA_D: |
| 6029 | case LoongArch::X86SRA_H: |
| 6030 | case LoongArch::X86SRA_W: |
| 6031 | case LoongArch::X86SRL_B: |
| 6032 | case LoongArch::X86SRL_D: |
| 6033 | case LoongArch::X86SRL_H: |
| 6034 | case LoongArch::X86SRL_W: |
| 6035 | case LoongArch::X86SUB_B: |
| 6036 | case LoongArch::X86SUB_D: |
| 6037 | case LoongArch::X86SUB_DU: |
| 6038 | case LoongArch::X86SUB_H: |
| 6039 | case LoongArch::X86SUB_W: |
| 6040 | case LoongArch::X86SUB_WU: |
| 6041 | case LoongArch::X86XOR_B: |
| 6042 | case LoongArch::X86XOR_D: |
| 6043 | case LoongArch::X86XOR_H: |
| 6044 | case LoongArch::X86XOR_W: { |
| 6045 | switch (OpNum) { |
| 6046 | case 1: |
| 6047 | // op: rk |
| 6048 | return 10; |
| 6049 | case 0: |
| 6050 | // op: rj |
| 6051 | return 5; |
| 6052 | } |
| 6053 | break; |
| 6054 | } |
| 6055 | case LoongArch::AMADD_B: |
| 6056 | case LoongArch::AMADD_D: |
| 6057 | case LoongArch::AMADD_H: |
| 6058 | case LoongArch::AMADD_W: |
| 6059 | case LoongArch::AMADD__DB_B: |
| 6060 | case LoongArch::AMADD__DB_D: |
| 6061 | case LoongArch::AMADD__DB_H: |
| 6062 | case LoongArch::AMADD__DB_W: |
| 6063 | case LoongArch::AMAND_D: |
| 6064 | case LoongArch::AMAND_W: |
| 6065 | case LoongArch::AMAND__DB_D: |
| 6066 | case LoongArch::AMAND__DB_W: |
| 6067 | case LoongArch::AMMAX_D: |
| 6068 | case LoongArch::AMMAX_DU: |
| 6069 | case LoongArch::AMMAX_W: |
| 6070 | case LoongArch::AMMAX_WU: |
| 6071 | case LoongArch::AMMAX__DB_D: |
| 6072 | case LoongArch::AMMAX__DB_DU: |
| 6073 | case LoongArch::AMMAX__DB_W: |
| 6074 | case LoongArch::AMMAX__DB_WU: |
| 6075 | case LoongArch::AMMIN_D: |
| 6076 | case LoongArch::AMMIN_DU: |
| 6077 | case LoongArch::AMMIN_W: |
| 6078 | case LoongArch::AMMIN_WU: |
| 6079 | case LoongArch::AMMIN__DB_D: |
| 6080 | case LoongArch::AMMIN__DB_DU: |
| 6081 | case LoongArch::AMMIN__DB_W: |
| 6082 | case LoongArch::AMMIN__DB_WU: |
| 6083 | case LoongArch::AMOR_D: |
| 6084 | case LoongArch::AMOR_W: |
| 6085 | case LoongArch::AMOR__DB_D: |
| 6086 | case LoongArch::AMOR__DB_W: |
| 6087 | case LoongArch::AMSWAP_B: |
| 6088 | case LoongArch::AMSWAP_D: |
| 6089 | case LoongArch::AMSWAP_H: |
| 6090 | case LoongArch::AMSWAP_W: |
| 6091 | case LoongArch::AMSWAP__DB_B: |
| 6092 | case LoongArch::AMSWAP__DB_D: |
| 6093 | case LoongArch::AMSWAP__DB_H: |
| 6094 | case LoongArch::AMSWAP__DB_W: |
| 6095 | case LoongArch::AMXOR_D: |
| 6096 | case LoongArch::AMXOR_W: |
| 6097 | case LoongArch::AMXOR__DB_D: |
| 6098 | case LoongArch::AMXOR__DB_W: { |
| 6099 | switch (OpNum) { |
| 6100 | case 1: |
| 6101 | // op: rk |
| 6102 | return 10; |
| 6103 | case 2: |
| 6104 | // op: rj |
| 6105 | return 5; |
| 6106 | case 0: |
| 6107 | // op: rd |
| 6108 | return 0; |
| 6109 | } |
| 6110 | break; |
| 6111 | } |
| 6112 | case LoongArch::LDPTE: { |
| 6113 | switch (OpNum) { |
| 6114 | case 1: |
| 6115 | // op: seq |
| 6116 | return 10; |
| 6117 | case 0: |
| 6118 | // op: rj |
| 6119 | return 5; |
| 6120 | } |
| 6121 | break; |
| 6122 | } |
| 6123 | case LoongArch::MOVSCR2GR: { |
| 6124 | switch (OpNum) { |
| 6125 | case 1: |
| 6126 | // op: sj |
| 6127 | return 5; |
| 6128 | case 0: |
| 6129 | // op: rd |
| 6130 | return 0; |
| 6131 | } |
| 6132 | break; |
| 6133 | } |
| 6134 | case LoongArch::FMOV_D: |
| 6135 | case LoongArch::FMOV_S: |
| 6136 | case LoongArch::MOVCF2FR_xS: |
| 6137 | case LoongArch::MOVCF2GR: |
| 6138 | case LoongArch::MOVFCSR2GR: |
| 6139 | case LoongArch::MOVFR2CF_xS: |
| 6140 | case LoongArch::MOVFR2GR_D: |
| 6141 | case LoongArch::MOVFR2GR_S: |
| 6142 | case LoongArch::MOVFR2GR_S_64: |
| 6143 | case LoongArch::MOVFRH2GR_S: |
| 6144 | case LoongArch::MOVGR2CF: |
| 6145 | case LoongArch::MOVGR2FCSR: |
| 6146 | case LoongArch::MOVGR2FR_D: |
| 6147 | case LoongArch::MOVGR2FR_W: |
| 6148 | case LoongArch::MOVGR2FR_W_64: { |
| 6149 | switch (OpNum) { |
| 6150 | case 1: |
| 6151 | // op: src |
| 6152 | return 5; |
| 6153 | case 0: |
| 6154 | // op: dst |
| 6155 | return 0; |
| 6156 | } |
| 6157 | break; |
| 6158 | } |
| 6159 | case LoongArch::VSETALLNEZ_B: |
| 6160 | case LoongArch::VSETALLNEZ_D: |
| 6161 | case LoongArch::VSETALLNEZ_H: |
| 6162 | case LoongArch::VSETALLNEZ_W: |
| 6163 | case LoongArch::VSETANYEQZ_B: |
| 6164 | case LoongArch::VSETANYEQZ_D: |
| 6165 | case LoongArch::VSETANYEQZ_H: |
| 6166 | case LoongArch::VSETANYEQZ_W: |
| 6167 | case LoongArch::VSETEQZ_V: |
| 6168 | case LoongArch::VSETNEZ_V: { |
| 6169 | switch (OpNum) { |
| 6170 | case 1: |
| 6171 | // op: vj |
| 6172 | return 5; |
| 6173 | case 0: |
| 6174 | // op: cd |
| 6175 | return 0; |
| 6176 | } |
| 6177 | break; |
| 6178 | } |
| 6179 | case LoongArch::VCLO_B: |
| 6180 | case LoongArch::VCLO_D: |
| 6181 | case LoongArch::VCLO_H: |
| 6182 | case LoongArch::VCLO_W: |
| 6183 | case LoongArch::VCLZ_B: |
| 6184 | case LoongArch::VCLZ_D: |
| 6185 | case LoongArch::VCLZ_H: |
| 6186 | case LoongArch::VCLZ_W: |
| 6187 | case LoongArch::VEXTH_DU_WU: |
| 6188 | case LoongArch::VEXTH_D_W: |
| 6189 | case LoongArch::VEXTH_HU_BU: |
| 6190 | case LoongArch::VEXTH_H_B: |
| 6191 | case LoongArch::VEXTH_QU_DU: |
| 6192 | case LoongArch::VEXTH_Q_D: |
| 6193 | case LoongArch::VEXTH_WU_HU: |
| 6194 | case LoongArch::VEXTH_W_H: |
| 6195 | case LoongArch::VEXTL_QU_DU: |
| 6196 | case LoongArch::VEXTL_Q_D: |
| 6197 | case LoongArch::VFCLASS_D: |
| 6198 | case LoongArch::VFCLASS_S: |
| 6199 | case LoongArch::VFCVTH_D_S: |
| 6200 | case LoongArch::VFCVTH_S_H: |
| 6201 | case LoongArch::VFCVTL_D_S: |
| 6202 | case LoongArch::VFCVTL_S_H: |
| 6203 | case LoongArch::VFFINTH_D_W: |
| 6204 | case LoongArch::VFFINTL_D_W: |
| 6205 | case LoongArch::VFFINT_D_L: |
| 6206 | case LoongArch::VFFINT_D_LU: |
| 6207 | case LoongArch::VFFINT_S_W: |
| 6208 | case LoongArch::VFFINT_S_WU: |
| 6209 | case LoongArch::VFLOGB_D: |
| 6210 | case LoongArch::VFLOGB_S: |
| 6211 | case LoongArch::VFRECIPE_D: |
| 6212 | case LoongArch::VFRECIPE_S: |
| 6213 | case LoongArch::VFRECIP_D: |
| 6214 | case LoongArch::VFRECIP_S: |
| 6215 | case LoongArch::VFRINTRM_D: |
| 6216 | case LoongArch::VFRINTRM_S: |
| 6217 | case LoongArch::VFRINTRNE_D: |
| 6218 | case LoongArch::VFRINTRNE_S: |
| 6219 | case LoongArch::VFRINTRP_D: |
| 6220 | case LoongArch::VFRINTRP_S: |
| 6221 | case LoongArch::VFRINTRZ_D: |
| 6222 | case LoongArch::VFRINTRZ_S: |
| 6223 | case LoongArch::VFRINT_D: |
| 6224 | case LoongArch::VFRINT_S: |
| 6225 | case LoongArch::VFRSQRTE_D: |
| 6226 | case LoongArch::VFRSQRTE_S: |
| 6227 | case LoongArch::VFRSQRT_D: |
| 6228 | case LoongArch::VFRSQRT_S: |
| 6229 | case LoongArch::VFSQRT_D: |
| 6230 | case LoongArch::VFSQRT_S: |
| 6231 | case LoongArch::VFTINTH_L_S: |
| 6232 | case LoongArch::VFTINTL_L_S: |
| 6233 | case LoongArch::VFTINTRMH_L_S: |
| 6234 | case LoongArch::VFTINTRML_L_S: |
| 6235 | case LoongArch::VFTINTRM_L_D: |
| 6236 | case LoongArch::VFTINTRM_W_S: |
| 6237 | case LoongArch::VFTINTRNEH_L_S: |
| 6238 | case LoongArch::VFTINTRNEL_L_S: |
| 6239 | case LoongArch::VFTINTRNE_L_D: |
| 6240 | case LoongArch::VFTINTRNE_W_S: |
| 6241 | case LoongArch::VFTINTRPH_L_S: |
| 6242 | case LoongArch::VFTINTRPL_L_S: |
| 6243 | case LoongArch::VFTINTRP_L_D: |
| 6244 | case LoongArch::VFTINTRP_W_S: |
| 6245 | case LoongArch::VFTINTRZH_L_S: |
| 6246 | case LoongArch::VFTINTRZL_L_S: |
| 6247 | case LoongArch::VFTINTRZ_LU_D: |
| 6248 | case LoongArch::VFTINTRZ_L_D: |
| 6249 | case LoongArch::VFTINTRZ_WU_S: |
| 6250 | case LoongArch::VFTINTRZ_W_S: |
| 6251 | case LoongArch::VFTINT_LU_D: |
| 6252 | case LoongArch::VFTINT_L_D: |
| 6253 | case LoongArch::VFTINT_WU_S: |
| 6254 | case LoongArch::VFTINT_W_S: |
| 6255 | case LoongArch::VMSKGEZ_B: |
| 6256 | case LoongArch::VMSKLTZ_B: |
| 6257 | case LoongArch::VMSKLTZ_D: |
| 6258 | case LoongArch::VMSKLTZ_H: |
| 6259 | case LoongArch::VMSKLTZ_W: |
| 6260 | case LoongArch::VMSKNZ_B: |
| 6261 | case LoongArch::VNEG_B: |
| 6262 | case LoongArch::VNEG_D: |
| 6263 | case LoongArch::VNEG_H: |
| 6264 | case LoongArch::VNEG_W: |
| 6265 | case LoongArch::VPCNT_B: |
| 6266 | case LoongArch::VPCNT_D: |
| 6267 | case LoongArch::VPCNT_H: |
| 6268 | case LoongArch::VPCNT_W: { |
| 6269 | switch (OpNum) { |
| 6270 | case 1: |
| 6271 | // op: vj |
| 6272 | return 5; |
| 6273 | case 0: |
| 6274 | // op: vd |
| 6275 | return 0; |
| 6276 | } |
| 6277 | break; |
| 6278 | } |
| 6279 | case LoongArch::XVSETALLNEZ_B: |
| 6280 | case LoongArch::XVSETALLNEZ_D: |
| 6281 | case LoongArch::XVSETALLNEZ_H: |
| 6282 | case LoongArch::XVSETALLNEZ_W: |
| 6283 | case LoongArch::XVSETANYEQZ_B: |
| 6284 | case LoongArch::XVSETANYEQZ_D: |
| 6285 | case LoongArch::XVSETANYEQZ_H: |
| 6286 | case LoongArch::XVSETANYEQZ_W: |
| 6287 | case LoongArch::XVSETEQZ_V: |
| 6288 | case LoongArch::XVSETNEZ_V: { |
| 6289 | switch (OpNum) { |
| 6290 | case 1: |
| 6291 | // op: xj |
| 6292 | return 5; |
| 6293 | case 0: |
| 6294 | // op: cd |
| 6295 | return 0; |
| 6296 | } |
| 6297 | break; |
| 6298 | } |
| 6299 | case LoongArch::VEXT2XV_DU_BU: |
| 6300 | case LoongArch::VEXT2XV_DU_HU: |
| 6301 | case LoongArch::VEXT2XV_DU_WU: |
| 6302 | case LoongArch::VEXT2XV_D_B: |
| 6303 | case LoongArch::VEXT2XV_D_H: |
| 6304 | case LoongArch::VEXT2XV_D_W: |
| 6305 | case LoongArch::VEXT2XV_HU_BU: |
| 6306 | case LoongArch::VEXT2XV_H_B: |
| 6307 | case LoongArch::VEXT2XV_WU_BU: |
| 6308 | case LoongArch::VEXT2XV_WU_HU: |
| 6309 | case LoongArch::VEXT2XV_W_B: |
| 6310 | case LoongArch::VEXT2XV_W_H: |
| 6311 | case LoongArch::XVCLO_B: |
| 6312 | case LoongArch::XVCLO_D: |
| 6313 | case LoongArch::XVCLO_H: |
| 6314 | case LoongArch::XVCLO_W: |
| 6315 | case LoongArch::XVCLZ_B: |
| 6316 | case LoongArch::XVCLZ_D: |
| 6317 | case LoongArch::XVCLZ_H: |
| 6318 | case LoongArch::XVCLZ_W: |
| 6319 | case LoongArch::XVEXTH_DU_WU: |
| 6320 | case LoongArch::XVEXTH_D_W: |
| 6321 | case LoongArch::XVEXTH_HU_BU: |
| 6322 | case LoongArch::XVEXTH_H_B: |
| 6323 | case LoongArch::XVEXTH_QU_DU: |
| 6324 | case LoongArch::XVEXTH_Q_D: |
| 6325 | case LoongArch::XVEXTH_WU_HU: |
| 6326 | case LoongArch::XVEXTH_W_H: |
| 6327 | case LoongArch::XVEXTL_QU_DU: |
| 6328 | case LoongArch::XVEXTL_Q_D: |
| 6329 | case LoongArch::XVFCLASS_D: |
| 6330 | case LoongArch::XVFCLASS_S: |
| 6331 | case LoongArch::XVFCVTH_D_S: |
| 6332 | case LoongArch::XVFCVTH_S_H: |
| 6333 | case LoongArch::XVFCVTL_D_S: |
| 6334 | case LoongArch::XVFCVTL_S_H: |
| 6335 | case LoongArch::XVFFINTH_D_W: |
| 6336 | case LoongArch::XVFFINTL_D_W: |
| 6337 | case LoongArch::XVFFINT_D_L: |
| 6338 | case LoongArch::XVFFINT_D_LU: |
| 6339 | case LoongArch::XVFFINT_S_W: |
| 6340 | case LoongArch::XVFFINT_S_WU: |
| 6341 | case LoongArch::XVFLOGB_D: |
| 6342 | case LoongArch::XVFLOGB_S: |
| 6343 | case LoongArch::XVFRECIPE_D: |
| 6344 | case LoongArch::XVFRECIPE_S: |
| 6345 | case LoongArch::XVFRECIP_D: |
| 6346 | case LoongArch::XVFRECIP_S: |
| 6347 | case LoongArch::XVFRINTRM_D: |
| 6348 | case LoongArch::XVFRINTRM_S: |
| 6349 | case LoongArch::XVFRINTRNE_D: |
| 6350 | case LoongArch::XVFRINTRNE_S: |
| 6351 | case LoongArch::XVFRINTRP_D: |
| 6352 | case LoongArch::XVFRINTRP_S: |
| 6353 | case LoongArch::XVFRINTRZ_D: |
| 6354 | case LoongArch::XVFRINTRZ_S: |
| 6355 | case LoongArch::XVFRINT_D: |
| 6356 | case LoongArch::XVFRINT_S: |
| 6357 | case LoongArch::XVFRSQRTE_D: |
| 6358 | case LoongArch::XVFRSQRTE_S: |
| 6359 | case LoongArch::XVFRSQRT_D: |
| 6360 | case LoongArch::XVFRSQRT_S: |
| 6361 | case LoongArch::XVFSQRT_D: |
| 6362 | case LoongArch::XVFSQRT_S: |
| 6363 | case LoongArch::XVFTINTH_L_S: |
| 6364 | case LoongArch::XVFTINTL_L_S: |
| 6365 | case LoongArch::XVFTINTRMH_L_S: |
| 6366 | case LoongArch::XVFTINTRML_L_S: |
| 6367 | case LoongArch::XVFTINTRM_L_D: |
| 6368 | case LoongArch::XVFTINTRM_W_S: |
| 6369 | case LoongArch::XVFTINTRNEH_L_S: |
| 6370 | case LoongArch::XVFTINTRNEL_L_S: |
| 6371 | case LoongArch::XVFTINTRNE_L_D: |
| 6372 | case LoongArch::XVFTINTRNE_W_S: |
| 6373 | case LoongArch::XVFTINTRPH_L_S: |
| 6374 | case LoongArch::XVFTINTRPL_L_S: |
| 6375 | case LoongArch::XVFTINTRP_L_D: |
| 6376 | case LoongArch::XVFTINTRP_W_S: |
| 6377 | case LoongArch::XVFTINTRZH_L_S: |
| 6378 | case LoongArch::XVFTINTRZL_L_S: |
| 6379 | case LoongArch::XVFTINTRZ_LU_D: |
| 6380 | case LoongArch::XVFTINTRZ_L_D: |
| 6381 | case LoongArch::XVFTINTRZ_WU_S: |
| 6382 | case LoongArch::XVFTINTRZ_W_S: |
| 6383 | case LoongArch::XVFTINT_LU_D: |
| 6384 | case LoongArch::XVFTINT_L_D: |
| 6385 | case LoongArch::XVFTINT_WU_S: |
| 6386 | case LoongArch::XVFTINT_W_S: |
| 6387 | case LoongArch::XVMSKGEZ_B: |
| 6388 | case LoongArch::XVMSKLTZ_B: |
| 6389 | case LoongArch::XVMSKLTZ_D: |
| 6390 | case LoongArch::XVMSKLTZ_H: |
| 6391 | case LoongArch::XVMSKLTZ_W: |
| 6392 | case LoongArch::XVMSKNZ_B: |
| 6393 | case LoongArch::XVNEG_B: |
| 6394 | case LoongArch::XVNEG_D: |
| 6395 | case LoongArch::XVNEG_H: |
| 6396 | case LoongArch::XVNEG_W: |
| 6397 | case LoongArch::XVPCNT_B: |
| 6398 | case LoongArch::XVPCNT_D: |
| 6399 | case LoongArch::XVPCNT_H: |
| 6400 | case LoongArch::XVPCNT_W: |
| 6401 | case LoongArch::XVREPLVE0_B: |
| 6402 | case LoongArch::XVREPLVE0_D: |
| 6403 | case LoongArch::XVREPLVE0_H: |
| 6404 | case LoongArch::XVREPLVE0_Q: |
| 6405 | case LoongArch::XVREPLVE0_W: { |
| 6406 | switch (OpNum) { |
| 6407 | case 1: |
| 6408 | // op: xj |
| 6409 | return 5; |
| 6410 | case 0: |
| 6411 | // op: xd |
| 6412 | return 0; |
| 6413 | } |
| 6414 | break; |
| 6415 | } |
| 6416 | case LoongArch::CSRWR: |
| 6417 | case LoongArch::GCSRWR: { |
| 6418 | switch (OpNum) { |
| 6419 | case 2: |
| 6420 | // op: csr_num |
| 6421 | return 10; |
| 6422 | case 1: |
| 6423 | // op: rd |
| 6424 | return 0; |
| 6425 | } |
| 6426 | break; |
| 6427 | } |
| 6428 | case LoongArch::FCMP_CAF_D: |
| 6429 | case LoongArch::FCMP_CAF_S: |
| 6430 | case LoongArch::FCMP_CEQ_D: |
| 6431 | case LoongArch::FCMP_CEQ_S: |
| 6432 | case LoongArch::FCMP_CLE_D: |
| 6433 | case LoongArch::FCMP_CLE_S: |
| 6434 | case LoongArch::FCMP_CLT_D: |
| 6435 | case LoongArch::FCMP_CLT_S: |
| 6436 | case LoongArch::FCMP_CNE_D: |
| 6437 | case LoongArch::FCMP_CNE_S: |
| 6438 | case LoongArch::FCMP_COR_D: |
| 6439 | case LoongArch::FCMP_COR_S: |
| 6440 | case LoongArch::FCMP_CUEQ_D: |
| 6441 | case LoongArch::FCMP_CUEQ_S: |
| 6442 | case LoongArch::FCMP_CULE_D: |
| 6443 | case LoongArch::FCMP_CULE_S: |
| 6444 | case LoongArch::FCMP_CULT_D: |
| 6445 | case LoongArch::FCMP_CULT_S: |
| 6446 | case LoongArch::FCMP_CUNE_D: |
| 6447 | case LoongArch::FCMP_CUNE_S: |
| 6448 | case LoongArch::FCMP_CUN_D: |
| 6449 | case LoongArch::FCMP_CUN_S: |
| 6450 | case LoongArch::FCMP_SAF_D: |
| 6451 | case LoongArch::FCMP_SAF_S: |
| 6452 | case LoongArch::FCMP_SEQ_D: |
| 6453 | case LoongArch::FCMP_SEQ_S: |
| 6454 | case LoongArch::FCMP_SLE_D: |
| 6455 | case LoongArch::FCMP_SLE_S: |
| 6456 | case LoongArch::FCMP_SLT_D: |
| 6457 | case LoongArch::FCMP_SLT_S: |
| 6458 | case LoongArch::FCMP_SNE_D: |
| 6459 | case LoongArch::FCMP_SNE_S: |
| 6460 | case LoongArch::FCMP_SOR_D: |
| 6461 | case LoongArch::FCMP_SOR_S: |
| 6462 | case LoongArch::FCMP_SUEQ_D: |
| 6463 | case LoongArch::FCMP_SUEQ_S: |
| 6464 | case LoongArch::FCMP_SULE_D: |
| 6465 | case LoongArch::FCMP_SULE_S: |
| 6466 | case LoongArch::FCMP_SULT_D: |
| 6467 | case LoongArch::FCMP_SULT_S: |
| 6468 | case LoongArch::FCMP_SUNE_D: |
| 6469 | case LoongArch::FCMP_SUNE_S: |
| 6470 | case LoongArch::FCMP_SUN_D: |
| 6471 | case LoongArch::FCMP_SUN_S: { |
| 6472 | switch (OpNum) { |
| 6473 | case 2: |
| 6474 | // op: fk |
| 6475 | return 10; |
| 6476 | case 1: |
| 6477 | // op: fj |
| 6478 | return 5; |
| 6479 | case 0: |
| 6480 | // op: cd |
| 6481 | return 0; |
| 6482 | } |
| 6483 | break; |
| 6484 | } |
| 6485 | case LoongArch::FADD_D: |
| 6486 | case LoongArch::FADD_S: |
| 6487 | case LoongArch::FCOPYSIGN_D: |
| 6488 | case LoongArch::FCOPYSIGN_S: |
| 6489 | case LoongArch::FCVT_D_LD: |
| 6490 | case LoongArch::FDIV_D: |
| 6491 | case LoongArch::FDIV_S: |
| 6492 | case LoongArch::FMAXA_D: |
| 6493 | case LoongArch::FMAXA_S: |
| 6494 | case LoongArch::FMAX_D: |
| 6495 | case LoongArch::FMAX_S: |
| 6496 | case LoongArch::FMINA_D: |
| 6497 | case LoongArch::FMINA_S: |
| 6498 | case LoongArch::FMIN_D: |
| 6499 | case LoongArch::FMIN_S: |
| 6500 | case LoongArch::FMUL_D: |
| 6501 | case LoongArch::FMUL_S: |
| 6502 | case LoongArch::FSCALEB_D: |
| 6503 | case LoongArch::FSCALEB_S: |
| 6504 | case LoongArch::FSUB_D: |
| 6505 | case LoongArch::FSUB_S: { |
| 6506 | switch (OpNum) { |
| 6507 | case 2: |
| 6508 | // op: fk |
| 6509 | return 10; |
| 6510 | case 1: |
| 6511 | // op: fj |
| 6512 | return 5; |
| 6513 | case 0: |
| 6514 | // op: fd |
| 6515 | return 0; |
| 6516 | } |
| 6517 | break; |
| 6518 | } |
| 6519 | case LoongArch::VPICKVE2GR_D: |
| 6520 | case LoongArch::VPICKVE2GR_DU: { |
| 6521 | switch (OpNum) { |
| 6522 | case 2: |
| 6523 | // op: imm1 |
| 6524 | return 10; |
| 6525 | case 1: |
| 6526 | // op: vj |
| 6527 | return 5; |
| 6528 | case 0: |
| 6529 | // op: rd |
| 6530 | return 0; |
| 6531 | } |
| 6532 | break; |
| 6533 | } |
| 6534 | case LoongArch::VREPLVEI_D: { |
| 6535 | switch (OpNum) { |
| 6536 | case 2: |
| 6537 | // op: imm1 |
| 6538 | return 10; |
| 6539 | case 1: |
| 6540 | // op: vj |
| 6541 | return 5; |
| 6542 | case 0: |
| 6543 | // op: vd |
| 6544 | return 0; |
| 6545 | } |
| 6546 | break; |
| 6547 | } |
| 6548 | case LoongArch::XVREPL128VEI_D: { |
| 6549 | switch (OpNum) { |
| 6550 | case 2: |
| 6551 | // op: imm1 |
| 6552 | return 10; |
| 6553 | case 1: |
| 6554 | // op: xj |
| 6555 | return 5; |
| 6556 | case 0: |
| 6557 | // op: xd |
| 6558 | return 0; |
| 6559 | } |
| 6560 | break; |
| 6561 | } |
| 6562 | case LoongArch::VLDREPL_W: { |
| 6563 | switch (OpNum) { |
| 6564 | case 2: |
| 6565 | // op: imm10 |
| 6566 | return 10; |
| 6567 | case 1: |
| 6568 | // op: rj |
| 6569 | return 5; |
| 6570 | case 0: |
| 6571 | // op: vd |
| 6572 | return 0; |
| 6573 | } |
| 6574 | break; |
| 6575 | } |
| 6576 | case LoongArch::XVLDREPL_W: { |
| 6577 | switch (OpNum) { |
| 6578 | case 2: |
| 6579 | // op: imm10 |
| 6580 | return 10; |
| 6581 | case 1: |
| 6582 | // op: rj |
| 6583 | return 5; |
| 6584 | case 0: |
| 6585 | // op: xd |
| 6586 | return 0; |
| 6587 | } |
| 6588 | break; |
| 6589 | } |
| 6590 | case LoongArch::VLDREPL_H: { |
| 6591 | switch (OpNum) { |
| 6592 | case 2: |
| 6593 | // op: imm11 |
| 6594 | return 10; |
| 6595 | case 1: |
| 6596 | // op: rj |
| 6597 | return 5; |
| 6598 | case 0: |
| 6599 | // op: vd |
| 6600 | return 0; |
| 6601 | } |
| 6602 | break; |
| 6603 | } |
| 6604 | case LoongArch::XVLDREPL_H: { |
| 6605 | switch (OpNum) { |
| 6606 | case 2: |
| 6607 | // op: imm11 |
| 6608 | return 10; |
| 6609 | case 1: |
| 6610 | // op: rj |
| 6611 | return 5; |
| 6612 | case 0: |
| 6613 | // op: xd |
| 6614 | return 0; |
| 6615 | } |
| 6616 | break; |
| 6617 | } |
| 6618 | case LoongArch::FLD_D: |
| 6619 | case LoongArch::FLD_S: |
| 6620 | case LoongArch::FST_D: |
| 6621 | case LoongArch::FST_S: { |
| 6622 | switch (OpNum) { |
| 6623 | case 2: |
| 6624 | // op: imm12 |
| 6625 | return 10; |
| 6626 | case 1: |
| 6627 | // op: rj |
| 6628 | return 5; |
| 6629 | case 0: |
| 6630 | // op: fd |
| 6631 | return 0; |
| 6632 | } |
| 6633 | break; |
| 6634 | } |
| 6635 | case LoongArch::PRELD: { |
| 6636 | switch (OpNum) { |
| 6637 | case 2: |
| 6638 | // op: imm12 |
| 6639 | return 10; |
| 6640 | case 1: |
| 6641 | // op: rj |
| 6642 | return 5; |
| 6643 | case 0: |
| 6644 | // op: imm5 |
| 6645 | return 0; |
| 6646 | } |
| 6647 | break; |
| 6648 | } |
| 6649 | case LoongArch::CACOP: { |
| 6650 | switch (OpNum) { |
| 6651 | case 2: |
| 6652 | // op: imm12 |
| 6653 | return 10; |
| 6654 | case 1: |
| 6655 | // op: rj |
| 6656 | return 5; |
| 6657 | case 0: |
| 6658 | // op: op |
| 6659 | return 0; |
| 6660 | } |
| 6661 | break; |
| 6662 | } |
| 6663 | case LoongArch::ADDI_D: |
| 6664 | case LoongArch::ADDI_W: |
| 6665 | case LoongArch::ANDI: |
| 6666 | case LoongArch::LDL_D: |
| 6667 | case LoongArch::LDL_W: |
| 6668 | case LoongArch::LDR_D: |
| 6669 | case LoongArch::LDR_W: |
| 6670 | case LoongArch::LD_B: |
| 6671 | case LoongArch::LD_BU: |
| 6672 | case LoongArch::LD_D: |
| 6673 | case LoongArch::LD_H: |
| 6674 | case LoongArch::LD_HU: |
| 6675 | case LoongArch::LD_W: |
| 6676 | case LoongArch::LD_WU: |
| 6677 | case LoongArch::LU52I_D: |
| 6678 | case LoongArch::ORI: |
| 6679 | case LoongArch::SLTI: |
| 6680 | case LoongArch::SLTUI: |
| 6681 | case LoongArch::STL_D: |
| 6682 | case LoongArch::STL_W: |
| 6683 | case LoongArch::STR_D: |
| 6684 | case LoongArch::STR_W: |
| 6685 | case LoongArch::ST_B: |
| 6686 | case LoongArch::ST_D: |
| 6687 | case LoongArch::ST_H: |
| 6688 | case LoongArch::ST_W: |
| 6689 | case LoongArch::XORI: { |
| 6690 | switch (OpNum) { |
| 6691 | case 2: |
| 6692 | // op: imm12 |
| 6693 | return 10; |
| 6694 | case 1: |
| 6695 | // op: rj |
| 6696 | return 5; |
| 6697 | case 0: |
| 6698 | // op: rd |
| 6699 | return 0; |
| 6700 | } |
| 6701 | break; |
| 6702 | } |
| 6703 | case LoongArch::VLD: |
| 6704 | case LoongArch::VLDREPL_B: |
| 6705 | case LoongArch::VST: { |
| 6706 | switch (OpNum) { |
| 6707 | case 2: |
| 6708 | // op: imm12 |
| 6709 | return 10; |
| 6710 | case 1: |
| 6711 | // op: rj |
| 6712 | return 5; |
| 6713 | case 0: |
| 6714 | // op: vd |
| 6715 | return 0; |
| 6716 | } |
| 6717 | break; |
| 6718 | } |
| 6719 | case LoongArch::XVLD: |
| 6720 | case LoongArch::XVLDREPL_B: |
| 6721 | case LoongArch::XVST: { |
| 6722 | switch (OpNum) { |
| 6723 | case 2: |
| 6724 | // op: imm12 |
| 6725 | return 10; |
| 6726 | case 1: |
| 6727 | // op: rj |
| 6728 | return 5; |
| 6729 | case 0: |
| 6730 | // op: xd |
| 6731 | return 0; |
| 6732 | } |
| 6733 | break; |
| 6734 | } |
| 6735 | case LoongArch::LDPTR_D: |
| 6736 | case LoongArch::LDPTR_W: |
| 6737 | case LoongArch::LL_D: |
| 6738 | case LoongArch::LL_W: |
| 6739 | case LoongArch::STPTR_D: |
| 6740 | case LoongArch::STPTR_W: { |
| 6741 | switch (OpNum) { |
| 6742 | case 2: |
| 6743 | // op: imm14 |
| 6744 | return 10; |
| 6745 | case 1: |
| 6746 | // op: rj |
| 6747 | return 5; |
| 6748 | case 0: |
| 6749 | // op: rd |
| 6750 | return 0; |
| 6751 | } |
| 6752 | break; |
| 6753 | } |
| 6754 | case LoongArch::BEQ: |
| 6755 | case LoongArch::BGE: |
| 6756 | case LoongArch::BGEU: |
| 6757 | case LoongArch::BLT: |
| 6758 | case LoongArch::BLTU: |
| 6759 | case LoongArch::BNE: { |
| 6760 | switch (OpNum) { |
| 6761 | case 2: |
| 6762 | // op: imm16 |
| 6763 | return 10; |
| 6764 | case 0: |
| 6765 | // op: rj |
| 6766 | return 5; |
| 6767 | case 1: |
| 6768 | // op: rd |
| 6769 | return 0; |
| 6770 | } |
| 6771 | break; |
| 6772 | } |
| 6773 | case LoongArch::ADDU16I_D: |
| 6774 | case LoongArch::JIRL: { |
| 6775 | switch (OpNum) { |
| 6776 | case 2: |
| 6777 | // op: imm16 |
| 6778 | return 10; |
| 6779 | case 1: |
| 6780 | // op: rj |
| 6781 | return 5; |
| 6782 | case 0: |
| 6783 | // op: rd |
| 6784 | return 0; |
| 6785 | } |
| 6786 | break; |
| 6787 | } |
| 6788 | case LoongArch::VPICKVE2GR_W: |
| 6789 | case LoongArch::VPICKVE2GR_WU: { |
| 6790 | switch (OpNum) { |
| 6791 | case 2: |
| 6792 | // op: imm2 |
| 6793 | return 10; |
| 6794 | case 1: |
| 6795 | // op: vj |
| 6796 | return 5; |
| 6797 | case 0: |
| 6798 | // op: rd |
| 6799 | return 0; |
| 6800 | } |
| 6801 | break; |
| 6802 | } |
| 6803 | case LoongArch::VREPLVEI_W: { |
| 6804 | switch (OpNum) { |
| 6805 | case 2: |
| 6806 | // op: imm2 |
| 6807 | return 10; |
| 6808 | case 1: |
| 6809 | // op: vj |
| 6810 | return 5; |
| 6811 | case 0: |
| 6812 | // op: vd |
| 6813 | return 0; |
| 6814 | } |
| 6815 | break; |
| 6816 | } |
| 6817 | case LoongArch::XVPICKVE2GR_D: |
| 6818 | case LoongArch::XVPICKVE2GR_DU: { |
| 6819 | switch (OpNum) { |
| 6820 | case 2: |
| 6821 | // op: imm2 |
| 6822 | return 10; |
| 6823 | case 1: |
| 6824 | // op: xj |
| 6825 | return 5; |
| 6826 | case 0: |
| 6827 | // op: rd |
| 6828 | return 0; |
| 6829 | } |
| 6830 | break; |
| 6831 | } |
| 6832 | case LoongArch::XVPICKVE_D: |
| 6833 | case LoongArch::XVREPL128VEI_W: { |
| 6834 | switch (OpNum) { |
| 6835 | case 2: |
| 6836 | // op: imm2 |
| 6837 | return 10; |
| 6838 | case 1: |
| 6839 | // op: xj |
| 6840 | return 5; |
| 6841 | case 0: |
| 6842 | // op: xd |
| 6843 | return 0; |
| 6844 | } |
| 6845 | break; |
| 6846 | } |
| 6847 | case LoongArch::LU32I_D: { |
| 6848 | switch (OpNum) { |
| 6849 | case 2: |
| 6850 | // op: imm20 |
| 6851 | return 5; |
| 6852 | case 1: |
| 6853 | // op: rd |
| 6854 | return 0; |
| 6855 | } |
| 6856 | break; |
| 6857 | } |
| 6858 | case LoongArch::RCRI_B: |
| 6859 | case LoongArch::ROTRI_B: { |
| 6860 | switch (OpNum) { |
| 6861 | case 2: |
| 6862 | // op: imm3 |
| 6863 | return 10; |
| 6864 | case 1: |
| 6865 | // op: rj |
| 6866 | return 5; |
| 6867 | case 0: |
| 6868 | // op: rd |
| 6869 | return 0; |
| 6870 | } |
| 6871 | break; |
| 6872 | } |
| 6873 | case LoongArch::VPICKVE2GR_H: |
| 6874 | case LoongArch::VPICKVE2GR_HU: { |
| 6875 | switch (OpNum) { |
| 6876 | case 2: |
| 6877 | // op: imm3 |
| 6878 | return 10; |
| 6879 | case 1: |
| 6880 | // op: vj |
| 6881 | return 5; |
| 6882 | case 0: |
| 6883 | // op: rd |
| 6884 | return 0; |
| 6885 | } |
| 6886 | break; |
| 6887 | } |
| 6888 | case LoongArch::VBITCLRI_B: |
| 6889 | case LoongArch::VBITREVI_B: |
| 6890 | case LoongArch::VBITSETI_B: |
| 6891 | case LoongArch::VREPLVEI_H: |
| 6892 | case LoongArch::VROTRI_B: |
| 6893 | case LoongArch::VSAT_B: |
| 6894 | case LoongArch::VSAT_BU: |
| 6895 | case LoongArch::VSLLI_B: |
| 6896 | case LoongArch::VSLLWIL_HU_BU: |
| 6897 | case LoongArch::VSLLWIL_H_B: |
| 6898 | case LoongArch::VSRAI_B: |
| 6899 | case LoongArch::VSRARI_B: |
| 6900 | case LoongArch::VSRLI_B: |
| 6901 | case LoongArch::VSRLRI_B: { |
| 6902 | switch (OpNum) { |
| 6903 | case 2: |
| 6904 | // op: imm3 |
| 6905 | return 10; |
| 6906 | case 1: |
| 6907 | // op: vj |
| 6908 | return 5; |
| 6909 | case 0: |
| 6910 | // op: vd |
| 6911 | return 0; |
| 6912 | } |
| 6913 | break; |
| 6914 | } |
| 6915 | case LoongArch::XVPICKVE2GR_W: |
| 6916 | case LoongArch::XVPICKVE2GR_WU: { |
| 6917 | switch (OpNum) { |
| 6918 | case 2: |
| 6919 | // op: imm3 |
| 6920 | return 10; |
| 6921 | case 1: |
| 6922 | // op: xj |
| 6923 | return 5; |
| 6924 | case 0: |
| 6925 | // op: rd |
| 6926 | return 0; |
| 6927 | } |
| 6928 | break; |
| 6929 | } |
| 6930 | case LoongArch::XVBITCLRI_B: |
| 6931 | case LoongArch::XVBITREVI_B: |
| 6932 | case LoongArch::XVBITSETI_B: |
| 6933 | case LoongArch::XVPICKVE_W: |
| 6934 | case LoongArch::XVREPL128VEI_H: |
| 6935 | case LoongArch::XVROTRI_B: |
| 6936 | case LoongArch::XVSAT_B: |
| 6937 | case LoongArch::XVSAT_BU: |
| 6938 | case LoongArch::XVSLLI_B: |
| 6939 | case LoongArch::XVSLLWIL_HU_BU: |
| 6940 | case LoongArch::XVSLLWIL_H_B: |
| 6941 | case LoongArch::XVSRAI_B: |
| 6942 | case LoongArch::XVSRARI_B: |
| 6943 | case LoongArch::XVSRLI_B: |
| 6944 | case LoongArch::XVSRLRI_B: { |
| 6945 | switch (OpNum) { |
| 6946 | case 2: |
| 6947 | // op: imm3 |
| 6948 | return 10; |
| 6949 | case 1: |
| 6950 | // op: xj |
| 6951 | return 5; |
| 6952 | case 0: |
| 6953 | // op: xd |
| 6954 | return 0; |
| 6955 | } |
| 6956 | break; |
| 6957 | } |
| 6958 | case LoongArch::ARMADC_W: |
| 6959 | case LoongArch::ARMADD_W: |
| 6960 | case LoongArch::ARMAND_W: |
| 6961 | case LoongArch::ARMOR_W: |
| 6962 | case LoongArch::ARMROTR_W: |
| 6963 | case LoongArch::ARMSBC_W: |
| 6964 | case LoongArch::ARMSLL_W: |
| 6965 | case LoongArch::ARMSRA_W: |
| 6966 | case LoongArch::ARMSRL_W: |
| 6967 | case LoongArch::ARMSUB_W: |
| 6968 | case LoongArch::ARMXOR_W: { |
| 6969 | switch (OpNum) { |
| 6970 | case 2: |
| 6971 | // op: imm4 |
| 6972 | return 0; |
| 6973 | case 1: |
| 6974 | // op: rk |
| 6975 | return 10; |
| 6976 | case 0: |
| 6977 | // op: rj |
| 6978 | return 5; |
| 6979 | } |
| 6980 | break; |
| 6981 | } |
| 6982 | case LoongArch::ARMMOVE: |
| 6983 | case LoongArch::RCRI_H: |
| 6984 | case LoongArch::ROTRI_H: { |
| 6985 | switch (OpNum) { |
| 6986 | case 2: |
| 6987 | // op: imm4 |
| 6988 | return 10; |
| 6989 | case 1: |
| 6990 | // op: rj |
| 6991 | return 5; |
| 6992 | case 0: |
| 6993 | // op: rd |
| 6994 | return 0; |
| 6995 | } |
| 6996 | break; |
| 6997 | } |
| 6998 | case LoongArch::VPICKVE2GR_B: |
| 6999 | case LoongArch::VPICKVE2GR_BU: { |
| 7000 | switch (OpNum) { |
| 7001 | case 2: |
| 7002 | // op: imm4 |
| 7003 | return 10; |
| 7004 | case 1: |
| 7005 | // op: vj |
| 7006 | return 5; |
| 7007 | case 0: |
| 7008 | // op: rd |
| 7009 | return 0; |
| 7010 | } |
| 7011 | break; |
| 7012 | } |
| 7013 | case LoongArch::VBITCLRI_H: |
| 7014 | case LoongArch::VBITREVI_H: |
| 7015 | case LoongArch::VBITSETI_H: |
| 7016 | case LoongArch::VREPLVEI_B: |
| 7017 | case LoongArch::VROTRI_H: |
| 7018 | case LoongArch::VSAT_H: |
| 7019 | case LoongArch::VSAT_HU: |
| 7020 | case LoongArch::VSLLI_H: |
| 7021 | case LoongArch::VSLLWIL_WU_HU: |
| 7022 | case LoongArch::VSLLWIL_W_H: |
| 7023 | case LoongArch::VSRAI_H: |
| 7024 | case LoongArch::VSRARI_H: |
| 7025 | case LoongArch::VSRLI_H: |
| 7026 | case LoongArch::VSRLRI_H: { |
| 7027 | switch (OpNum) { |
| 7028 | case 2: |
| 7029 | // op: imm4 |
| 7030 | return 10; |
| 7031 | case 1: |
| 7032 | // op: vj |
| 7033 | return 5; |
| 7034 | case 0: |
| 7035 | // op: vd |
| 7036 | return 0; |
| 7037 | } |
| 7038 | break; |
| 7039 | } |
| 7040 | case LoongArch::XVBITCLRI_H: |
| 7041 | case LoongArch::XVBITREVI_H: |
| 7042 | case LoongArch::XVBITSETI_H: |
| 7043 | case LoongArch::XVREPL128VEI_B: |
| 7044 | case LoongArch::XVROTRI_H: |
| 7045 | case LoongArch::XVSAT_H: |
| 7046 | case LoongArch::XVSAT_HU: |
| 7047 | case LoongArch::XVSLLI_H: |
| 7048 | case LoongArch::XVSLLWIL_WU_HU: |
| 7049 | case LoongArch::XVSLLWIL_W_H: |
| 7050 | case LoongArch::XVSRAI_H: |
| 7051 | case LoongArch::XVSRARI_H: |
| 7052 | case LoongArch::XVSRLI_H: |
| 7053 | case LoongArch::XVSRLRI_H: { |
| 7054 | switch (OpNum) { |
| 7055 | case 2: |
| 7056 | // op: imm4 |
| 7057 | return 10; |
| 7058 | case 1: |
| 7059 | // op: xj |
| 7060 | return 5; |
| 7061 | case 0: |
| 7062 | // op: xd |
| 7063 | return 0; |
| 7064 | } |
| 7065 | break; |
| 7066 | } |
| 7067 | case LoongArch::ADDU12I_D: |
| 7068 | case LoongArch::ADDU12I_W: |
| 7069 | case LoongArch::RCRI_W: |
| 7070 | case LoongArch::ROTRI_W: |
| 7071 | case LoongArch::SLLI_W: |
| 7072 | case LoongArch::SRAI_W: |
| 7073 | case LoongArch::SRLI_W: { |
| 7074 | switch (OpNum) { |
| 7075 | case 2: |
| 7076 | // op: imm5 |
| 7077 | return 10; |
| 7078 | case 1: |
| 7079 | // op: rj |
| 7080 | return 5; |
| 7081 | case 0: |
| 7082 | // op: rd |
| 7083 | return 0; |
| 7084 | } |
| 7085 | break; |
| 7086 | } |
| 7087 | case LoongArch::VADDI_BU: |
| 7088 | case LoongArch::VADDI_DU: |
| 7089 | case LoongArch::VADDI_HU: |
| 7090 | case LoongArch::VADDI_WU: |
| 7091 | case LoongArch::VBITCLRI_W: |
| 7092 | case LoongArch::VBITREVI_W: |
| 7093 | case LoongArch::VBITSETI_W: |
| 7094 | case LoongArch::VBSLL_V: |
| 7095 | case LoongArch::VBSRL_V: |
| 7096 | case LoongArch::VMAXI_B: |
| 7097 | case LoongArch::VMAXI_BU: |
| 7098 | case LoongArch::VMAXI_D: |
| 7099 | case LoongArch::VMAXI_DU: |
| 7100 | case LoongArch::VMAXI_H: |
| 7101 | case LoongArch::VMAXI_HU: |
| 7102 | case LoongArch::VMAXI_W: |
| 7103 | case LoongArch::VMAXI_WU: |
| 7104 | case LoongArch::VMINI_B: |
| 7105 | case LoongArch::VMINI_BU: |
| 7106 | case LoongArch::VMINI_D: |
| 7107 | case LoongArch::VMINI_DU: |
| 7108 | case LoongArch::VMINI_H: |
| 7109 | case LoongArch::VMINI_HU: |
| 7110 | case LoongArch::VMINI_W: |
| 7111 | case LoongArch::VMINI_WU: |
| 7112 | case LoongArch::VROTRI_W: |
| 7113 | case LoongArch::VSAT_W: |
| 7114 | case LoongArch::VSAT_WU: |
| 7115 | case LoongArch::VSEQI_B: |
| 7116 | case LoongArch::VSEQI_D: |
| 7117 | case LoongArch::VSEQI_H: |
| 7118 | case LoongArch::VSEQI_W: |
| 7119 | case LoongArch::VSLEI_B: |
| 7120 | case LoongArch::VSLEI_BU: |
| 7121 | case LoongArch::VSLEI_D: |
| 7122 | case LoongArch::VSLEI_DU: |
| 7123 | case LoongArch::VSLEI_H: |
| 7124 | case LoongArch::VSLEI_HU: |
| 7125 | case LoongArch::VSLEI_W: |
| 7126 | case LoongArch::VSLEI_WU: |
| 7127 | case LoongArch::VSLLI_W: |
| 7128 | case LoongArch::VSLLWIL_DU_WU: |
| 7129 | case LoongArch::VSLLWIL_D_W: |
| 7130 | case LoongArch::VSLTI_B: |
| 7131 | case LoongArch::VSLTI_BU: |
| 7132 | case LoongArch::VSLTI_D: |
| 7133 | case LoongArch::VSLTI_DU: |
| 7134 | case LoongArch::VSLTI_H: |
| 7135 | case LoongArch::VSLTI_HU: |
| 7136 | case LoongArch::VSLTI_W: |
| 7137 | case LoongArch::VSLTI_WU: |
| 7138 | case LoongArch::VSRAI_W: |
| 7139 | case LoongArch::VSRARI_W: |
| 7140 | case LoongArch::VSRLI_W: |
| 7141 | case LoongArch::VSRLRI_W: |
| 7142 | case LoongArch::VSUBI_BU: |
| 7143 | case LoongArch::VSUBI_DU: |
| 7144 | case LoongArch::VSUBI_HU: |
| 7145 | case LoongArch::VSUBI_WU: { |
| 7146 | switch (OpNum) { |
| 7147 | case 2: |
| 7148 | // op: imm5 |
| 7149 | return 10; |
| 7150 | case 1: |
| 7151 | // op: vj |
| 7152 | return 5; |
| 7153 | case 0: |
| 7154 | // op: vd |
| 7155 | return 0; |
| 7156 | } |
| 7157 | break; |
| 7158 | } |
| 7159 | case LoongArch::XVADDI_BU: |
| 7160 | case LoongArch::XVADDI_DU: |
| 7161 | case LoongArch::XVADDI_HU: |
| 7162 | case LoongArch::XVADDI_WU: |
| 7163 | case LoongArch::XVBITCLRI_W: |
| 7164 | case LoongArch::XVBITREVI_W: |
| 7165 | case LoongArch::XVBITSETI_W: |
| 7166 | case LoongArch::XVBSLL_V: |
| 7167 | case LoongArch::XVBSRL_V: |
| 7168 | case LoongArch::XVHSELI_D: |
| 7169 | case LoongArch::XVMAXI_B: |
| 7170 | case LoongArch::XVMAXI_BU: |
| 7171 | case LoongArch::XVMAXI_D: |
| 7172 | case LoongArch::XVMAXI_DU: |
| 7173 | case LoongArch::XVMAXI_H: |
| 7174 | case LoongArch::XVMAXI_HU: |
| 7175 | case LoongArch::XVMAXI_W: |
| 7176 | case LoongArch::XVMAXI_WU: |
| 7177 | case LoongArch::XVMINI_B: |
| 7178 | case LoongArch::XVMINI_BU: |
| 7179 | case LoongArch::XVMINI_D: |
| 7180 | case LoongArch::XVMINI_DU: |
| 7181 | case LoongArch::XVMINI_H: |
| 7182 | case LoongArch::XVMINI_HU: |
| 7183 | case LoongArch::XVMINI_W: |
| 7184 | case LoongArch::XVMINI_WU: |
| 7185 | case LoongArch::XVROTRI_W: |
| 7186 | case LoongArch::XVSAT_W: |
| 7187 | case LoongArch::XVSAT_WU: |
| 7188 | case LoongArch::XVSEQI_B: |
| 7189 | case LoongArch::XVSEQI_D: |
| 7190 | case LoongArch::XVSEQI_H: |
| 7191 | case LoongArch::XVSEQI_W: |
| 7192 | case LoongArch::XVSLEI_B: |
| 7193 | case LoongArch::XVSLEI_BU: |
| 7194 | case LoongArch::XVSLEI_D: |
| 7195 | case LoongArch::XVSLEI_DU: |
| 7196 | case LoongArch::XVSLEI_H: |
| 7197 | case LoongArch::XVSLEI_HU: |
| 7198 | case LoongArch::XVSLEI_W: |
| 7199 | case LoongArch::XVSLEI_WU: |
| 7200 | case LoongArch::XVSLLI_W: |
| 7201 | case LoongArch::XVSLLWIL_DU_WU: |
| 7202 | case LoongArch::XVSLLWIL_D_W: |
| 7203 | case LoongArch::XVSLTI_B: |
| 7204 | case LoongArch::XVSLTI_BU: |
| 7205 | case LoongArch::XVSLTI_D: |
| 7206 | case LoongArch::XVSLTI_DU: |
| 7207 | case LoongArch::XVSLTI_H: |
| 7208 | case LoongArch::XVSLTI_HU: |
| 7209 | case LoongArch::XVSLTI_W: |
| 7210 | case LoongArch::XVSLTI_WU: |
| 7211 | case LoongArch::XVSRAI_W: |
| 7212 | case LoongArch::XVSRARI_W: |
| 7213 | case LoongArch::XVSRLI_W: |
| 7214 | case LoongArch::XVSRLRI_W: |
| 7215 | case LoongArch::XVSUBI_BU: |
| 7216 | case LoongArch::XVSUBI_DU: |
| 7217 | case LoongArch::XVSUBI_HU: |
| 7218 | case LoongArch::XVSUBI_WU: { |
| 7219 | switch (OpNum) { |
| 7220 | case 2: |
| 7221 | // op: imm5 |
| 7222 | return 10; |
| 7223 | case 1: |
| 7224 | // op: xj |
| 7225 | return 5; |
| 7226 | case 0: |
| 7227 | // op: xd |
| 7228 | return 0; |
| 7229 | } |
| 7230 | break; |
| 7231 | } |
| 7232 | case LoongArch::RCRI_D: |
| 7233 | case LoongArch::ROTRI_D: |
| 7234 | case LoongArch::SLLI_D: |
| 7235 | case LoongArch::SRAI_D: |
| 7236 | case LoongArch::SRLI_D: { |
| 7237 | switch (OpNum) { |
| 7238 | case 2: |
| 7239 | // op: imm6 |
| 7240 | return 10; |
| 7241 | case 1: |
| 7242 | // op: rj |
| 7243 | return 5; |
| 7244 | case 0: |
| 7245 | // op: rd |
| 7246 | return 0; |
| 7247 | } |
| 7248 | break; |
| 7249 | } |
| 7250 | case LoongArch::VBITCLRI_D: |
| 7251 | case LoongArch::VBITREVI_D: |
| 7252 | case LoongArch::VBITSETI_D: |
| 7253 | case LoongArch::VROTRI_D: |
| 7254 | case LoongArch::VSAT_D: |
| 7255 | case LoongArch::VSAT_DU: |
| 7256 | case LoongArch::VSLLI_D: |
| 7257 | case LoongArch::VSRAI_D: |
| 7258 | case LoongArch::VSRARI_D: |
| 7259 | case LoongArch::VSRLI_D: |
| 7260 | case LoongArch::VSRLRI_D: { |
| 7261 | switch (OpNum) { |
| 7262 | case 2: |
| 7263 | // op: imm6 |
| 7264 | return 10; |
| 7265 | case 1: |
| 7266 | // op: vj |
| 7267 | return 5; |
| 7268 | case 0: |
| 7269 | // op: vd |
| 7270 | return 0; |
| 7271 | } |
| 7272 | break; |
| 7273 | } |
| 7274 | case LoongArch::XVBITCLRI_D: |
| 7275 | case LoongArch::XVBITREVI_D: |
| 7276 | case LoongArch::XVBITSETI_D: |
| 7277 | case LoongArch::XVROTRI_D: |
| 7278 | case LoongArch::XVSAT_D: |
| 7279 | case LoongArch::XVSAT_DU: |
| 7280 | case LoongArch::XVSLLI_D: |
| 7281 | case LoongArch::XVSRAI_D: |
| 7282 | case LoongArch::XVSRARI_D: |
| 7283 | case LoongArch::XVSRLI_D: |
| 7284 | case LoongArch::XVSRLRI_D: { |
| 7285 | switch (OpNum) { |
| 7286 | case 2: |
| 7287 | // op: imm6 |
| 7288 | return 10; |
| 7289 | case 1: |
| 7290 | // op: xj |
| 7291 | return 5; |
| 7292 | case 0: |
| 7293 | // op: xd |
| 7294 | return 0; |
| 7295 | } |
| 7296 | break; |
| 7297 | } |
| 7298 | case LoongArch::X86SETTAG: { |
| 7299 | switch (OpNum) { |
| 7300 | case 2: |
| 7301 | // op: imm8 |
| 7302 | return 10; |
| 7303 | case 1: |
| 7304 | // op: imm5 |
| 7305 | return 5; |
| 7306 | case 0: |
| 7307 | // op: rd |
| 7308 | return 0; |
| 7309 | } |
| 7310 | break; |
| 7311 | } |
| 7312 | case LoongArch::LDDIR: { |
| 7313 | switch (OpNum) { |
| 7314 | case 2: |
| 7315 | // op: imm8 |
| 7316 | return 10; |
| 7317 | case 1: |
| 7318 | // op: rj |
| 7319 | return 5; |
| 7320 | case 0: |
| 7321 | // op: rd |
| 7322 | return 0; |
| 7323 | } |
| 7324 | break; |
| 7325 | } |
| 7326 | case LoongArch::VANDI_B: |
| 7327 | case LoongArch::VNORI_B: |
| 7328 | case LoongArch::VORI_B: |
| 7329 | case LoongArch::VSHUF4I_B: |
| 7330 | case LoongArch::VSHUF4I_H: |
| 7331 | case LoongArch::VSHUF4I_W: |
| 7332 | case LoongArch::VXORI_B: { |
| 7333 | switch (OpNum) { |
| 7334 | case 2: |
| 7335 | // op: imm8 |
| 7336 | return 10; |
| 7337 | case 1: |
| 7338 | // op: vj |
| 7339 | return 5; |
| 7340 | case 0: |
| 7341 | // op: vd |
| 7342 | return 0; |
| 7343 | } |
| 7344 | break; |
| 7345 | } |
| 7346 | case LoongArch::XVANDI_B: |
| 7347 | case LoongArch::XVNORI_B: |
| 7348 | case LoongArch::XVORI_B: |
| 7349 | case LoongArch::XVPERMI_D: |
| 7350 | case LoongArch::XVSHUF4I_B: |
| 7351 | case LoongArch::XVSHUF4I_H: |
| 7352 | case LoongArch::XVSHUF4I_W: |
| 7353 | case LoongArch::XVXORI_B: { |
| 7354 | switch (OpNum) { |
| 7355 | case 2: |
| 7356 | // op: imm8 |
| 7357 | return 10; |
| 7358 | case 1: |
| 7359 | // op: xj |
| 7360 | return 5; |
| 7361 | case 0: |
| 7362 | // op: xd |
| 7363 | return 0; |
| 7364 | } |
| 7365 | break; |
| 7366 | } |
| 7367 | case LoongArch::VLDREPL_D: { |
| 7368 | switch (OpNum) { |
| 7369 | case 2: |
| 7370 | // op: imm9 |
| 7371 | return 10; |
| 7372 | case 1: |
| 7373 | // op: rj |
| 7374 | return 5; |
| 7375 | case 0: |
| 7376 | // op: vd |
| 7377 | return 0; |
| 7378 | } |
| 7379 | break; |
| 7380 | } |
| 7381 | case LoongArch::XVLDREPL_D: { |
| 7382 | switch (OpNum) { |
| 7383 | case 2: |
| 7384 | // op: imm9 |
| 7385 | return 10; |
| 7386 | case 1: |
| 7387 | // op: rj |
| 7388 | return 5; |
| 7389 | case 0: |
| 7390 | // op: xd |
| 7391 | return 0; |
| 7392 | } |
| 7393 | break; |
| 7394 | } |
| 7395 | case LoongArch::BSTRPICK_D: { |
| 7396 | switch (OpNum) { |
| 7397 | case 2: |
| 7398 | // op: msbd |
| 7399 | return 16; |
| 7400 | case 3: |
| 7401 | // op: lsbd |
| 7402 | return 10; |
| 7403 | case 1: |
| 7404 | // op: rj |
| 7405 | return 5; |
| 7406 | case 0: |
| 7407 | // op: rd |
| 7408 | return 0; |
| 7409 | } |
| 7410 | break; |
| 7411 | } |
| 7412 | case LoongArch::BSTRPICK_W: { |
| 7413 | switch (OpNum) { |
| 7414 | case 2: |
| 7415 | // op: msbw |
| 7416 | return 16; |
| 7417 | case 3: |
| 7418 | // op: lsbw |
| 7419 | return 10; |
| 7420 | case 1: |
| 7421 | // op: rj |
| 7422 | return 5; |
| 7423 | case 0: |
| 7424 | // op: rd |
| 7425 | return 0; |
| 7426 | } |
| 7427 | break; |
| 7428 | } |
| 7429 | case LoongArch::SCREL_D: |
| 7430 | case LoongArch::SCREL_W: { |
| 7431 | switch (OpNum) { |
| 7432 | case 2: |
| 7433 | // op: rj |
| 7434 | return 5; |
| 7435 | case 1: |
| 7436 | // op: rd |
| 7437 | return 0; |
| 7438 | } |
| 7439 | break; |
| 7440 | } |
| 7441 | case LoongArch::FLDGT_D: |
| 7442 | case LoongArch::FLDGT_S: |
| 7443 | case LoongArch::FLDLE_D: |
| 7444 | case LoongArch::FLDLE_S: |
| 7445 | case LoongArch::FLDX_D: |
| 7446 | case LoongArch::FLDX_S: |
| 7447 | case LoongArch::FSTGT_D: |
| 7448 | case LoongArch::FSTGT_S: |
| 7449 | case LoongArch::FSTLE_D: |
| 7450 | case LoongArch::FSTLE_S: |
| 7451 | case LoongArch::FSTX_D: |
| 7452 | case LoongArch::FSTX_S: { |
| 7453 | switch (OpNum) { |
| 7454 | case 2: |
| 7455 | // op: rk |
| 7456 | return 10; |
| 7457 | case 1: |
| 7458 | // op: rj |
| 7459 | return 5; |
| 7460 | case 0: |
| 7461 | // op: fd |
| 7462 | return 0; |
| 7463 | } |
| 7464 | break; |
| 7465 | } |
| 7466 | case LoongArch::PRELDX: { |
| 7467 | switch (OpNum) { |
| 7468 | case 2: |
| 7469 | // op: rk |
| 7470 | return 10; |
| 7471 | case 1: |
| 7472 | // op: rj |
| 7473 | return 5; |
| 7474 | case 0: |
| 7475 | // op: imm5 |
| 7476 | return 0; |
| 7477 | } |
| 7478 | break; |
| 7479 | } |
| 7480 | case LoongArch::ADC_B: |
| 7481 | case LoongArch::ADC_D: |
| 7482 | case LoongArch::ADC_H: |
| 7483 | case LoongArch::ADC_W: |
| 7484 | case LoongArch::ADD_D: |
| 7485 | case LoongArch::ADD_W: |
| 7486 | case LoongArch::AND: |
| 7487 | case LoongArch::ANDN: |
| 7488 | case LoongArch::CRCC_W_B_W: |
| 7489 | case LoongArch::CRCC_W_D_W: |
| 7490 | case LoongArch::CRCC_W_H_W: |
| 7491 | case LoongArch::CRCC_W_W_W: |
| 7492 | case LoongArch::CRC_W_B_W: |
| 7493 | case LoongArch::CRC_W_D_W: |
| 7494 | case LoongArch::CRC_W_H_W: |
| 7495 | case LoongArch::CRC_W_W_W: |
| 7496 | case LoongArch::DIV_D: |
| 7497 | case LoongArch::DIV_DU: |
| 7498 | case LoongArch::DIV_W: |
| 7499 | case LoongArch::DIV_WU: |
| 7500 | case LoongArch::LDGT_B: |
| 7501 | case LoongArch::LDGT_D: |
| 7502 | case LoongArch::LDGT_H: |
| 7503 | case LoongArch::LDGT_W: |
| 7504 | case LoongArch::LDLE_B: |
| 7505 | case LoongArch::LDLE_D: |
| 7506 | case LoongArch::LDLE_H: |
| 7507 | case LoongArch::LDLE_W: |
| 7508 | case LoongArch::LDX_B: |
| 7509 | case LoongArch::LDX_BU: |
| 7510 | case LoongArch::LDX_D: |
| 7511 | case LoongArch::LDX_H: |
| 7512 | case LoongArch::LDX_HU: |
| 7513 | case LoongArch::LDX_W: |
| 7514 | case LoongArch::LDX_WU: |
| 7515 | case LoongArch::MASKEQZ: |
| 7516 | case LoongArch::MASKNEZ: |
| 7517 | case LoongArch::MOD_D: |
| 7518 | case LoongArch::MOD_DU: |
| 7519 | case LoongArch::MOD_W: |
| 7520 | case LoongArch::MOD_WU: |
| 7521 | case LoongArch::MULH_D: |
| 7522 | case LoongArch::MULH_DU: |
| 7523 | case LoongArch::MULH_W: |
| 7524 | case LoongArch::MULH_WU: |
| 7525 | case LoongArch::MULW_D_W: |
| 7526 | case LoongArch::MULW_D_WU: |
| 7527 | case LoongArch::MUL_D: |
| 7528 | case LoongArch::MUL_W: |
| 7529 | case LoongArch::NOR: |
| 7530 | case LoongArch::OR: |
| 7531 | case LoongArch::ORN: |
| 7532 | case LoongArch::RCR_B: |
| 7533 | case LoongArch::RCR_D: |
| 7534 | case LoongArch::RCR_H: |
| 7535 | case LoongArch::RCR_W: |
| 7536 | case LoongArch::ROTR_B: |
| 7537 | case LoongArch::ROTR_D: |
| 7538 | case LoongArch::ROTR_H: |
| 7539 | case LoongArch::ROTR_W: |
| 7540 | case LoongArch::SBC_B: |
| 7541 | case LoongArch::SBC_D: |
| 7542 | case LoongArch::SBC_H: |
| 7543 | case LoongArch::SBC_W: |
| 7544 | case LoongArch::SLL_D: |
| 7545 | case LoongArch::SLL_W: |
| 7546 | case LoongArch::SLT: |
| 7547 | case LoongArch::SLTU: |
| 7548 | case LoongArch::SRA_D: |
| 7549 | case LoongArch::SRA_W: |
| 7550 | case LoongArch::SRL_D: |
| 7551 | case LoongArch::SRL_W: |
| 7552 | case LoongArch::STGT_B: |
| 7553 | case LoongArch::STGT_D: |
| 7554 | case LoongArch::STGT_H: |
| 7555 | case LoongArch::STGT_W: |
| 7556 | case LoongArch::STLE_B: |
| 7557 | case LoongArch::STLE_D: |
| 7558 | case LoongArch::STLE_H: |
| 7559 | case LoongArch::STLE_W: |
| 7560 | case LoongArch::STX_B: |
| 7561 | case LoongArch::STX_D: |
| 7562 | case LoongArch::STX_H: |
| 7563 | case LoongArch::STX_W: |
| 7564 | case LoongArch::SUB_D: |
| 7565 | case LoongArch::SUB_W: |
| 7566 | case LoongArch::XOR: { |
| 7567 | switch (OpNum) { |
| 7568 | case 2: |
| 7569 | // op: rk |
| 7570 | return 10; |
| 7571 | case 1: |
| 7572 | // op: rj |
| 7573 | return 5; |
| 7574 | case 0: |
| 7575 | // op: rd |
| 7576 | return 0; |
| 7577 | } |
| 7578 | break; |
| 7579 | } |
| 7580 | case LoongArch::VLDX: |
| 7581 | case LoongArch::VSTX: { |
| 7582 | switch (OpNum) { |
| 7583 | case 2: |
| 7584 | // op: rk |
| 7585 | return 10; |
| 7586 | case 1: |
| 7587 | // op: rj |
| 7588 | return 5; |
| 7589 | case 0: |
| 7590 | // op: vd |
| 7591 | return 0; |
| 7592 | } |
| 7593 | break; |
| 7594 | } |
| 7595 | case LoongArch::XVLDX: |
| 7596 | case LoongArch::XVSTX: { |
| 7597 | switch (OpNum) { |
| 7598 | case 2: |
| 7599 | // op: rk |
| 7600 | return 10; |
| 7601 | case 1: |
| 7602 | // op: rj |
| 7603 | return 5; |
| 7604 | case 0: |
| 7605 | // op: xd |
| 7606 | return 0; |
| 7607 | } |
| 7608 | break; |
| 7609 | } |
| 7610 | case LoongArch::VREPLVE_B: |
| 7611 | case LoongArch::VREPLVE_D: |
| 7612 | case LoongArch::VREPLVE_H: |
| 7613 | case LoongArch::VREPLVE_W: { |
| 7614 | switch (OpNum) { |
| 7615 | case 2: |
| 7616 | // op: rk |
| 7617 | return 10; |
| 7618 | case 1: |
| 7619 | // op: vj |
| 7620 | return 5; |
| 7621 | case 0: |
| 7622 | // op: vd |
| 7623 | return 0; |
| 7624 | } |
| 7625 | break; |
| 7626 | } |
| 7627 | case LoongArch::XVREPLVE_B: |
| 7628 | case LoongArch::XVREPLVE_D: |
| 7629 | case LoongArch::XVREPLVE_H: |
| 7630 | case LoongArch::XVREPLVE_W: { |
| 7631 | switch (OpNum) { |
| 7632 | case 2: |
| 7633 | // op: rk |
| 7634 | return 10; |
| 7635 | case 1: |
| 7636 | // op: xj |
| 7637 | return 5; |
| 7638 | case 0: |
| 7639 | // op: xd |
| 7640 | return 0; |
| 7641 | } |
| 7642 | break; |
| 7643 | } |
| 7644 | case LoongArch::AMCAS_B: |
| 7645 | case LoongArch::AMCAS_D: |
| 7646 | case LoongArch::AMCAS_H: |
| 7647 | case LoongArch::AMCAS_W: |
| 7648 | case LoongArch::AMCAS__DB_B: |
| 7649 | case LoongArch::AMCAS__DB_D: |
| 7650 | case LoongArch::AMCAS__DB_H: |
| 7651 | case LoongArch::AMCAS__DB_W: |
| 7652 | case LoongArch::SC_Q: { |
| 7653 | switch (OpNum) { |
| 7654 | case 2: |
| 7655 | // op: rk |
| 7656 | return 10; |
| 7657 | case 3: |
| 7658 | // op: rj |
| 7659 | return 5; |
| 7660 | case 1: |
| 7661 | // op: rd |
| 7662 | return 0; |
| 7663 | } |
| 7664 | break; |
| 7665 | } |
| 7666 | case LoongArch::MOVGR2FRH_W: { |
| 7667 | switch (OpNum) { |
| 7668 | case 2: |
| 7669 | // op: src |
| 7670 | return 5; |
| 7671 | case 1: |
| 7672 | // op: dst |
| 7673 | return 0; |
| 7674 | } |
| 7675 | break; |
| 7676 | } |
| 7677 | case LoongArch::VABSD_B: |
| 7678 | case LoongArch::VABSD_BU: |
| 7679 | case LoongArch::VABSD_D: |
| 7680 | case LoongArch::VABSD_DU: |
| 7681 | case LoongArch::VABSD_H: |
| 7682 | case LoongArch::VABSD_HU: |
| 7683 | case LoongArch::VABSD_W: |
| 7684 | case LoongArch::VABSD_WU: |
| 7685 | case LoongArch::VADDA_B: |
| 7686 | case LoongArch::VADDA_D: |
| 7687 | case LoongArch::VADDA_H: |
| 7688 | case LoongArch::VADDA_W: |
| 7689 | case LoongArch::VADDWEV_D_W: |
| 7690 | case LoongArch::VADDWEV_D_WU: |
| 7691 | case LoongArch::VADDWEV_D_WU_W: |
| 7692 | case LoongArch::VADDWEV_H_B: |
| 7693 | case LoongArch::VADDWEV_H_BU: |
| 7694 | case LoongArch::VADDWEV_H_BU_B: |
| 7695 | case LoongArch::VADDWEV_Q_D: |
| 7696 | case LoongArch::VADDWEV_Q_DU: |
| 7697 | case LoongArch::VADDWEV_Q_DU_D: |
| 7698 | case LoongArch::VADDWEV_W_H: |
| 7699 | case LoongArch::VADDWEV_W_HU: |
| 7700 | case LoongArch::VADDWEV_W_HU_H: |
| 7701 | case LoongArch::VADDWOD_D_W: |
| 7702 | case LoongArch::VADDWOD_D_WU: |
| 7703 | case LoongArch::VADDWOD_D_WU_W: |
| 7704 | case LoongArch::VADDWOD_H_B: |
| 7705 | case LoongArch::VADDWOD_H_BU: |
| 7706 | case LoongArch::VADDWOD_H_BU_B: |
| 7707 | case LoongArch::VADDWOD_Q_D: |
| 7708 | case LoongArch::VADDWOD_Q_DU: |
| 7709 | case LoongArch::VADDWOD_Q_DU_D: |
| 7710 | case LoongArch::VADDWOD_W_H: |
| 7711 | case LoongArch::VADDWOD_W_HU: |
| 7712 | case LoongArch::VADDWOD_W_HU_H: |
| 7713 | case LoongArch::VADD_B: |
| 7714 | case LoongArch::VADD_D: |
| 7715 | case LoongArch::VADD_H: |
| 7716 | case LoongArch::VADD_Q: |
| 7717 | case LoongArch::VADD_W: |
| 7718 | case LoongArch::VANDN_V: |
| 7719 | case LoongArch::VAND_V: |
| 7720 | case LoongArch::VAVGR_B: |
| 7721 | case LoongArch::VAVGR_BU: |
| 7722 | case LoongArch::VAVGR_D: |
| 7723 | case LoongArch::VAVGR_DU: |
| 7724 | case LoongArch::VAVGR_H: |
| 7725 | case LoongArch::VAVGR_HU: |
| 7726 | case LoongArch::VAVGR_W: |
| 7727 | case LoongArch::VAVGR_WU: |
| 7728 | case LoongArch::VAVG_B: |
| 7729 | case LoongArch::VAVG_BU: |
| 7730 | case LoongArch::VAVG_D: |
| 7731 | case LoongArch::VAVG_DU: |
| 7732 | case LoongArch::VAVG_H: |
| 7733 | case LoongArch::VAVG_HU: |
| 7734 | case LoongArch::VAVG_W: |
| 7735 | case LoongArch::VAVG_WU: |
| 7736 | case LoongArch::VBITCLR_B: |
| 7737 | case LoongArch::VBITCLR_D: |
| 7738 | case LoongArch::VBITCLR_H: |
| 7739 | case LoongArch::VBITCLR_W: |
| 7740 | case LoongArch::VBITREV_B: |
| 7741 | case LoongArch::VBITREV_D: |
| 7742 | case LoongArch::VBITREV_H: |
| 7743 | case LoongArch::VBITREV_W: |
| 7744 | case LoongArch::VBITSET_B: |
| 7745 | case LoongArch::VBITSET_D: |
| 7746 | case LoongArch::VBITSET_H: |
| 7747 | case LoongArch::VBITSET_W: |
| 7748 | case LoongArch::VDIV_B: |
| 7749 | case LoongArch::VDIV_BU: |
| 7750 | case LoongArch::VDIV_D: |
| 7751 | case LoongArch::VDIV_DU: |
| 7752 | case LoongArch::VDIV_H: |
| 7753 | case LoongArch::VDIV_HU: |
| 7754 | case LoongArch::VDIV_W: |
| 7755 | case LoongArch::VDIV_WU: |
| 7756 | case LoongArch::VFADD_D: |
| 7757 | case LoongArch::VFADD_S: |
| 7758 | case LoongArch::VFCMP_CAF_D: |
| 7759 | case LoongArch::VFCMP_CAF_S: |
| 7760 | case LoongArch::VFCMP_CEQ_D: |
| 7761 | case LoongArch::VFCMP_CEQ_S: |
| 7762 | case LoongArch::VFCMP_CLE_D: |
| 7763 | case LoongArch::VFCMP_CLE_S: |
| 7764 | case LoongArch::VFCMP_CLT_D: |
| 7765 | case LoongArch::VFCMP_CLT_S: |
| 7766 | case LoongArch::VFCMP_CNE_D: |
| 7767 | case LoongArch::VFCMP_CNE_S: |
| 7768 | case LoongArch::VFCMP_COR_D: |
| 7769 | case LoongArch::VFCMP_COR_S: |
| 7770 | case LoongArch::VFCMP_CUEQ_D: |
| 7771 | case LoongArch::VFCMP_CUEQ_S: |
| 7772 | case LoongArch::VFCMP_CULE_D: |
| 7773 | case LoongArch::VFCMP_CULE_S: |
| 7774 | case LoongArch::VFCMP_CULT_D: |
| 7775 | case LoongArch::VFCMP_CULT_S: |
| 7776 | case LoongArch::VFCMP_CUNE_D: |
| 7777 | case LoongArch::VFCMP_CUNE_S: |
| 7778 | case LoongArch::VFCMP_CUN_D: |
| 7779 | case LoongArch::VFCMP_CUN_S: |
| 7780 | case LoongArch::VFCMP_SAF_D: |
| 7781 | case LoongArch::VFCMP_SAF_S: |
| 7782 | case LoongArch::VFCMP_SEQ_D: |
| 7783 | case LoongArch::VFCMP_SEQ_S: |
| 7784 | case LoongArch::VFCMP_SLE_D: |
| 7785 | case LoongArch::VFCMP_SLE_S: |
| 7786 | case LoongArch::VFCMP_SLT_D: |
| 7787 | case LoongArch::VFCMP_SLT_S: |
| 7788 | case LoongArch::VFCMP_SNE_D: |
| 7789 | case LoongArch::VFCMP_SNE_S: |
| 7790 | case LoongArch::VFCMP_SOR_D: |
| 7791 | case LoongArch::VFCMP_SOR_S: |
| 7792 | case LoongArch::VFCMP_SUEQ_D: |
| 7793 | case LoongArch::VFCMP_SUEQ_S: |
| 7794 | case LoongArch::VFCMP_SULE_D: |
| 7795 | case LoongArch::VFCMP_SULE_S: |
| 7796 | case LoongArch::VFCMP_SULT_D: |
| 7797 | case LoongArch::VFCMP_SULT_S: |
| 7798 | case LoongArch::VFCMP_SUNE_D: |
| 7799 | case LoongArch::VFCMP_SUNE_S: |
| 7800 | case LoongArch::VFCMP_SUN_D: |
| 7801 | case LoongArch::VFCMP_SUN_S: |
| 7802 | case LoongArch::VFCVT_H_S: |
| 7803 | case LoongArch::VFCVT_S_D: |
| 7804 | case LoongArch::VFDIV_D: |
| 7805 | case LoongArch::VFDIV_S: |
| 7806 | case LoongArch::VFFINT_S_L: |
| 7807 | case LoongArch::VFMAXA_D: |
| 7808 | case LoongArch::VFMAXA_S: |
| 7809 | case LoongArch::VFMAX_D: |
| 7810 | case LoongArch::VFMAX_S: |
| 7811 | case LoongArch::VFMINA_D: |
| 7812 | case LoongArch::VFMINA_S: |
| 7813 | case LoongArch::VFMIN_D: |
| 7814 | case LoongArch::VFMIN_S: |
| 7815 | case LoongArch::VFMUL_D: |
| 7816 | case LoongArch::VFMUL_S: |
| 7817 | case LoongArch::VFSUB_D: |
| 7818 | case LoongArch::VFSUB_S: |
| 7819 | case LoongArch::VFTINTRM_W_D: |
| 7820 | case LoongArch::VFTINTRNE_W_D: |
| 7821 | case LoongArch::VFTINTRP_W_D: |
| 7822 | case LoongArch::VFTINTRZ_W_D: |
| 7823 | case LoongArch::VFTINT_W_D: |
| 7824 | case LoongArch::VHADDW_DU_WU: |
| 7825 | case LoongArch::VHADDW_D_W: |
| 7826 | case LoongArch::VHADDW_HU_BU: |
| 7827 | case LoongArch::VHADDW_H_B: |
| 7828 | case LoongArch::VHADDW_QU_DU: |
| 7829 | case LoongArch::VHADDW_Q_D: |
| 7830 | case LoongArch::VHADDW_WU_HU: |
| 7831 | case LoongArch::VHADDW_W_H: |
| 7832 | case LoongArch::VHSUBW_DU_WU: |
| 7833 | case LoongArch::VHSUBW_D_W: |
| 7834 | case LoongArch::VHSUBW_HU_BU: |
| 7835 | case LoongArch::VHSUBW_H_B: |
| 7836 | case LoongArch::VHSUBW_QU_DU: |
| 7837 | case LoongArch::VHSUBW_Q_D: |
| 7838 | case LoongArch::VHSUBW_WU_HU: |
| 7839 | case LoongArch::VHSUBW_W_H: |
| 7840 | case LoongArch::VILVH_B: |
| 7841 | case LoongArch::VILVH_D: |
| 7842 | case LoongArch::VILVH_H: |
| 7843 | case LoongArch::VILVH_W: |
| 7844 | case LoongArch::VILVL_B: |
| 7845 | case LoongArch::VILVL_D: |
| 7846 | case LoongArch::VILVL_H: |
| 7847 | case LoongArch::VILVL_W: |
| 7848 | case LoongArch::VMAX_B: |
| 7849 | case LoongArch::VMAX_BU: |
| 7850 | case LoongArch::VMAX_D: |
| 7851 | case LoongArch::VMAX_DU: |
| 7852 | case LoongArch::VMAX_H: |
| 7853 | case LoongArch::VMAX_HU: |
| 7854 | case LoongArch::VMAX_W: |
| 7855 | case LoongArch::VMAX_WU: |
| 7856 | case LoongArch::VMIN_B: |
| 7857 | case LoongArch::VMIN_BU: |
| 7858 | case LoongArch::VMIN_D: |
| 7859 | case LoongArch::VMIN_DU: |
| 7860 | case LoongArch::VMIN_H: |
| 7861 | case LoongArch::VMIN_HU: |
| 7862 | case LoongArch::VMIN_W: |
| 7863 | case LoongArch::VMIN_WU: |
| 7864 | case LoongArch::VMOD_B: |
| 7865 | case LoongArch::VMOD_BU: |
| 7866 | case LoongArch::VMOD_D: |
| 7867 | case LoongArch::VMOD_DU: |
| 7868 | case LoongArch::VMOD_H: |
| 7869 | case LoongArch::VMOD_HU: |
| 7870 | case LoongArch::VMOD_W: |
| 7871 | case LoongArch::VMOD_WU: |
| 7872 | case LoongArch::VMUH_B: |
| 7873 | case LoongArch::VMUH_BU: |
| 7874 | case LoongArch::VMUH_D: |
| 7875 | case LoongArch::VMUH_DU: |
| 7876 | case LoongArch::VMUH_H: |
| 7877 | case LoongArch::VMUH_HU: |
| 7878 | case LoongArch::VMUH_W: |
| 7879 | case LoongArch::VMUH_WU: |
| 7880 | case LoongArch::VMULWEV_D_W: |
| 7881 | case LoongArch::VMULWEV_D_WU: |
| 7882 | case LoongArch::VMULWEV_D_WU_W: |
| 7883 | case LoongArch::VMULWEV_H_B: |
| 7884 | case LoongArch::VMULWEV_H_BU: |
| 7885 | case LoongArch::VMULWEV_H_BU_B: |
| 7886 | case LoongArch::VMULWEV_Q_D: |
| 7887 | case LoongArch::VMULWEV_Q_DU: |
| 7888 | case LoongArch::VMULWEV_Q_DU_D: |
| 7889 | case LoongArch::VMULWEV_W_H: |
| 7890 | case LoongArch::VMULWEV_W_HU: |
| 7891 | case LoongArch::VMULWEV_W_HU_H: |
| 7892 | case LoongArch::VMULWOD_D_W: |
| 7893 | case LoongArch::VMULWOD_D_WU: |
| 7894 | case LoongArch::VMULWOD_D_WU_W: |
| 7895 | case LoongArch::VMULWOD_H_B: |
| 7896 | case LoongArch::VMULWOD_H_BU: |
| 7897 | case LoongArch::VMULWOD_H_BU_B: |
| 7898 | case LoongArch::VMULWOD_Q_D: |
| 7899 | case LoongArch::VMULWOD_Q_DU: |
| 7900 | case LoongArch::VMULWOD_Q_DU_D: |
| 7901 | case LoongArch::VMULWOD_W_H: |
| 7902 | case LoongArch::VMULWOD_W_HU: |
| 7903 | case LoongArch::VMULWOD_W_HU_H: |
| 7904 | case LoongArch::VMUL_B: |
| 7905 | case LoongArch::VMUL_D: |
| 7906 | case LoongArch::VMUL_H: |
| 7907 | case LoongArch::VMUL_W: |
| 7908 | case LoongArch::VNOR_V: |
| 7909 | case LoongArch::VORN_V: |
| 7910 | case LoongArch::VOR_V: |
| 7911 | case LoongArch::VPACKEV_B: |
| 7912 | case LoongArch::VPACKEV_D: |
| 7913 | case LoongArch::VPACKEV_H: |
| 7914 | case LoongArch::VPACKEV_W: |
| 7915 | case LoongArch::VPACKOD_B: |
| 7916 | case LoongArch::VPACKOD_D: |
| 7917 | case LoongArch::VPACKOD_H: |
| 7918 | case LoongArch::VPACKOD_W: |
| 7919 | case LoongArch::VPICKEV_B: |
| 7920 | case LoongArch::VPICKEV_D: |
| 7921 | case LoongArch::VPICKEV_H: |
| 7922 | case LoongArch::VPICKEV_W: |
| 7923 | case LoongArch::VPICKOD_B: |
| 7924 | case LoongArch::VPICKOD_D: |
| 7925 | case LoongArch::VPICKOD_H: |
| 7926 | case LoongArch::VPICKOD_W: |
| 7927 | case LoongArch::VROTR_B: |
| 7928 | case LoongArch::VROTR_D: |
| 7929 | case LoongArch::VROTR_H: |
| 7930 | case LoongArch::VROTR_W: |
| 7931 | case LoongArch::VSADD_B: |
| 7932 | case LoongArch::VSADD_BU: |
| 7933 | case LoongArch::VSADD_D: |
| 7934 | case LoongArch::VSADD_DU: |
| 7935 | case LoongArch::VSADD_H: |
| 7936 | case LoongArch::VSADD_HU: |
| 7937 | case LoongArch::VSADD_W: |
| 7938 | case LoongArch::VSADD_WU: |
| 7939 | case LoongArch::VSEQ_B: |
| 7940 | case LoongArch::VSEQ_D: |
| 7941 | case LoongArch::VSEQ_H: |
| 7942 | case LoongArch::VSEQ_W: |
| 7943 | case LoongArch::VSIGNCOV_B: |
| 7944 | case LoongArch::VSIGNCOV_D: |
| 7945 | case LoongArch::VSIGNCOV_H: |
| 7946 | case LoongArch::VSIGNCOV_W: |
| 7947 | case LoongArch::VSLE_B: |
| 7948 | case LoongArch::VSLE_BU: |
| 7949 | case LoongArch::VSLE_D: |
| 7950 | case LoongArch::VSLE_DU: |
| 7951 | case LoongArch::VSLE_H: |
| 7952 | case LoongArch::VSLE_HU: |
| 7953 | case LoongArch::VSLE_W: |
| 7954 | case LoongArch::VSLE_WU: |
| 7955 | case LoongArch::VSLL_B: |
| 7956 | case LoongArch::VSLL_D: |
| 7957 | case LoongArch::VSLL_H: |
| 7958 | case LoongArch::VSLL_W: |
| 7959 | case LoongArch::VSLT_B: |
| 7960 | case LoongArch::VSLT_BU: |
| 7961 | case LoongArch::VSLT_D: |
| 7962 | case LoongArch::VSLT_DU: |
| 7963 | case LoongArch::VSLT_H: |
| 7964 | case LoongArch::VSLT_HU: |
| 7965 | case LoongArch::VSLT_W: |
| 7966 | case LoongArch::VSLT_WU: |
| 7967 | case LoongArch::VSRAN_B_H: |
| 7968 | case LoongArch::VSRAN_H_W: |
| 7969 | case LoongArch::VSRAN_W_D: |
| 7970 | case LoongArch::VSRARN_B_H: |
| 7971 | case LoongArch::VSRARN_H_W: |
| 7972 | case LoongArch::VSRARN_W_D: |
| 7973 | case LoongArch::VSRAR_B: |
| 7974 | case LoongArch::VSRAR_D: |
| 7975 | case LoongArch::VSRAR_H: |
| 7976 | case LoongArch::VSRAR_W: |
| 7977 | case LoongArch::VSRA_B: |
| 7978 | case LoongArch::VSRA_D: |
| 7979 | case LoongArch::VSRA_H: |
| 7980 | case LoongArch::VSRA_W: |
| 7981 | case LoongArch::VSRLN_B_H: |
| 7982 | case LoongArch::VSRLN_H_W: |
| 7983 | case LoongArch::VSRLN_W_D: |
| 7984 | case LoongArch::VSRLRN_B_H: |
| 7985 | case LoongArch::VSRLRN_H_W: |
| 7986 | case LoongArch::VSRLRN_W_D: |
| 7987 | case LoongArch::VSRLR_B: |
| 7988 | case LoongArch::VSRLR_D: |
| 7989 | case LoongArch::VSRLR_H: |
| 7990 | case LoongArch::VSRLR_W: |
| 7991 | case LoongArch::VSRL_B: |
| 7992 | case LoongArch::VSRL_D: |
| 7993 | case LoongArch::VSRL_H: |
| 7994 | case LoongArch::VSRL_W: |
| 7995 | case LoongArch::VSSRAN_BU_H: |
| 7996 | case LoongArch::VSSRAN_B_H: |
| 7997 | case LoongArch::VSSRAN_HU_W: |
| 7998 | case LoongArch::VSSRAN_H_W: |
| 7999 | case LoongArch::VSSRAN_WU_D: |
| 8000 | case LoongArch::VSSRAN_W_D: |
| 8001 | case LoongArch::VSSRARN_BU_H: |
| 8002 | case LoongArch::VSSRARN_B_H: |
| 8003 | case LoongArch::VSSRARN_HU_W: |
| 8004 | case LoongArch::VSSRARN_H_W: |
| 8005 | case LoongArch::VSSRARN_WU_D: |
| 8006 | case LoongArch::VSSRARN_W_D: |
| 8007 | case LoongArch::VSSRLN_BU_H: |
| 8008 | case LoongArch::VSSRLN_B_H: |
| 8009 | case LoongArch::VSSRLN_HU_W: |
| 8010 | case LoongArch::VSSRLN_H_W: |
| 8011 | case LoongArch::VSSRLN_WU_D: |
| 8012 | case LoongArch::VSSRLN_W_D: |
| 8013 | case LoongArch::VSSRLRN_BU_H: |
| 8014 | case LoongArch::VSSRLRN_B_H: |
| 8015 | case LoongArch::VSSRLRN_HU_W: |
| 8016 | case LoongArch::VSSRLRN_H_W: |
| 8017 | case LoongArch::VSSRLRN_WU_D: |
| 8018 | case LoongArch::VSSRLRN_W_D: |
| 8019 | case LoongArch::VSSUB_B: |
| 8020 | case LoongArch::VSSUB_BU: |
| 8021 | case LoongArch::VSSUB_D: |
| 8022 | case LoongArch::VSSUB_DU: |
| 8023 | case LoongArch::VSSUB_H: |
| 8024 | case LoongArch::VSSUB_HU: |
| 8025 | case LoongArch::VSSUB_W: |
| 8026 | case LoongArch::VSSUB_WU: |
| 8027 | case LoongArch::VSUBWEV_D_W: |
| 8028 | case LoongArch::VSUBWEV_D_WU: |
| 8029 | case LoongArch::VSUBWEV_H_B: |
| 8030 | case LoongArch::VSUBWEV_H_BU: |
| 8031 | case LoongArch::VSUBWEV_Q_D: |
| 8032 | case LoongArch::VSUBWEV_Q_DU: |
| 8033 | case LoongArch::VSUBWEV_W_H: |
| 8034 | case LoongArch::VSUBWEV_W_HU: |
| 8035 | case LoongArch::VSUBWOD_D_W: |
| 8036 | case LoongArch::VSUBWOD_D_WU: |
| 8037 | case LoongArch::VSUBWOD_H_B: |
| 8038 | case LoongArch::VSUBWOD_H_BU: |
| 8039 | case LoongArch::VSUBWOD_Q_D: |
| 8040 | case LoongArch::VSUBWOD_Q_DU: |
| 8041 | case LoongArch::VSUBWOD_W_H: |
| 8042 | case LoongArch::VSUBWOD_W_HU: |
| 8043 | case LoongArch::VSUB_B: |
| 8044 | case LoongArch::VSUB_D: |
| 8045 | case LoongArch::VSUB_H: |
| 8046 | case LoongArch::VSUB_Q: |
| 8047 | case LoongArch::VSUB_W: |
| 8048 | case LoongArch::VXOR_V: { |
| 8049 | switch (OpNum) { |
| 8050 | case 2: |
| 8051 | // op: vk |
| 8052 | return 10; |
| 8053 | case 1: |
| 8054 | // op: vj |
| 8055 | return 5; |
| 8056 | case 0: |
| 8057 | // op: vd |
| 8058 | return 0; |
| 8059 | } |
| 8060 | break; |
| 8061 | } |
| 8062 | case LoongArch::XVABSD_B: |
| 8063 | case LoongArch::XVABSD_BU: |
| 8064 | case LoongArch::XVABSD_D: |
| 8065 | case LoongArch::XVABSD_DU: |
| 8066 | case LoongArch::XVABSD_H: |
| 8067 | case LoongArch::XVABSD_HU: |
| 8068 | case LoongArch::XVABSD_W: |
| 8069 | case LoongArch::XVABSD_WU: |
| 8070 | case LoongArch::XVADDA_B: |
| 8071 | case LoongArch::XVADDA_D: |
| 8072 | case LoongArch::XVADDA_H: |
| 8073 | case LoongArch::XVADDA_W: |
| 8074 | case LoongArch::XVADDWEV_D_W: |
| 8075 | case LoongArch::XVADDWEV_D_WU: |
| 8076 | case LoongArch::XVADDWEV_D_WU_W: |
| 8077 | case LoongArch::XVADDWEV_H_B: |
| 8078 | case LoongArch::XVADDWEV_H_BU: |
| 8079 | case LoongArch::XVADDWEV_H_BU_B: |
| 8080 | case LoongArch::XVADDWEV_Q_D: |
| 8081 | case LoongArch::XVADDWEV_Q_DU: |
| 8082 | case LoongArch::XVADDWEV_Q_DU_D: |
| 8083 | case LoongArch::XVADDWEV_W_H: |
| 8084 | case LoongArch::XVADDWEV_W_HU: |
| 8085 | case LoongArch::XVADDWEV_W_HU_H: |
| 8086 | case LoongArch::XVADDWOD_D_W: |
| 8087 | case LoongArch::XVADDWOD_D_WU: |
| 8088 | case LoongArch::XVADDWOD_D_WU_W: |
| 8089 | case LoongArch::XVADDWOD_H_B: |
| 8090 | case LoongArch::XVADDWOD_H_BU: |
| 8091 | case LoongArch::XVADDWOD_H_BU_B: |
| 8092 | case LoongArch::XVADDWOD_Q_D: |
| 8093 | case LoongArch::XVADDWOD_Q_DU: |
| 8094 | case LoongArch::XVADDWOD_Q_DU_D: |
| 8095 | case LoongArch::XVADDWOD_W_H: |
| 8096 | case LoongArch::XVADDWOD_W_HU: |
| 8097 | case LoongArch::XVADDWOD_W_HU_H: |
| 8098 | case LoongArch::XVADD_B: |
| 8099 | case LoongArch::XVADD_D: |
| 8100 | case LoongArch::XVADD_H: |
| 8101 | case LoongArch::XVADD_Q: |
| 8102 | case LoongArch::XVADD_W: |
| 8103 | case LoongArch::XVANDN_V: |
| 8104 | case LoongArch::XVAND_V: |
| 8105 | case LoongArch::XVAVGR_B: |
| 8106 | case LoongArch::XVAVGR_BU: |
| 8107 | case LoongArch::XVAVGR_D: |
| 8108 | case LoongArch::XVAVGR_DU: |
| 8109 | case LoongArch::XVAVGR_H: |
| 8110 | case LoongArch::XVAVGR_HU: |
| 8111 | case LoongArch::XVAVGR_W: |
| 8112 | case LoongArch::XVAVGR_WU: |
| 8113 | case LoongArch::XVAVG_B: |
| 8114 | case LoongArch::XVAVG_BU: |
| 8115 | case LoongArch::XVAVG_D: |
| 8116 | case LoongArch::XVAVG_DU: |
| 8117 | case LoongArch::XVAVG_H: |
| 8118 | case LoongArch::XVAVG_HU: |
| 8119 | case LoongArch::XVAVG_W: |
| 8120 | case LoongArch::XVAVG_WU: |
| 8121 | case LoongArch::XVBITCLR_B: |
| 8122 | case LoongArch::XVBITCLR_D: |
| 8123 | case LoongArch::XVBITCLR_H: |
| 8124 | case LoongArch::XVBITCLR_W: |
| 8125 | case LoongArch::XVBITREV_B: |
| 8126 | case LoongArch::XVBITREV_D: |
| 8127 | case LoongArch::XVBITREV_H: |
| 8128 | case LoongArch::XVBITREV_W: |
| 8129 | case LoongArch::XVBITSET_B: |
| 8130 | case LoongArch::XVBITSET_D: |
| 8131 | case LoongArch::XVBITSET_H: |
| 8132 | case LoongArch::XVBITSET_W: |
| 8133 | case LoongArch::XVDIV_B: |
| 8134 | case LoongArch::XVDIV_BU: |
| 8135 | case LoongArch::XVDIV_D: |
| 8136 | case LoongArch::XVDIV_DU: |
| 8137 | case LoongArch::XVDIV_H: |
| 8138 | case LoongArch::XVDIV_HU: |
| 8139 | case LoongArch::XVDIV_W: |
| 8140 | case LoongArch::XVDIV_WU: |
| 8141 | case LoongArch::XVFADD_D: |
| 8142 | case LoongArch::XVFADD_S: |
| 8143 | case LoongArch::XVFCMP_CAF_D: |
| 8144 | case LoongArch::XVFCMP_CAF_S: |
| 8145 | case LoongArch::XVFCMP_CEQ_D: |
| 8146 | case LoongArch::XVFCMP_CEQ_S: |
| 8147 | case LoongArch::XVFCMP_CLE_D: |
| 8148 | case LoongArch::XVFCMP_CLE_S: |
| 8149 | case LoongArch::XVFCMP_CLT_D: |
| 8150 | case LoongArch::XVFCMP_CLT_S: |
| 8151 | case LoongArch::XVFCMP_CNE_D: |
| 8152 | case LoongArch::XVFCMP_CNE_S: |
| 8153 | case LoongArch::XVFCMP_COR_D: |
| 8154 | case LoongArch::XVFCMP_COR_S: |
| 8155 | case LoongArch::XVFCMP_CUEQ_D: |
| 8156 | case LoongArch::XVFCMP_CUEQ_S: |
| 8157 | case LoongArch::XVFCMP_CULE_D: |
| 8158 | case LoongArch::XVFCMP_CULE_S: |
| 8159 | case LoongArch::XVFCMP_CULT_D: |
| 8160 | case LoongArch::XVFCMP_CULT_S: |
| 8161 | case LoongArch::XVFCMP_CUNE_D: |
| 8162 | case LoongArch::XVFCMP_CUNE_S: |
| 8163 | case LoongArch::XVFCMP_CUN_D: |
| 8164 | case LoongArch::XVFCMP_CUN_S: |
| 8165 | case LoongArch::XVFCMP_SAF_D: |
| 8166 | case LoongArch::XVFCMP_SAF_S: |
| 8167 | case LoongArch::XVFCMP_SEQ_D: |
| 8168 | case LoongArch::XVFCMP_SEQ_S: |
| 8169 | case LoongArch::XVFCMP_SLE_D: |
| 8170 | case LoongArch::XVFCMP_SLE_S: |
| 8171 | case LoongArch::XVFCMP_SLT_D: |
| 8172 | case LoongArch::XVFCMP_SLT_S: |
| 8173 | case LoongArch::XVFCMP_SNE_D: |
| 8174 | case LoongArch::XVFCMP_SNE_S: |
| 8175 | case LoongArch::XVFCMP_SOR_D: |
| 8176 | case LoongArch::XVFCMP_SOR_S: |
| 8177 | case LoongArch::XVFCMP_SUEQ_D: |
| 8178 | case LoongArch::XVFCMP_SUEQ_S: |
| 8179 | case LoongArch::XVFCMP_SULE_D: |
| 8180 | case LoongArch::XVFCMP_SULE_S: |
| 8181 | case LoongArch::XVFCMP_SULT_D: |
| 8182 | case LoongArch::XVFCMP_SULT_S: |
| 8183 | case LoongArch::XVFCMP_SUNE_D: |
| 8184 | case LoongArch::XVFCMP_SUNE_S: |
| 8185 | case LoongArch::XVFCMP_SUN_D: |
| 8186 | case LoongArch::XVFCMP_SUN_S: |
| 8187 | case LoongArch::XVFCVT_H_S: |
| 8188 | case LoongArch::XVFCVT_S_D: |
| 8189 | case LoongArch::XVFDIV_D: |
| 8190 | case LoongArch::XVFDIV_S: |
| 8191 | case LoongArch::XVFFINT_S_L: |
| 8192 | case LoongArch::XVFMAXA_D: |
| 8193 | case LoongArch::XVFMAXA_S: |
| 8194 | case LoongArch::XVFMAX_D: |
| 8195 | case LoongArch::XVFMAX_S: |
| 8196 | case LoongArch::XVFMINA_D: |
| 8197 | case LoongArch::XVFMINA_S: |
| 8198 | case LoongArch::XVFMIN_D: |
| 8199 | case LoongArch::XVFMIN_S: |
| 8200 | case LoongArch::XVFMUL_D: |
| 8201 | case LoongArch::XVFMUL_S: |
| 8202 | case LoongArch::XVFSUB_D: |
| 8203 | case LoongArch::XVFSUB_S: |
| 8204 | case LoongArch::XVFTINTRM_W_D: |
| 8205 | case LoongArch::XVFTINTRNE_W_D: |
| 8206 | case LoongArch::XVFTINTRP_W_D: |
| 8207 | case LoongArch::XVFTINTRZ_W_D: |
| 8208 | case LoongArch::XVFTINT_W_D: |
| 8209 | case LoongArch::XVHADDW_DU_WU: |
| 8210 | case LoongArch::XVHADDW_D_W: |
| 8211 | case LoongArch::XVHADDW_HU_BU: |
| 8212 | case LoongArch::XVHADDW_H_B: |
| 8213 | case LoongArch::XVHADDW_QU_DU: |
| 8214 | case LoongArch::XVHADDW_Q_D: |
| 8215 | case LoongArch::XVHADDW_WU_HU: |
| 8216 | case LoongArch::XVHADDW_W_H: |
| 8217 | case LoongArch::XVHSUBW_DU_WU: |
| 8218 | case LoongArch::XVHSUBW_D_W: |
| 8219 | case LoongArch::XVHSUBW_HU_BU: |
| 8220 | case LoongArch::XVHSUBW_H_B: |
| 8221 | case LoongArch::XVHSUBW_QU_DU: |
| 8222 | case LoongArch::XVHSUBW_Q_D: |
| 8223 | case LoongArch::XVHSUBW_WU_HU: |
| 8224 | case LoongArch::XVHSUBW_W_H: |
| 8225 | case LoongArch::XVILVH_B: |
| 8226 | case LoongArch::XVILVH_D: |
| 8227 | case LoongArch::XVILVH_H: |
| 8228 | case LoongArch::XVILVH_W: |
| 8229 | case LoongArch::XVILVL_B: |
| 8230 | case LoongArch::XVILVL_D: |
| 8231 | case LoongArch::XVILVL_H: |
| 8232 | case LoongArch::XVILVL_W: |
| 8233 | case LoongArch::XVMAX_B: |
| 8234 | case LoongArch::XVMAX_BU: |
| 8235 | case LoongArch::XVMAX_D: |
| 8236 | case LoongArch::XVMAX_DU: |
| 8237 | case LoongArch::XVMAX_H: |
| 8238 | case LoongArch::XVMAX_HU: |
| 8239 | case LoongArch::XVMAX_W: |
| 8240 | case LoongArch::XVMAX_WU: |
| 8241 | case LoongArch::XVMIN_B: |
| 8242 | case LoongArch::XVMIN_BU: |
| 8243 | case LoongArch::XVMIN_D: |
| 8244 | case LoongArch::XVMIN_DU: |
| 8245 | case LoongArch::XVMIN_H: |
| 8246 | case LoongArch::XVMIN_HU: |
| 8247 | case LoongArch::XVMIN_W: |
| 8248 | case LoongArch::XVMIN_WU: |
| 8249 | case LoongArch::XVMOD_B: |
| 8250 | case LoongArch::XVMOD_BU: |
| 8251 | case LoongArch::XVMOD_D: |
| 8252 | case LoongArch::XVMOD_DU: |
| 8253 | case LoongArch::XVMOD_H: |
| 8254 | case LoongArch::XVMOD_HU: |
| 8255 | case LoongArch::XVMOD_W: |
| 8256 | case LoongArch::XVMOD_WU: |
| 8257 | case LoongArch::XVMUH_B: |
| 8258 | case LoongArch::XVMUH_BU: |
| 8259 | case LoongArch::XVMUH_D: |
| 8260 | case LoongArch::XVMUH_DU: |
| 8261 | case LoongArch::XVMUH_H: |
| 8262 | case LoongArch::XVMUH_HU: |
| 8263 | case LoongArch::XVMUH_W: |
| 8264 | case LoongArch::XVMUH_WU: |
| 8265 | case LoongArch::XVMULWEV_D_W: |
| 8266 | case LoongArch::XVMULWEV_D_WU: |
| 8267 | case LoongArch::XVMULWEV_D_WU_W: |
| 8268 | case LoongArch::XVMULWEV_H_B: |
| 8269 | case LoongArch::XVMULWEV_H_BU: |
| 8270 | case LoongArch::XVMULWEV_H_BU_B: |
| 8271 | case LoongArch::XVMULWEV_Q_D: |
| 8272 | case LoongArch::XVMULWEV_Q_DU: |
| 8273 | case LoongArch::XVMULWEV_Q_DU_D: |
| 8274 | case LoongArch::XVMULWEV_W_H: |
| 8275 | case LoongArch::XVMULWEV_W_HU: |
| 8276 | case LoongArch::XVMULWEV_W_HU_H: |
| 8277 | case LoongArch::XVMULWOD_D_W: |
| 8278 | case LoongArch::XVMULWOD_D_WU: |
| 8279 | case LoongArch::XVMULWOD_D_WU_W: |
| 8280 | case LoongArch::XVMULWOD_H_B: |
| 8281 | case LoongArch::XVMULWOD_H_BU: |
| 8282 | case LoongArch::XVMULWOD_H_BU_B: |
| 8283 | case LoongArch::XVMULWOD_Q_D: |
| 8284 | case LoongArch::XVMULWOD_Q_DU: |
| 8285 | case LoongArch::XVMULWOD_Q_DU_D: |
| 8286 | case LoongArch::XVMULWOD_W_H: |
| 8287 | case LoongArch::XVMULWOD_W_HU: |
| 8288 | case LoongArch::XVMULWOD_W_HU_H: |
| 8289 | case LoongArch::XVMUL_B: |
| 8290 | case LoongArch::XVMUL_D: |
| 8291 | case LoongArch::XVMUL_H: |
| 8292 | case LoongArch::XVMUL_W: |
| 8293 | case LoongArch::XVNOR_V: |
| 8294 | case LoongArch::XVORN_V: |
| 8295 | case LoongArch::XVOR_V: |
| 8296 | case LoongArch::XVPACKEV_B: |
| 8297 | case LoongArch::XVPACKEV_D: |
| 8298 | case LoongArch::XVPACKEV_H: |
| 8299 | case LoongArch::XVPACKEV_W: |
| 8300 | case LoongArch::XVPACKOD_B: |
| 8301 | case LoongArch::XVPACKOD_D: |
| 8302 | case LoongArch::XVPACKOD_H: |
| 8303 | case LoongArch::XVPACKOD_W: |
| 8304 | case LoongArch::XVPERM_W: |
| 8305 | case LoongArch::XVPICKEV_B: |
| 8306 | case LoongArch::XVPICKEV_D: |
| 8307 | case LoongArch::XVPICKEV_H: |
| 8308 | case LoongArch::XVPICKEV_W: |
| 8309 | case LoongArch::XVPICKOD_B: |
| 8310 | case LoongArch::XVPICKOD_D: |
| 8311 | case LoongArch::XVPICKOD_H: |
| 8312 | case LoongArch::XVPICKOD_W: |
| 8313 | case LoongArch::XVROTR_B: |
| 8314 | case LoongArch::XVROTR_D: |
| 8315 | case LoongArch::XVROTR_H: |
| 8316 | case LoongArch::XVROTR_W: |
| 8317 | case LoongArch::XVSADD_B: |
| 8318 | case LoongArch::XVSADD_BU: |
| 8319 | case LoongArch::XVSADD_D: |
| 8320 | case LoongArch::XVSADD_DU: |
| 8321 | case LoongArch::XVSADD_H: |
| 8322 | case LoongArch::XVSADD_HU: |
| 8323 | case LoongArch::XVSADD_W: |
| 8324 | case LoongArch::XVSADD_WU: |
| 8325 | case LoongArch::XVSEQ_B: |
| 8326 | case LoongArch::XVSEQ_D: |
| 8327 | case LoongArch::XVSEQ_H: |
| 8328 | case LoongArch::XVSEQ_W: |
| 8329 | case LoongArch::XVSIGNCOV_B: |
| 8330 | case LoongArch::XVSIGNCOV_D: |
| 8331 | case LoongArch::XVSIGNCOV_H: |
| 8332 | case LoongArch::XVSIGNCOV_W: |
| 8333 | case LoongArch::XVSLE_B: |
| 8334 | case LoongArch::XVSLE_BU: |
| 8335 | case LoongArch::XVSLE_D: |
| 8336 | case LoongArch::XVSLE_DU: |
| 8337 | case LoongArch::XVSLE_H: |
| 8338 | case LoongArch::XVSLE_HU: |
| 8339 | case LoongArch::XVSLE_W: |
| 8340 | case LoongArch::XVSLE_WU: |
| 8341 | case LoongArch::XVSLL_B: |
| 8342 | case LoongArch::XVSLL_D: |
| 8343 | case LoongArch::XVSLL_H: |
| 8344 | case LoongArch::XVSLL_W: |
| 8345 | case LoongArch::XVSLT_B: |
| 8346 | case LoongArch::XVSLT_BU: |
| 8347 | case LoongArch::XVSLT_D: |
| 8348 | case LoongArch::XVSLT_DU: |
| 8349 | case LoongArch::XVSLT_H: |
| 8350 | case LoongArch::XVSLT_HU: |
| 8351 | case LoongArch::XVSLT_W: |
| 8352 | case LoongArch::XVSLT_WU: |
| 8353 | case LoongArch::XVSRAN_B_H: |
| 8354 | case LoongArch::XVSRAN_H_W: |
| 8355 | case LoongArch::XVSRAN_W_D: |
| 8356 | case LoongArch::XVSRARN_B_H: |
| 8357 | case LoongArch::XVSRARN_H_W: |
| 8358 | case LoongArch::XVSRARN_W_D: |
| 8359 | case LoongArch::XVSRAR_B: |
| 8360 | case LoongArch::XVSRAR_D: |
| 8361 | case LoongArch::XVSRAR_H: |
| 8362 | case LoongArch::XVSRAR_W: |
| 8363 | case LoongArch::XVSRA_B: |
| 8364 | case LoongArch::XVSRA_D: |
| 8365 | case LoongArch::XVSRA_H: |
| 8366 | case LoongArch::XVSRA_W: |
| 8367 | case LoongArch::XVSRLN_B_H: |
| 8368 | case LoongArch::XVSRLN_H_W: |
| 8369 | case LoongArch::XVSRLN_W_D: |
| 8370 | case LoongArch::XVSRLRN_B_H: |
| 8371 | case LoongArch::XVSRLRN_H_W: |
| 8372 | case LoongArch::XVSRLRN_W_D: |
| 8373 | case LoongArch::XVSRLR_B: |
| 8374 | case LoongArch::XVSRLR_D: |
| 8375 | case LoongArch::XVSRLR_H: |
| 8376 | case LoongArch::XVSRLR_W: |
| 8377 | case LoongArch::XVSRL_B: |
| 8378 | case LoongArch::XVSRL_D: |
| 8379 | case LoongArch::XVSRL_H: |
| 8380 | case LoongArch::XVSRL_W: |
| 8381 | case LoongArch::XVSSRAN_BU_H: |
| 8382 | case LoongArch::XVSSRAN_B_H: |
| 8383 | case LoongArch::XVSSRAN_HU_W: |
| 8384 | case LoongArch::XVSSRAN_H_W: |
| 8385 | case LoongArch::XVSSRAN_WU_D: |
| 8386 | case LoongArch::XVSSRAN_W_D: |
| 8387 | case LoongArch::XVSSRARN_BU_H: |
| 8388 | case LoongArch::XVSSRARN_B_H: |
| 8389 | case LoongArch::XVSSRARN_HU_W: |
| 8390 | case LoongArch::XVSSRARN_H_W: |
| 8391 | case LoongArch::XVSSRARN_WU_D: |
| 8392 | case LoongArch::XVSSRARN_W_D: |
| 8393 | case LoongArch::XVSSRLN_BU_H: |
| 8394 | case LoongArch::XVSSRLN_B_H: |
| 8395 | case LoongArch::XVSSRLN_HU_W: |
| 8396 | case LoongArch::XVSSRLN_H_W: |
| 8397 | case LoongArch::XVSSRLN_WU_D: |
| 8398 | case LoongArch::XVSSRLN_W_D: |
| 8399 | case LoongArch::XVSSRLRN_BU_H: |
| 8400 | case LoongArch::XVSSRLRN_B_H: |
| 8401 | case LoongArch::XVSSRLRN_HU_W: |
| 8402 | case LoongArch::XVSSRLRN_H_W: |
| 8403 | case LoongArch::XVSSRLRN_WU_D: |
| 8404 | case LoongArch::XVSSRLRN_W_D: |
| 8405 | case LoongArch::XVSSUB_B: |
| 8406 | case LoongArch::XVSSUB_BU: |
| 8407 | case LoongArch::XVSSUB_D: |
| 8408 | case LoongArch::XVSSUB_DU: |
| 8409 | case LoongArch::XVSSUB_H: |
| 8410 | case LoongArch::XVSSUB_HU: |
| 8411 | case LoongArch::XVSSUB_W: |
| 8412 | case LoongArch::XVSSUB_WU: |
| 8413 | case LoongArch::XVSUBWEV_D_W: |
| 8414 | case LoongArch::XVSUBWEV_D_WU: |
| 8415 | case LoongArch::XVSUBWEV_H_B: |
| 8416 | case LoongArch::XVSUBWEV_H_BU: |
| 8417 | case LoongArch::XVSUBWEV_Q_D: |
| 8418 | case LoongArch::XVSUBWEV_Q_DU: |
| 8419 | case LoongArch::XVSUBWEV_W_H: |
| 8420 | case LoongArch::XVSUBWEV_W_HU: |
| 8421 | case LoongArch::XVSUBWOD_D_W: |
| 8422 | case LoongArch::XVSUBWOD_D_WU: |
| 8423 | case LoongArch::XVSUBWOD_H_B: |
| 8424 | case LoongArch::XVSUBWOD_H_BU: |
| 8425 | case LoongArch::XVSUBWOD_Q_D: |
| 8426 | case LoongArch::XVSUBWOD_Q_DU: |
| 8427 | case LoongArch::XVSUBWOD_W_H: |
| 8428 | case LoongArch::XVSUBWOD_W_HU: |
| 8429 | case LoongArch::XVSUB_B: |
| 8430 | case LoongArch::XVSUB_D: |
| 8431 | case LoongArch::XVSUB_H: |
| 8432 | case LoongArch::XVSUB_Q: |
| 8433 | case LoongArch::XVSUB_W: |
| 8434 | case LoongArch::XVXOR_V: { |
| 8435 | switch (OpNum) { |
| 8436 | case 2: |
| 8437 | // op: xk |
| 8438 | return 10; |
| 8439 | case 1: |
| 8440 | // op: xj |
| 8441 | return 5; |
| 8442 | case 0: |
| 8443 | // op: xd |
| 8444 | return 0; |
| 8445 | } |
| 8446 | break; |
| 8447 | } |
| 8448 | case LoongArch::FSEL_xD: |
| 8449 | case LoongArch::FSEL_xS: { |
| 8450 | switch (OpNum) { |
| 8451 | case 3: |
| 8452 | // op: ca |
| 8453 | return 15; |
| 8454 | case 2: |
| 8455 | // op: fk |
| 8456 | return 10; |
| 8457 | case 1: |
| 8458 | // op: fj |
| 8459 | return 5; |
| 8460 | case 0: |
| 8461 | // op: fd |
| 8462 | return 0; |
| 8463 | } |
| 8464 | break; |
| 8465 | } |
| 8466 | case LoongArch::CSRXCHG: |
| 8467 | case LoongArch::GCSRXCHG: { |
| 8468 | switch (OpNum) { |
| 8469 | case 3: |
| 8470 | // op: csr_num |
| 8471 | return 10; |
| 8472 | case 2: |
| 8473 | // op: rj |
| 8474 | return 5; |
| 8475 | case 1: |
| 8476 | // op: rd |
| 8477 | return 0; |
| 8478 | } |
| 8479 | break; |
| 8480 | } |
| 8481 | case LoongArch::FMADD_D: |
| 8482 | case LoongArch::FMADD_S: |
| 8483 | case LoongArch::FMSUB_D: |
| 8484 | case LoongArch::FMSUB_S: |
| 8485 | case LoongArch::FNMADD_D: |
| 8486 | case LoongArch::FNMADD_S: |
| 8487 | case LoongArch::FNMSUB_D: |
| 8488 | case LoongArch::FNMSUB_S: { |
| 8489 | switch (OpNum) { |
| 8490 | case 3: |
| 8491 | // op: fa |
| 8492 | return 15; |
| 8493 | case 2: |
| 8494 | // op: fk |
| 8495 | return 10; |
| 8496 | case 1: |
| 8497 | // op: fj |
| 8498 | return 5; |
| 8499 | case 0: |
| 8500 | // op: fd |
| 8501 | return 0; |
| 8502 | } |
| 8503 | break; |
| 8504 | } |
| 8505 | case LoongArch::VINSGR2VR_D: { |
| 8506 | switch (OpNum) { |
| 8507 | case 3: |
| 8508 | // op: imm1 |
| 8509 | return 10; |
| 8510 | case 2: |
| 8511 | // op: rj |
| 8512 | return 5; |
| 8513 | case 1: |
| 8514 | // op: vd |
| 8515 | return 0; |
| 8516 | } |
| 8517 | break; |
| 8518 | } |
| 8519 | case LoongArch::VSTELM_D: { |
| 8520 | switch (OpNum) { |
| 8521 | case 3: |
| 8522 | // op: imm1 |
| 8523 | return 18; |
| 8524 | case 2: |
| 8525 | // op: imm8 |
| 8526 | return 10; |
| 8527 | case 1: |
| 8528 | // op: rj |
| 8529 | return 5; |
| 8530 | case 0: |
| 8531 | // op: vd |
| 8532 | return 0; |
| 8533 | } |
| 8534 | break; |
| 8535 | } |
| 8536 | case LoongArch::SC_D: |
| 8537 | case LoongArch::SC_W: { |
| 8538 | switch (OpNum) { |
| 8539 | case 3: |
| 8540 | // op: imm14 |
| 8541 | return 10; |
| 8542 | case 2: |
| 8543 | // op: rj |
| 8544 | return 5; |
| 8545 | case 1: |
| 8546 | // op: rd |
| 8547 | return 0; |
| 8548 | } |
| 8549 | break; |
| 8550 | } |
| 8551 | case LoongArch::VINSGR2VR_W: { |
| 8552 | switch (OpNum) { |
| 8553 | case 3: |
| 8554 | // op: imm2 |
| 8555 | return 10; |
| 8556 | case 2: |
| 8557 | // op: rj |
| 8558 | return 5; |
| 8559 | case 1: |
| 8560 | // op: vd |
| 8561 | return 0; |
| 8562 | } |
| 8563 | break; |
| 8564 | } |
| 8565 | case LoongArch::XVINSGR2VR_D: { |
| 8566 | switch (OpNum) { |
| 8567 | case 3: |
| 8568 | // op: imm2 |
| 8569 | return 10; |
| 8570 | case 2: |
| 8571 | // op: rj |
| 8572 | return 5; |
| 8573 | case 1: |
| 8574 | // op: xd |
| 8575 | return 0; |
| 8576 | } |
| 8577 | break; |
| 8578 | } |
| 8579 | case LoongArch::XVINSVE0_D: { |
| 8580 | switch (OpNum) { |
| 8581 | case 3: |
| 8582 | // op: imm2 |
| 8583 | return 10; |
| 8584 | case 2: |
| 8585 | // op: xj |
| 8586 | return 5; |
| 8587 | case 1: |
| 8588 | // op: xd |
| 8589 | return 0; |
| 8590 | } |
| 8591 | break; |
| 8592 | } |
| 8593 | case LoongArch::ALSL_D: |
| 8594 | case LoongArch::ALSL_W: |
| 8595 | case LoongArch::ALSL_WU: |
| 8596 | case LoongArch::BYTEPICK_W: { |
| 8597 | switch (OpNum) { |
| 8598 | case 3: |
| 8599 | // op: imm2 |
| 8600 | return 15; |
| 8601 | case 2: |
| 8602 | // op: rk |
| 8603 | return 10; |
| 8604 | case 1: |
| 8605 | // op: rj |
| 8606 | return 5; |
| 8607 | case 0: |
| 8608 | // op: rd |
| 8609 | return 0; |
| 8610 | } |
| 8611 | break; |
| 8612 | } |
| 8613 | case LoongArch::VSTELM_W: { |
| 8614 | switch (OpNum) { |
| 8615 | case 3: |
| 8616 | // op: imm2 |
| 8617 | return 18; |
| 8618 | case 2: |
| 8619 | // op: imm8 |
| 8620 | return 10; |
| 8621 | case 1: |
| 8622 | // op: rj |
| 8623 | return 5; |
| 8624 | case 0: |
| 8625 | // op: vd |
| 8626 | return 0; |
| 8627 | } |
| 8628 | break; |
| 8629 | } |
| 8630 | case LoongArch::XVSTELM_D: { |
| 8631 | switch (OpNum) { |
| 8632 | case 3: |
| 8633 | // op: imm2 |
| 8634 | return 18; |
| 8635 | case 2: |
| 8636 | // op: imm8 |
| 8637 | return 10; |
| 8638 | case 1: |
| 8639 | // op: rj |
| 8640 | return 5; |
| 8641 | case 0: |
| 8642 | // op: xd |
| 8643 | return 0; |
| 8644 | } |
| 8645 | break; |
| 8646 | } |
| 8647 | case LoongArch::VINSGR2VR_H: { |
| 8648 | switch (OpNum) { |
| 8649 | case 3: |
| 8650 | // op: imm3 |
| 8651 | return 10; |
| 8652 | case 2: |
| 8653 | // op: rj |
| 8654 | return 5; |
| 8655 | case 1: |
| 8656 | // op: vd |
| 8657 | return 0; |
| 8658 | } |
| 8659 | break; |
| 8660 | } |
| 8661 | case LoongArch::XVINSGR2VR_W: { |
| 8662 | switch (OpNum) { |
| 8663 | case 3: |
| 8664 | // op: imm3 |
| 8665 | return 10; |
| 8666 | case 2: |
| 8667 | // op: rj |
| 8668 | return 5; |
| 8669 | case 1: |
| 8670 | // op: xd |
| 8671 | return 0; |
| 8672 | } |
| 8673 | break; |
| 8674 | } |
| 8675 | case LoongArch::XVINSVE0_W: { |
| 8676 | switch (OpNum) { |
| 8677 | case 3: |
| 8678 | // op: imm3 |
| 8679 | return 10; |
| 8680 | case 2: |
| 8681 | // op: xj |
| 8682 | return 5; |
| 8683 | case 1: |
| 8684 | // op: xd |
| 8685 | return 0; |
| 8686 | } |
| 8687 | break; |
| 8688 | } |
| 8689 | case LoongArch::BYTEPICK_D: { |
| 8690 | switch (OpNum) { |
| 8691 | case 3: |
| 8692 | // op: imm3 |
| 8693 | return 15; |
| 8694 | case 2: |
| 8695 | // op: rk |
| 8696 | return 10; |
| 8697 | case 1: |
| 8698 | // op: rj |
| 8699 | return 5; |
| 8700 | case 0: |
| 8701 | // op: rd |
| 8702 | return 0; |
| 8703 | } |
| 8704 | break; |
| 8705 | } |
| 8706 | case LoongArch::VSTELM_H: { |
| 8707 | switch (OpNum) { |
| 8708 | case 3: |
| 8709 | // op: imm3 |
| 8710 | return 18; |
| 8711 | case 2: |
| 8712 | // op: imm8 |
| 8713 | return 10; |
| 8714 | case 1: |
| 8715 | // op: rj |
| 8716 | return 5; |
| 8717 | case 0: |
| 8718 | // op: vd |
| 8719 | return 0; |
| 8720 | } |
| 8721 | break; |
| 8722 | } |
| 8723 | case LoongArch::XVSTELM_W: { |
| 8724 | switch (OpNum) { |
| 8725 | case 3: |
| 8726 | // op: imm3 |
| 8727 | return 18; |
| 8728 | case 2: |
| 8729 | // op: imm8 |
| 8730 | return 10; |
| 8731 | case 1: |
| 8732 | // op: rj |
| 8733 | return 5; |
| 8734 | case 0: |
| 8735 | // op: xd |
| 8736 | return 0; |
| 8737 | } |
| 8738 | break; |
| 8739 | } |
| 8740 | case LoongArch::VINSGR2VR_B: { |
| 8741 | switch (OpNum) { |
| 8742 | case 3: |
| 8743 | // op: imm4 |
| 8744 | return 10; |
| 8745 | case 2: |
| 8746 | // op: rj |
| 8747 | return 5; |
| 8748 | case 1: |
| 8749 | // op: vd |
| 8750 | return 0; |
| 8751 | } |
| 8752 | break; |
| 8753 | } |
| 8754 | case LoongArch::VSRANI_B_H: |
| 8755 | case LoongArch::VSRARNI_B_H: |
| 8756 | case LoongArch::VSRLNI_B_H: |
| 8757 | case LoongArch::VSRLRNI_B_H: |
| 8758 | case LoongArch::VSSRANI_BU_H: |
| 8759 | case LoongArch::VSSRANI_B_H: |
| 8760 | case LoongArch::VSSRARNI_BU_H: |
| 8761 | case LoongArch::VSSRARNI_B_H: |
| 8762 | case LoongArch::VSSRLNI_BU_H: |
| 8763 | case LoongArch::VSSRLNI_B_H: |
| 8764 | case LoongArch::VSSRLRNI_BU_H: |
| 8765 | case LoongArch::VSSRLRNI_B_H: { |
| 8766 | switch (OpNum) { |
| 8767 | case 3: |
| 8768 | // op: imm4 |
| 8769 | return 10; |
| 8770 | case 2: |
| 8771 | // op: vj |
| 8772 | return 5; |
| 8773 | case 1: |
| 8774 | // op: vd |
| 8775 | return 0; |
| 8776 | } |
| 8777 | break; |
| 8778 | } |
| 8779 | case LoongArch::XVSRANI_B_H: |
| 8780 | case LoongArch::XVSRARNI_B_H: |
| 8781 | case LoongArch::XVSRLNI_B_H: |
| 8782 | case LoongArch::XVSRLRNI_B_H: |
| 8783 | case LoongArch::XVSSRANI_BU_H: |
| 8784 | case LoongArch::XVSSRANI_B_H: |
| 8785 | case LoongArch::XVSSRARNI_BU_H: |
| 8786 | case LoongArch::XVSSRARNI_B_H: |
| 8787 | case LoongArch::XVSSRLNI_BU_H: |
| 8788 | case LoongArch::XVSSRLNI_B_H: |
| 8789 | case LoongArch::XVSSRLRNI_BU_H: |
| 8790 | case LoongArch::XVSSRLRNI_B_H: { |
| 8791 | switch (OpNum) { |
| 8792 | case 3: |
| 8793 | // op: imm4 |
| 8794 | return 10; |
| 8795 | case 2: |
| 8796 | // op: xj |
| 8797 | return 5; |
| 8798 | case 1: |
| 8799 | // op: xd |
| 8800 | return 0; |
| 8801 | } |
| 8802 | break; |
| 8803 | } |
| 8804 | case LoongArch::VSTELM_B: { |
| 8805 | switch (OpNum) { |
| 8806 | case 3: |
| 8807 | // op: imm4 |
| 8808 | return 18; |
| 8809 | case 2: |
| 8810 | // op: imm8 |
| 8811 | return 10; |
| 8812 | case 1: |
| 8813 | // op: rj |
| 8814 | return 5; |
| 8815 | case 0: |
| 8816 | // op: vd |
| 8817 | return 0; |
| 8818 | } |
| 8819 | break; |
| 8820 | } |
| 8821 | case LoongArch::XVSTELM_H: { |
| 8822 | switch (OpNum) { |
| 8823 | case 3: |
| 8824 | // op: imm4 |
| 8825 | return 18; |
| 8826 | case 2: |
| 8827 | // op: imm8 |
| 8828 | return 10; |
| 8829 | case 1: |
| 8830 | // op: rj |
| 8831 | return 5; |
| 8832 | case 0: |
| 8833 | // op: xd |
| 8834 | return 0; |
| 8835 | } |
| 8836 | break; |
| 8837 | } |
| 8838 | case LoongArch::VFRSTPI_B: |
| 8839 | case LoongArch::VFRSTPI_H: |
| 8840 | case LoongArch::VSRANI_H_W: |
| 8841 | case LoongArch::VSRARNI_H_W: |
| 8842 | case LoongArch::VSRLNI_H_W: |
| 8843 | case LoongArch::VSRLRNI_H_W: |
| 8844 | case LoongArch::VSSRANI_HU_W: |
| 8845 | case LoongArch::VSSRANI_H_W: |
| 8846 | case LoongArch::VSSRARNI_HU_W: |
| 8847 | case LoongArch::VSSRARNI_H_W: |
| 8848 | case LoongArch::VSSRLNI_HU_W: |
| 8849 | case LoongArch::VSSRLNI_H_W: |
| 8850 | case LoongArch::VSSRLRNI_HU_W: |
| 8851 | case LoongArch::VSSRLRNI_H_W: { |
| 8852 | switch (OpNum) { |
| 8853 | case 3: |
| 8854 | // op: imm5 |
| 8855 | return 10; |
| 8856 | case 2: |
| 8857 | // op: vj |
| 8858 | return 5; |
| 8859 | case 1: |
| 8860 | // op: vd |
| 8861 | return 0; |
| 8862 | } |
| 8863 | break; |
| 8864 | } |
| 8865 | case LoongArch::XVFRSTPI_B: |
| 8866 | case LoongArch::XVFRSTPI_H: |
| 8867 | case LoongArch::XVSRANI_H_W: |
| 8868 | case LoongArch::XVSRARNI_H_W: |
| 8869 | case LoongArch::XVSRLNI_H_W: |
| 8870 | case LoongArch::XVSRLRNI_H_W: |
| 8871 | case LoongArch::XVSSRANI_HU_W: |
| 8872 | case LoongArch::XVSSRANI_H_W: |
| 8873 | case LoongArch::XVSSRARNI_HU_W: |
| 8874 | case LoongArch::XVSSRARNI_H_W: |
| 8875 | case LoongArch::XVSSRLNI_HU_W: |
| 8876 | case LoongArch::XVSSRLNI_H_W: |
| 8877 | case LoongArch::XVSSRLRNI_HU_W: |
| 8878 | case LoongArch::XVSSRLRNI_H_W: { |
| 8879 | switch (OpNum) { |
| 8880 | case 3: |
| 8881 | // op: imm5 |
| 8882 | return 10; |
| 8883 | case 2: |
| 8884 | // op: xj |
| 8885 | return 5; |
| 8886 | case 1: |
| 8887 | // op: xd |
| 8888 | return 0; |
| 8889 | } |
| 8890 | break; |
| 8891 | } |
| 8892 | case LoongArch::XVSTELM_B: { |
| 8893 | switch (OpNum) { |
| 8894 | case 3: |
| 8895 | // op: imm5 |
| 8896 | return 18; |
| 8897 | case 2: |
| 8898 | // op: imm8 |
| 8899 | return 10; |
| 8900 | case 1: |
| 8901 | // op: rj |
| 8902 | return 5; |
| 8903 | case 0: |
| 8904 | // op: xd |
| 8905 | return 0; |
| 8906 | } |
| 8907 | break; |
| 8908 | } |
| 8909 | case LoongArch::VSRANI_W_D: |
| 8910 | case LoongArch::VSRARNI_W_D: |
| 8911 | case LoongArch::VSRLNI_W_D: |
| 8912 | case LoongArch::VSRLRNI_W_D: |
| 8913 | case LoongArch::VSSRANI_WU_D: |
| 8914 | case LoongArch::VSSRANI_W_D: |
| 8915 | case LoongArch::VSSRARNI_WU_D: |
| 8916 | case LoongArch::VSSRARNI_W_D: |
| 8917 | case LoongArch::VSSRLNI_WU_D: |
| 8918 | case LoongArch::VSSRLNI_W_D: |
| 8919 | case LoongArch::VSSRLRNI_WU_D: |
| 8920 | case LoongArch::VSSRLRNI_W_D: { |
| 8921 | switch (OpNum) { |
| 8922 | case 3: |
| 8923 | // op: imm6 |
| 8924 | return 10; |
| 8925 | case 2: |
| 8926 | // op: vj |
| 8927 | return 5; |
| 8928 | case 1: |
| 8929 | // op: vd |
| 8930 | return 0; |
| 8931 | } |
| 8932 | break; |
| 8933 | } |
| 8934 | case LoongArch::XVSRANI_W_D: |
| 8935 | case LoongArch::XVSRARNI_W_D: |
| 8936 | case LoongArch::XVSRLNI_W_D: |
| 8937 | case LoongArch::XVSRLRNI_W_D: |
| 8938 | case LoongArch::XVSSRANI_WU_D: |
| 8939 | case LoongArch::XVSSRANI_W_D: |
| 8940 | case LoongArch::XVSSRARNI_WU_D: |
| 8941 | case LoongArch::XVSSRARNI_W_D: |
| 8942 | case LoongArch::XVSSRLNI_WU_D: |
| 8943 | case LoongArch::XVSSRLNI_W_D: |
| 8944 | case LoongArch::XVSSRLRNI_WU_D: |
| 8945 | case LoongArch::XVSSRLRNI_W_D: { |
| 8946 | switch (OpNum) { |
| 8947 | case 3: |
| 8948 | // op: imm6 |
| 8949 | return 10; |
| 8950 | case 2: |
| 8951 | // op: xj |
| 8952 | return 5; |
| 8953 | case 1: |
| 8954 | // op: xd |
| 8955 | return 0; |
| 8956 | } |
| 8957 | break; |
| 8958 | } |
| 8959 | case LoongArch::VSRANI_D_Q: |
| 8960 | case LoongArch::VSRARNI_D_Q: |
| 8961 | case LoongArch::VSRLNI_D_Q: |
| 8962 | case LoongArch::VSRLRNI_D_Q: |
| 8963 | case LoongArch::VSSRANI_DU_Q: |
| 8964 | case LoongArch::VSSRANI_D_Q: |
| 8965 | case LoongArch::VSSRARNI_DU_Q: |
| 8966 | case LoongArch::VSSRARNI_D_Q: |
| 8967 | case LoongArch::VSSRLNI_DU_Q: |
| 8968 | case LoongArch::VSSRLNI_D_Q: |
| 8969 | case LoongArch::VSSRLRNI_DU_Q: |
| 8970 | case LoongArch::VSSRLRNI_D_Q: { |
| 8971 | switch (OpNum) { |
| 8972 | case 3: |
| 8973 | // op: imm7 |
| 8974 | return 10; |
| 8975 | case 2: |
| 8976 | // op: vj |
| 8977 | return 5; |
| 8978 | case 1: |
| 8979 | // op: vd |
| 8980 | return 0; |
| 8981 | } |
| 8982 | break; |
| 8983 | } |
| 8984 | case LoongArch::XVSRANI_D_Q: |
| 8985 | case LoongArch::XVSRARNI_D_Q: |
| 8986 | case LoongArch::XVSRLNI_D_Q: |
| 8987 | case LoongArch::XVSRLRNI_D_Q: |
| 8988 | case LoongArch::XVSSRANI_DU_Q: |
| 8989 | case LoongArch::XVSSRANI_D_Q: |
| 8990 | case LoongArch::XVSSRARNI_DU_Q: |
| 8991 | case LoongArch::XVSSRARNI_D_Q: |
| 8992 | case LoongArch::XVSSRLNI_DU_Q: |
| 8993 | case LoongArch::XVSSRLNI_D_Q: |
| 8994 | case LoongArch::XVSSRLRNI_DU_Q: |
| 8995 | case LoongArch::XVSSRLRNI_D_Q: { |
| 8996 | switch (OpNum) { |
| 8997 | case 3: |
| 8998 | // op: imm7 |
| 8999 | return 10; |
| 9000 | case 2: |
| 9001 | // op: xj |
| 9002 | return 5; |
| 9003 | case 1: |
| 9004 | // op: xd |
| 9005 | return 0; |
| 9006 | } |
| 9007 | break; |
| 9008 | } |
| 9009 | case LoongArch::VBITSELI_B: |
| 9010 | case LoongArch::VEXTRINS_B: |
| 9011 | case LoongArch::VEXTRINS_D: |
| 9012 | case LoongArch::VEXTRINS_H: |
| 9013 | case LoongArch::VEXTRINS_W: |
| 9014 | case LoongArch::VPERMI_W: |
| 9015 | case LoongArch::VSHUF4I_D: { |
| 9016 | switch (OpNum) { |
| 9017 | case 3: |
| 9018 | // op: imm8 |
| 9019 | return 10; |
| 9020 | case 2: |
| 9021 | // op: vj |
| 9022 | return 5; |
| 9023 | case 1: |
| 9024 | // op: vd |
| 9025 | return 0; |
| 9026 | } |
| 9027 | break; |
| 9028 | } |
| 9029 | case LoongArch::XVBITSELI_B: |
| 9030 | case LoongArch::XVEXTRINS_B: |
| 9031 | case LoongArch::XVEXTRINS_D: |
| 9032 | case LoongArch::XVEXTRINS_H: |
| 9033 | case LoongArch::XVEXTRINS_W: |
| 9034 | case LoongArch::XVPERMI_Q: |
| 9035 | case LoongArch::XVPERMI_W: |
| 9036 | case LoongArch::XVSHUF4I_D: { |
| 9037 | switch (OpNum) { |
| 9038 | case 3: |
| 9039 | // op: imm8 |
| 9040 | return 10; |
| 9041 | case 2: |
| 9042 | // op: xj |
| 9043 | return 5; |
| 9044 | case 1: |
| 9045 | // op: xd |
| 9046 | return 0; |
| 9047 | } |
| 9048 | break; |
| 9049 | } |
| 9050 | case LoongArch::BSTRINS_D: { |
| 9051 | switch (OpNum) { |
| 9052 | case 3: |
| 9053 | // op: msbd |
| 9054 | return 16; |
| 9055 | case 4: |
| 9056 | // op: lsbd |
| 9057 | return 10; |
| 9058 | case 2: |
| 9059 | // op: rj |
| 9060 | return 5; |
| 9061 | case 1: |
| 9062 | // op: rd |
| 9063 | return 0; |
| 9064 | } |
| 9065 | break; |
| 9066 | } |
| 9067 | case LoongArch::BSTRINS_W: { |
| 9068 | switch (OpNum) { |
| 9069 | case 3: |
| 9070 | // op: msbw |
| 9071 | return 16; |
| 9072 | case 4: |
| 9073 | // op: lsbw |
| 9074 | return 10; |
| 9075 | case 2: |
| 9076 | // op: rj |
| 9077 | return 5; |
| 9078 | case 1: |
| 9079 | // op: rd |
| 9080 | return 0; |
| 9081 | } |
| 9082 | break; |
| 9083 | } |
| 9084 | case LoongArch::VBITSEL_V: |
| 9085 | case LoongArch::VFMADD_D: |
| 9086 | case LoongArch::VFMADD_S: |
| 9087 | case LoongArch::VFMSUB_D: |
| 9088 | case LoongArch::VFMSUB_S: |
| 9089 | case LoongArch::VFNMADD_D: |
| 9090 | case LoongArch::VFNMADD_S: |
| 9091 | case LoongArch::VFNMSUB_D: |
| 9092 | case LoongArch::VFNMSUB_S: |
| 9093 | case LoongArch::VSHUF_B: { |
| 9094 | switch (OpNum) { |
| 9095 | case 3: |
| 9096 | // op: va |
| 9097 | return 15; |
| 9098 | case 2: |
| 9099 | // op: vk |
| 9100 | return 10; |
| 9101 | case 1: |
| 9102 | // op: vj |
| 9103 | return 5; |
| 9104 | case 0: |
| 9105 | // op: vd |
| 9106 | return 0; |
| 9107 | } |
| 9108 | break; |
| 9109 | } |
| 9110 | case LoongArch::VFRSTP_B: |
| 9111 | case LoongArch::VFRSTP_H: |
| 9112 | case LoongArch::VMADDWEV_D_W: |
| 9113 | case LoongArch::VMADDWEV_D_WU: |
| 9114 | case LoongArch::VMADDWEV_D_WU_W: |
| 9115 | case LoongArch::VMADDWEV_H_B: |
| 9116 | case LoongArch::VMADDWEV_H_BU: |
| 9117 | case LoongArch::VMADDWEV_H_BU_B: |
| 9118 | case LoongArch::VMADDWEV_Q_D: |
| 9119 | case LoongArch::VMADDWEV_Q_DU: |
| 9120 | case LoongArch::VMADDWEV_Q_DU_D: |
| 9121 | case LoongArch::VMADDWEV_W_H: |
| 9122 | case LoongArch::VMADDWEV_W_HU: |
| 9123 | case LoongArch::VMADDWEV_W_HU_H: |
| 9124 | case LoongArch::VMADDWOD_D_W: |
| 9125 | case LoongArch::VMADDWOD_D_WU: |
| 9126 | case LoongArch::VMADDWOD_D_WU_W: |
| 9127 | case LoongArch::VMADDWOD_H_B: |
| 9128 | case LoongArch::VMADDWOD_H_BU: |
| 9129 | case LoongArch::VMADDWOD_H_BU_B: |
| 9130 | case LoongArch::VMADDWOD_Q_D: |
| 9131 | case LoongArch::VMADDWOD_Q_DU: |
| 9132 | case LoongArch::VMADDWOD_Q_DU_D: |
| 9133 | case LoongArch::VMADDWOD_W_H: |
| 9134 | case LoongArch::VMADDWOD_W_HU: |
| 9135 | case LoongArch::VMADDWOD_W_HU_H: |
| 9136 | case LoongArch::VMADD_B: |
| 9137 | case LoongArch::VMADD_D: |
| 9138 | case LoongArch::VMADD_H: |
| 9139 | case LoongArch::VMADD_W: |
| 9140 | case LoongArch::VMSUB_B: |
| 9141 | case LoongArch::VMSUB_D: |
| 9142 | case LoongArch::VMSUB_H: |
| 9143 | case LoongArch::VMSUB_W: |
| 9144 | case LoongArch::VSHUF_D: |
| 9145 | case LoongArch::VSHUF_H: |
| 9146 | case LoongArch::VSHUF_W: { |
| 9147 | switch (OpNum) { |
| 9148 | case 3: |
| 9149 | // op: vk |
| 9150 | return 10; |
| 9151 | case 2: |
| 9152 | // op: vj |
| 9153 | return 5; |
| 9154 | case 1: |
| 9155 | // op: vd |
| 9156 | return 0; |
| 9157 | } |
| 9158 | break; |
| 9159 | } |
| 9160 | case LoongArch::XVBITSEL_V: |
| 9161 | case LoongArch::XVFMADD_D: |
| 9162 | case LoongArch::XVFMADD_S: |
| 9163 | case LoongArch::XVFMSUB_D: |
| 9164 | case LoongArch::XVFMSUB_S: |
| 9165 | case LoongArch::XVFNMADD_D: |
| 9166 | case LoongArch::XVFNMADD_S: |
| 9167 | case LoongArch::XVFNMSUB_D: |
| 9168 | case LoongArch::XVFNMSUB_S: |
| 9169 | case LoongArch::XVSHUF_B: { |
| 9170 | switch (OpNum) { |
| 9171 | case 3: |
| 9172 | // op: xa |
| 9173 | return 15; |
| 9174 | case 2: |
| 9175 | // op: xk |
| 9176 | return 10; |
| 9177 | case 1: |
| 9178 | // op: xj |
| 9179 | return 5; |
| 9180 | case 0: |
| 9181 | // op: xd |
| 9182 | return 0; |
| 9183 | } |
| 9184 | break; |
| 9185 | } |
| 9186 | case LoongArch::XVFRSTP_B: |
| 9187 | case LoongArch::XVFRSTP_H: |
| 9188 | case LoongArch::XVMADDWEV_D_W: |
| 9189 | case LoongArch::XVMADDWEV_D_WU: |
| 9190 | case LoongArch::XVMADDWEV_D_WU_W: |
| 9191 | case LoongArch::XVMADDWEV_H_B: |
| 9192 | case LoongArch::XVMADDWEV_H_BU: |
| 9193 | case LoongArch::XVMADDWEV_H_BU_B: |
| 9194 | case LoongArch::XVMADDWEV_Q_D: |
| 9195 | case LoongArch::XVMADDWEV_Q_DU: |
| 9196 | case LoongArch::XVMADDWEV_Q_DU_D: |
| 9197 | case LoongArch::XVMADDWEV_W_H: |
| 9198 | case LoongArch::XVMADDWEV_W_HU: |
| 9199 | case LoongArch::XVMADDWEV_W_HU_H: |
| 9200 | case LoongArch::XVMADDWOD_D_W: |
| 9201 | case LoongArch::XVMADDWOD_D_WU: |
| 9202 | case LoongArch::XVMADDWOD_D_WU_W: |
| 9203 | case LoongArch::XVMADDWOD_H_B: |
| 9204 | case LoongArch::XVMADDWOD_H_BU: |
| 9205 | case LoongArch::XVMADDWOD_H_BU_B: |
| 9206 | case LoongArch::XVMADDWOD_Q_D: |
| 9207 | case LoongArch::XVMADDWOD_Q_DU: |
| 9208 | case LoongArch::XVMADDWOD_Q_DU_D: |
| 9209 | case LoongArch::XVMADDWOD_W_H: |
| 9210 | case LoongArch::XVMADDWOD_W_HU: |
| 9211 | case LoongArch::XVMADDWOD_W_HU_H: |
| 9212 | case LoongArch::XVMADD_B: |
| 9213 | case LoongArch::XVMADD_D: |
| 9214 | case LoongArch::XVMADD_H: |
| 9215 | case LoongArch::XVMADD_W: |
| 9216 | case LoongArch::XVMSUB_B: |
| 9217 | case LoongArch::XVMSUB_D: |
| 9218 | case LoongArch::XVMSUB_H: |
| 9219 | case LoongArch::XVMSUB_W: |
| 9220 | case LoongArch::XVSHUF_D: |
| 9221 | case LoongArch::XVSHUF_H: |
| 9222 | case LoongArch::XVSHUF_W: { |
| 9223 | switch (OpNum) { |
| 9224 | case 3: |
| 9225 | // op: xk |
| 9226 | return 10; |
| 9227 | case 2: |
| 9228 | // op: xj |
| 9229 | return 5; |
| 9230 | case 1: |
| 9231 | // op: xd |
| 9232 | return 0; |
| 9233 | } |
| 9234 | break; |
| 9235 | } |
| 9236 | default: |
| 9237 | reportUnsupportedInst(MI); |
| 9238 | } |
| 9239 | reportUnsupportedOperand(MI, OpNum); |
| 9240 | } |
| 9241 | |
| 9242 | #endif // GET_OPERAND_BIT_OFFSET |
| 9243 | |
| 9244 |
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