1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(20608), // ADD16mc
14 UINT64_C(20656), // ADD16mi
15 UINT64_C(20624), // ADD16mm
16 UINT64_C(20640), // ADD16mn
17 UINT64_C(20656), // ADD16mp
18 UINT64_C(20608), // ADD16mr
19 UINT64_C(20480), // ADD16rc
20 UINT64_C(20528), // ADD16ri
21 UINT64_C(20496), // ADD16rm
22 UINT64_C(20512), // ADD16rn
23 UINT64_C(20528), // ADD16rp
24 UINT64_C(20480), // ADD16rr
25 UINT64_C(20672), // ADD8mc
26 UINT64_C(20720), // ADD8mi
27 UINT64_C(20688), // ADD8mm
28 UINT64_C(20704), // ADD8mn
29 UINT64_C(20720), // ADD8mp
30 UINT64_C(20672), // ADD8mr
31 UINT64_C(20544), // ADD8rc
32 UINT64_C(20592), // ADD8ri
33 UINT64_C(20560), // ADD8rm
34 UINT64_C(20576), // ADD8rn
35 UINT64_C(20592), // ADD8rp
36 UINT64_C(20544), // ADD8rr
37 UINT64_C(24704), // ADDC16mc
38 UINT64_C(24752), // ADDC16mi
39 UINT64_C(24720), // ADDC16mm
40 UINT64_C(24736), // ADDC16mn
41 UINT64_C(24752), // ADDC16mp
42 UINT64_C(24704), // ADDC16mr
43 UINT64_C(24576), // ADDC16rc
44 UINT64_C(24624), // ADDC16ri
45 UINT64_C(24592), // ADDC16rm
46 UINT64_C(24608), // ADDC16rn
47 UINT64_C(24624), // ADDC16rp
48 UINT64_C(24576), // ADDC16rr
49 UINT64_C(24768), // ADDC8mc
50 UINT64_C(24816), // ADDC8mi
51 UINT64_C(24784), // ADDC8mm
52 UINT64_C(24800), // ADDC8mn
53 UINT64_C(24816), // ADDC8mp
54 UINT64_C(24768), // ADDC8mr
55 UINT64_C(24640), // ADDC8rc
56 UINT64_C(24688), // ADDC8ri
57 UINT64_C(24656), // ADDC8rm
58 UINT64_C(24672), // ADDC8rn
59 UINT64_C(24688), // ADDC8rp
60 UINT64_C(24640), // ADDC8rr
61 UINT64_C(0), // ADDframe
62 UINT64_C(0), // ADJCALLSTACKDOWN
63 UINT64_C(0), // ADJCALLSTACKUP
64 UINT64_C(61568), // AND16mc
65 UINT64_C(61616), // AND16mi
66 UINT64_C(61584), // AND16mm
67 UINT64_C(61600), // AND16mn
68 UINT64_C(61616), // AND16mp
69 UINT64_C(61568), // AND16mr
70 UINT64_C(61440), // AND16rc
71 UINT64_C(61488), // AND16ri
72 UINT64_C(61456), // AND16rm
73 UINT64_C(61472), // AND16rn
74 UINT64_C(61488), // AND16rp
75 UINT64_C(61440), // AND16rr
76 UINT64_C(61632), // AND8mc
77 UINT64_C(61680), // AND8mi
78 UINT64_C(61648), // AND8mm
79 UINT64_C(61664), // AND8mn
80 UINT64_C(61680), // AND8mp
81 UINT64_C(61632), // AND8mr
82 UINT64_C(61504), // AND8rc
83 UINT64_C(61552), // AND8ri
84 UINT64_C(61520), // AND8rm
85 UINT64_C(61536), // AND8rn
86 UINT64_C(61552), // AND8rp
87 UINT64_C(61504), // AND8rr
88 UINT64_C(49280), // BIC16mc
89 UINT64_C(49328), // BIC16mi
90 UINT64_C(49296), // BIC16mm
91 UINT64_C(49312), // BIC16mn
92 UINT64_C(49328), // BIC16mp
93 UINT64_C(49280), // BIC16mr
94 UINT64_C(49152), // BIC16rc
95 UINT64_C(49200), // BIC16ri
96 UINT64_C(49168), // BIC16rm
97 UINT64_C(49184), // BIC16rn
98 UINT64_C(49200), // BIC16rp
99 UINT64_C(49152), // BIC16rr
100 UINT64_C(49344), // BIC8mc
101 UINT64_C(49392), // BIC8mi
102 UINT64_C(49360), // BIC8mm
103 UINT64_C(49376), // BIC8mn
104 UINT64_C(49392), // BIC8mp
105 UINT64_C(49344), // BIC8mr
106 UINT64_C(49216), // BIC8rc
107 UINT64_C(49264), // BIC8ri
108 UINT64_C(49232), // BIC8rm
109 UINT64_C(49248), // BIC8rn
110 UINT64_C(49264), // BIC8rp
111 UINT64_C(49216), // BIC8rr
112 UINT64_C(53376), // BIS16mc
113 UINT64_C(53424), // BIS16mi
114 UINT64_C(53392), // BIS16mm
115 UINT64_C(53408), // BIS16mn
116 UINT64_C(53424), // BIS16mp
117 UINT64_C(53376), // BIS16mr
118 UINT64_C(53248), // BIS16rc
119 UINT64_C(53296), // BIS16ri
120 UINT64_C(53264), // BIS16rm
121 UINT64_C(53280), // BIS16rn
122 UINT64_C(53296), // BIS16rp
123 UINT64_C(53248), // BIS16rr
124 UINT64_C(53440), // BIS8mc
125 UINT64_C(53488), // BIS8mi
126 UINT64_C(53456), // BIS8mm
127 UINT64_C(53472), // BIS8mn
128 UINT64_C(53488), // BIS8mp
129 UINT64_C(53440), // BIS8mr
130 UINT64_C(53312), // BIS8rc
131 UINT64_C(53360), // BIS8ri
132 UINT64_C(53328), // BIS8rm
133 UINT64_C(53344), // BIS8rn
134 UINT64_C(53360), // BIS8rp
135 UINT64_C(53312), // BIS8rr
136 UINT64_C(45184), // BIT16mc
137 UINT64_C(45232), // BIT16mi
138 UINT64_C(45200), // BIT16mm
139 UINT64_C(45216), // BIT16mn
140 UINT64_C(45232), // BIT16mp
141 UINT64_C(45184), // BIT16mr
142 UINT64_C(45056), // BIT16rc
143 UINT64_C(45104), // BIT16ri
144 UINT64_C(45072), // BIT16rm
145 UINT64_C(45088), // BIT16rn
146 UINT64_C(45104), // BIT16rp
147 UINT64_C(45056), // BIT16rr
148 UINT64_C(45248), // BIT8mc
149 UINT64_C(45296), // BIT8mi
150 UINT64_C(45264), // BIT8mm
151 UINT64_C(45280), // BIT8mn
152 UINT64_C(45296), // BIT8mp
153 UINT64_C(45248), // BIT8mr
154 UINT64_C(45120), // BIT8rc
155 UINT64_C(45168), // BIT8ri
156 UINT64_C(45136), // BIT8rm
157 UINT64_C(45152), // BIT8rn
158 UINT64_C(45168), // BIT8rp
159 UINT64_C(45120), // BIT8rr
160 UINT64_C(16432), // Bi
161 UINT64_C(16400), // Bm
162 UINT64_C(16384), // Br
163 UINT64_C(4784), // CALLi
164 UINT64_C(4752), // CALLm
165 UINT64_C(4768), // CALLn
166 UINT64_C(4784), // CALLp
167 UINT64_C(4736), // CALLr
168 UINT64_C(36992), // CMP16mc
169 UINT64_C(37040), // CMP16mi
170 UINT64_C(37008), // CMP16mm
171 UINT64_C(37024), // CMP16mn
172 UINT64_C(37040), // CMP16mp
173 UINT64_C(36992), // CMP16mr
174 UINT64_C(36864), // CMP16rc
175 UINT64_C(36912), // CMP16ri
176 UINT64_C(36880), // CMP16rm
177 UINT64_C(36896), // CMP16rn
178 UINT64_C(36912), // CMP16rp
179 UINT64_C(36864), // CMP16rr
180 UINT64_C(37056), // CMP8mc
181 UINT64_C(37104), // CMP8mi
182 UINT64_C(37072), // CMP8mm
183 UINT64_C(37088), // CMP8mn
184 UINT64_C(37104), // CMP8mp
185 UINT64_C(37056), // CMP8mr
186 UINT64_C(36928), // CMP8rc
187 UINT64_C(36976), // CMP8ri
188 UINT64_C(36944), // CMP8rm
189 UINT64_C(36960), // CMP8rn
190 UINT64_C(36976), // CMP8rp
191 UINT64_C(36928), // CMP8rr
192 UINT64_C(41088), // DADD16mc
193 UINT64_C(41136), // DADD16mi
194 UINT64_C(41104), // DADD16mm
195 UINT64_C(41120), // DADD16mn
196 UINT64_C(41136), // DADD16mp
197 UINT64_C(41088), // DADD16mr
198 UINT64_C(40960), // DADD16rc
199 UINT64_C(41008), // DADD16ri
200 UINT64_C(40976), // DADD16rm
201 UINT64_C(40992), // DADD16rn
202 UINT64_C(41008), // DADD16rp
203 UINT64_C(40960), // DADD16rr
204 UINT64_C(41152), // DADD8mc
205 UINT64_C(41200), // DADD8mi
206 UINT64_C(41168), // DADD8mm
207 UINT64_C(41184), // DADD8mn
208 UINT64_C(41200), // DADD8mp
209 UINT64_C(41152), // DADD8mr
210 UINT64_C(41024), // DADD8rc
211 UINT64_C(41072), // DADD8ri
212 UINT64_C(41040), // DADD8rm
213 UINT64_C(41056), // DADD8rn
214 UINT64_C(41072), // DADD8rp
215 UINT64_C(41024), // DADD8rr
216 UINT64_C(8192), // JCC
217 UINT64_C(15360), // JMP
218 UINT64_C(16512), // MOV16mc
219 UINT64_C(16560), // MOV16mi
220 UINT64_C(16528), // MOV16mm
221 UINT64_C(16544), // MOV16mn
222 UINT64_C(16512), // MOV16mr
223 UINT64_C(16384), // MOV16rc
224 UINT64_C(16432), // MOV16ri
225 UINT64_C(16400), // MOV16rm
226 UINT64_C(16416), // MOV16rn
227 UINT64_C(16432), // MOV16rp
228 UINT64_C(16384), // MOV16rr
229 UINT64_C(16576), // MOV8mc
230 UINT64_C(16624), // MOV8mi
231 UINT64_C(16592), // MOV8mm
232 UINT64_C(16608), // MOV8mn
233 UINT64_C(16576), // MOV8mr
234 UINT64_C(16448), // MOV8rc
235 UINT64_C(16496), // MOV8ri
236 UINT64_C(16464), // MOV8rm
237 UINT64_C(16480), // MOV8rn
238 UINT64_C(16496), // MOV8rp
239 UINT64_C(16448), // MOV8rr
240 UINT64_C(16464), // MOVZX16rm8
241 UINT64_C(16448), // MOVZX16rr8
242 UINT64_C(16688), // POP16r
243 UINT64_C(4608), // PUSH16c
244 UINT64_C(4656), // PUSH16i
245 UINT64_C(4608), // PUSH16r
246 UINT64_C(4672), // PUSH8r
247 UINT64_C(16688), // RET
248 UINT64_C(4864), // RETI
249 UINT64_C(4368), // RRA16m
250 UINT64_C(4384), // RRA16n
251 UINT64_C(4400), // RRA16p
252 UINT64_C(4352), // RRA16r
253 UINT64_C(4432), // RRA8m
254 UINT64_C(4448), // RRA8n
255 UINT64_C(4464), // RRA8p
256 UINT64_C(4416), // RRA8r
257 UINT64_C(4112), // RRC16m
258 UINT64_C(4128), // RRC16n
259 UINT64_C(4144), // RRC16p
260 UINT64_C(4096), // RRC16r
261 UINT64_C(4176), // RRC8m
262 UINT64_C(4192), // RRC8n
263 UINT64_C(4208), // RRC8p
264 UINT64_C(4160), // RRC8r
265 UINT64_C(0), // Rrcl16
266 UINT64_C(0), // Rrcl8
267 UINT64_C(4496), // SEXT16m
268 UINT64_C(4512), // SEXT16n
269 UINT64_C(4528), // SEXT16p
270 UINT64_C(4480), // SEXT16r
271 UINT64_C(32896), // SUB16mc
272 UINT64_C(32944), // SUB16mi
273 UINT64_C(32912), // SUB16mm
274 UINT64_C(32928), // SUB16mn
275 UINT64_C(32944), // SUB16mp
276 UINT64_C(32896), // SUB16mr
277 UINT64_C(32768), // SUB16rc
278 UINT64_C(32816), // SUB16ri
279 UINT64_C(32784), // SUB16rm
280 UINT64_C(32800), // SUB16rn
281 UINT64_C(32816), // SUB16rp
282 UINT64_C(32768), // SUB16rr
283 UINT64_C(32960), // SUB8mc
284 UINT64_C(33008), // SUB8mi
285 UINT64_C(32976), // SUB8mm
286 UINT64_C(32992), // SUB8mn
287 UINT64_C(33008), // SUB8mp
288 UINT64_C(32960), // SUB8mr
289 UINT64_C(32832), // SUB8rc
290 UINT64_C(32880), // SUB8ri
291 UINT64_C(32848), // SUB8rm
292 UINT64_C(32864), // SUB8rn
293 UINT64_C(32880), // SUB8rp
294 UINT64_C(32832), // SUB8rr
295 UINT64_C(28800), // SUBC16mc
296 UINT64_C(28848), // SUBC16mi
297 UINT64_C(28816), // SUBC16mm
298 UINT64_C(28832), // SUBC16mn
299 UINT64_C(28848), // SUBC16mp
300 UINT64_C(28800), // SUBC16mr
301 UINT64_C(28672), // SUBC16rc
302 UINT64_C(28720), // SUBC16ri
303 UINT64_C(28688), // SUBC16rm
304 UINT64_C(28704), // SUBC16rn
305 UINT64_C(28720), // SUBC16rp
306 UINT64_C(28672), // SUBC16rr
307 UINT64_C(28864), // SUBC8mc
308 UINT64_C(28912), // SUBC8mi
309 UINT64_C(28880), // SUBC8mm
310 UINT64_C(28896), // SUBC8mn
311 UINT64_C(28912), // SUBC8mp
312 UINT64_C(28864), // SUBC8mr
313 UINT64_C(28736), // SUBC8rc
314 UINT64_C(28784), // SUBC8ri
315 UINT64_C(28752), // SUBC8rm
316 UINT64_C(28768), // SUBC8rn
317 UINT64_C(28784), // SUBC8rp
318 UINT64_C(28736), // SUBC8rr
319 UINT64_C(4240), // SWPB16m
320 UINT64_C(4256), // SWPB16n
321 UINT64_C(4272), // SWPB16p
322 UINT64_C(4224), // SWPB16r
323 UINT64_C(0), // Select16
324 UINT64_C(0), // Select8
325 UINT64_C(0), // Shl16
326 UINT64_C(0), // Shl8
327 UINT64_C(0), // Sra16
328 UINT64_C(0), // Sra8
329 UINT64_C(0), // Srl16
330 UINT64_C(0), // Srl8
331 UINT64_C(57472), // XOR16mc
332 UINT64_C(57520), // XOR16mi
333 UINT64_C(57488), // XOR16mm
334 UINT64_C(57504), // XOR16mn
335 UINT64_C(57520), // XOR16mp
336 UINT64_C(57472), // XOR16mr
337 UINT64_C(57344), // XOR16rc
338 UINT64_C(57392), // XOR16ri
339 UINT64_C(57360), // XOR16rm
340 UINT64_C(57376), // XOR16rn
341 UINT64_C(57392), // XOR16rp
342 UINT64_C(57344), // XOR16rr
343 UINT64_C(57536), // XOR8mc
344 UINT64_C(57584), // XOR8mi
345 UINT64_C(57552), // XOR8mm
346 UINT64_C(57568), // XOR8mn
347 UINT64_C(57584), // XOR8mp
348 UINT64_C(57536), // XOR8mr
349 UINT64_C(57408), // XOR8rc
350 UINT64_C(57456), // XOR8ri
351 UINT64_C(57424), // XOR8rm
352 UINT64_C(57440), // XOR8rn
353 UINT64_C(57456), // XOR8rp
354 UINT64_C(57408), // XOR8rr
355 UINT64_C(16448), // ZEXT16r
356 };
357 constexpr unsigned FirstSupportedOpcode = 323;
358
359 const unsigned opcode = MI.getOpcode();
360 if (opcode < FirstSupportedOpcode)
361 reportUnsupportedInst(Inst: MI);
362 unsigned TableIndex = opcode - FirstSupportedOpcode;
363 uint64_t Value = InstBits[TableIndex];
364 uint64_t op = 0;
365 (void)op; // suppress warning
366 switch (opcode) {
367 case MSP430::ADDframe:
368 case MSP430::ADJCALLSTACKDOWN:
369 case MSP430::ADJCALLSTACKUP:
370 case MSP430::RET:
371 case MSP430::RETI:
372 case MSP430::Rrcl16:
373 case MSP430::Rrcl8:
374 case MSP430::Select16:
375 case MSP430::Select8:
376 case MSP430::Shl16:
377 case MSP430::Shl8:
378 case MSP430::Sra16:
379 case MSP430::Sra8:
380 case MSP430::Srl16:
381 case MSP430::Srl8: {
382 break;
383 }
384 case MSP430::JCC: {
385 // op: cond
386 op = getCCOpValue(MI, Op: 1, Fixups, STI);
387 Value |= (op & 0x7) << 10;
388 // op: dst
389 op = getPCRelImmOpValue(MI, Op: 0, Fixups, STI);
390 Value |= (op & 0x3ff);
391 break;
392 }
393 case MSP430::JMP: {
394 // op: dst
395 op = getPCRelImmOpValue(MI, Op: 0, Fixups, STI);
396 Value |= (op & 0x3ff);
397 break;
398 }
399 case MSP430::PUSH16c: {
400 // op: imm
401 op = getCGImmOpValue(MI, Op: 0, Fixups, STI);
402 Value |= (op & 0x3f);
403 break;
404 }
405 case MSP430::BIT16rc:
406 case MSP430::BIT8rc:
407 case MSP430::CMP16rc:
408 case MSP430::CMP8rc:
409 case MSP430::MOV16rc:
410 case MSP430::MOV8rc: {
411 // op: imm
412 op = getCGImmOpValue(MI, Op: 1, Fixups, STI);
413 Value |= (op & 0xf) << 8;
414 Value |= (op & 0x30);
415 // op: rd
416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
417 Value |= (op & 0xf);
418 break;
419 }
420 case MSP430::ADD16mc:
421 case MSP430::ADD8mc:
422 case MSP430::ADDC16mc:
423 case MSP430::ADDC8mc:
424 case MSP430::AND16mc:
425 case MSP430::AND8mc:
426 case MSP430::BIC16mc:
427 case MSP430::BIC8mc:
428 case MSP430::BIS16mc:
429 case MSP430::BIS8mc:
430 case MSP430::BIT16mc:
431 case MSP430::BIT8mc:
432 case MSP430::CMP16mc:
433 case MSP430::CMP8mc:
434 case MSP430::DADD16mc:
435 case MSP430::DADD8mc:
436 case MSP430::MOV16mc:
437 case MSP430::MOV8mc:
438 case MSP430::SUB16mc:
439 case MSP430::SUB8mc:
440 case MSP430::SUBC16mc:
441 case MSP430::SUBC8mc:
442 case MSP430::XOR16mc:
443 case MSP430::XOR8mc: {
444 // op: imm
445 op = getCGImmOpValue(MI, Op: 2, Fixups, STI);
446 Value |= (op & 0xf) << 8;
447 Value |= (op & 0x30);
448 // op: dst
449 op = getMemOpValue(MI, Op: 0, Fixups, STI);
450 Value |= (op & 0xffff0) << 12;
451 Value |= (op & 0xf);
452 break;
453 }
454 case MSP430::ADD16rc:
455 case MSP430::ADD8rc:
456 case MSP430::ADDC16rc:
457 case MSP430::ADDC8rc:
458 case MSP430::AND16rc:
459 case MSP430::AND8rc:
460 case MSP430::BIC16rc:
461 case MSP430::BIC8rc:
462 case MSP430::BIS16rc:
463 case MSP430::BIS8rc:
464 case MSP430::DADD16rc:
465 case MSP430::DADD8rc:
466 case MSP430::SUB16rc:
467 case MSP430::SUB8rc:
468 case MSP430::SUBC16rc:
469 case MSP430::SUBC8rc:
470 case MSP430::XOR16rc:
471 case MSP430::XOR8rc: {
472 // op: imm
473 op = getCGImmOpValue(MI, Op: 2, Fixups, STI);
474 Value |= (op & 0xf) << 8;
475 Value |= (op & 0x30);
476 // op: rd
477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
478 Value |= (op & 0xf);
479 break;
480 }
481 case MSP430::Bi:
482 case MSP430::CALLi:
483 case MSP430::PUSH16i: {
484 // op: imm
485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
486 Value |= (op & 0xffff) << 16;
487 break;
488 }
489 case MSP430::ADD16mi:
490 case MSP430::ADD8mi:
491 case MSP430::ADDC16mi:
492 case MSP430::ADDC8mi:
493 case MSP430::AND16mi:
494 case MSP430::AND8mi:
495 case MSP430::BIC16mi:
496 case MSP430::BIC8mi:
497 case MSP430::BIS16mi:
498 case MSP430::BIS8mi:
499 case MSP430::BIT16mi:
500 case MSP430::BIT8mi:
501 case MSP430::CMP16mi:
502 case MSP430::CMP8mi:
503 case MSP430::DADD16mi:
504 case MSP430::DADD8mi:
505 case MSP430::MOV16mi:
506 case MSP430::MOV8mi:
507 case MSP430::SUB16mi:
508 case MSP430::SUB8mi:
509 case MSP430::SUBC16mi:
510 case MSP430::SUBC8mi:
511 case MSP430::XOR16mi:
512 case MSP430::XOR8mi: {
513 // op: imm
514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
515 Value |= (op & 0xffff) << 16;
516 // op: dst
517 op = getMemOpValue(MI, Op: 0, Fixups, STI);
518 Value |= (op & 0xffff0) << 28;
519 Value |= (op & 0xf);
520 break;
521 }
522 case MSP430::POP16r: {
523 // op: rd
524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
525 Value |= (op & 0xf);
526 break;
527 }
528 case MSP430::BIT16ri:
529 case MSP430::BIT8ri:
530 case MSP430::CMP16ri:
531 case MSP430::CMP8ri:
532 case MSP430::MOV16ri:
533 case MSP430::MOV8ri: {
534 // op: rd
535 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
536 Value |= (op & 0xf);
537 // op: imm
538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
539 Value |= (op & 0xffff) << 16;
540 break;
541 }
542 case MSP430::ADD16ri:
543 case MSP430::ADD8ri:
544 case MSP430::ADDC16ri:
545 case MSP430::ADDC8ri:
546 case MSP430::AND16ri:
547 case MSP430::AND8ri:
548 case MSP430::BIC16ri:
549 case MSP430::BIC8ri:
550 case MSP430::BIS16ri:
551 case MSP430::BIS8ri:
552 case MSP430::DADD16ri:
553 case MSP430::DADD8ri:
554 case MSP430::SUB16ri:
555 case MSP430::SUB8ri:
556 case MSP430::SUBC16ri:
557 case MSP430::SUBC8ri:
558 case MSP430::XOR16ri:
559 case MSP430::XOR8ri: {
560 // op: rd
561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
562 Value |= (op & 0xf);
563 // op: imm
564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
565 Value |= (op & 0xffff) << 16;
566 break;
567 }
568 case MSP430::BIT16rm:
569 case MSP430::BIT8rm:
570 case MSP430::CMP16rm:
571 case MSP430::CMP8rm:
572 case MSP430::MOV16rm:
573 case MSP430::MOV8rm:
574 case MSP430::MOVZX16rm8: {
575 // op: rd
576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
577 Value |= (op & 0xf);
578 // op: src
579 op = getMemOpValue(MI, Op: 1, Fixups, STI);
580 Value |= (op & 0xffff0) << 12;
581 Value |= (op & 0xf) << 8;
582 break;
583 }
584 case MSP430::ADD16rm:
585 case MSP430::ADD8rm:
586 case MSP430::ADDC16rm:
587 case MSP430::ADDC8rm:
588 case MSP430::AND16rm:
589 case MSP430::AND8rm:
590 case MSP430::BIC16rm:
591 case MSP430::BIC8rm:
592 case MSP430::BIS16rm:
593 case MSP430::BIS8rm:
594 case MSP430::DADD16rm:
595 case MSP430::DADD8rm:
596 case MSP430::SUB16rm:
597 case MSP430::SUB8rm:
598 case MSP430::SUBC16rm:
599 case MSP430::SUBC8rm:
600 case MSP430::XOR16rm:
601 case MSP430::XOR8rm: {
602 // op: rd
603 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
604 Value |= (op & 0xf);
605 // op: src
606 op = getMemOpValue(MI, Op: 2, Fixups, STI);
607 Value |= (op & 0xffff0) << 12;
608 Value |= (op & 0xf) << 8;
609 break;
610 }
611 case MSP430::Br: {
612 // op: rs
613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
614 Value |= (op & 0xf) << 8;
615 break;
616 }
617 case MSP430::CALLn:
618 case MSP430::CALLp:
619 case MSP430::CALLr:
620 case MSP430::PUSH16r:
621 case MSP430::PUSH8r:
622 case MSP430::RRA16n:
623 case MSP430::RRA16p:
624 case MSP430::RRA8n:
625 case MSP430::RRA8p:
626 case MSP430::RRC16n:
627 case MSP430::RRC16p:
628 case MSP430::RRC8n:
629 case MSP430::RRC8p:
630 case MSP430::SEXT16n:
631 case MSP430::SEXT16p:
632 case MSP430::SWPB16n:
633 case MSP430::SWPB16p: {
634 // op: rs
635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
636 Value |= (op & 0xf);
637 break;
638 }
639 case MSP430::BIT16rn:
640 case MSP430::BIT16rp:
641 case MSP430::BIT16rr:
642 case MSP430::BIT8rn:
643 case MSP430::BIT8rp:
644 case MSP430::BIT8rr:
645 case MSP430::CMP16rn:
646 case MSP430::CMP16rp:
647 case MSP430::CMP16rr:
648 case MSP430::CMP8rn:
649 case MSP430::CMP8rp:
650 case MSP430::CMP8rr:
651 case MSP430::MOV16rn:
652 case MSP430::MOV16rr:
653 case MSP430::MOV8rn:
654 case MSP430::MOV8rr:
655 case MSP430::MOVZX16rr8:
656 case MSP430::ZEXT16r: {
657 // op: rs
658 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
659 Value |= (op & 0xf) << 8;
660 // op: rd
661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
662 Value |= (op & 0xf);
663 break;
664 }
665 case MSP430::RRA16r:
666 case MSP430::RRA8r:
667 case MSP430::RRC16r:
668 case MSP430::RRC8r:
669 case MSP430::SEXT16r:
670 case MSP430::SWPB16r: {
671 // op: rs
672 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
673 Value |= (op & 0xf);
674 break;
675 }
676 case MSP430::ADD16mn:
677 case MSP430::ADD16mp:
678 case MSP430::ADD16mr:
679 case MSP430::ADD8mn:
680 case MSP430::ADD8mp:
681 case MSP430::ADD8mr:
682 case MSP430::ADDC16mn:
683 case MSP430::ADDC16mp:
684 case MSP430::ADDC16mr:
685 case MSP430::ADDC8mn:
686 case MSP430::ADDC8mp:
687 case MSP430::ADDC8mr:
688 case MSP430::AND16mn:
689 case MSP430::AND16mp:
690 case MSP430::AND16mr:
691 case MSP430::AND8mn:
692 case MSP430::AND8mp:
693 case MSP430::AND8mr:
694 case MSP430::BIC16mn:
695 case MSP430::BIC16mp:
696 case MSP430::BIC16mr:
697 case MSP430::BIC8mn:
698 case MSP430::BIC8mp:
699 case MSP430::BIC8mr:
700 case MSP430::BIS16mn:
701 case MSP430::BIS16mp:
702 case MSP430::BIS16mr:
703 case MSP430::BIS8mn:
704 case MSP430::BIS8mp:
705 case MSP430::BIS8mr:
706 case MSP430::BIT16mn:
707 case MSP430::BIT16mp:
708 case MSP430::BIT16mr:
709 case MSP430::BIT8mn:
710 case MSP430::BIT8mp:
711 case MSP430::BIT8mr:
712 case MSP430::CMP16mn:
713 case MSP430::CMP16mp:
714 case MSP430::CMP16mr:
715 case MSP430::CMP8mn:
716 case MSP430::CMP8mp:
717 case MSP430::CMP8mr:
718 case MSP430::DADD16mn:
719 case MSP430::DADD16mp:
720 case MSP430::DADD16mr:
721 case MSP430::DADD8mn:
722 case MSP430::DADD8mp:
723 case MSP430::DADD8mr:
724 case MSP430::MOV16mn:
725 case MSP430::MOV16mr:
726 case MSP430::MOV8mn:
727 case MSP430::MOV8mr:
728 case MSP430::SUB16mn:
729 case MSP430::SUB16mp:
730 case MSP430::SUB16mr:
731 case MSP430::SUB8mn:
732 case MSP430::SUB8mp:
733 case MSP430::SUB8mr:
734 case MSP430::SUBC16mn:
735 case MSP430::SUBC16mp:
736 case MSP430::SUBC16mr:
737 case MSP430::SUBC8mn:
738 case MSP430::SUBC8mp:
739 case MSP430::SUBC8mr:
740 case MSP430::XOR16mn:
741 case MSP430::XOR16mp:
742 case MSP430::XOR16mr:
743 case MSP430::XOR8mn:
744 case MSP430::XOR8mp:
745 case MSP430::XOR8mr: {
746 // op: rs
747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
748 Value |= (op & 0xf) << 8;
749 // op: dst
750 op = getMemOpValue(MI, Op: 0, Fixups, STI);
751 Value |= (op & 0xffff0) << 12;
752 Value |= (op & 0xf);
753 break;
754 }
755 case MSP430::ADD16rn:
756 case MSP430::ADD16rr:
757 case MSP430::ADD8rn:
758 case MSP430::ADD8rr:
759 case MSP430::ADDC16rn:
760 case MSP430::ADDC16rr:
761 case MSP430::ADDC8rn:
762 case MSP430::ADDC8rr:
763 case MSP430::AND16rn:
764 case MSP430::AND16rr:
765 case MSP430::AND8rn:
766 case MSP430::AND8rr:
767 case MSP430::BIC16rn:
768 case MSP430::BIC16rr:
769 case MSP430::BIC8rn:
770 case MSP430::BIC8rr:
771 case MSP430::BIS16rn:
772 case MSP430::BIS16rr:
773 case MSP430::BIS8rn:
774 case MSP430::BIS8rr:
775 case MSP430::DADD16rn:
776 case MSP430::DADD16rr:
777 case MSP430::DADD8rn:
778 case MSP430::DADD8rr:
779 case MSP430::MOV16rp:
780 case MSP430::MOV8rp:
781 case MSP430::SUB16rn:
782 case MSP430::SUB16rr:
783 case MSP430::SUB8rn:
784 case MSP430::SUB8rr:
785 case MSP430::SUBC16rn:
786 case MSP430::SUBC16rr:
787 case MSP430::SUBC8rn:
788 case MSP430::SUBC8rr:
789 case MSP430::XOR16rn:
790 case MSP430::XOR16rr:
791 case MSP430::XOR8rn:
792 case MSP430::XOR8rr: {
793 // op: rs
794 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
795 Value |= (op & 0xf) << 8;
796 // op: rd
797 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
798 Value |= (op & 0xf);
799 break;
800 }
801 case MSP430::ADD16rp:
802 case MSP430::ADD8rp:
803 case MSP430::ADDC16rp:
804 case MSP430::ADDC8rp:
805 case MSP430::AND16rp:
806 case MSP430::AND8rp:
807 case MSP430::BIC16rp:
808 case MSP430::BIC8rp:
809 case MSP430::BIS16rp:
810 case MSP430::BIS8rp:
811 case MSP430::DADD16rp:
812 case MSP430::DADD8rp:
813 case MSP430::SUB16rp:
814 case MSP430::SUB8rp:
815 case MSP430::SUBC16rp:
816 case MSP430::SUBC8rp:
817 case MSP430::XOR16rp:
818 case MSP430::XOR8rp: {
819 // op: rs
820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
821 Value |= (op & 0xf) << 8;
822 // op: rd
823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
824 Value |= (op & 0xf);
825 break;
826 }
827 case MSP430::Bm: {
828 // op: src
829 op = getMemOpValue(MI, Op: 0, Fixups, STI);
830 Value |= (op & 0xffff0) << 12;
831 Value |= (op & 0xf) << 8;
832 break;
833 }
834 case MSP430::CALLm:
835 case MSP430::RRA16m:
836 case MSP430::RRA8m:
837 case MSP430::RRC16m:
838 case MSP430::RRC8m:
839 case MSP430::SEXT16m:
840 case MSP430::SWPB16m: {
841 // op: src
842 op = getMemOpValue(MI, Op: 0, Fixups, STI);
843 Value |= (op & 0xffff0) << 12;
844 Value |= (op & 0xf);
845 break;
846 }
847 case MSP430::ADD16mm:
848 case MSP430::ADD8mm:
849 case MSP430::ADDC16mm:
850 case MSP430::ADDC8mm:
851 case MSP430::AND16mm:
852 case MSP430::AND8mm:
853 case MSP430::BIC16mm:
854 case MSP430::BIC8mm:
855 case MSP430::BIS16mm:
856 case MSP430::BIS8mm:
857 case MSP430::BIT16mm:
858 case MSP430::BIT8mm:
859 case MSP430::CMP16mm:
860 case MSP430::CMP8mm:
861 case MSP430::DADD16mm:
862 case MSP430::DADD8mm:
863 case MSP430::MOV16mm:
864 case MSP430::MOV8mm:
865 case MSP430::SUB16mm:
866 case MSP430::SUB8mm:
867 case MSP430::SUBC16mm:
868 case MSP430::SUBC8mm:
869 case MSP430::XOR16mm:
870 case MSP430::XOR8mm: {
871 // op: src
872 op = getMemOpValue(MI, Op: 2, Fixups, STI);
873 Value |= (op & 0xffff0) << 12;
874 Value |= (op & 0xf) << 8;
875 // op: dst
876 op = getMemOpValue(MI, Op: 0, Fixups, STI);
877 Value |= (op & 0xffff0) << 28;
878 Value |= (op & 0xf);
879 break;
880 }
881 default:
882 reportUnsupportedInst(Inst: MI);
883 }
884 return Value;
885}
886
887#ifdef GET_OPERAND_BIT_OFFSET
888#undef GET_OPERAND_BIT_OFFSET
889
890uint32_t MSP430MCCodeEmitter::getOperandBitOffset(const MCInst &MI,
891 unsigned OpNum,
892 const MCSubtargetInfo &STI) const {
893 switch (MI.getOpcode()) {
894 case MSP430::ADDframe:
895 case MSP430::ADJCALLSTACKDOWN:
896 case MSP430::ADJCALLSTACKUP:
897 case MSP430::RET:
898 case MSP430::RETI:
899 case MSP430::Rrcl16:
900 case MSP430::Rrcl8:
901 case MSP430::Select16:
902 case MSP430::Select8:
903 case MSP430::Shl16:
904 case MSP430::Shl8:
905 case MSP430::Sra16:
906 case MSP430::Sra8:
907 case MSP430::Srl16:
908 case MSP430::Srl8: {
909 break;
910 }
911 case MSP430::JMP: {
912 switch (OpNum) {
913 case 0:
914 // op: dst
915 return 0;
916 }
917 break;
918 }
919 case MSP430::PUSH16c: {
920 switch (OpNum) {
921 case 0:
922 // op: imm
923 return 0;
924 }
925 break;
926 }
927 case MSP430::Bi:
928 case MSP430::CALLi:
929 case MSP430::PUSH16i: {
930 switch (OpNum) {
931 case 0:
932 // op: imm
933 return 16;
934 }
935 break;
936 }
937 case MSP430::BIT16ri:
938 case MSP430::BIT8ri:
939 case MSP430::CMP16ri:
940 case MSP430::CMP8ri:
941 case MSP430::MOV16ri:
942 case MSP430::MOV8ri: {
943 switch (OpNum) {
944 case 0:
945 // op: rd
946 return 0;
947 case 1:
948 // op: imm
949 return 16;
950 }
951 break;
952 }
953 case MSP430::BIT16rm:
954 case MSP430::BIT8rm:
955 case MSP430::CMP16rm:
956 case MSP430::CMP8rm:
957 case MSP430::MOV16rm:
958 case MSP430::MOV8rm:
959 case MSP430::MOVZX16rm8: {
960 switch (OpNum) {
961 case 0:
962 // op: rd
963 return 0;
964 case 1:
965 // op: src
966 return 8;
967 }
968 break;
969 }
970 case MSP430::ADD16ri:
971 case MSP430::ADD8ri:
972 case MSP430::ADDC16ri:
973 case MSP430::ADDC8ri:
974 case MSP430::AND16ri:
975 case MSP430::AND8ri:
976 case MSP430::BIC16ri:
977 case MSP430::BIC8ri:
978 case MSP430::BIS16ri:
979 case MSP430::BIS8ri:
980 case MSP430::DADD16ri:
981 case MSP430::DADD8ri:
982 case MSP430::SUB16ri:
983 case MSP430::SUB8ri:
984 case MSP430::SUBC16ri:
985 case MSP430::SUBC8ri:
986 case MSP430::XOR16ri:
987 case MSP430::XOR8ri: {
988 switch (OpNum) {
989 case 0:
990 // op: rd
991 return 0;
992 case 2:
993 // op: imm
994 return 16;
995 }
996 break;
997 }
998 case MSP430::ADD16rm:
999 case MSP430::ADD8rm:
1000 case MSP430::ADDC16rm:
1001 case MSP430::ADDC8rm:
1002 case MSP430::AND16rm:
1003 case MSP430::AND8rm:
1004 case MSP430::BIC16rm:
1005 case MSP430::BIC8rm:
1006 case MSP430::BIS16rm:
1007 case MSP430::BIS8rm:
1008 case MSP430::DADD16rm:
1009 case MSP430::DADD8rm:
1010 case MSP430::SUB16rm:
1011 case MSP430::SUB8rm:
1012 case MSP430::SUBC16rm:
1013 case MSP430::SUBC8rm:
1014 case MSP430::XOR16rm:
1015 case MSP430::XOR8rm: {
1016 switch (OpNum) {
1017 case 0:
1018 // op: rd
1019 return 0;
1020 case 2:
1021 // op: src
1022 return 8;
1023 }
1024 break;
1025 }
1026 case MSP430::POP16r: {
1027 switch (OpNum) {
1028 case 0:
1029 // op: rd
1030 return 0;
1031 }
1032 break;
1033 }
1034 case MSP430::CALLn:
1035 case MSP430::CALLp:
1036 case MSP430::CALLr:
1037 case MSP430::PUSH16r:
1038 case MSP430::PUSH8r:
1039 case MSP430::RRA16n:
1040 case MSP430::RRA16p:
1041 case MSP430::RRA8n:
1042 case MSP430::RRA8p:
1043 case MSP430::RRC16n:
1044 case MSP430::RRC16p:
1045 case MSP430::RRC8n:
1046 case MSP430::RRC8p:
1047 case MSP430::SEXT16n:
1048 case MSP430::SEXT16p:
1049 case MSP430::SWPB16n:
1050 case MSP430::SWPB16p: {
1051 switch (OpNum) {
1052 case 0:
1053 // op: rs
1054 return 0;
1055 }
1056 break;
1057 }
1058 case MSP430::Br: {
1059 switch (OpNum) {
1060 case 0:
1061 // op: rs
1062 return 8;
1063 }
1064 break;
1065 }
1066 case MSP430::CALLm:
1067 case MSP430::RRA16m:
1068 case MSP430::RRA8m:
1069 case MSP430::RRC16m:
1070 case MSP430::RRC8m:
1071 case MSP430::SEXT16m:
1072 case MSP430::SWPB16m: {
1073 switch (OpNum) {
1074 case 0:
1075 // op: src
1076 return 0;
1077 }
1078 break;
1079 }
1080 case MSP430::Bm: {
1081 switch (OpNum) {
1082 case 0:
1083 // op: src
1084 return 8;
1085 }
1086 break;
1087 }
1088 case MSP430::JCC: {
1089 switch (OpNum) {
1090 case 1:
1091 // op: cond
1092 return 10;
1093 case 0:
1094 // op: dst
1095 return 0;
1096 }
1097 break;
1098 }
1099 case MSP430::BIT16rc:
1100 case MSP430::BIT8rc:
1101 case MSP430::CMP16rc:
1102 case MSP430::CMP8rc:
1103 case MSP430::MOV16rc:
1104 case MSP430::MOV8rc: {
1105 switch (OpNum) {
1106 case 1:
1107 // op: imm
1108 return 4;
1109 case 0:
1110 // op: rd
1111 return 0;
1112 }
1113 break;
1114 }
1115 case MSP430::RRA16r:
1116 case MSP430::RRA8r:
1117 case MSP430::RRC16r:
1118 case MSP430::RRC8r:
1119 case MSP430::SEXT16r:
1120 case MSP430::SWPB16r: {
1121 switch (OpNum) {
1122 case 1:
1123 // op: rs
1124 return 0;
1125 }
1126 break;
1127 }
1128 case MSP430::BIT16rn:
1129 case MSP430::BIT16rp:
1130 case MSP430::BIT16rr:
1131 case MSP430::BIT8rn:
1132 case MSP430::BIT8rp:
1133 case MSP430::BIT8rr:
1134 case MSP430::CMP16rn:
1135 case MSP430::CMP16rp:
1136 case MSP430::CMP16rr:
1137 case MSP430::CMP8rn:
1138 case MSP430::CMP8rp:
1139 case MSP430::CMP8rr:
1140 case MSP430::MOV16rn:
1141 case MSP430::MOV16rr:
1142 case MSP430::MOV8rn:
1143 case MSP430::MOV8rr:
1144 case MSP430::MOVZX16rr8:
1145 case MSP430::ZEXT16r: {
1146 switch (OpNum) {
1147 case 1:
1148 // op: rs
1149 return 8;
1150 case 0:
1151 // op: rd
1152 return 0;
1153 }
1154 break;
1155 }
1156 case MSP430::ADD16mi:
1157 case MSP430::ADD8mi:
1158 case MSP430::ADDC16mi:
1159 case MSP430::ADDC8mi:
1160 case MSP430::AND16mi:
1161 case MSP430::AND8mi:
1162 case MSP430::BIC16mi:
1163 case MSP430::BIC8mi:
1164 case MSP430::BIS16mi:
1165 case MSP430::BIS8mi:
1166 case MSP430::BIT16mi:
1167 case MSP430::BIT8mi:
1168 case MSP430::CMP16mi:
1169 case MSP430::CMP8mi:
1170 case MSP430::DADD16mi:
1171 case MSP430::DADD8mi:
1172 case MSP430::MOV16mi:
1173 case MSP430::MOV8mi:
1174 case MSP430::SUB16mi:
1175 case MSP430::SUB8mi:
1176 case MSP430::SUBC16mi:
1177 case MSP430::SUBC8mi:
1178 case MSP430::XOR16mi:
1179 case MSP430::XOR8mi: {
1180 switch (OpNum) {
1181 case 2:
1182 // op: imm
1183 return 16;
1184 case 0:
1185 // op: dst
1186 return 0;
1187 }
1188 break;
1189 }
1190 case MSP430::ADD16mc:
1191 case MSP430::ADD8mc:
1192 case MSP430::ADDC16mc:
1193 case MSP430::ADDC8mc:
1194 case MSP430::AND16mc:
1195 case MSP430::AND8mc:
1196 case MSP430::BIC16mc:
1197 case MSP430::BIC8mc:
1198 case MSP430::BIS16mc:
1199 case MSP430::BIS8mc:
1200 case MSP430::BIT16mc:
1201 case MSP430::BIT8mc:
1202 case MSP430::CMP16mc:
1203 case MSP430::CMP8mc:
1204 case MSP430::DADD16mc:
1205 case MSP430::DADD8mc:
1206 case MSP430::MOV16mc:
1207 case MSP430::MOV8mc:
1208 case MSP430::SUB16mc:
1209 case MSP430::SUB8mc:
1210 case MSP430::SUBC16mc:
1211 case MSP430::SUBC8mc:
1212 case MSP430::XOR16mc:
1213 case MSP430::XOR8mc: {
1214 switch (OpNum) {
1215 case 2:
1216 // op: imm
1217 return 4;
1218 case 0:
1219 // op: dst
1220 return 0;
1221 }
1222 break;
1223 }
1224 case MSP430::ADD16rc:
1225 case MSP430::ADD8rc:
1226 case MSP430::ADDC16rc:
1227 case MSP430::ADDC8rc:
1228 case MSP430::AND16rc:
1229 case MSP430::AND8rc:
1230 case MSP430::BIC16rc:
1231 case MSP430::BIC8rc:
1232 case MSP430::BIS16rc:
1233 case MSP430::BIS8rc:
1234 case MSP430::DADD16rc:
1235 case MSP430::DADD8rc:
1236 case MSP430::SUB16rc:
1237 case MSP430::SUB8rc:
1238 case MSP430::SUBC16rc:
1239 case MSP430::SUBC8rc:
1240 case MSP430::XOR16rc:
1241 case MSP430::XOR8rc: {
1242 switch (OpNum) {
1243 case 2:
1244 // op: imm
1245 return 4;
1246 case 0:
1247 // op: rd
1248 return 0;
1249 }
1250 break;
1251 }
1252 case MSP430::ADD16mn:
1253 case MSP430::ADD16mp:
1254 case MSP430::ADD16mr:
1255 case MSP430::ADD8mn:
1256 case MSP430::ADD8mp:
1257 case MSP430::ADD8mr:
1258 case MSP430::ADDC16mn:
1259 case MSP430::ADDC16mp:
1260 case MSP430::ADDC16mr:
1261 case MSP430::ADDC8mn:
1262 case MSP430::ADDC8mp:
1263 case MSP430::ADDC8mr:
1264 case MSP430::AND16mn:
1265 case MSP430::AND16mp:
1266 case MSP430::AND16mr:
1267 case MSP430::AND8mn:
1268 case MSP430::AND8mp:
1269 case MSP430::AND8mr:
1270 case MSP430::BIC16mn:
1271 case MSP430::BIC16mp:
1272 case MSP430::BIC16mr:
1273 case MSP430::BIC8mn:
1274 case MSP430::BIC8mp:
1275 case MSP430::BIC8mr:
1276 case MSP430::BIS16mn:
1277 case MSP430::BIS16mp:
1278 case MSP430::BIS16mr:
1279 case MSP430::BIS8mn:
1280 case MSP430::BIS8mp:
1281 case MSP430::BIS8mr:
1282 case MSP430::BIT16mn:
1283 case MSP430::BIT16mp:
1284 case MSP430::BIT16mr:
1285 case MSP430::BIT8mn:
1286 case MSP430::BIT8mp:
1287 case MSP430::BIT8mr:
1288 case MSP430::CMP16mn:
1289 case MSP430::CMP16mp:
1290 case MSP430::CMP16mr:
1291 case MSP430::CMP8mn:
1292 case MSP430::CMP8mp:
1293 case MSP430::CMP8mr:
1294 case MSP430::DADD16mn:
1295 case MSP430::DADD16mp:
1296 case MSP430::DADD16mr:
1297 case MSP430::DADD8mn:
1298 case MSP430::DADD8mp:
1299 case MSP430::DADD8mr:
1300 case MSP430::MOV16mn:
1301 case MSP430::MOV16mr:
1302 case MSP430::MOV8mn:
1303 case MSP430::MOV8mr:
1304 case MSP430::SUB16mn:
1305 case MSP430::SUB16mp:
1306 case MSP430::SUB16mr:
1307 case MSP430::SUB8mn:
1308 case MSP430::SUB8mp:
1309 case MSP430::SUB8mr:
1310 case MSP430::SUBC16mn:
1311 case MSP430::SUBC16mp:
1312 case MSP430::SUBC16mr:
1313 case MSP430::SUBC8mn:
1314 case MSP430::SUBC8mp:
1315 case MSP430::SUBC8mr:
1316 case MSP430::XOR16mn:
1317 case MSP430::XOR16mp:
1318 case MSP430::XOR16mr:
1319 case MSP430::XOR8mn:
1320 case MSP430::XOR8mp:
1321 case MSP430::XOR8mr: {
1322 switch (OpNum) {
1323 case 2:
1324 // op: rs
1325 return 8;
1326 case 0:
1327 // op: dst
1328 return 0;
1329 }
1330 break;
1331 }
1332 case MSP430::ADD16rn:
1333 case MSP430::ADD16rr:
1334 case MSP430::ADD8rn:
1335 case MSP430::ADD8rr:
1336 case MSP430::ADDC16rn:
1337 case MSP430::ADDC16rr:
1338 case MSP430::ADDC8rn:
1339 case MSP430::ADDC8rr:
1340 case MSP430::AND16rn:
1341 case MSP430::AND16rr:
1342 case MSP430::AND8rn:
1343 case MSP430::AND8rr:
1344 case MSP430::BIC16rn:
1345 case MSP430::BIC16rr:
1346 case MSP430::BIC8rn:
1347 case MSP430::BIC8rr:
1348 case MSP430::BIS16rn:
1349 case MSP430::BIS16rr:
1350 case MSP430::BIS8rn:
1351 case MSP430::BIS8rr:
1352 case MSP430::DADD16rn:
1353 case MSP430::DADD16rr:
1354 case MSP430::DADD8rn:
1355 case MSP430::DADD8rr:
1356 case MSP430::MOV16rp:
1357 case MSP430::MOV8rp:
1358 case MSP430::SUB16rn:
1359 case MSP430::SUB16rr:
1360 case MSP430::SUB8rn:
1361 case MSP430::SUB8rr:
1362 case MSP430::SUBC16rn:
1363 case MSP430::SUBC16rr:
1364 case MSP430::SUBC8rn:
1365 case MSP430::SUBC8rr:
1366 case MSP430::XOR16rn:
1367 case MSP430::XOR16rr:
1368 case MSP430::XOR8rn:
1369 case MSP430::XOR8rr: {
1370 switch (OpNum) {
1371 case 2:
1372 // op: rs
1373 return 8;
1374 case 0:
1375 // op: rd
1376 return 0;
1377 }
1378 break;
1379 }
1380 case MSP430::ADD16mm:
1381 case MSP430::ADD8mm:
1382 case MSP430::ADDC16mm:
1383 case MSP430::ADDC8mm:
1384 case MSP430::AND16mm:
1385 case MSP430::AND8mm:
1386 case MSP430::BIC16mm:
1387 case MSP430::BIC8mm:
1388 case MSP430::BIS16mm:
1389 case MSP430::BIS8mm:
1390 case MSP430::BIT16mm:
1391 case MSP430::BIT8mm:
1392 case MSP430::CMP16mm:
1393 case MSP430::CMP8mm:
1394 case MSP430::DADD16mm:
1395 case MSP430::DADD8mm:
1396 case MSP430::MOV16mm:
1397 case MSP430::MOV8mm:
1398 case MSP430::SUB16mm:
1399 case MSP430::SUB8mm:
1400 case MSP430::SUBC16mm:
1401 case MSP430::SUBC8mm:
1402 case MSP430::XOR16mm:
1403 case MSP430::XOR8mm: {
1404 switch (OpNum) {
1405 case 2:
1406 // op: src
1407 return 8;
1408 case 0:
1409 // op: dst
1410 return 0;
1411 }
1412 break;
1413 }
1414 case MSP430::ADD16rp:
1415 case MSP430::ADD8rp:
1416 case MSP430::ADDC16rp:
1417 case MSP430::ADDC8rp:
1418 case MSP430::AND16rp:
1419 case MSP430::AND8rp:
1420 case MSP430::BIC16rp:
1421 case MSP430::BIC8rp:
1422 case MSP430::BIS16rp:
1423 case MSP430::BIS8rp:
1424 case MSP430::DADD16rp:
1425 case MSP430::DADD8rp:
1426 case MSP430::SUB16rp:
1427 case MSP430::SUB8rp:
1428 case MSP430::SUBC16rp:
1429 case MSP430::SUBC8rp:
1430 case MSP430::XOR16rp:
1431 case MSP430::XOR8rp: {
1432 switch (OpNum) {
1433 case 3:
1434 // op: rs
1435 return 8;
1436 case 0:
1437 // op: rd
1438 return 0;
1439 }
1440 break;
1441 }
1442 default:
1443 reportUnsupportedInst(MI);
1444 }
1445 reportUnsupportedOperand(MI, OpNum);
1446}
1447
1448#endif // GET_OPERAND_BIT_OFFSET
1449
1450