| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Instruction Enum Values and Descriptors *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_INSTRINFO_ENUM |
| 10 | #undef GET_INSTRINFO_ENUM |
| 11 | |
| 12 | namespace llvm::Mips { |
| 13 | |
| 14 | enum { |
| 15 | PHI = 0, // Target.td:1314 |
| 16 | INLINEASM = 1, // Target.td:1320 |
| 17 | INLINEASM_BR = 2, // Target.td:1326 |
| 18 | CFI_INSTRUCTION = 3, // Target.td:1335 |
| 19 | EH_LABEL = 4, // Target.td:1344 |
| 20 | GC_LABEL = 5, // Target.td:1353 |
| 21 | ANNOTATION_LABEL = 6, // Target.td:1362 |
| 22 | KILL = 7, // Target.td:1370 |
| 23 | EXTRACT_SUBREG = 8, // Target.td:1377 |
| 24 | INSERT_SUBREG = 9, // Target.td:1383 |
| 25 | IMPLICIT_DEF = 10, // Target.td:1390 |
| 26 | INIT_UNDEF = 11, // Target.td:1399 |
| 27 | SUBREG_TO_REG = 12, // Target.td:1406 |
| 28 | COPY_TO_REGCLASS = 13, // Target.td:1412 |
| 29 | DBG_VALUE = 14, // Target.td:1419 |
| 30 | DBG_VALUE_LIST = 15, // Target.td:1426 |
| 31 | DBG_INSTR_REF = 16, // Target.td:1433 |
| 32 | DBG_PHI = 17, // Target.td:1440 |
| 33 | DBG_LABEL = 18, // Target.td:1447 |
| 34 | REG_SEQUENCE = 19, // Target.td:1454 |
| 35 | COPY = 20, // Target.td:1461 |
| 36 | COPY_LANEMASK = 21, // Target.td:1469 |
| 37 | BUNDLE = 22, // Target.td:1476 |
| 38 | LIFETIME_START = 23, // Target.td:1482 |
| 39 | LIFETIME_END = 24, // Target.td:1489 |
| 40 | PSEUDO_PROBE = 25, // Target.td:1496 |
| 41 | ARITH_FENCE = 26, // Target.td:1503 |
| 42 | STACKMAP = 27, // Target.td:1512 |
| 43 | FENTRY_CALL = 28, // Target.td:1647 |
| 44 | PATCHPOINT = 29, // Target.td:1520 |
| 45 | LOAD_STACK_GUARD = 30, // Target.td:1538 |
| 46 | PREALLOCATED_SETUP = 31, // Target.td:1546 |
| 47 | PREALLOCATED_ARG = 32, // Target.td:1552 |
| 48 | STATEPOINT = 33, // Target.td:1529 |
| 49 | LOCAL_ESCAPE = 34, // Target.td:1558 |
| 50 | FAULTING_OP = 35, // Target.td:1567 |
| 51 | PATCHABLE_OP = 36, // Target.td:1587 |
| 52 | PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595 |
| 53 | PATCHABLE_RET = 38, // Target.td:1602 |
| 54 | PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611 |
| 55 | PATCHABLE_TAIL_CALL = 40, // Target.td:1619 |
| 56 | PATCHABLE_EVENT_CALL = 41, // Target.td:1627 |
| 57 | PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637 |
| 58 | ICALL_BRANCH_FUNNEL = 43, // Target.td:1657 |
| 59 | FAKE_USE = 44, // Target.td:1577 |
| 60 | MEMBARRIER = 45, // Target.td:1663 |
| 61 | JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671 |
| 62 | RELOC_NONE = 47, // Target.td:1679 |
| 63 | CONVERGENCECTRL_ENTRY = 48, // Target.td:1691 |
| 64 | CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687 |
| 65 | CONVERGENCECTRL_LOOP = 50, // Target.td:1695 |
| 66 | CONVERGENCECTRL_GLUE = 51, // Target.td:1699 |
| 67 | G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955 |
| 68 | G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947 |
| 69 | G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962 |
| 70 | G_ADD = 55, // GenericOpcodes.td:308 |
| 71 | G_SUB = 56, // GenericOpcodes.td:316 |
| 72 | G_MUL = 57, // GenericOpcodes.td:324 |
| 73 | G_SDIV = 58, // GenericOpcodes.td:332 |
| 74 | G_UDIV = 59, // GenericOpcodes.td:340 |
| 75 | G_SREM = 60, // GenericOpcodes.td:348 |
| 76 | G_UREM = 61, // GenericOpcodes.td:356 |
| 77 | G_SDIVREM = 62, // GenericOpcodes.td:364 |
| 78 | G_UDIVREM = 63, // GenericOpcodes.td:372 |
| 79 | G_AND = 64, // GenericOpcodes.td:380 |
| 80 | G_OR = 65, // GenericOpcodes.td:388 |
| 81 | G_XOR = 66, // GenericOpcodes.td:396 |
| 82 | G_ABDS = 67, // GenericOpcodes.td:425 |
| 83 | G_ABDU = 68, // GenericOpcodes.td:433 |
| 84 | G_UAVGFLOOR = 69, // GenericOpcodes.td:441 |
| 85 | G_UAVGCEIL = 70, // GenericOpcodes.td:448 |
| 86 | G_SAVGFLOOR = 71, // GenericOpcodes.td:455 |
| 87 | G_SAVGCEIL = 72, // GenericOpcodes.td:462 |
| 88 | G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111 |
| 89 | G_PHI = 74, // GenericOpcodes.td:118 |
| 90 | G_FRAME_INDEX = 75, // GenericOpcodes.td:125 |
| 91 | G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131 |
| 92 | G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137 |
| 93 | G_CONSTANT_POOL = 78, // GenericOpcodes.td:143 |
| 94 | G_EXTRACT = 79, // GenericOpcodes.td:1540 |
| 95 | G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553 |
| 96 | G_INSERT = 81, // GenericOpcodes.td:1562 |
| 97 | G_MERGE_VALUES = 82, // GenericOpcodes.td:1572 |
| 98 | G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592 |
| 99 | G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602 |
| 100 | G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609 |
| 101 | G_PTRTOINT = 86, // GenericOpcodes.td:155 |
| 102 | G_INTTOPTR = 87, // GenericOpcodes.td:149 |
| 103 | G_BITCAST = 88, // GenericOpcodes.td:161 |
| 104 | G_FREEZE = 89, // GenericOpcodes.td:284 |
| 105 | G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969 |
| 106 | G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298 |
| 107 | G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304 |
| 108 | G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310 |
| 109 | G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316 |
| 110 | G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322 |
| 111 | G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328 |
| 112 | G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334 |
| 113 | G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340 |
| 114 | G_LOAD = 99, // GenericOpcodes.td:1367 |
| 115 | G_SEXTLOAD = 100, // GenericOpcodes.td:1376 |
| 116 | G_ZEXTLOAD = 101, // GenericOpcodes.td:1384 |
| 117 | G_FPEXTLOAD = 102, // GenericOpcodes.td:1393 |
| 118 | G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403 |
| 119 | G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412 |
| 120 | G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420 |
| 121 | G_STORE = 106, // GenericOpcodes.td:1428 |
| 122 | G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438 |
| 123 | G_INDEXED_STORE = 108, // GenericOpcodes.td:1446 |
| 124 | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457 |
| 125 | G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468 |
| 126 | G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488 |
| 127 | G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489 |
| 128 | G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490 |
| 129 | G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491 |
| 130 | G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492 |
| 131 | G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493 |
| 132 | G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494 |
| 133 | G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495 |
| 134 | G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496 |
| 135 | G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497 |
| 136 | G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498 |
| 137 | G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509 |
| 138 | G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510 |
| 139 | G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511 |
| 140 | G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512 |
| 141 | G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513 |
| 142 | G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514 |
| 143 | G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515 |
| 144 | G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516 |
| 145 | G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499 |
| 146 | G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500 |
| 147 | G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501 |
| 148 | G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502 |
| 149 | G_FENCE = 134, // GenericOpcodes.td:1518 |
| 150 | G_PREFETCH = 135, // GenericOpcodes.td:1525 |
| 151 | G_BRCOND = 136, // GenericOpcodes.td:1665 |
| 152 | G_BRINDIRECT = 137, // GenericOpcodes.td:1674 |
| 153 | G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697 |
| 154 | G_INTRINSIC = 139, // GenericOpcodes.td:1617 |
| 155 | G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624 |
| 156 | G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633 |
| 157 | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641 |
| 158 | G_ANYEXT = 143, // GenericOpcodes.td:44 |
| 159 | G_TRUNC = 144, // GenericOpcodes.td:83 |
| 160 | G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91 |
| 161 | G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98 |
| 162 | G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105 |
| 163 | G_CONSTANT = 148, // GenericOpcodes.td:169 |
| 164 | G_FCONSTANT = 149, // GenericOpcodes.td:177 |
| 165 | G_VASTART = 150, // GenericOpcodes.td:184 |
| 166 | G_VAARG = 151, // GenericOpcodes.td:191 |
| 167 | G_SEXT = 152, // GenericOpcodes.td:52 |
| 168 | G_SEXT_INREG = 153, // GenericOpcodes.td:66 |
| 169 | G_ZEXT = 154, // GenericOpcodes.td:74 |
| 170 | G_SHL = 155, // GenericOpcodes.td:404 |
| 171 | G_LSHR = 156, // GenericOpcodes.td:411 |
| 172 | G_ASHR = 157, // GenericOpcodes.td:418 |
| 173 | G_FSHL = 158, // GenericOpcodes.td:470 |
| 174 | G_FSHR = 159, // GenericOpcodes.td:478 |
| 175 | G_ROTR = 160, // GenericOpcodes.td:485 |
| 176 | G_ROTL = 161, // GenericOpcodes.td:492 |
| 177 | G_ICMP = 162, // GenericOpcodes.td:499 |
| 178 | G_FCMP = 163, // GenericOpcodes.td:506 |
| 179 | G_SCMP = 164, // GenericOpcodes.td:513 |
| 180 | G_UCMP = 165, // GenericOpcodes.td:520 |
| 181 | G_SELECT = 166, // GenericOpcodes.td:527 |
| 182 | G_UADDO = 167, // GenericOpcodes.td:619 |
| 183 | G_UADDE = 168, // GenericOpcodes.td:627 |
| 184 | G_USUBO = 169, // GenericOpcodes.td:649 |
| 185 | G_USUBE = 170, // GenericOpcodes.td:655 |
| 186 | G_SADDO = 171, // GenericOpcodes.td:634 |
| 187 | G_SADDE = 172, // GenericOpcodes.td:642 |
| 188 | G_SSUBO = 173, // GenericOpcodes.td:662 |
| 189 | G_SSUBE = 174, // GenericOpcodes.td:669 |
| 190 | G_UMULO = 175, // GenericOpcodes.td:676 |
| 191 | G_SMULO = 176, // GenericOpcodes.td:684 |
| 192 | G_UMULH = 177, // GenericOpcodes.td:693 |
| 193 | G_SMULH = 178, // GenericOpcodes.td:702 |
| 194 | G_UADDSAT = 179, // GenericOpcodes.td:714 |
| 195 | G_SADDSAT = 180, // GenericOpcodes.td:722 |
| 196 | G_USUBSAT = 181, // GenericOpcodes.td:730 |
| 197 | G_SSUBSAT = 182, // GenericOpcodes.td:738 |
| 198 | G_USHLSAT = 183, // GenericOpcodes.td:746 |
| 199 | G_SSHLSAT = 184, // GenericOpcodes.td:754 |
| 200 | G_SMULFIX = 185, // GenericOpcodes.td:766 |
| 201 | G_UMULFIX = 186, // GenericOpcodes.td:773 |
| 202 | G_SMULFIXSAT = 187, // GenericOpcodes.td:783 |
| 203 | G_UMULFIXSAT = 188, // GenericOpcodes.td:790 |
| 204 | G_SDIVFIX = 189, // GenericOpcodes.td:801 |
| 205 | G_UDIVFIX = 190, // GenericOpcodes.td:808 |
| 206 | G_SDIVFIXSAT = 191, // GenericOpcodes.td:818 |
| 207 | G_UDIVFIXSAT = 192, // GenericOpcodes.td:825 |
| 208 | G_FADD = 193, // GenericOpcodes.td:998 |
| 209 | G_FSUB = 194, // GenericOpcodes.td:1006 |
| 210 | G_FMUL = 195, // GenericOpcodes.td:1014 |
| 211 | G_FMA = 196, // GenericOpcodes.td:1023 |
| 212 | G_FMAD = 197, // GenericOpcodes.td:1032 |
| 213 | G_FDIV = 198, // GenericOpcodes.td:1040 |
| 214 | G_FREM = 199, // GenericOpcodes.td:1047 |
| 215 | G_FMODF = 200, // GenericOpcodes.td:1054 |
| 216 | G_FPOW = 201, // GenericOpcodes.td:1061 |
| 217 | G_FPOWI = 202, // GenericOpcodes.td:1068 |
| 218 | G_FEXP = 203, // GenericOpcodes.td:1075 |
| 219 | G_FEXP2 = 204, // GenericOpcodes.td:1082 |
| 220 | G_FEXP10 = 205, // GenericOpcodes.td:1089 |
| 221 | G_FLOG = 206, // GenericOpcodes.td:1096 |
| 222 | G_FLOG2 = 207, // GenericOpcodes.td:1103 |
| 223 | G_FLOG10 = 208, // GenericOpcodes.td:1110 |
| 224 | G_FLDEXP = 209, // GenericOpcodes.td:1117 |
| 225 | G_FFREXP = 210, // GenericOpcodes.td:1124 |
| 226 | G_FNEG = 211, // GenericOpcodes.td:836 |
| 227 | G_FPEXT = 212, // GenericOpcodes.td:842 |
| 228 | G_FPTRUNC = 213, // GenericOpcodes.td:848 |
| 229 | G_FPTOSI = 214, // GenericOpcodes.td:854 |
| 230 | G_FPTOUI = 215, // GenericOpcodes.td:860 |
| 231 | G_SITOFP = 216, // GenericOpcodes.td:866 |
| 232 | G_UITOFP = 217, // GenericOpcodes.td:872 |
| 233 | G_FPTOSI_SAT = 218, // GenericOpcodes.td:878 |
| 234 | G_FPTOUI_SAT = 219, // GenericOpcodes.td:884 |
| 235 | G_FABS = 220, // GenericOpcodes.td:890 |
| 236 | G_FCOPYSIGN = 221, // GenericOpcodes.td:896 |
| 237 | G_IS_FPCLASS = 222, // GenericOpcodes.td:909 |
| 238 | G_FCANONICALIZE = 223, // GenericOpcodes.td:902 |
| 239 | G_FMINNUM = 224, // GenericOpcodes.td:922 |
| 240 | G_FMAXNUM = 225, // GenericOpcodes.td:929 |
| 241 | G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947 |
| 242 | G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954 |
| 243 | G_FMINIMUM = 228, // GenericOpcodes.td:964 |
| 244 | G_FMAXIMUM = 229, // GenericOpcodes.td:971 |
| 245 | G_FMINIMUMNUM = 230, // GenericOpcodes.td:979 |
| 246 | G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986 |
| 247 | G_GET_FPENV = 232, // GenericOpcodes.td:1254 |
| 248 | G_SET_FPENV = 233, // GenericOpcodes.td:1261 |
| 249 | G_RESET_FPENV = 234, // GenericOpcodes.td:1268 |
| 250 | G_GET_FPMODE = 235, // GenericOpcodes.td:1275 |
| 251 | G_SET_FPMODE = 236, // GenericOpcodes.td:1282 |
| 252 | G_RESET_FPMODE = 237, // GenericOpcodes.td:1289 |
| 253 | G_GET_ROUNDING = 238, // GenericOpcodes.td:1346 |
| 254 | G_SET_ROUNDING = 239, // GenericOpcodes.td:1352 |
| 255 | G_PTR_ADD = 240, // GenericOpcodes.td:534 |
| 256 | G_PTRMASK = 241, // GenericOpcodes.td:542 |
| 257 | G_SMIN = 242, // GenericOpcodes.td:549 |
| 258 | G_SMAX = 243, // GenericOpcodes.td:557 |
| 259 | G_UMIN = 244, // GenericOpcodes.td:565 |
| 260 | G_UMAX = 245, // GenericOpcodes.td:573 |
| 261 | G_ABS = 246, // GenericOpcodes.td:581 |
| 262 | G_LROUND = 247, // GenericOpcodes.td:291 |
| 263 | G_LLROUND = 248, // GenericOpcodes.td:297 |
| 264 | G_BR = 249, // GenericOpcodes.td:1655 |
| 265 | G_BRJT = 250, // GenericOpcodes.td:1685 |
| 266 | G_VSCALE = 251, // GenericOpcodes.td:1583 |
| 267 | G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729 |
| 268 | G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737 |
| 269 | G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745 |
| 270 | G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753 |
| 271 | G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764 |
| 272 | G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772 |
| 273 | G_STEP_VECTOR = 258, // GenericOpcodes.td:1780 |
| 274 | G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787 |
| 275 | G_CTTZ = 260, // GenericOpcodes.td:211 |
| 276 | G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217 |
| 277 | G_CTLZ = 262, // GenericOpcodes.td:199 |
| 278 | G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205 |
| 279 | G_CTLS = 264, // GenericOpcodes.td:223 |
| 280 | G_CTPOP = 265, // GenericOpcodes.td:229 |
| 281 | G_BSWAP = 266, // GenericOpcodes.td:235 |
| 282 | G_BITREVERSE = 267, // GenericOpcodes.td:242 |
| 283 | G_CLMUL = 268, // GenericOpcodes.td:588 |
| 284 | G_CLMULH = 269, // GenericOpcodes.td:596 |
| 285 | G_CLMULR = 270, // GenericOpcodes.td:606 |
| 286 | G_FCEIL = 271, // GenericOpcodes.td:1131 |
| 287 | G_FCOS = 272, // GenericOpcodes.td:1138 |
| 288 | G_FSIN = 273, // GenericOpcodes.td:1145 |
| 289 | G_FSINCOS = 274, // GenericOpcodes.td:1152 |
| 290 | G_FTAN = 275, // GenericOpcodes.td:1159 |
| 291 | G_FACOS = 276, // GenericOpcodes.td:1166 |
| 292 | G_FASIN = 277, // GenericOpcodes.td:1173 |
| 293 | G_FATAN = 278, // GenericOpcodes.td:1180 |
| 294 | G_FATAN2 = 279, // GenericOpcodes.td:1187 |
| 295 | G_FCOSH = 280, // GenericOpcodes.td:1194 |
| 296 | G_FSINH = 281, // GenericOpcodes.td:1201 |
| 297 | G_FTANH = 282, // GenericOpcodes.td:1208 |
| 298 | G_FSQRT = 283, // GenericOpcodes.td:1218 |
| 299 | G_FFLOOR = 284, // GenericOpcodes.td:1225 |
| 300 | G_FRINT = 285, // GenericOpcodes.td:1232 |
| 301 | G_FNEARBYINT = 286, // GenericOpcodes.td:1239 |
| 302 | G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248 |
| 303 | G_BLOCK_ADDR = 288, // GenericOpcodes.td:254 |
| 304 | G_JUMP_TABLE = 289, // GenericOpcodes.td:260 |
| 305 | G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266 |
| 306 | G_STACKSAVE = 291, // GenericOpcodes.td:272 |
| 307 | G_STACKRESTORE = 292, // GenericOpcodes.td:278 |
| 308 | G_STRICT_FADD = 293, // GenericOpcodes.td:1839 |
| 309 | G_STRICT_FSUB = 294, // GenericOpcodes.td:1840 |
| 310 | G_STRICT_FMUL = 295, // GenericOpcodes.td:1841 |
| 311 | G_STRICT_FDIV = 296, // GenericOpcodes.td:1842 |
| 312 | G_STRICT_FREM = 297, // GenericOpcodes.td:1843 |
| 313 | G_STRICT_FMA = 298, // GenericOpcodes.td:1844 |
| 314 | G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845 |
| 315 | G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846 |
| 316 | G_STRICT_FCMP = 301, // GenericOpcodes.td:1847 |
| 317 | G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848 |
| 318 | G_READ_REGISTER = 303, // GenericOpcodes.td:1704 |
| 319 | G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714 |
| 320 | G_MEMCPY = 305, // GenericOpcodes.td:1854 |
| 321 | G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862 |
| 322 | G_MEMMOVE = 307, // GenericOpcodes.td:1870 |
| 323 | G_MEMSET = 308, // GenericOpcodes.td:1878 |
| 324 | G_BZERO = 309, // GenericOpcodes.td:1885 |
| 325 | G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892 |
| 326 | G_TRAP = 311, // GenericOpcodes.td:1902 |
| 327 | G_DEBUGTRAP = 312, // GenericOpcodes.td:1909 |
| 328 | G_UBSANTRAP = 313, // GenericOpcodes.td:1915 |
| 329 | G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803 |
| 330 | G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809 |
| 331 | G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815 |
| 332 | G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816 |
| 333 | G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818 |
| 334 | G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819 |
| 335 | G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820 |
| 336 | G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821 |
| 337 | G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822 |
| 338 | G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823 |
| 339 | G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825 |
| 340 | G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826 |
| 341 | G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827 |
| 342 | G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828 |
| 343 | G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829 |
| 344 | G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830 |
| 345 | G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831 |
| 346 | G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832 |
| 347 | G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833 |
| 348 | G_SBFX = 333, // GenericOpcodes.td:1927 |
| 349 | G_UBFX = 334, // GenericOpcodes.td:1935 |
| 350 | ABSMacro = 335, // MipsInstrInfo.td:2625 |
| 351 | ADJCALLSTACKDOWN = 336, // MipsInstrInfo.td:1926 |
| 352 | ADJCALLSTACKUP = 337, // MipsInstrInfo.td:1928 |
| 353 | AND_V_D_PSEUDO = 338, // MipsMSAInstrInfo.td:2657 |
| 354 | AND_V_H_PSEUDO = 339, // MipsMSAInstrInfo.td:2649 |
| 355 | AND_V_W_PSEUDO = 340, // MipsMSAInstrInfo.td:2653 |
| 356 | ATOMIC_CMP_SWAP_I16 = 341, // MipsInstrInfo.td:1957 |
| 357 | ATOMIC_CMP_SWAP_I16_POSTRA = 342, // MipsInstrInfo.td:1998 |
| 358 | ATOMIC_CMP_SWAP_I32 = 343, // MipsInstrInfo.td:1958 |
| 359 | ATOMIC_CMP_SWAP_I32_POSTRA = 344, // MipsInstrInfo.td:1999 |
| 360 | ATOMIC_CMP_SWAP_I64 = 345, // Mips64InstrInfo.td:85 |
| 361 | ATOMIC_CMP_SWAP_I64_POSTRA = 346, // Mips64InstrInfo.td:101 |
| 362 | ATOMIC_CMP_SWAP_I8 = 347, // MipsInstrInfo.td:1956 |
| 363 | ATOMIC_CMP_SWAP_I8_POSTRA = 348, // MipsInstrInfo.td:1997 |
| 364 | ATOMIC_LOAD_ADD_I16 = 349, // MipsInstrInfo.td:1934 |
| 365 | ATOMIC_LOAD_ADD_I16_POSTRA = 350, // MipsInstrInfo.td:1975 |
| 366 | ATOMIC_LOAD_ADD_I32 = 351, // MipsInstrInfo.td:1935 |
| 367 | ATOMIC_LOAD_ADD_I32_POSTRA = 352, // MipsInstrInfo.td:1976 |
| 368 | ATOMIC_LOAD_ADD_I64 = 353, // Mips64InstrInfo.td:78 |
| 369 | ATOMIC_LOAD_ADD_I64_POSTRA = 354, // Mips64InstrInfo.td:92 |
| 370 | ATOMIC_LOAD_ADD_I8 = 355, // MipsInstrInfo.td:1933 |
| 371 | ATOMIC_LOAD_ADD_I8_POSTRA = 356, // MipsInstrInfo.td:1974 |
| 372 | ATOMIC_LOAD_AND_I16 = 357, // MipsInstrInfo.td:1940 |
| 373 | ATOMIC_LOAD_AND_I16_POSTRA = 358, // MipsInstrInfo.td:1981 |
| 374 | ATOMIC_LOAD_AND_I32 = 359, // MipsInstrInfo.td:1941 |
| 375 | ATOMIC_LOAD_AND_I32_POSTRA = 360, // MipsInstrInfo.td:1982 |
| 376 | ATOMIC_LOAD_AND_I64 = 361, // Mips64InstrInfo.td:80 |
| 377 | ATOMIC_LOAD_AND_I64_POSTRA = 362, // Mips64InstrInfo.td:94 |
| 378 | ATOMIC_LOAD_AND_I8 = 363, // MipsInstrInfo.td:1939 |
| 379 | ATOMIC_LOAD_AND_I8_POSTRA = 364, // MipsInstrInfo.td:1980 |
| 380 | ATOMIC_LOAD_MAX_I16 = 365, // MipsInstrInfo.td:1964 |
| 381 | ATOMIC_LOAD_MAX_I16_POSTRA = 366, // MipsInstrInfo.td:2005 |
| 382 | ATOMIC_LOAD_MAX_I32 = 367, // MipsInstrInfo.td:1965 |
| 383 | ATOMIC_LOAD_MAX_I32_POSTRA = 368, // MipsInstrInfo.td:2006 |
| 384 | ATOMIC_LOAD_MAX_I64 = 369, // Mips64InstrInfo.td:87 |
| 385 | ATOMIC_LOAD_MAX_I64_POSTRA = 370, // Mips64InstrInfo.td:104 |
| 386 | ATOMIC_LOAD_MAX_I8 = 371, // MipsInstrInfo.td:1963 |
| 387 | ATOMIC_LOAD_MAX_I8_POSTRA = 372, // MipsInstrInfo.td:2004 |
| 388 | ATOMIC_LOAD_MIN_I16 = 373, // MipsInstrInfo.td:1961 |
| 389 | ATOMIC_LOAD_MIN_I16_POSTRA = 374, // MipsInstrInfo.td:2002 |
| 390 | ATOMIC_LOAD_MIN_I32 = 375, // MipsInstrInfo.td:1962 |
| 391 | ATOMIC_LOAD_MIN_I32_POSTRA = 376, // MipsInstrInfo.td:2003 |
| 392 | ATOMIC_LOAD_MIN_I64 = 377, // Mips64InstrInfo.td:86 |
| 393 | ATOMIC_LOAD_MIN_I64_POSTRA = 378, // Mips64InstrInfo.td:103 |
| 394 | ATOMIC_LOAD_MIN_I8 = 379, // MipsInstrInfo.td:1960 |
| 395 | ATOMIC_LOAD_MIN_I8_POSTRA = 380, // MipsInstrInfo.td:2001 |
| 396 | ATOMIC_LOAD_NAND_I16 = 381, // MipsInstrInfo.td:1949 |
| 397 | ATOMIC_LOAD_NAND_I16_POSTRA = 382, // MipsInstrInfo.td:1990 |
| 398 | ATOMIC_LOAD_NAND_I32 = 383, // MipsInstrInfo.td:1950 |
| 399 | ATOMIC_LOAD_NAND_I32_POSTRA = 384, // MipsInstrInfo.td:1991 |
| 400 | ATOMIC_LOAD_NAND_I64 = 385, // Mips64InstrInfo.td:83 |
| 401 | ATOMIC_LOAD_NAND_I64_POSTRA = 386, // Mips64InstrInfo.td:97 |
| 402 | ATOMIC_LOAD_NAND_I8 = 387, // MipsInstrInfo.td:1948 |
| 403 | ATOMIC_LOAD_NAND_I8_POSTRA = 388, // MipsInstrInfo.td:1989 |
| 404 | ATOMIC_LOAD_OR_I16 = 389, // MipsInstrInfo.td:1943 |
| 405 | ATOMIC_LOAD_OR_I16_POSTRA = 390, // MipsInstrInfo.td:1984 |
| 406 | ATOMIC_LOAD_OR_I32 = 391, // MipsInstrInfo.td:1944 |
| 407 | ATOMIC_LOAD_OR_I32_POSTRA = 392, // MipsInstrInfo.td:1985 |
| 408 | ATOMIC_LOAD_OR_I64 = 393, // Mips64InstrInfo.td:81 |
| 409 | ATOMIC_LOAD_OR_I64_POSTRA = 394, // Mips64InstrInfo.td:95 |
| 410 | ATOMIC_LOAD_OR_I8 = 395, // MipsInstrInfo.td:1942 |
| 411 | ATOMIC_LOAD_OR_I8_POSTRA = 396, // MipsInstrInfo.td:1983 |
| 412 | ATOMIC_LOAD_SUB_I16 = 397, // MipsInstrInfo.td:1937 |
| 413 | ATOMIC_LOAD_SUB_I16_POSTRA = 398, // MipsInstrInfo.td:1978 |
| 414 | ATOMIC_LOAD_SUB_I32 = 399, // MipsInstrInfo.td:1938 |
| 415 | ATOMIC_LOAD_SUB_I32_POSTRA = 400, // MipsInstrInfo.td:1979 |
| 416 | ATOMIC_LOAD_SUB_I64 = 401, // Mips64InstrInfo.td:79 |
| 417 | ATOMIC_LOAD_SUB_I64_POSTRA = 402, // Mips64InstrInfo.td:93 |
| 418 | ATOMIC_LOAD_SUB_I8 = 403, // MipsInstrInfo.td:1936 |
| 419 | ATOMIC_LOAD_SUB_I8_POSTRA = 404, // MipsInstrInfo.td:1977 |
| 420 | ATOMIC_LOAD_UMAX_I16 = 405, // MipsInstrInfo.td:1970 |
| 421 | ATOMIC_LOAD_UMAX_I16_POSTRA = 406, // MipsInstrInfo.td:2011 |
| 422 | ATOMIC_LOAD_UMAX_I32 = 407, // MipsInstrInfo.td:1971 |
| 423 | ATOMIC_LOAD_UMAX_I32_POSTRA = 408, // MipsInstrInfo.td:2012 |
| 424 | ATOMIC_LOAD_UMAX_I64 = 409, // Mips64InstrInfo.td:89 |
| 425 | ATOMIC_LOAD_UMAX_I64_POSTRA = 410, // Mips64InstrInfo.td:106 |
| 426 | ATOMIC_LOAD_UMAX_I8 = 411, // MipsInstrInfo.td:1969 |
| 427 | ATOMIC_LOAD_UMAX_I8_POSTRA = 412, // MipsInstrInfo.td:2010 |
| 428 | ATOMIC_LOAD_UMIN_I16 = 413, // MipsInstrInfo.td:1967 |
| 429 | ATOMIC_LOAD_UMIN_I16_POSTRA = 414, // MipsInstrInfo.td:2008 |
| 430 | ATOMIC_LOAD_UMIN_I32 = 415, // MipsInstrInfo.td:1968 |
| 431 | ATOMIC_LOAD_UMIN_I32_POSTRA = 416, // MipsInstrInfo.td:2009 |
| 432 | ATOMIC_LOAD_UMIN_I64 = 417, // Mips64InstrInfo.td:88 |
| 433 | ATOMIC_LOAD_UMIN_I64_POSTRA = 418, // Mips64InstrInfo.td:105 |
| 434 | ATOMIC_LOAD_UMIN_I8 = 419, // MipsInstrInfo.td:1966 |
| 435 | ATOMIC_LOAD_UMIN_I8_POSTRA = 420, // MipsInstrInfo.td:2007 |
| 436 | ATOMIC_LOAD_XOR_I16 = 421, // MipsInstrInfo.td:1946 |
| 437 | ATOMIC_LOAD_XOR_I16_POSTRA = 422, // MipsInstrInfo.td:1987 |
| 438 | ATOMIC_LOAD_XOR_I32 = 423, // MipsInstrInfo.td:1947 |
| 439 | ATOMIC_LOAD_XOR_I32_POSTRA = 424, // MipsInstrInfo.td:1988 |
| 440 | ATOMIC_LOAD_XOR_I64 = 425, // Mips64InstrInfo.td:82 |
| 441 | ATOMIC_LOAD_XOR_I64_POSTRA = 426, // Mips64InstrInfo.td:96 |
| 442 | ATOMIC_LOAD_XOR_I8 = 427, // MipsInstrInfo.td:1945 |
| 443 | ATOMIC_LOAD_XOR_I8_POSTRA = 428, // MipsInstrInfo.td:1986 |
| 444 | ATOMIC_SWAP_I16 = 429, // MipsInstrInfo.td:1953 |
| 445 | ATOMIC_SWAP_I16_POSTRA = 430, // MipsInstrInfo.td:1994 |
| 446 | ATOMIC_SWAP_I32 = 431, // MipsInstrInfo.td:1954 |
| 447 | ATOMIC_SWAP_I32_POSTRA = 432, // MipsInstrInfo.td:1995 |
| 448 | ATOMIC_SWAP_I64 = 433, // Mips64InstrInfo.td:84 |
| 449 | ATOMIC_SWAP_I64_POSTRA = 434, // Mips64InstrInfo.td:99 |
| 450 | ATOMIC_SWAP_I8 = 435, // MipsInstrInfo.td:1952 |
| 451 | ATOMIC_SWAP_I8_POSTRA = 436, // MipsInstrInfo.td:1993 |
| 452 | B = 437, // MipsInstrInfo.td:2295 |
| 453 | BAL_BR = 438, // MipsInstrInfo.td:2317 |
| 454 | BAL_BR_MM = 439, // MicroMipsInstrInfo.td:969 |
| 455 | BEQLImmMacro = 440, // MipsInstrInfo.td:3034 |
| 456 | BGE = 441, // MipsInstrInfo.td:3014 |
| 457 | BGEImmMacro = 442, // MipsInstrInfo.td:3039 |
| 458 | BGEL = 443, // MipsInstrInfo.td:3022 |
| 459 | BGELImmMacro = 444, // MipsInstrInfo.td:3047 |
| 460 | BGEU = 445, // MipsInstrInfo.td:3018 |
| 461 | BGEUImmMacro = 446, // MipsInstrInfo.td:3043 |
| 462 | BGEUL = 447, // MipsInstrInfo.td:3026 |
| 463 | BGEULImmMacro = 448, // MipsInstrInfo.td:3051 |
| 464 | BGT = 449, // MipsInstrInfo.td:3015 |
| 465 | BGTImmMacro = 450, // MipsInstrInfo.td:3040 |
| 466 | BGTL = 451, // MipsInstrInfo.td:3023 |
| 467 | BGTLImmMacro = 452, // MipsInstrInfo.td:3048 |
| 468 | BGTU = 453, // MipsInstrInfo.td:3019 |
| 469 | BGTUImmMacro = 454, // MipsInstrInfo.td:3044 |
| 470 | BGTUL = 455, // MipsInstrInfo.td:3027 |
| 471 | BGTULImmMacro = 456, // MipsInstrInfo.td:3052 |
| 472 | BLE = 457, // MipsInstrInfo.td:3013 |
| 473 | BLEImmMacro = 458, // MipsInstrInfo.td:3038 |
| 474 | BLEL = 459, // MipsInstrInfo.td:3021 |
| 475 | BLELImmMacro = 460, // MipsInstrInfo.td:3046 |
| 476 | BLEU = 461, // MipsInstrInfo.td:3017 |
| 477 | BLEUImmMacro = 462, // MipsInstrInfo.td:3042 |
| 478 | BLEUL = 463, // MipsInstrInfo.td:3025 |
| 479 | BLEULImmMacro = 464, // MipsInstrInfo.td:3050 |
| 480 | BLT = 465, // MipsInstrInfo.td:3012 |
| 481 | BLTImmMacro = 466, // MipsInstrInfo.td:3037 |
| 482 | BLTL = 467, // MipsInstrInfo.td:3020 |
| 483 | BLTLImmMacro = 468, // MipsInstrInfo.td:3045 |
| 484 | BLTU = 469, // MipsInstrInfo.td:3016 |
| 485 | BLTUImmMacro = 470, // MipsInstrInfo.td:3041 |
| 486 | BLTUL = 471, // MipsInstrInfo.td:3024 |
| 487 | BLTULImmMacro = 472, // MipsInstrInfo.td:3049 |
| 488 | BNELImmMacro = 473, // MipsInstrInfo.td:3035 |
| 489 | BPOSGE32_PSEUDO = 474, // MipsDSPInstrInfo.td:1083 |
| 490 | BSEL_D_PSEUDO = 475, // MipsMSAInstrInfo.td:2765 |
| 491 | BSEL_FD_PSEUDO = 476, // MipsMSAInstrInfo.td:2767 |
| 492 | BSEL_FW_PSEUDO = 477, // MipsMSAInstrInfo.td:2766 |
| 493 | BSEL_H_PSEUDO = 478, // MipsMSAInstrInfo.td:2763 |
| 494 | BSEL_W_PSEUDO = 479, // MipsMSAInstrInfo.td:2764 |
| 495 | B_MM = 480, // MicroMipsInstrInfo.td:979 |
| 496 | B_MMR6_Pseudo = 481, // MicroMips32r6InstrInfo.td:1587 |
| 497 | B_MM_Pseudo = 482, // MicroMipsInstrInfo.td:1297 |
| 498 | BeqImm = 483, // MipsInstrInfo.td:3002 |
| 499 | BneImm = 484, // MipsInstrInfo.td:2999 |
| 500 | BteqzT8CmpX16 = 485, // Mips16InstrInfo.td:622 |
| 501 | BteqzT8CmpiX16 = 486, // Mips16InstrInfo.td:624 |
| 502 | BteqzT8SltX16 = 487, // Mips16InstrInfo.td:627 |
| 503 | BteqzT8SltiX16 = 488, // Mips16InstrInfo.td:631 |
| 504 | BteqzT8SltiuX16 = 489, // Mips16InstrInfo.td:633 |
| 505 | BteqzT8SltuX16 = 490, // Mips16InstrInfo.td:629 |
| 506 | BtnezT8CmpX16 = 491, // Mips16InstrInfo.td:650 |
| 507 | BtnezT8CmpiX16 = 492, // Mips16InstrInfo.td:652 |
| 508 | BtnezT8SltX16 = 493, // Mips16InstrInfo.td:654 |
| 509 | BtnezT8SltiX16 = 494, // Mips16InstrInfo.td:658 |
| 510 | BtnezT8SltiuX16 = 495, // Mips16InstrInfo.td:660 |
| 511 | BtnezT8SltuX16 = 496, // Mips16InstrInfo.td:656 |
| 512 | BuildPairF64 = 497, // MipsInstrFPU.td:853 |
| 513 | BuildPairF64_64 = 498, // MipsInstrFPU.td:855 |
| 514 | BuildPairF64_FPR = 499, // MipsInstrFPU.td:854 |
| 515 | CFTC1 = 500, // MipsMTInstrInfo.td:138 |
| 516 | CONSTPOOL_ENTRY = 501, // Mips16InstrInfo.td:1885 |
| 517 | COPY_FD_PSEUDO = 502, // MipsMSAInstrInfo.td:2850 |
| 518 | COPY_FW_PSEUDO = 503, // MipsMSAInstrInfo.td:2849 |
| 519 | CTTC1 = 504, // MipsMTInstrInfo.td:167 |
| 520 | Constant32 = 505, // Mips16InstrInfo.td:459 |
| 521 | DMULImmMacro = 506, // Mips64InstrInfo.td:1135 |
| 522 | DMULMacro = 507, // Mips64InstrInfo.td:1151 |
| 523 | DMULOMacro = 508, // Mips64InstrInfo.td:1140 |
| 524 | DMULOUMacro = 509, // Mips64InstrInfo.td:1145 |
| 525 | DROL = 510, // MipsInstrInfo.td:2599 |
| 526 | DROLImm = 511, // MipsInstrInfo.td:2602 |
| 527 | DROR = 512, // MipsInstrInfo.td:2612 |
| 528 | DRORImm = 513, // MipsInstrInfo.td:2615 |
| 529 | DSDivIMacro = 514, // Mips64InstrInfo.td:1162 |
| 530 | DSDivMacro = 515, // Mips64InstrInfo.td:1158 |
| 531 | DSRemIMacro = 516, // Mips64InstrInfo.td:1204 |
| 532 | DSRemMacro = 517, // Mips64InstrInfo.td:1200 |
| 533 | DUDivIMacro = 518, // Mips64InstrInfo.td:1170 |
| 534 | DUDivMacro = 519, // Mips64InstrInfo.td:1166 |
| 535 | DURemIMacro = 520, // Mips64InstrInfo.td:1212 |
| 536 | DURemMacro = 521, // Mips64InstrInfo.td:1208 |
| 537 | ERet = 522, // MipsInstrInfo.td:1922 |
| 538 | ExtractElementF64 = 523, // MipsInstrFPU.td:867 |
| 539 | ExtractElementF64_64 = 524, // MipsInstrFPU.td:868 |
| 540 | FABS_D = 525, // MipsMSAInstrInfo.td:3465 |
| 541 | FABS_W = 526, // MipsMSAInstrInfo.td:3463 |
| 542 | FEXP2_D_1_PSEUDO = 527, // MipsMSAInstrInfo.td:2936 |
| 543 | FEXP2_W_1_PSEUDO = 528, // MipsMSAInstrInfo.td:2935 |
| 544 | FILL_FD_PSEUDO = 529, // MipsMSAInstrInfo.td:2961 |
| 545 | FILL_FW_PSEUDO = 530, // MipsMSAInstrInfo.td:2960 |
| 546 | GotPrologue16 = 531, // Mips16InstrInfo.td:1868 |
| 547 | INSERT_B_VIDX64_PSEUDO = 532, // MipsMSAInstrInfo.td:3127 |
| 548 | INSERT_B_VIDX_PSEUDO = 533, // MipsMSAInstrInfo.td:3120 |
| 549 | INSERT_D_VIDX64_PSEUDO = 534, // MipsMSAInstrInfo.td:3130 |
| 550 | INSERT_D_VIDX_PSEUDO = 535, // MipsMSAInstrInfo.td:3123 |
| 551 | INSERT_FD_PSEUDO = 536, // MipsMSAInstrInfo.td:3118 |
| 552 | INSERT_FD_VIDX64_PSEUDO = 537, // MipsMSAInstrInfo.td:3132 |
| 553 | INSERT_FD_VIDX_PSEUDO = 538, // MipsMSAInstrInfo.td:3125 |
| 554 | INSERT_FW_PSEUDO = 539, // MipsMSAInstrInfo.td:3117 |
| 555 | INSERT_FW_VIDX64_PSEUDO = 540, // MipsMSAInstrInfo.td:3131 |
| 556 | INSERT_FW_VIDX_PSEUDO = 541, // MipsMSAInstrInfo.td:3124 |
| 557 | INSERT_H_VIDX64_PSEUDO = 542, // MipsMSAInstrInfo.td:3128 |
| 558 | INSERT_H_VIDX_PSEUDO = 543, // MipsMSAInstrInfo.td:3121 |
| 559 | INSERT_W_VIDX64_PSEUDO = 544, // MipsMSAInstrInfo.td:3129 |
| 560 | INSERT_W_VIDX_PSEUDO = 545, // MipsMSAInstrInfo.td:3122 |
| 561 | JALR64Pseudo = 546, // Mips64InstrInfo.td:284 |
| 562 | JALRHB64Pseudo = 547, // Mips64InstrInfo.td:652 |
| 563 | JALRHBPseudo = 548, // MipsInstrInfo.td:2545 |
| 564 | JALRPseudo = 549, // MipsInstrInfo.td:2303 |
| 565 | JAL_MMR6 = 550, // MicroMips32r6InstrInfo.td:1724 |
| 566 | JalOneReg = 551, // MipsInstrInfo.td:2988 |
| 567 | JalTwoReg = 552, // MipsInstrInfo.td:2986 |
| 568 | LDMacro = 553, // MipsInstrInfo.td:3149 |
| 569 | LDR_D = 554, // MipsMSAInstrInfo.td:2214 |
| 570 | LDR_W = 555, // MipsMSAInstrInfo.td:2215 |
| 571 | LOAD_ACC128 = 556, // Mips64InstrInfo.td:110 |
| 572 | LOAD_ACC64 = 557, // MipsInstrInfo.td:2016 |
| 573 | LOAD_ACC64DSP = 558, // MipsDSPInstrInfo.td:1257 |
| 574 | LOAD_CCOND_DSP = 559, // MipsDSPInstrInfo.td:1261 |
| 575 | LONG_BRANCH_ADDiu = 560, // MipsInstrInfo.td:2036 |
| 576 | LONG_BRANCH_ADDiu2Op = 561, // MipsInstrInfo.td:2041 |
| 577 | LONG_BRANCH_DADDiu = 562, // Mips64InstrInfo.td:456 |
| 578 | LONG_BRANCH_DADDiu2Op = 563, // Mips64InstrInfo.td:448 |
| 579 | LONG_BRANCH_LUi = 564, // MipsInstrInfo.td:2025 |
| 580 | LONG_BRANCH_LUi2Op = 565, // MipsInstrInfo.td:2030 |
| 581 | LONG_BRANCH_LUi2Op_64 = 566, // Mips64InstrInfo.td:443 |
| 582 | LWM_MM = 567, // MicroMipsInstrInfo.td:869 |
| 583 | LoadAddrImm32 = 568, // MipsInstrInfo.td:2984 |
| 584 | LoadAddrImm64 = 569, // Mips64InstrInfo.td:1132 |
| 585 | LoadAddrReg32 = 570, // MipsInstrInfo.td:2979 |
| 586 | LoadAddrReg64 = 571, // Mips64InstrInfo.td:1130 |
| 587 | LoadImm32 = 572, // MipsInstrInfo.td:2973 |
| 588 | LoadImm64 = 573, // Mips64InstrInfo.td:1128 |
| 589 | LoadImmDoubleFGR = 574, // MipsInstrFPU.td:902 |
| 590 | LoadImmDoubleFGR_32 = 575, // MipsInstrFPU.td:897 |
| 591 | LoadImmDoubleGPR = 576, // MipsInstrFPU.td:893 |
| 592 | LoadImmSingleFGR = 577, // MipsInstrFPU.td:888 |
| 593 | LoadImmSingleGPR = 578, // MipsInstrFPU.td:884 |
| 594 | LwConstant32 = 579, // Mips16InstrInfo.td:461 |
| 595 | MFTACX = 580, // MipsMTInstrInfo.td:126 |
| 596 | MFTC0 = 581, // MipsMTInstrInfo.td:112 |
| 597 | MFTC1 = 582, // MipsMTInstrInfo.td:132 |
| 598 | MFTDSP = 583, // MipsMTInstrInfo.td:129 |
| 599 | MFTGPR = 584, // MipsMTInstrInfo.td:116 |
| 600 | MFTHC1 = 585, // MipsMTInstrInfo.td:135 |
| 601 | MFTHI = 586, // MipsMTInstrInfo.td:123 |
| 602 | MFTLO = 587, // MipsMTInstrInfo.td:120 |
| 603 | MIPSeh_return32 = 588, // MipsInstrInfo.td:2378 |
| 604 | MIPSeh_return64 = 589, // MipsInstrInfo.td:2380 |
| 605 | MTTACX = 590, // MipsMTInstrInfo.td:155 |
| 606 | MTTC0 = 591, // MipsMTInstrInfo.td:142 |
| 607 | MTTC1 = 592, // MipsMTInstrInfo.td:161 |
| 608 | MTTDSP = 593, // MipsMTInstrInfo.td:158 |
| 609 | MTTGPR = 594, // MipsMTInstrInfo.td:146 |
| 610 | MTTHC1 = 595, // MipsMTInstrInfo.td:164 |
| 611 | MTTHI = 596, // MipsMTInstrInfo.td:152 |
| 612 | MTTLO = 597, // MipsMTInstrInfo.td:149 |
| 613 | MULImmMacro = 598, // MipsInstrInfo.td:2660 |
| 614 | MULOMacro = 599, // MipsInstrInfo.td:2664 |
| 615 | MULOUMacro = 600, // MipsInstrInfo.td:2668 |
| 616 | MultRxRy16 = 601, // Mips16InstrInfo.td:876 |
| 617 | MultRxRyRz16 = 602, // Mips16InstrInfo.td:893 |
| 618 | MultuRxRy16 = 603, // Mips16InstrInfo.td:882 |
| 619 | MultuRxRyRz16 = 604, // Mips16InstrInfo.td:904 |
| 620 | NOP = 605, // MipsInstrInfo.td:2420 |
| 621 | NORImm = 606, // MipsInstrInfo.td:2994 |
| 622 | NORImm64 = 607, // Mips64InstrInfo.td:1234 |
| 623 | NOR_V_D_PSEUDO = 608, // MipsMSAInstrInfo.td:3261 |
| 624 | NOR_V_H_PSEUDO = 609, // MipsMSAInstrInfo.td:3253 |
| 625 | NOR_V_W_PSEUDO = 610, // MipsMSAInstrInfo.td:3257 |
| 626 | OR_V_D_PSEUDO = 611, // MipsMSAInstrInfo.td:3277 |
| 627 | OR_V_H_PSEUDO = 612, // MipsMSAInstrInfo.td:3269 |
| 628 | OR_V_W_PSEUDO = 613, // MipsMSAInstrInfo.td:3273 |
| 629 | PseudoCMPU_EQ_QB = 614, // MipsDSPInstrInfo.td:1285 |
| 630 | PseudoCMPU_LE_QB = 615, // MipsDSPInstrInfo.td:1287 |
| 631 | PseudoCMPU_LT_QB = 616, // MipsDSPInstrInfo.td:1286 |
| 632 | PseudoCMP_EQ_PH = 617, // MipsDSPInstrInfo.td:1282 |
| 633 | PseudoCMP_LE_PH = 618, // MipsDSPInstrInfo.td:1284 |
| 634 | PseudoCMP_LT_PH = 619, // MipsDSPInstrInfo.td:1283 |
| 635 | PseudoCVT_D32_W = 620, // MipsInstrFPU.td:569 |
| 636 | PseudoCVT_D64_L = 621, // MipsInstrFPU.td:572 |
| 637 | PseudoCVT_D64_W = 622, // MipsInstrFPU.td:571 |
| 638 | PseudoCVT_S_L = 623, // MipsInstrFPU.td:570 |
| 639 | PseudoCVT_S_W = 624, // MipsInstrFPU.td:567 |
| 640 | PseudoDMULT = 625, // Mips64InstrInfo.td:320 |
| 641 | PseudoDMULTu = 626, // Mips64InstrInfo.td:322 |
| 642 | PseudoDSDIV = 627, // Mips64InstrInfo.td:333 |
| 643 | PseudoDUDIV = 628, // Mips64InstrInfo.td:336 |
| 644 | PseudoD_SELECT_I = 629, // MipsCondMov.td:306 |
| 645 | PseudoD_SELECT_I64 = 630, // MipsCondMov.td:307 |
| 646 | PseudoIndirectBranch = 631, // MipsInstrInfo.td:2341 |
| 647 | PseudoIndirectBranch64 = 632, // Mips64InstrInfo.td:298 |
| 648 | PseudoIndirectBranch64R6 = 633, // Mips64r6InstrInfo.td:325 |
| 649 | PseudoIndirectBranchR6 = 634, // Mips32r6InstrInfo.td:1154 |
| 650 | PseudoIndirectBranch_MM = 635, // MicroMipsInstrInfo.td:1107 |
| 651 | PseudoIndirectBranch_MMR6 = 636, // MicroMips32r6InstrInfo.td:1735 |
| 652 | PseudoIndirectHazardBranch = 637, // MipsInstrInfo.td:2551 |
| 653 | PseudoIndirectHazardBranch64 = 638, // Mips64InstrInfo.td:306 |
| 654 | PseudoIndrectHazardBranch64R6 = 639, // Mips64r6InstrInfo.td:334 |
| 655 | PseudoIndrectHazardBranchR6 = 640, // Mips32r6InstrInfo.td:1162 |
| 656 | PseudoMADD = 641, // MipsInstrInfo.td:2450 |
| 657 | PseudoMADDU = 642, // MipsInstrInfo.td:2452 |
| 658 | PseudoMADDU_MM = 643, // MicroMipsInstrInfo.td:1093 |
| 659 | PseudoMADD_MM = 644, // MicroMipsInstrInfo.td:1091 |
| 660 | PseudoMFHI = 645, // MipsInstrInfo.td:2447 |
| 661 | PseudoMFHI64 = 646, // Mips64InstrInfo.td:349 |
| 662 | PseudoMFHI_MM = 647, // MicroMipsInstrInfo.td:1085 |
| 663 | PseudoMFLO = 648, // MipsInstrInfo.td:2448 |
| 664 | PseudoMFLO64 = 649, // Mips64InstrInfo.td:351 |
| 665 | PseudoMFLO_MM = 650, // MicroMipsInstrInfo.td:1087 |
| 666 | PseudoMSUB = 651, // MipsInstrInfo.td:2454 |
| 667 | PseudoMSUBU = 652, // MipsInstrInfo.td:2456 |
| 668 | PseudoMSUBU_MM = 653, // MicroMipsInstrInfo.td:1097 |
| 669 | PseudoMSUB_MM = 654, // MicroMipsInstrInfo.td:1095 |
| 670 | PseudoMTLOHI = 655, // MipsInstrInfo.td:2449 |
| 671 | PseudoMTLOHI64 = 656, // Mips64InstrInfo.td:353 |
| 672 | PseudoMTLOHI_DSP = 657, // MipsDSPInstrInfo.td:1293 |
| 673 | PseudoMTLOHI_MM = 658, // MicroMipsInstrInfo.td:1089 |
| 674 | PseudoMULT = 659, // MipsInstrInfo.td:2443 |
| 675 | PseudoMULT_MM = 660, // MicroMipsInstrInfo.td:1081 |
| 676 | PseudoMULTu = 661, // MipsInstrInfo.td:2445 |
| 677 | PseudoMULTu_MM = 662, // MicroMipsInstrInfo.td:1083 |
| 678 | PseudoPICK_PH = 663, // MipsDSPInstrInfo.td:1289 |
| 679 | PseudoPICK_QB = 664, // MipsDSPInstrInfo.td:1290 |
| 680 | PseudoReturn = 665, // MipsInstrInfo.td:2360 |
| 681 | PseudoReturn64 = 666, // Mips64InstrInfo.td:292 |
| 682 | PseudoSDIV = 667, // MipsInstrInfo.td:2461 |
| 683 | PseudoSELECTFP_F_D32 = 668, // MipsCondMov.td:296 |
| 684 | PseudoSELECTFP_F_D64 = 669, // MipsCondMov.td:297 |
| 685 | PseudoSELECTFP_F_I = 670, // MipsCondMov.td:293 |
| 686 | PseudoSELECTFP_F_I64 = 671, // MipsCondMov.td:294 |
| 687 | PseudoSELECTFP_F_S = 672, // MipsCondMov.td:295 |
| 688 | PseudoSELECTFP_T_D32 = 673, // MipsCondMov.td:290 |
| 689 | PseudoSELECTFP_T_D64 = 674, // MipsCondMov.td:291 |
| 690 | PseudoSELECTFP_T_I = 675, // MipsCondMov.td:287 |
| 691 | PseudoSELECTFP_T_I64 = 676, // MipsCondMov.td:288 |
| 692 | PseudoSELECTFP_T_S = 677, // MipsCondMov.td:289 |
| 693 | PseudoSELECT_D32 = 678, // MipsCondMov.td:284 |
| 694 | PseudoSELECT_D64 = 679, // MipsCondMov.td:285 |
| 695 | PseudoSELECT_I = 680, // MipsCondMov.td:281 |
| 696 | PseudoSELECT_I64 = 681, // MipsCondMov.td:282 |
| 697 | PseudoSELECT_S = 682, // MipsCondMov.td:283 |
| 698 | PseudoTRUNC_W_D = 683, // MipsInstrFPU.td:879 |
| 699 | PseudoTRUNC_W_D32 = 684, // MipsInstrFPU.td:874 |
| 700 | PseudoTRUNC_W_S = 685, // MipsInstrFPU.td:870 |
| 701 | PseudoUDIV = 686, // MipsInstrInfo.td:2463 |
| 702 | ROL = 687, // MipsInstrInfo.td:2577 |
| 703 | ROLImm = 688, // MipsInstrInfo.td:2580 |
| 704 | ROR = 689, // MipsInstrInfo.td:2588 |
| 705 | RORImm = 690, // MipsInstrInfo.td:2591 |
| 706 | RetRA = 691, // MipsInstrInfo.td:1919 |
| 707 | RetRA16 = 692, // Mips16InstrInfo.td:1369 |
| 708 | SDC1_M1 = 693, // MipsInstrFPU.td:907 |
| 709 | SDIV_MM_Pseudo = 694, // MicroMipsInstrInfo.td:1306 |
| 710 | SDMacro = 695, // MipsInstrInfo.td:3152 |
| 711 | SDivIMacro = 696, // MipsInstrInfo.td:3064 |
| 712 | SDivMacro = 697, // MipsInstrInfo.td:3060 |
| 713 | SEQIMacro = 698, // MipsInstrInfo.td:2636 |
| 714 | SEQMacro = 699, // MipsInstrInfo.td:2628 |
| 715 | SGE = 700, // MipsInstrInfo.td:2752 |
| 716 | SGEImm = 701, // MipsInstrInfo.td:2758 |
| 717 | SGEImm64 = 702, // Mips64InstrInfo.td:1248 |
| 718 | SGEU = 703, // MipsInstrInfo.td:2766 |
| 719 | SGEUImm = 704, // MipsInstrInfo.td:2772 |
| 720 | SGEUImm64 = 705, // Mips64InstrInfo.td:1255 |
| 721 | SGTImm = 706, // MipsInstrInfo.td:2787 |
| 722 | SGTImm64 = 707, // Mips64InstrInfo.td:1262 |
| 723 | SGTUImm = 708, // MipsInstrInfo.td:2801 |
| 724 | SGTUImm64 = 709, // Mips64InstrInfo.td:1269 |
| 725 | SLE = 710, // MipsInstrInfo.td:2809 |
| 726 | SLEImm = 711, // MipsInstrInfo.td:2815 |
| 727 | SLEImm64 = 712, // Mips64InstrInfo.td:1276 |
| 728 | SLEU = 713, // MipsInstrInfo.td:2823 |
| 729 | SLEUImm = 714, // MipsInstrInfo.td:2829 |
| 730 | SLEUImm64 = 715, // Mips64InstrInfo.td:1283 |
| 731 | SLTImm64 = 716, // Mips64InstrInfo.td:1237 |
| 732 | SLTUImm64 = 717, // Mips64InstrInfo.td:1242 |
| 733 | SNEIMacro = 718, // MipsInstrInfo.td:2652 |
| 734 | SNEMacro = 719, // MipsInstrInfo.td:2644 |
| 735 | SNZ_B_PSEUDO = 720, // MipsMSAInstrInfo.td:3632 |
| 736 | SNZ_D_PSEUDO = 721, // MipsMSAInstrInfo.td:3638 |
| 737 | SNZ_H_PSEUDO = 722, // MipsMSAInstrInfo.td:3634 |
| 738 | SNZ_V_PSEUDO = 723, // MipsMSAInstrInfo.td:3640 |
| 739 | SNZ_W_PSEUDO = 724, // MipsMSAInstrInfo.td:3636 |
| 740 | SRemIMacro = 725, // MipsInstrInfo.td:3108 |
| 741 | SRemMacro = 726, // MipsInstrInfo.td:3104 |
| 742 | STORE_ACC128 = 727, // Mips64InstrInfo.td:111 |
| 743 | STORE_ACC64 = 728, // MipsInstrInfo.td:2017 |
| 744 | STORE_ACC64DSP = 729, // MipsDSPInstrInfo.td:1258 |
| 745 | STORE_CCOND_DSP = 730, // MipsDSPInstrInfo.td:1262 |
| 746 | STR_D = 731, // MipsMSAInstrInfo.td:2551 |
| 747 | STR_W = 732, // MipsMSAInstrInfo.td:2552 |
| 748 | SWM_MM = 733, // MicroMipsInstrInfo.td:868 |
| 749 | SZ_B_PSEUDO = 734, // MipsMSAInstrInfo.td:3643 |
| 750 | SZ_D_PSEUDO = 735, // MipsMSAInstrInfo.td:3646 |
| 751 | SZ_H_PSEUDO = 736, // MipsMSAInstrInfo.td:3644 |
| 752 | SZ_V_PSEUDO = 737, // MipsMSAInstrInfo.td:3647 |
| 753 | SZ_W_PSEUDO = 738, // MipsMSAInstrInfo.td:3645 |
| 754 | SaaAddr = 739, // Mips64InstrInfo.td:623 |
| 755 | SaadAddr = 740, // Mips64InstrInfo.td:625 |
| 756 | SelBeqZ = 741, // Mips16InstrInfo.td:1013 |
| 757 | SelBneZ = 742, // Mips16InstrInfo.td:1068 |
| 758 | SelTBteqZCmp = 743, // Mips16InstrInfo.td:1021 |
| 759 | SelTBteqZCmpi = 744, // Mips16InstrInfo.td:1029 |
| 760 | SelTBteqZSlt = 745, // Mips16InstrInfo.td:1037 |
| 761 | SelTBteqZSlti = 746, // Mips16InstrInfo.td:1045 |
| 762 | SelTBteqZSltiu = 747, // Mips16InstrInfo.td:1061 |
| 763 | SelTBteqZSltu = 748, // Mips16InstrInfo.td:1053 |
| 764 | SelTBtneZCmp = 749, // Mips16InstrInfo.td:1076 |
| 765 | SelTBtneZCmpi = 750, // Mips16InstrInfo.td:1084 |
| 766 | SelTBtneZSlt = 751, // Mips16InstrInfo.td:1092 |
| 767 | SelTBtneZSlti = 752, // Mips16InstrInfo.td:1100 |
| 768 | SelTBtneZSltiu = 753, // Mips16InstrInfo.td:1116 |
| 769 | SelTBtneZSltu = 754, // Mips16InstrInfo.td:1108 |
| 770 | SltCCRxRy16 = 755, // Mips16InstrInfo.td:1196 |
| 771 | SltiCCRxImmX16 = 756, // Mips16InstrInfo.td:1160 |
| 772 | SltiuCCRxImmX16 = 757, // Mips16InstrInfo.td:1185 |
| 773 | SltuCCRxRy16 = 758, // Mips16InstrInfo.td:1212 |
| 774 | SltuRxRyRz16 = 759, // Mips16InstrInfo.td:1206 |
| 775 | TAILCALL = 760, // MipsInstrInfo.td:2320 |
| 776 | TAILCALL64R6REG = 761, // Mips64r6InstrInfo.td:324 |
| 777 | TAILCALLHB64R6REG = 762, // Mips64r6InstrInfo.td:332 |
| 778 | TAILCALLHBR6REG = 763, // Mips32r6InstrInfo.td:1161 |
| 779 | TAILCALLR6REG = 764, // Mips32r6InstrInfo.td:1153 |
| 780 | TAILCALLREG = 765, // MipsInstrInfo.td:2324 |
| 781 | TAILCALLREG64 = 766, // Mips64InstrInfo.td:296 |
| 782 | TAILCALLREGHB = 767, // MipsInstrInfo.td:2550 |
| 783 | TAILCALLREGHB64 = 768, // Mips64InstrInfo.td:304 |
| 784 | TAILCALLREG_MM = 769, // MicroMipsInstrInfo.td:1104 |
| 785 | TAILCALLREG_MMR6 = 770, // MicroMips32r6InstrInfo.td:1733 |
| 786 | TAILCALL_MM = 771, // MicroMipsInstrInfo.td:1101 |
| 787 | TAILCALL_MMR6 = 772, // MicroMips32r6InstrInfo.td:1731 |
| 788 | TRAP = 773, // MipsInstrInfo.td:2235 |
| 789 | TRAP_MM = 774, // MicroMipsInstrInfo.td:999 |
| 790 | UDIV_MM_Pseudo = 775, // MicroMipsInstrInfo.td:1308 |
| 791 | UDivIMacro = 776, // MipsInstrInfo.td:3072 |
| 792 | UDivMacro = 777, // MipsInstrInfo.td:3068 |
| 793 | URemIMacro = 778, // MipsInstrInfo.td:3116 |
| 794 | URemMacro = 779, // MipsInstrInfo.td:3112 |
| 795 | Ulh = 780, // MipsInstrInfo.td:3134 |
| 796 | Ulhu = 781, // MipsInstrInfo.td:3137 |
| 797 | Ulw = 782, // MipsInstrInfo.td:3140 |
| 798 | Ush = 783, // MipsInstrInfo.td:3143 |
| 799 | Usw = 784, // MipsInstrInfo.td:3146 |
| 800 | XOR_V_D_PSEUDO = 785, // MipsMSAInstrInfo.td:3432 |
| 801 | XOR_V_H_PSEUDO = 786, // MipsMSAInstrInfo.td:3424 |
| 802 | XOR_V_W_PSEUDO = 787, // MipsMSAInstrInfo.td:3428 |
| 803 | ABSQ_S_PH = 788, // MipsDSPInstrInfo.td:1102 |
| 804 | ABSQ_S_PH_MM = 789, // MicroMipsDSPInstrInfo.td:410 |
| 805 | ABSQ_S_QB = 790, // MipsDSPInstrInfo.td:1214 |
| 806 | ABSQ_S_QB_MMR2 = 791, // MicroMipsDSPInstrInfo.td:516 |
| 807 | ABSQ_S_W = 792, // MipsDSPInstrInfo.td:1103 |
| 808 | ABSQ_S_W_MM = 793, // MicroMipsDSPInstrInfo.td:411 |
| 809 | ADD = 794, // MipsInstrInfo.td:2088 |
| 810 | ADDIUPC = 795, // Mips32r6InstrInfo.td:818 |
| 811 | ADDIUPC_MM = 796, // MicroMipsInstrInfo.td:759 |
| 812 | ADDIUPC_MMR6 = 797, // MicroMips32r6InstrInfo.td:1262 |
| 813 | ADDIUR1SP_MM = 798, // MicroMipsInstrInfo.td:641 |
| 814 | ADDIUR2_MM = 799, // MicroMipsInstrInfo.td:643 |
| 815 | ADDIUS5_MM = 800, // MicroMipsInstrInfo.td:645 |
| 816 | ADDIUSP_MM = 801, // MicroMipsInstrInfo.td:647 |
| 817 | ADDIU_MMR6 = 802, // MicroMips32r6InstrInfo.td:1260 |
| 818 | ADDQH_PH = 803, // MipsDSPInstrInfo.td:1219 |
| 819 | ADDQH_PH_MMR2 = 804, // MicroMipsDSPInstrInfo.td:518 |
| 820 | ADDQH_R_PH = 805, // MipsDSPInstrInfo.td:1220 |
| 821 | ADDQH_R_PH_MMR2 = 806, // MicroMipsDSPInstrInfo.td:519 |
| 822 | ADDQH_R_W = 807, // MipsDSPInstrInfo.td:1224 |
| 823 | ADDQH_R_W_MMR2 = 808, // MicroMipsDSPInstrInfo.td:521 |
| 824 | ADDQH_W = 809, // MipsDSPInstrInfo.td:1223 |
| 825 | ADDQH_W_MMR2 = 810, // MicroMipsDSPInstrInfo.td:520 |
| 826 | ADDQ_PH = 811, // MipsDSPInstrInfo.td:1092 |
| 827 | ADDQ_PH_MM = 812, // MicroMipsDSPInstrInfo.td:399 |
| 828 | ADDQ_S_PH = 813, // MipsDSPInstrInfo.td:1093 |
| 829 | ADDQ_S_PH_MM = 814, // MicroMipsDSPInstrInfo.td:400 |
| 830 | ADDQ_S_W = 815, // MipsDSPInstrInfo.td:1096 |
| 831 | ADDQ_S_W_MM = 816, // MicroMipsDSPInstrInfo.td:401 |
| 832 | ADDR_PS64 = 817, // MipsInstrFPU.td:538 |
| 833 | ADDSC = 818, // MipsDSPInstrInfo.td:1098 |
| 834 | ADDSC_MM = 819, // MicroMipsDSPInstrInfo.td:404 |
| 835 | ADDS_A_B = 820, // MipsMSAInstrInfo.td:2623 |
| 836 | ADDS_A_D = 821, // MipsMSAInstrInfo.td:2626 |
| 837 | ADDS_A_H = 822, // MipsMSAInstrInfo.td:2624 |
| 838 | ADDS_A_W = 823, // MipsMSAInstrInfo.td:2625 |
| 839 | ADDS_S_B = 824, // MipsMSAInstrInfo.td:2628 |
| 840 | ADDS_S_D = 825, // MipsMSAInstrInfo.td:2631 |
| 841 | ADDS_S_H = 826, // MipsMSAInstrInfo.td:2629 |
| 842 | ADDS_S_W = 827, // MipsMSAInstrInfo.td:2630 |
| 843 | ADDS_U_B = 828, // MipsMSAInstrInfo.td:2633 |
| 844 | ADDS_U_D = 829, // MipsMSAInstrInfo.td:2636 |
| 845 | ADDS_U_H = 830, // MipsMSAInstrInfo.td:2634 |
| 846 | ADDS_U_W = 831, // MipsMSAInstrInfo.td:2635 |
| 847 | ADDU16_MM = 832, // MicroMipsInstrInfo.td:596 |
| 848 | ADDU16_MMR6 = 833, // MicroMips32r6InstrInfo.td:1458 |
| 849 | ADDUH_QB = 834, // MipsDSPInstrInfo.td:1215 |
| 850 | ADDUH_QB_MMR2 = 835, // MicroMipsDSPInstrInfo.td:524 |
| 851 | ADDUH_R_QB = 836, // MipsDSPInstrInfo.td:1216 |
| 852 | ADDUH_R_QB_MMR2 = 837, // MicroMipsDSPInstrInfo.td:525 |
| 853 | ADDU_MMR6 = 838, // MicroMips32r6InstrInfo.td:1261 |
| 854 | ADDU_PH = 839, // MipsDSPInstrInfo.td:1207 |
| 855 | ADDU_PH_MMR2 = 840, // MicroMipsDSPInstrInfo.td:522 |
| 856 | ADDU_QB = 841, // MipsDSPInstrInfo.td:1088 |
| 857 | ADDU_QB_MM = 842, // MicroMipsDSPInstrInfo.td:402 |
| 858 | ADDU_S_PH = 843, // MipsDSPInstrInfo.td:1208 |
| 859 | ADDU_S_PH_MMR2 = 844, // MicroMipsDSPInstrInfo.td:523 |
| 860 | ADDU_S_QB = 845, // MipsDSPInstrInfo.td:1089 |
| 861 | ADDU_S_QB_MM = 846, // MicroMipsDSPInstrInfo.td:403 |
| 862 | ADDVI_B = 847, // MipsMSAInstrInfo.td:2643 |
| 863 | ADDVI_D = 848, // MipsMSAInstrInfo.td:2646 |
| 864 | ADDVI_H = 849, // MipsMSAInstrInfo.td:2644 |
| 865 | ADDVI_W = 850, // MipsMSAInstrInfo.td:2645 |
| 866 | ADDV_B = 851, // MipsMSAInstrInfo.td:2638 |
| 867 | ADDV_D = 852, // MipsMSAInstrInfo.td:2641 |
| 868 | ADDV_H = 853, // MipsMSAInstrInfo.td:2639 |
| 869 | ADDV_W = 854, // MipsMSAInstrInfo.td:2640 |
| 870 | ADDWC = 855, // MipsDSPInstrInfo.td:1099 |
| 871 | ADDWC_MM = 856, // MicroMipsDSPInstrInfo.td:405 |
| 872 | ADD_A_B = 857, // MipsMSAInstrInfo.td:2618 |
| 873 | ADD_A_D = 858, // MipsMSAInstrInfo.td:2621 |
| 874 | ADD_A_H = 859, // MipsMSAInstrInfo.td:2619 |
| 875 | ADD_A_W = 860, // MipsMSAInstrInfo.td:2620 |
| 876 | ADD_MM = 861, // MicroMipsInstrInfo.td:733 |
| 877 | ADD_MMR6 = 862, // MicroMips32r6InstrInfo.td:1259 |
| 878 | ADDi = 863, // MipsInstrInfo.td:2068 |
| 879 | ADDi_MM = 864, // MicroMipsInstrInfo.td:705 |
| 880 | ADDiu = 865, // MipsInstrInfo.td:2055 |
| 881 | ADDiu_MM = 866, // MicroMipsInstrInfo.td:703 |
| 882 | ADDu = 867, // MipsInstrInfo.td:2079 |
| 883 | ADDu_MM = 868, // MicroMipsInstrInfo.td:726 |
| 884 | ALIGN = 869, // Mips32r6InstrInfo.td:819 |
| 885 | ALIGN_MMR6 = 870, // MicroMips32r6InstrInfo.td:1269 |
| 886 | ALUIPC = 871, // Mips32r6InstrInfo.td:820 |
| 887 | ALUIPC_MMR6 = 872, // MicroMips32r6InstrInfo.td:1264 |
| 888 | AND = 873, // MipsInstrInfo.td:2097 |
| 889 | AND16_MM = 874, // MicroMipsInstrInfo.td:598 |
| 890 | AND16_MMR6 = 875, // MicroMips32r6InstrInfo.td:1460 |
| 891 | AND64 = 876, // Mips64InstrInfo.td:156 |
| 892 | ANDI16_MM = 877, // MicroMipsInstrInfo.td:602 |
| 893 | ANDI16_MMR6 = 878, // MicroMips32r6InstrInfo.td:1462 |
| 894 | ANDI_B = 879, // MipsMSAInstrInfo.td:2662 |
| 895 | ANDI_MMR6 = 880, // MicroMips32r6InstrInfo.td:1267 |
| 896 | AND_MM = 881, // MicroMipsInstrInfo.td:741 |
| 897 | AND_MMR6 = 882, // MicroMips32r6InstrInfo.td:1266 |
| 898 | AND_V = 883, // MipsMSAInstrInfo.td:2648 |
| 899 | ANDi = 884, // MipsInstrInfo.td:2059 |
| 900 | ANDi64 = 885, // Mips64InstrInfo.td:132 |
| 901 | ANDi_MM = 886, // MicroMipsInstrInfo.td:711 |
| 902 | APPEND = 887, // MipsDSPInstrInfo.td:1250 |
| 903 | APPEND_MMR2 = 888, // MicroMipsDSPInstrInfo.td:576 |
| 904 | ASUB_S_B = 889, // MipsMSAInstrInfo.td:2664 |
| 905 | ASUB_S_D = 890, // MipsMSAInstrInfo.td:2667 |
| 906 | ASUB_S_H = 891, // MipsMSAInstrInfo.td:2665 |
| 907 | ASUB_S_W = 892, // MipsMSAInstrInfo.td:2666 |
| 908 | ASUB_U_B = 893, // MipsMSAInstrInfo.td:2669 |
| 909 | ASUB_U_D = 894, // MipsMSAInstrInfo.td:2672 |
| 910 | ASUB_U_H = 895, // MipsMSAInstrInfo.td:2670 |
| 911 | ASUB_U_W = 896, // MipsMSAInstrInfo.td:2671 |
| 912 | AUI = 897, // Mips32r6InstrInfo.td:821 |
| 913 | AUIPC = 898, // Mips32r6InstrInfo.td:822 |
| 914 | AUIPC_MMR6 = 899, // MicroMips32r6InstrInfo.td:1268 |
| 915 | AUI_MMR6 = 900, // MicroMips32r6InstrInfo.td:1270 |
| 916 | AVER_S_B = 901, // MipsMSAInstrInfo.td:2684 |
| 917 | AVER_S_D = 902, // MipsMSAInstrInfo.td:2687 |
| 918 | AVER_S_H = 903, // MipsMSAInstrInfo.td:2685 |
| 919 | AVER_S_W = 904, // MipsMSAInstrInfo.td:2686 |
| 920 | AVER_U_B = 905, // MipsMSAInstrInfo.td:2689 |
| 921 | AVER_U_D = 906, // MipsMSAInstrInfo.td:2692 |
| 922 | AVER_U_H = 907, // MipsMSAInstrInfo.td:2690 |
| 923 | AVER_U_W = 908, // MipsMSAInstrInfo.td:2691 |
| 924 | AVE_S_B = 909, // MipsMSAInstrInfo.td:2674 |
| 925 | AVE_S_D = 910, // MipsMSAInstrInfo.td:2677 |
| 926 | AVE_S_H = 911, // MipsMSAInstrInfo.td:2675 |
| 927 | AVE_S_W = 912, // MipsMSAInstrInfo.td:2676 |
| 928 | AVE_U_B = 913, // MipsMSAInstrInfo.td:2679 |
| 929 | AVE_U_D = 914, // MipsMSAInstrInfo.td:2682 |
| 930 | AVE_U_H = 915, // MipsMSAInstrInfo.td:2680 |
| 931 | AVE_U_W = 916, // MipsMSAInstrInfo.td:2681 |
| 932 | AddiuRxImmX16 = 917, // Mips16InstrInfo.td:502 |
| 933 | AddiuRxPcImmX16 = 918, // Mips16InstrInfo.td:523 |
| 934 | AddiuRxRxImm16 = 919, // Mips16InstrInfo.td:504 |
| 935 | AddiuRxRxImmX16 = 920, // Mips16InstrInfo.td:508 |
| 936 | AddiuRxRyOffMemX16 = 921, // Mips16InstrInfo.td:514 |
| 937 | AddiuSpImm16 = 922, // Mips16InstrInfo.td:530 |
| 938 | AddiuSpImmX16 = 923, // Mips16InstrInfo.td:537 |
| 939 | AdduRxRyRz16 = 924, // Mips16InstrInfo.td:549 |
| 940 | AndRxRxRy16 = 925, // Mips16InstrInfo.td:556 |
| 941 | B16_MM = 926, // MicroMipsInstrInfo.td:673 |
| 942 | BADDu = 927, // Mips64InstrInfo.td:518 |
| 943 | BAL = 928, // Mips32r6InstrInfo.td:823 |
| 944 | BALC = 929, // Mips32r6InstrInfo.td:824 |
| 945 | BALC_MMR6 = 930, // MicroMips32r6InstrInfo.td:1271 |
| 946 | BALIGN = 931, // MipsDSPInstrInfo.td:1251 |
| 947 | BALIGN_MMR2 = 932, // MicroMipsDSPInstrInfo.td:538 |
| 948 | BBIT0 = 933, // Mips64InstrInfo.td:525 |
| 949 | BBIT032 = 934, // Mips64InstrInfo.td:527 |
| 950 | BBIT1 = 935, // Mips64InstrInfo.td:531 |
| 951 | BBIT132 = 936, // Mips64InstrInfo.td:533 |
| 952 | BC = 937, // Mips32r6InstrInfo.td:832 |
| 953 | BC16_MMR6 = 938, // MicroMips32r6InstrInfo.td:1273 |
| 954 | BC1EQZ = 939, // Mips32r6InstrInfo.td:828 |
| 955 | BC1EQZC_MMR6 = 940, // MicroMips32r6InstrInfo.td:1529 |
| 956 | BC1F = 941, // MipsInstrFPU.td:804 |
| 957 | BC1FL = 942, // MipsInstrFPU.td:806 |
| 958 | BC1F_MM = 943, // MicroMipsInstrFPU.td:76 |
| 959 | BC1NEZ = 944, // Mips32r6InstrInfo.td:829 |
| 960 | BC1NEZC_MMR6 = 945, // MicroMips32r6InstrInfo.td:1531 |
| 961 | BC1T = 946, // MipsInstrFPU.td:808 |
| 962 | BC1TL = 947, // MipsInstrFPU.td:810 |
| 963 | BC1T_MM = 948, // MicroMipsInstrFPU.td:78 |
| 964 | BC2EQZ = 949, // Mips32r6InstrInfo.td:830 |
| 965 | BC2EQZC_MMR6 = 950, // MicroMips32r6InstrInfo.td:1533 |
| 966 | BC2NEZ = 951, // Mips32r6InstrInfo.td:831 |
| 967 | BC2NEZC_MMR6 = 952, // MicroMips32r6InstrInfo.td:1535 |
| 968 | BCLRI_B = 953, // MipsMSAInstrInfo.td:2699 |
| 969 | BCLRI_D = 954, // MipsMSAInstrInfo.td:2702 |
| 970 | BCLRI_H = 955, // MipsMSAInstrInfo.td:2700 |
| 971 | BCLRI_W = 956, // MipsMSAInstrInfo.td:2701 |
| 972 | BCLR_B = 957, // MipsMSAInstrInfo.td:2694 |
| 973 | BCLR_D = 958, // MipsMSAInstrInfo.td:2697 |
| 974 | BCLR_H = 959, // MipsMSAInstrInfo.td:2695 |
| 975 | BCLR_W = 960, // MipsMSAInstrInfo.td:2696 |
| 976 | BC_MMR6 = 961, // MicroMips32r6InstrInfo.td:1272 |
| 977 | BEQ = 962, // MipsInstrInfo.td:2271 |
| 978 | BEQ64 = 963, // Mips64InstrInfo.td:271 |
| 979 | BEQC = 964, // Mips32r6InstrInfo.td:833 |
| 980 | BEQC64 = 965, // Mips64r6InstrInfo.td:168 |
| 981 | BEQC_MMR6 = 966, // MicroMips32r6InstrInfo.td:1561 |
| 982 | BEQL = 967, // MipsInstrInfo.td:2273 |
| 983 | BEQZ16_MM = 968, // MicroMipsInstrInfo.td:669 |
| 984 | BEQZALC = 969, // Mips32r6InstrInfo.td:834 |
| 985 | BEQZALC_MMR6 = 970, // MicroMips32r6InstrInfo.td:1284 |
| 986 | BEQZC = 971, // Mips32r6InstrInfo.td:835 |
| 987 | BEQZC16_MMR6 = 972, // MicroMips32r6InstrInfo.td:1276 |
| 988 | BEQZC64 = 973, // Mips64r6InstrInfo.td:169 |
| 989 | BEQZC_MM = 974, // MicroMipsInstrInfo.td:697 |
| 990 | BEQZC_MMR6 = 975, // MicroMips32r6InstrInfo.td:1274 |
| 991 | BEQ_MM = 976, // MicroMipsInstrInfo.td:953 |
| 992 | BGEC = 977, // Mips32r6InstrInfo.td:836 |
| 993 | BGEC64 = 978, // Mips64r6InstrInfo.td:170 |
| 994 | BGEC_MMR6 = 979, // MicroMips32r6InstrInfo.td:1557 |
| 995 | BGEUC = 980, // Mips32r6InstrInfo.td:837 |
| 996 | BGEUC64 = 981, // Mips64r6InstrInfo.td:171 |
| 997 | BGEUC_MMR6 = 982, // MicroMips32r6InstrInfo.td:1558 |
| 998 | BGEZ = 983, // MipsInstrInfo.td:2279 |
| 999 | BGEZ64 = 984, // Mips64InstrInfo.td:275 |
| 1000 | BGEZAL = 985, // MipsInstrInfo.td:2309 |
| 1001 | BGEZALC = 986, // Mips32r6InstrInfo.td:838 |
| 1002 | BGEZALC_MMR6 = 987, // MicroMips32r6InstrInfo.td:1569 |
| 1003 | BGEZALL = 988, // MipsInstrInfo.td:2311 |
| 1004 | BGEZALS_MM = 989, // MicroMipsInstrInfo.td:973 |
| 1005 | BGEZAL_MM = 990, // MicroMipsInstrInfo.td:965 |
| 1006 | BGEZC = 991, // Mips32r6InstrInfo.td:839 |
| 1007 | BGEZC64 = 992, // Mips64r6InstrInfo.td:181 |
| 1008 | BGEZC_MMR6 = 993, // MicroMips32r6InstrInfo.td:1567 |
| 1009 | BGEZL = 994, // MipsInstrInfo.td:2281 |
| 1010 | BGEZ_MM = 995, // MicroMipsInstrInfo.td:957 |
| 1011 | BGTZ = 996, // MipsInstrInfo.td:2283 |
| 1012 | BGTZ64 = 997, // Mips64InstrInfo.td:277 |
| 1013 | BGTZALC = 998, // Mips32r6InstrInfo.td:840 |
| 1014 | BGTZALC_MMR6 = 999, // MicroMips32r6InstrInfo.td:1571 |
| 1015 | BGTZC = 1000, // Mips32r6InstrInfo.td:841 |
| 1016 | BGTZC64 = 1001, // Mips64r6InstrInfo.td:172 |
| 1017 | BGTZC_MMR6 = 1002, // MicroMips32r6InstrInfo.td:1568 |
| 1018 | BGTZL = 1003, // MipsInstrInfo.td:2285 |
| 1019 | BGTZ_MM = 1004, // MicroMipsInstrInfo.td:959 |
| 1020 | BINSLI_B = 1005, // MipsMSAInstrInfo.td:2709 |
| 1021 | BINSLI_D = 1006, // MipsMSAInstrInfo.td:2712 |
| 1022 | BINSLI_H = 1007, // MipsMSAInstrInfo.td:2710 |
| 1023 | BINSLI_W = 1008, // MipsMSAInstrInfo.td:2711 |
| 1024 | BINSL_B = 1009, // MipsMSAInstrInfo.td:2704 |
| 1025 | BINSL_D = 1010, // MipsMSAInstrInfo.td:2707 |
| 1026 | BINSL_H = 1011, // MipsMSAInstrInfo.td:2705 |
| 1027 | BINSL_W = 1012, // MipsMSAInstrInfo.td:2706 |
| 1028 | BINSRI_B = 1013, // MipsMSAInstrInfo.td:2719 |
| 1029 | BINSRI_D = 1014, // MipsMSAInstrInfo.td:2722 |
| 1030 | BINSRI_H = 1015, // MipsMSAInstrInfo.td:2720 |
| 1031 | BINSRI_W = 1016, // MipsMSAInstrInfo.td:2721 |
| 1032 | BINSR_B = 1017, // MipsMSAInstrInfo.td:2714 |
| 1033 | BINSR_D = 1018, // MipsMSAInstrInfo.td:2717 |
| 1034 | BINSR_H = 1019, // MipsMSAInstrInfo.td:2715 |
| 1035 | BINSR_W = 1020, // MipsMSAInstrInfo.td:2716 |
| 1036 | BITREV = 1021, // MipsDSPInstrInfo.td:1171 |
| 1037 | BITREV_MM = 1022, // MicroMipsDSPInstrInfo.td:503 |
| 1038 | BITSWAP = 1023, // Mips32r6InstrInfo.td:843 |
| 1039 | BITSWAP_MMR6 = 1024, // MicroMips32r6InstrInfo.td:1282 |
| 1040 | BLEZ = 1025, // MipsInstrInfo.td:2287 |
| 1041 | BLEZ64 = 1026, // Mips64InstrInfo.td:279 |
| 1042 | BLEZALC = 1027, // Mips32r6InstrInfo.td:845 |
| 1043 | BLEZALC_MMR6 = 1028, // MicroMips32r6InstrInfo.td:1573 |
| 1044 | BLEZC = 1029, // Mips32r6InstrInfo.td:846 |
| 1045 | BLEZC64 = 1030, // Mips64r6InstrInfo.td:173 |
| 1046 | BLEZC_MMR6 = 1031, // MicroMips32r6InstrInfo.td:1566 |
| 1047 | BLEZL = 1032, // MipsInstrInfo.td:2289 |
| 1048 | BLEZ_MM = 1033, // MicroMipsInstrInfo.td:961 |
| 1049 | BLTC = 1034, // Mips32r6InstrInfo.td:847 |
| 1050 | BLTC64 = 1035, // Mips64r6InstrInfo.td:174 |
| 1051 | BLTC_MMR6 = 1036, // MicroMips32r6InstrInfo.td:1559 |
| 1052 | BLTUC = 1037, // Mips32r6InstrInfo.td:848 |
| 1053 | BLTUC64 = 1038, // Mips64r6InstrInfo.td:175 |
| 1054 | BLTUC_MMR6 = 1039, // MicroMips32r6InstrInfo.td:1560 |
| 1055 | BLTZ = 1040, // MipsInstrInfo.td:2291 |
| 1056 | BLTZ64 = 1041, // Mips64InstrInfo.td:281 |
| 1057 | BLTZAL = 1042, // MipsInstrInfo.td:2313 |
| 1058 | BLTZALC = 1043, // Mips32r6InstrInfo.td:849 |
| 1059 | BLTZALC_MMR6 = 1044, // MicroMips32r6InstrInfo.td:1575 |
| 1060 | BLTZALL = 1045, // MipsInstrInfo.td:2315 |
| 1061 | BLTZALS_MM = 1046, // MicroMipsInstrInfo.td:976 |
| 1062 | BLTZAL_MM = 1047, // MicroMipsInstrInfo.td:967 |
| 1063 | BLTZC = 1048, // Mips32r6InstrInfo.td:850 |
| 1064 | BLTZC64 = 1049, // Mips64r6InstrInfo.td:180 |
| 1065 | BLTZC_MMR6 = 1050, // MicroMips32r6InstrInfo.td:1565 |
| 1066 | BLTZL = 1051, // MipsInstrInfo.td:2293 |
| 1067 | BLTZ_MM = 1052, // MicroMipsInstrInfo.td:963 |
| 1068 | BMNZI_B = 1053, // MipsMSAInstrInfo.td:2726 |
| 1069 | BMNZ_V = 1054, // MipsMSAInstrInfo.td:2724 |
| 1070 | BMZI_B = 1055, // MipsMSAInstrInfo.td:2730 |
| 1071 | BMZ_V = 1056, // MipsMSAInstrInfo.td:2728 |
| 1072 | BNE = 1057, // MipsInstrInfo.td:2275 |
| 1073 | BNE64 = 1058, // Mips64InstrInfo.td:273 |
| 1074 | BNEC = 1059, // Mips32r6InstrInfo.td:851 |
| 1075 | BNEC64 = 1060, // Mips64r6InstrInfo.td:176 |
| 1076 | BNEC_MMR6 = 1061, // MicroMips32r6InstrInfo.td:1563 |
| 1077 | BNEGI_B = 1062, // MipsMSAInstrInfo.td:2737 |
| 1078 | BNEGI_D = 1063, // MipsMSAInstrInfo.td:2740 |
| 1079 | BNEGI_H = 1064, // MipsMSAInstrInfo.td:2738 |
| 1080 | BNEGI_W = 1065, // MipsMSAInstrInfo.td:2739 |
| 1081 | BNEG_B = 1066, // MipsMSAInstrInfo.td:2732 |
| 1082 | BNEG_D = 1067, // MipsMSAInstrInfo.td:2735 |
| 1083 | BNEG_H = 1068, // MipsMSAInstrInfo.td:2733 |
| 1084 | BNEG_W = 1069, // MipsMSAInstrInfo.td:2734 |
| 1085 | BNEL = 1070, // MipsInstrInfo.td:2277 |
| 1086 | BNEZ16_MM = 1071, // MicroMipsInstrInfo.td:671 |
| 1087 | BNEZALC = 1072, // Mips32r6InstrInfo.td:852 |
| 1088 | BNEZALC_MMR6 = 1073, // MicroMips32r6InstrInfo.td:1286 |
| 1089 | BNEZC = 1074, // Mips32r6InstrInfo.td:853 |
| 1090 | BNEZC16_MMR6 = 1075, // MicroMips32r6InstrInfo.td:1280 |
| 1091 | BNEZC64 = 1076, // Mips64r6InstrInfo.td:177 |
| 1092 | BNEZC_MM = 1077, // MicroMipsInstrInfo.td:699 |
| 1093 | BNEZC_MMR6 = 1078, // MicroMips32r6InstrInfo.td:1278 |
| 1094 | BNE_MM = 1079, // MicroMipsInstrInfo.td:955 |
| 1095 | BNVC = 1080, // Mips32r6InstrInfo.td:854 |
| 1096 | BNVC_MMR6 = 1081, // MicroMips32r6InstrInfo.td:1555 |
| 1097 | BNZ_B = 1082, // MipsMSAInstrInfo.td:2742 |
| 1098 | BNZ_D = 1083, // MipsMSAInstrInfo.td:2745 |
| 1099 | BNZ_H = 1084, // MipsMSAInstrInfo.td:2743 |
| 1100 | BNZ_V = 1085, // MipsMSAInstrInfo.td:2747 |
| 1101 | BNZ_W = 1086, // MipsMSAInstrInfo.td:2744 |
| 1102 | BOVC = 1087, // Mips32r6InstrInfo.td:855 |
| 1103 | BOVC_MMR6 = 1088, // MicroMips32r6InstrInfo.td:1553 |
| 1104 | BPOSGE32 = 1089, // MipsDSPInstrInfo.td:1183 |
| 1105 | BPOSGE32C_MMR3 = 1090, // MicroMipsDSPInstrInfo.td:579 |
| 1106 | BPOSGE32_MM = 1091, // MicroMipsDSPInstrInfo.td:504 |
| 1107 | BREAK = 1092, // MipsInstrInfo.td:2232 |
| 1108 | BREAK16_MM = 1093, // MicroMipsInstrInfo.td:674 |
| 1109 | BREAK16_MMR6 = 1094, // MicroMips32r6InstrInfo.td:1472 |
| 1110 | BREAK_MM = 1095, // MicroMipsInstrInfo.td:987 |
| 1111 | BREAK_MMR6 = 1096, // MicroMips32r6InstrInfo.td:1288 |
| 1112 | BSELI_B = 1097, // MipsMSAInstrInfo.td:2769 |
| 1113 | BSEL_V = 1098, // MipsMSAInstrInfo.td:2749 |
| 1114 | BSETI_B = 1099, // MipsMSAInstrInfo.td:2776 |
| 1115 | BSETI_D = 1100, // MipsMSAInstrInfo.td:2779 |
| 1116 | BSETI_H = 1101, // MipsMSAInstrInfo.td:2777 |
| 1117 | BSETI_W = 1102, // MipsMSAInstrInfo.td:2778 |
| 1118 | BSET_B = 1103, // MipsMSAInstrInfo.td:2771 |
| 1119 | BSET_D = 1104, // MipsMSAInstrInfo.td:2774 |
| 1120 | BSET_H = 1105, // MipsMSAInstrInfo.td:2772 |
| 1121 | BSET_W = 1106, // MipsMSAInstrInfo.td:2773 |
| 1122 | BZ_B = 1107, // MipsMSAInstrInfo.td:2781 |
| 1123 | BZ_D = 1108, // MipsMSAInstrInfo.td:2784 |
| 1124 | BZ_H = 1109, // MipsMSAInstrInfo.td:2782 |
| 1125 | BZ_V = 1110, // MipsMSAInstrInfo.td:2786 |
| 1126 | BZ_W = 1111, // MipsMSAInstrInfo.td:2783 |
| 1127 | BeqzRxImm16 = 1112, // Mips16InstrInfo.td:564 |
| 1128 | BeqzRxImmX16 = 1113, // Mips16InstrInfo.td:572 |
| 1129 | Bimm16 = 1114, // Mips16InstrInfo.td:580 |
| 1130 | BimmX16 = 1115, // Mips16InstrInfo.td:586 |
| 1131 | BnezRxImm16 = 1116, // Mips16InstrInfo.td:593 |
| 1132 | BnezRxImmX16 = 1117, // Mips16InstrInfo.td:600 |
| 1133 | Break16 = 1118, // Mips16InstrInfo.td:608 |
| 1134 | Bteqz16 = 1119, // Mips16InstrInfo.td:614 |
| 1135 | BteqzX16 = 1120, // Mips16InstrInfo.td:618 |
| 1136 | Btnez16 = 1121, // Mips16InstrInfo.td:642 |
| 1137 | BtnezX16 = 1122, // Mips16InstrInfo.td:646 |
| 1138 | CACHE = 1123, // MipsInstrInfo.td:2571 |
| 1139 | CACHEE = 1124, // MipsEVAInstrInfo.td:199 |
| 1140 | CACHEE_MM = 1125, // MicroMipsInstrInfo.td:1049 |
| 1141 | CACHE_MM = 1126, // MicroMipsInstrInfo.td:1040 |
| 1142 | CACHE_MMR6 = 1127, // MicroMips32r6InstrInfo.td:1289 |
| 1143 | CACHE_R6 = 1128, // Mips32r6InstrInfo.td:856 |
| 1144 | CEIL_L_D64 = 1129, // MipsInstrFPU.td:473 |
| 1145 | CEIL_L_D_MMR6 = 1130, // MicroMips32r6InstrInfo.td:1439 |
| 1146 | CEIL_L_S = 1131, // MipsInstrFPU.td:471 |
| 1147 | CEIL_L_S_MMR6 = 1132, // MicroMips32r6InstrInfo.td:1437 |
| 1148 | CEIL_W_D32 = 1133, // MipsInstrFPU.td:179 |
| 1149 | CEIL_W_D64 = 1134, // MipsInstrFPU.td:180 |
| 1150 | CEIL_W_D_MMR6 = 1135, // MicroMips32r6InstrInfo.td:1443 |
| 1151 | CEIL_W_MM = 1136, // MicroMipsInstrFPU.td:91 |
| 1152 | CEIL_W_S = 1137, // MipsInstrFPU.td:420 |
| 1153 | CEIL_W_S_MM = 1138, // MicroMipsInstrFPU.td:236 |
| 1154 | CEIL_W_S_MMR6 = 1139, // MicroMips32r6InstrInfo.td:1441 |
| 1155 | CEQI_B = 1140, // MipsMSAInstrInfo.td:2793 |
| 1156 | CEQI_D = 1141, // MipsMSAInstrInfo.td:2796 |
| 1157 | CEQI_H = 1142, // MipsMSAInstrInfo.td:2794 |
| 1158 | CEQI_W = 1143, // MipsMSAInstrInfo.td:2795 |
| 1159 | CEQ_B = 1144, // MipsMSAInstrInfo.td:2788 |
| 1160 | CEQ_D = 1145, // MipsMSAInstrInfo.td:2791 |
| 1161 | CEQ_H = 1146, // MipsMSAInstrInfo.td:2789 |
| 1162 | CEQ_W = 1147, // MipsMSAInstrInfo.td:2790 |
| 1163 | CFC1 = 1148, // MipsInstrFPU.td:607 |
| 1164 | CFC1_MM = 1149, // MicroMipsInstrFPU.td:261 |
| 1165 | CFC2_MM = 1150, // MicroMipsInstrInfo.td:689 |
| 1166 | CFCMSA = 1151, // MipsMSAInstrInfo.td:2798 |
| 1167 | CINS = 1152, // Mips64InstrInfo.td:550 |
| 1168 | CINS32 = 1153, // Mips64InstrInfo.td:552 |
| 1169 | CINS64_32 = 1154, // Mips64InstrInfo.td:557 |
| 1170 | CINS_i32 = 1155, // Mips64InstrInfo.td:555 |
| 1171 | CLASS_D = 1156, // Mips32r6InstrInfo.td:857 |
| 1172 | CLASS_D_MMR6 = 1157, // MicroMips32r6InstrInfo.td:1521 |
| 1173 | CLASS_S = 1158, // Mips32r6InstrInfo.td:858 |
| 1174 | CLASS_S_MMR6 = 1159, // MicroMips32r6InstrInfo.td:1519 |
| 1175 | CLEI_S_B = 1160, // MipsMSAInstrInfo.td:2810 |
| 1176 | CLEI_S_D = 1161, // MipsMSAInstrInfo.td:2813 |
| 1177 | CLEI_S_H = 1162, // MipsMSAInstrInfo.td:2811 |
| 1178 | CLEI_S_W = 1163, // MipsMSAInstrInfo.td:2812 |
| 1179 | CLEI_U_B = 1164, // MipsMSAInstrInfo.td:2815 |
| 1180 | CLEI_U_D = 1165, // MipsMSAInstrInfo.td:2818 |
| 1181 | CLEI_U_H = 1166, // MipsMSAInstrInfo.td:2816 |
| 1182 | CLEI_U_W = 1167, // MipsMSAInstrInfo.td:2817 |
| 1183 | CLE_S_B = 1168, // MipsMSAInstrInfo.td:2800 |
| 1184 | CLE_S_D = 1169, // MipsMSAInstrInfo.td:2803 |
| 1185 | CLE_S_H = 1170, // MipsMSAInstrInfo.td:2801 |
| 1186 | CLE_S_W = 1171, // MipsMSAInstrInfo.td:2802 |
| 1187 | CLE_U_B = 1172, // MipsMSAInstrInfo.td:2805 |
| 1188 | CLE_U_D = 1173, // MipsMSAInstrInfo.td:2808 |
| 1189 | CLE_U_H = 1174, // MipsMSAInstrInfo.td:2806 |
| 1190 | CLE_U_W = 1175, // MipsMSAInstrInfo.td:2807 |
| 1191 | CLO = 1176, // MipsInstrInfo.td:2412 |
| 1192 | CLO_MM = 1177, // MicroMipsInstrInfo.td:903 |
| 1193 | CLO_MMR6 = 1178, // MicroMips32r6InstrInfo.td:1290 |
| 1194 | CLO_R6 = 1179, // Mips32r6InstrInfo.td:860 |
| 1195 | CLTI_S_B = 1180, // MipsMSAInstrInfo.td:2830 |
| 1196 | CLTI_S_D = 1181, // MipsMSAInstrInfo.td:2833 |
| 1197 | CLTI_S_H = 1182, // MipsMSAInstrInfo.td:2831 |
| 1198 | CLTI_S_W = 1183, // MipsMSAInstrInfo.td:2832 |
| 1199 | CLTI_U_B = 1184, // MipsMSAInstrInfo.td:2835 |
| 1200 | CLTI_U_D = 1185, // MipsMSAInstrInfo.td:2838 |
| 1201 | CLTI_U_H = 1186, // MipsMSAInstrInfo.td:2836 |
| 1202 | CLTI_U_W = 1187, // MipsMSAInstrInfo.td:2837 |
| 1203 | CLT_S_B = 1188, // MipsMSAInstrInfo.td:2820 |
| 1204 | CLT_S_D = 1189, // MipsMSAInstrInfo.td:2823 |
| 1205 | CLT_S_H = 1190, // MipsMSAInstrInfo.td:2821 |
| 1206 | CLT_S_W = 1191, // MipsMSAInstrInfo.td:2822 |
| 1207 | CLT_U_B = 1192, // MipsMSAInstrInfo.td:2825 |
| 1208 | CLT_U_D = 1193, // MipsMSAInstrInfo.td:2828 |
| 1209 | CLT_U_H = 1194, // MipsMSAInstrInfo.td:2826 |
| 1210 | CLT_U_W = 1195, // MipsMSAInstrInfo.td:2827 |
| 1211 | CLZ = 1196, // MipsInstrInfo.td:2410 |
| 1212 | CLZ_MM = 1197, // MicroMipsInstrInfo.td:901 |
| 1213 | CLZ_MMR6 = 1198, // MicroMips32r6InstrInfo.td:1291 |
| 1214 | CLZ_R6 = 1199, // Mips32r6InstrInfo.td:861 |
| 1215 | CMPGDU_EQ_QB = 1200, // MipsDSPInstrInfo.td:1211 |
| 1216 | CMPGDU_EQ_QB_MMR2 = 1201, // MicroMipsDSPInstrInfo.td:539 |
| 1217 | CMPGDU_LE_QB = 1202, // MipsDSPInstrInfo.td:1213 |
| 1218 | CMPGDU_LE_QB_MMR2 = 1203, // MicroMipsDSPInstrInfo.td:543 |
| 1219 | CMPGDU_LT_QB = 1204, // MipsDSPInstrInfo.td:1212 |
| 1220 | CMPGDU_LT_QB_MMR2 = 1205, // MicroMipsDSPInstrInfo.td:541 |
| 1221 | CMPGU_EQ_QB = 1206, // MipsDSPInstrInfo.td:1165 |
| 1222 | CMPGU_EQ_QB_MM = 1207, // MicroMipsDSPInstrInfo.td:509 |
| 1223 | CMPGU_LE_QB = 1208, // MipsDSPInstrInfo.td:1167 |
| 1224 | CMPGU_LE_QB_MM = 1209, // MicroMipsDSPInstrInfo.td:511 |
| 1225 | CMPGU_LT_QB = 1210, // MipsDSPInstrInfo.td:1166 |
| 1226 | CMPGU_LT_QB_MM = 1211, // MicroMipsDSPInstrInfo.td:510 |
| 1227 | CMPU_EQ_QB = 1212, // MipsDSPInstrInfo.td:1162 |
| 1228 | CMPU_EQ_QB_MM = 1213, // MicroMipsDSPInstrInfo.td:512 |
| 1229 | CMPU_LE_QB = 1214, // MipsDSPInstrInfo.td:1164 |
| 1230 | CMPU_LE_QB_MM = 1215, // MicroMipsDSPInstrInfo.td:514 |
| 1231 | CMPU_LT_QB = 1216, // MipsDSPInstrInfo.td:1163 |
| 1232 | CMPU_LT_QB_MM = 1217, // MicroMipsDSPInstrInfo.td:513 |
| 1233 | CMP_AF_D_MMR6 = 1218, // MicroMips32r6InstrInfo.td:883 |
| 1234 | CMP_AF_S_MMR6 = 1219, // MicroMips32r6InstrInfo.td:883 |
| 1235 | CMP_EQ_D = 1220, // Mips32r6InstrInfo.td:236 |
| 1236 | CMP_EQ_D_MMR6 = 1221, // MicroMips32r6InstrInfo.td:891 |
| 1237 | CMP_EQ_PH = 1222, // MipsDSPInstrInfo.td:1168 |
| 1238 | CMP_EQ_PH_MM = 1223, // MicroMipsDSPInstrInfo.td:506 |
| 1239 | CMP_EQ_S = 1224, // Mips32r6InstrInfo.td:236 |
| 1240 | CMP_EQ_S_MMR6 = 1225, // MicroMips32r6InstrInfo.td:891 |
| 1241 | CMP_F_D = 1226, // Mips32r6InstrInfo.td:228 |
| 1242 | CMP_F_S = 1227, // Mips32r6InstrInfo.td:228 |
| 1243 | CMP_LE_D = 1228, // Mips32r6InstrInfo.td:258 |
| 1244 | CMP_LE_D_MMR6 = 1229, // MicroMips32r6InstrInfo.td:907 |
| 1245 | CMP_LE_PH = 1230, // MipsDSPInstrInfo.td:1170 |
| 1246 | CMP_LE_PH_MM = 1231, // MicroMipsDSPInstrInfo.td:508 |
| 1247 | CMP_LE_S = 1232, // Mips32r6InstrInfo.td:258 |
| 1248 | CMP_LE_S_MMR6 = 1233, // MicroMips32r6InstrInfo.td:907 |
| 1249 | CMP_LT_D = 1234, // Mips32r6InstrInfo.td:247 |
| 1250 | CMP_LT_D_MMR6 = 1235, // MicroMips32r6InstrInfo.td:899 |
| 1251 | CMP_LT_PH = 1236, // MipsDSPInstrInfo.td:1169 |
| 1252 | CMP_LT_PH_MM = 1237, // MicroMipsDSPInstrInfo.td:507 |
| 1253 | CMP_LT_S = 1238, // Mips32r6InstrInfo.td:247 |
| 1254 | CMP_LT_S_MMR6 = 1239, // MicroMips32r6InstrInfo.td:899 |
| 1255 | CMP_SAF_D = 1240, // Mips32r6InstrInfo.td:270 |
| 1256 | CMP_SAF_D_MMR6 = 1241, // MicroMips32r6InstrInfo.td:917 |
| 1257 | CMP_SAF_S = 1242, // Mips32r6InstrInfo.td:270 |
| 1258 | CMP_SAF_S_MMR6 = 1243, // MicroMips32r6InstrInfo.td:917 |
| 1259 | CMP_SEQ_D = 1244, // Mips32r6InstrInfo.td:280 |
| 1260 | CMP_SEQ_D_MMR6 = 1245, // MicroMips32r6InstrInfo.td:925 |
| 1261 | CMP_SEQ_S = 1246, // Mips32r6InstrInfo.td:280 |
| 1262 | CMP_SEQ_S_MMR6 = 1247, // MicroMips32r6InstrInfo.td:925 |
| 1263 | CMP_SLE_D = 1248, // Mips32r6InstrInfo.td:300 |
| 1264 | CMP_SLE_D_MMR6 = 1249, // MicroMips32r6InstrInfo.td:941 |
| 1265 | CMP_SLE_S = 1250, // Mips32r6InstrInfo.td:300 |
| 1266 | CMP_SLE_S_MMR6 = 1251, // MicroMips32r6InstrInfo.td:941 |
| 1267 | CMP_SLT_D = 1252, // Mips32r6InstrInfo.td:290 |
| 1268 | CMP_SLT_D_MMR6 = 1253, // MicroMips32r6InstrInfo.td:933 |
| 1269 | CMP_SLT_S = 1254, // Mips32r6InstrInfo.td:290 |
| 1270 | CMP_SLT_S_MMR6 = 1255, // MicroMips32r6InstrInfo.td:933 |
| 1271 | CMP_SUEQ_D = 1256, // Mips32r6InstrInfo.td:285 |
| 1272 | CMP_SUEQ_D_MMR6 = 1257, // MicroMips32r6InstrInfo.td:929 |
| 1273 | CMP_SUEQ_S = 1258, // Mips32r6InstrInfo.td:285 |
| 1274 | CMP_SUEQ_S_MMR6 = 1259, // MicroMips32r6InstrInfo.td:929 |
| 1275 | CMP_SULE_D = 1260, // Mips32r6InstrInfo.td:305 |
| 1276 | CMP_SULE_D_MMR6 = 1261, // MicroMips32r6InstrInfo.td:945 |
| 1277 | CMP_SULE_S = 1262, // Mips32r6InstrInfo.td:305 |
| 1278 | CMP_SULE_S_MMR6 = 1263, // MicroMips32r6InstrInfo.td:945 |
| 1279 | CMP_SULT_D = 1264, // Mips32r6InstrInfo.td:295 |
| 1280 | CMP_SULT_D_MMR6 = 1265, // MicroMips32r6InstrInfo.td:937 |
| 1281 | CMP_SULT_S = 1266, // Mips32r6InstrInfo.td:295 |
| 1282 | CMP_SULT_S_MMR6 = 1267, // MicroMips32r6InstrInfo.td:937 |
| 1283 | CMP_SUN_D = 1268, // Mips32r6InstrInfo.td:275 |
| 1284 | CMP_SUN_D_MMR6 = 1269, // MicroMips32r6InstrInfo.td:921 |
| 1285 | CMP_SUN_S = 1270, // Mips32r6InstrInfo.td:275 |
| 1286 | CMP_SUN_S_MMR6 = 1271, // MicroMips32r6InstrInfo.td:921 |
| 1287 | CMP_UEQ_D = 1272, // Mips32r6InstrInfo.td:241 |
| 1288 | CMP_UEQ_D_MMR6 = 1273, // MicroMips32r6InstrInfo.td:895 |
| 1289 | CMP_UEQ_S = 1274, // Mips32r6InstrInfo.td:241 |
| 1290 | CMP_UEQ_S_MMR6 = 1275, // MicroMips32r6InstrInfo.td:895 |
| 1291 | CMP_ULE_D = 1276, // Mips32r6InstrInfo.td:263 |
| 1292 | CMP_ULE_D_MMR6 = 1277, // MicroMips32r6InstrInfo.td:911 |
| 1293 | CMP_ULE_S = 1278, // Mips32r6InstrInfo.td:263 |
| 1294 | CMP_ULE_S_MMR6 = 1279, // MicroMips32r6InstrInfo.td:911 |
| 1295 | CMP_ULT_D = 1280, // Mips32r6InstrInfo.td:252 |
| 1296 | CMP_ULT_D_MMR6 = 1281, // MicroMips32r6InstrInfo.td:903 |
| 1297 | CMP_ULT_S = 1282, // Mips32r6InstrInfo.td:252 |
| 1298 | CMP_ULT_S_MMR6 = 1283, // MicroMips32r6InstrInfo.td:903 |
| 1299 | CMP_UN_D = 1284, // Mips32r6InstrInfo.td:232 |
| 1300 | CMP_UN_D_MMR6 = 1285, // MicroMips32r6InstrInfo.td:887 |
| 1301 | CMP_UN_S = 1286, // Mips32r6InstrInfo.td:232 |
| 1302 | CMP_UN_S_MMR6 = 1287, // MicroMips32r6InstrInfo.td:887 |
| 1303 | COPY_S_B = 1288, // MipsMSAInstrInfo.td:2840 |
| 1304 | COPY_S_D = 1289, // MipsMSAInstrInfo.td:2843 |
| 1305 | COPY_S_H = 1290, // MipsMSAInstrInfo.td:2841 |
| 1306 | COPY_S_W = 1291, // MipsMSAInstrInfo.td:2842 |
| 1307 | COPY_U_B = 1292, // MipsMSAInstrInfo.td:2845 |
| 1308 | COPY_U_H = 1293, // MipsMSAInstrInfo.td:2846 |
| 1309 | COPY_U_W = 1294, // MipsMSAInstrInfo.td:2847 |
| 1310 | CRC32B = 1295, // Mips32r6InstrInfo.td:937 |
| 1311 | CRC32CB = 1296, // Mips32r6InstrInfo.td:940 |
| 1312 | CRC32CD = 1297, // Mips64r6InstrInfo.td:185 |
| 1313 | CRC32CH = 1298, // Mips32r6InstrInfo.td:941 |
| 1314 | CRC32CW = 1299, // Mips32r6InstrInfo.td:942 |
| 1315 | CRC32D = 1300, // Mips64r6InstrInfo.td:184 |
| 1316 | CRC32H = 1301, // Mips32r6InstrInfo.td:938 |
| 1317 | CRC32W = 1302, // Mips32r6InstrInfo.td:939 |
| 1318 | CTC1 = 1303, // MipsInstrFPU.td:609 |
| 1319 | CTC1_MM = 1304, // MicroMipsInstrFPU.td:263 |
| 1320 | CTC2_MM = 1305, // MicroMipsInstrInfo.td:692 |
| 1321 | CTCMSA = 1306, // MipsMSAInstrInfo.td:2852 |
| 1322 | CVT_D32_S = 1307, // MipsInstrFPU.td:494 |
| 1323 | CVT_D32_S_MM = 1308, // MicroMipsInstrFPU.td:146 |
| 1324 | CVT_D32_W = 1309, // MipsInstrFPU.td:496 |
| 1325 | CVT_D32_W_MM = 1310, // MicroMipsInstrFPU.td:148 |
| 1326 | CVT_D64_L = 1311, // MipsInstrFPU.td:561 |
| 1327 | CVT_D64_S = 1312, // MipsInstrFPU.td:559 |
| 1328 | CVT_D64_S_MM = 1313, // MicroMipsInstrFPU.td:153 |
| 1329 | CVT_D64_W = 1314, // MipsInstrFPU.td:557 |
| 1330 | CVT_D64_W_MM = 1315, // MicroMipsInstrFPU.td:155 |
| 1331 | CVT_D_L_MMR6 = 1316, // MicroMips32r6InstrInfo.td:1417 |
| 1332 | CVT_L_D64 = 1317, // MipsInstrFPU.td:487 |
| 1333 | CVT_L_D64_MM = 1318, // MicroMipsInstrFPU.td:104 |
| 1334 | CVT_L_D_MMR6 = 1319, // MicroMips32r6InstrInfo.td:1413 |
| 1335 | CVT_L_S = 1320, // MipsInstrFPU.td:485 |
| 1336 | CVT_L_S_MM = 1321, // MicroMipsInstrFPU.td:102 |
| 1337 | CVT_L_S_MMR6 = 1322, // MicroMips32r6InstrInfo.td:1411 |
| 1338 | CVT_PS_PW64 = 1323, // MipsInstrFPU.td:542 |
| 1339 | CVT_PS_S64 = 1324, // MipsInstrFPU.td:511 |
| 1340 | CVT_PW_PS64 = 1325, // MipsInstrFPU.td:545 |
| 1341 | CVT_S_D32 = 1326, // MipsInstrFPU.td:492 |
| 1342 | CVT_S_D32_MM = 1327, // MicroMipsInstrFPU.td:162 |
| 1343 | CVT_S_D64 = 1328, // MipsInstrFPU.td:555 |
| 1344 | CVT_S_D64_MM = 1329, // MicroMipsInstrFPU.td:157 |
| 1345 | CVT_S_L = 1330, // MipsInstrFPU.td:553 |
| 1346 | CVT_S_L_MMR6 = 1331, // MicroMips32r6InstrInfo.td:1421 |
| 1347 | CVT_S_PL64 = 1332, // MipsInstrFPU.td:531 |
| 1348 | CVT_S_PU64 = 1333, // MipsInstrFPU.td:528 |
| 1349 | CVT_S_W = 1334, // MipsInstrFPU.td:483 |
| 1350 | CVT_S_W_MM = 1335, // MicroMipsInstrFPU.td:164 |
| 1351 | CVT_S_W_MMR6 = 1336, // MicroMips32r6InstrInfo.td:1419 |
| 1352 | CVT_W_D32 = 1337, // MipsInstrFPU.td:179 |
| 1353 | CVT_W_D32_MM = 1338, // MicroMipsInstrFPU.td:107 |
| 1354 | CVT_W_D64 = 1339, // MipsInstrFPU.td:180 |
| 1355 | CVT_W_D64_MM = 1340, // MicroMipsInstrFPU.td:112 |
| 1356 | CVT_W_S = 1341, // MipsInstrFPU.td:432 |
| 1357 | CVT_W_S_MM = 1342, // MicroMipsInstrFPU.td:82 |
| 1358 | CVT_W_S_MMR6 = 1343, // MicroMips32r6InstrInfo.td:1415 |
| 1359 | C_EQ_D32 = 1344, // MipsInstrFPU.td:314 |
| 1360 | C_EQ_D32_MM = 1345, // MicroMipsInstrFPU.td:326 |
| 1361 | C_EQ_D64 = 1346, // MipsInstrFPU.td:314 |
| 1362 | C_EQ_D64_MM = 1347, // MicroMipsInstrFPU.td:326 |
| 1363 | C_EQ_S = 1348, // MipsInstrFPU.td:314 |
| 1364 | C_EQ_S_MM = 1349, // MicroMipsInstrFPU.td:326 |
| 1365 | C_F_D32 = 1350, // MipsInstrFPU.td:309 |
| 1366 | C_F_D32_MM = 1351, // MicroMipsInstrFPU.td:316 |
| 1367 | C_F_D64 = 1352, // MipsInstrFPU.td:309 |
| 1368 | C_F_D64_MM = 1353, // MicroMipsInstrFPU.td:316 |
| 1369 | C_F_S = 1354, // MipsInstrFPU.td:309 |
| 1370 | C_F_S_MM = 1355, // MicroMipsInstrFPU.td:316 |
| 1371 | C_LE_D32 = 1356, // MipsInstrFPU.td:381 |
| 1372 | C_LE_D32_MM = 1357, // MicroMipsInstrFPU.td:379 |
| 1373 | C_LE_D64 = 1358, // MipsInstrFPU.td:381 |
| 1374 | C_LE_D64_MM = 1359, // MicroMipsInstrFPU.td:379 |
| 1375 | C_LE_S = 1360, // MipsInstrFPU.td:381 |
| 1376 | C_LE_S_MM = 1361, // MicroMipsInstrFPU.td:379 |
| 1377 | C_LT_D32 = 1362, // MipsInstrFPU.td:371 |
| 1378 | C_LT_D32_MM = 1363, // MicroMipsInstrFPU.td:371 |
| 1379 | C_LT_D64 = 1364, // MipsInstrFPU.td:371 |
| 1380 | C_LT_D64_MM = 1365, // MicroMipsInstrFPU.td:371 |
| 1381 | C_LT_S = 1366, // MipsInstrFPU.td:371 |
| 1382 | C_LT_S_MM = 1367, // MicroMipsInstrFPU.td:371 |
| 1383 | C_NGE_D32 = 1368, // MipsInstrFPU.td:376 |
| 1384 | C_NGE_D32_MM = 1369, // MicroMipsInstrFPU.td:375 |
| 1385 | C_NGE_D64 = 1370, // MipsInstrFPU.td:376 |
| 1386 | C_NGE_D64_MM = 1371, // MicroMipsInstrFPU.td:375 |
| 1387 | C_NGE_S = 1372, // MipsInstrFPU.td:376 |
| 1388 | C_NGE_S_MM = 1373, // MicroMipsInstrFPU.td:375 |
| 1389 | C_NGLE_D32 = 1374, // MipsInstrFPU.td:355 |
| 1390 | C_NGLE_D32_MM = 1375, // MicroMipsInstrFPU.td:358 |
| 1391 | C_NGLE_D64 = 1376, // MipsInstrFPU.td:355 |
| 1392 | C_NGLE_D64_MM = 1377, // MicroMipsInstrFPU.td:358 |
| 1393 | C_NGLE_S = 1378, // MipsInstrFPU.td:355 |
| 1394 | C_NGLE_S_MM = 1379, // MicroMipsInstrFPU.td:358 |
| 1395 | C_NGL_D32 = 1380, // MipsInstrFPU.td:366 |
| 1396 | C_NGL_D32_MM = 1381, // MicroMipsInstrFPU.td:367 |
| 1397 | C_NGL_D64 = 1382, // MipsInstrFPU.td:366 |
| 1398 | C_NGL_D64_MM = 1383, // MicroMipsInstrFPU.td:367 |
| 1399 | C_NGL_S = 1384, // MipsInstrFPU.td:366 |
| 1400 | C_NGL_S_MM = 1385, // MicroMipsInstrFPU.td:367 |
| 1401 | C_NGT_D32 = 1386, // MipsInstrFPU.td:386 |
| 1402 | C_NGT_D32_MM = 1387, // MicroMipsInstrFPU.td:383 |
| 1403 | C_NGT_D64 = 1388, // MipsInstrFPU.td:386 |
| 1404 | C_NGT_D64_MM = 1389, // MicroMipsInstrFPU.td:383 |
| 1405 | C_NGT_S = 1390, // MipsInstrFPU.td:386 |
| 1406 | C_NGT_S_MM = 1391, // MicroMipsInstrFPU.td:383 |
| 1407 | C_OLE_D32 = 1392, // MipsInstrFPU.td:323 |
| 1408 | C_OLE_D32_MM = 1393, // MicroMipsInstrFPU.td:344 |
| 1409 | C_OLE_D64 = 1394, // MipsInstrFPU.td:323 |
| 1410 | C_OLE_D64_MM = 1395, // MicroMipsInstrFPU.td:344 |
| 1411 | C_OLE_S = 1396, // MipsInstrFPU.td:323 |
| 1412 | C_OLE_S_MM = 1397, // MicroMipsInstrFPU.td:344 |
| 1413 | C_OLT_D32 = 1398, // MipsInstrFPU.td:319 |
| 1414 | C_OLT_D32_MM = 1399, // MicroMipsInstrFPU.td:336 |
| 1415 | C_OLT_D64 = 1400, // MipsInstrFPU.td:319 |
| 1416 | C_OLT_D64_MM = 1401, // MicroMipsInstrFPU.td:336 |
| 1417 | C_OLT_S = 1402, // MipsInstrFPU.td:319 |
| 1418 | C_OLT_S_MM = 1403, // MicroMipsInstrFPU.td:336 |
| 1419 | C_SEQ_D32 = 1404, // MipsInstrFPU.td:360 |
| 1420 | C_SEQ_D32_MM = 1405, // MicroMipsInstrFPU.td:362 |
| 1421 | C_SEQ_D64 = 1406, // MipsInstrFPU.td:360 |
| 1422 | C_SEQ_D64_MM = 1407, // MicroMipsInstrFPU.td:362 |
| 1423 | C_SEQ_S = 1408, // MipsInstrFPU.td:360 |
| 1424 | C_SEQ_S_MM = 1409, // MicroMipsInstrFPU.td:362 |
| 1425 | C_SF_D32 = 1410, // MipsInstrFPU.td:349 |
| 1426 | C_SF_D32_MM = 1411, // MicroMipsInstrFPU.td:353 |
| 1427 | C_SF_D64 = 1412, // MipsInstrFPU.td:349 |
| 1428 | C_SF_D64_MM = 1413, // MicroMipsInstrFPU.td:353 |
| 1429 | C_SF_S = 1414, // MipsInstrFPU.td:349 |
| 1430 | C_SF_S_MM = 1415, // MicroMipsInstrFPU.td:353 |
| 1431 | C_UEQ_D32 = 1416, // MipsInstrFPU.td:335 |
| 1432 | C_UEQ_D32_MM = 1417, // MicroMipsInstrFPU.td:331 |
| 1433 | C_UEQ_D64 = 1418, // MipsInstrFPU.td:335 |
| 1434 | C_UEQ_D64_MM = 1419, // MicroMipsInstrFPU.td:331 |
| 1435 | C_UEQ_S = 1420, // MipsInstrFPU.td:335 |
| 1436 | C_UEQ_S_MM = 1421, // MicroMipsInstrFPU.td:331 |
| 1437 | C_ULE_D32 = 1422, // MipsInstrFPU.td:344 |
| 1438 | C_ULE_D32_MM = 1423, // MicroMipsInstrFPU.td:348 |
| 1439 | C_ULE_D64 = 1424, // MipsInstrFPU.td:344 |
| 1440 | C_ULE_D64_MM = 1425, // MicroMipsInstrFPU.td:348 |
| 1441 | C_ULE_S = 1426, // MipsInstrFPU.td:344 |
| 1442 | C_ULE_S_MM = 1427, // MicroMipsInstrFPU.td:348 |
| 1443 | C_ULT_D32 = 1428, // MipsInstrFPU.td:340 |
| 1444 | C_ULT_D32_MM = 1429, // MicroMipsInstrFPU.td:340 |
| 1445 | C_ULT_D64 = 1430, // MipsInstrFPU.td:340 |
| 1446 | C_ULT_D64_MM = 1431, // MicroMipsInstrFPU.td:340 |
| 1447 | C_ULT_S = 1432, // MipsInstrFPU.td:340 |
| 1448 | C_ULT_S_MM = 1433, // MicroMipsInstrFPU.td:340 |
| 1449 | C_UN_D32 = 1434, // MipsInstrFPU.td:330 |
| 1450 | C_UN_D32_MM = 1435, // MicroMipsInstrFPU.td:321 |
| 1451 | C_UN_D64 = 1436, // MipsInstrFPU.td:330 |
| 1452 | C_UN_D64_MM = 1437, // MicroMipsInstrFPU.td:321 |
| 1453 | C_UN_S = 1438, // MipsInstrFPU.td:330 |
| 1454 | C_UN_S_MM = 1439, // MicroMipsInstrFPU.td:321 |
| 1455 | CmpRxRy16 = 1440, // Mips16InstrInfo.td:668 |
| 1456 | CmpiRxImm16 = 1441, // Mips16InstrInfo.td:677 |
| 1457 | CmpiRxImmX16 = 1442, // Mips16InstrInfo.td:686 |
| 1458 | DADD = 1443, // Mips64InstrInfo.td:143 |
| 1459 | DADDi = 1444, // Mips64InstrInfo.td:119 |
| 1460 | DADDiu = 1445, // Mips64InstrInfo.td:122 |
| 1461 | DADDu = 1446, // Mips64InstrInfo.td:145 |
| 1462 | DAHI = 1447, // Mips64r6InstrInfo.td:131 |
| 1463 | DALIGN = 1448, // Mips64r6InstrInfo.td:134 |
| 1464 | DATI = 1449, // Mips64r6InstrInfo.td:130 |
| 1465 | DAUI = 1450, // Mips64r6InstrInfo.td:133 |
| 1466 | DBITSWAP = 1451, // Mips64r6InstrInfo.td:135 |
| 1467 | DCLO = 1452, // Mips64InstrInfo.td:366 |
| 1468 | DCLO_R6 = 1453, // Mips64r6InstrInfo.td:136 |
| 1469 | DCLZ = 1454, // Mips64InstrInfo.td:364 |
| 1470 | DCLZ_R6 = 1455, // Mips64r6InstrInfo.td:137 |
| 1471 | DDIV = 1456, // Mips64r6InstrInfo.td:138 |
| 1472 | DDIVU = 1457, // Mips64r6InstrInfo.td:139 |
| 1473 | DERET = 1458, // MipsInstrInfo.td:2242 |
| 1474 | DERET_MM = 1459, // MicroMipsInstrInfo.td:993 |
| 1475 | DERET_MMR6 = 1460, // MicroMips32r6InstrInfo.td:1298 |
| 1476 | DEXT = 1461, // Mips64InstrInfo.td:390 |
| 1477 | DEXT64_32 = 1462, // Mips64InstrInfo.td:419 |
| 1478 | DEXTM = 1463, // Mips64InstrInfo.td:393 |
| 1479 | DEXTU = 1464, // Mips64InstrInfo.td:395 |
| 1480 | DI = 1465, // MipsInstrInfo.td:2246 |
| 1481 | DINS = 1466, // Mips64InstrInfo.td:406 |
| 1482 | DINSM = 1467, // Mips64InstrInfo.td:412 |
| 1483 | DINSU = 1468, // Mips64InstrInfo.td:409 |
| 1484 | DIV = 1469, // Mips32r6InstrInfo.td:865 |
| 1485 | DIVU = 1470, // Mips32r6InstrInfo.td:866 |
| 1486 | DIVU_MMR6 = 1471, // MicroMips32r6InstrInfo.td:1293 |
| 1487 | DIV_MMR6 = 1472, // MicroMips32r6InstrInfo.td:1292 |
| 1488 | DIV_S_B = 1473, // MipsMSAInstrInfo.td:2854 |
| 1489 | DIV_S_D = 1474, // MipsMSAInstrInfo.td:2857 |
| 1490 | DIV_S_H = 1475, // MipsMSAInstrInfo.td:2855 |
| 1491 | DIV_S_W = 1476, // MipsMSAInstrInfo.td:2856 |
| 1492 | DIV_U_B = 1477, // MipsMSAInstrInfo.td:2859 |
| 1493 | DIV_U_D = 1478, // MipsMSAInstrInfo.td:2862 |
| 1494 | DIV_U_H = 1479, // MipsMSAInstrInfo.td:2860 |
| 1495 | DIV_U_W = 1480, // MipsMSAInstrInfo.td:2861 |
| 1496 | DI_MM = 1481, // MicroMipsInstrInfo.td:997 |
| 1497 | DI_MMR6 = 1482, // MicroMips32r6InstrInfo.td:1296 |
| 1498 | DLSA = 1483, // MipsMSAInstrInfo.td:3145 |
| 1499 | DLSA_R6 = 1484, // Mips64r6InstrInfo.td:142 |
| 1500 | DMFC0 = 1485, // Mips64InstrInfo.td:633 |
| 1501 | DMFC1 = 1486, // MipsInstrFPU.td:644 |
| 1502 | DMFC2 = 1487, // Mips64InstrInfo.td:637 |
| 1503 | DMFC2_OCTEON = 1488, // Mips64InstrInfo.td:605 |
| 1504 | DMFGC0 = 1489, // Mips64InstrInfo.td:645 |
| 1505 | DMOD = 1490, // Mips64r6InstrInfo.td:140 |
| 1506 | DMODU = 1491, // Mips64r6InstrInfo.td:141 |
| 1507 | DMT = 1492, // MipsMTInstrInfo.td:92 |
| 1508 | DMTC0 = 1493, // Mips64InstrInfo.td:635 |
| 1509 | DMTC1 = 1494, // MipsInstrFPU.td:641 |
| 1510 | DMTC2 = 1495, // Mips64InstrInfo.td:639 |
| 1511 | DMTC2_OCTEON = 1496, // Mips64InstrInfo.td:607 |
| 1512 | DMTGC0 = 1497, // Mips64InstrInfo.td:647 |
| 1513 | DMUH = 1498, // Mips64r6InstrInfo.td:143 |
| 1514 | DMUHU = 1499, // Mips64r6InstrInfo.td:144 |
| 1515 | DMUL = 1500, // Mips64InstrInfo.td:537 |
| 1516 | DMULT = 1501, // Mips64InstrInfo.td:313 |
| 1517 | DMULTu = 1502, // Mips64InstrInfo.td:316 |
| 1518 | DMULU = 1503, // Mips64r6InstrInfo.td:146 |
| 1519 | DMUL_R6 = 1504, // Mips64r6InstrInfo.td:145 |
| 1520 | DOTP_S_D = 1505, // MipsMSAInstrInfo.td:2866 |
| 1521 | DOTP_S_H = 1506, // MipsMSAInstrInfo.td:2864 |
| 1522 | DOTP_S_W = 1507, // MipsMSAInstrInfo.td:2865 |
| 1523 | DOTP_U_D = 1508, // MipsMSAInstrInfo.td:2870 |
| 1524 | DOTP_U_H = 1509, // MipsMSAInstrInfo.td:2868 |
| 1525 | DOTP_U_W = 1510, // MipsMSAInstrInfo.td:2869 |
| 1526 | DPADD_S_D = 1511, // MipsMSAInstrInfo.td:2874 |
| 1527 | DPADD_S_H = 1512, // MipsMSAInstrInfo.td:2872 |
| 1528 | DPADD_S_W = 1513, // MipsMSAInstrInfo.td:2873 |
| 1529 | DPADD_U_D = 1514, // MipsMSAInstrInfo.td:2878 |
| 1530 | DPADD_U_H = 1515, // MipsMSAInstrInfo.td:2876 |
| 1531 | DPADD_U_W = 1516, // MipsMSAInstrInfo.td:2877 |
| 1532 | DPAQX_SA_W_PH = 1517, // MipsDSPInstrInfo.td:1235 |
| 1533 | DPAQX_SA_W_PH_MMR2 = 1518, // MicroMipsDSPInstrInfo.td:529 |
| 1534 | DPAQX_S_W_PH = 1519, // MipsDSPInstrInfo.td:1234 |
| 1535 | DPAQX_S_W_PH_MMR2 = 1520, // MicroMipsDSPInstrInfo.td:527 |
| 1536 | DPAQ_SA_L_W = 1521, // MipsDSPInstrInfo.td:1154 |
| 1537 | DPAQ_SA_L_W_MM = 1522, // MicroMipsDSPInstrInfo.td:407 |
| 1538 | DPAQ_S_W_PH = 1523, // MipsDSPInstrInfo.td:1152 |
| 1539 | DPAQ_S_W_PH_MM = 1524, // MicroMipsDSPInstrInfo.td:406 |
| 1540 | DPAU_H_QBL = 1525, // MipsDSPInstrInfo.td:1148 |
| 1541 | DPAU_H_QBL_MM = 1526, // MicroMipsDSPInstrInfo.td:408 |
| 1542 | DPAU_H_QBR = 1527, // MipsDSPInstrInfo.td:1149 |
| 1543 | DPAU_H_QBR_MM = 1528, // MicroMipsDSPInstrInfo.td:409 |
| 1544 | DPAX_W_PH = 1529, // MipsDSPInstrInfo.td:1236 |
| 1545 | DPAX_W_PH_MMR2 = 1530, // MicroMipsDSPInstrInfo.td:531 |
| 1546 | DPA_W_PH = 1531, // MipsDSPInstrInfo.td:1232 |
| 1547 | DPA_W_PH_MMR2 = 1532, // MicroMipsDSPInstrInfo.td:526 |
| 1548 | DPOP = 1533, // Mips64InstrInfo.td:578 |
| 1549 | DPSQX_SA_W_PH = 1534, // MipsDSPInstrInfo.td:1239 |
| 1550 | DPSQX_SA_W_PH_MMR2 = 1535, // MicroMipsDSPInstrInfo.td:558 |
| 1551 | DPSQX_S_W_PH = 1536, // MipsDSPInstrInfo.td:1238 |
| 1552 | DPSQX_S_W_PH_MMR2 = 1537, // MicroMipsDSPInstrInfo.td:556 |
| 1553 | DPSQ_SA_L_W = 1538, // MipsDSPInstrInfo.td:1155 |
| 1554 | DPSQ_SA_L_W_MM = 1539, // MicroMipsDSPInstrInfo.td:465 |
| 1555 | DPSQ_S_W_PH = 1540, // MipsDSPInstrInfo.td:1153 |
| 1556 | DPSQ_S_W_PH_MM = 1541, // MicroMipsDSPInstrInfo.td:464 |
| 1557 | DPSUB_S_D = 1542, // MipsMSAInstrInfo.td:2882 |
| 1558 | DPSUB_S_H = 1543, // MipsMSAInstrInfo.td:2880 |
| 1559 | DPSUB_S_W = 1544, // MipsMSAInstrInfo.td:2881 |
| 1560 | DPSUB_U_D = 1545, // MipsMSAInstrInfo.td:2886 |
| 1561 | DPSUB_U_H = 1546, // MipsMSAInstrInfo.td:2884 |
| 1562 | DPSUB_U_W = 1547, // MipsMSAInstrInfo.td:2885 |
| 1563 | DPSU_H_QBL = 1548, // MipsDSPInstrInfo.td:1150 |
| 1564 | DPSU_H_QBL_MM = 1549, // MicroMipsDSPInstrInfo.td:466 |
| 1565 | DPSU_H_QBR = 1550, // MipsDSPInstrInfo.td:1151 |
| 1566 | DPSU_H_QBR_MM = 1551, // MicroMipsDSPInstrInfo.td:467 |
| 1567 | DPSX_W_PH = 1552, // MipsDSPInstrInfo.td:1237 |
| 1568 | DPSX_W_PH_MMR2 = 1553, // MicroMipsDSPInstrInfo.td:560 |
| 1569 | DPS_W_PH = 1554, // MipsDSPInstrInfo.td:1233 |
| 1570 | DPS_W_PH_MMR2 = 1555, // MicroMipsDSPInstrInfo.td:555 |
| 1571 | DROTR = 1556, // Mips64InstrInfo.td:190 |
| 1572 | DROTR32 = 1557, // Mips64InstrInfo.td:195 |
| 1573 | DROTRV = 1558, // Mips64InstrInfo.td:193 |
| 1574 | DSBH = 1559, // Mips64InstrInfo.td:370 |
| 1575 | DSDIV = 1560, // Mips64InstrInfo.td:326 |
| 1576 | DSHD = 1561, // Mips64InstrInfo.td:372 |
| 1577 | DSLL = 1562, // Mips64InstrInfo.td:167 |
| 1578 | DSLL32 = 1563, // Mips64InstrInfo.td:182 |
| 1579 | DSLL64_32 = 1564, // Mips64InstrInfo.td:427 |
| 1580 | DSLLV = 1565, // Mips64InstrInfo.td:176 |
| 1581 | DSRA = 1566, // Mips64InstrInfo.td:173 |
| 1582 | DSRA32 = 1567, // Mips64InstrInfo.td:186 |
| 1583 | DSRAV = 1568, // Mips64InstrInfo.td:178 |
| 1584 | DSRL = 1569, // Mips64InstrInfo.td:170 |
| 1585 | DSRL32 = 1570, // Mips64InstrInfo.td:184 |
| 1586 | DSRLV = 1571, // Mips64InstrInfo.td:180 |
| 1587 | DSUB = 1572, // Mips64InstrInfo.td:149 |
| 1588 | DSUBu = 1573, // Mips64InstrInfo.td:147 |
| 1589 | DUDIV = 1574, // Mips64InstrInfo.td:329 |
| 1590 | DVP = 1575, // Mips32r6InstrInfo.td:869 |
| 1591 | DVPE = 1576, // MipsMTInstrInfo.td:96 |
| 1592 | DVP_MMR6 = 1577, // MicroMips32r6InstrInfo.td:1527 |
| 1593 | DivRxRy16 = 1578, // Mips16InstrInfo.td:696 |
| 1594 | DivuRxRy16 = 1579, // Mips16InstrInfo.td:705 |
| 1595 | EHB = 1580, // MipsInstrInfo.td:2492 |
| 1596 | EHB_MM = 1581, // MicroMipsInstrInfo.td:1054 |
| 1597 | EHB_MMR6 = 1582, // MicroMips32r6InstrInfo.td:1294 |
| 1598 | EI = 1583, // MipsInstrInfo.td:2244 |
| 1599 | EI_MM = 1584, // MicroMipsInstrInfo.td:995 |
| 1600 | EI_MMR6 = 1585, // MicroMips32r6InstrInfo.td:1295 |
| 1601 | EMT = 1586, // MipsMTInstrInfo.td:94 |
| 1602 | ERET = 1587, // MipsInstrInfo.td:2239 |
| 1603 | ERETNC = 1588, // MipsInstrInfo.td:2240 |
| 1604 | ERETNC_MMR6 = 1589, // MicroMips32r6InstrInfo.td:1299 |
| 1605 | ERET_MM = 1590, // MicroMipsInstrInfo.td:991 |
| 1606 | ERET_MMR6 = 1591, // MicroMips32r6InstrInfo.td:1297 |
| 1607 | EVP = 1592, // Mips32r6InstrInfo.td:870 |
| 1608 | EVPE = 1593, // MipsMTInstrInfo.td:98 |
| 1609 | EVP_MMR6 = 1594, // MicroMips32r6InstrInfo.td:1528 |
| 1610 | EXT = 1595, // MipsInstrInfo.td:2467 |
| 1611 | EXTP = 1596, // MipsDSPInstrInfo.td:1186 |
| 1612 | EXTPDP = 1597, // MipsDSPInstrInfo.td:1188 |
| 1613 | EXTPDPV = 1598, // MipsDSPInstrInfo.td:1189 |
| 1614 | EXTPDPV_MM = 1599, // MicroMipsDSPInstrInfo.td:454 |
| 1615 | EXTPDP_MM = 1600, // MicroMipsDSPInstrInfo.td:453 |
| 1616 | EXTPV = 1601, // MipsDSPInstrInfo.td:1187 |
| 1617 | EXTPV_MM = 1602, // MicroMipsDSPInstrInfo.td:455 |
| 1618 | EXTP_MM = 1603, // MicroMipsDSPInstrInfo.td:452 |
| 1619 | EXTRV_RS_W = 1604, // MipsDSPInstrInfo.td:1195 |
| 1620 | EXTRV_RS_W_MM = 1605, // MicroMipsDSPInstrInfo.td:462 |
| 1621 | EXTRV_R_W = 1606, // MipsDSPInstrInfo.td:1193 |
| 1622 | EXTRV_R_W_MM = 1607, // MicroMipsDSPInstrInfo.td:461 |
| 1623 | EXTRV_S_H = 1608, // MipsDSPInstrInfo.td:1197 |
| 1624 | EXTRV_S_H_MM = 1609, // MicroMipsDSPInstrInfo.td:463 |
| 1625 | EXTRV_W = 1610, // MipsDSPInstrInfo.td:1191 |
| 1626 | EXTRV_W_MM = 1611, // MicroMipsDSPInstrInfo.td:460 |
| 1627 | EXTR_RS_W = 1612, // MipsDSPInstrInfo.td:1194 |
| 1628 | EXTR_RS_W_MM = 1613, // MicroMipsDSPInstrInfo.td:458 |
| 1629 | EXTR_R_W = 1614, // MipsDSPInstrInfo.td:1192 |
| 1630 | EXTR_R_W_MM = 1615, // MicroMipsDSPInstrInfo.td:457 |
| 1631 | EXTR_S_H = 1616, // MipsDSPInstrInfo.td:1196 |
| 1632 | EXTR_S_H_MM = 1617, // MicroMipsDSPInstrInfo.td:459 |
| 1633 | EXTR_W = 1618, // MipsDSPInstrInfo.td:1190 |
| 1634 | EXTR_W_MM = 1619, // MicroMipsDSPInstrInfo.td:456 |
| 1635 | EXTS = 1620, // Mips64InstrInfo.td:544 |
| 1636 | EXTS32 = 1621, // Mips64InstrInfo.td:546 |
| 1637 | EXT_MM = 1622, // MicroMipsInstrInfo.td:916 |
| 1638 | EXT_MMR6 = 1623, // MicroMips32r6InstrInfo.td:1488 |
| 1639 | FABS_D32 = 1624, // MipsInstrFPU.td:170 |
| 1640 | FABS_D32_MM = 1625, // MicroMipsInstrFPU.td:118 |
| 1641 | FABS_D64 = 1626, // MipsInstrFPU.td:172 |
| 1642 | FABS_D64_MM = 1627, // MicroMipsInstrFPU.td:122 |
| 1643 | FABS_S = 1628, // MipsInstrFPU.td:577 |
| 1644 | FABS_S_MM = 1629, // MicroMipsInstrFPU.td:133 |
| 1645 | FADD_D = 1630, // MipsMSAInstrInfo.td:2889 |
| 1646 | FADD_D32 = 1631, // MipsInstrFPU.td:142 |
| 1647 | FADD_D32_MM = 1632, // MicroMipsInstrFPU.td:15 |
| 1648 | FADD_D64 = 1633, // MipsInstrFPU.td:143 |
| 1649 | FADD_D64_MM = 1634, // MicroMipsInstrFPU.td:20 |
| 1650 | FADD_PS64 = 1635, // MipsInstrFPU.td:502 |
| 1651 | FADD_S = 1636, // MipsInstrFPU.td:722 |
| 1652 | FADD_S_MM = 1637, // MicroMipsInstrFPU.td:26 |
| 1653 | FADD_S_MMR6 = 1638, // MicroMips32r6InstrInfo.td:1371 |
| 1654 | FADD_W = 1639, // MipsMSAInstrInfo.td:2888 |
| 1655 | FCAF_D = 1640, // MipsMSAInstrInfo.td:2892 |
| 1656 | FCAF_W = 1641, // MipsMSAInstrInfo.td:2891 |
| 1657 | FCEQ_D = 1642, // MipsMSAInstrInfo.td:2895 |
| 1658 | FCEQ_W = 1643, // MipsMSAInstrInfo.td:2894 |
| 1659 | FCLASS_D = 1644, // MipsMSAInstrInfo.td:2904 |
| 1660 | FCLASS_W = 1645, // MipsMSAInstrInfo.td:2903 |
| 1661 | FCLE_D = 1646, // MipsMSAInstrInfo.td:2898 |
| 1662 | FCLE_W = 1647, // MipsMSAInstrInfo.td:2897 |
| 1663 | FCLT_D = 1648, // MipsMSAInstrInfo.td:2901 |
| 1664 | FCLT_W = 1649, // MipsMSAInstrInfo.td:2900 |
| 1665 | FCMP_D32 = 1650, // MipsInstrFPU.td:822 |
| 1666 | FCMP_D32_MM = 1651, // MicroMipsInstrFPU.td:65 |
| 1667 | FCMP_D64 = 1652, // MipsInstrFPU.td:831 |
| 1668 | FCMP_S32 = 1653, // MipsInstrFPU.td:814 |
| 1669 | FCMP_S32_MM = 1654, // MicroMipsInstrFPU.td:57 |
| 1670 | FCNE_D = 1655, // MipsMSAInstrInfo.td:2907 |
| 1671 | FCNE_W = 1656, // MipsMSAInstrInfo.td:2906 |
| 1672 | FCOR_D = 1657, // MipsMSAInstrInfo.td:2910 |
| 1673 | FCOR_W = 1658, // MipsMSAInstrInfo.td:2909 |
| 1674 | FCUEQ_D = 1659, // MipsMSAInstrInfo.td:2913 |
| 1675 | FCUEQ_W = 1660, // MipsMSAInstrInfo.td:2912 |
| 1676 | FCULE_D = 1661, // MipsMSAInstrInfo.td:2916 |
| 1677 | FCULE_W = 1662, // MipsMSAInstrInfo.td:2915 |
| 1678 | FCULT_D = 1663, // MipsMSAInstrInfo.td:2919 |
| 1679 | FCULT_W = 1664, // MipsMSAInstrInfo.td:2918 |
| 1680 | FCUNE_D = 1665, // MipsMSAInstrInfo.td:2925 |
| 1681 | FCUNE_W = 1666, // MipsMSAInstrInfo.td:2924 |
| 1682 | FCUN_D = 1667, // MipsMSAInstrInfo.td:2922 |
| 1683 | FCUN_W = 1668, // MipsMSAInstrInfo.td:2921 |
| 1684 | FDIV_D = 1669, // MipsMSAInstrInfo.td:2928 |
| 1685 | FDIV_D32 = 1670, // MipsInstrFPU.td:142 |
| 1686 | FDIV_D32_MM = 1671, // MicroMipsInstrFPU.td:15 |
| 1687 | FDIV_D64 = 1672, // MipsInstrFPU.td:143 |
| 1688 | FDIV_D64_MM = 1673, // MicroMipsInstrFPU.td:20 |
| 1689 | FDIV_S = 1674, // MipsInstrFPU.td:726 |
| 1690 | FDIV_S_MM = 1675, // MicroMipsInstrFPU.td:28 |
| 1691 | FDIV_S_MMR6 = 1676, // MicroMips32r6InstrInfo.td:1377 |
| 1692 | FDIV_W = 1677, // MipsMSAInstrInfo.td:2927 |
| 1693 | FEXDO_H = 1678, // MipsMSAInstrInfo.td:2930 |
| 1694 | FEXDO_W = 1679, // MipsMSAInstrInfo.td:2931 |
| 1695 | FEXP2_D = 1680, // MipsMSAInstrInfo.td:2934 |
| 1696 | FEXP2_W = 1681, // MipsMSAInstrInfo.td:2933 |
| 1697 | FEXUPL_D = 1682, // MipsMSAInstrInfo.td:2939 |
| 1698 | FEXUPL_W = 1683, // MipsMSAInstrInfo.td:2938 |
| 1699 | FEXUPR_D = 1684, // MipsMSAInstrInfo.td:2942 |
| 1700 | FEXUPR_W = 1685, // MipsMSAInstrInfo.td:2941 |
| 1701 | FFINT_S_D = 1686, // MipsMSAInstrInfo.td:2945 |
| 1702 | FFINT_S_W = 1687, // MipsMSAInstrInfo.td:2944 |
| 1703 | FFINT_U_D = 1688, // MipsMSAInstrInfo.td:2948 |
| 1704 | FFINT_U_W = 1689, // MipsMSAInstrInfo.td:2947 |
| 1705 | FFQL_D = 1690, // MipsMSAInstrInfo.td:2951 |
| 1706 | FFQL_W = 1691, // MipsMSAInstrInfo.td:2950 |
| 1707 | FFQR_D = 1692, // MipsMSAInstrInfo.td:2954 |
| 1708 | FFQR_W = 1693, // MipsMSAInstrInfo.td:2953 |
| 1709 | FILL_B = 1694, // MipsMSAInstrInfo.td:2956 |
| 1710 | FILL_D = 1695, // MipsMSAInstrInfo.td:2959 |
| 1711 | FILL_H = 1696, // MipsMSAInstrInfo.td:2957 |
| 1712 | FILL_W = 1697, // MipsMSAInstrInfo.td:2958 |
| 1713 | FLOG2_D = 1698, // MipsMSAInstrInfo.td:2964 |
| 1714 | FLOG2_W = 1699, // MipsMSAInstrInfo.td:2963 |
| 1715 | FLOOR_L_D64 = 1700, // MipsInstrFPU.td:477 |
| 1716 | FLOOR_L_D_MMR6 = 1701, // MicroMips32r6InstrInfo.td:1431 |
| 1717 | FLOOR_L_S = 1702, // MipsInstrFPU.td:475 |
| 1718 | FLOOR_L_S_MMR6 = 1703, // MicroMips32r6InstrInfo.td:1429 |
| 1719 | FLOOR_W_D32 = 1704, // MipsInstrFPU.td:179 |
| 1720 | FLOOR_W_D64 = 1705, // MipsInstrFPU.td:180 |
| 1721 | FLOOR_W_D_MMR6 = 1706, // MicroMips32r6InstrInfo.td:1435 |
| 1722 | FLOOR_W_MM = 1707, // MicroMipsInstrFPU.td:93 |
| 1723 | FLOOR_W_S = 1708, // MipsInstrFPU.td:423 |
| 1724 | FLOOR_W_S_MM = 1709, // MicroMipsInstrFPU.td:230 |
| 1725 | FLOOR_W_S_MMR6 = 1710, // MicroMips32r6InstrInfo.td:1433 |
| 1726 | FMADD_D = 1711, // MipsMSAInstrInfo.td:2967 |
| 1727 | FMADD_W = 1712, // MipsMSAInstrInfo.td:2966 |
| 1728 | FMAX_A_D = 1713, // MipsMSAInstrInfo.td:2973 |
| 1729 | FMAX_A_W = 1714, // MipsMSAInstrInfo.td:2972 |
| 1730 | FMAX_D = 1715, // MipsMSAInstrInfo.td:2970 |
| 1731 | FMAX_W = 1716, // MipsMSAInstrInfo.td:2969 |
| 1732 | FMIN_A_D = 1717, // MipsMSAInstrInfo.td:2979 |
| 1733 | FMIN_A_W = 1718, // MipsMSAInstrInfo.td:2978 |
| 1734 | FMIN_D = 1719, // MipsMSAInstrInfo.td:2976 |
| 1735 | FMIN_W = 1720, // MipsMSAInstrInfo.td:2975 |
| 1736 | FMOV_D32 = 1721, // MipsInstrFPU.td:170 |
| 1737 | FMOV_D32_MM = 1722, // MicroMipsInstrFPU.td:118 |
| 1738 | FMOV_D64 = 1723, // MipsInstrFPU.td:172 |
| 1739 | FMOV_D64_MM = 1724, // MicroMipsInstrFPU.td:122 |
| 1740 | FMOV_D_MMR6 = 1725, // MicroMips32r6InstrInfo.td:1391 |
| 1741 | FMOV_S = 1726, // MipsInstrFPU.td:649 |
| 1742 | FMOV_S_MM = 1727, // MicroMipsInstrFPU.td:138 |
| 1743 | FMOV_S_MMR6 = 1728, // MicroMips32r6InstrInfo.td:1389 |
| 1744 | FMSUB_D = 1729, // MipsMSAInstrInfo.td:2982 |
| 1745 | FMSUB_W = 1730, // MipsMSAInstrInfo.td:2981 |
| 1746 | FMUL_D = 1731, // MipsMSAInstrInfo.td:2985 |
| 1747 | FMUL_D32 = 1732, // MipsInstrFPU.td:142 |
| 1748 | FMUL_D32_MM = 1733, // MicroMipsInstrFPU.td:15 |
| 1749 | FMUL_D64 = 1734, // MipsInstrFPU.td:143 |
| 1750 | FMUL_D64_MM = 1735, // MicroMipsInstrFPU.td:20 |
| 1751 | FMUL_PS64 = 1736, // MipsInstrFPU.td:505 |
| 1752 | FMUL_S = 1737, // MipsInstrFPU.td:730 |
| 1753 | FMUL_S_MM = 1738, // MicroMipsInstrFPU.td:30 |
| 1754 | FMUL_S_MMR6 = 1739, // MicroMips32r6InstrInfo.td:1375 |
| 1755 | FMUL_W = 1740, // MipsMSAInstrInfo.td:2984 |
| 1756 | FNEG_D32 = 1741, // MipsInstrFPU.td:170 |
| 1757 | FNEG_D32_MM = 1742, // MicroMipsInstrFPU.td:118 |
| 1758 | FNEG_D64 = 1743, // MipsInstrFPU.td:172 |
| 1759 | FNEG_D64_MM = 1744, // MicroMipsInstrFPU.td:122 |
| 1760 | FNEG_S = 1745, // MipsInstrFPU.td:588 |
| 1761 | FNEG_S_MM = 1746, // MicroMipsInstrFPU.td:142 |
| 1762 | FNEG_S_MMR6 = 1747, // MicroMips32r6InstrInfo.td:1393 |
| 1763 | FORK = 1748, // MipsMTInstrInfo.td:100 |
| 1764 | FRCP_D = 1749, // MipsMSAInstrInfo.td:2991 |
| 1765 | FRCP_W = 1750, // MipsMSAInstrInfo.td:2990 |
| 1766 | FRINT_D = 1751, // MipsMSAInstrInfo.td:2988 |
| 1767 | FRINT_W = 1752, // MipsMSAInstrInfo.td:2987 |
| 1768 | FRSQRT_D = 1753, // MipsMSAInstrInfo.td:2994 |
| 1769 | FRSQRT_W = 1754, // MipsMSAInstrInfo.td:2993 |
| 1770 | FSAF_D = 1755, // MipsMSAInstrInfo.td:2997 |
| 1771 | FSAF_W = 1756, // MipsMSAInstrInfo.td:2996 |
| 1772 | FSEQ_D = 1757, // MipsMSAInstrInfo.td:3000 |
| 1773 | FSEQ_W = 1758, // MipsMSAInstrInfo.td:2999 |
| 1774 | FSLE_D = 1759, // MipsMSAInstrInfo.td:3003 |
| 1775 | FSLE_W = 1760, // MipsMSAInstrInfo.td:3002 |
| 1776 | FSLT_D = 1761, // MipsMSAInstrInfo.td:3006 |
| 1777 | FSLT_W = 1762, // MipsMSAInstrInfo.td:3005 |
| 1778 | FSNE_D = 1763, // MipsMSAInstrInfo.td:3009 |
| 1779 | FSNE_W = 1764, // MipsMSAInstrInfo.td:3008 |
| 1780 | FSOR_D = 1765, // MipsMSAInstrInfo.td:3012 |
| 1781 | FSOR_W = 1766, // MipsMSAInstrInfo.td:3011 |
| 1782 | FSQRT_D = 1767, // MipsMSAInstrInfo.td:3015 |
| 1783 | FSQRT_D32 = 1768, // MipsInstrFPU.td:170 |
| 1784 | FSQRT_D32_MM = 1769, // MicroMipsInstrFPU.td:118 |
| 1785 | FSQRT_D64 = 1770, // MipsInstrFPU.td:172 |
| 1786 | FSQRT_D64_MM = 1771, // MicroMipsInstrFPU.td:122 |
| 1787 | FSQRT_S = 1772, // MipsInstrFPU.td:595 |
| 1788 | FSQRT_S_MM = 1773, // MicroMipsInstrFPU.td:239 |
| 1789 | FSQRT_W = 1774, // MipsMSAInstrInfo.td:3014 |
| 1790 | FSUB_D = 1775, // MipsMSAInstrInfo.td:3018 |
| 1791 | FSUB_D32 = 1776, // MipsInstrFPU.td:142 |
| 1792 | FSUB_D32_MM = 1777, // MicroMipsInstrFPU.td:15 |
| 1793 | FSUB_D64 = 1778, // MipsInstrFPU.td:143 |
| 1794 | FSUB_D64_MM = 1779, // MicroMipsInstrFPU.td:20 |
| 1795 | FSUB_PS64 = 1780, // MipsInstrFPU.td:508 |
| 1796 | FSUB_S = 1781, // MipsInstrFPU.td:734 |
| 1797 | FSUB_S_MM = 1782, // MicroMipsInstrFPU.td:32 |
| 1798 | FSUB_S_MMR6 = 1783, // MicroMips32r6InstrInfo.td:1373 |
| 1799 | FSUB_W = 1784, // MipsMSAInstrInfo.td:3017 |
| 1800 | FSUEQ_D = 1785, // MipsMSAInstrInfo.td:3021 |
| 1801 | FSUEQ_W = 1786, // MipsMSAInstrInfo.td:3020 |
| 1802 | FSULE_D = 1787, // MipsMSAInstrInfo.td:3024 |
| 1803 | FSULE_W = 1788, // MipsMSAInstrInfo.td:3023 |
| 1804 | FSULT_D = 1789, // MipsMSAInstrInfo.td:3027 |
| 1805 | FSULT_W = 1790, // MipsMSAInstrInfo.td:3026 |
| 1806 | FSUNE_D = 1791, // MipsMSAInstrInfo.td:3033 |
| 1807 | FSUNE_W = 1792, // MipsMSAInstrInfo.td:3032 |
| 1808 | FSUN_D = 1793, // MipsMSAInstrInfo.td:3030 |
| 1809 | FSUN_W = 1794, // MipsMSAInstrInfo.td:3029 |
| 1810 | FTINT_S_D = 1795, // MipsMSAInstrInfo.td:3036 |
| 1811 | FTINT_S_W = 1796, // MipsMSAInstrInfo.td:3035 |
| 1812 | FTINT_U_D = 1797, // MipsMSAInstrInfo.td:3039 |
| 1813 | FTINT_U_W = 1798, // MipsMSAInstrInfo.td:3038 |
| 1814 | FTQ_H = 1799, // MipsMSAInstrInfo.td:3041 |
| 1815 | FTQ_W = 1800, // MipsMSAInstrInfo.td:3042 |
| 1816 | FTRUNC_S_D = 1801, // MipsMSAInstrInfo.td:3045 |
| 1817 | FTRUNC_S_W = 1802, // MipsMSAInstrInfo.td:3044 |
| 1818 | FTRUNC_U_D = 1803, // MipsMSAInstrInfo.td:3048 |
| 1819 | FTRUNC_U_W = 1804, // MipsMSAInstrInfo.td:3047 |
| 1820 | GINVI = 1805, // Mips32r6InstrInfo.td:946 |
| 1821 | GINVI_MMR6 = 1806, // MicroMips32r6InstrInfo.td:1301 |
| 1822 | GINVT = 1807, // Mips32r6InstrInfo.td:947 |
| 1823 | GINVT_MMR6 = 1808, // MicroMips32r6InstrInfo.td:1303 |
| 1824 | HADD_S_D = 1809, // MipsMSAInstrInfo.td:3066 |
| 1825 | HADD_S_H = 1810, // MipsMSAInstrInfo.td:3064 |
| 1826 | HADD_S_W = 1811, // MipsMSAInstrInfo.td:3065 |
| 1827 | HADD_U_D = 1812, // MipsMSAInstrInfo.td:3070 |
| 1828 | HADD_U_H = 1813, // MipsMSAInstrInfo.td:3068 |
| 1829 | HADD_U_W = 1814, // MipsMSAInstrInfo.td:3069 |
| 1830 | HSUB_S_D = 1815, // MipsMSAInstrInfo.td:3074 |
| 1831 | HSUB_S_H = 1816, // MipsMSAInstrInfo.td:3072 |
| 1832 | HSUB_S_W = 1817, // MipsMSAInstrInfo.td:3073 |
| 1833 | HSUB_U_D = 1818, // MipsMSAInstrInfo.td:3078 |
| 1834 | HSUB_U_H = 1819, // MipsMSAInstrInfo.td:3076 |
| 1835 | HSUB_U_W = 1820, // MipsMSAInstrInfo.td:3077 |
| 1836 | HYPCALL = 1821, // MipsInstrInfo.td:2701 |
| 1837 | HYPCALL_MM = 1822, // MicroMipsInstrInfo.td:1128 |
| 1838 | ILVEV_B = 1823, // MipsMSAInstrInfo.td:3080 |
| 1839 | ILVEV_D = 1824, // MipsMSAInstrInfo.td:3083 |
| 1840 | ILVEV_H = 1825, // MipsMSAInstrInfo.td:3081 |
| 1841 | ILVEV_W = 1826, // MipsMSAInstrInfo.td:3082 |
| 1842 | ILVL_B = 1827, // MipsMSAInstrInfo.td:3085 |
| 1843 | ILVL_D = 1828, // MipsMSAInstrInfo.td:3088 |
| 1844 | ILVL_H = 1829, // MipsMSAInstrInfo.td:3086 |
| 1845 | ILVL_W = 1830, // MipsMSAInstrInfo.td:3087 |
| 1846 | ILVOD_B = 1831, // MipsMSAInstrInfo.td:3090 |
| 1847 | ILVOD_D = 1832, // MipsMSAInstrInfo.td:3093 |
| 1848 | ILVOD_H = 1833, // MipsMSAInstrInfo.td:3091 |
| 1849 | ILVOD_W = 1834, // MipsMSAInstrInfo.td:3092 |
| 1850 | ILVR_B = 1835, // MipsMSAInstrInfo.td:3095 |
| 1851 | ILVR_D = 1836, // MipsMSAInstrInfo.td:3098 |
| 1852 | ILVR_H = 1837, // MipsMSAInstrInfo.td:3096 |
| 1853 | ILVR_W = 1838, // MipsMSAInstrInfo.td:3097 |
| 1854 | INS = 1839, // MipsInstrInfo.td:2470 |
| 1855 | INSERT_B = 1840, // MipsMSAInstrInfo.td:3100 |
| 1856 | INSERT_D = 1841, // MipsMSAInstrInfo.td:3103 |
| 1857 | INSERT_H = 1842, // MipsMSAInstrInfo.td:3101 |
| 1858 | INSERT_W = 1843, // MipsMSAInstrInfo.td:3102 |
| 1859 | INSV = 1844, // MipsDSPInstrInfo.td:1185 |
| 1860 | INSVE_B = 1845, // MipsMSAInstrInfo.td:3111 |
| 1861 | INSVE_D = 1846, // MipsMSAInstrInfo.td:3114 |
| 1862 | INSVE_H = 1847, // MipsMSAInstrInfo.td:3112 |
| 1863 | INSVE_W = 1848, // MipsMSAInstrInfo.td:3113 |
| 1864 | INSV_MM = 1849, // MicroMipsDSPInstrInfo.td:412 |
| 1865 | INS_MM = 1850, // MicroMipsInstrInfo.td:919 |
| 1866 | INS_MMR6 = 1851, // MicroMips32r6InstrInfo.td:1489 |
| 1867 | J = 1852, // MipsInstrInfo.td:2265 |
| 1868 | JAL = 1853, // MipsInstrInfo.td:2297 |
| 1869 | JALR = 1854, // MipsInstrInfo.td:2302 |
| 1870 | JALR16_MM = 1855, // MicroMipsInstrInfo.td:659 |
| 1871 | JALR64 = 1856, // Mips64InstrInfo.td:267 |
| 1872 | JALRC16_MMR6 = 1857, // MicroMips32r6InstrInfo.td:1306 |
| 1873 | JALRC_HB_MMR6 = 1858, // MicroMips32r6InstrInfo.td:1486 |
| 1874 | JALRC_MMR6 = 1859, // MicroMips32r6InstrInfo.td:1490 |
| 1875 | JALRS16_MM = 1860, // MicroMipsInstrInfo.td:661 |
| 1876 | JALRS_MM = 1861, // MicroMipsInstrInfo.td:949 |
| 1877 | JALR_HB = 1862, // MipsInstrInfo.td:2542 |
| 1878 | JALR_HB64 = 1863, // Mips64InstrInfo.td:290 |
| 1879 | JALR_HB_MM = 1864, // MicroMipsInstrInfo.td:943 |
| 1880 | JALR_MM = 1865, // MicroMipsInstrInfo.td:938 |
| 1881 | JALS_MM = 1866, // MicroMipsInstrInfo.td:947 |
| 1882 | JALX = 1867, // MipsInstrInfo.td:2307 |
| 1883 | JALX_MM = 1868, // MicroMipsInstrInfo.td:933 |
| 1884 | JAL_MM = 1869, // MicroMipsInstrInfo.td:928 |
| 1885 | JIALC = 1870, // Mips32r6InstrInfo.td:872 |
| 1886 | JIALC64 = 1871, // Mips64r6InstrInfo.td:165 |
| 1887 | JIALC_MMR6 = 1872, // MicroMips32r6InstrInfo.td:1308 |
| 1888 | JIC = 1873, // Mips32r6InstrInfo.td:873 |
| 1889 | JIC64 = 1874, // Mips64r6InstrInfo.td:166 |
| 1890 | JIC_MMR6 = 1875, // MicroMips32r6InstrInfo.td:1309 |
| 1891 | JR = 1876, // MipsInstrInfo.td:2269 |
| 1892 | JR16_MM = 1877, // MicroMipsInstrInfo.td:667 |
| 1893 | JR64 = 1878, // Mips64InstrInfo.td:264 |
| 1894 | JRADDIUSP = 1879, // MicroMipsInstrInfo.td:665 |
| 1895 | JRC16_MM = 1880, // MicroMipsInstrInfo.td:663 |
| 1896 | JRC16_MMR6 = 1881, // MicroMips32r6InstrInfo.td:1310 |
| 1897 | JRCADDIUSP_MMR6 = 1882, // MicroMips32r6InstrInfo.td:1311 |
| 1898 | JR_HB = 1883, // MipsInstrInfo.td:2540 |
| 1899 | JR_HB64 = 1884, // Mips64InstrInfo.td:289 |
| 1900 | JR_HB64_R6 = 1885, // Mips64r6InstrInfo.td:155 |
| 1901 | JR_HB_MM = 1886, // MicroMipsInstrInfo.td:941 |
| 1902 | JR_HB_R6 = 1887, // Mips32r6InstrInfo.td:874 |
| 1903 | JR_MM = 1888, // MicroMipsInstrInfo.td:936 |
| 1904 | J_MM = 1889, // MicroMipsInstrInfo.td:925 |
| 1905 | Jal16 = 1890, // Mips16InstrInfo.td:715 |
| 1906 | JalB16 = 1891, // Mips16InstrInfo.td:721 |
| 1907 | JrRa16 = 1892, // Mips16InstrInfo.td:734 |
| 1908 | JrcRa16 = 1893, // Mips16InstrInfo.td:743 |
| 1909 | JrcRx16 = 1894, // Mips16InstrInfo.td:751 |
| 1910 | JumpLinkReg16 = 1895, // Mips16InstrInfo.td:1360 |
| 1911 | LB = 1896, // MipsInstrInfo.td:2133 |
| 1912 | LB64 = 1897, // Mips64InstrInfo.td:202 |
| 1913 | LBE = 1898, // MipsEVAInstrInfo.td:175 |
| 1914 | LBE_MM = 1899, // MicroMipsInstrInfo.td:807 |
| 1915 | LBU16_MM = 1900, // MicroMipsInstrInfo.td:620 |
| 1916 | LBUX = 1901, // MipsDSPInstrInfo.td:1181 |
| 1917 | LBUX_MM = 1902, // MicroMipsDSPInstrInfo.td:477 |
| 1918 | LBU_MMR6 = 1903, // MicroMips32r6InstrInfo.td:1352 |
| 1919 | LB_MM = 1904, // MicroMipsInstrInfo.td:788 |
| 1920 | LB_MMR6 = 1905, // MicroMips32r6InstrInfo.td:1351 |
| 1921 | LBu = 1906, // MipsInstrInfo.td:2135 |
| 1922 | LBu64 = 1907, // Mips64InstrInfo.td:203 |
| 1923 | LBuE = 1908, // MipsEVAInstrInfo.td:176 |
| 1924 | LBuE_MM = 1909, // MicroMipsInstrInfo.td:809 |
| 1925 | LBu_MM = 1910, // MicroMipsInstrInfo.td:790 |
| 1926 | LD = 1911, // Mips64InstrInfo.td:217 |
| 1927 | LDC1 = 1912, // MipsInstrFPU.td:673 |
| 1928 | LDC164 = 1913, // MipsInstrFPU.td:664 |
| 1929 | LDC1_D64_MMR6 = 1914, // MicroMips32r6InstrInfo.td:1538 |
| 1930 | LDC1_MM_D32 = 1915, // MicroMipsInstrFPU.td:289 |
| 1931 | LDC1_MM_D64 = 1916, // MicroMipsInstrFPU.td:304 |
| 1932 | LDC2 = 1917, // MipsInstrInfo.td:2167 |
| 1933 | LDC2_MMR6 = 1918, // MicroMips32r6InstrInfo.td:1545 |
| 1934 | LDC2_R6 = 1919, // Mips32r6InstrInfo.td:876 |
| 1935 | LDC3 = 1920, // MipsInstrInfo.td:2182 |
| 1936 | LDI_B = 1921, // MipsMSAInstrInfo.td:3139 |
| 1937 | LDI_D = 1922, // MipsMSAInstrInfo.td:3142 |
| 1938 | LDI_H = 1923, // MipsMSAInstrInfo.td:3140 |
| 1939 | LDI_W = 1924, // MipsMSAInstrInfo.td:3141 |
| 1940 | LDL = 1925, // Mips64InstrInfo.td:237 |
| 1941 | LDPC = 1926, // Mips64r6InstrInfo.td:149 |
| 1942 | LDR = 1927, // Mips64InstrInfo.td:239 |
| 1943 | LDXC1 = 1928, // MipsInstrFPU.td:690 |
| 1944 | LDXC164 = 1929, // MipsInstrFPU.td:697 |
| 1945 | LD_B = 1930, // MipsMSAInstrInfo.td:3134 |
| 1946 | LD_D = 1931, // MipsMSAInstrInfo.td:3137 |
| 1947 | LD_H = 1932, // MipsMSAInstrInfo.td:3135 |
| 1948 | LD_W = 1933, // MipsMSAInstrInfo.td:3136 |
| 1949 | LEA_ADDiu = 1934, // MipsInstrInfo.td:2428 |
| 1950 | LEA_ADDiu64 = 1935, // Mips64InstrInfo.td:375 |
| 1951 | LEA_ADDiu_MM = 1936, // MicroMipsInstrInfo.td:722 |
| 1952 | LH = 1937, // MipsInstrInfo.td:2137 |
| 1953 | LH64 = 1938, // Mips64InstrInfo.td:204 |
| 1954 | LHE = 1939, // MipsEVAInstrInfo.td:177 |
| 1955 | LHE_MM = 1940, // MicroMipsInstrInfo.td:811 |
| 1956 | LHU16_MM = 1941, // MicroMipsInstrInfo.td:622 |
| 1957 | LHX = 1942, // MipsDSPInstrInfo.td:1180 |
| 1958 | LHX_MM = 1943, // MicroMipsDSPInstrInfo.td:478 |
| 1959 | LH_MM = 1944, // MicroMipsInstrInfo.td:792 |
| 1960 | LHu = 1945, // MipsInstrInfo.td:2139 |
| 1961 | LHu64 = 1946, // Mips64InstrInfo.td:205 |
| 1962 | LHuE = 1947, // MipsEVAInstrInfo.td:178 |
| 1963 | LHuE_MM = 1948, // MicroMipsInstrInfo.td:813 |
| 1964 | LHu_MM = 1949, // MicroMipsInstrInfo.td:794 |
| 1965 | LI16_MM = 1950, // MicroMipsInstrInfo.td:657 |
| 1966 | LI16_MMR6 = 1951, // MicroMips32r6InstrInfo.td:1474 |
| 1967 | LL = 1952, // MipsInstrInfo.td:2254 |
| 1968 | LL64 = 1953, // Mips64InstrInfo.td:256 |
| 1969 | LL64_R6 = 1954, // Mips64r6InstrInfo.td:159 |
| 1970 | LLD = 1955, // Mips64InstrInfo.td:248 |
| 1971 | LLD_R6 = 1956, // Mips64r6InstrInfo.td:147 |
| 1972 | LLE = 1957, // MipsEVAInstrInfo.td:191 |
| 1973 | LLE_MM = 1958, // MicroMipsInstrInfo.td:1034 |
| 1974 | LL_MM = 1959, // MicroMipsInstrInfo.td:1029 |
| 1975 | LL_MMR6 = 1960, // MicroMips32r6InstrInfo.td:1549 |
| 1976 | LL_R6 = 1961, // Mips32r6InstrInfo.td:877 |
| 1977 | LSA = 1962, // MipsMSAInstrInfo.td:3144 |
| 1978 | LSA_MMR6 = 1963, // MicroMips32r6InstrInfo.td:1313 |
| 1979 | LSA_R6 = 1964, // Mips32r6InstrInfo.td:879 |
| 1980 | LUI_MMR6 = 1965, // MicroMips32r6InstrInfo.td:1457 |
| 1981 | LUXC1 = 1966, // MipsInstrFPU.td:706 |
| 1982 | LUXC164 = 1967, // MipsInstrFPU.td:714 |
| 1983 | LUXC1_MM = 1968, // MicroMipsInstrFPU.td:51 |
| 1984 | LUi = 1969, // MipsInstrInfo.td:2075 |
| 1985 | LUi64 = 1970, // Mips64InstrInfo.td:138 |
| 1986 | LUi_MM = 1971, // MicroMipsInstrInfo.td:719 |
| 1987 | LW = 1972, // MipsInstrInfo.td:2141 |
| 1988 | LW16_MM = 1973, // MicroMipsInstrInfo.td:624 |
| 1989 | LW64 = 1974, // Mips64InstrInfo.td:206 |
| 1990 | LWC1 = 1975, // MipsInstrFPU.td:657 |
| 1991 | LWC1_MM = 1976, // MicroMipsInstrFPU.td:297 |
| 1992 | LWC2 = 1977, // MipsInstrInfo.td:2163 |
| 1993 | LWC2_MMR6 = 1978, // MicroMips32r6InstrInfo.td:1547 |
| 1994 | LWC2_R6 = 1979, // Mips32r6InstrInfo.td:881 |
| 1995 | LWC3 = 1980, // MipsInstrInfo.td:2174 |
| 1996 | LWDSP = 1981, // MipsDSPInstrInfo.td:1267 |
| 1997 | LWDSP_MM = 1982, // MicroMipsDSPInstrInfo.td:392 |
| 1998 | LWE = 1983, // MipsEVAInstrInfo.td:179 |
| 1999 | LWE_MM = 1984, // MicroMipsInstrInfo.td:815 |
| 2000 | LWGP_MM = 1985, // MicroMipsInstrInfo.td:635 |
| 2001 | LWL = 1986, // MipsInstrInfo.td:2153 |
| 2002 | LWL64 = 1987, // Mips64InstrInfo.td:227 |
| 2003 | LWLE = 1988, // MipsEVAInstrInfo.td:185 |
| 2004 | LWLE_MM = 1989, // MicroMipsInstrInfo.td:823 |
| 2005 | LWL_MM = 1990, // MicroMipsInstrInfo.td:841 |
| 2006 | LWM16_MM = 1991, // MicroMipsInstrInfo.td:687 |
| 2007 | LWM16_MMR6 = 1992, // MicroMips32r6InstrInfo.td:1315 |
| 2008 | LWM32_MM = 1993, // MicroMipsInstrInfo.td:852 |
| 2009 | LWPC = 1994, // Mips32r6InstrInfo.td:883 |
| 2010 | LWPC_MMR6 = 1995, // MicroMips32r6InstrInfo.td:1314 |
| 2011 | LWP_MM = 1996, // MicroMipsInstrInfo.td:856 |
| 2012 | LWR = 1997, // MipsInstrInfo.td:2155 |
| 2013 | LWR64 = 1998, // Mips64InstrInfo.td:229 |
| 2014 | LWRE = 1999, // MipsEVAInstrInfo.td:186 |
| 2015 | LWRE_MM = 2000, // MicroMipsInstrInfo.td:826 |
| 2016 | LWR_MM = 2001, // MicroMipsInstrInfo.td:843 |
| 2017 | LWSP_MM = 2002, // MicroMipsInstrInfo.td:637 |
| 2018 | LWUPC = 2003, // Mips64r6InstrInfo.td:150 |
| 2019 | LWU_MM = 2004, // MicroMipsInstrInfo.td:1113 |
| 2020 | LWX = 2005, // MipsDSPInstrInfo.td:1179 |
| 2021 | LWXC1 = 2006, // MipsInstrFPU.td:684 |
| 2022 | LWXC1_MM = 2007, // MicroMipsInstrFPU.td:46 |
| 2023 | LWXS_MM = 2008, // MicroMipsInstrInfo.td:837 |
| 2024 | LWX_MM = 2009, // MicroMipsDSPInstrInfo.td:479 |
| 2025 | LW_MM = 2010, // MicroMipsInstrInfo.td:796 |
| 2026 | LW_MMR6 = 2011, // MicroMips32r6InstrInfo.td:1456 |
| 2027 | LWu = 2012, // Mips64InstrInfo.td:215 |
| 2028 | LbRxRyOffMemX16 = 2013, // Mips16InstrInfo.td:762 |
| 2029 | LbuRxRyOffMemX16 = 2014, // Mips16InstrInfo.td:771 |
| 2030 | LhRxRyOffMemX16 = 2015, // Mips16InstrInfo.td:781 |
| 2031 | LhuRxRyOffMemX16 = 2016, // Mips16InstrInfo.td:790 |
| 2032 | LiRxImm16 = 2017, // Mips16InstrInfo.td:800 |
| 2033 | LiRxImmAlignX16 = 2018, // Mips16InstrInfo.td:809 |
| 2034 | LiRxImmX16 = 2019, // Mips16InstrInfo.td:807 |
| 2035 | LwRxPcTcp16 = 2020, // Mips16InstrInfo.td:829 |
| 2036 | LwRxPcTcpX16 = 2021, // Mips16InstrInfo.td:831 |
| 2037 | LwRxRyOffMemX16 = 2022, // Mips16InstrInfo.td:818 |
| 2038 | LwRxSpImmX16 = 2023, // Mips16InstrInfo.td:827 |
| 2039 | MADD = 2024, // MipsInstrInfo.td:2432 |
| 2040 | MADDF_D = 2025, // Mips32r6InstrInfo.td:888 |
| 2041 | MADDF_D_MMR6 = 2026, // MicroMips32r6InstrInfo.td:1381 |
| 2042 | MADDF_S = 2027, // Mips32r6InstrInfo.td:887 |
| 2043 | MADDF_S_MMR6 = 2028, // MicroMips32r6InstrInfo.td:1379 |
| 2044 | MADDR_Q_H = 2029, // MipsMSAInstrInfo.td:3150 |
| 2045 | MADDR_Q_W = 2030, // MipsMSAInstrInfo.td:3151 |
| 2046 | MADDU = 2031, // MipsInstrInfo.td:2434 |
| 2047 | MADDU_DSP = 2032, // MipsDSPInstrInfo.td:1159 |
| 2048 | MADDU_DSP_MM = 2033, // MicroMipsDSPInstrInfo.td:414 |
| 2049 | MADDU_MM = 2034, // MicroMipsInstrInfo.td:893 |
| 2050 | MADDV_B = 2035, // MipsMSAInstrInfo.td:3153 |
| 2051 | MADDV_D = 2036, // MipsMSAInstrInfo.td:3156 |
| 2052 | MADDV_H = 2037, // MipsMSAInstrInfo.td:3154 |
| 2053 | MADDV_W = 2038, // MipsMSAInstrInfo.td:3155 |
| 2054 | MADD_D32 = 2039, // MipsInstrFPU.td:746 |
| 2055 | MADD_D32_MM = 2040, // MicroMipsInstrFPU.td:210 |
| 2056 | MADD_D64 = 2041, // MipsInstrFPU.td:752 |
| 2057 | MADD_DSP = 2042, // MipsDSPInstrInfo.td:1158 |
| 2058 | MADD_DSP_MM = 2043, // MicroMipsDSPInstrInfo.td:413 |
| 2059 | MADD_MM = 2044, // MicroMipsInstrInfo.td:891 |
| 2060 | MADD_Q_H = 2045, // MipsMSAInstrInfo.td:3147 |
| 2061 | MADD_Q_W = 2046, // MipsMSAInstrInfo.td:3148 |
| 2062 | MADD_S = 2047, // MipsInstrFPU.td:741 |
| 2063 | MADD_S_MM = 2048, // MicroMipsInstrFPU.td:206 |
| 2064 | MAQ_SA_W_PHL = 2049, // MipsDSPInstrInfo.td:1142 |
| 2065 | MAQ_SA_W_PHL_MM = 2050, // MicroMipsDSPInstrInfo.td:481 |
| 2066 | MAQ_SA_W_PHR = 2051, // MipsDSPInstrInfo.td:1143 |
| 2067 | MAQ_SA_W_PHR_MM = 2052, // MicroMipsDSPInstrInfo.td:483 |
| 2068 | MAQ_S_W_PHL = 2053, // MipsDSPInstrInfo.td:1140 |
| 2069 | MAQ_S_W_PHL_MM = 2054, // MicroMipsDSPInstrInfo.td:480 |
| 2070 | MAQ_S_W_PHR = 2055, // MipsDSPInstrInfo.td:1141 |
| 2071 | MAQ_S_W_PHR_MM = 2056, // MicroMipsDSPInstrInfo.td:482 |
| 2072 | MAXA_D = 2057, // Mips32r6InstrInfo.td:893 |
| 2073 | MAXA_D_MMR6 = 2058, // MicroMips32r6InstrInfo.td:1403 |
| 2074 | MAXA_S = 2059, // Mips32r6InstrInfo.td:894 |
| 2075 | MAXA_S_MMR6 = 2060, // MicroMips32r6InstrInfo.td:1401 |
| 2076 | MAXI_S_B = 2061, // MipsMSAInstrInfo.td:3173 |
| 2077 | MAXI_S_D = 2062, // MipsMSAInstrInfo.td:3176 |
| 2078 | MAXI_S_H = 2063, // MipsMSAInstrInfo.td:3174 |
| 2079 | MAXI_S_W = 2064, // MipsMSAInstrInfo.td:3175 |
| 2080 | MAXI_U_B = 2065, // MipsMSAInstrInfo.td:3178 |
| 2081 | MAXI_U_D = 2066, // MipsMSAInstrInfo.td:3181 |
| 2082 | MAXI_U_H = 2067, // MipsMSAInstrInfo.td:3179 |
| 2083 | MAXI_U_W = 2068, // MipsMSAInstrInfo.td:3180 |
| 2084 | MAX_A_B = 2069, // MipsMSAInstrInfo.td:3158 |
| 2085 | MAX_A_D = 2070, // MipsMSAInstrInfo.td:3161 |
| 2086 | MAX_A_H = 2071, // MipsMSAInstrInfo.td:3159 |
| 2087 | MAX_A_W = 2072, // MipsMSAInstrInfo.td:3160 |
| 2088 | MAX_D = 2073, // Mips32r6InstrInfo.td:895 |
| 2089 | MAX_D_MMR6 = 2074, // MicroMips32r6InstrInfo.td:1398 |
| 2090 | MAX_S = 2075, // Mips32r6InstrInfo.td:896 |
| 2091 | MAX_S_B = 2076, // MipsMSAInstrInfo.td:3163 |
| 2092 | MAX_S_D = 2077, // MipsMSAInstrInfo.td:3166 |
| 2093 | MAX_S_H = 2078, // MipsMSAInstrInfo.td:3164 |
| 2094 | MAX_S_MMR6 = 2079, // MicroMips32r6InstrInfo.td:1397 |
| 2095 | MAX_S_W = 2080, // MipsMSAInstrInfo.td:3165 |
| 2096 | MAX_U_B = 2081, // MipsMSAInstrInfo.td:3168 |
| 2097 | MAX_U_D = 2082, // MipsMSAInstrInfo.td:3171 |
| 2098 | MAX_U_H = 2083, // MipsMSAInstrInfo.td:3169 |
| 2099 | MAX_U_W = 2084, // MipsMSAInstrInfo.td:3170 |
| 2100 | MFC0 = 2085, // MipsInstrInfo.td:2479 |
| 2101 | MFC0_MM = 2086, // MicroMipsInstrInfo.td:1059 |
| 2102 | MFC0_MMR6 = 2087, // MicroMips32r6InstrInfo.td:1321 |
| 2103 | MFC1 = 2088, // MipsInstrFPU.td:612 |
| 2104 | MFC1_D64 = 2089, // MipsInstrFPU.td:614 |
| 2105 | MFC1_MM = 2090, // MicroMipsInstrFPU.td:199 |
| 2106 | MFC1_MMR6 = 2091, // MicroMips32r6InstrInfo.td:1322 |
| 2107 | MFC2 = 2092, // MipsInstrInfo.td:2481 |
| 2108 | MFC2_MMR6 = 2093, // MicroMips32r6InstrInfo.td:1323 |
| 2109 | MFGC0 = 2094, // MipsInstrInfo.td:2681 |
| 2110 | MFGC0_MM = 2095, // MicroMipsInstrInfo.td:1116 |
| 2111 | MFHC0_MMR6 = 2096, // MicroMips32r6InstrInfo.td:1324 |
| 2112 | MFHC1_D32 = 2097, // MipsInstrFPU.td:625 |
| 2113 | MFHC1_D32_MM = 2098, // MicroMipsInstrFPU.td:247 |
| 2114 | MFHC1_D64 = 2099, // MipsInstrFPU.td:627 |
| 2115 | MFHC1_D64_MM = 2100, // MicroMipsInstrFPU.td:254 |
| 2116 | MFHC2_MMR6 = 2101, // MicroMips32r6InstrInfo.td:1325 |
| 2117 | MFHGC0 = 2102, // MipsInstrInfo.td:2685 |
| 2118 | MFHGC0_MM = 2103, // MicroMipsInstrInfo.td:1119 |
| 2119 | MFHI = 2104, // MipsInstrInfo.td:2398 |
| 2120 | MFHI16_MM = 2105, // MicroMipsInstrInfo.td:648 |
| 2121 | MFHI64 = 2106, // Mips64InstrInfo.td:345 |
| 2122 | MFHI_DSP = 2107, // MipsDSPInstrInfo.td:1144 |
| 2123 | MFHI_DSP_MM = 2108, // MicroMipsDSPInstrInfo.td:484 |
| 2124 | MFHI_MM = 2109, // MicroMipsInstrInfo.td:885 |
| 2125 | MFLO = 2110, // MipsInstrInfo.td:2400 |
| 2126 | MFLO16_MM = 2111, // MicroMipsInstrInfo.td:650 |
| 2127 | MFLO64 = 2112, // Mips64InstrInfo.td:347 |
| 2128 | MFLO_DSP = 2113, // MipsDSPInstrInfo.td:1145 |
| 2129 | MFLO_DSP_MM = 2114, // MicroMipsDSPInstrInfo.td:485 |
| 2130 | MFLO_MM = 2115, // MicroMipsInstrInfo.td:887 |
| 2131 | MFTR = 2116, // MipsMTInstrInfo.td:104 |
| 2132 | MINA_D = 2117, // Mips32r6InstrInfo.td:897 |
| 2133 | MINA_D_MMR6 = 2118, // MicroMips32r6InstrInfo.td:1407 |
| 2134 | MINA_S = 2119, // Mips32r6InstrInfo.td:898 |
| 2135 | MINA_S_MMR6 = 2120, // MicroMips32r6InstrInfo.td:1405 |
| 2136 | MINI_S_B = 2121, // MipsMSAInstrInfo.td:3198 |
| 2137 | MINI_S_D = 2122, // MipsMSAInstrInfo.td:3201 |
| 2138 | MINI_S_H = 2123, // MipsMSAInstrInfo.td:3199 |
| 2139 | MINI_S_W = 2124, // MipsMSAInstrInfo.td:3200 |
| 2140 | MINI_U_B = 2125, // MipsMSAInstrInfo.td:3203 |
| 2141 | MINI_U_D = 2126, // MipsMSAInstrInfo.td:3206 |
| 2142 | MINI_U_H = 2127, // MipsMSAInstrInfo.td:3204 |
| 2143 | MINI_U_W = 2128, // MipsMSAInstrInfo.td:3205 |
| 2144 | MIN_A_B = 2129, // MipsMSAInstrInfo.td:3183 |
| 2145 | MIN_A_D = 2130, // MipsMSAInstrInfo.td:3186 |
| 2146 | MIN_A_H = 2131, // MipsMSAInstrInfo.td:3184 |
| 2147 | MIN_A_W = 2132, // MipsMSAInstrInfo.td:3185 |
| 2148 | MIN_D = 2133, // Mips32r6InstrInfo.td:899 |
| 2149 | MIN_D_MMR6 = 2134, // MicroMips32r6InstrInfo.td:1400 |
| 2150 | MIN_S = 2135, // Mips32r6InstrInfo.td:900 |
| 2151 | MIN_S_B = 2136, // MipsMSAInstrInfo.td:3188 |
| 2152 | MIN_S_D = 2137, // MipsMSAInstrInfo.td:3191 |
| 2153 | MIN_S_H = 2138, // MipsMSAInstrInfo.td:3189 |
| 2154 | MIN_S_MMR6 = 2139, // MicroMips32r6InstrInfo.td:1399 |
| 2155 | MIN_S_W = 2140, // MipsMSAInstrInfo.td:3190 |
| 2156 | MIN_U_B = 2141, // MipsMSAInstrInfo.td:3193 |
| 2157 | MIN_U_D = 2142, // MipsMSAInstrInfo.td:3196 |
| 2158 | MIN_U_H = 2143, // MipsMSAInstrInfo.td:3194 |
| 2159 | MIN_U_W = 2144, // MipsMSAInstrInfo.td:3195 |
| 2160 | MOD = 2145, // Mips32r6InstrInfo.td:903 |
| 2161 | MODSUB = 2146, // MipsDSPInstrInfo.td:1100 |
| 2162 | MODSUB_MM = 2147, // MicroMipsDSPInstrInfo.td:501 |
| 2163 | MODU = 2148, // Mips32r6InstrInfo.td:904 |
| 2164 | MODU_MMR6 = 2149, // MicroMips32r6InstrInfo.td:1327 |
| 2165 | MOD_MMR6 = 2150, // MicroMips32r6InstrInfo.td:1326 |
| 2166 | MOD_S_B = 2151, // MipsMSAInstrInfo.td:3208 |
| 2167 | MOD_S_D = 2152, // MipsMSAInstrInfo.td:3211 |
| 2168 | MOD_S_H = 2153, // MipsMSAInstrInfo.td:3209 |
| 2169 | MOD_S_W = 2154, // MipsMSAInstrInfo.td:3210 |
| 2170 | MOD_U_B = 2155, // MipsMSAInstrInfo.td:3213 |
| 2171 | MOD_U_D = 2156, // MipsMSAInstrInfo.td:3216 |
| 2172 | MOD_U_H = 2157, // MipsMSAInstrInfo.td:3214 |
| 2173 | MOD_U_W = 2158, // MipsMSAInstrInfo.td:3215 |
| 2174 | MOVE16_MM = 2159, // MicroMipsInstrInfo.td:652 |
| 2175 | MOVE16_MMR6 = 2160, // MicroMips32r6InstrInfo.td:1476 |
| 2176 | MOVEP_MM = 2161, // MicroMipsInstrInfo.td:654 |
| 2177 | MOVEP_MMR6 = 2162, // MicroMips32r6InstrInfo.td:1478 |
| 2178 | MOVE_V = 2163, // MipsMSAInstrInfo.td:3218 |
| 2179 | MOVF_D32 = 2164, // MipsCondMov.td:185 |
| 2180 | MOVF_D32_MM = 2165, // MicroMipsInstrFPU.td:195 |
| 2181 | MOVF_D64 = 2166, // MipsCondMov.td:192 |
| 2182 | MOVF_I = 2167, // MipsCondMov.td:171 |
| 2183 | MOVF_I64 = 2168, // MipsCondMov.td:175 |
| 2184 | MOVF_I_MM = 2169, // MicroMipsInstrInfo.td:878 |
| 2185 | MOVF_S = 2170, // MipsCondMov.td:179 |
| 2186 | MOVF_S_MM = 2171, // MicroMipsInstrFPU.td:189 |
| 2187 | MOVN_I64_D64 = 2172, // MipsCondMov.td:158 |
| 2188 | MOVN_I64_I = 2173, // MipsCondMov.td:123 |
| 2189 | MOVN_I64_I64 = 2174, // MipsCondMov.td:125 |
| 2190 | MOVN_I64_S = 2175, // MipsCondMov.td:139 |
| 2191 | MOVN_I_D32 = 2176, // MipsCondMov.td:145 |
| 2192 | MOVN_I_D32_MM = 2177, // MicroMipsInstrFPU.td:182 |
| 2193 | MOVN_I_D64 = 2178, // MipsCondMov.td:152 |
| 2194 | MOVN_I_I = 2179, // MipsCondMov.td:117 |
| 2195 | MOVN_I_I64 = 2180, // MipsCondMov.td:121 |
| 2196 | MOVN_I_MM = 2181, // MicroMipsInstrInfo.td:874 |
| 2197 | MOVN_I_S = 2182, // MipsCondMov.td:135 |
| 2198 | MOVN_I_S_MM = 2183, // MicroMipsInstrFPU.td:176 |
| 2199 | MOVT_D32 = 2184, // MipsCondMov.td:182 |
| 2200 | MOVT_D32_MM = 2185, // MicroMipsInstrFPU.td:192 |
| 2201 | MOVT_D64 = 2186, // MipsCondMov.td:190 |
| 2202 | MOVT_I = 2187, // MipsCondMov.td:164 |
| 2203 | MOVT_I64 = 2188, // MipsCondMov.td:168 |
| 2204 | MOVT_I_MM = 2189, // MicroMipsInstrInfo.td:876 |
| 2205 | MOVT_S = 2190, // MipsCondMov.td:177 |
| 2206 | MOVT_S_MM = 2191, // MicroMipsInstrFPU.td:186 |
| 2207 | MOVZ_I64_D64 = 2192, // MipsCondMov.td:155 |
| 2208 | MOVZ_I64_I = 2193, // MipsCondMov.td:111 |
| 2209 | MOVZ_I64_I64 = 2194, // MipsCondMov.td:113 |
| 2210 | MOVZ_I64_S = 2195, // MipsCondMov.td:132 |
| 2211 | MOVZ_I_D32 = 2196, // MipsCondMov.td:142 |
| 2212 | MOVZ_I_D32_MM = 2197, // MicroMipsInstrFPU.td:179 |
| 2213 | MOVZ_I_D64 = 2198, // MipsCondMov.td:150 |
| 2214 | MOVZ_I_I = 2199, // MipsCondMov.td:105 |
| 2215 | MOVZ_I_I64 = 2200, // MipsCondMov.td:109 |
| 2216 | MOVZ_I_MM = 2201, // MicroMipsInstrInfo.td:872 |
| 2217 | MOVZ_I_S = 2202, // MipsCondMov.td:128 |
| 2218 | MOVZ_I_S_MM = 2203, // MicroMipsInstrFPU.td:173 |
| 2219 | MSUB = 2204, // MipsInstrInfo.td:2436 |
| 2220 | MSUBF_D = 2205, // Mips32r6InstrInfo.td:890 |
| 2221 | MSUBF_D_MMR6 = 2206, // MicroMips32r6InstrInfo.td:1385 |
| 2222 | MSUBF_S = 2207, // Mips32r6InstrInfo.td:889 |
| 2223 | MSUBF_S_MMR6 = 2208, // MicroMips32r6InstrInfo.td:1383 |
| 2224 | MSUBR_Q_H = 2209, // MipsMSAInstrInfo.td:3223 |
| 2225 | MSUBR_Q_W = 2210, // MipsMSAInstrInfo.td:3224 |
| 2226 | MSUBU = 2211, // MipsInstrInfo.td:2438 |
| 2227 | MSUBU_DSP = 2212, // MipsDSPInstrInfo.td:1161 |
| 2228 | MSUBU_DSP_MM = 2213, // MicroMipsDSPInstrInfo.td:416 |
| 2229 | MSUBU_MM = 2214, // MicroMipsInstrInfo.td:897 |
| 2230 | MSUBV_B = 2215, // MipsMSAInstrInfo.td:3226 |
| 2231 | MSUBV_D = 2216, // MipsMSAInstrInfo.td:3229 |
| 2232 | MSUBV_H = 2217, // MipsMSAInstrInfo.td:3227 |
| 2233 | MSUBV_W = 2218, // MipsMSAInstrInfo.td:3228 |
| 2234 | MSUB_D32 = 2219, // MipsInstrFPU.td:748 |
| 2235 | MSUB_D32_MM = 2220, // MicroMipsInstrFPU.td:213 |
| 2236 | MSUB_D64 = 2221, // MipsInstrFPU.td:754 |
| 2237 | MSUB_DSP = 2222, // MipsDSPInstrInfo.td:1160 |
| 2238 | MSUB_DSP_MM = 2223, // MicroMipsDSPInstrInfo.td:415 |
| 2239 | MSUB_MM = 2224, // MicroMipsInstrInfo.td:895 |
| 2240 | MSUB_Q_H = 2225, // MipsMSAInstrInfo.td:3220 |
| 2241 | MSUB_Q_W = 2226, // MipsMSAInstrInfo.td:3221 |
| 2242 | MSUB_S = 2227, // MipsInstrFPU.td:743 |
| 2243 | MSUB_S_MM = 2228, // MicroMipsInstrFPU.td:208 |
| 2244 | MTC0 = 2229, // MipsInstrInfo.td:2477 |
| 2245 | MTC0_MM = 2230, // MicroMipsInstrInfo.td:1061 |
| 2246 | MTC0_MMR6 = 2231, // MicroMips32r6InstrInfo.td:1316 |
| 2247 | MTC1 = 2232, // MipsInstrFPU.td:618 |
| 2248 | MTC1_D64 = 2233, // MipsInstrFPU.td:620 |
| 2249 | MTC1_D64_MM = 2234, // MicroMipsInstrFPU.td:256 |
| 2250 | MTC1_MM = 2235, // MicroMipsInstrFPU.td:202 |
| 2251 | MTC1_MMR6 = 2236, // MicroMips32r6InstrInfo.td:1317 |
| 2252 | MTC2 = 2237, // MipsInstrInfo.td:2483 |
| 2253 | MTC2_MMR6 = 2238, // MicroMips32r6InstrInfo.td:1318 |
| 2254 | MTGC0 = 2239, // MipsInstrInfo.td:2683 |
| 2255 | MTGC0_MM = 2240, // MicroMipsInstrInfo.td:1122 |
| 2256 | MTHC0_MMR6 = 2241, // MicroMips32r6InstrInfo.td:1319 |
| 2257 | MTHC1_D32 = 2242, // MipsInstrFPU.td:632 |
| 2258 | MTHC1_D32_MM = 2243, // MicroMipsInstrFPU.td:244 |
| 2259 | MTHC1_D64 = 2244, // MipsInstrFPU.td:635 |
| 2260 | MTHC1_D64_MM = 2245, // MicroMipsInstrFPU.td:252 |
| 2261 | MTHC2_MMR6 = 2246, // MicroMips32r6InstrInfo.td:1320 |
| 2262 | MTHGC0 = 2247, // MipsInstrInfo.td:2687 |
| 2263 | MTHGC0_MM = 2248, // MicroMipsInstrInfo.td:1125 |
| 2264 | MTHI = 2249, // MipsInstrInfo.td:2394 |
| 2265 | MTHI64 = 2250, // Mips64InstrInfo.td:341 |
| 2266 | MTHI_DSP = 2251, // MipsDSPInstrInfo.td:1146 |
| 2267 | MTHI_DSP_MM = 2252, // MicroMipsDSPInstrInfo.td:486 |
| 2268 | MTHI_MM = 2253, // MicroMipsInstrInfo.td:881 |
| 2269 | MTHLIP = 2254, // MipsDSPInstrInfo.td:1200 |
| 2270 | MTHLIP_MM = 2255, // MicroMipsDSPInstrInfo.td:494 |
| 2271 | MTLO = 2256, // MipsInstrInfo.td:2396 |
| 2272 | MTLO64 = 2257, // Mips64InstrInfo.td:343 |
| 2273 | MTLO_DSP = 2258, // MipsDSPInstrInfo.td:1147 |
| 2274 | MTLO_DSP_MM = 2259, // MicroMipsDSPInstrInfo.td:487 |
| 2275 | MTLO_MM = 2260, // MicroMipsInstrInfo.td:883 |
| 2276 | MTM0 = 2261, // Mips64InstrInfo.td:566 |
| 2277 | MTM1 = 2262, // Mips64InstrInfo.td:568 |
| 2278 | MTM2 = 2263, // Mips64InstrInfo.td:570 |
| 2279 | MTP0 = 2264, // Mips64InstrInfo.td:572 |
| 2280 | MTP1 = 2265, // Mips64InstrInfo.td:573 |
| 2281 | MTP2 = 2266, // Mips64InstrInfo.td:574 |
| 2282 | MTTR = 2267, // MipsMTInstrInfo.td:106 |
| 2283 | MUH = 2268, // Mips32r6InstrInfo.td:905 |
| 2284 | MUHU = 2269, // Mips32r6InstrInfo.td:906 |
| 2285 | MUHU_MMR6 = 2270, // MicroMips32r6InstrInfo.td:1331 |
| 2286 | MUH_MMR6 = 2271, // MicroMips32r6InstrInfo.td:1329 |
| 2287 | MUL = 2272, // MipsInstrInfo.td:2085 |
| 2288 | MULEQ_S_W_PHL = 2273, // MipsDSPInstrInfo.td:1136 |
| 2289 | MULEQ_S_W_PHL_MM = 2274, // MicroMipsDSPInstrInfo.td:468 |
| 2290 | MULEQ_S_W_PHR = 2275, // MipsDSPInstrInfo.td:1137 |
| 2291 | MULEQ_S_W_PHR_MM = 2276, // MicroMipsDSPInstrInfo.td:469 |
| 2292 | MULEU_S_PH_QBL = 2277, // MipsDSPInstrInfo.td:1134 |
| 2293 | MULEU_S_PH_QBL_MM = 2278, // MicroMipsDSPInstrInfo.td:470 |
| 2294 | MULEU_S_PH_QBR = 2279, // MipsDSPInstrInfo.td:1135 |
| 2295 | MULEU_S_PH_QBR_MM = 2280, // MicroMipsDSPInstrInfo.td:471 |
| 2296 | MULQ_RS_PH = 2281, // MipsDSPInstrInfo.td:1138 |
| 2297 | MULQ_RS_PH_MM = 2282, // MicroMipsDSPInstrInfo.td:472 |
| 2298 | MULQ_RS_W = 2283, // MipsDSPInstrInfo.td:1230 |
| 2299 | MULQ_RS_W_MMR2 = 2284, // MicroMipsDSPInstrInfo.td:563 |
| 2300 | MULQ_S_PH = 2285, // MipsDSPInstrInfo.td:1231 |
| 2301 | MULQ_S_PH_MMR2 = 2286, // MicroMipsDSPInstrInfo.td:564 |
| 2302 | MULQ_S_W = 2287, // MipsDSPInstrInfo.td:1229 |
| 2303 | MULQ_S_W_MMR2 = 2288, // MicroMipsDSPInstrInfo.td:565 |
| 2304 | MULR_PS64 = 2289, // MipsInstrFPU.td:540 |
| 2305 | MULR_Q_H = 2290, // MipsMSAInstrInfo.td:3234 |
| 2306 | MULR_Q_W = 2291, // MipsMSAInstrInfo.td:3235 |
| 2307 | MULSAQ_S_W_PH = 2292, // MipsDSPInstrInfo.td:1139 |
| 2308 | MULSAQ_S_W_PH_MM = 2293, // MicroMipsDSPInstrInfo.td:502 |
| 2309 | MULSA_W_PH = 2294, // MipsDSPInstrInfo.td:1240 |
| 2310 | MULSA_W_PH_MMR2 = 2295, // MicroMipsDSPInstrInfo.td:577 |
| 2311 | MULT = 2296, // MipsInstrInfo.td:2386 |
| 2312 | MULTU_DSP = 2297, // MipsDSPInstrInfo.td:1157 |
| 2313 | MULTU_DSP_MM = 2298, // MicroMipsDSPInstrInfo.td:418 |
| 2314 | MULT_DSP = 2299, // MipsDSPInstrInfo.td:1156 |
| 2315 | MULT_DSP_MM = 2300, // MicroMipsDSPInstrInfo.td:417 |
| 2316 | MULT_MM = 2301, // MicroMipsInstrInfo.td:749 |
| 2317 | MULTu = 2302, // MipsInstrInfo.td:2388 |
| 2318 | MULTu_MM = 2303, // MicroMipsInstrInfo.td:751 |
| 2319 | MULU = 2304, // Mips32r6InstrInfo.td:908 |
| 2320 | MULU_MMR6 = 2305, // MicroMips32r6InstrInfo.td:1330 |
| 2321 | MULV_B = 2306, // MipsMSAInstrInfo.td:3237 |
| 2322 | MULV_D = 2307, // MipsMSAInstrInfo.td:3240 |
| 2323 | MULV_H = 2308, // MipsMSAInstrInfo.td:3238 |
| 2324 | MULV_W = 2309, // MipsMSAInstrInfo.td:3239 |
| 2325 | MUL_MM = 2310, // MicroMipsInstrInfo.td:731 |
| 2326 | MUL_MMR6 = 2311, // MicroMips32r6InstrInfo.td:1328 |
| 2327 | MUL_PH = 2312, // MipsDSPInstrInfo.td:1227 |
| 2328 | MUL_PH_MMR2 = 2313, // MicroMipsDSPInstrInfo.td:561 |
| 2329 | MUL_Q_H = 2314, // MipsMSAInstrInfo.td:3231 |
| 2330 | MUL_Q_W = 2315, // MipsMSAInstrInfo.td:3232 |
| 2331 | MUL_R6 = 2316, // Mips32r6InstrInfo.td:907 |
| 2332 | MUL_S_PH = 2317, // MipsDSPInstrInfo.td:1228 |
| 2333 | MUL_S_PH_MMR2 = 2318, // MicroMipsDSPInstrInfo.td:562 |
| 2334 | Mfhi16 = 2319, // Mips16InstrInfo.td:854 |
| 2335 | Mflo16 = 2320, // Mips16InstrInfo.td:866 |
| 2336 | Move32R16 = 2321, // Mips16InstrInfo.td:838 |
| 2337 | MoveR3216 = 2322, // Mips16InstrInfo.td:845 |
| 2338 | NAL = 2323, // Mips32r6InstrInfo.td:825 |
| 2339 | NLOC_B = 2324, // MipsMSAInstrInfo.td:3242 |
| 2340 | NLOC_D = 2325, // MipsMSAInstrInfo.td:3245 |
| 2341 | NLOC_H = 2326, // MipsMSAInstrInfo.td:3243 |
| 2342 | NLOC_W = 2327, // MipsMSAInstrInfo.td:3244 |
| 2343 | NLZC_B = 2328, // MipsMSAInstrInfo.td:3247 |
| 2344 | NLZC_D = 2329, // MipsMSAInstrInfo.td:3250 |
| 2345 | NLZC_H = 2330, // MipsMSAInstrInfo.td:3248 |
| 2346 | NLZC_W = 2331, // MipsMSAInstrInfo.td:3249 |
| 2347 | NMADD_D32 = 2332, // MipsInstrFPU.td:765 |
| 2348 | NMADD_D32_MM = 2333, // MicroMipsInstrFPU.td:222 |
| 2349 | NMADD_D64 = 2334, // MipsInstrFPU.td:771 |
| 2350 | NMADD_S = 2335, // MipsInstrFPU.td:760 |
| 2351 | NMADD_S_MM = 2336, // MicroMipsInstrFPU.td:218 |
| 2352 | NMSUB_D32 = 2337, // MipsInstrFPU.td:767 |
| 2353 | NMSUB_D32_MM = 2338, // MicroMipsInstrFPU.td:224 |
| 2354 | NMSUB_D64 = 2339, // MipsInstrFPU.td:773 |
| 2355 | NMSUB_S = 2340, // MipsInstrFPU.td:762 |
| 2356 | NMSUB_S_MM = 2341, // MicroMipsInstrFPU.td:220 |
| 2357 | NOR = 2342, // MipsInstrInfo.td:2103 |
| 2358 | NOR64 = 2343, // Mips64InstrInfo.td:162 |
| 2359 | NORI_B = 2344, // MipsMSAInstrInfo.td:3266 |
| 2360 | NOR_MM = 2345, // MicroMipsInstrInfo.td:747 |
| 2361 | NOR_MMR6 = 2346, // MicroMips32r6InstrInfo.td:1332 |
| 2362 | NOR_V = 2347, // MipsMSAInstrInfo.td:3252 |
| 2363 | NOT16_MM = 2348, // MicroMipsInstrInfo.td:604 |
| 2364 | NOT16_MMR6 = 2349, // MicroMips32r6InstrInfo.td:1464 |
| 2365 | NegRxRy16 = 2350, // Mips16InstrInfo.td:915 |
| 2366 | NotRxRy16 = 2351, // Mips16InstrInfo.td:922 |
| 2367 | OR = 2352, // MipsInstrInfo.td:2099 |
| 2368 | OR16_MM = 2353, // MicroMipsInstrInfo.td:607 |
| 2369 | OR16_MMR6 = 2354, // MicroMips32r6InstrInfo.td:1466 |
| 2370 | OR64 = 2355, // Mips64InstrInfo.td:158 |
| 2371 | ORI_B = 2356, // MipsMSAInstrInfo.td:3282 |
| 2372 | ORI_MMR6 = 2357, // MicroMips32r6InstrInfo.td:1334 |
| 2373 | OR_MM = 2358, // MicroMipsInstrInfo.td:743 |
| 2374 | OR_MMR6 = 2359, // MicroMips32r6InstrInfo.td:1333 |
| 2375 | OR_V = 2360, // MipsMSAInstrInfo.td:3268 |
| 2376 | ORi = 2361, // MipsInstrInfo.td:2062 |
| 2377 | ORi64 = 2362, // Mips64InstrInfo.td:134 |
| 2378 | ORi_MM = 2363, // MicroMipsInstrInfo.td:713 |
| 2379 | OrRxRxRy16 = 2364, // Mips16InstrInfo.td:929 |
| 2380 | PACKRL_PH = 2365, // MipsDSPInstrInfo.td:1172 |
| 2381 | PACKRL_PH_MM = 2366, // MicroMipsDSPInstrInfo.td:495 |
| 2382 | PAUSE = 2367, // MipsInstrInfo.td:2495 |
| 2383 | PAUSE_MM = 2368, // MicroMipsInstrInfo.td:1056 |
| 2384 | PAUSE_MMR6 = 2369, // MicroMips32r6InstrInfo.td:1353 |
| 2385 | PCKEV_B = 2370, // MipsMSAInstrInfo.td:3284 |
| 2386 | PCKEV_D = 2371, // MipsMSAInstrInfo.td:3287 |
| 2387 | PCKEV_H = 2372, // MipsMSAInstrInfo.td:3285 |
| 2388 | PCKEV_W = 2373, // MipsMSAInstrInfo.td:3286 |
| 2389 | PCKOD_B = 2374, // MipsMSAInstrInfo.td:3289 |
| 2390 | PCKOD_D = 2375, // MipsMSAInstrInfo.td:3292 |
| 2391 | PCKOD_H = 2376, // MipsMSAInstrInfo.td:3290 |
| 2392 | PCKOD_W = 2377, // MipsMSAInstrInfo.td:3291 |
| 2393 | PCNT_B = 2378, // MipsMSAInstrInfo.td:3294 |
| 2394 | PCNT_D = 2379, // MipsMSAInstrInfo.td:3297 |
| 2395 | PCNT_H = 2380, // MipsMSAInstrInfo.td:3295 |
| 2396 | PCNT_W = 2381, // MipsMSAInstrInfo.td:3296 |
| 2397 | PICK_PH = 2382, // MipsDSPInstrInfo.td:1178 |
| 2398 | PICK_PH_MM = 2383, // MicroMipsDSPInstrInfo.td:496 |
| 2399 | PICK_QB = 2384, // MipsDSPInstrInfo.td:1177 |
| 2400 | PICK_QB_MM = 2385, // MicroMipsDSPInstrInfo.td:497 |
| 2401 | PLL_PS64 = 2386, // MipsInstrFPU.td:516 |
| 2402 | PLU_PS64 = 2387, // MipsInstrFPU.td:519 |
| 2403 | POP = 2388, // Mips64InstrInfo.td:577 |
| 2404 | PRECEQU_PH_QBL = 2389, // MipsDSPInstrInfo.td:1110 |
| 2405 | PRECEQU_PH_QBLA = 2390, // MipsDSPInstrInfo.td:1112 |
| 2406 | PRECEQU_PH_QBLA_MM = 2391, // MicroMipsDSPInstrInfo.td:438 |
| 2407 | PRECEQU_PH_QBL_MM = 2392, // MicroMipsDSPInstrInfo.td:437 |
| 2408 | PRECEQU_PH_QBR = 2393, // MipsDSPInstrInfo.td:1111 |
| 2409 | PRECEQU_PH_QBRA = 2394, // MipsDSPInstrInfo.td:1113 |
| 2410 | PRECEQU_PH_QBRA_MM = 2395, // MicroMipsDSPInstrInfo.td:441 |
| 2411 | PRECEQU_PH_QBR_MM = 2396, // MicroMipsDSPInstrInfo.td:440 |
| 2412 | PRECEQ_W_PHL = 2397, // MipsDSPInstrInfo.td:1108 |
| 2413 | PRECEQ_W_PHL_MM = 2398, // MicroMipsDSPInstrInfo.td:435 |
| 2414 | PRECEQ_W_PHR = 2399, // MipsDSPInstrInfo.td:1109 |
| 2415 | PRECEQ_W_PHR_MM = 2400, // MicroMipsDSPInstrInfo.td:436 |
| 2416 | PRECEU_PH_QBL = 2401, // MipsDSPInstrInfo.td:1114 |
| 2417 | PRECEU_PH_QBLA = 2402, // MipsDSPInstrInfo.td:1116 |
| 2418 | PRECEU_PH_QBLA_MM = 2403, // MicroMipsDSPInstrInfo.td:444 |
| 2419 | PRECEU_PH_QBL_MM = 2404, // MicroMipsDSPInstrInfo.td:443 |
| 2420 | PRECEU_PH_QBR = 2405, // MipsDSPInstrInfo.td:1115 |
| 2421 | PRECEU_PH_QBRA = 2406, // MipsDSPInstrInfo.td:1117 |
| 2422 | PRECEU_PH_QBRA_MM = 2407, // MicroMipsDSPInstrInfo.td:446 |
| 2423 | PRECEU_PH_QBR_MM = 2408, // MicroMipsDSPInstrInfo.td:445 |
| 2424 | PRECRQU_S_QB_PH = 2409, // MipsDSPInstrInfo.td:1107 |
| 2425 | PRECRQU_S_QB_PH_MM = 2410, // MicroMipsDSPInstrInfo.td:475 |
| 2426 | PRECRQ_PH_W = 2411, // MipsDSPInstrInfo.td:1105 |
| 2427 | PRECRQ_PH_W_MM = 2412, // MicroMipsDSPInstrInfo.td:473 |
| 2428 | PRECRQ_QB_PH = 2413, // MipsDSPInstrInfo.td:1104 |
| 2429 | PRECRQ_QB_PH_MM = 2414, // MicroMipsDSPInstrInfo.td:474 |
| 2430 | PRECRQ_RS_PH_W = 2415, // MipsDSPInstrInfo.td:1106 |
| 2431 | PRECRQ_RS_PH_W_MM = 2416, // MicroMipsDSPInstrInfo.td:476 |
| 2432 | PRECR_QB_PH = 2417, // MipsDSPInstrInfo.td:1241 |
| 2433 | PRECR_QB_PH_MMR2 = 2418, // MicroMipsDSPInstrInfo.td:566 |
| 2434 | PRECR_SRA_PH_W = 2419, // MipsDSPInstrInfo.td:1242 |
| 2435 | PRECR_SRA_PH_W_MMR2 = 2420, // MicroMipsDSPInstrInfo.td:568 |
| 2436 | PRECR_SRA_R_PH_W = 2421, // MipsDSPInstrInfo.td:1243 |
| 2437 | PRECR_SRA_R_PH_W_MMR2 = 2422, // MicroMipsDSPInstrInfo.td:570 |
| 2438 | PREF = 2423, // MipsInstrInfo.td:2573 |
| 2439 | PREFE = 2424, // MipsEVAInstrInfo.td:200 |
| 2440 | PREFE_MM = 2425, // MicroMipsInstrInfo.td:1047 |
| 2441 | PREFX_MM = 2426, // MicroMipsInstrInfo.td:1076 |
| 2442 | PREF_MM = 2427, // MicroMipsInstrInfo.td:1042 |
| 2443 | PREF_MMR6 = 2428, // MicroMips32r6InstrInfo.td:1335 |
| 2444 | PREF_R6 = 2429, // Mips32r6InstrInfo.td:916 |
| 2445 | PREPEND = 2430, // MipsDSPInstrInfo.td:1252 |
| 2446 | PREPEND_MMR2 = 2431, // MicroMipsDSPInstrInfo.td:572 |
| 2447 | PUL_PS64 = 2432, // MipsInstrFPU.td:522 |
| 2448 | PUU_PS64 = 2433, // MipsInstrFPU.td:525 |
| 2449 | RADDU_W_QB = 2434, // MipsDSPInstrInfo.td:1101 |
| 2450 | RADDU_W_QB_MM = 2435, // MicroMipsDSPInstrInfo.td:488 |
| 2451 | RDDSP = 2436, // MipsDSPInstrInfo.td:1201 |
| 2452 | RDDSP_MM = 2437, // MicroMipsDSPInstrInfo.td:489 |
| 2453 | RDHWR = 2438, // MipsInstrInfo.td:2465 |
| 2454 | RDHWR64 = 2439, // Mips64InstrInfo.td:380 |
| 2455 | RDHWR_MM = 2440, // MicroMipsInstrInfo.td:1111 |
| 2456 | RDHWR_MMR6 = 2441, // MicroMips32r6InstrInfo.td:1354 |
| 2457 | RDPGPR_MMR6 = 2442, // MicroMips32r6InstrInfo.td:1359 |
| 2458 | RECIP_D32 = 2443, // MipsInstrFPU.td:441 |
| 2459 | RECIP_D32_MM = 2444, // MicroMipsInstrFPU.td:269 |
| 2460 | RECIP_D64 = 2445, // MipsInstrFPU.td:446 |
| 2461 | RECIP_D64_MM = 2446, // MicroMipsInstrFPU.td:274 |
| 2462 | RECIP_S = 2447, // MipsInstrFPU.td:439 |
| 2463 | RECIP_S_MM = 2448, // MicroMipsInstrFPU.td:267 |
| 2464 | REPLV_PH = 2449, // MipsDSPInstrInfo.td:1176 |
| 2465 | REPLV_PH_MM = 2450, // MicroMipsDSPInstrInfo.td:492 |
| 2466 | REPLV_QB = 2451, // MipsDSPInstrInfo.td:1175 |
| 2467 | REPLV_QB_MM = 2452, // MicroMipsDSPInstrInfo.td:493 |
| 2468 | REPL_PH = 2453, // MipsDSPInstrInfo.td:1174 |
| 2469 | REPL_PH_MM = 2454, // MicroMipsDSPInstrInfo.td:490 |
| 2470 | REPL_QB = 2455, // MipsDSPInstrInfo.td:1173 |
| 2471 | REPL_QB_MM = 2456, // MicroMipsDSPInstrInfo.td:491 |
| 2472 | RINT_D = 2457, // Mips32r6InstrInfo.td:912 |
| 2473 | RINT_D_MMR6 = 2458, // MicroMips32r6InstrInfo.td:1496 |
| 2474 | RINT_S = 2459, // Mips32r6InstrInfo.td:913 |
| 2475 | RINT_S_MMR6 = 2460, // MicroMips32r6InstrInfo.td:1494 |
| 2476 | ROTR = 2461, // MipsInstrInfo.td:2123 |
| 2477 | ROTRV = 2462, // MipsInstrInfo.td:2126 |
| 2478 | ROTRV_MM = 2463, // MicroMipsInstrInfo.td:780 |
| 2479 | ROTR_MM = 2464, // MicroMipsInstrInfo.td:775 |
| 2480 | ROUND_L_D64 = 2465, // MipsInstrFPU.td:465 |
| 2481 | ROUND_L_D_MMR6 = 2466, // MicroMips32r6InstrInfo.td:1501 |
| 2482 | ROUND_L_S = 2467, // MipsInstrFPU.td:463 |
| 2483 | ROUND_L_S_MMR6 = 2468, // MicroMips32r6InstrInfo.td:1499 |
| 2484 | ROUND_W_D32 = 2469, // MipsInstrFPU.td:179 |
| 2485 | ROUND_W_D64 = 2470, // MipsInstrFPU.td:180 |
| 2486 | ROUND_W_D_MMR6 = 2471, // MicroMips32r6InstrInfo.td:1505 |
| 2487 | ROUND_W_MM = 2472, // MicroMipsInstrFPU.td:95 |
| 2488 | ROUND_W_S = 2473, // MipsInstrFPU.td:413 |
| 2489 | ROUND_W_S_MM = 2474, // MicroMipsInstrFPU.td:87 |
| 2490 | ROUND_W_S_MMR6 = 2475, // MicroMips32r6InstrInfo.td:1503 |
| 2491 | RSQRT_D32 = 2476, // MipsInstrFPU.td:451 |
| 2492 | RSQRT_D32_MM = 2477, // MicroMipsInstrFPU.td:278 |
| 2493 | RSQRT_D64 = 2478, // MipsInstrFPU.td:456 |
| 2494 | RSQRT_D64_MM = 2479, // MicroMipsInstrFPU.td:283 |
| 2495 | RSQRT_S = 2480, // MipsInstrFPU.td:449 |
| 2496 | RSQRT_S_MM = 2481, // MicroMipsInstrFPU.td:276 |
| 2497 | Restore16 = 2482, // Mips16InstrInfo.td:940 |
| 2498 | RestoreX16 = 2483, // Mips16InstrInfo.td:949 |
| 2499 | SAA = 2484, // Mips64InstrInfo.td:620 |
| 2500 | SAAD = 2485, // Mips64InstrInfo.td:621 |
| 2501 | SAT_S_B = 2486, // MipsMSAInstrInfo.td:3299 |
| 2502 | SAT_S_D = 2487, // MipsMSAInstrInfo.td:3302 |
| 2503 | SAT_S_H = 2488, // MipsMSAInstrInfo.td:3300 |
| 2504 | SAT_S_W = 2489, // MipsMSAInstrInfo.td:3301 |
| 2505 | SAT_U_B = 2490, // MipsMSAInstrInfo.td:3304 |
| 2506 | SAT_U_D = 2491, // MipsMSAInstrInfo.td:3307 |
| 2507 | SAT_U_H = 2492, // MipsMSAInstrInfo.td:3305 |
| 2508 | SAT_U_W = 2493, // MipsMSAInstrInfo.td:3306 |
| 2509 | SB = 2494, // MipsInstrInfo.td:2143 |
| 2510 | SB16_MM = 2495, // MicroMipsInstrInfo.td:626 |
| 2511 | SB16_MMR6 = 2496, // MicroMips32r6InstrInfo.td:1336 |
| 2512 | SB64 = 2497, // Mips64InstrInfo.td:207 |
| 2513 | SBE = 2498, // MipsEVAInstrInfo.td:180 |
| 2514 | SBE_MM = 2499, // MicroMipsInstrInfo.td:817 |
| 2515 | SB_MM = 2500, // MicroMipsInstrInfo.td:798 |
| 2516 | SB_MMR6 = 2501, // MicroMips32r6InstrInfo.td:1454 |
| 2517 | SC = 2502, // MipsInstrInfo.td:2258 |
| 2518 | SC64 = 2503, // Mips64InstrInfo.td:260 |
| 2519 | SC64_R6 = 2504, // Mips64r6InstrInfo.td:160 |
| 2520 | SCD = 2505, // Mips64InstrInfo.td:252 |
| 2521 | SCD_R6 = 2506, // Mips64r6InstrInfo.td:151 |
| 2522 | SCE = 2507, // MipsEVAInstrInfo.td:192 |
| 2523 | SCE_MM = 2508, // MicroMipsInstrInfo.td:1036 |
| 2524 | SC_MM = 2509, // MicroMipsInstrInfo.td:1031 |
| 2525 | SC_MMR6 = 2510, // MicroMips32r6InstrInfo.td:1550 |
| 2526 | SC_R6 = 2511, // Mips32r6InstrInfo.td:917 |
| 2527 | SD = 2512, // Mips64InstrInfo.td:219 |
| 2528 | SDBBP = 2513, // MipsInstrInfo.td:2236 |
| 2529 | SDBBP16_MM = 2514, // MicroMipsInstrInfo.td:676 |
| 2530 | SDBBP16_MMR6 = 2515, // MicroMips32r6InstrInfo.td:1480 |
| 2531 | SDBBP_MM = 2516, // MicroMipsInstrInfo.td:1073 |
| 2532 | SDBBP_MMR6 = 2517, // MicroMips32r6InstrInfo.td:1361 |
| 2533 | SDBBP_R6 = 2518, // Mips32r6InstrInfo.td:918 |
| 2534 | SDC1 = 2519, // MipsInstrFPU.td:677 |
| 2535 | SDC164 = 2520, // MipsInstrFPU.td:668 |
| 2536 | SDC1_D64_MMR6 = 2521, // MicroMips32r6InstrInfo.td:1542 |
| 2537 | SDC1_MM_D32 = 2522, // MicroMipsInstrFPU.td:293 |
| 2538 | SDC1_MM_D64 = 2523, // MicroMipsInstrFPU.td:308 |
| 2539 | SDC2 = 2524, // MipsInstrInfo.td:2169 |
| 2540 | SDC2_MMR6 = 2525, // MicroMips32r6InstrInfo.td:1546 |
| 2541 | SDC2_R6 = 2526, // Mips32r6InstrInfo.td:931 |
| 2542 | SDC3 = 2527, // MipsInstrInfo.td:2186 |
| 2543 | SDIV = 2528, // MipsInstrInfo.td:2390 |
| 2544 | SDIV_MM = 2529, // MicroMipsInstrInfo.td:753 |
| 2545 | SDL = 2530, // Mips64InstrInfo.td:241 |
| 2546 | SDR = 2531, // Mips64InstrInfo.td:243 |
| 2547 | SDXC1 = 2532, // MipsInstrFPU.td:692 |
| 2548 | SDXC164 = 2533, // MipsInstrFPU.td:699 |
| 2549 | SEB = 2534, // MipsInstrInfo.td:2404 |
| 2550 | SEB64 = 2535, // Mips64InstrInfo.td:356 |
| 2551 | SEB_MM = 2536, // MicroMipsInstrInfo.td:907 |
| 2552 | SEH = 2537, // MipsInstrInfo.td:2406 |
| 2553 | SEH64 = 2538, // Mips64InstrInfo.td:358 |
| 2554 | SEH_MM = 2539, // MicroMipsInstrInfo.td:909 |
| 2555 | SELEQZ = 2540, // Mips32r6InstrInfo.td:919 |
| 2556 | SELEQZ64 = 2541, // Mips64r6InstrInfo.td:153 |
| 2557 | SELEQZ_D = 2542, // Mips32r6InstrInfo.td:921 |
| 2558 | SELEQZ_D_MMR6 = 2543, // MicroMips32r6InstrInfo.td:1513 |
| 2559 | SELEQZ_MMR6 = 2544, // MicroMips32r6InstrInfo.td:1337 |
| 2560 | SELEQZ_S = 2545, // Mips32r6InstrInfo.td:923 |
| 2561 | SELEQZ_S_MMR6 = 2546, // MicroMips32r6InstrInfo.td:1511 |
| 2562 | SELNEZ = 2547, // Mips32r6InstrInfo.td:920 |
| 2563 | SELNEZ64 = 2548, // Mips64r6InstrInfo.td:154 |
| 2564 | SELNEZ_D = 2549, // Mips32r6InstrInfo.td:925 |
| 2565 | SELNEZ_D_MMR6 = 2550, // MicroMips32r6InstrInfo.td:1517 |
| 2566 | SELNEZ_MMR6 = 2551, // MicroMips32r6InstrInfo.td:1339 |
| 2567 | SELNEZ_S = 2552, // Mips32r6InstrInfo.td:927 |
| 2568 | SELNEZ_S_MMR6 = 2553, // MicroMips32r6InstrInfo.td:1515 |
| 2569 | SEL_D = 2554, // Mips32r6InstrInfo.td:929 |
| 2570 | SEL_D_MMR6 = 2555, // MicroMips32r6InstrInfo.td:1510 |
| 2571 | SEL_S = 2556, // Mips32r6InstrInfo.td:930 |
| 2572 | SEL_S_MMR6 = 2557, // MicroMips32r6InstrInfo.td:1509 |
| 2573 | SEQ = 2558, // Mips64InstrInfo.td:581 |
| 2574 | SEQi = 2559, // Mips64InstrInfo.td:582 |
| 2575 | SH = 2560, // MipsInstrInfo.td:2145 |
| 2576 | SH16_MM = 2561, // MicroMipsInstrInfo.td:629 |
| 2577 | SH16_MMR6 = 2562, // MicroMips32r6InstrInfo.td:1341 |
| 2578 | SH64 = 2563, // Mips64InstrInfo.td:208 |
| 2579 | SHE = 2564, // MipsEVAInstrInfo.td:181 |
| 2580 | SHE_MM = 2565, // MicroMipsInstrInfo.td:819 |
| 2581 | SHF_B = 2566, // MipsMSAInstrInfo.td:3309 |
| 2582 | SHF_H = 2567, // MipsMSAInstrInfo.td:3310 |
| 2583 | SHF_W = 2568, // MipsMSAInstrInfo.td:3311 |
| 2584 | SHILO = 2569, // MipsDSPInstrInfo.td:1198 |
| 2585 | SHILOV = 2570, // MipsDSPInstrInfo.td:1199 |
| 2586 | SHILOV_MM = 2571, // MicroMipsDSPInstrInfo.td:499 |
| 2587 | SHILO_MM = 2572, // MicroMipsDSPInstrInfo.td:498 |
| 2588 | SHLLV_PH = 2573, // MipsDSPInstrInfo.td:1123 |
| 2589 | SHLLV_PH_MM = 2574, // MicroMipsDSPInstrInfo.td:422 |
| 2590 | SHLLV_QB = 2575, // MipsDSPInstrInfo.td:1119 |
| 2591 | SHLLV_QB_MM = 2576, // MicroMipsDSPInstrInfo.td:424 |
| 2592 | SHLLV_S_PH = 2577, // MipsDSPInstrInfo.td:1125 |
| 2593 | SHLLV_S_PH_MM = 2578, // MicroMipsDSPInstrInfo.td:423 |
| 2594 | SHLLV_S_W = 2579, // MipsDSPInstrInfo.td:1131 |
| 2595 | SHLLV_S_W_MM = 2580, // MicroMipsDSPInstrInfo.td:425 |
| 2596 | SHLL_PH = 2581, // MipsDSPInstrInfo.td:1122 |
| 2597 | SHLL_PH_MM = 2582, // MicroMipsDSPInstrInfo.td:419 |
| 2598 | SHLL_QB = 2583, // MipsDSPInstrInfo.td:1118 |
| 2599 | SHLL_QB_MM = 2584, // MicroMipsDSPInstrInfo.td:421 |
| 2600 | SHLL_S_PH = 2585, // MipsDSPInstrInfo.td:1124 |
| 2601 | SHLL_S_PH_MM = 2586, // MicroMipsDSPInstrInfo.td:420 |
| 2602 | SHLL_S_W = 2587, // MipsDSPInstrInfo.td:1130 |
| 2603 | SHLL_S_W_MM = 2588, // MicroMipsDSPInstrInfo.td:426 |
| 2604 | SHRAV_PH = 2589, // MipsDSPInstrInfo.td:1127 |
| 2605 | SHRAV_PH_MM = 2590, // MicroMipsDSPInstrInfo.td:429 |
| 2606 | SHRAV_QB = 2591, // MipsDSPInstrInfo.td:1245 |
| 2607 | SHRAV_QB_MMR2 = 2592, // MicroMipsDSPInstrInfo.td:535 |
| 2608 | SHRAV_R_PH = 2593, // MipsDSPInstrInfo.td:1129 |
| 2609 | SHRAV_R_PH_MM = 2594, // MicroMipsDSPInstrInfo.td:430 |
| 2610 | SHRAV_R_QB = 2595, // MipsDSPInstrInfo.td:1247 |
| 2611 | SHRAV_R_QB_MMR2 = 2596, // MicroMipsDSPInstrInfo.td:536 |
| 2612 | SHRAV_R_W = 2597, // MipsDSPInstrInfo.td:1133 |
| 2613 | SHRAV_R_W_MM = 2598, // MicroMipsDSPInstrInfo.td:431 |
| 2614 | SHRA_PH = 2599, // MipsDSPInstrInfo.td:1126 |
| 2615 | SHRA_PH_MM = 2600, // MicroMipsDSPInstrInfo.td:427 |
| 2616 | SHRA_QB = 2601, // MipsDSPInstrInfo.td:1244 |
| 2617 | SHRA_QB_MMR2 = 2602, // MicroMipsDSPInstrInfo.td:532 |
| 2618 | SHRA_R_PH = 2603, // MipsDSPInstrInfo.td:1128 |
| 2619 | SHRA_R_PH_MM = 2604, // MicroMipsDSPInstrInfo.td:428 |
| 2620 | SHRA_R_QB = 2605, // MipsDSPInstrInfo.td:1246 |
| 2621 | SHRA_R_QB_MMR2 = 2606, // MicroMipsDSPInstrInfo.td:533 |
| 2622 | SHRA_R_W = 2607, // MipsDSPInstrInfo.td:1132 |
| 2623 | SHRA_R_W_MM = 2608, // MicroMipsDSPInstrInfo.td:432 |
| 2624 | SHRLV_PH = 2609, // MipsDSPInstrInfo.td:1249 |
| 2625 | SHRLV_PH_MMR2 = 2610, // MicroMipsDSPInstrInfo.td:546 |
| 2626 | SHRLV_QB = 2611, // MipsDSPInstrInfo.td:1121 |
| 2627 | SHRLV_QB_MM = 2612, // MicroMipsDSPInstrInfo.td:434 |
| 2628 | SHRL_PH = 2613, // MipsDSPInstrInfo.td:1248 |
| 2629 | SHRL_PH_MMR2 = 2614, // MicroMipsDSPInstrInfo.td:545 |
| 2630 | SHRL_QB = 2615, // MipsDSPInstrInfo.td:1120 |
| 2631 | SHRL_QB_MM = 2616, // MicroMipsDSPInstrInfo.td:433 |
| 2632 | SH_MM = 2617, // MicroMipsInstrInfo.td:800 |
| 2633 | SH_MMR6 = 2618, // MicroMips32r6InstrInfo.td:1455 |
| 2634 | SIGRIE = 2619, // Mips32r6InstrInfo.td:933 |
| 2635 | SIGRIE_MMR6 = 2620, // MicroMips32r6InstrInfo.td:1362 |
| 2636 | SLDI_B = 2621, // MipsMSAInstrInfo.td:3318 |
| 2637 | SLDI_D = 2622, // MipsMSAInstrInfo.td:3321 |
| 2638 | SLDI_H = 2623, // MipsMSAInstrInfo.td:3319 |
| 2639 | SLDI_W = 2624, // MipsMSAInstrInfo.td:3320 |
| 2640 | SLD_B = 2625, // MipsMSAInstrInfo.td:3313 |
| 2641 | SLD_D = 2626, // MipsMSAInstrInfo.td:3316 |
| 2642 | SLD_H = 2627, // MipsMSAInstrInfo.td:3314 |
| 2643 | SLD_W = 2628, // MipsMSAInstrInfo.td:3315 |
| 2644 | SLL = 2629, // MipsInstrInfo.td:2109 |
| 2645 | SLL16_MM = 2630, // MicroMipsInstrInfo.td:609 |
| 2646 | SLL16_MMR6 = 2631, // MicroMips32r6InstrInfo.td:1468 |
| 2647 | SLL64_32 = 2632, // Mips64InstrInfo.td:430 |
| 2648 | SLL64_64 = 2633, // Mips64InstrInfo.td:434 |
| 2649 | SLLI_B = 2634, // MipsMSAInstrInfo.td:3328 |
| 2650 | SLLI_D = 2635, // MipsMSAInstrInfo.td:3331 |
| 2651 | SLLI_H = 2636, // MipsMSAInstrInfo.td:3329 |
| 2652 | SLLI_W = 2637, // MipsMSAInstrInfo.td:3330 |
| 2653 | SLLV = 2638, // MipsInstrInfo.td:2115 |
| 2654 | SLLV_MM = 2639, // MicroMipsInstrInfo.td:769 |
| 2655 | SLL_B = 2640, // MipsMSAInstrInfo.td:3323 |
| 2656 | SLL_D = 2641, // MipsMSAInstrInfo.td:3326 |
| 2657 | SLL_H = 2642, // MipsMSAInstrInfo.td:3324 |
| 2658 | SLL_MM = 2643, // MicroMipsInstrInfo.td:763 |
| 2659 | SLL_MMR6 = 2644, // MicroMips32r6InstrInfo.td:1342 |
| 2660 | SLL_W = 2645, // MipsMSAInstrInfo.td:3325 |
| 2661 | SLT = 2646, // MipsInstrInfo.td:2093 |
| 2662 | SLT64 = 2647, // Mips64InstrInfo.td:154 |
| 2663 | SLT_MM = 2648, // MicroMipsInstrInfo.td:737 |
| 2664 | SLTi = 2649, // MipsInstrInfo.td:2070 |
| 2665 | SLTi64 = 2650, // Mips64InstrInfo.td:128 |
| 2666 | SLTi_MM = 2651, // MicroMipsInstrInfo.td:707 |
| 2667 | SLTiu = 2652, // MipsInstrInfo.td:2072 |
| 2668 | SLTiu64 = 2653, // Mips64InstrInfo.td:130 |
| 2669 | SLTiu_MM = 2654, // MicroMipsInstrInfo.td:709 |
| 2670 | SLTu = 2655, // MipsInstrInfo.td:2095 |
| 2671 | SLTu64 = 2656, // Mips64InstrInfo.td:155 |
| 2672 | SLTu_MM = 2657, // MicroMipsInstrInfo.td:739 |
| 2673 | SNE = 2658, // Mips64InstrInfo.td:583 |
| 2674 | SNEi = 2659, // Mips64InstrInfo.td:584 |
| 2675 | SPLATI_B = 2660, // MipsMSAInstrInfo.td:3338 |
| 2676 | SPLATI_D = 2661, // MipsMSAInstrInfo.td:3341 |
| 2677 | SPLATI_H = 2662, // MipsMSAInstrInfo.td:3339 |
| 2678 | SPLATI_W = 2663, // MipsMSAInstrInfo.td:3340 |
| 2679 | SPLAT_B = 2664, // MipsMSAInstrInfo.td:3333 |
| 2680 | SPLAT_D = 2665, // MipsMSAInstrInfo.td:3336 |
| 2681 | SPLAT_H = 2666, // MipsMSAInstrInfo.td:3334 |
| 2682 | SPLAT_W = 2667, // MipsMSAInstrInfo.td:3335 |
| 2683 | SRA = 2668, // MipsInstrInfo.td:2113 |
| 2684 | SRAI_B = 2669, // MipsMSAInstrInfo.td:3348 |
| 2685 | SRAI_D = 2670, // MipsMSAInstrInfo.td:3351 |
| 2686 | SRAI_H = 2671, // MipsMSAInstrInfo.td:3349 |
| 2687 | SRAI_W = 2672, // MipsMSAInstrInfo.td:3350 |
| 2688 | SRARI_B = 2673, // MipsMSAInstrInfo.td:3358 |
| 2689 | SRARI_D = 2674, // MipsMSAInstrInfo.td:3361 |
| 2690 | SRARI_H = 2675, // MipsMSAInstrInfo.td:3359 |
| 2691 | SRARI_W = 2676, // MipsMSAInstrInfo.td:3360 |
| 2692 | SRAR_B = 2677, // MipsMSAInstrInfo.td:3353 |
| 2693 | SRAR_D = 2678, // MipsMSAInstrInfo.td:3356 |
| 2694 | SRAR_H = 2679, // MipsMSAInstrInfo.td:3354 |
| 2695 | SRAR_W = 2680, // MipsMSAInstrInfo.td:3355 |
| 2696 | SRAV = 2681, // MipsInstrInfo.td:2119 |
| 2697 | SRAV_MM = 2682, // MicroMipsInstrInfo.td:773 |
| 2698 | SRA_B = 2683, // MipsMSAInstrInfo.td:3343 |
| 2699 | SRA_D = 2684, // MipsMSAInstrInfo.td:3346 |
| 2700 | SRA_H = 2685, // MipsMSAInstrInfo.td:3344 |
| 2701 | SRA_MM = 2686, // MicroMipsInstrInfo.td:767 |
| 2702 | SRA_W = 2687, // MipsMSAInstrInfo.td:3345 |
| 2703 | SRL = 2688, // MipsInstrInfo.td:2111 |
| 2704 | SRL16_MM = 2689, // MicroMipsInstrInfo.td:611 |
| 2705 | SRL16_MMR6 = 2690, // MicroMips32r6InstrInfo.td:1470 |
| 2706 | SRLI_B = 2691, // MipsMSAInstrInfo.td:3368 |
| 2707 | SRLI_D = 2692, // MipsMSAInstrInfo.td:3371 |
| 2708 | SRLI_H = 2693, // MipsMSAInstrInfo.td:3369 |
| 2709 | SRLI_W = 2694, // MipsMSAInstrInfo.td:3370 |
| 2710 | SRLRI_B = 2695, // MipsMSAInstrInfo.td:3378 |
| 2711 | SRLRI_D = 2696, // MipsMSAInstrInfo.td:3381 |
| 2712 | SRLRI_H = 2697, // MipsMSAInstrInfo.td:3379 |
| 2713 | SRLRI_W = 2698, // MipsMSAInstrInfo.td:3380 |
| 2714 | SRLR_B = 2699, // MipsMSAInstrInfo.td:3373 |
| 2715 | SRLR_D = 2700, // MipsMSAInstrInfo.td:3376 |
| 2716 | SRLR_H = 2701, // MipsMSAInstrInfo.td:3374 |
| 2717 | SRLR_W = 2702, // MipsMSAInstrInfo.td:3375 |
| 2718 | SRLV = 2703, // MipsInstrInfo.td:2117 |
| 2719 | SRLV_MM = 2704, // MicroMipsInstrInfo.td:771 |
| 2720 | SRL_B = 2705, // MipsMSAInstrInfo.td:3363 |
| 2721 | SRL_D = 2706, // MipsMSAInstrInfo.td:3366 |
| 2722 | SRL_H = 2707, // MipsMSAInstrInfo.td:3364 |
| 2723 | SRL_MM = 2708, // MicroMipsInstrInfo.td:765 |
| 2724 | SRL_W = 2709, // MipsMSAInstrInfo.td:3365 |
| 2725 | SSNOP = 2710, // MipsInstrInfo.td:2490 |
| 2726 | SSNOP_MM = 2711, // MicroMipsInstrInfo.td:1052 |
| 2727 | SSNOP_MMR6 = 2712, // MicroMips32r6InstrInfo.td:1356 |
| 2728 | ST_B = 2713, // MipsMSAInstrInfo.td:3383 |
| 2729 | ST_D = 2714, // MipsMSAInstrInfo.td:3386 |
| 2730 | ST_H = 2715, // MipsMSAInstrInfo.td:3384 |
| 2731 | ST_W = 2716, // MipsMSAInstrInfo.td:3385 |
| 2732 | SUB = 2717, // MipsInstrInfo.td:2090 |
| 2733 | SUBQH_PH = 2718, // MipsDSPInstrInfo.td:1221 |
| 2734 | SUBQH_PH_MMR2 = 2719, // MicroMipsDSPInstrInfo.td:547 |
| 2735 | SUBQH_R_PH = 2720, // MipsDSPInstrInfo.td:1222 |
| 2736 | SUBQH_R_PH_MMR2 = 2721, // MicroMipsDSPInstrInfo.td:548 |
| 2737 | SUBQH_R_W = 2722, // MipsDSPInstrInfo.td:1226 |
| 2738 | SUBQH_R_W_MMR2 = 2723, // MicroMipsDSPInstrInfo.td:550 |
| 2739 | SUBQH_W = 2724, // MipsDSPInstrInfo.td:1225 |
| 2740 | SUBQH_W_MMR2 = 2725, // MicroMipsDSPInstrInfo.td:549 |
| 2741 | SUBQ_PH = 2726, // MipsDSPInstrInfo.td:1094 |
| 2742 | SUBQ_PH_MM = 2727, // MicroMipsDSPInstrInfo.td:447 |
| 2743 | SUBQ_S_PH = 2728, // MipsDSPInstrInfo.td:1095 |
| 2744 | SUBQ_S_PH_MM = 2729, // MicroMipsDSPInstrInfo.td:448 |
| 2745 | SUBQ_S_W = 2730, // MipsDSPInstrInfo.td:1097 |
| 2746 | SUBQ_S_W_MM = 2731, // MicroMipsDSPInstrInfo.td:449 |
| 2747 | SUBSUS_U_B = 2732, // MipsMSAInstrInfo.td:3398 |
| 2748 | SUBSUS_U_D = 2733, // MipsMSAInstrInfo.td:3401 |
| 2749 | SUBSUS_U_H = 2734, // MipsMSAInstrInfo.td:3399 |
| 2750 | SUBSUS_U_W = 2735, // MipsMSAInstrInfo.td:3400 |
| 2751 | SUBSUU_S_B = 2736, // MipsMSAInstrInfo.td:3403 |
| 2752 | SUBSUU_S_D = 2737, // MipsMSAInstrInfo.td:3406 |
| 2753 | SUBSUU_S_H = 2738, // MipsMSAInstrInfo.td:3404 |
| 2754 | SUBSUU_S_W = 2739, // MipsMSAInstrInfo.td:3405 |
| 2755 | SUBS_S_B = 2740, // MipsMSAInstrInfo.td:3388 |
| 2756 | SUBS_S_D = 2741, // MipsMSAInstrInfo.td:3391 |
| 2757 | SUBS_S_H = 2742, // MipsMSAInstrInfo.td:3389 |
| 2758 | SUBS_S_W = 2743, // MipsMSAInstrInfo.td:3390 |
| 2759 | SUBS_U_B = 2744, // MipsMSAInstrInfo.td:3393 |
| 2760 | SUBS_U_D = 2745, // MipsMSAInstrInfo.td:3396 |
| 2761 | SUBS_U_H = 2746, // MipsMSAInstrInfo.td:3394 |
| 2762 | SUBS_U_W = 2747, // MipsMSAInstrInfo.td:3395 |
| 2763 | SUBU16_MM = 2748, // MicroMipsInstrInfo.td:615 |
| 2764 | SUBU16_MMR6 = 2749, // MicroMips32r6InstrInfo.td:1482 |
| 2765 | SUBUH_QB = 2750, // MipsDSPInstrInfo.td:1217 |
| 2766 | SUBUH_QB_MMR2 = 2751, // MicroMipsDSPInstrInfo.td:553 |
| 2767 | SUBUH_R_QB = 2752, // MipsDSPInstrInfo.td:1218 |
| 2768 | SUBUH_R_QB_MMR2 = 2753, // MicroMipsDSPInstrInfo.td:554 |
| 2769 | SUBU_MMR6 = 2754, // MicroMips32r6InstrInfo.td:1344 |
| 2770 | SUBU_PH = 2755, // MipsDSPInstrInfo.td:1209 |
| 2771 | SUBU_PH_MMR2 = 2756, // MicroMipsDSPInstrInfo.td:551 |
| 2772 | SUBU_QB = 2757, // MipsDSPInstrInfo.td:1090 |
| 2773 | SUBU_QB_MM = 2758, // MicroMipsDSPInstrInfo.td:450 |
| 2774 | SUBU_S_PH = 2759, // MipsDSPInstrInfo.td:1210 |
| 2775 | SUBU_S_PH_MMR2 = 2760, // MicroMipsDSPInstrInfo.td:552 |
| 2776 | SUBU_S_QB = 2761, // MipsDSPInstrInfo.td:1091 |
| 2777 | SUBU_S_QB_MM = 2762, // MicroMipsDSPInstrInfo.td:451 |
| 2778 | SUBVI_B = 2763, // MipsMSAInstrInfo.td:3413 |
| 2779 | SUBVI_D = 2764, // MipsMSAInstrInfo.td:3416 |
| 2780 | SUBVI_H = 2765, // MipsMSAInstrInfo.td:3414 |
| 2781 | SUBVI_W = 2766, // MipsMSAInstrInfo.td:3415 |
| 2782 | SUBV_B = 2767, // MipsMSAInstrInfo.td:3408 |
| 2783 | SUBV_D = 2768, // MipsMSAInstrInfo.td:3411 |
| 2784 | SUBV_H = 2769, // MipsMSAInstrInfo.td:3409 |
| 2785 | SUBV_W = 2770, // MipsMSAInstrInfo.td:3410 |
| 2786 | SUB_MM = 2771, // MicroMipsInstrInfo.td:735 |
| 2787 | SUB_MMR6 = 2772, // MicroMips32r6InstrInfo.td:1343 |
| 2788 | SUBu = 2773, // MipsInstrInfo.td:2081 |
| 2789 | SUBu_MM = 2774, // MicroMipsInstrInfo.td:728 |
| 2790 | SUXC1 = 2775, // MipsInstrFPU.td:708 |
| 2791 | SUXC164 = 2776, // MipsInstrFPU.td:716 |
| 2792 | SUXC1_MM = 2777, // MicroMipsInstrFPU.td:53 |
| 2793 | SW = 2778, // MipsInstrInfo.td:2147 |
| 2794 | SW16_MM = 2779, // MicroMipsInstrInfo.td:632 |
| 2795 | SW16_MMR6 = 2780, // MicroMips32r6InstrInfo.td:1345 |
| 2796 | SW64 = 2781, // Mips64InstrInfo.td:210 |
| 2797 | SWC1 = 2782, // MipsInstrFPU.td:659 |
| 2798 | SWC1_MM = 2783, // MicroMipsInstrFPU.td:299 |
| 2799 | SWC2 = 2784, // MipsInstrInfo.td:2165 |
| 2800 | SWC2_MMR6 = 2785, // MicroMips32r6InstrInfo.td:1548 |
| 2801 | SWC2_R6 = 2786, // Mips32r6InstrInfo.td:932 |
| 2802 | SWC3 = 2787, // MipsInstrInfo.td:2178 |
| 2803 | SWDSP = 2788, // MipsDSPInstrInfo.td:1268 |
| 2804 | SWDSP_MM = 2789, // MicroMipsDSPInstrInfo.td:394 |
| 2805 | SWE = 2790, // MipsEVAInstrInfo.td:182 |
| 2806 | SWE_MM = 2791, // MicroMipsInstrInfo.td:821 |
| 2807 | SWL = 2792, // MipsInstrInfo.td:2157 |
| 2808 | SWL64 = 2793, // Mips64InstrInfo.td:231 |
| 2809 | SWLE = 2794, // MipsEVAInstrInfo.td:187 |
| 2810 | SWLE_MM = 2795, // MicroMipsInstrInfo.td:829 |
| 2811 | SWL_MM = 2796, // MicroMipsInstrInfo.td:845 |
| 2812 | SWM16_MM = 2797, // MicroMipsInstrInfo.td:685 |
| 2813 | SWM16_MMR6 = 2798, // MicroMips32r6InstrInfo.td:1346 |
| 2814 | SWM32_MM = 2799, // MicroMipsInstrInfo.td:851 |
| 2815 | SWP_MM = 2800, // MicroMipsInstrInfo.td:855 |
| 2816 | SWR = 2801, // MipsInstrInfo.td:2159 |
| 2817 | SWR64 = 2802, // Mips64InstrInfo.td:233 |
| 2818 | SWRE = 2803, // MipsEVAInstrInfo.td:188 |
| 2819 | SWRE_MM = 2804, // MicroMipsInstrInfo.td:832 |
| 2820 | SWR_MM = 2805, // MicroMipsInstrInfo.td:847 |
| 2821 | SWSP_MM = 2806, // MicroMipsInstrInfo.td:639 |
| 2822 | SWSP_MMR6 = 2807, // MicroMips32r6InstrInfo.td:1347 |
| 2823 | SWXC1 = 2808, // MipsInstrFPU.td:686 |
| 2824 | SWXC1_MM = 2809, // MicroMipsInstrFPU.td:48 |
| 2825 | SW_MM = 2810, // MicroMipsInstrInfo.td:802 |
| 2826 | SW_MMR6 = 2811, // MicroMips32r6InstrInfo.td:1367 |
| 2827 | SYNC = 2812, // MipsInstrInfo.td:2192 |
| 2828 | SYNCI = 2813, // MipsInstrInfo.td:2193 |
| 2829 | SYNCI_MM = 2814, // MicroMipsInstrInfo.td:985 |
| 2830 | SYNCI_MMR6 = 2815, // MicroMips32r6InstrInfo.td:1358 |
| 2831 | SYNC_MM = 2816, // MicroMipsInstrInfo.td:983 |
| 2832 | SYNC_MMR6 = 2817, // MicroMips32r6InstrInfo.td:1357 |
| 2833 | SYSCALL = 2818, // MipsInstrInfo.td:2233 |
| 2834 | SYSCALL_MM = 2819, // MicroMipsInstrInfo.td:988 |
| 2835 | Save16 = 2820, // Mips16InstrInfo.td:964 |
| 2836 | SaveX16 = 2821, // Mips16InstrInfo.td:972 |
| 2837 | SbRxRyOffMemX16 = 2822, // Mips16InstrInfo.td:985 |
| 2838 | SebRx16 = 2823, // Mips16InstrInfo.td:993 |
| 2839 | SehRx16 = 2824, // Mips16InstrInfo.td:1001 |
| 2840 | ShRxRyOffMemX16 = 2825, // Mips16InstrInfo.td:1124 |
| 2841 | SllX16 = 2826, // Mips16InstrInfo.td:1132 |
| 2842 | SllvRxRy16 = 2827, // Mips16InstrInfo.td:1139 |
| 2843 | SltRxRy16 = 2828, // Mips16InstrInfo.td:1192 |
| 2844 | SltiRxImm16 = 2829, // Mips16InstrInfo.td:1146 |
| 2845 | SltiRxImmX16 = 2830, // Mips16InstrInfo.td:1156 |
| 2846 | SltiuRxImm16 = 2831, // Mips16InstrInfo.td:1167 |
| 2847 | SltiuRxImmX16 = 2832, // Mips16InstrInfo.td:1177 |
| 2848 | SltuRxRy16 = 2833, // Mips16InstrInfo.td:1202 |
| 2849 | SraX16 = 2834, // Mips16InstrInfo.td:1228 |
| 2850 | SravRxRy16 = 2835, // Mips16InstrInfo.td:1219 |
| 2851 | SrlX16 = 2836, // Mips16InstrInfo.td:1246 |
| 2852 | SrlvRxRy16 = 2837, // Mips16InstrInfo.td:1237 |
| 2853 | SubuRxRyRz16 = 2838, // Mips16InstrInfo.td:1253 |
| 2854 | SwRxRyOffMemX16 = 2839, // Mips16InstrInfo.td:1261 |
| 2855 | SwRxSpImmX16 = 2840, // Mips16InstrInfo.td:1269 |
| 2856 | TEQ = 2841, // MipsInstrInfo.td:2204 |
| 2857 | TEQI = 2842, // MipsInstrInfo.td:2217 |
| 2858 | TEQI_MM = 2843, // MicroMipsInstrInfo.td:1015 |
| 2859 | TEQ_MM = 2844, // MicroMipsInstrInfo.td:1002 |
| 2860 | TGE = 2845, // MipsInstrInfo.td:2206 |
| 2861 | TGEI = 2846, // MipsInstrInfo.td:2219 |
| 2862 | TGEIU = 2847, // MipsInstrInfo.td:2221 |
| 2863 | TGEIU_MM = 2848, // MicroMipsInstrInfo.td:1019 |
| 2864 | TGEI_MM = 2849, // MicroMipsInstrInfo.td:1017 |
| 2865 | TGEU = 2850, // MipsInstrInfo.td:2208 |
| 2866 | TGEU_MM = 2851, // MicroMipsInstrInfo.td:1006 |
| 2867 | TGE_MM = 2852, // MicroMipsInstrInfo.td:1004 |
| 2868 | TLBGINV = 2853, // MipsInstrInfo.td:2689 |
| 2869 | TLBGINVF = 2854, // MipsInstrInfo.td:2691 |
| 2870 | TLBGINVF_MM = 2855, // MicroMipsInstrInfo.td:1132 |
| 2871 | TLBGINV_MM = 2856, // MicroMipsInstrInfo.td:1130 |
| 2872 | TLBGP = 2857, // MipsInstrInfo.td:2693 |
| 2873 | TLBGP_MM = 2858, // MicroMipsInstrInfo.td:1134 |
| 2874 | TLBGR = 2859, // MipsInstrInfo.td:2695 |
| 2875 | TLBGR_MM = 2860, // MicroMipsInstrInfo.td:1136 |
| 2876 | TLBGWI = 2861, // MipsInstrInfo.td:2697 |
| 2877 | TLBGWI_MM = 2862, // MicroMipsInstrInfo.td:1138 |
| 2878 | TLBGWR = 2863, // MipsInstrInfo.td:2699 |
| 2879 | TLBGWR_MM = 2864, // MicroMipsInstrInfo.td:1140 |
| 2880 | TLBINV = 2865, // MipsEVAInstrInfo.td:195 |
| 2881 | TLBINVF = 2866, // MipsEVAInstrInfo.td:196 |
| 2882 | TLBINVF_MMR6 = 2867, // MicroMips32r6InstrInfo.td:1525 |
| 2883 | TLBINV_MMR6 = 2868, // MicroMips32r6InstrInfo.td:1523 |
| 2884 | TLBP = 2869, // MipsInstrInfo.td:2558 |
| 2885 | TLBP_MM = 2870, // MicroMipsInstrInfo.td:1064 |
| 2886 | TLBR = 2871, // MipsInstrInfo.td:2559 |
| 2887 | TLBR_MM = 2872, // MicroMipsInstrInfo.td:1066 |
| 2888 | TLBWI = 2873, // MipsInstrInfo.td:2560 |
| 2889 | TLBWI_MM = 2874, // MicroMipsInstrInfo.td:1068 |
| 2890 | TLBWR = 2875, // MipsInstrInfo.td:2561 |
| 2891 | TLBWR_MM = 2876, // MicroMipsInstrInfo.td:1070 |
| 2892 | TLT = 2877, // MipsInstrInfo.td:2210 |
| 2893 | TLTI = 2878, // MipsInstrInfo.td:2223 |
| 2894 | TLTIU_MM = 2879, // MicroMipsInstrInfo.td:1023 |
| 2895 | TLTI_MM = 2880, // MicroMipsInstrInfo.td:1021 |
| 2896 | TLTU = 2881, // MipsInstrInfo.td:2212 |
| 2897 | TLTU_MM = 2882, // MicroMipsInstrInfo.td:1010 |
| 2898 | TLT_MM = 2883, // MicroMipsInstrInfo.td:1008 |
| 2899 | TNE = 2884, // MipsInstrInfo.td:2214 |
| 2900 | TNEI = 2885, // MipsInstrInfo.td:2227 |
| 2901 | TNEI_MM = 2886, // MicroMipsInstrInfo.td:1025 |
| 2902 | TNE_MM = 2887, // MicroMipsInstrInfo.td:1012 |
| 2903 | TRUNC_L_D64 = 2888, // MipsInstrFPU.td:469 |
| 2904 | TRUNC_L_D_MMR6 = 2889, // MicroMips32r6InstrInfo.td:1447 |
| 2905 | TRUNC_L_S = 2890, // MipsInstrFPU.td:467 |
| 2906 | TRUNC_L_S_MMR6 = 2891, // MicroMips32r6InstrInfo.td:1445 |
| 2907 | TRUNC_W_D32 = 2892, // MipsInstrFPU.td:179 |
| 2908 | TRUNC_W_D64 = 2893, // MipsInstrFPU.td:180 |
| 2909 | TRUNC_W_D_MMR6 = 2894, // MicroMips32r6InstrInfo.td:1451 |
| 2910 | TRUNC_W_MM = 2895, // MicroMipsInstrFPU.td:98 |
| 2911 | TRUNC_W_S = 2896, // MipsInstrFPU.td:417 |
| 2912 | TRUNC_W_S_MM = 2897, // MicroMipsInstrFPU.td:233 |
| 2913 | TRUNC_W_S_MMR6 = 2898, // MicroMips32r6InstrInfo.td:1449 |
| 2914 | TTLTIU = 2899, // MipsInstrInfo.td:2225 |
| 2915 | UDIV = 2900, // MipsInstrInfo.td:2392 |
| 2916 | UDIV_MM = 2901, // MicroMipsInstrInfo.td:755 |
| 2917 | V3MULU = 2902, // Mips64InstrInfo.td:587 |
| 2918 | VMM0 = 2903, // Mips64InstrInfo.td:593 |
| 2919 | VMULU = 2904, // Mips64InstrInfo.td:599 |
| 2920 | VSHF_B = 2905, // MipsMSAInstrInfo.td:3418 |
| 2921 | VSHF_D = 2906, // MipsMSAInstrInfo.td:3421 |
| 2922 | VSHF_H = 2907, // MipsMSAInstrInfo.td:3419 |
| 2923 | VSHF_W = 2908, // MipsMSAInstrInfo.td:3420 |
| 2924 | WAIT = 2909, // MipsInstrInfo.td:2249 |
| 2925 | WAIT_MM = 2910, // MicroMipsInstrInfo.td:990 |
| 2926 | WAIT_MMR6 = 2911, // MicroMips32r6InstrInfo.td:1355 |
| 2927 | WRDSP = 2912, // MipsDSPInstrInfo.td:1203 |
| 2928 | WRDSP_MM = 2913, // MicroMipsDSPInstrInfo.td:500 |
| 2929 | WRPGPR_MMR6 = 2914, // MicroMips32r6InstrInfo.td:1348 |
| 2930 | WSBH = 2915, // MipsInstrInfo.td:2416 |
| 2931 | WSBH_MM = 2916, // MicroMipsInstrInfo.td:913 |
| 2932 | WSBH_MMR6 = 2917, // MicroMips32r6InstrInfo.td:1350 |
| 2933 | XOR = 2918, // MipsInstrInfo.td:2101 |
| 2934 | XOR16_MM = 2919, // MicroMipsInstrInfo.td:617 |
| 2935 | XOR16_MMR6 = 2920, // MicroMips32r6InstrInfo.td:1484 |
| 2936 | XOR64 = 2921, // Mips64InstrInfo.td:160 |
| 2937 | XORI_B = 2922, // MipsMSAInstrInfo.td:3437 |
| 2938 | XORI_MMR6 = 2923, // MicroMips32r6InstrInfo.td:1365 |
| 2939 | XOR_MM = 2924, // MicroMipsInstrInfo.td:745 |
| 2940 | XOR_MMR6 = 2925, // MicroMips32r6InstrInfo.td:1364 |
| 2941 | XOR_V = 2926, // MipsMSAInstrInfo.td:3423 |
| 2942 | XORi = 2927, // MipsInstrInfo.td:2065 |
| 2943 | XORi64 = 2928, // Mips64InstrInfo.td:136 |
| 2944 | XORi_MM = 2929, // MicroMipsInstrInfo.td:716 |
| 2945 | XorRxRxRy16 = 2930, // Mips16InstrInfo.td:1277 |
| 2946 | YIELD = 2931, // MipsMTInstrInfo.td:102 |
| 2947 | INSTRUCTION_LIST_END = 2932 |
| 2948 | }; |
| 2949 | enum RegClassByHwModeUses : uint16_t { |
| 2950 | mips_ptr_rc, |
| 2951 | ptr_gp_rc, |
| 2952 | ptr_gpr16mm_rc, |
| 2953 | ptr_sp_rc, |
| 2954 | }; |
| 2955 | |
| 2956 | } // namespace llvm::Mips |
| 2957 | |
| 2958 | #endif // GET_INSTRINFO_ENUM |
| 2959 | |
| 2960 | #ifdef GET_INSTRINFO_SCHED_ENUM |
| 2961 | #undef GET_INSTRINFO_SCHED_ENUM |
| 2962 | |
| 2963 | namespace llvm::Mips::Sched { |
| 2964 | |
| 2965 | enum { |
| 2966 | NoInstrModel = 0, |
| 2967 | SB_SD_SH_SW_SDC1_SDC164_SWC1_SWC2_R6_SDC2_R6_SDC3 = 1, |
| 2968 | SC_R6_SCD_R6_SYNCI_TLBP_TLBR_TLBWI_TLBWR_TLBINV_TLBINVF_CACHE_R6_SC64_R6 = 2, |
| 2969 | LB_LBu_LBu64_LD_LH_LHu_LHu64_LW_LWu_LDC1_LDC164_LWC1_LDC2_R6_LDC3_LWC2_R6_LLD_R6_LL_R6_LWPC_LWUPC_LDPC_ST_B_ST_H_ST_W_ST_D_LB64_LH64_LW64_LWL64_LWR64_SB64_SH64_SW64_SWL64_SWR64_LL64_R6 = 3, |
| 2970 | PREF_PREF_R6_PAUSE = 4, |
| 2971 | SYNC = 5, |
| 2972 | J_JAL_JALR_B_BEQ_BNE_BGEZ_BGTZ_BLEZ_BLTZ_JALR64_JALR64Pseudo_JIALC_JIALC64_JIC_JIC64_JR64_JR_HB_R6_JR_HB64_R6_NAL_SDBBP_R6_SYSCALL_BEQC64_BEQZC64_BGEC64_BGEUC64_BGTZC64_BLEZC64_BLTC64_BLTUC64_BNEC64_BNEZC64_PseudoIndirectBranchR6_BC_BALC_BEQZC_BNEZC_BLEZC_BGEZC_BGTZC_BLTZC_BEQZALC_BNEZALC_BLEZALC_BGEZALC_BGTZALC_BLTZALC_BEQC_BNEC_BGEC_BLTC_BGEUC_BLTUC_BAL_BOVC_BNVC_BC1EQZ_BC1NEZ_BREAK_ERET_ERETNC_BAL_BR_DERET_JALRHBPseudo_JALRPseudo_JALR_HB_JALR_HB64_TAILCALL_PseudoIndirectBranch64R6_TAILCALL64R6REG_TAILCALLR6REG_PseudoIndrectHazardBranch64R6_PseudoIndrectHazardBranchR6_TAILCALLHB64R6REG_TAILCALLHBR6REG_PseudoReturn_PseudoReturn64_ERet_RetRA_BC2EQZ_BC2NEZ_TLT_TLTU_TNE_WAIT_DI_TRAP_EI_BEQ64_BGEZ64_BGEZC64_BGTZ64_BLEZ64_BLTZ64_BLTZC64_BNE64_JALRHB64Pseudo = 6, |
| 2973 | ADD_ADDiu_ADDIUPC_ADDu_ALIGN_ALUIPC_AND_ANDi_AUI_AUIPC_BITSWAP_CFC1_CLO_R6_CLZ_R6_CTC1_DADD_DADDiu_DADDu_DAHI_DALIGN_DATI_DAUI_DBITSWAP_DCLO_R6_DCLZ_R6_DEXT_DEXT64_32_DEXTM_DEXTU_DINS_DINSM_DINSU_DLSA_R6_DMFC1_DMTC1_DROTR_DROTR32_DROTRV_DSBH_DSHD_DSLL_DSLL32_DSLLV_DSRA_DSRA32_DSRAV_DSRL_DSRL32_DSRLV_DSUB_DSUBu_EXT_INS_LSA_LSA_R6_LUi_MFC1_MFC1_D64_MFC0_MFC2_MTC0_MTC2_MFHC1_D32_MFHC1_D64_MTC1_MTC1_D64_MTHC1_D32_MTHC1_D64_NOP_NOR_OR_ORi_ROTR_ROTRV_SEB_SEB64_SEH_SEH64_SELEQZ_SELEQZ64_SELNEZ_SELNEZ64_SLL_SLLV_SLT_SLTi_SLTiu_SLTu_SRA_SRAV_SRL_SRLV_SSNOP_SUB_SUBu_WSBH_XOR_XORi_SLT64_SLTu64_AND64_OR64_XOR64_NOR64_SLTi64_SLTiu64_ANDi64_ORi64_XORi64_LUi64_DSLL64_32_SLL64_32_SLL64_64_LONG_BRANCH_LUi2Op_64_LONG_BRANCH_DADDiu2Op_LONG_BRANCH_DADDiu_DLSA_TEQ_TGE_TGEU_COPY_BuildPairF64_BuildPairF64_64_ExtractElementF64_ExtractElementF64_64_SELNEZ_D_SELNEZ_S_SELEQZ_D_SELEQZ_S_SEL_D_SEL_S_EHB_RDHWR_RDHWR64_EVP_DVP_DMFC0_DMFC2_DMTC0_DMTC2 = 7, |
| 2974 | MUL_R6_MULU_MUH_MUHU_DMUL_R6_DMUH_DMULU_DMUHU = 8, |
| 2975 | DIV_DIVU_MOD_MODU_DDIV_DMOD_DDIVU_DMODU = 9, |
| 2976 | MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 10, |
| 2977 | FABS_S_FNEG_S_FMOV_S_FMOV_D32_FMOV_D64_FNEG_D32_FNEG_D64_CLASS_S_CLASS_D = 11, |
| 2978 | FADD_S_FSUB_S_FSUB_D32_FSUB_D64 = 12, |
| 2979 | FMUL_S_FMUL_D32_FMUL_D64 = 13, |
| 2980 | FDIV_S_FSQRT_S_FDIV_D32_FDIV_D64_FSQRT_D_FSQRT_D32_FSQRT_D64_FSQRT_W_RECIP_S_RECIP_D32_RECIP_D64_FRSQRT_D_FRSQRT_W_RSQRT_S_RSQRT_D32_RSQRT_D64_FRCP_D_FRCP_W = 14, |
| 2981 | DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W = 15, |
| 2982 | DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 16, |
| 2983 | ADDV_B_ADDV_H_ADDV_W_ADDV_D_ADDVI_B_ADDVI_H_ADDVI_W_ADDVI_D_SUBV_B_SUBV_H_SUBV_W_SUBV_D_SUBVI_B_SUBVI_H_SUBVI_W_SUBVI_D = 17, |
| 2984 | ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W = 18, |
| 2985 | ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 19, |
| 2986 | SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 20, |
| 2987 | MAX_D_MAX_S_MAXA_D_MAXA_S_MIN_D_MIN_S_MINA_D_MINA_S = 21, |
| 2988 | ADD_A_B_ADD_A_H_ADD_A_W_ADD_A_D_ADDS_A_B_ADDS_A_H_ADDS_A_W_ADDS_A_D_ADDS_S_B_ADDS_S_H_ADDS_S_W_ADDS_S_D_ADDS_U_B_ADDS_U_H_ADDS_U_W_ADDS_U_D_HADD_S_H_HADD_S_W_HADD_S_D_HADD_U_H_HADD_U_W_HADD_U_D_SUBS_S_B_SUBS_S_H_SUBS_S_W_SUBS_S_D_SUBS_U_B_SUBS_U_H_SUBS_U_W_SUBS_U_D_SUBSUU_S_B_SUBSUU_S_H_SUBSUU_S_W_SUBSUU_S_D_HSUB_S_H_HSUB_S_W_HSUB_S_D_HSUB_U_H_HSUB_U_W_HSUB_U_D_AVE_S_B_AVE_S_H_AVE_S_W_AVE_S_D_AVE_U_B_AVE_U_H_AVE_U_W_AVE_U_D_AVER_S_B_AVER_S_H_AVER_S_W_AVER_S_D_AVER_U_B_AVER_U_H_AVER_U_W_AVER_U_D_MIN_A_B_MIN_A_H_MIN_A_W_MIN_A_D_MIN_S_B_MIN_S_H_MIN_S_W_MIN_S_D_MIN_U_B_MIN_U_H_MIN_U_W_MIN_U_D_MINI_S_B_MINI_S_H_MINI_S_W_MINI_S_D_MINI_U_B_MINI_U_H_MINI_U_W_MINI_U_D_MAX_A_B_MAX_A_H_MAX_A_W_MAX_A_D_MAX_S_B_MAX_S_H_MAX_S_W_MAX_S_D_MAX_U_B_MAX_U_H_MAX_U_W_MAX_U_D_MAXI_S_B_MAXI_S_H_MAXI_S_W_MAXI_S_D_MAXI_U_B_MAXI_U_H_MAXI_U_W_MAXI_U_D_CEQ_B_CEQ_H_CEQ_W_CEQ_D_CEQI_B_CEQI_H_CEQI_W_CEQI_D_CLE_S_B_CLE_S_H_CLE_S_W_CLE_S_D_CLE_U_B_CLE_U_H_CLE_U_W_CLE_U_D_CLEI_S_B_CLEI_S_H_CLEI_S_W_CLEI_S_D_CLEI_U_B_CLEI_U_H_CLEI_U_W_CLEI_U_D_CLT_S_B_CLT_S_H_CLT_S_W_CLT_S_D_CLT_U_B_CLT_U_H_CLT_U_W_CLT_U_D_CLTI_S_B_CLTI_S_H_CLTI_S_W_CLTI_S_D_CLTI_U_B_CLTI_U_H_CLTI_U_W_CLTI_U_D = 22, |
| 2989 | SAT_S_B_SAT_S_H_SAT_S_W_SAT_S_D_SAT_U_B_SAT_U_H_SAT_U_W_SAT_U_D_PCNT_B_PCNT_H_PCNT_W_PCNT_D = 23, |
| 2990 | SLL_B_SLL_H_SLL_W_SLL_D_SLLI_B_SLLI_H_SLLI_W_SLLI_D_SRA_B_SRA_H_SRA_W_SRA_D_SRAI_B_SRAI_H_SRAI_W_SRAI_D_SRAR_B_SRAR_H_SRAR_W_SRAR_D_SRARI_B_SRARI_H_SRARI_W_SRARI_D_SRL_B_SRL_H_SRL_W_SRL_D_SRLI_B_SRLI_H_SRLI_W_SRLI_D_SRLR_B_SRLR_H_SRLR_W_SRLR_D_SRLRI_B_SRLRI_H_SRLRI_W_SRLRI_D_NLOC_B_NLOC_H_NLOC_W_NLOC_D_NLZC_B_NLZC_H_NLZC_W_NLZC_D_BNEG_B_BNEG_H_BNEG_W_BNEG_D_BNEGI_B_BNEGI_H_BNEGI_W_BNEGI_D_BCLR_B_BCLR_H_BCLR_W_BCLR_D_BCLRI_B_BCLRI_H_BCLRI_W_BCLRI_D_SHF_B_SHF_H_SHF_W_FABS_W_FABS_D = 24, |
| 2991 | AND_V_ANDI_B_OR_V_ORI_B_XOR_V_XORI_B_NOR_V_NORI_B = 25, |
| 2992 | NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO = 26, |
| 2993 | OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO = 27, |
| 2994 | XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 28, |
| 2995 | AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO = 29, |
| 2996 | ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W = 30, |
| 2997 | ILVL_B_ILVL_D_ILVL_H_ILVL_W = 31, |
| 2998 | ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 32, |
| 2999 | ILVR_B_ILVR_D_ILVR_H_ILVR_W = 33, |
| 3000 | PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W = 34, |
| 3001 | PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 35, |
| 3002 | FILL_B_FILL_D_FILL_H_FILL_W = 36, |
| 3003 | FILL_FD_PSEUDO_FILL_FW_PSEUDO = 37, |
| 3004 | INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 38, |
| 3005 | SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 39, |
| 3006 | SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W = 40, |
| 3007 | CTCMSA_CFCMSA_COPY_S_B_COPY_S_H_COPY_S_W_COPY_S_D_COPY_U_B_COPY_U_H_COPY_U_W_BNZ_B_BNZ_H_BNZ_W_BNZ_D_BNZ_V_BZ_B_BZ_H_BZ_W_BZ_D_BZ_V = 41, |
| 3008 | LD_B_LD_H_LD_W_LD_D = 42, |
| 3009 | LDI_B_LDI_H_LDI_W_LDI_D_MOVE_V = 43, |
| 3010 | FCAF_W_FCAF_D_FCUN_W_FCUN_D_FCOR_W_FCOR_D_FCEQ_W_FCEQ_D_FCUNE_W_FCUNE_D_FCUEQ_W_FCUEQ_D_FCNE_W_FCNE_D_FCLT_W_FCLT_D_FCULT_W_FCULT_D_FCLE_W_FCLE_D_FCULE_W_FCULE_D_FSAF_W_FSAF_D_FSUN_W_FSUN_D_FSOR_W_FSOR_D_FSEQ_W_FSEQ_D_FSUNE_W_FSUNE_D_FSUEQ_W_FSUEQ_D_FSNE_W_FSNE_D_FSLT_W_FSLT_D_FSULT_W_FSULT_D_FSLE_W_FSLE_D_FSULE_W_FSULE_D = 44, |
| 3011 | FMAX_W_FMAX_D_FMAX_A_W_FMAX_A_D_FMIN_W_FMIN_D_FMIN_A_W_FMIN_A_D_FCLASS_W_FCLASS_D_FABS_D32_FABS_D64 = 45, |
| 3012 | CMP_UN_D_CMP_UN_S = 46, |
| 3013 | CMP_UEQ_D_CMP_UEQ_S = 47, |
| 3014 | CMP_EQ_D_CMP_EQ_S = 48, |
| 3015 | CMP_LT_D_CMP_LT_S = 49, |
| 3016 | CMP_ULT_D_CMP_ULT_S = 50, |
| 3017 | CMP_LE_D_CMP_LE_S = 51, |
| 3018 | CMP_ULE_D_CMP_ULE_S = 52, |
| 3019 | CMP_F_D_CMP_F_S = 53, |
| 3020 | CMP_SAF_D_CMP_SAF_S = 54, |
| 3021 | CMP_SEQ_D_CMP_SEQ_S = 55, |
| 3022 | CMP_SLE_D_CMP_SLE_S = 56, |
| 3023 | CMP_SLT_D_CMP_SLT_S = 57, |
| 3024 | CMP_SUEQ_D_CMP_SUEQ_S = 58, |
| 3025 | CMP_SULE_D_CMP_SULE_S = 59, |
| 3026 | CMP_SULT_D_CMP_SULT_S = 60, |
| 3027 | CMP_SUN_D_CMP_SUN_S = 61, |
| 3028 | TRUNC_W_S_TRUNC_L_S_TRUNC_L_D64_TRUNC_W_D32_TRUNC_W_D64_PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S_ROUND_W_S_ROUND_L_S_ROUND_L_D64_FLOOR_W_S_FLOOR_L_S_FLOOR_L_D64_CVT_D32_S_CVT_D32_W_CVT_D64_W_CVT_D64_S_CVT_D64_L_CVT_L_S_CVT_L_D64_CVT_S_W_CVT_S_D32_CVT_S_PU64_CVT_S_PL64_CVT_S_L_CVT_S_D64_CVT_W_S_CEIL_W_S_CEIL_L_S_CEIL_L_D64_FLOOR_W_D32_FLOOR_W_D64_CVT_W_D64_CVT_W_D32_RINT_D_RINT_S_ROUND_W_D32_ROUND_W_D64_CEIL_W_D32_CEIL_W_D64 = 62, |
| 3029 | BMZ_V_BMZI_B_BMNZ_V_BMNZI_B_INSERT_B_INSERT_H_INSERT_W_INSERT_D_INSVE_B_INSVE_H_INSVE_W_INSVE_D = 63, |
| 3030 | BSELI_B_BSEL_V = 64, |
| 3031 | BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 65, |
| 3032 | BINSL_B_BINSL_H_BINSL_W_BINSL_D_BINSLI_B_BINSLI_H_BINSLI_W_BINSLI_D_BINSR_B_BINSR_H_BINSR_W_BINSR_D_BINSRI_B_BINSRI_H_BINSRI_W_BINSRI_D_VSHF_B_VSHF_H_VSHF_W_VSHF_D_SLD_B_SLD_H_SLD_W_SLD_D_SLDI_B_SLDI_H_SLDI_W_SLDI_D_BSET_B_BSET_H_BSET_W_BSET_D_BSETI_B_BSETI_H_BSETI_W_BSETI_D = 66, |
| 3033 | MADDV_B_MADDV_H_MADDV_W_MADDV_D_MSUBV_B_MSUBV_H_MSUBV_W_MSUBV_D_MULV_B_MULV_H_MULV_W_MULV_D_DOTP_S_H_DOTP_S_W_DOTP_S_D_DOTP_U_H_DOTP_U_W_DOTP_U_D_MUL_Q_H_MUL_Q_W_MULR_Q_H_MULR_Q_W_MSUB_Q_H_MSUB_Q_W_MSUBR_Q_H_MSUBR_Q_W_MADD_Q_H_MADD_Q_W_MADDR_Q_H_MADDR_Q_W = 67, |
| 3034 | FLOG2_W_FLOG2_D = 68, |
| 3035 | FADD_W_FADD_D_FSUB_W_FSUB_D_FEXDO_H_FEXDO_W_FEXUPL_W_FEXUPL_D_FEXUPR_W_FEXUPR_D_FFINT_S_W_FFINT_S_D_FFINT_U_W_FFINT_U_D_FFQL_W_FFQL_D_FFQR_W_FFQR_D_FTINT_S_W_FTINT_S_D_FTINT_U_W_FTINT_U_D_FTRUNC_S_W_FTRUNC_S_D_FTRUNC_U_W_FTRUNC_U_D_FTQ_H_FTQ_W_FRINT_W_FRINT_D_FADD_D32_FADD_D64 = 69, |
| 3036 | PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 70, |
| 3037 | FMUL_W_FMUL_D_FEXP2_W_FEXP2_D_DPADD_S_H_DPADD_S_W_DPADD_S_D_DPADD_U_H_DPADD_U_W_DPADD_U_D_DPSUB_S_H_DPSUB_S_W_DPSUB_S_D_DPSUB_U_H_DPSUB_U_W_DPSUB_U_D = 71, |
| 3038 | FMADD_W_FMADD_D_FMSUB_W_FMSUB_D = 72, |
| 3039 | MSUBF_D_MSUBF_S_MADDF_D_MADDF_S = 73, |
| 3040 | FDIV_D = 74, |
| 3041 | FDIV_W = 75, |
| 3042 | ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 76, |
| 3043 | ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 77, |
| 3044 | ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 78, |
| 3045 | AND_LUi_NOR_OR_SLTi_SLTiu_SUB_SUBu_XOR = 79, |
| 3046 | SSNOP_NOP = 80, |
| 3047 | B_BAL_BAL_BR_BEQ_BGEZ_BGTZ_BLEZ_BLTZ_BNE_BREAK_DERET_ERET_ERet_ERETNC_J_PseudoReturn_SYSCALL_RetRA_TAILCALL_TLT_TLTU_TNE_TRAP_WAIT = 81, |
| 3048 | BEQL_BGEZAL_BGEZALL_BGEZL_BGTZL_BLEZL_BLTZAL_BLTZALL_BLTZL_BNEL_JR_JR_HB_PseudoIndirectBranch_PseudoIndirectHazardBranch_SDBBP_TAILCALLREG_TAILCALLREGHB_TEQI_TGEI_TGEIU_TLTI_TNEI_TTLTIU = 82, |
| 3049 | TEQ_TGE_TGEU = 83, |
| 3050 | PAUSE = 84, |
| 3051 | JAL_JALR_JALRHBPseudo_JALRPseudo_JALR_HB = 85, |
| 3052 | JALX = 86, |
| 3053 | TLBINV_TLBINVF_TLBP_TLBR_TLBWI_TLBWR = 87, |
| 3054 | MFC0_MTC0 = 88, |
| 3055 | MFC2_MTC2 = 89, |
| 3056 | HYPCALL_MFGC0_MFHGC0_MTGC0_MTHGC0_TLBGINV_TLBGINVF_TLBGP_TLBGR_TLBGWI_TLBGWR = 90, |
| 3057 | LB_LBu_LH_LHu_LW_LDC3_LWPC = 91, |
| 3058 | LL_LWC2_LWC3_LDC2_LBE_LBuE_LHE_LHuE_LWE_LLE = 92, |
| 3059 | LWL_LWR_LWLE_LWRE = 93, |
| 3060 | SB_SH_SW_SDC3 = 94, |
| 3061 | SWC2_SWC3_SDC2_SC_SBE_SHE_SWE_SCE_SWL_SWR_SWLE_SWRE = 95, |
| 3062 | PREF = 96, |
| 3063 | PREFE_CACHE_CACHEE = 97, |
| 3064 | SYNCI = 98, |
| 3065 | CLO_CLZ_MFHI_MFLO_PseudoMFHI_PseudoMFLO = 99, |
| 3066 | DI_EI = 100, |
| 3067 | EHB_RDHWR_WSBH = 101, |
| 3068 | MOVN_I_I_MOVZ_I_I = 102, |
| 3069 | DIV = 103, |
| 3070 | PseudoSDIV_SDIV = 104, |
| 3071 | DIVU = 105, |
| 3072 | PseudoUDIV_UDIV = 106, |
| 3073 | MUL = 107, |
| 3074 | MULT_MULTu_PseudoMULT_PseudoMULTu = 108, |
| 3075 | MADD_MADDU_MSUB_MSUBU_MTHI_MTLO_PseudoMADD_PseudoMADDU_PseudoMSUB_PseudoMSUBU_PseudoMTLOHI = 109, |
| 3076 | EXT_INS = 110, |
| 3077 | ADD_ADDiu_ANDi_ORi_ROTR_SEB_SEH_SLT_SLTu_SLL_SRA_SRL_XORi_ADDu_SLLV_SRAV_SRLV_LSA_COPY = 111, |
| 3078 | ADDi = 112, |
| 3079 | VSHF_B_VSHF_D_VSHF_H_VSHF_W = 113, |
| 3080 | BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 114, |
| 3081 | BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 115, |
| 3082 | INSERT_B_INSERT_D_INSERT_H_INSERT_W = 116, |
| 3083 | SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 117, |
| 3084 | BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 118, |
| 3085 | FABS_D_FABS_W = 119, |
| 3086 | BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 120, |
| 3087 | BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 121, |
| 3088 | PCNT_B_PCNT_D_PCNT_H_PCNT_W = 122, |
| 3089 | BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 123, |
| 3090 | CFCMSA_CTCMSA = 124, |
| 3091 | FABS_S_FMOV_D32_FMOV_D64_FMOV_S_FNEG_S_FNEG_D32_FNEG_D64 = 125, |
| 3092 | FABS_D32_FABS_D64 = 126, |
| 3093 | MOVF_D32_MOVF_D64_MOVF_S_MOVT_D32_MOVT_D64_MOVT_S = 127, |
| 3094 | ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 128, |
| 3095 | ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 129, |
| 3096 | ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 130, |
| 3097 | AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 131, |
| 3098 | SHF_B_SHF_H_SHF_W = 132, |
| 3099 | MOVE_V = 133, |
| 3100 | AND_V_NOR_V_OR_V_XOR_V = 134, |
| 3101 | FEXP2_D_FEXP2_W = 135, |
| 3102 | CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 136, |
| 3103 | CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 137, |
| 3104 | CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 138, |
| 3105 | FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 139, |
| 3106 | FSUEQ_D_FSUEQ_W = 140, |
| 3107 | FSULE_D_FSULE_W = 141, |
| 3108 | FSULT_D_FSULT_W = 142, |
| 3109 | FSUNE_D_FSUNE_W = 143, |
| 3110 | FSUN_D_FSUN_W = 144, |
| 3111 | FCAF_D_FCAF_W = 145, |
| 3112 | FCEQ_D_FCEQ_W = 146, |
| 3113 | FCLE_D_FCLE_W = 147, |
| 3114 | FCLT_D_FCLT_W = 148, |
| 3115 | FCNE_D_FCNE_W = 149, |
| 3116 | FCOR_D_FCOR_W = 150, |
| 3117 | FCUEQ_D_FCUEQ_W = 151, |
| 3118 | FCULE_D_FCULE_W = 152, |
| 3119 | FCULT_D_FCULT_W = 153, |
| 3120 | FCUNE_D_FCUNE_W = 154, |
| 3121 | FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 155, |
| 3122 | FFQL_D_FFQL_W = 156, |
| 3123 | FFQR_D_FFQR_W = 157, |
| 3124 | FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 158, |
| 3125 | FRINT_D_FRINT_W = 159, |
| 3126 | FTQ_H_FTQ_W = 160, |
| 3127 | FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 161, |
| 3128 | FEXDO_H_FEXDO_W = 162, |
| 3129 | FEXUPL_D_FEXUPL_W = 163, |
| 3130 | FEXUPR_D_FEXUPR_W = 164, |
| 3131 | FCLASS_D_FCLASS_W = 165, |
| 3132 | FMAX_A_D_FMAX_A_W = 166, |
| 3133 | FMAX_D_FMAX_W = 167, |
| 3134 | FMIN_A_D_FMIN_A_W = 168, |
| 3135 | SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 169, |
| 3136 | SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 170, |
| 3137 | SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 171, |
| 3138 | HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 172, |
| 3139 | HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 173, |
| 3140 | MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 174, |
| 3141 | MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 175, |
| 3142 | MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 176, |
| 3143 | SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 177, |
| 3144 | SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 178, |
| 3145 | SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 179, |
| 3146 | SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 180, |
| 3147 | SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 181, |
| 3148 | FADD_D32_FADD_D64 = 182, |
| 3149 | FADD_PS64_FMUL_PS64_FSUB_PS64 = 183, |
| 3150 | TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 184, |
| 3151 | CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 185, |
| 3152 | CVT_PS_S64 = 186, |
| 3153 | CVT_S_PL64_CVT_S_PU64 = 187, |
| 3154 | C_EQ_D32_C_EQ_D64_C_EQ_S_C_F_D32_C_F_D64_C_F_S_C_LE_D32_C_LE_D64_C_LE_S_C_LT_D32_C_LT_D64_C_LT_S_C_NGE_D32_C_NGE_D64_C_NGE_S_C_NGLE_D32_C_NGLE_D64_C_NGLE_S_C_NGL_D32_C_NGL_D64_C_NGL_S_C_NGT_D32_C_NGT_D64_C_NGT_S_C_OLE_D32_C_OLE_D64_C_OLE_S_C_OLT_D32_C_OLT_D64_C_OLT_S_C_SEQ_D32_C_SEQ_D64_C_SEQ_S_C_SF_D32_C_SF_D64_C_SF_S_C_UEQ_D32_C_UEQ_D64_C_UEQ_S_C_ULE_D32_C_ULE_D64_C_ULE_S_C_ULT_D32_C_ULT_D64_C_ULT_S_C_UN_D32_C_UN_D64_C_UN_S = 188, |
| 3155 | FCMP_D32_FCMP_D64_FCMP_S32 = 189, |
| 3156 | PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 190, |
| 3157 | FDIV_S = 191, |
| 3158 | FDIV_D32_FDIV_D64 = 192, |
| 3159 | FSQRT_S = 193, |
| 3160 | FSQRT_D32_FSQRT_D64 = 194, |
| 3161 | FRCP_D_FRCP_W = 195, |
| 3162 | FRSQRT_D_FRSQRT_W = 196, |
| 3163 | RECIP_D32_RECIP_D64_RSQRT_D32_RSQRT_D64 = 197, |
| 3164 | RECIP_S_RSQRT_S = 198, |
| 3165 | FMADD_D_FMADD_W = 199, |
| 3166 | FSQRT_W = 200, |
| 3167 | FMUL_D_FMUL_W = 201, |
| 3168 | FADD_D_FADD_W = 202, |
| 3169 | DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 203, |
| 3170 | DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 204, |
| 3171 | MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 205, |
| 3172 | MADDV_B_MADDV_D_MADDV_H_MADDV_W = 206, |
| 3173 | MULV_B_MULV_D_MULV_H_MULV_W = 207, |
| 3174 | MADDR_Q_H_MADDR_Q_W = 208, |
| 3175 | MADD_Q_H_MADD_Q_W = 209, |
| 3176 | MSUBR_Q_H_MSUBR_Q_W = 210, |
| 3177 | MSUB_Q_H_MSUB_Q_W = 211, |
| 3178 | MULR_Q_H_MULR_Q_W = 212, |
| 3179 | MADD_D32_MADD_D64_MADD_S_MSUB_D32_MSUB_D64_MSUB_S_NMADD_D32_NMADD_D64_NMADD_S_NMSUB_D32_NMSUB_D64_NMSUB_S = 213, |
| 3180 | CTC1_MTC1_MTC1_D64_MTHC1_D32_MTHC1_D64_BuildPairF64_BuildPairF64_64 = 214, |
| 3181 | BuildPairF64_FPR = 215, |
| 3182 | COPY_U_B_COPY_U_H_COPY_U_W = 216, |
| 3183 | BC1F_BC1FL_BC1T_BC1TL_MOVF_I_MOVT_I = 217, |
| 3184 | CFC1_MFC1_MFC1_D64_MFHC1_D32_MFHC1_D64_ExtractElementF64_ExtractElementF64_64 = 218, |
| 3185 | SDC1_SDC164_SWC1 = 219, |
| 3186 | SDXC1_SDXC164_SWXC1_SUXC1_SUXC164 = 220, |
| 3187 | ST_B_ST_D_ST_H_ST_W = 221, |
| 3188 | MOVN_I_D32_MOVN_I_D64_MOVN_I_S_MOVZ_I_D32_MOVZ_I_D64_MOVZ_I_S = 222, |
| 3189 | LDC1_LDC164_LWC1 = 223, |
| 3190 | LDXC1_LDXC164_LWXC1_LUXC1_LUXC164 = 224, |
| 3191 | CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 225, |
| 3192 | FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 226, |
| 3193 | ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 227, |
| 3194 | ROTRV = 228, |
| 3195 | ADD_ADDiu_ADDu_ANDi_ORi_ROTR_SEB_SEH_SLL_SLLV_SLT_SLTu_SRA_SRAV_SRL_SRLV_XORi = 229, |
| 3196 | CLO_CLZ = 230, |
| 3197 | LEA_ADDiu = 231, |
| 3198 | WSBH = 232, |
| 3199 | COPY = 233, |
| 3200 | ADDIUPC_ALIGN_ALUIPC_AUI_AUIPC_BITSWAP_CLO_R6_CLZ_R6_LSA_R6_SELEQZ_SELNEZ = 234, |
| 3201 | AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiCCRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltiuCCRxImmX16_SltRxRy16_SltCCRxRy16_SltuRxRy16_SltuRxRyRz16_SltuCCRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 235, |
| 3202 | Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 236, |
| 3203 | ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDU16_MM_ADD_MM_ADDi_MM_ADDiu_MM_ADDu_MM_AND16_MM_ANDI16_MM_AND_MM_ANDi_MM_CLO_MM_CLZ_MM_EXT_MM_INS_MM_LEA_ADDiu_MM_LI16_MM_LUi_MM_MOVE16_MM_MOVEP_MM_NOR_MM_NOT16_MM_OR16_MM_OR_MM_ORi_MM_ROTRV_MM_ROTR_MM_SEB_MM_SEH_MM_SLL16_MM_SLLV_MM_SLL_MM_SLT_MM_SLTi_MM_SLTiu_MM_SLTu_MM_SRAV_MM_SRA_MM_SRL16_MM_SRLV_MM_SRL_MM_SSNOP_MM_SUBU16_MM_SUB_MM_SUBu_MM_WSBH_MM_XOR16_MM_XOR_MM_XORi_MM = 237, |
| 3204 | ADDIUPC_MMR6_ADDIU_MMR6_ADDU16_MMR6_ADDU_MMR6_ADD_MMR6_ALIGN_MMR6_ALUIPC_MMR6_AND16_MMR6_ANDI16_MMR6_ANDI_MMR6_AND_MMR6_AUIPC_MMR6_AUI_MMR6_BITSWAP_MMR6_CLO_MMR6_CLZ_MMR6_EXT_MMR6_INS_MMR6_LI16_MMR6_LSA_MMR6_LUI_MMR6_MOVE16_MMR6_NOR_MMR6_NOT16_MMR6_OR16_MMR6_ORI_MMR6_OR_MMR6_SELEQZ_MMR6_SELNEZ_MMR6_SLL16_MMR6_SLL_MMR6_SRL16_MMR6_SSNOP_MMR6_SUBU16_MMR6_SUBU_MMR6_SUB_MMR6_WSBH_MMR6_XOR16_MMR6_XORI_MMR6_XOR_MMR6 = 238, |
| 3205 | AND64_ANDi64_DEXT64_32_DSLL64_32_ORi64_SEB64_SEH64_SLL64_32_SLL64_64_SLT64_SLTi64_SLTiu64_SLTu64_XOR64_XORi64 = 239, |
| 3206 | DADD_DADDiu_DADDu_DEXT_DEXTM_DEXTU_DINS_DINSM_DINSU_DROTR_DROTR32_DROTRV_DSBH_DSHD_DSLL_DSLL32_DSLLV_DSRA_DSRA32_DSRAV_DSRL_DSRL32_DSRLV_DSUB_DSUBu_LUi64_NOR64_OR64 = 240, |
| 3207 | DADDi_DCLO_DCLZ_LEA_ADDiu64 = 241, |
| 3208 | DALIGN_DAHI_DATI_DAUI_DCLO_R6_DCLZ_R6_DBITSWAP_DLSA_DLSA_R6_SELEQZ64_SELNEZ64 = 242, |
| 3209 | MADD_MADDU_MSUB_MSUBU = 243, |
| 3210 | PseudoMADD_MM_PseudoMADDU_MM_PseudoMSUB_MM_PseudoMSUBU_MM_PseudoMULT_MM_PseudoMULTu_MM = 244, |
| 3211 | PseudoMADD_PseudoMADDU_PseudoMSUB_PseudoMSUBU = 245, |
| 3212 | PseudoMULT_PseudoMULTu = 246, |
| 3213 | PseudoMFHI_MM_PseudoMFLO_MM = 247, |
| 3214 | RDHWR = 248, |
| 3215 | PseudoMTLOHI_MM = 249, |
| 3216 | MUH_MUHU_MULU_MUL_R6 = 250, |
| 3217 | MOD_MODU = 251, |
| 3218 | MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 252, |
| 3219 | DivRxRy16 = 253, |
| 3220 | DivuRxRy16 = 254, |
| 3221 | MULT_MM_MULTu_MM_MADD_MM_MADDU_MM_MSUB_MM_MSUBU_MM = 255, |
| 3222 | MUL_MM = 256, |
| 3223 | SDIV_MM_SDIV_MM_Pseudo = 257, |
| 3224 | UDIV_MM_UDIV_MM_Pseudo = 258, |
| 3225 | MFHI16_MM_MFLO16_MM_MOVF_I_MM_MOVT_I_MM_MFHI_MM_MFLO_MM_MTHI_MM_MTLO_MM = 259, |
| 3226 | RDHWR_MM = 260, |
| 3227 | MUHU_MMR6_MUH_MMR6_MULU_MMR6_MUL_MMR6 = 261, |
| 3228 | MODU_MMR6_MOD_MMR6_DIVU_MMR6_DIV_MMR6 = 262, |
| 3229 | RDHWR_MMR6 = 263, |
| 3230 | DMULU = 264, |
| 3231 | DMULT_DMULTu_PseudoDMULT_PseudoDMULTu = 265, |
| 3232 | DSDIV_PseudoDSDIV = 266, |
| 3233 | DUDIV_PseudoDUDIV = 267, |
| 3234 | MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64_PseudoMTLOHI64 = 268, |
| 3235 | MTHI64_MTLO64 = 269, |
| 3236 | RDHWR64 = 270, |
| 3237 | MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64_MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 271, |
| 3238 | DDIV_DMOD = 272, |
| 3239 | B_BAL_BAL_BR_BEQ_BNE_BGTZ_BGEZ_BLEZ_BLTZ_J_ERET_ERet_ERETNC_DERET = 273, |
| 3240 | BLTZAL_JR_JR_HB = 274, |
| 3241 | NAL = 275, |
| 3242 | JR_HB_MM = 276, |
| 3243 | BEQL_BNEL_BGEZL_BGTZL_BLEZL_BLTZL = 277, |
| 3244 | TAILCALL_PseudoReturn_RetRA = 278, |
| 3245 | TAILCALLREG_TAILCALLREGHB_PseudoIndirectBranch_PseudoIndirectHazardBranch = 279, |
| 3246 | BGEZAL = 280, |
| 3247 | JALR_HB_MM = 281, |
| 3248 | BGEZALL_BLTZALL = 282, |
| 3249 | BREAK_SYSCALL_TNE_TLT_TLTU_TRAP = 283, |
| 3250 | BALC_BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC_JIALC = 284, |
| 3251 | BC_BC2EQZ_BC2NEZ_BEQC_BEQZC_BGEC_BGEUC_BGEZC_BGTZC_BLEZC_BLTC_BLTUC_BLTZC_BNEC_BNEZC_BNVC_BOVC_JIC_JR_HB_R6_PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 285, |
| 3252 | SIGRIE = 286, |
| 3253 | TAILCALLR6REG_TAILCALLHBR6REG = 287, |
| 3254 | SDBBP_R6 = 288, |
| 3255 | Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_Btnez16_BtnezX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_JrRa16_JrcRa16_JrcRx16_RetRA16 = 289, |
| 3256 | Jal16_JalB16_JumpLinkReg16 = 290, |
| 3257 | Break16 = 291, |
| 3258 | SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 292, |
| 3259 | B16_MM_BAL_BR_MM_BC1F_MM_BC1T_MM_BEQZ16_MM_BEQZC_MM_BEQ_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM_BNEZC_MM_BNE_MM_B_MM_DERET_MM_ERET_MM_JR16_MM_JR_MM_J_MM_B_MM_Pseudo = 293, |
| 3260 | BGEZALS_MM_BGEZAL_MM_BLTZALS_MM_BLTZAL_MM_JALR16_MM_JALRS16_MM_JALRS_MM_JALR_MM_JALS_MM_JALX_MM_JAL_MM = 294, |
| 3261 | TAILCALLREG_MM_TAILCALL_MM_PseudoIndirectBranch_MM = 295, |
| 3262 | BREAK16_MM_BREAK_MM_SDBBP16_MM_SDBBP_MM_SYSCALL_MM_TEQI_MM_TEQ_MM_TGEIU_MM_TGEI_MM_TGEU_MM_TGE_MM_TLTIU_MM_TLTI_MM_TLTU_MM_TLT_MM_TNEI_MM_TNE_MM_TRAP_MM = 296, |
| 3263 | BC16_MMR6_BC1EQZC_MMR6_BC1NEZC_MMR6_BC2EQZC_MMR6_BC2NEZC_MMR6_BC_MMR6_BEQC_MMR6_BEQZC16_MMR6_BEQZC_MMR6_BGEC_MMR6_BGEUC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTC_MMR6_BLTUC_MMR6_BLTZC_MMR6_BNEC_MMR6_BNEZC16_MMR6_BNEZC_MMR6_BNVC_MMR6_BOVC_MMR6_DERET_MMR6_ERETNC_MMR6_JAL_MMR6_ERET_MMR6_JIC_MMR6_JRADDIUSP_JRC16_MM_JRC16_MMR6_JRCADDIUSP_MMR6_SIGRIE_MMR6_B_MMR6_Pseudo_PseudoIndirectBranch_MMR6 = 297, |
| 3264 | BALC_MMR6_BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6_JALRC16_MMR6_JALRC_HB_MMR6_JALRC_MMR6_JIALC_MMR6 = 298, |
| 3265 | TAILCALLREG_MMR6_TAILCALL_MMR6 = 299, |
| 3266 | BREAK16_MMR6_BREAK_MMR6_SDBBP_MMR6_SDBBP16_MMR6 = 300, |
| 3267 | BEQ64_BGEZ64_BGTZ64_BLEZ64_BLTZ64_BNE64_JR64 = 301, |
| 3268 | JALR64_JALR64Pseudo_JALRHB64Pseudo_JALR_HB64 = 302, |
| 3269 | JR_HB64_TAILCALLREG64_TAILCALLREGHB64 = 303, |
| 3270 | PseudoReturn64 = 304, |
| 3271 | BEQC64_BEQZC64_BGEC64_BGEUC64_BGEZC64_BGTZC64_BLEZC64_BLTC64_BLTUC64_BLTZC64_BNEC64_BNEZC64_JIC64 = 305, |
| 3272 | PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 306, |
| 3273 | JIALC64 = 307, |
| 3274 | JR_HB64_R6_TAILCALL64R6REG_TAILCALLHB64R6REG_PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 308, |
| 3275 | TLBP_TLBR_TLBWI_TLBWR = 309, |
| 3276 | MFC0 = 310, |
| 3277 | MFC0_MM = 311, |
| 3278 | MTC0_MM = 312, |
| 3279 | EVP_DVP = 313, |
| 3280 | TLBP_MM_TLBR_MM_TLBWI_MM_TLBWR_MM = 314, |
| 3281 | DI_MM_EI_MM = 315, |
| 3282 | EHB_MM_PAUSE_MM_WAIT_MM = 316, |
| 3283 | RDPGPR_MMR6_WRPGPR_MMR6 = 317, |
| 3284 | TLBINV_MMR6_TLBINVF_MMR6 = 318, |
| 3285 | MFHC0_MMR6_MFC0_MMR6_MFHC2_MMR6_MFC2_MMR6 = 319, |
| 3286 | MTHC0_MMR6_MTC0_MMR6_MTHC2_MMR6_MTC2_MMR6 = 320, |
| 3287 | EVP_MMR6_DVP_MMR6 = 321, |
| 3288 | DI_MMR6_EI_MMR6 = 322, |
| 3289 | EHB_MMR6_PAUSE_MMR6_WAIT_MMR6 = 323, |
| 3290 | DMFC0 = 324, |
| 3291 | DMTC0 = 325, |
| 3292 | DMFC2_DMTC2 = 326, |
| 3293 | CFC2_MM_CTC2_MM = 327, |
| 3294 | DMT_DVPE_EMT_EVPE_MFTR_MTTR = 328, |
| 3295 | YIELD = 329, |
| 3296 | FORK = 330, |
| 3297 | DMFGC0_DMTGC0 = 331, |
| 3298 | HYPCALL_MM_TLBGINVF_MM_TLBGINV_MM_TLBGP_MM_TLBGR_MM_TLBGWI_MM_TLBGWR_MM_MFGC0_MM_MFHGC0_MM_MTGC0_MM_MTHGC0_MM = 332, |
| 3299 | LB_LBu_LH_LHu_LW_LDC3 = 333, |
| 3300 | LL_LWC2_LWC3_LDC2 = 334, |
| 3301 | LWL_LWR = 335, |
| 3302 | SWC2_SWC3_SDC2 = 336, |
| 3303 | SWL_SWR = 337, |
| 3304 | SC = 338, |
| 3305 | SC_MMR6 = 339, |
| 3306 | CACHE = 340, |
| 3307 | LDC2_R6_LL_R6_LWC2_R6 = 341, |
| 3308 | SWC2_R6_SDC2_R6 = 342, |
| 3309 | SC_R6 = 343, |
| 3310 | CACHE_R6 = 344, |
| 3311 | GINVI_GINVT = 345, |
| 3312 | SBE_SHE_SWE_SCE = 346, |
| 3313 | PREFE = 347, |
| 3314 | LBE_MM_LBuE_MM_LHE_MM_LHuE_MM_LWE_MM_LWLE_MM_LWRE_MM_LLE_MM = 348, |
| 3315 | SBE_MM_SB_MM_SHE_MM_SWE_MM_SWLE_MM_SWRE_MM_SCE_MM = 349, |
| 3316 | PREFE_MM = 350, |
| 3317 | CACHEE_MM = 351, |
| 3318 | Restore16_RestoreX16_LbRxRyOffMemX16_LbuRxRyOffMemX16_LhRxRyOffMemX16_LhuRxRyOffMemX16_LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 352, |
| 3319 | Save16_SaveX16_SbRxRyOffMemX16_ShRxRyOffMemX16_SwRxRyOffMemX16_SwRxSpImmX16 = 353, |
| 3320 | LBU16_MM_LB_MM_LBu_MM_LHU16_MM_LH_MM_LHu_MM_LL_MM_LW16_MM_LWGP_MM_LWL_MM_LWM16_MM_LWM32_MM_LWP_MM_LWR_MM_LWSP_MM_LWU_MM_LWXS_MM_LW_MM = 354, |
| 3321 | SB16_MM_SC_MM_SH16_MM_SH_MM_SW16_MM_SWL_MM_SWM16_MM_SWM32_MM_SWM_MM_SWP_MM_SWR_MM_SWSP_MM_SW_MM = 355, |
| 3322 | PREF_MM_PREFX_MM = 356, |
| 3323 | CACHE_MM = 357, |
| 3324 | SYNC_MM_SYNCI_MM = 358, |
| 3325 | GINVI_MMR6_GINVT_MMR6 = 359, |
| 3326 | LBU_MMR6_LB_MMR6_LDC2_MMR6_LL_MMR6_LWM16_MMR6_LWC2_MMR6_LWPC_MMR6_LW_MMR6 = 360, |
| 3327 | SB16_MMR6_SB_MMR6_SDC2_MMR6_SH16_MMR6_SH_MMR6_SW16_MMR6_SWC2_MMR6_SWM16_MMR6_SWSP_MMR6_SW_MMR6 = 361, |
| 3328 | SYNC_MMR6_SYNCI_MMR6 = 362, |
| 3329 | PREF_MMR6 = 363, |
| 3330 | CACHE_MMR6 = 364, |
| 3331 | LD_LWu_LB64_LBu64_LH64_LHu64_LW64 = 365, |
| 3332 | LL64_LLD = 366, |
| 3333 | LWL64_LWR64 = 367, |
| 3334 | LDL_LDR = 368, |
| 3335 | SC64_SCD = 369, |
| 3336 | SB64_SH64_SW64_SWL64_SWR64 = 370, |
| 3337 | SDL_SDR = 371, |
| 3338 | LWUPC_LDPC = 372, |
| 3339 | CRC32B_CRC32H_CRC32W_CRC32CB_CRC32CH_CRC32CW = 373, |
| 3340 | CRC32D_CRC32CD = 374, |
| 3341 | BADDu_BBIT0_BBIT032_BBIT1_BBIT132_CINS_CINS32_CINS64_32_CINS_i32_DMFC2_OCTEON_DMTC2_OCTEON_DPOP_EXTS_EXTS32_MTM0_MTM1_MTM2_MTP0_MTP1_MTP2_POP_SEQ_SEQi_SNE_SNEi_V3MULU_VMM0_VMULU = 375, |
| 3342 | DMUL = 376, |
| 3343 | SAA_SAAD = 377, |
| 3344 | BC1F_BC1T_BC1FL_BC1TL = 378, |
| 3345 | FABS_S_FNEG_S_FNEG_D32_FNEG_D64 = 379, |
| 3346 | MADD_S_MSUB_S_NMADD_S_NMSUB_S = 380, |
| 3347 | FMUL_S = 381, |
| 3348 | ADDR_PS64_CVT_PS_PW64_CVT_PW_PS64_MULR_PS64 = 382, |
| 3349 | PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 383, |
| 3350 | MOVT_I64_MOVF_I64_MOVZ_I64_S_MOVN_I64_D64_MOVN_I64_S_MOVZ_I64_D64 = 384, |
| 3351 | SELEQZ_S_SELNEZ_S_SELEQZ_D_SELNEZ_D = 385, |
| 3352 | SEL_D_SEL_S = 386, |
| 3353 | MOVF_D32_MM_MOVF_S_MM_MOVN_I_D32_MM_MOVN_I_S_MM_MOVT_D32_MM_MOVT_S_MM_MOVZ_I_D32_MM_MOVZ_I_S_MM = 387, |
| 3354 | CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM_CEIL_W_MM_CEIL_W_S_MM_FLOOR_W_MM_FLOOR_W_S_MM_NMADD_S_MM_NMADD_D32_MM_NMSUB_S_MM_NMSUB_D32_MM_MADD_S_MM_MADD_D32_MM_ROUND_W_MM_ROUND_W_S_MM_TRUNC_W_MM_TRUNC_W_S_MM = 388, |
| 3355 | C_F_D32_MM_C_F_D64_MM_C_F_S_MM = 389, |
| 3356 | C_EQ_D32_MM_C_EQ_D64_MM_C_EQ_S_MM_C_LE_D32_MM_C_LE_D64_MM_C_LE_S_MM_C_LT_D32_MM_C_LT_D64_MM_C_LT_S_MM_C_SF_D32_MM_C_SF_D64_MM_C_SF_S_MM_C_UN_D32_MM_C_UN_D64_MM_C_UN_S_MM = 390, |
| 3357 | C_NGE_D32_MM_C_NGE_D64_MM_C_NGE_S_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGL_S_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_NGT_S_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLE_S_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_OLT_S_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_SEQ_S_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_UEQ_S_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULE_S_MM_C_ULT_D32_MM_C_ULT_D64_MM_C_ULT_S_MM = 391, |
| 3358 | C_NGLE_D32_MM_C_NGLE_D64_MM_C_NGLE_S_MM = 392, |
| 3359 | FCMP_S32_MM_FCMP_D32_MM = 393, |
| 3360 | MFC1_MM_MFHC1_D32_MM_MFHC1_D64_MM_MTC1_MM_MTC1_D64_MM_MTHC1_D32_MM_MTHC1_D64_MM = 394, |
| 3361 | FABS_D32_MM_FABS_D64_MM_FABS_S_MM_FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM_FADD_D32_MM_FADD_D64_MM_FADD_S_MM_FMOV_D32_MM_FMOV_D64_MM_FMOV_S_MM_FMUL_D32_MM_FMUL_D64_MM_FMUL_S_MM_FSUB_D32_MM_FSUB_D64_MM_FSUB_S_MM_MSUB_S_MM_MSUB_D32_MM = 395, |
| 3362 | FDIV_S_MM = 396, |
| 3363 | FDIV_D32_MM_FDIV_D64_MM = 397, |
| 3364 | FSQRT_S_MM = 398, |
| 3365 | FSQRT_D32_MM_FSQRT_D64_MM = 399, |
| 3366 | RECIP_S_MM_RSQRT_S_MM = 400, |
| 3367 | RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 401, |
| 3368 | SDC1_MM_D32_SDC1_MM_D64_SWC1_MM_SUXC1_MM_SWXC1_MM = 402, |
| 3369 | CFC1_MM_CTC1_MM = 403, |
| 3370 | LDC1_MM_D32_LDC1_MM_D64_LUXC1_MM_LWC1_MM_LWXC1_MM = 404, |
| 3371 | FNEG_S_MMR6 = 405, |
| 3372 | CMP_AF_D_MMR6_CMP_AF_S_MMR6_CMP_EQ_D_MMR6_CMP_EQ_S_MMR6_CMP_LE_D_MMR6_CMP_LE_S_MMR6_CMP_LT_D_MMR6_CMP_LT_S_MMR6_CMP_UN_D_MMR6_CMP_UN_S_MMR6 = 406, |
| 3373 | CMP_SAF_D_MMR6_CMP_SAF_S_MMR6_CMP_SEQ_D_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_D_MMR6_CMP_SLE_S_MMR6_CMP_SLT_D_MMR6_CMP_SLT_S_MMR6_CMP_SUN_D_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_D_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_D_MMR6_CMP_ULE_S_MMR6_CMP_ULT_D_MMR6_CMP_ULT_S_MMR6 = 407, |
| 3374 | CMP_SUEQ_D_MMR6_CMP_SUEQ_S_MMR6_CMP_SULE_D_MMR6_CMP_SULE_S_MMR6_CMP_SULT_D_MMR6_CMP_SULT_S_MMR6 = 408, |
| 3375 | CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 409, |
| 3376 | TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 410, |
| 3377 | ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 411, |
| 3378 | FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 412, |
| 3379 | CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 413, |
| 3380 | MFC1_MMR6_MTC1_MMR6_CLASS_S_MMR6_CLASS_D_MMR6_FADD_S_MMR6 = 414, |
| 3381 | MAX_D_MMR6_MAX_S_MMR6_MIN_D_MMR6_MIN_S_MMR6 = 415, |
| 3382 | MAXA_D_MMR6_MAXA_S_MMR6_MINA_D_MMR6_MINA_S_MMR6 = 416, |
| 3383 | SELEQZ_D_MMR6_SELEQZ_S_MMR6_SELNEZ_D_MMR6_SELNEZ_S_MMR6 = 417, |
| 3384 | SEL_D_MMR6_SEL_S_MMR6 = 418, |
| 3385 | RINT_S_MMR6_RINT_D_MMR6 = 419, |
| 3386 | MADDF_D_MMR6_MADDF_S_MMR6_MSUBF_D_MMR6_MSUBF_S_MMR6 = 420, |
| 3387 | FMOV_S_MMR6_FMUL_S_MMR6_FSUB_S_MMR6_FMOV_D_MMR6 = 421, |
| 3388 | FDIV_S_MMR6 = 422, |
| 3389 | SDC1_D64_MMR6 = 423, |
| 3390 | LDC1_D64_MMR6 = 424, |
| 3391 | DMFC1_DMTC1 = 425, |
| 3392 | SWDSP = 426, |
| 3393 | LWDSP = 427, |
| 3394 | PseudoMTLOHI_DSP = 428, |
| 3395 | EXTRV_RS_W = 429, |
| 3396 | EXTRV_R_W = 430, |
| 3397 | EXTRV_S_H = 431, |
| 3398 | EXTRV_W = 432, |
| 3399 | EXTR_RS_W = 433, |
| 3400 | EXTR_R_W = 434, |
| 3401 | EXTR_S_H = 435, |
| 3402 | EXTR_W = 436, |
| 3403 | INSV = 437, |
| 3404 | MTHLIP = 438, |
| 3405 | MTHI_DSP = 439, |
| 3406 | MTLO_DSP = 440, |
| 3407 | ABSQ_S_PH = 441, |
| 3408 | ABSQ_S_W = 442, |
| 3409 | ADDQ_PH = 443, |
| 3410 | ADDQ_S_PH = 444, |
| 3411 | ADDQ_S_W = 445, |
| 3412 | ADDSC = 446, |
| 3413 | ADDU_QB = 447, |
| 3414 | ADDU_S_QB = 448, |
| 3415 | ADDWC = 449, |
| 3416 | BITREV = 450, |
| 3417 | BPOSGE32 = 451, |
| 3418 | CMPGU_EQ_QB = 452, |
| 3419 | CMPGU_LE_QB = 453, |
| 3420 | CMPGU_LT_QB = 454, |
| 3421 | CMPU_EQ_QB = 455, |
| 3422 | CMPU_LE_QB = 456, |
| 3423 | CMPU_LT_QB = 457, |
| 3424 | CMP_EQ_PH = 458, |
| 3425 | CMP_LE_PH = 459, |
| 3426 | CMP_LT_PH = 460, |
| 3427 | DPAQ_SA_L_W = 461, |
| 3428 | DPAQ_S_W_PH = 462, |
| 3429 | DPAU_H_QBL = 463, |
| 3430 | DPAU_H_QBR = 464, |
| 3431 | DPSQ_SA_L_W = 465, |
| 3432 | DPSQ_S_W_PH = 466, |
| 3433 | DPSU_H_QBL = 467, |
| 3434 | DPSU_H_QBR = 468, |
| 3435 | EXTPDPV = 469, |
| 3436 | EXTPDP = 470, |
| 3437 | EXTPV = 471, |
| 3438 | EXTP = 472, |
| 3439 | LBUX = 473, |
| 3440 | LHX = 474, |
| 3441 | LWX = 475, |
| 3442 | MADDU_DSP = 476, |
| 3443 | MADD_DSP = 477, |
| 3444 | MAQ_SA_W_PHL = 478, |
| 3445 | MAQ_SA_W_PHR = 479, |
| 3446 | MAQ_S_W_PHL = 480, |
| 3447 | MAQ_S_W_PHR = 481, |
| 3448 | MFHI_DSP = 482, |
| 3449 | MFLO_DSP = 483, |
| 3450 | MODSUB = 484, |
| 3451 | MSUBU_DSP = 485, |
| 3452 | MSUB_DSP = 486, |
| 3453 | MULEQ_S_W_PHL = 487, |
| 3454 | MULEQ_S_W_PHR = 488, |
| 3455 | MULEU_S_PH_QBL = 489, |
| 3456 | MULEU_S_PH_QBR = 490, |
| 3457 | MULQ_RS_PH = 491, |
| 3458 | MULSAQ_S_W_PH = 492, |
| 3459 | MULTU_DSP = 493, |
| 3460 | MULT_DSP = 494, |
| 3461 | PACKRL_PH = 495, |
| 3462 | PICK_PH = 496, |
| 3463 | PICK_QB = 497, |
| 3464 | PRECEQU_PH_QBLA = 498, |
| 3465 | PRECEQU_PH_QBL = 499, |
| 3466 | PRECEQU_PH_QBRA = 500, |
| 3467 | PRECEQU_PH_QBR = 501, |
| 3468 | PRECEQ_W_PHL = 502, |
| 3469 | PRECEQ_W_PHR = 503, |
| 3470 | PRECEU_PH_QBLA = 504, |
| 3471 | PRECEU_PH_QBL = 505, |
| 3472 | PRECEU_PH_QBRA = 506, |
| 3473 | PRECEU_PH_QBR = 507, |
| 3474 | PRECRQU_S_QB_PH = 508, |
| 3475 | PRECRQ_PH_W = 509, |
| 3476 | PRECRQ_QB_PH = 510, |
| 3477 | PRECRQ_RS_PH_W = 511, |
| 3478 | RADDU_W_QB = 512, |
| 3479 | RDDSP = 513, |
| 3480 | REPLV_PH = 514, |
| 3481 | REPLV_QB = 515, |
| 3482 | REPL_PH = 516, |
| 3483 | REPL_QB = 517, |
| 3484 | SHILOV = 518, |
| 3485 | SHILO = 519, |
| 3486 | SHLLV_PH = 520, |
| 3487 | SHLLV_QB = 521, |
| 3488 | SHLLV_S_PH = 522, |
| 3489 | SHLLV_S_W = 523, |
| 3490 | SHLL_PH = 524, |
| 3491 | SHLL_QB = 525, |
| 3492 | SHLL_S_PH = 526, |
| 3493 | SHLL_S_W = 527, |
| 3494 | SHRAV_PH = 528, |
| 3495 | SHRAV_R_PH = 529, |
| 3496 | SHRAV_R_W = 530, |
| 3497 | SHRA_PH = 531, |
| 3498 | SHRA_R_PH = 532, |
| 3499 | SHRA_R_W = 533, |
| 3500 | SHRLV_QB = 534, |
| 3501 | SHRL_QB = 535, |
| 3502 | SUBQ_PH = 536, |
| 3503 | SUBQ_S_PH = 537, |
| 3504 | SUBQ_S_W = 538, |
| 3505 | SUBU_QB = 539, |
| 3506 | SUBU_S_QB = 540, |
| 3507 | WRDSP = 541, |
| 3508 | PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 542, |
| 3509 | PseudoPICK_PH_PseudoPICK_QB = 543, |
| 3510 | ABSQ_S_QB = 544, |
| 3511 | ADDQH_PH = 545, |
| 3512 | ADDQH_R_PH = 546, |
| 3513 | ADDQH_R_W = 547, |
| 3514 | ADDQH_W = 548, |
| 3515 | ADDUH_QB = 549, |
| 3516 | ADDUH_R_QB = 550, |
| 3517 | ADDU_PH = 551, |
| 3518 | ADDU_S_PH = 552, |
| 3519 | APPEND = 553, |
| 3520 | BALIGN = 554, |
| 3521 | CMPGDU_EQ_QB = 555, |
| 3522 | CMPGDU_LE_QB = 556, |
| 3523 | CMPGDU_LT_QB = 557, |
| 3524 | DPA_W_PH = 558, |
| 3525 | DPAQX_SA_W_PH = 559, |
| 3526 | DPAQX_S_W_PH = 560, |
| 3527 | DPAX_W_PH = 561, |
| 3528 | DPS_W_PH = 562, |
| 3529 | DPSQX_S_W_PH = 563, |
| 3530 | DPSQX_SA_W_PH = 564, |
| 3531 | DPSX_W_PH = 565, |
| 3532 | MUL_PH = 566, |
| 3533 | MUL_S_PH = 567, |
| 3534 | MULQ_RS_W = 568, |
| 3535 | MULQ_S_PH = 569, |
| 3536 | MULQ_S_W = 570, |
| 3537 | MULSA_W_PH = 571, |
| 3538 | PRECR_QB_PH = 572, |
| 3539 | PRECR_SRA_PH_W = 573, |
| 3540 | PRECR_SRA_R_PH_W = 574, |
| 3541 | PREPEND = 575, |
| 3542 | SHRA_QB = 576, |
| 3543 | SHRA_R_QB = 577, |
| 3544 | SHRAV_QB = 578, |
| 3545 | SHRAV_R_QB = 579, |
| 3546 | SHRL_PH = 580, |
| 3547 | SHRLV_PH = 581, |
| 3548 | SUBQH_PH = 582, |
| 3549 | SUBQH_R_PH = 583, |
| 3550 | SUBQH_W = 584, |
| 3551 | SUBQH_R_W = 585, |
| 3552 | SUBU_PH = 586, |
| 3553 | SUBU_S_PH = 587, |
| 3554 | SUBUH_QB = 588, |
| 3555 | SUBUH_R_QB = 589, |
| 3556 | LWDSP_MM = 590, |
| 3557 | SWDSP_MM = 591, |
| 3558 | ABSQ_S_PH_MM = 592, |
| 3559 | ABSQ_S_W_MM = 593, |
| 3560 | ADDQ_PH_MM = 594, |
| 3561 | ADDQ_S_PH_MM = 595, |
| 3562 | ADDQ_S_W_MM = 596, |
| 3563 | ADDSC_MM = 597, |
| 3564 | ADDU_QB_MM = 598, |
| 3565 | ADDU_S_QB_MM = 599, |
| 3566 | ADDWC_MM = 600, |
| 3567 | BITREV_MM = 601, |
| 3568 | BPOSGE32_MM = 602, |
| 3569 | CMPGU_EQ_QB_MM = 603, |
| 3570 | CMPGU_LE_QB_MM = 604, |
| 3571 | CMPGU_LT_QB_MM = 605, |
| 3572 | CMPU_EQ_QB_MM = 606, |
| 3573 | CMPU_LE_QB_MM = 607, |
| 3574 | CMPU_LT_QB_MM = 608, |
| 3575 | CMP_EQ_PH_MM = 609, |
| 3576 | CMP_LE_PH_MM = 610, |
| 3577 | CMP_LT_PH_MM = 611, |
| 3578 | DPAQ_SA_L_W_MM = 612, |
| 3579 | DPAQ_S_W_PH_MM = 613, |
| 3580 | DPAU_H_QBL_MM = 614, |
| 3581 | DPAU_H_QBR_MM = 615, |
| 3582 | DPSQ_SA_L_W_MM = 616, |
| 3583 | DPSQ_S_W_PH_MM = 617, |
| 3584 | DPSU_H_QBL_MM = 618, |
| 3585 | DPSU_H_QBR_MM = 619, |
| 3586 | EXTPDPV_MM = 620, |
| 3587 | EXTPDP_MM = 621, |
| 3588 | EXTPV_MM = 622, |
| 3589 | EXTP_MM = 623, |
| 3590 | EXTRV_RS_W_MM = 624, |
| 3591 | EXTRV_R_W_MM = 625, |
| 3592 | EXTRV_S_H_MM = 626, |
| 3593 | EXTRV_W_MM = 627, |
| 3594 | EXTR_RS_W_MM = 628, |
| 3595 | EXTR_R_W_MM = 629, |
| 3596 | EXTR_S_H_MM = 630, |
| 3597 | EXTR_W_MM = 631, |
| 3598 | INSV_MM = 632, |
| 3599 | LBUX_MM = 633, |
| 3600 | LHX_MM = 634, |
| 3601 | LWX_MM = 635, |
| 3602 | MADDU_DSP_MM = 636, |
| 3603 | MADD_DSP_MM = 637, |
| 3604 | MAQ_SA_W_PHL_MM = 638, |
| 3605 | MAQ_SA_W_PHR_MM = 639, |
| 3606 | MAQ_S_W_PHL_MM = 640, |
| 3607 | MAQ_S_W_PHR_MM = 641, |
| 3608 | MFHI_DSP_MM = 642, |
| 3609 | MFLO_DSP_MM = 643, |
| 3610 | MODSUB_MM = 644, |
| 3611 | MOVEP_MMR6 = 645, |
| 3612 | MOVN_I_MM = 646, |
| 3613 | MOVZ_I_MM = 647, |
| 3614 | MSUBU_DSP_MM = 648, |
| 3615 | MSUB_DSP_MM = 649, |
| 3616 | MTHI_DSP_MM = 650, |
| 3617 | MTHLIP_MM = 651, |
| 3618 | MTLO_DSP_MM = 652, |
| 3619 | MULEQ_S_W_PHL_MM = 653, |
| 3620 | MULEQ_S_W_PHR_MM = 654, |
| 3621 | MULEU_S_PH_QBL_MM = 655, |
| 3622 | MULEU_S_PH_QBR_MM = 656, |
| 3623 | MULQ_RS_PH_MM = 657, |
| 3624 | MULSAQ_S_W_PH_MM = 658, |
| 3625 | MULTU_DSP_MM = 659, |
| 3626 | MULT_DSP_MM = 660, |
| 3627 | PACKRL_PH_MM = 661, |
| 3628 | PICK_PH_MM = 662, |
| 3629 | PICK_QB_MM = 663, |
| 3630 | PRECEQU_PH_QBLA_MM = 664, |
| 3631 | PRECEQU_PH_QBL_MM = 665, |
| 3632 | PRECEQU_PH_QBRA_MM = 666, |
| 3633 | PRECEQU_PH_QBR_MM = 667, |
| 3634 | PRECEQ_W_PHL_MM = 668, |
| 3635 | PRECEQ_W_PHR_MM = 669, |
| 3636 | PRECEU_PH_QBLA_MM = 670, |
| 3637 | PRECEU_PH_QBL_MM = 671, |
| 3638 | PRECEU_PH_QBRA_MM = 672, |
| 3639 | PRECEU_PH_QBR_MM = 673, |
| 3640 | PRECRQU_S_QB_PH_MM = 674, |
| 3641 | PRECRQ_PH_W_MM = 675, |
| 3642 | PRECRQ_QB_PH_MM = 676, |
| 3643 | PRECRQ_RS_PH_W_MM = 677, |
| 3644 | RADDU_W_QB_MM = 678, |
| 3645 | RDDSP_MM = 679, |
| 3646 | REPLV_PH_MM = 680, |
| 3647 | REPLV_QB_MM = 681, |
| 3648 | REPL_PH_MM = 682, |
| 3649 | REPL_QB_MM = 683, |
| 3650 | SHILOV_MM = 684, |
| 3651 | SHILO_MM = 685, |
| 3652 | SHLLV_PH_MM = 686, |
| 3653 | SHLLV_QB_MM = 687, |
| 3654 | SHLLV_S_PH_MM = 688, |
| 3655 | SHLLV_S_W_MM = 689, |
| 3656 | SHLL_PH_MM = 690, |
| 3657 | SHLL_QB_MM = 691, |
| 3658 | SHLL_S_PH_MM = 692, |
| 3659 | SHLL_S_W_MM = 693, |
| 3660 | SHRAV_PH_MM = 694, |
| 3661 | SHRAV_R_PH_MM = 695, |
| 3662 | SHRAV_R_W_MM = 696, |
| 3663 | SHRA_PH_MM = 697, |
| 3664 | SHRA_R_PH_MM = 698, |
| 3665 | SHRA_R_W_MM = 699, |
| 3666 | SHRLV_QB_MM = 700, |
| 3667 | SHRL_QB_MM = 701, |
| 3668 | SUBQ_PH_MM = 702, |
| 3669 | SUBQ_S_PH_MM = 703, |
| 3670 | SUBQ_S_W_MM = 704, |
| 3671 | SUBU_QB_MM = 705, |
| 3672 | SUBU_S_QB_MM = 706, |
| 3673 | WRDSP_MM = 707, |
| 3674 | ABSQ_S_QB_MMR2 = 708, |
| 3675 | ADDQH_PH_MMR2 = 709, |
| 3676 | ADDQH_R_PH_MMR2 = 710, |
| 3677 | ADDQH_R_W_MMR2 = 711, |
| 3678 | ADDQH_W_MMR2 = 712, |
| 3679 | ADDUH_QB_MMR2 = 713, |
| 3680 | ADDUH_R_QB_MMR2 = 714, |
| 3681 | ADDU_PH_MMR2 = 715, |
| 3682 | ADDU_S_PH_MMR2 = 716, |
| 3683 | APPEND_MMR2 = 717, |
| 3684 | BALIGN_MMR2 = 718, |
| 3685 | CMPGDU_EQ_QB_MMR2 = 719, |
| 3686 | CMPGDU_LE_QB_MMR2 = 720, |
| 3687 | CMPGDU_LT_QB_MMR2 = 721, |
| 3688 | DPA_W_PH_MMR2 = 722, |
| 3689 | DPAQX_SA_W_PH_MMR2 = 723, |
| 3690 | DPAQX_S_W_PH_MMR2 = 724, |
| 3691 | DPAX_W_PH_MMR2 = 725, |
| 3692 | DPS_W_PH_MMR2 = 726, |
| 3693 | DPSQX_S_W_PH_MMR2 = 727, |
| 3694 | DPSQX_SA_W_PH_MMR2 = 728, |
| 3695 | DPSX_W_PH_MMR2 = 729, |
| 3696 | MUL_PH_MMR2 = 730, |
| 3697 | MUL_S_PH_MMR2 = 731, |
| 3698 | MULQ_RS_W_MMR2 = 732, |
| 3699 | MULQ_S_PH_MMR2 = 733, |
| 3700 | MULQ_S_W_MMR2 = 734, |
| 3701 | MULSA_W_PH_MMR2 = 735, |
| 3702 | PRECR_QB_PH_MMR2 = 736, |
| 3703 | PRECR_SRA_PH_W_MMR2 = 737, |
| 3704 | PRECR_SRA_R_PH_W_MMR2 = 738, |
| 3705 | PREPEND_MMR2 = 739, |
| 3706 | SHRA_QB_MMR2 = 740, |
| 3707 | SHRA_R_QB_MMR2 = 741, |
| 3708 | SHRAV_QB_MMR2 = 742, |
| 3709 | SHRAV_R_QB_MMR2 = 743, |
| 3710 | SHRL_PH_MMR2 = 744, |
| 3711 | SHRLV_PH_MMR2 = 745, |
| 3712 | SUBQH_PH_MMR2 = 746, |
| 3713 | SUBQH_R_PH_MMR2 = 747, |
| 3714 | SUBQH_W_MMR2 = 748, |
| 3715 | SUBQH_R_W_MMR2 = 749, |
| 3716 | SUBU_PH_MMR2 = 750, |
| 3717 | SUBU_S_PH_MMR2 = 751, |
| 3718 | SUBUH_QB_MMR2 = 752, |
| 3719 | SUBUH_R_QB_MMR2 = 753, |
| 3720 | BPOSGE32C_MMR3 = 754, |
| 3721 | SCHED_LIST_END = 755 |
| 3722 | }; |
| 3723 | |
| 3724 | } // namespace llvm::Mips::Sched |
| 3725 | |
| 3726 | #endif // GET_INSTRINFO_SCHED_ENUM |
| 3727 | |
| 3728 | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 3729 | |
| 3730 | namespace llvm { |
| 3731 | |
| 3732 | struct MipsInstrTable { |
| 3733 | MCInstrDesc Insts[2932]; |
| 3734 | static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps"); |
| 3735 | MCPhysReg ImplicitOps[68]; |
| 3736 | char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)]; |
| 3737 | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
| 3738 | MCOperandInfo OperandInfo[1138]; |
| 3739 | }; |
| 3740 | } // namespace llvm |
| 3741 | |
| 3742 | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 3743 | |
| 3744 | #ifdef GET_INSTRINFO_MC_DESC |
| 3745 | #undef GET_INSTRINFO_MC_DESC |
| 3746 | |
| 3747 | namespace llvm { |
| 3748 | |
| 3749 | static_assert((sizeof MipsInstrTable::ImplicitOps + sizeof MipsInstrTable::Padding) % sizeof(MCOperandInfo) == 0); |
| 3750 | static constexpr unsigned MipsOpInfoBase = (sizeof MipsInstrTable::ImplicitOps + sizeof MipsInstrTable::Padding) / sizeof(MCOperandInfo); |
| 3751 | |
| 3752 | extern const MipsInstrTable MipsDescs = { |
| 3753 | { |
| 3754 | { 2931, 2, 1, 4, 329, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // YIELD |
| 3755 | { 2930, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 579, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // XorRxRxRy16 |
| 3756 | { 2929, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // XORi_MM |
| 3757 | { 2928, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // XORi64 |
| 3758 | { 2927, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // XORi |
| 3759 | { 2926, 3, 1, 4, 134, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // XOR_V |
| 3760 | { 2925, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // XOR_MMR6 |
| 3761 | { 2924, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // XOR_MM |
| 3762 | { 2923, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // XORI_MMR6 |
| 3763 | { 2922, 3, 1, 4, 25, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // XORI_B |
| 3764 | { 2921, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // XOR64 |
| 3765 | { 2920, 3, 1, 2, 238, 0, 0, MipsOpInfoBase + 564, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XOR16_MMR6 |
| 3766 | { 2919, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 564, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // XOR16_MM |
| 3767 | { 2918, 3, 1, 4, 79, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // XOR |
| 3768 | { 2917, 2, 1, 4, 238, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x6ULL }, // WSBH_MMR6 |
| 3769 | { 2916, 2, 1, 4, 237, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // WSBH_MM |
| 3770 | { 2915, 2, 1, 4, 232, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // WSBH |
| 3771 | { 2914, 2, 1, 4, 317, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x6ULL }, // WRPGPR_MMR6 |
| 3772 | { 2913, 2, 0, 4, 707, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // WRDSP_MM |
| 3773 | { 2912, 2, 0, 4, 541, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // WRDSP |
| 3774 | { 2911, 1, 0, 4, 323, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // WAIT_MMR6 |
| 3775 | { 2910, 1, 0, 4, 316, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // WAIT_MM |
| 3776 | { 2909, 0, 0, 4, 81, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // WAIT |
| 3777 | { 2908, 4, 1, 4, 113, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // VSHF_W |
| 3778 | { 2907, 4, 1, 4, 113, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // VSHF_H |
| 3779 | { 2906, 4, 1, 4, 113, 0, 0, MipsOpInfoBase + 197, 0, 0, 0x6ULL }, // VSHF_D |
| 3780 | { 2905, 4, 1, 4, 113, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // VSHF_B |
| 3781 | { 2904, 3, 1, 4, 375, 0, 5, MipsOpInfoBase + 237, 63, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // VMULU |
| 3782 | { 2903, 3, 1, 4, 375, 0, 4, MipsOpInfoBase + 237, 43, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // VMM0 |
| 3783 | { 2902, 3, 1, 4, 375, 0, 3, MipsOpInfoBase + 237, 60, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // V3MULU |
| 3784 | { 2901, 2, 0, 4, 258, 0, 2, MipsOpInfoBase + 151, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // UDIV_MM |
| 3785 | { 2900, 2, 0, 4, 106, 0, 2, MipsOpInfoBase + 151, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // UDIV |
| 3786 | { 2899, 2, 0, 4, 82, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TTLTIU |
| 3787 | { 2898, 2, 1, 4, 410, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_S_MMR6 |
| 3788 | { 2897, 2, 1, 4, 388, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_S_MM |
| 3789 | { 2896, 2, 1, 4, 184, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_S |
| 3790 | { 2895, 2, 1, 4, 388, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_MM |
| 3791 | { 2894, 2, 1, 4, 410, 0, 0, MipsOpInfoBase + 632, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_D_MMR6 |
| 3792 | { 2893, 2, 1, 4, 184, 0, 0, MipsOpInfoBase + 632, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_D64 |
| 3793 | { 2892, 2, 1, 4, 184, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_D32 |
| 3794 | { 2891, 2, 1, 4, 410, 0, 0, MipsOpInfoBase + 628, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_L_S_MMR6 |
| 3795 | { 2890, 2, 1, 4, 184, 0, 0, MipsOpInfoBase + 628, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_L_S |
| 3796 | { 2889, 2, 1, 4, 410, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_L_D_MMR6 |
| 3797 | { 2888, 2, 1, 4, 184, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_L_D64 |
| 3798 | { 2887, 3, 0, 4, 296, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TNE_MM |
| 3799 | { 2886, 2, 0, 4, 296, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TNEI_MM |
| 3800 | { 2885, 2, 0, 4, 82, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TNEI |
| 3801 | { 2884, 3, 0, 4, 283, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TNE |
| 3802 | { 2883, 3, 0, 4, 296, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TLT_MM |
| 3803 | { 2882, 3, 0, 4, 296, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TLTU_MM |
| 3804 | { 2881, 3, 0, 4, 283, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TLTU |
| 3805 | { 2880, 2, 0, 4, 296, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TLTI_MM |
| 3806 | { 2879, 2, 0, 4, 296, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TLTIU_MM |
| 3807 | { 2878, 2, 0, 4, 82, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TLTI |
| 3808 | { 2877, 3, 0, 4, 283, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TLT |
| 3809 | { 2876, 0, 0, 4, 314, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBWR_MM |
| 3810 | { 2875, 0, 0, 4, 309, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBWR |
| 3811 | { 2874, 0, 0, 4, 314, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBWI_MM |
| 3812 | { 2873, 0, 0, 4, 309, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBWI |
| 3813 | { 2872, 0, 0, 4, 314, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBR_MM |
| 3814 | { 2871, 0, 0, 4, 309, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBR |
| 3815 | { 2870, 0, 0, 4, 314, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBP_MM |
| 3816 | { 2869, 0, 0, 4, 309, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBP |
| 3817 | { 2868, 0, 0, 4, 318, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBINV_MMR6 |
| 3818 | { 2867, 0, 0, 4, 318, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBINVF_MMR6 |
| 3819 | { 2866, 0, 0, 4, 87, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBINVF |
| 3820 | { 2865, 0, 0, 4, 87, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBINV |
| 3821 | { 2864, 0, 0, 4, 332, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGWR_MM |
| 3822 | { 2863, 0, 0, 4, 90, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGWR |
| 3823 | { 2862, 0, 0, 4, 332, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGWI_MM |
| 3824 | { 2861, 0, 0, 4, 90, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGWI |
| 3825 | { 2860, 0, 0, 4, 332, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGR_MM |
| 3826 | { 2859, 0, 0, 4, 90, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGR |
| 3827 | { 2858, 0, 0, 4, 332, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGP_MM |
| 3828 | { 2857, 0, 0, 4, 90, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGP |
| 3829 | { 2856, 0, 0, 4, 332, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGINV_MM |
| 3830 | { 2855, 0, 0, 4, 332, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGINVF_MM |
| 3831 | { 2854, 0, 0, 4, 90, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGINVF |
| 3832 | { 2853, 0, 0, 4, 90, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGINV |
| 3833 | { 2852, 3, 0, 4, 296, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TGE_MM |
| 3834 | { 2851, 3, 0, 4, 296, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TGEU_MM |
| 3835 | { 2850, 3, 0, 4, 83, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TGEU |
| 3836 | { 2849, 2, 0, 4, 296, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TGEI_MM |
| 3837 | { 2848, 2, 0, 4, 296, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TGEIU_MM |
| 3838 | { 2847, 2, 0, 4, 82, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TGEIU |
| 3839 | { 2846, 2, 0, 4, 82, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TGEI |
| 3840 | { 2845, 3, 0, 4, 83, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TGE |
| 3841 | { 2844, 3, 0, 4, 296, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TEQ_MM |
| 3842 | { 2843, 2, 0, 4, 296, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TEQI_MM |
| 3843 | { 2842, 2, 0, 4, 82, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TEQI |
| 3844 | { 2841, 3, 0, 4, 83, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TEQ |
| 3845 | { 2840, 3, 0, 4, 353, 0, 0, MipsOpInfoBase + 576, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // SwRxSpImmX16 |
| 3846 | { 2839, 3, 0, 4, 353, 0, 0, MipsOpInfoBase + 917, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SwRxRyOffMemX16 |
| 3847 | { 2838, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 399, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // SubuRxRyRz16 |
| 3848 | { 2837, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x0ULL }, // SrlvRxRy16 |
| 3849 | { 2836, 3, 1, 4, 235, 0, 0, MipsOpInfoBase + 523, 0, 0, 0x0ULL }, // SrlX16 |
| 3850 | { 2835, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x0ULL }, // SravRxRy16 |
| 3851 | { 2834, 3, 1, 4, 235, 0, 0, MipsOpInfoBase + 523, 0, 0, 0x0ULL }, // SraX16 |
| 3852 | { 2833, 2, 0, 2, 235, 0, 1, MipsOpInfoBase + 397, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltuRxRy16 |
| 3853 | { 2832, 2, 0, 4, 235, 0, 1, MipsOpInfoBase + 571, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltiuRxImmX16 |
| 3854 | { 2831, 2, 0, 2, 235, 0, 1, MipsOpInfoBase + 571, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltiuRxImm16 |
| 3855 | { 2830, 2, 0, 4, 235, 0, 1, MipsOpInfoBase + 571, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltiRxImmX16 |
| 3856 | { 2829, 2, 0, 2, 235, 0, 1, MipsOpInfoBase + 571, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltiRxImm16 |
| 3857 | { 2828, 2, 0, 2, 235, 0, 1, MipsOpInfoBase + 397, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltRxRy16 |
| 3858 | { 2827, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x0ULL }, // SllvRxRy16 |
| 3859 | { 2826, 3, 1, 4, 235, 0, 0, MipsOpInfoBase + 523, 0, 0, 0x0ULL }, // SllX16 |
| 3860 | { 2825, 3, 0, 4, 353, 0, 0, MipsOpInfoBase + 917, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // ShRxRyOffMemX16 |
| 3861 | { 2824, 2, 1, 2, 235, 0, 0, MipsOpInfoBase + 1136, 0, 0, 0x0ULL }, // SehRx16 |
| 3862 | { 2823, 2, 1, 2, 235, 0, 0, MipsOpInfoBase + 1136, 0, 0, 0x0ULL }, // SebRx16 |
| 3863 | { 2822, 3, 0, 4, 353, 0, 0, MipsOpInfoBase + 917, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // SbRxRyOffMemX16 |
| 3864 | { 2821, 0, 0, 2, 353, 1, 1, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SaveX16 |
| 3865 | { 2820, 0, 0, 2, 353, 1, 1, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Save16 |
| 3866 | { 2819, 1, 0, 4, 296, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // SYSCALL_MM |
| 3867 | { 2818, 1, 0, 4, 283, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // SYSCALL |
| 3868 | { 2817, 1, 0, 4, 362, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNC_MMR6 |
| 3869 | { 2816, 1, 0, 4, 358, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNC_MM |
| 3870 | { 2815, 2, 0, 4, 362, 0, 0, MipsOpInfoBase + 1134, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNCI_MMR6 |
| 3871 | { 2814, 2, 0, 4, 358, 0, 0, MipsOpInfoBase + 1134, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNCI_MM |
| 3872 | { 2813, 2, 0, 4, 98, 0, 0, MipsOpInfoBase + 1134, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNCI |
| 3873 | { 2812, 1, 0, 4, 5, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNC |
| 3874 | { 2811, 3, 0, 4, 361, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SW_MMR6 |
| 3875 | { 2810, 3, 0, 4, 355, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SW_MM |
| 3876 | { 2809, 3, 0, 4, 402, 0, 0, MipsOpInfoBase + 914, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWXC1_MM |
| 3877 | { 2808, 3, 0, 4, 220, 0, 0, MipsOpInfoBase + 914, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWXC1 |
| 3878 | { 2807, 3, 0, 2, 361, 0, 0, MipsOpInfoBase + 911, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWSP_MMR6 |
| 3879 | { 2806, 3, 0, 2, 355, 0, 0, MipsOpInfoBase + 911, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWSP_MM |
| 3880 | { 2805, 3, 0, 4, 355, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWR_MM |
| 3881 | { 2804, 3, 0, 4, 349, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWRE_MM |
| 3882 | { 2803, 3, 0, 4, 95, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SWRE |
| 3883 | { 2802, 3, 0, 4, 370, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWR64 |
| 3884 | { 2801, 3, 0, 4, 337, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWR |
| 3885 | { 2800, 4, 0, 4, 355, 0, 0, MipsOpInfoBase + 907, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWP_MM |
| 3886 | { 2799, 3, 0, 4, 355, 0, 0, MipsOpInfoBase + 360, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWM32_MM |
| 3887 | { 2798, 3, 0, 2, 361, 0, 0, MipsOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWM16_MMR6 |
| 3888 | { 2797, 3, 0, 2, 355, 0, 0, MipsOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWM16_MM |
| 3889 | { 2796, 3, 0, 4, 355, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWL_MM |
| 3890 | { 2795, 3, 0, 4, 349, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWLE_MM |
| 3891 | { 2794, 3, 0, 4, 95, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SWLE |
| 3892 | { 2793, 3, 0, 4, 370, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWL64 |
| 3893 | { 2792, 3, 0, 4, 337, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWL |
| 3894 | { 2791, 3, 0, 4, 349, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWE_MM |
| 3895 | { 2790, 3, 0, 4, 346, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SWE |
| 3896 | { 2789, 3, 0, 4, 591, 0, 0, MipsOpInfoBase + 894, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWDSP_MM |
| 3897 | { 2788, 3, 0, 4, 426, 0, 0, MipsOpInfoBase + 894, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWDSP |
| 3898 | { 2787, 3, 0, 4, 336, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWC3 |
| 3899 | { 2786, 3, 0, 4, 342, 0, 0, MipsOpInfoBase + 846, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SWC2_R6 |
| 3900 | { 2785, 3, 0, 4, 361, 0, 0, MipsOpInfoBase + 849, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // SWC2_MMR6 |
| 3901 | { 2784, 3, 0, 4, 336, 0, 0, MipsOpInfoBase + 846, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWC2 |
| 3902 | { 2783, 3, 0, 4, 402, 0, 0, MipsOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWC1_MM |
| 3903 | { 2782, 3, 0, 4, 219, 0, 0, MipsOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWC1 |
| 3904 | { 2781, 3, 0, 4, 370, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SW64 |
| 3905 | { 2780, 3, 0, 2, 361, 0, 0, MipsOpInfoBase + 1064, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // SW16_MMR6 |
| 3906 | { 2779, 3, 0, 2, 355, 0, 0, MipsOpInfoBase + 1064, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // SW16_MM |
| 3907 | { 2778, 3, 0, 4, 94, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SW |
| 3908 | { 2777, 3, 0, 4, 402, 0, 0, MipsOpInfoBase + 870, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // SUXC1_MM |
| 3909 | { 2776, 3, 0, 4, 220, 0, 0, MipsOpInfoBase + 870, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // SUXC164 |
| 3910 | { 2775, 3, 0, 4, 220, 0, 0, MipsOpInfoBase + 867, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // SUXC1 |
| 3911 | { 2774, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // SUBu_MM |
| 3912 | { 2773, 3, 1, 4, 79, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // SUBu |
| 3913 | { 2772, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SUB_MMR6 |
| 3914 | { 2771, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SUB_MM |
| 3915 | { 2770, 3, 1, 4, 17, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SUBV_W |
| 3916 | { 2769, 3, 1, 4, 17, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SUBV_H |
| 3917 | { 2768, 3, 1, 4, 17, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SUBV_D |
| 3918 | { 2767, 3, 1, 4, 17, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SUBV_B |
| 3919 | { 2766, 3, 1, 4, 171, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SUBVI_W |
| 3920 | { 2765, 3, 1, 4, 171, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SUBVI_H |
| 3921 | { 2764, 3, 1, 4, 171, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SUBVI_D |
| 3922 | { 2763, 3, 1, 4, 171, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBVI_B |
| 3923 | { 2762, 3, 1, 4, 706, 0, 1, MipsOpInfoBase + 536, 10, 0, 0x6ULL }, // SUBU_S_QB_MM |
| 3924 | { 2761, 3, 1, 4, 540, 0, 1, MipsOpInfoBase + 536, 10, 0, 0x6ULL }, // SUBU_S_QB |
| 3925 | { 2760, 3, 1, 4, 751, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_S_PH_MMR2 |
| 3926 | { 2759, 3, 1, 4, 587, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_S_PH |
| 3927 | { 2758, 3, 1, 4, 705, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_QB_MM |
| 3928 | { 2757, 3, 1, 4, 539, 0, 1, MipsOpInfoBase + 536, 10, 0, 0x6ULL }, // SUBU_QB |
| 3929 | { 2756, 3, 1, 4, 750, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_PH_MMR2 |
| 3930 | { 2755, 3, 1, 4, 586, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_PH |
| 3931 | { 2754, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // SUBU_MMR6 |
| 3932 | { 2753, 3, 1, 4, 753, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // SUBUH_R_QB_MMR2 |
| 3933 | { 2752, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // SUBUH_R_QB |
| 3934 | { 2751, 3, 1, 4, 752, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // SUBUH_QB_MMR2 |
| 3935 | { 2750, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // SUBUH_QB |
| 3936 | { 2749, 3, 1, 2, 238, 0, 0, MipsOpInfoBase + 545, 0, 0, 0x0ULL }, // SUBU16_MMR6 |
| 3937 | { 2748, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 545, 0, 0, 0x0ULL }, // SUBU16_MM |
| 3938 | { 2747, 3, 1, 4, 169, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SUBS_U_W |
| 3939 | { 2746, 3, 1, 4, 169, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SUBS_U_H |
| 3940 | { 2745, 3, 1, 4, 169, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SUBS_U_D |
| 3941 | { 2744, 3, 1, 4, 169, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SUBS_U_B |
| 3942 | { 2743, 3, 1, 4, 169, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SUBS_S_W |
| 3943 | { 2742, 3, 1, 4, 169, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SUBS_S_H |
| 3944 | { 2741, 3, 1, 4, 169, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SUBS_S_D |
| 3945 | { 2740, 3, 1, 4, 169, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SUBS_S_B |
| 3946 | { 2739, 3, 1, 4, 170, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SUBSUU_S_W |
| 3947 | { 2738, 3, 1, 4, 170, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SUBSUU_S_H |
| 3948 | { 2737, 3, 1, 4, 170, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SUBSUU_S_D |
| 3949 | { 2736, 3, 1, 4, 170, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SUBSUU_S_B |
| 3950 | { 2735, 3, 1, 4, 20, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SUBSUS_U_W |
| 3951 | { 2734, 3, 1, 4, 20, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SUBSUS_U_H |
| 3952 | { 2733, 3, 1, 4, 20, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SUBSUS_U_D |
| 3953 | { 2732, 3, 1, 4, 20, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SUBSUS_U_B |
| 3954 | { 2731, 3, 1, 4, 704, 0, 1, MipsOpInfoBase + 240, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBQ_S_W_MM |
| 3955 | { 2730, 3, 1, 4, 538, 0, 1, MipsOpInfoBase + 240, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBQ_S_W |
| 3956 | { 2729, 3, 1, 4, 703, 0, 1, MipsOpInfoBase + 536, 10, 0, 0x6ULL }, // SUBQ_S_PH_MM |
| 3957 | { 2728, 3, 1, 4, 537, 0, 1, MipsOpInfoBase + 536, 10, 0, 0x6ULL }, // SUBQ_S_PH |
| 3958 | { 2727, 3, 1, 4, 702, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBQ_PH_MM |
| 3959 | { 2726, 3, 1, 4, 536, 0, 1, MipsOpInfoBase + 536, 10, 0, 0x6ULL }, // SUBQ_PH |
| 3960 | { 2725, 3, 1, 4, 748, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SUBQH_W_MMR2 |
| 3961 | { 2724, 3, 1, 4, 584, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SUBQH_W |
| 3962 | { 2723, 3, 1, 4, 749, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SUBQH_R_W_MMR2 |
| 3963 | { 2722, 3, 1, 4, 585, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SUBQH_R_W |
| 3964 | { 2721, 3, 1, 4, 747, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // SUBQH_R_PH_MMR2 |
| 3965 | { 2720, 3, 1, 4, 583, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // SUBQH_R_PH |
| 3966 | { 2719, 3, 1, 4, 746, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // SUBQH_PH_MMR2 |
| 3967 | { 2718, 3, 1, 4, 582, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // SUBQH_PH |
| 3968 | { 2717, 3, 1, 4, 79, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SUB |
| 3969 | { 2716, 3, 0, 4, 221, 0, 0, MipsOpInfoBase + 882, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // ST_W |
| 3970 | { 2715, 3, 0, 4, 221, 0, 0, MipsOpInfoBase + 879, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // ST_H |
| 3971 | { 2714, 3, 0, 4, 221, 0, 0, MipsOpInfoBase + 876, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // ST_D |
| 3972 | { 2713, 3, 0, 4, 221, 0, 0, MipsOpInfoBase + 873, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // ST_B |
| 3973 | { 2712, 0, 0, 4, 238, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SSNOP_MMR6 |
| 3974 | { 2711, 0, 0, 4, 237, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SSNOP_MM |
| 3975 | { 2710, 0, 0, 4, 80, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SSNOP |
| 3976 | { 2709, 3, 1, 4, 178, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SRL_W |
| 3977 | { 2708, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x1ULL }, // SRL_MM |
| 3978 | { 2707, 3, 1, 4, 178, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SRL_H |
| 3979 | { 2706, 3, 1, 4, 178, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SRL_D |
| 3980 | { 2705, 3, 1, 4, 178, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SRL_B |
| 3981 | { 2704, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SRLV_MM |
| 3982 | { 2703, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SRLV |
| 3983 | { 2702, 3, 1, 4, 180, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SRLR_W |
| 3984 | { 2701, 3, 1, 4, 180, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SRLR_H |
| 3985 | { 2700, 3, 1, 4, 180, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SRLR_D |
| 3986 | { 2699, 3, 1, 4, 180, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SRLR_B |
| 3987 | { 2698, 3, 1, 4, 180, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SRLRI_W |
| 3988 | { 2697, 3, 1, 4, 180, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SRLRI_H |
| 3989 | { 2696, 3, 1, 4, 180, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SRLRI_D |
| 3990 | { 2695, 3, 1, 4, 180, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SRLRI_B |
| 3991 | { 2694, 3, 1, 4, 178, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SRLI_W |
| 3992 | { 2693, 3, 1, 4, 178, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SRLI_H |
| 3993 | { 2692, 3, 1, 4, 178, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SRLI_D |
| 3994 | { 2691, 3, 1, 4, 178, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SRLI_B |
| 3995 | { 2690, 3, 1, 2, 238, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SRL16_MMR6 |
| 3996 | { 2689, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 530, 0, 0, 0x0ULL }, // SRL16_MM |
| 3997 | { 2688, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x1ULL }, // SRL |
| 3998 | { 2687, 3, 1, 4, 177, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SRA_W |
| 3999 | { 2686, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x1ULL }, // SRA_MM |
| 4000 | { 2685, 3, 1, 4, 177, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SRA_H |
| 4001 | { 2684, 3, 1, 4, 177, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SRA_D |
| 4002 | { 2683, 3, 1, 4, 177, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SRA_B |
| 4003 | { 2682, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SRAV_MM |
| 4004 | { 2681, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SRAV |
| 4005 | { 2680, 3, 1, 4, 179, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SRAR_W |
| 4006 | { 2679, 3, 1, 4, 179, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SRAR_H |
| 4007 | { 2678, 3, 1, 4, 179, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SRAR_D |
| 4008 | { 2677, 3, 1, 4, 179, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SRAR_B |
| 4009 | { 2676, 3, 1, 4, 179, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SRARI_W |
| 4010 | { 2675, 3, 1, 4, 179, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SRARI_H |
| 4011 | { 2674, 3, 1, 4, 179, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SRARI_D |
| 4012 | { 2673, 3, 1, 4, 179, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SRARI_B |
| 4013 | { 2672, 3, 1, 4, 177, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SRAI_W |
| 4014 | { 2671, 3, 1, 4, 177, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SRAI_H |
| 4015 | { 2670, 3, 1, 4, 177, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SRAI_D |
| 4016 | { 2669, 3, 1, 4, 177, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SRAI_B |
| 4017 | { 2668, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x1ULL }, // SRA |
| 4018 | { 2667, 3, 1, 4, 39, 0, 0, MipsOpInfoBase + 1131, 0, 0, 0x6ULL }, // SPLAT_W |
| 4019 | { 2666, 3, 1, 4, 39, 0, 0, MipsOpInfoBase + 1128, 0, 0, 0x6ULL }, // SPLAT_H |
| 4020 | { 2665, 3, 1, 4, 39, 0, 0, MipsOpInfoBase + 1125, 0, 0, 0x6ULL }, // SPLAT_D |
| 4021 | { 2664, 3, 1, 4, 39, 0, 0, MipsOpInfoBase + 1122, 0, 0, 0x6ULL }, // SPLAT_B |
| 4022 | { 2663, 3, 1, 4, 40, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SPLATI_W |
| 4023 | { 2662, 3, 1, 4, 40, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SPLATI_H |
| 4024 | { 2661, 3, 1, 4, 40, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SPLATI_D |
| 4025 | { 2660, 3, 1, 4, 40, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SPLATI_B |
| 4026 | { 2659, 3, 1, 4, 375, 0, 0, MipsOpInfoBase + 234, 0, 0, 0x2ULL }, // SNEi |
| 4027 | { 2658, 3, 1, 4, 375, 0, 0, MipsOpInfoBase + 237, 0, 0, 0x1ULL }, // SNE |
| 4028 | { 2657, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SLTu_MM |
| 4029 | { 2656, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 1116, 0, 0, 0x1ULL }, // SLTu64 |
| 4030 | { 2655, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SLTu |
| 4031 | { 2654, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x2ULL }, // SLTiu_MM |
| 4032 | { 2653, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 1119, 0, 0, 0x2ULL }, // SLTiu64 |
| 4033 | { 2652, 3, 1, 4, 79, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x2ULL }, // SLTiu |
| 4034 | { 2651, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x2ULL }, // SLTi_MM |
| 4035 | { 2650, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 1119, 0, 0, 0x2ULL }, // SLTi64 |
| 4036 | { 2649, 3, 1, 4, 79, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x2ULL }, // SLTi |
| 4037 | { 2648, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SLT_MM |
| 4038 | { 2647, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 1116, 0, 0, 0x1ULL }, // SLT64 |
| 4039 | { 2646, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SLT |
| 4040 | { 2645, 3, 1, 4, 181, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // SLL_W |
| 4041 | { 2644, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SLL_MMR6 |
| 4042 | { 2643, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x1ULL }, // SLL_MM |
| 4043 | { 2642, 3, 1, 4, 181, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // SLL_H |
| 4044 | { 2641, 3, 1, 4, 181, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // SLL_D |
| 4045 | { 2640, 3, 1, 4, 181, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // SLL_B |
| 4046 | { 2639, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SLLV_MM |
| 4047 | { 2638, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // SLLV |
| 4048 | { 2637, 3, 1, 4, 181, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SLLI_W |
| 4049 | { 2636, 3, 1, 4, 181, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SLLI_H |
| 4050 | { 2635, 3, 1, 4, 181, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SLLI_D |
| 4051 | { 2634, 3, 1, 4, 181, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SLLI_B |
| 4052 | { 2633, 2, 1, 4, 239, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x1ULL }, // SLL64_64 |
| 4053 | { 2632, 2, 1, 4, 239, 0, 0, MipsOpInfoBase + 749, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // SLL64_32 |
| 4054 | { 2631, 3, 1, 2, 238, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLL16_MMR6 |
| 4055 | { 2630, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 530, 0, 0, 0x0ULL }, // SLL16_MM |
| 4056 | { 2629, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x1ULL }, // SLL |
| 4057 | { 2628, 4, 1, 4, 117, 0, 0, MipsOpInfoBase + 1112, 0, 0, 0x6ULL }, // SLD_W |
| 4058 | { 2627, 4, 1, 4, 117, 0, 0, MipsOpInfoBase + 1108, 0, 0, 0x6ULL }, // SLD_H |
| 4059 | { 2626, 4, 1, 4, 117, 0, 0, MipsOpInfoBase + 1104, 0, 0, 0x6ULL }, // SLD_D |
| 4060 | { 2625, 4, 1, 4, 117, 0, 0, MipsOpInfoBase + 1100, 0, 0, 0x6ULL }, // SLD_B |
| 4061 | { 2624, 4, 1, 4, 117, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // SLDI_W |
| 4062 | { 2623, 4, 1, 4, 117, 0, 0, MipsOpInfoBase + 601, 0, 0, 0x6ULL }, // SLDI_H |
| 4063 | { 2622, 4, 1, 4, 117, 0, 0, MipsOpInfoBase + 597, 0, 0, 0x6ULL }, // SLDI_D |
| 4064 | { 2621, 4, 1, 4, 117, 0, 0, MipsOpInfoBase + 593, 0, 0, 0x6ULL }, // SLDI_B |
| 4065 | { 2620, 1, 0, 4, 297, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SIGRIE_MMR6 |
| 4066 | { 2619, 1, 0, 4, 286, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SIGRIE |
| 4067 | { 2618, 3, 0, 4, 361, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SH_MMR6 |
| 4068 | { 2617, 3, 0, 4, 355, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SH_MM |
| 4069 | { 2616, 3, 1, 4, 701, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRL_QB_MM |
| 4070 | { 2615, 3, 1, 4, 535, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRL_QB |
| 4071 | { 2614, 3, 1, 4, 744, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRL_PH_MMR2 |
| 4072 | { 2613, 3, 1, 4, 580, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRL_PH |
| 4073 | { 2612, 3, 1, 4, 700, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRLV_QB_MM |
| 4074 | { 2611, 3, 1, 4, 534, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRLV_QB |
| 4075 | { 2610, 3, 1, 4, 745, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRLV_PH_MMR2 |
| 4076 | { 2609, 3, 1, 4, 581, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRLV_PH |
| 4077 | { 2608, 3, 1, 4, 699, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_W_MM |
| 4078 | { 2607, 3, 1, 4, 533, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_W |
| 4079 | { 2606, 3, 1, 4, 741, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_QB_MMR2 |
| 4080 | { 2605, 3, 1, 4, 577, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_QB |
| 4081 | { 2604, 3, 1, 4, 698, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_PH_MM |
| 4082 | { 2603, 3, 1, 4, 532, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_PH |
| 4083 | { 2602, 3, 1, 4, 740, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_QB_MMR2 |
| 4084 | { 2601, 3, 1, 4, 576, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_QB |
| 4085 | { 2600, 3, 1, 4, 697, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_PH_MM |
| 4086 | { 2599, 3, 1, 4, 531, 0, 0, MipsOpInfoBase + 1097, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_PH |
| 4087 | { 2598, 3, 1, 4, 696, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SHRAV_R_W_MM |
| 4088 | { 2597, 3, 1, 4, 530, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SHRAV_R_W |
| 4089 | { 2596, 3, 1, 4, 743, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRAV_R_QB_MMR2 |
| 4090 | { 2595, 3, 1, 4, 579, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRAV_R_QB |
| 4091 | { 2594, 3, 1, 4, 695, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRAV_R_PH_MM |
| 4092 | { 2593, 3, 1, 4, 529, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRAV_R_PH |
| 4093 | { 2592, 3, 1, 4, 742, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRAV_QB_MMR2 |
| 4094 | { 2591, 3, 1, 4, 578, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRAV_QB |
| 4095 | { 2590, 3, 1, 4, 694, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRAV_PH_MM |
| 4096 | { 2589, 3, 1, 4, 528, 0, 0, MipsOpInfoBase + 1094, 0, 0, 0x6ULL }, // SHRAV_PH |
| 4097 | { 2588, 3, 1, 4, 693, 0, 1, MipsOpInfoBase + 243, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_S_W_MM |
| 4098 | { 2587, 3, 1, 4, 527, 0, 1, MipsOpInfoBase + 243, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_S_W |
| 4099 | { 2586, 3, 1, 4, 692, 0, 1, MipsOpInfoBase + 1097, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_S_PH_MM |
| 4100 | { 2585, 3, 1, 4, 526, 0, 1, MipsOpInfoBase + 1097, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_S_PH |
| 4101 | { 2584, 3, 1, 4, 691, 0, 1, MipsOpInfoBase + 1097, 59, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_QB_MM |
| 4102 | { 2583, 3, 1, 4, 525, 0, 1, MipsOpInfoBase + 1097, 59, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_QB |
| 4103 | { 2582, 3, 1, 4, 690, 0, 1, MipsOpInfoBase + 1097, 59, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_PH_MM |
| 4104 | { 2581, 3, 1, 4, 524, 0, 1, MipsOpInfoBase + 1097, 59, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_PH |
| 4105 | { 2580, 3, 1, 4, 689, 0, 1, MipsOpInfoBase + 240, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_S_W_MM |
| 4106 | { 2579, 3, 1, 4, 523, 0, 1, MipsOpInfoBase + 240, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_S_W |
| 4107 | { 2578, 3, 1, 4, 688, 0, 1, MipsOpInfoBase + 1094, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_S_PH_MM |
| 4108 | { 2577, 3, 1, 4, 522, 0, 1, MipsOpInfoBase + 1094, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_S_PH |
| 4109 | { 2576, 3, 1, 4, 687, 0, 1, MipsOpInfoBase + 1094, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_QB_MM |
| 4110 | { 2575, 3, 1, 4, 521, 0, 1, MipsOpInfoBase + 1094, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_QB |
| 4111 | { 2574, 3, 1, 4, 686, 0, 1, MipsOpInfoBase + 1094, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_PH_MM |
| 4112 | { 2573, 3, 1, 4, 520, 0, 1, MipsOpInfoBase + 1094, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_PH |
| 4113 | { 2572, 3, 1, 4, 685, 0, 0, MipsOpInfoBase + 1091, 0, 0, 0x6ULL }, // SHILO_MM |
| 4114 | { 2571, 3, 1, 4, 684, 0, 0, MipsOpInfoBase + 1029, 0, 0, 0x6ULL }, // SHILOV_MM |
| 4115 | { 2570, 3, 1, 4, 518, 0, 0, MipsOpInfoBase + 1029, 0, 0, 0x6ULL }, // SHILOV |
| 4116 | { 2569, 3, 1, 4, 519, 0, 0, MipsOpInfoBase + 1091, 0, 0, 0x6ULL }, // SHILO |
| 4117 | { 2568, 3, 1, 4, 132, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SHF_W |
| 4118 | { 2567, 3, 1, 4, 132, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SHF_H |
| 4119 | { 2566, 3, 1, 4, 132, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SHF_B |
| 4120 | { 2565, 3, 0, 4, 349, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SHE_MM |
| 4121 | { 2564, 3, 0, 4, 346, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHE |
| 4122 | { 2563, 3, 0, 4, 370, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SH64 |
| 4123 | { 2562, 3, 0, 2, 361, 0, 0, MipsOpInfoBase + 1064, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SH16_MMR6 |
| 4124 | { 2561, 3, 0, 2, 355, 0, 0, MipsOpInfoBase + 1064, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SH16_MM |
| 4125 | { 2560, 3, 0, 4, 94, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SH |
| 4126 | { 2559, 3, 1, 4, 375, 0, 0, MipsOpInfoBase + 234, 0, 0, 0x2ULL }, // SEQi |
| 4127 | { 2558, 3, 1, 4, 375, 0, 0, MipsOpInfoBase + 237, 0, 0, 0x1ULL }, // SEQ |
| 4128 | { 2557, 4, 1, 4, 418, 0, 0, MipsOpInfoBase + 1087, 0, 0, 0x6ULL }, // SEL_S_MMR6 |
| 4129 | { 2556, 4, 1, 4, 386, 0, 0, MipsOpInfoBase + 1087, 0, 0, 0x6ULL }, // SEL_S |
| 4130 | { 2555, 4, 1, 4, 418, 0, 0, MipsOpInfoBase + 1083, 0, 0, 0x6ULL }, // SEL_D_MMR6 |
| 4131 | { 2554, 4, 1, 4, 386, 0, 0, MipsOpInfoBase + 1083, 0, 0, 0x6ULL }, // SEL_D |
| 4132 | { 2553, 3, 1, 4, 417, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELNEZ_S_MMR6 |
| 4133 | { 2552, 3, 1, 4, 385, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELNEZ_S |
| 4134 | { 2551, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SELNEZ_MMR6 |
| 4135 | { 2550, 3, 1, 4, 417, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELNEZ_D_MMR6 |
| 4136 | { 2549, 3, 1, 4, 385, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELNEZ_D |
| 4137 | { 2548, 3, 1, 4, 242, 0, 0, MipsOpInfoBase + 237, 0, 0, 0x6ULL }, // SELNEZ64 |
| 4138 | { 2547, 3, 1, 4, 234, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SELNEZ |
| 4139 | { 2546, 3, 1, 4, 417, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELEQZ_S_MMR6 |
| 4140 | { 2545, 3, 1, 4, 385, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELEQZ_S |
| 4141 | { 2544, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SELEQZ_MMR6 |
| 4142 | { 2543, 3, 1, 4, 417, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELEQZ_D_MMR6 |
| 4143 | { 2542, 3, 1, 4, 385, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELEQZ_D |
| 4144 | { 2541, 3, 1, 4, 242, 0, 0, MipsOpInfoBase + 237, 0, 0, 0x6ULL }, // SELEQZ64 |
| 4145 | { 2540, 3, 1, 4, 234, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // SELEQZ |
| 4146 | { 2539, 2, 1, 4, 237, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // SEH_MM |
| 4147 | { 2538, 2, 1, 4, 239, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x1ULL }, // SEH64 |
| 4148 | { 2537, 2, 1, 4, 229, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // SEH |
| 4149 | { 2536, 2, 1, 4, 237, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // SEB_MM |
| 4150 | { 2535, 2, 1, 4, 239, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x1ULL }, // SEB64 |
| 4151 | { 2534, 2, 1, 4, 229, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // SEB |
| 4152 | { 2533, 3, 0, 4, 220, 0, 0, MipsOpInfoBase + 870, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDXC164 |
| 4153 | { 2532, 3, 0, 4, 220, 0, 0, MipsOpInfoBase + 867, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDXC1 |
| 4154 | { 2531, 3, 0, 4, 371, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SDR |
| 4155 | { 2530, 3, 0, 4, 371, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SDL |
| 4156 | { 2529, 2, 0, 4, 257, 0, 2, MipsOpInfoBase + 151, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SDIV_MM |
| 4157 | { 2528, 2, 0, 4, 104, 0, 2, MipsOpInfoBase + 151, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SDIV |
| 4158 | { 2527, 3, 0, 4, 94, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC3 |
| 4159 | { 2526, 3, 0, 4, 342, 0, 0, MipsOpInfoBase + 846, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SDC2_R6 |
| 4160 | { 2525, 3, 0, 4, 361, 0, 0, MipsOpInfoBase + 849, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // SDC2_MMR6 |
| 4161 | { 2524, 3, 0, 4, 336, 0, 0, MipsOpInfoBase + 846, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC2 |
| 4162 | { 2523, 3, 0, 4, 402, 0, 0, MipsOpInfoBase + 843, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC1_MM_D64 |
| 4163 | { 2522, 3, 0, 4, 402, 0, 0, MipsOpInfoBase + 495, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC1_MM_D32 |
| 4164 | { 2521, 3, 0, 4, 423, 0, 0, MipsOpInfoBase + 843, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // SDC1_D64_MMR6 |
| 4165 | { 2520, 3, 0, 4, 219, 0, 0, MipsOpInfoBase + 843, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC164 |
| 4166 | { 2519, 3, 0, 4, 219, 0, 0, MipsOpInfoBase + 495, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC1 |
| 4167 | { 2518, 1, 0, 4, 288, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // SDBBP_R6 |
| 4168 | { 2517, 1, 0, 4, 300, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SDBBP_MMR6 |
| 4169 | { 2516, 1, 0, 4, 296, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // SDBBP_MM |
| 4170 | { 2515, 1, 0, 2, 300, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDBBP16_MMR6 |
| 4171 | { 2514, 1, 0, 2, 296, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDBBP16_MM |
| 4172 | { 2513, 1, 0, 4, 82, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // SDBBP |
| 4173 | { 2512, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SD |
| 4174 | { 2511, 4, 1, 4, 343, 0, 0, MipsOpInfoBase + 1071, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SC_R6 |
| 4175 | { 2510, 4, 1, 4, 339, 0, 0, MipsOpInfoBase + 1067, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SC_MMR6 |
| 4176 | { 2509, 4, 1, 4, 355, 0, 0, MipsOpInfoBase + 1067, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SC_MM |
| 4177 | { 2508, 4, 1, 4, 349, 0, 0, MipsOpInfoBase + 1067, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SCE_MM |
| 4178 | { 2507, 4, 1, 4, 346, 0, 0, MipsOpInfoBase + 1067, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SCE |
| 4179 | { 2506, 4, 1, 4, 2, 0, 0, MipsOpInfoBase + 1079, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SCD_R6 |
| 4180 | { 2505, 4, 1, 4, 369, 0, 0, MipsOpInfoBase + 1075, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SCD |
| 4181 | { 2504, 4, 1, 4, 2, 0, 0, MipsOpInfoBase + 1071, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SC64_R6 |
| 4182 | { 2503, 4, 1, 4, 369, 0, 0, MipsOpInfoBase + 1067, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SC64 |
| 4183 | { 2502, 4, 1, 4, 338, 0, 0, MipsOpInfoBase + 1067, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SC |
| 4184 | { 2501, 3, 0, 4, 361, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SB_MMR6 |
| 4185 | { 2500, 3, 0, 4, 349, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SB_MM |
| 4186 | { 2499, 3, 0, 4, 349, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SBE_MM |
| 4187 | { 2498, 3, 0, 4, 346, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SBE |
| 4188 | { 2497, 3, 0, 4, 370, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SB64 |
| 4189 | { 2496, 3, 0, 2, 361, 0, 0, MipsOpInfoBase + 1064, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SB16_MMR6 |
| 4190 | { 2495, 3, 0, 2, 355, 0, 0, MipsOpInfoBase + 1064, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SB16_MM |
| 4191 | { 2494, 3, 0, 4, 94, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SB |
| 4192 | { 2493, 3, 1, 4, 23, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SAT_U_W |
| 4193 | { 2492, 3, 1, 4, 23, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SAT_U_H |
| 4194 | { 2491, 3, 1, 4, 23, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SAT_U_D |
| 4195 | { 2490, 3, 1, 4, 23, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SAT_U_B |
| 4196 | { 2489, 3, 1, 4, 23, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // SAT_S_W |
| 4197 | { 2488, 3, 1, 4, 23, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SAT_S_H |
| 4198 | { 2487, 3, 1, 4, 23, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // SAT_S_D |
| 4199 | { 2486, 3, 1, 4, 23, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SAT_S_B |
| 4200 | { 2485, 2, 0, 4, 377, 0, 0, MipsOpInfoBase + 388, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SAAD |
| 4201 | { 2484, 2, 0, 4, 377, 0, 0, MipsOpInfoBase + 388, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SAA |
| 4202 | { 2483, 0, 0, 2, 352, 1, 1, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RestoreX16 |
| 4203 | { 2482, 0, 0, 2, 352, 1, 1, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Restore16 |
| 4204 | { 2481, 2, 1, 4, 400, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_S_MM |
| 4205 | { 2480, 2, 1, 4, 198, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_S |
| 4206 | { 2479, 2, 1, 4, 401, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_D64_MM |
| 4207 | { 2478, 2, 1, 4, 197, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_D64 |
| 4208 | { 2477, 2, 1, 4, 401, 1, 0, MipsOpInfoBase + 757, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_D32_MM |
| 4209 | { 2476, 2, 1, 4, 197, 1, 0, MipsOpInfoBase + 757, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_D32 |
| 4210 | { 2475, 2, 1, 4, 411, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_S_MMR6 |
| 4211 | { 2474, 2, 1, 4, 388, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_S_MM |
| 4212 | { 2473, 2, 1, 4, 227, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_S |
| 4213 | { 2472, 2, 1, 4, 388, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_MM |
| 4214 | { 2471, 2, 1, 4, 411, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_D_MMR6 |
| 4215 | { 2470, 2, 1, 4, 227, 0, 0, MipsOpInfoBase + 632, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_D64 |
| 4216 | { 2469, 2, 1, 4, 227, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_D32 |
| 4217 | { 2468, 2, 1, 4, 411, 0, 0, MipsOpInfoBase + 628, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_L_S_MMR6 |
| 4218 | { 2467, 2, 1, 4, 227, 0, 0, MipsOpInfoBase + 628, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_L_S |
| 4219 | { 2466, 2, 1, 4, 411, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_L_D_MMR6 |
| 4220 | { 2465, 2, 1, 4, 227, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_L_D64 |
| 4221 | { 2464, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x1ULL }, // ROTR_MM |
| 4222 | { 2463, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // ROTRV_MM |
| 4223 | { 2462, 3, 1, 4, 228, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x1ULL }, // ROTRV |
| 4224 | { 2461, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 243, 0, 0, 0x1ULL }, // ROTR |
| 4225 | { 2460, 2, 1, 4, 419, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RINT_S_MMR6 |
| 4226 | { 2459, 2, 1, 4, 62, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RINT_S |
| 4227 | { 2458, 2, 1, 4, 419, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RINT_D_MMR6 |
| 4228 | { 2457, 2, 1, 4, 62, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RINT_D |
| 4229 | { 2456, 2, 1, 4, 683, 0, 0, MipsOpInfoBase + 1062, 0, 0, 0x6ULL }, // REPL_QB_MM |
| 4230 | { 2455, 2, 1, 4, 517, 0, 0, MipsOpInfoBase + 1062, 0, 0, 0x6ULL }, // REPL_QB |
| 4231 | { 2454, 2, 1, 4, 682, 0, 0, MipsOpInfoBase + 1062, 0, 0, 0x6ULL }, // REPL_PH_MM |
| 4232 | { 2453, 2, 1, 4, 516, 0, 0, MipsOpInfoBase + 1062, 0, 0, 0x6ULL }, // REPL_PH |
| 4233 | { 2452, 2, 1, 4, 681, 0, 0, MipsOpInfoBase + 1060, 0, 0, 0x6ULL }, // REPLV_QB_MM |
| 4234 | { 2451, 2, 1, 4, 515, 0, 0, MipsOpInfoBase + 1060, 0, 0, 0x6ULL }, // REPLV_QB |
| 4235 | { 2450, 2, 1, 4, 680, 0, 0, MipsOpInfoBase + 1060, 0, 0, 0x6ULL }, // REPLV_PH_MM |
| 4236 | { 2449, 2, 1, 4, 514, 0, 0, MipsOpInfoBase + 1060, 0, 0, 0x6ULL }, // REPLV_PH |
| 4237 | { 2448, 2, 1, 4, 400, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_S_MM |
| 4238 | { 2447, 2, 1, 4, 198, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_S |
| 4239 | { 2446, 2, 1, 4, 401, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_D64_MM |
| 4240 | { 2445, 2, 1, 4, 197, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_D64 |
| 4241 | { 2444, 2, 1, 4, 401, 1, 0, MipsOpInfoBase + 757, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_D32_MM |
| 4242 | { 2443, 2, 1, 4, 197, 1, 0, MipsOpInfoBase + 757, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_D32 |
| 4243 | { 2442, 2, 1, 4, 317, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RDPGPR_MMR6 |
| 4244 | { 2441, 3, 1, 4, 263, 0, 0, MipsOpInfoBase + 1054, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // RDHWR_MMR6 |
| 4245 | { 2440, 3, 1, 4, 260, 0, 0, MipsOpInfoBase + 1054, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // RDHWR_MM |
| 4246 | { 2439, 3, 1, 4, 270, 0, 0, MipsOpInfoBase + 1057, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // RDHWR64 |
| 4247 | { 2438, 3, 1, 4, 248, 0, 0, MipsOpInfoBase + 1054, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // RDHWR |
| 4248 | { 2437, 2, 1, 4, 679, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // RDDSP_MM |
| 4249 | { 2436, 2, 1, 4, 513, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // RDDSP |
| 4250 | { 2435, 2, 1, 4, 678, 0, 0, MipsOpInfoBase + 1042, 0, 0, 0x6ULL }, // RADDU_W_QB_MM |
| 4251 | { 2434, 2, 1, 4, 512, 0, 0, MipsOpInfoBase + 1042, 0, 0, 0x6ULL }, // RADDU_W_QB |
| 4252 | { 2433, 3, 1, 4, 190, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // PUU_PS64 |
| 4253 | { 2432, 3, 1, 4, 190, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // PUL_PS64 |
| 4254 | { 2431, 4, 1, 4, 739, 0, 0, MipsOpInfoBase + 567, 0, 0, 0x6ULL }, // PREPEND_MMR2 |
| 4255 | { 2430, 4, 1, 4, 575, 0, 0, MipsOpInfoBase + 567, 0, 0, 0x6ULL }, // PREPEND |
| 4256 | { 2429, 3, 0, 4, 4, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREF_R6 |
| 4257 | { 2428, 3, 0, 4, 363, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREF_MMR6 |
| 4258 | { 2427, 3, 0, 4, 356, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREF_MM |
| 4259 | { 2426, 3, 0, 4, 356, 0, 0, MipsOpInfoBase + 1051, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREFX_MM |
| 4260 | { 2425, 3, 0, 4, 350, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREFE_MM |
| 4261 | { 2424, 3, 0, 4, 347, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREFE |
| 4262 | { 2423, 3, 0, 4, 96, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREF |
| 4263 | { 2422, 4, 1, 4, 738, 0, 0, MipsOpInfoBase + 1047, 0, 0, 0x6ULL }, // PRECR_SRA_R_PH_W_MMR2 |
| 4264 | { 2421, 4, 1, 4, 574, 0, 0, MipsOpInfoBase + 1047, 0, 0, 0x6ULL }, // PRECR_SRA_R_PH_W |
| 4265 | { 2420, 4, 1, 4, 737, 0, 0, MipsOpInfoBase + 1047, 0, 0, 0x6ULL }, // PRECR_SRA_PH_W_MMR2 |
| 4266 | { 2419, 4, 1, 4, 573, 0, 0, MipsOpInfoBase + 1047, 0, 0, 0x6ULL }, // PRECR_SRA_PH_W |
| 4267 | { 2418, 3, 1, 4, 736, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECR_QB_PH_MMR2 |
| 4268 | { 2417, 3, 1, 4, 572, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECR_QB_PH |
| 4269 | { 2416, 3, 1, 4, 677, 0, 1, MipsOpInfoBase + 1044, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECRQ_RS_PH_W_MM |
| 4270 | { 2415, 3, 1, 4, 511, 0, 1, MipsOpInfoBase + 1044, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECRQ_RS_PH_W |
| 4271 | { 2414, 3, 1, 4, 676, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // PRECRQ_QB_PH_MM |
| 4272 | { 2413, 3, 1, 4, 510, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // PRECRQ_QB_PH |
| 4273 | { 2412, 3, 1, 4, 675, 0, 0, MipsOpInfoBase + 1044, 0, 0, 0x6ULL }, // PRECRQ_PH_W_MM |
| 4274 | { 2411, 3, 1, 4, 509, 0, 0, MipsOpInfoBase + 1044, 0, 0, 0x6ULL }, // PRECRQ_PH_W |
| 4275 | { 2410, 3, 1, 4, 674, 0, 1, MipsOpInfoBase + 536, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECRQU_S_QB_PH_MM |
| 4276 | { 2409, 3, 1, 4, 508, 0, 1, MipsOpInfoBase + 536, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECRQU_S_QB_PH |
| 4277 | { 2408, 2, 1, 4, 673, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEU_PH_QBR_MM |
| 4278 | { 2407, 2, 1, 4, 672, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEU_PH_QBRA_MM |
| 4279 | { 2406, 2, 1, 4, 506, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEU_PH_QBRA |
| 4280 | { 2405, 2, 1, 4, 507, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEU_PH_QBR |
| 4281 | { 2404, 2, 1, 4, 671, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEU_PH_QBL_MM |
| 4282 | { 2403, 2, 1, 4, 670, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEU_PH_QBLA_MM |
| 4283 | { 2402, 2, 1, 4, 504, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEU_PH_QBLA |
| 4284 | { 2401, 2, 1, 4, 505, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEU_PH_QBL |
| 4285 | { 2400, 2, 1, 4, 669, 0, 0, MipsOpInfoBase + 1042, 0, 0, 0x6ULL }, // PRECEQ_W_PHR_MM |
| 4286 | { 2399, 2, 1, 4, 503, 0, 0, MipsOpInfoBase + 1042, 0, 0, 0x6ULL }, // PRECEQ_W_PHR |
| 4287 | { 2398, 2, 1, 4, 668, 0, 0, MipsOpInfoBase + 1042, 0, 0, 0x6ULL }, // PRECEQ_W_PHL_MM |
| 4288 | { 2397, 2, 1, 4, 502, 0, 0, MipsOpInfoBase + 1042, 0, 0, 0x6ULL }, // PRECEQ_W_PHL |
| 4289 | { 2396, 2, 1, 4, 667, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEQU_PH_QBR_MM |
| 4290 | { 2395, 2, 1, 4, 666, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEQU_PH_QBRA_MM |
| 4291 | { 2394, 2, 1, 4, 500, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEQU_PH_QBRA |
| 4292 | { 2393, 2, 1, 4, 501, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEQU_PH_QBR |
| 4293 | { 2392, 2, 1, 4, 665, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEQU_PH_QBL_MM |
| 4294 | { 2391, 2, 1, 4, 664, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEQU_PH_QBLA_MM |
| 4295 | { 2390, 2, 1, 4, 498, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEQU_PH_QBLA |
| 4296 | { 2389, 2, 1, 4, 499, 0, 0, MipsOpInfoBase + 526, 0, 0, 0x6ULL }, // PRECEQU_PH_QBL |
| 4297 | { 2388, 2, 1, 4, 375, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // POP |
| 4298 | { 2387, 3, 1, 4, 190, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // PLU_PS64 |
| 4299 | { 2386, 3, 1, 4, 190, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // PLL_PS64 |
| 4300 | { 2385, 3, 1, 4, 663, 1, 0, MipsOpInfoBase + 536, 15, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // PICK_QB_MM |
| 4301 | { 2384, 3, 1, 4, 497, 1, 0, MipsOpInfoBase + 536, 15, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // PICK_QB |
| 4302 | { 2383, 3, 1, 4, 662, 1, 0, MipsOpInfoBase + 536, 15, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // PICK_PH_MM |
| 4303 | { 2382, 3, 1, 4, 496, 1, 0, MipsOpInfoBase + 536, 15, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // PICK_PH |
| 4304 | { 2381, 2, 1, 4, 122, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // PCNT_W |
| 4305 | { 2380, 2, 1, 4, 122, 0, 0, MipsOpInfoBase + 1038, 0, 0, 0x6ULL }, // PCNT_H |
| 4306 | { 2379, 2, 1, 4, 122, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // PCNT_D |
| 4307 | { 2378, 2, 1, 4, 122, 0, 0, MipsOpInfoBase + 960, 0, 0, 0x6ULL }, // PCNT_B |
| 4308 | { 2377, 3, 1, 4, 35, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // PCKOD_W |
| 4309 | { 2376, 3, 1, 4, 35, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // PCKOD_H |
| 4310 | { 2375, 3, 1, 4, 35, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // PCKOD_D |
| 4311 | { 2374, 3, 1, 4, 35, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // PCKOD_B |
| 4312 | { 2373, 3, 1, 4, 34, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // PCKEV_W |
| 4313 | { 2372, 3, 1, 4, 34, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // PCKEV_H |
| 4314 | { 2371, 3, 1, 4, 34, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // PCKEV_D |
| 4315 | { 2370, 3, 1, 4, 34, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // PCKEV_B |
| 4316 | { 2369, 0, 0, 4, 323, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PAUSE_MMR6 |
| 4317 | { 2368, 0, 0, 4, 316, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PAUSE_MM |
| 4318 | { 2367, 0, 0, 4, 84, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // PAUSE |
| 4319 | { 2366, 3, 1, 4, 661, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // PACKRL_PH_MM |
| 4320 | { 2365, 3, 1, 4, 495, 0, 0, MipsOpInfoBase + 536, 0, 0, 0x6ULL }, // PACKRL_PH |
| 4321 | { 2364, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 579, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // OrRxRxRy16 |
| 4322 | { 2363, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ORi_MM |
| 4323 | { 2362, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ORi64 |
| 4324 | { 2361, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ORi |
| 4325 | { 2360, 3, 1, 4, 134, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // OR_V |
| 4326 | { 2359, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // OR_MMR6 |
| 4327 | { 2358, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // OR_MM |
| 4328 | { 2357, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ORI_MMR6 |
| 4329 | { 2356, 3, 1, 4, 25, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // ORI_B |
| 4330 | { 2355, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // OR64 |
| 4331 | { 2354, 3, 1, 2, 238, 0, 0, MipsOpInfoBase + 564, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // OR16_MMR6 |
| 4332 | { 2353, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 564, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // OR16_MM |
| 4333 | { 2352, 3, 1, 4, 79, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // OR |
| 4334 | { 2351, 2, 1, 2, 235, 0, 0, MipsOpInfoBase + 397, 0, 0, 0x0ULL }, // NotRxRy16 |
| 4335 | { 2350, 2, 1, 2, 235, 0, 0, MipsOpInfoBase + 397, 0, 0, 0x0ULL }, // NegRxRy16 |
| 4336 | { 2349, 2, 1, 2, 238, 0, 0, MipsOpInfoBase + 1040, 0, 0, 0x0ULL }, // NOT16_MMR6 |
| 4337 | { 2348, 2, 1, 2, 237, 0, 0, MipsOpInfoBase + 1040, 0, 0, 0x0ULL }, // NOT16_MM |
| 4338 | { 2347, 3, 1, 4, 134, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // NOR_V |
| 4339 | { 2346, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // NOR_MMR6 |
| 4340 | { 2345, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // NOR_MM |
| 4341 | { 2344, 3, 1, 4, 25, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // NORI_B |
| 4342 | { 2343, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // NOR64 |
| 4343 | { 2342, 3, 1, 4, 79, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // NOR |
| 4344 | { 2341, 4, 1, 4, 388, 1, 0, MipsOpInfoBase + 940, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_S_MM |
| 4345 | { 2340, 4, 1, 4, 380, 1, 0, MipsOpInfoBase + 940, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_S |
| 4346 | { 2339, 4, 1, 4, 213, 1, 0, MipsOpInfoBase + 936, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_D64 |
| 4347 | { 2338, 4, 1, 4, 388, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_D32_MM |
| 4348 | { 2337, 4, 1, 4, 213, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_D32 |
| 4349 | { 2336, 4, 1, 4, 388, 1, 0, MipsOpInfoBase + 940, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_S_MM |
| 4350 | { 2335, 4, 1, 4, 380, 1, 0, MipsOpInfoBase + 940, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_S |
| 4351 | { 2334, 4, 1, 4, 213, 1, 0, MipsOpInfoBase + 936, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_D64 |
| 4352 | { 2333, 4, 1, 4, 388, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_D32_MM |
| 4353 | { 2332, 4, 1, 4, 213, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_D32 |
| 4354 | { 2331, 2, 1, 4, 24, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // NLZC_W |
| 4355 | { 2330, 2, 1, 4, 24, 0, 0, MipsOpInfoBase + 1038, 0, 0, 0x6ULL }, // NLZC_H |
| 4356 | { 2329, 2, 1, 4, 24, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // NLZC_D |
| 4357 | { 2328, 2, 1, 4, 24, 0, 0, MipsOpInfoBase + 960, 0, 0, 0x6ULL }, // NLZC_B |
| 4358 | { 2327, 2, 1, 4, 24, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // NLOC_W |
| 4359 | { 2326, 2, 1, 4, 24, 0, 0, MipsOpInfoBase + 1038, 0, 0, 0x6ULL }, // NLOC_H |
| 4360 | { 2325, 2, 1, 4, 24, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // NLOC_D |
| 4361 | { 2324, 2, 1, 4, 24, 0, 0, MipsOpInfoBase + 960, 0, 0, 0x6ULL }, // NLOC_B |
| 4362 | { 2323, 0, 0, 4, 275, 0, 1, MipsOpInfoBase + 1, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // NAL |
| 4363 | { 2322, 2, 1, 2, 235, 0, 0, MipsOpInfoBase + 1036, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MoveR3216 |
| 4364 | { 2321, 2, 1, 2, 235, 0, 0, MipsOpInfoBase + 1034, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Move32R16 |
| 4365 | { 2320, 1, 1, 2, 235, 1, 0, MipsOpInfoBase + 836, 41, 0, 0x0ULL }, // Mflo16 |
| 4366 | { 2319, 1, 1, 2, 235, 1, 0, MipsOpInfoBase + 836, 39, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Mfhi16 |
| 4367 | { 2318, 3, 1, 4, 731, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MUL_S_PH_MMR2 |
| 4368 | { 2317, 3, 1, 4, 567, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MUL_S_PH |
| 4369 | { 2316, 3, 1, 4, 250, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // MUL_R6 |
| 4370 | { 2315, 3, 1, 4, 67, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MUL_Q_W |
| 4371 | { 2314, 3, 1, 4, 67, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MUL_Q_H |
| 4372 | { 2313, 3, 1, 4, 730, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MUL_PH_MMR2 |
| 4373 | { 2312, 3, 1, 4, 566, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MUL_PH |
| 4374 | { 2311, 3, 1, 4, 261, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUL_MMR6 |
| 4375 | { 2310, 3, 1, 4, 256, 0, 2, MipsOpInfoBase + 240, 7, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUL_MM |
| 4376 | { 2309, 3, 1, 4, 207, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MULV_W |
| 4377 | { 2308, 3, 1, 4, 207, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MULV_H |
| 4378 | { 2307, 3, 1, 4, 207, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MULV_D |
| 4379 | { 2306, 3, 1, 4, 207, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MULV_B |
| 4380 | { 2305, 3, 1, 4, 261, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MULU_MMR6 |
| 4381 | { 2304, 3, 1, 4, 250, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULU |
| 4382 | { 2303, 2, 0, 4, 255, 0, 2, MipsOpInfoBase + 151, 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // MULTu_MM |
| 4383 | { 2302, 2, 0, 4, 108, 0, 2, MipsOpInfoBase + 151, 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // MULTu |
| 4384 | { 2301, 2, 0, 4, 255, 0, 2, MipsOpInfoBase + 151, 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // MULT_MM |
| 4385 | { 2300, 3, 1, 4, 660, 0, 0, MipsOpInfoBase + 439, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // MULT_DSP_MM |
| 4386 | { 2299, 3, 1, 4, 494, 0, 0, MipsOpInfoBase + 439, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // MULT_DSP |
| 4387 | { 2298, 3, 1, 4, 659, 0, 0, MipsOpInfoBase + 439, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // MULTU_DSP_MM |
| 4388 | { 2297, 3, 1, 4, 493, 0, 0, MipsOpInfoBase + 439, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // MULTU_DSP |
| 4389 | { 2296, 2, 0, 4, 108, 0, 2, MipsOpInfoBase + 151, 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // MULT |
| 4390 | { 2295, 4, 1, 4, 735, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // MULSA_W_PH_MMR2 |
| 4391 | { 2294, 4, 1, 4, 571, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // MULSA_W_PH |
| 4392 | { 2293, 4, 1, 4, 658, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULSAQ_S_W_PH_MM |
| 4393 | { 2292, 4, 1, 4, 492, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULSAQ_S_W_PH |
| 4394 | { 2291, 3, 1, 4, 212, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MULR_Q_W |
| 4395 | { 2290, 3, 1, 4, 212, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MULR_Q_H |
| 4396 | { 2289, 3, 1, 4, 382, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MULR_PS64 |
| 4397 | { 2288, 3, 1, 4, 734, 0, 1, MipsOpInfoBase + 240, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_S_W_MMR2 |
| 4398 | { 2287, 3, 1, 4, 570, 0, 1, MipsOpInfoBase + 240, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_S_W |
| 4399 | { 2286, 3, 1, 4, 733, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_S_PH_MMR2 |
| 4400 | { 2285, 3, 1, 4, 569, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_S_PH |
| 4401 | { 2284, 3, 1, 4, 732, 0, 1, MipsOpInfoBase + 240, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_RS_W_MMR2 |
| 4402 | { 2283, 3, 1, 4, 568, 0, 1, MipsOpInfoBase + 240, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_RS_W |
| 4403 | { 2282, 3, 1, 4, 657, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_RS_PH_MM |
| 4404 | { 2281, 3, 1, 4, 491, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_RS_PH |
| 4405 | { 2280, 3, 1, 4, 656, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEU_S_PH_QBR_MM |
| 4406 | { 2279, 3, 1, 4, 490, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEU_S_PH_QBR |
| 4407 | { 2278, 3, 1, 4, 655, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEU_S_PH_QBL_MM |
| 4408 | { 2277, 3, 1, 4, 489, 0, 1, MipsOpInfoBase + 536, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEU_S_PH_QBL |
| 4409 | { 2276, 3, 1, 4, 654, 0, 1, MipsOpInfoBase + 654, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEQ_S_W_PHR_MM |
| 4410 | { 2275, 3, 1, 4, 488, 0, 1, MipsOpInfoBase + 654, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEQ_S_W_PHR |
| 4411 | { 2274, 3, 1, 4, 653, 0, 1, MipsOpInfoBase + 654, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEQ_S_W_PHL_MM |
| 4412 | { 2273, 3, 1, 4, 487, 0, 1, MipsOpInfoBase + 654, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEQ_S_W_PHL |
| 4413 | { 2272, 3, 1, 4, 107, 0, 2, MipsOpInfoBase + 240, 7, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUL |
| 4414 | { 2271, 3, 1, 4, 261, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUH_MMR6 |
| 4415 | { 2270, 3, 1, 4, 261, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUHU_MMR6 |
| 4416 | { 2269, 3, 1, 4, 250, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // MUHU |
| 4417 | { 2268, 3, 1, 4, 250, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // MUH |
| 4418 | { 2267, 5, 1, 4, 328, 0, 0, MipsOpInfoBase + 951, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTTR |
| 4419 | { 2266, 1, 0, 4, 375, 0, 1, MipsOpInfoBase + 320, 57, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTP2 |
| 4420 | { 2265, 1, 0, 4, 375, 0, 1, MipsOpInfoBase + 320, 56, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTP1 |
| 4421 | { 2264, 1, 0, 4, 375, 0, 1, MipsOpInfoBase + 320, 55, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTP0 |
| 4422 | { 2263, 1, 0, 4, 375, 0, 4, MipsOpInfoBase + 320, 51, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTM2 |
| 4423 | { 2262, 1, 0, 4, 375, 0, 4, MipsOpInfoBase + 320, 47, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTM1 |
| 4424 | { 2261, 1, 0, 4, 375, 0, 4, MipsOpInfoBase + 320, 43, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTM0 |
| 4425 | { 2260, 1, 0, 4, 259, 0, 1, MipsOpInfoBase + 196, 41, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTLO_MM |
| 4426 | { 2259, 2, 1, 4, 652, 0, 0, MipsOpInfoBase + 1032, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTLO_DSP_MM |
| 4427 | { 2258, 2, 1, 4, 440, 0, 0, MipsOpInfoBase + 1032, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTLO_DSP |
| 4428 | { 2257, 1, 0, 4, 269, 0, 1, MipsOpInfoBase + 320, 42, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTLO64 |
| 4429 | { 2256, 1, 0, 4, 109, 0, 1, MipsOpInfoBase + 196, 41, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTLO |
| 4430 | { 2255, 3, 1, 4, 651, 0, 1, MipsOpInfoBase + 1029, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHLIP_MM |
| 4431 | { 2254, 3, 1, 4, 438, 0, 1, MipsOpInfoBase + 1029, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHLIP |
| 4432 | { 2253, 1, 0, 4, 259, 0, 1, MipsOpInfoBase + 196, 39, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTHI_MM |
| 4433 | { 2252, 2, 1, 4, 650, 0, 0, MipsOpInfoBase + 1027, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHI_DSP_MM |
| 4434 | { 2251, 2, 1, 4, 439, 0, 0, MipsOpInfoBase + 1027, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHI_DSP |
| 4435 | { 2250, 1, 0, 4, 269, 0, 1, MipsOpInfoBase + 320, 40, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTHI64 |
| 4436 | { 2249, 1, 0, 4, 109, 0, 1, MipsOpInfoBase + 196, 39, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTHI |
| 4437 | { 2248, 3, 1, 4, 332, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MTHGC0_MM |
| 4438 | { 2247, 3, 1, 4, 90, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHGC0 |
| 4439 | { 2246, 2, 1, 4, 320, 0, 0, MipsOpInfoBase + 677, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHC2_MMR6 |
| 4440 | { 2245, 3, 1, 4, 394, 0, 0, MipsOpInfoBase + 1024, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHC1_D64_MM |
| 4441 | { 2244, 3, 1, 4, 214, 0, 0, MipsOpInfoBase + 1024, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHC1_D64 |
| 4442 | { 2243, 3, 1, 4, 394, 0, 0, MipsOpInfoBase + 1021, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHC1_D32_MM |
| 4443 | { 2242, 3, 1, 4, 214, 0, 0, MipsOpInfoBase + 1021, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHC1_D32 |
| 4444 | { 2241, 3, 1, 4, 320, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHC0_MMR6 |
| 4445 | { 2240, 3, 1, 4, 332, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MTGC0_MM |
| 4446 | { 2239, 3, 1, 4, 90, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTGC0 |
| 4447 | { 2238, 2, 1, 4, 320, 0, 0, MipsOpInfoBase + 677, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTC2_MMR6 |
| 4448 | { 2237, 3, 1, 4, 89, 0, 0, MipsOpInfoBase + 1018, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTC2 |
| 4449 | { 2236, 2, 1, 4, 414, 0, 0, MipsOpInfoBase + 395, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // MTC1_MMR6 |
| 4450 | { 2235, 2, 1, 4, 394, 0, 0, MipsOpInfoBase + 395, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // MTC1_MM |
| 4451 | { 2234, 2, 1, 4, 394, 0, 0, MipsOpInfoBase + 409, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // MTC1_D64_MM |
| 4452 | { 2233, 2, 1, 4, 214, 0, 0, MipsOpInfoBase + 409, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // MTC1_D64 |
| 4453 | { 2232, 2, 1, 4, 214, 0, 0, MipsOpInfoBase + 395, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // MTC1 |
| 4454 | { 2231, 3, 1, 4, 320, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTC0_MMR6 |
| 4455 | { 2230, 3, 1, 4, 312, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTC0_MM |
| 4456 | { 2229, 3, 1, 4, 88, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTC0 |
| 4457 | { 2228, 4, 1, 4, 395, 1, 0, MipsOpInfoBase + 940, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MSUB_S_MM |
| 4458 | { 2227, 4, 1, 4, 380, 1, 0, MipsOpInfoBase + 940, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MSUB_S |
| 4459 | { 2226, 4, 1, 4, 211, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // MSUB_Q_W |
| 4460 | { 2225, 4, 1, 4, 211, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MSUB_Q_H |
| 4461 | { 2224, 2, 0, 4, 255, 2, 2, MipsOpInfoBase + 151, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MSUB_MM |
| 4462 | { 2223, 4, 1, 4, 649, 0, 0, MipsOpInfoBase + 928, 0, 0, 0x6ULL }, // MSUB_DSP_MM |
| 4463 | { 2222, 4, 1, 4, 486, 0, 0, MipsOpInfoBase + 928, 0, 0, 0x6ULL }, // MSUB_DSP |
| 4464 | { 2221, 4, 1, 4, 213, 1, 0, MipsOpInfoBase + 936, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MSUB_D64 |
| 4465 | { 2220, 4, 1, 4, 395, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MSUB_D32_MM |
| 4466 | { 2219, 4, 1, 4, 213, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MSUB_D32 |
| 4467 | { 2218, 4, 1, 4, 205, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // MSUBV_W |
| 4468 | { 2217, 4, 1, 4, 205, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MSUBV_H |
| 4469 | { 2216, 4, 1, 4, 205, 0, 0, MipsOpInfoBase + 197, 0, 0, 0x6ULL }, // MSUBV_D |
| 4470 | { 2215, 4, 1, 4, 205, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // MSUBV_B |
| 4471 | { 2214, 2, 0, 4, 255, 2, 2, MipsOpInfoBase + 151, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MSUBU_MM |
| 4472 | { 2213, 4, 1, 4, 648, 0, 0, MipsOpInfoBase + 928, 0, 0, 0x6ULL }, // MSUBU_DSP_MM |
| 4473 | { 2212, 4, 1, 4, 485, 0, 0, MipsOpInfoBase + 928, 0, 0, 0x6ULL }, // MSUBU_DSP |
| 4474 | { 2211, 2, 0, 4, 243, 2, 2, MipsOpInfoBase + 151, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MSUBU |
| 4475 | { 2210, 4, 1, 4, 210, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // MSUBR_Q_W |
| 4476 | { 2209, 4, 1, 4, 210, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MSUBR_Q_H |
| 4477 | { 2208, 4, 1, 4, 420, 1, 0, MipsOpInfoBase + 924, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MSUBF_S_MMR6 |
| 4478 | { 2207, 4, 1, 4, 73, 1, 0, MipsOpInfoBase + 924, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MSUBF_S |
| 4479 | { 2206, 4, 1, 4, 420, 1, 0, MipsOpInfoBase + 920, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MSUBF_D_MMR6 |
| 4480 | { 2205, 4, 1, 4, 73, 1, 0, MipsOpInfoBase + 920, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MSUBF_D |
| 4481 | { 2204, 2, 0, 4, 243, 2, 2, MipsOpInfoBase + 151, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MSUB |
| 4482 | { 2203, 4, 1, 4, 387, 0, 0, MipsOpInfoBase + 1014, 0, 0, 0x4ULL }, // MOVZ_I_S_MM |
| 4483 | { 2202, 4, 1, 4, 222, 0, 0, MipsOpInfoBase + 1014, 0, 0, 0x4ULL }, // MOVZ_I_S |
| 4484 | { 2201, 4, 1, 4, 647, 0, 0, MipsOpInfoBase + 1006, 0, 0, 0x4ULL }, // MOVZ_I_MM |
| 4485 | { 2200, 4, 1, 4, 271, 0, 0, MipsOpInfoBase + 1010, 0, 0, 0x4ULL }, // MOVZ_I_I64 |
| 4486 | { 2199, 4, 1, 4, 102, 0, 0, MipsOpInfoBase + 1006, 0, 0, 0x4ULL }, // MOVZ_I_I |
| 4487 | { 2198, 4, 1, 4, 222, 0, 0, MipsOpInfoBase + 1002, 0, 0, 0x4ULL }, // MOVZ_I_D64 |
| 4488 | { 2197, 4, 1, 4, 387, 0, 0, MipsOpInfoBase + 998, 0, 0, 0x4ULL }, // MOVZ_I_D32_MM |
| 4489 | { 2196, 4, 1, 4, 222, 0, 0, MipsOpInfoBase + 998, 0, 0, 0x4ULL }, // MOVZ_I_D32 |
| 4490 | { 2195, 4, 1, 4, 384, 0, 0, MipsOpInfoBase + 994, 0, 0, 0x4ULL }, // MOVZ_I64_S |
| 4491 | { 2194, 4, 1, 4, 271, 0, 0, MipsOpInfoBase + 990, 0, 0, 0x4ULL }, // MOVZ_I64_I64 |
| 4492 | { 2193, 4, 1, 4, 271, 0, 0, MipsOpInfoBase + 986, 0, 0, 0x4ULL }, // MOVZ_I64_I |
| 4493 | { 2192, 4, 1, 4, 384, 0, 0, MipsOpInfoBase + 982, 0, 0, 0x4ULL }, // MOVZ_I64_D64 |
| 4494 | { 2191, 4, 1, 4, 387, 0, 0, MipsOpInfoBase + 978, 0, 0, 0x4ULL }, // MOVT_S_MM |
| 4495 | { 2190, 4, 1, 4, 127, 0, 0, MipsOpInfoBase + 978, 0, 0, 0x4ULL }, // MOVT_S |
| 4496 | { 2189, 4, 1, 4, 259, 0, 0, MipsOpInfoBase + 970, 0, 0, 0x4ULL }, // MOVT_I_MM |
| 4497 | { 2188, 4, 1, 4, 384, 0, 0, MipsOpInfoBase + 974, 0, 0, 0x4ULL }, // MOVT_I64 |
| 4498 | { 2187, 4, 1, 4, 217, 0, 0, MipsOpInfoBase + 970, 0, 0, 0x4ULL }, // MOVT_I |
| 4499 | { 2186, 4, 1, 4, 127, 0, 0, MipsOpInfoBase + 966, 0, 0, 0x4ULL }, // MOVT_D64 |
| 4500 | { 2185, 4, 1, 4, 387, 0, 0, MipsOpInfoBase + 962, 0, 0, 0x4ULL }, // MOVT_D32_MM |
| 4501 | { 2184, 4, 1, 4, 127, 0, 0, MipsOpInfoBase + 962, 0, 0, 0x4ULL }, // MOVT_D32 |
| 4502 | { 2183, 4, 1, 4, 387, 0, 0, MipsOpInfoBase + 1014, 0, 0, 0x4ULL }, // MOVN_I_S_MM |
| 4503 | { 2182, 4, 1, 4, 222, 0, 0, MipsOpInfoBase + 1014, 0, 0, 0x4ULL }, // MOVN_I_S |
| 4504 | { 2181, 4, 1, 4, 646, 0, 0, MipsOpInfoBase + 1006, 0, 0, 0x4ULL }, // MOVN_I_MM |
| 4505 | { 2180, 4, 1, 4, 271, 0, 0, MipsOpInfoBase + 1010, 0, 0, 0x4ULL }, // MOVN_I_I64 |
| 4506 | { 2179, 4, 1, 4, 102, 0, 0, MipsOpInfoBase + 1006, 0, 0, 0x4ULL }, // MOVN_I_I |
| 4507 | { 2178, 4, 1, 4, 222, 0, 0, MipsOpInfoBase + 1002, 0, 0, 0x4ULL }, // MOVN_I_D64 |
| 4508 | { 2177, 4, 1, 4, 387, 0, 0, MipsOpInfoBase + 998, 0, 0, 0x4ULL }, // MOVN_I_D32_MM |
| 4509 | { 2176, 4, 1, 4, 222, 0, 0, MipsOpInfoBase + 998, 0, 0, 0x4ULL }, // MOVN_I_D32 |
| 4510 | { 2175, 4, 1, 4, 384, 0, 0, MipsOpInfoBase + 994, 0, 0, 0x4ULL }, // MOVN_I64_S |
| 4511 | { 2174, 4, 1, 4, 271, 0, 0, MipsOpInfoBase + 990, 0, 0, 0x4ULL }, // MOVN_I64_I64 |
| 4512 | { 2173, 4, 1, 4, 271, 0, 0, MipsOpInfoBase + 986, 0, 0, 0x4ULL }, // MOVN_I64_I |
| 4513 | { 2172, 4, 1, 4, 384, 0, 0, MipsOpInfoBase + 982, 0, 0, 0x4ULL }, // MOVN_I64_D64 |
| 4514 | { 2171, 4, 1, 4, 387, 0, 0, MipsOpInfoBase + 978, 0, 0, 0x4ULL }, // MOVF_S_MM |
| 4515 | { 2170, 4, 1, 4, 127, 0, 0, MipsOpInfoBase + 978, 0, 0, 0x4ULL }, // MOVF_S |
| 4516 | { 2169, 4, 1, 4, 259, 0, 0, MipsOpInfoBase + 970, 0, 0, 0x4ULL }, // MOVF_I_MM |
| 4517 | { 2168, 4, 1, 4, 384, 0, 0, MipsOpInfoBase + 974, 0, 0, 0x4ULL }, // MOVF_I64 |
| 4518 | { 2167, 4, 1, 4, 217, 0, 0, MipsOpInfoBase + 970, 0, 0, 0x4ULL }, // MOVF_I |
| 4519 | { 2166, 4, 1, 4, 127, 0, 0, MipsOpInfoBase + 966, 0, 0, 0x4ULL }, // MOVF_D64 |
| 4520 | { 2165, 4, 1, 4, 387, 0, 0, MipsOpInfoBase + 962, 0, 0, 0x4ULL }, // MOVF_D32_MM |
| 4521 | { 2164, 4, 1, 4, 127, 0, 0, MipsOpInfoBase + 962, 0, 0, 0x4ULL }, // MOVF_D32 |
| 4522 | { 2163, 2, 1, 4, 133, 0, 0, MipsOpInfoBase + 960, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MOVE_V |
| 4523 | { 2162, 4, 2, 2, 645, 0, 0, MipsOpInfoBase + 956, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVEP_MMR6 |
| 4524 | { 2161, 4, 2, 2, 237, 0, 0, MipsOpInfoBase + 956, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVEP_MM |
| 4525 | { 2160, 2, 1, 2, 238, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVE16_MMR6 |
| 4526 | { 2159, 2, 1, 2, 237, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVE16_MM |
| 4527 | { 2158, 3, 1, 4, 10, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MOD_U_W |
| 4528 | { 2157, 3, 1, 4, 10, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MOD_U_H |
| 4529 | { 2156, 3, 1, 4, 10, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MOD_U_D |
| 4530 | { 2155, 3, 1, 4, 10, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MOD_U_B |
| 4531 | { 2154, 3, 1, 4, 10, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MOD_S_W |
| 4532 | { 2153, 3, 1, 4, 10, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MOD_S_H |
| 4533 | { 2152, 3, 1, 4, 10, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MOD_S_D |
| 4534 | { 2151, 3, 1, 4, 10, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MOD_S_B |
| 4535 | { 2150, 3, 1, 4, 262, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // MOD_MMR6 |
| 4536 | { 2149, 3, 1, 4, 262, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // MODU_MMR6 |
| 4537 | { 2148, 3, 1, 4, 251, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // MODU |
| 4538 | { 2147, 3, 1, 4, 644, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // MODSUB_MM |
| 4539 | { 2146, 3, 1, 4, 484, 0, 0, MipsOpInfoBase + 240, 0, 0, 0x6ULL }, // MODSUB |
| 4540 | { 2145, 3, 1, 4, 251, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // MOD |
| 4541 | { 2144, 3, 1, 4, 175, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MIN_U_W |
| 4542 | { 2143, 3, 1, 4, 175, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MIN_U_H |
| 4543 | { 2142, 3, 1, 4, 175, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MIN_U_D |
| 4544 | { 2141, 3, 1, 4, 175, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MIN_U_B |
| 4545 | { 2140, 3, 1, 4, 174, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MIN_S_W |
| 4546 | { 2139, 3, 1, 4, 415, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MIN_S_MMR6 |
| 4547 | { 2138, 3, 1, 4, 174, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MIN_S_H |
| 4548 | { 2137, 3, 1, 4, 174, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MIN_S_D |
| 4549 | { 2136, 3, 1, 4, 174, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MIN_S_B |
| 4550 | { 2135, 3, 1, 4, 21, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // MIN_S |
| 4551 | { 2134, 3, 1, 4, 415, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MIN_D_MMR6 |
| 4552 | { 2133, 3, 1, 4, 21, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // MIN_D |
| 4553 | { 2132, 3, 1, 4, 176, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MIN_A_W |
| 4554 | { 2131, 3, 1, 4, 176, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MIN_A_H |
| 4555 | { 2130, 3, 1, 4, 176, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MIN_A_D |
| 4556 | { 2129, 3, 1, 4, 176, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MIN_A_B |
| 4557 | { 2128, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // MINI_U_W |
| 4558 | { 2127, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MINI_U_H |
| 4559 | { 2126, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // MINI_U_D |
| 4560 | { 2125, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // MINI_U_B |
| 4561 | { 2124, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // MINI_S_W |
| 4562 | { 2123, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MINI_S_H |
| 4563 | { 2122, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // MINI_S_D |
| 4564 | { 2121, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // MINI_S_B |
| 4565 | { 2120, 3, 1, 4, 416, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MINA_S_MMR6 |
| 4566 | { 2119, 3, 1, 4, 21, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MINA_S |
| 4567 | { 2118, 3, 1, 4, 416, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MINA_D_MMR6 |
| 4568 | { 2117, 3, 1, 4, 21, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MINA_D |
| 4569 | { 2116, 5, 1, 4, 328, 0, 0, MipsOpInfoBase + 951, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFTR |
| 4570 | { 2115, 1, 1, 4, 259, 1, 0, MipsOpInfoBase + 196, 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFLO_MM |
| 4571 | { 2114, 2, 1, 4, 643, 0, 0, MipsOpInfoBase + 381, 0, 0, 0x6ULL }, // MFLO_DSP_MM |
| 4572 | { 2113, 2, 1, 4, 483, 0, 0, MipsOpInfoBase + 381, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // MFLO_DSP |
| 4573 | { 2112, 1, 1, 4, 268, 1, 0, MipsOpInfoBase + 320, 38, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFLO64 |
| 4574 | { 2111, 1, 1, 2, 259, 1, 0, MipsOpInfoBase + 196, 37, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // MFLO16_MM |
| 4575 | { 2110, 1, 1, 4, 99, 1, 0, MipsOpInfoBase + 196, 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFLO |
| 4576 | { 2109, 1, 1, 4, 259, 1, 0, MipsOpInfoBase + 196, 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFHI_MM |
| 4577 | { 2108, 2, 1, 4, 642, 0, 0, MipsOpInfoBase + 381, 0, 0, 0x6ULL }, // MFHI_DSP_MM |
| 4578 | { 2107, 2, 1, 4, 482, 0, 0, MipsOpInfoBase + 381, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // MFHI_DSP |
| 4579 | { 2106, 1, 1, 4, 268, 1, 0, MipsOpInfoBase + 320, 38, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFHI64 |
| 4580 | { 2105, 1, 1, 2, 259, 1, 0, MipsOpInfoBase + 196, 37, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // MFHI16_MM |
| 4581 | { 2104, 1, 1, 4, 99, 1, 0, MipsOpInfoBase + 196, 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFHI |
| 4582 | { 2103, 3, 1, 4, 332, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MFHGC0_MM |
| 4583 | { 2102, 3, 1, 4, 90, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHGC0 |
| 4584 | { 2101, 2, 1, 4, 319, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFHC2_MMR6 |
| 4585 | { 2100, 2, 1, 4, 394, 0, 0, MipsOpInfoBase + 944, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHC1_D64_MM |
| 4586 | { 2099, 2, 1, 4, 218, 0, 0, MipsOpInfoBase + 944, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHC1_D64 |
| 4587 | { 2098, 2, 1, 4, 394, 0, 0, MipsOpInfoBase + 949, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHC1_D32_MM |
| 4588 | { 2097, 2, 1, 4, 218, 0, 0, MipsOpInfoBase + 949, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHC1_D32 |
| 4589 | { 2096, 3, 1, 4, 319, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFHC0_MMR6 |
| 4590 | { 2095, 3, 1, 4, 332, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MFGC0_MM |
| 4591 | { 2094, 3, 1, 4, 90, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFGC0 |
| 4592 | { 2093, 2, 1, 4, 319, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFC2_MMR6 |
| 4593 | { 2092, 3, 1, 4, 89, 0, 0, MipsOpInfoBase + 946, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFC2 |
| 4594 | { 2091, 2, 1, 4, 414, 0, 0, MipsOpInfoBase + 386, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // MFC1_MMR6 |
| 4595 | { 2090, 2, 1, 4, 394, 0, 0, MipsOpInfoBase + 386, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // MFC1_MM |
| 4596 | { 2089, 2, 1, 4, 218, 0, 0, MipsOpInfoBase + 944, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFC1_D64 |
| 4597 | { 2088, 2, 1, 4, 218, 0, 0, MipsOpInfoBase + 386, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // MFC1 |
| 4598 | { 2087, 3, 1, 4, 319, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFC0_MMR6 |
| 4599 | { 2086, 3, 1, 4, 311, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFC0_MM |
| 4600 | { 2085, 3, 1, 4, 310, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFC0 |
| 4601 | { 2084, 3, 1, 4, 175, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MAX_U_W |
| 4602 | { 2083, 3, 1, 4, 175, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MAX_U_H |
| 4603 | { 2082, 3, 1, 4, 175, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MAX_U_D |
| 4604 | { 2081, 3, 1, 4, 175, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MAX_U_B |
| 4605 | { 2080, 3, 1, 4, 174, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MAX_S_W |
| 4606 | { 2079, 3, 1, 4, 415, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAX_S_MMR6 |
| 4607 | { 2078, 3, 1, 4, 174, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MAX_S_H |
| 4608 | { 2077, 3, 1, 4, 174, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MAX_S_D |
| 4609 | { 2076, 3, 1, 4, 174, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MAX_S_B |
| 4610 | { 2075, 3, 1, 4, 21, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // MAX_S |
| 4611 | { 2074, 3, 1, 4, 415, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAX_D_MMR6 |
| 4612 | { 2073, 3, 1, 4, 21, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // MAX_D |
| 4613 | { 2072, 3, 1, 4, 176, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // MAX_A_W |
| 4614 | { 2071, 3, 1, 4, 176, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // MAX_A_H |
| 4615 | { 2070, 3, 1, 4, 176, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // MAX_A_D |
| 4616 | { 2069, 3, 1, 4, 176, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // MAX_A_B |
| 4617 | { 2068, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // MAXI_U_W |
| 4618 | { 2067, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MAXI_U_H |
| 4619 | { 2066, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // MAXI_U_D |
| 4620 | { 2065, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // MAXI_U_B |
| 4621 | { 2064, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // MAXI_S_W |
| 4622 | { 2063, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MAXI_S_H |
| 4623 | { 2062, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // MAXI_S_D |
| 4624 | { 2061, 3, 1, 4, 22, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // MAXI_S_B |
| 4625 | { 2060, 3, 1, 4, 416, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAXA_S_MMR6 |
| 4626 | { 2059, 3, 1, 4, 21, 0, 0, MipsOpInfoBase + 762, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAXA_S |
| 4627 | { 2058, 3, 1, 4, 416, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAXA_D_MMR6 |
| 4628 | { 2057, 3, 1, 4, 21, 0, 0, MipsOpInfoBase + 539, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAXA_D |
| 4629 | { 2056, 4, 1, 4, 641, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_S_W_PHR_MM |
| 4630 | { 2055, 4, 1, 4, 481, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_S_W_PHR |
| 4631 | { 2054, 4, 1, 4, 640, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_S_W_PHL_MM |
| 4632 | { 2053, 4, 1, 4, 480, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_S_W_PHL |
| 4633 | { 2052, 4, 1, 4, 639, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_SA_W_PHR_MM |
| 4634 | { 2051, 4, 1, 4, 479, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_SA_W_PHR |
| 4635 | { 2050, 4, 1, 4, 638, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_SA_W_PHL_MM |
| 4636 | { 2049, 4, 1, 4, 478, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_SA_W_PHL |
| 4637 | { 2048, 4, 1, 4, 388, 1, 0, MipsOpInfoBase + 940, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MADD_S_MM |
| 4638 | { 2047, 4, 1, 4, 380, 1, 0, MipsOpInfoBase + 940, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MADD_S |
| 4639 | { 2046, 4, 1, 4, 209, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // MADD_Q_W |
| 4640 | { 2045, 4, 1, 4, 209, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MADD_Q_H |
| 4641 | { 2044, 2, 0, 4, 255, 2, 2, MipsOpInfoBase + 151, 33, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MADD_MM |
| 4642 | { 2043, 4, 1, 4, 637, 0, 0, MipsOpInfoBase + 928, 0, 0, 0x6ULL }, // MADD_DSP_MM |
| 4643 | { 2042, 4, 1, 4, 477, 0, 0, MipsOpInfoBase + 928, 0, 0, 0x6ULL }, // MADD_DSP |
| 4644 | { 2041, 4, 1, 4, 213, 1, 0, MipsOpInfoBase + 936, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MADD_D64 |
| 4645 | { 2040, 4, 1, 4, 388, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MADD_D32_MM |
| 4646 | { 2039, 4, 1, 4, 213, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MADD_D32 |
| 4647 | { 2038, 4, 1, 4, 206, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // MADDV_W |
| 4648 | { 2037, 4, 1, 4, 206, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MADDV_H |
| 4649 | { 2036, 4, 1, 4, 206, 0, 0, MipsOpInfoBase + 197, 0, 0, 0x6ULL }, // MADDV_D |
| 4650 | { 2035, 4, 1, 4, 206, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // MADDV_B |
| 4651 | { 2034, 2, 0, 4, 255, 2, 2, MipsOpInfoBase + 151, 33, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MADDU_MM |
| 4652 | { 2033, 4, 1, 4, 636, 0, 0, MipsOpInfoBase + 928, 0, 0, 0x6ULL }, // MADDU_DSP_MM |
| 4653 | { 2032, 4, 1, 4, 476, 0, 0, MipsOpInfoBase + 928, 0, 0, 0x6ULL }, // MADDU_DSP |
| 4654 | { 2031, 2, 0, 4, 243, 2, 2, MipsOpInfoBase + 151, 33, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MADDU |
| 4655 | { 2030, 4, 1, 4, 208, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // MADDR_Q_W |
| 4656 | { 2029, 4, 1, 4, 208, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MADDR_Q_H |
| 4657 | { 2028, 4, 1, 4, 420, 1, 0, MipsOpInfoBase + 924, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MADDF_S_MMR6 |
| 4658 | { 2027, 4, 1, 4, 73, 1, 0, MipsOpInfoBase + 924, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MADDF_S |
| 4659 | { 2026, 4, 1, 4, 420, 1, 0, MipsOpInfoBase + 920, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MADDF_D_MMR6 |
| 4660 | { 2025, 4, 1, 4, 73, 1, 0, MipsOpInfoBase + 920, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MADDF_D |
| 4661 | { 2024, 2, 0, 4, 243, 2, 2, MipsOpInfoBase + 151, 33, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MADD |
| 4662 | { 2023, 3, 1, 4, 352, 0, 0, MipsOpInfoBase + 576, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LwRxSpImmX16 |
| 4663 | { 2022, 3, 1, 4, 352, 0, 0, MipsOpInfoBase + 917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LwRxRyOffMemX16 |
| 4664 | { 2021, 2, 1, 4, 352, 0, 0, MipsOpInfoBase + 571, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LwRxPcTcpX16 |
| 4665 | { 2020, 2, 1, 2, 352, 0, 0, MipsOpInfoBase + 571, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LwRxPcTcp16 |
| 4666 | { 2019, 2, 1, 4, 235, 0, 0, MipsOpInfoBase + 571, 0, 0, 0x0ULL }, // LiRxImmX16 |
| 4667 | { 2018, 2, 1, 4, 235, 0, 0, MipsOpInfoBase + 571, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LiRxImmAlignX16 |
| 4668 | { 2017, 2, 1, 2, 235, 0, 0, MipsOpInfoBase + 571, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LiRxImm16 |
| 4669 | { 2016, 3, 1, 4, 352, 0, 0, MipsOpInfoBase + 917, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LhuRxRyOffMemX16 |
| 4670 | { 2015, 3, 1, 4, 352, 0, 0, MipsOpInfoBase + 917, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LhRxRyOffMemX16 |
| 4671 | { 2014, 3, 1, 4, 352, 0, 0, MipsOpInfoBase + 917, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LbuRxRyOffMemX16 |
| 4672 | { 2013, 3, 1, 4, 352, 0, 0, MipsOpInfoBase + 917, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LbRxRyOffMemX16 |
| 4673 | { 2012, 3, 1, 4, 365, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWu |
| 4674 | { 2011, 3, 1, 4, 360, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL }, // LW_MMR6 |
| 4675 | { 2010, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LW_MM |
| 4676 | { 2009, 3, 1, 4, 635, 0, 0, MipsOpInfoBase + 840, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LWX_MM |
| 4677 | { 2008, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 840, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // LWXS_MM |
| 4678 | { 2007, 3, 1, 4, 404, 0, 0, MipsOpInfoBase + 914, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWXC1_MM |
| 4679 | { 2006, 3, 1, 4, 224, 0, 0, MipsOpInfoBase + 914, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWXC1 |
| 4680 | { 2005, 3, 1, 4, 475, 0, 0, MipsOpInfoBase + 840, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LWX |
| 4681 | { 2004, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWU_MM |
| 4682 | { 2003, 2, 1, 4, 372, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWUPC |
| 4683 | { 2002, 3, 1, 2, 354, 0, 0, MipsOpInfoBase + 911, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWSP_MM |
| 4684 | { 2001, 4, 1, 4, 354, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWR_MM |
| 4685 | { 2000, 4, 1, 4, 348, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWRE_MM |
| 4686 | { 1999, 4, 1, 4, 93, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWRE |
| 4687 | { 1998, 4, 1, 4, 367, 0, 0, MipsOpInfoBase + 863, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWR64 |
| 4688 | { 1997, 4, 1, 4, 335, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWR |
| 4689 | { 1996, 4, 2, 4, 354, 0, 0, MipsOpInfoBase + 907, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWP_MM |
| 4690 | { 1995, 2, 1, 4, 360, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWPC_MMR6 |
| 4691 | { 1994, 2, 1, 4, 91, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWPC |
| 4692 | { 1993, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 360, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWM32_MM |
| 4693 | { 1992, 3, 1, 2, 360, 0, 0, MipsOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWM16_MMR6 |
| 4694 | { 1991, 3, 1, 2, 354, 0, 0, MipsOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWM16_MM |
| 4695 | { 1990, 4, 1, 4, 354, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWL_MM |
| 4696 | { 1989, 4, 1, 4, 348, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWLE_MM |
| 4697 | { 1988, 4, 1, 4, 93, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWLE |
| 4698 | { 1987, 4, 1, 4, 367, 0, 0, MipsOpInfoBase + 863, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWL64 |
| 4699 | { 1986, 4, 1, 4, 335, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWL |
| 4700 | { 1985, 3, 1, 2, 354, 0, 0, MipsOpInfoBase + 897, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWGP_MM |
| 4701 | { 1984, 3, 1, 4, 348, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWE_MM |
| 4702 | { 1983, 3, 1, 4, 92, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWE |
| 4703 | { 1982, 3, 1, 4, 590, 0, 0, MipsOpInfoBase + 894, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWDSP_MM |
| 4704 | { 1981, 3, 1, 4, 427, 0, 0, MipsOpInfoBase + 894, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWDSP |
| 4705 | { 1980, 3, 1, 4, 334, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWC3 |
| 4706 | { 1979, 3, 1, 4, 341, 0, 0, MipsOpInfoBase + 846, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWC2_R6 |
| 4707 | { 1978, 3, 1, 4, 360, 0, 0, MipsOpInfoBase + 849, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LWC2_MMR6 |
| 4708 | { 1977, 3, 1, 4, 334, 0, 0, MipsOpInfoBase + 846, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWC2 |
| 4709 | { 1976, 3, 1, 4, 404, 0, 0, MipsOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWC1_MM |
| 4710 | { 1975, 3, 1, 4, 223, 0, 0, MipsOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWC1 |
| 4711 | { 1974, 3, 1, 4, 365, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LW64 |
| 4712 | { 1973, 3, 1, 2, 354, 0, 0, MipsOpInfoBase + 837, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL }, // LW16_MM |
| 4713 | { 1972, 3, 1, 4, 333, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LW |
| 4714 | { 1971, 2, 1, 4, 237, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // LUi_MM |
| 4715 | { 1970, 2, 1, 4, 240, 0, 0, MipsOpInfoBase + 365, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // LUi64 |
| 4716 | { 1969, 2, 1, 4, 79, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // LUi |
| 4717 | { 1968, 3, 1, 4, 404, 0, 0, MipsOpInfoBase + 870, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // LUXC1_MM |
| 4718 | { 1967, 3, 1, 4, 224, 0, 0, MipsOpInfoBase + 870, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // LUXC164 |
| 4719 | { 1966, 3, 1, 4, 224, 0, 0, MipsOpInfoBase + 867, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // LUXC1 |
| 4720 | { 1965, 2, 1, 4, 238, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // LUI_MMR6 |
| 4721 | { 1964, 4, 1, 4, 234, 0, 0, MipsOpInfoBase + 560, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LSA_R6 |
| 4722 | { 1963, 4, 1, 4, 238, 0, 0, MipsOpInfoBase + 560, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LSA_MMR6 |
| 4723 | { 1962, 4, 1, 4, 111, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // LSA |
| 4724 | { 1961, 3, 1, 4, 341, 0, 0, MipsOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LL_R6 |
| 4725 | { 1960, 3, 1, 4, 360, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LL_MMR6 |
| 4726 | { 1959, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LL_MM |
| 4727 | { 1958, 3, 1, 4, 348, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LLE_MM |
| 4728 | { 1957, 3, 1, 4, 92, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LLE |
| 4729 | { 1956, 3, 1, 4, 3, 0, 0, MipsOpInfoBase + 888, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LLD_R6 |
| 4730 | { 1955, 3, 1, 4, 366, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LLD |
| 4731 | { 1954, 3, 1, 4, 3, 0, 0, MipsOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LL64_R6 |
| 4732 | { 1953, 3, 1, 4, 366, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LL64 |
| 4733 | { 1952, 3, 1, 4, 334, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LL |
| 4734 | { 1951, 2, 1, 2, 238, 0, 0, MipsOpInfoBase + 528, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // LI16_MMR6 |
| 4735 | { 1950, 2, 1, 2, 237, 0, 0, MipsOpInfoBase + 528, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // LI16_MM |
| 4736 | { 1949, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LHu_MM |
| 4737 | { 1948, 3, 1, 4, 348, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LHuE_MM |
| 4738 | { 1947, 3, 1, 4, 92, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LHuE |
| 4739 | { 1946, 3, 1, 4, 365, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LHu64 |
| 4740 | { 1945, 3, 1, 4, 333, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LHu |
| 4741 | { 1944, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LH_MM |
| 4742 | { 1943, 3, 1, 4, 634, 0, 0, MipsOpInfoBase + 840, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LHX_MM |
| 4743 | { 1942, 3, 1, 4, 474, 0, 0, MipsOpInfoBase + 840, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LHX |
| 4744 | { 1941, 3, 1, 2, 354, 0, 0, MipsOpInfoBase + 837, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LHU16_MM |
| 4745 | { 1940, 3, 1, 4, 348, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LHE_MM |
| 4746 | { 1939, 3, 1, 4, 92, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LHE |
| 4747 | { 1938, 3, 1, 4, 365, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LH64 |
| 4748 | { 1937, 3, 1, 4, 333, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LH |
| 4749 | { 1936, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 321, 0, 0, 0x2ULL }, // LEA_ADDiu_MM |
| 4750 | { 1935, 3, 1, 4, 241, 0, 0, MipsOpInfoBase + 367, 0, 0, 0x2ULL }, // LEA_ADDiu64 |
| 4751 | { 1934, 3, 1, 4, 231, 0, 0, MipsOpInfoBase + 321, 0, 0, 0x2ULL }, // LEA_ADDiu |
| 4752 | { 1933, 3, 1, 4, 42, 0, 0, MipsOpInfoBase + 882, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LD_W |
| 4753 | { 1932, 3, 1, 4, 42, 0, 0, MipsOpInfoBase + 879, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LD_H |
| 4754 | { 1931, 3, 1, 4, 42, 0, 0, MipsOpInfoBase + 876, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LD_D |
| 4755 | { 1930, 3, 1, 4, 42, 0, 0, MipsOpInfoBase + 873, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LD_B |
| 4756 | { 1929, 3, 1, 4, 224, 0, 0, MipsOpInfoBase + 870, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDXC164 |
| 4757 | { 1928, 3, 1, 4, 224, 0, 0, MipsOpInfoBase + 867, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDXC1 |
| 4758 | { 1927, 4, 1, 4, 368, 0, 0, MipsOpInfoBase + 863, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LDR |
| 4759 | { 1926, 2, 1, 4, 372, 0, 0, MipsOpInfoBase + 365, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LDPC |
| 4760 | { 1925, 4, 1, 4, 368, 0, 0, MipsOpInfoBase + 863, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LDL |
| 4761 | { 1924, 2, 1, 4, 43, 0, 0, MipsOpInfoBase + 861, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // LDI_W |
| 4762 | { 1923, 2, 1, 4, 43, 0, 0, MipsOpInfoBase + 859, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // LDI_H |
| 4763 | { 1922, 2, 1, 4, 43, 0, 0, MipsOpInfoBase + 857, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // LDI_D |
| 4764 | { 1921, 2, 1, 4, 43, 0, 0, MipsOpInfoBase + 855, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // LDI_B |
| 4765 | { 1920, 3, 1, 4, 333, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC3 |
| 4766 | { 1919, 3, 1, 4, 341, 0, 0, MipsOpInfoBase + 846, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LDC2_R6 |
| 4767 | { 1918, 3, 1, 4, 360, 0, 0, MipsOpInfoBase + 849, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LDC2_MMR6 |
| 4768 | { 1917, 3, 1, 4, 334, 0, 0, MipsOpInfoBase + 846, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC2 |
| 4769 | { 1916, 3, 1, 4, 404, 0, 0, MipsOpInfoBase + 843, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC1_MM_D64 |
| 4770 | { 1915, 3, 1, 4, 404, 0, 0, MipsOpInfoBase + 495, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC1_MM_D32 |
| 4771 | { 1914, 3, 1, 4, 424, 0, 0, MipsOpInfoBase + 843, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LDC1_D64_MMR6 |
| 4772 | { 1913, 3, 1, 4, 223, 0, 0, MipsOpInfoBase + 843, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC164 |
| 4773 | { 1912, 3, 1, 4, 223, 0, 0, MipsOpInfoBase + 495, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC1 |
| 4774 | { 1911, 3, 1, 4, 365, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LD |
| 4775 | { 1910, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LBu_MM |
| 4776 | { 1909, 3, 1, 4, 348, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LBuE_MM |
| 4777 | { 1908, 3, 1, 4, 92, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LBuE |
| 4778 | { 1907, 3, 1, 4, 365, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LBu64 |
| 4779 | { 1906, 3, 1, 4, 333, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LBu |
| 4780 | { 1905, 3, 1, 4, 360, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LB_MMR6 |
| 4781 | { 1904, 3, 1, 4, 354, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LB_MM |
| 4782 | { 1903, 3, 1, 4, 360, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LBU_MMR6 |
| 4783 | { 1902, 3, 1, 4, 633, 0, 0, MipsOpInfoBase + 840, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LBUX_MM |
| 4784 | { 1901, 3, 1, 4, 473, 0, 0, MipsOpInfoBase + 840, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LBUX |
| 4785 | { 1900, 3, 1, 2, 354, 0, 0, MipsOpInfoBase + 837, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LBU16_MM |
| 4786 | { 1899, 3, 1, 4, 348, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LBE_MM |
| 4787 | { 1898, 3, 1, 4, 92, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LBE |
| 4788 | { 1897, 3, 1, 4, 365, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LB64 |
| 4789 | { 1896, 3, 1, 4, 333, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LB |
| 4790 | { 1895, 1, 0, 2, 290, 0, 1, MipsOpInfoBase + 836, 3, 0|(1ULL<<MCID::Call), 0x0ULL }, // JumpLinkReg16 |
| 4791 | { 1894, 1, 0, 2, 289, 0, 0, MipsOpInfoBase + 836, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // JrcRx16 |
| 4792 | { 1893, 0, 0, 2, 289, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JrcRa16 |
| 4793 | { 1892, 0, 0, 2, 289, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JrRa16 |
| 4794 | { 1891, 1, 0, 6, 290, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JalB16 |
| 4795 | { 1890, 1, 0, 6, 290, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::Call), 0x0ULL }, // Jal16 |
| 4796 | { 1889, 1, 0, 4, 293, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // J_MM |
| 4797 | { 1888, 1, 0, 4, 293, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JR_MM |
| 4798 | { 1887, 1, 0, 4, 285, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JR_HB_R6 |
| 4799 | { 1886, 1, 0, 4, 276, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JR_HB_MM |
| 4800 | { 1885, 1, 0, 4, 308, 0, 0, MipsOpInfoBase + 320, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JR_HB64_R6 |
| 4801 | { 1884, 1, 0, 4, 303, 0, 0, MipsOpInfoBase + 320, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JR_HB64 |
| 4802 | { 1883, 1, 0, 4, 274, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JR_HB |
| 4803 | { 1882, 1, 0, 2, 297, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JRCADDIUSP_MMR6 |
| 4804 | { 1881, 1, 0, 2, 297, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JRC16_MMR6 |
| 4805 | { 1880, 1, 0, 2, 297, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JRC16_MM |
| 4806 | { 1879, 1, 0, 2, 297, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JRADDIUSP |
| 4807 | { 1878, 1, 0, 4, 301, 0, 0, MipsOpInfoBase + 320, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JR64 |
| 4808 | { 1877, 1, 0, 2, 293, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JR16_MM |
| 4809 | { 1876, 1, 0, 4, 274, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JR |
| 4810 | { 1875, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 370, 2, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // JIC_MMR6 |
| 4811 | { 1874, 2, 0, 4, 305, 0, 1, MipsOpInfoBase + 365, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JIC64 |
| 4812 | { 1873, 2, 0, 4, 285, 0, 1, MipsOpInfoBase + 370, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JIC |
| 4813 | { 1872, 2, 0, 4, 298, 0, 1, MipsOpInfoBase + 370, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // JIALC_MMR6 |
| 4814 | { 1871, 2, 0, 4, 307, 0, 1, MipsOpInfoBase + 365, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JIALC64 |
| 4815 | { 1870, 2, 0, 4, 284, 0, 1, MipsOpInfoBase + 370, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JIALC |
| 4816 | { 1869, 1, 0, 4, 294, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // JAL_MM |
| 4817 | { 1868, 1, 0, 4, 294, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // JALX_MM |
| 4818 | { 1867, 1, 0, 4, 86, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // JALX |
| 4819 | { 1866, 1, 0, 4, 294, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // JALS_MM |
| 4820 | { 1865, 2, 1, 4, 294, 0, 1, MipsOpInfoBase + 151, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JALR_MM |
| 4821 | { 1864, 2, 1, 4, 281, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JALR_HB_MM |
| 4822 | { 1863, 2, 1, 4, 302, 0, 0, MipsOpInfoBase + 388, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JALR_HB64 |
| 4823 | { 1862, 2, 1, 4, 85, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JALR_HB |
| 4824 | { 1861, 2, 1, 4, 294, 0, 1, MipsOpInfoBase + 151, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // JALRS_MM |
| 4825 | { 1860, 1, 0, 2, 294, 0, 1, MipsOpInfoBase + 196, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JALRS16_MM |
| 4826 | { 1859, 2, 1, 4, 298, 0, 1, MipsOpInfoBase + 151, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // JALRC_MMR6 |
| 4827 | { 1858, 2, 1, 4, 298, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // JALRC_HB_MMR6 |
| 4828 | { 1857, 1, 0, 2, 298, 0, 1, MipsOpInfoBase + 196, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // JALRC16_MMR6 |
| 4829 | { 1856, 2, 1, 4, 302, 0, 1, MipsOpInfoBase + 388, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JALR64 |
| 4830 | { 1855, 1, 0, 2, 294, 0, 1, MipsOpInfoBase + 196, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // JALR16_MM |
| 4831 | { 1854, 2, 1, 4, 85, 0, 1, MipsOpInfoBase + 151, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JALR |
| 4832 | { 1853, 1, 0, 4, 85, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // JAL |
| 4833 | { 1852, 1, 0, 4, 273, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // J |
| 4834 | { 1851, 5, 1, 4, 238, 0, 0, MipsOpInfoBase + 792, 0, 0, 0x1ULL }, // INS_MMR6 |
| 4835 | { 1850, 5, 1, 4, 237, 0, 0, MipsOpInfoBase + 792, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // INS_MM |
| 4836 | { 1849, 3, 1, 4, 632, 2, 0, MipsOpInfoBase + 813, 31, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // INSV_MM |
| 4837 | { 1848, 5, 1, 4, 63, 0, 0, MipsOpInfoBase + 831, 0, 0, 0x6ULL }, // INSVE_W |
| 4838 | { 1847, 5, 1, 4, 63, 0, 0, MipsOpInfoBase + 826, 0, 0, 0x6ULL }, // INSVE_H |
| 4839 | { 1846, 5, 1, 4, 63, 0, 0, MipsOpInfoBase + 821, 0, 0, 0x6ULL }, // INSVE_D |
| 4840 | { 1845, 5, 1, 4, 63, 0, 0, MipsOpInfoBase + 816, 0, 0, 0x6ULL }, // INSVE_B |
| 4841 | { 1844, 3, 1, 4, 437, 2, 0, MipsOpInfoBase + 813, 31, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // INSV |
| 4842 | { 1843, 4, 1, 4, 116, 0, 0, MipsOpInfoBase + 809, 0, 0, 0x6ULL }, // INSERT_W |
| 4843 | { 1842, 4, 1, 4, 116, 0, 0, MipsOpInfoBase + 805, 0, 0, 0x6ULL }, // INSERT_H |
| 4844 | { 1841, 4, 1, 4, 116, 0, 0, MipsOpInfoBase + 801, 0, 0, 0x6ULL }, // INSERT_D |
| 4845 | { 1840, 4, 1, 4, 116, 0, 0, MipsOpInfoBase + 797, 0, 0, 0x6ULL }, // INSERT_B |
| 4846 | { 1839, 5, 1, 4, 110, 0, 0, MipsOpInfoBase + 792, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // INS |
| 4847 | { 1838, 3, 1, 4, 33, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // ILVR_W |
| 4848 | { 1837, 3, 1, 4, 33, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // ILVR_H |
| 4849 | { 1836, 3, 1, 4, 33, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // ILVR_D |
| 4850 | { 1835, 3, 1, 4, 33, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // ILVR_B |
| 4851 | { 1834, 3, 1, 4, 32, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // ILVOD_W |
| 4852 | { 1833, 3, 1, 4, 32, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // ILVOD_H |
| 4853 | { 1832, 3, 1, 4, 32, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // ILVOD_D |
| 4854 | { 1831, 3, 1, 4, 32, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // ILVOD_B |
| 4855 | { 1830, 3, 1, 4, 31, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // ILVL_W |
| 4856 | { 1829, 3, 1, 4, 31, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // ILVL_H |
| 4857 | { 1828, 3, 1, 4, 31, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // ILVL_D |
| 4858 | { 1827, 3, 1, 4, 31, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // ILVL_B |
| 4859 | { 1826, 3, 1, 4, 30, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // ILVEV_W |
| 4860 | { 1825, 3, 1, 4, 30, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // ILVEV_H |
| 4861 | { 1824, 3, 1, 4, 30, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // ILVEV_D |
| 4862 | { 1823, 3, 1, 4, 30, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // ILVEV_B |
| 4863 | { 1822, 1, 0, 4, 332, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // HYPCALL_MM |
| 4864 | { 1821, 1, 0, 4, 90, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // HYPCALL |
| 4865 | { 1820, 3, 1, 4, 173, 0, 0, MipsOpInfoBase + 727, 0, 0, 0x6ULL }, // HSUB_U_W |
| 4866 | { 1819, 3, 1, 4, 173, 0, 0, MipsOpInfoBase + 724, 0, 0, 0x6ULL }, // HSUB_U_H |
| 4867 | { 1818, 3, 1, 4, 173, 0, 0, MipsOpInfoBase + 721, 0, 0, 0x6ULL }, // HSUB_U_D |
| 4868 | { 1817, 3, 1, 4, 173, 0, 0, MipsOpInfoBase + 727, 0, 0, 0x6ULL }, // HSUB_S_W |
| 4869 | { 1816, 3, 1, 4, 173, 0, 0, MipsOpInfoBase + 724, 0, 0, 0x6ULL }, // HSUB_S_H |
| 4870 | { 1815, 3, 1, 4, 173, 0, 0, MipsOpInfoBase + 721, 0, 0, 0x6ULL }, // HSUB_S_D |
| 4871 | { 1814, 3, 1, 4, 172, 0, 0, MipsOpInfoBase + 727, 0, 0, 0x6ULL }, // HADD_U_W |
| 4872 | { 1813, 3, 1, 4, 172, 0, 0, MipsOpInfoBase + 724, 0, 0, 0x6ULL }, // HADD_U_H |
| 4873 | { 1812, 3, 1, 4, 172, 0, 0, MipsOpInfoBase + 721, 0, 0, 0x6ULL }, // HADD_U_D |
| 4874 | { 1811, 3, 1, 4, 172, 0, 0, MipsOpInfoBase + 727, 0, 0, 0x6ULL }, // HADD_S_W |
| 4875 | { 1810, 3, 1, 4, 172, 0, 0, MipsOpInfoBase + 724, 0, 0, 0x6ULL }, // HADD_S_H |
| 4876 | { 1809, 3, 1, 4, 172, 0, 0, MipsOpInfoBase + 721, 0, 0, 0x6ULL }, // HADD_S_D |
| 4877 | { 1808, 2, 0, 4, 359, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // GINVT_MMR6 |
| 4878 | { 1807, 2, 0, 4, 345, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // GINVT |
| 4879 | { 1806, 1, 0, 4, 359, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // GINVI_MMR6 |
| 4880 | { 1805, 1, 0, 4, 345, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // GINVI |
| 4881 | { 1804, 2, 1, 4, 161, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FTRUNC_U_W |
| 4882 | { 1803, 2, 1, 4, 161, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FTRUNC_U_D |
| 4883 | { 1802, 2, 1, 4, 161, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FTRUNC_S_W |
| 4884 | { 1801, 2, 1, 4, 161, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FTRUNC_S_D |
| 4885 | { 1800, 3, 1, 4, 160, 0, 0, MipsOpInfoBase + 777, 0, 0, 0x6ULL }, // FTQ_W |
| 4886 | { 1799, 3, 1, 4, 160, 0, 0, MipsOpInfoBase + 774, 0, 0, 0x6ULL }, // FTQ_H |
| 4887 | { 1798, 2, 1, 4, 158, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FTINT_U_W |
| 4888 | { 1797, 2, 1, 4, 158, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FTINT_U_D |
| 4889 | { 1796, 2, 1, 4, 158, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FTINT_S_W |
| 4890 | { 1795, 2, 1, 4, 158, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FTINT_S_D |
| 4891 | { 1794, 3, 1, 4, 144, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSUN_W |
| 4892 | { 1793, 3, 1, 4, 144, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSUN_D |
| 4893 | { 1792, 3, 1, 4, 143, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSUNE_W |
| 4894 | { 1791, 3, 1, 4, 143, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSUNE_D |
| 4895 | { 1790, 3, 1, 4, 142, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSULT_W |
| 4896 | { 1789, 3, 1, 4, 142, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSULT_D |
| 4897 | { 1788, 3, 1, 4, 141, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSULE_W |
| 4898 | { 1787, 3, 1, 4, 141, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSULE_D |
| 4899 | { 1786, 3, 1, 4, 140, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSUEQ_W |
| 4900 | { 1785, 3, 1, 4, 140, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSUEQ_D |
| 4901 | { 1784, 3, 1, 4, 69, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSUB_W |
| 4902 | { 1783, 3, 1, 4, 421, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // FSUB_S_MMR6 |
| 4903 | { 1782, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_S_MM |
| 4904 | { 1781, 3, 1, 4, 12, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_S |
| 4905 | { 1780, 3, 1, 4, 183, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // FSUB_PS64 |
| 4906 | { 1779, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_D64_MM |
| 4907 | { 1778, 3, 1, 4, 12, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_D64 |
| 4908 | { 1777, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 759, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_D32_MM |
| 4909 | { 1776, 3, 1, 4, 12, 1, 0, MipsOpInfoBase + 759, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_D32 |
| 4910 | { 1775, 3, 1, 4, 69, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSUB_D |
| 4911 | { 1774, 2, 1, 4, 200, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FSQRT_W |
| 4912 | { 1773, 2, 1, 4, 398, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_S_MM |
| 4913 | { 1772, 2, 1, 4, 193, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_S |
| 4914 | { 1771, 2, 1, 4, 399, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_D64_MM |
| 4915 | { 1770, 2, 1, 4, 194, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_D64 |
| 4916 | { 1769, 2, 1, 4, 399, 1, 0, MipsOpInfoBase + 757, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_D32_MM |
| 4917 | { 1768, 2, 1, 4, 194, 1, 0, MipsOpInfoBase + 757, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_D32 |
| 4918 | { 1767, 2, 1, 4, 14, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FSQRT_D |
| 4919 | { 1766, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSOR_W |
| 4920 | { 1765, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSOR_D |
| 4921 | { 1764, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSNE_W |
| 4922 | { 1763, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSNE_D |
| 4923 | { 1762, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSLT_W |
| 4924 | { 1761, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSLT_D |
| 4925 | { 1760, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSLE_W |
| 4926 | { 1759, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSLE_D |
| 4927 | { 1758, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSEQ_W |
| 4928 | { 1757, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSEQ_D |
| 4929 | { 1756, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FSAF_W |
| 4930 | { 1755, 3, 1, 4, 139, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FSAF_D |
| 4931 | { 1754, 2, 1, 4, 196, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FRSQRT_W |
| 4932 | { 1753, 2, 1, 4, 196, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FRSQRT_D |
| 4933 | { 1752, 2, 1, 4, 159, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FRINT_W |
| 4934 | { 1751, 2, 1, 4, 159, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FRINT_D |
| 4935 | { 1750, 2, 1, 4, 195, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FRCP_W |
| 4936 | { 1749, 2, 1, 4, 195, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FRCP_D |
| 4937 | { 1748, 3, 2, 4, 330, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // FORK |
| 4938 | { 1747, 2, 1, 4, 405, 0, 0, MipsOpInfoBase + 634, 0, 0, 0x4ULL }, // FNEG_S_MMR6 |
| 4939 | { 1746, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 634, 0, 0, 0x4ULL }, // FNEG_S_MM |
| 4940 | { 1745, 2, 1, 4, 379, 0, 0, MipsOpInfoBase + 634, 0, 0, 0x4ULL }, // FNEG_S |
| 4941 | { 1744, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 626, 0, 0, 0x4ULL }, // FNEG_D64_MM |
| 4942 | { 1743, 2, 1, 4, 379, 0, 0, MipsOpInfoBase + 626, 0, 0, 0x4ULL }, // FNEG_D64 |
| 4943 | { 1742, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 757, 0, 0, 0x4ULL }, // FNEG_D32_MM |
| 4944 | { 1741, 2, 1, 4, 379, 0, 0, MipsOpInfoBase + 757, 0, 0, 0x4ULL }, // FNEG_D32 |
| 4945 | { 1740, 3, 1, 4, 201, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FMUL_W |
| 4946 | { 1739, 3, 1, 4, 421, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x6ULL }, // FMUL_S_MMR6 |
| 4947 | { 1738, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_S_MM |
| 4948 | { 1737, 3, 1, 4, 381, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_S |
| 4949 | { 1736, 3, 1, 4, 183, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // FMUL_PS64 |
| 4950 | { 1735, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_D64_MM |
| 4951 | { 1734, 3, 1, 4, 13, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_D64 |
| 4952 | { 1733, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 759, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_D32_MM |
| 4953 | { 1732, 3, 1, 4, 13, 1, 0, MipsOpInfoBase + 759, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_D32 |
| 4954 | { 1731, 3, 1, 4, 201, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FMUL_D |
| 4955 | { 1730, 4, 1, 4, 72, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // FMSUB_W |
| 4956 | { 1729, 4, 1, 4, 72, 0, 0, MipsOpInfoBase + 197, 0, 0, 0x6ULL }, // FMSUB_D |
| 4957 | { 1728, 2, 1, 4, 421, 0, 0, MipsOpInfoBase + 634, 0, 0, 0x4ULL }, // FMOV_S_MMR6 |
| 4958 | { 1727, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // FMOV_S_MM |
| 4959 | { 1726, 2, 1, 4, 125, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // FMOV_S |
| 4960 | { 1725, 2, 1, 4, 421, 0, 0, MipsOpInfoBase + 626, 0, 0, 0x4ULL }, // FMOV_D_MMR6 |
| 4961 | { 1724, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 626, 0, 0, 0x4ULL }, // FMOV_D64_MM |
| 4962 | { 1723, 2, 1, 4, 125, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // FMOV_D64 |
| 4963 | { 1722, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 757, 0, 0, 0x4ULL }, // FMOV_D32_MM |
| 4964 | { 1721, 2, 1, 4, 125, 0, 0, MipsOpInfoBase + 757, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // FMOV_D32 |
| 4965 | { 1720, 3, 1, 4, 45, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FMIN_W |
| 4966 | { 1719, 3, 1, 4, 45, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FMIN_D |
| 4967 | { 1718, 3, 1, 4, 168, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FMIN_A_W |
| 4968 | { 1717, 3, 1, 4, 168, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FMIN_A_D |
| 4969 | { 1716, 3, 1, 4, 167, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FMAX_W |
| 4970 | { 1715, 3, 1, 4, 167, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FMAX_D |
| 4971 | { 1714, 3, 1, 4, 166, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FMAX_A_W |
| 4972 | { 1713, 3, 1, 4, 166, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FMAX_A_D |
| 4973 | { 1712, 4, 1, 4, 199, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // FMADD_W |
| 4974 | { 1711, 4, 1, 4, 199, 0, 0, MipsOpInfoBase + 197, 0, 0, 0x6ULL }, // FMADD_D |
| 4975 | { 1710, 2, 1, 4, 412, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_S_MMR6 |
| 4976 | { 1709, 2, 1, 4, 388, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_S_MM |
| 4977 | { 1708, 2, 1, 4, 226, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_S |
| 4978 | { 1707, 2, 1, 4, 388, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_MM |
| 4979 | { 1706, 2, 1, 4, 412, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_D_MMR6 |
| 4980 | { 1705, 2, 1, 4, 226, 0, 0, MipsOpInfoBase + 632, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_D64 |
| 4981 | { 1704, 2, 1, 4, 226, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_D32 |
| 4982 | { 1703, 2, 1, 4, 412, 0, 0, MipsOpInfoBase + 628, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_L_S_MMR6 |
| 4983 | { 1702, 2, 1, 4, 226, 0, 0, MipsOpInfoBase + 628, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_L_S |
| 4984 | { 1701, 2, 1, 4, 412, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_L_D_MMR6 |
| 4985 | { 1700, 2, 1, 4, 226, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_L_D64 |
| 4986 | { 1699, 2, 1, 4, 68, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FLOG2_W |
| 4987 | { 1698, 2, 1, 4, 68, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FLOG2_D |
| 4988 | { 1697, 2, 1, 4, 36, 0, 0, MipsOpInfoBase + 790, 0, 0, 0x6ULL }, // FILL_W |
| 4989 | { 1696, 2, 1, 4, 36, 0, 0, MipsOpInfoBase + 788, 0, 0, 0x6ULL }, // FILL_H |
| 4990 | { 1695, 2, 1, 4, 36, 0, 0, MipsOpInfoBase + 786, 0, 0, 0x6ULL }, // FILL_D |
| 4991 | { 1694, 2, 1, 4, 36, 0, 0, MipsOpInfoBase + 784, 0, 0, 0x6ULL }, // FILL_B |
| 4992 | { 1693, 2, 1, 4, 157, 0, 0, MipsOpInfoBase + 782, 0, 0, 0x6ULL }, // FFQR_W |
| 4993 | { 1692, 2, 1, 4, 157, 0, 0, MipsOpInfoBase + 780, 0, 0, 0x6ULL }, // FFQR_D |
| 4994 | { 1691, 2, 1, 4, 156, 0, 0, MipsOpInfoBase + 782, 0, 0, 0x6ULL }, // FFQL_W |
| 4995 | { 1690, 2, 1, 4, 156, 0, 0, MipsOpInfoBase + 780, 0, 0, 0x6ULL }, // FFQL_D |
| 4996 | { 1689, 2, 1, 4, 155, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FFINT_U_W |
| 4997 | { 1688, 2, 1, 4, 155, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FFINT_U_D |
| 4998 | { 1687, 2, 1, 4, 155, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FFINT_S_W |
| 4999 | { 1686, 2, 1, 4, 155, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FFINT_S_D |
| 5000 | { 1685, 2, 1, 4, 164, 0, 0, MipsOpInfoBase + 782, 0, 0, 0x6ULL }, // FEXUPR_W |
| 5001 | { 1684, 2, 1, 4, 164, 0, 0, MipsOpInfoBase + 780, 0, 0, 0x6ULL }, // FEXUPR_D |
| 5002 | { 1683, 2, 1, 4, 163, 0, 0, MipsOpInfoBase + 782, 0, 0, 0x6ULL }, // FEXUPL_W |
| 5003 | { 1682, 2, 1, 4, 163, 0, 0, MipsOpInfoBase + 780, 0, 0, 0x6ULL }, // FEXUPL_D |
| 5004 | { 1681, 3, 1, 4, 135, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FEXP2_W |
| 5005 | { 1680, 3, 1, 4, 135, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FEXP2_D |
| 5006 | { 1679, 3, 1, 4, 162, 0, 0, MipsOpInfoBase + 777, 0, 0, 0x6ULL }, // FEXDO_W |
| 5007 | { 1678, 3, 1, 4, 162, 0, 0, MipsOpInfoBase + 774, 0, 0, 0x6ULL }, // FEXDO_H |
| 5008 | { 1677, 3, 1, 4, 75, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FDIV_W |
| 5009 | { 1676, 3, 1, 4, 422, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // FDIV_S_MMR6 |
| 5010 | { 1675, 3, 1, 4, 396, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_S_MM |
| 5011 | { 1674, 3, 1, 4, 191, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_S |
| 5012 | { 1673, 3, 1, 4, 397, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_D64_MM |
| 5013 | { 1672, 3, 1, 4, 192, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_D64 |
| 5014 | { 1671, 3, 1, 4, 397, 1, 0, MipsOpInfoBase + 759, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_D32_MM |
| 5015 | { 1670, 3, 1, 4, 192, 1, 0, MipsOpInfoBase + 759, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_D32 |
| 5016 | { 1669, 3, 1, 4, 74, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FDIV_D |
| 5017 | { 1668, 3, 1, 4, 44, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUN_W |
| 5018 | { 1667, 3, 1, 4, 44, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUN_D |
| 5019 | { 1666, 3, 1, 4, 154, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUNE_W |
| 5020 | { 1665, 3, 1, 4, 154, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUNE_D |
| 5021 | { 1664, 3, 1, 4, 153, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FCULT_W |
| 5022 | { 1663, 3, 1, 4, 153, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FCULT_D |
| 5023 | { 1662, 3, 1, 4, 152, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FCULE_W |
| 5024 | { 1661, 3, 1, 4, 152, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FCULE_D |
| 5025 | { 1660, 3, 1, 4, 151, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUEQ_W |
| 5026 | { 1659, 3, 1, 4, 151, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUEQ_D |
| 5027 | { 1658, 3, 1, 4, 150, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCOR_W |
| 5028 | { 1657, 3, 1, 4, 150, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCOR_D |
| 5029 | { 1656, 3, 1, 4, 149, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCNE_W |
| 5030 | { 1655, 3, 1, 4, 149, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCNE_D |
| 5031 | { 1654, 3, 0, 4, 393, 0, 1, MipsOpInfoBase + 771, 30, 0, 0x44ULL }, // FCMP_S32_MM |
| 5032 | { 1653, 3, 0, 4, 189, 0, 1, MipsOpInfoBase + 771, 30, 0, 0x44ULL }, // FCMP_S32 |
| 5033 | { 1652, 3, 0, 4, 189, 0, 1, MipsOpInfoBase + 768, 30, 0, 0x44ULL }, // FCMP_D64 |
| 5034 | { 1651, 3, 0, 4, 393, 0, 1, MipsOpInfoBase + 765, 30, 0, 0x44ULL }, // FCMP_D32_MM |
| 5035 | { 1650, 3, 0, 4, 189, 0, 1, MipsOpInfoBase + 765, 30, 0, 0x44ULL }, // FCMP_D32 |
| 5036 | { 1649, 3, 1, 4, 148, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FCLT_W |
| 5037 | { 1648, 3, 1, 4, 148, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FCLT_D |
| 5038 | { 1647, 3, 1, 4, 147, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // FCLE_W |
| 5039 | { 1646, 3, 1, 4, 147, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // FCLE_D |
| 5040 | { 1645, 2, 1, 4, 165, 0, 0, MipsOpInfoBase + 254, 0, 0, 0x6ULL }, // FCLASS_W |
| 5041 | { 1644, 2, 1, 4, 165, 0, 0, MipsOpInfoBase + 252, 0, 0, 0x6ULL }, // FCLASS_D |
| 5042 | { 1643, 3, 1, 4, 146, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCEQ_W |
| 5043 | { 1642, 3, 1, 4, 146, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCEQ_D |
| 5044 | { 1641, 3, 1, 4, 145, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCAF_W |
| 5045 | { 1640, 3, 1, 4, 145, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCAF_D |
| 5046 | { 1639, 3, 1, 4, 202, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FADD_W |
| 5047 | { 1638, 3, 1, 4, 414, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x6ULL }, // FADD_S_MMR6 |
| 5048 | { 1637, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_S_MM |
| 5049 | { 1636, 3, 1, 4, 12, 1, 0, MipsOpInfoBase + 762, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_S |
| 5050 | { 1635, 3, 1, 4, 183, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // FADD_PS64 |
| 5051 | { 1634, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_D64_MM |
| 5052 | { 1633, 3, 1, 4, 182, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_D64 |
| 5053 | { 1632, 3, 1, 4, 395, 1, 0, MipsOpInfoBase + 759, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_D32_MM |
| 5054 | { 1631, 3, 1, 4, 182, 1, 0, MipsOpInfoBase + 759, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_D32 |
| 5055 | { 1630, 3, 1, 4, 202, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FADD_D |
| 5056 | { 1629, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 634, 0, 0, 0x4ULL }, // FABS_S_MM |
| 5057 | { 1628, 2, 1, 4, 379, 0, 0, MipsOpInfoBase + 634, 0, 0, 0x4ULL }, // FABS_S |
| 5058 | { 1627, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 626, 0, 0, 0x4ULL }, // FABS_D64_MM |
| 5059 | { 1626, 2, 1, 4, 126, 0, 0, MipsOpInfoBase + 626, 0, 0, 0x4ULL }, // FABS_D64 |
| 5060 | { 1625, 2, 1, 4, 395, 0, 0, MipsOpInfoBase + 757, 0, 0, 0x4ULL }, // FABS_D32_MM |
| 5061 | { 1624, 2, 1, 4, 126, 0, 0, MipsOpInfoBase + 757, 0, 0, 0x4ULL }, // FABS_D32 |
| 5062 | { 1623, 4, 1, 4, 238, 0, 0, MipsOpInfoBase + 650, 0, 0, 0x1ULL }, // EXT_MMR6 |
| 5063 | { 1622, 4, 1, 4, 237, 0, 0, MipsOpInfoBase + 650, 0, 0, 0x1ULL }, // EXT_MM |
| 5064 | { 1621, 4, 1, 4, 375, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // EXTS32 |
| 5065 | { 1620, 4, 1, 4, 375, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // EXTS |
| 5066 | { 1619, 3, 1, 4, 631, 0, 1, MipsOpInfoBase + 751, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_W_MM |
| 5067 | { 1618, 3, 1, 4, 436, 0, 1, MipsOpInfoBase + 751, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_W |
| 5068 | { 1617, 3, 1, 4, 630, 0, 1, MipsOpInfoBase + 751, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_S_H_MM |
| 5069 | { 1616, 3, 1, 4, 435, 0, 1, MipsOpInfoBase + 751, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_S_H |
| 5070 | { 1615, 3, 1, 4, 629, 0, 1, MipsOpInfoBase + 751, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_R_W_MM |
| 5071 | { 1614, 3, 1, 4, 434, 0, 1, MipsOpInfoBase + 751, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_R_W |
| 5072 | { 1613, 3, 1, 4, 628, 0, 1, MipsOpInfoBase + 751, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_RS_W_MM |
| 5073 | { 1612, 3, 1, 4, 433, 0, 1, MipsOpInfoBase + 751, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_RS_W |
| 5074 | { 1611, 3, 1, 4, 627, 0, 1, MipsOpInfoBase + 754, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_W_MM |
| 5075 | { 1610, 3, 1, 4, 432, 0, 1, MipsOpInfoBase + 754, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_W |
| 5076 | { 1609, 3, 1, 4, 626, 0, 1, MipsOpInfoBase + 754, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_S_H_MM |
| 5077 | { 1608, 3, 1, 4, 431, 0, 1, MipsOpInfoBase + 754, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_S_H |
| 5078 | { 1607, 3, 1, 4, 625, 0, 1, MipsOpInfoBase + 754, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_R_W_MM |
| 5079 | { 1606, 3, 1, 4, 430, 0, 1, MipsOpInfoBase + 754, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_R_W |
| 5080 | { 1605, 3, 1, 4, 624, 0, 1, MipsOpInfoBase + 754, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_RS_W_MM |
| 5081 | { 1604, 3, 1, 4, 429, 0, 1, MipsOpInfoBase + 754, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_RS_W |
| 5082 | { 1603, 3, 1, 4, 623, 1, 1, MipsOpInfoBase + 751, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTP_MM |
| 5083 | { 1602, 3, 1, 4, 622, 1, 1, MipsOpInfoBase + 754, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPV_MM |
| 5084 | { 1601, 3, 1, 4, 471, 1, 1, MipsOpInfoBase + 754, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPV |
| 5085 | { 1600, 3, 1, 4, 621, 1, 2, MipsOpInfoBase + 751, 26, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPDP_MM |
| 5086 | { 1599, 3, 1, 4, 620, 1, 2, MipsOpInfoBase + 754, 26, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPDPV_MM |
| 5087 | { 1598, 3, 1, 4, 469, 1, 2, MipsOpInfoBase + 754, 26, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPDPV |
| 5088 | { 1597, 3, 1, 4, 470, 1, 2, MipsOpInfoBase + 751, 26, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPDP |
| 5089 | { 1596, 3, 1, 4, 472, 1, 1, MipsOpInfoBase + 751, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTP |
| 5090 | { 1595, 4, 1, 4, 110, 0, 0, MipsOpInfoBase + 650, 0, 0, 0x1ULL }, // EXT |
| 5091 | { 1594, 1, 1, 4, 321, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EVP_MMR6 |
| 5092 | { 1593, 1, 1, 4, 328, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EVPE |
| 5093 | { 1592, 1, 1, 4, 313, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EVP |
| 5094 | { 1591, 0, 0, 4, 297, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERET_MMR6 |
| 5095 | { 1590, 0, 0, 4, 293, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERET_MM |
| 5096 | { 1589, 0, 0, 4, 297, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERETNC_MMR6 |
| 5097 | { 1588, 0, 0, 4, 273, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERETNC |
| 5098 | { 1587, 0, 0, 4, 273, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERET |
| 5099 | { 1586, 1, 1, 4, 328, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EMT |
| 5100 | { 1585, 1, 1, 4, 322, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EI_MMR6 |
| 5101 | { 1584, 1, 1, 4, 315, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EI_MM |
| 5102 | { 1583, 1, 1, 4, 100, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EI |
| 5103 | { 1582, 0, 0, 4, 323, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EHB_MMR6 |
| 5104 | { 1581, 0, 0, 4, 316, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EHB_MM |
| 5105 | { 1580, 0, 0, 4, 101, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EHB |
| 5106 | { 1579, 2, 0, 2, 254, 0, 2, MipsOpInfoBase + 397, 7, 0, 0x0ULL }, // DivuRxRy16 |
| 5107 | { 1578, 2, 0, 2, 253, 0, 2, MipsOpInfoBase + 397, 7, 0, 0x0ULL }, // DivRxRy16 |
| 5108 | { 1577, 1, 1, 4, 321, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DVP_MMR6 |
| 5109 | { 1576, 1, 1, 4, 328, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DVPE |
| 5110 | { 1575, 1, 1, 4, 313, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DVP |
| 5111 | { 1574, 2, 0, 4, 267, 0, 2, MipsOpInfoBase + 388, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DUDIV |
| 5112 | { 1573, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // DSUBu |
| 5113 | { 1572, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSUB |
| 5114 | { 1571, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 746, 0, 0, 0x1ULL }, // DSRLV |
| 5115 | { 1570, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSRL32 |
| 5116 | { 1569, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0, 0x1ULL }, // DSRL |
| 5117 | { 1568, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 746, 0, 0, 0x1ULL }, // DSRAV |
| 5118 | { 1567, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSRA32 |
| 5119 | { 1566, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0, 0x1ULL }, // DSRA |
| 5120 | { 1565, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 746, 0, 0, 0x1ULL }, // DSLLV |
| 5121 | { 1564, 2, 1, 4, 239, 0, 0, MipsOpInfoBase + 749, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSLL64_32 |
| 5122 | { 1563, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSLL32 |
| 5123 | { 1562, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0, 0x1ULL }, // DSLL |
| 5124 | { 1561, 2, 1, 4, 240, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x1ULL }, // DSHD |
| 5125 | { 1560, 2, 0, 4, 266, 0, 2, MipsOpInfoBase + 388, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSDIV |
| 5126 | { 1559, 2, 1, 4, 240, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x1ULL }, // DSBH |
| 5127 | { 1558, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 746, 0, 0, 0x1ULL }, // DROTRV |
| 5128 | { 1557, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DROTR32 |
| 5129 | { 1556, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0, 0x1ULL }, // DROTR |
| 5130 | { 1555, 4, 1, 4, 726, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPS_W_PH_MMR2 |
| 5131 | { 1554, 4, 1, 4, 562, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPS_W_PH |
| 5132 | { 1553, 4, 1, 4, 729, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPSX_W_PH_MMR2 |
| 5133 | { 1552, 4, 1, 4, 565, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPSX_W_PH |
| 5134 | { 1551, 4, 1, 4, 619, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPSU_H_QBR_MM |
| 5135 | { 1550, 4, 1, 4, 468, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPSU_H_QBR |
| 5136 | { 1549, 4, 1, 4, 618, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPSU_H_QBL_MM |
| 5137 | { 1548, 4, 1, 4, 467, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPSU_H_QBL |
| 5138 | { 1547, 4, 1, 4, 71, 0, 0, MipsOpInfoBase + 738, 0, 0, 0x6ULL }, // DPSUB_U_W |
| 5139 | { 1546, 4, 1, 4, 71, 0, 0, MipsOpInfoBase + 734, 0, 0, 0x6ULL }, // DPSUB_U_H |
| 5140 | { 1545, 4, 1, 4, 71, 0, 0, MipsOpInfoBase + 730, 0, 0, 0x6ULL }, // DPSUB_U_D |
| 5141 | { 1544, 4, 1, 4, 71, 0, 0, MipsOpInfoBase + 738, 0, 0, 0x6ULL }, // DPSUB_S_W |
| 5142 | { 1543, 4, 1, 4, 71, 0, 0, MipsOpInfoBase + 734, 0, 0, 0x6ULL }, // DPSUB_S_H |
| 5143 | { 1542, 4, 1, 4, 71, 0, 0, MipsOpInfoBase + 730, 0, 0, 0x6ULL }, // DPSUB_S_D |
| 5144 | { 1541, 4, 1, 4, 617, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQ_S_W_PH_MM |
| 5145 | { 1540, 4, 1, 4, 466, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQ_S_W_PH |
| 5146 | { 1539, 4, 1, 4, 616, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQ_SA_L_W_MM |
| 5147 | { 1538, 4, 1, 4, 465, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQ_SA_L_W |
| 5148 | { 1537, 4, 1, 4, 727, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQX_S_W_PH_MMR2 |
| 5149 | { 1536, 4, 1, 4, 563, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQX_S_W_PH |
| 5150 | { 1535, 4, 1, 4, 728, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQX_SA_W_PH_MMR2 |
| 5151 | { 1534, 4, 1, 4, 564, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQX_SA_W_PH |
| 5152 | { 1533, 2, 1, 4, 375, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x1ULL }, // DPOP |
| 5153 | { 1532, 4, 1, 4, 722, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPA_W_PH_MMR2 |
| 5154 | { 1531, 4, 1, 4, 558, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPA_W_PH |
| 5155 | { 1530, 4, 1, 4, 725, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPAX_W_PH_MMR2 |
| 5156 | { 1529, 4, 1, 4, 561, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPAX_W_PH |
| 5157 | { 1528, 4, 1, 4, 615, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPAU_H_QBR_MM |
| 5158 | { 1527, 4, 1, 4, 464, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPAU_H_QBR |
| 5159 | { 1526, 4, 1, 4, 614, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPAU_H_QBL_MM |
| 5160 | { 1525, 4, 1, 4, 463, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPAU_H_QBL |
| 5161 | { 1524, 4, 1, 4, 613, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQ_S_W_PH_MM |
| 5162 | { 1523, 4, 1, 4, 462, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQ_S_W_PH |
| 5163 | { 1522, 4, 1, 4, 612, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQ_SA_L_W_MM |
| 5164 | { 1521, 4, 1, 4, 461, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQ_SA_L_W |
| 5165 | { 1520, 4, 1, 4, 724, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQX_S_W_PH_MMR2 |
| 5166 | { 1519, 4, 1, 4, 560, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQX_S_W_PH |
| 5167 | { 1518, 4, 1, 4, 723, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQX_SA_W_PH_MMR2 |
| 5168 | { 1517, 4, 1, 4, 559, 0, 1, MipsOpInfoBase + 742, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQX_SA_W_PH |
| 5169 | { 1516, 4, 1, 4, 203, 0, 0, MipsOpInfoBase + 738, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_U_W |
| 5170 | { 1515, 4, 1, 4, 203, 0, 0, MipsOpInfoBase + 734, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_U_H |
| 5171 | { 1514, 4, 1, 4, 203, 0, 0, MipsOpInfoBase + 730, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_U_D |
| 5172 | { 1513, 4, 1, 4, 203, 0, 0, MipsOpInfoBase + 738, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_S_W |
| 5173 | { 1512, 4, 1, 4, 203, 0, 0, MipsOpInfoBase + 734, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_S_H |
| 5174 | { 1511, 4, 1, 4, 203, 0, 0, MipsOpInfoBase + 730, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_S_D |
| 5175 | { 1510, 3, 1, 4, 204, 0, 0, MipsOpInfoBase + 727, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_U_W |
| 5176 | { 1509, 3, 1, 4, 204, 0, 0, MipsOpInfoBase + 724, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_U_H |
| 5177 | { 1508, 3, 1, 4, 204, 0, 0, MipsOpInfoBase + 721, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_U_D |
| 5178 | { 1507, 3, 1, 4, 204, 0, 0, MipsOpInfoBase + 727, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_S_W |
| 5179 | { 1506, 3, 1, 4, 204, 0, 0, MipsOpInfoBase + 724, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_S_H |
| 5180 | { 1505, 3, 1, 4, 204, 0, 0, MipsOpInfoBase + 721, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_S_D |
| 5181 | { 1504, 3, 1, 4, 8, 0, 0, MipsOpInfoBase + 237, 0, 0, 0x6ULL }, // DMUL_R6 |
| 5182 | { 1503, 3, 1, 4, 264, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DMULU |
| 5183 | { 1502, 2, 0, 4, 265, 0, 2, MipsOpInfoBase + 388, 21, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // DMULTu |
| 5184 | { 1501, 2, 0, 4, 265, 0, 2, MipsOpInfoBase + 388, 21, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // DMULT |
| 5185 | { 1500, 3, 1, 4, 376, 0, 5, MipsOpInfoBase + 237, 16, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // DMUL |
| 5186 | { 1499, 3, 1, 4, 8, 0, 0, MipsOpInfoBase + 237, 0, 0, 0x6ULL }, // DMUHU |
| 5187 | { 1498, 3, 1, 4, 8, 0, 0, MipsOpInfoBase + 237, 0, 0, 0x6ULL }, // DMUH |
| 5188 | { 1497, 3, 1, 4, 331, 0, 0, MipsOpInfoBase + 715, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMTGC0 |
| 5189 | { 1496, 2, 2, 4, 375, 0, 0, MipsOpInfoBase + 365, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMTC2_OCTEON |
| 5190 | { 1495, 3, 1, 4, 326, 0, 0, MipsOpInfoBase + 718, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMTC2 |
| 5191 | { 1494, 2, 1, 4, 425, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // DMTC1 |
| 5192 | { 1493, 3, 1, 4, 325, 0, 0, MipsOpInfoBase + 715, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMTC0 |
| 5193 | { 1492, 1, 1, 4, 328, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DMT |
| 5194 | { 1491, 3, 1, 4, 9, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DMODU |
| 5195 | { 1490, 3, 1, 4, 272, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DMOD |
| 5196 | { 1489, 3, 1, 4, 331, 0, 0, MipsOpInfoBase + 707, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMFGC0 |
| 5197 | { 1488, 2, 2, 4, 375, 0, 0, MipsOpInfoBase + 365, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMFC2_OCTEON |
| 5198 | { 1487, 3, 1, 4, 326, 0, 0, MipsOpInfoBase + 712, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMFC2 |
| 5199 | { 1486, 2, 1, 4, 425, 0, 0, MipsOpInfoBase + 710, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // DMFC1 |
| 5200 | { 1485, 3, 1, 4, 324, 0, 0, MipsOpInfoBase + 707, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMFC0 |
| 5201 | { 1484, 4, 1, 4, 242, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DLSA_R6 |
| 5202 | { 1483, 4, 1, 4, 242, 0, 0, MipsOpInfoBase + 698, 0, 0, 0x6ULL }, // DLSA |
| 5203 | { 1482, 1, 1, 4, 322, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DI_MMR6 |
| 5204 | { 1481, 1, 1, 4, 315, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DI_MM |
| 5205 | { 1480, 3, 1, 4, 16, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // DIV_U_W |
| 5206 | { 1479, 3, 1, 4, 16, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // DIV_U_H |
| 5207 | { 1478, 3, 1, 4, 16, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // DIV_U_D |
| 5208 | { 1477, 3, 1, 4, 16, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // DIV_U_B |
| 5209 | { 1476, 3, 1, 4, 15, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // DIV_S_W |
| 5210 | { 1475, 3, 1, 4, 15, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // DIV_S_H |
| 5211 | { 1474, 3, 1, 4, 15, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // DIV_S_D |
| 5212 | { 1473, 3, 1, 4, 15, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // DIV_S_B |
| 5213 | { 1472, 3, 1, 4, 262, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DIV_MMR6 |
| 5214 | { 1471, 3, 1, 4, 262, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DIVU_MMR6 |
| 5215 | { 1470, 3, 1, 4, 105, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DIVU |
| 5216 | { 1469, 3, 1, 4, 103, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DIV |
| 5217 | { 1468, 5, 1, 4, 240, 0, 0, MipsOpInfoBase + 702, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DINSU |
| 5218 | { 1467, 5, 1, 4, 240, 0, 0, MipsOpInfoBase + 702, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DINSM |
| 5219 | { 1466, 5, 1, 4, 240, 0, 0, MipsOpInfoBase + 702, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DINS |
| 5220 | { 1465, 1, 1, 4, 100, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DI |
| 5221 | { 1464, 4, 1, 4, 240, 0, 0, MipsOpInfoBase + 642, 0, 0, 0x1ULL }, // DEXTU |
| 5222 | { 1463, 4, 1, 4, 240, 0, 0, MipsOpInfoBase + 642, 0, 0, 0x1ULL }, // DEXTM |
| 5223 | { 1462, 4, 1, 4, 239, 0, 0, MipsOpInfoBase + 646, 0, 0, 0x1ULL }, // DEXT64_32 |
| 5224 | { 1461, 4, 1, 4, 240, 0, 0, MipsOpInfoBase + 642, 0, 0, 0x1ULL }, // DEXT |
| 5225 | { 1460, 0, 0, 4, 297, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // DERET_MMR6 |
| 5226 | { 1459, 0, 0, 4, 293, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // DERET_MM |
| 5227 | { 1458, 0, 0, 4, 273, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // DERET |
| 5228 | { 1457, 3, 1, 4, 9, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DDIVU |
| 5229 | { 1456, 3, 1, 4, 272, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DDIV |
| 5230 | { 1455, 2, 1, 4, 242, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x6ULL }, // DCLZ_R6 |
| 5231 | { 1454, 2, 1, 4, 241, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x1ULL }, // DCLZ |
| 5232 | { 1453, 2, 1, 4, 242, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x6ULL }, // DCLO_R6 |
| 5233 | { 1452, 2, 1, 4, 241, 0, 0, MipsOpInfoBase + 388, 0, 0, 0x1ULL }, // DCLO |
| 5234 | { 1451, 2, 1, 4, 242, 0, 0, MipsOpInfoBase + 388, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DBITSWAP |
| 5235 | { 1450, 3, 1, 4, 242, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DAUI |
| 5236 | { 1449, 3, 1, 4, 242, 0, 0, MipsOpInfoBase + 695, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DATI |
| 5237 | { 1448, 4, 1, 4, 242, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DALIGN |
| 5238 | { 1447, 3, 1, 4, 242, 0, 0, MipsOpInfoBase + 695, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DAHI |
| 5239 | { 1446, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // DADDu |
| 5240 | { 1445, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // DADDiu |
| 5241 | { 1444, 3, 1, 4, 241, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // DADDi |
| 5242 | { 1443, 3, 1, 4, 240, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DADD |
| 5243 | { 1442, 2, 0, 4, 235, 0, 1, MipsOpInfoBase + 571, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CmpiRxImmX16 |
| 5244 | { 1441, 2, 0, 2, 235, 0, 1, MipsOpInfoBase + 571, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CmpiRxImm16 |
| 5245 | { 1440, 2, 0, 2, 235, 0, 1, MipsOpInfoBase + 397, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CmpRxRy16 |
| 5246 | { 1439, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_S_MM |
| 5247 | { 1438, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_S |
| 5248 | { 1437, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_D64_MM |
| 5249 | { 1436, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_D64 |
| 5250 | { 1435, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_D32_MM |
| 5251 | { 1434, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_D32 |
| 5252 | { 1433, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_S_MM |
| 5253 | { 1432, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_S |
| 5254 | { 1431, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_D64_MM |
| 5255 | { 1430, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_D64 |
| 5256 | { 1429, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_D32_MM |
| 5257 | { 1428, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_D32 |
| 5258 | { 1427, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_S_MM |
| 5259 | { 1426, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_S |
| 5260 | { 1425, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_D64_MM |
| 5261 | { 1424, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_D64 |
| 5262 | { 1423, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_D32_MM |
| 5263 | { 1422, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_D32 |
| 5264 | { 1421, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_S_MM |
| 5265 | { 1420, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_S |
| 5266 | { 1419, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_D64_MM |
| 5267 | { 1418, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_D64 |
| 5268 | { 1417, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_D32_MM |
| 5269 | { 1416, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_D32 |
| 5270 | { 1415, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_S_MM |
| 5271 | { 1414, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_S |
| 5272 | { 1413, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_D64_MM |
| 5273 | { 1412, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_D64 |
| 5274 | { 1411, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_D32_MM |
| 5275 | { 1410, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_D32 |
| 5276 | { 1409, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_S_MM |
| 5277 | { 1408, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_S |
| 5278 | { 1407, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_D64_MM |
| 5279 | { 1406, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_D64 |
| 5280 | { 1405, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_D32_MM |
| 5281 | { 1404, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_D32 |
| 5282 | { 1403, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_S_MM |
| 5283 | { 1402, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_S |
| 5284 | { 1401, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_D64_MM |
| 5285 | { 1400, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_D64 |
| 5286 | { 1399, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_D32_MM |
| 5287 | { 1398, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_D32 |
| 5288 | { 1397, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_S_MM |
| 5289 | { 1396, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_S |
| 5290 | { 1395, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_D64_MM |
| 5291 | { 1394, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_D64 |
| 5292 | { 1393, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_D32_MM |
| 5293 | { 1392, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_D32 |
| 5294 | { 1391, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_S_MM |
| 5295 | { 1390, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_S |
| 5296 | { 1389, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_D64_MM |
| 5297 | { 1388, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_D64 |
| 5298 | { 1387, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_D32_MM |
| 5299 | { 1386, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_D32 |
| 5300 | { 1385, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_S_MM |
| 5301 | { 1384, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_S |
| 5302 | { 1383, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_D64_MM |
| 5303 | { 1382, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_D64 |
| 5304 | { 1381, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_D32_MM |
| 5305 | { 1380, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_D32 |
| 5306 | { 1379, 3, 1, 4, 392, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_S_MM |
| 5307 | { 1378, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_S |
| 5308 | { 1377, 3, 1, 4, 392, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_D64_MM |
| 5309 | { 1376, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_D64 |
| 5310 | { 1375, 3, 1, 4, 392, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_D32_MM |
| 5311 | { 1374, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_D32 |
| 5312 | { 1373, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_S_MM |
| 5313 | { 1372, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_S |
| 5314 | { 1371, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_D64_MM |
| 5315 | { 1370, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_D64 |
| 5316 | { 1369, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_D32_MM |
| 5317 | { 1368, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_D32 |
| 5318 | { 1367, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_S_MM |
| 5319 | { 1366, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_S |
| 5320 | { 1365, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_D64_MM |
| 5321 | { 1364, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_D64 |
| 5322 | { 1363, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_D32_MM |
| 5323 | { 1362, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_D32 |
| 5324 | { 1361, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_S_MM |
| 5325 | { 1360, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_S |
| 5326 | { 1359, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_D64_MM |
| 5327 | { 1358, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_D64 |
| 5328 | { 1357, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_D32_MM |
| 5329 | { 1356, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_D32 |
| 5330 | { 1355, 3, 1, 4, 389, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_S_MM |
| 5331 | { 1354, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_S |
| 5332 | { 1353, 3, 1, 4, 389, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_D64_MM |
| 5333 | { 1352, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_D64 |
| 5334 | { 1351, 3, 1, 4, 389, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_D32_MM |
| 5335 | { 1350, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_D32 |
| 5336 | { 1349, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_S_MM |
| 5337 | { 1348, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 692, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_S |
| 5338 | { 1347, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_D64_MM |
| 5339 | { 1346, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_D64 |
| 5340 | { 1345, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_D32_MM |
| 5341 | { 1344, 3, 1, 4, 188, 0, 0, MipsOpInfoBase + 686, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_D32 |
| 5342 | { 1343, 2, 1, 4, 409, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_S_MMR6 |
| 5343 | { 1342, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_S_MM |
| 5344 | { 1341, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_S |
| 5345 | { 1340, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 632, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_D64_MM |
| 5346 | { 1339, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 632, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_D64 |
| 5347 | { 1338, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 630, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_D32_MM |
| 5348 | { 1337, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 630, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_D32 |
| 5349 | { 1336, 2, 1, 4, 409, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_W_MMR6 |
| 5350 | { 1335, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_W_MM |
| 5351 | { 1334, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 634, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_W |
| 5352 | { 1333, 2, 1, 4, 187, 0, 0, MipsOpInfoBase + 632, 0, 0, 0x4ULL }, // CVT_S_PU64 |
| 5353 | { 1332, 2, 1, 4, 187, 0, 0, MipsOpInfoBase + 632, 0, 0, 0x4ULL }, // CVT_S_PL64 |
| 5354 | { 1331, 2, 1, 4, 409, 1, 0, MipsOpInfoBase + 628, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_L_MMR6 |
| 5355 | { 1330, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 632, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_L |
| 5356 | { 1329, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 632, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_D64_MM |
| 5357 | { 1328, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 632, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_D64 |
| 5358 | { 1327, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 630, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_D32_MM |
| 5359 | { 1326, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 630, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_D32 |
| 5360 | { 1325, 2, 1, 4, 382, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_PW_PS64 |
| 5361 | { 1324, 3, 1, 4, 186, 1, 0, MipsOpInfoBase + 683, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CVT_PS_S64 |
| 5362 | { 1323, 2, 1, 4, 382, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_PS_PW64 |
| 5363 | { 1322, 2, 1, 4, 409, 1, 0, MipsOpInfoBase + 628, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_S_MMR6 |
| 5364 | { 1321, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 628, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_S_MM |
| 5365 | { 1320, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 628, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_S |
| 5366 | { 1319, 2, 1, 4, 409, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_D_MMR6 |
| 5367 | { 1318, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_D64_MM |
| 5368 | { 1317, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_D64 |
| 5369 | { 1316, 2, 1, 4, 409, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D_L_MMR6 |
| 5370 | { 1315, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 628, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_W_MM |
| 5371 | { 1314, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 628, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_W |
| 5372 | { 1313, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 628, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_S_MM |
| 5373 | { 1312, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 628, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_S |
| 5374 | { 1311, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 626, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_L |
| 5375 | { 1310, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 681, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D32_W_MM |
| 5376 | { 1309, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 681, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D32_W |
| 5377 | { 1308, 2, 1, 4, 388, 1, 0, MipsOpInfoBase + 681, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D32_S_MM |
| 5378 | { 1307, 2, 1, 4, 185, 1, 0, MipsOpInfoBase + 681, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D32_S |
| 5379 | { 1306, 2, 0, 4, 124, 0, 0, MipsOpInfoBase + 679, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CTCMSA |
| 5380 | { 1305, 2, 1, 4, 327, 0, 0, MipsOpInfoBase + 677, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CTC2_MM |
| 5381 | { 1304, 2, 1, 4, 403, 0, 0, MipsOpInfoBase + 675, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CTC1_MM |
| 5382 | { 1303, 2, 1, 4, 214, 0, 0, MipsOpInfoBase + 675, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CTC1 |
| 5383 | { 1302, 3, 1, 4, 373, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32W |
| 5384 | { 1301, 3, 1, 4, 373, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32H |
| 5385 | { 1300, 3, 1, 4, 374, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32D |
| 5386 | { 1299, 3, 1, 4, 373, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32CW |
| 5387 | { 1298, 3, 1, 4, 373, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32CH |
| 5388 | { 1297, 3, 1, 4, 374, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32CD |
| 5389 | { 1296, 3, 1, 4, 373, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32CB |
| 5390 | { 1295, 3, 1, 4, 373, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32B |
| 5391 | { 1294, 3, 1, 4, 216, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x6ULL }, // COPY_U_W |
| 5392 | { 1293, 3, 1, 4, 216, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x6ULL }, // COPY_U_H |
| 5393 | { 1292, 3, 1, 4, 216, 0, 0, MipsOpInfoBase + 663, 0, 0, 0x6ULL }, // COPY_U_B |
| 5394 | { 1291, 3, 1, 4, 41, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x6ULL }, // COPY_S_W |
| 5395 | { 1290, 3, 1, 4, 41, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x6ULL }, // COPY_S_H |
| 5396 | { 1289, 3, 1, 4, 41, 0, 0, MipsOpInfoBase + 666, 0, 0, 0x6ULL }, // COPY_S_D |
| 5397 | { 1288, 3, 1, 4, 41, 0, 0, MipsOpInfoBase + 663, 0, 0, 0x6ULL }, // COPY_S_B |
| 5398 | { 1287, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_UN_S_MMR6 |
| 5399 | { 1286, 3, 1, 4, 46, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_UN_S |
| 5400 | { 1285, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_UN_D_MMR6 |
| 5401 | { 1284, 3, 1, 4, 46, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_UN_D |
| 5402 | { 1283, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_ULT_S_MMR6 |
| 5403 | { 1282, 3, 1, 4, 50, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_ULT_S |
| 5404 | { 1281, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_ULT_D_MMR6 |
| 5405 | { 1280, 3, 1, 4, 50, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_ULT_D |
| 5406 | { 1279, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_ULE_S_MMR6 |
| 5407 | { 1278, 3, 1, 4, 52, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_ULE_S |
| 5408 | { 1277, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_ULE_D_MMR6 |
| 5409 | { 1276, 3, 1, 4, 52, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_ULE_D |
| 5410 | { 1275, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_UEQ_S_MMR6 |
| 5411 | { 1274, 3, 1, 4, 47, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_UEQ_S |
| 5412 | { 1273, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_UEQ_D_MMR6 |
| 5413 | { 1272, 3, 1, 4, 47, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_UEQ_D |
| 5414 | { 1271, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUN_S_MMR6 |
| 5415 | { 1270, 3, 1, 4, 61, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUN_S |
| 5416 | { 1269, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUN_D_MMR6 |
| 5417 | { 1268, 3, 1, 4, 61, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUN_D |
| 5418 | { 1267, 3, 1, 4, 408, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULT_S_MMR6 |
| 5419 | { 1266, 3, 1, 4, 60, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULT_S |
| 5420 | { 1265, 3, 1, 4, 408, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULT_D_MMR6 |
| 5421 | { 1264, 3, 1, 4, 60, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULT_D |
| 5422 | { 1263, 3, 1, 4, 408, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULE_S_MMR6 |
| 5423 | { 1262, 3, 1, 4, 59, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULE_S |
| 5424 | { 1261, 3, 1, 4, 408, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULE_D_MMR6 |
| 5425 | { 1260, 3, 1, 4, 59, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULE_D |
| 5426 | { 1259, 3, 1, 4, 408, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUEQ_S_MMR6 |
| 5427 | { 1258, 3, 1, 4, 58, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUEQ_S |
| 5428 | { 1257, 3, 1, 4, 408, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUEQ_D_MMR6 |
| 5429 | { 1256, 3, 1, 4, 58, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUEQ_D |
| 5430 | { 1255, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLT_S_MMR6 |
| 5431 | { 1254, 3, 1, 4, 57, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLT_S |
| 5432 | { 1253, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLT_D_MMR6 |
| 5433 | { 1252, 3, 1, 4, 57, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLT_D |
| 5434 | { 1251, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLE_S_MMR6 |
| 5435 | { 1250, 3, 1, 4, 56, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLE_S |
| 5436 | { 1249, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLE_D_MMR6 |
| 5437 | { 1248, 3, 1, 4, 56, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLE_D |
| 5438 | { 1247, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SEQ_S_MMR6 |
| 5439 | { 1246, 3, 1, 4, 55, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SEQ_S |
| 5440 | { 1245, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SEQ_D_MMR6 |
| 5441 | { 1244, 3, 1, 4, 55, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SEQ_D |
| 5442 | { 1243, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SAF_S_MMR6 |
| 5443 | { 1242, 3, 1, 4, 54, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SAF_S |
| 5444 | { 1241, 3, 1, 4, 407, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SAF_D_MMR6 |
| 5445 | { 1240, 3, 1, 4, 54, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SAF_D |
| 5446 | { 1239, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_LT_S_MMR6 |
| 5447 | { 1238, 3, 1, 4, 49, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_LT_S |
| 5448 | { 1237, 2, 0, 4, 611, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_LT_PH_MM |
| 5449 | { 1236, 2, 0, 4, 460, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_LT_PH |
| 5450 | { 1235, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_LT_D_MMR6 |
| 5451 | { 1234, 3, 1, 4, 49, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_LT_D |
| 5452 | { 1233, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_LE_S_MMR6 |
| 5453 | { 1232, 3, 1, 4, 51, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_LE_S |
| 5454 | { 1231, 2, 0, 4, 610, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_LE_PH_MM |
| 5455 | { 1230, 2, 0, 4, 459, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_LE_PH |
| 5456 | { 1229, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_LE_D_MMR6 |
| 5457 | { 1228, 3, 1, 4, 51, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_LE_D |
| 5458 | { 1227, 3, 1, 4, 53, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_F_S |
| 5459 | { 1226, 3, 1, 4, 53, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_F_D |
| 5460 | { 1225, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_EQ_S_MMR6 |
| 5461 | { 1224, 3, 1, 4, 48, 0, 0, MipsOpInfoBase + 660, 0, 0, 0x16ULL }, // CMP_EQ_S |
| 5462 | { 1223, 2, 0, 4, 609, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_EQ_PH_MM |
| 5463 | { 1222, 2, 0, 4, 458, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_EQ_PH |
| 5464 | { 1221, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_EQ_D_MMR6 |
| 5465 | { 1220, 3, 1, 4, 48, 0, 0, MipsOpInfoBase + 657, 0, 0, 0x16ULL }, // CMP_EQ_D |
| 5466 | { 1219, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 660, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_AF_S_MMR6 |
| 5467 | { 1218, 3, 1, 4, 406, 0, 0, MipsOpInfoBase + 657, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_AF_D_MMR6 |
| 5468 | { 1217, 2, 0, 4, 608, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_LT_QB_MM |
| 5469 | { 1216, 2, 0, 4, 457, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_LT_QB |
| 5470 | { 1215, 2, 0, 4, 607, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_LE_QB_MM |
| 5471 | { 1214, 2, 0, 4, 456, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_LE_QB |
| 5472 | { 1213, 2, 0, 4, 606, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_EQ_QB_MM |
| 5473 | { 1212, 2, 0, 4, 455, 0, 1, MipsOpInfoBase + 526, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_EQ_QB |
| 5474 | { 1211, 3, 1, 4, 605, 0, 0, MipsOpInfoBase + 654, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_LT_QB_MM |
| 5475 | { 1210, 3, 1, 4, 454, 0, 0, MipsOpInfoBase + 654, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_LT_QB |
| 5476 | { 1209, 3, 1, 4, 604, 0, 0, MipsOpInfoBase + 654, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_LE_QB_MM |
| 5477 | { 1208, 3, 1, 4, 453, 0, 0, MipsOpInfoBase + 654, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_LE_QB |
| 5478 | { 1207, 3, 1, 4, 603, 0, 0, MipsOpInfoBase + 654, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_EQ_QB_MM |
| 5479 | { 1206, 3, 1, 4, 452, 0, 0, MipsOpInfoBase + 654, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_EQ_QB |
| 5480 | { 1205, 3, 1, 4, 721, 0, 1, MipsOpInfoBase + 654, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_LT_QB_MMR2 |
| 5481 | { 1204, 3, 1, 4, 557, 0, 1, MipsOpInfoBase + 654, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_LT_QB |
| 5482 | { 1203, 3, 1, 4, 720, 0, 1, MipsOpInfoBase + 654, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_LE_QB_MMR2 |
| 5483 | { 1202, 3, 1, 4, 556, 0, 1, MipsOpInfoBase + 654, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_LE_QB |
| 5484 | { 1201, 3, 1, 4, 719, 0, 1, MipsOpInfoBase + 654, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_EQ_QB_MMR2 |
| 5485 | { 1200, 3, 1, 4, 555, 0, 1, MipsOpInfoBase + 654, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_EQ_QB |
| 5486 | { 1199, 2, 1, 4, 234, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x6ULL }, // CLZ_R6 |
| 5487 | { 1198, 2, 1, 4, 238, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLZ_MMR6 |
| 5488 | { 1197, 2, 1, 4, 237, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // CLZ_MM |
| 5489 | { 1196, 2, 1, 4, 230, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // CLZ |
| 5490 | { 1195, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // CLT_U_W |
| 5491 | { 1194, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // CLT_U_H |
| 5492 | { 1193, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // CLT_U_D |
| 5493 | { 1192, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // CLT_U_B |
| 5494 | { 1191, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // CLT_S_W |
| 5495 | { 1190, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // CLT_S_H |
| 5496 | { 1189, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // CLT_S_D |
| 5497 | { 1188, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // CLT_S_B |
| 5498 | { 1187, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // CLTI_U_W |
| 5499 | { 1186, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CLTI_U_H |
| 5500 | { 1185, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // CLTI_U_D |
| 5501 | { 1184, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // CLTI_U_B |
| 5502 | { 1183, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // CLTI_S_W |
| 5503 | { 1182, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CLTI_S_H |
| 5504 | { 1181, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // CLTI_S_D |
| 5505 | { 1180, 3, 1, 4, 136, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // CLTI_S_B |
| 5506 | { 1179, 2, 1, 4, 234, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x6ULL }, // CLO_R6 |
| 5507 | { 1178, 2, 1, 4, 238, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLO_MMR6 |
| 5508 | { 1177, 2, 1, 4, 237, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // CLO_MM |
| 5509 | { 1176, 2, 1, 4, 230, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x1ULL }, // CLO |
| 5510 | { 1175, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // CLE_U_W |
| 5511 | { 1174, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // CLE_U_H |
| 5512 | { 1173, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // CLE_U_D |
| 5513 | { 1172, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // CLE_U_B |
| 5514 | { 1171, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // CLE_S_W |
| 5515 | { 1170, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // CLE_S_H |
| 5516 | { 1169, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // CLE_S_D |
| 5517 | { 1168, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // CLE_S_B |
| 5518 | { 1167, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // CLEI_U_W |
| 5519 | { 1166, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CLEI_U_H |
| 5520 | { 1165, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // CLEI_U_D |
| 5521 | { 1164, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // CLEI_U_B |
| 5522 | { 1163, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // CLEI_S_W |
| 5523 | { 1162, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CLEI_S_H |
| 5524 | { 1161, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // CLEI_S_D |
| 5525 | { 1160, 3, 1, 4, 137, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // CLEI_S_B |
| 5526 | { 1159, 2, 1, 4, 414, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLASS_S_MMR6 |
| 5527 | { 1158, 2, 1, 4, 11, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLASS_S |
| 5528 | { 1157, 2, 1, 4, 414, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLASS_D_MMR6 |
| 5529 | { 1156, 2, 1, 4, 11, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLASS_D |
| 5530 | { 1155, 4, 1, 4, 375, 0, 0, MipsOpInfoBase + 650, 0, 0, 0x1ULL }, // CINS_i32 |
| 5531 | { 1154, 4, 1, 4, 375, 0, 0, MipsOpInfoBase + 646, 0, 0, 0x1ULL }, // CINS64_32 |
| 5532 | { 1153, 4, 1, 4, 375, 0, 0, MipsOpInfoBase + 642, 0, 0, 0x1ULL }, // CINS32 |
| 5533 | { 1152, 4, 1, 4, 375, 0, 0, MipsOpInfoBase + 642, 0, 0, 0x1ULL }, // CINS |
| 5534 | { 1151, 2, 1, 4, 124, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CFCMSA |
| 5535 | { 1150, 2, 1, 4, 327, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CFC2_MM |
| 5536 | { 1149, 2, 1, 4, 403, 0, 0, MipsOpInfoBase + 636, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CFC1_MM |
| 5537 | { 1148, 2, 1, 4, 218, 0, 0, MipsOpInfoBase + 636, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CFC1 |
| 5538 | { 1147, 3, 1, 4, 138, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // CEQ_W |
| 5539 | { 1146, 3, 1, 4, 138, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // CEQ_H |
| 5540 | { 1145, 3, 1, 4, 138, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // CEQ_D |
| 5541 | { 1144, 3, 1, 4, 138, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // CEQ_B |
| 5542 | { 1143, 3, 1, 4, 138, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // CEQI_W |
| 5543 | { 1142, 3, 1, 4, 138, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CEQI_H |
| 5544 | { 1141, 3, 1, 4, 138, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // CEQI_D |
| 5545 | { 1140, 3, 1, 4, 138, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // CEQI_B |
| 5546 | { 1139, 2, 1, 4, 413, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_S_MMR6 |
| 5547 | { 1138, 2, 1, 4, 388, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_S_MM |
| 5548 | { 1137, 2, 1, 4, 225, 0, 0, MipsOpInfoBase + 634, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_S |
| 5549 | { 1136, 2, 1, 4, 388, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_MM |
| 5550 | { 1135, 2, 1, 4, 413, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_D_MMR6 |
| 5551 | { 1134, 2, 1, 4, 225, 0, 0, MipsOpInfoBase + 632, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_D64 |
| 5552 | { 1133, 2, 1, 4, 225, 0, 0, MipsOpInfoBase + 630, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_D32 |
| 5553 | { 1132, 2, 1, 4, 413, 0, 0, MipsOpInfoBase + 628, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_L_S_MMR6 |
| 5554 | { 1131, 2, 1, 4, 225, 0, 0, MipsOpInfoBase + 628, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_L_S |
| 5555 | { 1130, 2, 1, 4, 413, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_L_D_MMR6 |
| 5556 | { 1129, 2, 1, 4, 225, 0, 0, MipsOpInfoBase + 626, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_L_D64 |
| 5557 | { 1128, 3, 0, 4, 344, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHE_R6 |
| 5558 | { 1127, 3, 0, 4, 364, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHE_MMR6 |
| 5559 | { 1126, 3, 0, 4, 357, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHE_MM |
| 5560 | { 1125, 3, 0, 4, 351, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHEE_MM |
| 5561 | { 1124, 3, 0, 4, 97, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHEE |
| 5562 | { 1123, 3, 0, 4, 340, 0, 0, MipsOpInfoBase + 623, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHE |
| 5563 | { 1122, 1, 0, 4, 289, 1, 0, MipsOpInfoBase + 0, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BtnezX16 |
| 5564 | { 1121, 1, 0, 2, 289, 1, 0, MipsOpInfoBase + 0, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Btnez16 |
| 5565 | { 1120, 1, 0, 4, 289, 1, 0, MipsOpInfoBase + 0, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BteqzX16 |
| 5566 | { 1119, 1, 0, 2, 289, 1, 0, MipsOpInfoBase + 0, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Bteqz16 |
| 5567 | { 1118, 0, 0, 2, 291, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Break16 |
| 5568 | { 1117, 2, 0, 4, 289, 0, 0, MipsOpInfoBase + 621, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BnezRxImmX16 |
| 5569 | { 1116, 2, 0, 2, 289, 0, 0, MipsOpInfoBase + 621, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // BnezRxImm16 |
| 5570 | { 1115, 1, 0, 4, 289, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BimmX16 |
| 5571 | { 1114, 1, 0, 2, 289, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Bimm16 |
| 5572 | { 1113, 2, 0, 4, 289, 0, 0, MipsOpInfoBase + 621, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BeqzRxImmX16 |
| 5573 | { 1112, 2, 0, 2, 289, 0, 0, MipsOpInfoBase + 621, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // BeqzRxImm16 |
| 5574 | { 1111, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 619, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_W |
| 5575 | { 1110, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 613, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_V |
| 5576 | { 1109, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 617, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_H |
| 5577 | { 1108, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 615, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_D |
| 5578 | { 1107, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 613, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_B |
| 5579 | { 1106, 3, 1, 4, 66, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // BSET_W |
| 5580 | { 1105, 3, 1, 4, 66, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // BSET_H |
| 5581 | { 1104, 3, 1, 4, 66, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // BSET_D |
| 5582 | { 1103, 3, 1, 4, 66, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // BSET_B |
| 5583 | { 1102, 3, 1, 4, 66, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // BSETI_W |
| 5584 | { 1101, 3, 1, 4, 66, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // BSETI_H |
| 5585 | { 1100, 3, 1, 4, 66, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // BSETI_D |
| 5586 | { 1099, 3, 1, 4, 66, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // BSETI_B |
| 5587 | { 1098, 4, 1, 4, 64, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // BSEL_V |
| 5588 | { 1097, 4, 1, 4, 64, 0, 0, MipsOpInfoBase + 593, 0, 0, 0x6ULL }, // BSELI_B |
| 5589 | { 1096, 2, 0, 4, 300, 0, 0, MipsOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BREAK_MMR6 |
| 5590 | { 1095, 2, 0, 4, 296, 0, 0, MipsOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BREAK_MM |
| 5591 | { 1094, 1, 0, 2, 300, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BREAK16_MMR6 |
| 5592 | { 1093, 1, 0, 2, 296, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BREAK16_MM |
| 5593 | { 1092, 2, 0, 4, 283, 0, 0, MipsOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BREAK |
| 5594 | { 1091, 1, 0, 4, 602, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BPOSGE32_MM |
| 5595 | { 1090, 1, 0, 4, 754, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BPOSGE32C_MMR3 |
| 5596 | { 1089, 1, 0, 4, 451, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BPOSGE32 |
| 5597 | { 1088, 3, 0, 4, 297, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BOVC_MMR6 |
| 5598 | { 1087, 3, 0, 4, 285, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BOVC |
| 5599 | { 1086, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 619, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_W |
| 5600 | { 1085, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 613, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_V |
| 5601 | { 1084, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 617, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_H |
| 5602 | { 1083, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 615, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_D |
| 5603 | { 1082, 2, 0, 4, 123, 0, 1, MipsOpInfoBase + 613, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_B |
| 5604 | { 1081, 3, 0, 4, 297, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BNVC_MMR6 |
| 5605 | { 1080, 3, 0, 4, 285, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNVC |
| 5606 | { 1079, 3, 0, 4, 293, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BNE_MM |
| 5607 | { 1078, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BNEZC_MMR6 |
| 5608 | { 1077, 2, 0, 4, 293, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // BNEZC_MM |
| 5609 | { 1076, 2, 0, 4, 305, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEZC64 |
| 5610 | { 1075, 2, 0, 2, 297, 0, 1, MipsOpInfoBase + 591, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BNEZC16_MMR6 |
| 5611 | { 1074, 2, 0, 4, 285, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEZC |
| 5612 | { 1073, 2, 0, 4, 298, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BNEZALC_MMR6 |
| 5613 | { 1072, 2, 0, 4, 284, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEZALC |
| 5614 | { 1071, 2, 0, 2, 293, 0, 1, MipsOpInfoBase + 591, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BNEZ16_MM |
| 5615 | { 1070, 3, 0, 4, 277, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BNEL |
| 5616 | { 1069, 3, 1, 4, 120, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // BNEG_W |
| 5617 | { 1068, 3, 1, 4, 120, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // BNEG_H |
| 5618 | { 1067, 3, 1, 4, 120, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // BNEG_D |
| 5619 | { 1066, 3, 1, 4, 120, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // BNEG_B |
| 5620 | { 1065, 3, 1, 4, 120, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // BNEGI_W |
| 5621 | { 1064, 3, 1, 4, 120, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // BNEGI_H |
| 5622 | { 1063, 3, 1, 4, 120, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // BNEGI_D |
| 5623 | { 1062, 3, 1, 4, 120, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // BNEGI_B |
| 5624 | { 1061, 3, 0, 4, 297, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BNEC_MMR6 |
| 5625 | { 1060, 3, 0, 4, 305, 0, 1, MipsOpInfoBase + 350, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEC64 |
| 5626 | { 1059, 3, 0, 4, 285, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEC |
| 5627 | { 1058, 3, 0, 4, 301, 0, 1, MipsOpInfoBase + 350, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BNE64 |
| 5628 | { 1057, 3, 0, 4, 273, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BNE |
| 5629 | { 1056, 4, 1, 4, 121, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // BMZ_V |
| 5630 | { 1055, 4, 1, 4, 121, 0, 0, MipsOpInfoBase + 593, 0, 0, 0x6ULL }, // BMZI_B |
| 5631 | { 1054, 4, 1, 4, 121, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // BMNZ_V |
| 5632 | { 1053, 4, 1, 4, 121, 0, 0, MipsOpInfoBase + 593, 0, 0, 0x6ULL }, // BMNZI_B |
| 5633 | { 1052, 2, 0, 4, 293, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLTZ_MM |
| 5634 | { 1051, 2, 0, 4, 277, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLTZL |
| 5635 | { 1050, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLTZC_MMR6 |
| 5636 | { 1049, 2, 0, 4, 305, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTZC64 |
| 5637 | { 1048, 2, 0, 4, 285, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTZC |
| 5638 | { 1047, 2, 0, 4, 294, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLTZAL_MM |
| 5639 | { 1046, 2, 0, 4, 294, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // BLTZALS_MM |
| 5640 | { 1045, 2, 0, 4, 282, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLTZALL |
| 5641 | { 1044, 2, 0, 4, 298, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLTZALC_MMR6 |
| 5642 | { 1043, 2, 0, 4, 284, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BLTZALC |
| 5643 | { 1042, 2, 0, 4, 274, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLTZAL |
| 5644 | { 1041, 2, 0, 4, 301, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLTZ64 |
| 5645 | { 1040, 2, 0, 4, 273, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLTZ |
| 5646 | { 1039, 3, 0, 4, 297, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLTUC_MMR6 |
| 5647 | { 1038, 3, 0, 4, 305, 0, 1, MipsOpInfoBase + 350, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTUC64 |
| 5648 | { 1037, 3, 0, 4, 285, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTUC |
| 5649 | { 1036, 3, 0, 4, 297, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLTC_MMR6 |
| 5650 | { 1035, 3, 0, 4, 305, 0, 1, MipsOpInfoBase + 350, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTC64 |
| 5651 | { 1034, 3, 0, 4, 285, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTC |
| 5652 | { 1033, 2, 0, 4, 293, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLEZ_MM |
| 5653 | { 1032, 2, 0, 4, 277, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLEZL |
| 5654 | { 1031, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLEZC_MMR6 |
| 5655 | { 1030, 2, 0, 4, 305, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLEZC64 |
| 5656 | { 1029, 2, 0, 4, 285, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLEZC |
| 5657 | { 1028, 2, 0, 4, 298, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLEZALC_MMR6 |
| 5658 | { 1027, 2, 0, 4, 284, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BLEZALC |
| 5659 | { 1026, 2, 0, 4, 301, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLEZ64 |
| 5660 | { 1025, 2, 0, 4, 273, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLEZ |
| 5661 | { 1024, 2, 1, 4, 238, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BITSWAP_MMR6 |
| 5662 | { 1023, 2, 1, 4, 234, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BITSWAP |
| 5663 | { 1022, 2, 1, 4, 601, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x6ULL }, // BITREV_MM |
| 5664 | { 1021, 2, 1, 4, 450, 0, 0, MipsOpInfoBase + 151, 0, 0, 0x6ULL }, // BITREV |
| 5665 | { 1020, 4, 1, 4, 115, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // BINSR_W |
| 5666 | { 1019, 4, 1, 4, 115, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // BINSR_H |
| 5667 | { 1018, 4, 1, 4, 115, 0, 0, MipsOpInfoBase + 197, 0, 0, 0x6ULL }, // BINSR_D |
| 5668 | { 1017, 4, 1, 4, 115, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // BINSR_B |
| 5669 | { 1016, 4, 1, 4, 115, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // BINSRI_W |
| 5670 | { 1015, 4, 1, 4, 115, 0, 0, MipsOpInfoBase + 601, 0, 0, 0x6ULL }, // BINSRI_H |
| 5671 | { 1014, 4, 1, 4, 115, 0, 0, MipsOpInfoBase + 597, 0, 0, 0x6ULL }, // BINSRI_D |
| 5672 | { 1013, 4, 1, 4, 115, 0, 0, MipsOpInfoBase + 593, 0, 0, 0x6ULL }, // BINSRI_B |
| 5673 | { 1012, 4, 1, 4, 114, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // BINSL_W |
| 5674 | { 1011, 4, 1, 4, 114, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // BINSL_H |
| 5675 | { 1010, 4, 1, 4, 114, 0, 0, MipsOpInfoBase + 197, 0, 0, 0x6ULL }, // BINSL_D |
| 5676 | { 1009, 4, 1, 4, 114, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // BINSL_B |
| 5677 | { 1008, 4, 1, 4, 114, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // BINSLI_W |
| 5678 | { 1007, 4, 1, 4, 114, 0, 0, MipsOpInfoBase + 601, 0, 0, 0x6ULL }, // BINSLI_H |
| 5679 | { 1006, 4, 1, 4, 114, 0, 0, MipsOpInfoBase + 597, 0, 0, 0x6ULL }, // BINSLI_D |
| 5680 | { 1005, 4, 1, 4, 114, 0, 0, MipsOpInfoBase + 593, 0, 0, 0x6ULL }, // BINSLI_B |
| 5681 | { 1004, 2, 0, 4, 293, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGTZ_MM |
| 5682 | { 1003, 2, 0, 4, 277, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGTZL |
| 5683 | { 1002, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGTZC_MMR6 |
| 5684 | { 1001, 2, 0, 4, 305, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGTZC64 |
| 5685 | { 1000, 2, 0, 4, 285, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGTZC |
| 5686 | { 999, 2, 0, 4, 298, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGTZALC_MMR6 |
| 5687 | { 998, 2, 0, 4, 284, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BGTZALC |
| 5688 | { 997, 2, 0, 4, 301, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGTZ64 |
| 5689 | { 996, 2, 0, 4, 273, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGTZ |
| 5690 | { 995, 2, 0, 4, 293, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGEZ_MM |
| 5691 | { 994, 2, 0, 4, 277, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGEZL |
| 5692 | { 993, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGEZC_MMR6 |
| 5693 | { 992, 2, 0, 4, 305, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEZC64 |
| 5694 | { 991, 2, 0, 4, 285, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEZC |
| 5695 | { 990, 2, 0, 4, 294, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGEZAL_MM |
| 5696 | { 989, 2, 0, 4, 294, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // BGEZALS_MM |
| 5697 | { 988, 2, 0, 4, 282, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGEZALL |
| 5698 | { 987, 2, 0, 4, 298, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGEZALC_MMR6 |
| 5699 | { 986, 2, 0, 4, 284, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BGEZALC |
| 5700 | { 985, 2, 0, 4, 280, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGEZAL |
| 5701 | { 984, 2, 0, 4, 301, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGEZ64 |
| 5702 | { 983, 2, 0, 4, 273, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGEZ |
| 5703 | { 982, 3, 0, 4, 297, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGEUC_MMR6 |
| 5704 | { 981, 3, 0, 4, 305, 0, 1, MipsOpInfoBase + 350, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEUC64 |
| 5705 | { 980, 3, 0, 4, 285, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEUC |
| 5706 | { 979, 3, 0, 4, 297, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGEC_MMR6 |
| 5707 | { 978, 3, 0, 4, 305, 0, 1, MipsOpInfoBase + 350, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEC64 |
| 5708 | { 977, 3, 0, 4, 285, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEC |
| 5709 | { 976, 3, 0, 4, 293, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BEQ_MM |
| 5710 | { 975, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BEQZC_MMR6 |
| 5711 | { 974, 2, 0, 4, 293, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // BEQZC_MM |
| 5712 | { 973, 2, 0, 4, 305, 0, 1, MipsOpInfoBase + 358, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQZC64 |
| 5713 | { 972, 2, 0, 2, 297, 0, 1, MipsOpInfoBase + 591, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BEQZC16_MMR6 |
| 5714 | { 971, 2, 0, 4, 285, 0, 1, MipsOpInfoBase + 356, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQZC |
| 5715 | { 970, 2, 0, 4, 298, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BEQZALC_MMR6 |
| 5716 | { 969, 2, 0, 4, 284, 0, 1, MipsOpInfoBase + 356, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQZALC |
| 5717 | { 968, 2, 0, 2, 293, 0, 1, MipsOpInfoBase + 591, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BEQZ16_MM |
| 5718 | { 967, 3, 0, 4, 277, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BEQL |
| 5719 | { 966, 3, 0, 4, 297, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BEQC_MMR6 |
| 5720 | { 965, 3, 0, 4, 305, 0, 1, MipsOpInfoBase + 350, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQC64 |
| 5721 | { 964, 3, 0, 4, 285, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQC |
| 5722 | { 963, 3, 0, 4, 301, 0, 1, MipsOpInfoBase + 350, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BEQ64 |
| 5723 | { 962, 3, 0, 4, 273, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BEQ |
| 5724 | { 961, 1, 0, 4, 297, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL }, // BC_MMR6 |
| 5725 | { 960, 3, 1, 4, 118, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // BCLR_W |
| 5726 | { 959, 3, 1, 4, 118, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // BCLR_H |
| 5727 | { 958, 3, 1, 4, 118, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // BCLR_D |
| 5728 | { 957, 3, 1, 4, 118, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // BCLR_B |
| 5729 | { 956, 3, 1, 4, 118, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // BCLRI_W |
| 5730 | { 955, 3, 1, 4, 118, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // BCLRI_H |
| 5731 | { 954, 3, 1, 4, 118, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // BCLRI_D |
| 5732 | { 953, 3, 1, 4, 118, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // BCLRI_B |
| 5733 | { 952, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 589, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC2NEZC_MMR6 |
| 5734 | { 951, 2, 0, 4, 285, 0, 0, MipsOpInfoBase + 589, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC2NEZ |
| 5735 | { 950, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 589, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC2EQZC_MMR6 |
| 5736 | { 949, 2, 0, 4, 285, 0, 0, MipsOpInfoBase + 589, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC2EQZ |
| 5737 | { 948, 2, 0, 4, 293, 0, 1, MipsOpInfoBase + 587, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // BC1T_MM |
| 5738 | { 947, 2, 0, 4, 378, 0, 1, MipsOpInfoBase + 587, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // BC1TL |
| 5739 | { 946, 2, 0, 4, 378, 0, 1, MipsOpInfoBase + 587, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // BC1T |
| 5740 | { 945, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 585, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BC1NEZC_MMR6 |
| 5741 | { 944, 2, 0, 4, 6, 0, 0, MipsOpInfoBase + 585, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC1NEZ |
| 5742 | { 943, 2, 0, 4, 293, 0, 1, MipsOpInfoBase + 587, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // BC1F_MM |
| 5743 | { 942, 2, 0, 4, 378, 0, 1, MipsOpInfoBase + 587, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // BC1FL |
| 5744 | { 941, 2, 0, 4, 378, 0, 1, MipsOpInfoBase + 587, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // BC1F |
| 5745 | { 940, 2, 0, 4, 297, 0, 1, MipsOpInfoBase + 585, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BC1EQZC_MMR6 |
| 5746 | { 939, 2, 0, 4, 6, 0, 0, MipsOpInfoBase + 585, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC1EQZ |
| 5747 | { 938, 1, 0, 2, 297, 0, 1, MipsOpInfoBase + 189, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BC16_MMR6 |
| 5748 | { 937, 1, 0, 4, 285, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC |
| 5749 | { 936, 3, 0, 4, 375, 0, 1, MipsOpInfoBase + 582, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // BBIT132 |
| 5750 | { 935, 3, 0, 4, 375, 0, 1, MipsOpInfoBase + 582, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // BBIT1 |
| 5751 | { 934, 3, 0, 4, 375, 0, 1, MipsOpInfoBase + 582, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // BBIT032 |
| 5752 | { 933, 3, 0, 4, 375, 0, 1, MipsOpInfoBase + 582, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // BBIT0 |
| 5753 | { 932, 4, 1, 4, 718, 0, 0, MipsOpInfoBase + 567, 0, 0, 0x6ULL }, // BALIGN_MMR2 |
| 5754 | { 931, 4, 1, 4, 554, 0, 0, MipsOpInfoBase + 567, 0, 0, 0x6ULL }, // BALIGN |
| 5755 | { 930, 1, 0, 4, 298, 0, 1, MipsOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BALC_MMR6 |
| 5756 | { 929, 1, 0, 4, 284, 0, 1, MipsOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BALC |
| 5757 | { 928, 1, 0, 4, 273, 0, 1, MipsOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BAL |
| 5758 | { 927, 3, 1, 4, 375, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // BADDu |
| 5759 | { 926, 1, 0, 2, 293, 0, 1, MipsOpInfoBase + 189, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // B16_MM |
| 5760 | { 925, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 579, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // AndRxRxRy16 |
| 5761 | { 924, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 399, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // AdduRxRyRz16 |
| 5762 | { 923, 1, 0, 4, 235, 1, 1, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AddiuSpImmX16 |
| 5763 | { 922, 1, 0, 2, 235, 1, 1, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AddiuSpImm16 |
| 5764 | { 921, 3, 1, 4, 235, 0, 0, MipsOpInfoBase + 576, 0, 0, 0x0ULL }, // AddiuRxRyOffMemX16 |
| 5765 | { 920, 3, 1, 4, 235, 0, 0, MipsOpInfoBase + 573, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // AddiuRxRxImmX16 |
| 5766 | { 919, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 573, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // AddiuRxRxImm16 |
| 5767 | { 918, 2, 1, 4, 235, 0, 0, MipsOpInfoBase + 571, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AddiuRxPcImmX16 |
| 5768 | { 917, 2, 1, 4, 235, 0, 0, MipsOpInfoBase + 571, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AddiuRxImmX16 |
| 5769 | { 916, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_U_W |
| 5770 | { 915, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_U_H |
| 5771 | { 914, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_U_D |
| 5772 | { 913, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_U_B |
| 5773 | { 912, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_S_W |
| 5774 | { 911, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_S_H |
| 5775 | { 910, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_S_D |
| 5776 | { 909, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_S_B |
| 5777 | { 908, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_U_W |
| 5778 | { 907, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_U_H |
| 5779 | { 906, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_U_D |
| 5780 | { 905, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_U_B |
| 5781 | { 904, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_S_W |
| 5782 | { 903, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_S_H |
| 5783 | { 902, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_S_D |
| 5784 | { 901, 3, 1, 4, 131, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_S_B |
| 5785 | { 900, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // AUI_MMR6 |
| 5786 | { 899, 2, 1, 4, 238, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // AUIPC_MMR6 |
| 5787 | { 898, 2, 1, 4, 234, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // AUIPC |
| 5788 | { 897, 3, 1, 4, 234, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // AUI |
| 5789 | { 896, 3, 1, 4, 19, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // ASUB_U_W |
| 5790 | { 895, 3, 1, 4, 19, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // ASUB_U_H |
| 5791 | { 894, 3, 1, 4, 19, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // ASUB_U_D |
| 5792 | { 893, 3, 1, 4, 19, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // ASUB_U_B |
| 5793 | { 892, 3, 1, 4, 18, 0, 0, MipsOpInfoBase + 159, 0, 0, 0x6ULL }, // ASUB_S_W |
| 5794 | { 891, 3, 1, 4, 18, 0, 0, MipsOpInfoBase + 156, 0, 0, 0x6ULL }, // ASUB_S_H |
| 5795 | { 890, 3, 1, 4, 18, 0, 0, MipsOpInfoBase + 153, 0, 0, 0x6ULL }, // ASUB_S_D |
| 5796 | { 889, 3, 1, 4, 18, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // ASUB_S_B |
| 5797 | { 888, 4, 1, 4, 717, 0, 0, MipsOpInfoBase + 567, 0, 0, 0x6ULL }, // APPEND_MMR2 |
| 5798 | { 887, 4, 1, 4, 553, 0, 0, MipsOpInfoBase + 567, 0, 0, 0x6ULL }, // APPEND |
| 5799 | { 886, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ANDi_MM |
| 5800 | { 885, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ANDi64 |
| 5801 | { 884, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ANDi |
| 5802 | { 883, 3, 1, 4, 134, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x6ULL }, // AND_V |
| 5803 | { 882, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // AND_MMR6 |
| 5804 | { 881, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // AND_MM |
| 5805 | { 880, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ANDI_MMR6 |
| 5806 | { 879, 3, 1, 4, 25, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // ANDI_B |
| 5807 | { 878, 3, 1, 2, 238, 0, 0, MipsOpInfoBase + 530, 0, 0, 0x0ULL }, // ANDI16_MMR6 |
| 5808 | { 877, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 530, 0, 0, 0x0ULL }, // ANDI16_MM |
| 5809 | { 876, 3, 1, 4, 239, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // AND64 |
| 5810 | { 875, 3, 1, 2, 238, 0, 0, MipsOpInfoBase + 564, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AND16_MMR6 |
| 5811 | { 874, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 564, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // AND16_MM |
| 5812 | { 873, 3, 1, 4, 79, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // AND |
| 5813 | { 872, 2, 1, 4, 238, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ALUIPC_MMR6 |
| 5814 | { 871, 2, 1, 4, 234, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ALUIPC |
| 5815 | { 870, 4, 1, 4, 238, 0, 0, MipsOpInfoBase + 560, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ALIGN_MMR6 |
| 5816 | { 869, 4, 1, 4, 234, 0, 0, MipsOpInfoBase + 560, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ALIGN |
| 5817 | { 868, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // ADDu_MM |
| 5818 | { 867, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // ADDu |
| 5819 | { 866, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ADDiu_MM |
| 5820 | { 865, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // ADDiu |
| 5821 | { 864, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // ADDi_MM |
| 5822 | { 863, 3, 1, 4, 112, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // ADDi |
| 5823 | { 862, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADD_MMR6 |
| 5824 | { 861, 3, 1, 4, 237, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADD_MM |
| 5825 | { 860, 3, 1, 4, 128, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADD_A_W |
| 5826 | { 859, 3, 1, 4, 128, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADD_A_H |
| 5827 | { 858, 3, 1, 4, 128, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADD_A_D |
| 5828 | { 857, 3, 1, 4, 128, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADD_A_B |
| 5829 | { 856, 3, 1, 4, 600, 1, 1, MipsOpInfoBase + 240, 13, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDWC_MM |
| 5830 | { 855, 3, 1, 4, 449, 1, 1, MipsOpInfoBase + 240, 13, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDWC |
| 5831 | { 854, 3, 1, 4, 130, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDV_W |
| 5832 | { 853, 3, 1, 4, 130, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDV_H |
| 5833 | { 852, 3, 1, 4, 130, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDV_D |
| 5834 | { 851, 3, 1, 4, 130, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDV_B |
| 5835 | { 850, 3, 1, 4, 130, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x6ULL }, // ADDVI_W |
| 5836 | { 849, 3, 1, 4, 130, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // ADDVI_H |
| 5837 | { 848, 3, 1, 4, 130, 0, 0, MipsOpInfoBase + 551, 0, 0, 0x6ULL }, // ADDVI_D |
| 5838 | { 847, 3, 1, 4, 130, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // ADDVI_B |
| 5839 | { 846, 3, 1, 4, 599, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDU_S_QB_MM |
| 5840 | { 845, 3, 1, 4, 448, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDU_S_QB |
| 5841 | { 844, 3, 1, 4, 716, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_S_PH_MMR2 |
| 5842 | { 843, 3, 1, 4, 552, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_S_PH |
| 5843 | { 842, 3, 1, 4, 598, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_QB_MM |
| 5844 | { 841, 3, 1, 4, 447, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDU_QB |
| 5845 | { 840, 3, 1, 4, 715, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_PH_MMR2 |
| 5846 | { 839, 3, 1, 4, 551, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_PH |
| 5847 | { 838, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADDU_MMR6 |
| 5848 | { 837, 3, 1, 4, 714, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDUH_R_QB_MMR2 |
| 5849 | { 836, 3, 1, 4, 550, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDUH_R_QB |
| 5850 | { 835, 3, 1, 4, 713, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDUH_QB_MMR2 |
| 5851 | { 834, 3, 1, 4, 549, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDUH_QB |
| 5852 | { 833, 3, 1, 2, 238, 0, 0, MipsOpInfoBase + 545, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // ADDU16_MMR6 |
| 5853 | { 832, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 545, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // ADDU16_MM |
| 5854 | { 831, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_U_W |
| 5855 | { 830, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_U_H |
| 5856 | { 829, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_U_D |
| 5857 | { 828, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_U_B |
| 5858 | { 827, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_S_W |
| 5859 | { 826, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_S_H |
| 5860 | { 825, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_S_D |
| 5861 | { 824, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_S_B |
| 5862 | { 823, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_A_W |
| 5863 | { 822, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_A_H |
| 5864 | { 821, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_A_D |
| 5865 | { 820, 3, 1, 4, 129, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_A_B |
| 5866 | { 819, 3, 1, 4, 597, 0, 1, MipsOpInfoBase + 240, 12, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDSC_MM |
| 5867 | { 818, 3, 1, 4, 446, 0, 1, MipsOpInfoBase + 240, 12, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDSC |
| 5868 | { 817, 3, 1, 4, 382, 1, 0, MipsOpInfoBase + 539, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // ADDR_PS64 |
| 5869 | { 816, 3, 1, 4, 596, 0, 1, MipsOpInfoBase + 240, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDQ_S_W_MM |
| 5870 | { 815, 3, 1, 4, 445, 0, 1, MipsOpInfoBase + 240, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDQ_S_W |
| 5871 | { 814, 3, 1, 4, 595, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQ_S_PH_MM |
| 5872 | { 813, 3, 1, 4, 444, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQ_S_PH |
| 5873 | { 812, 3, 1, 4, 594, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDQ_PH_MM |
| 5874 | { 811, 3, 1, 4, 443, 0, 1, MipsOpInfoBase + 536, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQ_PH |
| 5875 | { 810, 3, 1, 4, 712, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_W_MMR2 |
| 5876 | { 809, 3, 1, 4, 548, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_W |
| 5877 | { 808, 3, 1, 4, 711, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_R_W_MMR2 |
| 5878 | { 807, 3, 1, 4, 547, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_R_W |
| 5879 | { 806, 3, 1, 4, 710, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_R_PH_MMR2 |
| 5880 | { 805, 3, 1, 4, 546, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_R_PH |
| 5881 | { 804, 3, 1, 4, 709, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_PH_MMR2 |
| 5882 | { 803, 3, 1, 4, 545, 0, 0, MipsOpInfoBase + 536, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_PH |
| 5883 | { 802, 3, 1, 4, 238, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ADDIU_MMR6 |
| 5884 | { 801, 1, 0, 2, 237, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDIUSP_MM |
| 5885 | { 800, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 533, 0, 0, 0x0ULL }, // ADDIUS5_MM |
| 5886 | { 799, 3, 1, 2, 237, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // ADDIUR2_MM |
| 5887 | { 798, 2, 1, 2, 237, 0, 0, MipsOpInfoBase + 528, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDIUR1SP_MM |
| 5888 | { 797, 2, 1, 4, 238, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDIUPC_MMR6 |
| 5889 | { 796, 2, 1, 4, 237, 0, 0, MipsOpInfoBase + 528, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADDIUPC_MM |
| 5890 | { 795, 2, 1, 4, 234, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDIUPC |
| 5891 | { 794, 3, 1, 4, 229, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADD |
| 5892 | { 793, 2, 1, 4, 593, 0, 1, MipsOpInfoBase + 151, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_W_MM |
| 5893 | { 792, 2, 1, 4, 442, 0, 1, MipsOpInfoBase + 151, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_W |
| 5894 | { 791, 2, 1, 4, 708, 0, 1, MipsOpInfoBase + 526, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_QB_MMR2 |
| 5895 | { 790, 2, 1, 4, 544, 0, 1, MipsOpInfoBase + 526, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_QB |
| 5896 | { 789, 2, 1, 4, 592, 0, 1, MipsOpInfoBase + 526, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_PH_MM |
| 5897 | { 788, 2, 1, 4, 441, 0, 1, MipsOpInfoBase + 526, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_PH |
| 5898 | { 787, 3, 1, 4, 28, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // XOR_V_W_PSEUDO |
| 5899 | { 786, 3, 1, 4, 28, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // XOR_V_H_PSEUDO |
| 5900 | { 785, 3, 1, 4, 28, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // XOR_V_D_PSEUDO |
| 5901 | { 784, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Usw |
| 5902 | { 783, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Ush |
| 5903 | { 782, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Ulw |
| 5904 | { 781, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Ulhu |
| 5905 | { 780, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Ulh |
| 5906 | { 779, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // URemMacro |
| 5907 | { 778, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // URemIMacro |
| 5908 | { 777, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDivMacro |
| 5909 | { 776, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDivIMacro |
| 5910 | { 775, 3, 1, 4, 258, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIV_MM_Pseudo |
| 5911 | { 774, 0, 0, 4, 296, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAP_MM |
| 5912 | { 773, 0, 0, 4, 283, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAP |
| 5913 | { 772, 1, 0, 4, 299, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALL_MMR6 |
| 5914 | { 771, 1, 0, 4, 295, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALL_MM |
| 5915 | { 770, 1, 0, 4, 299, 0, 1, MipsOpInfoBase + 196, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREG_MMR6 |
| 5916 | { 769, 1, 0, 4, 295, 0, 1, MipsOpInfoBase + 196, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREG_MM |
| 5917 | { 768, 1, 0, 4, 303, 0, 1, MipsOpInfoBase + 320, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREGHB64 |
| 5918 | { 767, 1, 0, 4, 279, 0, 1, MipsOpInfoBase + 196, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREGHB |
| 5919 | { 766, 1, 0, 4, 303, 0, 1, MipsOpInfoBase + 320, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREG64 |
| 5920 | { 765, 1, 0, 4, 279, 0, 1, MipsOpInfoBase + 196, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREG |
| 5921 | { 764, 1, 0, 4, 287, 0, 1, MipsOpInfoBase + 196, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLR6REG |
| 5922 | { 763, 1, 0, 4, 287, 0, 1, MipsOpInfoBase + 196, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLHBR6REG |
| 5923 | { 762, 1, 0, 4, 308, 0, 1, MipsOpInfoBase + 320, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLHB64R6REG |
| 5924 | { 761, 1, 0, 4, 308, 0, 1, MipsOpInfoBase + 320, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALL64R6REG |
| 5925 | { 760, 1, 0, 4, 278, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALL |
| 5926 | { 759, 3, 1, 2, 235, 0, 1, MipsOpInfoBase + 399, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltuRxRyRz16 |
| 5927 | { 758, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 399, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SltuCCRxRy16 |
| 5928 | { 757, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 523, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SltiuCCRxImmX16 |
| 5929 | { 756, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 523, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SltiCCRxImmX16 |
| 5930 | { 755, 3, 1, 2, 235, 0, 0, MipsOpInfoBase + 399, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SltCCRxRy16 |
| 5931 | { 754, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZSltu |
| 5932 | { 753, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 518, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SelTBtneZSltiu |
| 5933 | { 752, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 518, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZSlti |
| 5934 | { 751, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZSlt |
| 5935 | { 750, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 518, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZCmpi |
| 5936 | { 749, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZCmp |
| 5937 | { 748, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBteqZSltu |
| 5938 | { 747, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 518, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SelTBteqZSltiu |
| 5939 | { 746, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 518, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SelTBteqZSlti |
| 5940 | { 745, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBteqZSlt |
| 5941 | { 744, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 518, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBteqZCmpi |
| 5942 | { 743, 5, 1, 2, 292, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBteqZCmp |
| 5943 | { 742, 4, 1, 2, 292, 0, 0, MipsOpInfoBase + 509, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelBneZ |
| 5944 | { 741, 4, 1, 2, 292, 0, 0, MipsOpInfoBase + 509, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelBeqZ |
| 5945 | { 740, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SaadAddr |
| 5946 | { 739, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SaaAddr |
| 5947 | { 738, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 507, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_W_PSEUDO |
| 5948 | { 737, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 501, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_V_PSEUDO |
| 5949 | { 736, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 505, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_H_PSEUDO |
| 5950 | { 735, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 503, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_D_PSEUDO |
| 5951 | { 734, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 501, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_B_PSEUDO |
| 5952 | { 733, 3, 0, 4, 355, 0, 0, MipsOpInfoBase + 360, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWM_MM |
| 5953 | { 732, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 327, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STR_W |
| 5954 | { 731, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 324, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STR_D |
| 5955 | { 730, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 339, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // STORE_CCOND_DSP |
| 5956 | { 729, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 336, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // STORE_ACC64DSP |
| 5957 | { 728, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 333, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // STORE_ACC64 |
| 5958 | { 727, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 330, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // STORE_ACC128 |
| 5959 | { 726, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SRemMacro |
| 5960 | { 725, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SRemIMacro |
| 5961 | { 724, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 507, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_W_PSEUDO |
| 5962 | { 723, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 501, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_V_PSEUDO |
| 5963 | { 722, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 505, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_H_PSEUDO |
| 5964 | { 721, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 503, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_D_PSEUDO |
| 5965 | { 720, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 501, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_B_PSEUDO |
| 5966 | { 719, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SNEMacro |
| 5967 | { 718, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SNEIMacro |
| 5968 | { 717, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLTUImm64 |
| 5969 | { 716, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLTImm64 |
| 5970 | { 715, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEUImm64 |
| 5971 | { 714, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEUImm |
| 5972 | { 713, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEU |
| 5973 | { 712, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEImm64 |
| 5974 | { 711, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEImm |
| 5975 | { 710, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLE |
| 5976 | { 709, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGTUImm64 |
| 5977 | { 708, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGTUImm |
| 5978 | { 707, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGTImm64 |
| 5979 | { 706, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGTImm |
| 5980 | { 705, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEUImm64 |
| 5981 | { 704, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEUImm |
| 5982 | { 703, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEU |
| 5983 | { 702, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEImm64 |
| 5984 | { 701, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEImm |
| 5985 | { 700, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGE |
| 5986 | { 699, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEQMacro |
| 5987 | { 698, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEQIMacro |
| 5988 | { 697, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 498, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDivMacro |
| 5989 | { 696, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDivIMacro |
| 5990 | { 695, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDMacro |
| 5991 | { 694, 3, 1, 4, 257, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIV_MM_Pseudo |
| 5992 | { 693, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 495, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDC1_M1 |
| 5993 | { 692, 0, 0, 2, 289, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL }, // RetRA16 |
| 5994 | { 691, 0, 0, 4, 278, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // RetRA |
| 5995 | { 690, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RORImm |
| 5996 | { 689, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ROR |
| 5997 | { 688, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ROLImm |
| 5998 | { 687, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ROL |
| 5999 | { 686, 3, 1, 4, 106, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoUDIV |
| 6000 | { 685, 3, 1, 4, 383, 0, 0, MipsOpInfoBase + 492, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoTRUNC_W_S |
| 6001 | { 684, 3, 1, 4, 383, 0, 0, MipsOpInfoBase + 489, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoTRUNC_W_D32 |
| 6002 | { 683, 3, 1, 4, 383, 0, 0, MipsOpInfoBase + 486, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoTRUNC_W_D |
| 6003 | { 682, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 482, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_S |
| 6004 | { 681, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 478, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_I64 |
| 6005 | { 680, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 474, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_I |
| 6006 | { 679, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 470, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_D64 |
| 6007 | { 678, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 466, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_D32 |
| 6008 | { 677, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 462, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_S |
| 6009 | { 676, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 458, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_I64 |
| 6010 | { 675, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 454, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_I |
| 6011 | { 674, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 450, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_D64 |
| 6012 | { 673, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 446, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_D32 |
| 6013 | { 672, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 462, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_S |
| 6014 | { 671, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 458, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_I64 |
| 6015 | { 670, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 454, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_I |
| 6016 | { 669, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 450, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_D64 |
| 6017 | { 668, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 446, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_D32 |
| 6018 | { 667, 3, 1, 4, 104, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSDIV |
| 6019 | { 666, 1, 0, 4, 304, 0, 0, MipsOpInfoBase + 320, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // PseudoReturn64 |
| 6020 | { 665, 1, 0, 4, 278, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // PseudoReturn |
| 6021 | { 664, 4, 1, 4, 543, 0, 0, MipsOpInfoBase + 442, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoPICK_QB |
| 6022 | { 663, 4, 1, 4, 543, 0, 0, MipsOpInfoBase + 442, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoPICK_PH |
| 6023 | { 662, 3, 1, 4, 244, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoMULTu_MM |
| 6024 | { 661, 3, 1, 4, 246, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoMULTu |
| 6025 | { 660, 3, 1, 4, 244, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoMULT_MM |
| 6026 | { 659, 3, 1, 4, 246, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoMULT |
| 6027 | { 658, 3, 1, 4, 249, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMTLOHI_MM |
| 6028 | { 657, 3, 1, 4, 428, 0, 0, MipsOpInfoBase + 439, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMTLOHI_DSP |
| 6029 | { 656, 3, 1, 4, 268, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMTLOHI64 |
| 6030 | { 655, 3, 1, 4, 109, 0, 0, MipsOpInfoBase + 436, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMTLOHI |
| 6031 | { 654, 4, 1, 4, 244, 0, 0, MipsOpInfoBase + 428, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMSUB_MM |
| 6032 | { 653, 4, 1, 4, 244, 0, 0, MipsOpInfoBase + 428, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMSUBU_MM |
| 6033 | { 652, 4, 1, 4, 245, 0, 0, MipsOpInfoBase + 428, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMSUBU |
| 6034 | { 651, 4, 1, 4, 245, 0, 0, MipsOpInfoBase + 428, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMSUB |
| 6035 | { 650, 2, 1, 4, 247, 0, 0, MipsOpInfoBase + 432, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFLO_MM |
| 6036 | { 649, 2, 1, 4, 268, 0, 0, MipsOpInfoBase + 434, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFLO64 |
| 6037 | { 648, 2, 1, 4, 99, 0, 0, MipsOpInfoBase + 432, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFLO |
| 6038 | { 647, 2, 1, 4, 247, 0, 0, MipsOpInfoBase + 432, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFHI_MM |
| 6039 | { 646, 2, 1, 4, 268, 0, 0, MipsOpInfoBase + 434, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFHI64 |
| 6040 | { 645, 2, 1, 4, 99, 0, 0, MipsOpInfoBase + 432, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFHI |
| 6041 | { 644, 4, 1, 4, 244, 0, 0, MipsOpInfoBase + 428, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMADD_MM |
| 6042 | { 643, 4, 1, 4, 244, 0, 0, MipsOpInfoBase + 428, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMADDU_MM |
| 6043 | { 642, 4, 1, 4, 245, 0, 0, MipsOpInfoBase + 428, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMADDU |
| 6044 | { 641, 4, 1, 4, 245, 0, 0, MipsOpInfoBase + 428, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMADD |
| 6045 | { 640, 1, 0, 4, 285, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndrectHazardBranchR6 |
| 6046 | { 639, 1, 0, 4, 308, 0, 0, MipsOpInfoBase + 320, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndrectHazardBranch64R6 |
| 6047 | { 638, 1, 0, 4, 306, 0, 0, MipsOpInfoBase + 320, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectHazardBranch64 |
| 6048 | { 637, 1, 0, 4, 279, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectHazardBranch |
| 6049 | { 636, 1, 0, 4, 297, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch_MMR6 |
| 6050 | { 635, 1, 0, 4, 295, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch_MM |
| 6051 | { 634, 1, 0, 4, 285, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranchR6 |
| 6052 | { 633, 1, 0, 4, 308, 0, 0, MipsOpInfoBase + 320, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch64R6 |
| 6053 | { 632, 1, 0, 4, 306, 0, 0, MipsOpInfoBase + 320, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch64 |
| 6054 | { 631, 1, 0, 4, 279, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch |
| 6055 | { 630, 7, 2, 4, 0, 0, 0, MipsOpInfoBase + 421, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoD_SELECT_I64 |
| 6056 | { 629, 7, 2, 4, 0, 0, 0, MipsOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoD_SELECT_I |
| 6057 | { 628, 3, 1, 4, 267, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoDUDIV |
| 6058 | { 627, 3, 1, 4, 266, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoDSDIV |
| 6059 | { 626, 3, 1, 4, 265, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoDMULTu |
| 6060 | { 625, 3, 1, 4, 265, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoDMULT |
| 6061 | { 624, 2, 1, 4, 70, 0, 0, MipsOpInfoBase + 395, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_S_W |
| 6062 | { 623, 2, 1, 4, 70, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_S_L |
| 6063 | { 622, 2, 1, 4, 70, 0, 0, MipsOpInfoBase + 409, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_D64_W |
| 6064 | { 621, 2, 1, 4, 70, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_D64_L |
| 6065 | { 620, 2, 1, 4, 70, 0, 0, MipsOpInfoBase + 405, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_D32_W |
| 6066 | { 619, 3, 1, 4, 542, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMP_LT_PH |
| 6067 | { 618, 3, 1, 4, 542, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMP_LE_PH |
| 6068 | { 617, 3, 1, 4, 542, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMP_EQ_PH |
| 6069 | { 616, 3, 1, 4, 542, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMPU_LT_QB |
| 6070 | { 615, 3, 1, 4, 542, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMPU_LE_QB |
| 6071 | { 614, 3, 1, 4, 542, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMPU_EQ_QB |
| 6072 | { 613, 3, 1, 4, 27, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // OR_V_W_PSEUDO |
| 6073 | { 612, 3, 1, 4, 27, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // OR_V_H_PSEUDO |
| 6074 | { 611, 3, 1, 4, 27, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // OR_V_D_PSEUDO |
| 6075 | { 610, 3, 1, 4, 26, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // NOR_V_W_PSEUDO |
| 6076 | { 609, 3, 1, 4, 26, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // NOR_V_H_PSEUDO |
| 6077 | { 608, 3, 1, 4, 26, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // NOR_V_D_PSEUDO |
| 6078 | { 607, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NORImm64 |
| 6079 | { 606, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NORImm |
| 6080 | { 605, 0, 0, 4, 80, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NOP |
| 6081 | { 604, 3, 1, 2, 252, 0, 2, MipsOpInfoBase + 399, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // MultuRxRyRz16 |
| 6082 | { 603, 2, 0, 2, 252, 0, 2, MipsOpInfoBase + 397, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // MultuRxRy16 |
| 6083 | { 602, 3, 1, 2, 252, 0, 2, MipsOpInfoBase + 399, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // MultRxRyRz16 |
| 6084 | { 601, 2, 0, 2, 252, 0, 2, MipsOpInfoBase + 397, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // MultRxRy16 |
| 6085 | { 600, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULOUMacro |
| 6086 | { 599, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULOMacro |
| 6087 | { 598, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULImmMacro |
| 6088 | { 597, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 390, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTLO |
| 6089 | { 596, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 390, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTHI |
| 6090 | { 595, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 395, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTHC1 |
| 6091 | { 594, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTGPR |
| 6092 | { 593, 1, 0, 4, 0, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTDSP |
| 6093 | { 592, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 395, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTC1 |
| 6094 | { 591, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTC0 |
| 6095 | { 590, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 390, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTACX |
| 6096 | { 589, 2, 0, 4, 0, 2, 0, MipsOpInfoBase + 388, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // MIPSeh_return64 |
| 6097 | { 588, 2, 0, 4, 0, 2, 0, MipsOpInfoBase + 151, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // MIPSeh_return32 |
| 6098 | { 587, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 381, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTLO |
| 6099 | { 586, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 381, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTHI |
| 6100 | { 585, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTHC1 |
| 6101 | { 584, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTGPR |
| 6102 | { 583, 1, 1, 4, 0, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTDSP |
| 6103 | { 582, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTC1 |
| 6104 | { 581, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 383, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTC0 |
| 6105 | { 580, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 381, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTACX |
| 6106 | { 579, 3, 1, 2, 236, 0, 0, MipsOpInfoBase + 378, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LwConstant32 |
| 6107 | { 578, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmSingleGPR |
| 6108 | { 577, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 376, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmSingleFGR |
| 6109 | { 576, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmDoubleGPR |
| 6110 | { 575, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmDoubleFGR_32 |
| 6111 | { 574, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 372, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmDoubleFGR |
| 6112 | { 573, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 365, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImm64 |
| 6113 | { 572, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 370, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImm32 |
| 6114 | { 571, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadAddrReg64 |
| 6115 | { 570, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadAddrReg32 |
| 6116 | { 569, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 365, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadAddrImm64 |
| 6117 | { 568, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 363, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadAddrImm32 |
| 6118 | { 567, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 360, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWM_MM |
| 6119 | { 566, 2, 1, 4, 7, 0, 0, MipsOpInfoBase + 358, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_LUi2Op_64 |
| 6120 | { 565, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 356, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_LUi2Op |
| 6121 | { 564, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 353, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_LUi |
| 6122 | { 563, 3, 1, 4, 7, 0, 0, MipsOpInfoBase + 350, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_DADDiu2Op |
| 6123 | { 562, 4, 1, 4, 7, 0, 0, MipsOpInfoBase + 346, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_DADDiu |
| 6124 | { 561, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_ADDiu2Op |
| 6125 | { 560, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 342, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_ADDiu |
| 6126 | { 559, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 339, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LOAD_CCOND_DSP |
| 6127 | { 558, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 336, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LOAD_ACC64DSP |
| 6128 | { 557, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 333, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LOAD_ACC64 |
| 6129 | { 556, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 330, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LOAD_ACC128 |
| 6130 | { 555, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 327, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // LDR_W |
| 6131 | { 554, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 324, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // LDR_D |
| 6132 | { 553, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDMacro |
| 6133 | { 552, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JalTwoReg |
| 6134 | { 551, 1, 0, 4, 0, 0, 0, MipsOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JalOneReg |
| 6135 | { 550, 1, 0, 4, 297, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL }, // JAL_MMR6 |
| 6136 | { 549, 1, 0, 4, 85, 0, 1, MipsOpInfoBase + 196, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // JALRPseudo |
| 6137 | { 548, 1, 0, 4, 85, 0, 1, MipsOpInfoBase + 196, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // JALRHBPseudo |
| 6138 | { 547, 1, 0, 4, 302, 0, 1, MipsOpInfoBase + 320, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // JALRHB64Pseudo |
| 6139 | { 546, 1, 0, 4, 302, 0, 1, MipsOpInfoBase + 320, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // JALR64Pseudo |
| 6140 | { 545, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 316, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_W_VIDX_PSEUDO |
| 6141 | { 544, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 312, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_W_VIDX64_PSEUDO |
| 6142 | { 543, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 308, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_H_VIDX_PSEUDO |
| 6143 | { 542, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 304, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_H_VIDX64_PSEUDO |
| 6144 | { 541, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 300, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FW_VIDX_PSEUDO |
| 6145 | { 540, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 296, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FW_VIDX64_PSEUDO |
| 6146 | { 539, 4, 1, 4, 38, 0, 0, MipsOpInfoBase + 292, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FW_PSEUDO |
| 6147 | { 538, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 288, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FD_VIDX_PSEUDO |
| 6148 | { 537, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 284, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FD_VIDX64_PSEUDO |
| 6149 | { 536, 4, 1, 4, 38, 0, 0, MipsOpInfoBase + 280, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FD_PSEUDO |
| 6150 | { 535, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 276, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_D_VIDX_PSEUDO |
| 6151 | { 534, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 272, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_D_VIDX64_PSEUDO |
| 6152 | { 533, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 268, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_B_VIDX_PSEUDO |
| 6153 | { 532, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 264, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_B_VIDX64_PSEUDO |
| 6154 | { 531, 4, 2, 2, 236, 0, 0, MipsOpInfoBase + 260, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // GotPrologue16 |
| 6155 | { 530, 2, 1, 4, 37, 0, 0, MipsOpInfoBase + 258, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FILL_FW_PSEUDO |
| 6156 | { 529, 2, 1, 4, 37, 0, 0, MipsOpInfoBase + 256, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FILL_FD_PSEUDO |
| 6157 | { 528, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 254, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FEXP2_W_1_PSEUDO |
| 6158 | { 527, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 252, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FEXP2_D_1_PSEUDO |
| 6159 | { 526, 2, 1, 4, 119, 0, 0, MipsOpInfoBase + 254, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // FABS_W |
| 6160 | { 525, 2, 1, 4, 119, 0, 0, MipsOpInfoBase + 252, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // FABS_D |
| 6161 | { 524, 3, 1, 4, 218, 0, 0, MipsOpInfoBase + 249, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ExtractElementF64_64 |
| 6162 | { 523, 3, 1, 4, 218, 0, 0, MipsOpInfoBase + 246, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ExtractElementF64 |
| 6163 | { 522, 0, 0, 4, 273, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // ERet |
| 6164 | { 521, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DURemMacro |
| 6165 | { 520, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DURemIMacro |
| 6166 | { 519, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DUDivMacro |
| 6167 | { 518, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DUDivIMacro |
| 6168 | { 517, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DSRemMacro |
| 6169 | { 516, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DSRemIMacro |
| 6170 | { 515, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DSDivMacro |
| 6171 | { 514, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DSDivIMacro |
| 6172 | { 513, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DRORImm |
| 6173 | { 512, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DROR |
| 6174 | { 511, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DROLImm |
| 6175 | { 510, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DROL |
| 6176 | { 509, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DMULOUMacro |
| 6177 | { 508, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DMULOMacro |
| 6178 | { 507, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DMULMacro |
| 6179 | { 506, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 234, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DMULImmMacro |
| 6180 | { 505, 1, 0, 2, 236, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Constant32 |
| 6181 | { 504, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 232, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CTTC1 |
| 6182 | { 503, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 229, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // COPY_FW_PSEUDO |
| 6183 | { 502, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 226, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // COPY_FD_PSEUDO |
| 6184 | { 501, 3, 0, 2, 236, 0, 0, MipsOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CONSTPOOL_ENTRY |
| 6185 | { 500, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 224, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CFTC1 |
| 6186 | { 499, 3, 1, 4, 215, 0, 0, MipsOpInfoBase + 221, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BuildPairF64_FPR |
| 6187 | { 498, 3, 1, 4, 214, 0, 0, MipsOpInfoBase + 218, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BuildPairF64_64 |
| 6188 | { 497, 3, 1, 4, 214, 0, 0, MipsOpInfoBase + 215, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BuildPairF64 |
| 6189 | { 496, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 209, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BtnezT8SltuX16 |
| 6190 | { 495, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 212, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BtnezT8SltiuX16 |
| 6191 | { 494, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 212, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BtnezT8SltiX16 |
| 6192 | { 493, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 209, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BtnezT8SltX16 |
| 6193 | { 492, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 212, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BtnezT8CmpiX16 |
| 6194 | { 491, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 209, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BtnezT8CmpX16 |
| 6195 | { 490, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 209, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BteqzT8SltuX16 |
| 6196 | { 489, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 212, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BteqzT8SltiuX16 |
| 6197 | { 488, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 212, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BteqzT8SltiX16 |
| 6198 | { 487, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 209, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BteqzT8SltX16 |
| 6199 | { 486, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 212, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BteqzT8CmpiX16 |
| 6200 | { 485, 3, 0, 2, 289, 0, 0, MipsOpInfoBase + 209, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BteqzT8CmpX16 |
| 6201 | { 484, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BneImm |
| 6202 | { 483, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BeqImm |
| 6203 | { 482, 1, 0, 4, 293, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // B_MM_Pseudo |
| 6204 | { 481, 1, 0, 4, 297, 0, 0, MipsOpInfoBase + 189, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // B_MMR6_Pseudo |
| 6205 | { 480, 1, 0, 4, 293, 0, 1, MipsOpInfoBase + 189, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // B_MM |
| 6206 | { 479, 4, 1, 4, 65, 0, 0, MipsOpInfoBase + 201, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_W_PSEUDO |
| 6207 | { 478, 4, 1, 4, 65, 0, 0, MipsOpInfoBase + 205, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_H_PSEUDO |
| 6208 | { 477, 4, 1, 4, 65, 0, 0, MipsOpInfoBase + 201, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_FW_PSEUDO |
| 6209 | { 476, 4, 1, 4, 65, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_FD_PSEUDO |
| 6210 | { 475, 4, 1, 4, 65, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_D_PSEUDO |
| 6211 | { 474, 1, 1, 4, 0, 1, 0, MipsOpInfoBase + 196, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BPOSGE32_PSEUDO |
| 6212 | { 473, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BNELImmMacro |
| 6213 | { 472, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTULImmMacro |
| 6214 | { 471, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTUL |
| 6215 | { 470, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTUImmMacro |
| 6216 | { 469, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTU |
| 6217 | { 468, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTLImmMacro |
| 6218 | { 467, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTL |
| 6219 | { 466, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTImmMacro |
| 6220 | { 465, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLT |
| 6221 | { 464, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEULImmMacro |
| 6222 | { 463, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEUL |
| 6223 | { 462, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEUImmMacro |
| 6224 | { 461, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEU |
| 6225 | { 460, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLELImmMacro |
| 6226 | { 459, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEL |
| 6227 | { 458, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEImmMacro |
| 6228 | { 457, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLE |
| 6229 | { 456, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTULImmMacro |
| 6230 | { 455, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTUL |
| 6231 | { 454, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTUImmMacro |
| 6232 | { 453, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTU |
| 6233 | { 452, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTLImmMacro |
| 6234 | { 451, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTL |
| 6235 | { 450, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTImmMacro |
| 6236 | { 449, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGT |
| 6237 | { 448, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEULImmMacro |
| 6238 | { 447, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEUL |
| 6239 | { 446, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEUImmMacro |
| 6240 | { 445, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEU |
| 6241 | { 444, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGELImmMacro |
| 6242 | { 443, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEL |
| 6243 | { 442, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEImmMacro |
| 6244 | { 441, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGE |
| 6245 | { 440, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BEQLImmMacro |
| 6246 | { 439, 1, 0, 4, 293, 0, 1, MipsOpInfoBase + 189, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BAL_BR_MM |
| 6247 | { 438, 1, 0, 4, 273, 0, 1, MipsOpInfoBase + 189, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BAL_BR |
| 6248 | { 437, 1, 0, 4, 273, 0, 1, MipsOpInfoBase + 189, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // B |
| 6249 | { 436, 6, 1, 4, 76, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_SWAP_I8_POSTRA |
| 6250 | { 435, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_SWAP_I8 |
| 6251 | { 434, 3, 1, 4, 76, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_SWAP_I64_POSTRA |
| 6252 | { 433, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_SWAP_I64 |
| 6253 | { 432, 3, 1, 4, 76, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_SWAP_I32_POSTRA |
| 6254 | { 431, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_SWAP_I32 |
| 6255 | { 430, 6, 1, 4, 76, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_SWAP_I16_POSTRA |
| 6256 | { 429, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_SWAP_I16 |
| 6257 | { 428, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_XOR_I8_POSTRA |
| 6258 | { 427, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_XOR_I8 |
| 6259 | { 426, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_XOR_I64_POSTRA |
| 6260 | { 425, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_XOR_I64 |
| 6261 | { 424, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_XOR_I32_POSTRA |
| 6262 | { 423, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_XOR_I32 |
| 6263 | { 422, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_XOR_I16_POSTRA |
| 6264 | { 421, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_XOR_I16 |
| 6265 | { 420, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMIN_I8_POSTRA |
| 6266 | { 419, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMIN_I8 |
| 6267 | { 418, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMIN_I64_POSTRA |
| 6268 | { 417, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMIN_I64 |
| 6269 | { 416, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMIN_I32_POSTRA |
| 6270 | { 415, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMIN_I32 |
| 6271 | { 414, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMIN_I16_POSTRA |
| 6272 | { 413, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMIN_I16 |
| 6273 | { 412, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMAX_I8_POSTRA |
| 6274 | { 411, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMAX_I8 |
| 6275 | { 410, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMAX_I64_POSTRA |
| 6276 | { 409, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMAX_I64 |
| 6277 | { 408, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMAX_I32_POSTRA |
| 6278 | { 407, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMAX_I32 |
| 6279 | { 406, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMAX_I16_POSTRA |
| 6280 | { 405, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMAX_I16 |
| 6281 | { 404, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_SUB_I8_POSTRA |
| 6282 | { 403, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_SUB_I8 |
| 6283 | { 402, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_SUB_I64_POSTRA |
| 6284 | { 401, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_SUB_I64 |
| 6285 | { 400, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_SUB_I32_POSTRA |
| 6286 | { 399, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_SUB_I32 |
| 6287 | { 398, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_SUB_I16_POSTRA |
| 6288 | { 397, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_SUB_I16 |
| 6289 | { 396, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_OR_I8_POSTRA |
| 6290 | { 395, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_OR_I8 |
| 6291 | { 394, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_OR_I64_POSTRA |
| 6292 | { 393, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_OR_I64 |
| 6293 | { 392, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_OR_I32_POSTRA |
| 6294 | { 391, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_OR_I32 |
| 6295 | { 390, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_OR_I16_POSTRA |
| 6296 | { 389, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_OR_I16 |
| 6297 | { 388, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_NAND_I8_POSTRA |
| 6298 | { 387, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_NAND_I8 |
| 6299 | { 386, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_NAND_I64_POSTRA |
| 6300 | { 385, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_NAND_I64 |
| 6301 | { 384, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_NAND_I32_POSTRA |
| 6302 | { 383, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_NAND_I32 |
| 6303 | { 382, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_NAND_I16_POSTRA |
| 6304 | { 381, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_NAND_I16 |
| 6305 | { 380, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MIN_I8_POSTRA |
| 6306 | { 379, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MIN_I8 |
| 6307 | { 378, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MIN_I64_POSTRA |
| 6308 | { 377, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MIN_I64 |
| 6309 | { 376, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MIN_I32_POSTRA |
| 6310 | { 375, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MIN_I32 |
| 6311 | { 374, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MIN_I16_POSTRA |
| 6312 | { 373, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MIN_I16 |
| 6313 | { 372, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MAX_I8_POSTRA |
| 6314 | { 371, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MAX_I8 |
| 6315 | { 370, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MAX_I64_POSTRA |
| 6316 | { 369, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MAX_I64 |
| 6317 | { 368, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MAX_I32_POSTRA |
| 6318 | { 367, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MAX_I32 |
| 6319 | { 366, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MAX_I16_POSTRA |
| 6320 | { 365, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MAX_I16 |
| 6321 | { 364, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_AND_I8_POSTRA |
| 6322 | { 363, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_AND_I8 |
| 6323 | { 362, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_AND_I64_POSTRA |
| 6324 | { 361, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_AND_I64 |
| 6325 | { 360, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_AND_I32_POSTRA |
| 6326 | { 359, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_AND_I32 |
| 6327 | { 358, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_AND_I16_POSTRA |
| 6328 | { 357, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_AND_I16 |
| 6329 | { 356, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_ADD_I8_POSTRA |
| 6330 | { 355, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_ADD_I8 |
| 6331 | { 354, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_ADD_I64_POSTRA |
| 6332 | { 353, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_ADD_I64 |
| 6333 | { 352, 3, 1, 4, 78, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_ADD_I32_POSTRA |
| 6334 | { 351, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_ADD_I32 |
| 6335 | { 350, 6, 1, 4, 78, 0, 0, MipsOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_ADD_I16_POSTRA |
| 6336 | { 349, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_ADD_I16 |
| 6337 | { 348, 7, 1, 4, 77, 0, 0, MipsOpInfoBase + 166, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_CMP_SWAP_I8_POSTRA |
| 6338 | { 347, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_CMP_SWAP_I8 |
| 6339 | { 346, 4, 1, 4, 77, 0, 0, MipsOpInfoBase + 173, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_CMP_SWAP_I64_POSTRA |
| 6340 | { 345, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 173, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_CMP_SWAP_I64 |
| 6341 | { 344, 4, 1, 4, 77, 0, 0, MipsOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_CMP_SWAP_I32_POSTRA |
| 6342 | { 343, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_CMP_SWAP_I32 |
| 6343 | { 342, 7, 1, 4, 77, 0, 0, MipsOpInfoBase + 166, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_CMP_SWAP_I16_POSTRA |
| 6344 | { 341, 4, 1, 4, 0, 0, 0, MipsOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_CMP_SWAP_I16 |
| 6345 | { 340, 3, 1, 4, 29, 0, 0, MipsOpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // AND_V_W_PSEUDO |
| 6346 | { 339, 3, 1, 4, 29, 0, 0, MipsOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // AND_V_H_PSEUDO |
| 6347 | { 338, 3, 1, 4, 29, 0, 0, MipsOpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // AND_V_D_PSEUDO |
| 6348 | { 337, 2, 0, 4, 0, 1, 1, MipsOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADJCALLSTACKUP |
| 6349 | { 336, 2, 0, 4, 0, 1, 1, MipsOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADJCALLSTACKDOWN |
| 6350 | { 335, 2, 1, 4, 0, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ABSMacro |
| 6351 | { 334, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX |
| 6352 | { 333, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX |
| 6353 | { 332, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN |
| 6354 | { 331, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX |
| 6355 | { 330, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN |
| 6356 | { 329, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX |
| 6357 | { 328, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR |
| 6358 | { 327, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR |
| 6359 | { 326, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND |
| 6360 | { 325, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL |
| 6361 | { 324, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD |
| 6362 | { 323, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM |
| 6363 | { 322, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM |
| 6364 | { 321, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM |
| 6365 | { 320, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM |
| 6366 | { 319, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN |
| 6367 | { 318, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX |
| 6368 | { 317, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL |
| 6369 | { 316, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD |
| 6370 | { 315, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL |
| 6371 | { 314, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD |
| 6372 | { 313, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP |
| 6373 | { 312, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP |
| 6374 | { 311, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP |
| 6375 | { 310, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET_INLINE |
| 6376 | { 309, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO |
| 6377 | { 308, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET |
| 6378 | { 307, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE |
| 6379 | { 306, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE |
| 6380 | { 305, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY |
| 6381 | { 304, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER |
| 6382 | { 303, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER |
| 6383 | { 302, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMPS |
| 6384 | { 301, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMP |
| 6385 | { 300, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP |
| 6386 | { 299, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT |
| 6387 | { 298, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA |
| 6388 | { 297, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM |
| 6389 | { 296, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV |
| 6390 | { 295, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL |
| 6391 | { 294, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB |
| 6392 | { 293, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD |
| 6393 | { 292, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE |
| 6394 | { 291, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE |
| 6395 | { 290, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC |
| 6396 | { 289, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE |
| 6397 | { 288, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR |
| 6398 | { 287, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST |
| 6399 | { 286, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT |
| 6400 | { 285, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT |
| 6401 | { 284, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR |
| 6402 | { 283, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT |
| 6403 | { 282, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH |
| 6404 | { 281, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH |
| 6405 | { 280, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH |
| 6406 | { 279, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2 |
| 6407 | { 278, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN |
| 6408 | { 277, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN |
| 6409 | { 276, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS |
| 6410 | { 275, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN |
| 6411 | { 274, 3, 2, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS |
| 6412 | { 273, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN |
| 6413 | { 272, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS |
| 6414 | { 271, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL |
| 6415 | { 270, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMULR |
| 6416 | { 269, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMULH |
| 6417 | { 268, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMUL |
| 6418 | { 267, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE |
| 6419 | { 266, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP |
| 6420 | { 265, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP |
| 6421 | { 264, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS |
| 6422 | { 263, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_POISON |
| 6423 | { 262, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ |
| 6424 | { 261, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_POISON |
| 6425 | { 260, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ |
| 6426 | { 259, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS |
| 6427 | { 258, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR |
| 6428 | { 257, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR |
| 6429 | { 256, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR |
| 6430 | { 255, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT |
| 6431 | { 254, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT |
| 6432 | { 253, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR |
| 6433 | { 252, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR |
| 6434 | { 251, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE |
| 6435 | { 250, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT |
| 6436 | { 249, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR |
| 6437 | { 248, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND |
| 6438 | { 247, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND |
| 6439 | { 246, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS |
| 6440 | { 245, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX |
| 6441 | { 244, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN |
| 6442 | { 243, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX |
| 6443 | { 242, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN |
| 6444 | { 241, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK |
| 6445 | { 240, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD |
| 6446 | { 239, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING |
| 6447 | { 238, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING |
| 6448 | { 237, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE |
| 6449 | { 236, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE |
| 6450 | { 235, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE |
| 6451 | { 234, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV |
| 6452 | { 233, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV |
| 6453 | { 232, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV |
| 6454 | { 231, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM |
| 6455 | { 230, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM |
| 6456 | { 229, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM |
| 6457 | { 228, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM |
| 6458 | { 227, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE |
| 6459 | { 226, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE |
| 6460 | { 225, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM |
| 6461 | { 224, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM |
| 6462 | { 223, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE |
| 6463 | { 222, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS |
| 6464 | { 221, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN |
| 6465 | { 220, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS |
| 6466 | { 219, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT |
| 6467 | { 218, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT |
| 6468 | { 217, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP |
| 6469 | { 216, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP |
| 6470 | { 215, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI |
| 6471 | { 214, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI |
| 6472 | { 213, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC |
| 6473 | { 212, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT |
| 6474 | { 211, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG |
| 6475 | { 210, 3, 2, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP |
| 6476 | { 209, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP |
| 6477 | { 208, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10 |
| 6478 | { 207, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2 |
| 6479 | { 206, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG |
| 6480 | { 205, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10 |
| 6481 | { 204, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2 |
| 6482 | { 203, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP |
| 6483 | { 202, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI |
| 6484 | { 201, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW |
| 6485 | { 200, 3, 2, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF |
| 6486 | { 199, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM |
| 6487 | { 198, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV |
| 6488 | { 197, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD |
| 6489 | { 196, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA |
| 6490 | { 195, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL |
| 6491 | { 194, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB |
| 6492 | { 193, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD |
| 6493 | { 192, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT |
| 6494 | { 191, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT |
| 6495 | { 190, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX |
| 6496 | { 189, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX |
| 6497 | { 188, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT |
| 6498 | { 187, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT |
| 6499 | { 186, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX |
| 6500 | { 185, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX |
| 6501 | { 184, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT |
| 6502 | { 183, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT |
| 6503 | { 182, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT |
| 6504 | { 181, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT |
| 6505 | { 180, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT |
| 6506 | { 179, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT |
| 6507 | { 178, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH |
| 6508 | { 177, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH |
| 6509 | { 176, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO |
| 6510 | { 175, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO |
| 6511 | { 174, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE |
| 6512 | { 173, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO |
| 6513 | { 172, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE |
| 6514 | { 171, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO |
| 6515 | { 170, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE |
| 6516 | { 169, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO |
| 6517 | { 168, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE |
| 6518 | { 167, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO |
| 6519 | { 166, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT |
| 6520 | { 165, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP |
| 6521 | { 164, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP |
| 6522 | { 163, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP |
| 6523 | { 162, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP |
| 6524 | { 161, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL |
| 6525 | { 160, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR |
| 6526 | { 159, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR |
| 6527 | { 158, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL |
| 6528 | { 157, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR |
| 6529 | { 156, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR |
| 6530 | { 155, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL |
| 6531 | { 154, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT |
| 6532 | { 153, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG |
| 6533 | { 152, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT |
| 6534 | { 151, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG |
| 6535 | { 150, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART |
| 6536 | { 149, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT |
| 6537 | { 148, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT |
| 6538 | { 147, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U |
| 6539 | { 146, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U |
| 6540 | { 145, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S |
| 6541 | { 144, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC |
| 6542 | { 143, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT |
| 6543 | { 142, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 6544 | { 141, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT |
| 6545 | { 140, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS |
| 6546 | { 139, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC |
| 6547 | { 138, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START |
| 6548 | { 137, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT |
| 6549 | { 136, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND |
| 6550 | { 135, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH |
| 6551 | { 134, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE |
| 6552 | { 133, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT |
| 6553 | { 132, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND |
| 6554 | { 131, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP |
| 6555 | { 130, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP |
| 6556 | { 129, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM |
| 6557 | { 128, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM |
| 6558 | { 127, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM |
| 6559 | { 126, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM |
| 6560 | { 125, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN |
| 6561 | { 124, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX |
| 6562 | { 123, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB |
| 6563 | { 122, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD |
| 6564 | { 121, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN |
| 6565 | { 120, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX |
| 6566 | { 119, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN |
| 6567 | { 118, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX |
| 6568 | { 117, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR |
| 6569 | { 116, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR |
| 6570 | { 115, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND |
| 6571 | { 114, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND |
| 6572 | { 113, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB |
| 6573 | { 112, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD |
| 6574 | { 111, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG |
| 6575 | { 110, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG |
| 6576 | { 109, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 6577 | { 108, 5, 1, 0, 0, 0, 0, MipsOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE |
| 6578 | { 107, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_FPTRUNCSTORE |
| 6579 | { 106, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE |
| 6580 | { 105, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD |
| 6581 | { 104, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD |
| 6582 | { 103, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD |
| 6583 | { 102, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_FPEXTLOAD |
| 6584 | { 101, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD |
| 6585 | { 100, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD |
| 6586 | { 99, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD |
| 6587 | { 98, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER |
| 6588 | { 97, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER |
| 6589 | { 96, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN |
| 6590 | { 95, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT |
| 6591 | { 94, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT |
| 6592 | { 93, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND |
| 6593 | { 92, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC |
| 6594 | { 91, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND |
| 6595 | { 90, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER |
| 6596 | { 89, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE |
| 6597 | { 88, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST |
| 6598 | { 87, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR |
| 6599 | { 86, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT |
| 6600 | { 85, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS |
| 6601 | { 84, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC |
| 6602 | { 83, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR |
| 6603 | { 82, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES |
| 6604 | { 81, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT |
| 6605 | { 80, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES |
| 6606 | { 79, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT |
| 6607 | { 78, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL |
| 6608 | { 77, 5, 1, 0, 0, 0, 0, MipsOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE |
| 6609 | { 76, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE |
| 6610 | { 75, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX |
| 6611 | { 74, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI |
| 6612 | { 73, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF |
| 6613 | { 72, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL |
| 6614 | { 71, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR |
| 6615 | { 70, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL |
| 6616 | { 69, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR |
| 6617 | { 68, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU |
| 6618 | { 67, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS |
| 6619 | { 66, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR |
| 6620 | { 65, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR |
| 6621 | { 64, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND |
| 6622 | { 63, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM |
| 6623 | { 62, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM |
| 6624 | { 61, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM |
| 6625 | { 60, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM |
| 6626 | { 59, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV |
| 6627 | { 58, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV |
| 6628 | { 57, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL |
| 6629 | { 56, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB |
| 6630 | { 55, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD |
| 6631 | { 54, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN |
| 6632 | { 53, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT |
| 6633 | { 52, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT |
| 6634 | { 51, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE |
| 6635 | { 50, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP |
| 6636 | { 49, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR |
| 6637 | { 48, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY |
| 6638 | { 47, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE |
| 6639 | { 46, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO |
| 6640 | { 45, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER |
| 6641 | { 44, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE |
| 6642 | { 43, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL |
| 6643 | { 42, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17315 |
| 6644 | { 41, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17314 |
| 6645 | { 40, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL |
| 6646 | { 39, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT |
| 6647 | { 38, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET |
| 6648 | { 37, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER |
| 6649 | { 36, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP |
| 6650 | { 35, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP |
| 6651 | { 34, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE |
| 6652 | { 33, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT |
| 6653 | { 32, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17313 |
| 6654 | { 31, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP |
| 6655 | { 30, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_14418 |
| 6656 | { 29, 6, 1, 0, 0, 0, 0, MipsOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT |
| 6657 | { 28, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL |
| 6658 | { 27, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP |
| 6659 | { 26, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE |
| 6660 | { 25, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE |
| 6661 | { 24, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END |
| 6662 | { 23, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START |
| 6663 | { 22, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE |
| 6664 | { 21, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK |
| 6665 | { 20, 2, 1, 0, 233, 0, 0, MipsOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY |
| 6666 | { 19, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE |
| 6667 | { 18, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL |
| 6668 | { 17, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI |
| 6669 | { 16, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF |
| 6670 | { 15, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST |
| 6671 | { 14, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE |
| 6672 | { 13, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS |
| 6673 | { 12, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG |
| 6674 | { 11, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF |
| 6675 | { 10, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF |
| 6676 | { 9, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG |
| 6677 | { 8, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG |
| 6678 | { 7, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL |
| 6679 | { 6, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL |
| 6680 | { 5, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL |
| 6681 | { 4, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL |
| 6682 | { 3, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION |
| 6683 | { 2, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR |
| 6684 | { 1, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM |
| 6685 | { 0, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI |
| 6686 | }, { |
| 6687 | /* 0 */ |
| 6688 | /* 0 */ Mips::SP, Mips::SP, |
| 6689 | /* 2 */ Mips::AT, |
| 6690 | /* 3 */ Mips::RA, |
| 6691 | /* 4 */ Mips::DSPPos, |
| 6692 | /* 5 */ Mips::V0, Mips::V1, |
| 6693 | /* 7 */ Mips::HI0, Mips::LO0, |
| 6694 | /* 9 */ Mips::T8, |
| 6695 | /* 10 */ Mips::DSPOutFlag20, |
| 6696 | /* 11 */ Mips::FCR31, |
| 6697 | /* 12 */ Mips::DSPCarry, |
| 6698 | /* 13 */ Mips::DSPCarry, Mips::DSPOutFlag20, |
| 6699 | /* 15 */ Mips::DSPCCond, |
| 6700 | /* 16 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, |
| 6701 | /* 21 */ Mips::HI0_64, Mips::LO0_64, |
| 6702 | /* 23 */ Mips::DSPOutFlag16_19, |
| 6703 | /* 24 */ Mips::DSPPos, Mips::DSPEFI, |
| 6704 | /* 26 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI, |
| 6705 | /* 29 */ Mips::DSPOutFlag23, |
| 6706 | /* 30 */ Mips::FCC0, |
| 6707 | /* 31 */ Mips::DSPPos, Mips::DSPSCount, |
| 6708 | /* 33 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0, |
| 6709 | /* 37 */ Mips::AC0, |
| 6710 | /* 38 */ Mips::AC0_64, |
| 6711 | /* 39 */ Mips::HI0, |
| 6712 | /* 40 */ Mips::HI0_64, |
| 6713 | /* 41 */ Mips::LO0, |
| 6714 | /* 42 */ Mips::LO0_64, |
| 6715 | /* 43 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, |
| 6716 | /* 47 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, |
| 6717 | /* 51 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, |
| 6718 | /* 55 */ Mips::P0, |
| 6719 | /* 56 */ Mips::P1, |
| 6720 | /* 57 */ Mips::P2, |
| 6721 | /* 58 */ Mips::DSPOutFlag21, |
| 6722 | /* 59 */ Mips::DSPOutFlag22, |
| 6723 | /* 60 */ Mips::P0, Mips::P1, Mips::P2, |
| 6724 | /* 63 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, |
| 6725 | }, { |
| 6726 | 0 |
| 6727 | }, { |
| 6728 | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6729 | /* 1 */ |
| 6730 | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6731 | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6732 | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6733 | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6734 | /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6735 | /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6736 | /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
| 6737 | /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6738 | /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6739 | /* 28 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, |
| 6740 | /* 29 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6741 | /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6742 | /* 34 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6743 | /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6744 | /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 6745 | /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6746 | /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6747 | /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6748 | /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6749 | /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6750 | /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 6751 | /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 6752 | /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 6753 | /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6754 | /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6755 | /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6756 | /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6757 | /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6758 | /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6759 | /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6760 | /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 }, |
| 6761 | /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6762 | /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 6763 | /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 6764 | /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 6765 | /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 6766 | /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 6767 | /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 6768 | /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 6769 | /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 6770 | /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 6771 | /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6772 | /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6773 | /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 6774 | /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 6775 | /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 6776 | /* 151 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6777 | /* 153 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6778 | /* 156 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6779 | /* 159 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6780 | /* 162 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6781 | /* 166 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6782 | /* 173 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6783 | /* 177 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6784 | /* 180 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6785 | /* 186 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6786 | /* 189 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6787 | /* 190 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6788 | /* 193 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6789 | /* 196 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6790 | /* 197 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6791 | /* 201 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6792 | /* 205 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6793 | /* 209 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6794 | /* 212 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6795 | /* 215 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6796 | /* 218 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6797 | /* 221 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6798 | /* 224 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32CCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6799 | /* 226 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6800 | /* 229 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6801 | /* 232 */ { Mips::FGR32CCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6802 | /* 234 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6803 | /* 237 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6804 | /* 240 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6805 | /* 243 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6806 | /* 246 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6807 | /* 249 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6808 | /* 252 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6809 | /* 254 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6810 | /* 256 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6811 | /* 258 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6812 | /* 260 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6813 | /* 264 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6814 | /* 268 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6815 | /* 272 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6816 | /* 276 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6817 | /* 280 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6818 | /* 284 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6819 | /* 288 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6820 | /* 292 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6821 | /* 296 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6822 | /* 300 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6823 | /* 304 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6824 | /* 308 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6825 | /* 312 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6826 | /* 316 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6827 | /* 320 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6828 | /* 321 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 6829 | /* 324 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6830 | /* 327 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6831 | /* 330 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 6832 | /* 333 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 6833 | /* 336 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 6834 | /* 339 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 6835 | /* 342 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6836 | /* 346 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6837 | /* 350 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6838 | /* 353 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6839 | /* 356 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6840 | /* 358 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6841 | /* 360 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 6842 | /* 363 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 6843 | /* 365 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6844 | /* 367 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 6845 | /* 370 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6846 | /* 372 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6847 | /* 374 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6848 | /* 376 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6849 | /* 378 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6850 | /* 381 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6851 | /* 383 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6852 | /* 386 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6853 | /* 388 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6854 | /* 390 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6855 | /* 392 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6856 | /* 395 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6857 | /* 397 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6858 | /* 399 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6859 | /* 402 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6860 | /* 405 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6861 | /* 407 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6862 | /* 409 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6863 | /* 411 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6864 | /* 414 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6865 | /* 421 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6866 | /* 428 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 6867 | /* 432 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6868 | /* 434 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6869 | /* 436 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6870 | /* 439 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6871 | /* 442 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6872 | /* 446 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6873 | /* 450 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6874 | /* 454 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6875 | /* 458 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6876 | /* 462 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6877 | /* 466 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6878 | /* 470 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6879 | /* 474 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6880 | /* 478 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6881 | /* 482 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6882 | /* 486 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6883 | /* 489 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6884 | /* 492 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6885 | /* 495 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 6886 | /* 498 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6887 | /* 501 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6888 | /* 503 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6889 | /* 505 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6890 | /* 507 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6891 | /* 509 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6892 | /* 513 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6893 | /* 518 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6894 | /* 523 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6895 | /* 526 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6896 | /* 528 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6897 | /* 530 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6898 | /* 533 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6899 | /* 536 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6900 | /* 539 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6901 | /* 542 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6902 | /* 545 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6903 | /* 548 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6904 | /* 551 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6905 | /* 554 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6906 | /* 557 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6907 | /* 560 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6908 | /* 564 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 6909 | /* 567 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 6910 | /* 571 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6911 | /* 573 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6912 | /* 576 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6913 | /* 579 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6914 | /* 582 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6915 | /* 585 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6916 | /* 587 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6917 | /* 589 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6918 | /* 591 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6919 | /* 593 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6920 | /* 597 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6921 | /* 601 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6922 | /* 605 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6923 | /* 609 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6924 | /* 613 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6925 | /* 615 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6926 | /* 617 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6927 | /* 619 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6928 | /* 621 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 6929 | /* 623 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6930 | /* 626 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6931 | /* 628 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6932 | /* 630 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6933 | /* 632 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6934 | /* 634 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6935 | /* 636 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6936 | /* 638 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6937 | /* 640 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6938 | /* 642 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6939 | /* 646 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6940 | /* 650 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6941 | /* 654 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6942 | /* 657 */ { Mips::FGR64CCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6943 | /* 660 */ { Mips::FGR32CCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6944 | /* 663 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6945 | /* 666 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6946 | /* 669 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6947 | /* 672 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6948 | /* 675 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6949 | /* 677 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6950 | /* 679 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6951 | /* 681 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6952 | /* 683 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6953 | /* 686 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6954 | /* 689 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6955 | /* 692 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6956 | /* 695 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6957 | /* 698 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6958 | /* 702 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 6959 | /* 707 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6960 | /* 710 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6961 | /* 712 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6962 | /* 715 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6963 | /* 718 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6964 | /* 721 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6965 | /* 724 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6966 | /* 727 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6967 | /* 730 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6968 | /* 734 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6969 | /* 738 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6970 | /* 742 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 6971 | /* 746 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6972 | /* 749 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6973 | /* 751 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6974 | /* 754 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6975 | /* 757 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6976 | /* 759 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6977 | /* 762 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6978 | /* 765 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6979 | /* 768 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6980 | /* 771 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6981 | /* 774 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6982 | /* 777 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6983 | /* 780 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6984 | /* 782 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6985 | /* 784 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6986 | /* 786 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6987 | /* 788 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6988 | /* 790 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6989 | /* 792 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 6990 | /* 797 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6991 | /* 801 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6992 | /* 805 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6993 | /* 809 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6994 | /* 813 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 6995 | /* 816 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6996 | /* 821 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6997 | /* 826 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6998 | /* 831 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 6999 | /* 836 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7000 | /* 837 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ptr_gpr16mm_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7001 | /* 840 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, |
| 7002 | /* 843 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7003 | /* 846 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7004 | /* 849 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7005 | /* 852 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7006 | /* 855 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7007 | /* 857 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7008 | /* 859 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7009 | /* 861 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7010 | /* 863 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7011 | /* 867 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, |
| 7012 | /* 870 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, |
| 7013 | /* 873 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7014 | /* 876 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7015 | /* 879 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7016 | /* 882 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7017 | /* 885 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
| 7018 | /* 888 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
| 7019 | /* 891 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7020 | /* 894 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7021 | /* 897 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ptr_gp_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7022 | /* 900 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7023 | /* 904 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ptr_sp_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7024 | /* 907 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7025 | /* 911 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ptr_sp_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7026 | /* 914 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, |
| 7027 | /* 917 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7028 | /* 920 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7029 | /* 924 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7030 | /* 928 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7031 | /* 932 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7032 | /* 936 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7033 | /* 940 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7034 | /* 944 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7035 | /* 946 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7036 | /* 949 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7037 | /* 951 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7038 | /* 956 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7039 | /* 960 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7040 | /* 962 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7041 | /* 966 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7042 | /* 970 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7043 | /* 974 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7044 | /* 978 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7045 | /* 982 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7046 | /* 986 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7047 | /* 990 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7048 | /* 994 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7049 | /* 998 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7050 | /* 1002 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7051 | /* 1006 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7052 | /* 1010 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7053 | /* 1014 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7054 | /* 1018 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7055 | /* 1021 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7056 | /* 1024 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7057 | /* 1027 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7058 | /* 1029 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7059 | /* 1032 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7060 | /* 1034 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7061 | /* 1036 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7062 | /* 1038 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7063 | /* 1040 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7064 | /* 1042 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7065 | /* 1044 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7066 | /* 1047 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7067 | /* 1051 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7068 | /* 1054 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7069 | /* 1057 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7070 | /* 1060 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7071 | /* 1062 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7072 | /* 1064 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ptr_gpr16mm_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7073 | /* 1067 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7074 | /* 1071 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
| 7075 | /* 1075 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7076 | /* 1079 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
| 7077 | /* 1083 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64CCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7078 | /* 1087 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32CCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7079 | /* 1091 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7080 | /* 1094 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7081 | /* 1097 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7082 | /* 1100 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7083 | /* 1104 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7084 | /* 1108 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7085 | /* 1112 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7086 | /* 1116 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7087 | /* 1119 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7088 | /* 1122 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7089 | /* 1125 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7090 | /* 1128 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7091 | /* 1131 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7092 | /* 1134 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7093 | /* 1136 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7094 | } |
| 7095 | }; |
| 7096 | |
| 7097 | |
| 7098 | #ifdef __GNUC__ |
| 7099 | #pragma GCC diagnostic push |
| 7100 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 7101 | #endif |
| 7102 | extern const char MipsInstrNameData[] = { |
| 7103 | /* 0 */ "G_FLOG10\000" |
| 7104 | /* 9 */ "G_FEXP10\000" |
| 7105 | /* 18 */ "DMFC0\000" |
| 7106 | /* 24 */ "DMFGC0\000" |
| 7107 | /* 31 */ "MFHGC0\000" |
| 7108 | /* 38 */ "MTHGC0\000" |
| 7109 | /* 45 */ "DMTGC0\000" |
| 7110 | /* 52 */ "MFTC0\000" |
| 7111 | /* 58 */ "DMTC0\000" |
| 7112 | /* 64 */ "MTTC0\000" |
| 7113 | /* 70 */ "VMM0\000" |
| 7114 | /* 75 */ "MTM0\000" |
| 7115 | /* 80 */ "MTP0\000" |
| 7116 | /* 85 */ "BBIT0\000" |
| 7117 | /* 91 */ "LDC1\000" |
| 7118 | /* 96 */ "SDC1\000" |
| 7119 | /* 101 */ "CFC1\000" |
| 7120 | /* 106 */ "DMFC1\000" |
| 7121 | /* 112 */ "MFTHC1\000" |
| 7122 | /* 119 */ "MTTHC1\000" |
| 7123 | /* 126 */ "CTC1\000" |
| 7124 | /* 131 */ "CFTC1\000" |
| 7125 | /* 137 */ "MFTC1\000" |
| 7126 | /* 143 */ "DMTC1\000" |
| 7127 | /* 149 */ "CTTC1\000" |
| 7128 | /* 155 */ "MTTC1\000" |
| 7129 | /* 161 */ "LWC1\000" |
| 7130 | /* 166 */ "SWC1\000" |
| 7131 | /* 171 */ "LDXC1\000" |
| 7132 | /* 177 */ "SDXC1\000" |
| 7133 | /* 183 */ "LUXC1\000" |
| 7134 | /* 189 */ "SUXC1\000" |
| 7135 | /* 195 */ "LWXC1\000" |
| 7136 | /* 201 */ "SWXC1\000" |
| 7137 | /* 207 */ "MTM1\000" |
| 7138 | /* 212 */ "SDC1_M1\000" |
| 7139 | /* 220 */ "MTP1\000" |
| 7140 | /* 225 */ "BBIT1\000" |
| 7141 | /* 231 */ "BBIT032\000" |
| 7142 | /* 239 */ "BBIT132\000" |
| 7143 | /* 247 */ "DSRA32\000" |
| 7144 | /* 254 */ "MFHC1_D32\000" |
| 7145 | /* 264 */ "MTHC1_D32\000" |
| 7146 | /* 274 */ "FSUB_D32\000" |
| 7147 | /* 283 */ "NMSUB_D32\000" |
| 7148 | /* 293 */ "FADD_D32\000" |
| 7149 | /* 302 */ "NMADD_D32\000" |
| 7150 | /* 312 */ "C_NGE_D32\000" |
| 7151 | /* 322 */ "C_NGLE_D32\000" |
| 7152 | /* 333 */ "C_OLE_D32\000" |
| 7153 | /* 343 */ "C_ULE_D32\000" |
| 7154 | /* 353 */ "C_LE_D32\000" |
| 7155 | /* 362 */ "C_SF_D32\000" |
| 7156 | /* 371 */ "MOVF_D32\000" |
| 7157 | /* 380 */ "C_F_D32\000" |
| 7158 | /* 388 */ "PseudoSELECTFP_F_D32\000" |
| 7159 | /* 409 */ "FNEG_D32\000" |
| 7160 | /* 418 */ "MOVN_I_D32\000" |
| 7161 | /* 429 */ "MOVZ_I_D32\000" |
| 7162 | /* 440 */ "C_NGL_D32\000" |
| 7163 | /* 450 */ "FMUL_D32\000" |
| 7164 | /* 459 */ "LDC1_MM_D32\000" |
| 7165 | /* 471 */ "SDC1_MM_D32\000" |
| 7166 | /* 483 */ "C_UN_D32\000" |
| 7167 | /* 492 */ "RECIP_D32\000" |
| 7168 | /* 502 */ "FCMP_D32\000" |
| 7169 | /* 511 */ "C_SEQ_D32\000" |
| 7170 | /* 521 */ "C_UEQ_D32\000" |
| 7171 | /* 531 */ "C_EQ_D32\000" |
| 7172 | /* 540 */ "FABS_D32\000" |
| 7173 | /* 549 */ "CVT_S_D32\000" |
| 7174 | /* 559 */ "PseudoSELECT_D32\000" |
| 7175 | /* 576 */ "C_NGT_D32\000" |
| 7176 | /* 586 */ "C_OLT_D32\000" |
| 7177 | /* 596 */ "C_ULT_D32\000" |
| 7178 | /* 606 */ "C_LT_D32\000" |
| 7179 | /* 615 */ "FSQRT_D32\000" |
| 7180 | /* 625 */ "RSQRT_D32\000" |
| 7181 | /* 635 */ "MOVT_D32\000" |
| 7182 | /* 644 */ "PseudoSELECTFP_T_D32\000" |
| 7183 | /* 665 */ "FDIV_D32\000" |
| 7184 | /* 674 */ "FMOV_D32\000" |
| 7185 | /* 683 */ "PseudoTRUNC_W_D32\000" |
| 7186 | /* 701 */ "ROUND_W_D32\000" |
| 7187 | /* 713 */ "CEIL_W_D32\000" |
| 7188 | /* 724 */ "FLOOR_W_D32\000" |
| 7189 | /* 736 */ "CVT_W_D32\000" |
| 7190 | /* 746 */ "BPOSGE32\000" |
| 7191 | /* 755 */ "ATOMIC_LOAD_SUB_I32\000" |
| 7192 | /* 775 */ "ATOMIC_LOAD_ADD_I32\000" |
| 7193 | /* 795 */ "ATOMIC_LOAD_NAND_I32\000" |
| 7194 | /* 816 */ "ATOMIC_LOAD_AND_I32\000" |
| 7195 | /* 836 */ "ATOMIC_LOAD_UMIN_I32\000" |
| 7196 | /* 857 */ "ATOMIC_LOAD_MIN_I32\000" |
| 7197 | /* 877 */ "ATOMIC_SWAP_I32\000" |
| 7198 | /* 893 */ "ATOMIC_CMP_SWAP_I32\000" |
| 7199 | /* 913 */ "ATOMIC_LOAD_XOR_I32\000" |
| 7200 | /* 933 */ "ATOMIC_LOAD_OR_I32\000" |
| 7201 | /* 952 */ "ATOMIC_LOAD_UMAX_I32\000" |
| 7202 | /* 973 */ "ATOMIC_LOAD_MAX_I32\000" |
| 7203 | /* 993 */ "DSLL32\000" |
| 7204 | /* 1000 */ "DSRL32\000" |
| 7205 | /* 1007 */ "DROTR32\000" |
| 7206 | /* 1015 */ "CINS32\000" |
| 7207 | /* 1022 */ "EXTS32\000" |
| 7208 | /* 1029 */ "FCMP_S32\000" |
| 7209 | /* 1038 */ "DSLL64_32\000" |
| 7210 | /* 1048 */ "CINS64_32\000" |
| 7211 | /* 1058 */ "DEXT64_32\000" |
| 7212 | /* 1068 */ "LoadImmDoubleFGR_32\000" |
| 7213 | /* 1088 */ "LoadAddrReg32\000" |
| 7214 | /* 1102 */ "CINS_i32\000" |
| 7215 | /* 1111 */ "LoadImm32\000" |
| 7216 | /* 1121 */ "LoadAddrImm32\000" |
| 7217 | /* 1135 */ "MIPSeh_return32\000" |
| 7218 | /* 1151 */ "LwConstant32\000" |
| 7219 | /* 1164 */ "LDC2\000" |
| 7220 | /* 1169 */ "SDC2\000" |
| 7221 | /* 1174 */ "DMFC2\000" |
| 7222 | /* 1180 */ "DMTC2\000" |
| 7223 | /* 1186 */ "LWC2\000" |
| 7224 | /* 1191 */ "SWC2\000" |
| 7225 | /* 1196 */ "G_FLOG2\000" |
| 7226 | /* 1204 */ "MTM2\000" |
| 7227 | /* 1209 */ "G_FATAN2\000" |
| 7228 | /* 1218 */ "MTP2\000" |
| 7229 | /* 1223 */ "G_FEXP2\000" |
| 7230 | /* 1231 */ "SHRA_QB_MMR2\000" |
| 7231 | /* 1244 */ "CMPGDU_LE_QB_MMR2\000" |
| 7232 | /* 1262 */ "SUBUH_QB_MMR2\000" |
| 7233 | /* 1276 */ "ADDUH_QB_MMR2\000" |
| 7234 | /* 1290 */ "CMPGDU_EQ_QB_MMR2\000" |
| 7235 | /* 1308 */ "SHRA_R_QB_MMR2\000" |
| 7236 | /* 1323 */ "SUBUH_R_QB_MMR2\000" |
| 7237 | /* 1339 */ "ADDUH_R_QB_MMR2\000" |
| 7238 | /* 1355 */ "SHRAV_R_QB_MMR2\000" |
| 7239 | /* 1371 */ "ABSQ_S_QB_MMR2\000" |
| 7240 | /* 1386 */ "CMPGDU_LT_QB_MMR2\000" |
| 7241 | /* 1404 */ "SHRAV_QB_MMR2\000" |
| 7242 | /* 1418 */ "PREPEND_MMR2\000" |
| 7243 | /* 1431 */ "APPEND_MMR2\000" |
| 7244 | /* 1443 */ "PRECR_QB_PH_MMR2\000" |
| 7245 | /* 1460 */ "SUBQH_PH_MMR2\000" |
| 7246 | /* 1474 */ "ADDQH_PH_MMR2\000" |
| 7247 | /* 1488 */ "SHRL_PH_MMR2\000" |
| 7248 | /* 1501 */ "MUL_PH_MMR2\000" |
| 7249 | /* 1513 */ "SUBQH_R_PH_MMR2\000" |
| 7250 | /* 1529 */ "ADDQH_R_PH_MMR2\000" |
| 7251 | /* 1545 */ "MUL_S_PH_MMR2\000" |
| 7252 | /* 1559 */ "MULQ_S_PH_MMR2\000" |
| 7253 | /* 1574 */ "SUBU_S_PH_MMR2\000" |
| 7254 | /* 1589 */ "ADDU_S_PH_MMR2\000" |
| 7255 | /* 1604 */ "SUBU_PH_MMR2\000" |
| 7256 | /* 1617 */ "ADDU_PH_MMR2\000" |
| 7257 | /* 1630 */ "SHRLV_PH_MMR2\000" |
| 7258 | /* 1644 */ "DPA_W_PH_MMR2\000" |
| 7259 | /* 1658 */ "MULSA_W_PH_MMR2\000" |
| 7260 | /* 1674 */ "DPAQX_SA_W_PH_MMR2\000" |
| 7261 | /* 1693 */ "DPSQX_SA_W_PH_MMR2\000" |
| 7262 | /* 1712 */ "DPS_W_PH_MMR2\000" |
| 7263 | /* 1726 */ "DPAQX_S_W_PH_MMR2\000" |
| 7264 | /* 1744 */ "DPSQX_S_W_PH_MMR2\000" |
| 7265 | /* 1762 */ "DPAX_W_PH_MMR2\000" |
| 7266 | /* 1777 */ "DPSX_W_PH_MMR2\000" |
| 7267 | /* 1792 */ "BALIGN_MMR2\000" |
| 7268 | /* 1804 */ "PRECR_SRA_PH_W_MMR2\000" |
| 7269 | /* 1824 */ "PRECR_SRA_R_PH_W_MMR2\000" |
| 7270 | /* 1846 */ "SUBQH_W_MMR2\000" |
| 7271 | /* 1859 */ "ADDQH_W_MMR2\000" |
| 7272 | /* 1872 */ "SUBQH_R_W_MMR2\000" |
| 7273 | /* 1887 */ "ADDQH_R_W_MMR2\000" |
| 7274 | /* 1902 */ "MULQ_RS_W_MMR2\000" |
| 7275 | /* 1917 */ "MULQ_S_W_MMR2\000" |
| 7276 | /* 1931 */ "LDC3\000" |
| 7277 | /* 1936 */ "SDC3\000" |
| 7278 | /* 1941 */ "LWC3\000" |
| 7279 | /* 1946 */ "SWC3\000" |
| 7280 | /* 1951 */ "BPOSGE32C_MMR3\000" |
| 7281 | /* 1966 */ "LDC164\000" |
| 7282 | /* 1973 */ "SDC164\000" |
| 7283 | /* 1980 */ "LDXC164\000" |
| 7284 | /* 1988 */ "SDXC164\000" |
| 7285 | /* 1996 */ "LUXC164\000" |
| 7286 | /* 2004 */ "SUXC164\000" |
| 7287 | /* 2012 */ "SEB64\000" |
| 7288 | /* 2018 */ "TAILCALLREGHB64\000" |
| 7289 | /* 2034 */ "JR_HB64\000" |
| 7290 | /* 2042 */ "JALR_HB64\000" |
| 7291 | /* 2052 */ "LB64\000" |
| 7292 | /* 2057 */ "SB64\000" |
| 7293 | /* 2062 */ "LOAD_ACC64\000" |
| 7294 | /* 2073 */ "STORE_ACC64\000" |
| 7295 | /* 2085 */ "BGEC64\000" |
| 7296 | /* 2092 */ "BNEC64\000" |
| 7297 | /* 2099 */ "JIC64\000" |
| 7298 | /* 2105 */ "JIALC64\000" |
| 7299 | /* 2113 */ "BEQC64\000" |
| 7300 | /* 2120 */ "SC64\000" |
| 7301 | /* 2125 */ "BLTC64\000" |
| 7302 | /* 2132 */ "BGEUC64\000" |
| 7303 | /* 2140 */ "BLTUC64\000" |
| 7304 | /* 2148 */ "BGEZC64\000" |
| 7305 | /* 2156 */ "BLEZC64\000" |
| 7306 | /* 2164 */ "BNEZC64\000" |
| 7307 | /* 2172 */ "BEQZC64\000" |
| 7308 | /* 2180 */ "BGTZC64\000" |
| 7309 | /* 2188 */ "BLTZC64\000" |
| 7310 | /* 2196 */ "AND64\000" |
| 7311 | /* 2202 */ "MFC1_D64\000" |
| 7312 | /* 2211 */ "MFHC1_D64\000" |
| 7313 | /* 2221 */ "MTHC1_D64\000" |
| 7314 | /* 2231 */ "MTC1_D64\000" |
| 7315 | /* 2240 */ "MOVN_I64_D64\000" |
| 7316 | /* 2253 */ "MOVZ_I64_D64\000" |
| 7317 | /* 2266 */ "FSUB_D64\000" |
| 7318 | /* 2275 */ "NMSUB_D64\000" |
| 7319 | /* 2285 */ "FADD_D64\000" |
| 7320 | /* 2294 */ "NMADD_D64\000" |
| 7321 | /* 2304 */ "C_NGE_D64\000" |
| 7322 | /* 2314 */ "C_NGLE_D64\000" |
| 7323 | /* 2325 */ "C_OLE_D64\000" |
| 7324 | /* 2335 */ "C_ULE_D64\000" |
| 7325 | /* 2345 */ "C_LE_D64\000" |
| 7326 | /* 2354 */ "C_SF_D64\000" |
| 7327 | /* 2363 */ "MOVF_D64\000" |
| 7328 | /* 2372 */ "C_F_D64\000" |
| 7329 | /* 2380 */ "PseudoSELECTFP_F_D64\000" |
| 7330 | /* 2401 */ "FNEG_D64\000" |
| 7331 | /* 2410 */ "MOVN_I_D64\000" |
| 7332 | /* 2421 */ "MOVZ_I_D64\000" |
| 7333 | /* 2432 */ "C_NGL_D64\000" |
| 7334 | /* 2442 */ "FMUL_D64\000" |
| 7335 | /* 2451 */ "TRUNC_L_D64\000" |
| 7336 | /* 2463 */ "ROUND_L_D64\000" |
| 7337 | /* 2475 */ "CEIL_L_D64\000" |
| 7338 | /* 2486 */ "FLOOR_L_D64\000" |
| 7339 | /* 2498 */ "CVT_L_D64\000" |
| 7340 | /* 2508 */ "LDC1_MM_D64\000" |
| 7341 | /* 2520 */ "SDC1_MM_D64\000" |
| 7342 | /* 2532 */ "C_UN_D64\000" |
| 7343 | /* 2541 */ "RECIP_D64\000" |
| 7344 | /* 2551 */ "FCMP_D64\000" |
| 7345 | /* 2560 */ "C_SEQ_D64\000" |
| 7346 | /* 2570 */ "C_UEQ_D64\000" |
| 7347 | /* 2580 */ "C_EQ_D64\000" |
| 7348 | /* 2589 */ "FABS_D64\000" |
| 7349 | /* 2598 */ "CVT_S_D64\000" |
| 7350 | /* 2608 */ "PseudoSELECT_D64\000" |
| 7351 | /* 2625 */ "C_NGT_D64\000" |
| 7352 | /* 2635 */ "C_OLT_D64\000" |
| 7353 | /* 2645 */ "C_ULT_D64\000" |
| 7354 | /* 2655 */ "C_LT_D64\000" |
| 7355 | /* 2664 */ "FSQRT_D64\000" |
| 7356 | /* 2674 */ "RSQRT_D64\000" |
| 7357 | /* 2684 */ "MOVT_D64\000" |
| 7358 | /* 2693 */ "PseudoSELECTFP_T_D64\000" |
| 7359 | /* 2714 */ "FDIV_D64\000" |
| 7360 | /* 2723 */ "FMOV_D64\000" |
| 7361 | /* 2732 */ "TRUNC_W_D64\000" |
| 7362 | /* 2744 */ "ROUND_W_D64\000" |
| 7363 | /* 2756 */ "CEIL_W_D64\000" |
| 7364 | /* 2767 */ "FLOOR_W_D64\000" |
| 7365 | /* 2779 */ "CVT_W_D64\000" |
| 7366 | /* 2789 */ "BNE64\000" |
| 7367 | /* 2795 */ "BuildPairF64\000" |
| 7368 | /* 2808 */ "ExtractElementF64\000" |
| 7369 | /* 2826 */ "TAILCALLREG64\000" |
| 7370 | /* 2840 */ "SEH64\000" |
| 7371 | /* 2846 */ "LH64\000" |
| 7372 | /* 2851 */ "SH64\000" |
| 7373 | /* 2856 */ "PseudoMFHI64\000" |
| 7374 | /* 2869 */ "PseudoMTLOHI64\000" |
| 7375 | /* 2884 */ "MTHI64\000" |
| 7376 | /* 2891 */ "MOVN_I64_I64\000" |
| 7377 | /* 2904 */ "MOVZ_I64_I64\000" |
| 7378 | /* 2917 */ "ATOMIC_LOAD_SUB_I64\000" |
| 7379 | /* 2937 */ "ATOMIC_LOAD_ADD_I64\000" |
| 7380 | /* 2957 */ "ATOMIC_LOAD_NAND_I64\000" |
| 7381 | /* 2978 */ "ATOMIC_LOAD_AND_I64\000" |
| 7382 | /* 2998 */ "MOVF_I64\000" |
| 7383 | /* 3007 */ "PseudoSELECTFP_F_I64\000" |
| 7384 | /* 3028 */ "MOVN_I_I64\000" |
| 7385 | /* 3039 */ "MOVZ_I_I64\000" |
| 7386 | /* 3050 */ "ATOMIC_LOAD_UMIN_I64\000" |
| 7387 | /* 3071 */ "ATOMIC_LOAD_MIN_I64\000" |
| 7388 | /* 3091 */ "ATOMIC_SWAP_I64\000" |
| 7389 | /* 3107 */ "ATOMIC_CMP_SWAP_I64\000" |
| 7390 | /* 3127 */ "ATOMIC_LOAD_XOR_I64\000" |
| 7391 | /* 3147 */ "ATOMIC_LOAD_OR_I64\000" |
| 7392 | /* 3166 */ "PseudoD_SELECT_I64\000" |
| 7393 | /* 3185 */ "PseudoSELECT_I64\000" |
| 7394 | /* 3202 */ "MOVT_I64\000" |
| 7395 | /* 3211 */ "PseudoSELECTFP_T_I64\000" |
| 7396 | /* 3232 */ "ATOMIC_LOAD_UMAX_I64\000" |
| 7397 | /* 3253 */ "ATOMIC_LOAD_MAX_I64\000" |
| 7398 | /* 3273 */ "LL64\000" |
| 7399 | /* 3278 */ "CVT_S_PL64\000" |
| 7400 | /* 3289 */ "LWL64\000" |
| 7401 | /* 3295 */ "SWL64\000" |
| 7402 | /* 3301 */ "PseudoMFLO64\000" |
| 7403 | /* 3314 */ "MTLO64\000" |
| 7404 | /* 3321 */ "BEQ64\000" |
| 7405 | /* 3327 */ "JR64\000" |
| 7406 | /* 3332 */ "JALR64\000" |
| 7407 | /* 3339 */ "NOR64\000" |
| 7408 | /* 3345 */ "XOR64\000" |
| 7409 | /* 3351 */ "RDHWR64\000" |
| 7410 | /* 3359 */ "LWR64\000" |
| 7411 | /* 3365 */ "SWR64\000" |
| 7412 | /* 3371 */ "FSUB_PS64\000" |
| 7413 | /* 3381 */ "FADD_PS64\000" |
| 7414 | /* 3391 */ "PLL_PS64\000" |
| 7415 | /* 3400 */ "FMUL_PS64\000" |
| 7416 | /* 3410 */ "PUL_PS64\000" |
| 7417 | /* 3419 */ "ADDR_PS64\000" |
| 7418 | /* 3429 */ "MULR_PS64\000" |
| 7419 | /* 3439 */ "PLU_PS64\000" |
| 7420 | /* 3448 */ "PUU_PS64\000" |
| 7421 | /* 3457 */ "CVT_PW_PS64\000" |
| 7422 | /* 3469 */ "CVT_PS_S64\000" |
| 7423 | /* 3480 */ "SLT64\000" |
| 7424 | /* 3486 */ "CVT_S_PU64\000" |
| 7425 | /* 3497 */ "LW64\000" |
| 7426 | /* 3502 */ "CVT_PS_PW64\000" |
| 7427 | /* 3514 */ "SW64\000" |
| 7428 | /* 3519 */ "BGEZ64\000" |
| 7429 | /* 3526 */ "BLEZ64\000" |
| 7430 | /* 3533 */ "SELNEZ64\000" |
| 7431 | /* 3542 */ "SELEQZ64\000" |
| 7432 | /* 3551 */ "BGTZ64\000" |
| 7433 | /* 3558 */ "BLTZ64\000" |
| 7434 | /* 3565 */ "BuildPairF64_64\000" |
| 7435 | /* 3581 */ "ExtractElementF64_64\000" |
| 7436 | /* 3602 */ "SLL64_64\000" |
| 7437 | /* 3611 */ "LONG_BRANCH_LUi2Op_64\000" |
| 7438 | /* 3633 */ "LoadAddrReg64\000" |
| 7439 | /* 3647 */ "PseudoIndirectHazardBranch64\000" |
| 7440 | /* 3676 */ "PseudoIndirectBranch64\000" |
| 7441 | /* 3699 */ "ANDi64\000" |
| 7442 | /* 3706 */ "XORi64\000" |
| 7443 | /* 3713 */ "SLTi64\000" |
| 7444 | /* 3720 */ "LUi64\000" |
| 7445 | /* 3726 */ "SGEImm64\000" |
| 7446 | /* 3735 */ "SLEImm64\000" |
| 7447 | /* 3744 */ "NORImm64\000" |
| 7448 | /* 3753 */ "SGTImm64\000" |
| 7449 | /* 3762 */ "SLTImm64\000" |
| 7450 | /* 3771 */ "SGEUImm64\000" |
| 7451 | /* 3781 */ "SLEUImm64\000" |
| 7452 | /* 3791 */ "SGTUImm64\000" |
| 7453 | /* 3801 */ "SLTUImm64\000" |
| 7454 | /* 3811 */ "LoadImm64\000" |
| 7455 | /* 3821 */ "LoadAddrImm64\000" |
| 7456 | /* 3835 */ "PseudoReturn64\000" |
| 7457 | /* 3850 */ "MIPSeh_return64\000" |
| 7458 | /* 3866 */ "LBu64\000" |
| 7459 | /* 3872 */ "LHu64\000" |
| 7460 | /* 3878 */ "SLTu64\000" |
| 7461 | /* 3885 */ "LEA_ADDiu64\000" |
| 7462 | /* 3897 */ "SLTiu64\000" |
| 7463 | /* 3905 */ "MoveR3216\000" |
| 7464 | /* 3915 */ "RetRA16\000" |
| 7465 | /* 3923 */ "JalB16\000" |
| 7466 | /* 3930 */ "ATOMIC_LOAD_SUB_I16\000" |
| 7467 | /* 3950 */ "ATOMIC_LOAD_ADD_I16\000" |
| 7468 | /* 3970 */ "ATOMIC_LOAD_NAND_I16\000" |
| 7469 | /* 3991 */ "ATOMIC_LOAD_AND_I16\000" |
| 7470 | /* 4011 */ "ATOMIC_LOAD_UMIN_I16\000" |
| 7471 | /* 4032 */ "ATOMIC_LOAD_MIN_I16\000" |
| 7472 | /* 4052 */ "ATOMIC_SWAP_I16\000" |
| 7473 | /* 4068 */ "ATOMIC_CMP_SWAP_I16\000" |
| 7474 | /* 4088 */ "ATOMIC_LOAD_XOR_I16\000" |
| 7475 | /* 4108 */ "ATOMIC_LOAD_OR_I16\000" |
| 7476 | /* 4127 */ "ATOMIC_LOAD_UMAX_I16\000" |
| 7477 | /* 4148 */ "ATOMIC_LOAD_MAX_I16\000" |
| 7478 | /* 4168 */ "Move32R16\000" |
| 7479 | /* 4178 */ "SraX16\000" |
| 7480 | /* 4185 */ "RestoreX16\000" |
| 7481 | /* 4196 */ "SaveX16\000" |
| 7482 | /* 4204 */ "BtnezT8CmpiX16\000" |
| 7483 | /* 4219 */ "BteqzT8CmpiX16\000" |
| 7484 | /* 4234 */ "BtnezT8SltiX16\000" |
| 7485 | /* 4249 */ "BteqzT8SltiX16\000" |
| 7486 | /* 4264 */ "SllX16\000" |
| 7487 | /* 4271 */ "SrlX16\000" |
| 7488 | /* 4278 */ "LbRxRyOffMemX16\000" |
| 7489 | /* 4294 */ "SbRxRyOffMemX16\000" |
| 7490 | /* 4310 */ "LhRxRyOffMemX16\000" |
| 7491 | /* 4326 */ "ShRxRyOffMemX16\000" |
| 7492 | /* 4342 */ "LbuRxRyOffMemX16\000" |
| 7493 | /* 4359 */ "LhuRxRyOffMemX16\000" |
| 7494 | /* 4376 */ "AddiuRxRyOffMemX16\000" |
| 7495 | /* 4395 */ "LwRxRyOffMemX16\000" |
| 7496 | /* 4411 */ "SwRxRyOffMemX16\000" |
| 7497 | /* 4427 */ "AddiuRxPcImmX16\000" |
| 7498 | /* 4443 */ "AddiuSpImmX16\000" |
| 7499 | /* 4457 */ "LwRxSpImmX16\000" |
| 7500 | /* 4470 */ "SwRxSpImmX16\000" |
| 7501 | /* 4483 */ "SltiCCRxImmX16\000" |
| 7502 | /* 4498 */ "SltiuCCRxImmX16\000" |
| 7503 | /* 4514 */ "LiRxImmX16\000" |
| 7504 | /* 4525 */ "CmpiRxImmX16\000" |
| 7505 | /* 4538 */ "SltiRxImmX16\000" |
| 7506 | /* 4551 */ "AddiuRxImmX16\000" |
| 7507 | /* 4565 */ "SltiuRxImmX16\000" |
| 7508 | /* 4579 */ "AddiuRxRxImmX16\000" |
| 7509 | /* 4595 */ "BnezRxImmX16\000" |
| 7510 | /* 4608 */ "BeqzRxImmX16\000" |
| 7511 | /* 4621 */ "BimmX16\000" |
| 7512 | /* 4629 */ "LiRxImmAlignX16\000" |
| 7513 | /* 4645 */ "LwRxPcTcpX16\000" |
| 7514 | /* 4658 */ "BtnezT8CmpX16\000" |
| 7515 | /* 4672 */ "BteqzT8CmpX16\000" |
| 7516 | /* 4686 */ "BtnezT8SltX16\000" |
| 7517 | /* 4700 */ "BteqzT8SltX16\000" |
| 7518 | /* 4714 */ "BtnezT8SltiuX16\000" |
| 7519 | /* 4730 */ "BteqzT8SltiuX16\000" |
| 7520 | /* 4746 */ "BtnezT8SltuX16\000" |
| 7521 | /* 4761 */ "BteqzT8SltuX16\000" |
| 7522 | /* 4776 */ "BtnezX16\000" |
| 7523 | /* 4785 */ "BteqzX16\000" |
| 7524 | /* 4794 */ "JrcRa16\000" |
| 7525 | /* 4802 */ "JrRa16\000" |
| 7526 | /* 4809 */ "Restore16\000" |
| 7527 | /* 4819 */ "GotPrologue16\000" |
| 7528 | /* 4833 */ "Save16\000" |
| 7529 | /* 4840 */ "JumpLinkReg16\000" |
| 7530 | /* 4854 */ "Mfhi16\000" |
| 7531 | /* 4861 */ "Break16\000" |
| 7532 | /* 4869 */ "Jal16\000" |
| 7533 | /* 4875 */ "AddiuSpImm16\000" |
| 7534 | /* 4888 */ "LiRxImm16\000" |
| 7535 | /* 4898 */ "CmpiRxImm16\000" |
| 7536 | /* 4910 */ "SltiRxImm16\000" |
| 7537 | /* 4922 */ "SltiuRxImm16\000" |
| 7538 | /* 4935 */ "AddiuRxRxImm16\000" |
| 7539 | /* 4950 */ "BnezRxImm16\000" |
| 7540 | /* 4962 */ "BeqzRxImm16\000" |
| 7541 | /* 4974 */ "Bimm16\000" |
| 7542 | /* 4981 */ "Mflo16\000" |
| 7543 | /* 4988 */ "LwRxPcTcp16\000" |
| 7544 | /* 5000 */ "SebRx16\000" |
| 7545 | /* 5008 */ "JrcRx16\000" |
| 7546 | /* 5016 */ "SehRx16\000" |
| 7547 | /* 5024 */ "SltCCRxRy16\000" |
| 7548 | /* 5036 */ "SltuCCRxRy16\000" |
| 7549 | /* 5049 */ "NegRxRy16\000" |
| 7550 | /* 5059 */ "CmpRxRy16\000" |
| 7551 | /* 5069 */ "SltRxRy16\000" |
| 7552 | /* 5079 */ "MultRxRy16\000" |
| 7553 | /* 5090 */ "NotRxRy16\000" |
| 7554 | /* 5100 */ "SltuRxRy16\000" |
| 7555 | /* 5111 */ "MultuRxRy16\000" |
| 7556 | /* 5123 */ "DivuRxRy16\000" |
| 7557 | /* 5134 */ "SravRxRy16\000" |
| 7558 | /* 5145 */ "DivRxRy16\000" |
| 7559 | /* 5155 */ "SllvRxRy16\000" |
| 7560 | /* 5166 */ "SrlvRxRy16\000" |
| 7561 | /* 5177 */ "AndRxRxRy16\000" |
| 7562 | /* 5189 */ "OrRxRxRy16\000" |
| 7563 | /* 5200 */ "XorRxRxRy16\000" |
| 7564 | /* 5212 */ "MultRxRyRz16\000" |
| 7565 | /* 5225 */ "SubuRxRyRz16\000" |
| 7566 | /* 5238 */ "AdduRxRyRz16\000" |
| 7567 | /* 5251 */ "SltuRxRyRz16\000" |
| 7568 | /* 5264 */ "MultuRxRyRz16\000" |
| 7569 | /* 5278 */ "Btnez16\000" |
| 7570 | /* 5286 */ "Bteqz16\000" |
| 7571 | /* 5294 */ "PseudoIndrectHazardBranch64R6\000" |
| 7572 | /* 5324 */ "PseudoIndirectBranch64R6\000" |
| 7573 | /* 5349 */ "MFC0_MMR6\000" |
| 7574 | /* 5359 */ "MFHC0_MMR6\000" |
| 7575 | /* 5370 */ "MTHC0_MMR6\000" |
| 7576 | /* 5381 */ "MTC0_MMR6\000" |
| 7577 | /* 5391 */ "MFC1_MMR6\000" |
| 7578 | /* 5401 */ "MTC1_MMR6\000" |
| 7579 | /* 5411 */ "LDC2_MMR6\000" |
| 7580 | /* 5421 */ "SDC2_MMR6\000" |
| 7581 | /* 5431 */ "MFC2_MMR6\000" |
| 7582 | /* 5441 */ "MFHC2_MMR6\000" |
| 7583 | /* 5452 */ "MTHC2_MMR6\000" |
| 7584 | /* 5463 */ "MTC2_MMR6\000" |
| 7585 | /* 5473 */ "LWC2_MMR6\000" |
| 7586 | /* 5483 */ "SWC2_MMR6\000" |
| 7587 | /* 5493 */ "LDC1_D64_MMR6\000" |
| 7588 | /* 5507 */ "SDC1_D64_MMR6\000" |
| 7589 | /* 5521 */ "SB16_MMR6\000" |
| 7590 | /* 5531 */ "BC16_MMR6\000" |
| 7591 | /* 5541 */ "JRC16_MMR6\000" |
| 7592 | /* 5552 */ "JALRC16_MMR6\000" |
| 7593 | /* 5565 */ "BNEZC16_MMR6\000" |
| 7594 | /* 5578 */ "BEQZC16_MMR6\000" |
| 7595 | /* 5591 */ "AND16_MMR6\000" |
| 7596 | /* 5602 */ "MOVE16_MMR6\000" |
| 7597 | /* 5614 */ "SH16_MMR6\000" |
| 7598 | /* 5624 */ "ANDI16_MMR6\000" |
| 7599 | /* 5636 */ "LI16_MMR6\000" |
| 7600 | /* 5646 */ "BREAK16_MMR6\000" |
| 7601 | /* 5659 */ "SLL16_MMR6\000" |
| 7602 | /* 5670 */ "SRL16_MMR6\000" |
| 7603 | /* 5681 */ "LWM16_MMR6\000" |
| 7604 | /* 5692 */ "SWM16_MMR6\000" |
| 7605 | /* 5703 */ "SDBBP16_MMR6\000" |
| 7606 | /* 5716 */ "XOR16_MMR6\000" |
| 7607 | /* 5727 */ "NOT16_MMR6\000" |
| 7608 | /* 5738 */ "SUBU16_MMR6\000" |
| 7609 | /* 5750 */ "ADDU16_MMR6\000" |
| 7610 | /* 5762 */ "SW16_MMR6\000" |
| 7611 | /* 5772 */ "LSA_MMR6\000" |
| 7612 | /* 5781 */ "EHB_MMR6\000" |
| 7613 | /* 5790 */ "JALRC_HB_MMR6\000" |
| 7614 | /* 5804 */ "LB_MMR6\000" |
| 7615 | /* 5812 */ "SB_MMR6\000" |
| 7616 | /* 5820 */ "SUB_MMR6\000" |
| 7617 | /* 5829 */ "BC_MMR6\000" |
| 7618 | /* 5837 */ "BGEC_MMR6\000" |
| 7619 | /* 5847 */ "BNEC_MMR6\000" |
| 7620 | /* 5857 */ "JIC_MMR6\000" |
| 7621 | /* 5866 */ "BALC_MMR6\000" |
| 7622 | /* 5876 */ "JIALC_MMR6\000" |
| 7623 | /* 5887 */ "BGEZALC_MMR6\000" |
| 7624 | /* 5900 */ "BLEZALC_MMR6\000" |
| 7625 | /* 5913 */ "BNEZALC_MMR6\000" |
| 7626 | /* 5926 */ "BEQZALC_MMR6\000" |
| 7627 | /* 5939 */ "BGTZALC_MMR6\000" |
| 7628 | /* 5952 */ "BLTZALC_MMR6\000" |
| 7629 | /* 5965 */ "ERETNC_MMR6\000" |
| 7630 | /* 5977 */ "SYNC_MMR6\000" |
| 7631 | /* 5987 */ "AUIPC_MMR6\000" |
| 7632 | /* 5998 */ "ALUIPC_MMR6\000" |
| 7633 | /* 6010 */ "ADDIUPC_MMR6\000" |
| 7634 | /* 6023 */ "LWPC_MMR6\000" |
| 7635 | /* 6033 */ "BEQC_MMR6\000" |
| 7636 | /* 6043 */ "JALRC_MMR6\000" |
| 7637 | /* 6054 */ "SC_MMR6\000" |
| 7638 | /* 6062 */ "BLTC_MMR6\000" |
| 7639 | /* 6072 */ "BGEUC_MMR6\000" |
| 7640 | /* 6083 */ "BLTUC_MMR6\000" |
| 7641 | /* 6094 */ "BNVC_MMR6\000" |
| 7642 | /* 6104 */ "BOVC_MMR6\000" |
| 7643 | /* 6114 */ "BGEZC_MMR6\000" |
| 7644 | /* 6125 */ "BLEZC_MMR6\000" |
| 7645 | /* 6136 */ "BC1NEZC_MMR6\000" |
| 7646 | /* 6149 */ "BC2NEZC_MMR6\000" |
| 7647 | /* 6162 */ "BNEZC_MMR6\000" |
| 7648 | /* 6173 */ "BC1EQZC_MMR6\000" |
| 7649 | /* 6186 */ "BC2EQZC_MMR6\000" |
| 7650 | /* 6199 */ "BEQZC_MMR6\000" |
| 7651 | /* 6210 */ "BGTZC_MMR6\000" |
| 7652 | /* 6221 */ "BLTZC_MMR6\000" |
| 7653 | /* 6232 */ "ADD_MMR6\000" |
| 7654 | /* 6241 */ "AND_MMR6\000" |
| 7655 | /* 6250 */ "MOD_MMR6\000" |
| 7656 | /* 6259 */ "MINA_D_MMR6\000" |
| 7657 | /* 6271 */ "MAXA_D_MMR6\000" |
| 7658 | /* 6283 */ "CMP_SLE_D_MMR6\000" |
| 7659 | /* 6298 */ "CMP_SULE_D_MMR6\000" |
| 7660 | /* 6314 */ "CMP_ULE_D_MMR6\000" |
| 7661 | /* 6329 */ "CMP_LE_D_MMR6\000" |
| 7662 | /* 6343 */ "CMP_SAF_D_MMR6\000" |
| 7663 | /* 6358 */ "CMP_AF_D_MMR6\000" |
| 7664 | /* 6372 */ "MSUBF_D_MMR6\000" |
| 7665 | /* 6385 */ "MADDF_D_MMR6\000" |
| 7666 | /* 6398 */ "SEL_D_MMR6\000" |
| 7667 | /* 6409 */ "TRUNC_L_D_MMR6\000" |
| 7668 | /* 6424 */ "ROUND_L_D_MMR6\000" |
| 7669 | /* 6439 */ "CEIL_L_D_MMR6\000" |
| 7670 | /* 6453 */ "FLOOR_L_D_MMR6\000" |
| 7671 | /* 6468 */ "CVT_L_D_MMR6\000" |
| 7672 | /* 6481 */ "MIN_D_MMR6\000" |
| 7673 | /* 6492 */ "CMP_SUN_D_MMR6\000" |
| 7674 | /* 6507 */ "CMP_UN_D_MMR6\000" |
| 7675 | /* 6521 */ "CMP_SEQ_D_MMR6\000" |
| 7676 | /* 6536 */ "CMP_SUEQ_D_MMR6\000" |
| 7677 | /* 6552 */ "CMP_UEQ_D_MMR6\000" |
| 7678 | /* 6567 */ "CMP_EQ_D_MMR6\000" |
| 7679 | /* 6581 */ "CLASS_D_MMR6\000" |
| 7680 | /* 6594 */ "CMP_SLT_D_MMR6\000" |
| 7681 | /* 6609 */ "CMP_SULT_D_MMR6\000" |
| 7682 | /* 6625 */ "CMP_ULT_D_MMR6\000" |
| 7683 | /* 6640 */ "CMP_LT_D_MMR6\000" |
| 7684 | /* 6654 */ "RINT_D_MMR6\000" |
| 7685 | /* 6666 */ "FMOV_D_MMR6\000" |
| 7686 | /* 6678 */ "TRUNC_W_D_MMR6\000" |
| 7687 | /* 6693 */ "ROUND_W_D_MMR6\000" |
| 7688 | /* 6708 */ "CEIL_W_D_MMR6\000" |
| 7689 | /* 6722 */ "FLOOR_W_D_MMR6\000" |
| 7690 | /* 6737 */ "MAX_D_MMR6\000" |
| 7691 | /* 6748 */ "SELNEZ_D_MMR6\000" |
| 7692 | /* 6762 */ "SELEQZ_D_MMR6\000" |
| 7693 | /* 6776 */ "CACHE_MMR6\000" |
| 7694 | /* 6787 */ "SIGRIE_MMR6\000" |
| 7695 | /* 6799 */ "PAUSE_MMR6\000" |
| 7696 | /* 6810 */ "PREF_MMR6\000" |
| 7697 | /* 6820 */ "TLBINVF_MMR6\000" |
| 7698 | /* 6833 */ "TAILCALLREG_MMR6\000" |
| 7699 | /* 6850 */ "WSBH_MMR6\000" |
| 7700 | /* 6860 */ "SH_MMR6\000" |
| 7701 | /* 6868 */ "MUH_MMR6\000" |
| 7702 | /* 6877 */ "SYNCI_MMR6\000" |
| 7703 | /* 6888 */ "ANDI_MMR6\000" |
| 7704 | /* 6898 */ "EI_MMR6\000" |
| 7705 | /* 6906 */ "XORI_MMR6\000" |
| 7706 | /* 6916 */ "AUI_MMR6\000" |
| 7707 | /* 6925 */ "LUI_MMR6\000" |
| 7708 | /* 6934 */ "GINVI_MMR6\000" |
| 7709 | /* 6945 */ "BREAK_MMR6\000" |
| 7710 | /* 6956 */ "JAL_MMR6\000" |
| 7711 | /* 6965 */ "TAILCALL_MMR6\000" |
| 7712 | /* 6979 */ "SLL_MMR6\000" |
| 7713 | /* 6988 */ "MUL_MMR6\000" |
| 7714 | /* 6997 */ "CVT_D_L_MMR6\000" |
| 7715 | /* 7010 */ "CVT_S_L_MMR6\000" |
| 7716 | /* 7023 */ "ALIGN_MMR6\000" |
| 7717 | /* 7034 */ "CLO_MMR6\000" |
| 7718 | /* 7043 */ "BITSWAP_MMR6\000" |
| 7719 | /* 7056 */ "SDBBP_MMR6\000" |
| 7720 | /* 7067 */ "MOVEP_MMR6\000" |
| 7721 | /* 7078 */ "SSNOP_MMR6\000" |
| 7722 | /* 7089 */ "JRCADDIUSP_MMR6\000" |
| 7723 | /* 7105 */ "SWSP_MMR6\000" |
| 7724 | /* 7115 */ "DVP_MMR6\000" |
| 7725 | /* 7124 */ "EVP_MMR6\000" |
| 7726 | /* 7133 */ "NOR_MMR6\000" |
| 7727 | /* 7142 */ "XOR_MMR6\000" |
| 7728 | /* 7151 */ "RDPGPR_MMR6\000" |
| 7729 | /* 7163 */ "WRPGPR_MMR6\000" |
| 7730 | /* 7175 */ "RDHWR_MMR6\000" |
| 7731 | /* 7186 */ "INS_MMR6\000" |
| 7732 | /* 7195 */ "MINA_S_MMR6\000" |
| 7733 | /* 7207 */ "MAXA_S_MMR6\000" |
| 7734 | /* 7219 */ "FSUB_S_MMR6\000" |
| 7735 | /* 7231 */ "FADD_S_MMR6\000" |
| 7736 | /* 7243 */ "CMP_SLE_S_MMR6\000" |
| 7737 | /* 7258 */ "CMP_SULE_S_MMR6\000" |
| 7738 | /* 7274 */ "CMP_ULE_S_MMR6\000" |
| 7739 | /* 7289 */ "CMP_LE_S_MMR6\000" |
| 7740 | /* 7303 */ "CMP_SAF_S_MMR6\000" |
| 7741 | /* 7318 */ "CMP_AF_S_MMR6\000" |
| 7742 | /* 7332 */ "MSUBF_S_MMR6\000" |
| 7743 | /* 7345 */ "MADDF_S_MMR6\000" |
| 7744 | /* 7358 */ "FNEG_S_MMR6\000" |
| 7745 | /* 7370 */ "SEL_S_MMR6\000" |
| 7746 | /* 7381 */ "FMUL_S_MMR6\000" |
| 7747 | /* 7393 */ "TRUNC_L_S_MMR6\000" |
| 7748 | /* 7408 */ "ROUND_L_S_MMR6\000" |
| 7749 | /* 7423 */ "CEIL_L_S_MMR6\000" |
| 7750 | /* 7437 */ "FLOOR_L_S_MMR6\000" |
| 7751 | /* 7452 */ "CVT_L_S_MMR6\000" |
| 7752 | /* 7465 */ "MIN_S_MMR6\000" |
| 7753 | /* 7476 */ "CMP_SUN_S_MMR6\000" |
| 7754 | /* 7491 */ "CMP_UN_S_MMR6\000" |
| 7755 | /* 7505 */ "CMP_SEQ_S_MMR6\000" |
| 7756 | /* 7520 */ "CMP_SUEQ_S_MMR6\000" |
| 7757 | /* 7536 */ "CMP_UEQ_S_MMR6\000" |
| 7758 | /* 7551 */ "CMP_EQ_S_MMR6\000" |
| 7759 | /* 7565 */ "CLASS_S_MMR6\000" |
| 7760 | /* 7578 */ "CMP_SLT_S_MMR6\000" |
| 7761 | /* 7593 */ "CMP_SULT_S_MMR6\000" |
| 7762 | /* 7609 */ "CMP_ULT_S_MMR6\000" |
| 7763 | /* 7624 */ "CMP_LT_S_MMR6\000" |
| 7764 | /* 7638 */ "RINT_S_MMR6\000" |
| 7765 | /* 7650 */ "FDIV_S_MMR6\000" |
| 7766 | /* 7662 */ "FMOV_S_MMR6\000" |
| 7767 | /* 7674 */ "TRUNC_W_S_MMR6\000" |
| 7768 | /* 7689 */ "ROUND_W_S_MMR6\000" |
| 7769 | /* 7704 */ "CEIL_W_S_MMR6\000" |
| 7770 | /* 7718 */ "FLOOR_W_S_MMR6\000" |
| 7771 | /* 7733 */ "CVT_W_S_MMR6\000" |
| 7772 | /* 7746 */ "MAX_S_MMR6\000" |
| 7773 | /* 7757 */ "SELNEZ_S_MMR6\000" |
| 7774 | /* 7771 */ "SELEQZ_S_MMR6\000" |
| 7775 | /* 7785 */ "DERET_MMR6\000" |
| 7776 | /* 7796 */ "WAIT_MMR6\000" |
| 7777 | /* 7806 */ "GINVT_MMR6\000" |
| 7778 | /* 7817 */ "EXT_MMR6\000" |
| 7779 | /* 7826 */ "LBU_MMR6\000" |
| 7780 | /* 7835 */ "SUBU_MMR6\000" |
| 7781 | /* 7845 */ "ADDU_MMR6\000" |
| 7782 | /* 7855 */ "MODU_MMR6\000" |
| 7783 | /* 7865 */ "MUHU_MMR6\000" |
| 7784 | /* 7875 */ "ADDIU_MMR6\000" |
| 7785 | /* 7886 */ "MULU_MMR6\000" |
| 7786 | /* 7896 */ "DIVU_MMR6\000" |
| 7787 | /* 7906 */ "DIV_MMR6\000" |
| 7788 | /* 7915 */ "TLBINV_MMR6\000" |
| 7789 | /* 7927 */ "LW_MMR6\000" |
| 7790 | /* 7935 */ "SW_MMR6\000" |
| 7791 | /* 7943 */ "CVT_S_W_MMR6\000" |
| 7792 | /* 7956 */ "SELNEZ_MMR6\000" |
| 7793 | /* 7968 */ "CLZ_MMR6\000" |
| 7794 | /* 7977 */ "SELEQZ_MMR6\000" |
| 7795 | /* 7989 */ "PseudoIndirectBranch_MMR6\000" |
| 7796 | /* 8015 */ "LDC2_R6\000" |
| 7797 | /* 8023 */ "SDC2_R6\000" |
| 7798 | /* 8031 */ "LWC2_R6\000" |
| 7799 | /* 8039 */ "SWC2_R6\000" |
| 7800 | /* 8047 */ "JR_HB64_R6\000" |
| 7801 | /* 8058 */ "SC64_R6\000" |
| 7802 | /* 8066 */ "LL64_R6\000" |
| 7803 | /* 8074 */ "DLSA_R6\000" |
| 7804 | /* 8082 */ "JR_HB_R6\000" |
| 7805 | /* 8091 */ "SC_R6\000" |
| 7806 | /* 8097 */ "SCD_R6\000" |
| 7807 | /* 8104 */ "LLD_R6\000" |
| 7808 | /* 8111 */ "CACHE_R6\000" |
| 7809 | /* 8120 */ "PREF_R6\000" |
| 7810 | /* 8128 */ "LL_R6\000" |
| 7811 | /* 8134 */ "DMUL_R6\000" |
| 7812 | /* 8142 */ "DCLO_R6\000" |
| 7813 | /* 8150 */ "SDBBP_R6\000" |
| 7814 | /* 8159 */ "DCLZ_R6\000" |
| 7815 | /* 8167 */ "PseudoIndrectHazardBranchR6\000" |
| 7816 | /* 8195 */ "PseudoIndirectBranchR6\000" |
| 7817 | /* 8218 */ "LOAD_ACC128\000" |
| 7818 | /* 8230 */ "STORE_ACC128\000" |
| 7819 | /* 8243 */ "ATOMIC_LOAD_SUB_I8\000" |
| 7820 | /* 8262 */ "ATOMIC_LOAD_ADD_I8\000" |
| 7821 | /* 8281 */ "ATOMIC_LOAD_NAND_I8\000" |
| 7822 | /* 8301 */ "ATOMIC_LOAD_AND_I8\000" |
| 7823 | /* 8320 */ "ATOMIC_LOAD_UMIN_I8\000" |
| 7824 | /* 8340 */ "ATOMIC_LOAD_MIN_I8\000" |
| 7825 | /* 8359 */ "ATOMIC_SWAP_I8\000" |
| 7826 | /* 8374 */ "ATOMIC_CMP_SWAP_I8\000" |
| 7827 | /* 8393 */ "ATOMIC_LOAD_XOR_I8\000" |
| 7828 | /* 8412 */ "ATOMIC_LOAD_OR_I8\000" |
| 7829 | /* 8430 */ "ATOMIC_LOAD_UMAX_I8\000" |
| 7830 | /* 8450 */ "ATOMIC_LOAD_MAX_I8\000" |
| 7831 | /* 8469 */ "SAA\000" |
| 7832 | /* 8473 */ "PRECEU_PH_QBLA\000" |
| 7833 | /* 8488 */ "PRECEQU_PH_QBLA\000" |
| 7834 | /* 8504 */ "G_FMA\000" |
| 7835 | /* 8510 */ "G_STRICT_FMA\000" |
| 7836 | /* 8523 */ "PRECEU_PH_QBRA\000" |
| 7837 | /* 8538 */ "PRECEQU_PH_QBRA\000" |
| 7838 | /* 8554 */ "DSRA\000" |
| 7839 | /* 8559 */ "ATOMIC_LOAD_SUB_I32_POSTRA\000" |
| 7840 | /* 8586 */ "ATOMIC_LOAD_ADD_I32_POSTRA\000" |
| 7841 | /* 8613 */ "ATOMIC_LOAD_NAND_I32_POSTRA\000" |
| 7842 | /* 8641 */ "ATOMIC_LOAD_AND_I32_POSTRA\000" |
| 7843 | /* 8668 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\000" |
| 7844 | /* 8696 */ "ATOMIC_LOAD_MIN_I32_POSTRA\000" |
| 7845 | /* 8723 */ "ATOMIC_SWAP_I32_POSTRA\000" |
| 7846 | /* 8746 */ "ATOMIC_CMP_SWAP_I32_POSTRA\000" |
| 7847 | /* 8773 */ "ATOMIC_LOAD_XOR_I32_POSTRA\000" |
| 7848 | /* 8800 */ "ATOMIC_LOAD_OR_I32_POSTRA\000" |
| 7849 | /* 8826 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\000" |
| 7850 | /* 8854 */ "ATOMIC_LOAD_MAX_I32_POSTRA\000" |
| 7851 | /* 8881 */ "ATOMIC_LOAD_SUB_I64_POSTRA\000" |
| 7852 | /* 8908 */ "ATOMIC_LOAD_ADD_I64_POSTRA\000" |
| 7853 | /* 8935 */ "ATOMIC_LOAD_NAND_I64_POSTRA\000" |
| 7854 | /* 8963 */ "ATOMIC_LOAD_AND_I64_POSTRA\000" |
| 7855 | /* 8990 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\000" |
| 7856 | /* 9018 */ "ATOMIC_LOAD_MIN_I64_POSTRA\000" |
| 7857 | /* 9045 */ "ATOMIC_SWAP_I64_POSTRA\000" |
| 7858 | /* 9068 */ "ATOMIC_CMP_SWAP_I64_POSTRA\000" |
| 7859 | /* 9095 */ "ATOMIC_LOAD_XOR_I64_POSTRA\000" |
| 7860 | /* 9122 */ "ATOMIC_LOAD_OR_I64_POSTRA\000" |
| 7861 | /* 9148 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\000" |
| 7862 | /* 9176 */ "ATOMIC_LOAD_MAX_I64_POSTRA\000" |
| 7863 | /* 9203 */ "ATOMIC_LOAD_SUB_I16_POSTRA\000" |
| 7864 | /* 9230 */ "ATOMIC_LOAD_ADD_I16_POSTRA\000" |
| 7865 | /* 9257 */ "ATOMIC_LOAD_NAND_I16_POSTRA\000" |
| 7866 | /* 9285 */ "ATOMIC_LOAD_AND_I16_POSTRA\000" |
| 7867 | /* 9312 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\000" |
| 7868 | /* 9340 */ "ATOMIC_LOAD_MIN_I16_POSTRA\000" |
| 7869 | /* 9367 */ "ATOMIC_SWAP_I16_POSTRA\000" |
| 7870 | /* 9390 */ "ATOMIC_CMP_SWAP_I16_POSTRA\000" |
| 7871 | /* 9417 */ "ATOMIC_LOAD_XOR_I16_POSTRA\000" |
| 7872 | /* 9444 */ "ATOMIC_LOAD_OR_I16_POSTRA\000" |
| 7873 | /* 9470 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\000" |
| 7874 | /* 9498 */ "ATOMIC_LOAD_MAX_I16_POSTRA\000" |
| 7875 | /* 9525 */ "ATOMIC_LOAD_SUB_I8_POSTRA\000" |
| 7876 | /* 9551 */ "ATOMIC_LOAD_ADD_I8_POSTRA\000" |
| 7877 | /* 9577 */ "ATOMIC_LOAD_NAND_I8_POSTRA\000" |
| 7878 | /* 9604 */ "ATOMIC_LOAD_AND_I8_POSTRA\000" |
| 7879 | /* 9630 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\000" |
| 7880 | /* 9657 */ "ATOMIC_LOAD_MIN_I8_POSTRA\000" |
| 7881 | /* 9683 */ "ATOMIC_SWAP_I8_POSTRA\000" |
| 7882 | /* 9705 */ "ATOMIC_CMP_SWAP_I8_POSTRA\000" |
| 7883 | /* 9731 */ "ATOMIC_LOAD_XOR_I8_POSTRA\000" |
| 7884 | /* 9757 */ "ATOMIC_LOAD_OR_I8_POSTRA\000" |
| 7885 | /* 9782 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\000" |
| 7886 | /* 9809 */ "ATOMIC_LOAD_MAX_I8_POSTRA\000" |
| 7887 | /* 9835 */ "RetRA\000" |
| 7888 | /* 9841 */ "DLSA\000" |
| 7889 | /* 9846 */ "CFCMSA\000" |
| 7890 | /* 9853 */ "CTCMSA\000" |
| 7891 | /* 9860 */ "CRC32B\000" |
| 7892 | /* 9867 */ "CRC32CB\000" |
| 7893 | /* 9875 */ "SEB\000" |
| 7894 | /* 9879 */ "EHB\000" |
| 7895 | /* 9883 */ "TAILCALLREGHB\000" |
| 7896 | /* 9897 */ "JR_HB\000" |
| 7897 | /* 9903 */ "JALR_HB\000" |
| 7898 | /* 9911 */ "LB\000" |
| 7899 | /* 9914 */ "SHRA_QB\000" |
| 7900 | /* 9922 */ "CMPGDU_LE_QB\000" |
| 7901 | /* 9935 */ "CMPGU_LE_QB\000" |
| 7902 | /* 9947 */ "PseudoCMPU_LE_QB\000" |
| 7903 | /* 9964 */ "SUBUH_QB\000" |
| 7904 | /* 9973 */ "ADDUH_QB\000" |
| 7905 | /* 9982 */ "PseudoPICK_QB\000" |
| 7906 | /* 9996 */ "SHLL_QB\000" |
| 7907 | /* 10004 */ "REPL_QB\000" |
| 7908 | /* 10012 */ "SHRL_QB\000" |
| 7909 | /* 10020 */ "CMPGDU_EQ_QB\000" |
| 7910 | /* 10033 */ "CMPGU_EQ_QB\000" |
| 7911 | /* 10045 */ "PseudoCMPU_EQ_QB\000" |
| 7912 | /* 10062 */ "SHRA_R_QB\000" |
| 7913 | /* 10072 */ "SUBUH_R_QB\000" |
| 7914 | /* 10083 */ "ADDUH_R_QB\000" |
| 7915 | /* 10094 */ "SHRAV_R_QB\000" |
| 7916 | /* 10105 */ "ABSQ_S_QB\000" |
| 7917 | /* 10115 */ "SUBU_S_QB\000" |
| 7918 | /* 10125 */ "ADDU_S_QB\000" |
| 7919 | /* 10135 */ "CMPGDU_LT_QB\000" |
| 7920 | /* 10148 */ "CMPGU_LT_QB\000" |
| 7921 | /* 10160 */ "PseudoCMPU_LT_QB\000" |
| 7922 | /* 10177 */ "SUBU_QB\000" |
| 7923 | /* 10185 */ "ADDU_QB\000" |
| 7924 | /* 10193 */ "SHRAV_QB\000" |
| 7925 | /* 10202 */ "SHLLV_QB\000" |
| 7926 | /* 10211 */ "REPLV_QB\000" |
| 7927 | /* 10220 */ "SHRLV_QB\000" |
| 7928 | /* 10229 */ "RADDU_W_QB\000" |
| 7929 | /* 10240 */ "SB\000" |
| 7930 | /* 10243 */ "MODSUB\000" |
| 7931 | /* 10250 */ "G_FSUB\000" |
| 7932 | /* 10257 */ "G_STRICT_FSUB\000" |
| 7933 | /* 10271 */ "G_ATOMICRMW_FSUB\000" |
| 7934 | /* 10288 */ "PseudoMSUB\000" |
| 7935 | /* 10299 */ "G_SUB\000" |
| 7936 | /* 10305 */ "G_ATOMICRMW_SUB\000" |
| 7937 | /* 10321 */ "SRA_B\000" |
| 7938 | /* 10327 */ "ADD_A_B\000" |
| 7939 | /* 10335 */ "MIN_A_B\000" |
| 7940 | /* 10343 */ "ADDS_A_B\000" |
| 7941 | /* 10352 */ "MAX_A_B\000" |
| 7942 | /* 10360 */ "NLOC_B\000" |
| 7943 | /* 10367 */ "NLZC_B\000" |
| 7944 | /* 10374 */ "SLD_B\000" |
| 7945 | /* 10380 */ "PCKOD_B\000" |
| 7946 | /* 10388 */ "ILVOD_B\000" |
| 7947 | /* 10396 */ "INSVE_B\000" |
| 7948 | /* 10404 */ "VSHF_B\000" |
| 7949 | /* 10411 */ "BNEG_B\000" |
| 7950 | /* 10418 */ "SRAI_B\000" |
| 7951 | /* 10425 */ "SLDI_B\000" |
| 7952 | /* 10432 */ "ANDI_B\000" |
| 7953 | /* 10439 */ "BNEGI_B\000" |
| 7954 | /* 10447 */ "BSELI_B\000" |
| 7955 | /* 10455 */ "SLLI_B\000" |
| 7956 | /* 10462 */ "SRLI_B\000" |
| 7957 | /* 10469 */ "BINSLI_B\000" |
| 7958 | /* 10478 */ "CEQI_B\000" |
| 7959 | /* 10485 */ "SRARI_B\000" |
| 7960 | /* 10493 */ "BCLRI_B\000" |
| 7961 | /* 10501 */ "SRLRI_B\000" |
| 7962 | /* 10509 */ "NORI_B\000" |
| 7963 | /* 10516 */ "XORI_B\000" |
| 7964 | /* 10523 */ "BINSRI_B\000" |
| 7965 | /* 10532 */ "SPLATI_B\000" |
| 7966 | /* 10541 */ "BSETI_B\000" |
| 7967 | /* 10549 */ "SUBVI_B\000" |
| 7968 | /* 10557 */ "ADDVI_B\000" |
| 7969 | /* 10565 */ "BMZI_B\000" |
| 7970 | /* 10572 */ "BMNZI_B\000" |
| 7971 | /* 10580 */ "FILL_B\000" |
| 7972 | /* 10587 */ "SLL_B\000" |
| 7973 | /* 10593 */ "SRL_B\000" |
| 7974 | /* 10599 */ "BINSL_B\000" |
| 7975 | /* 10607 */ "ILVL_B\000" |
| 7976 | /* 10614 */ "CEQ_B\000" |
| 7977 | /* 10620 */ "SRAR_B\000" |
| 7978 | /* 10627 */ "BCLR_B\000" |
| 7979 | /* 10634 */ "SRLR_B\000" |
| 7980 | /* 10641 */ "BINSR_B\000" |
| 7981 | /* 10649 */ "ILVR_B\000" |
| 7982 | /* 10656 */ "ASUB_S_B\000" |
| 7983 | /* 10665 */ "MOD_S_B\000" |
| 7984 | /* 10673 */ "CLE_S_B\000" |
| 7985 | /* 10681 */ "AVE_S_B\000" |
| 7986 | /* 10689 */ "CLEI_S_B\000" |
| 7987 | /* 10698 */ "MINI_S_B\000" |
| 7988 | /* 10707 */ "CLTI_S_B\000" |
| 7989 | /* 10716 */ "MAXI_S_B\000" |
| 7990 | /* 10725 */ "MIN_S_B\000" |
| 7991 | /* 10733 */ "AVER_S_B\000" |
| 7992 | /* 10742 */ "SUBS_S_B\000" |
| 7993 | /* 10751 */ "ADDS_S_B\000" |
| 7994 | /* 10760 */ "SAT_S_B\000" |
| 7995 | /* 10768 */ "CLT_S_B\000" |
| 7996 | /* 10776 */ "SUBSUU_S_B\000" |
| 7997 | /* 10787 */ "DIV_S_B\000" |
| 7998 | /* 10795 */ "MAX_S_B\000" |
| 7999 | /* 10803 */ "COPY_S_B\000" |
| 8000 | /* 10812 */ "SPLAT_B\000" |
| 8001 | /* 10820 */ "BSET_B\000" |
| 8002 | /* 10827 */ "PCNT_B\000" |
| 8003 | /* 10834 */ "INSERT_B\000" |
| 8004 | /* 10843 */ "ST_B\000" |
| 8005 | /* 10848 */ "ASUB_U_B\000" |
| 8006 | /* 10857 */ "MOD_U_B\000" |
| 8007 | /* 10865 */ "CLE_U_B\000" |
| 8008 | /* 10873 */ "AVE_U_B\000" |
| 8009 | /* 10881 */ "CLEI_U_B\000" |
| 8010 | /* 10890 */ "MINI_U_B\000" |
| 8011 | /* 10899 */ "CLTI_U_B\000" |
| 8012 | /* 10908 */ "MAXI_U_B\000" |
| 8013 | /* 10917 */ "MIN_U_B\000" |
| 8014 | /* 10925 */ "AVER_U_B\000" |
| 8015 | /* 10934 */ "SUBS_U_B\000" |
| 8016 | /* 10943 */ "ADDS_U_B\000" |
| 8017 | /* 10952 */ "SUBSUS_U_B\000" |
| 8018 | /* 10963 */ "SAT_U_B\000" |
| 8019 | /* 10971 */ "CLT_U_B\000" |
| 8020 | /* 10979 */ "DIV_U_B\000" |
| 8021 | /* 10987 */ "MAX_U_B\000" |
| 8022 | /* 10995 */ "COPY_U_B\000" |
| 8023 | /* 11004 */ "MSUBV_B\000" |
| 8024 | /* 11012 */ "MADDV_B\000" |
| 8025 | /* 11020 */ "PCKEV_B\000" |
| 8026 | /* 11028 */ "ILVEV_B\000" |
| 8027 | /* 11036 */ "MULV_B\000" |
| 8028 | /* 11043 */ "BZ_B\000" |
| 8029 | /* 11048 */ "BNZ_B\000" |
| 8030 | /* 11054 */ "BC\000" |
| 8031 | /* 11057 */ "BGEC\000" |
| 8032 | /* 11062 */ "BNEC\000" |
| 8033 | /* 11067 */ "JIC\000" |
| 8034 | /* 11071 */ "G_INTRINSIC\000" |
| 8035 | /* 11083 */ "BALC\000" |
| 8036 | /* 11088 */ "JIALC\000" |
| 8037 | /* 11094 */ "BGEZALC\000" |
| 8038 | /* 11102 */ "BLEZALC\000" |
| 8039 | /* 11110 */ "BNEZALC\000" |
| 8040 | /* 11118 */ "BEQZALC\000" |
| 8041 | /* 11126 */ "BGTZALC\000" |
| 8042 | /* 11134 */ "BLTZALC\000" |
| 8043 | /* 11142 */ "ERETNC\000" |
| 8044 | /* 11149 */ "G_FPTRUNC\000" |
| 8045 | /* 11159 */ "G_INTRINSIC_TRUNC\000" |
| 8046 | /* 11177 */ "G_TRUNC\000" |
| 8047 | /* 11185 */ "G_BUILD_VECTOR_TRUNC\000" |
| 8048 | /* 11206 */ "SYNC\000" |
| 8049 | /* 11211 */ "G_DYN_STACKALLOC\000" |
| 8050 | /* 11228 */ "LDPC\000" |
| 8051 | /* 11233 */ "AUIPC\000" |
| 8052 | /* 11239 */ "ALUIPC\000" |
| 8053 | /* 11246 */ "ADDIUPC\000" |
| 8054 | /* 11254 */ "LWUPC\000" |
| 8055 | /* 11260 */ "LWPC\000" |
| 8056 | /* 11265 */ "BEQC\000" |
| 8057 | /* 11270 */ "ADDSC\000" |
| 8058 | /* 11276 */ "BLTC\000" |
| 8059 | /* 11281 */ "BGEUC\000" |
| 8060 | /* 11287 */ "BLTUC\000" |
| 8061 | /* 11293 */ "BNVC\000" |
| 8062 | /* 11298 */ "BOVC\000" |
| 8063 | /* 11303 */ "ADDWC\000" |
| 8064 | /* 11309 */ "BGEZC\000" |
| 8065 | /* 11315 */ "BLEZC\000" |
| 8066 | /* 11321 */ "BNEZC\000" |
| 8067 | /* 11327 */ "BEQZC\000" |
| 8068 | /* 11333 */ "BGTZC\000" |
| 8069 | /* 11339 */ "BLTZC\000" |
| 8070 | /* 11345 */ "CRC32D\000" |
| 8071 | /* 11352 */ "SAAD\000" |
| 8072 | /* 11357 */ "G_FMAD\000" |
| 8073 | /* 11364 */ "G_FPEXTLOAD\000" |
| 8074 | /* 11376 */ "G_INDEXED_SEXTLOAD\000" |
| 8075 | /* 11395 */ "G_SEXTLOAD\000" |
| 8076 | /* 11406 */ "G_INDEXED_ZEXTLOAD\000" |
| 8077 | /* 11425 */ "G_ZEXTLOAD\000" |
| 8078 | /* 11436 */ "G_INDEXED_LOAD\000" |
| 8079 | /* 11451 */ "G_LOAD\000" |
| 8080 | /* 11458 */ "CRC32CD\000" |
| 8081 | /* 11466 */ "SCD\000" |
| 8082 | /* 11470 */ "DADD\000" |
| 8083 | /* 11475 */ "G_VECREDUCE_FADD\000" |
| 8084 | /* 11492 */ "G_FADD\000" |
| 8085 | /* 11499 */ "G_VECREDUCE_SEQ_FADD\000" |
| 8086 | /* 11520 */ "G_STRICT_FADD\000" |
| 8087 | /* 11534 */ "G_ATOMICRMW_FADD\000" |
| 8088 | /* 11551 */ "PseudoMADD\000" |
| 8089 | /* 11562 */ "G_VECREDUCE_ADD\000" |
| 8090 | /* 11578 */ "G_ADD\000" |
| 8091 | /* 11584 */ "G_PTR_ADD\000" |
| 8092 | /* 11594 */ "G_ATOMICRMW_ADD\000" |
| 8093 | /* 11610 */ "DSHD\000" |
| 8094 | /* 11615 */ "YIELD\000" |
| 8095 | /* 11621 */ "LLD\000" |
| 8096 | /* 11625 */ "G_ATOMICRMW_NAND\000" |
| 8097 | /* 11642 */ "G_VECREDUCE_AND\000" |
| 8098 | /* 11658 */ "G_AND\000" |
| 8099 | /* 11664 */ "G_ATOMICRMW_AND\000" |
| 8100 | /* 11680 */ "PREPEND\000" |
| 8101 | /* 11688 */ "APPEND\000" |
| 8102 | /* 11695 */ "LIFETIME_END\000" |
| 8103 | /* 11708 */ "G_BRCOND\000" |
| 8104 | /* 11717 */ "G_ATOMICRMW_USUB_COND\000" |
| 8105 | /* 11739 */ "G_LLROUND\000" |
| 8106 | /* 11749 */ "G_LROUND\000" |
| 8107 | /* 11758 */ "G_INTRINSIC_ROUND\000" |
| 8108 | /* 11776 */ "G_INTRINSIC_FPTRUNC_ROUND\000" |
| 8109 | /* 11802 */ "DMOD\000" |
| 8110 | /* 11807 */ "LOAD_STACK_GUARD\000" |
| 8111 | /* 11824 */ "SD\000" |
| 8112 | /* 11827 */ "FLOG2_D\000" |
| 8113 | /* 11835 */ "FEXP2_D\000" |
| 8114 | /* 11843 */ "MINA_D\000" |
| 8115 | /* 11850 */ "SRA_D\000" |
| 8116 | /* 11856 */ "MAXA_D\000" |
| 8117 | /* 11863 */ "ADD_A_D\000" |
| 8118 | /* 11871 */ "FMIN_A_D\000" |
| 8119 | /* 11880 */ "ADDS_A_D\000" |
| 8120 | /* 11889 */ "FMAX_A_D\000" |
| 8121 | /* 11898 */ "FSUB_D\000" |
| 8122 | /* 11905 */ "FMSUB_D\000" |
| 8123 | /* 11913 */ "NLOC_D\000" |
| 8124 | /* 11920 */ "NLZC_D\000" |
| 8125 | /* 11927 */ "FADD_D\000" |
| 8126 | /* 11934 */ "FMADD_D\000" |
| 8127 | /* 11942 */ "SLD_D\000" |
| 8128 | /* 11948 */ "PCKOD_D\000" |
| 8129 | /* 11956 */ "ILVOD_D\000" |
| 8130 | /* 11964 */ "FCLE_D\000" |
| 8131 | /* 11971 */ "FSLE_D\000" |
| 8132 | /* 11978 */ "CMP_SLE_D\000" |
| 8133 | /* 11988 */ "FCULE_D\000" |
| 8134 | /* 11996 */ "FSULE_D\000" |
| 8135 | /* 12004 */ "CMP_SULE_D\000" |
| 8136 | /* 12015 */ "CMP_ULE_D\000" |
| 8137 | /* 12025 */ "CMP_LE_D\000" |
| 8138 | /* 12034 */ "FCNE_D\000" |
| 8139 | /* 12041 */ "FSNE_D\000" |
| 8140 | /* 12048 */ "FCUNE_D\000" |
| 8141 | /* 12056 */ "FSUNE_D\000" |
| 8142 | /* 12064 */ "INSVE_D\000" |
| 8143 | /* 12072 */ "FCAF_D\000" |
| 8144 | /* 12079 */ "FSAF_D\000" |
| 8145 | /* 12086 */ "CMP_SAF_D\000" |
| 8146 | /* 12096 */ "MSUBF_D\000" |
| 8147 | /* 12104 */ "MADDF_D\000" |
| 8148 | /* 12112 */ "VSHF_D\000" |
| 8149 | /* 12119 */ "CMP_F_D\000" |
| 8150 | /* 12127 */ "BNEG_D\000" |
| 8151 | /* 12134 */ "SRAI_D\000" |
| 8152 | /* 12141 */ "SLDI_D\000" |
| 8153 | /* 12148 */ "BNEGI_D\000" |
| 8154 | /* 12156 */ "SLLI_D\000" |
| 8155 | /* 12163 */ "SRLI_D\000" |
| 8156 | /* 12170 */ "BINSLI_D\000" |
| 8157 | /* 12179 */ "CEQI_D\000" |
| 8158 | /* 12186 */ "SRARI_D\000" |
| 8159 | /* 12194 */ "BCLRI_D\000" |
| 8160 | /* 12202 */ "SRLRI_D\000" |
| 8161 | /* 12210 */ "BINSRI_D\000" |
| 8162 | /* 12219 */ "SPLATI_D\000" |
| 8163 | /* 12228 */ "BSETI_D\000" |
| 8164 | /* 12236 */ "SUBVI_D\000" |
| 8165 | /* 12244 */ "ADDVI_D\000" |
| 8166 | /* 12252 */ "SEL_D\000" |
| 8167 | /* 12258 */ "FILL_D\000" |
| 8168 | /* 12265 */ "SLL_D\000" |
| 8169 | /* 12271 */ "FEXUPL_D\000" |
| 8170 | /* 12280 */ "FFQL_D\000" |
| 8171 | /* 12287 */ "SRL_D\000" |
| 8172 | /* 12293 */ "BINSL_D\000" |
| 8173 | /* 12301 */ "FMUL_D\000" |
| 8174 | /* 12308 */ "ILVL_D\000" |
| 8175 | /* 12315 */ "FMIN_D\000" |
| 8176 | /* 12322 */ "FCUN_D\000" |
| 8177 | /* 12329 */ "FSUN_D\000" |
| 8178 | /* 12336 */ "CMP_SUN_D\000" |
| 8179 | /* 12346 */ "CMP_UN_D\000" |
| 8180 | /* 12355 */ "FRCP_D\000" |
| 8181 | /* 12362 */ "FCEQ_D\000" |
| 8182 | /* 12369 */ "FSEQ_D\000" |
| 8183 | /* 12376 */ "CMP_SEQ_D\000" |
| 8184 | /* 12386 */ "FCUEQ_D\000" |
| 8185 | /* 12394 */ "FSUEQ_D\000" |
| 8186 | /* 12402 */ "CMP_SUEQ_D\000" |
| 8187 | /* 12413 */ "CMP_UEQ_D\000" |
| 8188 | /* 12423 */ "CMP_EQ_D\000" |
| 8189 | /* 12432 */ "SRAR_D\000" |
| 8190 | /* 12439 */ "LDR_D\000" |
| 8191 | /* 12445 */ "BCLR_D\000" |
| 8192 | /* 12452 */ "SRLR_D\000" |
| 8193 | /* 12459 */ "FCOR_D\000" |
| 8194 | /* 12466 */ "FSOR_D\000" |
| 8195 | /* 12473 */ "FEXUPR_D\000" |
| 8196 | /* 12482 */ "FFQR_D\000" |
| 8197 | /* 12489 */ "BINSR_D\000" |
| 8198 | /* 12497 */ "STR_D\000" |
| 8199 | /* 12503 */ "ILVR_D\000" |
| 8200 | /* 12510 */ "FABS_D\000" |
| 8201 | /* 12517 */ "FCLASS_D\000" |
| 8202 | /* 12526 */ "ASUB_S_D\000" |
| 8203 | /* 12535 */ "HSUB_S_D\000" |
| 8204 | /* 12544 */ "DPSUB_S_D\000" |
| 8205 | /* 12554 */ "FTRUNC_S_D\000" |
| 8206 | /* 12565 */ "HADD_S_D\000" |
| 8207 | /* 12574 */ "DPADD_S_D\000" |
| 8208 | /* 12584 */ "MOD_S_D\000" |
| 8209 | /* 12592 */ "CLE_S_D\000" |
| 8210 | /* 12600 */ "AVE_S_D\000" |
| 8211 | /* 12608 */ "CLEI_S_D\000" |
| 8212 | /* 12617 */ "MINI_S_D\000" |
| 8213 | /* 12626 */ "CLTI_S_D\000" |
| 8214 | /* 12635 */ "MAXI_S_D\000" |
| 8215 | /* 12644 */ "MIN_S_D\000" |
| 8216 | /* 12652 */ "DOTP_S_D\000" |
| 8217 | /* 12661 */ "AVER_S_D\000" |
| 8218 | /* 12670 */ "SUBS_S_D\000" |
| 8219 | /* 12679 */ "ADDS_S_D\000" |
| 8220 | /* 12688 */ "SAT_S_D\000" |
| 8221 | /* 12696 */ "CLT_S_D\000" |
| 8222 | /* 12704 */ "FFINT_S_D\000" |
| 8223 | /* 12714 */ "FTINT_S_D\000" |
| 8224 | /* 12724 */ "SUBSUU_S_D\000" |
| 8225 | /* 12735 */ "DIV_S_D\000" |
| 8226 | /* 12743 */ "MAX_S_D\000" |
| 8227 | /* 12751 */ "COPY_S_D\000" |
| 8228 | /* 12760 */ "SPLAT_D\000" |
| 8229 | /* 12768 */ "BSET_D\000" |
| 8230 | /* 12775 */ "FCLT_D\000" |
| 8231 | /* 12782 */ "FSLT_D\000" |
| 8232 | /* 12789 */ "CMP_SLT_D\000" |
| 8233 | /* 12799 */ "FCULT_D\000" |
| 8234 | /* 12807 */ "FSULT_D\000" |
| 8235 | /* 12815 */ "CMP_SULT_D\000" |
| 8236 | /* 12826 */ "CMP_ULT_D\000" |
| 8237 | /* 12836 */ "CMP_LT_D\000" |
| 8238 | /* 12845 */ "PCNT_D\000" |
| 8239 | /* 12852 */ "FRINT_D\000" |
| 8240 | /* 12860 */ "INSERT_D\000" |
| 8241 | /* 12869 */ "FSQRT_D\000" |
| 8242 | /* 12877 */ "FRSQRT_D\000" |
| 8243 | /* 12886 */ "ST_D\000" |
| 8244 | /* 12891 */ "ASUB_U_D\000" |
| 8245 | /* 12900 */ "HSUB_U_D\000" |
| 8246 | /* 12909 */ "DPSUB_U_D\000" |
| 8247 | /* 12919 */ "FTRUNC_U_D\000" |
| 8248 | /* 12930 */ "HADD_U_D\000" |
| 8249 | /* 12939 */ "DPADD_U_D\000" |
| 8250 | /* 12949 */ "MOD_U_D\000" |
| 8251 | /* 12957 */ "CLE_U_D\000" |
| 8252 | /* 12965 */ "AVE_U_D\000" |
| 8253 | /* 12973 */ "CLEI_U_D\000" |
| 8254 | /* 12982 */ "MINI_U_D\000" |
| 8255 | /* 12991 */ "CLTI_U_D\000" |
| 8256 | /* 13000 */ "MAXI_U_D\000" |
| 8257 | /* 13009 */ "MIN_U_D\000" |
| 8258 | /* 13017 */ "DOTP_U_D\000" |
| 8259 | /* 13026 */ "AVER_U_D\000" |
| 8260 | /* 13035 */ "SUBS_U_D\000" |
| 8261 | /* 13044 */ "ADDS_U_D\000" |
| 8262 | /* 13053 */ "SUBSUS_U_D\000" |
| 8263 | /* 13064 */ "SAT_U_D\000" |
| 8264 | /* 13072 */ "CLT_U_D\000" |
| 8265 | /* 13080 */ "FFINT_U_D\000" |
| 8266 | /* 13090 */ "FTINT_U_D\000" |
| 8267 | /* 13100 */ "DIV_U_D\000" |
| 8268 | /* 13108 */ "MAX_U_D\000" |
| 8269 | /* 13116 */ "MSUBV_D\000" |
| 8270 | /* 13124 */ "MADDV_D\000" |
| 8271 | /* 13132 */ "PCKEV_D\000" |
| 8272 | /* 13140 */ "ILVEV_D\000" |
| 8273 | /* 13148 */ "FDIV_D\000" |
| 8274 | /* 13155 */ "MULV_D\000" |
| 8275 | /* 13162 */ "PseudoTRUNC_W_D\000" |
| 8276 | /* 13178 */ "FMAX_D\000" |
| 8277 | /* 13185 */ "BZ_D\000" |
| 8278 | /* 13190 */ "SELNEZ_D\000" |
| 8279 | /* 13199 */ "BNZ_D\000" |
| 8280 | /* 13205 */ "SELEQZ_D\000" |
| 8281 | /* 13214 */ "LBE\000" |
| 8282 | /* 13218 */ "PSEUDO_PROBE\000" |
| 8283 | /* 13231 */ "SBE\000" |
| 8284 | /* 13235 */ "G_SSUBE\000" |
| 8285 | /* 13243 */ "G_USUBE\000" |
| 8286 | /* 13251 */ "G_FENCE\000" |
| 8287 | /* 13259 */ "ARITH_FENCE\000" |
| 8288 | /* 13271 */ "REG_SEQUENCE\000" |
| 8289 | /* 13284 */ "SCE\000" |
| 8290 | /* 13288 */ "G_SADDE\000" |
| 8291 | /* 13296 */ "G_UADDE\000" |
| 8292 | /* 13304 */ "G_GET_FPMODE\000" |
| 8293 | /* 13317 */ "G_RESET_FPMODE\000" |
| 8294 | /* 13332 */ "G_SET_FPMODE\000" |
| 8295 | /* 13345 */ "G_FMINNUM_IEEE\000" |
| 8296 | /* 13360 */ "G_FMAXNUM_IEEE\000" |
| 8297 | /* 13375 */ "CACHEE\000" |
| 8298 | /* 13382 */ "PREFE\000" |
| 8299 | /* 13388 */ "BGE\000" |
| 8300 | /* 13392 */ "SGE\000" |
| 8301 | /* 13396 */ "TGE\000" |
| 8302 | /* 13400 */ "CACHE\000" |
| 8303 | /* 13406 */ "LHE\000" |
| 8304 | /* 13410 */ "SHE\000" |
| 8305 | /* 13414 */ "SIGRIE\000" |
| 8306 | /* 13421 */ "G_VSCALE\000" |
| 8307 | /* 13430 */ "G_JUMP_TABLE\000" |
| 8308 | /* 13443 */ "BUNDLE\000" |
| 8309 | /* 13450 */ "LLE\000" |
| 8310 | /* 13454 */ "SLE\000" |
| 8311 | /* 13458 */ "LWLE\000" |
| 8312 | /* 13463 */ "SWLE\000" |
| 8313 | /* 13468 */ "BNE\000" |
| 8314 | /* 13472 */ "G_MEMSET_INLINE\000" |
| 8315 | /* 13488 */ "G_MEMCPY_INLINE\000" |
| 8316 | /* 13504 */ "RELOC_NONE\000" |
| 8317 | /* 13515 */ "SNE\000" |
| 8318 | /* 13519 */ "TNE\000" |
| 8319 | /* 13523 */ "LOCAL_ESCAPE\000" |
| 8320 | /* 13536 */ "DVPE\000" |
| 8321 | /* 13541 */ "EVPE\000" |
| 8322 | /* 13546 */ "G_FPTRUNCSTORE\000" |
| 8323 | /* 13561 */ "G_STACKRESTORE\000" |
| 8324 | /* 13576 */ "G_INDEXED_STORE\000" |
| 8325 | /* 13592 */ "G_STORE\000" |
| 8326 | /* 13600 */ "LWRE\000" |
| 8327 | /* 13605 */ "SWRE\000" |
| 8328 | /* 13610 */ "G_BITREVERSE\000" |
| 8329 | /* 13623 */ "PAUSE\000" |
| 8330 | /* 13629 */ "FAKE_USE\000" |
| 8331 | /* 13638 */ "DBG_VALUE\000" |
| 8332 | /* 13648 */ "G_GLOBAL_VALUE\000" |
| 8333 | /* 13663 */ "G_PTRAUTH_GLOBAL_VALUE\000" |
| 8334 | /* 13686 */ "CONVERGENCECTRL_GLUE\000" |
| 8335 | /* 13707 */ "G_STACKSAVE\000" |
| 8336 | /* 13719 */ "G_MEMMOVE\000" |
| 8337 | /* 13729 */ "LWE\000" |
| 8338 | /* 13733 */ "SWE\000" |
| 8339 | /* 13737 */ "G_FREEZE\000" |
| 8340 | /* 13746 */ "G_FCANONICALIZE\000" |
| 8341 | /* 13762 */ "LBuE\000" |
| 8342 | /* 13767 */ "LHuE\000" |
| 8343 | /* 13772 */ "BC1F\000" |
| 8344 | /* 13777 */ "G_FMODF\000" |
| 8345 | /* 13785 */ "INIT_UNDEF\000" |
| 8346 | /* 13796 */ "G_IMPLICIT_DEF\000" |
| 8347 | /* 13811 */ "PREF\000" |
| 8348 | /* 13816 */ "DBG_INSTR_REF\000" |
| 8349 | /* 13830 */ "TLBINVF\000" |
| 8350 | /* 13838 */ "TLBGINVF\000" |
| 8351 | /* 13847 */ "G_FNEG\000" |
| 8352 | /* 13854 */ "TAILCALLHB64R6REG\000" |
| 8353 | /* 13872 */ "TAILCALL64R6REG\000" |
| 8354 | /* 13888 */ "TAILCALLHBR6REG\000" |
| 8355 | /* 13904 */ "TAILCALLR6REG\000" |
| 8356 | /* 13918 */ "EXTRACT_SUBREG\000" |
| 8357 | /* 13933 */ "INSERT_SUBREG\000" |
| 8358 | /* 13947 */ "TAILCALLREG\000" |
| 8359 | /* 13959 */ "G_SEXT_INREG\000" |
| 8360 | /* 13972 */ "SUBREG_TO_REG\000" |
| 8361 | /* 13986 */ "G_ATOMIC_CMPXCHG\000" |
| 8362 | /* 14003 */ "G_ATOMICRMW_XCHG\000" |
| 8363 | /* 14020 */ "G_GET_ROUNDING\000" |
| 8364 | /* 14035 */ "G_SET_ROUNDING\000" |
| 8365 | /* 14050 */ "G_FLOG\000" |
| 8366 | /* 14057 */ "G_VAARG\000" |
| 8367 | /* 14065 */ "PREALLOCATED_ARG\000" |
| 8368 | /* 14082 */ "CRC32H\000" |
| 8369 | /* 14089 */ "DSBH\000" |
| 8370 | /* 14094 */ "WSBH\000" |
| 8371 | /* 14099 */ "CRC32CH\000" |
| 8372 | /* 14107 */ "G_PREFETCH\000" |
| 8373 | /* 14118 */ "SEH\000" |
| 8374 | /* 14122 */ "G_CLMULH\000" |
| 8375 | /* 14131 */ "G_SMULH\000" |
| 8376 | /* 14139 */ "G_UMULH\000" |
| 8377 | /* 14147 */ "G_FTANH\000" |
| 8378 | /* 14155 */ "G_FSINH\000" |
| 8379 | /* 14163 */ "SHRA_PH\000" |
| 8380 | /* 14171 */ "PRECRQ_QB_PH\000" |
| 8381 | /* 14184 */ "PRECR_QB_PH\000" |
| 8382 | /* 14196 */ "PRECRQU_S_QB_PH\000" |
| 8383 | /* 14212 */ "PseudoCMP_LE_PH\000" |
| 8384 | /* 14228 */ "SUBQH_PH\000" |
| 8385 | /* 14237 */ "ADDQH_PH\000" |
| 8386 | /* 14246 */ "PseudoPICK_PH\000" |
| 8387 | /* 14260 */ "SHLL_PH\000" |
| 8388 | /* 14268 */ "REPL_PH\000" |
| 8389 | /* 14276 */ "SHRL_PH\000" |
| 8390 | /* 14284 */ "PACKRL_PH\000" |
| 8391 | /* 14294 */ "MUL_PH\000" |
| 8392 | /* 14301 */ "SUBQ_PH\000" |
| 8393 | /* 14309 */ "ADDQ_PH\000" |
| 8394 | /* 14317 */ "PseudoCMP_EQ_PH\000" |
| 8395 | /* 14333 */ "SHRA_R_PH\000" |
| 8396 | /* 14343 */ "SUBQH_R_PH\000" |
| 8397 | /* 14354 */ "ADDQH_R_PH\000" |
| 8398 | /* 14365 */ "SHRAV_R_PH\000" |
| 8399 | /* 14376 */ "MULQ_RS_PH\000" |
| 8400 | /* 14387 */ "SHLL_S_PH\000" |
| 8401 | /* 14397 */ "MUL_S_PH\000" |
| 8402 | /* 14406 */ "SUBQ_S_PH\000" |
| 8403 | /* 14416 */ "ADDQ_S_PH\000" |
| 8404 | /* 14426 */ "MULQ_S_PH\000" |
| 8405 | /* 14436 */ "ABSQ_S_PH\000" |
| 8406 | /* 14446 */ "SUBU_S_PH\000" |
| 8407 | /* 14456 */ "ADDU_S_PH\000" |
| 8408 | /* 14466 */ "SHLLV_S_PH\000" |
| 8409 | /* 14477 */ "PseudoCMP_LT_PH\000" |
| 8410 | /* 14493 */ "SUBU_PH\000" |
| 8411 | /* 14501 */ "ADDU_PH\000" |
| 8412 | /* 14509 */ "SHRAV_PH\000" |
| 8413 | /* 14518 */ "SHLLV_PH\000" |
| 8414 | /* 14527 */ "REPLV_PH\000" |
| 8415 | /* 14536 */ "SHRLV_PH\000" |
| 8416 | /* 14545 */ "DPA_W_PH\000" |
| 8417 | /* 14554 */ "MULSA_W_PH\000" |
| 8418 | /* 14565 */ "DPAQX_SA_W_PH\000" |
| 8419 | /* 14579 */ "DPSQX_SA_W_PH\000" |
| 8420 | /* 14593 */ "DPS_W_PH\000" |
| 8421 | /* 14602 */ "DPAQ_S_W_PH\000" |
| 8422 | /* 14614 */ "MULSAQ_S_W_PH\000" |
| 8423 | /* 14628 */ "DPSQ_S_W_PH\000" |
| 8424 | /* 14640 */ "DPAQX_S_W_PH\000" |
| 8425 | /* 14653 */ "DPSQX_S_W_PH\000" |
| 8426 | /* 14666 */ "DPAX_W_PH\000" |
| 8427 | /* 14676 */ "DPSX_W_PH\000" |
| 8428 | /* 14686 */ "G_FCOSH\000" |
| 8429 | /* 14694 */ "DMUH\000" |
| 8430 | /* 14699 */ "SRA_H\000" |
| 8431 | /* 14705 */ "ADD_A_H\000" |
| 8432 | /* 14713 */ "MIN_A_H\000" |
| 8433 | /* 14721 */ "ADDS_A_H\000" |
| 8434 | /* 14730 */ "MAX_A_H\000" |
| 8435 | /* 14738 */ "NLOC_H\000" |
| 8436 | /* 14745 */ "NLZC_H\000" |
| 8437 | /* 14752 */ "SLD_H\000" |
| 8438 | /* 14758 */ "PCKOD_H\000" |
| 8439 | /* 14766 */ "ILVOD_H\000" |
| 8440 | /* 14774 */ "INSVE_H\000" |
| 8441 | /* 14782 */ "VSHF_H\000" |
| 8442 | /* 14789 */ "BNEG_H\000" |
| 8443 | /* 14796 */ "SRAI_H\000" |
| 8444 | /* 14803 */ "SLDI_H\000" |
| 8445 | /* 14810 */ "BNEGI_H\000" |
| 8446 | /* 14818 */ "SLLI_H\000" |
| 8447 | /* 14825 */ "SRLI_H\000" |
| 8448 | /* 14832 */ "BINSLI_H\000" |
| 8449 | /* 14841 */ "CEQI_H\000" |
| 8450 | /* 14848 */ "SRARI_H\000" |
| 8451 | /* 14856 */ "BCLRI_H\000" |
| 8452 | /* 14864 */ "SRLRI_H\000" |
| 8453 | /* 14872 */ "BINSRI_H\000" |
| 8454 | /* 14881 */ "SPLATI_H\000" |
| 8455 | /* 14890 */ "BSETI_H\000" |
| 8456 | /* 14898 */ "SUBVI_H\000" |
| 8457 | /* 14906 */ "ADDVI_H\000" |
| 8458 | /* 14914 */ "FILL_H\000" |
| 8459 | /* 14921 */ "SLL_H\000" |
| 8460 | /* 14927 */ "SRL_H\000" |
| 8461 | /* 14933 */ "BINSL_H\000" |
| 8462 | /* 14941 */ "ILVL_H\000" |
| 8463 | /* 14948 */ "FEXDO_H\000" |
| 8464 | /* 14956 */ "CEQ_H\000" |
| 8465 | /* 14962 */ "FTQ_H\000" |
| 8466 | /* 14968 */ "MSUB_Q_H\000" |
| 8467 | /* 14977 */ "MADD_Q_H\000" |
| 8468 | /* 14986 */ "MUL_Q_H\000" |
| 8469 | /* 14994 */ "MSUBR_Q_H\000" |
| 8470 | /* 15004 */ "MADDR_Q_H\000" |
| 8471 | /* 15014 */ "MULR_Q_H\000" |
| 8472 | /* 15023 */ "SRAR_H\000" |
| 8473 | /* 15030 */ "BCLR_H\000" |
| 8474 | /* 15037 */ "SRLR_H\000" |
| 8475 | /* 15044 */ "BINSR_H\000" |
| 8476 | /* 15052 */ "ILVR_H\000" |
| 8477 | /* 15059 */ "ASUB_S_H\000" |
| 8478 | /* 15068 */ "HSUB_S_H\000" |
| 8479 | /* 15077 */ "DPSUB_S_H\000" |
| 8480 | /* 15087 */ "HADD_S_H\000" |
| 8481 | /* 15096 */ "DPADD_S_H\000" |
| 8482 | /* 15106 */ "MOD_S_H\000" |
| 8483 | /* 15114 */ "CLE_S_H\000" |
| 8484 | /* 15122 */ "AVE_S_H\000" |
| 8485 | /* 15130 */ "CLEI_S_H\000" |
| 8486 | /* 15139 */ "MINI_S_H\000" |
| 8487 | /* 15148 */ "CLTI_S_H\000" |
| 8488 | /* 15157 */ "MAXI_S_H\000" |
| 8489 | /* 15166 */ "MIN_S_H\000" |
| 8490 | /* 15174 */ "DOTP_S_H\000" |
| 8491 | /* 15183 */ "AVER_S_H\000" |
| 8492 | /* 15192 */ "EXTR_S_H\000" |
| 8493 | /* 15201 */ "SUBS_S_H\000" |
| 8494 | /* 15210 */ "ADDS_S_H\000" |
| 8495 | /* 15219 */ "SAT_S_H\000" |
| 8496 | /* 15227 */ "CLT_S_H\000" |
| 8497 | /* 15235 */ "SUBSUU_S_H\000" |
| 8498 | /* 15246 */ "DIV_S_H\000" |
| 8499 | /* 15254 */ "EXTRV_S_H\000" |
| 8500 | /* 15264 */ "MAX_S_H\000" |
| 8501 | /* 15272 */ "COPY_S_H\000" |
| 8502 | /* 15281 */ "SPLAT_H\000" |
| 8503 | /* 15289 */ "BSET_H\000" |
| 8504 | /* 15296 */ "PCNT_H\000" |
| 8505 | /* 15303 */ "INSERT_H\000" |
| 8506 | /* 15312 */ "ST_H\000" |
| 8507 | /* 15317 */ "ASUB_U_H\000" |
| 8508 | /* 15326 */ "HSUB_U_H\000" |
| 8509 | /* 15335 */ "DPSUB_U_H\000" |
| 8510 | /* 15345 */ "HADD_U_H\000" |
| 8511 | /* 15354 */ "DPADD_U_H\000" |
| 8512 | /* 15364 */ "MOD_U_H\000" |
| 8513 | /* 15372 */ "CLE_U_H\000" |
| 8514 | /* 15380 */ "AVE_U_H\000" |
| 8515 | /* 15388 */ "CLEI_U_H\000" |
| 8516 | /* 15397 */ "MINI_U_H\000" |
| 8517 | /* 15406 */ "CLTI_U_H\000" |
| 8518 | /* 15415 */ "MAXI_U_H\000" |
| 8519 | /* 15424 */ "MIN_U_H\000" |
| 8520 | /* 15432 */ "DOTP_U_H\000" |
| 8521 | /* 15441 */ "AVER_U_H\000" |
| 8522 | /* 15450 */ "SUBS_U_H\000" |
| 8523 | /* 15459 */ "ADDS_U_H\000" |
| 8524 | /* 15468 */ "SUBSUS_U_H\000" |
| 8525 | /* 15479 */ "SAT_U_H\000" |
| 8526 | /* 15487 */ "CLT_U_H\000" |
| 8527 | /* 15495 */ "DIV_U_H\000" |
| 8528 | /* 15503 */ "MAX_U_H\000" |
| 8529 | /* 15511 */ "COPY_U_H\000" |
| 8530 | /* 15520 */ "MSUBV_H\000" |
| 8531 | /* 15528 */ "MADDV_H\000" |
| 8532 | /* 15536 */ "PCKEV_H\000" |
| 8533 | /* 15544 */ "ILVEV_H\000" |
| 8534 | /* 15552 */ "MULV_H\000" |
| 8535 | /* 15559 */ "BZ_H\000" |
| 8536 | /* 15564 */ "BNZ_H\000" |
| 8537 | /* 15570 */ "SYNCI\000" |
| 8538 | /* 15576 */ "DI\000" |
| 8539 | /* 15579 */ "TGEI\000" |
| 8540 | /* 15584 */ "TNEI\000" |
| 8541 | /* 15589 */ "DAHI\000" |
| 8542 | /* 15594 */ "PseudoMFHI\000" |
| 8543 | /* 15605 */ "PseudoMTLOHI\000" |
| 8544 | /* 15618 */ "DBG_PHI\000" |
| 8545 | /* 15626 */ "MFTHI\000" |
| 8546 | /* 15632 */ "MTHI\000" |
| 8547 | /* 15637 */ "MTTHI\000" |
| 8548 | /* 15643 */ "TEQI\000" |
| 8549 | /* 15648 */ "G_FPTOSI\000" |
| 8550 | /* 15657 */ "DATI\000" |
| 8551 | /* 15662 */ "TLTI\000" |
| 8552 | /* 15667 */ "DAUI\000" |
| 8553 | /* 15672 */ "G_FPTOUI\000" |
| 8554 | /* 15681 */ "GINVI\000" |
| 8555 | /* 15687 */ "TLBWI\000" |
| 8556 | /* 15693 */ "TLBGWI\000" |
| 8557 | /* 15700 */ "G_FPOWI\000" |
| 8558 | /* 15708 */ "MOVN_I64_I\000" |
| 8559 | /* 15719 */ "MOVZ_I64_I\000" |
| 8560 | /* 15730 */ "MOVF_I\000" |
| 8561 | /* 15737 */ "PseudoSELECTFP_F_I\000" |
| 8562 | /* 15756 */ "MOVN_I_I\000" |
| 8563 | /* 15765 */ "MOVZ_I_I\000" |
| 8564 | /* 15774 */ "PseudoD_SELECT_I\000" |
| 8565 | /* 15791 */ "PseudoSELECT_I\000" |
| 8566 | /* 15806 */ "MOVT_I\000" |
| 8567 | /* 15813 */ "PseudoSELECTFP_T_I\000" |
| 8568 | /* 15832 */ "J\000" |
| 8569 | /* 15834 */ "BREAK\000" |
| 8570 | /* 15840 */ "FORK\000" |
| 8571 | /* 15845 */ "COPY_LANEMASK\000" |
| 8572 | /* 15859 */ "G_PTRMASK\000" |
| 8573 | /* 15869 */ "BAL\000" |
| 8574 | /* 15873 */ "JAL\000" |
| 8575 | /* 15877 */ "NAL\000" |
| 8576 | /* 15881 */ "BGEZAL\000" |
| 8577 | /* 15888 */ "BLTZAL\000" |
| 8578 | /* 15895 */ "MULEU_S_PH_QBL\000" |
| 8579 | /* 15910 */ "PRECEU_PH_QBL\000" |
| 8580 | /* 15924 */ "PRECEQU_PH_QBL\000" |
| 8581 | /* 15939 */ "DPAU_H_QBL\000" |
| 8582 | /* 15950 */ "DPSU_H_QBL\000" |
| 8583 | /* 15961 */ "LDL\000" |
| 8584 | /* 15965 */ "SDL\000" |
| 8585 | /* 15969 */ "GC_LABEL\000" |
| 8586 | /* 15978 */ "DBG_LABEL\000" |
| 8587 | /* 15988 */ "EH_LABEL\000" |
| 8588 | /* 15997 */ "ANNOTATION_LABEL\000" |
| 8589 | /* 16014 */ "BGEL\000" |
| 8590 | /* 16019 */ "BLEL\000" |
| 8591 | /* 16024 */ "BNEL\000" |
| 8592 | /* 16029 */ "ICALL_BRANCH_FUNNEL\000" |
| 8593 | /* 16049 */ "BC1FL\000" |
| 8594 | /* 16055 */ "MAQ_SA_W_PHL\000" |
| 8595 | /* 16068 */ "PRECEQ_W_PHL\000" |
| 8596 | /* 16081 */ "MAQ_S_W_PHL\000" |
| 8597 | /* 16093 */ "MULEQ_S_W_PHL\000" |
| 8598 | /* 16107 */ "G_FSHL\000" |
| 8599 | /* 16114 */ "G_SHL\000" |
| 8600 | /* 16120 */ "G_FCEIL\000" |
| 8601 | /* 16128 */ "G_SAVGCEIL\000" |
| 8602 | /* 16139 */ "G_UAVGCEIL\000" |
| 8603 | /* 16150 */ "TAILCALL\000" |
| 8604 | /* 16159 */ "HYPCALL\000" |
| 8605 | /* 16167 */ "SYSCALL\000" |
| 8606 | /* 16175 */ "PATCHABLE_TAIL_CALL\000" |
| 8607 | /* 16195 */ "PATCHABLE_TYPED_EVENT_CALL\000" |
| 8608 | /* 16222 */ "PATCHABLE_EVENT_CALL\000" |
| 8609 | /* 16243 */ "FENTRY_CALL\000" |
| 8610 | /* 16255 */ "BGEZALL\000" |
| 8611 | /* 16263 */ "BLTZALL\000" |
| 8612 | /* 16271 */ "KILL\000" |
| 8613 | /* 16276 */ "DSLL\000" |
| 8614 | /* 16281 */ "G_CONSTANT_POOL\000" |
| 8615 | /* 16297 */ "DROL\000" |
| 8616 | /* 16302 */ "BEQL\000" |
| 8617 | /* 16307 */ "DSRL\000" |
| 8618 | /* 16312 */ "BC1TL\000" |
| 8619 | /* 16318 */ "BGTL\000" |
| 8620 | /* 16323 */ "BLTL\000" |
| 8621 | /* 16328 */ "G_ROTL\000" |
| 8622 | /* 16335 */ "BGEUL\000" |
| 8623 | /* 16341 */ "BLEUL\000" |
| 8624 | /* 16347 */ "DMUL\000" |
| 8625 | /* 16352 */ "G_VECREDUCE_FMUL\000" |
| 8626 | /* 16369 */ "G_FMUL\000" |
| 8627 | /* 16376 */ "G_VECREDUCE_SEQ_FMUL\000" |
| 8628 | /* 16397 */ "G_STRICT_FMUL\000" |
| 8629 | /* 16411 */ "G_CLMUL\000" |
| 8630 | /* 16419 */ "G_VECREDUCE_MUL\000" |
| 8631 | /* 16435 */ "G_MUL\000" |
| 8632 | /* 16441 */ "BGTUL\000" |
| 8633 | /* 16447 */ "BLTUL\000" |
| 8634 | /* 16453 */ "LWL\000" |
| 8635 | /* 16457 */ "SWL\000" |
| 8636 | /* 16461 */ "BGEZL\000" |
| 8637 | /* 16467 */ "BLEZL\000" |
| 8638 | /* 16473 */ "BGTZL\000" |
| 8639 | /* 16479 */ "BLTZL\000" |
| 8640 | /* 16485 */ "PseudoCVT_D64_L\000" |
| 8641 | /* 16501 */ "PseudoCVT_S_L\000" |
| 8642 | /* 16515 */ "G_FREM\000" |
| 8643 | /* 16522 */ "G_STRICT_FREM\000" |
| 8644 | /* 16536 */ "G_SREM\000" |
| 8645 | /* 16543 */ "G_UREM\000" |
| 8646 | /* 16550 */ "G_SDIVREM\000" |
| 8647 | /* 16560 */ "G_UDIVREM\000" |
| 8648 | /* 16570 */ "MFC0_MM\000" |
| 8649 | /* 16578 */ "MFGC0_MM\000" |
| 8650 | /* 16587 */ "MFHGC0_MM\000" |
| 8651 | /* 16597 */ "MTHGC0_MM\000" |
| 8652 | /* 16607 */ "MTGC0_MM\000" |
| 8653 | /* 16616 */ "MTC0_MM\000" |
| 8654 | /* 16624 */ "CFC1_MM\000" |
| 8655 | /* 16632 */ "MFC1_MM\000" |
| 8656 | /* 16640 */ "CTC1_MM\000" |
| 8657 | /* 16648 */ "MTC1_MM\000" |
| 8658 | /* 16656 */ "LWC1_MM\000" |
| 8659 | /* 16664 */ "SWC1_MM\000" |
| 8660 | /* 16672 */ "LUXC1_MM\000" |
| 8661 | /* 16681 */ "SUXC1_MM\000" |
| 8662 | /* 16690 */ "LWXC1_MM\000" |
| 8663 | /* 16699 */ "SWXC1_MM\000" |
| 8664 | /* 16708 */ "MFHC1_D32_MM\000" |
| 8665 | /* 16721 */ "MTHC1_D32_MM\000" |
| 8666 | /* 16734 */ "FSUB_D32_MM\000" |
| 8667 | /* 16746 */ "NMSUB_D32_MM\000" |
| 8668 | /* 16759 */ "FADD_D32_MM\000" |
| 8669 | /* 16771 */ "NMADD_D32_MM\000" |
| 8670 | /* 16784 */ "C_NGE_D32_MM\000" |
| 8671 | /* 16797 */ "C_NGLE_D32_MM\000" |
| 8672 | /* 16811 */ "C_OLE_D32_MM\000" |
| 8673 | /* 16824 */ "C_ULE_D32_MM\000" |
| 8674 | /* 16837 */ "C_LE_D32_MM\000" |
| 8675 | /* 16849 */ "C_SF_D32_MM\000" |
| 8676 | /* 16861 */ "MOVF_D32_MM\000" |
| 8677 | /* 16873 */ "C_F_D32_MM\000" |
| 8678 | /* 16884 */ "FNEG_D32_MM\000" |
| 8679 | /* 16896 */ "MOVN_I_D32_MM\000" |
| 8680 | /* 16910 */ "MOVZ_I_D32_MM\000" |
| 8681 | /* 16924 */ "C_NGL_D32_MM\000" |
| 8682 | /* 16937 */ "FMUL_D32_MM\000" |
| 8683 | /* 16949 */ "C_UN_D32_MM\000" |
| 8684 | /* 16961 */ "RECIP_D32_MM\000" |
| 8685 | /* 16974 */ "FCMP_D32_MM\000" |
| 8686 | /* 16986 */ "C_SEQ_D32_MM\000" |
| 8687 | /* 16999 */ "C_UEQ_D32_MM\000" |
| 8688 | /* 17012 */ "C_EQ_D32_MM\000" |
| 8689 | /* 17024 */ "FABS_D32_MM\000" |
| 8690 | /* 17036 */ "CVT_S_D32_MM\000" |
| 8691 | /* 17049 */ "C_NGT_D32_MM\000" |
| 8692 | /* 17062 */ "C_OLT_D32_MM\000" |
| 8693 | /* 17075 */ "C_ULT_D32_MM\000" |
| 8694 | /* 17088 */ "C_LT_D32_MM\000" |
| 8695 | /* 17100 */ "FSQRT_D32_MM\000" |
| 8696 | /* 17113 */ "RSQRT_D32_MM\000" |
| 8697 | /* 17126 */ "MOVT_D32_MM\000" |
| 8698 | /* 17138 */ "FDIV_D32_MM\000" |
| 8699 | /* 17150 */ "FMOV_D32_MM\000" |
| 8700 | /* 17162 */ "CVT_W_D32_MM\000" |
| 8701 | /* 17175 */ "BPOSGE32_MM\000" |
| 8702 | /* 17187 */ "LWM32_MM\000" |
| 8703 | /* 17196 */ "SWM32_MM\000" |
| 8704 | /* 17205 */ "FCMP_S32_MM\000" |
| 8705 | /* 17217 */ "CFC2_MM\000" |
| 8706 | /* 17225 */ "CTC2_MM\000" |
| 8707 | /* 17233 */ "ADDIUR2_MM\000" |
| 8708 | /* 17244 */ "MFHC1_D64_MM\000" |
| 8709 | /* 17257 */ "MTHC1_D64_MM\000" |
| 8710 | /* 17270 */ "MTC1_D64_MM\000" |
| 8711 | /* 17282 */ "FSUB_D64_MM\000" |
| 8712 | /* 17294 */ "FADD_D64_MM\000" |
| 8713 | /* 17306 */ "C_NGE_D64_MM\000" |
| 8714 | /* 17319 */ "C_NGLE_D64_MM\000" |
| 8715 | /* 17333 */ "C_OLE_D64_MM\000" |
| 8716 | /* 17346 */ "C_ULE_D64_MM\000" |
| 8717 | /* 17359 */ "C_LE_D64_MM\000" |
| 8718 | /* 17371 */ "C_SF_D64_MM\000" |
| 8719 | /* 17383 */ "C_F_D64_MM\000" |
| 8720 | /* 17394 */ "FNEG_D64_MM\000" |
| 8721 | /* 17406 */ "C_NGL_D64_MM\000" |
| 8722 | /* 17419 */ "FMUL_D64_MM\000" |
| 8723 | /* 17431 */ "CVT_L_D64_MM\000" |
| 8724 | /* 17444 */ "C_UN_D64_MM\000" |
| 8725 | /* 17456 */ "RECIP_D64_MM\000" |
| 8726 | /* 17469 */ "C_SEQ_D64_MM\000" |
| 8727 | /* 17482 */ "C_UEQ_D64_MM\000" |
| 8728 | /* 17495 */ "C_EQ_D64_MM\000" |
| 8729 | /* 17507 */ "FABS_D64_MM\000" |
| 8730 | /* 17519 */ "CVT_S_D64_MM\000" |
| 8731 | /* 17532 */ "C_NGT_D64_MM\000" |
| 8732 | /* 17545 */ "C_OLT_D64_MM\000" |
| 8733 | /* 17558 */ "C_ULT_D64_MM\000" |
| 8734 | /* 17571 */ "C_LT_D64_MM\000" |
| 8735 | /* 17583 */ "FSQRT_D64_MM\000" |
| 8736 | /* 17596 */ "RSQRT_D64_MM\000" |
| 8737 | /* 17609 */ "FDIV_D64_MM\000" |
| 8738 | /* 17621 */ "FMOV_D64_MM\000" |
| 8739 | /* 17633 */ "CVT_W_D64_MM\000" |
| 8740 | /* 17646 */ "ADDIUS5_MM\000" |
| 8741 | /* 17657 */ "SB16_MM\000" |
| 8742 | /* 17665 */ "JRC16_MM\000" |
| 8743 | /* 17674 */ "AND16_MM\000" |
| 8744 | /* 17683 */ "MOVE16_MM\000" |
| 8745 | /* 17693 */ "SH16_MM\000" |
| 8746 | /* 17701 */ "ANDI16_MM\000" |
| 8747 | /* 17711 */ "MFHI16_MM\000" |
| 8748 | /* 17721 */ "LI16_MM\000" |
| 8749 | /* 17729 */ "BREAK16_MM\000" |
| 8750 | /* 17740 */ "SLL16_MM\000" |
| 8751 | /* 17749 */ "SRL16_MM\000" |
| 8752 | /* 17758 */ "LWM16_MM\000" |
| 8753 | /* 17767 */ "SWM16_MM\000" |
| 8754 | /* 17776 */ "MFLO16_MM\000" |
| 8755 | /* 17786 */ "SDBBP16_MM\000" |
| 8756 | /* 17797 */ "JR16_MM\000" |
| 8757 | /* 17805 */ "JALR16_MM\000" |
| 8758 | /* 17815 */ "XOR16_MM\000" |
| 8759 | /* 17824 */ "JALRS16_MM\000" |
| 8760 | /* 17835 */ "NOT16_MM\000" |
| 8761 | /* 17844 */ "LBU16_MM\000" |
| 8762 | /* 17853 */ "SUBU16_MM\000" |
| 8763 | /* 17863 */ "ADDU16_MM\000" |
| 8764 | /* 17873 */ "LHU16_MM\000" |
| 8765 | /* 17882 */ "LW16_MM\000" |
| 8766 | /* 17890 */ "SW16_MM\000" |
| 8767 | /* 17898 */ "BNEZ16_MM\000" |
| 8768 | /* 17908 */ "BEQZ16_MM\000" |
| 8769 | /* 17918 */ "PRECEU_PH_QBLA_MM\000" |
| 8770 | /* 17936 */ "PRECEQU_PH_QBLA_MM\000" |
| 8771 | /* 17955 */ "PRECEU_PH_QBRA_MM\000" |
| 8772 | /* 17973 */ "PRECEQU_PH_QBRA_MM\000" |
| 8773 | /* 17992 */ "SRA_MM\000" |
| 8774 | /* 17999 */ "SEB_MM\000" |
| 8775 | /* 18006 */ "EHB_MM\000" |
| 8776 | /* 18013 */ "JR_HB_MM\000" |
| 8777 | /* 18022 */ "JALR_HB_MM\000" |
| 8778 | /* 18033 */ "LB_MM\000" |
| 8779 | /* 18039 */ "CMPGU_LE_QB_MM\000" |
| 8780 | /* 18054 */ "CMPU_LE_QB_MM\000" |
| 8781 | /* 18068 */ "PICK_QB_MM\000" |
| 8782 | /* 18079 */ "SHLL_QB_MM\000" |
| 8783 | /* 18090 */ "REPL_QB_MM\000" |
| 8784 | /* 18101 */ "SHRL_QB_MM\000" |
| 8785 | /* 18112 */ "CMPGU_EQ_QB_MM\000" |
| 8786 | /* 18127 */ "CMPU_EQ_QB_MM\000" |
| 8787 | /* 18141 */ "SUBU_S_QB_MM\000" |
| 8788 | /* 18154 */ "ADDU_S_QB_MM\000" |
| 8789 | /* 18167 */ "CMPGU_LT_QB_MM\000" |
| 8790 | /* 18182 */ "CMPU_LT_QB_MM\000" |
| 8791 | /* 18196 */ "SUBU_QB_MM\000" |
| 8792 | /* 18207 */ "ADDU_QB_MM\000" |
| 8793 | /* 18218 */ "SHLLV_QB_MM\000" |
| 8794 | /* 18230 */ "REPLV_QB_MM\000" |
| 8795 | /* 18242 */ "SHRLV_QB_MM\000" |
| 8796 | /* 18254 */ "RADDU_W_QB_MM\000" |
| 8797 | /* 18268 */ "SB_MM\000" |
| 8798 | /* 18274 */ "MODSUB_MM\000" |
| 8799 | /* 18284 */ "PseudoMSUB_MM\000" |
| 8800 | /* 18298 */ "SYNC_MM\000" |
| 8801 | /* 18306 */ "ADDIUPC_MM\000" |
| 8802 | /* 18317 */ "ADDSC_MM\000" |
| 8803 | /* 18326 */ "ADDWC_MM\000" |
| 8804 | /* 18335 */ "BNEZC_MM\000" |
| 8805 | /* 18344 */ "BEQZC_MM\000" |
| 8806 | /* 18353 */ "PseudoMADD_MM\000" |
| 8807 | /* 18367 */ "AND_MM\000" |
| 8808 | /* 18374 */ "LBE_MM\000" |
| 8809 | /* 18381 */ "SBE_MM\000" |
| 8810 | /* 18388 */ "SCE_MM\000" |
| 8811 | /* 18395 */ "CACHEE_MM\000" |
| 8812 | /* 18405 */ "PREFE_MM\000" |
| 8813 | /* 18414 */ "TGE_MM\000" |
| 8814 | /* 18421 */ "CACHE_MM\000" |
| 8815 | /* 18430 */ "LHE_MM\000" |
| 8816 | /* 18437 */ "SHE_MM\000" |
| 8817 | /* 18444 */ "LLE_MM\000" |
| 8818 | /* 18451 */ "LWLE_MM\000" |
| 8819 | /* 18459 */ "SWLE_MM\000" |
| 8820 | /* 18467 */ "BNE_MM\000" |
| 8821 | /* 18474 */ "TNE_MM\000" |
| 8822 | /* 18481 */ "LWRE_MM\000" |
| 8823 | /* 18489 */ "SWRE_MM\000" |
| 8824 | /* 18497 */ "PAUSE_MM\000" |
| 8825 | /* 18506 */ "LWE_MM\000" |
| 8826 | /* 18513 */ "SWE_MM\000" |
| 8827 | /* 18520 */ "LBuE_MM\000" |
| 8828 | /* 18528 */ "LHuE_MM\000" |
| 8829 | /* 18536 */ "BC1F_MM\000" |
| 8830 | /* 18544 */ "PREF_MM\000" |
| 8831 | /* 18552 */ "TLBGINVF_MM\000" |
| 8832 | /* 18564 */ "TAILCALLREG_MM\000" |
| 8833 | /* 18579 */ "WSBH_MM\000" |
| 8834 | /* 18587 */ "SEH_MM\000" |
| 8835 | /* 18594 */ "LH_MM\000" |
| 8836 | /* 18600 */ "SHRA_PH_MM\000" |
| 8837 | /* 18611 */ "PRECRQ_QB_PH_MM\000" |
| 8838 | /* 18627 */ "PRECRQU_S_QB_PH_MM\000" |
| 8839 | /* 18646 */ "CMP_LE_PH_MM\000" |
| 8840 | /* 18659 */ "PICK_PH_MM\000" |
| 8841 | /* 18670 */ "SHLL_PH_MM\000" |
| 8842 | /* 18681 */ "REPL_PH_MM\000" |
| 8843 | /* 18692 */ "PACKRL_PH_MM\000" |
| 8844 | /* 18705 */ "SUBQ_PH_MM\000" |
| 8845 | /* 18716 */ "ADDQ_PH_MM\000" |
| 8846 | /* 18727 */ "CMP_EQ_PH_MM\000" |
| 8847 | /* 18740 */ "SHRA_R_PH_MM\000" |
| 8848 | /* 18753 */ "SHRAV_R_PH_MM\000" |
| 8849 | /* 18767 */ "MULQ_RS_PH_MM\000" |
| 8850 | /* 18781 */ "SHLL_S_PH_MM\000" |
| 8851 | /* 18794 */ "SUBQ_S_PH_MM\000" |
| 8852 | /* 18807 */ "ADDQ_S_PH_MM\000" |
| 8853 | /* 18820 */ "ABSQ_S_PH_MM\000" |
| 8854 | /* 18833 */ "SHLLV_S_PH_MM\000" |
| 8855 | /* 18847 */ "CMP_LT_PH_MM\000" |
| 8856 | /* 18860 */ "SHRAV_PH_MM\000" |
| 8857 | /* 18872 */ "SHLLV_PH_MM\000" |
| 8858 | /* 18884 */ "REPLV_PH_MM\000" |
| 8859 | /* 18896 */ "DPAQ_S_W_PH_MM\000" |
| 8860 | /* 18911 */ "MULSAQ_S_W_PH_MM\000" |
| 8861 | /* 18928 */ "DPSQ_S_W_PH_MM\000" |
| 8862 | /* 18943 */ "SH_MM\000" |
| 8863 | /* 18949 */ "EXTR_S_H_MM\000" |
| 8864 | /* 18961 */ "EXTRV_S_H_MM\000" |
| 8865 | /* 18974 */ "SYNCI_MM\000" |
| 8866 | /* 18983 */ "DI_MM\000" |
| 8867 | /* 18989 */ "TGEI_MM\000" |
| 8868 | /* 18997 */ "TNEI_MM\000" |
| 8869 | /* 19005 */ "PseudoMFHI_MM\000" |
| 8870 | /* 19019 */ "PseudoMTLOHI_MM\000" |
| 8871 | /* 19035 */ "MTHI_MM\000" |
| 8872 | /* 19043 */ "TEQI_MM\000" |
| 8873 | /* 19051 */ "TLTI_MM\000" |
| 8874 | /* 19059 */ "TLBWI_MM\000" |
| 8875 | /* 19068 */ "TLBGWI_MM\000" |
| 8876 | /* 19078 */ "MOVF_I_MM\000" |
| 8877 | /* 19088 */ "MOVN_I_MM\000" |
| 8878 | /* 19098 */ "MOVT_I_MM\000" |
| 8879 | /* 19108 */ "MOVZ_I_MM\000" |
| 8880 | /* 19118 */ "J_MM\000" |
| 8881 | /* 19123 */ "BREAK_MM\000" |
| 8882 | /* 19132 */ "JAL_MM\000" |
| 8883 | /* 19139 */ "BGEZAL_MM\000" |
| 8884 | /* 19149 */ "BLTZAL_MM\000" |
| 8885 | /* 19159 */ "MULEU_S_PH_QBL_MM\000" |
| 8886 | /* 19177 */ "PRECEU_PH_QBL_MM\000" |
| 8887 | /* 19194 */ "PRECEQU_PH_QBL_MM\000" |
| 8888 | /* 19212 */ "DPAU_H_QBL_MM\000" |
| 8889 | /* 19226 */ "DPSU_H_QBL_MM\000" |
| 8890 | /* 19240 */ "MAQ_SA_W_PHL_MM\000" |
| 8891 | /* 19256 */ "PRECEQ_W_PHL_MM\000" |
| 8892 | /* 19272 */ "MAQ_S_W_PHL_MM\000" |
| 8893 | /* 19287 */ "MULEQ_S_W_PHL_MM\000" |
| 8894 | /* 19304 */ "TAILCALL_MM\000" |
| 8895 | /* 19316 */ "HYPCALL_MM\000" |
| 8896 | /* 19327 */ "SYSCALL_MM\000" |
| 8897 | /* 19338 */ "SLL_MM\000" |
| 8898 | /* 19345 */ "SRL_MM\000" |
| 8899 | /* 19352 */ "MUL_MM\000" |
| 8900 | /* 19359 */ "LWL_MM\000" |
| 8901 | /* 19366 */ "SWL_MM\000" |
| 8902 | /* 19373 */ "LWM_MM\000" |
| 8903 | /* 19380 */ "SWM_MM\000" |
| 8904 | /* 19387 */ "CLO_MM\000" |
| 8905 | /* 19394 */ "PseudoMFLO_MM\000" |
| 8906 | /* 19408 */ "SHILO_MM\000" |
| 8907 | /* 19417 */ "MTLO_MM\000" |
| 8908 | /* 19425 */ "TRAP_MM\000" |
| 8909 | /* 19433 */ "SDBBP_MM\000" |
| 8910 | /* 19442 */ "TLBP_MM\000" |
| 8911 | /* 19450 */ "EXTPDP_MM\000" |
| 8912 | /* 19460 */ "MOVEP_MM\000" |
| 8913 | /* 19469 */ "TLBGP_MM\000" |
| 8914 | /* 19478 */ "LWGP_MM\000" |
| 8915 | /* 19486 */ "MTHLIP_MM\000" |
| 8916 | /* 19496 */ "SSNOP_MM\000" |
| 8917 | /* 19505 */ "ADDIUR1SP_MM\000" |
| 8918 | /* 19518 */ "RDDSP_MM\000" |
| 8919 | /* 19527 */ "WRDSP_MM\000" |
| 8920 | /* 19536 */ "LWDSP_MM\000" |
| 8921 | /* 19545 */ "SWDSP_MM\000" |
| 8922 | /* 19554 */ "MSUB_DSP_MM\000" |
| 8923 | /* 19566 */ "MADD_DSP_MM\000" |
| 8924 | /* 19578 */ "MFHI_DSP_MM\000" |
| 8925 | /* 19590 */ "MTHI_DSP_MM\000" |
| 8926 | /* 19602 */ "MFLO_DSP_MM\000" |
| 8927 | /* 19614 */ "MTLO_DSP_MM\000" |
| 8928 | /* 19626 */ "MULT_DSP_MM\000" |
| 8929 | /* 19638 */ "MSUBU_DSP_MM\000" |
| 8930 | /* 19651 */ "MADDU_DSP_MM\000" |
| 8931 | /* 19664 */ "MULTU_DSP_MM\000" |
| 8932 | /* 19677 */ "ADDIUSP_MM\000" |
| 8933 | /* 19688 */ "LWSP_MM\000" |
| 8934 | /* 19696 */ "SWSP_MM\000" |
| 8935 | /* 19704 */ "EXTP_MM\000" |
| 8936 | /* 19712 */ "LWP_MM\000" |
| 8937 | /* 19719 */ "SWP_MM\000" |
| 8938 | /* 19726 */ "BEQ_MM\000" |
| 8939 | /* 19733 */ "TEQ_MM\000" |
| 8940 | /* 19740 */ "TLBR_MM\000" |
| 8941 | /* 19748 */ "MULEU_S_PH_QBR_MM\000" |
| 8942 | /* 19766 */ "PRECEU_PH_QBR_MM\000" |
| 8943 | /* 19783 */ "PRECEQU_PH_QBR_MM\000" |
| 8944 | /* 19801 */ "DPAU_H_QBR_MM\000" |
| 8945 | /* 19815 */ "DPSU_H_QBR_MM\000" |
| 8946 | /* 19829 */ "BAL_BR_MM\000" |
| 8947 | /* 19839 */ "TLBGR_MM\000" |
| 8948 | /* 19848 */ "MAQ_SA_W_PHR_MM\000" |
| 8949 | /* 19864 */ "PRECEQ_W_PHR_MM\000" |
| 8950 | /* 19880 */ "MAQ_S_W_PHR_MM\000" |
| 8951 | /* 19895 */ "MULEQ_S_W_PHR_MM\000" |
| 8952 | /* 19912 */ "JR_MM\000" |
| 8953 | /* 19918 */ "JALR_MM\000" |
| 8954 | /* 19926 */ "NOR_MM\000" |
| 8955 | /* 19933 */ "XOR_MM\000" |
| 8956 | /* 19940 */ "ROTR_MM\000" |
| 8957 | /* 19948 */ "TLBWR_MM\000" |
| 8958 | /* 19957 */ "TLBGWR_MM\000" |
| 8959 | /* 19967 */ "RDHWR_MM\000" |
| 8960 | /* 19976 */ "LWR_MM\000" |
| 8961 | /* 19983 */ "SWR_MM\000" |
| 8962 | /* 19990 */ "JALS_MM\000" |
| 8963 | /* 19998 */ "BGEZALS_MM\000" |
| 8964 | /* 20009 */ "BLTZALS_MM\000" |
| 8965 | /* 20020 */ "INS_MM\000" |
| 8966 | /* 20027 */ "JALRS_MM\000" |
| 8967 | /* 20036 */ "LWXS_MM\000" |
| 8968 | /* 20044 */ "CVT_D32_S_MM\000" |
| 8969 | /* 20057 */ "CVT_D64_S_MM\000" |
| 8970 | /* 20070 */ "FSUB_S_MM\000" |
| 8971 | /* 20080 */ "NMSUB_S_MM\000" |
| 8972 | /* 20091 */ "FADD_S_MM\000" |
| 8973 | /* 20101 */ "NMADD_S_MM\000" |
| 8974 | /* 20112 */ "C_NGE_S_MM\000" |
| 8975 | /* 20123 */ "C_NGLE_S_MM\000" |
| 8976 | /* 20135 */ "C_OLE_S_MM\000" |
| 8977 | /* 20146 */ "C_ULE_S_MM\000" |
| 8978 | /* 20157 */ "C_LE_S_MM\000" |
| 8979 | /* 20167 */ "C_SF_S_MM\000" |
| 8980 | /* 20177 */ "MOVF_S_MM\000" |
| 8981 | /* 20187 */ "C_F_S_MM\000" |
| 8982 | /* 20196 */ "FNEG_S_MM\000" |
| 8983 | /* 20206 */ "MOVN_I_S_MM\000" |
| 8984 | /* 20218 */ "MOVZ_I_S_MM\000" |
| 8985 | /* 20230 */ "C_NGL_S_MM\000" |
| 8986 | /* 20241 */ "FMUL_S_MM\000" |
| 8987 | /* 20251 */ "CVT_L_S_MM\000" |
| 8988 | /* 20262 */ "C_UN_S_MM\000" |
| 8989 | /* 20272 */ "RECIP_S_MM\000" |
| 8990 | /* 20283 */ "C_SEQ_S_MM\000" |
| 8991 | /* 20294 */ "C_UEQ_S_MM\000" |
| 8992 | /* 20305 */ "C_EQ_S_MM\000" |
| 8993 | /* 20315 */ "FABS_S_MM\000" |
| 8994 | /* 20325 */ "C_NGT_S_MM\000" |
| 8995 | /* 20336 */ "C_OLT_S_MM\000" |
| 8996 | /* 20347 */ "C_ULT_S_MM\000" |
| 8997 | /* 20358 */ "C_LT_S_MM\000" |
| 8998 | /* 20368 */ "FSQRT_S_MM\000" |
| 8999 | /* 20379 */ "RSQRT_S_MM\000" |
| 9000 | /* 20390 */ "MOVT_S_MM\000" |
| 9001 | /* 20400 */ "FDIV_S_MM\000" |
| 9002 | /* 20410 */ "FMOV_S_MM\000" |
| 9003 | /* 20420 */ "TRUNC_W_S_MM\000" |
| 9004 | /* 20433 */ "ROUND_W_S_MM\000" |
| 9005 | /* 20446 */ "CEIL_W_S_MM\000" |
| 9006 | /* 20458 */ "FLOOR_W_S_MM\000" |
| 9007 | /* 20471 */ "CVT_W_S_MM\000" |
| 9008 | /* 20482 */ "BC1T_MM\000" |
| 9009 | /* 20490 */ "DERET_MM\000" |
| 9010 | /* 20499 */ "WAIT_MM\000" |
| 9011 | /* 20507 */ "SLT_MM\000" |
| 9012 | /* 20514 */ "TLT_MM\000" |
| 9013 | /* 20521 */ "PseudoMULT_MM\000" |
| 9014 | /* 20535 */ "EXT_MM\000" |
| 9015 | /* 20542 */ "PseudoMSUBU_MM\000" |
| 9016 | /* 20557 */ "PseudoMADDU_MM\000" |
| 9017 | /* 20572 */ "TGEU_MM\000" |
| 9018 | /* 20580 */ "TGEIU_MM\000" |
| 9019 | /* 20589 */ "TLTIU_MM\000" |
| 9020 | /* 20598 */ "TLTU_MM\000" |
| 9021 | /* 20606 */ "LWU_MM\000" |
| 9022 | /* 20613 */ "SRAV_MM\000" |
| 9023 | /* 20621 */ "BITREV_MM\000" |
| 9024 | /* 20631 */ "SDIV_MM\000" |
| 9025 | /* 20639 */ "UDIV_MM\000" |
| 9026 | /* 20647 */ "SLLV_MM\000" |
| 9027 | /* 20655 */ "SRLV_MM\000" |
| 9028 | /* 20663 */ "TLBGINV_MM\000" |
| 9029 | /* 20674 */ "SHILOV_MM\000" |
| 9030 | /* 20684 */ "EXTPDPV_MM\000" |
| 9031 | /* 20695 */ "EXTPV_MM\000" |
| 9032 | /* 20704 */ "ROTRV_MM\000" |
| 9033 | /* 20713 */ "INSV_MM\000" |
| 9034 | /* 20721 */ "LW_MM\000" |
| 9035 | /* 20727 */ "SW_MM\000" |
| 9036 | /* 20733 */ "CVT_D32_W_MM\000" |
| 9037 | /* 20746 */ "CVT_D64_W_MM\000" |
| 9038 | /* 20759 */ "TRUNC_W_MM\000" |
| 9039 | /* 20770 */ "ROUND_W_MM\000" |
| 9040 | /* 20781 */ "PRECRQ_PH_W_MM\000" |
| 9041 | /* 20796 */ "PRECRQ_RS_PH_W_MM\000" |
| 9042 | /* 20814 */ "CEIL_W_MM\000" |
| 9043 | /* 20824 */ "DPAQ_SA_L_W_MM\000" |
| 9044 | /* 20839 */ "DPSQ_SA_L_W_MM\000" |
| 9045 | /* 20854 */ "FLOOR_W_MM\000" |
| 9046 | /* 20865 */ "EXTR_W_MM\000" |
| 9047 | /* 20875 */ "SHRA_R_W_MM\000" |
| 9048 | /* 20887 */ "EXTR_R_W_MM\000" |
| 9049 | /* 20899 */ "SHRAV_R_W_MM\000" |
| 9050 | /* 20912 */ "EXTRV_R_W_MM\000" |
| 9051 | /* 20925 */ "EXTR_RS_W_MM\000" |
| 9052 | /* 20938 */ "EXTRV_RS_W_MM\000" |
| 9053 | /* 20952 */ "SHLL_S_W_MM\000" |
| 9054 | /* 20964 */ "SUBQ_S_W_MM\000" |
| 9055 | /* 20976 */ "ADDQ_S_W_MM\000" |
| 9056 | /* 20988 */ "ABSQ_S_W_MM\000" |
| 9057 | /* 21000 */ "CVT_S_W_MM\000" |
| 9058 | /* 21011 */ "SHLLV_S_W_MM\000" |
| 9059 | /* 21024 */ "EXTRV_W_MM\000" |
| 9060 | /* 21035 */ "PREFX_MM\000" |
| 9061 | /* 21044 */ "LHX_MM\000" |
| 9062 | /* 21051 */ "JALX_MM\000" |
| 9063 | /* 21059 */ "LBUX_MM\000" |
| 9064 | /* 21067 */ "LWX_MM\000" |
| 9065 | /* 21074 */ "BGEZ_MM\000" |
| 9066 | /* 21082 */ "BLEZ_MM\000" |
| 9067 | /* 21090 */ "CLZ_MM\000" |
| 9068 | /* 21097 */ "BGTZ_MM\000" |
| 9069 | /* 21105 */ "BLTZ_MM\000" |
| 9070 | /* 21113 */ "PseudoIndirectBranch_MM\000" |
| 9071 | /* 21137 */ "ADDi_MM\000" |
| 9072 | /* 21145 */ "ANDi_MM\000" |
| 9073 | /* 21153 */ "XORi_MM\000" |
| 9074 | /* 21161 */ "SLTi_MM\000" |
| 9075 | /* 21169 */ "LUi_MM\000" |
| 9076 | /* 21176 */ "LBu_MM\000" |
| 9077 | /* 21183 */ "SUBu_MM\000" |
| 9078 | /* 21191 */ "ADDu_MM\000" |
| 9079 | /* 21199 */ "LHu_MM\000" |
| 9080 | /* 21206 */ "SLTu_MM\000" |
| 9081 | /* 21214 */ "PseudoMULTu_MM\000" |
| 9082 | /* 21229 */ "LEA_ADDiu_MM\000" |
| 9083 | /* 21242 */ "SLTiu_MM\000" |
| 9084 | /* 21251 */ "INLINEASM\000" |
| 9085 | /* 21261 */ "DINSM\000" |
| 9086 | /* 21267 */ "DEXTM\000" |
| 9087 | /* 21273 */ "G_VECREDUCE_FMINIMUM\000" |
| 9088 | /* 21294 */ "G_FMINIMUM\000" |
| 9089 | /* 21305 */ "G_ATOMICRMW_FMINIMUM\000" |
| 9090 | /* 21326 */ "G_VECREDUCE_FMAXIMUM\000" |
| 9091 | /* 21347 */ "G_FMAXIMUM\000" |
| 9092 | /* 21358 */ "G_ATOMICRMW_FMAXIMUM\000" |
| 9093 | /* 21379 */ "G_VECREDUCE_FMINIMUMNUM\000" |
| 9094 | /* 21403 */ "G_FMINIMUMNUM\000" |
| 9095 | /* 21417 */ "G_ATOMICRMW_FMINIMUMNUM\000" |
| 9096 | /* 21441 */ "G_VECREDUCE_FMAXIMUMNUM\000" |
| 9097 | /* 21465 */ "G_FMAXIMUMNUM\000" |
| 9098 | /* 21479 */ "G_ATOMICRMW_FMAXIMUMNUM\000" |
| 9099 | /* 21503 */ "G_FMINNUM\000" |
| 9100 | /* 21513 */ "G_FMAXNUM\000" |
| 9101 | /* 21523 */ "G_FATAN\000" |
| 9102 | /* 21531 */ "G_FTAN\000" |
| 9103 | /* 21538 */ "G_INTRINSIC_ROUNDEVEN\000" |
| 9104 | /* 21560 */ "BALIGN\000" |
| 9105 | /* 21567 */ "DALIGN\000" |
| 9106 | /* 21574 */ "G_ASSERT_ALIGN\000" |
| 9107 | /* 21589 */ "G_FCOPYSIGN\000" |
| 9108 | /* 21601 */ "G_VECREDUCE_FMIN\000" |
| 9109 | /* 21618 */ "G_ATOMICRMW_FMIN\000" |
| 9110 | /* 21635 */ "G_VECREDUCE_SMIN\000" |
| 9111 | /* 21652 */ "G_SMIN\000" |
| 9112 | /* 21659 */ "G_VECREDUCE_UMIN\000" |
| 9113 | /* 21676 */ "G_UMIN\000" |
| 9114 | /* 21683 */ "G_ATOMICRMW_UMIN\000" |
| 9115 | /* 21700 */ "G_ATOMICRMW_MIN\000" |
| 9116 | /* 21716 */ "G_FASIN\000" |
| 9117 | /* 21724 */ "G_FSIN\000" |
| 9118 | /* 21731 */ "DMFC2_OCTEON\000" |
| 9119 | /* 21744 */ "DMTC2_OCTEON\000" |
| 9120 | /* 21757 */ "CFI_INSTRUCTION\000" |
| 9121 | /* 21773 */ "G_CTLZ_ZERO_POISON\000" |
| 9122 | /* 21792 */ "G_CTTZ_ZERO_POISON\000" |
| 9123 | /* 21811 */ "ADJCALLSTACKDOWN\000" |
| 9124 | /* 21828 */ "G_SSUBO\000" |
| 9125 | /* 21836 */ "G_USUBO\000" |
| 9126 | /* 21844 */ "G_SADDO\000" |
| 9127 | /* 21852 */ "G_UADDO\000" |
| 9128 | /* 21860 */ "FEXP2_D_1_PSEUDO\000" |
| 9129 | /* 21877 */ "FEXP2_W_1_PSEUDO\000" |
| 9130 | /* 21894 */ "BPOSGE32_PSEUDO\000" |
| 9131 | /* 21910 */ "INSERT_B_VIDX64_PSEUDO\000" |
| 9132 | /* 21933 */ "INSERT_FD_VIDX64_PSEUDO\000" |
| 9133 | /* 21957 */ "INSERT_D_VIDX64_PSEUDO\000" |
| 9134 | /* 21980 */ "INSERT_H_VIDX64_PSEUDO\000" |
| 9135 | /* 22003 */ "INSERT_FW_VIDX64_PSEUDO\000" |
| 9136 | /* 22027 */ "INSERT_W_VIDX64_PSEUDO\000" |
| 9137 | /* 22050 */ "SNZ_B_PSEUDO\000" |
| 9138 | /* 22063 */ "SZ_B_PSEUDO\000" |
| 9139 | /* 22075 */ "BSEL_FD_PSEUDO\000" |
| 9140 | /* 22090 */ "FILL_FD_PSEUDO\000" |
| 9141 | /* 22105 */ "INSERT_FD_PSEUDO\000" |
| 9142 | /* 22122 */ "COPY_FD_PSEUDO\000" |
| 9143 | /* 22137 */ "BSEL_D_PSEUDO\000" |
| 9144 | /* 22151 */ "AND_V_D_PSEUDO\000" |
| 9145 | /* 22166 */ "NOR_V_D_PSEUDO\000" |
| 9146 | /* 22181 */ "XOR_V_D_PSEUDO\000" |
| 9147 | /* 22196 */ "SNZ_D_PSEUDO\000" |
| 9148 | /* 22209 */ "SZ_D_PSEUDO\000" |
| 9149 | /* 22221 */ "BSEL_H_PSEUDO\000" |
| 9150 | /* 22235 */ "AND_V_H_PSEUDO\000" |
| 9151 | /* 22250 */ "NOR_V_H_PSEUDO\000" |
| 9152 | /* 22265 */ "XOR_V_H_PSEUDO\000" |
| 9153 | /* 22280 */ "SNZ_H_PSEUDO\000" |
| 9154 | /* 22293 */ "SZ_H_PSEUDO\000" |
| 9155 | /* 22305 */ "SNZ_V_PSEUDO\000" |
| 9156 | /* 22318 */ "SZ_V_PSEUDO\000" |
| 9157 | /* 22330 */ "BSEL_FW_PSEUDO\000" |
| 9158 | /* 22345 */ "FILL_FW_PSEUDO\000" |
| 9159 | /* 22360 */ "INSERT_FW_PSEUDO\000" |
| 9160 | /* 22377 */ "COPY_FW_PSEUDO\000" |
| 9161 | /* 22392 */ "BSEL_W_PSEUDO\000" |
| 9162 | /* 22406 */ "AND_V_W_PSEUDO\000" |
| 9163 | /* 22421 */ "NOR_V_W_PSEUDO\000" |
| 9164 | /* 22436 */ "XOR_V_W_PSEUDO\000" |
| 9165 | /* 22451 */ "SNZ_W_PSEUDO\000" |
| 9166 | /* 22464 */ "SZ_W_PSEUDO\000" |
| 9167 | /* 22476 */ "INSERT_B_VIDX_PSEUDO\000" |
| 9168 | /* 22497 */ "INSERT_FD_VIDX_PSEUDO\000" |
| 9169 | /* 22519 */ "INSERT_D_VIDX_PSEUDO\000" |
| 9170 | /* 22540 */ "INSERT_H_VIDX_PSEUDO\000" |
| 9171 | /* 22561 */ "INSERT_FW_VIDX_PSEUDO\000" |
| 9172 | /* 22583 */ "INSERT_W_VIDX_PSEUDO\000" |
| 9173 | /* 22604 */ "JUMP_TABLE_DEBUG_INFO\000" |
| 9174 | /* 22626 */ "DCLO\000" |
| 9175 | /* 22631 */ "PseudoMFLO\000" |
| 9176 | /* 22642 */ "SHILO\000" |
| 9177 | /* 22648 */ "MFTLO\000" |
| 9178 | /* 22654 */ "MTLO\000" |
| 9179 | /* 22659 */ "MTTLO\000" |
| 9180 | /* 22665 */ "G_SMULO\000" |
| 9181 | /* 22673 */ "G_UMULO\000" |
| 9182 | /* 22681 */ "G_BZERO\000" |
| 9183 | /* 22689 */ "STACKMAP\000" |
| 9184 | /* 22698 */ "G_DEBUGTRAP\000" |
| 9185 | /* 22710 */ "G_UBSANTRAP\000" |
| 9186 | /* 22722 */ "G_TRAP\000" |
| 9187 | /* 22729 */ "G_ATOMICRMW_UDEC_WRAP\000" |
| 9188 | /* 22751 */ "G_ATOMICRMW_UINC_WRAP\000" |
| 9189 | /* 22773 */ "G_BSWAP\000" |
| 9190 | /* 22781 */ "DBITSWAP\000" |
| 9191 | /* 22790 */ "SDBBP\000" |
| 9192 | /* 22796 */ "TLBP\000" |
| 9193 | /* 22801 */ "EXTPDP\000" |
| 9194 | /* 22808 */ "G_SITOFP\000" |
| 9195 | /* 22817 */ "G_UITOFP\000" |
| 9196 | /* 22826 */ "TLBGP\000" |
| 9197 | /* 22832 */ "MTHLIP\000" |
| 9198 | /* 22839 */ "G_FCMP\000" |
| 9199 | /* 22846 */ "G_STRICT_FCMP\000" |
| 9200 | /* 22860 */ "G_ICMP\000" |
| 9201 | /* 22867 */ "G_SCMP\000" |
| 9202 | /* 22874 */ "G_UCMP\000" |
| 9203 | /* 22881 */ "SSNOP\000" |
| 9204 | /* 22887 */ "CONVERGENCECTRL_LOOP\000" |
| 9205 | /* 22908 */ "DPOP\000" |
| 9206 | /* 22913 */ "G_CTPOP\000" |
| 9207 | /* 22921 */ "PATCHABLE_OP\000" |
| 9208 | /* 22934 */ "FAULTING_OP\000" |
| 9209 | /* 22946 */ "LOAD_ACC64DSP\000" |
| 9210 | /* 22960 */ "STORE_ACC64DSP\000" |
| 9211 | /* 22975 */ "RDDSP\000" |
| 9212 | /* 22981 */ "WRDSP\000" |
| 9213 | /* 22987 */ "MFTDSP\000" |
| 9214 | /* 22994 */ "MTTDSP\000" |
| 9215 | /* 23001 */ "LWDSP\000" |
| 9216 | /* 23007 */ "SWDSP\000" |
| 9217 | /* 23013 */ "MSUB_DSP\000" |
| 9218 | /* 23022 */ "MADD_DSP\000" |
| 9219 | /* 23031 */ "LOAD_CCOND_DSP\000" |
| 9220 | /* 23046 */ "STORE_CCOND_DSP\000" |
| 9221 | /* 23062 */ "MFHI_DSP\000" |
| 9222 | /* 23071 */ "PseudoMTLOHI_DSP\000" |
| 9223 | /* 23088 */ "MTHI_DSP\000" |
| 9224 | /* 23097 */ "MFLO_DSP\000" |
| 9225 | /* 23106 */ "MTLO_DSP\000" |
| 9226 | /* 23115 */ "MULT_DSP\000" |
| 9227 | /* 23124 */ "MSUBU_DSP\000" |
| 9228 | /* 23134 */ "MADDU_DSP\000" |
| 9229 | /* 23144 */ "MULTU_DSP\000" |
| 9230 | /* 23154 */ "JRADDIUSP\000" |
| 9231 | /* 23164 */ "EXTP\000" |
| 9232 | /* 23169 */ "ADJCALLSTACKUP\000" |
| 9233 | /* 23184 */ "PREALLOCATED_SETUP\000" |
| 9234 | /* 23203 */ "DVP\000" |
| 9235 | /* 23207 */ "EVP\000" |
| 9236 | /* 23211 */ "G_FLDEXP\000" |
| 9237 | /* 23220 */ "G_STRICT_FLDEXP\000" |
| 9238 | /* 23236 */ "G_FEXP\000" |
| 9239 | /* 23243 */ "G_FFREXP\000" |
| 9240 | /* 23252 */ "BEQ\000" |
| 9241 | /* 23256 */ "SEQ\000" |
| 9242 | /* 23260 */ "TEQ\000" |
| 9243 | /* 23264 */ "TLBR\000" |
| 9244 | /* 23269 */ "MULEU_S_PH_QBR\000" |
| 9245 | /* 23284 */ "PRECEU_PH_QBR\000" |
| 9246 | /* 23298 */ "PRECEQU_PH_QBR\000" |
| 9247 | /* 23313 */ "DPAU_H_QBR\000" |
| 9248 | /* 23324 */ "DPSU_H_QBR\000" |
| 9249 | /* 23335 */ "G_BR\000" |
| 9250 | /* 23340 */ "BAL_BR\000" |
| 9251 | /* 23347 */ "INLINEASM_BR\000" |
| 9252 | /* 23360 */ "G_BLOCK_ADDR\000" |
| 9253 | /* 23373 */ "LDR\000" |
| 9254 | /* 23377 */ "SDR\000" |
| 9255 | /* 23381 */ "MEMBARRIER\000" |
| 9256 | /* 23392 */ "G_CONSTANT_FOLD_BARRIER\000" |
| 9257 | /* 23416 */ "PATCHABLE_FUNCTION_ENTER\000" |
| 9258 | /* 23441 */ "G_READCYCLECOUNTER\000" |
| 9259 | /* 23460 */ "G_READSTEADYCOUNTER\000" |
| 9260 | /* 23480 */ "G_READ_REGISTER\000" |
| 9261 | /* 23496 */ "G_WRITE_REGISTER\000" |
| 9262 | /* 23513 */ "TLBGR\000" |
| 9263 | /* 23519 */ "LoadImmDoubleFGR\000" |
| 9264 | /* 23536 */ "LoadImmSingleFGR\000" |
| 9265 | /* 23553 */ "MAQ_SA_W_PHR\000" |
| 9266 | /* 23566 */ "PRECEQ_W_PHR\000" |
| 9267 | /* 23579 */ "MAQ_S_W_PHR\000" |
| 9268 | /* 23591 */ "MULEQ_S_W_PHR\000" |
| 9269 | /* 23605 */ "G_ASHR\000" |
| 9270 | /* 23612 */ "G_FSHR\000" |
| 9271 | /* 23619 */ "G_LSHR\000" |
| 9272 | /* 23626 */ "JR\000" |
| 9273 | /* 23629 */ "JALR\000" |
| 9274 | /* 23634 */ "G_CLMULR\000" |
| 9275 | /* 23643 */ "CONVERGENCECTRL_ANCHOR\000" |
| 9276 | /* 23666 */ "NOR\000" |
| 9277 | /* 23670 */ "G_FFLOOR\000" |
| 9278 | /* 23679 */ "G_SAVGFLOOR\000" |
| 9279 | /* 23691 */ "G_UAVGFLOOR\000" |
| 9280 | /* 23703 */ "DROR\000" |
| 9281 | /* 23708 */ "G_EXTRACT_SUBVECTOR\000" |
| 9282 | /* 23728 */ "G_INSERT_SUBVECTOR\000" |
| 9283 | /* 23747 */ "G_BUILD_VECTOR\000" |
| 9284 | /* 23762 */ "G_SHUFFLE_VECTOR\000" |
| 9285 | /* 23779 */ "G_STEP_VECTOR\000" |
| 9286 | /* 23793 */ "G_SPLAT_VECTOR\000" |
| 9287 | /* 23808 */ "G_VECREDUCE_XOR\000" |
| 9288 | /* 23824 */ "G_XOR\000" |
| 9289 | /* 23830 */ "G_ATOMICRMW_XOR\000" |
| 9290 | /* 23846 */ "G_VECREDUCE_OR\000" |
| 9291 | /* 23861 */ "G_OR\000" |
| 9292 | /* 23866 */ "G_ATOMICRMW_OR\000" |
| 9293 | /* 23881 */ "BuildPairF64_FPR\000" |
| 9294 | /* 23898 */ "MFTGPR\000" |
| 9295 | /* 23905 */ "MTTGPR\000" |
| 9296 | /* 23912 */ "LoadImmDoubleGPR\000" |
| 9297 | /* 23929 */ "LoadImmSingleGPR\000" |
| 9298 | /* 23946 */ "MFTR\000" |
| 9299 | /* 23951 */ "DROTR\000" |
| 9300 | /* 23957 */ "G_ROTR\000" |
| 9301 | /* 23964 */ "G_INTTOPTR\000" |
| 9302 | /* 23975 */ "MTTR\000" |
| 9303 | /* 23980 */ "TLBWR\000" |
| 9304 | /* 23986 */ "TLBGWR\000" |
| 9305 | /* 23993 */ "RDHWR\000" |
| 9306 | /* 23999 */ "LWR\000" |
| 9307 | /* 24003 */ "SWR\000" |
| 9308 | /* 24007 */ "G_FABS\000" |
| 9309 | /* 24014 */ "G_ABS\000" |
| 9310 | /* 24020 */ "G_ABDS\000" |
| 9311 | /* 24027 */ "G_UNMERGE_VALUES\000" |
| 9312 | /* 24044 */ "G_MERGE_VALUES\000" |
| 9313 | /* 24059 */ "G_CTLS\000" |
| 9314 | /* 24066 */ "CINS\000" |
| 9315 | /* 24071 */ "DINS\000" |
| 9316 | /* 24076 */ "G_FACOS\000" |
| 9317 | /* 24084 */ "G_FCOS\000" |
| 9318 | /* 24091 */ "G_FSINCOS\000" |
| 9319 | /* 24101 */ "G_STRICT_FCMPS\000" |
| 9320 | /* 24116 */ "G_CONCAT_VECTORS\000" |
| 9321 | /* 24133 */ "COPY_TO_REGCLASS\000" |
| 9322 | /* 24150 */ "G_IS_FPCLASS\000" |
| 9323 | /* 24163 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000" |
| 9324 | /* 24193 */ "G_VECTOR_COMPRESS\000" |
| 9325 | /* 24211 */ "G_INTRINSIC_W_SIDE_EFFECTS\000" |
| 9326 | /* 24238 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000" |
| 9327 | /* 24276 */ "EXTS\000" |
| 9328 | /* 24281 */ "CVT_D32_S\000" |
| 9329 | /* 24291 */ "CVT_D64_S\000" |
| 9330 | /* 24301 */ "MOVN_I64_S\000" |
| 9331 | /* 24312 */ "MOVZ_I64_S\000" |
| 9332 | /* 24323 */ "MINA_S\000" |
| 9333 | /* 24330 */ "MAXA_S\000" |
| 9334 | /* 24337 */ "FSUB_S\000" |
| 9335 | /* 24344 */ "NMSUB_S\000" |
| 9336 | /* 24352 */ "FADD_S\000" |
| 9337 | /* 24359 */ "NMADD_S\000" |
| 9338 | /* 24367 */ "C_NGE_S\000" |
| 9339 | /* 24375 */ "C_NGLE_S\000" |
| 9340 | /* 24384 */ "C_OLE_S\000" |
| 9341 | /* 24392 */ "CMP_SLE_S\000" |
| 9342 | /* 24402 */ "CMP_SULE_S\000" |
| 9343 | /* 24413 */ "C_ULE_S\000" |
| 9344 | /* 24421 */ "CMP_ULE_S\000" |
| 9345 | /* 24431 */ "C_LE_S\000" |
| 9346 | /* 24438 */ "CMP_LE_S\000" |
| 9347 | /* 24447 */ "CMP_SAF_S\000" |
| 9348 | /* 24457 */ "MSUBF_S\000" |
| 9349 | /* 24465 */ "MADDF_S\000" |
| 9350 | /* 24473 */ "C_SF_S\000" |
| 9351 | /* 24480 */ "MOVF_S\000" |
| 9352 | /* 24487 */ "C_F_S\000" |
| 9353 | /* 24493 */ "PseudoSELECTFP_F_S\000" |
| 9354 | /* 24512 */ "CMP_F_S\000" |
| 9355 | /* 24520 */ "FNEG_S\000" |
| 9356 | /* 24527 */ "MOVN_I_S\000" |
| 9357 | /* 24536 */ "MOVZ_I_S\000" |
| 9358 | /* 24545 */ "SEL_S\000" |
| 9359 | /* 24551 */ "C_NGL_S\000" |
| 9360 | /* 24559 */ "FMUL_S\000" |
| 9361 | /* 24566 */ "TRUNC_L_S\000" |
| 9362 | /* 24576 */ "ROUND_L_S\000" |
| 9363 | /* 24586 */ "CEIL_L_S\000" |
| 9364 | /* 24595 */ "FLOOR_L_S\000" |
| 9365 | /* 24605 */ "CVT_L_S\000" |
| 9366 | /* 24613 */ "MIN_S\000" |
| 9367 | /* 24619 */ "CMP_SUN_S\000" |
| 9368 | /* 24629 */ "C_UN_S\000" |
| 9369 | /* 24636 */ "CMP_UN_S\000" |
| 9370 | /* 24645 */ "RECIP_S\000" |
| 9371 | /* 24653 */ "C_SEQ_S\000" |
| 9372 | /* 24661 */ "CMP_SEQ_S\000" |
| 9373 | /* 24671 */ "CMP_SUEQ_S\000" |
| 9374 | /* 24682 */ "C_UEQ_S\000" |
| 9375 | /* 24690 */ "CMP_UEQ_S\000" |
| 9376 | /* 24700 */ "C_EQ_S\000" |
| 9377 | /* 24707 */ "CMP_EQ_S\000" |
| 9378 | /* 24716 */ "FABS_S\000" |
| 9379 | /* 24723 */ "CLASS_S\000" |
| 9380 | /* 24731 */ "G_TRUNC_SSAT_S\000" |
| 9381 | /* 24746 */ "PseudoSELECT_S\000" |
| 9382 | /* 24761 */ "C_NGT_S\000" |
| 9383 | /* 24769 */ "C_OLT_S\000" |
| 9384 | /* 24777 */ "CMP_SLT_S\000" |
| 9385 | /* 24787 */ "CMP_SULT_S\000" |
| 9386 | /* 24798 */ "C_ULT_S\000" |
| 9387 | /* 24806 */ "CMP_ULT_S\000" |
| 9388 | /* 24816 */ "C_LT_S\000" |
| 9389 | /* 24823 */ "CMP_LT_S\000" |
| 9390 | /* 24832 */ "RINT_S\000" |
| 9391 | /* 24839 */ "FSQRT_S\000" |
| 9392 | /* 24847 */ "RSQRT_S\000" |
| 9393 | /* 24855 */ "MOVT_S\000" |
| 9394 | /* 24862 */ "PseudoSELECTFP_T_S\000" |
| 9395 | /* 24881 */ "FDIV_S\000" |
| 9396 | /* 24888 */ "FMOV_S\000" |
| 9397 | /* 24895 */ "PseudoTRUNC_W_S\000" |
| 9398 | /* 24911 */ "ROUND_W_S\000" |
| 9399 | /* 24921 */ "CEIL_W_S\000" |
| 9400 | /* 24930 */ "FLOOR_W_S\000" |
| 9401 | /* 24940 */ "CVT_W_S\000" |
| 9402 | /* 24948 */ "MAX_S\000" |
| 9403 | /* 24954 */ "SELNEZ_S\000" |
| 9404 | /* 24963 */ "SELEQZ_S\000" |
| 9405 | /* 24972 */ "BC1T\000" |
| 9406 | /* 24977 */ "G_SSUBSAT\000" |
| 9407 | /* 24987 */ "G_USUBSAT\000" |
| 9408 | /* 24997 */ "G_SADDSAT\000" |
| 9409 | /* 25007 */ "G_UADDSAT\000" |
| 9410 | /* 25017 */ "G_SSHLSAT\000" |
| 9411 | /* 25027 */ "G_USHLSAT\000" |
| 9412 | /* 25037 */ "G_SMULFIXSAT\000" |
| 9413 | /* 25050 */ "G_UMULFIXSAT\000" |
| 9414 | /* 25063 */ "G_SDIVFIXSAT\000" |
| 9415 | /* 25076 */ "G_UDIVFIXSAT\000" |
| 9416 | /* 25089 */ "G_ATOMICRMW_USUB_SAT\000" |
| 9417 | /* 25110 */ "G_FPTOSI_SAT\000" |
| 9418 | /* 25123 */ "G_FPTOUI_SAT\000" |
| 9419 | /* 25136 */ "G_EXTRACT\000" |
| 9420 | /* 25146 */ "G_SELECT\000" |
| 9421 | /* 25155 */ "G_BRINDIRECT\000" |
| 9422 | /* 25168 */ "DERET\000" |
| 9423 | /* 25174 */ "PATCHABLE_RET\000" |
| 9424 | /* 25188 */ "G_MEMSET\000" |
| 9425 | /* 25197 */ "BGT\000" |
| 9426 | /* 25201 */ "WAIT\000" |
| 9427 | /* 25206 */ "PATCHABLE_FUNCTION_EXIT\000" |
| 9428 | /* 25230 */ "G_BRJT\000" |
| 9429 | /* 25237 */ "BLT\000" |
| 9430 | /* 25241 */ "G_EXTRACT_VECTOR_ELT\000" |
| 9431 | /* 25262 */ "G_INSERT_VECTOR_ELT\000" |
| 9432 | /* 25282 */ "SLT\000" |
| 9433 | /* 25286 */ "TLT\000" |
| 9434 | /* 25290 */ "PseudoDMULT\000" |
| 9435 | /* 25302 */ "PseudoMULT\000" |
| 9436 | /* 25313 */ "DMT\000" |
| 9437 | /* 25317 */ "EMT\000" |
| 9438 | /* 25321 */ "G_FCONSTANT\000" |
| 9439 | /* 25333 */ "G_CONSTANT\000" |
| 9440 | /* 25344 */ "G_INTRINSIC_CONVERGENT\000" |
| 9441 | /* 25367 */ "STATEPOINT\000" |
| 9442 | /* 25378 */ "PATCHPOINT\000" |
| 9443 | /* 25389 */ "G_PTRTOINT\000" |
| 9444 | /* 25400 */ "G_FRINT\000" |
| 9445 | /* 25408 */ "G_INTRINSIC_LLRINT\000" |
| 9446 | /* 25427 */ "G_INTRINSIC_LRINT\000" |
| 9447 | /* 25445 */ "G_FNEARBYINT\000" |
| 9448 | /* 25458 */ "G_VASTART\000" |
| 9449 | /* 25468 */ "LIFETIME_START\000" |
| 9450 | /* 25483 */ "G_INVOKE_REGION_START\000" |
| 9451 | /* 25505 */ "G_INSERT\000" |
| 9452 | /* 25514 */ "G_FSQRT\000" |
| 9453 | /* 25522 */ "G_STRICT_FSQRT\000" |
| 9454 | /* 25537 */ "G_BITCAST\000" |
| 9455 | /* 25547 */ "G_ADDRSPACE_CAST\000" |
| 9456 | /* 25564 */ "DBG_VALUE_LIST\000" |
| 9457 | /* 25579 */ "GINVT\000" |
| 9458 | /* 25585 */ "DEXT\000" |
| 9459 | /* 25590 */ "G_FPEXT\000" |
| 9460 | /* 25598 */ "G_SEXT\000" |
| 9461 | /* 25605 */ "G_ASSERT_SEXT\000" |
| 9462 | /* 25619 */ "G_ANYEXT\000" |
| 9463 | /* 25628 */ "G_ZEXT\000" |
| 9464 | /* 25635 */ "G_ASSERT_ZEXT\000" |
| 9465 | /* 25649 */ "PseudoMSUBU\000" |
| 9466 | /* 25661 */ "G_ABDU\000" |
| 9467 | /* 25668 */ "PseudoMADDU\000" |
| 9468 | /* 25680 */ "DMODU\000" |
| 9469 | /* 25686 */ "BGEU\000" |
| 9470 | /* 25691 */ "SGEU\000" |
| 9471 | /* 25696 */ "TGEU\000" |
| 9472 | /* 25701 */ "BLEU\000" |
| 9473 | /* 25706 */ "SLEU\000" |
| 9474 | /* 25711 */ "DMUHU\000" |
| 9475 | /* 25717 */ "TGEIU\000" |
| 9476 | /* 25723 */ "TTLTIU\000" |
| 9477 | /* 25730 */ "V3MULU\000" |
| 9478 | /* 25737 */ "DMULU\000" |
| 9479 | /* 25743 */ "VMULU\000" |
| 9480 | /* 25749 */ "DINSU\000" |
| 9481 | /* 25755 */ "BGTU\000" |
| 9482 | /* 25760 */ "BLTU\000" |
| 9483 | /* 25765 */ "TLTU\000" |
| 9484 | /* 25770 */ "DEXTU\000" |
| 9485 | /* 25776 */ "DDIVU\000" |
| 9486 | /* 25782 */ "G_TRUNC_SSAT_U\000" |
| 9487 | /* 25797 */ "G_TRUNC_USAT_U\000" |
| 9488 | /* 25812 */ "DSRAV\000" |
| 9489 | /* 25818 */ "BITREV\000" |
| 9490 | /* 25825 */ "DDIV\000" |
| 9491 | /* 25830 */ "G_FDIV\000" |
| 9492 | /* 25837 */ "G_STRICT_FDIV\000" |
| 9493 | /* 25851 */ "PseudoDSDIV\000" |
| 9494 | /* 25863 */ "G_SDIV\000" |
| 9495 | /* 25870 */ "PseudoSDIV\000" |
| 9496 | /* 25881 */ "PseudoDUDIV\000" |
| 9497 | /* 25893 */ "G_UDIV\000" |
| 9498 | /* 25900 */ "PseudoUDIV\000" |
| 9499 | /* 25911 */ "DSLLV\000" |
| 9500 | /* 25917 */ "DSRLV\000" |
| 9501 | /* 25923 */ "G_GET_FPENV\000" |
| 9502 | /* 25935 */ "G_RESET_FPENV\000" |
| 9503 | /* 25949 */ "G_SET_FPENV\000" |
| 9504 | /* 25961 */ "TLBINV\000" |
| 9505 | /* 25968 */ "TLBGINV\000" |
| 9506 | /* 25976 */ "SHILOV\000" |
| 9507 | /* 25983 */ "EXTPDPV\000" |
| 9508 | /* 25991 */ "EXTPV\000" |
| 9509 | /* 25997 */ "DROTRV\000" |
| 9510 | /* 26004 */ "INSV\000" |
| 9511 | /* 26009 */ "AND_V\000" |
| 9512 | /* 26015 */ "MOVE_V\000" |
| 9513 | /* 26022 */ "BSEL_V\000" |
| 9514 | /* 26029 */ "NOR_V\000" |
| 9515 | /* 26035 */ "XOR_V\000" |
| 9516 | /* 26041 */ "BZ_V\000" |
| 9517 | /* 26046 */ "BMZ_V\000" |
| 9518 | /* 26052 */ "BNZ_V\000" |
| 9519 | /* 26058 */ "BMNZ_V\000" |
| 9520 | /* 26065 */ "CRC32W\000" |
| 9521 | /* 26072 */ "CRC32CW\000" |
| 9522 | /* 26080 */ "LW\000" |
| 9523 | /* 26083 */ "G_FPOW\000" |
| 9524 | /* 26090 */ "SW\000" |
| 9525 | /* 26093 */ "PseudoCVT_D32_W\000" |
| 9526 | /* 26109 */ "FLOG2_W\000" |
| 9527 | /* 26117 */ "FEXP2_W\000" |
| 9528 | /* 26125 */ "PseudoCVT_D64_W\000" |
| 9529 | /* 26141 */ "SRA_W\000" |
| 9530 | /* 26147 */ "ADD_A_W\000" |
| 9531 | /* 26155 */ "FMIN_A_W\000" |
| 9532 | /* 26164 */ "ADDS_A_W\000" |
| 9533 | /* 26173 */ "FMAX_A_W\000" |
| 9534 | /* 26182 */ "FSUB_W\000" |
| 9535 | /* 26189 */ "FMSUB_W\000" |
| 9536 | /* 26197 */ "NLOC_W\000" |
| 9537 | /* 26204 */ "NLZC_W\000" |
| 9538 | /* 26211 */ "FADD_W\000" |
| 9539 | /* 26218 */ "FMADD_W\000" |
| 9540 | /* 26226 */ "SLD_W\000" |
| 9541 | /* 26232 */ "PCKOD_W\000" |
| 9542 | /* 26240 */ "ILVOD_W\000" |
| 9543 | /* 26248 */ "FCLE_W\000" |
| 9544 | /* 26255 */ "FSLE_W\000" |
| 9545 | /* 26262 */ "FCULE_W\000" |
| 9546 | /* 26270 */ "FSULE_W\000" |
| 9547 | /* 26278 */ "FCNE_W\000" |
| 9548 | /* 26285 */ "FSNE_W\000" |
| 9549 | /* 26292 */ "FCUNE_W\000" |
| 9550 | /* 26300 */ "FSUNE_W\000" |
| 9551 | /* 26308 */ "INSVE_W\000" |
| 9552 | /* 26316 */ "FCAF_W\000" |
| 9553 | /* 26323 */ "FSAF_W\000" |
| 9554 | /* 26330 */ "VSHF_W\000" |
| 9555 | /* 26337 */ "BNEG_W\000" |
| 9556 | /* 26344 */ "PRECR_SRA_PH_W\000" |
| 9557 | /* 26359 */ "PRECRQ_PH_W\000" |
| 9558 | /* 26371 */ "PRECR_SRA_R_PH_W\000" |
| 9559 | /* 26388 */ "PRECRQ_RS_PH_W\000" |
| 9560 | /* 26403 */ "SUBQH_W\000" |
| 9561 | /* 26411 */ "ADDQH_W\000" |
| 9562 | /* 26419 */ "SRAI_W\000" |
| 9563 | /* 26426 */ "SLDI_W\000" |
| 9564 | /* 26433 */ "BNEGI_W\000" |
| 9565 | /* 26441 */ "SLLI_W\000" |
| 9566 | /* 26448 */ "SRLI_W\000" |
| 9567 | /* 26455 */ "BINSLI_W\000" |
| 9568 | /* 26464 */ "CEQI_W\000" |
| 9569 | /* 26471 */ "SRARI_W\000" |
| 9570 | /* 26479 */ "BCLRI_W\000" |
| 9571 | /* 26487 */ "SRLRI_W\000" |
| 9572 | /* 26495 */ "BINSRI_W\000" |
| 9573 | /* 26504 */ "SPLATI_W\000" |
| 9574 | /* 26513 */ "BSETI_W\000" |
| 9575 | /* 26521 */ "SUBVI_W\000" |
| 9576 | /* 26529 */ "ADDVI_W\000" |
| 9577 | /* 26537 */ "FILL_W\000" |
| 9578 | /* 26544 */ "SLL_W\000" |
| 9579 | /* 26550 */ "FEXUPL_W\000" |
| 9580 | /* 26559 */ "FFQL_W\000" |
| 9581 | /* 26566 */ "SRL_W\000" |
| 9582 | /* 26572 */ "BINSL_W\000" |
| 9583 | /* 26580 */ "FMUL_W\000" |
| 9584 | /* 26587 */ "ILVL_W\000" |
| 9585 | /* 26594 */ "DPAQ_SA_L_W\000" |
| 9586 | /* 26606 */ "DPSQ_SA_L_W\000" |
| 9587 | /* 26618 */ "FMIN_W\000" |
| 9588 | /* 26625 */ "FCUN_W\000" |
| 9589 | /* 26632 */ "FSUN_W\000" |
| 9590 | /* 26639 */ "FEXDO_W\000" |
| 9591 | /* 26647 */ "FRCP_W\000" |
| 9592 | /* 26654 */ "FCEQ_W\000" |
| 9593 | /* 26661 */ "FSEQ_W\000" |
| 9594 | /* 26668 */ "FCUEQ_W\000" |
| 9595 | /* 26676 */ "FSUEQ_W\000" |
| 9596 | /* 26684 */ "FTQ_W\000" |
| 9597 | /* 26690 */ "MSUB_Q_W\000" |
| 9598 | /* 26699 */ "MADD_Q_W\000" |
| 9599 | /* 26708 */ "MUL_Q_W\000" |
| 9600 | /* 26716 */ "MSUBR_Q_W\000" |
| 9601 | /* 26726 */ "MADDR_Q_W\000" |
| 9602 | /* 26736 */ "MULR_Q_W\000" |
| 9603 | /* 26745 */ "SRAR_W\000" |
| 9604 | /* 26752 */ "LDR_W\000" |
| 9605 | /* 26758 */ "BCLR_W\000" |
| 9606 | /* 26765 */ "SRLR_W\000" |
| 9607 | /* 26772 */ "FCOR_W\000" |
| 9608 | /* 26779 */ "FSOR_W\000" |
| 9609 | /* 26786 */ "FEXUPR_W\000" |
| 9610 | /* 26795 */ "FFQR_W\000" |
| 9611 | /* 26802 */ "BINSR_W\000" |
| 9612 | /* 26810 */ "STR_W\000" |
| 9613 | /* 26816 */ "EXTR_W\000" |
| 9614 | /* 26823 */ "ILVR_W\000" |
| 9615 | /* 26830 */ "SHRA_R_W\000" |
| 9616 | /* 26839 */ "SUBQH_R_W\000" |
| 9617 | /* 26849 */ "ADDQH_R_W\000" |
| 9618 | /* 26859 */ "EXTR_R_W\000" |
| 9619 | /* 26868 */ "SHRAV_R_W\000" |
| 9620 | /* 26878 */ "EXTRV_R_W\000" |
| 9621 | /* 26888 */ "FABS_W\000" |
| 9622 | /* 26895 */ "MULQ_RS_W\000" |
| 9623 | /* 26905 */ "EXTR_RS_W\000" |
| 9624 | /* 26915 */ "EXTRV_RS_W\000" |
| 9625 | /* 26926 */ "FCLASS_W\000" |
| 9626 | /* 26935 */ "ASUB_S_W\000" |
| 9627 | /* 26944 */ "HSUB_S_W\000" |
| 9628 | /* 26953 */ "DPSUB_S_W\000" |
| 9629 | /* 26963 */ "FTRUNC_S_W\000" |
| 9630 | /* 26974 */ "HADD_S_W\000" |
| 9631 | /* 26983 */ "DPADD_S_W\000" |
| 9632 | /* 26993 */ "MOD_S_W\000" |
| 9633 | /* 27001 */ "CLE_S_W\000" |
| 9634 | /* 27009 */ "AVE_S_W\000" |
| 9635 | /* 27017 */ "CLEI_S_W\000" |
| 9636 | /* 27026 */ "MINI_S_W\000" |
| 9637 | /* 27035 */ "CLTI_S_W\000" |
| 9638 | /* 27044 */ "MAXI_S_W\000" |
| 9639 | /* 27053 */ "SHLL_S_W\000" |
| 9640 | /* 27062 */ "MIN_S_W\000" |
| 9641 | /* 27070 */ "DOTP_S_W\000" |
| 9642 | /* 27079 */ "SUBQ_S_W\000" |
| 9643 | /* 27088 */ "ADDQ_S_W\000" |
| 9644 | /* 27097 */ "MULQ_S_W\000" |
| 9645 | /* 27106 */ "ABSQ_S_W\000" |
| 9646 | /* 27115 */ "AVER_S_W\000" |
| 9647 | /* 27124 */ "SUBS_S_W\000" |
| 9648 | /* 27133 */ "ADDS_S_W\000" |
| 9649 | /* 27142 */ "SAT_S_W\000" |
| 9650 | /* 27150 */ "CLT_S_W\000" |
| 9651 | /* 27158 */ "FFINT_S_W\000" |
| 9652 | /* 27168 */ "FTINT_S_W\000" |
| 9653 | /* 27178 */ "PseudoCVT_S_W\000" |
| 9654 | /* 27192 */ "SUBSUU_S_W\000" |
| 9655 | /* 27203 */ "DIV_S_W\000" |
| 9656 | /* 27211 */ "SHLLV_S_W\000" |
| 9657 | /* 27221 */ "MAX_S_W\000" |
| 9658 | /* 27229 */ "COPY_S_W\000" |
| 9659 | /* 27238 */ "SPLAT_W\000" |
| 9660 | /* 27246 */ "BSET_W\000" |
| 9661 | /* 27253 */ "FCLT_W\000" |
| 9662 | /* 27260 */ "FSLT_W\000" |
| 9663 | /* 27267 */ "FCULT_W\000" |
| 9664 | /* 27275 */ "FSULT_W\000" |
| 9665 | /* 27283 */ "PCNT_W\000" |
| 9666 | /* 27290 */ "FRINT_W\000" |
| 9667 | /* 27298 */ "INSERT_W\000" |
| 9668 | /* 27307 */ "FSQRT_W\000" |
| 9669 | /* 27315 */ "FRSQRT_W\000" |
| 9670 | /* 27324 */ "ST_W\000" |
| 9671 | /* 27329 */ "ASUB_U_W\000" |
| 9672 | /* 27338 */ "HSUB_U_W\000" |
| 9673 | /* 27347 */ "DPSUB_U_W\000" |
| 9674 | /* 27357 */ "FTRUNC_U_W\000" |
| 9675 | /* 27368 */ "HADD_U_W\000" |
| 9676 | /* 27377 */ "DPADD_U_W\000" |
| 9677 | /* 27387 */ "MOD_U_W\000" |
| 9678 | /* 27395 */ "CLE_U_W\000" |
| 9679 | /* 27403 */ "AVE_U_W\000" |
| 9680 | /* 27411 */ "CLEI_U_W\000" |
| 9681 | /* 27420 */ "MINI_U_W\000" |
| 9682 | /* 27429 */ "CLTI_U_W\000" |
| 9683 | /* 27438 */ "MAXI_U_W\000" |
| 9684 | /* 27447 */ "MIN_U_W\000" |
| 9685 | /* 27455 */ "DOTP_U_W\000" |
| 9686 | /* 27464 */ "AVER_U_W\000" |
| 9687 | /* 27473 */ "SUBS_U_W\000" |
| 9688 | /* 27482 */ "ADDS_U_W\000" |
| 9689 | /* 27491 */ "SUBSUS_U_W\000" |
| 9690 | /* 27502 */ "SAT_U_W\000" |
| 9691 | /* 27510 */ "CLT_U_W\000" |
| 9692 | /* 27518 */ "FFINT_U_W\000" |
| 9693 | /* 27528 */ "FTINT_U_W\000" |
| 9694 | /* 27538 */ "DIV_U_W\000" |
| 9695 | /* 27546 */ "MAX_U_W\000" |
| 9696 | /* 27554 */ "COPY_U_W\000" |
| 9697 | /* 27563 */ "MSUBV_W\000" |
| 9698 | /* 27571 */ "MADDV_W\000" |
| 9699 | /* 27579 */ "PCKEV_W\000" |
| 9700 | /* 27587 */ "ILVEV_W\000" |
| 9701 | /* 27595 */ "FDIV_W\000" |
| 9702 | /* 27602 */ "MULV_W\000" |
| 9703 | /* 27609 */ "EXTRV_W\000" |
| 9704 | /* 27617 */ "FMAX_W\000" |
| 9705 | /* 27624 */ "BZ_W\000" |
| 9706 | /* 27629 */ "BNZ_W\000" |
| 9707 | /* 27635 */ "G_VECREDUCE_FMAX\000" |
| 9708 | /* 27652 */ "G_ATOMICRMW_FMAX\000" |
| 9709 | /* 27669 */ "G_VECREDUCE_SMAX\000" |
| 9710 | /* 27686 */ "G_SMAX\000" |
| 9711 | /* 27693 */ "G_VECREDUCE_UMAX\000" |
| 9712 | /* 27710 */ "G_UMAX\000" |
| 9713 | /* 27717 */ "G_ATOMICRMW_UMAX\000" |
| 9714 | /* 27734 */ "G_ATOMICRMW_MAX\000" |
| 9715 | /* 27750 */ "MFTACX\000" |
| 9716 | /* 27757 */ "MTTACX\000" |
| 9717 | /* 27764 */ "G_FRAME_INDEX\000" |
| 9718 | /* 27778 */ "G_SBFX\000" |
| 9719 | /* 27785 */ "G_UBFX\000" |
| 9720 | /* 27792 */ "LHX\000" |
| 9721 | /* 27796 */ "G_SMULFIX\000" |
| 9722 | /* 27806 */ "G_UMULFIX\000" |
| 9723 | /* 27816 */ "G_SDIVFIX\000" |
| 9724 | /* 27826 */ "G_UDIVFIX\000" |
| 9725 | /* 27836 */ "JALX\000" |
| 9726 | /* 27841 */ "LBUX\000" |
| 9727 | /* 27846 */ "LWX\000" |
| 9728 | /* 27850 */ "G_MEMCPY\000" |
| 9729 | /* 27859 */ "COPY\000" |
| 9730 | /* 27864 */ "CONSTPOOL_ENTRY\000" |
| 9731 | /* 27880 */ "CONVERGENCECTRL_ENTRY\000" |
| 9732 | /* 27902 */ "BGEZ\000" |
| 9733 | /* 27907 */ "BLEZ\000" |
| 9734 | /* 27912 */ "BC1NEZ\000" |
| 9735 | /* 27919 */ "BC2NEZ\000" |
| 9736 | /* 27926 */ "SELNEZ\000" |
| 9737 | /* 27933 */ "DCLZ\000" |
| 9738 | /* 27938 */ "G_CTLZ\000" |
| 9739 | /* 27945 */ "BC1EQZ\000" |
| 9740 | /* 27952 */ "BC2EQZ\000" |
| 9741 | /* 27959 */ "SELEQZ\000" |
| 9742 | /* 27966 */ "BGTZ\000" |
| 9743 | /* 27971 */ "BLTZ\000" |
| 9744 | /* 27976 */ "G_CTTZ\000" |
| 9745 | /* 27983 */ "SelBneZ\000" |
| 9746 | /* 27991 */ "SelBeqZ\000" |
| 9747 | /* 27999 */ "JalOneReg\000" |
| 9748 | /* 28009 */ "JalTwoReg\000" |
| 9749 | /* 28019 */ "PseudoIndirectHazardBranch\000" |
| 9750 | /* 28046 */ "PseudoIndirectBranch\000" |
| 9751 | /* 28067 */ "Ulh\000" |
| 9752 | /* 28071 */ "Ush\000" |
| 9753 | /* 28075 */ "DADDi\000" |
| 9754 | /* 28081 */ "ANDi\000" |
| 9755 | /* 28086 */ "SNEi\000" |
| 9756 | /* 28091 */ "SEQi\000" |
| 9757 | /* 28096 */ "XORi\000" |
| 9758 | /* 28101 */ "SLTi\000" |
| 9759 | /* 28106 */ "LONG_BRANCH_LUi\000" |
| 9760 | /* 28122 */ "SelTBtneZCmpi\000" |
| 9761 | /* 28136 */ "SelTBteqZCmpi\000" |
| 9762 | /* 28150 */ "SelTBtneZSlti\000" |
| 9763 | /* 28164 */ "SelTBteqZSlti\000" |
| 9764 | /* 28178 */ "SGEImm\000" |
| 9765 | /* 28185 */ "SLEImm\000" |
| 9766 | /* 28192 */ "DROLImm\000" |
| 9767 | /* 28200 */ "NORImm\000" |
| 9768 | /* 28207 */ "DRORImm\000" |
| 9769 | /* 28215 */ "SGTImm\000" |
| 9770 | /* 28222 */ "SGEUImm\000" |
| 9771 | /* 28230 */ "SLEUImm\000" |
| 9772 | /* 28238 */ "SGTUImm\000" |
| 9773 | /* 28246 */ "BneImm\000" |
| 9774 | /* 28253 */ "BeqImm\000" |
| 9775 | /* 28260 */ "PseudoReturn\000" |
| 9776 | /* 28273 */ "JALRHB64Pseudo\000" |
| 9777 | /* 28288 */ "JALR64Pseudo\000" |
| 9778 | /* 28301 */ "JALRHBPseudo\000" |
| 9779 | /* 28314 */ "JALRPseudo\000" |
| 9780 | /* 28325 */ "B_MMR6_Pseudo\000" |
| 9781 | /* 28339 */ "B_MM_Pseudo\000" |
| 9782 | /* 28351 */ "SDIV_MM_Pseudo\000" |
| 9783 | /* 28366 */ "UDIV_MM_Pseudo\000" |
| 9784 | /* 28381 */ "LDMacro\000" |
| 9785 | /* 28389 */ "SDMacro\000" |
| 9786 | /* 28397 */ "SNEMacro\000" |
| 9787 | /* 28406 */ "SNEIMacro\000" |
| 9788 | /* 28416 */ "SEQIMacro\000" |
| 9789 | /* 28426 */ "DSRemIMacro\000" |
| 9790 | /* 28438 */ "DURemIMacro\000" |
| 9791 | /* 28450 */ "DSDivIMacro\000" |
| 9792 | /* 28462 */ "DUDivIMacro\000" |
| 9793 | /* 28474 */ "DMULMacro\000" |
| 9794 | /* 28484 */ "DMULOMacro\000" |
| 9795 | /* 28495 */ "SEQMacro\000" |
| 9796 | /* 28504 */ "ABSMacro\000" |
| 9797 | /* 28513 */ "DMULOUMacro\000" |
| 9798 | /* 28525 */ "DSRemMacro\000" |
| 9799 | /* 28536 */ "DURemMacro\000" |
| 9800 | /* 28547 */ "BGEImmMacro\000" |
| 9801 | /* 28559 */ "BLEImmMacro\000" |
| 9802 | /* 28571 */ "BGELImmMacro\000" |
| 9803 | /* 28584 */ "BLELImmMacro\000" |
| 9804 | /* 28597 */ "BNELImmMacro\000" |
| 9805 | /* 28610 */ "BEQLImmMacro\000" |
| 9806 | /* 28623 */ "BGTLImmMacro\000" |
| 9807 | /* 28636 */ "BLTLImmMacro\000" |
| 9808 | /* 28649 */ "BGEULImmMacro\000" |
| 9809 | /* 28663 */ "BLEULImmMacro\000" |
| 9810 | /* 28677 */ "DMULImmMacro\000" |
| 9811 | /* 28690 */ "BGTULImmMacro\000" |
| 9812 | /* 28704 */ "BLTULImmMacro\000" |
| 9813 | /* 28718 */ "BGTImmMacro\000" |
| 9814 | /* 28730 */ "BLTImmMacro\000" |
| 9815 | /* 28742 */ "BGEUImmMacro\000" |
| 9816 | /* 28755 */ "BLEUImmMacro\000" |
| 9817 | /* 28768 */ "BGTUImmMacro\000" |
| 9818 | /* 28781 */ "BLTUImmMacro\000" |
| 9819 | /* 28794 */ "DSDivMacro\000" |
| 9820 | /* 28805 */ "DUDivMacro\000" |
| 9821 | /* 28816 */ "LONG_BRANCH_LUi2Op\000" |
| 9822 | /* 28835 */ "LONG_BRANCH_DADDiu2Op\000" |
| 9823 | /* 28857 */ "LONG_BRANCH_ADDiu2Op\000" |
| 9824 | /* 28878 */ "SelTBtneZCmp\000" |
| 9825 | /* 28891 */ "SelTBteqZCmp\000" |
| 9826 | /* 28904 */ "SaaAddr\000" |
| 9827 | /* 28912 */ "SaadAddr\000" |
| 9828 | /* 28921 */ "ERet\000" |
| 9829 | /* 28926 */ "SelTBtneZSlt\000" |
| 9830 | /* 28939 */ "SelTBteqZSlt\000" |
| 9831 | /* 28952 */ "LBu\000" |
| 9832 | /* 28956 */ "DSUBu\000" |
| 9833 | /* 28962 */ "BADDu\000" |
| 9834 | /* 28968 */ "DADDu\000" |
| 9835 | /* 28974 */ "LHu\000" |
| 9836 | /* 28978 */ "SLTu\000" |
| 9837 | /* 28983 */ "PseudoDMULTu\000" |
| 9838 | /* 28996 */ "PseudoMULTu\000" |
| 9839 | /* 29008 */ "LWu\000" |
| 9840 | /* 29012 */ "Ulhu\000" |
| 9841 | /* 29017 */ "LONG_BRANCH_DADDiu\000" |
| 9842 | /* 29036 */ "LEA_ADDiu\000" |
| 9843 | /* 29046 */ "LONG_BRANCH_ADDiu\000" |
| 9844 | /* 29064 */ "SLTiu\000" |
| 9845 | /* 29070 */ "SelTBtneZSltiu\000" |
| 9846 | /* 29085 */ "SelTBteqZSltiu\000" |
| 9847 | /* 29100 */ "SelTBtneZSltu\000" |
| 9848 | /* 29114 */ "SelTBteqZSltu\000" |
| 9849 | /* 29128 */ "Ulw\000" |
| 9850 | /* 29132 */ "Usw\000" |
| 9851 | }; |
| 9852 | #ifdef __GNUC__ |
| 9853 | #pragma GCC diagnostic pop |
| 9854 | #endif |
| 9855 | |
| 9856 | extern const unsigned MipsInstrNameIndices[] = { |
| 9857 | 15622U, 21251U, 23347U, 21757U, 15988U, 15969U, 15997U, 16271U, |
| 9858 | 13918U, 13933U, 13798U, 13785U, 13972U, 24133U, 13638U, 25564U, |
| 9859 | 13816U, 15618U, 15978U, 13271U, 27859U, 15845U, 13443U, 25468U, |
| 9860 | 11695U, 13218U, 13259U, 22689U, 16243U, 25378U, 11807U, 23184U, |
| 9861 | 14065U, 25367U, 13523U, 22934U, 22921U, 23416U, 25174U, 25206U, |
| 9862 | 16175U, 16222U, 16195U, 16029U, 13629U, 23381U, 22604U, 13504U, |
| 9863 | 27880U, 23643U, 22887U, 13686U, 25605U, 25635U, 21574U, 11578U, |
| 9864 | 10299U, 16435U, 25863U, 25893U, 16536U, 16543U, 16550U, 16560U, |
| 9865 | 11658U, 23861U, 23824U, 24020U, 25661U, 23691U, 16139U, 23679U, |
| 9866 | 16128U, 13796U, 15620U, 27764U, 13648U, 13663U, 16281U, 25136U, |
| 9867 | 24027U, 25505U, 24044U, 23747U, 11185U, 24116U, 25389U, 23964U, |
| 9868 | 25537U, 13737U, 23392U, 11776U, 11159U, 11758U, 25427U, 25408U, |
| 9869 | 21538U, 23441U, 23460U, 11451U, 11395U, 11425U, 11364U, 11436U, |
| 9870 | 11376U, 11406U, 13592U, 13546U, 13576U, 24163U, 13986U, 14003U, |
| 9871 | 11594U, 10305U, 11664U, 11625U, 23866U, 23830U, 27734U, 21700U, |
| 9872 | 27717U, 21683U, 11534U, 10271U, 27652U, 21618U, 21358U, 21305U, |
| 9873 | 21479U, 21417U, 22751U, 22729U, 11717U, 25089U, 13251U, 14107U, |
| 9874 | 11708U, 25155U, 25483U, 11071U, 24211U, 25344U, 24238U, 25619U, |
| 9875 | 11177U, 24731U, 25782U, 25797U, 25333U, 25321U, 25458U, 14057U, |
| 9876 | 25598U, 13959U, 25628U, 16114U, 23619U, 23605U, 16107U, 23612U, |
| 9877 | 23957U, 16328U, 22860U, 22839U, 22867U, 22874U, 25146U, 21852U, |
| 9878 | 13296U, 21836U, 13243U, 21844U, 13288U, 21828U, 13235U, 22673U, |
| 9879 | 22665U, 14139U, 14131U, 25007U, 24997U, 24987U, 24977U, 25027U, |
| 9880 | 25017U, 27796U, 27806U, 25037U, 25050U, 27816U, 27826U, 25063U, |
| 9881 | 25076U, 11492U, 10250U, 16369U, 8504U, 11357U, 25830U, 16515U, |
| 9882 | 13777U, 26083U, 15700U, 23236U, 1223U, 9U, 14050U, 1196U, |
| 9883 | 0U, 23211U, 23243U, 13847U, 25590U, 11149U, 15648U, 15672U, |
| 9884 | 22808U, 22817U, 25110U, 25123U, 24007U, 21589U, 24150U, 13746U, |
| 9885 | 21503U, 21513U, 13345U, 13360U, 21294U, 21347U, 21403U, 21465U, |
| 9886 | 25923U, 25949U, 25935U, 13304U, 13332U, 13317U, 14020U, 14035U, |
| 9887 | 11584U, 15859U, 21652U, 27686U, 21676U, 27710U, 24014U, 11749U, |
| 9888 | 11739U, 23335U, 25230U, 13421U, 23728U, 23708U, 25262U, 25241U, |
| 9889 | 23762U, 23793U, 23779U, 24193U, 27976U, 21792U, 27938U, 21773U, |
| 9890 | 24059U, 22913U, 22773U, 13610U, 16411U, 14122U, 23634U, 16120U, |
| 9891 | 24084U, 21724U, 24091U, 21531U, 24076U, 21716U, 21523U, 1209U, |
| 9892 | 14686U, 14155U, 14147U, 25514U, 23670U, 25400U, 25445U, 25547U, |
| 9893 | 23360U, 13430U, 11211U, 13707U, 13561U, 11520U, 10257U, 16397U, |
| 9894 | 25837U, 16522U, 8510U, 25522U, 23220U, 22846U, 24101U, 23480U, |
| 9895 | 23496U, 27850U, 13488U, 13719U, 25188U, 22681U, 13472U, 22722U, |
| 9896 | 22698U, 22710U, 11499U, 16376U, 11475U, 16352U, 27635U, 21601U, |
| 9897 | 21326U, 21273U, 21441U, 21379U, 11562U, 16419U, 11642U, 23846U, |
| 9898 | 23808U, 27669U, 21635U, 27693U, 21659U, 27778U, 27785U, 28504U, |
| 9899 | 21811U, 23169U, 22151U, 22235U, 22406U, 4068U, 9390U, 893U, |
| 9900 | 8746U, 3107U, 9068U, 8374U, 9705U, 3950U, 9230U, 775U, |
| 9901 | 8586U, 2937U, 8908U, 8262U, 9551U, 3991U, 9285U, 816U, |
| 9902 | 8641U, 2978U, 8963U, 8301U, 9604U, 4148U, 9498U, 973U, |
| 9903 | 8854U, 3253U, 9176U, 8450U, 9809U, 4032U, 9340U, 857U, |
| 9904 | 8696U, 3071U, 9018U, 8340U, 9657U, 3970U, 9257U, 795U, |
| 9905 | 8613U, 2957U, 8935U, 8281U, 9577U, 4108U, 9444U, 933U, |
| 9906 | 8800U, 3147U, 9122U, 8412U, 9757U, 3930U, 9203U, 755U, |
| 9907 | 8559U, 2917U, 8881U, 8243U, 9525U, 4127U, 9470U, 952U, |
| 9908 | 8826U, 3232U, 9148U, 8430U, 9782U, 4011U, 9312U, 836U, |
| 9909 | 8668U, 3050U, 8990U, 8320U, 9630U, 4088U, 9417U, 913U, |
| 9910 | 8773U, 3127U, 9095U, 8393U, 9731U, 4052U, 9367U, 877U, |
| 9911 | 8723U, 3091U, 9045U, 8359U, 9683U, 9865U, 23340U, 19829U, |
| 9912 | 28610U, 13388U, 28547U, 16014U, 28571U, 25686U, 28742U, 16335U, |
| 9913 | 28649U, 25197U, 28718U, 16318U, 28623U, 25755U, 28768U, 16441U, |
| 9914 | 28690U, 13439U, 28559U, 16019U, 28584U, 25701U, 28755U, 16341U, |
| 9915 | 28663U, 25237U, 28730U, 16323U, 28636U, 25760U, 28781U, 16447U, |
| 9916 | 28704U, 28597U, 21894U, 22137U, 22075U, 22330U, 22221U, 22392U, |
| 9917 | 18001U, 28325U, 28339U, 28253U, 28246U, 4672U, 4219U, 4700U, |
| 9918 | 4249U, 4730U, 4761U, 4658U, 4204U, 4686U, 4234U, 4714U, |
| 9919 | 4746U, 2795U, 3565U, 23881U, 131U, 27864U, 22122U, 22377U, |
| 9920 | 149U, 1153U, 28677U, 28474U, 28484U, 28513U, 16297U, 28192U, |
| 9921 | 23703U, 28207U, 28450U, 28794U, 28426U, 28525U, 28462U, 28805U, |
| 9922 | 28438U, 28536U, 28921U, 2808U, 3581U, 12510U, 26888U, 21860U, |
| 9923 | 21877U, 22090U, 22345U, 4819U, 21910U, 22476U, 21957U, 22519U, |
| 9924 | 22105U, 21933U, 22497U, 22360U, 22003U, 22561U, 21980U, 22540U, |
| 9925 | 22027U, 22583U, 28288U, 28273U, 28301U, 28314U, 6956U, 27999U, |
| 9926 | 28009U, 28381U, 12439U, 26752U, 8218U, 2062U, 22946U, 23031U, |
| 9927 | 29046U, 28857U, 29017U, 28835U, 28106U, 28816U, 3611U, 19373U, |
| 9928 | 1121U, 3821U, 1088U, 3633U, 1111U, 3811U, 23519U, 1068U, |
| 9929 | 23912U, 23536U, 23929U, 1151U, 27750U, 52U, 137U, 22987U, |
| 9930 | 23898U, 112U, 15626U, 22648U, 1135U, 3850U, 27757U, 64U, |
| 9931 | 155U, 22994U, 23905U, 119U, 15637U, 22659U, 28678U, 28485U, |
| 9932 | 28514U, 5079U, 5212U, 5111U, 5264U, 22883U, 28200U, 3744U, |
| 9933 | 22166U, 22250U, 22421U, 22167U, 22251U, 22422U, 10045U, 9947U, |
| 9934 | 10160U, 14317U, 14212U, 14477U, 26093U, 16485U, 26125U, 16501U, |
| 9935 | 27178U, 25290U, 28983U, 25851U, 25881U, 15774U, 3166U, 28046U, |
| 9936 | 3676U, 5324U, 8195U, 21113U, 7989U, 28019U, 3647U, 5294U, |
| 9937 | 8167U, 11551U, 25668U, 20557U, 18353U, 15594U, 2856U, 19005U, |
| 9938 | 22631U, 3301U, 19394U, 10288U, 25649U, 20542U, 18284U, 15605U, |
| 9939 | 2869U, 23071U, 19019U, 25302U, 20521U, 28996U, 21214U, 14246U, |
| 9940 | 9982U, 28260U, 3835U, 25870U, 388U, 2380U, 15737U, 3007U, |
| 9941 | 24493U, 644U, 2693U, 15813U, 3211U, 24862U, 559U, 2608U, |
| 9942 | 15791U, 3185U, 24746U, 13162U, 683U, 24895U, 25900U, 16298U, |
| 9943 | 28193U, 23704U, 28208U, 9835U, 3915U, 212U, 28351U, 28389U, |
| 9944 | 28451U, 28795U, 28416U, 28495U, 13392U, 28178U, 3726U, 25691U, |
| 9945 | 28222U, 3771U, 28215U, 3753U, 28238U, 3791U, 13454U, 28185U, |
| 9946 | 3735U, 25706U, 28230U, 3781U, 3762U, 3801U, 28406U, 28397U, |
| 9947 | 22050U, 22196U, 22280U, 22305U, 22451U, 28427U, 28526U, 8230U, |
| 9948 | 2073U, 22960U, 23046U, 12497U, 26810U, 19380U, 22063U, 22209U, |
| 9949 | 22293U, 22318U, 22464U, 28904U, 28912U, 27991U, 27983U, 28891U, |
| 9950 | 28136U, 28939U, 28164U, 29085U, 29114U, 28878U, 28122U, 28926U, |
| 9951 | 28150U, 29070U, 29100U, 5024U, 4483U, 4498U, 5036U, 5251U, |
| 9952 | 16150U, 13872U, 13854U, 13888U, 13904U, 13947U, 2826U, 9883U, |
| 9953 | 2018U, 18564U, 6833U, 19304U, 6965U, 22705U, 19425U, 28366U, |
| 9954 | 28463U, 28806U, 28439U, 28537U, 28067U, 29012U, 29128U, 28071U, |
| 9955 | 29132U, 22181U, 22265U, 22436U, 14436U, 18820U, 10105U, 1371U, |
| 9956 | 27106U, 20988U, 11471U, 11246U, 18306U, 6010U, 19505U, 17233U, |
| 9957 | 17646U, 19677U, 7875U, 14237U, 1474U, 14354U, 1529U, 26849U, |
| 9958 | 1887U, 26411U, 1859U, 14309U, 18716U, 14416U, 18807U, 27088U, |
| 9959 | 20976U, 3419U, 11270U, 18317U, 10343U, 11880U, 14721U, 26164U, |
| 9960 | 10751U, 12679U, 15210U, 27133U, 10943U, 13044U, 15459U, 27482U, |
| 9961 | 17863U, 5750U, 9973U, 1276U, 10083U, 1339U, 7845U, 14501U, |
| 9962 | 1617U, 10185U, 18207U, 14456U, 1589U, 10125U, 18154U, 10557U, |
| 9963 | 12244U, 14906U, 26529U, 11013U, 13125U, 15529U, 27572U, 11303U, |
| 9964 | 18326U, 10327U, 11863U, 14705U, 26147U, 18360U, 6232U, 28076U, |
| 9965 | 21137U, 29030U, 21233U, 28963U, 21191U, 21561U, 7023U, 11239U, |
| 9966 | 5998U, 11638U, 17674U, 5591U, 2196U, 17701U, 5624U, 10432U, |
| 9967 | 6888U, 18367U, 6241U, 26009U, 28081U, 3699U, 21145U, 11688U, |
| 9968 | 1431U, 10656U, 12526U, 15059U, 26935U, 10848U, 12891U, 15317U, |
| 9969 | 27329U, 15668U, 11233U, 5987U, 6916U, 10733U, 12661U, 15183U, |
| 9970 | 27115U, 10925U, 13026U, 15441U, 27464U, 10681U, 12600U, 15122U, |
| 9971 | 27009U, 10873U, 12965U, 15380U, 27403U, 4551U, 4427U, 4935U, |
| 9972 | 4579U, 4376U, 4875U, 4443U, 5238U, 5177U, 17658U, 28962U, |
| 9973 | 15869U, 11083U, 5866U, 21560U, 1792U, 85U, 231U, 225U, |
| 9974 | 239U, 11054U, 5531U, 27945U, 6173U, 13772U, 16049U, 18536U, |
| 9975 | 27912U, 6136U, 24972U, 16312U, 20482U, 27952U, 6186U, 27919U, |
| 9976 | 6149U, 10493U, 12194U, 14856U, 26479U, 10627U, 12445U, 15030U, |
| 9977 | 26758U, 5829U, 23252U, 3321U, 11265U, 2113U, 6033U, 16302U, |
| 9978 | 17908U, 11118U, 5926U, 11327U, 5578U, 2172U, 18344U, 6199U, |
| 9979 | 19726U, 11057U, 2085U, 5837U, 11281U, 2132U, 6072U, 27902U, |
| 9980 | 3519U, 15881U, 11094U, 5887U, 16255U, 19998U, 19139U, 11309U, |
| 9981 | 2148U, 6114U, 16461U, 21074U, 27966U, 3551U, 11126U, 5939U, |
| 9982 | 11333U, 2180U, 6210U, 16473U, 21097U, 10469U, 12170U, 14832U, |
| 9983 | 26455U, 10599U, 12293U, 14933U, 26572U, 10523U, 12210U, 14872U, |
| 9984 | 26495U, 10641U, 12489U, 15044U, 26802U, 25818U, 20621U, 22782U, |
| 9985 | 7043U, 27907U, 3526U, 11102U, 5900U, 11315U, 2156U, 6125U, |
| 9986 | 16467U, 21082U, 11276U, 2125U, 6062U, 11287U, 2140U, 6083U, |
| 9987 | 27971U, 3558U, 15888U, 11134U, 5952U, 16263U, 20009U, 19149U, |
| 9988 | 11339U, 2188U, 6221U, 16479U, 21105U, 10572U, 26058U, 10565U, |
| 9989 | 26046U, 13468U, 2789U, 11062U, 2092U, 5847U, 10439U, 12148U, |
| 9990 | 14810U, 26433U, 10411U, 12127U, 14789U, 26337U, 16024U, 17898U, |
| 9991 | 11110U, 5913U, 11321U, 5565U, 2164U, 18335U, 6162U, 18467U, |
| 9992 | 11293U, 6094U, 11048U, 13199U, 15564U, 26052U, 27629U, 11298U, |
| 9993 | 6104U, 746U, 1951U, 17175U, 15834U, 17729U, 5646U, 19123U, |
| 9994 | 6945U, 10447U, 26022U, 10541U, 12228U, 14890U, 26513U, 10820U, |
| 9995 | 12768U, 15289U, 27246U, 11043U, 13185U, 15559U, 26041U, 27624U, |
| 9996 | 4962U, 4608U, 4974U, 4621U, 4950U, 4595U, 4861U, 5286U, |
| 9997 | 4785U, 5278U, 4776U, 13400U, 13375U, 18395U, 18421U, 6776U, |
| 9998 | 8111U, 2475U, 6439U, 24586U, 7423U, 713U, 2756U, 6708U, |
| 9999 | 20814U, 24921U, 20446U, 7704U, 10478U, 12179U, 14841U, 26464U, |
| 10000 | 10614U, 12363U, 14956U, 26655U, 101U, 16624U, 17217U, 9846U, |
| 10001 | 24066U, 1015U, 1048U, 1102U, 12518U, 6581U, 24723U, 7565U, |
| 10002 | 10689U, 12608U, 15130U, 27017U, 10881U, 12973U, 15388U, 27411U, |
| 10003 | 10673U, 12592U, 15114U, 27001U, 10865U, 12957U, 15372U, 27395U, |
| 10004 | 22627U, 19387U, 7034U, 8143U, 10707U, 12626U, 15148U, 27035U, |
| 10005 | 10899U, 12991U, 15406U, 27429U, 10768U, 12696U, 15227U, 27150U, |
| 10006 | 10971U, 13072U, 15487U, 27510U, 27934U, 21090U, 7968U, 8160U, |
| 10007 | 10020U, 1290U, 9922U, 1244U, 10135U, 1386U, 10033U, 18112U, |
| 10008 | 9935U, 18039U, 10148U, 18167U, 10051U, 18127U, 9953U, 18054U, |
| 10009 | 10166U, 18182U, 6358U, 7318U, 12423U, 6567U, 14323U, 18727U, |
| 10010 | 24707U, 7551U, 12119U, 24512U, 12025U, 6329U, 14218U, 18646U, |
| 10011 | 24438U, 7289U, 12836U, 6640U, 14483U, 18847U, 24823U, 7624U, |
| 10012 | 12086U, 6343U, 24447U, 7303U, 12376U, 6521U, 24661U, 7505U, |
| 10013 | 11978U, 6283U, 24392U, 7243U, 12789U, 6594U, 24777U, 7578U, |
| 10014 | 12402U, 6536U, 24671U, 7520U, 12004U, 6298U, 24402U, 7258U, |
| 10015 | 12815U, 6609U, 24787U, 7593U, 12336U, 6492U, 24619U, 7476U, |
| 10016 | 12413U, 6552U, 24690U, 7536U, 12015U, 6314U, 24421U, 7274U, |
| 10017 | 12826U, 6625U, 24806U, 7609U, 12346U, 6507U, 24636U, 7491U, |
| 10018 | 10803U, 12751U, 15272U, 27229U, 10995U, 15511U, 27554U, 9860U, |
| 10019 | 9867U, 11458U, 14099U, 26072U, 11345U, 14082U, 26065U, 126U, |
| 10020 | 16640U, 17225U, 9853U, 24281U, 20044U, 26099U, 20733U, 16491U, |
| 10021 | 24291U, 20057U, 26131U, 20746U, 6997U, 2498U, 17431U, 6468U, |
| 10022 | 24605U, 20251U, 7452U, 3502U, 3469U, 3457U, 549U, 17036U, |
| 10023 | 2598U, 17519U, 16507U, 7010U, 3278U, 3486U, 27184U, 21000U, |
| 10024 | 7943U, 736U, 17162U, 2779U, 17633U, 24940U, 20471U, 7733U, |
| 10025 | 531U, 17012U, 2580U, 17495U, 24700U, 20305U, 380U, 16873U, |
| 10026 | 2372U, 17383U, 24487U, 20187U, 353U, 16837U, 2345U, 17359U, |
| 10027 | 24431U, 20157U, 606U, 17088U, 2655U, 17571U, 24816U, 20358U, |
| 10028 | 312U, 16784U, 2304U, 17306U, 24367U, 20112U, 322U, 16797U, |
| 10029 | 2314U, 17319U, 24375U, 20123U, 440U, 16924U, 2432U, 17406U, |
| 10030 | 24551U, 20230U, 576U, 17049U, 2625U, 17532U, 24761U, 20325U, |
| 10031 | 333U, 16811U, 2325U, 17333U, 24384U, 20135U, 586U, 17062U, |
| 10032 | 2635U, 17545U, 24769U, 20336U, 511U, 16986U, 2560U, 17469U, |
| 10033 | 24653U, 20283U, 362U, 16849U, 2354U, 17371U, 24473U, 20167U, |
| 10034 | 521U, 16999U, 2570U, 17482U, 24682U, 20294U, 343U, 16824U, |
| 10035 | 2335U, 17346U, 24413U, 20146U, 596U, 17075U, 2645U, 17558U, |
| 10036 | 24798U, 20347U, 483U, 16949U, 2532U, 17444U, 24629U, 20262U, |
| 10037 | 5059U, 4898U, 4525U, 11470U, 28075U, 29029U, 28968U, 15589U, |
| 10038 | 21567U, 15657U, 15667U, 22781U, 22626U, 8142U, 27933U, 8159U, |
| 10039 | 25825U, 25776U, 25168U, 20490U, 7785U, 25585U, 1058U, 21267U, |
| 10040 | 25770U, 15576U, 24071U, 21261U, 25749U, 25826U, 25777U, 7896U, |
| 10041 | 7906U, 10787U, 12735U, 15246U, 27203U, 10979U, 13100U, 15495U, |
| 10042 | 27538U, 18983U, 6890U, 9841U, 8074U, 18U, 106U, 1174U, |
| 10043 | 21731U, 24U, 11802U, 25680U, 25313U, 58U, 143U, 1180U, |
| 10044 | 21744U, 45U, 14694U, 25711U, 16347U, 25296U, 28989U, 25737U, |
| 10045 | 8134U, 12652U, 15174U, 27070U, 13017U, 15432U, 27455U, 12574U, |
| 10046 | 15096U, 26983U, 12939U, 15354U, 27377U, 14565U, 1674U, 14640U, |
| 10047 | 1726U, 26594U, 20824U, 14602U, 18896U, 15939U, 19212U, 23313U, |
| 10048 | 19801U, 14666U, 1762U, 14545U, 1644U, 22908U, 14579U, 1693U, |
| 10049 | 14653U, 1744U, 26606U, 20839U, 14628U, 18928U, 12544U, 15077U, |
| 10050 | 26953U, 12909U, 15335U, 27347U, 15950U, 19226U, 23324U, 19815U, |
| 10051 | 14676U, 1777U, 14593U, 1712U, 23951U, 1007U, 25997U, 14089U, |
| 10052 | 25857U, 11610U, 16276U, 993U, 1038U, 25911U, 8554U, 247U, |
| 10053 | 25812U, 16307U, 1000U, 25917U, 10245U, 28956U, 25887U, 23203U, |
| 10054 | 13536U, 7115U, 5145U, 5123U, 9879U, 18006U, 5781U, 15581U, |
| 10055 | 18991U, 6898U, 25317U, 25169U, 11142U, 5965U, 20491U, 7786U, |
| 10056 | 23207U, 13541U, 7124U, 25586U, 23164U, 22801U, 25983U, 20684U, |
| 10057 | 19450U, 25991U, 20695U, 19704U, 26915U, 20938U, 26878U, 20912U, |
| 10058 | 15254U, 18961U, 27609U, 21024U, 26905U, 20925U, 26859U, 20887U, |
| 10059 | 15192U, 18949U, 26816U, 20865U, 24276U, 1022U, 20535U, 7817U, |
| 10060 | 540U, 17024U, 2589U, 17507U, 24716U, 20315U, 11927U, 293U, |
| 10061 | 16759U, 2285U, 17294U, 3381U, 24352U, 20091U, 7231U, 26211U, |
| 10062 | 12072U, 26316U, 12362U, 26654U, 12517U, 26926U, 11964U, 26248U, |
| 10063 | 12775U, 27253U, 502U, 16974U, 2551U, 1029U, 17205U, 12034U, |
| 10064 | 26278U, 12459U, 26772U, 12386U, 26668U, 11988U, 26262U, 12799U, |
| 10065 | 27267U, 12048U, 26292U, 12322U, 26625U, 13148U, 665U, 17138U, |
| 10066 | 2714U, 17609U, 24881U, 20400U, 7650U, 27595U, 14948U, 26639U, |
| 10067 | 11835U, 26117U, 12271U, 26550U, 12473U, 26786U, 12704U, 27158U, |
| 10068 | 13080U, 27518U, 12280U, 26559U, 12482U, 26795U, 10580U, 12258U, |
| 10069 | 14914U, 26537U, 11827U, 26109U, 2486U, 6453U, 24595U, 7437U, |
| 10070 | 724U, 2767U, 6722U, 20854U, 24930U, 20458U, 7718U, 11934U, |
| 10071 | 26218U, 11889U, 26173U, 13178U, 27617U, 11871U, 26155U, 12315U, |
| 10072 | 26618U, 674U, 17150U, 2723U, 17621U, 6666U, 24888U, 20410U, |
| 10073 | 7662U, 11905U, 26189U, 12301U, 450U, 16937U, 2442U, 17419U, |
| 10074 | 3400U, 24559U, 20241U, 7381U, 26580U, 409U, 16884U, 2401U, |
| 10075 | 17394U, 24520U, 20196U, 7358U, 15840U, 12355U, 26647U, 12852U, |
| 10076 | 27290U, 12877U, 27315U, 12079U, 26323U, 12369U, 26661U, 11971U, |
| 10077 | 26255U, 12782U, 27260U, 12041U, 26285U, 12466U, 26779U, 12869U, |
| 10078 | 615U, 17100U, 2664U, 17583U, 24839U, 20368U, 27307U, 11898U, |
| 10079 | 274U, 16734U, 2266U, 17282U, 3371U, 24337U, 20070U, 7219U, |
| 10080 | 26182U, 12394U, 26676U, 11996U, 26270U, 12807U, 27275U, 12056U, |
| 10081 | 26300U, 12329U, 26632U, 12714U, 27168U, 13090U, 27528U, 14962U, |
| 10082 | 26684U, 12554U, 26963U, 12919U, 27357U, 15681U, 6934U, 25579U, |
| 10083 | 7806U, 12565U, 15087U, 26974U, 12930U, 15345U, 27368U, 12535U, |
| 10084 | 15068U, 26944U, 12900U, 15326U, 27338U, 16159U, 19316U, 11028U, |
| 10085 | 13140U, 15544U, 27587U, 10607U, 12308U, 14941U, 26587U, 10388U, |
| 10086 | 11956U, 14766U, 26240U, 10649U, 12503U, 15052U, 26823U, 24067U, |
| 10087 | 10834U, 12860U, 15303U, 27298U, 26004U, 10396U, 12064U, 14774U, |
| 10088 | 26308U, 20713U, 20020U, 7186U, 15832U, 15873U, 23629U, 17805U, |
| 10089 | 3332U, 5552U, 5790U, 6043U, 17824U, 20027U, 9903U, 2042U, |
| 10090 | 18022U, 19918U, 19990U, 27836U, 21051U, 19132U, 11088U, 2105U, |
| 10091 | 5876U, 11067U, 2099U, 5857U, 23626U, 17797U, 3327U, 23154U, |
| 10092 | 17665U, 5541U, 7089U, 9897U, 2034U, 8047U, 18013U, 8082U, |
| 10093 | 19912U, 19118U, 4869U, 3923U, 4802U, 4794U, 5008U, 4840U, |
| 10094 | 9911U, 2052U, 13214U, 18374U, 17844U, 27841U, 21059U, 7826U, |
| 10095 | 18033U, 5804U, 28952U, 3866U, 13762U, 18520U, 21176U, 11618U, |
| 10096 | 91U, 1966U, 5493U, 459U, 2508U, 1164U, 5411U, 8015U, |
| 10097 | 1931U, 10426U, 12142U, 14804U, 26427U, 15961U, 11228U, 23373U, |
| 10098 | 171U, 1980U, 10375U, 11943U, 14753U, 26227U, 29036U, 3885U, |
| 10099 | 21229U, 14128U, 2846U, 13406U, 18430U, 17873U, 27792U, 21044U, |
| 10100 | 18594U, 28974U, 3872U, 13767U, 18528U, 21199U, 17721U, 5636U, |
| 10101 | 16156U, 3273U, 8066U, 11621U, 8104U, 13450U, 18444U, 19310U, |
| 10102 | 6971U, 8128U, 9842U, 5772U, 8075U, 6925U, 183U, 1996U, |
| 10103 | 16672U, 28118U, 3720U, 21169U, 26080U, 17882U, 3497U, 161U, |
| 10104 | 16656U, 1186U, 5473U, 8031U, 1941U, 23001U, 19536U, 13729U, |
| 10105 | 18506U, 19478U, 16453U, 3289U, 13458U, 18451U, 19359U, 17758U, |
| 10106 | 5681U, 17187U, 11260U, 6023U, 19712U, 23999U, 3359U, 13600U, |
| 10107 | 18481U, 19976U, 19688U, 11254U, 20606U, 27846U, 195U, 16690U, |
| 10108 | 20036U, 21067U, 20721U, 7927U, 29008U, 4278U, 4342U, 4310U, |
| 10109 | 4359U, 4888U, 4629U, 4514U, 4988U, 4645U, 4395U, 4457U, |
| 10110 | 11557U, 12104U, 6385U, 24465U, 7345U, 15004U, 26726U, 25674U, |
| 10111 | 23134U, 19651U, 20563U, 11012U, 13124U, 15528U, 27571U, 303U, |
| 10112 | 16772U, 2295U, 23022U, 19566U, 18359U, 14977U, 26699U, 24360U, |
| 10113 | 20102U, 16055U, 19240U, 23553U, 19848U, 16081U, 19272U, 23579U, |
| 10114 | 19880U, 11856U, 6271U, 24330U, 7207U, 10716U, 12635U, 15157U, |
| 10115 | 27044U, 10908U, 13000U, 15415U, 27438U, 10352U, 11890U, 14730U, |
| 10116 | 26174U, 13179U, 6737U, 24948U, 10795U, 12743U, 15264U, 7746U, |
| 10117 | 27221U, 10987U, 13108U, 15503U, 27546U, 19U, 16570U, 5349U, |
| 10118 | 107U, 2202U, 16632U, 5391U, 1175U, 5431U, 25U, 16578U, |
| 10119 | 5359U, 254U, 16708U, 2211U, 17244U, 5441U, 31U, 16587U, |
| 10120 | 15600U, 17711U, 2862U, 23062U, 19578U, 19011U, 22637U, 17776U, |
| 10121 | 3307U, 23097U, 19602U, 19400U, 23946U, 11843U, 6259U, 24323U, |
| 10122 | 7195U, 10698U, 12617U, 15139U, 27026U, 10890U, 12982U, 15397U, |
| 10123 | 27420U, 10335U, 11872U, 14713U, 26156U, 12316U, 6481U, 24613U, |
| 10124 | 10725U, 12644U, 15166U, 7465U, 27062U, 10917U, 13009U, 15424U, |
| 10125 | 27447U, 11803U, 10243U, 18274U, 25681U, 7855U, 6250U, 10665U, |
| 10126 | 12584U, 15106U, 26993U, 10857U, 12949U, 15364U, 27387U, 17683U, |
| 10127 | 5602U, 19460U, 7067U, 26015U, 371U, 16861U, 2363U, 15730U, |
| 10128 | 2998U, 19078U, 24480U, 20177U, 2240U, 15708U, 2891U, 24301U, |
| 10129 | 418U, 16896U, 2410U, 15756U, 3028U, 19088U, 24527U, 20206U, |
| 10130 | 635U, 17126U, 2684U, 15806U, 3202U, 19098U, 24855U, 20390U, |
| 10131 | 2253U, 15719U, 2904U, 24312U, 429U, 16910U, 2421U, 15765U, |
| 10132 | 3039U, 19108U, 24536U, 20218U, 10294U, 12096U, 6372U, 24457U, |
| 10133 | 7332U, 14994U, 26716U, 25655U, 23124U, 19638U, 20548U, 11004U, |
| 10134 | 13116U, 15520U, 27563U, 284U, 16747U, 2276U, 23013U, 19554U, |
| 10135 | 18290U, 14968U, 26690U, 24345U, 20081U, 59U, 16616U, 5381U, |
| 10136 | 144U, 2231U, 17270U, 16648U, 5401U, 1181U, 5463U, 46U, |
| 10137 | 16607U, 5370U, 264U, 16721U, 2221U, 17257U, 5452U, 38U, |
| 10138 | 16597U, 15632U, 2884U, 23088U, 19590U, 19035U, 22832U, 19486U, |
| 10139 | 22654U, 3314U, 23106U, 19614U, 19417U, 75U, 207U, 1204U, |
| 10140 | 80U, 220U, 1218U, 23975U, 14695U, 25712U, 7865U, 6868U, |
| 10141 | 16348U, 16093U, 19287U, 23591U, 19895U, 15895U, 19159U, 23269U, |
| 10142 | 19748U, 14376U, 18767U, 26895U, 1902U, 14426U, 1559U, 27097U, |
| 10143 | 1917U, 3429U, 15014U, 26736U, 14614U, 18911U, 14554U, 1658U, |
| 10144 | 25297U, 23144U, 19664U, 23115U, 19626U, 20527U, 28990U, 21220U, |
| 10145 | 25732U, 7886U, 11036U, 13155U, 15552U, 27602U, 19352U, 6988U, |
| 10146 | 14294U, 1501U, 14986U, 26708U, 8135U, 14397U, 1545U, 4854U, |
| 10147 | 4981U, 4168U, 3905U, 15877U, 10360U, 11913U, 14738U, 26197U, |
| 10148 | 10367U, 11920U, 14745U, 26204U, 302U, 16771U, 2294U, 24359U, |
| 10149 | 20101U, 283U, 16746U, 2275U, 24344U, 20080U, 23666U, 3339U, |
| 10150 | 10509U, 19926U, 7133U, 26029U, 17835U, 5727U, 5049U, 5090U, |
| 10151 | 23663U, 17816U, 5717U, 3340U, 10510U, 6907U, 19927U, 7134U, |
| 10152 | 26030U, 28097U, 3707U, 21154U, 5189U, 14284U, 18692U, 13623U, |
| 10153 | 18497U, 6799U, 11020U, 13132U, 15536U, 27579U, 10380U, 11948U, |
| 10154 | 14758U, 26232U, 10827U, 12845U, 15296U, 27283U, 14252U, 18659U, |
| 10155 | 9988U, 18068U, 3391U, 3439U, 22909U, 15924U, 8488U, 17936U, |
| 10156 | 19194U, 23298U, 8538U, 17973U, 19783U, 16068U, 19256U, 23566U, |
| 10157 | 19864U, 15910U, 8473U, 17918U, 19177U, 23284U, 8523U, 17955U, |
| 10158 | 19766U, 14196U, 18627U, 26359U, 20781U, 14171U, 18611U, 26388U, |
| 10159 | 20796U, 14184U, 1443U, 26344U, 1804U, 26371U, 1824U, 13811U, |
| 10160 | 13382U, 18405U, 21035U, 18544U, 6810U, 8120U, 11680U, 1418U, |
| 10161 | 3410U, 3448U, 10229U, 18254U, 22975U, 19518U, 23993U, 3351U, |
| 10162 | 19967U, 7175U, 7151U, 492U, 16961U, 2541U, 17456U, 24645U, |
| 10163 | 20272U, 14527U, 18884U, 10211U, 18230U, 14268U, 18681U, 10004U, |
| 10164 | 18090U, 12853U, 6654U, 24832U, 7638U, 23952U, 25998U, 20704U, |
| 10165 | 19940U, 2463U, 6424U, 24576U, 7408U, 701U, 2744U, 6693U, |
| 10166 | 20770U, 24911U, 20433U, 7689U, 625U, 17113U, 2674U, 17596U, |
| 10167 | 24847U, 20379U, 4809U, 4185U, 8469U, 11352U, 10760U, 12688U, |
| 10168 | 15219U, 27142U, 10963U, 13064U, 15479U, 27502U, 10240U, 17657U, |
| 10169 | 5521U, 2057U, 13231U, 18381U, 18268U, 5812U, 11273U, 2120U, |
| 10170 | 8058U, 11466U, 8097U, 13284U, 18388U, 18320U, 6054U, 8091U, |
| 10171 | 11824U, 22790U, 17786U, 5703U, 19433U, 7056U, 8150U, 96U, |
| 10172 | 1973U, 5507U, 471U, 2520U, 1169U, 5421U, 8023U, 1936U, |
| 10173 | 25858U, 20631U, 15965U, 23377U, 177U, 1988U, 9875U, 2012U, |
| 10174 | 17999U, 14118U, 2840U, 18587U, 27959U, 3542U, 13205U, 6762U, |
| 10175 | 7977U, 24963U, 7771U, 27926U, 3533U, 13190U, 6748U, 7956U, |
| 10176 | 24954U, 7757U, 12252U, 6398U, 24545U, 7370U, 23256U, 28091U, |
| 10177 | 14691U, 17693U, 5614U, 2851U, 13410U, 18437U, 10405U, 14783U, |
| 10178 | 26331U, 22642U, 25976U, 20674U, 19408U, 14518U, 18872U, 10202U, |
| 10179 | 18218U, 14466U, 18833U, 27211U, 21011U, 14260U, 18670U, 9996U, |
| 10180 | 18079U, 14387U, 18781U, 27053U, 20952U, 14509U, 18860U, 10193U, |
| 10181 | 1404U, 14365U, 18753U, 10094U, 1355U, 26868U, 20899U, 14163U, |
| 10182 | 18600U, 9914U, 1231U, 14333U, 18740U, 10062U, 1308U, 26830U, |
| 10183 | 20875U, 14536U, 1630U, 10220U, 18242U, 14276U, 1488U, 10012U, |
| 10184 | 18101U, 18943U, 6860U, 13414U, 6787U, 10425U, 12141U, 14803U, |
| 10185 | 26426U, 10374U, 11942U, 14752U, 26226U, 16277U, 17740U, 5659U, |
| 10186 | 1039U, 3602U, 10455U, 12156U, 14818U, 26441U, 25912U, 20647U, |
| 10187 | 10587U, 12265U, 14921U, 19338U, 6979U, 26544U, 25282U, 3480U, |
| 10188 | 20507U, 28101U, 3713U, 21161U, 29064U, 3897U, 21242U, 28978U, |
| 10189 | 3878U, 21206U, 13515U, 28086U, 10532U, 12219U, 14881U, 26504U, |
| 10190 | 10812U, 12760U, 15281U, 27238U, 8555U, 10418U, 12134U, 14796U, |
| 10191 | 26419U, 10485U, 12186U, 14848U, 26471U, 10620U, 12432U, 15023U, |
| 10192 | 26745U, 25813U, 20613U, 10321U, 11850U, 14699U, 17992U, 26141U, |
| 10193 | 16308U, 17749U, 5670U, 10462U, 12163U, 14825U, 26448U, 10501U, |
| 10194 | 12202U, 14864U, 26487U, 10634U, 12452U, 15037U, 26765U, 25918U, |
| 10195 | 20655U, 10593U, 12287U, 14927U, 19345U, 26566U, 22881U, 19496U, |
| 10196 | 7078U, 10843U, 12886U, 15312U, 27324U, 10246U, 14228U, 1460U, |
| 10197 | 14343U, 1513U, 26839U, 1872U, 26403U, 1846U, 14301U, 18705U, |
| 10198 | 14406U, 18794U, 27079U, 20964U, 10952U, 13053U, 15468U, 27491U, |
| 10199 | 10776U, 12724U, 15235U, 27192U, 10742U, 12670U, 15201U, 27124U, |
| 10200 | 10934U, 13035U, 15450U, 27473U, 17853U, 5738U, 9964U, 1262U, |
| 10201 | 10072U, 1323U, 7835U, 14493U, 1604U, 10177U, 18196U, 14446U, |
| 10202 | 1574U, 10115U, 18141U, 10549U, 12236U, 14898U, 26521U, 11005U, |
| 10203 | 13117U, 15521U, 27564U, 18277U, 5820U, 28957U, 21183U, 189U, |
| 10204 | 2004U, 16681U, 26090U, 17890U, 5762U, 3514U, 166U, 16664U, |
| 10205 | 1191U, 5483U, 8039U, 1946U, 23007U, 19545U, 13733U, 18513U, |
| 10206 | 16457U, 3295U, 13463U, 18459U, 19366U, 17767U, 5692U, 17196U, |
| 10207 | 19719U, 24003U, 3365U, 13605U, 18489U, 19983U, 19696U, 7105U, |
| 10208 | 201U, 16699U, 20727U, 7935U, 11206U, 15570U, 18974U, 6877U, |
| 10209 | 18298U, 5977U, 16167U, 19327U, 4833U, 4196U, 4294U, 5000U, |
| 10210 | 5016U, 4326U, 4264U, 5155U, 5069U, 4910U, 4538U, 4922U, |
| 10211 | 4565U, 5100U, 4178U, 5134U, 4271U, 5166U, 5225U, 4411U, |
| 10212 | 4470U, 23260U, 15643U, 19043U, 19733U, 13396U, 15579U, 25717U, |
| 10213 | 20580U, 18989U, 25696U, 20572U, 18414U, 25968U, 13838U, 18552U, |
| 10214 | 20663U, 22826U, 19469U, 23513U, 19839U, 15693U, 19068U, 23986U, |
| 10215 | 19957U, 25961U, 13830U, 6820U, 7915U, 22796U, 19442U, 23264U, |
| 10216 | 19740U, 15687U, 19059U, 23980U, 19948U, 25286U, 15662U, 20589U, |
| 10217 | 19051U, 25765U, 20598U, 20514U, 13519U, 15584U, 18997U, 18474U, |
| 10218 | 2451U, 6409U, 24566U, 7393U, 689U, 2732U, 6678U, 20759U, |
| 10219 | 24901U, 20420U, 7674U, 25723U, 25888U, 20639U, 25730U, 70U, |
| 10220 | 25743U, 10404U, 12112U, 14782U, 26330U, 25201U, 20499U, 7796U, |
| 10221 | 22981U, 19527U, 7163U, 14094U, 18579U, 6850U, 23820U, 17815U, |
| 10222 | 5716U, 3345U, 10516U, 6906U, 19933U, 7142U, 26035U, 28096U, |
| 10223 | 3706U, 21153U, 5200U, 11615U, |
| 10224 | }; |
| 10225 | |
| 10226 | extern const int16_t MipsRegClassByHwModeTables[2][4] = { |
| 10227 | { // DefaultMode |
| 10228 | Mips::GPR32RegClassID, // mips_ptr_rc |
| 10229 | Mips::GP32RegClassID, // ptr_gp_rc |
| 10230 | Mips::GPRMM16RegClassID, // ptr_gpr16mm_rc |
| 10231 | Mips::SP32RegClassID, // ptr_sp_rc |
| 10232 | }, |
| 10233 | { // MIPS64 |
| 10234 | Mips::GPR64RegClassID, // mips_ptr_rc |
| 10235 | Mips::GP64RegClassID, // ptr_gp_rc |
| 10236 | Mips::GPRMM16RegClassID, // ptr_gpr16mm_rc |
| 10237 | Mips::SP64RegClassID, // ptr_sp_rc |
| 10238 | }, |
| 10239 | }; |
| 10240 | |
| 10241 | static inline void InitMipsMCInstrInfo(MCInstrInfo *II) { |
| 10242 | II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2932, &MipsRegClassByHwModeTables[0][0], 4); |
| 10243 | } |
| 10244 | |
| 10245 | |
| 10246 | } // namespace llvm |
| 10247 | |
| 10248 | #endif // GET_INSTRINFO_MC_DESC |
| 10249 | |
| 10250 | #ifdef GET_INSTRINFO_HEADER |
| 10251 | #undef GET_INSTRINFO_HEADER |
| 10252 | |
| 10253 | namespace llvm { |
| 10254 | |
| 10255 | struct MipsGenInstrInfo : public TargetInstrInfo { |
| 10256 | explicit MipsGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| 10257 | ~MipsGenInstrInfo() override = default; |
| 10258 | }; |
| 10259 | extern const int16_t MipsRegClassByHwModeTables[2][4]; |
| 10260 | |
| 10261 | } // namespace llvm |
| 10262 | |
| 10263 | namespace llvm::Mips { |
| 10264 | |
| 10265 | constexpr unsigned SUBOP_mem_mm_gp_simm7_lsl2_base = 0; |
| 10266 | constexpr unsigned SUBOP_mem_mm_gp_simm7_lsl2_offset = 1; |
| 10267 | constexpr unsigned SUBOP_mem_mm_sp_imm5_lsl2_base = 0; |
| 10268 | constexpr unsigned SUBOP_mem_mm_sp_imm5_lsl2_offset = 1; |
| 10269 | |
| 10270 | } // namespace llvm::Mips |
| 10271 | |
| 10272 | #endif // GET_INSTRINFO_HEADER |
| 10273 | |
| 10274 | #ifdef GET_INSTRINFO_HELPER_DECLS |
| 10275 | #undef GET_INSTRINFO_HELPER_DECLS |
| 10276 | |
| 10277 | |
| 10278 | #endif // GET_INSTRINFO_HELPER_DECLS |
| 10279 | |
| 10280 | #ifdef GET_INSTRINFO_HELPERS |
| 10281 | #undef GET_INSTRINFO_HELPERS |
| 10282 | |
| 10283 | |
| 10284 | #endif // GET_INSTRINFO_HELPERS |
| 10285 | |
| 10286 | #ifdef GET_INSTRINFO_CTOR_DTOR |
| 10287 | #undef GET_INSTRINFO_CTOR_DTOR |
| 10288 | |
| 10289 | namespace llvm { |
| 10290 | |
| 10291 | extern const MipsInstrTable MipsDescs; |
| 10292 | extern const unsigned MipsInstrNameIndices[]; |
| 10293 | extern const char MipsInstrNameData[]; |
| 10294 | MipsGenInstrInfo::MipsGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| 10295 | : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, MipsRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) { |
| 10296 | InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2932, &MipsRegClassByHwModeTables[0][0], 4); |
| 10297 | } |
| 10298 | |
| 10299 | } // namespace llvm |
| 10300 | |
| 10301 | #endif // GET_INSTRINFO_CTOR_DTOR |
| 10302 | |
| 10303 | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| 10304 | #undef GET_INSTRINFO_MC_HELPER_DECLS |
| 10305 | |
| 10306 | namespace llvm { |
| 10307 | |
| 10308 | class MCInst; |
| 10309 | class FeatureBitset; |
| 10310 | |
| 10311 | extern const int16_t MipsRegClassByHwModeTables[2][4]; |
| 10312 | |
| 10313 | namespace Mips_MC { |
| 10314 | |
| 10315 | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| 10316 | |
| 10317 | } // namespace Mips_MC |
| 10318 | |
| 10319 | } // namespace llvm |
| 10320 | |
| 10321 | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| 10322 | |
| 10323 | #ifdef GET_INSTRINFO_MC_HELPERS |
| 10324 | #undef GET_INSTRINFO_MC_HELPERS |
| 10325 | |
| 10326 | namespace llvm::Mips_MC { |
| 10327 | |
| 10328 | |
| 10329 | } // namespace llvm::Mips_MC |
| 10330 | |
| 10331 | #endif // GET_INSTRINFO_MC_HELPERS |
| 10332 | |
| 10333 | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
| 10334 | defined(GET_AVAILABLE_OPCODE_CHECKER) |
| 10335 | #define GET_COMPUTE_FEATURES |
| 10336 | #endif |
| 10337 | #ifdef GET_COMPUTE_FEATURES |
| 10338 | #undef GET_COMPUTE_FEATURES |
| 10339 | |
| 10340 | namespace llvm::Mips_MC { |
| 10341 | |
| 10342 | // Bits for subtarget features that participate in instruction matching. |
| 10343 | enum SubtargetFeatureBits : uint8_t { |
| 10344 | Feature_IsPTR64bitBit = 37, |
| 10345 | Feature_IsPTR32bitBit = 36, |
| 10346 | Feature_UseCompactBranchesBit = 54, |
| 10347 | Feature_HasMips2Bit = 11, |
| 10348 | Feature_HasMips3_32Bit = 14, |
| 10349 | Feature_HasMips3_32r2Bit = 15, |
| 10350 | Feature_HasMips3Bit = 12, |
| 10351 | Feature_NotMips3Bit = 48, |
| 10352 | Feature_HasMips4_32Bit = 16, |
| 10353 | Feature_NotMips4_32Bit = 49, |
| 10354 | Feature_HasMips4_32r2Bit = 17, |
| 10355 | Feature_HasMips5_32r2Bit = 18, |
| 10356 | Feature_HasMips32Bit = 19, |
| 10357 | Feature_HasMips32r2Bit = 20, |
| 10358 | Feature_HasMips32r5Bit = 21, |
| 10359 | Feature_HasMips32r6Bit = 22, |
| 10360 | Feature_NotMips32r6Bit = 50, |
| 10361 | Feature_IsGP64bitBit = 33, |
| 10362 | Feature_IsGP32bitBit = 32, |
| 10363 | Feature_HasMips64Bit = 23, |
| 10364 | Feature_NotMips64Bit = 51, |
| 10365 | Feature_HasMips64r2Bit = 24, |
| 10366 | Feature_HasMips64r5Bit = 25, |
| 10367 | Feature_HasMips64r6Bit = 26, |
| 10368 | Feature_NotMips64r6Bit = 52, |
| 10369 | Feature_InMips16ModeBit = 30, |
| 10370 | Feature_NotInMips16ModeBit = 47, |
| 10371 | Feature_HasCnMipsBit = 1, |
| 10372 | Feature_NotCnMipsBit = 43, |
| 10373 | Feature_HasCnMipsPBit = 2, |
| 10374 | Feature_NotCnMipsPBit = 44, |
| 10375 | Feature_IsSym32Bit = 40, |
| 10376 | Feature_IsSym64Bit = 41, |
| 10377 | Feature_HasStdEncBit = 27, |
| 10378 | Feature_InMicroMipsBit = 29, |
| 10379 | Feature_NotInMicroMipsBit = 46, |
| 10380 | Feature_HasEVABit = 6, |
| 10381 | Feature_HasMSABit = 8, |
| 10382 | Feature_HasMadd4Bit = 10, |
| 10383 | Feature_HasMTBit = 9, |
| 10384 | Feature_UseIndirectJumpsHazardBit = 55, |
| 10385 | Feature_NoIndirectJumpGuardsBit = 42, |
| 10386 | Feature_IsR5900Bit = 38, |
| 10387 | Feature_NotR5900Bit = 53, |
| 10388 | Feature_HasCRCBit = 0, |
| 10389 | Feature_HasVirtBit = 28, |
| 10390 | Feature_HasGINVBit = 7, |
| 10391 | Feature_IsFP64bitBit = 31, |
| 10392 | Feature_NotFP64bitBit = 45, |
| 10393 | Feature_IsSingleFloatBit = 39, |
| 10394 | Feature_IsNotSingleFloatBit = 34, |
| 10395 | Feature_IsNotSoftFloatBit = 35, |
| 10396 | Feature_HasMips3DBit = 13, |
| 10397 | Feature_HasDSPBit = 3, |
| 10398 | Feature_HasDSPR2Bit = 4, |
| 10399 | Feature_HasDSPR3Bit = 5, |
| 10400 | }; |
| 10401 | |
| 10402 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| 10403 | FeatureBitset Features; |
| 10404 | if (FB[Mips::FeaturePTR64Bit]) |
| 10405 | Features.set(Feature_IsPTR64bitBit); |
| 10406 | if (!(FB[Mips::FeaturePTR64Bit])) |
| 10407 | Features.set(Feature_IsPTR32bitBit); |
| 10408 | if (FB[Mips::FeatureUseCompactBranches]) |
| 10409 | Features.set(Feature_UseCompactBranchesBit); |
| 10410 | if (FB[Mips::FeatureMips2]) |
| 10411 | Features.set(Feature_HasMips2Bit); |
| 10412 | if (FB[Mips::FeatureMips3_32]) |
| 10413 | Features.set(Feature_HasMips3_32Bit); |
| 10414 | if (FB[Mips::FeatureMips3_32r2]) |
| 10415 | Features.set(Feature_HasMips3_32r2Bit); |
| 10416 | if (FB[Mips::FeatureMips3]) |
| 10417 | Features.set(Feature_HasMips3Bit); |
| 10418 | if (!(FB[Mips::FeatureMips3])) |
| 10419 | Features.set(Feature_NotMips3Bit); |
| 10420 | if (FB[Mips::FeatureMips4_32]) |
| 10421 | Features.set(Feature_HasMips4_32Bit); |
| 10422 | if (!(FB[Mips::FeatureMips4_32])) |
| 10423 | Features.set(Feature_NotMips4_32Bit); |
| 10424 | if (FB[Mips::FeatureMips4_32r2]) |
| 10425 | Features.set(Feature_HasMips4_32r2Bit); |
| 10426 | if (FB[Mips::FeatureMips5_32r2]) |
| 10427 | Features.set(Feature_HasMips5_32r2Bit); |
| 10428 | if (FB[Mips::FeatureMips32]) |
| 10429 | Features.set(Feature_HasMips32Bit); |
| 10430 | if (FB[Mips::FeatureMips32r2]) |
| 10431 | Features.set(Feature_HasMips32r2Bit); |
| 10432 | if (FB[Mips::FeatureMips32r5]) |
| 10433 | Features.set(Feature_HasMips32r5Bit); |
| 10434 | if (FB[Mips::FeatureMips32r6]) |
| 10435 | Features.set(Feature_HasMips32r6Bit); |
| 10436 | if (!(FB[Mips::FeatureMips32r6])) |
| 10437 | Features.set(Feature_NotMips32r6Bit); |
| 10438 | if (FB[Mips::FeatureGP64Bit]) |
| 10439 | Features.set(Feature_IsGP64bitBit); |
| 10440 | if (!(FB[Mips::FeatureGP64Bit])) |
| 10441 | Features.set(Feature_IsGP32bitBit); |
| 10442 | if (FB[Mips::FeatureMips64]) |
| 10443 | Features.set(Feature_HasMips64Bit); |
| 10444 | if (!(FB[Mips::FeatureMips64])) |
| 10445 | Features.set(Feature_NotMips64Bit); |
| 10446 | if (FB[Mips::FeatureMips64r2]) |
| 10447 | Features.set(Feature_HasMips64r2Bit); |
| 10448 | if (FB[Mips::FeatureMips64r5]) |
| 10449 | Features.set(Feature_HasMips64r5Bit); |
| 10450 | if (FB[Mips::FeatureMips64r6]) |
| 10451 | Features.set(Feature_HasMips64r6Bit); |
| 10452 | if (!(FB[Mips::FeatureMips64r6])) |
| 10453 | Features.set(Feature_NotMips64r6Bit); |
| 10454 | if (FB[Mips::FeatureMips16]) |
| 10455 | Features.set(Feature_InMips16ModeBit); |
| 10456 | if (!(FB[Mips::FeatureMips16])) |
| 10457 | Features.set(Feature_NotInMips16ModeBit); |
| 10458 | if (FB[Mips::FeatureCnMips]) |
| 10459 | Features.set(Feature_HasCnMipsBit); |
| 10460 | if (!(FB[Mips::FeatureCnMips])) |
| 10461 | Features.set(Feature_NotCnMipsBit); |
| 10462 | if (FB[Mips::FeatureCnMipsP]) |
| 10463 | Features.set(Feature_HasCnMipsPBit); |
| 10464 | if (!(FB[Mips::FeatureCnMipsP])) |
| 10465 | Features.set(Feature_NotCnMipsPBit); |
| 10466 | if (FB[Mips::FeatureSym32]) |
| 10467 | Features.set(Feature_IsSym32Bit); |
| 10468 | if (!(FB[Mips::FeatureSym32])) |
| 10469 | Features.set(Feature_IsSym64Bit); |
| 10470 | if (!(FB[Mips::FeatureMips16])) |
| 10471 | Features.set(Feature_HasStdEncBit); |
| 10472 | if (FB[Mips::FeatureMicroMips]) |
| 10473 | Features.set(Feature_InMicroMipsBit); |
| 10474 | if (!(FB[Mips::FeatureMicroMips])) |
| 10475 | Features.set(Feature_NotInMicroMipsBit); |
| 10476 | if (FB[Mips::FeatureEVA]) |
| 10477 | Features.set(Feature_HasEVABit); |
| 10478 | if (FB[Mips::FeatureMSA]) |
| 10479 | Features.set(Feature_HasMSABit); |
| 10480 | if (!(FB[Mips::FeatureNoMadd4])) |
| 10481 | Features.set(Feature_HasMadd4Bit); |
| 10482 | if (FB[Mips::FeatureMT]) |
| 10483 | Features.set(Feature_HasMTBit); |
| 10484 | if (FB[Mips::FeatureUseIndirectJumpsHazard]) |
| 10485 | Features.set(Feature_UseIndirectJumpsHazardBit); |
| 10486 | if (!(FB[Mips::FeatureUseIndirectJumpsHazard])) |
| 10487 | Features.set(Feature_NoIndirectJumpGuardsBit); |
| 10488 | if (FB[Mips::FeatureR5900]) |
| 10489 | Features.set(Feature_IsR5900Bit); |
| 10490 | if (!(FB[Mips::FeatureR5900])) |
| 10491 | Features.set(Feature_NotR5900Bit); |
| 10492 | if (FB[Mips::FeatureCRC]) |
| 10493 | Features.set(Feature_HasCRCBit); |
| 10494 | if (FB[Mips::FeatureVirt]) |
| 10495 | Features.set(Feature_HasVirtBit); |
| 10496 | if (FB[Mips::FeatureGINV]) |
| 10497 | Features.set(Feature_HasGINVBit); |
| 10498 | if (FB[Mips::FeatureFP64Bit]) |
| 10499 | Features.set(Feature_IsFP64bitBit); |
| 10500 | if (!(FB[Mips::FeatureFP64Bit])) |
| 10501 | Features.set(Feature_NotFP64bitBit); |
| 10502 | if (FB[Mips::FeatureSingleFloat]) |
| 10503 | Features.set(Feature_IsSingleFloatBit); |
| 10504 | if (!(FB[Mips::FeatureSingleFloat])) |
| 10505 | Features.set(Feature_IsNotSingleFloatBit); |
| 10506 | if (!(FB[Mips::FeatureSoftFloat])) |
| 10507 | Features.set(Feature_IsNotSoftFloatBit); |
| 10508 | if (FB[Mips::FeatureMips3D]) |
| 10509 | Features.set(Feature_HasMips3DBit); |
| 10510 | if (FB[Mips::FeatureDSP]) |
| 10511 | Features.set(Feature_HasDSPBit); |
| 10512 | if (FB[Mips::FeatureDSPR2]) |
| 10513 | Features.set(Feature_HasDSPR2Bit); |
| 10514 | if (FB[Mips::FeatureDSPR3]) |
| 10515 | Features.set(Feature_HasDSPR3Bit); |
| 10516 | return Features; |
| 10517 | } |
| 10518 | |
| 10519 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
| 10520 | enum : uint8_t { |
| 10521 | CEFBS_None, |
| 10522 | CEFBS_HasCnMips, |
| 10523 | CEFBS_HasCnMipsP, |
| 10524 | CEFBS_HasDSP, |
| 10525 | CEFBS_HasDSPR2, |
| 10526 | CEFBS_HasMT, |
| 10527 | CEFBS_InMicroMips, |
| 10528 | CEFBS_InMips16Mode, |
| 10529 | CEFBS_IsGP32bit, |
| 10530 | CEFBS_IsGP64bit, |
| 10531 | CEFBS_IsNotSingleFloat, |
| 10532 | CEFBS_IsNotSoftFloat, |
| 10533 | CEFBS_NotCnMips, |
| 10534 | CEFBS_NotInMips16Mode, |
| 10535 | CEFBS_NotR5900, |
| 10536 | CEFBS_HasDSP_NotInMicroMips, |
| 10537 | CEFBS_HasStdEnc_HasMSA, |
| 10538 | CEFBS_HasStdEnc_HasMips32, |
| 10539 | CEFBS_HasStdEnc_HasMips32r6, |
| 10540 | CEFBS_HasStdEnc_HasMips64, |
| 10541 | CEFBS_HasStdEnc_HasMips64r6, |
| 10542 | CEFBS_HasStdEnc_IsNotSoftFloat, |
| 10543 | CEFBS_HasStdEnc_NotInMicroMips, |
| 10544 | CEFBS_HasStdEnc_NotMips3, |
| 10545 | CEFBS_HasStdEnc_NotMips4_32, |
| 10546 | CEFBS_InMicroMips_HasDSP, |
| 10547 | CEFBS_InMicroMips_HasDSPR2, |
| 10548 | CEFBS_InMicroMips_HasDSPR3, |
| 10549 | CEFBS_InMicroMips_HasEVA, |
| 10550 | CEFBS_InMicroMips_HasMips32r6, |
| 10551 | CEFBS_InMicroMips_IsNotSoftFloat, |
| 10552 | CEFBS_InMicroMips_NotMips32r6, |
| 10553 | CEFBS_IsGP32bit_NotInMicroMips, |
| 10554 | CEFBS_NotInMips16Mode_HasDSP, |
| 10555 | CEFBS_NotInMips16Mode_IsGP64bit, |
| 10556 | CEFBS_NotInMips16Mode_IsNotSoftFloat, |
| 10557 | CEFBS_NotInMips16Mode_IsPTR64bit, |
| 10558 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, |
| 10559 | CEFBS_HasStdEnc_HasMSA_HasMips64, |
| 10560 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, |
| 10561 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, |
| 10562 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, |
| 10563 | CEFBS_HasStdEnc_HasMips32_NotInMicroMips, |
| 10564 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, |
| 10565 | CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, |
| 10566 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, |
| 10567 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, |
| 10568 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, |
| 10569 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, |
| 10570 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, |
| 10571 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, |
| 10572 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, |
| 10573 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, |
| 10574 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, |
| 10575 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 10576 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, |
| 10577 | CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, |
| 10578 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, |
| 10579 | CEFBS_InMicroMips_HasMips32r5_HasVirt, |
| 10580 | CEFBS_InMicroMips_HasMips32r6_HasGINV, |
| 10581 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, |
| 10582 | CEFBS_InMicroMips_NotMips32r6_HasDSP, |
| 10583 | CEFBS_InMicroMips_NotMips32r6_HasEVA, |
| 10584 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, |
| 10585 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, |
| 10586 | CEFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, |
| 10587 | CEFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, |
| 10588 | CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, |
| 10589 | CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, |
| 10590 | CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, |
| 10591 | CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, |
| 10592 | CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 10593 | CEFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900, |
| 10594 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 10595 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, |
| 10596 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat, |
| 10597 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, |
| 10598 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, |
| 10599 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, |
| 10600 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, |
| 10601 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, |
| 10602 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, |
| 10603 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, |
| 10604 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, |
| 10605 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
| 10606 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 10607 | CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, |
| 10608 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, |
| 10609 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32, |
| 10610 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, |
| 10611 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, |
| 10612 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, |
| 10613 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, |
| 10614 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips4_32, |
| 10615 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 10616 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, |
| 10617 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, |
| 10618 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, |
| 10619 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, |
| 10620 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, |
| 10621 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 10622 | CEFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, |
| 10623 | CEFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, |
| 10624 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, |
| 10625 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 10626 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 10627 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 10628 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 10629 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 10630 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| 10631 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 10632 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 10633 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, |
| 10634 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, |
| 10635 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, |
| 10636 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10637 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, |
| 10638 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, |
| 10639 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, |
| 10640 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10641 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, |
| 10642 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, |
| 10643 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10644 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 10645 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
| 10646 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, |
| 10647 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
| 10648 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 10649 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| 10650 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 10651 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 10652 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
| 10653 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 10654 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 10655 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, |
| 10656 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, |
| 10657 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, |
| 10658 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 10659 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 10660 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 10661 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 10662 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 10663 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| 10664 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10665 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10666 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, |
| 10667 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, |
| 10668 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10669 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, |
| 10670 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10671 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10672 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10673 | CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 10674 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 10675 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10676 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10677 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10678 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 10679 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 10680 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 10681 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 10682 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 10683 | }; |
| 10684 | |
| 10685 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 10686 | {}, // CEFBS_None |
| 10687 | {Feature_HasCnMipsBit, }, |
| 10688 | {Feature_HasCnMipsPBit, }, |
| 10689 | {Feature_HasDSPBit, }, |
| 10690 | {Feature_HasDSPR2Bit, }, |
| 10691 | {Feature_HasMTBit, }, |
| 10692 | {Feature_InMicroMipsBit, }, |
| 10693 | {Feature_InMips16ModeBit, }, |
| 10694 | {Feature_IsGP32bitBit, }, |
| 10695 | {Feature_IsGP64bitBit, }, |
| 10696 | {Feature_IsNotSingleFloatBit, }, |
| 10697 | {Feature_IsNotSoftFloatBit, }, |
| 10698 | {Feature_NotCnMipsBit, }, |
| 10699 | {Feature_NotInMips16ModeBit, }, |
| 10700 | {Feature_NotR5900Bit, }, |
| 10701 | {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, |
| 10702 | {Feature_HasStdEncBit, Feature_HasMSABit, }, |
| 10703 | {Feature_HasStdEncBit, Feature_HasMips32Bit, }, |
| 10704 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, |
| 10705 | {Feature_HasStdEncBit, Feature_HasMips64Bit, }, |
| 10706 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, |
| 10707 | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, |
| 10708 | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 10709 | {Feature_HasStdEncBit, Feature_NotMips3Bit, }, |
| 10710 | {Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, |
| 10711 | {Feature_InMicroMipsBit, Feature_HasDSPBit, }, |
| 10712 | {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, |
| 10713 | {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, |
| 10714 | {Feature_InMicroMipsBit, Feature_HasEVABit, }, |
| 10715 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, |
| 10716 | {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
| 10717 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, |
| 10718 | {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, |
| 10719 | {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, |
| 10720 | {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, }, |
| 10721 | {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, }, |
| 10722 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, |
| 10723 | {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 10724 | {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, |
| 10725 | {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, |
| 10726 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, |
| 10727 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, |
| 10728 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, |
| 10729 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, |
| 10730 | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, |
| 10731 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 10732 | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, |
| 10733 | {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, |
| 10734 | {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, |
| 10735 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10736 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, |
| 10737 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, }, |
| 10738 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, |
| 10739 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, |
| 10740 | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10741 | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 10742 | {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, }, |
| 10743 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 10744 | {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, |
| 10745 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, |
| 10746 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 10747 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, |
| 10748 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, |
| 10749 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 10750 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 10751 | {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, |
| 10752 | {Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, |
| 10753 | {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
| 10754 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, }, |
| 10755 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, |
| 10756 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, }, |
| 10757 | {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 10758 | {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotR5900Bit, }, |
| 10759 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10760 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 10761 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_IsNotSingleFloatBit, }, |
| 10762 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 10763 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 10764 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
| 10765 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 10766 | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, |
| 10767 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
| 10768 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, |
| 10769 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10770 | {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10771 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10772 | {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10773 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
| 10774 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips4_32Bit, }, |
| 10775 | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 10776 | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 10777 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10778 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, |
| 10779 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips4_32Bit, }, |
| 10780 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10781 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, |
| 10782 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, |
| 10783 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
| 10784 | {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, |
| 10785 | {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, |
| 10786 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10787 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotR5900Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10788 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotR5900Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 10789 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, }, |
| 10790 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10791 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 10792 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 10793 | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10794 | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10795 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| 10796 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 10797 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 10798 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10799 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10800 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10801 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10802 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 10803 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 10804 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 10805 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10806 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, |
| 10807 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
| 10808 | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10809 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10810 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10811 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10812 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10813 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10814 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| 10815 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 10816 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10817 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10818 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10819 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 10820 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10821 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 10822 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
| 10823 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 10824 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 10825 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 10826 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 10827 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 10828 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| 10829 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10830 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10831 | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, |
| 10832 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, |
| 10833 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10834 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, |
| 10835 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10836 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10837 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10838 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 10839 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 10840 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10841 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10842 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10843 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 10844 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 10845 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 10846 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 10847 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 10848 | }; |
| 10849 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
| 10850 | CEFBS_None, // PHI |
| 10851 | CEFBS_None, // INLINEASM |
| 10852 | CEFBS_None, // INLINEASM_BR |
| 10853 | CEFBS_None, // CFI_INSTRUCTION |
| 10854 | CEFBS_None, // EH_LABEL |
| 10855 | CEFBS_None, // GC_LABEL |
| 10856 | CEFBS_None, // ANNOTATION_LABEL |
| 10857 | CEFBS_None, // KILL |
| 10858 | CEFBS_None, // EXTRACT_SUBREG |
| 10859 | CEFBS_None, // INSERT_SUBREG |
| 10860 | CEFBS_None, // IMPLICIT_DEF |
| 10861 | CEFBS_None, // INIT_UNDEF |
| 10862 | CEFBS_None, // SUBREG_TO_REG |
| 10863 | CEFBS_None, // COPY_TO_REGCLASS |
| 10864 | CEFBS_None, // DBG_VALUE |
| 10865 | CEFBS_None, // DBG_VALUE_LIST |
| 10866 | CEFBS_None, // DBG_INSTR_REF |
| 10867 | CEFBS_None, // DBG_PHI |
| 10868 | CEFBS_None, // DBG_LABEL |
| 10869 | CEFBS_None, // REG_SEQUENCE |
| 10870 | CEFBS_None, // COPY |
| 10871 | CEFBS_None, // COPY_LANEMASK |
| 10872 | CEFBS_None, // BUNDLE |
| 10873 | CEFBS_None, // LIFETIME_START |
| 10874 | CEFBS_None, // LIFETIME_END |
| 10875 | CEFBS_None, // PSEUDO_PROBE |
| 10876 | CEFBS_None, // ARITH_FENCE |
| 10877 | CEFBS_None, // STACKMAP |
| 10878 | CEFBS_None, // FENTRY_CALL |
| 10879 | CEFBS_None, // PATCHPOINT |
| 10880 | CEFBS_None, // LOAD_STACK_GUARD |
| 10881 | CEFBS_None, // PREALLOCATED_SETUP |
| 10882 | CEFBS_None, // PREALLOCATED_ARG |
| 10883 | CEFBS_None, // STATEPOINT |
| 10884 | CEFBS_None, // LOCAL_ESCAPE |
| 10885 | CEFBS_None, // FAULTING_OP |
| 10886 | CEFBS_None, // PATCHABLE_OP |
| 10887 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER |
| 10888 | CEFBS_None, // PATCHABLE_RET |
| 10889 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT |
| 10890 | CEFBS_None, // PATCHABLE_TAIL_CALL |
| 10891 | CEFBS_None, // PATCHABLE_EVENT_CALL |
| 10892 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL |
| 10893 | CEFBS_None, // ICALL_BRANCH_FUNNEL |
| 10894 | CEFBS_None, // FAKE_USE |
| 10895 | CEFBS_None, // MEMBARRIER |
| 10896 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO |
| 10897 | CEFBS_None, // RELOC_NONE |
| 10898 | CEFBS_None, // CONVERGENCECTRL_ENTRY |
| 10899 | CEFBS_None, // CONVERGENCECTRL_ANCHOR |
| 10900 | CEFBS_None, // CONVERGENCECTRL_LOOP |
| 10901 | CEFBS_None, // CONVERGENCECTRL_GLUE |
| 10902 | CEFBS_None, // G_ASSERT_SEXT |
| 10903 | CEFBS_None, // G_ASSERT_ZEXT |
| 10904 | CEFBS_None, // G_ASSERT_ALIGN |
| 10905 | CEFBS_None, // G_ADD |
| 10906 | CEFBS_None, // G_SUB |
| 10907 | CEFBS_None, // G_MUL |
| 10908 | CEFBS_None, // G_SDIV |
| 10909 | CEFBS_None, // G_UDIV |
| 10910 | CEFBS_None, // G_SREM |
| 10911 | CEFBS_None, // G_UREM |
| 10912 | CEFBS_None, // G_SDIVREM |
| 10913 | CEFBS_None, // G_UDIVREM |
| 10914 | CEFBS_None, // G_AND |
| 10915 | CEFBS_None, // G_OR |
| 10916 | CEFBS_None, // G_XOR |
| 10917 | CEFBS_None, // G_ABDS |
| 10918 | CEFBS_None, // G_ABDU |
| 10919 | CEFBS_None, // G_UAVGFLOOR |
| 10920 | CEFBS_None, // G_UAVGCEIL |
| 10921 | CEFBS_None, // G_SAVGFLOOR |
| 10922 | CEFBS_None, // G_SAVGCEIL |
| 10923 | CEFBS_None, // G_IMPLICIT_DEF |
| 10924 | CEFBS_None, // G_PHI |
| 10925 | CEFBS_None, // G_FRAME_INDEX |
| 10926 | CEFBS_None, // G_GLOBAL_VALUE |
| 10927 | CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE |
| 10928 | CEFBS_None, // G_CONSTANT_POOL |
| 10929 | CEFBS_None, // G_EXTRACT |
| 10930 | CEFBS_None, // G_UNMERGE_VALUES |
| 10931 | CEFBS_None, // G_INSERT |
| 10932 | CEFBS_None, // G_MERGE_VALUES |
| 10933 | CEFBS_None, // G_BUILD_VECTOR |
| 10934 | CEFBS_None, // G_BUILD_VECTOR_TRUNC |
| 10935 | CEFBS_None, // G_CONCAT_VECTORS |
| 10936 | CEFBS_None, // G_PTRTOINT |
| 10937 | CEFBS_None, // G_INTTOPTR |
| 10938 | CEFBS_None, // G_BITCAST |
| 10939 | CEFBS_None, // G_FREEZE |
| 10940 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER |
| 10941 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND |
| 10942 | CEFBS_None, // G_INTRINSIC_TRUNC |
| 10943 | CEFBS_None, // G_INTRINSIC_ROUND |
| 10944 | CEFBS_None, // G_INTRINSIC_LRINT |
| 10945 | CEFBS_None, // G_INTRINSIC_LLRINT |
| 10946 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN |
| 10947 | CEFBS_None, // G_READCYCLECOUNTER |
| 10948 | CEFBS_None, // G_READSTEADYCOUNTER |
| 10949 | CEFBS_None, // G_LOAD |
| 10950 | CEFBS_None, // G_SEXTLOAD |
| 10951 | CEFBS_None, // G_ZEXTLOAD |
| 10952 | CEFBS_None, // G_FPEXTLOAD |
| 10953 | CEFBS_None, // G_INDEXED_LOAD |
| 10954 | CEFBS_None, // G_INDEXED_SEXTLOAD |
| 10955 | CEFBS_None, // G_INDEXED_ZEXTLOAD |
| 10956 | CEFBS_None, // G_STORE |
| 10957 | CEFBS_None, // G_FPTRUNCSTORE |
| 10958 | CEFBS_None, // G_INDEXED_STORE |
| 10959 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 10960 | CEFBS_None, // G_ATOMIC_CMPXCHG |
| 10961 | CEFBS_None, // G_ATOMICRMW_XCHG |
| 10962 | CEFBS_None, // G_ATOMICRMW_ADD |
| 10963 | CEFBS_None, // G_ATOMICRMW_SUB |
| 10964 | CEFBS_None, // G_ATOMICRMW_AND |
| 10965 | CEFBS_None, // G_ATOMICRMW_NAND |
| 10966 | CEFBS_None, // G_ATOMICRMW_OR |
| 10967 | CEFBS_None, // G_ATOMICRMW_XOR |
| 10968 | CEFBS_None, // G_ATOMICRMW_MAX |
| 10969 | CEFBS_None, // G_ATOMICRMW_MIN |
| 10970 | CEFBS_None, // G_ATOMICRMW_UMAX |
| 10971 | CEFBS_None, // G_ATOMICRMW_UMIN |
| 10972 | CEFBS_None, // G_ATOMICRMW_FADD |
| 10973 | CEFBS_None, // G_ATOMICRMW_FSUB |
| 10974 | CEFBS_None, // G_ATOMICRMW_FMAX |
| 10975 | CEFBS_None, // G_ATOMICRMW_FMIN |
| 10976 | CEFBS_None, // G_ATOMICRMW_FMAXIMUM |
| 10977 | CEFBS_None, // G_ATOMICRMW_FMINIMUM |
| 10978 | CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM |
| 10979 | CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM |
| 10980 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP |
| 10981 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP |
| 10982 | CEFBS_None, // G_ATOMICRMW_USUB_COND |
| 10983 | CEFBS_None, // G_ATOMICRMW_USUB_SAT |
| 10984 | CEFBS_None, // G_FENCE |
| 10985 | CEFBS_None, // G_PREFETCH |
| 10986 | CEFBS_None, // G_BRCOND |
| 10987 | CEFBS_None, // G_BRINDIRECT |
| 10988 | CEFBS_None, // G_INVOKE_REGION_START |
| 10989 | CEFBS_None, // G_INTRINSIC |
| 10990 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS |
| 10991 | CEFBS_None, // G_INTRINSIC_CONVERGENT |
| 10992 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 10993 | CEFBS_None, // G_ANYEXT |
| 10994 | CEFBS_None, // G_TRUNC |
| 10995 | CEFBS_None, // G_TRUNC_SSAT_S |
| 10996 | CEFBS_None, // G_TRUNC_SSAT_U |
| 10997 | CEFBS_None, // G_TRUNC_USAT_U |
| 10998 | CEFBS_None, // G_CONSTANT |
| 10999 | CEFBS_None, // G_FCONSTANT |
| 11000 | CEFBS_None, // G_VASTART |
| 11001 | CEFBS_None, // G_VAARG |
| 11002 | CEFBS_None, // G_SEXT |
| 11003 | CEFBS_None, // G_SEXT_INREG |
| 11004 | CEFBS_None, // G_ZEXT |
| 11005 | CEFBS_None, // G_SHL |
| 11006 | CEFBS_None, // G_LSHR |
| 11007 | CEFBS_None, // G_ASHR |
| 11008 | CEFBS_None, // G_FSHL |
| 11009 | CEFBS_None, // G_FSHR |
| 11010 | CEFBS_None, // G_ROTR |
| 11011 | CEFBS_None, // G_ROTL |
| 11012 | CEFBS_None, // G_ICMP |
| 11013 | CEFBS_None, // G_FCMP |
| 11014 | CEFBS_None, // G_SCMP |
| 11015 | CEFBS_None, // G_UCMP |
| 11016 | CEFBS_None, // G_SELECT |
| 11017 | CEFBS_None, // G_UADDO |
| 11018 | CEFBS_None, // G_UADDE |
| 11019 | CEFBS_None, // G_USUBO |
| 11020 | CEFBS_None, // G_USUBE |
| 11021 | CEFBS_None, // G_SADDO |
| 11022 | CEFBS_None, // G_SADDE |
| 11023 | CEFBS_None, // G_SSUBO |
| 11024 | CEFBS_None, // G_SSUBE |
| 11025 | CEFBS_None, // G_UMULO |
| 11026 | CEFBS_None, // G_SMULO |
| 11027 | CEFBS_None, // G_UMULH |
| 11028 | CEFBS_None, // G_SMULH |
| 11029 | CEFBS_None, // G_UADDSAT |
| 11030 | CEFBS_None, // G_SADDSAT |
| 11031 | CEFBS_None, // G_USUBSAT |
| 11032 | CEFBS_None, // G_SSUBSAT |
| 11033 | CEFBS_None, // G_USHLSAT |
| 11034 | CEFBS_None, // G_SSHLSAT |
| 11035 | CEFBS_None, // G_SMULFIX |
| 11036 | CEFBS_None, // G_UMULFIX |
| 11037 | CEFBS_None, // G_SMULFIXSAT |
| 11038 | CEFBS_None, // G_UMULFIXSAT |
| 11039 | CEFBS_None, // G_SDIVFIX |
| 11040 | CEFBS_None, // G_UDIVFIX |
| 11041 | CEFBS_None, // G_SDIVFIXSAT |
| 11042 | CEFBS_None, // G_UDIVFIXSAT |
| 11043 | CEFBS_None, // G_FADD |
| 11044 | CEFBS_None, // G_FSUB |
| 11045 | CEFBS_None, // G_FMUL |
| 11046 | CEFBS_None, // G_FMA |
| 11047 | CEFBS_None, // G_FMAD |
| 11048 | CEFBS_None, // G_FDIV |
| 11049 | CEFBS_None, // G_FREM |
| 11050 | CEFBS_None, // G_FMODF |
| 11051 | CEFBS_None, // G_FPOW |
| 11052 | CEFBS_None, // G_FPOWI |
| 11053 | CEFBS_None, // G_FEXP |
| 11054 | CEFBS_None, // G_FEXP2 |
| 11055 | CEFBS_None, // G_FEXP10 |
| 11056 | CEFBS_None, // G_FLOG |
| 11057 | CEFBS_None, // G_FLOG2 |
| 11058 | CEFBS_None, // G_FLOG10 |
| 11059 | CEFBS_None, // G_FLDEXP |
| 11060 | CEFBS_None, // G_FFREXP |
| 11061 | CEFBS_None, // G_FNEG |
| 11062 | CEFBS_None, // G_FPEXT |
| 11063 | CEFBS_None, // G_FPTRUNC |
| 11064 | CEFBS_None, // G_FPTOSI |
| 11065 | CEFBS_None, // G_FPTOUI |
| 11066 | CEFBS_None, // G_SITOFP |
| 11067 | CEFBS_None, // G_UITOFP |
| 11068 | CEFBS_None, // G_FPTOSI_SAT |
| 11069 | CEFBS_None, // G_FPTOUI_SAT |
| 11070 | CEFBS_None, // G_FABS |
| 11071 | CEFBS_None, // G_FCOPYSIGN |
| 11072 | CEFBS_None, // G_IS_FPCLASS |
| 11073 | CEFBS_None, // G_FCANONICALIZE |
| 11074 | CEFBS_None, // G_FMINNUM |
| 11075 | CEFBS_None, // G_FMAXNUM |
| 11076 | CEFBS_None, // G_FMINNUM_IEEE |
| 11077 | CEFBS_None, // G_FMAXNUM_IEEE |
| 11078 | CEFBS_None, // G_FMINIMUM |
| 11079 | CEFBS_None, // G_FMAXIMUM |
| 11080 | CEFBS_None, // G_FMINIMUMNUM |
| 11081 | CEFBS_None, // G_FMAXIMUMNUM |
| 11082 | CEFBS_None, // G_GET_FPENV |
| 11083 | CEFBS_None, // G_SET_FPENV |
| 11084 | CEFBS_None, // G_RESET_FPENV |
| 11085 | CEFBS_None, // G_GET_FPMODE |
| 11086 | CEFBS_None, // G_SET_FPMODE |
| 11087 | CEFBS_None, // G_RESET_FPMODE |
| 11088 | CEFBS_None, // G_GET_ROUNDING |
| 11089 | CEFBS_None, // G_SET_ROUNDING |
| 11090 | CEFBS_None, // G_PTR_ADD |
| 11091 | CEFBS_None, // G_PTRMASK |
| 11092 | CEFBS_None, // G_SMIN |
| 11093 | CEFBS_None, // G_SMAX |
| 11094 | CEFBS_None, // G_UMIN |
| 11095 | CEFBS_None, // G_UMAX |
| 11096 | CEFBS_None, // G_ABS |
| 11097 | CEFBS_None, // G_LROUND |
| 11098 | CEFBS_None, // G_LLROUND |
| 11099 | CEFBS_None, // G_BR |
| 11100 | CEFBS_None, // G_BRJT |
| 11101 | CEFBS_None, // G_VSCALE |
| 11102 | CEFBS_None, // G_INSERT_SUBVECTOR |
| 11103 | CEFBS_None, // G_EXTRACT_SUBVECTOR |
| 11104 | CEFBS_None, // G_INSERT_VECTOR_ELT |
| 11105 | CEFBS_None, // G_EXTRACT_VECTOR_ELT |
| 11106 | CEFBS_None, // G_SHUFFLE_VECTOR |
| 11107 | CEFBS_None, // G_SPLAT_VECTOR |
| 11108 | CEFBS_None, // G_STEP_VECTOR |
| 11109 | CEFBS_None, // G_VECTOR_COMPRESS |
| 11110 | CEFBS_None, // G_CTTZ |
| 11111 | CEFBS_None, // G_CTTZ_ZERO_POISON |
| 11112 | CEFBS_None, // G_CTLZ |
| 11113 | CEFBS_None, // G_CTLZ_ZERO_POISON |
| 11114 | CEFBS_None, // G_CTLS |
| 11115 | CEFBS_None, // G_CTPOP |
| 11116 | CEFBS_None, // G_BSWAP |
| 11117 | CEFBS_None, // G_BITREVERSE |
| 11118 | CEFBS_None, // G_CLMUL |
| 11119 | CEFBS_None, // G_CLMULH |
| 11120 | CEFBS_None, // G_CLMULR |
| 11121 | CEFBS_None, // G_FCEIL |
| 11122 | CEFBS_None, // G_FCOS |
| 11123 | CEFBS_None, // G_FSIN |
| 11124 | CEFBS_None, // G_FSINCOS |
| 11125 | CEFBS_None, // G_FTAN |
| 11126 | CEFBS_None, // G_FACOS |
| 11127 | CEFBS_None, // G_FASIN |
| 11128 | CEFBS_None, // G_FATAN |
| 11129 | CEFBS_None, // G_FATAN2 |
| 11130 | CEFBS_None, // G_FCOSH |
| 11131 | CEFBS_None, // G_FSINH |
| 11132 | CEFBS_None, // G_FTANH |
| 11133 | CEFBS_None, // G_FSQRT |
| 11134 | CEFBS_None, // G_FFLOOR |
| 11135 | CEFBS_None, // G_FRINT |
| 11136 | CEFBS_None, // G_FNEARBYINT |
| 11137 | CEFBS_None, // G_ADDRSPACE_CAST |
| 11138 | CEFBS_None, // G_BLOCK_ADDR |
| 11139 | CEFBS_None, // G_JUMP_TABLE |
| 11140 | CEFBS_None, // G_DYN_STACKALLOC |
| 11141 | CEFBS_None, // G_STACKSAVE |
| 11142 | CEFBS_None, // G_STACKRESTORE |
| 11143 | CEFBS_None, // G_STRICT_FADD |
| 11144 | CEFBS_None, // G_STRICT_FSUB |
| 11145 | CEFBS_None, // G_STRICT_FMUL |
| 11146 | CEFBS_None, // G_STRICT_FDIV |
| 11147 | CEFBS_None, // G_STRICT_FREM |
| 11148 | CEFBS_None, // G_STRICT_FMA |
| 11149 | CEFBS_None, // G_STRICT_FSQRT |
| 11150 | CEFBS_None, // G_STRICT_FLDEXP |
| 11151 | CEFBS_None, // G_STRICT_FCMP |
| 11152 | CEFBS_None, // G_STRICT_FCMPS |
| 11153 | CEFBS_None, // G_READ_REGISTER |
| 11154 | CEFBS_None, // G_WRITE_REGISTER |
| 11155 | CEFBS_None, // G_MEMCPY |
| 11156 | CEFBS_None, // G_MEMCPY_INLINE |
| 11157 | CEFBS_None, // G_MEMMOVE |
| 11158 | CEFBS_None, // G_MEMSET |
| 11159 | CEFBS_None, // G_BZERO |
| 11160 | CEFBS_None, // G_MEMSET_INLINE |
| 11161 | CEFBS_None, // G_TRAP |
| 11162 | CEFBS_None, // G_DEBUGTRAP |
| 11163 | CEFBS_None, // G_UBSANTRAP |
| 11164 | CEFBS_None, // G_VECREDUCE_SEQ_FADD |
| 11165 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL |
| 11166 | CEFBS_None, // G_VECREDUCE_FADD |
| 11167 | CEFBS_None, // G_VECREDUCE_FMUL |
| 11168 | CEFBS_None, // G_VECREDUCE_FMAX |
| 11169 | CEFBS_None, // G_VECREDUCE_FMIN |
| 11170 | CEFBS_None, // G_VECREDUCE_FMAXIMUM |
| 11171 | CEFBS_None, // G_VECREDUCE_FMINIMUM |
| 11172 | CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM |
| 11173 | CEFBS_None, // G_VECREDUCE_FMINIMUMNUM |
| 11174 | CEFBS_None, // G_VECREDUCE_ADD |
| 11175 | CEFBS_None, // G_VECREDUCE_MUL |
| 11176 | CEFBS_None, // G_VECREDUCE_AND |
| 11177 | CEFBS_None, // G_VECREDUCE_OR |
| 11178 | CEFBS_None, // G_VECREDUCE_XOR |
| 11179 | CEFBS_None, // G_VECREDUCE_SMAX |
| 11180 | CEFBS_None, // G_VECREDUCE_SMIN |
| 11181 | CEFBS_None, // G_VECREDUCE_UMAX |
| 11182 | CEFBS_None, // G_VECREDUCE_UMIN |
| 11183 | CEFBS_None, // G_SBFX |
| 11184 | CEFBS_None, // G_UBFX |
| 11185 | CEFBS_None, // ABSMacro |
| 11186 | CEFBS_None, // ADJCALLSTACKDOWN |
| 11187 | CEFBS_None, // ADJCALLSTACKUP |
| 11188 | CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO |
| 11189 | CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO |
| 11190 | CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO |
| 11191 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 |
| 11192 | CEFBS_NotR5900, // ATOMIC_CMP_SWAP_I16_POSTRA |
| 11193 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 |
| 11194 | CEFBS_NotR5900, // ATOMIC_CMP_SWAP_I32_POSTRA |
| 11195 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 |
| 11196 | CEFBS_NotR5900, // ATOMIC_CMP_SWAP_I64_POSTRA |
| 11197 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 |
| 11198 | CEFBS_NotR5900, // ATOMIC_CMP_SWAP_I8_POSTRA |
| 11199 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 |
| 11200 | CEFBS_NotR5900, // ATOMIC_LOAD_ADD_I16_POSTRA |
| 11201 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 |
| 11202 | CEFBS_NotR5900, // ATOMIC_LOAD_ADD_I32_POSTRA |
| 11203 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 |
| 11204 | CEFBS_NotR5900, // ATOMIC_LOAD_ADD_I64_POSTRA |
| 11205 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 |
| 11206 | CEFBS_NotR5900, // ATOMIC_LOAD_ADD_I8_POSTRA |
| 11207 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 |
| 11208 | CEFBS_NotR5900, // ATOMIC_LOAD_AND_I16_POSTRA |
| 11209 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 |
| 11210 | CEFBS_NotR5900, // ATOMIC_LOAD_AND_I32_POSTRA |
| 11211 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 |
| 11212 | CEFBS_NotR5900, // ATOMIC_LOAD_AND_I64_POSTRA |
| 11213 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 |
| 11214 | CEFBS_NotR5900, // ATOMIC_LOAD_AND_I8_POSTRA |
| 11215 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 |
| 11216 | CEFBS_NotR5900, // ATOMIC_LOAD_MAX_I16_POSTRA |
| 11217 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 |
| 11218 | CEFBS_NotR5900, // ATOMIC_LOAD_MAX_I32_POSTRA |
| 11219 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 |
| 11220 | CEFBS_NotR5900, // ATOMIC_LOAD_MAX_I64_POSTRA |
| 11221 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 |
| 11222 | CEFBS_NotR5900, // ATOMIC_LOAD_MAX_I8_POSTRA |
| 11223 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 |
| 11224 | CEFBS_NotR5900, // ATOMIC_LOAD_MIN_I16_POSTRA |
| 11225 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 |
| 11226 | CEFBS_NotR5900, // ATOMIC_LOAD_MIN_I32_POSTRA |
| 11227 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 |
| 11228 | CEFBS_NotR5900, // ATOMIC_LOAD_MIN_I64_POSTRA |
| 11229 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 |
| 11230 | CEFBS_NotR5900, // ATOMIC_LOAD_MIN_I8_POSTRA |
| 11231 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 |
| 11232 | CEFBS_NotR5900, // ATOMIC_LOAD_NAND_I16_POSTRA |
| 11233 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 |
| 11234 | CEFBS_NotR5900, // ATOMIC_LOAD_NAND_I32_POSTRA |
| 11235 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 |
| 11236 | CEFBS_NotR5900, // ATOMIC_LOAD_NAND_I64_POSTRA |
| 11237 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 |
| 11238 | CEFBS_NotR5900, // ATOMIC_LOAD_NAND_I8_POSTRA |
| 11239 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 |
| 11240 | CEFBS_NotR5900, // ATOMIC_LOAD_OR_I16_POSTRA |
| 11241 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 |
| 11242 | CEFBS_NotR5900, // ATOMIC_LOAD_OR_I32_POSTRA |
| 11243 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 |
| 11244 | CEFBS_NotR5900, // ATOMIC_LOAD_OR_I64_POSTRA |
| 11245 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 |
| 11246 | CEFBS_NotR5900, // ATOMIC_LOAD_OR_I8_POSTRA |
| 11247 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 |
| 11248 | CEFBS_NotR5900, // ATOMIC_LOAD_SUB_I16_POSTRA |
| 11249 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 |
| 11250 | CEFBS_NotR5900, // ATOMIC_LOAD_SUB_I32_POSTRA |
| 11251 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 |
| 11252 | CEFBS_NotR5900, // ATOMIC_LOAD_SUB_I64_POSTRA |
| 11253 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 |
| 11254 | CEFBS_NotR5900, // ATOMIC_LOAD_SUB_I8_POSTRA |
| 11255 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 |
| 11256 | CEFBS_NotR5900, // ATOMIC_LOAD_UMAX_I16_POSTRA |
| 11257 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 |
| 11258 | CEFBS_NotR5900, // ATOMIC_LOAD_UMAX_I32_POSTRA |
| 11259 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 |
| 11260 | CEFBS_NotR5900, // ATOMIC_LOAD_UMAX_I64_POSTRA |
| 11261 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 |
| 11262 | CEFBS_NotR5900, // ATOMIC_LOAD_UMAX_I8_POSTRA |
| 11263 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 |
| 11264 | CEFBS_NotR5900, // ATOMIC_LOAD_UMIN_I16_POSTRA |
| 11265 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 |
| 11266 | CEFBS_NotR5900, // ATOMIC_LOAD_UMIN_I32_POSTRA |
| 11267 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 |
| 11268 | CEFBS_NotR5900, // ATOMIC_LOAD_UMIN_I64_POSTRA |
| 11269 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 |
| 11270 | CEFBS_NotR5900, // ATOMIC_LOAD_UMIN_I8_POSTRA |
| 11271 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 |
| 11272 | CEFBS_NotR5900, // ATOMIC_LOAD_XOR_I16_POSTRA |
| 11273 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 |
| 11274 | CEFBS_NotR5900, // ATOMIC_LOAD_XOR_I32_POSTRA |
| 11275 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 |
| 11276 | CEFBS_NotR5900, // ATOMIC_LOAD_XOR_I64_POSTRA |
| 11277 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 |
| 11278 | CEFBS_NotR5900, // ATOMIC_LOAD_XOR_I8_POSTRA |
| 11279 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 |
| 11280 | CEFBS_NotR5900, // ATOMIC_SWAP_I16_POSTRA |
| 11281 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 |
| 11282 | CEFBS_NotR5900, // ATOMIC_SWAP_I32_POSTRA |
| 11283 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 |
| 11284 | CEFBS_NotR5900, // ATOMIC_SWAP_I64_POSTRA |
| 11285 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 |
| 11286 | CEFBS_NotR5900, // ATOMIC_SWAP_I8_POSTRA |
| 11287 | CEFBS_HasStdEnc_NotInMicroMips, // B |
| 11288 | CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR |
| 11289 | CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM |
| 11290 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro |
| 11291 | CEFBS_None, // BGE |
| 11292 | CEFBS_None, // BGEImmMacro |
| 11293 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL |
| 11294 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro |
| 11295 | CEFBS_None, // BGEU |
| 11296 | CEFBS_None, // BGEUImmMacro |
| 11297 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL |
| 11298 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro |
| 11299 | CEFBS_None, // BGT |
| 11300 | CEFBS_None, // BGTImmMacro |
| 11301 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL |
| 11302 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro |
| 11303 | CEFBS_None, // BGTU |
| 11304 | CEFBS_None, // BGTUImmMacro |
| 11305 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL |
| 11306 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro |
| 11307 | CEFBS_None, // BLE |
| 11308 | CEFBS_None, // BLEImmMacro |
| 11309 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL |
| 11310 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro |
| 11311 | CEFBS_None, // BLEU |
| 11312 | CEFBS_None, // BLEUImmMacro |
| 11313 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL |
| 11314 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro |
| 11315 | CEFBS_None, // BLT |
| 11316 | CEFBS_None, // BLTImmMacro |
| 11317 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL |
| 11318 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro |
| 11319 | CEFBS_None, // BLTU |
| 11320 | CEFBS_None, // BLTUImmMacro |
| 11321 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL |
| 11322 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro |
| 11323 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro |
| 11324 | CEFBS_None, // BPOSGE32_PSEUDO |
| 11325 | CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO |
| 11326 | CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO |
| 11327 | CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO |
| 11328 | CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO |
| 11329 | CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO |
| 11330 | CEFBS_InMicroMips_NotMips32r6, // B_MM |
| 11331 | CEFBS_None, // B_MMR6_Pseudo |
| 11332 | CEFBS_InMicroMips, // B_MM_Pseudo |
| 11333 | CEFBS_None, // BeqImm |
| 11334 | CEFBS_None, // BneImm |
| 11335 | CEFBS_InMips16Mode, // BteqzT8CmpX16 |
| 11336 | CEFBS_InMips16Mode, // BteqzT8CmpiX16 |
| 11337 | CEFBS_InMips16Mode, // BteqzT8SltX16 |
| 11338 | CEFBS_InMips16Mode, // BteqzT8SltiX16 |
| 11339 | CEFBS_InMips16Mode, // BteqzT8SltiuX16 |
| 11340 | CEFBS_InMips16Mode, // BteqzT8SltuX16 |
| 11341 | CEFBS_InMips16Mode, // BtnezT8CmpX16 |
| 11342 | CEFBS_InMips16Mode, // BtnezT8CmpiX16 |
| 11343 | CEFBS_InMips16Mode, // BtnezT8SltX16 |
| 11344 | CEFBS_InMips16Mode, // BtnezT8SltiX16 |
| 11345 | CEFBS_InMips16Mode, // BtnezT8SltiuX16 |
| 11346 | CEFBS_InMips16Mode, // BtnezT8SltuX16 |
| 11347 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // BuildPairF64 |
| 11348 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // BuildPairF64_64 |
| 11349 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // BuildPairF64_FPR |
| 11350 | CEFBS_HasMT, // CFTC1 |
| 11351 | CEFBS_InMips16Mode, // CONSTPOOL_ENTRY |
| 11352 | CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO |
| 11353 | CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO |
| 11354 | CEFBS_HasMT, // CTTC1 |
| 11355 | CEFBS_InMips16Mode, // Constant32 |
| 11356 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // DMULImmMacro |
| 11357 | CEFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900, // DMULMacro |
| 11358 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // DMULOMacro |
| 11359 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // DMULOUMacro |
| 11360 | CEFBS_HasStdEnc_HasMips64, // DROL |
| 11361 | CEFBS_HasStdEnc_HasMips64, // DROLImm |
| 11362 | CEFBS_HasStdEnc_HasMips64, // DROR |
| 11363 | CEFBS_HasStdEnc_HasMips64, // DRORImm |
| 11364 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSDivIMacro |
| 11365 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSDivMacro |
| 11366 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSRemIMacro |
| 11367 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSRemMacro |
| 11368 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DUDivIMacro |
| 11369 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DUDivMacro |
| 11370 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DURemIMacro |
| 11371 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DURemMacro |
| 11372 | CEFBS_NotInMips16Mode, // ERet |
| 11373 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // ExtractElementF64 |
| 11374 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // ExtractElementF64_64 |
| 11375 | CEFBS_HasStdEnc_HasMSA, // FABS_D |
| 11376 | CEFBS_HasStdEnc_HasMSA, // FABS_W |
| 11377 | CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO |
| 11378 | CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO |
| 11379 | CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO |
| 11380 | CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO |
| 11381 | CEFBS_InMips16Mode, // GotPrologue16 |
| 11382 | CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO |
| 11383 | CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO |
| 11384 | CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO |
| 11385 | CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO |
| 11386 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO |
| 11387 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO |
| 11388 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO |
| 11389 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO |
| 11390 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO |
| 11391 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO |
| 11392 | CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO |
| 11393 | CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO |
| 11394 | CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO |
| 11395 | CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO |
| 11396 | CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo |
| 11397 | CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo |
| 11398 | CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo |
| 11399 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo |
| 11400 | CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 |
| 11401 | CEFBS_None, // JalOneReg |
| 11402 | CEFBS_None, // JalTwoReg |
| 11403 | CEFBS_HasStdEnc_NotMips3, // LDMacro |
| 11404 | CEFBS_NotInMips16Mode, // LDR_D |
| 11405 | CEFBS_NotInMips16Mode, // LDR_W |
| 11406 | CEFBS_NotInMips16Mode, // LOAD_ACC128 |
| 11407 | CEFBS_NotInMips16Mode, // LOAD_ACC64 |
| 11408 | CEFBS_NotInMips16Mode, // LOAD_ACC64DSP |
| 11409 | CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP |
| 11410 | CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu |
| 11411 | CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op |
| 11412 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu |
| 11413 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op |
| 11414 | CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi |
| 11415 | CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op |
| 11416 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 |
| 11417 | CEFBS_InMicroMips, // LWM_MM |
| 11418 | CEFBS_None, // LoadAddrImm32 |
| 11419 | CEFBS_None, // LoadAddrImm64 |
| 11420 | CEFBS_None, // LoadAddrReg32 |
| 11421 | CEFBS_None, // LoadAddrReg64 |
| 11422 | CEFBS_None, // LoadImm32 |
| 11423 | CEFBS_None, // LoadImm64 |
| 11424 | CEFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // LoadImmDoubleFGR |
| 11425 | CEFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // LoadImmDoubleFGR_32 |
| 11426 | CEFBS_None, // LoadImmDoubleGPR |
| 11427 | CEFBS_IsNotSoftFloat, // LoadImmSingleFGR |
| 11428 | CEFBS_None, // LoadImmSingleGPR |
| 11429 | CEFBS_InMips16Mode, // LwConstant32 |
| 11430 | CEFBS_HasMT, // MFTACX |
| 11431 | CEFBS_HasMT, // MFTC0 |
| 11432 | CEFBS_HasMT, // MFTC1 |
| 11433 | CEFBS_HasMT, // MFTDSP |
| 11434 | CEFBS_HasMT, // MFTGPR |
| 11435 | CEFBS_HasMT, // MFTHC1 |
| 11436 | CEFBS_HasMT, // MFTHI |
| 11437 | CEFBS_HasMT, // MFTLO |
| 11438 | CEFBS_None, // MIPSeh_return32 |
| 11439 | CEFBS_None, // MIPSeh_return64 |
| 11440 | CEFBS_HasMT, // MTTACX |
| 11441 | CEFBS_HasMT, // MTTC0 |
| 11442 | CEFBS_HasMT, // MTTC1 |
| 11443 | CEFBS_HasMT, // MTTDSP |
| 11444 | CEFBS_HasMT, // MTTGPR |
| 11445 | CEFBS_HasMT, // MTTHC1 |
| 11446 | CEFBS_HasMT, // MTTHI |
| 11447 | CEFBS_HasMT, // MTTLO |
| 11448 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro |
| 11449 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro |
| 11450 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro |
| 11451 | CEFBS_InMips16Mode, // MultRxRy16 |
| 11452 | CEFBS_InMips16Mode, // MultRxRyRz16 |
| 11453 | CEFBS_InMips16Mode, // MultuRxRy16 |
| 11454 | CEFBS_InMips16Mode, // MultuRxRyRz16 |
| 11455 | CEFBS_HasStdEnc_NotInMicroMips, // NOP |
| 11456 | CEFBS_IsGP32bit, // NORImm |
| 11457 | CEFBS_IsGP64bit, // NORImm64 |
| 11458 | CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO |
| 11459 | CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO |
| 11460 | CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO |
| 11461 | CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO |
| 11462 | CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO |
| 11463 | CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO |
| 11464 | CEFBS_HasDSP, // PseudoCMPU_EQ_QB |
| 11465 | CEFBS_HasDSP, // PseudoCMPU_LE_QB |
| 11466 | CEFBS_HasDSP, // PseudoCMPU_LT_QB |
| 11467 | CEFBS_HasDSP, // PseudoCMP_EQ_PH |
| 11468 | CEFBS_HasDSP, // PseudoCMP_LE_PH |
| 11469 | CEFBS_HasDSP, // PseudoCMP_LT_PH |
| 11470 | CEFBS_IsNotSingleFloat, // PseudoCVT_D32_W |
| 11471 | CEFBS_IsNotSingleFloat, // PseudoCVT_D64_L |
| 11472 | CEFBS_IsNotSingleFloat, // PseudoCVT_D64_W |
| 11473 | CEFBS_IsNotSingleFloat, // PseudoCVT_S_L |
| 11474 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W |
| 11475 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // PseudoDMULT |
| 11476 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // PseudoDMULTu |
| 11477 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // PseudoDSDIV |
| 11478 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // PseudoDUDIV |
| 11479 | CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I |
| 11480 | CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 |
| 11481 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch |
| 11482 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 |
| 11483 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 |
| 11484 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 |
| 11485 | CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM |
| 11486 | CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 |
| 11487 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch |
| 11488 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 |
| 11489 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 |
| 11490 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 |
| 11491 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD |
| 11492 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU |
| 11493 | CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM |
| 11494 | CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM |
| 11495 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI |
| 11496 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 |
| 11497 | CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM |
| 11498 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO |
| 11499 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 |
| 11500 | CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM |
| 11501 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB |
| 11502 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU |
| 11503 | CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM |
| 11504 | CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM |
| 11505 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI |
| 11506 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 |
| 11507 | CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP |
| 11508 | CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM |
| 11509 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT |
| 11510 | CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM |
| 11511 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu |
| 11512 | CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM |
| 11513 | CEFBS_HasDSP, // PseudoPICK_PH |
| 11514 | CEFBS_HasDSP, // PseudoPICK_QB |
| 11515 | CEFBS_None, // PseudoReturn |
| 11516 | CEFBS_IsGP64bit, // PseudoReturn64 |
| 11517 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV |
| 11518 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips4_32, // PseudoSELECTFP_F_D32 |
| 11519 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32, // PseudoSELECTFP_F_D64 |
| 11520 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I |
| 11521 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 |
| 11522 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S |
| 11523 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips4_32, // PseudoSELECTFP_T_D32 |
| 11524 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32, // PseudoSELECTFP_T_D64 |
| 11525 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I |
| 11526 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 |
| 11527 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S |
| 11528 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips4_32, // PseudoSELECT_D32 |
| 11529 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32, // PseudoSELECT_D64 |
| 11530 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I |
| 11531 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 |
| 11532 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S |
| 11533 | CEFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // PseudoTRUNC_W_D |
| 11534 | CEFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // PseudoTRUNC_W_D32 |
| 11535 | CEFBS_None, // PseudoTRUNC_W_S |
| 11536 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV |
| 11537 | CEFBS_None, // ROL |
| 11538 | CEFBS_None, // ROLImm |
| 11539 | CEFBS_None, // ROR |
| 11540 | CEFBS_None, // RORImm |
| 11541 | CEFBS_NotInMips16Mode, // RetRA |
| 11542 | CEFBS_InMips16Mode, // RetRA16 |
| 11543 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // SDC1_M1 |
| 11544 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo |
| 11545 | CEFBS_HasStdEnc_NotMips3, // SDMacro |
| 11546 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro |
| 11547 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro |
| 11548 | CEFBS_NotCnMips, // SEQIMacro |
| 11549 | CEFBS_NotCnMips, // SEQMacro |
| 11550 | CEFBS_HasStdEnc_NotInMicroMips, // SGE |
| 11551 | CEFBS_IsGP32bit_NotInMicroMips, // SGEImm |
| 11552 | CEFBS_IsGP64bit, // SGEImm64 |
| 11553 | CEFBS_HasStdEnc_NotInMicroMips, // SGEU |
| 11554 | CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm |
| 11555 | CEFBS_IsGP64bit, // SGEUImm64 |
| 11556 | CEFBS_IsGP32bit_NotInMicroMips, // SGTImm |
| 11557 | CEFBS_IsGP64bit, // SGTImm64 |
| 11558 | CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm |
| 11559 | CEFBS_IsGP64bit, // SGTUImm64 |
| 11560 | CEFBS_HasStdEnc_NotInMicroMips, // SLE |
| 11561 | CEFBS_IsGP32bit_NotInMicroMips, // SLEImm |
| 11562 | CEFBS_IsGP64bit, // SLEImm64 |
| 11563 | CEFBS_HasStdEnc_NotInMicroMips, // SLEU |
| 11564 | CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm |
| 11565 | CEFBS_IsGP64bit, // SLEUImm64 |
| 11566 | CEFBS_IsGP64bit, // SLTImm64 |
| 11567 | CEFBS_IsGP64bit, // SLTUImm64 |
| 11568 | CEFBS_NotCnMips, // SNEIMacro |
| 11569 | CEFBS_NotCnMips, // SNEMacro |
| 11570 | CEFBS_None, // SNZ_B_PSEUDO |
| 11571 | CEFBS_None, // SNZ_D_PSEUDO |
| 11572 | CEFBS_None, // SNZ_H_PSEUDO |
| 11573 | CEFBS_None, // SNZ_V_PSEUDO |
| 11574 | CEFBS_None, // SNZ_W_PSEUDO |
| 11575 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro |
| 11576 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro |
| 11577 | CEFBS_NotInMips16Mode, // STORE_ACC128 |
| 11578 | CEFBS_NotInMips16Mode, // STORE_ACC64 |
| 11579 | CEFBS_NotInMips16Mode, // STORE_ACC64DSP |
| 11580 | CEFBS_NotInMips16Mode, // STORE_CCOND_DSP |
| 11581 | CEFBS_NotInMips16Mode, // STR_D |
| 11582 | CEFBS_NotInMips16Mode, // STR_W |
| 11583 | CEFBS_InMicroMips, // SWM_MM |
| 11584 | CEFBS_None, // SZ_B_PSEUDO |
| 11585 | CEFBS_None, // SZ_D_PSEUDO |
| 11586 | CEFBS_None, // SZ_H_PSEUDO |
| 11587 | CEFBS_None, // SZ_V_PSEUDO |
| 11588 | CEFBS_None, // SZ_W_PSEUDO |
| 11589 | CEFBS_HasCnMipsP, // SaaAddr |
| 11590 | CEFBS_HasCnMipsP, // SaadAddr |
| 11591 | CEFBS_InMips16Mode, // SelBeqZ |
| 11592 | CEFBS_InMips16Mode, // SelBneZ |
| 11593 | CEFBS_InMips16Mode, // SelTBteqZCmp |
| 11594 | CEFBS_InMips16Mode, // SelTBteqZCmpi |
| 11595 | CEFBS_InMips16Mode, // SelTBteqZSlt |
| 11596 | CEFBS_InMips16Mode, // SelTBteqZSlti |
| 11597 | CEFBS_InMips16Mode, // SelTBteqZSltiu |
| 11598 | CEFBS_InMips16Mode, // SelTBteqZSltu |
| 11599 | CEFBS_InMips16Mode, // SelTBtneZCmp |
| 11600 | CEFBS_InMips16Mode, // SelTBtneZCmpi |
| 11601 | CEFBS_InMips16Mode, // SelTBtneZSlt |
| 11602 | CEFBS_InMips16Mode, // SelTBtneZSlti |
| 11603 | CEFBS_InMips16Mode, // SelTBtneZSltiu |
| 11604 | CEFBS_InMips16Mode, // SelTBtneZSltu |
| 11605 | CEFBS_InMips16Mode, // SltCCRxRy16 |
| 11606 | CEFBS_InMips16Mode, // SltiCCRxImmX16 |
| 11607 | CEFBS_InMips16Mode, // SltiuCCRxImmX16 |
| 11608 | CEFBS_InMips16Mode, // SltuCCRxRy16 |
| 11609 | CEFBS_InMips16Mode, // SltuRxRyRz16 |
| 11610 | CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL |
| 11611 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG |
| 11612 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG |
| 11613 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG |
| 11614 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG |
| 11615 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG |
| 11616 | CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 |
| 11617 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB |
| 11618 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 |
| 11619 | CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM |
| 11620 | CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 |
| 11621 | CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM |
| 11622 | CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 |
| 11623 | CEFBS_HasStdEnc_NotInMicroMips, // TRAP |
| 11624 | CEFBS_InMicroMips, // TRAP_MM |
| 11625 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo |
| 11626 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro |
| 11627 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro |
| 11628 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro |
| 11629 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro |
| 11630 | CEFBS_None, // Ulh |
| 11631 | CEFBS_None, // Ulhu |
| 11632 | CEFBS_None, // Ulw |
| 11633 | CEFBS_None, // Ush |
| 11634 | CEFBS_None, // Usw |
| 11635 | CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO |
| 11636 | CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO |
| 11637 | CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO |
| 11638 | CEFBS_HasDSP, // ABSQ_S_PH |
| 11639 | CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM |
| 11640 | CEFBS_HasDSPR2, // ABSQ_S_QB |
| 11641 | CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 |
| 11642 | CEFBS_HasDSP, // ABSQ_S_W |
| 11643 | CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM |
| 11644 | CEFBS_HasStdEnc_NotInMicroMips, // ADD |
| 11645 | CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC |
| 11646 | CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM |
| 11647 | CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 |
| 11648 | CEFBS_InMicroMips, // ADDIUR1SP_MM |
| 11649 | CEFBS_InMicroMips, // ADDIUR2_MM |
| 11650 | CEFBS_InMicroMips, // ADDIUS5_MM |
| 11651 | CEFBS_InMicroMips, // ADDIUSP_MM |
| 11652 | CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 |
| 11653 | CEFBS_HasDSPR2, // ADDQH_PH |
| 11654 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 |
| 11655 | CEFBS_HasDSPR2, // ADDQH_R_PH |
| 11656 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 |
| 11657 | CEFBS_HasDSPR2, // ADDQH_R_W |
| 11658 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 |
| 11659 | CEFBS_HasDSPR2, // ADDQH_W |
| 11660 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 |
| 11661 | CEFBS_HasDSP, // ADDQ_PH |
| 11662 | CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM |
| 11663 | CEFBS_HasDSP, // ADDQ_S_PH |
| 11664 | CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM |
| 11665 | CEFBS_HasDSP, // ADDQ_S_W |
| 11666 | CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM |
| 11667 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 |
| 11668 | CEFBS_HasDSP, // ADDSC |
| 11669 | CEFBS_InMicroMips_HasDSP, // ADDSC_MM |
| 11670 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_B |
| 11671 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_D |
| 11672 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_H |
| 11673 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_W |
| 11674 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_B |
| 11675 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_D |
| 11676 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_H |
| 11677 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_W |
| 11678 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_B |
| 11679 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_D |
| 11680 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_H |
| 11681 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_W |
| 11682 | CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM |
| 11683 | CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 |
| 11684 | CEFBS_HasDSPR2, // ADDUH_QB |
| 11685 | CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 |
| 11686 | CEFBS_HasDSPR2, // ADDUH_R_QB |
| 11687 | CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 |
| 11688 | CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 |
| 11689 | CEFBS_HasDSPR2, // ADDU_PH |
| 11690 | CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 |
| 11691 | CEFBS_HasDSP, // ADDU_QB |
| 11692 | CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM |
| 11693 | CEFBS_HasDSPR2, // ADDU_S_PH |
| 11694 | CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 |
| 11695 | CEFBS_HasDSP, // ADDU_S_QB |
| 11696 | CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM |
| 11697 | CEFBS_HasStdEnc_HasMSA, // ADDVI_B |
| 11698 | CEFBS_HasStdEnc_HasMSA, // ADDVI_D |
| 11699 | CEFBS_HasStdEnc_HasMSA, // ADDVI_H |
| 11700 | CEFBS_HasStdEnc_HasMSA, // ADDVI_W |
| 11701 | CEFBS_HasStdEnc_HasMSA, // ADDV_B |
| 11702 | CEFBS_HasStdEnc_HasMSA, // ADDV_D |
| 11703 | CEFBS_HasStdEnc_HasMSA, // ADDV_H |
| 11704 | CEFBS_HasStdEnc_HasMSA, // ADDV_W |
| 11705 | CEFBS_HasDSP, // ADDWC |
| 11706 | CEFBS_InMicroMips_HasDSP, // ADDWC_MM |
| 11707 | CEFBS_HasStdEnc_HasMSA, // ADD_A_B |
| 11708 | CEFBS_HasStdEnc_HasMSA, // ADD_A_D |
| 11709 | CEFBS_HasStdEnc_HasMSA, // ADD_A_H |
| 11710 | CEFBS_HasStdEnc_HasMSA, // ADD_A_W |
| 11711 | CEFBS_InMicroMips_NotMips32r6, // ADD_MM |
| 11712 | CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 |
| 11713 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi |
| 11714 | CEFBS_InMicroMips_NotMips32r6, // ADDi_MM |
| 11715 | CEFBS_HasStdEnc_NotInMicroMips, // ADDiu |
| 11716 | CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM |
| 11717 | CEFBS_HasStdEnc_NotInMicroMips, // ADDu |
| 11718 | CEFBS_InMicroMips_NotMips32r6, // ADDu_MM |
| 11719 | CEFBS_HasStdEnc_HasMips32r6, // ALIGN |
| 11720 | CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 |
| 11721 | CEFBS_HasStdEnc_HasMips32r6, // ALUIPC |
| 11722 | CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 |
| 11723 | CEFBS_HasStdEnc_NotInMicroMips, // AND |
| 11724 | CEFBS_InMicroMips_NotMips32r6, // AND16_MM |
| 11725 | CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 |
| 11726 | CEFBS_NotInMips16Mode_IsGP64bit, // AND64 |
| 11727 | CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM |
| 11728 | CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 |
| 11729 | CEFBS_HasStdEnc_HasMSA, // ANDI_B |
| 11730 | CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 |
| 11731 | CEFBS_InMicroMips_NotMips32r6, // AND_MM |
| 11732 | CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 |
| 11733 | CEFBS_HasStdEnc_HasMSA, // AND_V |
| 11734 | CEFBS_HasStdEnc_NotInMicroMips, // ANDi |
| 11735 | CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 |
| 11736 | CEFBS_InMicroMips_NotMips32r6, // ANDi_MM |
| 11737 | CEFBS_HasDSPR2, // APPEND |
| 11738 | CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 |
| 11739 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_B |
| 11740 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_D |
| 11741 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_H |
| 11742 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_W |
| 11743 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_B |
| 11744 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_D |
| 11745 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_H |
| 11746 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_W |
| 11747 | CEFBS_HasStdEnc_HasMips32r6, // AUI |
| 11748 | CEFBS_HasStdEnc_HasMips32r6, // AUIPC |
| 11749 | CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 |
| 11750 | CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 |
| 11751 | CEFBS_HasStdEnc_HasMSA, // AVER_S_B |
| 11752 | CEFBS_HasStdEnc_HasMSA, // AVER_S_D |
| 11753 | CEFBS_HasStdEnc_HasMSA, // AVER_S_H |
| 11754 | CEFBS_HasStdEnc_HasMSA, // AVER_S_W |
| 11755 | CEFBS_HasStdEnc_HasMSA, // AVER_U_B |
| 11756 | CEFBS_HasStdEnc_HasMSA, // AVER_U_D |
| 11757 | CEFBS_HasStdEnc_HasMSA, // AVER_U_H |
| 11758 | CEFBS_HasStdEnc_HasMSA, // AVER_U_W |
| 11759 | CEFBS_HasStdEnc_HasMSA, // AVE_S_B |
| 11760 | CEFBS_HasStdEnc_HasMSA, // AVE_S_D |
| 11761 | CEFBS_HasStdEnc_HasMSA, // AVE_S_H |
| 11762 | CEFBS_HasStdEnc_HasMSA, // AVE_S_W |
| 11763 | CEFBS_HasStdEnc_HasMSA, // AVE_U_B |
| 11764 | CEFBS_HasStdEnc_HasMSA, // AVE_U_D |
| 11765 | CEFBS_HasStdEnc_HasMSA, // AVE_U_H |
| 11766 | CEFBS_HasStdEnc_HasMSA, // AVE_U_W |
| 11767 | CEFBS_InMips16Mode, // AddiuRxImmX16 |
| 11768 | CEFBS_InMips16Mode, // AddiuRxPcImmX16 |
| 11769 | CEFBS_InMips16Mode, // AddiuRxRxImm16 |
| 11770 | CEFBS_InMips16Mode, // AddiuRxRxImmX16 |
| 11771 | CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 |
| 11772 | CEFBS_InMips16Mode, // AddiuSpImm16 |
| 11773 | CEFBS_InMips16Mode, // AddiuSpImmX16 |
| 11774 | CEFBS_InMips16Mode, // AdduRxRyRz16 |
| 11775 | CEFBS_InMips16Mode, // AndRxRxRy16 |
| 11776 | CEFBS_InMicroMips, // B16_MM |
| 11777 | CEFBS_HasCnMips, // BADDu |
| 11778 | CEFBS_HasStdEnc_HasMips32r6, // BAL |
| 11779 | CEFBS_HasStdEnc_HasMips32r6, // BALC |
| 11780 | CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 |
| 11781 | CEFBS_HasDSPR2, // BALIGN |
| 11782 | CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 |
| 11783 | CEFBS_HasCnMips, // BBIT0 |
| 11784 | CEFBS_HasCnMips, // BBIT032 |
| 11785 | CEFBS_HasCnMips, // BBIT1 |
| 11786 | CEFBS_HasCnMips, // BBIT132 |
| 11787 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC |
| 11788 | CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 |
| 11789 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ |
| 11790 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 |
| 11791 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F |
| 11792 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL |
| 11793 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM |
| 11794 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ |
| 11795 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 |
| 11796 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T |
| 11797 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL |
| 11798 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM |
| 11799 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ |
| 11800 | CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 |
| 11801 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ |
| 11802 | CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 |
| 11803 | CEFBS_HasStdEnc_HasMSA, // BCLRI_B |
| 11804 | CEFBS_HasStdEnc_HasMSA, // BCLRI_D |
| 11805 | CEFBS_HasStdEnc_HasMSA, // BCLRI_H |
| 11806 | CEFBS_HasStdEnc_HasMSA, // BCLRI_W |
| 11807 | CEFBS_HasStdEnc_HasMSA, // BCLR_B |
| 11808 | CEFBS_HasStdEnc_HasMSA, // BCLR_D |
| 11809 | CEFBS_HasStdEnc_HasMSA, // BCLR_H |
| 11810 | CEFBS_HasStdEnc_HasMSA, // BCLR_W |
| 11811 | CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 |
| 11812 | CEFBS_HasStdEnc_NotInMicroMips, // BEQ |
| 11813 | CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 |
| 11814 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC |
| 11815 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 |
| 11816 | CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 |
| 11817 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL |
| 11818 | CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM |
| 11819 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC |
| 11820 | CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 |
| 11821 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC |
| 11822 | CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 |
| 11823 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 |
| 11824 | CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM |
| 11825 | CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 |
| 11826 | CEFBS_InMicroMips_NotMips32r6, // BEQ_MM |
| 11827 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC |
| 11828 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 |
| 11829 | CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 |
| 11830 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC |
| 11831 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 |
| 11832 | CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 |
| 11833 | CEFBS_HasStdEnc_NotInMicroMips, // BGEZ |
| 11834 | CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 |
| 11835 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL |
| 11836 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC |
| 11837 | CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 |
| 11838 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL |
| 11839 | CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM |
| 11840 | CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM |
| 11841 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC |
| 11842 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 |
| 11843 | CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 |
| 11844 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL |
| 11845 | CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM |
| 11846 | CEFBS_HasStdEnc_NotInMicroMips, // BGTZ |
| 11847 | CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 |
| 11848 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC |
| 11849 | CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 |
| 11850 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC |
| 11851 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 |
| 11852 | CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 |
| 11853 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL |
| 11854 | CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM |
| 11855 | CEFBS_HasStdEnc_HasMSA, // BINSLI_B |
| 11856 | CEFBS_HasStdEnc_HasMSA, // BINSLI_D |
| 11857 | CEFBS_HasStdEnc_HasMSA, // BINSLI_H |
| 11858 | CEFBS_HasStdEnc_HasMSA, // BINSLI_W |
| 11859 | CEFBS_HasStdEnc_HasMSA, // BINSL_B |
| 11860 | CEFBS_HasStdEnc_HasMSA, // BINSL_D |
| 11861 | CEFBS_HasStdEnc_HasMSA, // BINSL_H |
| 11862 | CEFBS_HasStdEnc_HasMSA, // BINSL_W |
| 11863 | CEFBS_HasStdEnc_HasMSA, // BINSRI_B |
| 11864 | CEFBS_HasStdEnc_HasMSA, // BINSRI_D |
| 11865 | CEFBS_HasStdEnc_HasMSA, // BINSRI_H |
| 11866 | CEFBS_HasStdEnc_HasMSA, // BINSRI_W |
| 11867 | CEFBS_HasStdEnc_HasMSA, // BINSR_B |
| 11868 | CEFBS_HasStdEnc_HasMSA, // BINSR_D |
| 11869 | CEFBS_HasStdEnc_HasMSA, // BINSR_H |
| 11870 | CEFBS_HasStdEnc_HasMSA, // BINSR_W |
| 11871 | CEFBS_HasDSP, // BITREV |
| 11872 | CEFBS_InMicroMips_HasDSP, // BITREV_MM |
| 11873 | CEFBS_HasStdEnc_HasMips32r6, // BITSWAP |
| 11874 | CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 |
| 11875 | CEFBS_HasStdEnc_NotInMicroMips, // BLEZ |
| 11876 | CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 |
| 11877 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC |
| 11878 | CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 |
| 11879 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC |
| 11880 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 |
| 11881 | CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 |
| 11882 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL |
| 11883 | CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM |
| 11884 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC |
| 11885 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 |
| 11886 | CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 |
| 11887 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC |
| 11888 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 |
| 11889 | CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 |
| 11890 | CEFBS_HasStdEnc_NotInMicroMips, // BLTZ |
| 11891 | CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 |
| 11892 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL |
| 11893 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC |
| 11894 | CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 |
| 11895 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL |
| 11896 | CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM |
| 11897 | CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM |
| 11898 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC |
| 11899 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 |
| 11900 | CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 |
| 11901 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL |
| 11902 | CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM |
| 11903 | CEFBS_HasStdEnc_HasMSA, // BMNZI_B |
| 11904 | CEFBS_HasStdEnc_HasMSA, // BMNZ_V |
| 11905 | CEFBS_HasStdEnc_HasMSA, // BMZI_B |
| 11906 | CEFBS_HasStdEnc_HasMSA, // BMZ_V |
| 11907 | CEFBS_HasStdEnc_NotInMicroMips, // BNE |
| 11908 | CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 |
| 11909 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC |
| 11910 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 |
| 11911 | CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 |
| 11912 | CEFBS_HasStdEnc_HasMSA, // BNEGI_B |
| 11913 | CEFBS_HasStdEnc_HasMSA, // BNEGI_D |
| 11914 | CEFBS_HasStdEnc_HasMSA, // BNEGI_H |
| 11915 | CEFBS_HasStdEnc_HasMSA, // BNEGI_W |
| 11916 | CEFBS_HasStdEnc_HasMSA, // BNEG_B |
| 11917 | CEFBS_HasStdEnc_HasMSA, // BNEG_D |
| 11918 | CEFBS_HasStdEnc_HasMSA, // BNEG_H |
| 11919 | CEFBS_HasStdEnc_HasMSA, // BNEG_W |
| 11920 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL |
| 11921 | CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM |
| 11922 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC |
| 11923 | CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 |
| 11924 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC |
| 11925 | CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 |
| 11926 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 |
| 11927 | CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM |
| 11928 | CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 |
| 11929 | CEFBS_InMicroMips_NotMips32r6, // BNE_MM |
| 11930 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC |
| 11931 | CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 |
| 11932 | CEFBS_HasStdEnc_HasMSA, // BNZ_B |
| 11933 | CEFBS_HasStdEnc_HasMSA, // BNZ_D |
| 11934 | CEFBS_HasStdEnc_HasMSA, // BNZ_H |
| 11935 | CEFBS_HasStdEnc_HasMSA, // BNZ_V |
| 11936 | CEFBS_HasStdEnc_HasMSA, // BNZ_W |
| 11937 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC |
| 11938 | CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 |
| 11939 | CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 |
| 11940 | CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 |
| 11941 | CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM |
| 11942 | CEFBS_HasStdEnc_NotInMicroMips, // BREAK |
| 11943 | CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM |
| 11944 | CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 |
| 11945 | CEFBS_InMicroMips, // BREAK_MM |
| 11946 | CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 |
| 11947 | CEFBS_HasStdEnc_HasMSA, // BSELI_B |
| 11948 | CEFBS_HasStdEnc_HasMSA, // BSEL_V |
| 11949 | CEFBS_HasStdEnc_HasMSA, // BSETI_B |
| 11950 | CEFBS_HasStdEnc_HasMSA, // BSETI_D |
| 11951 | CEFBS_HasStdEnc_HasMSA, // BSETI_H |
| 11952 | CEFBS_HasStdEnc_HasMSA, // BSETI_W |
| 11953 | CEFBS_HasStdEnc_HasMSA, // BSET_B |
| 11954 | CEFBS_HasStdEnc_HasMSA, // BSET_D |
| 11955 | CEFBS_HasStdEnc_HasMSA, // BSET_H |
| 11956 | CEFBS_HasStdEnc_HasMSA, // BSET_W |
| 11957 | CEFBS_HasStdEnc_HasMSA, // BZ_B |
| 11958 | CEFBS_HasStdEnc_HasMSA, // BZ_D |
| 11959 | CEFBS_HasStdEnc_HasMSA, // BZ_H |
| 11960 | CEFBS_HasStdEnc_HasMSA, // BZ_V |
| 11961 | CEFBS_HasStdEnc_HasMSA, // BZ_W |
| 11962 | CEFBS_InMips16Mode, // BeqzRxImm16 |
| 11963 | CEFBS_InMips16Mode, // BeqzRxImmX16 |
| 11964 | CEFBS_InMips16Mode, // Bimm16 |
| 11965 | CEFBS_InMips16Mode, // BimmX16 |
| 11966 | CEFBS_InMips16Mode, // BnezRxImm16 |
| 11967 | CEFBS_InMips16Mode, // BnezRxImmX16 |
| 11968 | CEFBS_InMips16Mode, // Break16 |
| 11969 | CEFBS_InMips16Mode, // Bteqz16 |
| 11970 | CEFBS_InMips16Mode, // BteqzX16 |
| 11971 | CEFBS_InMips16Mode, // Btnez16 |
| 11972 | CEFBS_InMips16Mode, // BtnezX16 |
| 11973 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE |
| 11974 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE |
| 11975 | CEFBS_InMicroMips_HasEVA, // CACHEE_MM |
| 11976 | CEFBS_InMicroMips_NotMips32r6, // CACHE_MM |
| 11977 | CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 |
| 11978 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 |
| 11979 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 |
| 11980 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 |
| 11981 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S |
| 11982 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 |
| 11983 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 |
| 11984 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 |
| 11985 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 |
| 11986 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CEIL_W_MM |
| 11987 | CEFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S |
| 11988 | CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM |
| 11989 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 |
| 11990 | CEFBS_HasStdEnc_HasMSA, // CEQI_B |
| 11991 | CEFBS_HasStdEnc_HasMSA, // CEQI_D |
| 11992 | CEFBS_HasStdEnc_HasMSA, // CEQI_H |
| 11993 | CEFBS_HasStdEnc_HasMSA, // CEQI_W |
| 11994 | CEFBS_HasStdEnc_HasMSA, // CEQ_B |
| 11995 | CEFBS_HasStdEnc_HasMSA, // CEQ_D |
| 11996 | CEFBS_HasStdEnc_HasMSA, // CEQ_H |
| 11997 | CEFBS_HasStdEnc_HasMSA, // CEQ_W |
| 11998 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 |
| 11999 | CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM |
| 12000 | CEFBS_InMicroMips, // CFC2_MM |
| 12001 | CEFBS_HasStdEnc_HasMSA, // CFCMSA |
| 12002 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS |
| 12003 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 |
| 12004 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 |
| 12005 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 |
| 12006 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D |
| 12007 | CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 |
| 12008 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S |
| 12009 | CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 |
| 12010 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_B |
| 12011 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_D |
| 12012 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_H |
| 12013 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_W |
| 12014 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_B |
| 12015 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_D |
| 12016 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_H |
| 12017 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_W |
| 12018 | CEFBS_HasStdEnc_HasMSA, // CLE_S_B |
| 12019 | CEFBS_HasStdEnc_HasMSA, // CLE_S_D |
| 12020 | CEFBS_HasStdEnc_HasMSA, // CLE_S_H |
| 12021 | CEFBS_HasStdEnc_HasMSA, // CLE_S_W |
| 12022 | CEFBS_HasStdEnc_HasMSA, // CLE_U_B |
| 12023 | CEFBS_HasStdEnc_HasMSA, // CLE_U_D |
| 12024 | CEFBS_HasStdEnc_HasMSA, // CLE_U_H |
| 12025 | CEFBS_HasStdEnc_HasMSA, // CLE_U_W |
| 12026 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO |
| 12027 | CEFBS_InMicroMips, // CLO_MM |
| 12028 | CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 |
| 12029 | CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 |
| 12030 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_B |
| 12031 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_D |
| 12032 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_H |
| 12033 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_W |
| 12034 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_B |
| 12035 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_D |
| 12036 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_H |
| 12037 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_W |
| 12038 | CEFBS_HasStdEnc_HasMSA, // CLT_S_B |
| 12039 | CEFBS_HasStdEnc_HasMSA, // CLT_S_D |
| 12040 | CEFBS_HasStdEnc_HasMSA, // CLT_S_H |
| 12041 | CEFBS_HasStdEnc_HasMSA, // CLT_S_W |
| 12042 | CEFBS_HasStdEnc_HasMSA, // CLT_U_B |
| 12043 | CEFBS_HasStdEnc_HasMSA, // CLT_U_D |
| 12044 | CEFBS_HasStdEnc_HasMSA, // CLT_U_H |
| 12045 | CEFBS_HasStdEnc_HasMSA, // CLT_U_W |
| 12046 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ |
| 12047 | CEFBS_InMicroMips, // CLZ_MM |
| 12048 | CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 |
| 12049 | CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 |
| 12050 | CEFBS_HasDSPR2, // CMPGDU_EQ_QB |
| 12051 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 |
| 12052 | CEFBS_HasDSPR2, // CMPGDU_LE_QB |
| 12053 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 |
| 12054 | CEFBS_HasDSPR2, // CMPGDU_LT_QB |
| 12055 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 |
| 12056 | CEFBS_HasDSP, // CMPGU_EQ_QB |
| 12057 | CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM |
| 12058 | CEFBS_HasDSP, // CMPGU_LE_QB |
| 12059 | CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM |
| 12060 | CEFBS_HasDSP, // CMPGU_LT_QB |
| 12061 | CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM |
| 12062 | CEFBS_HasDSP, // CMPU_EQ_QB |
| 12063 | CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM |
| 12064 | CEFBS_HasDSP, // CMPU_LE_QB |
| 12065 | CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM |
| 12066 | CEFBS_HasDSP, // CMPU_LT_QB |
| 12067 | CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM |
| 12068 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 |
| 12069 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 |
| 12070 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D |
| 12071 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 |
| 12072 | CEFBS_HasDSP, // CMP_EQ_PH |
| 12073 | CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM |
| 12074 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S |
| 12075 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 |
| 12076 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D |
| 12077 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S |
| 12078 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D |
| 12079 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 |
| 12080 | CEFBS_HasDSP, // CMP_LE_PH |
| 12081 | CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM |
| 12082 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S |
| 12083 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 |
| 12084 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D |
| 12085 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 |
| 12086 | CEFBS_HasDSP, // CMP_LT_PH |
| 12087 | CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM |
| 12088 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S |
| 12089 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 |
| 12090 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D |
| 12091 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 |
| 12092 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S |
| 12093 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 |
| 12094 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D |
| 12095 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 |
| 12096 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S |
| 12097 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 |
| 12098 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D |
| 12099 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 |
| 12100 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S |
| 12101 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 |
| 12102 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D |
| 12103 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 |
| 12104 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S |
| 12105 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 |
| 12106 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D |
| 12107 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 |
| 12108 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S |
| 12109 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 |
| 12110 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D |
| 12111 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 |
| 12112 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S |
| 12113 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 |
| 12114 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D |
| 12115 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 |
| 12116 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S |
| 12117 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 |
| 12118 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D |
| 12119 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 |
| 12120 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S |
| 12121 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 |
| 12122 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D |
| 12123 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 |
| 12124 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S |
| 12125 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 |
| 12126 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D |
| 12127 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 |
| 12128 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S |
| 12129 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 |
| 12130 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D |
| 12131 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 |
| 12132 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S |
| 12133 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 |
| 12134 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D |
| 12135 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 |
| 12136 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S |
| 12137 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 |
| 12138 | CEFBS_HasStdEnc_HasMSA, // COPY_S_B |
| 12139 | CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D |
| 12140 | CEFBS_HasStdEnc_HasMSA, // COPY_S_H |
| 12141 | CEFBS_HasStdEnc_HasMSA, // COPY_S_W |
| 12142 | CEFBS_HasStdEnc_HasMSA, // COPY_U_B |
| 12143 | CEFBS_HasStdEnc_HasMSA, // COPY_U_H |
| 12144 | CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W |
| 12145 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B |
| 12146 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB |
| 12147 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD |
| 12148 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH |
| 12149 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW |
| 12150 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D |
| 12151 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H |
| 12152 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W |
| 12153 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 |
| 12154 | CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM |
| 12155 | CEFBS_InMicroMips, // CTC2_MM |
| 12156 | CEFBS_HasStdEnc_HasMSA, // CTCMSA |
| 12157 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S |
| 12158 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_D32_S_MM |
| 12159 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W |
| 12160 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_D32_W_MM |
| 12161 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L |
| 12162 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S |
| 12163 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_D64_S_MM |
| 12164 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W |
| 12165 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_D64_W_MM |
| 12166 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 |
| 12167 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 |
| 12168 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_L_D64_MM |
| 12169 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 |
| 12170 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S |
| 12171 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_L_S_MM |
| 12172 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 |
| 12173 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 |
| 12174 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 |
| 12175 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 |
| 12176 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 |
| 12177 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_S_D32_MM |
| 12178 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 |
| 12179 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_S_D64_MM |
| 12180 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L |
| 12181 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 |
| 12182 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 |
| 12183 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 |
| 12184 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W |
| 12185 | CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM |
| 12186 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 |
| 12187 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 |
| 12188 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_W_D32_MM |
| 12189 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 |
| 12190 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // CVT_W_D64_MM |
| 12191 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S |
| 12192 | CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM |
| 12193 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 |
| 12194 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 |
| 12195 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM |
| 12196 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 |
| 12197 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM |
| 12198 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S |
| 12199 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM |
| 12200 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 |
| 12201 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM |
| 12202 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 |
| 12203 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM |
| 12204 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S |
| 12205 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM |
| 12206 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 |
| 12207 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM |
| 12208 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 |
| 12209 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM |
| 12210 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_LE_S |
| 12211 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM |
| 12212 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 |
| 12213 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM |
| 12214 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 |
| 12215 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM |
| 12216 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_LT_S |
| 12217 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM |
| 12218 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 |
| 12219 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM |
| 12220 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 |
| 12221 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM |
| 12222 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_NGE_S |
| 12223 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM |
| 12224 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 |
| 12225 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM |
| 12226 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 |
| 12227 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM |
| 12228 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S |
| 12229 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM |
| 12230 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 |
| 12231 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM |
| 12232 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 |
| 12233 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM |
| 12234 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_NGL_S |
| 12235 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM |
| 12236 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 |
| 12237 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM |
| 12238 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 |
| 12239 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM |
| 12240 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_NGT_S |
| 12241 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM |
| 12242 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 |
| 12243 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM |
| 12244 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 |
| 12245 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM |
| 12246 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S |
| 12247 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM |
| 12248 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 |
| 12249 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM |
| 12250 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 |
| 12251 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM |
| 12252 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S |
| 12253 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM |
| 12254 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 |
| 12255 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM |
| 12256 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 |
| 12257 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM |
| 12258 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S |
| 12259 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM |
| 12260 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 |
| 12261 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM |
| 12262 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 |
| 12263 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM |
| 12264 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_SF_S |
| 12265 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM |
| 12266 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 |
| 12267 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM |
| 12268 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 |
| 12269 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM |
| 12270 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S |
| 12271 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM |
| 12272 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 |
| 12273 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM |
| 12274 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 |
| 12275 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM |
| 12276 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_ULE_S |
| 12277 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM |
| 12278 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 |
| 12279 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM |
| 12280 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 |
| 12281 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM |
| 12282 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_ULT_S |
| 12283 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM |
| 12284 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 |
| 12285 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM |
| 12286 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 |
| 12287 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM |
| 12288 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, // C_UN_S |
| 12289 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM |
| 12290 | CEFBS_InMips16Mode, // CmpRxRy16 |
| 12291 | CEFBS_InMips16Mode, // CmpiRxImm16 |
| 12292 | CEFBS_InMips16Mode, // CmpiRxImmX16 |
| 12293 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD |
| 12294 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi |
| 12295 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu |
| 12296 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu |
| 12297 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI |
| 12298 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN |
| 12299 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI |
| 12300 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI |
| 12301 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP |
| 12302 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO |
| 12303 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 |
| 12304 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ |
| 12305 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 |
| 12306 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV |
| 12307 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU |
| 12308 | CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET |
| 12309 | CEFBS_InMicroMips, // DERET_MM |
| 12310 | CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 |
| 12311 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT |
| 12312 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 |
| 12313 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM |
| 12314 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU |
| 12315 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI |
| 12316 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS |
| 12317 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM |
| 12318 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU |
| 12319 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV |
| 12320 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU |
| 12321 | CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 |
| 12322 | CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 |
| 12323 | CEFBS_HasStdEnc_HasMSA, // DIV_S_B |
| 12324 | CEFBS_HasStdEnc_HasMSA, // DIV_S_D |
| 12325 | CEFBS_HasStdEnc_HasMSA, // DIV_S_H |
| 12326 | CEFBS_HasStdEnc_HasMSA, // DIV_S_W |
| 12327 | CEFBS_HasStdEnc_HasMSA, // DIV_U_B |
| 12328 | CEFBS_HasStdEnc_HasMSA, // DIV_U_D |
| 12329 | CEFBS_HasStdEnc_HasMSA, // DIV_U_H |
| 12330 | CEFBS_HasStdEnc_HasMSA, // DIV_U_W |
| 12331 | CEFBS_InMicroMips, // DI_MM |
| 12332 | CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 |
| 12333 | CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA |
| 12334 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 |
| 12335 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 |
| 12336 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat, // DMFC1 |
| 12337 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 |
| 12338 | CEFBS_HasCnMips, // DMFC2_OCTEON |
| 12339 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 |
| 12340 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD |
| 12341 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU |
| 12342 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT |
| 12343 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 |
| 12344 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat, // DMTC1 |
| 12345 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 |
| 12346 | CEFBS_HasCnMips, // DMTC2_OCTEON |
| 12347 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 |
| 12348 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH |
| 12349 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU |
| 12350 | CEFBS_HasCnMips, // DMUL |
| 12351 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DMULT |
| 12352 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DMULTu |
| 12353 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU |
| 12354 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 |
| 12355 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_D |
| 12356 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_H |
| 12357 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_W |
| 12358 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_D |
| 12359 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_H |
| 12360 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_W |
| 12361 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_D |
| 12362 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_H |
| 12363 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_W |
| 12364 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_D |
| 12365 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_H |
| 12366 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_W |
| 12367 | CEFBS_HasDSPR2, // DPAQX_SA_W_PH |
| 12368 | CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 |
| 12369 | CEFBS_HasDSPR2, // DPAQX_S_W_PH |
| 12370 | CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 |
| 12371 | CEFBS_HasDSP, // DPAQ_SA_L_W |
| 12372 | CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM |
| 12373 | CEFBS_HasDSP, // DPAQ_S_W_PH |
| 12374 | CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM |
| 12375 | CEFBS_HasDSP, // DPAU_H_QBL |
| 12376 | CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM |
| 12377 | CEFBS_HasDSP, // DPAU_H_QBR |
| 12378 | CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM |
| 12379 | CEFBS_HasDSPR2, // DPAX_W_PH |
| 12380 | CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 |
| 12381 | CEFBS_HasDSPR2, // DPA_W_PH |
| 12382 | CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 |
| 12383 | CEFBS_HasCnMips, // DPOP |
| 12384 | CEFBS_HasDSPR2, // DPSQX_SA_W_PH |
| 12385 | CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 |
| 12386 | CEFBS_HasDSPR2, // DPSQX_S_W_PH |
| 12387 | CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 |
| 12388 | CEFBS_HasDSP, // DPSQ_SA_L_W |
| 12389 | CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM |
| 12390 | CEFBS_HasDSP, // DPSQ_S_W_PH |
| 12391 | CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM |
| 12392 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D |
| 12393 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H |
| 12394 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W |
| 12395 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D |
| 12396 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H |
| 12397 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W |
| 12398 | CEFBS_HasDSP, // DPSU_H_QBL |
| 12399 | CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM |
| 12400 | CEFBS_HasDSP, // DPSU_H_QBR |
| 12401 | CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM |
| 12402 | CEFBS_HasDSPR2, // DPSX_W_PH |
| 12403 | CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 |
| 12404 | CEFBS_HasDSPR2, // DPS_W_PH |
| 12405 | CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 |
| 12406 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR |
| 12407 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 |
| 12408 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV |
| 12409 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH |
| 12410 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSDIV |
| 12411 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD |
| 12412 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL |
| 12413 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 |
| 12414 | CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 |
| 12415 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV |
| 12416 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA |
| 12417 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 |
| 12418 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV |
| 12419 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL |
| 12420 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 |
| 12421 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV |
| 12422 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB |
| 12423 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu |
| 12424 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DUDIV |
| 12425 | CEFBS_HasStdEnc_HasMips32r6, // DVP |
| 12426 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE |
| 12427 | CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 |
| 12428 | CEFBS_InMips16Mode, // DivRxRy16 |
| 12429 | CEFBS_InMips16Mode, // DivuRxRy16 |
| 12430 | CEFBS_HasStdEnc_NotInMicroMips, // EHB |
| 12431 | CEFBS_InMicroMips, // EHB_MM |
| 12432 | CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 |
| 12433 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI |
| 12434 | CEFBS_InMicroMips, // EI_MM |
| 12435 | CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 |
| 12436 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT |
| 12437 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET |
| 12438 | CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC |
| 12439 | CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 |
| 12440 | CEFBS_InMicroMips, // ERET_MM |
| 12441 | CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 |
| 12442 | CEFBS_HasStdEnc_HasMips32r6, // EVP |
| 12443 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE |
| 12444 | CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 |
| 12445 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT |
| 12446 | CEFBS_HasDSP, // EXTP |
| 12447 | CEFBS_HasDSP, // EXTPDP |
| 12448 | CEFBS_HasDSP, // EXTPDPV |
| 12449 | CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM |
| 12450 | CEFBS_InMicroMips_HasDSP, // EXTPDP_MM |
| 12451 | CEFBS_HasDSP, // EXTPV |
| 12452 | CEFBS_InMicroMips_HasDSP, // EXTPV_MM |
| 12453 | CEFBS_InMicroMips_HasDSP, // EXTP_MM |
| 12454 | CEFBS_HasDSP, // EXTRV_RS_W |
| 12455 | CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM |
| 12456 | CEFBS_HasDSP, // EXTRV_R_W |
| 12457 | CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM |
| 12458 | CEFBS_HasDSP, // EXTRV_S_H |
| 12459 | CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM |
| 12460 | CEFBS_HasDSP, // EXTRV_W |
| 12461 | CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM |
| 12462 | CEFBS_HasDSP, // EXTR_RS_W |
| 12463 | CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM |
| 12464 | CEFBS_HasDSP, // EXTR_R_W |
| 12465 | CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM |
| 12466 | CEFBS_HasDSP, // EXTR_S_H |
| 12467 | CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM |
| 12468 | CEFBS_HasDSP, // EXTR_W |
| 12469 | CEFBS_InMicroMips_HasDSP, // EXTR_W_MM |
| 12470 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS |
| 12471 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 |
| 12472 | CEFBS_InMicroMips_NotMips32r6, // EXT_MM |
| 12473 | CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 |
| 12474 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FABS_D32 |
| 12475 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FABS_D32_MM |
| 12476 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FABS_D64 |
| 12477 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FABS_D64_MM |
| 12478 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S |
| 12479 | CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM |
| 12480 | CEFBS_HasStdEnc_HasMSA, // FADD_D |
| 12481 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FADD_D32 |
| 12482 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FADD_D32_MM |
| 12483 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FADD_D64 |
| 12484 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FADD_D64_MM |
| 12485 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 |
| 12486 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S |
| 12487 | CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM |
| 12488 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 |
| 12489 | CEFBS_HasStdEnc_HasMSA, // FADD_W |
| 12490 | CEFBS_HasStdEnc_HasMSA, // FCAF_D |
| 12491 | CEFBS_HasStdEnc_HasMSA, // FCAF_W |
| 12492 | CEFBS_HasStdEnc_HasMSA, // FCEQ_D |
| 12493 | CEFBS_HasStdEnc_HasMSA, // FCEQ_W |
| 12494 | CEFBS_HasStdEnc_HasMSA, // FCLASS_D |
| 12495 | CEFBS_HasStdEnc_HasMSA, // FCLASS_W |
| 12496 | CEFBS_HasStdEnc_HasMSA, // FCLE_D |
| 12497 | CEFBS_HasStdEnc_HasMSA, // FCLE_W |
| 12498 | CEFBS_HasStdEnc_HasMSA, // FCLT_D |
| 12499 | CEFBS_HasStdEnc_HasMSA, // FCLT_W |
| 12500 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 |
| 12501 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM |
| 12502 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 |
| 12503 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 |
| 12504 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM |
| 12505 | CEFBS_HasStdEnc_HasMSA, // FCNE_D |
| 12506 | CEFBS_HasStdEnc_HasMSA, // FCNE_W |
| 12507 | CEFBS_HasStdEnc_HasMSA, // FCOR_D |
| 12508 | CEFBS_HasStdEnc_HasMSA, // FCOR_W |
| 12509 | CEFBS_HasStdEnc_HasMSA, // FCUEQ_D |
| 12510 | CEFBS_HasStdEnc_HasMSA, // FCUEQ_W |
| 12511 | CEFBS_HasStdEnc_HasMSA, // FCULE_D |
| 12512 | CEFBS_HasStdEnc_HasMSA, // FCULE_W |
| 12513 | CEFBS_HasStdEnc_HasMSA, // FCULT_D |
| 12514 | CEFBS_HasStdEnc_HasMSA, // FCULT_W |
| 12515 | CEFBS_HasStdEnc_HasMSA, // FCUNE_D |
| 12516 | CEFBS_HasStdEnc_HasMSA, // FCUNE_W |
| 12517 | CEFBS_HasStdEnc_HasMSA, // FCUN_D |
| 12518 | CEFBS_HasStdEnc_HasMSA, // FCUN_W |
| 12519 | CEFBS_HasStdEnc_HasMSA, // FDIV_D |
| 12520 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 |
| 12521 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FDIV_D32_MM |
| 12522 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 |
| 12523 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FDIV_D64_MM |
| 12524 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S |
| 12525 | CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM |
| 12526 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 |
| 12527 | CEFBS_HasStdEnc_HasMSA, // FDIV_W |
| 12528 | CEFBS_HasStdEnc_HasMSA, // FEXDO_H |
| 12529 | CEFBS_HasStdEnc_HasMSA, // FEXDO_W |
| 12530 | CEFBS_HasStdEnc_HasMSA, // FEXP2_D |
| 12531 | CEFBS_HasStdEnc_HasMSA, // FEXP2_W |
| 12532 | CEFBS_HasStdEnc_HasMSA, // FEXUPL_D |
| 12533 | CEFBS_HasStdEnc_HasMSA, // FEXUPL_W |
| 12534 | CEFBS_HasStdEnc_HasMSA, // FEXUPR_D |
| 12535 | CEFBS_HasStdEnc_HasMSA, // FEXUPR_W |
| 12536 | CEFBS_HasStdEnc_HasMSA, // FFINT_S_D |
| 12537 | CEFBS_HasStdEnc_HasMSA, // FFINT_S_W |
| 12538 | CEFBS_HasStdEnc_HasMSA, // FFINT_U_D |
| 12539 | CEFBS_HasStdEnc_HasMSA, // FFINT_U_W |
| 12540 | CEFBS_HasStdEnc_HasMSA, // FFQL_D |
| 12541 | CEFBS_HasStdEnc_HasMSA, // FFQL_W |
| 12542 | CEFBS_HasStdEnc_HasMSA, // FFQR_D |
| 12543 | CEFBS_HasStdEnc_HasMSA, // FFQR_W |
| 12544 | CEFBS_HasStdEnc_HasMSA, // FILL_B |
| 12545 | CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D |
| 12546 | CEFBS_HasStdEnc_HasMSA, // FILL_H |
| 12547 | CEFBS_HasStdEnc_HasMSA, // FILL_W |
| 12548 | CEFBS_HasStdEnc_HasMSA, // FLOG2_D |
| 12549 | CEFBS_HasStdEnc_HasMSA, // FLOG2_W |
| 12550 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 |
| 12551 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 |
| 12552 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S |
| 12553 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 |
| 12554 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 |
| 12555 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 |
| 12556 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 |
| 12557 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FLOOR_W_MM |
| 12558 | CEFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S |
| 12559 | CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM |
| 12560 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 |
| 12561 | CEFBS_HasStdEnc_HasMSA, // FMADD_D |
| 12562 | CEFBS_HasStdEnc_HasMSA, // FMADD_W |
| 12563 | CEFBS_HasStdEnc_HasMSA, // FMAX_A_D |
| 12564 | CEFBS_HasStdEnc_HasMSA, // FMAX_A_W |
| 12565 | CEFBS_HasStdEnc_HasMSA, // FMAX_D |
| 12566 | CEFBS_HasStdEnc_HasMSA, // FMAX_W |
| 12567 | CEFBS_HasStdEnc_HasMSA, // FMIN_A_D |
| 12568 | CEFBS_HasStdEnc_HasMSA, // FMIN_A_W |
| 12569 | CEFBS_HasStdEnc_HasMSA, // FMIN_D |
| 12570 | CEFBS_HasStdEnc_HasMSA, // FMIN_W |
| 12571 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 |
| 12572 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FMOV_D32_MM |
| 12573 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 |
| 12574 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FMOV_D64_MM |
| 12575 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 |
| 12576 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S |
| 12577 | CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM |
| 12578 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 |
| 12579 | CEFBS_HasStdEnc_HasMSA, // FMSUB_D |
| 12580 | CEFBS_HasStdEnc_HasMSA, // FMSUB_W |
| 12581 | CEFBS_HasStdEnc_HasMSA, // FMUL_D |
| 12582 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 |
| 12583 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FMUL_D32_MM |
| 12584 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 |
| 12585 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FMUL_D64_MM |
| 12586 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 |
| 12587 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S |
| 12588 | CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM |
| 12589 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 |
| 12590 | CEFBS_HasStdEnc_HasMSA, // FMUL_W |
| 12591 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 |
| 12592 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FNEG_D32_MM |
| 12593 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 |
| 12594 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FNEG_D64_MM |
| 12595 | CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S |
| 12596 | CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM |
| 12597 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 |
| 12598 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK |
| 12599 | CEFBS_HasStdEnc_HasMSA, // FRCP_D |
| 12600 | CEFBS_HasStdEnc_HasMSA, // FRCP_W |
| 12601 | CEFBS_HasStdEnc_HasMSA, // FRINT_D |
| 12602 | CEFBS_HasStdEnc_HasMSA, // FRINT_W |
| 12603 | CEFBS_HasStdEnc_HasMSA, // FRSQRT_D |
| 12604 | CEFBS_HasStdEnc_HasMSA, // FRSQRT_W |
| 12605 | CEFBS_HasStdEnc_HasMSA, // FSAF_D |
| 12606 | CEFBS_HasStdEnc_HasMSA, // FSAF_W |
| 12607 | CEFBS_HasStdEnc_HasMSA, // FSEQ_D |
| 12608 | CEFBS_HasStdEnc_HasMSA, // FSEQ_W |
| 12609 | CEFBS_HasStdEnc_HasMSA, // FSLE_D |
| 12610 | CEFBS_HasStdEnc_HasMSA, // FSLE_W |
| 12611 | CEFBS_HasStdEnc_HasMSA, // FSLT_D |
| 12612 | CEFBS_HasStdEnc_HasMSA, // FSLT_W |
| 12613 | CEFBS_HasStdEnc_HasMSA, // FSNE_D |
| 12614 | CEFBS_HasStdEnc_HasMSA, // FSNE_W |
| 12615 | CEFBS_HasStdEnc_HasMSA, // FSOR_D |
| 12616 | CEFBS_HasStdEnc_HasMSA, // FSOR_W |
| 12617 | CEFBS_HasStdEnc_HasMSA, // FSQRT_D |
| 12618 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 |
| 12619 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FSQRT_D32_MM |
| 12620 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 |
| 12621 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FSQRT_D64_MM |
| 12622 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S |
| 12623 | CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM |
| 12624 | CEFBS_HasStdEnc_HasMSA, // FSQRT_W |
| 12625 | CEFBS_HasStdEnc_HasMSA, // FSUB_D |
| 12626 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 |
| 12627 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FSUB_D32_MM |
| 12628 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 |
| 12629 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // FSUB_D64_MM |
| 12630 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 |
| 12631 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S |
| 12632 | CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM |
| 12633 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 |
| 12634 | CEFBS_HasStdEnc_HasMSA, // FSUB_W |
| 12635 | CEFBS_HasStdEnc_HasMSA, // FSUEQ_D |
| 12636 | CEFBS_HasStdEnc_HasMSA, // FSUEQ_W |
| 12637 | CEFBS_HasStdEnc_HasMSA, // FSULE_D |
| 12638 | CEFBS_HasStdEnc_HasMSA, // FSULE_W |
| 12639 | CEFBS_HasStdEnc_HasMSA, // FSULT_D |
| 12640 | CEFBS_HasStdEnc_HasMSA, // FSULT_W |
| 12641 | CEFBS_HasStdEnc_HasMSA, // FSUNE_D |
| 12642 | CEFBS_HasStdEnc_HasMSA, // FSUNE_W |
| 12643 | CEFBS_HasStdEnc_HasMSA, // FSUN_D |
| 12644 | CEFBS_HasStdEnc_HasMSA, // FSUN_W |
| 12645 | CEFBS_HasStdEnc_HasMSA, // FTINT_S_D |
| 12646 | CEFBS_HasStdEnc_HasMSA, // FTINT_S_W |
| 12647 | CEFBS_HasStdEnc_HasMSA, // FTINT_U_D |
| 12648 | CEFBS_HasStdEnc_HasMSA, // FTINT_U_W |
| 12649 | CEFBS_HasStdEnc_HasMSA, // FTQ_H |
| 12650 | CEFBS_HasStdEnc_HasMSA, // FTQ_W |
| 12651 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D |
| 12652 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W |
| 12653 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D |
| 12654 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W |
| 12655 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI |
| 12656 | CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 |
| 12657 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT |
| 12658 | CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 |
| 12659 | CEFBS_HasStdEnc_HasMSA, // HADD_S_D |
| 12660 | CEFBS_HasStdEnc_HasMSA, // HADD_S_H |
| 12661 | CEFBS_HasStdEnc_HasMSA, // HADD_S_W |
| 12662 | CEFBS_HasStdEnc_HasMSA, // HADD_U_D |
| 12663 | CEFBS_HasStdEnc_HasMSA, // HADD_U_H |
| 12664 | CEFBS_HasStdEnc_HasMSA, // HADD_U_W |
| 12665 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_D |
| 12666 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_H |
| 12667 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_W |
| 12668 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_D |
| 12669 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_H |
| 12670 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_W |
| 12671 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL |
| 12672 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM |
| 12673 | CEFBS_HasStdEnc_HasMSA, // ILVEV_B |
| 12674 | CEFBS_HasStdEnc_HasMSA, // ILVEV_D |
| 12675 | CEFBS_HasStdEnc_HasMSA, // ILVEV_H |
| 12676 | CEFBS_HasStdEnc_HasMSA, // ILVEV_W |
| 12677 | CEFBS_HasStdEnc_HasMSA, // ILVL_B |
| 12678 | CEFBS_HasStdEnc_HasMSA, // ILVL_D |
| 12679 | CEFBS_HasStdEnc_HasMSA, // ILVL_H |
| 12680 | CEFBS_HasStdEnc_HasMSA, // ILVL_W |
| 12681 | CEFBS_HasStdEnc_HasMSA, // ILVOD_B |
| 12682 | CEFBS_HasStdEnc_HasMSA, // ILVOD_D |
| 12683 | CEFBS_HasStdEnc_HasMSA, // ILVOD_H |
| 12684 | CEFBS_HasStdEnc_HasMSA, // ILVOD_W |
| 12685 | CEFBS_HasStdEnc_HasMSA, // ILVR_B |
| 12686 | CEFBS_HasStdEnc_HasMSA, // ILVR_D |
| 12687 | CEFBS_HasStdEnc_HasMSA, // ILVR_H |
| 12688 | CEFBS_HasStdEnc_HasMSA, // ILVR_W |
| 12689 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS |
| 12690 | CEFBS_HasStdEnc_HasMSA, // INSERT_B |
| 12691 | CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D |
| 12692 | CEFBS_HasStdEnc_HasMSA, // INSERT_H |
| 12693 | CEFBS_HasStdEnc_HasMSA, // INSERT_W |
| 12694 | CEFBS_HasDSP, // INSV |
| 12695 | CEFBS_HasStdEnc_HasMSA, // INSVE_B |
| 12696 | CEFBS_HasStdEnc_HasMSA, // INSVE_D |
| 12697 | CEFBS_HasStdEnc_HasMSA, // INSVE_H |
| 12698 | CEFBS_HasStdEnc_HasMSA, // INSVE_W |
| 12699 | CEFBS_InMicroMips_HasDSP, // INSV_MM |
| 12700 | CEFBS_InMicroMips_NotMips32r6, // INS_MM |
| 12701 | CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 |
| 12702 | CEFBS_HasStdEnc_NotInMicroMips, // J |
| 12703 | CEFBS_HasStdEnc_NotInMicroMips, // JAL |
| 12704 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR |
| 12705 | CEFBS_InMicroMips_NotMips32r6, // JALR16_MM |
| 12706 | CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 |
| 12707 | CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 |
| 12708 | CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 |
| 12709 | CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 |
| 12710 | CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM |
| 12711 | CEFBS_InMicroMips_NotMips32r6, // JALRS_MM |
| 12712 | CEFBS_HasStdEnc_HasMips32, // JALR_HB |
| 12713 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 |
| 12714 | CEFBS_InMicroMips_NotMips32r6, // JALR_HB_MM |
| 12715 | CEFBS_InMicroMips_NotMips32r6, // JALR_MM |
| 12716 | CEFBS_InMicroMips_NotMips32r6, // JALS_MM |
| 12717 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX |
| 12718 | CEFBS_InMicroMips_NotMips32r6, // JALX_MM |
| 12719 | CEFBS_InMicroMips_NotMips32r6, // JAL_MM |
| 12720 | CEFBS_HasStdEnc_HasMips32r6, // JIALC |
| 12721 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 |
| 12722 | CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 |
| 12723 | CEFBS_HasStdEnc_HasMips32r6, // JIC |
| 12724 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 |
| 12725 | CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 |
| 12726 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR |
| 12727 | CEFBS_InMicroMips_NotMips32r6, // JR16_MM |
| 12728 | CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 |
| 12729 | CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP |
| 12730 | CEFBS_InMicroMips_NotMips32r6, // JRC16_MM |
| 12731 | CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 |
| 12732 | CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 |
| 12733 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB |
| 12734 | CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 |
| 12735 | CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 |
| 12736 | CEFBS_InMicroMips_NotMips32r6, // JR_HB_MM |
| 12737 | CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 |
| 12738 | CEFBS_InMicroMips_NotMips32r6, // JR_MM |
| 12739 | CEFBS_InMicroMips_NotMips32r6, // J_MM |
| 12740 | CEFBS_InMips16Mode, // Jal16 |
| 12741 | CEFBS_InMips16Mode, // JalB16 |
| 12742 | CEFBS_InMips16Mode, // JrRa16 |
| 12743 | CEFBS_InMips16Mode, // JrcRa16 |
| 12744 | CEFBS_InMips16Mode, // JrcRx16 |
| 12745 | CEFBS_InMips16Mode, // JumpLinkReg16 |
| 12746 | CEFBS_HasStdEnc_NotInMicroMips, // LB |
| 12747 | CEFBS_NotInMips16Mode_IsGP64bit, // LB64 |
| 12748 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE |
| 12749 | CEFBS_InMicroMips_HasEVA, // LBE_MM |
| 12750 | CEFBS_InMicroMips, // LBU16_MM |
| 12751 | CEFBS_HasDSP, // LBUX |
| 12752 | CEFBS_InMicroMips_HasDSP, // LBUX_MM |
| 12753 | CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 |
| 12754 | CEFBS_InMicroMips, // LB_MM |
| 12755 | CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 |
| 12756 | CEFBS_HasStdEnc_NotInMicroMips, // LBu |
| 12757 | CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 |
| 12758 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE |
| 12759 | CEFBS_InMicroMips_HasEVA, // LBuE_MM |
| 12760 | CEFBS_InMicroMips, // LBu_MM |
| 12761 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD |
| 12762 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 |
| 12763 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 |
| 12764 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 |
| 12765 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // LDC1_MM_D32 |
| 12766 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // LDC1_MM_D64 |
| 12767 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 |
| 12768 | CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 |
| 12769 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 |
| 12770 | CEFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, // LDC3 |
| 12771 | CEFBS_HasStdEnc_HasMSA, // LDI_B |
| 12772 | CEFBS_HasStdEnc_HasMSA, // LDI_D |
| 12773 | CEFBS_HasStdEnc_HasMSA, // LDI_H |
| 12774 | CEFBS_HasStdEnc_HasMSA, // LDI_W |
| 12775 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL |
| 12776 | CEFBS_HasStdEnc_HasMips64r6, // LDPC |
| 12777 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR |
| 12778 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 |
| 12779 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 |
| 12780 | CEFBS_HasStdEnc_HasMSA, // LD_B |
| 12781 | CEFBS_HasStdEnc_HasMSA, // LD_D |
| 12782 | CEFBS_HasStdEnc_HasMSA, // LD_H |
| 12783 | CEFBS_HasStdEnc_HasMSA, // LD_W |
| 12784 | CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu |
| 12785 | CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 |
| 12786 | CEFBS_InMicroMips, // LEA_ADDiu_MM |
| 12787 | CEFBS_HasStdEnc_NotInMicroMips, // LH |
| 12788 | CEFBS_NotInMips16Mode_IsGP64bit, // LH64 |
| 12789 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE |
| 12790 | CEFBS_InMicroMips_HasEVA, // LHE_MM |
| 12791 | CEFBS_InMicroMips, // LHU16_MM |
| 12792 | CEFBS_HasDSP, // LHX |
| 12793 | CEFBS_InMicroMips_HasDSP, // LHX_MM |
| 12794 | CEFBS_InMicroMips, // LH_MM |
| 12795 | CEFBS_HasStdEnc_NotInMicroMips, // LHu |
| 12796 | CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 |
| 12797 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE |
| 12798 | CEFBS_InMicroMips_HasEVA, // LHuE_MM |
| 12799 | CEFBS_InMicroMips, // LHu_MM |
| 12800 | CEFBS_InMicroMips_NotMips32r6, // LI16_MM |
| 12801 | CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 |
| 12802 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // LL |
| 12803 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // LL64 |
| 12804 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 |
| 12805 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // LLD |
| 12806 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 |
| 12807 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE |
| 12808 | CEFBS_InMicroMips_HasEVA, // LLE_MM |
| 12809 | CEFBS_InMicroMips_NotMips32r6, // LL_MM |
| 12810 | CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 |
| 12811 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 |
| 12812 | CEFBS_HasStdEnc_HasMSA, // LSA |
| 12813 | CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 |
| 12814 | CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 |
| 12815 | CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 |
| 12816 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 |
| 12817 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 |
| 12818 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // LUXC1_MM |
| 12819 | CEFBS_HasStdEnc_NotInMicroMips, // LUi |
| 12820 | CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 |
| 12821 | CEFBS_InMicroMips_NotMips32r6, // LUi_MM |
| 12822 | CEFBS_HasStdEnc_NotInMicroMips, // LW |
| 12823 | CEFBS_InMicroMips, // LW16_MM |
| 12824 | CEFBS_NotInMips16Mode_IsGP64bit, // LW64 |
| 12825 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 |
| 12826 | CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM |
| 12827 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 |
| 12828 | CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 |
| 12829 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 |
| 12830 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, // LWC3 |
| 12831 | CEFBS_NotInMips16Mode_HasDSP, // LWDSP |
| 12832 | CEFBS_InMicroMips_HasDSP, // LWDSP_MM |
| 12833 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE |
| 12834 | CEFBS_InMicroMips_HasEVA, // LWE_MM |
| 12835 | CEFBS_InMicroMips, // LWGP_MM |
| 12836 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL |
| 12837 | CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 |
| 12838 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE |
| 12839 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM |
| 12840 | CEFBS_InMicroMips_NotMips32r6, // LWL_MM |
| 12841 | CEFBS_InMicroMips_NotMips32r6, // LWM16_MM |
| 12842 | CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 |
| 12843 | CEFBS_InMicroMips, // LWM32_MM |
| 12844 | CEFBS_HasStdEnc_HasMips32r6, // LWPC |
| 12845 | CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 |
| 12846 | CEFBS_InMicroMips, // LWP_MM |
| 12847 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR |
| 12848 | CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 |
| 12849 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE |
| 12850 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM |
| 12851 | CEFBS_InMicroMips_NotMips32r6, // LWR_MM |
| 12852 | CEFBS_InMicroMips, // LWSP_MM |
| 12853 | CEFBS_HasStdEnc_HasMips64r6, // LWUPC |
| 12854 | CEFBS_InMicroMips_NotMips32r6, // LWU_MM |
| 12855 | CEFBS_HasDSP, // LWX |
| 12856 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 |
| 12857 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM |
| 12858 | CEFBS_InMicroMips, // LWXS_MM |
| 12859 | CEFBS_InMicroMips_HasDSP, // LWX_MM |
| 12860 | CEFBS_InMicroMips, // LW_MM |
| 12861 | CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 |
| 12862 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu |
| 12863 | CEFBS_InMips16Mode, // LbRxRyOffMemX16 |
| 12864 | CEFBS_InMips16Mode, // LbuRxRyOffMemX16 |
| 12865 | CEFBS_InMips16Mode, // LhRxRyOffMemX16 |
| 12866 | CEFBS_InMips16Mode, // LhuRxRyOffMemX16 |
| 12867 | CEFBS_InMips16Mode, // LiRxImm16 |
| 12868 | CEFBS_InMips16Mode, // LiRxImmAlignX16 |
| 12869 | CEFBS_InMips16Mode, // LiRxImmX16 |
| 12870 | CEFBS_InMips16Mode, // LwRxPcTcp16 |
| 12871 | CEFBS_InMips16Mode, // LwRxPcTcpX16 |
| 12872 | CEFBS_InMips16Mode, // LwRxRyOffMemX16 |
| 12873 | CEFBS_InMips16Mode, // LwRxSpImmX16 |
| 12874 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD |
| 12875 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D |
| 12876 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 |
| 12877 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S |
| 12878 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 |
| 12879 | CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H |
| 12880 | CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W |
| 12881 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU |
| 12882 | CEFBS_HasDSP, // MADDU_DSP |
| 12883 | CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM |
| 12884 | CEFBS_InMicroMips_NotMips32r6, // MADDU_MM |
| 12885 | CEFBS_HasStdEnc_HasMSA, // MADDV_B |
| 12886 | CEFBS_HasStdEnc_HasMSA, // MADDV_D |
| 12887 | CEFBS_HasStdEnc_HasMSA, // MADDV_H |
| 12888 | CEFBS_HasStdEnc_HasMSA, // MADDV_W |
| 12889 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 |
| 12890 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM |
| 12891 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 |
| 12892 | CEFBS_HasDSP, // MADD_DSP |
| 12893 | CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM |
| 12894 | CEFBS_InMicroMips_NotMips32r6, // MADD_MM |
| 12895 | CEFBS_HasStdEnc_HasMSA, // MADD_Q_H |
| 12896 | CEFBS_HasStdEnc_HasMSA, // MADD_Q_W |
| 12897 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S |
| 12898 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM |
| 12899 | CEFBS_HasDSP, // MAQ_SA_W_PHL |
| 12900 | CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM |
| 12901 | CEFBS_HasDSP, // MAQ_SA_W_PHR |
| 12902 | CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM |
| 12903 | CEFBS_HasDSP, // MAQ_S_W_PHL |
| 12904 | CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM |
| 12905 | CEFBS_HasDSP, // MAQ_S_W_PHR |
| 12906 | CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM |
| 12907 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D |
| 12908 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 |
| 12909 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S |
| 12910 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 |
| 12911 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_B |
| 12912 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_D |
| 12913 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_H |
| 12914 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_W |
| 12915 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_B |
| 12916 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_D |
| 12917 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_H |
| 12918 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_W |
| 12919 | CEFBS_HasStdEnc_HasMSA, // MAX_A_B |
| 12920 | CEFBS_HasStdEnc_HasMSA, // MAX_A_D |
| 12921 | CEFBS_HasStdEnc_HasMSA, // MAX_A_H |
| 12922 | CEFBS_HasStdEnc_HasMSA, // MAX_A_W |
| 12923 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D |
| 12924 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 |
| 12925 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S |
| 12926 | CEFBS_HasStdEnc_HasMSA, // MAX_S_B |
| 12927 | CEFBS_HasStdEnc_HasMSA, // MAX_S_D |
| 12928 | CEFBS_HasStdEnc_HasMSA, // MAX_S_H |
| 12929 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 |
| 12930 | CEFBS_HasStdEnc_HasMSA, // MAX_S_W |
| 12931 | CEFBS_HasStdEnc_HasMSA, // MAX_U_B |
| 12932 | CEFBS_HasStdEnc_HasMSA, // MAX_U_D |
| 12933 | CEFBS_HasStdEnc_HasMSA, // MAX_U_H |
| 12934 | CEFBS_HasStdEnc_HasMSA, // MAX_U_W |
| 12935 | CEFBS_HasStdEnc_NotInMicroMips, // MFC0 |
| 12936 | CEFBS_InMicroMips_NotMips32r6, // MFC0_MM |
| 12937 | CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 |
| 12938 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 |
| 12939 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 |
| 12940 | CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM |
| 12941 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 |
| 12942 | CEFBS_HasStdEnc_NotInMicroMips, // MFC2 |
| 12943 | CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 |
| 12944 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 |
| 12945 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM |
| 12946 | CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 |
| 12947 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 |
| 12948 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // MFHC1_D32_MM |
| 12949 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 |
| 12950 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // MFHC1_D64_MM |
| 12951 | CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 |
| 12952 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 |
| 12953 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM |
| 12954 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI |
| 12955 | CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM |
| 12956 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 |
| 12957 | CEFBS_HasDSP, // MFHI_DSP |
| 12958 | CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM |
| 12959 | CEFBS_InMicroMips_NotMips32r6, // MFHI_MM |
| 12960 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO |
| 12961 | CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM |
| 12962 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 |
| 12963 | CEFBS_HasDSP, // MFLO_DSP |
| 12964 | CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM |
| 12965 | CEFBS_InMicroMips_NotMips32r6, // MFLO_MM |
| 12966 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR |
| 12967 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D |
| 12968 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 |
| 12969 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S |
| 12970 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 |
| 12971 | CEFBS_HasStdEnc_HasMSA, // MINI_S_B |
| 12972 | CEFBS_HasStdEnc_HasMSA, // MINI_S_D |
| 12973 | CEFBS_HasStdEnc_HasMSA, // MINI_S_H |
| 12974 | CEFBS_HasStdEnc_HasMSA, // MINI_S_W |
| 12975 | CEFBS_HasStdEnc_HasMSA, // MINI_U_B |
| 12976 | CEFBS_HasStdEnc_HasMSA, // MINI_U_D |
| 12977 | CEFBS_HasStdEnc_HasMSA, // MINI_U_H |
| 12978 | CEFBS_HasStdEnc_HasMSA, // MINI_U_W |
| 12979 | CEFBS_HasStdEnc_HasMSA, // MIN_A_B |
| 12980 | CEFBS_HasStdEnc_HasMSA, // MIN_A_D |
| 12981 | CEFBS_HasStdEnc_HasMSA, // MIN_A_H |
| 12982 | CEFBS_HasStdEnc_HasMSA, // MIN_A_W |
| 12983 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D |
| 12984 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 |
| 12985 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S |
| 12986 | CEFBS_HasStdEnc_HasMSA, // MIN_S_B |
| 12987 | CEFBS_HasStdEnc_HasMSA, // MIN_S_D |
| 12988 | CEFBS_HasStdEnc_HasMSA, // MIN_S_H |
| 12989 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 |
| 12990 | CEFBS_HasStdEnc_HasMSA, // MIN_S_W |
| 12991 | CEFBS_HasStdEnc_HasMSA, // MIN_U_B |
| 12992 | CEFBS_HasStdEnc_HasMSA, // MIN_U_D |
| 12993 | CEFBS_HasStdEnc_HasMSA, // MIN_U_H |
| 12994 | CEFBS_HasStdEnc_HasMSA, // MIN_U_W |
| 12995 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD |
| 12996 | CEFBS_HasDSP, // MODSUB |
| 12997 | CEFBS_InMicroMips_HasDSP, // MODSUB_MM |
| 12998 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU |
| 12999 | CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 |
| 13000 | CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 |
| 13001 | CEFBS_HasStdEnc_HasMSA, // MOD_S_B |
| 13002 | CEFBS_HasStdEnc_HasMSA, // MOD_S_D |
| 13003 | CEFBS_HasStdEnc_HasMSA, // MOD_S_H |
| 13004 | CEFBS_HasStdEnc_HasMSA, // MOD_S_W |
| 13005 | CEFBS_HasStdEnc_HasMSA, // MOD_U_B |
| 13006 | CEFBS_HasStdEnc_HasMSA, // MOD_U_D |
| 13007 | CEFBS_HasStdEnc_HasMSA, // MOD_U_H |
| 13008 | CEFBS_HasStdEnc_HasMSA, // MOD_U_W |
| 13009 | CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM |
| 13010 | CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 |
| 13011 | CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM |
| 13012 | CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 |
| 13013 | CEFBS_HasStdEnc_HasMSA, // MOVE_V |
| 13014 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 |
| 13015 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM |
| 13016 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 |
| 13017 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I |
| 13018 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 |
| 13019 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM |
| 13020 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S |
| 13021 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM |
| 13022 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 |
| 13023 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I |
| 13024 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 |
| 13025 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S |
| 13026 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 |
| 13027 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM |
| 13028 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 |
| 13029 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I |
| 13030 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 |
| 13031 | CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM |
| 13032 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S |
| 13033 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM |
| 13034 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 |
| 13035 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM |
| 13036 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 |
| 13037 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I |
| 13038 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 |
| 13039 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM |
| 13040 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S |
| 13041 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM |
| 13042 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 |
| 13043 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I |
| 13044 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 |
| 13045 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S |
| 13046 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 |
| 13047 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM |
| 13048 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 |
| 13049 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I |
| 13050 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 |
| 13051 | CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM |
| 13052 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S |
| 13053 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM |
| 13054 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB |
| 13055 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D |
| 13056 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 |
| 13057 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S |
| 13058 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 |
| 13059 | CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H |
| 13060 | CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W |
| 13061 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU |
| 13062 | CEFBS_HasDSP, // MSUBU_DSP |
| 13063 | CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM |
| 13064 | CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM |
| 13065 | CEFBS_HasStdEnc_HasMSA, // MSUBV_B |
| 13066 | CEFBS_HasStdEnc_HasMSA, // MSUBV_D |
| 13067 | CEFBS_HasStdEnc_HasMSA, // MSUBV_H |
| 13068 | CEFBS_HasStdEnc_HasMSA, // MSUBV_W |
| 13069 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 |
| 13070 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM |
| 13071 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 |
| 13072 | CEFBS_HasDSP, // MSUB_DSP |
| 13073 | CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM |
| 13074 | CEFBS_InMicroMips_NotMips32r6, // MSUB_MM |
| 13075 | CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H |
| 13076 | CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W |
| 13077 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S |
| 13078 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM |
| 13079 | CEFBS_HasStdEnc_NotInMicroMips, // MTC0 |
| 13080 | CEFBS_InMicroMips_NotMips32r6, // MTC0_MM |
| 13081 | CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 |
| 13082 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 |
| 13083 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 |
| 13084 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // MTC1_D64_MM |
| 13085 | CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM |
| 13086 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 |
| 13087 | CEFBS_HasStdEnc_NotInMicroMips, // MTC2 |
| 13088 | CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 |
| 13089 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 |
| 13090 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM |
| 13091 | CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 |
| 13092 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 |
| 13093 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // MTHC1_D32_MM |
| 13094 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 |
| 13095 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // MTHC1_D64_MM |
| 13096 | CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 |
| 13097 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 |
| 13098 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM |
| 13099 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI |
| 13100 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 |
| 13101 | CEFBS_HasDSP, // MTHI_DSP |
| 13102 | CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM |
| 13103 | CEFBS_InMicroMips_NotMips32r6, // MTHI_MM |
| 13104 | CEFBS_HasDSP, // MTHLIP |
| 13105 | CEFBS_InMicroMips_HasDSP, // MTHLIP_MM |
| 13106 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO |
| 13107 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 |
| 13108 | CEFBS_HasDSP, // MTLO_DSP |
| 13109 | CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM |
| 13110 | CEFBS_InMicroMips_NotMips32r6, // MTLO_MM |
| 13111 | CEFBS_HasCnMips, // MTM0 |
| 13112 | CEFBS_HasCnMips, // MTM1 |
| 13113 | CEFBS_HasCnMips, // MTM2 |
| 13114 | CEFBS_HasCnMips, // MTP0 |
| 13115 | CEFBS_HasCnMips, // MTP1 |
| 13116 | CEFBS_HasCnMips, // MTP2 |
| 13117 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR |
| 13118 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH |
| 13119 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU |
| 13120 | CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 |
| 13121 | CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 |
| 13122 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL |
| 13123 | CEFBS_HasDSP, // MULEQ_S_W_PHL |
| 13124 | CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM |
| 13125 | CEFBS_HasDSP, // MULEQ_S_W_PHR |
| 13126 | CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM |
| 13127 | CEFBS_HasDSP, // MULEU_S_PH_QBL |
| 13128 | CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM |
| 13129 | CEFBS_HasDSP, // MULEU_S_PH_QBR |
| 13130 | CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM |
| 13131 | CEFBS_HasDSP, // MULQ_RS_PH |
| 13132 | CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM |
| 13133 | CEFBS_HasDSPR2, // MULQ_RS_W |
| 13134 | CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 |
| 13135 | CEFBS_HasDSPR2, // MULQ_S_PH |
| 13136 | CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 |
| 13137 | CEFBS_HasDSPR2, // MULQ_S_W |
| 13138 | CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 |
| 13139 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 |
| 13140 | CEFBS_HasStdEnc_HasMSA, // MULR_Q_H |
| 13141 | CEFBS_HasStdEnc_HasMSA, // MULR_Q_W |
| 13142 | CEFBS_HasDSP, // MULSAQ_S_W_PH |
| 13143 | CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM |
| 13144 | CEFBS_HasDSPR2, // MULSA_W_PH |
| 13145 | CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 |
| 13146 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT |
| 13147 | CEFBS_HasDSP, // MULTU_DSP |
| 13148 | CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM |
| 13149 | CEFBS_HasDSP, // MULT_DSP |
| 13150 | CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM |
| 13151 | CEFBS_InMicroMips_NotMips32r6, // MULT_MM |
| 13152 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu |
| 13153 | CEFBS_InMicroMips_NotMips32r6, // MULTu_MM |
| 13154 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU |
| 13155 | CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 |
| 13156 | CEFBS_HasStdEnc_HasMSA, // MULV_B |
| 13157 | CEFBS_HasStdEnc_HasMSA, // MULV_D |
| 13158 | CEFBS_HasStdEnc_HasMSA, // MULV_H |
| 13159 | CEFBS_HasStdEnc_HasMSA, // MULV_W |
| 13160 | CEFBS_InMicroMips_NotMips32r6, // MUL_MM |
| 13161 | CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 |
| 13162 | CEFBS_HasDSPR2, // MUL_PH |
| 13163 | CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 |
| 13164 | CEFBS_HasStdEnc_HasMSA, // MUL_Q_H |
| 13165 | CEFBS_HasStdEnc_HasMSA, // MUL_Q_W |
| 13166 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 |
| 13167 | CEFBS_HasDSPR2, // MUL_S_PH |
| 13168 | CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 |
| 13169 | CEFBS_InMips16Mode, // Mfhi16 |
| 13170 | CEFBS_InMips16Mode, // Mflo16 |
| 13171 | CEFBS_InMips16Mode, // Move32R16 |
| 13172 | CEFBS_InMips16Mode, // MoveR3216 |
| 13173 | CEFBS_HasStdEnc_HasMips32r6, // NAL |
| 13174 | CEFBS_HasStdEnc_HasMSA, // NLOC_B |
| 13175 | CEFBS_HasStdEnc_HasMSA, // NLOC_D |
| 13176 | CEFBS_HasStdEnc_HasMSA, // NLOC_H |
| 13177 | CEFBS_HasStdEnc_HasMSA, // NLOC_W |
| 13178 | CEFBS_HasStdEnc_HasMSA, // NLZC_B |
| 13179 | CEFBS_HasStdEnc_HasMSA, // NLZC_D |
| 13180 | CEFBS_HasStdEnc_HasMSA, // NLZC_H |
| 13181 | CEFBS_HasStdEnc_HasMSA, // NLZC_W |
| 13182 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 |
| 13183 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM |
| 13184 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 |
| 13185 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S |
| 13186 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM |
| 13187 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 |
| 13188 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM |
| 13189 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 |
| 13190 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S |
| 13191 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM |
| 13192 | CEFBS_HasStdEnc_NotInMicroMips, // NOR |
| 13193 | CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 |
| 13194 | CEFBS_HasStdEnc_HasMSA, // NORI_B |
| 13195 | CEFBS_InMicroMips_NotMips32r6, // NOR_MM |
| 13196 | CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 |
| 13197 | CEFBS_HasStdEnc_HasMSA, // NOR_V |
| 13198 | CEFBS_InMicroMips_NotMips32r6, // NOT16_MM |
| 13199 | CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 |
| 13200 | CEFBS_InMips16Mode, // NegRxRy16 |
| 13201 | CEFBS_InMips16Mode, // NotRxRy16 |
| 13202 | CEFBS_HasStdEnc_NotInMicroMips, // OR |
| 13203 | CEFBS_InMicroMips_NotMips32r6, // OR16_MM |
| 13204 | CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 |
| 13205 | CEFBS_NotInMips16Mode_IsGP64bit, // OR64 |
| 13206 | CEFBS_HasStdEnc_HasMSA, // ORI_B |
| 13207 | CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 |
| 13208 | CEFBS_InMicroMips_NotMips32r6, // OR_MM |
| 13209 | CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 |
| 13210 | CEFBS_HasStdEnc_HasMSA, // OR_V |
| 13211 | CEFBS_HasStdEnc_NotInMicroMips, // ORi |
| 13212 | CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 |
| 13213 | CEFBS_InMicroMips_NotMips32r6, // ORi_MM |
| 13214 | CEFBS_InMips16Mode, // OrRxRxRy16 |
| 13215 | CEFBS_HasDSP, // PACKRL_PH |
| 13216 | CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM |
| 13217 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE |
| 13218 | CEFBS_InMicroMips, // PAUSE_MM |
| 13219 | CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 |
| 13220 | CEFBS_HasStdEnc_HasMSA, // PCKEV_B |
| 13221 | CEFBS_HasStdEnc_HasMSA, // PCKEV_D |
| 13222 | CEFBS_HasStdEnc_HasMSA, // PCKEV_H |
| 13223 | CEFBS_HasStdEnc_HasMSA, // PCKEV_W |
| 13224 | CEFBS_HasStdEnc_HasMSA, // PCKOD_B |
| 13225 | CEFBS_HasStdEnc_HasMSA, // PCKOD_D |
| 13226 | CEFBS_HasStdEnc_HasMSA, // PCKOD_H |
| 13227 | CEFBS_HasStdEnc_HasMSA, // PCKOD_W |
| 13228 | CEFBS_HasStdEnc_HasMSA, // PCNT_B |
| 13229 | CEFBS_HasStdEnc_HasMSA, // PCNT_D |
| 13230 | CEFBS_HasStdEnc_HasMSA, // PCNT_H |
| 13231 | CEFBS_HasStdEnc_HasMSA, // PCNT_W |
| 13232 | CEFBS_HasDSP, // PICK_PH |
| 13233 | CEFBS_InMicroMips_HasDSP, // PICK_PH_MM |
| 13234 | CEFBS_HasDSP, // PICK_QB |
| 13235 | CEFBS_InMicroMips_HasDSP, // PICK_QB_MM |
| 13236 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 |
| 13237 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 |
| 13238 | CEFBS_HasCnMips, // POP |
| 13239 | CEFBS_HasDSP, // PRECEQU_PH_QBL |
| 13240 | CEFBS_HasDSP, // PRECEQU_PH_QBLA |
| 13241 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM |
| 13242 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM |
| 13243 | CEFBS_HasDSP, // PRECEQU_PH_QBR |
| 13244 | CEFBS_HasDSP, // PRECEQU_PH_QBRA |
| 13245 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM |
| 13246 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM |
| 13247 | CEFBS_HasDSP, // PRECEQ_W_PHL |
| 13248 | CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM |
| 13249 | CEFBS_HasDSP, // PRECEQ_W_PHR |
| 13250 | CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM |
| 13251 | CEFBS_HasDSP, // PRECEU_PH_QBL |
| 13252 | CEFBS_HasDSP, // PRECEU_PH_QBLA |
| 13253 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM |
| 13254 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM |
| 13255 | CEFBS_HasDSP, // PRECEU_PH_QBR |
| 13256 | CEFBS_HasDSP, // PRECEU_PH_QBRA |
| 13257 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM |
| 13258 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM |
| 13259 | CEFBS_HasDSP, // PRECRQU_S_QB_PH |
| 13260 | CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM |
| 13261 | CEFBS_HasDSP, // PRECRQ_PH_W |
| 13262 | CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM |
| 13263 | CEFBS_HasDSP, // PRECRQ_QB_PH |
| 13264 | CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM |
| 13265 | CEFBS_HasDSP, // PRECRQ_RS_PH_W |
| 13266 | CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM |
| 13267 | CEFBS_HasDSPR2, // PRECR_QB_PH |
| 13268 | CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 |
| 13269 | CEFBS_HasDSPR2, // PRECR_SRA_PH_W |
| 13270 | CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 |
| 13271 | CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W |
| 13272 | CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 |
| 13273 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF |
| 13274 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE |
| 13275 | CEFBS_InMicroMips_HasEVA, // PREFE_MM |
| 13276 | CEFBS_InMicroMips_NotMips32r6, // PREFX_MM |
| 13277 | CEFBS_InMicroMips_NotMips32r6, // PREF_MM |
| 13278 | CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 |
| 13279 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 |
| 13280 | CEFBS_HasDSPR2, // PREPEND |
| 13281 | CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 |
| 13282 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 |
| 13283 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 |
| 13284 | CEFBS_HasDSP, // RADDU_W_QB |
| 13285 | CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM |
| 13286 | CEFBS_HasDSP, // RDDSP |
| 13287 | CEFBS_InMicroMips_HasDSP, // RDDSP_MM |
| 13288 | CEFBS_HasStdEnc_NotInMicroMips, // RDHWR |
| 13289 | CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 |
| 13290 | CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM |
| 13291 | CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 |
| 13292 | CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 |
| 13293 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 |
| 13294 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // RECIP_D32_MM |
| 13295 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 |
| 13296 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // RECIP_D64_MM |
| 13297 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S |
| 13298 | CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM |
| 13299 | CEFBS_HasDSP, // REPLV_PH |
| 13300 | CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM |
| 13301 | CEFBS_HasDSP, // REPLV_QB |
| 13302 | CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM |
| 13303 | CEFBS_HasDSP, // REPL_PH |
| 13304 | CEFBS_InMicroMips_HasDSP, // REPL_PH_MM |
| 13305 | CEFBS_HasDSP, // REPL_QB |
| 13306 | CEFBS_InMicroMips_HasDSP, // REPL_QB_MM |
| 13307 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D |
| 13308 | CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 |
| 13309 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S |
| 13310 | CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 |
| 13311 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR |
| 13312 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV |
| 13313 | CEFBS_InMicroMips, // ROTRV_MM |
| 13314 | CEFBS_InMicroMips, // ROTR_MM |
| 13315 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 |
| 13316 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 |
| 13317 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S |
| 13318 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 |
| 13319 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 |
| 13320 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 |
| 13321 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 |
| 13322 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // ROUND_W_MM |
| 13323 | CEFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S |
| 13324 | CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM |
| 13325 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 |
| 13326 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 |
| 13327 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // RSQRT_D32_MM |
| 13328 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 |
| 13329 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // RSQRT_D64_MM |
| 13330 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S |
| 13331 | CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM |
| 13332 | CEFBS_InMips16Mode, // Restore16 |
| 13333 | CEFBS_InMips16Mode, // RestoreX16 |
| 13334 | CEFBS_HasCnMipsP, // SAA |
| 13335 | CEFBS_HasCnMipsP, // SAAD |
| 13336 | CEFBS_HasStdEnc_HasMSA, // SAT_S_B |
| 13337 | CEFBS_HasStdEnc_HasMSA, // SAT_S_D |
| 13338 | CEFBS_HasStdEnc_HasMSA, // SAT_S_H |
| 13339 | CEFBS_HasStdEnc_HasMSA, // SAT_S_W |
| 13340 | CEFBS_HasStdEnc_HasMSA, // SAT_U_B |
| 13341 | CEFBS_HasStdEnc_HasMSA, // SAT_U_D |
| 13342 | CEFBS_HasStdEnc_HasMSA, // SAT_U_H |
| 13343 | CEFBS_HasStdEnc_HasMSA, // SAT_U_W |
| 13344 | CEFBS_HasStdEnc_NotInMicroMips, // SB |
| 13345 | CEFBS_InMicroMips_NotMips32r6, // SB16_MM |
| 13346 | CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 |
| 13347 | CEFBS_NotInMips16Mode_IsGP64bit, // SB64 |
| 13348 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE |
| 13349 | CEFBS_InMicroMips_HasEVA, // SBE_MM |
| 13350 | CEFBS_InMicroMips, // SB_MM |
| 13351 | CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 |
| 13352 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // SC |
| 13353 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // SC64 |
| 13354 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 |
| 13355 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // SCD |
| 13356 | CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 |
| 13357 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE |
| 13358 | CEFBS_InMicroMips_HasEVA, // SCE_MM |
| 13359 | CEFBS_InMicroMips_NotMips32r6, // SC_MM |
| 13360 | CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 |
| 13361 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 |
| 13362 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD |
| 13363 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP |
| 13364 | CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM |
| 13365 | CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 |
| 13366 | CEFBS_InMicroMips, // SDBBP_MM |
| 13367 | CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 |
| 13368 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 |
| 13369 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 |
| 13370 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 |
| 13371 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 |
| 13372 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // SDC1_MM_D32 |
| 13373 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, // SDC1_MM_D64 |
| 13374 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 |
| 13375 | CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 |
| 13376 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 |
| 13377 | CEFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, // SDC3 |
| 13378 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV |
| 13379 | CEFBS_InMicroMips_NotMips32r6, // SDIV_MM |
| 13380 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL |
| 13381 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR |
| 13382 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 |
| 13383 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 |
| 13384 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB |
| 13385 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 |
| 13386 | CEFBS_InMicroMips, // SEB_MM |
| 13387 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH |
| 13388 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 |
| 13389 | CEFBS_InMicroMips, // SEH_MM |
| 13390 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ |
| 13391 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 |
| 13392 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D |
| 13393 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 |
| 13394 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 |
| 13395 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S |
| 13396 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 |
| 13397 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ |
| 13398 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 |
| 13399 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D |
| 13400 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 |
| 13401 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 |
| 13402 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S |
| 13403 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 |
| 13404 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D |
| 13405 | CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 |
| 13406 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S |
| 13407 | CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 |
| 13408 | CEFBS_HasCnMips, // SEQ |
| 13409 | CEFBS_HasCnMips, // SEQi |
| 13410 | CEFBS_HasStdEnc_NotInMicroMips, // SH |
| 13411 | CEFBS_InMicroMips_NotMips32r6, // SH16_MM |
| 13412 | CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 |
| 13413 | CEFBS_NotInMips16Mode_IsGP64bit, // SH64 |
| 13414 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE |
| 13415 | CEFBS_InMicroMips_HasEVA, // SHE_MM |
| 13416 | CEFBS_HasStdEnc_HasMSA, // SHF_B |
| 13417 | CEFBS_HasStdEnc_HasMSA, // SHF_H |
| 13418 | CEFBS_HasStdEnc_HasMSA, // SHF_W |
| 13419 | CEFBS_HasDSP, // SHILO |
| 13420 | CEFBS_HasDSP, // SHILOV |
| 13421 | CEFBS_InMicroMips_HasDSP, // SHILOV_MM |
| 13422 | CEFBS_InMicroMips_HasDSP, // SHILO_MM |
| 13423 | CEFBS_HasDSP, // SHLLV_PH |
| 13424 | CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM |
| 13425 | CEFBS_HasDSP, // SHLLV_QB |
| 13426 | CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM |
| 13427 | CEFBS_HasDSP, // SHLLV_S_PH |
| 13428 | CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM |
| 13429 | CEFBS_HasDSP, // SHLLV_S_W |
| 13430 | CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM |
| 13431 | CEFBS_HasDSP, // SHLL_PH |
| 13432 | CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM |
| 13433 | CEFBS_HasDSP, // SHLL_QB |
| 13434 | CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM |
| 13435 | CEFBS_HasDSP, // SHLL_S_PH |
| 13436 | CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM |
| 13437 | CEFBS_HasDSP, // SHLL_S_W |
| 13438 | CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM |
| 13439 | CEFBS_HasDSP, // SHRAV_PH |
| 13440 | CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM |
| 13441 | CEFBS_HasDSPR2, // SHRAV_QB |
| 13442 | CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 |
| 13443 | CEFBS_HasDSP, // SHRAV_R_PH |
| 13444 | CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM |
| 13445 | CEFBS_HasDSPR2, // SHRAV_R_QB |
| 13446 | CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 |
| 13447 | CEFBS_HasDSP, // SHRAV_R_W |
| 13448 | CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM |
| 13449 | CEFBS_HasDSP, // SHRA_PH |
| 13450 | CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM |
| 13451 | CEFBS_HasDSPR2, // SHRA_QB |
| 13452 | CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 |
| 13453 | CEFBS_HasDSP, // SHRA_R_PH |
| 13454 | CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM |
| 13455 | CEFBS_HasDSPR2, // SHRA_R_QB |
| 13456 | CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 |
| 13457 | CEFBS_HasDSP, // SHRA_R_W |
| 13458 | CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM |
| 13459 | CEFBS_HasDSPR2, // SHRLV_PH |
| 13460 | CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 |
| 13461 | CEFBS_HasDSP, // SHRLV_QB |
| 13462 | CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM |
| 13463 | CEFBS_HasDSPR2, // SHRL_PH |
| 13464 | CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 |
| 13465 | CEFBS_HasDSP, // SHRL_QB |
| 13466 | CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM |
| 13467 | CEFBS_InMicroMips, // SH_MM |
| 13468 | CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 |
| 13469 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE |
| 13470 | CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 |
| 13471 | CEFBS_HasStdEnc_HasMSA, // SLDI_B |
| 13472 | CEFBS_HasStdEnc_HasMSA, // SLDI_D |
| 13473 | CEFBS_HasStdEnc_HasMSA, // SLDI_H |
| 13474 | CEFBS_HasStdEnc_HasMSA, // SLDI_W |
| 13475 | CEFBS_HasStdEnc_HasMSA, // SLD_B |
| 13476 | CEFBS_HasStdEnc_HasMSA, // SLD_D |
| 13477 | CEFBS_HasStdEnc_HasMSA, // SLD_H |
| 13478 | CEFBS_HasStdEnc_HasMSA, // SLD_W |
| 13479 | CEFBS_HasStdEnc_NotInMicroMips, // SLL |
| 13480 | CEFBS_InMicroMips_NotMips32r6, // SLL16_MM |
| 13481 | CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 |
| 13482 | CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 |
| 13483 | CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 |
| 13484 | CEFBS_HasStdEnc_HasMSA, // SLLI_B |
| 13485 | CEFBS_HasStdEnc_HasMSA, // SLLI_D |
| 13486 | CEFBS_HasStdEnc_HasMSA, // SLLI_H |
| 13487 | CEFBS_HasStdEnc_HasMSA, // SLLI_W |
| 13488 | CEFBS_HasStdEnc_NotInMicroMips, // SLLV |
| 13489 | CEFBS_InMicroMips, // SLLV_MM |
| 13490 | CEFBS_HasStdEnc_HasMSA, // SLL_B |
| 13491 | CEFBS_HasStdEnc_HasMSA, // SLL_D |
| 13492 | CEFBS_HasStdEnc_HasMSA, // SLL_H |
| 13493 | CEFBS_InMicroMips, // SLL_MM |
| 13494 | CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 |
| 13495 | CEFBS_HasStdEnc_HasMSA, // SLL_W |
| 13496 | CEFBS_HasStdEnc_NotInMicroMips, // SLT |
| 13497 | CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 |
| 13498 | CEFBS_InMicroMips, // SLT_MM |
| 13499 | CEFBS_HasStdEnc_NotInMicroMips, // SLTi |
| 13500 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 |
| 13501 | CEFBS_InMicroMips, // SLTi_MM |
| 13502 | CEFBS_HasStdEnc_NotInMicroMips, // SLTiu |
| 13503 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 |
| 13504 | CEFBS_InMicroMips, // SLTiu_MM |
| 13505 | CEFBS_HasStdEnc_NotInMicroMips, // SLTu |
| 13506 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 |
| 13507 | CEFBS_InMicroMips, // SLTu_MM |
| 13508 | CEFBS_HasCnMips, // SNE |
| 13509 | CEFBS_HasCnMips, // SNEi |
| 13510 | CEFBS_HasStdEnc_HasMSA, // SPLATI_B |
| 13511 | CEFBS_HasStdEnc_HasMSA, // SPLATI_D |
| 13512 | CEFBS_HasStdEnc_HasMSA, // SPLATI_H |
| 13513 | CEFBS_HasStdEnc_HasMSA, // SPLATI_W |
| 13514 | CEFBS_HasStdEnc_HasMSA, // SPLAT_B |
| 13515 | CEFBS_HasStdEnc_HasMSA, // SPLAT_D |
| 13516 | CEFBS_HasStdEnc_HasMSA, // SPLAT_H |
| 13517 | CEFBS_HasStdEnc_HasMSA, // SPLAT_W |
| 13518 | CEFBS_HasStdEnc_NotInMicroMips, // SRA |
| 13519 | CEFBS_HasStdEnc_HasMSA, // SRAI_B |
| 13520 | CEFBS_HasStdEnc_HasMSA, // SRAI_D |
| 13521 | CEFBS_HasStdEnc_HasMSA, // SRAI_H |
| 13522 | CEFBS_HasStdEnc_HasMSA, // SRAI_W |
| 13523 | CEFBS_HasStdEnc_HasMSA, // SRARI_B |
| 13524 | CEFBS_HasStdEnc_HasMSA, // SRARI_D |
| 13525 | CEFBS_HasStdEnc_HasMSA, // SRARI_H |
| 13526 | CEFBS_HasStdEnc_HasMSA, // SRARI_W |
| 13527 | CEFBS_HasStdEnc_HasMSA, // SRAR_B |
| 13528 | CEFBS_HasStdEnc_HasMSA, // SRAR_D |
| 13529 | CEFBS_HasStdEnc_HasMSA, // SRAR_H |
| 13530 | CEFBS_HasStdEnc_HasMSA, // SRAR_W |
| 13531 | CEFBS_HasStdEnc_NotInMicroMips, // SRAV |
| 13532 | CEFBS_InMicroMips, // SRAV_MM |
| 13533 | CEFBS_HasStdEnc_HasMSA, // SRA_B |
| 13534 | CEFBS_HasStdEnc_HasMSA, // SRA_D |
| 13535 | CEFBS_HasStdEnc_HasMSA, // SRA_H |
| 13536 | CEFBS_InMicroMips, // SRA_MM |
| 13537 | CEFBS_HasStdEnc_HasMSA, // SRA_W |
| 13538 | CEFBS_HasStdEnc_NotInMicroMips, // SRL |
| 13539 | CEFBS_InMicroMips_NotMips32r6, // SRL16_MM |
| 13540 | CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 |
| 13541 | CEFBS_HasStdEnc_HasMSA, // SRLI_B |
| 13542 | CEFBS_HasStdEnc_HasMSA, // SRLI_D |
| 13543 | CEFBS_HasStdEnc_HasMSA, // SRLI_H |
| 13544 | CEFBS_HasStdEnc_HasMSA, // SRLI_W |
| 13545 | CEFBS_HasStdEnc_HasMSA, // SRLRI_B |
| 13546 | CEFBS_HasStdEnc_HasMSA, // SRLRI_D |
| 13547 | CEFBS_HasStdEnc_HasMSA, // SRLRI_H |
| 13548 | CEFBS_HasStdEnc_HasMSA, // SRLRI_W |
| 13549 | CEFBS_HasStdEnc_HasMSA, // SRLR_B |
| 13550 | CEFBS_HasStdEnc_HasMSA, // SRLR_D |
| 13551 | CEFBS_HasStdEnc_HasMSA, // SRLR_H |
| 13552 | CEFBS_HasStdEnc_HasMSA, // SRLR_W |
| 13553 | CEFBS_HasStdEnc_NotInMicroMips, // SRLV |
| 13554 | CEFBS_InMicroMips, // SRLV_MM |
| 13555 | CEFBS_HasStdEnc_HasMSA, // SRL_B |
| 13556 | CEFBS_HasStdEnc_HasMSA, // SRL_D |
| 13557 | CEFBS_HasStdEnc_HasMSA, // SRL_H |
| 13558 | CEFBS_InMicroMips, // SRL_MM |
| 13559 | CEFBS_HasStdEnc_HasMSA, // SRL_W |
| 13560 | CEFBS_HasStdEnc_NotInMicroMips, // SSNOP |
| 13561 | CEFBS_InMicroMips, // SSNOP_MM |
| 13562 | CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 |
| 13563 | CEFBS_HasStdEnc_HasMSA, // ST_B |
| 13564 | CEFBS_HasStdEnc_HasMSA, // ST_D |
| 13565 | CEFBS_HasStdEnc_HasMSA, // ST_H |
| 13566 | CEFBS_HasStdEnc_HasMSA, // ST_W |
| 13567 | CEFBS_HasStdEnc_NotInMicroMips, // SUB |
| 13568 | CEFBS_HasDSPR2, // SUBQH_PH |
| 13569 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 |
| 13570 | CEFBS_HasDSPR2, // SUBQH_R_PH |
| 13571 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 |
| 13572 | CEFBS_HasDSPR2, // SUBQH_R_W |
| 13573 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 |
| 13574 | CEFBS_HasDSPR2, // SUBQH_W |
| 13575 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 |
| 13576 | CEFBS_HasDSP, // SUBQ_PH |
| 13577 | CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM |
| 13578 | CEFBS_HasDSP, // SUBQ_S_PH |
| 13579 | CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM |
| 13580 | CEFBS_HasDSP, // SUBQ_S_W |
| 13581 | CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM |
| 13582 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B |
| 13583 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D |
| 13584 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H |
| 13585 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W |
| 13586 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B |
| 13587 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D |
| 13588 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H |
| 13589 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W |
| 13590 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_B |
| 13591 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_D |
| 13592 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_H |
| 13593 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_W |
| 13594 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_B |
| 13595 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_D |
| 13596 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_H |
| 13597 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_W |
| 13598 | CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM |
| 13599 | CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 |
| 13600 | CEFBS_HasDSPR2, // SUBUH_QB |
| 13601 | CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 |
| 13602 | CEFBS_HasDSPR2, // SUBUH_R_QB |
| 13603 | CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 |
| 13604 | CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 |
| 13605 | CEFBS_HasDSPR2, // SUBU_PH |
| 13606 | CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 |
| 13607 | CEFBS_HasDSP, // SUBU_QB |
| 13608 | CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM |
| 13609 | CEFBS_HasDSPR2, // SUBU_S_PH |
| 13610 | CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 |
| 13611 | CEFBS_HasDSP, // SUBU_S_QB |
| 13612 | CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM |
| 13613 | CEFBS_HasStdEnc_HasMSA, // SUBVI_B |
| 13614 | CEFBS_HasStdEnc_HasMSA, // SUBVI_D |
| 13615 | CEFBS_HasStdEnc_HasMSA, // SUBVI_H |
| 13616 | CEFBS_HasStdEnc_HasMSA, // SUBVI_W |
| 13617 | CEFBS_HasStdEnc_HasMSA, // SUBV_B |
| 13618 | CEFBS_HasStdEnc_HasMSA, // SUBV_D |
| 13619 | CEFBS_HasStdEnc_HasMSA, // SUBV_H |
| 13620 | CEFBS_HasStdEnc_HasMSA, // SUBV_W |
| 13621 | CEFBS_InMicroMips_NotMips32r6, // SUB_MM |
| 13622 | CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 |
| 13623 | CEFBS_HasStdEnc_NotInMicroMips, // SUBu |
| 13624 | CEFBS_InMicroMips_NotMips32r6, // SUBu_MM |
| 13625 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 |
| 13626 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 |
| 13627 | CEFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, // SUXC1_MM |
| 13628 | CEFBS_HasStdEnc_NotInMicroMips, // SW |
| 13629 | CEFBS_InMicroMips_NotMips32r6, // SW16_MM |
| 13630 | CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 |
| 13631 | CEFBS_NotInMips16Mode_IsGP64bit, // SW64 |
| 13632 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 |
| 13633 | CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM |
| 13634 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 |
| 13635 | CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 |
| 13636 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 |
| 13637 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, // SWC3 |
| 13638 | CEFBS_NotInMips16Mode_HasDSP, // SWDSP |
| 13639 | CEFBS_InMicroMips_HasDSP, // SWDSP_MM |
| 13640 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE |
| 13641 | CEFBS_InMicroMips_HasEVA, // SWE_MM |
| 13642 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL |
| 13643 | CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 |
| 13644 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE |
| 13645 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM |
| 13646 | CEFBS_InMicroMips_NotMips32r6, // SWL_MM |
| 13647 | CEFBS_InMicroMips_NotMips32r6, // SWM16_MM |
| 13648 | CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 |
| 13649 | CEFBS_InMicroMips, // SWM32_MM |
| 13650 | CEFBS_InMicroMips, // SWP_MM |
| 13651 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR |
| 13652 | CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 |
| 13653 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE |
| 13654 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM |
| 13655 | CEFBS_InMicroMips_NotMips32r6, // SWR_MM |
| 13656 | CEFBS_InMicroMips_NotMips32r6, // SWSP_MM |
| 13657 | CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 |
| 13658 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 |
| 13659 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM |
| 13660 | CEFBS_InMicroMips, // SW_MM |
| 13661 | CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 |
| 13662 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC |
| 13663 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI |
| 13664 | CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM |
| 13665 | CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 |
| 13666 | CEFBS_InMicroMips, // SYNC_MM |
| 13667 | CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 |
| 13668 | CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL |
| 13669 | CEFBS_InMicroMips, // SYSCALL_MM |
| 13670 | CEFBS_InMips16Mode, // Save16 |
| 13671 | CEFBS_InMips16Mode, // SaveX16 |
| 13672 | CEFBS_InMips16Mode, // SbRxRyOffMemX16 |
| 13673 | CEFBS_InMips16Mode, // SebRx16 |
| 13674 | CEFBS_InMips16Mode, // SehRx16 |
| 13675 | CEFBS_InMips16Mode, // ShRxRyOffMemX16 |
| 13676 | CEFBS_InMips16Mode, // SllX16 |
| 13677 | CEFBS_InMips16Mode, // SllvRxRy16 |
| 13678 | CEFBS_InMips16Mode, // SltRxRy16 |
| 13679 | CEFBS_InMips16Mode, // SltiRxImm16 |
| 13680 | CEFBS_InMips16Mode, // SltiRxImmX16 |
| 13681 | CEFBS_InMips16Mode, // SltiuRxImm16 |
| 13682 | CEFBS_InMips16Mode, // SltiuRxImmX16 |
| 13683 | CEFBS_InMips16Mode, // SltuRxRy16 |
| 13684 | CEFBS_InMips16Mode, // SraX16 |
| 13685 | CEFBS_InMips16Mode, // SravRxRy16 |
| 13686 | CEFBS_InMips16Mode, // SrlX16 |
| 13687 | CEFBS_InMips16Mode, // SrlvRxRy16 |
| 13688 | CEFBS_InMips16Mode, // SubuRxRyRz16 |
| 13689 | CEFBS_InMips16Mode, // SwRxRyOffMemX16 |
| 13690 | CEFBS_InMips16Mode, // SwRxSpImmX16 |
| 13691 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ |
| 13692 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI |
| 13693 | CEFBS_InMicroMips_NotMips32r6, // TEQI_MM |
| 13694 | CEFBS_InMicroMips, // TEQ_MM |
| 13695 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE |
| 13696 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI |
| 13697 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU |
| 13698 | CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM |
| 13699 | CEFBS_InMicroMips_NotMips32r6, // TGEI_MM |
| 13700 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU |
| 13701 | CEFBS_InMicroMips, // TGEU_MM |
| 13702 | CEFBS_InMicroMips, // TGE_MM |
| 13703 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV |
| 13704 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF |
| 13705 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM |
| 13706 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM |
| 13707 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP |
| 13708 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM |
| 13709 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR |
| 13710 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM |
| 13711 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI |
| 13712 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM |
| 13713 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR |
| 13714 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM |
| 13715 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV |
| 13716 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF |
| 13717 | CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 |
| 13718 | CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 |
| 13719 | CEFBS_HasStdEnc_NotInMicroMips, // TLBP |
| 13720 | CEFBS_InMicroMips, // TLBP_MM |
| 13721 | CEFBS_HasStdEnc_NotInMicroMips, // TLBR |
| 13722 | CEFBS_InMicroMips, // TLBR_MM |
| 13723 | CEFBS_HasStdEnc_NotInMicroMips, // TLBWI |
| 13724 | CEFBS_InMicroMips, // TLBWI_MM |
| 13725 | CEFBS_HasStdEnc_NotInMicroMips, // TLBWR |
| 13726 | CEFBS_InMicroMips, // TLBWR_MM |
| 13727 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT |
| 13728 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI |
| 13729 | CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM |
| 13730 | CEFBS_InMicroMips_NotMips32r6, // TLTI_MM |
| 13731 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU |
| 13732 | CEFBS_InMicroMips, // TLTU_MM |
| 13733 | CEFBS_InMicroMips, // TLT_MM |
| 13734 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE |
| 13735 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI |
| 13736 | CEFBS_InMicroMips_NotMips32r6, // TNEI_MM |
| 13737 | CEFBS_InMicroMips, // TNE_MM |
| 13738 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 |
| 13739 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 |
| 13740 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S |
| 13741 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 |
| 13742 | CEFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 |
| 13743 | CEFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 |
| 13744 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 |
| 13745 | CEFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, // TRUNC_W_MM |
| 13746 | CEFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S |
| 13747 | CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM |
| 13748 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 |
| 13749 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU |
| 13750 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV |
| 13751 | CEFBS_InMicroMips_NotMips32r6, // UDIV_MM |
| 13752 | CEFBS_HasCnMips, // V3MULU |
| 13753 | CEFBS_HasCnMips, // VMM0 |
| 13754 | CEFBS_HasCnMips, // VMULU |
| 13755 | CEFBS_HasStdEnc_HasMSA, // VSHF_B |
| 13756 | CEFBS_HasStdEnc_HasMSA, // VSHF_D |
| 13757 | CEFBS_HasStdEnc_HasMSA, // VSHF_H |
| 13758 | CEFBS_HasStdEnc_HasMSA, // VSHF_W |
| 13759 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT |
| 13760 | CEFBS_InMicroMips, // WAIT_MM |
| 13761 | CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 |
| 13762 | CEFBS_HasDSP_NotInMicroMips, // WRDSP |
| 13763 | CEFBS_InMicroMips_HasDSP, // WRDSP_MM |
| 13764 | CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 |
| 13765 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH |
| 13766 | CEFBS_InMicroMips, // WSBH_MM |
| 13767 | CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 |
| 13768 | CEFBS_HasStdEnc_NotInMicroMips, // XOR |
| 13769 | CEFBS_InMicroMips_NotMips32r6, // XOR16_MM |
| 13770 | CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 |
| 13771 | CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 |
| 13772 | CEFBS_HasStdEnc_HasMSA, // XORI_B |
| 13773 | CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 |
| 13774 | CEFBS_InMicroMips_NotMips32r6, // XOR_MM |
| 13775 | CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 |
| 13776 | CEFBS_HasStdEnc_HasMSA, // XOR_V |
| 13777 | CEFBS_HasStdEnc_NotInMicroMips, // XORi |
| 13778 | CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 |
| 13779 | CEFBS_InMicroMips_NotMips32r6, // XORi_MM |
| 13780 | CEFBS_InMips16Mode, // XorRxRxRy16 |
| 13781 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD |
| 13782 | }; |
| 13783 | |
| 13784 | assert(Opcode < 2932); |
| 13785 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| 13786 | } |
| 13787 | |
| 13788 | |
| 13789 | } // namespace llvm::Mips_MC |
| 13790 | |
| 13791 | #endif // GET_COMPUTE_FEATURES |
| 13792 | |
| 13793 | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
| 13794 | #undef GET_AVAILABLE_OPCODE_CHECKER |
| 13795 | |
| 13796 | namespace llvm::Mips_MC { |
| 13797 | |
| 13798 | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
| 13799 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 13800 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 13801 | FeatureBitset MissingFeatures = |
| 13802 | (AvailableFeatures & RequiredFeatures) ^ |
| 13803 | RequiredFeatures; |
| 13804 | return !MissingFeatures.any(); |
| 13805 | } |
| 13806 | |
| 13807 | } // namespace llvm::Mips_MC |
| 13808 | |
| 13809 | #endif // GET_AVAILABLE_OPCODE_CHECKER |
| 13810 | |
| 13811 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 13812 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 13813 | |
| 13814 | #include <sstream> |
| 13815 | |
| 13816 | namespace llvm::Mips_MC { |
| 13817 | |
| 13818 | #ifndef NDEBUG |
| 13819 | static const char *SubtargetFeatureNames[] = { |
| 13820 | "Feature_HasCRC", |
| 13821 | "Feature_HasCnMips", |
| 13822 | "Feature_HasCnMipsP", |
| 13823 | "Feature_HasDSP", |
| 13824 | "Feature_HasDSPR2", |
| 13825 | "Feature_HasDSPR3", |
| 13826 | "Feature_HasEVA", |
| 13827 | "Feature_HasGINV", |
| 13828 | "Feature_HasMSA", |
| 13829 | "Feature_HasMT", |
| 13830 | "Feature_HasMadd4", |
| 13831 | "Feature_HasMips2", |
| 13832 | "Feature_HasMips3", |
| 13833 | "Feature_HasMips3D", |
| 13834 | "Feature_HasMips3_32", |
| 13835 | "Feature_HasMips3_32r2", |
| 13836 | "Feature_HasMips4_32", |
| 13837 | "Feature_HasMips4_32r2", |
| 13838 | "Feature_HasMips5_32r2", |
| 13839 | "Feature_HasMips32", |
| 13840 | "Feature_HasMips32r2", |
| 13841 | "Feature_HasMips32r5", |
| 13842 | "Feature_HasMips32r6", |
| 13843 | "Feature_HasMips64", |
| 13844 | "Feature_HasMips64r2", |
| 13845 | "Feature_HasMips64r5", |
| 13846 | "Feature_HasMips64r6", |
| 13847 | "Feature_HasStdEnc", |
| 13848 | "Feature_HasVirt", |
| 13849 | "Feature_InMicroMips", |
| 13850 | "Feature_InMips16Mode", |
| 13851 | "Feature_IsFP64bit", |
| 13852 | "Feature_IsGP32bit", |
| 13853 | "Feature_IsGP64bit", |
| 13854 | "Feature_IsNotSingleFloat", |
| 13855 | "Feature_IsNotSoftFloat", |
| 13856 | "Feature_IsPTR32bit", |
| 13857 | "Feature_IsPTR64bit", |
| 13858 | "Feature_IsR5900", |
| 13859 | "Feature_IsSingleFloat", |
| 13860 | "Feature_IsSym32", |
| 13861 | "Feature_IsSym64", |
| 13862 | "Feature_NoIndirectJumpGuards", |
| 13863 | "Feature_NotCnMips", |
| 13864 | "Feature_NotCnMipsP", |
| 13865 | "Feature_NotFP64bit", |
| 13866 | "Feature_NotInMicroMips", |
| 13867 | "Feature_NotInMips16Mode", |
| 13868 | "Feature_NotMips3", |
| 13869 | "Feature_NotMips4_32", |
| 13870 | "Feature_NotMips32r6", |
| 13871 | "Feature_NotMips64", |
| 13872 | "Feature_NotMips64r6", |
| 13873 | "Feature_NotR5900", |
| 13874 | "Feature_UseCompactBranches", |
| 13875 | "Feature_UseIndirectJumpsHazard", |
| 13876 | nullptr |
| 13877 | }; |
| 13878 | |
| 13879 | #endif // NDEBUG |
| 13880 | |
| 13881 | void verifyInstructionPredicates( |
| 13882 | unsigned Opcode, const FeatureBitset &Features) { |
| 13883 | #ifndef NDEBUG |
| 13884 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 13885 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 13886 | FeatureBitset MissingFeatures = |
| 13887 | (AvailableFeatures & RequiredFeatures) ^ |
| 13888 | RequiredFeatures; |
| 13889 | if (MissingFeatures.any()) { |
| 13890 | std::ostringstream Msg; |
| 13891 | Msg << "Attempting to emit "<< &MipsInstrNameData[MipsInstrNameIndices[Opcode]] |
| 13892 | << " instruction but the "; |
| 13893 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 13894 | if (MissingFeatures.test(i)) |
| 13895 | Msg << SubtargetFeatureNames[i] << " "; |
| 13896 | Msg << "predicate(s) are not met"; |
| 13897 | report_fatal_error(Msg.str().c_str()); |
| 13898 | } |
| 13899 | #endif // NDEBUG |
| 13900 | } |
| 13901 | |
| 13902 | } // namespace llvm::Mips_MC |
| 13903 | |
| 13904 | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| 13905 | |
| 13906 | #ifdef GET_INSTRMAP_INFO |
| 13907 | #undef GET_INSTRMAP_INFO |
| 13908 | |
| 13909 | namespace llvm::Mips { |
| 13910 | |
| 13911 | enum Arch { |
| 13912 | Arch_dsp, |
| 13913 | Arch_mmdsp, |
| 13914 | Arch_mipsr6, |
| 13915 | Arch_micromipsr6, |
| 13916 | Arch_se, |
| 13917 | Arch_micromips |
| 13918 | }; |
| 13919 | |
| 13920 | // Dsp2MicroMips |
| 13921 | LLVM_READONLY |
| 13922 | int32_t Dsp2MicroMips(uint32_t Opcode, enum Arch inArch) { |
| 13923 | using namespace Mips; |
| 13924 | static constexpr uint32_t Table[][3] = { |
| 13925 | { ABSQ_S_PH, ABSQ_S_PH, ABSQ_S_PH_MM }, |
| 13926 | { ABSQ_S_QB, ABSQ_S_QB, ABSQ_S_QB_MMR2 }, |
| 13927 | { ABSQ_S_W, ABSQ_S_W, ABSQ_S_W_MM }, |
| 13928 | { ADDQH_PH, ADDQH_PH, ADDQH_PH_MMR2 }, |
| 13929 | { ADDQH_R_PH, ADDQH_R_PH, ADDQH_R_PH_MMR2 }, |
| 13930 | { ADDQH_R_W, ADDQH_R_W, ADDQH_R_W_MMR2 }, |
| 13931 | { ADDQH_W, ADDQH_W, ADDQH_W_MMR2 }, |
| 13932 | { ADDQ_PH, ADDQ_PH, ADDQ_PH_MM }, |
| 13933 | { ADDQ_S_PH, ADDQ_S_PH, ADDQ_S_PH_MM }, |
| 13934 | { ADDQ_S_W, ADDQ_S_W, ADDQ_S_W_MM }, |
| 13935 | { ADDSC, ADDSC, ADDSC_MM }, |
| 13936 | { ADDUH_QB, ADDUH_QB, ADDUH_QB_MMR2 }, |
| 13937 | { ADDUH_R_QB, ADDUH_R_QB, ADDUH_R_QB_MMR2 }, |
| 13938 | { ADDU_PH, ADDU_PH, ADDU_PH_MMR2 }, |
| 13939 | { ADDU_QB, ADDU_QB, ADDU_QB_MM }, |
| 13940 | { ADDU_S_PH, ADDU_S_PH, ADDU_S_PH_MMR2 }, |
| 13941 | { ADDU_S_QB, ADDU_S_QB, ADDU_S_QB_MM }, |
| 13942 | { ADDWC, ADDWC, ADDWC_MM }, |
| 13943 | { APPEND, APPEND, APPEND_MMR2 }, |
| 13944 | { BALIGN, BALIGN, BALIGN_MMR2 }, |
| 13945 | { BITREV, BITREV, BITREV_MM }, |
| 13946 | { BPOSGE32, BPOSGE32, BPOSGE32_MM }, |
| 13947 | { CMPGDU_EQ_QB, CMPGDU_EQ_QB, CMPGDU_EQ_QB_MMR2 }, |
| 13948 | { CMPGDU_LE_QB, CMPGDU_LE_QB, CMPGDU_LE_QB_MMR2 }, |
| 13949 | { CMPGDU_LT_QB, CMPGDU_LT_QB, CMPGDU_LT_QB_MMR2 }, |
| 13950 | { CMPGU_EQ_QB, CMPGU_EQ_QB, CMPGU_EQ_QB_MM }, |
| 13951 | { CMPGU_LE_QB, CMPGU_LE_QB, CMPGU_LE_QB_MM }, |
| 13952 | { CMPGU_LT_QB, CMPGU_LT_QB, CMPGU_LT_QB_MM }, |
| 13953 | { CMPU_EQ_QB, CMPU_EQ_QB, CMPU_EQ_QB_MM }, |
| 13954 | { CMPU_LE_QB, CMPU_LE_QB, CMPU_LE_QB_MM }, |
| 13955 | { CMPU_LT_QB, CMPU_LT_QB, CMPU_LT_QB_MM }, |
| 13956 | { CMP_EQ_PH, CMP_EQ_PH, CMP_EQ_PH_MM }, |
| 13957 | { CMP_LE_PH, CMP_LE_PH, CMP_LE_PH_MM }, |
| 13958 | { CMP_LT_PH, CMP_LT_PH, CMP_LT_PH_MM }, |
| 13959 | { DPAQX_SA_W_PH, DPAQX_SA_W_PH, DPAQX_SA_W_PH_MMR2 }, |
| 13960 | { DPAQX_S_W_PH, DPAQX_S_W_PH, DPAQX_S_W_PH_MMR2 }, |
| 13961 | { DPAQ_SA_L_W, DPAQ_SA_L_W, DPAQ_SA_L_W_MM }, |
| 13962 | { DPAQ_S_W_PH, DPAQ_S_W_PH, DPAQ_S_W_PH_MM }, |
| 13963 | { DPAU_H_QBL, DPAU_H_QBL, DPAU_H_QBL_MM }, |
| 13964 | { DPAU_H_QBR, DPAU_H_QBR, DPAU_H_QBR_MM }, |
| 13965 | { DPAX_W_PH, DPAX_W_PH, DPAX_W_PH_MMR2 }, |
| 13966 | { DPA_W_PH, DPA_W_PH, DPA_W_PH_MMR2 }, |
| 13967 | { DPSQX_SA_W_PH, DPSQX_SA_W_PH, DPSQX_SA_W_PH_MMR2 }, |
| 13968 | { DPSQX_S_W_PH, DPSQX_S_W_PH, DPSQX_S_W_PH_MMR2 }, |
| 13969 | { DPSQ_SA_L_W, DPSQ_SA_L_W, DPSQ_SA_L_W_MM }, |
| 13970 | { DPSQ_S_W_PH, DPSQ_S_W_PH, DPSQ_S_W_PH_MM }, |
| 13971 | { DPSU_H_QBL, DPSU_H_QBL, DPSU_H_QBL_MM }, |
| 13972 | { DPSU_H_QBR, DPSU_H_QBR, DPSU_H_QBR_MM }, |
| 13973 | { DPSX_W_PH, DPSX_W_PH, DPSX_W_PH_MMR2 }, |
| 13974 | { DPS_W_PH, DPS_W_PH, DPS_W_PH_MMR2 }, |
| 13975 | { EXTP, EXTP, EXTP_MM }, |
| 13976 | { EXTPDP, EXTPDP, EXTPDP_MM }, |
| 13977 | { EXTPDPV, EXTPDPV, EXTPDPV_MM }, |
| 13978 | { EXTPV, EXTPV, EXTPV_MM }, |
| 13979 | { EXTRV_RS_W, EXTRV_RS_W, EXTRV_RS_W_MM }, |
| 13980 | { EXTRV_R_W, EXTRV_R_W, EXTRV_R_W_MM }, |
| 13981 | { EXTRV_S_H, EXTRV_S_H, EXTRV_S_H_MM }, |
| 13982 | { EXTRV_W, EXTRV_W, EXTRV_W_MM }, |
| 13983 | { EXTR_RS_W, EXTR_RS_W, EXTR_RS_W_MM }, |
| 13984 | { EXTR_R_W, EXTR_R_W, EXTR_R_W_MM }, |
| 13985 | { EXTR_S_H, EXTR_S_H, EXTR_S_H_MM }, |
| 13986 | { EXTR_W, EXTR_W, EXTR_W_MM }, |
| 13987 | { INSV, INSV, INSV_MM }, |
| 13988 | { LBUX, LBUX, LBUX_MM }, |
| 13989 | { LHX, LHX, LHX_MM }, |
| 13990 | { LWDSP, LWDSP, LWDSP_MM }, |
| 13991 | { LWX, LWX, LWX_MM }, |
| 13992 | { MADDU_DSP, MADDU_DSP, MADDU_DSP_MM }, |
| 13993 | { MADD_DSP, MADD_DSP, MADD_DSP_MM }, |
| 13994 | { MAQ_SA_W_PHL, MAQ_SA_W_PHL, MAQ_SA_W_PHL_MM }, |
| 13995 | { MAQ_SA_W_PHR, MAQ_SA_W_PHR, MAQ_SA_W_PHR_MM }, |
| 13996 | { MAQ_S_W_PHL, MAQ_S_W_PHL, MAQ_S_W_PHL_MM }, |
| 13997 | { MAQ_S_W_PHR, MAQ_S_W_PHR, MAQ_S_W_PHR_MM }, |
| 13998 | { MFHI_DSP, MFHI_DSP, MFHI_DSP_MM }, |
| 13999 | { MFLO_DSP, MFLO_DSP, MFLO_DSP_MM }, |
| 14000 | { MODSUB, MODSUB, MODSUB_MM }, |
| 14001 | { MSUBU_DSP, MSUBU_DSP, MSUBU_DSP_MM }, |
| 14002 | { MSUB_DSP, MSUB_DSP, MSUB_DSP_MM }, |
| 14003 | { MTHI_DSP, MTHI_DSP, MTHI_DSP_MM }, |
| 14004 | { MTHLIP, MTHLIP, MTHLIP_MM }, |
| 14005 | { MTLO_DSP, MTLO_DSP, MTLO_DSP_MM }, |
| 14006 | { MULEQ_S_W_PHL, MULEQ_S_W_PHL, MULEQ_S_W_PHL_MM }, |
| 14007 | { MULEQ_S_W_PHR, MULEQ_S_W_PHR, MULEQ_S_W_PHR_MM }, |
| 14008 | { MULEU_S_PH_QBL, MULEU_S_PH_QBL, MULEU_S_PH_QBL_MM }, |
| 14009 | { MULEU_S_PH_QBR, MULEU_S_PH_QBR, MULEU_S_PH_QBR_MM }, |
| 14010 | { MULQ_RS_PH, MULQ_RS_PH, MULQ_RS_PH_MM }, |
| 14011 | { MULQ_RS_W, MULQ_RS_W, MULQ_RS_W_MMR2 }, |
| 14012 | { MULQ_S_PH, MULQ_S_PH, MULQ_S_PH_MMR2 }, |
| 14013 | { MULQ_S_W, MULQ_S_W, MULQ_S_W_MMR2 }, |
| 14014 | { MULSAQ_S_W_PH, MULSAQ_S_W_PH, MULSAQ_S_W_PH_MM }, |
| 14015 | { MULSA_W_PH, MULSA_W_PH, MULSA_W_PH_MMR2 }, |
| 14016 | { MULTU_DSP, MULTU_DSP, MULTU_DSP_MM }, |
| 14017 | { MULT_DSP, MULT_DSP, MULT_DSP_MM }, |
| 14018 | { MUL_PH, MUL_PH, MUL_PH_MMR2 }, |
| 14019 | { MUL_S_PH, MUL_S_PH, MUL_S_PH_MMR2 }, |
| 14020 | { PACKRL_PH, PACKRL_PH, PACKRL_PH_MM }, |
| 14021 | { PICK_PH, PICK_PH, PICK_PH_MM }, |
| 14022 | { PICK_QB, PICK_QB, PICK_QB_MM }, |
| 14023 | { PRECEQU_PH_QBL, PRECEQU_PH_QBL, PRECEQU_PH_QBL_MM }, |
| 14024 | { PRECEQU_PH_QBLA, PRECEQU_PH_QBLA, PRECEQU_PH_QBLA_MM }, |
| 14025 | { PRECEQU_PH_QBR, PRECEQU_PH_QBR, PRECEQU_PH_QBR_MM }, |
| 14026 | { PRECEQU_PH_QBRA, PRECEQU_PH_QBRA, PRECEQU_PH_QBRA_MM }, |
| 14027 | { PRECEQ_W_PHL, PRECEQ_W_PHL, PRECEQ_W_PHL_MM }, |
| 14028 | { PRECEQ_W_PHR, PRECEQ_W_PHR, PRECEQ_W_PHR_MM }, |
| 14029 | { PRECEU_PH_QBL, PRECEU_PH_QBL, PRECEU_PH_QBL_MM }, |
| 14030 | { PRECEU_PH_QBLA, PRECEU_PH_QBLA, PRECEU_PH_QBLA_MM }, |
| 14031 | { PRECEU_PH_QBR, PRECEU_PH_QBR, PRECEU_PH_QBR_MM }, |
| 14032 | { PRECEU_PH_QBRA, PRECEU_PH_QBRA, PRECEU_PH_QBRA_MM }, |
| 14033 | { PRECRQU_S_QB_PH, PRECRQU_S_QB_PH, PRECRQU_S_QB_PH_MM }, |
| 14034 | { PRECRQ_PH_W, PRECRQ_PH_W, PRECRQ_PH_W_MM }, |
| 14035 | { PRECRQ_QB_PH, PRECRQ_QB_PH, PRECRQ_QB_PH_MM }, |
| 14036 | { PRECRQ_RS_PH_W, PRECRQ_RS_PH_W, PRECRQ_RS_PH_W_MM }, |
| 14037 | { PRECR_QB_PH, PRECR_QB_PH, PRECR_QB_PH_MMR2 }, |
| 14038 | { PRECR_SRA_PH_W, PRECR_SRA_PH_W, PRECR_SRA_PH_W_MMR2 }, |
| 14039 | { PRECR_SRA_R_PH_W, PRECR_SRA_R_PH_W, PRECR_SRA_R_PH_W_MMR2 }, |
| 14040 | { PREPEND, PREPEND, PREPEND_MMR2 }, |
| 14041 | { RADDU_W_QB, RADDU_W_QB, RADDU_W_QB_MM }, |
| 14042 | { RDDSP, RDDSP, RDDSP_MM }, |
| 14043 | { REPLV_PH, REPLV_PH, REPLV_PH_MM }, |
| 14044 | { REPLV_QB, REPLV_QB, REPLV_QB_MM }, |
| 14045 | { REPL_PH, REPL_PH, REPL_PH_MM }, |
| 14046 | { REPL_QB, REPL_QB, REPL_QB_MM }, |
| 14047 | { SHILO, SHILO, SHILO_MM }, |
| 14048 | { SHILOV, SHILOV, SHILOV_MM }, |
| 14049 | { SHLLV_PH, SHLLV_PH, SHLLV_PH_MM }, |
| 14050 | { SHLLV_QB, SHLLV_QB, SHLLV_QB_MM }, |
| 14051 | { SHLLV_S_PH, SHLLV_S_PH, SHLLV_S_PH_MM }, |
| 14052 | { SHLLV_S_W, SHLLV_S_W, SHLLV_S_W_MM }, |
| 14053 | { SHLL_PH, SHLL_PH, SHLL_PH_MM }, |
| 14054 | { SHLL_QB, SHLL_QB, SHLL_QB_MM }, |
| 14055 | { SHLL_S_PH, SHLL_S_PH, SHLL_S_PH_MM }, |
| 14056 | { SHLL_S_W, SHLL_S_W, SHLL_S_W_MM }, |
| 14057 | { SHRAV_PH, SHRAV_PH, SHRAV_PH_MM }, |
| 14058 | { SHRAV_QB, SHRAV_QB, SHRAV_QB_MMR2 }, |
| 14059 | { SHRAV_R_PH, SHRAV_R_PH, SHRAV_R_PH_MM }, |
| 14060 | { SHRAV_R_QB, SHRAV_R_QB, SHRAV_R_QB_MMR2 }, |
| 14061 | { SHRAV_R_W, SHRAV_R_W, SHRAV_R_W_MM }, |
| 14062 | { SHRA_PH, SHRA_PH, SHRA_PH_MM }, |
| 14063 | { SHRA_QB, SHRA_QB, SHRA_QB_MMR2 }, |
| 14064 | { SHRA_R_PH, SHRA_R_PH, SHRA_R_PH_MM }, |
| 14065 | { SHRA_R_QB, SHRA_R_QB, SHRA_R_QB_MMR2 }, |
| 14066 | { SHRA_R_W, SHRA_R_W, SHRA_R_W_MM }, |
| 14067 | { SHRLV_PH, SHRLV_PH, SHRLV_PH_MMR2 }, |
| 14068 | { SHRLV_QB, SHRLV_QB, SHRLV_QB_MM }, |
| 14069 | { SHRL_PH, SHRL_PH, SHRL_PH_MMR2 }, |
| 14070 | { SHRL_QB, SHRL_QB, SHRL_QB_MM }, |
| 14071 | { SUBQH_PH, SUBQH_PH, SUBQH_PH_MMR2 }, |
| 14072 | { SUBQH_R_PH, SUBQH_R_PH, SUBQH_R_PH_MMR2 }, |
| 14073 | { SUBQH_R_W, SUBQH_R_W, SUBQH_R_W_MMR2 }, |
| 14074 | { SUBQH_W, SUBQH_W, SUBQH_W_MMR2 }, |
| 14075 | { SUBQ_PH, SUBQ_PH, SUBQ_PH_MM }, |
| 14076 | { SUBQ_S_PH, SUBQ_S_PH, SUBQ_S_PH_MM }, |
| 14077 | { SUBQ_S_W, SUBQ_S_W, SUBQ_S_W_MM }, |
| 14078 | { SUBUH_QB, SUBUH_QB, SUBUH_QB_MMR2 }, |
| 14079 | { SUBUH_R_QB, SUBUH_R_QB, SUBUH_R_QB_MMR2 }, |
| 14080 | { SUBU_PH, SUBU_PH, SUBU_PH_MMR2 }, |
| 14081 | { SUBU_QB, SUBU_QB, SUBU_QB_MM }, |
| 14082 | { SUBU_S_PH, SUBU_S_PH, SUBU_S_PH_MMR2 }, |
| 14083 | { SUBU_S_QB, SUBU_S_QB, SUBU_S_QB_MM }, |
| 14084 | { SWDSP, SWDSP, SWDSP_MM }, |
| 14085 | }; // End of Table |
| 14086 | |
| 14087 | unsigned mid; |
| 14088 | unsigned start = 0; |
| 14089 | unsigned end = 160; |
| 14090 | while (start < end) { |
| 14091 | mid = start + (end - start) / 2; |
| 14092 | if (Opcode == Table[mid][0]) |
| 14093 | break; |
| 14094 | if (Opcode < Table[mid][0]) |
| 14095 | end = mid; |
| 14096 | else |
| 14097 | start = mid + 1; |
| 14098 | } |
| 14099 | if (start == end) |
| 14100 | return -1; // Instruction doesn't exist in this table. |
| 14101 | |
| 14102 | if (inArch == Arch_dsp) |
| 14103 | return Table[mid][1]; |
| 14104 | if (inArch == Arch_mmdsp) |
| 14105 | return Table[mid][2]; |
| 14106 | llvm_unreachable("Unrecognized column value!"); |
| 14107 | } |
| 14108 | |
| 14109 | // MipsR62MicroMipsR6 |
| 14110 | LLVM_READONLY |
| 14111 | int32_t MipsR62MicroMipsR6(uint32_t Opcode, enum Arch inArch) { |
| 14112 | using namespace Mips; |
| 14113 | static constexpr uint32_t Table[][3] = { |
| 14114 | { ADDIUPC, ADDIUPC, ADDIUPC_MMR6 }, |
| 14115 | { ALIGN, ALIGN, ALIGN_MMR6 }, |
| 14116 | { ALUIPC, ALUIPC, ALUIPC_MMR6 }, |
| 14117 | { AUI, AUI, AUI_MMR6 }, |
| 14118 | { AUIPC, AUIPC, AUIPC_MMR6 }, |
| 14119 | { BALC, BALC, BALC_MMR6 }, |
| 14120 | { BC, BC, BC_MMR6 }, |
| 14121 | { BEQC, BEQC, BEQC_MMR6 }, |
| 14122 | { BEQZALC, BEQZALC, BEQZALC_MMR6 }, |
| 14123 | { BEQZC, BEQZC, BEQZC_MMR6 }, |
| 14124 | { BGEC, BGEC, BGEC_MMR6 }, |
| 14125 | { BGEUC, BGEUC, BGEUC_MMR6 }, |
| 14126 | { BGEZALC, BGEZALC, BGEZALC_MMR6 }, |
| 14127 | { BGEZC, BGEZC, BGEZC_MMR6 }, |
| 14128 | { BGTZALC, BGTZALC, BGTZALC_MMR6 }, |
| 14129 | { BGTZC, BGTZC, BGTZC_MMR6 }, |
| 14130 | { BITSWAP, BITSWAP, BITSWAP_MMR6 }, |
| 14131 | { BLEZALC, BLEZALC, BLEZALC_MMR6 }, |
| 14132 | { BLEZC, BLEZC, BLEZC_MMR6 }, |
| 14133 | { BLTC, BLTC, BLTC_MMR6 }, |
| 14134 | { BLTUC, BLTUC, BLTUC_MMR6 }, |
| 14135 | { BLTZALC, BLTZALC, BLTZALC_MMR6 }, |
| 14136 | { BLTZC, BLTZC, BLTZC_MMR6 }, |
| 14137 | { BNEC, BNEC, BNEC_MMR6 }, |
| 14138 | { BNEZALC, BNEZALC, BNEZALC_MMR6 }, |
| 14139 | { BNEZC, BNEZC, BNEZC_MMR6 }, |
| 14140 | { BNVC, BNVC, BNVC_MMR6 }, |
| 14141 | { BOVC, BOVC, BOVC_MMR6 }, |
| 14142 | { CACHE_R6, CACHE_R6, CACHE_MMR6 }, |
| 14143 | { CLO_R6, CLO_R6, CLO_MMR6 }, |
| 14144 | { CLZ_R6, CLZ_R6, CLZ_MMR6 }, |
| 14145 | { CMP_EQ_D, CMP_EQ_D, CMP_EQ_D_MMR6 }, |
| 14146 | { CMP_EQ_S, CMP_EQ_S, CMP_EQ_S_MMR6 }, |
| 14147 | { CMP_F_D, CMP_F_D, CMP_AF_D_MMR6 }, |
| 14148 | { CMP_F_S, CMP_F_S, CMP_AF_S_MMR6 }, |
| 14149 | { CMP_LE_D, CMP_LE_D, CMP_LE_D_MMR6 }, |
| 14150 | { CMP_LE_S, CMP_LE_S, CMP_LE_S_MMR6 }, |
| 14151 | { CMP_LT_D, CMP_LT_D, CMP_LT_D_MMR6 }, |
| 14152 | { CMP_LT_S, CMP_LT_S, CMP_LT_S_MMR6 }, |
| 14153 | { CMP_SAF_D, CMP_SAF_D, CMP_SAF_D_MMR6 }, |
| 14154 | { CMP_SAF_S, CMP_SAF_S, CMP_SAF_S_MMR6 }, |
| 14155 | { CMP_SEQ_D, CMP_SEQ_D, CMP_SEQ_D_MMR6 }, |
| 14156 | { CMP_SEQ_S, CMP_SEQ_S, CMP_SEQ_S_MMR6 }, |
| 14157 | { CMP_SLE_D, CMP_SLE_D, CMP_SLE_D_MMR6 }, |
| 14158 | { CMP_SLE_S, CMP_SLE_S, CMP_SLE_S_MMR6 }, |
| 14159 | { CMP_SLT_D, CMP_SLT_D, CMP_SLT_D_MMR6 }, |
| 14160 | { CMP_SLT_S, CMP_SLT_S, CMP_SLT_S_MMR6 }, |
| 14161 | { CMP_SUEQ_D, CMP_SUEQ_D, CMP_SUEQ_D_MMR6 }, |
| 14162 | { CMP_SUEQ_S, CMP_SUEQ_S, CMP_SUEQ_S_MMR6 }, |
| 14163 | { CMP_SULE_D, CMP_SULE_D, CMP_SULE_D_MMR6 }, |
| 14164 | { CMP_SULE_S, CMP_SULE_S, CMP_SULE_S_MMR6 }, |
| 14165 | { CMP_SULT_D, CMP_SULT_D, CMP_SULT_D_MMR6 }, |
| 14166 | { CMP_SULT_S, CMP_SULT_S, CMP_SULT_S_MMR6 }, |
| 14167 | { CMP_SUN_D, CMP_SUN_D, CMP_SUN_D_MMR6 }, |
| 14168 | { CMP_SUN_S, CMP_SUN_S, CMP_SUN_S_MMR6 }, |
| 14169 | { CMP_UEQ_D, CMP_UEQ_D, CMP_UEQ_D_MMR6 }, |
| 14170 | { CMP_UEQ_S, CMP_UEQ_S, CMP_UEQ_S_MMR6 }, |
| 14171 | { CMP_ULE_D, CMP_ULE_D, CMP_ULE_D_MMR6 }, |
| 14172 | { CMP_ULE_S, CMP_ULE_S, CMP_ULE_S_MMR6 }, |
| 14173 | { CMP_ULT_D, CMP_ULT_D, CMP_ULT_D_MMR6 }, |
| 14174 | { CMP_ULT_S, CMP_ULT_S, CMP_ULT_S_MMR6 }, |
| 14175 | { CMP_UN_D, CMP_UN_D, CMP_UN_D_MMR6 }, |
| 14176 | { CMP_UN_S, CMP_UN_S, CMP_UN_S_MMR6 }, |
| 14177 | { CRC32B, CRC32B, INSTRUCTION_LIST_END }, |
| 14178 | { CRC32CB, CRC32CB, INSTRUCTION_LIST_END }, |
| 14179 | { CRC32CD, CRC32CD, INSTRUCTION_LIST_END }, |
| 14180 | { CRC32CH, CRC32CH, INSTRUCTION_LIST_END }, |
| 14181 | { CRC32CW, CRC32CW, INSTRUCTION_LIST_END }, |
| 14182 | { CRC32D, CRC32D, INSTRUCTION_LIST_END }, |
| 14183 | { CRC32H, CRC32H, INSTRUCTION_LIST_END }, |
| 14184 | { CRC32W, CRC32W, INSTRUCTION_LIST_END }, |
| 14185 | { DIV, DIV, DIV_MMR6 }, |
| 14186 | { DIVU, DIVU, DIVU_MMR6 }, |
| 14187 | { DVP, DVP, DVP_MMR6 }, |
| 14188 | { EVP, EVP, EVP_MMR6 }, |
| 14189 | { GINVI, GINVI, GINVI_MMR6 }, |
| 14190 | { GINVT, GINVT, GINVT_MMR6 }, |
| 14191 | { JIALC, JIALC, JIALC_MMR6 }, |
| 14192 | { JIC, JIC, JIC_MMR6 }, |
| 14193 | { LSA_R6, LSA_R6, LSA_MMR6 }, |
| 14194 | { LWPC, LWPC, LWPC_MMR6 }, |
| 14195 | { MOD, MOD, MOD_MMR6 }, |
| 14196 | { MODU, MODU, MODU_MMR6 }, |
| 14197 | { MUH, MUH, MUH_MMR6 }, |
| 14198 | { MUHU, MUHU, MUHU_MMR6 }, |
| 14199 | { MULU, MULU, MULU_MMR6 }, |
| 14200 | { MUL_R6, MUL_R6, MUL_MMR6 }, |
| 14201 | { PREF_R6, PREF_R6, PREF_MMR6 }, |
| 14202 | { SELEQZ, SELEQZ, SELEQZ_MMR6 }, |
| 14203 | { SELEQZ_D, SELEQZ_D, SELEQZ_D_MMR6 }, |
| 14204 | { SELEQZ_S, SELEQZ_S, SELEQZ_S_MMR6 }, |
| 14205 | { SELNEZ, SELNEZ, SELNEZ_MMR6 }, |
| 14206 | { SELNEZ_D, SELNEZ_D, SELNEZ_D_MMR6 }, |
| 14207 | { SELNEZ_S, SELNEZ_S, SELNEZ_S_MMR6 }, |
| 14208 | { SEL_D, SEL_D, SEL_D_MMR6 }, |
| 14209 | { SEL_S, SEL_S, SEL_S_MMR6 }, |
| 14210 | }; // End of Table |
| 14211 | |
| 14212 | unsigned mid; |
| 14213 | unsigned start = 0; |
| 14214 | unsigned end = 96; |
| 14215 | while (start < end) { |
| 14216 | mid = start + (end - start) / 2; |
| 14217 | if (Opcode == Table[mid][0]) |
| 14218 | break; |
| 14219 | if (Opcode < Table[mid][0]) |
| 14220 | end = mid; |
| 14221 | else |
| 14222 | start = mid + 1; |
| 14223 | } |
| 14224 | if (start == end) |
| 14225 | return -1; // Instruction doesn't exist in this table. |
| 14226 | |
| 14227 | if (inArch == Arch_mipsr6) |
| 14228 | return Table[mid][1]; |
| 14229 | if (inArch == Arch_micromipsr6) |
| 14230 | return Table[mid][2]; |
| 14231 | llvm_unreachable("Unrecognized column value!"); |
| 14232 | } |
| 14233 | |
| 14234 | // Std2MicroMips |
| 14235 | LLVM_READONLY |
| 14236 | int32_t Std2MicroMips(uint32_t Opcode, enum Arch inArch) { |
| 14237 | using namespace Mips; |
| 14238 | static constexpr uint32_t Table[][3] = { |
| 14239 | { ADD, ADD, ADD_MM }, |
| 14240 | { ADDi, ADDi, ADDi_MM }, |
| 14241 | { ADDiu, ADDiu, ADDiu_MM }, |
| 14242 | { ADDu, ADDu, ADDu_MM }, |
| 14243 | { AND, AND, AND_MM }, |
| 14244 | { ANDi, ANDi, ANDi_MM }, |
| 14245 | { BC1F, BC1F, BC1F_MM }, |
| 14246 | { BC1FL, BC1FL, INSTRUCTION_LIST_END }, |
| 14247 | { BC1T, BC1T, BC1T_MM }, |
| 14248 | { BC1TL, BC1TL, INSTRUCTION_LIST_END }, |
| 14249 | { BEQ, BEQ, BEQ_MM }, |
| 14250 | { BEQL, BEQL, INSTRUCTION_LIST_END }, |
| 14251 | { BGEZ, BGEZ, BGEZ_MM }, |
| 14252 | { BGEZAL, BGEZAL, BGEZAL_MM }, |
| 14253 | { BGEZALL, BGEZALL, INSTRUCTION_LIST_END }, |
| 14254 | { BGEZL, BGEZL, INSTRUCTION_LIST_END }, |
| 14255 | { BGTZ, BGTZ, BGTZ_MM }, |
| 14256 | { BGTZL, BGTZL, INSTRUCTION_LIST_END }, |
| 14257 | { BLEZ, BLEZ, BLEZ_MM }, |
| 14258 | { BLEZL, BLEZL, INSTRUCTION_LIST_END }, |
| 14259 | { BLTZ, BLTZ, BLTZ_MM }, |
| 14260 | { BLTZAL, BLTZAL, BLTZAL_MM }, |
| 14261 | { BLTZALL, BLTZALL, INSTRUCTION_LIST_END }, |
| 14262 | { BLTZL, BLTZL, INSTRUCTION_LIST_END }, |
| 14263 | { BNE, BNE, BNE_MM }, |
| 14264 | { BNEL, BNEL, INSTRUCTION_LIST_END }, |
| 14265 | { BREAK, BREAK, BREAK_MM }, |
| 14266 | { CACHE, CACHE, CACHE_MM }, |
| 14267 | { CACHEE, CACHEE, CACHEE_MM }, |
| 14268 | { CEIL_W_D32, CEIL_W_D32, CEIL_W_MM }, |
| 14269 | { CEIL_W_S, CEIL_W_S, CEIL_W_S_MM }, |
| 14270 | { CFC1, CFC1, CFC1_MM }, |
| 14271 | { CLO, CLO, CLO_MM }, |
| 14272 | { CLZ, CLZ, CLZ_MM }, |
| 14273 | { CTC1, CTC1, CTC1_MM }, |
| 14274 | { CVT_D32_S, CVT_D32_S, CVT_D32_S_MM }, |
| 14275 | { CVT_D32_W, CVT_D32_W, CVT_D32_W_MM }, |
| 14276 | { CVT_L_D64, CVT_L_D64, CVT_L_D64_MM }, |
| 14277 | { CVT_L_S, CVT_L_S, CVT_L_S_MM }, |
| 14278 | { CVT_S_D32, CVT_S_D32, CVT_S_D32_MM }, |
| 14279 | { CVT_S_W, CVT_S_W, CVT_S_W_MM }, |
| 14280 | { CVT_W_D32, CVT_W_D32, CVT_W_D32_MM }, |
| 14281 | { CVT_W_S, CVT_W_S, CVT_W_S_MM }, |
| 14282 | { C_EQ_D32, C_EQ_D32, C_EQ_D32_MM }, |
| 14283 | { C_EQ_D64, C_EQ_D64, C_EQ_D64_MM }, |
| 14284 | { C_EQ_S, C_EQ_S, C_EQ_S_MM }, |
| 14285 | { C_F_D32, C_F_D32, C_F_D32_MM }, |
| 14286 | { C_F_D64, C_F_D64, C_F_D64_MM }, |
| 14287 | { C_F_S, C_F_S, C_F_S_MM }, |
| 14288 | { C_LE_D32, C_LE_D32, C_LE_D32_MM }, |
| 14289 | { C_LE_D64, C_LE_D64, C_LE_D64_MM }, |
| 14290 | { C_LE_S, C_LE_S, C_LE_S_MM }, |
| 14291 | { C_LT_D32, C_LT_D32, C_LT_D32_MM }, |
| 14292 | { C_LT_D64, C_LT_D64, C_LT_D64_MM }, |
| 14293 | { C_LT_S, C_LT_S, C_LT_S_MM }, |
| 14294 | { C_NGE_D32, C_NGE_D32, C_NGE_D32_MM }, |
| 14295 | { C_NGE_D64, C_NGE_D64, C_NGE_D64_MM }, |
| 14296 | { C_NGE_S, C_NGE_S, C_NGE_S_MM }, |
| 14297 | { C_NGLE_D32, C_NGLE_D32, C_NGLE_D32_MM }, |
| 14298 | { C_NGLE_D64, C_NGLE_D64, C_NGLE_D64_MM }, |
| 14299 | { C_NGLE_S, C_NGLE_S, C_NGLE_S_MM }, |
| 14300 | { C_NGL_D32, C_NGL_D32, C_NGL_D32_MM }, |
| 14301 | { C_NGL_D64, C_NGL_D64, C_NGL_D64_MM }, |
| 14302 | { C_NGL_S, C_NGL_S, C_NGL_S_MM }, |
| 14303 | { C_NGT_D32, C_NGT_D32, C_NGT_D32_MM }, |
| 14304 | { C_NGT_D64, C_NGT_D64, C_NGT_D64_MM }, |
| 14305 | { C_NGT_S, C_NGT_S, C_NGT_S_MM }, |
| 14306 | { C_OLE_D32, C_OLE_D32, C_OLE_D32_MM }, |
| 14307 | { C_OLE_D64, C_OLE_D64, C_OLE_D64_MM }, |
| 14308 | { C_OLE_S, C_OLE_S, C_OLE_S_MM }, |
| 14309 | { C_OLT_D32, C_OLT_D32, C_OLT_D32_MM }, |
| 14310 | { C_OLT_D64, C_OLT_D64, C_OLT_D64_MM }, |
| 14311 | { C_OLT_S, C_OLT_S, C_OLT_S_MM }, |
| 14312 | { C_SEQ_D32, C_SEQ_D32, C_SEQ_D32_MM }, |
| 14313 | { C_SEQ_D64, C_SEQ_D64, C_SEQ_D64_MM }, |
| 14314 | { C_SEQ_S, C_SEQ_S, C_SEQ_S_MM }, |
| 14315 | { C_SF_D32, C_SF_D32, C_SF_D32_MM }, |
| 14316 | { C_SF_D64, C_SF_D64, C_SF_D64_MM }, |
| 14317 | { C_SF_S, C_SF_S, C_SF_S_MM }, |
| 14318 | { C_UEQ_D32, C_UEQ_D32, C_UEQ_D32_MM }, |
| 14319 | { C_UEQ_D64, C_UEQ_D64, C_UEQ_D64_MM }, |
| 14320 | { C_UEQ_S, C_UEQ_S, C_UEQ_S_MM }, |
| 14321 | { C_ULE_D32, C_ULE_D32, C_ULE_D32_MM }, |
| 14322 | { C_ULE_D64, C_ULE_D64, C_ULE_D64_MM }, |
| 14323 | { C_ULE_S, C_ULE_S, C_ULE_S_MM }, |
| 14324 | { C_ULT_D32, C_ULT_D32, C_ULT_D32_MM }, |
| 14325 | { C_ULT_D64, C_ULT_D64, C_ULT_D64_MM }, |
| 14326 | { C_ULT_S, C_ULT_S, C_ULT_S_MM }, |
| 14327 | { C_UN_D32, C_UN_D32, C_UN_D32_MM }, |
| 14328 | { C_UN_D64, C_UN_D64, C_UN_D64_MM }, |
| 14329 | { C_UN_S, C_UN_S, C_UN_S_MM }, |
| 14330 | { DERET, DERET, DERET_MM }, |
| 14331 | { DI, DI, DI_MM }, |
| 14332 | { EHB, EHB, EHB_MM }, |
| 14333 | { EI, EI, EI_MM }, |
| 14334 | { ERET, ERET, ERET_MM }, |
| 14335 | { ERETNC, ERETNC, INSTRUCTION_LIST_END }, |
| 14336 | { EXT, EXT, EXT_MM }, |
| 14337 | { FABS_D32, FABS_D32, FABS_D32_MM }, |
| 14338 | { FABS_S, FABS_S, FABS_S_MM }, |
| 14339 | { FADD_D32, FADD_D32, FADD_D32_MM }, |
| 14340 | { FADD_S, FADD_S, FADD_S_MM }, |
| 14341 | { FCMP_D32, FCMP_D32, FCMP_D32_MM }, |
| 14342 | { FCMP_S32, FCMP_S32, FCMP_S32_MM }, |
| 14343 | { FDIV_D32, FDIV_D32, FDIV_D32_MM }, |
| 14344 | { FDIV_S, FDIV_S, FDIV_S_MM }, |
| 14345 | { FLOOR_W_D32, FLOOR_W_D32, FLOOR_W_MM }, |
| 14346 | { FLOOR_W_S, FLOOR_W_S, FLOOR_W_S_MM }, |
| 14347 | { FMOV_D32, FMOV_D32, FMOV_D32_MM }, |
| 14348 | { FMOV_S, FMOV_S, FMOV_S_MM }, |
| 14349 | { FMUL_D32, FMUL_D32, FMUL_D32_MM }, |
| 14350 | { FMUL_S, FMUL_S, FMUL_S_MM }, |
| 14351 | { FNEG_D32, FNEG_D32, FNEG_D32_MM }, |
| 14352 | { FNEG_S, FNEG_S, FNEG_S_MM }, |
| 14353 | { FSQRT_D32, FSQRT_D32, FSQRT_D32_MM }, |
| 14354 | { FSQRT_S, FSQRT_S, FSQRT_S_MM }, |
| 14355 | { FSUB_D32, FSUB_D32, FSUB_D32_MM }, |
| 14356 | { FSUB_S, FSUB_S, FSUB_S_MM }, |
| 14357 | { HYPCALL, HYPCALL, HYPCALL_MM }, |
| 14358 | { INS, INS, INS_MM }, |
| 14359 | { J, J, J_MM }, |
| 14360 | { JAL, JAL, JAL_MM }, |
| 14361 | { JALR_HB, JALR_HB, JALR_HB_MM }, |
| 14362 | { JALX, JALX, JALX_MM }, |
| 14363 | { JR, JR, JR_MM }, |
| 14364 | { JR_HB, JR_HB, JR_HB_MM }, |
| 14365 | { LB, LB, LB_MM }, |
| 14366 | { LBE, LBE, LBE_MM }, |
| 14367 | { LBu, LBu, LBu_MM }, |
| 14368 | { LBuE, LBuE, LBuE_MM }, |
| 14369 | { LDC1, LDC1, LDC1_MM_D32 }, |
| 14370 | { LEA_ADDiu, LEA_ADDiu, LEA_ADDiu_MM }, |
| 14371 | { LH, LH, LH_MM }, |
| 14372 | { LHE, LHE, LHE_MM }, |
| 14373 | { LHu, LHu, LHu_MM }, |
| 14374 | { LHuE, LHuE, LHuE_MM }, |
| 14375 | { LLE, LLE, LLE_MM }, |
| 14376 | { LUXC1, LUXC1, LUXC1_MM }, |
| 14377 | { LUi, LUi, LUi_MM }, |
| 14378 | { LW, LW, LW_MM }, |
| 14379 | { LWC1, LWC1, LWC1_MM }, |
| 14380 | { LWE, LWE, LWE_MM }, |
| 14381 | { LWL, LWL, LWL_MM }, |
| 14382 | { LWLE, LWLE, LWLE_MM }, |
| 14383 | { LWR, LWR, LWR_MM }, |
| 14384 | { LWRE, LWRE, LWRE_MM }, |
| 14385 | { LWXC1, LWXC1, LWXC1_MM }, |
| 14386 | { LWu, LWu, LWU_MM }, |
| 14387 | { MADD, MADD, MADD_MM }, |
| 14388 | { MADDU, MADDU, MADDU_MM }, |
| 14389 | { MADD_D32, MADD_D32, MADD_D32_MM }, |
| 14390 | { MADD_S, MADD_S, MADD_S_MM }, |
| 14391 | { MFC1, MFC1, MFC1_MM }, |
| 14392 | { MFGC0, MFGC0, MFGC0_MM }, |
| 14393 | { MFHC1_D32, MFHC1_D32, MFHC1_D32_MM }, |
| 14394 | { MFHGC0, MFHGC0, MFHGC0_MM }, |
| 14395 | { MFHI, MFHI, MFHI_MM }, |
| 14396 | { MFLO, MFLO, MFLO_MM }, |
| 14397 | { MOVF_D32, MOVF_D32, MOVF_D32_MM }, |
| 14398 | { MOVF_I, MOVF_I, MOVF_I_MM }, |
| 14399 | { MOVF_S, MOVF_S, MOVF_S_MM }, |
| 14400 | { MOVN_I_D32, MOVN_I_D32, MOVN_I_D32_MM }, |
| 14401 | { MOVN_I_I, MOVN_I_I, MOVN_I_MM }, |
| 14402 | { MOVN_I_S, MOVN_I_S, MOVN_I_S_MM }, |
| 14403 | { MOVT_D32, MOVT_D32, MOVT_D32_MM }, |
| 14404 | { MOVT_I, MOVT_I, MOVT_I_MM }, |
| 14405 | { MOVT_S, MOVT_S, MOVT_S_MM }, |
| 14406 | { MOVZ_I_D32, MOVZ_I_D32, MOVZ_I_D32_MM }, |
| 14407 | { MOVZ_I_I, MOVZ_I_I, MOVZ_I_MM }, |
| 14408 | { MOVZ_I_S, MOVZ_I_S, MOVZ_I_S_MM }, |
| 14409 | { MSUB, MSUB, MSUB_MM }, |
| 14410 | { MSUBU, MSUBU, MSUBU_MM }, |
| 14411 | { MSUB_D32, MSUB_D32, MSUB_D32_MM }, |
| 14412 | { MSUB_S, MSUB_S, MSUB_S_MM }, |
| 14413 | { MTC1, MTC1, MTC1_MM }, |
| 14414 | { MTGC0, MTGC0, MTGC0_MM }, |
| 14415 | { MTHC1_D32, MTHC1_D32, MTHC1_D32_MM }, |
| 14416 | { MTHGC0, MTHGC0, MTHGC0_MM }, |
| 14417 | { MTHI, MTHI, MTHI_MM }, |
| 14418 | { MTLO, MTLO, MTLO_MM }, |
| 14419 | { MUL, MUL, MUL_MM }, |
| 14420 | { MULT, MULT, MULT_MM }, |
| 14421 | { MULTu, MULTu, MULTu_MM }, |
| 14422 | { NMADD_D32, NMADD_D32, NMADD_D32_MM }, |
| 14423 | { NMADD_S, NMADD_S, NMADD_S_MM }, |
| 14424 | { NMSUB_D32, NMSUB_D32, NMSUB_D32_MM }, |
| 14425 | { NMSUB_S, NMSUB_S, NMSUB_S_MM }, |
| 14426 | { NOR, NOR, NOR_MM }, |
| 14427 | { OR, OR, OR_MM }, |
| 14428 | { ORi, ORi, ORi_MM }, |
| 14429 | { PAUSE, PAUSE, PAUSE_MM }, |
| 14430 | { PREF, PREF, PREF_MM }, |
| 14431 | { PREFE, PREFE, PREFE_MM }, |
| 14432 | { RDHWR, RDHWR, RDHWR_MM }, |
| 14433 | { RECIP_D32, RECIP_D32, RECIP_D32_MM }, |
| 14434 | { RECIP_D64, RECIP_D64, RECIP_D64_MM }, |
| 14435 | { RECIP_S, RECIP_S, RECIP_S_MM }, |
| 14436 | { ROTR, ROTR, ROTR_MM }, |
| 14437 | { ROTRV, ROTRV, ROTRV_MM }, |
| 14438 | { ROUND_W_D32, ROUND_W_D32, ROUND_W_MM }, |
| 14439 | { ROUND_W_S, ROUND_W_S, ROUND_W_S_MM }, |
| 14440 | { RSQRT_D32, RSQRT_D32, RSQRT_D32_MM }, |
| 14441 | { RSQRT_D64, RSQRT_D64, RSQRT_D64_MM }, |
| 14442 | { RSQRT_S, RSQRT_S, RSQRT_S_MM }, |
| 14443 | { SB, SB, SB_MM }, |
| 14444 | { SBE, SBE, SBE_MM }, |
| 14445 | { SCE, SCE, SCE_MM }, |
| 14446 | { SDBBP, SDBBP, SDBBP_MM }, |
| 14447 | { SDC1, SDC1, INSTRUCTION_LIST_END }, |
| 14448 | { SDIV, SDIV, SDIV_MM }, |
| 14449 | { SEB, SEB, SEB_MM }, |
| 14450 | { SEH, SEH, SEH_MM }, |
| 14451 | { SH, SH, SH_MM }, |
| 14452 | { SHE, SHE, SHE_MM }, |
| 14453 | { SLL, SLL, SLL_MM }, |
| 14454 | { SLLV, SLLV, SLLV_MM }, |
| 14455 | { SLT, SLT, SLT_MM }, |
| 14456 | { SLTi, SLTi, SLTi_MM }, |
| 14457 | { SLTiu, SLTiu, SLTiu_MM }, |
| 14458 | { SLTu, SLTu, SLTu_MM }, |
| 14459 | { SRA, SRA, SRA_MM }, |
| 14460 | { SRAV, SRAV, SRAV_MM }, |
| 14461 | { SRL, SRL, SRL_MM }, |
| 14462 | { SRLV, SRLV, SRLV_MM }, |
| 14463 | { SSNOP, SSNOP, SSNOP_MM }, |
| 14464 | { SUB, SUB, SUB_MM }, |
| 14465 | { SUBu, SUBu, SUBu_MM }, |
| 14466 | { SUXC1, SUXC1, SUXC1_MM }, |
| 14467 | { SW, SW, SW_MM }, |
| 14468 | { SWC1, SWC1, SWC1_MM }, |
| 14469 | { SWE, SWE, SWE_MM }, |
| 14470 | { SWL, SWL, SWL_MM }, |
| 14471 | { SWLE, SWLE, SWLE_MM }, |
| 14472 | { SWR, SWR, SWR_MM }, |
| 14473 | { SWRE, SWRE, SWRE_MM }, |
| 14474 | { SWXC1, SWXC1, SWXC1_MM }, |
| 14475 | { SYNC, SYNC, SYNC_MM }, |
| 14476 | { SYNCI, SYNCI, SYNCI_MM }, |
| 14477 | { SYSCALL, SYSCALL, SYSCALL_MM }, |
| 14478 | { TEQ, TEQ, TEQ_MM }, |
| 14479 | { TEQI, TEQI, TEQI_MM }, |
| 14480 | { TGE, TGE, TGE_MM }, |
| 14481 | { TGEI, TGEI, TGEI_MM }, |
| 14482 | { TGEIU, TGEIU, TGEIU_MM }, |
| 14483 | { TGEU, TGEU, TGEU_MM }, |
| 14484 | { TLBGINV, TLBGINV, TLBGINV_MM }, |
| 14485 | { TLBGINVF, TLBGINVF, TLBGINVF_MM }, |
| 14486 | { TLBGP, TLBGP, TLBGP_MM }, |
| 14487 | { TLBGR, TLBGR, TLBGR_MM }, |
| 14488 | { TLBGWI, TLBGWI, TLBGWI_MM }, |
| 14489 | { TLBGWR, TLBGWR, TLBGWR_MM }, |
| 14490 | { TLBP, TLBP, TLBP_MM }, |
| 14491 | { TLBR, TLBR, TLBR_MM }, |
| 14492 | { TLBWI, TLBWI, TLBWI_MM }, |
| 14493 | { TLBWR, TLBWR, TLBWR_MM }, |
| 14494 | { TLT, TLT, TLT_MM }, |
| 14495 | { TLTI, TLTI, TLTI_MM }, |
| 14496 | { TLTU, TLTU, TLTU_MM }, |
| 14497 | { TNE, TNE, TNE_MM }, |
| 14498 | { TNEI, TNEI, TNEI_MM }, |
| 14499 | { TRUNC_W_D32, TRUNC_W_D32, TRUNC_W_MM }, |
| 14500 | { TRUNC_W_S, TRUNC_W_S, TRUNC_W_S_MM }, |
| 14501 | { TTLTIU, TTLTIU, TLTIU_MM }, |
| 14502 | { UDIV, UDIV, UDIV_MM }, |
| 14503 | { WAIT, WAIT, WAIT_MM }, |
| 14504 | { WSBH, WSBH, WSBH_MM }, |
| 14505 | { XOR, XOR, XOR_MM }, |
| 14506 | { XORi, XORi, XORi_MM }, |
| 14507 | }; // End of Table |
| 14508 | |
| 14509 | unsigned mid; |
| 14510 | unsigned start = 0; |
| 14511 | unsigned end = 268; |
| 14512 | while (start < end) { |
| 14513 | mid = start + (end - start) / 2; |
| 14514 | if (Opcode == Table[mid][0]) |
| 14515 | break; |
| 14516 | if (Opcode < Table[mid][0]) |
| 14517 | end = mid; |
| 14518 | else |
| 14519 | start = mid + 1; |
| 14520 | } |
| 14521 | if (start == end) |
| 14522 | return -1; // Instruction doesn't exist in this table. |
| 14523 | |
| 14524 | if (inArch == Arch_se) |
| 14525 | return Table[mid][1]; |
| 14526 | if (inArch == Arch_micromips) |
| 14527 | return Table[mid][2]; |
| 14528 | llvm_unreachable("Unrecognized column value!"); |
| 14529 | } |
| 14530 | |
| 14531 | // Std2MicroMipsR6 |
| 14532 | LLVM_READONLY |
| 14533 | int32_t Std2MicroMipsR6(uint32_t Opcode, enum Arch inArch) { |
| 14534 | using namespace Mips; |
| 14535 | static constexpr uint32_t Table[][3] = { |
| 14536 | { ADD, ADD, ADD_MMR6 }, |
| 14537 | { ADDiu, ADDiu, ADDIU_MMR6 }, |
| 14538 | { ADDu, ADDu, ADDU_MMR6 }, |
| 14539 | { AND, AND, AND_MMR6 }, |
| 14540 | { ANDi, ANDi, ANDI_MMR6 }, |
| 14541 | { BREAK, BREAK, BREAK_MMR6 }, |
| 14542 | { CEIL_W_D64, CEIL_W_D64, CEIL_W_D_MMR6 }, |
| 14543 | { CEIL_W_S, CEIL_W_S, CEIL_W_S_MMR6 }, |
| 14544 | { CVT_W_D64, CVT_W_D64, INSTRUCTION_LIST_END }, |
| 14545 | { DI, DI, DI_MMR6 }, |
| 14546 | { EI, EI, EI_MMR6 }, |
| 14547 | { EXT, EXT, EXT_MMR6 }, |
| 14548 | { FABS_D64, FABS_D64, INSTRUCTION_LIST_END }, |
| 14549 | { FLOOR_W_D64, FLOOR_W_D64, FLOOR_W_D_MMR6 }, |
| 14550 | { FLOOR_W_S, FLOOR_W_S, FLOOR_W_S_MMR6 }, |
| 14551 | { FMOV_D64, FMOV_D64, FMOV_D_MMR6 }, |
| 14552 | { FNEG_D64, FNEG_D64, INSTRUCTION_LIST_END }, |
| 14553 | { FSQRT_D64, FSQRT_D64, INSTRUCTION_LIST_END }, |
| 14554 | { FSQRT_S, FSQRT_S, INSTRUCTION_LIST_END }, |
| 14555 | { INS, INS, INS_MMR6 }, |
| 14556 | { LDC1, LDC1, INSTRUCTION_LIST_END }, |
| 14557 | { LDC164, LDC164, LDC1_D64_MMR6 }, |
| 14558 | { LDC2, LDC2, LDC2_MMR6 }, |
| 14559 | { LW, LW, LW_MMR6 }, |
| 14560 | { LWC2, LWC2, LWC2_MMR6 }, |
| 14561 | { MFC1, MFC1, MFC1_MMR6 }, |
| 14562 | { MTC1, MTC1, MTC1_MMR6 }, |
| 14563 | { MTHC1_D32, MTHC1_D32, INSTRUCTION_LIST_END }, |
| 14564 | { NOR, NOR, NOR_MMR6 }, |
| 14565 | { OR, OR, OR_MMR6 }, |
| 14566 | { ORi, ORi, ORI_MMR6 }, |
| 14567 | { PAUSE, PAUSE, PAUSE_MMR6 }, |
| 14568 | { ROUND_W_D64, ROUND_W_D64, ROUND_W_D_MMR6 }, |
| 14569 | { ROUND_W_S, ROUND_W_S, ROUND_W_S_MMR6 }, |
| 14570 | { SB, SB, SB_MMR6 }, |
| 14571 | { SDC164, SDC164, SDC1_D64_MMR6 }, |
| 14572 | { SDC2, SDC2, SDC2_MMR6 }, |
| 14573 | { SEB, SEB, INSTRUCTION_LIST_END }, |
| 14574 | { SEH, SEH, INSTRUCTION_LIST_END }, |
| 14575 | { SSNOP, SSNOP, SSNOP_MMR6 }, |
| 14576 | { SUB, SUB, SUB_MMR6 }, |
| 14577 | { SUBu, SUBu, SUBU_MMR6 }, |
| 14578 | { SW, SW, SW_MMR6 }, |
| 14579 | { SWC2, SWC2, SWC2_MMR6 }, |
| 14580 | { SYNC, SYNC, SYNC_MMR6 }, |
| 14581 | { SYNCI, SYNCI, SYNCI_MMR6 }, |
| 14582 | { TRUNC_W_D64, TRUNC_W_D64, TRUNC_W_D_MMR6 }, |
| 14583 | { TRUNC_W_S, TRUNC_W_S, TRUNC_W_S_MMR6 }, |
| 14584 | { WAIT, WAIT, WAIT_MMR6 }, |
| 14585 | { XOR, XOR, XOR_MMR6 }, |
| 14586 | { XORi, XORi, XORI_MMR6 }, |
| 14587 | }; // End of Table |
| 14588 | |
| 14589 | unsigned mid; |
| 14590 | unsigned start = 0; |
| 14591 | unsigned end = 51; |
| 14592 | while (start < end) { |
| 14593 | mid = start + (end - start) / 2; |
| 14594 | if (Opcode == Table[mid][0]) |
| 14595 | break; |
| 14596 | if (Opcode < Table[mid][0]) |
| 14597 | end = mid; |
| 14598 | else |
| 14599 | start = mid + 1; |
| 14600 | } |
| 14601 | if (start == end) |
| 14602 | return -1; // Instruction doesn't exist in this table. |
| 14603 | |
| 14604 | if (inArch == Arch_se) |
| 14605 | return Table[mid][1]; |
| 14606 | if (inArch == Arch_micromipsr6) |
| 14607 | return Table[mid][2]; |
| 14608 | llvm_unreachable("Unrecognized column value!"); |
| 14609 | } |
| 14610 | |
| 14611 | |
| 14612 | } // namespace llvm::Mips |
| 14613 | |
| 14614 | #endif // GET_INSTRMAP_INFO |
| 14615 | |
| 14616 |
Generated while processing llvm_projects/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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