| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Instruction Enum Values and Descriptors *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_INSTRINFO_ENUM |
| 10 | #undef GET_INSTRINFO_ENUM |
| 11 | |
| 12 | namespace llvm::Mips { |
| 13 | |
| 14 | enum { |
| 15 | PHI = 0, // Target.td:1200 |
| 16 | INLINEASM = 1, // Target.td:1206 |
| 17 | INLINEASM_BR = 2, // Target.td:1212 |
| 18 | CFI_INSTRUCTION = 3, // Target.td:1221 |
| 19 | EH_LABEL = 4, // Target.td:1230 |
| 20 | GC_LABEL = 5, // Target.td:1239 |
| 21 | ANNOTATION_LABEL = 6, // Target.td:1248 |
| 22 | KILL = 7, // Target.td:1256 |
| 23 | EXTRACT_SUBREG = 8, // Target.td:1263 |
| 24 | INSERT_SUBREG = 9, // Target.td:1269 |
| 25 | IMPLICIT_DEF = 10, // Target.td:1276 |
| 26 | INIT_UNDEF = 11, // Target.td:1285 |
| 27 | SUBREG_TO_REG = 12, // Target.td:1292 |
| 28 | COPY_TO_REGCLASS = 13, // Target.td:1298 |
| 29 | DBG_VALUE = 14, // Target.td:1305 |
| 30 | DBG_VALUE_LIST = 15, // Target.td:1312 |
| 31 | DBG_INSTR_REF = 16, // Target.td:1319 |
| 32 | DBG_PHI = 17, // Target.td:1326 |
| 33 | DBG_LABEL = 18, // Target.td:1333 |
| 34 | REG_SEQUENCE = 19, // Target.td:1340 |
| 35 | COPY = 20, // Target.td:1347 |
| 36 | COPY_LANEMASK = 21, // Target.td:1355 |
| 37 | BUNDLE = 22, // Target.td:1362 |
| 38 | LIFETIME_START = 23, // Target.td:1368 |
| 39 | LIFETIME_END = 24, // Target.td:1375 |
| 40 | PSEUDO_PROBE = 25, // Target.td:1382 |
| 41 | ARITH_FENCE = 26, // Target.td:1389 |
| 42 | STACKMAP = 27, // Target.td:1398 |
| 43 | FENTRY_CALL = 28, // Target.td:1533 |
| 44 | PATCHPOINT = 29, // Target.td:1406 |
| 45 | LOAD_STACK_GUARD = 30, // Target.td:1424 |
| 46 | PREALLOCATED_SETUP = 31, // Target.td:1432 |
| 47 | PREALLOCATED_ARG = 32, // Target.td:1438 |
| 48 | STATEPOINT = 33, // Target.td:1415 |
| 49 | LOCAL_ESCAPE = 34, // Target.td:1444 |
| 50 | FAULTING_OP = 35, // Target.td:1453 |
| 51 | PATCHABLE_OP = 36, // Target.td:1473 |
| 52 | PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481 |
| 53 | PATCHABLE_RET = 38, // Target.td:1488 |
| 54 | PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497 |
| 55 | PATCHABLE_TAIL_CALL = 40, // Target.td:1505 |
| 56 | PATCHABLE_EVENT_CALL = 41, // Target.td:1513 |
| 57 | PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523 |
| 58 | ICALL_BRANCH_FUNNEL = 43, // Target.td:1543 |
| 59 | FAKE_USE = 44, // Target.td:1463 |
| 60 | MEMBARRIER = 45, // Target.td:1549 |
| 61 | JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557 |
| 62 | RELOC_NONE = 47, // Target.td:1565 |
| 63 | CONVERGENCECTRL_ENTRY = 48, // Target.td:1576 |
| 64 | CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572 |
| 65 | CONVERGENCECTRL_LOOP = 50, // Target.td:1580 |
| 66 | CONVERGENCECTRL_GLUE = 51, // Target.td:1584 |
| 67 | G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865 |
| 68 | G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857 |
| 69 | G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872 |
| 70 | G_ADD = 55, // GenericOpcodes.td:300 |
| 71 | G_SUB = 56, // GenericOpcodes.td:308 |
| 72 | G_MUL = 57, // GenericOpcodes.td:316 |
| 73 | G_SDIV = 58, // GenericOpcodes.td:324 |
| 74 | G_UDIV = 59, // GenericOpcodes.td:332 |
| 75 | G_SREM = 60, // GenericOpcodes.td:340 |
| 76 | G_UREM = 61, // GenericOpcodes.td:348 |
| 77 | G_SDIVREM = 62, // GenericOpcodes.td:356 |
| 78 | G_UDIVREM = 63, // GenericOpcodes.td:364 |
| 79 | G_AND = 64, // GenericOpcodes.td:372 |
| 80 | G_OR = 65, // GenericOpcodes.td:380 |
| 81 | G_XOR = 66, // GenericOpcodes.td:388 |
| 82 | G_ABDS = 67, // GenericOpcodes.td:417 |
| 83 | G_ABDU = 68, // GenericOpcodes.td:425 |
| 84 | G_UAVGFLOOR = 69, // GenericOpcodes.td:433 |
| 85 | G_UAVGCEIL = 70, // GenericOpcodes.td:440 |
| 86 | G_SAVGFLOOR = 71, // GenericOpcodes.td:447 |
| 87 | G_SAVGCEIL = 72, // GenericOpcodes.td:454 |
| 88 | G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110 |
| 89 | G_PHI = 74, // GenericOpcodes.td:116 |
| 90 | G_FRAME_INDEX = 75, // GenericOpcodes.td:122 |
| 91 | G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128 |
| 92 | G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134 |
| 93 | G_CONSTANT_POOL = 78, // GenericOpcodes.td:140 |
| 94 | G_EXTRACT = 79, // GenericOpcodes.td:1472 |
| 95 | G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484 |
| 96 | G_INSERT = 81, // GenericOpcodes.td:1492 |
| 97 | G_MERGE_VALUES = 82, // GenericOpcodes.td:1502 |
| 98 | G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521 |
| 99 | G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530 |
| 100 | G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537 |
| 101 | G_PTRTOINT = 86, // GenericOpcodes.td:152 |
| 102 | G_INTTOPTR = 87, // GenericOpcodes.td:146 |
| 103 | G_BITCAST = 88, // GenericOpcodes.td:158 |
| 104 | G_FREEZE = 89, // GenericOpcodes.td:277 |
| 105 | G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879 |
| 106 | G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263 |
| 107 | G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269 |
| 108 | G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275 |
| 109 | G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281 |
| 110 | G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287 |
| 111 | G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293 |
| 112 | G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299 |
| 113 | G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305 |
| 114 | G_LOAD = 99, // GenericOpcodes.td:1332 |
| 115 | G_SEXTLOAD = 100, // GenericOpcodes.td:1340 |
| 116 | G_ZEXTLOAD = 101, // GenericOpcodes.td:1348 |
| 117 | G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358 |
| 118 | G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366 |
| 119 | G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374 |
| 120 | G_STORE = 105, // GenericOpcodes.td:1382 |
| 121 | G_INDEXED_STORE = 106, // GenericOpcodes.td:1390 |
| 122 | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400 |
| 123 | G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410 |
| 124 | G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428 |
| 125 | G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429 |
| 126 | G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430 |
| 127 | G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431 |
| 128 | G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432 |
| 129 | G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433 |
| 130 | G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434 |
| 131 | G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435 |
| 132 | G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436 |
| 133 | G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437 |
| 134 | G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438 |
| 135 | G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439 |
| 136 | G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440 |
| 137 | G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441 |
| 138 | G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442 |
| 139 | G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443 |
| 140 | G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444 |
| 141 | G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445 |
| 142 | G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446 |
| 143 | G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447 |
| 144 | G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448 |
| 145 | G_FENCE = 130, // GenericOpcodes.td:1450 |
| 146 | G_PREFETCH = 131, // GenericOpcodes.td:1457 |
| 147 | G_BRCOND = 132, // GenericOpcodes.td:1592 |
| 148 | G_BRINDIRECT = 133, // GenericOpcodes.td:1601 |
| 149 | G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624 |
| 150 | G_INTRINSIC = 135, // GenericOpcodes.td:1544 |
| 151 | G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551 |
| 152 | G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560 |
| 153 | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568 |
| 154 | G_ANYEXT = 139, // GenericOpcodes.td:44 |
| 155 | G_TRUNC = 140, // GenericOpcodes.td:83 |
| 156 | G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90 |
| 157 | G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97 |
| 158 | G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104 |
| 159 | G_CONSTANT = 144, // GenericOpcodes.td:165 |
| 160 | G_FCONSTANT = 145, // GenericOpcodes.td:172 |
| 161 | G_VASTART = 146, // GenericOpcodes.td:178 |
| 162 | G_VAARG = 147, // GenericOpcodes.td:185 |
| 163 | G_SEXT = 148, // GenericOpcodes.td:52 |
| 164 | G_SEXT_INREG = 149, // GenericOpcodes.td:66 |
| 165 | G_ZEXT = 150, // GenericOpcodes.td:74 |
| 166 | G_SHL = 151, // GenericOpcodes.td:396 |
| 167 | G_LSHR = 152, // GenericOpcodes.td:403 |
| 168 | G_ASHR = 153, // GenericOpcodes.td:410 |
| 169 | G_FSHL = 154, // GenericOpcodes.td:462 |
| 170 | G_FSHR = 155, // GenericOpcodes.td:470 |
| 171 | G_ROTR = 156, // GenericOpcodes.td:477 |
| 172 | G_ROTL = 157, // GenericOpcodes.td:484 |
| 173 | G_ICMP = 158, // GenericOpcodes.td:491 |
| 174 | G_FCMP = 159, // GenericOpcodes.td:498 |
| 175 | G_SCMP = 160, // GenericOpcodes.td:505 |
| 176 | G_UCMP = 161, // GenericOpcodes.td:512 |
| 177 | G_SELECT = 162, // GenericOpcodes.td:519 |
| 178 | G_UADDO = 163, // GenericOpcodes.td:584 |
| 179 | G_UADDE = 164, // GenericOpcodes.td:592 |
| 180 | G_USUBO = 165, // GenericOpcodes.td:614 |
| 181 | G_USUBE = 166, // GenericOpcodes.td:620 |
| 182 | G_SADDO = 167, // GenericOpcodes.td:599 |
| 183 | G_SADDE = 168, // GenericOpcodes.td:607 |
| 184 | G_SSUBO = 169, // GenericOpcodes.td:627 |
| 185 | G_SSUBE = 170, // GenericOpcodes.td:634 |
| 186 | G_UMULO = 171, // GenericOpcodes.td:641 |
| 187 | G_SMULO = 172, // GenericOpcodes.td:649 |
| 188 | G_UMULH = 173, // GenericOpcodes.td:658 |
| 189 | G_SMULH = 174, // GenericOpcodes.td:667 |
| 190 | G_UADDSAT = 175, // GenericOpcodes.td:679 |
| 191 | G_SADDSAT = 176, // GenericOpcodes.td:687 |
| 192 | G_USUBSAT = 177, // GenericOpcodes.td:695 |
| 193 | G_SSUBSAT = 178, // GenericOpcodes.td:703 |
| 194 | G_USHLSAT = 179, // GenericOpcodes.td:711 |
| 195 | G_SSHLSAT = 180, // GenericOpcodes.td:719 |
| 196 | G_SMULFIX = 181, // GenericOpcodes.td:731 |
| 197 | G_UMULFIX = 182, // GenericOpcodes.td:738 |
| 198 | G_SMULFIXSAT = 183, // GenericOpcodes.td:748 |
| 199 | G_UMULFIXSAT = 184, // GenericOpcodes.td:755 |
| 200 | G_SDIVFIX = 185, // GenericOpcodes.td:766 |
| 201 | G_UDIVFIX = 186, // GenericOpcodes.td:773 |
| 202 | G_SDIVFIXSAT = 187, // GenericOpcodes.td:783 |
| 203 | G_UDIVFIXSAT = 188, // GenericOpcodes.td:790 |
| 204 | G_FADD = 189, // GenericOpcodes.td:963 |
| 205 | G_FSUB = 190, // GenericOpcodes.td:971 |
| 206 | G_FMUL = 191, // GenericOpcodes.td:979 |
| 207 | G_FMA = 192, // GenericOpcodes.td:988 |
| 208 | G_FMAD = 193, // GenericOpcodes.td:997 |
| 209 | G_FDIV = 194, // GenericOpcodes.td:1005 |
| 210 | G_FREM = 195, // GenericOpcodes.td:1012 |
| 211 | G_FMODF = 196, // GenericOpcodes.td:1019 |
| 212 | G_FPOW = 197, // GenericOpcodes.td:1026 |
| 213 | G_FPOWI = 198, // GenericOpcodes.td:1033 |
| 214 | G_FEXP = 199, // GenericOpcodes.td:1040 |
| 215 | G_FEXP2 = 200, // GenericOpcodes.td:1047 |
| 216 | G_FEXP10 = 201, // GenericOpcodes.td:1054 |
| 217 | G_FLOG = 202, // GenericOpcodes.td:1061 |
| 218 | G_FLOG2 = 203, // GenericOpcodes.td:1068 |
| 219 | G_FLOG10 = 204, // GenericOpcodes.td:1075 |
| 220 | G_FLDEXP = 205, // GenericOpcodes.td:1082 |
| 221 | G_FFREXP = 206, // GenericOpcodes.td:1089 |
| 222 | G_FNEG = 207, // GenericOpcodes.td:801 |
| 223 | G_FPEXT = 208, // GenericOpcodes.td:807 |
| 224 | G_FPTRUNC = 209, // GenericOpcodes.td:813 |
| 225 | G_FPTOSI = 210, // GenericOpcodes.td:819 |
| 226 | G_FPTOUI = 211, // GenericOpcodes.td:825 |
| 227 | G_SITOFP = 212, // GenericOpcodes.td:831 |
| 228 | G_UITOFP = 213, // GenericOpcodes.td:837 |
| 229 | G_FPTOSI_SAT = 214, // GenericOpcodes.td:843 |
| 230 | G_FPTOUI_SAT = 215, // GenericOpcodes.td:849 |
| 231 | G_FABS = 216, // GenericOpcodes.td:855 |
| 232 | G_FCOPYSIGN = 217, // GenericOpcodes.td:861 |
| 233 | G_IS_FPCLASS = 218, // GenericOpcodes.td:874 |
| 234 | G_FCANONICALIZE = 219, // GenericOpcodes.td:867 |
| 235 | G_FMINNUM = 220, // GenericOpcodes.td:887 |
| 236 | G_FMAXNUM = 221, // GenericOpcodes.td:894 |
| 237 | G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912 |
| 238 | G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919 |
| 239 | G_FMINIMUM = 224, // GenericOpcodes.td:929 |
| 240 | G_FMAXIMUM = 225, // GenericOpcodes.td:936 |
| 241 | G_FMINIMUMNUM = 226, // GenericOpcodes.td:944 |
| 242 | G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951 |
| 243 | G_GET_FPENV = 228, // GenericOpcodes.td:1219 |
| 244 | G_SET_FPENV = 229, // GenericOpcodes.td:1226 |
| 245 | G_RESET_FPENV = 230, // GenericOpcodes.td:1233 |
| 246 | G_GET_FPMODE = 231, // GenericOpcodes.td:1240 |
| 247 | G_SET_FPMODE = 232, // GenericOpcodes.td:1247 |
| 248 | G_RESET_FPMODE = 233, // GenericOpcodes.td:1254 |
| 249 | G_GET_ROUNDING = 234, // GenericOpcodes.td:1311 |
| 250 | G_SET_ROUNDING = 235, // GenericOpcodes.td:1317 |
| 251 | G_PTR_ADD = 236, // GenericOpcodes.td:526 |
| 252 | G_PTRMASK = 237, // GenericOpcodes.td:534 |
| 253 | G_SMIN = 238, // GenericOpcodes.td:541 |
| 254 | G_SMAX = 239, // GenericOpcodes.td:549 |
| 255 | G_UMIN = 240, // GenericOpcodes.td:557 |
| 256 | G_UMAX = 241, // GenericOpcodes.td:565 |
| 257 | G_ABS = 242, // GenericOpcodes.td:573 |
| 258 | G_LROUND = 243, // GenericOpcodes.td:283 |
| 259 | G_LLROUND = 244, // GenericOpcodes.td:289 |
| 260 | G_BR = 245, // GenericOpcodes.td:1582 |
| 261 | G_BRJT = 246, // GenericOpcodes.td:1612 |
| 262 | G_VSCALE = 247, // GenericOpcodes.td:1512 |
| 263 | G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656 |
| 264 | G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663 |
| 265 | G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670 |
| 266 | G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677 |
| 267 | G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687 |
| 268 | G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694 |
| 269 | G_STEP_VECTOR = 254, // GenericOpcodes.td:1701 |
| 270 | G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708 |
| 271 | G_CTTZ = 256, // GenericOpcodes.td:205 |
| 272 | G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211 |
| 273 | G_CTLZ = 258, // GenericOpcodes.td:193 |
| 274 | G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199 |
| 275 | G_CTLS = 260, // GenericOpcodes.td:217 |
| 276 | G_CTPOP = 261, // GenericOpcodes.td:223 |
| 277 | G_BSWAP = 262, // GenericOpcodes.td:229 |
| 278 | G_BITREVERSE = 263, // GenericOpcodes.td:235 |
| 279 | G_FCEIL = 264, // GenericOpcodes.td:1096 |
| 280 | G_FCOS = 265, // GenericOpcodes.td:1103 |
| 281 | G_FSIN = 266, // GenericOpcodes.td:1110 |
| 282 | G_FSINCOS = 267, // GenericOpcodes.td:1117 |
| 283 | G_FTAN = 268, // GenericOpcodes.td:1124 |
| 284 | G_FACOS = 269, // GenericOpcodes.td:1131 |
| 285 | G_FASIN = 270, // GenericOpcodes.td:1138 |
| 286 | G_FATAN = 271, // GenericOpcodes.td:1145 |
| 287 | G_FATAN2 = 272, // GenericOpcodes.td:1152 |
| 288 | G_FCOSH = 273, // GenericOpcodes.td:1159 |
| 289 | G_FSINH = 274, // GenericOpcodes.td:1166 |
| 290 | G_FTANH = 275, // GenericOpcodes.td:1173 |
| 291 | G_FSQRT = 276, // GenericOpcodes.td:1183 |
| 292 | G_FFLOOR = 277, // GenericOpcodes.td:1190 |
| 293 | G_FRINT = 278, // GenericOpcodes.td:1197 |
| 294 | G_FNEARBYINT = 279, // GenericOpcodes.td:1204 |
| 295 | G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241 |
| 296 | G_BLOCK_ADDR = 281, // GenericOpcodes.td:247 |
| 297 | G_JUMP_TABLE = 282, // GenericOpcodes.td:253 |
| 298 | G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259 |
| 299 | G_STACKSAVE = 284, // GenericOpcodes.td:265 |
| 300 | G_STACKRESTORE = 285, // GenericOpcodes.td:271 |
| 301 | G_STRICT_FADD = 286, // GenericOpcodes.td:1758 |
| 302 | G_STRICT_FSUB = 287, // GenericOpcodes.td:1759 |
| 303 | G_STRICT_FMUL = 288, // GenericOpcodes.td:1760 |
| 304 | G_STRICT_FDIV = 289, // GenericOpcodes.td:1761 |
| 305 | G_STRICT_FREM = 290, // GenericOpcodes.td:1762 |
| 306 | G_STRICT_FMA = 291, // GenericOpcodes.td:1763 |
| 307 | G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764 |
| 308 | G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765 |
| 309 | G_READ_REGISTER = 294, // GenericOpcodes.td:1631 |
| 310 | G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641 |
| 311 | G_MEMCPY = 296, // GenericOpcodes.td:1771 |
| 312 | G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779 |
| 313 | G_MEMMOVE = 298, // GenericOpcodes.td:1787 |
| 314 | G_MEMSET = 299, // GenericOpcodes.td:1795 |
| 315 | G_BZERO = 300, // GenericOpcodes.td:1802 |
| 316 | G_TRAP = 301, // GenericOpcodes.td:1812 |
| 317 | G_DEBUGTRAP = 302, // GenericOpcodes.td:1819 |
| 318 | G_UBSANTRAP = 303, // GenericOpcodes.td:1825 |
| 319 | G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724 |
| 320 | G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730 |
| 321 | G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736 |
| 322 | G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737 |
| 323 | G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739 |
| 324 | G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740 |
| 325 | G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741 |
| 326 | G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742 |
| 327 | G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744 |
| 328 | G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745 |
| 329 | G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746 |
| 330 | G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747 |
| 331 | G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748 |
| 332 | G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749 |
| 333 | G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750 |
| 334 | G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751 |
| 335 | G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752 |
| 336 | G_SBFX = 321, // GenericOpcodes.td:1837 |
| 337 | G_UBFX = 322, // GenericOpcodes.td:1845 |
| 338 | ABSMacro = 323, // MipsInstrInfo.td:2642 |
| 339 | ADJCALLSTACKDOWN = 324, // MipsInstrInfo.td:1949 |
| 340 | ADJCALLSTACKUP = 325, // MipsInstrInfo.td:1951 |
| 341 | AND_V_D_PSEUDO = 326, // MipsMSAInstrInfo.td:2733 |
| 342 | AND_V_H_PSEUDO = 327, // MipsMSAInstrInfo.td:2725 |
| 343 | AND_V_W_PSEUDO = 328, // MipsMSAInstrInfo.td:2729 |
| 344 | ATOMIC_CMP_SWAP_I16 = 329, // MipsInstrInfo.td:1980 |
| 345 | ATOMIC_CMP_SWAP_I16_POSTRA = 330, // MipsInstrInfo.td:2021 |
| 346 | ATOMIC_CMP_SWAP_I32 = 331, // MipsInstrInfo.td:1981 |
| 347 | ATOMIC_CMP_SWAP_I32_POSTRA = 332, // MipsInstrInfo.td:2022 |
| 348 | ATOMIC_CMP_SWAP_I64 = 333, // Mips64InstrInfo.td:85 |
| 349 | ATOMIC_CMP_SWAP_I64_POSTRA = 334, // Mips64InstrInfo.td:101 |
| 350 | ATOMIC_CMP_SWAP_I8 = 335, // MipsInstrInfo.td:1979 |
| 351 | ATOMIC_CMP_SWAP_I8_POSTRA = 336, // MipsInstrInfo.td:2020 |
| 352 | ATOMIC_LOAD_ADD_I16 = 337, // MipsInstrInfo.td:1957 |
| 353 | ATOMIC_LOAD_ADD_I16_POSTRA = 338, // MipsInstrInfo.td:1998 |
| 354 | ATOMIC_LOAD_ADD_I32 = 339, // MipsInstrInfo.td:1958 |
| 355 | ATOMIC_LOAD_ADD_I32_POSTRA = 340, // MipsInstrInfo.td:1999 |
| 356 | ATOMIC_LOAD_ADD_I64 = 341, // Mips64InstrInfo.td:78 |
| 357 | ATOMIC_LOAD_ADD_I64_POSTRA = 342, // Mips64InstrInfo.td:92 |
| 358 | ATOMIC_LOAD_ADD_I8 = 343, // MipsInstrInfo.td:1956 |
| 359 | ATOMIC_LOAD_ADD_I8_POSTRA = 344, // MipsInstrInfo.td:1997 |
| 360 | ATOMIC_LOAD_AND_I16 = 345, // MipsInstrInfo.td:1963 |
| 361 | ATOMIC_LOAD_AND_I16_POSTRA = 346, // MipsInstrInfo.td:2004 |
| 362 | ATOMIC_LOAD_AND_I32 = 347, // MipsInstrInfo.td:1964 |
| 363 | ATOMIC_LOAD_AND_I32_POSTRA = 348, // MipsInstrInfo.td:2005 |
| 364 | ATOMIC_LOAD_AND_I64 = 349, // Mips64InstrInfo.td:80 |
| 365 | ATOMIC_LOAD_AND_I64_POSTRA = 350, // Mips64InstrInfo.td:94 |
| 366 | ATOMIC_LOAD_AND_I8 = 351, // MipsInstrInfo.td:1962 |
| 367 | ATOMIC_LOAD_AND_I8_POSTRA = 352, // MipsInstrInfo.td:2003 |
| 368 | ATOMIC_LOAD_MAX_I16 = 353, // MipsInstrInfo.td:1987 |
| 369 | ATOMIC_LOAD_MAX_I16_POSTRA = 354, // MipsInstrInfo.td:2028 |
| 370 | ATOMIC_LOAD_MAX_I32 = 355, // MipsInstrInfo.td:1988 |
| 371 | ATOMIC_LOAD_MAX_I32_POSTRA = 356, // MipsInstrInfo.td:2029 |
| 372 | ATOMIC_LOAD_MAX_I64 = 357, // Mips64InstrInfo.td:87 |
| 373 | ATOMIC_LOAD_MAX_I64_POSTRA = 358, // Mips64InstrInfo.td:104 |
| 374 | ATOMIC_LOAD_MAX_I8 = 359, // MipsInstrInfo.td:1986 |
| 375 | ATOMIC_LOAD_MAX_I8_POSTRA = 360, // MipsInstrInfo.td:2027 |
| 376 | ATOMIC_LOAD_MIN_I16 = 361, // MipsInstrInfo.td:1984 |
| 377 | ATOMIC_LOAD_MIN_I16_POSTRA = 362, // MipsInstrInfo.td:2025 |
| 378 | ATOMIC_LOAD_MIN_I32 = 363, // MipsInstrInfo.td:1985 |
| 379 | ATOMIC_LOAD_MIN_I32_POSTRA = 364, // MipsInstrInfo.td:2026 |
| 380 | ATOMIC_LOAD_MIN_I64 = 365, // Mips64InstrInfo.td:86 |
| 381 | ATOMIC_LOAD_MIN_I64_POSTRA = 366, // Mips64InstrInfo.td:103 |
| 382 | ATOMIC_LOAD_MIN_I8 = 367, // MipsInstrInfo.td:1983 |
| 383 | ATOMIC_LOAD_MIN_I8_POSTRA = 368, // MipsInstrInfo.td:2024 |
| 384 | ATOMIC_LOAD_NAND_I16 = 369, // MipsInstrInfo.td:1972 |
| 385 | ATOMIC_LOAD_NAND_I16_POSTRA = 370, // MipsInstrInfo.td:2013 |
| 386 | ATOMIC_LOAD_NAND_I32 = 371, // MipsInstrInfo.td:1973 |
| 387 | ATOMIC_LOAD_NAND_I32_POSTRA = 372, // MipsInstrInfo.td:2014 |
| 388 | ATOMIC_LOAD_NAND_I64 = 373, // Mips64InstrInfo.td:83 |
| 389 | ATOMIC_LOAD_NAND_I64_POSTRA = 374, // Mips64InstrInfo.td:97 |
| 390 | ATOMIC_LOAD_NAND_I8 = 375, // MipsInstrInfo.td:1971 |
| 391 | ATOMIC_LOAD_NAND_I8_POSTRA = 376, // MipsInstrInfo.td:2012 |
| 392 | ATOMIC_LOAD_OR_I16 = 377, // MipsInstrInfo.td:1966 |
| 393 | ATOMIC_LOAD_OR_I16_POSTRA = 378, // MipsInstrInfo.td:2007 |
| 394 | ATOMIC_LOAD_OR_I32 = 379, // MipsInstrInfo.td:1967 |
| 395 | ATOMIC_LOAD_OR_I32_POSTRA = 380, // MipsInstrInfo.td:2008 |
| 396 | ATOMIC_LOAD_OR_I64 = 381, // Mips64InstrInfo.td:81 |
| 397 | ATOMIC_LOAD_OR_I64_POSTRA = 382, // Mips64InstrInfo.td:95 |
| 398 | ATOMIC_LOAD_OR_I8 = 383, // MipsInstrInfo.td:1965 |
| 399 | ATOMIC_LOAD_OR_I8_POSTRA = 384, // MipsInstrInfo.td:2006 |
| 400 | ATOMIC_LOAD_SUB_I16 = 385, // MipsInstrInfo.td:1960 |
| 401 | ATOMIC_LOAD_SUB_I16_POSTRA = 386, // MipsInstrInfo.td:2001 |
| 402 | ATOMIC_LOAD_SUB_I32 = 387, // MipsInstrInfo.td:1961 |
| 403 | ATOMIC_LOAD_SUB_I32_POSTRA = 388, // MipsInstrInfo.td:2002 |
| 404 | ATOMIC_LOAD_SUB_I64 = 389, // Mips64InstrInfo.td:79 |
| 405 | ATOMIC_LOAD_SUB_I64_POSTRA = 390, // Mips64InstrInfo.td:93 |
| 406 | ATOMIC_LOAD_SUB_I8 = 391, // MipsInstrInfo.td:1959 |
| 407 | ATOMIC_LOAD_SUB_I8_POSTRA = 392, // MipsInstrInfo.td:2000 |
| 408 | ATOMIC_LOAD_UMAX_I16 = 393, // MipsInstrInfo.td:1993 |
| 409 | ATOMIC_LOAD_UMAX_I16_POSTRA = 394, // MipsInstrInfo.td:2034 |
| 410 | ATOMIC_LOAD_UMAX_I32 = 395, // MipsInstrInfo.td:1994 |
| 411 | ATOMIC_LOAD_UMAX_I32_POSTRA = 396, // MipsInstrInfo.td:2035 |
| 412 | ATOMIC_LOAD_UMAX_I64 = 397, // Mips64InstrInfo.td:89 |
| 413 | ATOMIC_LOAD_UMAX_I64_POSTRA = 398, // Mips64InstrInfo.td:106 |
| 414 | ATOMIC_LOAD_UMAX_I8 = 399, // MipsInstrInfo.td:1992 |
| 415 | ATOMIC_LOAD_UMAX_I8_POSTRA = 400, // MipsInstrInfo.td:2033 |
| 416 | ATOMIC_LOAD_UMIN_I16 = 401, // MipsInstrInfo.td:1990 |
| 417 | ATOMIC_LOAD_UMIN_I16_POSTRA = 402, // MipsInstrInfo.td:2031 |
| 418 | ATOMIC_LOAD_UMIN_I32 = 403, // MipsInstrInfo.td:1991 |
| 419 | ATOMIC_LOAD_UMIN_I32_POSTRA = 404, // MipsInstrInfo.td:2032 |
| 420 | ATOMIC_LOAD_UMIN_I64 = 405, // Mips64InstrInfo.td:88 |
| 421 | ATOMIC_LOAD_UMIN_I64_POSTRA = 406, // Mips64InstrInfo.td:105 |
| 422 | ATOMIC_LOAD_UMIN_I8 = 407, // MipsInstrInfo.td:1989 |
| 423 | ATOMIC_LOAD_UMIN_I8_POSTRA = 408, // MipsInstrInfo.td:2030 |
| 424 | ATOMIC_LOAD_XOR_I16 = 409, // MipsInstrInfo.td:1969 |
| 425 | ATOMIC_LOAD_XOR_I16_POSTRA = 410, // MipsInstrInfo.td:2010 |
| 426 | ATOMIC_LOAD_XOR_I32 = 411, // MipsInstrInfo.td:1970 |
| 427 | ATOMIC_LOAD_XOR_I32_POSTRA = 412, // MipsInstrInfo.td:2011 |
| 428 | ATOMIC_LOAD_XOR_I64 = 413, // Mips64InstrInfo.td:82 |
| 429 | ATOMIC_LOAD_XOR_I64_POSTRA = 414, // Mips64InstrInfo.td:96 |
| 430 | ATOMIC_LOAD_XOR_I8 = 415, // MipsInstrInfo.td:1968 |
| 431 | ATOMIC_LOAD_XOR_I8_POSTRA = 416, // MipsInstrInfo.td:2009 |
| 432 | ATOMIC_SWAP_I16 = 417, // MipsInstrInfo.td:1976 |
| 433 | ATOMIC_SWAP_I16_POSTRA = 418, // MipsInstrInfo.td:2017 |
| 434 | ATOMIC_SWAP_I32 = 419, // MipsInstrInfo.td:1977 |
| 435 | ATOMIC_SWAP_I32_POSTRA = 420, // MipsInstrInfo.td:2018 |
| 436 | ATOMIC_SWAP_I64 = 421, // Mips64InstrInfo.td:84 |
| 437 | ATOMIC_SWAP_I64_POSTRA = 422, // Mips64InstrInfo.td:99 |
| 438 | ATOMIC_SWAP_I8 = 423, // MipsInstrInfo.td:1975 |
| 439 | ATOMIC_SWAP_I8_POSTRA = 424, // MipsInstrInfo.td:2016 |
| 440 | B = 425, // MipsInstrInfo.td:2312 |
| 441 | BAL_BR = 426, // MipsInstrInfo.td:2334 |
| 442 | BAL_BR_MM = 427, // MicroMipsInstrInfo.td:989 |
| 443 | BEQLImmMacro = 428, // MipsInstrInfo.td:3049 |
| 444 | BGE = 429, // MipsInstrInfo.td:3029 |
| 445 | BGEImmMacro = 430, // MipsInstrInfo.td:3054 |
| 446 | BGEL = 431, // MipsInstrInfo.td:3037 |
| 447 | BGELImmMacro = 432, // MipsInstrInfo.td:3062 |
| 448 | BGEU = 433, // MipsInstrInfo.td:3033 |
| 449 | BGEUImmMacro = 434, // MipsInstrInfo.td:3058 |
| 450 | BGEUL = 435, // MipsInstrInfo.td:3041 |
| 451 | BGEULImmMacro = 436, // MipsInstrInfo.td:3066 |
| 452 | BGT = 437, // MipsInstrInfo.td:3030 |
| 453 | BGTImmMacro = 438, // MipsInstrInfo.td:3055 |
| 454 | BGTL = 439, // MipsInstrInfo.td:3038 |
| 455 | BGTLImmMacro = 440, // MipsInstrInfo.td:3063 |
| 456 | BGTU = 441, // MipsInstrInfo.td:3034 |
| 457 | BGTUImmMacro = 442, // MipsInstrInfo.td:3059 |
| 458 | BGTUL = 443, // MipsInstrInfo.td:3042 |
| 459 | BGTULImmMacro = 444, // MipsInstrInfo.td:3067 |
| 460 | BLE = 445, // MipsInstrInfo.td:3028 |
| 461 | BLEImmMacro = 446, // MipsInstrInfo.td:3053 |
| 462 | BLEL = 447, // MipsInstrInfo.td:3036 |
| 463 | BLELImmMacro = 448, // MipsInstrInfo.td:3061 |
| 464 | BLEU = 449, // MipsInstrInfo.td:3032 |
| 465 | BLEUImmMacro = 450, // MipsInstrInfo.td:3057 |
| 466 | BLEUL = 451, // MipsInstrInfo.td:3040 |
| 467 | BLEULImmMacro = 452, // MipsInstrInfo.td:3065 |
| 468 | BLT = 453, // MipsInstrInfo.td:3027 |
| 469 | BLTImmMacro = 454, // MipsInstrInfo.td:3052 |
| 470 | BLTL = 455, // MipsInstrInfo.td:3035 |
| 471 | BLTLImmMacro = 456, // MipsInstrInfo.td:3060 |
| 472 | BLTU = 457, // MipsInstrInfo.td:3031 |
| 473 | BLTUImmMacro = 458, // MipsInstrInfo.td:3056 |
| 474 | BLTUL = 459, // MipsInstrInfo.td:3039 |
| 475 | BLTULImmMacro = 460, // MipsInstrInfo.td:3064 |
| 476 | BNELImmMacro = 461, // MipsInstrInfo.td:3050 |
| 477 | BPOSGE32_PSEUDO = 462, // MipsDSPInstrInfo.td:1117 |
| 478 | BSEL_D_PSEUDO = 463, // MipsMSAInstrInfo.td:2841 |
| 479 | BSEL_FD_PSEUDO = 464, // MipsMSAInstrInfo.td:2843 |
| 480 | BSEL_FW_PSEUDO = 465, // MipsMSAInstrInfo.td:2842 |
| 481 | BSEL_H_PSEUDO = 466, // MipsMSAInstrInfo.td:2839 |
| 482 | BSEL_W_PSEUDO = 467, // MipsMSAInstrInfo.td:2840 |
| 483 | B_MM = 468, // MicroMipsInstrInfo.td:999 |
| 484 | B_MMR6_Pseudo = 469, // MicroMips32r6InstrInfo.td:1678 |
| 485 | B_MM_Pseudo = 470, // MicroMipsInstrInfo.td:1313 |
| 486 | BeqImm = 471, // MipsInstrInfo.td:3017 |
| 487 | BneImm = 472, // MipsInstrInfo.td:3014 |
| 488 | BteqzT8CmpX16 = 473, // Mips16InstrInfo.td:649 |
| 489 | BteqzT8CmpiX16 = 474, // Mips16InstrInfo.td:651 |
| 490 | BteqzT8SltX16 = 475, // Mips16InstrInfo.td:654 |
| 491 | BteqzT8SltiX16 = 476, // Mips16InstrInfo.td:658 |
| 492 | BteqzT8SltiuX16 = 477, // Mips16InstrInfo.td:660 |
| 493 | BteqzT8SltuX16 = 478, // Mips16InstrInfo.td:656 |
| 494 | BtnezT8CmpX16 = 479, // Mips16InstrInfo.td:677 |
| 495 | BtnezT8CmpiX16 = 480, // Mips16InstrInfo.td:679 |
| 496 | BtnezT8SltX16 = 481, // Mips16InstrInfo.td:681 |
| 497 | BtnezT8SltiX16 = 482, // Mips16InstrInfo.td:685 |
| 498 | BtnezT8SltiuX16 = 483, // Mips16InstrInfo.td:687 |
| 499 | BtnezT8SltuX16 = 484, // Mips16InstrInfo.td:683 |
| 500 | BuildPairF64 = 485, // MipsInstrFPU.td:796 |
| 501 | BuildPairF64_64 = 486, // MipsInstrFPU.td:797 |
| 502 | CFTC1 = 487, // MipsMTInstrInfo.td:143 |
| 503 | CONSTPOOL_ENTRY = 488, // Mips16InstrInfo.td:1912 |
| 504 | COPY_FD_PSEUDO = 489, // MipsMSAInstrInfo.td:2926 |
| 505 | COPY_FW_PSEUDO = 490, // MipsMSAInstrInfo.td:2925 |
| 506 | CTTC1 = 491, // MipsMTInstrInfo.td:172 |
| 507 | Constant32 = 492, // Mips16InstrInfo.td:486 |
| 508 | DMULImmMacro = 493, // Mips64InstrInfo.td:1134 |
| 509 | DMULMacro = 494, // Mips64InstrInfo.td:1150 |
| 510 | DMULOMacro = 495, // Mips64InstrInfo.td:1139 |
| 511 | DMULOUMacro = 496, // Mips64InstrInfo.td:1144 |
| 512 | DROL = 497, // MipsInstrInfo.td:2616 |
| 513 | DROLImm = 498, // MipsInstrInfo.td:2619 |
| 514 | DROR = 499, // MipsInstrInfo.td:2629 |
| 515 | DRORImm = 500, // MipsInstrInfo.td:2632 |
| 516 | DSDivIMacro = 501, // Mips64InstrInfo.td:1161 |
| 517 | DSDivMacro = 502, // Mips64InstrInfo.td:1157 |
| 518 | DSRemIMacro = 503, // Mips64InstrInfo.td:1203 |
| 519 | DSRemMacro = 504, // Mips64InstrInfo.td:1199 |
| 520 | DUDivIMacro = 505, // Mips64InstrInfo.td:1169 |
| 521 | DUDivMacro = 506, // Mips64InstrInfo.td:1165 |
| 522 | DURemIMacro = 507, // Mips64InstrInfo.td:1211 |
| 523 | DURemMacro = 508, // Mips64InstrInfo.td:1207 |
| 524 | ERet = 509, // MipsInstrInfo.td:1945 |
| 525 | ExtractElementF64 = 510, // MipsInstrFPU.td:810 |
| 526 | ExtractElementF64_64 = 511, // MipsInstrFPU.td:811 |
| 527 | FABS_D = 512, // MipsMSAInstrInfo.td:3544 |
| 528 | FABS_W = 513, // MipsMSAInstrInfo.td:3541 |
| 529 | FEXP2_D_1_PSEUDO = 514, // MipsMSAInstrInfo.td:3012 |
| 530 | FEXP2_W_1_PSEUDO = 515, // MipsMSAInstrInfo.td:3011 |
| 531 | FILL_FD_PSEUDO = 516, // MipsMSAInstrInfo.td:3037 |
| 532 | FILL_FW_PSEUDO = 517, // MipsMSAInstrInfo.td:3036 |
| 533 | GotPrologue16 = 518, // Mips16InstrInfo.td:1895 |
| 534 | INSERT_B_VIDX64_PSEUDO = 519, // MipsMSAInstrInfo.td:3203 |
| 535 | INSERT_B_VIDX_PSEUDO = 520, // MipsMSAInstrInfo.td:3196 |
| 536 | INSERT_D_VIDX64_PSEUDO = 521, // MipsMSAInstrInfo.td:3206 |
| 537 | INSERT_D_VIDX_PSEUDO = 522, // MipsMSAInstrInfo.td:3199 |
| 538 | INSERT_FD_PSEUDO = 523, // MipsMSAInstrInfo.td:3194 |
| 539 | INSERT_FD_VIDX64_PSEUDO = 524, // MipsMSAInstrInfo.td:3208 |
| 540 | INSERT_FD_VIDX_PSEUDO = 525, // MipsMSAInstrInfo.td:3201 |
| 541 | INSERT_FW_PSEUDO = 526, // MipsMSAInstrInfo.td:3193 |
| 542 | INSERT_FW_VIDX64_PSEUDO = 527, // MipsMSAInstrInfo.td:3207 |
| 543 | INSERT_FW_VIDX_PSEUDO = 528, // MipsMSAInstrInfo.td:3200 |
| 544 | INSERT_H_VIDX64_PSEUDO = 529, // MipsMSAInstrInfo.td:3204 |
| 545 | INSERT_H_VIDX_PSEUDO = 530, // MipsMSAInstrInfo.td:3197 |
| 546 | INSERT_W_VIDX64_PSEUDO = 531, // MipsMSAInstrInfo.td:3205 |
| 547 | INSERT_W_VIDX_PSEUDO = 532, // MipsMSAInstrInfo.td:3198 |
| 548 | JALR64Pseudo = 533, // Mips64InstrInfo.td:284 |
| 549 | JALRHB64Pseudo = 534, // Mips64InstrInfo.td:651 |
| 550 | JALRHBPseudo = 535, // MipsInstrInfo.td:2561 |
| 551 | JALRPseudo = 536, // MipsInstrInfo.td:2320 |
| 552 | JAL_MMR6 = 537, // MicroMips32r6InstrInfo.td:1815 |
| 553 | JalOneReg = 538, // MipsInstrInfo.td:3003 |
| 554 | JalTwoReg = 539, // MipsInstrInfo.td:3001 |
| 555 | LDMacro = 540, // MipsInstrInfo.td:3164 |
| 556 | LDR_D = 541, // MipsMSAInstrInfo.td:2285 |
| 557 | LDR_W = 542, // MipsMSAInstrInfo.td:2286 |
| 558 | LD_F16 = 543, // MipsMSAInstrInfo.td:3730 |
| 559 | LOAD_ACC128 = 544, // Mips64InstrInfo.td:110 |
| 560 | LOAD_ACC64 = 545, // MipsInstrInfo.td:2039 |
| 561 | LOAD_ACC64DSP = 546, // MipsDSPInstrInfo.td:1291 |
| 562 | LOAD_CCOND_DSP = 547, // MipsDSPInstrInfo.td:1295 |
| 563 | LONG_BRANCH_ADDiu = 548, // MipsInstrInfo.td:2059 |
| 564 | LONG_BRANCH_ADDiu2Op = 549, // MipsInstrInfo.td:2064 |
| 565 | LONG_BRANCH_DADDiu = 550, // Mips64InstrInfo.td:455 |
| 566 | LONG_BRANCH_DADDiu2Op = 551, // Mips64InstrInfo.td:447 |
| 567 | LONG_BRANCH_LUi = 552, // MipsInstrInfo.td:2048 |
| 568 | LONG_BRANCH_LUi2Op = 553, // MipsInstrInfo.td:2053 |
| 569 | LONG_BRANCH_LUi2Op_64 = 554, // Mips64InstrInfo.td:442 |
| 570 | LWM_MM = 555, // MicroMipsInstrInfo.td:892 |
| 571 | LoadAddrImm32 = 556, // MipsInstrInfo.td:2999 |
| 572 | LoadAddrImm64 = 557, // Mips64InstrInfo.td:1131 |
| 573 | LoadAddrReg32 = 558, // MipsInstrInfo.td:2994 |
| 574 | LoadAddrReg64 = 559, // Mips64InstrInfo.td:1129 |
| 575 | LoadImm32 = 560, // MipsInstrInfo.td:2988 |
| 576 | LoadImm64 = 561, // Mips64InstrInfo.td:1127 |
| 577 | LoadImmDoubleFGR = 562, // MipsInstrFPU.td:845 |
| 578 | LoadImmDoubleFGR_32 = 563, // MipsInstrFPU.td:840 |
| 579 | LoadImmDoubleGPR = 564, // MipsInstrFPU.td:836 |
| 580 | LoadImmSingleFGR = 565, // MipsInstrFPU.td:831 |
| 581 | LoadImmSingleGPR = 566, // MipsInstrFPU.td:827 |
| 582 | LwConstant32 = 567, // Mips16InstrInfo.td:488 |
| 583 | MFTACX = 568, // MipsMTInstrInfo.td:131 |
| 584 | MFTC0 = 569, // MipsMTInstrInfo.td:117 |
| 585 | MFTC1 = 570, // MipsMTInstrInfo.td:137 |
| 586 | MFTDSP = 571, // MipsMTInstrInfo.td:134 |
| 587 | MFTGPR = 572, // MipsMTInstrInfo.td:121 |
| 588 | MFTHC1 = 573, // MipsMTInstrInfo.td:140 |
| 589 | MFTHI = 574, // MipsMTInstrInfo.td:128 |
| 590 | MFTLO = 575, // MipsMTInstrInfo.td:125 |
| 591 | MIPSeh_return32 = 576, // MipsInstrInfo.td:2396 |
| 592 | MIPSeh_return64 = 577, // MipsInstrInfo.td:2398 |
| 593 | MSA_FP_EXTEND_D_PSEUDO = 578, // MipsMSAInstrInfo.td:3742 |
| 594 | MSA_FP_EXTEND_W_PSEUDO = 579, // MipsMSAInstrInfo.td:3736 |
| 595 | MSA_FP_ROUND_D_PSEUDO = 580, // MipsMSAInstrInfo.td:3745 |
| 596 | MSA_FP_ROUND_W_PSEUDO = 581, // MipsMSAInstrInfo.td:3739 |
| 597 | MTTACX = 582, // MipsMTInstrInfo.td:160 |
| 598 | MTTC0 = 583, // MipsMTInstrInfo.td:147 |
| 599 | MTTC1 = 584, // MipsMTInstrInfo.td:166 |
| 600 | MTTDSP = 585, // MipsMTInstrInfo.td:163 |
| 601 | MTTGPR = 586, // MipsMTInstrInfo.td:151 |
| 602 | MTTHC1 = 587, // MipsMTInstrInfo.td:169 |
| 603 | MTTHI = 588, // MipsMTInstrInfo.td:157 |
| 604 | MTTLO = 589, // MipsMTInstrInfo.td:154 |
| 605 | MULImmMacro = 590, // MipsInstrInfo.td:2677 |
| 606 | MULOMacro = 591, // MipsInstrInfo.td:2681 |
| 607 | MULOUMacro = 592, // MipsInstrInfo.td:2685 |
| 608 | MultRxRy16 = 593, // Mips16InstrInfo.td:903 |
| 609 | MultRxRyRz16 = 594, // Mips16InstrInfo.td:920 |
| 610 | MultuRxRy16 = 595, // Mips16InstrInfo.td:909 |
| 611 | MultuRxRyRz16 = 596, // Mips16InstrInfo.td:931 |
| 612 | NOP = 597, // MipsInstrInfo.td:2438 |
| 613 | NORImm = 598, // MipsInstrInfo.td:3009 |
| 614 | NORImm64 = 599, // Mips64InstrInfo.td:1233 |
| 615 | NOR_V_D_PSEUDO = 600, // MipsMSAInstrInfo.td:3337 |
| 616 | NOR_V_H_PSEUDO = 601, // MipsMSAInstrInfo.td:3329 |
| 617 | NOR_V_W_PSEUDO = 602, // MipsMSAInstrInfo.td:3333 |
| 618 | OR_V_D_PSEUDO = 603, // MipsMSAInstrInfo.td:3353 |
| 619 | OR_V_H_PSEUDO = 604, // MipsMSAInstrInfo.td:3345 |
| 620 | OR_V_W_PSEUDO = 605, // MipsMSAInstrInfo.td:3349 |
| 621 | PseudoCMPU_EQ_QB = 606, // MipsDSPInstrInfo.td:1319 |
| 622 | PseudoCMPU_LE_QB = 607, // MipsDSPInstrInfo.td:1321 |
| 623 | PseudoCMPU_LT_QB = 608, // MipsDSPInstrInfo.td:1320 |
| 624 | PseudoCMP_EQ_PH = 609, // MipsDSPInstrInfo.td:1316 |
| 625 | PseudoCMP_LE_PH = 610, // MipsDSPInstrInfo.td:1318 |
| 626 | PseudoCMP_LT_PH = 611, // MipsDSPInstrInfo.td:1317 |
| 627 | PseudoCVT_D32_W = 612, // MipsInstrFPU.td:544 |
| 628 | PseudoCVT_D64_L = 613, // MipsInstrFPU.td:547 |
| 629 | PseudoCVT_D64_W = 614, // MipsInstrFPU.td:546 |
| 630 | PseudoCVT_S_L = 615, // MipsInstrFPU.td:545 |
| 631 | PseudoCVT_S_W = 616, // MipsInstrFPU.td:543 |
| 632 | PseudoDMULT = 617, // Mips64InstrInfo.td:320 |
| 633 | PseudoDMULTu = 618, // Mips64InstrInfo.td:322 |
| 634 | PseudoDSDIV = 619, // Mips64InstrInfo.td:333 |
| 635 | PseudoDUDIV = 620, // Mips64InstrInfo.td:336 |
| 636 | PseudoD_SELECT_I = 621, // MipsCondMov.td:308 |
| 637 | PseudoD_SELECT_I64 = 622, // MipsCondMov.td:309 |
| 638 | PseudoIndirectBranch = 623, // MipsInstrInfo.td:2359 |
| 639 | PseudoIndirectBranch64 = 624, // Mips64InstrInfo.td:298 |
| 640 | PseudoIndirectBranch64R6 = 625, // Mips64r6InstrInfo.td:328 |
| 641 | PseudoIndirectBranchR6 = 626, // Mips32r6InstrInfo.td:1210 |
| 642 | PseudoIndirectBranch_MM = 627, // MicroMipsInstrInfo.td:1122 |
| 643 | PseudoIndirectBranch_MMR6 = 628, // MicroMips32r6InstrInfo.td:1826 |
| 644 | PseudoIndirectHazardBranch = 629, // MipsInstrInfo.td:2567 |
| 645 | PseudoIndirectHazardBranch64 = 630, // Mips64InstrInfo.td:306 |
| 646 | PseudoIndrectHazardBranch64R6 = 631, // Mips64r6InstrInfo.td:337 |
| 647 | PseudoIndrectHazardBranchR6 = 632, // Mips32r6InstrInfo.td:1218 |
| 648 | PseudoMADD = 633, // MipsInstrInfo.td:2468 |
| 649 | PseudoMADDU = 634, // MipsInstrInfo.td:2470 |
| 650 | PseudoMADDU_MM = 635, // MicroMipsInstrInfo.td:1108 |
| 651 | PseudoMADD_MM = 636, // MicroMipsInstrInfo.td:1106 |
| 652 | PseudoMFHI = 637, // MipsInstrInfo.td:2465 |
| 653 | PseudoMFHI64 = 638, // Mips64InstrInfo.td:349 |
| 654 | PseudoMFHI_MM = 639, // MicroMipsInstrInfo.td:1100 |
| 655 | PseudoMFLO = 640, // MipsInstrInfo.td:2466 |
| 656 | PseudoMFLO64 = 641, // Mips64InstrInfo.td:351 |
| 657 | PseudoMFLO_MM = 642, // MicroMipsInstrInfo.td:1102 |
| 658 | PseudoMSUB = 643, // MipsInstrInfo.td:2472 |
| 659 | PseudoMSUBU = 644, // MipsInstrInfo.td:2474 |
| 660 | PseudoMSUBU_MM = 645, // MicroMipsInstrInfo.td:1112 |
| 661 | PseudoMSUB_MM = 646, // MicroMipsInstrInfo.td:1110 |
| 662 | PseudoMTLOHI = 647, // MipsInstrInfo.td:2467 |
| 663 | PseudoMTLOHI64 = 648, // Mips64InstrInfo.td:353 |
| 664 | PseudoMTLOHI_DSP = 649, // MipsDSPInstrInfo.td:1327 |
| 665 | PseudoMTLOHI_MM = 650, // MicroMipsInstrInfo.td:1104 |
| 666 | PseudoMULT = 651, // MipsInstrInfo.td:2461 |
| 667 | PseudoMULT_MM = 652, // MicroMipsInstrInfo.td:1096 |
| 668 | PseudoMULTu = 653, // MipsInstrInfo.td:2463 |
| 669 | PseudoMULTu_MM = 654, // MicroMipsInstrInfo.td:1098 |
| 670 | PseudoPICK_PH = 655, // MipsDSPInstrInfo.td:1323 |
| 671 | PseudoPICK_QB = 656, // MipsDSPInstrInfo.td:1324 |
| 672 | PseudoReturn = 657, // MipsInstrInfo.td:2378 |
| 673 | PseudoReturn64 = 658, // Mips64InstrInfo.td:292 |
| 674 | PseudoSDIV = 659, // MipsInstrInfo.td:2479 |
| 675 | PseudoSELECTFP_F_D32 = 660, // MipsCondMov.td:298 |
| 676 | PseudoSELECTFP_F_D64 = 661, // MipsCondMov.td:299 |
| 677 | PseudoSELECTFP_F_I = 662, // MipsCondMov.td:295 |
| 678 | PseudoSELECTFP_F_I64 = 663, // MipsCondMov.td:296 |
| 679 | PseudoSELECTFP_F_S = 664, // MipsCondMov.td:297 |
| 680 | PseudoSELECTFP_T_D32 = 665, // MipsCondMov.td:292 |
| 681 | PseudoSELECTFP_T_D64 = 666, // MipsCondMov.td:293 |
| 682 | PseudoSELECTFP_T_I = 667, // MipsCondMov.td:289 |
| 683 | PseudoSELECTFP_T_I64 = 668, // MipsCondMov.td:290 |
| 684 | PseudoSELECTFP_T_S = 669, // MipsCondMov.td:291 |
| 685 | PseudoSELECT_D32 = 670, // MipsCondMov.td:286 |
| 686 | PseudoSELECT_D64 = 671, // MipsCondMov.td:287 |
| 687 | PseudoSELECT_I = 672, // MipsCondMov.td:283 |
| 688 | PseudoSELECT_I64 = 673, // MipsCondMov.td:284 |
| 689 | PseudoSELECT_S = 674, // MipsCondMov.td:285 |
| 690 | PseudoTRUNC_W_D = 675, // MipsInstrFPU.td:822 |
| 691 | PseudoTRUNC_W_D32 = 676, // MipsInstrFPU.td:817 |
| 692 | PseudoTRUNC_W_S = 677, // MipsInstrFPU.td:813 |
| 693 | PseudoUDIV = 678, // MipsInstrInfo.td:2481 |
| 694 | ROL = 679, // MipsInstrInfo.td:2594 |
| 695 | ROLImm = 680, // MipsInstrInfo.td:2597 |
| 696 | ROR = 681, // MipsInstrInfo.td:2605 |
| 697 | RORImm = 682, // MipsInstrInfo.td:2608 |
| 698 | RetRA = 683, // MipsInstrInfo.td:1942 |
| 699 | RetRA16 = 684, // Mips16InstrInfo.td:1396 |
| 700 | SDC1_M1 = 685, // MipsInstrFPU.td:850 |
| 701 | SDIV_MM_Pseudo = 686, // MicroMipsInstrInfo.td:1316 |
| 702 | SDMacro = 687, // MipsInstrInfo.td:3167 |
| 703 | SDivIMacro = 688, // MipsInstrInfo.td:3079 |
| 704 | SDivMacro = 689, // MipsInstrInfo.td:3075 |
| 705 | SEQIMacro = 690, // MipsInstrInfo.td:2653 |
| 706 | SEQMacro = 691, // MipsInstrInfo.td:2645 |
| 707 | SGE = 692, // MipsInstrInfo.td:2767 |
| 708 | SGEImm = 693, // MipsInstrInfo.td:2773 |
| 709 | SGEImm64 = 694, // Mips64InstrInfo.td:1247 |
| 710 | SGEU = 695, // MipsInstrInfo.td:2781 |
| 711 | SGEUImm = 696, // MipsInstrInfo.td:2787 |
| 712 | SGEUImm64 = 697, // Mips64InstrInfo.td:1254 |
| 713 | SGTImm = 698, // MipsInstrInfo.td:2802 |
| 714 | SGTImm64 = 699, // Mips64InstrInfo.td:1261 |
| 715 | SGTUImm = 700, // MipsInstrInfo.td:2816 |
| 716 | SGTUImm64 = 701, // Mips64InstrInfo.td:1268 |
| 717 | SLE = 702, // MipsInstrInfo.td:2824 |
| 718 | SLEImm = 703, // MipsInstrInfo.td:2830 |
| 719 | SLEImm64 = 704, // Mips64InstrInfo.td:1275 |
| 720 | SLEU = 705, // MipsInstrInfo.td:2838 |
| 721 | SLEUImm = 706, // MipsInstrInfo.td:2844 |
| 722 | SLEUImm64 = 707, // Mips64InstrInfo.td:1282 |
| 723 | SLTImm64 = 708, // Mips64InstrInfo.td:1236 |
| 724 | SLTUImm64 = 709, // Mips64InstrInfo.td:1241 |
| 725 | SNEIMacro = 710, // MipsInstrInfo.td:2669 |
| 726 | SNEMacro = 711, // MipsInstrInfo.td:2661 |
| 727 | SNZ_B_PSEUDO = 712, // MipsMSAInstrInfo.td:3706 |
| 728 | SNZ_D_PSEUDO = 713, // MipsMSAInstrInfo.td:3712 |
| 729 | SNZ_H_PSEUDO = 714, // MipsMSAInstrInfo.td:3708 |
| 730 | SNZ_V_PSEUDO = 715, // MipsMSAInstrInfo.td:3714 |
| 731 | SNZ_W_PSEUDO = 716, // MipsMSAInstrInfo.td:3710 |
| 732 | SRemIMacro = 717, // MipsInstrInfo.td:3123 |
| 733 | SRemMacro = 718, // MipsInstrInfo.td:3119 |
| 734 | STORE_ACC128 = 719, // Mips64InstrInfo.td:111 |
| 735 | STORE_ACC64 = 720, // MipsInstrInfo.td:2040 |
| 736 | STORE_ACC64DSP = 721, // MipsDSPInstrInfo.td:1292 |
| 737 | STORE_CCOND_DSP = 722, // MipsDSPInstrInfo.td:1296 |
| 738 | STR_D = 723, // MipsMSAInstrInfo.td:2627 |
| 739 | STR_W = 724, // MipsMSAInstrInfo.td:2628 |
| 740 | ST_F16 = 725, // MipsMSAInstrInfo.td:3727 |
| 741 | SWM_MM = 726, // MicroMipsInstrInfo.td:891 |
| 742 | SZ_B_PSEUDO = 727, // MipsMSAInstrInfo.td:3717 |
| 743 | SZ_D_PSEUDO = 728, // MipsMSAInstrInfo.td:3720 |
| 744 | SZ_H_PSEUDO = 729, // MipsMSAInstrInfo.td:3718 |
| 745 | SZ_V_PSEUDO = 730, // MipsMSAInstrInfo.td:3721 |
| 746 | SZ_W_PSEUDO = 731, // MipsMSAInstrInfo.td:3719 |
| 747 | SaaAddr = 732, // Mips64InstrInfo.td:622 |
| 748 | SaadAddr = 733, // Mips64InstrInfo.td:624 |
| 749 | SelBeqZ = 734, // Mips16InstrInfo.td:1040 |
| 750 | SelBneZ = 735, // Mips16InstrInfo.td:1095 |
| 751 | SelTBteqZCmp = 736, // Mips16InstrInfo.td:1048 |
| 752 | SelTBteqZCmpi = 737, // Mips16InstrInfo.td:1056 |
| 753 | SelTBteqZSlt = 738, // Mips16InstrInfo.td:1064 |
| 754 | SelTBteqZSlti = 739, // Mips16InstrInfo.td:1072 |
| 755 | SelTBteqZSltiu = 740, // Mips16InstrInfo.td:1088 |
| 756 | SelTBteqZSltu = 741, // Mips16InstrInfo.td:1080 |
| 757 | SelTBtneZCmp = 742, // Mips16InstrInfo.td:1103 |
| 758 | SelTBtneZCmpi = 743, // Mips16InstrInfo.td:1111 |
| 759 | SelTBtneZSlt = 744, // Mips16InstrInfo.td:1119 |
| 760 | SelTBtneZSlti = 745, // Mips16InstrInfo.td:1127 |
| 761 | SelTBtneZSltiu = 746, // Mips16InstrInfo.td:1143 |
| 762 | SelTBtneZSltu = 747, // Mips16InstrInfo.td:1135 |
| 763 | SltCCRxRy16 = 748, // Mips16InstrInfo.td:1223 |
| 764 | SltiCCRxImmX16 = 749, // Mips16InstrInfo.td:1187 |
| 765 | SltiuCCRxImmX16 = 750, // Mips16InstrInfo.td:1212 |
| 766 | SltuCCRxRy16 = 751, // Mips16InstrInfo.td:1239 |
| 767 | SltuRxRyRz16 = 752, // Mips16InstrInfo.td:1233 |
| 768 | TAILCALL = 753, // MipsInstrInfo.td:2337 |
| 769 | TAILCALL64R6REG = 754, // Mips64r6InstrInfo.td:327 |
| 770 | TAILCALLHB64R6REG = 755, // Mips64r6InstrInfo.td:335 |
| 771 | TAILCALLHBR6REG = 756, // Mips32r6InstrInfo.td:1217 |
| 772 | TAILCALLR6REG = 757, // Mips32r6InstrInfo.td:1209 |
| 773 | TAILCALLREG = 758, // MipsInstrInfo.td:2341 |
| 774 | TAILCALLREG64 = 759, // Mips64InstrInfo.td:296 |
| 775 | TAILCALLREGHB = 760, // MipsInstrInfo.td:2566 |
| 776 | TAILCALLREGHB64 = 761, // Mips64InstrInfo.td:304 |
| 777 | TAILCALLREG_MM = 762, // MicroMipsInstrInfo.td:1119 |
| 778 | TAILCALLREG_MMR6 = 763, // MicroMips32r6InstrInfo.td:1824 |
| 779 | TAILCALL_MM = 764, // MicroMipsInstrInfo.td:1116 |
| 780 | TAILCALL_MMR6 = 765, // MicroMips32r6InstrInfo.td:1822 |
| 781 | TRAP = 766, // MipsInstrInfo.td:2252 |
| 782 | TRAP_MM = 767, // MicroMipsInstrInfo.td:1019 |
| 783 | UDIV_MM_Pseudo = 768, // MicroMipsInstrInfo.td:1318 |
| 784 | UDivIMacro = 769, // MipsInstrInfo.td:3087 |
| 785 | UDivMacro = 770, // MipsInstrInfo.td:3083 |
| 786 | URemIMacro = 771, // MipsInstrInfo.td:3131 |
| 787 | URemMacro = 772, // MipsInstrInfo.td:3127 |
| 788 | Ulh = 773, // MipsInstrInfo.td:3149 |
| 789 | Ulhu = 774, // MipsInstrInfo.td:3152 |
| 790 | Ulw = 775, // MipsInstrInfo.td:3155 |
| 791 | Ush = 776, // MipsInstrInfo.td:3158 |
| 792 | Usw = 777, // MipsInstrInfo.td:3161 |
| 793 | XOR_V_D_PSEUDO = 778, // MipsMSAInstrInfo.td:3508 |
| 794 | XOR_V_H_PSEUDO = 779, // MipsMSAInstrInfo.td:3500 |
| 795 | XOR_V_W_PSEUDO = 780, // MipsMSAInstrInfo.td:3504 |
| 796 | ABSQ_S_PH = 781, // MipsDSPInstrInfo.td:1136 |
| 797 | ABSQ_S_PH_MM = 782, // MicroMipsDSPInstrInfo.td:426 |
| 798 | ABSQ_S_QB = 783, // MipsDSPInstrInfo.td:1248 |
| 799 | ABSQ_S_QB_MMR2 = 784, // MicroMipsDSPInstrInfo.td:532 |
| 800 | ABSQ_S_W = 785, // MipsDSPInstrInfo.td:1137 |
| 801 | ABSQ_S_W_MM = 786, // MicroMipsDSPInstrInfo.td:427 |
| 802 | ADD = 787, // MipsInstrInfo.td:2111 |
| 803 | ADDIUPC = 788, // Mips32r6InstrInfo.td:873 |
| 804 | ADDIUPC_MM = 789, // MicroMipsInstrInfo.td:768 |
| 805 | ADDIUPC_MMR6 = 790, // MicroMips32r6InstrInfo.td:1353 |
| 806 | ADDIUR1SP_MM = 791, // MicroMipsInstrInfo.td:650 |
| 807 | ADDIUR2_MM = 792, // MicroMipsInstrInfo.td:652 |
| 808 | ADDIUS5_MM = 793, // MicroMipsInstrInfo.td:654 |
| 809 | ADDIUSP_MM = 794, // MicroMipsInstrInfo.td:656 |
| 810 | ADDIU_MMR6 = 795, // MicroMips32r6InstrInfo.td:1351 |
| 811 | ADDQH_PH = 796, // MipsDSPInstrInfo.td:1253 |
| 812 | ADDQH_PH_MMR2 = 797, // MicroMipsDSPInstrInfo.td:534 |
| 813 | ADDQH_R_PH = 798, // MipsDSPInstrInfo.td:1254 |
| 814 | ADDQH_R_PH_MMR2 = 799, // MicroMipsDSPInstrInfo.td:535 |
| 815 | ADDQH_R_W = 800, // MipsDSPInstrInfo.td:1258 |
| 816 | ADDQH_R_W_MMR2 = 801, // MicroMipsDSPInstrInfo.td:537 |
| 817 | ADDQH_W = 802, // MipsDSPInstrInfo.td:1257 |
| 818 | ADDQH_W_MMR2 = 803, // MicroMipsDSPInstrInfo.td:536 |
| 819 | ADDQ_PH = 804, // MipsDSPInstrInfo.td:1126 |
| 820 | ADDQ_PH_MM = 805, // MicroMipsDSPInstrInfo.td:415 |
| 821 | ADDQ_S_PH = 806, // MipsDSPInstrInfo.td:1127 |
| 822 | ADDQ_S_PH_MM = 807, // MicroMipsDSPInstrInfo.td:416 |
| 823 | ADDQ_S_W = 808, // MipsDSPInstrInfo.td:1130 |
| 824 | ADDQ_S_W_MM = 809, // MicroMipsDSPInstrInfo.td:417 |
| 825 | ADDR_PS64 = 810, // MipsInstrFPU.td:514 |
| 826 | ADDSC = 811, // MipsDSPInstrInfo.td:1132 |
| 827 | ADDSC_MM = 812, // MicroMipsDSPInstrInfo.td:420 |
| 828 | ADDS_A_B = 813, // MipsMSAInstrInfo.td:2699 |
| 829 | ADDS_A_D = 814, // MipsMSAInstrInfo.td:2702 |
| 830 | ADDS_A_H = 815, // MipsMSAInstrInfo.td:2700 |
| 831 | ADDS_A_W = 816, // MipsMSAInstrInfo.td:2701 |
| 832 | ADDS_S_B = 817, // MipsMSAInstrInfo.td:2704 |
| 833 | ADDS_S_D = 818, // MipsMSAInstrInfo.td:2707 |
| 834 | ADDS_S_H = 819, // MipsMSAInstrInfo.td:2705 |
| 835 | ADDS_S_W = 820, // MipsMSAInstrInfo.td:2706 |
| 836 | ADDS_U_B = 821, // MipsMSAInstrInfo.td:2709 |
| 837 | ADDS_U_D = 822, // MipsMSAInstrInfo.td:2712 |
| 838 | ADDS_U_H = 823, // MipsMSAInstrInfo.td:2710 |
| 839 | ADDS_U_W = 824, // MipsMSAInstrInfo.td:2711 |
| 840 | ADDU16_MM = 825, // MicroMipsInstrInfo.td:605 |
| 841 | ADDU16_MMR6 = 826, // MicroMips32r6InstrInfo.td:1549 |
| 842 | ADDUH_QB = 827, // MipsDSPInstrInfo.td:1249 |
| 843 | ADDUH_QB_MMR2 = 828, // MicroMipsDSPInstrInfo.td:540 |
| 844 | ADDUH_R_QB = 829, // MipsDSPInstrInfo.td:1250 |
| 845 | ADDUH_R_QB_MMR2 = 830, // MicroMipsDSPInstrInfo.td:541 |
| 846 | ADDU_MMR6 = 831, // MicroMips32r6InstrInfo.td:1352 |
| 847 | ADDU_PH = 832, // MipsDSPInstrInfo.td:1241 |
| 848 | ADDU_PH_MMR2 = 833, // MicroMipsDSPInstrInfo.td:538 |
| 849 | ADDU_QB = 834, // MipsDSPInstrInfo.td:1122 |
| 850 | ADDU_QB_MM = 835, // MicroMipsDSPInstrInfo.td:418 |
| 851 | ADDU_S_PH = 836, // MipsDSPInstrInfo.td:1242 |
| 852 | ADDU_S_PH_MMR2 = 837, // MicroMipsDSPInstrInfo.td:539 |
| 853 | ADDU_S_QB = 838, // MipsDSPInstrInfo.td:1123 |
| 854 | ADDU_S_QB_MM = 839, // MicroMipsDSPInstrInfo.td:419 |
| 855 | ADDVI_B = 840, // MipsMSAInstrInfo.td:2719 |
| 856 | ADDVI_D = 841, // MipsMSAInstrInfo.td:2722 |
| 857 | ADDVI_H = 842, // MipsMSAInstrInfo.td:2720 |
| 858 | ADDVI_W = 843, // MipsMSAInstrInfo.td:2721 |
| 859 | ADDV_B = 844, // MipsMSAInstrInfo.td:2714 |
| 860 | ADDV_D = 845, // MipsMSAInstrInfo.td:2717 |
| 861 | ADDV_H = 846, // MipsMSAInstrInfo.td:2715 |
| 862 | ADDV_W = 847, // MipsMSAInstrInfo.td:2716 |
| 863 | ADDWC = 848, // MipsDSPInstrInfo.td:1133 |
| 864 | ADDWC_MM = 849, // MicroMipsDSPInstrInfo.td:421 |
| 865 | ADD_A_B = 850, // MipsMSAInstrInfo.td:2694 |
| 866 | ADD_A_D = 851, // MipsMSAInstrInfo.td:2697 |
| 867 | ADD_A_H = 852, // MipsMSAInstrInfo.td:2695 |
| 868 | ADD_A_W = 853, // MipsMSAInstrInfo.td:2696 |
| 869 | ADD_MM = 854, // MicroMipsInstrInfo.td:742 |
| 870 | ADD_MMR6 = 855, // MicroMips32r6InstrInfo.td:1350 |
| 871 | ADDi = 856, // MipsInstrInfo.td:2091 |
| 872 | ADDi_MM = 857, // MicroMipsInstrInfo.td:714 |
| 873 | ADDiu = 858, // MipsInstrInfo.td:2078 |
| 874 | ADDiu_MM = 859, // MicroMipsInstrInfo.td:712 |
| 875 | ADDu = 860, // MipsInstrInfo.td:2102 |
| 876 | ADDu_MM = 861, // MicroMipsInstrInfo.td:735 |
| 877 | ALIGN = 862, // Mips32r6InstrInfo.td:874 |
| 878 | ALIGN_MMR6 = 863, // MicroMips32r6InstrInfo.td:1360 |
| 879 | ALUIPC = 864, // Mips32r6InstrInfo.td:875 |
| 880 | ALUIPC_MMR6 = 865, // MicroMips32r6InstrInfo.td:1355 |
| 881 | AND = 866, // MipsInstrInfo.td:2120 |
| 882 | AND16_MM = 867, // MicroMipsInstrInfo.td:607 |
| 883 | AND16_MMR6 = 868, // MicroMips32r6InstrInfo.td:1551 |
| 884 | AND64 = 869, // Mips64InstrInfo.td:156 |
| 885 | ANDI16_MM = 870, // MicroMipsInstrInfo.td:611 |
| 886 | ANDI16_MMR6 = 871, // MicroMips32r6InstrInfo.td:1553 |
| 887 | ANDI_B = 872, // MipsMSAInstrInfo.td:2738 |
| 888 | ANDI_MMR6 = 873, // MicroMips32r6InstrInfo.td:1358 |
| 889 | AND_MM = 874, // MicroMipsInstrInfo.td:750 |
| 890 | AND_MMR6 = 875, // MicroMips32r6InstrInfo.td:1357 |
| 891 | AND_V = 876, // MipsMSAInstrInfo.td:2724 |
| 892 | ANDi = 877, // MipsInstrInfo.td:2082 |
| 893 | ANDi64 = 878, // Mips64InstrInfo.td:132 |
| 894 | ANDi_MM = 879, // MicroMipsInstrInfo.td:720 |
| 895 | APPEND = 880, // MipsDSPInstrInfo.td:1284 |
| 896 | APPEND_MMR2 = 881, // MicroMipsDSPInstrInfo.td:592 |
| 897 | ASUB_S_B = 882, // MipsMSAInstrInfo.td:2740 |
| 898 | ASUB_S_D = 883, // MipsMSAInstrInfo.td:2743 |
| 899 | ASUB_S_H = 884, // MipsMSAInstrInfo.td:2741 |
| 900 | ASUB_S_W = 885, // MipsMSAInstrInfo.td:2742 |
| 901 | ASUB_U_B = 886, // MipsMSAInstrInfo.td:2745 |
| 902 | ASUB_U_D = 887, // MipsMSAInstrInfo.td:2748 |
| 903 | ASUB_U_H = 888, // MipsMSAInstrInfo.td:2746 |
| 904 | ASUB_U_W = 889, // MipsMSAInstrInfo.td:2747 |
| 905 | AUI = 890, // Mips32r6InstrInfo.td:876 |
| 906 | AUIPC = 891, // Mips32r6InstrInfo.td:877 |
| 907 | AUIPC_MMR6 = 892, // MicroMips32r6InstrInfo.td:1359 |
| 908 | AUI_MMR6 = 893, // MicroMips32r6InstrInfo.td:1361 |
| 909 | AVER_S_B = 894, // MipsMSAInstrInfo.td:2760 |
| 910 | AVER_S_D = 895, // MipsMSAInstrInfo.td:2763 |
| 911 | AVER_S_H = 896, // MipsMSAInstrInfo.td:2761 |
| 912 | AVER_S_W = 897, // MipsMSAInstrInfo.td:2762 |
| 913 | AVER_U_B = 898, // MipsMSAInstrInfo.td:2765 |
| 914 | AVER_U_D = 899, // MipsMSAInstrInfo.td:2768 |
| 915 | AVER_U_H = 900, // MipsMSAInstrInfo.td:2766 |
| 916 | AVER_U_W = 901, // MipsMSAInstrInfo.td:2767 |
| 917 | AVE_S_B = 902, // MipsMSAInstrInfo.td:2750 |
| 918 | AVE_S_D = 903, // MipsMSAInstrInfo.td:2753 |
| 919 | AVE_S_H = 904, // MipsMSAInstrInfo.td:2751 |
| 920 | AVE_S_W = 905, // MipsMSAInstrInfo.td:2752 |
| 921 | AVE_U_B = 906, // MipsMSAInstrInfo.td:2755 |
| 922 | AVE_U_D = 907, // MipsMSAInstrInfo.td:2758 |
| 923 | AVE_U_H = 908, // MipsMSAInstrInfo.td:2756 |
| 924 | AVE_U_W = 909, // MipsMSAInstrInfo.td:2757 |
| 925 | AddiuRxImmX16 = 910, // Mips16InstrInfo.td:529 |
| 926 | AddiuRxPcImmX16 = 911, // Mips16InstrInfo.td:550 |
| 927 | AddiuRxRxImm16 = 912, // Mips16InstrInfo.td:531 |
| 928 | AddiuRxRxImmX16 = 913, // Mips16InstrInfo.td:535 |
| 929 | AddiuRxRyOffMemX16 = 914, // Mips16InstrInfo.td:541 |
| 930 | AddiuSpImm16 = 915, // Mips16InstrInfo.td:557 |
| 931 | AddiuSpImmX16 = 916, // Mips16InstrInfo.td:564 |
| 932 | AdduRxRyRz16 = 917, // Mips16InstrInfo.td:576 |
| 933 | AndRxRxRy16 = 918, // Mips16InstrInfo.td:583 |
| 934 | B16_MM = 919, // MicroMipsInstrInfo.td:682 |
| 935 | BADDu = 920, // Mips64InstrInfo.td:517 |
| 936 | BAL = 921, // Mips32r6InstrInfo.td:878 |
| 937 | BALC = 922, // Mips32r6InstrInfo.td:879 |
| 938 | BALC_MMR6 = 923, // MicroMips32r6InstrInfo.td:1362 |
| 939 | BALIGN = 924, // MipsDSPInstrInfo.td:1285 |
| 940 | BALIGN_MMR2 = 925, // MicroMipsDSPInstrInfo.td:554 |
| 941 | BBIT0 = 926, // Mips64InstrInfo.td:524 |
| 942 | BBIT032 = 927, // Mips64InstrInfo.td:526 |
| 943 | BBIT1 = 928, // Mips64InstrInfo.td:530 |
| 944 | BBIT132 = 929, // Mips64InstrInfo.td:532 |
| 945 | BC = 930, // Mips32r6InstrInfo.td:887 |
| 946 | BC16_MMR6 = 931, // MicroMips32r6InstrInfo.td:1364 |
| 947 | BC1EQZ = 932, // Mips32r6InstrInfo.td:883 |
| 948 | BC1EQZC_MMR6 = 933, // MicroMips32r6InstrInfo.td:1620 |
| 949 | BC1F = 934, // MipsInstrFPU.td:750 |
| 950 | BC1FL = 935, // MipsInstrFPU.td:752 |
| 951 | BC1F_MM = 936, // MicroMipsInstrFPU.td:76 |
| 952 | BC1NEZ = 937, // Mips32r6InstrInfo.td:884 |
| 953 | BC1NEZC_MMR6 = 938, // MicroMips32r6InstrInfo.td:1622 |
| 954 | BC1T = 939, // MipsInstrFPU.td:754 |
| 955 | BC1TL = 940, // MipsInstrFPU.td:756 |
| 956 | BC1T_MM = 941, // MicroMipsInstrFPU.td:78 |
| 957 | BC2EQZ = 942, // Mips32r6InstrInfo.td:885 |
| 958 | BC2EQZC_MMR6 = 943, // MicroMips32r6InstrInfo.td:1624 |
| 959 | BC2NEZ = 944, // Mips32r6InstrInfo.td:886 |
| 960 | BC2NEZC_MMR6 = 945, // MicroMips32r6InstrInfo.td:1626 |
| 961 | BCLRI_B = 946, // MipsMSAInstrInfo.td:2775 |
| 962 | BCLRI_D = 947, // MipsMSAInstrInfo.td:2778 |
| 963 | BCLRI_H = 948, // MipsMSAInstrInfo.td:2776 |
| 964 | BCLRI_W = 949, // MipsMSAInstrInfo.td:2777 |
| 965 | BCLR_B = 950, // MipsMSAInstrInfo.td:2770 |
| 966 | BCLR_D = 951, // MipsMSAInstrInfo.td:2773 |
| 967 | BCLR_H = 952, // MipsMSAInstrInfo.td:2771 |
| 968 | BCLR_W = 953, // MipsMSAInstrInfo.td:2772 |
| 969 | BC_MMR6 = 954, // MicroMips32r6InstrInfo.td:1363 |
| 970 | BEQ = 955, // MipsInstrInfo.td:2288 |
| 971 | BEQ64 = 956, // Mips64InstrInfo.td:271 |
| 972 | BEQC = 957, // Mips32r6InstrInfo.td:888 |
| 973 | BEQC64 = 958, // Mips64r6InstrInfo.td:171 |
| 974 | BEQC_MMR6 = 959, // MicroMips32r6InstrInfo.td:1652 |
| 975 | BEQL = 960, // MipsInstrInfo.td:2290 |
| 976 | BEQZ16_MM = 961, // MicroMipsInstrInfo.td:678 |
| 977 | BEQZALC = 962, // Mips32r6InstrInfo.td:889 |
| 978 | BEQZALC_MMR6 = 963, // MicroMips32r6InstrInfo.td:1375 |
| 979 | BEQZC = 964, // Mips32r6InstrInfo.td:890 |
| 980 | BEQZC16_MMR6 = 965, // MicroMips32r6InstrInfo.td:1367 |
| 981 | BEQZC64 = 966, // Mips64r6InstrInfo.td:172 |
| 982 | BEQZC_MM = 967, // MicroMipsInstrInfo.td:706 |
| 983 | BEQZC_MMR6 = 968, // MicroMips32r6InstrInfo.td:1365 |
| 984 | BEQ_MM = 969, // MicroMipsInstrInfo.td:973 |
| 985 | BGEC = 970, // Mips32r6InstrInfo.td:891 |
| 986 | BGEC64 = 971, // Mips64r6InstrInfo.td:173 |
| 987 | BGEC_MMR6 = 972, // MicroMips32r6InstrInfo.td:1648 |
| 988 | BGEUC = 973, // Mips32r6InstrInfo.td:892 |
| 989 | BGEUC64 = 974, // Mips64r6InstrInfo.td:174 |
| 990 | BGEUC_MMR6 = 975, // MicroMips32r6InstrInfo.td:1649 |
| 991 | BGEZ = 976, // MipsInstrInfo.td:2296 |
| 992 | BGEZ64 = 977, // Mips64InstrInfo.td:275 |
| 993 | BGEZAL = 978, // MipsInstrInfo.td:2326 |
| 994 | BGEZALC = 979, // Mips32r6InstrInfo.td:893 |
| 995 | BGEZALC_MMR6 = 980, // MicroMips32r6InstrInfo.td:1660 |
| 996 | BGEZALL = 981, // MipsInstrInfo.td:2328 |
| 997 | BGEZALS_MM = 982, // MicroMipsInstrInfo.td:993 |
| 998 | BGEZAL_MM = 983, // MicroMipsInstrInfo.td:985 |
| 999 | BGEZC = 984, // Mips32r6InstrInfo.td:894 |
| 1000 | BGEZC64 = 985, // Mips64r6InstrInfo.td:184 |
| 1001 | BGEZC_MMR6 = 986, // MicroMips32r6InstrInfo.td:1658 |
| 1002 | BGEZL = 987, // MipsInstrInfo.td:2298 |
| 1003 | BGEZ_MM = 988, // MicroMipsInstrInfo.td:977 |
| 1004 | BGTZ = 989, // MipsInstrInfo.td:2300 |
| 1005 | BGTZ64 = 990, // Mips64InstrInfo.td:277 |
| 1006 | BGTZALC = 991, // Mips32r6InstrInfo.td:895 |
| 1007 | BGTZALC_MMR6 = 992, // MicroMips32r6InstrInfo.td:1662 |
| 1008 | BGTZC = 993, // Mips32r6InstrInfo.td:896 |
| 1009 | BGTZC64 = 994, // Mips64r6InstrInfo.td:175 |
| 1010 | BGTZC_MMR6 = 995, // MicroMips32r6InstrInfo.td:1659 |
| 1011 | BGTZL = 996, // MipsInstrInfo.td:2302 |
| 1012 | BGTZ_MM = 997, // MicroMipsInstrInfo.td:979 |
| 1013 | BINSLI_B = 998, // MipsMSAInstrInfo.td:2785 |
| 1014 | BINSLI_D = 999, // MipsMSAInstrInfo.td:2788 |
| 1015 | BINSLI_H = 1000, // MipsMSAInstrInfo.td:2786 |
| 1016 | BINSLI_W = 1001, // MipsMSAInstrInfo.td:2787 |
| 1017 | BINSL_B = 1002, // MipsMSAInstrInfo.td:2780 |
| 1018 | BINSL_D = 1003, // MipsMSAInstrInfo.td:2783 |
| 1019 | BINSL_H = 1004, // MipsMSAInstrInfo.td:2781 |
| 1020 | BINSL_W = 1005, // MipsMSAInstrInfo.td:2782 |
| 1021 | BINSRI_B = 1006, // MipsMSAInstrInfo.td:2795 |
| 1022 | BINSRI_D = 1007, // MipsMSAInstrInfo.td:2798 |
| 1023 | BINSRI_H = 1008, // MipsMSAInstrInfo.td:2796 |
| 1024 | BINSRI_W = 1009, // MipsMSAInstrInfo.td:2797 |
| 1025 | BINSR_B = 1010, // MipsMSAInstrInfo.td:2790 |
| 1026 | BINSR_D = 1011, // MipsMSAInstrInfo.td:2793 |
| 1027 | BINSR_H = 1012, // MipsMSAInstrInfo.td:2791 |
| 1028 | BINSR_W = 1013, // MipsMSAInstrInfo.td:2792 |
| 1029 | BITREV = 1014, // MipsDSPInstrInfo.td:1205 |
| 1030 | BITREV_MM = 1015, // MicroMipsDSPInstrInfo.td:519 |
| 1031 | BITSWAP = 1016, // Mips32r6InstrInfo.td:898 |
| 1032 | BITSWAP_MMR6 = 1017, // MicroMips32r6InstrInfo.td:1373 |
| 1033 | BLEZ = 1018, // MipsInstrInfo.td:2304 |
| 1034 | BLEZ64 = 1019, // Mips64InstrInfo.td:279 |
| 1035 | BLEZALC = 1020, // Mips32r6InstrInfo.td:900 |
| 1036 | BLEZALC_MMR6 = 1021, // MicroMips32r6InstrInfo.td:1664 |
| 1037 | BLEZC = 1022, // Mips32r6InstrInfo.td:901 |
| 1038 | BLEZC64 = 1023, // Mips64r6InstrInfo.td:176 |
| 1039 | BLEZC_MMR6 = 1024, // MicroMips32r6InstrInfo.td:1657 |
| 1040 | BLEZL = 1025, // MipsInstrInfo.td:2306 |
| 1041 | BLEZ_MM = 1026, // MicroMipsInstrInfo.td:981 |
| 1042 | BLTC = 1027, // Mips32r6InstrInfo.td:902 |
| 1043 | BLTC64 = 1028, // Mips64r6InstrInfo.td:177 |
| 1044 | BLTC_MMR6 = 1029, // MicroMips32r6InstrInfo.td:1650 |
| 1045 | BLTUC = 1030, // Mips32r6InstrInfo.td:903 |
| 1046 | BLTUC64 = 1031, // Mips64r6InstrInfo.td:178 |
| 1047 | BLTUC_MMR6 = 1032, // MicroMips32r6InstrInfo.td:1651 |
| 1048 | BLTZ = 1033, // MipsInstrInfo.td:2308 |
| 1049 | BLTZ64 = 1034, // Mips64InstrInfo.td:281 |
| 1050 | BLTZAL = 1035, // MipsInstrInfo.td:2330 |
| 1051 | BLTZALC = 1036, // Mips32r6InstrInfo.td:904 |
| 1052 | BLTZALC_MMR6 = 1037, // MicroMips32r6InstrInfo.td:1666 |
| 1053 | BLTZALL = 1038, // MipsInstrInfo.td:2332 |
| 1054 | BLTZALS_MM = 1039, // MicroMipsInstrInfo.td:996 |
| 1055 | BLTZAL_MM = 1040, // MicroMipsInstrInfo.td:987 |
| 1056 | BLTZC = 1041, // Mips32r6InstrInfo.td:905 |
| 1057 | BLTZC64 = 1042, // Mips64r6InstrInfo.td:183 |
| 1058 | BLTZC_MMR6 = 1043, // MicroMips32r6InstrInfo.td:1656 |
| 1059 | BLTZL = 1044, // MipsInstrInfo.td:2310 |
| 1060 | BLTZ_MM = 1045, // MicroMipsInstrInfo.td:983 |
| 1061 | BMNZI_B = 1046, // MipsMSAInstrInfo.td:2802 |
| 1062 | BMNZ_V = 1047, // MipsMSAInstrInfo.td:2800 |
| 1063 | BMZI_B = 1048, // MipsMSAInstrInfo.td:2806 |
| 1064 | BMZ_V = 1049, // MipsMSAInstrInfo.td:2804 |
| 1065 | BNE = 1050, // MipsInstrInfo.td:2292 |
| 1066 | BNE64 = 1051, // Mips64InstrInfo.td:273 |
| 1067 | BNEC = 1052, // Mips32r6InstrInfo.td:906 |
| 1068 | BNEC64 = 1053, // Mips64r6InstrInfo.td:179 |
| 1069 | BNEC_MMR6 = 1054, // MicroMips32r6InstrInfo.td:1654 |
| 1070 | BNEGI_B = 1055, // MipsMSAInstrInfo.td:2813 |
| 1071 | BNEGI_D = 1056, // MipsMSAInstrInfo.td:2816 |
| 1072 | BNEGI_H = 1057, // MipsMSAInstrInfo.td:2814 |
| 1073 | BNEGI_W = 1058, // MipsMSAInstrInfo.td:2815 |
| 1074 | BNEG_B = 1059, // MipsMSAInstrInfo.td:2808 |
| 1075 | BNEG_D = 1060, // MipsMSAInstrInfo.td:2811 |
| 1076 | BNEG_H = 1061, // MipsMSAInstrInfo.td:2809 |
| 1077 | BNEG_W = 1062, // MipsMSAInstrInfo.td:2810 |
| 1078 | BNEL = 1063, // MipsInstrInfo.td:2294 |
| 1079 | BNEZ16_MM = 1064, // MicroMipsInstrInfo.td:680 |
| 1080 | BNEZALC = 1065, // Mips32r6InstrInfo.td:907 |
| 1081 | BNEZALC_MMR6 = 1066, // MicroMips32r6InstrInfo.td:1377 |
| 1082 | BNEZC = 1067, // Mips32r6InstrInfo.td:908 |
| 1083 | BNEZC16_MMR6 = 1068, // MicroMips32r6InstrInfo.td:1371 |
| 1084 | BNEZC64 = 1069, // Mips64r6InstrInfo.td:180 |
| 1085 | BNEZC_MM = 1070, // MicroMipsInstrInfo.td:708 |
| 1086 | BNEZC_MMR6 = 1071, // MicroMips32r6InstrInfo.td:1369 |
| 1087 | BNE_MM = 1072, // MicroMipsInstrInfo.td:975 |
| 1088 | BNVC = 1073, // Mips32r6InstrInfo.td:909 |
| 1089 | BNVC_MMR6 = 1074, // MicroMips32r6InstrInfo.td:1646 |
| 1090 | BNZ_B = 1075, // MipsMSAInstrInfo.td:2818 |
| 1091 | BNZ_D = 1076, // MipsMSAInstrInfo.td:2821 |
| 1092 | BNZ_H = 1077, // MipsMSAInstrInfo.td:2819 |
| 1093 | BNZ_V = 1078, // MipsMSAInstrInfo.td:2823 |
| 1094 | BNZ_W = 1079, // MipsMSAInstrInfo.td:2820 |
| 1095 | BOVC = 1080, // Mips32r6InstrInfo.td:910 |
| 1096 | BOVC_MMR6 = 1081, // MicroMips32r6InstrInfo.td:1644 |
| 1097 | BPOSGE32 = 1082, // MipsDSPInstrInfo.td:1217 |
| 1098 | BPOSGE32C_MMR3 = 1083, // MicroMipsDSPInstrInfo.td:595 |
| 1099 | BPOSGE32_MM = 1084, // MicroMipsDSPInstrInfo.td:520 |
| 1100 | BREAK = 1085, // MipsInstrInfo.td:2249 |
| 1101 | BREAK16_MM = 1086, // MicroMipsInstrInfo.td:683 |
| 1102 | BREAK16_MMR6 = 1087, // MicroMips32r6InstrInfo.td:1563 |
| 1103 | BREAK_MM = 1088, // MicroMipsInstrInfo.td:1007 |
| 1104 | BREAK_MMR6 = 1089, // MicroMips32r6InstrInfo.td:1379 |
| 1105 | BSELI_B = 1090, // MipsMSAInstrInfo.td:2845 |
| 1106 | BSEL_V = 1091, // MipsMSAInstrInfo.td:2825 |
| 1107 | BSETI_B = 1092, // MipsMSAInstrInfo.td:2852 |
| 1108 | BSETI_D = 1093, // MipsMSAInstrInfo.td:2855 |
| 1109 | BSETI_H = 1094, // MipsMSAInstrInfo.td:2853 |
| 1110 | BSETI_W = 1095, // MipsMSAInstrInfo.td:2854 |
| 1111 | BSET_B = 1096, // MipsMSAInstrInfo.td:2847 |
| 1112 | BSET_D = 1097, // MipsMSAInstrInfo.td:2850 |
| 1113 | BSET_H = 1098, // MipsMSAInstrInfo.td:2848 |
| 1114 | BSET_W = 1099, // MipsMSAInstrInfo.td:2849 |
| 1115 | BZ_B = 1100, // MipsMSAInstrInfo.td:2857 |
| 1116 | BZ_D = 1101, // MipsMSAInstrInfo.td:2860 |
| 1117 | BZ_H = 1102, // MipsMSAInstrInfo.td:2858 |
| 1118 | BZ_V = 1103, // MipsMSAInstrInfo.td:2862 |
| 1119 | BZ_W = 1104, // MipsMSAInstrInfo.td:2859 |
| 1120 | BeqzRxImm16 = 1105, // Mips16InstrInfo.td:591 |
| 1121 | BeqzRxImmX16 = 1106, // Mips16InstrInfo.td:599 |
| 1122 | Bimm16 = 1107, // Mips16InstrInfo.td:607 |
| 1123 | BimmX16 = 1108, // Mips16InstrInfo.td:613 |
| 1124 | BnezRxImm16 = 1109, // Mips16InstrInfo.td:620 |
| 1125 | BnezRxImmX16 = 1110, // Mips16InstrInfo.td:627 |
| 1126 | Break16 = 1111, // Mips16InstrInfo.td:635 |
| 1127 | Bteqz16 = 1112, // Mips16InstrInfo.td:641 |
| 1128 | BteqzX16 = 1113, // Mips16InstrInfo.td:645 |
| 1129 | Btnez16 = 1114, // Mips16InstrInfo.td:669 |
| 1130 | BtnezX16 = 1115, // Mips16InstrInfo.td:673 |
| 1131 | CACHE = 1116, // MipsInstrInfo.td:2588 |
| 1132 | CACHEE = 1117, // MipsEVAInstrInfo.td:214 |
| 1133 | CACHEE_MM = 1118, // MicroMipsInstrInfo.td:1069 |
| 1134 | CACHE_MM = 1119, // MicroMipsInstrInfo.td:1060 |
| 1135 | CACHE_MMR6 = 1120, // MicroMips32r6InstrInfo.td:1380 |
| 1136 | CACHE_R6 = 1121, // Mips32r6InstrInfo.td:911 |
| 1137 | CEIL_L_D64 = 1122, // MipsInstrFPU.td:449 |
| 1138 | CEIL_L_D_MMR6 = 1123, // MicroMips32r6InstrInfo.td:1530 |
| 1139 | CEIL_L_S = 1124, // MipsInstrFPU.td:447 |
| 1140 | CEIL_L_S_MMR6 = 1125, // MicroMips32r6InstrInfo.td:1528 |
| 1141 | CEIL_W_D32 = 1126, // MipsInstrFPU.td:166 |
| 1142 | CEIL_W_D64 = 1127, // MipsInstrFPU.td:167 |
| 1143 | CEIL_W_D_MMR6 = 1128, // MicroMips32r6InstrInfo.td:1534 |
| 1144 | CEIL_W_MM = 1129, // MicroMipsInstrFPU.td:91 |
| 1145 | CEIL_W_S = 1130, // MipsInstrFPU.td:396 |
| 1146 | CEIL_W_S_MM = 1131, // MicroMipsInstrFPU.td:235 |
| 1147 | CEIL_W_S_MMR6 = 1132, // MicroMips32r6InstrInfo.td:1532 |
| 1148 | CEQI_B = 1133, // MipsMSAInstrInfo.td:2869 |
| 1149 | CEQI_D = 1134, // MipsMSAInstrInfo.td:2872 |
| 1150 | CEQI_H = 1135, // MipsMSAInstrInfo.td:2870 |
| 1151 | CEQI_W = 1136, // MipsMSAInstrInfo.td:2871 |
| 1152 | CEQ_B = 1137, // MipsMSAInstrInfo.td:2864 |
| 1153 | CEQ_D = 1138, // MipsMSAInstrInfo.td:2867 |
| 1154 | CEQ_H = 1139, // MipsMSAInstrInfo.td:2865 |
| 1155 | CEQ_W = 1140, // MipsMSAInstrInfo.td:2866 |
| 1156 | CFC1 = 1141, // MipsInstrFPU.td:575 |
| 1157 | CFC1_MM = 1142, // MicroMipsInstrFPU.td:260 |
| 1158 | CFC2_MM = 1143, // MicroMipsInstrInfo.td:698 |
| 1159 | CFCMSA = 1144, // MipsMSAInstrInfo.td:2874 |
| 1160 | CINS = 1145, // Mips64InstrInfo.td:549 |
| 1161 | CINS32 = 1146, // Mips64InstrInfo.td:551 |
| 1162 | CINS64_32 = 1147, // Mips64InstrInfo.td:556 |
| 1163 | CINS_i32 = 1148, // Mips64InstrInfo.td:554 |
| 1164 | CLASS_D = 1149, // Mips32r6InstrInfo.td:912 |
| 1165 | CLASS_D_MMR6 = 1150, // MicroMips32r6InstrInfo.td:1612 |
| 1166 | CLASS_S = 1151, // Mips32r6InstrInfo.td:913 |
| 1167 | CLASS_S_MMR6 = 1152, // MicroMips32r6InstrInfo.td:1610 |
| 1168 | CLEI_S_B = 1153, // MipsMSAInstrInfo.td:2886 |
| 1169 | CLEI_S_D = 1154, // MipsMSAInstrInfo.td:2889 |
| 1170 | CLEI_S_H = 1155, // MipsMSAInstrInfo.td:2887 |
| 1171 | CLEI_S_W = 1156, // MipsMSAInstrInfo.td:2888 |
| 1172 | CLEI_U_B = 1157, // MipsMSAInstrInfo.td:2891 |
| 1173 | CLEI_U_D = 1158, // MipsMSAInstrInfo.td:2894 |
| 1174 | CLEI_U_H = 1159, // MipsMSAInstrInfo.td:2892 |
| 1175 | CLEI_U_W = 1160, // MipsMSAInstrInfo.td:2893 |
| 1176 | CLE_S_B = 1161, // MipsMSAInstrInfo.td:2876 |
| 1177 | CLE_S_D = 1162, // MipsMSAInstrInfo.td:2879 |
| 1178 | CLE_S_H = 1163, // MipsMSAInstrInfo.td:2877 |
| 1179 | CLE_S_W = 1164, // MipsMSAInstrInfo.td:2878 |
| 1180 | CLE_U_B = 1165, // MipsMSAInstrInfo.td:2881 |
| 1181 | CLE_U_D = 1166, // MipsMSAInstrInfo.td:2884 |
| 1182 | CLE_U_H = 1167, // MipsMSAInstrInfo.td:2882 |
| 1183 | CLE_U_W = 1168, // MipsMSAInstrInfo.td:2883 |
| 1184 | CLO = 1169, // MipsInstrInfo.td:2430 |
| 1185 | CLO_MM = 1170, // MicroMipsInstrInfo.td:928 |
| 1186 | CLO_MMR6 = 1171, // MicroMips32r6InstrInfo.td:1381 |
| 1187 | CLO_R6 = 1172, // Mips32r6InstrInfo.td:915 |
| 1188 | CLTI_S_B = 1173, // MipsMSAInstrInfo.td:2906 |
| 1189 | CLTI_S_D = 1174, // MipsMSAInstrInfo.td:2909 |
| 1190 | CLTI_S_H = 1175, // MipsMSAInstrInfo.td:2907 |
| 1191 | CLTI_S_W = 1176, // MipsMSAInstrInfo.td:2908 |
| 1192 | CLTI_U_B = 1177, // MipsMSAInstrInfo.td:2911 |
| 1193 | CLTI_U_D = 1178, // MipsMSAInstrInfo.td:2914 |
| 1194 | CLTI_U_H = 1179, // MipsMSAInstrInfo.td:2912 |
| 1195 | CLTI_U_W = 1180, // MipsMSAInstrInfo.td:2913 |
| 1196 | CLT_S_B = 1181, // MipsMSAInstrInfo.td:2896 |
| 1197 | CLT_S_D = 1182, // MipsMSAInstrInfo.td:2899 |
| 1198 | CLT_S_H = 1183, // MipsMSAInstrInfo.td:2897 |
| 1199 | CLT_S_W = 1184, // MipsMSAInstrInfo.td:2898 |
| 1200 | CLT_U_B = 1185, // MipsMSAInstrInfo.td:2901 |
| 1201 | CLT_U_D = 1186, // MipsMSAInstrInfo.td:2904 |
| 1202 | CLT_U_H = 1187, // MipsMSAInstrInfo.td:2902 |
| 1203 | CLT_U_W = 1188, // MipsMSAInstrInfo.td:2903 |
| 1204 | CLZ = 1189, // MipsInstrInfo.td:2428 |
| 1205 | CLZ_MM = 1190, // MicroMipsInstrInfo.td:926 |
| 1206 | CLZ_MMR6 = 1191, // MicroMips32r6InstrInfo.td:1382 |
| 1207 | CLZ_R6 = 1192, // Mips32r6InstrInfo.td:916 |
| 1208 | CMPGDU_EQ_QB = 1193, // MipsDSPInstrInfo.td:1245 |
| 1209 | CMPGDU_EQ_QB_MMR2 = 1194, // MicroMipsDSPInstrInfo.td:555 |
| 1210 | CMPGDU_LE_QB = 1195, // MipsDSPInstrInfo.td:1247 |
| 1211 | CMPGDU_LE_QB_MMR2 = 1196, // MicroMipsDSPInstrInfo.td:559 |
| 1212 | CMPGDU_LT_QB = 1197, // MipsDSPInstrInfo.td:1246 |
| 1213 | CMPGDU_LT_QB_MMR2 = 1198, // MicroMipsDSPInstrInfo.td:557 |
| 1214 | CMPGU_EQ_QB = 1199, // MipsDSPInstrInfo.td:1199 |
| 1215 | CMPGU_EQ_QB_MM = 1200, // MicroMipsDSPInstrInfo.td:525 |
| 1216 | CMPGU_LE_QB = 1201, // MipsDSPInstrInfo.td:1201 |
| 1217 | CMPGU_LE_QB_MM = 1202, // MicroMipsDSPInstrInfo.td:527 |
| 1218 | CMPGU_LT_QB = 1203, // MipsDSPInstrInfo.td:1200 |
| 1219 | CMPGU_LT_QB_MM = 1204, // MicroMipsDSPInstrInfo.td:526 |
| 1220 | CMPU_EQ_QB = 1205, // MipsDSPInstrInfo.td:1196 |
| 1221 | CMPU_EQ_QB_MM = 1206, // MicroMipsDSPInstrInfo.td:528 |
| 1222 | CMPU_LE_QB = 1207, // MipsDSPInstrInfo.td:1198 |
| 1223 | CMPU_LE_QB_MM = 1208, // MicroMipsDSPInstrInfo.td:530 |
| 1224 | CMPU_LT_QB = 1209, // MipsDSPInstrInfo.td:1197 |
| 1225 | CMPU_LT_QB_MM = 1210, // MicroMipsDSPInstrInfo.td:529 |
| 1226 | CMP_AF_D_MMR6 = 1211, // MicroMips32r6InstrInfo.td:949 |
| 1227 | CMP_AF_S_MMR6 = 1212, // MicroMips32r6InstrInfo.td:949 |
| 1228 | CMP_EQ_D = 1213, // Mips32r6InstrInfo.td:239 |
| 1229 | CMP_EQ_D_MMR6 = 1214, // MicroMips32r6InstrInfo.td:957 |
| 1230 | CMP_EQ_PH = 1215, // MipsDSPInstrInfo.td:1202 |
| 1231 | CMP_EQ_PH_MM = 1216, // MicroMipsDSPInstrInfo.td:522 |
| 1232 | CMP_EQ_S = 1217, // Mips32r6InstrInfo.td:239 |
| 1233 | CMP_EQ_S_MMR6 = 1218, // MicroMips32r6InstrInfo.td:957 |
| 1234 | CMP_F_D = 1219, // Mips32r6InstrInfo.td:231 |
| 1235 | CMP_F_S = 1220, // Mips32r6InstrInfo.td:231 |
| 1236 | CMP_LE_D = 1221, // Mips32r6InstrInfo.td:261 |
| 1237 | CMP_LE_D_MMR6 = 1222, // MicroMips32r6InstrInfo.td:973 |
| 1238 | CMP_LE_PH = 1223, // MipsDSPInstrInfo.td:1204 |
| 1239 | CMP_LE_PH_MM = 1224, // MicroMipsDSPInstrInfo.td:524 |
| 1240 | CMP_LE_S = 1225, // Mips32r6InstrInfo.td:261 |
| 1241 | CMP_LE_S_MMR6 = 1226, // MicroMips32r6InstrInfo.td:973 |
| 1242 | CMP_LT_D = 1227, // Mips32r6InstrInfo.td:250 |
| 1243 | CMP_LT_D_MMR6 = 1228, // MicroMips32r6InstrInfo.td:965 |
| 1244 | CMP_LT_PH = 1229, // MipsDSPInstrInfo.td:1203 |
| 1245 | CMP_LT_PH_MM = 1230, // MicroMipsDSPInstrInfo.td:523 |
| 1246 | CMP_LT_S = 1231, // Mips32r6InstrInfo.td:250 |
| 1247 | CMP_LT_S_MMR6 = 1232, // MicroMips32r6InstrInfo.td:965 |
| 1248 | CMP_SAF_D = 1233, // Mips32r6InstrInfo.td:273 |
| 1249 | CMP_SAF_D_MMR6 = 1234, // MicroMips32r6InstrInfo.td:983 |
| 1250 | CMP_SAF_S = 1235, // Mips32r6InstrInfo.td:273 |
| 1251 | CMP_SAF_S_MMR6 = 1236, // MicroMips32r6InstrInfo.td:983 |
| 1252 | CMP_SEQ_D = 1237, // Mips32r6InstrInfo.td:283 |
| 1253 | CMP_SEQ_D_MMR6 = 1238, // MicroMips32r6InstrInfo.td:991 |
| 1254 | CMP_SEQ_S = 1239, // Mips32r6InstrInfo.td:283 |
| 1255 | CMP_SEQ_S_MMR6 = 1240, // MicroMips32r6InstrInfo.td:991 |
| 1256 | CMP_SLE_D = 1241, // Mips32r6InstrInfo.td:303 |
| 1257 | CMP_SLE_D_MMR6 = 1242, // MicroMips32r6InstrInfo.td:1007 |
| 1258 | CMP_SLE_S = 1243, // Mips32r6InstrInfo.td:303 |
| 1259 | CMP_SLE_S_MMR6 = 1244, // MicroMips32r6InstrInfo.td:1007 |
| 1260 | CMP_SLT_D = 1245, // Mips32r6InstrInfo.td:293 |
| 1261 | CMP_SLT_D_MMR6 = 1246, // MicroMips32r6InstrInfo.td:999 |
| 1262 | CMP_SLT_S = 1247, // Mips32r6InstrInfo.td:293 |
| 1263 | CMP_SLT_S_MMR6 = 1248, // MicroMips32r6InstrInfo.td:999 |
| 1264 | CMP_SUEQ_D = 1249, // Mips32r6InstrInfo.td:288 |
| 1265 | CMP_SUEQ_D_MMR6 = 1250, // MicroMips32r6InstrInfo.td:995 |
| 1266 | CMP_SUEQ_S = 1251, // Mips32r6InstrInfo.td:288 |
| 1267 | CMP_SUEQ_S_MMR6 = 1252, // MicroMips32r6InstrInfo.td:995 |
| 1268 | CMP_SULE_D = 1253, // Mips32r6InstrInfo.td:308 |
| 1269 | CMP_SULE_D_MMR6 = 1254, // MicroMips32r6InstrInfo.td:1011 |
| 1270 | CMP_SULE_S = 1255, // Mips32r6InstrInfo.td:308 |
| 1271 | CMP_SULE_S_MMR6 = 1256, // MicroMips32r6InstrInfo.td:1011 |
| 1272 | CMP_SULT_D = 1257, // Mips32r6InstrInfo.td:298 |
| 1273 | CMP_SULT_D_MMR6 = 1258, // MicroMips32r6InstrInfo.td:1003 |
| 1274 | CMP_SULT_S = 1259, // Mips32r6InstrInfo.td:298 |
| 1275 | CMP_SULT_S_MMR6 = 1260, // MicroMips32r6InstrInfo.td:1003 |
| 1276 | CMP_SUN_D = 1261, // Mips32r6InstrInfo.td:278 |
| 1277 | CMP_SUN_D_MMR6 = 1262, // MicroMips32r6InstrInfo.td:987 |
| 1278 | CMP_SUN_S = 1263, // Mips32r6InstrInfo.td:278 |
| 1279 | CMP_SUN_S_MMR6 = 1264, // MicroMips32r6InstrInfo.td:987 |
| 1280 | CMP_UEQ_D = 1265, // Mips32r6InstrInfo.td:244 |
| 1281 | CMP_UEQ_D_MMR6 = 1266, // MicroMips32r6InstrInfo.td:961 |
| 1282 | CMP_UEQ_S = 1267, // Mips32r6InstrInfo.td:244 |
| 1283 | CMP_UEQ_S_MMR6 = 1268, // MicroMips32r6InstrInfo.td:961 |
| 1284 | CMP_ULE_D = 1269, // Mips32r6InstrInfo.td:266 |
| 1285 | CMP_ULE_D_MMR6 = 1270, // MicroMips32r6InstrInfo.td:977 |
| 1286 | CMP_ULE_S = 1271, // Mips32r6InstrInfo.td:266 |
| 1287 | CMP_ULE_S_MMR6 = 1272, // MicroMips32r6InstrInfo.td:977 |
| 1288 | CMP_ULT_D = 1273, // Mips32r6InstrInfo.td:255 |
| 1289 | CMP_ULT_D_MMR6 = 1274, // MicroMips32r6InstrInfo.td:969 |
| 1290 | CMP_ULT_S = 1275, // Mips32r6InstrInfo.td:255 |
| 1291 | CMP_ULT_S_MMR6 = 1276, // MicroMips32r6InstrInfo.td:969 |
| 1292 | CMP_UN_D = 1277, // Mips32r6InstrInfo.td:235 |
| 1293 | CMP_UN_D_MMR6 = 1278, // MicroMips32r6InstrInfo.td:953 |
| 1294 | CMP_UN_S = 1279, // Mips32r6InstrInfo.td:235 |
| 1295 | CMP_UN_S_MMR6 = 1280, // MicroMips32r6InstrInfo.td:953 |
| 1296 | COPY_S_B = 1281, // MipsMSAInstrInfo.td:2916 |
| 1297 | COPY_S_D = 1282, // MipsMSAInstrInfo.td:2919 |
| 1298 | COPY_S_H = 1283, // MipsMSAInstrInfo.td:2917 |
| 1299 | COPY_S_W = 1284, // MipsMSAInstrInfo.td:2918 |
| 1300 | COPY_U_B = 1285, // MipsMSAInstrInfo.td:2921 |
| 1301 | COPY_U_H = 1286, // MipsMSAInstrInfo.td:2922 |
| 1302 | COPY_U_W = 1287, // MipsMSAInstrInfo.td:2923 |
| 1303 | CRC32B = 1288, // Mips32r6InstrInfo.td:992 |
| 1304 | CRC32CB = 1289, // Mips32r6InstrInfo.td:995 |
| 1305 | CRC32CD = 1290, // Mips64r6InstrInfo.td:188 |
| 1306 | CRC32CH = 1291, // Mips32r6InstrInfo.td:996 |
| 1307 | CRC32CW = 1292, // Mips32r6InstrInfo.td:997 |
| 1308 | CRC32D = 1293, // Mips64r6InstrInfo.td:187 |
| 1309 | CRC32H = 1294, // Mips32r6InstrInfo.td:993 |
| 1310 | CRC32W = 1295, // Mips32r6InstrInfo.td:994 |
| 1311 | CTC1 = 1296, // MipsInstrFPU.td:577 |
| 1312 | CTC1_MM = 1297, // MicroMipsInstrFPU.td:262 |
| 1313 | CTC2_MM = 1298, // MicroMipsInstrInfo.td:701 |
| 1314 | CTCMSA = 1299, // MipsMSAInstrInfo.td:2928 |
| 1315 | CVT_D32_S = 1300, // MipsInstrFPU.td:470 |
| 1316 | CVT_D32_S_MM = 1301, // MicroMipsInstrFPU.td:145 |
| 1317 | CVT_D32_W = 1302, // MipsInstrFPU.td:472 |
| 1318 | CVT_D32_W_MM = 1303, // MicroMipsInstrFPU.td:147 |
| 1319 | CVT_D64_L = 1304, // MipsInstrFPU.td:537 |
| 1320 | CVT_D64_S = 1305, // MipsInstrFPU.td:535 |
| 1321 | CVT_D64_S_MM = 1306, // MicroMipsInstrFPU.td:152 |
| 1322 | CVT_D64_W = 1307, // MipsInstrFPU.td:533 |
| 1323 | CVT_D64_W_MM = 1308, // MicroMipsInstrFPU.td:154 |
| 1324 | CVT_D_L_MMR6 = 1309, // MicroMips32r6InstrInfo.td:1508 |
| 1325 | CVT_L_D64 = 1310, // MipsInstrFPU.td:463 |
| 1326 | CVT_L_D64_MM = 1311, // MicroMipsInstrFPU.td:104 |
| 1327 | CVT_L_D_MMR6 = 1312, // MicroMips32r6InstrInfo.td:1504 |
| 1328 | CVT_L_S = 1313, // MipsInstrFPU.td:461 |
| 1329 | CVT_L_S_MM = 1314, // MicroMipsInstrFPU.td:102 |
| 1330 | CVT_L_S_MMR6 = 1315, // MicroMips32r6InstrInfo.td:1502 |
| 1331 | CVT_PS_PW64 = 1316, // MipsInstrFPU.td:518 |
| 1332 | CVT_PS_S64 = 1317, // MipsInstrFPU.td:487 |
| 1333 | CVT_PW_PS64 = 1318, // MipsInstrFPU.td:521 |
| 1334 | CVT_S_D32 = 1319, // MipsInstrFPU.td:468 |
| 1335 | CVT_S_D32_MM = 1320, // MicroMipsInstrFPU.td:161 |
| 1336 | CVT_S_D64 = 1321, // MipsInstrFPU.td:531 |
| 1337 | CVT_S_D64_MM = 1322, // MicroMipsInstrFPU.td:156 |
| 1338 | CVT_S_L = 1323, // MipsInstrFPU.td:529 |
| 1339 | CVT_S_L_MMR6 = 1324, // MicroMips32r6InstrInfo.td:1512 |
| 1340 | CVT_S_PL64 = 1325, // MipsInstrFPU.td:507 |
| 1341 | CVT_S_PU64 = 1326, // MipsInstrFPU.td:504 |
| 1342 | CVT_S_W = 1327, // MipsInstrFPU.td:459 |
| 1343 | CVT_S_W_MM = 1328, // MicroMipsInstrFPU.td:163 |
| 1344 | CVT_S_W_MMR6 = 1329, // MicroMips32r6InstrInfo.td:1510 |
| 1345 | CVT_W_D32 = 1330, // MipsInstrFPU.td:166 |
| 1346 | CVT_W_D32_MM = 1331, // MicroMipsInstrFPU.td:107 |
| 1347 | CVT_W_D64 = 1332, // MipsInstrFPU.td:167 |
| 1348 | CVT_W_D64_MM = 1333, // MicroMipsInstrFPU.td:112 |
| 1349 | CVT_W_S = 1334, // MipsInstrFPU.td:408 |
| 1350 | CVT_W_S_MM = 1335, // MicroMipsInstrFPU.td:82 |
| 1351 | CVT_W_S_MMR6 = 1336, // MicroMips32r6InstrInfo.td:1506 |
| 1352 | C_EQ_D32 = 1337, // MipsInstrFPU.td:305 |
| 1353 | C_EQ_D32_MM = 1338, // MicroMipsInstrFPU.td:332 |
| 1354 | C_EQ_D64 = 1339, // MipsInstrFPU.td:305 |
| 1355 | C_EQ_D64_MM = 1340, // MicroMipsInstrFPU.td:332 |
| 1356 | C_EQ_S = 1341, // MipsInstrFPU.td:305 |
| 1357 | C_EQ_S_MM = 1342, // MicroMipsInstrFPU.td:332 |
| 1358 | C_F_D32 = 1343, // MipsInstrFPU.td:295 |
| 1359 | C_F_D32_MM = 1344, // MicroMipsInstrFPU.td:322 |
| 1360 | C_F_D64 = 1345, // MipsInstrFPU.td:295 |
| 1361 | C_F_D64_MM = 1346, // MicroMipsInstrFPU.td:322 |
| 1362 | C_F_S = 1347, // MipsInstrFPU.td:295 |
| 1363 | C_F_S_MM = 1348, // MicroMipsInstrFPU.td:322 |
| 1364 | C_LE_D32 = 1349, // MipsInstrFPU.td:364 |
| 1365 | C_LE_D32_MM = 1350, // MicroMipsInstrFPU.td:385 |
| 1366 | C_LE_D64 = 1351, // MipsInstrFPU.td:364 |
| 1367 | C_LE_D64_MM = 1352, // MicroMipsInstrFPU.td:385 |
| 1368 | C_LE_S = 1353, // MipsInstrFPU.td:364 |
| 1369 | C_LE_S_MM = 1354, // MicroMipsInstrFPU.td:385 |
| 1370 | C_LT_D32 = 1355, // MipsInstrFPU.td:354 |
| 1371 | C_LT_D32_MM = 1356, // MicroMipsInstrFPU.td:377 |
| 1372 | C_LT_D64 = 1357, // MipsInstrFPU.td:354 |
| 1373 | C_LT_D64_MM = 1358, // MicroMipsInstrFPU.td:377 |
| 1374 | C_LT_S = 1359, // MipsInstrFPU.td:354 |
| 1375 | C_LT_S_MM = 1360, // MicroMipsInstrFPU.td:377 |
| 1376 | C_NGE_D32 = 1361, // MipsInstrFPU.td:359 |
| 1377 | C_NGE_D32_MM = 1362, // MicroMipsInstrFPU.td:381 |
| 1378 | C_NGE_D64 = 1363, // MipsInstrFPU.td:359 |
| 1379 | C_NGE_D64_MM = 1364, // MicroMipsInstrFPU.td:381 |
| 1380 | C_NGE_S = 1365, // MipsInstrFPU.td:359 |
| 1381 | C_NGE_S_MM = 1366, // MicroMipsInstrFPU.td:381 |
| 1382 | C_NGLE_D32 = 1367, // MipsInstrFPU.td:338 |
| 1383 | C_NGLE_D32_MM = 1368, // MicroMipsInstrFPU.td:364 |
| 1384 | C_NGLE_D64 = 1369, // MipsInstrFPU.td:338 |
| 1385 | C_NGLE_D64_MM = 1370, // MicroMipsInstrFPU.td:364 |
| 1386 | C_NGLE_S = 1371, // MipsInstrFPU.td:338 |
| 1387 | C_NGLE_S_MM = 1372, // MicroMipsInstrFPU.td:364 |
| 1388 | C_NGL_D32 = 1373, // MipsInstrFPU.td:349 |
| 1389 | C_NGL_D32_MM = 1374, // MicroMipsInstrFPU.td:373 |
| 1390 | C_NGL_D64 = 1375, // MipsInstrFPU.td:349 |
| 1391 | C_NGL_D64_MM = 1376, // MicroMipsInstrFPU.td:373 |
| 1392 | C_NGL_S = 1377, // MipsInstrFPU.td:349 |
| 1393 | C_NGL_S_MM = 1378, // MicroMipsInstrFPU.td:373 |
| 1394 | C_NGT_D32 = 1379, // MipsInstrFPU.td:369 |
| 1395 | C_NGT_D32_MM = 1380, // MicroMipsInstrFPU.td:389 |
| 1396 | C_NGT_D64 = 1381, // MipsInstrFPU.td:369 |
| 1397 | C_NGT_D64_MM = 1382, // MicroMipsInstrFPU.td:389 |
| 1398 | C_NGT_S = 1383, // MipsInstrFPU.td:369 |
| 1399 | C_NGT_S_MM = 1384, // MicroMipsInstrFPU.td:389 |
| 1400 | C_OLE_D32 = 1385, // MipsInstrFPU.td:323 |
| 1401 | C_OLE_D32_MM = 1386, // MicroMipsInstrFPU.td:350 |
| 1402 | C_OLE_D64 = 1387, // MipsInstrFPU.td:323 |
| 1403 | C_OLE_D64_MM = 1388, // MicroMipsInstrFPU.td:350 |
| 1404 | C_OLE_S = 1389, // MipsInstrFPU.td:323 |
| 1405 | C_OLE_S_MM = 1390, // MicroMipsInstrFPU.td:350 |
| 1406 | C_OLT_D32 = 1391, // MipsInstrFPU.td:315 |
| 1407 | C_OLT_D32_MM = 1392, // MicroMipsInstrFPU.td:342 |
| 1408 | C_OLT_D64 = 1393, // MipsInstrFPU.td:315 |
| 1409 | C_OLT_D64_MM = 1394, // MicroMipsInstrFPU.td:342 |
| 1410 | C_OLT_S = 1395, // MipsInstrFPU.td:315 |
| 1411 | C_OLT_S_MM = 1396, // MicroMipsInstrFPU.td:342 |
| 1412 | C_SEQ_D32 = 1397, // MipsInstrFPU.td:343 |
| 1413 | C_SEQ_D32_MM = 1398, // MicroMipsInstrFPU.td:368 |
| 1414 | C_SEQ_D64 = 1399, // MipsInstrFPU.td:343 |
| 1415 | C_SEQ_D64_MM = 1400, // MicroMipsInstrFPU.td:368 |
| 1416 | C_SEQ_S = 1401, // MipsInstrFPU.td:343 |
| 1417 | C_SEQ_S_MM = 1402, // MicroMipsInstrFPU.td:368 |
| 1418 | C_SF_D32 = 1403, // MipsInstrFPU.td:332 |
| 1419 | C_SF_D32_MM = 1404, // MicroMipsInstrFPU.td:359 |
| 1420 | C_SF_D64 = 1405, // MipsInstrFPU.td:332 |
| 1421 | C_SF_D64_MM = 1406, // MicroMipsInstrFPU.td:359 |
| 1422 | C_SF_S = 1407, // MipsInstrFPU.td:332 |
| 1423 | C_SF_S_MM = 1408, // MicroMipsInstrFPU.td:359 |
| 1424 | C_UEQ_D32 = 1409, // MipsInstrFPU.td:310 |
| 1425 | C_UEQ_D32_MM = 1410, // MicroMipsInstrFPU.td:337 |
| 1426 | C_UEQ_D64 = 1411, // MipsInstrFPU.td:310 |
| 1427 | C_UEQ_D64_MM = 1412, // MicroMipsInstrFPU.td:337 |
| 1428 | C_UEQ_S = 1413, // MipsInstrFPU.td:310 |
| 1429 | C_UEQ_S_MM = 1414, // MicroMipsInstrFPU.td:337 |
| 1430 | C_ULE_D32 = 1415, // MipsInstrFPU.td:327 |
| 1431 | C_ULE_D32_MM = 1416, // MicroMipsInstrFPU.td:354 |
| 1432 | C_ULE_D64 = 1417, // MipsInstrFPU.td:327 |
| 1433 | C_ULE_D64_MM = 1418, // MicroMipsInstrFPU.td:354 |
| 1434 | C_ULE_S = 1419, // MipsInstrFPU.td:327 |
| 1435 | C_ULE_S_MM = 1420, // MicroMipsInstrFPU.td:354 |
| 1436 | C_ULT_D32 = 1421, // MipsInstrFPU.td:319 |
| 1437 | C_ULT_D32_MM = 1422, // MicroMipsInstrFPU.td:346 |
| 1438 | C_ULT_D64 = 1423, // MipsInstrFPU.td:319 |
| 1439 | C_ULT_D64_MM = 1424, // MicroMipsInstrFPU.td:346 |
| 1440 | C_ULT_S = 1425, // MipsInstrFPU.td:319 |
| 1441 | C_ULT_S_MM = 1426, // MicroMipsInstrFPU.td:346 |
| 1442 | C_UN_D32 = 1427, // MipsInstrFPU.td:300 |
| 1443 | C_UN_D32_MM = 1428, // MicroMipsInstrFPU.td:327 |
| 1444 | C_UN_D64 = 1429, // MipsInstrFPU.td:300 |
| 1445 | C_UN_D64_MM = 1430, // MicroMipsInstrFPU.td:327 |
| 1446 | C_UN_S = 1431, // MipsInstrFPU.td:300 |
| 1447 | C_UN_S_MM = 1432, // MicroMipsInstrFPU.td:327 |
| 1448 | CmpRxRy16 = 1433, // Mips16InstrInfo.td:695 |
| 1449 | CmpiRxImm16 = 1434, // Mips16InstrInfo.td:704 |
| 1450 | CmpiRxImmX16 = 1435, // Mips16InstrInfo.td:713 |
| 1451 | DADD = 1436, // Mips64InstrInfo.td:143 |
| 1452 | DADDi = 1437, // Mips64InstrInfo.td:119 |
| 1453 | DADDiu = 1438, // Mips64InstrInfo.td:122 |
| 1454 | DADDu = 1439, // Mips64InstrInfo.td:145 |
| 1455 | DAHI = 1440, // Mips64r6InstrInfo.td:134 |
| 1456 | DALIGN = 1441, // Mips64r6InstrInfo.td:137 |
| 1457 | DATI = 1442, // Mips64r6InstrInfo.td:133 |
| 1458 | DAUI = 1443, // Mips64r6InstrInfo.td:136 |
| 1459 | DBITSWAP = 1444, // Mips64r6InstrInfo.td:138 |
| 1460 | DCLO = 1445, // Mips64InstrInfo.td:366 |
| 1461 | DCLO_R6 = 1446, // Mips64r6InstrInfo.td:139 |
| 1462 | DCLZ = 1447, // Mips64InstrInfo.td:364 |
| 1463 | DCLZ_R6 = 1448, // Mips64r6InstrInfo.td:140 |
| 1464 | DDIV = 1449, // Mips64r6InstrInfo.td:141 |
| 1465 | DDIVU = 1450, // Mips64r6InstrInfo.td:142 |
| 1466 | DERET = 1451, // MipsInstrInfo.td:2259 |
| 1467 | DERET_MM = 1452, // MicroMipsInstrInfo.td:1013 |
| 1468 | DERET_MMR6 = 1453, // MicroMips32r6InstrInfo.td:1389 |
| 1469 | DEXT = 1454, // Mips64InstrInfo.td:390 |
| 1470 | DEXT64_32 = 1455, // Mips64InstrInfo.td:419 |
| 1471 | DEXTM = 1456, // Mips64InstrInfo.td:393 |
| 1472 | DEXTU = 1457, // Mips64InstrInfo.td:395 |
| 1473 | DI = 1458, // MipsInstrInfo.td:2263 |
| 1474 | DINS = 1459, // Mips64InstrInfo.td:406 |
| 1475 | DINSM = 1460, // Mips64InstrInfo.td:412 |
| 1476 | DINSU = 1461, // Mips64InstrInfo.td:409 |
| 1477 | DIV = 1462, // Mips32r6InstrInfo.td:920 |
| 1478 | DIVU = 1463, // Mips32r6InstrInfo.td:921 |
| 1479 | DIVU_MMR6 = 1464, // MicroMips32r6InstrInfo.td:1384 |
| 1480 | DIV_MMR6 = 1465, // MicroMips32r6InstrInfo.td:1383 |
| 1481 | DIV_S_B = 1466, // MipsMSAInstrInfo.td:2930 |
| 1482 | DIV_S_D = 1467, // MipsMSAInstrInfo.td:2933 |
| 1483 | DIV_S_H = 1468, // MipsMSAInstrInfo.td:2931 |
| 1484 | DIV_S_W = 1469, // MipsMSAInstrInfo.td:2932 |
| 1485 | DIV_U_B = 1470, // MipsMSAInstrInfo.td:2935 |
| 1486 | DIV_U_D = 1471, // MipsMSAInstrInfo.td:2938 |
| 1487 | DIV_U_H = 1472, // MipsMSAInstrInfo.td:2936 |
| 1488 | DIV_U_W = 1473, // MipsMSAInstrInfo.td:2937 |
| 1489 | DI_MM = 1474, // MicroMipsInstrInfo.td:1017 |
| 1490 | DI_MMR6 = 1475, // MicroMips32r6InstrInfo.td:1387 |
| 1491 | DLSA = 1476, // MipsMSAInstrInfo.td:3221 |
| 1492 | DLSA_R6 = 1477, // Mips64r6InstrInfo.td:145 |
| 1493 | DMFC0 = 1478, // Mips64InstrInfo.td:632 |
| 1494 | DMFC1 = 1479, // MipsInstrFPU.td:610 |
| 1495 | DMFC2 = 1480, // Mips64InstrInfo.td:636 |
| 1496 | DMFC2_OCTEON = 1481, // Mips64InstrInfo.td:604 |
| 1497 | DMFGC0 = 1482, // Mips64InstrInfo.td:644 |
| 1498 | DMOD = 1483, // Mips64r6InstrInfo.td:143 |
| 1499 | DMODU = 1484, // Mips64r6InstrInfo.td:144 |
| 1500 | DMT = 1485, // MipsMTInstrInfo.td:97 |
| 1501 | DMTC0 = 1486, // Mips64InstrInfo.td:634 |
| 1502 | DMTC1 = 1487, // MipsInstrFPU.td:608 |
| 1503 | DMTC2 = 1488, // Mips64InstrInfo.td:638 |
| 1504 | DMTC2_OCTEON = 1489, // Mips64InstrInfo.td:606 |
| 1505 | DMTGC0 = 1490, // Mips64InstrInfo.td:646 |
| 1506 | DMUH = 1491, // Mips64r6InstrInfo.td:146 |
| 1507 | DMUHU = 1492, // Mips64r6InstrInfo.td:147 |
| 1508 | DMUL = 1493, // Mips64InstrInfo.td:536 |
| 1509 | DMULT = 1494, // Mips64InstrInfo.td:313 |
| 1510 | DMULTu = 1495, // Mips64InstrInfo.td:316 |
| 1511 | DMULU = 1496, // Mips64r6InstrInfo.td:149 |
| 1512 | DMUL_R6 = 1497, // Mips64r6InstrInfo.td:148 |
| 1513 | DOTP_S_D = 1498, // MipsMSAInstrInfo.td:2942 |
| 1514 | DOTP_S_H = 1499, // MipsMSAInstrInfo.td:2940 |
| 1515 | DOTP_S_W = 1500, // MipsMSAInstrInfo.td:2941 |
| 1516 | DOTP_U_D = 1501, // MipsMSAInstrInfo.td:2946 |
| 1517 | DOTP_U_H = 1502, // MipsMSAInstrInfo.td:2944 |
| 1518 | DOTP_U_W = 1503, // MipsMSAInstrInfo.td:2945 |
| 1519 | DPADD_S_D = 1504, // MipsMSAInstrInfo.td:2950 |
| 1520 | DPADD_S_H = 1505, // MipsMSAInstrInfo.td:2948 |
| 1521 | DPADD_S_W = 1506, // MipsMSAInstrInfo.td:2949 |
| 1522 | DPADD_U_D = 1507, // MipsMSAInstrInfo.td:2954 |
| 1523 | DPADD_U_H = 1508, // MipsMSAInstrInfo.td:2952 |
| 1524 | DPADD_U_W = 1509, // MipsMSAInstrInfo.td:2953 |
| 1525 | DPAQX_SA_W_PH = 1510, // MipsDSPInstrInfo.td:1269 |
| 1526 | DPAQX_SA_W_PH_MMR2 = 1511, // MicroMipsDSPInstrInfo.td:545 |
| 1527 | DPAQX_S_W_PH = 1512, // MipsDSPInstrInfo.td:1268 |
| 1528 | DPAQX_S_W_PH_MMR2 = 1513, // MicroMipsDSPInstrInfo.td:543 |
| 1529 | DPAQ_SA_L_W = 1514, // MipsDSPInstrInfo.td:1188 |
| 1530 | DPAQ_SA_L_W_MM = 1515, // MicroMipsDSPInstrInfo.td:423 |
| 1531 | DPAQ_S_W_PH = 1516, // MipsDSPInstrInfo.td:1186 |
| 1532 | DPAQ_S_W_PH_MM = 1517, // MicroMipsDSPInstrInfo.td:422 |
| 1533 | DPAU_H_QBL = 1518, // MipsDSPInstrInfo.td:1182 |
| 1534 | DPAU_H_QBL_MM = 1519, // MicroMipsDSPInstrInfo.td:424 |
| 1535 | DPAU_H_QBR = 1520, // MipsDSPInstrInfo.td:1183 |
| 1536 | DPAU_H_QBR_MM = 1521, // MicroMipsDSPInstrInfo.td:425 |
| 1537 | DPAX_W_PH = 1522, // MipsDSPInstrInfo.td:1270 |
| 1538 | DPAX_W_PH_MMR2 = 1523, // MicroMipsDSPInstrInfo.td:547 |
| 1539 | DPA_W_PH = 1524, // MipsDSPInstrInfo.td:1266 |
| 1540 | DPA_W_PH_MMR2 = 1525, // MicroMipsDSPInstrInfo.td:542 |
| 1541 | DPOP = 1526, // Mips64InstrInfo.td:577 |
| 1542 | DPSQX_SA_W_PH = 1527, // MipsDSPInstrInfo.td:1273 |
| 1543 | DPSQX_SA_W_PH_MMR2 = 1528, // MicroMipsDSPInstrInfo.td:574 |
| 1544 | DPSQX_S_W_PH = 1529, // MipsDSPInstrInfo.td:1272 |
| 1545 | DPSQX_S_W_PH_MMR2 = 1530, // MicroMipsDSPInstrInfo.td:572 |
| 1546 | DPSQ_SA_L_W = 1531, // MipsDSPInstrInfo.td:1189 |
| 1547 | DPSQ_SA_L_W_MM = 1532, // MicroMipsDSPInstrInfo.td:481 |
| 1548 | DPSQ_S_W_PH = 1533, // MipsDSPInstrInfo.td:1187 |
| 1549 | DPSQ_S_W_PH_MM = 1534, // MicroMipsDSPInstrInfo.td:480 |
| 1550 | DPSUB_S_D = 1535, // MipsMSAInstrInfo.td:2958 |
| 1551 | DPSUB_S_H = 1536, // MipsMSAInstrInfo.td:2956 |
| 1552 | DPSUB_S_W = 1537, // MipsMSAInstrInfo.td:2957 |
| 1553 | DPSUB_U_D = 1538, // MipsMSAInstrInfo.td:2962 |
| 1554 | DPSUB_U_H = 1539, // MipsMSAInstrInfo.td:2960 |
| 1555 | DPSUB_U_W = 1540, // MipsMSAInstrInfo.td:2961 |
| 1556 | DPSU_H_QBL = 1541, // MipsDSPInstrInfo.td:1184 |
| 1557 | DPSU_H_QBL_MM = 1542, // MicroMipsDSPInstrInfo.td:482 |
| 1558 | DPSU_H_QBR = 1543, // MipsDSPInstrInfo.td:1185 |
| 1559 | DPSU_H_QBR_MM = 1544, // MicroMipsDSPInstrInfo.td:483 |
| 1560 | DPSX_W_PH = 1545, // MipsDSPInstrInfo.td:1271 |
| 1561 | DPSX_W_PH_MMR2 = 1546, // MicroMipsDSPInstrInfo.td:576 |
| 1562 | DPS_W_PH = 1547, // MipsDSPInstrInfo.td:1267 |
| 1563 | DPS_W_PH_MMR2 = 1548, // MicroMipsDSPInstrInfo.td:571 |
| 1564 | DROTR = 1549, // Mips64InstrInfo.td:190 |
| 1565 | DROTR32 = 1550, // Mips64InstrInfo.td:195 |
| 1566 | DROTRV = 1551, // Mips64InstrInfo.td:193 |
| 1567 | DSBH = 1552, // Mips64InstrInfo.td:370 |
| 1568 | DSDIV = 1553, // Mips64InstrInfo.td:326 |
| 1569 | DSHD = 1554, // Mips64InstrInfo.td:372 |
| 1570 | DSLL = 1555, // Mips64InstrInfo.td:167 |
| 1571 | DSLL32 = 1556, // Mips64InstrInfo.td:182 |
| 1572 | DSLL64_32 = 1557, // Mips64InstrInfo.td:427 |
| 1573 | DSLLV = 1558, // Mips64InstrInfo.td:176 |
| 1574 | DSRA = 1559, // Mips64InstrInfo.td:173 |
| 1575 | DSRA32 = 1560, // Mips64InstrInfo.td:186 |
| 1576 | DSRAV = 1561, // Mips64InstrInfo.td:178 |
| 1577 | DSRL = 1562, // Mips64InstrInfo.td:170 |
| 1578 | DSRL32 = 1563, // Mips64InstrInfo.td:184 |
| 1579 | DSRLV = 1564, // Mips64InstrInfo.td:180 |
| 1580 | DSUB = 1565, // Mips64InstrInfo.td:149 |
| 1581 | DSUBu = 1566, // Mips64InstrInfo.td:147 |
| 1582 | DUDIV = 1567, // Mips64InstrInfo.td:329 |
| 1583 | DVP = 1568, // Mips32r6InstrInfo.td:924 |
| 1584 | DVPE = 1569, // MipsMTInstrInfo.td:101 |
| 1585 | DVP_MMR6 = 1570, // MicroMips32r6InstrInfo.td:1618 |
| 1586 | DivRxRy16 = 1571, // Mips16InstrInfo.td:723 |
| 1587 | DivuRxRy16 = 1572, // Mips16InstrInfo.td:732 |
| 1588 | EHB = 1573, // MipsInstrInfo.td:2510 |
| 1589 | EHB_MM = 1574, // MicroMipsInstrInfo.td:1074 |
| 1590 | EHB_MMR6 = 1575, // MicroMips32r6InstrInfo.td:1385 |
| 1591 | EI = 1576, // MipsInstrInfo.td:2261 |
| 1592 | EI_MM = 1577, // MicroMipsInstrInfo.td:1015 |
| 1593 | EI_MMR6 = 1578, // MicroMips32r6InstrInfo.td:1386 |
| 1594 | EMT = 1579, // MipsMTInstrInfo.td:99 |
| 1595 | ERET = 1580, // MipsInstrInfo.td:2256 |
| 1596 | ERETNC = 1581, // MipsInstrInfo.td:2257 |
| 1597 | ERETNC_MMR6 = 1582, // MicroMips32r6InstrInfo.td:1390 |
| 1598 | ERET_MM = 1583, // MicroMipsInstrInfo.td:1011 |
| 1599 | ERET_MMR6 = 1584, // MicroMips32r6InstrInfo.td:1388 |
| 1600 | EVP = 1585, // Mips32r6InstrInfo.td:925 |
| 1601 | EVPE = 1586, // MipsMTInstrInfo.td:103 |
| 1602 | EVP_MMR6 = 1587, // MicroMips32r6InstrInfo.td:1619 |
| 1603 | EXT = 1588, // MipsInstrInfo.td:2485 |
| 1604 | EXTP = 1589, // MipsDSPInstrInfo.td:1220 |
| 1605 | EXTPDP = 1590, // MipsDSPInstrInfo.td:1222 |
| 1606 | EXTPDPV = 1591, // MipsDSPInstrInfo.td:1223 |
| 1607 | EXTPDPV_MM = 1592, // MicroMipsDSPInstrInfo.td:470 |
| 1608 | EXTPDP_MM = 1593, // MicroMipsDSPInstrInfo.td:469 |
| 1609 | EXTPV = 1594, // MipsDSPInstrInfo.td:1221 |
| 1610 | EXTPV_MM = 1595, // MicroMipsDSPInstrInfo.td:471 |
| 1611 | EXTP_MM = 1596, // MicroMipsDSPInstrInfo.td:468 |
| 1612 | EXTRV_RS_W = 1597, // MipsDSPInstrInfo.td:1229 |
| 1613 | EXTRV_RS_W_MM = 1598, // MicroMipsDSPInstrInfo.td:478 |
| 1614 | EXTRV_R_W = 1599, // MipsDSPInstrInfo.td:1227 |
| 1615 | EXTRV_R_W_MM = 1600, // MicroMipsDSPInstrInfo.td:477 |
| 1616 | EXTRV_S_H = 1601, // MipsDSPInstrInfo.td:1231 |
| 1617 | EXTRV_S_H_MM = 1602, // MicroMipsDSPInstrInfo.td:479 |
| 1618 | EXTRV_W = 1603, // MipsDSPInstrInfo.td:1225 |
| 1619 | EXTRV_W_MM = 1604, // MicroMipsDSPInstrInfo.td:476 |
| 1620 | EXTR_RS_W = 1605, // MipsDSPInstrInfo.td:1228 |
| 1621 | EXTR_RS_W_MM = 1606, // MicroMipsDSPInstrInfo.td:474 |
| 1622 | EXTR_R_W = 1607, // MipsDSPInstrInfo.td:1226 |
| 1623 | EXTR_R_W_MM = 1608, // MicroMipsDSPInstrInfo.td:473 |
| 1624 | EXTR_S_H = 1609, // MipsDSPInstrInfo.td:1230 |
| 1625 | EXTR_S_H_MM = 1610, // MicroMipsDSPInstrInfo.td:475 |
| 1626 | EXTR_W = 1611, // MipsDSPInstrInfo.td:1224 |
| 1627 | EXTR_W_MM = 1612, // MicroMipsDSPInstrInfo.td:472 |
| 1628 | EXTS = 1613, // Mips64InstrInfo.td:543 |
| 1629 | EXTS32 = 1614, // Mips64InstrInfo.td:545 |
| 1630 | EXT_MM = 1615, // MicroMipsInstrInfo.td:941 |
| 1631 | EXT_MMR6 = 1616, // MicroMips32r6InstrInfo.td:1579 |
| 1632 | FABS_D32 = 1617, // MipsInstrFPU.td:157 |
| 1633 | FABS_D32_MM = 1618, // MicroMipsInstrFPU.td:118 |
| 1634 | FABS_D64 = 1619, // MipsInstrFPU.td:159 |
| 1635 | FABS_D64_MM = 1620, // MicroMipsInstrFPU.td:122 |
| 1636 | FABS_S = 1621, // MipsInstrFPU.td:551 |
| 1637 | FABS_S_MM = 1622, // MicroMipsInstrFPU.td:133 |
| 1638 | FADD_D = 1623, // MipsMSAInstrInfo.td:2965 |
| 1639 | FADD_D32 = 1624, // MipsInstrFPU.td:131 |
| 1640 | FADD_D32_MM = 1625, // MicroMipsInstrFPU.td:15 |
| 1641 | FADD_D64 = 1626, // MipsInstrFPU.td:132 |
| 1642 | FADD_D64_MM = 1627, // MicroMipsInstrFPU.td:20 |
| 1643 | FADD_PS64 = 1628, // MipsInstrFPU.td:478 |
| 1644 | FADD_S = 1629, // MipsInstrFPU.td:686 |
| 1645 | FADD_S_MM = 1630, // MicroMipsInstrFPU.td:26 |
| 1646 | FADD_S_MMR6 = 1631, // MicroMips32r6InstrInfo.td:1462 |
| 1647 | FADD_W = 1632, // MipsMSAInstrInfo.td:2964 |
| 1648 | FCAF_D = 1633, // MipsMSAInstrInfo.td:2968 |
| 1649 | FCAF_W = 1634, // MipsMSAInstrInfo.td:2967 |
| 1650 | FCEQ_D = 1635, // MipsMSAInstrInfo.td:2971 |
| 1651 | FCEQ_W = 1636, // MipsMSAInstrInfo.td:2970 |
| 1652 | FCLASS_D = 1637, // MipsMSAInstrInfo.td:2980 |
| 1653 | FCLASS_W = 1638, // MipsMSAInstrInfo.td:2979 |
| 1654 | FCLE_D = 1639, // MipsMSAInstrInfo.td:2974 |
| 1655 | FCLE_W = 1640, // MipsMSAInstrInfo.td:2973 |
| 1656 | FCLT_D = 1641, // MipsMSAInstrInfo.td:2977 |
| 1657 | FCLT_W = 1642, // MipsMSAInstrInfo.td:2976 |
| 1658 | FCMP_D32 = 1643, // MipsInstrFPU.td:768 |
| 1659 | FCMP_D32_MM = 1644, // MicroMipsInstrFPU.td:65 |
| 1660 | FCMP_D64 = 1645, // MipsInstrFPU.td:777 |
| 1661 | FCMP_S32 = 1646, // MipsInstrFPU.td:760 |
| 1662 | FCMP_S32_MM = 1647, // MicroMipsInstrFPU.td:57 |
| 1663 | FCNE_D = 1648, // MipsMSAInstrInfo.td:2983 |
| 1664 | FCNE_W = 1649, // MipsMSAInstrInfo.td:2982 |
| 1665 | FCOR_D = 1650, // MipsMSAInstrInfo.td:2986 |
| 1666 | FCOR_W = 1651, // MipsMSAInstrInfo.td:2985 |
| 1667 | FCUEQ_D = 1652, // MipsMSAInstrInfo.td:2989 |
| 1668 | FCUEQ_W = 1653, // MipsMSAInstrInfo.td:2988 |
| 1669 | FCULE_D = 1654, // MipsMSAInstrInfo.td:2992 |
| 1670 | FCULE_W = 1655, // MipsMSAInstrInfo.td:2991 |
| 1671 | FCULT_D = 1656, // MipsMSAInstrInfo.td:2995 |
| 1672 | FCULT_W = 1657, // MipsMSAInstrInfo.td:2994 |
| 1673 | FCUNE_D = 1658, // MipsMSAInstrInfo.td:3001 |
| 1674 | FCUNE_W = 1659, // MipsMSAInstrInfo.td:3000 |
| 1675 | FCUN_D = 1660, // MipsMSAInstrInfo.td:2998 |
| 1676 | FCUN_W = 1661, // MipsMSAInstrInfo.td:2997 |
| 1677 | FDIV_D = 1662, // MipsMSAInstrInfo.td:3004 |
| 1678 | FDIV_D32 = 1663, // MipsInstrFPU.td:131 |
| 1679 | FDIV_D32_MM = 1664, // MicroMipsInstrFPU.td:15 |
| 1680 | FDIV_D64 = 1665, // MipsInstrFPU.td:132 |
| 1681 | FDIV_D64_MM = 1666, // MicroMipsInstrFPU.td:20 |
| 1682 | FDIV_S = 1667, // MipsInstrFPU.td:690 |
| 1683 | FDIV_S_MM = 1668, // MicroMipsInstrFPU.td:28 |
| 1684 | FDIV_S_MMR6 = 1669, // MicroMips32r6InstrInfo.td:1468 |
| 1685 | FDIV_W = 1670, // MipsMSAInstrInfo.td:3003 |
| 1686 | FEXDO_H = 1671, // MipsMSAInstrInfo.td:3006 |
| 1687 | FEXDO_W = 1672, // MipsMSAInstrInfo.td:3007 |
| 1688 | FEXP2_D = 1673, // MipsMSAInstrInfo.td:3010 |
| 1689 | FEXP2_W = 1674, // MipsMSAInstrInfo.td:3009 |
| 1690 | FEXUPL_D = 1675, // MipsMSAInstrInfo.td:3015 |
| 1691 | FEXUPL_W = 1676, // MipsMSAInstrInfo.td:3014 |
| 1692 | FEXUPR_D = 1677, // MipsMSAInstrInfo.td:3018 |
| 1693 | FEXUPR_W = 1678, // MipsMSAInstrInfo.td:3017 |
| 1694 | FFINT_S_D = 1679, // MipsMSAInstrInfo.td:3021 |
| 1695 | FFINT_S_W = 1680, // MipsMSAInstrInfo.td:3020 |
| 1696 | FFINT_U_D = 1681, // MipsMSAInstrInfo.td:3024 |
| 1697 | FFINT_U_W = 1682, // MipsMSAInstrInfo.td:3023 |
| 1698 | FFQL_D = 1683, // MipsMSAInstrInfo.td:3027 |
| 1699 | FFQL_W = 1684, // MipsMSAInstrInfo.td:3026 |
| 1700 | FFQR_D = 1685, // MipsMSAInstrInfo.td:3030 |
| 1701 | FFQR_W = 1686, // MipsMSAInstrInfo.td:3029 |
| 1702 | FILL_B = 1687, // MipsMSAInstrInfo.td:3032 |
| 1703 | FILL_D = 1688, // MipsMSAInstrInfo.td:3035 |
| 1704 | FILL_H = 1689, // MipsMSAInstrInfo.td:3033 |
| 1705 | FILL_W = 1690, // MipsMSAInstrInfo.td:3034 |
| 1706 | FLOG2_D = 1691, // MipsMSAInstrInfo.td:3040 |
| 1707 | FLOG2_W = 1692, // MipsMSAInstrInfo.td:3039 |
| 1708 | FLOOR_L_D64 = 1693, // MipsInstrFPU.td:453 |
| 1709 | FLOOR_L_D_MMR6 = 1694, // MicroMips32r6InstrInfo.td:1522 |
| 1710 | FLOOR_L_S = 1695, // MipsInstrFPU.td:451 |
| 1711 | FLOOR_L_S_MMR6 = 1696, // MicroMips32r6InstrInfo.td:1520 |
| 1712 | FLOOR_W_D32 = 1697, // MipsInstrFPU.td:166 |
| 1713 | FLOOR_W_D64 = 1698, // MipsInstrFPU.td:167 |
| 1714 | FLOOR_W_D_MMR6 = 1699, // MicroMips32r6InstrInfo.td:1526 |
| 1715 | FLOOR_W_MM = 1700, // MicroMipsInstrFPU.td:93 |
| 1716 | FLOOR_W_S = 1701, // MipsInstrFPU.td:399 |
| 1717 | FLOOR_W_S_MM = 1702, // MicroMipsInstrFPU.td:229 |
| 1718 | FLOOR_W_S_MMR6 = 1703, // MicroMips32r6InstrInfo.td:1524 |
| 1719 | FMADD_D = 1704, // MipsMSAInstrInfo.td:3043 |
| 1720 | FMADD_W = 1705, // MipsMSAInstrInfo.td:3042 |
| 1721 | FMAX_A_D = 1706, // MipsMSAInstrInfo.td:3049 |
| 1722 | FMAX_A_W = 1707, // MipsMSAInstrInfo.td:3048 |
| 1723 | FMAX_D = 1708, // MipsMSAInstrInfo.td:3046 |
| 1724 | FMAX_W = 1709, // MipsMSAInstrInfo.td:3045 |
| 1725 | FMIN_A_D = 1710, // MipsMSAInstrInfo.td:3055 |
| 1726 | FMIN_A_W = 1711, // MipsMSAInstrInfo.td:3054 |
| 1727 | FMIN_D = 1712, // MipsMSAInstrInfo.td:3052 |
| 1728 | FMIN_W = 1713, // MipsMSAInstrInfo.td:3051 |
| 1729 | FMOV_D32 = 1714, // MipsInstrFPU.td:157 |
| 1730 | FMOV_D32_MM = 1715, // MicroMipsInstrFPU.td:118 |
| 1731 | FMOV_D64 = 1716, // MipsInstrFPU.td:159 |
| 1732 | FMOV_D64_MM = 1717, // MicroMipsInstrFPU.td:122 |
| 1733 | FMOV_D_MMR6 = 1718, // MicroMips32r6InstrInfo.td:1482 |
| 1734 | FMOV_S = 1719, // MipsInstrFPU.td:613 |
| 1735 | FMOV_S_MM = 1720, // MicroMipsInstrFPU.td:137 |
| 1736 | FMOV_S_MMR6 = 1721, // MicroMips32r6InstrInfo.td:1480 |
| 1737 | FMSUB_D = 1722, // MipsMSAInstrInfo.td:3058 |
| 1738 | FMSUB_W = 1723, // MipsMSAInstrInfo.td:3057 |
| 1739 | FMUL_D = 1724, // MipsMSAInstrInfo.td:3061 |
| 1740 | FMUL_D32 = 1725, // MipsInstrFPU.td:131 |
| 1741 | FMUL_D32_MM = 1726, // MicroMipsInstrFPU.td:15 |
| 1742 | FMUL_D64 = 1727, // MipsInstrFPU.td:132 |
| 1743 | FMUL_D64_MM = 1728, // MicroMipsInstrFPU.td:20 |
| 1744 | FMUL_PS64 = 1729, // MipsInstrFPU.td:481 |
| 1745 | FMUL_S = 1730, // MipsInstrFPU.td:694 |
| 1746 | FMUL_S_MM = 1731, // MicroMipsInstrFPU.td:30 |
| 1747 | FMUL_S_MMR6 = 1732, // MicroMips32r6InstrInfo.td:1466 |
| 1748 | FMUL_W = 1733, // MipsMSAInstrInfo.td:3060 |
| 1749 | FNEG_D32 = 1734, // MipsInstrFPU.td:157 |
| 1750 | FNEG_D32_MM = 1735, // MicroMipsInstrFPU.td:118 |
| 1751 | FNEG_D64 = 1736, // MipsInstrFPU.td:159 |
| 1752 | FNEG_D64_MM = 1737, // MicroMipsInstrFPU.td:122 |
| 1753 | FNEG_S = 1738, // MipsInstrFPU.td:556 |
| 1754 | FNEG_S_MM = 1739, // MicroMipsInstrFPU.td:141 |
| 1755 | FNEG_S_MMR6 = 1740, // MicroMips32r6InstrInfo.td:1484 |
| 1756 | FORK = 1741, // MipsMTInstrInfo.td:105 |
| 1757 | FRCP_D = 1742, // MipsMSAInstrInfo.td:3067 |
| 1758 | FRCP_W = 1743, // MipsMSAInstrInfo.td:3066 |
| 1759 | FRINT_D = 1744, // MipsMSAInstrInfo.td:3064 |
| 1760 | FRINT_W = 1745, // MipsMSAInstrInfo.td:3063 |
| 1761 | FRSQRT_D = 1746, // MipsMSAInstrInfo.td:3070 |
| 1762 | FRSQRT_W = 1747, // MipsMSAInstrInfo.td:3069 |
| 1763 | FSAF_D = 1748, // MipsMSAInstrInfo.td:3073 |
| 1764 | FSAF_W = 1749, // MipsMSAInstrInfo.td:3072 |
| 1765 | FSEQ_D = 1750, // MipsMSAInstrInfo.td:3076 |
| 1766 | FSEQ_W = 1751, // MipsMSAInstrInfo.td:3075 |
| 1767 | FSLE_D = 1752, // MipsMSAInstrInfo.td:3079 |
| 1768 | FSLE_W = 1753, // MipsMSAInstrInfo.td:3078 |
| 1769 | FSLT_D = 1754, // MipsMSAInstrInfo.td:3082 |
| 1770 | FSLT_W = 1755, // MipsMSAInstrInfo.td:3081 |
| 1771 | FSNE_D = 1756, // MipsMSAInstrInfo.td:3085 |
| 1772 | FSNE_W = 1757, // MipsMSAInstrInfo.td:3084 |
| 1773 | FSOR_D = 1758, // MipsMSAInstrInfo.td:3088 |
| 1774 | FSOR_W = 1759, // MipsMSAInstrInfo.td:3087 |
| 1775 | FSQRT_D = 1760, // MipsMSAInstrInfo.td:3091 |
| 1776 | FSQRT_D32 = 1761, // MipsInstrFPU.td:157 |
| 1777 | FSQRT_D32_MM = 1762, // MicroMipsInstrFPU.td:118 |
| 1778 | FSQRT_D64 = 1763, // MipsInstrFPU.td:159 |
| 1779 | FSQRT_D64_MM = 1764, // MicroMipsInstrFPU.td:122 |
| 1780 | FSQRT_S = 1765, // MipsInstrFPU.td:563 |
| 1781 | FSQRT_S_MM = 1766, // MicroMipsInstrFPU.td:238 |
| 1782 | FSQRT_W = 1767, // MipsMSAInstrInfo.td:3090 |
| 1783 | FSUB_D = 1768, // MipsMSAInstrInfo.td:3094 |
| 1784 | FSUB_D32 = 1769, // MipsInstrFPU.td:131 |
| 1785 | FSUB_D32_MM = 1770, // MicroMipsInstrFPU.td:15 |
| 1786 | FSUB_D64 = 1771, // MipsInstrFPU.td:132 |
| 1787 | FSUB_D64_MM = 1772, // MicroMipsInstrFPU.td:20 |
| 1788 | FSUB_PS64 = 1773, // MipsInstrFPU.td:484 |
| 1789 | FSUB_S = 1774, // MipsInstrFPU.td:698 |
| 1790 | FSUB_S_MM = 1775, // MicroMipsInstrFPU.td:32 |
| 1791 | FSUB_S_MMR6 = 1776, // MicroMips32r6InstrInfo.td:1464 |
| 1792 | FSUB_W = 1777, // MipsMSAInstrInfo.td:3093 |
| 1793 | FSUEQ_D = 1778, // MipsMSAInstrInfo.td:3097 |
| 1794 | FSUEQ_W = 1779, // MipsMSAInstrInfo.td:3096 |
| 1795 | FSULE_D = 1780, // MipsMSAInstrInfo.td:3100 |
| 1796 | FSULE_W = 1781, // MipsMSAInstrInfo.td:3099 |
| 1797 | FSULT_D = 1782, // MipsMSAInstrInfo.td:3103 |
| 1798 | FSULT_W = 1783, // MipsMSAInstrInfo.td:3102 |
| 1799 | FSUNE_D = 1784, // MipsMSAInstrInfo.td:3109 |
| 1800 | FSUNE_W = 1785, // MipsMSAInstrInfo.td:3108 |
| 1801 | FSUN_D = 1786, // MipsMSAInstrInfo.td:3106 |
| 1802 | FSUN_W = 1787, // MipsMSAInstrInfo.td:3105 |
| 1803 | FTINT_S_D = 1788, // MipsMSAInstrInfo.td:3112 |
| 1804 | FTINT_S_W = 1789, // MipsMSAInstrInfo.td:3111 |
| 1805 | FTINT_U_D = 1790, // MipsMSAInstrInfo.td:3115 |
| 1806 | FTINT_U_W = 1791, // MipsMSAInstrInfo.td:3114 |
| 1807 | FTQ_H = 1792, // MipsMSAInstrInfo.td:3117 |
| 1808 | FTQ_W = 1793, // MipsMSAInstrInfo.td:3118 |
| 1809 | FTRUNC_S_D = 1794, // MipsMSAInstrInfo.td:3121 |
| 1810 | FTRUNC_S_W = 1795, // MipsMSAInstrInfo.td:3120 |
| 1811 | FTRUNC_U_D = 1796, // MipsMSAInstrInfo.td:3124 |
| 1812 | FTRUNC_U_W = 1797, // MipsMSAInstrInfo.td:3123 |
| 1813 | GINVI = 1798, // Mips32r6InstrInfo.td:1001 |
| 1814 | GINVI_MMR6 = 1799, // MicroMips32r6InstrInfo.td:1392 |
| 1815 | GINVT = 1800, // Mips32r6InstrInfo.td:1002 |
| 1816 | GINVT_MMR6 = 1801, // MicroMips32r6InstrInfo.td:1394 |
| 1817 | HADD_S_D = 1802, // MipsMSAInstrInfo.td:3142 |
| 1818 | HADD_S_H = 1803, // MipsMSAInstrInfo.td:3140 |
| 1819 | HADD_S_W = 1804, // MipsMSAInstrInfo.td:3141 |
| 1820 | HADD_U_D = 1805, // MipsMSAInstrInfo.td:3146 |
| 1821 | HADD_U_H = 1806, // MipsMSAInstrInfo.td:3144 |
| 1822 | HADD_U_W = 1807, // MipsMSAInstrInfo.td:3145 |
| 1823 | HSUB_S_D = 1808, // MipsMSAInstrInfo.td:3150 |
| 1824 | HSUB_S_H = 1809, // MipsMSAInstrInfo.td:3148 |
| 1825 | HSUB_S_W = 1810, // MipsMSAInstrInfo.td:3149 |
| 1826 | HSUB_U_D = 1811, // MipsMSAInstrInfo.td:3154 |
| 1827 | HSUB_U_H = 1812, // MipsMSAInstrInfo.td:3152 |
| 1828 | HSUB_U_W = 1813, // MipsMSAInstrInfo.td:3153 |
| 1829 | HYPCALL = 1814, // MipsInstrInfo.td:2718 |
| 1830 | HYPCALL_MM = 1815, // MicroMipsInstrInfo.td:1144 |
| 1831 | ILVEV_B = 1816, // MipsMSAInstrInfo.td:3156 |
| 1832 | ILVEV_D = 1817, // MipsMSAInstrInfo.td:3159 |
| 1833 | ILVEV_H = 1818, // MipsMSAInstrInfo.td:3157 |
| 1834 | ILVEV_W = 1819, // MipsMSAInstrInfo.td:3158 |
| 1835 | ILVL_B = 1820, // MipsMSAInstrInfo.td:3161 |
| 1836 | ILVL_D = 1821, // MipsMSAInstrInfo.td:3164 |
| 1837 | ILVL_H = 1822, // MipsMSAInstrInfo.td:3162 |
| 1838 | ILVL_W = 1823, // MipsMSAInstrInfo.td:3163 |
| 1839 | ILVOD_B = 1824, // MipsMSAInstrInfo.td:3166 |
| 1840 | ILVOD_D = 1825, // MipsMSAInstrInfo.td:3169 |
| 1841 | ILVOD_H = 1826, // MipsMSAInstrInfo.td:3167 |
| 1842 | ILVOD_W = 1827, // MipsMSAInstrInfo.td:3168 |
| 1843 | ILVR_B = 1828, // MipsMSAInstrInfo.td:3171 |
| 1844 | ILVR_D = 1829, // MipsMSAInstrInfo.td:3174 |
| 1845 | ILVR_H = 1830, // MipsMSAInstrInfo.td:3172 |
| 1846 | ILVR_W = 1831, // MipsMSAInstrInfo.td:3173 |
| 1847 | INS = 1832, // MipsInstrInfo.td:2488 |
| 1848 | INSERT_B = 1833, // MipsMSAInstrInfo.td:3176 |
| 1849 | INSERT_D = 1834, // MipsMSAInstrInfo.td:3179 |
| 1850 | INSERT_H = 1835, // MipsMSAInstrInfo.td:3177 |
| 1851 | INSERT_W = 1836, // MipsMSAInstrInfo.td:3178 |
| 1852 | INSV = 1837, // MipsDSPInstrInfo.td:1219 |
| 1853 | INSVE_B = 1838, // MipsMSAInstrInfo.td:3187 |
| 1854 | INSVE_D = 1839, // MipsMSAInstrInfo.td:3190 |
| 1855 | INSVE_H = 1840, // MipsMSAInstrInfo.td:3188 |
| 1856 | INSVE_W = 1841, // MipsMSAInstrInfo.td:3189 |
| 1857 | INSV_MM = 1842, // MicroMipsDSPInstrInfo.td:428 |
| 1858 | INS_MM = 1843, // MicroMipsInstrInfo.td:944 |
| 1859 | INS_MMR6 = 1844, // MicroMips32r6InstrInfo.td:1580 |
| 1860 | J = 1845, // MipsInstrInfo.td:2282 |
| 1861 | JAL = 1846, // MipsInstrInfo.td:2314 |
| 1862 | JALR = 1847, // MipsInstrInfo.td:2319 |
| 1863 | JALR16_MM = 1848, // MicroMipsInstrInfo.td:668 |
| 1864 | JALR64 = 1849, // Mips64InstrInfo.td:267 |
| 1865 | JALRC16_MMR6 = 1850, // MicroMips32r6InstrInfo.td:1397 |
| 1866 | JALRC_HB_MMR6 = 1851, // MicroMips32r6InstrInfo.td:1577 |
| 1867 | JALRC_MMR6 = 1852, // MicroMips32r6InstrInfo.td:1581 |
| 1868 | JALRS16_MM = 1853, // MicroMipsInstrInfo.td:670 |
| 1869 | JALRS_MM = 1854, // MicroMipsInstrInfo.td:969 |
| 1870 | JALR_HB = 1855, // MipsInstrInfo.td:2558 |
| 1871 | JALR_HB64 = 1856, // Mips64InstrInfo.td:290 |
| 1872 | JALR_MM = 1857, // MicroMipsInstrInfo.td:963 |
| 1873 | JALS_MM = 1858, // MicroMipsInstrInfo.td:967 |
| 1874 | JALX = 1859, // MipsInstrInfo.td:2324 |
| 1875 | JALX_MM = 1860, // MicroMipsInstrInfo.td:958 |
| 1876 | JAL_MM = 1861, // MicroMipsInstrInfo.td:953 |
| 1877 | JIALC = 1862, // Mips32r6InstrInfo.td:927 |
| 1878 | JIALC64 = 1863, // Mips64r6InstrInfo.td:168 |
| 1879 | JIALC_MMR6 = 1864, // MicroMips32r6InstrInfo.td:1399 |
| 1880 | JIC = 1865, // Mips32r6InstrInfo.td:928 |
| 1881 | JIC64 = 1866, // Mips64r6InstrInfo.td:169 |
| 1882 | JIC_MMR6 = 1867, // MicroMips32r6InstrInfo.td:1400 |
| 1883 | JR = 1868, // MipsInstrInfo.td:2286 |
| 1884 | JR16_MM = 1869, // MicroMipsInstrInfo.td:676 |
| 1885 | JR64 = 1870, // Mips64InstrInfo.td:264 |
| 1886 | JRADDIUSP = 1871, // MicroMipsInstrInfo.td:674 |
| 1887 | JRC16_MM = 1872, // MicroMipsInstrInfo.td:672 |
| 1888 | JRC16_MMR6 = 1873, // MicroMips32r6InstrInfo.td:1401 |
| 1889 | JRCADDIUSP_MMR6 = 1874, // MicroMips32r6InstrInfo.td:1402 |
| 1890 | JR_HB = 1875, // MipsInstrInfo.td:2557 |
| 1891 | JR_HB64 = 1876, // Mips64InstrInfo.td:289 |
| 1892 | JR_HB64_R6 = 1877, // Mips64r6InstrInfo.td:158 |
| 1893 | JR_HB_R6 = 1878, // Mips32r6InstrInfo.td:929 |
| 1894 | JR_MM = 1879, // MicroMipsInstrInfo.td:961 |
| 1895 | J_MM = 1880, // MicroMipsInstrInfo.td:950 |
| 1896 | Jal16 = 1881, // Mips16InstrInfo.td:742 |
| 1897 | JalB16 = 1882, // Mips16InstrInfo.td:748 |
| 1898 | JrRa16 = 1883, // Mips16InstrInfo.td:761 |
| 1899 | JrcRa16 = 1884, // Mips16InstrInfo.td:770 |
| 1900 | JrcRx16 = 1885, // Mips16InstrInfo.td:778 |
| 1901 | JumpLinkReg16 = 1886, // Mips16InstrInfo.td:1387 |
| 1902 | LB = 1887, // MipsInstrInfo.td:2156 |
| 1903 | LB64 = 1888, // Mips64InstrInfo.td:202 |
| 1904 | LBE = 1889, // MipsEVAInstrInfo.td:190 |
| 1905 | LBE_MM = 1890, // MicroMipsInstrInfo.td:816 |
| 1906 | LBU16_MM = 1891, // MicroMipsInstrInfo.td:629 |
| 1907 | LBUX = 1892, // MipsDSPInstrInfo.td:1215 |
| 1908 | LBUX_MM = 1893, // MicroMipsDSPInstrInfo.td:493 |
| 1909 | LBU_MMR6 = 1894, // MicroMips32r6InstrInfo.td:1443 |
| 1910 | LB_MM = 1895, // MicroMipsInstrInfo.td:797 |
| 1911 | LB_MMR6 = 1896, // MicroMips32r6InstrInfo.td:1442 |
| 1912 | LBu = 1897, // MipsInstrInfo.td:2158 |
| 1913 | LBu64 = 1898, // Mips64InstrInfo.td:203 |
| 1914 | LBuE = 1899, // MipsEVAInstrInfo.td:191 |
| 1915 | LBuE_MM = 1900, // MicroMipsInstrInfo.td:818 |
| 1916 | LBu_MM = 1901, // MicroMipsInstrInfo.td:799 |
| 1917 | LD = 1902, // Mips64InstrInfo.td:217 |
| 1918 | LDC1 = 1903, // MipsInstrFPU.td:637 |
| 1919 | LDC164 = 1904, // MipsInstrFPU.td:628 |
| 1920 | LDC1_D64_MMR6 = 1905, // MicroMips32r6InstrInfo.td:1629 |
| 1921 | LDC1_MM_D32 = 1906, // MicroMipsInstrFPU.td:294 |
| 1922 | LDC1_MM_D64 = 1907, // MicroMipsInstrFPU.td:309 |
| 1923 | LDC2 = 1908, // MipsInstrInfo.td:2190 |
| 1924 | LDC2_MMR6 = 1909, // MicroMips32r6InstrInfo.td:1636 |
| 1925 | LDC2_R6 = 1910, // Mips32r6InstrInfo.td:931 |
| 1926 | LDC3 = 1911, // MipsInstrInfo.td:2205 |
| 1927 | LDI_B = 1912, // MipsMSAInstrInfo.td:3215 |
| 1928 | LDI_D = 1913, // MipsMSAInstrInfo.td:3218 |
| 1929 | LDI_H = 1914, // MipsMSAInstrInfo.td:3216 |
| 1930 | LDI_W = 1915, // MipsMSAInstrInfo.td:3217 |
| 1931 | LDL = 1916, // Mips64InstrInfo.td:237 |
| 1932 | LDPC = 1917, // Mips64r6InstrInfo.td:152 |
| 1933 | LDR = 1918, // Mips64InstrInfo.td:239 |
| 1934 | LDXC1 = 1919, // MipsInstrFPU.td:654 |
| 1935 | LDXC164 = 1920, // MipsInstrFPU.td:661 |
| 1936 | LD_B = 1921, // MipsMSAInstrInfo.td:3210 |
| 1937 | LD_D = 1922, // MipsMSAInstrInfo.td:3213 |
| 1938 | LD_H = 1923, // MipsMSAInstrInfo.td:3211 |
| 1939 | LD_W = 1924, // MipsMSAInstrInfo.td:3212 |
| 1940 | LEA_ADDiu = 1925, // MipsInstrInfo.td:2446 |
| 1941 | LEA_ADDiu64 = 1926, // Mips64InstrInfo.td:375 |
| 1942 | LEA_ADDiu_MM = 1927, // MicroMipsInstrInfo.td:731 |
| 1943 | LH = 1928, // MipsInstrInfo.td:2160 |
| 1944 | LH64 = 1929, // Mips64InstrInfo.td:204 |
| 1945 | LHE = 1930, // MipsEVAInstrInfo.td:192 |
| 1946 | LHE_MM = 1931, // MicroMipsInstrInfo.td:820 |
| 1947 | LHU16_MM = 1932, // MicroMipsInstrInfo.td:631 |
| 1948 | LHX = 1933, // MipsDSPInstrInfo.td:1214 |
| 1949 | LHX_MM = 1934, // MicroMipsDSPInstrInfo.td:494 |
| 1950 | LH_MM = 1935, // MicroMipsInstrInfo.td:801 |
| 1951 | LHu = 1936, // MipsInstrInfo.td:2162 |
| 1952 | LHu64 = 1937, // Mips64InstrInfo.td:205 |
| 1953 | LHuE = 1938, // MipsEVAInstrInfo.td:193 |
| 1954 | LHuE_MM = 1939, // MicroMipsInstrInfo.td:823 |
| 1955 | LHu_MM = 1940, // MicroMipsInstrInfo.td:803 |
| 1956 | LI16_MM = 1941, // MicroMipsInstrInfo.td:666 |
| 1957 | LI16_MMR6 = 1942, // MicroMips32r6InstrInfo.td:1565 |
| 1958 | LL = 1943, // MipsInstrInfo.td:2271 |
| 1959 | LL64 = 1944, // Mips64InstrInfo.td:256 |
| 1960 | LL64_R6 = 1945, // Mips64r6InstrInfo.td:162 |
| 1961 | LLD = 1946, // Mips64InstrInfo.td:248 |
| 1962 | LLD_R6 = 1947, // Mips64r6InstrInfo.td:150 |
| 1963 | LLE = 1948, // MipsEVAInstrInfo.td:206 |
| 1964 | LLE_MM = 1949, // MicroMipsInstrInfo.td:1054 |
| 1965 | LL_MM = 1950, // MicroMipsInstrInfo.td:1049 |
| 1966 | LL_MMR6 = 1951, // MicroMips32r6InstrInfo.td:1640 |
| 1967 | LL_R6 = 1952, // Mips32r6InstrInfo.td:932 |
| 1968 | LSA = 1953, // MipsMSAInstrInfo.td:3220 |
| 1969 | LSA_MMR6 = 1954, // MicroMips32r6InstrInfo.td:1404 |
| 1970 | LSA_R6 = 1955, // Mips32r6InstrInfo.td:934 |
| 1971 | LUI_MMR6 = 1956, // MicroMips32r6InstrInfo.td:1548 |
| 1972 | LUXC1 = 1957, // MipsInstrFPU.td:670 |
| 1973 | LUXC164 = 1958, // MipsInstrFPU.td:678 |
| 1974 | LUXC1_MM = 1959, // MicroMipsInstrFPU.td:51 |
| 1975 | LUi = 1960, // MipsInstrInfo.td:2098 |
| 1976 | LUi64 = 1961, // Mips64InstrInfo.td:138 |
| 1977 | LUi_MM = 1962, // MicroMipsInstrInfo.td:728 |
| 1978 | LW = 1963, // MipsInstrInfo.td:2164 |
| 1979 | LW16_MM = 1964, // MicroMipsInstrInfo.td:633 |
| 1980 | LW64 = 1965, // Mips64InstrInfo.td:206 |
| 1981 | LWC1 = 1966, // MipsInstrFPU.td:621 |
| 1982 | LWC1_MM = 1967, // MicroMipsInstrFPU.td:302 |
| 1983 | LWC2 = 1968, // MipsInstrInfo.td:2186 |
| 1984 | LWC2_MMR6 = 1969, // MicroMips32r6InstrInfo.td:1638 |
| 1985 | LWC2_R6 = 1970, // Mips32r6InstrInfo.td:936 |
| 1986 | LWC3 = 1971, // MipsInstrInfo.td:2197 |
| 1987 | LWDSP = 1972, // MipsDSPInstrInfo.td:1301 |
| 1988 | LWDSP_MM = 1973, // MicroMipsDSPInstrInfo.td:408 |
| 1989 | LWE = 1974, // MipsEVAInstrInfo.td:194 |
| 1990 | LWE_MM = 1975, // MicroMipsInstrInfo.td:826 |
| 1991 | LWGP_MM = 1976, // MicroMipsInstrInfo.td:644 |
| 1992 | LWL = 1977, // MipsInstrInfo.td:2176 |
| 1993 | LWL64 = 1978, // Mips64InstrInfo.td:227 |
| 1994 | LWLE = 1979, // MipsEVAInstrInfo.td:200 |
| 1995 | LWLE_MM = 1980, // MicroMipsInstrInfo.td:838 |
| 1996 | LWL_MM = 1981, // MicroMipsInstrInfo.td:860 |
| 1997 | LWM16_MM = 1982, // MicroMipsInstrInfo.td:696 |
| 1998 | LWM16_MMR6 = 1983, // MicroMips32r6InstrInfo.td:1406 |
| 1999 | LWM32_MM = 1984, // MicroMipsInstrInfo.td:875 |
| 2000 | LWPC = 1985, // Mips32r6InstrInfo.td:938 |
| 2001 | LWPC_MMR6 = 1986, // MicroMips32r6InstrInfo.td:1405 |
| 2002 | LWP_MM = 1987, // MicroMipsInstrInfo.td:879 |
| 2003 | LWR = 1988, // MipsInstrInfo.td:2178 |
| 2004 | LWR64 = 1989, // Mips64InstrInfo.td:229 |
| 2005 | LWRE = 1990, // MipsEVAInstrInfo.td:201 |
| 2006 | LWRE_MM = 1991, // MicroMipsInstrInfo.td:842 |
| 2007 | LWR_MM = 1992, // MicroMipsInstrInfo.td:863 |
| 2008 | LWSP_MM = 1993, // MicroMipsInstrInfo.td:646 |
| 2009 | LWUPC = 1994, // Mips64r6InstrInfo.td:153 |
| 2010 | LWU_MM = 1995, // MicroMipsInstrInfo.td:1128 |
| 2011 | LWX = 1996, // MipsDSPInstrInfo.td:1213 |
| 2012 | LWXC1 = 1997, // MipsInstrFPU.td:648 |
| 2013 | LWXC1_MM = 1998, // MicroMipsInstrFPU.td:46 |
| 2014 | LWXS_MM = 1999, // MicroMipsInstrInfo.td:856 |
| 2015 | LWX_MM = 2000, // MicroMipsDSPInstrInfo.td:495 |
| 2016 | LW_MM = 2001, // MicroMipsInstrInfo.td:805 |
| 2017 | LW_MMR6 = 2002, // MicroMips32r6InstrInfo.td:1547 |
| 2018 | LWu = 2003, // Mips64InstrInfo.td:215 |
| 2019 | LbRxRyOffMemX16 = 2004, // Mips16InstrInfo.td:789 |
| 2020 | LbuRxRyOffMemX16 = 2005, // Mips16InstrInfo.td:798 |
| 2021 | LhRxRyOffMemX16 = 2006, // Mips16InstrInfo.td:808 |
| 2022 | LhuRxRyOffMemX16 = 2007, // Mips16InstrInfo.td:817 |
| 2023 | LiRxImm16 = 2008, // Mips16InstrInfo.td:827 |
| 2024 | LiRxImmAlignX16 = 2009, // Mips16InstrInfo.td:836 |
| 2025 | LiRxImmX16 = 2010, // Mips16InstrInfo.td:834 |
| 2026 | LwRxPcTcp16 = 2011, // Mips16InstrInfo.td:856 |
| 2027 | LwRxPcTcpX16 = 2012, // Mips16InstrInfo.td:858 |
| 2028 | LwRxRyOffMemX16 = 2013, // Mips16InstrInfo.td:845 |
| 2029 | LwRxSpImmX16 = 2014, // Mips16InstrInfo.td:854 |
| 2030 | MADD = 2015, // MipsInstrInfo.td:2450 |
| 2031 | MADDF_D = 2016, // Mips32r6InstrInfo.td:943 |
| 2032 | MADDF_D_MMR6 = 2017, // MicroMips32r6InstrInfo.td:1472 |
| 2033 | MADDF_S = 2018, // Mips32r6InstrInfo.td:942 |
| 2034 | MADDF_S_MMR6 = 2019, // MicroMips32r6InstrInfo.td:1470 |
| 2035 | MADDR_Q_H = 2020, // MipsMSAInstrInfo.td:3226 |
| 2036 | MADDR_Q_W = 2021, // MipsMSAInstrInfo.td:3227 |
| 2037 | MADDU = 2022, // MipsInstrInfo.td:2452 |
| 2038 | MADDU_DSP = 2023, // MipsDSPInstrInfo.td:1193 |
| 2039 | MADDU_DSP_MM = 2024, // MicroMipsDSPInstrInfo.td:430 |
| 2040 | MADDU_MM = 2025, // MicroMipsInstrInfo.td:918 |
| 2041 | MADDV_B = 2026, // MipsMSAInstrInfo.td:3229 |
| 2042 | MADDV_D = 2027, // MipsMSAInstrInfo.td:3232 |
| 2043 | MADDV_H = 2028, // MipsMSAInstrInfo.td:3230 |
| 2044 | MADDV_W = 2029, // MipsMSAInstrInfo.td:3231 |
| 2045 | MADD_D32 = 2030, // MipsInstrFPU.td:710 |
| 2046 | MADD_D32_MM = 2031, // MicroMipsInstrFPU.td:209 |
| 2047 | MADD_D64 = 2032, // MipsInstrFPU.td:716 |
| 2048 | MADD_DSP = 2033, // MipsDSPInstrInfo.td:1192 |
| 2049 | MADD_DSP_MM = 2034, // MicroMipsDSPInstrInfo.td:429 |
| 2050 | MADD_MM = 2035, // MicroMipsInstrInfo.td:916 |
| 2051 | MADD_Q_H = 2036, // MipsMSAInstrInfo.td:3223 |
| 2052 | MADD_Q_W = 2037, // MipsMSAInstrInfo.td:3224 |
| 2053 | MADD_S = 2038, // MipsInstrFPU.td:705 |
| 2054 | MADD_S_MM = 2039, // MicroMipsInstrFPU.td:205 |
| 2055 | MAQ_SA_W_PHL = 2040, // MipsDSPInstrInfo.td:1176 |
| 2056 | MAQ_SA_W_PHL_MM = 2041, // MicroMipsDSPInstrInfo.td:497 |
| 2057 | MAQ_SA_W_PHR = 2042, // MipsDSPInstrInfo.td:1177 |
| 2058 | MAQ_SA_W_PHR_MM = 2043, // MicroMipsDSPInstrInfo.td:499 |
| 2059 | MAQ_S_W_PHL = 2044, // MipsDSPInstrInfo.td:1174 |
| 2060 | MAQ_S_W_PHL_MM = 2045, // MicroMipsDSPInstrInfo.td:496 |
| 2061 | MAQ_S_W_PHR = 2046, // MipsDSPInstrInfo.td:1175 |
| 2062 | MAQ_S_W_PHR_MM = 2047, // MicroMipsDSPInstrInfo.td:498 |
| 2063 | MAXA_D = 2048, // Mips32r6InstrInfo.td:948 |
| 2064 | MAXA_D_MMR6 = 2049, // MicroMips32r6InstrInfo.td:1494 |
| 2065 | MAXA_S = 2050, // Mips32r6InstrInfo.td:949 |
| 2066 | MAXA_S_MMR6 = 2051, // MicroMips32r6InstrInfo.td:1492 |
| 2067 | MAXI_S_B = 2052, // MipsMSAInstrInfo.td:3249 |
| 2068 | MAXI_S_D = 2053, // MipsMSAInstrInfo.td:3252 |
| 2069 | MAXI_S_H = 2054, // MipsMSAInstrInfo.td:3250 |
| 2070 | MAXI_S_W = 2055, // MipsMSAInstrInfo.td:3251 |
| 2071 | MAXI_U_B = 2056, // MipsMSAInstrInfo.td:3254 |
| 2072 | MAXI_U_D = 2057, // MipsMSAInstrInfo.td:3257 |
| 2073 | MAXI_U_H = 2058, // MipsMSAInstrInfo.td:3255 |
| 2074 | MAXI_U_W = 2059, // MipsMSAInstrInfo.td:3256 |
| 2075 | MAX_A_B = 2060, // MipsMSAInstrInfo.td:3234 |
| 2076 | MAX_A_D = 2061, // MipsMSAInstrInfo.td:3237 |
| 2077 | MAX_A_H = 2062, // MipsMSAInstrInfo.td:3235 |
| 2078 | MAX_A_W = 2063, // MipsMSAInstrInfo.td:3236 |
| 2079 | MAX_D = 2064, // Mips32r6InstrInfo.td:950 |
| 2080 | MAX_D_MMR6 = 2065, // MicroMips32r6InstrInfo.td:1489 |
| 2081 | MAX_S = 2066, // Mips32r6InstrInfo.td:951 |
| 2082 | MAX_S_B = 2067, // MipsMSAInstrInfo.td:3239 |
| 2083 | MAX_S_D = 2068, // MipsMSAInstrInfo.td:3242 |
| 2084 | MAX_S_H = 2069, // MipsMSAInstrInfo.td:3240 |
| 2085 | MAX_S_MMR6 = 2070, // MicroMips32r6InstrInfo.td:1488 |
| 2086 | MAX_S_W = 2071, // MipsMSAInstrInfo.td:3241 |
| 2087 | MAX_U_B = 2072, // MipsMSAInstrInfo.td:3244 |
| 2088 | MAX_U_D = 2073, // MipsMSAInstrInfo.td:3247 |
| 2089 | MAX_U_H = 2074, // MipsMSAInstrInfo.td:3245 |
| 2090 | MAX_U_W = 2075, // MipsMSAInstrInfo.td:3246 |
| 2091 | MFC0 = 2076, // MipsInstrInfo.td:2497 |
| 2092 | MFC0_MMR6 = 2077, // MicroMips32r6InstrInfo.td:1412 |
| 2093 | MFC1 = 2078, // MipsInstrFPU.td:580 |
| 2094 | MFC1_D64 = 2079, // MipsInstrFPU.td:582 |
| 2095 | MFC1_MM = 2080, // MicroMipsInstrFPU.td:198 |
| 2096 | MFC1_MMR6 = 2081, // MicroMips32r6InstrInfo.td:1413 |
| 2097 | MFC2 = 2082, // MipsInstrInfo.td:2499 |
| 2098 | MFC2_MMR6 = 2083, // MicroMips32r6InstrInfo.td:1414 |
| 2099 | MFGC0 = 2084, // MipsInstrInfo.td:2698 |
| 2100 | MFGC0_MM = 2085, // MicroMipsInstrInfo.td:1132 |
| 2101 | MFHC0_MMR6 = 2086, // MicroMips32r6InstrInfo.td:1415 |
| 2102 | MFHC1_D32 = 2087, // MipsInstrFPU.td:593 |
| 2103 | MFHC1_D32_MM = 2088, // MicroMipsInstrFPU.td:246 |
| 2104 | MFHC1_D64 = 2089, // MipsInstrFPU.td:595 |
| 2105 | MFHC1_D64_MM = 2090, // MicroMipsInstrFPU.td:253 |
| 2106 | MFHC2_MMR6 = 2091, // MicroMips32r6InstrInfo.td:1416 |
| 2107 | MFHGC0 = 2092, // MipsInstrInfo.td:2702 |
| 2108 | MFHGC0_MM = 2093, // MicroMipsInstrInfo.td:1135 |
| 2109 | MFHI = 2094, // MipsInstrInfo.td:2416 |
| 2110 | MFHI16_MM = 2095, // MicroMipsInstrInfo.td:657 |
| 2111 | MFHI64 = 2096, // Mips64InstrInfo.td:345 |
| 2112 | MFHI_DSP = 2097, // MipsDSPInstrInfo.td:1178 |
| 2113 | MFHI_DSP_MM = 2098, // MicroMipsDSPInstrInfo.td:500 |
| 2114 | MFHI_MM = 2099, // MicroMipsInstrInfo.td:910 |
| 2115 | MFLO = 2100, // MipsInstrInfo.td:2418 |
| 2116 | MFLO16_MM = 2101, // MicroMipsInstrInfo.td:659 |
| 2117 | MFLO64 = 2102, // Mips64InstrInfo.td:347 |
| 2118 | MFLO_DSP = 2103, // MipsDSPInstrInfo.td:1179 |
| 2119 | MFLO_DSP_MM = 2104, // MicroMipsDSPInstrInfo.td:501 |
| 2120 | MFLO_MM = 2105, // MicroMipsInstrInfo.td:912 |
| 2121 | MFTR = 2106, // MipsMTInstrInfo.td:109 |
| 2122 | MINA_D = 2107, // Mips32r6InstrInfo.td:952 |
| 2123 | MINA_D_MMR6 = 2108, // MicroMips32r6InstrInfo.td:1498 |
| 2124 | MINA_S = 2109, // Mips32r6InstrInfo.td:953 |
| 2125 | MINA_S_MMR6 = 2110, // MicroMips32r6InstrInfo.td:1496 |
| 2126 | MINI_S_B = 2111, // MipsMSAInstrInfo.td:3274 |
| 2127 | MINI_S_D = 2112, // MipsMSAInstrInfo.td:3277 |
| 2128 | MINI_S_H = 2113, // MipsMSAInstrInfo.td:3275 |
| 2129 | MINI_S_W = 2114, // MipsMSAInstrInfo.td:3276 |
| 2130 | MINI_U_B = 2115, // MipsMSAInstrInfo.td:3279 |
| 2131 | MINI_U_D = 2116, // MipsMSAInstrInfo.td:3282 |
| 2132 | MINI_U_H = 2117, // MipsMSAInstrInfo.td:3280 |
| 2133 | MINI_U_W = 2118, // MipsMSAInstrInfo.td:3281 |
| 2134 | MIN_A_B = 2119, // MipsMSAInstrInfo.td:3259 |
| 2135 | MIN_A_D = 2120, // MipsMSAInstrInfo.td:3262 |
| 2136 | MIN_A_H = 2121, // MipsMSAInstrInfo.td:3260 |
| 2137 | MIN_A_W = 2122, // MipsMSAInstrInfo.td:3261 |
| 2138 | MIN_D = 2123, // Mips32r6InstrInfo.td:954 |
| 2139 | MIN_D_MMR6 = 2124, // MicroMips32r6InstrInfo.td:1491 |
| 2140 | MIN_S = 2125, // Mips32r6InstrInfo.td:955 |
| 2141 | MIN_S_B = 2126, // MipsMSAInstrInfo.td:3264 |
| 2142 | MIN_S_D = 2127, // MipsMSAInstrInfo.td:3267 |
| 2143 | MIN_S_H = 2128, // MipsMSAInstrInfo.td:3265 |
| 2144 | MIN_S_MMR6 = 2129, // MicroMips32r6InstrInfo.td:1490 |
| 2145 | MIN_S_W = 2130, // MipsMSAInstrInfo.td:3266 |
| 2146 | MIN_U_B = 2131, // MipsMSAInstrInfo.td:3269 |
| 2147 | MIN_U_D = 2132, // MipsMSAInstrInfo.td:3272 |
| 2148 | MIN_U_H = 2133, // MipsMSAInstrInfo.td:3270 |
| 2149 | MIN_U_W = 2134, // MipsMSAInstrInfo.td:3271 |
| 2150 | MOD = 2135, // Mips32r6InstrInfo.td:958 |
| 2151 | MODSUB = 2136, // MipsDSPInstrInfo.td:1134 |
| 2152 | MODSUB_MM = 2137, // MicroMipsDSPInstrInfo.td:517 |
| 2153 | MODU = 2138, // Mips32r6InstrInfo.td:959 |
| 2154 | MODU_MMR6 = 2139, // MicroMips32r6InstrInfo.td:1418 |
| 2155 | MOD_MMR6 = 2140, // MicroMips32r6InstrInfo.td:1417 |
| 2156 | MOD_S_B = 2141, // MipsMSAInstrInfo.td:3284 |
| 2157 | MOD_S_D = 2142, // MipsMSAInstrInfo.td:3287 |
| 2158 | MOD_S_H = 2143, // MipsMSAInstrInfo.td:3285 |
| 2159 | MOD_S_W = 2144, // MipsMSAInstrInfo.td:3286 |
| 2160 | MOD_U_B = 2145, // MipsMSAInstrInfo.td:3289 |
| 2161 | MOD_U_D = 2146, // MipsMSAInstrInfo.td:3292 |
| 2162 | MOD_U_H = 2147, // MipsMSAInstrInfo.td:3290 |
| 2163 | MOD_U_W = 2148, // MipsMSAInstrInfo.td:3291 |
| 2164 | MOVE16_MM = 2149, // MicroMipsInstrInfo.td:661 |
| 2165 | MOVE16_MMR6 = 2150, // MicroMips32r6InstrInfo.td:1567 |
| 2166 | MOVEP_MM = 2151, // MicroMipsInstrInfo.td:663 |
| 2167 | MOVEP_MMR6 = 2152, // MicroMips32r6InstrInfo.td:1569 |
| 2168 | MOVE_V = 2153, // MipsMSAInstrInfo.td:3294 |
| 2169 | MOVF_D32 = 2154, // MipsCondMov.td:187 |
| 2170 | MOVF_D32_MM = 2155, // MicroMipsInstrFPU.td:194 |
| 2171 | MOVF_D64 = 2156, // MipsCondMov.td:194 |
| 2172 | MOVF_I = 2157, // MipsCondMov.td:173 |
| 2173 | MOVF_I64 = 2158, // MipsCondMov.td:177 |
| 2174 | MOVF_I_MM = 2159, // MicroMipsInstrInfo.td:903 |
| 2175 | MOVF_S = 2160, // MipsCondMov.td:181 |
| 2176 | MOVF_S_MM = 2161, // MicroMipsInstrFPU.td:188 |
| 2177 | MOVN_I64_D64 = 2162, // MipsCondMov.td:160 |
| 2178 | MOVN_I64_I = 2163, // MipsCondMov.td:125 |
| 2179 | MOVN_I64_I64 = 2164, // MipsCondMov.td:127 |
| 2180 | MOVN_I64_S = 2165, // MipsCondMov.td:141 |
| 2181 | MOVN_I_D32 = 2166, // MipsCondMov.td:147 |
| 2182 | MOVN_I_D32_MM = 2167, // MicroMipsInstrFPU.td:181 |
| 2183 | MOVN_I_D64 = 2168, // MipsCondMov.td:154 |
| 2184 | MOVN_I_I = 2169, // MipsCondMov.td:119 |
| 2185 | MOVN_I_I64 = 2170, // MipsCondMov.td:123 |
| 2186 | MOVN_I_MM = 2171, // MicroMipsInstrInfo.td:898 |
| 2187 | MOVN_I_S = 2172, // MipsCondMov.td:137 |
| 2188 | MOVN_I_S_MM = 2173, // MicroMipsInstrFPU.td:175 |
| 2189 | MOVT_D32 = 2174, // MipsCondMov.td:184 |
| 2190 | MOVT_D32_MM = 2175, // MicroMipsInstrFPU.td:191 |
| 2191 | MOVT_D64 = 2176, // MipsCondMov.td:192 |
| 2192 | MOVT_I = 2177, // MipsCondMov.td:166 |
| 2193 | MOVT_I64 = 2178, // MipsCondMov.td:170 |
| 2194 | MOVT_I_MM = 2179, // MicroMipsInstrInfo.td:901 |
| 2195 | MOVT_S = 2180, // MipsCondMov.td:179 |
| 2196 | MOVT_S_MM = 2181, // MicroMipsInstrFPU.td:185 |
| 2197 | MOVZ_I64_D64 = 2182, // MipsCondMov.td:157 |
| 2198 | MOVZ_I64_I = 2183, // MipsCondMov.td:113 |
| 2199 | MOVZ_I64_I64 = 2184, // MipsCondMov.td:115 |
| 2200 | MOVZ_I64_S = 2185, // MipsCondMov.td:134 |
| 2201 | MOVZ_I_D32 = 2186, // MipsCondMov.td:144 |
| 2202 | MOVZ_I_D32_MM = 2187, // MicroMipsInstrFPU.td:178 |
| 2203 | MOVZ_I_D64 = 2188, // MipsCondMov.td:152 |
| 2204 | MOVZ_I_I = 2189, // MipsCondMov.td:107 |
| 2205 | MOVZ_I_I64 = 2190, // MipsCondMov.td:111 |
| 2206 | MOVZ_I_MM = 2191, // MicroMipsInstrInfo.td:895 |
| 2207 | MOVZ_I_S = 2192, // MipsCondMov.td:130 |
| 2208 | MOVZ_I_S_MM = 2193, // MicroMipsInstrFPU.td:172 |
| 2209 | MSUB = 2194, // MipsInstrInfo.td:2454 |
| 2210 | MSUBF_D = 2195, // Mips32r6InstrInfo.td:945 |
| 2211 | MSUBF_D_MMR6 = 2196, // MicroMips32r6InstrInfo.td:1476 |
| 2212 | MSUBF_S = 2197, // Mips32r6InstrInfo.td:944 |
| 2213 | MSUBF_S_MMR6 = 2198, // MicroMips32r6InstrInfo.td:1474 |
| 2214 | MSUBR_Q_H = 2199, // MipsMSAInstrInfo.td:3299 |
| 2215 | MSUBR_Q_W = 2200, // MipsMSAInstrInfo.td:3300 |
| 2216 | MSUBU = 2201, // MipsInstrInfo.td:2456 |
| 2217 | MSUBU_DSP = 2202, // MipsDSPInstrInfo.td:1195 |
| 2218 | MSUBU_DSP_MM = 2203, // MicroMipsDSPInstrInfo.td:432 |
| 2219 | MSUBU_MM = 2204, // MicroMipsInstrInfo.td:922 |
| 2220 | MSUBV_B = 2205, // MipsMSAInstrInfo.td:3302 |
| 2221 | MSUBV_D = 2206, // MipsMSAInstrInfo.td:3305 |
| 2222 | MSUBV_H = 2207, // MipsMSAInstrInfo.td:3303 |
| 2223 | MSUBV_W = 2208, // MipsMSAInstrInfo.td:3304 |
| 2224 | MSUB_D32 = 2209, // MipsInstrFPU.td:712 |
| 2225 | MSUB_D32_MM = 2210, // MicroMipsInstrFPU.td:212 |
| 2226 | MSUB_D64 = 2211, // MipsInstrFPU.td:718 |
| 2227 | MSUB_DSP = 2212, // MipsDSPInstrInfo.td:1194 |
| 2228 | MSUB_DSP_MM = 2213, // MicroMipsDSPInstrInfo.td:431 |
| 2229 | MSUB_MM = 2214, // MicroMipsInstrInfo.td:920 |
| 2230 | MSUB_Q_H = 2215, // MipsMSAInstrInfo.td:3296 |
| 2231 | MSUB_Q_W = 2216, // MipsMSAInstrInfo.td:3297 |
| 2232 | MSUB_S = 2217, // MipsInstrFPU.td:707 |
| 2233 | MSUB_S_MM = 2218, // MicroMipsInstrFPU.td:207 |
| 2234 | MTC0 = 2219, // MipsInstrInfo.td:2495 |
| 2235 | MTC0_MMR6 = 2220, // MicroMips32r6InstrInfo.td:1407 |
| 2236 | MTC1 = 2221, // MipsInstrFPU.td:586 |
| 2237 | MTC1_D64 = 2222, // MipsInstrFPU.td:588 |
| 2238 | MTC1_D64_MM = 2223, // MicroMipsInstrFPU.td:255 |
| 2239 | MTC1_MM = 2224, // MicroMipsInstrFPU.td:201 |
| 2240 | MTC1_MMR6 = 2225, // MicroMips32r6InstrInfo.td:1408 |
| 2241 | MTC2 = 2226, // MipsInstrInfo.td:2501 |
| 2242 | MTC2_MMR6 = 2227, // MicroMips32r6InstrInfo.td:1409 |
| 2243 | MTGC0 = 2228, // MipsInstrInfo.td:2700 |
| 2244 | MTGC0_MM = 2229, // MicroMipsInstrInfo.td:1138 |
| 2245 | MTHC0_MMR6 = 2230, // MicroMips32r6InstrInfo.td:1410 |
| 2246 | MTHC1_D32 = 2231, // MipsInstrFPU.td:600 |
| 2247 | MTHC1_D32_MM = 2232, // MicroMipsInstrFPU.td:243 |
| 2248 | MTHC1_D64 = 2233, // MipsInstrFPU.td:603 |
| 2249 | MTHC1_D64_MM = 2234, // MicroMipsInstrFPU.td:251 |
| 2250 | MTHC2_MMR6 = 2235, // MicroMips32r6InstrInfo.td:1411 |
| 2251 | MTHGC0 = 2236, // MipsInstrInfo.td:2704 |
| 2252 | MTHGC0_MM = 2237, // MicroMipsInstrInfo.td:1141 |
| 2253 | MTHI = 2238, // MipsInstrInfo.td:2412 |
| 2254 | MTHI64 = 2239, // Mips64InstrInfo.td:341 |
| 2255 | MTHI_DSP = 2240, // MipsDSPInstrInfo.td:1180 |
| 2256 | MTHI_DSP_MM = 2241, // MicroMipsDSPInstrInfo.td:502 |
| 2257 | MTHI_MM = 2242, // MicroMipsInstrInfo.td:906 |
| 2258 | MTHLIP = 2243, // MipsDSPInstrInfo.td:1234 |
| 2259 | MTHLIP_MM = 2244, // MicroMipsDSPInstrInfo.td:510 |
| 2260 | MTLO = 2245, // MipsInstrInfo.td:2414 |
| 2261 | MTLO64 = 2246, // Mips64InstrInfo.td:343 |
| 2262 | MTLO_DSP = 2247, // MipsDSPInstrInfo.td:1181 |
| 2263 | MTLO_DSP_MM = 2248, // MicroMipsDSPInstrInfo.td:503 |
| 2264 | MTLO_MM = 2249, // MicroMipsInstrInfo.td:908 |
| 2265 | MTM0 = 2250, // Mips64InstrInfo.td:565 |
| 2266 | MTM1 = 2251, // Mips64InstrInfo.td:567 |
| 2267 | MTM2 = 2252, // Mips64InstrInfo.td:569 |
| 2268 | MTP0 = 2253, // Mips64InstrInfo.td:571 |
| 2269 | MTP1 = 2254, // Mips64InstrInfo.td:572 |
| 2270 | MTP2 = 2255, // Mips64InstrInfo.td:573 |
| 2271 | MTTR = 2256, // MipsMTInstrInfo.td:111 |
| 2272 | MUH = 2257, // Mips32r6InstrInfo.td:960 |
| 2273 | MUHU = 2258, // Mips32r6InstrInfo.td:961 |
| 2274 | MUHU_MMR6 = 2259, // MicroMips32r6InstrInfo.td:1422 |
| 2275 | MUH_MMR6 = 2260, // MicroMips32r6InstrInfo.td:1420 |
| 2276 | MUL = 2261, // MipsInstrInfo.td:2108 |
| 2277 | MULEQ_S_W_PHL = 2262, // MipsDSPInstrInfo.td:1170 |
| 2278 | MULEQ_S_W_PHL_MM = 2263, // MicroMipsDSPInstrInfo.td:484 |
| 2279 | MULEQ_S_W_PHR = 2264, // MipsDSPInstrInfo.td:1171 |
| 2280 | MULEQ_S_W_PHR_MM = 2265, // MicroMipsDSPInstrInfo.td:485 |
| 2281 | MULEU_S_PH_QBL = 2266, // MipsDSPInstrInfo.td:1168 |
| 2282 | MULEU_S_PH_QBL_MM = 2267, // MicroMipsDSPInstrInfo.td:486 |
| 2283 | MULEU_S_PH_QBR = 2268, // MipsDSPInstrInfo.td:1169 |
| 2284 | MULEU_S_PH_QBR_MM = 2269, // MicroMipsDSPInstrInfo.td:487 |
| 2285 | MULQ_RS_PH = 2270, // MipsDSPInstrInfo.td:1172 |
| 2286 | MULQ_RS_PH_MM = 2271, // MicroMipsDSPInstrInfo.td:488 |
| 2287 | MULQ_RS_W = 2272, // MipsDSPInstrInfo.td:1264 |
| 2288 | MULQ_RS_W_MMR2 = 2273, // MicroMipsDSPInstrInfo.td:579 |
| 2289 | MULQ_S_PH = 2274, // MipsDSPInstrInfo.td:1265 |
| 2290 | MULQ_S_PH_MMR2 = 2275, // MicroMipsDSPInstrInfo.td:580 |
| 2291 | MULQ_S_W = 2276, // MipsDSPInstrInfo.td:1263 |
| 2292 | MULQ_S_W_MMR2 = 2277, // MicroMipsDSPInstrInfo.td:581 |
| 2293 | MULR_PS64 = 2278, // MipsInstrFPU.td:516 |
| 2294 | MULR_Q_H = 2279, // MipsMSAInstrInfo.td:3310 |
| 2295 | MULR_Q_W = 2280, // MipsMSAInstrInfo.td:3311 |
| 2296 | MULSAQ_S_W_PH = 2281, // MipsDSPInstrInfo.td:1173 |
| 2297 | MULSAQ_S_W_PH_MM = 2282, // MicroMipsDSPInstrInfo.td:518 |
| 2298 | MULSA_W_PH = 2283, // MipsDSPInstrInfo.td:1274 |
| 2299 | MULSA_W_PH_MMR2 = 2284, // MicroMipsDSPInstrInfo.td:593 |
| 2300 | MULT = 2285, // MipsInstrInfo.td:2404 |
| 2301 | MULTU_DSP = 2286, // MipsDSPInstrInfo.td:1191 |
| 2302 | MULTU_DSP_MM = 2287, // MicroMipsDSPInstrInfo.td:434 |
| 2303 | MULT_DSP = 2288, // MipsDSPInstrInfo.td:1190 |
| 2304 | MULT_DSP_MM = 2289, // MicroMipsDSPInstrInfo.td:433 |
| 2305 | MULT_MM = 2290, // MicroMipsInstrInfo.td:758 |
| 2306 | MULTu = 2291, // MipsInstrInfo.td:2406 |
| 2307 | MULTu_MM = 2292, // MicroMipsInstrInfo.td:760 |
| 2308 | MULU = 2293, // Mips32r6InstrInfo.td:963 |
| 2309 | MULU_MMR6 = 2294, // MicroMips32r6InstrInfo.td:1421 |
| 2310 | MULV_B = 2295, // MipsMSAInstrInfo.td:3313 |
| 2311 | MULV_D = 2296, // MipsMSAInstrInfo.td:3316 |
| 2312 | MULV_H = 2297, // MipsMSAInstrInfo.td:3314 |
| 2313 | MULV_W = 2298, // MipsMSAInstrInfo.td:3315 |
| 2314 | MUL_MM = 2299, // MicroMipsInstrInfo.td:740 |
| 2315 | MUL_MMR6 = 2300, // MicroMips32r6InstrInfo.td:1419 |
| 2316 | MUL_PH = 2301, // MipsDSPInstrInfo.td:1261 |
| 2317 | MUL_PH_MMR2 = 2302, // MicroMipsDSPInstrInfo.td:577 |
| 2318 | MUL_Q_H = 2303, // MipsMSAInstrInfo.td:3307 |
| 2319 | MUL_Q_W = 2304, // MipsMSAInstrInfo.td:3308 |
| 2320 | MUL_R6 = 2305, // Mips32r6InstrInfo.td:962 |
| 2321 | MUL_S_PH = 2306, // MipsDSPInstrInfo.td:1262 |
| 2322 | MUL_S_PH_MMR2 = 2307, // MicroMipsDSPInstrInfo.td:578 |
| 2323 | Mfhi16 = 2308, // Mips16InstrInfo.td:881 |
| 2324 | Mflo16 = 2309, // Mips16InstrInfo.td:893 |
| 2325 | Move32R16 = 2310, // Mips16InstrInfo.td:865 |
| 2326 | MoveR3216 = 2311, // Mips16InstrInfo.td:872 |
| 2327 | NAL = 2312, // Mips32r6InstrInfo.td:880 |
| 2328 | NLOC_B = 2313, // MipsMSAInstrInfo.td:3318 |
| 2329 | NLOC_D = 2314, // MipsMSAInstrInfo.td:3321 |
| 2330 | NLOC_H = 2315, // MipsMSAInstrInfo.td:3319 |
| 2331 | NLOC_W = 2316, // MipsMSAInstrInfo.td:3320 |
| 2332 | NLZC_B = 2317, // MipsMSAInstrInfo.td:3323 |
| 2333 | NLZC_D = 2318, // MipsMSAInstrInfo.td:3326 |
| 2334 | NLZC_H = 2319, // MipsMSAInstrInfo.td:3324 |
| 2335 | NLZC_W = 2320, // MipsMSAInstrInfo.td:3325 |
| 2336 | NMADD_D32 = 2321, // MipsInstrFPU.td:729 |
| 2337 | NMADD_D32_MM = 2322, // MicroMipsInstrFPU.td:221 |
| 2338 | NMADD_D64 = 2323, // MipsInstrFPU.td:735 |
| 2339 | NMADD_S = 2324, // MipsInstrFPU.td:724 |
| 2340 | NMADD_S_MM = 2325, // MicroMipsInstrFPU.td:217 |
| 2341 | NMSUB_D32 = 2326, // MipsInstrFPU.td:731 |
| 2342 | NMSUB_D32_MM = 2327, // MicroMipsInstrFPU.td:223 |
| 2343 | NMSUB_D64 = 2328, // MipsInstrFPU.td:737 |
| 2344 | NMSUB_S = 2329, // MipsInstrFPU.td:726 |
| 2345 | NMSUB_S_MM = 2330, // MicroMipsInstrFPU.td:219 |
| 2346 | NOR = 2331, // MipsInstrInfo.td:2126 |
| 2347 | NOR64 = 2332, // Mips64InstrInfo.td:162 |
| 2348 | NORI_B = 2333, // MipsMSAInstrInfo.td:3342 |
| 2349 | NOR_MM = 2334, // MicroMipsInstrInfo.td:756 |
| 2350 | NOR_MMR6 = 2335, // MicroMips32r6InstrInfo.td:1423 |
| 2351 | NOR_V = 2336, // MipsMSAInstrInfo.td:3328 |
| 2352 | NOT16_MM = 2337, // MicroMipsInstrInfo.td:613 |
| 2353 | NOT16_MMR6 = 2338, // MicroMips32r6InstrInfo.td:1555 |
| 2354 | NegRxRy16 = 2339, // Mips16InstrInfo.td:942 |
| 2355 | NotRxRy16 = 2340, // Mips16InstrInfo.td:949 |
| 2356 | OR = 2341, // MipsInstrInfo.td:2122 |
| 2357 | OR16_MM = 2342, // MicroMipsInstrInfo.td:616 |
| 2358 | OR16_MMR6 = 2343, // MicroMips32r6InstrInfo.td:1557 |
| 2359 | OR64 = 2344, // Mips64InstrInfo.td:158 |
| 2360 | ORI_B = 2345, // MipsMSAInstrInfo.td:3358 |
| 2361 | ORI_MMR6 = 2346, // MicroMips32r6InstrInfo.td:1425 |
| 2362 | OR_MM = 2347, // MicroMipsInstrInfo.td:752 |
| 2363 | OR_MMR6 = 2348, // MicroMips32r6InstrInfo.td:1424 |
| 2364 | OR_V = 2349, // MipsMSAInstrInfo.td:3344 |
| 2365 | ORi = 2350, // MipsInstrInfo.td:2085 |
| 2366 | ORi64 = 2351, // Mips64InstrInfo.td:134 |
| 2367 | ORi_MM = 2352, // MicroMipsInstrInfo.td:722 |
| 2368 | OrRxRxRy16 = 2353, // Mips16InstrInfo.td:956 |
| 2369 | PACKRL_PH = 2354, // MipsDSPInstrInfo.td:1206 |
| 2370 | PACKRL_PH_MM = 2355, // MicroMipsDSPInstrInfo.td:511 |
| 2371 | PAUSE = 2356, // MipsInstrInfo.td:2513 |
| 2372 | PAUSE_MM = 2357, // MicroMipsInstrInfo.td:1076 |
| 2373 | PAUSE_MMR6 = 2358, // MicroMips32r6InstrInfo.td:1444 |
| 2374 | PCKEV_B = 2359, // MipsMSAInstrInfo.td:3360 |
| 2375 | PCKEV_D = 2360, // MipsMSAInstrInfo.td:3363 |
| 2376 | PCKEV_H = 2361, // MipsMSAInstrInfo.td:3361 |
| 2377 | PCKEV_W = 2362, // MipsMSAInstrInfo.td:3362 |
| 2378 | PCKOD_B = 2363, // MipsMSAInstrInfo.td:3365 |
| 2379 | PCKOD_D = 2364, // MipsMSAInstrInfo.td:3368 |
| 2380 | PCKOD_H = 2365, // MipsMSAInstrInfo.td:3366 |
| 2381 | PCKOD_W = 2366, // MipsMSAInstrInfo.td:3367 |
| 2382 | PCNT_B = 2367, // MipsMSAInstrInfo.td:3370 |
| 2383 | PCNT_D = 2368, // MipsMSAInstrInfo.td:3373 |
| 2384 | PCNT_H = 2369, // MipsMSAInstrInfo.td:3371 |
| 2385 | PCNT_W = 2370, // MipsMSAInstrInfo.td:3372 |
| 2386 | PICK_PH = 2371, // MipsDSPInstrInfo.td:1212 |
| 2387 | PICK_PH_MM = 2372, // MicroMipsDSPInstrInfo.td:512 |
| 2388 | PICK_QB = 2373, // MipsDSPInstrInfo.td:1211 |
| 2389 | PICK_QB_MM = 2374, // MicroMipsDSPInstrInfo.td:513 |
| 2390 | PLL_PS64 = 2375, // MipsInstrFPU.td:492 |
| 2391 | PLU_PS64 = 2376, // MipsInstrFPU.td:495 |
| 2392 | POP = 2377, // Mips64InstrInfo.td:576 |
| 2393 | PRECEQU_PH_QBL = 2378, // MipsDSPInstrInfo.td:1144 |
| 2394 | PRECEQU_PH_QBLA = 2379, // MipsDSPInstrInfo.td:1146 |
| 2395 | PRECEQU_PH_QBLA_MM = 2380, // MicroMipsDSPInstrInfo.td:454 |
| 2396 | PRECEQU_PH_QBL_MM = 2381, // MicroMipsDSPInstrInfo.td:453 |
| 2397 | PRECEQU_PH_QBR = 2382, // MipsDSPInstrInfo.td:1145 |
| 2398 | PRECEQU_PH_QBRA = 2383, // MipsDSPInstrInfo.td:1147 |
| 2399 | PRECEQU_PH_QBRA_MM = 2384, // MicroMipsDSPInstrInfo.td:457 |
| 2400 | PRECEQU_PH_QBR_MM = 2385, // MicroMipsDSPInstrInfo.td:456 |
| 2401 | PRECEQ_W_PHL = 2386, // MipsDSPInstrInfo.td:1142 |
| 2402 | PRECEQ_W_PHL_MM = 2387, // MicroMipsDSPInstrInfo.td:451 |
| 2403 | PRECEQ_W_PHR = 2388, // MipsDSPInstrInfo.td:1143 |
| 2404 | PRECEQ_W_PHR_MM = 2389, // MicroMipsDSPInstrInfo.td:452 |
| 2405 | PRECEU_PH_QBL = 2390, // MipsDSPInstrInfo.td:1148 |
| 2406 | PRECEU_PH_QBLA = 2391, // MipsDSPInstrInfo.td:1150 |
| 2407 | PRECEU_PH_QBLA_MM = 2392, // MicroMipsDSPInstrInfo.td:460 |
| 2408 | PRECEU_PH_QBL_MM = 2393, // MicroMipsDSPInstrInfo.td:459 |
| 2409 | PRECEU_PH_QBR = 2394, // MipsDSPInstrInfo.td:1149 |
| 2410 | PRECEU_PH_QBRA = 2395, // MipsDSPInstrInfo.td:1151 |
| 2411 | PRECEU_PH_QBRA_MM = 2396, // MicroMipsDSPInstrInfo.td:462 |
| 2412 | PRECEU_PH_QBR_MM = 2397, // MicroMipsDSPInstrInfo.td:461 |
| 2413 | PRECRQU_S_QB_PH = 2398, // MipsDSPInstrInfo.td:1141 |
| 2414 | PRECRQU_S_QB_PH_MM = 2399, // MicroMipsDSPInstrInfo.td:491 |
| 2415 | PRECRQ_PH_W = 2400, // MipsDSPInstrInfo.td:1139 |
| 2416 | PRECRQ_PH_W_MM = 2401, // MicroMipsDSPInstrInfo.td:489 |
| 2417 | PRECRQ_QB_PH = 2402, // MipsDSPInstrInfo.td:1138 |
| 2418 | PRECRQ_QB_PH_MM = 2403, // MicroMipsDSPInstrInfo.td:490 |
| 2419 | PRECRQ_RS_PH_W = 2404, // MipsDSPInstrInfo.td:1140 |
| 2420 | PRECRQ_RS_PH_W_MM = 2405, // MicroMipsDSPInstrInfo.td:492 |
| 2421 | PRECR_QB_PH = 2406, // MipsDSPInstrInfo.td:1275 |
| 2422 | PRECR_QB_PH_MMR2 = 2407, // MicroMipsDSPInstrInfo.td:582 |
| 2423 | PRECR_SRA_PH_W = 2408, // MipsDSPInstrInfo.td:1276 |
| 2424 | PRECR_SRA_PH_W_MMR2 = 2409, // MicroMipsDSPInstrInfo.td:584 |
| 2425 | PRECR_SRA_R_PH_W = 2410, // MipsDSPInstrInfo.td:1277 |
| 2426 | PRECR_SRA_R_PH_W_MMR2 = 2411, // MicroMipsDSPInstrInfo.td:586 |
| 2427 | PREF = 2412, // MipsInstrInfo.td:2590 |
| 2428 | PREFE = 2413, // MipsEVAInstrInfo.td:215 |
| 2429 | PREFE_MM = 2414, // MicroMipsInstrInfo.td:1067 |
| 2430 | PREFX_MM = 2415, // MicroMipsInstrInfo.td:1091 |
| 2431 | PREF_MM = 2416, // MicroMipsInstrInfo.td:1062 |
| 2432 | PREF_MMR6 = 2417, // MicroMips32r6InstrInfo.td:1426 |
| 2433 | PREF_R6 = 2418, // Mips32r6InstrInfo.td:971 |
| 2434 | PREPEND = 2419, // MipsDSPInstrInfo.td:1286 |
| 2435 | PREPEND_MMR2 = 2420, // MicroMipsDSPInstrInfo.td:588 |
| 2436 | PUL_PS64 = 2421, // MipsInstrFPU.td:498 |
| 2437 | PUU_PS64 = 2422, // MipsInstrFPU.td:501 |
| 2438 | RADDU_W_QB = 2423, // MipsDSPInstrInfo.td:1135 |
| 2439 | RADDU_W_QB_MM = 2424, // MicroMipsDSPInstrInfo.td:504 |
| 2440 | RDDSP = 2425, // MipsDSPInstrInfo.td:1235 |
| 2441 | RDDSP_MM = 2426, // MicroMipsDSPInstrInfo.td:505 |
| 2442 | RDHWR = 2427, // MipsInstrInfo.td:2483 |
| 2443 | RDHWR64 = 2428, // Mips64InstrInfo.td:380 |
| 2444 | RDHWR_MM = 2429, // MicroMipsInstrInfo.td:1126 |
| 2445 | RDHWR_MMR6 = 2430, // MicroMips32r6InstrInfo.td:1445 |
| 2446 | RDPGPR_MMR6 = 2431, // MicroMips32r6InstrInfo.td:1450 |
| 2447 | RECIP_D32 = 2432, // MipsInstrFPU.td:417 |
| 2448 | RECIP_D32_MM = 2433, // MicroMipsInstrFPU.td:269 |
| 2449 | RECIP_D64 = 2434, // MipsInstrFPU.td:422 |
| 2450 | RECIP_D64_MM = 2435, // MicroMipsInstrFPU.td:275 |
| 2451 | RECIP_S = 2436, // MipsInstrFPU.td:415 |
| 2452 | RECIP_S_MM = 2437, // MicroMipsInstrFPU.td:266 |
| 2453 | REPLV_PH = 2438, // MipsDSPInstrInfo.td:1210 |
| 2454 | REPLV_PH_MM = 2439, // MicroMipsDSPInstrInfo.td:508 |
| 2455 | REPLV_QB = 2440, // MipsDSPInstrInfo.td:1209 |
| 2456 | REPLV_QB_MM = 2441, // MicroMipsDSPInstrInfo.td:509 |
| 2457 | REPL_PH = 2442, // MipsDSPInstrInfo.td:1208 |
| 2458 | REPL_PH_MM = 2443, // MicroMipsDSPInstrInfo.td:506 |
| 2459 | REPL_QB = 2444, // MipsDSPInstrInfo.td:1207 |
| 2460 | REPL_QB_MM = 2445, // MicroMipsDSPInstrInfo.td:507 |
| 2461 | RINT_D = 2446, // Mips32r6InstrInfo.td:967 |
| 2462 | RINT_D_MMR6 = 2447, // MicroMips32r6InstrInfo.td:1587 |
| 2463 | RINT_S = 2448, // Mips32r6InstrInfo.td:968 |
| 2464 | RINT_S_MMR6 = 2449, // MicroMips32r6InstrInfo.td:1585 |
| 2465 | ROTR = 2450, // MipsInstrInfo.td:2146 |
| 2466 | ROTRV = 2451, // MipsInstrInfo.td:2149 |
| 2467 | ROTRV_MM = 2452, // MicroMipsInstrInfo.td:789 |
| 2468 | ROTR_MM = 2453, // MicroMipsInstrInfo.td:784 |
| 2469 | ROUND_L_D64 = 2454, // MipsInstrFPU.td:441 |
| 2470 | ROUND_L_D_MMR6 = 2455, // MicroMips32r6InstrInfo.td:1592 |
| 2471 | ROUND_L_S = 2456, // MipsInstrFPU.td:439 |
| 2472 | ROUND_L_S_MMR6 = 2457, // MicroMips32r6InstrInfo.td:1590 |
| 2473 | ROUND_W_D32 = 2458, // MipsInstrFPU.td:166 |
| 2474 | ROUND_W_D64 = 2459, // MipsInstrFPU.td:167 |
| 2475 | ROUND_W_D_MMR6 = 2460, // MicroMips32r6InstrInfo.td:1596 |
| 2476 | ROUND_W_MM = 2461, // MicroMipsInstrFPU.td:95 |
| 2477 | ROUND_W_S = 2462, // MipsInstrFPU.td:389 |
| 2478 | ROUND_W_S_MM = 2463, // MicroMipsInstrFPU.td:87 |
| 2479 | ROUND_W_S_MMR6 = 2464, // MicroMips32r6InstrInfo.td:1594 |
| 2480 | RSQRT_D32 = 2465, // MipsInstrFPU.td:427 |
| 2481 | RSQRT_D32_MM = 2466, // MicroMipsInstrFPU.td:281 |
| 2482 | RSQRT_D64 = 2467, // MipsInstrFPU.td:432 |
| 2483 | RSQRT_D64_MM = 2468, // MicroMipsInstrFPU.td:287 |
| 2484 | RSQRT_S = 2469, // MipsInstrFPU.td:425 |
| 2485 | RSQRT_S_MM = 2470, // MicroMipsInstrFPU.td:278 |
| 2486 | Restore16 = 2471, // Mips16InstrInfo.td:967 |
| 2487 | RestoreX16 = 2472, // Mips16InstrInfo.td:976 |
| 2488 | SAA = 2473, // Mips64InstrInfo.td:619 |
| 2489 | SAAD = 2474, // Mips64InstrInfo.td:620 |
| 2490 | SAT_S_B = 2475, // MipsMSAInstrInfo.td:3375 |
| 2491 | SAT_S_D = 2476, // MipsMSAInstrInfo.td:3378 |
| 2492 | SAT_S_H = 2477, // MipsMSAInstrInfo.td:3376 |
| 2493 | SAT_S_W = 2478, // MipsMSAInstrInfo.td:3377 |
| 2494 | SAT_U_B = 2479, // MipsMSAInstrInfo.td:3380 |
| 2495 | SAT_U_D = 2480, // MipsMSAInstrInfo.td:3383 |
| 2496 | SAT_U_H = 2481, // MipsMSAInstrInfo.td:3381 |
| 2497 | SAT_U_W = 2482, // MipsMSAInstrInfo.td:3382 |
| 2498 | SB = 2483, // MipsInstrInfo.td:2166 |
| 2499 | SB16_MM = 2484, // MicroMipsInstrInfo.td:635 |
| 2500 | SB16_MMR6 = 2485, // MicroMips32r6InstrInfo.td:1427 |
| 2501 | SB64 = 2486, // Mips64InstrInfo.td:207 |
| 2502 | SBE = 2487, // MipsEVAInstrInfo.td:195 |
| 2503 | SBE_MM = 2488, // MicroMipsInstrInfo.td:829 |
| 2504 | SB_MM = 2489, // MicroMipsInstrInfo.td:807 |
| 2505 | SB_MMR6 = 2490, // MicroMips32r6InstrInfo.td:1545 |
| 2506 | SC = 2491, // MipsInstrInfo.td:2275 |
| 2507 | SC64 = 2492, // Mips64InstrInfo.td:260 |
| 2508 | SC64_R6 = 2493, // Mips64r6InstrInfo.td:163 |
| 2509 | SCD = 2494, // Mips64InstrInfo.td:252 |
| 2510 | SCD_R6 = 2495, // Mips64r6InstrInfo.td:154 |
| 2511 | SCE = 2496, // MipsEVAInstrInfo.td:207 |
| 2512 | SCE_MM = 2497, // MicroMipsInstrInfo.td:1056 |
| 2513 | SC_MM = 2498, // MicroMipsInstrInfo.td:1051 |
| 2514 | SC_MMR6 = 2499, // MicroMips32r6InstrInfo.td:1641 |
| 2515 | SC_R6 = 2500, // Mips32r6InstrInfo.td:972 |
| 2516 | SD = 2501, // Mips64InstrInfo.td:219 |
| 2517 | SDBBP = 2502, // MipsInstrInfo.td:2253 |
| 2518 | SDBBP16_MM = 2503, // MicroMipsInstrInfo.td:685 |
| 2519 | SDBBP16_MMR6 = 2504, // MicroMips32r6InstrInfo.td:1571 |
| 2520 | SDBBP_MM = 2505, // MicroMipsInstrInfo.td:1088 |
| 2521 | SDBBP_MMR6 = 2506, // MicroMips32r6InstrInfo.td:1452 |
| 2522 | SDBBP_R6 = 2507, // Mips32r6InstrInfo.td:973 |
| 2523 | SDC1 = 2508, // MipsInstrFPU.td:641 |
| 2524 | SDC164 = 2509, // MipsInstrFPU.td:632 |
| 2525 | SDC1_D64_MMR6 = 2510, // MicroMips32r6InstrInfo.td:1633 |
| 2526 | SDC1_MM_D32 = 2511, // MicroMipsInstrFPU.td:298 |
| 2527 | SDC1_MM_D64 = 2512, // MicroMipsInstrFPU.td:313 |
| 2528 | SDC2 = 2513, // MipsInstrInfo.td:2192 |
| 2529 | SDC2_MMR6 = 2514, // MicroMips32r6InstrInfo.td:1637 |
| 2530 | SDC2_R6 = 2515, // Mips32r6InstrInfo.td:986 |
| 2531 | SDC3 = 2516, // MipsInstrInfo.td:2209 |
| 2532 | SDIV = 2517, // MipsInstrInfo.td:2408 |
| 2533 | SDIV_MM = 2518, // MicroMipsInstrInfo.td:762 |
| 2534 | SDL = 2519, // Mips64InstrInfo.td:241 |
| 2535 | SDR = 2520, // Mips64InstrInfo.td:243 |
| 2536 | SDXC1 = 2521, // MipsInstrFPU.td:656 |
| 2537 | SDXC164 = 2522, // MipsInstrFPU.td:663 |
| 2538 | SEB = 2523, // MipsInstrInfo.td:2422 |
| 2539 | SEB64 = 2524, // Mips64InstrInfo.td:356 |
| 2540 | SEB_MM = 2525, // MicroMipsInstrInfo.td:932 |
| 2541 | SEH = 2526, // MipsInstrInfo.td:2424 |
| 2542 | SEH64 = 2527, // Mips64InstrInfo.td:358 |
| 2543 | SEH_MM = 2528, // MicroMipsInstrInfo.td:934 |
| 2544 | SELEQZ = 2529, // Mips32r6InstrInfo.td:974 |
| 2545 | SELEQZ64 = 2530, // Mips64r6InstrInfo.td:156 |
| 2546 | SELEQZ_D = 2531, // Mips32r6InstrInfo.td:976 |
| 2547 | SELEQZ_D_MMR6 = 2532, // MicroMips32r6InstrInfo.td:1604 |
| 2548 | SELEQZ_MMR6 = 2533, // MicroMips32r6InstrInfo.td:1428 |
| 2549 | SELEQZ_S = 2534, // Mips32r6InstrInfo.td:978 |
| 2550 | SELEQZ_S_MMR6 = 2535, // MicroMips32r6InstrInfo.td:1602 |
| 2551 | SELNEZ = 2536, // Mips32r6InstrInfo.td:975 |
| 2552 | SELNEZ64 = 2537, // Mips64r6InstrInfo.td:157 |
| 2553 | SELNEZ_D = 2538, // Mips32r6InstrInfo.td:980 |
| 2554 | SELNEZ_D_MMR6 = 2539, // MicroMips32r6InstrInfo.td:1608 |
| 2555 | SELNEZ_MMR6 = 2540, // MicroMips32r6InstrInfo.td:1430 |
| 2556 | SELNEZ_S = 2541, // Mips32r6InstrInfo.td:982 |
| 2557 | SELNEZ_S_MMR6 = 2542, // MicroMips32r6InstrInfo.td:1606 |
| 2558 | SEL_D = 2543, // Mips32r6InstrInfo.td:984 |
| 2559 | SEL_D_MMR6 = 2544, // MicroMips32r6InstrInfo.td:1601 |
| 2560 | SEL_S = 2545, // Mips32r6InstrInfo.td:985 |
| 2561 | SEL_S_MMR6 = 2546, // MicroMips32r6InstrInfo.td:1600 |
| 2562 | SEQ = 2547, // Mips64InstrInfo.td:580 |
| 2563 | SEQi = 2548, // Mips64InstrInfo.td:581 |
| 2564 | SH = 2549, // MipsInstrInfo.td:2168 |
| 2565 | SH16_MM = 2550, // MicroMipsInstrInfo.td:638 |
| 2566 | SH16_MMR6 = 2551, // MicroMips32r6InstrInfo.td:1432 |
| 2567 | SH64 = 2552, // Mips64InstrInfo.td:208 |
| 2568 | SHE = 2553, // MipsEVAInstrInfo.td:196 |
| 2569 | SHE_MM = 2554, // MicroMipsInstrInfo.td:832 |
| 2570 | SHF_B = 2555, // MipsMSAInstrInfo.td:3385 |
| 2571 | SHF_H = 2556, // MipsMSAInstrInfo.td:3386 |
| 2572 | SHF_W = 2557, // MipsMSAInstrInfo.td:3387 |
| 2573 | SHILO = 2558, // MipsDSPInstrInfo.td:1232 |
| 2574 | SHILOV = 2559, // MipsDSPInstrInfo.td:1233 |
| 2575 | SHILOV_MM = 2560, // MicroMipsDSPInstrInfo.td:515 |
| 2576 | SHILO_MM = 2561, // MicroMipsDSPInstrInfo.td:514 |
| 2577 | SHLLV_PH = 2562, // MipsDSPInstrInfo.td:1157 |
| 2578 | SHLLV_PH_MM = 2563, // MicroMipsDSPInstrInfo.td:438 |
| 2579 | SHLLV_QB = 2564, // MipsDSPInstrInfo.td:1153 |
| 2580 | SHLLV_QB_MM = 2565, // MicroMipsDSPInstrInfo.td:440 |
| 2581 | SHLLV_S_PH = 2566, // MipsDSPInstrInfo.td:1159 |
| 2582 | SHLLV_S_PH_MM = 2567, // MicroMipsDSPInstrInfo.td:439 |
| 2583 | SHLLV_S_W = 2568, // MipsDSPInstrInfo.td:1165 |
| 2584 | SHLLV_S_W_MM = 2569, // MicroMipsDSPInstrInfo.td:441 |
| 2585 | SHLL_PH = 2570, // MipsDSPInstrInfo.td:1156 |
| 2586 | SHLL_PH_MM = 2571, // MicroMipsDSPInstrInfo.td:435 |
| 2587 | SHLL_QB = 2572, // MipsDSPInstrInfo.td:1152 |
| 2588 | SHLL_QB_MM = 2573, // MicroMipsDSPInstrInfo.td:437 |
| 2589 | SHLL_S_PH = 2574, // MipsDSPInstrInfo.td:1158 |
| 2590 | SHLL_S_PH_MM = 2575, // MicroMipsDSPInstrInfo.td:436 |
| 2591 | SHLL_S_W = 2576, // MipsDSPInstrInfo.td:1164 |
| 2592 | SHLL_S_W_MM = 2577, // MicroMipsDSPInstrInfo.td:442 |
| 2593 | SHRAV_PH = 2578, // MipsDSPInstrInfo.td:1161 |
| 2594 | SHRAV_PH_MM = 2579, // MicroMipsDSPInstrInfo.td:445 |
| 2595 | SHRAV_QB = 2580, // MipsDSPInstrInfo.td:1279 |
| 2596 | SHRAV_QB_MMR2 = 2581, // MicroMipsDSPInstrInfo.td:551 |
| 2597 | SHRAV_R_PH = 2582, // MipsDSPInstrInfo.td:1163 |
| 2598 | SHRAV_R_PH_MM = 2583, // MicroMipsDSPInstrInfo.td:446 |
| 2599 | SHRAV_R_QB = 2584, // MipsDSPInstrInfo.td:1281 |
| 2600 | SHRAV_R_QB_MMR2 = 2585, // MicroMipsDSPInstrInfo.td:552 |
| 2601 | SHRAV_R_W = 2586, // MipsDSPInstrInfo.td:1167 |
| 2602 | SHRAV_R_W_MM = 2587, // MicroMipsDSPInstrInfo.td:447 |
| 2603 | SHRA_PH = 2588, // MipsDSPInstrInfo.td:1160 |
| 2604 | SHRA_PH_MM = 2589, // MicroMipsDSPInstrInfo.td:443 |
| 2605 | SHRA_QB = 2590, // MipsDSPInstrInfo.td:1278 |
| 2606 | SHRA_QB_MMR2 = 2591, // MicroMipsDSPInstrInfo.td:548 |
| 2607 | SHRA_R_PH = 2592, // MipsDSPInstrInfo.td:1162 |
| 2608 | SHRA_R_PH_MM = 2593, // MicroMipsDSPInstrInfo.td:444 |
| 2609 | SHRA_R_QB = 2594, // MipsDSPInstrInfo.td:1280 |
| 2610 | SHRA_R_QB_MMR2 = 2595, // MicroMipsDSPInstrInfo.td:549 |
| 2611 | SHRA_R_W = 2596, // MipsDSPInstrInfo.td:1166 |
| 2612 | SHRA_R_W_MM = 2597, // MicroMipsDSPInstrInfo.td:448 |
| 2613 | SHRLV_PH = 2598, // MipsDSPInstrInfo.td:1283 |
| 2614 | SHRLV_PH_MMR2 = 2599, // MicroMipsDSPInstrInfo.td:562 |
| 2615 | SHRLV_QB = 2600, // MipsDSPInstrInfo.td:1155 |
| 2616 | SHRLV_QB_MM = 2601, // MicroMipsDSPInstrInfo.td:450 |
| 2617 | SHRL_PH = 2602, // MipsDSPInstrInfo.td:1282 |
| 2618 | SHRL_PH_MMR2 = 2603, // MicroMipsDSPInstrInfo.td:561 |
| 2619 | SHRL_QB = 2604, // MipsDSPInstrInfo.td:1154 |
| 2620 | SHRL_QB_MM = 2605, // MicroMipsDSPInstrInfo.td:449 |
| 2621 | SH_MM = 2606, // MicroMipsInstrInfo.td:809 |
| 2622 | SH_MMR6 = 2607, // MicroMips32r6InstrInfo.td:1546 |
| 2623 | SIGRIE = 2608, // Mips32r6InstrInfo.td:988 |
| 2624 | SIGRIE_MMR6 = 2609, // MicroMips32r6InstrInfo.td:1453 |
| 2625 | SLDI_B = 2610, // MipsMSAInstrInfo.td:3394 |
| 2626 | SLDI_D = 2611, // MipsMSAInstrInfo.td:3397 |
| 2627 | SLDI_H = 2612, // MipsMSAInstrInfo.td:3395 |
| 2628 | SLDI_W = 2613, // MipsMSAInstrInfo.td:3396 |
| 2629 | SLD_B = 2614, // MipsMSAInstrInfo.td:3389 |
| 2630 | SLD_D = 2615, // MipsMSAInstrInfo.td:3392 |
| 2631 | SLD_H = 2616, // MipsMSAInstrInfo.td:3390 |
| 2632 | SLD_W = 2617, // MipsMSAInstrInfo.td:3391 |
| 2633 | SLL = 2618, // MipsInstrInfo.td:2132 |
| 2634 | SLL16_MM = 2619, // MicroMipsInstrInfo.td:618 |
| 2635 | SLL16_MMR6 = 2620, // MicroMips32r6InstrInfo.td:1559 |
| 2636 | SLL64_32 = 2621, // Mips64InstrInfo.td:430 |
| 2637 | SLL64_64 = 2622, // Mips64InstrInfo.td:432 |
| 2638 | SLLI_B = 2623, // MipsMSAInstrInfo.td:3404 |
| 2639 | SLLI_D = 2624, // MipsMSAInstrInfo.td:3407 |
| 2640 | SLLI_H = 2625, // MipsMSAInstrInfo.td:3405 |
| 2641 | SLLI_W = 2626, // MipsMSAInstrInfo.td:3406 |
| 2642 | SLLV = 2627, // MipsInstrInfo.td:2138 |
| 2643 | SLLV_MM = 2628, // MicroMipsInstrInfo.td:778 |
| 2644 | SLL_B = 2629, // MipsMSAInstrInfo.td:3399 |
| 2645 | SLL_D = 2630, // MipsMSAInstrInfo.td:3402 |
| 2646 | SLL_H = 2631, // MipsMSAInstrInfo.td:3400 |
| 2647 | SLL_MM = 2632, // MicroMipsInstrInfo.td:772 |
| 2648 | SLL_MMR6 = 2633, // MicroMips32r6InstrInfo.td:1433 |
| 2649 | SLL_W = 2634, // MipsMSAInstrInfo.td:3401 |
| 2650 | SLT = 2635, // MipsInstrInfo.td:2116 |
| 2651 | SLT64 = 2636, // Mips64InstrInfo.td:154 |
| 2652 | SLT_MM = 2637, // MicroMipsInstrInfo.td:746 |
| 2653 | SLTi = 2638, // MipsInstrInfo.td:2093 |
| 2654 | SLTi64 = 2639, // Mips64InstrInfo.td:128 |
| 2655 | SLTi_MM = 2640, // MicroMipsInstrInfo.td:716 |
| 2656 | SLTiu = 2641, // MipsInstrInfo.td:2095 |
| 2657 | SLTiu64 = 2642, // Mips64InstrInfo.td:130 |
| 2658 | SLTiu_MM = 2643, // MicroMipsInstrInfo.td:718 |
| 2659 | SLTu = 2644, // MipsInstrInfo.td:2118 |
| 2660 | SLTu64 = 2645, // Mips64InstrInfo.td:155 |
| 2661 | SLTu_MM = 2646, // MicroMipsInstrInfo.td:748 |
| 2662 | SNE = 2647, // Mips64InstrInfo.td:582 |
| 2663 | SNEi = 2648, // Mips64InstrInfo.td:583 |
| 2664 | SPLATI_B = 2649, // MipsMSAInstrInfo.td:3414 |
| 2665 | SPLATI_D = 2650, // MipsMSAInstrInfo.td:3417 |
| 2666 | SPLATI_H = 2651, // MipsMSAInstrInfo.td:3415 |
| 2667 | SPLATI_W = 2652, // MipsMSAInstrInfo.td:3416 |
| 2668 | SPLAT_B = 2653, // MipsMSAInstrInfo.td:3409 |
| 2669 | SPLAT_D = 2654, // MipsMSAInstrInfo.td:3412 |
| 2670 | SPLAT_H = 2655, // MipsMSAInstrInfo.td:3410 |
| 2671 | SPLAT_W = 2656, // MipsMSAInstrInfo.td:3411 |
| 2672 | SRA = 2657, // MipsInstrInfo.td:2136 |
| 2673 | SRAI_B = 2658, // MipsMSAInstrInfo.td:3424 |
| 2674 | SRAI_D = 2659, // MipsMSAInstrInfo.td:3427 |
| 2675 | SRAI_H = 2660, // MipsMSAInstrInfo.td:3425 |
| 2676 | SRAI_W = 2661, // MipsMSAInstrInfo.td:3426 |
| 2677 | SRARI_B = 2662, // MipsMSAInstrInfo.td:3434 |
| 2678 | SRARI_D = 2663, // MipsMSAInstrInfo.td:3437 |
| 2679 | SRARI_H = 2664, // MipsMSAInstrInfo.td:3435 |
| 2680 | SRARI_W = 2665, // MipsMSAInstrInfo.td:3436 |
| 2681 | SRAR_B = 2666, // MipsMSAInstrInfo.td:3429 |
| 2682 | SRAR_D = 2667, // MipsMSAInstrInfo.td:3432 |
| 2683 | SRAR_H = 2668, // MipsMSAInstrInfo.td:3430 |
| 2684 | SRAR_W = 2669, // MipsMSAInstrInfo.td:3431 |
| 2685 | SRAV = 2670, // MipsInstrInfo.td:2142 |
| 2686 | SRAV_MM = 2671, // MicroMipsInstrInfo.td:782 |
| 2687 | SRA_B = 2672, // MipsMSAInstrInfo.td:3419 |
| 2688 | SRA_D = 2673, // MipsMSAInstrInfo.td:3422 |
| 2689 | SRA_H = 2674, // MipsMSAInstrInfo.td:3420 |
| 2690 | SRA_MM = 2675, // MicroMipsInstrInfo.td:776 |
| 2691 | SRA_W = 2676, // MipsMSAInstrInfo.td:3421 |
| 2692 | SRL = 2677, // MipsInstrInfo.td:2134 |
| 2693 | SRL16_MM = 2678, // MicroMipsInstrInfo.td:620 |
| 2694 | SRL16_MMR6 = 2679, // MicroMips32r6InstrInfo.td:1561 |
| 2695 | SRLI_B = 2680, // MipsMSAInstrInfo.td:3444 |
| 2696 | SRLI_D = 2681, // MipsMSAInstrInfo.td:3447 |
| 2697 | SRLI_H = 2682, // MipsMSAInstrInfo.td:3445 |
| 2698 | SRLI_W = 2683, // MipsMSAInstrInfo.td:3446 |
| 2699 | SRLRI_B = 2684, // MipsMSAInstrInfo.td:3454 |
| 2700 | SRLRI_D = 2685, // MipsMSAInstrInfo.td:3457 |
| 2701 | SRLRI_H = 2686, // MipsMSAInstrInfo.td:3455 |
| 2702 | SRLRI_W = 2687, // MipsMSAInstrInfo.td:3456 |
| 2703 | SRLR_B = 2688, // MipsMSAInstrInfo.td:3449 |
| 2704 | SRLR_D = 2689, // MipsMSAInstrInfo.td:3452 |
| 2705 | SRLR_H = 2690, // MipsMSAInstrInfo.td:3450 |
| 2706 | SRLR_W = 2691, // MipsMSAInstrInfo.td:3451 |
| 2707 | SRLV = 2692, // MipsInstrInfo.td:2140 |
| 2708 | SRLV_MM = 2693, // MicroMipsInstrInfo.td:780 |
| 2709 | SRL_B = 2694, // MipsMSAInstrInfo.td:3439 |
| 2710 | SRL_D = 2695, // MipsMSAInstrInfo.td:3442 |
| 2711 | SRL_H = 2696, // MipsMSAInstrInfo.td:3440 |
| 2712 | SRL_MM = 2697, // MicroMipsInstrInfo.td:774 |
| 2713 | SRL_W = 2698, // MipsMSAInstrInfo.td:3441 |
| 2714 | SSNOP = 2699, // MipsInstrInfo.td:2508 |
| 2715 | SSNOP_MM = 2700, // MicroMipsInstrInfo.td:1072 |
| 2716 | SSNOP_MMR6 = 2701, // MicroMips32r6InstrInfo.td:1447 |
| 2717 | ST_B = 2702, // MipsMSAInstrInfo.td:3459 |
| 2718 | ST_D = 2703, // MipsMSAInstrInfo.td:3462 |
| 2719 | ST_H = 2704, // MipsMSAInstrInfo.td:3460 |
| 2720 | ST_W = 2705, // MipsMSAInstrInfo.td:3461 |
| 2721 | SUB = 2706, // MipsInstrInfo.td:2113 |
| 2722 | SUBQH_PH = 2707, // MipsDSPInstrInfo.td:1255 |
| 2723 | SUBQH_PH_MMR2 = 2708, // MicroMipsDSPInstrInfo.td:563 |
| 2724 | SUBQH_R_PH = 2709, // MipsDSPInstrInfo.td:1256 |
| 2725 | SUBQH_R_PH_MMR2 = 2710, // MicroMipsDSPInstrInfo.td:564 |
| 2726 | SUBQH_R_W = 2711, // MipsDSPInstrInfo.td:1260 |
| 2727 | SUBQH_R_W_MMR2 = 2712, // MicroMipsDSPInstrInfo.td:566 |
| 2728 | SUBQH_W = 2713, // MipsDSPInstrInfo.td:1259 |
| 2729 | SUBQH_W_MMR2 = 2714, // MicroMipsDSPInstrInfo.td:565 |
| 2730 | SUBQ_PH = 2715, // MipsDSPInstrInfo.td:1128 |
| 2731 | SUBQ_PH_MM = 2716, // MicroMipsDSPInstrInfo.td:463 |
| 2732 | SUBQ_S_PH = 2717, // MipsDSPInstrInfo.td:1129 |
| 2733 | SUBQ_S_PH_MM = 2718, // MicroMipsDSPInstrInfo.td:464 |
| 2734 | SUBQ_S_W = 2719, // MipsDSPInstrInfo.td:1131 |
| 2735 | SUBQ_S_W_MM = 2720, // MicroMipsDSPInstrInfo.td:465 |
| 2736 | SUBSUS_U_B = 2721, // MipsMSAInstrInfo.td:3474 |
| 2737 | SUBSUS_U_D = 2722, // MipsMSAInstrInfo.td:3477 |
| 2738 | SUBSUS_U_H = 2723, // MipsMSAInstrInfo.td:3475 |
| 2739 | SUBSUS_U_W = 2724, // MipsMSAInstrInfo.td:3476 |
| 2740 | SUBSUU_S_B = 2725, // MipsMSAInstrInfo.td:3479 |
| 2741 | SUBSUU_S_D = 2726, // MipsMSAInstrInfo.td:3482 |
| 2742 | SUBSUU_S_H = 2727, // MipsMSAInstrInfo.td:3480 |
| 2743 | SUBSUU_S_W = 2728, // MipsMSAInstrInfo.td:3481 |
| 2744 | SUBS_S_B = 2729, // MipsMSAInstrInfo.td:3464 |
| 2745 | SUBS_S_D = 2730, // MipsMSAInstrInfo.td:3467 |
| 2746 | SUBS_S_H = 2731, // MipsMSAInstrInfo.td:3465 |
| 2747 | SUBS_S_W = 2732, // MipsMSAInstrInfo.td:3466 |
| 2748 | SUBS_U_B = 2733, // MipsMSAInstrInfo.td:3469 |
| 2749 | SUBS_U_D = 2734, // MipsMSAInstrInfo.td:3472 |
| 2750 | SUBS_U_H = 2735, // MipsMSAInstrInfo.td:3470 |
| 2751 | SUBS_U_W = 2736, // MipsMSAInstrInfo.td:3471 |
| 2752 | SUBU16_MM = 2737, // MicroMipsInstrInfo.td:624 |
| 2753 | SUBU16_MMR6 = 2738, // MicroMips32r6InstrInfo.td:1573 |
| 2754 | SUBUH_QB = 2739, // MipsDSPInstrInfo.td:1251 |
| 2755 | SUBUH_QB_MMR2 = 2740, // MicroMipsDSPInstrInfo.td:569 |
| 2756 | SUBUH_R_QB = 2741, // MipsDSPInstrInfo.td:1252 |
| 2757 | SUBUH_R_QB_MMR2 = 2742, // MicroMipsDSPInstrInfo.td:570 |
| 2758 | SUBU_MMR6 = 2743, // MicroMips32r6InstrInfo.td:1435 |
| 2759 | SUBU_PH = 2744, // MipsDSPInstrInfo.td:1243 |
| 2760 | SUBU_PH_MMR2 = 2745, // MicroMipsDSPInstrInfo.td:567 |
| 2761 | SUBU_QB = 2746, // MipsDSPInstrInfo.td:1124 |
| 2762 | SUBU_QB_MM = 2747, // MicroMipsDSPInstrInfo.td:466 |
| 2763 | SUBU_S_PH = 2748, // MipsDSPInstrInfo.td:1244 |
| 2764 | SUBU_S_PH_MMR2 = 2749, // MicroMipsDSPInstrInfo.td:568 |
| 2765 | SUBU_S_QB = 2750, // MipsDSPInstrInfo.td:1125 |
| 2766 | SUBU_S_QB_MM = 2751, // MicroMipsDSPInstrInfo.td:467 |
| 2767 | SUBVI_B = 2752, // MipsMSAInstrInfo.td:3489 |
| 2768 | SUBVI_D = 2753, // MipsMSAInstrInfo.td:3492 |
| 2769 | SUBVI_H = 2754, // MipsMSAInstrInfo.td:3490 |
| 2770 | SUBVI_W = 2755, // MipsMSAInstrInfo.td:3491 |
| 2771 | SUBV_B = 2756, // MipsMSAInstrInfo.td:3484 |
| 2772 | SUBV_D = 2757, // MipsMSAInstrInfo.td:3487 |
| 2773 | SUBV_H = 2758, // MipsMSAInstrInfo.td:3485 |
| 2774 | SUBV_W = 2759, // MipsMSAInstrInfo.td:3486 |
| 2775 | SUB_MM = 2760, // MicroMipsInstrInfo.td:744 |
| 2776 | SUB_MMR6 = 2761, // MicroMips32r6InstrInfo.td:1434 |
| 2777 | SUBu = 2762, // MipsInstrInfo.td:2104 |
| 2778 | SUBu_MM = 2763, // MicroMipsInstrInfo.td:737 |
| 2779 | SUXC1 = 2764, // MipsInstrFPU.td:672 |
| 2780 | SUXC164 = 2765, // MipsInstrFPU.td:680 |
| 2781 | SUXC1_MM = 2766, // MicroMipsInstrFPU.td:53 |
| 2782 | SW = 2767, // MipsInstrInfo.td:2170 |
| 2783 | SW16_MM = 2768, // MicroMipsInstrInfo.td:641 |
| 2784 | SW16_MMR6 = 2769, // MicroMips32r6InstrInfo.td:1436 |
| 2785 | SW64 = 2770, // Mips64InstrInfo.td:210 |
| 2786 | SWC1 = 2771, // MipsInstrFPU.td:623 |
| 2787 | SWC1_MM = 2772, // MicroMipsInstrFPU.td:304 |
| 2788 | SWC2 = 2773, // MipsInstrInfo.td:2188 |
| 2789 | SWC2_MMR6 = 2774, // MicroMips32r6InstrInfo.td:1639 |
| 2790 | SWC2_R6 = 2775, // Mips32r6InstrInfo.td:987 |
| 2791 | SWC3 = 2776, // MipsInstrInfo.td:2201 |
| 2792 | SWDSP = 2777, // MipsDSPInstrInfo.td:1302 |
| 2793 | SWDSP_MM = 2778, // MicroMipsDSPInstrInfo.td:410 |
| 2794 | SWE = 2779, // MipsEVAInstrInfo.td:197 |
| 2795 | SWE_MM = 2780, // MicroMipsInstrInfo.td:835 |
| 2796 | SWL = 2781, // MipsInstrInfo.td:2180 |
| 2797 | SWL64 = 2782, // Mips64InstrInfo.td:231 |
| 2798 | SWLE = 2783, // MipsEVAInstrInfo.td:202 |
| 2799 | SWLE_MM = 2784, // MicroMipsInstrInfo.td:846 |
| 2800 | SWL_MM = 2785, // MicroMipsInstrInfo.td:866 |
| 2801 | SWM16_MM = 2786, // MicroMipsInstrInfo.td:694 |
| 2802 | SWM16_MMR6 = 2787, // MicroMips32r6InstrInfo.td:1437 |
| 2803 | SWM32_MM = 2788, // MicroMipsInstrInfo.td:874 |
| 2804 | SWP_MM = 2789, // MicroMipsInstrInfo.td:878 |
| 2805 | SWR = 2790, // MipsInstrInfo.td:2182 |
| 2806 | SWR64 = 2791, // Mips64InstrInfo.td:233 |
| 2807 | SWRE = 2792, // MipsEVAInstrInfo.td:203 |
| 2808 | SWRE_MM = 2793, // MicroMipsInstrInfo.td:850 |
| 2809 | SWR_MM = 2794, // MicroMipsInstrInfo.td:869 |
| 2810 | SWSP_MM = 2795, // MicroMipsInstrInfo.td:648 |
| 2811 | SWSP_MMR6 = 2796, // MicroMips32r6InstrInfo.td:1438 |
| 2812 | SWXC1 = 2797, // MipsInstrFPU.td:650 |
| 2813 | SWXC1_MM = 2798, // MicroMipsInstrFPU.td:48 |
| 2814 | SW_MM = 2799, // MicroMipsInstrInfo.td:811 |
| 2815 | SW_MMR6 = 2800, // MicroMips32r6InstrInfo.td:1458 |
| 2816 | SYNC = 2801, // MipsInstrInfo.td:2215 |
| 2817 | SYNCI = 2802, // MipsInstrInfo.td:2216 |
| 2818 | SYNCI_MM = 2803, // MicroMipsInstrInfo.td:1005 |
| 2819 | SYNCI_MMR6 = 2804, // MicroMips32r6InstrInfo.td:1449 |
| 2820 | SYNC_MM = 2805, // MicroMipsInstrInfo.td:1003 |
| 2821 | SYNC_MMR6 = 2806, // MicroMips32r6InstrInfo.td:1448 |
| 2822 | SYSCALL = 2807, // MipsInstrInfo.td:2250 |
| 2823 | SYSCALL_MM = 2808, // MicroMipsInstrInfo.td:1008 |
| 2824 | Save16 = 2809, // Mips16InstrInfo.td:991 |
| 2825 | SaveX16 = 2810, // Mips16InstrInfo.td:999 |
| 2826 | SbRxRyOffMemX16 = 2811, // Mips16InstrInfo.td:1012 |
| 2827 | SebRx16 = 2812, // Mips16InstrInfo.td:1020 |
| 2828 | SehRx16 = 2813, // Mips16InstrInfo.td:1028 |
| 2829 | ShRxRyOffMemX16 = 2814, // Mips16InstrInfo.td:1151 |
| 2830 | SllX16 = 2815, // Mips16InstrInfo.td:1159 |
| 2831 | SllvRxRy16 = 2816, // Mips16InstrInfo.td:1166 |
| 2832 | SltRxRy16 = 2817, // Mips16InstrInfo.td:1219 |
| 2833 | SltiRxImm16 = 2818, // Mips16InstrInfo.td:1173 |
| 2834 | SltiRxImmX16 = 2819, // Mips16InstrInfo.td:1183 |
| 2835 | SltiuRxImm16 = 2820, // Mips16InstrInfo.td:1194 |
| 2836 | SltiuRxImmX16 = 2821, // Mips16InstrInfo.td:1204 |
| 2837 | SltuRxRy16 = 2822, // Mips16InstrInfo.td:1229 |
| 2838 | SraX16 = 2823, // Mips16InstrInfo.td:1255 |
| 2839 | SravRxRy16 = 2824, // Mips16InstrInfo.td:1246 |
| 2840 | SrlX16 = 2825, // Mips16InstrInfo.td:1273 |
| 2841 | SrlvRxRy16 = 2826, // Mips16InstrInfo.td:1264 |
| 2842 | SubuRxRyRz16 = 2827, // Mips16InstrInfo.td:1280 |
| 2843 | SwRxRyOffMemX16 = 2828, // Mips16InstrInfo.td:1288 |
| 2844 | SwRxSpImmX16 = 2829, // Mips16InstrInfo.td:1296 |
| 2845 | TEQ = 2830, // MipsInstrInfo.td:2221 |
| 2846 | TEQI = 2831, // MipsInstrInfo.td:2234 |
| 2847 | TEQI_MM = 2832, // MicroMipsInstrInfo.td:1035 |
| 2848 | TEQ_MM = 2833, // MicroMipsInstrInfo.td:1022 |
| 2849 | TGE = 2834, // MipsInstrInfo.td:2223 |
| 2850 | TGEI = 2835, // MipsInstrInfo.td:2236 |
| 2851 | TGEIU = 2836, // MipsInstrInfo.td:2238 |
| 2852 | TGEIU_MM = 2837, // MicroMipsInstrInfo.td:1039 |
| 2853 | TGEI_MM = 2838, // MicroMipsInstrInfo.td:1037 |
| 2854 | TGEU = 2839, // MipsInstrInfo.td:2225 |
| 2855 | TGEU_MM = 2840, // MicroMipsInstrInfo.td:1026 |
| 2856 | TGE_MM = 2841, // MicroMipsInstrInfo.td:1024 |
| 2857 | TLBGINV = 2842, // MipsInstrInfo.td:2706 |
| 2858 | TLBGINVF = 2843, // MipsInstrInfo.td:2708 |
| 2859 | TLBGINVF_MM = 2844, // MicroMipsInstrInfo.td:1148 |
| 2860 | TLBGINV_MM = 2845, // MicroMipsInstrInfo.td:1146 |
| 2861 | TLBGP = 2846, // MipsInstrInfo.td:2710 |
| 2862 | TLBGP_MM = 2847, // MicroMipsInstrInfo.td:1150 |
| 2863 | TLBGR = 2848, // MipsInstrInfo.td:2712 |
| 2864 | TLBGR_MM = 2849, // MicroMipsInstrInfo.td:1152 |
| 2865 | TLBGWI = 2850, // MipsInstrInfo.td:2714 |
| 2866 | TLBGWI_MM = 2851, // MicroMipsInstrInfo.td:1154 |
| 2867 | TLBGWR = 2852, // MipsInstrInfo.td:2716 |
| 2868 | TLBGWR_MM = 2853, // MicroMipsInstrInfo.td:1156 |
| 2869 | TLBINV = 2854, // MipsEVAInstrInfo.td:210 |
| 2870 | TLBINVF = 2855, // MipsEVAInstrInfo.td:211 |
| 2871 | TLBINVF_MMR6 = 2856, // MicroMips32r6InstrInfo.td:1616 |
| 2872 | TLBINV_MMR6 = 2857, // MicroMips32r6InstrInfo.td:1614 |
| 2873 | TLBP = 2858, // MipsInstrInfo.td:2574 |
| 2874 | TLBP_MM = 2859, // MicroMipsInstrInfo.td:1079 |
| 2875 | TLBR = 2860, // MipsInstrInfo.td:2575 |
| 2876 | TLBR_MM = 2861, // MicroMipsInstrInfo.td:1081 |
| 2877 | TLBWI = 2862, // MipsInstrInfo.td:2576 |
| 2878 | TLBWI_MM = 2863, // MicroMipsInstrInfo.td:1083 |
| 2879 | TLBWR = 2864, // MipsInstrInfo.td:2577 |
| 2880 | TLBWR_MM = 2865, // MicroMipsInstrInfo.td:1085 |
| 2881 | TLT = 2866, // MipsInstrInfo.td:2227 |
| 2882 | TLTI = 2867, // MipsInstrInfo.td:2240 |
| 2883 | TLTIU_MM = 2868, // MicroMipsInstrInfo.td:1043 |
| 2884 | TLTI_MM = 2869, // MicroMipsInstrInfo.td:1041 |
| 2885 | TLTU = 2870, // MipsInstrInfo.td:2229 |
| 2886 | TLTU_MM = 2871, // MicroMipsInstrInfo.td:1030 |
| 2887 | TLT_MM = 2872, // MicroMipsInstrInfo.td:1028 |
| 2888 | TNE = 2873, // MipsInstrInfo.td:2231 |
| 2889 | TNEI = 2874, // MipsInstrInfo.td:2244 |
| 2890 | TNEI_MM = 2875, // MicroMipsInstrInfo.td:1045 |
| 2891 | TNE_MM = 2876, // MicroMipsInstrInfo.td:1032 |
| 2892 | TRUNC_L_D64 = 2877, // MipsInstrFPU.td:445 |
| 2893 | TRUNC_L_D_MMR6 = 2878, // MicroMips32r6InstrInfo.td:1538 |
| 2894 | TRUNC_L_S = 2879, // MipsInstrFPU.td:443 |
| 2895 | TRUNC_L_S_MMR6 = 2880, // MicroMips32r6InstrInfo.td:1536 |
| 2896 | TRUNC_W_D32 = 2881, // MipsInstrFPU.td:166 |
| 2897 | TRUNC_W_D64 = 2882, // MipsInstrFPU.td:167 |
| 2898 | TRUNC_W_D_MMR6 = 2883, // MicroMips32r6InstrInfo.td:1542 |
| 2899 | TRUNC_W_MM = 2884, // MicroMipsInstrFPU.td:98 |
| 2900 | TRUNC_W_S = 2885, // MipsInstrFPU.td:393 |
| 2901 | TRUNC_W_S_MM = 2886, // MicroMipsInstrFPU.td:232 |
| 2902 | TRUNC_W_S_MMR6 = 2887, // MicroMips32r6InstrInfo.td:1540 |
| 2903 | TTLTIU = 2888, // MipsInstrInfo.td:2242 |
| 2904 | UDIV = 2889, // MipsInstrInfo.td:2410 |
| 2905 | UDIV_MM = 2890, // MicroMipsInstrInfo.td:764 |
| 2906 | V3MULU = 2891, // Mips64InstrInfo.td:586 |
| 2907 | VMM0 = 2892, // Mips64InstrInfo.td:592 |
| 2908 | VMULU = 2893, // Mips64InstrInfo.td:598 |
| 2909 | VSHF_B = 2894, // MipsMSAInstrInfo.td:3494 |
| 2910 | VSHF_D = 2895, // MipsMSAInstrInfo.td:3497 |
| 2911 | VSHF_H = 2896, // MipsMSAInstrInfo.td:3495 |
| 2912 | VSHF_W = 2897, // MipsMSAInstrInfo.td:3496 |
| 2913 | WAIT = 2898, // MipsInstrInfo.td:2266 |
| 2914 | WAIT_MM = 2899, // MicroMipsInstrInfo.td:1010 |
| 2915 | WAIT_MMR6 = 2900, // MicroMips32r6InstrInfo.td:1446 |
| 2916 | WRDSP = 2901, // MipsDSPInstrInfo.td:1237 |
| 2917 | WRDSP_MM = 2902, // MicroMipsDSPInstrInfo.td:516 |
| 2918 | WRPGPR_MMR6 = 2903, // MicroMips32r6InstrInfo.td:1439 |
| 2919 | WSBH = 2904, // MipsInstrInfo.td:2434 |
| 2920 | WSBH_MM = 2905, // MicroMipsInstrInfo.td:938 |
| 2921 | WSBH_MMR6 = 2906, // MicroMips32r6InstrInfo.td:1441 |
| 2922 | XOR = 2907, // MipsInstrInfo.td:2124 |
| 2923 | XOR16_MM = 2908, // MicroMipsInstrInfo.td:626 |
| 2924 | XOR16_MMR6 = 2909, // MicroMips32r6InstrInfo.td:1575 |
| 2925 | XOR64 = 2910, // Mips64InstrInfo.td:160 |
| 2926 | XORI_B = 2911, // MipsMSAInstrInfo.td:3513 |
| 2927 | XORI_MMR6 = 2912, // MicroMips32r6InstrInfo.td:1456 |
| 2928 | XOR_MM = 2913, // MicroMipsInstrInfo.td:754 |
| 2929 | XOR_MMR6 = 2914, // MicroMips32r6InstrInfo.td:1455 |
| 2930 | XOR_V = 2915, // MipsMSAInstrInfo.td:3499 |
| 2931 | XORi = 2916, // MipsInstrInfo.td:2088 |
| 2932 | XORi64 = 2917, // Mips64InstrInfo.td:136 |
| 2933 | XORi_MM = 2918, // MicroMipsInstrInfo.td:725 |
| 2934 | XorRxRxRy16 = 2919, // Mips16InstrInfo.td:1304 |
| 2935 | YIELD = 2920, // MipsMTInstrInfo.td:107 |
| 2936 | INSTRUCTION_LIST_END = 2921 |
| 2937 | }; |
| 2938 | enum RegClassByHwModeUses : uint16_t { |
| 2939 | mips_ptr_rc, |
| 2940 | ptr_gp_rc, |
| 2941 | ptr_gpr16mm_rc, |
| 2942 | ptr_sp_rc, |
| 2943 | }; |
| 2944 | |
| 2945 | } // namespace llvm::Mips |
| 2946 | |
| 2947 | #endif // GET_INSTRINFO_ENUM |
| 2948 | |
| 2949 | #ifdef GET_INSTRINFO_SCHED_ENUM |
| 2950 | #undef GET_INSTRINFO_SCHED_ENUM |
| 2951 | |
| 2952 | namespace llvm::Mips::Sched { |
| 2953 | |
| 2954 | enum { |
| 2955 | NoInstrModel = 0, |
| 2956 | IIPseudo = 1, |
| 2957 | II_B = 2, |
| 2958 | II_BCCZAL = 3, |
| 2959 | II_MTC1 = 4, |
| 2960 | II_MFC1 = 5, |
| 2961 | II_JALR = 6, |
| 2962 | II_JAL = 7, |
| 2963 | II_CVT = 8, |
| 2964 | II_DMULT = 9, |
| 2965 | II_DMULTU = 10, |
| 2966 | II_DDIV = 11, |
| 2967 | II_DDIVU = 12, |
| 2968 | II_IndirectBranchPseudo = 13, |
| 2969 | II_MADD = 14, |
| 2970 | II_MADDU = 15, |
| 2971 | II_MFHI_MFLO = 16, |
| 2972 | II_MSUB = 17, |
| 2973 | II_MSUBU = 18, |
| 2974 | II_MTHI_MTLO = 19, |
| 2975 | II_MULT = 20, |
| 2976 | II_MULTU = 21, |
| 2977 | II_ReturnPseudo = 22, |
| 2978 | II_DIV = 23, |
| 2979 | II_DIVU = 24, |
| 2980 | II_J = 25, |
| 2981 | II_JR = 26, |
| 2982 | II_TRAP = 27, |
| 2983 | II_ADD = 28, |
| 2984 | II_ADDIUPC = 29, |
| 2985 | II_ADDIU = 30, |
| 2986 | II_ADDR_PS = 31, |
| 2987 | II_ADDU = 32, |
| 2988 | II_ADDI = 33, |
| 2989 | II_ALIGN = 34, |
| 2990 | II_ALUIPC = 35, |
| 2991 | II_AND = 36, |
| 2992 | II_ANDI = 37, |
| 2993 | II_AUI = 38, |
| 2994 | II_AUIPC = 39, |
| 2995 | IIM16Alu = 40, |
| 2996 | II_BADDU = 41, |
| 2997 | II_BC = 42, |
| 2998 | II_BALC = 43, |
| 2999 | II_BBIT = 44, |
| 3000 | II_BC1CCZ = 45, |
| 3001 | II_BC1F = 46, |
| 3002 | II_BC1FL = 47, |
| 3003 | II_BC1T = 48, |
| 3004 | II_BC1TL = 49, |
| 3005 | II_BC2CCZ = 50, |
| 3006 | II_BCC = 51, |
| 3007 | II_BCCC = 52, |
| 3008 | II_BCCZ = 53, |
| 3009 | II_BCCZC = 54, |
| 3010 | II_BCCZALS = 55, |
| 3011 | II_BITSWAP = 56, |
| 3012 | II_BREAK = 57, |
| 3013 | II_CACHE = 58, |
| 3014 | II_CACHEE = 59, |
| 3015 | II_CEIL = 60, |
| 3016 | II_CFC1 = 61, |
| 3017 | II_CFC2 = 62, |
| 3018 | II_INS = 63, |
| 3019 | II_CLASS_D = 64, |
| 3020 | II_CLASS_S = 65, |
| 3021 | II_CLO = 66, |
| 3022 | II_CLZ = 67, |
| 3023 | II_CMP_CC_D = 68, |
| 3024 | II_CMP_CC_S = 69, |
| 3025 | II_CRC32B = 70, |
| 3026 | II_CRC32CB = 71, |
| 3027 | II_CRC32CD = 72, |
| 3028 | II_CRC32CH = 73, |
| 3029 | II_CRC32CW = 74, |
| 3030 | II_CRC32D = 75, |
| 3031 | II_CRC32H = 76, |
| 3032 | II_CRC32W = 77, |
| 3033 | II_CTC1 = 78, |
| 3034 | II_CTC2 = 79, |
| 3035 | II_C_CC_D = 80, |
| 3036 | II_C_CC_S = 81, |
| 3037 | II_DADD = 82, |
| 3038 | II_DADDI = 83, |
| 3039 | II_DADDIU = 84, |
| 3040 | II_DADDU = 85, |
| 3041 | II_DAHI = 86, |
| 3042 | II_DALIGN = 87, |
| 3043 | II_DATI = 88, |
| 3044 | II_DAUI = 89, |
| 3045 | II_DBITSWAP = 90, |
| 3046 | II_DCLO = 91, |
| 3047 | II_DCLZ = 92, |
| 3048 | II_DERET = 93, |
| 3049 | II_EXT = 94, |
| 3050 | II_DI = 95, |
| 3051 | II_DLSA = 96, |
| 3052 | II_DMFC0 = 97, |
| 3053 | II_DMFC1 = 98, |
| 3054 | II_DMFC2 = 99, |
| 3055 | II_DMFGC0 = 100, |
| 3056 | II_DMOD = 101, |
| 3057 | II_DMODU = 102, |
| 3058 | II_DMT = 103, |
| 3059 | II_DMTC0 = 104, |
| 3060 | II_DMTC1 = 105, |
| 3061 | II_DMTC2 = 106, |
| 3062 | II_DMTGC0 = 107, |
| 3063 | II_DMUH = 108, |
| 3064 | II_DMUHU = 109, |
| 3065 | II_DMUL = 110, |
| 3066 | II_POP = 111, |
| 3067 | II_DROTR = 112, |
| 3068 | II_DROTR32 = 113, |
| 3069 | II_DROTRV = 114, |
| 3070 | II_DSBH = 115, |
| 3071 | II_DSHD = 116, |
| 3072 | II_DSLL = 117, |
| 3073 | II_DSLL32 = 118, |
| 3074 | II_DSLLV = 119, |
| 3075 | II_DSRA = 120, |
| 3076 | II_DSRA32 = 121, |
| 3077 | II_DSRAV = 122, |
| 3078 | II_DSRL = 123, |
| 3079 | II_DSRL32 = 124, |
| 3080 | II_DSRLV = 125, |
| 3081 | II_DSUB = 126, |
| 3082 | II_DSUBU = 127, |
| 3083 | II_DVP = 128, |
| 3084 | II_DVPE = 129, |
| 3085 | II_EHB = 130, |
| 3086 | II_EI = 131, |
| 3087 | II_EMT = 132, |
| 3088 | II_ERET = 133, |
| 3089 | II_ERETNC = 134, |
| 3090 | II_EVP = 135, |
| 3091 | II_EVPE = 136, |
| 3092 | II_ABS = 137, |
| 3093 | II_SQRT_D = 138, |
| 3094 | II_ADD_D = 139, |
| 3095 | II_ADD_PS = 140, |
| 3096 | II_ADD_S = 141, |
| 3097 | II_DIV_D = 142, |
| 3098 | II_DIV_S = 143, |
| 3099 | II_FLOOR = 144, |
| 3100 | II_MOV_D = 145, |
| 3101 | II_MOV_S = 146, |
| 3102 | II_MUL_D = 147, |
| 3103 | II_MUL_PS = 148, |
| 3104 | II_MUL_S = 149, |
| 3105 | II_NEG = 150, |
| 3106 | II_FORK = 151, |
| 3107 | II_SQRT_S = 152, |
| 3108 | II_SUB_D = 153, |
| 3109 | II_SUB_PS = 154, |
| 3110 | II_SUB_S = 155, |
| 3111 | II_GINVI = 156, |
| 3112 | II_GINVT = 157, |
| 3113 | II_HYPCALL = 158, |
| 3114 | II_JALR_HB = 159, |
| 3115 | II_JALRC = 160, |
| 3116 | II_JALRS = 161, |
| 3117 | II_JALS = 162, |
| 3118 | II_JIALC = 163, |
| 3119 | II_JIC = 164, |
| 3120 | II_JRADDIUSP = 165, |
| 3121 | II_JRC = 166, |
| 3122 | II_JR_HB = 167, |
| 3123 | II_LB = 168, |
| 3124 | II_LBE = 169, |
| 3125 | II_LBU = 170, |
| 3126 | II_LBUE = 171, |
| 3127 | II_LD = 172, |
| 3128 | II_LDC1 = 173, |
| 3129 | II_LDC2 = 174, |
| 3130 | II_LDC3 = 175, |
| 3131 | II_LDL = 176, |
| 3132 | II_LDPC = 177, |
| 3133 | II_LDR = 178, |
| 3134 | II_LDXC1 = 179, |
| 3135 | II_LH = 180, |
| 3136 | II_LHE = 181, |
| 3137 | II_LHU = 182, |
| 3138 | II_LHUE = 183, |
| 3139 | II_LI = 184, |
| 3140 | II_LL = 185, |
| 3141 | II_LLD = 186, |
| 3142 | II_LLE = 187, |
| 3143 | II_LSA = 188, |
| 3144 | II_LUI = 189, |
| 3145 | II_LUXC1 = 190, |
| 3146 | II_LW = 191, |
| 3147 | II_LWC1 = 192, |
| 3148 | II_LWC2 = 193, |
| 3149 | II_LWC3 = 194, |
| 3150 | II_LWE = 195, |
| 3151 | II_LWL = 196, |
| 3152 | II_LWLE = 197, |
| 3153 | II_LWM = 198, |
| 3154 | II_LWPC = 199, |
| 3155 | II_LWP = 200, |
| 3156 | II_LWR = 201, |
| 3157 | II_LWRE = 202, |
| 3158 | II_LWUPC = 203, |
| 3159 | II_LWU = 204, |
| 3160 | II_LWXC1 = 205, |
| 3161 | II_LWXS = 206, |
| 3162 | II_MADDF_D = 207, |
| 3163 | II_MADDF_S = 208, |
| 3164 | II_MADD_D = 209, |
| 3165 | II_MADD_S = 210, |
| 3166 | II_MAX_D = 211, |
| 3167 | II_MAXA_D = 212, |
| 3168 | II_MAX_S = 213, |
| 3169 | II_MAXA_S = 214, |
| 3170 | II_MFC0 = 215, |
| 3171 | II_MFC2 = 216, |
| 3172 | II_MFGC0 = 217, |
| 3173 | II_MFHC0 = 218, |
| 3174 | II_MFHC1 = 219, |
| 3175 | II_MFHGC0 = 220, |
| 3176 | II_MFTR = 221, |
| 3177 | II_MIN_S = 222, |
| 3178 | II_MINA_D = 223, |
| 3179 | II_MIN_D = 224, |
| 3180 | II_MINA_S = 225, |
| 3181 | II_MOD = 226, |
| 3182 | II_MODU = 227, |
| 3183 | II_MOVE = 228, |
| 3184 | II_MOVF_D = 229, |
| 3185 | II_MOVF = 230, |
| 3186 | II_MOVF_S = 231, |
| 3187 | II_MOVN_D = 232, |
| 3188 | II_MOVN = 233, |
| 3189 | II_MOVN_S = 234, |
| 3190 | II_MOVT_D = 235, |
| 3191 | II_MOVT = 236, |
| 3192 | II_MOVT_S = 237, |
| 3193 | II_MOVZ_D = 238, |
| 3194 | II_MOVZ = 239, |
| 3195 | II_MOVZ_S = 240, |
| 3196 | II_MSUBF_D = 241, |
| 3197 | II_MSUBF_S = 242, |
| 3198 | II_MSUB_D = 243, |
| 3199 | II_MSUB_S = 244, |
| 3200 | II_MTC0 = 245, |
| 3201 | II_MTC2 = 246, |
| 3202 | II_MTGC0 = 247, |
| 3203 | II_MTHC0 = 248, |
| 3204 | II_MTHC1 = 249, |
| 3205 | II_MTHGC0 = 250, |
| 3206 | II_MTTR = 251, |
| 3207 | II_MUH = 252, |
| 3208 | II_MUHU = 253, |
| 3209 | II_MUL = 254, |
| 3210 | II_MULR_PS = 255, |
| 3211 | II_MULU = 256, |
| 3212 | II_NMADD_D = 257, |
| 3213 | II_NMADD_S = 258, |
| 3214 | II_NMSUB_D = 259, |
| 3215 | II_NMSUB_S = 260, |
| 3216 | II_NOR = 261, |
| 3217 | II_NOT = 262, |
| 3218 | II_OR = 263, |
| 3219 | II_ORI = 264, |
| 3220 | II_PAUSE = 265, |
| 3221 | II_PREF = 266, |
| 3222 | II_PREFE = 267, |
| 3223 | II_RDHWR = 268, |
| 3224 | II_RDPGPR = 269, |
| 3225 | II_RECIP_D = 270, |
| 3226 | II_RECIP_S = 271, |
| 3227 | II_RINT_D = 272, |
| 3228 | II_RINT_S = 273, |
| 3229 | II_ROTR = 274, |
| 3230 | II_ROTRV = 275, |
| 3231 | II_ROUND = 276, |
| 3232 | II_RSQRT_D = 277, |
| 3233 | II_RSQRT_S = 278, |
| 3234 | II_RESTORE = 279, |
| 3235 | II_SB = 280, |
| 3236 | II_SBE = 281, |
| 3237 | II_SC = 282, |
| 3238 | II_SCD = 283, |
| 3239 | II_SCE = 284, |
| 3240 | II_SD = 285, |
| 3241 | II_SDBBP = 286, |
| 3242 | II_SDC1 = 287, |
| 3243 | II_SDC2 = 288, |
| 3244 | II_SDC3 = 289, |
| 3245 | II_SDL = 290, |
| 3246 | II_SDR = 291, |
| 3247 | II_SDXC1 = 292, |
| 3248 | II_SEB = 293, |
| 3249 | II_SEH = 294, |
| 3250 | II_SELCCZ = 295, |
| 3251 | II_SELCCZ_D = 296, |
| 3252 | II_SELCCZ_S = 297, |
| 3253 | II_SEL_D = 298, |
| 3254 | II_SEL_S = 299, |
| 3255 | II_SEQ_SNE = 300, |
| 3256 | II_SEQI_SNEI = 301, |
| 3257 | II_SH = 302, |
| 3258 | II_SHE = 303, |
| 3259 | II_SIGRIE = 304, |
| 3260 | II_SLL = 305, |
| 3261 | II_SLLV = 306, |
| 3262 | II_SLT_SLTU = 307, |
| 3263 | II_SLTI_SLTIU = 308, |
| 3264 | II_SRA = 309, |
| 3265 | II_SRAV = 310, |
| 3266 | II_SRL = 311, |
| 3267 | II_SRLV = 312, |
| 3268 | II_SSNOP = 313, |
| 3269 | II_SUB = 314, |
| 3270 | II_SUBU = 315, |
| 3271 | II_SUXC1 = 316, |
| 3272 | II_SW = 317, |
| 3273 | II_SWC1 = 318, |
| 3274 | II_SWC2 = 319, |
| 3275 | II_SWC3 = 320, |
| 3276 | II_SWE = 321, |
| 3277 | II_SWL = 322, |
| 3278 | II_SWLE = 323, |
| 3279 | II_SWM = 324, |
| 3280 | II_SWP = 325, |
| 3281 | II_SWR = 326, |
| 3282 | II_SWRE = 327, |
| 3283 | II_SWXC1 = 328, |
| 3284 | II_SYNC = 329, |
| 3285 | II_SYNCI = 330, |
| 3286 | II_SYSCALL = 331, |
| 3287 | II_SAVE = 332, |
| 3288 | II_TEQ = 333, |
| 3289 | II_TEQI = 334, |
| 3290 | II_TGE = 335, |
| 3291 | II_TGEI = 336, |
| 3292 | II_TGEIU = 337, |
| 3293 | II_TGEU = 338, |
| 3294 | II_TLBGINV = 339, |
| 3295 | II_TLBGINVF = 340, |
| 3296 | II_TLBGP = 341, |
| 3297 | II_TLBGR = 342, |
| 3298 | II_TLBGWI = 343, |
| 3299 | II_TLBGWR = 344, |
| 3300 | II_TLBINV = 345, |
| 3301 | II_TLBINVF = 346, |
| 3302 | II_TLBP = 347, |
| 3303 | II_TLBR = 348, |
| 3304 | II_TLBWI = 349, |
| 3305 | II_TLBWR = 350, |
| 3306 | II_TLT = 351, |
| 3307 | II_TLTI = 352, |
| 3308 | II_TTLTIU = 353, |
| 3309 | II_TLTU = 354, |
| 3310 | II_TNE = 355, |
| 3311 | II_TNEI = 356, |
| 3312 | II_TRUNC = 357, |
| 3313 | II_WAIT = 358, |
| 3314 | II_WRPGPR = 359, |
| 3315 | II_WSBH = 360, |
| 3316 | II_XOR = 361, |
| 3317 | II_XORI = 362, |
| 3318 | II_YIELD = 363, |
| 3319 | SB = 364, |
| 3320 | SD = 365, |
| 3321 | SH = 366, |
| 3322 | SW = 367, |
| 3323 | SDC1_SDC164 = 368, |
| 3324 | SWC1 = 369, |
| 3325 | SWC2_R6 = 370, |
| 3326 | SDC2_R6 = 371, |
| 3327 | SDC3 = 372, |
| 3328 | SC_R6_SC64_R6 = 373, |
| 3329 | SCD_R6 = 374, |
| 3330 | SYNCI = 375, |
| 3331 | TLBP = 376, |
| 3332 | TLBR = 377, |
| 3333 | TLBWI = 378, |
| 3334 | TLBWR = 379, |
| 3335 | TLBINV = 380, |
| 3336 | TLBINVF = 381, |
| 3337 | CACHE_R6 = 382, |
| 3338 | LB_LB64 = 383, |
| 3339 | LBu_LBu64 = 384, |
| 3340 | LD = 385, |
| 3341 | LH_LH64 = 386, |
| 3342 | LHu_LHu64 = 387, |
| 3343 | LW_LW64 = 388, |
| 3344 | LWu = 389, |
| 3345 | LDC1_LDC164 = 390, |
| 3346 | LWC1 = 391, |
| 3347 | LD_F16_ST_F16 = 392, |
| 3348 | LDC2_R6 = 393, |
| 3349 | LDC3 = 394, |
| 3350 | LWC2_R6 = 395, |
| 3351 | LLD_R6 = 396, |
| 3352 | LL_R6_LL64_R6 = 397, |
| 3353 | LWPC = 398, |
| 3354 | LWUPC = 399, |
| 3355 | LDPC = 400, |
| 3356 | ST_B_ST_H_ST_W_ST_D = 401, |
| 3357 | LWL64 = 402, |
| 3358 | LWR64 = 403, |
| 3359 | SB64 = 404, |
| 3360 | SH64 = 405, |
| 3361 | SW64 = 406, |
| 3362 | SWL64 = 407, |
| 3363 | SWR64 = 408, |
| 3364 | PREF_PREF_R6 = 409, |
| 3365 | PAUSE = 410, |
| 3366 | SYNC = 411, |
| 3367 | J_TAILCALL = 412, |
| 3368 | JAL = 413, |
| 3369 | JALR_JALR64_JALR64Pseudo_JALRHBPseudo_JALRPseudo_JALRHB64Pseudo = 414, |
| 3370 | B = 415, |
| 3371 | BEQ_BNE_BEQ64_BNE64 = 416, |
| 3372 | BGEZ_BGTZ_BLEZ_BLTZ_BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 417, |
| 3373 | JIALC_JIALC64_JIC = 418, |
| 3374 | JIC64 = 419, |
| 3375 | JR64_TAILCALL64R6REG_TAILCALLR6REG_TAILCALLHB64R6REG_TAILCALLHBR6REG = 420, |
| 3376 | JR_HB_R6_JR_HB64_R6 = 421, |
| 3377 | NAL = 422, |
| 3378 | SDBBP_R6 = 423, |
| 3379 | SYSCALL = 424, |
| 3380 | BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64_BEQC_BNEC_BGEC_BLTC_BGEUC_BLTUC_BOVC_BNVC = 425, |
| 3381 | BEQZC64_BGTZC64_BLEZC64_BNEZC64_BEQZC_BNEZC_BLEZC_BGEZC_BGTZC_BLTZC_BEQZALC_BNEZALC_BLEZALC_BGEZALC_BGTZALC_BLTZALC_BGEZC64_BLTZC64 = 426, |
| 3382 | PseudoIndirectBranchR6_PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6_PseudoIndrectHazardBranchR6 = 427, |
| 3383 | BC_BAL = 428, |
| 3384 | BALC = 429, |
| 3385 | BC1EQZ_BC1NEZ = 430, |
| 3386 | BREAK = 431, |
| 3387 | ERET = 432, |
| 3388 | ERETNC = 433, |
| 3389 | BAL_BR = 434, |
| 3390 | DERET = 435, |
| 3391 | JALR_HB_JALR_HB64 = 436, |
| 3392 | PseudoReturn_PseudoReturn64 = 437, |
| 3393 | ERet_RetRA = 438, |
| 3394 | BC2EQZ_BC2NEZ = 439, |
| 3395 | TLT = 440, |
| 3396 | TLTU = 441, |
| 3397 | TNE = 442, |
| 3398 | WAIT = 443, |
| 3399 | DI = 444, |
| 3400 | TRAP = 445, |
| 3401 | EI = 446, |
| 3402 | ADD = 447, |
| 3403 | ADDiu = 448, |
| 3404 | ADDIUPC = 449, |
| 3405 | ADDu = 450, |
| 3406 | ALIGN = 451, |
| 3407 | ALUIPC = 452, |
| 3408 | AND_AND64_ANDi64 = 453, |
| 3409 | ANDi = 454, |
| 3410 | AUI = 455, |
| 3411 | AUIPC = 456, |
| 3412 | BITSWAP = 457, |
| 3413 | CFC1 = 458, |
| 3414 | CLO_R6 = 459, |
| 3415 | CLZ_R6 = 460, |
| 3416 | CTC1 = 461, |
| 3417 | DADD = 462, |
| 3418 | DADDiu = 463, |
| 3419 | DADDu = 464, |
| 3420 | DAHI = 465, |
| 3421 | DALIGN = 466, |
| 3422 | DATI = 467, |
| 3423 | DAUI = 468, |
| 3424 | DBITSWAP = 469, |
| 3425 | DCLO_R6 = 470, |
| 3426 | DCLZ_R6 = 471, |
| 3427 | DEXT_DEXT64_32_DEXTM_DEXTU_EXT = 472, |
| 3428 | DINS_DINSM_DINSU_INS = 473, |
| 3429 | DLSA_R6_DLSA = 474, |
| 3430 | DMFC1 = 475, |
| 3431 | DMTC1 = 476, |
| 3432 | DROTR = 477, |
| 3433 | DROTR32 = 478, |
| 3434 | DROTRV = 479, |
| 3435 | DSBH = 480, |
| 3436 | DSHD = 481, |
| 3437 | DSLL_DSLL64_32 = 482, |
| 3438 | DSLL32 = 483, |
| 3439 | DSLLV = 484, |
| 3440 | DSRA = 485, |
| 3441 | DSRA32 = 486, |
| 3442 | DSRAV = 487, |
| 3443 | DSRL = 488, |
| 3444 | DSRL32 = 489, |
| 3445 | DSRLV = 490, |
| 3446 | DSUB = 491, |
| 3447 | DSUBu = 492, |
| 3448 | LSA_LSA_R6 = 493, |
| 3449 | LUi_LUi64 = 494, |
| 3450 | MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 495, |
| 3451 | MFC0 = 496, |
| 3452 | MFC2 = 497, |
| 3453 | MTC0 = 498, |
| 3454 | MTC2 = 499, |
| 3455 | MFHC1_D32_MFHC1_D64 = 500, |
| 3456 | MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 501, |
| 3457 | MTHC1_D32_MTHC1_D64 = 502, |
| 3458 | NOP_LONG_BRANCH_LUi2Op_64_LONG_BRANCH_DADDiu2Op_LONG_BRANCH_DADDiu = 503, |
| 3459 | NOR_NOR64 = 504, |
| 3460 | OR_OR64_ORi64 = 505, |
| 3461 | ORi = 506, |
| 3462 | ROTR = 507, |
| 3463 | ROTRV = 508, |
| 3464 | SEB_SEB64 = 509, |
| 3465 | SEH_SEH64 = 510, |
| 3466 | SELEQZ_SELEQZ64_SELNEZ_SELNEZ64 = 511, |
| 3467 | SLL_SLL64_32_SLL64_64 = 512, |
| 3468 | SLLV = 513, |
| 3469 | SLT_SLTu_SLT64_SLTu64 = 514, |
| 3470 | SLTi_SLTiu_SLTi64_SLTiu64 = 515, |
| 3471 | SRA = 516, |
| 3472 | SRAV = 517, |
| 3473 | SRL = 518, |
| 3474 | SRLV = 519, |
| 3475 | SSNOP = 520, |
| 3476 | SUB = 521, |
| 3477 | SUBu = 522, |
| 3478 | WSBH = 523, |
| 3479 | XOR_XOR64_XORi64 = 524, |
| 3480 | XORi = 525, |
| 3481 | TEQ = 526, |
| 3482 | TGE = 527, |
| 3483 | TGEU = 528, |
| 3484 | COPY = 529, |
| 3485 | SELNEZ_D_SELEQZ_D = 530, |
| 3486 | SELNEZ_S_SELEQZ_S = 531, |
| 3487 | SEL_D = 532, |
| 3488 | SEL_S = 533, |
| 3489 | EHB = 534, |
| 3490 | RDHWR_RDHWR64 = 535, |
| 3491 | EVP = 536, |
| 3492 | DVP = 537, |
| 3493 | DMFC0 = 538, |
| 3494 | DMFC2 = 539, |
| 3495 | DMTC0 = 540, |
| 3496 | DMTC2 = 541, |
| 3497 | MUL_R6 = 542, |
| 3498 | MULU = 543, |
| 3499 | MUH = 544, |
| 3500 | MUHU = 545, |
| 3501 | DMUL_R6_DMULU = 546, |
| 3502 | DMUH = 547, |
| 3503 | DMUHU = 548, |
| 3504 | DIV = 549, |
| 3505 | DIVU = 550, |
| 3506 | MOD = 551, |
| 3507 | MODU = 552, |
| 3508 | DDIV = 553, |
| 3509 | DMOD = 554, |
| 3510 | DDIVU = 555, |
| 3511 | DMODU = 556, |
| 3512 | MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 557, |
| 3513 | FABS_S = 558, |
| 3514 | FNEG_S_FNEG_D32_FNEG_D64 = 559, |
| 3515 | FMOV_S = 560, |
| 3516 | FMOV_D32_FMOV_D64 = 561, |
| 3517 | CLASS_S = 562, |
| 3518 | CLASS_D = 563, |
| 3519 | FADD_S = 564, |
| 3520 | FSUB_S = 565, |
| 3521 | FSUB_D32_FSUB_D64 = 566, |
| 3522 | FMUL_S = 567, |
| 3523 | FMUL_D32_FMUL_D64 = 568, |
| 3524 | FDIV_S = 569, |
| 3525 | FSQRT_S = 570, |
| 3526 | FDIV_D32_FDIV_D64 = 571, |
| 3527 | FSQRT_D_FSQRT_W_FRSQRT_D_FRSQRT_W_FRCP_D_FRCP_W = 572, |
| 3528 | FSQRT_D32_FSQRT_D64 = 573, |
| 3529 | RECIP_S = 574, |
| 3530 | RECIP_D32_RECIP_D64 = 575, |
| 3531 | RSQRT_S = 576, |
| 3532 | RSQRT_D32_RSQRT_D64 = 577, |
| 3533 | DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W = 578, |
| 3534 | DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 579, |
| 3535 | ADDV_B_ADDV_H_ADDV_W_ADDV_D_ADDVI_B_ADDVI_H_ADDVI_W_ADDVI_D_SUBV_B_SUBV_H_SUBV_W_SUBV_D_SUBVI_B_SUBVI_H_SUBVI_W_SUBVI_D = 580, |
| 3536 | ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W = 581, |
| 3537 | ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 582, |
| 3538 | SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 583, |
| 3539 | MAX_D_MAXA_D = 584, |
| 3540 | MAX_S_MAXA_S = 585, |
| 3541 | MIN_D_MINA_S = 586, |
| 3542 | MIN_S_MINA_D = 587, |
| 3543 | ADD_A_B_ADD_A_H_ADD_A_W_ADD_A_D_ADDS_A_B_ADDS_A_H_ADDS_A_W_ADDS_A_D_ADDS_S_B_ADDS_S_H_ADDS_S_W_ADDS_S_D_ADDS_U_B_ADDS_U_H_ADDS_U_W_ADDS_U_D_HADD_S_H_HADD_S_W_HADD_S_D_HADD_U_H_HADD_U_W_HADD_U_D_SUBS_S_B_SUBS_S_H_SUBS_S_W_SUBS_S_D_SUBS_U_B_SUBS_U_H_SUBS_U_W_SUBS_U_D_SUBSUU_S_B_SUBSUU_S_H_SUBSUU_S_W_SUBSUU_S_D_HSUB_S_H_HSUB_S_W_HSUB_S_D_HSUB_U_H_HSUB_U_W_HSUB_U_D_AVE_S_B_AVE_S_H_AVE_S_W_AVE_S_D_AVE_U_B_AVE_U_H_AVE_U_W_AVE_U_D_AVER_S_B_AVER_S_H_AVER_S_W_AVER_S_D_AVER_U_B_AVER_U_H_AVER_U_W_AVER_U_D_MIN_A_B_MIN_A_H_MIN_A_W_MIN_A_D_MIN_S_B_MIN_S_H_MIN_S_W_MIN_S_D_MIN_U_B_MIN_U_H_MIN_U_W_MIN_U_D_MINI_S_B_MINI_S_H_MINI_S_W_MINI_S_D_MINI_U_B_MINI_U_H_MINI_U_W_MINI_U_D_MAX_A_B_MAX_A_H_MAX_A_W_MAX_A_D_MAX_S_B_MAX_S_H_MAX_S_W_MAX_S_D_MAX_U_B_MAX_U_H_MAX_U_W_MAX_U_D_MAXI_S_B_MAXI_S_H_MAXI_S_W_MAXI_S_D_MAXI_U_B_MAXI_U_H_MAXI_U_W_MAXI_U_D_CEQ_B_CEQ_H_CEQ_W_CEQ_D_CEQI_B_CEQI_H_CEQI_W_CEQI_D_CLE_S_B_CLE_S_H_CLE_S_W_CLE_S_D_CLE_U_B_CLE_U_H_CLE_U_W_CLE_U_D_CLEI_S_B_CLEI_S_H_CLEI_S_W_CLEI_S_D_CLEI_U_B_CLEI_U_H_CLEI_U_W_CLEI_U_D_CLT_S_B_CLT_S_H_CLT_S_W_CLT_S_D_CLT_U_B_CLT_U_H_CLT_U_W_CLT_U_D_CLTI_S_B_CLTI_S_H_CLTI_S_W_CLTI_S_D_CLTI_U_B_CLTI_U_H_CLTI_U_W_CLTI_U_D = 588, |
| 3544 | SAT_S_B_SAT_S_H_SAT_S_W_SAT_S_D_SAT_U_B_SAT_U_H_SAT_U_W_SAT_U_D_PCNT_B_PCNT_H_PCNT_W_PCNT_D = 589, |
| 3545 | SLL_B_SLL_H_SLL_W_SLL_D_SLLI_B_SLLI_H_SLLI_W_SLLI_D_SRA_B_SRA_H_SRA_W_SRA_D_SRAI_B_SRAI_H_SRAI_W_SRAI_D_SRAR_B_SRAR_H_SRAR_W_SRAR_D_SRARI_B_SRARI_H_SRARI_W_SRARI_D_SRL_B_SRL_H_SRL_W_SRL_D_SRLI_B_SRLI_H_SRLI_W_SRLI_D_SRLR_B_SRLR_H_SRLR_W_SRLR_D_SRLRI_B_SRLRI_H_SRLRI_W_SRLRI_D_NLOC_B_NLOC_H_NLOC_W_NLOC_D_NLZC_B_NLZC_H_NLZC_W_NLZC_D_BNEG_B_BNEG_H_BNEG_W_BNEG_D_BNEGI_B_BNEGI_H_BNEGI_W_BNEGI_D_BCLR_B_BCLR_H_BCLR_W_BCLR_D_BCLRI_B_BCLRI_H_BCLRI_W_BCLRI_D_SHF_B_SHF_H_SHF_W = 590, |
| 3546 | AND_V_ANDI_B_OR_V_ORI_B_XOR_V_XORI_B_NOR_V_NORI_B = 591, |
| 3547 | NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO = 592, |
| 3548 | OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO = 593, |
| 3549 | XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 594, |
| 3550 | AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO = 595, |
| 3551 | ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W = 596, |
| 3552 | ILVL_B_ILVL_D_ILVL_H_ILVL_W = 597, |
| 3553 | ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 598, |
| 3554 | ILVR_B_ILVR_D_ILVR_H_ILVR_W = 599, |
| 3555 | PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W = 600, |
| 3556 | PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 601, |
| 3557 | FILL_B_FILL_D_FILL_H_FILL_W = 602, |
| 3558 | FILL_FD_PSEUDO_FILL_FW_PSEUDO = 603, |
| 3559 | INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 604, |
| 3560 | SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 605, |
| 3561 | SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W = 606, |
| 3562 | CTCMSA_CFCMSA_COPY_S_B_COPY_S_H_COPY_S_W_COPY_S_D_COPY_U_B_COPY_U_H_COPY_U_W_BNZ_B_BNZ_H_BNZ_W_BNZ_D_BNZ_V_BZ_B_BZ_H_BZ_W_BZ_D_BZ_V = 607, |
| 3563 | LD_B_LD_H_LD_W_LD_D = 608, |
| 3564 | LDI_B_LDI_H_LDI_W_LDI_D_MOVE_V = 609, |
| 3565 | FCAF_W_FCAF_D_FCUN_W_FCUN_D_FCOR_W_FCOR_D_FCEQ_W_FCEQ_D_FCUNE_W_FCUNE_D_FCUEQ_W_FCUEQ_D_FCNE_W_FCNE_D_FCLT_W_FCLT_D_FCULT_W_FCULT_D_FCLE_W_FCLE_D_FCULE_W_FCULE_D_FSAF_W_FSAF_D_FSUN_W_FSUN_D_FSOR_W_FSOR_D_FSEQ_W_FSEQ_D_FSUNE_W_FSUNE_D_FSUEQ_W_FSUEQ_D_FSNE_W_FSNE_D_FSLT_W_FSLT_D_FSULT_W_FSULT_D_FSLE_W_FSLE_D_FSULE_W_FSULE_D = 610, |
| 3566 | FMAX_W_FMAX_D_FMAX_A_W_FMAX_A_D_FMIN_W_FMIN_D_FMIN_A_W_FMIN_A_D_FCLASS_W_FCLASS_D_FABS_D_FABS_W = 611, |
| 3567 | FABS_D32_FABS_D64 = 612, |
| 3568 | CMP_UN_D = 613, |
| 3569 | CMP_UN_S = 614, |
| 3570 | CMP_UEQ_D = 615, |
| 3571 | CMP_UEQ_S = 616, |
| 3572 | CMP_EQ_D = 617, |
| 3573 | CMP_EQ_S = 618, |
| 3574 | CMP_LT_D = 619, |
| 3575 | CMP_LT_S = 620, |
| 3576 | CMP_ULT_D = 621, |
| 3577 | CMP_ULT_S = 622, |
| 3578 | CMP_LE_D = 623, |
| 3579 | CMP_LE_S = 624, |
| 3580 | CMP_ULE_D = 625, |
| 3581 | CMP_ULE_S = 626, |
| 3582 | CMP_F_D = 627, |
| 3583 | CMP_F_S = 628, |
| 3584 | CMP_SAF_D = 629, |
| 3585 | CMP_SAF_S = 630, |
| 3586 | CMP_SEQ_D = 631, |
| 3587 | CMP_SEQ_S = 632, |
| 3588 | CMP_SLE_D = 633, |
| 3589 | CMP_SLE_S = 634, |
| 3590 | CMP_SLT_D = 635, |
| 3591 | CMP_SLT_S = 636, |
| 3592 | CMP_SUEQ_D = 637, |
| 3593 | CMP_SUEQ_S = 638, |
| 3594 | CMP_SULE_D = 639, |
| 3595 | CMP_SULE_S = 640, |
| 3596 | CMP_SULT_D = 641, |
| 3597 | CMP_SULT_S = 642, |
| 3598 | CMP_SUN_D = 643, |
| 3599 | CMP_SUN_S = 644, |
| 3600 | TRUNC_W_S_TRUNC_L_S_TRUNC_L_D64_TRUNC_W_D32_TRUNC_W_D64 = 645, |
| 3601 | PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 646, |
| 3602 | ROUND_W_S_ROUND_L_S_ROUND_L_D64_ROUND_W_D32_ROUND_W_D64 = 647, |
| 3603 | FLOOR_W_S_FLOOR_L_S_FLOOR_L_D64_FLOOR_W_D32_FLOOR_W_D64 = 648, |
| 3604 | CVT_D32_S_CVT_D32_W_CVT_D64_W_CVT_D64_S_CVT_D64_L_CVT_L_S_CVT_L_D64_CVT_S_W_CVT_S_D32_CVT_S_PU64_CVT_S_PL64_CVT_S_L_CVT_S_D64_CVT_W_S_CVT_W_D64_CVT_W_D32 = 649, |
| 3605 | CEIL_W_S_CEIL_L_S_CEIL_L_D64_CEIL_W_D32_CEIL_W_D64 = 650, |
| 3606 | RINT_D = 651, |
| 3607 | RINT_S = 652, |
| 3608 | BMZ_V_BMZI_B_BMNZ_V_BMNZI_B_INSERT_B_INSERT_H_INSERT_W_INSERT_D_INSVE_B_INSVE_H_INSVE_W_INSVE_D = 653, |
| 3609 | BSELI_B_BSEL_V = 654, |
| 3610 | BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 655, |
| 3611 | BINSL_B_BINSL_H_BINSL_W_BINSL_D_BINSLI_B_BINSLI_H_BINSLI_W_BINSLI_D_BINSR_B_BINSR_H_BINSR_W_BINSR_D_BINSRI_B_BINSRI_H_BINSRI_W_BINSRI_D_VSHF_B_VSHF_H_VSHF_W_VSHF_D_SLD_B_SLD_H_SLD_W_SLD_D_SLDI_B_SLDI_H_SLDI_W_SLDI_D_BSET_B_BSET_H_BSET_W_BSET_D_BSETI_B_BSETI_H_BSETI_W_BSETI_D = 656, |
| 3612 | MADDV_B_MADDV_H_MADDV_W_MADDV_D_MSUBV_B_MSUBV_H_MSUBV_W_MSUBV_D_MULV_B_MULV_H_MULV_W_MULV_D_DOTP_S_H_DOTP_S_W_DOTP_S_D_DOTP_U_H_DOTP_U_W_DOTP_U_D_MUL_Q_H_MUL_Q_W_MULR_Q_H_MULR_Q_W_MSUB_Q_H_MSUB_Q_W_MSUBR_Q_H_MSUBR_Q_W_MADD_Q_H_MADD_Q_W_MADDR_Q_H_MADDR_Q_W = 657, |
| 3613 | FLOG2_W_FLOG2_D = 658, |
| 3614 | FADD_W_FADD_D_FSUB_W_FSUB_D_FEXDO_H_FEXDO_W_FEXUPL_W_FEXUPL_D_FEXUPR_W_FEXUPR_D_FFINT_S_W_FFINT_S_D_FFINT_U_W_FFINT_U_D_FFQL_W_FFQL_D_FFQR_W_FFQR_D_FTINT_S_W_FTINT_S_D_FTINT_U_W_FTINT_U_D_FTRUNC_S_W_FTRUNC_S_D_FTRUNC_U_W_FTRUNC_U_D_FTQ_H_FTQ_W_FRINT_W_FRINT_D = 659, |
| 3615 | FADD_D32_FADD_D64 = 660, |
| 3616 | PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 661, |
| 3617 | FMUL_W_FMUL_D_FEXP2_W_FEXP2_D_DPADD_S_H_DPADD_S_W_DPADD_S_D_DPADD_U_H_DPADD_U_W_DPADD_U_D_DPSUB_S_H_DPSUB_S_W_DPSUB_S_D_DPSUB_U_H_DPSUB_U_W_DPSUB_U_D = 662, |
| 3618 | FMADD_W_FMADD_D_FMSUB_W_FMSUB_D = 663, |
| 3619 | MSUBF_D = 664, |
| 3620 | MSUBF_S = 665, |
| 3621 | MADDF_D = 666, |
| 3622 | MADDF_S = 667, |
| 3623 | FDIV_D = 668, |
| 3624 | FDIV_W = 669, |
| 3625 | ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 670, |
| 3626 | ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 671, |
| 3627 | ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 672, |
| 3628 | AND = 673, |
| 3629 | LUi = 674, |
| 3630 | NOR = 675, |
| 3631 | OR = 676, |
| 3632 | SLTi_SLTiu = 677, |
| 3633 | XOR = 678, |
| 3634 | NOP = 679, |
| 3635 | BAL = 680, |
| 3636 | BEQ_BNE = 681, |
| 3637 | BEQL_BNEL = 682, |
| 3638 | BGEZ_BGTZ_BLEZ_BLTZ = 683, |
| 3639 | BGEZAL_BGEZALL_BLTZAL_BLTZALL = 684, |
| 3640 | BGEZL_BGTZL_BLEZL_BLTZL = 685, |
| 3641 | JR_TAILCALLREG_TAILCALLREGHB = 686, |
| 3642 | JR_HB = 687, |
| 3643 | PseudoIndirectBranch_PseudoIndirectHazardBranch = 688, |
| 3644 | PseudoReturn = 689, |
| 3645 | SDBBP = 690, |
| 3646 | TEQI = 691, |
| 3647 | TGEI = 692, |
| 3648 | TGEIU = 693, |
| 3649 | TLTI = 694, |
| 3650 | TNEI = 695, |
| 3651 | TTLTIU = 696, |
| 3652 | JALR_JALRHBPseudo_JALRPseudo = 697, |
| 3653 | JALR_HB = 698, |
| 3654 | JALX = 699, |
| 3655 | HYPCALL = 700, |
| 3656 | MFGC0 = 701, |
| 3657 | MFHGC0 = 702, |
| 3658 | MTGC0 = 703, |
| 3659 | MTHGC0 = 704, |
| 3660 | TLBGINV = 705, |
| 3661 | TLBGINVF = 706, |
| 3662 | TLBGP = 707, |
| 3663 | TLBGR = 708, |
| 3664 | TLBGWI = 709, |
| 3665 | TLBGWR = 710, |
| 3666 | LB = 711, |
| 3667 | LBu = 712, |
| 3668 | LH = 713, |
| 3669 | LHu = 714, |
| 3670 | LW = 715, |
| 3671 | LL = 716, |
| 3672 | LWC2 = 717, |
| 3673 | LWC3 = 718, |
| 3674 | LDC2 = 719, |
| 3675 | LBE = 720, |
| 3676 | LBuE = 721, |
| 3677 | LHE = 722, |
| 3678 | LHuE = 723, |
| 3679 | LWE = 724, |
| 3680 | LLE = 725, |
| 3681 | LWL = 726, |
| 3682 | LWR = 727, |
| 3683 | LWLE = 728, |
| 3684 | LWRE = 729, |
| 3685 | SWC2 = 730, |
| 3686 | SWC3 = 731, |
| 3687 | SDC2 = 732, |
| 3688 | SC = 733, |
| 3689 | SBE = 734, |
| 3690 | SHE = 735, |
| 3691 | SWE = 736, |
| 3692 | SCE = 737, |
| 3693 | SWL = 738, |
| 3694 | SWR = 739, |
| 3695 | SWLE = 740, |
| 3696 | SWRE = 741, |
| 3697 | PREF = 742, |
| 3698 | PREFE = 743, |
| 3699 | CACHE = 744, |
| 3700 | CACHEE = 745, |
| 3701 | CLO = 746, |
| 3702 | CLZ = 747, |
| 3703 | MFHI_MFLO_PseudoMFHI_PseudoMFLO = 748, |
| 3704 | RDHWR = 749, |
| 3705 | MOVN_I_I = 750, |
| 3706 | MOVZ_I_I = 751, |
| 3707 | PseudoSDIV_SDIV = 752, |
| 3708 | PseudoUDIV_UDIV = 753, |
| 3709 | MUL = 754, |
| 3710 | MULT_PseudoMULT = 755, |
| 3711 | MULTu_PseudoMULTu = 756, |
| 3712 | MADD_PseudoMADD = 757, |
| 3713 | MADDU_PseudoMADDU = 758, |
| 3714 | MSUB_PseudoMSUB = 759, |
| 3715 | MSUBU_PseudoMSUBU = 760, |
| 3716 | MTHI_MTLO_PseudoMTLOHI = 761, |
| 3717 | EXT = 762, |
| 3718 | INS = 763, |
| 3719 | ADDi = 764, |
| 3720 | SEB = 765, |
| 3721 | SEH = 766, |
| 3722 | SLT_SLTu = 767, |
| 3723 | SLL = 768, |
| 3724 | LSA = 769, |
| 3725 | VSHF_B_VSHF_D_VSHF_H_VSHF_W = 770, |
| 3726 | BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 771, |
| 3727 | BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 772, |
| 3728 | INSERT_B_INSERT_D_INSERT_H_INSERT_W = 773, |
| 3729 | SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 774, |
| 3730 | BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 775, |
| 3731 | BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 776, |
| 3732 | BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 777, |
| 3733 | PCNT_B_PCNT_D_PCNT_H_PCNT_W = 778, |
| 3734 | BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 779, |
| 3735 | CFCMSA_CTCMSA = 780, |
| 3736 | MOVF_D32_MOVF_D64 = 781, |
| 3737 | MOVF_S = 782, |
| 3738 | MOVT_D32_MOVT_D64 = 783, |
| 3739 | MOVT_S = 784, |
| 3740 | ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 785, |
| 3741 | ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 786, |
| 3742 | ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 787, |
| 3743 | AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 788, |
| 3744 | SHF_B_SHF_H_SHF_W = 789, |
| 3745 | MOVE_V = 790, |
| 3746 | AND_V_NOR_V_OR_V_XOR_V = 791, |
| 3747 | FEXP2_D_FEXP2_W = 792, |
| 3748 | CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 793, |
| 3749 | CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 794, |
| 3750 | CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 795, |
| 3751 | FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 796, |
| 3752 | FSUEQ_D_FSUEQ_W = 797, |
| 3753 | FSULE_D_FSULE_W = 798, |
| 3754 | FSULT_D_FSULT_W = 799, |
| 3755 | FSUNE_D_FSUNE_W = 800, |
| 3756 | FSUN_D_FSUN_W = 801, |
| 3757 | FCAF_D_FCAF_W = 802, |
| 3758 | FCEQ_D_FCEQ_W = 803, |
| 3759 | FCLE_D_FCLE_W = 804, |
| 3760 | FCLT_D_FCLT_W = 805, |
| 3761 | FCNE_D_FCNE_W = 806, |
| 3762 | FCOR_D_FCOR_W = 807, |
| 3763 | FCUEQ_D_FCUEQ_W = 808, |
| 3764 | FCULE_D_FCULE_W = 809, |
| 3765 | FCULT_D_FCULT_W = 810, |
| 3766 | FCUNE_D_FCUNE_W = 811, |
| 3767 | FABS_D_FABS_W = 812, |
| 3768 | FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 813, |
| 3769 | FFQL_D_FFQL_W = 814, |
| 3770 | FFQR_D_FFQR_W = 815, |
| 3771 | FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 816, |
| 3772 | FRINT_D_FRINT_W = 817, |
| 3773 | FTQ_H_FTQ_W = 818, |
| 3774 | FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 819, |
| 3775 | FEXDO_H_FEXDO_W = 820, |
| 3776 | FEXUPL_D_FEXUPL_W = 821, |
| 3777 | FEXUPR_D_FEXUPR_W = 822, |
| 3778 | FCLASS_D_FCLASS_W = 823, |
| 3779 | FMAX_A_D_FMAX_A_W = 824, |
| 3780 | FMAX_D_FMAX_W = 825, |
| 3781 | FMIN_A_D_FMIN_A_W = 826, |
| 3782 | SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 827, |
| 3783 | SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 828, |
| 3784 | SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 829, |
| 3785 | HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 830, |
| 3786 | HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 831, |
| 3787 | MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 832, |
| 3788 | MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 833, |
| 3789 | MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 834, |
| 3790 | SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 835, |
| 3791 | SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 836, |
| 3792 | SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 837, |
| 3793 | SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 838, |
| 3794 | SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 839, |
| 3795 | FADD_PS64 = 840, |
| 3796 | FMUL_PS64 = 841, |
| 3797 | FSUB_PS64 = 842, |
| 3798 | CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 843, |
| 3799 | CVT_PS_S64 = 844, |
| 3800 | C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 845, |
| 3801 | C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 846, |
| 3802 | FCMP_D32_FCMP_D64 = 847, |
| 3803 | FCMP_S32 = 848, |
| 3804 | PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 849, |
| 3805 | FRCP_D_FRCP_W = 850, |
| 3806 | FRSQRT_D_FRSQRT_W = 851, |
| 3807 | FMADD_D_FMADD_W = 852, |
| 3808 | FSQRT_W = 853, |
| 3809 | FMUL_D_FMUL_W = 854, |
| 3810 | FADD_D_FADD_W = 855, |
| 3811 | DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 856, |
| 3812 | DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 857, |
| 3813 | MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 858, |
| 3814 | MADDV_B_MADDV_D_MADDV_H_MADDV_W = 859, |
| 3815 | MULV_B_MULV_D_MULV_H_MULV_W = 860, |
| 3816 | MADDR_Q_H_MADDR_Q_W = 861, |
| 3817 | MADD_Q_H_MADD_Q_W = 862, |
| 3818 | MSUBR_Q_H_MSUBR_Q_W = 863, |
| 3819 | MSUB_Q_H_MSUB_Q_W = 864, |
| 3820 | MULR_Q_H_MULR_Q_W = 865, |
| 3821 | MADD_D32_MADD_D64 = 866, |
| 3822 | MADD_S = 867, |
| 3823 | MSUB_D32_MSUB_D64 = 868, |
| 3824 | MSUB_S = 869, |
| 3825 | NMADD_D32_NMADD_D64 = 870, |
| 3826 | NMADD_S = 871, |
| 3827 | NMSUB_D32_NMSUB_D64 = 872, |
| 3828 | NMSUB_S = 873, |
| 3829 | COPY_U_B_COPY_U_H_COPY_U_W = 874, |
| 3830 | BC1F = 875, |
| 3831 | BC1FL = 876, |
| 3832 | BC1T = 877, |
| 3833 | BC1TL = 878, |
| 3834 | MOVF_I = 879, |
| 3835 | MOVT_I = 880, |
| 3836 | SDXC1_SDXC164 = 881, |
| 3837 | SWXC1 = 882, |
| 3838 | SUXC1_SUXC164 = 883, |
| 3839 | ST_F16 = 884, |
| 3840 | MOVN_I_D32_MOVN_I_D64 = 885, |
| 3841 | MOVN_I_S = 886, |
| 3842 | MOVZ_I_D32_MOVZ_I_D64 = 887, |
| 3843 | MOVZ_I_S = 888, |
| 3844 | LDXC1_LDXC164 = 889, |
| 3845 | LWXC1 = 890, |
| 3846 | LUXC1_LUXC164 = 891, |
| 3847 | LEA_ADDiu = 892, |
| 3848 | SELEQZ_SELNEZ = 893, |
| 3849 | AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 894, |
| 3850 | SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 895, |
| 3851 | Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 896, |
| 3852 | ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 897, |
| 3853 | ADDU16_MM_ADDu_MM = 898, |
| 3854 | ADD_MM = 899, |
| 3855 | ADDi_MM = 900, |
| 3856 | AND16_MM_ANDI16_MM_AND_MM = 901, |
| 3857 | ANDi_MM = 902, |
| 3858 | CLO_MM = 903, |
| 3859 | CLZ_MM = 904, |
| 3860 | EXT_MM = 905, |
| 3861 | INS_MM = 906, |
| 3862 | LI16_MM = 907, |
| 3863 | LUi_MM = 908, |
| 3864 | MOVE16_MM = 909, |
| 3865 | MOVEP_MM = 910, |
| 3866 | NOR_MM = 911, |
| 3867 | NOT16_MM = 912, |
| 3868 | OR16_MM_OR_MM = 913, |
| 3869 | ORi_MM = 914, |
| 3870 | ROTRV_MM = 915, |
| 3871 | ROTR_MM = 916, |
| 3872 | SEB_MM = 917, |
| 3873 | SEH_MM = 918, |
| 3874 | SLL16_MM_SLL_MM = 919, |
| 3875 | SLLV_MM = 920, |
| 3876 | SLT_MM_SLTu_MM = 921, |
| 3877 | SLTi_MM_SLTiu_MM = 922, |
| 3878 | SRAV_MM = 923, |
| 3879 | SRA_MM = 924, |
| 3880 | SRL16_MM_SRL_MM = 925, |
| 3881 | SRLV_MM = 926, |
| 3882 | SSNOP_MM = 927, |
| 3883 | SUBU16_MM_SUBu_MM = 928, |
| 3884 | SUB_MM = 929, |
| 3885 | WSBH_MM = 930, |
| 3886 | XOR16_MM_XOR_MM = 931, |
| 3887 | XORi_MM = 932, |
| 3888 | ADDIUPC_MMR6 = 933, |
| 3889 | ADDIU_MMR6 = 934, |
| 3890 | ADDU16_MMR6_ADDU_MMR6 = 935, |
| 3891 | ADD_MMR6 = 936, |
| 3892 | ALIGN_MMR6 = 937, |
| 3893 | ALUIPC_MMR6 = 938, |
| 3894 | AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 939, |
| 3895 | ANDI_MMR6 = 940, |
| 3896 | AUIPC_MMR6 = 941, |
| 3897 | AUI_MMR6 = 942, |
| 3898 | BITSWAP_MMR6 = 943, |
| 3899 | CLO_MMR6 = 944, |
| 3900 | CLZ_MMR6 = 945, |
| 3901 | EXT_MMR6 = 946, |
| 3902 | INS_MMR6 = 947, |
| 3903 | LI16_MMR6 = 948, |
| 3904 | LSA_MMR6 = 949, |
| 3905 | LUI_MMR6 = 950, |
| 3906 | MOVE16_MMR6 = 951, |
| 3907 | NOR_MMR6 = 952, |
| 3908 | NOT16_MMR6 = 953, |
| 3909 | OR16_MMR6_OR_MMR6 = 954, |
| 3910 | ORI_MMR6 = 955, |
| 3911 | SELEQZ_MMR6_SELNEZ_MMR6 = 956, |
| 3912 | SLL16_MMR6_SLL_MMR6 = 957, |
| 3913 | SRL16_MMR6 = 958, |
| 3914 | SSNOP_MMR6 = 959, |
| 3915 | SUBU16_MMR6_SUBU_MMR6 = 960, |
| 3916 | SUB_MMR6 = 961, |
| 3917 | WSBH_MMR6 = 962, |
| 3918 | XOR16_MMR6_XOR_MMR6 = 963, |
| 3919 | XORI_MMR6 = 964, |
| 3920 | DEXT64_32 = 965, |
| 3921 | DSLL64_32 = 966, |
| 3922 | ORi64 = 967, |
| 3923 | DADDi = 968, |
| 3924 | DCLO = 969, |
| 3925 | DCLZ = 970, |
| 3926 | LEA_ADDiu64 = 971, |
| 3927 | MADD = 972, |
| 3928 | MADDU = 973, |
| 3929 | MSUB = 974, |
| 3930 | MSUBU = 975, |
| 3931 | PseudoMADD_MM = 976, |
| 3932 | PseudoMADDU_MM = 977, |
| 3933 | PseudoMSUB_MM = 978, |
| 3934 | PseudoMSUBU_MM = 979, |
| 3935 | PseudoMULT_MM = 980, |
| 3936 | PseudoMULTu_MM = 981, |
| 3937 | PseudoMULT = 982, |
| 3938 | PseudoMULTu = 983, |
| 3939 | PseudoMFHI_MM_PseudoMFLO_MM = 984, |
| 3940 | PseudoMTLOHI_MM = 985, |
| 3941 | MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 986, |
| 3942 | DivRxRy16 = 987, |
| 3943 | DivuRxRy16 = 988, |
| 3944 | MULT_MM = 989, |
| 3945 | MULTu_MM = 990, |
| 3946 | MADD_MM = 991, |
| 3947 | MADDU_MM = 992, |
| 3948 | MSUB_MM = 993, |
| 3949 | MSUBU_MM = 994, |
| 3950 | MUL_MM = 995, |
| 3951 | SDIV_MM_SDIV_MM_Pseudo = 996, |
| 3952 | UDIV_MM_UDIV_MM_Pseudo = 997, |
| 3953 | MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 998, |
| 3954 | MOVF_I_MM = 999, |
| 3955 | MOVT_I_MM = 1000, |
| 3956 | MTHI_MM_MTLO_MM = 1001, |
| 3957 | RDHWR_MM = 1002, |
| 3958 | MUHU_MMR6 = 1003, |
| 3959 | MUH_MMR6 = 1004, |
| 3960 | MULU_MMR6 = 1005, |
| 3961 | MUL_MMR6 = 1006, |
| 3962 | MODU_MMR6 = 1007, |
| 3963 | MOD_MMR6 = 1008, |
| 3964 | DIVU_MMR6 = 1009, |
| 3965 | DIV_MMR6 = 1010, |
| 3966 | RDHWR_MMR6 = 1011, |
| 3967 | DMULU = 1012, |
| 3968 | DMULT_PseudoDMULT = 1013, |
| 3969 | DMULTu_PseudoDMULTu = 1014, |
| 3970 | DSDIV_PseudoDSDIV = 1015, |
| 3971 | DUDIV_PseudoDUDIV = 1016, |
| 3972 | MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 1017, |
| 3973 | PseudoMTLOHI64 = 1018, |
| 3974 | MTHI64_MTLO64 = 1019, |
| 3975 | MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 1020, |
| 3976 | MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 1021, |
| 3977 | BLTZAL = 1022, |
| 3978 | J = 1023, |
| 3979 | JR = 1024, |
| 3980 | ERet = 1025, |
| 3981 | BGEZAL = 1026, |
| 3982 | BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 1027, |
| 3983 | JIALC = 1028, |
| 3984 | BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 1029, |
| 3985 | BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 1030, |
| 3986 | JIC = 1031, |
| 3987 | JR_HB_R6 = 1032, |
| 3988 | SIGRIE = 1033, |
| 3989 | PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 1034, |
| 3990 | TAILCALLR6REG_TAILCALLHBR6REG = 1035, |
| 3991 | Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 1036, |
| 3992 | BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 1037, |
| 3993 | Jal16_JalB16 = 1038, |
| 3994 | JumpLinkReg16 = 1039, |
| 3995 | Break16 = 1040, |
| 3996 | SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 1041, |
| 3997 | B16_MM_B_MM = 1042, |
| 3998 | BAL_BR_MM = 1043, |
| 3999 | BC1F_MM = 1044, |
| 4000 | BC1T_MM = 1045, |
| 4001 | BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 1046, |
| 4002 | BEQZC_MM_BNEZC_MM = 1047, |
| 4003 | BEQ_MM_BNE_MM = 1048, |
| 4004 | DERET_MM = 1049, |
| 4005 | ERET_MM = 1050, |
| 4006 | JR16_MM_JR_MM = 1051, |
| 4007 | J_MM = 1052, |
| 4008 | B_MM_Pseudo = 1053, |
| 4009 | BGEZALS_MM_BLTZALS_MM = 1054, |
| 4010 | BGEZAL_MM_BLTZAL_MM = 1055, |
| 4011 | JALR16_MM_JALR_MM = 1056, |
| 4012 | JALRS16_MM_JALRS_MM = 1057, |
| 4013 | JALS_MM = 1058, |
| 4014 | JALX_MM_JAL_MM = 1059, |
| 4015 | TAILCALLREG_MM = 1060, |
| 4016 | TAILCALL_MM = 1061, |
| 4017 | PseudoIndirectBranch_MM = 1062, |
| 4018 | BREAK16_MM_BREAK_MM = 1063, |
| 4019 | SDBBP16_MM_SDBBP_MM = 1064, |
| 4020 | SYSCALL_MM = 1065, |
| 4021 | TEQI_MM = 1066, |
| 4022 | TEQ_MM = 1067, |
| 4023 | TGEIU_MM = 1068, |
| 4024 | TGEI_MM = 1069, |
| 4025 | TGEU_MM = 1070, |
| 4026 | TGE_MM = 1071, |
| 4027 | TLTIU_MM = 1072, |
| 4028 | TLTI_MM = 1073, |
| 4029 | TLTU_MM = 1074, |
| 4030 | TLT_MM = 1075, |
| 4031 | TNEI_MM = 1076, |
| 4032 | TNE_MM = 1077, |
| 4033 | TRAP_MM = 1078, |
| 4034 | BC16_MMR6_BC_MMR6 = 1079, |
| 4035 | BC1EQZC_MMR6_BC1NEZC_MMR6 = 1080, |
| 4036 | BC2EQZC_MMR6_BC2NEZC_MMR6 = 1081, |
| 4037 | BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 1082, |
| 4038 | BEQZC16_MMR6_BNEZC16_MMR6 = 1083, |
| 4039 | BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 1084, |
| 4040 | DERET_MMR6 = 1085, |
| 4041 | ERETNC_MMR6 = 1086, |
| 4042 | JAL_MMR6 = 1087, |
| 4043 | ERET_MMR6 = 1088, |
| 4044 | JIC_MMR6 = 1089, |
| 4045 | JRADDIUSP_JRCADDIUSP_MMR6 = 1090, |
| 4046 | JRC16_MM = 1091, |
| 4047 | JRC16_MMR6 = 1092, |
| 4048 | SIGRIE_MMR6 = 1093, |
| 4049 | B_MMR6_Pseudo = 1094, |
| 4050 | PseudoIndirectBranch_MMR6 = 1095, |
| 4051 | BALC_MMR6 = 1096, |
| 4052 | BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1097, |
| 4053 | JALRC16_MMR6 = 1098, |
| 4054 | JALRC_HB_MMR6 = 1099, |
| 4055 | JALRC_MMR6 = 1100, |
| 4056 | JIALC_MMR6 = 1101, |
| 4057 | TAILCALLREG_MMR6 = 1102, |
| 4058 | TAILCALL_MMR6 = 1103, |
| 4059 | BREAK16_MMR6_BREAK_MMR6 = 1104, |
| 4060 | SDBBP_MMR6_SDBBP16_MMR6 = 1105, |
| 4061 | JR64 = 1106, |
| 4062 | JR_HB64 = 1107, |
| 4063 | TAILCALLREG64_TAILCALLREGHB64 = 1108, |
| 4064 | PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1109, |
| 4065 | TLBP_MM = 1110, |
| 4066 | TLBR_MM = 1111, |
| 4067 | TLBWI_MM = 1112, |
| 4068 | TLBWR_MM = 1113, |
| 4069 | DI_MM = 1114, |
| 4070 | EI_MM = 1115, |
| 4071 | EHB_MM = 1116, |
| 4072 | PAUSE_MM = 1117, |
| 4073 | WAIT_MM = 1118, |
| 4074 | RDPGPR_MMR6 = 1119, |
| 4075 | WRPGPR_MMR6 = 1120, |
| 4076 | TLBINV_MMR6 = 1121, |
| 4077 | TLBINVF_MMR6 = 1122, |
| 4078 | MFHC0_MMR6 = 1123, |
| 4079 | MFC0_MMR6 = 1124, |
| 4080 | MFHC2_MMR6_MFC2_MMR6 = 1125, |
| 4081 | MTHC0_MMR6 = 1126, |
| 4082 | MTC0_MMR6 = 1127, |
| 4083 | MTHC2_MMR6_MTC2_MMR6 = 1128, |
| 4084 | EVP_MMR6 = 1129, |
| 4085 | DVP_MMR6 = 1130, |
| 4086 | DI_MMR6 = 1131, |
| 4087 | EI_MMR6 = 1132, |
| 4088 | EHB_MMR6 = 1133, |
| 4089 | PAUSE_MMR6 = 1134, |
| 4090 | WAIT_MMR6 = 1135, |
| 4091 | CFC2_MM = 1136, |
| 4092 | CTC2_MM = 1137, |
| 4093 | DMT = 1138, |
| 4094 | DVPE = 1139, |
| 4095 | EMT = 1140, |
| 4096 | EVPE = 1141, |
| 4097 | MFTR = 1142, |
| 4098 | MTTR = 1143, |
| 4099 | YIELD = 1144, |
| 4100 | FORK = 1145, |
| 4101 | DMFGC0 = 1146, |
| 4102 | DMTGC0 = 1147, |
| 4103 | HYPCALL_MM = 1148, |
| 4104 | TLBGINVF_MM = 1149, |
| 4105 | TLBGINV_MM = 1150, |
| 4106 | TLBGP_MM = 1151, |
| 4107 | TLBGR_MM = 1152, |
| 4108 | TLBGWI_MM = 1153, |
| 4109 | TLBGWR_MM = 1154, |
| 4110 | MFGC0_MM = 1155, |
| 4111 | MFHGC0_MM = 1156, |
| 4112 | MTGC0_MM = 1157, |
| 4113 | MTHGC0_MM = 1158, |
| 4114 | SC_MMR6 = 1159, |
| 4115 | LL_R6 = 1160, |
| 4116 | SC_R6 = 1161, |
| 4117 | GINVI = 1162, |
| 4118 | GINVT = 1163, |
| 4119 | LBE_MM = 1164, |
| 4120 | LBuE_MM = 1165, |
| 4121 | LHE_MM = 1166, |
| 4122 | LHuE_MM = 1167, |
| 4123 | LWE_MM = 1168, |
| 4124 | LWLE_MM = 1169, |
| 4125 | LWRE_MM = 1170, |
| 4126 | LLE_MM = 1171, |
| 4127 | SBE_MM = 1172, |
| 4128 | SB_MM = 1173, |
| 4129 | SHE_MM = 1174, |
| 4130 | SWE_MM = 1175, |
| 4131 | SWLE_MM = 1176, |
| 4132 | SWRE_MM = 1177, |
| 4133 | SCE_MM = 1178, |
| 4134 | PREFE_MM = 1179, |
| 4135 | CACHEE_MM = 1180, |
| 4136 | Restore16_RestoreX16 = 1181, |
| 4137 | LbRxRyOffMemX16 = 1182, |
| 4138 | LbuRxRyOffMemX16 = 1183, |
| 4139 | LhRxRyOffMemX16 = 1184, |
| 4140 | LhuRxRyOffMemX16 = 1185, |
| 4141 | LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1186, |
| 4142 | Save16_SaveX16 = 1187, |
| 4143 | SbRxRyOffMemX16 = 1188, |
| 4144 | ShRxRyOffMemX16 = 1189, |
| 4145 | SwRxRyOffMemX16_SwRxSpImmX16 = 1190, |
| 4146 | LBU16_MM_LBu_MM = 1191, |
| 4147 | LB_MM = 1192, |
| 4148 | LHU16_MM_LHu_MM = 1193, |
| 4149 | LH_MM = 1194, |
| 4150 | LL_MM = 1195, |
| 4151 | LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1196, |
| 4152 | LWL_MM = 1197, |
| 4153 | LWM16_MM_LWM32_MM = 1198, |
| 4154 | LWP_MM = 1199, |
| 4155 | LWR_MM = 1200, |
| 4156 | LWU_MM = 1201, |
| 4157 | LWXS_MM = 1202, |
| 4158 | SB16_MM = 1203, |
| 4159 | SC_MM = 1204, |
| 4160 | SH16_MM_SH_MM = 1205, |
| 4161 | SW16_MM_SWSP_MM_SW_MM = 1206, |
| 4162 | SWL_MM = 1207, |
| 4163 | SWM16_MM_SWM32_MM = 1208, |
| 4164 | SWM_MM = 1209, |
| 4165 | SWP_MM = 1210, |
| 4166 | SWR_MM = 1211, |
| 4167 | PREF_MM_PREFX_MM = 1212, |
| 4168 | CACHE_MM = 1213, |
| 4169 | SYNC_MM = 1214, |
| 4170 | SYNCI_MM = 1215, |
| 4171 | GINVI_MMR6 = 1216, |
| 4172 | GINVT_MMR6 = 1217, |
| 4173 | LBU_MMR6 = 1218, |
| 4174 | LB_MMR6 = 1219, |
| 4175 | LDC2_MMR6 = 1220, |
| 4176 | LL_MMR6 = 1221, |
| 4177 | LWM16_MMR6 = 1222, |
| 4178 | LWC2_MMR6 = 1223, |
| 4179 | LWPC_MMR6 = 1224, |
| 4180 | LW_MMR6 = 1225, |
| 4181 | SB16_MMR6_SB_MMR6 = 1226, |
| 4182 | SDC2_MMR6 = 1227, |
| 4183 | SH16_MMR6_SH_MMR6 = 1228, |
| 4184 | SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1229, |
| 4185 | SWC2_MMR6 = 1230, |
| 4186 | SWM16_MMR6 = 1231, |
| 4187 | SYNC_MMR6 = 1232, |
| 4188 | SYNCI_MMR6 = 1233, |
| 4189 | PREF_MMR6 = 1234, |
| 4190 | CACHE_MMR6 = 1235, |
| 4191 | LL64_LLD = 1236, |
| 4192 | LDL = 1237, |
| 4193 | LDR = 1238, |
| 4194 | SC64_SCD = 1239, |
| 4195 | SDL = 1240, |
| 4196 | SDR = 1241, |
| 4197 | CRC32B = 1242, |
| 4198 | CRC32H = 1243, |
| 4199 | CRC32W = 1244, |
| 4200 | CRC32CB = 1245, |
| 4201 | CRC32CH = 1246, |
| 4202 | CRC32CW = 1247, |
| 4203 | CRC32D = 1248, |
| 4204 | CRC32CD = 1249, |
| 4205 | BADDu = 1250, |
| 4206 | BBIT0_BBIT032_BBIT1_BBIT132 = 1251, |
| 4207 | CINS_CINS32_CINS64_32_CINS_i32 = 1252, |
| 4208 | DMFC2_OCTEON = 1253, |
| 4209 | DMTC2_OCTEON = 1254, |
| 4210 | DPOP_POP = 1255, |
| 4211 | EXTS_EXTS32 = 1256, |
| 4212 | MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1257, |
| 4213 | SEQ_SNE = 1258, |
| 4214 | SEQi_SNEi = 1259, |
| 4215 | V3MULU_VMM0_VMULU = 1260, |
| 4216 | DMUL = 1261, |
| 4217 | SAA_SAAD = 1262, |
| 4218 | ADDR_PS64 = 1263, |
| 4219 | CVT_PS_PW64_CVT_PW_PS64 = 1264, |
| 4220 | MULR_PS64 = 1265, |
| 4221 | MOVT_I64 = 1266, |
| 4222 | MOVF_I64 = 1267, |
| 4223 | MOVZ_I64_S = 1268, |
| 4224 | MOVN_I64_D64 = 1269, |
| 4225 | MOVN_I64_S = 1270, |
| 4226 | MOVZ_I64_D64 = 1271, |
| 4227 | MOVF_D32_MM = 1272, |
| 4228 | MOVF_S_MM = 1273, |
| 4229 | MOVN_I_D32_MM = 1274, |
| 4230 | MOVN_I_S_MM = 1275, |
| 4231 | MOVT_D32_MM = 1276, |
| 4232 | MOVT_S_MM = 1277, |
| 4233 | MOVZ_I_D32_MM = 1278, |
| 4234 | MOVZ_I_S_MM = 1279, |
| 4235 | CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1280, |
| 4236 | CEIL_W_MM_CEIL_W_S_MM = 1281, |
| 4237 | FLOOR_W_MM_FLOOR_W_S_MM = 1282, |
| 4238 | NMADD_S_MM = 1283, |
| 4239 | NMADD_D32_MM = 1284, |
| 4240 | NMSUB_S_MM = 1285, |
| 4241 | NMSUB_D32_MM = 1286, |
| 4242 | MADD_S_MM = 1287, |
| 4243 | MADD_D32_MM = 1288, |
| 4244 | ROUND_W_MM_ROUND_W_S_MM = 1289, |
| 4245 | TRUNC_W_MM_TRUNC_W_S_MM = 1290, |
| 4246 | C_F_D32_MM_C_F_D64_MM = 1291, |
| 4247 | C_F_S_MM = 1292, |
| 4248 | C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1293, |
| 4249 | C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1294, |
| 4250 | C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1295, |
| 4251 | C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1296, |
| 4252 | C_NGLE_D32_MM_C_NGLE_D64_MM = 1297, |
| 4253 | C_NGLE_S_MM = 1298, |
| 4254 | FCMP_S32_MM = 1299, |
| 4255 | FCMP_D32_MM = 1300, |
| 4256 | MFC1_MM = 1301, |
| 4257 | MFHC1_D32_MM_MFHC1_D64_MM = 1302, |
| 4258 | MTC1_MM_MTC1_D64_MM = 1303, |
| 4259 | MTHC1_D32_MM_MTHC1_D64_MM = 1304, |
| 4260 | FABS_D32_MM_FABS_D64_MM = 1305, |
| 4261 | FABS_S_MM = 1306, |
| 4262 | FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1307, |
| 4263 | FADD_D32_MM_FADD_D64_MM = 1308, |
| 4264 | FADD_S_MM = 1309, |
| 4265 | FMOV_D32_MM_FMOV_D64_MM = 1310, |
| 4266 | FMOV_S_MM = 1311, |
| 4267 | FMUL_D32_MM_FMUL_D64_MM = 1312, |
| 4268 | FMUL_S_MM = 1313, |
| 4269 | FSUB_D32_MM_FSUB_D64_MM = 1314, |
| 4270 | FSUB_S_MM = 1315, |
| 4271 | MSUB_S_MM = 1316, |
| 4272 | MSUB_D32_MM = 1317, |
| 4273 | FDIV_S_MM = 1318, |
| 4274 | FDIV_D32_MM_FDIV_D64_MM = 1319, |
| 4275 | FSQRT_S_MM = 1320, |
| 4276 | FSQRT_D32_MM_FSQRT_D64_MM = 1321, |
| 4277 | RECIP_S_MM_RSQRT_S_MM = 1322, |
| 4278 | RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1323, |
| 4279 | SDC1_MM_D32_SDC1_MM_D64 = 1324, |
| 4280 | SWC1_MM = 1325, |
| 4281 | SUXC1_MM = 1326, |
| 4282 | SWXC1_MM = 1327, |
| 4283 | CFC1_MM = 1328, |
| 4284 | CTC1_MM = 1329, |
| 4285 | LDC1_MM_D32_LDC1_MM_D64 = 1330, |
| 4286 | LUXC1_MM = 1331, |
| 4287 | LWC1_MM = 1332, |
| 4288 | LWXC1_MM = 1333, |
| 4289 | FNEG_S_MMR6 = 1334, |
| 4290 | CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1335, |
| 4291 | CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1336, |
| 4292 | CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1337, |
| 4293 | CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1338, |
| 4294 | CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1339, |
| 4295 | CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1340, |
| 4296 | CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1341, |
| 4297 | TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1342, |
| 4298 | ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1343, |
| 4299 | FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1344, |
| 4300 | CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1345, |
| 4301 | MFC1_MMR6 = 1346, |
| 4302 | MTC1_MMR6 = 1347, |
| 4303 | CLASS_S_MMR6_CLASS_D_MMR6 = 1348, |
| 4304 | FADD_S_MMR6 = 1349, |
| 4305 | MAX_D_MMR6 = 1350, |
| 4306 | MAX_S_MMR6 = 1351, |
| 4307 | MIN_D_MMR6 = 1352, |
| 4308 | MIN_S_MMR6 = 1353, |
| 4309 | MAXA_D_MMR6 = 1354, |
| 4310 | MAXA_S_MMR6 = 1355, |
| 4311 | MINA_D_MMR6 = 1356, |
| 4312 | MINA_S_MMR6 = 1357, |
| 4313 | SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1358, |
| 4314 | SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1359, |
| 4315 | SEL_D_MMR6 = 1360, |
| 4316 | SEL_S_MMR6 = 1361, |
| 4317 | RINT_S_MMR6_RINT_D_MMR6 = 1362, |
| 4318 | MADDF_D_MMR6 = 1363, |
| 4319 | MADDF_S_MMR6 = 1364, |
| 4320 | MSUBF_D_MMR6 = 1365, |
| 4321 | MSUBF_S_MMR6 = 1366, |
| 4322 | FMOV_S_MMR6 = 1367, |
| 4323 | FMUL_S_MMR6 = 1368, |
| 4324 | FSUB_S_MMR6 = 1369, |
| 4325 | FMOV_D_MMR6 = 1370, |
| 4326 | FDIV_S_MMR6 = 1371, |
| 4327 | SDC1_D64_MMR6 = 1372, |
| 4328 | LDC1_D64_MMR6 = 1373, |
| 4329 | SWDSP = 1374, |
| 4330 | LWDSP = 1375, |
| 4331 | PseudoMTLOHI_DSP = 1376, |
| 4332 | EXTRV_RS_W = 1377, |
| 4333 | EXTRV_R_W = 1378, |
| 4334 | EXTRV_S_H = 1379, |
| 4335 | EXTRV_W = 1380, |
| 4336 | EXTR_RS_W = 1381, |
| 4337 | EXTR_R_W = 1382, |
| 4338 | EXTR_S_H = 1383, |
| 4339 | EXTR_W = 1384, |
| 4340 | INSV = 1385, |
| 4341 | MTHLIP = 1386, |
| 4342 | MTHI_DSP = 1387, |
| 4343 | MTLO_DSP = 1388, |
| 4344 | ABSQ_S_PH = 1389, |
| 4345 | ABSQ_S_W = 1390, |
| 4346 | ADDQ_PH = 1391, |
| 4347 | ADDQ_S_PH = 1392, |
| 4348 | ADDQ_S_W = 1393, |
| 4349 | ADDSC = 1394, |
| 4350 | ADDU_QB = 1395, |
| 4351 | ADDU_S_QB = 1396, |
| 4352 | ADDWC = 1397, |
| 4353 | BITREV = 1398, |
| 4354 | BPOSGE32 = 1399, |
| 4355 | CMPGU_EQ_QB = 1400, |
| 4356 | CMPGU_LE_QB = 1401, |
| 4357 | CMPGU_LT_QB = 1402, |
| 4358 | CMPU_EQ_QB = 1403, |
| 4359 | CMPU_LE_QB = 1404, |
| 4360 | CMPU_LT_QB = 1405, |
| 4361 | CMP_EQ_PH = 1406, |
| 4362 | CMP_LE_PH = 1407, |
| 4363 | CMP_LT_PH = 1408, |
| 4364 | DPAQ_SA_L_W = 1409, |
| 4365 | DPAQ_S_W_PH = 1410, |
| 4366 | DPAU_H_QBL = 1411, |
| 4367 | DPAU_H_QBR = 1412, |
| 4368 | DPSQ_SA_L_W = 1413, |
| 4369 | DPSQ_S_W_PH = 1414, |
| 4370 | DPSU_H_QBL = 1415, |
| 4371 | DPSU_H_QBR = 1416, |
| 4372 | EXTPDPV = 1417, |
| 4373 | EXTPDP = 1418, |
| 4374 | EXTPV = 1419, |
| 4375 | EXTP = 1420, |
| 4376 | LBUX = 1421, |
| 4377 | LHX = 1422, |
| 4378 | LWX = 1423, |
| 4379 | MADDU_DSP = 1424, |
| 4380 | MADD_DSP = 1425, |
| 4381 | MAQ_SA_W_PHL = 1426, |
| 4382 | MAQ_SA_W_PHR = 1427, |
| 4383 | MAQ_S_W_PHL = 1428, |
| 4384 | MAQ_S_W_PHR = 1429, |
| 4385 | MFHI_DSP = 1430, |
| 4386 | MFLO_DSP = 1431, |
| 4387 | MODSUB = 1432, |
| 4388 | MSUBU_DSP = 1433, |
| 4389 | MSUB_DSP = 1434, |
| 4390 | MULEQ_S_W_PHL = 1435, |
| 4391 | MULEQ_S_W_PHR = 1436, |
| 4392 | MULEU_S_PH_QBL = 1437, |
| 4393 | MULEU_S_PH_QBR = 1438, |
| 4394 | MULQ_RS_PH = 1439, |
| 4395 | MULSAQ_S_W_PH = 1440, |
| 4396 | MULTU_DSP = 1441, |
| 4397 | MULT_DSP = 1442, |
| 4398 | PACKRL_PH = 1443, |
| 4399 | PICK_PH = 1444, |
| 4400 | PICK_QB = 1445, |
| 4401 | PRECEQU_PH_QBLA = 1446, |
| 4402 | PRECEQU_PH_QBL = 1447, |
| 4403 | PRECEQU_PH_QBRA = 1448, |
| 4404 | PRECEQU_PH_QBR = 1449, |
| 4405 | PRECEQ_W_PHL = 1450, |
| 4406 | PRECEQ_W_PHR = 1451, |
| 4407 | PRECEU_PH_QBLA = 1452, |
| 4408 | PRECEU_PH_QBL = 1453, |
| 4409 | PRECEU_PH_QBRA = 1454, |
| 4410 | PRECEU_PH_QBR = 1455, |
| 4411 | PRECRQU_S_QB_PH = 1456, |
| 4412 | PRECRQ_PH_W = 1457, |
| 4413 | PRECRQ_QB_PH = 1458, |
| 4414 | PRECRQ_RS_PH_W = 1459, |
| 4415 | RADDU_W_QB = 1460, |
| 4416 | RDDSP = 1461, |
| 4417 | REPLV_PH = 1462, |
| 4418 | REPLV_QB = 1463, |
| 4419 | REPL_PH = 1464, |
| 4420 | REPL_QB = 1465, |
| 4421 | SHILOV = 1466, |
| 4422 | SHILO = 1467, |
| 4423 | SHLLV_PH = 1468, |
| 4424 | SHLLV_QB = 1469, |
| 4425 | SHLLV_S_PH = 1470, |
| 4426 | SHLLV_S_W = 1471, |
| 4427 | SHLL_PH = 1472, |
| 4428 | SHLL_QB = 1473, |
| 4429 | SHLL_S_PH = 1474, |
| 4430 | SHLL_S_W = 1475, |
| 4431 | SHRAV_PH = 1476, |
| 4432 | SHRAV_R_PH = 1477, |
| 4433 | SHRAV_R_W = 1478, |
| 4434 | SHRA_PH = 1479, |
| 4435 | SHRA_R_PH = 1480, |
| 4436 | SHRA_R_W = 1481, |
| 4437 | SHRLV_QB = 1482, |
| 4438 | SHRL_QB = 1483, |
| 4439 | SUBQ_PH = 1484, |
| 4440 | SUBQ_S_PH = 1485, |
| 4441 | SUBQ_S_W = 1486, |
| 4442 | SUBU_QB = 1487, |
| 4443 | SUBU_S_QB = 1488, |
| 4444 | WRDSP = 1489, |
| 4445 | PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1490, |
| 4446 | PseudoPICK_PH_PseudoPICK_QB = 1491, |
| 4447 | ABSQ_S_QB = 1492, |
| 4448 | ADDQH_PH = 1493, |
| 4449 | ADDQH_R_PH = 1494, |
| 4450 | ADDQH_R_W = 1495, |
| 4451 | ADDQH_W = 1496, |
| 4452 | ADDUH_QB = 1497, |
| 4453 | ADDUH_R_QB = 1498, |
| 4454 | ADDU_PH = 1499, |
| 4455 | ADDU_S_PH = 1500, |
| 4456 | APPEND = 1501, |
| 4457 | BALIGN = 1502, |
| 4458 | CMPGDU_EQ_QB = 1503, |
| 4459 | CMPGDU_LE_QB = 1504, |
| 4460 | CMPGDU_LT_QB = 1505, |
| 4461 | DPA_W_PH = 1506, |
| 4462 | DPAQX_SA_W_PH = 1507, |
| 4463 | DPAQX_S_W_PH = 1508, |
| 4464 | DPAX_W_PH = 1509, |
| 4465 | DPS_W_PH = 1510, |
| 4466 | DPSQX_S_W_PH = 1511, |
| 4467 | DPSQX_SA_W_PH = 1512, |
| 4468 | DPSX_W_PH = 1513, |
| 4469 | MUL_PH = 1514, |
| 4470 | MUL_S_PH = 1515, |
| 4471 | MULQ_RS_W = 1516, |
| 4472 | MULQ_S_PH = 1517, |
| 4473 | MULQ_S_W = 1518, |
| 4474 | MULSA_W_PH = 1519, |
| 4475 | PRECR_QB_PH = 1520, |
| 4476 | PRECR_SRA_PH_W = 1521, |
| 4477 | PRECR_SRA_R_PH_W = 1522, |
| 4478 | PREPEND = 1523, |
| 4479 | SHRA_QB = 1524, |
| 4480 | SHRA_R_QB = 1525, |
| 4481 | SHRAV_QB = 1526, |
| 4482 | SHRAV_R_QB = 1527, |
| 4483 | SHRL_PH = 1528, |
| 4484 | SHRLV_PH = 1529, |
| 4485 | SUBQH_PH = 1530, |
| 4486 | SUBQH_R_PH = 1531, |
| 4487 | SUBQH_W = 1532, |
| 4488 | SUBQH_R_W = 1533, |
| 4489 | SUBU_PH = 1534, |
| 4490 | SUBU_S_PH = 1535, |
| 4491 | SUBUH_QB = 1536, |
| 4492 | SUBUH_R_QB = 1537, |
| 4493 | LWDSP_MM = 1538, |
| 4494 | SWDSP_MM = 1539, |
| 4495 | ABSQ_S_PH_MM = 1540, |
| 4496 | ABSQ_S_W_MM = 1541, |
| 4497 | ADDQ_PH_MM = 1542, |
| 4498 | ADDQ_S_PH_MM = 1543, |
| 4499 | ADDQ_S_W_MM = 1544, |
| 4500 | ADDSC_MM = 1545, |
| 4501 | ADDU_QB_MM = 1546, |
| 4502 | ADDU_S_QB_MM = 1547, |
| 4503 | ADDWC_MM = 1548, |
| 4504 | BITREV_MM = 1549, |
| 4505 | BPOSGE32_MM = 1550, |
| 4506 | CMPGU_EQ_QB_MM = 1551, |
| 4507 | CMPGU_LE_QB_MM = 1552, |
| 4508 | CMPGU_LT_QB_MM = 1553, |
| 4509 | CMPU_EQ_QB_MM = 1554, |
| 4510 | CMPU_LE_QB_MM = 1555, |
| 4511 | CMPU_LT_QB_MM = 1556, |
| 4512 | CMP_EQ_PH_MM = 1557, |
| 4513 | CMP_LE_PH_MM = 1558, |
| 4514 | CMP_LT_PH_MM = 1559, |
| 4515 | DPAQ_SA_L_W_MM = 1560, |
| 4516 | DPAQ_S_W_PH_MM = 1561, |
| 4517 | DPAU_H_QBL_MM = 1562, |
| 4518 | DPAU_H_QBR_MM = 1563, |
| 4519 | DPSQ_SA_L_W_MM = 1564, |
| 4520 | DPSQ_S_W_PH_MM = 1565, |
| 4521 | DPSU_H_QBL_MM = 1566, |
| 4522 | DPSU_H_QBR_MM = 1567, |
| 4523 | EXTPDPV_MM = 1568, |
| 4524 | EXTPDP_MM = 1569, |
| 4525 | EXTPV_MM = 1570, |
| 4526 | EXTP_MM = 1571, |
| 4527 | EXTRV_RS_W_MM = 1572, |
| 4528 | EXTRV_R_W_MM = 1573, |
| 4529 | EXTRV_S_H_MM = 1574, |
| 4530 | EXTRV_W_MM = 1575, |
| 4531 | EXTR_RS_W_MM = 1576, |
| 4532 | EXTR_R_W_MM = 1577, |
| 4533 | EXTR_S_H_MM = 1578, |
| 4534 | EXTR_W_MM = 1579, |
| 4535 | INSV_MM = 1580, |
| 4536 | LBUX_MM = 1581, |
| 4537 | LHX_MM = 1582, |
| 4538 | LWX_MM = 1583, |
| 4539 | MADDU_DSP_MM = 1584, |
| 4540 | MADD_DSP_MM = 1585, |
| 4541 | MAQ_SA_W_PHL_MM = 1586, |
| 4542 | MAQ_SA_W_PHR_MM = 1587, |
| 4543 | MAQ_S_W_PHL_MM = 1588, |
| 4544 | MAQ_S_W_PHR_MM = 1589, |
| 4545 | MFHI_DSP_MM = 1590, |
| 4546 | MFLO_DSP_MM = 1591, |
| 4547 | MODSUB_MM = 1592, |
| 4548 | MOVEP_MMR6 = 1593, |
| 4549 | MOVN_I_MM = 1594, |
| 4550 | MOVZ_I_MM = 1595, |
| 4551 | MSUBU_DSP_MM = 1596, |
| 4552 | MSUB_DSP_MM = 1597, |
| 4553 | MTHI_DSP_MM = 1598, |
| 4554 | MTHLIP_MM = 1599, |
| 4555 | MTLO_DSP_MM = 1600, |
| 4556 | MULEQ_S_W_PHL_MM = 1601, |
| 4557 | MULEQ_S_W_PHR_MM = 1602, |
| 4558 | MULEU_S_PH_QBL_MM = 1603, |
| 4559 | MULEU_S_PH_QBR_MM = 1604, |
| 4560 | MULQ_RS_PH_MM = 1605, |
| 4561 | MULSAQ_S_W_PH_MM = 1606, |
| 4562 | MULTU_DSP_MM = 1607, |
| 4563 | MULT_DSP_MM = 1608, |
| 4564 | PACKRL_PH_MM = 1609, |
| 4565 | PICK_PH_MM = 1610, |
| 4566 | PICK_QB_MM = 1611, |
| 4567 | PRECEQU_PH_QBLA_MM = 1612, |
| 4568 | PRECEQU_PH_QBL_MM = 1613, |
| 4569 | PRECEQU_PH_QBRA_MM = 1614, |
| 4570 | PRECEQU_PH_QBR_MM = 1615, |
| 4571 | PRECEQ_W_PHL_MM = 1616, |
| 4572 | PRECEQ_W_PHR_MM = 1617, |
| 4573 | PRECEU_PH_QBLA_MM = 1618, |
| 4574 | PRECEU_PH_QBL_MM = 1619, |
| 4575 | PRECEU_PH_QBRA_MM = 1620, |
| 4576 | PRECEU_PH_QBR_MM = 1621, |
| 4577 | PRECRQU_S_QB_PH_MM = 1622, |
| 4578 | PRECRQ_PH_W_MM = 1623, |
| 4579 | PRECRQ_QB_PH_MM = 1624, |
| 4580 | PRECRQ_RS_PH_W_MM = 1625, |
| 4581 | RADDU_W_QB_MM = 1626, |
| 4582 | RDDSP_MM = 1627, |
| 4583 | REPLV_PH_MM = 1628, |
| 4584 | REPLV_QB_MM = 1629, |
| 4585 | REPL_PH_MM = 1630, |
| 4586 | REPL_QB_MM = 1631, |
| 4587 | SHILOV_MM = 1632, |
| 4588 | SHILO_MM = 1633, |
| 4589 | SHLLV_PH_MM = 1634, |
| 4590 | SHLLV_QB_MM = 1635, |
| 4591 | SHLLV_S_PH_MM = 1636, |
| 4592 | SHLLV_S_W_MM = 1637, |
| 4593 | SHLL_PH_MM = 1638, |
| 4594 | SHLL_QB_MM = 1639, |
| 4595 | SHLL_S_PH_MM = 1640, |
| 4596 | SHLL_S_W_MM = 1641, |
| 4597 | SHRAV_PH_MM = 1642, |
| 4598 | SHRAV_R_PH_MM = 1643, |
| 4599 | SHRAV_R_W_MM = 1644, |
| 4600 | SHRA_PH_MM = 1645, |
| 4601 | SHRA_R_PH_MM = 1646, |
| 4602 | SHRA_R_W_MM = 1647, |
| 4603 | SHRLV_QB_MM = 1648, |
| 4604 | SHRL_QB_MM = 1649, |
| 4605 | SUBQ_PH_MM = 1650, |
| 4606 | SUBQ_S_PH_MM = 1651, |
| 4607 | SUBQ_S_W_MM = 1652, |
| 4608 | SUBU_QB_MM = 1653, |
| 4609 | SUBU_S_QB_MM = 1654, |
| 4610 | WRDSP_MM = 1655, |
| 4611 | ABSQ_S_QB_MMR2 = 1656, |
| 4612 | ADDQH_PH_MMR2 = 1657, |
| 4613 | ADDQH_R_PH_MMR2 = 1658, |
| 4614 | ADDQH_R_W_MMR2 = 1659, |
| 4615 | ADDQH_W_MMR2 = 1660, |
| 4616 | ADDUH_QB_MMR2 = 1661, |
| 4617 | ADDUH_R_QB_MMR2 = 1662, |
| 4618 | ADDU_PH_MMR2 = 1663, |
| 4619 | ADDU_S_PH_MMR2 = 1664, |
| 4620 | APPEND_MMR2 = 1665, |
| 4621 | BALIGN_MMR2 = 1666, |
| 4622 | CMPGDU_EQ_QB_MMR2 = 1667, |
| 4623 | CMPGDU_LE_QB_MMR2 = 1668, |
| 4624 | CMPGDU_LT_QB_MMR2 = 1669, |
| 4625 | DPA_W_PH_MMR2 = 1670, |
| 4626 | DPAQX_SA_W_PH_MMR2 = 1671, |
| 4627 | DPAQX_S_W_PH_MMR2 = 1672, |
| 4628 | DPAX_W_PH_MMR2 = 1673, |
| 4629 | DPS_W_PH_MMR2 = 1674, |
| 4630 | DPSQX_S_W_PH_MMR2 = 1675, |
| 4631 | DPSQX_SA_W_PH_MMR2 = 1676, |
| 4632 | DPSX_W_PH_MMR2 = 1677, |
| 4633 | MUL_PH_MMR2 = 1678, |
| 4634 | MUL_S_PH_MMR2 = 1679, |
| 4635 | MULQ_RS_W_MMR2 = 1680, |
| 4636 | MULQ_S_PH_MMR2 = 1681, |
| 4637 | MULQ_S_W_MMR2 = 1682, |
| 4638 | MULSA_W_PH_MMR2 = 1683, |
| 4639 | PRECR_QB_PH_MMR2 = 1684, |
| 4640 | PRECR_SRA_PH_W_MMR2 = 1685, |
| 4641 | PRECR_SRA_R_PH_W_MMR2 = 1686, |
| 4642 | PREPEND_MMR2 = 1687, |
| 4643 | SHRA_QB_MMR2 = 1688, |
| 4644 | SHRA_R_QB_MMR2 = 1689, |
| 4645 | SHRAV_QB_MMR2 = 1690, |
| 4646 | SHRAV_R_QB_MMR2 = 1691, |
| 4647 | SHRL_PH_MMR2 = 1692, |
| 4648 | SHRLV_PH_MMR2 = 1693, |
| 4649 | SUBQH_PH_MMR2 = 1694, |
| 4650 | SUBQH_R_PH_MMR2 = 1695, |
| 4651 | SUBQH_W_MMR2 = 1696, |
| 4652 | SUBQH_R_W_MMR2 = 1697, |
| 4653 | SUBU_PH_MMR2 = 1698, |
| 4654 | SUBU_S_PH_MMR2 = 1699, |
| 4655 | SUBUH_QB_MMR2 = 1700, |
| 4656 | SUBUH_R_QB_MMR2 = 1701, |
| 4657 | BPOSGE32C_MMR3 = 1702, |
| 4658 | SCHED_LIST_END = 1703 |
| 4659 | }; |
| 4660 | |
| 4661 | } // namespace llvm::Mips::Sched |
| 4662 | |
| 4663 | #endif // GET_INSTRINFO_SCHED_ENUM |
| 4664 | |
| 4665 | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 4666 | |
| 4667 | namespace llvm { |
| 4668 | |
| 4669 | struct MipsInstrTable { |
| 4670 | MCInstrDesc Insts[2921]; |
| 4671 | static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps"); |
| 4672 | MCPhysReg ImplicitOps[68]; |
| 4673 | char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)]; |
| 4674 | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
| 4675 | MCOperandInfo OperandInfo[1150]; |
| 4676 | }; |
| 4677 | } // namespace llvm |
| 4678 | |
| 4679 | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 4680 | |
| 4681 | #ifdef GET_INSTRINFO_MC_DESC |
| 4682 | #undef GET_INSTRINFO_MC_DESC |
| 4683 | |
| 4684 | namespace llvm { |
| 4685 | |
| 4686 | static_assert((sizeof MipsInstrTable::ImplicitOps + sizeof MipsInstrTable::Padding) % sizeof(MCOperandInfo) == 0); |
| 4687 | static constexpr unsigned MipsOpInfoBase = (sizeof MipsInstrTable::ImplicitOps + sizeof MipsInstrTable::Padding) / sizeof(MCOperandInfo); |
| 4688 | |
| 4689 | extern const MipsInstrTable MipsDescs = { |
| 4690 | { |
| 4691 | { 2920, 2, 1, 4, 1144, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // YIELD |
| 4692 | { 2919, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 591, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // XorRxRxRy16 |
| 4693 | { 2918, 3, 1, 4, 932, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // XORi_MM |
| 4694 | { 2917, 3, 1, 4, 524, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // XORi64 |
| 4695 | { 2916, 3, 1, 4, 525, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // XORi |
| 4696 | { 2915, 3, 1, 4, 791, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // XOR_V |
| 4697 | { 2914, 3, 1, 4, 963, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // XOR_MMR6 |
| 4698 | { 2913, 3, 1, 4, 931, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // XOR_MM |
| 4699 | { 2912, 3, 1, 4, 964, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // XORI_MMR6 |
| 4700 | { 2911, 3, 1, 4, 591, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // XORI_B |
| 4701 | { 2910, 3, 1, 4, 524, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // XOR64 |
| 4702 | { 2909, 3, 1, 2, 963, 0, 0, MipsOpInfoBase + 576, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XOR16_MMR6 |
| 4703 | { 2908, 3, 1, 2, 931, 0, 0, MipsOpInfoBase + 576, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // XOR16_MM |
| 4704 | { 2907, 3, 1, 4, 678, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // XOR |
| 4705 | { 2906, 2, 1, 4, 962, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x6ULL }, // WSBH_MMR6 |
| 4706 | { 2905, 2, 1, 4, 930, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // WSBH_MM |
| 4707 | { 2904, 2, 1, 4, 523, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // WSBH |
| 4708 | { 2903, 2, 1, 4, 1120, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x6ULL }, // WRPGPR_MMR6 |
| 4709 | { 2902, 2, 0, 4, 1655, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // WRDSP_MM |
| 4710 | { 2901, 2, 0, 4, 1489, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // WRDSP |
| 4711 | { 2900, 1, 0, 4, 1135, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // WAIT_MMR6 |
| 4712 | { 2899, 1, 0, 4, 1118, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // WAIT_MM |
| 4713 | { 2898, 0, 0, 4, 443, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // WAIT |
| 4714 | { 2897, 4, 1, 4, 770, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // VSHF_W |
| 4715 | { 2896, 4, 1, 4, 770, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // VSHF_H |
| 4716 | { 2895, 4, 1, 4, 770, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // VSHF_D |
| 4717 | { 2894, 4, 1, 4, 770, 0, 0, MipsOpInfoBase + 621, 0, 0, 0x6ULL }, // VSHF_B |
| 4718 | { 2893, 3, 1, 4, 1260, 0, 5, MipsOpInfoBase + 238, 63, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // VMULU |
| 4719 | { 2892, 3, 1, 4, 1260, 0, 4, MipsOpInfoBase + 238, 43, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // VMM0 |
| 4720 | { 2891, 3, 1, 4, 1260, 0, 3, MipsOpInfoBase + 238, 60, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // V3MULU |
| 4721 | { 2890, 2, 0, 4, 997, 0, 2, MipsOpInfoBase + 155, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // UDIV_MM |
| 4722 | { 2889, 2, 0, 4, 753, 0, 2, MipsOpInfoBase + 155, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // UDIV |
| 4723 | { 2888, 2, 0, 4, 696, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TTLTIU |
| 4724 | { 2887, 2, 1, 4, 1342, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_S_MMR6 |
| 4725 | { 2886, 2, 1, 4, 1290, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_S_MM |
| 4726 | { 2885, 2, 1, 4, 645, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_S |
| 4727 | { 2884, 2, 1, 4, 1290, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_MM |
| 4728 | { 2883, 2, 1, 4, 1342, 0, 0, MipsOpInfoBase + 644, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_D_MMR6 |
| 4729 | { 2882, 2, 1, 4, 645, 0, 0, MipsOpInfoBase + 644, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_D64 |
| 4730 | { 2881, 2, 1, 4, 645, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_W_D32 |
| 4731 | { 2880, 2, 1, 4, 1342, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_L_S_MMR6 |
| 4732 | { 2879, 2, 1, 4, 645, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_L_S |
| 4733 | { 2878, 2, 1, 4, 1342, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_L_D_MMR6 |
| 4734 | { 2877, 2, 1, 4, 645, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // TRUNC_L_D64 |
| 4735 | { 2876, 3, 0, 4, 1077, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TNE_MM |
| 4736 | { 2875, 2, 0, 4, 1076, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TNEI_MM |
| 4737 | { 2874, 2, 0, 4, 695, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TNEI |
| 4738 | { 2873, 3, 0, 4, 442, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TNE |
| 4739 | { 2872, 3, 0, 4, 1075, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TLT_MM |
| 4740 | { 2871, 3, 0, 4, 1074, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TLTU_MM |
| 4741 | { 2870, 3, 0, 4, 441, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TLTU |
| 4742 | { 2869, 2, 0, 4, 1073, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TLTI_MM |
| 4743 | { 2868, 2, 0, 4, 1072, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TLTIU_MM |
| 4744 | { 2867, 2, 0, 4, 694, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TLTI |
| 4745 | { 2866, 3, 0, 4, 440, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TLT |
| 4746 | { 2865, 0, 0, 4, 1113, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBWR_MM |
| 4747 | { 2864, 0, 0, 4, 379, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBWR |
| 4748 | { 2863, 0, 0, 4, 1112, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBWI_MM |
| 4749 | { 2862, 0, 0, 4, 378, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBWI |
| 4750 | { 2861, 0, 0, 4, 1111, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBR_MM |
| 4751 | { 2860, 0, 0, 4, 377, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBR |
| 4752 | { 2859, 0, 0, 4, 1110, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBP_MM |
| 4753 | { 2858, 0, 0, 4, 376, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBP |
| 4754 | { 2857, 0, 0, 4, 1121, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBINV_MMR6 |
| 4755 | { 2856, 0, 0, 4, 1122, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBINVF_MMR6 |
| 4756 | { 2855, 0, 0, 4, 381, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBINVF |
| 4757 | { 2854, 0, 0, 4, 380, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBINV |
| 4758 | { 2853, 0, 0, 4, 1154, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGWR_MM |
| 4759 | { 2852, 0, 0, 4, 710, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGWR |
| 4760 | { 2851, 0, 0, 4, 1153, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGWI_MM |
| 4761 | { 2850, 0, 0, 4, 709, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGWI |
| 4762 | { 2849, 0, 0, 4, 1152, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGR_MM |
| 4763 | { 2848, 0, 0, 4, 708, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGR |
| 4764 | { 2847, 0, 0, 4, 1151, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGP_MM |
| 4765 | { 2846, 0, 0, 4, 707, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGP |
| 4766 | { 2845, 0, 0, 4, 1150, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGINV_MM |
| 4767 | { 2844, 0, 0, 4, 1149, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGINVF_MM |
| 4768 | { 2843, 0, 0, 4, 706, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGINVF |
| 4769 | { 2842, 0, 0, 4, 705, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // TLBGINV |
| 4770 | { 2841, 3, 0, 4, 1071, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TGE_MM |
| 4771 | { 2840, 3, 0, 4, 1070, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TGEU_MM |
| 4772 | { 2839, 3, 0, 4, 528, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TGEU |
| 4773 | { 2838, 2, 0, 4, 1069, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TGEI_MM |
| 4774 | { 2837, 2, 0, 4, 1068, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TGEIU_MM |
| 4775 | { 2836, 2, 0, 4, 693, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TGEIU |
| 4776 | { 2835, 2, 0, 4, 692, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TGEI |
| 4777 | { 2834, 3, 0, 4, 527, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TGE |
| 4778 | { 2833, 3, 0, 4, 1067, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TEQ_MM |
| 4779 | { 2832, 2, 0, 4, 1066, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TEQI_MM |
| 4780 | { 2831, 2, 0, 4, 691, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // TEQI |
| 4781 | { 2830, 3, 0, 4, 526, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // TEQ |
| 4782 | { 2829, 3, 0, 4, 1190, 0, 0, MipsOpInfoBase + 588, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // SwRxSpImmX16 |
| 4783 | { 2828, 3, 0, 4, 1190, 0, 0, MipsOpInfoBase + 929, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SwRxRyOffMemX16 |
| 4784 | { 2827, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // SubuRxRyRz16 |
| 4785 | { 2826, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 591, 0, 0, 0x0ULL }, // SrlvRxRy16 |
| 4786 | { 2825, 3, 1, 4, 894, 0, 0, MipsOpInfoBase + 535, 0, 0, 0x0ULL }, // SrlX16 |
| 4787 | { 2824, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 591, 0, 0, 0x0ULL }, // SravRxRy16 |
| 4788 | { 2823, 3, 1, 4, 894, 0, 0, MipsOpInfoBase + 535, 0, 0, 0x0ULL }, // SraX16 |
| 4789 | { 2822, 2, 0, 2, 894, 0, 1, MipsOpInfoBase + 409, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltuRxRy16 |
| 4790 | { 2821, 2, 0, 4, 894, 0, 1, MipsOpInfoBase + 583, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltiuRxImmX16 |
| 4791 | { 2820, 2, 0, 2, 894, 0, 1, MipsOpInfoBase + 583, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltiuRxImm16 |
| 4792 | { 2819, 2, 0, 4, 894, 0, 1, MipsOpInfoBase + 583, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltiRxImmX16 |
| 4793 | { 2818, 2, 0, 2, 894, 0, 1, MipsOpInfoBase + 583, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltiRxImm16 |
| 4794 | { 2817, 2, 0, 2, 894, 0, 1, MipsOpInfoBase + 409, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltRxRy16 |
| 4795 | { 2816, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 591, 0, 0, 0x0ULL }, // SllvRxRy16 |
| 4796 | { 2815, 3, 1, 4, 894, 0, 0, MipsOpInfoBase + 535, 0, 0, 0x0ULL }, // SllX16 |
| 4797 | { 2814, 3, 0, 4, 1189, 0, 0, MipsOpInfoBase + 929, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // ShRxRyOffMemX16 |
| 4798 | { 2813, 2, 1, 2, 894, 0, 0, MipsOpInfoBase + 1148, 0, 0, 0x0ULL }, // SehRx16 |
| 4799 | { 2812, 2, 1, 2, 894, 0, 0, MipsOpInfoBase + 1148, 0, 0, 0x0ULL }, // SebRx16 |
| 4800 | { 2811, 3, 0, 4, 1188, 0, 0, MipsOpInfoBase + 929, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // SbRxRyOffMemX16 |
| 4801 | { 2810, 0, 0, 2, 1187, 1, 1, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SaveX16 |
| 4802 | { 2809, 0, 0, 2, 1187, 1, 1, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Save16 |
| 4803 | { 2808, 1, 0, 4, 1065, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // SYSCALL_MM |
| 4804 | { 2807, 1, 0, 4, 424, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // SYSCALL |
| 4805 | { 2806, 1, 0, 4, 1232, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNC_MMR6 |
| 4806 | { 2805, 1, 0, 4, 1214, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNC_MM |
| 4807 | { 2804, 2, 0, 4, 1233, 0, 0, MipsOpInfoBase + 1146, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNCI_MMR6 |
| 4808 | { 2803, 2, 0, 4, 1215, 0, 0, MipsOpInfoBase + 1146, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNCI_MM |
| 4809 | { 2802, 2, 0, 4, 375, 0, 0, MipsOpInfoBase + 1146, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNCI |
| 4810 | { 2801, 1, 0, 4, 411, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SYNC |
| 4811 | { 2800, 3, 0, 4, 1229, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SW_MMR6 |
| 4812 | { 2799, 3, 0, 4, 1206, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SW_MM |
| 4813 | { 2798, 3, 0, 4, 1327, 0, 0, MipsOpInfoBase + 926, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWXC1_MM |
| 4814 | { 2797, 3, 0, 4, 882, 0, 0, MipsOpInfoBase + 926, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWXC1 |
| 4815 | { 2796, 3, 0, 2, 1229, 0, 0, MipsOpInfoBase + 923, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWSP_MMR6 |
| 4816 | { 2795, 3, 0, 2, 1206, 0, 0, MipsOpInfoBase + 923, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWSP_MM |
| 4817 | { 2794, 3, 0, 4, 1211, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWR_MM |
| 4818 | { 2793, 3, 0, 4, 1177, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWRE_MM |
| 4819 | { 2792, 3, 0, 4, 741, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SWRE |
| 4820 | { 2791, 3, 0, 4, 408, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWR64 |
| 4821 | { 2790, 3, 0, 4, 739, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWR |
| 4822 | { 2789, 4, 0, 4, 1210, 0, 0, MipsOpInfoBase + 919, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWP_MM |
| 4823 | { 2788, 3, 0, 4, 1208, 0, 0, MipsOpInfoBase + 364, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWM32_MM |
| 4824 | { 2787, 3, 0, 2, 1231, 0, 0, MipsOpInfoBase + 916, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWM16_MMR6 |
| 4825 | { 2786, 3, 0, 2, 1208, 0, 0, MipsOpInfoBase + 916, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWM16_MM |
| 4826 | { 2785, 3, 0, 4, 1207, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWL_MM |
| 4827 | { 2784, 3, 0, 4, 1176, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWLE_MM |
| 4828 | { 2783, 3, 0, 4, 740, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SWLE |
| 4829 | { 2782, 3, 0, 4, 407, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWL64 |
| 4830 | { 2781, 3, 0, 4, 738, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SWL |
| 4831 | { 2780, 3, 0, 4, 1175, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWE_MM |
| 4832 | { 2779, 3, 0, 4, 736, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SWE |
| 4833 | { 2778, 3, 0, 4, 1539, 0, 0, MipsOpInfoBase + 906, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWDSP_MM |
| 4834 | { 2777, 3, 0, 4, 1374, 0, 0, MipsOpInfoBase + 906, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SWDSP |
| 4835 | { 2776, 3, 0, 4, 731, 0, 0, MipsOpInfoBase + 864, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWC3 |
| 4836 | { 2775, 3, 0, 4, 370, 0, 0, MipsOpInfoBase + 858, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SWC2_R6 |
| 4837 | { 2774, 3, 0, 4, 1230, 0, 0, MipsOpInfoBase + 861, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // SWC2_MMR6 |
| 4838 | { 2773, 3, 0, 4, 730, 0, 0, MipsOpInfoBase + 858, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWC2 |
| 4839 | { 2772, 3, 0, 4, 1325, 0, 0, MipsOpInfoBase + 903, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWC1_MM |
| 4840 | { 2771, 3, 0, 4, 369, 0, 0, MipsOpInfoBase + 903, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SWC1 |
| 4841 | { 2770, 3, 0, 4, 406, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SW64 |
| 4842 | { 2769, 3, 0, 2, 1229, 0, 0, MipsOpInfoBase + 1076, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // SW16_MMR6 |
| 4843 | { 2768, 3, 0, 2, 1206, 0, 0, MipsOpInfoBase + 1076, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // SW16_MM |
| 4844 | { 2767, 3, 0, 4, 367, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SW |
| 4845 | { 2766, 3, 0, 4, 1326, 0, 0, MipsOpInfoBase + 882, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // SUXC1_MM |
| 4846 | { 2765, 3, 0, 4, 883, 0, 0, MipsOpInfoBase + 882, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // SUXC164 |
| 4847 | { 2764, 3, 0, 4, 883, 0, 0, MipsOpInfoBase + 879, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // SUXC1 |
| 4848 | { 2763, 3, 1, 4, 928, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // SUBu_MM |
| 4849 | { 2762, 3, 1, 4, 522, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // SUBu |
| 4850 | { 2761, 3, 1, 4, 961, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SUB_MMR6 |
| 4851 | { 2760, 3, 1, 4, 929, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SUB_MM |
| 4852 | { 2759, 3, 1, 4, 580, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SUBV_W |
| 4853 | { 2758, 3, 1, 4, 580, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SUBV_H |
| 4854 | { 2757, 3, 1, 4, 580, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SUBV_D |
| 4855 | { 2756, 3, 1, 4, 580, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SUBV_B |
| 4856 | { 2755, 3, 1, 4, 829, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SUBVI_W |
| 4857 | { 2754, 3, 1, 4, 829, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SUBVI_H |
| 4858 | { 2753, 3, 1, 4, 829, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SUBVI_D |
| 4859 | { 2752, 3, 1, 4, 829, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SUBVI_B |
| 4860 | { 2751, 3, 1, 4, 1654, 0, 1, MipsOpInfoBase + 548, 10, 0, 0x6ULL }, // SUBU_S_QB_MM |
| 4861 | { 2750, 3, 1, 4, 1488, 0, 1, MipsOpInfoBase + 548, 10, 0, 0x6ULL }, // SUBU_S_QB |
| 4862 | { 2749, 3, 1, 4, 1699, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_S_PH_MMR2 |
| 4863 | { 2748, 3, 1, 4, 1535, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_S_PH |
| 4864 | { 2747, 3, 1, 4, 1653, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_QB_MM |
| 4865 | { 2746, 3, 1, 4, 1487, 0, 1, MipsOpInfoBase + 548, 10, 0, 0x6ULL }, // SUBU_QB |
| 4866 | { 2745, 3, 1, 4, 1698, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_PH_MMR2 |
| 4867 | { 2744, 3, 1, 4, 1534, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBU_PH |
| 4868 | { 2743, 3, 1, 4, 960, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // SUBU_MMR6 |
| 4869 | { 2742, 3, 1, 4, 1701, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBUH_R_QB_MMR2 |
| 4870 | { 2741, 3, 1, 4, 1537, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBUH_R_QB |
| 4871 | { 2740, 3, 1, 4, 1700, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBUH_QB_MMR2 |
| 4872 | { 2739, 3, 1, 4, 1536, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBUH_QB |
| 4873 | { 2738, 3, 1, 2, 960, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x0ULL }, // SUBU16_MMR6 |
| 4874 | { 2737, 3, 1, 2, 928, 0, 0, MipsOpInfoBase + 557, 0, 0, 0x0ULL }, // SUBU16_MM |
| 4875 | { 2736, 3, 1, 4, 827, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SUBS_U_W |
| 4876 | { 2735, 3, 1, 4, 827, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SUBS_U_H |
| 4877 | { 2734, 3, 1, 4, 827, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SUBS_U_D |
| 4878 | { 2733, 3, 1, 4, 827, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SUBS_U_B |
| 4879 | { 2732, 3, 1, 4, 827, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SUBS_S_W |
| 4880 | { 2731, 3, 1, 4, 827, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SUBS_S_H |
| 4881 | { 2730, 3, 1, 4, 827, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SUBS_S_D |
| 4882 | { 2729, 3, 1, 4, 827, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SUBS_S_B |
| 4883 | { 2728, 3, 1, 4, 828, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SUBSUU_S_W |
| 4884 | { 2727, 3, 1, 4, 828, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SUBSUU_S_H |
| 4885 | { 2726, 3, 1, 4, 828, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SUBSUU_S_D |
| 4886 | { 2725, 3, 1, 4, 828, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SUBSUU_S_B |
| 4887 | { 2724, 3, 1, 4, 583, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SUBSUS_U_W |
| 4888 | { 2723, 3, 1, 4, 583, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SUBSUS_U_H |
| 4889 | { 2722, 3, 1, 4, 583, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SUBSUS_U_D |
| 4890 | { 2721, 3, 1, 4, 583, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SUBSUS_U_B |
| 4891 | { 2720, 3, 1, 4, 1652, 0, 1, MipsOpInfoBase + 241, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBQ_S_W_MM |
| 4892 | { 2719, 3, 1, 4, 1486, 0, 1, MipsOpInfoBase + 241, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBQ_S_W |
| 4893 | { 2718, 3, 1, 4, 1651, 0, 1, MipsOpInfoBase + 548, 10, 0, 0x6ULL }, // SUBQ_S_PH_MM |
| 4894 | { 2717, 3, 1, 4, 1485, 0, 1, MipsOpInfoBase + 548, 10, 0, 0x6ULL }, // SUBQ_S_PH |
| 4895 | { 2716, 3, 1, 4, 1650, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SUBQ_PH_MM |
| 4896 | { 2715, 3, 1, 4, 1484, 0, 1, MipsOpInfoBase + 548, 10, 0, 0x6ULL }, // SUBQ_PH |
| 4897 | { 2714, 3, 1, 4, 1696, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SUBQH_W_MMR2 |
| 4898 | { 2713, 3, 1, 4, 1532, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SUBQH_W |
| 4899 | { 2712, 3, 1, 4, 1697, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SUBQH_R_W_MMR2 |
| 4900 | { 2711, 3, 1, 4, 1533, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SUBQH_R_W |
| 4901 | { 2710, 3, 1, 4, 1695, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBQH_R_PH_MMR2 |
| 4902 | { 2709, 3, 1, 4, 1531, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBQH_R_PH |
| 4903 | { 2708, 3, 1, 4, 1694, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBQH_PH_MMR2 |
| 4904 | { 2707, 3, 1, 4, 1530, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // SUBQH_PH |
| 4905 | { 2706, 3, 1, 4, 521, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SUB |
| 4906 | { 2705, 3, 0, 4, 401, 0, 0, MipsOpInfoBase + 894, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // ST_W |
| 4907 | { 2704, 3, 0, 4, 401, 0, 0, MipsOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // ST_H |
| 4908 | { 2703, 3, 0, 4, 401, 0, 0, MipsOpInfoBase + 888, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // ST_D |
| 4909 | { 2702, 3, 0, 4, 401, 0, 0, MipsOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // ST_B |
| 4910 | { 2701, 0, 0, 4, 959, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SSNOP_MMR6 |
| 4911 | { 2700, 0, 0, 4, 927, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SSNOP_MM |
| 4912 | { 2699, 0, 0, 4, 520, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SSNOP |
| 4913 | { 2698, 3, 1, 4, 836, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SRL_W |
| 4914 | { 2697, 3, 1, 4, 925, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x1ULL }, // SRL_MM |
| 4915 | { 2696, 3, 1, 4, 836, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SRL_H |
| 4916 | { 2695, 3, 1, 4, 836, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SRL_D |
| 4917 | { 2694, 3, 1, 4, 836, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SRL_B |
| 4918 | { 2693, 3, 1, 4, 926, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SRLV_MM |
| 4919 | { 2692, 3, 1, 4, 519, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SRLV |
| 4920 | { 2691, 3, 1, 4, 838, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SRLR_W |
| 4921 | { 2690, 3, 1, 4, 838, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SRLR_H |
| 4922 | { 2689, 3, 1, 4, 838, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SRLR_D |
| 4923 | { 2688, 3, 1, 4, 838, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SRLR_B |
| 4924 | { 2687, 3, 1, 4, 838, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SRLRI_W |
| 4925 | { 2686, 3, 1, 4, 838, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SRLRI_H |
| 4926 | { 2685, 3, 1, 4, 838, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SRLRI_D |
| 4927 | { 2684, 3, 1, 4, 838, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SRLRI_B |
| 4928 | { 2683, 3, 1, 4, 836, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SRLI_W |
| 4929 | { 2682, 3, 1, 4, 836, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SRLI_H |
| 4930 | { 2681, 3, 1, 4, 836, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SRLI_D |
| 4931 | { 2680, 3, 1, 4, 836, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SRLI_B |
| 4932 | { 2679, 3, 1, 2, 958, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SRL16_MMR6 |
| 4933 | { 2678, 3, 1, 2, 925, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x0ULL }, // SRL16_MM |
| 4934 | { 2677, 3, 1, 4, 518, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x1ULL }, // SRL |
| 4935 | { 2676, 3, 1, 4, 835, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SRA_W |
| 4936 | { 2675, 3, 1, 4, 924, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x1ULL }, // SRA_MM |
| 4937 | { 2674, 3, 1, 4, 835, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SRA_H |
| 4938 | { 2673, 3, 1, 4, 835, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SRA_D |
| 4939 | { 2672, 3, 1, 4, 835, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SRA_B |
| 4940 | { 2671, 3, 1, 4, 923, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SRAV_MM |
| 4941 | { 2670, 3, 1, 4, 517, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SRAV |
| 4942 | { 2669, 3, 1, 4, 837, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SRAR_W |
| 4943 | { 2668, 3, 1, 4, 837, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SRAR_H |
| 4944 | { 2667, 3, 1, 4, 837, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SRAR_D |
| 4945 | { 2666, 3, 1, 4, 837, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SRAR_B |
| 4946 | { 2665, 3, 1, 4, 837, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SRARI_W |
| 4947 | { 2664, 3, 1, 4, 837, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SRARI_H |
| 4948 | { 2663, 3, 1, 4, 837, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SRARI_D |
| 4949 | { 2662, 3, 1, 4, 837, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SRARI_B |
| 4950 | { 2661, 3, 1, 4, 835, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SRAI_W |
| 4951 | { 2660, 3, 1, 4, 835, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SRAI_H |
| 4952 | { 2659, 3, 1, 4, 835, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SRAI_D |
| 4953 | { 2658, 3, 1, 4, 835, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SRAI_B |
| 4954 | { 2657, 3, 1, 4, 516, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x1ULL }, // SRA |
| 4955 | { 2656, 3, 1, 4, 605, 0, 0, MipsOpInfoBase + 1143, 0, 0, 0x6ULL }, // SPLAT_W |
| 4956 | { 2655, 3, 1, 4, 605, 0, 0, MipsOpInfoBase + 1140, 0, 0, 0x6ULL }, // SPLAT_H |
| 4957 | { 2654, 3, 1, 4, 605, 0, 0, MipsOpInfoBase + 1137, 0, 0, 0x6ULL }, // SPLAT_D |
| 4958 | { 2653, 3, 1, 4, 605, 0, 0, MipsOpInfoBase + 1134, 0, 0, 0x6ULL }, // SPLAT_B |
| 4959 | { 2652, 3, 1, 4, 606, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SPLATI_W |
| 4960 | { 2651, 3, 1, 4, 606, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SPLATI_H |
| 4961 | { 2650, 3, 1, 4, 606, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SPLATI_D |
| 4962 | { 2649, 3, 1, 4, 606, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SPLATI_B |
| 4963 | { 2648, 3, 1, 4, 1259, 0, 0, MipsOpInfoBase + 235, 0, 0, 0x2ULL }, // SNEi |
| 4964 | { 2647, 3, 1, 4, 1258, 0, 0, MipsOpInfoBase + 238, 0, 0, 0x1ULL }, // SNE |
| 4965 | { 2646, 3, 1, 4, 921, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SLTu_MM |
| 4966 | { 2645, 3, 1, 4, 514, 0, 0, MipsOpInfoBase + 1128, 0, 0, 0x1ULL }, // SLTu64 |
| 4967 | { 2644, 3, 1, 4, 767, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SLTu |
| 4968 | { 2643, 3, 1, 4, 922, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x2ULL }, // SLTiu_MM |
| 4969 | { 2642, 3, 1, 4, 515, 0, 0, MipsOpInfoBase + 1131, 0, 0, 0x2ULL }, // SLTiu64 |
| 4970 | { 2641, 3, 1, 4, 677, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x2ULL }, // SLTiu |
| 4971 | { 2640, 3, 1, 4, 922, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x2ULL }, // SLTi_MM |
| 4972 | { 2639, 3, 1, 4, 515, 0, 0, MipsOpInfoBase + 1131, 0, 0, 0x2ULL }, // SLTi64 |
| 4973 | { 2638, 3, 1, 4, 677, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x2ULL }, // SLTi |
| 4974 | { 2637, 3, 1, 4, 921, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SLT_MM |
| 4975 | { 2636, 3, 1, 4, 514, 0, 0, MipsOpInfoBase + 1128, 0, 0, 0x1ULL }, // SLT64 |
| 4976 | { 2635, 3, 1, 4, 767, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SLT |
| 4977 | { 2634, 3, 1, 4, 839, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // SLL_W |
| 4978 | { 2633, 3, 1, 4, 957, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SLL_MMR6 |
| 4979 | { 2632, 3, 1, 4, 919, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x1ULL }, // SLL_MM |
| 4980 | { 2631, 3, 1, 4, 839, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // SLL_H |
| 4981 | { 2630, 3, 1, 4, 839, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // SLL_D |
| 4982 | { 2629, 3, 1, 4, 839, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // SLL_B |
| 4983 | { 2628, 3, 1, 4, 920, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SLLV_MM |
| 4984 | { 2627, 3, 1, 4, 513, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // SLLV |
| 4985 | { 2626, 3, 1, 4, 839, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SLLI_W |
| 4986 | { 2625, 3, 1, 4, 839, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SLLI_H |
| 4987 | { 2624, 3, 1, 4, 839, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SLLI_D |
| 4988 | { 2623, 3, 1, 4, 839, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SLLI_B |
| 4989 | { 2622, 2, 1, 4, 512, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // SLL64_64 |
| 4990 | { 2621, 2, 1, 4, 512, 0, 0, MipsOpInfoBase + 761, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // SLL64_32 |
| 4991 | { 2620, 3, 1, 2, 957, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLL16_MMR6 |
| 4992 | { 2619, 3, 1, 2, 919, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x0ULL }, // SLL16_MM |
| 4993 | { 2618, 3, 1, 4, 768, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x1ULL }, // SLL |
| 4994 | { 2617, 4, 1, 4, 774, 0, 0, MipsOpInfoBase + 1124, 0, 0, 0x6ULL }, // SLD_W |
| 4995 | { 2616, 4, 1, 4, 774, 0, 0, MipsOpInfoBase + 1120, 0, 0, 0x6ULL }, // SLD_H |
| 4996 | { 2615, 4, 1, 4, 774, 0, 0, MipsOpInfoBase + 1116, 0, 0, 0x6ULL }, // SLD_D |
| 4997 | { 2614, 4, 1, 4, 774, 0, 0, MipsOpInfoBase + 1112, 0, 0, 0x6ULL }, // SLD_B |
| 4998 | { 2613, 4, 1, 4, 774, 0, 0, MipsOpInfoBase + 617, 0, 0, 0x6ULL }, // SLDI_W |
| 4999 | { 2612, 4, 1, 4, 774, 0, 0, MipsOpInfoBase + 613, 0, 0, 0x6ULL }, // SLDI_H |
| 5000 | { 2611, 4, 1, 4, 774, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // SLDI_D |
| 5001 | { 2610, 4, 1, 4, 774, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // SLDI_B |
| 5002 | { 2609, 1, 0, 4, 1093, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SIGRIE_MMR6 |
| 5003 | { 2608, 1, 0, 4, 1033, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SIGRIE |
| 5004 | { 2607, 3, 0, 4, 1228, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SH_MMR6 |
| 5005 | { 2606, 3, 0, 4, 1205, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SH_MM |
| 5006 | { 2605, 3, 1, 4, 1649, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRL_QB_MM |
| 5007 | { 2604, 3, 1, 4, 1483, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRL_QB |
| 5008 | { 2603, 3, 1, 4, 1692, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRL_PH_MMR2 |
| 5009 | { 2602, 3, 1, 4, 1528, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRL_PH |
| 5010 | { 2601, 3, 1, 4, 1648, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRLV_QB_MM |
| 5011 | { 2600, 3, 1, 4, 1482, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRLV_QB |
| 5012 | { 2599, 3, 1, 4, 1693, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRLV_PH_MMR2 |
| 5013 | { 2598, 3, 1, 4, 1529, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRLV_PH |
| 5014 | { 2597, 3, 1, 4, 1647, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_W_MM |
| 5015 | { 2596, 3, 1, 4, 1481, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_W |
| 5016 | { 2595, 3, 1, 4, 1689, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_QB_MMR2 |
| 5017 | { 2594, 3, 1, 4, 1525, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_QB |
| 5018 | { 2593, 3, 1, 4, 1646, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_PH_MM |
| 5019 | { 2592, 3, 1, 4, 1480, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_R_PH |
| 5020 | { 2591, 3, 1, 4, 1688, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_QB_MMR2 |
| 5021 | { 2590, 3, 1, 4, 1524, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_QB |
| 5022 | { 2589, 3, 1, 4, 1645, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_PH_MM |
| 5023 | { 2588, 3, 1, 4, 1479, 0, 0, MipsOpInfoBase + 1109, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHRA_PH |
| 5024 | { 2587, 3, 1, 4, 1644, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SHRAV_R_W_MM |
| 5025 | { 2586, 3, 1, 4, 1478, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SHRAV_R_W |
| 5026 | { 2585, 3, 1, 4, 1691, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRAV_R_QB_MMR2 |
| 5027 | { 2584, 3, 1, 4, 1527, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRAV_R_QB |
| 5028 | { 2583, 3, 1, 4, 1643, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRAV_R_PH_MM |
| 5029 | { 2582, 3, 1, 4, 1477, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRAV_R_PH |
| 5030 | { 2581, 3, 1, 4, 1690, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRAV_QB_MMR2 |
| 5031 | { 2580, 3, 1, 4, 1526, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRAV_QB |
| 5032 | { 2579, 3, 1, 4, 1642, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRAV_PH_MM |
| 5033 | { 2578, 3, 1, 4, 1476, 0, 0, MipsOpInfoBase + 1106, 0, 0, 0x6ULL }, // SHRAV_PH |
| 5034 | { 2577, 3, 1, 4, 1641, 0, 1, MipsOpInfoBase + 244, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_S_W_MM |
| 5035 | { 2576, 3, 1, 4, 1475, 0, 1, MipsOpInfoBase + 244, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_S_W |
| 5036 | { 2575, 3, 1, 4, 1640, 0, 1, MipsOpInfoBase + 1109, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_S_PH_MM |
| 5037 | { 2574, 3, 1, 4, 1474, 0, 1, MipsOpInfoBase + 1109, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_S_PH |
| 5038 | { 2573, 3, 1, 4, 1639, 0, 1, MipsOpInfoBase + 1109, 59, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_QB_MM |
| 5039 | { 2572, 3, 1, 4, 1473, 0, 1, MipsOpInfoBase + 1109, 59, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_QB |
| 5040 | { 2571, 3, 1, 4, 1638, 0, 1, MipsOpInfoBase + 1109, 59, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_PH_MM |
| 5041 | { 2570, 3, 1, 4, 1472, 0, 1, MipsOpInfoBase + 1109, 59, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLL_PH |
| 5042 | { 2569, 3, 1, 4, 1637, 0, 1, MipsOpInfoBase + 241, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_S_W_MM |
| 5043 | { 2568, 3, 1, 4, 1471, 0, 1, MipsOpInfoBase + 241, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_S_W |
| 5044 | { 2567, 3, 1, 4, 1636, 0, 1, MipsOpInfoBase + 1106, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_S_PH_MM |
| 5045 | { 2566, 3, 1, 4, 1470, 0, 1, MipsOpInfoBase + 1106, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_S_PH |
| 5046 | { 2565, 3, 1, 4, 1635, 0, 1, MipsOpInfoBase + 1106, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_QB_MM |
| 5047 | { 2564, 3, 1, 4, 1469, 0, 1, MipsOpInfoBase + 1106, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_QB |
| 5048 | { 2563, 3, 1, 4, 1634, 0, 1, MipsOpInfoBase + 1106, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_PH_MM |
| 5049 | { 2562, 3, 1, 4, 1468, 0, 1, MipsOpInfoBase + 1106, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHLLV_PH |
| 5050 | { 2561, 3, 1, 4, 1633, 0, 0, MipsOpInfoBase + 1103, 0, 0, 0x6ULL }, // SHILO_MM |
| 5051 | { 2560, 3, 1, 4, 1632, 0, 0, MipsOpInfoBase + 1041, 0, 0, 0x6ULL }, // SHILOV_MM |
| 5052 | { 2559, 3, 1, 4, 1466, 0, 0, MipsOpInfoBase + 1041, 0, 0, 0x6ULL }, // SHILOV |
| 5053 | { 2558, 3, 1, 4, 1467, 0, 0, MipsOpInfoBase + 1103, 0, 0, 0x6ULL }, // SHILO |
| 5054 | { 2557, 3, 1, 4, 789, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SHF_W |
| 5055 | { 2556, 3, 1, 4, 789, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SHF_H |
| 5056 | { 2555, 3, 1, 4, 789, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SHF_B |
| 5057 | { 2554, 3, 0, 4, 1174, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SHE_MM |
| 5058 | { 2553, 3, 0, 4, 735, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SHE |
| 5059 | { 2552, 3, 0, 4, 405, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SH64 |
| 5060 | { 2551, 3, 0, 2, 1228, 0, 0, MipsOpInfoBase + 1076, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SH16_MMR6 |
| 5061 | { 2550, 3, 0, 2, 1205, 0, 0, MipsOpInfoBase + 1076, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SH16_MM |
| 5062 | { 2549, 3, 0, 4, 366, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SH |
| 5063 | { 2548, 3, 1, 4, 1259, 0, 0, MipsOpInfoBase + 235, 0, 0, 0x2ULL }, // SEQi |
| 5064 | { 2547, 3, 1, 4, 1258, 0, 0, MipsOpInfoBase + 238, 0, 0, 0x1ULL }, // SEQ |
| 5065 | { 2546, 4, 1, 4, 1361, 0, 0, MipsOpInfoBase + 1099, 0, 0, 0x6ULL }, // SEL_S_MMR6 |
| 5066 | { 2545, 4, 1, 4, 533, 0, 0, MipsOpInfoBase + 1099, 0, 0, 0x6ULL }, // SEL_S |
| 5067 | { 2544, 4, 1, 4, 1360, 0, 0, MipsOpInfoBase + 1095, 0, 0, 0x6ULL }, // SEL_D_MMR6 |
| 5068 | { 2543, 4, 1, 4, 532, 0, 0, MipsOpInfoBase + 1095, 0, 0, 0x6ULL }, // SEL_D |
| 5069 | { 2542, 3, 1, 4, 1359, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELNEZ_S_MMR6 |
| 5070 | { 2541, 3, 1, 4, 531, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELNEZ_S |
| 5071 | { 2540, 3, 1, 4, 956, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SELNEZ_MMR6 |
| 5072 | { 2539, 3, 1, 4, 1358, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELNEZ_D_MMR6 |
| 5073 | { 2538, 3, 1, 4, 530, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELNEZ_D |
| 5074 | { 2537, 3, 1, 4, 511, 0, 0, MipsOpInfoBase + 238, 0, 0, 0x6ULL }, // SELNEZ64 |
| 5075 | { 2536, 3, 1, 4, 893, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SELNEZ |
| 5076 | { 2535, 3, 1, 4, 1359, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELEQZ_S_MMR6 |
| 5077 | { 2534, 3, 1, 4, 531, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELEQZ_S |
| 5078 | { 2533, 3, 1, 4, 956, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SELEQZ_MMR6 |
| 5079 | { 2532, 3, 1, 4, 1358, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELEQZ_D_MMR6 |
| 5080 | { 2531, 3, 1, 4, 530, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SELEQZ_D |
| 5081 | { 2530, 3, 1, 4, 511, 0, 0, MipsOpInfoBase + 238, 0, 0, 0x6ULL }, // SELEQZ64 |
| 5082 | { 2529, 3, 1, 4, 893, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // SELEQZ |
| 5083 | { 2528, 2, 1, 4, 918, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // SEH_MM |
| 5084 | { 2527, 2, 1, 4, 510, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x1ULL }, // SEH64 |
| 5085 | { 2526, 2, 1, 4, 766, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // SEH |
| 5086 | { 2525, 2, 1, 4, 917, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // SEB_MM |
| 5087 | { 2524, 2, 1, 4, 509, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x1ULL }, // SEB64 |
| 5088 | { 2523, 2, 1, 4, 765, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // SEB |
| 5089 | { 2522, 3, 0, 4, 881, 0, 0, MipsOpInfoBase + 882, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDXC164 |
| 5090 | { 2521, 3, 0, 4, 881, 0, 0, MipsOpInfoBase + 879, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDXC1 |
| 5091 | { 2520, 3, 0, 4, 1241, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SDR |
| 5092 | { 2519, 3, 0, 4, 1240, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SDL |
| 5093 | { 2518, 2, 0, 4, 996, 0, 2, MipsOpInfoBase + 155, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SDIV_MM |
| 5094 | { 2517, 2, 0, 4, 752, 0, 2, MipsOpInfoBase + 155, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SDIV |
| 5095 | { 2516, 3, 0, 4, 372, 0, 0, MipsOpInfoBase + 864, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC3 |
| 5096 | { 2515, 3, 0, 4, 371, 0, 0, MipsOpInfoBase + 858, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SDC2_R6 |
| 5097 | { 2514, 3, 0, 4, 1227, 0, 0, MipsOpInfoBase + 861, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // SDC2_MMR6 |
| 5098 | { 2513, 3, 0, 4, 732, 0, 0, MipsOpInfoBase + 858, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC2 |
| 5099 | { 2512, 3, 0, 4, 1324, 0, 0, MipsOpInfoBase + 855, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC1_MM_D64 |
| 5100 | { 2511, 3, 0, 4, 1324, 0, 0, MipsOpInfoBase + 507, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC1_MM_D32 |
| 5101 | { 2510, 3, 0, 4, 1372, 0, 0, MipsOpInfoBase + 855, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // SDC1_D64_MMR6 |
| 5102 | { 2509, 3, 0, 4, 368, 0, 0, MipsOpInfoBase + 855, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC164 |
| 5103 | { 2508, 3, 0, 4, 368, 0, 0, MipsOpInfoBase + 507, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // SDC1 |
| 5104 | { 2507, 1, 0, 4, 423, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // SDBBP_R6 |
| 5105 | { 2506, 1, 0, 4, 1105, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SDBBP_MMR6 |
| 5106 | { 2505, 1, 0, 4, 1064, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // SDBBP_MM |
| 5107 | { 2504, 1, 0, 2, 1105, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDBBP16_MMR6 |
| 5108 | { 2503, 1, 0, 2, 1064, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDBBP16_MM |
| 5109 | { 2502, 1, 0, 4, 690, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // SDBBP |
| 5110 | { 2501, 3, 0, 4, 365, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SD |
| 5111 | { 2500, 4, 1, 4, 1161, 0, 0, MipsOpInfoBase + 1083, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SC_R6 |
| 5112 | { 2499, 4, 1, 4, 1159, 0, 0, MipsOpInfoBase + 1079, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SC_MMR6 |
| 5113 | { 2498, 4, 1, 4, 1204, 0, 0, MipsOpInfoBase + 1079, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SC_MM |
| 5114 | { 2497, 4, 1, 4, 1178, 0, 0, MipsOpInfoBase + 1079, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SCE_MM |
| 5115 | { 2496, 4, 1, 4, 737, 0, 0, MipsOpInfoBase + 1079, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SCE |
| 5116 | { 2495, 4, 1, 4, 374, 0, 0, MipsOpInfoBase + 1091, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SCD_R6 |
| 5117 | { 2494, 4, 1, 4, 1239, 0, 0, MipsOpInfoBase + 1087, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SCD |
| 5118 | { 2493, 4, 1, 4, 373, 0, 0, MipsOpInfoBase + 1083, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SC64_R6 |
| 5119 | { 2492, 4, 1, 4, 1239, 0, 0, MipsOpInfoBase + 1079, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SC64 |
| 5120 | { 2491, 4, 1, 4, 733, 0, 0, MipsOpInfoBase + 1079, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SC |
| 5121 | { 2490, 3, 0, 4, 1226, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SB_MMR6 |
| 5122 | { 2489, 3, 0, 4, 1173, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SB_MM |
| 5123 | { 2488, 3, 0, 4, 1172, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // SBE_MM |
| 5124 | { 2487, 3, 0, 4, 734, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // SBE |
| 5125 | { 2486, 3, 0, 4, 404, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SB64 |
| 5126 | { 2485, 3, 0, 2, 1226, 0, 0, MipsOpInfoBase + 1076, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SB16_MMR6 |
| 5127 | { 2484, 3, 0, 2, 1203, 0, 0, MipsOpInfoBase + 1076, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SB16_MM |
| 5128 | { 2483, 3, 0, 4, 364, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // SB |
| 5129 | { 2482, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SAT_U_W |
| 5130 | { 2481, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SAT_U_H |
| 5131 | { 2480, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SAT_U_D |
| 5132 | { 2479, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SAT_U_B |
| 5133 | { 2478, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // SAT_S_W |
| 5134 | { 2477, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // SAT_S_H |
| 5135 | { 2476, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // SAT_S_D |
| 5136 | { 2475, 3, 1, 4, 589, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // SAT_S_B |
| 5137 | { 2474, 2, 0, 4, 1262, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SAAD |
| 5138 | { 2473, 2, 0, 4, 1262, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // SAA |
| 5139 | { 2472, 0, 0, 2, 1181, 1, 1, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RestoreX16 |
| 5140 | { 2471, 0, 0, 2, 1181, 1, 1, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Restore16 |
| 5141 | { 2470, 2, 1, 4, 1322, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_S_MM |
| 5142 | { 2469, 2, 1, 4, 576, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_S |
| 5143 | { 2468, 2, 1, 4, 1323, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_D64_MM |
| 5144 | { 2467, 2, 1, 4, 577, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_D64 |
| 5145 | { 2466, 2, 1, 4, 1323, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_D32_MM |
| 5146 | { 2465, 2, 1, 4, 577, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RSQRT_D32 |
| 5147 | { 2464, 2, 1, 4, 1343, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_S_MMR6 |
| 5148 | { 2463, 2, 1, 4, 1289, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_S_MM |
| 5149 | { 2462, 2, 1, 4, 647, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_S |
| 5150 | { 2461, 2, 1, 4, 1289, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_MM |
| 5151 | { 2460, 2, 1, 4, 1343, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_D_MMR6 |
| 5152 | { 2459, 2, 1, 4, 647, 0, 0, MipsOpInfoBase + 644, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_D64 |
| 5153 | { 2458, 2, 1, 4, 647, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_W_D32 |
| 5154 | { 2457, 2, 1, 4, 1343, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_L_S_MMR6 |
| 5155 | { 2456, 2, 1, 4, 647, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_L_S |
| 5156 | { 2455, 2, 1, 4, 1343, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_L_D_MMR6 |
| 5157 | { 2454, 2, 1, 4, 647, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // ROUND_L_D64 |
| 5158 | { 2453, 3, 1, 4, 916, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x1ULL }, // ROTR_MM |
| 5159 | { 2452, 3, 1, 4, 915, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // ROTRV_MM |
| 5160 | { 2451, 3, 1, 4, 508, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x1ULL }, // ROTRV |
| 5161 | { 2450, 3, 1, 4, 507, 0, 0, MipsOpInfoBase + 244, 0, 0, 0x1ULL }, // ROTR |
| 5162 | { 2449, 2, 1, 4, 1362, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RINT_S_MMR6 |
| 5163 | { 2448, 2, 1, 4, 652, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RINT_S |
| 5164 | { 2447, 2, 1, 4, 1362, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RINT_D_MMR6 |
| 5165 | { 2446, 2, 1, 4, 651, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RINT_D |
| 5166 | { 2445, 2, 1, 4, 1631, 0, 0, MipsOpInfoBase + 1074, 0, 0, 0x6ULL }, // REPL_QB_MM |
| 5167 | { 2444, 2, 1, 4, 1465, 0, 0, MipsOpInfoBase + 1074, 0, 0, 0x6ULL }, // REPL_QB |
| 5168 | { 2443, 2, 1, 4, 1630, 0, 0, MipsOpInfoBase + 1074, 0, 0, 0x6ULL }, // REPL_PH_MM |
| 5169 | { 2442, 2, 1, 4, 1464, 0, 0, MipsOpInfoBase + 1074, 0, 0, 0x6ULL }, // REPL_PH |
| 5170 | { 2441, 2, 1, 4, 1629, 0, 0, MipsOpInfoBase + 1072, 0, 0, 0x6ULL }, // REPLV_QB_MM |
| 5171 | { 2440, 2, 1, 4, 1463, 0, 0, MipsOpInfoBase + 1072, 0, 0, 0x6ULL }, // REPLV_QB |
| 5172 | { 2439, 2, 1, 4, 1628, 0, 0, MipsOpInfoBase + 1072, 0, 0, 0x6ULL }, // REPLV_PH_MM |
| 5173 | { 2438, 2, 1, 4, 1462, 0, 0, MipsOpInfoBase + 1072, 0, 0, 0x6ULL }, // REPLV_PH |
| 5174 | { 2437, 2, 1, 4, 1322, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_S_MM |
| 5175 | { 2436, 2, 1, 4, 574, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_S |
| 5176 | { 2435, 2, 1, 4, 1323, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_D64_MM |
| 5177 | { 2434, 2, 1, 4, 575, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_D64 |
| 5178 | { 2433, 2, 1, 4, 1323, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_D32_MM |
| 5179 | { 2432, 2, 1, 4, 575, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // RECIP_D32 |
| 5180 | { 2431, 2, 1, 4, 1119, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // RDPGPR_MMR6 |
| 5181 | { 2430, 3, 1, 4, 1011, 0, 0, MipsOpInfoBase + 1066, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // RDHWR_MMR6 |
| 5182 | { 2429, 3, 1, 4, 1002, 0, 0, MipsOpInfoBase + 1066, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // RDHWR_MM |
| 5183 | { 2428, 3, 1, 4, 535, 0, 0, MipsOpInfoBase + 1069, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // RDHWR64 |
| 5184 | { 2427, 3, 1, 4, 749, 0, 0, MipsOpInfoBase + 1066, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // RDHWR |
| 5185 | { 2426, 2, 1, 4, 1627, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // RDDSP_MM |
| 5186 | { 2425, 2, 1, 4, 1461, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // RDDSP |
| 5187 | { 2424, 2, 1, 4, 1626, 0, 0, MipsOpInfoBase + 1054, 0, 0, 0x6ULL }, // RADDU_W_QB_MM |
| 5188 | { 2423, 2, 1, 4, 1460, 0, 0, MipsOpInfoBase + 1054, 0, 0, 0x6ULL }, // RADDU_W_QB |
| 5189 | { 2422, 3, 1, 4, 849, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // PUU_PS64 |
| 5190 | { 2421, 3, 1, 4, 849, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // PUL_PS64 |
| 5191 | { 2420, 4, 1, 4, 1687, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x6ULL }, // PREPEND_MMR2 |
| 5192 | { 2419, 4, 1, 4, 1523, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x6ULL }, // PREPEND |
| 5193 | { 2418, 3, 0, 4, 409, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREF_R6 |
| 5194 | { 2417, 3, 0, 4, 1234, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREF_MMR6 |
| 5195 | { 2416, 3, 0, 4, 1212, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREF_MM |
| 5196 | { 2415, 3, 0, 4, 1212, 0, 0, MipsOpInfoBase + 1063, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREFX_MM |
| 5197 | { 2414, 3, 0, 4, 1179, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREFE_MM |
| 5198 | { 2413, 3, 0, 4, 743, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREFE |
| 5199 | { 2412, 3, 0, 4, 742, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PREF |
| 5200 | { 2411, 4, 1, 4, 1686, 0, 0, MipsOpInfoBase + 1059, 0, 0, 0x6ULL }, // PRECR_SRA_R_PH_W_MMR2 |
| 5201 | { 2410, 4, 1, 4, 1522, 0, 0, MipsOpInfoBase + 1059, 0, 0, 0x6ULL }, // PRECR_SRA_R_PH_W |
| 5202 | { 2409, 4, 1, 4, 1685, 0, 0, MipsOpInfoBase + 1059, 0, 0, 0x6ULL }, // PRECR_SRA_PH_W_MMR2 |
| 5203 | { 2408, 4, 1, 4, 1521, 0, 0, MipsOpInfoBase + 1059, 0, 0, 0x6ULL }, // PRECR_SRA_PH_W |
| 5204 | { 2407, 3, 1, 4, 1684, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECR_QB_PH_MMR2 |
| 5205 | { 2406, 3, 1, 4, 1520, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECR_QB_PH |
| 5206 | { 2405, 3, 1, 4, 1625, 0, 1, MipsOpInfoBase + 1056, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECRQ_RS_PH_W_MM |
| 5207 | { 2404, 3, 1, 4, 1459, 0, 1, MipsOpInfoBase + 1056, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECRQ_RS_PH_W |
| 5208 | { 2403, 3, 1, 4, 1624, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // PRECRQ_QB_PH_MM |
| 5209 | { 2402, 3, 1, 4, 1458, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // PRECRQ_QB_PH |
| 5210 | { 2401, 3, 1, 4, 1623, 0, 0, MipsOpInfoBase + 1056, 0, 0, 0x6ULL }, // PRECRQ_PH_W_MM |
| 5211 | { 2400, 3, 1, 4, 1457, 0, 0, MipsOpInfoBase + 1056, 0, 0, 0x6ULL }, // PRECRQ_PH_W |
| 5212 | { 2399, 3, 1, 4, 1622, 0, 1, MipsOpInfoBase + 548, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECRQU_S_QB_PH_MM |
| 5213 | { 2398, 3, 1, 4, 1456, 0, 1, MipsOpInfoBase + 548, 59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PRECRQU_S_QB_PH |
| 5214 | { 2397, 2, 1, 4, 1621, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEU_PH_QBR_MM |
| 5215 | { 2396, 2, 1, 4, 1620, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEU_PH_QBRA_MM |
| 5216 | { 2395, 2, 1, 4, 1454, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEU_PH_QBRA |
| 5217 | { 2394, 2, 1, 4, 1455, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEU_PH_QBR |
| 5218 | { 2393, 2, 1, 4, 1619, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEU_PH_QBL_MM |
| 5219 | { 2392, 2, 1, 4, 1618, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEU_PH_QBLA_MM |
| 5220 | { 2391, 2, 1, 4, 1452, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEU_PH_QBLA |
| 5221 | { 2390, 2, 1, 4, 1453, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEU_PH_QBL |
| 5222 | { 2389, 2, 1, 4, 1617, 0, 0, MipsOpInfoBase + 1054, 0, 0, 0x6ULL }, // PRECEQ_W_PHR_MM |
| 5223 | { 2388, 2, 1, 4, 1451, 0, 0, MipsOpInfoBase + 1054, 0, 0, 0x6ULL }, // PRECEQ_W_PHR |
| 5224 | { 2387, 2, 1, 4, 1616, 0, 0, MipsOpInfoBase + 1054, 0, 0, 0x6ULL }, // PRECEQ_W_PHL_MM |
| 5225 | { 2386, 2, 1, 4, 1450, 0, 0, MipsOpInfoBase + 1054, 0, 0, 0x6ULL }, // PRECEQ_W_PHL |
| 5226 | { 2385, 2, 1, 4, 1615, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEQU_PH_QBR_MM |
| 5227 | { 2384, 2, 1, 4, 1614, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEQU_PH_QBRA_MM |
| 5228 | { 2383, 2, 1, 4, 1448, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEQU_PH_QBRA |
| 5229 | { 2382, 2, 1, 4, 1449, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEQU_PH_QBR |
| 5230 | { 2381, 2, 1, 4, 1613, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEQU_PH_QBL_MM |
| 5231 | { 2380, 2, 1, 4, 1612, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEQU_PH_QBLA_MM |
| 5232 | { 2379, 2, 1, 4, 1446, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEQU_PH_QBLA |
| 5233 | { 2378, 2, 1, 4, 1447, 0, 0, MipsOpInfoBase + 538, 0, 0, 0x6ULL }, // PRECEQU_PH_QBL |
| 5234 | { 2377, 2, 1, 4, 1255, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // POP |
| 5235 | { 2376, 3, 1, 4, 849, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // PLU_PS64 |
| 5236 | { 2375, 3, 1, 4, 849, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // PLL_PS64 |
| 5237 | { 2374, 3, 1, 4, 1611, 1, 0, MipsOpInfoBase + 548, 15, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // PICK_QB_MM |
| 5238 | { 2373, 3, 1, 4, 1445, 1, 0, MipsOpInfoBase + 548, 15, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // PICK_QB |
| 5239 | { 2372, 3, 1, 4, 1610, 1, 0, MipsOpInfoBase + 548, 15, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // PICK_PH_MM |
| 5240 | { 2371, 3, 1, 4, 1444, 1, 0, MipsOpInfoBase + 548, 15, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // PICK_PH |
| 5241 | { 2370, 2, 1, 4, 778, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // PCNT_W |
| 5242 | { 2369, 2, 1, 4, 778, 0, 0, MipsOpInfoBase + 1050, 0, 0, 0x6ULL }, // PCNT_H |
| 5243 | { 2368, 2, 1, 4, 778, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // PCNT_D |
| 5244 | { 2367, 2, 1, 4, 778, 0, 0, MipsOpInfoBase + 972, 0, 0, 0x6ULL }, // PCNT_B |
| 5245 | { 2366, 3, 1, 4, 601, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // PCKOD_W |
| 5246 | { 2365, 3, 1, 4, 601, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // PCKOD_H |
| 5247 | { 2364, 3, 1, 4, 601, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // PCKOD_D |
| 5248 | { 2363, 3, 1, 4, 601, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // PCKOD_B |
| 5249 | { 2362, 3, 1, 4, 600, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // PCKEV_W |
| 5250 | { 2361, 3, 1, 4, 600, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // PCKEV_H |
| 5251 | { 2360, 3, 1, 4, 600, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // PCKEV_D |
| 5252 | { 2359, 3, 1, 4, 600, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // PCKEV_B |
| 5253 | { 2358, 0, 0, 4, 1134, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PAUSE_MMR6 |
| 5254 | { 2357, 0, 0, 4, 1117, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // PAUSE_MM |
| 5255 | { 2356, 0, 0, 4, 410, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // PAUSE |
| 5256 | { 2355, 3, 1, 4, 1609, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // PACKRL_PH_MM |
| 5257 | { 2354, 3, 1, 4, 1443, 0, 0, MipsOpInfoBase + 548, 0, 0, 0x6ULL }, // PACKRL_PH |
| 5258 | { 2353, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 591, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // OrRxRxRy16 |
| 5259 | { 2352, 3, 1, 4, 914, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ORi_MM |
| 5260 | { 2351, 3, 1, 4, 967, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ORi64 |
| 5261 | { 2350, 3, 1, 4, 506, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ORi |
| 5262 | { 2349, 3, 1, 4, 791, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // OR_V |
| 5263 | { 2348, 3, 1, 4, 954, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // OR_MMR6 |
| 5264 | { 2347, 3, 1, 4, 913, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // OR_MM |
| 5265 | { 2346, 3, 1, 4, 955, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ORI_MMR6 |
| 5266 | { 2345, 3, 1, 4, 591, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // ORI_B |
| 5267 | { 2344, 3, 1, 4, 505, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // OR64 |
| 5268 | { 2343, 3, 1, 2, 954, 0, 0, MipsOpInfoBase + 576, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // OR16_MMR6 |
| 5269 | { 2342, 3, 1, 2, 913, 0, 0, MipsOpInfoBase + 576, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // OR16_MM |
| 5270 | { 2341, 3, 1, 4, 676, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // OR |
| 5271 | { 2340, 2, 1, 2, 894, 0, 0, MipsOpInfoBase + 409, 0, 0, 0x0ULL }, // NotRxRy16 |
| 5272 | { 2339, 2, 1, 2, 894, 0, 0, MipsOpInfoBase + 409, 0, 0, 0x0ULL }, // NegRxRy16 |
| 5273 | { 2338, 2, 1, 2, 953, 0, 0, MipsOpInfoBase + 1052, 0, 0, 0x0ULL }, // NOT16_MMR6 |
| 5274 | { 2337, 2, 1, 2, 912, 0, 0, MipsOpInfoBase + 1052, 0, 0, 0x0ULL }, // NOT16_MM |
| 5275 | { 2336, 3, 1, 4, 791, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // NOR_V |
| 5276 | { 2335, 3, 1, 4, 952, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // NOR_MMR6 |
| 5277 | { 2334, 3, 1, 4, 911, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // NOR_MM |
| 5278 | { 2333, 3, 1, 4, 591, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // NORI_B |
| 5279 | { 2332, 3, 1, 4, 504, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // NOR64 |
| 5280 | { 2331, 3, 1, 4, 675, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // NOR |
| 5281 | { 2330, 4, 1, 4, 1285, 1, 0, MipsOpInfoBase + 952, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_S_MM |
| 5282 | { 2329, 4, 1, 4, 873, 1, 0, MipsOpInfoBase + 952, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_S |
| 5283 | { 2328, 4, 1, 4, 872, 1, 0, MipsOpInfoBase + 948, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_D64 |
| 5284 | { 2327, 4, 1, 4, 1286, 1, 0, MipsOpInfoBase + 944, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_D32_MM |
| 5285 | { 2326, 4, 1, 4, 872, 1, 0, MipsOpInfoBase + 944, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMSUB_D32 |
| 5286 | { 2325, 4, 1, 4, 1283, 1, 0, MipsOpInfoBase + 952, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_S_MM |
| 5287 | { 2324, 4, 1, 4, 871, 1, 0, MipsOpInfoBase + 952, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_S |
| 5288 | { 2323, 4, 1, 4, 870, 1, 0, MipsOpInfoBase + 948, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_D64 |
| 5289 | { 2322, 4, 1, 4, 1284, 1, 0, MipsOpInfoBase + 944, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_D32_MM |
| 5290 | { 2321, 4, 1, 4, 870, 1, 0, MipsOpInfoBase + 944, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // NMADD_D32 |
| 5291 | { 2320, 2, 1, 4, 590, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // NLZC_W |
| 5292 | { 2319, 2, 1, 4, 590, 0, 0, MipsOpInfoBase + 1050, 0, 0, 0x6ULL }, // NLZC_H |
| 5293 | { 2318, 2, 1, 4, 590, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // NLZC_D |
| 5294 | { 2317, 2, 1, 4, 590, 0, 0, MipsOpInfoBase + 972, 0, 0, 0x6ULL }, // NLZC_B |
| 5295 | { 2316, 2, 1, 4, 590, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // NLOC_W |
| 5296 | { 2315, 2, 1, 4, 590, 0, 0, MipsOpInfoBase + 1050, 0, 0, 0x6ULL }, // NLOC_H |
| 5297 | { 2314, 2, 1, 4, 590, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // NLOC_D |
| 5298 | { 2313, 2, 1, 4, 590, 0, 0, MipsOpInfoBase + 972, 0, 0, 0x6ULL }, // NLOC_B |
| 5299 | { 2312, 0, 0, 4, 422, 0, 1, MipsOpInfoBase + 1, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // NAL |
| 5300 | { 2311, 2, 1, 2, 894, 0, 0, MipsOpInfoBase + 1048, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MoveR3216 |
| 5301 | { 2310, 2, 1, 2, 894, 0, 0, MipsOpInfoBase + 1046, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Move32R16 |
| 5302 | { 2309, 1, 1, 2, 894, 1, 0, MipsOpInfoBase + 848, 41, 0, 0x0ULL }, // Mflo16 |
| 5303 | { 2308, 1, 1, 2, 894, 1, 0, MipsOpInfoBase + 848, 39, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Mfhi16 |
| 5304 | { 2307, 3, 1, 4, 1679, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MUL_S_PH_MMR2 |
| 5305 | { 2306, 3, 1, 4, 1515, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MUL_S_PH |
| 5306 | { 2305, 3, 1, 4, 542, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // MUL_R6 |
| 5307 | { 2304, 3, 1, 4, 657, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MUL_Q_W |
| 5308 | { 2303, 3, 1, 4, 657, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MUL_Q_H |
| 5309 | { 2302, 3, 1, 4, 1678, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MUL_PH_MMR2 |
| 5310 | { 2301, 3, 1, 4, 1514, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MUL_PH |
| 5311 | { 2300, 3, 1, 4, 1006, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUL_MMR6 |
| 5312 | { 2299, 3, 1, 4, 995, 0, 2, MipsOpInfoBase + 241, 7, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUL_MM |
| 5313 | { 2298, 3, 1, 4, 860, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MULV_W |
| 5314 | { 2297, 3, 1, 4, 860, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MULV_H |
| 5315 | { 2296, 3, 1, 4, 860, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MULV_D |
| 5316 | { 2295, 3, 1, 4, 860, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MULV_B |
| 5317 | { 2294, 3, 1, 4, 1005, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MULU_MMR6 |
| 5318 | { 2293, 3, 1, 4, 543, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULU |
| 5319 | { 2292, 2, 0, 4, 990, 0, 2, MipsOpInfoBase + 155, 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // MULTu_MM |
| 5320 | { 2291, 2, 0, 4, 756, 0, 2, MipsOpInfoBase + 155, 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // MULTu |
| 5321 | { 2290, 2, 0, 4, 989, 0, 2, MipsOpInfoBase + 155, 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // MULT_MM |
| 5322 | { 2289, 3, 1, 4, 1608, 0, 0, MipsOpInfoBase + 451, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // MULT_DSP_MM |
| 5323 | { 2288, 3, 1, 4, 1442, 0, 0, MipsOpInfoBase + 451, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // MULT_DSP |
| 5324 | { 2287, 3, 1, 4, 1607, 0, 0, MipsOpInfoBase + 451, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // MULTU_DSP_MM |
| 5325 | { 2286, 3, 1, 4, 1441, 0, 0, MipsOpInfoBase + 451, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // MULTU_DSP |
| 5326 | { 2285, 2, 0, 4, 755, 0, 2, MipsOpInfoBase + 155, 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // MULT |
| 5327 | { 2284, 4, 1, 4, 1683, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // MULSA_W_PH_MMR2 |
| 5328 | { 2283, 4, 1, 4, 1519, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // MULSA_W_PH |
| 5329 | { 2282, 4, 1, 4, 1606, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULSAQ_S_W_PH_MM |
| 5330 | { 2281, 4, 1, 4, 1440, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULSAQ_S_W_PH |
| 5331 | { 2280, 3, 1, 4, 865, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MULR_Q_W |
| 5332 | { 2279, 3, 1, 4, 865, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MULR_Q_H |
| 5333 | { 2278, 3, 1, 4, 1265, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MULR_PS64 |
| 5334 | { 2277, 3, 1, 4, 1682, 0, 1, MipsOpInfoBase + 241, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_S_W_MMR2 |
| 5335 | { 2276, 3, 1, 4, 1518, 0, 1, MipsOpInfoBase + 241, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_S_W |
| 5336 | { 2275, 3, 1, 4, 1681, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_S_PH_MMR2 |
| 5337 | { 2274, 3, 1, 4, 1517, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_S_PH |
| 5338 | { 2273, 3, 1, 4, 1680, 0, 1, MipsOpInfoBase + 241, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_RS_W_MMR2 |
| 5339 | { 2272, 3, 1, 4, 1516, 0, 1, MipsOpInfoBase + 241, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_RS_W |
| 5340 | { 2271, 3, 1, 4, 1605, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_RS_PH_MM |
| 5341 | { 2270, 3, 1, 4, 1439, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULQ_RS_PH |
| 5342 | { 2269, 3, 1, 4, 1604, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEU_S_PH_QBR_MM |
| 5343 | { 2268, 3, 1, 4, 1438, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEU_S_PH_QBR |
| 5344 | { 2267, 3, 1, 4, 1603, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEU_S_PH_QBL_MM |
| 5345 | { 2266, 3, 1, 4, 1437, 0, 1, MipsOpInfoBase + 548, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEU_S_PH_QBL |
| 5346 | { 2265, 3, 1, 4, 1602, 0, 1, MipsOpInfoBase + 666, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEQ_S_W_PHR_MM |
| 5347 | { 2264, 3, 1, 4, 1436, 0, 1, MipsOpInfoBase + 666, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEQ_S_W_PHR |
| 5348 | { 2263, 3, 1, 4, 1601, 0, 1, MipsOpInfoBase + 666, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEQ_S_W_PHL_MM |
| 5349 | { 2262, 3, 1, 4, 1435, 0, 1, MipsOpInfoBase + 666, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MULEQ_S_W_PHL |
| 5350 | { 2261, 3, 1, 4, 754, 0, 2, MipsOpInfoBase + 241, 7, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUL |
| 5351 | { 2260, 3, 1, 4, 1004, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUH_MMR6 |
| 5352 | { 2259, 3, 1, 4, 1003, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // MUHU_MMR6 |
| 5353 | { 2258, 3, 1, 4, 545, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // MUHU |
| 5354 | { 2257, 3, 1, 4, 544, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // MUH |
| 5355 | { 2256, 5, 1, 4, 1143, 0, 0, MipsOpInfoBase + 963, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTTR |
| 5356 | { 2255, 1, 0, 4, 1257, 0, 1, MipsOpInfoBase + 321, 57, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTP2 |
| 5357 | { 2254, 1, 0, 4, 1257, 0, 1, MipsOpInfoBase + 321, 56, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTP1 |
| 5358 | { 2253, 1, 0, 4, 1257, 0, 1, MipsOpInfoBase + 321, 55, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTP0 |
| 5359 | { 2252, 1, 0, 4, 1257, 0, 4, MipsOpInfoBase + 321, 51, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTM2 |
| 5360 | { 2251, 1, 0, 4, 1257, 0, 4, MipsOpInfoBase + 321, 47, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTM1 |
| 5361 | { 2250, 1, 0, 4, 1257, 0, 4, MipsOpInfoBase + 321, 43, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTM0 |
| 5362 | { 2249, 1, 0, 4, 1001, 0, 1, MipsOpInfoBase + 200, 41, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTLO_MM |
| 5363 | { 2248, 2, 1, 4, 1600, 0, 0, MipsOpInfoBase + 1044, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTLO_DSP_MM |
| 5364 | { 2247, 2, 1, 4, 1388, 0, 0, MipsOpInfoBase + 1044, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTLO_DSP |
| 5365 | { 2246, 1, 0, 4, 1019, 0, 1, MipsOpInfoBase + 321, 42, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTLO64 |
| 5366 | { 2245, 1, 0, 4, 761, 0, 1, MipsOpInfoBase + 200, 41, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTLO |
| 5367 | { 2244, 3, 1, 4, 1599, 0, 1, MipsOpInfoBase + 1041, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHLIP_MM |
| 5368 | { 2243, 3, 1, 4, 1386, 0, 1, MipsOpInfoBase + 1041, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHLIP |
| 5369 | { 2242, 1, 0, 4, 1001, 0, 1, MipsOpInfoBase + 200, 39, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTHI_MM |
| 5370 | { 2241, 2, 1, 4, 1598, 0, 0, MipsOpInfoBase + 1039, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHI_DSP_MM |
| 5371 | { 2240, 2, 1, 4, 1387, 0, 0, MipsOpInfoBase + 1039, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHI_DSP |
| 5372 | { 2239, 1, 0, 4, 1019, 0, 1, MipsOpInfoBase + 321, 40, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTHI64 |
| 5373 | { 2238, 1, 0, 4, 761, 0, 1, MipsOpInfoBase + 200, 39, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MTHI |
| 5374 | { 2237, 3, 1, 4, 1158, 0, 0, MipsOpInfoBase + 404, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MTHGC0_MM |
| 5375 | { 2236, 3, 1, 4, 704, 0, 0, MipsOpInfoBase + 404, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHGC0 |
| 5376 | { 2235, 2, 1, 4, 1128, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHC2_MMR6 |
| 5377 | { 2234, 3, 1, 4, 1304, 0, 0, MipsOpInfoBase + 1036, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHC1_D64_MM |
| 5378 | { 2233, 3, 1, 4, 502, 0, 0, MipsOpInfoBase + 1036, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHC1_D64 |
| 5379 | { 2232, 3, 1, 4, 1304, 0, 0, MipsOpInfoBase + 1033, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHC1_D32_MM |
| 5380 | { 2231, 3, 1, 4, 502, 0, 0, MipsOpInfoBase + 1033, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTHC1_D32 |
| 5381 | { 2230, 3, 1, 4, 1126, 0, 0, MipsOpInfoBase + 404, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTHC0_MMR6 |
| 5382 | { 2229, 3, 1, 4, 1157, 0, 0, MipsOpInfoBase + 404, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MTGC0_MM |
| 5383 | { 2228, 3, 1, 4, 703, 0, 0, MipsOpInfoBase + 404, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTGC0 |
| 5384 | { 2227, 2, 1, 4, 1128, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTC2_MMR6 |
| 5385 | { 2226, 3, 1, 4, 499, 0, 0, MipsOpInfoBase + 1030, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTC2 |
| 5386 | { 2225, 2, 1, 4, 1347, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // MTC1_MMR6 |
| 5387 | { 2224, 2, 1, 4, 1303, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // MTC1_MM |
| 5388 | { 2223, 2, 1, 4, 1303, 0, 0, MipsOpInfoBase + 421, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // MTC1_D64_MM |
| 5389 | { 2222, 2, 1, 4, 501, 0, 0, MipsOpInfoBase + 421, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // MTC1_D64 |
| 5390 | { 2221, 2, 1, 4, 501, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // MTC1 |
| 5391 | { 2220, 3, 1, 4, 1127, 0, 0, MipsOpInfoBase + 404, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MTC0_MMR6 |
| 5392 | { 2219, 3, 1, 4, 498, 0, 0, MipsOpInfoBase + 404, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MTC0 |
| 5393 | { 2218, 4, 1, 4, 1316, 1, 0, MipsOpInfoBase + 952, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MSUB_S_MM |
| 5394 | { 2217, 4, 1, 4, 869, 1, 0, MipsOpInfoBase + 952, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MSUB_S |
| 5395 | { 2216, 4, 1, 4, 864, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MSUB_Q_W |
| 5396 | { 2215, 4, 1, 4, 864, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // MSUB_Q_H |
| 5397 | { 2214, 2, 0, 4, 993, 2, 2, MipsOpInfoBase + 155, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MSUB_MM |
| 5398 | { 2213, 4, 1, 4, 1597, 0, 0, MipsOpInfoBase + 940, 0, 0, 0x6ULL }, // MSUB_DSP_MM |
| 5399 | { 2212, 4, 1, 4, 1434, 0, 0, MipsOpInfoBase + 940, 0, 0, 0x6ULL }, // MSUB_DSP |
| 5400 | { 2211, 4, 1, 4, 868, 1, 0, MipsOpInfoBase + 948, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MSUB_D64 |
| 5401 | { 2210, 4, 1, 4, 1317, 1, 0, MipsOpInfoBase + 944, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MSUB_D32_MM |
| 5402 | { 2209, 4, 1, 4, 868, 1, 0, MipsOpInfoBase + 944, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MSUB_D32 |
| 5403 | { 2208, 4, 1, 4, 858, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MSUBV_W |
| 5404 | { 2207, 4, 1, 4, 858, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // MSUBV_H |
| 5405 | { 2206, 4, 1, 4, 858, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // MSUBV_D |
| 5406 | { 2205, 4, 1, 4, 858, 0, 0, MipsOpInfoBase + 621, 0, 0, 0x6ULL }, // MSUBV_B |
| 5407 | { 2204, 2, 0, 4, 994, 2, 2, MipsOpInfoBase + 155, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MSUBU_MM |
| 5408 | { 2203, 4, 1, 4, 1596, 0, 0, MipsOpInfoBase + 940, 0, 0, 0x6ULL }, // MSUBU_DSP_MM |
| 5409 | { 2202, 4, 1, 4, 1433, 0, 0, MipsOpInfoBase + 940, 0, 0, 0x6ULL }, // MSUBU_DSP |
| 5410 | { 2201, 2, 0, 4, 975, 2, 2, MipsOpInfoBase + 155, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MSUBU |
| 5411 | { 2200, 4, 1, 4, 863, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MSUBR_Q_W |
| 5412 | { 2199, 4, 1, 4, 863, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // MSUBR_Q_H |
| 5413 | { 2198, 4, 1, 4, 1366, 1, 0, MipsOpInfoBase + 936, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MSUBF_S_MMR6 |
| 5414 | { 2197, 4, 1, 4, 665, 1, 0, MipsOpInfoBase + 936, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MSUBF_S |
| 5415 | { 2196, 4, 1, 4, 1365, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MSUBF_D_MMR6 |
| 5416 | { 2195, 4, 1, 4, 664, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MSUBF_D |
| 5417 | { 2194, 2, 0, 4, 974, 2, 2, MipsOpInfoBase + 155, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MSUB |
| 5418 | { 2193, 4, 1, 4, 1279, 0, 0, MipsOpInfoBase + 1026, 0, 0, 0x4ULL }, // MOVZ_I_S_MM |
| 5419 | { 2192, 4, 1, 4, 888, 0, 0, MipsOpInfoBase + 1026, 0, 0, 0x4ULL }, // MOVZ_I_S |
| 5420 | { 2191, 4, 1, 4, 1595, 0, 0, MipsOpInfoBase + 1018, 0, 0, 0x4ULL }, // MOVZ_I_MM |
| 5421 | { 2190, 4, 1, 4, 1021, 0, 0, MipsOpInfoBase + 1022, 0, 0, 0x4ULL }, // MOVZ_I_I64 |
| 5422 | { 2189, 4, 1, 4, 751, 0, 0, MipsOpInfoBase + 1018, 0, 0, 0x4ULL }, // MOVZ_I_I |
| 5423 | { 2188, 4, 1, 4, 887, 0, 0, MipsOpInfoBase + 1014, 0, 0, 0x4ULL }, // MOVZ_I_D64 |
| 5424 | { 2187, 4, 1, 4, 1278, 0, 0, MipsOpInfoBase + 1010, 0, 0, 0x4ULL }, // MOVZ_I_D32_MM |
| 5425 | { 2186, 4, 1, 4, 887, 0, 0, MipsOpInfoBase + 1010, 0, 0, 0x4ULL }, // MOVZ_I_D32 |
| 5426 | { 2185, 4, 1, 4, 1268, 0, 0, MipsOpInfoBase + 1006, 0, 0, 0x4ULL }, // MOVZ_I64_S |
| 5427 | { 2184, 4, 1, 4, 1021, 0, 0, MipsOpInfoBase + 1002, 0, 0, 0x4ULL }, // MOVZ_I64_I64 |
| 5428 | { 2183, 4, 1, 4, 1021, 0, 0, MipsOpInfoBase + 998, 0, 0, 0x4ULL }, // MOVZ_I64_I |
| 5429 | { 2182, 4, 1, 4, 1271, 0, 0, MipsOpInfoBase + 994, 0, 0, 0x4ULL }, // MOVZ_I64_D64 |
| 5430 | { 2181, 4, 1, 4, 1277, 0, 0, MipsOpInfoBase + 990, 0, 0, 0x4ULL }, // MOVT_S_MM |
| 5431 | { 2180, 4, 1, 4, 784, 0, 0, MipsOpInfoBase + 990, 0, 0, 0x4ULL }, // MOVT_S |
| 5432 | { 2179, 4, 1, 4, 1000, 0, 0, MipsOpInfoBase + 982, 0, 0, 0x4ULL }, // MOVT_I_MM |
| 5433 | { 2178, 4, 1, 4, 1266, 0, 0, MipsOpInfoBase + 986, 0, 0, 0x4ULL }, // MOVT_I64 |
| 5434 | { 2177, 4, 1, 4, 880, 0, 0, MipsOpInfoBase + 982, 0, 0, 0x4ULL }, // MOVT_I |
| 5435 | { 2176, 4, 1, 4, 783, 0, 0, MipsOpInfoBase + 978, 0, 0, 0x4ULL }, // MOVT_D64 |
| 5436 | { 2175, 4, 1, 4, 1276, 0, 0, MipsOpInfoBase + 974, 0, 0, 0x4ULL }, // MOVT_D32_MM |
| 5437 | { 2174, 4, 1, 4, 783, 0, 0, MipsOpInfoBase + 974, 0, 0, 0x4ULL }, // MOVT_D32 |
| 5438 | { 2173, 4, 1, 4, 1275, 0, 0, MipsOpInfoBase + 1026, 0, 0, 0x4ULL }, // MOVN_I_S_MM |
| 5439 | { 2172, 4, 1, 4, 886, 0, 0, MipsOpInfoBase + 1026, 0, 0, 0x4ULL }, // MOVN_I_S |
| 5440 | { 2171, 4, 1, 4, 1594, 0, 0, MipsOpInfoBase + 1018, 0, 0, 0x4ULL }, // MOVN_I_MM |
| 5441 | { 2170, 4, 1, 4, 1020, 0, 0, MipsOpInfoBase + 1022, 0, 0, 0x4ULL }, // MOVN_I_I64 |
| 5442 | { 2169, 4, 1, 4, 750, 0, 0, MipsOpInfoBase + 1018, 0, 0, 0x4ULL }, // MOVN_I_I |
| 5443 | { 2168, 4, 1, 4, 885, 0, 0, MipsOpInfoBase + 1014, 0, 0, 0x4ULL }, // MOVN_I_D64 |
| 5444 | { 2167, 4, 1, 4, 1274, 0, 0, MipsOpInfoBase + 1010, 0, 0, 0x4ULL }, // MOVN_I_D32_MM |
| 5445 | { 2166, 4, 1, 4, 885, 0, 0, MipsOpInfoBase + 1010, 0, 0, 0x4ULL }, // MOVN_I_D32 |
| 5446 | { 2165, 4, 1, 4, 1270, 0, 0, MipsOpInfoBase + 1006, 0, 0, 0x4ULL }, // MOVN_I64_S |
| 5447 | { 2164, 4, 1, 4, 1020, 0, 0, MipsOpInfoBase + 1002, 0, 0, 0x4ULL }, // MOVN_I64_I64 |
| 5448 | { 2163, 4, 1, 4, 1020, 0, 0, MipsOpInfoBase + 998, 0, 0, 0x4ULL }, // MOVN_I64_I |
| 5449 | { 2162, 4, 1, 4, 1269, 0, 0, MipsOpInfoBase + 994, 0, 0, 0x4ULL }, // MOVN_I64_D64 |
| 5450 | { 2161, 4, 1, 4, 1273, 0, 0, MipsOpInfoBase + 990, 0, 0, 0x4ULL }, // MOVF_S_MM |
| 5451 | { 2160, 4, 1, 4, 782, 0, 0, MipsOpInfoBase + 990, 0, 0, 0x4ULL }, // MOVF_S |
| 5452 | { 2159, 4, 1, 4, 999, 0, 0, MipsOpInfoBase + 982, 0, 0, 0x4ULL }, // MOVF_I_MM |
| 5453 | { 2158, 4, 1, 4, 1267, 0, 0, MipsOpInfoBase + 986, 0, 0, 0x4ULL }, // MOVF_I64 |
| 5454 | { 2157, 4, 1, 4, 879, 0, 0, MipsOpInfoBase + 982, 0, 0, 0x4ULL }, // MOVF_I |
| 5455 | { 2156, 4, 1, 4, 781, 0, 0, MipsOpInfoBase + 978, 0, 0, 0x4ULL }, // MOVF_D64 |
| 5456 | { 2155, 4, 1, 4, 1272, 0, 0, MipsOpInfoBase + 974, 0, 0, 0x4ULL }, // MOVF_D32_MM |
| 5457 | { 2154, 4, 1, 4, 781, 0, 0, MipsOpInfoBase + 974, 0, 0, 0x4ULL }, // MOVF_D32 |
| 5458 | { 2153, 2, 1, 4, 790, 0, 0, MipsOpInfoBase + 972, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MOVE_V |
| 5459 | { 2152, 4, 2, 2, 1593, 0, 0, MipsOpInfoBase + 968, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVEP_MMR6 |
| 5460 | { 2151, 4, 2, 2, 910, 0, 0, MipsOpInfoBase + 968, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVEP_MM |
| 5461 | { 2150, 2, 1, 2, 951, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVE16_MMR6 |
| 5462 | { 2149, 2, 1, 2, 909, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVE16_MM |
| 5463 | { 2148, 3, 1, 4, 557, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MOD_U_W |
| 5464 | { 2147, 3, 1, 4, 557, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MOD_U_H |
| 5465 | { 2146, 3, 1, 4, 557, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MOD_U_D |
| 5466 | { 2145, 3, 1, 4, 557, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MOD_U_B |
| 5467 | { 2144, 3, 1, 4, 557, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MOD_S_W |
| 5468 | { 2143, 3, 1, 4, 557, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MOD_S_H |
| 5469 | { 2142, 3, 1, 4, 557, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MOD_S_D |
| 5470 | { 2141, 3, 1, 4, 557, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MOD_S_B |
| 5471 | { 2140, 3, 1, 4, 1008, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // MOD_MMR6 |
| 5472 | { 2139, 3, 1, 4, 1007, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // MODU_MMR6 |
| 5473 | { 2138, 3, 1, 4, 552, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // MODU |
| 5474 | { 2137, 3, 1, 4, 1592, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // MODSUB_MM |
| 5475 | { 2136, 3, 1, 4, 1432, 0, 0, MipsOpInfoBase + 241, 0, 0, 0x6ULL }, // MODSUB |
| 5476 | { 2135, 3, 1, 4, 551, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // MOD |
| 5477 | { 2134, 3, 1, 4, 833, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MIN_U_W |
| 5478 | { 2133, 3, 1, 4, 833, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MIN_U_H |
| 5479 | { 2132, 3, 1, 4, 833, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MIN_U_D |
| 5480 | { 2131, 3, 1, 4, 833, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MIN_U_B |
| 5481 | { 2130, 3, 1, 4, 832, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MIN_S_W |
| 5482 | { 2129, 3, 1, 4, 1353, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MIN_S_MMR6 |
| 5483 | { 2128, 3, 1, 4, 832, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MIN_S_H |
| 5484 | { 2127, 3, 1, 4, 832, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MIN_S_D |
| 5485 | { 2126, 3, 1, 4, 832, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MIN_S_B |
| 5486 | { 2125, 3, 1, 4, 587, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // MIN_S |
| 5487 | { 2124, 3, 1, 4, 1352, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MIN_D_MMR6 |
| 5488 | { 2123, 3, 1, 4, 586, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // MIN_D |
| 5489 | { 2122, 3, 1, 4, 834, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MIN_A_W |
| 5490 | { 2121, 3, 1, 4, 834, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MIN_A_H |
| 5491 | { 2120, 3, 1, 4, 834, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MIN_A_D |
| 5492 | { 2119, 3, 1, 4, 834, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MIN_A_B |
| 5493 | { 2118, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // MINI_U_W |
| 5494 | { 2117, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // MINI_U_H |
| 5495 | { 2116, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // MINI_U_D |
| 5496 | { 2115, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // MINI_U_B |
| 5497 | { 2114, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // MINI_S_W |
| 5498 | { 2113, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // MINI_S_H |
| 5499 | { 2112, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // MINI_S_D |
| 5500 | { 2111, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // MINI_S_B |
| 5501 | { 2110, 3, 1, 4, 1357, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MINA_S_MMR6 |
| 5502 | { 2109, 3, 1, 4, 586, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MINA_S |
| 5503 | { 2108, 3, 1, 4, 1356, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MINA_D_MMR6 |
| 5504 | { 2107, 3, 1, 4, 587, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MINA_D |
| 5505 | { 2106, 5, 1, 4, 1142, 0, 0, MipsOpInfoBase + 963, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFTR |
| 5506 | { 2105, 1, 1, 4, 998, 1, 0, MipsOpInfoBase + 200, 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFLO_MM |
| 5507 | { 2104, 2, 1, 4, 1591, 0, 0, MipsOpInfoBase + 385, 0, 0, 0x6ULL }, // MFLO_DSP_MM |
| 5508 | { 2103, 2, 1, 4, 1431, 0, 0, MipsOpInfoBase + 385, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // MFLO_DSP |
| 5509 | { 2102, 1, 1, 4, 1017, 1, 0, MipsOpInfoBase + 321, 38, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFLO64 |
| 5510 | { 2101, 1, 1, 2, 998, 1, 0, MipsOpInfoBase + 200, 37, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // MFLO16_MM |
| 5511 | { 2100, 1, 1, 4, 748, 1, 0, MipsOpInfoBase + 200, 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFLO |
| 5512 | { 2099, 1, 1, 4, 998, 1, 0, MipsOpInfoBase + 200, 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFHI_MM |
| 5513 | { 2098, 2, 1, 4, 1590, 0, 0, MipsOpInfoBase + 385, 0, 0, 0x6ULL }, // MFHI_DSP_MM |
| 5514 | { 2097, 2, 1, 4, 1430, 0, 0, MipsOpInfoBase + 385, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // MFHI_DSP |
| 5515 | { 2096, 1, 1, 4, 1017, 1, 0, MipsOpInfoBase + 321, 38, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFHI64 |
| 5516 | { 2095, 1, 1, 2, 998, 1, 0, MipsOpInfoBase + 200, 37, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // MFHI16_MM |
| 5517 | { 2094, 1, 1, 4, 748, 1, 0, MipsOpInfoBase + 200, 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // MFHI |
| 5518 | { 2093, 3, 1, 4, 1156, 0, 0, MipsOpInfoBase + 387, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MFHGC0_MM |
| 5519 | { 2092, 3, 1, 4, 702, 0, 0, MipsOpInfoBase + 387, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHGC0 |
| 5520 | { 2091, 2, 1, 4, 1125, 0, 0, MipsOpInfoBase + 650, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFHC2_MMR6 |
| 5521 | { 2090, 2, 1, 4, 1302, 0, 0, MipsOpInfoBase + 956, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHC1_D64_MM |
| 5522 | { 2089, 2, 1, 4, 500, 0, 0, MipsOpInfoBase + 956, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHC1_D64 |
| 5523 | { 2088, 2, 1, 4, 1302, 0, 0, MipsOpInfoBase + 961, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHC1_D32_MM |
| 5524 | { 2087, 2, 1, 4, 500, 0, 0, MipsOpInfoBase + 961, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFHC1_D32 |
| 5525 | { 2086, 3, 1, 4, 1123, 0, 0, MipsOpInfoBase + 387, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFHC0_MMR6 |
| 5526 | { 2085, 3, 1, 4, 1155, 0, 0, MipsOpInfoBase + 387, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MFGC0_MM |
| 5527 | { 2084, 3, 1, 4, 701, 0, 0, MipsOpInfoBase + 387, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFGC0 |
| 5528 | { 2083, 2, 1, 4, 1125, 0, 0, MipsOpInfoBase + 650, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFC2_MMR6 |
| 5529 | { 2082, 3, 1, 4, 497, 0, 0, MipsOpInfoBase + 958, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFC2 |
| 5530 | { 2081, 2, 1, 4, 1346, 0, 0, MipsOpInfoBase + 390, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // MFC1_MMR6 |
| 5531 | { 2080, 2, 1, 4, 1301, 0, 0, MipsOpInfoBase + 390, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // MFC1_MM |
| 5532 | { 2079, 2, 1, 4, 495, 0, 0, MipsOpInfoBase + 956, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFC1_D64 |
| 5533 | { 2078, 2, 1, 4, 495, 0, 0, MipsOpInfoBase + 390, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // MFC1 |
| 5534 | { 2077, 3, 1, 4, 1124, 0, 0, MipsOpInfoBase + 387, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MFC0_MMR6 |
| 5535 | { 2076, 3, 1, 4, 496, 0, 0, MipsOpInfoBase + 387, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MFC0 |
| 5536 | { 2075, 3, 1, 4, 833, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MAX_U_W |
| 5537 | { 2074, 3, 1, 4, 833, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MAX_U_H |
| 5538 | { 2073, 3, 1, 4, 833, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MAX_U_D |
| 5539 | { 2072, 3, 1, 4, 833, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MAX_U_B |
| 5540 | { 2071, 3, 1, 4, 832, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MAX_S_W |
| 5541 | { 2070, 3, 1, 4, 1351, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAX_S_MMR6 |
| 5542 | { 2069, 3, 1, 4, 832, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MAX_S_H |
| 5543 | { 2068, 3, 1, 4, 832, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MAX_S_D |
| 5544 | { 2067, 3, 1, 4, 832, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MAX_S_B |
| 5545 | { 2066, 3, 1, 4, 585, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // MAX_S |
| 5546 | { 2065, 3, 1, 4, 1350, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAX_D_MMR6 |
| 5547 | { 2064, 3, 1, 4, 584, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // MAX_D |
| 5548 | { 2063, 3, 1, 4, 834, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // MAX_A_W |
| 5549 | { 2062, 3, 1, 4, 834, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // MAX_A_H |
| 5550 | { 2061, 3, 1, 4, 834, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // MAX_A_D |
| 5551 | { 2060, 3, 1, 4, 834, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // MAX_A_B |
| 5552 | { 2059, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // MAXI_U_W |
| 5553 | { 2058, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // MAXI_U_H |
| 5554 | { 2057, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // MAXI_U_D |
| 5555 | { 2056, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // MAXI_U_B |
| 5556 | { 2055, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // MAXI_S_W |
| 5557 | { 2054, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // MAXI_S_H |
| 5558 | { 2053, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // MAXI_S_D |
| 5559 | { 2052, 3, 1, 4, 588, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // MAXI_S_B |
| 5560 | { 2051, 3, 1, 4, 1355, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAXA_S_MMR6 |
| 5561 | { 2050, 3, 1, 4, 585, 0, 0, MipsOpInfoBase + 774, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAXA_S |
| 5562 | { 2049, 3, 1, 4, 1354, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAXA_D_MMR6 |
| 5563 | { 2048, 3, 1, 4, 584, 0, 0, MipsOpInfoBase + 551, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAXA_D |
| 5564 | { 2047, 4, 1, 4, 1589, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_S_W_PHR_MM |
| 5565 | { 2046, 4, 1, 4, 1429, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_S_W_PHR |
| 5566 | { 2045, 4, 1, 4, 1588, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_S_W_PHL_MM |
| 5567 | { 2044, 4, 1, 4, 1428, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_S_W_PHL |
| 5568 | { 2043, 4, 1, 4, 1587, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_SA_W_PHR_MM |
| 5569 | { 2042, 4, 1, 4, 1427, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_SA_W_PHR |
| 5570 | { 2041, 4, 1, 4, 1586, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_SA_W_PHL_MM |
| 5571 | { 2040, 4, 1, 4, 1426, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MAQ_SA_W_PHL |
| 5572 | { 2039, 4, 1, 4, 1287, 1, 0, MipsOpInfoBase + 952, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MADD_S_MM |
| 5573 | { 2038, 4, 1, 4, 867, 1, 0, MipsOpInfoBase + 952, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MADD_S |
| 5574 | { 2037, 4, 1, 4, 862, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MADD_Q_W |
| 5575 | { 2036, 4, 1, 4, 862, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // MADD_Q_H |
| 5576 | { 2035, 2, 0, 4, 991, 2, 2, MipsOpInfoBase + 155, 33, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MADD_MM |
| 5577 | { 2034, 4, 1, 4, 1585, 0, 0, MipsOpInfoBase + 940, 0, 0, 0x6ULL }, // MADD_DSP_MM |
| 5578 | { 2033, 4, 1, 4, 1425, 0, 0, MipsOpInfoBase + 940, 0, 0, 0x6ULL }, // MADD_DSP |
| 5579 | { 2032, 4, 1, 4, 866, 1, 0, MipsOpInfoBase + 948, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MADD_D64 |
| 5580 | { 2031, 4, 1, 4, 1288, 1, 0, MipsOpInfoBase + 944, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // MADD_D32_MM |
| 5581 | { 2030, 4, 1, 4, 866, 1, 0, MipsOpInfoBase + 944, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // MADD_D32 |
| 5582 | { 2029, 4, 1, 4, 859, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MADDV_W |
| 5583 | { 2028, 4, 1, 4, 859, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // MADDV_H |
| 5584 | { 2027, 4, 1, 4, 859, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // MADDV_D |
| 5585 | { 2026, 4, 1, 4, 859, 0, 0, MipsOpInfoBase + 621, 0, 0, 0x6ULL }, // MADDV_B |
| 5586 | { 2025, 2, 0, 4, 992, 2, 2, MipsOpInfoBase + 155, 33, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MADDU_MM |
| 5587 | { 2024, 4, 1, 4, 1584, 0, 0, MipsOpInfoBase + 940, 0, 0, 0x6ULL }, // MADDU_DSP_MM |
| 5588 | { 2023, 4, 1, 4, 1424, 0, 0, MipsOpInfoBase + 940, 0, 0, 0x6ULL }, // MADDU_DSP |
| 5589 | { 2022, 2, 0, 4, 973, 2, 2, MipsOpInfoBase + 155, 33, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MADDU |
| 5590 | { 2021, 4, 1, 4, 861, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // MADDR_Q_W |
| 5591 | { 2020, 4, 1, 4, 861, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // MADDR_Q_H |
| 5592 | { 2019, 4, 1, 4, 1364, 1, 0, MipsOpInfoBase + 936, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MADDF_S_MMR6 |
| 5593 | { 2018, 4, 1, 4, 667, 1, 0, MipsOpInfoBase + 936, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MADDF_S |
| 5594 | { 2017, 4, 1, 4, 1363, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MADDF_D_MMR6 |
| 5595 | { 2016, 4, 1, 4, 666, 1, 0, MipsOpInfoBase + 932, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // MADDF_D |
| 5596 | { 2015, 2, 0, 4, 972, 2, 2, MipsOpInfoBase + 155, 33, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // MADD |
| 5597 | { 2014, 3, 1, 4, 1186, 0, 0, MipsOpInfoBase + 588, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LwRxSpImmX16 |
| 5598 | { 2013, 3, 1, 4, 1186, 0, 0, MipsOpInfoBase + 929, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LwRxRyOffMemX16 |
| 5599 | { 2012, 2, 1, 4, 1186, 0, 0, MipsOpInfoBase + 583, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LwRxPcTcpX16 |
| 5600 | { 2011, 2, 1, 2, 1186, 0, 0, MipsOpInfoBase + 583, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LwRxPcTcp16 |
| 5601 | { 2010, 2, 1, 4, 894, 0, 0, MipsOpInfoBase + 583, 0, 0, 0x0ULL }, // LiRxImmX16 |
| 5602 | { 2009, 2, 1, 4, 894, 0, 0, MipsOpInfoBase + 583, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LiRxImmAlignX16 |
| 5603 | { 2008, 2, 1, 2, 894, 0, 0, MipsOpInfoBase + 583, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LiRxImm16 |
| 5604 | { 2007, 3, 1, 4, 1185, 0, 0, MipsOpInfoBase + 929, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LhuRxRyOffMemX16 |
| 5605 | { 2006, 3, 1, 4, 1184, 0, 0, MipsOpInfoBase + 929, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LhRxRyOffMemX16 |
| 5606 | { 2005, 3, 1, 4, 1183, 0, 0, MipsOpInfoBase + 929, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LbuRxRyOffMemX16 |
| 5607 | { 2004, 3, 1, 4, 1182, 0, 0, MipsOpInfoBase + 929, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LbRxRyOffMemX16 |
| 5608 | { 2003, 3, 1, 4, 389, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWu |
| 5609 | { 2002, 3, 1, 4, 1225, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL }, // LW_MMR6 |
| 5610 | { 2001, 3, 1, 4, 1196, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LW_MM |
| 5611 | { 2000, 3, 1, 4, 1583, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LWX_MM |
| 5612 | { 1999, 3, 1, 4, 1202, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // LWXS_MM |
| 5613 | { 1998, 3, 1, 4, 1333, 0, 0, MipsOpInfoBase + 926, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWXC1_MM |
| 5614 | { 1997, 3, 1, 4, 890, 0, 0, MipsOpInfoBase + 926, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWXC1 |
| 5615 | { 1996, 3, 1, 4, 1423, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LWX |
| 5616 | { 1995, 3, 1, 4, 1201, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWU_MM |
| 5617 | { 1994, 2, 1, 4, 399, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWUPC |
| 5618 | { 1993, 3, 1, 2, 1196, 0, 0, MipsOpInfoBase + 923, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWSP_MM |
| 5619 | { 1992, 4, 1, 4, 1200, 0, 0, MipsOpInfoBase + 912, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWR_MM |
| 5620 | { 1991, 4, 1, 4, 1170, 0, 0, MipsOpInfoBase + 912, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWRE_MM |
| 5621 | { 1990, 4, 1, 4, 729, 0, 0, MipsOpInfoBase + 912, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWRE |
| 5622 | { 1989, 4, 1, 4, 403, 0, 0, MipsOpInfoBase + 875, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWR64 |
| 5623 | { 1988, 4, 1, 4, 727, 0, 0, MipsOpInfoBase + 912, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWR |
| 5624 | { 1987, 4, 2, 4, 1199, 0, 0, MipsOpInfoBase + 919, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWP_MM |
| 5625 | { 1986, 2, 1, 4, 1224, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWPC_MMR6 |
| 5626 | { 1985, 2, 1, 4, 398, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWPC |
| 5627 | { 1984, 3, 1, 4, 1198, 0, 0, MipsOpInfoBase + 364, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWM32_MM |
| 5628 | { 1983, 3, 1, 2, 1222, 0, 0, MipsOpInfoBase + 916, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWM16_MMR6 |
| 5629 | { 1982, 3, 1, 2, 1198, 0, 0, MipsOpInfoBase + 916, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWM16_MM |
| 5630 | { 1981, 4, 1, 4, 1197, 0, 0, MipsOpInfoBase + 912, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWL_MM |
| 5631 | { 1980, 4, 1, 4, 1169, 0, 0, MipsOpInfoBase + 912, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWLE_MM |
| 5632 | { 1979, 4, 1, 4, 728, 0, 0, MipsOpInfoBase + 912, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWLE |
| 5633 | { 1978, 4, 1, 4, 402, 0, 0, MipsOpInfoBase + 875, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWL64 |
| 5634 | { 1977, 4, 1, 4, 726, 0, 0, MipsOpInfoBase + 912, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LWL |
| 5635 | { 1976, 3, 1, 2, 1196, 0, 0, MipsOpInfoBase + 909, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWGP_MM |
| 5636 | { 1975, 3, 1, 4, 1168, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWE_MM |
| 5637 | { 1974, 3, 1, 4, 724, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWE |
| 5638 | { 1973, 3, 1, 4, 1538, 0, 0, MipsOpInfoBase + 906, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWDSP_MM |
| 5639 | { 1972, 3, 1, 4, 1375, 0, 0, MipsOpInfoBase + 906, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LWDSP |
| 5640 | { 1971, 3, 1, 4, 718, 0, 0, MipsOpInfoBase + 864, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWC3 |
| 5641 | { 1970, 3, 1, 4, 395, 0, 0, MipsOpInfoBase + 858, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LWC2_R6 |
| 5642 | { 1969, 3, 1, 4, 1223, 0, 0, MipsOpInfoBase + 861, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LWC2_MMR6 |
| 5643 | { 1968, 3, 1, 4, 717, 0, 0, MipsOpInfoBase + 858, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWC2 |
| 5644 | { 1967, 3, 1, 4, 1332, 0, 0, MipsOpInfoBase + 903, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWC1_MM |
| 5645 | { 1966, 3, 1, 4, 391, 0, 0, MipsOpInfoBase + 903, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LWC1 |
| 5646 | { 1965, 3, 1, 4, 388, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LW64 |
| 5647 | { 1964, 3, 1, 2, 1196, 0, 0, MipsOpInfoBase + 849, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL }, // LW16_MM |
| 5648 | { 1963, 3, 1, 4, 715, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LW |
| 5649 | { 1962, 2, 1, 4, 908, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // LUi_MM |
| 5650 | { 1961, 2, 1, 4, 494, 0, 0, MipsOpInfoBase + 369, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // LUi64 |
| 5651 | { 1960, 2, 1, 4, 674, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // LUi |
| 5652 | { 1959, 3, 1, 4, 1331, 0, 0, MipsOpInfoBase + 882, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // LUXC1_MM |
| 5653 | { 1958, 3, 1, 4, 891, 0, 0, MipsOpInfoBase + 882, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // LUXC164 |
| 5654 | { 1957, 3, 1, 4, 891, 0, 0, MipsOpInfoBase + 879, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // LUXC1 |
| 5655 | { 1956, 2, 1, 4, 950, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // LUI_MMR6 |
| 5656 | { 1955, 4, 1, 4, 493, 0, 0, MipsOpInfoBase + 572, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LSA_R6 |
| 5657 | { 1954, 4, 1, 4, 949, 0, 0, MipsOpInfoBase + 572, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LSA_MMR6 |
| 5658 | { 1953, 4, 1, 4, 769, 0, 0, MipsOpInfoBase + 572, 0, 0, 0x6ULL }, // LSA |
| 5659 | { 1952, 3, 1, 4, 1160, 0, 0, MipsOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LL_R6 |
| 5660 | { 1951, 3, 1, 4, 1221, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LL_MMR6 |
| 5661 | { 1950, 3, 1, 4, 1195, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LL_MM |
| 5662 | { 1949, 3, 1, 4, 1171, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LLE_MM |
| 5663 | { 1948, 3, 1, 4, 725, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LLE |
| 5664 | { 1947, 3, 1, 4, 396, 0, 0, MipsOpInfoBase + 900, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LLD_R6 |
| 5665 | { 1946, 3, 1, 4, 1236, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LLD |
| 5666 | { 1945, 3, 1, 4, 397, 0, 0, MipsOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LL64_R6 |
| 5667 | { 1944, 3, 1, 4, 1236, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LL64 |
| 5668 | { 1943, 3, 1, 4, 716, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LL |
| 5669 | { 1942, 2, 1, 2, 948, 0, 0, MipsOpInfoBase + 540, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // LI16_MMR6 |
| 5670 | { 1941, 2, 1, 2, 907, 0, 0, MipsOpInfoBase + 540, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // LI16_MM |
| 5671 | { 1940, 3, 1, 4, 1193, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LHu_MM |
| 5672 | { 1939, 3, 1, 4, 1167, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LHuE_MM |
| 5673 | { 1938, 3, 1, 4, 723, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LHuE |
| 5674 | { 1937, 3, 1, 4, 387, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LHu64 |
| 5675 | { 1936, 3, 1, 4, 714, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LHu |
| 5676 | { 1935, 3, 1, 4, 1194, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LH_MM |
| 5677 | { 1934, 3, 1, 4, 1582, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LHX_MM |
| 5678 | { 1933, 3, 1, 4, 1422, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LHX |
| 5679 | { 1932, 3, 1, 2, 1193, 0, 0, MipsOpInfoBase + 849, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LHU16_MM |
| 5680 | { 1931, 3, 1, 4, 1166, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LHE_MM |
| 5681 | { 1930, 3, 1, 4, 722, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LHE |
| 5682 | { 1929, 3, 1, 4, 386, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LH64 |
| 5683 | { 1928, 3, 1, 4, 713, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LH |
| 5684 | { 1927, 3, 1, 4, 897, 0, 0, MipsOpInfoBase + 322, 0, 0, 0x2ULL }, // LEA_ADDiu_MM |
| 5685 | { 1926, 3, 1, 4, 971, 0, 0, MipsOpInfoBase + 371, 0, 0, 0x2ULL }, // LEA_ADDiu64 |
| 5686 | { 1925, 3, 1, 4, 892, 0, 0, MipsOpInfoBase + 322, 0, 0, 0x2ULL }, // LEA_ADDiu |
| 5687 | { 1924, 3, 1, 4, 608, 0, 0, MipsOpInfoBase + 894, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LD_W |
| 5688 | { 1923, 3, 1, 4, 608, 0, 0, MipsOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LD_H |
| 5689 | { 1922, 3, 1, 4, 608, 0, 0, MipsOpInfoBase + 888, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LD_D |
| 5690 | { 1921, 3, 1, 4, 608, 0, 0, MipsOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LD_B |
| 5691 | { 1920, 3, 1, 4, 889, 0, 0, MipsOpInfoBase + 882, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDXC164 |
| 5692 | { 1919, 3, 1, 4, 889, 0, 0, MipsOpInfoBase + 879, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDXC1 |
| 5693 | { 1918, 4, 1, 4, 1238, 0, 0, MipsOpInfoBase + 875, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LDR |
| 5694 | { 1917, 2, 1, 4, 400, 0, 0, MipsOpInfoBase + 369, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LDPC |
| 5695 | { 1916, 4, 1, 4, 1237, 0, 0, MipsOpInfoBase + 875, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LDL |
| 5696 | { 1915, 2, 1, 4, 609, 0, 0, MipsOpInfoBase + 873, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // LDI_W |
| 5697 | { 1914, 2, 1, 4, 609, 0, 0, MipsOpInfoBase + 871, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // LDI_H |
| 5698 | { 1913, 2, 1, 4, 609, 0, 0, MipsOpInfoBase + 869, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // LDI_D |
| 5699 | { 1912, 2, 1, 4, 609, 0, 0, MipsOpInfoBase + 867, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // LDI_B |
| 5700 | { 1911, 3, 1, 4, 394, 0, 0, MipsOpInfoBase + 864, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC3 |
| 5701 | { 1910, 3, 1, 4, 393, 0, 0, MipsOpInfoBase + 858, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LDC2_R6 |
| 5702 | { 1909, 3, 1, 4, 1220, 0, 0, MipsOpInfoBase + 861, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LDC2_MMR6 |
| 5703 | { 1908, 3, 1, 4, 719, 0, 0, MipsOpInfoBase + 858, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC2 |
| 5704 | { 1907, 3, 1, 4, 1330, 0, 0, MipsOpInfoBase + 855, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC1_MM_D64 |
| 5705 | { 1906, 3, 1, 4, 1330, 0, 0, MipsOpInfoBase + 507, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC1_MM_D32 |
| 5706 | { 1905, 3, 1, 4, 1373, 0, 0, MipsOpInfoBase + 855, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LDC1_D64_MMR6 |
| 5707 | { 1904, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 855, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC164 |
| 5708 | { 1903, 3, 1, 4, 390, 0, 0, MipsOpInfoBase + 507, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // LDC1 |
| 5709 | { 1902, 3, 1, 4, 385, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LD |
| 5710 | { 1901, 3, 1, 4, 1191, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LBu_MM |
| 5711 | { 1900, 3, 1, 4, 1165, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LBuE_MM |
| 5712 | { 1899, 3, 1, 4, 721, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LBuE |
| 5713 | { 1898, 3, 1, 4, 384, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LBu64 |
| 5714 | { 1897, 3, 1, 4, 712, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LBu |
| 5715 | { 1896, 3, 1, 4, 1219, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LB_MMR6 |
| 5716 | { 1895, 3, 1, 4, 1192, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LB_MM |
| 5717 | { 1894, 3, 1, 4, 1218, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LBU_MMR6 |
| 5718 | { 1893, 3, 1, 4, 1581, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LBUX_MM |
| 5719 | { 1892, 3, 1, 4, 1421, 0, 0, MipsOpInfoBase + 852, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // LBUX |
| 5720 | { 1891, 3, 1, 2, 1191, 0, 0, MipsOpInfoBase + 849, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LBU16_MM |
| 5721 | { 1890, 3, 1, 4, 1164, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LBE_MM |
| 5722 | { 1889, 3, 1, 4, 720, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // LBE |
| 5723 | { 1888, 3, 1, 4, 383, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LB64 |
| 5724 | { 1887, 3, 1, 4, 711, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // LB |
| 5725 | { 1886, 1, 0, 2, 1039, 0, 1, MipsOpInfoBase + 848, 3, 0|(1ULL<<MCID::Call), 0x0ULL }, // JumpLinkReg16 |
| 5726 | { 1885, 1, 0, 2, 1036, 0, 0, MipsOpInfoBase + 848, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // JrcRx16 |
| 5727 | { 1884, 0, 0, 2, 1036, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JrcRa16 |
| 5728 | { 1883, 0, 0, 2, 1036, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JrRa16 |
| 5729 | { 1882, 1, 0, 6, 1038, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JalB16 |
| 5730 | { 1881, 1, 0, 6, 1038, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::Call), 0x0ULL }, // Jal16 |
| 5731 | { 1880, 1, 0, 4, 1052, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // J_MM |
| 5732 | { 1879, 1, 0, 4, 1051, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JR_MM |
| 5733 | { 1878, 1, 0, 4, 1032, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JR_HB_R6 |
| 5734 | { 1877, 1, 0, 4, 421, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JR_HB64_R6 |
| 5735 | { 1876, 1, 0, 4, 1107, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JR_HB64 |
| 5736 | { 1875, 1, 0, 4, 687, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JR_HB |
| 5737 | { 1874, 1, 0, 2, 1090, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JRCADDIUSP_MMR6 |
| 5738 | { 1873, 1, 0, 2, 1092, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JRC16_MMR6 |
| 5739 | { 1872, 1, 0, 2, 1091, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JRC16_MM |
| 5740 | { 1871, 1, 0, 2, 1090, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JRADDIUSP |
| 5741 | { 1870, 1, 0, 4, 1106, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JR64 |
| 5742 | { 1869, 1, 0, 2, 1051, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JR16_MM |
| 5743 | { 1868, 1, 0, 4, 1024, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JR |
| 5744 | { 1867, 2, 0, 4, 1089, 0, 1, MipsOpInfoBase + 374, 2, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // JIC_MMR6 |
| 5745 | { 1866, 2, 0, 4, 419, 0, 1, MipsOpInfoBase + 369, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JIC64 |
| 5746 | { 1865, 2, 0, 4, 1031, 0, 1, MipsOpInfoBase + 374, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JIC |
| 5747 | { 1864, 2, 0, 4, 1101, 0, 1, MipsOpInfoBase + 374, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // JIALC_MMR6 |
| 5748 | { 1863, 2, 0, 4, 418, 0, 1, MipsOpInfoBase + 369, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JIALC64 |
| 5749 | { 1862, 2, 0, 4, 1028, 0, 1, MipsOpInfoBase + 374, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // JIALC |
| 5750 | { 1861, 1, 0, 4, 1059, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // JAL_MM |
| 5751 | { 1860, 1, 0, 4, 1059, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // JALX_MM |
| 5752 | { 1859, 1, 0, 4, 699, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // JALX |
| 5753 | { 1858, 1, 0, 4, 1058, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // JALS_MM |
| 5754 | { 1857, 2, 1, 4, 1056, 0, 1, MipsOpInfoBase + 155, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JALR_MM |
| 5755 | { 1856, 2, 1, 4, 436, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JALR_HB64 |
| 5756 | { 1855, 2, 1, 4, 698, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // JALR_HB |
| 5757 | { 1854, 2, 1, 4, 1057, 0, 1, MipsOpInfoBase + 155, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // JALRS_MM |
| 5758 | { 1853, 1, 0, 2, 1057, 0, 1, MipsOpInfoBase + 200, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JALRS16_MM |
| 5759 | { 1852, 2, 1, 4, 1100, 0, 1, MipsOpInfoBase + 155, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // JALRC_MMR6 |
| 5760 | { 1851, 2, 1, 4, 1099, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // JALRC_HB_MMR6 |
| 5761 | { 1850, 1, 0, 2, 1098, 0, 1, MipsOpInfoBase + 200, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // JALRC16_MMR6 |
| 5762 | { 1849, 2, 1, 4, 414, 0, 1, MipsOpInfoBase + 392, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JALR64 |
| 5763 | { 1848, 1, 0, 2, 1056, 0, 1, MipsOpInfoBase + 200, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // JALR16_MM |
| 5764 | { 1847, 2, 1, 4, 697, 0, 1, MipsOpInfoBase + 155, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // JALR |
| 5765 | { 1846, 1, 0, 4, 413, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // JAL |
| 5766 | { 1845, 1, 0, 4, 1023, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // J |
| 5767 | { 1844, 5, 1, 4, 947, 0, 0, MipsOpInfoBase + 804, 0, 0, 0x1ULL }, // INS_MMR6 |
| 5768 | { 1843, 5, 1, 4, 906, 0, 0, MipsOpInfoBase + 804, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // INS_MM |
| 5769 | { 1842, 3, 1, 4, 1580, 2, 0, MipsOpInfoBase + 825, 31, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // INSV_MM |
| 5770 | { 1841, 5, 1, 4, 653, 0, 0, MipsOpInfoBase + 843, 0, 0, 0x6ULL }, // INSVE_W |
| 5771 | { 1840, 5, 1, 4, 653, 0, 0, MipsOpInfoBase + 838, 0, 0, 0x6ULL }, // INSVE_H |
| 5772 | { 1839, 5, 1, 4, 653, 0, 0, MipsOpInfoBase + 833, 0, 0, 0x6ULL }, // INSVE_D |
| 5773 | { 1838, 5, 1, 4, 653, 0, 0, MipsOpInfoBase + 828, 0, 0, 0x6ULL }, // INSVE_B |
| 5774 | { 1837, 3, 1, 4, 1385, 2, 0, MipsOpInfoBase + 825, 31, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // INSV |
| 5775 | { 1836, 4, 1, 4, 773, 0, 0, MipsOpInfoBase + 821, 0, 0, 0x6ULL }, // INSERT_W |
| 5776 | { 1835, 4, 1, 4, 773, 0, 0, MipsOpInfoBase + 817, 0, 0, 0x6ULL }, // INSERT_H |
| 5777 | { 1834, 4, 1, 4, 773, 0, 0, MipsOpInfoBase + 813, 0, 0, 0x6ULL }, // INSERT_D |
| 5778 | { 1833, 4, 1, 4, 773, 0, 0, MipsOpInfoBase + 809, 0, 0, 0x6ULL }, // INSERT_B |
| 5779 | { 1832, 5, 1, 4, 763, 0, 0, MipsOpInfoBase + 804, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // INS |
| 5780 | { 1831, 3, 1, 4, 599, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // ILVR_W |
| 5781 | { 1830, 3, 1, 4, 599, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // ILVR_H |
| 5782 | { 1829, 3, 1, 4, 599, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // ILVR_D |
| 5783 | { 1828, 3, 1, 4, 599, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // ILVR_B |
| 5784 | { 1827, 3, 1, 4, 598, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // ILVOD_W |
| 5785 | { 1826, 3, 1, 4, 598, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // ILVOD_H |
| 5786 | { 1825, 3, 1, 4, 598, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // ILVOD_D |
| 5787 | { 1824, 3, 1, 4, 598, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // ILVOD_B |
| 5788 | { 1823, 3, 1, 4, 597, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // ILVL_W |
| 5789 | { 1822, 3, 1, 4, 597, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // ILVL_H |
| 5790 | { 1821, 3, 1, 4, 597, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // ILVL_D |
| 5791 | { 1820, 3, 1, 4, 597, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // ILVL_B |
| 5792 | { 1819, 3, 1, 4, 596, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // ILVEV_W |
| 5793 | { 1818, 3, 1, 4, 596, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // ILVEV_H |
| 5794 | { 1817, 3, 1, 4, 596, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // ILVEV_D |
| 5795 | { 1816, 3, 1, 4, 596, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // ILVEV_B |
| 5796 | { 1815, 1, 0, 4, 1148, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // HYPCALL_MM |
| 5797 | { 1814, 1, 0, 4, 700, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // HYPCALL |
| 5798 | { 1813, 3, 1, 4, 831, 0, 0, MipsOpInfoBase + 739, 0, 0, 0x6ULL }, // HSUB_U_W |
| 5799 | { 1812, 3, 1, 4, 831, 0, 0, MipsOpInfoBase + 736, 0, 0, 0x6ULL }, // HSUB_U_H |
| 5800 | { 1811, 3, 1, 4, 831, 0, 0, MipsOpInfoBase + 733, 0, 0, 0x6ULL }, // HSUB_U_D |
| 5801 | { 1810, 3, 1, 4, 831, 0, 0, MipsOpInfoBase + 739, 0, 0, 0x6ULL }, // HSUB_S_W |
| 5802 | { 1809, 3, 1, 4, 831, 0, 0, MipsOpInfoBase + 736, 0, 0, 0x6ULL }, // HSUB_S_H |
| 5803 | { 1808, 3, 1, 4, 831, 0, 0, MipsOpInfoBase + 733, 0, 0, 0x6ULL }, // HSUB_S_D |
| 5804 | { 1807, 3, 1, 4, 830, 0, 0, MipsOpInfoBase + 739, 0, 0, 0x6ULL }, // HADD_U_W |
| 5805 | { 1806, 3, 1, 4, 830, 0, 0, MipsOpInfoBase + 736, 0, 0, 0x6ULL }, // HADD_U_H |
| 5806 | { 1805, 3, 1, 4, 830, 0, 0, MipsOpInfoBase + 733, 0, 0, 0x6ULL }, // HADD_U_D |
| 5807 | { 1804, 3, 1, 4, 830, 0, 0, MipsOpInfoBase + 739, 0, 0, 0x6ULL }, // HADD_S_W |
| 5808 | { 1803, 3, 1, 4, 830, 0, 0, MipsOpInfoBase + 736, 0, 0, 0x6ULL }, // HADD_S_H |
| 5809 | { 1802, 3, 1, 4, 830, 0, 0, MipsOpInfoBase + 733, 0, 0, 0x6ULL }, // HADD_S_D |
| 5810 | { 1801, 2, 0, 4, 1217, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // GINVT_MMR6 |
| 5811 | { 1800, 2, 0, 4, 1163, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // GINVT |
| 5812 | { 1799, 1, 0, 4, 1216, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // GINVI_MMR6 |
| 5813 | { 1798, 1, 0, 4, 1162, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // GINVI |
| 5814 | { 1797, 2, 1, 4, 819, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FTRUNC_U_W |
| 5815 | { 1796, 2, 1, 4, 819, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FTRUNC_U_D |
| 5816 | { 1795, 2, 1, 4, 819, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FTRUNC_S_W |
| 5817 | { 1794, 2, 1, 4, 819, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FTRUNC_S_D |
| 5818 | { 1793, 3, 1, 4, 818, 0, 0, MipsOpInfoBase + 789, 0, 0, 0x6ULL }, // FTQ_W |
| 5819 | { 1792, 3, 1, 4, 818, 0, 0, MipsOpInfoBase + 786, 0, 0, 0x6ULL }, // FTQ_H |
| 5820 | { 1791, 2, 1, 4, 816, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FTINT_U_W |
| 5821 | { 1790, 2, 1, 4, 816, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FTINT_U_D |
| 5822 | { 1789, 2, 1, 4, 816, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FTINT_S_W |
| 5823 | { 1788, 2, 1, 4, 816, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FTINT_S_D |
| 5824 | { 1787, 3, 1, 4, 801, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSUN_W |
| 5825 | { 1786, 3, 1, 4, 801, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSUN_D |
| 5826 | { 1785, 3, 1, 4, 800, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSUNE_W |
| 5827 | { 1784, 3, 1, 4, 800, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSUNE_D |
| 5828 | { 1783, 3, 1, 4, 799, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSULT_W |
| 5829 | { 1782, 3, 1, 4, 799, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSULT_D |
| 5830 | { 1781, 3, 1, 4, 798, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSULE_W |
| 5831 | { 1780, 3, 1, 4, 798, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSULE_D |
| 5832 | { 1779, 3, 1, 4, 797, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSUEQ_W |
| 5833 | { 1778, 3, 1, 4, 797, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSUEQ_D |
| 5834 | { 1777, 3, 1, 4, 659, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSUB_W |
| 5835 | { 1776, 3, 1, 4, 1369, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // FSUB_S_MMR6 |
| 5836 | { 1775, 3, 1, 4, 1315, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_S_MM |
| 5837 | { 1774, 3, 1, 4, 565, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_S |
| 5838 | { 1773, 3, 1, 4, 842, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // FSUB_PS64 |
| 5839 | { 1772, 3, 1, 4, 1314, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_D64_MM |
| 5840 | { 1771, 3, 1, 4, 566, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_D64 |
| 5841 | { 1770, 3, 1, 4, 1314, 1, 0, MipsOpInfoBase + 771, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_D32_MM |
| 5842 | { 1769, 3, 1, 4, 566, 1, 0, MipsOpInfoBase + 771, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSUB_D32 |
| 5843 | { 1768, 3, 1, 4, 659, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSUB_D |
| 5844 | { 1767, 2, 1, 4, 853, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FSQRT_W |
| 5845 | { 1766, 2, 1, 4, 1320, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_S_MM |
| 5846 | { 1765, 2, 1, 4, 570, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_S |
| 5847 | { 1764, 2, 1, 4, 1321, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_D64_MM |
| 5848 | { 1763, 2, 1, 4, 573, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_D64 |
| 5849 | { 1762, 2, 1, 4, 1321, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_D32_MM |
| 5850 | { 1761, 2, 1, 4, 573, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FSQRT_D32 |
| 5851 | { 1760, 2, 1, 4, 572, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FSQRT_D |
| 5852 | { 1759, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSOR_W |
| 5853 | { 1758, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSOR_D |
| 5854 | { 1757, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSNE_W |
| 5855 | { 1756, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSNE_D |
| 5856 | { 1755, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSLT_W |
| 5857 | { 1754, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSLT_D |
| 5858 | { 1753, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSLE_W |
| 5859 | { 1752, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSLE_D |
| 5860 | { 1751, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSEQ_W |
| 5861 | { 1750, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSEQ_D |
| 5862 | { 1749, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FSAF_W |
| 5863 | { 1748, 3, 1, 4, 796, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FSAF_D |
| 5864 | { 1747, 2, 1, 4, 851, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FRSQRT_W |
| 5865 | { 1746, 2, 1, 4, 851, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FRSQRT_D |
| 5866 | { 1745, 2, 1, 4, 817, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FRINT_W |
| 5867 | { 1744, 2, 1, 4, 817, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FRINT_D |
| 5868 | { 1743, 2, 1, 4, 850, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FRCP_W |
| 5869 | { 1742, 2, 1, 4, 850, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FRCP_D |
| 5870 | { 1741, 3, 2, 4, 1145, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // FORK |
| 5871 | { 1740, 2, 1, 4, 1334, 0, 0, MipsOpInfoBase + 646, 0, 0, 0x4ULL }, // FNEG_S_MMR6 |
| 5872 | { 1739, 2, 1, 4, 1307, 0, 0, MipsOpInfoBase + 646, 0, 0, 0x4ULL }, // FNEG_S_MM |
| 5873 | { 1738, 2, 1, 4, 559, 0, 0, MipsOpInfoBase + 646, 0, 0, 0x4ULL }, // FNEG_S |
| 5874 | { 1737, 2, 1, 4, 1307, 0, 0, MipsOpInfoBase + 638, 0, 0, 0x4ULL }, // FNEG_D64_MM |
| 5875 | { 1736, 2, 1, 4, 559, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FNEG_D64 |
| 5876 | { 1735, 2, 1, 4, 1307, 0, 0, MipsOpInfoBase + 769, 0, 0, 0x4ULL }, // FNEG_D32_MM |
| 5877 | { 1734, 2, 1, 4, 559, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FNEG_D32 |
| 5878 | { 1733, 3, 1, 4, 854, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FMUL_W |
| 5879 | { 1732, 3, 1, 4, 1368, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x6ULL }, // FMUL_S_MMR6 |
| 5880 | { 1731, 3, 1, 4, 1313, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_S_MM |
| 5881 | { 1730, 3, 1, 4, 567, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_S |
| 5882 | { 1729, 3, 1, 4, 841, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // FMUL_PS64 |
| 5883 | { 1728, 3, 1, 4, 1312, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_D64_MM |
| 5884 | { 1727, 3, 1, 4, 568, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_D64 |
| 5885 | { 1726, 3, 1, 4, 1312, 1, 0, MipsOpInfoBase + 771, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_D32_MM |
| 5886 | { 1725, 3, 1, 4, 568, 1, 0, MipsOpInfoBase + 771, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FMUL_D32 |
| 5887 | { 1724, 3, 1, 4, 854, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FMUL_D |
| 5888 | { 1723, 4, 1, 4, 663, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // FMSUB_W |
| 5889 | { 1722, 4, 1, 4, 663, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // FMSUB_D |
| 5890 | { 1721, 2, 1, 4, 1367, 0, 0, MipsOpInfoBase + 646, 0, 0, 0x4ULL }, // FMOV_S_MMR6 |
| 5891 | { 1720, 2, 1, 4, 1311, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // FMOV_S_MM |
| 5892 | { 1719, 2, 1, 4, 560, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // FMOV_S |
| 5893 | { 1718, 2, 1, 4, 1370, 0, 0, MipsOpInfoBase + 638, 0, 0, 0x4ULL }, // FMOV_D_MMR6 |
| 5894 | { 1717, 2, 1, 4, 1310, 0, 0, MipsOpInfoBase + 638, 0, 0, 0x4ULL }, // FMOV_D64_MM |
| 5895 | { 1716, 2, 1, 4, 561, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FMOV_D64 |
| 5896 | { 1715, 2, 1, 4, 1310, 0, 0, MipsOpInfoBase + 769, 0, 0, 0x4ULL }, // FMOV_D32_MM |
| 5897 | { 1714, 2, 1, 4, 561, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FMOV_D32 |
| 5898 | { 1713, 3, 1, 4, 611, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FMIN_W |
| 5899 | { 1712, 3, 1, 4, 611, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FMIN_D |
| 5900 | { 1711, 3, 1, 4, 826, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FMIN_A_W |
| 5901 | { 1710, 3, 1, 4, 826, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FMIN_A_D |
| 5902 | { 1709, 3, 1, 4, 825, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FMAX_W |
| 5903 | { 1708, 3, 1, 4, 825, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FMAX_D |
| 5904 | { 1707, 3, 1, 4, 824, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FMAX_A_W |
| 5905 | { 1706, 3, 1, 4, 824, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FMAX_A_D |
| 5906 | { 1705, 4, 1, 4, 852, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // FMADD_W |
| 5907 | { 1704, 4, 1, 4, 852, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // FMADD_D |
| 5908 | { 1703, 2, 1, 4, 1344, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_S_MMR6 |
| 5909 | { 1702, 2, 1, 4, 1282, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_S_MM |
| 5910 | { 1701, 2, 1, 4, 648, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_S |
| 5911 | { 1700, 2, 1, 4, 1282, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_MM |
| 5912 | { 1699, 2, 1, 4, 1344, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_D_MMR6 |
| 5913 | { 1698, 2, 1, 4, 648, 0, 0, MipsOpInfoBase + 644, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_D64 |
| 5914 | { 1697, 2, 1, 4, 648, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_W_D32 |
| 5915 | { 1696, 2, 1, 4, 1344, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_L_S_MMR6 |
| 5916 | { 1695, 2, 1, 4, 648, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_L_S |
| 5917 | { 1694, 2, 1, 4, 1344, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_L_D_MMR6 |
| 5918 | { 1693, 2, 1, 4, 648, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FLOOR_L_D64 |
| 5919 | { 1692, 2, 1, 4, 658, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FLOG2_W |
| 5920 | { 1691, 2, 1, 4, 658, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FLOG2_D |
| 5921 | { 1690, 2, 1, 4, 602, 0, 0, MipsOpInfoBase + 802, 0, 0, 0x6ULL }, // FILL_W |
| 5922 | { 1689, 2, 1, 4, 602, 0, 0, MipsOpInfoBase + 800, 0, 0, 0x6ULL }, // FILL_H |
| 5923 | { 1688, 2, 1, 4, 602, 0, 0, MipsOpInfoBase + 798, 0, 0, 0x6ULL }, // FILL_D |
| 5924 | { 1687, 2, 1, 4, 602, 0, 0, MipsOpInfoBase + 796, 0, 0, 0x6ULL }, // FILL_B |
| 5925 | { 1686, 2, 1, 4, 815, 0, 0, MipsOpInfoBase + 794, 0, 0, 0x6ULL }, // FFQR_W |
| 5926 | { 1685, 2, 1, 4, 815, 0, 0, MipsOpInfoBase + 792, 0, 0, 0x6ULL }, // FFQR_D |
| 5927 | { 1684, 2, 1, 4, 814, 0, 0, MipsOpInfoBase + 794, 0, 0, 0x6ULL }, // FFQL_W |
| 5928 | { 1683, 2, 1, 4, 814, 0, 0, MipsOpInfoBase + 792, 0, 0, 0x6ULL }, // FFQL_D |
| 5929 | { 1682, 2, 1, 4, 813, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FFINT_U_W |
| 5930 | { 1681, 2, 1, 4, 813, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FFINT_U_D |
| 5931 | { 1680, 2, 1, 4, 813, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FFINT_S_W |
| 5932 | { 1679, 2, 1, 4, 813, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FFINT_S_D |
| 5933 | { 1678, 2, 1, 4, 822, 0, 0, MipsOpInfoBase + 794, 0, 0, 0x6ULL }, // FEXUPR_W |
| 5934 | { 1677, 2, 1, 4, 822, 0, 0, MipsOpInfoBase + 792, 0, 0, 0x6ULL }, // FEXUPR_D |
| 5935 | { 1676, 2, 1, 4, 821, 0, 0, MipsOpInfoBase + 794, 0, 0, 0x6ULL }, // FEXUPL_W |
| 5936 | { 1675, 2, 1, 4, 821, 0, 0, MipsOpInfoBase + 792, 0, 0, 0x6ULL }, // FEXUPL_D |
| 5937 | { 1674, 3, 1, 4, 792, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FEXP2_W |
| 5938 | { 1673, 3, 1, 4, 792, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FEXP2_D |
| 5939 | { 1672, 3, 1, 4, 820, 0, 0, MipsOpInfoBase + 789, 0, 0, 0x6ULL }, // FEXDO_W |
| 5940 | { 1671, 3, 1, 4, 820, 0, 0, MipsOpInfoBase + 786, 0, 0, 0x6ULL }, // FEXDO_H |
| 5941 | { 1670, 3, 1, 4, 669, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FDIV_W |
| 5942 | { 1669, 3, 1, 4, 1371, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x6ULL }, // FDIV_S_MMR6 |
| 5943 | { 1668, 3, 1, 4, 1318, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_S_MM |
| 5944 | { 1667, 3, 1, 4, 569, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_S |
| 5945 | { 1666, 3, 1, 4, 1319, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_D64_MM |
| 5946 | { 1665, 3, 1, 4, 571, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_D64 |
| 5947 | { 1664, 3, 1, 4, 1319, 1, 0, MipsOpInfoBase + 771, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_D32_MM |
| 5948 | { 1663, 3, 1, 4, 571, 1, 0, MipsOpInfoBase + 771, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FDIV_D32 |
| 5949 | { 1662, 3, 1, 4, 668, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FDIV_D |
| 5950 | { 1661, 3, 1, 4, 610, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUN_W |
| 5951 | { 1660, 3, 1, 4, 610, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUN_D |
| 5952 | { 1659, 3, 1, 4, 811, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUNE_W |
| 5953 | { 1658, 3, 1, 4, 811, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUNE_D |
| 5954 | { 1657, 3, 1, 4, 810, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCULT_W |
| 5955 | { 1656, 3, 1, 4, 810, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCULT_D |
| 5956 | { 1655, 3, 1, 4, 809, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCULE_W |
| 5957 | { 1654, 3, 1, 4, 809, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCULE_D |
| 5958 | { 1653, 3, 1, 4, 808, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUEQ_W |
| 5959 | { 1652, 3, 1, 4, 808, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCUEQ_D |
| 5960 | { 1651, 3, 1, 4, 807, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCOR_W |
| 5961 | { 1650, 3, 1, 4, 807, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCOR_D |
| 5962 | { 1649, 3, 1, 4, 806, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCNE_W |
| 5963 | { 1648, 3, 1, 4, 806, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCNE_D |
| 5964 | { 1647, 3, 0, 4, 1299, 0, 1, MipsOpInfoBase + 783, 30, 0, 0x44ULL }, // FCMP_S32_MM |
| 5965 | { 1646, 3, 0, 4, 848, 0, 1, MipsOpInfoBase + 783, 30, 0, 0x44ULL }, // FCMP_S32 |
| 5966 | { 1645, 3, 0, 4, 847, 0, 1, MipsOpInfoBase + 780, 30, 0, 0x44ULL }, // FCMP_D64 |
| 5967 | { 1644, 3, 0, 4, 1300, 0, 1, MipsOpInfoBase + 777, 30, 0, 0x44ULL }, // FCMP_D32_MM |
| 5968 | { 1643, 3, 0, 4, 847, 0, 1, MipsOpInfoBase + 777, 30, 0, 0x44ULL }, // FCMP_D32 |
| 5969 | { 1642, 3, 1, 4, 805, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FCLT_W |
| 5970 | { 1641, 3, 1, 4, 805, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FCLT_D |
| 5971 | { 1640, 3, 1, 4, 804, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // FCLE_W |
| 5972 | { 1639, 3, 1, 4, 804, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // FCLE_D |
| 5973 | { 1638, 2, 1, 4, 823, 0, 0, MipsOpInfoBase + 255, 0, 0, 0x6ULL }, // FCLASS_W |
| 5974 | { 1637, 2, 1, 4, 823, 0, 0, MipsOpInfoBase + 253, 0, 0, 0x6ULL }, // FCLASS_D |
| 5975 | { 1636, 3, 1, 4, 803, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCEQ_W |
| 5976 | { 1635, 3, 1, 4, 803, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCEQ_D |
| 5977 | { 1634, 3, 1, 4, 802, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCAF_W |
| 5978 | { 1633, 3, 1, 4, 802, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FCAF_D |
| 5979 | { 1632, 3, 1, 4, 855, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FADD_W |
| 5980 | { 1631, 3, 1, 4, 1349, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x6ULL }, // FADD_S_MMR6 |
| 5981 | { 1630, 3, 1, 4, 1309, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_S_MM |
| 5982 | { 1629, 3, 1, 4, 564, 1, 0, MipsOpInfoBase + 774, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_S |
| 5983 | { 1628, 3, 1, 4, 840, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // FADD_PS64 |
| 5984 | { 1627, 3, 1, 4, 1308, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_D64_MM |
| 5985 | { 1626, 3, 1, 4, 660, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_D64 |
| 5986 | { 1625, 3, 1, 4, 1308, 1, 0, MipsOpInfoBase + 771, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_D32_MM |
| 5987 | { 1624, 3, 1, 4, 660, 1, 0, MipsOpInfoBase + 771, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x4ULL }, // FADD_D32 |
| 5988 | { 1623, 3, 1, 4, 855, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // FADD_D |
| 5989 | { 1622, 2, 1, 4, 1306, 0, 0, MipsOpInfoBase + 646, 0, 0, 0x4ULL }, // FABS_S_MM |
| 5990 | { 1621, 2, 1, 4, 558, 0, 0, MipsOpInfoBase + 646, 0, 0, 0x4ULL }, // FABS_S |
| 5991 | { 1620, 2, 1, 4, 1305, 0, 0, MipsOpInfoBase + 638, 0, 0, 0x4ULL }, // FABS_D64_MM |
| 5992 | { 1619, 2, 1, 4, 612, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FABS_D64 |
| 5993 | { 1618, 2, 1, 4, 1305, 0, 0, MipsOpInfoBase + 769, 0, 0, 0x4ULL }, // FABS_D32_MM |
| 5994 | { 1617, 2, 1, 4, 612, 1, 0, MipsOpInfoBase + 769, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // FABS_D32 |
| 5995 | { 1616, 4, 1, 4, 946, 0, 0, MipsOpInfoBase + 662, 0, 0, 0x1ULL }, // EXT_MMR6 |
| 5996 | { 1615, 4, 1, 4, 905, 0, 0, MipsOpInfoBase + 662, 0, 0, 0x1ULL }, // EXT_MM |
| 5997 | { 1614, 4, 1, 4, 1256, 0, 0, MipsOpInfoBase + 654, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // EXTS32 |
| 5998 | { 1613, 4, 1, 4, 1256, 0, 0, MipsOpInfoBase + 654, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // EXTS |
| 5999 | { 1612, 3, 1, 4, 1579, 0, 1, MipsOpInfoBase + 763, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_W_MM |
| 6000 | { 1611, 3, 1, 4, 1384, 0, 1, MipsOpInfoBase + 763, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_W |
| 6001 | { 1610, 3, 1, 4, 1578, 0, 1, MipsOpInfoBase + 763, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_S_H_MM |
| 6002 | { 1609, 3, 1, 4, 1383, 0, 1, MipsOpInfoBase + 763, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_S_H |
| 6003 | { 1608, 3, 1, 4, 1577, 0, 1, MipsOpInfoBase + 763, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_R_W_MM |
| 6004 | { 1607, 3, 1, 4, 1382, 0, 1, MipsOpInfoBase + 763, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_R_W |
| 6005 | { 1606, 3, 1, 4, 1576, 0, 1, MipsOpInfoBase + 763, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_RS_W_MM |
| 6006 | { 1605, 3, 1, 4, 1381, 0, 1, MipsOpInfoBase + 763, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTR_RS_W |
| 6007 | { 1604, 3, 1, 4, 1575, 0, 1, MipsOpInfoBase + 766, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_W_MM |
| 6008 | { 1603, 3, 1, 4, 1380, 0, 1, MipsOpInfoBase + 766, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_W |
| 6009 | { 1602, 3, 1, 4, 1574, 0, 1, MipsOpInfoBase + 766, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_S_H_MM |
| 6010 | { 1601, 3, 1, 4, 1379, 0, 1, MipsOpInfoBase + 766, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_S_H |
| 6011 | { 1600, 3, 1, 4, 1573, 0, 1, MipsOpInfoBase + 766, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_R_W_MM |
| 6012 | { 1599, 3, 1, 4, 1378, 0, 1, MipsOpInfoBase + 766, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_R_W |
| 6013 | { 1598, 3, 1, 4, 1572, 0, 1, MipsOpInfoBase + 766, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_RS_W_MM |
| 6014 | { 1597, 3, 1, 4, 1377, 0, 1, MipsOpInfoBase + 766, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTRV_RS_W |
| 6015 | { 1596, 3, 1, 4, 1571, 1, 1, MipsOpInfoBase + 763, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTP_MM |
| 6016 | { 1595, 3, 1, 4, 1570, 1, 1, MipsOpInfoBase + 766, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPV_MM |
| 6017 | { 1594, 3, 1, 4, 1419, 1, 1, MipsOpInfoBase + 766, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPV |
| 6018 | { 1593, 3, 1, 4, 1569, 1, 2, MipsOpInfoBase + 763, 26, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPDP_MM |
| 6019 | { 1592, 3, 1, 4, 1568, 1, 2, MipsOpInfoBase + 766, 26, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPDPV_MM |
| 6020 | { 1591, 3, 1, 4, 1417, 1, 2, MipsOpInfoBase + 766, 26, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPDPV |
| 6021 | { 1590, 3, 1, 4, 1418, 1, 2, MipsOpInfoBase + 763, 26, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTPDP |
| 6022 | { 1589, 3, 1, 4, 1420, 1, 1, MipsOpInfoBase + 763, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EXTP |
| 6023 | { 1588, 4, 1, 4, 762, 0, 0, MipsOpInfoBase + 662, 0, 0, 0x1ULL }, // EXT |
| 6024 | { 1587, 1, 1, 4, 1129, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EVP_MMR6 |
| 6025 | { 1586, 1, 1, 4, 1141, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EVPE |
| 6026 | { 1585, 1, 1, 4, 536, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EVP |
| 6027 | { 1584, 0, 0, 4, 1088, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERET_MMR6 |
| 6028 | { 1583, 0, 0, 4, 1050, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERET_MM |
| 6029 | { 1582, 0, 0, 4, 1086, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERETNC_MMR6 |
| 6030 | { 1581, 0, 0, 4, 433, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERETNC |
| 6031 | { 1580, 0, 0, 4, 432, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // ERET |
| 6032 | { 1579, 1, 1, 4, 1140, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EMT |
| 6033 | { 1578, 1, 1, 4, 1132, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EI_MMR6 |
| 6034 | { 1577, 1, 1, 4, 1115, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EI_MM |
| 6035 | { 1576, 1, 1, 4, 446, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EI |
| 6036 | { 1575, 0, 0, 4, 1133, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EHB_MMR6 |
| 6037 | { 1574, 0, 0, 4, 1116, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EHB_MM |
| 6038 | { 1573, 0, 0, 4, 534, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // EHB |
| 6039 | { 1572, 2, 0, 2, 988, 0, 2, MipsOpInfoBase + 409, 7, 0, 0x0ULL }, // DivuRxRy16 |
| 6040 | { 1571, 2, 0, 2, 987, 0, 2, MipsOpInfoBase + 409, 7, 0, 0x0ULL }, // DivRxRy16 |
| 6041 | { 1570, 1, 1, 4, 1130, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DVP_MMR6 |
| 6042 | { 1569, 1, 1, 4, 1139, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DVPE |
| 6043 | { 1568, 1, 1, 4, 537, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DVP |
| 6044 | { 1567, 2, 0, 4, 1016, 0, 2, MipsOpInfoBase + 392, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DUDIV |
| 6045 | { 1566, 3, 1, 4, 492, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // DSUBu |
| 6046 | { 1565, 3, 1, 4, 491, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSUB |
| 6047 | { 1564, 3, 1, 4, 490, 0, 0, MipsOpInfoBase + 758, 0, 0, 0x1ULL }, // DSRLV |
| 6048 | { 1563, 3, 1, 4, 489, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSRL32 |
| 6049 | { 1562, 3, 1, 4, 488, 0, 0, MipsOpInfoBase + 235, 0, 0, 0x1ULL }, // DSRL |
| 6050 | { 1561, 3, 1, 4, 487, 0, 0, MipsOpInfoBase + 758, 0, 0, 0x1ULL }, // DSRAV |
| 6051 | { 1560, 3, 1, 4, 486, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSRA32 |
| 6052 | { 1559, 3, 1, 4, 485, 0, 0, MipsOpInfoBase + 235, 0, 0, 0x1ULL }, // DSRA |
| 6053 | { 1558, 3, 1, 4, 484, 0, 0, MipsOpInfoBase + 758, 0, 0, 0x1ULL }, // DSLLV |
| 6054 | { 1557, 2, 1, 4, 966, 0, 0, MipsOpInfoBase + 761, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSLL64_32 |
| 6055 | { 1556, 3, 1, 4, 483, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSLL32 |
| 6056 | { 1555, 3, 1, 4, 482, 0, 0, MipsOpInfoBase + 235, 0, 0, 0x1ULL }, // DSLL |
| 6057 | { 1554, 2, 1, 4, 481, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x1ULL }, // DSHD |
| 6058 | { 1553, 2, 0, 4, 1015, 0, 2, MipsOpInfoBase + 392, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DSDIV |
| 6059 | { 1552, 2, 1, 4, 480, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x1ULL }, // DSBH |
| 6060 | { 1551, 3, 1, 4, 479, 0, 0, MipsOpInfoBase + 758, 0, 0, 0x1ULL }, // DROTRV |
| 6061 | { 1550, 3, 1, 4, 478, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DROTR32 |
| 6062 | { 1549, 3, 1, 4, 477, 0, 0, MipsOpInfoBase + 235, 0, 0, 0x1ULL }, // DROTR |
| 6063 | { 1548, 4, 1, 4, 1674, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPS_W_PH_MMR2 |
| 6064 | { 1547, 4, 1, 4, 1510, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPS_W_PH |
| 6065 | { 1546, 4, 1, 4, 1677, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPSX_W_PH_MMR2 |
| 6066 | { 1545, 4, 1, 4, 1513, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPSX_W_PH |
| 6067 | { 1544, 4, 1, 4, 1567, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPSU_H_QBR_MM |
| 6068 | { 1543, 4, 1, 4, 1416, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPSU_H_QBR |
| 6069 | { 1542, 4, 1, 4, 1566, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPSU_H_QBL_MM |
| 6070 | { 1541, 4, 1, 4, 1415, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPSU_H_QBL |
| 6071 | { 1540, 4, 1, 4, 662, 0, 0, MipsOpInfoBase + 750, 0, 0, 0x6ULL }, // DPSUB_U_W |
| 6072 | { 1539, 4, 1, 4, 662, 0, 0, MipsOpInfoBase + 746, 0, 0, 0x6ULL }, // DPSUB_U_H |
| 6073 | { 1538, 4, 1, 4, 662, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPSUB_U_D |
| 6074 | { 1537, 4, 1, 4, 662, 0, 0, MipsOpInfoBase + 750, 0, 0, 0x6ULL }, // DPSUB_S_W |
| 6075 | { 1536, 4, 1, 4, 662, 0, 0, MipsOpInfoBase + 746, 0, 0, 0x6ULL }, // DPSUB_S_H |
| 6076 | { 1535, 4, 1, 4, 662, 0, 0, MipsOpInfoBase + 742, 0, 0, 0x6ULL }, // DPSUB_S_D |
| 6077 | { 1534, 4, 1, 4, 1565, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQ_S_W_PH_MM |
| 6078 | { 1533, 4, 1, 4, 1414, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQ_S_W_PH |
| 6079 | { 1532, 4, 1, 4, 1564, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQ_SA_L_W_MM |
| 6080 | { 1531, 4, 1, 4, 1413, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQ_SA_L_W |
| 6081 | { 1530, 4, 1, 4, 1675, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQX_S_W_PH_MMR2 |
| 6082 | { 1529, 4, 1, 4, 1511, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQX_S_W_PH |
| 6083 | { 1528, 4, 1, 4, 1676, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQX_SA_W_PH_MMR2 |
| 6084 | { 1527, 4, 1, 4, 1512, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPSQX_SA_W_PH |
| 6085 | { 1526, 2, 1, 4, 1255, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x1ULL }, // DPOP |
| 6086 | { 1525, 4, 1, 4, 1670, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPA_W_PH_MMR2 |
| 6087 | { 1524, 4, 1, 4, 1506, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPA_W_PH |
| 6088 | { 1523, 4, 1, 4, 1673, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPAX_W_PH_MMR2 |
| 6089 | { 1522, 4, 1, 4, 1509, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPAX_W_PH |
| 6090 | { 1521, 4, 1, 4, 1563, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPAU_H_QBR_MM |
| 6091 | { 1520, 4, 1, 4, 1412, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPAU_H_QBR |
| 6092 | { 1519, 4, 1, 4, 1562, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPAU_H_QBL_MM |
| 6093 | { 1518, 4, 1, 4, 1411, 0, 0, MipsOpInfoBase + 754, 0, 0, 0x6ULL }, // DPAU_H_QBL |
| 6094 | { 1517, 4, 1, 4, 1561, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQ_S_W_PH_MM |
| 6095 | { 1516, 4, 1, 4, 1410, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQ_S_W_PH |
| 6096 | { 1515, 4, 1, 4, 1560, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQ_SA_L_W_MM |
| 6097 | { 1514, 4, 1, 4, 1409, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQ_SA_L_W |
| 6098 | { 1513, 4, 1, 4, 1672, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQX_S_W_PH_MMR2 |
| 6099 | { 1512, 4, 1, 4, 1508, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQX_S_W_PH |
| 6100 | { 1511, 4, 1, 4, 1671, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQX_SA_W_PH_MMR2 |
| 6101 | { 1510, 4, 1, 4, 1507, 0, 1, MipsOpInfoBase + 754, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DPAQX_SA_W_PH |
| 6102 | { 1509, 4, 1, 4, 856, 0, 0, MipsOpInfoBase + 750, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_U_W |
| 6103 | { 1508, 4, 1, 4, 856, 0, 0, MipsOpInfoBase + 746, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_U_H |
| 6104 | { 1507, 4, 1, 4, 856, 0, 0, MipsOpInfoBase + 742, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_U_D |
| 6105 | { 1506, 4, 1, 4, 856, 0, 0, MipsOpInfoBase + 750, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_S_W |
| 6106 | { 1505, 4, 1, 4, 856, 0, 0, MipsOpInfoBase + 746, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_S_H |
| 6107 | { 1504, 4, 1, 4, 856, 0, 0, MipsOpInfoBase + 742, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DPADD_S_D |
| 6108 | { 1503, 3, 1, 4, 857, 0, 0, MipsOpInfoBase + 739, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_U_W |
| 6109 | { 1502, 3, 1, 4, 857, 0, 0, MipsOpInfoBase + 736, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_U_H |
| 6110 | { 1501, 3, 1, 4, 857, 0, 0, MipsOpInfoBase + 733, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_U_D |
| 6111 | { 1500, 3, 1, 4, 857, 0, 0, MipsOpInfoBase + 739, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_S_W |
| 6112 | { 1499, 3, 1, 4, 857, 0, 0, MipsOpInfoBase + 736, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_S_H |
| 6113 | { 1498, 3, 1, 4, 857, 0, 0, MipsOpInfoBase + 733, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // DOTP_S_D |
| 6114 | { 1497, 3, 1, 4, 546, 0, 0, MipsOpInfoBase + 238, 0, 0, 0x6ULL }, // DMUL_R6 |
| 6115 | { 1496, 3, 1, 4, 1012, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DMULU |
| 6116 | { 1495, 2, 0, 4, 1014, 0, 2, MipsOpInfoBase + 392, 21, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // DMULTu |
| 6117 | { 1494, 2, 0, 4, 1013, 0, 2, MipsOpInfoBase + 392, 21, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // DMULT |
| 6118 | { 1493, 3, 1, 4, 1261, 0, 5, MipsOpInfoBase + 238, 16, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // DMUL |
| 6119 | { 1492, 3, 1, 4, 548, 0, 0, MipsOpInfoBase + 238, 0, 0, 0x6ULL }, // DMUHU |
| 6120 | { 1491, 3, 1, 4, 547, 0, 0, MipsOpInfoBase + 238, 0, 0, 0x6ULL }, // DMUH |
| 6121 | { 1490, 3, 1, 4, 1147, 0, 0, MipsOpInfoBase + 727, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMTGC0 |
| 6122 | { 1489, 2, 2, 4, 1254, 0, 0, MipsOpInfoBase + 369, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMTC2_OCTEON |
| 6123 | { 1488, 3, 1, 4, 541, 0, 0, MipsOpInfoBase + 730, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMTC2 |
| 6124 | { 1487, 2, 1, 4, 476, 0, 0, MipsOpInfoBase + 419, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // DMTC1 |
| 6125 | { 1486, 3, 1, 4, 540, 0, 0, MipsOpInfoBase + 727, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMTC0 |
| 6126 | { 1485, 1, 1, 4, 1138, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DMT |
| 6127 | { 1484, 3, 1, 4, 556, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DMODU |
| 6128 | { 1483, 3, 1, 4, 554, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DMOD |
| 6129 | { 1482, 3, 1, 4, 1146, 0, 0, MipsOpInfoBase + 719, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMFGC0 |
| 6130 | { 1481, 2, 2, 4, 1253, 0, 0, MipsOpInfoBase + 369, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMFC2_OCTEON |
| 6131 | { 1480, 3, 1, 4, 539, 0, 0, MipsOpInfoBase + 724, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMFC2 |
| 6132 | { 1479, 2, 1, 4, 475, 0, 0, MipsOpInfoBase + 722, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // DMFC1 |
| 6133 | { 1478, 3, 1, 4, 538, 0, 0, MipsOpInfoBase + 719, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // DMFC0 |
| 6134 | { 1477, 4, 1, 4, 474, 0, 0, MipsOpInfoBase + 710, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DLSA_R6 |
| 6135 | { 1476, 4, 1, 4, 474, 0, 0, MipsOpInfoBase + 710, 0, 0, 0x6ULL }, // DLSA |
| 6136 | { 1475, 1, 1, 4, 1131, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DI_MMR6 |
| 6137 | { 1474, 1, 1, 4, 1114, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DI_MM |
| 6138 | { 1473, 3, 1, 4, 579, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // DIV_U_W |
| 6139 | { 1472, 3, 1, 4, 579, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // DIV_U_H |
| 6140 | { 1471, 3, 1, 4, 579, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // DIV_U_D |
| 6141 | { 1470, 3, 1, 4, 579, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // DIV_U_B |
| 6142 | { 1469, 3, 1, 4, 578, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // DIV_S_W |
| 6143 | { 1468, 3, 1, 4, 578, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // DIV_S_H |
| 6144 | { 1467, 3, 1, 4, 578, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // DIV_S_D |
| 6145 | { 1466, 3, 1, 4, 578, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // DIV_S_B |
| 6146 | { 1465, 3, 1, 4, 1010, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DIV_MMR6 |
| 6147 | { 1464, 3, 1, 4, 1009, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DIVU_MMR6 |
| 6148 | { 1463, 3, 1, 4, 550, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DIVU |
| 6149 | { 1462, 3, 1, 4, 549, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DIV |
| 6150 | { 1461, 5, 1, 4, 473, 0, 0, MipsOpInfoBase + 714, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DINSU |
| 6151 | { 1460, 5, 1, 4, 473, 0, 0, MipsOpInfoBase + 714, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DINSM |
| 6152 | { 1459, 5, 1, 4, 473, 0, 0, MipsOpInfoBase + 714, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DINS |
| 6153 | { 1458, 1, 1, 4, 444, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DI |
| 6154 | { 1457, 4, 1, 4, 472, 0, 0, MipsOpInfoBase + 654, 0, 0, 0x1ULL }, // DEXTU |
| 6155 | { 1456, 4, 1, 4, 472, 0, 0, MipsOpInfoBase + 654, 0, 0, 0x1ULL }, // DEXTM |
| 6156 | { 1455, 4, 1, 4, 965, 0, 0, MipsOpInfoBase + 658, 0, 0, 0x1ULL }, // DEXT64_32 |
| 6157 | { 1454, 4, 1, 4, 472, 0, 0, MipsOpInfoBase + 654, 0, 0, 0x1ULL }, // DEXT |
| 6158 | { 1453, 0, 0, 4, 1085, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // DERET_MMR6 |
| 6159 | { 1452, 0, 0, 4, 1049, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // DERET_MM |
| 6160 | { 1451, 0, 0, 4, 435, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // DERET |
| 6161 | { 1450, 3, 1, 4, 555, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DDIVU |
| 6162 | { 1449, 3, 1, 4, 553, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // DDIV |
| 6163 | { 1448, 2, 1, 4, 471, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x6ULL }, // DCLZ_R6 |
| 6164 | { 1447, 2, 1, 4, 970, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x1ULL }, // DCLZ |
| 6165 | { 1446, 2, 1, 4, 470, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x6ULL }, // DCLO_R6 |
| 6166 | { 1445, 2, 1, 4, 969, 0, 0, MipsOpInfoBase + 392, 0, 0, 0x1ULL }, // DCLO |
| 6167 | { 1444, 2, 1, 4, 469, 0, 0, MipsOpInfoBase + 392, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DBITSWAP |
| 6168 | { 1443, 3, 1, 4, 468, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DAUI |
| 6169 | { 1442, 3, 1, 4, 467, 0, 0, MipsOpInfoBase + 707, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DATI |
| 6170 | { 1441, 4, 1, 4, 466, 0, 0, MipsOpInfoBase + 710, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DALIGN |
| 6171 | { 1440, 3, 1, 4, 465, 0, 0, MipsOpInfoBase + 707, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // DAHI |
| 6172 | { 1439, 3, 1, 4, 464, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // DADDu |
| 6173 | { 1438, 3, 1, 4, 463, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // DADDiu |
| 6174 | { 1437, 3, 1, 4, 968, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // DADDi |
| 6175 | { 1436, 3, 1, 4, 462, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // DADD |
| 6176 | { 1435, 2, 0, 4, 894, 0, 1, MipsOpInfoBase + 583, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CmpiRxImmX16 |
| 6177 | { 1434, 2, 0, 2, 894, 0, 1, MipsOpInfoBase + 583, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CmpiRxImm16 |
| 6178 | { 1433, 2, 0, 2, 894, 0, 1, MipsOpInfoBase + 409, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CmpRxRy16 |
| 6179 | { 1432, 3, 1, 4, 1294, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_S_MM |
| 6180 | { 1431, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_S |
| 6181 | { 1430, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_D64_MM |
| 6182 | { 1429, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_D64 |
| 6183 | { 1428, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_D32_MM |
| 6184 | { 1427, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UN_D32 |
| 6185 | { 1426, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_S_MM |
| 6186 | { 1425, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_S |
| 6187 | { 1424, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_D64_MM |
| 6188 | { 1423, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_D64 |
| 6189 | { 1422, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_D32_MM |
| 6190 | { 1421, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULT_D32 |
| 6191 | { 1420, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_S_MM |
| 6192 | { 1419, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_S |
| 6193 | { 1418, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_D64_MM |
| 6194 | { 1417, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_D64 |
| 6195 | { 1416, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_D32_MM |
| 6196 | { 1415, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_ULE_D32 |
| 6197 | { 1414, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_S_MM |
| 6198 | { 1413, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_S |
| 6199 | { 1412, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_D64_MM |
| 6200 | { 1411, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_D64 |
| 6201 | { 1410, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_D32_MM |
| 6202 | { 1409, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_UEQ_D32 |
| 6203 | { 1408, 3, 1, 4, 1294, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_S_MM |
| 6204 | { 1407, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_S |
| 6205 | { 1406, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_D64_MM |
| 6206 | { 1405, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_D64 |
| 6207 | { 1404, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_D32_MM |
| 6208 | { 1403, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SF_D32 |
| 6209 | { 1402, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_S_MM |
| 6210 | { 1401, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_S |
| 6211 | { 1400, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_D64_MM |
| 6212 | { 1399, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_D64 |
| 6213 | { 1398, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_D32_MM |
| 6214 | { 1397, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_SEQ_D32 |
| 6215 | { 1396, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_S_MM |
| 6216 | { 1395, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_S |
| 6217 | { 1394, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_D64_MM |
| 6218 | { 1393, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_D64 |
| 6219 | { 1392, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_D32_MM |
| 6220 | { 1391, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLT_D32 |
| 6221 | { 1390, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_S_MM |
| 6222 | { 1389, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_S |
| 6223 | { 1388, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_D64_MM |
| 6224 | { 1387, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_D64 |
| 6225 | { 1386, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_D32_MM |
| 6226 | { 1385, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_OLE_D32 |
| 6227 | { 1384, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_S_MM |
| 6228 | { 1383, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_S |
| 6229 | { 1382, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_D64_MM |
| 6230 | { 1381, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_D64 |
| 6231 | { 1380, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_D32_MM |
| 6232 | { 1379, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGT_D32 |
| 6233 | { 1378, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_S_MM |
| 6234 | { 1377, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_S |
| 6235 | { 1376, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_D64_MM |
| 6236 | { 1375, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_D64 |
| 6237 | { 1374, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_D32_MM |
| 6238 | { 1373, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGL_D32 |
| 6239 | { 1372, 3, 1, 4, 1298, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_S_MM |
| 6240 | { 1371, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_S |
| 6241 | { 1370, 3, 1, 4, 1297, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_D64_MM |
| 6242 | { 1369, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_D64 |
| 6243 | { 1368, 3, 1, 4, 1297, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_D32_MM |
| 6244 | { 1367, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGLE_D32 |
| 6245 | { 1366, 3, 1, 4, 1296, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_S_MM |
| 6246 | { 1365, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_S |
| 6247 | { 1364, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_D64_MM |
| 6248 | { 1363, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_D64 |
| 6249 | { 1362, 3, 1, 4, 1295, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_D32_MM |
| 6250 | { 1361, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_NGE_D32 |
| 6251 | { 1360, 3, 1, 4, 1294, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_S_MM |
| 6252 | { 1359, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_S |
| 6253 | { 1358, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_D64_MM |
| 6254 | { 1357, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_D64 |
| 6255 | { 1356, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_D32_MM |
| 6256 | { 1355, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LT_D32 |
| 6257 | { 1354, 3, 1, 4, 1294, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_S_MM |
| 6258 | { 1353, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_S |
| 6259 | { 1352, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_D64_MM |
| 6260 | { 1351, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_D64 |
| 6261 | { 1350, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_D32_MM |
| 6262 | { 1349, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_LE_D32 |
| 6263 | { 1348, 3, 1, 4, 1292, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_S_MM |
| 6264 | { 1347, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_S |
| 6265 | { 1346, 3, 1, 4, 1291, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_D64_MM |
| 6266 | { 1345, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_D64 |
| 6267 | { 1344, 3, 1, 4, 1291, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_D32_MM |
| 6268 | { 1343, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_F_D32 |
| 6269 | { 1342, 3, 1, 4, 1294, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_S_MM |
| 6270 | { 1341, 3, 1, 4, 846, 0, 0, MipsOpInfoBase + 704, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_S |
| 6271 | { 1340, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_D64_MM |
| 6272 | { 1339, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 701, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_D64 |
| 6273 | { 1338, 3, 1, 4, 1293, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_D32_MM |
| 6274 | { 1337, 3, 1, 4, 845, 0, 0, MipsOpInfoBase + 698, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // C_EQ_D32 |
| 6275 | { 1336, 2, 1, 4, 1341, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_S_MMR6 |
| 6276 | { 1335, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_S_MM |
| 6277 | { 1334, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_S |
| 6278 | { 1333, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 644, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_D64_MM |
| 6279 | { 1332, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 644, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_D64 |
| 6280 | { 1331, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 642, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_D32_MM |
| 6281 | { 1330, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 642, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_W_D32 |
| 6282 | { 1329, 2, 1, 4, 1341, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_W_MMR6 |
| 6283 | { 1328, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_W_MM |
| 6284 | { 1327, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 646, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_W |
| 6285 | { 1326, 2, 1, 4, 649, 0, 0, MipsOpInfoBase + 644, 0, 0, 0x4ULL }, // CVT_S_PU64 |
| 6286 | { 1325, 2, 1, 4, 649, 0, 0, MipsOpInfoBase + 644, 0, 0, 0x4ULL }, // CVT_S_PL64 |
| 6287 | { 1324, 2, 1, 4, 1341, 1, 0, MipsOpInfoBase + 640, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_L_MMR6 |
| 6288 | { 1323, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 644, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_L |
| 6289 | { 1322, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 644, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_D64_MM |
| 6290 | { 1321, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 644, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_D64 |
| 6291 | { 1320, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 642, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_D32_MM |
| 6292 | { 1319, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 642, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_S_D32 |
| 6293 | { 1318, 2, 1, 4, 1264, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_PW_PS64 |
| 6294 | { 1317, 3, 1, 4, 844, 1, 0, MipsOpInfoBase + 695, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CVT_PS_S64 |
| 6295 | { 1316, 2, 1, 4, 1264, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_PS_PW64 |
| 6296 | { 1315, 2, 1, 4, 1341, 1, 0, MipsOpInfoBase + 640, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_S_MMR6 |
| 6297 | { 1314, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 640, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_S_MM |
| 6298 | { 1313, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 640, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_S |
| 6299 | { 1312, 2, 1, 4, 1341, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_D_MMR6 |
| 6300 | { 1311, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_D64_MM |
| 6301 | { 1310, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_L_D64 |
| 6302 | { 1309, 2, 1, 4, 1341, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D_L_MMR6 |
| 6303 | { 1308, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 640, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_W_MM |
| 6304 | { 1307, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 640, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_W |
| 6305 | { 1306, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 640, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_S_MM |
| 6306 | { 1305, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 640, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_S |
| 6307 | { 1304, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 638, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D64_L |
| 6308 | { 1303, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 693, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D32_W_MM |
| 6309 | { 1302, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 693, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D32_W |
| 6310 | { 1301, 2, 1, 4, 1280, 1, 0, MipsOpInfoBase + 693, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D32_S_MM |
| 6311 | { 1300, 2, 1, 4, 843, 1, 0, MipsOpInfoBase + 693, 11, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CVT_D32_S |
| 6312 | { 1299, 2, 0, 4, 780, 0, 0, MipsOpInfoBase + 691, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CTCMSA |
| 6313 | { 1298, 2, 1, 4, 1137, 0, 0, MipsOpInfoBase + 689, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CTC2_MM |
| 6314 | { 1297, 2, 1, 4, 1329, 0, 0, MipsOpInfoBase + 687, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CTC1_MM |
| 6315 | { 1296, 2, 1, 4, 461, 0, 0, MipsOpInfoBase + 687, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CTC1 |
| 6316 | { 1295, 3, 1, 4, 1244, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32W |
| 6317 | { 1294, 3, 1, 4, 1243, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32H |
| 6318 | { 1293, 3, 1, 4, 1248, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32D |
| 6319 | { 1292, 3, 1, 4, 1247, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32CW |
| 6320 | { 1291, 3, 1, 4, 1246, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32CH |
| 6321 | { 1290, 3, 1, 4, 1249, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32CD |
| 6322 | { 1289, 3, 1, 4, 1245, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32CB |
| 6323 | { 1288, 3, 1, 4, 1242, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CRC32B |
| 6324 | { 1287, 3, 1, 4, 874, 0, 0, MipsOpInfoBase + 684, 0, 0, 0x6ULL }, // COPY_U_W |
| 6325 | { 1286, 3, 1, 4, 874, 0, 0, MipsOpInfoBase + 681, 0, 0, 0x6ULL }, // COPY_U_H |
| 6326 | { 1285, 3, 1, 4, 874, 0, 0, MipsOpInfoBase + 675, 0, 0, 0x6ULL }, // COPY_U_B |
| 6327 | { 1284, 3, 1, 4, 607, 0, 0, MipsOpInfoBase + 684, 0, 0, 0x6ULL }, // COPY_S_W |
| 6328 | { 1283, 3, 1, 4, 607, 0, 0, MipsOpInfoBase + 681, 0, 0, 0x6ULL }, // COPY_S_H |
| 6329 | { 1282, 3, 1, 4, 607, 0, 0, MipsOpInfoBase + 678, 0, 0, 0x6ULL }, // COPY_S_D |
| 6330 | { 1281, 3, 1, 4, 607, 0, 0, MipsOpInfoBase + 675, 0, 0, 0x6ULL }, // COPY_S_B |
| 6331 | { 1280, 3, 1, 4, 1336, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_UN_S_MMR6 |
| 6332 | { 1279, 3, 1, 4, 614, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_UN_S |
| 6333 | { 1278, 3, 1, 4, 1335, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_UN_D_MMR6 |
| 6334 | { 1277, 3, 1, 4, 613, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_UN_D |
| 6335 | { 1276, 3, 1, 4, 1338, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_ULT_S_MMR6 |
| 6336 | { 1275, 3, 1, 4, 622, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_ULT_S |
| 6337 | { 1274, 3, 1, 4, 1337, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_ULT_D_MMR6 |
| 6338 | { 1273, 3, 1, 4, 621, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_ULT_D |
| 6339 | { 1272, 3, 1, 4, 1338, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_ULE_S_MMR6 |
| 6340 | { 1271, 3, 1, 4, 626, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_ULE_S |
| 6341 | { 1270, 3, 1, 4, 1337, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_ULE_D_MMR6 |
| 6342 | { 1269, 3, 1, 4, 625, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_ULE_D |
| 6343 | { 1268, 3, 1, 4, 1338, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_UEQ_S_MMR6 |
| 6344 | { 1267, 3, 1, 4, 616, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_UEQ_S |
| 6345 | { 1266, 3, 1, 4, 1337, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_UEQ_D_MMR6 |
| 6346 | { 1265, 3, 1, 4, 615, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_UEQ_D |
| 6347 | { 1264, 3, 1, 4, 1338, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUN_S_MMR6 |
| 6348 | { 1263, 3, 1, 4, 644, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUN_S |
| 6349 | { 1262, 3, 1, 4, 1337, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUN_D_MMR6 |
| 6350 | { 1261, 3, 1, 4, 643, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUN_D |
| 6351 | { 1260, 3, 1, 4, 1340, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULT_S_MMR6 |
| 6352 | { 1259, 3, 1, 4, 642, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULT_S |
| 6353 | { 1258, 3, 1, 4, 1339, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULT_D_MMR6 |
| 6354 | { 1257, 3, 1, 4, 641, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULT_D |
| 6355 | { 1256, 3, 1, 4, 1340, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULE_S_MMR6 |
| 6356 | { 1255, 3, 1, 4, 640, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULE_S |
| 6357 | { 1254, 3, 1, 4, 1339, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULE_D_MMR6 |
| 6358 | { 1253, 3, 1, 4, 639, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SULE_D |
| 6359 | { 1252, 3, 1, 4, 1340, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUEQ_S_MMR6 |
| 6360 | { 1251, 3, 1, 4, 638, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUEQ_S |
| 6361 | { 1250, 3, 1, 4, 1339, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUEQ_D_MMR6 |
| 6362 | { 1249, 3, 1, 4, 637, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SUEQ_D |
| 6363 | { 1248, 3, 1, 4, 1338, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLT_S_MMR6 |
| 6364 | { 1247, 3, 1, 4, 636, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLT_S |
| 6365 | { 1246, 3, 1, 4, 1337, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLT_D_MMR6 |
| 6366 | { 1245, 3, 1, 4, 635, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLT_D |
| 6367 | { 1244, 3, 1, 4, 1338, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLE_S_MMR6 |
| 6368 | { 1243, 3, 1, 4, 634, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLE_S |
| 6369 | { 1242, 3, 1, 4, 1337, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLE_D_MMR6 |
| 6370 | { 1241, 3, 1, 4, 633, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SLE_D |
| 6371 | { 1240, 3, 1, 4, 1338, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SEQ_S_MMR6 |
| 6372 | { 1239, 3, 1, 4, 632, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SEQ_S |
| 6373 | { 1238, 3, 1, 4, 1337, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SEQ_D_MMR6 |
| 6374 | { 1237, 3, 1, 4, 631, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SEQ_D |
| 6375 | { 1236, 3, 1, 4, 1338, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SAF_S_MMR6 |
| 6376 | { 1235, 3, 1, 4, 630, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SAF_S |
| 6377 | { 1234, 3, 1, 4, 1337, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SAF_D_MMR6 |
| 6378 | { 1233, 3, 1, 4, 629, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_SAF_D |
| 6379 | { 1232, 3, 1, 4, 1336, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_LT_S_MMR6 |
| 6380 | { 1231, 3, 1, 4, 620, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_LT_S |
| 6381 | { 1230, 2, 0, 4, 1559, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_LT_PH_MM |
| 6382 | { 1229, 2, 0, 4, 1408, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_LT_PH |
| 6383 | { 1228, 3, 1, 4, 1335, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_LT_D_MMR6 |
| 6384 | { 1227, 3, 1, 4, 619, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_LT_D |
| 6385 | { 1226, 3, 1, 4, 1336, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_LE_S_MMR6 |
| 6386 | { 1225, 3, 1, 4, 624, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_LE_S |
| 6387 | { 1224, 2, 0, 4, 1558, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_LE_PH_MM |
| 6388 | { 1223, 2, 0, 4, 1407, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_LE_PH |
| 6389 | { 1222, 3, 1, 4, 1335, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_LE_D_MMR6 |
| 6390 | { 1221, 3, 1, 4, 623, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_LE_D |
| 6391 | { 1220, 3, 1, 4, 628, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_F_S |
| 6392 | { 1219, 3, 1, 4, 627, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_F_D |
| 6393 | { 1218, 3, 1, 4, 1336, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_EQ_S_MMR6 |
| 6394 | { 1217, 3, 1, 4, 618, 0, 0, MipsOpInfoBase + 672, 0, 0, 0x16ULL }, // CMP_EQ_S |
| 6395 | { 1216, 2, 0, 4, 1557, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_EQ_PH_MM |
| 6396 | { 1215, 2, 0, 4, 1406, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMP_EQ_PH |
| 6397 | { 1214, 3, 1, 4, 1335, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_EQ_D_MMR6 |
| 6398 | { 1213, 3, 1, 4, 617, 0, 0, MipsOpInfoBase + 669, 0, 0, 0x16ULL }, // CMP_EQ_D |
| 6399 | { 1212, 3, 1, 4, 1336, 0, 0, MipsOpInfoBase + 672, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_AF_S_MMR6 |
| 6400 | { 1211, 3, 1, 4, 1335, 0, 0, MipsOpInfoBase + 669, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // CMP_AF_D_MMR6 |
| 6401 | { 1210, 2, 0, 4, 1556, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_LT_QB_MM |
| 6402 | { 1209, 2, 0, 4, 1405, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_LT_QB |
| 6403 | { 1208, 2, 0, 4, 1555, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_LE_QB_MM |
| 6404 | { 1207, 2, 0, 4, 1404, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_LE_QB |
| 6405 | { 1206, 2, 0, 4, 1554, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_EQ_QB_MM |
| 6406 | { 1205, 2, 0, 4, 1403, 0, 1, MipsOpInfoBase + 538, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPU_EQ_QB |
| 6407 | { 1204, 3, 1, 4, 1553, 0, 0, MipsOpInfoBase + 666, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_LT_QB_MM |
| 6408 | { 1203, 3, 1, 4, 1402, 0, 0, MipsOpInfoBase + 666, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_LT_QB |
| 6409 | { 1202, 3, 1, 4, 1552, 0, 0, MipsOpInfoBase + 666, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_LE_QB_MM |
| 6410 | { 1201, 3, 1, 4, 1401, 0, 0, MipsOpInfoBase + 666, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_LE_QB |
| 6411 | { 1200, 3, 1, 4, 1551, 0, 0, MipsOpInfoBase + 666, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_EQ_QB_MM |
| 6412 | { 1199, 3, 1, 4, 1400, 0, 0, MipsOpInfoBase + 666, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGU_EQ_QB |
| 6413 | { 1198, 3, 1, 4, 1669, 0, 1, MipsOpInfoBase + 666, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_LT_QB_MMR2 |
| 6414 | { 1197, 3, 1, 4, 1505, 0, 1, MipsOpInfoBase + 666, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_LT_QB |
| 6415 | { 1196, 3, 1, 4, 1668, 0, 1, MipsOpInfoBase + 666, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_LE_QB_MMR2 |
| 6416 | { 1195, 3, 1, 4, 1504, 0, 1, MipsOpInfoBase + 666, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_LE_QB |
| 6417 | { 1194, 3, 1, 4, 1667, 0, 1, MipsOpInfoBase + 666, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_EQ_QB_MMR2 |
| 6418 | { 1193, 3, 1, 4, 1503, 0, 1, MipsOpInfoBase + 666, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CMPGDU_EQ_QB |
| 6419 | { 1192, 2, 1, 4, 460, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x6ULL }, // CLZ_R6 |
| 6420 | { 1191, 2, 1, 4, 945, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLZ_MMR6 |
| 6421 | { 1190, 2, 1, 4, 904, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // CLZ_MM |
| 6422 | { 1189, 2, 1, 4, 747, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // CLZ |
| 6423 | { 1188, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // CLT_U_W |
| 6424 | { 1187, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // CLT_U_H |
| 6425 | { 1186, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // CLT_U_D |
| 6426 | { 1185, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CLT_U_B |
| 6427 | { 1184, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // CLT_S_W |
| 6428 | { 1183, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // CLT_S_H |
| 6429 | { 1182, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // CLT_S_D |
| 6430 | { 1181, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CLT_S_B |
| 6431 | { 1180, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // CLTI_U_W |
| 6432 | { 1179, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // CLTI_U_H |
| 6433 | { 1178, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // CLTI_U_D |
| 6434 | { 1177, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // CLTI_U_B |
| 6435 | { 1176, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // CLTI_S_W |
| 6436 | { 1175, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // CLTI_S_H |
| 6437 | { 1174, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // CLTI_S_D |
| 6438 | { 1173, 3, 1, 4, 793, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // CLTI_S_B |
| 6439 | { 1172, 2, 1, 4, 459, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x6ULL }, // CLO_R6 |
| 6440 | { 1171, 2, 1, 4, 944, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLO_MMR6 |
| 6441 | { 1170, 2, 1, 4, 903, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // CLO_MM |
| 6442 | { 1169, 2, 1, 4, 746, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x1ULL }, // CLO |
| 6443 | { 1168, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // CLE_U_W |
| 6444 | { 1167, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // CLE_U_H |
| 6445 | { 1166, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // CLE_U_D |
| 6446 | { 1165, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CLE_U_B |
| 6447 | { 1164, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // CLE_S_W |
| 6448 | { 1163, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // CLE_S_H |
| 6449 | { 1162, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // CLE_S_D |
| 6450 | { 1161, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // CLE_S_B |
| 6451 | { 1160, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // CLEI_U_W |
| 6452 | { 1159, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // CLEI_U_H |
| 6453 | { 1158, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // CLEI_U_D |
| 6454 | { 1157, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // CLEI_U_B |
| 6455 | { 1156, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // CLEI_S_W |
| 6456 | { 1155, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // CLEI_S_H |
| 6457 | { 1154, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // CLEI_S_D |
| 6458 | { 1153, 3, 1, 4, 794, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // CLEI_S_B |
| 6459 | { 1152, 2, 1, 4, 1348, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLASS_S_MMR6 |
| 6460 | { 1151, 2, 1, 4, 562, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLASS_S |
| 6461 | { 1150, 2, 1, 4, 1348, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLASS_D_MMR6 |
| 6462 | { 1149, 2, 1, 4, 563, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CLASS_D |
| 6463 | { 1148, 4, 1, 4, 1252, 0, 0, MipsOpInfoBase + 662, 0, 0, 0x1ULL }, // CINS_i32 |
| 6464 | { 1147, 4, 1, 4, 1252, 0, 0, MipsOpInfoBase + 658, 0, 0, 0x1ULL }, // CINS64_32 |
| 6465 | { 1146, 4, 1, 4, 1252, 0, 0, MipsOpInfoBase + 654, 0, 0, 0x1ULL }, // CINS32 |
| 6466 | { 1145, 4, 1, 4, 1252, 0, 0, MipsOpInfoBase + 654, 0, 0, 0x1ULL }, // CINS |
| 6467 | { 1144, 2, 1, 4, 780, 0, 0, MipsOpInfoBase + 652, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CFCMSA |
| 6468 | { 1143, 2, 1, 4, 1136, 0, 0, MipsOpInfoBase + 650, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CFC2_MM |
| 6469 | { 1142, 2, 1, 4, 1328, 0, 0, MipsOpInfoBase + 648, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CFC1_MM |
| 6470 | { 1141, 2, 1, 4, 458, 0, 0, MipsOpInfoBase + 648, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // CFC1 |
| 6471 | { 1140, 3, 1, 4, 795, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // CEQ_W |
| 6472 | { 1139, 3, 1, 4, 795, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // CEQ_H |
| 6473 | { 1138, 3, 1, 4, 795, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // CEQ_D |
| 6474 | { 1137, 3, 1, 4, 795, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // CEQ_B |
| 6475 | { 1136, 3, 1, 4, 795, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // CEQI_W |
| 6476 | { 1135, 3, 1, 4, 795, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // CEQI_H |
| 6477 | { 1134, 3, 1, 4, 795, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // CEQI_D |
| 6478 | { 1133, 3, 1, 4, 795, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // CEQI_B |
| 6479 | { 1132, 2, 1, 4, 1345, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_S_MMR6 |
| 6480 | { 1131, 2, 1, 4, 1281, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_S_MM |
| 6481 | { 1130, 2, 1, 4, 650, 0, 0, MipsOpInfoBase + 646, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_S |
| 6482 | { 1129, 2, 1, 4, 1281, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_MM |
| 6483 | { 1128, 2, 1, 4, 1345, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_D_MMR6 |
| 6484 | { 1127, 2, 1, 4, 650, 0, 0, MipsOpInfoBase + 644, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_D64 |
| 6485 | { 1126, 2, 1, 4, 650, 0, 0, MipsOpInfoBase + 642, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_W_D32 |
| 6486 | { 1125, 2, 1, 4, 1345, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_L_S_MMR6 |
| 6487 | { 1124, 2, 1, 4, 650, 0, 0, MipsOpInfoBase + 640, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_L_S |
| 6488 | { 1123, 2, 1, 4, 1345, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_L_D_MMR6 |
| 6489 | { 1122, 2, 1, 4, 650, 0, 0, MipsOpInfoBase + 638, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x4ULL }, // CEIL_L_D64 |
| 6490 | { 1121, 3, 0, 4, 382, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHE_R6 |
| 6491 | { 1120, 3, 0, 4, 1235, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHE_MMR6 |
| 6492 | { 1119, 3, 0, 4, 1213, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHE_MM |
| 6493 | { 1118, 3, 0, 4, 1180, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHEE_MM |
| 6494 | { 1117, 3, 0, 4, 745, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHEE |
| 6495 | { 1116, 3, 0, 4, 744, 0, 0, MipsOpInfoBase + 635, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // CACHE |
| 6496 | { 1115, 1, 0, 4, 1036, 1, 0, MipsOpInfoBase + 0, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BtnezX16 |
| 6497 | { 1114, 1, 0, 2, 1036, 1, 0, MipsOpInfoBase + 0, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Btnez16 |
| 6498 | { 1113, 1, 0, 4, 1036, 1, 0, MipsOpInfoBase + 0, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BteqzX16 |
| 6499 | { 1112, 1, 0, 2, 1036, 1, 0, MipsOpInfoBase + 0, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Bteqz16 |
| 6500 | { 1111, 0, 0, 2, 1040, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Break16 |
| 6501 | { 1110, 2, 0, 4, 1036, 0, 0, MipsOpInfoBase + 633, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BnezRxImmX16 |
| 6502 | { 1109, 2, 0, 2, 1036, 0, 0, MipsOpInfoBase + 633, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // BnezRxImm16 |
| 6503 | { 1108, 1, 0, 4, 1036, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BimmX16 |
| 6504 | { 1107, 1, 0, 2, 1036, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Bimm16 |
| 6505 | { 1106, 2, 0, 4, 1036, 0, 0, MipsOpInfoBase + 633, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BeqzRxImmX16 |
| 6506 | { 1105, 2, 0, 2, 1036, 0, 0, MipsOpInfoBase + 633, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // BeqzRxImm16 |
| 6507 | { 1104, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 631, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_W |
| 6508 | { 1103, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 625, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_V |
| 6509 | { 1102, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 629, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_H |
| 6510 | { 1101, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 627, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_D |
| 6511 | { 1100, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 625, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BZ_B |
| 6512 | { 1099, 3, 1, 4, 656, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // BSET_W |
| 6513 | { 1098, 3, 1, 4, 656, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // BSET_H |
| 6514 | { 1097, 3, 1, 4, 656, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // BSET_D |
| 6515 | { 1096, 3, 1, 4, 656, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // BSET_B |
| 6516 | { 1095, 3, 1, 4, 656, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // BSETI_W |
| 6517 | { 1094, 3, 1, 4, 656, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // BSETI_H |
| 6518 | { 1093, 3, 1, 4, 656, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // BSETI_D |
| 6519 | { 1092, 3, 1, 4, 656, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // BSETI_B |
| 6520 | { 1091, 4, 1, 4, 654, 0, 0, MipsOpInfoBase + 621, 0, 0, 0x6ULL }, // BSEL_V |
| 6521 | { 1090, 4, 1, 4, 654, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // BSELI_B |
| 6522 | { 1089, 2, 0, 4, 1104, 0, 0, MipsOpInfoBase + 13, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BREAK_MMR6 |
| 6523 | { 1088, 2, 0, 4, 1063, 0, 0, MipsOpInfoBase + 13, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BREAK_MM |
| 6524 | { 1087, 1, 0, 2, 1104, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BREAK16_MMR6 |
| 6525 | { 1086, 1, 0, 2, 1063, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BREAK16_MM |
| 6526 | { 1085, 2, 0, 4, 431, 0, 0, MipsOpInfoBase + 13, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BREAK |
| 6527 | { 1084, 1, 0, 4, 1550, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BPOSGE32_MM |
| 6528 | { 1083, 1, 0, 4, 1702, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BPOSGE32C_MMR3 |
| 6529 | { 1082, 1, 0, 4, 1399, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BPOSGE32 |
| 6530 | { 1081, 3, 0, 4, 1082, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BOVC_MMR6 |
| 6531 | { 1080, 3, 0, 4, 1029, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BOVC |
| 6532 | { 1079, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 631, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_W |
| 6533 | { 1078, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 625, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_V |
| 6534 | { 1077, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 629, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_H |
| 6535 | { 1076, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 627, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_D |
| 6536 | { 1075, 2, 0, 4, 779, 0, 1, MipsOpInfoBase + 625, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BNZ_B |
| 6537 | { 1074, 3, 0, 4, 1082, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BNVC_MMR6 |
| 6538 | { 1073, 3, 0, 4, 1029, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNVC |
| 6539 | { 1072, 3, 0, 4, 1048, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BNE_MM |
| 6540 | { 1071, 2, 0, 4, 1084, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BNEZC_MMR6 |
| 6541 | { 1070, 2, 0, 4, 1047, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // BNEZC_MM |
| 6542 | { 1069, 2, 0, 4, 426, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEZC64 |
| 6543 | { 1068, 2, 0, 2, 1083, 0, 1, MipsOpInfoBase + 603, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BNEZC16_MMR6 |
| 6544 | { 1067, 2, 0, 4, 1030, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEZC |
| 6545 | { 1066, 2, 0, 4, 1097, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BNEZALC_MMR6 |
| 6546 | { 1065, 2, 0, 4, 1027, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEZALC |
| 6547 | { 1064, 2, 0, 2, 1046, 0, 1, MipsOpInfoBase + 603, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BNEZ16_MM |
| 6548 | { 1063, 3, 0, 4, 682, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BNEL |
| 6549 | { 1062, 3, 1, 4, 776, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // BNEG_W |
| 6550 | { 1061, 3, 1, 4, 776, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // BNEG_H |
| 6551 | { 1060, 3, 1, 4, 776, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // BNEG_D |
| 6552 | { 1059, 3, 1, 4, 776, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // BNEG_B |
| 6553 | { 1058, 3, 1, 4, 776, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // BNEGI_W |
| 6554 | { 1057, 3, 1, 4, 776, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // BNEGI_H |
| 6555 | { 1056, 3, 1, 4, 776, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // BNEGI_D |
| 6556 | { 1055, 3, 1, 4, 776, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // BNEGI_B |
| 6557 | { 1054, 3, 0, 4, 1082, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BNEC_MMR6 |
| 6558 | { 1053, 3, 0, 4, 425, 0, 1, MipsOpInfoBase + 354, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEC64 |
| 6559 | { 1052, 3, 0, 4, 1029, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BNEC |
| 6560 | { 1051, 3, 0, 4, 416, 0, 1, MipsOpInfoBase + 354, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BNE64 |
| 6561 | { 1050, 3, 0, 4, 681, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BNE |
| 6562 | { 1049, 4, 1, 4, 777, 0, 0, MipsOpInfoBase + 621, 0, 0, 0x6ULL }, // BMZ_V |
| 6563 | { 1048, 4, 1, 4, 777, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // BMZI_B |
| 6564 | { 1047, 4, 1, 4, 777, 0, 0, MipsOpInfoBase + 621, 0, 0, 0x6ULL }, // BMNZ_V |
| 6565 | { 1046, 4, 1, 4, 777, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // BMNZI_B |
| 6566 | { 1045, 2, 0, 4, 1046, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLTZ_MM |
| 6567 | { 1044, 2, 0, 4, 685, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLTZL |
| 6568 | { 1043, 2, 0, 4, 1084, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLTZC_MMR6 |
| 6569 | { 1042, 2, 0, 4, 426, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTZC64 |
| 6570 | { 1041, 2, 0, 4, 1030, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTZC |
| 6571 | { 1040, 2, 0, 4, 1055, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLTZAL_MM |
| 6572 | { 1039, 2, 0, 4, 1054, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // BLTZALS_MM |
| 6573 | { 1038, 2, 0, 4, 684, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLTZALL |
| 6574 | { 1037, 2, 0, 4, 1097, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLTZALC_MMR6 |
| 6575 | { 1036, 2, 0, 4, 1027, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BLTZALC |
| 6576 | { 1035, 2, 0, 4, 1022, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLTZAL |
| 6577 | { 1034, 2, 0, 4, 417, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLTZ64 |
| 6578 | { 1033, 2, 0, 4, 683, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLTZ |
| 6579 | { 1032, 3, 0, 4, 1082, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLTUC_MMR6 |
| 6580 | { 1031, 3, 0, 4, 425, 0, 1, MipsOpInfoBase + 354, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTUC64 |
| 6581 | { 1030, 3, 0, 4, 1029, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTUC |
| 6582 | { 1029, 3, 0, 4, 1082, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLTC_MMR6 |
| 6583 | { 1028, 3, 0, 4, 425, 0, 1, MipsOpInfoBase + 354, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTC64 |
| 6584 | { 1027, 3, 0, 4, 1029, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLTC |
| 6585 | { 1026, 2, 0, 4, 1046, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLEZ_MM |
| 6586 | { 1025, 2, 0, 4, 685, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BLEZL |
| 6587 | { 1024, 2, 0, 4, 1084, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLEZC_MMR6 |
| 6588 | { 1023, 2, 0, 4, 426, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLEZC64 |
| 6589 | { 1022, 2, 0, 4, 1030, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BLEZC |
| 6590 | { 1021, 2, 0, 4, 1097, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BLEZALC_MMR6 |
| 6591 | { 1020, 2, 0, 4, 1027, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BLEZALC |
| 6592 | { 1019, 2, 0, 4, 417, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLEZ64 |
| 6593 | { 1018, 2, 0, 4, 683, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BLEZ |
| 6594 | { 1017, 2, 1, 4, 943, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BITSWAP_MMR6 |
| 6595 | { 1016, 2, 1, 4, 457, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // BITSWAP |
| 6596 | { 1015, 2, 1, 4, 1549, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x6ULL }, // BITREV_MM |
| 6597 | { 1014, 2, 1, 4, 1398, 0, 0, MipsOpInfoBase + 155, 0, 0, 0x6ULL }, // BITREV |
| 6598 | { 1013, 4, 1, 4, 772, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // BINSR_W |
| 6599 | { 1012, 4, 1, 4, 772, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // BINSR_H |
| 6600 | { 1011, 4, 1, 4, 772, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // BINSR_D |
| 6601 | { 1010, 4, 1, 4, 772, 0, 0, MipsOpInfoBase + 621, 0, 0, 0x6ULL }, // BINSR_B |
| 6602 | { 1009, 4, 1, 4, 772, 0, 0, MipsOpInfoBase + 617, 0, 0, 0x6ULL }, // BINSRI_W |
| 6603 | { 1008, 4, 1, 4, 772, 0, 0, MipsOpInfoBase + 613, 0, 0, 0x6ULL }, // BINSRI_H |
| 6604 | { 1007, 4, 1, 4, 772, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // BINSRI_D |
| 6605 | { 1006, 4, 1, 4, 772, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // BINSRI_B |
| 6606 | { 1005, 4, 1, 4, 771, 0, 0, MipsOpInfoBase + 205, 0, 0, 0x6ULL }, // BINSL_W |
| 6607 | { 1004, 4, 1, 4, 771, 0, 0, MipsOpInfoBase + 209, 0, 0, 0x6ULL }, // BINSL_H |
| 6608 | { 1003, 4, 1, 4, 771, 0, 0, MipsOpInfoBase + 201, 0, 0, 0x6ULL }, // BINSL_D |
| 6609 | { 1002, 4, 1, 4, 771, 0, 0, MipsOpInfoBase + 621, 0, 0, 0x6ULL }, // BINSL_B |
| 6610 | { 1001, 4, 1, 4, 771, 0, 0, MipsOpInfoBase + 617, 0, 0, 0x6ULL }, // BINSLI_W |
| 6611 | { 1000, 4, 1, 4, 771, 0, 0, MipsOpInfoBase + 613, 0, 0, 0x6ULL }, // BINSLI_H |
| 6612 | { 999, 4, 1, 4, 771, 0, 0, MipsOpInfoBase + 609, 0, 0, 0x6ULL }, // BINSLI_D |
| 6613 | { 998, 4, 1, 4, 771, 0, 0, MipsOpInfoBase + 605, 0, 0, 0x6ULL }, // BINSLI_B |
| 6614 | { 997, 2, 0, 4, 1046, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGTZ_MM |
| 6615 | { 996, 2, 0, 4, 685, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGTZL |
| 6616 | { 995, 2, 0, 4, 1084, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGTZC_MMR6 |
| 6617 | { 994, 2, 0, 4, 426, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGTZC64 |
| 6618 | { 993, 2, 0, 4, 1030, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGTZC |
| 6619 | { 992, 2, 0, 4, 1097, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGTZALC_MMR6 |
| 6620 | { 991, 2, 0, 4, 1027, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BGTZALC |
| 6621 | { 990, 2, 0, 4, 417, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGTZ64 |
| 6622 | { 989, 2, 0, 4, 683, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGTZ |
| 6623 | { 988, 2, 0, 4, 1046, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGEZ_MM |
| 6624 | { 987, 2, 0, 4, 685, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGEZL |
| 6625 | { 986, 2, 0, 4, 1084, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGEZC_MMR6 |
| 6626 | { 985, 2, 0, 4, 426, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEZC64 |
| 6627 | { 984, 2, 0, 4, 1030, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEZC |
| 6628 | { 983, 2, 0, 4, 1055, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGEZAL_MM |
| 6629 | { 982, 2, 0, 4, 1054, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // BGEZALS_MM |
| 6630 | { 981, 2, 0, 4, 684, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGEZALL |
| 6631 | { 980, 2, 0, 4, 1097, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGEZALC_MMR6 |
| 6632 | { 979, 2, 0, 4, 1027, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BGEZALC |
| 6633 | { 978, 2, 0, 4, 1026, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BGEZAL |
| 6634 | { 977, 2, 0, 4, 417, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGEZ64 |
| 6635 | { 976, 2, 0, 4, 683, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BGEZ |
| 6636 | { 975, 3, 0, 4, 1082, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGEUC_MMR6 |
| 6637 | { 974, 3, 0, 4, 425, 0, 1, MipsOpInfoBase + 354, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEUC64 |
| 6638 | { 973, 3, 0, 4, 1029, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEUC |
| 6639 | { 972, 3, 0, 4, 1082, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BGEC_MMR6 |
| 6640 | { 971, 3, 0, 4, 425, 0, 1, MipsOpInfoBase + 354, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEC64 |
| 6641 | { 970, 3, 0, 4, 1029, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BGEC |
| 6642 | { 969, 3, 0, 4, 1048, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BEQ_MM |
| 6643 | { 968, 2, 0, 4, 1084, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // BEQZC_MMR6 |
| 6644 | { 967, 2, 0, 4, 1047, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // BEQZC_MM |
| 6645 | { 966, 2, 0, 4, 426, 0, 1, MipsOpInfoBase + 362, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQZC64 |
| 6646 | { 965, 2, 0, 2, 1083, 0, 1, MipsOpInfoBase + 603, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BEQZC16_MMR6 |
| 6647 | { 964, 2, 0, 4, 1030, 0, 1, MipsOpInfoBase + 360, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQZC |
| 6648 | { 963, 2, 0, 4, 1097, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BEQZALC_MMR6 |
| 6649 | { 962, 2, 0, 4, 1027, 0, 1, MipsOpInfoBase + 360, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQZALC |
| 6650 | { 961, 2, 0, 2, 1046, 0, 1, MipsOpInfoBase + 603, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BEQZ16_MM |
| 6651 | { 960, 3, 0, 4, 682, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BEQL |
| 6652 | { 959, 3, 0, 4, 1082, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BEQC_MMR6 |
| 6653 | { 958, 3, 0, 4, 425, 0, 1, MipsOpInfoBase + 354, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQC64 |
| 6654 | { 957, 3, 0, 4, 1029, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // BEQC |
| 6655 | { 956, 3, 0, 4, 416, 0, 1, MipsOpInfoBase + 354, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BEQ64 |
| 6656 | { 955, 3, 0, 4, 681, 0, 1, MipsOpInfoBase + 197, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // BEQ |
| 6657 | { 954, 1, 0, 4, 1079, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL }, // BC_MMR6 |
| 6658 | { 953, 3, 1, 4, 775, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // BCLR_W |
| 6659 | { 952, 3, 1, 4, 775, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // BCLR_H |
| 6660 | { 951, 3, 1, 4, 775, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // BCLR_D |
| 6661 | { 950, 3, 1, 4, 775, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // BCLR_B |
| 6662 | { 949, 3, 1, 4, 775, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // BCLRI_W |
| 6663 | { 948, 3, 1, 4, 775, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // BCLRI_H |
| 6664 | { 947, 3, 1, 4, 775, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // BCLRI_D |
| 6665 | { 946, 3, 1, 4, 775, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // BCLRI_B |
| 6666 | { 945, 2, 0, 4, 1081, 0, 1, MipsOpInfoBase + 601, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC2NEZC_MMR6 |
| 6667 | { 944, 2, 0, 4, 439, 0, 0, MipsOpInfoBase + 601, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC2NEZ |
| 6668 | { 943, 2, 0, 4, 1081, 0, 1, MipsOpInfoBase + 601, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC2EQZC_MMR6 |
| 6669 | { 942, 2, 0, 4, 439, 0, 0, MipsOpInfoBase + 601, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC2EQZ |
| 6670 | { 941, 2, 0, 4, 1045, 0, 1, MipsOpInfoBase + 599, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // BC1T_MM |
| 6671 | { 940, 2, 0, 4, 878, 0, 1, MipsOpInfoBase + 599, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // BC1TL |
| 6672 | { 939, 2, 0, 4, 877, 0, 1, MipsOpInfoBase + 599, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // BC1T |
| 6673 | { 938, 2, 0, 4, 1080, 0, 1, MipsOpInfoBase + 597, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BC1NEZC_MMR6 |
| 6674 | { 937, 2, 0, 4, 430, 0, 0, MipsOpInfoBase + 597, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC1NEZ |
| 6675 | { 936, 2, 0, 4, 1044, 0, 1, MipsOpInfoBase + 599, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // BC1F_MM |
| 6676 | { 935, 2, 0, 4, 876, 0, 1, MipsOpInfoBase + 599, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // BC1FL |
| 6677 | { 934, 2, 0, 4, 875, 0, 1, MipsOpInfoBase + 599, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // BC1F |
| 6678 | { 933, 2, 0, 4, 1080, 0, 1, MipsOpInfoBase + 597, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // BC1EQZC_MMR6 |
| 6679 | { 932, 2, 0, 4, 430, 0, 0, MipsOpInfoBase + 597, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC1EQZ |
| 6680 | { 931, 1, 0, 2, 1079, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BC16_MMR6 |
| 6681 | { 930, 1, 0, 4, 428, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BC |
| 6682 | { 929, 3, 0, 4, 1251, 0, 1, MipsOpInfoBase + 594, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // BBIT132 |
| 6683 | { 928, 3, 0, 4, 1251, 0, 1, MipsOpInfoBase + 594, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // BBIT1 |
| 6684 | { 927, 3, 0, 4, 1251, 0, 1, MipsOpInfoBase + 594, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // BBIT032 |
| 6685 | { 926, 3, 0, 4, 1251, 0, 1, MipsOpInfoBase + 594, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // BBIT0 |
| 6686 | { 925, 4, 1, 4, 1666, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x6ULL }, // BALIGN_MMR2 |
| 6687 | { 924, 4, 1, 4, 1502, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x6ULL }, // BALIGN |
| 6688 | { 923, 1, 0, 4, 1096, 0, 1, MipsOpInfoBase + 193, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BALC_MMR6 |
| 6689 | { 922, 1, 0, 4, 429, 0, 1, MipsOpInfoBase + 193, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BALC |
| 6690 | { 921, 1, 0, 4, 680, 0, 1, MipsOpInfoBase + 193, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // BAL |
| 6691 | { 920, 3, 1, 4, 1250, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // BADDu |
| 6692 | { 919, 1, 0, 2, 1042, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // B16_MM |
| 6693 | { 918, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 591, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // AndRxRxRy16 |
| 6694 | { 917, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // AdduRxRyRz16 |
| 6695 | { 916, 1, 0, 4, 894, 1, 1, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AddiuSpImmX16 |
| 6696 | { 915, 1, 0, 2, 894, 1, 1, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AddiuSpImm16 |
| 6697 | { 914, 3, 1, 4, 894, 0, 0, MipsOpInfoBase + 588, 0, 0, 0x0ULL }, // AddiuRxRyOffMemX16 |
| 6698 | { 913, 3, 1, 4, 894, 0, 0, MipsOpInfoBase + 585, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // AddiuRxRxImmX16 |
| 6699 | { 912, 3, 1, 2, 894, 0, 0, MipsOpInfoBase + 585, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // AddiuRxRxImm16 |
| 6700 | { 911, 2, 1, 4, 894, 0, 0, MipsOpInfoBase + 583, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AddiuRxPcImmX16 |
| 6701 | { 910, 2, 1, 4, 894, 0, 0, MipsOpInfoBase + 583, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AddiuRxImmX16 |
| 6702 | { 909, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_U_W |
| 6703 | { 908, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_U_H |
| 6704 | { 907, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_U_D |
| 6705 | { 906, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_U_B |
| 6706 | { 905, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_S_W |
| 6707 | { 904, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_S_H |
| 6708 | { 903, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_S_D |
| 6709 | { 902, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVE_S_B |
| 6710 | { 901, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_U_W |
| 6711 | { 900, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_U_H |
| 6712 | { 899, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_U_D |
| 6713 | { 898, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_U_B |
| 6714 | { 897, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_S_W |
| 6715 | { 896, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_S_H |
| 6716 | { 895, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_S_D |
| 6717 | { 894, 3, 1, 4, 788, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // AVER_S_B |
| 6718 | { 893, 3, 1, 4, 942, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // AUI_MMR6 |
| 6719 | { 892, 2, 1, 4, 941, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // AUIPC_MMR6 |
| 6720 | { 891, 2, 1, 4, 456, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // AUIPC |
| 6721 | { 890, 3, 1, 4, 455, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // AUI |
| 6722 | { 889, 3, 1, 4, 582, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // ASUB_U_W |
| 6723 | { 888, 3, 1, 4, 582, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // ASUB_U_H |
| 6724 | { 887, 3, 1, 4, 582, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // ASUB_U_D |
| 6725 | { 886, 3, 1, 4, 582, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // ASUB_U_B |
| 6726 | { 885, 3, 1, 4, 581, 0, 0, MipsOpInfoBase + 163, 0, 0, 0x6ULL }, // ASUB_S_W |
| 6727 | { 884, 3, 1, 4, 581, 0, 0, MipsOpInfoBase + 160, 0, 0, 0x6ULL }, // ASUB_S_H |
| 6728 | { 883, 3, 1, 4, 581, 0, 0, MipsOpInfoBase + 157, 0, 0, 0x6ULL }, // ASUB_S_D |
| 6729 | { 882, 3, 1, 4, 581, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // ASUB_S_B |
| 6730 | { 881, 4, 1, 4, 1665, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x6ULL }, // APPEND_MMR2 |
| 6731 | { 880, 4, 1, 4, 1501, 0, 0, MipsOpInfoBase + 579, 0, 0, 0x6ULL }, // APPEND |
| 6732 | { 879, 3, 1, 4, 902, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ANDi_MM |
| 6733 | { 878, 3, 1, 4, 453, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ANDi64 |
| 6734 | { 877, 3, 1, 4, 454, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ANDi |
| 6735 | { 876, 3, 1, 4, 791, 0, 0, MipsOpInfoBase + 554, 0, 0, 0x6ULL }, // AND_V |
| 6736 | { 875, 3, 1, 4, 939, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // AND_MMR6 |
| 6737 | { 874, 3, 1, 4, 901, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // AND_MM |
| 6738 | { 873, 3, 1, 4, 940, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ANDI_MMR6 |
| 6739 | { 872, 3, 1, 4, 591, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // ANDI_B |
| 6740 | { 871, 3, 1, 2, 939, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x0ULL }, // ANDI16_MMR6 |
| 6741 | { 870, 3, 1, 2, 901, 0, 0, MipsOpInfoBase + 542, 0, 0, 0x0ULL }, // ANDI16_MM |
| 6742 | { 869, 3, 1, 4, 453, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // AND64 |
| 6743 | { 868, 3, 1, 2, 939, 0, 0, MipsOpInfoBase + 576, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AND16_MMR6 |
| 6744 | { 867, 3, 1, 2, 901, 0, 0, MipsOpInfoBase + 576, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // AND16_MM |
| 6745 | { 866, 3, 1, 4, 673, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // AND |
| 6746 | { 865, 2, 1, 4, 938, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ALUIPC_MMR6 |
| 6747 | { 864, 2, 1, 4, 452, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ALUIPC |
| 6748 | { 863, 4, 1, 4, 937, 0, 0, MipsOpInfoBase + 572, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ALIGN_MMR6 |
| 6749 | { 862, 4, 1, 4, 451, 0, 0, MipsOpInfoBase + 572, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ALIGN |
| 6750 | { 861, 3, 1, 4, 898, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // ADDu_MM |
| 6751 | { 860, 3, 1, 4, 450, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // ADDu |
| 6752 | { 859, 3, 1, 4, 897, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ADDiu_MM |
| 6753 | { 858, 3, 1, 4, 448, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // ADDiu |
| 6754 | { 857, 3, 1, 4, 900, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // ADDi_MM |
| 6755 | { 856, 3, 1, 4, 764, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // ADDi |
| 6756 | { 855, 3, 1, 4, 936, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADD_MMR6 |
| 6757 | { 854, 3, 1, 4, 899, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADD_MM |
| 6758 | { 853, 3, 1, 4, 785, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADD_A_W |
| 6759 | { 852, 3, 1, 4, 785, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADD_A_H |
| 6760 | { 851, 3, 1, 4, 785, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADD_A_D |
| 6761 | { 850, 3, 1, 4, 785, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADD_A_B |
| 6762 | { 849, 3, 1, 4, 1548, 1, 1, MipsOpInfoBase + 241, 13, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDWC_MM |
| 6763 | { 848, 3, 1, 4, 1397, 1, 1, MipsOpInfoBase + 241, 13, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDWC |
| 6764 | { 847, 3, 1, 4, 787, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDV_W |
| 6765 | { 846, 3, 1, 4, 787, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDV_H |
| 6766 | { 845, 3, 1, 4, 787, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDV_D |
| 6767 | { 844, 3, 1, 4, 787, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDV_B |
| 6768 | { 843, 3, 1, 4, 787, 0, 0, MipsOpInfoBase + 569, 0, 0, 0x6ULL }, // ADDVI_W |
| 6769 | { 842, 3, 1, 4, 787, 0, 0, MipsOpInfoBase + 566, 0, 0, 0x6ULL }, // ADDVI_H |
| 6770 | { 841, 3, 1, 4, 787, 0, 0, MipsOpInfoBase + 563, 0, 0, 0x6ULL }, // ADDVI_D |
| 6771 | { 840, 3, 1, 4, 787, 0, 0, MipsOpInfoBase + 560, 0, 0, 0x6ULL }, // ADDVI_B |
| 6772 | { 839, 3, 1, 4, 1547, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDU_S_QB_MM |
| 6773 | { 838, 3, 1, 4, 1396, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDU_S_QB |
| 6774 | { 837, 3, 1, 4, 1664, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_S_PH_MMR2 |
| 6775 | { 836, 3, 1, 4, 1500, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_S_PH |
| 6776 | { 835, 3, 1, 4, 1546, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_QB_MM |
| 6777 | { 834, 3, 1, 4, 1395, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDU_QB |
| 6778 | { 833, 3, 1, 4, 1663, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_PH_MMR2 |
| 6779 | { 832, 3, 1, 4, 1499, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDU_PH |
| 6780 | { 831, 3, 1, 4, 935, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADDU_MMR6 |
| 6781 | { 830, 3, 1, 4, 1662, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDUH_R_QB_MMR2 |
| 6782 | { 829, 3, 1, 4, 1498, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDUH_R_QB |
| 6783 | { 828, 3, 1, 4, 1661, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDUH_QB_MMR2 |
| 6784 | { 827, 3, 1, 4, 1497, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDUH_QB |
| 6785 | { 826, 3, 1, 2, 935, 0, 0, MipsOpInfoBase + 557, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // ADDU16_MMR6 |
| 6786 | { 825, 3, 1, 2, 898, 0, 0, MipsOpInfoBase + 557, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // ADDU16_MM |
| 6787 | { 824, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_U_W |
| 6788 | { 823, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_U_H |
| 6789 | { 822, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_U_D |
| 6790 | { 821, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_U_B |
| 6791 | { 820, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_S_W |
| 6792 | { 819, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_S_H |
| 6793 | { 818, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_S_D |
| 6794 | { 817, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_S_B |
| 6795 | { 816, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_A_W |
| 6796 | { 815, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_A_H |
| 6797 | { 814, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_A_D |
| 6798 | { 813, 3, 1, 4, 786, 0, 0, MipsOpInfoBase + 554, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDS_A_B |
| 6799 | { 812, 3, 1, 4, 1545, 0, 1, MipsOpInfoBase + 241, 12, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDSC_MM |
| 6800 | { 811, 3, 1, 4, 1394, 0, 1, MipsOpInfoBase + 241, 12, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDSC |
| 6801 | { 810, 3, 1, 4, 1263, 1, 0, MipsOpInfoBase + 551, 11, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // ADDR_PS64 |
| 6802 | { 809, 3, 1, 4, 1544, 0, 1, MipsOpInfoBase + 241, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDQ_S_W_MM |
| 6803 | { 808, 3, 1, 4, 1393, 0, 1, MipsOpInfoBase + 241, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDQ_S_W |
| 6804 | { 807, 3, 1, 4, 1543, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQ_S_PH_MM |
| 6805 | { 806, 3, 1, 4, 1392, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQ_S_PH |
| 6806 | { 805, 3, 1, 4, 1542, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDQ_PH_MM |
| 6807 | { 804, 3, 1, 4, 1391, 0, 1, MipsOpInfoBase + 548, 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQ_PH |
| 6808 | { 803, 3, 1, 4, 1660, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_W_MMR2 |
| 6809 | { 802, 3, 1, 4, 1496, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_W |
| 6810 | { 801, 3, 1, 4, 1659, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_R_W_MMR2 |
| 6811 | { 800, 3, 1, 4, 1495, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_R_W |
| 6812 | { 799, 3, 1, 4, 1658, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_R_PH_MMR2 |
| 6813 | { 798, 3, 1, 4, 1494, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_R_PH |
| 6814 | { 797, 3, 1, 4, 1657, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_PH_MMR2 |
| 6815 | { 796, 3, 1, 4, 1493, 0, 0, MipsOpInfoBase + 548, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // ADDQH_PH |
| 6816 | { 795, 3, 1, 4, 934, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // ADDIU_MMR6 |
| 6817 | { 794, 1, 0, 2, 897, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDIUSP_MM |
| 6818 | { 793, 3, 1, 2, 897, 0, 0, MipsOpInfoBase + 545, 0, 0, 0x0ULL }, // ADDIUS5_MM |
| 6819 | { 792, 3, 1, 2, 897, 0, 0, MipsOpInfoBase + 542, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // ADDIUR2_MM |
| 6820 | { 791, 2, 1, 2, 897, 0, 0, MipsOpInfoBase + 540, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDIUR1SP_MM |
| 6821 | { 790, 2, 1, 4, 933, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDIUPC_MMR6 |
| 6822 | { 789, 2, 1, 4, 897, 0, 0, MipsOpInfoBase + 540, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADDIUPC_MM |
| 6823 | { 788, 2, 1, 4, 449, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ADDIUPC |
| 6824 | { 787, 3, 1, 4, 447, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // ADD |
| 6825 | { 786, 2, 1, 4, 1541, 0, 1, MipsOpInfoBase + 155, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_W_MM |
| 6826 | { 785, 2, 1, 4, 1390, 0, 1, MipsOpInfoBase + 155, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_W |
| 6827 | { 784, 2, 1, 4, 1656, 0, 1, MipsOpInfoBase + 538, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_QB_MMR2 |
| 6828 | { 783, 2, 1, 4, 1492, 0, 1, MipsOpInfoBase + 538, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_QB |
| 6829 | { 782, 2, 1, 4, 1540, 0, 1, MipsOpInfoBase + 538, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_PH_MM |
| 6830 | { 781, 2, 1, 4, 1389, 0, 1, MipsOpInfoBase + 538, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // ABSQ_S_PH |
| 6831 | { 780, 3, 1, 4, 594, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // XOR_V_W_PSEUDO |
| 6832 | { 779, 3, 1, 4, 594, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // XOR_V_H_PSEUDO |
| 6833 | { 778, 3, 1, 4, 594, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // XOR_V_D_PSEUDO |
| 6834 | { 777, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Usw |
| 6835 | { 776, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Ush |
| 6836 | { 775, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Ulw |
| 6837 | { 774, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Ulhu |
| 6838 | { 773, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Ulh |
| 6839 | { 772, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // URemMacro |
| 6840 | { 771, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // URemIMacro |
| 6841 | { 770, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDivMacro |
| 6842 | { 769, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDivIMacro |
| 6843 | { 768, 3, 1, 4, 997, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIV_MM_Pseudo |
| 6844 | { 767, 0, 0, 4, 1078, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAP_MM |
| 6845 | { 766, 0, 0, 4, 445, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAP |
| 6846 | { 765, 1, 0, 4, 1103, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALL_MMR6 |
| 6847 | { 764, 1, 0, 4, 1061, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALL_MM |
| 6848 | { 763, 1, 0, 4, 1102, 0, 1, MipsOpInfoBase + 200, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREG_MMR6 |
| 6849 | { 762, 1, 0, 4, 1060, 0, 1, MipsOpInfoBase + 200, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREG_MM |
| 6850 | { 761, 1, 0, 4, 1108, 0, 1, MipsOpInfoBase + 321, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREGHB64 |
| 6851 | { 760, 1, 0, 4, 686, 0, 1, MipsOpInfoBase + 200, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREGHB |
| 6852 | { 759, 1, 0, 4, 1108, 0, 1, MipsOpInfoBase + 321, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREG64 |
| 6853 | { 758, 1, 0, 4, 686, 0, 1, MipsOpInfoBase + 200, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLREG |
| 6854 | { 757, 1, 0, 4, 1035, 0, 1, MipsOpInfoBase + 200, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLR6REG |
| 6855 | { 756, 1, 0, 4, 1035, 0, 1, MipsOpInfoBase + 200, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLHBR6REG |
| 6856 | { 755, 1, 0, 4, 420, 0, 1, MipsOpInfoBase + 321, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALLHB64R6REG |
| 6857 | { 754, 1, 0, 4, 420, 0, 1, MipsOpInfoBase + 321, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALL64R6REG |
| 6858 | { 753, 1, 0, 4, 412, 0, 1, MipsOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // TAILCALL |
| 6859 | { 752, 3, 1, 2, 895, 0, 1, MipsOpInfoBase + 411, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SltuRxRyRz16 |
| 6860 | { 751, 3, 1, 2, 895, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SltuCCRxRy16 |
| 6861 | { 750, 3, 1, 2, 895, 0, 0, MipsOpInfoBase + 535, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SltiuCCRxImmX16 |
| 6862 | { 749, 3, 1, 2, 895, 0, 0, MipsOpInfoBase + 535, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SltiCCRxImmX16 |
| 6863 | { 748, 3, 1, 2, 895, 0, 0, MipsOpInfoBase + 411, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SltCCRxRy16 |
| 6864 | { 747, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 525, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZSltu |
| 6865 | { 746, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SelTBtneZSltiu |
| 6866 | { 745, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZSlti |
| 6867 | { 744, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 525, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZSlt |
| 6868 | { 743, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZCmpi |
| 6869 | { 742, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 525, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBtneZCmp |
| 6870 | { 741, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 525, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBteqZSltu |
| 6871 | { 740, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SelTBteqZSltiu |
| 6872 | { 739, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SelTBteqZSlti |
| 6873 | { 738, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 525, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBteqZSlt |
| 6874 | { 737, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 530, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBteqZCmpi |
| 6875 | { 736, 5, 1, 2, 1041, 0, 0, MipsOpInfoBase + 525, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelTBteqZCmp |
| 6876 | { 735, 4, 1, 2, 1041, 0, 0, MipsOpInfoBase + 521, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelBneZ |
| 6877 | { 734, 4, 1, 2, 1041, 0, 0, MipsOpInfoBase + 521, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SelBeqZ |
| 6878 | { 733, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SaadAddr |
| 6879 | { 732, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SaaAddr |
| 6880 | { 731, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 519, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_W_PSEUDO |
| 6881 | { 730, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_V_PSEUDO |
| 6882 | { 729, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 517, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_H_PSEUDO |
| 6883 | { 728, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 515, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_D_PSEUDO |
| 6884 | { 727, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SZ_B_PSEUDO |
| 6885 | { 726, 3, 0, 4, 1209, 0, 0, MipsOpInfoBase + 364, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWM_MM |
| 6886 | { 725, 3, 0, 4, 884, 0, 0, MipsOpInfoBase + 331, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ST_F16 |
| 6887 | { 724, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 328, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STR_W |
| 6888 | { 723, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 325, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STR_D |
| 6889 | { 722, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 343, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // STORE_CCOND_DSP |
| 6890 | { 721, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 340, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // STORE_ACC64DSP |
| 6891 | { 720, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 337, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // STORE_ACC64 |
| 6892 | { 719, 3, 0, 4, 0, 0, 0, MipsOpInfoBase + 334, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // STORE_ACC128 |
| 6893 | { 718, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SRemMacro |
| 6894 | { 717, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SRemIMacro |
| 6895 | { 716, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 519, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_W_PSEUDO |
| 6896 | { 715, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_V_PSEUDO |
| 6897 | { 714, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 517, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_H_PSEUDO |
| 6898 | { 713, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 515, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_D_PSEUDO |
| 6899 | { 712, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 513, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SNZ_B_PSEUDO |
| 6900 | { 711, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SNEMacro |
| 6901 | { 710, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SNEIMacro |
| 6902 | { 709, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLTUImm64 |
| 6903 | { 708, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLTImm64 |
| 6904 | { 707, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEUImm64 |
| 6905 | { 706, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEUImm |
| 6906 | { 705, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEU |
| 6907 | { 704, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEImm64 |
| 6908 | { 703, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLEImm |
| 6909 | { 702, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SLE |
| 6910 | { 701, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGTUImm64 |
| 6911 | { 700, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGTUImm |
| 6912 | { 699, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGTImm64 |
| 6913 | { 698, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGTImm |
| 6914 | { 697, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEUImm64 |
| 6915 | { 696, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEUImm |
| 6916 | { 695, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEU |
| 6917 | { 694, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEImm64 |
| 6918 | { 693, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGEImm |
| 6919 | { 692, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SGE |
| 6920 | { 691, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEQMacro |
| 6921 | { 690, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEQIMacro |
| 6922 | { 689, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 510, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDivMacro |
| 6923 | { 688, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDivIMacro |
| 6924 | { 687, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDMacro |
| 6925 | { 686, 3, 1, 4, 996, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIV_MM_Pseudo |
| 6926 | { 685, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 507, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDC1_M1 |
| 6927 | { 684, 0, 0, 2, 1037, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL }, // RetRA16 |
| 6928 | { 683, 0, 0, 4, 438, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // RetRA |
| 6929 | { 682, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RORImm |
| 6930 | { 681, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ROR |
| 6931 | { 680, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ROLImm |
| 6932 | { 679, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ROL |
| 6933 | { 678, 3, 1, 4, 753, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoUDIV |
| 6934 | { 677, 3, 1, 4, 646, 0, 0, MipsOpInfoBase + 504, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoTRUNC_W_S |
| 6935 | { 676, 3, 1, 4, 646, 0, 0, MipsOpInfoBase + 501, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoTRUNC_W_D32 |
| 6936 | { 675, 3, 1, 4, 646, 0, 0, MipsOpInfoBase + 498, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoTRUNC_W_D |
| 6937 | { 674, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 494, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_S |
| 6938 | { 673, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 490, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_I64 |
| 6939 | { 672, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 486, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_I |
| 6940 | { 671, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 482, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_D64 |
| 6941 | { 670, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 478, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECT_D32 |
| 6942 | { 669, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 474, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_S |
| 6943 | { 668, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 470, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_I64 |
| 6944 | { 667, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 466, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_I |
| 6945 | { 666, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 462, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_D64 |
| 6946 | { 665, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 458, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_T_D32 |
| 6947 | { 664, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 474, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_S |
| 6948 | { 663, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 470, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_I64 |
| 6949 | { 662, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 466, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_I |
| 6950 | { 661, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 462, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_D64 |
| 6951 | { 660, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 458, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // PseudoSELECTFP_F_D32 |
| 6952 | { 659, 3, 1, 4, 752, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoSDIV |
| 6953 | { 658, 1, 0, 4, 437, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // PseudoReturn64 |
| 6954 | { 657, 1, 0, 4, 689, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // PseudoReturn |
| 6955 | { 656, 4, 1, 4, 1491, 0, 0, MipsOpInfoBase + 454, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoPICK_QB |
| 6956 | { 655, 4, 1, 4, 1491, 0, 0, MipsOpInfoBase + 454, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoPICK_PH |
| 6957 | { 654, 3, 1, 4, 981, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoMULTu_MM |
| 6958 | { 653, 3, 1, 4, 983, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoMULTu |
| 6959 | { 652, 3, 1, 4, 980, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoMULT_MM |
| 6960 | { 651, 3, 1, 4, 982, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoMULT |
| 6961 | { 650, 3, 1, 4, 985, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMTLOHI_MM |
| 6962 | { 649, 3, 1, 4, 1376, 0, 0, MipsOpInfoBase + 451, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMTLOHI_DSP |
| 6963 | { 648, 3, 1, 4, 1018, 0, 0, MipsOpInfoBase + 423, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMTLOHI64 |
| 6964 | { 647, 3, 1, 4, 761, 0, 0, MipsOpInfoBase + 448, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMTLOHI |
| 6965 | { 646, 4, 1, 4, 978, 0, 0, MipsOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMSUB_MM |
| 6966 | { 645, 4, 1, 4, 979, 0, 0, MipsOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMSUBU_MM |
| 6967 | { 644, 4, 1, 4, 760, 0, 0, MipsOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMSUBU |
| 6968 | { 643, 4, 1, 4, 759, 0, 0, MipsOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMSUB |
| 6969 | { 642, 2, 1, 4, 984, 0, 0, MipsOpInfoBase + 444, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFLO_MM |
| 6970 | { 641, 2, 1, 4, 1017, 0, 0, MipsOpInfoBase + 446, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFLO64 |
| 6971 | { 640, 2, 1, 4, 748, 0, 0, MipsOpInfoBase + 444, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFLO |
| 6972 | { 639, 2, 1, 4, 984, 0, 0, MipsOpInfoBase + 444, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFHI_MM |
| 6973 | { 638, 2, 1, 4, 1017, 0, 0, MipsOpInfoBase + 446, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFHI64 |
| 6974 | { 637, 2, 1, 4, 748, 0, 0, MipsOpInfoBase + 444, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMFHI |
| 6975 | { 636, 4, 1, 4, 976, 0, 0, MipsOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMADD_MM |
| 6976 | { 635, 4, 1, 4, 977, 0, 0, MipsOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMADDU_MM |
| 6977 | { 634, 4, 1, 4, 758, 0, 0, MipsOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMADDU |
| 6978 | { 633, 4, 1, 4, 757, 0, 0, MipsOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoMADD |
| 6979 | { 632, 1, 0, 4, 1034, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndrectHazardBranchR6 |
| 6980 | { 631, 1, 0, 4, 427, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndrectHazardBranch64R6 |
| 6981 | { 630, 1, 0, 4, 1109, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectHazardBranch64 |
| 6982 | { 629, 1, 0, 4, 688, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectHazardBranch |
| 6983 | { 628, 1, 0, 4, 1095, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch_MMR6 |
| 6984 | { 627, 1, 0, 4, 1062, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch_MM |
| 6985 | { 626, 1, 0, 4, 1034, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranchR6 |
| 6986 | { 625, 1, 0, 4, 427, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch64R6 |
| 6987 | { 624, 1, 0, 4, 1109, 0, 0, MipsOpInfoBase + 321, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch64 |
| 6988 | { 623, 1, 0, 4, 688, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // PseudoIndirectBranch |
| 6989 | { 622, 7, 2, 4, 1, 0, 0, MipsOpInfoBase + 433, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoD_SELECT_I64 |
| 6990 | { 621, 7, 2, 4, 1, 0, 0, MipsOpInfoBase + 426, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoD_SELECT_I |
| 6991 | { 620, 3, 1, 4, 1016, 0, 0, MipsOpInfoBase + 423, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoDUDIV |
| 6992 | { 619, 3, 1, 4, 1015, 0, 0, MipsOpInfoBase + 423, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PseudoDSDIV |
| 6993 | { 618, 3, 1, 4, 1014, 0, 0, MipsOpInfoBase + 423, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoDMULTu |
| 6994 | { 617, 3, 1, 4, 1013, 0, 0, MipsOpInfoBase + 423, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // PseudoDMULT |
| 6995 | { 616, 2, 1, 4, 661, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_S_W |
| 6996 | { 615, 2, 1, 4, 661, 0, 0, MipsOpInfoBase + 419, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_S_L |
| 6997 | { 614, 2, 1, 4, 661, 0, 0, MipsOpInfoBase + 421, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_D64_W |
| 6998 | { 613, 2, 1, 4, 661, 0, 0, MipsOpInfoBase + 419, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_D64_L |
| 6999 | { 612, 2, 1, 4, 661, 0, 0, MipsOpInfoBase + 417, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // PseudoCVT_D32_W |
| 7000 | { 611, 3, 1, 4, 1490, 0, 0, MipsOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMP_LT_PH |
| 7001 | { 610, 3, 1, 4, 1490, 0, 0, MipsOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMP_LE_PH |
| 7002 | { 609, 3, 1, 4, 1490, 0, 0, MipsOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMP_EQ_PH |
| 7003 | { 608, 3, 1, 4, 1490, 0, 0, MipsOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMPU_LT_QB |
| 7004 | { 607, 3, 1, 4, 1490, 0, 0, MipsOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMPU_LE_QB |
| 7005 | { 606, 3, 1, 4, 1490, 0, 0, MipsOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // PseudoCMPU_EQ_QB |
| 7006 | { 605, 3, 1, 4, 593, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // OR_V_W_PSEUDO |
| 7007 | { 604, 3, 1, 4, 593, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // OR_V_H_PSEUDO |
| 7008 | { 603, 3, 1, 4, 593, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // OR_V_D_PSEUDO |
| 7009 | { 602, 3, 1, 4, 592, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // NOR_V_W_PSEUDO |
| 7010 | { 601, 3, 1, 4, 592, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // NOR_V_H_PSEUDO |
| 7011 | { 600, 3, 1, 4, 592, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // NOR_V_D_PSEUDO |
| 7012 | { 599, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NORImm64 |
| 7013 | { 598, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NORImm |
| 7014 | { 597, 0, 0, 4, 679, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NOP |
| 7015 | { 596, 3, 1, 2, 986, 0, 2, MipsOpInfoBase + 411, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // MultuRxRyRz16 |
| 7016 | { 595, 2, 0, 2, 986, 0, 2, MipsOpInfoBase + 409, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // MultuRxRy16 |
| 7017 | { 594, 3, 1, 2, 986, 0, 2, MipsOpInfoBase + 411, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // MultRxRyRz16 |
| 7018 | { 593, 2, 0, 2, 986, 0, 2, MipsOpInfoBase + 409, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // MultRxRy16 |
| 7019 | { 592, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULOUMacro |
| 7020 | { 591, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULOMacro |
| 7021 | { 590, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULImmMacro |
| 7022 | { 589, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTLO |
| 7023 | { 588, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTHI |
| 7024 | { 587, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTHC1 |
| 7025 | { 586, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTGPR |
| 7026 | { 585, 1, 0, 4, 1, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTDSP |
| 7027 | { 584, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 407, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTC1 |
| 7028 | { 583, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 404, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTC0 |
| 7029 | { 582, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 402, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MTTACX |
| 7030 | { 581, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 400, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MSA_FP_ROUND_W_PSEUDO |
| 7031 | { 580, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 398, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MSA_FP_ROUND_D_PSEUDO |
| 7032 | { 579, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 396, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MSA_FP_EXTEND_W_PSEUDO |
| 7033 | { 578, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 394, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MSA_FP_EXTEND_D_PSEUDO |
| 7034 | { 577, 2, 0, 4, 1, 2, 0, MipsOpInfoBase + 392, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // MIPSeh_return64 |
| 7035 | { 576, 2, 0, 4, 1, 2, 0, MipsOpInfoBase + 155, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // MIPSeh_return32 |
| 7036 | { 575, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 385, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTLO |
| 7037 | { 574, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 385, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTHI |
| 7038 | { 573, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 390, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTHC1 |
| 7039 | { 572, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTGPR |
| 7040 | { 571, 1, 1, 4, 1, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTDSP |
| 7041 | { 570, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 390, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTC1 |
| 7042 | { 569, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 387, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTC0 |
| 7043 | { 568, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 385, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MFTACX |
| 7044 | { 567, 3, 1, 2, 896, 0, 0, MipsOpInfoBase + 382, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LwConstant32 |
| 7045 | { 566, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmSingleGPR |
| 7046 | { 565, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 380, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmSingleFGR |
| 7047 | { 564, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmDoubleGPR |
| 7048 | { 563, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 378, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmDoubleFGR_32 |
| 7049 | { 562, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 376, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImmDoubleFGR |
| 7050 | { 561, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 369, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImm64 |
| 7051 | { 560, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 374, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadImm32 |
| 7052 | { 559, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 371, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadAddrReg64 |
| 7053 | { 558, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadAddrReg32 |
| 7054 | { 557, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 369, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadAddrImm64 |
| 7055 | { 556, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 367, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LoadAddrImm32 |
| 7056 | { 555, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 364, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LWM_MM |
| 7057 | { 554, 2, 1, 4, 503, 0, 0, MipsOpInfoBase + 362, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_LUi2Op_64 |
| 7058 | { 553, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 360, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_LUi2Op |
| 7059 | { 552, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 357, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_LUi |
| 7060 | { 551, 3, 1, 4, 503, 0, 0, MipsOpInfoBase + 354, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_DADDiu2Op |
| 7061 | { 550, 4, 1, 4, 503, 0, 0, MipsOpInfoBase + 350, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_DADDiu |
| 7062 | { 549, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_ADDiu2Op |
| 7063 | { 548, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 346, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LONG_BRANCH_ADDiu |
| 7064 | { 547, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 343, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LOAD_CCOND_DSP |
| 7065 | { 546, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 340, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LOAD_ACC64DSP |
| 7066 | { 545, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 337, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LOAD_ACC64 |
| 7067 | { 544, 3, 1, 4, 0, 0, 0, MipsOpInfoBase + 334, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // LOAD_ACC128 |
| 7068 | { 543, 3, 1, 4, 392, 0, 0, MipsOpInfoBase + 331, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // LD_F16 |
| 7069 | { 542, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 328, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // LDR_W |
| 7070 | { 541, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 325, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // LDR_D |
| 7071 | { 540, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDMacro |
| 7072 | { 539, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JalTwoReg |
| 7073 | { 538, 1, 0, 4, 1, 0, 0, MipsOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JalOneReg |
| 7074 | { 537, 1, 0, 4, 1087, 0, 1, MipsOpInfoBase + 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL }, // JAL_MMR6 |
| 7075 | { 536, 1, 0, 4, 697, 0, 1, MipsOpInfoBase + 200, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // JALRPseudo |
| 7076 | { 535, 1, 0, 4, 697, 0, 1, MipsOpInfoBase + 200, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // JALRHBPseudo |
| 7077 | { 534, 1, 0, 4, 414, 0, 1, MipsOpInfoBase + 321, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // JALRHB64Pseudo |
| 7078 | { 533, 1, 0, 4, 414, 0, 1, MipsOpInfoBase + 321, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // JALR64Pseudo |
| 7079 | { 532, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 317, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_W_VIDX_PSEUDO |
| 7080 | { 531, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 313, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_W_VIDX64_PSEUDO |
| 7081 | { 530, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 309, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_H_VIDX_PSEUDO |
| 7082 | { 529, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 305, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_H_VIDX64_PSEUDO |
| 7083 | { 528, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 301, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FW_VIDX_PSEUDO |
| 7084 | { 527, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 297, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FW_VIDX64_PSEUDO |
| 7085 | { 526, 4, 1, 4, 604, 0, 0, MipsOpInfoBase + 293, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FW_PSEUDO |
| 7086 | { 525, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 289, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FD_VIDX_PSEUDO |
| 7087 | { 524, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 285, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FD_VIDX64_PSEUDO |
| 7088 | { 523, 4, 1, 4, 604, 0, 0, MipsOpInfoBase + 281, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_FD_PSEUDO |
| 7089 | { 522, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 277, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_D_VIDX_PSEUDO |
| 7090 | { 521, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 273, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_D_VIDX64_PSEUDO |
| 7091 | { 520, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 269, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_B_VIDX_PSEUDO |
| 7092 | { 519, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 265, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // INSERT_B_VIDX64_PSEUDO |
| 7093 | { 518, 4, 2, 2, 896, 0, 0, MipsOpInfoBase + 261, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // GotPrologue16 |
| 7094 | { 517, 2, 1, 4, 603, 0, 0, MipsOpInfoBase + 259, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FILL_FW_PSEUDO |
| 7095 | { 516, 2, 1, 4, 603, 0, 0, MipsOpInfoBase + 257, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FILL_FD_PSEUDO |
| 7096 | { 515, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FEXP2_W_1_PSEUDO |
| 7097 | { 514, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 253, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FEXP2_D_1_PSEUDO |
| 7098 | { 513, 2, 1, 4, 812, 0, 0, MipsOpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // FABS_W |
| 7099 | { 512, 2, 1, 4, 812, 0, 0, MipsOpInfoBase + 253, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // FABS_D |
| 7100 | { 511, 3, 1, 4, 495, 0, 0, MipsOpInfoBase + 250, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ExtractElementF64_64 |
| 7101 | { 510, 3, 1, 4, 495, 0, 0, MipsOpInfoBase + 247, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ExtractElementF64 |
| 7102 | { 509, 0, 0, 4, 1025, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // ERet |
| 7103 | { 508, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DURemMacro |
| 7104 | { 507, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DURemIMacro |
| 7105 | { 506, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DUDivMacro |
| 7106 | { 505, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DUDivIMacro |
| 7107 | { 504, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DSRemMacro |
| 7108 | { 503, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DSRemIMacro |
| 7109 | { 502, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DSDivMacro |
| 7110 | { 501, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DSDivIMacro |
| 7111 | { 500, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DRORImm |
| 7112 | { 499, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DROR |
| 7113 | { 498, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DROLImm |
| 7114 | { 497, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DROL |
| 7115 | { 496, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DMULOUMacro |
| 7116 | { 495, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DMULOMacro |
| 7117 | { 494, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 238, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DMULMacro |
| 7118 | { 493, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DMULImmMacro |
| 7119 | { 492, 1, 0, 2, 896, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Constant32 |
| 7120 | { 491, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 233, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CTTC1 |
| 7121 | { 490, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 230, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // COPY_FW_PSEUDO |
| 7122 | { 489, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 227, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // COPY_FD_PSEUDO |
| 7123 | { 488, 3, 0, 2, 896, 0, 0, MipsOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CONSTPOOL_ENTRY |
| 7124 | { 487, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 225, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CFTC1 |
| 7125 | { 486, 3, 1, 4, 501, 0, 0, MipsOpInfoBase + 222, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BuildPairF64_64 |
| 7126 | { 485, 3, 1, 4, 501, 0, 0, MipsOpInfoBase + 219, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BuildPairF64 |
| 7127 | { 484, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 213, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BtnezT8SltuX16 |
| 7128 | { 483, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 216, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BtnezT8SltiuX16 |
| 7129 | { 482, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 216, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BtnezT8SltiX16 |
| 7130 | { 481, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 213, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BtnezT8SltX16 |
| 7131 | { 480, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 216, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BtnezT8CmpiX16 |
| 7132 | { 479, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 213, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BtnezT8CmpX16 |
| 7133 | { 478, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 213, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BteqzT8SltuX16 |
| 7134 | { 477, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 216, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BteqzT8SltiuX16 |
| 7135 | { 476, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 216, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BteqzT8SltiX16 |
| 7136 | { 475, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 213, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BteqzT8SltX16 |
| 7137 | { 474, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 216, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BteqzT8CmpiX16 |
| 7138 | { 473, 3, 0, 2, 1037, 0, 0, MipsOpInfoBase + 213, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BteqzT8CmpX16 |
| 7139 | { 472, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BneImm |
| 7140 | { 471, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BeqImm |
| 7141 | { 470, 1, 0, 4, 1053, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // B_MM_Pseudo |
| 7142 | { 469, 1, 0, 4, 1094, 0, 0, MipsOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // B_MMR6_Pseudo |
| 7143 | { 468, 1, 0, 4, 1042, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // B_MM |
| 7144 | { 467, 4, 1, 4, 655, 0, 0, MipsOpInfoBase + 205, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_W_PSEUDO |
| 7145 | { 466, 4, 1, 4, 655, 0, 0, MipsOpInfoBase + 209, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_H_PSEUDO |
| 7146 | { 465, 4, 1, 4, 655, 0, 0, MipsOpInfoBase + 205, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_FW_PSEUDO |
| 7147 | { 464, 4, 1, 4, 655, 0, 0, MipsOpInfoBase + 201, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_FD_PSEUDO |
| 7148 | { 463, 4, 1, 4, 655, 0, 0, MipsOpInfoBase + 201, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // BSEL_D_PSEUDO |
| 7149 | { 462, 1, 1, 4, 1, 1, 0, MipsOpInfoBase + 200, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BPOSGE32_PSEUDO |
| 7150 | { 461, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BNELImmMacro |
| 7151 | { 460, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTULImmMacro |
| 7152 | { 459, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTUL |
| 7153 | { 458, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTUImmMacro |
| 7154 | { 457, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTU |
| 7155 | { 456, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTLImmMacro |
| 7156 | { 455, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTL |
| 7157 | { 454, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLTImmMacro |
| 7158 | { 453, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLT |
| 7159 | { 452, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEULImmMacro |
| 7160 | { 451, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEUL |
| 7161 | { 450, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEUImmMacro |
| 7162 | { 449, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEU |
| 7163 | { 448, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLELImmMacro |
| 7164 | { 447, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEL |
| 7165 | { 446, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLEImmMacro |
| 7166 | { 445, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BLE |
| 7167 | { 444, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTULImmMacro |
| 7168 | { 443, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTUL |
| 7169 | { 442, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTUImmMacro |
| 7170 | { 441, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTU |
| 7171 | { 440, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTLImmMacro |
| 7172 | { 439, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTL |
| 7173 | { 438, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGTImmMacro |
| 7174 | { 437, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGT |
| 7175 | { 436, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEULImmMacro |
| 7176 | { 435, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEUL |
| 7177 | { 434, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEUImmMacro |
| 7178 | { 433, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEU |
| 7179 | { 432, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGELImmMacro |
| 7180 | { 431, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEL |
| 7181 | { 430, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGEImmMacro |
| 7182 | { 429, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BGE |
| 7183 | { 428, 3, 0, 4, 1, 0, 0, MipsOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BEQLImmMacro |
| 7184 | { 427, 1, 0, 4, 1043, 0, 1, MipsOpInfoBase + 193, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BAL_BR_MM |
| 7185 | { 426, 1, 0, 4, 434, 0, 1, MipsOpInfoBase + 193, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // BAL_BR |
| 7186 | { 425, 1, 0, 4, 415, 0, 1, MipsOpInfoBase + 193, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // B |
| 7187 | { 424, 6, 1, 4, 670, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_SWAP_I8_POSTRA |
| 7188 | { 423, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_SWAP_I8 |
| 7189 | { 422, 3, 1, 4, 670, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_SWAP_I64_POSTRA |
| 7190 | { 421, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_SWAP_I64 |
| 7191 | { 420, 3, 1, 4, 670, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_SWAP_I32_POSTRA |
| 7192 | { 419, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_SWAP_I32 |
| 7193 | { 418, 6, 1, 4, 670, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_SWAP_I16_POSTRA |
| 7194 | { 417, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_SWAP_I16 |
| 7195 | { 416, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_XOR_I8_POSTRA |
| 7196 | { 415, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_XOR_I8 |
| 7197 | { 414, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_XOR_I64_POSTRA |
| 7198 | { 413, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_XOR_I64 |
| 7199 | { 412, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_XOR_I32_POSTRA |
| 7200 | { 411, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_XOR_I32 |
| 7201 | { 410, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_XOR_I16_POSTRA |
| 7202 | { 409, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_XOR_I16 |
| 7203 | { 408, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMIN_I8_POSTRA |
| 7204 | { 407, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMIN_I8 |
| 7205 | { 406, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMIN_I64_POSTRA |
| 7206 | { 405, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMIN_I64 |
| 7207 | { 404, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMIN_I32_POSTRA |
| 7208 | { 403, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMIN_I32 |
| 7209 | { 402, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMIN_I16_POSTRA |
| 7210 | { 401, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMIN_I16 |
| 7211 | { 400, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMAX_I8_POSTRA |
| 7212 | { 399, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMAX_I8 |
| 7213 | { 398, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMAX_I64_POSTRA |
| 7214 | { 397, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMAX_I64 |
| 7215 | { 396, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMAX_I32_POSTRA |
| 7216 | { 395, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMAX_I32 |
| 7217 | { 394, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_UMAX_I16_POSTRA |
| 7218 | { 393, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_UMAX_I16 |
| 7219 | { 392, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_SUB_I8_POSTRA |
| 7220 | { 391, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_SUB_I8 |
| 7221 | { 390, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_SUB_I64_POSTRA |
| 7222 | { 389, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_SUB_I64 |
| 7223 | { 388, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_SUB_I32_POSTRA |
| 7224 | { 387, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_SUB_I32 |
| 7225 | { 386, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_SUB_I16_POSTRA |
| 7226 | { 385, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_SUB_I16 |
| 7227 | { 384, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_OR_I8_POSTRA |
| 7228 | { 383, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_OR_I8 |
| 7229 | { 382, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_OR_I64_POSTRA |
| 7230 | { 381, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_OR_I64 |
| 7231 | { 380, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_OR_I32_POSTRA |
| 7232 | { 379, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_OR_I32 |
| 7233 | { 378, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_OR_I16_POSTRA |
| 7234 | { 377, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_OR_I16 |
| 7235 | { 376, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_NAND_I8_POSTRA |
| 7236 | { 375, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_NAND_I8 |
| 7237 | { 374, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_NAND_I64_POSTRA |
| 7238 | { 373, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_NAND_I64 |
| 7239 | { 372, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_NAND_I32_POSTRA |
| 7240 | { 371, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_NAND_I32 |
| 7241 | { 370, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_NAND_I16_POSTRA |
| 7242 | { 369, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_NAND_I16 |
| 7243 | { 368, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MIN_I8_POSTRA |
| 7244 | { 367, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MIN_I8 |
| 7245 | { 366, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MIN_I64_POSTRA |
| 7246 | { 365, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MIN_I64 |
| 7247 | { 364, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MIN_I32_POSTRA |
| 7248 | { 363, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MIN_I32 |
| 7249 | { 362, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MIN_I16_POSTRA |
| 7250 | { 361, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MIN_I16 |
| 7251 | { 360, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MAX_I8_POSTRA |
| 7252 | { 359, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MAX_I8 |
| 7253 | { 358, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MAX_I64_POSTRA |
| 7254 | { 357, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MAX_I64 |
| 7255 | { 356, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MAX_I32_POSTRA |
| 7256 | { 355, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MAX_I32 |
| 7257 | { 354, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_MAX_I16_POSTRA |
| 7258 | { 353, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_MAX_I16 |
| 7259 | { 352, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_AND_I8_POSTRA |
| 7260 | { 351, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_AND_I8 |
| 7261 | { 350, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_AND_I64_POSTRA |
| 7262 | { 349, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_AND_I64 |
| 7263 | { 348, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_AND_I32_POSTRA |
| 7264 | { 347, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_AND_I32 |
| 7265 | { 346, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_AND_I16_POSTRA |
| 7266 | { 345, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_AND_I16 |
| 7267 | { 344, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_ADD_I8_POSTRA |
| 7268 | { 343, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_ADD_I8 |
| 7269 | { 342, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_ADD_I64_POSTRA |
| 7270 | { 341, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_ADD_I64 |
| 7271 | { 340, 3, 1, 4, 672, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_ADD_I32_POSTRA |
| 7272 | { 339, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_ADD_I32 |
| 7273 | { 338, 6, 1, 4, 672, 0, 0, MipsOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_LOAD_ADD_I16_POSTRA |
| 7274 | { 337, 3, 1, 4, 1, 0, 0, MipsOpInfoBase + 181, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_LOAD_ADD_I16 |
| 7275 | { 336, 7, 1, 4, 671, 0, 0, MipsOpInfoBase + 170, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_CMP_SWAP_I8_POSTRA |
| 7276 | { 335, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 166, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_CMP_SWAP_I8 |
| 7277 | { 334, 4, 1, 4, 671, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_CMP_SWAP_I64_POSTRA |
| 7278 | { 333, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 177, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_CMP_SWAP_I64 |
| 7279 | { 332, 4, 1, 4, 671, 0, 0, MipsOpInfoBase + 166, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_CMP_SWAP_I32_POSTRA |
| 7280 | { 331, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 166, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_CMP_SWAP_I32 |
| 7281 | { 330, 7, 1, 4, 671, 0, 0, MipsOpInfoBase + 170, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ATOMIC_CMP_SWAP_I16_POSTRA |
| 7282 | { 329, 4, 1, 4, 1, 0, 0, MipsOpInfoBase + 166, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // ATOMIC_CMP_SWAP_I16 |
| 7283 | { 328, 3, 1, 4, 595, 0, 0, MipsOpInfoBase + 163, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // AND_V_W_PSEUDO |
| 7284 | { 327, 3, 1, 4, 595, 0, 0, MipsOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // AND_V_H_PSEUDO |
| 7285 | { 326, 3, 1, 4, 595, 0, 0, MipsOpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // AND_V_D_PSEUDO |
| 7286 | { 325, 2, 0, 4, 1, 1, 1, MipsOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADJCALLSTACKUP |
| 7287 | { 324, 2, 0, 4, 1, 1, 1, MipsOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADJCALLSTACKDOWN |
| 7288 | { 323, 2, 1, 4, 1, 0, 0, MipsOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ABSMacro |
| 7289 | { 322, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX |
| 7290 | { 321, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX |
| 7291 | { 320, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN |
| 7292 | { 319, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX |
| 7293 | { 318, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN |
| 7294 | { 317, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX |
| 7295 | { 316, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR |
| 7296 | { 315, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR |
| 7297 | { 314, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND |
| 7298 | { 313, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL |
| 7299 | { 312, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD |
| 7300 | { 311, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM |
| 7301 | { 310, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM |
| 7302 | { 309, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN |
| 7303 | { 308, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX |
| 7304 | { 307, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL |
| 7305 | { 306, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD |
| 7306 | { 305, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL |
| 7307 | { 304, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD |
| 7308 | { 303, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP |
| 7309 | { 302, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP |
| 7310 | { 301, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP |
| 7311 | { 300, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO |
| 7312 | { 299, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET |
| 7313 | { 298, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE |
| 7314 | { 297, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE |
| 7315 | { 296, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY |
| 7316 | { 295, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER |
| 7317 | { 294, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER |
| 7318 | { 293, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP |
| 7319 | { 292, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT |
| 7320 | { 291, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA |
| 7321 | { 290, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM |
| 7322 | { 289, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV |
| 7323 | { 288, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL |
| 7324 | { 287, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB |
| 7325 | { 286, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD |
| 7326 | { 285, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE |
| 7327 | { 284, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE |
| 7328 | { 283, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC |
| 7329 | { 282, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE |
| 7330 | { 281, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR |
| 7331 | { 280, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST |
| 7332 | { 279, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT |
| 7333 | { 278, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT |
| 7334 | { 277, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR |
| 7335 | { 276, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT |
| 7336 | { 275, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH |
| 7337 | { 274, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH |
| 7338 | { 273, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH |
| 7339 | { 272, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2 |
| 7340 | { 271, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN |
| 7341 | { 270, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN |
| 7342 | { 269, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS |
| 7343 | { 268, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN |
| 7344 | { 267, 3, 2, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS |
| 7345 | { 266, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN |
| 7346 | { 265, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS |
| 7347 | { 264, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL |
| 7348 | { 263, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE |
| 7349 | { 262, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP |
| 7350 | { 261, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP |
| 7351 | { 260, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS |
| 7352 | { 259, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_UNDEF |
| 7353 | { 258, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ |
| 7354 | { 257, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_UNDEF |
| 7355 | { 256, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ |
| 7356 | { 255, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS |
| 7357 | { 254, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR |
| 7358 | { 253, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR |
| 7359 | { 252, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR |
| 7360 | { 251, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT |
| 7361 | { 250, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT |
| 7362 | { 249, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR |
| 7363 | { 248, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR |
| 7364 | { 247, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE |
| 7365 | { 246, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT |
| 7366 | { 245, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR |
| 7367 | { 244, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND |
| 7368 | { 243, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND |
| 7369 | { 242, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS |
| 7370 | { 241, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX |
| 7371 | { 240, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN |
| 7372 | { 239, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX |
| 7373 | { 238, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN |
| 7374 | { 237, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK |
| 7375 | { 236, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD |
| 7376 | { 235, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING |
| 7377 | { 234, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING |
| 7378 | { 233, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE |
| 7379 | { 232, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE |
| 7380 | { 231, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE |
| 7381 | { 230, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV |
| 7382 | { 229, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV |
| 7383 | { 228, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV |
| 7384 | { 227, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM |
| 7385 | { 226, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM |
| 7386 | { 225, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM |
| 7387 | { 224, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM |
| 7388 | { 223, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE |
| 7389 | { 222, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE |
| 7390 | { 221, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM |
| 7391 | { 220, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM |
| 7392 | { 219, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE |
| 7393 | { 218, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS |
| 7394 | { 217, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN |
| 7395 | { 216, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS |
| 7396 | { 215, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT |
| 7397 | { 214, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT |
| 7398 | { 213, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP |
| 7399 | { 212, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP |
| 7400 | { 211, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI |
| 7401 | { 210, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI |
| 7402 | { 209, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC |
| 7403 | { 208, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT |
| 7404 | { 207, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG |
| 7405 | { 206, 3, 2, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP |
| 7406 | { 205, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP |
| 7407 | { 204, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10 |
| 7408 | { 203, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2 |
| 7409 | { 202, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG |
| 7410 | { 201, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10 |
| 7411 | { 200, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2 |
| 7412 | { 199, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP |
| 7413 | { 198, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI |
| 7414 | { 197, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW |
| 7415 | { 196, 3, 2, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF |
| 7416 | { 195, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM |
| 7417 | { 194, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV |
| 7418 | { 193, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD |
| 7419 | { 192, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA |
| 7420 | { 191, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL |
| 7421 | { 190, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB |
| 7422 | { 189, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD |
| 7423 | { 188, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT |
| 7424 | { 187, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT |
| 7425 | { 186, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX |
| 7426 | { 185, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX |
| 7427 | { 184, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT |
| 7428 | { 183, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT |
| 7429 | { 182, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX |
| 7430 | { 181, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX |
| 7431 | { 180, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT |
| 7432 | { 179, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT |
| 7433 | { 178, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT |
| 7434 | { 177, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT |
| 7435 | { 176, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT |
| 7436 | { 175, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT |
| 7437 | { 174, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH |
| 7438 | { 173, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH |
| 7439 | { 172, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO |
| 7440 | { 171, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO |
| 7441 | { 170, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE |
| 7442 | { 169, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO |
| 7443 | { 168, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE |
| 7444 | { 167, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO |
| 7445 | { 166, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE |
| 7446 | { 165, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO |
| 7447 | { 164, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE |
| 7448 | { 163, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO |
| 7449 | { 162, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT |
| 7450 | { 161, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP |
| 7451 | { 160, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP |
| 7452 | { 159, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP |
| 7453 | { 158, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP |
| 7454 | { 157, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL |
| 7455 | { 156, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR |
| 7456 | { 155, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR |
| 7457 | { 154, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL |
| 7458 | { 153, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR |
| 7459 | { 152, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR |
| 7460 | { 151, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL |
| 7461 | { 150, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT |
| 7462 | { 149, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG |
| 7463 | { 148, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT |
| 7464 | { 147, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG |
| 7465 | { 146, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART |
| 7466 | { 145, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT |
| 7467 | { 144, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT |
| 7468 | { 143, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U |
| 7469 | { 142, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U |
| 7470 | { 141, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S |
| 7471 | { 140, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC |
| 7472 | { 139, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT |
| 7473 | { 138, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 7474 | { 137, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT |
| 7475 | { 136, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS |
| 7476 | { 135, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC |
| 7477 | { 134, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START |
| 7478 | { 133, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT |
| 7479 | { 132, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND |
| 7480 | { 131, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH |
| 7481 | { 130, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE |
| 7482 | { 129, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT |
| 7483 | { 128, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND |
| 7484 | { 127, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP |
| 7485 | { 126, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP |
| 7486 | { 125, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM |
| 7487 | { 124, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM |
| 7488 | { 123, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN |
| 7489 | { 122, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX |
| 7490 | { 121, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB |
| 7491 | { 120, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD |
| 7492 | { 119, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN |
| 7493 | { 118, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX |
| 7494 | { 117, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN |
| 7495 | { 116, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX |
| 7496 | { 115, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR |
| 7497 | { 114, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR |
| 7498 | { 113, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND |
| 7499 | { 112, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND |
| 7500 | { 111, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB |
| 7501 | { 110, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD |
| 7502 | { 109, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG |
| 7503 | { 108, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG |
| 7504 | { 107, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 7505 | { 106, 5, 1, 0, 0, 0, 0, MipsOpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE |
| 7506 | { 105, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE |
| 7507 | { 104, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD |
| 7508 | { 103, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD |
| 7509 | { 102, 5, 2, 0, 0, 0, 0, MipsOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD |
| 7510 | { 101, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD |
| 7511 | { 100, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD |
| 7512 | { 99, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD |
| 7513 | { 98, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER |
| 7514 | { 97, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER |
| 7515 | { 96, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN |
| 7516 | { 95, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT |
| 7517 | { 94, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT |
| 7518 | { 93, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND |
| 7519 | { 92, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC |
| 7520 | { 91, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND |
| 7521 | { 90, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER |
| 7522 | { 89, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE |
| 7523 | { 88, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST |
| 7524 | { 87, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR |
| 7525 | { 86, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT |
| 7526 | { 85, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS |
| 7527 | { 84, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC |
| 7528 | { 83, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR |
| 7529 | { 82, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES |
| 7530 | { 81, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT |
| 7531 | { 80, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES |
| 7532 | { 79, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT |
| 7533 | { 78, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL |
| 7534 | { 77, 5, 1, 0, 0, 0, 0, MipsOpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE |
| 7535 | { 76, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE |
| 7536 | { 75, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX |
| 7537 | { 74, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI |
| 7538 | { 73, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF |
| 7539 | { 72, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL |
| 7540 | { 71, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR |
| 7541 | { 70, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL |
| 7542 | { 69, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR |
| 7543 | { 68, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU |
| 7544 | { 67, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS |
| 7545 | { 66, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR |
| 7546 | { 65, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR |
| 7547 | { 64, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND |
| 7548 | { 63, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM |
| 7549 | { 62, 4, 2, 0, 0, 0, 0, MipsOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM |
| 7550 | { 61, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM |
| 7551 | { 60, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM |
| 7552 | { 59, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV |
| 7553 | { 58, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV |
| 7554 | { 57, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL |
| 7555 | { 56, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB |
| 7556 | { 55, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD |
| 7557 | { 54, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN |
| 7558 | { 53, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT |
| 7559 | { 52, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT |
| 7560 | { 51, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE |
| 7561 | { 50, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP |
| 7562 | { 49, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR |
| 7563 | { 48, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY |
| 7564 | { 47, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE |
| 7565 | { 46, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO |
| 7566 | { 45, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER |
| 7567 | { 44, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE |
| 7568 | { 43, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL |
| 7569 | { 42, 3, 0, 0, 0, 0, 0, MipsOpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17524 |
| 7570 | { 41, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17523 |
| 7571 | { 40, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL |
| 7572 | { 39, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT |
| 7573 | { 38, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET |
| 7574 | { 37, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER |
| 7575 | { 36, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP |
| 7576 | { 35, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP |
| 7577 | { 34, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE |
| 7578 | { 33, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT |
| 7579 | { 32, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17522 |
| 7580 | { 31, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP |
| 7581 | { 30, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_14301 |
| 7582 | { 29, 6, 1, 0, 0, 0, 0, MipsOpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT |
| 7583 | { 28, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL |
| 7584 | { 27, 2, 0, 0, 0, 0, 0, MipsOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP |
| 7585 | { 26, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE |
| 7586 | { 25, 4, 0, 0, 0, 0, 0, MipsOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE |
| 7587 | { 24, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END |
| 7588 | { 23, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START |
| 7589 | { 22, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE |
| 7590 | { 21, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK |
| 7591 | { 20, 2, 1, 0, 529, 0, 0, MipsOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY |
| 7592 | { 19, 2, 1, 0, 0, 0, 0, MipsOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE |
| 7593 | { 18, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL |
| 7594 | { 17, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI |
| 7595 | { 16, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF |
| 7596 | { 15, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST |
| 7597 | { 14, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE |
| 7598 | { 13, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS |
| 7599 | { 12, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG |
| 7600 | { 11, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF |
| 7601 | { 10, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF |
| 7602 | { 9, 4, 1, 0, 0, 0, 0, MipsOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG |
| 7603 | { 8, 3, 1, 0, 0, 0, 0, MipsOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG |
| 7604 | { 7, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL |
| 7605 | { 6, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL |
| 7606 | { 5, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL |
| 7607 | { 4, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL |
| 7608 | { 3, 1, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION |
| 7609 | { 2, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR |
| 7610 | { 1, 0, 0, 0, 0, 0, 0, MipsOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM |
| 7611 | { 0, 1, 1, 0, 0, 0, 0, MipsOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI |
| 7612 | }, { |
| 7613 | /* 0 */ |
| 7614 | /* 0 */ Mips::SP, Mips::SP, |
| 7615 | /* 2 */ Mips::AT, |
| 7616 | /* 3 */ Mips::RA, |
| 7617 | /* 4 */ Mips::DSPPos, |
| 7618 | /* 5 */ Mips::V0, Mips::V1, |
| 7619 | /* 7 */ Mips::HI0, Mips::LO0, |
| 7620 | /* 9 */ Mips::T8, |
| 7621 | /* 10 */ Mips::DSPOutFlag20, |
| 7622 | /* 11 */ Mips::FCR31, |
| 7623 | /* 12 */ Mips::DSPCarry, |
| 7624 | /* 13 */ Mips::DSPCarry, Mips::DSPOutFlag20, |
| 7625 | /* 15 */ Mips::DSPCCond, |
| 7626 | /* 16 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, |
| 7627 | /* 21 */ Mips::HI0_64, Mips::LO0_64, |
| 7628 | /* 23 */ Mips::DSPOutFlag16_19, |
| 7629 | /* 24 */ Mips::DSPPos, Mips::DSPEFI, |
| 7630 | /* 26 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI, |
| 7631 | /* 29 */ Mips::DSPOutFlag23, |
| 7632 | /* 30 */ Mips::FCC0, |
| 7633 | /* 31 */ Mips::DSPPos, Mips::DSPSCount, |
| 7634 | /* 33 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0, |
| 7635 | /* 37 */ Mips::AC0, |
| 7636 | /* 38 */ Mips::AC0_64, |
| 7637 | /* 39 */ Mips::HI0, |
| 7638 | /* 40 */ Mips::HI0_64, |
| 7639 | /* 41 */ Mips::LO0, |
| 7640 | /* 42 */ Mips::LO0_64, |
| 7641 | /* 43 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, |
| 7642 | /* 47 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, |
| 7643 | /* 51 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, |
| 7644 | /* 55 */ Mips::P0, |
| 7645 | /* 56 */ Mips::P1, |
| 7646 | /* 57 */ Mips::P2, |
| 7647 | /* 58 */ Mips::DSPOutFlag21, |
| 7648 | /* 59 */ Mips::DSPOutFlag22, |
| 7649 | /* 60 */ Mips::P0, Mips::P1, Mips::P2, |
| 7650 | /* 63 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, |
| 7651 | }, { |
| 7652 | 0 |
| 7653 | }, { |
| 7654 | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7655 | /* 1 */ |
| 7656 | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7657 | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7658 | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7659 | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7660 | /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7661 | /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7662 | /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7663 | /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
| 7664 | /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7665 | /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7666 | /* 32 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, |
| 7667 | /* 33 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7668 | /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7669 | /* 38 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7670 | /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7671 | /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 7672 | /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7673 | /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7674 | /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7675 | /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7676 | /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7677 | /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 7678 | /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 7679 | /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 7680 | /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7681 | /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7682 | /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7683 | /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7684 | /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7685 | /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7686 | /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7687 | /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7688 | /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7689 | /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 7690 | /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 7691 | /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 7692 | /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 7693 | /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 7694 | /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 7695 | /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 7696 | /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 7697 | /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 7698 | /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7699 | /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7700 | /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 7701 | /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 7702 | /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 7703 | /* 155 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7704 | /* 157 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7705 | /* 160 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7706 | /* 163 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7707 | /* 166 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7708 | /* 170 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7709 | /* 177 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7710 | /* 181 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7711 | /* 184 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7712 | /* 190 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7713 | /* 193 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7714 | /* 194 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7715 | /* 197 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7716 | /* 200 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7717 | /* 201 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7718 | /* 205 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7719 | /* 209 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7720 | /* 213 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7721 | /* 216 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7722 | /* 219 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7723 | /* 222 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7724 | /* 225 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32CCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7725 | /* 227 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7726 | /* 230 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7727 | /* 233 */ { Mips::FGR32CCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7728 | /* 235 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7729 | /* 238 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7730 | /* 241 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7731 | /* 244 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7732 | /* 247 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7733 | /* 250 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7734 | /* 253 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7735 | /* 255 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7736 | /* 257 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7737 | /* 259 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7738 | /* 261 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7739 | /* 265 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7740 | /* 269 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7741 | /* 273 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7742 | /* 277 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7743 | /* 281 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7744 | /* 285 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7745 | /* 289 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7746 | /* 293 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7747 | /* 297 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7748 | /* 301 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7749 | /* 305 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7750 | /* 309 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7751 | /* 313 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7752 | /* 317 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7753 | /* 321 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7754 | /* 322 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7755 | /* 325 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7756 | /* 328 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7757 | /* 331 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7758 | /* 334 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7759 | /* 337 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7760 | /* 340 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7761 | /* 343 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7762 | /* 346 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7763 | /* 350 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7764 | /* 354 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7765 | /* 357 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7766 | /* 360 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7767 | /* 362 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7768 | /* 364 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7769 | /* 367 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 7770 | /* 369 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7771 | /* 371 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7772 | /* 374 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7773 | /* 376 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7774 | /* 378 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7775 | /* 380 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7776 | /* 382 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7777 | /* 385 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7778 | /* 387 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7779 | /* 390 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7780 | /* 392 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7781 | /* 394 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7782 | /* 396 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7783 | /* 398 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7784 | /* 400 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7785 | /* 402 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7786 | /* 404 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7787 | /* 407 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7788 | /* 409 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7789 | /* 411 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7790 | /* 414 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7791 | /* 417 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7792 | /* 419 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7793 | /* 421 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7794 | /* 423 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7795 | /* 426 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7796 | /* 433 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7797 | /* 440 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7798 | /* 444 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7799 | /* 446 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7800 | /* 448 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7801 | /* 451 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7802 | /* 454 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7803 | /* 458 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7804 | /* 462 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7805 | /* 466 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7806 | /* 470 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7807 | /* 474 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7808 | /* 478 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7809 | /* 482 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7810 | /* 486 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7811 | /* 490 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7812 | /* 494 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7813 | /* 498 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7814 | /* 501 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7815 | /* 504 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7816 | /* 507 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7817 | /* 510 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7818 | /* 513 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7819 | /* 515 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7820 | /* 517 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7821 | /* 519 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7822 | /* 521 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7823 | /* 525 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7824 | /* 530 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7825 | /* 535 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7826 | /* 538 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7827 | /* 540 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7828 | /* 542 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7829 | /* 545 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7830 | /* 548 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7831 | /* 551 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7832 | /* 554 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7833 | /* 557 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7834 | /* 560 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7835 | /* 563 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7836 | /* 566 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7837 | /* 569 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7838 | /* 572 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7839 | /* 576 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7840 | /* 579 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7841 | /* 583 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7842 | /* 585 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7843 | /* 588 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7844 | /* 591 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7845 | /* 594 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7846 | /* 597 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7847 | /* 599 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7848 | /* 601 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7849 | /* 603 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7850 | /* 605 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7851 | /* 609 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7852 | /* 613 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7853 | /* 617 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7854 | /* 621 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7855 | /* 625 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7856 | /* 627 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7857 | /* 629 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7858 | /* 631 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7859 | /* 633 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 7860 | /* 635 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7861 | /* 638 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7862 | /* 640 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7863 | /* 642 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7864 | /* 644 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7865 | /* 646 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7866 | /* 648 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7867 | /* 650 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7868 | /* 652 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7869 | /* 654 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7870 | /* 658 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7871 | /* 662 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7872 | /* 666 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7873 | /* 669 */ { Mips::FGR64CCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7874 | /* 672 */ { Mips::FGR32CCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7875 | /* 675 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7876 | /* 678 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7877 | /* 681 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7878 | /* 684 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7879 | /* 687 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7880 | /* 689 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7881 | /* 691 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7882 | /* 693 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7883 | /* 695 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7884 | /* 698 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7885 | /* 701 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7886 | /* 704 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7887 | /* 707 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7888 | /* 710 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7889 | /* 714 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7890 | /* 719 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7891 | /* 722 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7892 | /* 724 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7893 | /* 727 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7894 | /* 730 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7895 | /* 733 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7896 | /* 736 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7897 | /* 739 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7898 | /* 742 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7899 | /* 746 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7900 | /* 750 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7901 | /* 754 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7902 | /* 758 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7903 | /* 761 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7904 | /* 763 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7905 | /* 766 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7906 | /* 769 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7907 | /* 771 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7908 | /* 774 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7909 | /* 777 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7910 | /* 780 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7911 | /* 783 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7912 | /* 786 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7913 | /* 789 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7914 | /* 792 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7915 | /* 794 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7916 | /* 796 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7917 | /* 798 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7918 | /* 800 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7919 | /* 802 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7920 | /* 804 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7921 | /* 809 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7922 | /* 813 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7923 | /* 817 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7924 | /* 821 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7925 | /* 825 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7926 | /* 828 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7927 | /* 833 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7928 | /* 838 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7929 | /* 843 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7930 | /* 848 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7931 | /* 849 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ptr_gpr16mm_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7932 | /* 852 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, |
| 7933 | /* 855 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7934 | /* 858 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7935 | /* 861 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7936 | /* 864 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7937 | /* 867 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7938 | /* 869 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7939 | /* 871 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7940 | /* 873 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7941 | /* 875 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7942 | /* 879 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, |
| 7943 | /* 882 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, |
| 7944 | /* 885 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7945 | /* 888 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7946 | /* 891 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7947 | /* 894 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7948 | /* 897 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
| 7949 | /* 900 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
| 7950 | /* 903 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7951 | /* 906 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7952 | /* 909 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ptr_gp_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7953 | /* 912 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7954 | /* 916 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ptr_sp_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7955 | /* 919 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7956 | /* 923 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ptr_sp_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 7957 | /* 926 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, |
| 7958 | /* 929 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7959 | /* 932 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7960 | /* 936 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7961 | /* 940 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7962 | /* 944 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7963 | /* 948 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7964 | /* 952 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7965 | /* 956 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7966 | /* 958 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7967 | /* 961 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7968 | /* 963 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7969 | /* 968 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7970 | /* 972 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7971 | /* 974 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7972 | /* 978 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7973 | /* 982 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7974 | /* 986 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7975 | /* 990 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7976 | /* 994 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7977 | /* 998 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7978 | /* 1002 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7979 | /* 1006 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7980 | /* 1010 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7981 | /* 1014 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7982 | /* 1018 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7983 | /* 1022 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7984 | /* 1026 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7985 | /* 1030 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7986 | /* 1033 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7987 | /* 1036 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7988 | /* 1039 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7989 | /* 1041 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7990 | /* 1044 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7991 | /* 1046 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7992 | /* 1048 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7993 | /* 1050 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7994 | /* 1052 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7995 | /* 1054 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7996 | /* 1056 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 7997 | /* 1059 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 7998 | /* 1063 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 7999 | /* 1066 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 8000 | /* 1069 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 8001 | /* 1072 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8002 | /* 1074 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 8003 | /* 1076 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ptr_gpr16mm_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 8004 | /* 1079 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 8005 | /* 1083 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
| 8006 | /* 1087 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 8007 | /* 1091 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
| 8008 | /* 1095 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64CCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8009 | /* 1099 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32CCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8010 | /* 1103 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 8011 | /* 1106 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8012 | /* 1109 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 8013 | /* 1112 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8014 | /* 1116 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8015 | /* 1120 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8016 | /* 1124 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8017 | /* 1128 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8018 | /* 1131 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 8019 | /* 1134 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8020 | /* 1137 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8021 | /* 1140 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8022 | /* 1143 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 8023 | /* 1146 */ { Mips::mips_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 8024 | /* 1148 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
| 8025 | } |
| 8026 | }; |
| 8027 | |
| 8028 | |
| 8029 | #ifdef __GNUC__ |
| 8030 | #pragma GCC diagnostic push |
| 8031 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 8032 | #endif |
| 8033 | extern const char MipsInstrNameData[] = { |
| 8034 | /* 0 */ "G_FLOG10\000" |
| 8035 | /* 9 */ "G_FEXP10\000" |
| 8036 | /* 18 */ "DMFC0\000" |
| 8037 | /* 24 */ "DMFGC0\000" |
| 8038 | /* 31 */ "MFHGC0\000" |
| 8039 | /* 38 */ "MTHGC0\000" |
| 8040 | /* 45 */ "DMTGC0\000" |
| 8041 | /* 52 */ "MFTC0\000" |
| 8042 | /* 58 */ "DMTC0\000" |
| 8043 | /* 64 */ "MTTC0\000" |
| 8044 | /* 70 */ "VMM0\000" |
| 8045 | /* 75 */ "MTM0\000" |
| 8046 | /* 80 */ "MTP0\000" |
| 8047 | /* 85 */ "BBIT0\000" |
| 8048 | /* 91 */ "LDC1\000" |
| 8049 | /* 96 */ "SDC1\000" |
| 8050 | /* 101 */ "CFC1\000" |
| 8051 | /* 106 */ "DMFC1\000" |
| 8052 | /* 112 */ "MFTHC1\000" |
| 8053 | /* 119 */ "MTTHC1\000" |
| 8054 | /* 126 */ "CTC1\000" |
| 8055 | /* 131 */ "CFTC1\000" |
| 8056 | /* 137 */ "MFTC1\000" |
| 8057 | /* 143 */ "DMTC1\000" |
| 8058 | /* 149 */ "CTTC1\000" |
| 8059 | /* 155 */ "MTTC1\000" |
| 8060 | /* 161 */ "LWC1\000" |
| 8061 | /* 166 */ "SWC1\000" |
| 8062 | /* 171 */ "LDXC1\000" |
| 8063 | /* 177 */ "SDXC1\000" |
| 8064 | /* 183 */ "LUXC1\000" |
| 8065 | /* 189 */ "SUXC1\000" |
| 8066 | /* 195 */ "LWXC1\000" |
| 8067 | /* 201 */ "SWXC1\000" |
| 8068 | /* 207 */ "MTM1\000" |
| 8069 | /* 212 */ "SDC1_M1\000" |
| 8070 | /* 220 */ "MTP1\000" |
| 8071 | /* 225 */ "BBIT1\000" |
| 8072 | /* 231 */ "BBIT032\000" |
| 8073 | /* 239 */ "BBIT132\000" |
| 8074 | /* 247 */ "DSRA32\000" |
| 8075 | /* 254 */ "MFHC1_D32\000" |
| 8076 | /* 264 */ "MTHC1_D32\000" |
| 8077 | /* 274 */ "FSUB_D32\000" |
| 8078 | /* 283 */ "NMSUB_D32\000" |
| 8079 | /* 293 */ "FADD_D32\000" |
| 8080 | /* 302 */ "NMADD_D32\000" |
| 8081 | /* 312 */ "C_NGE_D32\000" |
| 8082 | /* 322 */ "C_NGLE_D32\000" |
| 8083 | /* 333 */ "C_OLE_D32\000" |
| 8084 | /* 343 */ "C_ULE_D32\000" |
| 8085 | /* 353 */ "C_LE_D32\000" |
| 8086 | /* 362 */ "C_SF_D32\000" |
| 8087 | /* 371 */ "MOVF_D32\000" |
| 8088 | /* 380 */ "C_F_D32\000" |
| 8089 | /* 388 */ "PseudoSELECTFP_F_D32\000" |
| 8090 | /* 409 */ "FNEG_D32\000" |
| 8091 | /* 418 */ "MOVN_I_D32\000" |
| 8092 | /* 429 */ "MOVZ_I_D32\000" |
| 8093 | /* 440 */ "C_NGL_D32\000" |
| 8094 | /* 450 */ "FMUL_D32\000" |
| 8095 | /* 459 */ "LDC1_MM_D32\000" |
| 8096 | /* 471 */ "SDC1_MM_D32\000" |
| 8097 | /* 483 */ "C_UN_D32\000" |
| 8098 | /* 492 */ "RECIP_D32\000" |
| 8099 | /* 502 */ "FCMP_D32\000" |
| 8100 | /* 511 */ "C_SEQ_D32\000" |
| 8101 | /* 521 */ "C_UEQ_D32\000" |
| 8102 | /* 531 */ "C_EQ_D32\000" |
| 8103 | /* 540 */ "FABS_D32\000" |
| 8104 | /* 549 */ "CVT_S_D32\000" |
| 8105 | /* 559 */ "PseudoSELECT_D32\000" |
| 8106 | /* 576 */ "C_NGT_D32\000" |
| 8107 | /* 586 */ "C_OLT_D32\000" |
| 8108 | /* 596 */ "C_ULT_D32\000" |
| 8109 | /* 606 */ "C_LT_D32\000" |
| 8110 | /* 615 */ "FSQRT_D32\000" |
| 8111 | /* 625 */ "RSQRT_D32\000" |
| 8112 | /* 635 */ "MOVT_D32\000" |
| 8113 | /* 644 */ "PseudoSELECTFP_T_D32\000" |
| 8114 | /* 665 */ "FDIV_D32\000" |
| 8115 | /* 674 */ "FMOV_D32\000" |
| 8116 | /* 683 */ "PseudoTRUNC_W_D32\000" |
| 8117 | /* 701 */ "ROUND_W_D32\000" |
| 8118 | /* 713 */ "CEIL_W_D32\000" |
| 8119 | /* 724 */ "FLOOR_W_D32\000" |
| 8120 | /* 736 */ "CVT_W_D32\000" |
| 8121 | /* 746 */ "BPOSGE32\000" |
| 8122 | /* 755 */ "ATOMIC_LOAD_SUB_I32\000" |
| 8123 | /* 775 */ "ATOMIC_LOAD_ADD_I32\000" |
| 8124 | /* 795 */ "ATOMIC_LOAD_NAND_I32\000" |
| 8125 | /* 816 */ "ATOMIC_LOAD_AND_I32\000" |
| 8126 | /* 836 */ "ATOMIC_LOAD_UMIN_I32\000" |
| 8127 | /* 857 */ "ATOMIC_LOAD_MIN_I32\000" |
| 8128 | /* 877 */ "ATOMIC_SWAP_I32\000" |
| 8129 | /* 893 */ "ATOMIC_CMP_SWAP_I32\000" |
| 8130 | /* 913 */ "ATOMIC_LOAD_XOR_I32\000" |
| 8131 | /* 933 */ "ATOMIC_LOAD_OR_I32\000" |
| 8132 | /* 952 */ "ATOMIC_LOAD_UMAX_I32\000" |
| 8133 | /* 973 */ "ATOMIC_LOAD_MAX_I32\000" |
| 8134 | /* 993 */ "DSLL32\000" |
| 8135 | /* 1000 */ "DSRL32\000" |
| 8136 | /* 1007 */ "DROTR32\000" |
| 8137 | /* 1015 */ "CINS32\000" |
| 8138 | /* 1022 */ "EXTS32\000" |
| 8139 | /* 1029 */ "FCMP_S32\000" |
| 8140 | /* 1038 */ "DSLL64_32\000" |
| 8141 | /* 1048 */ "CINS64_32\000" |
| 8142 | /* 1058 */ "DEXT64_32\000" |
| 8143 | /* 1068 */ "LoadImmDoubleFGR_32\000" |
| 8144 | /* 1088 */ "LoadAddrReg32\000" |
| 8145 | /* 1102 */ "CINS_i32\000" |
| 8146 | /* 1111 */ "LoadImm32\000" |
| 8147 | /* 1121 */ "LoadAddrImm32\000" |
| 8148 | /* 1135 */ "MIPSeh_return32\000" |
| 8149 | /* 1151 */ "LwConstant32\000" |
| 8150 | /* 1164 */ "LDC2\000" |
| 8151 | /* 1169 */ "SDC2\000" |
| 8152 | /* 1174 */ "DMFC2\000" |
| 8153 | /* 1180 */ "DMTC2\000" |
| 8154 | /* 1186 */ "LWC2\000" |
| 8155 | /* 1191 */ "SWC2\000" |
| 8156 | /* 1196 */ "G_FLOG2\000" |
| 8157 | /* 1204 */ "MTM2\000" |
| 8158 | /* 1209 */ "G_FATAN2\000" |
| 8159 | /* 1218 */ "MTP2\000" |
| 8160 | /* 1223 */ "G_FEXP2\000" |
| 8161 | /* 1231 */ "SHRA_QB_MMR2\000" |
| 8162 | /* 1244 */ "CMPGDU_LE_QB_MMR2\000" |
| 8163 | /* 1262 */ "SUBUH_QB_MMR2\000" |
| 8164 | /* 1276 */ "ADDUH_QB_MMR2\000" |
| 8165 | /* 1290 */ "CMPGDU_EQ_QB_MMR2\000" |
| 8166 | /* 1308 */ "SHRA_R_QB_MMR2\000" |
| 8167 | /* 1323 */ "SUBUH_R_QB_MMR2\000" |
| 8168 | /* 1339 */ "ADDUH_R_QB_MMR2\000" |
| 8169 | /* 1355 */ "SHRAV_R_QB_MMR2\000" |
| 8170 | /* 1371 */ "ABSQ_S_QB_MMR2\000" |
| 8171 | /* 1386 */ "CMPGDU_LT_QB_MMR2\000" |
| 8172 | /* 1404 */ "SHRAV_QB_MMR2\000" |
| 8173 | /* 1418 */ "PREPEND_MMR2\000" |
| 8174 | /* 1431 */ "APPEND_MMR2\000" |
| 8175 | /* 1443 */ "PRECR_QB_PH_MMR2\000" |
| 8176 | /* 1460 */ "SUBQH_PH_MMR2\000" |
| 8177 | /* 1474 */ "ADDQH_PH_MMR2\000" |
| 8178 | /* 1488 */ "SHRL_PH_MMR2\000" |
| 8179 | /* 1501 */ "MUL_PH_MMR2\000" |
| 8180 | /* 1513 */ "SUBQH_R_PH_MMR2\000" |
| 8181 | /* 1529 */ "ADDQH_R_PH_MMR2\000" |
| 8182 | /* 1545 */ "MUL_S_PH_MMR2\000" |
| 8183 | /* 1559 */ "MULQ_S_PH_MMR2\000" |
| 8184 | /* 1574 */ "SUBU_S_PH_MMR2\000" |
| 8185 | /* 1589 */ "ADDU_S_PH_MMR2\000" |
| 8186 | /* 1604 */ "SUBU_PH_MMR2\000" |
| 8187 | /* 1617 */ "ADDU_PH_MMR2\000" |
| 8188 | /* 1630 */ "SHRLV_PH_MMR2\000" |
| 8189 | /* 1644 */ "DPA_W_PH_MMR2\000" |
| 8190 | /* 1658 */ "MULSA_W_PH_MMR2\000" |
| 8191 | /* 1674 */ "DPAQX_SA_W_PH_MMR2\000" |
| 8192 | /* 1693 */ "DPSQX_SA_W_PH_MMR2\000" |
| 8193 | /* 1712 */ "DPS_W_PH_MMR2\000" |
| 8194 | /* 1726 */ "DPAQX_S_W_PH_MMR2\000" |
| 8195 | /* 1744 */ "DPSQX_S_W_PH_MMR2\000" |
| 8196 | /* 1762 */ "DPAX_W_PH_MMR2\000" |
| 8197 | /* 1777 */ "DPSX_W_PH_MMR2\000" |
| 8198 | /* 1792 */ "BALIGN_MMR2\000" |
| 8199 | /* 1804 */ "PRECR_SRA_PH_W_MMR2\000" |
| 8200 | /* 1824 */ "PRECR_SRA_R_PH_W_MMR2\000" |
| 8201 | /* 1846 */ "SUBQH_W_MMR2\000" |
| 8202 | /* 1859 */ "ADDQH_W_MMR2\000" |
| 8203 | /* 1872 */ "SUBQH_R_W_MMR2\000" |
| 8204 | /* 1887 */ "ADDQH_R_W_MMR2\000" |
| 8205 | /* 1902 */ "MULQ_RS_W_MMR2\000" |
| 8206 | /* 1917 */ "MULQ_S_W_MMR2\000" |
| 8207 | /* 1931 */ "LDC3\000" |
| 8208 | /* 1936 */ "SDC3\000" |
| 8209 | /* 1941 */ "LWC3\000" |
| 8210 | /* 1946 */ "SWC3\000" |
| 8211 | /* 1951 */ "BPOSGE32C_MMR3\000" |
| 8212 | /* 1966 */ "LDC164\000" |
| 8213 | /* 1973 */ "SDC164\000" |
| 8214 | /* 1980 */ "LDXC164\000" |
| 8215 | /* 1988 */ "SDXC164\000" |
| 8216 | /* 1996 */ "LUXC164\000" |
| 8217 | /* 2004 */ "SUXC164\000" |
| 8218 | /* 2012 */ "SEB64\000" |
| 8219 | /* 2018 */ "TAILCALLREGHB64\000" |
| 8220 | /* 2034 */ "JR_HB64\000" |
| 8221 | /* 2042 */ "JALR_HB64\000" |
| 8222 | /* 2052 */ "LB64\000" |
| 8223 | /* 2057 */ "SB64\000" |
| 8224 | /* 2062 */ "LOAD_ACC64\000" |
| 8225 | /* 2073 */ "STORE_ACC64\000" |
| 8226 | /* 2085 */ "BGEC64\000" |
| 8227 | /* 2092 */ "BNEC64\000" |
| 8228 | /* 2099 */ "JIC64\000" |
| 8229 | /* 2105 */ "JIALC64\000" |
| 8230 | /* 2113 */ "BEQC64\000" |
| 8231 | /* 2120 */ "SC64\000" |
| 8232 | /* 2125 */ "BLTC64\000" |
| 8233 | /* 2132 */ "BGEUC64\000" |
| 8234 | /* 2140 */ "BLTUC64\000" |
| 8235 | /* 2148 */ "BGEZC64\000" |
| 8236 | /* 2156 */ "BLEZC64\000" |
| 8237 | /* 2164 */ "BNEZC64\000" |
| 8238 | /* 2172 */ "BEQZC64\000" |
| 8239 | /* 2180 */ "BGTZC64\000" |
| 8240 | /* 2188 */ "BLTZC64\000" |
| 8241 | /* 2196 */ "AND64\000" |
| 8242 | /* 2202 */ "MFC1_D64\000" |
| 8243 | /* 2211 */ "MFHC1_D64\000" |
| 8244 | /* 2221 */ "MTHC1_D64\000" |
| 8245 | /* 2231 */ "MTC1_D64\000" |
| 8246 | /* 2240 */ "MOVN_I64_D64\000" |
| 8247 | /* 2253 */ "MOVZ_I64_D64\000" |
| 8248 | /* 2266 */ "FSUB_D64\000" |
| 8249 | /* 2275 */ "NMSUB_D64\000" |
| 8250 | /* 2285 */ "FADD_D64\000" |
| 8251 | /* 2294 */ "NMADD_D64\000" |
| 8252 | /* 2304 */ "C_NGE_D64\000" |
| 8253 | /* 2314 */ "C_NGLE_D64\000" |
| 8254 | /* 2325 */ "C_OLE_D64\000" |
| 8255 | /* 2335 */ "C_ULE_D64\000" |
| 8256 | /* 2345 */ "C_LE_D64\000" |
| 8257 | /* 2354 */ "C_SF_D64\000" |
| 8258 | /* 2363 */ "MOVF_D64\000" |
| 8259 | /* 2372 */ "C_F_D64\000" |
| 8260 | /* 2380 */ "PseudoSELECTFP_F_D64\000" |
| 8261 | /* 2401 */ "FNEG_D64\000" |
| 8262 | /* 2410 */ "MOVN_I_D64\000" |
| 8263 | /* 2421 */ "MOVZ_I_D64\000" |
| 8264 | /* 2432 */ "C_NGL_D64\000" |
| 8265 | /* 2442 */ "FMUL_D64\000" |
| 8266 | /* 2451 */ "TRUNC_L_D64\000" |
| 8267 | /* 2463 */ "ROUND_L_D64\000" |
| 8268 | /* 2475 */ "CEIL_L_D64\000" |
| 8269 | /* 2486 */ "FLOOR_L_D64\000" |
| 8270 | /* 2498 */ "CVT_L_D64\000" |
| 8271 | /* 2508 */ "LDC1_MM_D64\000" |
| 8272 | /* 2520 */ "SDC1_MM_D64\000" |
| 8273 | /* 2532 */ "C_UN_D64\000" |
| 8274 | /* 2541 */ "RECIP_D64\000" |
| 8275 | /* 2551 */ "FCMP_D64\000" |
| 8276 | /* 2560 */ "C_SEQ_D64\000" |
| 8277 | /* 2570 */ "C_UEQ_D64\000" |
| 8278 | /* 2580 */ "C_EQ_D64\000" |
| 8279 | /* 2589 */ "FABS_D64\000" |
| 8280 | /* 2598 */ "CVT_S_D64\000" |
| 8281 | /* 2608 */ "PseudoSELECT_D64\000" |
| 8282 | /* 2625 */ "C_NGT_D64\000" |
| 8283 | /* 2635 */ "C_OLT_D64\000" |
| 8284 | /* 2645 */ "C_ULT_D64\000" |
| 8285 | /* 2655 */ "C_LT_D64\000" |
| 8286 | /* 2664 */ "FSQRT_D64\000" |
| 8287 | /* 2674 */ "RSQRT_D64\000" |
| 8288 | /* 2684 */ "MOVT_D64\000" |
| 8289 | /* 2693 */ "PseudoSELECTFP_T_D64\000" |
| 8290 | /* 2714 */ "FDIV_D64\000" |
| 8291 | /* 2723 */ "FMOV_D64\000" |
| 8292 | /* 2732 */ "TRUNC_W_D64\000" |
| 8293 | /* 2744 */ "ROUND_W_D64\000" |
| 8294 | /* 2756 */ "CEIL_W_D64\000" |
| 8295 | /* 2767 */ "FLOOR_W_D64\000" |
| 8296 | /* 2779 */ "CVT_W_D64\000" |
| 8297 | /* 2789 */ "BNE64\000" |
| 8298 | /* 2795 */ "BuildPairF64\000" |
| 8299 | /* 2808 */ "ExtractElementF64\000" |
| 8300 | /* 2826 */ "TAILCALLREG64\000" |
| 8301 | /* 2840 */ "SEH64\000" |
| 8302 | /* 2846 */ "LH64\000" |
| 8303 | /* 2851 */ "SH64\000" |
| 8304 | /* 2856 */ "PseudoMFHI64\000" |
| 8305 | /* 2869 */ "PseudoMTLOHI64\000" |
| 8306 | /* 2884 */ "MTHI64\000" |
| 8307 | /* 2891 */ "MOVN_I64_I64\000" |
| 8308 | /* 2904 */ "MOVZ_I64_I64\000" |
| 8309 | /* 2917 */ "ATOMIC_LOAD_SUB_I64\000" |
| 8310 | /* 2937 */ "ATOMIC_LOAD_ADD_I64\000" |
| 8311 | /* 2957 */ "ATOMIC_LOAD_NAND_I64\000" |
| 8312 | /* 2978 */ "ATOMIC_LOAD_AND_I64\000" |
| 8313 | /* 2998 */ "MOVF_I64\000" |
| 8314 | /* 3007 */ "PseudoSELECTFP_F_I64\000" |
| 8315 | /* 3028 */ "MOVN_I_I64\000" |
| 8316 | /* 3039 */ "MOVZ_I_I64\000" |
| 8317 | /* 3050 */ "ATOMIC_LOAD_UMIN_I64\000" |
| 8318 | /* 3071 */ "ATOMIC_LOAD_MIN_I64\000" |
| 8319 | /* 3091 */ "ATOMIC_SWAP_I64\000" |
| 8320 | /* 3107 */ "ATOMIC_CMP_SWAP_I64\000" |
| 8321 | /* 3127 */ "ATOMIC_LOAD_XOR_I64\000" |
| 8322 | /* 3147 */ "ATOMIC_LOAD_OR_I64\000" |
| 8323 | /* 3166 */ "PseudoD_SELECT_I64\000" |
| 8324 | /* 3185 */ "PseudoSELECT_I64\000" |
| 8325 | /* 3202 */ "MOVT_I64\000" |
| 8326 | /* 3211 */ "PseudoSELECTFP_T_I64\000" |
| 8327 | /* 3232 */ "ATOMIC_LOAD_UMAX_I64\000" |
| 8328 | /* 3253 */ "ATOMIC_LOAD_MAX_I64\000" |
| 8329 | /* 3273 */ "LL64\000" |
| 8330 | /* 3278 */ "CVT_S_PL64\000" |
| 8331 | /* 3289 */ "LWL64\000" |
| 8332 | /* 3295 */ "SWL64\000" |
| 8333 | /* 3301 */ "PseudoMFLO64\000" |
| 8334 | /* 3314 */ "MTLO64\000" |
| 8335 | /* 3321 */ "BEQ64\000" |
| 8336 | /* 3327 */ "JR64\000" |
| 8337 | /* 3332 */ "JALR64\000" |
| 8338 | /* 3339 */ "NOR64\000" |
| 8339 | /* 3345 */ "XOR64\000" |
| 8340 | /* 3351 */ "RDHWR64\000" |
| 8341 | /* 3359 */ "LWR64\000" |
| 8342 | /* 3365 */ "SWR64\000" |
| 8343 | /* 3371 */ "FSUB_PS64\000" |
| 8344 | /* 3381 */ "FADD_PS64\000" |
| 8345 | /* 3391 */ "PLL_PS64\000" |
| 8346 | /* 3400 */ "FMUL_PS64\000" |
| 8347 | /* 3410 */ "PUL_PS64\000" |
| 8348 | /* 3419 */ "ADDR_PS64\000" |
| 8349 | /* 3429 */ "MULR_PS64\000" |
| 8350 | /* 3439 */ "PLU_PS64\000" |
| 8351 | /* 3448 */ "PUU_PS64\000" |
| 8352 | /* 3457 */ "CVT_PW_PS64\000" |
| 8353 | /* 3469 */ "CVT_PS_S64\000" |
| 8354 | /* 3480 */ "SLT64\000" |
| 8355 | /* 3486 */ "CVT_S_PU64\000" |
| 8356 | /* 3497 */ "LW64\000" |
| 8357 | /* 3502 */ "CVT_PS_PW64\000" |
| 8358 | /* 3514 */ "SW64\000" |
| 8359 | /* 3519 */ "BGEZ64\000" |
| 8360 | /* 3526 */ "BLEZ64\000" |
| 8361 | /* 3533 */ "SELNEZ64\000" |
| 8362 | /* 3542 */ "SELEQZ64\000" |
| 8363 | /* 3551 */ "BGTZ64\000" |
| 8364 | /* 3558 */ "BLTZ64\000" |
| 8365 | /* 3565 */ "BuildPairF64_64\000" |
| 8366 | /* 3581 */ "ExtractElementF64_64\000" |
| 8367 | /* 3602 */ "SLL64_64\000" |
| 8368 | /* 3611 */ "LONG_BRANCH_LUi2Op_64\000" |
| 8369 | /* 3633 */ "LoadAddrReg64\000" |
| 8370 | /* 3647 */ "PseudoIndirectHazardBranch64\000" |
| 8371 | /* 3676 */ "PseudoIndirectBranch64\000" |
| 8372 | /* 3699 */ "ANDi64\000" |
| 8373 | /* 3706 */ "XORi64\000" |
| 8374 | /* 3713 */ "SLTi64\000" |
| 8375 | /* 3720 */ "LUi64\000" |
| 8376 | /* 3726 */ "SGEImm64\000" |
| 8377 | /* 3735 */ "SLEImm64\000" |
| 8378 | /* 3744 */ "NORImm64\000" |
| 8379 | /* 3753 */ "SGTImm64\000" |
| 8380 | /* 3762 */ "SLTImm64\000" |
| 8381 | /* 3771 */ "SGEUImm64\000" |
| 8382 | /* 3781 */ "SLEUImm64\000" |
| 8383 | /* 3791 */ "SGTUImm64\000" |
| 8384 | /* 3801 */ "SLTUImm64\000" |
| 8385 | /* 3811 */ "LoadImm64\000" |
| 8386 | /* 3821 */ "LoadAddrImm64\000" |
| 8387 | /* 3835 */ "PseudoReturn64\000" |
| 8388 | /* 3850 */ "MIPSeh_return64\000" |
| 8389 | /* 3866 */ "LBu64\000" |
| 8390 | /* 3872 */ "LHu64\000" |
| 8391 | /* 3878 */ "SLTu64\000" |
| 8392 | /* 3885 */ "LEA_ADDiu64\000" |
| 8393 | /* 3897 */ "SLTiu64\000" |
| 8394 | /* 3905 */ "MoveR3216\000" |
| 8395 | /* 3915 */ "RetRA16\000" |
| 8396 | /* 3923 */ "JalB16\000" |
| 8397 | /* 3930 */ "LD_F16\000" |
| 8398 | /* 3937 */ "ST_F16\000" |
| 8399 | /* 3944 */ "ATOMIC_LOAD_SUB_I16\000" |
| 8400 | /* 3964 */ "ATOMIC_LOAD_ADD_I16\000" |
| 8401 | /* 3984 */ "ATOMIC_LOAD_NAND_I16\000" |
| 8402 | /* 4005 */ "ATOMIC_LOAD_AND_I16\000" |
| 8403 | /* 4025 */ "ATOMIC_LOAD_UMIN_I16\000" |
| 8404 | /* 4046 */ "ATOMIC_LOAD_MIN_I16\000" |
| 8405 | /* 4066 */ "ATOMIC_SWAP_I16\000" |
| 8406 | /* 4082 */ "ATOMIC_CMP_SWAP_I16\000" |
| 8407 | /* 4102 */ "ATOMIC_LOAD_XOR_I16\000" |
| 8408 | /* 4122 */ "ATOMIC_LOAD_OR_I16\000" |
| 8409 | /* 4141 */ "ATOMIC_LOAD_UMAX_I16\000" |
| 8410 | /* 4162 */ "ATOMIC_LOAD_MAX_I16\000" |
| 8411 | /* 4182 */ "Move32R16\000" |
| 8412 | /* 4192 */ "SraX16\000" |
| 8413 | /* 4199 */ "RestoreX16\000" |
| 8414 | /* 4210 */ "SaveX16\000" |
| 8415 | /* 4218 */ "BtnezT8CmpiX16\000" |
| 8416 | /* 4233 */ "BteqzT8CmpiX16\000" |
| 8417 | /* 4248 */ "BtnezT8SltiX16\000" |
| 8418 | /* 4263 */ "BteqzT8SltiX16\000" |
| 8419 | /* 4278 */ "SllX16\000" |
| 8420 | /* 4285 */ "SrlX16\000" |
| 8421 | /* 4292 */ "LbRxRyOffMemX16\000" |
| 8422 | /* 4308 */ "SbRxRyOffMemX16\000" |
| 8423 | /* 4324 */ "LhRxRyOffMemX16\000" |
| 8424 | /* 4340 */ "ShRxRyOffMemX16\000" |
| 8425 | /* 4356 */ "LbuRxRyOffMemX16\000" |
| 8426 | /* 4373 */ "LhuRxRyOffMemX16\000" |
| 8427 | /* 4390 */ "AddiuRxRyOffMemX16\000" |
| 8428 | /* 4409 */ "LwRxRyOffMemX16\000" |
| 8429 | /* 4425 */ "SwRxRyOffMemX16\000" |
| 8430 | /* 4441 */ "AddiuRxPcImmX16\000" |
| 8431 | /* 4457 */ "AddiuSpImmX16\000" |
| 8432 | /* 4471 */ "LwRxSpImmX16\000" |
| 8433 | /* 4484 */ "SwRxSpImmX16\000" |
| 8434 | /* 4497 */ "SltiCCRxImmX16\000" |
| 8435 | /* 4512 */ "SltiuCCRxImmX16\000" |
| 8436 | /* 4528 */ "LiRxImmX16\000" |
| 8437 | /* 4539 */ "CmpiRxImmX16\000" |
| 8438 | /* 4552 */ "SltiRxImmX16\000" |
| 8439 | /* 4565 */ "AddiuRxImmX16\000" |
| 8440 | /* 4579 */ "SltiuRxImmX16\000" |
| 8441 | /* 4593 */ "AddiuRxRxImmX16\000" |
| 8442 | /* 4609 */ "BnezRxImmX16\000" |
| 8443 | /* 4622 */ "BeqzRxImmX16\000" |
| 8444 | /* 4635 */ "BimmX16\000" |
| 8445 | /* 4643 */ "LiRxImmAlignX16\000" |
| 8446 | /* 4659 */ "LwRxPcTcpX16\000" |
| 8447 | /* 4672 */ "BtnezT8CmpX16\000" |
| 8448 | /* 4686 */ "BteqzT8CmpX16\000" |
| 8449 | /* 4700 */ "BtnezT8SltX16\000" |
| 8450 | /* 4714 */ "BteqzT8SltX16\000" |
| 8451 | /* 4728 */ "BtnezT8SltiuX16\000" |
| 8452 | /* 4744 */ "BteqzT8SltiuX16\000" |
| 8453 | /* 4760 */ "BtnezT8SltuX16\000" |
| 8454 | /* 4775 */ "BteqzT8SltuX16\000" |
| 8455 | /* 4790 */ "BtnezX16\000" |
| 8456 | /* 4799 */ "BteqzX16\000" |
| 8457 | /* 4808 */ "JrcRa16\000" |
| 8458 | /* 4816 */ "JrRa16\000" |
| 8459 | /* 4823 */ "Restore16\000" |
| 8460 | /* 4833 */ "GotPrologue16\000" |
| 8461 | /* 4847 */ "Save16\000" |
| 8462 | /* 4854 */ "JumpLinkReg16\000" |
| 8463 | /* 4868 */ "Mfhi16\000" |
| 8464 | /* 4875 */ "Break16\000" |
| 8465 | /* 4883 */ "Jal16\000" |
| 8466 | /* 4889 */ "AddiuSpImm16\000" |
| 8467 | /* 4902 */ "LiRxImm16\000" |
| 8468 | /* 4912 */ "CmpiRxImm16\000" |
| 8469 | /* 4924 */ "SltiRxImm16\000" |
| 8470 | /* 4936 */ "SltiuRxImm16\000" |
| 8471 | /* 4949 */ "AddiuRxRxImm16\000" |
| 8472 | /* 4964 */ "BnezRxImm16\000" |
| 8473 | /* 4976 */ "BeqzRxImm16\000" |
| 8474 | /* 4988 */ "Bimm16\000" |
| 8475 | /* 4995 */ "Mflo16\000" |
| 8476 | /* 5002 */ "LwRxPcTcp16\000" |
| 8477 | /* 5014 */ "SebRx16\000" |
| 8478 | /* 5022 */ "JrcRx16\000" |
| 8479 | /* 5030 */ "SehRx16\000" |
| 8480 | /* 5038 */ "SltCCRxRy16\000" |
| 8481 | /* 5050 */ "SltuCCRxRy16\000" |
| 8482 | /* 5063 */ "NegRxRy16\000" |
| 8483 | /* 5073 */ "CmpRxRy16\000" |
| 8484 | /* 5083 */ "SltRxRy16\000" |
| 8485 | /* 5093 */ "MultRxRy16\000" |
| 8486 | /* 5104 */ "NotRxRy16\000" |
| 8487 | /* 5114 */ "SltuRxRy16\000" |
| 8488 | /* 5125 */ "MultuRxRy16\000" |
| 8489 | /* 5137 */ "DivuRxRy16\000" |
| 8490 | /* 5148 */ "SravRxRy16\000" |
| 8491 | /* 5159 */ "DivRxRy16\000" |
| 8492 | /* 5169 */ "SllvRxRy16\000" |
| 8493 | /* 5180 */ "SrlvRxRy16\000" |
| 8494 | /* 5191 */ "AndRxRxRy16\000" |
| 8495 | /* 5203 */ "OrRxRxRy16\000" |
| 8496 | /* 5214 */ "XorRxRxRy16\000" |
| 8497 | /* 5226 */ "MultRxRyRz16\000" |
| 8498 | /* 5239 */ "SubuRxRyRz16\000" |
| 8499 | /* 5252 */ "AdduRxRyRz16\000" |
| 8500 | /* 5265 */ "SltuRxRyRz16\000" |
| 8501 | /* 5278 */ "MultuRxRyRz16\000" |
| 8502 | /* 5292 */ "Btnez16\000" |
| 8503 | /* 5300 */ "Bteqz16\000" |
| 8504 | /* 5308 */ "PseudoIndrectHazardBranch64R6\000" |
| 8505 | /* 5338 */ "PseudoIndirectBranch64R6\000" |
| 8506 | /* 5363 */ "MFC0_MMR6\000" |
| 8507 | /* 5373 */ "MFHC0_MMR6\000" |
| 8508 | /* 5384 */ "MTHC0_MMR6\000" |
| 8509 | /* 5395 */ "MTC0_MMR6\000" |
| 8510 | /* 5405 */ "MFC1_MMR6\000" |
| 8511 | /* 5415 */ "MTC1_MMR6\000" |
| 8512 | /* 5425 */ "LDC2_MMR6\000" |
| 8513 | /* 5435 */ "SDC2_MMR6\000" |
| 8514 | /* 5445 */ "MFC2_MMR6\000" |
| 8515 | /* 5455 */ "MFHC2_MMR6\000" |
| 8516 | /* 5466 */ "MTHC2_MMR6\000" |
| 8517 | /* 5477 */ "MTC2_MMR6\000" |
| 8518 | /* 5487 */ "LWC2_MMR6\000" |
| 8519 | /* 5497 */ "SWC2_MMR6\000" |
| 8520 | /* 5507 */ "LDC1_D64_MMR6\000" |
| 8521 | /* 5521 */ "SDC1_D64_MMR6\000" |
| 8522 | /* 5535 */ "SB16_MMR6\000" |
| 8523 | /* 5545 */ "BC16_MMR6\000" |
| 8524 | /* 5555 */ "JRC16_MMR6\000" |
| 8525 | /* 5566 */ "JALRC16_MMR6\000" |
| 8526 | /* 5579 */ "BNEZC16_MMR6\000" |
| 8527 | /* 5592 */ "BEQZC16_MMR6\000" |
| 8528 | /* 5605 */ "AND16_MMR6\000" |
| 8529 | /* 5616 */ "MOVE16_MMR6\000" |
| 8530 | /* 5628 */ "SH16_MMR6\000" |
| 8531 | /* 5638 */ "ANDI16_MMR6\000" |
| 8532 | /* 5650 */ "LI16_MMR6\000" |
| 8533 | /* 5660 */ "BREAK16_MMR6\000" |
| 8534 | /* 5673 */ "SLL16_MMR6\000" |
| 8535 | /* 5684 */ "SRL16_MMR6\000" |
| 8536 | /* 5695 */ "LWM16_MMR6\000" |
| 8537 | /* 5706 */ "SWM16_MMR6\000" |
| 8538 | /* 5717 */ "SDBBP16_MMR6\000" |
| 8539 | /* 5730 */ "XOR16_MMR6\000" |
| 8540 | /* 5741 */ "NOT16_MMR6\000" |
| 8541 | /* 5752 */ "SUBU16_MMR6\000" |
| 8542 | /* 5764 */ "ADDU16_MMR6\000" |
| 8543 | /* 5776 */ "SW16_MMR6\000" |
| 8544 | /* 5786 */ "LSA_MMR6\000" |
| 8545 | /* 5795 */ "EHB_MMR6\000" |
| 8546 | /* 5804 */ "JALRC_HB_MMR6\000" |
| 8547 | /* 5818 */ "LB_MMR6\000" |
| 8548 | /* 5826 */ "SB_MMR6\000" |
| 8549 | /* 5834 */ "SUB_MMR6\000" |
| 8550 | /* 5843 */ "BC_MMR6\000" |
| 8551 | /* 5851 */ "BGEC_MMR6\000" |
| 8552 | /* 5861 */ "BNEC_MMR6\000" |
| 8553 | /* 5871 */ "JIC_MMR6\000" |
| 8554 | /* 5880 */ "BALC_MMR6\000" |
| 8555 | /* 5890 */ "JIALC_MMR6\000" |
| 8556 | /* 5901 */ "BGEZALC_MMR6\000" |
| 8557 | /* 5914 */ "BLEZALC_MMR6\000" |
| 8558 | /* 5927 */ "BNEZALC_MMR6\000" |
| 8559 | /* 5940 */ "BEQZALC_MMR6\000" |
| 8560 | /* 5953 */ "BGTZALC_MMR6\000" |
| 8561 | /* 5966 */ "BLTZALC_MMR6\000" |
| 8562 | /* 5979 */ "ERETNC_MMR6\000" |
| 8563 | /* 5991 */ "SYNC_MMR6\000" |
| 8564 | /* 6001 */ "AUIPC_MMR6\000" |
| 8565 | /* 6012 */ "ALUIPC_MMR6\000" |
| 8566 | /* 6024 */ "ADDIUPC_MMR6\000" |
| 8567 | /* 6037 */ "LWPC_MMR6\000" |
| 8568 | /* 6047 */ "BEQC_MMR6\000" |
| 8569 | /* 6057 */ "JALRC_MMR6\000" |
| 8570 | /* 6068 */ "SC_MMR6\000" |
| 8571 | /* 6076 */ "BLTC_MMR6\000" |
| 8572 | /* 6086 */ "BGEUC_MMR6\000" |
| 8573 | /* 6097 */ "BLTUC_MMR6\000" |
| 8574 | /* 6108 */ "BNVC_MMR6\000" |
| 8575 | /* 6118 */ "BOVC_MMR6\000" |
| 8576 | /* 6128 */ "BGEZC_MMR6\000" |
| 8577 | /* 6139 */ "BLEZC_MMR6\000" |
| 8578 | /* 6150 */ "BC1NEZC_MMR6\000" |
| 8579 | /* 6163 */ "BC2NEZC_MMR6\000" |
| 8580 | /* 6176 */ "BNEZC_MMR6\000" |
| 8581 | /* 6187 */ "BC1EQZC_MMR6\000" |
| 8582 | /* 6200 */ "BC2EQZC_MMR6\000" |
| 8583 | /* 6213 */ "BEQZC_MMR6\000" |
| 8584 | /* 6224 */ "BGTZC_MMR6\000" |
| 8585 | /* 6235 */ "BLTZC_MMR6\000" |
| 8586 | /* 6246 */ "ADD_MMR6\000" |
| 8587 | /* 6255 */ "AND_MMR6\000" |
| 8588 | /* 6264 */ "MOD_MMR6\000" |
| 8589 | /* 6273 */ "MINA_D_MMR6\000" |
| 8590 | /* 6285 */ "MAXA_D_MMR6\000" |
| 8591 | /* 6297 */ "CMP_SLE_D_MMR6\000" |
| 8592 | /* 6312 */ "CMP_SULE_D_MMR6\000" |
| 8593 | /* 6328 */ "CMP_ULE_D_MMR6\000" |
| 8594 | /* 6343 */ "CMP_LE_D_MMR6\000" |
| 8595 | /* 6357 */ "CMP_SAF_D_MMR6\000" |
| 8596 | /* 6372 */ "CMP_AF_D_MMR6\000" |
| 8597 | /* 6386 */ "MSUBF_D_MMR6\000" |
| 8598 | /* 6399 */ "MADDF_D_MMR6\000" |
| 8599 | /* 6412 */ "SEL_D_MMR6\000" |
| 8600 | /* 6423 */ "TRUNC_L_D_MMR6\000" |
| 8601 | /* 6438 */ "ROUND_L_D_MMR6\000" |
| 8602 | /* 6453 */ "CEIL_L_D_MMR6\000" |
| 8603 | /* 6467 */ "FLOOR_L_D_MMR6\000" |
| 8604 | /* 6482 */ "CVT_L_D_MMR6\000" |
| 8605 | /* 6495 */ "MIN_D_MMR6\000" |
| 8606 | /* 6506 */ "CMP_SUN_D_MMR6\000" |
| 8607 | /* 6521 */ "CMP_UN_D_MMR6\000" |
| 8608 | /* 6535 */ "CMP_SEQ_D_MMR6\000" |
| 8609 | /* 6550 */ "CMP_SUEQ_D_MMR6\000" |
| 8610 | /* 6566 */ "CMP_UEQ_D_MMR6\000" |
| 8611 | /* 6581 */ "CMP_EQ_D_MMR6\000" |
| 8612 | /* 6595 */ "CLASS_D_MMR6\000" |
| 8613 | /* 6608 */ "CMP_SLT_D_MMR6\000" |
| 8614 | /* 6623 */ "CMP_SULT_D_MMR6\000" |
| 8615 | /* 6639 */ "CMP_ULT_D_MMR6\000" |
| 8616 | /* 6654 */ "CMP_LT_D_MMR6\000" |
| 8617 | /* 6668 */ "RINT_D_MMR6\000" |
| 8618 | /* 6680 */ "FMOV_D_MMR6\000" |
| 8619 | /* 6692 */ "TRUNC_W_D_MMR6\000" |
| 8620 | /* 6707 */ "ROUND_W_D_MMR6\000" |
| 8621 | /* 6722 */ "CEIL_W_D_MMR6\000" |
| 8622 | /* 6736 */ "FLOOR_W_D_MMR6\000" |
| 8623 | /* 6751 */ "MAX_D_MMR6\000" |
| 8624 | /* 6762 */ "SELNEZ_D_MMR6\000" |
| 8625 | /* 6776 */ "SELEQZ_D_MMR6\000" |
| 8626 | /* 6790 */ "CACHE_MMR6\000" |
| 8627 | /* 6801 */ "SIGRIE_MMR6\000" |
| 8628 | /* 6813 */ "PAUSE_MMR6\000" |
| 8629 | /* 6824 */ "PREF_MMR6\000" |
| 8630 | /* 6834 */ "TLBINVF_MMR6\000" |
| 8631 | /* 6847 */ "TAILCALLREG_MMR6\000" |
| 8632 | /* 6864 */ "WSBH_MMR6\000" |
| 8633 | /* 6874 */ "SH_MMR6\000" |
| 8634 | /* 6882 */ "MUH_MMR6\000" |
| 8635 | /* 6891 */ "SYNCI_MMR6\000" |
| 8636 | /* 6902 */ "ANDI_MMR6\000" |
| 8637 | /* 6912 */ "EI_MMR6\000" |
| 8638 | /* 6920 */ "XORI_MMR6\000" |
| 8639 | /* 6930 */ "AUI_MMR6\000" |
| 8640 | /* 6939 */ "LUI_MMR6\000" |
| 8641 | /* 6948 */ "GINVI_MMR6\000" |
| 8642 | /* 6959 */ "BREAK_MMR6\000" |
| 8643 | /* 6970 */ "JAL_MMR6\000" |
| 8644 | /* 6979 */ "TAILCALL_MMR6\000" |
| 8645 | /* 6993 */ "SLL_MMR6\000" |
| 8646 | /* 7002 */ "MUL_MMR6\000" |
| 8647 | /* 7011 */ "CVT_D_L_MMR6\000" |
| 8648 | /* 7024 */ "CVT_S_L_MMR6\000" |
| 8649 | /* 7037 */ "ALIGN_MMR6\000" |
| 8650 | /* 7048 */ "CLO_MMR6\000" |
| 8651 | /* 7057 */ "BITSWAP_MMR6\000" |
| 8652 | /* 7070 */ "SDBBP_MMR6\000" |
| 8653 | /* 7081 */ "MOVEP_MMR6\000" |
| 8654 | /* 7092 */ "SSNOP_MMR6\000" |
| 8655 | /* 7103 */ "JRCADDIUSP_MMR6\000" |
| 8656 | /* 7119 */ "SWSP_MMR6\000" |
| 8657 | /* 7129 */ "DVP_MMR6\000" |
| 8658 | /* 7138 */ "EVP_MMR6\000" |
| 8659 | /* 7147 */ "NOR_MMR6\000" |
| 8660 | /* 7156 */ "XOR_MMR6\000" |
| 8661 | /* 7165 */ "RDPGPR_MMR6\000" |
| 8662 | /* 7177 */ "WRPGPR_MMR6\000" |
| 8663 | /* 7189 */ "RDHWR_MMR6\000" |
| 8664 | /* 7200 */ "INS_MMR6\000" |
| 8665 | /* 7209 */ "MINA_S_MMR6\000" |
| 8666 | /* 7221 */ "MAXA_S_MMR6\000" |
| 8667 | /* 7233 */ "FSUB_S_MMR6\000" |
| 8668 | /* 7245 */ "FADD_S_MMR6\000" |
| 8669 | /* 7257 */ "CMP_SLE_S_MMR6\000" |
| 8670 | /* 7272 */ "CMP_SULE_S_MMR6\000" |
| 8671 | /* 7288 */ "CMP_ULE_S_MMR6\000" |
| 8672 | /* 7303 */ "CMP_LE_S_MMR6\000" |
| 8673 | /* 7317 */ "CMP_SAF_S_MMR6\000" |
| 8674 | /* 7332 */ "CMP_AF_S_MMR6\000" |
| 8675 | /* 7346 */ "MSUBF_S_MMR6\000" |
| 8676 | /* 7359 */ "MADDF_S_MMR6\000" |
| 8677 | /* 7372 */ "FNEG_S_MMR6\000" |
| 8678 | /* 7384 */ "SEL_S_MMR6\000" |
| 8679 | /* 7395 */ "FMUL_S_MMR6\000" |
| 8680 | /* 7407 */ "TRUNC_L_S_MMR6\000" |
| 8681 | /* 7422 */ "ROUND_L_S_MMR6\000" |
| 8682 | /* 7437 */ "CEIL_L_S_MMR6\000" |
| 8683 | /* 7451 */ "FLOOR_L_S_MMR6\000" |
| 8684 | /* 7466 */ "CVT_L_S_MMR6\000" |
| 8685 | /* 7479 */ "MIN_S_MMR6\000" |
| 8686 | /* 7490 */ "CMP_SUN_S_MMR6\000" |
| 8687 | /* 7505 */ "CMP_UN_S_MMR6\000" |
| 8688 | /* 7519 */ "CMP_SEQ_S_MMR6\000" |
| 8689 | /* 7534 */ "CMP_SUEQ_S_MMR6\000" |
| 8690 | /* 7550 */ "CMP_UEQ_S_MMR6\000" |
| 8691 | /* 7565 */ "CMP_EQ_S_MMR6\000" |
| 8692 | /* 7579 */ "CLASS_S_MMR6\000" |
| 8693 | /* 7592 */ "CMP_SLT_S_MMR6\000" |
| 8694 | /* 7607 */ "CMP_SULT_S_MMR6\000" |
| 8695 | /* 7623 */ "CMP_ULT_S_MMR6\000" |
| 8696 | /* 7638 */ "CMP_LT_S_MMR6\000" |
| 8697 | /* 7652 */ "RINT_S_MMR6\000" |
| 8698 | /* 7664 */ "FDIV_S_MMR6\000" |
| 8699 | /* 7676 */ "FMOV_S_MMR6\000" |
| 8700 | /* 7688 */ "TRUNC_W_S_MMR6\000" |
| 8701 | /* 7703 */ "ROUND_W_S_MMR6\000" |
| 8702 | /* 7718 */ "CEIL_W_S_MMR6\000" |
| 8703 | /* 7732 */ "FLOOR_W_S_MMR6\000" |
| 8704 | /* 7747 */ "CVT_W_S_MMR6\000" |
| 8705 | /* 7760 */ "MAX_S_MMR6\000" |
| 8706 | /* 7771 */ "SELNEZ_S_MMR6\000" |
| 8707 | /* 7785 */ "SELEQZ_S_MMR6\000" |
| 8708 | /* 7799 */ "DERET_MMR6\000" |
| 8709 | /* 7810 */ "WAIT_MMR6\000" |
| 8710 | /* 7820 */ "GINVT_MMR6\000" |
| 8711 | /* 7831 */ "EXT_MMR6\000" |
| 8712 | /* 7840 */ "LBU_MMR6\000" |
| 8713 | /* 7849 */ "SUBU_MMR6\000" |
| 8714 | /* 7859 */ "ADDU_MMR6\000" |
| 8715 | /* 7869 */ "MODU_MMR6\000" |
| 8716 | /* 7879 */ "MUHU_MMR6\000" |
| 8717 | /* 7889 */ "ADDIU_MMR6\000" |
| 8718 | /* 7900 */ "MULU_MMR6\000" |
| 8719 | /* 7910 */ "DIVU_MMR6\000" |
| 8720 | /* 7920 */ "DIV_MMR6\000" |
| 8721 | /* 7929 */ "TLBINV_MMR6\000" |
| 8722 | /* 7941 */ "LW_MMR6\000" |
| 8723 | /* 7949 */ "SW_MMR6\000" |
| 8724 | /* 7957 */ "CVT_S_W_MMR6\000" |
| 8725 | /* 7970 */ "SELNEZ_MMR6\000" |
| 8726 | /* 7982 */ "CLZ_MMR6\000" |
| 8727 | /* 7991 */ "SELEQZ_MMR6\000" |
| 8728 | /* 8003 */ "PseudoIndirectBranch_MMR6\000" |
| 8729 | /* 8029 */ "LDC2_R6\000" |
| 8730 | /* 8037 */ "SDC2_R6\000" |
| 8731 | /* 8045 */ "LWC2_R6\000" |
| 8732 | /* 8053 */ "SWC2_R6\000" |
| 8733 | /* 8061 */ "JR_HB64_R6\000" |
| 8734 | /* 8072 */ "SC64_R6\000" |
| 8735 | /* 8080 */ "LL64_R6\000" |
| 8736 | /* 8088 */ "DLSA_R6\000" |
| 8737 | /* 8096 */ "JR_HB_R6\000" |
| 8738 | /* 8105 */ "SC_R6\000" |
| 8739 | /* 8111 */ "SCD_R6\000" |
| 8740 | /* 8118 */ "LLD_R6\000" |
| 8741 | /* 8125 */ "CACHE_R6\000" |
| 8742 | /* 8134 */ "PREF_R6\000" |
| 8743 | /* 8142 */ "LL_R6\000" |
| 8744 | /* 8148 */ "DMUL_R6\000" |
| 8745 | /* 8156 */ "DCLO_R6\000" |
| 8746 | /* 8164 */ "SDBBP_R6\000" |
| 8747 | /* 8173 */ "DCLZ_R6\000" |
| 8748 | /* 8181 */ "PseudoIndrectHazardBranchR6\000" |
| 8749 | /* 8209 */ "PseudoIndirectBranchR6\000" |
| 8750 | /* 8232 */ "LOAD_ACC128\000" |
| 8751 | /* 8244 */ "STORE_ACC128\000" |
| 8752 | /* 8257 */ "ATOMIC_LOAD_SUB_I8\000" |
| 8753 | /* 8276 */ "ATOMIC_LOAD_ADD_I8\000" |
| 8754 | /* 8295 */ "ATOMIC_LOAD_NAND_I8\000" |
| 8755 | /* 8315 */ "ATOMIC_LOAD_AND_I8\000" |
| 8756 | /* 8334 */ "ATOMIC_LOAD_UMIN_I8\000" |
| 8757 | /* 8354 */ "ATOMIC_LOAD_MIN_I8\000" |
| 8758 | /* 8373 */ "ATOMIC_SWAP_I8\000" |
| 8759 | /* 8388 */ "ATOMIC_CMP_SWAP_I8\000" |
| 8760 | /* 8407 */ "ATOMIC_LOAD_XOR_I8\000" |
| 8761 | /* 8426 */ "ATOMIC_LOAD_OR_I8\000" |
| 8762 | /* 8444 */ "ATOMIC_LOAD_UMAX_I8\000" |
| 8763 | /* 8464 */ "ATOMIC_LOAD_MAX_I8\000" |
| 8764 | /* 8483 */ "SAA\000" |
| 8765 | /* 8487 */ "PRECEU_PH_QBLA\000" |
| 8766 | /* 8502 */ "PRECEQU_PH_QBLA\000" |
| 8767 | /* 8518 */ "G_FMA\000" |
| 8768 | /* 8524 */ "G_STRICT_FMA\000" |
| 8769 | /* 8537 */ "PRECEU_PH_QBRA\000" |
| 8770 | /* 8552 */ "PRECEQU_PH_QBRA\000" |
| 8771 | /* 8568 */ "DSRA\000" |
| 8772 | /* 8573 */ "ATOMIC_LOAD_SUB_I32_POSTRA\000" |
| 8773 | /* 8600 */ "ATOMIC_LOAD_ADD_I32_POSTRA\000" |
| 8774 | /* 8627 */ "ATOMIC_LOAD_NAND_I32_POSTRA\000" |
| 8775 | /* 8655 */ "ATOMIC_LOAD_AND_I32_POSTRA\000" |
| 8776 | /* 8682 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\000" |
| 8777 | /* 8710 */ "ATOMIC_LOAD_MIN_I32_POSTRA\000" |
| 8778 | /* 8737 */ "ATOMIC_SWAP_I32_POSTRA\000" |
| 8779 | /* 8760 */ "ATOMIC_CMP_SWAP_I32_POSTRA\000" |
| 8780 | /* 8787 */ "ATOMIC_LOAD_XOR_I32_POSTRA\000" |
| 8781 | /* 8814 */ "ATOMIC_LOAD_OR_I32_POSTRA\000" |
| 8782 | /* 8840 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\000" |
| 8783 | /* 8868 */ "ATOMIC_LOAD_MAX_I32_POSTRA\000" |
| 8784 | /* 8895 */ "ATOMIC_LOAD_SUB_I64_POSTRA\000" |
| 8785 | /* 8922 */ "ATOMIC_LOAD_ADD_I64_POSTRA\000" |
| 8786 | /* 8949 */ "ATOMIC_LOAD_NAND_I64_POSTRA\000" |
| 8787 | /* 8977 */ "ATOMIC_LOAD_AND_I64_POSTRA\000" |
| 8788 | /* 9004 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\000" |
| 8789 | /* 9032 */ "ATOMIC_LOAD_MIN_I64_POSTRA\000" |
| 8790 | /* 9059 */ "ATOMIC_SWAP_I64_POSTRA\000" |
| 8791 | /* 9082 */ "ATOMIC_CMP_SWAP_I64_POSTRA\000" |
| 8792 | /* 9109 */ "ATOMIC_LOAD_XOR_I64_POSTRA\000" |
| 8793 | /* 9136 */ "ATOMIC_LOAD_OR_I64_POSTRA\000" |
| 8794 | /* 9162 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\000" |
| 8795 | /* 9190 */ "ATOMIC_LOAD_MAX_I64_POSTRA\000" |
| 8796 | /* 9217 */ "ATOMIC_LOAD_SUB_I16_POSTRA\000" |
| 8797 | /* 9244 */ "ATOMIC_LOAD_ADD_I16_POSTRA\000" |
| 8798 | /* 9271 */ "ATOMIC_LOAD_NAND_I16_POSTRA\000" |
| 8799 | /* 9299 */ "ATOMIC_LOAD_AND_I16_POSTRA\000" |
| 8800 | /* 9326 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\000" |
| 8801 | /* 9354 */ "ATOMIC_LOAD_MIN_I16_POSTRA\000" |
| 8802 | /* 9381 */ "ATOMIC_SWAP_I16_POSTRA\000" |
| 8803 | /* 9404 */ "ATOMIC_CMP_SWAP_I16_POSTRA\000" |
| 8804 | /* 9431 */ "ATOMIC_LOAD_XOR_I16_POSTRA\000" |
| 8805 | /* 9458 */ "ATOMIC_LOAD_OR_I16_POSTRA\000" |
| 8806 | /* 9484 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\000" |
| 8807 | /* 9512 */ "ATOMIC_LOAD_MAX_I16_POSTRA\000" |
| 8808 | /* 9539 */ "ATOMIC_LOAD_SUB_I8_POSTRA\000" |
| 8809 | /* 9565 */ "ATOMIC_LOAD_ADD_I8_POSTRA\000" |
| 8810 | /* 9591 */ "ATOMIC_LOAD_NAND_I8_POSTRA\000" |
| 8811 | /* 9618 */ "ATOMIC_LOAD_AND_I8_POSTRA\000" |
| 8812 | /* 9644 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\000" |
| 8813 | /* 9671 */ "ATOMIC_LOAD_MIN_I8_POSTRA\000" |
| 8814 | /* 9697 */ "ATOMIC_SWAP_I8_POSTRA\000" |
| 8815 | /* 9719 */ "ATOMIC_CMP_SWAP_I8_POSTRA\000" |
| 8816 | /* 9745 */ "ATOMIC_LOAD_XOR_I8_POSTRA\000" |
| 8817 | /* 9771 */ "ATOMIC_LOAD_OR_I8_POSTRA\000" |
| 8818 | /* 9796 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\000" |
| 8819 | /* 9823 */ "ATOMIC_LOAD_MAX_I8_POSTRA\000" |
| 8820 | /* 9849 */ "RetRA\000" |
| 8821 | /* 9855 */ "DLSA\000" |
| 8822 | /* 9860 */ "CFCMSA\000" |
| 8823 | /* 9867 */ "CTCMSA\000" |
| 8824 | /* 9874 */ "CRC32B\000" |
| 8825 | /* 9881 */ "CRC32CB\000" |
| 8826 | /* 9889 */ "SEB\000" |
| 8827 | /* 9893 */ "EHB\000" |
| 8828 | /* 9897 */ "TAILCALLREGHB\000" |
| 8829 | /* 9911 */ "JR_HB\000" |
| 8830 | /* 9917 */ "JALR_HB\000" |
| 8831 | /* 9925 */ "LB\000" |
| 8832 | /* 9928 */ "SHRA_QB\000" |
| 8833 | /* 9936 */ "CMPGDU_LE_QB\000" |
| 8834 | /* 9949 */ "CMPGU_LE_QB\000" |
| 8835 | /* 9961 */ "PseudoCMPU_LE_QB\000" |
| 8836 | /* 9978 */ "SUBUH_QB\000" |
| 8837 | /* 9987 */ "ADDUH_QB\000" |
| 8838 | /* 9996 */ "PseudoPICK_QB\000" |
| 8839 | /* 10010 */ "SHLL_QB\000" |
| 8840 | /* 10018 */ "REPL_QB\000" |
| 8841 | /* 10026 */ "SHRL_QB\000" |
| 8842 | /* 10034 */ "CMPGDU_EQ_QB\000" |
| 8843 | /* 10047 */ "CMPGU_EQ_QB\000" |
| 8844 | /* 10059 */ "PseudoCMPU_EQ_QB\000" |
| 8845 | /* 10076 */ "SHRA_R_QB\000" |
| 8846 | /* 10086 */ "SUBUH_R_QB\000" |
| 8847 | /* 10097 */ "ADDUH_R_QB\000" |
| 8848 | /* 10108 */ "SHRAV_R_QB\000" |
| 8849 | /* 10119 */ "ABSQ_S_QB\000" |
| 8850 | /* 10129 */ "SUBU_S_QB\000" |
| 8851 | /* 10139 */ "ADDU_S_QB\000" |
| 8852 | /* 10149 */ "CMPGDU_LT_QB\000" |
| 8853 | /* 10162 */ "CMPGU_LT_QB\000" |
| 8854 | /* 10174 */ "PseudoCMPU_LT_QB\000" |
| 8855 | /* 10191 */ "SUBU_QB\000" |
| 8856 | /* 10199 */ "ADDU_QB\000" |
| 8857 | /* 10207 */ "SHRAV_QB\000" |
| 8858 | /* 10216 */ "SHLLV_QB\000" |
| 8859 | /* 10225 */ "REPLV_QB\000" |
| 8860 | /* 10234 */ "SHRLV_QB\000" |
| 8861 | /* 10243 */ "RADDU_W_QB\000" |
| 8862 | /* 10254 */ "SB\000" |
| 8863 | /* 10257 */ "MODSUB\000" |
| 8864 | /* 10264 */ "G_FSUB\000" |
| 8865 | /* 10271 */ "G_STRICT_FSUB\000" |
| 8866 | /* 10285 */ "G_ATOMICRMW_FSUB\000" |
| 8867 | /* 10302 */ "PseudoMSUB\000" |
| 8868 | /* 10313 */ "G_SUB\000" |
| 8869 | /* 10319 */ "G_ATOMICRMW_SUB\000" |
| 8870 | /* 10335 */ "SRA_B\000" |
| 8871 | /* 10341 */ "ADD_A_B\000" |
| 8872 | /* 10349 */ "MIN_A_B\000" |
| 8873 | /* 10357 */ "ADDS_A_B\000" |
| 8874 | /* 10366 */ "MAX_A_B\000" |
| 8875 | /* 10374 */ "NLOC_B\000" |
| 8876 | /* 10381 */ "NLZC_B\000" |
| 8877 | /* 10388 */ "SLD_B\000" |
| 8878 | /* 10394 */ "PCKOD_B\000" |
| 8879 | /* 10402 */ "ILVOD_B\000" |
| 8880 | /* 10410 */ "INSVE_B\000" |
| 8881 | /* 10418 */ "VSHF_B\000" |
| 8882 | /* 10425 */ "BNEG_B\000" |
| 8883 | /* 10432 */ "SRAI_B\000" |
| 8884 | /* 10439 */ "SLDI_B\000" |
| 8885 | /* 10446 */ "ANDI_B\000" |
| 8886 | /* 10453 */ "BNEGI_B\000" |
| 8887 | /* 10461 */ "BSELI_B\000" |
| 8888 | /* 10469 */ "SLLI_B\000" |
| 8889 | /* 10476 */ "SRLI_B\000" |
| 8890 | /* 10483 */ "BINSLI_B\000" |
| 8891 | /* 10492 */ "CEQI_B\000" |
| 8892 | /* 10499 */ "SRARI_B\000" |
| 8893 | /* 10507 */ "BCLRI_B\000" |
| 8894 | /* 10515 */ "SRLRI_B\000" |
| 8895 | /* 10523 */ "NORI_B\000" |
| 8896 | /* 10530 */ "XORI_B\000" |
| 8897 | /* 10537 */ "BINSRI_B\000" |
| 8898 | /* 10546 */ "SPLATI_B\000" |
| 8899 | /* 10555 */ "BSETI_B\000" |
| 8900 | /* 10563 */ "SUBVI_B\000" |
| 8901 | /* 10571 */ "ADDVI_B\000" |
| 8902 | /* 10579 */ "BMZI_B\000" |
| 8903 | /* 10586 */ "BMNZI_B\000" |
| 8904 | /* 10594 */ "FILL_B\000" |
| 8905 | /* 10601 */ "SLL_B\000" |
| 8906 | /* 10607 */ "SRL_B\000" |
| 8907 | /* 10613 */ "BINSL_B\000" |
| 8908 | /* 10621 */ "ILVL_B\000" |
| 8909 | /* 10628 */ "CEQ_B\000" |
| 8910 | /* 10634 */ "SRAR_B\000" |
| 8911 | /* 10641 */ "BCLR_B\000" |
| 8912 | /* 10648 */ "SRLR_B\000" |
| 8913 | /* 10655 */ "BINSR_B\000" |
| 8914 | /* 10663 */ "ILVR_B\000" |
| 8915 | /* 10670 */ "ASUB_S_B\000" |
| 8916 | /* 10679 */ "MOD_S_B\000" |
| 8917 | /* 10687 */ "CLE_S_B\000" |
| 8918 | /* 10695 */ "AVE_S_B\000" |
| 8919 | /* 10703 */ "CLEI_S_B\000" |
| 8920 | /* 10712 */ "MINI_S_B\000" |
| 8921 | /* 10721 */ "CLTI_S_B\000" |
| 8922 | /* 10730 */ "MAXI_S_B\000" |
| 8923 | /* 10739 */ "MIN_S_B\000" |
| 8924 | /* 10747 */ "AVER_S_B\000" |
| 8925 | /* 10756 */ "SUBS_S_B\000" |
| 8926 | /* 10765 */ "ADDS_S_B\000" |
| 8927 | /* 10774 */ "SAT_S_B\000" |
| 8928 | /* 10782 */ "CLT_S_B\000" |
| 8929 | /* 10790 */ "SUBSUU_S_B\000" |
| 8930 | /* 10801 */ "DIV_S_B\000" |
| 8931 | /* 10809 */ "MAX_S_B\000" |
| 8932 | /* 10817 */ "COPY_S_B\000" |
| 8933 | /* 10826 */ "SPLAT_B\000" |
| 8934 | /* 10834 */ "BSET_B\000" |
| 8935 | /* 10841 */ "PCNT_B\000" |
| 8936 | /* 10848 */ "INSERT_B\000" |
| 8937 | /* 10857 */ "ST_B\000" |
| 8938 | /* 10862 */ "ASUB_U_B\000" |
| 8939 | /* 10871 */ "MOD_U_B\000" |
| 8940 | /* 10879 */ "CLE_U_B\000" |
| 8941 | /* 10887 */ "AVE_U_B\000" |
| 8942 | /* 10895 */ "CLEI_U_B\000" |
| 8943 | /* 10904 */ "MINI_U_B\000" |
| 8944 | /* 10913 */ "CLTI_U_B\000" |
| 8945 | /* 10922 */ "MAXI_U_B\000" |
| 8946 | /* 10931 */ "MIN_U_B\000" |
| 8947 | /* 10939 */ "AVER_U_B\000" |
| 8948 | /* 10948 */ "SUBS_U_B\000" |
| 8949 | /* 10957 */ "ADDS_U_B\000" |
| 8950 | /* 10966 */ "SUBSUS_U_B\000" |
| 8951 | /* 10977 */ "SAT_U_B\000" |
| 8952 | /* 10985 */ "CLT_U_B\000" |
| 8953 | /* 10993 */ "DIV_U_B\000" |
| 8954 | /* 11001 */ "MAX_U_B\000" |
| 8955 | /* 11009 */ "COPY_U_B\000" |
| 8956 | /* 11018 */ "MSUBV_B\000" |
| 8957 | /* 11026 */ "MADDV_B\000" |
| 8958 | /* 11034 */ "PCKEV_B\000" |
| 8959 | /* 11042 */ "ILVEV_B\000" |
| 8960 | /* 11050 */ "MULV_B\000" |
| 8961 | /* 11057 */ "BZ_B\000" |
| 8962 | /* 11062 */ "BNZ_B\000" |
| 8963 | /* 11068 */ "BC\000" |
| 8964 | /* 11071 */ "BGEC\000" |
| 8965 | /* 11076 */ "BNEC\000" |
| 8966 | /* 11081 */ "JIC\000" |
| 8967 | /* 11085 */ "G_INTRINSIC\000" |
| 8968 | /* 11097 */ "BALC\000" |
| 8969 | /* 11102 */ "JIALC\000" |
| 8970 | /* 11108 */ "BGEZALC\000" |
| 8971 | /* 11116 */ "BLEZALC\000" |
| 8972 | /* 11124 */ "BNEZALC\000" |
| 8973 | /* 11132 */ "BEQZALC\000" |
| 8974 | /* 11140 */ "BGTZALC\000" |
| 8975 | /* 11148 */ "BLTZALC\000" |
| 8976 | /* 11156 */ "ERETNC\000" |
| 8977 | /* 11163 */ "G_FPTRUNC\000" |
| 8978 | /* 11173 */ "G_INTRINSIC_TRUNC\000" |
| 8979 | /* 11191 */ "G_TRUNC\000" |
| 8980 | /* 11199 */ "G_BUILD_VECTOR_TRUNC\000" |
| 8981 | /* 11220 */ "SYNC\000" |
| 8982 | /* 11225 */ "G_DYN_STACKALLOC\000" |
| 8983 | /* 11242 */ "LDPC\000" |
| 8984 | /* 11247 */ "AUIPC\000" |
| 8985 | /* 11253 */ "ALUIPC\000" |
| 8986 | /* 11260 */ "ADDIUPC\000" |
| 8987 | /* 11268 */ "LWUPC\000" |
| 8988 | /* 11274 */ "LWPC\000" |
| 8989 | /* 11279 */ "BEQC\000" |
| 8990 | /* 11284 */ "ADDSC\000" |
| 8991 | /* 11290 */ "BLTC\000" |
| 8992 | /* 11295 */ "BGEUC\000" |
| 8993 | /* 11301 */ "BLTUC\000" |
| 8994 | /* 11307 */ "BNVC\000" |
| 8995 | /* 11312 */ "BOVC\000" |
| 8996 | /* 11317 */ "ADDWC\000" |
| 8997 | /* 11323 */ "BGEZC\000" |
| 8998 | /* 11329 */ "BLEZC\000" |
| 8999 | /* 11335 */ "BNEZC\000" |
| 9000 | /* 11341 */ "BEQZC\000" |
| 9001 | /* 11347 */ "BGTZC\000" |
| 9002 | /* 11353 */ "BLTZC\000" |
| 9003 | /* 11359 */ "CRC32D\000" |
| 9004 | /* 11366 */ "SAAD\000" |
| 9005 | /* 11371 */ "G_FMAD\000" |
| 9006 | /* 11378 */ "G_INDEXED_SEXTLOAD\000" |
| 9007 | /* 11397 */ "G_SEXTLOAD\000" |
| 9008 | /* 11408 */ "G_INDEXED_ZEXTLOAD\000" |
| 9009 | /* 11427 */ "G_ZEXTLOAD\000" |
| 9010 | /* 11438 */ "G_INDEXED_LOAD\000" |
| 9011 | /* 11453 */ "G_LOAD\000" |
| 9012 | /* 11460 */ "CRC32CD\000" |
| 9013 | /* 11468 */ "SCD\000" |
| 9014 | /* 11472 */ "DADD\000" |
| 9015 | /* 11477 */ "G_VECREDUCE_FADD\000" |
| 9016 | /* 11494 */ "G_FADD\000" |
| 9017 | /* 11501 */ "G_VECREDUCE_SEQ_FADD\000" |
| 9018 | /* 11522 */ "G_STRICT_FADD\000" |
| 9019 | /* 11536 */ "G_ATOMICRMW_FADD\000" |
| 9020 | /* 11553 */ "PseudoMADD\000" |
| 9021 | /* 11564 */ "G_VECREDUCE_ADD\000" |
| 9022 | /* 11580 */ "G_ADD\000" |
| 9023 | /* 11586 */ "G_PTR_ADD\000" |
| 9024 | /* 11596 */ "G_ATOMICRMW_ADD\000" |
| 9025 | /* 11612 */ "DSHD\000" |
| 9026 | /* 11617 */ "YIELD\000" |
| 9027 | /* 11623 */ "LLD\000" |
| 9028 | /* 11627 */ "G_ATOMICRMW_NAND\000" |
| 9029 | /* 11644 */ "G_VECREDUCE_AND\000" |
| 9030 | /* 11660 */ "G_AND\000" |
| 9031 | /* 11666 */ "G_ATOMICRMW_AND\000" |
| 9032 | /* 11682 */ "PREPEND\000" |
| 9033 | /* 11690 */ "APPEND\000" |
| 9034 | /* 11697 */ "LIFETIME_END\000" |
| 9035 | /* 11710 */ "G_BRCOND\000" |
| 9036 | /* 11719 */ "G_ATOMICRMW_USUB_COND\000" |
| 9037 | /* 11741 */ "G_LLROUND\000" |
| 9038 | /* 11751 */ "G_LROUND\000" |
| 9039 | /* 11760 */ "G_INTRINSIC_ROUND\000" |
| 9040 | /* 11778 */ "G_INTRINSIC_FPTRUNC_ROUND\000" |
| 9041 | /* 11804 */ "DMOD\000" |
| 9042 | /* 11809 */ "LOAD_STACK_GUARD\000" |
| 9043 | /* 11826 */ "SD\000" |
| 9044 | /* 11829 */ "FLOG2_D\000" |
| 9045 | /* 11837 */ "FEXP2_D\000" |
| 9046 | /* 11845 */ "MINA_D\000" |
| 9047 | /* 11852 */ "SRA_D\000" |
| 9048 | /* 11858 */ "MAXA_D\000" |
| 9049 | /* 11865 */ "ADD_A_D\000" |
| 9050 | /* 11873 */ "FMIN_A_D\000" |
| 9051 | /* 11882 */ "ADDS_A_D\000" |
| 9052 | /* 11891 */ "FMAX_A_D\000" |
| 9053 | /* 11900 */ "FSUB_D\000" |
| 9054 | /* 11907 */ "FMSUB_D\000" |
| 9055 | /* 11915 */ "NLOC_D\000" |
| 9056 | /* 11922 */ "NLZC_D\000" |
| 9057 | /* 11929 */ "FADD_D\000" |
| 9058 | /* 11936 */ "FMADD_D\000" |
| 9059 | /* 11944 */ "SLD_D\000" |
| 9060 | /* 11950 */ "PCKOD_D\000" |
| 9061 | /* 11958 */ "ILVOD_D\000" |
| 9062 | /* 11966 */ "FCLE_D\000" |
| 9063 | /* 11973 */ "FSLE_D\000" |
| 9064 | /* 11980 */ "CMP_SLE_D\000" |
| 9065 | /* 11990 */ "FCULE_D\000" |
| 9066 | /* 11998 */ "FSULE_D\000" |
| 9067 | /* 12006 */ "CMP_SULE_D\000" |
| 9068 | /* 12017 */ "CMP_ULE_D\000" |
| 9069 | /* 12027 */ "CMP_LE_D\000" |
| 9070 | /* 12036 */ "FCNE_D\000" |
| 9071 | /* 12043 */ "FSNE_D\000" |
| 9072 | /* 12050 */ "FCUNE_D\000" |
| 9073 | /* 12058 */ "FSUNE_D\000" |
| 9074 | /* 12066 */ "INSVE_D\000" |
| 9075 | /* 12074 */ "FCAF_D\000" |
| 9076 | /* 12081 */ "FSAF_D\000" |
| 9077 | /* 12088 */ "CMP_SAF_D\000" |
| 9078 | /* 12098 */ "MSUBF_D\000" |
| 9079 | /* 12106 */ "MADDF_D\000" |
| 9080 | /* 12114 */ "VSHF_D\000" |
| 9081 | /* 12121 */ "CMP_F_D\000" |
| 9082 | /* 12129 */ "BNEG_D\000" |
| 9083 | /* 12136 */ "SRAI_D\000" |
| 9084 | /* 12143 */ "SLDI_D\000" |
| 9085 | /* 12150 */ "BNEGI_D\000" |
| 9086 | /* 12158 */ "SLLI_D\000" |
| 9087 | /* 12165 */ "SRLI_D\000" |
| 9088 | /* 12172 */ "BINSLI_D\000" |
| 9089 | /* 12181 */ "CEQI_D\000" |
| 9090 | /* 12188 */ "SRARI_D\000" |
| 9091 | /* 12196 */ "BCLRI_D\000" |
| 9092 | /* 12204 */ "SRLRI_D\000" |
| 9093 | /* 12212 */ "BINSRI_D\000" |
| 9094 | /* 12221 */ "SPLATI_D\000" |
| 9095 | /* 12230 */ "BSETI_D\000" |
| 9096 | /* 12238 */ "SUBVI_D\000" |
| 9097 | /* 12246 */ "ADDVI_D\000" |
| 9098 | /* 12254 */ "SEL_D\000" |
| 9099 | /* 12260 */ "FILL_D\000" |
| 9100 | /* 12267 */ "SLL_D\000" |
| 9101 | /* 12273 */ "FEXUPL_D\000" |
| 9102 | /* 12282 */ "FFQL_D\000" |
| 9103 | /* 12289 */ "SRL_D\000" |
| 9104 | /* 12295 */ "BINSL_D\000" |
| 9105 | /* 12303 */ "FMUL_D\000" |
| 9106 | /* 12310 */ "ILVL_D\000" |
| 9107 | /* 12317 */ "FMIN_D\000" |
| 9108 | /* 12324 */ "FCUN_D\000" |
| 9109 | /* 12331 */ "FSUN_D\000" |
| 9110 | /* 12338 */ "CMP_SUN_D\000" |
| 9111 | /* 12348 */ "CMP_UN_D\000" |
| 9112 | /* 12357 */ "FRCP_D\000" |
| 9113 | /* 12364 */ "FCEQ_D\000" |
| 9114 | /* 12371 */ "FSEQ_D\000" |
| 9115 | /* 12378 */ "CMP_SEQ_D\000" |
| 9116 | /* 12388 */ "FCUEQ_D\000" |
| 9117 | /* 12396 */ "FSUEQ_D\000" |
| 9118 | /* 12404 */ "CMP_SUEQ_D\000" |
| 9119 | /* 12415 */ "CMP_UEQ_D\000" |
| 9120 | /* 12425 */ "CMP_EQ_D\000" |
| 9121 | /* 12434 */ "SRAR_D\000" |
| 9122 | /* 12441 */ "LDR_D\000" |
| 9123 | /* 12447 */ "BCLR_D\000" |
| 9124 | /* 12454 */ "SRLR_D\000" |
| 9125 | /* 12461 */ "FCOR_D\000" |
| 9126 | /* 12468 */ "FSOR_D\000" |
| 9127 | /* 12475 */ "FEXUPR_D\000" |
| 9128 | /* 12484 */ "FFQR_D\000" |
| 9129 | /* 12491 */ "BINSR_D\000" |
| 9130 | /* 12499 */ "STR_D\000" |
| 9131 | /* 12505 */ "ILVR_D\000" |
| 9132 | /* 12512 */ "FABS_D\000" |
| 9133 | /* 12519 */ "FCLASS_D\000" |
| 9134 | /* 12528 */ "ASUB_S_D\000" |
| 9135 | /* 12537 */ "HSUB_S_D\000" |
| 9136 | /* 12546 */ "DPSUB_S_D\000" |
| 9137 | /* 12556 */ "FTRUNC_S_D\000" |
| 9138 | /* 12567 */ "HADD_S_D\000" |
| 9139 | /* 12576 */ "DPADD_S_D\000" |
| 9140 | /* 12586 */ "MOD_S_D\000" |
| 9141 | /* 12594 */ "CLE_S_D\000" |
| 9142 | /* 12602 */ "AVE_S_D\000" |
| 9143 | /* 12610 */ "CLEI_S_D\000" |
| 9144 | /* 12619 */ "MINI_S_D\000" |
| 9145 | /* 12628 */ "CLTI_S_D\000" |
| 9146 | /* 12637 */ "MAXI_S_D\000" |
| 9147 | /* 12646 */ "MIN_S_D\000" |
| 9148 | /* 12654 */ "DOTP_S_D\000" |
| 9149 | /* 12663 */ "AVER_S_D\000" |
| 9150 | /* 12672 */ "SUBS_S_D\000" |
| 9151 | /* 12681 */ "ADDS_S_D\000" |
| 9152 | /* 12690 */ "SAT_S_D\000" |
| 9153 | /* 12698 */ "CLT_S_D\000" |
| 9154 | /* 12706 */ "FFINT_S_D\000" |
| 9155 | /* 12716 */ "FTINT_S_D\000" |
| 9156 | /* 12726 */ "SUBSUU_S_D\000" |
| 9157 | /* 12737 */ "DIV_S_D\000" |
| 9158 | /* 12745 */ "MAX_S_D\000" |
| 9159 | /* 12753 */ "COPY_S_D\000" |
| 9160 | /* 12762 */ "SPLAT_D\000" |
| 9161 | /* 12770 */ "BSET_D\000" |
| 9162 | /* 12777 */ "FCLT_D\000" |
| 9163 | /* 12784 */ "FSLT_D\000" |
| 9164 | /* 12791 */ "CMP_SLT_D\000" |
| 9165 | /* 12801 */ "FCULT_D\000" |
| 9166 | /* 12809 */ "FSULT_D\000" |
| 9167 | /* 12817 */ "CMP_SULT_D\000" |
| 9168 | /* 12828 */ "CMP_ULT_D\000" |
| 9169 | /* 12838 */ "CMP_LT_D\000" |
| 9170 | /* 12847 */ "PCNT_D\000" |
| 9171 | /* 12854 */ "FRINT_D\000" |
| 9172 | /* 12862 */ "INSERT_D\000" |
| 9173 | /* 12871 */ "FSQRT_D\000" |
| 9174 | /* 12879 */ "FRSQRT_D\000" |
| 9175 | /* 12888 */ "ST_D\000" |
| 9176 | /* 12893 */ "ASUB_U_D\000" |
| 9177 | /* 12902 */ "HSUB_U_D\000" |
| 9178 | /* 12911 */ "DPSUB_U_D\000" |
| 9179 | /* 12921 */ "FTRUNC_U_D\000" |
| 9180 | /* 12932 */ "HADD_U_D\000" |
| 9181 | /* 12941 */ "DPADD_U_D\000" |
| 9182 | /* 12951 */ "MOD_U_D\000" |
| 9183 | /* 12959 */ "CLE_U_D\000" |
| 9184 | /* 12967 */ "AVE_U_D\000" |
| 9185 | /* 12975 */ "CLEI_U_D\000" |
| 9186 | /* 12984 */ "MINI_U_D\000" |
| 9187 | /* 12993 */ "CLTI_U_D\000" |
| 9188 | /* 13002 */ "MAXI_U_D\000" |
| 9189 | /* 13011 */ "MIN_U_D\000" |
| 9190 | /* 13019 */ "DOTP_U_D\000" |
| 9191 | /* 13028 */ "AVER_U_D\000" |
| 9192 | /* 13037 */ "SUBS_U_D\000" |
| 9193 | /* 13046 */ "ADDS_U_D\000" |
| 9194 | /* 13055 */ "SUBSUS_U_D\000" |
| 9195 | /* 13066 */ "SAT_U_D\000" |
| 9196 | /* 13074 */ "CLT_U_D\000" |
| 9197 | /* 13082 */ "FFINT_U_D\000" |
| 9198 | /* 13092 */ "FTINT_U_D\000" |
| 9199 | /* 13102 */ "DIV_U_D\000" |
| 9200 | /* 13110 */ "MAX_U_D\000" |
| 9201 | /* 13118 */ "MSUBV_D\000" |
| 9202 | /* 13126 */ "MADDV_D\000" |
| 9203 | /* 13134 */ "PCKEV_D\000" |
| 9204 | /* 13142 */ "ILVEV_D\000" |
| 9205 | /* 13150 */ "FDIV_D\000" |
| 9206 | /* 13157 */ "MULV_D\000" |
| 9207 | /* 13164 */ "PseudoTRUNC_W_D\000" |
| 9208 | /* 13180 */ "FMAX_D\000" |
| 9209 | /* 13187 */ "BZ_D\000" |
| 9210 | /* 13192 */ "SELNEZ_D\000" |
| 9211 | /* 13201 */ "BNZ_D\000" |
| 9212 | /* 13207 */ "SELEQZ_D\000" |
| 9213 | /* 13216 */ "LBE\000" |
| 9214 | /* 13220 */ "PSEUDO_PROBE\000" |
| 9215 | /* 13233 */ "SBE\000" |
| 9216 | /* 13237 */ "G_SSUBE\000" |
| 9217 | /* 13245 */ "G_USUBE\000" |
| 9218 | /* 13253 */ "G_FENCE\000" |
| 9219 | /* 13261 */ "ARITH_FENCE\000" |
| 9220 | /* 13273 */ "REG_SEQUENCE\000" |
| 9221 | /* 13286 */ "SCE\000" |
| 9222 | /* 13290 */ "G_SADDE\000" |
| 9223 | /* 13298 */ "G_UADDE\000" |
| 9224 | /* 13306 */ "G_GET_FPMODE\000" |
| 9225 | /* 13319 */ "G_RESET_FPMODE\000" |
| 9226 | /* 13334 */ "G_SET_FPMODE\000" |
| 9227 | /* 13347 */ "G_FMINNUM_IEEE\000" |
| 9228 | /* 13362 */ "G_FMAXNUM_IEEE\000" |
| 9229 | /* 13377 */ "CACHEE\000" |
| 9230 | /* 13384 */ "PREFE\000" |
| 9231 | /* 13390 */ "BGE\000" |
| 9232 | /* 13394 */ "SGE\000" |
| 9233 | /* 13398 */ "TGE\000" |
| 9234 | /* 13402 */ "CACHE\000" |
| 9235 | /* 13408 */ "LHE\000" |
| 9236 | /* 13412 */ "SHE\000" |
| 9237 | /* 13416 */ "SIGRIE\000" |
| 9238 | /* 13423 */ "G_VSCALE\000" |
| 9239 | /* 13432 */ "G_JUMP_TABLE\000" |
| 9240 | /* 13445 */ "BUNDLE\000" |
| 9241 | /* 13452 */ "LLE\000" |
| 9242 | /* 13456 */ "SLE\000" |
| 9243 | /* 13460 */ "LWLE\000" |
| 9244 | /* 13465 */ "SWLE\000" |
| 9245 | /* 13470 */ "BNE\000" |
| 9246 | /* 13474 */ "G_MEMCPY_INLINE\000" |
| 9247 | /* 13490 */ "RELOC_NONE\000" |
| 9248 | /* 13501 */ "SNE\000" |
| 9249 | /* 13505 */ "TNE\000" |
| 9250 | /* 13509 */ "LOCAL_ESCAPE\000" |
| 9251 | /* 13522 */ "DVPE\000" |
| 9252 | /* 13527 */ "EVPE\000" |
| 9253 | /* 13532 */ "G_STACKRESTORE\000" |
| 9254 | /* 13547 */ "G_INDEXED_STORE\000" |
| 9255 | /* 13563 */ "G_STORE\000" |
| 9256 | /* 13571 */ "LWRE\000" |
| 9257 | /* 13576 */ "SWRE\000" |
| 9258 | /* 13581 */ "G_BITREVERSE\000" |
| 9259 | /* 13594 */ "PAUSE\000" |
| 9260 | /* 13600 */ "FAKE_USE\000" |
| 9261 | /* 13609 */ "DBG_VALUE\000" |
| 9262 | /* 13619 */ "G_GLOBAL_VALUE\000" |
| 9263 | /* 13634 */ "G_PTRAUTH_GLOBAL_VALUE\000" |
| 9264 | /* 13657 */ "CONVERGENCECTRL_GLUE\000" |
| 9265 | /* 13678 */ "G_STACKSAVE\000" |
| 9266 | /* 13690 */ "G_MEMMOVE\000" |
| 9267 | /* 13700 */ "LWE\000" |
| 9268 | /* 13704 */ "SWE\000" |
| 9269 | /* 13708 */ "G_FREEZE\000" |
| 9270 | /* 13717 */ "G_FCANONICALIZE\000" |
| 9271 | /* 13733 */ "LBuE\000" |
| 9272 | /* 13738 */ "LHuE\000" |
| 9273 | /* 13743 */ "BC1F\000" |
| 9274 | /* 13748 */ "G_FMODF\000" |
| 9275 | /* 13756 */ "G_CTLZ_ZERO_UNDEF\000" |
| 9276 | /* 13774 */ "G_CTTZ_ZERO_UNDEF\000" |
| 9277 | /* 13792 */ "INIT_UNDEF\000" |
| 9278 | /* 13803 */ "G_IMPLICIT_DEF\000" |
| 9279 | /* 13818 */ "PREF\000" |
| 9280 | /* 13823 */ "DBG_INSTR_REF\000" |
| 9281 | /* 13837 */ "TLBINVF\000" |
| 9282 | /* 13845 */ "TLBGINVF\000" |
| 9283 | /* 13854 */ "G_FNEG\000" |
| 9284 | /* 13861 */ "TAILCALLHB64R6REG\000" |
| 9285 | /* 13879 */ "TAILCALL64R6REG\000" |
| 9286 | /* 13895 */ "TAILCALLHBR6REG\000" |
| 9287 | /* 13911 */ "TAILCALLR6REG\000" |
| 9288 | /* 13925 */ "EXTRACT_SUBREG\000" |
| 9289 | /* 13940 */ "INSERT_SUBREG\000" |
| 9290 | /* 13954 */ "TAILCALLREG\000" |
| 9291 | /* 13966 */ "G_SEXT_INREG\000" |
| 9292 | /* 13979 */ "SUBREG_TO_REG\000" |
| 9293 | /* 13993 */ "G_ATOMIC_CMPXCHG\000" |
| 9294 | /* 14010 */ "G_ATOMICRMW_XCHG\000" |
| 9295 | /* 14027 */ "G_GET_ROUNDING\000" |
| 9296 | /* 14042 */ "G_SET_ROUNDING\000" |
| 9297 | /* 14057 */ "G_FLOG\000" |
| 9298 | /* 14064 */ "G_VAARG\000" |
| 9299 | /* 14072 */ "PREALLOCATED_ARG\000" |
| 9300 | /* 14089 */ "CRC32H\000" |
| 9301 | /* 14096 */ "DSBH\000" |
| 9302 | /* 14101 */ "WSBH\000" |
| 9303 | /* 14106 */ "CRC32CH\000" |
| 9304 | /* 14114 */ "G_PREFETCH\000" |
| 9305 | /* 14125 */ "SEH\000" |
| 9306 | /* 14129 */ "G_SMULH\000" |
| 9307 | /* 14137 */ "G_UMULH\000" |
| 9308 | /* 14145 */ "G_FTANH\000" |
| 9309 | /* 14153 */ "G_FSINH\000" |
| 9310 | /* 14161 */ "SHRA_PH\000" |
| 9311 | /* 14169 */ "PRECRQ_QB_PH\000" |
| 9312 | /* 14182 */ "PRECR_QB_PH\000" |
| 9313 | /* 14194 */ "PRECRQU_S_QB_PH\000" |
| 9314 | /* 14210 */ "PseudoCMP_LE_PH\000" |
| 9315 | /* 14226 */ "SUBQH_PH\000" |
| 9316 | /* 14235 */ "ADDQH_PH\000" |
| 9317 | /* 14244 */ "PseudoPICK_PH\000" |
| 9318 | /* 14258 */ "SHLL_PH\000" |
| 9319 | /* 14266 */ "REPL_PH\000" |
| 9320 | /* 14274 */ "SHRL_PH\000" |
| 9321 | /* 14282 */ "PACKRL_PH\000" |
| 9322 | /* 14292 */ "MUL_PH\000" |
| 9323 | /* 14299 */ "SUBQ_PH\000" |
| 9324 | /* 14307 */ "ADDQ_PH\000" |
| 9325 | /* 14315 */ "PseudoCMP_EQ_PH\000" |
| 9326 | /* 14331 */ "SHRA_R_PH\000" |
| 9327 | /* 14341 */ "SUBQH_R_PH\000" |
| 9328 | /* 14352 */ "ADDQH_R_PH\000" |
| 9329 | /* 14363 */ "SHRAV_R_PH\000" |
| 9330 | /* 14374 */ "MULQ_RS_PH\000" |
| 9331 | /* 14385 */ "SHLL_S_PH\000" |
| 9332 | /* 14395 */ "MUL_S_PH\000" |
| 9333 | /* 14404 */ "SUBQ_S_PH\000" |
| 9334 | /* 14414 */ "ADDQ_S_PH\000" |
| 9335 | /* 14424 */ "MULQ_S_PH\000" |
| 9336 | /* 14434 */ "ABSQ_S_PH\000" |
| 9337 | /* 14444 */ "SUBU_S_PH\000" |
| 9338 | /* 14454 */ "ADDU_S_PH\000" |
| 9339 | /* 14464 */ "SHLLV_S_PH\000" |
| 9340 | /* 14475 */ "PseudoCMP_LT_PH\000" |
| 9341 | /* 14491 */ "SUBU_PH\000" |
| 9342 | /* 14499 */ "ADDU_PH\000" |
| 9343 | /* 14507 */ "SHRAV_PH\000" |
| 9344 | /* 14516 */ "SHLLV_PH\000" |
| 9345 | /* 14525 */ "REPLV_PH\000" |
| 9346 | /* 14534 */ "SHRLV_PH\000" |
| 9347 | /* 14543 */ "DPA_W_PH\000" |
| 9348 | /* 14552 */ "MULSA_W_PH\000" |
| 9349 | /* 14563 */ "DPAQX_SA_W_PH\000" |
| 9350 | /* 14577 */ "DPSQX_SA_W_PH\000" |
| 9351 | /* 14591 */ "DPS_W_PH\000" |
| 9352 | /* 14600 */ "DPAQ_S_W_PH\000" |
| 9353 | /* 14612 */ "MULSAQ_S_W_PH\000" |
| 9354 | /* 14626 */ "DPSQ_S_W_PH\000" |
| 9355 | /* 14638 */ "DPAQX_S_W_PH\000" |
| 9356 | /* 14651 */ "DPSQX_S_W_PH\000" |
| 9357 | /* 14664 */ "DPAX_W_PH\000" |
| 9358 | /* 14674 */ "DPSX_W_PH\000" |
| 9359 | /* 14684 */ "G_FCOSH\000" |
| 9360 | /* 14692 */ "DMUH\000" |
| 9361 | /* 14697 */ "SRA_H\000" |
| 9362 | /* 14703 */ "ADD_A_H\000" |
| 9363 | /* 14711 */ "MIN_A_H\000" |
| 9364 | /* 14719 */ "ADDS_A_H\000" |
| 9365 | /* 14728 */ "MAX_A_H\000" |
| 9366 | /* 14736 */ "NLOC_H\000" |
| 9367 | /* 14743 */ "NLZC_H\000" |
| 9368 | /* 14750 */ "SLD_H\000" |
| 9369 | /* 14756 */ "PCKOD_H\000" |
| 9370 | /* 14764 */ "ILVOD_H\000" |
| 9371 | /* 14772 */ "INSVE_H\000" |
| 9372 | /* 14780 */ "VSHF_H\000" |
| 9373 | /* 14787 */ "BNEG_H\000" |
| 9374 | /* 14794 */ "SRAI_H\000" |
| 9375 | /* 14801 */ "SLDI_H\000" |
| 9376 | /* 14808 */ "BNEGI_H\000" |
| 9377 | /* 14816 */ "SLLI_H\000" |
| 9378 | /* 14823 */ "SRLI_H\000" |
| 9379 | /* 14830 */ "BINSLI_H\000" |
| 9380 | /* 14839 */ "CEQI_H\000" |
| 9381 | /* 14846 */ "SRARI_H\000" |
| 9382 | /* 14854 */ "BCLRI_H\000" |
| 9383 | /* 14862 */ "SRLRI_H\000" |
| 9384 | /* 14870 */ "BINSRI_H\000" |
| 9385 | /* 14879 */ "SPLATI_H\000" |
| 9386 | /* 14888 */ "BSETI_H\000" |
| 9387 | /* 14896 */ "SUBVI_H\000" |
| 9388 | /* 14904 */ "ADDVI_H\000" |
| 9389 | /* 14912 */ "FILL_H\000" |
| 9390 | /* 14919 */ "SLL_H\000" |
| 9391 | /* 14925 */ "SRL_H\000" |
| 9392 | /* 14931 */ "BINSL_H\000" |
| 9393 | /* 14939 */ "ILVL_H\000" |
| 9394 | /* 14946 */ "FEXDO_H\000" |
| 9395 | /* 14954 */ "CEQ_H\000" |
| 9396 | /* 14960 */ "FTQ_H\000" |
| 9397 | /* 14966 */ "MSUB_Q_H\000" |
| 9398 | /* 14975 */ "MADD_Q_H\000" |
| 9399 | /* 14984 */ "MUL_Q_H\000" |
| 9400 | /* 14992 */ "MSUBR_Q_H\000" |
| 9401 | /* 15002 */ "MADDR_Q_H\000" |
| 9402 | /* 15012 */ "MULR_Q_H\000" |
| 9403 | /* 15021 */ "SRAR_H\000" |
| 9404 | /* 15028 */ "BCLR_H\000" |
| 9405 | /* 15035 */ "SRLR_H\000" |
| 9406 | /* 15042 */ "BINSR_H\000" |
| 9407 | /* 15050 */ "ILVR_H\000" |
| 9408 | /* 15057 */ "ASUB_S_H\000" |
| 9409 | /* 15066 */ "HSUB_S_H\000" |
| 9410 | /* 15075 */ "DPSUB_S_H\000" |
| 9411 | /* 15085 */ "HADD_S_H\000" |
| 9412 | /* 15094 */ "DPADD_S_H\000" |
| 9413 | /* 15104 */ "MOD_S_H\000" |
| 9414 | /* 15112 */ "CLE_S_H\000" |
| 9415 | /* 15120 */ "AVE_S_H\000" |
| 9416 | /* 15128 */ "CLEI_S_H\000" |
| 9417 | /* 15137 */ "MINI_S_H\000" |
| 9418 | /* 15146 */ "CLTI_S_H\000" |
| 9419 | /* 15155 */ "MAXI_S_H\000" |
| 9420 | /* 15164 */ "MIN_S_H\000" |
| 9421 | /* 15172 */ "DOTP_S_H\000" |
| 9422 | /* 15181 */ "AVER_S_H\000" |
| 9423 | /* 15190 */ "EXTR_S_H\000" |
| 9424 | /* 15199 */ "SUBS_S_H\000" |
| 9425 | /* 15208 */ "ADDS_S_H\000" |
| 9426 | /* 15217 */ "SAT_S_H\000" |
| 9427 | /* 15225 */ "CLT_S_H\000" |
| 9428 | /* 15233 */ "SUBSUU_S_H\000" |
| 9429 | /* 15244 */ "DIV_S_H\000" |
| 9430 | /* 15252 */ "EXTRV_S_H\000" |
| 9431 | /* 15262 */ "MAX_S_H\000" |
| 9432 | /* 15270 */ "COPY_S_H\000" |
| 9433 | /* 15279 */ "SPLAT_H\000" |
| 9434 | /* 15287 */ "BSET_H\000" |
| 9435 | /* 15294 */ "PCNT_H\000" |
| 9436 | /* 15301 */ "INSERT_H\000" |
| 9437 | /* 15310 */ "ST_H\000" |
| 9438 | /* 15315 */ "ASUB_U_H\000" |
| 9439 | /* 15324 */ "HSUB_U_H\000" |
| 9440 | /* 15333 */ "DPSUB_U_H\000" |
| 9441 | /* 15343 */ "HADD_U_H\000" |
| 9442 | /* 15352 */ "DPADD_U_H\000" |
| 9443 | /* 15362 */ "MOD_U_H\000" |
| 9444 | /* 15370 */ "CLE_U_H\000" |
| 9445 | /* 15378 */ "AVE_U_H\000" |
| 9446 | /* 15386 */ "CLEI_U_H\000" |
| 9447 | /* 15395 */ "MINI_U_H\000" |
| 9448 | /* 15404 */ "CLTI_U_H\000" |
| 9449 | /* 15413 */ "MAXI_U_H\000" |
| 9450 | /* 15422 */ "MIN_U_H\000" |
| 9451 | /* 15430 */ "DOTP_U_H\000" |
| 9452 | /* 15439 */ "AVER_U_H\000" |
| 9453 | /* 15448 */ "SUBS_U_H\000" |
| 9454 | /* 15457 */ "ADDS_U_H\000" |
| 9455 | /* 15466 */ "SUBSUS_U_H\000" |
| 9456 | /* 15477 */ "SAT_U_H\000" |
| 9457 | /* 15485 */ "CLT_U_H\000" |
| 9458 | /* 15493 */ "DIV_U_H\000" |
| 9459 | /* 15501 */ "MAX_U_H\000" |
| 9460 | /* 15509 */ "COPY_U_H\000" |
| 9461 | /* 15518 */ "MSUBV_H\000" |
| 9462 | /* 15526 */ "MADDV_H\000" |
| 9463 | /* 15534 */ "PCKEV_H\000" |
| 9464 | /* 15542 */ "ILVEV_H\000" |
| 9465 | /* 15550 */ "MULV_H\000" |
| 9466 | /* 15557 */ "BZ_H\000" |
| 9467 | /* 15562 */ "BNZ_H\000" |
| 9468 | /* 15568 */ "SYNCI\000" |
| 9469 | /* 15574 */ "DI\000" |
| 9470 | /* 15577 */ "TGEI\000" |
| 9471 | /* 15582 */ "TNEI\000" |
| 9472 | /* 15587 */ "DAHI\000" |
| 9473 | /* 15592 */ "PseudoMFHI\000" |
| 9474 | /* 15603 */ "PseudoMTLOHI\000" |
| 9475 | /* 15616 */ "DBG_PHI\000" |
| 9476 | /* 15624 */ "MFTHI\000" |
| 9477 | /* 15630 */ "MTHI\000" |
| 9478 | /* 15635 */ "MTTHI\000" |
| 9479 | /* 15641 */ "TEQI\000" |
| 9480 | /* 15646 */ "G_FPTOSI\000" |
| 9481 | /* 15655 */ "DATI\000" |
| 9482 | /* 15660 */ "TLTI\000" |
| 9483 | /* 15665 */ "DAUI\000" |
| 9484 | /* 15670 */ "G_FPTOUI\000" |
| 9485 | /* 15679 */ "GINVI\000" |
| 9486 | /* 15685 */ "TLBWI\000" |
| 9487 | /* 15691 */ "TLBGWI\000" |
| 9488 | /* 15698 */ "G_FPOWI\000" |
| 9489 | /* 15706 */ "MOVN_I64_I\000" |
| 9490 | /* 15717 */ "MOVZ_I64_I\000" |
| 9491 | /* 15728 */ "MOVF_I\000" |
| 9492 | /* 15735 */ "PseudoSELECTFP_F_I\000" |
| 9493 | /* 15754 */ "MOVN_I_I\000" |
| 9494 | /* 15763 */ "MOVZ_I_I\000" |
| 9495 | /* 15772 */ "PseudoD_SELECT_I\000" |
| 9496 | /* 15789 */ "PseudoSELECT_I\000" |
| 9497 | /* 15804 */ "MOVT_I\000" |
| 9498 | /* 15811 */ "PseudoSELECTFP_T_I\000" |
| 9499 | /* 15830 */ "J\000" |
| 9500 | /* 15832 */ "BREAK\000" |
| 9501 | /* 15838 */ "FORK\000" |
| 9502 | /* 15843 */ "COPY_LANEMASK\000" |
| 9503 | /* 15857 */ "G_PTRMASK\000" |
| 9504 | /* 15867 */ "BAL\000" |
| 9505 | /* 15871 */ "JAL\000" |
| 9506 | /* 15875 */ "NAL\000" |
| 9507 | /* 15879 */ "BGEZAL\000" |
| 9508 | /* 15886 */ "BLTZAL\000" |
| 9509 | /* 15893 */ "MULEU_S_PH_QBL\000" |
| 9510 | /* 15908 */ "PRECEU_PH_QBL\000" |
| 9511 | /* 15922 */ "PRECEQU_PH_QBL\000" |
| 9512 | /* 15937 */ "DPAU_H_QBL\000" |
| 9513 | /* 15948 */ "DPSU_H_QBL\000" |
| 9514 | /* 15959 */ "LDL\000" |
| 9515 | /* 15963 */ "SDL\000" |
| 9516 | /* 15967 */ "GC_LABEL\000" |
| 9517 | /* 15976 */ "DBG_LABEL\000" |
| 9518 | /* 15986 */ "EH_LABEL\000" |
| 9519 | /* 15995 */ "ANNOTATION_LABEL\000" |
| 9520 | /* 16012 */ "BGEL\000" |
| 9521 | /* 16017 */ "BLEL\000" |
| 9522 | /* 16022 */ "BNEL\000" |
| 9523 | /* 16027 */ "ICALL_BRANCH_FUNNEL\000" |
| 9524 | /* 16047 */ "BC1FL\000" |
| 9525 | /* 16053 */ "MAQ_SA_W_PHL\000" |
| 9526 | /* 16066 */ "PRECEQ_W_PHL\000" |
| 9527 | /* 16079 */ "MAQ_S_W_PHL\000" |
| 9528 | /* 16091 */ "MULEQ_S_W_PHL\000" |
| 9529 | /* 16105 */ "G_FSHL\000" |
| 9530 | /* 16112 */ "G_SHL\000" |
| 9531 | /* 16118 */ "G_FCEIL\000" |
| 9532 | /* 16126 */ "G_SAVGCEIL\000" |
| 9533 | /* 16137 */ "G_UAVGCEIL\000" |
| 9534 | /* 16148 */ "TAILCALL\000" |
| 9535 | /* 16157 */ "HYPCALL\000" |
| 9536 | /* 16165 */ "SYSCALL\000" |
| 9537 | /* 16173 */ "PATCHABLE_TAIL_CALL\000" |
| 9538 | /* 16193 */ "PATCHABLE_TYPED_EVENT_CALL\000" |
| 9539 | /* 16220 */ "PATCHABLE_EVENT_CALL\000" |
| 9540 | /* 16241 */ "FENTRY_CALL\000" |
| 9541 | /* 16253 */ "BGEZALL\000" |
| 9542 | /* 16261 */ "BLTZALL\000" |
| 9543 | /* 16269 */ "KILL\000" |
| 9544 | /* 16274 */ "DSLL\000" |
| 9545 | /* 16279 */ "G_CONSTANT_POOL\000" |
| 9546 | /* 16295 */ "DROL\000" |
| 9547 | /* 16300 */ "BEQL\000" |
| 9548 | /* 16305 */ "DSRL\000" |
| 9549 | /* 16310 */ "BC1TL\000" |
| 9550 | /* 16316 */ "BGTL\000" |
| 9551 | /* 16321 */ "BLTL\000" |
| 9552 | /* 16326 */ "G_ROTL\000" |
| 9553 | /* 16333 */ "BGEUL\000" |
| 9554 | /* 16339 */ "BLEUL\000" |
| 9555 | /* 16345 */ "DMUL\000" |
| 9556 | /* 16350 */ "G_VECREDUCE_FMUL\000" |
| 9557 | /* 16367 */ "G_FMUL\000" |
| 9558 | /* 16374 */ "G_VECREDUCE_SEQ_FMUL\000" |
| 9559 | /* 16395 */ "G_STRICT_FMUL\000" |
| 9560 | /* 16409 */ "G_VECREDUCE_MUL\000" |
| 9561 | /* 16425 */ "G_MUL\000" |
| 9562 | /* 16431 */ "BGTUL\000" |
| 9563 | /* 16437 */ "BLTUL\000" |
| 9564 | /* 16443 */ "LWL\000" |
| 9565 | /* 16447 */ "SWL\000" |
| 9566 | /* 16451 */ "BGEZL\000" |
| 9567 | /* 16457 */ "BLEZL\000" |
| 9568 | /* 16463 */ "BGTZL\000" |
| 9569 | /* 16469 */ "BLTZL\000" |
| 9570 | /* 16475 */ "PseudoCVT_D64_L\000" |
| 9571 | /* 16491 */ "PseudoCVT_S_L\000" |
| 9572 | /* 16505 */ "G_FREM\000" |
| 9573 | /* 16512 */ "G_STRICT_FREM\000" |
| 9574 | /* 16526 */ "G_SREM\000" |
| 9575 | /* 16533 */ "G_UREM\000" |
| 9576 | /* 16540 */ "G_SDIVREM\000" |
| 9577 | /* 16550 */ "G_UDIVREM\000" |
| 9578 | /* 16560 */ "MFGC0_MM\000" |
| 9579 | /* 16569 */ "MFHGC0_MM\000" |
| 9580 | /* 16579 */ "MTHGC0_MM\000" |
| 9581 | /* 16589 */ "MTGC0_MM\000" |
| 9582 | /* 16598 */ "CFC1_MM\000" |
| 9583 | /* 16606 */ "MFC1_MM\000" |
| 9584 | /* 16614 */ "CTC1_MM\000" |
| 9585 | /* 16622 */ "MTC1_MM\000" |
| 9586 | /* 16630 */ "LWC1_MM\000" |
| 9587 | /* 16638 */ "SWC1_MM\000" |
| 9588 | /* 16646 */ "LUXC1_MM\000" |
| 9589 | /* 16655 */ "SUXC1_MM\000" |
| 9590 | /* 16664 */ "LWXC1_MM\000" |
| 9591 | /* 16673 */ "SWXC1_MM\000" |
| 9592 | /* 16682 */ "MFHC1_D32_MM\000" |
| 9593 | /* 16695 */ "MTHC1_D32_MM\000" |
| 9594 | /* 16708 */ "FSUB_D32_MM\000" |
| 9595 | /* 16720 */ "NMSUB_D32_MM\000" |
| 9596 | /* 16733 */ "FADD_D32_MM\000" |
| 9597 | /* 16745 */ "NMADD_D32_MM\000" |
| 9598 | /* 16758 */ "C_NGE_D32_MM\000" |
| 9599 | /* 16771 */ "C_NGLE_D32_MM\000" |
| 9600 | /* 16785 */ "C_OLE_D32_MM\000" |
| 9601 | /* 16798 */ "C_ULE_D32_MM\000" |
| 9602 | /* 16811 */ "C_LE_D32_MM\000" |
| 9603 | /* 16823 */ "C_SF_D32_MM\000" |
| 9604 | /* 16835 */ "MOVF_D32_MM\000" |
| 9605 | /* 16847 */ "C_F_D32_MM\000" |
| 9606 | /* 16858 */ "FNEG_D32_MM\000" |
| 9607 | /* 16870 */ "MOVN_I_D32_MM\000" |
| 9608 | /* 16884 */ "MOVZ_I_D32_MM\000" |
| 9609 | /* 16898 */ "C_NGL_D32_MM\000" |
| 9610 | /* 16911 */ "FMUL_D32_MM\000" |
| 9611 | /* 16923 */ "C_UN_D32_MM\000" |
| 9612 | /* 16935 */ "RECIP_D32_MM\000" |
| 9613 | /* 16948 */ "FCMP_D32_MM\000" |
| 9614 | /* 16960 */ "C_SEQ_D32_MM\000" |
| 9615 | /* 16973 */ "C_UEQ_D32_MM\000" |
| 9616 | /* 16986 */ "C_EQ_D32_MM\000" |
| 9617 | /* 16998 */ "FABS_D32_MM\000" |
| 9618 | /* 17010 */ "CVT_S_D32_MM\000" |
| 9619 | /* 17023 */ "C_NGT_D32_MM\000" |
| 9620 | /* 17036 */ "C_OLT_D32_MM\000" |
| 9621 | /* 17049 */ "C_ULT_D32_MM\000" |
| 9622 | /* 17062 */ "C_LT_D32_MM\000" |
| 9623 | /* 17074 */ "FSQRT_D32_MM\000" |
| 9624 | /* 17087 */ "RSQRT_D32_MM\000" |
| 9625 | /* 17100 */ "MOVT_D32_MM\000" |
| 9626 | /* 17112 */ "FDIV_D32_MM\000" |
| 9627 | /* 17124 */ "FMOV_D32_MM\000" |
| 9628 | /* 17136 */ "CVT_W_D32_MM\000" |
| 9629 | /* 17149 */ "BPOSGE32_MM\000" |
| 9630 | /* 17161 */ "LWM32_MM\000" |
| 9631 | /* 17170 */ "SWM32_MM\000" |
| 9632 | /* 17179 */ "FCMP_S32_MM\000" |
| 9633 | /* 17191 */ "CFC2_MM\000" |
| 9634 | /* 17199 */ "CTC2_MM\000" |
| 9635 | /* 17207 */ "ADDIUR2_MM\000" |
| 9636 | /* 17218 */ "MFHC1_D64_MM\000" |
| 9637 | /* 17231 */ "MTHC1_D64_MM\000" |
| 9638 | /* 17244 */ "MTC1_D64_MM\000" |
| 9639 | /* 17256 */ "FSUB_D64_MM\000" |
| 9640 | /* 17268 */ "FADD_D64_MM\000" |
| 9641 | /* 17280 */ "C_NGE_D64_MM\000" |
| 9642 | /* 17293 */ "C_NGLE_D64_MM\000" |
| 9643 | /* 17307 */ "C_OLE_D64_MM\000" |
| 9644 | /* 17320 */ "C_ULE_D64_MM\000" |
| 9645 | /* 17333 */ "C_LE_D64_MM\000" |
| 9646 | /* 17345 */ "C_SF_D64_MM\000" |
| 9647 | /* 17357 */ "C_F_D64_MM\000" |
| 9648 | /* 17368 */ "FNEG_D64_MM\000" |
| 9649 | /* 17380 */ "C_NGL_D64_MM\000" |
| 9650 | /* 17393 */ "FMUL_D64_MM\000" |
| 9651 | /* 17405 */ "CVT_L_D64_MM\000" |
| 9652 | /* 17418 */ "C_UN_D64_MM\000" |
| 9653 | /* 17430 */ "RECIP_D64_MM\000" |
| 9654 | /* 17443 */ "C_SEQ_D64_MM\000" |
| 9655 | /* 17456 */ "C_UEQ_D64_MM\000" |
| 9656 | /* 17469 */ "C_EQ_D64_MM\000" |
| 9657 | /* 17481 */ "FABS_D64_MM\000" |
| 9658 | /* 17493 */ "CVT_S_D64_MM\000" |
| 9659 | /* 17506 */ "C_NGT_D64_MM\000" |
| 9660 | /* 17519 */ "C_OLT_D64_MM\000" |
| 9661 | /* 17532 */ "C_ULT_D64_MM\000" |
| 9662 | /* 17545 */ "C_LT_D64_MM\000" |
| 9663 | /* 17557 */ "FSQRT_D64_MM\000" |
| 9664 | /* 17570 */ "RSQRT_D64_MM\000" |
| 9665 | /* 17583 */ "FDIV_D64_MM\000" |
| 9666 | /* 17595 */ "FMOV_D64_MM\000" |
| 9667 | /* 17607 */ "CVT_W_D64_MM\000" |
| 9668 | /* 17620 */ "ADDIUS5_MM\000" |
| 9669 | /* 17631 */ "SB16_MM\000" |
| 9670 | /* 17639 */ "JRC16_MM\000" |
| 9671 | /* 17648 */ "AND16_MM\000" |
| 9672 | /* 17657 */ "MOVE16_MM\000" |
| 9673 | /* 17667 */ "SH16_MM\000" |
| 9674 | /* 17675 */ "ANDI16_MM\000" |
| 9675 | /* 17685 */ "MFHI16_MM\000" |
| 9676 | /* 17695 */ "LI16_MM\000" |
| 9677 | /* 17703 */ "BREAK16_MM\000" |
| 9678 | /* 17714 */ "SLL16_MM\000" |
| 9679 | /* 17723 */ "SRL16_MM\000" |
| 9680 | /* 17732 */ "LWM16_MM\000" |
| 9681 | /* 17741 */ "SWM16_MM\000" |
| 9682 | /* 17750 */ "MFLO16_MM\000" |
| 9683 | /* 17760 */ "SDBBP16_MM\000" |
| 9684 | /* 17771 */ "JR16_MM\000" |
| 9685 | /* 17779 */ "JALR16_MM\000" |
| 9686 | /* 17789 */ "XOR16_MM\000" |
| 9687 | /* 17798 */ "JALRS16_MM\000" |
| 9688 | /* 17809 */ "NOT16_MM\000" |
| 9689 | /* 17818 */ "LBU16_MM\000" |
| 9690 | /* 17827 */ "SUBU16_MM\000" |
| 9691 | /* 17837 */ "ADDU16_MM\000" |
| 9692 | /* 17847 */ "LHU16_MM\000" |
| 9693 | /* 17856 */ "LW16_MM\000" |
| 9694 | /* 17864 */ "SW16_MM\000" |
| 9695 | /* 17872 */ "BNEZ16_MM\000" |
| 9696 | /* 17882 */ "BEQZ16_MM\000" |
| 9697 | /* 17892 */ "PRECEU_PH_QBLA_MM\000" |
| 9698 | /* 17910 */ "PRECEQU_PH_QBLA_MM\000" |
| 9699 | /* 17929 */ "PRECEU_PH_QBRA_MM\000" |
| 9700 | /* 17947 */ "PRECEQU_PH_QBRA_MM\000" |
| 9701 | /* 17966 */ "SRA_MM\000" |
| 9702 | /* 17973 */ "SEB_MM\000" |
| 9703 | /* 17980 */ "EHB_MM\000" |
| 9704 | /* 17987 */ "LB_MM\000" |
| 9705 | /* 17993 */ "CMPGU_LE_QB_MM\000" |
| 9706 | /* 18008 */ "CMPU_LE_QB_MM\000" |
| 9707 | /* 18022 */ "PICK_QB_MM\000" |
| 9708 | /* 18033 */ "SHLL_QB_MM\000" |
| 9709 | /* 18044 */ "REPL_QB_MM\000" |
| 9710 | /* 18055 */ "SHRL_QB_MM\000" |
| 9711 | /* 18066 */ "CMPGU_EQ_QB_MM\000" |
| 9712 | /* 18081 */ "CMPU_EQ_QB_MM\000" |
| 9713 | /* 18095 */ "SUBU_S_QB_MM\000" |
| 9714 | /* 18108 */ "ADDU_S_QB_MM\000" |
| 9715 | /* 18121 */ "CMPGU_LT_QB_MM\000" |
| 9716 | /* 18136 */ "CMPU_LT_QB_MM\000" |
| 9717 | /* 18150 */ "SUBU_QB_MM\000" |
| 9718 | /* 18161 */ "ADDU_QB_MM\000" |
| 9719 | /* 18172 */ "SHLLV_QB_MM\000" |
| 9720 | /* 18184 */ "REPLV_QB_MM\000" |
| 9721 | /* 18196 */ "SHRLV_QB_MM\000" |
| 9722 | /* 18208 */ "RADDU_W_QB_MM\000" |
| 9723 | /* 18222 */ "SB_MM\000" |
| 9724 | /* 18228 */ "MODSUB_MM\000" |
| 9725 | /* 18238 */ "PseudoMSUB_MM\000" |
| 9726 | /* 18252 */ "SYNC_MM\000" |
| 9727 | /* 18260 */ "ADDIUPC_MM\000" |
| 9728 | /* 18271 */ "ADDSC_MM\000" |
| 9729 | /* 18280 */ "ADDWC_MM\000" |
| 9730 | /* 18289 */ "BNEZC_MM\000" |
| 9731 | /* 18298 */ "BEQZC_MM\000" |
| 9732 | /* 18307 */ "PseudoMADD_MM\000" |
| 9733 | /* 18321 */ "AND_MM\000" |
| 9734 | /* 18328 */ "LBE_MM\000" |
| 9735 | /* 18335 */ "SBE_MM\000" |
| 9736 | /* 18342 */ "SCE_MM\000" |
| 9737 | /* 18349 */ "CACHEE_MM\000" |
| 9738 | /* 18359 */ "PREFE_MM\000" |
| 9739 | /* 18368 */ "TGE_MM\000" |
| 9740 | /* 18375 */ "CACHE_MM\000" |
| 9741 | /* 18384 */ "LHE_MM\000" |
| 9742 | /* 18391 */ "SHE_MM\000" |
| 9743 | /* 18398 */ "LLE_MM\000" |
| 9744 | /* 18405 */ "LWLE_MM\000" |
| 9745 | /* 18413 */ "SWLE_MM\000" |
| 9746 | /* 18421 */ "BNE_MM\000" |
| 9747 | /* 18428 */ "TNE_MM\000" |
| 9748 | /* 18435 */ "LWRE_MM\000" |
| 9749 | /* 18443 */ "SWRE_MM\000" |
| 9750 | /* 18451 */ "PAUSE_MM\000" |
| 9751 | /* 18460 */ "LWE_MM\000" |
| 9752 | /* 18467 */ "SWE_MM\000" |
| 9753 | /* 18474 */ "LBuE_MM\000" |
| 9754 | /* 18482 */ "LHuE_MM\000" |
| 9755 | /* 18490 */ "BC1F_MM\000" |
| 9756 | /* 18498 */ "PREF_MM\000" |
| 9757 | /* 18506 */ "TLBGINVF_MM\000" |
| 9758 | /* 18518 */ "TAILCALLREG_MM\000" |
| 9759 | /* 18533 */ "WSBH_MM\000" |
| 9760 | /* 18541 */ "SEH_MM\000" |
| 9761 | /* 18548 */ "LH_MM\000" |
| 9762 | /* 18554 */ "SHRA_PH_MM\000" |
| 9763 | /* 18565 */ "PRECRQ_QB_PH_MM\000" |
| 9764 | /* 18581 */ "PRECRQU_S_QB_PH_MM\000" |
| 9765 | /* 18600 */ "CMP_LE_PH_MM\000" |
| 9766 | /* 18613 */ "PICK_PH_MM\000" |
| 9767 | /* 18624 */ "SHLL_PH_MM\000" |
| 9768 | /* 18635 */ "REPL_PH_MM\000" |
| 9769 | /* 18646 */ "PACKRL_PH_MM\000" |
| 9770 | /* 18659 */ "SUBQ_PH_MM\000" |
| 9771 | /* 18670 */ "ADDQ_PH_MM\000" |
| 9772 | /* 18681 */ "CMP_EQ_PH_MM\000" |
| 9773 | /* 18694 */ "SHRA_R_PH_MM\000" |
| 9774 | /* 18707 */ "SHRAV_R_PH_MM\000" |
| 9775 | /* 18721 */ "MULQ_RS_PH_MM\000" |
| 9776 | /* 18735 */ "SHLL_S_PH_MM\000" |
| 9777 | /* 18748 */ "SUBQ_S_PH_MM\000" |
| 9778 | /* 18761 */ "ADDQ_S_PH_MM\000" |
| 9779 | /* 18774 */ "ABSQ_S_PH_MM\000" |
| 9780 | /* 18787 */ "SHLLV_S_PH_MM\000" |
| 9781 | /* 18801 */ "CMP_LT_PH_MM\000" |
| 9782 | /* 18814 */ "SHRAV_PH_MM\000" |
| 9783 | /* 18826 */ "SHLLV_PH_MM\000" |
| 9784 | /* 18838 */ "REPLV_PH_MM\000" |
| 9785 | /* 18850 */ "DPAQ_S_W_PH_MM\000" |
| 9786 | /* 18865 */ "MULSAQ_S_W_PH_MM\000" |
| 9787 | /* 18882 */ "DPSQ_S_W_PH_MM\000" |
| 9788 | /* 18897 */ "SH_MM\000" |
| 9789 | /* 18903 */ "EXTR_S_H_MM\000" |
| 9790 | /* 18915 */ "EXTRV_S_H_MM\000" |
| 9791 | /* 18928 */ "SYNCI_MM\000" |
| 9792 | /* 18937 */ "DI_MM\000" |
| 9793 | /* 18943 */ "TGEI_MM\000" |
| 9794 | /* 18951 */ "TNEI_MM\000" |
| 9795 | /* 18959 */ "PseudoMFHI_MM\000" |
| 9796 | /* 18973 */ "PseudoMTLOHI_MM\000" |
| 9797 | /* 18989 */ "MTHI_MM\000" |
| 9798 | /* 18997 */ "TEQI_MM\000" |
| 9799 | /* 19005 */ "TLTI_MM\000" |
| 9800 | /* 19013 */ "TLBWI_MM\000" |
| 9801 | /* 19022 */ "TLBGWI_MM\000" |
| 9802 | /* 19032 */ "MOVF_I_MM\000" |
| 9803 | /* 19042 */ "MOVN_I_MM\000" |
| 9804 | /* 19052 */ "MOVT_I_MM\000" |
| 9805 | /* 19062 */ "MOVZ_I_MM\000" |
| 9806 | /* 19072 */ "J_MM\000" |
| 9807 | /* 19077 */ "BREAK_MM\000" |
| 9808 | /* 19086 */ "JAL_MM\000" |
| 9809 | /* 19093 */ "BGEZAL_MM\000" |
| 9810 | /* 19103 */ "BLTZAL_MM\000" |
| 9811 | /* 19113 */ "MULEU_S_PH_QBL_MM\000" |
| 9812 | /* 19131 */ "PRECEU_PH_QBL_MM\000" |
| 9813 | /* 19148 */ "PRECEQU_PH_QBL_MM\000" |
| 9814 | /* 19166 */ "DPAU_H_QBL_MM\000" |
| 9815 | /* 19180 */ "DPSU_H_QBL_MM\000" |
| 9816 | /* 19194 */ "MAQ_SA_W_PHL_MM\000" |
| 9817 | /* 19210 */ "PRECEQ_W_PHL_MM\000" |
| 9818 | /* 19226 */ "MAQ_S_W_PHL_MM\000" |
| 9819 | /* 19241 */ "MULEQ_S_W_PHL_MM\000" |
| 9820 | /* 19258 */ "TAILCALL_MM\000" |
| 9821 | /* 19270 */ "HYPCALL_MM\000" |
| 9822 | /* 19281 */ "SYSCALL_MM\000" |
| 9823 | /* 19292 */ "SLL_MM\000" |
| 9824 | /* 19299 */ "SRL_MM\000" |
| 9825 | /* 19306 */ "MUL_MM\000" |
| 9826 | /* 19313 */ "LWL_MM\000" |
| 9827 | /* 19320 */ "SWL_MM\000" |
| 9828 | /* 19327 */ "LWM_MM\000" |
| 9829 | /* 19334 */ "SWM_MM\000" |
| 9830 | /* 19341 */ "CLO_MM\000" |
| 9831 | /* 19348 */ "PseudoMFLO_MM\000" |
| 9832 | /* 19362 */ "SHILO_MM\000" |
| 9833 | /* 19371 */ "MTLO_MM\000" |
| 9834 | /* 19379 */ "TRAP_MM\000" |
| 9835 | /* 19387 */ "SDBBP_MM\000" |
| 9836 | /* 19396 */ "TLBP_MM\000" |
| 9837 | /* 19404 */ "EXTPDP_MM\000" |
| 9838 | /* 19414 */ "MOVEP_MM\000" |
| 9839 | /* 19423 */ "TLBGP_MM\000" |
| 9840 | /* 19432 */ "LWGP_MM\000" |
| 9841 | /* 19440 */ "MTHLIP_MM\000" |
| 9842 | /* 19450 */ "SSNOP_MM\000" |
| 9843 | /* 19459 */ "ADDIUR1SP_MM\000" |
| 9844 | /* 19472 */ "RDDSP_MM\000" |
| 9845 | /* 19481 */ "WRDSP_MM\000" |
| 9846 | /* 19490 */ "LWDSP_MM\000" |
| 9847 | /* 19499 */ "SWDSP_MM\000" |
| 9848 | /* 19508 */ "MSUB_DSP_MM\000" |
| 9849 | /* 19520 */ "MADD_DSP_MM\000" |
| 9850 | /* 19532 */ "MFHI_DSP_MM\000" |
| 9851 | /* 19544 */ "MTHI_DSP_MM\000" |
| 9852 | /* 19556 */ "MFLO_DSP_MM\000" |
| 9853 | /* 19568 */ "MTLO_DSP_MM\000" |
| 9854 | /* 19580 */ "MULT_DSP_MM\000" |
| 9855 | /* 19592 */ "MSUBU_DSP_MM\000" |
| 9856 | /* 19605 */ "MADDU_DSP_MM\000" |
| 9857 | /* 19618 */ "MULTU_DSP_MM\000" |
| 9858 | /* 19631 */ "ADDIUSP_MM\000" |
| 9859 | /* 19642 */ "LWSP_MM\000" |
| 9860 | /* 19650 */ "SWSP_MM\000" |
| 9861 | /* 19658 */ "EXTP_MM\000" |
| 9862 | /* 19666 */ "LWP_MM\000" |
| 9863 | /* 19673 */ "SWP_MM\000" |
| 9864 | /* 19680 */ "BEQ_MM\000" |
| 9865 | /* 19687 */ "TEQ_MM\000" |
| 9866 | /* 19694 */ "TLBR_MM\000" |
| 9867 | /* 19702 */ "MULEU_S_PH_QBR_MM\000" |
| 9868 | /* 19720 */ "PRECEU_PH_QBR_MM\000" |
| 9869 | /* 19737 */ "PRECEQU_PH_QBR_MM\000" |
| 9870 | /* 19755 */ "DPAU_H_QBR_MM\000" |
| 9871 | /* 19769 */ "DPSU_H_QBR_MM\000" |
| 9872 | /* 19783 */ "BAL_BR_MM\000" |
| 9873 | /* 19793 */ "TLBGR_MM\000" |
| 9874 | /* 19802 */ "MAQ_SA_W_PHR_MM\000" |
| 9875 | /* 19818 */ "PRECEQ_W_PHR_MM\000" |
| 9876 | /* 19834 */ "MAQ_S_W_PHR_MM\000" |
| 9877 | /* 19849 */ "MULEQ_S_W_PHR_MM\000" |
| 9878 | /* 19866 */ "JR_MM\000" |
| 9879 | /* 19872 */ "JALR_MM\000" |
| 9880 | /* 19880 */ "NOR_MM\000" |
| 9881 | /* 19887 */ "XOR_MM\000" |
| 9882 | /* 19894 */ "ROTR_MM\000" |
| 9883 | /* 19902 */ "TLBWR_MM\000" |
| 9884 | /* 19911 */ "TLBGWR_MM\000" |
| 9885 | /* 19921 */ "RDHWR_MM\000" |
| 9886 | /* 19930 */ "LWR_MM\000" |
| 9887 | /* 19937 */ "SWR_MM\000" |
| 9888 | /* 19944 */ "JALS_MM\000" |
| 9889 | /* 19952 */ "BGEZALS_MM\000" |
| 9890 | /* 19963 */ "BLTZALS_MM\000" |
| 9891 | /* 19974 */ "INS_MM\000" |
| 9892 | /* 19981 */ "JALRS_MM\000" |
| 9893 | /* 19990 */ "LWXS_MM\000" |
| 9894 | /* 19998 */ "CVT_D32_S_MM\000" |
| 9895 | /* 20011 */ "CVT_D64_S_MM\000" |
| 9896 | /* 20024 */ "FSUB_S_MM\000" |
| 9897 | /* 20034 */ "NMSUB_S_MM\000" |
| 9898 | /* 20045 */ "FADD_S_MM\000" |
| 9899 | /* 20055 */ "NMADD_S_MM\000" |
| 9900 | /* 20066 */ "C_NGE_S_MM\000" |
| 9901 | /* 20077 */ "C_NGLE_S_MM\000" |
| 9902 | /* 20089 */ "C_OLE_S_MM\000" |
| 9903 | /* 20100 */ "C_ULE_S_MM\000" |
| 9904 | /* 20111 */ "C_LE_S_MM\000" |
| 9905 | /* 20121 */ "C_SF_S_MM\000" |
| 9906 | /* 20131 */ "MOVF_S_MM\000" |
| 9907 | /* 20141 */ "C_F_S_MM\000" |
| 9908 | /* 20150 */ "FNEG_S_MM\000" |
| 9909 | /* 20160 */ "MOVN_I_S_MM\000" |
| 9910 | /* 20172 */ "MOVZ_I_S_MM\000" |
| 9911 | /* 20184 */ "C_NGL_S_MM\000" |
| 9912 | /* 20195 */ "FMUL_S_MM\000" |
| 9913 | /* 20205 */ "CVT_L_S_MM\000" |
| 9914 | /* 20216 */ "C_UN_S_MM\000" |
| 9915 | /* 20226 */ "RECIP_S_MM\000" |
| 9916 | /* 20237 */ "C_SEQ_S_MM\000" |
| 9917 | /* 20248 */ "C_UEQ_S_MM\000" |
| 9918 | /* 20259 */ "C_EQ_S_MM\000" |
| 9919 | /* 20269 */ "FABS_S_MM\000" |
| 9920 | /* 20279 */ "C_NGT_S_MM\000" |
| 9921 | /* 20290 */ "C_OLT_S_MM\000" |
| 9922 | /* 20301 */ "C_ULT_S_MM\000" |
| 9923 | /* 20312 */ "C_LT_S_MM\000" |
| 9924 | /* 20322 */ "FSQRT_S_MM\000" |
| 9925 | /* 20333 */ "RSQRT_S_MM\000" |
| 9926 | /* 20344 */ "MOVT_S_MM\000" |
| 9927 | /* 20354 */ "FDIV_S_MM\000" |
| 9928 | /* 20364 */ "FMOV_S_MM\000" |
| 9929 | /* 20374 */ "TRUNC_W_S_MM\000" |
| 9930 | /* 20387 */ "ROUND_W_S_MM\000" |
| 9931 | /* 20400 */ "CEIL_W_S_MM\000" |
| 9932 | /* 20412 */ "FLOOR_W_S_MM\000" |
| 9933 | /* 20425 */ "CVT_W_S_MM\000" |
| 9934 | /* 20436 */ "BC1T_MM\000" |
| 9935 | /* 20444 */ "DERET_MM\000" |
| 9936 | /* 20453 */ "WAIT_MM\000" |
| 9937 | /* 20461 */ "SLT_MM\000" |
| 9938 | /* 20468 */ "TLT_MM\000" |
| 9939 | /* 20475 */ "PseudoMULT_MM\000" |
| 9940 | /* 20489 */ "EXT_MM\000" |
| 9941 | /* 20496 */ "PseudoMSUBU_MM\000" |
| 9942 | /* 20511 */ "PseudoMADDU_MM\000" |
| 9943 | /* 20526 */ "TGEU_MM\000" |
| 9944 | /* 20534 */ "TGEIU_MM\000" |
| 9945 | /* 20543 */ "TLTIU_MM\000" |
| 9946 | /* 20552 */ "TLTU_MM\000" |
| 9947 | /* 20560 */ "LWU_MM\000" |
| 9948 | /* 20567 */ "SRAV_MM\000" |
| 9949 | /* 20575 */ "BITREV_MM\000" |
| 9950 | /* 20585 */ "SDIV_MM\000" |
| 9951 | /* 20593 */ "UDIV_MM\000" |
| 9952 | /* 20601 */ "SLLV_MM\000" |
| 9953 | /* 20609 */ "SRLV_MM\000" |
| 9954 | /* 20617 */ "TLBGINV_MM\000" |
| 9955 | /* 20628 */ "SHILOV_MM\000" |
| 9956 | /* 20638 */ "EXTPDPV_MM\000" |
| 9957 | /* 20649 */ "EXTPV_MM\000" |
| 9958 | /* 20658 */ "ROTRV_MM\000" |
| 9959 | /* 20667 */ "INSV_MM\000" |
| 9960 | /* 20675 */ "LW_MM\000" |
| 9961 | /* 20681 */ "SW_MM\000" |
| 9962 | /* 20687 */ "CVT_D32_W_MM\000" |
| 9963 | /* 20700 */ "CVT_D64_W_MM\000" |
| 9964 | /* 20713 */ "TRUNC_W_MM\000" |
| 9965 | /* 20724 */ "ROUND_W_MM\000" |
| 9966 | /* 20735 */ "PRECRQ_PH_W_MM\000" |
| 9967 | /* 20750 */ "PRECRQ_RS_PH_W_MM\000" |
| 9968 | /* 20768 */ "CEIL_W_MM\000" |
| 9969 | /* 20778 */ "DPAQ_SA_L_W_MM\000" |
| 9970 | /* 20793 */ "DPSQ_SA_L_W_MM\000" |
| 9971 | /* 20808 */ "FLOOR_W_MM\000" |
| 9972 | /* 20819 */ "EXTR_W_MM\000" |
| 9973 | /* 20829 */ "SHRA_R_W_MM\000" |
| 9974 | /* 20841 */ "EXTR_R_W_MM\000" |
| 9975 | /* 20853 */ "SHRAV_R_W_MM\000" |
| 9976 | /* 20866 */ "EXTRV_R_W_MM\000" |
| 9977 | /* 20879 */ "EXTR_RS_W_MM\000" |
| 9978 | /* 20892 */ "EXTRV_RS_W_MM\000" |
| 9979 | /* 20906 */ "SHLL_S_W_MM\000" |
| 9980 | /* 20918 */ "SUBQ_S_W_MM\000" |
| 9981 | /* 20930 */ "ADDQ_S_W_MM\000" |
| 9982 | /* 20942 */ "ABSQ_S_W_MM\000" |
| 9983 | /* 20954 */ "CVT_S_W_MM\000" |
| 9984 | /* 20965 */ "SHLLV_S_W_MM\000" |
| 9985 | /* 20978 */ "EXTRV_W_MM\000" |
| 9986 | /* 20989 */ "PREFX_MM\000" |
| 9987 | /* 20998 */ "LHX_MM\000" |
| 9988 | /* 21005 */ "JALX_MM\000" |
| 9989 | /* 21013 */ "LBUX_MM\000" |
| 9990 | /* 21021 */ "LWX_MM\000" |
| 9991 | /* 21028 */ "BGEZ_MM\000" |
| 9992 | /* 21036 */ "BLEZ_MM\000" |
| 9993 | /* 21044 */ "CLZ_MM\000" |
| 9994 | /* 21051 */ "BGTZ_MM\000" |
| 9995 | /* 21059 */ "BLTZ_MM\000" |
| 9996 | /* 21067 */ "PseudoIndirectBranch_MM\000" |
| 9997 | /* 21091 */ "ADDi_MM\000" |
| 9998 | /* 21099 */ "ANDi_MM\000" |
| 9999 | /* 21107 */ "XORi_MM\000" |
| 10000 | /* 21115 */ "SLTi_MM\000" |
| 10001 | /* 21123 */ "LUi_MM\000" |
| 10002 | /* 21130 */ "LBu_MM\000" |
| 10003 | /* 21137 */ "SUBu_MM\000" |
| 10004 | /* 21145 */ "ADDu_MM\000" |
| 10005 | /* 21153 */ "LHu_MM\000" |
| 10006 | /* 21160 */ "SLTu_MM\000" |
| 10007 | /* 21168 */ "PseudoMULTu_MM\000" |
| 10008 | /* 21183 */ "LEA_ADDiu_MM\000" |
| 10009 | /* 21196 */ "SLTiu_MM\000" |
| 10010 | /* 21205 */ "INLINEASM\000" |
| 10011 | /* 21215 */ "DINSM\000" |
| 10012 | /* 21221 */ "DEXTM\000" |
| 10013 | /* 21227 */ "G_VECREDUCE_FMINIMUM\000" |
| 10014 | /* 21248 */ "G_FMINIMUM\000" |
| 10015 | /* 21259 */ "G_ATOMICRMW_FMINIMUM\000" |
| 10016 | /* 21280 */ "G_VECREDUCE_FMAXIMUM\000" |
| 10017 | /* 21301 */ "G_FMAXIMUM\000" |
| 10018 | /* 21312 */ "G_ATOMICRMW_FMAXIMUM\000" |
| 10019 | /* 21333 */ "G_FMINIMUMNUM\000" |
| 10020 | /* 21347 */ "G_FMAXIMUMNUM\000" |
| 10021 | /* 21361 */ "G_FMINNUM\000" |
| 10022 | /* 21371 */ "G_FMAXNUM\000" |
| 10023 | /* 21381 */ "G_FATAN\000" |
| 10024 | /* 21389 */ "G_FTAN\000" |
| 10025 | /* 21396 */ "G_INTRINSIC_ROUNDEVEN\000" |
| 10026 | /* 21418 */ "BALIGN\000" |
| 10027 | /* 21425 */ "DALIGN\000" |
| 10028 | /* 21432 */ "G_ASSERT_ALIGN\000" |
| 10029 | /* 21447 */ "G_FCOPYSIGN\000" |
| 10030 | /* 21459 */ "G_VECREDUCE_FMIN\000" |
| 10031 | /* 21476 */ "G_ATOMICRMW_FMIN\000" |
| 10032 | /* 21493 */ "G_VECREDUCE_SMIN\000" |
| 10033 | /* 21510 */ "G_SMIN\000" |
| 10034 | /* 21517 */ "G_VECREDUCE_UMIN\000" |
| 10035 | /* 21534 */ "G_UMIN\000" |
| 10036 | /* 21541 */ "G_ATOMICRMW_UMIN\000" |
| 10037 | /* 21558 */ "G_ATOMICRMW_MIN\000" |
| 10038 | /* 21574 */ "G_FASIN\000" |
| 10039 | /* 21582 */ "G_FSIN\000" |
| 10040 | /* 21589 */ "DMFC2_OCTEON\000" |
| 10041 | /* 21602 */ "DMTC2_OCTEON\000" |
| 10042 | /* 21615 */ "CFI_INSTRUCTION\000" |
| 10043 | /* 21631 */ "ADJCALLSTACKDOWN\000" |
| 10044 | /* 21648 */ "G_SSUBO\000" |
| 10045 | /* 21656 */ "G_USUBO\000" |
| 10046 | /* 21664 */ "G_SADDO\000" |
| 10047 | /* 21672 */ "G_UADDO\000" |
| 10048 | /* 21680 */ "FEXP2_D_1_PSEUDO\000" |
| 10049 | /* 21697 */ "FEXP2_W_1_PSEUDO\000" |
| 10050 | /* 21714 */ "BPOSGE32_PSEUDO\000" |
| 10051 | /* 21730 */ "INSERT_B_VIDX64_PSEUDO\000" |
| 10052 | /* 21753 */ "INSERT_FD_VIDX64_PSEUDO\000" |
| 10053 | /* 21777 */ "INSERT_D_VIDX64_PSEUDO\000" |
| 10054 | /* 21800 */ "INSERT_H_VIDX64_PSEUDO\000" |
| 10055 | /* 21823 */ "INSERT_FW_VIDX64_PSEUDO\000" |
| 10056 | /* 21847 */ "INSERT_W_VIDX64_PSEUDO\000" |
| 10057 | /* 21870 */ "SNZ_B_PSEUDO\000" |
| 10058 | /* 21883 */ "SZ_B_PSEUDO\000" |
| 10059 | /* 21895 */ "BSEL_FD_PSEUDO\000" |
| 10060 | /* 21910 */ "FILL_FD_PSEUDO\000" |
| 10061 | /* 21925 */ "INSERT_FD_PSEUDO\000" |
| 10062 | /* 21942 */ "COPY_FD_PSEUDO\000" |
| 10063 | /* 21957 */ "MSA_FP_EXTEND_D_PSEUDO\000" |
| 10064 | /* 21980 */ "MSA_FP_ROUND_D_PSEUDO\000" |
| 10065 | /* 22002 */ "BSEL_D_PSEUDO\000" |
| 10066 | /* 22016 */ "AND_V_D_PSEUDO\000" |
| 10067 | /* 22031 */ "NOR_V_D_PSEUDO\000" |
| 10068 | /* 22046 */ "XOR_V_D_PSEUDO\000" |
| 10069 | /* 22061 */ "SNZ_D_PSEUDO\000" |
| 10070 | /* 22074 */ "SZ_D_PSEUDO\000" |
| 10071 | /* 22086 */ "BSEL_H_PSEUDO\000" |
| 10072 | /* 22100 */ "AND_V_H_PSEUDO\000" |
| 10073 | /* 22115 */ "NOR_V_H_PSEUDO\000" |
| 10074 | /* 22130 */ "XOR_V_H_PSEUDO\000" |
| 10075 | /* 22145 */ "SNZ_H_PSEUDO\000" |
| 10076 | /* 22158 */ "SZ_H_PSEUDO\000" |
| 10077 | /* 22170 */ "SNZ_V_PSEUDO\000" |
| 10078 | /* 22183 */ "SZ_V_PSEUDO\000" |
| 10079 | /* 22195 */ "BSEL_FW_PSEUDO\000" |
| 10080 | /* 22210 */ "FILL_FW_PSEUDO\000" |
| 10081 | /* 22225 */ "INSERT_FW_PSEUDO\000" |
| 10082 | /* 22242 */ "COPY_FW_PSEUDO\000" |
| 10083 | /* 22257 */ "MSA_FP_EXTEND_W_PSEUDO\000" |
| 10084 | /* 22280 */ "MSA_FP_ROUND_W_PSEUDO\000" |
| 10085 | /* 22302 */ "BSEL_W_PSEUDO\000" |
| 10086 | /* 22316 */ "AND_V_W_PSEUDO\000" |
| 10087 | /* 22331 */ "NOR_V_W_PSEUDO\000" |
| 10088 | /* 22346 */ "XOR_V_W_PSEUDO\000" |
| 10089 | /* 22361 */ "SNZ_W_PSEUDO\000" |
| 10090 | /* 22374 */ "SZ_W_PSEUDO\000" |
| 10091 | /* 22386 */ "INSERT_B_VIDX_PSEUDO\000" |
| 10092 | /* 22407 */ "INSERT_FD_VIDX_PSEUDO\000" |
| 10093 | /* 22429 */ "INSERT_D_VIDX_PSEUDO\000" |
| 10094 | /* 22450 */ "INSERT_H_VIDX_PSEUDO\000" |
| 10095 | /* 22471 */ "INSERT_FW_VIDX_PSEUDO\000" |
| 10096 | /* 22493 */ "INSERT_W_VIDX_PSEUDO\000" |
| 10097 | /* 22514 */ "JUMP_TABLE_DEBUG_INFO\000" |
| 10098 | /* 22536 */ "DCLO\000" |
| 10099 | /* 22541 */ "PseudoMFLO\000" |
| 10100 | /* 22552 */ "SHILO\000" |
| 10101 | /* 22558 */ "MFTLO\000" |
| 10102 | /* 22564 */ "MTLO\000" |
| 10103 | /* 22569 */ "MTTLO\000" |
| 10104 | /* 22575 */ "G_SMULO\000" |
| 10105 | /* 22583 */ "G_UMULO\000" |
| 10106 | /* 22591 */ "G_BZERO\000" |
| 10107 | /* 22599 */ "STACKMAP\000" |
| 10108 | /* 22608 */ "G_DEBUGTRAP\000" |
| 10109 | /* 22620 */ "G_UBSANTRAP\000" |
| 10110 | /* 22632 */ "G_TRAP\000" |
| 10111 | /* 22639 */ "G_ATOMICRMW_UDEC_WRAP\000" |
| 10112 | /* 22661 */ "G_ATOMICRMW_UINC_WRAP\000" |
| 10113 | /* 22683 */ "G_BSWAP\000" |
| 10114 | /* 22691 */ "DBITSWAP\000" |
| 10115 | /* 22700 */ "SDBBP\000" |
| 10116 | /* 22706 */ "TLBP\000" |
| 10117 | /* 22711 */ "EXTPDP\000" |
| 10118 | /* 22718 */ "G_SITOFP\000" |
| 10119 | /* 22727 */ "G_UITOFP\000" |
| 10120 | /* 22736 */ "TLBGP\000" |
| 10121 | /* 22742 */ "MTHLIP\000" |
| 10122 | /* 22749 */ "G_FCMP\000" |
| 10123 | /* 22756 */ "G_ICMP\000" |
| 10124 | /* 22763 */ "G_SCMP\000" |
| 10125 | /* 22770 */ "G_UCMP\000" |
| 10126 | /* 22777 */ "SSNOP\000" |
| 10127 | /* 22783 */ "CONVERGENCECTRL_LOOP\000" |
| 10128 | /* 22804 */ "DPOP\000" |
| 10129 | /* 22809 */ "G_CTPOP\000" |
| 10130 | /* 22817 */ "PATCHABLE_OP\000" |
| 10131 | /* 22830 */ "FAULTING_OP\000" |
| 10132 | /* 22842 */ "LOAD_ACC64DSP\000" |
| 10133 | /* 22856 */ "STORE_ACC64DSP\000" |
| 10134 | /* 22871 */ "RDDSP\000" |
| 10135 | /* 22877 */ "WRDSP\000" |
| 10136 | /* 22883 */ "MFTDSP\000" |
| 10137 | /* 22890 */ "MTTDSP\000" |
| 10138 | /* 22897 */ "LWDSP\000" |
| 10139 | /* 22903 */ "SWDSP\000" |
| 10140 | /* 22909 */ "MSUB_DSP\000" |
| 10141 | /* 22918 */ "MADD_DSP\000" |
| 10142 | /* 22927 */ "LOAD_CCOND_DSP\000" |
| 10143 | /* 22942 */ "STORE_CCOND_DSP\000" |
| 10144 | /* 22958 */ "MFHI_DSP\000" |
| 10145 | /* 22967 */ "PseudoMTLOHI_DSP\000" |
| 10146 | /* 22984 */ "MTHI_DSP\000" |
| 10147 | /* 22993 */ "MFLO_DSP\000" |
| 10148 | /* 23002 */ "MTLO_DSP\000" |
| 10149 | /* 23011 */ "MULT_DSP\000" |
| 10150 | /* 23020 */ "MSUBU_DSP\000" |
| 10151 | /* 23030 */ "MADDU_DSP\000" |
| 10152 | /* 23040 */ "MULTU_DSP\000" |
| 10153 | /* 23050 */ "JRADDIUSP\000" |
| 10154 | /* 23060 */ "EXTP\000" |
| 10155 | /* 23065 */ "ADJCALLSTACKUP\000" |
| 10156 | /* 23080 */ "PREALLOCATED_SETUP\000" |
| 10157 | /* 23099 */ "DVP\000" |
| 10158 | /* 23103 */ "EVP\000" |
| 10159 | /* 23107 */ "G_FLDEXP\000" |
| 10160 | /* 23116 */ "G_STRICT_FLDEXP\000" |
| 10161 | /* 23132 */ "G_FEXP\000" |
| 10162 | /* 23139 */ "G_FFREXP\000" |
| 10163 | /* 23148 */ "BEQ\000" |
| 10164 | /* 23152 */ "SEQ\000" |
| 10165 | /* 23156 */ "TEQ\000" |
| 10166 | /* 23160 */ "TLBR\000" |
| 10167 | /* 23165 */ "MULEU_S_PH_QBR\000" |
| 10168 | /* 23180 */ "PRECEU_PH_QBR\000" |
| 10169 | /* 23194 */ "PRECEQU_PH_QBR\000" |
| 10170 | /* 23209 */ "DPAU_H_QBR\000" |
| 10171 | /* 23220 */ "DPSU_H_QBR\000" |
| 10172 | /* 23231 */ "G_BR\000" |
| 10173 | /* 23236 */ "BAL_BR\000" |
| 10174 | /* 23243 */ "INLINEASM_BR\000" |
| 10175 | /* 23256 */ "G_BLOCK_ADDR\000" |
| 10176 | /* 23269 */ "LDR\000" |
| 10177 | /* 23273 */ "SDR\000" |
| 10178 | /* 23277 */ "MEMBARRIER\000" |
| 10179 | /* 23288 */ "G_CONSTANT_FOLD_BARRIER\000" |
| 10180 | /* 23312 */ "PATCHABLE_FUNCTION_ENTER\000" |
| 10181 | /* 23337 */ "G_READCYCLECOUNTER\000" |
| 10182 | /* 23356 */ "G_READSTEADYCOUNTER\000" |
| 10183 | /* 23376 */ "G_READ_REGISTER\000" |
| 10184 | /* 23392 */ "G_WRITE_REGISTER\000" |
| 10185 | /* 23409 */ "TLBGR\000" |
| 10186 | /* 23415 */ "LoadImmDoubleFGR\000" |
| 10187 | /* 23432 */ "LoadImmSingleFGR\000" |
| 10188 | /* 23449 */ "MAQ_SA_W_PHR\000" |
| 10189 | /* 23462 */ "PRECEQ_W_PHR\000" |
| 10190 | /* 23475 */ "MAQ_S_W_PHR\000" |
| 10191 | /* 23487 */ "MULEQ_S_W_PHR\000" |
| 10192 | /* 23501 */ "G_ASHR\000" |
| 10193 | /* 23508 */ "G_FSHR\000" |
| 10194 | /* 23515 */ "G_LSHR\000" |
| 10195 | /* 23522 */ "JR\000" |
| 10196 | /* 23525 */ "JALR\000" |
| 10197 | /* 23530 */ "CONVERGENCECTRL_ANCHOR\000" |
| 10198 | /* 23553 */ "NOR\000" |
| 10199 | /* 23557 */ "G_FFLOOR\000" |
| 10200 | /* 23566 */ "G_SAVGFLOOR\000" |
| 10201 | /* 23578 */ "G_UAVGFLOOR\000" |
| 10202 | /* 23590 */ "DROR\000" |
| 10203 | /* 23595 */ "G_EXTRACT_SUBVECTOR\000" |
| 10204 | /* 23615 */ "G_INSERT_SUBVECTOR\000" |
| 10205 | /* 23634 */ "G_BUILD_VECTOR\000" |
| 10206 | /* 23649 */ "G_SHUFFLE_VECTOR\000" |
| 10207 | /* 23666 */ "G_STEP_VECTOR\000" |
| 10208 | /* 23680 */ "G_SPLAT_VECTOR\000" |
| 10209 | /* 23695 */ "G_VECREDUCE_XOR\000" |
| 10210 | /* 23711 */ "G_XOR\000" |
| 10211 | /* 23717 */ "G_ATOMICRMW_XOR\000" |
| 10212 | /* 23733 */ "G_VECREDUCE_OR\000" |
| 10213 | /* 23748 */ "G_OR\000" |
| 10214 | /* 23753 */ "G_ATOMICRMW_OR\000" |
| 10215 | /* 23768 */ "MFTGPR\000" |
| 10216 | /* 23775 */ "MTTGPR\000" |
| 10217 | /* 23782 */ "LoadImmDoubleGPR\000" |
| 10218 | /* 23799 */ "LoadImmSingleGPR\000" |
| 10219 | /* 23816 */ "MFTR\000" |
| 10220 | /* 23821 */ "DROTR\000" |
| 10221 | /* 23827 */ "G_ROTR\000" |
| 10222 | /* 23834 */ "G_INTTOPTR\000" |
| 10223 | /* 23845 */ "MTTR\000" |
| 10224 | /* 23850 */ "TLBWR\000" |
| 10225 | /* 23856 */ "TLBGWR\000" |
| 10226 | /* 23863 */ "RDHWR\000" |
| 10227 | /* 23869 */ "LWR\000" |
| 10228 | /* 23873 */ "SWR\000" |
| 10229 | /* 23877 */ "G_FABS\000" |
| 10230 | /* 23884 */ "G_ABS\000" |
| 10231 | /* 23890 */ "G_ABDS\000" |
| 10232 | /* 23897 */ "G_UNMERGE_VALUES\000" |
| 10233 | /* 23914 */ "G_MERGE_VALUES\000" |
| 10234 | /* 23929 */ "G_CTLS\000" |
| 10235 | /* 23936 */ "CINS\000" |
| 10236 | /* 23941 */ "DINS\000" |
| 10237 | /* 23946 */ "G_FACOS\000" |
| 10238 | /* 23954 */ "G_FCOS\000" |
| 10239 | /* 23961 */ "G_FSINCOS\000" |
| 10240 | /* 23971 */ "G_CONCAT_VECTORS\000" |
| 10241 | /* 23988 */ "COPY_TO_REGCLASS\000" |
| 10242 | /* 24005 */ "G_IS_FPCLASS\000" |
| 10243 | /* 24018 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000" |
| 10244 | /* 24048 */ "G_VECTOR_COMPRESS\000" |
| 10245 | /* 24066 */ "G_INTRINSIC_W_SIDE_EFFECTS\000" |
| 10246 | /* 24093 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000" |
| 10247 | /* 24131 */ "EXTS\000" |
| 10248 | /* 24136 */ "CVT_D32_S\000" |
| 10249 | /* 24146 */ "CVT_D64_S\000" |
| 10250 | /* 24156 */ "MOVN_I64_S\000" |
| 10251 | /* 24167 */ "MOVZ_I64_S\000" |
| 10252 | /* 24178 */ "MINA_S\000" |
| 10253 | /* 24185 */ "MAXA_S\000" |
| 10254 | /* 24192 */ "FSUB_S\000" |
| 10255 | /* 24199 */ "NMSUB_S\000" |
| 10256 | /* 24207 */ "FADD_S\000" |
| 10257 | /* 24214 */ "NMADD_S\000" |
| 10258 | /* 24222 */ "C_NGE_S\000" |
| 10259 | /* 24230 */ "C_NGLE_S\000" |
| 10260 | /* 24239 */ "C_OLE_S\000" |
| 10261 | /* 24247 */ "CMP_SLE_S\000" |
| 10262 | /* 24257 */ "CMP_SULE_S\000" |
| 10263 | /* 24268 */ "C_ULE_S\000" |
| 10264 | /* 24276 */ "CMP_ULE_S\000" |
| 10265 | /* 24286 */ "C_LE_S\000" |
| 10266 | /* 24293 */ "CMP_LE_S\000" |
| 10267 | /* 24302 */ "CMP_SAF_S\000" |
| 10268 | /* 24312 */ "MSUBF_S\000" |
| 10269 | /* 24320 */ "MADDF_S\000" |
| 10270 | /* 24328 */ "C_SF_S\000" |
| 10271 | /* 24335 */ "MOVF_S\000" |
| 10272 | /* 24342 */ "C_F_S\000" |
| 10273 | /* 24348 */ "PseudoSELECTFP_F_S\000" |
| 10274 | /* 24367 */ "CMP_F_S\000" |
| 10275 | /* 24375 */ "FNEG_S\000" |
| 10276 | /* 24382 */ "MOVN_I_S\000" |
| 10277 | /* 24391 */ "MOVZ_I_S\000" |
| 10278 | /* 24400 */ "SEL_S\000" |
| 10279 | /* 24406 */ "C_NGL_S\000" |
| 10280 | /* 24414 */ "FMUL_S\000" |
| 10281 | /* 24421 */ "TRUNC_L_S\000" |
| 10282 | /* 24431 */ "ROUND_L_S\000" |
| 10283 | /* 24441 */ "CEIL_L_S\000" |
| 10284 | /* 24450 */ "FLOOR_L_S\000" |
| 10285 | /* 24460 */ "CVT_L_S\000" |
| 10286 | /* 24468 */ "MIN_S\000" |
| 10287 | /* 24474 */ "CMP_SUN_S\000" |
| 10288 | /* 24484 */ "C_UN_S\000" |
| 10289 | /* 24491 */ "CMP_UN_S\000" |
| 10290 | /* 24500 */ "RECIP_S\000" |
| 10291 | /* 24508 */ "C_SEQ_S\000" |
| 10292 | /* 24516 */ "CMP_SEQ_S\000" |
| 10293 | /* 24526 */ "CMP_SUEQ_S\000" |
| 10294 | /* 24537 */ "C_UEQ_S\000" |
| 10295 | /* 24545 */ "CMP_UEQ_S\000" |
| 10296 | /* 24555 */ "C_EQ_S\000" |
| 10297 | /* 24562 */ "CMP_EQ_S\000" |
| 10298 | /* 24571 */ "FABS_S\000" |
| 10299 | /* 24578 */ "CLASS_S\000" |
| 10300 | /* 24586 */ "G_TRUNC_SSAT_S\000" |
| 10301 | /* 24601 */ "PseudoSELECT_S\000" |
| 10302 | /* 24616 */ "C_NGT_S\000" |
| 10303 | /* 24624 */ "C_OLT_S\000" |
| 10304 | /* 24632 */ "CMP_SLT_S\000" |
| 10305 | /* 24642 */ "CMP_SULT_S\000" |
| 10306 | /* 24653 */ "C_ULT_S\000" |
| 10307 | /* 24661 */ "CMP_ULT_S\000" |
| 10308 | /* 24671 */ "C_LT_S\000" |
| 10309 | /* 24678 */ "CMP_LT_S\000" |
| 10310 | /* 24687 */ "RINT_S\000" |
| 10311 | /* 24694 */ "FSQRT_S\000" |
| 10312 | /* 24702 */ "RSQRT_S\000" |
| 10313 | /* 24710 */ "MOVT_S\000" |
| 10314 | /* 24717 */ "PseudoSELECTFP_T_S\000" |
| 10315 | /* 24736 */ "FDIV_S\000" |
| 10316 | /* 24743 */ "FMOV_S\000" |
| 10317 | /* 24750 */ "PseudoTRUNC_W_S\000" |
| 10318 | /* 24766 */ "ROUND_W_S\000" |
| 10319 | /* 24776 */ "CEIL_W_S\000" |
| 10320 | /* 24785 */ "FLOOR_W_S\000" |
| 10321 | /* 24795 */ "CVT_W_S\000" |
| 10322 | /* 24803 */ "MAX_S\000" |
| 10323 | /* 24809 */ "SELNEZ_S\000" |
| 10324 | /* 24818 */ "SELEQZ_S\000" |
| 10325 | /* 24827 */ "BC1T\000" |
| 10326 | /* 24832 */ "G_SSUBSAT\000" |
| 10327 | /* 24842 */ "G_USUBSAT\000" |
| 10328 | /* 24852 */ "G_SADDSAT\000" |
| 10329 | /* 24862 */ "G_UADDSAT\000" |
| 10330 | /* 24872 */ "G_SSHLSAT\000" |
| 10331 | /* 24882 */ "G_USHLSAT\000" |
| 10332 | /* 24892 */ "G_SMULFIXSAT\000" |
| 10333 | /* 24905 */ "G_UMULFIXSAT\000" |
| 10334 | /* 24918 */ "G_SDIVFIXSAT\000" |
| 10335 | /* 24931 */ "G_UDIVFIXSAT\000" |
| 10336 | /* 24944 */ "G_ATOMICRMW_USUB_SAT\000" |
| 10337 | /* 24965 */ "G_FPTOSI_SAT\000" |
| 10338 | /* 24978 */ "G_FPTOUI_SAT\000" |
| 10339 | /* 24991 */ "G_EXTRACT\000" |
| 10340 | /* 25001 */ "G_SELECT\000" |
| 10341 | /* 25010 */ "G_BRINDIRECT\000" |
| 10342 | /* 25023 */ "DERET\000" |
| 10343 | /* 25029 */ "PATCHABLE_RET\000" |
| 10344 | /* 25043 */ "G_MEMSET\000" |
| 10345 | /* 25052 */ "BGT\000" |
| 10346 | /* 25056 */ "WAIT\000" |
| 10347 | /* 25061 */ "PATCHABLE_FUNCTION_EXIT\000" |
| 10348 | /* 25085 */ "G_BRJT\000" |
| 10349 | /* 25092 */ "BLT\000" |
| 10350 | /* 25096 */ "G_EXTRACT_VECTOR_ELT\000" |
| 10351 | /* 25117 */ "G_INSERT_VECTOR_ELT\000" |
| 10352 | /* 25137 */ "SLT\000" |
| 10353 | /* 25141 */ "TLT\000" |
| 10354 | /* 25145 */ "PseudoDMULT\000" |
| 10355 | /* 25157 */ "PseudoMULT\000" |
| 10356 | /* 25168 */ "DMT\000" |
| 10357 | /* 25172 */ "EMT\000" |
| 10358 | /* 25176 */ "G_FCONSTANT\000" |
| 10359 | /* 25188 */ "G_CONSTANT\000" |
| 10360 | /* 25199 */ "G_INTRINSIC_CONVERGENT\000" |
| 10361 | /* 25222 */ "STATEPOINT\000" |
| 10362 | /* 25233 */ "PATCHPOINT\000" |
| 10363 | /* 25244 */ "G_PTRTOINT\000" |
| 10364 | /* 25255 */ "G_FRINT\000" |
| 10365 | /* 25263 */ "G_INTRINSIC_LLRINT\000" |
| 10366 | /* 25282 */ "G_INTRINSIC_LRINT\000" |
| 10367 | /* 25300 */ "G_FNEARBYINT\000" |
| 10368 | /* 25313 */ "G_VASTART\000" |
| 10369 | /* 25323 */ "LIFETIME_START\000" |
| 10370 | /* 25338 */ "G_INVOKE_REGION_START\000" |
| 10371 | /* 25360 */ "G_INSERT\000" |
| 10372 | /* 25369 */ "G_FSQRT\000" |
| 10373 | /* 25377 */ "G_STRICT_FSQRT\000" |
| 10374 | /* 25392 */ "G_BITCAST\000" |
| 10375 | /* 25402 */ "G_ADDRSPACE_CAST\000" |
| 10376 | /* 25419 */ "DBG_VALUE_LIST\000" |
| 10377 | /* 25434 */ "GINVT\000" |
| 10378 | /* 25440 */ "DEXT\000" |
| 10379 | /* 25445 */ "G_FPEXT\000" |
| 10380 | /* 25453 */ "G_SEXT\000" |
| 10381 | /* 25460 */ "G_ASSERT_SEXT\000" |
| 10382 | /* 25474 */ "G_ANYEXT\000" |
| 10383 | /* 25483 */ "G_ZEXT\000" |
| 10384 | /* 25490 */ "G_ASSERT_ZEXT\000" |
| 10385 | /* 25504 */ "PseudoMSUBU\000" |
| 10386 | /* 25516 */ "G_ABDU\000" |
| 10387 | /* 25523 */ "PseudoMADDU\000" |
| 10388 | /* 25535 */ "DMODU\000" |
| 10389 | /* 25541 */ "BGEU\000" |
| 10390 | /* 25546 */ "SGEU\000" |
| 10391 | /* 25551 */ "TGEU\000" |
| 10392 | /* 25556 */ "BLEU\000" |
| 10393 | /* 25561 */ "SLEU\000" |
| 10394 | /* 25566 */ "DMUHU\000" |
| 10395 | /* 25572 */ "TGEIU\000" |
| 10396 | /* 25578 */ "TTLTIU\000" |
| 10397 | /* 25585 */ "V3MULU\000" |
| 10398 | /* 25592 */ "DMULU\000" |
| 10399 | /* 25598 */ "VMULU\000" |
| 10400 | /* 25604 */ "DINSU\000" |
| 10401 | /* 25610 */ "BGTU\000" |
| 10402 | /* 25615 */ "BLTU\000" |
| 10403 | /* 25620 */ "TLTU\000" |
| 10404 | /* 25625 */ "DEXTU\000" |
| 10405 | /* 25631 */ "DDIVU\000" |
| 10406 | /* 25637 */ "G_TRUNC_SSAT_U\000" |
| 10407 | /* 25652 */ "G_TRUNC_USAT_U\000" |
| 10408 | /* 25667 */ "DSRAV\000" |
| 10409 | /* 25673 */ "BITREV\000" |
| 10410 | /* 25680 */ "DDIV\000" |
| 10411 | /* 25685 */ "G_FDIV\000" |
| 10412 | /* 25692 */ "G_STRICT_FDIV\000" |
| 10413 | /* 25706 */ "PseudoDSDIV\000" |
| 10414 | /* 25718 */ "G_SDIV\000" |
| 10415 | /* 25725 */ "PseudoSDIV\000" |
| 10416 | /* 25736 */ "PseudoDUDIV\000" |
| 10417 | /* 25748 */ "G_UDIV\000" |
| 10418 | /* 25755 */ "PseudoUDIV\000" |
| 10419 | /* 25766 */ "DSLLV\000" |
| 10420 | /* 25772 */ "DSRLV\000" |
| 10421 | /* 25778 */ "G_GET_FPENV\000" |
| 10422 | /* 25790 */ "G_RESET_FPENV\000" |
| 10423 | /* 25804 */ "G_SET_FPENV\000" |
| 10424 | /* 25816 */ "TLBINV\000" |
| 10425 | /* 25823 */ "TLBGINV\000" |
| 10426 | /* 25831 */ "SHILOV\000" |
| 10427 | /* 25838 */ "EXTPDPV\000" |
| 10428 | /* 25846 */ "EXTPV\000" |
| 10429 | /* 25852 */ "DROTRV\000" |
| 10430 | /* 25859 */ "INSV\000" |
| 10431 | /* 25864 */ "AND_V\000" |
| 10432 | /* 25870 */ "MOVE_V\000" |
| 10433 | /* 25877 */ "BSEL_V\000" |
| 10434 | /* 25884 */ "NOR_V\000" |
| 10435 | /* 25890 */ "XOR_V\000" |
| 10436 | /* 25896 */ "BZ_V\000" |
| 10437 | /* 25901 */ "BMZ_V\000" |
| 10438 | /* 25907 */ "BNZ_V\000" |
| 10439 | /* 25913 */ "BMNZ_V\000" |
| 10440 | /* 25920 */ "CRC32W\000" |
| 10441 | /* 25927 */ "CRC32CW\000" |
| 10442 | /* 25935 */ "LW\000" |
| 10443 | /* 25938 */ "G_FPOW\000" |
| 10444 | /* 25945 */ "SW\000" |
| 10445 | /* 25948 */ "PseudoCVT_D32_W\000" |
| 10446 | /* 25964 */ "FLOG2_W\000" |
| 10447 | /* 25972 */ "FEXP2_W\000" |
| 10448 | /* 25980 */ "PseudoCVT_D64_W\000" |
| 10449 | /* 25996 */ "SRA_W\000" |
| 10450 | /* 26002 */ "ADD_A_W\000" |
| 10451 | /* 26010 */ "FMIN_A_W\000" |
| 10452 | /* 26019 */ "ADDS_A_W\000" |
| 10453 | /* 26028 */ "FMAX_A_W\000" |
| 10454 | /* 26037 */ "FSUB_W\000" |
| 10455 | /* 26044 */ "FMSUB_W\000" |
| 10456 | /* 26052 */ "NLOC_W\000" |
| 10457 | /* 26059 */ "NLZC_W\000" |
| 10458 | /* 26066 */ "FADD_W\000" |
| 10459 | /* 26073 */ "FMADD_W\000" |
| 10460 | /* 26081 */ "SLD_W\000" |
| 10461 | /* 26087 */ "PCKOD_W\000" |
| 10462 | /* 26095 */ "ILVOD_W\000" |
| 10463 | /* 26103 */ "FCLE_W\000" |
| 10464 | /* 26110 */ "FSLE_W\000" |
| 10465 | /* 26117 */ "FCULE_W\000" |
| 10466 | /* 26125 */ "FSULE_W\000" |
| 10467 | /* 26133 */ "FCNE_W\000" |
| 10468 | /* 26140 */ "FSNE_W\000" |
| 10469 | /* 26147 */ "FCUNE_W\000" |
| 10470 | /* 26155 */ "FSUNE_W\000" |
| 10471 | /* 26163 */ "INSVE_W\000" |
| 10472 | /* 26171 */ "FCAF_W\000" |
| 10473 | /* 26178 */ "FSAF_W\000" |
| 10474 | /* 26185 */ "VSHF_W\000" |
| 10475 | /* 26192 */ "BNEG_W\000" |
| 10476 | /* 26199 */ "PRECR_SRA_PH_W\000" |
| 10477 | /* 26214 */ "PRECRQ_PH_W\000" |
| 10478 | /* 26226 */ "PRECR_SRA_R_PH_W\000" |
| 10479 | /* 26243 */ "PRECRQ_RS_PH_W\000" |
| 10480 | /* 26258 */ "SUBQH_W\000" |
| 10481 | /* 26266 */ "ADDQH_W\000" |
| 10482 | /* 26274 */ "SRAI_W\000" |
| 10483 | /* 26281 */ "SLDI_W\000" |
| 10484 | /* 26288 */ "BNEGI_W\000" |
| 10485 | /* 26296 */ "SLLI_W\000" |
| 10486 | /* 26303 */ "SRLI_W\000" |
| 10487 | /* 26310 */ "BINSLI_W\000" |
| 10488 | /* 26319 */ "CEQI_W\000" |
| 10489 | /* 26326 */ "SRARI_W\000" |
| 10490 | /* 26334 */ "BCLRI_W\000" |
| 10491 | /* 26342 */ "SRLRI_W\000" |
| 10492 | /* 26350 */ "BINSRI_W\000" |
| 10493 | /* 26359 */ "SPLATI_W\000" |
| 10494 | /* 26368 */ "BSETI_W\000" |
| 10495 | /* 26376 */ "SUBVI_W\000" |
| 10496 | /* 26384 */ "ADDVI_W\000" |
| 10497 | /* 26392 */ "FILL_W\000" |
| 10498 | /* 26399 */ "SLL_W\000" |
| 10499 | /* 26405 */ "FEXUPL_W\000" |
| 10500 | /* 26414 */ "FFQL_W\000" |
| 10501 | /* 26421 */ "SRL_W\000" |
| 10502 | /* 26427 */ "BINSL_W\000" |
| 10503 | /* 26435 */ "FMUL_W\000" |
| 10504 | /* 26442 */ "ILVL_W\000" |
| 10505 | /* 26449 */ "DPAQ_SA_L_W\000" |
| 10506 | /* 26461 */ "DPSQ_SA_L_W\000" |
| 10507 | /* 26473 */ "FMIN_W\000" |
| 10508 | /* 26480 */ "FCUN_W\000" |
| 10509 | /* 26487 */ "FSUN_W\000" |
| 10510 | /* 26494 */ "FEXDO_W\000" |
| 10511 | /* 26502 */ "FRCP_W\000" |
| 10512 | /* 26509 */ "FCEQ_W\000" |
| 10513 | /* 26516 */ "FSEQ_W\000" |
| 10514 | /* 26523 */ "FCUEQ_W\000" |
| 10515 | /* 26531 */ "FSUEQ_W\000" |
| 10516 | /* 26539 */ "FTQ_W\000" |
| 10517 | /* 26545 */ "MSUB_Q_W\000" |
| 10518 | /* 26554 */ "MADD_Q_W\000" |
| 10519 | /* 26563 */ "MUL_Q_W\000" |
| 10520 | /* 26571 */ "MSUBR_Q_W\000" |
| 10521 | /* 26581 */ "MADDR_Q_W\000" |
| 10522 | /* 26591 */ "MULR_Q_W\000" |
| 10523 | /* 26600 */ "SRAR_W\000" |
| 10524 | /* 26607 */ "LDR_W\000" |
| 10525 | /* 26613 */ "BCLR_W\000" |
| 10526 | /* 26620 */ "SRLR_W\000" |
| 10527 | /* 26627 */ "FCOR_W\000" |
| 10528 | /* 26634 */ "FSOR_W\000" |
| 10529 | /* 26641 */ "FEXUPR_W\000" |
| 10530 | /* 26650 */ "FFQR_W\000" |
| 10531 | /* 26657 */ "BINSR_W\000" |
| 10532 | /* 26665 */ "STR_W\000" |
| 10533 | /* 26671 */ "EXTR_W\000" |
| 10534 | /* 26678 */ "ILVR_W\000" |
| 10535 | /* 26685 */ "SHRA_R_W\000" |
| 10536 | /* 26694 */ "SUBQH_R_W\000" |
| 10537 | /* 26704 */ "ADDQH_R_W\000" |
| 10538 | /* 26714 */ "EXTR_R_W\000" |
| 10539 | /* 26723 */ "SHRAV_R_W\000" |
| 10540 | /* 26733 */ "EXTRV_R_W\000" |
| 10541 | /* 26743 */ "FABS_W\000" |
| 10542 | /* 26750 */ "MULQ_RS_W\000" |
| 10543 | /* 26760 */ "EXTR_RS_W\000" |
| 10544 | /* 26770 */ "EXTRV_RS_W\000" |
| 10545 | /* 26781 */ "FCLASS_W\000" |
| 10546 | /* 26790 */ "ASUB_S_W\000" |
| 10547 | /* 26799 */ "HSUB_S_W\000" |
| 10548 | /* 26808 */ "DPSUB_S_W\000" |
| 10549 | /* 26818 */ "FTRUNC_S_W\000" |
| 10550 | /* 26829 */ "HADD_S_W\000" |
| 10551 | /* 26838 */ "DPADD_S_W\000" |
| 10552 | /* 26848 */ "MOD_S_W\000" |
| 10553 | /* 26856 */ "CLE_S_W\000" |
| 10554 | /* 26864 */ "AVE_S_W\000" |
| 10555 | /* 26872 */ "CLEI_S_W\000" |
| 10556 | /* 26881 */ "MINI_S_W\000" |
| 10557 | /* 26890 */ "CLTI_S_W\000" |
| 10558 | /* 26899 */ "MAXI_S_W\000" |
| 10559 | /* 26908 */ "SHLL_S_W\000" |
| 10560 | /* 26917 */ "MIN_S_W\000" |
| 10561 | /* 26925 */ "DOTP_S_W\000" |
| 10562 | /* 26934 */ "SUBQ_S_W\000" |
| 10563 | /* 26943 */ "ADDQ_S_W\000" |
| 10564 | /* 26952 */ "MULQ_S_W\000" |
| 10565 | /* 26961 */ "ABSQ_S_W\000" |
| 10566 | /* 26970 */ "AVER_S_W\000" |
| 10567 | /* 26979 */ "SUBS_S_W\000" |
| 10568 | /* 26988 */ "ADDS_S_W\000" |
| 10569 | /* 26997 */ "SAT_S_W\000" |
| 10570 | /* 27005 */ "CLT_S_W\000" |
| 10571 | /* 27013 */ "FFINT_S_W\000" |
| 10572 | /* 27023 */ "FTINT_S_W\000" |
| 10573 | /* 27033 */ "PseudoCVT_S_W\000" |
| 10574 | /* 27047 */ "SUBSUU_S_W\000" |
| 10575 | /* 27058 */ "DIV_S_W\000" |
| 10576 | /* 27066 */ "SHLLV_S_W\000" |
| 10577 | /* 27076 */ "MAX_S_W\000" |
| 10578 | /* 27084 */ "COPY_S_W\000" |
| 10579 | /* 27093 */ "SPLAT_W\000" |
| 10580 | /* 27101 */ "BSET_W\000" |
| 10581 | /* 27108 */ "FCLT_W\000" |
| 10582 | /* 27115 */ "FSLT_W\000" |
| 10583 | /* 27122 */ "FCULT_W\000" |
| 10584 | /* 27130 */ "FSULT_W\000" |
| 10585 | /* 27138 */ "PCNT_W\000" |
| 10586 | /* 27145 */ "FRINT_W\000" |
| 10587 | /* 27153 */ "INSERT_W\000" |
| 10588 | /* 27162 */ "FSQRT_W\000" |
| 10589 | /* 27170 */ "FRSQRT_W\000" |
| 10590 | /* 27179 */ "ST_W\000" |
| 10591 | /* 27184 */ "ASUB_U_W\000" |
| 10592 | /* 27193 */ "HSUB_U_W\000" |
| 10593 | /* 27202 */ "DPSUB_U_W\000" |
| 10594 | /* 27212 */ "FTRUNC_U_W\000" |
| 10595 | /* 27223 */ "HADD_U_W\000" |
| 10596 | /* 27232 */ "DPADD_U_W\000" |
| 10597 | /* 27242 */ "MOD_U_W\000" |
| 10598 | /* 27250 */ "CLE_U_W\000" |
| 10599 | /* 27258 */ "AVE_U_W\000" |
| 10600 | /* 27266 */ "CLEI_U_W\000" |
| 10601 | /* 27275 */ "MINI_U_W\000" |
| 10602 | /* 27284 */ "CLTI_U_W\000" |
| 10603 | /* 27293 */ "MAXI_U_W\000" |
| 10604 | /* 27302 */ "MIN_U_W\000" |
| 10605 | /* 27310 */ "DOTP_U_W\000" |
| 10606 | /* 27319 */ "AVER_U_W\000" |
| 10607 | /* 27328 */ "SUBS_U_W\000" |
| 10608 | /* 27337 */ "ADDS_U_W\000" |
| 10609 | /* 27346 */ "SUBSUS_U_W\000" |
| 10610 | /* 27357 */ "SAT_U_W\000" |
| 10611 | /* 27365 */ "CLT_U_W\000" |
| 10612 | /* 27373 */ "FFINT_U_W\000" |
| 10613 | /* 27383 */ "FTINT_U_W\000" |
| 10614 | /* 27393 */ "DIV_U_W\000" |
| 10615 | /* 27401 */ "MAX_U_W\000" |
| 10616 | /* 27409 */ "COPY_U_W\000" |
| 10617 | /* 27418 */ "MSUBV_W\000" |
| 10618 | /* 27426 */ "MADDV_W\000" |
| 10619 | /* 27434 */ "PCKEV_W\000" |
| 10620 | /* 27442 */ "ILVEV_W\000" |
| 10621 | /* 27450 */ "FDIV_W\000" |
| 10622 | /* 27457 */ "MULV_W\000" |
| 10623 | /* 27464 */ "EXTRV_W\000" |
| 10624 | /* 27472 */ "FMAX_W\000" |
| 10625 | /* 27479 */ "BZ_W\000" |
| 10626 | /* 27484 */ "BNZ_W\000" |
| 10627 | /* 27490 */ "G_VECREDUCE_FMAX\000" |
| 10628 | /* 27507 */ "G_ATOMICRMW_FMAX\000" |
| 10629 | /* 27524 */ "G_VECREDUCE_SMAX\000" |
| 10630 | /* 27541 */ "G_SMAX\000" |
| 10631 | /* 27548 */ "G_VECREDUCE_UMAX\000" |
| 10632 | /* 27565 */ "G_UMAX\000" |
| 10633 | /* 27572 */ "G_ATOMICRMW_UMAX\000" |
| 10634 | /* 27589 */ "G_ATOMICRMW_MAX\000" |
| 10635 | /* 27605 */ "MFTACX\000" |
| 10636 | /* 27612 */ "MTTACX\000" |
| 10637 | /* 27619 */ "G_FRAME_INDEX\000" |
| 10638 | /* 27633 */ "G_SBFX\000" |
| 10639 | /* 27640 */ "G_UBFX\000" |
| 10640 | /* 27647 */ "LHX\000" |
| 10641 | /* 27651 */ "G_SMULFIX\000" |
| 10642 | /* 27661 */ "G_UMULFIX\000" |
| 10643 | /* 27671 */ "G_SDIVFIX\000" |
| 10644 | /* 27681 */ "G_UDIVFIX\000" |
| 10645 | /* 27691 */ "JALX\000" |
| 10646 | /* 27696 */ "LBUX\000" |
| 10647 | /* 27701 */ "LWX\000" |
| 10648 | /* 27705 */ "G_MEMCPY\000" |
| 10649 | /* 27714 */ "COPY\000" |
| 10650 | /* 27719 */ "CONSTPOOL_ENTRY\000" |
| 10651 | /* 27735 */ "CONVERGENCECTRL_ENTRY\000" |
| 10652 | /* 27757 */ "BGEZ\000" |
| 10653 | /* 27762 */ "BLEZ\000" |
| 10654 | /* 27767 */ "BC1NEZ\000" |
| 10655 | /* 27774 */ "BC2NEZ\000" |
| 10656 | /* 27781 */ "SELNEZ\000" |
| 10657 | /* 27788 */ "DCLZ\000" |
| 10658 | /* 27793 */ "G_CTLZ\000" |
| 10659 | /* 27800 */ "BC1EQZ\000" |
| 10660 | /* 27807 */ "BC2EQZ\000" |
| 10661 | /* 27814 */ "SELEQZ\000" |
| 10662 | /* 27821 */ "BGTZ\000" |
| 10663 | /* 27826 */ "BLTZ\000" |
| 10664 | /* 27831 */ "G_CTTZ\000" |
| 10665 | /* 27838 */ "SelBneZ\000" |
| 10666 | /* 27846 */ "SelBeqZ\000" |
| 10667 | /* 27854 */ "JalOneReg\000" |
| 10668 | /* 27864 */ "JalTwoReg\000" |
| 10669 | /* 27874 */ "PseudoIndirectHazardBranch\000" |
| 10670 | /* 27901 */ "PseudoIndirectBranch\000" |
| 10671 | /* 27922 */ "Ulh\000" |
| 10672 | /* 27926 */ "Ush\000" |
| 10673 | /* 27930 */ "DADDi\000" |
| 10674 | /* 27936 */ "ANDi\000" |
| 10675 | /* 27941 */ "SNEi\000" |
| 10676 | /* 27946 */ "SEQi\000" |
| 10677 | /* 27951 */ "XORi\000" |
| 10678 | /* 27956 */ "SLTi\000" |
| 10679 | /* 27961 */ "LONG_BRANCH_LUi\000" |
| 10680 | /* 27977 */ "SelTBtneZCmpi\000" |
| 10681 | /* 27991 */ "SelTBteqZCmpi\000" |
| 10682 | /* 28005 */ "SelTBtneZSlti\000" |
| 10683 | /* 28019 */ "SelTBteqZSlti\000" |
| 10684 | /* 28033 */ "SGEImm\000" |
| 10685 | /* 28040 */ "SLEImm\000" |
| 10686 | /* 28047 */ "DROLImm\000" |
| 10687 | /* 28055 */ "NORImm\000" |
| 10688 | /* 28062 */ "DRORImm\000" |
| 10689 | /* 28070 */ "SGTImm\000" |
| 10690 | /* 28077 */ "SGEUImm\000" |
| 10691 | /* 28085 */ "SLEUImm\000" |
| 10692 | /* 28093 */ "SGTUImm\000" |
| 10693 | /* 28101 */ "BneImm\000" |
| 10694 | /* 28108 */ "BeqImm\000" |
| 10695 | /* 28115 */ "PseudoReturn\000" |
| 10696 | /* 28128 */ "JALRHB64Pseudo\000" |
| 10697 | /* 28143 */ "JALR64Pseudo\000" |
| 10698 | /* 28156 */ "JALRHBPseudo\000" |
| 10699 | /* 28169 */ "JALRPseudo\000" |
| 10700 | /* 28180 */ "B_MMR6_Pseudo\000" |
| 10701 | /* 28194 */ "B_MM_Pseudo\000" |
| 10702 | /* 28206 */ "SDIV_MM_Pseudo\000" |
| 10703 | /* 28221 */ "UDIV_MM_Pseudo\000" |
| 10704 | /* 28236 */ "LDMacro\000" |
| 10705 | /* 28244 */ "SDMacro\000" |
| 10706 | /* 28252 */ "SNEMacro\000" |
| 10707 | /* 28261 */ "SNEIMacro\000" |
| 10708 | /* 28271 */ "SEQIMacro\000" |
| 10709 | /* 28281 */ "DSRemIMacro\000" |
| 10710 | /* 28293 */ "DURemIMacro\000" |
| 10711 | /* 28305 */ "DSDivIMacro\000" |
| 10712 | /* 28317 */ "DUDivIMacro\000" |
| 10713 | /* 28329 */ "DMULMacro\000" |
| 10714 | /* 28339 */ "DMULOMacro\000" |
| 10715 | /* 28350 */ "SEQMacro\000" |
| 10716 | /* 28359 */ "ABSMacro\000" |
| 10717 | /* 28368 */ "DMULOUMacro\000" |
| 10718 | /* 28380 */ "DSRemMacro\000" |
| 10719 | /* 28391 */ "DURemMacro\000" |
| 10720 | /* 28402 */ "BGEImmMacro\000" |
| 10721 | /* 28414 */ "BLEImmMacro\000" |
| 10722 | /* 28426 */ "BGELImmMacro\000" |
| 10723 | /* 28439 */ "BLELImmMacro\000" |
| 10724 | /* 28452 */ "BNELImmMacro\000" |
| 10725 | /* 28465 */ "BEQLImmMacro\000" |
| 10726 | /* 28478 */ "BGTLImmMacro\000" |
| 10727 | /* 28491 */ "BLTLImmMacro\000" |
| 10728 | /* 28504 */ "BGEULImmMacro\000" |
| 10729 | /* 28518 */ "BLEULImmMacro\000" |
| 10730 | /* 28532 */ "DMULImmMacro\000" |
| 10731 | /* 28545 */ "BGTULImmMacro\000" |
| 10732 | /* 28559 */ "BLTULImmMacro\000" |
| 10733 | /* 28573 */ "BGTImmMacro\000" |
| 10734 | /* 28585 */ "BLTImmMacro\000" |
| 10735 | /* 28597 */ "BGEUImmMacro\000" |
| 10736 | /* 28610 */ "BLEUImmMacro\000" |
| 10737 | /* 28623 */ "BGTUImmMacro\000" |
| 10738 | /* 28636 */ "BLTUImmMacro\000" |
| 10739 | /* 28649 */ "DSDivMacro\000" |
| 10740 | /* 28660 */ "DUDivMacro\000" |
| 10741 | /* 28671 */ "LONG_BRANCH_LUi2Op\000" |
| 10742 | /* 28690 */ "LONG_BRANCH_DADDiu2Op\000" |
| 10743 | /* 28712 */ "LONG_BRANCH_ADDiu2Op\000" |
| 10744 | /* 28733 */ "SelTBtneZCmp\000" |
| 10745 | /* 28746 */ "SelTBteqZCmp\000" |
| 10746 | /* 28759 */ "SaaAddr\000" |
| 10747 | /* 28767 */ "SaadAddr\000" |
| 10748 | /* 28776 */ "ERet\000" |
| 10749 | /* 28781 */ "SelTBtneZSlt\000" |
| 10750 | /* 28794 */ "SelTBteqZSlt\000" |
| 10751 | /* 28807 */ "LBu\000" |
| 10752 | /* 28811 */ "DSUBu\000" |
| 10753 | /* 28817 */ "BADDu\000" |
| 10754 | /* 28823 */ "DADDu\000" |
| 10755 | /* 28829 */ "LHu\000" |
| 10756 | /* 28833 */ "SLTu\000" |
| 10757 | /* 28838 */ "PseudoDMULTu\000" |
| 10758 | /* 28851 */ "PseudoMULTu\000" |
| 10759 | /* 28863 */ "LWu\000" |
| 10760 | /* 28867 */ "Ulhu\000" |
| 10761 | /* 28872 */ "LONG_BRANCH_DADDiu\000" |
| 10762 | /* 28891 */ "LEA_ADDiu\000" |
| 10763 | /* 28901 */ "LONG_BRANCH_ADDiu\000" |
| 10764 | /* 28919 */ "SLTiu\000" |
| 10765 | /* 28925 */ "SelTBtneZSltiu\000" |
| 10766 | /* 28940 */ "SelTBteqZSltiu\000" |
| 10767 | /* 28955 */ "SelTBtneZSltu\000" |
| 10768 | /* 28969 */ "SelTBteqZSltu\000" |
| 10769 | /* 28983 */ "Ulw\000" |
| 10770 | /* 28987 */ "Usw\000" |
| 10771 | }; |
| 10772 | #ifdef __GNUC__ |
| 10773 | #pragma GCC diagnostic pop |
| 10774 | #endif |
| 10775 | |
| 10776 | extern const unsigned MipsInstrNameIndices[] = { |
| 10777 | 15620U, 21205U, 23243U, 21615U, 15986U, 15967U, 15995U, 16269U, |
| 10778 | 13925U, 13940U, 13805U, 13792U, 13979U, 23988U, 13609U, 25419U, |
| 10779 | 13823U, 15616U, 15976U, 13273U, 27714U, 15843U, 13445U, 25323U, |
| 10780 | 11697U, 13220U, 13261U, 22599U, 16241U, 25233U, 11809U, 23080U, |
| 10781 | 14072U, 25222U, 13509U, 22830U, 22817U, 23312U, 25029U, 25061U, |
| 10782 | 16173U, 16220U, 16193U, 16027U, 13600U, 23277U, 22514U, 13490U, |
| 10783 | 27735U, 23530U, 22783U, 13657U, 25460U, 25490U, 21432U, 11580U, |
| 10784 | 10313U, 16425U, 25718U, 25748U, 16526U, 16533U, 16540U, 16550U, |
| 10785 | 11660U, 23748U, 23711U, 23890U, 25516U, 23578U, 16137U, 23566U, |
| 10786 | 16126U, 13803U, 15618U, 27619U, 13619U, 13634U, 16279U, 24991U, |
| 10787 | 23897U, 25360U, 23914U, 23634U, 11199U, 23971U, 25244U, 23834U, |
| 10788 | 25392U, 13708U, 23288U, 11778U, 11173U, 11760U, 25282U, 25263U, |
| 10789 | 21396U, 23337U, 23356U, 11453U, 11397U, 11427U, 11438U, 11378U, |
| 10790 | 11408U, 13563U, 13547U, 24018U, 13993U, 14010U, 11596U, 10319U, |
| 10791 | 11666U, 11627U, 23753U, 23717U, 27589U, 21558U, 27572U, 21541U, |
| 10792 | 11536U, 10285U, 27507U, 21476U, 21312U, 21259U, 22661U, 22639U, |
| 10793 | 11719U, 24944U, 13253U, 14114U, 11710U, 25010U, 25338U, 11085U, |
| 10794 | 24066U, 25199U, 24093U, 25474U, 11191U, 24586U, 25637U, 25652U, |
| 10795 | 25188U, 25176U, 25313U, 14064U, 25453U, 13966U, 25483U, 16112U, |
| 10796 | 23515U, 23501U, 16105U, 23508U, 23827U, 16326U, 22756U, 22749U, |
| 10797 | 22763U, 22770U, 25001U, 21672U, 13298U, 21656U, 13245U, 21664U, |
| 10798 | 13290U, 21648U, 13237U, 22583U, 22575U, 14137U, 14129U, 24862U, |
| 10799 | 24852U, 24842U, 24832U, 24882U, 24872U, 27651U, 27661U, 24892U, |
| 10800 | 24905U, 27671U, 27681U, 24918U, 24931U, 11494U, 10264U, 16367U, |
| 10801 | 8518U, 11371U, 25685U, 16505U, 13748U, 25938U, 15698U, 23132U, |
| 10802 | 1223U, 9U, 14057U, 1196U, 0U, 23107U, 23139U, 13854U, |
| 10803 | 25445U, 11163U, 15646U, 15670U, 22718U, 22727U, 24965U, 24978U, |
| 10804 | 23877U, 21447U, 24005U, 13717U, 21361U, 21371U, 13347U, 13362U, |
| 10805 | 21248U, 21301U, 21333U, 21347U, 25778U, 25804U, 25790U, 13306U, |
| 10806 | 13334U, 13319U, 14027U, 14042U, 11586U, 15857U, 21510U, 27541U, |
| 10807 | 21534U, 27565U, 23884U, 11751U, 11741U, 23231U, 25085U, 13423U, |
| 10808 | 23615U, 23595U, 25117U, 25096U, 23649U, 23680U, 23666U, 24048U, |
| 10809 | 27831U, 13774U, 27793U, 13756U, 23929U, 22809U, 22683U, 13581U, |
| 10810 | 16118U, 23954U, 21582U, 23961U, 21389U, 23946U, 21574U, 21381U, |
| 10811 | 1209U, 14684U, 14153U, 14145U, 25369U, 23557U, 25255U, 25300U, |
| 10812 | 25402U, 23256U, 13432U, 11225U, 13678U, 13532U, 11522U, 10271U, |
| 10813 | 16395U, 25692U, 16512U, 8524U, 25377U, 23116U, 23376U, 23392U, |
| 10814 | 27705U, 13474U, 13690U, 25043U, 22591U, 22632U, 22608U, 22620U, |
| 10815 | 11501U, 16374U, 11477U, 16350U, 27490U, 21459U, 21280U, 21227U, |
| 10816 | 11564U, 16409U, 11644U, 23733U, 23695U, 27524U, 21493U, 27548U, |
| 10817 | 21517U, 27633U, 27640U, 28359U, 21631U, 23065U, 22016U, 22100U, |
| 10818 | 22316U, 4082U, 9404U, 893U, 8760U, 3107U, 9082U, 8388U, |
| 10819 | 9719U, 3964U, 9244U, 775U, 8600U, 2937U, 8922U, 8276U, |
| 10820 | 9565U, 4005U, 9299U, 816U, 8655U, 2978U, 8977U, 8315U, |
| 10821 | 9618U, 4162U, 9512U, 973U, 8868U, 3253U, 9190U, 8464U, |
| 10822 | 9823U, 4046U, 9354U, 857U, 8710U, 3071U, 9032U, 8354U, |
| 10823 | 9671U, 3984U, 9271U, 795U, 8627U, 2957U, 8949U, 8295U, |
| 10824 | 9591U, 4122U, 9458U, 933U, 8814U, 3147U, 9136U, 8426U, |
| 10825 | 9771U, 3944U, 9217U, 755U, 8573U, 2917U, 8895U, 8257U, |
| 10826 | 9539U, 4141U, 9484U, 952U, 8840U, 3232U, 9162U, 8444U, |
| 10827 | 9796U, 4025U, 9326U, 836U, 8682U, 3050U, 9004U, 8334U, |
| 10828 | 9644U, 4102U, 9431U, 913U, 8787U, 3127U, 9109U, 8407U, |
| 10829 | 9745U, 4066U, 9381U, 877U, 8737U, 3091U, 9059U, 8373U, |
| 10830 | 9697U, 9879U, 23236U, 19783U, 28465U, 13390U, 28402U, 16012U, |
| 10831 | 28426U, 25541U, 28597U, 16333U, 28504U, 25052U, 28573U, 16316U, |
| 10832 | 28478U, 25610U, 28623U, 16431U, 28545U, 13441U, 28414U, 16017U, |
| 10833 | 28439U, 25556U, 28610U, 16339U, 28518U, 25092U, 28585U, 16321U, |
| 10834 | 28491U, 25615U, 28636U, 16437U, 28559U, 28452U, 21714U, 22002U, |
| 10835 | 21895U, 22195U, 22086U, 22302U, 17975U, 28180U, 28194U, 28108U, |
| 10836 | 28101U, 4686U, 4233U, 4714U, 4263U, 4744U, 4775U, 4672U, |
| 10837 | 4218U, 4700U, 4248U, 4728U, 4760U, 2795U, 3565U, 131U, |
| 10838 | 27719U, 21942U, 22242U, 149U, 1153U, 28532U, 28329U, 28339U, |
| 10839 | 28368U, 16295U, 28047U, 23590U, 28062U, 28305U, 28649U, 28281U, |
| 10840 | 28380U, 28317U, 28660U, 28293U, 28391U, 28776U, 2808U, 3581U, |
| 10841 | 12512U, 26743U, 21680U, 21697U, 21910U, 22210U, 4833U, 21730U, |
| 10842 | 22386U, 21777U, 22429U, 21925U, 21753U, 22407U, 22225U, 21823U, |
| 10843 | 22471U, 21800U, 22450U, 21847U, 22493U, 28143U, 28128U, 28156U, |
| 10844 | 28169U, 6970U, 27854U, 27864U, 28236U, 12441U, 26607U, 3930U, |
| 10845 | 8232U, 2062U, 22842U, 22927U, 28901U, 28712U, 28872U, 28690U, |
| 10846 | 27961U, 28671U, 3611U, 19327U, 1121U, 3821U, 1088U, 3633U, |
| 10847 | 1111U, 3811U, 23415U, 1068U, 23782U, 23432U, 23799U, 1151U, |
| 10848 | 27605U, 52U, 137U, 22883U, 23768U, 112U, 15624U, 22558U, |
| 10849 | 1135U, 3850U, 21957U, 22257U, 21980U, 22280U, 27612U, 64U, |
| 10850 | 155U, 22890U, 23775U, 119U, 15635U, 22569U, 28533U, 28340U, |
| 10851 | 28369U, 5093U, 5226U, 5125U, 5278U, 22779U, 28055U, 3744U, |
| 10852 | 22031U, 22115U, 22331U, 22032U, 22116U, 22332U, 10059U, 9961U, |
| 10853 | 10174U, 14315U, 14210U, 14475U, 25948U, 16475U, 25980U, 16491U, |
| 10854 | 27033U, 25145U, 28838U, 25706U, 25736U, 15772U, 3166U, 27901U, |
| 10855 | 3676U, 5338U, 8209U, 21067U, 8003U, 27874U, 3647U, 5308U, |
| 10856 | 8181U, 11553U, 25523U, 20511U, 18307U, 15592U, 2856U, 18959U, |
| 10857 | 22541U, 3301U, 19348U, 10302U, 25504U, 20496U, 18238U, 15603U, |
| 10858 | 2869U, 22967U, 18973U, 25157U, 20475U, 28851U, 21168U, 14244U, |
| 10859 | 9996U, 28115U, 3835U, 25725U, 388U, 2380U, 15735U, 3007U, |
| 10860 | 24348U, 644U, 2693U, 15811U, 3211U, 24717U, 559U, 2608U, |
| 10861 | 15789U, 3185U, 24601U, 13164U, 683U, 24750U, 25755U, 16296U, |
| 10862 | 28048U, 23591U, 28063U, 9849U, 3915U, 212U, 28206U, 28244U, |
| 10863 | 28306U, 28650U, 28271U, 28350U, 13394U, 28033U, 3726U, 25546U, |
| 10864 | 28077U, 3771U, 28070U, 3753U, 28093U, 3791U, 13456U, 28040U, |
| 10865 | 3735U, 25561U, 28085U, 3781U, 3762U, 3801U, 28261U, 28252U, |
| 10866 | 21870U, 22061U, 22145U, 22170U, 22361U, 28282U, 28381U, 8244U, |
| 10867 | 2073U, 22856U, 22942U, 12499U, 26665U, 3937U, 19334U, 21883U, |
| 10868 | 22074U, 22158U, 22183U, 22374U, 28759U, 28767U, 27846U, 27838U, |
| 10869 | 28746U, 27991U, 28794U, 28019U, 28940U, 28969U, 28733U, 27977U, |
| 10870 | 28781U, 28005U, 28925U, 28955U, 5038U, 4497U, 4512U, 5050U, |
| 10871 | 5265U, 16148U, 13879U, 13861U, 13895U, 13911U, 13954U, 2826U, |
| 10872 | 9897U, 2018U, 18518U, 6847U, 19258U, 6979U, 22615U, 19379U, |
| 10873 | 28221U, 28318U, 28661U, 28294U, 28392U, 27922U, 28867U, 28983U, |
| 10874 | 27926U, 28987U, 22046U, 22130U, 22346U, 14434U, 18774U, 10119U, |
| 10875 | 1371U, 26961U, 20942U, 11473U, 11260U, 18260U, 6024U, 19459U, |
| 10876 | 17207U, 17620U, 19631U, 7889U, 14235U, 1474U, 14352U, 1529U, |
| 10877 | 26704U, 1887U, 26266U, 1859U, 14307U, 18670U, 14414U, 18761U, |
| 10878 | 26943U, 20930U, 3419U, 11284U, 18271U, 10357U, 11882U, 14719U, |
| 10879 | 26019U, 10765U, 12681U, 15208U, 26988U, 10957U, 13046U, 15457U, |
| 10880 | 27337U, 17837U, 5764U, 9987U, 1276U, 10097U, 1339U, 7859U, |
| 10881 | 14499U, 1617U, 10199U, 18161U, 14454U, 1589U, 10139U, 18108U, |
| 10882 | 10571U, 12246U, 14904U, 26384U, 11027U, 13127U, 15527U, 27427U, |
| 10883 | 11317U, 18280U, 10341U, 11865U, 14703U, 26002U, 18314U, 6246U, |
| 10884 | 27931U, 21091U, 28885U, 21187U, 28818U, 21145U, 21419U, 7037U, |
| 10885 | 11253U, 6012U, 11640U, 17648U, 5605U, 2196U, 17675U, 5638U, |
| 10886 | 10446U, 6902U, 18321U, 6255U, 25864U, 27936U, 3699U, 21099U, |
| 10887 | 11690U, 1431U, 10670U, 12528U, 15057U, 26790U, 10862U, 12893U, |
| 10888 | 15315U, 27184U, 15666U, 11247U, 6001U, 6930U, 10747U, 12663U, |
| 10889 | 15181U, 26970U, 10939U, 13028U, 15439U, 27319U, 10695U, 12602U, |
| 10890 | 15120U, 26864U, 10887U, 12967U, 15378U, 27258U, 4565U, 4441U, |
| 10891 | 4949U, 4593U, 4390U, 4889U, 4457U, 5252U, 5191U, 17632U, |
| 10892 | 28817U, 15867U, 11097U, 5880U, 21418U, 1792U, 85U, 231U, |
| 10893 | 225U, 239U, 11068U, 5545U, 27800U, 6187U, 13743U, 16047U, |
| 10894 | 18490U, 27767U, 6150U, 24827U, 16310U, 20436U, 27807U, 6200U, |
| 10895 | 27774U, 6163U, 10507U, 12196U, 14854U, 26334U, 10641U, 12447U, |
| 10896 | 15028U, 26613U, 5843U, 23148U, 3321U, 11279U, 2113U, 6047U, |
| 10897 | 16300U, 17882U, 11132U, 5940U, 11341U, 5592U, 2172U, 18298U, |
| 10898 | 6213U, 19680U, 11071U, 2085U, 5851U, 11295U, 2132U, 6086U, |
| 10899 | 27757U, 3519U, 15879U, 11108U, 5901U, 16253U, 19952U, 19093U, |
| 10900 | 11323U, 2148U, 6128U, 16451U, 21028U, 27821U, 3551U, 11140U, |
| 10901 | 5953U, 11347U, 2180U, 6224U, 16463U, 21051U, 10483U, 12172U, |
| 10902 | 14830U, 26310U, 10613U, 12295U, 14931U, 26427U, 10537U, 12212U, |
| 10903 | 14870U, 26350U, 10655U, 12491U, 15042U, 26657U, 25673U, 20575U, |
| 10904 | 22692U, 7057U, 27762U, 3526U, 11116U, 5914U, 11329U, 2156U, |
| 10905 | 6139U, 16457U, 21036U, 11290U, 2125U, 6076U, 11301U, 2140U, |
| 10906 | 6097U, 27826U, 3558U, 15886U, 11148U, 5966U, 16261U, 19963U, |
| 10907 | 19103U, 11353U, 2188U, 6235U, 16469U, 21059U, 10586U, 25913U, |
| 10908 | 10579U, 25901U, 13470U, 2789U, 11076U, 2092U, 5861U, 10453U, |
| 10909 | 12150U, 14808U, 26288U, 10425U, 12129U, 14787U, 26192U, 16022U, |
| 10910 | 17872U, 11124U, 5927U, 11335U, 5579U, 2164U, 18289U, 6176U, |
| 10911 | 18421U, 11307U, 6108U, 11062U, 13201U, 15562U, 25907U, 27484U, |
| 10912 | 11312U, 6118U, 746U, 1951U, 17149U, 15832U, 17703U, 5660U, |
| 10913 | 19077U, 6959U, 10461U, 25877U, 10555U, 12230U, 14888U, 26368U, |
| 10914 | 10834U, 12770U, 15287U, 27101U, 11057U, 13187U, 15557U, 25896U, |
| 10915 | 27479U, 4976U, 4622U, 4988U, 4635U, 4964U, 4609U, 4875U, |
| 10916 | 5300U, 4799U, 5292U, 4790U, 13402U, 13377U, 18349U, 18375U, |
| 10917 | 6790U, 8125U, 2475U, 6453U, 24441U, 7437U, 713U, 2756U, |
| 10918 | 6722U, 20768U, 24776U, 20400U, 7718U, 10492U, 12181U, 14839U, |
| 10919 | 26319U, 10628U, 12365U, 14954U, 26510U, 101U, 16598U, 17191U, |
| 10920 | 9860U, 23936U, 1015U, 1048U, 1102U, 12520U, 6595U, 24578U, |
| 10921 | 7579U, 10703U, 12610U, 15128U, 26872U, 10895U, 12975U, 15386U, |
| 10922 | 27266U, 10687U, 12594U, 15112U, 26856U, 10879U, 12959U, 15370U, |
| 10923 | 27250U, 22537U, 19341U, 7048U, 8157U, 10721U, 12628U, 15146U, |
| 10924 | 26890U, 10913U, 12993U, 15404U, 27284U, 10782U, 12698U, 15225U, |
| 10925 | 27005U, 10985U, 13074U, 15485U, 27365U, 27789U, 21044U, 7982U, |
| 10926 | 8174U, 10034U, 1290U, 9936U, 1244U, 10149U, 1386U, 10047U, |
| 10927 | 18066U, 9949U, 17993U, 10162U, 18121U, 10065U, 18081U, 9967U, |
| 10928 | 18008U, 10180U, 18136U, 6372U, 7332U, 12425U, 6581U, 14321U, |
| 10929 | 18681U, 24562U, 7565U, 12121U, 24367U, 12027U, 6343U, 14216U, |
| 10930 | 18600U, 24293U, 7303U, 12838U, 6654U, 14481U, 18801U, 24678U, |
| 10931 | 7638U, 12088U, 6357U, 24302U, 7317U, 12378U, 6535U, 24516U, |
| 10932 | 7519U, 11980U, 6297U, 24247U, 7257U, 12791U, 6608U, 24632U, |
| 10933 | 7592U, 12404U, 6550U, 24526U, 7534U, 12006U, 6312U, 24257U, |
| 10934 | 7272U, 12817U, 6623U, 24642U, 7607U, 12338U, 6506U, 24474U, |
| 10935 | 7490U, 12415U, 6566U, 24545U, 7550U, 12017U, 6328U, 24276U, |
| 10936 | 7288U, 12828U, 6639U, 24661U, 7623U, 12348U, 6521U, 24491U, |
| 10937 | 7505U, 10817U, 12753U, 15270U, 27084U, 11009U, 15509U, 27409U, |
| 10938 | 9874U, 9881U, 11460U, 14106U, 25927U, 11359U, 14089U, 25920U, |
| 10939 | 126U, 16614U, 17199U, 9867U, 24136U, 19998U, 25954U, 20687U, |
| 10940 | 16481U, 24146U, 20011U, 25986U, 20700U, 7011U, 2498U, 17405U, |
| 10941 | 6482U, 24460U, 20205U, 7466U, 3502U, 3469U, 3457U, 549U, |
| 10942 | 17010U, 2598U, 17493U, 16497U, 7024U, 3278U, 3486U, 27039U, |
| 10943 | 20954U, 7957U, 736U, 17136U, 2779U, 17607U, 24795U, 20425U, |
| 10944 | 7747U, 531U, 16986U, 2580U, 17469U, 24555U, 20259U, 380U, |
| 10945 | 16847U, 2372U, 17357U, 24342U, 20141U, 353U, 16811U, 2345U, |
| 10946 | 17333U, 24286U, 20111U, 606U, 17062U, 2655U, 17545U, 24671U, |
| 10947 | 20312U, 312U, 16758U, 2304U, 17280U, 24222U, 20066U, 322U, |
| 10948 | 16771U, 2314U, 17293U, 24230U, 20077U, 440U, 16898U, 2432U, |
| 10949 | 17380U, 24406U, 20184U, 576U, 17023U, 2625U, 17506U, 24616U, |
| 10950 | 20279U, 333U, 16785U, 2325U, 17307U, 24239U, 20089U, 586U, |
| 10951 | 17036U, 2635U, 17519U, 24624U, 20290U, 511U, 16960U, 2560U, |
| 10952 | 17443U, 24508U, 20237U, 362U, 16823U, 2354U, 17345U, 24328U, |
| 10953 | 20121U, 521U, 16973U, 2570U, 17456U, 24537U, 20248U, 343U, |
| 10954 | 16798U, 2335U, 17320U, 24268U, 20100U, 596U, 17049U, 2645U, |
| 10955 | 17532U, 24653U, 20301U, 483U, 16923U, 2532U, 17418U, 24484U, |
| 10956 | 20216U, 5073U, 4912U, 4539U, 11472U, 27930U, 28884U, 28823U, |
| 10957 | 15587U, 21425U, 15655U, 15665U, 22691U, 22536U, 8156U, 27788U, |
| 10958 | 8173U, 25680U, 25631U, 25023U, 20444U, 7799U, 25440U, 1058U, |
| 10959 | 21221U, 25625U, 15574U, 23941U, 21215U, 25604U, 25681U, 25632U, |
| 10960 | 7910U, 7920U, 10801U, 12737U, 15244U, 27058U, 10993U, 13102U, |
| 10961 | 15493U, 27393U, 18937U, 6904U, 9855U, 8088U, 18U, 106U, |
| 10962 | 1174U, 21589U, 24U, 11804U, 25535U, 25168U, 58U, 143U, |
| 10963 | 1180U, 21602U, 45U, 14692U, 25566U, 16345U, 25151U, 28844U, |
| 10964 | 25592U, 8148U, 12654U, 15172U, 26925U, 13019U, 15430U, 27310U, |
| 10965 | 12576U, 15094U, 26838U, 12941U, 15352U, 27232U, 14563U, 1674U, |
| 10966 | 14638U, 1726U, 26449U, 20778U, 14600U, 18850U, 15937U, 19166U, |
| 10967 | 23209U, 19755U, 14664U, 1762U, 14543U, 1644U, 22804U, 14577U, |
| 10968 | 1693U, 14651U, 1744U, 26461U, 20793U, 14626U, 18882U, 12546U, |
| 10969 | 15075U, 26808U, 12911U, 15333U, 27202U, 15948U, 19180U, 23220U, |
| 10970 | 19769U, 14674U, 1777U, 14591U, 1712U, 23821U, 1007U, 25852U, |
| 10971 | 14096U, 25712U, 11612U, 16274U, 993U, 1038U, 25766U, 8568U, |
| 10972 | 247U, 25667U, 16305U, 1000U, 25772U, 10259U, 28811U, 25742U, |
| 10973 | 23099U, 13522U, 7129U, 5159U, 5137U, 9893U, 17980U, 5795U, |
| 10974 | 15579U, 18945U, 6912U, 25172U, 25024U, 11156U, 5979U, 20445U, |
| 10975 | 7800U, 23103U, 13527U, 7138U, 25441U, 23060U, 22711U, 25838U, |
| 10976 | 20638U, 19404U, 25846U, 20649U, 19658U, 26770U, 20892U, 26733U, |
| 10977 | 20866U, 15252U, 18915U, 27464U, 20978U, 26760U, 20879U, 26714U, |
| 10978 | 20841U, 15190U, 18903U, 26671U, 20819U, 24131U, 1022U, 20489U, |
| 10979 | 7831U, 540U, 16998U, 2589U, 17481U, 24571U, 20269U, 11929U, |
| 10980 | 293U, 16733U, 2285U, 17268U, 3381U, 24207U, 20045U, 7245U, |
| 10981 | 26066U, 12074U, 26171U, 12364U, 26509U, 12519U, 26781U, 11966U, |
| 10982 | 26103U, 12777U, 27108U, 502U, 16948U, 2551U, 1029U, 17179U, |
| 10983 | 12036U, 26133U, 12461U, 26627U, 12388U, 26523U, 11990U, 26117U, |
| 10984 | 12801U, 27122U, 12050U, 26147U, 12324U, 26480U, 13150U, 665U, |
| 10985 | 17112U, 2714U, 17583U, 24736U, 20354U, 7664U, 27450U, 14946U, |
| 10986 | 26494U, 11837U, 25972U, 12273U, 26405U, 12475U, 26641U, 12706U, |
| 10987 | 27013U, 13082U, 27373U, 12282U, 26414U, 12484U, 26650U, 10594U, |
| 10988 | 12260U, 14912U, 26392U, 11829U, 25964U, 2486U, 6467U, 24450U, |
| 10989 | 7451U, 724U, 2767U, 6736U, 20808U, 24785U, 20412U, 7732U, |
| 10990 | 11936U, 26073U, 11891U, 26028U, 13180U, 27472U, 11873U, 26010U, |
| 10991 | 12317U, 26473U, 674U, 17124U, 2723U, 17595U, 6680U, 24743U, |
| 10992 | 20364U, 7676U, 11907U, 26044U, 12303U, 450U, 16911U, 2442U, |
| 10993 | 17393U, 3400U, 24414U, 20195U, 7395U, 26435U, 409U, 16858U, |
| 10994 | 2401U, 17368U, 24375U, 20150U, 7372U, 15838U, 12357U, 26502U, |
| 10995 | 12854U, 27145U, 12879U, 27170U, 12081U, 26178U, 12371U, 26516U, |
| 10996 | 11973U, 26110U, 12784U, 27115U, 12043U, 26140U, 12468U, 26634U, |
| 10997 | 12871U, 615U, 17074U, 2664U, 17557U, 24694U, 20322U, 27162U, |
| 10998 | 11900U, 274U, 16708U, 2266U, 17256U, 3371U, 24192U, 20024U, |
| 10999 | 7233U, 26037U, 12396U, 26531U, 11998U, 26125U, 12809U, 27130U, |
| 11000 | 12058U, 26155U, 12331U, 26487U, 12716U, 27023U, 13092U, 27383U, |
| 11001 | 14960U, 26539U, 12556U, 26818U, 12921U, 27212U, 15679U, 6948U, |
| 11002 | 25434U, 7820U, 12567U, 15085U, 26829U, 12932U, 15343U, 27223U, |
| 11003 | 12537U, 15066U, 26799U, 12902U, 15324U, 27193U, 16157U, 19270U, |
| 11004 | 11042U, 13142U, 15542U, 27442U, 10621U, 12310U, 14939U, 26442U, |
| 11005 | 10402U, 11958U, 14764U, 26095U, 10663U, 12505U, 15050U, 26678U, |
| 11006 | 23937U, 10848U, 12862U, 15301U, 27153U, 25859U, 10410U, 12066U, |
| 11007 | 14772U, 26163U, 20667U, 19974U, 7200U, 15830U, 15871U, 23525U, |
| 11008 | 17779U, 3332U, 5566U, 5804U, 6057U, 17798U, 19981U, 9917U, |
| 11009 | 2042U, 19872U, 19944U, 27691U, 21005U, 19086U, 11102U, 2105U, |
| 11010 | 5890U, 11081U, 2099U, 5871U, 23522U, 17771U, 3327U, 23050U, |
| 11011 | 17639U, 5555U, 7103U, 9911U, 2034U, 8061U, 8096U, 19866U, |
| 11012 | 19072U, 4883U, 3923U, 4816U, 4808U, 5022U, 4854U, 9925U, |
| 11013 | 2052U, 13216U, 18328U, 17818U, 27696U, 21013U, 7840U, 17987U, |
| 11014 | 5818U, 28807U, 3866U, 13733U, 18474U, 21130U, 11620U, 91U, |
| 11015 | 1966U, 5507U, 459U, 2508U, 1164U, 5425U, 8029U, 1931U, |
| 11016 | 10440U, 12144U, 14802U, 26282U, 15959U, 11242U, 23269U, 171U, |
| 11017 | 1980U, 10389U, 11945U, 14751U, 26082U, 28891U, 3885U, 21183U, |
| 11018 | 14134U, 2846U, 13408U, 18384U, 17847U, 27647U, 20998U, 18548U, |
| 11019 | 28829U, 3872U, 13738U, 18482U, 21153U, 17695U, 5650U, 16154U, |
| 11020 | 3273U, 8080U, 11623U, 8118U, 13452U, 18398U, 19264U, 6985U, |
| 11021 | 8142U, 9856U, 5786U, 8089U, 6939U, 183U, 1996U, 16646U, |
| 11022 | 27973U, 3720U, 21123U, 25935U, 17856U, 3497U, 161U, 16630U, |
| 11023 | 1186U, 5487U, 8045U, 1941U, 22897U, 19490U, 13700U, 18460U, |
| 11024 | 19432U, 16443U, 3289U, 13460U, 18405U, 19313U, 17732U, 5695U, |
| 11025 | 17161U, 11274U, 6037U, 19666U, 23869U, 3359U, 13571U, 18435U, |
| 11026 | 19930U, 19642U, 11268U, 20560U, 27701U, 195U, 16664U, 19990U, |
| 11027 | 21021U, 20675U, 7941U, 28863U, 4292U, 4356U, 4324U, 4373U, |
| 11028 | 4902U, 4643U, 4528U, 5002U, 4659U, 4409U, 4471U, 11559U, |
| 11029 | 12106U, 6399U, 24320U, 7359U, 15002U, 26581U, 25529U, 23030U, |
| 11030 | 19605U, 20517U, 11026U, 13126U, 15526U, 27426U, 303U, 16746U, |
| 11031 | 2295U, 22918U, 19520U, 18313U, 14975U, 26554U, 24215U, 20056U, |
| 11032 | 16053U, 19194U, 23449U, 19802U, 16079U, 19226U, 23475U, 19834U, |
| 11033 | 11858U, 6285U, 24185U, 7221U, 10730U, 12637U, 15155U, 26899U, |
| 11034 | 10922U, 13002U, 15413U, 27293U, 10366U, 11892U, 14728U, 26029U, |
| 11035 | 13181U, 6751U, 24803U, 10809U, 12745U, 15262U, 7760U, 27076U, |
| 11036 | 11001U, 13110U, 15501U, 27401U, 19U, 5363U, 107U, 2202U, |
| 11037 | 16606U, 5405U, 1175U, 5445U, 25U, 16560U, 5373U, 254U, |
| 11038 | 16682U, 2211U, 17218U, 5455U, 31U, 16569U, 15598U, 17685U, |
| 11039 | 2862U, 22958U, 19532U, 18965U, 22547U, 17750U, 3307U, 22993U, |
| 11040 | 19556U, 19354U, 23816U, 11845U, 6273U, 24178U, 7209U, 10712U, |
| 11041 | 12619U, 15137U, 26881U, 10904U, 12984U, 15395U, 27275U, 10349U, |
| 11042 | 11874U, 14711U, 26011U, 12318U, 6495U, 24468U, 10739U, 12646U, |
| 11043 | 15164U, 7479U, 26917U, 10931U, 13011U, 15422U, 27302U, 11805U, |
| 11044 | 10257U, 18228U, 25536U, 7869U, 6264U, 10679U, 12586U, 15104U, |
| 11045 | 26848U, 10871U, 12951U, 15362U, 27242U, 17657U, 5616U, 19414U, |
| 11046 | 7081U, 25870U, 371U, 16835U, 2363U, 15728U, 2998U, 19032U, |
| 11047 | 24335U, 20131U, 2240U, 15706U, 2891U, 24156U, 418U, 16870U, |
| 11048 | 2410U, 15754U, 3028U, 19042U, 24382U, 20160U, 635U, 17100U, |
| 11049 | 2684U, 15804U, 3202U, 19052U, 24710U, 20344U, 2253U, 15717U, |
| 11050 | 2904U, 24167U, 429U, 16884U, 2421U, 15763U, 3039U, 19062U, |
| 11051 | 24391U, 20172U, 10308U, 12098U, 6386U, 24312U, 7346U, 14992U, |
| 11052 | 26571U, 25510U, 23020U, 19592U, 20502U, 11018U, 13118U, 15518U, |
| 11053 | 27418U, 284U, 16721U, 2276U, 22909U, 19508U, 18244U, 14966U, |
| 11054 | 26545U, 24200U, 20035U, 59U, 5395U, 144U, 2231U, 17244U, |
| 11055 | 16622U, 5415U, 1181U, 5477U, 46U, 16589U, 5384U, 264U, |
| 11056 | 16695U, 2221U, 17231U, 5466U, 38U, 16579U, 15630U, 2884U, |
| 11057 | 22984U, 19544U, 18989U, 22742U, 19440U, 22564U, 3314U, 23002U, |
| 11058 | 19568U, 19371U, 75U, 207U, 1204U, 80U, 220U, 1218U, |
| 11059 | 23845U, 14693U, 25567U, 7879U, 6882U, 16346U, 16091U, 19241U, |
| 11060 | 23487U, 19849U, 15893U, 19113U, 23165U, 19702U, 14374U, 18721U, |
| 11061 | 26750U, 1902U, 14424U, 1559U, 26952U, 1917U, 3429U, 15012U, |
| 11062 | 26591U, 14612U, 18865U, 14552U, 1658U, 25152U, 23040U, 19618U, |
| 11063 | 23011U, 19580U, 20481U, 28845U, 21174U, 25587U, 7900U, 11050U, |
| 11064 | 13157U, 15550U, 27457U, 19306U, 7002U, 14292U, 1501U, 14984U, |
| 11065 | 26563U, 8149U, 14395U, 1545U, 4868U, 4995U, 4182U, 3905U, |
| 11066 | 15875U, 10374U, 11915U, 14736U, 26052U, 10381U, 11922U, 14743U, |
| 11067 | 26059U, 302U, 16745U, 2294U, 24214U, 20055U, 283U, 16720U, |
| 11068 | 2275U, 24199U, 20034U, 23553U, 3339U, 10523U, 19880U, 7147U, |
| 11069 | 25884U, 17809U, 5741U, 5063U, 5104U, 23550U, 17790U, 5731U, |
| 11070 | 3340U, 10524U, 6921U, 19881U, 7148U, 25885U, 27952U, 3707U, |
| 11071 | 21108U, 5203U, 14282U, 18646U, 13594U, 18451U, 6813U, 11034U, |
| 11072 | 13134U, 15534U, 27434U, 10394U, 11950U, 14756U, 26087U, 10841U, |
| 11073 | 12847U, 15294U, 27138U, 14250U, 18613U, 10002U, 18022U, 3391U, |
| 11074 | 3439U, 22805U, 15922U, 8502U, 17910U, 19148U, 23194U, 8552U, |
| 11075 | 17947U, 19737U, 16066U, 19210U, 23462U, 19818U, 15908U, 8487U, |
| 11076 | 17892U, 19131U, 23180U, 8537U, 17929U, 19720U, 14194U, 18581U, |
| 11077 | 26214U, 20735U, 14169U, 18565U, 26243U, 20750U, 14182U, 1443U, |
| 11078 | 26199U, 1804U, 26226U, 1824U, 13818U, 13384U, 18359U, 20989U, |
| 11079 | 18498U, 6824U, 8134U, 11682U, 1418U, 3410U, 3448U, 10243U, |
| 11080 | 18208U, 22871U, 19472U, 23863U, 3351U, 19921U, 7189U, 7165U, |
| 11081 | 492U, 16935U, 2541U, 17430U, 24500U, 20226U, 14525U, 18838U, |
| 11082 | 10225U, 18184U, 14266U, 18635U, 10018U, 18044U, 12855U, 6668U, |
| 11083 | 24687U, 7652U, 23822U, 25853U, 20658U, 19894U, 2463U, 6438U, |
| 11084 | 24431U, 7422U, 701U, 2744U, 6707U, 20724U, 24766U, 20387U, |
| 11085 | 7703U, 625U, 17087U, 2674U, 17570U, 24702U, 20333U, 4823U, |
| 11086 | 4199U, 8483U, 11366U, 10774U, 12690U, 15217U, 26997U, 10977U, |
| 11087 | 13066U, 15477U, 27357U, 10254U, 17631U, 5535U, 2057U, 13233U, |
| 11088 | 18335U, 18222U, 5826U, 11287U, 2120U, 8072U, 11468U, 8111U, |
| 11089 | 13286U, 18342U, 18274U, 6068U, 8105U, 11826U, 22700U, 17760U, |
| 11090 | 5717U, 19387U, 7070U, 8164U, 96U, 1973U, 5521U, 471U, |
| 11091 | 2520U, 1169U, 5435U, 8037U, 1936U, 25713U, 20585U, 15963U, |
| 11092 | 23273U, 177U, 1988U, 9889U, 2012U, 17973U, 14125U, 2840U, |
| 11093 | 18541U, 27814U, 3542U, 13207U, 6776U, 7991U, 24818U, 7785U, |
| 11094 | 27781U, 3533U, 13192U, 6762U, 7970U, 24809U, 7771U, 12254U, |
| 11095 | 6412U, 24400U, 7384U, 23152U, 27946U, 14689U, 17667U, 5628U, |
| 11096 | 2851U, 13412U, 18391U, 10419U, 14781U, 26186U, 22552U, 25831U, |
| 11097 | 20628U, 19362U, 14516U, 18826U, 10216U, 18172U, 14464U, 18787U, |
| 11098 | 27066U, 20965U, 14258U, 18624U, 10010U, 18033U, 14385U, 18735U, |
| 11099 | 26908U, 20906U, 14507U, 18814U, 10207U, 1404U, 14363U, 18707U, |
| 11100 | 10108U, 1355U, 26723U, 20853U, 14161U, 18554U, 9928U, 1231U, |
| 11101 | 14331U, 18694U, 10076U, 1308U, 26685U, 20829U, 14534U, 1630U, |
| 11102 | 10234U, 18196U, 14274U, 1488U, 10026U, 18055U, 18897U, 6874U, |
| 11103 | 13416U, 6801U, 10439U, 12143U, 14801U, 26281U, 10388U, 11944U, |
| 11104 | 14750U, 26081U, 16275U, 17714U, 5673U, 1039U, 3602U, 10469U, |
| 11105 | 12158U, 14816U, 26296U, 25767U, 20601U, 10601U, 12267U, 14919U, |
| 11106 | 19292U, 6993U, 26399U, 25137U, 3480U, 20461U, 27956U, 3713U, |
| 11107 | 21115U, 28919U, 3897U, 21196U, 28833U, 3878U, 21160U, 13501U, |
| 11108 | 27941U, 10546U, 12221U, 14879U, 26359U, 10826U, 12762U, 15279U, |
| 11109 | 27093U, 8569U, 10432U, 12136U, 14794U, 26274U, 10499U, 12188U, |
| 11110 | 14846U, 26326U, 10634U, 12434U, 15021U, 26600U, 25668U, 20567U, |
| 11111 | 10335U, 11852U, 14697U, 17966U, 25996U, 16306U, 17723U, 5684U, |
| 11112 | 10476U, 12165U, 14823U, 26303U, 10515U, 12204U, 14862U, 26342U, |
| 11113 | 10648U, 12454U, 15035U, 26620U, 25773U, 20609U, 10607U, 12289U, |
| 11114 | 14925U, 19299U, 26421U, 22777U, 19450U, 7092U, 10857U, 12888U, |
| 11115 | 15310U, 27179U, 10260U, 14226U, 1460U, 14341U, 1513U, 26694U, |
| 11116 | 1872U, 26258U, 1846U, 14299U, 18659U, 14404U, 18748U, 26934U, |
| 11117 | 20918U, 10966U, 13055U, 15466U, 27346U, 10790U, 12726U, 15233U, |
| 11118 | 27047U, 10756U, 12672U, 15199U, 26979U, 10948U, 13037U, 15448U, |
| 11119 | 27328U, 17827U, 5752U, 9978U, 1262U, 10086U, 1323U, 7849U, |
| 11120 | 14491U, 1604U, 10191U, 18150U, 14444U, 1574U, 10129U, 18095U, |
| 11121 | 10563U, 12238U, 14896U, 26376U, 11019U, 13119U, 15519U, 27419U, |
| 11122 | 18231U, 5834U, 28812U, 21137U, 189U, 2004U, 16655U, 25945U, |
| 11123 | 17864U, 5776U, 3514U, 166U, 16638U, 1191U, 5497U, 8053U, |
| 11124 | 1946U, 22903U, 19499U, 13704U, 18467U, 16447U, 3295U, 13465U, |
| 11125 | 18413U, 19320U, 17741U, 5706U, 17170U, 19673U, 23873U, 3365U, |
| 11126 | 13576U, 18443U, 19937U, 19650U, 7119U, 201U, 16673U, 20681U, |
| 11127 | 7949U, 11220U, 15568U, 18928U, 6891U, 18252U, 5991U, 16165U, |
| 11128 | 19281U, 4847U, 4210U, 4308U, 5014U, 5030U, 4340U, 4278U, |
| 11129 | 5169U, 5083U, 4924U, 4552U, 4936U, 4579U, 5114U, 4192U, |
| 11130 | 5148U, 4285U, 5180U, 5239U, 4425U, 4484U, 23156U, 15641U, |
| 11131 | 18997U, 19687U, 13398U, 15577U, 25572U, 20534U, 18943U, 25551U, |
| 11132 | 20526U, 18368U, 25823U, 13845U, 18506U, 20617U, 22736U, 19423U, |
| 11133 | 23409U, 19793U, 15691U, 19022U, 23856U, 19911U, 25816U, 13837U, |
| 11134 | 6834U, 7929U, 22706U, 19396U, 23160U, 19694U, 15685U, 19013U, |
| 11135 | 23850U, 19902U, 25141U, 15660U, 20543U, 19005U, 25620U, 20552U, |
| 11136 | 20468U, 13505U, 15582U, 18951U, 18428U, 2451U, 6423U, 24421U, |
| 11137 | 7407U, 689U, 2732U, 6692U, 20713U, 24756U, 20374U, 7688U, |
| 11138 | 25578U, 25743U, 20593U, 25585U, 70U, 25598U, 10418U, 12114U, |
| 11139 | 14780U, 26185U, 25056U, 20453U, 7810U, 22877U, 19481U, 7177U, |
| 11140 | 14101U, 18533U, 6864U, 23707U, 17789U, 5730U, 3345U, 10530U, |
| 11141 | 6920U, 19887U, 7156U, 25890U, 27951U, 3706U, 21107U, 5214U, |
| 11142 | 11617U, |
| 11143 | }; |
| 11144 | |
| 11145 | extern const int16_t MipsRegClassByHwModeTables[2][4] = { |
| 11146 | { // DefaultMode |
| 11147 | Mips::GPR32RegClassID, // mips_ptr_rc |
| 11148 | Mips::GP32RegClassID, // ptr_gp_rc |
| 11149 | Mips::GPRMM16RegClassID, // ptr_gpr16mm_rc |
| 11150 | Mips::SP32RegClassID, // ptr_sp_rc |
| 11151 | }, |
| 11152 | { // MIPS64 |
| 11153 | Mips::GPR64RegClassID, // mips_ptr_rc |
| 11154 | Mips::GP64RegClassID, // ptr_gp_rc |
| 11155 | Mips::GPRMM16RegClassID, // ptr_gpr16mm_rc |
| 11156 | Mips::SP64RegClassID, // ptr_sp_rc |
| 11157 | }, |
| 11158 | }; |
| 11159 | |
| 11160 | static inline void InitMipsMCInstrInfo(MCInstrInfo *II) { |
| 11161 | II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2921, &MipsRegClassByHwModeTables[0][0], 4); |
| 11162 | } |
| 11163 | |
| 11164 | |
| 11165 | } // namespace llvm |
| 11166 | |
| 11167 | #endif // GET_INSTRINFO_MC_DESC |
| 11168 | |
| 11169 | #ifdef GET_INSTRINFO_HEADER |
| 11170 | #undef GET_INSTRINFO_HEADER |
| 11171 | |
| 11172 | namespace llvm { |
| 11173 | |
| 11174 | struct MipsGenInstrInfo : public TargetInstrInfo { |
| 11175 | explicit MipsGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| 11176 | ~MipsGenInstrInfo() override = default; |
| 11177 | }; |
| 11178 | extern const int16_t MipsRegClassByHwModeTables[2][4]; |
| 11179 | |
| 11180 | } // namespace llvm |
| 11181 | |
| 11182 | namespace llvm::Mips { |
| 11183 | |
| 11184 | constexpr unsigned SUBOP_mem_mm_gp_simm7_lsl2_base = 0; |
| 11185 | constexpr unsigned SUBOP_mem_mm_gp_simm7_lsl2_offset = 1; |
| 11186 | constexpr unsigned SUBOP_mem_mm_sp_imm5_lsl2_base = 0; |
| 11187 | constexpr unsigned SUBOP_mem_mm_sp_imm5_lsl2_offset = 1; |
| 11188 | |
| 11189 | } // namespace llvm::Mips |
| 11190 | |
| 11191 | #endif // GET_INSTRINFO_HEADER |
| 11192 | |
| 11193 | #ifdef GET_INSTRINFO_HELPER_DECLS |
| 11194 | #undef GET_INSTRINFO_HELPER_DECLS |
| 11195 | |
| 11196 | |
| 11197 | #endif // GET_INSTRINFO_HELPER_DECLS |
| 11198 | |
| 11199 | #ifdef GET_INSTRINFO_HELPERS |
| 11200 | #undef GET_INSTRINFO_HELPERS |
| 11201 | |
| 11202 | |
| 11203 | #endif // GET_INSTRINFO_HELPERS |
| 11204 | |
| 11205 | #ifdef GET_INSTRINFO_CTOR_DTOR |
| 11206 | #undef GET_INSTRINFO_CTOR_DTOR |
| 11207 | |
| 11208 | namespace llvm { |
| 11209 | |
| 11210 | extern const MipsInstrTable MipsDescs; |
| 11211 | extern const unsigned MipsInstrNameIndices[]; |
| 11212 | extern const char MipsInstrNameData[]; |
| 11213 | MipsGenInstrInfo::MipsGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| 11214 | : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, MipsRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) { |
| 11215 | InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2921, &MipsRegClassByHwModeTables[0][0], 4); |
| 11216 | } |
| 11217 | |
| 11218 | } // namespace llvm |
| 11219 | |
| 11220 | #endif // GET_INSTRINFO_CTOR_DTOR |
| 11221 | |
| 11222 | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| 11223 | #undef GET_INSTRINFO_MC_HELPER_DECLS |
| 11224 | |
| 11225 | namespace llvm { |
| 11226 | |
| 11227 | class MCInst; |
| 11228 | class FeatureBitset; |
| 11229 | |
| 11230 | namespace Mips_MC { |
| 11231 | |
| 11232 | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| 11233 | |
| 11234 | } // namespace Mips_MC |
| 11235 | |
| 11236 | } // namespace llvm |
| 11237 | |
| 11238 | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| 11239 | |
| 11240 | #ifdef GET_INSTRINFO_MC_HELPERS |
| 11241 | #undef GET_INSTRINFO_MC_HELPERS |
| 11242 | |
| 11243 | namespace llvm::Mips_MC { |
| 11244 | |
| 11245 | |
| 11246 | } // namespace llvm::Mips_MC |
| 11247 | |
| 11248 | #endif // GET_INSTRINFO_MC_HELPERS |
| 11249 | |
| 11250 | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
| 11251 | defined(GET_AVAILABLE_OPCODE_CHECKER) |
| 11252 | #define GET_COMPUTE_FEATURES |
| 11253 | #endif |
| 11254 | #ifdef GET_COMPUTE_FEATURES |
| 11255 | #undef GET_COMPUTE_FEATURES |
| 11256 | |
| 11257 | namespace llvm::Mips_MC { |
| 11258 | |
| 11259 | // Bits for subtarget features that participate in instruction matching. |
| 11260 | enum SubtargetFeatureBits : uint8_t { |
| 11261 | Feature_IsPTR64bitBit = 38, |
| 11262 | Feature_IsPTR32bitBit = 37, |
| 11263 | Feature_UseCompactBranchesBit = 54, |
| 11264 | Feature_HasMips2Bit = 11, |
| 11265 | Feature_HasMips3_32Bit = 14, |
| 11266 | Feature_HasMips3_32r2Bit = 15, |
| 11267 | Feature_HasMips3Bit = 12, |
| 11268 | Feature_NotMips3Bit = 48, |
| 11269 | Feature_HasMips4_32Bit = 16, |
| 11270 | Feature_NotMips4_32Bit = 49, |
| 11271 | Feature_HasMips4_32r2Bit = 17, |
| 11272 | Feature_HasMips5_32r2Bit = 18, |
| 11273 | Feature_HasMips32Bit = 19, |
| 11274 | Feature_HasMips32r2Bit = 20, |
| 11275 | Feature_HasMips32r5Bit = 21, |
| 11276 | Feature_HasMips32r6Bit = 22, |
| 11277 | Feature_NotMips32r6Bit = 50, |
| 11278 | Feature_IsGP64bitBit = 34, |
| 11279 | Feature_IsGP32bitBit = 33, |
| 11280 | Feature_HasMips64Bit = 23, |
| 11281 | Feature_NotMips64Bit = 51, |
| 11282 | Feature_HasMips64r2Bit = 24, |
| 11283 | Feature_HasMips64r5Bit = 25, |
| 11284 | Feature_HasMips64r6Bit = 26, |
| 11285 | Feature_NotMips64r6Bit = 52, |
| 11286 | Feature_InMips16ModeBit = 31, |
| 11287 | Feature_NotInMips16ModeBit = 47, |
| 11288 | Feature_HasCnMipsBit = 1, |
| 11289 | Feature_NotCnMipsBit = 43, |
| 11290 | Feature_HasCnMipsPBit = 2, |
| 11291 | Feature_NotCnMipsPBit = 44, |
| 11292 | Feature_IsSym32Bit = 40, |
| 11293 | Feature_IsSym64Bit = 41, |
| 11294 | Feature_HasStdEncBit = 28, |
| 11295 | Feature_InMicroMipsBit = 30, |
| 11296 | Feature_NotInMicroMipsBit = 46, |
| 11297 | Feature_HasEVABit = 6, |
| 11298 | Feature_HasMSABit = 8, |
| 11299 | Feature_HasMadd4Bit = 10, |
| 11300 | Feature_HasMTBit = 9, |
| 11301 | Feature_UseIndirectJumpsHazardBit = 55, |
| 11302 | Feature_NoIndirectJumpGuardsBit = 42, |
| 11303 | Feature_HasR5900Bit = 27, |
| 11304 | Feature_NotR5900Bit = 53, |
| 11305 | Feature_HasCRCBit = 0, |
| 11306 | Feature_HasVirtBit = 29, |
| 11307 | Feature_HasGINVBit = 7, |
| 11308 | Feature_IsFP64bitBit = 32, |
| 11309 | Feature_NotFP64bitBit = 45, |
| 11310 | Feature_IsSingleFloatBit = 39, |
| 11311 | Feature_IsNotSingleFloatBit = 35, |
| 11312 | Feature_IsNotSoftFloatBit = 36, |
| 11313 | Feature_HasMips3DBit = 13, |
| 11314 | Feature_HasDSPBit = 3, |
| 11315 | Feature_HasDSPR2Bit = 4, |
| 11316 | Feature_HasDSPR3Bit = 5, |
| 11317 | }; |
| 11318 | |
| 11319 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| 11320 | FeatureBitset Features; |
| 11321 | if (FB[Mips::FeaturePTR64Bit]) |
| 11322 | Features.set(Feature_IsPTR64bitBit); |
| 11323 | if (!FB[Mips::FeaturePTR64Bit]) |
| 11324 | Features.set(Feature_IsPTR32bitBit); |
| 11325 | if (FB[Mips::FeatureUseCompactBranches]) |
| 11326 | Features.set(Feature_UseCompactBranchesBit); |
| 11327 | if (FB[Mips::FeatureMips2]) |
| 11328 | Features.set(Feature_HasMips2Bit); |
| 11329 | if (FB[Mips::FeatureMips3_32]) |
| 11330 | Features.set(Feature_HasMips3_32Bit); |
| 11331 | if (FB[Mips::FeatureMips3_32r2]) |
| 11332 | Features.set(Feature_HasMips3_32r2Bit); |
| 11333 | if (FB[Mips::FeatureMips3]) |
| 11334 | Features.set(Feature_HasMips3Bit); |
| 11335 | if (!FB[Mips::FeatureMips3]) |
| 11336 | Features.set(Feature_NotMips3Bit); |
| 11337 | if (FB[Mips::FeatureMips4_32]) |
| 11338 | Features.set(Feature_HasMips4_32Bit); |
| 11339 | if (!FB[Mips::FeatureMips4_32]) |
| 11340 | Features.set(Feature_NotMips4_32Bit); |
| 11341 | if (FB[Mips::FeatureMips4_32r2]) |
| 11342 | Features.set(Feature_HasMips4_32r2Bit); |
| 11343 | if (FB[Mips::FeatureMips5_32r2]) |
| 11344 | Features.set(Feature_HasMips5_32r2Bit); |
| 11345 | if (FB[Mips::FeatureMips32]) |
| 11346 | Features.set(Feature_HasMips32Bit); |
| 11347 | if (FB[Mips::FeatureMips32r2]) |
| 11348 | Features.set(Feature_HasMips32r2Bit); |
| 11349 | if (FB[Mips::FeatureMips32r5]) |
| 11350 | Features.set(Feature_HasMips32r5Bit); |
| 11351 | if (FB[Mips::FeatureMips32r6]) |
| 11352 | Features.set(Feature_HasMips32r6Bit); |
| 11353 | if (!FB[Mips::FeatureMips32r6]) |
| 11354 | Features.set(Feature_NotMips32r6Bit); |
| 11355 | if (FB[Mips::FeatureGP64Bit]) |
| 11356 | Features.set(Feature_IsGP64bitBit); |
| 11357 | if (!FB[Mips::FeatureGP64Bit]) |
| 11358 | Features.set(Feature_IsGP32bitBit); |
| 11359 | if (FB[Mips::FeatureMips64]) |
| 11360 | Features.set(Feature_HasMips64Bit); |
| 11361 | if (!FB[Mips::FeatureMips64]) |
| 11362 | Features.set(Feature_NotMips64Bit); |
| 11363 | if (FB[Mips::FeatureMips64r2]) |
| 11364 | Features.set(Feature_HasMips64r2Bit); |
| 11365 | if (FB[Mips::FeatureMips64r5]) |
| 11366 | Features.set(Feature_HasMips64r5Bit); |
| 11367 | if (FB[Mips::FeatureMips64r6]) |
| 11368 | Features.set(Feature_HasMips64r6Bit); |
| 11369 | if (!FB[Mips::FeatureMips64r6]) |
| 11370 | Features.set(Feature_NotMips64r6Bit); |
| 11371 | if (FB[Mips::FeatureMips16]) |
| 11372 | Features.set(Feature_InMips16ModeBit); |
| 11373 | if (!FB[Mips::FeatureMips16]) |
| 11374 | Features.set(Feature_NotInMips16ModeBit); |
| 11375 | if (FB[Mips::FeatureCnMips]) |
| 11376 | Features.set(Feature_HasCnMipsBit); |
| 11377 | if (!FB[Mips::FeatureCnMips]) |
| 11378 | Features.set(Feature_NotCnMipsBit); |
| 11379 | if (FB[Mips::FeatureCnMipsP]) |
| 11380 | Features.set(Feature_HasCnMipsPBit); |
| 11381 | if (!FB[Mips::FeatureCnMipsP]) |
| 11382 | Features.set(Feature_NotCnMipsPBit); |
| 11383 | if (FB[Mips::FeatureSym32]) |
| 11384 | Features.set(Feature_IsSym32Bit); |
| 11385 | if (!FB[Mips::FeatureSym32]) |
| 11386 | Features.set(Feature_IsSym64Bit); |
| 11387 | if (!FB[Mips::FeatureMips16]) |
| 11388 | Features.set(Feature_HasStdEncBit); |
| 11389 | if (FB[Mips::FeatureMicroMips]) |
| 11390 | Features.set(Feature_InMicroMipsBit); |
| 11391 | if (!FB[Mips::FeatureMicroMips]) |
| 11392 | Features.set(Feature_NotInMicroMipsBit); |
| 11393 | if (FB[Mips::FeatureEVA]) |
| 11394 | Features.set(Feature_HasEVABit); |
| 11395 | if (FB[Mips::FeatureMSA]) |
| 11396 | Features.set(Feature_HasMSABit); |
| 11397 | if (!FB[Mips::FeatureNoMadd4]) |
| 11398 | Features.set(Feature_HasMadd4Bit); |
| 11399 | if (FB[Mips::FeatureMT]) |
| 11400 | Features.set(Feature_HasMTBit); |
| 11401 | if (FB[Mips::FeatureUseIndirectJumpsHazard]) |
| 11402 | Features.set(Feature_UseIndirectJumpsHazardBit); |
| 11403 | if (!FB[Mips::FeatureUseIndirectJumpsHazard]) |
| 11404 | Features.set(Feature_NoIndirectJumpGuardsBit); |
| 11405 | if (FB[Mips::FeatureR5900]) |
| 11406 | Features.set(Feature_HasR5900Bit); |
| 11407 | if (!FB[Mips::FeatureR5900]) |
| 11408 | Features.set(Feature_NotR5900Bit); |
| 11409 | if (FB[Mips::FeatureCRC]) |
| 11410 | Features.set(Feature_HasCRCBit); |
| 11411 | if (FB[Mips::FeatureVirt]) |
| 11412 | Features.set(Feature_HasVirtBit); |
| 11413 | if (FB[Mips::FeatureGINV]) |
| 11414 | Features.set(Feature_HasGINVBit); |
| 11415 | if (FB[Mips::FeatureFP64Bit]) |
| 11416 | Features.set(Feature_IsFP64bitBit); |
| 11417 | if (!FB[Mips::FeatureFP64Bit]) |
| 11418 | Features.set(Feature_NotFP64bitBit); |
| 11419 | if (FB[Mips::FeatureSingleFloat]) |
| 11420 | Features.set(Feature_IsSingleFloatBit); |
| 11421 | if (!FB[Mips::FeatureSingleFloat]) |
| 11422 | Features.set(Feature_IsNotSingleFloatBit); |
| 11423 | if (!FB[Mips::FeatureSoftFloat]) |
| 11424 | Features.set(Feature_IsNotSoftFloatBit); |
| 11425 | if (FB[Mips::FeatureMips3D]) |
| 11426 | Features.set(Feature_HasMips3DBit); |
| 11427 | if (FB[Mips::FeatureDSP]) |
| 11428 | Features.set(Feature_HasDSPBit); |
| 11429 | if (FB[Mips::FeatureDSPR2]) |
| 11430 | Features.set(Feature_HasDSPR2Bit); |
| 11431 | if (FB[Mips::FeatureDSPR3]) |
| 11432 | Features.set(Feature_HasDSPR3Bit); |
| 11433 | return Features; |
| 11434 | } |
| 11435 | |
| 11436 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
| 11437 | enum : uint8_t { |
| 11438 | CEFBS_None, |
| 11439 | CEFBS_HasCnMips, |
| 11440 | CEFBS_HasCnMipsP, |
| 11441 | CEFBS_HasDSP, |
| 11442 | CEFBS_HasDSPR2, |
| 11443 | CEFBS_HasMSA, |
| 11444 | CEFBS_HasMT, |
| 11445 | CEFBS_InMicroMips, |
| 11446 | CEFBS_InMips16Mode, |
| 11447 | CEFBS_IsGP32bit, |
| 11448 | CEFBS_IsGP64bit, |
| 11449 | CEFBS_IsNotSoftFloat, |
| 11450 | CEFBS_NotCnMips, |
| 11451 | CEFBS_NotInMips16Mode, |
| 11452 | CEFBS_NotR5900, |
| 11453 | CEFBS_HasDSP_NotInMicroMips, |
| 11454 | CEFBS_HasStdEnc_HasMSA, |
| 11455 | CEFBS_HasStdEnc_HasMips32, |
| 11456 | CEFBS_HasStdEnc_HasMips32r6, |
| 11457 | CEFBS_HasStdEnc_HasMips64, |
| 11458 | CEFBS_HasStdEnc_HasMips64r6, |
| 11459 | CEFBS_HasStdEnc_IsNotSoftFloat, |
| 11460 | CEFBS_HasStdEnc_NotInMicroMips, |
| 11461 | CEFBS_HasStdEnc_NotMips3, |
| 11462 | CEFBS_HasStdEnc_NotMips4_32, |
| 11463 | CEFBS_InMicroMips_HasDSP, |
| 11464 | CEFBS_InMicroMips_HasDSPR2, |
| 11465 | CEFBS_InMicroMips_HasDSPR3, |
| 11466 | CEFBS_InMicroMips_HasEVA, |
| 11467 | CEFBS_InMicroMips_HasMips32r6, |
| 11468 | CEFBS_InMicroMips_IsNotSoftFloat, |
| 11469 | CEFBS_InMicroMips_NotMips32r6, |
| 11470 | CEFBS_IsFP64bit_IsNotSoftFloat, |
| 11471 | CEFBS_IsGP32bit_NotInMicroMips, |
| 11472 | CEFBS_NotFP64bit_IsNotSoftFloat, |
| 11473 | CEFBS_NotInMips16Mode_HasDSP, |
| 11474 | CEFBS_NotInMips16Mode_IsGP64bit, |
| 11475 | CEFBS_NotInMips16Mode_IsNotSoftFloat, |
| 11476 | CEFBS_NotInMips16Mode_IsPTR64bit, |
| 11477 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, |
| 11478 | CEFBS_HasStdEnc_HasMSA_HasMips64, |
| 11479 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, |
| 11480 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, |
| 11481 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, |
| 11482 | CEFBS_HasStdEnc_HasMips32_NotInMicroMips, |
| 11483 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, |
| 11484 | CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, |
| 11485 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, |
| 11486 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, |
| 11487 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, |
| 11488 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, |
| 11489 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, |
| 11490 | CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, |
| 11491 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, |
| 11492 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, |
| 11493 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, |
| 11494 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, |
| 11495 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 11496 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, |
| 11497 | CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, |
| 11498 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, |
| 11499 | CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, |
| 11500 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, |
| 11501 | CEFBS_InMicroMips_HasMips32r5_HasVirt, |
| 11502 | CEFBS_InMicroMips_HasMips32r6_HasGINV, |
| 11503 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, |
| 11504 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 11505 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, |
| 11506 | CEFBS_InMicroMips_NotMips32r6_HasDSP, |
| 11507 | CEFBS_InMicroMips_NotMips32r6_HasEVA, |
| 11508 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, |
| 11509 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, |
| 11510 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, |
| 11511 | CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, |
| 11512 | CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, |
| 11513 | CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, |
| 11514 | CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, |
| 11515 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, |
| 11516 | CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 11517 | CEFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900, |
| 11518 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 11519 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, |
| 11520 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, |
| 11521 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, |
| 11522 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, |
| 11523 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, |
| 11524 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, |
| 11525 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, |
| 11526 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, |
| 11527 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, |
| 11528 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, |
| 11529 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
| 11530 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 11531 | CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, |
| 11532 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, |
| 11533 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 11534 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, |
| 11535 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, |
| 11536 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, |
| 11537 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 11538 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 11539 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, |
| 11540 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, |
| 11541 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, |
| 11542 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, |
| 11543 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 11544 | CEFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, |
| 11545 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, |
| 11546 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 11547 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 11548 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 11549 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 11550 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 11551 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| 11552 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 11553 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 11554 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 11555 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
| 11556 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, |
| 11557 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
| 11558 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 11559 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| 11560 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, |
| 11561 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 11562 | CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
| 11563 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 11564 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11565 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, |
| 11566 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11567 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, |
| 11568 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, |
| 11569 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11570 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| 11571 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11572 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 11573 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11574 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 11575 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, |
| 11576 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 11577 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 11578 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 11579 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 11580 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 11581 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, |
| 11582 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11583 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11584 | CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11585 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11586 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, |
| 11587 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, |
| 11588 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11589 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11590 | CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11591 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 11592 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 11593 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 11594 | CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| 11595 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| 11596 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 11597 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 11598 | }; |
| 11599 | |
| 11600 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 11601 | {}, // CEFBS_None |
| 11602 | {Feature_HasCnMipsBit, }, |
| 11603 | {Feature_HasCnMipsPBit, }, |
| 11604 | {Feature_HasDSPBit, }, |
| 11605 | {Feature_HasDSPR2Bit, }, |
| 11606 | {Feature_HasMSABit, }, |
| 11607 | {Feature_HasMTBit, }, |
| 11608 | {Feature_InMicroMipsBit, }, |
| 11609 | {Feature_InMips16ModeBit, }, |
| 11610 | {Feature_IsGP32bitBit, }, |
| 11611 | {Feature_IsGP64bitBit, }, |
| 11612 | {Feature_IsNotSoftFloatBit, }, |
| 11613 | {Feature_NotCnMipsBit, }, |
| 11614 | {Feature_NotInMips16ModeBit, }, |
| 11615 | {Feature_NotR5900Bit, }, |
| 11616 | {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, |
| 11617 | {Feature_HasStdEncBit, Feature_HasMSABit, }, |
| 11618 | {Feature_HasStdEncBit, Feature_HasMips32Bit, }, |
| 11619 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, |
| 11620 | {Feature_HasStdEncBit, Feature_HasMips64Bit, }, |
| 11621 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, |
| 11622 | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, |
| 11623 | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 11624 | {Feature_HasStdEncBit, Feature_NotMips3Bit, }, |
| 11625 | {Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, |
| 11626 | {Feature_InMicroMipsBit, Feature_HasDSPBit, }, |
| 11627 | {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, |
| 11628 | {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, |
| 11629 | {Feature_InMicroMipsBit, Feature_HasEVABit, }, |
| 11630 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, |
| 11631 | {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
| 11632 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, |
| 11633 | {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 11634 | {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, |
| 11635 | {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 11636 | {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, |
| 11637 | {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, }, |
| 11638 | {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, }, |
| 11639 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, |
| 11640 | {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 11641 | {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, |
| 11642 | {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, |
| 11643 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, |
| 11644 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, |
| 11645 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, |
| 11646 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, |
| 11647 | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, |
| 11648 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 11649 | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, |
| 11650 | {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, |
| 11651 | {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, |
| 11652 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11653 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, |
| 11654 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, |
| 11655 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, }, |
| 11656 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, |
| 11657 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, |
| 11658 | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11659 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 11660 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, |
| 11661 | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 11662 | {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, }, |
| 11663 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 11664 | {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, |
| 11665 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, |
| 11666 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 11667 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 11668 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 11669 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, |
| 11670 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, |
| 11671 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 11672 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 11673 | {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 11674 | {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
| 11675 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, }, |
| 11676 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, |
| 11677 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, }, |
| 11678 | {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 11679 | {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 11680 | {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotR5900Bit, }, |
| 11681 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11682 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 11683 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11684 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 11685 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 11686 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
| 11687 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 11688 | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, |
| 11689 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
| 11690 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, |
| 11691 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11692 | {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11693 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11694 | {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11695 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
| 11696 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11697 | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 11698 | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 11699 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11700 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11701 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11702 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 11703 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 11704 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 11705 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
| 11706 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11707 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotR5900Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 11708 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, }, |
| 11709 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11710 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 11711 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 11712 | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11713 | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11714 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| 11715 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 11716 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 11717 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11718 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11719 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11720 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11721 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11722 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| 11723 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11724 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11725 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11726 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11727 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11728 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
| 11729 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11730 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, |
| 11731 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
| 11732 | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11733 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| 11734 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11735 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 11736 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11737 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 11738 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 11739 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 11740 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 11741 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 11742 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 11743 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 11744 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, |
| 11745 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11746 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11747 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11748 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11749 | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, |
| 11750 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, |
| 11751 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11752 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11753 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11754 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 11755 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 11756 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 11757 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 11758 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| 11759 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 11760 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 11761 | }; |
| 11762 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
| 11763 | CEFBS_None, // PHI |
| 11764 | CEFBS_None, // INLINEASM |
| 11765 | CEFBS_None, // INLINEASM_BR |
| 11766 | CEFBS_None, // CFI_INSTRUCTION |
| 11767 | CEFBS_None, // EH_LABEL |
| 11768 | CEFBS_None, // GC_LABEL |
| 11769 | CEFBS_None, // ANNOTATION_LABEL |
| 11770 | CEFBS_None, // KILL |
| 11771 | CEFBS_None, // EXTRACT_SUBREG |
| 11772 | CEFBS_None, // INSERT_SUBREG |
| 11773 | CEFBS_None, // IMPLICIT_DEF |
| 11774 | CEFBS_None, // INIT_UNDEF |
| 11775 | CEFBS_None, // SUBREG_TO_REG |
| 11776 | CEFBS_None, // COPY_TO_REGCLASS |
| 11777 | CEFBS_None, // DBG_VALUE |
| 11778 | CEFBS_None, // DBG_VALUE_LIST |
| 11779 | CEFBS_None, // DBG_INSTR_REF |
| 11780 | CEFBS_None, // DBG_PHI |
| 11781 | CEFBS_None, // DBG_LABEL |
| 11782 | CEFBS_None, // REG_SEQUENCE |
| 11783 | CEFBS_None, // COPY |
| 11784 | CEFBS_None, // COPY_LANEMASK |
| 11785 | CEFBS_None, // BUNDLE |
| 11786 | CEFBS_None, // LIFETIME_START |
| 11787 | CEFBS_None, // LIFETIME_END |
| 11788 | CEFBS_None, // PSEUDO_PROBE |
| 11789 | CEFBS_None, // ARITH_FENCE |
| 11790 | CEFBS_None, // STACKMAP |
| 11791 | CEFBS_None, // FENTRY_CALL |
| 11792 | CEFBS_None, // PATCHPOINT |
| 11793 | CEFBS_None, // LOAD_STACK_GUARD |
| 11794 | CEFBS_None, // PREALLOCATED_SETUP |
| 11795 | CEFBS_None, // PREALLOCATED_ARG |
| 11796 | CEFBS_None, // STATEPOINT |
| 11797 | CEFBS_None, // LOCAL_ESCAPE |
| 11798 | CEFBS_None, // FAULTING_OP |
| 11799 | CEFBS_None, // PATCHABLE_OP |
| 11800 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER |
| 11801 | CEFBS_None, // PATCHABLE_RET |
| 11802 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT |
| 11803 | CEFBS_None, // PATCHABLE_TAIL_CALL |
| 11804 | CEFBS_None, // PATCHABLE_EVENT_CALL |
| 11805 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL |
| 11806 | CEFBS_None, // ICALL_BRANCH_FUNNEL |
| 11807 | CEFBS_None, // FAKE_USE |
| 11808 | CEFBS_None, // MEMBARRIER |
| 11809 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO |
| 11810 | CEFBS_None, // RELOC_NONE |
| 11811 | CEFBS_None, // CONVERGENCECTRL_ENTRY |
| 11812 | CEFBS_None, // CONVERGENCECTRL_ANCHOR |
| 11813 | CEFBS_None, // CONVERGENCECTRL_LOOP |
| 11814 | CEFBS_None, // CONVERGENCECTRL_GLUE |
| 11815 | CEFBS_None, // G_ASSERT_SEXT |
| 11816 | CEFBS_None, // G_ASSERT_ZEXT |
| 11817 | CEFBS_None, // G_ASSERT_ALIGN |
| 11818 | CEFBS_None, // G_ADD |
| 11819 | CEFBS_None, // G_SUB |
| 11820 | CEFBS_None, // G_MUL |
| 11821 | CEFBS_None, // G_SDIV |
| 11822 | CEFBS_None, // G_UDIV |
| 11823 | CEFBS_None, // G_SREM |
| 11824 | CEFBS_None, // G_UREM |
| 11825 | CEFBS_None, // G_SDIVREM |
| 11826 | CEFBS_None, // G_UDIVREM |
| 11827 | CEFBS_None, // G_AND |
| 11828 | CEFBS_None, // G_OR |
| 11829 | CEFBS_None, // G_XOR |
| 11830 | CEFBS_None, // G_ABDS |
| 11831 | CEFBS_None, // G_ABDU |
| 11832 | CEFBS_None, // G_UAVGFLOOR |
| 11833 | CEFBS_None, // G_UAVGCEIL |
| 11834 | CEFBS_None, // G_SAVGFLOOR |
| 11835 | CEFBS_None, // G_SAVGCEIL |
| 11836 | CEFBS_None, // G_IMPLICIT_DEF |
| 11837 | CEFBS_None, // G_PHI |
| 11838 | CEFBS_None, // G_FRAME_INDEX |
| 11839 | CEFBS_None, // G_GLOBAL_VALUE |
| 11840 | CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE |
| 11841 | CEFBS_None, // G_CONSTANT_POOL |
| 11842 | CEFBS_None, // G_EXTRACT |
| 11843 | CEFBS_None, // G_UNMERGE_VALUES |
| 11844 | CEFBS_None, // G_INSERT |
| 11845 | CEFBS_None, // G_MERGE_VALUES |
| 11846 | CEFBS_None, // G_BUILD_VECTOR |
| 11847 | CEFBS_None, // G_BUILD_VECTOR_TRUNC |
| 11848 | CEFBS_None, // G_CONCAT_VECTORS |
| 11849 | CEFBS_None, // G_PTRTOINT |
| 11850 | CEFBS_None, // G_INTTOPTR |
| 11851 | CEFBS_None, // G_BITCAST |
| 11852 | CEFBS_None, // G_FREEZE |
| 11853 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER |
| 11854 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND |
| 11855 | CEFBS_None, // G_INTRINSIC_TRUNC |
| 11856 | CEFBS_None, // G_INTRINSIC_ROUND |
| 11857 | CEFBS_None, // G_INTRINSIC_LRINT |
| 11858 | CEFBS_None, // G_INTRINSIC_LLRINT |
| 11859 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN |
| 11860 | CEFBS_None, // G_READCYCLECOUNTER |
| 11861 | CEFBS_None, // G_READSTEADYCOUNTER |
| 11862 | CEFBS_None, // G_LOAD |
| 11863 | CEFBS_None, // G_SEXTLOAD |
| 11864 | CEFBS_None, // G_ZEXTLOAD |
| 11865 | CEFBS_None, // G_INDEXED_LOAD |
| 11866 | CEFBS_None, // G_INDEXED_SEXTLOAD |
| 11867 | CEFBS_None, // G_INDEXED_ZEXTLOAD |
| 11868 | CEFBS_None, // G_STORE |
| 11869 | CEFBS_None, // G_INDEXED_STORE |
| 11870 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 11871 | CEFBS_None, // G_ATOMIC_CMPXCHG |
| 11872 | CEFBS_None, // G_ATOMICRMW_XCHG |
| 11873 | CEFBS_None, // G_ATOMICRMW_ADD |
| 11874 | CEFBS_None, // G_ATOMICRMW_SUB |
| 11875 | CEFBS_None, // G_ATOMICRMW_AND |
| 11876 | CEFBS_None, // G_ATOMICRMW_NAND |
| 11877 | CEFBS_None, // G_ATOMICRMW_OR |
| 11878 | CEFBS_None, // G_ATOMICRMW_XOR |
| 11879 | CEFBS_None, // G_ATOMICRMW_MAX |
| 11880 | CEFBS_None, // G_ATOMICRMW_MIN |
| 11881 | CEFBS_None, // G_ATOMICRMW_UMAX |
| 11882 | CEFBS_None, // G_ATOMICRMW_UMIN |
| 11883 | CEFBS_None, // G_ATOMICRMW_FADD |
| 11884 | CEFBS_None, // G_ATOMICRMW_FSUB |
| 11885 | CEFBS_None, // G_ATOMICRMW_FMAX |
| 11886 | CEFBS_None, // G_ATOMICRMW_FMIN |
| 11887 | CEFBS_None, // G_ATOMICRMW_FMAXIMUM |
| 11888 | CEFBS_None, // G_ATOMICRMW_FMINIMUM |
| 11889 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP |
| 11890 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP |
| 11891 | CEFBS_None, // G_ATOMICRMW_USUB_COND |
| 11892 | CEFBS_None, // G_ATOMICRMW_USUB_SAT |
| 11893 | CEFBS_None, // G_FENCE |
| 11894 | CEFBS_None, // G_PREFETCH |
| 11895 | CEFBS_None, // G_BRCOND |
| 11896 | CEFBS_None, // G_BRINDIRECT |
| 11897 | CEFBS_None, // G_INVOKE_REGION_START |
| 11898 | CEFBS_None, // G_INTRINSIC |
| 11899 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS |
| 11900 | CEFBS_None, // G_INTRINSIC_CONVERGENT |
| 11901 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 11902 | CEFBS_None, // G_ANYEXT |
| 11903 | CEFBS_None, // G_TRUNC |
| 11904 | CEFBS_None, // G_TRUNC_SSAT_S |
| 11905 | CEFBS_None, // G_TRUNC_SSAT_U |
| 11906 | CEFBS_None, // G_TRUNC_USAT_U |
| 11907 | CEFBS_None, // G_CONSTANT |
| 11908 | CEFBS_None, // G_FCONSTANT |
| 11909 | CEFBS_None, // G_VASTART |
| 11910 | CEFBS_None, // G_VAARG |
| 11911 | CEFBS_None, // G_SEXT |
| 11912 | CEFBS_None, // G_SEXT_INREG |
| 11913 | CEFBS_None, // G_ZEXT |
| 11914 | CEFBS_None, // G_SHL |
| 11915 | CEFBS_None, // G_LSHR |
| 11916 | CEFBS_None, // G_ASHR |
| 11917 | CEFBS_None, // G_FSHL |
| 11918 | CEFBS_None, // G_FSHR |
| 11919 | CEFBS_None, // G_ROTR |
| 11920 | CEFBS_None, // G_ROTL |
| 11921 | CEFBS_None, // G_ICMP |
| 11922 | CEFBS_None, // G_FCMP |
| 11923 | CEFBS_None, // G_SCMP |
| 11924 | CEFBS_None, // G_UCMP |
| 11925 | CEFBS_None, // G_SELECT |
| 11926 | CEFBS_None, // G_UADDO |
| 11927 | CEFBS_None, // G_UADDE |
| 11928 | CEFBS_None, // G_USUBO |
| 11929 | CEFBS_None, // G_USUBE |
| 11930 | CEFBS_None, // G_SADDO |
| 11931 | CEFBS_None, // G_SADDE |
| 11932 | CEFBS_None, // G_SSUBO |
| 11933 | CEFBS_None, // G_SSUBE |
| 11934 | CEFBS_None, // G_UMULO |
| 11935 | CEFBS_None, // G_SMULO |
| 11936 | CEFBS_None, // G_UMULH |
| 11937 | CEFBS_None, // G_SMULH |
| 11938 | CEFBS_None, // G_UADDSAT |
| 11939 | CEFBS_None, // G_SADDSAT |
| 11940 | CEFBS_None, // G_USUBSAT |
| 11941 | CEFBS_None, // G_SSUBSAT |
| 11942 | CEFBS_None, // G_USHLSAT |
| 11943 | CEFBS_None, // G_SSHLSAT |
| 11944 | CEFBS_None, // G_SMULFIX |
| 11945 | CEFBS_None, // G_UMULFIX |
| 11946 | CEFBS_None, // G_SMULFIXSAT |
| 11947 | CEFBS_None, // G_UMULFIXSAT |
| 11948 | CEFBS_None, // G_SDIVFIX |
| 11949 | CEFBS_None, // G_UDIVFIX |
| 11950 | CEFBS_None, // G_SDIVFIXSAT |
| 11951 | CEFBS_None, // G_UDIVFIXSAT |
| 11952 | CEFBS_None, // G_FADD |
| 11953 | CEFBS_None, // G_FSUB |
| 11954 | CEFBS_None, // G_FMUL |
| 11955 | CEFBS_None, // G_FMA |
| 11956 | CEFBS_None, // G_FMAD |
| 11957 | CEFBS_None, // G_FDIV |
| 11958 | CEFBS_None, // G_FREM |
| 11959 | CEFBS_None, // G_FMODF |
| 11960 | CEFBS_None, // G_FPOW |
| 11961 | CEFBS_None, // G_FPOWI |
| 11962 | CEFBS_None, // G_FEXP |
| 11963 | CEFBS_None, // G_FEXP2 |
| 11964 | CEFBS_None, // G_FEXP10 |
| 11965 | CEFBS_None, // G_FLOG |
| 11966 | CEFBS_None, // G_FLOG2 |
| 11967 | CEFBS_None, // G_FLOG10 |
| 11968 | CEFBS_None, // G_FLDEXP |
| 11969 | CEFBS_None, // G_FFREXP |
| 11970 | CEFBS_None, // G_FNEG |
| 11971 | CEFBS_None, // G_FPEXT |
| 11972 | CEFBS_None, // G_FPTRUNC |
| 11973 | CEFBS_None, // G_FPTOSI |
| 11974 | CEFBS_None, // G_FPTOUI |
| 11975 | CEFBS_None, // G_SITOFP |
| 11976 | CEFBS_None, // G_UITOFP |
| 11977 | CEFBS_None, // G_FPTOSI_SAT |
| 11978 | CEFBS_None, // G_FPTOUI_SAT |
| 11979 | CEFBS_None, // G_FABS |
| 11980 | CEFBS_None, // G_FCOPYSIGN |
| 11981 | CEFBS_None, // G_IS_FPCLASS |
| 11982 | CEFBS_None, // G_FCANONICALIZE |
| 11983 | CEFBS_None, // G_FMINNUM |
| 11984 | CEFBS_None, // G_FMAXNUM |
| 11985 | CEFBS_None, // G_FMINNUM_IEEE |
| 11986 | CEFBS_None, // G_FMAXNUM_IEEE |
| 11987 | CEFBS_None, // G_FMINIMUM |
| 11988 | CEFBS_None, // G_FMAXIMUM |
| 11989 | CEFBS_None, // G_FMINIMUMNUM |
| 11990 | CEFBS_None, // G_FMAXIMUMNUM |
| 11991 | CEFBS_None, // G_GET_FPENV |
| 11992 | CEFBS_None, // G_SET_FPENV |
| 11993 | CEFBS_None, // G_RESET_FPENV |
| 11994 | CEFBS_None, // G_GET_FPMODE |
| 11995 | CEFBS_None, // G_SET_FPMODE |
| 11996 | CEFBS_None, // G_RESET_FPMODE |
| 11997 | CEFBS_None, // G_GET_ROUNDING |
| 11998 | CEFBS_None, // G_SET_ROUNDING |
| 11999 | CEFBS_None, // G_PTR_ADD |
| 12000 | CEFBS_None, // G_PTRMASK |
| 12001 | CEFBS_None, // G_SMIN |
| 12002 | CEFBS_None, // G_SMAX |
| 12003 | CEFBS_None, // G_UMIN |
| 12004 | CEFBS_None, // G_UMAX |
| 12005 | CEFBS_None, // G_ABS |
| 12006 | CEFBS_None, // G_LROUND |
| 12007 | CEFBS_None, // G_LLROUND |
| 12008 | CEFBS_None, // G_BR |
| 12009 | CEFBS_None, // G_BRJT |
| 12010 | CEFBS_None, // G_VSCALE |
| 12011 | CEFBS_None, // G_INSERT_SUBVECTOR |
| 12012 | CEFBS_None, // G_EXTRACT_SUBVECTOR |
| 12013 | CEFBS_None, // G_INSERT_VECTOR_ELT |
| 12014 | CEFBS_None, // G_EXTRACT_VECTOR_ELT |
| 12015 | CEFBS_None, // G_SHUFFLE_VECTOR |
| 12016 | CEFBS_None, // G_SPLAT_VECTOR |
| 12017 | CEFBS_None, // G_STEP_VECTOR |
| 12018 | CEFBS_None, // G_VECTOR_COMPRESS |
| 12019 | CEFBS_None, // G_CTTZ |
| 12020 | CEFBS_None, // G_CTTZ_ZERO_UNDEF |
| 12021 | CEFBS_None, // G_CTLZ |
| 12022 | CEFBS_None, // G_CTLZ_ZERO_UNDEF |
| 12023 | CEFBS_None, // G_CTLS |
| 12024 | CEFBS_None, // G_CTPOP |
| 12025 | CEFBS_None, // G_BSWAP |
| 12026 | CEFBS_None, // G_BITREVERSE |
| 12027 | CEFBS_None, // G_FCEIL |
| 12028 | CEFBS_None, // G_FCOS |
| 12029 | CEFBS_None, // G_FSIN |
| 12030 | CEFBS_None, // G_FSINCOS |
| 12031 | CEFBS_None, // G_FTAN |
| 12032 | CEFBS_None, // G_FACOS |
| 12033 | CEFBS_None, // G_FASIN |
| 12034 | CEFBS_None, // G_FATAN |
| 12035 | CEFBS_None, // G_FATAN2 |
| 12036 | CEFBS_None, // G_FCOSH |
| 12037 | CEFBS_None, // G_FSINH |
| 12038 | CEFBS_None, // G_FTANH |
| 12039 | CEFBS_None, // G_FSQRT |
| 12040 | CEFBS_None, // G_FFLOOR |
| 12041 | CEFBS_None, // G_FRINT |
| 12042 | CEFBS_None, // G_FNEARBYINT |
| 12043 | CEFBS_None, // G_ADDRSPACE_CAST |
| 12044 | CEFBS_None, // G_BLOCK_ADDR |
| 12045 | CEFBS_None, // G_JUMP_TABLE |
| 12046 | CEFBS_None, // G_DYN_STACKALLOC |
| 12047 | CEFBS_None, // G_STACKSAVE |
| 12048 | CEFBS_None, // G_STACKRESTORE |
| 12049 | CEFBS_None, // G_STRICT_FADD |
| 12050 | CEFBS_None, // G_STRICT_FSUB |
| 12051 | CEFBS_None, // G_STRICT_FMUL |
| 12052 | CEFBS_None, // G_STRICT_FDIV |
| 12053 | CEFBS_None, // G_STRICT_FREM |
| 12054 | CEFBS_None, // G_STRICT_FMA |
| 12055 | CEFBS_None, // G_STRICT_FSQRT |
| 12056 | CEFBS_None, // G_STRICT_FLDEXP |
| 12057 | CEFBS_None, // G_READ_REGISTER |
| 12058 | CEFBS_None, // G_WRITE_REGISTER |
| 12059 | CEFBS_None, // G_MEMCPY |
| 12060 | CEFBS_None, // G_MEMCPY_INLINE |
| 12061 | CEFBS_None, // G_MEMMOVE |
| 12062 | CEFBS_None, // G_MEMSET |
| 12063 | CEFBS_None, // G_BZERO |
| 12064 | CEFBS_None, // G_TRAP |
| 12065 | CEFBS_None, // G_DEBUGTRAP |
| 12066 | CEFBS_None, // G_UBSANTRAP |
| 12067 | CEFBS_None, // G_VECREDUCE_SEQ_FADD |
| 12068 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL |
| 12069 | CEFBS_None, // G_VECREDUCE_FADD |
| 12070 | CEFBS_None, // G_VECREDUCE_FMUL |
| 12071 | CEFBS_None, // G_VECREDUCE_FMAX |
| 12072 | CEFBS_None, // G_VECREDUCE_FMIN |
| 12073 | CEFBS_None, // G_VECREDUCE_FMAXIMUM |
| 12074 | CEFBS_None, // G_VECREDUCE_FMINIMUM |
| 12075 | CEFBS_None, // G_VECREDUCE_ADD |
| 12076 | CEFBS_None, // G_VECREDUCE_MUL |
| 12077 | CEFBS_None, // G_VECREDUCE_AND |
| 12078 | CEFBS_None, // G_VECREDUCE_OR |
| 12079 | CEFBS_None, // G_VECREDUCE_XOR |
| 12080 | CEFBS_None, // G_VECREDUCE_SMAX |
| 12081 | CEFBS_None, // G_VECREDUCE_SMIN |
| 12082 | CEFBS_None, // G_VECREDUCE_UMAX |
| 12083 | CEFBS_None, // G_VECREDUCE_UMIN |
| 12084 | CEFBS_None, // G_SBFX |
| 12085 | CEFBS_None, // G_UBFX |
| 12086 | CEFBS_None, // ABSMacro |
| 12087 | CEFBS_None, // ADJCALLSTACKDOWN |
| 12088 | CEFBS_None, // ADJCALLSTACKUP |
| 12089 | CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO |
| 12090 | CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO |
| 12091 | CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO |
| 12092 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 |
| 12093 | CEFBS_NotR5900, // ATOMIC_CMP_SWAP_I16_POSTRA |
| 12094 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 |
| 12095 | CEFBS_NotR5900, // ATOMIC_CMP_SWAP_I32_POSTRA |
| 12096 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 |
| 12097 | CEFBS_NotR5900, // ATOMIC_CMP_SWAP_I64_POSTRA |
| 12098 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 |
| 12099 | CEFBS_NotR5900, // ATOMIC_CMP_SWAP_I8_POSTRA |
| 12100 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 |
| 12101 | CEFBS_NotR5900, // ATOMIC_LOAD_ADD_I16_POSTRA |
| 12102 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 |
| 12103 | CEFBS_NotR5900, // ATOMIC_LOAD_ADD_I32_POSTRA |
| 12104 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 |
| 12105 | CEFBS_NotR5900, // ATOMIC_LOAD_ADD_I64_POSTRA |
| 12106 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 |
| 12107 | CEFBS_NotR5900, // ATOMIC_LOAD_ADD_I8_POSTRA |
| 12108 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 |
| 12109 | CEFBS_NotR5900, // ATOMIC_LOAD_AND_I16_POSTRA |
| 12110 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 |
| 12111 | CEFBS_NotR5900, // ATOMIC_LOAD_AND_I32_POSTRA |
| 12112 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 |
| 12113 | CEFBS_NotR5900, // ATOMIC_LOAD_AND_I64_POSTRA |
| 12114 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 |
| 12115 | CEFBS_NotR5900, // ATOMIC_LOAD_AND_I8_POSTRA |
| 12116 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 |
| 12117 | CEFBS_NotR5900, // ATOMIC_LOAD_MAX_I16_POSTRA |
| 12118 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 |
| 12119 | CEFBS_NotR5900, // ATOMIC_LOAD_MAX_I32_POSTRA |
| 12120 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 |
| 12121 | CEFBS_NotR5900, // ATOMIC_LOAD_MAX_I64_POSTRA |
| 12122 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 |
| 12123 | CEFBS_NotR5900, // ATOMIC_LOAD_MAX_I8_POSTRA |
| 12124 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 |
| 12125 | CEFBS_NotR5900, // ATOMIC_LOAD_MIN_I16_POSTRA |
| 12126 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 |
| 12127 | CEFBS_NotR5900, // ATOMIC_LOAD_MIN_I32_POSTRA |
| 12128 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 |
| 12129 | CEFBS_NotR5900, // ATOMIC_LOAD_MIN_I64_POSTRA |
| 12130 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 |
| 12131 | CEFBS_NotR5900, // ATOMIC_LOAD_MIN_I8_POSTRA |
| 12132 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 |
| 12133 | CEFBS_NotR5900, // ATOMIC_LOAD_NAND_I16_POSTRA |
| 12134 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 |
| 12135 | CEFBS_NotR5900, // ATOMIC_LOAD_NAND_I32_POSTRA |
| 12136 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 |
| 12137 | CEFBS_NotR5900, // ATOMIC_LOAD_NAND_I64_POSTRA |
| 12138 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 |
| 12139 | CEFBS_NotR5900, // ATOMIC_LOAD_NAND_I8_POSTRA |
| 12140 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 |
| 12141 | CEFBS_NotR5900, // ATOMIC_LOAD_OR_I16_POSTRA |
| 12142 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 |
| 12143 | CEFBS_NotR5900, // ATOMIC_LOAD_OR_I32_POSTRA |
| 12144 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 |
| 12145 | CEFBS_NotR5900, // ATOMIC_LOAD_OR_I64_POSTRA |
| 12146 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 |
| 12147 | CEFBS_NotR5900, // ATOMIC_LOAD_OR_I8_POSTRA |
| 12148 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 |
| 12149 | CEFBS_NotR5900, // ATOMIC_LOAD_SUB_I16_POSTRA |
| 12150 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 |
| 12151 | CEFBS_NotR5900, // ATOMIC_LOAD_SUB_I32_POSTRA |
| 12152 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 |
| 12153 | CEFBS_NotR5900, // ATOMIC_LOAD_SUB_I64_POSTRA |
| 12154 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 |
| 12155 | CEFBS_NotR5900, // ATOMIC_LOAD_SUB_I8_POSTRA |
| 12156 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 |
| 12157 | CEFBS_NotR5900, // ATOMIC_LOAD_UMAX_I16_POSTRA |
| 12158 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 |
| 12159 | CEFBS_NotR5900, // ATOMIC_LOAD_UMAX_I32_POSTRA |
| 12160 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 |
| 12161 | CEFBS_NotR5900, // ATOMIC_LOAD_UMAX_I64_POSTRA |
| 12162 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 |
| 12163 | CEFBS_NotR5900, // ATOMIC_LOAD_UMAX_I8_POSTRA |
| 12164 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 |
| 12165 | CEFBS_NotR5900, // ATOMIC_LOAD_UMIN_I16_POSTRA |
| 12166 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 |
| 12167 | CEFBS_NotR5900, // ATOMIC_LOAD_UMIN_I32_POSTRA |
| 12168 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 |
| 12169 | CEFBS_NotR5900, // ATOMIC_LOAD_UMIN_I64_POSTRA |
| 12170 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 |
| 12171 | CEFBS_NotR5900, // ATOMIC_LOAD_UMIN_I8_POSTRA |
| 12172 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 |
| 12173 | CEFBS_NotR5900, // ATOMIC_LOAD_XOR_I16_POSTRA |
| 12174 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 |
| 12175 | CEFBS_NotR5900, // ATOMIC_LOAD_XOR_I32_POSTRA |
| 12176 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 |
| 12177 | CEFBS_NotR5900, // ATOMIC_LOAD_XOR_I64_POSTRA |
| 12178 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 |
| 12179 | CEFBS_NotR5900, // ATOMIC_LOAD_XOR_I8_POSTRA |
| 12180 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 |
| 12181 | CEFBS_NotR5900, // ATOMIC_SWAP_I16_POSTRA |
| 12182 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 |
| 12183 | CEFBS_NotR5900, // ATOMIC_SWAP_I32_POSTRA |
| 12184 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 |
| 12185 | CEFBS_NotR5900, // ATOMIC_SWAP_I64_POSTRA |
| 12186 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 |
| 12187 | CEFBS_NotR5900, // ATOMIC_SWAP_I8_POSTRA |
| 12188 | CEFBS_HasStdEnc_NotInMicroMips, // B |
| 12189 | CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR |
| 12190 | CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM |
| 12191 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro |
| 12192 | CEFBS_None, // BGE |
| 12193 | CEFBS_None, // BGEImmMacro |
| 12194 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL |
| 12195 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro |
| 12196 | CEFBS_None, // BGEU |
| 12197 | CEFBS_None, // BGEUImmMacro |
| 12198 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL |
| 12199 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro |
| 12200 | CEFBS_None, // BGT |
| 12201 | CEFBS_None, // BGTImmMacro |
| 12202 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL |
| 12203 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro |
| 12204 | CEFBS_None, // BGTU |
| 12205 | CEFBS_None, // BGTUImmMacro |
| 12206 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL |
| 12207 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro |
| 12208 | CEFBS_None, // BLE |
| 12209 | CEFBS_None, // BLEImmMacro |
| 12210 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL |
| 12211 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro |
| 12212 | CEFBS_None, // BLEU |
| 12213 | CEFBS_None, // BLEUImmMacro |
| 12214 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL |
| 12215 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro |
| 12216 | CEFBS_None, // BLT |
| 12217 | CEFBS_None, // BLTImmMacro |
| 12218 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL |
| 12219 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro |
| 12220 | CEFBS_None, // BLTU |
| 12221 | CEFBS_None, // BLTUImmMacro |
| 12222 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL |
| 12223 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro |
| 12224 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro |
| 12225 | CEFBS_None, // BPOSGE32_PSEUDO |
| 12226 | CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO |
| 12227 | CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO |
| 12228 | CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO |
| 12229 | CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO |
| 12230 | CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO |
| 12231 | CEFBS_InMicroMips_NotMips32r6, // B_MM |
| 12232 | CEFBS_None, // B_MMR6_Pseudo |
| 12233 | CEFBS_InMicroMips, // B_MM_Pseudo |
| 12234 | CEFBS_None, // BeqImm |
| 12235 | CEFBS_None, // BneImm |
| 12236 | CEFBS_InMips16Mode, // BteqzT8CmpX16 |
| 12237 | CEFBS_InMips16Mode, // BteqzT8CmpiX16 |
| 12238 | CEFBS_InMips16Mode, // BteqzT8SltX16 |
| 12239 | CEFBS_InMips16Mode, // BteqzT8SltiX16 |
| 12240 | CEFBS_InMips16Mode, // BteqzT8SltiuX16 |
| 12241 | CEFBS_InMips16Mode, // BteqzT8SltuX16 |
| 12242 | CEFBS_InMips16Mode, // BtnezT8CmpX16 |
| 12243 | CEFBS_InMips16Mode, // BtnezT8CmpiX16 |
| 12244 | CEFBS_InMips16Mode, // BtnezT8SltX16 |
| 12245 | CEFBS_InMips16Mode, // BtnezT8SltiX16 |
| 12246 | CEFBS_InMips16Mode, // BtnezT8SltiuX16 |
| 12247 | CEFBS_InMips16Mode, // BtnezT8SltuX16 |
| 12248 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 |
| 12249 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 |
| 12250 | CEFBS_HasMT, // CFTC1 |
| 12251 | CEFBS_InMips16Mode, // CONSTPOOL_ENTRY |
| 12252 | CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO |
| 12253 | CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO |
| 12254 | CEFBS_HasMT, // CTTC1 |
| 12255 | CEFBS_InMips16Mode, // Constant32 |
| 12256 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // DMULImmMacro |
| 12257 | CEFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900, // DMULMacro |
| 12258 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // DMULOMacro |
| 12259 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // DMULOUMacro |
| 12260 | CEFBS_HasStdEnc_HasMips64, // DROL |
| 12261 | CEFBS_HasStdEnc_HasMips64, // DROLImm |
| 12262 | CEFBS_HasStdEnc_HasMips64, // DROR |
| 12263 | CEFBS_HasStdEnc_HasMips64, // DRORImm |
| 12264 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSDivIMacro |
| 12265 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSDivMacro |
| 12266 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSRemIMacro |
| 12267 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSRemMacro |
| 12268 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DUDivIMacro |
| 12269 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DUDivMacro |
| 12270 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DURemIMacro |
| 12271 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DURemMacro |
| 12272 | CEFBS_NotInMips16Mode, // ERet |
| 12273 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 |
| 12274 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 |
| 12275 | CEFBS_HasStdEnc_HasMSA, // FABS_D |
| 12276 | CEFBS_HasStdEnc_HasMSA, // FABS_W |
| 12277 | CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO |
| 12278 | CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO |
| 12279 | CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO |
| 12280 | CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO |
| 12281 | CEFBS_InMips16Mode, // GotPrologue16 |
| 12282 | CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO |
| 12283 | CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO |
| 12284 | CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO |
| 12285 | CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO |
| 12286 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO |
| 12287 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO |
| 12288 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO |
| 12289 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO |
| 12290 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO |
| 12291 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO |
| 12292 | CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO |
| 12293 | CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO |
| 12294 | CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO |
| 12295 | CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO |
| 12296 | CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo |
| 12297 | CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo |
| 12298 | CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo |
| 12299 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo |
| 12300 | CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 |
| 12301 | CEFBS_None, // JalOneReg |
| 12302 | CEFBS_None, // JalTwoReg |
| 12303 | CEFBS_HasStdEnc_NotMips3, // LDMacro |
| 12304 | CEFBS_NotInMips16Mode, // LDR_D |
| 12305 | CEFBS_NotInMips16Mode, // LDR_W |
| 12306 | CEFBS_HasMSA, // LD_F16 |
| 12307 | CEFBS_NotInMips16Mode, // LOAD_ACC128 |
| 12308 | CEFBS_NotInMips16Mode, // LOAD_ACC64 |
| 12309 | CEFBS_NotInMips16Mode, // LOAD_ACC64DSP |
| 12310 | CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP |
| 12311 | CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu |
| 12312 | CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op |
| 12313 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu |
| 12314 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op |
| 12315 | CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi |
| 12316 | CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op |
| 12317 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 |
| 12318 | CEFBS_InMicroMips, // LWM_MM |
| 12319 | CEFBS_None, // LoadAddrImm32 |
| 12320 | CEFBS_None, // LoadAddrImm64 |
| 12321 | CEFBS_None, // LoadAddrReg32 |
| 12322 | CEFBS_None, // LoadAddrReg64 |
| 12323 | CEFBS_None, // LoadImm32 |
| 12324 | CEFBS_None, // LoadImm64 |
| 12325 | CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR |
| 12326 | CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 |
| 12327 | CEFBS_None, // LoadImmDoubleGPR |
| 12328 | CEFBS_IsNotSoftFloat, // LoadImmSingleFGR |
| 12329 | CEFBS_None, // LoadImmSingleGPR |
| 12330 | CEFBS_InMips16Mode, // LwConstant32 |
| 12331 | CEFBS_HasMT, // MFTACX |
| 12332 | CEFBS_HasMT, // MFTC0 |
| 12333 | CEFBS_HasMT, // MFTC1 |
| 12334 | CEFBS_HasMT, // MFTDSP |
| 12335 | CEFBS_HasMT, // MFTGPR |
| 12336 | CEFBS_HasMT, // MFTHC1 |
| 12337 | CEFBS_HasMT, // MFTHI |
| 12338 | CEFBS_HasMT, // MFTLO |
| 12339 | CEFBS_None, // MIPSeh_return32 |
| 12340 | CEFBS_None, // MIPSeh_return64 |
| 12341 | CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO |
| 12342 | CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO |
| 12343 | CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO |
| 12344 | CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO |
| 12345 | CEFBS_HasMT, // MTTACX |
| 12346 | CEFBS_HasMT, // MTTC0 |
| 12347 | CEFBS_HasMT, // MTTC1 |
| 12348 | CEFBS_HasMT, // MTTDSP |
| 12349 | CEFBS_HasMT, // MTTGPR |
| 12350 | CEFBS_HasMT, // MTTHC1 |
| 12351 | CEFBS_HasMT, // MTTHI |
| 12352 | CEFBS_HasMT, // MTTLO |
| 12353 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro |
| 12354 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro |
| 12355 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro |
| 12356 | CEFBS_InMips16Mode, // MultRxRy16 |
| 12357 | CEFBS_InMips16Mode, // MultRxRyRz16 |
| 12358 | CEFBS_InMips16Mode, // MultuRxRy16 |
| 12359 | CEFBS_InMips16Mode, // MultuRxRyRz16 |
| 12360 | CEFBS_HasStdEnc_NotInMicroMips, // NOP |
| 12361 | CEFBS_IsGP32bit, // NORImm |
| 12362 | CEFBS_IsGP64bit, // NORImm64 |
| 12363 | CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO |
| 12364 | CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO |
| 12365 | CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO |
| 12366 | CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO |
| 12367 | CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO |
| 12368 | CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO |
| 12369 | CEFBS_HasDSP, // PseudoCMPU_EQ_QB |
| 12370 | CEFBS_HasDSP, // PseudoCMPU_LE_QB |
| 12371 | CEFBS_HasDSP, // PseudoCMPU_LT_QB |
| 12372 | CEFBS_HasDSP, // PseudoCMP_EQ_PH |
| 12373 | CEFBS_HasDSP, // PseudoCMP_LE_PH |
| 12374 | CEFBS_HasDSP, // PseudoCMP_LT_PH |
| 12375 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W |
| 12376 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L |
| 12377 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W |
| 12378 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L |
| 12379 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W |
| 12380 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // PseudoDMULT |
| 12381 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // PseudoDMULTu |
| 12382 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // PseudoDSDIV |
| 12383 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // PseudoDUDIV |
| 12384 | CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I |
| 12385 | CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 |
| 12386 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch |
| 12387 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 |
| 12388 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 |
| 12389 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 |
| 12390 | CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM |
| 12391 | CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 |
| 12392 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch |
| 12393 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 |
| 12394 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 |
| 12395 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 |
| 12396 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD |
| 12397 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU |
| 12398 | CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM |
| 12399 | CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM |
| 12400 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI |
| 12401 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 |
| 12402 | CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM |
| 12403 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO |
| 12404 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 |
| 12405 | CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM |
| 12406 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB |
| 12407 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU |
| 12408 | CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM |
| 12409 | CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM |
| 12410 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI |
| 12411 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 |
| 12412 | CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP |
| 12413 | CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM |
| 12414 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT |
| 12415 | CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM |
| 12416 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu |
| 12417 | CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM |
| 12418 | CEFBS_HasDSP, // PseudoPICK_PH |
| 12419 | CEFBS_HasDSP, // PseudoPICK_QB |
| 12420 | CEFBS_None, // PseudoReturn |
| 12421 | CEFBS_IsGP64bit, // PseudoReturn64 |
| 12422 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV |
| 12423 | CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 |
| 12424 | CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 |
| 12425 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I |
| 12426 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 |
| 12427 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S |
| 12428 | CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 |
| 12429 | CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 |
| 12430 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I |
| 12431 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 |
| 12432 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S |
| 12433 | CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 |
| 12434 | CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 |
| 12435 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I |
| 12436 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 |
| 12437 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S |
| 12438 | CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D |
| 12439 | CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 |
| 12440 | CEFBS_None, // PseudoTRUNC_W_S |
| 12441 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV |
| 12442 | CEFBS_None, // ROL |
| 12443 | CEFBS_None, // ROLImm |
| 12444 | CEFBS_None, // ROR |
| 12445 | CEFBS_None, // RORImm |
| 12446 | CEFBS_NotInMips16Mode, // RetRA |
| 12447 | CEFBS_InMips16Mode, // RetRA16 |
| 12448 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 |
| 12449 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo |
| 12450 | CEFBS_HasStdEnc_NotMips3, // SDMacro |
| 12451 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro |
| 12452 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro |
| 12453 | CEFBS_NotCnMips, // SEQIMacro |
| 12454 | CEFBS_NotCnMips, // SEQMacro |
| 12455 | CEFBS_HasStdEnc_NotInMicroMips, // SGE |
| 12456 | CEFBS_IsGP32bit_NotInMicroMips, // SGEImm |
| 12457 | CEFBS_IsGP64bit, // SGEImm64 |
| 12458 | CEFBS_HasStdEnc_NotInMicroMips, // SGEU |
| 12459 | CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm |
| 12460 | CEFBS_IsGP64bit, // SGEUImm64 |
| 12461 | CEFBS_IsGP32bit_NotInMicroMips, // SGTImm |
| 12462 | CEFBS_IsGP64bit, // SGTImm64 |
| 12463 | CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm |
| 12464 | CEFBS_IsGP64bit, // SGTUImm64 |
| 12465 | CEFBS_HasStdEnc_NotInMicroMips, // SLE |
| 12466 | CEFBS_IsGP32bit_NotInMicroMips, // SLEImm |
| 12467 | CEFBS_IsGP64bit, // SLEImm64 |
| 12468 | CEFBS_HasStdEnc_NotInMicroMips, // SLEU |
| 12469 | CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm |
| 12470 | CEFBS_IsGP64bit, // SLEUImm64 |
| 12471 | CEFBS_IsGP64bit, // SLTImm64 |
| 12472 | CEFBS_IsGP64bit, // SLTUImm64 |
| 12473 | CEFBS_NotCnMips, // SNEIMacro |
| 12474 | CEFBS_NotCnMips, // SNEMacro |
| 12475 | CEFBS_None, // SNZ_B_PSEUDO |
| 12476 | CEFBS_None, // SNZ_D_PSEUDO |
| 12477 | CEFBS_None, // SNZ_H_PSEUDO |
| 12478 | CEFBS_None, // SNZ_V_PSEUDO |
| 12479 | CEFBS_None, // SNZ_W_PSEUDO |
| 12480 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro |
| 12481 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro |
| 12482 | CEFBS_NotInMips16Mode, // STORE_ACC128 |
| 12483 | CEFBS_NotInMips16Mode, // STORE_ACC64 |
| 12484 | CEFBS_NotInMips16Mode, // STORE_ACC64DSP |
| 12485 | CEFBS_NotInMips16Mode, // STORE_CCOND_DSP |
| 12486 | CEFBS_NotInMips16Mode, // STR_D |
| 12487 | CEFBS_NotInMips16Mode, // STR_W |
| 12488 | CEFBS_HasMSA, // ST_F16 |
| 12489 | CEFBS_InMicroMips, // SWM_MM |
| 12490 | CEFBS_None, // SZ_B_PSEUDO |
| 12491 | CEFBS_None, // SZ_D_PSEUDO |
| 12492 | CEFBS_None, // SZ_H_PSEUDO |
| 12493 | CEFBS_None, // SZ_V_PSEUDO |
| 12494 | CEFBS_None, // SZ_W_PSEUDO |
| 12495 | CEFBS_HasCnMipsP, // SaaAddr |
| 12496 | CEFBS_HasCnMipsP, // SaadAddr |
| 12497 | CEFBS_InMips16Mode, // SelBeqZ |
| 12498 | CEFBS_InMips16Mode, // SelBneZ |
| 12499 | CEFBS_InMips16Mode, // SelTBteqZCmp |
| 12500 | CEFBS_InMips16Mode, // SelTBteqZCmpi |
| 12501 | CEFBS_InMips16Mode, // SelTBteqZSlt |
| 12502 | CEFBS_InMips16Mode, // SelTBteqZSlti |
| 12503 | CEFBS_InMips16Mode, // SelTBteqZSltiu |
| 12504 | CEFBS_InMips16Mode, // SelTBteqZSltu |
| 12505 | CEFBS_InMips16Mode, // SelTBtneZCmp |
| 12506 | CEFBS_InMips16Mode, // SelTBtneZCmpi |
| 12507 | CEFBS_InMips16Mode, // SelTBtneZSlt |
| 12508 | CEFBS_InMips16Mode, // SelTBtneZSlti |
| 12509 | CEFBS_InMips16Mode, // SelTBtneZSltiu |
| 12510 | CEFBS_InMips16Mode, // SelTBtneZSltu |
| 12511 | CEFBS_InMips16Mode, // SltCCRxRy16 |
| 12512 | CEFBS_InMips16Mode, // SltiCCRxImmX16 |
| 12513 | CEFBS_InMips16Mode, // SltiuCCRxImmX16 |
| 12514 | CEFBS_InMips16Mode, // SltuCCRxRy16 |
| 12515 | CEFBS_InMips16Mode, // SltuRxRyRz16 |
| 12516 | CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL |
| 12517 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG |
| 12518 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG |
| 12519 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG |
| 12520 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG |
| 12521 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG |
| 12522 | CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 |
| 12523 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB |
| 12524 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 |
| 12525 | CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM |
| 12526 | CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 |
| 12527 | CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM |
| 12528 | CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 |
| 12529 | CEFBS_HasStdEnc_NotInMicroMips, // TRAP |
| 12530 | CEFBS_InMicroMips, // TRAP_MM |
| 12531 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo |
| 12532 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro |
| 12533 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro |
| 12534 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro |
| 12535 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro |
| 12536 | CEFBS_None, // Ulh |
| 12537 | CEFBS_None, // Ulhu |
| 12538 | CEFBS_None, // Ulw |
| 12539 | CEFBS_None, // Ush |
| 12540 | CEFBS_None, // Usw |
| 12541 | CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO |
| 12542 | CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO |
| 12543 | CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO |
| 12544 | CEFBS_HasDSP, // ABSQ_S_PH |
| 12545 | CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM |
| 12546 | CEFBS_HasDSPR2, // ABSQ_S_QB |
| 12547 | CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 |
| 12548 | CEFBS_HasDSP, // ABSQ_S_W |
| 12549 | CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM |
| 12550 | CEFBS_HasStdEnc_NotInMicroMips, // ADD |
| 12551 | CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC |
| 12552 | CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM |
| 12553 | CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 |
| 12554 | CEFBS_InMicroMips, // ADDIUR1SP_MM |
| 12555 | CEFBS_InMicroMips, // ADDIUR2_MM |
| 12556 | CEFBS_InMicroMips, // ADDIUS5_MM |
| 12557 | CEFBS_InMicroMips, // ADDIUSP_MM |
| 12558 | CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 |
| 12559 | CEFBS_HasDSPR2, // ADDQH_PH |
| 12560 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 |
| 12561 | CEFBS_HasDSPR2, // ADDQH_R_PH |
| 12562 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 |
| 12563 | CEFBS_HasDSPR2, // ADDQH_R_W |
| 12564 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 |
| 12565 | CEFBS_HasDSPR2, // ADDQH_W |
| 12566 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 |
| 12567 | CEFBS_HasDSP, // ADDQ_PH |
| 12568 | CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM |
| 12569 | CEFBS_HasDSP, // ADDQ_S_PH |
| 12570 | CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM |
| 12571 | CEFBS_HasDSP, // ADDQ_S_W |
| 12572 | CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM |
| 12573 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 |
| 12574 | CEFBS_HasDSP, // ADDSC |
| 12575 | CEFBS_InMicroMips_HasDSP, // ADDSC_MM |
| 12576 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_B |
| 12577 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_D |
| 12578 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_H |
| 12579 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_W |
| 12580 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_B |
| 12581 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_D |
| 12582 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_H |
| 12583 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_W |
| 12584 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_B |
| 12585 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_D |
| 12586 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_H |
| 12587 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_W |
| 12588 | CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM |
| 12589 | CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 |
| 12590 | CEFBS_HasDSPR2, // ADDUH_QB |
| 12591 | CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 |
| 12592 | CEFBS_HasDSPR2, // ADDUH_R_QB |
| 12593 | CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 |
| 12594 | CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 |
| 12595 | CEFBS_HasDSPR2, // ADDU_PH |
| 12596 | CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 |
| 12597 | CEFBS_HasDSP, // ADDU_QB |
| 12598 | CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM |
| 12599 | CEFBS_HasDSPR2, // ADDU_S_PH |
| 12600 | CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 |
| 12601 | CEFBS_HasDSP, // ADDU_S_QB |
| 12602 | CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM |
| 12603 | CEFBS_HasStdEnc_HasMSA, // ADDVI_B |
| 12604 | CEFBS_HasStdEnc_HasMSA, // ADDVI_D |
| 12605 | CEFBS_HasStdEnc_HasMSA, // ADDVI_H |
| 12606 | CEFBS_HasStdEnc_HasMSA, // ADDVI_W |
| 12607 | CEFBS_HasStdEnc_HasMSA, // ADDV_B |
| 12608 | CEFBS_HasStdEnc_HasMSA, // ADDV_D |
| 12609 | CEFBS_HasStdEnc_HasMSA, // ADDV_H |
| 12610 | CEFBS_HasStdEnc_HasMSA, // ADDV_W |
| 12611 | CEFBS_HasDSP, // ADDWC |
| 12612 | CEFBS_InMicroMips_HasDSP, // ADDWC_MM |
| 12613 | CEFBS_HasStdEnc_HasMSA, // ADD_A_B |
| 12614 | CEFBS_HasStdEnc_HasMSA, // ADD_A_D |
| 12615 | CEFBS_HasStdEnc_HasMSA, // ADD_A_H |
| 12616 | CEFBS_HasStdEnc_HasMSA, // ADD_A_W |
| 12617 | CEFBS_InMicroMips_NotMips32r6, // ADD_MM |
| 12618 | CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 |
| 12619 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi |
| 12620 | CEFBS_InMicroMips_NotMips32r6, // ADDi_MM |
| 12621 | CEFBS_HasStdEnc_NotInMicroMips, // ADDiu |
| 12622 | CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM |
| 12623 | CEFBS_HasStdEnc_NotInMicroMips, // ADDu |
| 12624 | CEFBS_InMicroMips_NotMips32r6, // ADDu_MM |
| 12625 | CEFBS_HasStdEnc_HasMips32r6, // ALIGN |
| 12626 | CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 |
| 12627 | CEFBS_HasStdEnc_HasMips32r6, // ALUIPC |
| 12628 | CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 |
| 12629 | CEFBS_HasStdEnc_NotInMicroMips, // AND |
| 12630 | CEFBS_InMicroMips_NotMips32r6, // AND16_MM |
| 12631 | CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 |
| 12632 | CEFBS_NotInMips16Mode_IsGP64bit, // AND64 |
| 12633 | CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM |
| 12634 | CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 |
| 12635 | CEFBS_HasStdEnc_HasMSA, // ANDI_B |
| 12636 | CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 |
| 12637 | CEFBS_InMicroMips_NotMips32r6, // AND_MM |
| 12638 | CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 |
| 12639 | CEFBS_HasStdEnc_HasMSA, // AND_V |
| 12640 | CEFBS_HasStdEnc_NotInMicroMips, // ANDi |
| 12641 | CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 |
| 12642 | CEFBS_InMicroMips_NotMips32r6, // ANDi_MM |
| 12643 | CEFBS_HasDSPR2, // APPEND |
| 12644 | CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 |
| 12645 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_B |
| 12646 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_D |
| 12647 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_H |
| 12648 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_W |
| 12649 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_B |
| 12650 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_D |
| 12651 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_H |
| 12652 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_W |
| 12653 | CEFBS_HasStdEnc_HasMips32r6, // AUI |
| 12654 | CEFBS_HasStdEnc_HasMips32r6, // AUIPC |
| 12655 | CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 |
| 12656 | CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 |
| 12657 | CEFBS_HasStdEnc_HasMSA, // AVER_S_B |
| 12658 | CEFBS_HasStdEnc_HasMSA, // AVER_S_D |
| 12659 | CEFBS_HasStdEnc_HasMSA, // AVER_S_H |
| 12660 | CEFBS_HasStdEnc_HasMSA, // AVER_S_W |
| 12661 | CEFBS_HasStdEnc_HasMSA, // AVER_U_B |
| 12662 | CEFBS_HasStdEnc_HasMSA, // AVER_U_D |
| 12663 | CEFBS_HasStdEnc_HasMSA, // AVER_U_H |
| 12664 | CEFBS_HasStdEnc_HasMSA, // AVER_U_W |
| 12665 | CEFBS_HasStdEnc_HasMSA, // AVE_S_B |
| 12666 | CEFBS_HasStdEnc_HasMSA, // AVE_S_D |
| 12667 | CEFBS_HasStdEnc_HasMSA, // AVE_S_H |
| 12668 | CEFBS_HasStdEnc_HasMSA, // AVE_S_W |
| 12669 | CEFBS_HasStdEnc_HasMSA, // AVE_U_B |
| 12670 | CEFBS_HasStdEnc_HasMSA, // AVE_U_D |
| 12671 | CEFBS_HasStdEnc_HasMSA, // AVE_U_H |
| 12672 | CEFBS_HasStdEnc_HasMSA, // AVE_U_W |
| 12673 | CEFBS_InMips16Mode, // AddiuRxImmX16 |
| 12674 | CEFBS_InMips16Mode, // AddiuRxPcImmX16 |
| 12675 | CEFBS_InMips16Mode, // AddiuRxRxImm16 |
| 12676 | CEFBS_InMips16Mode, // AddiuRxRxImmX16 |
| 12677 | CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 |
| 12678 | CEFBS_InMips16Mode, // AddiuSpImm16 |
| 12679 | CEFBS_InMips16Mode, // AddiuSpImmX16 |
| 12680 | CEFBS_InMips16Mode, // AdduRxRyRz16 |
| 12681 | CEFBS_InMips16Mode, // AndRxRxRy16 |
| 12682 | CEFBS_InMicroMips, // B16_MM |
| 12683 | CEFBS_HasCnMips, // BADDu |
| 12684 | CEFBS_HasStdEnc_HasMips32r6, // BAL |
| 12685 | CEFBS_HasStdEnc_HasMips32r6, // BALC |
| 12686 | CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 |
| 12687 | CEFBS_HasDSPR2, // BALIGN |
| 12688 | CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 |
| 12689 | CEFBS_HasCnMips, // BBIT0 |
| 12690 | CEFBS_HasCnMips, // BBIT032 |
| 12691 | CEFBS_HasCnMips, // BBIT1 |
| 12692 | CEFBS_HasCnMips, // BBIT132 |
| 12693 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC |
| 12694 | CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 |
| 12695 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ |
| 12696 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 |
| 12697 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F |
| 12698 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL |
| 12699 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM |
| 12700 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ |
| 12701 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 |
| 12702 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T |
| 12703 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL |
| 12704 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM |
| 12705 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ |
| 12706 | CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 |
| 12707 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ |
| 12708 | CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 |
| 12709 | CEFBS_HasStdEnc_HasMSA, // BCLRI_B |
| 12710 | CEFBS_HasStdEnc_HasMSA, // BCLRI_D |
| 12711 | CEFBS_HasStdEnc_HasMSA, // BCLRI_H |
| 12712 | CEFBS_HasStdEnc_HasMSA, // BCLRI_W |
| 12713 | CEFBS_HasStdEnc_HasMSA, // BCLR_B |
| 12714 | CEFBS_HasStdEnc_HasMSA, // BCLR_D |
| 12715 | CEFBS_HasStdEnc_HasMSA, // BCLR_H |
| 12716 | CEFBS_HasStdEnc_HasMSA, // BCLR_W |
| 12717 | CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 |
| 12718 | CEFBS_HasStdEnc_NotInMicroMips, // BEQ |
| 12719 | CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 |
| 12720 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC |
| 12721 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 |
| 12722 | CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 |
| 12723 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL |
| 12724 | CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM |
| 12725 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC |
| 12726 | CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 |
| 12727 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC |
| 12728 | CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 |
| 12729 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 |
| 12730 | CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM |
| 12731 | CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 |
| 12732 | CEFBS_InMicroMips_NotMips32r6, // BEQ_MM |
| 12733 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC |
| 12734 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 |
| 12735 | CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 |
| 12736 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC |
| 12737 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 |
| 12738 | CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 |
| 12739 | CEFBS_HasStdEnc_NotInMicroMips, // BGEZ |
| 12740 | CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 |
| 12741 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL |
| 12742 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC |
| 12743 | CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 |
| 12744 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL |
| 12745 | CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM |
| 12746 | CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM |
| 12747 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC |
| 12748 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 |
| 12749 | CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 |
| 12750 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL |
| 12751 | CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM |
| 12752 | CEFBS_HasStdEnc_NotInMicroMips, // BGTZ |
| 12753 | CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 |
| 12754 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC |
| 12755 | CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 |
| 12756 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC |
| 12757 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 |
| 12758 | CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 |
| 12759 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL |
| 12760 | CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM |
| 12761 | CEFBS_HasStdEnc_HasMSA, // BINSLI_B |
| 12762 | CEFBS_HasStdEnc_HasMSA, // BINSLI_D |
| 12763 | CEFBS_HasStdEnc_HasMSA, // BINSLI_H |
| 12764 | CEFBS_HasStdEnc_HasMSA, // BINSLI_W |
| 12765 | CEFBS_HasStdEnc_HasMSA, // BINSL_B |
| 12766 | CEFBS_HasStdEnc_HasMSA, // BINSL_D |
| 12767 | CEFBS_HasStdEnc_HasMSA, // BINSL_H |
| 12768 | CEFBS_HasStdEnc_HasMSA, // BINSL_W |
| 12769 | CEFBS_HasStdEnc_HasMSA, // BINSRI_B |
| 12770 | CEFBS_HasStdEnc_HasMSA, // BINSRI_D |
| 12771 | CEFBS_HasStdEnc_HasMSA, // BINSRI_H |
| 12772 | CEFBS_HasStdEnc_HasMSA, // BINSRI_W |
| 12773 | CEFBS_HasStdEnc_HasMSA, // BINSR_B |
| 12774 | CEFBS_HasStdEnc_HasMSA, // BINSR_D |
| 12775 | CEFBS_HasStdEnc_HasMSA, // BINSR_H |
| 12776 | CEFBS_HasStdEnc_HasMSA, // BINSR_W |
| 12777 | CEFBS_HasDSP, // BITREV |
| 12778 | CEFBS_InMicroMips_HasDSP, // BITREV_MM |
| 12779 | CEFBS_HasStdEnc_HasMips32r6, // BITSWAP |
| 12780 | CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 |
| 12781 | CEFBS_HasStdEnc_NotInMicroMips, // BLEZ |
| 12782 | CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 |
| 12783 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC |
| 12784 | CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 |
| 12785 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC |
| 12786 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 |
| 12787 | CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 |
| 12788 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL |
| 12789 | CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM |
| 12790 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC |
| 12791 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 |
| 12792 | CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 |
| 12793 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC |
| 12794 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 |
| 12795 | CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 |
| 12796 | CEFBS_HasStdEnc_NotInMicroMips, // BLTZ |
| 12797 | CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 |
| 12798 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL |
| 12799 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC |
| 12800 | CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 |
| 12801 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL |
| 12802 | CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM |
| 12803 | CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM |
| 12804 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC |
| 12805 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 |
| 12806 | CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 |
| 12807 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL |
| 12808 | CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM |
| 12809 | CEFBS_HasStdEnc_HasMSA, // BMNZI_B |
| 12810 | CEFBS_HasStdEnc_HasMSA, // BMNZ_V |
| 12811 | CEFBS_HasStdEnc_HasMSA, // BMZI_B |
| 12812 | CEFBS_HasStdEnc_HasMSA, // BMZ_V |
| 12813 | CEFBS_HasStdEnc_NotInMicroMips, // BNE |
| 12814 | CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 |
| 12815 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC |
| 12816 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 |
| 12817 | CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 |
| 12818 | CEFBS_HasStdEnc_HasMSA, // BNEGI_B |
| 12819 | CEFBS_HasStdEnc_HasMSA, // BNEGI_D |
| 12820 | CEFBS_HasStdEnc_HasMSA, // BNEGI_H |
| 12821 | CEFBS_HasStdEnc_HasMSA, // BNEGI_W |
| 12822 | CEFBS_HasStdEnc_HasMSA, // BNEG_B |
| 12823 | CEFBS_HasStdEnc_HasMSA, // BNEG_D |
| 12824 | CEFBS_HasStdEnc_HasMSA, // BNEG_H |
| 12825 | CEFBS_HasStdEnc_HasMSA, // BNEG_W |
| 12826 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL |
| 12827 | CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM |
| 12828 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC |
| 12829 | CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 |
| 12830 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC |
| 12831 | CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 |
| 12832 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 |
| 12833 | CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM |
| 12834 | CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 |
| 12835 | CEFBS_InMicroMips_NotMips32r6, // BNE_MM |
| 12836 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC |
| 12837 | CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 |
| 12838 | CEFBS_HasStdEnc_HasMSA, // BNZ_B |
| 12839 | CEFBS_HasStdEnc_HasMSA, // BNZ_D |
| 12840 | CEFBS_HasStdEnc_HasMSA, // BNZ_H |
| 12841 | CEFBS_HasStdEnc_HasMSA, // BNZ_V |
| 12842 | CEFBS_HasStdEnc_HasMSA, // BNZ_W |
| 12843 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC |
| 12844 | CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 |
| 12845 | CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 |
| 12846 | CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 |
| 12847 | CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM |
| 12848 | CEFBS_HasStdEnc_NotInMicroMips, // BREAK |
| 12849 | CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM |
| 12850 | CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 |
| 12851 | CEFBS_InMicroMips, // BREAK_MM |
| 12852 | CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 |
| 12853 | CEFBS_HasStdEnc_HasMSA, // BSELI_B |
| 12854 | CEFBS_HasStdEnc_HasMSA, // BSEL_V |
| 12855 | CEFBS_HasStdEnc_HasMSA, // BSETI_B |
| 12856 | CEFBS_HasStdEnc_HasMSA, // BSETI_D |
| 12857 | CEFBS_HasStdEnc_HasMSA, // BSETI_H |
| 12858 | CEFBS_HasStdEnc_HasMSA, // BSETI_W |
| 12859 | CEFBS_HasStdEnc_HasMSA, // BSET_B |
| 12860 | CEFBS_HasStdEnc_HasMSA, // BSET_D |
| 12861 | CEFBS_HasStdEnc_HasMSA, // BSET_H |
| 12862 | CEFBS_HasStdEnc_HasMSA, // BSET_W |
| 12863 | CEFBS_HasStdEnc_HasMSA, // BZ_B |
| 12864 | CEFBS_HasStdEnc_HasMSA, // BZ_D |
| 12865 | CEFBS_HasStdEnc_HasMSA, // BZ_H |
| 12866 | CEFBS_HasStdEnc_HasMSA, // BZ_V |
| 12867 | CEFBS_HasStdEnc_HasMSA, // BZ_W |
| 12868 | CEFBS_InMips16Mode, // BeqzRxImm16 |
| 12869 | CEFBS_InMips16Mode, // BeqzRxImmX16 |
| 12870 | CEFBS_InMips16Mode, // Bimm16 |
| 12871 | CEFBS_InMips16Mode, // BimmX16 |
| 12872 | CEFBS_InMips16Mode, // BnezRxImm16 |
| 12873 | CEFBS_InMips16Mode, // BnezRxImmX16 |
| 12874 | CEFBS_InMips16Mode, // Break16 |
| 12875 | CEFBS_InMips16Mode, // Bteqz16 |
| 12876 | CEFBS_InMips16Mode, // BteqzX16 |
| 12877 | CEFBS_InMips16Mode, // Btnez16 |
| 12878 | CEFBS_InMips16Mode, // BtnezX16 |
| 12879 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE |
| 12880 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE |
| 12881 | CEFBS_InMicroMips_HasEVA, // CACHEE_MM |
| 12882 | CEFBS_InMicroMips_NotMips32r6, // CACHE_MM |
| 12883 | CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 |
| 12884 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 |
| 12885 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 |
| 12886 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 |
| 12887 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S |
| 12888 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 |
| 12889 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 |
| 12890 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 |
| 12891 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 |
| 12892 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM |
| 12893 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S |
| 12894 | CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM |
| 12895 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 |
| 12896 | CEFBS_HasStdEnc_HasMSA, // CEQI_B |
| 12897 | CEFBS_HasStdEnc_HasMSA, // CEQI_D |
| 12898 | CEFBS_HasStdEnc_HasMSA, // CEQI_H |
| 12899 | CEFBS_HasStdEnc_HasMSA, // CEQI_W |
| 12900 | CEFBS_HasStdEnc_HasMSA, // CEQ_B |
| 12901 | CEFBS_HasStdEnc_HasMSA, // CEQ_D |
| 12902 | CEFBS_HasStdEnc_HasMSA, // CEQ_H |
| 12903 | CEFBS_HasStdEnc_HasMSA, // CEQ_W |
| 12904 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 |
| 12905 | CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM |
| 12906 | CEFBS_InMicroMips, // CFC2_MM |
| 12907 | CEFBS_HasStdEnc_HasMSA, // CFCMSA |
| 12908 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS |
| 12909 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 |
| 12910 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 |
| 12911 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 |
| 12912 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D |
| 12913 | CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 |
| 12914 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S |
| 12915 | CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 |
| 12916 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_B |
| 12917 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_D |
| 12918 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_H |
| 12919 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_W |
| 12920 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_B |
| 12921 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_D |
| 12922 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_H |
| 12923 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_W |
| 12924 | CEFBS_HasStdEnc_HasMSA, // CLE_S_B |
| 12925 | CEFBS_HasStdEnc_HasMSA, // CLE_S_D |
| 12926 | CEFBS_HasStdEnc_HasMSA, // CLE_S_H |
| 12927 | CEFBS_HasStdEnc_HasMSA, // CLE_S_W |
| 12928 | CEFBS_HasStdEnc_HasMSA, // CLE_U_B |
| 12929 | CEFBS_HasStdEnc_HasMSA, // CLE_U_D |
| 12930 | CEFBS_HasStdEnc_HasMSA, // CLE_U_H |
| 12931 | CEFBS_HasStdEnc_HasMSA, // CLE_U_W |
| 12932 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO |
| 12933 | CEFBS_InMicroMips, // CLO_MM |
| 12934 | CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 |
| 12935 | CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 |
| 12936 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_B |
| 12937 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_D |
| 12938 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_H |
| 12939 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_W |
| 12940 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_B |
| 12941 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_D |
| 12942 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_H |
| 12943 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_W |
| 12944 | CEFBS_HasStdEnc_HasMSA, // CLT_S_B |
| 12945 | CEFBS_HasStdEnc_HasMSA, // CLT_S_D |
| 12946 | CEFBS_HasStdEnc_HasMSA, // CLT_S_H |
| 12947 | CEFBS_HasStdEnc_HasMSA, // CLT_S_W |
| 12948 | CEFBS_HasStdEnc_HasMSA, // CLT_U_B |
| 12949 | CEFBS_HasStdEnc_HasMSA, // CLT_U_D |
| 12950 | CEFBS_HasStdEnc_HasMSA, // CLT_U_H |
| 12951 | CEFBS_HasStdEnc_HasMSA, // CLT_U_W |
| 12952 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ |
| 12953 | CEFBS_InMicroMips, // CLZ_MM |
| 12954 | CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 |
| 12955 | CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 |
| 12956 | CEFBS_HasDSPR2, // CMPGDU_EQ_QB |
| 12957 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 |
| 12958 | CEFBS_HasDSPR2, // CMPGDU_LE_QB |
| 12959 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 |
| 12960 | CEFBS_HasDSPR2, // CMPGDU_LT_QB |
| 12961 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 |
| 12962 | CEFBS_HasDSP, // CMPGU_EQ_QB |
| 12963 | CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM |
| 12964 | CEFBS_HasDSP, // CMPGU_LE_QB |
| 12965 | CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM |
| 12966 | CEFBS_HasDSP, // CMPGU_LT_QB |
| 12967 | CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM |
| 12968 | CEFBS_HasDSP, // CMPU_EQ_QB |
| 12969 | CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM |
| 12970 | CEFBS_HasDSP, // CMPU_LE_QB |
| 12971 | CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM |
| 12972 | CEFBS_HasDSP, // CMPU_LT_QB |
| 12973 | CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM |
| 12974 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 |
| 12975 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 |
| 12976 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D |
| 12977 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 |
| 12978 | CEFBS_HasDSP, // CMP_EQ_PH |
| 12979 | CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM |
| 12980 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S |
| 12981 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 |
| 12982 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D |
| 12983 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S |
| 12984 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D |
| 12985 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 |
| 12986 | CEFBS_HasDSP, // CMP_LE_PH |
| 12987 | CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM |
| 12988 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S |
| 12989 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 |
| 12990 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D |
| 12991 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 |
| 12992 | CEFBS_HasDSP, // CMP_LT_PH |
| 12993 | CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM |
| 12994 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S |
| 12995 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 |
| 12996 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D |
| 12997 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 |
| 12998 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S |
| 12999 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 |
| 13000 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D |
| 13001 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 |
| 13002 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S |
| 13003 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 |
| 13004 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D |
| 13005 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 |
| 13006 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S |
| 13007 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 |
| 13008 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D |
| 13009 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 |
| 13010 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S |
| 13011 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 |
| 13012 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D |
| 13013 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 |
| 13014 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S |
| 13015 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 |
| 13016 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D |
| 13017 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 |
| 13018 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S |
| 13019 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 |
| 13020 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D |
| 13021 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 |
| 13022 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S |
| 13023 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 |
| 13024 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D |
| 13025 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 |
| 13026 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S |
| 13027 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 |
| 13028 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D |
| 13029 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 |
| 13030 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S |
| 13031 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 |
| 13032 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D |
| 13033 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 |
| 13034 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S |
| 13035 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 |
| 13036 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D |
| 13037 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 |
| 13038 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S |
| 13039 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 |
| 13040 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D |
| 13041 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 |
| 13042 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S |
| 13043 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 |
| 13044 | CEFBS_HasStdEnc_HasMSA, // COPY_S_B |
| 13045 | CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D |
| 13046 | CEFBS_HasStdEnc_HasMSA, // COPY_S_H |
| 13047 | CEFBS_HasStdEnc_HasMSA, // COPY_S_W |
| 13048 | CEFBS_HasStdEnc_HasMSA, // COPY_U_B |
| 13049 | CEFBS_HasStdEnc_HasMSA, // COPY_U_H |
| 13050 | CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W |
| 13051 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B |
| 13052 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB |
| 13053 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD |
| 13054 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH |
| 13055 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW |
| 13056 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D |
| 13057 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H |
| 13058 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W |
| 13059 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 |
| 13060 | CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM |
| 13061 | CEFBS_InMicroMips, // CTC2_MM |
| 13062 | CEFBS_HasStdEnc_HasMSA, // CTCMSA |
| 13063 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S |
| 13064 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM |
| 13065 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W |
| 13066 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM |
| 13067 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L |
| 13068 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S |
| 13069 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM |
| 13070 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W |
| 13071 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM |
| 13072 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 |
| 13073 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 |
| 13074 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM |
| 13075 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 |
| 13076 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S |
| 13077 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM |
| 13078 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 |
| 13079 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 |
| 13080 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 |
| 13081 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 |
| 13082 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 |
| 13083 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM |
| 13084 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 |
| 13085 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM |
| 13086 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L |
| 13087 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 |
| 13088 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 |
| 13089 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 |
| 13090 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W |
| 13091 | CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM |
| 13092 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 |
| 13093 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 |
| 13094 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM |
| 13095 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 |
| 13096 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM |
| 13097 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S |
| 13098 | CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM |
| 13099 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 |
| 13100 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 |
| 13101 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM |
| 13102 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 |
| 13103 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM |
| 13104 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S |
| 13105 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM |
| 13106 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 |
| 13107 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM |
| 13108 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 |
| 13109 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM |
| 13110 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S |
| 13111 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM |
| 13112 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 |
| 13113 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM |
| 13114 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 |
| 13115 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM |
| 13116 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S |
| 13117 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM |
| 13118 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 |
| 13119 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM |
| 13120 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 |
| 13121 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM |
| 13122 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S |
| 13123 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM |
| 13124 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 |
| 13125 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM |
| 13126 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 |
| 13127 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM |
| 13128 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S |
| 13129 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM |
| 13130 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 |
| 13131 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM |
| 13132 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 |
| 13133 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM |
| 13134 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S |
| 13135 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM |
| 13136 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 |
| 13137 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM |
| 13138 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 |
| 13139 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM |
| 13140 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S |
| 13141 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM |
| 13142 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 |
| 13143 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM |
| 13144 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 |
| 13145 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM |
| 13146 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S |
| 13147 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM |
| 13148 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 |
| 13149 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM |
| 13150 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 |
| 13151 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM |
| 13152 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S |
| 13153 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM |
| 13154 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 |
| 13155 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM |
| 13156 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 |
| 13157 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM |
| 13158 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S |
| 13159 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM |
| 13160 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 |
| 13161 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM |
| 13162 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 |
| 13163 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM |
| 13164 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S |
| 13165 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM |
| 13166 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 |
| 13167 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM |
| 13168 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 |
| 13169 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM |
| 13170 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S |
| 13171 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM |
| 13172 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 |
| 13173 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM |
| 13174 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 |
| 13175 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM |
| 13176 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S |
| 13177 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM |
| 13178 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 |
| 13179 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM |
| 13180 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 |
| 13181 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM |
| 13182 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S |
| 13183 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM |
| 13184 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 |
| 13185 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM |
| 13186 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 |
| 13187 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM |
| 13188 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S |
| 13189 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM |
| 13190 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 |
| 13191 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM |
| 13192 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 |
| 13193 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM |
| 13194 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S |
| 13195 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM |
| 13196 | CEFBS_InMips16Mode, // CmpRxRy16 |
| 13197 | CEFBS_InMips16Mode, // CmpiRxImm16 |
| 13198 | CEFBS_InMips16Mode, // CmpiRxImmX16 |
| 13199 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD |
| 13200 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi |
| 13201 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu |
| 13202 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu |
| 13203 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI |
| 13204 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN |
| 13205 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI |
| 13206 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI |
| 13207 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP |
| 13208 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO |
| 13209 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 |
| 13210 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ |
| 13211 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 |
| 13212 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV |
| 13213 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU |
| 13214 | CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET |
| 13215 | CEFBS_InMicroMips, // DERET_MM |
| 13216 | CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 |
| 13217 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT |
| 13218 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 |
| 13219 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM |
| 13220 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU |
| 13221 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI |
| 13222 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS |
| 13223 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM |
| 13224 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU |
| 13225 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV |
| 13226 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU |
| 13227 | CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 |
| 13228 | CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 |
| 13229 | CEFBS_HasStdEnc_HasMSA, // DIV_S_B |
| 13230 | CEFBS_HasStdEnc_HasMSA, // DIV_S_D |
| 13231 | CEFBS_HasStdEnc_HasMSA, // DIV_S_H |
| 13232 | CEFBS_HasStdEnc_HasMSA, // DIV_S_W |
| 13233 | CEFBS_HasStdEnc_HasMSA, // DIV_U_B |
| 13234 | CEFBS_HasStdEnc_HasMSA, // DIV_U_D |
| 13235 | CEFBS_HasStdEnc_HasMSA, // DIV_U_H |
| 13236 | CEFBS_HasStdEnc_HasMSA, // DIV_U_W |
| 13237 | CEFBS_InMicroMips, // DI_MM |
| 13238 | CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 |
| 13239 | CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA |
| 13240 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 |
| 13241 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 |
| 13242 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 |
| 13243 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 |
| 13244 | CEFBS_HasCnMips, // DMFC2_OCTEON |
| 13245 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 |
| 13246 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD |
| 13247 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU |
| 13248 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT |
| 13249 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 |
| 13250 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 |
| 13251 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 |
| 13252 | CEFBS_HasCnMips, // DMTC2_OCTEON |
| 13253 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 |
| 13254 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH |
| 13255 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU |
| 13256 | CEFBS_HasCnMips, // DMUL |
| 13257 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DMULT |
| 13258 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DMULTu |
| 13259 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU |
| 13260 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 |
| 13261 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_D |
| 13262 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_H |
| 13263 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_W |
| 13264 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_D |
| 13265 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_H |
| 13266 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_W |
| 13267 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_D |
| 13268 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_H |
| 13269 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_W |
| 13270 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_D |
| 13271 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_H |
| 13272 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_W |
| 13273 | CEFBS_HasDSPR2, // DPAQX_SA_W_PH |
| 13274 | CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 |
| 13275 | CEFBS_HasDSPR2, // DPAQX_S_W_PH |
| 13276 | CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 |
| 13277 | CEFBS_HasDSP, // DPAQ_SA_L_W |
| 13278 | CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM |
| 13279 | CEFBS_HasDSP, // DPAQ_S_W_PH |
| 13280 | CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM |
| 13281 | CEFBS_HasDSP, // DPAU_H_QBL |
| 13282 | CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM |
| 13283 | CEFBS_HasDSP, // DPAU_H_QBR |
| 13284 | CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM |
| 13285 | CEFBS_HasDSPR2, // DPAX_W_PH |
| 13286 | CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 |
| 13287 | CEFBS_HasDSPR2, // DPA_W_PH |
| 13288 | CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 |
| 13289 | CEFBS_HasCnMips, // DPOP |
| 13290 | CEFBS_HasDSPR2, // DPSQX_SA_W_PH |
| 13291 | CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 |
| 13292 | CEFBS_HasDSPR2, // DPSQX_S_W_PH |
| 13293 | CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 |
| 13294 | CEFBS_HasDSP, // DPSQ_SA_L_W |
| 13295 | CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM |
| 13296 | CEFBS_HasDSP, // DPSQ_S_W_PH |
| 13297 | CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM |
| 13298 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D |
| 13299 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H |
| 13300 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W |
| 13301 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D |
| 13302 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H |
| 13303 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W |
| 13304 | CEFBS_HasDSP, // DPSU_H_QBL |
| 13305 | CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM |
| 13306 | CEFBS_HasDSP, // DPSU_H_QBR |
| 13307 | CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM |
| 13308 | CEFBS_HasDSPR2, // DPSX_W_PH |
| 13309 | CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 |
| 13310 | CEFBS_HasDSPR2, // DPS_W_PH |
| 13311 | CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 |
| 13312 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR |
| 13313 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 |
| 13314 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV |
| 13315 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH |
| 13316 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DSDIV |
| 13317 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD |
| 13318 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL |
| 13319 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 |
| 13320 | CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 |
| 13321 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV |
| 13322 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA |
| 13323 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 |
| 13324 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV |
| 13325 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL |
| 13326 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 |
| 13327 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV |
| 13328 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB |
| 13329 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu |
| 13330 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // DUDIV |
| 13331 | CEFBS_HasStdEnc_HasMips32r6, // DVP |
| 13332 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE |
| 13333 | CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 |
| 13334 | CEFBS_InMips16Mode, // DivRxRy16 |
| 13335 | CEFBS_InMips16Mode, // DivuRxRy16 |
| 13336 | CEFBS_HasStdEnc_NotInMicroMips, // EHB |
| 13337 | CEFBS_InMicroMips, // EHB_MM |
| 13338 | CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 |
| 13339 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI |
| 13340 | CEFBS_InMicroMips, // EI_MM |
| 13341 | CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 |
| 13342 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT |
| 13343 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET |
| 13344 | CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC |
| 13345 | CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 |
| 13346 | CEFBS_InMicroMips, // ERET_MM |
| 13347 | CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 |
| 13348 | CEFBS_HasStdEnc_HasMips32r6, // EVP |
| 13349 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE |
| 13350 | CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 |
| 13351 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT |
| 13352 | CEFBS_HasDSP, // EXTP |
| 13353 | CEFBS_HasDSP, // EXTPDP |
| 13354 | CEFBS_HasDSP, // EXTPDPV |
| 13355 | CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM |
| 13356 | CEFBS_InMicroMips_HasDSP, // EXTPDP_MM |
| 13357 | CEFBS_HasDSP, // EXTPV |
| 13358 | CEFBS_InMicroMips_HasDSP, // EXTPV_MM |
| 13359 | CEFBS_InMicroMips_HasDSP, // EXTP_MM |
| 13360 | CEFBS_HasDSP, // EXTRV_RS_W |
| 13361 | CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM |
| 13362 | CEFBS_HasDSP, // EXTRV_R_W |
| 13363 | CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM |
| 13364 | CEFBS_HasDSP, // EXTRV_S_H |
| 13365 | CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM |
| 13366 | CEFBS_HasDSP, // EXTRV_W |
| 13367 | CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM |
| 13368 | CEFBS_HasDSP, // EXTR_RS_W |
| 13369 | CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM |
| 13370 | CEFBS_HasDSP, // EXTR_R_W |
| 13371 | CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM |
| 13372 | CEFBS_HasDSP, // EXTR_S_H |
| 13373 | CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM |
| 13374 | CEFBS_HasDSP, // EXTR_W |
| 13375 | CEFBS_InMicroMips_HasDSP, // EXTR_W_MM |
| 13376 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS |
| 13377 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 |
| 13378 | CEFBS_InMicroMips_NotMips32r6, // EXT_MM |
| 13379 | CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 |
| 13380 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 |
| 13381 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM |
| 13382 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 |
| 13383 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM |
| 13384 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S |
| 13385 | CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM |
| 13386 | CEFBS_HasStdEnc_HasMSA, // FADD_D |
| 13387 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 |
| 13388 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM |
| 13389 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 |
| 13390 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM |
| 13391 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 |
| 13392 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S |
| 13393 | CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM |
| 13394 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 |
| 13395 | CEFBS_HasStdEnc_HasMSA, // FADD_W |
| 13396 | CEFBS_HasStdEnc_HasMSA, // FCAF_D |
| 13397 | CEFBS_HasStdEnc_HasMSA, // FCAF_W |
| 13398 | CEFBS_HasStdEnc_HasMSA, // FCEQ_D |
| 13399 | CEFBS_HasStdEnc_HasMSA, // FCEQ_W |
| 13400 | CEFBS_HasStdEnc_HasMSA, // FCLASS_D |
| 13401 | CEFBS_HasStdEnc_HasMSA, // FCLASS_W |
| 13402 | CEFBS_HasStdEnc_HasMSA, // FCLE_D |
| 13403 | CEFBS_HasStdEnc_HasMSA, // FCLE_W |
| 13404 | CEFBS_HasStdEnc_HasMSA, // FCLT_D |
| 13405 | CEFBS_HasStdEnc_HasMSA, // FCLT_W |
| 13406 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 |
| 13407 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM |
| 13408 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 |
| 13409 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 |
| 13410 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM |
| 13411 | CEFBS_HasStdEnc_HasMSA, // FCNE_D |
| 13412 | CEFBS_HasStdEnc_HasMSA, // FCNE_W |
| 13413 | CEFBS_HasStdEnc_HasMSA, // FCOR_D |
| 13414 | CEFBS_HasStdEnc_HasMSA, // FCOR_W |
| 13415 | CEFBS_HasStdEnc_HasMSA, // FCUEQ_D |
| 13416 | CEFBS_HasStdEnc_HasMSA, // FCUEQ_W |
| 13417 | CEFBS_HasStdEnc_HasMSA, // FCULE_D |
| 13418 | CEFBS_HasStdEnc_HasMSA, // FCULE_W |
| 13419 | CEFBS_HasStdEnc_HasMSA, // FCULT_D |
| 13420 | CEFBS_HasStdEnc_HasMSA, // FCULT_W |
| 13421 | CEFBS_HasStdEnc_HasMSA, // FCUNE_D |
| 13422 | CEFBS_HasStdEnc_HasMSA, // FCUNE_W |
| 13423 | CEFBS_HasStdEnc_HasMSA, // FCUN_D |
| 13424 | CEFBS_HasStdEnc_HasMSA, // FCUN_W |
| 13425 | CEFBS_HasStdEnc_HasMSA, // FDIV_D |
| 13426 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 |
| 13427 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM |
| 13428 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 |
| 13429 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM |
| 13430 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S |
| 13431 | CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM |
| 13432 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 |
| 13433 | CEFBS_HasStdEnc_HasMSA, // FDIV_W |
| 13434 | CEFBS_HasStdEnc_HasMSA, // FEXDO_H |
| 13435 | CEFBS_HasStdEnc_HasMSA, // FEXDO_W |
| 13436 | CEFBS_HasStdEnc_HasMSA, // FEXP2_D |
| 13437 | CEFBS_HasStdEnc_HasMSA, // FEXP2_W |
| 13438 | CEFBS_HasStdEnc_HasMSA, // FEXUPL_D |
| 13439 | CEFBS_HasStdEnc_HasMSA, // FEXUPL_W |
| 13440 | CEFBS_HasStdEnc_HasMSA, // FEXUPR_D |
| 13441 | CEFBS_HasStdEnc_HasMSA, // FEXUPR_W |
| 13442 | CEFBS_HasStdEnc_HasMSA, // FFINT_S_D |
| 13443 | CEFBS_HasStdEnc_HasMSA, // FFINT_S_W |
| 13444 | CEFBS_HasStdEnc_HasMSA, // FFINT_U_D |
| 13445 | CEFBS_HasStdEnc_HasMSA, // FFINT_U_W |
| 13446 | CEFBS_HasStdEnc_HasMSA, // FFQL_D |
| 13447 | CEFBS_HasStdEnc_HasMSA, // FFQL_W |
| 13448 | CEFBS_HasStdEnc_HasMSA, // FFQR_D |
| 13449 | CEFBS_HasStdEnc_HasMSA, // FFQR_W |
| 13450 | CEFBS_HasStdEnc_HasMSA, // FILL_B |
| 13451 | CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D |
| 13452 | CEFBS_HasStdEnc_HasMSA, // FILL_H |
| 13453 | CEFBS_HasStdEnc_HasMSA, // FILL_W |
| 13454 | CEFBS_HasStdEnc_HasMSA, // FLOG2_D |
| 13455 | CEFBS_HasStdEnc_HasMSA, // FLOG2_W |
| 13456 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 |
| 13457 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 |
| 13458 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S |
| 13459 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 |
| 13460 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 |
| 13461 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 |
| 13462 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 |
| 13463 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM |
| 13464 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S |
| 13465 | CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM |
| 13466 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 |
| 13467 | CEFBS_HasStdEnc_HasMSA, // FMADD_D |
| 13468 | CEFBS_HasStdEnc_HasMSA, // FMADD_W |
| 13469 | CEFBS_HasStdEnc_HasMSA, // FMAX_A_D |
| 13470 | CEFBS_HasStdEnc_HasMSA, // FMAX_A_W |
| 13471 | CEFBS_HasStdEnc_HasMSA, // FMAX_D |
| 13472 | CEFBS_HasStdEnc_HasMSA, // FMAX_W |
| 13473 | CEFBS_HasStdEnc_HasMSA, // FMIN_A_D |
| 13474 | CEFBS_HasStdEnc_HasMSA, // FMIN_A_W |
| 13475 | CEFBS_HasStdEnc_HasMSA, // FMIN_D |
| 13476 | CEFBS_HasStdEnc_HasMSA, // FMIN_W |
| 13477 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 |
| 13478 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM |
| 13479 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 |
| 13480 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM |
| 13481 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 |
| 13482 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S |
| 13483 | CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM |
| 13484 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 |
| 13485 | CEFBS_HasStdEnc_HasMSA, // FMSUB_D |
| 13486 | CEFBS_HasStdEnc_HasMSA, // FMSUB_W |
| 13487 | CEFBS_HasStdEnc_HasMSA, // FMUL_D |
| 13488 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 |
| 13489 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM |
| 13490 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 |
| 13491 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM |
| 13492 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 |
| 13493 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S |
| 13494 | CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM |
| 13495 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 |
| 13496 | CEFBS_HasStdEnc_HasMSA, // FMUL_W |
| 13497 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 |
| 13498 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM |
| 13499 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 |
| 13500 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM |
| 13501 | CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S |
| 13502 | CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM |
| 13503 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 |
| 13504 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK |
| 13505 | CEFBS_HasStdEnc_HasMSA, // FRCP_D |
| 13506 | CEFBS_HasStdEnc_HasMSA, // FRCP_W |
| 13507 | CEFBS_HasStdEnc_HasMSA, // FRINT_D |
| 13508 | CEFBS_HasStdEnc_HasMSA, // FRINT_W |
| 13509 | CEFBS_HasStdEnc_HasMSA, // FRSQRT_D |
| 13510 | CEFBS_HasStdEnc_HasMSA, // FRSQRT_W |
| 13511 | CEFBS_HasStdEnc_HasMSA, // FSAF_D |
| 13512 | CEFBS_HasStdEnc_HasMSA, // FSAF_W |
| 13513 | CEFBS_HasStdEnc_HasMSA, // FSEQ_D |
| 13514 | CEFBS_HasStdEnc_HasMSA, // FSEQ_W |
| 13515 | CEFBS_HasStdEnc_HasMSA, // FSLE_D |
| 13516 | CEFBS_HasStdEnc_HasMSA, // FSLE_W |
| 13517 | CEFBS_HasStdEnc_HasMSA, // FSLT_D |
| 13518 | CEFBS_HasStdEnc_HasMSA, // FSLT_W |
| 13519 | CEFBS_HasStdEnc_HasMSA, // FSNE_D |
| 13520 | CEFBS_HasStdEnc_HasMSA, // FSNE_W |
| 13521 | CEFBS_HasStdEnc_HasMSA, // FSOR_D |
| 13522 | CEFBS_HasStdEnc_HasMSA, // FSOR_W |
| 13523 | CEFBS_HasStdEnc_HasMSA, // FSQRT_D |
| 13524 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 |
| 13525 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM |
| 13526 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 |
| 13527 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM |
| 13528 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S |
| 13529 | CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM |
| 13530 | CEFBS_HasStdEnc_HasMSA, // FSQRT_W |
| 13531 | CEFBS_HasStdEnc_HasMSA, // FSUB_D |
| 13532 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 |
| 13533 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM |
| 13534 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 |
| 13535 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM |
| 13536 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 |
| 13537 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S |
| 13538 | CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM |
| 13539 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 |
| 13540 | CEFBS_HasStdEnc_HasMSA, // FSUB_W |
| 13541 | CEFBS_HasStdEnc_HasMSA, // FSUEQ_D |
| 13542 | CEFBS_HasStdEnc_HasMSA, // FSUEQ_W |
| 13543 | CEFBS_HasStdEnc_HasMSA, // FSULE_D |
| 13544 | CEFBS_HasStdEnc_HasMSA, // FSULE_W |
| 13545 | CEFBS_HasStdEnc_HasMSA, // FSULT_D |
| 13546 | CEFBS_HasStdEnc_HasMSA, // FSULT_W |
| 13547 | CEFBS_HasStdEnc_HasMSA, // FSUNE_D |
| 13548 | CEFBS_HasStdEnc_HasMSA, // FSUNE_W |
| 13549 | CEFBS_HasStdEnc_HasMSA, // FSUN_D |
| 13550 | CEFBS_HasStdEnc_HasMSA, // FSUN_W |
| 13551 | CEFBS_HasStdEnc_HasMSA, // FTINT_S_D |
| 13552 | CEFBS_HasStdEnc_HasMSA, // FTINT_S_W |
| 13553 | CEFBS_HasStdEnc_HasMSA, // FTINT_U_D |
| 13554 | CEFBS_HasStdEnc_HasMSA, // FTINT_U_W |
| 13555 | CEFBS_HasStdEnc_HasMSA, // FTQ_H |
| 13556 | CEFBS_HasStdEnc_HasMSA, // FTQ_W |
| 13557 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D |
| 13558 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W |
| 13559 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D |
| 13560 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W |
| 13561 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI |
| 13562 | CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 |
| 13563 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT |
| 13564 | CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 |
| 13565 | CEFBS_HasStdEnc_HasMSA, // HADD_S_D |
| 13566 | CEFBS_HasStdEnc_HasMSA, // HADD_S_H |
| 13567 | CEFBS_HasStdEnc_HasMSA, // HADD_S_W |
| 13568 | CEFBS_HasStdEnc_HasMSA, // HADD_U_D |
| 13569 | CEFBS_HasStdEnc_HasMSA, // HADD_U_H |
| 13570 | CEFBS_HasStdEnc_HasMSA, // HADD_U_W |
| 13571 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_D |
| 13572 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_H |
| 13573 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_W |
| 13574 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_D |
| 13575 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_H |
| 13576 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_W |
| 13577 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL |
| 13578 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM |
| 13579 | CEFBS_HasStdEnc_HasMSA, // ILVEV_B |
| 13580 | CEFBS_HasStdEnc_HasMSA, // ILVEV_D |
| 13581 | CEFBS_HasStdEnc_HasMSA, // ILVEV_H |
| 13582 | CEFBS_HasStdEnc_HasMSA, // ILVEV_W |
| 13583 | CEFBS_HasStdEnc_HasMSA, // ILVL_B |
| 13584 | CEFBS_HasStdEnc_HasMSA, // ILVL_D |
| 13585 | CEFBS_HasStdEnc_HasMSA, // ILVL_H |
| 13586 | CEFBS_HasStdEnc_HasMSA, // ILVL_W |
| 13587 | CEFBS_HasStdEnc_HasMSA, // ILVOD_B |
| 13588 | CEFBS_HasStdEnc_HasMSA, // ILVOD_D |
| 13589 | CEFBS_HasStdEnc_HasMSA, // ILVOD_H |
| 13590 | CEFBS_HasStdEnc_HasMSA, // ILVOD_W |
| 13591 | CEFBS_HasStdEnc_HasMSA, // ILVR_B |
| 13592 | CEFBS_HasStdEnc_HasMSA, // ILVR_D |
| 13593 | CEFBS_HasStdEnc_HasMSA, // ILVR_H |
| 13594 | CEFBS_HasStdEnc_HasMSA, // ILVR_W |
| 13595 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS |
| 13596 | CEFBS_HasStdEnc_HasMSA, // INSERT_B |
| 13597 | CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D |
| 13598 | CEFBS_HasStdEnc_HasMSA, // INSERT_H |
| 13599 | CEFBS_HasStdEnc_HasMSA, // INSERT_W |
| 13600 | CEFBS_HasDSP, // INSV |
| 13601 | CEFBS_HasStdEnc_HasMSA, // INSVE_B |
| 13602 | CEFBS_HasStdEnc_HasMSA, // INSVE_D |
| 13603 | CEFBS_HasStdEnc_HasMSA, // INSVE_H |
| 13604 | CEFBS_HasStdEnc_HasMSA, // INSVE_W |
| 13605 | CEFBS_InMicroMips_HasDSP, // INSV_MM |
| 13606 | CEFBS_InMicroMips_NotMips32r6, // INS_MM |
| 13607 | CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 |
| 13608 | CEFBS_HasStdEnc_NotInMicroMips, // J |
| 13609 | CEFBS_HasStdEnc_NotInMicroMips, // JAL |
| 13610 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR |
| 13611 | CEFBS_InMicroMips_NotMips32r6, // JALR16_MM |
| 13612 | CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 |
| 13613 | CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 |
| 13614 | CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 |
| 13615 | CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 |
| 13616 | CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM |
| 13617 | CEFBS_InMicroMips_NotMips32r6, // JALRS_MM |
| 13618 | CEFBS_HasStdEnc_HasMips32, // JALR_HB |
| 13619 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 |
| 13620 | CEFBS_InMicroMips_NotMips32r6, // JALR_MM |
| 13621 | CEFBS_InMicroMips_NotMips32r6, // JALS_MM |
| 13622 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX |
| 13623 | CEFBS_InMicroMips_NotMips32r6, // JALX_MM |
| 13624 | CEFBS_InMicroMips_NotMips32r6, // JAL_MM |
| 13625 | CEFBS_HasStdEnc_HasMips32r6, // JIALC |
| 13626 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 |
| 13627 | CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 |
| 13628 | CEFBS_HasStdEnc_HasMips32r6, // JIC |
| 13629 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 |
| 13630 | CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 |
| 13631 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR |
| 13632 | CEFBS_InMicroMips_NotMips32r6, // JR16_MM |
| 13633 | CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 |
| 13634 | CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP |
| 13635 | CEFBS_InMicroMips_NotMips32r6, // JRC16_MM |
| 13636 | CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 |
| 13637 | CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 |
| 13638 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB |
| 13639 | CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 |
| 13640 | CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 |
| 13641 | CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 |
| 13642 | CEFBS_InMicroMips_NotMips32r6, // JR_MM |
| 13643 | CEFBS_InMicroMips_NotMips32r6, // J_MM |
| 13644 | CEFBS_InMips16Mode, // Jal16 |
| 13645 | CEFBS_InMips16Mode, // JalB16 |
| 13646 | CEFBS_InMips16Mode, // JrRa16 |
| 13647 | CEFBS_InMips16Mode, // JrcRa16 |
| 13648 | CEFBS_InMips16Mode, // JrcRx16 |
| 13649 | CEFBS_InMips16Mode, // JumpLinkReg16 |
| 13650 | CEFBS_HasStdEnc_NotInMicroMips, // LB |
| 13651 | CEFBS_NotInMips16Mode_IsGP64bit, // LB64 |
| 13652 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE |
| 13653 | CEFBS_InMicroMips_HasEVA, // LBE_MM |
| 13654 | CEFBS_InMicroMips, // LBU16_MM |
| 13655 | CEFBS_HasDSP, // LBUX |
| 13656 | CEFBS_InMicroMips_HasDSP, // LBUX_MM |
| 13657 | CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 |
| 13658 | CEFBS_InMicroMips, // LB_MM |
| 13659 | CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 |
| 13660 | CEFBS_HasStdEnc_NotInMicroMips, // LBu |
| 13661 | CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 |
| 13662 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE |
| 13663 | CEFBS_InMicroMips_HasEVA, // LBuE_MM |
| 13664 | CEFBS_InMicroMips, // LBu_MM |
| 13665 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD |
| 13666 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 |
| 13667 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 |
| 13668 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 |
| 13669 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 |
| 13670 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 |
| 13671 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 |
| 13672 | CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 |
| 13673 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 |
| 13674 | CEFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, // LDC3 |
| 13675 | CEFBS_HasStdEnc_HasMSA, // LDI_B |
| 13676 | CEFBS_HasStdEnc_HasMSA, // LDI_D |
| 13677 | CEFBS_HasStdEnc_HasMSA, // LDI_H |
| 13678 | CEFBS_HasStdEnc_HasMSA, // LDI_W |
| 13679 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL |
| 13680 | CEFBS_HasStdEnc_HasMips64r6, // LDPC |
| 13681 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR |
| 13682 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 |
| 13683 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 |
| 13684 | CEFBS_HasStdEnc_HasMSA, // LD_B |
| 13685 | CEFBS_HasStdEnc_HasMSA, // LD_D |
| 13686 | CEFBS_HasStdEnc_HasMSA, // LD_H |
| 13687 | CEFBS_HasStdEnc_HasMSA, // LD_W |
| 13688 | CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu |
| 13689 | CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 |
| 13690 | CEFBS_InMicroMips, // LEA_ADDiu_MM |
| 13691 | CEFBS_HasStdEnc_NotInMicroMips, // LH |
| 13692 | CEFBS_NotInMips16Mode_IsGP64bit, // LH64 |
| 13693 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE |
| 13694 | CEFBS_InMicroMips_HasEVA, // LHE_MM |
| 13695 | CEFBS_InMicroMips, // LHU16_MM |
| 13696 | CEFBS_HasDSP, // LHX |
| 13697 | CEFBS_InMicroMips_HasDSP, // LHX_MM |
| 13698 | CEFBS_InMicroMips, // LH_MM |
| 13699 | CEFBS_HasStdEnc_NotInMicroMips, // LHu |
| 13700 | CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 |
| 13701 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE |
| 13702 | CEFBS_InMicroMips_HasEVA, // LHuE_MM |
| 13703 | CEFBS_InMicroMips, // LHu_MM |
| 13704 | CEFBS_InMicroMips_NotMips32r6, // LI16_MM |
| 13705 | CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 |
| 13706 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // LL |
| 13707 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // LL64 |
| 13708 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 |
| 13709 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // LLD |
| 13710 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 |
| 13711 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE |
| 13712 | CEFBS_InMicroMips_HasEVA, // LLE_MM |
| 13713 | CEFBS_InMicroMips_NotMips32r6, // LL_MM |
| 13714 | CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 |
| 13715 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 |
| 13716 | CEFBS_HasStdEnc_HasMSA, // LSA |
| 13717 | CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 |
| 13718 | CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 |
| 13719 | CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 |
| 13720 | CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 |
| 13721 | CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 |
| 13722 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM |
| 13723 | CEFBS_HasStdEnc_NotInMicroMips, // LUi |
| 13724 | CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 |
| 13725 | CEFBS_InMicroMips_NotMips32r6, // LUi_MM |
| 13726 | CEFBS_HasStdEnc_NotInMicroMips, // LW |
| 13727 | CEFBS_InMicroMips, // LW16_MM |
| 13728 | CEFBS_NotInMips16Mode_IsGP64bit, // LW64 |
| 13729 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 |
| 13730 | CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM |
| 13731 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 |
| 13732 | CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 |
| 13733 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 |
| 13734 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, // LWC3 |
| 13735 | CEFBS_NotInMips16Mode_HasDSP, // LWDSP |
| 13736 | CEFBS_InMicroMips_HasDSP, // LWDSP_MM |
| 13737 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE |
| 13738 | CEFBS_InMicroMips_HasEVA, // LWE_MM |
| 13739 | CEFBS_InMicroMips, // LWGP_MM |
| 13740 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL |
| 13741 | CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 |
| 13742 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE |
| 13743 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM |
| 13744 | CEFBS_InMicroMips_NotMips32r6, // LWL_MM |
| 13745 | CEFBS_InMicroMips_NotMips32r6, // LWM16_MM |
| 13746 | CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 |
| 13747 | CEFBS_InMicroMips, // LWM32_MM |
| 13748 | CEFBS_HasStdEnc_HasMips32r6, // LWPC |
| 13749 | CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 |
| 13750 | CEFBS_InMicroMips, // LWP_MM |
| 13751 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR |
| 13752 | CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 |
| 13753 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE |
| 13754 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM |
| 13755 | CEFBS_InMicroMips_NotMips32r6, // LWR_MM |
| 13756 | CEFBS_InMicroMips, // LWSP_MM |
| 13757 | CEFBS_HasStdEnc_HasMips64r6, // LWUPC |
| 13758 | CEFBS_InMicroMips_NotMips32r6, // LWU_MM |
| 13759 | CEFBS_HasDSP, // LWX |
| 13760 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 |
| 13761 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM |
| 13762 | CEFBS_InMicroMips, // LWXS_MM |
| 13763 | CEFBS_InMicroMips_HasDSP, // LWX_MM |
| 13764 | CEFBS_InMicroMips, // LW_MM |
| 13765 | CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 |
| 13766 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu |
| 13767 | CEFBS_InMips16Mode, // LbRxRyOffMemX16 |
| 13768 | CEFBS_InMips16Mode, // LbuRxRyOffMemX16 |
| 13769 | CEFBS_InMips16Mode, // LhRxRyOffMemX16 |
| 13770 | CEFBS_InMips16Mode, // LhuRxRyOffMemX16 |
| 13771 | CEFBS_InMips16Mode, // LiRxImm16 |
| 13772 | CEFBS_InMips16Mode, // LiRxImmAlignX16 |
| 13773 | CEFBS_InMips16Mode, // LiRxImmX16 |
| 13774 | CEFBS_InMips16Mode, // LwRxPcTcp16 |
| 13775 | CEFBS_InMips16Mode, // LwRxPcTcpX16 |
| 13776 | CEFBS_InMips16Mode, // LwRxRyOffMemX16 |
| 13777 | CEFBS_InMips16Mode, // LwRxSpImmX16 |
| 13778 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD |
| 13779 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D |
| 13780 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 |
| 13781 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S |
| 13782 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 |
| 13783 | CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H |
| 13784 | CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W |
| 13785 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU |
| 13786 | CEFBS_HasDSP, // MADDU_DSP |
| 13787 | CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM |
| 13788 | CEFBS_InMicroMips_NotMips32r6, // MADDU_MM |
| 13789 | CEFBS_HasStdEnc_HasMSA, // MADDV_B |
| 13790 | CEFBS_HasStdEnc_HasMSA, // MADDV_D |
| 13791 | CEFBS_HasStdEnc_HasMSA, // MADDV_H |
| 13792 | CEFBS_HasStdEnc_HasMSA, // MADDV_W |
| 13793 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 |
| 13794 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM |
| 13795 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 |
| 13796 | CEFBS_HasDSP, // MADD_DSP |
| 13797 | CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM |
| 13798 | CEFBS_InMicroMips_NotMips32r6, // MADD_MM |
| 13799 | CEFBS_HasStdEnc_HasMSA, // MADD_Q_H |
| 13800 | CEFBS_HasStdEnc_HasMSA, // MADD_Q_W |
| 13801 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S |
| 13802 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM |
| 13803 | CEFBS_HasDSP, // MAQ_SA_W_PHL |
| 13804 | CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM |
| 13805 | CEFBS_HasDSP, // MAQ_SA_W_PHR |
| 13806 | CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM |
| 13807 | CEFBS_HasDSP, // MAQ_S_W_PHL |
| 13808 | CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM |
| 13809 | CEFBS_HasDSP, // MAQ_S_W_PHR |
| 13810 | CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM |
| 13811 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D |
| 13812 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 |
| 13813 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S |
| 13814 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 |
| 13815 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_B |
| 13816 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_D |
| 13817 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_H |
| 13818 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_W |
| 13819 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_B |
| 13820 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_D |
| 13821 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_H |
| 13822 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_W |
| 13823 | CEFBS_HasStdEnc_HasMSA, // MAX_A_B |
| 13824 | CEFBS_HasStdEnc_HasMSA, // MAX_A_D |
| 13825 | CEFBS_HasStdEnc_HasMSA, // MAX_A_H |
| 13826 | CEFBS_HasStdEnc_HasMSA, // MAX_A_W |
| 13827 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D |
| 13828 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 |
| 13829 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S |
| 13830 | CEFBS_HasStdEnc_HasMSA, // MAX_S_B |
| 13831 | CEFBS_HasStdEnc_HasMSA, // MAX_S_D |
| 13832 | CEFBS_HasStdEnc_HasMSA, // MAX_S_H |
| 13833 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 |
| 13834 | CEFBS_HasStdEnc_HasMSA, // MAX_S_W |
| 13835 | CEFBS_HasStdEnc_HasMSA, // MAX_U_B |
| 13836 | CEFBS_HasStdEnc_HasMSA, // MAX_U_D |
| 13837 | CEFBS_HasStdEnc_HasMSA, // MAX_U_H |
| 13838 | CEFBS_HasStdEnc_HasMSA, // MAX_U_W |
| 13839 | CEFBS_HasStdEnc_NotInMicroMips, // MFC0 |
| 13840 | CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 |
| 13841 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 |
| 13842 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 |
| 13843 | CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM |
| 13844 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 |
| 13845 | CEFBS_HasStdEnc_NotInMicroMips, // MFC2 |
| 13846 | CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 |
| 13847 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 |
| 13848 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM |
| 13849 | CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 |
| 13850 | CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 |
| 13851 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM |
| 13852 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 |
| 13853 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM |
| 13854 | CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 |
| 13855 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 |
| 13856 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM |
| 13857 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI |
| 13858 | CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM |
| 13859 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 |
| 13860 | CEFBS_HasDSP, // MFHI_DSP |
| 13861 | CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM |
| 13862 | CEFBS_InMicroMips_NotMips32r6, // MFHI_MM |
| 13863 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO |
| 13864 | CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM |
| 13865 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 |
| 13866 | CEFBS_HasDSP, // MFLO_DSP |
| 13867 | CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM |
| 13868 | CEFBS_InMicroMips_NotMips32r6, // MFLO_MM |
| 13869 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR |
| 13870 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D |
| 13871 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 |
| 13872 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S |
| 13873 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 |
| 13874 | CEFBS_HasStdEnc_HasMSA, // MINI_S_B |
| 13875 | CEFBS_HasStdEnc_HasMSA, // MINI_S_D |
| 13876 | CEFBS_HasStdEnc_HasMSA, // MINI_S_H |
| 13877 | CEFBS_HasStdEnc_HasMSA, // MINI_S_W |
| 13878 | CEFBS_HasStdEnc_HasMSA, // MINI_U_B |
| 13879 | CEFBS_HasStdEnc_HasMSA, // MINI_U_D |
| 13880 | CEFBS_HasStdEnc_HasMSA, // MINI_U_H |
| 13881 | CEFBS_HasStdEnc_HasMSA, // MINI_U_W |
| 13882 | CEFBS_HasStdEnc_HasMSA, // MIN_A_B |
| 13883 | CEFBS_HasStdEnc_HasMSA, // MIN_A_D |
| 13884 | CEFBS_HasStdEnc_HasMSA, // MIN_A_H |
| 13885 | CEFBS_HasStdEnc_HasMSA, // MIN_A_W |
| 13886 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D |
| 13887 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 |
| 13888 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S |
| 13889 | CEFBS_HasStdEnc_HasMSA, // MIN_S_B |
| 13890 | CEFBS_HasStdEnc_HasMSA, // MIN_S_D |
| 13891 | CEFBS_HasStdEnc_HasMSA, // MIN_S_H |
| 13892 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 |
| 13893 | CEFBS_HasStdEnc_HasMSA, // MIN_S_W |
| 13894 | CEFBS_HasStdEnc_HasMSA, // MIN_U_B |
| 13895 | CEFBS_HasStdEnc_HasMSA, // MIN_U_D |
| 13896 | CEFBS_HasStdEnc_HasMSA, // MIN_U_H |
| 13897 | CEFBS_HasStdEnc_HasMSA, // MIN_U_W |
| 13898 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD |
| 13899 | CEFBS_HasDSP, // MODSUB |
| 13900 | CEFBS_InMicroMips_HasDSP, // MODSUB_MM |
| 13901 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU |
| 13902 | CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 |
| 13903 | CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 |
| 13904 | CEFBS_HasStdEnc_HasMSA, // MOD_S_B |
| 13905 | CEFBS_HasStdEnc_HasMSA, // MOD_S_D |
| 13906 | CEFBS_HasStdEnc_HasMSA, // MOD_S_H |
| 13907 | CEFBS_HasStdEnc_HasMSA, // MOD_S_W |
| 13908 | CEFBS_HasStdEnc_HasMSA, // MOD_U_B |
| 13909 | CEFBS_HasStdEnc_HasMSA, // MOD_U_D |
| 13910 | CEFBS_HasStdEnc_HasMSA, // MOD_U_H |
| 13911 | CEFBS_HasStdEnc_HasMSA, // MOD_U_W |
| 13912 | CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM |
| 13913 | CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 |
| 13914 | CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM |
| 13915 | CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 |
| 13916 | CEFBS_HasStdEnc_HasMSA, // MOVE_V |
| 13917 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 |
| 13918 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM |
| 13919 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 |
| 13920 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I |
| 13921 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 |
| 13922 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM |
| 13923 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S |
| 13924 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM |
| 13925 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 |
| 13926 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I |
| 13927 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 |
| 13928 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S |
| 13929 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 |
| 13930 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM |
| 13931 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 |
| 13932 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I |
| 13933 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 |
| 13934 | CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM |
| 13935 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S |
| 13936 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM |
| 13937 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 |
| 13938 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM |
| 13939 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 |
| 13940 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I |
| 13941 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 |
| 13942 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM |
| 13943 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S |
| 13944 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM |
| 13945 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 |
| 13946 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I |
| 13947 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 |
| 13948 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S |
| 13949 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 |
| 13950 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM |
| 13951 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 |
| 13952 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I |
| 13953 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 |
| 13954 | CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM |
| 13955 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S |
| 13956 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM |
| 13957 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB |
| 13958 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D |
| 13959 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 |
| 13960 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S |
| 13961 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 |
| 13962 | CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H |
| 13963 | CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W |
| 13964 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU |
| 13965 | CEFBS_HasDSP, // MSUBU_DSP |
| 13966 | CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM |
| 13967 | CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM |
| 13968 | CEFBS_HasStdEnc_HasMSA, // MSUBV_B |
| 13969 | CEFBS_HasStdEnc_HasMSA, // MSUBV_D |
| 13970 | CEFBS_HasStdEnc_HasMSA, // MSUBV_H |
| 13971 | CEFBS_HasStdEnc_HasMSA, // MSUBV_W |
| 13972 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 |
| 13973 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM |
| 13974 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 |
| 13975 | CEFBS_HasDSP, // MSUB_DSP |
| 13976 | CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM |
| 13977 | CEFBS_InMicroMips_NotMips32r6, // MSUB_MM |
| 13978 | CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H |
| 13979 | CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W |
| 13980 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S |
| 13981 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM |
| 13982 | CEFBS_HasStdEnc_NotInMicroMips, // MTC0 |
| 13983 | CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 |
| 13984 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 |
| 13985 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 |
| 13986 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM |
| 13987 | CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM |
| 13988 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 |
| 13989 | CEFBS_HasStdEnc_NotInMicroMips, // MTC2 |
| 13990 | CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 |
| 13991 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 |
| 13992 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM |
| 13993 | CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 |
| 13994 | CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 |
| 13995 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM |
| 13996 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 |
| 13997 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM |
| 13998 | CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 |
| 13999 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 |
| 14000 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM |
| 14001 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI |
| 14002 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 |
| 14003 | CEFBS_HasDSP, // MTHI_DSP |
| 14004 | CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM |
| 14005 | CEFBS_InMicroMips_NotMips32r6, // MTHI_MM |
| 14006 | CEFBS_HasDSP, // MTHLIP |
| 14007 | CEFBS_InMicroMips_HasDSP, // MTHLIP_MM |
| 14008 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO |
| 14009 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 |
| 14010 | CEFBS_HasDSP, // MTLO_DSP |
| 14011 | CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM |
| 14012 | CEFBS_InMicroMips_NotMips32r6, // MTLO_MM |
| 14013 | CEFBS_HasCnMips, // MTM0 |
| 14014 | CEFBS_HasCnMips, // MTM1 |
| 14015 | CEFBS_HasCnMips, // MTM2 |
| 14016 | CEFBS_HasCnMips, // MTP0 |
| 14017 | CEFBS_HasCnMips, // MTP1 |
| 14018 | CEFBS_HasCnMips, // MTP2 |
| 14019 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR |
| 14020 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH |
| 14021 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU |
| 14022 | CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 |
| 14023 | CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 |
| 14024 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL |
| 14025 | CEFBS_HasDSP, // MULEQ_S_W_PHL |
| 14026 | CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM |
| 14027 | CEFBS_HasDSP, // MULEQ_S_W_PHR |
| 14028 | CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM |
| 14029 | CEFBS_HasDSP, // MULEU_S_PH_QBL |
| 14030 | CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM |
| 14031 | CEFBS_HasDSP, // MULEU_S_PH_QBR |
| 14032 | CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM |
| 14033 | CEFBS_HasDSP, // MULQ_RS_PH |
| 14034 | CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM |
| 14035 | CEFBS_HasDSPR2, // MULQ_RS_W |
| 14036 | CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 |
| 14037 | CEFBS_HasDSPR2, // MULQ_S_PH |
| 14038 | CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 |
| 14039 | CEFBS_HasDSPR2, // MULQ_S_W |
| 14040 | CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 |
| 14041 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 |
| 14042 | CEFBS_HasStdEnc_HasMSA, // MULR_Q_H |
| 14043 | CEFBS_HasStdEnc_HasMSA, // MULR_Q_W |
| 14044 | CEFBS_HasDSP, // MULSAQ_S_W_PH |
| 14045 | CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM |
| 14046 | CEFBS_HasDSPR2, // MULSA_W_PH |
| 14047 | CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 |
| 14048 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT |
| 14049 | CEFBS_HasDSP, // MULTU_DSP |
| 14050 | CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM |
| 14051 | CEFBS_HasDSP, // MULT_DSP |
| 14052 | CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM |
| 14053 | CEFBS_InMicroMips_NotMips32r6, // MULT_MM |
| 14054 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu |
| 14055 | CEFBS_InMicroMips_NotMips32r6, // MULTu_MM |
| 14056 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU |
| 14057 | CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 |
| 14058 | CEFBS_HasStdEnc_HasMSA, // MULV_B |
| 14059 | CEFBS_HasStdEnc_HasMSA, // MULV_D |
| 14060 | CEFBS_HasStdEnc_HasMSA, // MULV_H |
| 14061 | CEFBS_HasStdEnc_HasMSA, // MULV_W |
| 14062 | CEFBS_InMicroMips_NotMips32r6, // MUL_MM |
| 14063 | CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 |
| 14064 | CEFBS_HasDSPR2, // MUL_PH |
| 14065 | CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 |
| 14066 | CEFBS_HasStdEnc_HasMSA, // MUL_Q_H |
| 14067 | CEFBS_HasStdEnc_HasMSA, // MUL_Q_W |
| 14068 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 |
| 14069 | CEFBS_HasDSPR2, // MUL_S_PH |
| 14070 | CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 |
| 14071 | CEFBS_InMips16Mode, // Mfhi16 |
| 14072 | CEFBS_InMips16Mode, // Mflo16 |
| 14073 | CEFBS_InMips16Mode, // Move32R16 |
| 14074 | CEFBS_InMips16Mode, // MoveR3216 |
| 14075 | CEFBS_HasStdEnc_HasMips32r6, // NAL |
| 14076 | CEFBS_HasStdEnc_HasMSA, // NLOC_B |
| 14077 | CEFBS_HasStdEnc_HasMSA, // NLOC_D |
| 14078 | CEFBS_HasStdEnc_HasMSA, // NLOC_H |
| 14079 | CEFBS_HasStdEnc_HasMSA, // NLOC_W |
| 14080 | CEFBS_HasStdEnc_HasMSA, // NLZC_B |
| 14081 | CEFBS_HasStdEnc_HasMSA, // NLZC_D |
| 14082 | CEFBS_HasStdEnc_HasMSA, // NLZC_H |
| 14083 | CEFBS_HasStdEnc_HasMSA, // NLZC_W |
| 14084 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 |
| 14085 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM |
| 14086 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 |
| 14087 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S |
| 14088 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM |
| 14089 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 |
| 14090 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM |
| 14091 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 |
| 14092 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S |
| 14093 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM |
| 14094 | CEFBS_HasStdEnc_NotInMicroMips, // NOR |
| 14095 | CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 |
| 14096 | CEFBS_HasStdEnc_HasMSA, // NORI_B |
| 14097 | CEFBS_InMicroMips_NotMips32r6, // NOR_MM |
| 14098 | CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 |
| 14099 | CEFBS_HasStdEnc_HasMSA, // NOR_V |
| 14100 | CEFBS_InMicroMips_NotMips32r6, // NOT16_MM |
| 14101 | CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 |
| 14102 | CEFBS_InMips16Mode, // NegRxRy16 |
| 14103 | CEFBS_InMips16Mode, // NotRxRy16 |
| 14104 | CEFBS_HasStdEnc_NotInMicroMips, // OR |
| 14105 | CEFBS_InMicroMips_NotMips32r6, // OR16_MM |
| 14106 | CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 |
| 14107 | CEFBS_NotInMips16Mode_IsGP64bit, // OR64 |
| 14108 | CEFBS_HasStdEnc_HasMSA, // ORI_B |
| 14109 | CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 |
| 14110 | CEFBS_InMicroMips_NotMips32r6, // OR_MM |
| 14111 | CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 |
| 14112 | CEFBS_HasStdEnc_HasMSA, // OR_V |
| 14113 | CEFBS_HasStdEnc_NotInMicroMips, // ORi |
| 14114 | CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 |
| 14115 | CEFBS_InMicroMips_NotMips32r6, // ORi_MM |
| 14116 | CEFBS_InMips16Mode, // OrRxRxRy16 |
| 14117 | CEFBS_HasDSP, // PACKRL_PH |
| 14118 | CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM |
| 14119 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE |
| 14120 | CEFBS_InMicroMips, // PAUSE_MM |
| 14121 | CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 |
| 14122 | CEFBS_HasStdEnc_HasMSA, // PCKEV_B |
| 14123 | CEFBS_HasStdEnc_HasMSA, // PCKEV_D |
| 14124 | CEFBS_HasStdEnc_HasMSA, // PCKEV_H |
| 14125 | CEFBS_HasStdEnc_HasMSA, // PCKEV_W |
| 14126 | CEFBS_HasStdEnc_HasMSA, // PCKOD_B |
| 14127 | CEFBS_HasStdEnc_HasMSA, // PCKOD_D |
| 14128 | CEFBS_HasStdEnc_HasMSA, // PCKOD_H |
| 14129 | CEFBS_HasStdEnc_HasMSA, // PCKOD_W |
| 14130 | CEFBS_HasStdEnc_HasMSA, // PCNT_B |
| 14131 | CEFBS_HasStdEnc_HasMSA, // PCNT_D |
| 14132 | CEFBS_HasStdEnc_HasMSA, // PCNT_H |
| 14133 | CEFBS_HasStdEnc_HasMSA, // PCNT_W |
| 14134 | CEFBS_HasDSP, // PICK_PH |
| 14135 | CEFBS_InMicroMips_HasDSP, // PICK_PH_MM |
| 14136 | CEFBS_HasDSP, // PICK_QB |
| 14137 | CEFBS_InMicroMips_HasDSP, // PICK_QB_MM |
| 14138 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 |
| 14139 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 |
| 14140 | CEFBS_HasCnMips, // POP |
| 14141 | CEFBS_HasDSP, // PRECEQU_PH_QBL |
| 14142 | CEFBS_HasDSP, // PRECEQU_PH_QBLA |
| 14143 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM |
| 14144 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM |
| 14145 | CEFBS_HasDSP, // PRECEQU_PH_QBR |
| 14146 | CEFBS_HasDSP, // PRECEQU_PH_QBRA |
| 14147 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM |
| 14148 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM |
| 14149 | CEFBS_HasDSP, // PRECEQ_W_PHL |
| 14150 | CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM |
| 14151 | CEFBS_HasDSP, // PRECEQ_W_PHR |
| 14152 | CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM |
| 14153 | CEFBS_HasDSP, // PRECEU_PH_QBL |
| 14154 | CEFBS_HasDSP, // PRECEU_PH_QBLA |
| 14155 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM |
| 14156 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM |
| 14157 | CEFBS_HasDSP, // PRECEU_PH_QBR |
| 14158 | CEFBS_HasDSP, // PRECEU_PH_QBRA |
| 14159 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM |
| 14160 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM |
| 14161 | CEFBS_HasDSP, // PRECRQU_S_QB_PH |
| 14162 | CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM |
| 14163 | CEFBS_HasDSP, // PRECRQ_PH_W |
| 14164 | CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM |
| 14165 | CEFBS_HasDSP, // PRECRQ_QB_PH |
| 14166 | CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM |
| 14167 | CEFBS_HasDSP, // PRECRQ_RS_PH_W |
| 14168 | CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM |
| 14169 | CEFBS_HasDSPR2, // PRECR_QB_PH |
| 14170 | CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 |
| 14171 | CEFBS_HasDSPR2, // PRECR_SRA_PH_W |
| 14172 | CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 |
| 14173 | CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W |
| 14174 | CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 |
| 14175 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF |
| 14176 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE |
| 14177 | CEFBS_InMicroMips_HasEVA, // PREFE_MM |
| 14178 | CEFBS_InMicroMips_NotMips32r6, // PREFX_MM |
| 14179 | CEFBS_InMicroMips_NotMips32r6, // PREF_MM |
| 14180 | CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 |
| 14181 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 |
| 14182 | CEFBS_HasDSPR2, // PREPEND |
| 14183 | CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 |
| 14184 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 |
| 14185 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 |
| 14186 | CEFBS_HasDSP, // RADDU_W_QB |
| 14187 | CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM |
| 14188 | CEFBS_HasDSP, // RDDSP |
| 14189 | CEFBS_InMicroMips_HasDSP, // RDDSP_MM |
| 14190 | CEFBS_HasStdEnc_NotInMicroMips, // RDHWR |
| 14191 | CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 |
| 14192 | CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM |
| 14193 | CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 |
| 14194 | CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 |
| 14195 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 |
| 14196 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM |
| 14197 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 |
| 14198 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM |
| 14199 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S |
| 14200 | CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM |
| 14201 | CEFBS_HasDSP, // REPLV_PH |
| 14202 | CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM |
| 14203 | CEFBS_HasDSP, // REPLV_QB |
| 14204 | CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM |
| 14205 | CEFBS_HasDSP, // REPL_PH |
| 14206 | CEFBS_InMicroMips_HasDSP, // REPL_PH_MM |
| 14207 | CEFBS_HasDSP, // REPL_QB |
| 14208 | CEFBS_InMicroMips_HasDSP, // REPL_QB_MM |
| 14209 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D |
| 14210 | CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 |
| 14211 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S |
| 14212 | CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 |
| 14213 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR |
| 14214 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV |
| 14215 | CEFBS_InMicroMips, // ROTRV_MM |
| 14216 | CEFBS_InMicroMips, // ROTR_MM |
| 14217 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 |
| 14218 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 |
| 14219 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S |
| 14220 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 |
| 14221 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 |
| 14222 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 |
| 14223 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 |
| 14224 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM |
| 14225 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S |
| 14226 | CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM |
| 14227 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 |
| 14228 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 |
| 14229 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM |
| 14230 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 |
| 14231 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM |
| 14232 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S |
| 14233 | CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM |
| 14234 | CEFBS_InMips16Mode, // Restore16 |
| 14235 | CEFBS_InMips16Mode, // RestoreX16 |
| 14236 | CEFBS_HasCnMipsP, // SAA |
| 14237 | CEFBS_HasCnMipsP, // SAAD |
| 14238 | CEFBS_HasStdEnc_HasMSA, // SAT_S_B |
| 14239 | CEFBS_HasStdEnc_HasMSA, // SAT_S_D |
| 14240 | CEFBS_HasStdEnc_HasMSA, // SAT_S_H |
| 14241 | CEFBS_HasStdEnc_HasMSA, // SAT_S_W |
| 14242 | CEFBS_HasStdEnc_HasMSA, // SAT_U_B |
| 14243 | CEFBS_HasStdEnc_HasMSA, // SAT_U_D |
| 14244 | CEFBS_HasStdEnc_HasMSA, // SAT_U_H |
| 14245 | CEFBS_HasStdEnc_HasMSA, // SAT_U_W |
| 14246 | CEFBS_HasStdEnc_NotInMicroMips, // SB |
| 14247 | CEFBS_InMicroMips_NotMips32r6, // SB16_MM |
| 14248 | CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 |
| 14249 | CEFBS_NotInMips16Mode_IsGP64bit, // SB64 |
| 14250 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE |
| 14251 | CEFBS_InMicroMips_HasEVA, // SBE_MM |
| 14252 | CEFBS_InMicroMips, // SB_MM |
| 14253 | CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 |
| 14254 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // SC |
| 14255 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, // SC64 |
| 14256 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 |
| 14257 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, // SCD |
| 14258 | CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 |
| 14259 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE |
| 14260 | CEFBS_InMicroMips_HasEVA, // SCE_MM |
| 14261 | CEFBS_InMicroMips_NotMips32r6, // SC_MM |
| 14262 | CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 |
| 14263 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 |
| 14264 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD |
| 14265 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP |
| 14266 | CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM |
| 14267 | CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 |
| 14268 | CEFBS_InMicroMips, // SDBBP_MM |
| 14269 | CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 |
| 14270 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 |
| 14271 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 |
| 14272 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 |
| 14273 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 |
| 14274 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 |
| 14275 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 |
| 14276 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 |
| 14277 | CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 |
| 14278 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 |
| 14279 | CEFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, // SDC3 |
| 14280 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV |
| 14281 | CEFBS_InMicroMips_NotMips32r6, // SDIV_MM |
| 14282 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL |
| 14283 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR |
| 14284 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 |
| 14285 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 |
| 14286 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB |
| 14287 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 |
| 14288 | CEFBS_InMicroMips, // SEB_MM |
| 14289 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH |
| 14290 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 |
| 14291 | CEFBS_InMicroMips, // SEH_MM |
| 14292 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ |
| 14293 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 |
| 14294 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D |
| 14295 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 |
| 14296 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 |
| 14297 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S |
| 14298 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 |
| 14299 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ |
| 14300 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 |
| 14301 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D |
| 14302 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 |
| 14303 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 |
| 14304 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S |
| 14305 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 |
| 14306 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D |
| 14307 | CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 |
| 14308 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S |
| 14309 | CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 |
| 14310 | CEFBS_HasCnMips, // SEQ |
| 14311 | CEFBS_HasCnMips, // SEQi |
| 14312 | CEFBS_HasStdEnc_NotInMicroMips, // SH |
| 14313 | CEFBS_InMicroMips_NotMips32r6, // SH16_MM |
| 14314 | CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 |
| 14315 | CEFBS_NotInMips16Mode_IsGP64bit, // SH64 |
| 14316 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE |
| 14317 | CEFBS_InMicroMips_HasEVA, // SHE_MM |
| 14318 | CEFBS_HasStdEnc_HasMSA, // SHF_B |
| 14319 | CEFBS_HasStdEnc_HasMSA, // SHF_H |
| 14320 | CEFBS_HasStdEnc_HasMSA, // SHF_W |
| 14321 | CEFBS_HasDSP, // SHILO |
| 14322 | CEFBS_HasDSP, // SHILOV |
| 14323 | CEFBS_InMicroMips_HasDSP, // SHILOV_MM |
| 14324 | CEFBS_InMicroMips_HasDSP, // SHILO_MM |
| 14325 | CEFBS_HasDSP, // SHLLV_PH |
| 14326 | CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM |
| 14327 | CEFBS_HasDSP, // SHLLV_QB |
| 14328 | CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM |
| 14329 | CEFBS_HasDSP, // SHLLV_S_PH |
| 14330 | CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM |
| 14331 | CEFBS_HasDSP, // SHLLV_S_W |
| 14332 | CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM |
| 14333 | CEFBS_HasDSP, // SHLL_PH |
| 14334 | CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM |
| 14335 | CEFBS_HasDSP, // SHLL_QB |
| 14336 | CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM |
| 14337 | CEFBS_HasDSP, // SHLL_S_PH |
| 14338 | CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM |
| 14339 | CEFBS_HasDSP, // SHLL_S_W |
| 14340 | CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM |
| 14341 | CEFBS_HasDSP, // SHRAV_PH |
| 14342 | CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM |
| 14343 | CEFBS_HasDSPR2, // SHRAV_QB |
| 14344 | CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 |
| 14345 | CEFBS_HasDSP, // SHRAV_R_PH |
| 14346 | CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM |
| 14347 | CEFBS_HasDSPR2, // SHRAV_R_QB |
| 14348 | CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 |
| 14349 | CEFBS_HasDSP, // SHRAV_R_W |
| 14350 | CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM |
| 14351 | CEFBS_HasDSP, // SHRA_PH |
| 14352 | CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM |
| 14353 | CEFBS_HasDSPR2, // SHRA_QB |
| 14354 | CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 |
| 14355 | CEFBS_HasDSP, // SHRA_R_PH |
| 14356 | CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM |
| 14357 | CEFBS_HasDSPR2, // SHRA_R_QB |
| 14358 | CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 |
| 14359 | CEFBS_HasDSP, // SHRA_R_W |
| 14360 | CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM |
| 14361 | CEFBS_HasDSPR2, // SHRLV_PH |
| 14362 | CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 |
| 14363 | CEFBS_HasDSP, // SHRLV_QB |
| 14364 | CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM |
| 14365 | CEFBS_HasDSPR2, // SHRL_PH |
| 14366 | CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 |
| 14367 | CEFBS_HasDSP, // SHRL_QB |
| 14368 | CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM |
| 14369 | CEFBS_InMicroMips, // SH_MM |
| 14370 | CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 |
| 14371 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE |
| 14372 | CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 |
| 14373 | CEFBS_HasStdEnc_HasMSA, // SLDI_B |
| 14374 | CEFBS_HasStdEnc_HasMSA, // SLDI_D |
| 14375 | CEFBS_HasStdEnc_HasMSA, // SLDI_H |
| 14376 | CEFBS_HasStdEnc_HasMSA, // SLDI_W |
| 14377 | CEFBS_HasStdEnc_HasMSA, // SLD_B |
| 14378 | CEFBS_HasStdEnc_HasMSA, // SLD_D |
| 14379 | CEFBS_HasStdEnc_HasMSA, // SLD_H |
| 14380 | CEFBS_HasStdEnc_HasMSA, // SLD_W |
| 14381 | CEFBS_HasStdEnc_NotInMicroMips, // SLL |
| 14382 | CEFBS_InMicroMips_NotMips32r6, // SLL16_MM |
| 14383 | CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 |
| 14384 | CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 |
| 14385 | CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 |
| 14386 | CEFBS_HasStdEnc_HasMSA, // SLLI_B |
| 14387 | CEFBS_HasStdEnc_HasMSA, // SLLI_D |
| 14388 | CEFBS_HasStdEnc_HasMSA, // SLLI_H |
| 14389 | CEFBS_HasStdEnc_HasMSA, // SLLI_W |
| 14390 | CEFBS_HasStdEnc_NotInMicroMips, // SLLV |
| 14391 | CEFBS_InMicroMips, // SLLV_MM |
| 14392 | CEFBS_HasStdEnc_HasMSA, // SLL_B |
| 14393 | CEFBS_HasStdEnc_HasMSA, // SLL_D |
| 14394 | CEFBS_HasStdEnc_HasMSA, // SLL_H |
| 14395 | CEFBS_InMicroMips, // SLL_MM |
| 14396 | CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 |
| 14397 | CEFBS_HasStdEnc_HasMSA, // SLL_W |
| 14398 | CEFBS_HasStdEnc_NotInMicroMips, // SLT |
| 14399 | CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 |
| 14400 | CEFBS_InMicroMips, // SLT_MM |
| 14401 | CEFBS_HasStdEnc_NotInMicroMips, // SLTi |
| 14402 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 |
| 14403 | CEFBS_InMicroMips, // SLTi_MM |
| 14404 | CEFBS_HasStdEnc_NotInMicroMips, // SLTiu |
| 14405 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 |
| 14406 | CEFBS_InMicroMips, // SLTiu_MM |
| 14407 | CEFBS_HasStdEnc_NotInMicroMips, // SLTu |
| 14408 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 |
| 14409 | CEFBS_InMicroMips, // SLTu_MM |
| 14410 | CEFBS_HasCnMips, // SNE |
| 14411 | CEFBS_HasCnMips, // SNEi |
| 14412 | CEFBS_HasStdEnc_HasMSA, // SPLATI_B |
| 14413 | CEFBS_HasStdEnc_HasMSA, // SPLATI_D |
| 14414 | CEFBS_HasStdEnc_HasMSA, // SPLATI_H |
| 14415 | CEFBS_HasStdEnc_HasMSA, // SPLATI_W |
| 14416 | CEFBS_HasStdEnc_HasMSA, // SPLAT_B |
| 14417 | CEFBS_HasStdEnc_HasMSA, // SPLAT_D |
| 14418 | CEFBS_HasStdEnc_HasMSA, // SPLAT_H |
| 14419 | CEFBS_HasStdEnc_HasMSA, // SPLAT_W |
| 14420 | CEFBS_HasStdEnc_NotInMicroMips, // SRA |
| 14421 | CEFBS_HasStdEnc_HasMSA, // SRAI_B |
| 14422 | CEFBS_HasStdEnc_HasMSA, // SRAI_D |
| 14423 | CEFBS_HasStdEnc_HasMSA, // SRAI_H |
| 14424 | CEFBS_HasStdEnc_HasMSA, // SRAI_W |
| 14425 | CEFBS_HasStdEnc_HasMSA, // SRARI_B |
| 14426 | CEFBS_HasStdEnc_HasMSA, // SRARI_D |
| 14427 | CEFBS_HasStdEnc_HasMSA, // SRARI_H |
| 14428 | CEFBS_HasStdEnc_HasMSA, // SRARI_W |
| 14429 | CEFBS_HasStdEnc_HasMSA, // SRAR_B |
| 14430 | CEFBS_HasStdEnc_HasMSA, // SRAR_D |
| 14431 | CEFBS_HasStdEnc_HasMSA, // SRAR_H |
| 14432 | CEFBS_HasStdEnc_HasMSA, // SRAR_W |
| 14433 | CEFBS_HasStdEnc_NotInMicroMips, // SRAV |
| 14434 | CEFBS_InMicroMips, // SRAV_MM |
| 14435 | CEFBS_HasStdEnc_HasMSA, // SRA_B |
| 14436 | CEFBS_HasStdEnc_HasMSA, // SRA_D |
| 14437 | CEFBS_HasStdEnc_HasMSA, // SRA_H |
| 14438 | CEFBS_InMicroMips, // SRA_MM |
| 14439 | CEFBS_HasStdEnc_HasMSA, // SRA_W |
| 14440 | CEFBS_HasStdEnc_NotInMicroMips, // SRL |
| 14441 | CEFBS_InMicroMips_NotMips32r6, // SRL16_MM |
| 14442 | CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 |
| 14443 | CEFBS_HasStdEnc_HasMSA, // SRLI_B |
| 14444 | CEFBS_HasStdEnc_HasMSA, // SRLI_D |
| 14445 | CEFBS_HasStdEnc_HasMSA, // SRLI_H |
| 14446 | CEFBS_HasStdEnc_HasMSA, // SRLI_W |
| 14447 | CEFBS_HasStdEnc_HasMSA, // SRLRI_B |
| 14448 | CEFBS_HasStdEnc_HasMSA, // SRLRI_D |
| 14449 | CEFBS_HasStdEnc_HasMSA, // SRLRI_H |
| 14450 | CEFBS_HasStdEnc_HasMSA, // SRLRI_W |
| 14451 | CEFBS_HasStdEnc_HasMSA, // SRLR_B |
| 14452 | CEFBS_HasStdEnc_HasMSA, // SRLR_D |
| 14453 | CEFBS_HasStdEnc_HasMSA, // SRLR_H |
| 14454 | CEFBS_HasStdEnc_HasMSA, // SRLR_W |
| 14455 | CEFBS_HasStdEnc_NotInMicroMips, // SRLV |
| 14456 | CEFBS_InMicroMips, // SRLV_MM |
| 14457 | CEFBS_HasStdEnc_HasMSA, // SRL_B |
| 14458 | CEFBS_HasStdEnc_HasMSA, // SRL_D |
| 14459 | CEFBS_HasStdEnc_HasMSA, // SRL_H |
| 14460 | CEFBS_InMicroMips, // SRL_MM |
| 14461 | CEFBS_HasStdEnc_HasMSA, // SRL_W |
| 14462 | CEFBS_HasStdEnc_NotInMicroMips, // SSNOP |
| 14463 | CEFBS_InMicroMips, // SSNOP_MM |
| 14464 | CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 |
| 14465 | CEFBS_HasStdEnc_HasMSA, // ST_B |
| 14466 | CEFBS_HasStdEnc_HasMSA, // ST_D |
| 14467 | CEFBS_HasStdEnc_HasMSA, // ST_H |
| 14468 | CEFBS_HasStdEnc_HasMSA, // ST_W |
| 14469 | CEFBS_HasStdEnc_NotInMicroMips, // SUB |
| 14470 | CEFBS_HasDSPR2, // SUBQH_PH |
| 14471 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 |
| 14472 | CEFBS_HasDSPR2, // SUBQH_R_PH |
| 14473 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 |
| 14474 | CEFBS_HasDSPR2, // SUBQH_R_W |
| 14475 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 |
| 14476 | CEFBS_HasDSPR2, // SUBQH_W |
| 14477 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 |
| 14478 | CEFBS_HasDSP, // SUBQ_PH |
| 14479 | CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM |
| 14480 | CEFBS_HasDSP, // SUBQ_S_PH |
| 14481 | CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM |
| 14482 | CEFBS_HasDSP, // SUBQ_S_W |
| 14483 | CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM |
| 14484 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B |
| 14485 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D |
| 14486 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H |
| 14487 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W |
| 14488 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B |
| 14489 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D |
| 14490 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H |
| 14491 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W |
| 14492 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_B |
| 14493 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_D |
| 14494 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_H |
| 14495 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_W |
| 14496 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_B |
| 14497 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_D |
| 14498 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_H |
| 14499 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_W |
| 14500 | CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM |
| 14501 | CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 |
| 14502 | CEFBS_HasDSPR2, // SUBUH_QB |
| 14503 | CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 |
| 14504 | CEFBS_HasDSPR2, // SUBUH_R_QB |
| 14505 | CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 |
| 14506 | CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 |
| 14507 | CEFBS_HasDSPR2, // SUBU_PH |
| 14508 | CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 |
| 14509 | CEFBS_HasDSP, // SUBU_QB |
| 14510 | CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM |
| 14511 | CEFBS_HasDSPR2, // SUBU_S_PH |
| 14512 | CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 |
| 14513 | CEFBS_HasDSP, // SUBU_S_QB |
| 14514 | CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM |
| 14515 | CEFBS_HasStdEnc_HasMSA, // SUBVI_B |
| 14516 | CEFBS_HasStdEnc_HasMSA, // SUBVI_D |
| 14517 | CEFBS_HasStdEnc_HasMSA, // SUBVI_H |
| 14518 | CEFBS_HasStdEnc_HasMSA, // SUBVI_W |
| 14519 | CEFBS_HasStdEnc_HasMSA, // SUBV_B |
| 14520 | CEFBS_HasStdEnc_HasMSA, // SUBV_D |
| 14521 | CEFBS_HasStdEnc_HasMSA, // SUBV_H |
| 14522 | CEFBS_HasStdEnc_HasMSA, // SUBV_W |
| 14523 | CEFBS_InMicroMips_NotMips32r6, // SUB_MM |
| 14524 | CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 |
| 14525 | CEFBS_HasStdEnc_NotInMicroMips, // SUBu |
| 14526 | CEFBS_InMicroMips_NotMips32r6, // SUBu_MM |
| 14527 | CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 |
| 14528 | CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 |
| 14529 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM |
| 14530 | CEFBS_HasStdEnc_NotInMicroMips, // SW |
| 14531 | CEFBS_InMicroMips_NotMips32r6, // SW16_MM |
| 14532 | CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 |
| 14533 | CEFBS_NotInMips16Mode_IsGP64bit, // SW64 |
| 14534 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 |
| 14535 | CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM |
| 14536 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 |
| 14537 | CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 |
| 14538 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 |
| 14539 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, // SWC3 |
| 14540 | CEFBS_NotInMips16Mode_HasDSP, // SWDSP |
| 14541 | CEFBS_InMicroMips_HasDSP, // SWDSP_MM |
| 14542 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE |
| 14543 | CEFBS_InMicroMips_HasEVA, // SWE_MM |
| 14544 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL |
| 14545 | CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 |
| 14546 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE |
| 14547 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM |
| 14548 | CEFBS_InMicroMips_NotMips32r6, // SWL_MM |
| 14549 | CEFBS_InMicroMips_NotMips32r6, // SWM16_MM |
| 14550 | CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 |
| 14551 | CEFBS_InMicroMips, // SWM32_MM |
| 14552 | CEFBS_InMicroMips, // SWP_MM |
| 14553 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR |
| 14554 | CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 |
| 14555 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE |
| 14556 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM |
| 14557 | CEFBS_InMicroMips_NotMips32r6, // SWR_MM |
| 14558 | CEFBS_InMicroMips_NotMips32r6, // SWSP_MM |
| 14559 | CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 |
| 14560 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 |
| 14561 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM |
| 14562 | CEFBS_InMicroMips, // SW_MM |
| 14563 | CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 |
| 14564 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC |
| 14565 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI |
| 14566 | CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM |
| 14567 | CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 |
| 14568 | CEFBS_InMicroMips, // SYNC_MM |
| 14569 | CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 |
| 14570 | CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL |
| 14571 | CEFBS_InMicroMips, // SYSCALL_MM |
| 14572 | CEFBS_InMips16Mode, // Save16 |
| 14573 | CEFBS_InMips16Mode, // SaveX16 |
| 14574 | CEFBS_InMips16Mode, // SbRxRyOffMemX16 |
| 14575 | CEFBS_InMips16Mode, // SebRx16 |
| 14576 | CEFBS_InMips16Mode, // SehRx16 |
| 14577 | CEFBS_InMips16Mode, // ShRxRyOffMemX16 |
| 14578 | CEFBS_InMips16Mode, // SllX16 |
| 14579 | CEFBS_InMips16Mode, // SllvRxRy16 |
| 14580 | CEFBS_InMips16Mode, // SltRxRy16 |
| 14581 | CEFBS_InMips16Mode, // SltiRxImm16 |
| 14582 | CEFBS_InMips16Mode, // SltiRxImmX16 |
| 14583 | CEFBS_InMips16Mode, // SltiuRxImm16 |
| 14584 | CEFBS_InMips16Mode, // SltiuRxImmX16 |
| 14585 | CEFBS_InMips16Mode, // SltuRxRy16 |
| 14586 | CEFBS_InMips16Mode, // SraX16 |
| 14587 | CEFBS_InMips16Mode, // SravRxRy16 |
| 14588 | CEFBS_InMips16Mode, // SrlX16 |
| 14589 | CEFBS_InMips16Mode, // SrlvRxRy16 |
| 14590 | CEFBS_InMips16Mode, // SubuRxRyRz16 |
| 14591 | CEFBS_InMips16Mode, // SwRxRyOffMemX16 |
| 14592 | CEFBS_InMips16Mode, // SwRxSpImmX16 |
| 14593 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ |
| 14594 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI |
| 14595 | CEFBS_InMicroMips_NotMips32r6, // TEQI_MM |
| 14596 | CEFBS_InMicroMips, // TEQ_MM |
| 14597 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE |
| 14598 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI |
| 14599 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU |
| 14600 | CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM |
| 14601 | CEFBS_InMicroMips_NotMips32r6, // TGEI_MM |
| 14602 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU |
| 14603 | CEFBS_InMicroMips, // TGEU_MM |
| 14604 | CEFBS_InMicroMips, // TGE_MM |
| 14605 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV |
| 14606 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF |
| 14607 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM |
| 14608 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM |
| 14609 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP |
| 14610 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM |
| 14611 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR |
| 14612 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM |
| 14613 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI |
| 14614 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM |
| 14615 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR |
| 14616 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM |
| 14617 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV |
| 14618 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF |
| 14619 | CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 |
| 14620 | CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 |
| 14621 | CEFBS_HasStdEnc_NotInMicroMips, // TLBP |
| 14622 | CEFBS_InMicroMips, // TLBP_MM |
| 14623 | CEFBS_HasStdEnc_NotInMicroMips, // TLBR |
| 14624 | CEFBS_InMicroMips, // TLBR_MM |
| 14625 | CEFBS_HasStdEnc_NotInMicroMips, // TLBWI |
| 14626 | CEFBS_InMicroMips, // TLBWI_MM |
| 14627 | CEFBS_HasStdEnc_NotInMicroMips, // TLBWR |
| 14628 | CEFBS_InMicroMips, // TLBWR_MM |
| 14629 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT |
| 14630 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI |
| 14631 | CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM |
| 14632 | CEFBS_InMicroMips_NotMips32r6, // TLTI_MM |
| 14633 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU |
| 14634 | CEFBS_InMicroMips, // TLTU_MM |
| 14635 | CEFBS_InMicroMips, // TLT_MM |
| 14636 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE |
| 14637 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI |
| 14638 | CEFBS_InMicroMips_NotMips32r6, // TNEI_MM |
| 14639 | CEFBS_InMicroMips, // TNE_MM |
| 14640 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 |
| 14641 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 |
| 14642 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S |
| 14643 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 |
| 14644 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 |
| 14645 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 |
| 14646 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 |
| 14647 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM |
| 14648 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S |
| 14649 | CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM |
| 14650 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 |
| 14651 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU |
| 14652 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV |
| 14653 | CEFBS_InMicroMips_NotMips32r6, // UDIV_MM |
| 14654 | CEFBS_HasCnMips, // V3MULU |
| 14655 | CEFBS_HasCnMips, // VMM0 |
| 14656 | CEFBS_HasCnMips, // VMULU |
| 14657 | CEFBS_HasStdEnc_HasMSA, // VSHF_B |
| 14658 | CEFBS_HasStdEnc_HasMSA, // VSHF_D |
| 14659 | CEFBS_HasStdEnc_HasMSA, // VSHF_H |
| 14660 | CEFBS_HasStdEnc_HasMSA, // VSHF_W |
| 14661 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT |
| 14662 | CEFBS_InMicroMips, // WAIT_MM |
| 14663 | CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 |
| 14664 | CEFBS_HasDSP_NotInMicroMips, // WRDSP |
| 14665 | CEFBS_InMicroMips_HasDSP, // WRDSP_MM |
| 14666 | CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 |
| 14667 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH |
| 14668 | CEFBS_InMicroMips, // WSBH_MM |
| 14669 | CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 |
| 14670 | CEFBS_HasStdEnc_NotInMicroMips, // XOR |
| 14671 | CEFBS_InMicroMips_NotMips32r6, // XOR16_MM |
| 14672 | CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 |
| 14673 | CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 |
| 14674 | CEFBS_HasStdEnc_HasMSA, // XORI_B |
| 14675 | CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 |
| 14676 | CEFBS_InMicroMips_NotMips32r6, // XOR_MM |
| 14677 | CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 |
| 14678 | CEFBS_HasStdEnc_HasMSA, // XOR_V |
| 14679 | CEFBS_HasStdEnc_NotInMicroMips, // XORi |
| 14680 | CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 |
| 14681 | CEFBS_InMicroMips_NotMips32r6, // XORi_MM |
| 14682 | CEFBS_InMips16Mode, // XorRxRxRy16 |
| 14683 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD |
| 14684 | }; |
| 14685 | |
| 14686 | assert(Opcode < 2921); |
| 14687 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| 14688 | } |
| 14689 | |
| 14690 | |
| 14691 | } // namespace llvm::Mips_MC |
| 14692 | |
| 14693 | #endif // GET_COMPUTE_FEATURES |
| 14694 | |
| 14695 | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
| 14696 | #undef GET_AVAILABLE_OPCODE_CHECKER |
| 14697 | |
| 14698 | namespace llvm::Mips_MC { |
| 14699 | |
| 14700 | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
| 14701 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 14702 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 14703 | FeatureBitset MissingFeatures = |
| 14704 | (AvailableFeatures & RequiredFeatures) ^ |
| 14705 | RequiredFeatures; |
| 14706 | return !MissingFeatures.any(); |
| 14707 | } |
| 14708 | |
| 14709 | } // namespace llvm::Mips_MC |
| 14710 | |
| 14711 | #endif // GET_AVAILABLE_OPCODE_CHECKER |
| 14712 | |
| 14713 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 14714 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 14715 | |
| 14716 | #include <sstream> |
| 14717 | |
| 14718 | namespace llvm::Mips_MC { |
| 14719 | |
| 14720 | #ifndef NDEBUG |
| 14721 | static const char *SubtargetFeatureNames[] = { |
| 14722 | "Feature_HasCRC", |
| 14723 | "Feature_HasCnMips", |
| 14724 | "Feature_HasCnMipsP", |
| 14725 | "Feature_HasDSP", |
| 14726 | "Feature_HasDSPR2", |
| 14727 | "Feature_HasDSPR3", |
| 14728 | "Feature_HasEVA", |
| 14729 | "Feature_HasGINV", |
| 14730 | "Feature_HasMSA", |
| 14731 | "Feature_HasMT", |
| 14732 | "Feature_HasMadd4", |
| 14733 | "Feature_HasMips2", |
| 14734 | "Feature_HasMips3", |
| 14735 | "Feature_HasMips3D", |
| 14736 | "Feature_HasMips3_32", |
| 14737 | "Feature_HasMips3_32r2", |
| 14738 | "Feature_HasMips4_32", |
| 14739 | "Feature_HasMips4_32r2", |
| 14740 | "Feature_HasMips5_32r2", |
| 14741 | "Feature_HasMips32", |
| 14742 | "Feature_HasMips32r2", |
| 14743 | "Feature_HasMips32r5", |
| 14744 | "Feature_HasMips32r6", |
| 14745 | "Feature_HasMips64", |
| 14746 | "Feature_HasMips64r2", |
| 14747 | "Feature_HasMips64r5", |
| 14748 | "Feature_HasMips64r6", |
| 14749 | "Feature_HasR5900", |
| 14750 | "Feature_HasStdEnc", |
| 14751 | "Feature_HasVirt", |
| 14752 | "Feature_InMicroMips", |
| 14753 | "Feature_InMips16Mode", |
| 14754 | "Feature_IsFP64bit", |
| 14755 | "Feature_IsGP32bit", |
| 14756 | "Feature_IsGP64bit", |
| 14757 | "Feature_IsNotSingleFloat", |
| 14758 | "Feature_IsNotSoftFloat", |
| 14759 | "Feature_IsPTR32bit", |
| 14760 | "Feature_IsPTR64bit", |
| 14761 | "Feature_IsSingleFloat", |
| 14762 | "Feature_IsSym32", |
| 14763 | "Feature_IsSym64", |
| 14764 | "Feature_NoIndirectJumpGuards", |
| 14765 | "Feature_NotCnMips", |
| 14766 | "Feature_NotCnMipsP", |
| 14767 | "Feature_NotFP64bit", |
| 14768 | "Feature_NotInMicroMips", |
| 14769 | "Feature_NotInMips16Mode", |
| 14770 | "Feature_NotMips3", |
| 14771 | "Feature_NotMips4_32", |
| 14772 | "Feature_NotMips32r6", |
| 14773 | "Feature_NotMips64", |
| 14774 | "Feature_NotMips64r6", |
| 14775 | "Feature_NotR5900", |
| 14776 | "Feature_UseCompactBranches", |
| 14777 | "Feature_UseIndirectJumpsHazard", |
| 14778 | nullptr |
| 14779 | }; |
| 14780 | |
| 14781 | #endif // NDEBUG |
| 14782 | |
| 14783 | void verifyInstructionPredicates( |
| 14784 | unsigned Opcode, const FeatureBitset &Features) { |
| 14785 | #ifndef NDEBUG |
| 14786 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 14787 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 14788 | FeatureBitset MissingFeatures = |
| 14789 | (AvailableFeatures & RequiredFeatures) ^ |
| 14790 | RequiredFeatures; |
| 14791 | if (MissingFeatures.any()) { |
| 14792 | std::ostringstream Msg; |
| 14793 | Msg << "Attempting to emit "<< &MipsInstrNameData[MipsInstrNameIndices[Opcode]] |
| 14794 | << " instruction but the "; |
| 14795 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 14796 | if (MissingFeatures.test(i)) |
| 14797 | Msg << SubtargetFeatureNames[i] << " "; |
| 14798 | Msg << "predicate(s) are not met"; |
| 14799 | report_fatal_error(Msg.str().c_str()); |
| 14800 | } |
| 14801 | #endif // NDEBUG |
| 14802 | } |
| 14803 | |
| 14804 | } // namespace llvm::Mips_MC |
| 14805 | |
| 14806 | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| 14807 | |
| 14808 | #ifdef GET_INSTRMAP_INFO |
| 14809 | #undef GET_INSTRMAP_INFO |
| 14810 | |
| 14811 | namespace llvm::Mips { |
| 14812 | |
| 14813 | enum Arch { |
| 14814 | Arch_dsp, |
| 14815 | Arch_mmdsp, |
| 14816 | Arch_mipsr6, |
| 14817 | Arch_micromipsr6, |
| 14818 | Arch_se, |
| 14819 | Arch_micromips |
| 14820 | }; |
| 14821 | |
| 14822 | // Dsp2MicroMips |
| 14823 | LLVM_READONLY |
| 14824 | int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) { |
| 14825 | using namespace Mips; |
| 14826 | static constexpr uint16_t Table[][3] = { |
| 14827 | { ABSQ_S_PH, ABSQ_S_PH, ABSQ_S_PH_MM }, |
| 14828 | { ABSQ_S_QB, ABSQ_S_QB, ABSQ_S_QB_MMR2 }, |
| 14829 | { ABSQ_S_W, ABSQ_S_W, ABSQ_S_W_MM }, |
| 14830 | { ADDQH_PH, ADDQH_PH, ADDQH_PH_MMR2 }, |
| 14831 | { ADDQH_R_PH, ADDQH_R_PH, ADDQH_R_PH_MMR2 }, |
| 14832 | { ADDQH_R_W, ADDQH_R_W, ADDQH_R_W_MMR2 }, |
| 14833 | { ADDQH_W, ADDQH_W, ADDQH_W_MMR2 }, |
| 14834 | { ADDQ_PH, ADDQ_PH, ADDQ_PH_MM }, |
| 14835 | { ADDQ_S_PH, ADDQ_S_PH, ADDQ_S_PH_MM }, |
| 14836 | { ADDQ_S_W, ADDQ_S_W, ADDQ_S_W_MM }, |
| 14837 | { ADDSC, ADDSC, ADDSC_MM }, |
| 14838 | { ADDUH_QB, ADDUH_QB, ADDUH_QB_MMR2 }, |
| 14839 | { ADDUH_R_QB, ADDUH_R_QB, ADDUH_R_QB_MMR2 }, |
| 14840 | { ADDU_PH, ADDU_PH, ADDU_PH_MMR2 }, |
| 14841 | { ADDU_QB, ADDU_QB, ADDU_QB_MM }, |
| 14842 | { ADDU_S_PH, ADDU_S_PH, ADDU_S_PH_MMR2 }, |
| 14843 | { ADDU_S_QB, ADDU_S_QB, ADDU_S_QB_MM }, |
| 14844 | { ADDWC, ADDWC, ADDWC_MM }, |
| 14845 | { APPEND, APPEND, APPEND_MMR2 }, |
| 14846 | { BALIGN, BALIGN, BALIGN_MMR2 }, |
| 14847 | { BITREV, BITREV, BITREV_MM }, |
| 14848 | { BPOSGE32, BPOSGE32, BPOSGE32_MM }, |
| 14849 | { CMPGDU_EQ_QB, CMPGDU_EQ_QB, CMPGDU_EQ_QB_MMR2 }, |
| 14850 | { CMPGDU_LE_QB, CMPGDU_LE_QB, CMPGDU_LE_QB_MMR2 }, |
| 14851 | { CMPGDU_LT_QB, CMPGDU_LT_QB, CMPGDU_LT_QB_MMR2 }, |
| 14852 | { CMPGU_EQ_QB, CMPGU_EQ_QB, CMPGU_EQ_QB_MM }, |
| 14853 | { CMPGU_LE_QB, CMPGU_LE_QB, CMPGU_LE_QB_MM }, |
| 14854 | { CMPGU_LT_QB, CMPGU_LT_QB, CMPGU_LT_QB_MM }, |
| 14855 | { CMPU_EQ_QB, CMPU_EQ_QB, CMPU_EQ_QB_MM }, |
| 14856 | { CMPU_LE_QB, CMPU_LE_QB, CMPU_LE_QB_MM }, |
| 14857 | { CMPU_LT_QB, CMPU_LT_QB, CMPU_LT_QB_MM }, |
| 14858 | { CMP_EQ_PH, CMP_EQ_PH, CMP_EQ_PH_MM }, |
| 14859 | { CMP_LE_PH, CMP_LE_PH, CMP_LE_PH_MM }, |
| 14860 | { CMP_LT_PH, CMP_LT_PH, CMP_LT_PH_MM }, |
| 14861 | { DPAQX_SA_W_PH, DPAQX_SA_W_PH, DPAQX_SA_W_PH_MMR2 }, |
| 14862 | { DPAQX_S_W_PH, DPAQX_S_W_PH, DPAQX_S_W_PH_MMR2 }, |
| 14863 | { DPAQ_SA_L_W, DPAQ_SA_L_W, DPAQ_SA_L_W_MM }, |
| 14864 | { DPAQ_S_W_PH, DPAQ_S_W_PH, DPAQ_S_W_PH_MM }, |
| 14865 | { DPAU_H_QBL, DPAU_H_QBL, DPAU_H_QBL_MM }, |
| 14866 | { DPAU_H_QBR, DPAU_H_QBR, DPAU_H_QBR_MM }, |
| 14867 | { DPAX_W_PH, DPAX_W_PH, DPAX_W_PH_MMR2 }, |
| 14868 | { DPA_W_PH, DPA_W_PH, DPA_W_PH_MMR2 }, |
| 14869 | { DPSQX_SA_W_PH, DPSQX_SA_W_PH, DPSQX_SA_W_PH_MMR2 }, |
| 14870 | { DPSQX_S_W_PH, DPSQX_S_W_PH, DPSQX_S_W_PH_MMR2 }, |
| 14871 | { DPSQ_SA_L_W, DPSQ_SA_L_W, DPSQ_SA_L_W_MM }, |
| 14872 | { DPSQ_S_W_PH, DPSQ_S_W_PH, DPSQ_S_W_PH_MM }, |
| 14873 | { DPSU_H_QBL, DPSU_H_QBL, DPSU_H_QBL_MM }, |
| 14874 | { DPSU_H_QBR, DPSU_H_QBR, DPSU_H_QBR_MM }, |
| 14875 | { DPSX_W_PH, DPSX_W_PH, DPSX_W_PH_MMR2 }, |
| 14876 | { DPS_W_PH, DPS_W_PH, DPS_W_PH_MMR2 }, |
| 14877 | { EXTP, EXTP, EXTP_MM }, |
| 14878 | { EXTPDP, EXTPDP, EXTPDP_MM }, |
| 14879 | { EXTPDPV, EXTPDPV, EXTPDPV_MM }, |
| 14880 | { EXTPV, EXTPV, EXTPV_MM }, |
| 14881 | { EXTRV_RS_W, EXTRV_RS_W, EXTRV_RS_W_MM }, |
| 14882 | { EXTRV_R_W, EXTRV_R_W, EXTRV_R_W_MM }, |
| 14883 | { EXTRV_S_H, EXTRV_S_H, EXTRV_S_H_MM }, |
| 14884 | { EXTRV_W, EXTRV_W, EXTRV_W_MM }, |
| 14885 | { EXTR_RS_W, EXTR_RS_W, EXTR_RS_W_MM }, |
| 14886 | { EXTR_R_W, EXTR_R_W, EXTR_R_W_MM }, |
| 14887 | { EXTR_S_H, EXTR_S_H, EXTR_S_H_MM }, |
| 14888 | { EXTR_W, EXTR_W, EXTR_W_MM }, |
| 14889 | { INSV, INSV, INSV_MM }, |
| 14890 | { LBUX, LBUX, LBUX_MM }, |
| 14891 | { LHX, LHX, LHX_MM }, |
| 14892 | { LWDSP, LWDSP, LWDSP_MM }, |
| 14893 | { LWX, LWX, LWX_MM }, |
| 14894 | { MADDU_DSP, MADDU_DSP, MADDU_DSP_MM }, |
| 14895 | { MADD_DSP, MADD_DSP, MADD_DSP_MM }, |
| 14896 | { MAQ_SA_W_PHL, MAQ_SA_W_PHL, MAQ_SA_W_PHL_MM }, |
| 14897 | { MAQ_SA_W_PHR, MAQ_SA_W_PHR, MAQ_SA_W_PHR_MM }, |
| 14898 | { MAQ_S_W_PHL, MAQ_S_W_PHL, MAQ_S_W_PHL_MM }, |
| 14899 | { MAQ_S_W_PHR, MAQ_S_W_PHR, MAQ_S_W_PHR_MM }, |
| 14900 | { MFHI_DSP, MFHI_DSP, MFHI_DSP_MM }, |
| 14901 | { MFLO_DSP, MFLO_DSP, MFLO_DSP_MM }, |
| 14902 | { MODSUB, MODSUB, MODSUB_MM }, |
| 14903 | { MSUBU_DSP, MSUBU_DSP, MSUBU_DSP_MM }, |
| 14904 | { MSUB_DSP, MSUB_DSP, MSUB_DSP_MM }, |
| 14905 | { MTHI_DSP, MTHI_DSP, MTHI_DSP_MM }, |
| 14906 | { MTHLIP, MTHLIP, MTHLIP_MM }, |
| 14907 | { MTLO_DSP, MTLO_DSP, MTLO_DSP_MM }, |
| 14908 | { MULEQ_S_W_PHL, MULEQ_S_W_PHL, MULEQ_S_W_PHL_MM }, |
| 14909 | { MULEQ_S_W_PHR, MULEQ_S_W_PHR, MULEQ_S_W_PHR_MM }, |
| 14910 | { MULEU_S_PH_QBL, MULEU_S_PH_QBL, MULEU_S_PH_QBL_MM }, |
| 14911 | { MULEU_S_PH_QBR, MULEU_S_PH_QBR, MULEU_S_PH_QBR_MM }, |
| 14912 | { MULQ_RS_PH, MULQ_RS_PH, MULQ_RS_PH_MM }, |
| 14913 | { MULQ_RS_W, MULQ_RS_W, MULQ_RS_W_MMR2 }, |
| 14914 | { MULQ_S_PH, MULQ_S_PH, MULQ_S_PH_MMR2 }, |
| 14915 | { MULQ_S_W, MULQ_S_W, MULQ_S_W_MMR2 }, |
| 14916 | { MULSAQ_S_W_PH, MULSAQ_S_W_PH, MULSAQ_S_W_PH_MM }, |
| 14917 | { MULSA_W_PH, MULSA_W_PH, MULSA_W_PH_MMR2 }, |
| 14918 | { MULTU_DSP, MULTU_DSP, MULTU_DSP_MM }, |
| 14919 | { MULT_DSP, MULT_DSP, MULT_DSP_MM }, |
| 14920 | { MUL_PH, MUL_PH, MUL_PH_MMR2 }, |
| 14921 | { MUL_S_PH, MUL_S_PH, MUL_S_PH_MMR2 }, |
| 14922 | { PACKRL_PH, PACKRL_PH, PACKRL_PH_MM }, |
| 14923 | { PICK_PH, PICK_PH, PICK_PH_MM }, |
| 14924 | { PICK_QB, PICK_QB, PICK_QB_MM }, |
| 14925 | { PRECEQU_PH_QBL, PRECEQU_PH_QBL, PRECEQU_PH_QBL_MM }, |
| 14926 | { PRECEQU_PH_QBLA, PRECEQU_PH_QBLA, PRECEQU_PH_QBLA_MM }, |
| 14927 | { PRECEQU_PH_QBR, PRECEQU_PH_QBR, PRECEQU_PH_QBR_MM }, |
| 14928 | { PRECEQU_PH_QBRA, PRECEQU_PH_QBRA, PRECEQU_PH_QBRA_MM }, |
| 14929 | { PRECEQ_W_PHL, PRECEQ_W_PHL, PRECEQ_W_PHL_MM }, |
| 14930 | { PRECEQ_W_PHR, PRECEQ_W_PHR, PRECEQ_W_PHR_MM }, |
| 14931 | { PRECEU_PH_QBL, PRECEU_PH_QBL, PRECEU_PH_QBL_MM }, |
| 14932 | { PRECEU_PH_QBLA, PRECEU_PH_QBLA, PRECEU_PH_QBLA_MM }, |
| 14933 | { PRECEU_PH_QBR, PRECEU_PH_QBR, PRECEU_PH_QBR_MM }, |
| 14934 | { PRECEU_PH_QBRA, PRECEU_PH_QBRA, PRECEU_PH_QBRA_MM }, |
| 14935 | { PRECRQU_S_QB_PH, PRECRQU_S_QB_PH, PRECRQU_S_QB_PH_MM }, |
| 14936 | { PRECRQ_PH_W, PRECRQ_PH_W, PRECRQ_PH_W_MM }, |
| 14937 | { PRECRQ_QB_PH, PRECRQ_QB_PH, PRECRQ_QB_PH_MM }, |
| 14938 | { PRECRQ_RS_PH_W, PRECRQ_RS_PH_W, PRECRQ_RS_PH_W_MM }, |
| 14939 | { PRECR_QB_PH, PRECR_QB_PH, PRECR_QB_PH_MMR2 }, |
| 14940 | { PRECR_SRA_PH_W, PRECR_SRA_PH_W, PRECR_SRA_PH_W_MMR2 }, |
| 14941 | { PRECR_SRA_R_PH_W, PRECR_SRA_R_PH_W, PRECR_SRA_R_PH_W_MMR2 }, |
| 14942 | { PREPEND, PREPEND, PREPEND_MMR2 }, |
| 14943 | { RADDU_W_QB, RADDU_W_QB, RADDU_W_QB_MM }, |
| 14944 | { RDDSP, RDDSP, RDDSP_MM }, |
| 14945 | { REPLV_PH, REPLV_PH, REPLV_PH_MM }, |
| 14946 | { REPLV_QB, REPLV_QB, REPLV_QB_MM }, |
| 14947 | { REPL_PH, REPL_PH, REPL_PH_MM }, |
| 14948 | { REPL_QB, REPL_QB, REPL_QB_MM }, |
| 14949 | { SHILO, SHILO, SHILO_MM }, |
| 14950 | { SHILOV, SHILOV, SHILOV_MM }, |
| 14951 | { SHLLV_PH, SHLLV_PH, SHLLV_PH_MM }, |
| 14952 | { SHLLV_QB, SHLLV_QB, SHLLV_QB_MM }, |
| 14953 | { SHLLV_S_PH, SHLLV_S_PH, SHLLV_S_PH_MM }, |
| 14954 | { SHLLV_S_W, SHLLV_S_W, SHLLV_S_W_MM }, |
| 14955 | { SHLL_PH, SHLL_PH, SHLL_PH_MM }, |
| 14956 | { SHLL_QB, SHLL_QB, SHLL_QB_MM }, |
| 14957 | { SHLL_S_PH, SHLL_S_PH, SHLL_S_PH_MM }, |
| 14958 | { SHLL_S_W, SHLL_S_W, SHLL_S_W_MM }, |
| 14959 | { SHRAV_PH, SHRAV_PH, SHRAV_PH_MM }, |
| 14960 | { SHRAV_QB, SHRAV_QB, SHRAV_QB_MMR2 }, |
| 14961 | { SHRAV_R_PH, SHRAV_R_PH, SHRAV_R_PH_MM }, |
| 14962 | { SHRAV_R_QB, SHRAV_R_QB, SHRAV_R_QB_MMR2 }, |
| 14963 | { SHRAV_R_W, SHRAV_R_W, SHRAV_R_W_MM }, |
| 14964 | { SHRA_PH, SHRA_PH, SHRA_PH_MM }, |
| 14965 | { SHRA_QB, SHRA_QB, SHRA_QB_MMR2 }, |
| 14966 | { SHRA_R_PH, SHRA_R_PH, SHRA_R_PH_MM }, |
| 14967 | { SHRA_R_QB, SHRA_R_QB, SHRA_R_QB_MMR2 }, |
| 14968 | { SHRA_R_W, SHRA_R_W, SHRA_R_W_MM }, |
| 14969 | { SHRLV_PH, SHRLV_PH, SHRLV_PH_MMR2 }, |
| 14970 | { SHRLV_QB, SHRLV_QB, SHRLV_QB_MM }, |
| 14971 | { SHRL_PH, SHRL_PH, SHRL_PH_MMR2 }, |
| 14972 | { SHRL_QB, SHRL_QB, SHRL_QB_MM }, |
| 14973 | { SUBQH_PH, SUBQH_PH, SUBQH_PH_MMR2 }, |
| 14974 | { SUBQH_R_PH, SUBQH_R_PH, SUBQH_R_PH_MMR2 }, |
| 14975 | { SUBQH_R_W, SUBQH_R_W, SUBQH_R_W_MMR2 }, |
| 14976 | { SUBQH_W, SUBQH_W, SUBQH_W_MMR2 }, |
| 14977 | { SUBQ_PH, SUBQ_PH, SUBQ_PH_MM }, |
| 14978 | { SUBQ_S_PH, SUBQ_S_PH, SUBQ_S_PH_MM }, |
| 14979 | { SUBQ_S_W, SUBQ_S_W, SUBQ_S_W_MM }, |
| 14980 | { SUBUH_QB, SUBUH_QB, SUBUH_QB_MMR2 }, |
| 14981 | { SUBUH_R_QB, SUBUH_R_QB, SUBUH_R_QB_MMR2 }, |
| 14982 | { SUBU_PH, SUBU_PH, SUBU_PH_MMR2 }, |
| 14983 | { SUBU_QB, SUBU_QB, SUBU_QB_MM }, |
| 14984 | { SUBU_S_PH, SUBU_S_PH, SUBU_S_PH_MMR2 }, |
| 14985 | { SUBU_S_QB, SUBU_S_QB, SUBU_S_QB_MM }, |
| 14986 | { SWDSP, SWDSP, SWDSP_MM }, |
| 14987 | }; // End of Table |
| 14988 | |
| 14989 | unsigned mid; |
| 14990 | unsigned start = 0; |
| 14991 | unsigned end = 160; |
| 14992 | while (start < end) { |
| 14993 | mid = start + (end - start) / 2; |
| 14994 | if (Opcode == Table[mid][0]) |
| 14995 | break; |
| 14996 | if (Opcode < Table[mid][0]) |
| 14997 | end = mid; |
| 14998 | else |
| 14999 | start = mid + 1; |
| 15000 | } |
| 15001 | if (start == end) |
| 15002 | return -1; // Instruction doesn't exist in this table. |
| 15003 | |
| 15004 | if (inArch == Arch_dsp) |
| 15005 | return Table[mid][1]; |
| 15006 | if (inArch == Arch_mmdsp) |
| 15007 | return Table[mid][2]; |
| 15008 | return -1;} |
| 15009 | |
| 15010 | // MipsR62MicroMipsR6 |
| 15011 | LLVM_READONLY |
| 15012 | int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) { |
| 15013 | using namespace Mips; |
| 15014 | static constexpr uint16_t Table[][3] = { |
| 15015 | { ADDIUPC, ADDIUPC, ADDIUPC_MMR6 }, |
| 15016 | { ALIGN, ALIGN, ALIGN_MMR6 }, |
| 15017 | { ALUIPC, ALUIPC, ALUIPC_MMR6 }, |
| 15018 | { AUI, AUI, AUI_MMR6 }, |
| 15019 | { AUIPC, AUIPC, AUIPC_MMR6 }, |
| 15020 | { BALC, BALC, BALC_MMR6 }, |
| 15021 | { BC, BC, BC_MMR6 }, |
| 15022 | { BEQC, BEQC, BEQC_MMR6 }, |
| 15023 | { BEQZALC, BEQZALC, BEQZALC_MMR6 }, |
| 15024 | { BEQZC, BEQZC, BEQZC_MMR6 }, |
| 15025 | { BGEC, BGEC, BGEC_MMR6 }, |
| 15026 | { BGEUC, BGEUC, BGEUC_MMR6 }, |
| 15027 | { BGEZALC, BGEZALC, BGEZALC_MMR6 }, |
| 15028 | { BGEZC, BGEZC, BGEZC_MMR6 }, |
| 15029 | { BGTZALC, BGTZALC, BGTZALC_MMR6 }, |
| 15030 | { BGTZC, BGTZC, BGTZC_MMR6 }, |
| 15031 | { BITSWAP, BITSWAP, BITSWAP_MMR6 }, |
| 15032 | { BLEZALC, BLEZALC, BLEZALC_MMR6 }, |
| 15033 | { BLEZC, BLEZC, BLEZC_MMR6 }, |
| 15034 | { BLTC, BLTC, BLTC_MMR6 }, |
| 15035 | { BLTUC, BLTUC, BLTUC_MMR6 }, |
| 15036 | { BLTZALC, BLTZALC, BLTZALC_MMR6 }, |
| 15037 | { BLTZC, BLTZC, BLTZC_MMR6 }, |
| 15038 | { BNEC, BNEC, BNEC_MMR6 }, |
| 15039 | { BNEZALC, BNEZALC, BNEZALC_MMR6 }, |
| 15040 | { BNEZC, BNEZC, BNEZC_MMR6 }, |
| 15041 | { BNVC, BNVC, BNVC_MMR6 }, |
| 15042 | { BOVC, BOVC, BOVC_MMR6 }, |
| 15043 | { CACHE_R6, CACHE_R6, CACHE_MMR6 }, |
| 15044 | { CLO_R6, CLO_R6, CLO_MMR6 }, |
| 15045 | { CLZ_R6, CLZ_R6, CLZ_MMR6 }, |
| 15046 | { CMP_EQ_D, CMP_EQ_D, CMP_EQ_D_MMR6 }, |
| 15047 | { CMP_EQ_S, CMP_EQ_S, CMP_EQ_S_MMR6 }, |
| 15048 | { CMP_F_D, CMP_F_D, CMP_AF_D_MMR6 }, |
| 15049 | { CMP_F_S, CMP_F_S, CMP_AF_S_MMR6 }, |
| 15050 | { CMP_LE_D, CMP_LE_D, CMP_LE_D_MMR6 }, |
| 15051 | { CMP_LE_S, CMP_LE_S, CMP_LE_S_MMR6 }, |
| 15052 | { CMP_LT_D, CMP_LT_D, CMP_LT_D_MMR6 }, |
| 15053 | { CMP_LT_S, CMP_LT_S, CMP_LT_S_MMR6 }, |
| 15054 | { CMP_SAF_D, CMP_SAF_D, CMP_SAF_D_MMR6 }, |
| 15055 | { CMP_SAF_S, CMP_SAF_S, CMP_SAF_S_MMR6 }, |
| 15056 | { CMP_SEQ_D, CMP_SEQ_D, CMP_SEQ_D_MMR6 }, |
| 15057 | { CMP_SEQ_S, CMP_SEQ_S, CMP_SEQ_S_MMR6 }, |
| 15058 | { CMP_SLE_D, CMP_SLE_D, CMP_SLE_D_MMR6 }, |
| 15059 | { CMP_SLE_S, CMP_SLE_S, CMP_SLE_S_MMR6 }, |
| 15060 | { CMP_SLT_D, CMP_SLT_D, CMP_SLT_D_MMR6 }, |
| 15061 | { CMP_SLT_S, CMP_SLT_S, CMP_SLT_S_MMR6 }, |
| 15062 | { CMP_SUEQ_D, CMP_SUEQ_D, CMP_SUEQ_D_MMR6 }, |
| 15063 | { CMP_SUEQ_S, CMP_SUEQ_S, CMP_SUEQ_S_MMR6 }, |
| 15064 | { CMP_SULE_D, CMP_SULE_D, CMP_SULE_D_MMR6 }, |
| 15065 | { CMP_SULE_S, CMP_SULE_S, CMP_SULE_S_MMR6 }, |
| 15066 | { CMP_SULT_D, CMP_SULT_D, CMP_SULT_D_MMR6 }, |
| 15067 | { CMP_SULT_S, CMP_SULT_S, CMP_SULT_S_MMR6 }, |
| 15068 | { CMP_SUN_D, CMP_SUN_D, CMP_SUN_D_MMR6 }, |
| 15069 | { CMP_SUN_S, CMP_SUN_S, CMP_SUN_S_MMR6 }, |
| 15070 | { CMP_UEQ_D, CMP_UEQ_D, CMP_UEQ_D_MMR6 }, |
| 15071 | { CMP_UEQ_S, CMP_UEQ_S, CMP_UEQ_S_MMR6 }, |
| 15072 | { CMP_ULE_D, CMP_ULE_D, CMP_ULE_D_MMR6 }, |
| 15073 | { CMP_ULE_S, CMP_ULE_S, CMP_ULE_S_MMR6 }, |
| 15074 | { CMP_ULT_D, CMP_ULT_D, CMP_ULT_D_MMR6 }, |
| 15075 | { CMP_ULT_S, CMP_ULT_S, CMP_ULT_S_MMR6 }, |
| 15076 | { CMP_UN_D, CMP_UN_D, CMP_UN_D_MMR6 }, |
| 15077 | { CMP_UN_S, CMP_UN_S, CMP_UN_S_MMR6 }, |
| 15078 | { CRC32B, CRC32B, (uint16_t)-1U }, |
| 15079 | { CRC32CB, CRC32CB, (uint16_t)-1U }, |
| 15080 | { CRC32CD, CRC32CD, (uint16_t)-1U }, |
| 15081 | { CRC32CH, CRC32CH, (uint16_t)-1U }, |
| 15082 | { CRC32CW, CRC32CW, (uint16_t)-1U }, |
| 15083 | { CRC32D, CRC32D, (uint16_t)-1U }, |
| 15084 | { CRC32H, CRC32H, (uint16_t)-1U }, |
| 15085 | { CRC32W, CRC32W, (uint16_t)-1U }, |
| 15086 | { DIV, DIV, DIV_MMR6 }, |
| 15087 | { DIVU, DIVU, DIVU_MMR6 }, |
| 15088 | { DVP, DVP, DVP_MMR6 }, |
| 15089 | { EVP, EVP, EVP_MMR6 }, |
| 15090 | { GINVI, GINVI, GINVI_MMR6 }, |
| 15091 | { GINVT, GINVT, GINVT_MMR6 }, |
| 15092 | { JIALC, JIALC, JIALC_MMR6 }, |
| 15093 | { JIC, JIC, JIC_MMR6 }, |
| 15094 | { LSA_R6, LSA_R6, LSA_MMR6 }, |
| 15095 | { LWPC, LWPC, LWPC_MMR6 }, |
| 15096 | { MOD, MOD, MOD_MMR6 }, |
| 15097 | { MODU, MODU, MODU_MMR6 }, |
| 15098 | { MUH, MUH, MUH_MMR6 }, |
| 15099 | { MUHU, MUHU, MUHU_MMR6 }, |
| 15100 | { MULU, MULU, MULU_MMR6 }, |
| 15101 | { MUL_R6, MUL_R6, MUL_MMR6 }, |
| 15102 | { PREF_R6, PREF_R6, PREF_MMR6 }, |
| 15103 | { SELEQZ, SELEQZ, SELEQZ_MMR6 }, |
| 15104 | { SELEQZ_D, SELEQZ_D, SELEQZ_D_MMR6 }, |
| 15105 | { SELEQZ_S, SELEQZ_S, SELEQZ_S_MMR6 }, |
| 15106 | { SELNEZ, SELNEZ, SELNEZ_MMR6 }, |
| 15107 | { SELNEZ_D, SELNEZ_D, SELNEZ_D_MMR6 }, |
| 15108 | { SELNEZ_S, SELNEZ_S, SELNEZ_S_MMR6 }, |
| 15109 | { SEL_D, SEL_D, SEL_D_MMR6 }, |
| 15110 | { SEL_S, SEL_S, SEL_S_MMR6 }, |
| 15111 | }; // End of Table |
| 15112 | |
| 15113 | unsigned mid; |
| 15114 | unsigned start = 0; |
| 15115 | unsigned end = 96; |
| 15116 | while (start < end) { |
| 15117 | mid = start + (end - start) / 2; |
| 15118 | if (Opcode == Table[mid][0]) |
| 15119 | break; |
| 15120 | if (Opcode < Table[mid][0]) |
| 15121 | end = mid; |
| 15122 | else |
| 15123 | start = mid + 1; |
| 15124 | } |
| 15125 | if (start == end) |
| 15126 | return -1; // Instruction doesn't exist in this table. |
| 15127 | |
| 15128 | if (inArch == Arch_mipsr6) |
| 15129 | return Table[mid][1]; |
| 15130 | if (inArch == Arch_micromipsr6) |
| 15131 | return Table[mid][2]; |
| 15132 | return -1;} |
| 15133 | |
| 15134 | // Std2MicroMips |
| 15135 | LLVM_READONLY |
| 15136 | int Std2MicroMips(uint16_t Opcode, enum Arch inArch) { |
| 15137 | using namespace Mips; |
| 15138 | static constexpr uint16_t Table[][3] = { |
| 15139 | { ADD, ADD, ADD_MM }, |
| 15140 | { ADDi, ADDi, ADDi_MM }, |
| 15141 | { ADDiu, ADDiu, ADDiu_MM }, |
| 15142 | { ADDu, ADDu, ADDu_MM }, |
| 15143 | { AND, AND, AND_MM }, |
| 15144 | { ANDi, ANDi, ANDi_MM }, |
| 15145 | { BC1F, BC1F, BC1F_MM }, |
| 15146 | { BC1FL, BC1FL, (uint16_t)-1U }, |
| 15147 | { BC1T, BC1T, BC1T_MM }, |
| 15148 | { BC1TL, BC1TL, (uint16_t)-1U }, |
| 15149 | { BEQ, BEQ, BEQ_MM }, |
| 15150 | { BEQL, BEQL, (uint16_t)-1U }, |
| 15151 | { BGEZ, BGEZ, BGEZ_MM }, |
| 15152 | { BGEZAL, BGEZAL, BGEZAL_MM }, |
| 15153 | { BGEZALL, BGEZALL, (uint16_t)-1U }, |
| 15154 | { BGEZL, BGEZL, (uint16_t)-1U }, |
| 15155 | { BGTZ, BGTZ, BGTZ_MM }, |
| 15156 | { BGTZL, BGTZL, (uint16_t)-1U }, |
| 15157 | { BLEZ, BLEZ, BLEZ_MM }, |
| 15158 | { BLEZL, BLEZL, (uint16_t)-1U }, |
| 15159 | { BLTZ, BLTZ, BLTZ_MM }, |
| 15160 | { BLTZAL, BLTZAL, BLTZAL_MM }, |
| 15161 | { BLTZALL, BLTZALL, (uint16_t)-1U }, |
| 15162 | { BLTZL, BLTZL, (uint16_t)-1U }, |
| 15163 | { BNE, BNE, BNE_MM }, |
| 15164 | { BNEL, BNEL, (uint16_t)-1U }, |
| 15165 | { BREAK, BREAK, BREAK_MM }, |
| 15166 | { CACHE, CACHE, CACHE_MM }, |
| 15167 | { CACHEE, CACHEE, CACHEE_MM }, |
| 15168 | { CEIL_W_D32, CEIL_W_D32, CEIL_W_MM }, |
| 15169 | { CEIL_W_S, CEIL_W_S, CEIL_W_S_MM }, |
| 15170 | { CFC1, CFC1, CFC1_MM }, |
| 15171 | { CLO, CLO, CLO_MM }, |
| 15172 | { CLZ, CLZ, CLZ_MM }, |
| 15173 | { CTC1, CTC1, CTC1_MM }, |
| 15174 | { CVT_D32_S, CVT_D32_S, CVT_D32_S_MM }, |
| 15175 | { CVT_D32_W, CVT_D32_W, CVT_D32_W_MM }, |
| 15176 | { CVT_L_D64, CVT_L_D64, CVT_L_D64_MM }, |
| 15177 | { CVT_L_S, CVT_L_S, CVT_L_S_MM }, |
| 15178 | { CVT_S_D32, CVT_S_D32, CVT_S_D32_MM }, |
| 15179 | { CVT_S_W, CVT_S_W, CVT_S_W_MM }, |
| 15180 | { CVT_W_D32, CVT_W_D32, CVT_W_D32_MM }, |
| 15181 | { CVT_W_S, CVT_W_S, CVT_W_S_MM }, |
| 15182 | { C_EQ_D32, C_EQ_D32, C_EQ_D32_MM }, |
| 15183 | { C_EQ_D64, C_EQ_D64, C_EQ_D64_MM }, |
| 15184 | { C_EQ_S, C_EQ_S, C_EQ_S_MM }, |
| 15185 | { C_F_D32, C_F_D32, C_F_D32_MM }, |
| 15186 | { C_F_D64, C_F_D64, C_F_D64_MM }, |
| 15187 | { C_F_S, C_F_S, C_F_S_MM }, |
| 15188 | { C_LE_D32, C_LE_D32, C_LE_D32_MM }, |
| 15189 | { C_LE_D64, C_LE_D64, C_LE_D64_MM }, |
| 15190 | { C_LE_S, C_LE_S, C_LE_S_MM }, |
| 15191 | { C_LT_D32, C_LT_D32, C_LT_D32_MM }, |
| 15192 | { C_LT_D64, C_LT_D64, C_LT_D64_MM }, |
| 15193 | { C_LT_S, C_LT_S, C_LT_S_MM }, |
| 15194 | { C_NGE_D32, C_NGE_D32, C_NGE_D32_MM }, |
| 15195 | { C_NGE_D64, C_NGE_D64, C_NGE_D64_MM }, |
| 15196 | { C_NGE_S, C_NGE_S, C_NGE_S_MM }, |
| 15197 | { C_NGLE_D32, C_NGLE_D32, C_NGLE_D32_MM }, |
| 15198 | { C_NGLE_D64, C_NGLE_D64, C_NGLE_D64_MM }, |
| 15199 | { C_NGLE_S, C_NGLE_S, C_NGLE_S_MM }, |
| 15200 | { C_NGL_D32, C_NGL_D32, C_NGL_D32_MM }, |
| 15201 | { C_NGL_D64, C_NGL_D64, C_NGL_D64_MM }, |
| 15202 | { C_NGL_S, C_NGL_S, C_NGL_S_MM }, |
| 15203 | { C_NGT_D32, C_NGT_D32, C_NGT_D32_MM }, |
| 15204 | { C_NGT_D64, C_NGT_D64, C_NGT_D64_MM }, |
| 15205 | { C_NGT_S, C_NGT_S, C_NGT_S_MM }, |
| 15206 | { C_OLE_D32, C_OLE_D32, C_OLE_D32_MM }, |
| 15207 | { C_OLE_D64, C_OLE_D64, C_OLE_D64_MM }, |
| 15208 | { C_OLE_S, C_OLE_S, C_OLE_S_MM }, |
| 15209 | { C_OLT_D32, C_OLT_D32, C_OLT_D32_MM }, |
| 15210 | { C_OLT_D64, C_OLT_D64, C_OLT_D64_MM }, |
| 15211 | { C_OLT_S, C_OLT_S, C_OLT_S_MM }, |
| 15212 | { C_SEQ_D32, C_SEQ_D32, C_SEQ_D32_MM }, |
| 15213 | { C_SEQ_D64, C_SEQ_D64, C_SEQ_D64_MM }, |
| 15214 | { C_SEQ_S, C_SEQ_S, C_SEQ_S_MM }, |
| 15215 | { C_SF_D32, C_SF_D32, C_SF_D32_MM }, |
| 15216 | { C_SF_D64, C_SF_D64, C_SF_D64_MM }, |
| 15217 | { C_SF_S, C_SF_S, C_SF_S_MM }, |
| 15218 | { C_UEQ_D32, C_UEQ_D32, C_UEQ_D32_MM }, |
| 15219 | { C_UEQ_D64, C_UEQ_D64, C_UEQ_D64_MM }, |
| 15220 | { C_UEQ_S, C_UEQ_S, C_UEQ_S_MM }, |
| 15221 | { C_ULE_D32, C_ULE_D32, C_ULE_D32_MM }, |
| 15222 | { C_ULE_D64, C_ULE_D64, C_ULE_D64_MM }, |
| 15223 | { C_ULE_S, C_ULE_S, C_ULE_S_MM }, |
| 15224 | { C_ULT_D32, C_ULT_D32, C_ULT_D32_MM }, |
| 15225 | { C_ULT_D64, C_ULT_D64, C_ULT_D64_MM }, |
| 15226 | { C_ULT_S, C_ULT_S, C_ULT_S_MM }, |
| 15227 | { C_UN_D32, C_UN_D32, C_UN_D32_MM }, |
| 15228 | { C_UN_D64, C_UN_D64, C_UN_D64_MM }, |
| 15229 | { C_UN_S, C_UN_S, C_UN_S_MM }, |
| 15230 | { DERET, DERET, DERET_MM }, |
| 15231 | { DI, DI, DI_MM }, |
| 15232 | { EHB, EHB, EHB_MM }, |
| 15233 | { EI, EI, EI_MM }, |
| 15234 | { ERET, ERET, ERET_MM }, |
| 15235 | { ERETNC, ERETNC, (uint16_t)-1U }, |
| 15236 | { EXT, EXT, EXT_MM }, |
| 15237 | { FABS_D32, FABS_D32, FABS_D32_MM }, |
| 15238 | { FABS_S, FABS_S, FABS_S_MM }, |
| 15239 | { FADD_D32, FADD_D32, FADD_D32_MM }, |
| 15240 | { FADD_S, FADD_S, FADD_S_MM }, |
| 15241 | { FCMP_D32, FCMP_D32, FCMP_D32_MM }, |
| 15242 | { FCMP_S32, FCMP_S32, FCMP_S32_MM }, |
| 15243 | { FDIV_D32, FDIV_D32, FDIV_D32_MM }, |
| 15244 | { FDIV_S, FDIV_S, FDIV_S_MM }, |
| 15245 | { FLOOR_W_D32, FLOOR_W_D32, FLOOR_W_MM }, |
| 15246 | { FLOOR_W_S, FLOOR_W_S, FLOOR_W_S_MM }, |
| 15247 | { FMOV_D32, FMOV_D32, FMOV_D32_MM }, |
| 15248 | { FMOV_S, FMOV_S, FMOV_S_MM }, |
| 15249 | { FMUL_D32, FMUL_D32, FMUL_D32_MM }, |
| 15250 | { FMUL_S, FMUL_S, FMUL_S_MM }, |
| 15251 | { FNEG_D32, FNEG_D32, FNEG_D32_MM }, |
| 15252 | { FNEG_S, FNEG_S, FNEG_S_MM }, |
| 15253 | { FSQRT_D32, FSQRT_D32, FSQRT_D32_MM }, |
| 15254 | { FSQRT_S, FSQRT_S, FSQRT_S_MM }, |
| 15255 | { FSUB_D32, FSUB_D32, FSUB_D32_MM }, |
| 15256 | { FSUB_S, FSUB_S, FSUB_S_MM }, |
| 15257 | { HYPCALL, HYPCALL, HYPCALL_MM }, |
| 15258 | { INS, INS, INS_MM }, |
| 15259 | { J, J, J_MM }, |
| 15260 | { JAL, JAL, JAL_MM }, |
| 15261 | { JALX, JALX, JALX_MM }, |
| 15262 | { JR, JR, JR_MM }, |
| 15263 | { LB, LB, LB_MM }, |
| 15264 | { LBE, LBE, LBE_MM }, |
| 15265 | { LBu, LBu, LBu_MM }, |
| 15266 | { LBuE, LBuE, LBuE_MM }, |
| 15267 | { LDC1, LDC1, LDC1_MM_D32 }, |
| 15268 | { LEA_ADDiu, LEA_ADDiu, LEA_ADDiu_MM }, |
| 15269 | { LH, LH, LH_MM }, |
| 15270 | { LHE, LHE, LHE_MM }, |
| 15271 | { LHu, LHu, LHu_MM }, |
| 15272 | { LHuE, LHuE, LHuE_MM }, |
| 15273 | { LLE, LLE, LLE_MM }, |
| 15274 | { LUXC1, LUXC1, LUXC1_MM }, |
| 15275 | { LUi, LUi, LUi_MM }, |
| 15276 | { LW, LW, LW_MM }, |
| 15277 | { LWC1, LWC1, LWC1_MM }, |
| 15278 | { LWE, LWE, LWE_MM }, |
| 15279 | { LWL, LWL, LWL_MM }, |
| 15280 | { LWLE, LWLE, LWLE_MM }, |
| 15281 | { LWR, LWR, LWR_MM }, |
| 15282 | { LWRE, LWRE, LWRE_MM }, |
| 15283 | { LWXC1, LWXC1, LWXC1_MM }, |
| 15284 | { LWu, LWu, LWU_MM }, |
| 15285 | { MADD, MADD, MADD_MM }, |
| 15286 | { MADDU, MADDU, MADDU_MM }, |
| 15287 | { MADD_D32, MADD_D32, MADD_D32_MM }, |
| 15288 | { MADD_S, MADD_S, MADD_S_MM }, |
| 15289 | { MFC1, MFC1, MFC1_MM }, |
| 15290 | { MFGC0, MFGC0, MFGC0_MM }, |
| 15291 | { MFHC1_D32, MFHC1_D32, MFHC1_D32_MM }, |
| 15292 | { MFHGC0, MFHGC0, MFHGC0_MM }, |
| 15293 | { MFHI, MFHI, MFHI_MM }, |
| 15294 | { MFLO, MFLO, MFLO_MM }, |
| 15295 | { MOVF_D32, MOVF_D32, MOVF_D32_MM }, |
| 15296 | { MOVF_I, MOVF_I, MOVF_I_MM }, |
| 15297 | { MOVF_S, MOVF_S, MOVF_S_MM }, |
| 15298 | { MOVN_I_D32, MOVN_I_D32, MOVN_I_D32_MM }, |
| 15299 | { MOVN_I_I, MOVN_I_I, MOVN_I_MM }, |
| 15300 | { MOVN_I_S, MOVN_I_S, MOVN_I_S_MM }, |
| 15301 | { MOVT_D32, MOVT_D32, MOVT_D32_MM }, |
| 15302 | { MOVT_I, MOVT_I, MOVT_I_MM }, |
| 15303 | { MOVT_S, MOVT_S, MOVT_S_MM }, |
| 15304 | { MOVZ_I_D32, MOVZ_I_D32, MOVZ_I_D32_MM }, |
| 15305 | { MOVZ_I_I, MOVZ_I_I, MOVZ_I_MM }, |
| 15306 | { MOVZ_I_S, MOVZ_I_S, MOVZ_I_S_MM }, |
| 15307 | { MSUB, MSUB, MSUB_MM }, |
| 15308 | { MSUBU, MSUBU, MSUBU_MM }, |
| 15309 | { MSUB_D32, MSUB_D32, MSUB_D32_MM }, |
| 15310 | { MSUB_S, MSUB_S, MSUB_S_MM }, |
| 15311 | { MTC1, MTC1, MTC1_MM }, |
| 15312 | { MTGC0, MTGC0, MTGC0_MM }, |
| 15313 | { MTHC1_D32, MTHC1_D32, MTHC1_D32_MM }, |
| 15314 | { MTHGC0, MTHGC0, MTHGC0_MM }, |
| 15315 | { MTHI, MTHI, MTHI_MM }, |
| 15316 | { MTLO, MTLO, MTLO_MM }, |
| 15317 | { MUL, MUL, MUL_MM }, |
| 15318 | { MULT, MULT, MULT_MM }, |
| 15319 | { MULTu, MULTu, MULTu_MM }, |
| 15320 | { NMADD_D32, NMADD_D32, NMADD_D32_MM }, |
| 15321 | { NMADD_S, NMADD_S, NMADD_S_MM }, |
| 15322 | { NMSUB_D32, NMSUB_D32, NMSUB_D32_MM }, |
| 15323 | { NMSUB_S, NMSUB_S, NMSUB_S_MM }, |
| 15324 | { NOR, NOR, NOR_MM }, |
| 15325 | { OR, OR, OR_MM }, |
| 15326 | { ORi, ORi, ORi_MM }, |
| 15327 | { PAUSE, PAUSE, PAUSE_MM }, |
| 15328 | { PREF, PREF, PREF_MM }, |
| 15329 | { PREFE, PREFE, PREFE_MM }, |
| 15330 | { RDHWR, RDHWR, RDHWR_MM }, |
| 15331 | { RECIP_D32, RECIP_D32, RECIP_D32_MM }, |
| 15332 | { RECIP_D64, RECIP_D64, RECIP_D64_MM }, |
| 15333 | { RECIP_S, RECIP_S, RECIP_S_MM }, |
| 15334 | { ROTR, ROTR, ROTR_MM }, |
| 15335 | { ROTRV, ROTRV, ROTRV_MM }, |
| 15336 | { ROUND_W_D32, ROUND_W_D32, ROUND_W_MM }, |
| 15337 | { ROUND_W_S, ROUND_W_S, ROUND_W_S_MM }, |
| 15338 | { RSQRT_D32, RSQRT_D32, RSQRT_D32_MM }, |
| 15339 | { RSQRT_D64, RSQRT_D64, RSQRT_D64_MM }, |
| 15340 | { RSQRT_S, RSQRT_S, RSQRT_S_MM }, |
| 15341 | { SB, SB, SB_MM }, |
| 15342 | { SBE, SBE, SBE_MM }, |
| 15343 | { SCE, SCE, SCE_MM }, |
| 15344 | { SDBBP, SDBBP, SDBBP_MM }, |
| 15345 | { SDC1, SDC1, (uint16_t)-1U }, |
| 15346 | { SDIV, SDIV, SDIV_MM }, |
| 15347 | { SEB, SEB, SEB_MM }, |
| 15348 | { SEH, SEH, SEH_MM }, |
| 15349 | { SH, SH, SH_MM }, |
| 15350 | { SHE, SHE, SHE_MM }, |
| 15351 | { SLL, SLL, SLL_MM }, |
| 15352 | { SLLV, SLLV, SLLV_MM }, |
| 15353 | { SLT, SLT, SLT_MM }, |
| 15354 | { SLTi, SLTi, SLTi_MM }, |
| 15355 | { SLTiu, SLTiu, SLTiu_MM }, |
| 15356 | { SLTu, SLTu, SLTu_MM }, |
| 15357 | { SRA, SRA, SRA_MM }, |
| 15358 | { SRAV, SRAV, SRAV_MM }, |
| 15359 | { SRL, SRL, SRL_MM }, |
| 15360 | { SRLV, SRLV, SRLV_MM }, |
| 15361 | { SSNOP, SSNOP, SSNOP_MM }, |
| 15362 | { SUB, SUB, SUB_MM }, |
| 15363 | { SUBu, SUBu, SUBu_MM }, |
| 15364 | { SUXC1, SUXC1, SUXC1_MM }, |
| 15365 | { SW, SW, SW_MM }, |
| 15366 | { SWC1, SWC1, SWC1_MM }, |
| 15367 | { SWE, SWE, SWE_MM }, |
| 15368 | { SWL, SWL, SWL_MM }, |
| 15369 | { SWLE, SWLE, SWLE_MM }, |
| 15370 | { SWR, SWR, SWR_MM }, |
| 15371 | { SWRE, SWRE, SWRE_MM }, |
| 15372 | { SWXC1, SWXC1, SWXC1_MM }, |
| 15373 | { SYNC, SYNC, SYNC_MM }, |
| 15374 | { SYNCI, SYNCI, SYNCI_MM }, |
| 15375 | { SYSCALL, SYSCALL, SYSCALL_MM }, |
| 15376 | { TEQ, TEQ, TEQ_MM }, |
| 15377 | { TEQI, TEQI, TEQI_MM }, |
| 15378 | { TGE, TGE, TGE_MM }, |
| 15379 | { TGEI, TGEI, TGEI_MM }, |
| 15380 | { TGEIU, TGEIU, TGEIU_MM }, |
| 15381 | { TGEU, TGEU, TGEU_MM }, |
| 15382 | { TLBGINV, TLBGINV, TLBGINV_MM }, |
| 15383 | { TLBGINVF, TLBGINVF, TLBGINVF_MM }, |
| 15384 | { TLBGP, TLBGP, TLBGP_MM }, |
| 15385 | { TLBGR, TLBGR, TLBGR_MM }, |
| 15386 | { TLBGWI, TLBGWI, TLBGWI_MM }, |
| 15387 | { TLBGWR, TLBGWR, TLBGWR_MM }, |
| 15388 | { TLBP, TLBP, TLBP_MM }, |
| 15389 | { TLBR, TLBR, TLBR_MM }, |
| 15390 | { TLBWI, TLBWI, TLBWI_MM }, |
| 15391 | { TLBWR, TLBWR, TLBWR_MM }, |
| 15392 | { TLT, TLT, TLT_MM }, |
| 15393 | { TLTI, TLTI, TLTI_MM }, |
| 15394 | { TLTU, TLTU, TLTU_MM }, |
| 15395 | { TNE, TNE, TNE_MM }, |
| 15396 | { TNEI, TNEI, TNEI_MM }, |
| 15397 | { TRUNC_W_D32, TRUNC_W_D32, TRUNC_W_MM }, |
| 15398 | { TRUNC_W_S, TRUNC_W_S, TRUNC_W_S_MM }, |
| 15399 | { TTLTIU, TTLTIU, TLTIU_MM }, |
| 15400 | { UDIV, UDIV, UDIV_MM }, |
| 15401 | { WAIT, WAIT, WAIT_MM }, |
| 15402 | { WSBH, WSBH, WSBH_MM }, |
| 15403 | { XOR, XOR, XOR_MM }, |
| 15404 | { XORi, XORi, XORi_MM }, |
| 15405 | }; // End of Table |
| 15406 | |
| 15407 | unsigned mid; |
| 15408 | unsigned start = 0; |
| 15409 | unsigned end = 266; |
| 15410 | while (start < end) { |
| 15411 | mid = start + (end - start) / 2; |
| 15412 | if (Opcode == Table[mid][0]) |
| 15413 | break; |
| 15414 | if (Opcode < Table[mid][0]) |
| 15415 | end = mid; |
| 15416 | else |
| 15417 | start = mid + 1; |
| 15418 | } |
| 15419 | if (start == end) |
| 15420 | return -1; // Instruction doesn't exist in this table. |
| 15421 | |
| 15422 | if (inArch == Arch_se) |
| 15423 | return Table[mid][1]; |
| 15424 | if (inArch == Arch_micromips) |
| 15425 | return Table[mid][2]; |
| 15426 | return -1;} |
| 15427 | |
| 15428 | // Std2MicroMipsR6 |
| 15429 | LLVM_READONLY |
| 15430 | int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) { |
| 15431 | using namespace Mips; |
| 15432 | static constexpr uint16_t Table[][3] = { |
| 15433 | { ADD, ADD, ADD_MMR6 }, |
| 15434 | { ADDiu, ADDiu, ADDIU_MMR6 }, |
| 15435 | { ADDu, ADDu, ADDU_MMR6 }, |
| 15436 | { AND, AND, AND_MMR6 }, |
| 15437 | { ANDi, ANDi, ANDI_MMR6 }, |
| 15438 | { BREAK, BREAK, BREAK_MMR6 }, |
| 15439 | { CEIL_W_D64, CEIL_W_D64, CEIL_W_D_MMR6 }, |
| 15440 | { CEIL_W_S, CEIL_W_S, CEIL_W_S_MMR6 }, |
| 15441 | { CVT_W_D64, CVT_W_D64, (uint16_t)-1U }, |
| 15442 | { DI, DI, DI_MMR6 }, |
| 15443 | { EI, EI, EI_MMR6 }, |
| 15444 | { EXT, EXT, EXT_MMR6 }, |
| 15445 | { FABS_D64, FABS_D64, (uint16_t)-1U }, |
| 15446 | { FLOOR_W_D64, FLOOR_W_D64, FLOOR_W_D_MMR6 }, |
| 15447 | { FLOOR_W_S, FLOOR_W_S, FLOOR_W_S_MMR6 }, |
| 15448 | { FMOV_D64, FMOV_D64, FMOV_D_MMR6 }, |
| 15449 | { FNEG_D64, FNEG_D64, (uint16_t)-1U }, |
| 15450 | { FSQRT_D64, FSQRT_D64, (uint16_t)-1U }, |
| 15451 | { FSQRT_S, FSQRT_S, (uint16_t)-1U }, |
| 15452 | { INS, INS, INS_MMR6 }, |
| 15453 | { LDC1, LDC1, (uint16_t)-1U }, |
| 15454 | { LDC164, LDC164, LDC1_D64_MMR6 }, |
| 15455 | { LDC2, LDC2, LDC2_MMR6 }, |
| 15456 | { LW, LW, LW_MMR6 }, |
| 15457 | { LWC2, LWC2, LWC2_MMR6 }, |
| 15458 | { MFC1, MFC1, MFC1_MMR6 }, |
| 15459 | { MTC1, MTC1, MTC1_MMR6 }, |
| 15460 | { MTHC1_D32, MTHC1_D32, (uint16_t)-1U }, |
| 15461 | { NOR, NOR, NOR_MMR6 }, |
| 15462 | { OR, OR, OR_MMR6 }, |
| 15463 | { ORi, ORi, ORI_MMR6 }, |
| 15464 | { PAUSE, PAUSE, PAUSE_MMR6 }, |
| 15465 | { ROUND_W_D64, ROUND_W_D64, ROUND_W_D_MMR6 }, |
| 15466 | { ROUND_W_S, ROUND_W_S, ROUND_W_S_MMR6 }, |
| 15467 | { SB, SB, SB_MMR6 }, |
| 15468 | { SDC164, SDC164, SDC1_D64_MMR6 }, |
| 15469 | { SDC2, SDC2, SDC2_MMR6 }, |
| 15470 | { SEB, SEB, (uint16_t)-1U }, |
| 15471 | { SEH, SEH, (uint16_t)-1U }, |
| 15472 | { SSNOP, SSNOP, SSNOP_MMR6 }, |
| 15473 | { SUB, SUB, SUB_MMR6 }, |
| 15474 | { SUBu, SUBu, SUBU_MMR6 }, |
| 15475 | { SW, SW, SW_MMR6 }, |
| 15476 | { SWC2, SWC2, SWC2_MMR6 }, |
| 15477 | { SYNC, SYNC, SYNC_MMR6 }, |
| 15478 | { SYNCI, SYNCI, SYNCI_MMR6 }, |
| 15479 | { TRUNC_W_D64, TRUNC_W_D64, TRUNC_W_D_MMR6 }, |
| 15480 | { TRUNC_W_S, TRUNC_W_S, TRUNC_W_S_MMR6 }, |
| 15481 | { WAIT, WAIT, WAIT_MMR6 }, |
| 15482 | { XOR, XOR, XOR_MMR6 }, |
| 15483 | { XORi, XORi, XORI_MMR6 }, |
| 15484 | }; // End of Table |
| 15485 | |
| 15486 | unsigned mid; |
| 15487 | unsigned start = 0; |
| 15488 | unsigned end = 51; |
| 15489 | while (start < end) { |
| 15490 | mid = start + (end - start) / 2; |
| 15491 | if (Opcode == Table[mid][0]) |
| 15492 | break; |
| 15493 | if (Opcode < Table[mid][0]) |
| 15494 | end = mid; |
| 15495 | else |
| 15496 | start = mid + 1; |
| 15497 | } |
| 15498 | if (start == end) |
| 15499 | return -1; // Instruction doesn't exist in this table. |
| 15500 | |
| 15501 | if (inArch == Arch_se) |
| 15502 | return Table[mid][1]; |
| 15503 | if (inArch == Arch_micromipsr6) |
| 15504 | return Table[mid][2]; |
| 15505 | return -1;} |
| 15506 | |
| 15507 | |
| 15508 | } // namespace llvm::Mips |
| 15509 | |
| 15510 | #endif // GET_INSTRMAP_INFO |
| 15511 | |
| 15512 |
Generated while processing llvm_projects/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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