1//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
14#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
15
16#include "llvm/Support/DataTypes.h"
17
18#include <memory>
19
20namespace llvm {
21class MCAsmBackend;
22class MCCodeEmitter;
23class MCContext;
24class MCInstrInfo;
25class MCObjectTargetWriter;
26class MCObjectWriter;
27class MCRegister;
28class MCRegisterInfo;
29class MCStreamer;
30class MCSubtargetInfo;
31class MCTargetOptions;
32class StringRef;
33class Target;
34class Triple;
35
36MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 MCContext &Ctx);
38MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
39 MCContext &Ctx);
40
41MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
42 const MCRegisterInfo &MRI,
43 const MCTargetOptions &Options);
44
45/// Construct an MIPS Windows COFF machine code streamer which will generate
46/// PE/COFF format object files.
47///
48/// Takes ownership of \p AB and \p CE.
49MCStreamer *createMipsWinCOFFStreamer(MCContext &C,
50 std::unique_ptr<MCAsmBackend> &&AB,
51 std::unique_ptr<MCObjectWriter> &&OW,
52 std::unique_ptr<MCCodeEmitter> &&CE);
53
54/// Construct a Mips ELF object writer.
55std::unique_ptr<MCObjectTargetWriter>
56createMipsELFObjectWriter(const Triple &TT, bool IsN32);
57/// Construct a Mips Win COFF object writer.
58std::unique_ptr<MCObjectTargetWriter> createMipsWinCOFFObjectWriter();
59
60namespace MIPS_MC {
61void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
62
63StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
64
65/// Match a symbolic name in RegClassID, or return an invalid register.
66MCRegister matchRegisterName(StringRef Name, const MCRegisterInfo &MRI,
67 unsigned RegClassID, unsigned AltIdx);
68
69/// Return a GPR name's hardware index, or -1 if unknown.
70int getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
71 unsigned AltIdx, bool *IsDeprecated = nullptr);
72}
73
74} // End llvm namespace
75
76// Defines symbolic names for Mips registers. This defines a mapping from
77// register name to register number.
78#define GET_REGINFO_ENUM
79#include "MipsGenRegisterInfo.inc"
80
81// Defines symbolic names for the Mips instructions.
82#define GET_INSTRINFO_ENUM
83#define GET_INSTRINFO_MC_HELPER_DECLS
84#include "MipsGenInstrInfo.inc"
85
86#define GET_SUBTARGETINFO_ENUM
87#include "MipsGenSubtargetInfo.inc"
88
89#endif
90