1//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
14#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
15
16#include "llvm/MC/MCRegister.h"
17#include "llvm/Support/DataTypes.h"
18
19#include <memory>
20
21namespace llvm {
22class MCAsmBackend;
23class MCCodeEmitter;
24class MCContext;
25class MCInstrInfo;
26class MCObjectTargetWriter;
27class MCObjectWriter;
28class MCRegister;
29class MCRegisterInfo;
30class MCStreamer;
31class MCSubtargetInfo;
32class MCTargetOptions;
33class StringRef;
34class Target;
35class Triple;
36
37MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
38 MCContext &Ctx);
39MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
40 MCContext &Ctx);
41
42MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
43 const MCRegisterInfo &MRI,
44 const MCTargetOptions &Options);
45
46/// Construct an MIPS Windows COFF machine code streamer which will generate
47/// PE/COFF format object files.
48///
49/// Takes ownership of \p AB and \p CE.
50MCStreamer *createMipsWinCOFFStreamer(MCContext &C,
51 std::unique_ptr<MCAsmBackend> &&AB,
52 std::unique_ptr<MCObjectWriter> &&OW,
53 std::unique_ptr<MCCodeEmitter> &&CE);
54
55/// Construct a Mips ELF object writer.
56std::unique_ptr<MCObjectTargetWriter>
57createMipsELFObjectWriter(const Triple &TT, bool IsN32);
58/// Construct a Mips Win COFF object writer.
59std::unique_ptr<MCObjectTargetWriter> createMipsWinCOFFObjectWriter();
60
61namespace MIPS_MC {
62void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
63
64StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
65
66/// Match a symbolic name in RegClassID, or return an invalid register.
67MCRegister matchRegisterName(StringRef Name, const MCRegisterInfo &MRI,
68 unsigned RegClassID, unsigned AltIdx);
69
70/// Return a GPR name's hardware index, or -1 if unknown.
71int getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
72 unsigned AltIdx, bool *IsDeprecated = nullptr);
73}
74
75} // End llvm namespace
76
77// Defines symbolic names for Mips registers. This defines a mapping from
78// register name to register number.
79#define GET_REGINFO_ENUM
80#include "MipsGenRegisterInfo.inc"
81
82namespace llvm {
83namespace Mips {
84// Readable names for the GPRs with a dedicated role. Other GPRs use their R<n>
85// names, or the MipsABIInfo accessors when their role depends on the ABI.
86inline constexpr MCPhysReg GP = R28;
87inline constexpr MCPhysReg SP = R29;
88inline constexpr MCPhysReg FP = R30;
89inline constexpr MCPhysReg RA = R31;
90inline constexpr MCPhysReg GP_64 = R28_64;
91inline constexpr MCPhysReg SP_64 = R29_64;
92inline constexpr MCPhysReg FP_64 = R30_64;
93inline constexpr MCPhysReg RA_64 = R31_64;
94} // namespace Mips
95} // namespace llvm
96
97// Defines symbolic names for the Mips instructions.
98#define GET_INSTRINFO_ENUM
99#define GET_INSTRINFO_MC_HELPER_DECLS
100#include "MipsGenInstrInfo.inc"
101
102#define GET_SUBTARGETINFO_ENUM
103#include "MipsGenSubtargetInfo.inc"
104
105#endif
106