| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(2080375378), // ABSQ_S_PH |
| 14 | UINT64_C(4412), // ABSQ_S_PH_MM |
| 15 | UINT64_C(2080374866), // ABSQ_S_QB |
| 16 | UINT64_C(316), // ABSQ_S_QB_MMR2 |
| 17 | UINT64_C(2080375890), // ABSQ_S_W |
| 18 | UINT64_C(8508), // ABSQ_S_W_MM |
| 19 | UINT64_C(32), // ADD |
| 20 | UINT64_C(3959422976), // ADDIUPC |
| 21 | UINT64_C(2013265920), // ADDIUPC_MM |
| 22 | UINT64_C(2013265920), // ADDIUPC_MMR6 |
| 23 | UINT64_C(27649), // ADDIUR1SP_MM |
| 24 | UINT64_C(27648), // ADDIUR2_MM |
| 25 | UINT64_C(19456), // ADDIUS5_MM |
| 26 | UINT64_C(19457), // ADDIUSP_MM |
| 27 | UINT64_C(805306368), // ADDIU_MMR6 |
| 28 | UINT64_C(2080375320), // ADDQH_PH |
| 29 | UINT64_C(77), // ADDQH_PH_MMR2 |
| 30 | UINT64_C(2080375448), // ADDQH_R_PH |
| 31 | UINT64_C(1101), // ADDQH_R_PH_MMR2 |
| 32 | UINT64_C(2080375960), // ADDQH_R_W |
| 33 | UINT64_C(1165), // ADDQH_R_W_MMR2 |
| 34 | UINT64_C(2080375832), // ADDQH_W |
| 35 | UINT64_C(141), // ADDQH_W_MMR2 |
| 36 | UINT64_C(2080375440), // ADDQ_PH |
| 37 | UINT64_C(13), // ADDQ_PH_MM |
| 38 | UINT64_C(2080375696), // ADDQ_S_PH |
| 39 | UINT64_C(1037), // ADDQ_S_PH_MM |
| 40 | UINT64_C(2080376208), // ADDQ_S_W |
| 41 | UINT64_C(773), // ADDQ_S_W_MM |
| 42 | UINT64_C(1186988056), // ADDR_PS64 |
| 43 | UINT64_C(2080375824), // ADDSC |
| 44 | UINT64_C(901), // ADDSC_MM |
| 45 | UINT64_C(2021654544), // ADDS_A_B |
| 46 | UINT64_C(2027946000), // ADDS_A_D |
| 47 | UINT64_C(2023751696), // ADDS_A_H |
| 48 | UINT64_C(2025848848), // ADDS_A_W |
| 49 | UINT64_C(2030043152), // ADDS_S_B |
| 50 | UINT64_C(2036334608), // ADDS_S_D |
| 51 | UINT64_C(2032140304), // ADDS_S_H |
| 52 | UINT64_C(2034237456), // ADDS_S_W |
| 53 | UINT64_C(2038431760), // ADDS_U_B |
| 54 | UINT64_C(2044723216), // ADDS_U_D |
| 55 | UINT64_C(2040528912), // ADDS_U_H |
| 56 | UINT64_C(2042626064), // ADDS_U_W |
| 57 | UINT64_C(1024), // ADDU16_MM |
| 58 | UINT64_C(1024), // ADDU16_MMR6 |
| 59 | UINT64_C(2080374808), // ADDUH_QB |
| 60 | UINT64_C(333), // ADDUH_QB_MMR2 |
| 61 | UINT64_C(2080374936), // ADDUH_R_QB |
| 62 | UINT64_C(1357), // ADDUH_R_QB_MMR2 |
| 63 | UINT64_C(336), // ADDU_MMR6 |
| 64 | UINT64_C(2080375312), // ADDU_PH |
| 65 | UINT64_C(269), // ADDU_PH_MMR2 |
| 66 | UINT64_C(2080374800), // ADDU_QB |
| 67 | UINT64_C(205), // ADDU_QB_MM |
| 68 | UINT64_C(2080375568), // ADDU_S_PH |
| 69 | UINT64_C(1293), // ADDU_S_PH_MMR2 |
| 70 | UINT64_C(2080375056), // ADDU_S_QB |
| 71 | UINT64_C(1229), // ADDU_S_QB_MM |
| 72 | UINT64_C(2013265926), // ADDVI_B |
| 73 | UINT64_C(2019557382), // ADDVI_D |
| 74 | UINT64_C(2015363078), // ADDVI_H |
| 75 | UINT64_C(2017460230), // ADDVI_W |
| 76 | UINT64_C(2013265934), // ADDV_B |
| 77 | UINT64_C(2019557390), // ADDV_D |
| 78 | UINT64_C(2015363086), // ADDV_H |
| 79 | UINT64_C(2017460238), // ADDV_W |
| 80 | UINT64_C(2080375888), // ADDWC |
| 81 | UINT64_C(965), // ADDWC_MM |
| 82 | UINT64_C(2013265936), // ADD_A_B |
| 83 | UINT64_C(2019557392), // ADD_A_D |
| 84 | UINT64_C(2015363088), // ADD_A_H |
| 85 | UINT64_C(2017460240), // ADD_A_W |
| 86 | UINT64_C(272), // ADD_MM |
| 87 | UINT64_C(272), // ADD_MMR6 |
| 88 | UINT64_C(536870912), // ADDi |
| 89 | UINT64_C(268435456), // ADDi_MM |
| 90 | UINT64_C(603979776), // ADDiu |
| 91 | UINT64_C(805306368), // ADDiu_MM |
| 92 | UINT64_C(33), // ADDu |
| 93 | UINT64_C(336), // ADDu_MM |
| 94 | UINT64_C(2080375328), // ALIGN |
| 95 | UINT64_C(31), // ALIGN_MMR6 |
| 96 | UINT64_C(3961454592), // ALUIPC |
| 97 | UINT64_C(2015297536), // ALUIPC_MMR6 |
| 98 | UINT64_C(36), // AND |
| 99 | UINT64_C(17536), // AND16_MM |
| 100 | UINT64_C(17409), // AND16_MMR6 |
| 101 | UINT64_C(36), // AND64 |
| 102 | UINT64_C(11264), // ANDI16_MM |
| 103 | UINT64_C(11264), // ANDI16_MMR6 |
| 104 | UINT64_C(2013265920), // ANDI_B |
| 105 | UINT64_C(3489660928), // ANDI_MMR6 |
| 106 | UINT64_C(592), // AND_MM |
| 107 | UINT64_C(592), // AND_MMR6 |
| 108 | UINT64_C(2013265950), // AND_V |
| 109 | UINT64_C(805306368), // ANDi |
| 110 | UINT64_C(805306368), // ANDi64 |
| 111 | UINT64_C(3489660928), // ANDi_MM |
| 112 | UINT64_C(2080374833), // APPEND |
| 113 | UINT64_C(533), // APPEND_MMR2 |
| 114 | UINT64_C(2046820369), // ASUB_S_B |
| 115 | UINT64_C(2053111825), // ASUB_S_D |
| 116 | UINT64_C(2048917521), // ASUB_S_H |
| 117 | UINT64_C(2051014673), // ASUB_S_W |
| 118 | UINT64_C(2055208977), // ASUB_U_B |
| 119 | UINT64_C(2061500433), // ASUB_U_D |
| 120 | UINT64_C(2057306129), // ASUB_U_H |
| 121 | UINT64_C(2059403281), // ASUB_U_W |
| 122 | UINT64_C(1006632960), // AUI |
| 123 | UINT64_C(3961389056), // AUIPC |
| 124 | UINT64_C(2015232000), // AUIPC_MMR6 |
| 125 | UINT64_C(268435456), // AUI_MMR6 |
| 126 | UINT64_C(2063597584), // AVER_S_B |
| 127 | UINT64_C(2069889040), // AVER_S_D |
| 128 | UINT64_C(2065694736), // AVER_S_H |
| 129 | UINT64_C(2067791888), // AVER_S_W |
| 130 | UINT64_C(2071986192), // AVER_U_B |
| 131 | UINT64_C(2078277648), // AVER_U_D |
| 132 | UINT64_C(2074083344), // AVER_U_H |
| 133 | UINT64_C(2076180496), // AVER_U_W |
| 134 | UINT64_C(2046820368), // AVE_S_B |
| 135 | UINT64_C(2053111824), // AVE_S_D |
| 136 | UINT64_C(2048917520), // AVE_S_H |
| 137 | UINT64_C(2051014672), // AVE_S_W |
| 138 | UINT64_C(2055208976), // AVE_U_B |
| 139 | UINT64_C(2061500432), // AVE_U_D |
| 140 | UINT64_C(2057306128), // AVE_U_H |
| 141 | UINT64_C(2059403280), // AVE_U_W |
| 142 | UINT64_C(4026550272), // AddiuRxImmX16 |
| 143 | UINT64_C(4026533888), // AddiuRxPcImmX16 |
| 144 | UINT64_C(18432), // AddiuRxRxImm16 |
| 145 | UINT64_C(4026550272), // AddiuRxRxImmX16 |
| 146 | UINT64_C(4026548224), // AddiuRxRyOffMemX16 |
| 147 | UINT64_C(25344), // AddiuSpImm16 |
| 148 | UINT64_C(4026544896), // AddiuSpImmX16 |
| 149 | UINT64_C(57345), // AdduRxRyRz16 |
| 150 | UINT64_C(59404), // AndRxRxRy16 |
| 151 | UINT64_C(52224), // B16_MM |
| 152 | UINT64_C(1879048232), // BADDu |
| 153 | UINT64_C(68222976), // BAL |
| 154 | UINT64_C(3892314112), // BALC |
| 155 | UINT64_C(3019898880), // BALC_MMR6 |
| 156 | UINT64_C(2080375857), // BALIGN |
| 157 | UINT64_C(2236), // BALIGN_MMR2 |
| 158 | UINT64_C(3355443200), // BBIT0 |
| 159 | UINT64_C(3623878656), // BBIT032 |
| 160 | UINT64_C(3892314112), // BBIT1 |
| 161 | UINT64_C(4160749568), // BBIT132 |
| 162 | UINT64_C(3355443200), // BC |
| 163 | UINT64_C(52224), // BC16_MMR6 |
| 164 | UINT64_C(1159725056), // BC1EQZ |
| 165 | UINT64_C(1090519040), // BC1EQZC_MMR6 |
| 166 | UINT64_C(1157627904), // BC1F |
| 167 | UINT64_C(1157758976), // BC1FL |
| 168 | UINT64_C(1132462080), // BC1F_MM |
| 169 | UINT64_C(1168113664), // BC1NEZ |
| 170 | UINT64_C(1092616192), // BC1NEZC_MMR6 |
| 171 | UINT64_C(1157693440), // BC1T |
| 172 | UINT64_C(1157824512), // BC1TL |
| 173 | UINT64_C(1134559232), // BC1T_MM |
| 174 | UINT64_C(1226833920), // BC2EQZ |
| 175 | UINT64_C(1094713344), // BC2EQZC_MMR6 |
| 176 | UINT64_C(1235222528), // BC2NEZ |
| 177 | UINT64_C(1096810496), // BC2NEZC_MMR6 |
| 178 | UINT64_C(2045771785), // BCLRI_B |
| 179 | UINT64_C(2038431753), // BCLRI_D |
| 180 | UINT64_C(2044723209), // BCLRI_H |
| 181 | UINT64_C(2042626057), // BCLRI_W |
| 182 | UINT64_C(2038431757), // BCLR_B |
| 183 | UINT64_C(2044723213), // BCLR_D |
| 184 | UINT64_C(2040528909), // BCLR_H |
| 185 | UINT64_C(2042626061), // BCLR_W |
| 186 | UINT64_C(2483027968), // BC_MMR6 |
| 187 | UINT64_C(268435456), // BEQ |
| 188 | UINT64_C(268435456), // BEQ64 |
| 189 | UINT64_C(536870912), // BEQC |
| 190 | UINT64_C(536870912), // BEQC64 |
| 191 | UINT64_C(1946157056), // BEQC_MMR6 |
| 192 | UINT64_C(1342177280), // BEQL |
| 193 | UINT64_C(35840), // BEQZ16_MM |
| 194 | UINT64_C(536870912), // BEQZALC |
| 195 | UINT64_C(1946157056), // BEQZALC_MMR6 |
| 196 | UINT64_C(3623878656), // BEQZC |
| 197 | UINT64_C(35840), // BEQZC16_MMR6 |
| 198 | UINT64_C(3623878656), // BEQZC64 |
| 199 | UINT64_C(1088421888), // BEQZC_MM |
| 200 | UINT64_C(2147483648), // BEQZC_MMR6 |
| 201 | UINT64_C(2483027968), // BEQ_MM |
| 202 | UINT64_C(1476395008), // BGEC |
| 203 | UINT64_C(1476395008), // BGEC64 |
| 204 | UINT64_C(4093640704), // BGEC_MMR6 |
| 205 | UINT64_C(402653184), // BGEUC |
| 206 | UINT64_C(402653184), // BGEUC64 |
| 207 | UINT64_C(3221225472), // BGEUC_MMR6 |
| 208 | UINT64_C(67174400), // BGEZ |
| 209 | UINT64_C(67174400), // BGEZ64 |
| 210 | UINT64_C(68222976), // BGEZAL |
| 211 | UINT64_C(402653184), // BGEZALC |
| 212 | UINT64_C(3221225472), // BGEZALC_MMR6 |
| 213 | UINT64_C(68354048), // BGEZALL |
| 214 | UINT64_C(1113587712), // BGEZALS_MM |
| 215 | UINT64_C(1080033280), // BGEZAL_MM |
| 216 | UINT64_C(1476395008), // BGEZC |
| 217 | UINT64_C(1476395008), // BGEZC64 |
| 218 | UINT64_C(4093640704), // BGEZC_MMR6 |
| 219 | UINT64_C(67305472), // BGEZL |
| 220 | UINT64_C(1077936128), // BGEZ_MM |
| 221 | UINT64_C(469762048), // BGTZ |
| 222 | UINT64_C(469762048), // BGTZ64 |
| 223 | UINT64_C(469762048), // BGTZALC |
| 224 | UINT64_C(3758096384), // BGTZALC_MMR6 |
| 225 | UINT64_C(1543503872), // BGTZC |
| 226 | UINT64_C(1543503872), // BGTZC64 |
| 227 | UINT64_C(3556769792), // BGTZC_MMR6 |
| 228 | UINT64_C(1543503872), // BGTZL |
| 229 | UINT64_C(1086324736), // BGTZ_MM |
| 230 | UINT64_C(2070937609), // BINSLI_B |
| 231 | UINT64_C(2063597577), // BINSLI_D |
| 232 | UINT64_C(2069889033), // BINSLI_H |
| 233 | UINT64_C(2067791881), // BINSLI_W |
| 234 | UINT64_C(2063597581), // BINSL_B |
| 235 | UINT64_C(2069889037), // BINSL_D |
| 236 | UINT64_C(2065694733), // BINSL_H |
| 237 | UINT64_C(2067791885), // BINSL_W |
| 238 | UINT64_C(2079326217), // BINSRI_B |
| 239 | UINT64_C(2071986185), // BINSRI_D |
| 240 | UINT64_C(2078277641), // BINSRI_H |
| 241 | UINT64_C(2076180489), // BINSRI_W |
| 242 | UINT64_C(2071986189), // BINSR_B |
| 243 | UINT64_C(2078277645), // BINSR_D |
| 244 | UINT64_C(2074083341), // BINSR_H |
| 245 | UINT64_C(2076180493), // BINSR_W |
| 246 | UINT64_C(2080376530), // BITREV |
| 247 | UINT64_C(12604), // BITREV_MM |
| 248 | UINT64_C(2080374816), // BITSWAP |
| 249 | UINT64_C(2876), // BITSWAP_MMR6 |
| 250 | UINT64_C(402653184), // BLEZ |
| 251 | UINT64_C(402653184), // BLEZ64 |
| 252 | UINT64_C(402653184), // BLEZALC |
| 253 | UINT64_C(3221225472), // BLEZALC_MMR6 |
| 254 | UINT64_C(1476395008), // BLEZC |
| 255 | UINT64_C(1476395008), // BLEZC64 |
| 256 | UINT64_C(4093640704), // BLEZC_MMR6 |
| 257 | UINT64_C(1476395008), // BLEZL |
| 258 | UINT64_C(1082130432), // BLEZ_MM |
| 259 | UINT64_C(1543503872), // BLTC |
| 260 | UINT64_C(1543503872), // BLTC64 |
| 261 | UINT64_C(3556769792), // BLTC_MMR6 |
| 262 | UINT64_C(469762048), // BLTUC |
| 263 | UINT64_C(469762048), // BLTUC64 |
| 264 | UINT64_C(3758096384), // BLTUC_MMR6 |
| 265 | UINT64_C(67108864), // BLTZ |
| 266 | UINT64_C(67108864), // BLTZ64 |
| 267 | UINT64_C(68157440), // BLTZAL |
| 268 | UINT64_C(469762048), // BLTZALC |
| 269 | UINT64_C(3758096384), // BLTZALC_MMR6 |
| 270 | UINT64_C(68288512), // BLTZALL |
| 271 | UINT64_C(1109393408), // BLTZALS_MM |
| 272 | UINT64_C(1075838976), // BLTZAL_MM |
| 273 | UINT64_C(1543503872), // BLTZC |
| 274 | UINT64_C(1543503872), // BLTZC64 |
| 275 | UINT64_C(3556769792), // BLTZC_MMR6 |
| 276 | UINT64_C(67239936), // BLTZL |
| 277 | UINT64_C(1073741824), // BLTZ_MM |
| 278 | UINT64_C(2013265921), // BMNZI_B |
| 279 | UINT64_C(2021654558), // BMNZ_V |
| 280 | UINT64_C(2030043137), // BMZI_B |
| 281 | UINT64_C(2023751710), // BMZ_V |
| 282 | UINT64_C(335544320), // BNE |
| 283 | UINT64_C(335544320), // BNE64 |
| 284 | UINT64_C(1610612736), // BNEC |
| 285 | UINT64_C(1610612736), // BNEC64 |
| 286 | UINT64_C(2080374784), // BNEC_MMR6 |
| 287 | UINT64_C(2062549001), // BNEGI_B |
| 288 | UINT64_C(2055208969), // BNEGI_D |
| 289 | UINT64_C(2061500425), // BNEGI_H |
| 290 | UINT64_C(2059403273), // BNEGI_W |
| 291 | UINT64_C(2055208973), // BNEG_B |
| 292 | UINT64_C(2061500429), // BNEG_D |
| 293 | UINT64_C(2057306125), // BNEG_H |
| 294 | UINT64_C(2059403277), // BNEG_W |
| 295 | UINT64_C(1409286144), // BNEL |
| 296 | UINT64_C(44032), // BNEZ16_MM |
| 297 | UINT64_C(1610612736), // BNEZALC |
| 298 | UINT64_C(2080374784), // BNEZALC_MMR6 |
| 299 | UINT64_C(4160749568), // BNEZC |
| 300 | UINT64_C(44032), // BNEZC16_MMR6 |
| 301 | UINT64_C(4160749568), // BNEZC64 |
| 302 | UINT64_C(1084227584), // BNEZC_MM |
| 303 | UINT64_C(2684354560), // BNEZC_MMR6 |
| 304 | UINT64_C(3019898880), // BNE_MM |
| 305 | UINT64_C(1610612736), // BNVC |
| 306 | UINT64_C(2080374784), // BNVC_MMR6 |
| 307 | UINT64_C(1199570944), // BNZ_B |
| 308 | UINT64_C(1205862400), // BNZ_D |
| 309 | UINT64_C(1201668096), // BNZ_H |
| 310 | UINT64_C(1172307968), // BNZ_V |
| 311 | UINT64_C(1203765248), // BNZ_W |
| 312 | UINT64_C(536870912), // BOVC |
| 313 | UINT64_C(1946157056), // BOVC_MMR6 |
| 314 | UINT64_C(68943872), // BPOSGE32 |
| 315 | UINT64_C(1126170624), // BPOSGE32C_MMR3 |
| 316 | UINT64_C(1130364928), // BPOSGE32_MM |
| 317 | UINT64_C(13), // BREAK |
| 318 | UINT64_C(18048), // BREAK16_MM |
| 319 | UINT64_C(17435), // BREAK16_MMR6 |
| 320 | UINT64_C(7), // BREAK_MM |
| 321 | UINT64_C(7), // BREAK_MMR6 |
| 322 | UINT64_C(2046820353), // BSELI_B |
| 323 | UINT64_C(2025848862), // BSEL_V |
| 324 | UINT64_C(2054160393), // BSETI_B |
| 325 | UINT64_C(2046820361), // BSETI_D |
| 326 | UINT64_C(2053111817), // BSETI_H |
| 327 | UINT64_C(2051014665), // BSETI_W |
| 328 | UINT64_C(2046820365), // BSET_B |
| 329 | UINT64_C(2053111821), // BSET_D |
| 330 | UINT64_C(2048917517), // BSET_H |
| 331 | UINT64_C(2051014669), // BSET_W |
| 332 | UINT64_C(1191182336), // BZ_B |
| 333 | UINT64_C(1197473792), // BZ_D |
| 334 | UINT64_C(1193279488), // BZ_H |
| 335 | UINT64_C(1163919360), // BZ_V |
| 336 | UINT64_C(1195376640), // BZ_W |
| 337 | UINT64_C(8192), // BeqzRxImm16 |
| 338 | UINT64_C(4026540032), // BeqzRxImmX16 |
| 339 | UINT64_C(4096), // Bimm16 |
| 340 | UINT64_C(4026535936), // BimmX16 |
| 341 | UINT64_C(10240), // BnezRxImm16 |
| 342 | UINT64_C(4026542080), // BnezRxImmX16 |
| 343 | UINT64_C(59397), // Break16 |
| 344 | UINT64_C(24576), // Bteqz16 |
| 345 | UINT64_C(4026544128), // BteqzX16 |
| 346 | UINT64_C(24832), // Btnez16 |
| 347 | UINT64_C(4026544384), // BtnezX16 |
| 348 | UINT64_C(3154116608), // CACHE |
| 349 | UINT64_C(2080374811), // CACHEE |
| 350 | UINT64_C(1610655232), // CACHEE_MM |
| 351 | UINT64_C(536895488), // CACHE_MM |
| 352 | UINT64_C(536895488), // CACHE_MMR6 |
| 353 | UINT64_C(2080374821), // CACHE_R6 |
| 354 | UINT64_C(1176502282), // CEIL_L_D64 |
| 355 | UINT64_C(1409307451), // CEIL_L_D_MMR6 |
| 356 | UINT64_C(1174405130), // CEIL_L_S |
| 357 | UINT64_C(1409291067), // CEIL_L_S_MMR6 |
| 358 | UINT64_C(1176502286), // CEIL_W_D32 |
| 359 | UINT64_C(1176502286), // CEIL_W_D64 |
| 360 | UINT64_C(1409309499), // CEIL_W_D_MMR6 |
| 361 | UINT64_C(1409309499), // CEIL_W_MM |
| 362 | UINT64_C(1174405134), // CEIL_W_S |
| 363 | UINT64_C(1409293115), // CEIL_W_S_MM |
| 364 | UINT64_C(1409293115), // CEIL_W_S_MMR6 |
| 365 | UINT64_C(2013265927), // CEQI_B |
| 366 | UINT64_C(2019557383), // CEQI_D |
| 367 | UINT64_C(2015363079), // CEQI_H |
| 368 | UINT64_C(2017460231), // CEQI_W |
| 369 | UINT64_C(2013265935), // CEQ_B |
| 370 | UINT64_C(2019557391), // CEQ_D |
| 371 | UINT64_C(2015363087), // CEQ_H |
| 372 | UINT64_C(2017460239), // CEQ_W |
| 373 | UINT64_C(1145044992), // CFC1 |
| 374 | UINT64_C(1409290299), // CFC1_MM |
| 375 | UINT64_C(52540), // CFC2_MM |
| 376 | UINT64_C(2021523481), // CFCMSA |
| 377 | UINT64_C(1879048242), // CINS |
| 378 | UINT64_C(1879048243), // CINS32 |
| 379 | UINT64_C(1879048242), // CINS64_32 |
| 380 | UINT64_C(1879048242), // CINS_i32 |
| 381 | UINT64_C(1176502299), // CLASS_D |
| 382 | UINT64_C(1409286752), // CLASS_D_MMR6 |
| 383 | UINT64_C(1174405147), // CLASS_S |
| 384 | UINT64_C(1409286240), // CLASS_S_MMR6 |
| 385 | UINT64_C(2046820359), // CLEI_S_B |
| 386 | UINT64_C(2053111815), // CLEI_S_D |
| 387 | UINT64_C(2048917511), // CLEI_S_H |
| 388 | UINT64_C(2051014663), // CLEI_S_W |
| 389 | UINT64_C(2055208967), // CLEI_U_B |
| 390 | UINT64_C(2061500423), // CLEI_U_D |
| 391 | UINT64_C(2057306119), // CLEI_U_H |
| 392 | UINT64_C(2059403271), // CLEI_U_W |
| 393 | UINT64_C(2046820367), // CLE_S_B |
| 394 | UINT64_C(2053111823), // CLE_S_D |
| 395 | UINT64_C(2048917519), // CLE_S_H |
| 396 | UINT64_C(2051014671), // CLE_S_W |
| 397 | UINT64_C(2055208975), // CLE_U_B |
| 398 | UINT64_C(2061500431), // CLE_U_D |
| 399 | UINT64_C(2057306127), // CLE_U_H |
| 400 | UINT64_C(2059403279), // CLE_U_W |
| 401 | UINT64_C(1879048225), // CLO |
| 402 | UINT64_C(19260), // CLO_MM |
| 403 | UINT64_C(19260), // CLO_MMR6 |
| 404 | UINT64_C(81), // CLO_R6 |
| 405 | UINT64_C(2030043143), // CLTI_S_B |
| 406 | UINT64_C(2036334599), // CLTI_S_D |
| 407 | UINT64_C(2032140295), // CLTI_S_H |
| 408 | UINT64_C(2034237447), // CLTI_S_W |
| 409 | UINT64_C(2038431751), // CLTI_U_B |
| 410 | UINT64_C(2044723207), // CLTI_U_D |
| 411 | UINT64_C(2040528903), // CLTI_U_H |
| 412 | UINT64_C(2042626055), // CLTI_U_W |
| 413 | UINT64_C(2030043151), // CLT_S_B |
| 414 | UINT64_C(2036334607), // CLT_S_D |
| 415 | UINT64_C(2032140303), // CLT_S_H |
| 416 | UINT64_C(2034237455), // CLT_S_W |
| 417 | UINT64_C(2038431759), // CLT_U_B |
| 418 | UINT64_C(2044723215), // CLT_U_D |
| 419 | UINT64_C(2040528911), // CLT_U_H |
| 420 | UINT64_C(2042626063), // CLT_U_W |
| 421 | UINT64_C(1879048224), // CLZ |
| 422 | UINT64_C(23356), // CLZ_MM |
| 423 | UINT64_C(80), // CLZ_MMR6 |
| 424 | UINT64_C(80), // CLZ_R6 |
| 425 | UINT64_C(2080376337), // CMPGDU_EQ_QB |
| 426 | UINT64_C(389), // CMPGDU_EQ_QB_MMR2 |
| 427 | UINT64_C(2080376465), // CMPGDU_LE_QB |
| 428 | UINT64_C(517), // CMPGDU_LE_QB_MMR2 |
| 429 | UINT64_C(2080376401), // CMPGDU_LT_QB |
| 430 | UINT64_C(453), // CMPGDU_LT_QB_MMR2 |
| 431 | UINT64_C(2080375057), // CMPGU_EQ_QB |
| 432 | UINT64_C(1476395205), // CMPGU_EQ_QB_MM |
| 433 | UINT64_C(2080375185), // CMPGU_LE_QB |
| 434 | UINT64_C(1476395333), // CMPGU_LE_QB_MM |
| 435 | UINT64_C(2080375121), // CMPGU_LT_QB |
| 436 | UINT64_C(1476395269), // CMPGU_LT_QB_MM |
| 437 | UINT64_C(2080374801), // CMPU_EQ_QB |
| 438 | UINT64_C(581), // CMPU_EQ_QB_MM |
| 439 | UINT64_C(2080374929), // CMPU_LE_QB |
| 440 | UINT64_C(709), // CMPU_LE_QB_MM |
| 441 | UINT64_C(2080374865), // CMPU_LT_QB |
| 442 | UINT64_C(645), // CMPU_LT_QB_MM |
| 443 | UINT64_C(1409286165), // CMP_AF_D_MMR6 |
| 444 | UINT64_C(1409286149), // CMP_AF_S_MMR6 |
| 445 | UINT64_C(1184890882), // CMP_EQ_D |
| 446 | UINT64_C(1409286293), // CMP_EQ_D_MMR6 |
| 447 | UINT64_C(2080375313), // CMP_EQ_PH |
| 448 | UINT64_C(5), // CMP_EQ_PH_MM |
| 449 | UINT64_C(1182793730), // CMP_EQ_S |
| 450 | UINT64_C(1409286277), // CMP_EQ_S_MMR6 |
| 451 | UINT64_C(1184890880), // CMP_F_D |
| 452 | UINT64_C(1182793728), // CMP_F_S |
| 453 | UINT64_C(1184890886), // CMP_LE_D |
| 454 | UINT64_C(1409286549), // CMP_LE_D_MMR6 |
| 455 | UINT64_C(2080375441), // CMP_LE_PH |
| 456 | UINT64_C(133), // CMP_LE_PH_MM |
| 457 | UINT64_C(1182793734), // CMP_LE_S |
| 458 | UINT64_C(1409286533), // CMP_LE_S_MMR6 |
| 459 | UINT64_C(1184890884), // CMP_LT_D |
| 460 | UINT64_C(1409286421), // CMP_LT_D_MMR6 |
| 461 | UINT64_C(2080375377), // CMP_LT_PH |
| 462 | UINT64_C(69), // CMP_LT_PH_MM |
| 463 | UINT64_C(1182793732), // CMP_LT_S |
| 464 | UINT64_C(1409286405), // CMP_LT_S_MMR6 |
| 465 | UINT64_C(1184890888), // CMP_SAF_D |
| 466 | UINT64_C(1409286677), // CMP_SAF_D_MMR6 |
| 467 | UINT64_C(1182793736), // CMP_SAF_S |
| 468 | UINT64_C(1409286661), // CMP_SAF_S_MMR6 |
| 469 | UINT64_C(1184890890), // CMP_SEQ_D |
| 470 | UINT64_C(1409286805), // CMP_SEQ_D_MMR6 |
| 471 | UINT64_C(1182793738), // CMP_SEQ_S |
| 472 | UINT64_C(1409286789), // CMP_SEQ_S_MMR6 |
| 473 | UINT64_C(1184890894), // CMP_SLE_D |
| 474 | UINT64_C(1409287061), // CMP_SLE_D_MMR6 |
| 475 | UINT64_C(1182793742), // CMP_SLE_S |
| 476 | UINT64_C(1409287045), // CMP_SLE_S_MMR6 |
| 477 | UINT64_C(1184890892), // CMP_SLT_D |
| 478 | UINT64_C(1409286933), // CMP_SLT_D_MMR6 |
| 479 | UINT64_C(1182793740), // CMP_SLT_S |
| 480 | UINT64_C(1409286917), // CMP_SLT_S_MMR6 |
| 481 | UINT64_C(1184890891), // CMP_SUEQ_D |
| 482 | UINT64_C(1409286869), // CMP_SUEQ_D_MMR6 |
| 483 | UINT64_C(1182793739), // CMP_SUEQ_S |
| 484 | UINT64_C(1409286853), // CMP_SUEQ_S_MMR6 |
| 485 | UINT64_C(1184890895), // CMP_SULE_D |
| 486 | UINT64_C(1409287125), // CMP_SULE_D_MMR6 |
| 487 | UINT64_C(1182793743), // CMP_SULE_S |
| 488 | UINT64_C(1409287109), // CMP_SULE_S_MMR6 |
| 489 | UINT64_C(1184890893), // CMP_SULT_D |
| 490 | UINT64_C(1409286997), // CMP_SULT_D_MMR6 |
| 491 | UINT64_C(1182793741), // CMP_SULT_S |
| 492 | UINT64_C(1409286981), // CMP_SULT_S_MMR6 |
| 493 | UINT64_C(1184890889), // CMP_SUN_D |
| 494 | UINT64_C(1409286741), // CMP_SUN_D_MMR6 |
| 495 | UINT64_C(1182793737), // CMP_SUN_S |
| 496 | UINT64_C(1409286725), // CMP_SUN_S_MMR6 |
| 497 | UINT64_C(1184890883), // CMP_UEQ_D |
| 498 | UINT64_C(1409286357), // CMP_UEQ_D_MMR6 |
| 499 | UINT64_C(1182793731), // CMP_UEQ_S |
| 500 | UINT64_C(1409286341), // CMP_UEQ_S_MMR6 |
| 501 | UINT64_C(1184890887), // CMP_ULE_D |
| 502 | UINT64_C(1409286613), // CMP_ULE_D_MMR6 |
| 503 | UINT64_C(1182793735), // CMP_ULE_S |
| 504 | UINT64_C(1409286597), // CMP_ULE_S_MMR6 |
| 505 | UINT64_C(1184890885), // CMP_ULT_D |
| 506 | UINT64_C(1409286485), // CMP_ULT_D_MMR6 |
| 507 | UINT64_C(1182793733), // CMP_ULT_S |
| 508 | UINT64_C(1409286469), // CMP_ULT_S_MMR6 |
| 509 | UINT64_C(1184890881), // CMP_UN_D |
| 510 | UINT64_C(1409286229), // CMP_UN_D_MMR6 |
| 511 | UINT64_C(1182793729), // CMP_UN_S |
| 512 | UINT64_C(1409286213), // CMP_UN_S_MMR6 |
| 513 | UINT64_C(2021654553), // COPY_S_B |
| 514 | UINT64_C(2025324569), // COPY_S_D |
| 515 | UINT64_C(2023751705), // COPY_S_H |
| 516 | UINT64_C(2024800281), // COPY_S_W |
| 517 | UINT64_C(2025848857), // COPY_U_B |
| 518 | UINT64_C(2027946009), // COPY_U_H |
| 519 | UINT64_C(2028994585), // COPY_U_W |
| 520 | UINT64_C(2080374799), // CRC32B |
| 521 | UINT64_C(2080375055), // CRC32CB |
| 522 | UINT64_C(2080375247), // CRC32CD |
| 523 | UINT64_C(2080375119), // CRC32CH |
| 524 | UINT64_C(2080375183), // CRC32CW |
| 525 | UINT64_C(2080374991), // CRC32D |
| 526 | UINT64_C(2080374863), // CRC32H |
| 527 | UINT64_C(2080374927), // CRC32W |
| 528 | UINT64_C(1153433600), // CTC1 |
| 529 | UINT64_C(1409292347), // CTC1_MM |
| 530 | UINT64_C(56636), // CTC2_MM |
| 531 | UINT64_C(2017329177), // CTCMSA |
| 532 | UINT64_C(1174405153), // CVT_D32_S |
| 533 | UINT64_C(1409291131), // CVT_D32_S_MM |
| 534 | UINT64_C(1182793761), // CVT_D32_W |
| 535 | UINT64_C(1409299323), // CVT_D32_W_MM |
| 536 | UINT64_C(1184890913), // CVT_D64_L |
| 537 | UINT64_C(1174405153), // CVT_D64_S |
| 538 | UINT64_C(1409291131), // CVT_D64_S_MM |
| 539 | UINT64_C(1182793761), // CVT_D64_W |
| 540 | UINT64_C(1409299323), // CVT_D64_W_MM |
| 541 | UINT64_C(1409307515), // CVT_D_L_MMR6 |
| 542 | UINT64_C(1176502309), // CVT_L_D64 |
| 543 | UINT64_C(1409302843), // CVT_L_D64_MM |
| 544 | UINT64_C(1409302843), // CVT_L_D_MMR6 |
| 545 | UINT64_C(1174405157), // CVT_L_S |
| 546 | UINT64_C(1409286459), // CVT_L_S_MM |
| 547 | UINT64_C(1409286459), // CVT_L_S_MMR6 |
| 548 | UINT64_C(1182793766), // CVT_PS_PW64 |
| 549 | UINT64_C(1174405158), // CVT_PS_S64 |
| 550 | UINT64_C(1186988068), // CVT_PW_PS64 |
| 551 | UINT64_C(1176502304), // CVT_S_D32 |
| 552 | UINT64_C(1409293179), // CVT_S_D32_MM |
| 553 | UINT64_C(1176502304), // CVT_S_D64 |
| 554 | UINT64_C(1409293179), // CVT_S_D64_MM |
| 555 | UINT64_C(1184890912), // CVT_S_L |
| 556 | UINT64_C(1409309563), // CVT_S_L_MMR6 |
| 557 | UINT64_C(1186988072), // CVT_S_PL64 |
| 558 | UINT64_C(1186988064), // CVT_S_PU64 |
| 559 | UINT64_C(1182793760), // CVT_S_W |
| 560 | UINT64_C(1409301371), // CVT_S_W_MM |
| 561 | UINT64_C(1409301371), // CVT_S_W_MMR6 |
| 562 | UINT64_C(1176502308), // CVT_W_D32 |
| 563 | UINT64_C(1409304891), // CVT_W_D32_MM |
| 564 | UINT64_C(1176502308), // CVT_W_D64 |
| 565 | UINT64_C(1409304891), // CVT_W_D64_MM |
| 566 | UINT64_C(1174405156), // CVT_W_S |
| 567 | UINT64_C(1409288507), // CVT_W_S_MM |
| 568 | UINT64_C(1409288507), // CVT_W_S_MMR6 |
| 569 | UINT64_C(1176502322), // C_EQ_D32 |
| 570 | UINT64_C(1409287356), // C_EQ_D32_MM |
| 571 | UINT64_C(1176502322), // C_EQ_D64 |
| 572 | UINT64_C(1409287356), // C_EQ_D64_MM |
| 573 | UINT64_C(1174405170), // C_EQ_S |
| 574 | UINT64_C(1409286332), // C_EQ_S_MM |
| 575 | UINT64_C(1176502320), // C_F_D32 |
| 576 | UINT64_C(1409287228), // C_F_D32_MM |
| 577 | UINT64_C(1176502320), // C_F_D64 |
| 578 | UINT64_C(1409287228), // C_F_D64_MM |
| 579 | UINT64_C(1174405168), // C_F_S |
| 580 | UINT64_C(1409286204), // C_F_S_MM |
| 581 | UINT64_C(1176502334), // C_LE_D32 |
| 582 | UINT64_C(1409288124), // C_LE_D32_MM |
| 583 | UINT64_C(1176502334), // C_LE_D64 |
| 584 | UINT64_C(1409288124), // C_LE_D64_MM |
| 585 | UINT64_C(1174405182), // C_LE_S |
| 586 | UINT64_C(1409287100), // C_LE_S_MM |
| 587 | UINT64_C(1176502332), // C_LT_D32 |
| 588 | UINT64_C(1409287996), // C_LT_D32_MM |
| 589 | UINT64_C(1176502332), // C_LT_D64 |
| 590 | UINT64_C(1409287996), // C_LT_D64_MM |
| 591 | UINT64_C(1174405180), // C_LT_S |
| 592 | UINT64_C(1409286972), // C_LT_S_MM |
| 593 | UINT64_C(1176502333), // C_NGE_D32 |
| 594 | UINT64_C(1409288060), // C_NGE_D32_MM |
| 595 | UINT64_C(1176502333), // C_NGE_D64 |
| 596 | UINT64_C(1409288060), // C_NGE_D64_MM |
| 597 | UINT64_C(1174405181), // C_NGE_S |
| 598 | UINT64_C(1409287036), // C_NGE_S_MM |
| 599 | UINT64_C(1176502329), // C_NGLE_D32 |
| 600 | UINT64_C(1409287804), // C_NGLE_D32_MM |
| 601 | UINT64_C(1176502329), // C_NGLE_D64 |
| 602 | UINT64_C(1409287804), // C_NGLE_D64_MM |
| 603 | UINT64_C(1174405177), // C_NGLE_S |
| 604 | UINT64_C(1409286780), // C_NGLE_S_MM |
| 605 | UINT64_C(1176502331), // C_NGL_D32 |
| 606 | UINT64_C(1409287932), // C_NGL_D32_MM |
| 607 | UINT64_C(1176502331), // C_NGL_D64 |
| 608 | UINT64_C(1409287932), // C_NGL_D64_MM |
| 609 | UINT64_C(1174405179), // C_NGL_S |
| 610 | UINT64_C(1409286908), // C_NGL_S_MM |
| 611 | UINT64_C(1176502335), // C_NGT_D32 |
| 612 | UINT64_C(1409288188), // C_NGT_D32_MM |
| 613 | UINT64_C(1176502335), // C_NGT_D64 |
| 614 | UINT64_C(1409288188), // C_NGT_D64_MM |
| 615 | UINT64_C(1174405183), // C_NGT_S |
| 616 | UINT64_C(1409287164), // C_NGT_S_MM |
| 617 | UINT64_C(1176502326), // C_OLE_D32 |
| 618 | UINT64_C(1409287612), // C_OLE_D32_MM |
| 619 | UINT64_C(1176502326), // C_OLE_D64 |
| 620 | UINT64_C(1409287612), // C_OLE_D64_MM |
| 621 | UINT64_C(1174405174), // C_OLE_S |
| 622 | UINT64_C(1409286588), // C_OLE_S_MM |
| 623 | UINT64_C(1176502324), // C_OLT_D32 |
| 624 | UINT64_C(1409287484), // C_OLT_D32_MM |
| 625 | UINT64_C(1176502324), // C_OLT_D64 |
| 626 | UINT64_C(1409287484), // C_OLT_D64_MM |
| 627 | UINT64_C(1174405172), // C_OLT_S |
| 628 | UINT64_C(1409286460), // C_OLT_S_MM |
| 629 | UINT64_C(1176502330), // C_SEQ_D32 |
| 630 | UINT64_C(1409287868), // C_SEQ_D32_MM |
| 631 | UINT64_C(1176502330), // C_SEQ_D64 |
| 632 | UINT64_C(1409287868), // C_SEQ_D64_MM |
| 633 | UINT64_C(1174405178), // C_SEQ_S |
| 634 | UINT64_C(1409286844), // C_SEQ_S_MM |
| 635 | UINT64_C(1176502328), // C_SF_D32 |
| 636 | UINT64_C(1409287740), // C_SF_D32_MM |
| 637 | UINT64_C(1176502328), // C_SF_D64 |
| 638 | UINT64_C(1409287740), // C_SF_D64_MM |
| 639 | UINT64_C(1174405176), // C_SF_S |
| 640 | UINT64_C(1409286716), // C_SF_S_MM |
| 641 | UINT64_C(1176502323), // C_UEQ_D32 |
| 642 | UINT64_C(1409287420), // C_UEQ_D32_MM |
| 643 | UINT64_C(1176502323), // C_UEQ_D64 |
| 644 | UINT64_C(1409287420), // C_UEQ_D64_MM |
| 645 | UINT64_C(1174405171), // C_UEQ_S |
| 646 | UINT64_C(1409286396), // C_UEQ_S_MM |
| 647 | UINT64_C(1176502327), // C_ULE_D32 |
| 648 | UINT64_C(1409287676), // C_ULE_D32_MM |
| 649 | UINT64_C(1176502327), // C_ULE_D64 |
| 650 | UINT64_C(1409287676), // C_ULE_D64_MM |
| 651 | UINT64_C(1174405175), // C_ULE_S |
| 652 | UINT64_C(1409286652), // C_ULE_S_MM |
| 653 | UINT64_C(1176502325), // C_ULT_D32 |
| 654 | UINT64_C(1409287548), // C_ULT_D32_MM |
| 655 | UINT64_C(1176502325), // C_ULT_D64 |
| 656 | UINT64_C(1409287548), // C_ULT_D64_MM |
| 657 | UINT64_C(1174405173), // C_ULT_S |
| 658 | UINT64_C(1409286524), // C_ULT_S_MM |
| 659 | UINT64_C(1176502321), // C_UN_D32 |
| 660 | UINT64_C(1409287292), // C_UN_D32_MM |
| 661 | UINT64_C(1176502321), // C_UN_D64 |
| 662 | UINT64_C(1409287292), // C_UN_D64_MM |
| 663 | UINT64_C(1174405169), // C_UN_S |
| 664 | UINT64_C(1409286268), // C_UN_S_MM |
| 665 | UINT64_C(59402), // CmpRxRy16 |
| 666 | UINT64_C(28672), // CmpiRxImm16 |
| 667 | UINT64_C(4026560512), // CmpiRxImmX16 |
| 668 | UINT64_C(44), // DADD |
| 669 | UINT64_C(1610612736), // DADDi |
| 670 | UINT64_C(1677721600), // DADDiu |
| 671 | UINT64_C(45), // DADDu |
| 672 | UINT64_C(67502080), // DAHI |
| 673 | UINT64_C(2080375332), // DALIGN |
| 674 | UINT64_C(69074944), // DATI |
| 675 | UINT64_C(1946157056), // DAUI |
| 676 | UINT64_C(2080374820), // DBITSWAP |
| 677 | UINT64_C(1879048229), // DCLO |
| 678 | UINT64_C(83), // DCLO_R6 |
| 679 | UINT64_C(1879048228), // DCLZ |
| 680 | UINT64_C(82), // DCLZ_R6 |
| 681 | UINT64_C(158), // DDIV |
| 682 | UINT64_C(159), // DDIVU |
| 683 | UINT64_C(1107296287), // DERET |
| 684 | UINT64_C(58236), // DERET_MM |
| 685 | UINT64_C(58236), // DERET_MMR6 |
| 686 | UINT64_C(2080374787), // DEXT |
| 687 | UINT64_C(2080374787), // DEXT64_32 |
| 688 | UINT64_C(2080374785), // DEXTM |
| 689 | UINT64_C(2080374786), // DEXTU |
| 690 | UINT64_C(1096835072), // DI |
| 691 | UINT64_C(2080374791), // DINS |
| 692 | UINT64_C(2080374789), // DINSM |
| 693 | UINT64_C(2080374790), // DINSU |
| 694 | UINT64_C(154), // DIV |
| 695 | UINT64_C(155), // DIVU |
| 696 | UINT64_C(408), // DIVU_MMR6 |
| 697 | UINT64_C(280), // DIV_MMR6 |
| 698 | UINT64_C(2046820370), // DIV_S_B |
| 699 | UINT64_C(2053111826), // DIV_S_D |
| 700 | UINT64_C(2048917522), // DIV_S_H |
| 701 | UINT64_C(2051014674), // DIV_S_W |
| 702 | UINT64_C(2055208978), // DIV_U_B |
| 703 | UINT64_C(2061500434), // DIV_U_D |
| 704 | UINT64_C(2057306130), // DIV_U_H |
| 705 | UINT64_C(2059403282), // DIV_U_W |
| 706 | UINT64_C(18300), // DI_MM |
| 707 | UINT64_C(18300), // DI_MMR6 |
| 708 | UINT64_C(21), // DLSA |
| 709 | UINT64_C(21), // DLSA_R6 |
| 710 | UINT64_C(1075838976), // DMFC0 |
| 711 | UINT64_C(1142947840), // DMFC1 |
| 712 | UINT64_C(1210056704), // DMFC2 |
| 713 | UINT64_C(1210056704), // DMFC2_OCTEON |
| 714 | UINT64_C(1080033536), // DMFGC0 |
| 715 | UINT64_C(222), // DMOD |
| 716 | UINT64_C(223), // DMODU |
| 717 | UINT64_C(1096813505), // DMT |
| 718 | UINT64_C(1084227584), // DMTC0 |
| 719 | UINT64_C(1151336448), // DMTC1 |
| 720 | UINT64_C(1218445312), // DMTC2 |
| 721 | UINT64_C(1218445312), // DMTC2_OCTEON |
| 722 | UINT64_C(1080034048), // DMTGC0 |
| 723 | UINT64_C(220), // DMUH |
| 724 | UINT64_C(221), // DMUHU |
| 725 | UINT64_C(1879048195), // DMUL |
| 726 | UINT64_C(28), // DMULT |
| 727 | UINT64_C(29), // DMULTu |
| 728 | UINT64_C(157), // DMULU |
| 729 | UINT64_C(156), // DMUL_R6 |
| 730 | UINT64_C(2019557395), // DOTP_S_D |
| 731 | UINT64_C(2015363091), // DOTP_S_H |
| 732 | UINT64_C(2017460243), // DOTP_S_W |
| 733 | UINT64_C(2027946003), // DOTP_U_D |
| 734 | UINT64_C(2023751699), // DOTP_U_H |
| 735 | UINT64_C(2025848851), // DOTP_U_W |
| 736 | UINT64_C(2036334611), // DPADD_S_D |
| 737 | UINT64_C(2032140307), // DPADD_S_H |
| 738 | UINT64_C(2034237459), // DPADD_S_W |
| 739 | UINT64_C(2044723219), // DPADD_U_D |
| 740 | UINT64_C(2040528915), // DPADD_U_H |
| 741 | UINT64_C(2042626067), // DPADD_U_W |
| 742 | UINT64_C(2080376496), // DPAQX_SA_W_PH |
| 743 | UINT64_C(12988), // DPAQX_SA_W_PH_MMR2 |
| 744 | UINT64_C(2080376368), // DPAQX_S_W_PH |
| 745 | UINT64_C(8892), // DPAQX_S_W_PH_MMR2 |
| 746 | UINT64_C(2080375600), // DPAQ_SA_L_W |
| 747 | UINT64_C(4796), // DPAQ_SA_L_W_MM |
| 748 | UINT64_C(2080375088), // DPAQ_S_W_PH |
| 749 | UINT64_C(700), // DPAQ_S_W_PH_MM |
| 750 | UINT64_C(2080375024), // DPAU_H_QBL |
| 751 | UINT64_C(8380), // DPAU_H_QBL_MM |
| 752 | UINT64_C(2080375280), // DPAU_H_QBR |
| 753 | UINT64_C(12476), // DPAU_H_QBR_MM |
| 754 | UINT64_C(2080375344), // DPAX_W_PH |
| 755 | UINT64_C(4284), // DPAX_W_PH_MMR2 |
| 756 | UINT64_C(2080374832), // DPA_W_PH |
| 757 | UINT64_C(188), // DPA_W_PH_MMR2 |
| 758 | UINT64_C(1879048237), // DPOP |
| 759 | UINT64_C(2080376560), // DPSQX_SA_W_PH |
| 760 | UINT64_C(14012), // DPSQX_SA_W_PH_MMR2 |
| 761 | UINT64_C(2080376432), // DPSQX_S_W_PH |
| 762 | UINT64_C(9916), // DPSQX_S_W_PH_MMR2 |
| 763 | UINT64_C(2080375664), // DPSQ_SA_L_W |
| 764 | UINT64_C(5820), // DPSQ_SA_L_W_MM |
| 765 | UINT64_C(2080375152), // DPSQ_S_W_PH |
| 766 | UINT64_C(1724), // DPSQ_S_W_PH_MM |
| 767 | UINT64_C(2053111827), // DPSUB_S_D |
| 768 | UINT64_C(2048917523), // DPSUB_S_H |
| 769 | UINT64_C(2051014675), // DPSUB_S_W |
| 770 | UINT64_C(2061500435), // DPSUB_U_D |
| 771 | UINT64_C(2057306131), // DPSUB_U_H |
| 772 | UINT64_C(2059403283), // DPSUB_U_W |
| 773 | UINT64_C(2080375536), // DPSU_H_QBL |
| 774 | UINT64_C(9404), // DPSU_H_QBL_MM |
| 775 | UINT64_C(2080375792), // DPSU_H_QBR |
| 776 | UINT64_C(13500), // DPSU_H_QBR_MM |
| 777 | UINT64_C(2080375408), // DPSX_W_PH |
| 778 | UINT64_C(5308), // DPSX_W_PH_MMR2 |
| 779 | UINT64_C(2080374896), // DPS_W_PH |
| 780 | UINT64_C(1212), // DPS_W_PH_MMR2 |
| 781 | UINT64_C(2097210), // DROTR |
| 782 | UINT64_C(2097214), // DROTR32 |
| 783 | UINT64_C(86), // DROTRV |
| 784 | UINT64_C(2080374948), // DSBH |
| 785 | UINT64_C(30), // DSDIV |
| 786 | UINT64_C(2080375140), // DSHD |
| 787 | UINT64_C(56), // DSLL |
| 788 | UINT64_C(60), // DSLL32 |
| 789 | UINT64_C(60), // DSLL64_32 |
| 790 | UINT64_C(20), // DSLLV |
| 791 | UINT64_C(59), // DSRA |
| 792 | UINT64_C(63), // DSRA32 |
| 793 | UINT64_C(23), // DSRAV |
| 794 | UINT64_C(58), // DSRL |
| 795 | UINT64_C(62), // DSRL32 |
| 796 | UINT64_C(22), // DSRLV |
| 797 | UINT64_C(46), // DSUB |
| 798 | UINT64_C(47), // DSUBu |
| 799 | UINT64_C(31), // DUDIV |
| 800 | UINT64_C(1096810532), // DVP |
| 801 | UINT64_C(1096810497), // DVPE |
| 802 | UINT64_C(6524), // DVP_MMR6 |
| 803 | UINT64_C(59418), // DivRxRy16 |
| 804 | UINT64_C(59419), // DivuRxRy16 |
| 805 | UINT64_C(192), // EHB |
| 806 | UINT64_C(6144), // EHB_MM |
| 807 | UINT64_C(6144), // EHB_MMR6 |
| 808 | UINT64_C(1096835104), // EI |
| 809 | UINT64_C(22396), // EI_MM |
| 810 | UINT64_C(22396), // EI_MMR6 |
| 811 | UINT64_C(1096813537), // EMT |
| 812 | UINT64_C(1107296280), // ERET |
| 813 | UINT64_C(1107296344), // ERETNC |
| 814 | UINT64_C(127868), // ERETNC_MMR6 |
| 815 | UINT64_C(62332), // ERET_MM |
| 816 | UINT64_C(62332), // ERET_MMR6 |
| 817 | UINT64_C(1096810500), // EVP |
| 818 | UINT64_C(1096810529), // EVPE |
| 819 | UINT64_C(14716), // EVP_MMR6 |
| 820 | UINT64_C(2080374784), // EXT |
| 821 | UINT64_C(2080374968), // EXTP |
| 822 | UINT64_C(2080375480), // EXTPDP |
| 823 | UINT64_C(2080375544), // EXTPDPV |
| 824 | UINT64_C(14524), // EXTPDPV_MM |
| 825 | UINT64_C(13948), // EXTPDP_MM |
| 826 | UINT64_C(2080375032), // EXTPV |
| 827 | UINT64_C(10428), // EXTPV_MM |
| 828 | UINT64_C(9852), // EXTP_MM |
| 829 | UINT64_C(2080375288), // EXTRV_RS_W |
| 830 | UINT64_C(11964), // EXTRV_RS_W_MM |
| 831 | UINT64_C(2080375160), // EXTRV_R_W |
| 832 | UINT64_C(7868), // EXTRV_R_W_MM |
| 833 | UINT64_C(2080375800), // EXTRV_S_H |
| 834 | UINT64_C(16060), // EXTRV_S_H_MM |
| 835 | UINT64_C(2080374904), // EXTRV_W |
| 836 | UINT64_C(3772), // EXTRV_W_MM |
| 837 | UINT64_C(2080375224), // EXTR_RS_W |
| 838 | UINT64_C(11900), // EXTR_RS_W_MM |
| 839 | UINT64_C(2080375096), // EXTR_R_W |
| 840 | UINT64_C(7804), // EXTR_R_W_MM |
| 841 | UINT64_C(2080375736), // EXTR_S_H |
| 842 | UINT64_C(15996), // EXTR_S_H_MM |
| 843 | UINT64_C(2080374840), // EXTR_W |
| 844 | UINT64_C(3708), // EXTR_W_MM |
| 845 | UINT64_C(1879048250), // EXTS |
| 846 | UINT64_C(1879048251), // EXTS32 |
| 847 | UINT64_C(44), // EXT_MM |
| 848 | UINT64_C(44), // EXT_MMR6 |
| 849 | UINT64_C(1176502277), // FABS_D32 |
| 850 | UINT64_C(1409295227), // FABS_D32_MM |
| 851 | UINT64_C(1176502277), // FABS_D64 |
| 852 | UINT64_C(1409295227), // FABS_D64_MM |
| 853 | UINT64_C(1174405125), // FABS_S |
| 854 | UINT64_C(1409287035), // FABS_S_MM |
| 855 | UINT64_C(2015363099), // FADD_D |
| 856 | UINT64_C(1176502272), // FADD_D32 |
| 857 | UINT64_C(1409286448), // FADD_D32_MM |
| 858 | UINT64_C(1176502272), // FADD_D64 |
| 859 | UINT64_C(1409286448), // FADD_D64_MM |
| 860 | UINT64_C(1186988032), // FADD_PS64 |
| 861 | UINT64_C(1174405120), // FADD_S |
| 862 | UINT64_C(1409286192), // FADD_S_MM |
| 863 | UINT64_C(1409286192), // FADD_S_MMR6 |
| 864 | UINT64_C(2013265947), // FADD_W |
| 865 | UINT64_C(2015363098), // FCAF_D |
| 866 | UINT64_C(2013265946), // FCAF_W |
| 867 | UINT64_C(2023751706), // FCEQ_D |
| 868 | UINT64_C(2021654554), // FCEQ_W |
| 869 | UINT64_C(2065760286), // FCLASS_D |
| 870 | UINT64_C(2065694750), // FCLASS_W |
| 871 | UINT64_C(2040528922), // FCLE_D |
| 872 | UINT64_C(2038431770), // FCLE_W |
| 873 | UINT64_C(2032140314), // FCLT_D |
| 874 | UINT64_C(2030043162), // FCLT_W |
| 875 | UINT64_C(1176502320), // FCMP_D32 |
| 876 | UINT64_C(1409287228), // FCMP_D32_MM |
| 877 | UINT64_C(1176502320), // FCMP_D64 |
| 878 | UINT64_C(1174405168), // FCMP_S32 |
| 879 | UINT64_C(1409286204), // FCMP_S32_MM |
| 880 | UINT64_C(2027946012), // FCNE_D |
| 881 | UINT64_C(2025848860), // FCNE_W |
| 882 | UINT64_C(2019557404), // FCOR_D |
| 883 | UINT64_C(2017460252), // FCOR_W |
| 884 | UINT64_C(2027946010), // FCUEQ_D |
| 885 | UINT64_C(2025848858), // FCUEQ_W |
| 886 | UINT64_C(2044723226), // FCULE_D |
| 887 | UINT64_C(2042626074), // FCULE_W |
| 888 | UINT64_C(2036334618), // FCULT_D |
| 889 | UINT64_C(2034237466), // FCULT_W |
| 890 | UINT64_C(2023751708), // FCUNE_D |
| 891 | UINT64_C(2021654556), // FCUNE_W |
| 892 | UINT64_C(2019557402), // FCUN_D |
| 893 | UINT64_C(2017460250), // FCUN_W |
| 894 | UINT64_C(2027946011), // FDIV_D |
| 895 | UINT64_C(1176502275), // FDIV_D32 |
| 896 | UINT64_C(1409286640), // FDIV_D32_MM |
| 897 | UINT64_C(1176502275), // FDIV_D64 |
| 898 | UINT64_C(1409286640), // FDIV_D64_MM |
| 899 | UINT64_C(1174405123), // FDIV_S |
| 900 | UINT64_C(1409286384), // FDIV_S_MM |
| 901 | UINT64_C(1409286384), // FDIV_S_MMR6 |
| 902 | UINT64_C(2025848859), // FDIV_W |
| 903 | UINT64_C(2046820379), // FEXDO_H |
| 904 | UINT64_C(2048917531), // FEXDO_W |
| 905 | UINT64_C(2044723227), // FEXP2_D |
| 906 | UINT64_C(2042626075), // FEXP2_W |
| 907 | UINT64_C(2066808862), // FEXUPL_D |
| 908 | UINT64_C(2066743326), // FEXUPL_W |
| 909 | UINT64_C(2066939934), // FEXUPR_D |
| 910 | UINT64_C(2066874398), // FEXUPR_W |
| 911 | UINT64_C(2067595294), // FFINT_S_D |
| 912 | UINT64_C(2067529758), // FFINT_S_W |
| 913 | UINT64_C(2067726366), // FFINT_U_D |
| 914 | UINT64_C(2067660830), // FFINT_U_W |
| 915 | UINT64_C(2067071006), // FFQL_D |
| 916 | UINT64_C(2067005470), // FFQL_W |
| 917 | UINT64_C(2067202078), // FFQR_D |
| 918 | UINT64_C(2067136542), // FFQR_W |
| 919 | UINT64_C(2063597598), // FILL_B |
| 920 | UINT64_C(2063794206), // FILL_D |
| 921 | UINT64_C(2063663134), // FILL_H |
| 922 | UINT64_C(2063728670), // FILL_W |
| 923 | UINT64_C(2066677790), // FLOG2_D |
| 924 | UINT64_C(2066612254), // FLOG2_W |
| 925 | UINT64_C(1176502283), // FLOOR_L_D64 |
| 926 | UINT64_C(1409303355), // FLOOR_L_D_MMR6 |
| 927 | UINT64_C(1174405131), // FLOOR_L_S |
| 928 | UINT64_C(1409286971), // FLOOR_L_S_MMR6 |
| 929 | UINT64_C(1176502287), // FLOOR_W_D32 |
| 930 | UINT64_C(1176502287), // FLOOR_W_D64 |
| 931 | UINT64_C(1409305403), // FLOOR_W_D_MMR6 |
| 932 | UINT64_C(1409305403), // FLOOR_W_MM |
| 933 | UINT64_C(1174405135), // FLOOR_W_S |
| 934 | UINT64_C(1409289019), // FLOOR_W_S_MM |
| 935 | UINT64_C(1409289019), // FLOOR_W_S_MMR6 |
| 936 | UINT64_C(2032140315), // FMADD_D |
| 937 | UINT64_C(2030043163), // FMADD_W |
| 938 | UINT64_C(2078277659), // FMAX_A_D |
| 939 | UINT64_C(2076180507), // FMAX_A_W |
| 940 | UINT64_C(2074083355), // FMAX_D |
| 941 | UINT64_C(2071986203), // FMAX_W |
| 942 | UINT64_C(2069889051), // FMIN_A_D |
| 943 | UINT64_C(2067791899), // FMIN_A_W |
| 944 | UINT64_C(2065694747), // FMIN_D |
| 945 | UINT64_C(2063597595), // FMIN_W |
| 946 | UINT64_C(1176502278), // FMOV_D32 |
| 947 | UINT64_C(1409294459), // FMOV_D32_MM |
| 948 | UINT64_C(1176502278), // FMOV_D64 |
| 949 | UINT64_C(1409294459), // FMOV_D64_MM |
| 950 | UINT64_C(1409294459), // FMOV_D_MMR6 |
| 951 | UINT64_C(1174405126), // FMOV_S |
| 952 | UINT64_C(1409286267), // FMOV_S_MM |
| 953 | UINT64_C(1409286267), // FMOV_S_MMR6 |
| 954 | UINT64_C(2036334619), // FMSUB_D |
| 955 | UINT64_C(2034237467), // FMSUB_W |
| 956 | UINT64_C(2023751707), // FMUL_D |
| 957 | UINT64_C(1176502274), // FMUL_D32 |
| 958 | UINT64_C(1409286576), // FMUL_D32_MM |
| 959 | UINT64_C(1176502274), // FMUL_D64 |
| 960 | UINT64_C(1409286576), // FMUL_D64_MM |
| 961 | UINT64_C(1186988034), // FMUL_PS64 |
| 962 | UINT64_C(1174405122), // FMUL_S |
| 963 | UINT64_C(1409286320), // FMUL_S_MM |
| 964 | UINT64_C(1409286320), // FMUL_S_MMR6 |
| 965 | UINT64_C(2021654555), // FMUL_W |
| 966 | UINT64_C(1176502279), // FNEG_D32 |
| 967 | UINT64_C(1409297275), // FNEG_D32_MM |
| 968 | UINT64_C(1176502279), // FNEG_D64 |
| 969 | UINT64_C(1409297275), // FNEG_D64_MM |
| 970 | UINT64_C(1174405127), // FNEG_S |
| 971 | UINT64_C(1409289083), // FNEG_S_MM |
| 972 | UINT64_C(1409289083), // FNEG_S_MMR6 |
| 973 | UINT64_C(2080374792), // FORK |
| 974 | UINT64_C(2066415646), // FRCP_D |
| 975 | UINT64_C(2066350110), // FRCP_W |
| 976 | UINT64_C(2066546718), // FRINT_D |
| 977 | UINT64_C(2066481182), // FRINT_W |
| 978 | UINT64_C(2066284574), // FRSQRT_D |
| 979 | UINT64_C(2066219038), // FRSQRT_W |
| 980 | UINT64_C(2048917530), // FSAF_D |
| 981 | UINT64_C(2046820378), // FSAF_W |
| 982 | UINT64_C(2057306138), // FSEQ_D |
| 983 | UINT64_C(2055208986), // FSEQ_W |
| 984 | UINT64_C(2074083354), // FSLE_D |
| 985 | UINT64_C(2071986202), // FSLE_W |
| 986 | UINT64_C(2065694746), // FSLT_D |
| 987 | UINT64_C(2063597594), // FSLT_W |
| 988 | UINT64_C(2061500444), // FSNE_D |
| 989 | UINT64_C(2059403292), // FSNE_W |
| 990 | UINT64_C(2053111836), // FSOR_D |
| 991 | UINT64_C(2051014684), // FSOR_W |
| 992 | UINT64_C(2066153502), // FSQRT_D |
| 993 | UINT64_C(1176502276), // FSQRT_D32 |
| 994 | UINT64_C(1409305147), // FSQRT_D32_MM |
| 995 | UINT64_C(1176502276), // FSQRT_D64 |
| 996 | UINT64_C(1409305147), // FSQRT_D64_MM |
| 997 | UINT64_C(1174405124), // FSQRT_S |
| 998 | UINT64_C(1409288763), // FSQRT_S_MM |
| 999 | UINT64_C(2066087966), // FSQRT_W |
| 1000 | UINT64_C(2019557403), // FSUB_D |
| 1001 | UINT64_C(1176502273), // FSUB_D32 |
| 1002 | UINT64_C(1409286512), // FSUB_D32_MM |
| 1003 | UINT64_C(1176502273), // FSUB_D64 |
| 1004 | UINT64_C(1409286512), // FSUB_D64_MM |
| 1005 | UINT64_C(1186988033), // FSUB_PS64 |
| 1006 | UINT64_C(1174405121), // FSUB_S |
| 1007 | UINT64_C(1409286256), // FSUB_S_MM |
| 1008 | UINT64_C(1409286256), // FSUB_S_MMR6 |
| 1009 | UINT64_C(2017460251), // FSUB_W |
| 1010 | UINT64_C(2061500442), // FSUEQ_D |
| 1011 | UINT64_C(2059403290), // FSUEQ_W |
| 1012 | UINT64_C(2078277658), // FSULE_D |
| 1013 | UINT64_C(2076180506), // FSULE_W |
| 1014 | UINT64_C(2069889050), // FSULT_D |
| 1015 | UINT64_C(2067791898), // FSULT_W |
| 1016 | UINT64_C(2057306140), // FSUNE_D |
| 1017 | UINT64_C(2055208988), // FSUNE_W |
| 1018 | UINT64_C(2053111834), // FSUN_D |
| 1019 | UINT64_C(2051014682), // FSUN_W |
| 1020 | UINT64_C(2067333150), // FTINT_S_D |
| 1021 | UINT64_C(2067267614), // FTINT_S_W |
| 1022 | UINT64_C(2067464222), // FTINT_U_D |
| 1023 | UINT64_C(2067398686), // FTINT_U_W |
| 1024 | UINT64_C(2055208987), // FTQ_H |
| 1025 | UINT64_C(2057306139), // FTQ_W |
| 1026 | UINT64_C(2065891358), // FTRUNC_S_D |
| 1027 | UINT64_C(2065825822), // FTRUNC_S_W |
| 1028 | UINT64_C(2066022430), // FTRUNC_U_D |
| 1029 | UINT64_C(2065956894), // FTRUNC_U_W |
| 1030 | UINT64_C(2080374845), // GINVI |
| 1031 | UINT64_C(24956), // GINVI_MMR6 |
| 1032 | UINT64_C(2080374973), // GINVT |
| 1033 | UINT64_C(29052), // GINVT_MMR6 |
| 1034 | UINT64_C(2053111829), // HADD_S_D |
| 1035 | UINT64_C(2048917525), // HADD_S_H |
| 1036 | UINT64_C(2051014677), // HADD_S_W |
| 1037 | UINT64_C(2061500437), // HADD_U_D |
| 1038 | UINT64_C(2057306133), // HADD_U_H |
| 1039 | UINT64_C(2059403285), // HADD_U_W |
| 1040 | UINT64_C(2069889045), // HSUB_S_D |
| 1041 | UINT64_C(2065694741), // HSUB_S_H |
| 1042 | UINT64_C(2067791893), // HSUB_S_W |
| 1043 | UINT64_C(2078277653), // HSUB_U_D |
| 1044 | UINT64_C(2074083349), // HSUB_U_H |
| 1045 | UINT64_C(2076180501), // HSUB_U_W |
| 1046 | UINT64_C(1107296296), // HYPCALL |
| 1047 | UINT64_C(50044), // HYPCALL_MM |
| 1048 | UINT64_C(2063597588), // ILVEV_B |
| 1049 | UINT64_C(2069889044), // ILVEV_D |
| 1050 | UINT64_C(2065694740), // ILVEV_H |
| 1051 | UINT64_C(2067791892), // ILVEV_W |
| 1052 | UINT64_C(2046820372), // ILVL_B |
| 1053 | UINT64_C(2053111828), // ILVL_D |
| 1054 | UINT64_C(2048917524), // ILVL_H |
| 1055 | UINT64_C(2051014676), // ILVL_W |
| 1056 | UINT64_C(2071986196), // ILVOD_B |
| 1057 | UINT64_C(2078277652), // ILVOD_D |
| 1058 | UINT64_C(2074083348), // ILVOD_H |
| 1059 | UINT64_C(2076180500), // ILVOD_W |
| 1060 | UINT64_C(2055208980), // ILVR_B |
| 1061 | UINT64_C(2061500436), // ILVR_D |
| 1062 | UINT64_C(2057306132), // ILVR_H |
| 1063 | UINT64_C(2059403284), // ILVR_W |
| 1064 | UINT64_C(2080374788), // INS |
| 1065 | UINT64_C(2030043161), // INSERT_B |
| 1066 | UINT64_C(2033713177), // INSERT_D |
| 1067 | UINT64_C(2032140313), // INSERT_H |
| 1068 | UINT64_C(2033188889), // INSERT_W |
| 1069 | UINT64_C(2080374796), // INSV |
| 1070 | UINT64_C(2034237465), // INSVE_B |
| 1071 | UINT64_C(2037907481), // INSVE_D |
| 1072 | UINT64_C(2036334617), // INSVE_H |
| 1073 | UINT64_C(2037383193), // INSVE_W |
| 1074 | UINT64_C(16700), // INSV_MM |
| 1075 | UINT64_C(12), // INS_MM |
| 1076 | UINT64_C(12), // INS_MMR6 |
| 1077 | UINT64_C(134217728), // J |
| 1078 | UINT64_C(201326592), // JAL |
| 1079 | UINT64_C(9), // JALR |
| 1080 | UINT64_C(17856), // JALR16_MM |
| 1081 | UINT64_C(9), // JALR64 |
| 1082 | UINT64_C(17419), // JALRC16_MMR6 |
| 1083 | UINT64_C(7996), // JALRC_HB_MMR6 |
| 1084 | UINT64_C(3900), // JALRC_MMR6 |
| 1085 | UINT64_C(17888), // JALRS16_MM |
| 1086 | UINT64_C(20284), // JALRS_MM |
| 1087 | UINT64_C(1033), // JALR_HB |
| 1088 | UINT64_C(1033), // JALR_HB64 |
| 1089 | UINT64_C(7996), // JALR_HB_MM |
| 1090 | UINT64_C(3900), // JALR_MM |
| 1091 | UINT64_C(1946157056), // JALS_MM |
| 1092 | UINT64_C(1946157056), // JALX |
| 1093 | UINT64_C(4026531840), // JALX_MM |
| 1094 | UINT64_C(4093640704), // JAL_MM |
| 1095 | UINT64_C(4160749568), // JIALC |
| 1096 | UINT64_C(4160749568), // JIALC64 |
| 1097 | UINT64_C(2147483648), // JIALC_MMR6 |
| 1098 | UINT64_C(3623878656), // JIC |
| 1099 | UINT64_C(3623878656), // JIC64 |
| 1100 | UINT64_C(2684354560), // JIC_MMR6 |
| 1101 | UINT64_C(8), // JR |
| 1102 | UINT64_C(17792), // JR16_MM |
| 1103 | UINT64_C(8), // JR64 |
| 1104 | UINT64_C(18176), // JRADDIUSP |
| 1105 | UINT64_C(17824), // JRC16_MM |
| 1106 | UINT64_C(17411), // JRC16_MMR6 |
| 1107 | UINT64_C(17427), // JRCADDIUSP_MMR6 |
| 1108 | UINT64_C(1032), // JR_HB |
| 1109 | UINT64_C(1032), // JR_HB64 |
| 1110 | UINT64_C(1033), // JR_HB64_R6 |
| 1111 | UINT64_C(7996), // JR_HB_MM |
| 1112 | UINT64_C(1033), // JR_HB_R6 |
| 1113 | UINT64_C(3900), // JR_MM |
| 1114 | UINT64_C(3556769792), // J_MM |
| 1115 | UINT64_C(402653184), // Jal16 |
| 1116 | UINT64_C(402653184), // JalB16 |
| 1117 | UINT64_C(59424), // JrRa16 |
| 1118 | UINT64_C(59616), // JrcRa16 |
| 1119 | UINT64_C(59584), // JrcRx16 |
| 1120 | UINT64_C(59392), // JumpLinkReg16 |
| 1121 | UINT64_C(2147483648), // LB |
| 1122 | UINT64_C(2147483648), // LB64 |
| 1123 | UINT64_C(2080374828), // LBE |
| 1124 | UINT64_C(1610639360), // LBE_MM |
| 1125 | UINT64_C(2048), // LBU16_MM |
| 1126 | UINT64_C(2080375178), // LBUX |
| 1127 | UINT64_C(549), // LBUX_MM |
| 1128 | UINT64_C(335544320), // LBU_MMR6 |
| 1129 | UINT64_C(469762048), // LB_MM |
| 1130 | UINT64_C(469762048), // LB_MMR6 |
| 1131 | UINT64_C(2415919104), // LBu |
| 1132 | UINT64_C(2415919104), // LBu64 |
| 1133 | UINT64_C(2080374824), // LBuE |
| 1134 | UINT64_C(1610637312), // LBuE_MM |
| 1135 | UINT64_C(335544320), // LBu_MM |
| 1136 | UINT64_C(3690987520), // LD |
| 1137 | UINT64_C(3556769792), // LDC1 |
| 1138 | UINT64_C(3556769792), // LDC164 |
| 1139 | UINT64_C(3154116608), // LDC1_D64_MMR6 |
| 1140 | UINT64_C(3154116608), // LDC1_MM_D32 |
| 1141 | UINT64_C(3154116608), // LDC1_MM_D64 |
| 1142 | UINT64_C(3623878656), // LDC2 |
| 1143 | UINT64_C(536879104), // LDC2_MMR6 |
| 1144 | UINT64_C(1237319680), // LDC2_R6 |
| 1145 | UINT64_C(3690987520), // LDC3 |
| 1146 | UINT64_C(2063597575), // LDI_B |
| 1147 | UINT64_C(2069889031), // LDI_D |
| 1148 | UINT64_C(2065694727), // LDI_H |
| 1149 | UINT64_C(2067791879), // LDI_W |
| 1150 | UINT64_C(1744830464), // LDL |
| 1151 | UINT64_C(3960995840), // LDPC |
| 1152 | UINT64_C(1811939328), // LDR |
| 1153 | UINT64_C(1275068417), // LDXC1 |
| 1154 | UINT64_C(1275068417), // LDXC164 |
| 1155 | UINT64_C(2013265952), // LD_B |
| 1156 | UINT64_C(2013265955), // LD_D |
| 1157 | UINT64_C(2013265953), // LD_H |
| 1158 | UINT64_C(2013265954), // LD_W |
| 1159 | UINT64_C(603979776), // LEA_ADDiu |
| 1160 | UINT64_C(1677721600), // LEA_ADDiu64 |
| 1161 | UINT64_C(805306368), // LEA_ADDiu_MM |
| 1162 | UINT64_C(2214592512), // LH |
| 1163 | UINT64_C(2214592512), // LH64 |
| 1164 | UINT64_C(2080374829), // LHE |
| 1165 | UINT64_C(1610639872), // LHE_MM |
| 1166 | UINT64_C(10240), // LHU16_MM |
| 1167 | UINT64_C(2080375050), // LHX |
| 1168 | UINT64_C(357), // LHX_MM |
| 1169 | UINT64_C(1006632960), // LH_MM |
| 1170 | UINT64_C(2483027968), // LHu |
| 1171 | UINT64_C(2483027968), // LHu64 |
| 1172 | UINT64_C(2080374825), // LHuE |
| 1173 | UINT64_C(1610637824), // LHuE_MM |
| 1174 | UINT64_C(872415232), // LHu_MM |
| 1175 | UINT64_C(60416), // LI16_MM |
| 1176 | UINT64_C(60416), // LI16_MMR6 |
| 1177 | UINT64_C(3221225472), // LL |
| 1178 | UINT64_C(3221225472), // LL64 |
| 1179 | UINT64_C(2080374838), // LL64_R6 |
| 1180 | UINT64_C(3489660928), // LLD |
| 1181 | UINT64_C(2080374839), // LLD_R6 |
| 1182 | UINT64_C(2080374830), // LLE |
| 1183 | UINT64_C(1610640384), // LLE_MM |
| 1184 | UINT64_C(1610625024), // LL_MM |
| 1185 | UINT64_C(1610625024), // LL_MMR6 |
| 1186 | UINT64_C(2080374838), // LL_R6 |
| 1187 | UINT64_C(5), // LSA |
| 1188 | UINT64_C(15), // LSA_MMR6 |
| 1189 | UINT64_C(5), // LSA_R6 |
| 1190 | UINT64_C(268435456), // LUI_MMR6 |
| 1191 | UINT64_C(1275068421), // LUXC1 |
| 1192 | UINT64_C(1275068421), // LUXC164 |
| 1193 | UINT64_C(1409286472), // LUXC1_MM |
| 1194 | UINT64_C(1006632960), // LUi |
| 1195 | UINT64_C(1006632960), // LUi64 |
| 1196 | UINT64_C(1101004800), // LUi_MM |
| 1197 | UINT64_C(2348810240), // LW |
| 1198 | UINT64_C(26624), // LW16_MM |
| 1199 | UINT64_C(2348810240), // LW64 |
| 1200 | UINT64_C(3288334336), // LWC1 |
| 1201 | UINT64_C(2617245696), // LWC1_MM |
| 1202 | UINT64_C(3355443200), // LWC2 |
| 1203 | UINT64_C(536870912), // LWC2_MMR6 |
| 1204 | UINT64_C(1228931072), // LWC2_R6 |
| 1205 | UINT64_C(3422552064), // LWC3 |
| 1206 | UINT64_C(2348810240), // LWDSP |
| 1207 | UINT64_C(4227858432), // LWDSP_MM |
| 1208 | UINT64_C(2080374831), // LWE |
| 1209 | UINT64_C(1610640896), // LWE_MM |
| 1210 | UINT64_C(25600), // LWGP_MM |
| 1211 | UINT64_C(2281701376), // LWL |
| 1212 | UINT64_C(2281701376), // LWL64 |
| 1213 | UINT64_C(2080374809), // LWLE |
| 1214 | UINT64_C(1610638336), // LWLE_MM |
| 1215 | UINT64_C(1610612736), // LWL_MM |
| 1216 | UINT64_C(17664), // LWM16_MM |
| 1217 | UINT64_C(17410), // LWM16_MMR6 |
| 1218 | UINT64_C(536891392), // LWM32_MM |
| 1219 | UINT64_C(3959947264), // LWPC |
| 1220 | UINT64_C(2013790208), // LWPC_MMR6 |
| 1221 | UINT64_C(536875008), // LWP_MM |
| 1222 | UINT64_C(2550136832), // LWR |
| 1223 | UINT64_C(2550136832), // LWR64 |
| 1224 | UINT64_C(2080374810), // LWRE |
| 1225 | UINT64_C(1610638848), // LWRE_MM |
| 1226 | UINT64_C(1610616832), // LWR_MM |
| 1227 | UINT64_C(18432), // LWSP_MM |
| 1228 | UINT64_C(3960471552), // LWUPC |
| 1229 | UINT64_C(1610670080), // LWU_MM |
| 1230 | UINT64_C(2080374794), // LWX |
| 1231 | UINT64_C(1275068416), // LWXC1 |
| 1232 | UINT64_C(1409286216), // LWXC1_MM |
| 1233 | UINT64_C(280), // LWXS_MM |
| 1234 | UINT64_C(421), // LWX_MM |
| 1235 | UINT64_C(4227858432), // LW_MM |
| 1236 | UINT64_C(4227858432), // LW_MMR6 |
| 1237 | UINT64_C(2617245696), // LWu |
| 1238 | UINT64_C(4026570752), // LbRxRyOffMemX16 |
| 1239 | UINT64_C(4026572800), // LbuRxRyOffMemX16 |
| 1240 | UINT64_C(4026572800), // LhRxRyOffMemX16 |
| 1241 | UINT64_C(4026572800), // LhuRxRyOffMemX16 |
| 1242 | UINT64_C(26624), // LiRxImm16 |
| 1243 | UINT64_C(4026558464), // LiRxImmAlignX16 |
| 1244 | UINT64_C(4026558464), // LiRxImmX16 |
| 1245 | UINT64_C(45056), // LwRxPcTcp16 |
| 1246 | UINT64_C(4026576896), // LwRxPcTcpX16 |
| 1247 | UINT64_C(4026570752), // LwRxRyOffMemX16 |
| 1248 | UINT64_C(4026568704), // LwRxSpImmX16 |
| 1249 | UINT64_C(1879048192), // MADD |
| 1250 | UINT64_C(1176502296), // MADDF_D |
| 1251 | UINT64_C(1409287096), // MADDF_D_MMR6 |
| 1252 | UINT64_C(1174405144), // MADDF_S |
| 1253 | UINT64_C(1409286584), // MADDF_S_MMR6 |
| 1254 | UINT64_C(2067791900), // MADDR_Q_H |
| 1255 | UINT64_C(2069889052), // MADDR_Q_W |
| 1256 | UINT64_C(1879048193), // MADDU |
| 1257 | UINT64_C(1879048193), // MADDU_DSP |
| 1258 | UINT64_C(6844), // MADDU_DSP_MM |
| 1259 | UINT64_C(56124), // MADDU_MM |
| 1260 | UINT64_C(2021654546), // MADDV_B |
| 1261 | UINT64_C(2027946002), // MADDV_D |
| 1262 | UINT64_C(2023751698), // MADDV_H |
| 1263 | UINT64_C(2025848850), // MADDV_W |
| 1264 | UINT64_C(1275068449), // MADD_D32 |
| 1265 | UINT64_C(1409286153), // MADD_D32_MM |
| 1266 | UINT64_C(1275068449), // MADD_D64 |
| 1267 | UINT64_C(1879048192), // MADD_DSP |
| 1268 | UINT64_C(2748), // MADD_DSP_MM |
| 1269 | UINT64_C(52028), // MADD_MM |
| 1270 | UINT64_C(2034237468), // MADD_Q_H |
| 1271 | UINT64_C(2036334620), // MADD_Q_W |
| 1272 | UINT64_C(1275068448), // MADD_S |
| 1273 | UINT64_C(1409286145), // MADD_S_MM |
| 1274 | UINT64_C(2080375856), // MAQ_SA_W_PHL |
| 1275 | UINT64_C(14972), // MAQ_SA_W_PHL_MM |
| 1276 | UINT64_C(2080375984), // MAQ_SA_W_PHR |
| 1277 | UINT64_C(10876), // MAQ_SA_W_PHR_MM |
| 1278 | UINT64_C(2080376112), // MAQ_S_W_PHL |
| 1279 | UINT64_C(6780), // MAQ_S_W_PHL_MM |
| 1280 | UINT64_C(2080376240), // MAQ_S_W_PHR |
| 1281 | UINT64_C(2684), // MAQ_S_W_PHR_MM |
| 1282 | UINT64_C(1176502303), // MAXA_D |
| 1283 | UINT64_C(1409286699), // MAXA_D_MMR6 |
| 1284 | UINT64_C(1174405151), // MAXA_S |
| 1285 | UINT64_C(1409286187), // MAXA_S_MMR6 |
| 1286 | UINT64_C(2030043142), // MAXI_S_B |
| 1287 | UINT64_C(2036334598), // MAXI_S_D |
| 1288 | UINT64_C(2032140294), // MAXI_S_H |
| 1289 | UINT64_C(2034237446), // MAXI_S_W |
| 1290 | UINT64_C(2038431750), // MAXI_U_B |
| 1291 | UINT64_C(2044723206), // MAXI_U_D |
| 1292 | UINT64_C(2040528902), // MAXI_U_H |
| 1293 | UINT64_C(2042626054), // MAXI_U_W |
| 1294 | UINT64_C(2063597582), // MAX_A_B |
| 1295 | UINT64_C(2069889038), // MAX_A_D |
| 1296 | UINT64_C(2065694734), // MAX_A_H |
| 1297 | UINT64_C(2067791886), // MAX_A_W |
| 1298 | UINT64_C(1176502302), // MAX_D |
| 1299 | UINT64_C(1409286667), // MAX_D_MMR6 |
| 1300 | UINT64_C(1174405150), // MAX_S |
| 1301 | UINT64_C(2030043150), // MAX_S_B |
| 1302 | UINT64_C(2036334606), // MAX_S_D |
| 1303 | UINT64_C(2032140302), // MAX_S_H |
| 1304 | UINT64_C(1409286155), // MAX_S_MMR6 |
| 1305 | UINT64_C(2034237454), // MAX_S_W |
| 1306 | UINT64_C(2038431758), // MAX_U_B |
| 1307 | UINT64_C(2044723214), // MAX_U_D |
| 1308 | UINT64_C(2040528910), // MAX_U_H |
| 1309 | UINT64_C(2042626062), // MAX_U_W |
| 1310 | UINT64_C(1073741824), // MFC0 |
| 1311 | UINT64_C(252), // MFC0_MM |
| 1312 | UINT64_C(252), // MFC0_MMR6 |
| 1313 | UINT64_C(1140850688), // MFC1 |
| 1314 | UINT64_C(1140850688), // MFC1_D64 |
| 1315 | UINT64_C(1409294395), // MFC1_MM |
| 1316 | UINT64_C(1409294395), // MFC1_MMR6 |
| 1317 | UINT64_C(1207959552), // MFC2 |
| 1318 | UINT64_C(19772), // MFC2_MMR6 |
| 1319 | UINT64_C(1080033280), // MFGC0 |
| 1320 | UINT64_C(1276), // MFGC0_MM |
| 1321 | UINT64_C(244), // MFHC0_MMR6 |
| 1322 | UINT64_C(1147142144), // MFHC1_D32 |
| 1323 | UINT64_C(1409298491), // MFHC1_D32_MM |
| 1324 | UINT64_C(1147142144), // MFHC1_D64 |
| 1325 | UINT64_C(1409298491), // MFHC1_D64_MM |
| 1326 | UINT64_C(36156), // MFHC2_MMR6 |
| 1327 | UINT64_C(1080034304), // MFHGC0 |
| 1328 | UINT64_C(1268), // MFHGC0_MM |
| 1329 | UINT64_C(16), // MFHI |
| 1330 | UINT64_C(17920), // MFHI16_MM |
| 1331 | UINT64_C(16), // MFHI64 |
| 1332 | UINT64_C(16), // MFHI_DSP |
| 1333 | UINT64_C(124), // MFHI_DSP_MM |
| 1334 | UINT64_C(3452), // MFHI_MM |
| 1335 | UINT64_C(18), // MFLO |
| 1336 | UINT64_C(17984), // MFLO16_MM |
| 1337 | UINT64_C(18), // MFLO64 |
| 1338 | UINT64_C(18), // MFLO_DSP |
| 1339 | UINT64_C(4220), // MFLO_DSP_MM |
| 1340 | UINT64_C(7548), // MFLO_MM |
| 1341 | UINT64_C(1090519040), // MFTR |
| 1342 | UINT64_C(1176502301), // MINA_D |
| 1343 | UINT64_C(1409286691), // MINA_D_MMR6 |
| 1344 | UINT64_C(1174405149), // MINA_S |
| 1345 | UINT64_C(1409286179), // MINA_S_MMR6 |
| 1346 | UINT64_C(2046820358), // MINI_S_B |
| 1347 | UINT64_C(2053111814), // MINI_S_D |
| 1348 | UINT64_C(2048917510), // MINI_S_H |
| 1349 | UINT64_C(2051014662), // MINI_S_W |
| 1350 | UINT64_C(2055208966), // MINI_U_B |
| 1351 | UINT64_C(2061500422), // MINI_U_D |
| 1352 | UINT64_C(2057306118), // MINI_U_H |
| 1353 | UINT64_C(2059403270), // MINI_U_W |
| 1354 | UINT64_C(2071986190), // MIN_A_B |
| 1355 | UINT64_C(2078277646), // MIN_A_D |
| 1356 | UINT64_C(2074083342), // MIN_A_H |
| 1357 | UINT64_C(2076180494), // MIN_A_W |
| 1358 | UINT64_C(1176502300), // MIN_D |
| 1359 | UINT64_C(1409286659), // MIN_D_MMR6 |
| 1360 | UINT64_C(1174405148), // MIN_S |
| 1361 | UINT64_C(2046820366), // MIN_S_B |
| 1362 | UINT64_C(2053111822), // MIN_S_D |
| 1363 | UINT64_C(2048917518), // MIN_S_H |
| 1364 | UINT64_C(1409286147), // MIN_S_MMR6 |
| 1365 | UINT64_C(2051014670), // MIN_S_W |
| 1366 | UINT64_C(2055208974), // MIN_U_B |
| 1367 | UINT64_C(2061500430), // MIN_U_D |
| 1368 | UINT64_C(2057306126), // MIN_U_H |
| 1369 | UINT64_C(2059403278), // MIN_U_W |
| 1370 | UINT64_C(218), // MOD |
| 1371 | UINT64_C(2080375952), // MODSUB |
| 1372 | UINT64_C(661), // MODSUB_MM |
| 1373 | UINT64_C(219), // MODU |
| 1374 | UINT64_C(472), // MODU_MMR6 |
| 1375 | UINT64_C(344), // MOD_MMR6 |
| 1376 | UINT64_C(2063597586), // MOD_S_B |
| 1377 | UINT64_C(2069889042), // MOD_S_D |
| 1378 | UINT64_C(2065694738), // MOD_S_H |
| 1379 | UINT64_C(2067791890), // MOD_S_W |
| 1380 | UINT64_C(2071986194), // MOD_U_B |
| 1381 | UINT64_C(2078277650), // MOD_U_D |
| 1382 | UINT64_C(2074083346), // MOD_U_H |
| 1383 | UINT64_C(2076180498), // MOD_U_W |
| 1384 | UINT64_C(3072), // MOVE16_MM |
| 1385 | UINT64_C(3072), // MOVE16_MMR6 |
| 1386 | UINT64_C(33792), // MOVEP_MM |
| 1387 | UINT64_C(17412), // MOVEP_MMR6 |
| 1388 | UINT64_C(2025717785), // MOVE_V |
| 1389 | UINT64_C(1176502289), // MOVF_D32 |
| 1390 | UINT64_C(1409286688), // MOVF_D32_MM |
| 1391 | UINT64_C(1176502289), // MOVF_D64 |
| 1392 | UINT64_C(1), // MOVF_I |
| 1393 | UINT64_C(1), // MOVF_I64 |
| 1394 | UINT64_C(1409286523), // MOVF_I_MM |
| 1395 | UINT64_C(1174405137), // MOVF_S |
| 1396 | UINT64_C(1409286176), // MOVF_S_MM |
| 1397 | UINT64_C(1176502291), // MOVN_I64_D64 |
| 1398 | UINT64_C(11), // MOVN_I64_I |
| 1399 | UINT64_C(11), // MOVN_I64_I64 |
| 1400 | UINT64_C(1174405139), // MOVN_I64_S |
| 1401 | UINT64_C(1176502291), // MOVN_I_D32 |
| 1402 | UINT64_C(1409286456), // MOVN_I_D32_MM |
| 1403 | UINT64_C(1176502291), // MOVN_I_D64 |
| 1404 | UINT64_C(11), // MOVN_I_I |
| 1405 | UINT64_C(11), // MOVN_I_I64 |
| 1406 | UINT64_C(24), // MOVN_I_MM |
| 1407 | UINT64_C(1174405139), // MOVN_I_S |
| 1408 | UINT64_C(1409286200), // MOVN_I_S_MM |
| 1409 | UINT64_C(1176567825), // MOVT_D32 |
| 1410 | UINT64_C(1409286752), // MOVT_D32_MM |
| 1411 | UINT64_C(1176567825), // MOVT_D64 |
| 1412 | UINT64_C(65537), // MOVT_I |
| 1413 | UINT64_C(65537), // MOVT_I64 |
| 1414 | UINT64_C(1409288571), // MOVT_I_MM |
| 1415 | UINT64_C(1174470673), // MOVT_S |
| 1416 | UINT64_C(1409286240), // MOVT_S_MM |
| 1417 | UINT64_C(1176502290), // MOVZ_I64_D64 |
| 1418 | UINT64_C(10), // MOVZ_I64_I |
| 1419 | UINT64_C(10), // MOVZ_I64_I64 |
| 1420 | UINT64_C(1174405138), // MOVZ_I64_S |
| 1421 | UINT64_C(1176502290), // MOVZ_I_D32 |
| 1422 | UINT64_C(1409286520), // MOVZ_I_D32_MM |
| 1423 | UINT64_C(1176502290), // MOVZ_I_D64 |
| 1424 | UINT64_C(10), // MOVZ_I_I |
| 1425 | UINT64_C(10), // MOVZ_I_I64 |
| 1426 | UINT64_C(88), // MOVZ_I_MM |
| 1427 | UINT64_C(1174405138), // MOVZ_I_S |
| 1428 | UINT64_C(1409286264), // MOVZ_I_S_MM |
| 1429 | UINT64_C(1879048196), // MSUB |
| 1430 | UINT64_C(1176502297), // MSUBF_D |
| 1431 | UINT64_C(1409287160), // MSUBF_D_MMR6 |
| 1432 | UINT64_C(1174405145), // MSUBF_S |
| 1433 | UINT64_C(1409286648), // MSUBF_S_MMR6 |
| 1434 | UINT64_C(2071986204), // MSUBR_Q_H |
| 1435 | UINT64_C(2074083356), // MSUBR_Q_W |
| 1436 | UINT64_C(1879048197), // MSUBU |
| 1437 | UINT64_C(1879048197), // MSUBU_DSP |
| 1438 | UINT64_C(15036), // MSUBU_DSP_MM |
| 1439 | UINT64_C(64316), // MSUBU_MM |
| 1440 | UINT64_C(2030043154), // MSUBV_B |
| 1441 | UINT64_C(2036334610), // MSUBV_D |
| 1442 | UINT64_C(2032140306), // MSUBV_H |
| 1443 | UINT64_C(2034237458), // MSUBV_W |
| 1444 | UINT64_C(1275068457), // MSUB_D32 |
| 1445 | UINT64_C(1409286185), // MSUB_D32_MM |
| 1446 | UINT64_C(1275068457), // MSUB_D64 |
| 1447 | UINT64_C(1879048196), // MSUB_DSP |
| 1448 | UINT64_C(10940), // MSUB_DSP_MM |
| 1449 | UINT64_C(60220), // MSUB_MM |
| 1450 | UINT64_C(2038431772), // MSUB_Q_H |
| 1451 | UINT64_C(2040528924), // MSUB_Q_W |
| 1452 | UINT64_C(1275068456), // MSUB_S |
| 1453 | UINT64_C(1409286177), // MSUB_S_MM |
| 1454 | UINT64_C(1082130432), // MTC0 |
| 1455 | UINT64_C(764), // MTC0_MM |
| 1456 | UINT64_C(764), // MTC0_MMR6 |
| 1457 | UINT64_C(1149239296), // MTC1 |
| 1458 | UINT64_C(1149239296), // MTC1_D64 |
| 1459 | UINT64_C(1409296443), // MTC1_D64_MM |
| 1460 | UINT64_C(1409296443), // MTC1_MM |
| 1461 | UINT64_C(1409296443), // MTC1_MMR6 |
| 1462 | UINT64_C(1216348160), // MTC2 |
| 1463 | UINT64_C(23868), // MTC2_MMR6 |
| 1464 | UINT64_C(1080033792), // MTGC0 |
| 1465 | UINT64_C(1788), // MTGC0_MM |
| 1466 | UINT64_C(756), // MTHC0_MMR6 |
| 1467 | UINT64_C(1155530752), // MTHC1_D32 |
| 1468 | UINT64_C(1409300539), // MTHC1_D32_MM |
| 1469 | UINT64_C(1155530752), // MTHC1_D64 |
| 1470 | UINT64_C(1409300539), // MTHC1_D64_MM |
| 1471 | UINT64_C(40252), // MTHC2_MMR6 |
| 1472 | UINT64_C(1080034816), // MTHGC0 |
| 1473 | UINT64_C(1780), // MTHGC0_MM |
| 1474 | UINT64_C(17), // MTHI |
| 1475 | UINT64_C(17), // MTHI64 |
| 1476 | UINT64_C(17), // MTHI_DSP |
| 1477 | UINT64_C(8316), // MTHI_DSP_MM |
| 1478 | UINT64_C(11644), // MTHI_MM |
| 1479 | UINT64_C(2080376824), // MTHLIP |
| 1480 | UINT64_C(636), // MTHLIP_MM |
| 1481 | UINT64_C(19), // MTLO |
| 1482 | UINT64_C(19), // MTLO64 |
| 1483 | UINT64_C(19), // MTLO_DSP |
| 1484 | UINT64_C(12412), // MTLO_DSP_MM |
| 1485 | UINT64_C(15740), // MTLO_MM |
| 1486 | UINT64_C(1879048200), // MTM0 |
| 1487 | UINT64_C(1879048204), // MTM1 |
| 1488 | UINT64_C(1879048205), // MTM2 |
| 1489 | UINT64_C(1879048201), // MTP0 |
| 1490 | UINT64_C(1879048202), // MTP1 |
| 1491 | UINT64_C(1879048203), // MTP2 |
| 1492 | UINT64_C(1098907648), // MTTR |
| 1493 | UINT64_C(216), // MUH |
| 1494 | UINT64_C(217), // MUHU |
| 1495 | UINT64_C(216), // MUHU_MMR6 |
| 1496 | UINT64_C(88), // MUH_MMR6 |
| 1497 | UINT64_C(1879048194), // MUL |
| 1498 | UINT64_C(2080376592), // MULEQ_S_W_PHL |
| 1499 | UINT64_C(37), // MULEQ_S_W_PHL_MM |
| 1500 | UINT64_C(2080376656), // MULEQ_S_W_PHR |
| 1501 | UINT64_C(101), // MULEQ_S_W_PHR_MM |
| 1502 | UINT64_C(2080375184), // MULEU_S_PH_QBL |
| 1503 | UINT64_C(149), // MULEU_S_PH_QBL_MM |
| 1504 | UINT64_C(2080375248), // MULEU_S_PH_QBR |
| 1505 | UINT64_C(213), // MULEU_S_PH_QBR_MM |
| 1506 | UINT64_C(2080376784), // MULQ_RS_PH |
| 1507 | UINT64_C(277), // MULQ_RS_PH_MM |
| 1508 | UINT64_C(2080376280), // MULQ_RS_W |
| 1509 | UINT64_C(405), // MULQ_RS_W_MMR2 |
| 1510 | UINT64_C(2080376720), // MULQ_S_PH |
| 1511 | UINT64_C(341), // MULQ_S_PH_MMR2 |
| 1512 | UINT64_C(2080376216), // MULQ_S_W |
| 1513 | UINT64_C(469), // MULQ_S_W_MMR2 |
| 1514 | UINT64_C(1186988058), // MULR_PS64 |
| 1515 | UINT64_C(2063597596), // MULR_Q_H |
| 1516 | UINT64_C(2065694748), // MULR_Q_W |
| 1517 | UINT64_C(2080375216), // MULSAQ_S_W_PH |
| 1518 | UINT64_C(15548), // MULSAQ_S_W_PH_MM |
| 1519 | UINT64_C(2080374960), // MULSA_W_PH |
| 1520 | UINT64_C(11452), // MULSA_W_PH_MMR2 |
| 1521 | UINT64_C(24), // MULT |
| 1522 | UINT64_C(25), // MULTU_DSP |
| 1523 | UINT64_C(7356), // MULTU_DSP_MM |
| 1524 | UINT64_C(24), // MULT_DSP |
| 1525 | UINT64_C(3260), // MULT_DSP_MM |
| 1526 | UINT64_C(35644), // MULT_MM |
| 1527 | UINT64_C(25), // MULTu |
| 1528 | UINT64_C(39740), // MULTu_MM |
| 1529 | UINT64_C(153), // MULU |
| 1530 | UINT64_C(152), // MULU_MMR6 |
| 1531 | UINT64_C(2013265938), // MULV_B |
| 1532 | UINT64_C(2019557394), // MULV_D |
| 1533 | UINT64_C(2015363090), // MULV_H |
| 1534 | UINT64_C(2017460242), // MULV_W |
| 1535 | UINT64_C(528), // MUL_MM |
| 1536 | UINT64_C(24), // MUL_MMR6 |
| 1537 | UINT64_C(2080375576), // MUL_PH |
| 1538 | UINT64_C(45), // MUL_PH_MMR2 |
| 1539 | UINT64_C(2030043164), // MUL_Q_H |
| 1540 | UINT64_C(2032140316), // MUL_Q_W |
| 1541 | UINT64_C(152), // MUL_R6 |
| 1542 | UINT64_C(2080375704), // MUL_S_PH |
| 1543 | UINT64_C(1069), // MUL_S_PH_MMR2 |
| 1544 | UINT64_C(59408), // Mfhi16 |
| 1545 | UINT64_C(59410), // Mflo16 |
| 1546 | UINT64_C(25856), // Move32R16 |
| 1547 | UINT64_C(26368), // MoveR3216 |
| 1548 | UINT64_C(68157440), // NAL |
| 1549 | UINT64_C(2064121886), // NLOC_B |
| 1550 | UINT64_C(2064318494), // NLOC_D |
| 1551 | UINT64_C(2064187422), // NLOC_H |
| 1552 | UINT64_C(2064252958), // NLOC_W |
| 1553 | UINT64_C(2064384030), // NLZC_B |
| 1554 | UINT64_C(2064580638), // NLZC_D |
| 1555 | UINT64_C(2064449566), // NLZC_H |
| 1556 | UINT64_C(2064515102), // NLZC_W |
| 1557 | UINT64_C(1275068465), // NMADD_D32 |
| 1558 | UINT64_C(1409286154), // NMADD_D32_MM |
| 1559 | UINT64_C(1275068465), // NMADD_D64 |
| 1560 | UINT64_C(1275068464), // NMADD_S |
| 1561 | UINT64_C(1409286146), // NMADD_S_MM |
| 1562 | UINT64_C(1275068473), // NMSUB_D32 |
| 1563 | UINT64_C(1409286186), // NMSUB_D32_MM |
| 1564 | UINT64_C(1275068473), // NMSUB_D64 |
| 1565 | UINT64_C(1275068472), // NMSUB_S |
| 1566 | UINT64_C(1409286178), // NMSUB_S_MM |
| 1567 | UINT64_C(39), // NOR |
| 1568 | UINT64_C(39), // NOR64 |
| 1569 | UINT64_C(2046820352), // NORI_B |
| 1570 | UINT64_C(720), // NOR_MM |
| 1571 | UINT64_C(720), // NOR_MMR6 |
| 1572 | UINT64_C(2017460254), // NOR_V |
| 1573 | UINT64_C(17408), // NOT16_MM |
| 1574 | UINT64_C(17408), // NOT16_MMR6 |
| 1575 | UINT64_C(59421), // NegRxRy16 |
| 1576 | UINT64_C(59407), // NotRxRy16 |
| 1577 | UINT64_C(37), // OR |
| 1578 | UINT64_C(17600), // OR16_MM |
| 1579 | UINT64_C(17417), // OR16_MMR6 |
| 1580 | UINT64_C(37), // OR64 |
| 1581 | UINT64_C(2030043136), // ORI_B |
| 1582 | UINT64_C(1342177280), // ORI_MMR6 |
| 1583 | UINT64_C(656), // OR_MM |
| 1584 | UINT64_C(656), // OR_MMR6 |
| 1585 | UINT64_C(2015363102), // OR_V |
| 1586 | UINT64_C(872415232), // ORi |
| 1587 | UINT64_C(872415232), // ORi64 |
| 1588 | UINT64_C(1342177280), // ORi_MM |
| 1589 | UINT64_C(59405), // OrRxRxRy16 |
| 1590 | UINT64_C(2080375697), // PACKRL_PH |
| 1591 | UINT64_C(429), // PACKRL_PH_MM |
| 1592 | UINT64_C(320), // PAUSE |
| 1593 | UINT64_C(10240), // PAUSE_MM |
| 1594 | UINT64_C(10240), // PAUSE_MMR6 |
| 1595 | UINT64_C(2030043156), // PCKEV_B |
| 1596 | UINT64_C(2036334612), // PCKEV_D |
| 1597 | UINT64_C(2032140308), // PCKEV_H |
| 1598 | UINT64_C(2034237460), // PCKEV_W |
| 1599 | UINT64_C(2038431764), // PCKOD_B |
| 1600 | UINT64_C(2044723220), // PCKOD_D |
| 1601 | UINT64_C(2040528916), // PCKOD_H |
| 1602 | UINT64_C(2042626068), // PCKOD_W |
| 1603 | UINT64_C(2063859742), // PCNT_B |
| 1604 | UINT64_C(2064056350), // PCNT_D |
| 1605 | UINT64_C(2063925278), // PCNT_H |
| 1606 | UINT64_C(2063990814), // PCNT_W |
| 1607 | UINT64_C(2080375505), // PICK_PH |
| 1608 | UINT64_C(557), // PICK_PH_MM |
| 1609 | UINT64_C(2080374993), // PICK_QB |
| 1610 | UINT64_C(493), // PICK_QB_MM |
| 1611 | UINT64_C(1186988076), // PLL_PS64 |
| 1612 | UINT64_C(1186988077), // PLU_PS64 |
| 1613 | UINT64_C(1879048236), // POP |
| 1614 | UINT64_C(2080375058), // PRECEQU_PH_QBL |
| 1615 | UINT64_C(2080375186), // PRECEQU_PH_QBLA |
| 1616 | UINT64_C(29500), // PRECEQU_PH_QBLA_MM |
| 1617 | UINT64_C(28988), // PRECEQU_PH_QBL_MM |
| 1618 | UINT64_C(2080375122), // PRECEQU_PH_QBR |
| 1619 | UINT64_C(2080375250), // PRECEQU_PH_QBRA |
| 1620 | UINT64_C(37692), // PRECEQU_PH_QBRA_MM |
| 1621 | UINT64_C(37180), // PRECEQU_PH_QBR_MM |
| 1622 | UINT64_C(2080375570), // PRECEQ_W_PHL |
| 1623 | UINT64_C(20796), // PRECEQ_W_PHL_MM |
| 1624 | UINT64_C(2080375634), // PRECEQ_W_PHR |
| 1625 | UINT64_C(24892), // PRECEQ_W_PHR_MM |
| 1626 | UINT64_C(2080376594), // PRECEU_PH_QBL |
| 1627 | UINT64_C(2080376722), // PRECEU_PH_QBLA |
| 1628 | UINT64_C(45884), // PRECEU_PH_QBLA_MM |
| 1629 | UINT64_C(45372), // PRECEU_PH_QBL_MM |
| 1630 | UINT64_C(2080376658), // PRECEU_PH_QBR |
| 1631 | UINT64_C(2080376786), // PRECEU_PH_QBRA |
| 1632 | UINT64_C(54076), // PRECEU_PH_QBRA_MM |
| 1633 | UINT64_C(53564), // PRECEU_PH_QBR_MM |
| 1634 | UINT64_C(2080375761), // PRECRQU_S_QB_PH |
| 1635 | UINT64_C(365), // PRECRQU_S_QB_PH_MM |
| 1636 | UINT64_C(2080376081), // PRECRQ_PH_W |
| 1637 | UINT64_C(237), // PRECRQ_PH_W_MM |
| 1638 | UINT64_C(2080375569), // PRECRQ_QB_PH |
| 1639 | UINT64_C(173), // PRECRQ_QB_PH_MM |
| 1640 | UINT64_C(2080376145), // PRECRQ_RS_PH_W |
| 1641 | UINT64_C(301), // PRECRQ_RS_PH_W_MM |
| 1642 | UINT64_C(2080375633), // PRECR_QB_PH |
| 1643 | UINT64_C(109), // PRECR_QB_PH_MMR2 |
| 1644 | UINT64_C(2080376721), // PRECR_SRA_PH_W |
| 1645 | UINT64_C(973), // PRECR_SRA_PH_W_MMR2 |
| 1646 | UINT64_C(2080376785), // PRECR_SRA_R_PH_W |
| 1647 | UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2 |
| 1648 | UINT64_C(3422552064), // PREF |
| 1649 | UINT64_C(2080374819), // PREFE |
| 1650 | UINT64_C(1610654720), // PREFE_MM |
| 1651 | UINT64_C(1409286560), // PREFX_MM |
| 1652 | UINT64_C(1610620928), // PREF_MM |
| 1653 | UINT64_C(1610620928), // PREF_MMR6 |
| 1654 | UINT64_C(2080374837), // PREF_R6 |
| 1655 | UINT64_C(2080374897), // PREPEND |
| 1656 | UINT64_C(597), // PREPEND_MMR2 |
| 1657 | UINT64_C(1186988078), // PUL_PS64 |
| 1658 | UINT64_C(1186988079), // PUU_PS64 |
| 1659 | UINT64_C(2080376080), // RADDU_W_QB |
| 1660 | UINT64_C(61756), // RADDU_W_QB_MM |
| 1661 | UINT64_C(2080375992), // RDDSP |
| 1662 | UINT64_C(1660), // RDDSP_MM |
| 1663 | UINT64_C(2080374843), // RDHWR |
| 1664 | UINT64_C(2080374843), // RDHWR64 |
| 1665 | UINT64_C(27452), // RDHWR_MM |
| 1666 | UINT64_C(448), // RDHWR_MMR6 |
| 1667 | UINT64_C(57724), // RDPGPR_MMR6 |
| 1668 | UINT64_C(1176502293), // RECIP_D32 |
| 1669 | UINT64_C(1409307195), // RECIP_D32_MM |
| 1670 | UINT64_C(1176502293), // RECIP_D64 |
| 1671 | UINT64_C(1409307195), // RECIP_D64_MM |
| 1672 | UINT64_C(1174405141), // RECIP_S |
| 1673 | UINT64_C(1409290811), // RECIP_S_MM |
| 1674 | UINT64_C(2080375506), // REPLV_PH |
| 1675 | UINT64_C(828), // REPLV_PH_MM |
| 1676 | UINT64_C(2080374994), // REPLV_QB |
| 1677 | UINT64_C(4924), // REPLV_QB_MM |
| 1678 | UINT64_C(2080375442), // REPL_PH |
| 1679 | UINT64_C(61), // REPL_PH_MM |
| 1680 | UINT64_C(2080374930), // REPL_QB |
| 1681 | UINT64_C(1532), // REPL_QB_MM |
| 1682 | UINT64_C(1176502298), // RINT_D |
| 1683 | UINT64_C(1409286688), // RINT_D_MMR6 |
| 1684 | UINT64_C(1174405146), // RINT_S |
| 1685 | UINT64_C(1409286176), // RINT_S_MMR6 |
| 1686 | UINT64_C(2097154), // ROTR |
| 1687 | UINT64_C(70), // ROTRV |
| 1688 | UINT64_C(208), // ROTRV_MM |
| 1689 | UINT64_C(192), // ROTR_MM |
| 1690 | UINT64_C(1176502280), // ROUND_L_D64 |
| 1691 | UINT64_C(1409315643), // ROUND_L_D_MMR6 |
| 1692 | UINT64_C(1174405128), // ROUND_L_S |
| 1693 | UINT64_C(1409299259), // ROUND_L_S_MMR6 |
| 1694 | UINT64_C(1176502284), // ROUND_W_D32 |
| 1695 | UINT64_C(1176502284), // ROUND_W_D64 |
| 1696 | UINT64_C(1409317691), // ROUND_W_D_MMR6 |
| 1697 | UINT64_C(1409317691), // ROUND_W_MM |
| 1698 | UINT64_C(1174405132), // ROUND_W_S |
| 1699 | UINT64_C(1409301307), // ROUND_W_S_MM |
| 1700 | UINT64_C(1409301307), // ROUND_W_S_MMR6 |
| 1701 | UINT64_C(1176502294), // RSQRT_D32 |
| 1702 | UINT64_C(1409303099), // RSQRT_D32_MM |
| 1703 | UINT64_C(1176502294), // RSQRT_D64 |
| 1704 | UINT64_C(1409303099), // RSQRT_D64_MM |
| 1705 | UINT64_C(1174405142), // RSQRT_S |
| 1706 | UINT64_C(1409286715), // RSQRT_S_MM |
| 1707 | UINT64_C(25728), // Restore16 |
| 1708 | UINT64_C(25728), // RestoreX16 |
| 1709 | UINT64_C(1879048216), // SAA |
| 1710 | UINT64_C(1879048217), // SAAD |
| 1711 | UINT64_C(2020605962), // SAT_S_B |
| 1712 | UINT64_C(2013265930), // SAT_S_D |
| 1713 | UINT64_C(2019557386), // SAT_S_H |
| 1714 | UINT64_C(2017460234), // SAT_S_W |
| 1715 | UINT64_C(2028994570), // SAT_U_B |
| 1716 | UINT64_C(2021654538), // SAT_U_D |
| 1717 | UINT64_C(2027945994), // SAT_U_H |
| 1718 | UINT64_C(2025848842), // SAT_U_W |
| 1719 | UINT64_C(2684354560), // SB |
| 1720 | UINT64_C(34816), // SB16_MM |
| 1721 | UINT64_C(34816), // SB16_MMR6 |
| 1722 | UINT64_C(2684354560), // SB64 |
| 1723 | UINT64_C(2080374812), // SBE |
| 1724 | UINT64_C(1610655744), // SBE_MM |
| 1725 | UINT64_C(402653184), // SB_MM |
| 1726 | UINT64_C(402653184), // SB_MMR6 |
| 1727 | UINT64_C(3758096384), // SC |
| 1728 | UINT64_C(3758096384), // SC64 |
| 1729 | UINT64_C(2080374822), // SC64_R6 |
| 1730 | UINT64_C(4026531840), // SCD |
| 1731 | UINT64_C(2080374823), // SCD_R6 |
| 1732 | UINT64_C(2080374814), // SCE |
| 1733 | UINT64_C(1610656768), // SCE_MM |
| 1734 | UINT64_C(1610657792), // SC_MM |
| 1735 | UINT64_C(1610657792), // SC_MMR6 |
| 1736 | UINT64_C(2080374822), // SC_R6 |
| 1737 | UINT64_C(4227858432), // SD |
| 1738 | UINT64_C(1879048255), // SDBBP |
| 1739 | UINT64_C(18112), // SDBBP16_MM |
| 1740 | UINT64_C(17467), // SDBBP16_MMR6 |
| 1741 | UINT64_C(56188), // SDBBP_MM |
| 1742 | UINT64_C(56188), // SDBBP_MMR6 |
| 1743 | UINT64_C(14), // SDBBP_R6 |
| 1744 | UINT64_C(4093640704), // SDC1 |
| 1745 | UINT64_C(4093640704), // SDC164 |
| 1746 | UINT64_C(3087007744), // SDC1_D64_MMR6 |
| 1747 | UINT64_C(3087007744), // SDC1_MM_D32 |
| 1748 | UINT64_C(3087007744), // SDC1_MM_D64 |
| 1749 | UINT64_C(4160749568), // SDC2 |
| 1750 | UINT64_C(536911872), // SDC2_MMR6 |
| 1751 | UINT64_C(1239416832), // SDC2_R6 |
| 1752 | UINT64_C(4227858432), // SDC3 |
| 1753 | UINT64_C(26), // SDIV |
| 1754 | UINT64_C(43836), // SDIV_MM |
| 1755 | UINT64_C(2952790016), // SDL |
| 1756 | UINT64_C(3019898880), // SDR |
| 1757 | UINT64_C(1275068425), // SDXC1 |
| 1758 | UINT64_C(1275068425), // SDXC164 |
| 1759 | UINT64_C(2080375840), // SEB |
| 1760 | UINT64_C(2080375840), // SEB64 |
| 1761 | UINT64_C(11068), // SEB_MM |
| 1762 | UINT64_C(2080376352), // SEH |
| 1763 | UINT64_C(2080376352), // SEH64 |
| 1764 | UINT64_C(15164), // SEH_MM |
| 1765 | UINT64_C(53), // SELEQZ |
| 1766 | UINT64_C(53), // SELEQZ64 |
| 1767 | UINT64_C(1176502292), // SELEQZ_D |
| 1768 | UINT64_C(1409286712), // SELEQZ_D_MMR6 |
| 1769 | UINT64_C(320), // SELEQZ_MMR6 |
| 1770 | UINT64_C(1174405140), // SELEQZ_S |
| 1771 | UINT64_C(1409286200), // SELEQZ_S_MMR6 |
| 1772 | UINT64_C(55), // SELNEZ |
| 1773 | UINT64_C(55), // SELNEZ64 |
| 1774 | UINT64_C(1176502295), // SELNEZ_D |
| 1775 | UINT64_C(1409286776), // SELNEZ_D_MMR6 |
| 1776 | UINT64_C(384), // SELNEZ_MMR6 |
| 1777 | UINT64_C(1174405143), // SELNEZ_S |
| 1778 | UINT64_C(1409286264), // SELNEZ_S_MMR6 |
| 1779 | UINT64_C(1176502288), // SEL_D |
| 1780 | UINT64_C(1409286840), // SEL_D_MMR6 |
| 1781 | UINT64_C(1174405136), // SEL_S |
| 1782 | UINT64_C(1409286328), // SEL_S_MMR6 |
| 1783 | UINT64_C(1879048234), // SEQ |
| 1784 | UINT64_C(1879048238), // SEQi |
| 1785 | UINT64_C(2751463424), // SH |
| 1786 | UINT64_C(43008), // SH16_MM |
| 1787 | UINT64_C(43008), // SH16_MMR6 |
| 1788 | UINT64_C(2751463424), // SH64 |
| 1789 | UINT64_C(2080374813), // SHE |
| 1790 | UINT64_C(1610656256), // SHE_MM |
| 1791 | UINT64_C(2013265922), // SHF_B |
| 1792 | UINT64_C(2030043138), // SHF_H |
| 1793 | UINT64_C(2046820354), // SHF_W |
| 1794 | UINT64_C(2080376504), // SHILO |
| 1795 | UINT64_C(2080376568), // SHILOV |
| 1796 | UINT64_C(4732), // SHILOV_MM |
| 1797 | UINT64_C(29), // SHILO_MM |
| 1798 | UINT64_C(2080375443), // SHLLV_PH |
| 1799 | UINT64_C(14), // SHLLV_PH_MM |
| 1800 | UINT64_C(2080374931), // SHLLV_QB |
| 1801 | UINT64_C(917), // SHLLV_QB_MM |
| 1802 | UINT64_C(2080375699), // SHLLV_S_PH |
| 1803 | UINT64_C(1038), // SHLLV_S_PH_MM |
| 1804 | UINT64_C(2080376211), // SHLLV_S_W |
| 1805 | UINT64_C(981), // SHLLV_S_W_MM |
| 1806 | UINT64_C(2080375315), // SHLL_PH |
| 1807 | UINT64_C(949), // SHLL_PH_MM |
| 1808 | UINT64_C(2080374803), // SHLL_QB |
| 1809 | UINT64_C(2172), // SHLL_QB_MM |
| 1810 | UINT64_C(2080375571), // SHLL_S_PH |
| 1811 | UINT64_C(2997), // SHLL_S_PH_MM |
| 1812 | UINT64_C(2080376083), // SHLL_S_W |
| 1813 | UINT64_C(1013), // SHLL_S_W_MM |
| 1814 | UINT64_C(2080375507), // SHRAV_PH |
| 1815 | UINT64_C(397), // SHRAV_PH_MM |
| 1816 | UINT64_C(2080375187), // SHRAV_QB |
| 1817 | UINT64_C(461), // SHRAV_QB_MMR2 |
| 1818 | UINT64_C(2080375763), // SHRAV_R_PH |
| 1819 | UINT64_C(1421), // SHRAV_R_PH_MM |
| 1820 | UINT64_C(2080375251), // SHRAV_R_QB |
| 1821 | UINT64_C(1485), // SHRAV_R_QB_MMR2 |
| 1822 | UINT64_C(2080376275), // SHRAV_R_W |
| 1823 | UINT64_C(725), // SHRAV_R_W_MM |
| 1824 | UINT64_C(2080375379), // SHRA_PH |
| 1825 | UINT64_C(821), // SHRA_PH_MM |
| 1826 | UINT64_C(2080375059), // SHRA_QB |
| 1827 | UINT64_C(508), // SHRA_QB_MMR2 |
| 1828 | UINT64_C(2080375635), // SHRA_R_PH |
| 1829 | UINT64_C(1845), // SHRA_R_PH_MM |
| 1830 | UINT64_C(2080375123), // SHRA_R_QB |
| 1831 | UINT64_C(4604), // SHRA_R_QB_MMR2 |
| 1832 | UINT64_C(2080376147), // SHRA_R_W |
| 1833 | UINT64_C(757), // SHRA_R_W_MM |
| 1834 | UINT64_C(2080376531), // SHRLV_PH |
| 1835 | UINT64_C(789), // SHRLV_PH_MMR2 |
| 1836 | UINT64_C(2080374995), // SHRLV_QB |
| 1837 | UINT64_C(853), // SHRLV_QB_MM |
| 1838 | UINT64_C(2080376403), // SHRL_PH |
| 1839 | UINT64_C(1020), // SHRL_PH_MMR2 |
| 1840 | UINT64_C(2080374867), // SHRL_QB |
| 1841 | UINT64_C(6268), // SHRL_QB_MM |
| 1842 | UINT64_C(939524096), // SH_MM |
| 1843 | UINT64_C(939524096), // SH_MMR6 |
| 1844 | UINT64_C(68616192), // SIGRIE |
| 1845 | UINT64_C(63), // SIGRIE_MMR6 |
| 1846 | UINT64_C(2013265945), // SLDI_B |
| 1847 | UINT64_C(2016935961), // SLDI_D |
| 1848 | UINT64_C(2015363097), // SLDI_H |
| 1849 | UINT64_C(2016411673), // SLDI_W |
| 1850 | UINT64_C(2013265940), // SLD_B |
| 1851 | UINT64_C(2019557396), // SLD_D |
| 1852 | UINT64_C(2015363092), // SLD_H |
| 1853 | UINT64_C(2017460244), // SLD_W |
| 1854 | UINT64_C(0), // SLL |
| 1855 | UINT64_C(9216), // SLL16_MM |
| 1856 | UINT64_C(9216), // SLL16_MMR6 |
| 1857 | UINT64_C(0), // SLL64_32 |
| 1858 | UINT64_C(0), // SLL64_64 |
| 1859 | UINT64_C(2020605961), // SLLI_B |
| 1860 | UINT64_C(2013265929), // SLLI_D |
| 1861 | UINT64_C(2019557385), // SLLI_H |
| 1862 | UINT64_C(2017460233), // SLLI_W |
| 1863 | UINT64_C(4), // SLLV |
| 1864 | UINT64_C(16), // SLLV_MM |
| 1865 | UINT64_C(2013265933), // SLL_B |
| 1866 | UINT64_C(2019557389), // SLL_D |
| 1867 | UINT64_C(2015363085), // SLL_H |
| 1868 | UINT64_C(0), // SLL_MM |
| 1869 | UINT64_C(0), // SLL_MMR6 |
| 1870 | UINT64_C(2017460237), // SLL_W |
| 1871 | UINT64_C(42), // SLT |
| 1872 | UINT64_C(42), // SLT64 |
| 1873 | UINT64_C(848), // SLT_MM |
| 1874 | UINT64_C(671088640), // SLTi |
| 1875 | UINT64_C(671088640), // SLTi64 |
| 1876 | UINT64_C(2415919104), // SLTi_MM |
| 1877 | UINT64_C(738197504), // SLTiu |
| 1878 | UINT64_C(738197504), // SLTiu64 |
| 1879 | UINT64_C(2952790016), // SLTiu_MM |
| 1880 | UINT64_C(43), // SLTu |
| 1881 | UINT64_C(43), // SLTu64 |
| 1882 | UINT64_C(912), // SLTu_MM |
| 1883 | UINT64_C(1879048235), // SNE |
| 1884 | UINT64_C(1879048239), // SNEi |
| 1885 | UINT64_C(2017460249), // SPLATI_B |
| 1886 | UINT64_C(2021130265), // SPLATI_D |
| 1887 | UINT64_C(2019557401), // SPLATI_H |
| 1888 | UINT64_C(2020605977), // SPLATI_W |
| 1889 | UINT64_C(2021654548), // SPLAT_B |
| 1890 | UINT64_C(2027946004), // SPLAT_D |
| 1891 | UINT64_C(2023751700), // SPLAT_H |
| 1892 | UINT64_C(2025848852), // SPLAT_W |
| 1893 | UINT64_C(3), // SRA |
| 1894 | UINT64_C(2028994569), // SRAI_B |
| 1895 | UINT64_C(2021654537), // SRAI_D |
| 1896 | UINT64_C(2027945993), // SRAI_H |
| 1897 | UINT64_C(2025848841), // SRAI_W |
| 1898 | UINT64_C(2037383178), // SRARI_B |
| 1899 | UINT64_C(2030043146), // SRARI_D |
| 1900 | UINT64_C(2036334602), // SRARI_H |
| 1901 | UINT64_C(2034237450), // SRARI_W |
| 1902 | UINT64_C(2021654549), // SRAR_B |
| 1903 | UINT64_C(2027946005), // SRAR_D |
| 1904 | UINT64_C(2023751701), // SRAR_H |
| 1905 | UINT64_C(2025848853), // SRAR_W |
| 1906 | UINT64_C(7), // SRAV |
| 1907 | UINT64_C(144), // SRAV_MM |
| 1908 | UINT64_C(2021654541), // SRA_B |
| 1909 | UINT64_C(2027945997), // SRA_D |
| 1910 | UINT64_C(2023751693), // SRA_H |
| 1911 | UINT64_C(128), // SRA_MM |
| 1912 | UINT64_C(2025848845), // SRA_W |
| 1913 | UINT64_C(2), // SRL |
| 1914 | UINT64_C(9217), // SRL16_MM |
| 1915 | UINT64_C(9217), // SRL16_MMR6 |
| 1916 | UINT64_C(2037383177), // SRLI_B |
| 1917 | UINT64_C(2030043145), // SRLI_D |
| 1918 | UINT64_C(2036334601), // SRLI_H |
| 1919 | UINT64_C(2034237449), // SRLI_W |
| 1920 | UINT64_C(2045771786), // SRLRI_B |
| 1921 | UINT64_C(2038431754), // SRLRI_D |
| 1922 | UINT64_C(2044723210), // SRLRI_H |
| 1923 | UINT64_C(2042626058), // SRLRI_W |
| 1924 | UINT64_C(2030043157), // SRLR_B |
| 1925 | UINT64_C(2036334613), // SRLR_D |
| 1926 | UINT64_C(2032140309), // SRLR_H |
| 1927 | UINT64_C(2034237461), // SRLR_W |
| 1928 | UINT64_C(6), // SRLV |
| 1929 | UINT64_C(80), // SRLV_MM |
| 1930 | UINT64_C(2030043149), // SRL_B |
| 1931 | UINT64_C(2036334605), // SRL_D |
| 1932 | UINT64_C(2032140301), // SRL_H |
| 1933 | UINT64_C(64), // SRL_MM |
| 1934 | UINT64_C(2034237453), // SRL_W |
| 1935 | UINT64_C(64), // SSNOP |
| 1936 | UINT64_C(2048), // SSNOP_MM |
| 1937 | UINT64_C(2048), // SSNOP_MMR6 |
| 1938 | UINT64_C(2013265956), // ST_B |
| 1939 | UINT64_C(2013265959), // ST_D |
| 1940 | UINT64_C(2013265957), // ST_H |
| 1941 | UINT64_C(2013265958), // ST_W |
| 1942 | UINT64_C(34), // SUB |
| 1943 | UINT64_C(2080375384), // SUBQH_PH |
| 1944 | UINT64_C(589), // SUBQH_PH_MMR2 |
| 1945 | UINT64_C(2080375512), // SUBQH_R_PH |
| 1946 | UINT64_C(1613), // SUBQH_R_PH_MMR2 |
| 1947 | UINT64_C(2080376024), // SUBQH_R_W |
| 1948 | UINT64_C(1677), // SUBQH_R_W_MMR2 |
| 1949 | UINT64_C(2080375896), // SUBQH_W |
| 1950 | UINT64_C(653), // SUBQH_W_MMR2 |
| 1951 | UINT64_C(2080375504), // SUBQ_PH |
| 1952 | UINT64_C(525), // SUBQ_PH_MM |
| 1953 | UINT64_C(2080375760), // SUBQ_S_PH |
| 1954 | UINT64_C(1549), // SUBQ_S_PH_MM |
| 1955 | UINT64_C(2080376272), // SUBQ_S_W |
| 1956 | UINT64_C(837), // SUBQ_S_W_MM |
| 1957 | UINT64_C(2030043153), // SUBSUS_U_B |
| 1958 | UINT64_C(2036334609), // SUBSUS_U_D |
| 1959 | UINT64_C(2032140305), // SUBSUS_U_H |
| 1960 | UINT64_C(2034237457), // SUBSUS_U_W |
| 1961 | UINT64_C(2038431761), // SUBSUU_S_B |
| 1962 | UINT64_C(2044723217), // SUBSUU_S_D |
| 1963 | UINT64_C(2040528913), // SUBSUU_S_H |
| 1964 | UINT64_C(2042626065), // SUBSUU_S_W |
| 1965 | UINT64_C(2013265937), // SUBS_S_B |
| 1966 | UINT64_C(2019557393), // SUBS_S_D |
| 1967 | UINT64_C(2015363089), // SUBS_S_H |
| 1968 | UINT64_C(2017460241), // SUBS_S_W |
| 1969 | UINT64_C(2021654545), // SUBS_U_B |
| 1970 | UINT64_C(2027946001), // SUBS_U_D |
| 1971 | UINT64_C(2023751697), // SUBS_U_H |
| 1972 | UINT64_C(2025848849), // SUBS_U_W |
| 1973 | UINT64_C(1025), // SUBU16_MM |
| 1974 | UINT64_C(1025), // SUBU16_MMR6 |
| 1975 | UINT64_C(2080374872), // SUBUH_QB |
| 1976 | UINT64_C(845), // SUBUH_QB_MMR2 |
| 1977 | UINT64_C(2080375000), // SUBUH_R_QB |
| 1978 | UINT64_C(1869), // SUBUH_R_QB_MMR2 |
| 1979 | UINT64_C(464), // SUBU_MMR6 |
| 1980 | UINT64_C(2080375376), // SUBU_PH |
| 1981 | UINT64_C(781), // SUBU_PH_MMR2 |
| 1982 | UINT64_C(2080374864), // SUBU_QB |
| 1983 | UINT64_C(717), // SUBU_QB_MM |
| 1984 | UINT64_C(2080375632), // SUBU_S_PH |
| 1985 | UINT64_C(1805), // SUBU_S_PH_MMR2 |
| 1986 | UINT64_C(2080375120), // SUBU_S_QB |
| 1987 | UINT64_C(1741), // SUBU_S_QB_MM |
| 1988 | UINT64_C(2021654534), // SUBVI_B |
| 1989 | UINT64_C(2027945990), // SUBVI_D |
| 1990 | UINT64_C(2023751686), // SUBVI_H |
| 1991 | UINT64_C(2025848838), // SUBVI_W |
| 1992 | UINT64_C(2021654542), // SUBV_B |
| 1993 | UINT64_C(2027945998), // SUBV_D |
| 1994 | UINT64_C(2023751694), // SUBV_H |
| 1995 | UINT64_C(2025848846), // SUBV_W |
| 1996 | UINT64_C(400), // SUB_MM |
| 1997 | UINT64_C(400), // SUB_MMR6 |
| 1998 | UINT64_C(35), // SUBu |
| 1999 | UINT64_C(464), // SUBu_MM |
| 2000 | UINT64_C(1275068429), // SUXC1 |
| 2001 | UINT64_C(1275068429), // SUXC164 |
| 2002 | UINT64_C(1409286536), // SUXC1_MM |
| 2003 | UINT64_C(2885681152), // SW |
| 2004 | UINT64_C(59392), // SW16_MM |
| 2005 | UINT64_C(59392), // SW16_MMR6 |
| 2006 | UINT64_C(2885681152), // SW64 |
| 2007 | UINT64_C(3825205248), // SWC1 |
| 2008 | UINT64_C(2550136832), // SWC1_MM |
| 2009 | UINT64_C(3892314112), // SWC2 |
| 2010 | UINT64_C(536903680), // SWC2_MMR6 |
| 2011 | UINT64_C(1231028224), // SWC2_R6 |
| 2012 | UINT64_C(3959422976), // SWC3 |
| 2013 | UINT64_C(2885681152), // SWDSP |
| 2014 | UINT64_C(4160749568), // SWDSP_MM |
| 2015 | UINT64_C(2080374815), // SWE |
| 2016 | UINT64_C(1610657280), // SWE_MM |
| 2017 | UINT64_C(2818572288), // SWL |
| 2018 | UINT64_C(2818572288), // SWL64 |
| 2019 | UINT64_C(2080374817), // SWLE |
| 2020 | UINT64_C(1610653696), // SWLE_MM |
| 2021 | UINT64_C(1610645504), // SWL_MM |
| 2022 | UINT64_C(17728), // SWM16_MM |
| 2023 | UINT64_C(17418), // SWM16_MMR6 |
| 2024 | UINT64_C(536924160), // SWM32_MM |
| 2025 | UINT64_C(536907776), // SWP_MM |
| 2026 | UINT64_C(3087007744), // SWR |
| 2027 | UINT64_C(3087007744), // SWR64 |
| 2028 | UINT64_C(2080374818), // SWRE |
| 2029 | UINT64_C(1610654208), // SWRE_MM |
| 2030 | UINT64_C(1610649600), // SWR_MM |
| 2031 | UINT64_C(51200), // SWSP_MM |
| 2032 | UINT64_C(51200), // SWSP_MMR6 |
| 2033 | UINT64_C(1275068424), // SWXC1 |
| 2034 | UINT64_C(1409286280), // SWXC1_MM |
| 2035 | UINT64_C(4160749568), // SW_MM |
| 2036 | UINT64_C(4160749568), // SW_MMR6 |
| 2037 | UINT64_C(15), // SYNC |
| 2038 | UINT64_C(69140480), // SYNCI |
| 2039 | UINT64_C(1107296256), // SYNCI_MM |
| 2040 | UINT64_C(1098907648), // SYNCI_MMR6 |
| 2041 | UINT64_C(27516), // SYNC_MM |
| 2042 | UINT64_C(27516), // SYNC_MMR6 |
| 2043 | UINT64_C(12), // SYSCALL |
| 2044 | UINT64_C(35708), // SYSCALL_MM |
| 2045 | UINT64_C(25728), // Save16 |
| 2046 | UINT64_C(25728), // SaveX16 |
| 2047 | UINT64_C(4026580992), // SbRxRyOffMemX16 |
| 2048 | UINT64_C(59537), // SebRx16 |
| 2049 | UINT64_C(59569), // SehRx16 |
| 2050 | UINT64_C(4026583040), // ShRxRyOffMemX16 |
| 2051 | UINT64_C(4026544128), // SllX16 |
| 2052 | UINT64_C(59396), // SllvRxRy16 |
| 2053 | UINT64_C(59394), // SltRxRy16 |
| 2054 | UINT64_C(20480), // SltiRxImm16 |
| 2055 | UINT64_C(4026552320), // SltiRxImmX16 |
| 2056 | UINT64_C(22528), // SltiuRxImm16 |
| 2057 | UINT64_C(4026554368), // SltiuRxImmX16 |
| 2058 | UINT64_C(59395), // SltuRxRy16 |
| 2059 | UINT64_C(4026544131), // SraX16 |
| 2060 | UINT64_C(59399), // SravRxRy16 |
| 2061 | UINT64_C(4026544130), // SrlX16 |
| 2062 | UINT64_C(59398), // SrlvRxRy16 |
| 2063 | UINT64_C(57347), // SubuRxRyRz16 |
| 2064 | UINT64_C(4026587136), // SwRxRyOffMemX16 |
| 2065 | UINT64_C(4026585088), // SwRxSpImmX16 |
| 2066 | UINT64_C(52), // TEQ |
| 2067 | UINT64_C(67895296), // TEQI |
| 2068 | UINT64_C(1103101952), // TEQI_MM |
| 2069 | UINT64_C(60), // TEQ_MM |
| 2070 | UINT64_C(48), // TGE |
| 2071 | UINT64_C(67633152), // TGEI |
| 2072 | UINT64_C(67698688), // TGEIU |
| 2073 | UINT64_C(1096810496), // TGEIU_MM |
| 2074 | UINT64_C(1092616192), // TGEI_MM |
| 2075 | UINT64_C(49), // TGEU |
| 2076 | UINT64_C(1084), // TGEU_MM |
| 2077 | UINT64_C(572), // TGE_MM |
| 2078 | UINT64_C(1107296267), // TLBGINV |
| 2079 | UINT64_C(1107296268), // TLBGINVF |
| 2080 | UINT64_C(20860), // TLBGINVF_MM |
| 2081 | UINT64_C(16764), // TLBGINV_MM |
| 2082 | UINT64_C(1107296272), // TLBGP |
| 2083 | UINT64_C(380), // TLBGP_MM |
| 2084 | UINT64_C(1107296265), // TLBGR |
| 2085 | UINT64_C(4476), // TLBGR_MM |
| 2086 | UINT64_C(1107296266), // TLBGWI |
| 2087 | UINT64_C(8572), // TLBGWI_MM |
| 2088 | UINT64_C(1107296270), // TLBGWR |
| 2089 | UINT64_C(12668), // TLBGWR_MM |
| 2090 | UINT64_C(1107296259), // TLBINV |
| 2091 | UINT64_C(1107296260), // TLBINVF |
| 2092 | UINT64_C(21372), // TLBINVF_MMR6 |
| 2093 | UINT64_C(17276), // TLBINV_MMR6 |
| 2094 | UINT64_C(1107296264), // TLBP |
| 2095 | UINT64_C(892), // TLBP_MM |
| 2096 | UINT64_C(1107296257), // TLBR |
| 2097 | UINT64_C(4988), // TLBR_MM |
| 2098 | UINT64_C(1107296258), // TLBWI |
| 2099 | UINT64_C(9084), // TLBWI_MM |
| 2100 | UINT64_C(1107296262), // TLBWR |
| 2101 | UINT64_C(13180), // TLBWR_MM |
| 2102 | UINT64_C(50), // TLT |
| 2103 | UINT64_C(67764224), // TLTI |
| 2104 | UINT64_C(1094713344), // TLTIU_MM |
| 2105 | UINT64_C(1090519040), // TLTI_MM |
| 2106 | UINT64_C(51), // TLTU |
| 2107 | UINT64_C(2620), // TLTU_MM |
| 2108 | UINT64_C(2108), // TLT_MM |
| 2109 | UINT64_C(54), // TNE |
| 2110 | UINT64_C(68026368), // TNEI |
| 2111 | UINT64_C(1098907648), // TNEI_MM |
| 2112 | UINT64_C(3132), // TNE_MM |
| 2113 | UINT64_C(1176502281), // TRUNC_L_D64 |
| 2114 | UINT64_C(1409311547), // TRUNC_L_D_MMR6 |
| 2115 | UINT64_C(1174405129), // TRUNC_L_S |
| 2116 | UINT64_C(1409295163), // TRUNC_L_S_MMR6 |
| 2117 | UINT64_C(1176502285), // TRUNC_W_D32 |
| 2118 | UINT64_C(1176502285), // TRUNC_W_D64 |
| 2119 | UINT64_C(1409313595), // TRUNC_W_D_MMR6 |
| 2120 | UINT64_C(1409313595), // TRUNC_W_MM |
| 2121 | UINT64_C(1174405133), // TRUNC_W_S |
| 2122 | UINT64_C(1409297211), // TRUNC_W_S_MM |
| 2123 | UINT64_C(1409297211), // TRUNC_W_S_MMR6 |
| 2124 | UINT64_C(67829760), // TTLTIU |
| 2125 | UINT64_C(27), // UDIV |
| 2126 | UINT64_C(47932), // UDIV_MM |
| 2127 | UINT64_C(1879048209), // V3MULU |
| 2128 | UINT64_C(1879048208), // VMM0 |
| 2129 | UINT64_C(1879048207), // VMULU |
| 2130 | UINT64_C(2013265941), // VSHF_B |
| 2131 | UINT64_C(2019557397), // VSHF_D |
| 2132 | UINT64_C(2015363093), // VSHF_H |
| 2133 | UINT64_C(2017460245), // VSHF_W |
| 2134 | UINT64_C(1107296288), // WAIT |
| 2135 | UINT64_C(37756), // WAIT_MM |
| 2136 | UINT64_C(37756), // WAIT_MMR6 |
| 2137 | UINT64_C(2080376056), // WRDSP |
| 2138 | UINT64_C(5756), // WRDSP_MM |
| 2139 | UINT64_C(61820), // WRPGPR_MMR6 |
| 2140 | UINT64_C(2080374944), // WSBH |
| 2141 | UINT64_C(31548), // WSBH_MM |
| 2142 | UINT64_C(31548), // WSBH_MMR6 |
| 2143 | UINT64_C(38), // XOR |
| 2144 | UINT64_C(17472), // XOR16_MM |
| 2145 | UINT64_C(17416), // XOR16_MMR6 |
| 2146 | UINT64_C(38), // XOR64 |
| 2147 | UINT64_C(2063597568), // XORI_B |
| 2148 | UINT64_C(1879048192), // XORI_MMR6 |
| 2149 | UINT64_C(784), // XOR_MM |
| 2150 | UINT64_C(784), // XOR_MMR6 |
| 2151 | UINT64_C(2019557406), // XOR_V |
| 2152 | UINT64_C(939524096), // XORi |
| 2153 | UINT64_C(939524096), // XORi64 |
| 2154 | UINT64_C(1879048192), // XORi_MM |
| 2155 | UINT64_C(59406), // XorRxRxRy16 |
| 2156 | UINT64_C(2080374793), // YIELD |
| 2157 | }; |
| 2158 | constexpr unsigned FirstSupportedOpcode = 788; |
| 2159 | |
| 2160 | const unsigned opcode = MI.getOpcode(); |
| 2161 | if (opcode < FirstSupportedOpcode) |
| 2162 | reportUnsupportedInst(Inst: MI); |
| 2163 | unsigned TableIndex = opcode - FirstSupportedOpcode; |
| 2164 | uint64_t Value = InstBits[TableIndex]; |
| 2165 | uint64_t op = 0; |
| 2166 | (void)op; // suppress warning |
| 2167 | switch (opcode) { |
| 2168 | case Mips::Break16: |
| 2169 | case Mips::DERET: |
| 2170 | case Mips::DERET_MM: |
| 2171 | case Mips::DERET_MMR6: |
| 2172 | case Mips::EHB: |
| 2173 | case Mips::EHB_MM: |
| 2174 | case Mips::EHB_MMR6: |
| 2175 | case Mips::ERET: |
| 2176 | case Mips::ERETNC: |
| 2177 | case Mips::ERETNC_MMR6: |
| 2178 | case Mips::ERET_MM: |
| 2179 | case Mips::ERET_MMR6: |
| 2180 | case Mips::JrRa16: |
| 2181 | case Mips::JrcRa16: |
| 2182 | case Mips::NAL: |
| 2183 | case Mips::PAUSE: |
| 2184 | case Mips::PAUSE_MM: |
| 2185 | case Mips::PAUSE_MMR6: |
| 2186 | case Mips::Restore16: |
| 2187 | case Mips::RestoreX16: |
| 2188 | case Mips::SSNOP: |
| 2189 | case Mips::SSNOP_MM: |
| 2190 | case Mips::SSNOP_MMR6: |
| 2191 | case Mips::Save16: |
| 2192 | case Mips::SaveX16: |
| 2193 | case Mips::TLBGINV: |
| 2194 | case Mips::TLBGINVF: |
| 2195 | case Mips::TLBGINVF_MM: |
| 2196 | case Mips::TLBGINV_MM: |
| 2197 | case Mips::TLBGP: |
| 2198 | case Mips::TLBGP_MM: |
| 2199 | case Mips::TLBGR: |
| 2200 | case Mips::TLBGR_MM: |
| 2201 | case Mips::TLBGWI: |
| 2202 | case Mips::TLBGWI_MM: |
| 2203 | case Mips::TLBGWR: |
| 2204 | case Mips::TLBGWR_MM: |
| 2205 | case Mips::TLBINV: |
| 2206 | case Mips::TLBINVF: |
| 2207 | case Mips::TLBINVF_MMR6: |
| 2208 | case Mips::TLBINV_MMR6: |
| 2209 | case Mips::TLBP: |
| 2210 | case Mips::TLBP_MM: |
| 2211 | case Mips::TLBR: |
| 2212 | case Mips::TLBR_MM: |
| 2213 | case Mips::TLBWI: |
| 2214 | case Mips::TLBWI_MM: |
| 2215 | case Mips::TLBWR: |
| 2216 | case Mips::TLBWR_MM: |
| 2217 | case Mips::WAIT: { |
| 2218 | break; |
| 2219 | } |
| 2220 | case Mips::MTHLIP: |
| 2221 | case Mips::SHILOV: { |
| 2222 | // op: ac |
| 2223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2224 | Value |= (op & 0x3) << 11; |
| 2225 | // op: rs |
| 2226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2227 | Value |= (op & 0x1f) << 21; |
| 2228 | break; |
| 2229 | } |
| 2230 | case Mips::DPAQX_SA_W_PH: |
| 2231 | case Mips::DPAQX_S_W_PH: |
| 2232 | case Mips::DPAQ_SA_L_W: |
| 2233 | case Mips::DPAQ_S_W_PH: |
| 2234 | case Mips::DPAU_H_QBL: |
| 2235 | case Mips::DPAU_H_QBR: |
| 2236 | case Mips::DPAX_W_PH: |
| 2237 | case Mips::DPA_W_PH: |
| 2238 | case Mips::DPSQX_SA_W_PH: |
| 2239 | case Mips::DPSQX_S_W_PH: |
| 2240 | case Mips::DPSQ_SA_L_W: |
| 2241 | case Mips::DPSQ_S_W_PH: |
| 2242 | case Mips::DPSU_H_QBL: |
| 2243 | case Mips::DPSU_H_QBR: |
| 2244 | case Mips::DPSX_W_PH: |
| 2245 | case Mips::DPS_W_PH: |
| 2246 | case Mips::MADDU_DSP: |
| 2247 | case Mips::MADD_DSP: |
| 2248 | case Mips::MAQ_SA_W_PHL: |
| 2249 | case Mips::MAQ_SA_W_PHR: |
| 2250 | case Mips::MAQ_S_W_PHL: |
| 2251 | case Mips::MAQ_S_W_PHR: |
| 2252 | case Mips::MSUBU_DSP: |
| 2253 | case Mips::MSUB_DSP: |
| 2254 | case Mips::MULSAQ_S_W_PH: |
| 2255 | case Mips::MULSA_W_PH: |
| 2256 | case Mips::MULTU_DSP: |
| 2257 | case Mips::MULT_DSP: { |
| 2258 | // op: ac |
| 2259 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2260 | Value |= (op & 0x3) << 11; |
| 2261 | // op: rs |
| 2262 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2263 | Value |= (op & 0x1f) << 21; |
| 2264 | // op: rt |
| 2265 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2266 | Value |= (op & 0x1f) << 16; |
| 2267 | break; |
| 2268 | } |
| 2269 | case Mips::SHILO: { |
| 2270 | // op: ac |
| 2271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2272 | Value |= (op & 0x3) << 11; |
| 2273 | // op: shift |
| 2274 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2275 | Value |= (op & 0x3f) << 20; |
| 2276 | break; |
| 2277 | } |
| 2278 | case Mips::CACHEE: |
| 2279 | case Mips::CACHE_R6: |
| 2280 | case Mips::PREFE: |
| 2281 | case Mips::PREF_R6: { |
| 2282 | // op: addr |
| 2283 | op = getMemEncoding(MI, OpNo: 0, Fixups, STI); |
| 2284 | Value |= (op & 0x1f0000) << 5; |
| 2285 | Value |= (op & 0x1ff) << 7; |
| 2286 | // op: hint |
| 2287 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2288 | Value |= (op & 0x1f) << 16; |
| 2289 | break; |
| 2290 | } |
| 2291 | case Mips::SYNCI: { |
| 2292 | // op: addr |
| 2293 | op = getMemEncoding(MI, OpNo: 0, Fixups, STI); |
| 2294 | Value |= (op & 0x1f0000) << 5; |
| 2295 | Value |= (op & 0xffff); |
| 2296 | break; |
| 2297 | } |
| 2298 | case Mips::CACHE: |
| 2299 | case Mips::PREF: { |
| 2300 | // op: addr |
| 2301 | op = getMemEncoding(MI, OpNo: 0, Fixups, STI); |
| 2302 | Value |= (op & 0x1f0000) << 5; |
| 2303 | Value |= (op & 0xffff); |
| 2304 | // op: hint |
| 2305 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2306 | Value |= (op & 0x1f) << 16; |
| 2307 | break; |
| 2308 | } |
| 2309 | case Mips::LBE: |
| 2310 | case Mips::LBuE: |
| 2311 | case Mips::LHE: |
| 2312 | case Mips::LHuE: |
| 2313 | case Mips::LLE: |
| 2314 | case Mips::LWE: |
| 2315 | case Mips::LWLE: |
| 2316 | case Mips::LWRE: |
| 2317 | case Mips::SBE: |
| 2318 | case Mips::SHE: |
| 2319 | case Mips::SWE: |
| 2320 | case Mips::SWLE: |
| 2321 | case Mips::SWRE: { |
| 2322 | // op: addr |
| 2323 | op = getMemEncoding(MI, OpNo: 1, Fixups, STI); |
| 2324 | Value |= (op & 0x1f0000) << 5; |
| 2325 | Value |= (op & 0x1ff) << 7; |
| 2326 | // op: rt |
| 2327 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2328 | Value |= (op & 0x1f) << 16; |
| 2329 | break; |
| 2330 | } |
| 2331 | case Mips::LD_B: |
| 2332 | case Mips::ST_B: { |
| 2333 | // op: addr |
| 2334 | op = getMemEncoding(MI, OpNo: 1, Fixups, STI); |
| 2335 | Value |= (op & 0x3ff) << 16; |
| 2336 | Value |= (op & 0x1f0000) >> 5; |
| 2337 | // op: wd |
| 2338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2339 | Value |= (op & 0x1f) << 6; |
| 2340 | break; |
| 2341 | } |
| 2342 | case Mips::SCE: { |
| 2343 | // op: addr |
| 2344 | op = getMemEncoding(MI, OpNo: 2, Fixups, STI); |
| 2345 | Value |= (op & 0x1f0000) << 5; |
| 2346 | Value |= (op & 0x1ff) << 7; |
| 2347 | // op: rt |
| 2348 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2349 | Value |= (op & 0x1f) << 16; |
| 2350 | break; |
| 2351 | } |
| 2352 | case Mips::LD_H: |
| 2353 | case Mips::ST_H: { |
| 2354 | // op: addr |
| 2355 | op = getMemEncoding<1>(MI, OpNo: 1, Fixups, STI); |
| 2356 | Value |= (op & 0x3ff) << 16; |
| 2357 | Value |= (op & 0x1f0000) >> 5; |
| 2358 | // op: wd |
| 2359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2360 | Value |= (op & 0x1f) << 6; |
| 2361 | break; |
| 2362 | } |
| 2363 | case Mips::LD_W: |
| 2364 | case Mips::ST_W: { |
| 2365 | // op: addr |
| 2366 | op = getMemEncoding<2>(MI, OpNo: 1, Fixups, STI); |
| 2367 | Value |= (op & 0x3ff) << 16; |
| 2368 | Value |= (op & 0x1f0000) >> 5; |
| 2369 | // op: wd |
| 2370 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2371 | Value |= (op & 0x1f) << 6; |
| 2372 | break; |
| 2373 | } |
| 2374 | case Mips::LD_D: |
| 2375 | case Mips::ST_D: { |
| 2376 | // op: addr |
| 2377 | op = getMemEncoding<3>(MI, OpNo: 1, Fixups, STI); |
| 2378 | Value |= (op & 0x3ff) << 16; |
| 2379 | Value |= (op & 0x1f0000) >> 5; |
| 2380 | // op: wd |
| 2381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2382 | Value |= (op & 0x1f) << 6; |
| 2383 | break; |
| 2384 | } |
| 2385 | case Mips::CACHE_MM: |
| 2386 | case Mips::CACHE_MMR6: |
| 2387 | case Mips::PREF_MM: |
| 2388 | case Mips::PREF_MMR6: { |
| 2389 | // op: addr |
| 2390 | op = getMemEncodingMMImm12(MI, OpNo: 0, Fixups, STI); |
| 2391 | Value |= (op & 0x1f0000); |
| 2392 | Value |= (op & 0xfff); |
| 2393 | // op: hint |
| 2394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2395 | Value |= (op & 0x1f) << 21; |
| 2396 | break; |
| 2397 | } |
| 2398 | case Mips::SYNCI_MM: |
| 2399 | case Mips::SYNCI_MMR6: { |
| 2400 | // op: addr |
| 2401 | op = getMemEncodingMMImm16(MI, OpNo: 0, Fixups, STI); |
| 2402 | Value |= (op & 0x1fffff); |
| 2403 | break; |
| 2404 | } |
| 2405 | case Mips::LBU_MMR6: |
| 2406 | case Mips::LB_MMR6: { |
| 2407 | // op: addr |
| 2408 | op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI); |
| 2409 | Value |= (op & 0x1fffff); |
| 2410 | // op: rt |
| 2411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2412 | Value |= (op & 0x1f) << 21; |
| 2413 | break; |
| 2414 | } |
| 2415 | case Mips::CACHEE_MM: |
| 2416 | case Mips::PREFE_MM: { |
| 2417 | // op: addr |
| 2418 | op = getMemEncodingMMImm9(MI, OpNo: 0, Fixups, STI); |
| 2419 | Value |= (op & 0x1f0000); |
| 2420 | Value |= (op & 0x1ff); |
| 2421 | // op: hint |
| 2422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2423 | Value |= (op & 0x1f) << 21; |
| 2424 | break; |
| 2425 | } |
| 2426 | case Mips::HYPCALL: { |
| 2427 | // op: code_ |
| 2428 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2429 | Value |= (op & 0x3ff) << 11; |
| 2430 | break; |
| 2431 | } |
| 2432 | case Mips::HYPCALL_MM: |
| 2433 | case Mips::SDBBP_MM: |
| 2434 | case Mips::SDBBP_MMR6: |
| 2435 | case Mips::SYSCALL_MM: |
| 2436 | case Mips::WAIT_MM: |
| 2437 | case Mips::WAIT_MMR6: { |
| 2438 | // op: code_ |
| 2439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2440 | Value |= (op & 0x3ff) << 16; |
| 2441 | break; |
| 2442 | } |
| 2443 | case Mips::BREAK16_MMR6: |
| 2444 | case Mips::SDBBP16_MMR6: { |
| 2445 | // op: code_ |
| 2446 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2447 | Value |= (op & 0xf) << 6; |
| 2448 | break; |
| 2449 | } |
| 2450 | case Mips::BREAK16_MM: |
| 2451 | case Mips::SDBBP16_MM: { |
| 2452 | // op: code_ |
| 2453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2454 | Value |= (op & 0xf); |
| 2455 | break; |
| 2456 | } |
| 2457 | case Mips::SIGRIE_MMR6: { |
| 2458 | // op: code_ |
| 2459 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2460 | Value |= (op & 0xffff) << 6; |
| 2461 | break; |
| 2462 | } |
| 2463 | case Mips::SIGRIE: { |
| 2464 | // op: code_ |
| 2465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2466 | Value |= (op & 0xffff); |
| 2467 | break; |
| 2468 | } |
| 2469 | case Mips::SDBBP: |
| 2470 | case Mips::SDBBP_R6: |
| 2471 | case Mips::SYSCALL: { |
| 2472 | // op: code_ |
| 2473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2474 | Value |= (op & 0xfffff) << 6; |
| 2475 | break; |
| 2476 | } |
| 2477 | case Mips::BREAK: |
| 2478 | case Mips::BREAK_MM: |
| 2479 | case Mips::BREAK_MMR6: { |
| 2480 | // op: code_1 |
| 2481 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2482 | Value |= (op & 0x3ff) << 16; |
| 2483 | // op: code_2 |
| 2484 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2485 | Value |= (op & 0x3ff) << 6; |
| 2486 | break; |
| 2487 | } |
| 2488 | case Mips::BC2EQZ: |
| 2489 | case Mips::BC2NEZ: { |
| 2490 | // op: ct |
| 2491 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2492 | Value |= (op & 0x1f) << 16; |
| 2493 | // op: offset |
| 2494 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 2495 | Value |= (op & 0xffff); |
| 2496 | break; |
| 2497 | } |
| 2498 | case Mips::BC1F: |
| 2499 | case Mips::BC1FL: |
| 2500 | case Mips::BC1T: |
| 2501 | case Mips::BC1TL: { |
| 2502 | // op: fcc |
| 2503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2504 | Value |= (op & 0x7) << 18; |
| 2505 | // op: offset |
| 2506 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 2507 | Value |= (op & 0xffff); |
| 2508 | break; |
| 2509 | } |
| 2510 | case Mips::BC1F_MM: |
| 2511 | case Mips::BC1T_MM: { |
| 2512 | // op: fcc |
| 2513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2514 | Value |= (op & 0x7) << 18; |
| 2515 | // op: offset |
| 2516 | op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI); |
| 2517 | Value |= (op & 0xffff); |
| 2518 | break; |
| 2519 | } |
| 2520 | case Mips::LUXC1_MM: |
| 2521 | case Mips::LWXC1_MM: { |
| 2522 | // op: fd |
| 2523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2524 | Value |= (op & 0x1f) << 11; |
| 2525 | // op: base |
| 2526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2527 | Value |= (op & 0x1f) << 16; |
| 2528 | // op: index |
| 2529 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2530 | Value |= (op & 0x1f) << 21; |
| 2531 | break; |
| 2532 | } |
| 2533 | case Mips::MOVN_I_D32_MM: |
| 2534 | case Mips::MOVN_I_S_MM: |
| 2535 | case Mips::MOVZ_I_D32_MM: |
| 2536 | case Mips::MOVZ_I_S_MM: { |
| 2537 | // op: fd |
| 2538 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2539 | Value |= (op & 0x1f) << 11; |
| 2540 | // op: fs |
| 2541 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2542 | Value |= (op & 0x1f) << 16; |
| 2543 | // op: rt |
| 2544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2545 | Value |= (op & 0x1f) << 21; |
| 2546 | break; |
| 2547 | } |
| 2548 | case Mips::CEIL_W_MM: |
| 2549 | case Mips::CEIL_W_S_MM: |
| 2550 | case Mips::CVT_D32_S_MM: |
| 2551 | case Mips::CVT_D32_W_MM: |
| 2552 | case Mips::CVT_D64_S_MM: |
| 2553 | case Mips::CVT_D64_W_MM: |
| 2554 | case Mips::CVT_L_D64_MM: |
| 2555 | case Mips::CVT_L_S_MM: |
| 2556 | case Mips::CVT_S_D32_MM: |
| 2557 | case Mips::CVT_S_D64_MM: |
| 2558 | case Mips::CVT_S_W_MM: |
| 2559 | case Mips::CVT_W_D32_MM: |
| 2560 | case Mips::CVT_W_D64_MM: |
| 2561 | case Mips::CVT_W_S_MM: |
| 2562 | case Mips::FABS_D32_MM: |
| 2563 | case Mips::FABS_D64_MM: |
| 2564 | case Mips::FABS_S_MM: |
| 2565 | case Mips::FLOOR_W_MM: |
| 2566 | case Mips::FLOOR_W_S_MM: |
| 2567 | case Mips::FMOV_D32_MM: |
| 2568 | case Mips::FMOV_D64_MM: |
| 2569 | case Mips::FMOV_S_MM: |
| 2570 | case Mips::FNEG_D32_MM: |
| 2571 | case Mips::FNEG_D64_MM: |
| 2572 | case Mips::FNEG_S_MM: |
| 2573 | case Mips::FSQRT_D32_MM: |
| 2574 | case Mips::FSQRT_D64_MM: |
| 2575 | case Mips::FSQRT_S_MM: |
| 2576 | case Mips::RECIP_D32_MM: |
| 2577 | case Mips::RECIP_D64_MM: |
| 2578 | case Mips::RECIP_S_MM: |
| 2579 | case Mips::ROUND_W_MM: |
| 2580 | case Mips::ROUND_W_S_MM: |
| 2581 | case Mips::RSQRT_D32_MM: |
| 2582 | case Mips::RSQRT_D64_MM: |
| 2583 | case Mips::RSQRT_S_MM: |
| 2584 | case Mips::TRUNC_W_MM: |
| 2585 | case Mips::TRUNC_W_S_MM: { |
| 2586 | // op: fd |
| 2587 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2588 | Value |= (op & 0x1f) << 21; |
| 2589 | // op: fs |
| 2590 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2591 | Value |= (op & 0x1f) << 16; |
| 2592 | break; |
| 2593 | } |
| 2594 | case Mips::MOVF_D32_MM: |
| 2595 | case Mips::MOVF_S_MM: |
| 2596 | case Mips::MOVT_D32_MM: |
| 2597 | case Mips::MOVT_S_MM: { |
| 2598 | // op: fd |
| 2599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2600 | Value |= (op & 0x1f) << 21; |
| 2601 | // op: fs |
| 2602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2603 | Value |= (op & 0x1f) << 16; |
| 2604 | // op: fcc |
| 2605 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2606 | Value |= (op & 0x7) << 13; |
| 2607 | break; |
| 2608 | } |
| 2609 | case Mips::LDXC1: |
| 2610 | case Mips::LDXC164: |
| 2611 | case Mips::LUXC1: |
| 2612 | case Mips::LUXC164: |
| 2613 | case Mips::LWXC1: { |
| 2614 | // op: fd |
| 2615 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2616 | Value |= (op & 0x1f) << 6; |
| 2617 | // op: base |
| 2618 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2619 | Value |= (op & 0x1f) << 21; |
| 2620 | // op: index |
| 2621 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2622 | Value |= (op & 0x1f) << 16; |
| 2623 | break; |
| 2624 | } |
| 2625 | case Mips::MADD_D32: |
| 2626 | case Mips::MADD_D64: |
| 2627 | case Mips::MADD_S: |
| 2628 | case Mips::MSUB_D32: |
| 2629 | case Mips::MSUB_D64: |
| 2630 | case Mips::MSUB_S: |
| 2631 | case Mips::NMADD_D32: |
| 2632 | case Mips::NMADD_D64: |
| 2633 | case Mips::NMADD_S: |
| 2634 | case Mips::NMSUB_D32: |
| 2635 | case Mips::NMSUB_D64: |
| 2636 | case Mips::NMSUB_S: { |
| 2637 | // op: fd |
| 2638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2639 | Value |= (op & 0x1f) << 6; |
| 2640 | // op: fr |
| 2641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2642 | Value |= (op & 0x1f) << 21; |
| 2643 | // op: fs |
| 2644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2645 | Value |= (op & 0x1f) << 11; |
| 2646 | // op: ft |
| 2647 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2648 | Value |= (op & 0x1f) << 16; |
| 2649 | break; |
| 2650 | } |
| 2651 | case Mips::CEIL_L_D64: |
| 2652 | case Mips::CEIL_L_S: |
| 2653 | case Mips::CEIL_W_D32: |
| 2654 | case Mips::CEIL_W_D64: |
| 2655 | case Mips::CEIL_W_S: |
| 2656 | case Mips::CVT_D32_S: |
| 2657 | case Mips::CVT_D32_W: |
| 2658 | case Mips::CVT_D64_L: |
| 2659 | case Mips::CVT_D64_S: |
| 2660 | case Mips::CVT_D64_W: |
| 2661 | case Mips::CVT_L_D64: |
| 2662 | case Mips::CVT_L_S: |
| 2663 | case Mips::CVT_PS_PW64: |
| 2664 | case Mips::CVT_PW_PS64: |
| 2665 | case Mips::CVT_S_D32: |
| 2666 | case Mips::CVT_S_D64: |
| 2667 | case Mips::CVT_S_L: |
| 2668 | case Mips::CVT_S_PL64: |
| 2669 | case Mips::CVT_S_PU64: |
| 2670 | case Mips::CVT_S_W: |
| 2671 | case Mips::CVT_W_D32: |
| 2672 | case Mips::CVT_W_D64: |
| 2673 | case Mips::CVT_W_S: |
| 2674 | case Mips::FABS_D32: |
| 2675 | case Mips::FABS_D64: |
| 2676 | case Mips::FABS_S: |
| 2677 | case Mips::FLOOR_L_D64: |
| 2678 | case Mips::FLOOR_L_S: |
| 2679 | case Mips::FLOOR_W_D32: |
| 2680 | case Mips::FLOOR_W_D64: |
| 2681 | case Mips::FLOOR_W_S: |
| 2682 | case Mips::FMOV_D32: |
| 2683 | case Mips::FMOV_D64: |
| 2684 | case Mips::FMOV_S: |
| 2685 | case Mips::FNEG_D32: |
| 2686 | case Mips::FNEG_D64: |
| 2687 | case Mips::FNEG_S: |
| 2688 | case Mips::FSQRT_D32: |
| 2689 | case Mips::FSQRT_D64: |
| 2690 | case Mips::FSQRT_S: |
| 2691 | case Mips::RECIP_D32: |
| 2692 | case Mips::RECIP_D64: |
| 2693 | case Mips::RECIP_S: |
| 2694 | case Mips::ROUND_L_D64: |
| 2695 | case Mips::ROUND_L_S: |
| 2696 | case Mips::ROUND_W_D32: |
| 2697 | case Mips::ROUND_W_D64: |
| 2698 | case Mips::ROUND_W_S: |
| 2699 | case Mips::RSQRT_D32: |
| 2700 | case Mips::RSQRT_D64: |
| 2701 | case Mips::RSQRT_S: |
| 2702 | case Mips::TRUNC_L_D64: |
| 2703 | case Mips::TRUNC_L_S: |
| 2704 | case Mips::TRUNC_W_D32: |
| 2705 | case Mips::TRUNC_W_D64: |
| 2706 | case Mips::TRUNC_W_S: { |
| 2707 | // op: fd |
| 2708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2709 | Value |= (op & 0x1f) << 6; |
| 2710 | // op: fs |
| 2711 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2712 | Value |= (op & 0x1f) << 11; |
| 2713 | break; |
| 2714 | } |
| 2715 | case Mips::MOVF_D32: |
| 2716 | case Mips::MOVF_D64: |
| 2717 | case Mips::MOVF_S: |
| 2718 | case Mips::MOVT_D32: |
| 2719 | case Mips::MOVT_D64: |
| 2720 | case Mips::MOVT_S: { |
| 2721 | // op: fd |
| 2722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2723 | Value |= (op & 0x1f) << 6; |
| 2724 | // op: fs |
| 2725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2726 | Value |= (op & 0x1f) << 11; |
| 2727 | // op: fcc |
| 2728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2729 | Value |= (op & 0x7) << 18; |
| 2730 | break; |
| 2731 | } |
| 2732 | case Mips::ADDR_PS64: |
| 2733 | case Mips::CMP_EQ_D: |
| 2734 | case Mips::CMP_EQ_S: |
| 2735 | case Mips::CMP_F_D: |
| 2736 | case Mips::CMP_F_S: |
| 2737 | case Mips::CMP_LE_D: |
| 2738 | case Mips::CMP_LE_S: |
| 2739 | case Mips::CMP_LT_D: |
| 2740 | case Mips::CMP_LT_S: |
| 2741 | case Mips::CMP_SAF_D: |
| 2742 | case Mips::CMP_SAF_S: |
| 2743 | case Mips::CMP_SEQ_D: |
| 2744 | case Mips::CMP_SEQ_S: |
| 2745 | case Mips::CMP_SLE_D: |
| 2746 | case Mips::CMP_SLE_S: |
| 2747 | case Mips::CMP_SLT_D: |
| 2748 | case Mips::CMP_SLT_S: |
| 2749 | case Mips::CMP_SUEQ_D: |
| 2750 | case Mips::CMP_SUEQ_S: |
| 2751 | case Mips::CMP_SULE_D: |
| 2752 | case Mips::CMP_SULE_S: |
| 2753 | case Mips::CMP_SULT_D: |
| 2754 | case Mips::CMP_SULT_S: |
| 2755 | case Mips::CMP_SUN_D: |
| 2756 | case Mips::CMP_SUN_S: |
| 2757 | case Mips::CMP_UEQ_D: |
| 2758 | case Mips::CMP_UEQ_S: |
| 2759 | case Mips::CMP_ULE_D: |
| 2760 | case Mips::CMP_ULE_S: |
| 2761 | case Mips::CMP_ULT_D: |
| 2762 | case Mips::CMP_ULT_S: |
| 2763 | case Mips::CMP_UN_D: |
| 2764 | case Mips::CMP_UN_S: |
| 2765 | case Mips::CVT_PS_S64: |
| 2766 | case Mips::FADD_D32: |
| 2767 | case Mips::FADD_D64: |
| 2768 | case Mips::FADD_PS64: |
| 2769 | case Mips::FADD_S: |
| 2770 | case Mips::FDIV_D32: |
| 2771 | case Mips::FDIV_D64: |
| 2772 | case Mips::FDIV_S: |
| 2773 | case Mips::FMUL_D32: |
| 2774 | case Mips::FMUL_D64: |
| 2775 | case Mips::FMUL_PS64: |
| 2776 | case Mips::FMUL_S: |
| 2777 | case Mips::FSUB_D32: |
| 2778 | case Mips::FSUB_D64: |
| 2779 | case Mips::FSUB_PS64: |
| 2780 | case Mips::FSUB_S: |
| 2781 | case Mips::MULR_PS64: |
| 2782 | case Mips::PLL_PS64: |
| 2783 | case Mips::PLU_PS64: |
| 2784 | case Mips::PUL_PS64: |
| 2785 | case Mips::PUU_PS64: { |
| 2786 | // op: fd |
| 2787 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2788 | Value |= (op & 0x1f) << 6; |
| 2789 | // op: fs |
| 2790 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2791 | Value |= (op & 0x1f) << 11; |
| 2792 | // op: ft |
| 2793 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2794 | Value |= (op & 0x1f) << 16; |
| 2795 | break; |
| 2796 | } |
| 2797 | case Mips::MOVN_I64_D64: |
| 2798 | case Mips::MOVN_I64_S: |
| 2799 | case Mips::MOVN_I_D32: |
| 2800 | case Mips::MOVN_I_D64: |
| 2801 | case Mips::MOVN_I_S: |
| 2802 | case Mips::MOVZ_I64_D64: |
| 2803 | case Mips::MOVZ_I64_S: |
| 2804 | case Mips::MOVZ_I_D32: |
| 2805 | case Mips::MOVZ_I_D64: |
| 2806 | case Mips::MOVZ_I_S: { |
| 2807 | // op: fd |
| 2808 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2809 | Value |= (op & 0x1f) << 6; |
| 2810 | // op: fs |
| 2811 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2812 | Value |= (op & 0x1f) << 11; |
| 2813 | // op: rt |
| 2814 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2815 | Value |= (op & 0x1f) << 16; |
| 2816 | break; |
| 2817 | } |
| 2818 | case Mips::SUXC1_MM: |
| 2819 | case Mips::SWXC1_MM: { |
| 2820 | // op: fs |
| 2821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2822 | Value |= (op & 0x1f) << 11; |
| 2823 | // op: base |
| 2824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2825 | Value |= (op & 0x1f) << 16; |
| 2826 | // op: index |
| 2827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2828 | Value |= (op & 0x1f) << 21; |
| 2829 | break; |
| 2830 | } |
| 2831 | case Mips::SDXC1: |
| 2832 | case Mips::SDXC164: |
| 2833 | case Mips::SUXC1: |
| 2834 | case Mips::SUXC164: |
| 2835 | case Mips::SWXC1: { |
| 2836 | // op: fs |
| 2837 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2838 | Value |= (op & 0x1f) << 11; |
| 2839 | // op: base |
| 2840 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2841 | Value |= (op & 0x1f) << 21; |
| 2842 | // op: index |
| 2843 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2844 | Value |= (op & 0x1f) << 16; |
| 2845 | break; |
| 2846 | } |
| 2847 | case Mips::FCMP_D32: |
| 2848 | case Mips::FCMP_D64: |
| 2849 | case Mips::FCMP_S32: { |
| 2850 | // op: fs |
| 2851 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2852 | Value |= (op & 0x1f) << 11; |
| 2853 | // op: ft |
| 2854 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2855 | Value |= (op & 0x1f) << 16; |
| 2856 | // op: cond |
| 2857 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2858 | Value |= (op & 0xf); |
| 2859 | break; |
| 2860 | } |
| 2861 | case Mips::FCMP_D32_MM: |
| 2862 | case Mips::FCMP_S32_MM: { |
| 2863 | // op: fs |
| 2864 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2865 | Value |= (op & 0x1f) << 16; |
| 2866 | // op: ft |
| 2867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2868 | Value |= (op & 0x1f) << 21; |
| 2869 | // op: cond |
| 2870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2871 | Value |= (op & 0xf) << 6; |
| 2872 | break; |
| 2873 | } |
| 2874 | case Mips::CLASS_D: |
| 2875 | case Mips::CLASS_S: |
| 2876 | case Mips::RINT_D: |
| 2877 | case Mips::RINT_S: { |
| 2878 | // op: fs |
| 2879 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2880 | Value |= (op & 0x1f) << 11; |
| 2881 | // op: fd |
| 2882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2883 | Value |= (op & 0x1f) << 6; |
| 2884 | break; |
| 2885 | } |
| 2886 | case Mips::C_EQ_D32: |
| 2887 | case Mips::C_EQ_D64: |
| 2888 | case Mips::C_EQ_S: |
| 2889 | case Mips::C_F_D32: |
| 2890 | case Mips::C_F_D64: |
| 2891 | case Mips::C_F_S: |
| 2892 | case Mips::C_LE_D32: |
| 2893 | case Mips::C_LE_D64: |
| 2894 | case Mips::C_LE_S: |
| 2895 | case Mips::C_LT_D32: |
| 2896 | case Mips::C_LT_D64: |
| 2897 | case Mips::C_LT_S: |
| 2898 | case Mips::C_NGE_D32: |
| 2899 | case Mips::C_NGE_D64: |
| 2900 | case Mips::C_NGE_S: |
| 2901 | case Mips::C_NGLE_D32: |
| 2902 | case Mips::C_NGLE_D64: |
| 2903 | case Mips::C_NGLE_S: |
| 2904 | case Mips::C_NGL_D32: |
| 2905 | case Mips::C_NGL_D64: |
| 2906 | case Mips::C_NGL_S: |
| 2907 | case Mips::C_NGT_D32: |
| 2908 | case Mips::C_NGT_D64: |
| 2909 | case Mips::C_NGT_S: |
| 2910 | case Mips::C_OLE_D32: |
| 2911 | case Mips::C_OLE_D64: |
| 2912 | case Mips::C_OLE_S: |
| 2913 | case Mips::C_OLT_D32: |
| 2914 | case Mips::C_OLT_D64: |
| 2915 | case Mips::C_OLT_S: |
| 2916 | case Mips::C_SEQ_D32: |
| 2917 | case Mips::C_SEQ_D64: |
| 2918 | case Mips::C_SEQ_S: |
| 2919 | case Mips::C_SF_D32: |
| 2920 | case Mips::C_SF_D64: |
| 2921 | case Mips::C_SF_S: |
| 2922 | case Mips::C_UEQ_D32: |
| 2923 | case Mips::C_UEQ_D64: |
| 2924 | case Mips::C_UEQ_S: |
| 2925 | case Mips::C_ULE_D32: |
| 2926 | case Mips::C_ULE_D64: |
| 2927 | case Mips::C_ULE_S: |
| 2928 | case Mips::C_ULT_D32: |
| 2929 | case Mips::C_ULT_D64: |
| 2930 | case Mips::C_ULT_S: |
| 2931 | case Mips::C_UN_D32: |
| 2932 | case Mips::C_UN_D64: |
| 2933 | case Mips::C_UN_S: { |
| 2934 | // op: fs |
| 2935 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2936 | Value |= (op & 0x1f) << 11; |
| 2937 | // op: ft |
| 2938 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2939 | Value |= (op & 0x1f) << 16; |
| 2940 | // op: fcc |
| 2941 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2942 | Value |= (op & 0x7) << 8; |
| 2943 | break; |
| 2944 | } |
| 2945 | case Mips::C_EQ_D32_MM: |
| 2946 | case Mips::C_EQ_D64_MM: |
| 2947 | case Mips::C_EQ_S_MM: |
| 2948 | case Mips::C_F_D32_MM: |
| 2949 | case Mips::C_F_D64_MM: |
| 2950 | case Mips::C_F_S_MM: |
| 2951 | case Mips::C_LE_D32_MM: |
| 2952 | case Mips::C_LE_D64_MM: |
| 2953 | case Mips::C_LE_S_MM: |
| 2954 | case Mips::C_LT_D32_MM: |
| 2955 | case Mips::C_LT_D64_MM: |
| 2956 | case Mips::C_LT_S_MM: |
| 2957 | case Mips::C_NGE_D32_MM: |
| 2958 | case Mips::C_NGE_D64_MM: |
| 2959 | case Mips::C_NGE_S_MM: |
| 2960 | case Mips::C_NGLE_D32_MM: |
| 2961 | case Mips::C_NGLE_D64_MM: |
| 2962 | case Mips::C_NGLE_S_MM: |
| 2963 | case Mips::C_NGL_D32_MM: |
| 2964 | case Mips::C_NGL_D64_MM: |
| 2965 | case Mips::C_NGL_S_MM: |
| 2966 | case Mips::C_NGT_D32_MM: |
| 2967 | case Mips::C_NGT_D64_MM: |
| 2968 | case Mips::C_NGT_S_MM: |
| 2969 | case Mips::C_OLE_D32_MM: |
| 2970 | case Mips::C_OLE_D64_MM: |
| 2971 | case Mips::C_OLE_S_MM: |
| 2972 | case Mips::C_OLT_D32_MM: |
| 2973 | case Mips::C_OLT_D64_MM: |
| 2974 | case Mips::C_OLT_S_MM: |
| 2975 | case Mips::C_SEQ_D32_MM: |
| 2976 | case Mips::C_SEQ_D64_MM: |
| 2977 | case Mips::C_SEQ_S_MM: |
| 2978 | case Mips::C_SF_D32_MM: |
| 2979 | case Mips::C_SF_D64_MM: |
| 2980 | case Mips::C_SF_S_MM: |
| 2981 | case Mips::C_UEQ_D32_MM: |
| 2982 | case Mips::C_UEQ_D64_MM: |
| 2983 | case Mips::C_UEQ_S_MM: |
| 2984 | case Mips::C_ULE_D32_MM: |
| 2985 | case Mips::C_ULE_D64_MM: |
| 2986 | case Mips::C_ULE_S_MM: |
| 2987 | case Mips::C_ULT_D32_MM: |
| 2988 | case Mips::C_ULT_D64_MM: |
| 2989 | case Mips::C_ULT_S_MM: |
| 2990 | case Mips::C_UN_D32_MM: |
| 2991 | case Mips::C_UN_D64_MM: |
| 2992 | case Mips::C_UN_S_MM: { |
| 2993 | // op: fs |
| 2994 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2995 | Value |= (op & 0x1f) << 16; |
| 2996 | // op: ft |
| 2997 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2998 | Value |= (op & 0x1f) << 21; |
| 2999 | // op: fcc |
| 3000 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3001 | Value |= (op & 0x7) << 13; |
| 3002 | break; |
| 3003 | } |
| 3004 | case Mips::CLASS_D_MMR6: |
| 3005 | case Mips::CLASS_S_MMR6: |
| 3006 | case Mips::RINT_D_MMR6: |
| 3007 | case Mips::RINT_S_MMR6: { |
| 3008 | // op: fs |
| 3009 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3010 | Value |= (op & 0x1f) << 21; |
| 3011 | // op: fd |
| 3012 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3013 | Value |= (op & 0x1f) << 16; |
| 3014 | break; |
| 3015 | } |
| 3016 | case Mips::BC1EQZ: |
| 3017 | case Mips::BC1NEZ: { |
| 3018 | // op: ft |
| 3019 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3020 | Value |= (op & 0x1f) << 16; |
| 3021 | // op: offset |
| 3022 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 3023 | Value |= (op & 0xffff); |
| 3024 | break; |
| 3025 | } |
| 3026 | case Mips::LDC1_D64_MMR6: |
| 3027 | case Mips::SDC1_D64_MMR6: { |
| 3028 | // op: ft |
| 3029 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3030 | Value |= (op & 0x1f) << 21; |
| 3031 | // op: addr |
| 3032 | op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI); |
| 3033 | Value |= (op & 0x1fffff); |
| 3034 | break; |
| 3035 | } |
| 3036 | case Mips::CEIL_L_D_MMR6: |
| 3037 | case Mips::CEIL_L_S_MMR6: |
| 3038 | case Mips::CEIL_W_D_MMR6: |
| 3039 | case Mips::CEIL_W_S_MMR6: |
| 3040 | case Mips::CVT_D_L_MMR6: |
| 3041 | case Mips::CVT_L_D_MMR6: |
| 3042 | case Mips::CVT_L_S_MMR6: |
| 3043 | case Mips::CVT_S_L_MMR6: |
| 3044 | case Mips::CVT_S_W_MMR6: |
| 3045 | case Mips::CVT_W_S_MMR6: |
| 3046 | case Mips::FLOOR_L_D_MMR6: |
| 3047 | case Mips::FLOOR_L_S_MMR6: |
| 3048 | case Mips::FLOOR_W_D_MMR6: |
| 3049 | case Mips::FLOOR_W_S_MMR6: |
| 3050 | case Mips::FMOV_D_MMR6: |
| 3051 | case Mips::FMOV_S_MMR6: |
| 3052 | case Mips::FNEG_S_MMR6: |
| 3053 | case Mips::ROUND_L_D_MMR6: |
| 3054 | case Mips::ROUND_L_S_MMR6: |
| 3055 | case Mips::ROUND_W_D_MMR6: |
| 3056 | case Mips::ROUND_W_S_MMR6: |
| 3057 | case Mips::TRUNC_L_D_MMR6: |
| 3058 | case Mips::TRUNC_L_S_MMR6: |
| 3059 | case Mips::TRUNC_W_D_MMR6: |
| 3060 | case Mips::TRUNC_W_S_MMR6: { |
| 3061 | // op: ft |
| 3062 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3063 | Value |= (op & 0x1f) << 21; |
| 3064 | // op: fs |
| 3065 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3066 | Value |= (op & 0x1f) << 16; |
| 3067 | break; |
| 3068 | } |
| 3069 | case Mips::FADD_S_MMR6: |
| 3070 | case Mips::FDIV_S_MMR6: |
| 3071 | case Mips::FMUL_S_MMR6: |
| 3072 | case Mips::FSUB_S_MMR6: { |
| 3073 | // op: ft |
| 3074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3075 | Value |= (op & 0x1f) << 21; |
| 3076 | // op: fs |
| 3077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3078 | Value |= (op & 0x1f) << 16; |
| 3079 | // op: fd |
| 3080 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3081 | Value |= (op & 0x1f) << 11; |
| 3082 | break; |
| 3083 | } |
| 3084 | case Mips::MAXA_D: |
| 3085 | case Mips::MAXA_S: |
| 3086 | case Mips::MAX_D: |
| 3087 | case Mips::MAX_S: |
| 3088 | case Mips::MINA_D: |
| 3089 | case Mips::MINA_S: |
| 3090 | case Mips::MIN_D: |
| 3091 | case Mips::MIN_S: |
| 3092 | case Mips::SELEQZ_D: |
| 3093 | case Mips::SELEQZ_S: |
| 3094 | case Mips::SELNEZ_D: |
| 3095 | case Mips::SELNEZ_S: { |
| 3096 | // op: ft |
| 3097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3098 | Value |= (op & 0x1f) << 16; |
| 3099 | // op: fs |
| 3100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3101 | Value |= (op & 0x1f) << 11; |
| 3102 | // op: fd |
| 3103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3104 | Value |= (op & 0x1f) << 6; |
| 3105 | break; |
| 3106 | } |
| 3107 | case Mips::CMP_AF_D_MMR6: |
| 3108 | case Mips::CMP_AF_S_MMR6: |
| 3109 | case Mips::CMP_EQ_D_MMR6: |
| 3110 | case Mips::CMP_EQ_S_MMR6: |
| 3111 | case Mips::CMP_LE_D_MMR6: |
| 3112 | case Mips::CMP_LE_S_MMR6: |
| 3113 | case Mips::CMP_LT_D_MMR6: |
| 3114 | case Mips::CMP_LT_S_MMR6: |
| 3115 | case Mips::CMP_SAF_D_MMR6: |
| 3116 | case Mips::CMP_SAF_S_MMR6: |
| 3117 | case Mips::CMP_SEQ_D_MMR6: |
| 3118 | case Mips::CMP_SEQ_S_MMR6: |
| 3119 | case Mips::CMP_SLE_D_MMR6: |
| 3120 | case Mips::CMP_SLE_S_MMR6: |
| 3121 | case Mips::CMP_SLT_D_MMR6: |
| 3122 | case Mips::CMP_SLT_S_MMR6: |
| 3123 | case Mips::CMP_SUEQ_D_MMR6: |
| 3124 | case Mips::CMP_SUEQ_S_MMR6: |
| 3125 | case Mips::CMP_SULE_D_MMR6: |
| 3126 | case Mips::CMP_SULE_S_MMR6: |
| 3127 | case Mips::CMP_SULT_D_MMR6: |
| 3128 | case Mips::CMP_SULT_S_MMR6: |
| 3129 | case Mips::CMP_SUN_D_MMR6: |
| 3130 | case Mips::CMP_SUN_S_MMR6: |
| 3131 | case Mips::CMP_UEQ_D_MMR6: |
| 3132 | case Mips::CMP_UEQ_S_MMR6: |
| 3133 | case Mips::CMP_ULE_D_MMR6: |
| 3134 | case Mips::CMP_ULE_S_MMR6: |
| 3135 | case Mips::CMP_ULT_D_MMR6: |
| 3136 | case Mips::CMP_ULT_S_MMR6: |
| 3137 | case Mips::CMP_UN_D_MMR6: |
| 3138 | case Mips::CMP_UN_S_MMR6: |
| 3139 | case Mips::FADD_D32_MM: |
| 3140 | case Mips::FADD_D64_MM: |
| 3141 | case Mips::FADD_S_MM: |
| 3142 | case Mips::FDIV_D32_MM: |
| 3143 | case Mips::FDIV_D64_MM: |
| 3144 | case Mips::FDIV_S_MM: |
| 3145 | case Mips::FMUL_D32_MM: |
| 3146 | case Mips::FMUL_D64_MM: |
| 3147 | case Mips::FMUL_S_MM: |
| 3148 | case Mips::FSUB_D32_MM: |
| 3149 | case Mips::FSUB_D64_MM: |
| 3150 | case Mips::FSUB_S_MM: |
| 3151 | case Mips::MAXA_D_MMR6: |
| 3152 | case Mips::MAXA_S_MMR6: |
| 3153 | case Mips::MAX_D_MMR6: |
| 3154 | case Mips::MAX_S_MMR6: |
| 3155 | case Mips::MINA_D_MMR6: |
| 3156 | case Mips::MINA_S_MMR6: |
| 3157 | case Mips::MIN_D_MMR6: |
| 3158 | case Mips::MIN_S_MMR6: |
| 3159 | case Mips::SELEQZ_D_MMR6: |
| 3160 | case Mips::SELEQZ_S_MMR6: |
| 3161 | case Mips::SELNEZ_D_MMR6: |
| 3162 | case Mips::SELNEZ_S_MMR6: { |
| 3163 | // op: ft |
| 3164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3165 | Value |= (op & 0x1f) << 21; |
| 3166 | // op: fs |
| 3167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3168 | Value |= (op & 0x1f) << 16; |
| 3169 | // op: fd |
| 3170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3171 | Value |= (op & 0x1f) << 11; |
| 3172 | break; |
| 3173 | } |
| 3174 | case Mips::MADDF_D: |
| 3175 | case Mips::MADDF_S: |
| 3176 | case Mips::MSUBF_D: |
| 3177 | case Mips::MSUBF_S: |
| 3178 | case Mips::SEL_D: |
| 3179 | case Mips::SEL_S: { |
| 3180 | // op: ft |
| 3181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3182 | Value |= (op & 0x1f) << 16; |
| 3183 | // op: fs |
| 3184 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3185 | Value |= (op & 0x1f) << 11; |
| 3186 | // op: fd |
| 3187 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3188 | Value |= (op & 0x1f) << 6; |
| 3189 | break; |
| 3190 | } |
| 3191 | case Mips::MADDF_D_MMR6: |
| 3192 | case Mips::MADDF_S_MMR6: |
| 3193 | case Mips::MSUBF_D_MMR6: |
| 3194 | case Mips::MSUBF_S_MMR6: |
| 3195 | case Mips::SEL_D_MMR6: |
| 3196 | case Mips::SEL_S_MMR6: { |
| 3197 | // op: ft |
| 3198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3199 | Value |= (op & 0x1f) << 21; |
| 3200 | // op: fs |
| 3201 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3202 | Value |= (op & 0x1f) << 16; |
| 3203 | // op: fd |
| 3204 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3205 | Value |= (op & 0x1f) << 11; |
| 3206 | break; |
| 3207 | } |
| 3208 | case Mips::MADD_D32_MM: |
| 3209 | case Mips::MADD_S_MM: |
| 3210 | case Mips::MSUB_D32_MM: |
| 3211 | case Mips::MSUB_S_MM: |
| 3212 | case Mips::NMADD_D32_MM: |
| 3213 | case Mips::NMADD_S_MM: |
| 3214 | case Mips::NMSUB_D32_MM: |
| 3215 | case Mips::NMSUB_S_MM: { |
| 3216 | // op: ft |
| 3217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3218 | Value |= (op & 0x1f) << 21; |
| 3219 | // op: fs |
| 3220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3221 | Value |= (op & 0x1f) << 16; |
| 3222 | // op: fd |
| 3223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3224 | Value |= (op & 0x1f) << 11; |
| 3225 | // op: fr |
| 3226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3227 | Value |= (op & 0x1f) << 6; |
| 3228 | break; |
| 3229 | } |
| 3230 | case Mips::ADDVI_B: |
| 3231 | case Mips::ADDVI_D: |
| 3232 | case Mips::ADDVI_H: |
| 3233 | case Mips::ADDVI_W: |
| 3234 | case Mips::CEQI_B: |
| 3235 | case Mips::CEQI_D: |
| 3236 | case Mips::CEQI_H: |
| 3237 | case Mips::CEQI_W: |
| 3238 | case Mips::CLEI_S_B: |
| 3239 | case Mips::CLEI_S_D: |
| 3240 | case Mips::CLEI_S_H: |
| 3241 | case Mips::CLEI_S_W: |
| 3242 | case Mips::CLEI_U_B: |
| 3243 | case Mips::CLEI_U_D: |
| 3244 | case Mips::CLEI_U_H: |
| 3245 | case Mips::CLEI_U_W: |
| 3246 | case Mips::CLTI_S_B: |
| 3247 | case Mips::CLTI_S_D: |
| 3248 | case Mips::CLTI_S_H: |
| 3249 | case Mips::CLTI_S_W: |
| 3250 | case Mips::CLTI_U_B: |
| 3251 | case Mips::CLTI_U_D: |
| 3252 | case Mips::CLTI_U_H: |
| 3253 | case Mips::CLTI_U_W: |
| 3254 | case Mips::MAXI_S_B: |
| 3255 | case Mips::MAXI_S_D: |
| 3256 | case Mips::MAXI_S_H: |
| 3257 | case Mips::MAXI_S_W: |
| 3258 | case Mips::MAXI_U_B: |
| 3259 | case Mips::MAXI_U_D: |
| 3260 | case Mips::MAXI_U_H: |
| 3261 | case Mips::MAXI_U_W: |
| 3262 | case Mips::MINI_S_B: |
| 3263 | case Mips::MINI_S_D: |
| 3264 | case Mips::MINI_S_H: |
| 3265 | case Mips::MINI_S_W: |
| 3266 | case Mips::MINI_U_B: |
| 3267 | case Mips::MINI_U_D: |
| 3268 | case Mips::MINI_U_H: |
| 3269 | case Mips::MINI_U_W: |
| 3270 | case Mips::SUBVI_B: |
| 3271 | case Mips::SUBVI_D: |
| 3272 | case Mips::SUBVI_H: |
| 3273 | case Mips::SUBVI_W: { |
| 3274 | // op: imm |
| 3275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3276 | Value |= (op & 0x1f) << 16; |
| 3277 | // op: ws |
| 3278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3279 | Value |= (op & 0x1f) << 11; |
| 3280 | // op: wd |
| 3281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3282 | Value |= (op & 0x1f) << 6; |
| 3283 | break; |
| 3284 | } |
| 3285 | case Mips::ADDIUSP_MM: { |
| 3286 | // op: imm |
| 3287 | op = getSImm9AddiuspValue(MI, OpNo: 0, Fixups, STI); |
| 3288 | Value |= (op & 0x1ff) << 1; |
| 3289 | break; |
| 3290 | } |
| 3291 | case Mips::JRCADDIUSP_MMR6: { |
| 3292 | // op: imm |
| 3293 | op = getUImm5Lsl2Encoding(MI, OpNo: 0, Fixups, STI); |
| 3294 | Value |= (op & 0x1f) << 5; |
| 3295 | break; |
| 3296 | } |
| 3297 | case Mips::JRADDIUSP: { |
| 3298 | // op: imm |
| 3299 | op = getUImm5Lsl2Encoding(MI, OpNo: 0, Fixups, STI); |
| 3300 | Value |= (op & 0x1f); |
| 3301 | break; |
| 3302 | } |
| 3303 | case Mips::Bimm16: { |
| 3304 | // op: imm11 |
| 3305 | op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI); |
| 3306 | Value |= (op & 0x7ff); |
| 3307 | break; |
| 3308 | } |
| 3309 | case Mips::AddiuRxRyOffMemX16: { |
| 3310 | // op: imm15 |
| 3311 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3312 | Value |= (op & 0x7f0) << 16; |
| 3313 | Value |= (op & 0x7800) << 5; |
| 3314 | Value |= (op & 0xf); |
| 3315 | // op: rx |
| 3316 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3317 | Value |= (op & 0x7) << 8; |
| 3318 | // op: ry |
| 3319 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3320 | Value |= (op & 0x7) << 5; |
| 3321 | break; |
| 3322 | } |
| 3323 | case Mips::BimmX16: { |
| 3324 | // op: imm16 |
| 3325 | op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI); |
| 3326 | Value |= (op & 0x7e0) << 16; |
| 3327 | Value |= (op & 0xf800) << 5; |
| 3328 | Value |= (op & 0x1f); |
| 3329 | break; |
| 3330 | } |
| 3331 | case Mips::BeqzRxImmX16: |
| 3332 | case Mips::BnezRxImmX16: { |
| 3333 | // op: imm16 |
| 3334 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 3335 | Value |= (op & 0x7e0) << 16; |
| 3336 | Value |= (op & 0xf800) << 5; |
| 3337 | Value |= (op & 0x1f); |
| 3338 | // op: rx |
| 3339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3340 | Value |= (op & 0x7) << 8; |
| 3341 | break; |
| 3342 | } |
| 3343 | case Mips::AddiuSpImmX16: |
| 3344 | case Mips::BteqzX16: |
| 3345 | case Mips::BtnezX16: { |
| 3346 | // op: imm16 |
| 3347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3348 | Value |= (op & 0x7e0) << 16; |
| 3349 | Value |= (op & 0xf800) << 5; |
| 3350 | Value |= (op & 0x1f); |
| 3351 | break; |
| 3352 | } |
| 3353 | case Mips::AddiuRxImmX16: |
| 3354 | case Mips::AddiuRxPcImmX16: |
| 3355 | case Mips::CmpiRxImmX16: |
| 3356 | case Mips::LiRxImmAlignX16: |
| 3357 | case Mips::LiRxImmX16: |
| 3358 | case Mips::LwRxPcTcpX16: |
| 3359 | case Mips::SltiRxImmX16: |
| 3360 | case Mips::SltiuRxImmX16: { |
| 3361 | // op: imm16 |
| 3362 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3363 | Value |= (op & 0x7e0) << 16; |
| 3364 | Value |= (op & 0xf800) << 5; |
| 3365 | Value |= (op & 0x1f); |
| 3366 | // op: rx |
| 3367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3368 | Value |= (op & 0x7) << 8; |
| 3369 | break; |
| 3370 | } |
| 3371 | case Mips::AddiuRxRxImmX16: { |
| 3372 | // op: imm16 |
| 3373 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3374 | Value |= (op & 0x7e0) << 16; |
| 3375 | Value |= (op & 0xf800) << 5; |
| 3376 | Value |= (op & 0x1f); |
| 3377 | // op: rx |
| 3378 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3379 | Value |= (op & 0x7) << 8; |
| 3380 | break; |
| 3381 | } |
| 3382 | case Mips::LbRxRyOffMemX16: |
| 3383 | case Mips::LbuRxRyOffMemX16: |
| 3384 | case Mips::LhRxRyOffMemX16: |
| 3385 | case Mips::LhuRxRyOffMemX16: |
| 3386 | case Mips::LwRxRyOffMemX16: |
| 3387 | case Mips::LwRxSpImmX16: |
| 3388 | case Mips::SbRxRyOffMemX16: |
| 3389 | case Mips::ShRxRyOffMemX16: |
| 3390 | case Mips::SwRxRyOffMemX16: |
| 3391 | case Mips::SwRxSpImmX16: { |
| 3392 | // op: imm16 |
| 3393 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3394 | Value |= (op & 0x7e0) << 16; |
| 3395 | Value |= (op & 0xf800) << 5; |
| 3396 | Value |= (op & 0x1f); |
| 3397 | // op: rx |
| 3398 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3399 | Value |= (op & 0x7) << 8; |
| 3400 | // op: ry |
| 3401 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3402 | Value |= (op & 0x7) << 5; |
| 3403 | break; |
| 3404 | } |
| 3405 | case Mips::Jal16: |
| 3406 | case Mips::JalB16: { |
| 3407 | // op: imm26 |
| 3408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3409 | Value |= (op & 0x1f0000) << 5; |
| 3410 | Value |= (op & 0x3e00000) >> 5; |
| 3411 | Value |= (op & 0xffff); |
| 3412 | break; |
| 3413 | } |
| 3414 | case Mips::AddiuSpImm16: |
| 3415 | case Mips::Bteqz16: |
| 3416 | case Mips::Btnez16: { |
| 3417 | // op: imm8 |
| 3418 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3419 | Value |= (op & 0xff); |
| 3420 | break; |
| 3421 | } |
| 3422 | case Mips::PREFX_MM: { |
| 3423 | // op: index |
| 3424 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3425 | Value |= (op & 0x1f) << 21; |
| 3426 | // op: base |
| 3427 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3428 | Value |= (op & 0x1f) << 16; |
| 3429 | // op: hint |
| 3430 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3431 | Value |= (op & 0x1f) << 11; |
| 3432 | break; |
| 3433 | } |
| 3434 | case Mips::LBUX_MM: |
| 3435 | case Mips::LHX_MM: |
| 3436 | case Mips::LWX_MM: { |
| 3437 | // op: index |
| 3438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3439 | Value |= (op & 0x1f) << 21; |
| 3440 | // op: base |
| 3441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3442 | Value |= (op & 0x1f) << 16; |
| 3443 | // op: rd |
| 3444 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3445 | Value |= (op & 0x1f) << 11; |
| 3446 | break; |
| 3447 | } |
| 3448 | case Mips::COPY_S_D: { |
| 3449 | // op: n |
| 3450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3451 | Value |= (op & 0x1) << 16; |
| 3452 | // op: ws |
| 3453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3454 | Value |= (op & 0x1f) << 11; |
| 3455 | // op: rd |
| 3456 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3457 | Value |= (op & 0x1f) << 6; |
| 3458 | break; |
| 3459 | } |
| 3460 | case Mips::SPLATI_D: { |
| 3461 | // op: n |
| 3462 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3463 | Value |= (op & 0x1) << 16; |
| 3464 | // op: ws |
| 3465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3466 | Value |= (op & 0x1f) << 11; |
| 3467 | // op: wd |
| 3468 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3469 | Value |= (op & 0x1f) << 6; |
| 3470 | break; |
| 3471 | } |
| 3472 | case Mips::INSVE_D: { |
| 3473 | // op: n |
| 3474 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3475 | Value |= (op & 0x1) << 16; |
| 3476 | // op: ws |
| 3477 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3478 | Value |= (op & 0x1f) << 11; |
| 3479 | // op: wd |
| 3480 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3481 | Value |= (op & 0x1f) << 6; |
| 3482 | break; |
| 3483 | } |
| 3484 | case Mips::COPY_S_W: |
| 3485 | case Mips::COPY_U_W: { |
| 3486 | // op: n |
| 3487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3488 | Value |= (op & 0x3) << 16; |
| 3489 | // op: ws |
| 3490 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3491 | Value |= (op & 0x1f) << 11; |
| 3492 | // op: rd |
| 3493 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3494 | Value |= (op & 0x1f) << 6; |
| 3495 | break; |
| 3496 | } |
| 3497 | case Mips::SPLATI_W: { |
| 3498 | // op: n |
| 3499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3500 | Value |= (op & 0x3) << 16; |
| 3501 | // op: ws |
| 3502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3503 | Value |= (op & 0x1f) << 11; |
| 3504 | // op: wd |
| 3505 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3506 | Value |= (op & 0x1f) << 6; |
| 3507 | break; |
| 3508 | } |
| 3509 | case Mips::INSVE_W: { |
| 3510 | // op: n |
| 3511 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3512 | Value |= (op & 0x3) << 16; |
| 3513 | // op: ws |
| 3514 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3515 | Value |= (op & 0x1f) << 11; |
| 3516 | // op: wd |
| 3517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3518 | Value |= (op & 0x1f) << 6; |
| 3519 | break; |
| 3520 | } |
| 3521 | case Mips::COPY_S_H: |
| 3522 | case Mips::COPY_U_H: { |
| 3523 | // op: n |
| 3524 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3525 | Value |= (op & 0x7) << 16; |
| 3526 | // op: ws |
| 3527 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3528 | Value |= (op & 0x1f) << 11; |
| 3529 | // op: rd |
| 3530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3531 | Value |= (op & 0x1f) << 6; |
| 3532 | break; |
| 3533 | } |
| 3534 | case Mips::SPLATI_H: { |
| 3535 | // op: n |
| 3536 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3537 | Value |= (op & 0x7) << 16; |
| 3538 | // op: ws |
| 3539 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3540 | Value |= (op & 0x1f) << 11; |
| 3541 | // op: wd |
| 3542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3543 | Value |= (op & 0x1f) << 6; |
| 3544 | break; |
| 3545 | } |
| 3546 | case Mips::INSVE_H: { |
| 3547 | // op: n |
| 3548 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3549 | Value |= (op & 0x7) << 16; |
| 3550 | // op: ws |
| 3551 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3552 | Value |= (op & 0x1f) << 11; |
| 3553 | // op: wd |
| 3554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3555 | Value |= (op & 0x1f) << 6; |
| 3556 | break; |
| 3557 | } |
| 3558 | case Mips::COPY_S_B: |
| 3559 | case Mips::COPY_U_B: { |
| 3560 | // op: n |
| 3561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3562 | Value |= (op & 0xf) << 16; |
| 3563 | // op: ws |
| 3564 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3565 | Value |= (op & 0x1f) << 11; |
| 3566 | // op: rd |
| 3567 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3568 | Value |= (op & 0x1f) << 6; |
| 3569 | break; |
| 3570 | } |
| 3571 | case Mips::SPLATI_B: { |
| 3572 | // op: n |
| 3573 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3574 | Value |= (op & 0xf) << 16; |
| 3575 | // op: ws |
| 3576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3577 | Value |= (op & 0x1f) << 11; |
| 3578 | // op: wd |
| 3579 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3580 | Value |= (op & 0x1f) << 6; |
| 3581 | break; |
| 3582 | } |
| 3583 | case Mips::INSVE_B: { |
| 3584 | // op: n |
| 3585 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3586 | Value |= (op & 0xf) << 16; |
| 3587 | // op: ws |
| 3588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3589 | Value |= (op & 0x1f) << 11; |
| 3590 | // op: wd |
| 3591 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3592 | Value |= (op & 0x1f) << 6; |
| 3593 | break; |
| 3594 | } |
| 3595 | case Mips::INSERT_D: { |
| 3596 | // op: n |
| 3597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3598 | Value |= (op & 0x1) << 16; |
| 3599 | // op: rs |
| 3600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3601 | Value |= (op & 0x1f) << 11; |
| 3602 | // op: wd |
| 3603 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3604 | Value |= (op & 0x1f) << 6; |
| 3605 | break; |
| 3606 | } |
| 3607 | case Mips::SLDI_D: { |
| 3608 | // op: n |
| 3609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3610 | Value |= (op & 0x1) << 16; |
| 3611 | // op: ws |
| 3612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3613 | Value |= (op & 0x1f) << 11; |
| 3614 | // op: wd |
| 3615 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3616 | Value |= (op & 0x1f) << 6; |
| 3617 | break; |
| 3618 | } |
| 3619 | case Mips::INSERT_W: { |
| 3620 | // op: n |
| 3621 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3622 | Value |= (op & 0x3) << 16; |
| 3623 | // op: rs |
| 3624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3625 | Value |= (op & 0x1f) << 11; |
| 3626 | // op: wd |
| 3627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3628 | Value |= (op & 0x1f) << 6; |
| 3629 | break; |
| 3630 | } |
| 3631 | case Mips::SLDI_W: { |
| 3632 | // op: n |
| 3633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3634 | Value |= (op & 0x3) << 16; |
| 3635 | // op: ws |
| 3636 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3637 | Value |= (op & 0x1f) << 11; |
| 3638 | // op: wd |
| 3639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3640 | Value |= (op & 0x1f) << 6; |
| 3641 | break; |
| 3642 | } |
| 3643 | case Mips::INSERT_H: { |
| 3644 | // op: n |
| 3645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3646 | Value |= (op & 0x7) << 16; |
| 3647 | // op: rs |
| 3648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3649 | Value |= (op & 0x1f) << 11; |
| 3650 | // op: wd |
| 3651 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3652 | Value |= (op & 0x1f) << 6; |
| 3653 | break; |
| 3654 | } |
| 3655 | case Mips::SLDI_H: { |
| 3656 | // op: n |
| 3657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3658 | Value |= (op & 0x7) << 16; |
| 3659 | // op: ws |
| 3660 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3661 | Value |= (op & 0x1f) << 11; |
| 3662 | // op: wd |
| 3663 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3664 | Value |= (op & 0x1f) << 6; |
| 3665 | break; |
| 3666 | } |
| 3667 | case Mips::INSERT_B: { |
| 3668 | // op: n |
| 3669 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3670 | Value |= (op & 0xf) << 16; |
| 3671 | // op: rs |
| 3672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3673 | Value |= (op & 0x1f) << 11; |
| 3674 | // op: wd |
| 3675 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3676 | Value |= (op & 0x1f) << 6; |
| 3677 | break; |
| 3678 | } |
| 3679 | case Mips::SLDI_B: { |
| 3680 | // op: n |
| 3681 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3682 | Value |= (op & 0xf) << 16; |
| 3683 | // op: ws |
| 3684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3685 | Value |= (op & 0x1f) << 11; |
| 3686 | // op: wd |
| 3687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3688 | Value |= (op & 0x1f) << 6; |
| 3689 | break; |
| 3690 | } |
| 3691 | case Mips::BALC: |
| 3692 | case Mips::BC: { |
| 3693 | // op: offset |
| 3694 | op = getBranchTarget26OpValue(MI, OpNo: 0, Fixups, STI); |
| 3695 | Value |= (op & 0x3ffffff); |
| 3696 | break; |
| 3697 | } |
| 3698 | case Mips::BALC_MMR6: |
| 3699 | case Mips::BC_MMR6: { |
| 3700 | // op: offset |
| 3701 | op = getBranchTarget26OpValueMM(MI, OpNo: 0, Fixups, STI); |
| 3702 | Value |= (op & 0x3ffffff); |
| 3703 | break; |
| 3704 | } |
| 3705 | case Mips::BAL: |
| 3706 | case Mips::BPOSGE32: { |
| 3707 | // op: offset |
| 3708 | op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI); |
| 3709 | Value |= (op & 0xffff); |
| 3710 | break; |
| 3711 | } |
| 3712 | case Mips::BNZ_B: |
| 3713 | case Mips::BNZ_D: |
| 3714 | case Mips::BNZ_H: |
| 3715 | case Mips::BNZ_V: |
| 3716 | case Mips::BNZ_W: |
| 3717 | case Mips::BZ_B: |
| 3718 | case Mips::BZ_D: |
| 3719 | case Mips::BZ_H: |
| 3720 | case Mips::BZ_V: |
| 3721 | case Mips::BZ_W: { |
| 3722 | // op: offset |
| 3723 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 3724 | Value |= (op & 0xffff); |
| 3725 | // op: wt |
| 3726 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3727 | Value |= (op & 0x1f) << 16; |
| 3728 | break; |
| 3729 | } |
| 3730 | case Mips::BPOSGE32C_MMR3: { |
| 3731 | // op: offset |
| 3732 | op = getBranchTargetOpValue1SImm16(MI, OpNo: 0, Fixups, STI); |
| 3733 | Value |= (op & 0xffff); |
| 3734 | break; |
| 3735 | } |
| 3736 | case Mips::BPOSGE32_MM: { |
| 3737 | // op: offset |
| 3738 | op = getBranchTargetOpValueMM(MI, OpNo: 0, Fixups, STI); |
| 3739 | Value |= (op & 0xffff); |
| 3740 | break; |
| 3741 | } |
| 3742 | case Mips::B16_MM: |
| 3743 | case Mips::BC16_MMR6: { |
| 3744 | // op: offset |
| 3745 | op = getBranchTargetOpValueMMPC10(MI, OpNo: 0, Fixups, STI); |
| 3746 | Value |= (op & 0x3ff); |
| 3747 | break; |
| 3748 | } |
| 3749 | case Mips::Move32R16: { |
| 3750 | // op: r32 |
| 3751 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3752 | Value |= (op & 0x7) << 5; |
| 3753 | Value |= (op & 0x18); |
| 3754 | // op: rz |
| 3755 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3756 | Value |= (op & 0x7); |
| 3757 | break; |
| 3758 | } |
| 3759 | case Mips::MFHI: |
| 3760 | case Mips::MFHI64: |
| 3761 | case Mips::MFLO: |
| 3762 | case Mips::MFLO64: { |
| 3763 | // op: rd |
| 3764 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3765 | Value |= (op & 0x1f) << 11; |
| 3766 | break; |
| 3767 | } |
| 3768 | case Mips::MFHI_DSP: |
| 3769 | case Mips::MFLO_DSP: { |
| 3770 | // op: rd |
| 3771 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3772 | Value |= (op & 0x1f) << 11; |
| 3773 | // op: ac |
| 3774 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3775 | Value |= (op & 0x3) << 21; |
| 3776 | break; |
| 3777 | } |
| 3778 | case Mips::LWXS_MM: { |
| 3779 | // op: rd |
| 3780 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3781 | Value |= (op & 0x1f) << 11; |
| 3782 | // op: base |
| 3783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3784 | Value |= (op & 0x1f) << 16; |
| 3785 | // op: index |
| 3786 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3787 | Value |= (op & 0x1f) << 21; |
| 3788 | break; |
| 3789 | } |
| 3790 | case Mips::LBUX: |
| 3791 | case Mips::LHX: |
| 3792 | case Mips::LWX: { |
| 3793 | // op: rd |
| 3794 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3795 | Value |= (op & 0x1f) << 11; |
| 3796 | // op: base |
| 3797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3798 | Value |= (op & 0x1f) << 21; |
| 3799 | // op: index |
| 3800 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3801 | Value |= (op & 0x1f) << 16; |
| 3802 | break; |
| 3803 | } |
| 3804 | case Mips::REPL_PH: |
| 3805 | case Mips::REPL_PH_MM: |
| 3806 | case Mips::REPL_QB: { |
| 3807 | // op: rd |
| 3808 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3809 | Value |= (op & 0x1f) << 11; |
| 3810 | // op: imm |
| 3811 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3812 | Value |= (op & 0x3ff) << 16; |
| 3813 | break; |
| 3814 | } |
| 3815 | case Mips::RDDSP: { |
| 3816 | // op: rd |
| 3817 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3818 | Value |= (op & 0x1f) << 11; |
| 3819 | // op: mask |
| 3820 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3821 | Value |= (op & 0x3ff) << 16; |
| 3822 | break; |
| 3823 | } |
| 3824 | case Mips::ADDQH_PH_MMR2: |
| 3825 | case Mips::ADDQH_R_PH_MMR2: |
| 3826 | case Mips::ADDQH_R_W_MMR2: |
| 3827 | case Mips::ADDQH_W_MMR2: |
| 3828 | case Mips::ADDQ_PH_MM: |
| 3829 | case Mips::ADDQ_S_PH_MM: |
| 3830 | case Mips::ADDQ_S_W_MM: |
| 3831 | case Mips::ADDSC_MM: |
| 3832 | case Mips::ADDUH_QB_MMR2: |
| 3833 | case Mips::ADDUH_R_QB_MMR2: |
| 3834 | case Mips::ADDU_PH_MMR2: |
| 3835 | case Mips::ADDU_QB_MM: |
| 3836 | case Mips::ADDU_S_PH_MMR2: |
| 3837 | case Mips::ADDU_S_QB_MM: |
| 3838 | case Mips::ADDWC_MM: |
| 3839 | case Mips::CMPGDU_EQ_QB_MMR2: |
| 3840 | case Mips::CMPGDU_LE_QB_MMR2: |
| 3841 | case Mips::CMPGDU_LT_QB_MMR2: |
| 3842 | case Mips::MODSUB_MM: |
| 3843 | case Mips::MULEQ_S_W_PHL_MM: |
| 3844 | case Mips::MULEQ_S_W_PHR_MM: |
| 3845 | case Mips::MULEU_S_PH_QBL_MM: |
| 3846 | case Mips::MULEU_S_PH_QBR_MM: |
| 3847 | case Mips::MULQ_RS_PH_MM: |
| 3848 | case Mips::MULQ_RS_W_MMR2: |
| 3849 | case Mips::MULQ_S_PH_MMR2: |
| 3850 | case Mips::MULQ_S_W_MMR2: |
| 3851 | case Mips::MUL_PH_MMR2: |
| 3852 | case Mips::MUL_S_PH_MMR2: |
| 3853 | case Mips::PACKRL_PH_MM: |
| 3854 | case Mips::PICK_PH_MM: |
| 3855 | case Mips::PICK_QB_MM: |
| 3856 | case Mips::PRECRQU_S_QB_PH_MM: |
| 3857 | case Mips::PRECRQ_PH_W_MM: |
| 3858 | case Mips::PRECRQ_QB_PH_MM: |
| 3859 | case Mips::PRECRQ_RS_PH_W_MM: |
| 3860 | case Mips::PRECR_QB_PH_MMR2: |
| 3861 | case Mips::SELEQZ_MMR6: |
| 3862 | case Mips::SELNEZ_MMR6: |
| 3863 | case Mips::SUBQH_PH_MMR2: |
| 3864 | case Mips::SUBQH_R_PH_MMR2: |
| 3865 | case Mips::SUBQH_R_W_MMR2: |
| 3866 | case Mips::SUBQH_W_MMR2: |
| 3867 | case Mips::SUBQ_PH_MM: |
| 3868 | case Mips::SUBQ_S_PH_MM: |
| 3869 | case Mips::SUBQ_S_W_MM: |
| 3870 | case Mips::SUBUH_QB_MMR2: |
| 3871 | case Mips::SUBUH_R_QB_MMR2: |
| 3872 | case Mips::SUBU_PH_MMR2: |
| 3873 | case Mips::SUBU_QB_MM: |
| 3874 | case Mips::SUBU_S_PH_MMR2: |
| 3875 | case Mips::SUBU_S_QB_MM: { |
| 3876 | // op: rd |
| 3877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3878 | Value |= (op & 0x1f) << 11; |
| 3879 | // op: rs |
| 3880 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3881 | Value |= (op & 0x1f) << 16; |
| 3882 | // op: rt |
| 3883 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3884 | Value |= (op & 0x1f) << 21; |
| 3885 | break; |
| 3886 | } |
| 3887 | case Mips::LSA_MMR6: { |
| 3888 | // op: rd |
| 3889 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3890 | Value |= (op & 0x1f) << 11; |
| 3891 | // op: rs |
| 3892 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3893 | Value |= (op & 0x1f) << 16; |
| 3894 | // op: rt |
| 3895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3896 | Value |= (op & 0x1f) << 21; |
| 3897 | // op: imm2 |
| 3898 | op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI); |
| 3899 | Value |= (op & 0x3) << 9; |
| 3900 | break; |
| 3901 | } |
| 3902 | case Mips::CLO_R6: |
| 3903 | case Mips::CLZ_R6: |
| 3904 | case Mips::DCLO_R6: |
| 3905 | case Mips::DCLZ_R6: |
| 3906 | case Mips::DPOP: |
| 3907 | case Mips::JALR: |
| 3908 | case Mips::JALR64: |
| 3909 | case Mips::JALR_HB: |
| 3910 | case Mips::JALR_HB64: |
| 3911 | case Mips::POP: |
| 3912 | case Mips::RADDU_W_QB: { |
| 3913 | // op: rd |
| 3914 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3915 | Value |= (op & 0x1f) << 11; |
| 3916 | // op: rs |
| 3917 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3918 | Value |= (op & 0x1f) << 21; |
| 3919 | break; |
| 3920 | } |
| 3921 | case Mips::MOVF_I: |
| 3922 | case Mips::MOVF_I64: |
| 3923 | case Mips::MOVT_I: |
| 3924 | case Mips::MOVT_I64: { |
| 3925 | // op: rd |
| 3926 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3927 | Value |= (op & 0x1f) << 11; |
| 3928 | // op: rs |
| 3929 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3930 | Value |= (op & 0x1f) << 21; |
| 3931 | // op: fcc |
| 3932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3933 | Value |= (op & 0x7) << 18; |
| 3934 | break; |
| 3935 | } |
| 3936 | case Mips::ADD: |
| 3937 | case Mips::ADDQH_PH: |
| 3938 | case Mips::ADDQH_R_PH: |
| 3939 | case Mips::ADDQH_R_W: |
| 3940 | case Mips::ADDQH_W: |
| 3941 | case Mips::ADDQ_PH: |
| 3942 | case Mips::ADDQ_S_PH: |
| 3943 | case Mips::ADDQ_S_W: |
| 3944 | case Mips::ADDSC: |
| 3945 | case Mips::ADDUH_QB: |
| 3946 | case Mips::ADDUH_R_QB: |
| 3947 | case Mips::ADDU_PH: |
| 3948 | case Mips::ADDU_QB: |
| 3949 | case Mips::ADDU_S_PH: |
| 3950 | case Mips::ADDU_S_QB: |
| 3951 | case Mips::ADDWC: |
| 3952 | case Mips::ADDu: |
| 3953 | case Mips::AND: |
| 3954 | case Mips::AND64: |
| 3955 | case Mips::BADDu: |
| 3956 | case Mips::DADD: |
| 3957 | case Mips::DADDu: |
| 3958 | case Mips::DDIV: |
| 3959 | case Mips::DDIVU: |
| 3960 | case Mips::DIV: |
| 3961 | case Mips::DIVU: |
| 3962 | case Mips::DMOD: |
| 3963 | case Mips::DMODU: |
| 3964 | case Mips::DMUH: |
| 3965 | case Mips::DMUHU: |
| 3966 | case Mips::DMUL: |
| 3967 | case Mips::DMULU: |
| 3968 | case Mips::DMUL_R6: |
| 3969 | case Mips::DSUB: |
| 3970 | case Mips::DSUBu: |
| 3971 | case Mips::MOD: |
| 3972 | case Mips::MODSUB: |
| 3973 | case Mips::MODU: |
| 3974 | case Mips::MOVN_I64_I: |
| 3975 | case Mips::MOVN_I64_I64: |
| 3976 | case Mips::MOVN_I_I: |
| 3977 | case Mips::MOVN_I_I64: |
| 3978 | case Mips::MOVZ_I64_I: |
| 3979 | case Mips::MOVZ_I64_I64: |
| 3980 | case Mips::MOVZ_I_I: |
| 3981 | case Mips::MOVZ_I_I64: |
| 3982 | case Mips::MUH: |
| 3983 | case Mips::MUHU: |
| 3984 | case Mips::MUL: |
| 3985 | case Mips::MULEQ_S_W_PHL: |
| 3986 | case Mips::MULEQ_S_W_PHR: |
| 3987 | case Mips::MULEU_S_PH_QBL: |
| 3988 | case Mips::MULEU_S_PH_QBR: |
| 3989 | case Mips::MULQ_RS_PH: |
| 3990 | case Mips::MULQ_RS_W: |
| 3991 | case Mips::MULQ_S_PH: |
| 3992 | case Mips::MULQ_S_W: |
| 3993 | case Mips::MULU: |
| 3994 | case Mips::MUL_PH: |
| 3995 | case Mips::MUL_R6: |
| 3996 | case Mips::MUL_S_PH: |
| 3997 | case Mips::NOR: |
| 3998 | case Mips::NOR64: |
| 3999 | case Mips::OR: |
| 4000 | case Mips::OR64: |
| 4001 | case Mips::SELEQZ: |
| 4002 | case Mips::SELEQZ64: |
| 4003 | case Mips::SELNEZ: |
| 4004 | case Mips::SELNEZ64: |
| 4005 | case Mips::SEQ: |
| 4006 | case Mips::SLT: |
| 4007 | case Mips::SLT64: |
| 4008 | case Mips::SLTu: |
| 4009 | case Mips::SLTu64: |
| 4010 | case Mips::SNE: |
| 4011 | case Mips::SUB: |
| 4012 | case Mips::SUBQH_PH: |
| 4013 | case Mips::SUBQH_R_PH: |
| 4014 | case Mips::SUBQH_R_W: |
| 4015 | case Mips::SUBQH_W: |
| 4016 | case Mips::SUBQ_PH: |
| 4017 | case Mips::SUBQ_S_PH: |
| 4018 | case Mips::SUBQ_S_W: |
| 4019 | case Mips::SUBUH_QB: |
| 4020 | case Mips::SUBUH_R_QB: |
| 4021 | case Mips::SUBU_PH: |
| 4022 | case Mips::SUBU_QB: |
| 4023 | case Mips::SUBU_S_PH: |
| 4024 | case Mips::SUBU_S_QB: |
| 4025 | case Mips::SUBu: |
| 4026 | case Mips::V3MULU: |
| 4027 | case Mips::VMM0: |
| 4028 | case Mips::VMULU: |
| 4029 | case Mips::XOR: |
| 4030 | case Mips::XOR64: { |
| 4031 | // op: rd |
| 4032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4033 | Value |= (op & 0x1f) << 11; |
| 4034 | // op: rs |
| 4035 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4036 | Value |= (op & 0x1f) << 21; |
| 4037 | // op: rt |
| 4038 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4039 | Value |= (op & 0x1f) << 16; |
| 4040 | break; |
| 4041 | } |
| 4042 | case Mips::ALIGN: { |
| 4043 | // op: rd |
| 4044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4045 | Value |= (op & 0x1f) << 11; |
| 4046 | // op: rs |
| 4047 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4048 | Value |= (op & 0x1f) << 21; |
| 4049 | // op: rt |
| 4050 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4051 | Value |= (op & 0x1f) << 16; |
| 4052 | // op: bp |
| 4053 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4054 | Value |= (op & 0x3) << 6; |
| 4055 | break; |
| 4056 | } |
| 4057 | case Mips::ALIGN_MMR6: { |
| 4058 | // op: rd |
| 4059 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4060 | Value |= (op & 0x1f) << 11; |
| 4061 | // op: rs |
| 4062 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4063 | Value |= (op & 0x1f) << 21; |
| 4064 | // op: rt |
| 4065 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4066 | Value |= (op & 0x1f) << 16; |
| 4067 | // op: bp |
| 4068 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4069 | Value |= (op & 0x3) << 9; |
| 4070 | break; |
| 4071 | } |
| 4072 | case Mips::DALIGN: { |
| 4073 | // op: rd |
| 4074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4075 | Value |= (op & 0x1f) << 11; |
| 4076 | // op: rs |
| 4077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4078 | Value |= (op & 0x1f) << 21; |
| 4079 | // op: rt |
| 4080 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4081 | Value |= (op & 0x1f) << 16; |
| 4082 | // op: bp |
| 4083 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4084 | Value |= (op & 0x7) << 6; |
| 4085 | break; |
| 4086 | } |
| 4087 | case Mips::DLSA_R6: |
| 4088 | case Mips::LSA_R6: { |
| 4089 | // op: rd |
| 4090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4091 | Value |= (op & 0x1f) << 11; |
| 4092 | // op: rs |
| 4093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4094 | Value |= (op & 0x1f) << 21; |
| 4095 | // op: rt |
| 4096 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4097 | Value |= (op & 0x1f) << 16; |
| 4098 | // op: imm2 |
| 4099 | op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI); |
| 4100 | Value |= (op & 0x3) << 6; |
| 4101 | break; |
| 4102 | } |
| 4103 | case Mips::SHLLV_PH_MM: |
| 4104 | case Mips::SHLLV_QB_MM: |
| 4105 | case Mips::SHLLV_S_PH_MM: |
| 4106 | case Mips::SHLLV_S_W_MM: |
| 4107 | case Mips::SHRAV_PH_MM: |
| 4108 | case Mips::SHRAV_QB_MMR2: |
| 4109 | case Mips::SHRAV_R_PH_MM: |
| 4110 | case Mips::SHRAV_R_QB_MMR2: |
| 4111 | case Mips::SHRAV_R_W_MM: |
| 4112 | case Mips::SHRLV_PH_MMR2: |
| 4113 | case Mips::SHRLV_QB_MM: { |
| 4114 | // op: rd |
| 4115 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4116 | Value |= (op & 0x1f) << 11; |
| 4117 | // op: rs |
| 4118 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4119 | Value |= (op & 0x1f) << 16; |
| 4120 | // op: rt |
| 4121 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4122 | Value |= (op & 0x1f) << 21; |
| 4123 | break; |
| 4124 | } |
| 4125 | case Mips::ABSQ_S_PH: |
| 4126 | case Mips::ABSQ_S_QB: |
| 4127 | case Mips::ABSQ_S_W: |
| 4128 | case Mips::BITREV: |
| 4129 | case Mips::BITSWAP: |
| 4130 | case Mips::DBITSWAP: |
| 4131 | case Mips::DSBH: |
| 4132 | case Mips::DSHD: |
| 4133 | case Mips::DSLL64_32: |
| 4134 | case Mips::PRECEQU_PH_QBL: |
| 4135 | case Mips::PRECEQU_PH_QBLA: |
| 4136 | case Mips::PRECEQU_PH_QBR: |
| 4137 | case Mips::PRECEQU_PH_QBRA: |
| 4138 | case Mips::PRECEQ_W_PHL: |
| 4139 | case Mips::PRECEQ_W_PHR: |
| 4140 | case Mips::PRECEU_PH_QBL: |
| 4141 | case Mips::PRECEU_PH_QBLA: |
| 4142 | case Mips::PRECEU_PH_QBR: |
| 4143 | case Mips::PRECEU_PH_QBRA: |
| 4144 | case Mips::REPLV_PH: |
| 4145 | case Mips::REPLV_QB: |
| 4146 | case Mips::SEB: |
| 4147 | case Mips::SEB64: |
| 4148 | case Mips::SEH: |
| 4149 | case Mips::SEH64: |
| 4150 | case Mips::SLL64_32: |
| 4151 | case Mips::SLL64_64: |
| 4152 | case Mips::WSBH: { |
| 4153 | // op: rd |
| 4154 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4155 | Value |= (op & 0x1f) << 11; |
| 4156 | // op: rt |
| 4157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4158 | Value |= (op & 0x1f) << 16; |
| 4159 | break; |
| 4160 | } |
| 4161 | case Mips::DROTRV: |
| 4162 | case Mips::DSLLV: |
| 4163 | case Mips::DSRAV: |
| 4164 | case Mips::DSRLV: |
| 4165 | case Mips::ROTRV: |
| 4166 | case Mips::SLLV: |
| 4167 | case Mips::SRAV: |
| 4168 | case Mips::SRLV: { |
| 4169 | // op: rd |
| 4170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4171 | Value |= (op & 0x1f) << 11; |
| 4172 | // op: rt |
| 4173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4174 | Value |= (op & 0x1f) << 16; |
| 4175 | // op: rs |
| 4176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4177 | Value |= (op & 0x1f) << 21; |
| 4178 | break; |
| 4179 | } |
| 4180 | case Mips::SHLLV_PH: |
| 4181 | case Mips::SHLLV_QB: |
| 4182 | case Mips::SHLLV_S_PH: |
| 4183 | case Mips::SHLLV_S_W: |
| 4184 | case Mips::SHLL_PH: |
| 4185 | case Mips::SHLL_QB: |
| 4186 | case Mips::SHLL_S_PH: |
| 4187 | case Mips::SHLL_S_W: |
| 4188 | case Mips::SHRAV_PH: |
| 4189 | case Mips::SHRAV_QB: |
| 4190 | case Mips::SHRAV_R_PH: |
| 4191 | case Mips::SHRAV_R_QB: |
| 4192 | case Mips::SHRAV_R_W: |
| 4193 | case Mips::SHRA_PH: |
| 4194 | case Mips::SHRA_QB: |
| 4195 | case Mips::SHRA_R_PH: |
| 4196 | case Mips::SHRA_R_QB: |
| 4197 | case Mips::SHRA_R_W: |
| 4198 | case Mips::SHRLV_PH: |
| 4199 | case Mips::SHRLV_QB: |
| 4200 | case Mips::SHRL_PH: |
| 4201 | case Mips::SHRL_QB: { |
| 4202 | // op: rd |
| 4203 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4204 | Value |= (op & 0x1f) << 11; |
| 4205 | // op: rt |
| 4206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4207 | Value |= (op & 0x1f) << 16; |
| 4208 | // op: rs_sa |
| 4209 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4210 | Value |= (op & 0x1f) << 21; |
| 4211 | break; |
| 4212 | } |
| 4213 | case Mips::DROTR: |
| 4214 | case Mips::DROTR32: |
| 4215 | case Mips::DSLL: |
| 4216 | case Mips::DSLL32: |
| 4217 | case Mips::DSRA: |
| 4218 | case Mips::DSRA32: |
| 4219 | case Mips::DSRL: |
| 4220 | case Mips::DSRL32: |
| 4221 | case Mips::ROTR: |
| 4222 | case Mips::SLL: |
| 4223 | case Mips::SRA: |
| 4224 | case Mips::SRL: { |
| 4225 | // op: rd |
| 4226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4227 | Value |= (op & 0x1f) << 11; |
| 4228 | // op: rt |
| 4229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4230 | Value |= (op & 0x1f) << 16; |
| 4231 | // op: shamt |
| 4232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4233 | Value |= (op & 0x1f) << 6; |
| 4234 | break; |
| 4235 | } |
| 4236 | case Mips::ROTRV_MM: |
| 4237 | case Mips::SLLV_MM: |
| 4238 | case Mips::SRAV_MM: |
| 4239 | case Mips::SRLV_MM: { |
| 4240 | // op: rd |
| 4241 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4242 | Value |= (op & 0x1f) << 11; |
| 4243 | // op: rt |
| 4244 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4245 | Value |= (op & 0x1f) << 21; |
| 4246 | // op: rs |
| 4247 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4248 | Value |= (op & 0x1f) << 16; |
| 4249 | break; |
| 4250 | } |
| 4251 | case Mips::ADDU_MMR6: |
| 4252 | case Mips::ADD_MMR6: |
| 4253 | case Mips::AND_MMR6: |
| 4254 | case Mips::DIVU_MMR6: |
| 4255 | case Mips::DIV_MMR6: |
| 4256 | case Mips::MODU_MMR6: |
| 4257 | case Mips::MOD_MMR6: |
| 4258 | case Mips::MUHU_MMR6: |
| 4259 | case Mips::MUH_MMR6: |
| 4260 | case Mips::MULU_MMR6: |
| 4261 | case Mips::MUL_MMR6: |
| 4262 | case Mips::NOR_MMR6: |
| 4263 | case Mips::OR_MMR6: |
| 4264 | case Mips::SUBU_MMR6: |
| 4265 | case Mips::SUB_MMR6: |
| 4266 | case Mips::XOR_MMR6: { |
| 4267 | // op: rd |
| 4268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4269 | Value |= (op & 0x1f) << 11; |
| 4270 | // op: rt |
| 4271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4272 | Value |= (op & 0x1f) << 21; |
| 4273 | // op: rs |
| 4274 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4275 | Value |= (op & 0x1f) << 16; |
| 4276 | break; |
| 4277 | } |
| 4278 | case Mips::MFHI_MM: |
| 4279 | case Mips::MFLO_MM: { |
| 4280 | // op: rd |
| 4281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4282 | Value |= (op & 0x1f) << 16; |
| 4283 | break; |
| 4284 | } |
| 4285 | case Mips::BITSWAP_MMR6: { |
| 4286 | // op: rd |
| 4287 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4288 | Value |= (op & 0x1f) << 16; |
| 4289 | // op: rt |
| 4290 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4291 | Value |= (op & 0x1f) << 21; |
| 4292 | break; |
| 4293 | } |
| 4294 | case Mips::CLO: |
| 4295 | case Mips::CLZ: |
| 4296 | case Mips::DCLO: |
| 4297 | case Mips::DCLZ: { |
| 4298 | // op: rd |
| 4299 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4300 | Value |= (op & 0x1f) << 16; |
| 4301 | Value |= (op & 0x1f) << 11; |
| 4302 | // op: rs |
| 4303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4304 | Value |= (op & 0x1f) << 21; |
| 4305 | break; |
| 4306 | } |
| 4307 | case Mips::CLO_MM: |
| 4308 | case Mips::CLZ_MM: { |
| 4309 | // op: rd |
| 4310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4311 | Value |= (op & 0x1f) << 21; |
| 4312 | // op: rs |
| 4313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4314 | Value |= (op & 0x1f) << 16; |
| 4315 | break; |
| 4316 | } |
| 4317 | case Mips::MOVF_I_MM: |
| 4318 | case Mips::MOVT_I_MM: { |
| 4319 | // op: rd |
| 4320 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4321 | Value |= (op & 0x1f) << 21; |
| 4322 | // op: rs |
| 4323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4324 | Value |= (op & 0x1f) << 16; |
| 4325 | // op: fcc |
| 4326 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4327 | Value |= (op & 0x7) << 13; |
| 4328 | break; |
| 4329 | } |
| 4330 | case Mips::SEB_MM: |
| 4331 | case Mips::SEH_MM: |
| 4332 | case Mips::WSBH_MM: { |
| 4333 | // op: rd |
| 4334 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4335 | Value |= (op & 0x1f) << 21; |
| 4336 | // op: rt |
| 4337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4338 | Value |= (op & 0x1f) << 16; |
| 4339 | break; |
| 4340 | } |
| 4341 | case Mips::ROTR_MM: |
| 4342 | case Mips::SLL_MM: |
| 4343 | case Mips::SLL_MMR6: |
| 4344 | case Mips::SRA_MM: |
| 4345 | case Mips::SRL_MM: { |
| 4346 | // op: rd |
| 4347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4348 | Value |= (op & 0x1f) << 21; |
| 4349 | // op: rt |
| 4350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4351 | Value |= (op & 0x1f) << 16; |
| 4352 | // op: shamt |
| 4353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4354 | Value |= (op & 0x1f) << 11; |
| 4355 | break; |
| 4356 | } |
| 4357 | case Mips::CFCMSA: { |
| 4358 | // op: rd |
| 4359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4360 | Value |= (op & 0x1f) << 6; |
| 4361 | // op: cs |
| 4362 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4363 | Value |= (op & 0x1f) << 11; |
| 4364 | break; |
| 4365 | } |
| 4366 | case Mips::MFHI16_MM: |
| 4367 | case Mips::MFLO16_MM: { |
| 4368 | // op: rd |
| 4369 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4370 | Value |= (op & 0x1f); |
| 4371 | break; |
| 4372 | } |
| 4373 | case Mips::LI16_MM: |
| 4374 | case Mips::LI16_MMR6: { |
| 4375 | // op: rd |
| 4376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4377 | Value |= (op & 0x7) << 7; |
| 4378 | // op: imm |
| 4379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4380 | Value |= (op & 0x7f); |
| 4381 | break; |
| 4382 | } |
| 4383 | case Mips::ADDIUR1SP_MM: { |
| 4384 | // op: rd |
| 4385 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4386 | Value |= (op & 0x7) << 7; |
| 4387 | // op: imm |
| 4388 | op = getUImm6Lsl2Encoding(MI, OpNo: 1, Fixups, STI); |
| 4389 | Value |= (op & 0x3f) << 1; |
| 4390 | break; |
| 4391 | } |
| 4392 | case Mips::ADDIUR2_MM: { |
| 4393 | // op: rd |
| 4394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4395 | Value |= (op & 0x7) << 7; |
| 4396 | // op: rs |
| 4397 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4398 | Value |= (op & 0x7) << 4; |
| 4399 | // op: imm |
| 4400 | op = getSImm3Lsa2Value(MI, OpNo: 2, Fixups, STI); |
| 4401 | Value |= (op & 0x7) << 1; |
| 4402 | break; |
| 4403 | } |
| 4404 | case Mips::ANDI16_MM: |
| 4405 | case Mips::ANDI16_MMR6: { |
| 4406 | // op: rd |
| 4407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4408 | Value |= (op & 0x7) << 7; |
| 4409 | // op: rs |
| 4410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4411 | Value |= (op & 0x7) << 4; |
| 4412 | // op: imm |
| 4413 | op = getUImm4AndValue(MI, OpNo: 2, Fixups, STI); |
| 4414 | Value |= (op & 0xf); |
| 4415 | break; |
| 4416 | } |
| 4417 | case Mips::SLL16_MM: |
| 4418 | case Mips::SLL16_MMR6: |
| 4419 | case Mips::SRL16_MM: |
| 4420 | case Mips::SRL16_MMR6: { |
| 4421 | // op: rd |
| 4422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4423 | Value |= (op & 0x7) << 7; |
| 4424 | // op: rt |
| 4425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4426 | Value |= (op & 0x7) << 4; |
| 4427 | // op: shamt |
| 4428 | op = getUImm3Mod8Encoding(MI, OpNo: 2, Fixups, STI); |
| 4429 | Value |= (op & 0x7) << 1; |
| 4430 | break; |
| 4431 | } |
| 4432 | case Mips::ADDU16_MM: |
| 4433 | case Mips::SUBU16_MM: { |
| 4434 | // op: rd |
| 4435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4436 | Value |= (op & 0x7) << 7; |
| 4437 | // op: rt |
| 4438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4439 | Value |= (op & 0x7) << 4; |
| 4440 | // op: rs |
| 4441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4442 | Value |= (op & 0x7) << 1; |
| 4443 | break; |
| 4444 | } |
| 4445 | case Mips::ADDIUS5_MM: { |
| 4446 | // op: rd |
| 4447 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4448 | Value |= (op & 0x1f) << 5; |
| 4449 | // op: imm |
| 4450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4451 | Value |= (op & 0xf) << 1; |
| 4452 | break; |
| 4453 | } |
| 4454 | case Mips::DVP_MMR6: |
| 4455 | case Mips::EVP_MMR6: |
| 4456 | case Mips::GINVI_MMR6: |
| 4457 | case Mips::JR_HB_MM: |
| 4458 | case Mips::JR_MM: |
| 4459 | case Mips::MTHI_MM: |
| 4460 | case Mips::MTLO_MM: { |
| 4461 | // op: rs |
| 4462 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4463 | Value |= (op & 0x1f) << 16; |
| 4464 | break; |
| 4465 | } |
| 4466 | case Mips::MFHI_DSP_MM: |
| 4467 | case Mips::MFLO_DSP_MM: { |
| 4468 | // op: rs |
| 4469 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4470 | Value |= (op & 0x1f) << 16; |
| 4471 | // op: ac |
| 4472 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4473 | Value |= (op & 0x3) << 14; |
| 4474 | break; |
| 4475 | } |
| 4476 | case Mips::TEQI_MM: |
| 4477 | case Mips::TGEIU_MM: |
| 4478 | case Mips::TGEI_MM: |
| 4479 | case Mips::TLTIU_MM: |
| 4480 | case Mips::TLTI_MM: |
| 4481 | case Mips::TNEI_MM: { |
| 4482 | // op: rs |
| 4483 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4484 | Value |= (op & 0x1f) << 16; |
| 4485 | // op: imm16 |
| 4486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4487 | Value |= (op & 0xffff); |
| 4488 | break; |
| 4489 | } |
| 4490 | case Mips::BEQZC_MM: |
| 4491 | case Mips::BGEZALS_MM: |
| 4492 | case Mips::BGEZAL_MM: |
| 4493 | case Mips::BGEZ_MM: |
| 4494 | case Mips::BGTZ_MM: |
| 4495 | case Mips::BLEZ_MM: |
| 4496 | case Mips::BLTZALS_MM: |
| 4497 | case Mips::BLTZAL_MM: |
| 4498 | case Mips::BLTZ_MM: |
| 4499 | case Mips::BNEZC_MM: { |
| 4500 | // op: rs |
| 4501 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4502 | Value |= (op & 0x1f) << 16; |
| 4503 | // op: offset |
| 4504 | op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI); |
| 4505 | Value |= (op & 0xffff); |
| 4506 | break; |
| 4507 | } |
| 4508 | case Mips::MADDU_MM: |
| 4509 | case Mips::MADD_MM: |
| 4510 | case Mips::MSUBU_MM: |
| 4511 | case Mips::MSUB_MM: |
| 4512 | case Mips::MULT_MM: |
| 4513 | case Mips::MULTu_MM: |
| 4514 | case Mips::SDIV_MM: |
| 4515 | case Mips::UDIV_MM: { |
| 4516 | // op: rs |
| 4517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4518 | Value |= (op & 0x1f) << 16; |
| 4519 | // op: rt |
| 4520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4521 | Value |= (op & 0x1f) << 21; |
| 4522 | break; |
| 4523 | } |
| 4524 | case Mips::TEQ_MM: |
| 4525 | case Mips::TGEU_MM: |
| 4526 | case Mips::TGE_MM: |
| 4527 | case Mips::TLTU_MM: |
| 4528 | case Mips::TLT_MM: |
| 4529 | case Mips::TNE_MM: { |
| 4530 | // op: rs |
| 4531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4532 | Value |= (op & 0x1f) << 16; |
| 4533 | // op: rt |
| 4534 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4535 | Value |= (op & 0x1f) << 21; |
| 4536 | // op: code_ |
| 4537 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4538 | Value |= (op & 0xf) << 12; |
| 4539 | break; |
| 4540 | } |
| 4541 | case Mips::BEQ_MM: |
| 4542 | case Mips::BNE_MM: { |
| 4543 | // op: rs |
| 4544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4545 | Value |= (op & 0x1f) << 16; |
| 4546 | // op: rt |
| 4547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4548 | Value |= (op & 0x1f) << 21; |
| 4549 | // op: offset |
| 4550 | op = getBranchTargetOpValueMM(MI, OpNo: 2, Fixups, STI); |
| 4551 | Value |= (op & 0xffff); |
| 4552 | break; |
| 4553 | } |
| 4554 | case Mips::GINVT_MMR6: { |
| 4555 | // op: rs |
| 4556 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4557 | Value |= (op & 0x1f) << 16; |
| 4558 | // op: type |
| 4559 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4560 | Value |= (op & 0x3) << 9; |
| 4561 | break; |
| 4562 | } |
| 4563 | case Mips::GINVI: |
| 4564 | case Mips::JR: |
| 4565 | case Mips::JR64: |
| 4566 | case Mips::JR_HB: |
| 4567 | case Mips::JR_HB64: |
| 4568 | case Mips::JR_HB64_R6: |
| 4569 | case Mips::JR_HB_R6: |
| 4570 | case Mips::MTHI: |
| 4571 | case Mips::MTHI64: |
| 4572 | case Mips::MTLO: |
| 4573 | case Mips::MTLO64: |
| 4574 | case Mips::MTM0: |
| 4575 | case Mips::MTM1: |
| 4576 | case Mips::MTM2: |
| 4577 | case Mips::MTP0: |
| 4578 | case Mips::MTP1: |
| 4579 | case Mips::MTP2: { |
| 4580 | // op: rs |
| 4581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4582 | Value |= (op & 0x1f) << 21; |
| 4583 | break; |
| 4584 | } |
| 4585 | case Mips::ALUIPC: |
| 4586 | case Mips::AUIPC: { |
| 4587 | // op: rs |
| 4588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4589 | Value |= (op & 0x1f) << 21; |
| 4590 | // op: imm |
| 4591 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4592 | Value |= (op & 0xffff); |
| 4593 | break; |
| 4594 | } |
| 4595 | case Mips::DAHI: |
| 4596 | case Mips::DATI: { |
| 4597 | // op: rs |
| 4598 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4599 | Value |= (op & 0x1f) << 21; |
| 4600 | // op: imm |
| 4601 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4602 | Value |= (op & 0xffff); |
| 4603 | break; |
| 4604 | } |
| 4605 | case Mips::LDPC: { |
| 4606 | // op: rs |
| 4607 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4608 | Value |= (op & 0x1f) << 21; |
| 4609 | // op: imm |
| 4610 | op = getSimm18Lsl3Encoding(MI, OpNo: 1, Fixups, STI); |
| 4611 | Value |= (op & 0x3ffff); |
| 4612 | break; |
| 4613 | } |
| 4614 | case Mips::ADDIUPC: |
| 4615 | case Mips::LWPC: |
| 4616 | case Mips::LWUPC: { |
| 4617 | // op: rs |
| 4618 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4619 | Value |= (op & 0x1f) << 21; |
| 4620 | // op: imm |
| 4621 | op = getSimm19Lsl2Encoding(MI, OpNo: 1, Fixups, STI); |
| 4622 | Value |= (op & 0x7ffff); |
| 4623 | break; |
| 4624 | } |
| 4625 | case Mips::TEQI: |
| 4626 | case Mips::TGEI: |
| 4627 | case Mips::TGEIU: |
| 4628 | case Mips::TLTI: |
| 4629 | case Mips::TNEI: |
| 4630 | case Mips::TTLTIU: { |
| 4631 | // op: rs |
| 4632 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4633 | Value |= (op & 0x1f) << 21; |
| 4634 | // op: imm16 |
| 4635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4636 | Value |= (op & 0xffff); |
| 4637 | break; |
| 4638 | } |
| 4639 | case Mips::WRDSP: { |
| 4640 | // op: rs |
| 4641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4642 | Value |= (op & 0x1f) << 21; |
| 4643 | // op: mask |
| 4644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4645 | Value |= (op & 0x3ff) << 11; |
| 4646 | break; |
| 4647 | } |
| 4648 | case Mips::BEQZC: |
| 4649 | case Mips::BEQZC64: |
| 4650 | case Mips::BNEZC: |
| 4651 | case Mips::BNEZC64: { |
| 4652 | // op: rs |
| 4653 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4654 | Value |= (op & 0x1f) << 21; |
| 4655 | // op: offset |
| 4656 | op = getBranchTarget21OpValue(MI, OpNo: 1, Fixups, STI); |
| 4657 | Value |= (op & 0x1fffff); |
| 4658 | break; |
| 4659 | } |
| 4660 | case Mips::BEQZC_MMR6: |
| 4661 | case Mips::BNEZC_MMR6: { |
| 4662 | // op: rs |
| 4663 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4664 | Value |= (op & 0x1f) << 21; |
| 4665 | // op: offset |
| 4666 | op = getBranchTarget21OpValueMM(MI, OpNo: 1, Fixups, STI); |
| 4667 | Value |= (op & 0x1fffff); |
| 4668 | break; |
| 4669 | } |
| 4670 | case Mips::BGEZ: |
| 4671 | case Mips::BGEZ64: |
| 4672 | case Mips::BGEZAL: |
| 4673 | case Mips::BGEZALL: |
| 4674 | case Mips::BGEZL: |
| 4675 | case Mips::BGTZ: |
| 4676 | case Mips::BGTZ64: |
| 4677 | case Mips::BGTZL: |
| 4678 | case Mips::BLEZ: |
| 4679 | case Mips::BLEZ64: |
| 4680 | case Mips::BLEZL: |
| 4681 | case Mips::BLTZ: |
| 4682 | case Mips::BLTZ64: |
| 4683 | case Mips::BLTZAL: |
| 4684 | case Mips::BLTZALL: |
| 4685 | case Mips::BLTZL: { |
| 4686 | // op: rs |
| 4687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4688 | Value |= (op & 0x1f) << 21; |
| 4689 | // op: offset |
| 4690 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 4691 | Value |= (op & 0xffff); |
| 4692 | break; |
| 4693 | } |
| 4694 | case Mips::BBIT0: |
| 4695 | case Mips::BBIT032: |
| 4696 | case Mips::BBIT1: |
| 4697 | case Mips::BBIT132: { |
| 4698 | // op: rs |
| 4699 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4700 | Value |= (op & 0x1f) << 21; |
| 4701 | // op: p |
| 4702 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4703 | Value |= (op & 0x1f) << 16; |
| 4704 | // op: offset |
| 4705 | op = getBranchTargetOpValue(MI, OpNo: 2, Fixups, STI); |
| 4706 | Value |= (op & 0xffff); |
| 4707 | break; |
| 4708 | } |
| 4709 | case Mips::CMPU_EQ_QB: |
| 4710 | case Mips::CMPU_LE_QB: |
| 4711 | case Mips::CMPU_LT_QB: |
| 4712 | case Mips::CMP_EQ_PH: |
| 4713 | case Mips::CMP_LE_PH: |
| 4714 | case Mips::CMP_LT_PH: |
| 4715 | case Mips::DMULT: |
| 4716 | case Mips::DMULTu: |
| 4717 | case Mips::DSDIV: |
| 4718 | case Mips::DUDIV: |
| 4719 | case Mips::MADD: |
| 4720 | case Mips::MADDU: |
| 4721 | case Mips::MSUB: |
| 4722 | case Mips::MSUBU: |
| 4723 | case Mips::MULT: |
| 4724 | case Mips::MULTu: |
| 4725 | case Mips::SDIV: |
| 4726 | case Mips::UDIV: { |
| 4727 | // op: rs |
| 4728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4729 | Value |= (op & 0x1f) << 21; |
| 4730 | // op: rt |
| 4731 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4732 | Value |= (op & 0x1f) << 16; |
| 4733 | break; |
| 4734 | } |
| 4735 | case Mips::TEQ: |
| 4736 | case Mips::TGE: |
| 4737 | case Mips::TGEU: |
| 4738 | case Mips::TLT: |
| 4739 | case Mips::TLTU: |
| 4740 | case Mips::TNE: { |
| 4741 | // op: rs |
| 4742 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4743 | Value |= (op & 0x1f) << 21; |
| 4744 | // op: rt |
| 4745 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4746 | Value |= (op & 0x1f) << 16; |
| 4747 | // op: code_ |
| 4748 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4749 | Value |= (op & 0x3ff) << 6; |
| 4750 | break; |
| 4751 | } |
| 4752 | case Mips::BEQ: |
| 4753 | case Mips::BEQ64: |
| 4754 | case Mips::BEQC: |
| 4755 | case Mips::BEQC64: |
| 4756 | case Mips::BEQL: |
| 4757 | case Mips::BGEC: |
| 4758 | case Mips::BGEC64: |
| 4759 | case Mips::BGEUC: |
| 4760 | case Mips::BGEUC64: |
| 4761 | case Mips::BLTC: |
| 4762 | case Mips::BLTC64: |
| 4763 | case Mips::BLTUC: |
| 4764 | case Mips::BLTUC64: |
| 4765 | case Mips::BNE: |
| 4766 | case Mips::BNE64: |
| 4767 | case Mips::BNEC: |
| 4768 | case Mips::BNEC64: |
| 4769 | case Mips::BNEL: |
| 4770 | case Mips::BNVC: |
| 4771 | case Mips::BOVC: { |
| 4772 | // op: rs |
| 4773 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4774 | Value |= (op & 0x1f) << 21; |
| 4775 | // op: rt |
| 4776 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4777 | Value |= (op & 0x1f) << 16; |
| 4778 | // op: offset |
| 4779 | op = getBranchTargetOpValue(MI, OpNo: 2, Fixups, STI); |
| 4780 | Value |= (op & 0xffff); |
| 4781 | break; |
| 4782 | } |
| 4783 | case Mips::FORK: { |
| 4784 | // op: rs |
| 4785 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4786 | Value |= (op & 0x1f) << 21; |
| 4787 | // op: rt |
| 4788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4789 | Value |= (op & 0x1f) << 16; |
| 4790 | // op: rd |
| 4791 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4792 | Value |= (op & 0x1f) << 11; |
| 4793 | break; |
| 4794 | } |
| 4795 | case Mips::GINVT: { |
| 4796 | // op: rs |
| 4797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4798 | Value |= (op & 0x1f) << 21; |
| 4799 | // op: type_ |
| 4800 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4801 | Value |= (op & 0x3) << 8; |
| 4802 | break; |
| 4803 | } |
| 4804 | case Mips::JALRC16_MMR6: |
| 4805 | case Mips::JRC16_MMR6: { |
| 4806 | // op: rs |
| 4807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4808 | Value |= (op & 0x1f) << 5; |
| 4809 | break; |
| 4810 | } |
| 4811 | case Mips::JALR16_MM: |
| 4812 | case Mips::JALRS16_MM: |
| 4813 | case Mips::JR16_MM: |
| 4814 | case Mips::JRC16_MM: { |
| 4815 | // op: rs |
| 4816 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4817 | Value |= (op & 0x1f); |
| 4818 | break; |
| 4819 | } |
| 4820 | case Mips::ADDIUPC_MM: { |
| 4821 | // op: rs |
| 4822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4823 | Value |= (op & 0x7) << 23; |
| 4824 | // op: imm |
| 4825 | op = getSimm23Lsl2Encoding(MI, OpNo: 1, Fixups, STI); |
| 4826 | Value |= (op & 0x7fffff); |
| 4827 | break; |
| 4828 | } |
| 4829 | case Mips::BEQZ16_MM: |
| 4830 | case Mips::BEQZC16_MMR6: |
| 4831 | case Mips::BNEZ16_MM: |
| 4832 | case Mips::BNEZC16_MMR6: { |
| 4833 | // op: rs |
| 4834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4835 | Value |= (op & 0x7) << 7; |
| 4836 | // op: offset |
| 4837 | op = getBranchTarget7OpValueMM(MI, OpNo: 1, Fixups, STI); |
| 4838 | Value |= (op & 0x7f); |
| 4839 | break; |
| 4840 | } |
| 4841 | case Mips::CTCMSA: { |
| 4842 | // op: rs |
| 4843 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4844 | Value |= (op & 0x1f) << 11; |
| 4845 | // op: cd |
| 4846 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4847 | Value |= (op & 0x1f) << 6; |
| 4848 | break; |
| 4849 | } |
| 4850 | case Mips::FILL_B: |
| 4851 | case Mips::FILL_D: |
| 4852 | case Mips::FILL_H: |
| 4853 | case Mips::FILL_W: { |
| 4854 | // op: rs |
| 4855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4856 | Value |= (op & 0x1f) << 11; |
| 4857 | // op: wd |
| 4858 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4859 | Value |= (op & 0x1f) << 6; |
| 4860 | break; |
| 4861 | } |
| 4862 | case Mips::MTHI_DSP_MM: |
| 4863 | case Mips::MTHLIP_MM: |
| 4864 | case Mips::MTLO_DSP_MM: |
| 4865 | case Mips::SHILOV_MM: { |
| 4866 | // op: rs |
| 4867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4868 | Value |= (op & 0x1f) << 16; |
| 4869 | // op: ac |
| 4870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4871 | Value |= (op & 0x3) << 14; |
| 4872 | break; |
| 4873 | } |
| 4874 | case Mips::JALRS_MM: |
| 4875 | case Mips::JALR_HB_MM: |
| 4876 | case Mips::JALR_MM: { |
| 4877 | // op: rs |
| 4878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4879 | Value |= (op & 0x1f) << 16; |
| 4880 | // op: rd |
| 4881 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4882 | Value |= (op & 0x1f) << 21; |
| 4883 | break; |
| 4884 | } |
| 4885 | case Mips::CLO_MMR6: { |
| 4886 | // op: rs |
| 4887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4888 | Value |= (op & 0x1f) << 16; |
| 4889 | // op: rt |
| 4890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4891 | Value |= (op & 0x1f) << 21; |
| 4892 | break; |
| 4893 | } |
| 4894 | case Mips::AUI_MMR6: { |
| 4895 | // op: rs |
| 4896 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4897 | Value |= (op & 0x1f) << 16; |
| 4898 | // op: rt |
| 4899 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4900 | Value |= (op & 0x1f) << 21; |
| 4901 | // op: imm |
| 4902 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4903 | Value |= (op & 0xffff); |
| 4904 | break; |
| 4905 | } |
| 4906 | case Mips::ADDi_MM: |
| 4907 | case Mips::ADDiu_MM: |
| 4908 | case Mips::ANDi_MM: |
| 4909 | case Mips::ORi_MM: |
| 4910 | case Mips::XORi_MM: { |
| 4911 | // op: rs |
| 4912 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4913 | Value |= (op & 0x1f) << 16; |
| 4914 | // op: rt |
| 4915 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4916 | Value |= (op & 0x1f) << 21; |
| 4917 | // op: imm16 |
| 4918 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4919 | Value |= (op & 0xffff); |
| 4920 | break; |
| 4921 | } |
| 4922 | case Mips::MTHI_DSP: |
| 4923 | case Mips::MTLO_DSP: { |
| 4924 | // op: rs |
| 4925 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4926 | Value |= (op & 0x1f) << 21; |
| 4927 | // op: ac |
| 4928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4929 | Value |= (op & 0x3) << 11; |
| 4930 | break; |
| 4931 | } |
| 4932 | case Mips::YIELD: { |
| 4933 | // op: rs |
| 4934 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4935 | Value |= (op & 0x1f) << 21; |
| 4936 | // op: rd |
| 4937 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4938 | Value |= (op & 0x1f) << 11; |
| 4939 | break; |
| 4940 | } |
| 4941 | case Mips::CLZ_MMR6: { |
| 4942 | // op: rs |
| 4943 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4944 | Value |= (op & 0x1f) << 21; |
| 4945 | // op: rt |
| 4946 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4947 | Value |= (op & 0x1f) << 11; |
| 4948 | break; |
| 4949 | } |
| 4950 | case Mips::AUI: |
| 4951 | case Mips::DAUI: { |
| 4952 | // op: rs |
| 4953 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4954 | Value |= (op & 0x1f) << 21; |
| 4955 | // op: rt |
| 4956 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4957 | Value |= (op & 0x1f) << 16; |
| 4958 | // op: imm |
| 4959 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4960 | Value |= (op & 0xffff); |
| 4961 | break; |
| 4962 | } |
| 4963 | case Mips::SEQi: |
| 4964 | case Mips::SNEi: { |
| 4965 | // op: rs |
| 4966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4967 | Value |= (op & 0x1f) << 21; |
| 4968 | // op: rt |
| 4969 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4970 | Value |= (op & 0x1f) << 16; |
| 4971 | // op: imm10 |
| 4972 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4973 | Value |= (op & 0x3ff) << 6; |
| 4974 | break; |
| 4975 | } |
| 4976 | case Mips::ADDi: |
| 4977 | case Mips::ADDiu: |
| 4978 | case Mips::ANDi: |
| 4979 | case Mips::ANDi64: |
| 4980 | case Mips::DADDi: |
| 4981 | case Mips::DADDiu: |
| 4982 | case Mips::ORi: |
| 4983 | case Mips::ORi64: |
| 4984 | case Mips::XORi: |
| 4985 | case Mips::XORi64: { |
| 4986 | // op: rs |
| 4987 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4988 | Value |= (op & 0x1f) << 21; |
| 4989 | // op: rt |
| 4990 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4991 | Value |= (op & 0x1f) << 16; |
| 4992 | // op: imm16 |
| 4993 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4994 | Value |= (op & 0xffff); |
| 4995 | break; |
| 4996 | } |
| 4997 | case Mips::PRECR_SRA_PH_W: |
| 4998 | case Mips::PRECR_SRA_R_PH_W: { |
| 4999 | // op: rs |
| 5000 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5001 | Value |= (op & 0x1f) << 21; |
| 5002 | // op: rt |
| 5003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5004 | Value |= (op & 0x1f) << 16; |
| 5005 | // op: sa |
| 5006 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5007 | Value |= (op & 0x1f) << 11; |
| 5008 | break; |
| 5009 | } |
| 5010 | case Mips::CRC32B: |
| 5011 | case Mips::CRC32CB: |
| 5012 | case Mips::CRC32CD: |
| 5013 | case Mips::CRC32CH: |
| 5014 | case Mips::CRC32CW: |
| 5015 | case Mips::CRC32D: |
| 5016 | case Mips::CRC32H: |
| 5017 | case Mips::CRC32W: { |
| 5018 | // op: rs |
| 5019 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5020 | Value |= (op & 0x1f) << 21; |
| 5021 | // op: rt |
| 5022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5023 | Value |= (op & 0x1f) << 16; |
| 5024 | break; |
| 5025 | } |
| 5026 | case Mips::CMPGDU_EQ_QB: |
| 5027 | case Mips::CMPGDU_LE_QB: |
| 5028 | case Mips::CMPGDU_LT_QB: |
| 5029 | case Mips::CMPGU_EQ_QB: |
| 5030 | case Mips::CMPGU_LE_QB: |
| 5031 | case Mips::CMPGU_LT_QB: |
| 5032 | case Mips::PACKRL_PH: |
| 5033 | case Mips::PICK_PH: |
| 5034 | case Mips::PICK_QB: |
| 5035 | case Mips::PRECRQU_S_QB_PH: |
| 5036 | case Mips::PRECRQ_PH_W: |
| 5037 | case Mips::PRECRQ_QB_PH: |
| 5038 | case Mips::PRECRQ_RS_PH_W: |
| 5039 | case Mips::PRECR_QB_PH: { |
| 5040 | // op: rs |
| 5041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5042 | Value |= (op & 0x1f) << 21; |
| 5043 | // op: rt |
| 5044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5045 | Value |= (op & 0x1f) << 16; |
| 5046 | // op: rd |
| 5047 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5048 | Value |= (op & 0x1f) << 11; |
| 5049 | break; |
| 5050 | } |
| 5051 | case Mips::DLSA: |
| 5052 | case Mips::LSA: { |
| 5053 | // op: rs |
| 5054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5055 | Value |= (op & 0x1f) << 21; |
| 5056 | // op: rt |
| 5057 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5058 | Value |= (op & 0x1f) << 16; |
| 5059 | // op: rd |
| 5060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5061 | Value |= (op & 0x1f) << 11; |
| 5062 | // op: sa |
| 5063 | op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI); |
| 5064 | Value |= (op & 0x3) << 6; |
| 5065 | break; |
| 5066 | } |
| 5067 | case Mips::MOVE16_MM: |
| 5068 | case Mips::MOVE16_MMR6: { |
| 5069 | // op: rs |
| 5070 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5071 | Value |= (op & 0x1f); |
| 5072 | // op: rd |
| 5073 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5074 | Value |= (op & 0x1f) << 5; |
| 5075 | break; |
| 5076 | } |
| 5077 | case Mips::ADDU16_MMR6: |
| 5078 | case Mips::SUBU16_MMR6: { |
| 5079 | // op: rs |
| 5080 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5081 | Value |= (op & 0x7) << 7; |
| 5082 | // op: rt |
| 5083 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5084 | Value |= (op & 0x7) << 4; |
| 5085 | // op: rd |
| 5086 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5087 | Value |= (op & 0x7) << 1; |
| 5088 | break; |
| 5089 | } |
| 5090 | case Mips::DI: |
| 5091 | case Mips::DI_MM: |
| 5092 | case Mips::DI_MMR6: |
| 5093 | case Mips::DMT: |
| 5094 | case Mips::DVP: |
| 5095 | case Mips::DVPE: |
| 5096 | case Mips::EI: |
| 5097 | case Mips::EI_MM: |
| 5098 | case Mips::EI_MMR6: |
| 5099 | case Mips::EMT: |
| 5100 | case Mips::EVP: |
| 5101 | case Mips::EVPE: { |
| 5102 | // op: rt |
| 5103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5104 | Value |= (op & 0x1f) << 16; |
| 5105 | break; |
| 5106 | } |
| 5107 | case Mips::EXTP: |
| 5108 | case Mips::EXTPDP: |
| 5109 | case Mips::EXTPDPV: |
| 5110 | case Mips::EXTPV: |
| 5111 | case Mips::EXTRV_RS_W: |
| 5112 | case Mips::EXTRV_R_W: |
| 5113 | case Mips::EXTRV_S_H: |
| 5114 | case Mips::EXTRV_W: |
| 5115 | case Mips::EXTR_RS_W: |
| 5116 | case Mips::EXTR_R_W: |
| 5117 | case Mips::EXTR_S_H: |
| 5118 | case Mips::EXTR_W: { |
| 5119 | // op: rt |
| 5120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5121 | Value |= (op & 0x1f) << 16; |
| 5122 | // op: ac |
| 5123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5124 | Value |= (op & 0x3) << 11; |
| 5125 | // op: shift_rs |
| 5126 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5127 | Value |= (op & 0x1f) << 21; |
| 5128 | break; |
| 5129 | } |
| 5130 | case Mips::LL64_R6: |
| 5131 | case Mips::LLD_R6: |
| 5132 | case Mips::LL_R6: { |
| 5133 | // op: rt |
| 5134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5135 | Value |= (op & 0x1f) << 16; |
| 5136 | // op: addr |
| 5137 | op = getMemEncoding(MI, OpNo: 1, Fixups, STI); |
| 5138 | Value |= (op & 0x1f0000) << 5; |
| 5139 | Value |= (op & 0x1ff) << 7; |
| 5140 | break; |
| 5141 | } |
| 5142 | case Mips::LB: |
| 5143 | case Mips::LB64: |
| 5144 | case Mips::LBu: |
| 5145 | case Mips::LBu64: |
| 5146 | case Mips::LD: |
| 5147 | case Mips::LDC1: |
| 5148 | case Mips::LDC164: |
| 5149 | case Mips::LDC2: |
| 5150 | case Mips::LDC3: |
| 5151 | case Mips::LDL: |
| 5152 | case Mips::LDR: |
| 5153 | case Mips::LEA_ADDiu: |
| 5154 | case Mips::LEA_ADDiu64: |
| 5155 | case Mips::LH: |
| 5156 | case Mips::LH64: |
| 5157 | case Mips::LHu: |
| 5158 | case Mips::LHu64: |
| 5159 | case Mips::LL: |
| 5160 | case Mips::LL64: |
| 5161 | case Mips::LLD: |
| 5162 | case Mips::LW: |
| 5163 | case Mips::LW64: |
| 5164 | case Mips::LWC1: |
| 5165 | case Mips::LWC2: |
| 5166 | case Mips::LWC3: |
| 5167 | case Mips::LWDSP: |
| 5168 | case Mips::LWL: |
| 5169 | case Mips::LWL64: |
| 5170 | case Mips::LWR: |
| 5171 | case Mips::LWR64: |
| 5172 | case Mips::LWu: |
| 5173 | case Mips::SB: |
| 5174 | case Mips::SB64: |
| 5175 | case Mips::SD: |
| 5176 | case Mips::SDC1: |
| 5177 | case Mips::SDC164: |
| 5178 | case Mips::SDC2: |
| 5179 | case Mips::SDC3: |
| 5180 | case Mips::SDL: |
| 5181 | case Mips::SDR: |
| 5182 | case Mips::SH: |
| 5183 | case Mips::SH64: |
| 5184 | case Mips::SW: |
| 5185 | case Mips::SW64: |
| 5186 | case Mips::SWC1: |
| 5187 | case Mips::SWC2: |
| 5188 | case Mips::SWC3: |
| 5189 | case Mips::SWDSP: |
| 5190 | case Mips::SWL: |
| 5191 | case Mips::SWL64: |
| 5192 | case Mips::SWR: |
| 5193 | case Mips::SWR64: { |
| 5194 | // op: rt |
| 5195 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5196 | Value |= (op & 0x1f) << 16; |
| 5197 | // op: addr |
| 5198 | op = getMemEncoding(MI, OpNo: 1, Fixups, STI); |
| 5199 | Value |= (op & 0x1f0000) << 5; |
| 5200 | Value |= (op & 0xffff); |
| 5201 | break; |
| 5202 | } |
| 5203 | case Mips::LDC2_R6: |
| 5204 | case Mips::LWC2_R6: |
| 5205 | case Mips::SDC2_R6: |
| 5206 | case Mips::SWC2_R6: { |
| 5207 | // op: rt |
| 5208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5209 | Value |= (op & 0x1f) << 16; |
| 5210 | // op: addr |
| 5211 | op = getMemEncoding(MI, OpNo: 1, Fixups, STI); |
| 5212 | Value |= (op & 0x1f0000) >> 5; |
| 5213 | Value |= (op & 0x7ff); |
| 5214 | break; |
| 5215 | } |
| 5216 | case Mips::CFC1: |
| 5217 | case Mips::DMFC1: |
| 5218 | case Mips::MFC1: |
| 5219 | case Mips::MFC1_D64: |
| 5220 | case Mips::MFHC1_D32: |
| 5221 | case Mips::MFHC1_D64: { |
| 5222 | // op: rt |
| 5223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5224 | Value |= (op & 0x1f) << 16; |
| 5225 | // op: fs |
| 5226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5227 | Value |= (op & 0x1f) << 11; |
| 5228 | break; |
| 5229 | } |
| 5230 | case Mips::DMFC2_OCTEON: |
| 5231 | case Mips::DMTC2_OCTEON: |
| 5232 | case Mips::LUi: |
| 5233 | case Mips::LUi64: |
| 5234 | case Mips::LUi_MM: { |
| 5235 | // op: rt |
| 5236 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5237 | Value |= (op & 0x1f) << 16; |
| 5238 | // op: imm16 |
| 5239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5240 | Value |= (op & 0xffff); |
| 5241 | break; |
| 5242 | } |
| 5243 | case Mips::BEQZALC: |
| 5244 | case Mips::BGTZALC: |
| 5245 | case Mips::BGTZC: |
| 5246 | case Mips::BGTZC64: |
| 5247 | case Mips::BLEZALC: |
| 5248 | case Mips::BLEZC: |
| 5249 | case Mips::BLEZC64: |
| 5250 | case Mips::BNEZALC: { |
| 5251 | // op: rt |
| 5252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5253 | Value |= (op & 0x1f) << 16; |
| 5254 | // op: offset |
| 5255 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 5256 | Value |= (op & 0xffff); |
| 5257 | break; |
| 5258 | } |
| 5259 | case Mips::BC1EQZC_MMR6: |
| 5260 | case Mips::BC1NEZC_MMR6: |
| 5261 | case Mips::BC2EQZC_MMR6: |
| 5262 | case Mips::BC2NEZC_MMR6: { |
| 5263 | // op: rt |
| 5264 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5265 | Value |= (op & 0x1f) << 16; |
| 5266 | // op: offset |
| 5267 | op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI); |
| 5268 | Value |= (op & 0xffff); |
| 5269 | break; |
| 5270 | } |
| 5271 | case Mips::JIALC: |
| 5272 | case Mips::JIALC64: |
| 5273 | case Mips::JIALC_MMR6: |
| 5274 | case Mips::JIC: |
| 5275 | case Mips::JIC64: |
| 5276 | case Mips::JIC_MMR6: { |
| 5277 | // op: rt |
| 5278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5279 | Value |= (op & 0x1f) << 16; |
| 5280 | // op: offset |
| 5281 | op = getJumpOffset16OpValue(MI, OpNo: 1, Fixups, STI); |
| 5282 | Value |= (op & 0xffff); |
| 5283 | break; |
| 5284 | } |
| 5285 | case Mips::RDHWR: |
| 5286 | case Mips::RDHWR64: { |
| 5287 | // op: rt |
| 5288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5289 | Value |= (op & 0x1f) << 16; |
| 5290 | // op: rd |
| 5291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5292 | Value |= (op & 0x1f) << 11; |
| 5293 | // op: sel |
| 5294 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5295 | Value |= (op & 0x7) << 6; |
| 5296 | break; |
| 5297 | } |
| 5298 | case Mips::DMFC0: |
| 5299 | case Mips::DMFC2: |
| 5300 | case Mips::DMFGC0: |
| 5301 | case Mips::MFC0: |
| 5302 | case Mips::MFC2: |
| 5303 | case Mips::MFGC0: |
| 5304 | case Mips::MFHGC0: { |
| 5305 | // op: rt |
| 5306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5307 | Value |= (op & 0x1f) << 16; |
| 5308 | // op: rd |
| 5309 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5310 | Value |= (op & 0x1f) << 11; |
| 5311 | // op: sel |
| 5312 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5313 | Value |= (op & 0x7); |
| 5314 | break; |
| 5315 | } |
| 5316 | case Mips::SAA: |
| 5317 | case Mips::SAAD: { |
| 5318 | // op: rt |
| 5319 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5320 | Value |= (op & 0x1f) << 16; |
| 5321 | // op: rs |
| 5322 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5323 | Value |= (op & 0x1f) << 21; |
| 5324 | break; |
| 5325 | } |
| 5326 | case Mips::SLTi: |
| 5327 | case Mips::SLTi64: |
| 5328 | case Mips::SLTiu: |
| 5329 | case Mips::SLTiu64: { |
| 5330 | // op: rt |
| 5331 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5332 | Value |= (op & 0x1f) << 16; |
| 5333 | // op: rs |
| 5334 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5335 | Value |= (op & 0x1f) << 21; |
| 5336 | // op: imm16 |
| 5337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5338 | Value |= (op & 0xffff); |
| 5339 | break; |
| 5340 | } |
| 5341 | case Mips::CINS: |
| 5342 | case Mips::CINS32: |
| 5343 | case Mips::CINS64_32: |
| 5344 | case Mips::CINS_i32: |
| 5345 | case Mips::EXTS: |
| 5346 | case Mips::EXTS32: { |
| 5347 | // op: rt |
| 5348 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5349 | Value |= (op & 0x1f) << 16; |
| 5350 | // op: rs |
| 5351 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5352 | Value |= (op & 0x1f) << 21; |
| 5353 | // op: pos |
| 5354 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5355 | Value |= (op & 0x1f) << 6; |
| 5356 | // op: lenm1 |
| 5357 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5358 | Value |= (op & 0x1f) << 11; |
| 5359 | break; |
| 5360 | } |
| 5361 | case Mips::DINS: |
| 5362 | case Mips::DINSM: |
| 5363 | case Mips::DINSU: |
| 5364 | case Mips::INS: { |
| 5365 | // op: rt |
| 5366 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5367 | Value |= (op & 0x1f) << 16; |
| 5368 | // op: rs |
| 5369 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5370 | Value |= (op & 0x1f) << 21; |
| 5371 | // op: pos |
| 5372 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5373 | Value |= (op & 0x1f) << 6; |
| 5374 | // op: size |
| 5375 | op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI); |
| 5376 | Value |= (op & 0x1f) << 11; |
| 5377 | break; |
| 5378 | } |
| 5379 | case Mips::DEXT: |
| 5380 | case Mips::DEXT64_32: |
| 5381 | case Mips::DEXTM: |
| 5382 | case Mips::DEXTU: |
| 5383 | case Mips::EXT: { |
| 5384 | // op: rt |
| 5385 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5386 | Value |= (op & 0x1f) << 16; |
| 5387 | // op: rs |
| 5388 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5389 | Value |= (op & 0x1f) << 21; |
| 5390 | // op: pos |
| 5391 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5392 | Value |= (op & 0x1f) << 6; |
| 5393 | // op: size |
| 5394 | op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI); |
| 5395 | Value |= (op & 0x1f) << 11; |
| 5396 | break; |
| 5397 | } |
| 5398 | case Mips::APPEND: |
| 5399 | case Mips::BALIGN: |
| 5400 | case Mips::PREPEND: { |
| 5401 | // op: rt |
| 5402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5403 | Value |= (op & 0x1f) << 16; |
| 5404 | // op: rs |
| 5405 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5406 | Value |= (op & 0x1f) << 21; |
| 5407 | // op: sa |
| 5408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5409 | Value |= (op & 0x1f) << 11; |
| 5410 | break; |
| 5411 | } |
| 5412 | case Mips::INSV: { |
| 5413 | // op: rt |
| 5414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5415 | Value |= (op & 0x1f) << 16; |
| 5416 | // op: rs |
| 5417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5418 | Value |= (op & 0x1f) << 21; |
| 5419 | break; |
| 5420 | } |
| 5421 | case Mips::LBE_MM: |
| 5422 | case Mips::LBuE_MM: |
| 5423 | case Mips::LHE_MM: |
| 5424 | case Mips::LHuE_MM: |
| 5425 | case Mips::LLE_MM: |
| 5426 | case Mips::LWE_MM: |
| 5427 | case Mips::SBE_MM: |
| 5428 | case Mips::SHE_MM: |
| 5429 | case Mips::SWE_MM: { |
| 5430 | // op: rt |
| 5431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5432 | Value |= (op & 0x1f) << 21; |
| 5433 | // op: addr |
| 5434 | op = getMemEncoding(MI, OpNo: 1, Fixups, STI); |
| 5435 | Value |= (op & 0x1f0000); |
| 5436 | Value |= (op & 0x1ff); |
| 5437 | break; |
| 5438 | } |
| 5439 | case Mips::LWU_MM: { |
| 5440 | // op: rt |
| 5441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5442 | Value |= (op & 0x1f) << 21; |
| 5443 | // op: addr |
| 5444 | op = getMemEncoding(MI, OpNo: 1, Fixups, STI); |
| 5445 | Value |= (op & 0x1f0000); |
| 5446 | Value |= (op & 0xfff); |
| 5447 | break; |
| 5448 | } |
| 5449 | case Mips::LEA_ADDiu_MM: |
| 5450 | case Mips::LH_MM: |
| 5451 | case Mips::LHu_MM: |
| 5452 | case Mips::LWDSP_MM: |
| 5453 | case Mips::LW_MM: |
| 5454 | case Mips::LW_MMR6: |
| 5455 | case Mips::SB_MM: |
| 5456 | case Mips::SB_MMR6: |
| 5457 | case Mips::SH_MM: |
| 5458 | case Mips::SH_MMR6: |
| 5459 | case Mips::SWDSP_MM: |
| 5460 | case Mips::SW_MM: |
| 5461 | case Mips::SW_MMR6: { |
| 5462 | // op: rt |
| 5463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5464 | Value |= (op & 0x1f) << 21; |
| 5465 | // op: addr |
| 5466 | op = getMemEncoding(MI, OpNo: 1, Fixups, STI); |
| 5467 | Value |= (op & 0x1fffff); |
| 5468 | break; |
| 5469 | } |
| 5470 | case Mips::LWP_MM: |
| 5471 | case Mips::SWP_MM: { |
| 5472 | // op: rt |
| 5473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5474 | Value |= (op & 0x1f) << 21; |
| 5475 | // op: addr |
| 5476 | op = getMemEncoding(MI, OpNo: 2, Fixups, STI); |
| 5477 | Value |= (op & 0x1f0000); |
| 5478 | Value |= (op & 0xfff); |
| 5479 | break; |
| 5480 | } |
| 5481 | case Mips::LDC2_MMR6: |
| 5482 | case Mips::LWC2_MMR6: |
| 5483 | case Mips::SDC2_MMR6: |
| 5484 | case Mips::SWC2_MMR6: { |
| 5485 | // op: rt |
| 5486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5487 | Value |= (op & 0x1f) << 21; |
| 5488 | // op: addr |
| 5489 | op = getMemEncodingMMImm11(MI, OpNo: 1, Fixups, STI); |
| 5490 | Value |= (op & 0x1f0000); |
| 5491 | Value |= (op & 0x7ff); |
| 5492 | break; |
| 5493 | } |
| 5494 | case Mips::LL_MM: |
| 5495 | case Mips::LWL_MM: |
| 5496 | case Mips::LWR_MM: |
| 5497 | case Mips::SWL_MM: |
| 5498 | case Mips::SWR_MM: { |
| 5499 | // op: rt |
| 5500 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5501 | Value |= (op & 0x1f) << 21; |
| 5502 | // op: addr |
| 5503 | op = getMemEncodingMMImm12(MI, OpNo: 1, Fixups, STI); |
| 5504 | Value |= (op & 0x1f0000); |
| 5505 | Value |= (op & 0xfff); |
| 5506 | break; |
| 5507 | } |
| 5508 | case Mips::LB_MM: |
| 5509 | case Mips::LBu_MM: |
| 5510 | case Mips::LDC1_MM_D32: |
| 5511 | case Mips::LDC1_MM_D64: |
| 5512 | case Mips::LWC1_MM: |
| 5513 | case Mips::SDC1_MM_D32: |
| 5514 | case Mips::SDC1_MM_D64: |
| 5515 | case Mips::SWC1_MM: { |
| 5516 | // op: rt |
| 5517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5518 | Value |= (op & 0x1f) << 21; |
| 5519 | // op: addr |
| 5520 | op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI); |
| 5521 | Value |= (op & 0x1fffff); |
| 5522 | break; |
| 5523 | } |
| 5524 | case Mips::LL_MMR6: |
| 5525 | case Mips::LWLE_MM: |
| 5526 | case Mips::LWRE_MM: |
| 5527 | case Mips::SWLE_MM: |
| 5528 | case Mips::SWRE_MM: { |
| 5529 | // op: rt |
| 5530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5531 | Value |= (op & 0x1f) << 21; |
| 5532 | // op: addr |
| 5533 | op = getMemEncodingMMImm9(MI, OpNo: 1, Fixups, STI); |
| 5534 | Value |= (op & 0x1f0000); |
| 5535 | Value |= (op & 0x1ff); |
| 5536 | break; |
| 5537 | } |
| 5538 | case Mips::CFC1_MM: |
| 5539 | case Mips::MFC1_MM: |
| 5540 | case Mips::MFC1_MMR6: |
| 5541 | case Mips::MFHC1_D32_MM: |
| 5542 | case Mips::MFHC1_D64_MM: { |
| 5543 | // op: rt |
| 5544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5545 | Value |= (op & 0x1f) << 21; |
| 5546 | // op: fs |
| 5547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5548 | Value |= (op & 0x1f) << 16; |
| 5549 | break; |
| 5550 | } |
| 5551 | case Mips::REPL_QB_MM: { |
| 5552 | // op: rt |
| 5553 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5554 | Value |= (op & 0x1f) << 21; |
| 5555 | // op: imm |
| 5556 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5557 | Value |= (op & 0xff) << 13; |
| 5558 | break; |
| 5559 | } |
| 5560 | case Mips::ALUIPC_MMR6: |
| 5561 | case Mips::AUIPC_MMR6: { |
| 5562 | // op: rt |
| 5563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5564 | Value |= (op & 0x1f) << 21; |
| 5565 | // op: imm |
| 5566 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5567 | Value |= (op & 0xffff); |
| 5568 | break; |
| 5569 | } |
| 5570 | case Mips::EXTPDP_MM: |
| 5571 | case Mips::EXTP_MM: |
| 5572 | case Mips::EXTR_RS_W_MM: |
| 5573 | case Mips::EXTR_R_W_MM: |
| 5574 | case Mips::EXTR_S_H_MM: |
| 5575 | case Mips::EXTR_W_MM: { |
| 5576 | // op: rt |
| 5577 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5578 | Value |= (op & 0x1f) << 21; |
| 5579 | // op: imm |
| 5580 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5581 | Value |= (op & 0x1f) << 16; |
| 5582 | // op: ac |
| 5583 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5584 | Value |= (op & 0x3) << 14; |
| 5585 | break; |
| 5586 | } |
| 5587 | case Mips::ADDIUPC_MMR6: |
| 5588 | case Mips::LWPC_MMR6: { |
| 5589 | // op: rt |
| 5590 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5591 | Value |= (op & 0x1f) << 21; |
| 5592 | // op: imm |
| 5593 | op = getSimm19Lsl2Encoding(MI, OpNo: 1, Fixups, STI); |
| 5594 | Value |= (op & 0x7ffff); |
| 5595 | break; |
| 5596 | } |
| 5597 | case Mips::LUI_MMR6: { |
| 5598 | // op: rt |
| 5599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5600 | Value |= (op & 0x1f) << 21; |
| 5601 | // op: imm16 |
| 5602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5603 | Value |= (op & 0xffff); |
| 5604 | break; |
| 5605 | } |
| 5606 | case Mips::CFC2_MM: |
| 5607 | case Mips::MFC2_MMR6: |
| 5608 | case Mips::MFHC2_MMR6: { |
| 5609 | // op: rt |
| 5610 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5611 | Value |= (op & 0x1f) << 21; |
| 5612 | // op: impl |
| 5613 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5614 | Value |= (op & 0x1f) << 16; |
| 5615 | break; |
| 5616 | } |
| 5617 | case Mips::RDDSP_MM: |
| 5618 | case Mips::WRDSP_MM: { |
| 5619 | // op: rt |
| 5620 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5621 | Value |= (op & 0x1f) << 21; |
| 5622 | // op: mask |
| 5623 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5624 | Value |= (op & 0x7f) << 14; |
| 5625 | break; |
| 5626 | } |
| 5627 | case Mips::BGTZC_MMR6: |
| 5628 | case Mips::BLEZC_MMR6: { |
| 5629 | // op: rt |
| 5630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5631 | Value |= (op & 0x1f) << 21; |
| 5632 | // op: offset |
| 5633 | op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 1, Fixups, STI); |
| 5634 | Value |= (op & 0xffff); |
| 5635 | break; |
| 5636 | } |
| 5637 | case Mips::BEQZALC_MMR6: |
| 5638 | case Mips::BGTZALC_MMR6: |
| 5639 | case Mips::BLEZALC_MMR6: |
| 5640 | case Mips::BNEZALC_MMR6: { |
| 5641 | // op: rt |
| 5642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5643 | Value |= (op & 0x1f) << 21; |
| 5644 | // op: offset |
| 5645 | op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI); |
| 5646 | Value |= (op & 0xffff); |
| 5647 | break; |
| 5648 | } |
| 5649 | case Mips::RDHWR_MM: |
| 5650 | case Mips::RDPGPR_MMR6: { |
| 5651 | // op: rt |
| 5652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5653 | Value |= (op & 0x1f) << 21; |
| 5654 | // op: rd |
| 5655 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5656 | Value |= (op & 0x1f) << 16; |
| 5657 | break; |
| 5658 | } |
| 5659 | case Mips::MFC0_MM: { |
| 5660 | // op: rt |
| 5661 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5662 | Value |= (op & 0x1f) << 21; |
| 5663 | // op: rd |
| 5664 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5665 | Value |= (op & 0x1f) << 16; |
| 5666 | // op: sel |
| 5667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5668 | Value |= (op & 0x7) << 11; |
| 5669 | break; |
| 5670 | } |
| 5671 | case Mips::ABSQ_S_PH_MM: |
| 5672 | case Mips::ABSQ_S_QB_MMR2: |
| 5673 | case Mips::ABSQ_S_W_MM: |
| 5674 | case Mips::BITREV_MM: |
| 5675 | case Mips::JALRC_HB_MMR6: |
| 5676 | case Mips::JALRC_MMR6: |
| 5677 | case Mips::PRECEQU_PH_QBLA_MM: |
| 5678 | case Mips::PRECEQU_PH_QBL_MM: |
| 5679 | case Mips::PRECEQU_PH_QBRA_MM: |
| 5680 | case Mips::PRECEQU_PH_QBR_MM: |
| 5681 | case Mips::PRECEQ_W_PHL_MM: |
| 5682 | case Mips::PRECEQ_W_PHR_MM: |
| 5683 | case Mips::PRECEU_PH_QBLA_MM: |
| 5684 | case Mips::PRECEU_PH_QBL_MM: |
| 5685 | case Mips::PRECEU_PH_QBRA_MM: |
| 5686 | case Mips::PRECEU_PH_QBR_MM: |
| 5687 | case Mips::RADDU_W_QB_MM: |
| 5688 | case Mips::REPLV_PH_MM: |
| 5689 | case Mips::REPLV_QB_MM: |
| 5690 | case Mips::WRPGPR_MMR6: |
| 5691 | case Mips::WSBH_MMR6: { |
| 5692 | // op: rt |
| 5693 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5694 | Value |= (op & 0x1f) << 21; |
| 5695 | // op: rs |
| 5696 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5697 | Value |= (op & 0x1f) << 16; |
| 5698 | break; |
| 5699 | } |
| 5700 | case Mips::BALIGN_MMR2: { |
| 5701 | // op: rt |
| 5702 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5703 | Value |= (op & 0x1f) << 21; |
| 5704 | // op: rs |
| 5705 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5706 | Value |= (op & 0x1f) << 16; |
| 5707 | // op: bp |
| 5708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5709 | Value |= (op & 0x3) << 14; |
| 5710 | break; |
| 5711 | } |
| 5712 | case Mips::ADDIU_MMR6: |
| 5713 | case Mips::ANDI_MMR6: |
| 5714 | case Mips::ORI_MMR6: |
| 5715 | case Mips::SLTi_MM: |
| 5716 | case Mips::SLTiu_MM: |
| 5717 | case Mips::XORI_MMR6: { |
| 5718 | // op: rt |
| 5719 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5720 | Value |= (op & 0x1f) << 21; |
| 5721 | // op: rs |
| 5722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5723 | Value |= (op & 0x1f) << 16; |
| 5724 | // op: imm16 |
| 5725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5726 | Value |= (op & 0xffff); |
| 5727 | break; |
| 5728 | } |
| 5729 | case Mips::BNVC_MMR6: |
| 5730 | case Mips::BOVC_MMR6: { |
| 5731 | // op: rt |
| 5732 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5733 | Value |= (op & 0x1f) << 21; |
| 5734 | // op: rs |
| 5735 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5736 | Value |= (op & 0x1f) << 16; |
| 5737 | // op: offset |
| 5738 | op = getBranchTargetOpValueMMR6(MI, OpNo: 2, Fixups, STI); |
| 5739 | Value |= (op & 0xffff); |
| 5740 | break; |
| 5741 | } |
| 5742 | case Mips::INS_MM: { |
| 5743 | // op: rt |
| 5744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5745 | Value |= (op & 0x1f) << 21; |
| 5746 | // op: rs |
| 5747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5748 | Value |= (op & 0x1f) << 16; |
| 5749 | // op: pos |
| 5750 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5751 | Value |= (op & 0x1f) << 6; |
| 5752 | // op: size |
| 5753 | op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI); |
| 5754 | Value |= (op & 0x1f) << 11; |
| 5755 | break; |
| 5756 | } |
| 5757 | case Mips::EXT_MM: { |
| 5758 | // op: rt |
| 5759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5760 | Value |= (op & 0x1f) << 21; |
| 5761 | // op: rs |
| 5762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5763 | Value |= (op & 0x1f) << 16; |
| 5764 | // op: pos |
| 5765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5766 | Value |= (op & 0x1f) << 6; |
| 5767 | // op: size |
| 5768 | op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI); |
| 5769 | Value |= (op & 0x1f) << 11; |
| 5770 | break; |
| 5771 | } |
| 5772 | case Mips::APPEND_MMR2: |
| 5773 | case Mips::PRECR_SRA_PH_W_MMR2: |
| 5774 | case Mips::PRECR_SRA_R_PH_W_MMR2: |
| 5775 | case Mips::PREPEND_MMR2: |
| 5776 | case Mips::SHLL_S_W_MM: |
| 5777 | case Mips::SHRA_R_W_MM: { |
| 5778 | // op: rt |
| 5779 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5780 | Value |= (op & 0x1f) << 21; |
| 5781 | // op: rs |
| 5782 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5783 | Value |= (op & 0x1f) << 16; |
| 5784 | // op: sa |
| 5785 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5786 | Value |= (op & 0x1f) << 11; |
| 5787 | break; |
| 5788 | } |
| 5789 | case Mips::SHLL_QB_MM: |
| 5790 | case Mips::SHRA_QB_MMR2: |
| 5791 | case Mips::SHRA_R_QB_MMR2: |
| 5792 | case Mips::SHRL_QB_MM: { |
| 5793 | // op: rt |
| 5794 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5795 | Value |= (op & 0x1f) << 21; |
| 5796 | // op: rs |
| 5797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5798 | Value |= (op & 0x1f) << 16; |
| 5799 | // op: sa |
| 5800 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5801 | Value |= (op & 0x7) << 13; |
| 5802 | break; |
| 5803 | } |
| 5804 | case Mips::SHLL_PH_MM: |
| 5805 | case Mips::SHLL_S_PH_MM: |
| 5806 | case Mips::SHRA_PH_MM: |
| 5807 | case Mips::SHRA_R_PH_MM: |
| 5808 | case Mips::SHRL_PH_MMR2: { |
| 5809 | // op: rt |
| 5810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5811 | Value |= (op & 0x1f) << 21; |
| 5812 | // op: rs |
| 5813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5814 | Value |= (op & 0x1f) << 16; |
| 5815 | // op: sa |
| 5816 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5817 | Value |= (op & 0xf) << 12; |
| 5818 | break; |
| 5819 | } |
| 5820 | case Mips::MFC0_MMR6: |
| 5821 | case Mips::MFGC0_MM: |
| 5822 | case Mips::MFHC0_MMR6: |
| 5823 | case Mips::MFHGC0_MM: |
| 5824 | case Mips::RDHWR_MMR6: { |
| 5825 | // op: rt |
| 5826 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5827 | Value |= (op & 0x1f) << 21; |
| 5828 | // op: rs |
| 5829 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5830 | Value |= (op & 0x1f) << 16; |
| 5831 | // op: sel |
| 5832 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5833 | Value |= (op & 0x7) << 11; |
| 5834 | break; |
| 5835 | } |
| 5836 | case Mips::INS_MMR6: { |
| 5837 | // op: rt |
| 5838 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5839 | Value |= (op & 0x1f) << 21; |
| 5840 | // op: rs |
| 5841 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5842 | Value |= (op & 0x1f) << 16; |
| 5843 | // op: size |
| 5844 | op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI); |
| 5845 | Value |= (op & 0x1f) << 11; |
| 5846 | // op: pos |
| 5847 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5848 | Value |= (op & 0x1f) << 6; |
| 5849 | break; |
| 5850 | } |
| 5851 | case Mips::EXT_MMR6: { |
| 5852 | // op: rt |
| 5853 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5854 | Value |= (op & 0x1f) << 21; |
| 5855 | // op: rs |
| 5856 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5857 | Value |= (op & 0x1f) << 16; |
| 5858 | // op: size |
| 5859 | op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI); |
| 5860 | Value |= (op & 0x1f) << 11; |
| 5861 | // op: pos |
| 5862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5863 | Value |= (op & 0x1f) << 6; |
| 5864 | break; |
| 5865 | } |
| 5866 | case Mips::INSV_MM: { |
| 5867 | // op: rt |
| 5868 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5869 | Value |= (op & 0x1f) << 21; |
| 5870 | // op: rs |
| 5871 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5872 | Value |= (op & 0x1f) << 16; |
| 5873 | break; |
| 5874 | } |
| 5875 | case Mips::EXTPDPV_MM: |
| 5876 | case Mips::EXTPV_MM: |
| 5877 | case Mips::EXTRV_RS_W_MM: |
| 5878 | case Mips::EXTRV_R_W_MM: |
| 5879 | case Mips::EXTRV_S_H_MM: |
| 5880 | case Mips::EXTRV_W_MM: { |
| 5881 | // op: rt |
| 5882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5883 | Value |= (op & 0x1f) << 21; |
| 5884 | // op: rs |
| 5885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5886 | Value |= (op & 0x1f) << 16; |
| 5887 | // op: ac |
| 5888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5889 | Value |= (op & 0x3) << 14; |
| 5890 | break; |
| 5891 | } |
| 5892 | case Mips::BGEZALC: |
| 5893 | case Mips::BGEZC: |
| 5894 | case Mips::BGEZC64: |
| 5895 | case Mips::BLTZALC: |
| 5896 | case Mips::BLTZC: |
| 5897 | case Mips::BLTZC64: { |
| 5898 | // op: rt |
| 5899 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5900 | Value |= (op & 0x1f) << 21; |
| 5901 | Value |= (op & 0x1f) << 16; |
| 5902 | // op: offset |
| 5903 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 5904 | Value |= (op & 0xffff); |
| 5905 | break; |
| 5906 | } |
| 5907 | case Mips::BGEZC_MMR6: |
| 5908 | case Mips::BLTZC_MMR6: { |
| 5909 | // op: rt |
| 5910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5911 | Value |= (op & 0x1f) << 21; |
| 5912 | Value |= (op & 0x1f) << 16; |
| 5913 | // op: offset |
| 5914 | op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 1, Fixups, STI); |
| 5915 | Value |= (op & 0xffff); |
| 5916 | break; |
| 5917 | } |
| 5918 | case Mips::BGEZALC_MMR6: |
| 5919 | case Mips::BLTZALC_MMR6: { |
| 5920 | // op: rt |
| 5921 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5922 | Value |= (op & 0x1f) << 21; |
| 5923 | Value |= (op & 0x1f) << 16; |
| 5924 | // op: offset |
| 5925 | op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI); |
| 5926 | Value |= (op & 0xffff); |
| 5927 | break; |
| 5928 | } |
| 5929 | case Mips::LWSP_MM: |
| 5930 | case Mips::SWSP_MM: |
| 5931 | case Mips::SWSP_MMR6: { |
| 5932 | // op: rt |
| 5933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5934 | Value |= (op & 0x1f) << 5; |
| 5935 | // op: offset |
| 5936 | op = getMemEncodingMMSPImm5Lsl2(MI, OpNo: 1, Fixups, STI); |
| 5937 | Value |= (op & 0x1f); |
| 5938 | break; |
| 5939 | } |
| 5940 | case Mips::NOT16_MM: { |
| 5941 | // op: rt |
| 5942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5943 | Value |= (op & 0x7) << 3; |
| 5944 | // op: rs |
| 5945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5946 | Value |= (op & 0x7); |
| 5947 | break; |
| 5948 | } |
| 5949 | case Mips::LBU16_MM: |
| 5950 | case Mips::SB16_MM: |
| 5951 | case Mips::SB16_MMR6: { |
| 5952 | // op: rt |
| 5953 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5954 | Value |= (op & 0x7) << 7; |
| 5955 | // op: addr |
| 5956 | op = getMemEncodingMMImm4(MI, OpNo: 1, Fixups, STI); |
| 5957 | Value |= (op & 0x7f); |
| 5958 | break; |
| 5959 | } |
| 5960 | case Mips::LHU16_MM: |
| 5961 | case Mips::SH16_MM: |
| 5962 | case Mips::SH16_MMR6: { |
| 5963 | // op: rt |
| 5964 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5965 | Value |= (op & 0x7) << 7; |
| 5966 | // op: addr |
| 5967 | op = getMemEncodingMMImm4Lsl1(MI, OpNo: 1, Fixups, STI); |
| 5968 | Value |= (op & 0x7f); |
| 5969 | break; |
| 5970 | } |
| 5971 | case Mips::LW16_MM: |
| 5972 | case Mips::SW16_MM: |
| 5973 | case Mips::SW16_MMR6: { |
| 5974 | // op: rt |
| 5975 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5976 | Value |= (op & 0x7) << 7; |
| 5977 | // op: addr |
| 5978 | op = getMemEncodingMMImm4Lsl2(MI, OpNo: 1, Fixups, STI); |
| 5979 | Value |= (op & 0x7f); |
| 5980 | break; |
| 5981 | } |
| 5982 | case Mips::LWGP_MM: { |
| 5983 | // op: rt |
| 5984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5985 | Value |= (op & 0x7) << 7; |
| 5986 | // op: offset |
| 5987 | op = getMemEncodingMMGPImm7Lsl2(MI, OpNo: 1, Fixups, STI); |
| 5988 | Value |= (op & 0x7f); |
| 5989 | break; |
| 5990 | } |
| 5991 | case Mips::NOT16_MMR6: { |
| 5992 | // op: rt |
| 5993 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5994 | Value |= (op & 0x7) << 7; |
| 5995 | // op: rs |
| 5996 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5997 | Value |= (op & 0x7) << 4; |
| 5998 | break; |
| 5999 | } |
| 6000 | case Mips::SC64_R6: |
| 6001 | case Mips::SCD_R6: |
| 6002 | case Mips::SC_R6: { |
| 6003 | // op: rt |
| 6004 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6005 | Value |= (op & 0x1f) << 16; |
| 6006 | // op: addr |
| 6007 | op = getMemEncoding(MI, OpNo: 2, Fixups, STI); |
| 6008 | Value |= (op & 0x1f0000) << 5; |
| 6009 | Value |= (op & 0x1ff) << 7; |
| 6010 | break; |
| 6011 | } |
| 6012 | case Mips::SC: |
| 6013 | case Mips::SC64: |
| 6014 | case Mips::SCD: { |
| 6015 | // op: rt |
| 6016 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6017 | Value |= (op & 0x1f) << 16; |
| 6018 | // op: addr |
| 6019 | op = getMemEncoding(MI, OpNo: 2, Fixups, STI); |
| 6020 | Value |= (op & 0x1f0000) << 5; |
| 6021 | Value |= (op & 0xffff); |
| 6022 | break; |
| 6023 | } |
| 6024 | case Mips::CTC1: |
| 6025 | case Mips::DMTC1: |
| 6026 | case Mips::MTC1: |
| 6027 | case Mips::MTC1_D64: { |
| 6028 | // op: rt |
| 6029 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6030 | Value |= (op & 0x1f) << 16; |
| 6031 | // op: fs |
| 6032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6033 | Value |= (op & 0x1f) << 11; |
| 6034 | break; |
| 6035 | } |
| 6036 | case Mips::DMTC0: |
| 6037 | case Mips::DMTC2: |
| 6038 | case Mips::DMTGC0: |
| 6039 | case Mips::MTC0: |
| 6040 | case Mips::MTC2: |
| 6041 | case Mips::MTGC0: |
| 6042 | case Mips::MTHGC0: { |
| 6043 | // op: rt |
| 6044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6045 | Value |= (op & 0x1f) << 16; |
| 6046 | // op: rd |
| 6047 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6048 | Value |= (op & 0x1f) << 11; |
| 6049 | // op: sel |
| 6050 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6051 | Value |= (op & 0x7); |
| 6052 | break; |
| 6053 | } |
| 6054 | case Mips::MFTR: |
| 6055 | case Mips::MTTR: { |
| 6056 | // op: rt |
| 6057 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6058 | Value |= (op & 0x1f) << 16; |
| 6059 | // op: rd |
| 6060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6061 | Value |= (op & 0x1f) << 11; |
| 6062 | // op: u |
| 6063 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6064 | Value |= (op & 0x1) << 5; |
| 6065 | // op: h |
| 6066 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6067 | Value |= (op & 0x1) << 4; |
| 6068 | // op: sel |
| 6069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6070 | Value |= (op & 0x7); |
| 6071 | break; |
| 6072 | } |
| 6073 | case Mips::SCE_MM: { |
| 6074 | // op: rt |
| 6075 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6076 | Value |= (op & 0x1f) << 21; |
| 6077 | // op: addr |
| 6078 | op = getMemEncoding(MI, OpNo: 2, Fixups, STI); |
| 6079 | Value |= (op & 0x1f0000); |
| 6080 | Value |= (op & 0x1ff); |
| 6081 | break; |
| 6082 | } |
| 6083 | case Mips::SC_MM: { |
| 6084 | // op: rt |
| 6085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6086 | Value |= (op & 0x1f) << 21; |
| 6087 | // op: addr |
| 6088 | op = getMemEncodingMMImm12(MI, OpNo: 2, Fixups, STI); |
| 6089 | Value |= (op & 0x1f0000); |
| 6090 | Value |= (op & 0xfff); |
| 6091 | break; |
| 6092 | } |
| 6093 | case Mips::SC_MMR6: { |
| 6094 | // op: rt |
| 6095 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6096 | Value |= (op & 0x1f) << 21; |
| 6097 | // op: addr |
| 6098 | op = getMemEncodingMMImm9(MI, OpNo: 2, Fixups, STI); |
| 6099 | Value |= (op & 0x1f0000); |
| 6100 | Value |= (op & 0x1ff); |
| 6101 | break; |
| 6102 | } |
| 6103 | case Mips::CTC1_MM: |
| 6104 | case Mips::MTC1_D64_MM: |
| 6105 | case Mips::MTC1_MM: |
| 6106 | case Mips::MTC1_MMR6: { |
| 6107 | // op: rt |
| 6108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6109 | Value |= (op & 0x1f) << 21; |
| 6110 | // op: fs |
| 6111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6112 | Value |= (op & 0x1f) << 16; |
| 6113 | break; |
| 6114 | } |
| 6115 | case Mips::CTC2_MM: |
| 6116 | case Mips::MTC2_MMR6: |
| 6117 | case Mips::MTHC2_MMR6: { |
| 6118 | // op: rt |
| 6119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6120 | Value |= (op & 0x1f) << 21; |
| 6121 | // op: impl |
| 6122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6123 | Value |= (op & 0x1f) << 16; |
| 6124 | break; |
| 6125 | } |
| 6126 | case Mips::MTC0_MM: { |
| 6127 | // op: rt |
| 6128 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6129 | Value |= (op & 0x1f) << 21; |
| 6130 | // op: rd |
| 6131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6132 | Value |= (op & 0x1f) << 16; |
| 6133 | // op: sel |
| 6134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6135 | Value |= (op & 0x7) << 11; |
| 6136 | break; |
| 6137 | } |
| 6138 | case Mips::CMPU_EQ_QB_MM: |
| 6139 | case Mips::CMPU_LE_QB_MM: |
| 6140 | case Mips::CMPU_LT_QB_MM: |
| 6141 | case Mips::CMP_EQ_PH_MM: |
| 6142 | case Mips::CMP_LE_PH_MM: |
| 6143 | case Mips::CMP_LT_PH_MM: { |
| 6144 | // op: rt |
| 6145 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6146 | Value |= (op & 0x1f) << 21; |
| 6147 | // op: rs |
| 6148 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6149 | Value |= (op & 0x1f) << 16; |
| 6150 | break; |
| 6151 | } |
| 6152 | case Mips::BEQC_MMR6: |
| 6153 | case Mips::BGEC_MMR6: |
| 6154 | case Mips::BGEUC_MMR6: |
| 6155 | case Mips::BLTC_MMR6: |
| 6156 | case Mips::BLTUC_MMR6: |
| 6157 | case Mips::BNEC_MMR6: { |
| 6158 | // op: rt |
| 6159 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6160 | Value |= (op & 0x1f) << 21; |
| 6161 | // op: rs |
| 6162 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6163 | Value |= (op & 0x1f) << 16; |
| 6164 | // op: offset |
| 6165 | op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 2, Fixups, STI); |
| 6166 | Value |= (op & 0xffff); |
| 6167 | break; |
| 6168 | } |
| 6169 | case Mips::MTC0_MMR6: |
| 6170 | case Mips::MTGC0_MM: |
| 6171 | case Mips::MTHC0_MMR6: |
| 6172 | case Mips::MTHGC0_MM: { |
| 6173 | // op: rt |
| 6174 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6175 | Value |= (op & 0x1f) << 21; |
| 6176 | // op: rs |
| 6177 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6178 | Value |= (op & 0x1f) << 16; |
| 6179 | // op: sel |
| 6180 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6181 | Value |= (op & 0x7) << 11; |
| 6182 | break; |
| 6183 | } |
| 6184 | case Mips::MTHC1_D32: |
| 6185 | case Mips::MTHC1_D64: { |
| 6186 | // op: rt |
| 6187 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6188 | Value |= (op & 0x1f) << 16; |
| 6189 | // op: fs |
| 6190 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6191 | Value |= (op & 0x1f) << 11; |
| 6192 | break; |
| 6193 | } |
| 6194 | case Mips::SPLAT_B: |
| 6195 | case Mips::SPLAT_D: |
| 6196 | case Mips::SPLAT_H: |
| 6197 | case Mips::SPLAT_W: { |
| 6198 | // op: rt |
| 6199 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6200 | Value |= (op & 0x1f) << 16; |
| 6201 | // op: ws |
| 6202 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6203 | Value |= (op & 0x1f) << 11; |
| 6204 | // op: wd |
| 6205 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6206 | Value |= (op & 0x1f) << 6; |
| 6207 | break; |
| 6208 | } |
| 6209 | case Mips::MTHC1_D32_MM: |
| 6210 | case Mips::MTHC1_D64_MM: { |
| 6211 | // op: rt |
| 6212 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6213 | Value |= (op & 0x1f) << 21; |
| 6214 | // op: fs |
| 6215 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6216 | Value |= (op & 0x1f) << 16; |
| 6217 | break; |
| 6218 | } |
| 6219 | case Mips::DPAQX_SA_W_PH_MMR2: |
| 6220 | case Mips::DPAQX_S_W_PH_MMR2: |
| 6221 | case Mips::DPAQ_SA_L_W_MM: |
| 6222 | case Mips::DPAQ_S_W_PH_MM: |
| 6223 | case Mips::DPAU_H_QBL_MM: |
| 6224 | case Mips::DPAU_H_QBR_MM: |
| 6225 | case Mips::DPAX_W_PH_MMR2: |
| 6226 | case Mips::DPA_W_PH_MMR2: |
| 6227 | case Mips::DPSQX_SA_W_PH_MMR2: |
| 6228 | case Mips::DPSQX_S_W_PH_MMR2: |
| 6229 | case Mips::DPSQ_SA_L_W_MM: |
| 6230 | case Mips::DPSQ_S_W_PH_MM: |
| 6231 | case Mips::DPSU_H_QBL_MM: |
| 6232 | case Mips::DPSU_H_QBR_MM: |
| 6233 | case Mips::DPSX_W_PH_MMR2: |
| 6234 | case Mips::DPS_W_PH_MMR2: |
| 6235 | case Mips::MADDU_DSP_MM: |
| 6236 | case Mips::MADD_DSP_MM: |
| 6237 | case Mips::MAQ_SA_W_PHL_MM: |
| 6238 | case Mips::MAQ_SA_W_PHR_MM: |
| 6239 | case Mips::MAQ_S_W_PHL_MM: |
| 6240 | case Mips::MAQ_S_W_PHR_MM: |
| 6241 | case Mips::MSUBU_DSP_MM: |
| 6242 | case Mips::MSUB_DSP_MM: |
| 6243 | case Mips::MULSAQ_S_W_PH_MM: |
| 6244 | case Mips::MULSA_W_PH_MMR2: |
| 6245 | case Mips::MULTU_DSP_MM: |
| 6246 | case Mips::MULT_DSP_MM: { |
| 6247 | // op: rt |
| 6248 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6249 | Value |= (op & 0x1f) << 21; |
| 6250 | // op: rs |
| 6251 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6252 | Value |= (op & 0x1f) << 16; |
| 6253 | // op: ac |
| 6254 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6255 | Value |= (op & 0x3) << 14; |
| 6256 | break; |
| 6257 | } |
| 6258 | case Mips::ADD_MM: |
| 6259 | case Mips::ADDu_MM: |
| 6260 | case Mips::AND_MM: |
| 6261 | case Mips::CMPGU_EQ_QB_MM: |
| 6262 | case Mips::CMPGU_LE_QB_MM: |
| 6263 | case Mips::CMPGU_LT_QB_MM: |
| 6264 | case Mips::MOVN_I_MM: |
| 6265 | case Mips::MOVZ_I_MM: |
| 6266 | case Mips::MUL_MM: |
| 6267 | case Mips::NOR_MM: |
| 6268 | case Mips::OR_MM: |
| 6269 | case Mips::SLT_MM: |
| 6270 | case Mips::SLTu_MM: |
| 6271 | case Mips::SUB_MM: |
| 6272 | case Mips::SUBu_MM: |
| 6273 | case Mips::XOR_MM: { |
| 6274 | // op: rt |
| 6275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6276 | Value |= (op & 0x1f) << 21; |
| 6277 | // op: rs |
| 6278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6279 | Value |= (op & 0x1f) << 16; |
| 6280 | // op: rd |
| 6281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6282 | Value |= (op & 0x1f) << 11; |
| 6283 | break; |
| 6284 | } |
| 6285 | case Mips::AND16_MM: |
| 6286 | case Mips::OR16_MM: |
| 6287 | case Mips::XOR16_MM: { |
| 6288 | // op: rt |
| 6289 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6290 | Value |= (op & 0x7) << 3; |
| 6291 | // op: rs |
| 6292 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6293 | Value |= (op & 0x7); |
| 6294 | break; |
| 6295 | } |
| 6296 | case Mips::AND16_MMR6: |
| 6297 | case Mips::OR16_MMR6: |
| 6298 | case Mips::XOR16_MMR6: { |
| 6299 | // op: rt |
| 6300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6301 | Value |= (op & 0x7) << 7; |
| 6302 | // op: rs |
| 6303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6304 | Value |= (op & 0x7) << 4; |
| 6305 | break; |
| 6306 | } |
| 6307 | case Mips::SLD_B: |
| 6308 | case Mips::SLD_D: |
| 6309 | case Mips::SLD_H: |
| 6310 | case Mips::SLD_W: { |
| 6311 | // op: rt |
| 6312 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6313 | Value |= (op & 0x1f) << 16; |
| 6314 | // op: ws |
| 6315 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6316 | Value |= (op & 0x1f) << 11; |
| 6317 | // op: wd |
| 6318 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6319 | Value |= (op & 0x1f) << 6; |
| 6320 | break; |
| 6321 | } |
| 6322 | case Mips::MOVEP_MMR6: { |
| 6323 | // op: rt |
| 6324 | op = getMovePRegSingleOpValue(MI, OpNo: 3, Fixups, STI); |
| 6325 | Value |= (op & 0x7) << 4; |
| 6326 | // op: rs |
| 6327 | op = getMovePRegSingleOpValue(MI, OpNo: 2, Fixups, STI); |
| 6328 | Value |= (op & 0x4) << 1; |
| 6329 | Value |= (op & 0x3); |
| 6330 | break; |
| 6331 | } |
| 6332 | case Mips::MOVEP_MM: { |
| 6333 | // op: rt |
| 6334 | op = getMovePRegSingleOpValue(MI, OpNo: 3, Fixups, STI); |
| 6335 | Value |= (op & 0x7) << 4; |
| 6336 | // op: rs |
| 6337 | op = getMovePRegSingleOpValue(MI, OpNo: 2, Fixups, STI); |
| 6338 | Value |= (op & 0x7) << 1; |
| 6339 | break; |
| 6340 | } |
| 6341 | case Mips::LWM32_MM: |
| 6342 | case Mips::SWM32_MM: { |
| 6343 | // op: rt |
| 6344 | op = getRegisterListOpValue(MI, OpNo: 0, Fixups, STI); |
| 6345 | Value |= (op & 0x1f) << 21; |
| 6346 | // op: addr |
| 6347 | op = getMemEncodingMMImm12(MI, OpNo: 1, Fixups, STI); |
| 6348 | Value |= (op & 0x1f0000); |
| 6349 | Value |= (op & 0xfff); |
| 6350 | break; |
| 6351 | } |
| 6352 | case Mips::LWM16_MM: |
| 6353 | case Mips::SWM16_MM: { |
| 6354 | // op: rt |
| 6355 | op = getRegisterListOpValue16(MI, OpNo: 0, Fixups, STI); |
| 6356 | Value |= (op & 0x3) << 4; |
| 6357 | // op: addr |
| 6358 | op = getMemEncodingMMImm4sp(MI, OpNo: 1, Fixups, STI); |
| 6359 | Value |= (op & 0xf); |
| 6360 | break; |
| 6361 | } |
| 6362 | case Mips::LWM16_MMR6: |
| 6363 | case Mips::SWM16_MMR6: { |
| 6364 | // op: rt |
| 6365 | op = getRegisterListOpValue16(MI, OpNo: 0, Fixups, STI); |
| 6366 | Value |= (op & 0x3) << 8; |
| 6367 | // op: addr |
| 6368 | op = getMemEncodingMMImm4sp(MI, OpNo: 1, Fixups, STI); |
| 6369 | Value |= (op & 0xf) << 4; |
| 6370 | break; |
| 6371 | } |
| 6372 | case Mips::JrcRx16: |
| 6373 | case Mips::JumpLinkReg16: |
| 6374 | case Mips::Mfhi16: |
| 6375 | case Mips::Mflo16: |
| 6376 | case Mips::SebRx16: |
| 6377 | case Mips::SehRx16: { |
| 6378 | // op: rx |
| 6379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6380 | Value |= (op & 0x7) << 8; |
| 6381 | break; |
| 6382 | } |
| 6383 | case Mips::BeqzRxImm16: |
| 6384 | case Mips::BnezRxImm16: { |
| 6385 | // op: rx |
| 6386 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6387 | Value |= (op & 0x7) << 8; |
| 6388 | // op: imm8 |
| 6389 | op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI); |
| 6390 | Value |= (op & 0xff); |
| 6391 | break; |
| 6392 | } |
| 6393 | case Mips::CmpiRxImm16: |
| 6394 | case Mips::LiRxImm16: |
| 6395 | case Mips::LwRxPcTcp16: |
| 6396 | case Mips::SltiRxImm16: |
| 6397 | case Mips::SltiuRxImm16: { |
| 6398 | // op: rx |
| 6399 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6400 | Value |= (op & 0x7) << 8; |
| 6401 | // op: imm8 |
| 6402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6403 | Value |= (op & 0xff); |
| 6404 | break; |
| 6405 | } |
| 6406 | case Mips::AddiuRxRxImm16: { |
| 6407 | // op: rx |
| 6408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6409 | Value |= (op & 0x7) << 8; |
| 6410 | // op: imm8 |
| 6411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6412 | Value |= (op & 0xff); |
| 6413 | break; |
| 6414 | } |
| 6415 | case Mips::CmpRxRy16: |
| 6416 | case Mips::DivRxRy16: |
| 6417 | case Mips::DivuRxRy16: |
| 6418 | case Mips::NegRxRy16: |
| 6419 | case Mips::NotRxRy16: |
| 6420 | case Mips::SltRxRy16: |
| 6421 | case Mips::SltuRxRy16: { |
| 6422 | // op: rx |
| 6423 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6424 | Value |= (op & 0x7) << 8; |
| 6425 | // op: ry |
| 6426 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6427 | Value |= (op & 0x7) << 5; |
| 6428 | break; |
| 6429 | } |
| 6430 | case Mips::AndRxRxRy16: |
| 6431 | case Mips::OrRxRxRy16: |
| 6432 | case Mips::SllvRxRy16: |
| 6433 | case Mips::SravRxRy16: |
| 6434 | case Mips::SrlvRxRy16: |
| 6435 | case Mips::XorRxRxRy16: { |
| 6436 | // op: rx |
| 6437 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6438 | Value |= (op & 0x7) << 8; |
| 6439 | // op: ry |
| 6440 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6441 | Value |= (op & 0x7) << 5; |
| 6442 | break; |
| 6443 | } |
| 6444 | case Mips::AdduRxRyRz16: |
| 6445 | case Mips::SubuRxRyRz16: { |
| 6446 | // op: rx |
| 6447 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6448 | Value |= (op & 0x7) << 8; |
| 6449 | // op: ry |
| 6450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6451 | Value |= (op & 0x7) << 5; |
| 6452 | // op: rz |
| 6453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6454 | Value |= (op & 0x7) << 2; |
| 6455 | break; |
| 6456 | } |
| 6457 | case Mips::MoveR3216: { |
| 6458 | // op: ry |
| 6459 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6460 | Value |= (op & 0xf) << 4; |
| 6461 | // op: r32 |
| 6462 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6463 | Value |= (op & 0xf); |
| 6464 | break; |
| 6465 | } |
| 6466 | case Mips::LDI_B: |
| 6467 | case Mips::LDI_D: |
| 6468 | case Mips::LDI_H: |
| 6469 | case Mips::LDI_W: { |
| 6470 | // op: s10 |
| 6471 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6472 | Value |= (op & 0x3ff) << 11; |
| 6473 | // op: wd |
| 6474 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6475 | Value |= (op & 0x1f) << 6; |
| 6476 | break; |
| 6477 | } |
| 6478 | case Mips::SllX16: |
| 6479 | case Mips::SraX16: |
| 6480 | case Mips::SrlX16: { |
| 6481 | // op: sa6 |
| 6482 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6483 | Value |= (op & 0x1f) << 22; |
| 6484 | Value |= (op & 0x20) << 16; |
| 6485 | // op: rx |
| 6486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6487 | Value |= (op & 0x7) << 8; |
| 6488 | // op: ry |
| 6489 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6490 | Value |= (op & 0x7) << 5; |
| 6491 | break; |
| 6492 | } |
| 6493 | case Mips::SHILO_MM: { |
| 6494 | // op: shift |
| 6495 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6496 | Value |= (op & 0x3f) << 16; |
| 6497 | // op: ac |
| 6498 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6499 | Value |= (op & 0x3) << 14; |
| 6500 | break; |
| 6501 | } |
| 6502 | case Mips::SYNC_MM: |
| 6503 | case Mips::SYNC_MMR6: { |
| 6504 | // op: stype |
| 6505 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6506 | Value |= (op & 0x1f) << 16; |
| 6507 | break; |
| 6508 | } |
| 6509 | case Mips::SYNC: { |
| 6510 | // op: stype |
| 6511 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6512 | Value |= (op & 0x1f) << 6; |
| 6513 | break; |
| 6514 | } |
| 6515 | case Mips::J: |
| 6516 | case Mips::JAL: |
| 6517 | case Mips::JALX: |
| 6518 | case Mips::JALX_MM: { |
| 6519 | // op: target |
| 6520 | op = getJumpTargetOpValue(MI, OpNo: 0, Fixups, STI); |
| 6521 | Value |= (op & 0x3ffffff); |
| 6522 | break; |
| 6523 | } |
| 6524 | case Mips::JALS_MM: |
| 6525 | case Mips::JAL_MM: |
| 6526 | case Mips::J_MM: { |
| 6527 | // op: target |
| 6528 | op = getJumpTargetOpValueMM(MI, OpNo: 0, Fixups, STI); |
| 6529 | Value |= (op & 0x3ffffff); |
| 6530 | break; |
| 6531 | } |
| 6532 | case Mips::ANDI_B: |
| 6533 | case Mips::NORI_B: |
| 6534 | case Mips::ORI_B: |
| 6535 | case Mips::SHF_B: |
| 6536 | case Mips::SHF_H: |
| 6537 | case Mips::SHF_W: |
| 6538 | case Mips::XORI_B: { |
| 6539 | // op: u8 |
| 6540 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6541 | Value |= (op & 0xff) << 16; |
| 6542 | // op: ws |
| 6543 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6544 | Value |= (op & 0x1f) << 11; |
| 6545 | // op: wd |
| 6546 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6547 | Value |= (op & 0x1f) << 6; |
| 6548 | break; |
| 6549 | } |
| 6550 | case Mips::BMNZI_B: |
| 6551 | case Mips::BMZI_B: |
| 6552 | case Mips::BSELI_B: { |
| 6553 | // op: u8 |
| 6554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6555 | Value |= (op & 0xff) << 16; |
| 6556 | // op: ws |
| 6557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6558 | Value |= (op & 0x1f) << 11; |
| 6559 | // op: wd |
| 6560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6561 | Value |= (op & 0x1f) << 6; |
| 6562 | break; |
| 6563 | } |
| 6564 | case Mips::FCLASS_D: |
| 6565 | case Mips::FCLASS_W: |
| 6566 | case Mips::FEXUPL_D: |
| 6567 | case Mips::FEXUPL_W: |
| 6568 | case Mips::FEXUPR_D: |
| 6569 | case Mips::FEXUPR_W: |
| 6570 | case Mips::FFINT_S_D: |
| 6571 | case Mips::FFINT_S_W: |
| 6572 | case Mips::FFINT_U_D: |
| 6573 | case Mips::FFINT_U_W: |
| 6574 | case Mips::FFQL_D: |
| 6575 | case Mips::FFQL_W: |
| 6576 | case Mips::FFQR_D: |
| 6577 | case Mips::FFQR_W: |
| 6578 | case Mips::FLOG2_D: |
| 6579 | case Mips::FLOG2_W: |
| 6580 | case Mips::FRCP_D: |
| 6581 | case Mips::FRCP_W: |
| 6582 | case Mips::FRINT_D: |
| 6583 | case Mips::FRINT_W: |
| 6584 | case Mips::FRSQRT_D: |
| 6585 | case Mips::FRSQRT_W: |
| 6586 | case Mips::FSQRT_D: |
| 6587 | case Mips::FSQRT_W: |
| 6588 | case Mips::FTINT_S_D: |
| 6589 | case Mips::FTINT_S_W: |
| 6590 | case Mips::FTINT_U_D: |
| 6591 | case Mips::FTINT_U_W: |
| 6592 | case Mips::FTRUNC_S_D: |
| 6593 | case Mips::FTRUNC_S_W: |
| 6594 | case Mips::FTRUNC_U_D: |
| 6595 | case Mips::FTRUNC_U_W: |
| 6596 | case Mips::MOVE_V: |
| 6597 | case Mips::NLOC_B: |
| 6598 | case Mips::NLOC_D: |
| 6599 | case Mips::NLOC_H: |
| 6600 | case Mips::NLOC_W: |
| 6601 | case Mips::NLZC_B: |
| 6602 | case Mips::NLZC_D: |
| 6603 | case Mips::NLZC_H: |
| 6604 | case Mips::NLZC_W: |
| 6605 | case Mips::PCNT_B: |
| 6606 | case Mips::PCNT_D: |
| 6607 | case Mips::PCNT_H: |
| 6608 | case Mips::PCNT_W: { |
| 6609 | // op: ws |
| 6610 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6611 | Value |= (op & 0x1f) << 11; |
| 6612 | // op: wd |
| 6613 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6614 | Value |= (op & 0x1f) << 6; |
| 6615 | break; |
| 6616 | } |
| 6617 | case Mips::BCLRI_W: |
| 6618 | case Mips::BNEGI_W: |
| 6619 | case Mips::BSETI_W: |
| 6620 | case Mips::SAT_S_W: |
| 6621 | case Mips::SAT_U_W: |
| 6622 | case Mips::SLLI_W: |
| 6623 | case Mips::SRAI_W: |
| 6624 | case Mips::SRARI_W: |
| 6625 | case Mips::SRLI_W: |
| 6626 | case Mips::SRLRI_W: { |
| 6627 | // op: ws |
| 6628 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6629 | Value |= (op & 0x1f) << 11; |
| 6630 | // op: wd |
| 6631 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6632 | Value |= (op & 0x1f) << 6; |
| 6633 | // op: m |
| 6634 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6635 | Value |= (op & 0x1f) << 16; |
| 6636 | break; |
| 6637 | } |
| 6638 | case Mips::BCLRI_D: |
| 6639 | case Mips::BNEGI_D: |
| 6640 | case Mips::BSETI_D: |
| 6641 | case Mips::SAT_S_D: |
| 6642 | case Mips::SAT_U_D: |
| 6643 | case Mips::SLLI_D: |
| 6644 | case Mips::SRAI_D: |
| 6645 | case Mips::SRARI_D: |
| 6646 | case Mips::SRLI_D: |
| 6647 | case Mips::SRLRI_D: { |
| 6648 | // op: ws |
| 6649 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6650 | Value |= (op & 0x1f) << 11; |
| 6651 | // op: wd |
| 6652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6653 | Value |= (op & 0x1f) << 6; |
| 6654 | // op: m |
| 6655 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6656 | Value |= (op & 0x3f) << 16; |
| 6657 | break; |
| 6658 | } |
| 6659 | case Mips::BCLRI_B: |
| 6660 | case Mips::BNEGI_B: |
| 6661 | case Mips::BSETI_B: |
| 6662 | case Mips::SAT_S_B: |
| 6663 | case Mips::SAT_U_B: |
| 6664 | case Mips::SLLI_B: |
| 6665 | case Mips::SRAI_B: |
| 6666 | case Mips::SRARI_B: |
| 6667 | case Mips::SRLI_B: |
| 6668 | case Mips::SRLRI_B: { |
| 6669 | // op: ws |
| 6670 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6671 | Value |= (op & 0x1f) << 11; |
| 6672 | // op: wd |
| 6673 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6674 | Value |= (op & 0x1f) << 6; |
| 6675 | // op: m |
| 6676 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6677 | Value |= (op & 0x7) << 16; |
| 6678 | break; |
| 6679 | } |
| 6680 | case Mips::BCLRI_H: |
| 6681 | case Mips::BNEGI_H: |
| 6682 | case Mips::BSETI_H: |
| 6683 | case Mips::SAT_S_H: |
| 6684 | case Mips::SAT_U_H: |
| 6685 | case Mips::SLLI_H: |
| 6686 | case Mips::SRAI_H: |
| 6687 | case Mips::SRARI_H: |
| 6688 | case Mips::SRLI_H: |
| 6689 | case Mips::SRLRI_H: { |
| 6690 | // op: ws |
| 6691 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6692 | Value |= (op & 0x1f) << 11; |
| 6693 | // op: wd |
| 6694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6695 | Value |= (op & 0x1f) << 6; |
| 6696 | // op: m |
| 6697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6698 | Value |= (op & 0xf) << 16; |
| 6699 | break; |
| 6700 | } |
| 6701 | case Mips::BINSLI_W: |
| 6702 | case Mips::BINSRI_W: { |
| 6703 | // op: ws |
| 6704 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6705 | Value |= (op & 0x1f) << 11; |
| 6706 | // op: wd |
| 6707 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6708 | Value |= (op & 0x1f) << 6; |
| 6709 | // op: m |
| 6710 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6711 | Value |= (op & 0x1f) << 16; |
| 6712 | break; |
| 6713 | } |
| 6714 | case Mips::BINSLI_D: |
| 6715 | case Mips::BINSRI_D: { |
| 6716 | // op: ws |
| 6717 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6718 | Value |= (op & 0x1f) << 11; |
| 6719 | // op: wd |
| 6720 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6721 | Value |= (op & 0x1f) << 6; |
| 6722 | // op: m |
| 6723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6724 | Value |= (op & 0x3f) << 16; |
| 6725 | break; |
| 6726 | } |
| 6727 | case Mips::BINSLI_B: |
| 6728 | case Mips::BINSRI_B: { |
| 6729 | // op: ws |
| 6730 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6731 | Value |= (op & 0x1f) << 11; |
| 6732 | // op: wd |
| 6733 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6734 | Value |= (op & 0x1f) << 6; |
| 6735 | // op: m |
| 6736 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6737 | Value |= (op & 0x7) << 16; |
| 6738 | break; |
| 6739 | } |
| 6740 | case Mips::BINSLI_H: |
| 6741 | case Mips::BINSRI_H: { |
| 6742 | // op: ws |
| 6743 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6744 | Value |= (op & 0x1f) << 11; |
| 6745 | // op: wd |
| 6746 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6747 | Value |= (op & 0x1f) << 6; |
| 6748 | // op: m |
| 6749 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6750 | Value |= (op & 0xf) << 16; |
| 6751 | break; |
| 6752 | } |
| 6753 | case Mips::ADDS_A_B: |
| 6754 | case Mips::ADDS_A_D: |
| 6755 | case Mips::ADDS_A_H: |
| 6756 | case Mips::ADDS_A_W: |
| 6757 | case Mips::ADDS_S_B: |
| 6758 | case Mips::ADDS_S_D: |
| 6759 | case Mips::ADDS_S_H: |
| 6760 | case Mips::ADDS_S_W: |
| 6761 | case Mips::ADDS_U_B: |
| 6762 | case Mips::ADDS_U_D: |
| 6763 | case Mips::ADDS_U_H: |
| 6764 | case Mips::ADDS_U_W: |
| 6765 | case Mips::ADDV_B: |
| 6766 | case Mips::ADDV_D: |
| 6767 | case Mips::ADDV_H: |
| 6768 | case Mips::ADDV_W: |
| 6769 | case Mips::ADD_A_B: |
| 6770 | case Mips::ADD_A_D: |
| 6771 | case Mips::ADD_A_H: |
| 6772 | case Mips::ADD_A_W: |
| 6773 | case Mips::AND_V: |
| 6774 | case Mips::ASUB_S_B: |
| 6775 | case Mips::ASUB_S_D: |
| 6776 | case Mips::ASUB_S_H: |
| 6777 | case Mips::ASUB_S_W: |
| 6778 | case Mips::ASUB_U_B: |
| 6779 | case Mips::ASUB_U_D: |
| 6780 | case Mips::ASUB_U_H: |
| 6781 | case Mips::ASUB_U_W: |
| 6782 | case Mips::AVER_S_B: |
| 6783 | case Mips::AVER_S_D: |
| 6784 | case Mips::AVER_S_H: |
| 6785 | case Mips::AVER_S_W: |
| 6786 | case Mips::AVER_U_B: |
| 6787 | case Mips::AVER_U_D: |
| 6788 | case Mips::AVER_U_H: |
| 6789 | case Mips::AVER_U_W: |
| 6790 | case Mips::AVE_S_B: |
| 6791 | case Mips::AVE_S_D: |
| 6792 | case Mips::AVE_S_H: |
| 6793 | case Mips::AVE_S_W: |
| 6794 | case Mips::AVE_U_B: |
| 6795 | case Mips::AVE_U_D: |
| 6796 | case Mips::AVE_U_H: |
| 6797 | case Mips::AVE_U_W: |
| 6798 | case Mips::BCLR_B: |
| 6799 | case Mips::BCLR_D: |
| 6800 | case Mips::BCLR_H: |
| 6801 | case Mips::BCLR_W: |
| 6802 | case Mips::BNEG_B: |
| 6803 | case Mips::BNEG_D: |
| 6804 | case Mips::BNEG_H: |
| 6805 | case Mips::BNEG_W: |
| 6806 | case Mips::BSET_B: |
| 6807 | case Mips::BSET_D: |
| 6808 | case Mips::BSET_H: |
| 6809 | case Mips::BSET_W: |
| 6810 | case Mips::CEQ_B: |
| 6811 | case Mips::CEQ_D: |
| 6812 | case Mips::CEQ_H: |
| 6813 | case Mips::CEQ_W: |
| 6814 | case Mips::CLE_S_B: |
| 6815 | case Mips::CLE_S_D: |
| 6816 | case Mips::CLE_S_H: |
| 6817 | case Mips::CLE_S_W: |
| 6818 | case Mips::CLE_U_B: |
| 6819 | case Mips::CLE_U_D: |
| 6820 | case Mips::CLE_U_H: |
| 6821 | case Mips::CLE_U_W: |
| 6822 | case Mips::CLT_S_B: |
| 6823 | case Mips::CLT_S_D: |
| 6824 | case Mips::CLT_S_H: |
| 6825 | case Mips::CLT_S_W: |
| 6826 | case Mips::CLT_U_B: |
| 6827 | case Mips::CLT_U_D: |
| 6828 | case Mips::CLT_U_H: |
| 6829 | case Mips::CLT_U_W: |
| 6830 | case Mips::DIV_S_B: |
| 6831 | case Mips::DIV_S_D: |
| 6832 | case Mips::DIV_S_H: |
| 6833 | case Mips::DIV_S_W: |
| 6834 | case Mips::DIV_U_B: |
| 6835 | case Mips::DIV_U_D: |
| 6836 | case Mips::DIV_U_H: |
| 6837 | case Mips::DIV_U_W: |
| 6838 | case Mips::DOTP_S_D: |
| 6839 | case Mips::DOTP_S_H: |
| 6840 | case Mips::DOTP_S_W: |
| 6841 | case Mips::DOTP_U_D: |
| 6842 | case Mips::DOTP_U_H: |
| 6843 | case Mips::DOTP_U_W: |
| 6844 | case Mips::FADD_D: |
| 6845 | case Mips::FADD_W: |
| 6846 | case Mips::FCAF_D: |
| 6847 | case Mips::FCAF_W: |
| 6848 | case Mips::FCEQ_D: |
| 6849 | case Mips::FCEQ_W: |
| 6850 | case Mips::FCLE_D: |
| 6851 | case Mips::FCLE_W: |
| 6852 | case Mips::FCLT_D: |
| 6853 | case Mips::FCLT_W: |
| 6854 | case Mips::FCNE_D: |
| 6855 | case Mips::FCNE_W: |
| 6856 | case Mips::FCOR_D: |
| 6857 | case Mips::FCOR_W: |
| 6858 | case Mips::FCUEQ_D: |
| 6859 | case Mips::FCUEQ_W: |
| 6860 | case Mips::FCULE_D: |
| 6861 | case Mips::FCULE_W: |
| 6862 | case Mips::FCULT_D: |
| 6863 | case Mips::FCULT_W: |
| 6864 | case Mips::FCUNE_D: |
| 6865 | case Mips::FCUNE_W: |
| 6866 | case Mips::FCUN_D: |
| 6867 | case Mips::FCUN_W: |
| 6868 | case Mips::FDIV_D: |
| 6869 | case Mips::FDIV_W: |
| 6870 | case Mips::FEXDO_H: |
| 6871 | case Mips::FEXDO_W: |
| 6872 | case Mips::FEXP2_D: |
| 6873 | case Mips::FEXP2_W: |
| 6874 | case Mips::FMAX_A_D: |
| 6875 | case Mips::FMAX_A_W: |
| 6876 | case Mips::FMAX_D: |
| 6877 | case Mips::FMAX_W: |
| 6878 | case Mips::FMIN_A_D: |
| 6879 | case Mips::FMIN_A_W: |
| 6880 | case Mips::FMIN_D: |
| 6881 | case Mips::FMIN_W: |
| 6882 | case Mips::FMUL_D: |
| 6883 | case Mips::FMUL_W: |
| 6884 | case Mips::FSAF_D: |
| 6885 | case Mips::FSAF_W: |
| 6886 | case Mips::FSEQ_D: |
| 6887 | case Mips::FSEQ_W: |
| 6888 | case Mips::FSLE_D: |
| 6889 | case Mips::FSLE_W: |
| 6890 | case Mips::FSLT_D: |
| 6891 | case Mips::FSLT_W: |
| 6892 | case Mips::FSNE_D: |
| 6893 | case Mips::FSNE_W: |
| 6894 | case Mips::FSOR_D: |
| 6895 | case Mips::FSOR_W: |
| 6896 | case Mips::FSUB_D: |
| 6897 | case Mips::FSUB_W: |
| 6898 | case Mips::FSUEQ_D: |
| 6899 | case Mips::FSUEQ_W: |
| 6900 | case Mips::FSULE_D: |
| 6901 | case Mips::FSULE_W: |
| 6902 | case Mips::FSULT_D: |
| 6903 | case Mips::FSULT_W: |
| 6904 | case Mips::FSUNE_D: |
| 6905 | case Mips::FSUNE_W: |
| 6906 | case Mips::FSUN_D: |
| 6907 | case Mips::FSUN_W: |
| 6908 | case Mips::FTQ_H: |
| 6909 | case Mips::FTQ_W: |
| 6910 | case Mips::HADD_S_D: |
| 6911 | case Mips::HADD_S_H: |
| 6912 | case Mips::HADD_S_W: |
| 6913 | case Mips::HADD_U_D: |
| 6914 | case Mips::HADD_U_H: |
| 6915 | case Mips::HADD_U_W: |
| 6916 | case Mips::HSUB_S_D: |
| 6917 | case Mips::HSUB_S_H: |
| 6918 | case Mips::HSUB_S_W: |
| 6919 | case Mips::HSUB_U_D: |
| 6920 | case Mips::HSUB_U_H: |
| 6921 | case Mips::HSUB_U_W: |
| 6922 | case Mips::ILVEV_B: |
| 6923 | case Mips::ILVEV_D: |
| 6924 | case Mips::ILVEV_H: |
| 6925 | case Mips::ILVEV_W: |
| 6926 | case Mips::ILVL_B: |
| 6927 | case Mips::ILVL_D: |
| 6928 | case Mips::ILVL_H: |
| 6929 | case Mips::ILVL_W: |
| 6930 | case Mips::ILVOD_B: |
| 6931 | case Mips::ILVOD_D: |
| 6932 | case Mips::ILVOD_H: |
| 6933 | case Mips::ILVOD_W: |
| 6934 | case Mips::ILVR_B: |
| 6935 | case Mips::ILVR_D: |
| 6936 | case Mips::ILVR_H: |
| 6937 | case Mips::ILVR_W: |
| 6938 | case Mips::MAX_A_B: |
| 6939 | case Mips::MAX_A_D: |
| 6940 | case Mips::MAX_A_H: |
| 6941 | case Mips::MAX_A_W: |
| 6942 | case Mips::MAX_S_B: |
| 6943 | case Mips::MAX_S_D: |
| 6944 | case Mips::MAX_S_H: |
| 6945 | case Mips::MAX_S_W: |
| 6946 | case Mips::MAX_U_B: |
| 6947 | case Mips::MAX_U_D: |
| 6948 | case Mips::MAX_U_H: |
| 6949 | case Mips::MAX_U_W: |
| 6950 | case Mips::MIN_A_B: |
| 6951 | case Mips::MIN_A_D: |
| 6952 | case Mips::MIN_A_H: |
| 6953 | case Mips::MIN_A_W: |
| 6954 | case Mips::MIN_S_B: |
| 6955 | case Mips::MIN_S_D: |
| 6956 | case Mips::MIN_S_H: |
| 6957 | case Mips::MIN_S_W: |
| 6958 | case Mips::MIN_U_B: |
| 6959 | case Mips::MIN_U_D: |
| 6960 | case Mips::MIN_U_H: |
| 6961 | case Mips::MIN_U_W: |
| 6962 | case Mips::MOD_S_B: |
| 6963 | case Mips::MOD_S_D: |
| 6964 | case Mips::MOD_S_H: |
| 6965 | case Mips::MOD_S_W: |
| 6966 | case Mips::MOD_U_B: |
| 6967 | case Mips::MOD_U_D: |
| 6968 | case Mips::MOD_U_H: |
| 6969 | case Mips::MOD_U_W: |
| 6970 | case Mips::MULR_Q_H: |
| 6971 | case Mips::MULR_Q_W: |
| 6972 | case Mips::MULV_B: |
| 6973 | case Mips::MULV_D: |
| 6974 | case Mips::MULV_H: |
| 6975 | case Mips::MULV_W: |
| 6976 | case Mips::MUL_Q_H: |
| 6977 | case Mips::MUL_Q_W: |
| 6978 | case Mips::NOR_V: |
| 6979 | case Mips::OR_V: |
| 6980 | case Mips::PCKEV_B: |
| 6981 | case Mips::PCKEV_D: |
| 6982 | case Mips::PCKEV_H: |
| 6983 | case Mips::PCKEV_W: |
| 6984 | case Mips::PCKOD_B: |
| 6985 | case Mips::PCKOD_D: |
| 6986 | case Mips::PCKOD_H: |
| 6987 | case Mips::PCKOD_W: |
| 6988 | case Mips::SLL_B: |
| 6989 | case Mips::SLL_D: |
| 6990 | case Mips::SLL_H: |
| 6991 | case Mips::SLL_W: |
| 6992 | case Mips::SRAR_B: |
| 6993 | case Mips::SRAR_D: |
| 6994 | case Mips::SRAR_H: |
| 6995 | case Mips::SRAR_W: |
| 6996 | case Mips::SRA_B: |
| 6997 | case Mips::SRA_D: |
| 6998 | case Mips::SRA_H: |
| 6999 | case Mips::SRA_W: |
| 7000 | case Mips::SRLR_B: |
| 7001 | case Mips::SRLR_D: |
| 7002 | case Mips::SRLR_H: |
| 7003 | case Mips::SRLR_W: |
| 7004 | case Mips::SRL_B: |
| 7005 | case Mips::SRL_D: |
| 7006 | case Mips::SRL_H: |
| 7007 | case Mips::SRL_W: |
| 7008 | case Mips::SUBSUS_U_B: |
| 7009 | case Mips::SUBSUS_U_D: |
| 7010 | case Mips::SUBSUS_U_H: |
| 7011 | case Mips::SUBSUS_U_W: |
| 7012 | case Mips::SUBSUU_S_B: |
| 7013 | case Mips::SUBSUU_S_D: |
| 7014 | case Mips::SUBSUU_S_H: |
| 7015 | case Mips::SUBSUU_S_W: |
| 7016 | case Mips::SUBS_S_B: |
| 7017 | case Mips::SUBS_S_D: |
| 7018 | case Mips::SUBS_S_H: |
| 7019 | case Mips::SUBS_S_W: |
| 7020 | case Mips::SUBS_U_B: |
| 7021 | case Mips::SUBS_U_D: |
| 7022 | case Mips::SUBS_U_H: |
| 7023 | case Mips::SUBS_U_W: |
| 7024 | case Mips::SUBV_B: |
| 7025 | case Mips::SUBV_D: |
| 7026 | case Mips::SUBV_H: |
| 7027 | case Mips::SUBV_W: |
| 7028 | case Mips::XOR_V: { |
| 7029 | // op: wt |
| 7030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7031 | Value |= (op & 0x1f) << 16; |
| 7032 | // op: ws |
| 7033 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7034 | Value |= (op & 0x1f) << 11; |
| 7035 | // op: wd |
| 7036 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7037 | Value |= (op & 0x1f) << 6; |
| 7038 | break; |
| 7039 | } |
| 7040 | case Mips::BINSL_B: |
| 7041 | case Mips::BINSL_D: |
| 7042 | case Mips::BINSL_H: |
| 7043 | case Mips::BINSL_W: |
| 7044 | case Mips::BINSR_B: |
| 7045 | case Mips::BINSR_D: |
| 7046 | case Mips::BINSR_H: |
| 7047 | case Mips::BINSR_W: |
| 7048 | case Mips::BMNZ_V: |
| 7049 | case Mips::BMZ_V: |
| 7050 | case Mips::BSEL_V: |
| 7051 | case Mips::DPADD_S_D: |
| 7052 | case Mips::DPADD_S_H: |
| 7053 | case Mips::DPADD_S_W: |
| 7054 | case Mips::DPADD_U_D: |
| 7055 | case Mips::DPADD_U_H: |
| 7056 | case Mips::DPADD_U_W: |
| 7057 | case Mips::DPSUB_S_D: |
| 7058 | case Mips::DPSUB_S_H: |
| 7059 | case Mips::DPSUB_S_W: |
| 7060 | case Mips::DPSUB_U_D: |
| 7061 | case Mips::DPSUB_U_H: |
| 7062 | case Mips::DPSUB_U_W: |
| 7063 | case Mips::FMADD_D: |
| 7064 | case Mips::FMADD_W: |
| 7065 | case Mips::FMSUB_D: |
| 7066 | case Mips::FMSUB_W: |
| 7067 | case Mips::MADDR_Q_H: |
| 7068 | case Mips::MADDR_Q_W: |
| 7069 | case Mips::MADDV_B: |
| 7070 | case Mips::MADDV_D: |
| 7071 | case Mips::MADDV_H: |
| 7072 | case Mips::MADDV_W: |
| 7073 | case Mips::MADD_Q_H: |
| 7074 | case Mips::MADD_Q_W: |
| 7075 | case Mips::MSUBR_Q_H: |
| 7076 | case Mips::MSUBR_Q_W: |
| 7077 | case Mips::MSUBV_B: |
| 7078 | case Mips::MSUBV_D: |
| 7079 | case Mips::MSUBV_H: |
| 7080 | case Mips::MSUBV_W: |
| 7081 | case Mips::MSUB_Q_H: |
| 7082 | case Mips::MSUB_Q_W: |
| 7083 | case Mips::VSHF_B: |
| 7084 | case Mips::VSHF_D: |
| 7085 | case Mips::VSHF_H: |
| 7086 | case Mips::VSHF_W: { |
| 7087 | // op: wt |
| 7088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7089 | Value |= (op & 0x1f) << 16; |
| 7090 | // op: ws |
| 7091 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7092 | Value |= (op & 0x1f) << 11; |
| 7093 | // op: wd |
| 7094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7095 | Value |= (op & 0x1f) << 6; |
| 7096 | break; |
| 7097 | } |
| 7098 | default: |
| 7099 | reportUnsupportedInst(Inst: MI); |
| 7100 | } |
| 7101 | return Value; |
| 7102 | } |
| 7103 | |
| 7104 | #ifdef GET_OPERAND_BIT_OFFSET |
| 7105 | #undef GET_OPERAND_BIT_OFFSET |
| 7106 | |
| 7107 | uint32_t MipsMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
| 7108 | unsigned OpNum, |
| 7109 | const MCSubtargetInfo &STI) const { |
| 7110 | switch (MI.getOpcode()) { |
| 7111 | case Mips::Break16: |
| 7112 | case Mips::DERET: |
| 7113 | case Mips::DERET_MM: |
| 7114 | case Mips::DERET_MMR6: |
| 7115 | case Mips::EHB: |
| 7116 | case Mips::EHB_MM: |
| 7117 | case Mips::EHB_MMR6: |
| 7118 | case Mips::ERET: |
| 7119 | case Mips::ERETNC: |
| 7120 | case Mips::ERETNC_MMR6: |
| 7121 | case Mips::ERET_MM: |
| 7122 | case Mips::ERET_MMR6: |
| 7123 | case Mips::JrRa16: |
| 7124 | case Mips::JrcRa16: |
| 7125 | case Mips::NAL: |
| 7126 | case Mips::PAUSE: |
| 7127 | case Mips::PAUSE_MM: |
| 7128 | case Mips::PAUSE_MMR6: |
| 7129 | case Mips::Restore16: |
| 7130 | case Mips::RestoreX16: |
| 7131 | case Mips::SSNOP: |
| 7132 | case Mips::SSNOP_MM: |
| 7133 | case Mips::SSNOP_MMR6: |
| 7134 | case Mips::Save16: |
| 7135 | case Mips::SaveX16: |
| 7136 | case Mips::TLBGINV: |
| 7137 | case Mips::TLBGINVF: |
| 7138 | case Mips::TLBGINVF_MM: |
| 7139 | case Mips::TLBGINV_MM: |
| 7140 | case Mips::TLBGP: |
| 7141 | case Mips::TLBGP_MM: |
| 7142 | case Mips::TLBGR: |
| 7143 | case Mips::TLBGR_MM: |
| 7144 | case Mips::TLBGWI: |
| 7145 | case Mips::TLBGWI_MM: |
| 7146 | case Mips::TLBGWR: |
| 7147 | case Mips::TLBGWR_MM: |
| 7148 | case Mips::TLBINV: |
| 7149 | case Mips::TLBINVF: |
| 7150 | case Mips::TLBINVF_MMR6: |
| 7151 | case Mips::TLBINV_MMR6: |
| 7152 | case Mips::TLBP: |
| 7153 | case Mips::TLBP_MM: |
| 7154 | case Mips::TLBR: |
| 7155 | case Mips::TLBR_MM: |
| 7156 | case Mips::TLBWI: |
| 7157 | case Mips::TLBWI_MM: |
| 7158 | case Mips::TLBWR: |
| 7159 | case Mips::TLBWR_MM: |
| 7160 | case Mips::WAIT: { |
| 7161 | break; |
| 7162 | } |
| 7163 | case Mips::DPAQX_SA_W_PH: |
| 7164 | case Mips::DPAQX_S_W_PH: |
| 7165 | case Mips::DPAQ_SA_L_W: |
| 7166 | case Mips::DPAQ_S_W_PH: |
| 7167 | case Mips::DPAU_H_QBL: |
| 7168 | case Mips::DPAU_H_QBR: |
| 7169 | case Mips::DPAX_W_PH: |
| 7170 | case Mips::DPA_W_PH: |
| 7171 | case Mips::DPSQX_SA_W_PH: |
| 7172 | case Mips::DPSQX_S_W_PH: |
| 7173 | case Mips::DPSQ_SA_L_W: |
| 7174 | case Mips::DPSQ_S_W_PH: |
| 7175 | case Mips::DPSU_H_QBL: |
| 7176 | case Mips::DPSU_H_QBR: |
| 7177 | case Mips::DPSX_W_PH: |
| 7178 | case Mips::DPS_W_PH: |
| 7179 | case Mips::MADDU_DSP: |
| 7180 | case Mips::MADD_DSP: |
| 7181 | case Mips::MAQ_SA_W_PHL: |
| 7182 | case Mips::MAQ_SA_W_PHR: |
| 7183 | case Mips::MAQ_S_W_PHL: |
| 7184 | case Mips::MAQ_S_W_PHR: |
| 7185 | case Mips::MSUBU_DSP: |
| 7186 | case Mips::MSUB_DSP: |
| 7187 | case Mips::MULSAQ_S_W_PH: |
| 7188 | case Mips::MULSA_W_PH: |
| 7189 | case Mips::MULTU_DSP: |
| 7190 | case Mips::MULT_DSP: { |
| 7191 | switch (OpNum) { |
| 7192 | case 0: |
| 7193 | // op: ac |
| 7194 | return 11; |
| 7195 | case 1: |
| 7196 | // op: rs |
| 7197 | return 21; |
| 7198 | case 2: |
| 7199 | // op: rt |
| 7200 | return 16; |
| 7201 | } |
| 7202 | break; |
| 7203 | } |
| 7204 | case Mips::MTHLIP: |
| 7205 | case Mips::SHILOV: { |
| 7206 | switch (OpNum) { |
| 7207 | case 0: |
| 7208 | // op: ac |
| 7209 | return 11; |
| 7210 | case 1: |
| 7211 | // op: rs |
| 7212 | return 21; |
| 7213 | } |
| 7214 | break; |
| 7215 | } |
| 7216 | case Mips::SHILO: { |
| 7217 | switch (OpNum) { |
| 7218 | case 0: |
| 7219 | // op: ac |
| 7220 | return 11; |
| 7221 | case 1: |
| 7222 | // op: shift |
| 7223 | return 20; |
| 7224 | } |
| 7225 | break; |
| 7226 | } |
| 7227 | case Mips::CACHE: |
| 7228 | case Mips::PREF: { |
| 7229 | switch (OpNum) { |
| 7230 | case 0: |
| 7231 | // op: addr |
| 7232 | return 0; |
| 7233 | case 2: |
| 7234 | // op: hint |
| 7235 | return 16; |
| 7236 | } |
| 7237 | break; |
| 7238 | } |
| 7239 | case Mips::CACHEE_MM: |
| 7240 | case Mips::CACHE_MM: |
| 7241 | case Mips::CACHE_MMR6: |
| 7242 | case Mips::PREFE_MM: |
| 7243 | case Mips::PREF_MM: |
| 7244 | case Mips::PREF_MMR6: { |
| 7245 | switch (OpNum) { |
| 7246 | case 0: |
| 7247 | // op: addr |
| 7248 | return 0; |
| 7249 | case 2: |
| 7250 | // op: hint |
| 7251 | return 21; |
| 7252 | } |
| 7253 | break; |
| 7254 | } |
| 7255 | case Mips::SYNCI: |
| 7256 | case Mips::SYNCI_MM: |
| 7257 | case Mips::SYNCI_MMR6: { |
| 7258 | switch (OpNum) { |
| 7259 | case 0: |
| 7260 | // op: addr |
| 7261 | return 0; |
| 7262 | } |
| 7263 | break; |
| 7264 | } |
| 7265 | case Mips::CACHEE: |
| 7266 | case Mips::CACHE_R6: |
| 7267 | case Mips::PREFE: |
| 7268 | case Mips::PREF_R6: { |
| 7269 | switch (OpNum) { |
| 7270 | case 0: |
| 7271 | // op: addr |
| 7272 | return 7; |
| 7273 | case 2: |
| 7274 | // op: hint |
| 7275 | return 16; |
| 7276 | } |
| 7277 | break; |
| 7278 | } |
| 7279 | case Mips::BREAK16_MM: |
| 7280 | case Mips::SDBBP16_MM: |
| 7281 | case Mips::SIGRIE: { |
| 7282 | switch (OpNum) { |
| 7283 | case 0: |
| 7284 | // op: code_ |
| 7285 | return 0; |
| 7286 | } |
| 7287 | break; |
| 7288 | } |
| 7289 | case Mips::HYPCALL: { |
| 7290 | switch (OpNum) { |
| 7291 | case 0: |
| 7292 | // op: code_ |
| 7293 | return 11; |
| 7294 | } |
| 7295 | break; |
| 7296 | } |
| 7297 | case Mips::HYPCALL_MM: |
| 7298 | case Mips::SDBBP_MM: |
| 7299 | case Mips::SDBBP_MMR6: |
| 7300 | case Mips::SYSCALL_MM: |
| 7301 | case Mips::WAIT_MM: |
| 7302 | case Mips::WAIT_MMR6: { |
| 7303 | switch (OpNum) { |
| 7304 | case 0: |
| 7305 | // op: code_ |
| 7306 | return 16; |
| 7307 | } |
| 7308 | break; |
| 7309 | } |
| 7310 | case Mips::BREAK16_MMR6: |
| 7311 | case Mips::SDBBP: |
| 7312 | case Mips::SDBBP16_MMR6: |
| 7313 | case Mips::SDBBP_R6: |
| 7314 | case Mips::SIGRIE_MMR6: |
| 7315 | case Mips::SYSCALL: { |
| 7316 | switch (OpNum) { |
| 7317 | case 0: |
| 7318 | // op: code_ |
| 7319 | return 6; |
| 7320 | } |
| 7321 | break; |
| 7322 | } |
| 7323 | case Mips::BREAK: |
| 7324 | case Mips::BREAK_MM: |
| 7325 | case Mips::BREAK_MMR6: { |
| 7326 | switch (OpNum) { |
| 7327 | case 0: |
| 7328 | // op: code_1 |
| 7329 | return 16; |
| 7330 | case 1: |
| 7331 | // op: code_2 |
| 7332 | return 6; |
| 7333 | } |
| 7334 | break; |
| 7335 | } |
| 7336 | case Mips::BC2EQZ: |
| 7337 | case Mips::BC2NEZ: { |
| 7338 | switch (OpNum) { |
| 7339 | case 0: |
| 7340 | // op: ct |
| 7341 | return 16; |
| 7342 | case 1: |
| 7343 | // op: offset |
| 7344 | return 0; |
| 7345 | } |
| 7346 | break; |
| 7347 | } |
| 7348 | case Mips::BC1F: |
| 7349 | case Mips::BC1FL: |
| 7350 | case Mips::BC1F_MM: |
| 7351 | case Mips::BC1T: |
| 7352 | case Mips::BC1TL: |
| 7353 | case Mips::BC1T_MM: { |
| 7354 | switch (OpNum) { |
| 7355 | case 0: |
| 7356 | // op: fcc |
| 7357 | return 18; |
| 7358 | case 1: |
| 7359 | // op: offset |
| 7360 | return 0; |
| 7361 | } |
| 7362 | break; |
| 7363 | } |
| 7364 | case Mips::LUXC1_MM: |
| 7365 | case Mips::LWXC1_MM: { |
| 7366 | switch (OpNum) { |
| 7367 | case 0: |
| 7368 | // op: fd |
| 7369 | return 11; |
| 7370 | case 1: |
| 7371 | // op: base |
| 7372 | return 16; |
| 7373 | case 2: |
| 7374 | // op: index |
| 7375 | return 21; |
| 7376 | } |
| 7377 | break; |
| 7378 | } |
| 7379 | case Mips::MOVN_I_D32_MM: |
| 7380 | case Mips::MOVN_I_S_MM: |
| 7381 | case Mips::MOVZ_I_D32_MM: |
| 7382 | case Mips::MOVZ_I_S_MM: { |
| 7383 | switch (OpNum) { |
| 7384 | case 0: |
| 7385 | // op: fd |
| 7386 | return 11; |
| 7387 | case 1: |
| 7388 | // op: fs |
| 7389 | return 16; |
| 7390 | case 2: |
| 7391 | // op: rt |
| 7392 | return 21; |
| 7393 | } |
| 7394 | break; |
| 7395 | } |
| 7396 | case Mips::MOVF_D32_MM: |
| 7397 | case Mips::MOVF_S_MM: |
| 7398 | case Mips::MOVT_D32_MM: |
| 7399 | case Mips::MOVT_S_MM: { |
| 7400 | switch (OpNum) { |
| 7401 | case 0: |
| 7402 | // op: fd |
| 7403 | return 21; |
| 7404 | case 1: |
| 7405 | // op: fs |
| 7406 | return 16; |
| 7407 | case 2: |
| 7408 | // op: fcc |
| 7409 | return 13; |
| 7410 | } |
| 7411 | break; |
| 7412 | } |
| 7413 | case Mips::CEIL_W_MM: |
| 7414 | case Mips::CEIL_W_S_MM: |
| 7415 | case Mips::CVT_D32_S_MM: |
| 7416 | case Mips::CVT_D32_W_MM: |
| 7417 | case Mips::CVT_D64_S_MM: |
| 7418 | case Mips::CVT_D64_W_MM: |
| 7419 | case Mips::CVT_L_D64_MM: |
| 7420 | case Mips::CVT_L_S_MM: |
| 7421 | case Mips::CVT_S_D32_MM: |
| 7422 | case Mips::CVT_S_D64_MM: |
| 7423 | case Mips::CVT_S_W_MM: |
| 7424 | case Mips::CVT_W_D32_MM: |
| 7425 | case Mips::CVT_W_D64_MM: |
| 7426 | case Mips::CVT_W_S_MM: |
| 7427 | case Mips::FABS_D32_MM: |
| 7428 | case Mips::FABS_D64_MM: |
| 7429 | case Mips::FABS_S_MM: |
| 7430 | case Mips::FLOOR_W_MM: |
| 7431 | case Mips::FLOOR_W_S_MM: |
| 7432 | case Mips::FMOV_D32_MM: |
| 7433 | case Mips::FMOV_D64_MM: |
| 7434 | case Mips::FMOV_S_MM: |
| 7435 | case Mips::FNEG_D32_MM: |
| 7436 | case Mips::FNEG_D64_MM: |
| 7437 | case Mips::FNEG_S_MM: |
| 7438 | case Mips::FSQRT_D32_MM: |
| 7439 | case Mips::FSQRT_D64_MM: |
| 7440 | case Mips::FSQRT_S_MM: |
| 7441 | case Mips::RECIP_D32_MM: |
| 7442 | case Mips::RECIP_D64_MM: |
| 7443 | case Mips::RECIP_S_MM: |
| 7444 | case Mips::ROUND_W_MM: |
| 7445 | case Mips::ROUND_W_S_MM: |
| 7446 | case Mips::RSQRT_D32_MM: |
| 7447 | case Mips::RSQRT_D64_MM: |
| 7448 | case Mips::RSQRT_S_MM: |
| 7449 | case Mips::TRUNC_W_MM: |
| 7450 | case Mips::TRUNC_W_S_MM: { |
| 7451 | switch (OpNum) { |
| 7452 | case 0: |
| 7453 | // op: fd |
| 7454 | return 21; |
| 7455 | case 1: |
| 7456 | // op: fs |
| 7457 | return 16; |
| 7458 | } |
| 7459 | break; |
| 7460 | } |
| 7461 | case Mips::LDXC1: |
| 7462 | case Mips::LDXC164: |
| 7463 | case Mips::LUXC1: |
| 7464 | case Mips::LUXC164: |
| 7465 | case Mips::LWXC1: { |
| 7466 | switch (OpNum) { |
| 7467 | case 0: |
| 7468 | // op: fd |
| 7469 | return 6; |
| 7470 | case 1: |
| 7471 | // op: base |
| 7472 | return 21; |
| 7473 | case 2: |
| 7474 | // op: index |
| 7475 | return 16; |
| 7476 | } |
| 7477 | break; |
| 7478 | } |
| 7479 | case Mips::MADD_D32: |
| 7480 | case Mips::MADD_D64: |
| 7481 | case Mips::MADD_S: |
| 7482 | case Mips::MSUB_D32: |
| 7483 | case Mips::MSUB_D64: |
| 7484 | case Mips::MSUB_S: |
| 7485 | case Mips::NMADD_D32: |
| 7486 | case Mips::NMADD_D64: |
| 7487 | case Mips::NMADD_S: |
| 7488 | case Mips::NMSUB_D32: |
| 7489 | case Mips::NMSUB_D64: |
| 7490 | case Mips::NMSUB_S: { |
| 7491 | switch (OpNum) { |
| 7492 | case 0: |
| 7493 | // op: fd |
| 7494 | return 6; |
| 7495 | case 1: |
| 7496 | // op: fr |
| 7497 | return 21; |
| 7498 | case 2: |
| 7499 | // op: fs |
| 7500 | return 11; |
| 7501 | case 3: |
| 7502 | // op: ft |
| 7503 | return 16; |
| 7504 | } |
| 7505 | break; |
| 7506 | } |
| 7507 | case Mips::MOVF_D32: |
| 7508 | case Mips::MOVF_D64: |
| 7509 | case Mips::MOVF_S: |
| 7510 | case Mips::MOVT_D32: |
| 7511 | case Mips::MOVT_D64: |
| 7512 | case Mips::MOVT_S: { |
| 7513 | switch (OpNum) { |
| 7514 | case 0: |
| 7515 | // op: fd |
| 7516 | return 6; |
| 7517 | case 1: |
| 7518 | // op: fs |
| 7519 | return 11; |
| 7520 | case 2: |
| 7521 | // op: fcc |
| 7522 | return 18; |
| 7523 | } |
| 7524 | break; |
| 7525 | } |
| 7526 | case Mips::ADDR_PS64: |
| 7527 | case Mips::CMP_EQ_D: |
| 7528 | case Mips::CMP_EQ_S: |
| 7529 | case Mips::CMP_F_D: |
| 7530 | case Mips::CMP_F_S: |
| 7531 | case Mips::CMP_LE_D: |
| 7532 | case Mips::CMP_LE_S: |
| 7533 | case Mips::CMP_LT_D: |
| 7534 | case Mips::CMP_LT_S: |
| 7535 | case Mips::CMP_SAF_D: |
| 7536 | case Mips::CMP_SAF_S: |
| 7537 | case Mips::CMP_SEQ_D: |
| 7538 | case Mips::CMP_SEQ_S: |
| 7539 | case Mips::CMP_SLE_D: |
| 7540 | case Mips::CMP_SLE_S: |
| 7541 | case Mips::CMP_SLT_D: |
| 7542 | case Mips::CMP_SLT_S: |
| 7543 | case Mips::CMP_SUEQ_D: |
| 7544 | case Mips::CMP_SUEQ_S: |
| 7545 | case Mips::CMP_SULE_D: |
| 7546 | case Mips::CMP_SULE_S: |
| 7547 | case Mips::CMP_SULT_D: |
| 7548 | case Mips::CMP_SULT_S: |
| 7549 | case Mips::CMP_SUN_D: |
| 7550 | case Mips::CMP_SUN_S: |
| 7551 | case Mips::CMP_UEQ_D: |
| 7552 | case Mips::CMP_UEQ_S: |
| 7553 | case Mips::CMP_ULE_D: |
| 7554 | case Mips::CMP_ULE_S: |
| 7555 | case Mips::CMP_ULT_D: |
| 7556 | case Mips::CMP_ULT_S: |
| 7557 | case Mips::CMP_UN_D: |
| 7558 | case Mips::CMP_UN_S: |
| 7559 | case Mips::CVT_PS_S64: |
| 7560 | case Mips::FADD_D32: |
| 7561 | case Mips::FADD_D64: |
| 7562 | case Mips::FADD_PS64: |
| 7563 | case Mips::FADD_S: |
| 7564 | case Mips::FDIV_D32: |
| 7565 | case Mips::FDIV_D64: |
| 7566 | case Mips::FDIV_S: |
| 7567 | case Mips::FMUL_D32: |
| 7568 | case Mips::FMUL_D64: |
| 7569 | case Mips::FMUL_PS64: |
| 7570 | case Mips::FMUL_S: |
| 7571 | case Mips::FSUB_D32: |
| 7572 | case Mips::FSUB_D64: |
| 7573 | case Mips::FSUB_PS64: |
| 7574 | case Mips::FSUB_S: |
| 7575 | case Mips::MULR_PS64: |
| 7576 | case Mips::PLL_PS64: |
| 7577 | case Mips::PLU_PS64: |
| 7578 | case Mips::PUL_PS64: |
| 7579 | case Mips::PUU_PS64: { |
| 7580 | switch (OpNum) { |
| 7581 | case 0: |
| 7582 | // op: fd |
| 7583 | return 6; |
| 7584 | case 1: |
| 7585 | // op: fs |
| 7586 | return 11; |
| 7587 | case 2: |
| 7588 | // op: ft |
| 7589 | return 16; |
| 7590 | } |
| 7591 | break; |
| 7592 | } |
| 7593 | case Mips::MOVN_I64_D64: |
| 7594 | case Mips::MOVN_I64_S: |
| 7595 | case Mips::MOVN_I_D32: |
| 7596 | case Mips::MOVN_I_D64: |
| 7597 | case Mips::MOVN_I_S: |
| 7598 | case Mips::MOVZ_I64_D64: |
| 7599 | case Mips::MOVZ_I64_S: |
| 7600 | case Mips::MOVZ_I_D32: |
| 7601 | case Mips::MOVZ_I_D64: |
| 7602 | case Mips::MOVZ_I_S: { |
| 7603 | switch (OpNum) { |
| 7604 | case 0: |
| 7605 | // op: fd |
| 7606 | return 6; |
| 7607 | case 1: |
| 7608 | // op: fs |
| 7609 | return 11; |
| 7610 | case 2: |
| 7611 | // op: rt |
| 7612 | return 16; |
| 7613 | } |
| 7614 | break; |
| 7615 | } |
| 7616 | case Mips::CEIL_L_D64: |
| 7617 | case Mips::CEIL_L_S: |
| 7618 | case Mips::CEIL_W_D32: |
| 7619 | case Mips::CEIL_W_D64: |
| 7620 | case Mips::CEIL_W_S: |
| 7621 | case Mips::CVT_D32_S: |
| 7622 | case Mips::CVT_D32_W: |
| 7623 | case Mips::CVT_D64_L: |
| 7624 | case Mips::CVT_D64_S: |
| 7625 | case Mips::CVT_D64_W: |
| 7626 | case Mips::CVT_L_D64: |
| 7627 | case Mips::CVT_L_S: |
| 7628 | case Mips::CVT_PS_PW64: |
| 7629 | case Mips::CVT_PW_PS64: |
| 7630 | case Mips::CVT_S_D32: |
| 7631 | case Mips::CVT_S_D64: |
| 7632 | case Mips::CVT_S_L: |
| 7633 | case Mips::CVT_S_PL64: |
| 7634 | case Mips::CVT_S_PU64: |
| 7635 | case Mips::CVT_S_W: |
| 7636 | case Mips::CVT_W_D32: |
| 7637 | case Mips::CVT_W_D64: |
| 7638 | case Mips::CVT_W_S: |
| 7639 | case Mips::FABS_D32: |
| 7640 | case Mips::FABS_D64: |
| 7641 | case Mips::FABS_S: |
| 7642 | case Mips::FLOOR_L_D64: |
| 7643 | case Mips::FLOOR_L_S: |
| 7644 | case Mips::FLOOR_W_D32: |
| 7645 | case Mips::FLOOR_W_D64: |
| 7646 | case Mips::FLOOR_W_S: |
| 7647 | case Mips::FMOV_D32: |
| 7648 | case Mips::FMOV_D64: |
| 7649 | case Mips::FMOV_S: |
| 7650 | case Mips::FNEG_D32: |
| 7651 | case Mips::FNEG_D64: |
| 7652 | case Mips::FNEG_S: |
| 7653 | case Mips::FSQRT_D32: |
| 7654 | case Mips::FSQRT_D64: |
| 7655 | case Mips::FSQRT_S: |
| 7656 | case Mips::RECIP_D32: |
| 7657 | case Mips::RECIP_D64: |
| 7658 | case Mips::RECIP_S: |
| 7659 | case Mips::ROUND_L_D64: |
| 7660 | case Mips::ROUND_L_S: |
| 7661 | case Mips::ROUND_W_D32: |
| 7662 | case Mips::ROUND_W_D64: |
| 7663 | case Mips::ROUND_W_S: |
| 7664 | case Mips::RSQRT_D32: |
| 7665 | case Mips::RSQRT_D64: |
| 7666 | case Mips::RSQRT_S: |
| 7667 | case Mips::TRUNC_L_D64: |
| 7668 | case Mips::TRUNC_L_S: |
| 7669 | case Mips::TRUNC_W_D32: |
| 7670 | case Mips::TRUNC_W_D64: |
| 7671 | case Mips::TRUNC_W_S: { |
| 7672 | switch (OpNum) { |
| 7673 | case 0: |
| 7674 | // op: fd |
| 7675 | return 6; |
| 7676 | case 1: |
| 7677 | // op: fs |
| 7678 | return 11; |
| 7679 | } |
| 7680 | break; |
| 7681 | } |
| 7682 | case Mips::SUXC1_MM: |
| 7683 | case Mips::SWXC1_MM: { |
| 7684 | switch (OpNum) { |
| 7685 | case 0: |
| 7686 | // op: fs |
| 7687 | return 11; |
| 7688 | case 1: |
| 7689 | // op: base |
| 7690 | return 16; |
| 7691 | case 2: |
| 7692 | // op: index |
| 7693 | return 21; |
| 7694 | } |
| 7695 | break; |
| 7696 | } |
| 7697 | case Mips::SDXC1: |
| 7698 | case Mips::SDXC164: |
| 7699 | case Mips::SUXC1: |
| 7700 | case Mips::SUXC164: |
| 7701 | case Mips::SWXC1: { |
| 7702 | switch (OpNum) { |
| 7703 | case 0: |
| 7704 | // op: fs |
| 7705 | return 11; |
| 7706 | case 1: |
| 7707 | // op: base |
| 7708 | return 21; |
| 7709 | case 2: |
| 7710 | // op: index |
| 7711 | return 16; |
| 7712 | } |
| 7713 | break; |
| 7714 | } |
| 7715 | case Mips::FCMP_D32: |
| 7716 | case Mips::FCMP_D64: |
| 7717 | case Mips::FCMP_S32: { |
| 7718 | switch (OpNum) { |
| 7719 | case 0: |
| 7720 | // op: fs |
| 7721 | return 11; |
| 7722 | case 1: |
| 7723 | // op: ft |
| 7724 | return 16; |
| 7725 | case 2: |
| 7726 | // op: cond |
| 7727 | return 0; |
| 7728 | } |
| 7729 | break; |
| 7730 | } |
| 7731 | case Mips::FCMP_D32_MM: |
| 7732 | case Mips::FCMP_S32_MM: { |
| 7733 | switch (OpNum) { |
| 7734 | case 0: |
| 7735 | // op: fs |
| 7736 | return 16; |
| 7737 | case 1: |
| 7738 | // op: ft |
| 7739 | return 21; |
| 7740 | case 2: |
| 7741 | // op: cond |
| 7742 | return 6; |
| 7743 | } |
| 7744 | break; |
| 7745 | } |
| 7746 | case Mips::BC1EQZ: |
| 7747 | case Mips::BC1NEZ: { |
| 7748 | switch (OpNum) { |
| 7749 | case 0: |
| 7750 | // op: ft |
| 7751 | return 16; |
| 7752 | case 1: |
| 7753 | // op: offset |
| 7754 | return 0; |
| 7755 | } |
| 7756 | break; |
| 7757 | } |
| 7758 | case Mips::LDC1_D64_MMR6: |
| 7759 | case Mips::SDC1_D64_MMR6: { |
| 7760 | switch (OpNum) { |
| 7761 | case 0: |
| 7762 | // op: ft |
| 7763 | return 21; |
| 7764 | case 1: |
| 7765 | // op: addr |
| 7766 | return 0; |
| 7767 | } |
| 7768 | break; |
| 7769 | } |
| 7770 | case Mips::CEIL_L_D_MMR6: |
| 7771 | case Mips::CEIL_L_S_MMR6: |
| 7772 | case Mips::CEIL_W_D_MMR6: |
| 7773 | case Mips::CEIL_W_S_MMR6: |
| 7774 | case Mips::CVT_D_L_MMR6: |
| 7775 | case Mips::CVT_L_D_MMR6: |
| 7776 | case Mips::CVT_L_S_MMR6: |
| 7777 | case Mips::CVT_S_L_MMR6: |
| 7778 | case Mips::CVT_S_W_MMR6: |
| 7779 | case Mips::CVT_W_S_MMR6: |
| 7780 | case Mips::FLOOR_L_D_MMR6: |
| 7781 | case Mips::FLOOR_L_S_MMR6: |
| 7782 | case Mips::FLOOR_W_D_MMR6: |
| 7783 | case Mips::FLOOR_W_S_MMR6: |
| 7784 | case Mips::FMOV_D_MMR6: |
| 7785 | case Mips::FMOV_S_MMR6: |
| 7786 | case Mips::FNEG_S_MMR6: |
| 7787 | case Mips::ROUND_L_D_MMR6: |
| 7788 | case Mips::ROUND_L_S_MMR6: |
| 7789 | case Mips::ROUND_W_D_MMR6: |
| 7790 | case Mips::ROUND_W_S_MMR6: |
| 7791 | case Mips::TRUNC_L_D_MMR6: |
| 7792 | case Mips::TRUNC_L_S_MMR6: |
| 7793 | case Mips::TRUNC_W_D_MMR6: |
| 7794 | case Mips::TRUNC_W_S_MMR6: { |
| 7795 | switch (OpNum) { |
| 7796 | case 0: |
| 7797 | // op: ft |
| 7798 | return 21; |
| 7799 | case 1: |
| 7800 | // op: fs |
| 7801 | return 16; |
| 7802 | } |
| 7803 | break; |
| 7804 | } |
| 7805 | case Mips::JRADDIUSP: { |
| 7806 | switch (OpNum) { |
| 7807 | case 0: |
| 7808 | // op: imm |
| 7809 | return 0; |
| 7810 | } |
| 7811 | break; |
| 7812 | } |
| 7813 | case Mips::ADDIUSP_MM: { |
| 7814 | switch (OpNum) { |
| 7815 | case 0: |
| 7816 | // op: imm |
| 7817 | return 1; |
| 7818 | } |
| 7819 | break; |
| 7820 | } |
| 7821 | case Mips::JRCADDIUSP_MMR6: { |
| 7822 | switch (OpNum) { |
| 7823 | case 0: |
| 7824 | // op: imm |
| 7825 | return 5; |
| 7826 | } |
| 7827 | break; |
| 7828 | } |
| 7829 | case Mips::Bimm16: { |
| 7830 | switch (OpNum) { |
| 7831 | case 0: |
| 7832 | // op: imm11 |
| 7833 | return 0; |
| 7834 | } |
| 7835 | break; |
| 7836 | } |
| 7837 | case Mips::AddiuSpImmX16: |
| 7838 | case Mips::BimmX16: |
| 7839 | case Mips::BteqzX16: |
| 7840 | case Mips::BtnezX16: { |
| 7841 | switch (OpNum) { |
| 7842 | case 0: |
| 7843 | // op: imm16 |
| 7844 | return 0; |
| 7845 | } |
| 7846 | break; |
| 7847 | } |
| 7848 | case Mips::Jal16: |
| 7849 | case Mips::JalB16: { |
| 7850 | switch (OpNum) { |
| 7851 | case 0: |
| 7852 | // op: imm26 |
| 7853 | return 0; |
| 7854 | } |
| 7855 | break; |
| 7856 | } |
| 7857 | case Mips::AddiuSpImm16: |
| 7858 | case Mips::Bteqz16: |
| 7859 | case Mips::Btnez16: { |
| 7860 | switch (OpNum) { |
| 7861 | case 0: |
| 7862 | // op: imm8 |
| 7863 | return 0; |
| 7864 | } |
| 7865 | break; |
| 7866 | } |
| 7867 | case Mips::B16_MM: |
| 7868 | case Mips::BAL: |
| 7869 | case Mips::BALC: |
| 7870 | case Mips::BALC_MMR6: |
| 7871 | case Mips::BC: |
| 7872 | case Mips::BC16_MMR6: |
| 7873 | case Mips::BC_MMR6: |
| 7874 | case Mips::BPOSGE32: |
| 7875 | case Mips::BPOSGE32C_MMR3: |
| 7876 | case Mips::BPOSGE32_MM: { |
| 7877 | switch (OpNum) { |
| 7878 | case 0: |
| 7879 | // op: offset |
| 7880 | return 0; |
| 7881 | } |
| 7882 | break; |
| 7883 | } |
| 7884 | case Mips::Move32R16: { |
| 7885 | switch (OpNum) { |
| 7886 | case 0: |
| 7887 | // op: r32 |
| 7888 | return 3; |
| 7889 | case 1: |
| 7890 | // op: rz |
| 7891 | return 0; |
| 7892 | } |
| 7893 | break; |
| 7894 | } |
| 7895 | case Mips::MFHI16_MM: |
| 7896 | case Mips::MFLO16_MM: { |
| 7897 | switch (OpNum) { |
| 7898 | case 0: |
| 7899 | // op: rd |
| 7900 | return 0; |
| 7901 | } |
| 7902 | break; |
| 7903 | } |
| 7904 | case Mips::MFHI_DSP: |
| 7905 | case Mips::MFLO_DSP: { |
| 7906 | switch (OpNum) { |
| 7907 | case 0: |
| 7908 | // op: rd |
| 7909 | return 11; |
| 7910 | case 1: |
| 7911 | // op: ac |
| 7912 | return 21; |
| 7913 | } |
| 7914 | break; |
| 7915 | } |
| 7916 | case Mips::LWXS_MM: { |
| 7917 | switch (OpNum) { |
| 7918 | case 0: |
| 7919 | // op: rd |
| 7920 | return 11; |
| 7921 | case 1: |
| 7922 | // op: base |
| 7923 | return 16; |
| 7924 | case 2: |
| 7925 | // op: index |
| 7926 | return 21; |
| 7927 | } |
| 7928 | break; |
| 7929 | } |
| 7930 | case Mips::LBUX: |
| 7931 | case Mips::LHX: |
| 7932 | case Mips::LWX: { |
| 7933 | switch (OpNum) { |
| 7934 | case 0: |
| 7935 | // op: rd |
| 7936 | return 11; |
| 7937 | case 1: |
| 7938 | // op: base |
| 7939 | return 21; |
| 7940 | case 2: |
| 7941 | // op: index |
| 7942 | return 16; |
| 7943 | } |
| 7944 | break; |
| 7945 | } |
| 7946 | case Mips::REPL_PH: |
| 7947 | case Mips::REPL_PH_MM: |
| 7948 | case Mips::REPL_QB: { |
| 7949 | switch (OpNum) { |
| 7950 | case 0: |
| 7951 | // op: rd |
| 7952 | return 11; |
| 7953 | case 1: |
| 7954 | // op: imm |
| 7955 | return 16; |
| 7956 | } |
| 7957 | break; |
| 7958 | } |
| 7959 | case Mips::RDDSP: { |
| 7960 | switch (OpNum) { |
| 7961 | case 0: |
| 7962 | // op: rd |
| 7963 | return 11; |
| 7964 | case 1: |
| 7965 | // op: mask |
| 7966 | return 16; |
| 7967 | } |
| 7968 | break; |
| 7969 | } |
| 7970 | case Mips::LSA_MMR6: { |
| 7971 | switch (OpNum) { |
| 7972 | case 0: |
| 7973 | // op: rd |
| 7974 | return 11; |
| 7975 | case 1: |
| 7976 | // op: rs |
| 7977 | return 16; |
| 7978 | case 2: |
| 7979 | // op: rt |
| 7980 | return 21; |
| 7981 | case 3: |
| 7982 | // op: imm2 |
| 7983 | return 9; |
| 7984 | } |
| 7985 | break; |
| 7986 | } |
| 7987 | case Mips::ADDQH_PH_MMR2: |
| 7988 | case Mips::ADDQH_R_PH_MMR2: |
| 7989 | case Mips::ADDQH_R_W_MMR2: |
| 7990 | case Mips::ADDQH_W_MMR2: |
| 7991 | case Mips::ADDQ_PH_MM: |
| 7992 | case Mips::ADDQ_S_PH_MM: |
| 7993 | case Mips::ADDQ_S_W_MM: |
| 7994 | case Mips::ADDSC_MM: |
| 7995 | case Mips::ADDUH_QB_MMR2: |
| 7996 | case Mips::ADDUH_R_QB_MMR2: |
| 7997 | case Mips::ADDU_PH_MMR2: |
| 7998 | case Mips::ADDU_QB_MM: |
| 7999 | case Mips::ADDU_S_PH_MMR2: |
| 8000 | case Mips::ADDU_S_QB_MM: |
| 8001 | case Mips::ADDWC_MM: |
| 8002 | case Mips::CMPGDU_EQ_QB_MMR2: |
| 8003 | case Mips::CMPGDU_LE_QB_MMR2: |
| 8004 | case Mips::CMPGDU_LT_QB_MMR2: |
| 8005 | case Mips::MODSUB_MM: |
| 8006 | case Mips::MULEQ_S_W_PHL_MM: |
| 8007 | case Mips::MULEQ_S_W_PHR_MM: |
| 8008 | case Mips::MULEU_S_PH_QBL_MM: |
| 8009 | case Mips::MULEU_S_PH_QBR_MM: |
| 8010 | case Mips::MULQ_RS_PH_MM: |
| 8011 | case Mips::MULQ_RS_W_MMR2: |
| 8012 | case Mips::MULQ_S_PH_MMR2: |
| 8013 | case Mips::MULQ_S_W_MMR2: |
| 8014 | case Mips::MUL_PH_MMR2: |
| 8015 | case Mips::MUL_S_PH_MMR2: |
| 8016 | case Mips::PACKRL_PH_MM: |
| 8017 | case Mips::PICK_PH_MM: |
| 8018 | case Mips::PICK_QB_MM: |
| 8019 | case Mips::PRECRQU_S_QB_PH_MM: |
| 8020 | case Mips::PRECRQ_PH_W_MM: |
| 8021 | case Mips::PRECRQ_QB_PH_MM: |
| 8022 | case Mips::PRECRQ_RS_PH_W_MM: |
| 8023 | case Mips::PRECR_QB_PH_MMR2: |
| 8024 | case Mips::SELEQZ_MMR6: |
| 8025 | case Mips::SELNEZ_MMR6: |
| 8026 | case Mips::SUBQH_PH_MMR2: |
| 8027 | case Mips::SUBQH_R_PH_MMR2: |
| 8028 | case Mips::SUBQH_R_W_MMR2: |
| 8029 | case Mips::SUBQH_W_MMR2: |
| 8030 | case Mips::SUBQ_PH_MM: |
| 8031 | case Mips::SUBQ_S_PH_MM: |
| 8032 | case Mips::SUBQ_S_W_MM: |
| 8033 | case Mips::SUBUH_QB_MMR2: |
| 8034 | case Mips::SUBUH_R_QB_MMR2: |
| 8035 | case Mips::SUBU_PH_MMR2: |
| 8036 | case Mips::SUBU_QB_MM: |
| 8037 | case Mips::SUBU_S_PH_MMR2: |
| 8038 | case Mips::SUBU_S_QB_MM: { |
| 8039 | switch (OpNum) { |
| 8040 | case 0: |
| 8041 | // op: rd |
| 8042 | return 11; |
| 8043 | case 1: |
| 8044 | // op: rs |
| 8045 | return 16; |
| 8046 | case 2: |
| 8047 | // op: rt |
| 8048 | return 21; |
| 8049 | } |
| 8050 | break; |
| 8051 | } |
| 8052 | case Mips::MOVF_I: |
| 8053 | case Mips::MOVF_I64: |
| 8054 | case Mips::MOVT_I: |
| 8055 | case Mips::MOVT_I64: { |
| 8056 | switch (OpNum) { |
| 8057 | case 0: |
| 8058 | // op: rd |
| 8059 | return 11; |
| 8060 | case 1: |
| 8061 | // op: rs |
| 8062 | return 21; |
| 8063 | case 2: |
| 8064 | // op: fcc |
| 8065 | return 18; |
| 8066 | } |
| 8067 | break; |
| 8068 | } |
| 8069 | case Mips::ALIGN: |
| 8070 | case Mips::DALIGN: { |
| 8071 | switch (OpNum) { |
| 8072 | case 0: |
| 8073 | // op: rd |
| 8074 | return 11; |
| 8075 | case 1: |
| 8076 | // op: rs |
| 8077 | return 21; |
| 8078 | case 2: |
| 8079 | // op: rt |
| 8080 | return 16; |
| 8081 | case 3: |
| 8082 | // op: bp |
| 8083 | return 6; |
| 8084 | } |
| 8085 | break; |
| 8086 | } |
| 8087 | case Mips::ALIGN_MMR6: { |
| 8088 | switch (OpNum) { |
| 8089 | case 0: |
| 8090 | // op: rd |
| 8091 | return 11; |
| 8092 | case 1: |
| 8093 | // op: rs |
| 8094 | return 21; |
| 8095 | case 2: |
| 8096 | // op: rt |
| 8097 | return 16; |
| 8098 | case 3: |
| 8099 | // op: bp |
| 8100 | return 9; |
| 8101 | } |
| 8102 | break; |
| 8103 | } |
| 8104 | case Mips::DLSA_R6: |
| 8105 | case Mips::LSA_R6: { |
| 8106 | switch (OpNum) { |
| 8107 | case 0: |
| 8108 | // op: rd |
| 8109 | return 11; |
| 8110 | case 1: |
| 8111 | // op: rs |
| 8112 | return 21; |
| 8113 | case 2: |
| 8114 | // op: rt |
| 8115 | return 16; |
| 8116 | case 3: |
| 8117 | // op: imm2 |
| 8118 | return 6; |
| 8119 | } |
| 8120 | break; |
| 8121 | } |
| 8122 | case Mips::ADD: |
| 8123 | case Mips::ADDQH_PH: |
| 8124 | case Mips::ADDQH_R_PH: |
| 8125 | case Mips::ADDQH_R_W: |
| 8126 | case Mips::ADDQH_W: |
| 8127 | case Mips::ADDQ_PH: |
| 8128 | case Mips::ADDQ_S_PH: |
| 8129 | case Mips::ADDQ_S_W: |
| 8130 | case Mips::ADDSC: |
| 8131 | case Mips::ADDUH_QB: |
| 8132 | case Mips::ADDUH_R_QB: |
| 8133 | case Mips::ADDU_PH: |
| 8134 | case Mips::ADDU_QB: |
| 8135 | case Mips::ADDU_S_PH: |
| 8136 | case Mips::ADDU_S_QB: |
| 8137 | case Mips::ADDWC: |
| 8138 | case Mips::ADDu: |
| 8139 | case Mips::AND: |
| 8140 | case Mips::AND64: |
| 8141 | case Mips::BADDu: |
| 8142 | case Mips::DADD: |
| 8143 | case Mips::DADDu: |
| 8144 | case Mips::DDIV: |
| 8145 | case Mips::DDIVU: |
| 8146 | case Mips::DIV: |
| 8147 | case Mips::DIVU: |
| 8148 | case Mips::DMOD: |
| 8149 | case Mips::DMODU: |
| 8150 | case Mips::DMUH: |
| 8151 | case Mips::DMUHU: |
| 8152 | case Mips::DMUL: |
| 8153 | case Mips::DMULU: |
| 8154 | case Mips::DMUL_R6: |
| 8155 | case Mips::DSUB: |
| 8156 | case Mips::DSUBu: |
| 8157 | case Mips::MOD: |
| 8158 | case Mips::MODSUB: |
| 8159 | case Mips::MODU: |
| 8160 | case Mips::MOVN_I64_I: |
| 8161 | case Mips::MOVN_I64_I64: |
| 8162 | case Mips::MOVN_I_I: |
| 8163 | case Mips::MOVN_I_I64: |
| 8164 | case Mips::MOVZ_I64_I: |
| 8165 | case Mips::MOVZ_I64_I64: |
| 8166 | case Mips::MOVZ_I_I: |
| 8167 | case Mips::MOVZ_I_I64: |
| 8168 | case Mips::MUH: |
| 8169 | case Mips::MUHU: |
| 8170 | case Mips::MUL: |
| 8171 | case Mips::MULEQ_S_W_PHL: |
| 8172 | case Mips::MULEQ_S_W_PHR: |
| 8173 | case Mips::MULEU_S_PH_QBL: |
| 8174 | case Mips::MULEU_S_PH_QBR: |
| 8175 | case Mips::MULQ_RS_PH: |
| 8176 | case Mips::MULQ_RS_W: |
| 8177 | case Mips::MULQ_S_PH: |
| 8178 | case Mips::MULQ_S_W: |
| 8179 | case Mips::MULU: |
| 8180 | case Mips::MUL_PH: |
| 8181 | case Mips::MUL_R6: |
| 8182 | case Mips::MUL_S_PH: |
| 8183 | case Mips::NOR: |
| 8184 | case Mips::NOR64: |
| 8185 | case Mips::OR: |
| 8186 | case Mips::OR64: |
| 8187 | case Mips::SELEQZ: |
| 8188 | case Mips::SELEQZ64: |
| 8189 | case Mips::SELNEZ: |
| 8190 | case Mips::SELNEZ64: |
| 8191 | case Mips::SEQ: |
| 8192 | case Mips::SLT: |
| 8193 | case Mips::SLT64: |
| 8194 | case Mips::SLTu: |
| 8195 | case Mips::SLTu64: |
| 8196 | case Mips::SNE: |
| 8197 | case Mips::SUB: |
| 8198 | case Mips::SUBQH_PH: |
| 8199 | case Mips::SUBQH_R_PH: |
| 8200 | case Mips::SUBQH_R_W: |
| 8201 | case Mips::SUBQH_W: |
| 8202 | case Mips::SUBQ_PH: |
| 8203 | case Mips::SUBQ_S_PH: |
| 8204 | case Mips::SUBQ_S_W: |
| 8205 | case Mips::SUBUH_QB: |
| 8206 | case Mips::SUBUH_R_QB: |
| 8207 | case Mips::SUBU_PH: |
| 8208 | case Mips::SUBU_QB: |
| 8209 | case Mips::SUBU_S_PH: |
| 8210 | case Mips::SUBU_S_QB: |
| 8211 | case Mips::SUBu: |
| 8212 | case Mips::V3MULU: |
| 8213 | case Mips::VMM0: |
| 8214 | case Mips::VMULU: |
| 8215 | case Mips::XOR: |
| 8216 | case Mips::XOR64: { |
| 8217 | switch (OpNum) { |
| 8218 | case 0: |
| 8219 | // op: rd |
| 8220 | return 11; |
| 8221 | case 1: |
| 8222 | // op: rs |
| 8223 | return 21; |
| 8224 | case 2: |
| 8225 | // op: rt |
| 8226 | return 16; |
| 8227 | } |
| 8228 | break; |
| 8229 | } |
| 8230 | case Mips::CLO: |
| 8231 | case Mips::CLO_R6: |
| 8232 | case Mips::CLZ: |
| 8233 | case Mips::CLZ_R6: |
| 8234 | case Mips::DCLO: |
| 8235 | case Mips::DCLO_R6: |
| 8236 | case Mips::DCLZ: |
| 8237 | case Mips::DCLZ_R6: |
| 8238 | case Mips::DPOP: |
| 8239 | case Mips::JALR: |
| 8240 | case Mips::JALR64: |
| 8241 | case Mips::JALR_HB: |
| 8242 | case Mips::JALR_HB64: |
| 8243 | case Mips::POP: |
| 8244 | case Mips::RADDU_W_QB: { |
| 8245 | switch (OpNum) { |
| 8246 | case 0: |
| 8247 | // op: rd |
| 8248 | return 11; |
| 8249 | case 1: |
| 8250 | // op: rs |
| 8251 | return 21; |
| 8252 | } |
| 8253 | break; |
| 8254 | } |
| 8255 | case Mips::DROTRV: |
| 8256 | case Mips::DSLLV: |
| 8257 | case Mips::DSRAV: |
| 8258 | case Mips::DSRLV: |
| 8259 | case Mips::ROTRV: |
| 8260 | case Mips::SLLV: |
| 8261 | case Mips::SRAV: |
| 8262 | case Mips::SRLV: { |
| 8263 | switch (OpNum) { |
| 8264 | case 0: |
| 8265 | // op: rd |
| 8266 | return 11; |
| 8267 | case 1: |
| 8268 | // op: rt |
| 8269 | return 16; |
| 8270 | case 2: |
| 8271 | // op: rs |
| 8272 | return 21; |
| 8273 | } |
| 8274 | break; |
| 8275 | } |
| 8276 | case Mips::SHLLV_PH: |
| 8277 | case Mips::SHLLV_QB: |
| 8278 | case Mips::SHLLV_S_PH: |
| 8279 | case Mips::SHLLV_S_W: |
| 8280 | case Mips::SHLL_PH: |
| 8281 | case Mips::SHLL_QB: |
| 8282 | case Mips::SHLL_S_PH: |
| 8283 | case Mips::SHLL_S_W: |
| 8284 | case Mips::SHRAV_PH: |
| 8285 | case Mips::SHRAV_QB: |
| 8286 | case Mips::SHRAV_R_PH: |
| 8287 | case Mips::SHRAV_R_QB: |
| 8288 | case Mips::SHRAV_R_W: |
| 8289 | case Mips::SHRA_PH: |
| 8290 | case Mips::SHRA_QB: |
| 8291 | case Mips::SHRA_R_PH: |
| 8292 | case Mips::SHRA_R_QB: |
| 8293 | case Mips::SHRA_R_W: |
| 8294 | case Mips::SHRLV_PH: |
| 8295 | case Mips::SHRLV_QB: |
| 8296 | case Mips::SHRL_PH: |
| 8297 | case Mips::SHRL_QB: { |
| 8298 | switch (OpNum) { |
| 8299 | case 0: |
| 8300 | // op: rd |
| 8301 | return 11; |
| 8302 | case 1: |
| 8303 | // op: rt |
| 8304 | return 16; |
| 8305 | case 2: |
| 8306 | // op: rs_sa |
| 8307 | return 21; |
| 8308 | } |
| 8309 | break; |
| 8310 | } |
| 8311 | case Mips::DROTR: |
| 8312 | case Mips::DROTR32: |
| 8313 | case Mips::DSLL: |
| 8314 | case Mips::DSLL32: |
| 8315 | case Mips::DSRA: |
| 8316 | case Mips::DSRA32: |
| 8317 | case Mips::DSRL: |
| 8318 | case Mips::DSRL32: |
| 8319 | case Mips::ROTR: |
| 8320 | case Mips::SLL: |
| 8321 | case Mips::SRA: |
| 8322 | case Mips::SRL: { |
| 8323 | switch (OpNum) { |
| 8324 | case 0: |
| 8325 | // op: rd |
| 8326 | return 11; |
| 8327 | case 1: |
| 8328 | // op: rt |
| 8329 | return 16; |
| 8330 | case 2: |
| 8331 | // op: shamt |
| 8332 | return 6; |
| 8333 | } |
| 8334 | break; |
| 8335 | } |
| 8336 | case Mips::ABSQ_S_PH: |
| 8337 | case Mips::ABSQ_S_QB: |
| 8338 | case Mips::ABSQ_S_W: |
| 8339 | case Mips::BITREV: |
| 8340 | case Mips::BITSWAP: |
| 8341 | case Mips::DBITSWAP: |
| 8342 | case Mips::DSBH: |
| 8343 | case Mips::DSHD: |
| 8344 | case Mips::DSLL64_32: |
| 8345 | case Mips::PRECEQU_PH_QBL: |
| 8346 | case Mips::PRECEQU_PH_QBLA: |
| 8347 | case Mips::PRECEQU_PH_QBR: |
| 8348 | case Mips::PRECEQU_PH_QBRA: |
| 8349 | case Mips::PRECEQ_W_PHL: |
| 8350 | case Mips::PRECEQ_W_PHR: |
| 8351 | case Mips::PRECEU_PH_QBL: |
| 8352 | case Mips::PRECEU_PH_QBLA: |
| 8353 | case Mips::PRECEU_PH_QBR: |
| 8354 | case Mips::PRECEU_PH_QBRA: |
| 8355 | case Mips::REPLV_PH: |
| 8356 | case Mips::REPLV_QB: |
| 8357 | case Mips::SEB: |
| 8358 | case Mips::SEB64: |
| 8359 | case Mips::SEH: |
| 8360 | case Mips::SEH64: |
| 8361 | case Mips::SLL64_32: |
| 8362 | case Mips::SLL64_64: |
| 8363 | case Mips::WSBH: { |
| 8364 | switch (OpNum) { |
| 8365 | case 0: |
| 8366 | // op: rd |
| 8367 | return 11; |
| 8368 | case 1: |
| 8369 | // op: rt |
| 8370 | return 16; |
| 8371 | } |
| 8372 | break; |
| 8373 | } |
| 8374 | case Mips::ROTRV_MM: |
| 8375 | case Mips::SLLV_MM: |
| 8376 | case Mips::SRAV_MM: |
| 8377 | case Mips::SRLV_MM: { |
| 8378 | switch (OpNum) { |
| 8379 | case 0: |
| 8380 | // op: rd |
| 8381 | return 11; |
| 8382 | case 1: |
| 8383 | // op: rt |
| 8384 | return 21; |
| 8385 | case 2: |
| 8386 | // op: rs |
| 8387 | return 16; |
| 8388 | } |
| 8389 | break; |
| 8390 | } |
| 8391 | case Mips::SHLLV_PH_MM: |
| 8392 | case Mips::SHLLV_QB_MM: |
| 8393 | case Mips::SHLLV_S_PH_MM: |
| 8394 | case Mips::SHLLV_S_W_MM: |
| 8395 | case Mips::SHRAV_PH_MM: |
| 8396 | case Mips::SHRAV_QB_MMR2: |
| 8397 | case Mips::SHRAV_R_PH_MM: |
| 8398 | case Mips::SHRAV_R_QB_MMR2: |
| 8399 | case Mips::SHRAV_R_W_MM: |
| 8400 | case Mips::SHRLV_PH_MMR2: |
| 8401 | case Mips::SHRLV_QB_MM: { |
| 8402 | switch (OpNum) { |
| 8403 | case 0: |
| 8404 | // op: rd |
| 8405 | return 11; |
| 8406 | case 2: |
| 8407 | // op: rs |
| 8408 | return 16; |
| 8409 | case 1: |
| 8410 | // op: rt |
| 8411 | return 21; |
| 8412 | } |
| 8413 | break; |
| 8414 | } |
| 8415 | case Mips::ADDU_MMR6: |
| 8416 | case Mips::ADD_MMR6: |
| 8417 | case Mips::AND_MMR6: |
| 8418 | case Mips::DIVU_MMR6: |
| 8419 | case Mips::DIV_MMR6: |
| 8420 | case Mips::MODU_MMR6: |
| 8421 | case Mips::MOD_MMR6: |
| 8422 | case Mips::MUHU_MMR6: |
| 8423 | case Mips::MUH_MMR6: |
| 8424 | case Mips::MULU_MMR6: |
| 8425 | case Mips::MUL_MMR6: |
| 8426 | case Mips::NOR_MMR6: |
| 8427 | case Mips::OR_MMR6: |
| 8428 | case Mips::SUBU_MMR6: |
| 8429 | case Mips::SUB_MMR6: |
| 8430 | case Mips::XOR_MMR6: { |
| 8431 | switch (OpNum) { |
| 8432 | case 0: |
| 8433 | // op: rd |
| 8434 | return 11; |
| 8435 | case 2: |
| 8436 | // op: rt |
| 8437 | return 21; |
| 8438 | case 1: |
| 8439 | // op: rs |
| 8440 | return 16; |
| 8441 | } |
| 8442 | break; |
| 8443 | } |
| 8444 | case Mips::MFHI: |
| 8445 | case Mips::MFHI64: |
| 8446 | case Mips::MFLO: |
| 8447 | case Mips::MFLO64: { |
| 8448 | switch (OpNum) { |
| 8449 | case 0: |
| 8450 | // op: rd |
| 8451 | return 11; |
| 8452 | } |
| 8453 | break; |
| 8454 | } |
| 8455 | case Mips::BITSWAP_MMR6: { |
| 8456 | switch (OpNum) { |
| 8457 | case 0: |
| 8458 | // op: rd |
| 8459 | return 16; |
| 8460 | case 1: |
| 8461 | // op: rt |
| 8462 | return 21; |
| 8463 | } |
| 8464 | break; |
| 8465 | } |
| 8466 | case Mips::MFHI_MM: |
| 8467 | case Mips::MFLO_MM: { |
| 8468 | switch (OpNum) { |
| 8469 | case 0: |
| 8470 | // op: rd |
| 8471 | return 16; |
| 8472 | } |
| 8473 | break; |
| 8474 | } |
| 8475 | case Mips::MOVF_I_MM: |
| 8476 | case Mips::MOVT_I_MM: { |
| 8477 | switch (OpNum) { |
| 8478 | case 0: |
| 8479 | // op: rd |
| 8480 | return 21; |
| 8481 | case 1: |
| 8482 | // op: rs |
| 8483 | return 16; |
| 8484 | case 2: |
| 8485 | // op: fcc |
| 8486 | return 13; |
| 8487 | } |
| 8488 | break; |
| 8489 | } |
| 8490 | case Mips::CLO_MM: |
| 8491 | case Mips::CLZ_MM: { |
| 8492 | switch (OpNum) { |
| 8493 | case 0: |
| 8494 | // op: rd |
| 8495 | return 21; |
| 8496 | case 1: |
| 8497 | // op: rs |
| 8498 | return 16; |
| 8499 | } |
| 8500 | break; |
| 8501 | } |
| 8502 | case Mips::ROTR_MM: |
| 8503 | case Mips::SLL_MM: |
| 8504 | case Mips::SLL_MMR6: |
| 8505 | case Mips::SRA_MM: |
| 8506 | case Mips::SRL_MM: { |
| 8507 | switch (OpNum) { |
| 8508 | case 0: |
| 8509 | // op: rd |
| 8510 | return 21; |
| 8511 | case 1: |
| 8512 | // op: rt |
| 8513 | return 16; |
| 8514 | case 2: |
| 8515 | // op: shamt |
| 8516 | return 11; |
| 8517 | } |
| 8518 | break; |
| 8519 | } |
| 8520 | case Mips::SEB_MM: |
| 8521 | case Mips::SEH_MM: |
| 8522 | case Mips::WSBH_MM: { |
| 8523 | switch (OpNum) { |
| 8524 | case 0: |
| 8525 | // op: rd |
| 8526 | return 21; |
| 8527 | case 1: |
| 8528 | // op: rt |
| 8529 | return 16; |
| 8530 | } |
| 8531 | break; |
| 8532 | } |
| 8533 | case Mips::CFCMSA: { |
| 8534 | switch (OpNum) { |
| 8535 | case 0: |
| 8536 | // op: rd |
| 8537 | return 6; |
| 8538 | case 1: |
| 8539 | // op: cs |
| 8540 | return 11; |
| 8541 | } |
| 8542 | break; |
| 8543 | } |
| 8544 | case Mips::LI16_MM: |
| 8545 | case Mips::LI16_MMR6: { |
| 8546 | switch (OpNum) { |
| 8547 | case 0: |
| 8548 | // op: rd |
| 8549 | return 7; |
| 8550 | case 1: |
| 8551 | // op: imm |
| 8552 | return 0; |
| 8553 | } |
| 8554 | break; |
| 8555 | } |
| 8556 | case Mips::ADDIUR1SP_MM: { |
| 8557 | switch (OpNum) { |
| 8558 | case 0: |
| 8559 | // op: rd |
| 8560 | return 7; |
| 8561 | case 1: |
| 8562 | // op: imm |
| 8563 | return 1; |
| 8564 | } |
| 8565 | break; |
| 8566 | } |
| 8567 | case Mips::ANDI16_MM: |
| 8568 | case Mips::ANDI16_MMR6: { |
| 8569 | switch (OpNum) { |
| 8570 | case 0: |
| 8571 | // op: rd |
| 8572 | return 7; |
| 8573 | case 1: |
| 8574 | // op: rs |
| 8575 | return 4; |
| 8576 | case 2: |
| 8577 | // op: imm |
| 8578 | return 0; |
| 8579 | } |
| 8580 | break; |
| 8581 | } |
| 8582 | case Mips::ADDIUR2_MM: { |
| 8583 | switch (OpNum) { |
| 8584 | case 0: |
| 8585 | // op: rd |
| 8586 | return 7; |
| 8587 | case 1: |
| 8588 | // op: rs |
| 8589 | return 4; |
| 8590 | case 2: |
| 8591 | // op: imm |
| 8592 | return 1; |
| 8593 | } |
| 8594 | break; |
| 8595 | } |
| 8596 | case Mips::SLL16_MM: |
| 8597 | case Mips::SLL16_MMR6: |
| 8598 | case Mips::SRL16_MM: |
| 8599 | case Mips::SRL16_MMR6: { |
| 8600 | switch (OpNum) { |
| 8601 | case 0: |
| 8602 | // op: rd |
| 8603 | return 7; |
| 8604 | case 1: |
| 8605 | // op: rt |
| 8606 | return 4; |
| 8607 | case 2: |
| 8608 | // op: shamt |
| 8609 | return 1; |
| 8610 | } |
| 8611 | break; |
| 8612 | } |
| 8613 | case Mips::ADDU16_MM: |
| 8614 | case Mips::SUBU16_MM: { |
| 8615 | switch (OpNum) { |
| 8616 | case 0: |
| 8617 | // op: rd |
| 8618 | return 7; |
| 8619 | case 2: |
| 8620 | // op: rt |
| 8621 | return 4; |
| 8622 | case 1: |
| 8623 | // op: rs |
| 8624 | return 1; |
| 8625 | } |
| 8626 | break; |
| 8627 | } |
| 8628 | case Mips::JALR16_MM: |
| 8629 | case Mips::JALRS16_MM: |
| 8630 | case Mips::JR16_MM: |
| 8631 | case Mips::JRC16_MM: { |
| 8632 | switch (OpNum) { |
| 8633 | case 0: |
| 8634 | // op: rs |
| 8635 | return 0; |
| 8636 | } |
| 8637 | break; |
| 8638 | } |
| 8639 | case Mips::MFHI_DSP_MM: |
| 8640 | case Mips::MFLO_DSP_MM: { |
| 8641 | switch (OpNum) { |
| 8642 | case 0: |
| 8643 | // op: rs |
| 8644 | return 16; |
| 8645 | case 1: |
| 8646 | // op: ac |
| 8647 | return 14; |
| 8648 | } |
| 8649 | break; |
| 8650 | } |
| 8651 | case Mips::TEQI_MM: |
| 8652 | case Mips::TGEIU_MM: |
| 8653 | case Mips::TGEI_MM: |
| 8654 | case Mips::TLTIU_MM: |
| 8655 | case Mips::TLTI_MM: |
| 8656 | case Mips::TNEI_MM: { |
| 8657 | switch (OpNum) { |
| 8658 | case 0: |
| 8659 | // op: rs |
| 8660 | return 16; |
| 8661 | case 1: |
| 8662 | // op: imm16 |
| 8663 | return 0; |
| 8664 | } |
| 8665 | break; |
| 8666 | } |
| 8667 | case Mips::BEQZC_MM: |
| 8668 | case Mips::BGEZALS_MM: |
| 8669 | case Mips::BGEZAL_MM: |
| 8670 | case Mips::BGEZ_MM: |
| 8671 | case Mips::BGTZ_MM: |
| 8672 | case Mips::BLEZ_MM: |
| 8673 | case Mips::BLTZALS_MM: |
| 8674 | case Mips::BLTZAL_MM: |
| 8675 | case Mips::BLTZ_MM: |
| 8676 | case Mips::BNEZC_MM: { |
| 8677 | switch (OpNum) { |
| 8678 | case 0: |
| 8679 | // op: rs |
| 8680 | return 16; |
| 8681 | case 1: |
| 8682 | // op: offset |
| 8683 | return 0; |
| 8684 | } |
| 8685 | break; |
| 8686 | } |
| 8687 | case Mips::TEQ_MM: |
| 8688 | case Mips::TGEU_MM: |
| 8689 | case Mips::TGE_MM: |
| 8690 | case Mips::TLTU_MM: |
| 8691 | case Mips::TLT_MM: |
| 8692 | case Mips::TNE_MM: { |
| 8693 | switch (OpNum) { |
| 8694 | case 0: |
| 8695 | // op: rs |
| 8696 | return 16; |
| 8697 | case 1: |
| 8698 | // op: rt |
| 8699 | return 21; |
| 8700 | case 2: |
| 8701 | // op: code_ |
| 8702 | return 12; |
| 8703 | } |
| 8704 | break; |
| 8705 | } |
| 8706 | case Mips::BEQ_MM: |
| 8707 | case Mips::BNE_MM: { |
| 8708 | switch (OpNum) { |
| 8709 | case 0: |
| 8710 | // op: rs |
| 8711 | return 16; |
| 8712 | case 1: |
| 8713 | // op: rt |
| 8714 | return 21; |
| 8715 | case 2: |
| 8716 | // op: offset |
| 8717 | return 0; |
| 8718 | } |
| 8719 | break; |
| 8720 | } |
| 8721 | case Mips::MADDU_MM: |
| 8722 | case Mips::MADD_MM: |
| 8723 | case Mips::MSUBU_MM: |
| 8724 | case Mips::MSUB_MM: |
| 8725 | case Mips::MULT_MM: |
| 8726 | case Mips::MULTu_MM: |
| 8727 | case Mips::SDIV_MM: |
| 8728 | case Mips::UDIV_MM: { |
| 8729 | switch (OpNum) { |
| 8730 | case 0: |
| 8731 | // op: rs |
| 8732 | return 16; |
| 8733 | case 1: |
| 8734 | // op: rt |
| 8735 | return 21; |
| 8736 | } |
| 8737 | break; |
| 8738 | } |
| 8739 | case Mips::GINVT_MMR6: { |
| 8740 | switch (OpNum) { |
| 8741 | case 0: |
| 8742 | // op: rs |
| 8743 | return 16; |
| 8744 | case 1: |
| 8745 | // op: type |
| 8746 | return 9; |
| 8747 | } |
| 8748 | break; |
| 8749 | } |
| 8750 | case Mips::DVP_MMR6: |
| 8751 | case Mips::EVP_MMR6: |
| 8752 | case Mips::GINVI_MMR6: |
| 8753 | case Mips::JR_HB_MM: |
| 8754 | case Mips::JR_MM: |
| 8755 | case Mips::MTHI_MM: |
| 8756 | case Mips::MTLO_MM: { |
| 8757 | switch (OpNum) { |
| 8758 | case 0: |
| 8759 | // op: rs |
| 8760 | return 16; |
| 8761 | } |
| 8762 | break; |
| 8763 | } |
| 8764 | case Mips::ADDIUPC: |
| 8765 | case Mips::ALUIPC: |
| 8766 | case Mips::AUIPC: |
| 8767 | case Mips::LDPC: |
| 8768 | case Mips::LWPC: |
| 8769 | case Mips::LWUPC: { |
| 8770 | switch (OpNum) { |
| 8771 | case 0: |
| 8772 | // op: rs |
| 8773 | return 21; |
| 8774 | case 1: |
| 8775 | // op: imm |
| 8776 | return 0; |
| 8777 | } |
| 8778 | break; |
| 8779 | } |
| 8780 | case Mips::TEQI: |
| 8781 | case Mips::TGEI: |
| 8782 | case Mips::TGEIU: |
| 8783 | case Mips::TLTI: |
| 8784 | case Mips::TNEI: |
| 8785 | case Mips::TTLTIU: { |
| 8786 | switch (OpNum) { |
| 8787 | case 0: |
| 8788 | // op: rs |
| 8789 | return 21; |
| 8790 | case 1: |
| 8791 | // op: imm16 |
| 8792 | return 0; |
| 8793 | } |
| 8794 | break; |
| 8795 | } |
| 8796 | case Mips::WRDSP: { |
| 8797 | switch (OpNum) { |
| 8798 | case 0: |
| 8799 | // op: rs |
| 8800 | return 21; |
| 8801 | case 1: |
| 8802 | // op: mask |
| 8803 | return 11; |
| 8804 | } |
| 8805 | break; |
| 8806 | } |
| 8807 | case Mips::BEQZC: |
| 8808 | case Mips::BEQZC64: |
| 8809 | case Mips::BEQZC_MMR6: |
| 8810 | case Mips::BGEZ: |
| 8811 | case Mips::BGEZ64: |
| 8812 | case Mips::BGEZAL: |
| 8813 | case Mips::BGEZALL: |
| 8814 | case Mips::BGEZL: |
| 8815 | case Mips::BGTZ: |
| 8816 | case Mips::BGTZ64: |
| 8817 | case Mips::BGTZL: |
| 8818 | case Mips::BLEZ: |
| 8819 | case Mips::BLEZ64: |
| 8820 | case Mips::BLEZL: |
| 8821 | case Mips::BLTZ: |
| 8822 | case Mips::BLTZ64: |
| 8823 | case Mips::BLTZAL: |
| 8824 | case Mips::BLTZALL: |
| 8825 | case Mips::BLTZL: |
| 8826 | case Mips::BNEZC: |
| 8827 | case Mips::BNEZC64: |
| 8828 | case Mips::BNEZC_MMR6: { |
| 8829 | switch (OpNum) { |
| 8830 | case 0: |
| 8831 | // op: rs |
| 8832 | return 21; |
| 8833 | case 1: |
| 8834 | // op: offset |
| 8835 | return 0; |
| 8836 | } |
| 8837 | break; |
| 8838 | } |
| 8839 | case Mips::BBIT0: |
| 8840 | case Mips::BBIT032: |
| 8841 | case Mips::BBIT1: |
| 8842 | case Mips::BBIT132: { |
| 8843 | switch (OpNum) { |
| 8844 | case 0: |
| 8845 | // op: rs |
| 8846 | return 21; |
| 8847 | case 1: |
| 8848 | // op: p |
| 8849 | return 16; |
| 8850 | case 2: |
| 8851 | // op: offset |
| 8852 | return 0; |
| 8853 | } |
| 8854 | break; |
| 8855 | } |
| 8856 | case Mips::TEQ: |
| 8857 | case Mips::TGE: |
| 8858 | case Mips::TGEU: |
| 8859 | case Mips::TLT: |
| 8860 | case Mips::TLTU: |
| 8861 | case Mips::TNE: { |
| 8862 | switch (OpNum) { |
| 8863 | case 0: |
| 8864 | // op: rs |
| 8865 | return 21; |
| 8866 | case 1: |
| 8867 | // op: rt |
| 8868 | return 16; |
| 8869 | case 2: |
| 8870 | // op: code_ |
| 8871 | return 6; |
| 8872 | } |
| 8873 | break; |
| 8874 | } |
| 8875 | case Mips::BEQ: |
| 8876 | case Mips::BEQ64: |
| 8877 | case Mips::BEQC: |
| 8878 | case Mips::BEQC64: |
| 8879 | case Mips::BEQL: |
| 8880 | case Mips::BGEC: |
| 8881 | case Mips::BGEC64: |
| 8882 | case Mips::BGEUC: |
| 8883 | case Mips::BGEUC64: |
| 8884 | case Mips::BLTC: |
| 8885 | case Mips::BLTC64: |
| 8886 | case Mips::BLTUC: |
| 8887 | case Mips::BLTUC64: |
| 8888 | case Mips::BNE: |
| 8889 | case Mips::BNE64: |
| 8890 | case Mips::BNEC: |
| 8891 | case Mips::BNEC64: |
| 8892 | case Mips::BNEL: |
| 8893 | case Mips::BNVC: |
| 8894 | case Mips::BOVC: { |
| 8895 | switch (OpNum) { |
| 8896 | case 0: |
| 8897 | // op: rs |
| 8898 | return 21; |
| 8899 | case 1: |
| 8900 | // op: rt |
| 8901 | return 16; |
| 8902 | case 2: |
| 8903 | // op: offset |
| 8904 | return 0; |
| 8905 | } |
| 8906 | break; |
| 8907 | } |
| 8908 | case Mips::CMPU_EQ_QB: |
| 8909 | case Mips::CMPU_LE_QB: |
| 8910 | case Mips::CMPU_LT_QB: |
| 8911 | case Mips::CMP_EQ_PH: |
| 8912 | case Mips::CMP_LE_PH: |
| 8913 | case Mips::CMP_LT_PH: |
| 8914 | case Mips::DMULT: |
| 8915 | case Mips::DMULTu: |
| 8916 | case Mips::DSDIV: |
| 8917 | case Mips::DUDIV: |
| 8918 | case Mips::MADD: |
| 8919 | case Mips::MADDU: |
| 8920 | case Mips::MSUB: |
| 8921 | case Mips::MSUBU: |
| 8922 | case Mips::MULT: |
| 8923 | case Mips::MULTu: |
| 8924 | case Mips::SDIV: |
| 8925 | case Mips::UDIV: { |
| 8926 | switch (OpNum) { |
| 8927 | case 0: |
| 8928 | // op: rs |
| 8929 | return 21; |
| 8930 | case 1: |
| 8931 | // op: rt |
| 8932 | return 16; |
| 8933 | } |
| 8934 | break; |
| 8935 | } |
| 8936 | case Mips::GINVT: { |
| 8937 | switch (OpNum) { |
| 8938 | case 0: |
| 8939 | // op: rs |
| 8940 | return 21; |
| 8941 | case 1: |
| 8942 | // op: type_ |
| 8943 | return 8; |
| 8944 | } |
| 8945 | break; |
| 8946 | } |
| 8947 | case Mips::DAHI: |
| 8948 | case Mips::DATI: { |
| 8949 | switch (OpNum) { |
| 8950 | case 0: |
| 8951 | // op: rs |
| 8952 | return 21; |
| 8953 | case 2: |
| 8954 | // op: imm |
| 8955 | return 0; |
| 8956 | } |
| 8957 | break; |
| 8958 | } |
| 8959 | case Mips::FORK: { |
| 8960 | switch (OpNum) { |
| 8961 | case 0: |
| 8962 | // op: rs |
| 8963 | return 21; |
| 8964 | case 2: |
| 8965 | // op: rt |
| 8966 | return 16; |
| 8967 | case 1: |
| 8968 | // op: rd |
| 8969 | return 11; |
| 8970 | } |
| 8971 | break; |
| 8972 | } |
| 8973 | case Mips::GINVI: |
| 8974 | case Mips::JR: |
| 8975 | case Mips::JR64: |
| 8976 | case Mips::JR_HB: |
| 8977 | case Mips::JR_HB64: |
| 8978 | case Mips::JR_HB64_R6: |
| 8979 | case Mips::JR_HB_R6: |
| 8980 | case Mips::MTHI: |
| 8981 | case Mips::MTHI64: |
| 8982 | case Mips::MTLO: |
| 8983 | case Mips::MTLO64: |
| 8984 | case Mips::MTM0: |
| 8985 | case Mips::MTM1: |
| 8986 | case Mips::MTM2: |
| 8987 | case Mips::MTP0: |
| 8988 | case Mips::MTP1: |
| 8989 | case Mips::MTP2: { |
| 8990 | switch (OpNum) { |
| 8991 | case 0: |
| 8992 | // op: rs |
| 8993 | return 21; |
| 8994 | } |
| 8995 | break; |
| 8996 | } |
| 8997 | case Mips::ADDIUPC_MM: { |
| 8998 | switch (OpNum) { |
| 8999 | case 0: |
| 9000 | // op: rs |
| 9001 | return 23; |
| 9002 | case 1: |
| 9003 | // op: imm |
| 9004 | return 0; |
| 9005 | } |
| 9006 | break; |
| 9007 | } |
| 9008 | case Mips::JALRC16_MMR6: |
| 9009 | case Mips::JRC16_MMR6: { |
| 9010 | switch (OpNum) { |
| 9011 | case 0: |
| 9012 | // op: rs |
| 9013 | return 5; |
| 9014 | } |
| 9015 | break; |
| 9016 | } |
| 9017 | case Mips::BEQZ16_MM: |
| 9018 | case Mips::BEQZC16_MMR6: |
| 9019 | case Mips::BNEZ16_MM: |
| 9020 | case Mips::BNEZC16_MMR6: { |
| 9021 | switch (OpNum) { |
| 9022 | case 0: |
| 9023 | // op: rs |
| 9024 | return 7; |
| 9025 | case 1: |
| 9026 | // op: offset |
| 9027 | return 0; |
| 9028 | } |
| 9029 | break; |
| 9030 | } |
| 9031 | case Mips::EXTP: |
| 9032 | case Mips::EXTPDP: |
| 9033 | case Mips::EXTPDPV: |
| 9034 | case Mips::EXTPV: |
| 9035 | case Mips::EXTRV_RS_W: |
| 9036 | case Mips::EXTRV_R_W: |
| 9037 | case Mips::EXTRV_S_H: |
| 9038 | case Mips::EXTRV_W: |
| 9039 | case Mips::EXTR_RS_W: |
| 9040 | case Mips::EXTR_R_W: |
| 9041 | case Mips::EXTR_S_H: |
| 9042 | case Mips::EXTR_W: { |
| 9043 | switch (OpNum) { |
| 9044 | case 0: |
| 9045 | // op: rt |
| 9046 | return 16; |
| 9047 | case 1: |
| 9048 | // op: ac |
| 9049 | return 11; |
| 9050 | case 2: |
| 9051 | // op: shift_rs |
| 9052 | return 21; |
| 9053 | } |
| 9054 | break; |
| 9055 | } |
| 9056 | case Mips::LB: |
| 9057 | case Mips::LB64: |
| 9058 | case Mips::LBu: |
| 9059 | case Mips::LBu64: |
| 9060 | case Mips::LD: |
| 9061 | case Mips::LDC1: |
| 9062 | case Mips::LDC164: |
| 9063 | case Mips::LDC2: |
| 9064 | case Mips::LDC2_R6: |
| 9065 | case Mips::LDC3: |
| 9066 | case Mips::LDL: |
| 9067 | case Mips::LDR: |
| 9068 | case Mips::LEA_ADDiu: |
| 9069 | case Mips::LEA_ADDiu64: |
| 9070 | case Mips::LH: |
| 9071 | case Mips::LH64: |
| 9072 | case Mips::LHu: |
| 9073 | case Mips::LHu64: |
| 9074 | case Mips::LL: |
| 9075 | case Mips::LL64: |
| 9076 | case Mips::LLD: |
| 9077 | case Mips::LW: |
| 9078 | case Mips::LW64: |
| 9079 | case Mips::LWC1: |
| 9080 | case Mips::LWC2: |
| 9081 | case Mips::LWC2_R6: |
| 9082 | case Mips::LWC3: |
| 9083 | case Mips::LWDSP: |
| 9084 | case Mips::LWL: |
| 9085 | case Mips::LWL64: |
| 9086 | case Mips::LWR: |
| 9087 | case Mips::LWR64: |
| 9088 | case Mips::LWu: |
| 9089 | case Mips::SB: |
| 9090 | case Mips::SB64: |
| 9091 | case Mips::SD: |
| 9092 | case Mips::SDC1: |
| 9093 | case Mips::SDC164: |
| 9094 | case Mips::SDC2: |
| 9095 | case Mips::SDC2_R6: |
| 9096 | case Mips::SDC3: |
| 9097 | case Mips::SDL: |
| 9098 | case Mips::SDR: |
| 9099 | case Mips::SH: |
| 9100 | case Mips::SH64: |
| 9101 | case Mips::SW: |
| 9102 | case Mips::SW64: |
| 9103 | case Mips::SWC1: |
| 9104 | case Mips::SWC2: |
| 9105 | case Mips::SWC2_R6: |
| 9106 | case Mips::SWC3: |
| 9107 | case Mips::SWDSP: |
| 9108 | case Mips::SWL: |
| 9109 | case Mips::SWL64: |
| 9110 | case Mips::SWR: |
| 9111 | case Mips::SWR64: { |
| 9112 | switch (OpNum) { |
| 9113 | case 0: |
| 9114 | // op: rt |
| 9115 | return 16; |
| 9116 | case 1: |
| 9117 | // op: addr |
| 9118 | return 0; |
| 9119 | } |
| 9120 | break; |
| 9121 | } |
| 9122 | case Mips::LL64_R6: |
| 9123 | case Mips::LLD_R6: |
| 9124 | case Mips::LL_R6: { |
| 9125 | switch (OpNum) { |
| 9126 | case 0: |
| 9127 | // op: rt |
| 9128 | return 16; |
| 9129 | case 1: |
| 9130 | // op: addr |
| 9131 | return 7; |
| 9132 | } |
| 9133 | break; |
| 9134 | } |
| 9135 | case Mips::CFC1: |
| 9136 | case Mips::DMFC1: |
| 9137 | case Mips::MFC1: |
| 9138 | case Mips::MFC1_D64: |
| 9139 | case Mips::MFHC1_D32: |
| 9140 | case Mips::MFHC1_D64: { |
| 9141 | switch (OpNum) { |
| 9142 | case 0: |
| 9143 | // op: rt |
| 9144 | return 16; |
| 9145 | case 1: |
| 9146 | // op: fs |
| 9147 | return 11; |
| 9148 | } |
| 9149 | break; |
| 9150 | } |
| 9151 | case Mips::DMFC2_OCTEON: |
| 9152 | case Mips::DMTC2_OCTEON: |
| 9153 | case Mips::LUi: |
| 9154 | case Mips::LUi64: |
| 9155 | case Mips::LUi_MM: { |
| 9156 | switch (OpNum) { |
| 9157 | case 0: |
| 9158 | // op: rt |
| 9159 | return 16; |
| 9160 | case 1: |
| 9161 | // op: imm16 |
| 9162 | return 0; |
| 9163 | } |
| 9164 | break; |
| 9165 | } |
| 9166 | case Mips::BC1EQZC_MMR6: |
| 9167 | case Mips::BC1NEZC_MMR6: |
| 9168 | case Mips::BC2EQZC_MMR6: |
| 9169 | case Mips::BC2NEZC_MMR6: |
| 9170 | case Mips::BEQZALC: |
| 9171 | case Mips::BGEZALC: |
| 9172 | case Mips::BGEZALC_MMR6: |
| 9173 | case Mips::BGEZC: |
| 9174 | case Mips::BGEZC64: |
| 9175 | case Mips::BGEZC_MMR6: |
| 9176 | case Mips::BGTZALC: |
| 9177 | case Mips::BGTZC: |
| 9178 | case Mips::BGTZC64: |
| 9179 | case Mips::BLEZALC: |
| 9180 | case Mips::BLEZC: |
| 9181 | case Mips::BLEZC64: |
| 9182 | case Mips::BLTZALC: |
| 9183 | case Mips::BLTZALC_MMR6: |
| 9184 | case Mips::BLTZC: |
| 9185 | case Mips::BLTZC64: |
| 9186 | case Mips::BLTZC_MMR6: |
| 9187 | case Mips::BNEZALC: |
| 9188 | case Mips::JIALC: |
| 9189 | case Mips::JIALC64: |
| 9190 | case Mips::JIALC_MMR6: |
| 9191 | case Mips::JIC: |
| 9192 | case Mips::JIC64: |
| 9193 | case Mips::JIC_MMR6: { |
| 9194 | switch (OpNum) { |
| 9195 | case 0: |
| 9196 | // op: rt |
| 9197 | return 16; |
| 9198 | case 1: |
| 9199 | // op: offset |
| 9200 | return 0; |
| 9201 | } |
| 9202 | break; |
| 9203 | } |
| 9204 | case Mips::DMFC0: |
| 9205 | case Mips::DMFC2: |
| 9206 | case Mips::DMFGC0: |
| 9207 | case Mips::MFC0: |
| 9208 | case Mips::MFC2: |
| 9209 | case Mips::MFGC0: |
| 9210 | case Mips::MFHGC0: { |
| 9211 | switch (OpNum) { |
| 9212 | case 0: |
| 9213 | // op: rt |
| 9214 | return 16; |
| 9215 | case 1: |
| 9216 | // op: rd |
| 9217 | return 11; |
| 9218 | case 2: |
| 9219 | // op: sel |
| 9220 | return 0; |
| 9221 | } |
| 9222 | break; |
| 9223 | } |
| 9224 | case Mips::RDHWR: |
| 9225 | case Mips::RDHWR64: { |
| 9226 | switch (OpNum) { |
| 9227 | case 0: |
| 9228 | // op: rt |
| 9229 | return 16; |
| 9230 | case 1: |
| 9231 | // op: rd |
| 9232 | return 11; |
| 9233 | case 2: |
| 9234 | // op: sel |
| 9235 | return 6; |
| 9236 | } |
| 9237 | break; |
| 9238 | } |
| 9239 | case Mips::SLTi: |
| 9240 | case Mips::SLTi64: |
| 9241 | case Mips::SLTiu: |
| 9242 | case Mips::SLTiu64: { |
| 9243 | switch (OpNum) { |
| 9244 | case 0: |
| 9245 | // op: rt |
| 9246 | return 16; |
| 9247 | case 1: |
| 9248 | // op: rs |
| 9249 | return 21; |
| 9250 | case 2: |
| 9251 | // op: imm16 |
| 9252 | return 0; |
| 9253 | } |
| 9254 | break; |
| 9255 | } |
| 9256 | case Mips::CINS: |
| 9257 | case Mips::CINS32: |
| 9258 | case Mips::CINS64_32: |
| 9259 | case Mips::CINS_i32: |
| 9260 | case Mips::EXTS: |
| 9261 | case Mips::EXTS32: { |
| 9262 | switch (OpNum) { |
| 9263 | case 0: |
| 9264 | // op: rt |
| 9265 | return 16; |
| 9266 | case 1: |
| 9267 | // op: rs |
| 9268 | return 21; |
| 9269 | case 2: |
| 9270 | // op: pos |
| 9271 | return 6; |
| 9272 | case 3: |
| 9273 | // op: lenm1 |
| 9274 | return 11; |
| 9275 | } |
| 9276 | break; |
| 9277 | } |
| 9278 | case Mips::DEXT: |
| 9279 | case Mips::DEXT64_32: |
| 9280 | case Mips::DEXTM: |
| 9281 | case Mips::DEXTU: |
| 9282 | case Mips::DINS: |
| 9283 | case Mips::DINSM: |
| 9284 | case Mips::DINSU: |
| 9285 | case Mips::EXT: |
| 9286 | case Mips::INS: { |
| 9287 | switch (OpNum) { |
| 9288 | case 0: |
| 9289 | // op: rt |
| 9290 | return 16; |
| 9291 | case 1: |
| 9292 | // op: rs |
| 9293 | return 21; |
| 9294 | case 2: |
| 9295 | // op: pos |
| 9296 | return 6; |
| 9297 | case 3: |
| 9298 | // op: size |
| 9299 | return 11; |
| 9300 | } |
| 9301 | break; |
| 9302 | } |
| 9303 | case Mips::APPEND: |
| 9304 | case Mips::BALIGN: |
| 9305 | case Mips::PREPEND: { |
| 9306 | switch (OpNum) { |
| 9307 | case 0: |
| 9308 | // op: rt |
| 9309 | return 16; |
| 9310 | case 1: |
| 9311 | // op: rs |
| 9312 | return 21; |
| 9313 | case 2: |
| 9314 | // op: sa |
| 9315 | return 11; |
| 9316 | } |
| 9317 | break; |
| 9318 | } |
| 9319 | case Mips::SAA: |
| 9320 | case Mips::SAAD: { |
| 9321 | switch (OpNum) { |
| 9322 | case 0: |
| 9323 | // op: rt |
| 9324 | return 16; |
| 9325 | case 1: |
| 9326 | // op: rs |
| 9327 | return 21; |
| 9328 | } |
| 9329 | break; |
| 9330 | } |
| 9331 | case Mips::INSV: { |
| 9332 | switch (OpNum) { |
| 9333 | case 0: |
| 9334 | // op: rt |
| 9335 | return 16; |
| 9336 | case 2: |
| 9337 | // op: rs |
| 9338 | return 21; |
| 9339 | } |
| 9340 | break; |
| 9341 | } |
| 9342 | case Mips::DI: |
| 9343 | case Mips::DI_MM: |
| 9344 | case Mips::DI_MMR6: |
| 9345 | case Mips::DMT: |
| 9346 | case Mips::DVP: |
| 9347 | case Mips::DVPE: |
| 9348 | case Mips::EI: |
| 9349 | case Mips::EI_MM: |
| 9350 | case Mips::EI_MMR6: |
| 9351 | case Mips::EMT: |
| 9352 | case Mips::EVP: |
| 9353 | case Mips::EVPE: { |
| 9354 | switch (OpNum) { |
| 9355 | case 0: |
| 9356 | // op: rt |
| 9357 | return 16; |
| 9358 | } |
| 9359 | break; |
| 9360 | } |
| 9361 | case Mips::LBE_MM: |
| 9362 | case Mips::LB_MM: |
| 9363 | case Mips::LBuE_MM: |
| 9364 | case Mips::LBu_MM: |
| 9365 | case Mips::LDC1_MM_D32: |
| 9366 | case Mips::LDC1_MM_D64: |
| 9367 | case Mips::LDC2_MMR6: |
| 9368 | case Mips::LEA_ADDiu_MM: |
| 9369 | case Mips::LHE_MM: |
| 9370 | case Mips::LH_MM: |
| 9371 | case Mips::LHuE_MM: |
| 9372 | case Mips::LHu_MM: |
| 9373 | case Mips::LLE_MM: |
| 9374 | case Mips::LL_MM: |
| 9375 | case Mips::LL_MMR6: |
| 9376 | case Mips::LWC1_MM: |
| 9377 | case Mips::LWC2_MMR6: |
| 9378 | case Mips::LWDSP_MM: |
| 9379 | case Mips::LWE_MM: |
| 9380 | case Mips::LWLE_MM: |
| 9381 | case Mips::LWL_MM: |
| 9382 | case Mips::LWM32_MM: |
| 9383 | case Mips::LWRE_MM: |
| 9384 | case Mips::LWR_MM: |
| 9385 | case Mips::LWU_MM: |
| 9386 | case Mips::LW_MM: |
| 9387 | case Mips::LW_MMR6: |
| 9388 | case Mips::SBE_MM: |
| 9389 | case Mips::SB_MM: |
| 9390 | case Mips::SB_MMR6: |
| 9391 | case Mips::SDC1_MM_D32: |
| 9392 | case Mips::SDC1_MM_D64: |
| 9393 | case Mips::SDC2_MMR6: |
| 9394 | case Mips::SHE_MM: |
| 9395 | case Mips::SH_MM: |
| 9396 | case Mips::SH_MMR6: |
| 9397 | case Mips::SWC1_MM: |
| 9398 | case Mips::SWC2_MMR6: |
| 9399 | case Mips::SWDSP_MM: |
| 9400 | case Mips::SWE_MM: |
| 9401 | case Mips::SWLE_MM: |
| 9402 | case Mips::SWL_MM: |
| 9403 | case Mips::SWM32_MM: |
| 9404 | case Mips::SWRE_MM: |
| 9405 | case Mips::SWR_MM: |
| 9406 | case Mips::SW_MM: |
| 9407 | case Mips::SW_MMR6: { |
| 9408 | switch (OpNum) { |
| 9409 | case 0: |
| 9410 | // op: rt |
| 9411 | return 21; |
| 9412 | case 1: |
| 9413 | // op: addr |
| 9414 | return 0; |
| 9415 | } |
| 9416 | break; |
| 9417 | } |
| 9418 | case Mips::CFC1_MM: |
| 9419 | case Mips::MFC1_MM: |
| 9420 | case Mips::MFC1_MMR6: |
| 9421 | case Mips::MFHC1_D32_MM: |
| 9422 | case Mips::MFHC1_D64_MM: { |
| 9423 | switch (OpNum) { |
| 9424 | case 0: |
| 9425 | // op: rt |
| 9426 | return 21; |
| 9427 | case 1: |
| 9428 | // op: fs |
| 9429 | return 16; |
| 9430 | } |
| 9431 | break; |
| 9432 | } |
| 9433 | case Mips::ADDIUPC_MMR6: |
| 9434 | case Mips::ALUIPC_MMR6: |
| 9435 | case Mips::AUIPC_MMR6: |
| 9436 | case Mips::LWPC_MMR6: { |
| 9437 | switch (OpNum) { |
| 9438 | case 0: |
| 9439 | // op: rt |
| 9440 | return 21; |
| 9441 | case 1: |
| 9442 | // op: imm |
| 9443 | return 0; |
| 9444 | } |
| 9445 | break; |
| 9446 | } |
| 9447 | case Mips::REPL_QB_MM: { |
| 9448 | switch (OpNum) { |
| 9449 | case 0: |
| 9450 | // op: rt |
| 9451 | return 21; |
| 9452 | case 1: |
| 9453 | // op: imm |
| 9454 | return 13; |
| 9455 | } |
| 9456 | break; |
| 9457 | } |
| 9458 | case Mips::LUI_MMR6: { |
| 9459 | switch (OpNum) { |
| 9460 | case 0: |
| 9461 | // op: rt |
| 9462 | return 21; |
| 9463 | case 1: |
| 9464 | // op: imm16 |
| 9465 | return 0; |
| 9466 | } |
| 9467 | break; |
| 9468 | } |
| 9469 | case Mips::CFC2_MM: |
| 9470 | case Mips::MFC2_MMR6: |
| 9471 | case Mips::MFHC2_MMR6: { |
| 9472 | switch (OpNum) { |
| 9473 | case 0: |
| 9474 | // op: rt |
| 9475 | return 21; |
| 9476 | case 1: |
| 9477 | // op: impl |
| 9478 | return 16; |
| 9479 | } |
| 9480 | break; |
| 9481 | } |
| 9482 | case Mips::RDDSP_MM: |
| 9483 | case Mips::WRDSP_MM: { |
| 9484 | switch (OpNum) { |
| 9485 | case 0: |
| 9486 | // op: rt |
| 9487 | return 21; |
| 9488 | case 1: |
| 9489 | // op: mask |
| 9490 | return 14; |
| 9491 | } |
| 9492 | break; |
| 9493 | } |
| 9494 | case Mips::BEQZALC_MMR6: |
| 9495 | case Mips::BGTZALC_MMR6: |
| 9496 | case Mips::BGTZC_MMR6: |
| 9497 | case Mips::BLEZALC_MMR6: |
| 9498 | case Mips::BLEZC_MMR6: |
| 9499 | case Mips::BNEZALC_MMR6: { |
| 9500 | switch (OpNum) { |
| 9501 | case 0: |
| 9502 | // op: rt |
| 9503 | return 21; |
| 9504 | case 1: |
| 9505 | // op: offset |
| 9506 | return 0; |
| 9507 | } |
| 9508 | break; |
| 9509 | } |
| 9510 | case Mips::MFC0_MM: { |
| 9511 | switch (OpNum) { |
| 9512 | case 0: |
| 9513 | // op: rt |
| 9514 | return 21; |
| 9515 | case 1: |
| 9516 | // op: rd |
| 9517 | return 16; |
| 9518 | case 2: |
| 9519 | // op: sel |
| 9520 | return 11; |
| 9521 | } |
| 9522 | break; |
| 9523 | } |
| 9524 | case Mips::RDHWR_MM: |
| 9525 | case Mips::RDPGPR_MMR6: { |
| 9526 | switch (OpNum) { |
| 9527 | case 0: |
| 9528 | // op: rt |
| 9529 | return 21; |
| 9530 | case 1: |
| 9531 | // op: rd |
| 9532 | return 16; |
| 9533 | } |
| 9534 | break; |
| 9535 | } |
| 9536 | case Mips::BALIGN_MMR2: { |
| 9537 | switch (OpNum) { |
| 9538 | case 0: |
| 9539 | // op: rt |
| 9540 | return 21; |
| 9541 | case 1: |
| 9542 | // op: rs |
| 9543 | return 16; |
| 9544 | case 2: |
| 9545 | // op: bp |
| 9546 | return 14; |
| 9547 | } |
| 9548 | break; |
| 9549 | } |
| 9550 | case Mips::ADDIU_MMR6: |
| 9551 | case Mips::ANDI_MMR6: |
| 9552 | case Mips::ORI_MMR6: |
| 9553 | case Mips::SLTi_MM: |
| 9554 | case Mips::SLTiu_MM: |
| 9555 | case Mips::XORI_MMR6: { |
| 9556 | switch (OpNum) { |
| 9557 | case 0: |
| 9558 | // op: rt |
| 9559 | return 21; |
| 9560 | case 1: |
| 9561 | // op: rs |
| 9562 | return 16; |
| 9563 | case 2: |
| 9564 | // op: imm16 |
| 9565 | return 0; |
| 9566 | } |
| 9567 | break; |
| 9568 | } |
| 9569 | case Mips::BNVC_MMR6: |
| 9570 | case Mips::BOVC_MMR6: { |
| 9571 | switch (OpNum) { |
| 9572 | case 0: |
| 9573 | // op: rt |
| 9574 | return 21; |
| 9575 | case 1: |
| 9576 | // op: rs |
| 9577 | return 16; |
| 9578 | case 2: |
| 9579 | // op: offset |
| 9580 | return 0; |
| 9581 | } |
| 9582 | break; |
| 9583 | } |
| 9584 | case Mips::EXT_MM: |
| 9585 | case Mips::INS_MM: { |
| 9586 | switch (OpNum) { |
| 9587 | case 0: |
| 9588 | // op: rt |
| 9589 | return 21; |
| 9590 | case 1: |
| 9591 | // op: rs |
| 9592 | return 16; |
| 9593 | case 2: |
| 9594 | // op: pos |
| 9595 | return 6; |
| 9596 | case 3: |
| 9597 | // op: size |
| 9598 | return 11; |
| 9599 | } |
| 9600 | break; |
| 9601 | } |
| 9602 | case Mips::APPEND_MMR2: |
| 9603 | case Mips::PRECR_SRA_PH_W_MMR2: |
| 9604 | case Mips::PRECR_SRA_R_PH_W_MMR2: |
| 9605 | case Mips::PREPEND_MMR2: |
| 9606 | case Mips::SHLL_S_W_MM: |
| 9607 | case Mips::SHRA_R_W_MM: { |
| 9608 | switch (OpNum) { |
| 9609 | case 0: |
| 9610 | // op: rt |
| 9611 | return 21; |
| 9612 | case 1: |
| 9613 | // op: rs |
| 9614 | return 16; |
| 9615 | case 2: |
| 9616 | // op: sa |
| 9617 | return 11; |
| 9618 | } |
| 9619 | break; |
| 9620 | } |
| 9621 | case Mips::SHLL_PH_MM: |
| 9622 | case Mips::SHLL_S_PH_MM: |
| 9623 | case Mips::SHRA_PH_MM: |
| 9624 | case Mips::SHRA_R_PH_MM: |
| 9625 | case Mips::SHRL_PH_MMR2: { |
| 9626 | switch (OpNum) { |
| 9627 | case 0: |
| 9628 | // op: rt |
| 9629 | return 21; |
| 9630 | case 1: |
| 9631 | // op: rs |
| 9632 | return 16; |
| 9633 | case 2: |
| 9634 | // op: sa |
| 9635 | return 12; |
| 9636 | } |
| 9637 | break; |
| 9638 | } |
| 9639 | case Mips::SHLL_QB_MM: |
| 9640 | case Mips::SHRA_QB_MMR2: |
| 9641 | case Mips::SHRA_R_QB_MMR2: |
| 9642 | case Mips::SHRL_QB_MM: { |
| 9643 | switch (OpNum) { |
| 9644 | case 0: |
| 9645 | // op: rt |
| 9646 | return 21; |
| 9647 | case 1: |
| 9648 | // op: rs |
| 9649 | return 16; |
| 9650 | case 2: |
| 9651 | // op: sa |
| 9652 | return 13; |
| 9653 | } |
| 9654 | break; |
| 9655 | } |
| 9656 | case Mips::MFC0_MMR6: |
| 9657 | case Mips::MFGC0_MM: |
| 9658 | case Mips::MFHC0_MMR6: |
| 9659 | case Mips::MFHGC0_MM: |
| 9660 | case Mips::RDHWR_MMR6: { |
| 9661 | switch (OpNum) { |
| 9662 | case 0: |
| 9663 | // op: rt |
| 9664 | return 21; |
| 9665 | case 1: |
| 9666 | // op: rs |
| 9667 | return 16; |
| 9668 | case 2: |
| 9669 | // op: sel |
| 9670 | return 11; |
| 9671 | } |
| 9672 | break; |
| 9673 | } |
| 9674 | case Mips::EXT_MMR6: |
| 9675 | case Mips::INS_MMR6: { |
| 9676 | switch (OpNum) { |
| 9677 | case 0: |
| 9678 | // op: rt |
| 9679 | return 21; |
| 9680 | case 1: |
| 9681 | // op: rs |
| 9682 | return 16; |
| 9683 | case 3: |
| 9684 | // op: size |
| 9685 | return 11; |
| 9686 | case 2: |
| 9687 | // op: pos |
| 9688 | return 6; |
| 9689 | } |
| 9690 | break; |
| 9691 | } |
| 9692 | case Mips::ABSQ_S_PH_MM: |
| 9693 | case Mips::ABSQ_S_QB_MMR2: |
| 9694 | case Mips::ABSQ_S_W_MM: |
| 9695 | case Mips::BITREV_MM: |
| 9696 | case Mips::JALRC_HB_MMR6: |
| 9697 | case Mips::JALRC_MMR6: |
| 9698 | case Mips::PRECEQU_PH_QBLA_MM: |
| 9699 | case Mips::PRECEQU_PH_QBL_MM: |
| 9700 | case Mips::PRECEQU_PH_QBRA_MM: |
| 9701 | case Mips::PRECEQU_PH_QBR_MM: |
| 9702 | case Mips::PRECEQ_W_PHL_MM: |
| 9703 | case Mips::PRECEQ_W_PHR_MM: |
| 9704 | case Mips::PRECEU_PH_QBLA_MM: |
| 9705 | case Mips::PRECEU_PH_QBL_MM: |
| 9706 | case Mips::PRECEU_PH_QBRA_MM: |
| 9707 | case Mips::PRECEU_PH_QBR_MM: |
| 9708 | case Mips::RADDU_W_QB_MM: |
| 9709 | case Mips::REPLV_PH_MM: |
| 9710 | case Mips::REPLV_QB_MM: |
| 9711 | case Mips::WRPGPR_MMR6: |
| 9712 | case Mips::WSBH_MMR6: { |
| 9713 | switch (OpNum) { |
| 9714 | case 0: |
| 9715 | // op: rt |
| 9716 | return 21; |
| 9717 | case 1: |
| 9718 | // op: rs |
| 9719 | return 16; |
| 9720 | } |
| 9721 | break; |
| 9722 | } |
| 9723 | case Mips::LWP_MM: |
| 9724 | case Mips::SWP_MM: { |
| 9725 | switch (OpNum) { |
| 9726 | case 0: |
| 9727 | // op: rt |
| 9728 | return 21; |
| 9729 | case 2: |
| 9730 | // op: addr |
| 9731 | return 0; |
| 9732 | } |
| 9733 | break; |
| 9734 | } |
| 9735 | case Mips::EXTPDP_MM: |
| 9736 | case Mips::EXTP_MM: |
| 9737 | case Mips::EXTR_RS_W_MM: |
| 9738 | case Mips::EXTR_R_W_MM: |
| 9739 | case Mips::EXTR_S_H_MM: |
| 9740 | case Mips::EXTR_W_MM: { |
| 9741 | switch (OpNum) { |
| 9742 | case 0: |
| 9743 | // op: rt |
| 9744 | return 21; |
| 9745 | case 2: |
| 9746 | // op: imm |
| 9747 | return 16; |
| 9748 | case 1: |
| 9749 | // op: ac |
| 9750 | return 14; |
| 9751 | } |
| 9752 | break; |
| 9753 | } |
| 9754 | case Mips::EXTPDPV_MM: |
| 9755 | case Mips::EXTPV_MM: |
| 9756 | case Mips::EXTRV_RS_W_MM: |
| 9757 | case Mips::EXTRV_R_W_MM: |
| 9758 | case Mips::EXTRV_S_H_MM: |
| 9759 | case Mips::EXTRV_W_MM: { |
| 9760 | switch (OpNum) { |
| 9761 | case 0: |
| 9762 | // op: rt |
| 9763 | return 21; |
| 9764 | case 2: |
| 9765 | // op: rs |
| 9766 | return 16; |
| 9767 | case 1: |
| 9768 | // op: ac |
| 9769 | return 14; |
| 9770 | } |
| 9771 | break; |
| 9772 | } |
| 9773 | case Mips::INSV_MM: { |
| 9774 | switch (OpNum) { |
| 9775 | case 0: |
| 9776 | // op: rt |
| 9777 | return 21; |
| 9778 | case 2: |
| 9779 | // op: rs |
| 9780 | return 16; |
| 9781 | } |
| 9782 | break; |
| 9783 | } |
| 9784 | case Mips::NOT16_MM: { |
| 9785 | switch (OpNum) { |
| 9786 | case 0: |
| 9787 | // op: rt |
| 9788 | return 3; |
| 9789 | case 1: |
| 9790 | // op: rs |
| 9791 | return 0; |
| 9792 | } |
| 9793 | break; |
| 9794 | } |
| 9795 | case Mips::LWM16_MM: |
| 9796 | case Mips::SWM16_MM: { |
| 9797 | switch (OpNum) { |
| 9798 | case 0: |
| 9799 | // op: rt |
| 9800 | return 4; |
| 9801 | case 1: |
| 9802 | // op: addr |
| 9803 | return 0; |
| 9804 | } |
| 9805 | break; |
| 9806 | } |
| 9807 | case Mips::LWSP_MM: |
| 9808 | case Mips::SWSP_MM: |
| 9809 | case Mips::SWSP_MMR6: { |
| 9810 | switch (OpNum) { |
| 9811 | case 0: |
| 9812 | // op: rt |
| 9813 | return 5; |
| 9814 | case 1: |
| 9815 | // op: offset |
| 9816 | return 0; |
| 9817 | } |
| 9818 | break; |
| 9819 | } |
| 9820 | case Mips::LBU16_MM: |
| 9821 | case Mips::LHU16_MM: |
| 9822 | case Mips::LW16_MM: |
| 9823 | case Mips::SB16_MM: |
| 9824 | case Mips::SB16_MMR6: |
| 9825 | case Mips::SH16_MM: |
| 9826 | case Mips::SH16_MMR6: |
| 9827 | case Mips::SW16_MM: |
| 9828 | case Mips::SW16_MMR6: { |
| 9829 | switch (OpNum) { |
| 9830 | case 0: |
| 9831 | // op: rt |
| 9832 | return 7; |
| 9833 | case 1: |
| 9834 | // op: addr |
| 9835 | return 0; |
| 9836 | } |
| 9837 | break; |
| 9838 | } |
| 9839 | case Mips::LWGP_MM: { |
| 9840 | switch (OpNum) { |
| 9841 | case 0: |
| 9842 | // op: rt |
| 9843 | return 7; |
| 9844 | case 1: |
| 9845 | // op: offset |
| 9846 | return 0; |
| 9847 | } |
| 9848 | break; |
| 9849 | } |
| 9850 | case Mips::NOT16_MMR6: { |
| 9851 | switch (OpNum) { |
| 9852 | case 0: |
| 9853 | // op: rt |
| 9854 | return 7; |
| 9855 | case 1: |
| 9856 | // op: rs |
| 9857 | return 4; |
| 9858 | } |
| 9859 | break; |
| 9860 | } |
| 9861 | case Mips::LWM16_MMR6: |
| 9862 | case Mips::SWM16_MMR6: { |
| 9863 | switch (OpNum) { |
| 9864 | case 0: |
| 9865 | // op: rt |
| 9866 | return 8; |
| 9867 | case 1: |
| 9868 | // op: addr |
| 9869 | return 4; |
| 9870 | } |
| 9871 | break; |
| 9872 | } |
| 9873 | case Mips::BeqzRxImm16: |
| 9874 | case Mips::BnezRxImm16: |
| 9875 | case Mips::CmpiRxImm16: |
| 9876 | case Mips::LiRxImm16: |
| 9877 | case Mips::LwRxPcTcp16: |
| 9878 | case Mips::SltiRxImm16: |
| 9879 | case Mips::SltiuRxImm16: { |
| 9880 | switch (OpNum) { |
| 9881 | case 0: |
| 9882 | // op: rx |
| 9883 | return 8; |
| 9884 | case 1: |
| 9885 | // op: imm8 |
| 9886 | return 0; |
| 9887 | } |
| 9888 | break; |
| 9889 | } |
| 9890 | case Mips::CmpRxRy16: |
| 9891 | case Mips::DivRxRy16: |
| 9892 | case Mips::DivuRxRy16: |
| 9893 | case Mips::NegRxRy16: |
| 9894 | case Mips::NotRxRy16: |
| 9895 | case Mips::SltRxRy16: |
| 9896 | case Mips::SltuRxRy16: { |
| 9897 | switch (OpNum) { |
| 9898 | case 0: |
| 9899 | // op: rx |
| 9900 | return 8; |
| 9901 | case 1: |
| 9902 | // op: ry |
| 9903 | return 5; |
| 9904 | } |
| 9905 | break; |
| 9906 | } |
| 9907 | case Mips::AddiuRxRxImm16: { |
| 9908 | switch (OpNum) { |
| 9909 | case 0: |
| 9910 | // op: rx |
| 9911 | return 8; |
| 9912 | case 2: |
| 9913 | // op: imm8 |
| 9914 | return 0; |
| 9915 | } |
| 9916 | break; |
| 9917 | } |
| 9918 | case Mips::JrcRx16: |
| 9919 | case Mips::JumpLinkReg16: |
| 9920 | case Mips::Mfhi16: |
| 9921 | case Mips::Mflo16: |
| 9922 | case Mips::SebRx16: |
| 9923 | case Mips::SehRx16: { |
| 9924 | switch (OpNum) { |
| 9925 | case 0: |
| 9926 | // op: rx |
| 9927 | return 8; |
| 9928 | } |
| 9929 | break; |
| 9930 | } |
| 9931 | case Mips::MoveR3216: { |
| 9932 | switch (OpNum) { |
| 9933 | case 0: |
| 9934 | // op: ry |
| 9935 | return 4; |
| 9936 | case 1: |
| 9937 | // op: r32 |
| 9938 | return 0; |
| 9939 | } |
| 9940 | break; |
| 9941 | } |
| 9942 | case Mips::SYNC_MM: |
| 9943 | case Mips::SYNC_MMR6: { |
| 9944 | switch (OpNum) { |
| 9945 | case 0: |
| 9946 | // op: stype |
| 9947 | return 16; |
| 9948 | } |
| 9949 | break; |
| 9950 | } |
| 9951 | case Mips::SYNC: { |
| 9952 | switch (OpNum) { |
| 9953 | case 0: |
| 9954 | // op: stype |
| 9955 | return 6; |
| 9956 | } |
| 9957 | break; |
| 9958 | } |
| 9959 | case Mips::J: |
| 9960 | case Mips::JAL: |
| 9961 | case Mips::JALS_MM: |
| 9962 | case Mips::JALX: |
| 9963 | case Mips::JALX_MM: |
| 9964 | case Mips::JAL_MM: |
| 9965 | case Mips::J_MM: { |
| 9966 | switch (OpNum) { |
| 9967 | case 0: |
| 9968 | // op: target |
| 9969 | return 0; |
| 9970 | } |
| 9971 | break; |
| 9972 | } |
| 9973 | case Mips::LBU_MMR6: |
| 9974 | case Mips::LB_MMR6: { |
| 9975 | switch (OpNum) { |
| 9976 | case 1: |
| 9977 | // op: addr |
| 9978 | return 0; |
| 9979 | case 0: |
| 9980 | // op: rt |
| 9981 | return 21; |
| 9982 | } |
| 9983 | break; |
| 9984 | } |
| 9985 | case Mips::LD_B: |
| 9986 | case Mips::LD_D: |
| 9987 | case Mips::LD_H: |
| 9988 | case Mips::LD_W: |
| 9989 | case Mips::ST_B: |
| 9990 | case Mips::ST_D: |
| 9991 | case Mips::ST_H: |
| 9992 | case Mips::ST_W: { |
| 9993 | switch (OpNum) { |
| 9994 | case 1: |
| 9995 | // op: addr |
| 9996 | return 11; |
| 9997 | case 0: |
| 9998 | // op: wd |
| 9999 | return 6; |
| 10000 | } |
| 10001 | break; |
| 10002 | } |
| 10003 | case Mips::LBE: |
| 10004 | case Mips::LBuE: |
| 10005 | case Mips::LHE: |
| 10006 | case Mips::LHuE: |
| 10007 | case Mips::LLE: |
| 10008 | case Mips::LWE: |
| 10009 | case Mips::LWLE: |
| 10010 | case Mips::LWRE: |
| 10011 | case Mips::SBE: |
| 10012 | case Mips::SHE: |
| 10013 | case Mips::SWE: |
| 10014 | case Mips::SWLE: |
| 10015 | case Mips::SWRE: { |
| 10016 | switch (OpNum) { |
| 10017 | case 1: |
| 10018 | // op: addr |
| 10019 | return 7; |
| 10020 | case 0: |
| 10021 | // op: rt |
| 10022 | return 16; |
| 10023 | } |
| 10024 | break; |
| 10025 | } |
| 10026 | case Mips::CLASS_D: |
| 10027 | case Mips::CLASS_S: |
| 10028 | case Mips::RINT_D: |
| 10029 | case Mips::RINT_S: { |
| 10030 | switch (OpNum) { |
| 10031 | case 1: |
| 10032 | // op: fs |
| 10033 | return 11; |
| 10034 | case 0: |
| 10035 | // op: fd |
| 10036 | return 6; |
| 10037 | } |
| 10038 | break; |
| 10039 | } |
| 10040 | case Mips::C_EQ_D32: |
| 10041 | case Mips::C_EQ_D64: |
| 10042 | case Mips::C_EQ_S: |
| 10043 | case Mips::C_F_D32: |
| 10044 | case Mips::C_F_D64: |
| 10045 | case Mips::C_F_S: |
| 10046 | case Mips::C_LE_D32: |
| 10047 | case Mips::C_LE_D64: |
| 10048 | case Mips::C_LE_S: |
| 10049 | case Mips::C_LT_D32: |
| 10050 | case Mips::C_LT_D64: |
| 10051 | case Mips::C_LT_S: |
| 10052 | case Mips::C_NGE_D32: |
| 10053 | case Mips::C_NGE_D64: |
| 10054 | case Mips::C_NGE_S: |
| 10055 | case Mips::C_NGLE_D32: |
| 10056 | case Mips::C_NGLE_D64: |
| 10057 | case Mips::C_NGLE_S: |
| 10058 | case Mips::C_NGL_D32: |
| 10059 | case Mips::C_NGL_D64: |
| 10060 | case Mips::C_NGL_S: |
| 10061 | case Mips::C_NGT_D32: |
| 10062 | case Mips::C_NGT_D64: |
| 10063 | case Mips::C_NGT_S: |
| 10064 | case Mips::C_OLE_D32: |
| 10065 | case Mips::C_OLE_D64: |
| 10066 | case Mips::C_OLE_S: |
| 10067 | case Mips::C_OLT_D32: |
| 10068 | case Mips::C_OLT_D64: |
| 10069 | case Mips::C_OLT_S: |
| 10070 | case Mips::C_SEQ_D32: |
| 10071 | case Mips::C_SEQ_D64: |
| 10072 | case Mips::C_SEQ_S: |
| 10073 | case Mips::C_SF_D32: |
| 10074 | case Mips::C_SF_D64: |
| 10075 | case Mips::C_SF_S: |
| 10076 | case Mips::C_UEQ_D32: |
| 10077 | case Mips::C_UEQ_D64: |
| 10078 | case Mips::C_UEQ_S: |
| 10079 | case Mips::C_ULE_D32: |
| 10080 | case Mips::C_ULE_D64: |
| 10081 | case Mips::C_ULE_S: |
| 10082 | case Mips::C_ULT_D32: |
| 10083 | case Mips::C_ULT_D64: |
| 10084 | case Mips::C_ULT_S: |
| 10085 | case Mips::C_UN_D32: |
| 10086 | case Mips::C_UN_D64: |
| 10087 | case Mips::C_UN_S: { |
| 10088 | switch (OpNum) { |
| 10089 | case 1: |
| 10090 | // op: fs |
| 10091 | return 11; |
| 10092 | case 2: |
| 10093 | // op: ft |
| 10094 | return 16; |
| 10095 | case 0: |
| 10096 | // op: fcc |
| 10097 | return 8; |
| 10098 | } |
| 10099 | break; |
| 10100 | } |
| 10101 | case Mips::C_EQ_D32_MM: |
| 10102 | case Mips::C_EQ_D64_MM: |
| 10103 | case Mips::C_EQ_S_MM: |
| 10104 | case Mips::C_F_D32_MM: |
| 10105 | case Mips::C_F_D64_MM: |
| 10106 | case Mips::C_F_S_MM: |
| 10107 | case Mips::C_LE_D32_MM: |
| 10108 | case Mips::C_LE_D64_MM: |
| 10109 | case Mips::C_LE_S_MM: |
| 10110 | case Mips::C_LT_D32_MM: |
| 10111 | case Mips::C_LT_D64_MM: |
| 10112 | case Mips::C_LT_S_MM: |
| 10113 | case Mips::C_NGE_D32_MM: |
| 10114 | case Mips::C_NGE_D64_MM: |
| 10115 | case Mips::C_NGE_S_MM: |
| 10116 | case Mips::C_NGLE_D32_MM: |
| 10117 | case Mips::C_NGLE_D64_MM: |
| 10118 | case Mips::C_NGLE_S_MM: |
| 10119 | case Mips::C_NGL_D32_MM: |
| 10120 | case Mips::C_NGL_D64_MM: |
| 10121 | case Mips::C_NGL_S_MM: |
| 10122 | case Mips::C_NGT_D32_MM: |
| 10123 | case Mips::C_NGT_D64_MM: |
| 10124 | case Mips::C_NGT_S_MM: |
| 10125 | case Mips::C_OLE_D32_MM: |
| 10126 | case Mips::C_OLE_D64_MM: |
| 10127 | case Mips::C_OLE_S_MM: |
| 10128 | case Mips::C_OLT_D32_MM: |
| 10129 | case Mips::C_OLT_D64_MM: |
| 10130 | case Mips::C_OLT_S_MM: |
| 10131 | case Mips::C_SEQ_D32_MM: |
| 10132 | case Mips::C_SEQ_D64_MM: |
| 10133 | case Mips::C_SEQ_S_MM: |
| 10134 | case Mips::C_SF_D32_MM: |
| 10135 | case Mips::C_SF_D64_MM: |
| 10136 | case Mips::C_SF_S_MM: |
| 10137 | case Mips::C_UEQ_D32_MM: |
| 10138 | case Mips::C_UEQ_D64_MM: |
| 10139 | case Mips::C_UEQ_S_MM: |
| 10140 | case Mips::C_ULE_D32_MM: |
| 10141 | case Mips::C_ULE_D64_MM: |
| 10142 | case Mips::C_ULE_S_MM: |
| 10143 | case Mips::C_ULT_D32_MM: |
| 10144 | case Mips::C_ULT_D64_MM: |
| 10145 | case Mips::C_ULT_S_MM: |
| 10146 | case Mips::C_UN_D32_MM: |
| 10147 | case Mips::C_UN_D64_MM: |
| 10148 | case Mips::C_UN_S_MM: { |
| 10149 | switch (OpNum) { |
| 10150 | case 1: |
| 10151 | // op: fs |
| 10152 | return 16; |
| 10153 | case 2: |
| 10154 | // op: ft |
| 10155 | return 21; |
| 10156 | case 0: |
| 10157 | // op: fcc |
| 10158 | return 13; |
| 10159 | } |
| 10160 | break; |
| 10161 | } |
| 10162 | case Mips::CLASS_D_MMR6: |
| 10163 | case Mips::CLASS_S_MMR6: |
| 10164 | case Mips::RINT_D_MMR6: |
| 10165 | case Mips::RINT_S_MMR6: { |
| 10166 | switch (OpNum) { |
| 10167 | case 1: |
| 10168 | // op: fs |
| 10169 | return 21; |
| 10170 | case 0: |
| 10171 | // op: fd |
| 10172 | return 16; |
| 10173 | } |
| 10174 | break; |
| 10175 | } |
| 10176 | case Mips::FADD_S_MMR6: |
| 10177 | case Mips::FDIV_S_MMR6: |
| 10178 | case Mips::FMUL_S_MMR6: |
| 10179 | case Mips::FSUB_S_MMR6: { |
| 10180 | switch (OpNum) { |
| 10181 | case 1: |
| 10182 | // op: ft |
| 10183 | return 21; |
| 10184 | case 2: |
| 10185 | // op: fs |
| 10186 | return 16; |
| 10187 | case 0: |
| 10188 | // op: fd |
| 10189 | return 11; |
| 10190 | } |
| 10191 | break; |
| 10192 | } |
| 10193 | case Mips::AddiuRxImmX16: |
| 10194 | case Mips::AddiuRxPcImmX16: |
| 10195 | case Mips::BeqzRxImmX16: |
| 10196 | case Mips::BnezRxImmX16: |
| 10197 | case Mips::CmpiRxImmX16: |
| 10198 | case Mips::LiRxImmAlignX16: |
| 10199 | case Mips::LiRxImmX16: |
| 10200 | case Mips::LwRxPcTcpX16: |
| 10201 | case Mips::SltiRxImmX16: |
| 10202 | case Mips::SltiuRxImmX16: { |
| 10203 | switch (OpNum) { |
| 10204 | case 1: |
| 10205 | // op: imm16 |
| 10206 | return 0; |
| 10207 | case 0: |
| 10208 | // op: rx |
| 10209 | return 8; |
| 10210 | } |
| 10211 | break; |
| 10212 | } |
| 10213 | case Mips::PREFX_MM: { |
| 10214 | switch (OpNum) { |
| 10215 | case 1: |
| 10216 | // op: index |
| 10217 | return 21; |
| 10218 | case 0: |
| 10219 | // op: base |
| 10220 | return 16; |
| 10221 | case 2: |
| 10222 | // op: hint |
| 10223 | return 11; |
| 10224 | } |
| 10225 | break; |
| 10226 | } |
| 10227 | case Mips::BNZ_B: |
| 10228 | case Mips::BNZ_D: |
| 10229 | case Mips::BNZ_H: |
| 10230 | case Mips::BNZ_V: |
| 10231 | case Mips::BNZ_W: |
| 10232 | case Mips::BZ_B: |
| 10233 | case Mips::BZ_D: |
| 10234 | case Mips::BZ_H: |
| 10235 | case Mips::BZ_V: |
| 10236 | case Mips::BZ_W: { |
| 10237 | switch (OpNum) { |
| 10238 | case 1: |
| 10239 | // op: offset |
| 10240 | return 0; |
| 10241 | case 0: |
| 10242 | // op: wt |
| 10243 | return 16; |
| 10244 | } |
| 10245 | break; |
| 10246 | } |
| 10247 | case Mips::ADDIUS5_MM: { |
| 10248 | switch (OpNum) { |
| 10249 | case 1: |
| 10250 | // op: rd |
| 10251 | return 5; |
| 10252 | case 2: |
| 10253 | // op: imm |
| 10254 | return 1; |
| 10255 | } |
| 10256 | break; |
| 10257 | } |
| 10258 | case Mips::MOVE16_MM: |
| 10259 | case Mips::MOVE16_MMR6: { |
| 10260 | switch (OpNum) { |
| 10261 | case 1: |
| 10262 | // op: rs |
| 10263 | return 0; |
| 10264 | case 0: |
| 10265 | // op: rd |
| 10266 | return 5; |
| 10267 | } |
| 10268 | break; |
| 10269 | } |
| 10270 | case Mips::CTCMSA: { |
| 10271 | switch (OpNum) { |
| 10272 | case 1: |
| 10273 | // op: rs |
| 10274 | return 11; |
| 10275 | case 0: |
| 10276 | // op: cd |
| 10277 | return 6; |
| 10278 | } |
| 10279 | break; |
| 10280 | } |
| 10281 | case Mips::FILL_B: |
| 10282 | case Mips::FILL_D: |
| 10283 | case Mips::FILL_H: |
| 10284 | case Mips::FILL_W: { |
| 10285 | switch (OpNum) { |
| 10286 | case 1: |
| 10287 | // op: rs |
| 10288 | return 11; |
| 10289 | case 0: |
| 10290 | // op: wd |
| 10291 | return 6; |
| 10292 | } |
| 10293 | break; |
| 10294 | } |
| 10295 | case Mips::MTHI_DSP_MM: |
| 10296 | case Mips::MTHLIP_MM: |
| 10297 | case Mips::MTLO_DSP_MM: |
| 10298 | case Mips::SHILOV_MM: { |
| 10299 | switch (OpNum) { |
| 10300 | case 1: |
| 10301 | // op: rs |
| 10302 | return 16; |
| 10303 | case 0: |
| 10304 | // op: ac |
| 10305 | return 14; |
| 10306 | } |
| 10307 | break; |
| 10308 | } |
| 10309 | case Mips::JALRS_MM: |
| 10310 | case Mips::JALR_HB_MM: |
| 10311 | case Mips::JALR_MM: { |
| 10312 | switch (OpNum) { |
| 10313 | case 1: |
| 10314 | // op: rs |
| 10315 | return 16; |
| 10316 | case 0: |
| 10317 | // op: rd |
| 10318 | return 21; |
| 10319 | } |
| 10320 | break; |
| 10321 | } |
| 10322 | case Mips::AUI_MMR6: { |
| 10323 | switch (OpNum) { |
| 10324 | case 1: |
| 10325 | // op: rs |
| 10326 | return 16; |
| 10327 | case 0: |
| 10328 | // op: rt |
| 10329 | return 21; |
| 10330 | case 2: |
| 10331 | // op: imm |
| 10332 | return 0; |
| 10333 | } |
| 10334 | break; |
| 10335 | } |
| 10336 | case Mips::ADDi_MM: |
| 10337 | case Mips::ADDiu_MM: |
| 10338 | case Mips::ANDi_MM: |
| 10339 | case Mips::ORi_MM: |
| 10340 | case Mips::XORi_MM: { |
| 10341 | switch (OpNum) { |
| 10342 | case 1: |
| 10343 | // op: rs |
| 10344 | return 16; |
| 10345 | case 0: |
| 10346 | // op: rt |
| 10347 | return 21; |
| 10348 | case 2: |
| 10349 | // op: imm16 |
| 10350 | return 0; |
| 10351 | } |
| 10352 | break; |
| 10353 | } |
| 10354 | case Mips::CLO_MMR6: { |
| 10355 | switch (OpNum) { |
| 10356 | case 1: |
| 10357 | // op: rs |
| 10358 | return 16; |
| 10359 | case 0: |
| 10360 | // op: rt |
| 10361 | return 21; |
| 10362 | } |
| 10363 | break; |
| 10364 | } |
| 10365 | case Mips::MTHI_DSP: |
| 10366 | case Mips::MTLO_DSP: { |
| 10367 | switch (OpNum) { |
| 10368 | case 1: |
| 10369 | // op: rs |
| 10370 | return 21; |
| 10371 | case 0: |
| 10372 | // op: ac |
| 10373 | return 11; |
| 10374 | } |
| 10375 | break; |
| 10376 | } |
| 10377 | case Mips::YIELD: { |
| 10378 | switch (OpNum) { |
| 10379 | case 1: |
| 10380 | // op: rs |
| 10381 | return 21; |
| 10382 | case 0: |
| 10383 | // op: rd |
| 10384 | return 11; |
| 10385 | } |
| 10386 | break; |
| 10387 | } |
| 10388 | case Mips::CLZ_MMR6: { |
| 10389 | switch (OpNum) { |
| 10390 | case 1: |
| 10391 | // op: rs |
| 10392 | return 21; |
| 10393 | case 0: |
| 10394 | // op: rt |
| 10395 | return 11; |
| 10396 | } |
| 10397 | break; |
| 10398 | } |
| 10399 | case Mips::AUI: |
| 10400 | case Mips::DAUI: { |
| 10401 | switch (OpNum) { |
| 10402 | case 1: |
| 10403 | // op: rs |
| 10404 | return 21; |
| 10405 | case 0: |
| 10406 | // op: rt |
| 10407 | return 16; |
| 10408 | case 2: |
| 10409 | // op: imm |
| 10410 | return 0; |
| 10411 | } |
| 10412 | break; |
| 10413 | } |
| 10414 | case Mips::SEQi: |
| 10415 | case Mips::SNEi: { |
| 10416 | switch (OpNum) { |
| 10417 | case 1: |
| 10418 | // op: rs |
| 10419 | return 21; |
| 10420 | case 0: |
| 10421 | // op: rt |
| 10422 | return 16; |
| 10423 | case 2: |
| 10424 | // op: imm10 |
| 10425 | return 6; |
| 10426 | } |
| 10427 | break; |
| 10428 | } |
| 10429 | case Mips::ADDi: |
| 10430 | case Mips::ADDiu: |
| 10431 | case Mips::ANDi: |
| 10432 | case Mips::ANDi64: |
| 10433 | case Mips::DADDi: |
| 10434 | case Mips::DADDiu: |
| 10435 | case Mips::ORi: |
| 10436 | case Mips::ORi64: |
| 10437 | case Mips::XORi: |
| 10438 | case Mips::XORi64: { |
| 10439 | switch (OpNum) { |
| 10440 | case 1: |
| 10441 | // op: rs |
| 10442 | return 21; |
| 10443 | case 0: |
| 10444 | // op: rt |
| 10445 | return 16; |
| 10446 | case 2: |
| 10447 | // op: imm16 |
| 10448 | return 0; |
| 10449 | } |
| 10450 | break; |
| 10451 | } |
| 10452 | case Mips::PRECR_SRA_PH_W: |
| 10453 | case Mips::PRECR_SRA_R_PH_W: { |
| 10454 | switch (OpNum) { |
| 10455 | case 1: |
| 10456 | // op: rs |
| 10457 | return 21; |
| 10458 | case 0: |
| 10459 | // op: rt |
| 10460 | return 16; |
| 10461 | case 2: |
| 10462 | // op: sa |
| 10463 | return 11; |
| 10464 | } |
| 10465 | break; |
| 10466 | } |
| 10467 | case Mips::DLSA: |
| 10468 | case Mips::LSA: { |
| 10469 | switch (OpNum) { |
| 10470 | case 1: |
| 10471 | // op: rs |
| 10472 | return 21; |
| 10473 | case 2: |
| 10474 | // op: rt |
| 10475 | return 16; |
| 10476 | case 0: |
| 10477 | // op: rd |
| 10478 | return 11; |
| 10479 | case 3: |
| 10480 | // op: sa |
| 10481 | return 6; |
| 10482 | } |
| 10483 | break; |
| 10484 | } |
| 10485 | case Mips::CMPGDU_EQ_QB: |
| 10486 | case Mips::CMPGDU_LE_QB: |
| 10487 | case Mips::CMPGDU_LT_QB: |
| 10488 | case Mips::CMPGU_EQ_QB: |
| 10489 | case Mips::CMPGU_LE_QB: |
| 10490 | case Mips::CMPGU_LT_QB: |
| 10491 | case Mips::PACKRL_PH: |
| 10492 | case Mips::PICK_PH: |
| 10493 | case Mips::PICK_QB: |
| 10494 | case Mips::PRECRQU_S_QB_PH: |
| 10495 | case Mips::PRECRQ_PH_W: |
| 10496 | case Mips::PRECRQ_QB_PH: |
| 10497 | case Mips::PRECRQ_RS_PH_W: |
| 10498 | case Mips::PRECR_QB_PH: { |
| 10499 | switch (OpNum) { |
| 10500 | case 1: |
| 10501 | // op: rs |
| 10502 | return 21; |
| 10503 | case 2: |
| 10504 | // op: rt |
| 10505 | return 16; |
| 10506 | case 0: |
| 10507 | // op: rd |
| 10508 | return 11; |
| 10509 | } |
| 10510 | break; |
| 10511 | } |
| 10512 | case Mips::CRC32B: |
| 10513 | case Mips::CRC32CB: |
| 10514 | case Mips::CRC32CD: |
| 10515 | case Mips::CRC32CH: |
| 10516 | case Mips::CRC32CW: |
| 10517 | case Mips::CRC32D: |
| 10518 | case Mips::CRC32H: |
| 10519 | case Mips::CRC32W: { |
| 10520 | switch (OpNum) { |
| 10521 | case 1: |
| 10522 | // op: rs |
| 10523 | return 21; |
| 10524 | case 2: |
| 10525 | // op: rt |
| 10526 | return 16; |
| 10527 | } |
| 10528 | break; |
| 10529 | } |
| 10530 | case Mips::ADDU16_MMR6: |
| 10531 | case Mips::SUBU16_MMR6: { |
| 10532 | switch (OpNum) { |
| 10533 | case 1: |
| 10534 | // op: rs |
| 10535 | return 7; |
| 10536 | case 2: |
| 10537 | // op: rt |
| 10538 | return 4; |
| 10539 | case 0: |
| 10540 | // op: rd |
| 10541 | return 1; |
| 10542 | } |
| 10543 | break; |
| 10544 | } |
| 10545 | case Mips::CTC1: |
| 10546 | case Mips::DMTC1: |
| 10547 | case Mips::MTC1: |
| 10548 | case Mips::MTC1_D64: { |
| 10549 | switch (OpNum) { |
| 10550 | case 1: |
| 10551 | // op: rt |
| 10552 | return 16; |
| 10553 | case 0: |
| 10554 | // op: fs |
| 10555 | return 11; |
| 10556 | } |
| 10557 | break; |
| 10558 | } |
| 10559 | case Mips::DMTC0: |
| 10560 | case Mips::DMTC2: |
| 10561 | case Mips::DMTGC0: |
| 10562 | case Mips::MTC0: |
| 10563 | case Mips::MTC2: |
| 10564 | case Mips::MTGC0: |
| 10565 | case Mips::MTHGC0: { |
| 10566 | switch (OpNum) { |
| 10567 | case 1: |
| 10568 | // op: rt |
| 10569 | return 16; |
| 10570 | case 0: |
| 10571 | // op: rd |
| 10572 | return 11; |
| 10573 | case 2: |
| 10574 | // op: sel |
| 10575 | return 0; |
| 10576 | } |
| 10577 | break; |
| 10578 | } |
| 10579 | case Mips::MFTR: |
| 10580 | case Mips::MTTR: { |
| 10581 | switch (OpNum) { |
| 10582 | case 1: |
| 10583 | // op: rt |
| 10584 | return 16; |
| 10585 | case 0: |
| 10586 | // op: rd |
| 10587 | return 11; |
| 10588 | case 2: |
| 10589 | // op: u |
| 10590 | return 5; |
| 10591 | case 4: |
| 10592 | // op: h |
| 10593 | return 4; |
| 10594 | case 3: |
| 10595 | // op: sel |
| 10596 | return 0; |
| 10597 | } |
| 10598 | break; |
| 10599 | } |
| 10600 | case Mips::SC: |
| 10601 | case Mips::SC64: |
| 10602 | case Mips::SCD: { |
| 10603 | switch (OpNum) { |
| 10604 | case 1: |
| 10605 | // op: rt |
| 10606 | return 16; |
| 10607 | case 2: |
| 10608 | // op: addr |
| 10609 | return 0; |
| 10610 | } |
| 10611 | break; |
| 10612 | } |
| 10613 | case Mips::SC64_R6: |
| 10614 | case Mips::SCD_R6: |
| 10615 | case Mips::SC_R6: { |
| 10616 | switch (OpNum) { |
| 10617 | case 1: |
| 10618 | // op: rt |
| 10619 | return 16; |
| 10620 | case 2: |
| 10621 | // op: addr |
| 10622 | return 7; |
| 10623 | } |
| 10624 | break; |
| 10625 | } |
| 10626 | case Mips::CTC1_MM: |
| 10627 | case Mips::MTC1_D64_MM: |
| 10628 | case Mips::MTC1_MM: |
| 10629 | case Mips::MTC1_MMR6: { |
| 10630 | switch (OpNum) { |
| 10631 | case 1: |
| 10632 | // op: rt |
| 10633 | return 21; |
| 10634 | case 0: |
| 10635 | // op: fs |
| 10636 | return 16; |
| 10637 | } |
| 10638 | break; |
| 10639 | } |
| 10640 | case Mips::CTC2_MM: |
| 10641 | case Mips::MTC2_MMR6: |
| 10642 | case Mips::MTHC2_MMR6: { |
| 10643 | switch (OpNum) { |
| 10644 | case 1: |
| 10645 | // op: rt |
| 10646 | return 21; |
| 10647 | case 0: |
| 10648 | // op: impl |
| 10649 | return 16; |
| 10650 | } |
| 10651 | break; |
| 10652 | } |
| 10653 | case Mips::MTC0_MM: { |
| 10654 | switch (OpNum) { |
| 10655 | case 1: |
| 10656 | // op: rt |
| 10657 | return 21; |
| 10658 | case 0: |
| 10659 | // op: rd |
| 10660 | return 16; |
| 10661 | case 2: |
| 10662 | // op: sel |
| 10663 | return 11; |
| 10664 | } |
| 10665 | break; |
| 10666 | } |
| 10667 | case Mips::BEQC_MMR6: |
| 10668 | case Mips::BGEC_MMR6: |
| 10669 | case Mips::BGEUC_MMR6: |
| 10670 | case Mips::BLTC_MMR6: |
| 10671 | case Mips::BLTUC_MMR6: |
| 10672 | case Mips::BNEC_MMR6: { |
| 10673 | switch (OpNum) { |
| 10674 | case 1: |
| 10675 | // op: rt |
| 10676 | return 21; |
| 10677 | case 0: |
| 10678 | // op: rs |
| 10679 | return 16; |
| 10680 | case 2: |
| 10681 | // op: offset |
| 10682 | return 0; |
| 10683 | } |
| 10684 | break; |
| 10685 | } |
| 10686 | case Mips::MTC0_MMR6: |
| 10687 | case Mips::MTGC0_MM: |
| 10688 | case Mips::MTHC0_MMR6: |
| 10689 | case Mips::MTHGC0_MM: { |
| 10690 | switch (OpNum) { |
| 10691 | case 1: |
| 10692 | // op: rt |
| 10693 | return 21; |
| 10694 | case 0: |
| 10695 | // op: rs |
| 10696 | return 16; |
| 10697 | case 2: |
| 10698 | // op: sel |
| 10699 | return 11; |
| 10700 | } |
| 10701 | break; |
| 10702 | } |
| 10703 | case Mips::CMPU_EQ_QB_MM: |
| 10704 | case Mips::CMPU_LE_QB_MM: |
| 10705 | case Mips::CMPU_LT_QB_MM: |
| 10706 | case Mips::CMP_EQ_PH_MM: |
| 10707 | case Mips::CMP_LE_PH_MM: |
| 10708 | case Mips::CMP_LT_PH_MM: { |
| 10709 | switch (OpNum) { |
| 10710 | case 1: |
| 10711 | // op: rt |
| 10712 | return 21; |
| 10713 | case 0: |
| 10714 | // op: rs |
| 10715 | return 16; |
| 10716 | } |
| 10717 | break; |
| 10718 | } |
| 10719 | case Mips::SCE_MM: |
| 10720 | case Mips::SC_MM: |
| 10721 | case Mips::SC_MMR6: { |
| 10722 | switch (OpNum) { |
| 10723 | case 1: |
| 10724 | // op: rt |
| 10725 | return 21; |
| 10726 | case 2: |
| 10727 | // op: addr |
| 10728 | return 0; |
| 10729 | } |
| 10730 | break; |
| 10731 | } |
| 10732 | case Mips::AdduRxRyRz16: |
| 10733 | case Mips::SubuRxRyRz16: { |
| 10734 | switch (OpNum) { |
| 10735 | case 1: |
| 10736 | // op: rx |
| 10737 | return 8; |
| 10738 | case 2: |
| 10739 | // op: ry |
| 10740 | return 5; |
| 10741 | case 0: |
| 10742 | // op: rz |
| 10743 | return 2; |
| 10744 | } |
| 10745 | break; |
| 10746 | } |
| 10747 | case Mips::AndRxRxRy16: |
| 10748 | case Mips::OrRxRxRy16: |
| 10749 | case Mips::SllvRxRy16: |
| 10750 | case Mips::SravRxRy16: |
| 10751 | case Mips::SrlvRxRy16: |
| 10752 | case Mips::XorRxRxRy16: { |
| 10753 | switch (OpNum) { |
| 10754 | case 1: |
| 10755 | // op: rx |
| 10756 | return 8; |
| 10757 | case 2: |
| 10758 | // op: ry |
| 10759 | return 5; |
| 10760 | } |
| 10761 | break; |
| 10762 | } |
| 10763 | case Mips::LDI_B: |
| 10764 | case Mips::LDI_D: |
| 10765 | case Mips::LDI_H: |
| 10766 | case Mips::LDI_W: { |
| 10767 | switch (OpNum) { |
| 10768 | case 1: |
| 10769 | // op: s10 |
| 10770 | return 11; |
| 10771 | case 0: |
| 10772 | // op: wd |
| 10773 | return 6; |
| 10774 | } |
| 10775 | break; |
| 10776 | } |
| 10777 | case Mips::SHILO_MM: { |
| 10778 | switch (OpNum) { |
| 10779 | case 1: |
| 10780 | // op: shift |
| 10781 | return 16; |
| 10782 | case 0: |
| 10783 | // op: ac |
| 10784 | return 14; |
| 10785 | } |
| 10786 | break; |
| 10787 | } |
| 10788 | case Mips::BCLRI_B: |
| 10789 | case Mips::BCLRI_D: |
| 10790 | case Mips::BCLRI_H: |
| 10791 | case Mips::BCLRI_W: |
| 10792 | case Mips::BNEGI_B: |
| 10793 | case Mips::BNEGI_D: |
| 10794 | case Mips::BNEGI_H: |
| 10795 | case Mips::BNEGI_W: |
| 10796 | case Mips::BSETI_B: |
| 10797 | case Mips::BSETI_D: |
| 10798 | case Mips::BSETI_H: |
| 10799 | case Mips::BSETI_W: |
| 10800 | case Mips::SAT_S_B: |
| 10801 | case Mips::SAT_S_D: |
| 10802 | case Mips::SAT_S_H: |
| 10803 | case Mips::SAT_S_W: |
| 10804 | case Mips::SAT_U_B: |
| 10805 | case Mips::SAT_U_D: |
| 10806 | case Mips::SAT_U_H: |
| 10807 | case Mips::SAT_U_W: |
| 10808 | case Mips::SLLI_B: |
| 10809 | case Mips::SLLI_D: |
| 10810 | case Mips::SLLI_H: |
| 10811 | case Mips::SLLI_W: |
| 10812 | case Mips::SRAI_B: |
| 10813 | case Mips::SRAI_D: |
| 10814 | case Mips::SRAI_H: |
| 10815 | case Mips::SRAI_W: |
| 10816 | case Mips::SRARI_B: |
| 10817 | case Mips::SRARI_D: |
| 10818 | case Mips::SRARI_H: |
| 10819 | case Mips::SRARI_W: |
| 10820 | case Mips::SRLI_B: |
| 10821 | case Mips::SRLI_D: |
| 10822 | case Mips::SRLI_H: |
| 10823 | case Mips::SRLI_W: |
| 10824 | case Mips::SRLRI_B: |
| 10825 | case Mips::SRLRI_D: |
| 10826 | case Mips::SRLRI_H: |
| 10827 | case Mips::SRLRI_W: { |
| 10828 | switch (OpNum) { |
| 10829 | case 1: |
| 10830 | // op: ws |
| 10831 | return 11; |
| 10832 | case 0: |
| 10833 | // op: wd |
| 10834 | return 6; |
| 10835 | case 2: |
| 10836 | // op: m |
| 10837 | return 16; |
| 10838 | } |
| 10839 | break; |
| 10840 | } |
| 10841 | case Mips::FCLASS_D: |
| 10842 | case Mips::FCLASS_W: |
| 10843 | case Mips::FEXUPL_D: |
| 10844 | case Mips::FEXUPL_W: |
| 10845 | case Mips::FEXUPR_D: |
| 10846 | case Mips::FEXUPR_W: |
| 10847 | case Mips::FFINT_S_D: |
| 10848 | case Mips::FFINT_S_W: |
| 10849 | case Mips::FFINT_U_D: |
| 10850 | case Mips::FFINT_U_W: |
| 10851 | case Mips::FFQL_D: |
| 10852 | case Mips::FFQL_W: |
| 10853 | case Mips::FFQR_D: |
| 10854 | case Mips::FFQR_W: |
| 10855 | case Mips::FLOG2_D: |
| 10856 | case Mips::FLOG2_W: |
| 10857 | case Mips::FRCP_D: |
| 10858 | case Mips::FRCP_W: |
| 10859 | case Mips::FRINT_D: |
| 10860 | case Mips::FRINT_W: |
| 10861 | case Mips::FRSQRT_D: |
| 10862 | case Mips::FRSQRT_W: |
| 10863 | case Mips::FSQRT_D: |
| 10864 | case Mips::FSQRT_W: |
| 10865 | case Mips::FTINT_S_D: |
| 10866 | case Mips::FTINT_S_W: |
| 10867 | case Mips::FTINT_U_D: |
| 10868 | case Mips::FTINT_U_W: |
| 10869 | case Mips::FTRUNC_S_D: |
| 10870 | case Mips::FTRUNC_S_W: |
| 10871 | case Mips::FTRUNC_U_D: |
| 10872 | case Mips::FTRUNC_U_W: |
| 10873 | case Mips::MOVE_V: |
| 10874 | case Mips::NLOC_B: |
| 10875 | case Mips::NLOC_D: |
| 10876 | case Mips::NLOC_H: |
| 10877 | case Mips::NLOC_W: |
| 10878 | case Mips::NLZC_B: |
| 10879 | case Mips::NLZC_D: |
| 10880 | case Mips::NLZC_H: |
| 10881 | case Mips::NLZC_W: |
| 10882 | case Mips::PCNT_B: |
| 10883 | case Mips::PCNT_D: |
| 10884 | case Mips::PCNT_H: |
| 10885 | case Mips::PCNT_W: { |
| 10886 | switch (OpNum) { |
| 10887 | case 1: |
| 10888 | // op: ws |
| 10889 | return 11; |
| 10890 | case 0: |
| 10891 | // op: wd |
| 10892 | return 6; |
| 10893 | } |
| 10894 | break; |
| 10895 | } |
| 10896 | case Mips::SCE: { |
| 10897 | switch (OpNum) { |
| 10898 | case 2: |
| 10899 | // op: addr |
| 10900 | return 7; |
| 10901 | case 1: |
| 10902 | // op: rt |
| 10903 | return 16; |
| 10904 | } |
| 10905 | break; |
| 10906 | } |
| 10907 | case Mips::MAXA_D: |
| 10908 | case Mips::MAXA_S: |
| 10909 | case Mips::MAX_D: |
| 10910 | case Mips::MAX_S: |
| 10911 | case Mips::MINA_D: |
| 10912 | case Mips::MINA_S: |
| 10913 | case Mips::MIN_D: |
| 10914 | case Mips::MIN_S: |
| 10915 | case Mips::SELEQZ_D: |
| 10916 | case Mips::SELEQZ_S: |
| 10917 | case Mips::SELNEZ_D: |
| 10918 | case Mips::SELNEZ_S: { |
| 10919 | switch (OpNum) { |
| 10920 | case 2: |
| 10921 | // op: ft |
| 10922 | return 16; |
| 10923 | case 1: |
| 10924 | // op: fs |
| 10925 | return 11; |
| 10926 | case 0: |
| 10927 | // op: fd |
| 10928 | return 6; |
| 10929 | } |
| 10930 | break; |
| 10931 | } |
| 10932 | case Mips::CMP_AF_D_MMR6: |
| 10933 | case Mips::CMP_AF_S_MMR6: |
| 10934 | case Mips::CMP_EQ_D_MMR6: |
| 10935 | case Mips::CMP_EQ_S_MMR6: |
| 10936 | case Mips::CMP_LE_D_MMR6: |
| 10937 | case Mips::CMP_LE_S_MMR6: |
| 10938 | case Mips::CMP_LT_D_MMR6: |
| 10939 | case Mips::CMP_LT_S_MMR6: |
| 10940 | case Mips::CMP_SAF_D_MMR6: |
| 10941 | case Mips::CMP_SAF_S_MMR6: |
| 10942 | case Mips::CMP_SEQ_D_MMR6: |
| 10943 | case Mips::CMP_SEQ_S_MMR6: |
| 10944 | case Mips::CMP_SLE_D_MMR6: |
| 10945 | case Mips::CMP_SLE_S_MMR6: |
| 10946 | case Mips::CMP_SLT_D_MMR6: |
| 10947 | case Mips::CMP_SLT_S_MMR6: |
| 10948 | case Mips::CMP_SUEQ_D_MMR6: |
| 10949 | case Mips::CMP_SUEQ_S_MMR6: |
| 10950 | case Mips::CMP_SULE_D_MMR6: |
| 10951 | case Mips::CMP_SULE_S_MMR6: |
| 10952 | case Mips::CMP_SULT_D_MMR6: |
| 10953 | case Mips::CMP_SULT_S_MMR6: |
| 10954 | case Mips::CMP_SUN_D_MMR6: |
| 10955 | case Mips::CMP_SUN_S_MMR6: |
| 10956 | case Mips::CMP_UEQ_D_MMR6: |
| 10957 | case Mips::CMP_UEQ_S_MMR6: |
| 10958 | case Mips::CMP_ULE_D_MMR6: |
| 10959 | case Mips::CMP_ULE_S_MMR6: |
| 10960 | case Mips::CMP_ULT_D_MMR6: |
| 10961 | case Mips::CMP_ULT_S_MMR6: |
| 10962 | case Mips::CMP_UN_D_MMR6: |
| 10963 | case Mips::CMP_UN_S_MMR6: |
| 10964 | case Mips::FADD_D32_MM: |
| 10965 | case Mips::FADD_D64_MM: |
| 10966 | case Mips::FADD_S_MM: |
| 10967 | case Mips::FDIV_D32_MM: |
| 10968 | case Mips::FDIV_D64_MM: |
| 10969 | case Mips::FDIV_S_MM: |
| 10970 | case Mips::FMUL_D32_MM: |
| 10971 | case Mips::FMUL_D64_MM: |
| 10972 | case Mips::FMUL_S_MM: |
| 10973 | case Mips::FSUB_D32_MM: |
| 10974 | case Mips::FSUB_D64_MM: |
| 10975 | case Mips::FSUB_S_MM: |
| 10976 | case Mips::MAXA_D_MMR6: |
| 10977 | case Mips::MAXA_S_MMR6: |
| 10978 | case Mips::MAX_D_MMR6: |
| 10979 | case Mips::MAX_S_MMR6: |
| 10980 | case Mips::MINA_D_MMR6: |
| 10981 | case Mips::MINA_S_MMR6: |
| 10982 | case Mips::MIN_D_MMR6: |
| 10983 | case Mips::MIN_S_MMR6: |
| 10984 | case Mips::SELEQZ_D_MMR6: |
| 10985 | case Mips::SELEQZ_S_MMR6: |
| 10986 | case Mips::SELNEZ_D_MMR6: |
| 10987 | case Mips::SELNEZ_S_MMR6: { |
| 10988 | switch (OpNum) { |
| 10989 | case 2: |
| 10990 | // op: ft |
| 10991 | return 21; |
| 10992 | case 1: |
| 10993 | // op: fs |
| 10994 | return 16; |
| 10995 | case 0: |
| 10996 | // op: fd |
| 10997 | return 11; |
| 10998 | } |
| 10999 | break; |
| 11000 | } |
| 11001 | case Mips::ADDVI_B: |
| 11002 | case Mips::ADDVI_D: |
| 11003 | case Mips::ADDVI_H: |
| 11004 | case Mips::ADDVI_W: |
| 11005 | case Mips::CEQI_B: |
| 11006 | case Mips::CEQI_D: |
| 11007 | case Mips::CEQI_H: |
| 11008 | case Mips::CEQI_W: |
| 11009 | case Mips::CLEI_S_B: |
| 11010 | case Mips::CLEI_S_D: |
| 11011 | case Mips::CLEI_S_H: |
| 11012 | case Mips::CLEI_S_W: |
| 11013 | case Mips::CLEI_U_B: |
| 11014 | case Mips::CLEI_U_D: |
| 11015 | case Mips::CLEI_U_H: |
| 11016 | case Mips::CLEI_U_W: |
| 11017 | case Mips::CLTI_S_B: |
| 11018 | case Mips::CLTI_S_D: |
| 11019 | case Mips::CLTI_S_H: |
| 11020 | case Mips::CLTI_S_W: |
| 11021 | case Mips::CLTI_U_B: |
| 11022 | case Mips::CLTI_U_D: |
| 11023 | case Mips::CLTI_U_H: |
| 11024 | case Mips::CLTI_U_W: |
| 11025 | case Mips::MAXI_S_B: |
| 11026 | case Mips::MAXI_S_D: |
| 11027 | case Mips::MAXI_S_H: |
| 11028 | case Mips::MAXI_S_W: |
| 11029 | case Mips::MAXI_U_B: |
| 11030 | case Mips::MAXI_U_D: |
| 11031 | case Mips::MAXI_U_H: |
| 11032 | case Mips::MAXI_U_W: |
| 11033 | case Mips::MINI_S_B: |
| 11034 | case Mips::MINI_S_D: |
| 11035 | case Mips::MINI_S_H: |
| 11036 | case Mips::MINI_S_W: |
| 11037 | case Mips::MINI_U_B: |
| 11038 | case Mips::MINI_U_D: |
| 11039 | case Mips::MINI_U_H: |
| 11040 | case Mips::MINI_U_W: |
| 11041 | case Mips::SUBVI_B: |
| 11042 | case Mips::SUBVI_D: |
| 11043 | case Mips::SUBVI_H: |
| 11044 | case Mips::SUBVI_W: { |
| 11045 | switch (OpNum) { |
| 11046 | case 2: |
| 11047 | // op: imm |
| 11048 | return 16; |
| 11049 | case 1: |
| 11050 | // op: ws |
| 11051 | return 11; |
| 11052 | case 0: |
| 11053 | // op: wd |
| 11054 | return 6; |
| 11055 | } |
| 11056 | break; |
| 11057 | } |
| 11058 | case Mips::AddiuRxRyOffMemX16: { |
| 11059 | switch (OpNum) { |
| 11060 | case 2: |
| 11061 | // op: imm15 |
| 11062 | return 0; |
| 11063 | case 1: |
| 11064 | // op: rx |
| 11065 | return 8; |
| 11066 | case 0: |
| 11067 | // op: ry |
| 11068 | return 5; |
| 11069 | } |
| 11070 | break; |
| 11071 | } |
| 11072 | case Mips::AddiuRxRxImmX16: { |
| 11073 | switch (OpNum) { |
| 11074 | case 2: |
| 11075 | // op: imm16 |
| 11076 | return 0; |
| 11077 | case 0: |
| 11078 | // op: rx |
| 11079 | return 8; |
| 11080 | } |
| 11081 | break; |
| 11082 | } |
| 11083 | case Mips::LbRxRyOffMemX16: |
| 11084 | case Mips::LbuRxRyOffMemX16: |
| 11085 | case Mips::LhRxRyOffMemX16: |
| 11086 | case Mips::LhuRxRyOffMemX16: |
| 11087 | case Mips::LwRxRyOffMemX16: |
| 11088 | case Mips::LwRxSpImmX16: |
| 11089 | case Mips::SbRxRyOffMemX16: |
| 11090 | case Mips::ShRxRyOffMemX16: |
| 11091 | case Mips::SwRxRyOffMemX16: |
| 11092 | case Mips::SwRxSpImmX16: { |
| 11093 | switch (OpNum) { |
| 11094 | case 2: |
| 11095 | // op: imm16 |
| 11096 | return 0; |
| 11097 | case 1: |
| 11098 | // op: rx |
| 11099 | return 8; |
| 11100 | case 0: |
| 11101 | // op: ry |
| 11102 | return 5; |
| 11103 | } |
| 11104 | break; |
| 11105 | } |
| 11106 | case Mips::LBUX_MM: |
| 11107 | case Mips::LHX_MM: |
| 11108 | case Mips::LWX_MM: { |
| 11109 | switch (OpNum) { |
| 11110 | case 2: |
| 11111 | // op: index |
| 11112 | return 21; |
| 11113 | case 1: |
| 11114 | // op: base |
| 11115 | return 16; |
| 11116 | case 0: |
| 11117 | // op: rd |
| 11118 | return 11; |
| 11119 | } |
| 11120 | break; |
| 11121 | } |
| 11122 | case Mips::COPY_S_B: |
| 11123 | case Mips::COPY_S_D: |
| 11124 | case Mips::COPY_S_H: |
| 11125 | case Mips::COPY_S_W: |
| 11126 | case Mips::COPY_U_B: |
| 11127 | case Mips::COPY_U_H: |
| 11128 | case Mips::COPY_U_W: { |
| 11129 | switch (OpNum) { |
| 11130 | case 2: |
| 11131 | // op: n |
| 11132 | return 16; |
| 11133 | case 1: |
| 11134 | // op: ws |
| 11135 | return 11; |
| 11136 | case 0: |
| 11137 | // op: rd |
| 11138 | return 6; |
| 11139 | } |
| 11140 | break; |
| 11141 | } |
| 11142 | case Mips::SPLATI_B: |
| 11143 | case Mips::SPLATI_D: |
| 11144 | case Mips::SPLATI_H: |
| 11145 | case Mips::SPLATI_W: { |
| 11146 | switch (OpNum) { |
| 11147 | case 2: |
| 11148 | // op: n |
| 11149 | return 16; |
| 11150 | case 1: |
| 11151 | // op: ws |
| 11152 | return 11; |
| 11153 | case 0: |
| 11154 | // op: wd |
| 11155 | return 6; |
| 11156 | } |
| 11157 | break; |
| 11158 | } |
| 11159 | case Mips::INSVE_B: |
| 11160 | case Mips::INSVE_D: |
| 11161 | case Mips::INSVE_H: |
| 11162 | case Mips::INSVE_W: { |
| 11163 | switch (OpNum) { |
| 11164 | case 2: |
| 11165 | // op: n |
| 11166 | return 16; |
| 11167 | case 3: |
| 11168 | // op: ws |
| 11169 | return 11; |
| 11170 | case 0: |
| 11171 | // op: wd |
| 11172 | return 6; |
| 11173 | } |
| 11174 | break; |
| 11175 | } |
| 11176 | case Mips::MTHC1_D32: |
| 11177 | case Mips::MTHC1_D64: { |
| 11178 | switch (OpNum) { |
| 11179 | case 2: |
| 11180 | // op: rt |
| 11181 | return 16; |
| 11182 | case 0: |
| 11183 | // op: fs |
| 11184 | return 11; |
| 11185 | } |
| 11186 | break; |
| 11187 | } |
| 11188 | case Mips::SPLAT_B: |
| 11189 | case Mips::SPLAT_D: |
| 11190 | case Mips::SPLAT_H: |
| 11191 | case Mips::SPLAT_W: { |
| 11192 | switch (OpNum) { |
| 11193 | case 2: |
| 11194 | // op: rt |
| 11195 | return 16; |
| 11196 | case 1: |
| 11197 | // op: ws |
| 11198 | return 11; |
| 11199 | case 0: |
| 11200 | // op: wd |
| 11201 | return 6; |
| 11202 | } |
| 11203 | break; |
| 11204 | } |
| 11205 | case Mips::MTHC1_D32_MM: |
| 11206 | case Mips::MTHC1_D64_MM: { |
| 11207 | switch (OpNum) { |
| 11208 | case 2: |
| 11209 | // op: rt |
| 11210 | return 21; |
| 11211 | case 0: |
| 11212 | // op: fs |
| 11213 | return 16; |
| 11214 | } |
| 11215 | break; |
| 11216 | } |
| 11217 | case Mips::DPAQX_SA_W_PH_MMR2: |
| 11218 | case Mips::DPAQX_S_W_PH_MMR2: |
| 11219 | case Mips::DPAQ_SA_L_W_MM: |
| 11220 | case Mips::DPAQ_S_W_PH_MM: |
| 11221 | case Mips::DPAU_H_QBL_MM: |
| 11222 | case Mips::DPAU_H_QBR_MM: |
| 11223 | case Mips::DPAX_W_PH_MMR2: |
| 11224 | case Mips::DPA_W_PH_MMR2: |
| 11225 | case Mips::DPSQX_SA_W_PH_MMR2: |
| 11226 | case Mips::DPSQX_S_W_PH_MMR2: |
| 11227 | case Mips::DPSQ_SA_L_W_MM: |
| 11228 | case Mips::DPSQ_S_W_PH_MM: |
| 11229 | case Mips::DPSU_H_QBL_MM: |
| 11230 | case Mips::DPSU_H_QBR_MM: |
| 11231 | case Mips::DPSX_W_PH_MMR2: |
| 11232 | case Mips::DPS_W_PH_MMR2: |
| 11233 | case Mips::MADDU_DSP_MM: |
| 11234 | case Mips::MADD_DSP_MM: |
| 11235 | case Mips::MAQ_SA_W_PHL_MM: |
| 11236 | case Mips::MAQ_SA_W_PHR_MM: |
| 11237 | case Mips::MAQ_S_W_PHL_MM: |
| 11238 | case Mips::MAQ_S_W_PHR_MM: |
| 11239 | case Mips::MSUBU_DSP_MM: |
| 11240 | case Mips::MSUB_DSP_MM: |
| 11241 | case Mips::MULSAQ_S_W_PH_MM: |
| 11242 | case Mips::MULSA_W_PH_MMR2: |
| 11243 | case Mips::MULTU_DSP_MM: |
| 11244 | case Mips::MULT_DSP_MM: { |
| 11245 | switch (OpNum) { |
| 11246 | case 2: |
| 11247 | // op: rt |
| 11248 | return 21; |
| 11249 | case 1: |
| 11250 | // op: rs |
| 11251 | return 16; |
| 11252 | case 0: |
| 11253 | // op: ac |
| 11254 | return 14; |
| 11255 | } |
| 11256 | break; |
| 11257 | } |
| 11258 | case Mips::ADD_MM: |
| 11259 | case Mips::ADDu_MM: |
| 11260 | case Mips::AND_MM: |
| 11261 | case Mips::CMPGU_EQ_QB_MM: |
| 11262 | case Mips::CMPGU_LE_QB_MM: |
| 11263 | case Mips::CMPGU_LT_QB_MM: |
| 11264 | case Mips::MOVN_I_MM: |
| 11265 | case Mips::MOVZ_I_MM: |
| 11266 | case Mips::MUL_MM: |
| 11267 | case Mips::NOR_MM: |
| 11268 | case Mips::OR_MM: |
| 11269 | case Mips::SLT_MM: |
| 11270 | case Mips::SLTu_MM: |
| 11271 | case Mips::SUB_MM: |
| 11272 | case Mips::SUBu_MM: |
| 11273 | case Mips::XOR_MM: { |
| 11274 | switch (OpNum) { |
| 11275 | case 2: |
| 11276 | // op: rt |
| 11277 | return 21; |
| 11278 | case 1: |
| 11279 | // op: rs |
| 11280 | return 16; |
| 11281 | case 0: |
| 11282 | // op: rd |
| 11283 | return 11; |
| 11284 | } |
| 11285 | break; |
| 11286 | } |
| 11287 | case Mips::AND16_MM: |
| 11288 | case Mips::OR16_MM: |
| 11289 | case Mips::XOR16_MM: { |
| 11290 | switch (OpNum) { |
| 11291 | case 2: |
| 11292 | // op: rt |
| 11293 | return 3; |
| 11294 | case 1: |
| 11295 | // op: rs |
| 11296 | return 0; |
| 11297 | } |
| 11298 | break; |
| 11299 | } |
| 11300 | case Mips::AND16_MMR6: |
| 11301 | case Mips::OR16_MMR6: |
| 11302 | case Mips::XOR16_MMR6: { |
| 11303 | switch (OpNum) { |
| 11304 | case 2: |
| 11305 | // op: rt |
| 11306 | return 7; |
| 11307 | case 1: |
| 11308 | // op: rs |
| 11309 | return 4; |
| 11310 | } |
| 11311 | break; |
| 11312 | } |
| 11313 | case Mips::SllX16: |
| 11314 | case Mips::SraX16: |
| 11315 | case Mips::SrlX16: { |
| 11316 | switch (OpNum) { |
| 11317 | case 2: |
| 11318 | // op: sa6 |
| 11319 | return 21; |
| 11320 | case 0: |
| 11321 | // op: rx |
| 11322 | return 8; |
| 11323 | case 1: |
| 11324 | // op: ry |
| 11325 | return 5; |
| 11326 | } |
| 11327 | break; |
| 11328 | } |
| 11329 | case Mips::ANDI_B: |
| 11330 | case Mips::NORI_B: |
| 11331 | case Mips::ORI_B: |
| 11332 | case Mips::SHF_B: |
| 11333 | case Mips::SHF_H: |
| 11334 | case Mips::SHF_W: |
| 11335 | case Mips::XORI_B: { |
| 11336 | switch (OpNum) { |
| 11337 | case 2: |
| 11338 | // op: u8 |
| 11339 | return 16; |
| 11340 | case 1: |
| 11341 | // op: ws |
| 11342 | return 11; |
| 11343 | case 0: |
| 11344 | // op: wd |
| 11345 | return 6; |
| 11346 | } |
| 11347 | break; |
| 11348 | } |
| 11349 | case Mips::BINSLI_B: |
| 11350 | case Mips::BINSLI_D: |
| 11351 | case Mips::BINSLI_H: |
| 11352 | case Mips::BINSLI_W: |
| 11353 | case Mips::BINSRI_B: |
| 11354 | case Mips::BINSRI_D: |
| 11355 | case Mips::BINSRI_H: |
| 11356 | case Mips::BINSRI_W: { |
| 11357 | switch (OpNum) { |
| 11358 | case 2: |
| 11359 | // op: ws |
| 11360 | return 11; |
| 11361 | case 0: |
| 11362 | // op: wd |
| 11363 | return 6; |
| 11364 | case 3: |
| 11365 | // op: m |
| 11366 | return 16; |
| 11367 | } |
| 11368 | break; |
| 11369 | } |
| 11370 | case Mips::ADDS_A_B: |
| 11371 | case Mips::ADDS_A_D: |
| 11372 | case Mips::ADDS_A_H: |
| 11373 | case Mips::ADDS_A_W: |
| 11374 | case Mips::ADDS_S_B: |
| 11375 | case Mips::ADDS_S_D: |
| 11376 | case Mips::ADDS_S_H: |
| 11377 | case Mips::ADDS_S_W: |
| 11378 | case Mips::ADDS_U_B: |
| 11379 | case Mips::ADDS_U_D: |
| 11380 | case Mips::ADDS_U_H: |
| 11381 | case Mips::ADDS_U_W: |
| 11382 | case Mips::ADDV_B: |
| 11383 | case Mips::ADDV_D: |
| 11384 | case Mips::ADDV_H: |
| 11385 | case Mips::ADDV_W: |
| 11386 | case Mips::ADD_A_B: |
| 11387 | case Mips::ADD_A_D: |
| 11388 | case Mips::ADD_A_H: |
| 11389 | case Mips::ADD_A_W: |
| 11390 | case Mips::AND_V: |
| 11391 | case Mips::ASUB_S_B: |
| 11392 | case Mips::ASUB_S_D: |
| 11393 | case Mips::ASUB_S_H: |
| 11394 | case Mips::ASUB_S_W: |
| 11395 | case Mips::ASUB_U_B: |
| 11396 | case Mips::ASUB_U_D: |
| 11397 | case Mips::ASUB_U_H: |
| 11398 | case Mips::ASUB_U_W: |
| 11399 | case Mips::AVER_S_B: |
| 11400 | case Mips::AVER_S_D: |
| 11401 | case Mips::AVER_S_H: |
| 11402 | case Mips::AVER_S_W: |
| 11403 | case Mips::AVER_U_B: |
| 11404 | case Mips::AVER_U_D: |
| 11405 | case Mips::AVER_U_H: |
| 11406 | case Mips::AVER_U_W: |
| 11407 | case Mips::AVE_S_B: |
| 11408 | case Mips::AVE_S_D: |
| 11409 | case Mips::AVE_S_H: |
| 11410 | case Mips::AVE_S_W: |
| 11411 | case Mips::AVE_U_B: |
| 11412 | case Mips::AVE_U_D: |
| 11413 | case Mips::AVE_U_H: |
| 11414 | case Mips::AVE_U_W: |
| 11415 | case Mips::BCLR_B: |
| 11416 | case Mips::BCLR_D: |
| 11417 | case Mips::BCLR_H: |
| 11418 | case Mips::BCLR_W: |
| 11419 | case Mips::BNEG_B: |
| 11420 | case Mips::BNEG_D: |
| 11421 | case Mips::BNEG_H: |
| 11422 | case Mips::BNEG_W: |
| 11423 | case Mips::BSET_B: |
| 11424 | case Mips::BSET_D: |
| 11425 | case Mips::BSET_H: |
| 11426 | case Mips::BSET_W: |
| 11427 | case Mips::CEQ_B: |
| 11428 | case Mips::CEQ_D: |
| 11429 | case Mips::CEQ_H: |
| 11430 | case Mips::CEQ_W: |
| 11431 | case Mips::CLE_S_B: |
| 11432 | case Mips::CLE_S_D: |
| 11433 | case Mips::CLE_S_H: |
| 11434 | case Mips::CLE_S_W: |
| 11435 | case Mips::CLE_U_B: |
| 11436 | case Mips::CLE_U_D: |
| 11437 | case Mips::CLE_U_H: |
| 11438 | case Mips::CLE_U_W: |
| 11439 | case Mips::CLT_S_B: |
| 11440 | case Mips::CLT_S_D: |
| 11441 | case Mips::CLT_S_H: |
| 11442 | case Mips::CLT_S_W: |
| 11443 | case Mips::CLT_U_B: |
| 11444 | case Mips::CLT_U_D: |
| 11445 | case Mips::CLT_U_H: |
| 11446 | case Mips::CLT_U_W: |
| 11447 | case Mips::DIV_S_B: |
| 11448 | case Mips::DIV_S_D: |
| 11449 | case Mips::DIV_S_H: |
| 11450 | case Mips::DIV_S_W: |
| 11451 | case Mips::DIV_U_B: |
| 11452 | case Mips::DIV_U_D: |
| 11453 | case Mips::DIV_U_H: |
| 11454 | case Mips::DIV_U_W: |
| 11455 | case Mips::DOTP_S_D: |
| 11456 | case Mips::DOTP_S_H: |
| 11457 | case Mips::DOTP_S_W: |
| 11458 | case Mips::DOTP_U_D: |
| 11459 | case Mips::DOTP_U_H: |
| 11460 | case Mips::DOTP_U_W: |
| 11461 | case Mips::FADD_D: |
| 11462 | case Mips::FADD_W: |
| 11463 | case Mips::FCAF_D: |
| 11464 | case Mips::FCAF_W: |
| 11465 | case Mips::FCEQ_D: |
| 11466 | case Mips::FCEQ_W: |
| 11467 | case Mips::FCLE_D: |
| 11468 | case Mips::FCLE_W: |
| 11469 | case Mips::FCLT_D: |
| 11470 | case Mips::FCLT_W: |
| 11471 | case Mips::FCNE_D: |
| 11472 | case Mips::FCNE_W: |
| 11473 | case Mips::FCOR_D: |
| 11474 | case Mips::FCOR_W: |
| 11475 | case Mips::FCUEQ_D: |
| 11476 | case Mips::FCUEQ_W: |
| 11477 | case Mips::FCULE_D: |
| 11478 | case Mips::FCULE_W: |
| 11479 | case Mips::FCULT_D: |
| 11480 | case Mips::FCULT_W: |
| 11481 | case Mips::FCUNE_D: |
| 11482 | case Mips::FCUNE_W: |
| 11483 | case Mips::FCUN_D: |
| 11484 | case Mips::FCUN_W: |
| 11485 | case Mips::FDIV_D: |
| 11486 | case Mips::FDIV_W: |
| 11487 | case Mips::FEXDO_H: |
| 11488 | case Mips::FEXDO_W: |
| 11489 | case Mips::FEXP2_D: |
| 11490 | case Mips::FEXP2_W: |
| 11491 | case Mips::FMAX_A_D: |
| 11492 | case Mips::FMAX_A_W: |
| 11493 | case Mips::FMAX_D: |
| 11494 | case Mips::FMAX_W: |
| 11495 | case Mips::FMIN_A_D: |
| 11496 | case Mips::FMIN_A_W: |
| 11497 | case Mips::FMIN_D: |
| 11498 | case Mips::FMIN_W: |
| 11499 | case Mips::FMUL_D: |
| 11500 | case Mips::FMUL_W: |
| 11501 | case Mips::FSAF_D: |
| 11502 | case Mips::FSAF_W: |
| 11503 | case Mips::FSEQ_D: |
| 11504 | case Mips::FSEQ_W: |
| 11505 | case Mips::FSLE_D: |
| 11506 | case Mips::FSLE_W: |
| 11507 | case Mips::FSLT_D: |
| 11508 | case Mips::FSLT_W: |
| 11509 | case Mips::FSNE_D: |
| 11510 | case Mips::FSNE_W: |
| 11511 | case Mips::FSOR_D: |
| 11512 | case Mips::FSOR_W: |
| 11513 | case Mips::FSUB_D: |
| 11514 | case Mips::FSUB_W: |
| 11515 | case Mips::FSUEQ_D: |
| 11516 | case Mips::FSUEQ_W: |
| 11517 | case Mips::FSULE_D: |
| 11518 | case Mips::FSULE_W: |
| 11519 | case Mips::FSULT_D: |
| 11520 | case Mips::FSULT_W: |
| 11521 | case Mips::FSUNE_D: |
| 11522 | case Mips::FSUNE_W: |
| 11523 | case Mips::FSUN_D: |
| 11524 | case Mips::FSUN_W: |
| 11525 | case Mips::FTQ_H: |
| 11526 | case Mips::FTQ_W: |
| 11527 | case Mips::HADD_S_D: |
| 11528 | case Mips::HADD_S_H: |
| 11529 | case Mips::HADD_S_W: |
| 11530 | case Mips::HADD_U_D: |
| 11531 | case Mips::HADD_U_H: |
| 11532 | case Mips::HADD_U_W: |
| 11533 | case Mips::HSUB_S_D: |
| 11534 | case Mips::HSUB_S_H: |
| 11535 | case Mips::HSUB_S_W: |
| 11536 | case Mips::HSUB_U_D: |
| 11537 | case Mips::HSUB_U_H: |
| 11538 | case Mips::HSUB_U_W: |
| 11539 | case Mips::ILVEV_B: |
| 11540 | case Mips::ILVEV_D: |
| 11541 | case Mips::ILVEV_H: |
| 11542 | case Mips::ILVEV_W: |
| 11543 | case Mips::ILVL_B: |
| 11544 | case Mips::ILVL_D: |
| 11545 | case Mips::ILVL_H: |
| 11546 | case Mips::ILVL_W: |
| 11547 | case Mips::ILVOD_B: |
| 11548 | case Mips::ILVOD_D: |
| 11549 | case Mips::ILVOD_H: |
| 11550 | case Mips::ILVOD_W: |
| 11551 | case Mips::ILVR_B: |
| 11552 | case Mips::ILVR_D: |
| 11553 | case Mips::ILVR_H: |
| 11554 | case Mips::ILVR_W: |
| 11555 | case Mips::MAX_A_B: |
| 11556 | case Mips::MAX_A_D: |
| 11557 | case Mips::MAX_A_H: |
| 11558 | case Mips::MAX_A_W: |
| 11559 | case Mips::MAX_S_B: |
| 11560 | case Mips::MAX_S_D: |
| 11561 | case Mips::MAX_S_H: |
| 11562 | case Mips::MAX_S_W: |
| 11563 | case Mips::MAX_U_B: |
| 11564 | case Mips::MAX_U_D: |
| 11565 | case Mips::MAX_U_H: |
| 11566 | case Mips::MAX_U_W: |
| 11567 | case Mips::MIN_A_B: |
| 11568 | case Mips::MIN_A_D: |
| 11569 | case Mips::MIN_A_H: |
| 11570 | case Mips::MIN_A_W: |
| 11571 | case Mips::MIN_S_B: |
| 11572 | case Mips::MIN_S_D: |
| 11573 | case Mips::MIN_S_H: |
| 11574 | case Mips::MIN_S_W: |
| 11575 | case Mips::MIN_U_B: |
| 11576 | case Mips::MIN_U_D: |
| 11577 | case Mips::MIN_U_H: |
| 11578 | case Mips::MIN_U_W: |
| 11579 | case Mips::MOD_S_B: |
| 11580 | case Mips::MOD_S_D: |
| 11581 | case Mips::MOD_S_H: |
| 11582 | case Mips::MOD_S_W: |
| 11583 | case Mips::MOD_U_B: |
| 11584 | case Mips::MOD_U_D: |
| 11585 | case Mips::MOD_U_H: |
| 11586 | case Mips::MOD_U_W: |
| 11587 | case Mips::MULR_Q_H: |
| 11588 | case Mips::MULR_Q_W: |
| 11589 | case Mips::MULV_B: |
| 11590 | case Mips::MULV_D: |
| 11591 | case Mips::MULV_H: |
| 11592 | case Mips::MULV_W: |
| 11593 | case Mips::MUL_Q_H: |
| 11594 | case Mips::MUL_Q_W: |
| 11595 | case Mips::NOR_V: |
| 11596 | case Mips::OR_V: |
| 11597 | case Mips::PCKEV_B: |
| 11598 | case Mips::PCKEV_D: |
| 11599 | case Mips::PCKEV_H: |
| 11600 | case Mips::PCKEV_W: |
| 11601 | case Mips::PCKOD_B: |
| 11602 | case Mips::PCKOD_D: |
| 11603 | case Mips::PCKOD_H: |
| 11604 | case Mips::PCKOD_W: |
| 11605 | case Mips::SLL_B: |
| 11606 | case Mips::SLL_D: |
| 11607 | case Mips::SLL_H: |
| 11608 | case Mips::SLL_W: |
| 11609 | case Mips::SRAR_B: |
| 11610 | case Mips::SRAR_D: |
| 11611 | case Mips::SRAR_H: |
| 11612 | case Mips::SRAR_W: |
| 11613 | case Mips::SRA_B: |
| 11614 | case Mips::SRA_D: |
| 11615 | case Mips::SRA_H: |
| 11616 | case Mips::SRA_W: |
| 11617 | case Mips::SRLR_B: |
| 11618 | case Mips::SRLR_D: |
| 11619 | case Mips::SRLR_H: |
| 11620 | case Mips::SRLR_W: |
| 11621 | case Mips::SRL_B: |
| 11622 | case Mips::SRL_D: |
| 11623 | case Mips::SRL_H: |
| 11624 | case Mips::SRL_W: |
| 11625 | case Mips::SUBSUS_U_B: |
| 11626 | case Mips::SUBSUS_U_D: |
| 11627 | case Mips::SUBSUS_U_H: |
| 11628 | case Mips::SUBSUS_U_W: |
| 11629 | case Mips::SUBSUU_S_B: |
| 11630 | case Mips::SUBSUU_S_D: |
| 11631 | case Mips::SUBSUU_S_H: |
| 11632 | case Mips::SUBSUU_S_W: |
| 11633 | case Mips::SUBS_S_B: |
| 11634 | case Mips::SUBS_S_D: |
| 11635 | case Mips::SUBS_S_H: |
| 11636 | case Mips::SUBS_S_W: |
| 11637 | case Mips::SUBS_U_B: |
| 11638 | case Mips::SUBS_U_D: |
| 11639 | case Mips::SUBS_U_H: |
| 11640 | case Mips::SUBS_U_W: |
| 11641 | case Mips::SUBV_B: |
| 11642 | case Mips::SUBV_D: |
| 11643 | case Mips::SUBV_H: |
| 11644 | case Mips::SUBV_W: |
| 11645 | case Mips::XOR_V: { |
| 11646 | switch (OpNum) { |
| 11647 | case 2: |
| 11648 | // op: wt |
| 11649 | return 16; |
| 11650 | case 1: |
| 11651 | // op: ws |
| 11652 | return 11; |
| 11653 | case 0: |
| 11654 | // op: wd |
| 11655 | return 6; |
| 11656 | } |
| 11657 | break; |
| 11658 | } |
| 11659 | case Mips::MADDF_D: |
| 11660 | case Mips::MADDF_S: |
| 11661 | case Mips::MSUBF_D: |
| 11662 | case Mips::MSUBF_S: |
| 11663 | case Mips::SEL_D: |
| 11664 | case Mips::SEL_S: { |
| 11665 | switch (OpNum) { |
| 11666 | case 3: |
| 11667 | // op: ft |
| 11668 | return 16; |
| 11669 | case 2: |
| 11670 | // op: fs |
| 11671 | return 11; |
| 11672 | case 0: |
| 11673 | // op: fd |
| 11674 | return 6; |
| 11675 | } |
| 11676 | break; |
| 11677 | } |
| 11678 | case Mips::MADD_D32_MM: |
| 11679 | case Mips::MADD_S_MM: |
| 11680 | case Mips::MSUB_D32_MM: |
| 11681 | case Mips::MSUB_S_MM: |
| 11682 | case Mips::NMADD_D32_MM: |
| 11683 | case Mips::NMADD_S_MM: |
| 11684 | case Mips::NMSUB_D32_MM: |
| 11685 | case Mips::NMSUB_S_MM: { |
| 11686 | switch (OpNum) { |
| 11687 | case 3: |
| 11688 | // op: ft |
| 11689 | return 21; |
| 11690 | case 2: |
| 11691 | // op: fs |
| 11692 | return 16; |
| 11693 | case 0: |
| 11694 | // op: fd |
| 11695 | return 11; |
| 11696 | case 1: |
| 11697 | // op: fr |
| 11698 | return 6; |
| 11699 | } |
| 11700 | break; |
| 11701 | } |
| 11702 | case Mips::MADDF_D_MMR6: |
| 11703 | case Mips::MADDF_S_MMR6: |
| 11704 | case Mips::MSUBF_D_MMR6: |
| 11705 | case Mips::MSUBF_S_MMR6: |
| 11706 | case Mips::SEL_D_MMR6: |
| 11707 | case Mips::SEL_S_MMR6: { |
| 11708 | switch (OpNum) { |
| 11709 | case 3: |
| 11710 | // op: ft |
| 11711 | return 21; |
| 11712 | case 2: |
| 11713 | // op: fs |
| 11714 | return 16; |
| 11715 | case 0: |
| 11716 | // op: fd |
| 11717 | return 11; |
| 11718 | } |
| 11719 | break; |
| 11720 | } |
| 11721 | case Mips::INSERT_B: |
| 11722 | case Mips::INSERT_D: |
| 11723 | case Mips::INSERT_H: |
| 11724 | case Mips::INSERT_W: { |
| 11725 | switch (OpNum) { |
| 11726 | case 3: |
| 11727 | // op: n |
| 11728 | return 16; |
| 11729 | case 2: |
| 11730 | // op: rs |
| 11731 | return 11; |
| 11732 | case 0: |
| 11733 | // op: wd |
| 11734 | return 6; |
| 11735 | } |
| 11736 | break; |
| 11737 | } |
| 11738 | case Mips::SLDI_B: |
| 11739 | case Mips::SLDI_D: |
| 11740 | case Mips::SLDI_H: |
| 11741 | case Mips::SLDI_W: { |
| 11742 | switch (OpNum) { |
| 11743 | case 3: |
| 11744 | // op: n |
| 11745 | return 16; |
| 11746 | case 2: |
| 11747 | // op: ws |
| 11748 | return 11; |
| 11749 | case 0: |
| 11750 | // op: wd |
| 11751 | return 6; |
| 11752 | } |
| 11753 | break; |
| 11754 | } |
| 11755 | case Mips::SLD_B: |
| 11756 | case Mips::SLD_D: |
| 11757 | case Mips::SLD_H: |
| 11758 | case Mips::SLD_W: { |
| 11759 | switch (OpNum) { |
| 11760 | case 3: |
| 11761 | // op: rt |
| 11762 | return 16; |
| 11763 | case 2: |
| 11764 | // op: ws |
| 11765 | return 11; |
| 11766 | case 0: |
| 11767 | // op: wd |
| 11768 | return 6; |
| 11769 | } |
| 11770 | break; |
| 11771 | } |
| 11772 | case Mips::MOVEP_MMR6: { |
| 11773 | switch (OpNum) { |
| 11774 | case 3: |
| 11775 | // op: rt |
| 11776 | return 4; |
| 11777 | case 2: |
| 11778 | // op: rs |
| 11779 | return 0; |
| 11780 | } |
| 11781 | break; |
| 11782 | } |
| 11783 | case Mips::MOVEP_MM: { |
| 11784 | switch (OpNum) { |
| 11785 | case 3: |
| 11786 | // op: rt |
| 11787 | return 4; |
| 11788 | case 2: |
| 11789 | // op: rs |
| 11790 | return 1; |
| 11791 | } |
| 11792 | break; |
| 11793 | } |
| 11794 | case Mips::BMNZI_B: |
| 11795 | case Mips::BMZI_B: |
| 11796 | case Mips::BSELI_B: { |
| 11797 | switch (OpNum) { |
| 11798 | case 3: |
| 11799 | // op: u8 |
| 11800 | return 16; |
| 11801 | case 2: |
| 11802 | // op: ws |
| 11803 | return 11; |
| 11804 | case 0: |
| 11805 | // op: wd |
| 11806 | return 6; |
| 11807 | } |
| 11808 | break; |
| 11809 | } |
| 11810 | case Mips::BINSL_B: |
| 11811 | case Mips::BINSL_D: |
| 11812 | case Mips::BINSL_H: |
| 11813 | case Mips::BINSL_W: |
| 11814 | case Mips::BINSR_B: |
| 11815 | case Mips::BINSR_D: |
| 11816 | case Mips::BINSR_H: |
| 11817 | case Mips::BINSR_W: |
| 11818 | case Mips::BMNZ_V: |
| 11819 | case Mips::BMZ_V: |
| 11820 | case Mips::BSEL_V: |
| 11821 | case Mips::DPADD_S_D: |
| 11822 | case Mips::DPADD_S_H: |
| 11823 | case Mips::DPADD_S_W: |
| 11824 | case Mips::DPADD_U_D: |
| 11825 | case Mips::DPADD_U_H: |
| 11826 | case Mips::DPADD_U_W: |
| 11827 | case Mips::DPSUB_S_D: |
| 11828 | case Mips::DPSUB_S_H: |
| 11829 | case Mips::DPSUB_S_W: |
| 11830 | case Mips::DPSUB_U_D: |
| 11831 | case Mips::DPSUB_U_H: |
| 11832 | case Mips::DPSUB_U_W: |
| 11833 | case Mips::FMADD_D: |
| 11834 | case Mips::FMADD_W: |
| 11835 | case Mips::FMSUB_D: |
| 11836 | case Mips::FMSUB_W: |
| 11837 | case Mips::MADDR_Q_H: |
| 11838 | case Mips::MADDR_Q_W: |
| 11839 | case Mips::MADDV_B: |
| 11840 | case Mips::MADDV_D: |
| 11841 | case Mips::MADDV_H: |
| 11842 | case Mips::MADDV_W: |
| 11843 | case Mips::MADD_Q_H: |
| 11844 | case Mips::MADD_Q_W: |
| 11845 | case Mips::MSUBR_Q_H: |
| 11846 | case Mips::MSUBR_Q_W: |
| 11847 | case Mips::MSUBV_B: |
| 11848 | case Mips::MSUBV_D: |
| 11849 | case Mips::MSUBV_H: |
| 11850 | case Mips::MSUBV_W: |
| 11851 | case Mips::MSUB_Q_H: |
| 11852 | case Mips::MSUB_Q_W: |
| 11853 | case Mips::VSHF_B: |
| 11854 | case Mips::VSHF_D: |
| 11855 | case Mips::VSHF_H: |
| 11856 | case Mips::VSHF_W: { |
| 11857 | switch (OpNum) { |
| 11858 | case 3: |
| 11859 | // op: wt |
| 11860 | return 16; |
| 11861 | case 2: |
| 11862 | // op: ws |
| 11863 | return 11; |
| 11864 | case 0: |
| 11865 | // op: wd |
| 11866 | return 6; |
| 11867 | } |
| 11868 | break; |
| 11869 | } |
| 11870 | default: |
| 11871 | reportUnsupportedInst(MI); |
| 11872 | } |
| 11873 | reportUnsupportedOperand(MI, OpNum); |
| 11874 | } |
| 11875 | |
| 11876 | #endif // GET_OPERAND_BIT_OFFSET |
| 11877 | |
| 11878 |
Generated while processing llvm_projects/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
Generated on 2026-Oct-10 from project llvm_projects revision b1dd93c6a
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