1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(2080375378), // ABSQ_S_PH
14 UINT64_C(4412), // ABSQ_S_PH_MM
15 UINT64_C(2080374866), // ABSQ_S_QB
16 UINT64_C(316), // ABSQ_S_QB_MMR2
17 UINT64_C(2080375890), // ABSQ_S_W
18 UINT64_C(8508), // ABSQ_S_W_MM
19 UINT64_C(32), // ADD
20 UINT64_C(3959422976), // ADDIUPC
21 UINT64_C(2013265920), // ADDIUPC_MM
22 UINT64_C(2013265920), // ADDIUPC_MMR6
23 UINT64_C(27649), // ADDIUR1SP_MM
24 UINT64_C(27648), // ADDIUR2_MM
25 UINT64_C(19456), // ADDIUS5_MM
26 UINT64_C(19457), // ADDIUSP_MM
27 UINT64_C(805306368), // ADDIU_MMR6
28 UINT64_C(2080375320), // ADDQH_PH
29 UINT64_C(77), // ADDQH_PH_MMR2
30 UINT64_C(2080375448), // ADDQH_R_PH
31 UINT64_C(1101), // ADDQH_R_PH_MMR2
32 UINT64_C(2080375960), // ADDQH_R_W
33 UINT64_C(1165), // ADDQH_R_W_MMR2
34 UINT64_C(2080375832), // ADDQH_W
35 UINT64_C(141), // ADDQH_W_MMR2
36 UINT64_C(2080375440), // ADDQ_PH
37 UINT64_C(13), // ADDQ_PH_MM
38 UINT64_C(2080375696), // ADDQ_S_PH
39 UINT64_C(1037), // ADDQ_S_PH_MM
40 UINT64_C(2080376208), // ADDQ_S_W
41 UINT64_C(773), // ADDQ_S_W_MM
42 UINT64_C(1186988056), // ADDR_PS64
43 UINT64_C(2080375824), // ADDSC
44 UINT64_C(901), // ADDSC_MM
45 UINT64_C(2021654544), // ADDS_A_B
46 UINT64_C(2027946000), // ADDS_A_D
47 UINT64_C(2023751696), // ADDS_A_H
48 UINT64_C(2025848848), // ADDS_A_W
49 UINT64_C(2030043152), // ADDS_S_B
50 UINT64_C(2036334608), // ADDS_S_D
51 UINT64_C(2032140304), // ADDS_S_H
52 UINT64_C(2034237456), // ADDS_S_W
53 UINT64_C(2038431760), // ADDS_U_B
54 UINT64_C(2044723216), // ADDS_U_D
55 UINT64_C(2040528912), // ADDS_U_H
56 UINT64_C(2042626064), // ADDS_U_W
57 UINT64_C(1024), // ADDU16_MM
58 UINT64_C(1024), // ADDU16_MMR6
59 UINT64_C(2080374808), // ADDUH_QB
60 UINT64_C(333), // ADDUH_QB_MMR2
61 UINT64_C(2080374936), // ADDUH_R_QB
62 UINT64_C(1357), // ADDUH_R_QB_MMR2
63 UINT64_C(336), // ADDU_MMR6
64 UINT64_C(2080375312), // ADDU_PH
65 UINT64_C(269), // ADDU_PH_MMR2
66 UINT64_C(2080374800), // ADDU_QB
67 UINT64_C(205), // ADDU_QB_MM
68 UINT64_C(2080375568), // ADDU_S_PH
69 UINT64_C(1293), // ADDU_S_PH_MMR2
70 UINT64_C(2080375056), // ADDU_S_QB
71 UINT64_C(1229), // ADDU_S_QB_MM
72 UINT64_C(2013265926), // ADDVI_B
73 UINT64_C(2019557382), // ADDVI_D
74 UINT64_C(2015363078), // ADDVI_H
75 UINT64_C(2017460230), // ADDVI_W
76 UINT64_C(2013265934), // ADDV_B
77 UINT64_C(2019557390), // ADDV_D
78 UINT64_C(2015363086), // ADDV_H
79 UINT64_C(2017460238), // ADDV_W
80 UINT64_C(2080375888), // ADDWC
81 UINT64_C(965), // ADDWC_MM
82 UINT64_C(2013265936), // ADD_A_B
83 UINT64_C(2019557392), // ADD_A_D
84 UINT64_C(2015363088), // ADD_A_H
85 UINT64_C(2017460240), // ADD_A_W
86 UINT64_C(272), // ADD_MM
87 UINT64_C(272), // ADD_MMR6
88 UINT64_C(536870912), // ADDi
89 UINT64_C(268435456), // ADDi_MM
90 UINT64_C(603979776), // ADDiu
91 UINT64_C(805306368), // ADDiu_MM
92 UINT64_C(33), // ADDu
93 UINT64_C(336), // ADDu_MM
94 UINT64_C(2080375328), // ALIGN
95 UINT64_C(31), // ALIGN_MMR6
96 UINT64_C(3961454592), // ALUIPC
97 UINT64_C(2015297536), // ALUIPC_MMR6
98 UINT64_C(36), // AND
99 UINT64_C(17536), // AND16_MM
100 UINT64_C(17409), // AND16_MMR6
101 UINT64_C(36), // AND64
102 UINT64_C(11264), // ANDI16_MM
103 UINT64_C(11264), // ANDI16_MMR6
104 UINT64_C(2013265920), // ANDI_B
105 UINT64_C(3489660928), // ANDI_MMR6
106 UINT64_C(592), // AND_MM
107 UINT64_C(592), // AND_MMR6
108 UINT64_C(2013265950), // AND_V
109 UINT64_C(805306368), // ANDi
110 UINT64_C(805306368), // ANDi64
111 UINT64_C(3489660928), // ANDi_MM
112 UINT64_C(2080374833), // APPEND
113 UINT64_C(533), // APPEND_MMR2
114 UINT64_C(2046820369), // ASUB_S_B
115 UINT64_C(2053111825), // ASUB_S_D
116 UINT64_C(2048917521), // ASUB_S_H
117 UINT64_C(2051014673), // ASUB_S_W
118 UINT64_C(2055208977), // ASUB_U_B
119 UINT64_C(2061500433), // ASUB_U_D
120 UINT64_C(2057306129), // ASUB_U_H
121 UINT64_C(2059403281), // ASUB_U_W
122 UINT64_C(1006632960), // AUI
123 UINT64_C(3961389056), // AUIPC
124 UINT64_C(2015232000), // AUIPC_MMR6
125 UINT64_C(268435456), // AUI_MMR6
126 UINT64_C(2063597584), // AVER_S_B
127 UINT64_C(2069889040), // AVER_S_D
128 UINT64_C(2065694736), // AVER_S_H
129 UINT64_C(2067791888), // AVER_S_W
130 UINT64_C(2071986192), // AVER_U_B
131 UINT64_C(2078277648), // AVER_U_D
132 UINT64_C(2074083344), // AVER_U_H
133 UINT64_C(2076180496), // AVER_U_W
134 UINT64_C(2046820368), // AVE_S_B
135 UINT64_C(2053111824), // AVE_S_D
136 UINT64_C(2048917520), // AVE_S_H
137 UINT64_C(2051014672), // AVE_S_W
138 UINT64_C(2055208976), // AVE_U_B
139 UINT64_C(2061500432), // AVE_U_D
140 UINT64_C(2057306128), // AVE_U_H
141 UINT64_C(2059403280), // AVE_U_W
142 UINT64_C(4026550272), // AddiuRxImmX16
143 UINT64_C(4026533888), // AddiuRxPcImmX16
144 UINT64_C(18432), // AddiuRxRxImm16
145 UINT64_C(4026550272), // AddiuRxRxImmX16
146 UINT64_C(4026548224), // AddiuRxRyOffMemX16
147 UINT64_C(25344), // AddiuSpImm16
148 UINT64_C(4026544896), // AddiuSpImmX16
149 UINT64_C(57345), // AdduRxRyRz16
150 UINT64_C(59404), // AndRxRxRy16
151 UINT64_C(52224), // B16_MM
152 UINT64_C(1879048232), // BADDu
153 UINT64_C(68222976), // BAL
154 UINT64_C(3892314112), // BALC
155 UINT64_C(3019898880), // BALC_MMR6
156 UINT64_C(2080375857), // BALIGN
157 UINT64_C(2236), // BALIGN_MMR2
158 UINT64_C(3355443200), // BBIT0
159 UINT64_C(3623878656), // BBIT032
160 UINT64_C(3892314112), // BBIT1
161 UINT64_C(4160749568), // BBIT132
162 UINT64_C(3355443200), // BC
163 UINT64_C(52224), // BC16_MMR6
164 UINT64_C(1159725056), // BC1EQZ
165 UINT64_C(1090519040), // BC1EQZC_MMR6
166 UINT64_C(1157627904), // BC1F
167 UINT64_C(1157758976), // BC1FL
168 UINT64_C(1132462080), // BC1F_MM
169 UINT64_C(1168113664), // BC1NEZ
170 UINT64_C(1092616192), // BC1NEZC_MMR6
171 UINT64_C(1157693440), // BC1T
172 UINT64_C(1157824512), // BC1TL
173 UINT64_C(1134559232), // BC1T_MM
174 UINT64_C(1226833920), // BC2EQZ
175 UINT64_C(1094713344), // BC2EQZC_MMR6
176 UINT64_C(1235222528), // BC2NEZ
177 UINT64_C(1096810496), // BC2NEZC_MMR6
178 UINT64_C(2045771785), // BCLRI_B
179 UINT64_C(2038431753), // BCLRI_D
180 UINT64_C(2044723209), // BCLRI_H
181 UINT64_C(2042626057), // BCLRI_W
182 UINT64_C(2038431757), // BCLR_B
183 UINT64_C(2044723213), // BCLR_D
184 UINT64_C(2040528909), // BCLR_H
185 UINT64_C(2042626061), // BCLR_W
186 UINT64_C(2483027968), // BC_MMR6
187 UINT64_C(268435456), // BEQ
188 UINT64_C(268435456), // BEQ64
189 UINT64_C(536870912), // BEQC
190 UINT64_C(536870912), // BEQC64
191 UINT64_C(1946157056), // BEQC_MMR6
192 UINT64_C(1342177280), // BEQL
193 UINT64_C(35840), // BEQZ16_MM
194 UINT64_C(536870912), // BEQZALC
195 UINT64_C(1946157056), // BEQZALC_MMR6
196 UINT64_C(3623878656), // BEQZC
197 UINT64_C(35840), // BEQZC16_MMR6
198 UINT64_C(3623878656), // BEQZC64
199 UINT64_C(1088421888), // BEQZC_MM
200 UINT64_C(2147483648), // BEQZC_MMR6
201 UINT64_C(2483027968), // BEQ_MM
202 UINT64_C(1476395008), // BGEC
203 UINT64_C(1476395008), // BGEC64
204 UINT64_C(4093640704), // BGEC_MMR6
205 UINT64_C(402653184), // BGEUC
206 UINT64_C(402653184), // BGEUC64
207 UINT64_C(3221225472), // BGEUC_MMR6
208 UINT64_C(67174400), // BGEZ
209 UINT64_C(67174400), // BGEZ64
210 UINT64_C(68222976), // BGEZAL
211 UINT64_C(402653184), // BGEZALC
212 UINT64_C(3221225472), // BGEZALC_MMR6
213 UINT64_C(68354048), // BGEZALL
214 UINT64_C(1113587712), // BGEZALS_MM
215 UINT64_C(1080033280), // BGEZAL_MM
216 UINT64_C(1476395008), // BGEZC
217 UINT64_C(1476395008), // BGEZC64
218 UINT64_C(4093640704), // BGEZC_MMR6
219 UINT64_C(67305472), // BGEZL
220 UINT64_C(1077936128), // BGEZ_MM
221 UINT64_C(469762048), // BGTZ
222 UINT64_C(469762048), // BGTZ64
223 UINT64_C(469762048), // BGTZALC
224 UINT64_C(3758096384), // BGTZALC_MMR6
225 UINT64_C(1543503872), // BGTZC
226 UINT64_C(1543503872), // BGTZC64
227 UINT64_C(3556769792), // BGTZC_MMR6
228 UINT64_C(1543503872), // BGTZL
229 UINT64_C(1086324736), // BGTZ_MM
230 UINT64_C(2070937609), // BINSLI_B
231 UINT64_C(2063597577), // BINSLI_D
232 UINT64_C(2069889033), // BINSLI_H
233 UINT64_C(2067791881), // BINSLI_W
234 UINT64_C(2063597581), // BINSL_B
235 UINT64_C(2069889037), // BINSL_D
236 UINT64_C(2065694733), // BINSL_H
237 UINT64_C(2067791885), // BINSL_W
238 UINT64_C(2079326217), // BINSRI_B
239 UINT64_C(2071986185), // BINSRI_D
240 UINT64_C(2078277641), // BINSRI_H
241 UINT64_C(2076180489), // BINSRI_W
242 UINT64_C(2071986189), // BINSR_B
243 UINT64_C(2078277645), // BINSR_D
244 UINT64_C(2074083341), // BINSR_H
245 UINT64_C(2076180493), // BINSR_W
246 UINT64_C(2080376530), // BITREV
247 UINT64_C(12604), // BITREV_MM
248 UINT64_C(2080374816), // BITSWAP
249 UINT64_C(2876), // BITSWAP_MMR6
250 UINT64_C(402653184), // BLEZ
251 UINT64_C(402653184), // BLEZ64
252 UINT64_C(402653184), // BLEZALC
253 UINT64_C(3221225472), // BLEZALC_MMR6
254 UINT64_C(1476395008), // BLEZC
255 UINT64_C(1476395008), // BLEZC64
256 UINT64_C(4093640704), // BLEZC_MMR6
257 UINT64_C(1476395008), // BLEZL
258 UINT64_C(1082130432), // BLEZ_MM
259 UINT64_C(1543503872), // BLTC
260 UINT64_C(1543503872), // BLTC64
261 UINT64_C(3556769792), // BLTC_MMR6
262 UINT64_C(469762048), // BLTUC
263 UINT64_C(469762048), // BLTUC64
264 UINT64_C(3758096384), // BLTUC_MMR6
265 UINT64_C(67108864), // BLTZ
266 UINT64_C(67108864), // BLTZ64
267 UINT64_C(68157440), // BLTZAL
268 UINT64_C(469762048), // BLTZALC
269 UINT64_C(3758096384), // BLTZALC_MMR6
270 UINT64_C(68288512), // BLTZALL
271 UINT64_C(1109393408), // BLTZALS_MM
272 UINT64_C(1075838976), // BLTZAL_MM
273 UINT64_C(1543503872), // BLTZC
274 UINT64_C(1543503872), // BLTZC64
275 UINT64_C(3556769792), // BLTZC_MMR6
276 UINT64_C(67239936), // BLTZL
277 UINT64_C(1073741824), // BLTZ_MM
278 UINT64_C(2013265921), // BMNZI_B
279 UINT64_C(2021654558), // BMNZ_V
280 UINT64_C(2030043137), // BMZI_B
281 UINT64_C(2023751710), // BMZ_V
282 UINT64_C(335544320), // BNE
283 UINT64_C(335544320), // BNE64
284 UINT64_C(1610612736), // BNEC
285 UINT64_C(1610612736), // BNEC64
286 UINT64_C(2080374784), // BNEC_MMR6
287 UINT64_C(2062549001), // BNEGI_B
288 UINT64_C(2055208969), // BNEGI_D
289 UINT64_C(2061500425), // BNEGI_H
290 UINT64_C(2059403273), // BNEGI_W
291 UINT64_C(2055208973), // BNEG_B
292 UINT64_C(2061500429), // BNEG_D
293 UINT64_C(2057306125), // BNEG_H
294 UINT64_C(2059403277), // BNEG_W
295 UINT64_C(1409286144), // BNEL
296 UINT64_C(44032), // BNEZ16_MM
297 UINT64_C(1610612736), // BNEZALC
298 UINT64_C(2080374784), // BNEZALC_MMR6
299 UINT64_C(4160749568), // BNEZC
300 UINT64_C(44032), // BNEZC16_MMR6
301 UINT64_C(4160749568), // BNEZC64
302 UINT64_C(1084227584), // BNEZC_MM
303 UINT64_C(2684354560), // BNEZC_MMR6
304 UINT64_C(3019898880), // BNE_MM
305 UINT64_C(1610612736), // BNVC
306 UINT64_C(2080374784), // BNVC_MMR6
307 UINT64_C(1199570944), // BNZ_B
308 UINT64_C(1205862400), // BNZ_D
309 UINT64_C(1201668096), // BNZ_H
310 UINT64_C(1172307968), // BNZ_V
311 UINT64_C(1203765248), // BNZ_W
312 UINT64_C(536870912), // BOVC
313 UINT64_C(1946157056), // BOVC_MMR6
314 UINT64_C(68943872), // BPOSGE32
315 UINT64_C(1126170624), // BPOSGE32C_MMR3
316 UINT64_C(1130364928), // BPOSGE32_MM
317 UINT64_C(13), // BREAK
318 UINT64_C(18048), // BREAK16_MM
319 UINT64_C(17435), // BREAK16_MMR6
320 UINT64_C(7), // BREAK_MM
321 UINT64_C(7), // BREAK_MMR6
322 UINT64_C(2046820353), // BSELI_B
323 UINT64_C(2025848862), // BSEL_V
324 UINT64_C(2054160393), // BSETI_B
325 UINT64_C(2046820361), // BSETI_D
326 UINT64_C(2053111817), // BSETI_H
327 UINT64_C(2051014665), // BSETI_W
328 UINT64_C(2046820365), // BSET_B
329 UINT64_C(2053111821), // BSET_D
330 UINT64_C(2048917517), // BSET_H
331 UINT64_C(2051014669), // BSET_W
332 UINT64_C(1191182336), // BZ_B
333 UINT64_C(1197473792), // BZ_D
334 UINT64_C(1193279488), // BZ_H
335 UINT64_C(1163919360), // BZ_V
336 UINT64_C(1195376640), // BZ_W
337 UINT64_C(8192), // BeqzRxImm16
338 UINT64_C(4026540032), // BeqzRxImmX16
339 UINT64_C(4096), // Bimm16
340 UINT64_C(4026535936), // BimmX16
341 UINT64_C(10240), // BnezRxImm16
342 UINT64_C(4026542080), // BnezRxImmX16
343 UINT64_C(59397), // Break16
344 UINT64_C(24576), // Bteqz16
345 UINT64_C(4026544128), // BteqzX16
346 UINT64_C(24832), // Btnez16
347 UINT64_C(4026544384), // BtnezX16
348 UINT64_C(3154116608), // CACHE
349 UINT64_C(2080374811), // CACHEE
350 UINT64_C(1610655232), // CACHEE_MM
351 UINT64_C(536895488), // CACHE_MM
352 UINT64_C(536895488), // CACHE_MMR6
353 UINT64_C(2080374821), // CACHE_R6
354 UINT64_C(1176502282), // CEIL_L_D64
355 UINT64_C(1409307451), // CEIL_L_D_MMR6
356 UINT64_C(1174405130), // CEIL_L_S
357 UINT64_C(1409291067), // CEIL_L_S_MMR6
358 UINT64_C(1176502286), // CEIL_W_D32
359 UINT64_C(1176502286), // CEIL_W_D64
360 UINT64_C(1409309499), // CEIL_W_D_MMR6
361 UINT64_C(1409309499), // CEIL_W_MM
362 UINT64_C(1174405134), // CEIL_W_S
363 UINT64_C(1409293115), // CEIL_W_S_MM
364 UINT64_C(1409293115), // CEIL_W_S_MMR6
365 UINT64_C(2013265927), // CEQI_B
366 UINT64_C(2019557383), // CEQI_D
367 UINT64_C(2015363079), // CEQI_H
368 UINT64_C(2017460231), // CEQI_W
369 UINT64_C(2013265935), // CEQ_B
370 UINT64_C(2019557391), // CEQ_D
371 UINT64_C(2015363087), // CEQ_H
372 UINT64_C(2017460239), // CEQ_W
373 UINT64_C(1145044992), // CFC1
374 UINT64_C(1409290299), // CFC1_MM
375 UINT64_C(52540), // CFC2_MM
376 UINT64_C(2021523481), // CFCMSA
377 UINT64_C(1879048242), // CINS
378 UINT64_C(1879048243), // CINS32
379 UINT64_C(1879048242), // CINS64_32
380 UINT64_C(1879048242), // CINS_i32
381 UINT64_C(1176502299), // CLASS_D
382 UINT64_C(1409286752), // CLASS_D_MMR6
383 UINT64_C(1174405147), // CLASS_S
384 UINT64_C(1409286240), // CLASS_S_MMR6
385 UINT64_C(2046820359), // CLEI_S_B
386 UINT64_C(2053111815), // CLEI_S_D
387 UINT64_C(2048917511), // CLEI_S_H
388 UINT64_C(2051014663), // CLEI_S_W
389 UINT64_C(2055208967), // CLEI_U_B
390 UINT64_C(2061500423), // CLEI_U_D
391 UINT64_C(2057306119), // CLEI_U_H
392 UINT64_C(2059403271), // CLEI_U_W
393 UINT64_C(2046820367), // CLE_S_B
394 UINT64_C(2053111823), // CLE_S_D
395 UINT64_C(2048917519), // CLE_S_H
396 UINT64_C(2051014671), // CLE_S_W
397 UINT64_C(2055208975), // CLE_U_B
398 UINT64_C(2061500431), // CLE_U_D
399 UINT64_C(2057306127), // CLE_U_H
400 UINT64_C(2059403279), // CLE_U_W
401 UINT64_C(1879048225), // CLO
402 UINT64_C(19260), // CLO_MM
403 UINT64_C(19260), // CLO_MMR6
404 UINT64_C(81), // CLO_R6
405 UINT64_C(2030043143), // CLTI_S_B
406 UINT64_C(2036334599), // CLTI_S_D
407 UINT64_C(2032140295), // CLTI_S_H
408 UINT64_C(2034237447), // CLTI_S_W
409 UINT64_C(2038431751), // CLTI_U_B
410 UINT64_C(2044723207), // CLTI_U_D
411 UINT64_C(2040528903), // CLTI_U_H
412 UINT64_C(2042626055), // CLTI_U_W
413 UINT64_C(2030043151), // CLT_S_B
414 UINT64_C(2036334607), // CLT_S_D
415 UINT64_C(2032140303), // CLT_S_H
416 UINT64_C(2034237455), // CLT_S_W
417 UINT64_C(2038431759), // CLT_U_B
418 UINT64_C(2044723215), // CLT_U_D
419 UINT64_C(2040528911), // CLT_U_H
420 UINT64_C(2042626063), // CLT_U_W
421 UINT64_C(1879048224), // CLZ
422 UINT64_C(23356), // CLZ_MM
423 UINT64_C(80), // CLZ_MMR6
424 UINT64_C(80), // CLZ_R6
425 UINT64_C(2080376337), // CMPGDU_EQ_QB
426 UINT64_C(389), // CMPGDU_EQ_QB_MMR2
427 UINT64_C(2080376465), // CMPGDU_LE_QB
428 UINT64_C(517), // CMPGDU_LE_QB_MMR2
429 UINT64_C(2080376401), // CMPGDU_LT_QB
430 UINT64_C(453), // CMPGDU_LT_QB_MMR2
431 UINT64_C(2080375057), // CMPGU_EQ_QB
432 UINT64_C(1476395205), // CMPGU_EQ_QB_MM
433 UINT64_C(2080375185), // CMPGU_LE_QB
434 UINT64_C(1476395333), // CMPGU_LE_QB_MM
435 UINT64_C(2080375121), // CMPGU_LT_QB
436 UINT64_C(1476395269), // CMPGU_LT_QB_MM
437 UINT64_C(2080374801), // CMPU_EQ_QB
438 UINT64_C(581), // CMPU_EQ_QB_MM
439 UINT64_C(2080374929), // CMPU_LE_QB
440 UINT64_C(709), // CMPU_LE_QB_MM
441 UINT64_C(2080374865), // CMPU_LT_QB
442 UINT64_C(645), // CMPU_LT_QB_MM
443 UINT64_C(1409286165), // CMP_AF_D_MMR6
444 UINT64_C(1409286149), // CMP_AF_S_MMR6
445 UINT64_C(1184890882), // CMP_EQ_D
446 UINT64_C(1409286293), // CMP_EQ_D_MMR6
447 UINT64_C(2080375313), // CMP_EQ_PH
448 UINT64_C(5), // CMP_EQ_PH_MM
449 UINT64_C(1182793730), // CMP_EQ_S
450 UINT64_C(1409286277), // CMP_EQ_S_MMR6
451 UINT64_C(1184890880), // CMP_F_D
452 UINT64_C(1182793728), // CMP_F_S
453 UINT64_C(1184890886), // CMP_LE_D
454 UINT64_C(1409286549), // CMP_LE_D_MMR6
455 UINT64_C(2080375441), // CMP_LE_PH
456 UINT64_C(133), // CMP_LE_PH_MM
457 UINT64_C(1182793734), // CMP_LE_S
458 UINT64_C(1409286533), // CMP_LE_S_MMR6
459 UINT64_C(1184890884), // CMP_LT_D
460 UINT64_C(1409286421), // CMP_LT_D_MMR6
461 UINT64_C(2080375377), // CMP_LT_PH
462 UINT64_C(69), // CMP_LT_PH_MM
463 UINT64_C(1182793732), // CMP_LT_S
464 UINT64_C(1409286405), // CMP_LT_S_MMR6
465 UINT64_C(1184890888), // CMP_SAF_D
466 UINT64_C(1409286677), // CMP_SAF_D_MMR6
467 UINT64_C(1182793736), // CMP_SAF_S
468 UINT64_C(1409286661), // CMP_SAF_S_MMR6
469 UINT64_C(1184890890), // CMP_SEQ_D
470 UINT64_C(1409286805), // CMP_SEQ_D_MMR6
471 UINT64_C(1182793738), // CMP_SEQ_S
472 UINT64_C(1409286789), // CMP_SEQ_S_MMR6
473 UINT64_C(1184890894), // CMP_SLE_D
474 UINT64_C(1409287061), // CMP_SLE_D_MMR6
475 UINT64_C(1182793742), // CMP_SLE_S
476 UINT64_C(1409287045), // CMP_SLE_S_MMR6
477 UINT64_C(1184890892), // CMP_SLT_D
478 UINT64_C(1409286933), // CMP_SLT_D_MMR6
479 UINT64_C(1182793740), // CMP_SLT_S
480 UINT64_C(1409286917), // CMP_SLT_S_MMR6
481 UINT64_C(1184890891), // CMP_SUEQ_D
482 UINT64_C(1409286869), // CMP_SUEQ_D_MMR6
483 UINT64_C(1182793739), // CMP_SUEQ_S
484 UINT64_C(1409286853), // CMP_SUEQ_S_MMR6
485 UINT64_C(1184890895), // CMP_SULE_D
486 UINT64_C(1409287125), // CMP_SULE_D_MMR6
487 UINT64_C(1182793743), // CMP_SULE_S
488 UINT64_C(1409287109), // CMP_SULE_S_MMR6
489 UINT64_C(1184890893), // CMP_SULT_D
490 UINT64_C(1409286997), // CMP_SULT_D_MMR6
491 UINT64_C(1182793741), // CMP_SULT_S
492 UINT64_C(1409286981), // CMP_SULT_S_MMR6
493 UINT64_C(1184890889), // CMP_SUN_D
494 UINT64_C(1409286741), // CMP_SUN_D_MMR6
495 UINT64_C(1182793737), // CMP_SUN_S
496 UINT64_C(1409286725), // CMP_SUN_S_MMR6
497 UINT64_C(1184890883), // CMP_UEQ_D
498 UINT64_C(1409286357), // CMP_UEQ_D_MMR6
499 UINT64_C(1182793731), // CMP_UEQ_S
500 UINT64_C(1409286341), // CMP_UEQ_S_MMR6
501 UINT64_C(1184890887), // CMP_ULE_D
502 UINT64_C(1409286613), // CMP_ULE_D_MMR6
503 UINT64_C(1182793735), // CMP_ULE_S
504 UINT64_C(1409286597), // CMP_ULE_S_MMR6
505 UINT64_C(1184890885), // CMP_ULT_D
506 UINT64_C(1409286485), // CMP_ULT_D_MMR6
507 UINT64_C(1182793733), // CMP_ULT_S
508 UINT64_C(1409286469), // CMP_ULT_S_MMR6
509 UINT64_C(1184890881), // CMP_UN_D
510 UINT64_C(1409286229), // CMP_UN_D_MMR6
511 UINT64_C(1182793729), // CMP_UN_S
512 UINT64_C(1409286213), // CMP_UN_S_MMR6
513 UINT64_C(2021654553), // COPY_S_B
514 UINT64_C(2025324569), // COPY_S_D
515 UINT64_C(2023751705), // COPY_S_H
516 UINT64_C(2024800281), // COPY_S_W
517 UINT64_C(2025848857), // COPY_U_B
518 UINT64_C(2027946009), // COPY_U_H
519 UINT64_C(2028994585), // COPY_U_W
520 UINT64_C(2080374799), // CRC32B
521 UINT64_C(2080375055), // CRC32CB
522 UINT64_C(2080375247), // CRC32CD
523 UINT64_C(2080375119), // CRC32CH
524 UINT64_C(2080375183), // CRC32CW
525 UINT64_C(2080374991), // CRC32D
526 UINT64_C(2080374863), // CRC32H
527 UINT64_C(2080374927), // CRC32W
528 UINT64_C(1153433600), // CTC1
529 UINT64_C(1409292347), // CTC1_MM
530 UINT64_C(56636), // CTC2_MM
531 UINT64_C(2017329177), // CTCMSA
532 UINT64_C(1174405153), // CVT_D32_S
533 UINT64_C(1409291131), // CVT_D32_S_MM
534 UINT64_C(1182793761), // CVT_D32_W
535 UINT64_C(1409299323), // CVT_D32_W_MM
536 UINT64_C(1184890913), // CVT_D64_L
537 UINT64_C(1174405153), // CVT_D64_S
538 UINT64_C(1409291131), // CVT_D64_S_MM
539 UINT64_C(1182793761), // CVT_D64_W
540 UINT64_C(1409299323), // CVT_D64_W_MM
541 UINT64_C(1409307515), // CVT_D_L_MMR6
542 UINT64_C(1176502309), // CVT_L_D64
543 UINT64_C(1409302843), // CVT_L_D64_MM
544 UINT64_C(1409302843), // CVT_L_D_MMR6
545 UINT64_C(1174405157), // CVT_L_S
546 UINT64_C(1409286459), // CVT_L_S_MM
547 UINT64_C(1409286459), // CVT_L_S_MMR6
548 UINT64_C(1182793766), // CVT_PS_PW64
549 UINT64_C(1174405158), // CVT_PS_S64
550 UINT64_C(1186988068), // CVT_PW_PS64
551 UINT64_C(1176502304), // CVT_S_D32
552 UINT64_C(1409293179), // CVT_S_D32_MM
553 UINT64_C(1176502304), // CVT_S_D64
554 UINT64_C(1409293179), // CVT_S_D64_MM
555 UINT64_C(1184890912), // CVT_S_L
556 UINT64_C(1409309563), // CVT_S_L_MMR6
557 UINT64_C(1186988072), // CVT_S_PL64
558 UINT64_C(1186988064), // CVT_S_PU64
559 UINT64_C(1182793760), // CVT_S_W
560 UINT64_C(1409301371), // CVT_S_W_MM
561 UINT64_C(1409301371), // CVT_S_W_MMR6
562 UINT64_C(1176502308), // CVT_W_D32
563 UINT64_C(1409304891), // CVT_W_D32_MM
564 UINT64_C(1176502308), // CVT_W_D64
565 UINT64_C(1409304891), // CVT_W_D64_MM
566 UINT64_C(1174405156), // CVT_W_S
567 UINT64_C(1409288507), // CVT_W_S_MM
568 UINT64_C(1409288507), // CVT_W_S_MMR6
569 UINT64_C(1176502322), // C_EQ_D32
570 UINT64_C(1409287356), // C_EQ_D32_MM
571 UINT64_C(1176502322), // C_EQ_D64
572 UINT64_C(1409287356), // C_EQ_D64_MM
573 UINT64_C(1174405170), // C_EQ_S
574 UINT64_C(1409286332), // C_EQ_S_MM
575 UINT64_C(1176502320), // C_F_D32
576 UINT64_C(1409287228), // C_F_D32_MM
577 UINT64_C(1176502320), // C_F_D64
578 UINT64_C(1409287228), // C_F_D64_MM
579 UINT64_C(1174405168), // C_F_S
580 UINT64_C(1409286204), // C_F_S_MM
581 UINT64_C(1176502334), // C_LE_D32
582 UINT64_C(1409288124), // C_LE_D32_MM
583 UINT64_C(1176502334), // C_LE_D64
584 UINT64_C(1409288124), // C_LE_D64_MM
585 UINT64_C(1174405182), // C_LE_S
586 UINT64_C(1409287100), // C_LE_S_MM
587 UINT64_C(1176502332), // C_LT_D32
588 UINT64_C(1409287996), // C_LT_D32_MM
589 UINT64_C(1176502332), // C_LT_D64
590 UINT64_C(1409287996), // C_LT_D64_MM
591 UINT64_C(1174405180), // C_LT_S
592 UINT64_C(1409286972), // C_LT_S_MM
593 UINT64_C(1176502333), // C_NGE_D32
594 UINT64_C(1409288060), // C_NGE_D32_MM
595 UINT64_C(1176502333), // C_NGE_D64
596 UINT64_C(1409288060), // C_NGE_D64_MM
597 UINT64_C(1174405181), // C_NGE_S
598 UINT64_C(1409287036), // C_NGE_S_MM
599 UINT64_C(1176502329), // C_NGLE_D32
600 UINT64_C(1409287804), // C_NGLE_D32_MM
601 UINT64_C(1176502329), // C_NGLE_D64
602 UINT64_C(1409287804), // C_NGLE_D64_MM
603 UINT64_C(1174405177), // C_NGLE_S
604 UINT64_C(1409286780), // C_NGLE_S_MM
605 UINT64_C(1176502331), // C_NGL_D32
606 UINT64_C(1409287932), // C_NGL_D32_MM
607 UINT64_C(1176502331), // C_NGL_D64
608 UINT64_C(1409287932), // C_NGL_D64_MM
609 UINT64_C(1174405179), // C_NGL_S
610 UINT64_C(1409286908), // C_NGL_S_MM
611 UINT64_C(1176502335), // C_NGT_D32
612 UINT64_C(1409288188), // C_NGT_D32_MM
613 UINT64_C(1176502335), // C_NGT_D64
614 UINT64_C(1409288188), // C_NGT_D64_MM
615 UINT64_C(1174405183), // C_NGT_S
616 UINT64_C(1409287164), // C_NGT_S_MM
617 UINT64_C(1176502326), // C_OLE_D32
618 UINT64_C(1409287612), // C_OLE_D32_MM
619 UINT64_C(1176502326), // C_OLE_D64
620 UINT64_C(1409287612), // C_OLE_D64_MM
621 UINT64_C(1174405174), // C_OLE_S
622 UINT64_C(1409286588), // C_OLE_S_MM
623 UINT64_C(1176502324), // C_OLT_D32
624 UINT64_C(1409287484), // C_OLT_D32_MM
625 UINT64_C(1176502324), // C_OLT_D64
626 UINT64_C(1409287484), // C_OLT_D64_MM
627 UINT64_C(1174405172), // C_OLT_S
628 UINT64_C(1409286460), // C_OLT_S_MM
629 UINT64_C(1176502330), // C_SEQ_D32
630 UINT64_C(1409287868), // C_SEQ_D32_MM
631 UINT64_C(1176502330), // C_SEQ_D64
632 UINT64_C(1409287868), // C_SEQ_D64_MM
633 UINT64_C(1174405178), // C_SEQ_S
634 UINT64_C(1409286844), // C_SEQ_S_MM
635 UINT64_C(1176502328), // C_SF_D32
636 UINT64_C(1409287740), // C_SF_D32_MM
637 UINT64_C(1176502328), // C_SF_D64
638 UINT64_C(1409287740), // C_SF_D64_MM
639 UINT64_C(1174405176), // C_SF_S
640 UINT64_C(1409286716), // C_SF_S_MM
641 UINT64_C(1176502323), // C_UEQ_D32
642 UINT64_C(1409287420), // C_UEQ_D32_MM
643 UINT64_C(1176502323), // C_UEQ_D64
644 UINT64_C(1409287420), // C_UEQ_D64_MM
645 UINT64_C(1174405171), // C_UEQ_S
646 UINT64_C(1409286396), // C_UEQ_S_MM
647 UINT64_C(1176502327), // C_ULE_D32
648 UINT64_C(1409287676), // C_ULE_D32_MM
649 UINT64_C(1176502327), // C_ULE_D64
650 UINT64_C(1409287676), // C_ULE_D64_MM
651 UINT64_C(1174405175), // C_ULE_S
652 UINT64_C(1409286652), // C_ULE_S_MM
653 UINT64_C(1176502325), // C_ULT_D32
654 UINT64_C(1409287548), // C_ULT_D32_MM
655 UINT64_C(1176502325), // C_ULT_D64
656 UINT64_C(1409287548), // C_ULT_D64_MM
657 UINT64_C(1174405173), // C_ULT_S
658 UINT64_C(1409286524), // C_ULT_S_MM
659 UINT64_C(1176502321), // C_UN_D32
660 UINT64_C(1409287292), // C_UN_D32_MM
661 UINT64_C(1176502321), // C_UN_D64
662 UINT64_C(1409287292), // C_UN_D64_MM
663 UINT64_C(1174405169), // C_UN_S
664 UINT64_C(1409286268), // C_UN_S_MM
665 UINT64_C(59402), // CmpRxRy16
666 UINT64_C(28672), // CmpiRxImm16
667 UINT64_C(4026560512), // CmpiRxImmX16
668 UINT64_C(44), // DADD
669 UINT64_C(1610612736), // DADDi
670 UINT64_C(1677721600), // DADDiu
671 UINT64_C(45), // DADDu
672 UINT64_C(67502080), // DAHI
673 UINT64_C(2080375332), // DALIGN
674 UINT64_C(69074944), // DATI
675 UINT64_C(1946157056), // DAUI
676 UINT64_C(2080374820), // DBITSWAP
677 UINT64_C(1879048229), // DCLO
678 UINT64_C(83), // DCLO_R6
679 UINT64_C(1879048228), // DCLZ
680 UINT64_C(82), // DCLZ_R6
681 UINT64_C(158), // DDIV
682 UINT64_C(159), // DDIVU
683 UINT64_C(1107296287), // DERET
684 UINT64_C(58236), // DERET_MM
685 UINT64_C(58236), // DERET_MMR6
686 UINT64_C(2080374787), // DEXT
687 UINT64_C(2080374787), // DEXT64_32
688 UINT64_C(2080374785), // DEXTM
689 UINT64_C(2080374786), // DEXTU
690 UINT64_C(1096835072), // DI
691 UINT64_C(2080374791), // DINS
692 UINT64_C(2080374789), // DINSM
693 UINT64_C(2080374790), // DINSU
694 UINT64_C(154), // DIV
695 UINT64_C(155), // DIVU
696 UINT64_C(408), // DIVU_MMR6
697 UINT64_C(280), // DIV_MMR6
698 UINT64_C(2046820370), // DIV_S_B
699 UINT64_C(2053111826), // DIV_S_D
700 UINT64_C(2048917522), // DIV_S_H
701 UINT64_C(2051014674), // DIV_S_W
702 UINT64_C(2055208978), // DIV_U_B
703 UINT64_C(2061500434), // DIV_U_D
704 UINT64_C(2057306130), // DIV_U_H
705 UINT64_C(2059403282), // DIV_U_W
706 UINT64_C(18300), // DI_MM
707 UINT64_C(18300), // DI_MMR6
708 UINT64_C(21), // DLSA
709 UINT64_C(21), // DLSA_R6
710 UINT64_C(1075838976), // DMFC0
711 UINT64_C(1142947840), // DMFC1
712 UINT64_C(1210056704), // DMFC2
713 UINT64_C(1210056704), // DMFC2_OCTEON
714 UINT64_C(1080033536), // DMFGC0
715 UINT64_C(222), // DMOD
716 UINT64_C(223), // DMODU
717 UINT64_C(1096813505), // DMT
718 UINT64_C(1084227584), // DMTC0
719 UINT64_C(1151336448), // DMTC1
720 UINT64_C(1218445312), // DMTC2
721 UINT64_C(1218445312), // DMTC2_OCTEON
722 UINT64_C(1080034048), // DMTGC0
723 UINT64_C(220), // DMUH
724 UINT64_C(221), // DMUHU
725 UINT64_C(1879048195), // DMUL
726 UINT64_C(28), // DMULT
727 UINT64_C(29), // DMULTu
728 UINT64_C(157), // DMULU
729 UINT64_C(156), // DMUL_R6
730 UINT64_C(2019557395), // DOTP_S_D
731 UINT64_C(2015363091), // DOTP_S_H
732 UINT64_C(2017460243), // DOTP_S_W
733 UINT64_C(2027946003), // DOTP_U_D
734 UINT64_C(2023751699), // DOTP_U_H
735 UINT64_C(2025848851), // DOTP_U_W
736 UINT64_C(2036334611), // DPADD_S_D
737 UINT64_C(2032140307), // DPADD_S_H
738 UINT64_C(2034237459), // DPADD_S_W
739 UINT64_C(2044723219), // DPADD_U_D
740 UINT64_C(2040528915), // DPADD_U_H
741 UINT64_C(2042626067), // DPADD_U_W
742 UINT64_C(2080376496), // DPAQX_SA_W_PH
743 UINT64_C(12988), // DPAQX_SA_W_PH_MMR2
744 UINT64_C(2080376368), // DPAQX_S_W_PH
745 UINT64_C(8892), // DPAQX_S_W_PH_MMR2
746 UINT64_C(2080375600), // DPAQ_SA_L_W
747 UINT64_C(4796), // DPAQ_SA_L_W_MM
748 UINT64_C(2080375088), // DPAQ_S_W_PH
749 UINT64_C(700), // DPAQ_S_W_PH_MM
750 UINT64_C(2080375024), // DPAU_H_QBL
751 UINT64_C(8380), // DPAU_H_QBL_MM
752 UINT64_C(2080375280), // DPAU_H_QBR
753 UINT64_C(12476), // DPAU_H_QBR_MM
754 UINT64_C(2080375344), // DPAX_W_PH
755 UINT64_C(4284), // DPAX_W_PH_MMR2
756 UINT64_C(2080374832), // DPA_W_PH
757 UINT64_C(188), // DPA_W_PH_MMR2
758 UINT64_C(1879048237), // DPOP
759 UINT64_C(2080376560), // DPSQX_SA_W_PH
760 UINT64_C(14012), // DPSQX_SA_W_PH_MMR2
761 UINT64_C(2080376432), // DPSQX_S_W_PH
762 UINT64_C(9916), // DPSQX_S_W_PH_MMR2
763 UINT64_C(2080375664), // DPSQ_SA_L_W
764 UINT64_C(5820), // DPSQ_SA_L_W_MM
765 UINT64_C(2080375152), // DPSQ_S_W_PH
766 UINT64_C(1724), // DPSQ_S_W_PH_MM
767 UINT64_C(2053111827), // DPSUB_S_D
768 UINT64_C(2048917523), // DPSUB_S_H
769 UINT64_C(2051014675), // DPSUB_S_W
770 UINT64_C(2061500435), // DPSUB_U_D
771 UINT64_C(2057306131), // DPSUB_U_H
772 UINT64_C(2059403283), // DPSUB_U_W
773 UINT64_C(2080375536), // DPSU_H_QBL
774 UINT64_C(9404), // DPSU_H_QBL_MM
775 UINT64_C(2080375792), // DPSU_H_QBR
776 UINT64_C(13500), // DPSU_H_QBR_MM
777 UINT64_C(2080375408), // DPSX_W_PH
778 UINT64_C(5308), // DPSX_W_PH_MMR2
779 UINT64_C(2080374896), // DPS_W_PH
780 UINT64_C(1212), // DPS_W_PH_MMR2
781 UINT64_C(2097210), // DROTR
782 UINT64_C(2097214), // DROTR32
783 UINT64_C(86), // DROTRV
784 UINT64_C(2080374948), // DSBH
785 UINT64_C(30), // DSDIV
786 UINT64_C(2080375140), // DSHD
787 UINT64_C(56), // DSLL
788 UINT64_C(60), // DSLL32
789 UINT64_C(60), // DSLL64_32
790 UINT64_C(20), // DSLLV
791 UINT64_C(59), // DSRA
792 UINT64_C(63), // DSRA32
793 UINT64_C(23), // DSRAV
794 UINT64_C(58), // DSRL
795 UINT64_C(62), // DSRL32
796 UINT64_C(22), // DSRLV
797 UINT64_C(46), // DSUB
798 UINT64_C(47), // DSUBu
799 UINT64_C(31), // DUDIV
800 UINT64_C(1096810532), // DVP
801 UINT64_C(1096810497), // DVPE
802 UINT64_C(6524), // DVP_MMR6
803 UINT64_C(59418), // DivRxRy16
804 UINT64_C(59419), // DivuRxRy16
805 UINT64_C(192), // EHB
806 UINT64_C(6144), // EHB_MM
807 UINT64_C(6144), // EHB_MMR6
808 UINT64_C(1096835104), // EI
809 UINT64_C(22396), // EI_MM
810 UINT64_C(22396), // EI_MMR6
811 UINT64_C(1096813537), // EMT
812 UINT64_C(1107296280), // ERET
813 UINT64_C(1107296344), // ERETNC
814 UINT64_C(127868), // ERETNC_MMR6
815 UINT64_C(62332), // ERET_MM
816 UINT64_C(62332), // ERET_MMR6
817 UINT64_C(1096810500), // EVP
818 UINT64_C(1096810529), // EVPE
819 UINT64_C(14716), // EVP_MMR6
820 UINT64_C(2080374784), // EXT
821 UINT64_C(2080374968), // EXTP
822 UINT64_C(2080375480), // EXTPDP
823 UINT64_C(2080375544), // EXTPDPV
824 UINT64_C(14524), // EXTPDPV_MM
825 UINT64_C(13948), // EXTPDP_MM
826 UINT64_C(2080375032), // EXTPV
827 UINT64_C(10428), // EXTPV_MM
828 UINT64_C(9852), // EXTP_MM
829 UINT64_C(2080375288), // EXTRV_RS_W
830 UINT64_C(11964), // EXTRV_RS_W_MM
831 UINT64_C(2080375160), // EXTRV_R_W
832 UINT64_C(7868), // EXTRV_R_W_MM
833 UINT64_C(2080375800), // EXTRV_S_H
834 UINT64_C(16060), // EXTRV_S_H_MM
835 UINT64_C(2080374904), // EXTRV_W
836 UINT64_C(3772), // EXTRV_W_MM
837 UINT64_C(2080375224), // EXTR_RS_W
838 UINT64_C(11900), // EXTR_RS_W_MM
839 UINT64_C(2080375096), // EXTR_R_W
840 UINT64_C(7804), // EXTR_R_W_MM
841 UINT64_C(2080375736), // EXTR_S_H
842 UINT64_C(15996), // EXTR_S_H_MM
843 UINT64_C(2080374840), // EXTR_W
844 UINT64_C(3708), // EXTR_W_MM
845 UINT64_C(1879048250), // EXTS
846 UINT64_C(1879048251), // EXTS32
847 UINT64_C(44), // EXT_MM
848 UINT64_C(44), // EXT_MMR6
849 UINT64_C(1176502277), // FABS_D32
850 UINT64_C(1409295227), // FABS_D32_MM
851 UINT64_C(1176502277), // FABS_D64
852 UINT64_C(1409295227), // FABS_D64_MM
853 UINT64_C(1174405125), // FABS_S
854 UINT64_C(1409287035), // FABS_S_MM
855 UINT64_C(2015363099), // FADD_D
856 UINT64_C(1176502272), // FADD_D32
857 UINT64_C(1409286448), // FADD_D32_MM
858 UINT64_C(1176502272), // FADD_D64
859 UINT64_C(1409286448), // FADD_D64_MM
860 UINT64_C(1186988032), // FADD_PS64
861 UINT64_C(1174405120), // FADD_S
862 UINT64_C(1409286192), // FADD_S_MM
863 UINT64_C(1409286192), // FADD_S_MMR6
864 UINT64_C(2013265947), // FADD_W
865 UINT64_C(2015363098), // FCAF_D
866 UINT64_C(2013265946), // FCAF_W
867 UINT64_C(2023751706), // FCEQ_D
868 UINT64_C(2021654554), // FCEQ_W
869 UINT64_C(2065760286), // FCLASS_D
870 UINT64_C(2065694750), // FCLASS_W
871 UINT64_C(2040528922), // FCLE_D
872 UINT64_C(2038431770), // FCLE_W
873 UINT64_C(2032140314), // FCLT_D
874 UINT64_C(2030043162), // FCLT_W
875 UINT64_C(1176502320), // FCMP_D32
876 UINT64_C(1409287228), // FCMP_D32_MM
877 UINT64_C(1176502320), // FCMP_D64
878 UINT64_C(1174405168), // FCMP_S32
879 UINT64_C(1409286204), // FCMP_S32_MM
880 UINT64_C(2027946012), // FCNE_D
881 UINT64_C(2025848860), // FCNE_W
882 UINT64_C(2019557404), // FCOR_D
883 UINT64_C(2017460252), // FCOR_W
884 UINT64_C(2027946010), // FCUEQ_D
885 UINT64_C(2025848858), // FCUEQ_W
886 UINT64_C(2044723226), // FCULE_D
887 UINT64_C(2042626074), // FCULE_W
888 UINT64_C(2036334618), // FCULT_D
889 UINT64_C(2034237466), // FCULT_W
890 UINT64_C(2023751708), // FCUNE_D
891 UINT64_C(2021654556), // FCUNE_W
892 UINT64_C(2019557402), // FCUN_D
893 UINT64_C(2017460250), // FCUN_W
894 UINT64_C(2027946011), // FDIV_D
895 UINT64_C(1176502275), // FDIV_D32
896 UINT64_C(1409286640), // FDIV_D32_MM
897 UINT64_C(1176502275), // FDIV_D64
898 UINT64_C(1409286640), // FDIV_D64_MM
899 UINT64_C(1174405123), // FDIV_S
900 UINT64_C(1409286384), // FDIV_S_MM
901 UINT64_C(1409286384), // FDIV_S_MMR6
902 UINT64_C(2025848859), // FDIV_W
903 UINT64_C(2046820379), // FEXDO_H
904 UINT64_C(2048917531), // FEXDO_W
905 UINT64_C(2044723227), // FEXP2_D
906 UINT64_C(2042626075), // FEXP2_W
907 UINT64_C(2066808862), // FEXUPL_D
908 UINT64_C(2066743326), // FEXUPL_W
909 UINT64_C(2066939934), // FEXUPR_D
910 UINT64_C(2066874398), // FEXUPR_W
911 UINT64_C(2067595294), // FFINT_S_D
912 UINT64_C(2067529758), // FFINT_S_W
913 UINT64_C(2067726366), // FFINT_U_D
914 UINT64_C(2067660830), // FFINT_U_W
915 UINT64_C(2067071006), // FFQL_D
916 UINT64_C(2067005470), // FFQL_W
917 UINT64_C(2067202078), // FFQR_D
918 UINT64_C(2067136542), // FFQR_W
919 UINT64_C(2063597598), // FILL_B
920 UINT64_C(2063794206), // FILL_D
921 UINT64_C(2063663134), // FILL_H
922 UINT64_C(2063728670), // FILL_W
923 UINT64_C(2066677790), // FLOG2_D
924 UINT64_C(2066612254), // FLOG2_W
925 UINT64_C(1176502283), // FLOOR_L_D64
926 UINT64_C(1409303355), // FLOOR_L_D_MMR6
927 UINT64_C(1174405131), // FLOOR_L_S
928 UINT64_C(1409286971), // FLOOR_L_S_MMR6
929 UINT64_C(1176502287), // FLOOR_W_D32
930 UINT64_C(1176502287), // FLOOR_W_D64
931 UINT64_C(1409305403), // FLOOR_W_D_MMR6
932 UINT64_C(1409305403), // FLOOR_W_MM
933 UINT64_C(1174405135), // FLOOR_W_S
934 UINT64_C(1409289019), // FLOOR_W_S_MM
935 UINT64_C(1409289019), // FLOOR_W_S_MMR6
936 UINT64_C(2032140315), // FMADD_D
937 UINT64_C(2030043163), // FMADD_W
938 UINT64_C(2078277659), // FMAX_A_D
939 UINT64_C(2076180507), // FMAX_A_W
940 UINT64_C(2074083355), // FMAX_D
941 UINT64_C(2071986203), // FMAX_W
942 UINT64_C(2069889051), // FMIN_A_D
943 UINT64_C(2067791899), // FMIN_A_W
944 UINT64_C(2065694747), // FMIN_D
945 UINT64_C(2063597595), // FMIN_W
946 UINT64_C(1176502278), // FMOV_D32
947 UINT64_C(1409294459), // FMOV_D32_MM
948 UINT64_C(1176502278), // FMOV_D64
949 UINT64_C(1409294459), // FMOV_D64_MM
950 UINT64_C(1409294459), // FMOV_D_MMR6
951 UINT64_C(1174405126), // FMOV_S
952 UINT64_C(1409286267), // FMOV_S_MM
953 UINT64_C(1409286267), // FMOV_S_MMR6
954 UINT64_C(2036334619), // FMSUB_D
955 UINT64_C(2034237467), // FMSUB_W
956 UINT64_C(2023751707), // FMUL_D
957 UINT64_C(1176502274), // FMUL_D32
958 UINT64_C(1409286576), // FMUL_D32_MM
959 UINT64_C(1176502274), // FMUL_D64
960 UINT64_C(1409286576), // FMUL_D64_MM
961 UINT64_C(1186988034), // FMUL_PS64
962 UINT64_C(1174405122), // FMUL_S
963 UINT64_C(1409286320), // FMUL_S_MM
964 UINT64_C(1409286320), // FMUL_S_MMR6
965 UINT64_C(2021654555), // FMUL_W
966 UINT64_C(1176502279), // FNEG_D32
967 UINT64_C(1409297275), // FNEG_D32_MM
968 UINT64_C(1176502279), // FNEG_D64
969 UINT64_C(1409297275), // FNEG_D64_MM
970 UINT64_C(1174405127), // FNEG_S
971 UINT64_C(1409289083), // FNEG_S_MM
972 UINT64_C(1409289083), // FNEG_S_MMR6
973 UINT64_C(2080374792), // FORK
974 UINT64_C(2066415646), // FRCP_D
975 UINT64_C(2066350110), // FRCP_W
976 UINT64_C(2066546718), // FRINT_D
977 UINT64_C(2066481182), // FRINT_W
978 UINT64_C(2066284574), // FRSQRT_D
979 UINT64_C(2066219038), // FRSQRT_W
980 UINT64_C(2048917530), // FSAF_D
981 UINT64_C(2046820378), // FSAF_W
982 UINT64_C(2057306138), // FSEQ_D
983 UINT64_C(2055208986), // FSEQ_W
984 UINT64_C(2074083354), // FSLE_D
985 UINT64_C(2071986202), // FSLE_W
986 UINT64_C(2065694746), // FSLT_D
987 UINT64_C(2063597594), // FSLT_W
988 UINT64_C(2061500444), // FSNE_D
989 UINT64_C(2059403292), // FSNE_W
990 UINT64_C(2053111836), // FSOR_D
991 UINT64_C(2051014684), // FSOR_W
992 UINT64_C(2066153502), // FSQRT_D
993 UINT64_C(1176502276), // FSQRT_D32
994 UINT64_C(1409305147), // FSQRT_D32_MM
995 UINT64_C(1176502276), // FSQRT_D64
996 UINT64_C(1409305147), // FSQRT_D64_MM
997 UINT64_C(1174405124), // FSQRT_S
998 UINT64_C(1409288763), // FSQRT_S_MM
999 UINT64_C(2066087966), // FSQRT_W
1000 UINT64_C(2019557403), // FSUB_D
1001 UINT64_C(1176502273), // FSUB_D32
1002 UINT64_C(1409286512), // FSUB_D32_MM
1003 UINT64_C(1176502273), // FSUB_D64
1004 UINT64_C(1409286512), // FSUB_D64_MM
1005 UINT64_C(1186988033), // FSUB_PS64
1006 UINT64_C(1174405121), // FSUB_S
1007 UINT64_C(1409286256), // FSUB_S_MM
1008 UINT64_C(1409286256), // FSUB_S_MMR6
1009 UINT64_C(2017460251), // FSUB_W
1010 UINT64_C(2061500442), // FSUEQ_D
1011 UINT64_C(2059403290), // FSUEQ_W
1012 UINT64_C(2078277658), // FSULE_D
1013 UINT64_C(2076180506), // FSULE_W
1014 UINT64_C(2069889050), // FSULT_D
1015 UINT64_C(2067791898), // FSULT_W
1016 UINT64_C(2057306140), // FSUNE_D
1017 UINT64_C(2055208988), // FSUNE_W
1018 UINT64_C(2053111834), // FSUN_D
1019 UINT64_C(2051014682), // FSUN_W
1020 UINT64_C(2067333150), // FTINT_S_D
1021 UINT64_C(2067267614), // FTINT_S_W
1022 UINT64_C(2067464222), // FTINT_U_D
1023 UINT64_C(2067398686), // FTINT_U_W
1024 UINT64_C(2055208987), // FTQ_H
1025 UINT64_C(2057306139), // FTQ_W
1026 UINT64_C(2065891358), // FTRUNC_S_D
1027 UINT64_C(2065825822), // FTRUNC_S_W
1028 UINT64_C(2066022430), // FTRUNC_U_D
1029 UINT64_C(2065956894), // FTRUNC_U_W
1030 UINT64_C(2080374845), // GINVI
1031 UINT64_C(24956), // GINVI_MMR6
1032 UINT64_C(2080374973), // GINVT
1033 UINT64_C(29052), // GINVT_MMR6
1034 UINT64_C(2053111829), // HADD_S_D
1035 UINT64_C(2048917525), // HADD_S_H
1036 UINT64_C(2051014677), // HADD_S_W
1037 UINT64_C(2061500437), // HADD_U_D
1038 UINT64_C(2057306133), // HADD_U_H
1039 UINT64_C(2059403285), // HADD_U_W
1040 UINT64_C(2069889045), // HSUB_S_D
1041 UINT64_C(2065694741), // HSUB_S_H
1042 UINT64_C(2067791893), // HSUB_S_W
1043 UINT64_C(2078277653), // HSUB_U_D
1044 UINT64_C(2074083349), // HSUB_U_H
1045 UINT64_C(2076180501), // HSUB_U_W
1046 UINT64_C(1107296296), // HYPCALL
1047 UINT64_C(50044), // HYPCALL_MM
1048 UINT64_C(2063597588), // ILVEV_B
1049 UINT64_C(2069889044), // ILVEV_D
1050 UINT64_C(2065694740), // ILVEV_H
1051 UINT64_C(2067791892), // ILVEV_W
1052 UINT64_C(2046820372), // ILVL_B
1053 UINT64_C(2053111828), // ILVL_D
1054 UINT64_C(2048917524), // ILVL_H
1055 UINT64_C(2051014676), // ILVL_W
1056 UINT64_C(2071986196), // ILVOD_B
1057 UINT64_C(2078277652), // ILVOD_D
1058 UINT64_C(2074083348), // ILVOD_H
1059 UINT64_C(2076180500), // ILVOD_W
1060 UINT64_C(2055208980), // ILVR_B
1061 UINT64_C(2061500436), // ILVR_D
1062 UINT64_C(2057306132), // ILVR_H
1063 UINT64_C(2059403284), // ILVR_W
1064 UINT64_C(2080374788), // INS
1065 UINT64_C(2030043161), // INSERT_B
1066 UINT64_C(2033713177), // INSERT_D
1067 UINT64_C(2032140313), // INSERT_H
1068 UINT64_C(2033188889), // INSERT_W
1069 UINT64_C(2080374796), // INSV
1070 UINT64_C(2034237465), // INSVE_B
1071 UINT64_C(2037907481), // INSVE_D
1072 UINT64_C(2036334617), // INSVE_H
1073 UINT64_C(2037383193), // INSVE_W
1074 UINT64_C(16700), // INSV_MM
1075 UINT64_C(12), // INS_MM
1076 UINT64_C(12), // INS_MMR6
1077 UINT64_C(134217728), // J
1078 UINT64_C(201326592), // JAL
1079 UINT64_C(9), // JALR
1080 UINT64_C(17856), // JALR16_MM
1081 UINT64_C(9), // JALR64
1082 UINT64_C(17419), // JALRC16_MMR6
1083 UINT64_C(7996), // JALRC_HB_MMR6
1084 UINT64_C(3900), // JALRC_MMR6
1085 UINT64_C(17888), // JALRS16_MM
1086 UINT64_C(20284), // JALRS_MM
1087 UINT64_C(1033), // JALR_HB
1088 UINT64_C(1033), // JALR_HB64
1089 UINT64_C(3900), // JALR_MM
1090 UINT64_C(1946157056), // JALS_MM
1091 UINT64_C(1946157056), // JALX
1092 UINT64_C(4026531840), // JALX_MM
1093 UINT64_C(4093640704), // JAL_MM
1094 UINT64_C(4160749568), // JIALC
1095 UINT64_C(4160749568), // JIALC64
1096 UINT64_C(2147483648), // JIALC_MMR6
1097 UINT64_C(3623878656), // JIC
1098 UINT64_C(3623878656), // JIC64
1099 UINT64_C(2684354560), // JIC_MMR6
1100 UINT64_C(8), // JR
1101 UINT64_C(17792), // JR16_MM
1102 UINT64_C(8), // JR64
1103 UINT64_C(18176), // JRADDIUSP
1104 UINT64_C(17824), // JRC16_MM
1105 UINT64_C(17411), // JRC16_MMR6
1106 UINT64_C(17427), // JRCADDIUSP_MMR6
1107 UINT64_C(1032), // JR_HB
1108 UINT64_C(1032), // JR_HB64
1109 UINT64_C(1033), // JR_HB64_R6
1110 UINT64_C(1033), // JR_HB_R6
1111 UINT64_C(3900), // JR_MM
1112 UINT64_C(3556769792), // J_MM
1113 UINT64_C(402653184), // Jal16
1114 UINT64_C(402653184), // JalB16
1115 UINT64_C(59424), // JrRa16
1116 UINT64_C(59616), // JrcRa16
1117 UINT64_C(59584), // JrcRx16
1118 UINT64_C(59392), // JumpLinkReg16
1119 UINT64_C(2147483648), // LB
1120 UINT64_C(2147483648), // LB64
1121 UINT64_C(2080374828), // LBE
1122 UINT64_C(1610639360), // LBE_MM
1123 UINT64_C(2048), // LBU16_MM
1124 UINT64_C(2080375178), // LBUX
1125 UINT64_C(549), // LBUX_MM
1126 UINT64_C(335544320), // LBU_MMR6
1127 UINT64_C(469762048), // LB_MM
1128 UINT64_C(469762048), // LB_MMR6
1129 UINT64_C(2415919104), // LBu
1130 UINT64_C(2415919104), // LBu64
1131 UINT64_C(2080374824), // LBuE
1132 UINT64_C(1610637312), // LBuE_MM
1133 UINT64_C(335544320), // LBu_MM
1134 UINT64_C(3690987520), // LD
1135 UINT64_C(3556769792), // LDC1
1136 UINT64_C(3556769792), // LDC164
1137 UINT64_C(3154116608), // LDC1_D64_MMR6
1138 UINT64_C(3154116608), // LDC1_MM_D32
1139 UINT64_C(3154116608), // LDC1_MM_D64
1140 UINT64_C(3623878656), // LDC2
1141 UINT64_C(536879104), // LDC2_MMR6
1142 UINT64_C(1237319680), // LDC2_R6
1143 UINT64_C(3690987520), // LDC3
1144 UINT64_C(2063597575), // LDI_B
1145 UINT64_C(2069889031), // LDI_D
1146 UINT64_C(2065694727), // LDI_H
1147 UINT64_C(2067791879), // LDI_W
1148 UINT64_C(1744830464), // LDL
1149 UINT64_C(3960995840), // LDPC
1150 UINT64_C(1811939328), // LDR
1151 UINT64_C(1275068417), // LDXC1
1152 UINT64_C(1275068417), // LDXC164
1153 UINT64_C(2013265952), // LD_B
1154 UINT64_C(2013265955), // LD_D
1155 UINT64_C(2013265953), // LD_H
1156 UINT64_C(2013265954), // LD_W
1157 UINT64_C(603979776), // LEA_ADDiu
1158 UINT64_C(1677721600), // LEA_ADDiu64
1159 UINT64_C(805306368), // LEA_ADDiu_MM
1160 UINT64_C(2214592512), // LH
1161 UINT64_C(2214592512), // LH64
1162 UINT64_C(2080374829), // LHE
1163 UINT64_C(1610639872), // LHE_MM
1164 UINT64_C(10240), // LHU16_MM
1165 UINT64_C(2080375050), // LHX
1166 UINT64_C(357), // LHX_MM
1167 UINT64_C(1006632960), // LH_MM
1168 UINT64_C(2483027968), // LHu
1169 UINT64_C(2483027968), // LHu64
1170 UINT64_C(2080374825), // LHuE
1171 UINT64_C(1610637824), // LHuE_MM
1172 UINT64_C(872415232), // LHu_MM
1173 UINT64_C(60416), // LI16_MM
1174 UINT64_C(60416), // LI16_MMR6
1175 UINT64_C(3221225472), // LL
1176 UINT64_C(3221225472), // LL64
1177 UINT64_C(2080374838), // LL64_R6
1178 UINT64_C(3489660928), // LLD
1179 UINT64_C(2080374839), // LLD_R6
1180 UINT64_C(2080374830), // LLE
1181 UINT64_C(1610640384), // LLE_MM
1182 UINT64_C(1610625024), // LL_MM
1183 UINT64_C(1610625024), // LL_MMR6
1184 UINT64_C(2080374838), // LL_R6
1185 UINT64_C(5), // LSA
1186 UINT64_C(15), // LSA_MMR6
1187 UINT64_C(5), // LSA_R6
1188 UINT64_C(268435456), // LUI_MMR6
1189 UINT64_C(1275068421), // LUXC1
1190 UINT64_C(1275068421), // LUXC164
1191 UINT64_C(1409286472), // LUXC1_MM
1192 UINT64_C(1006632960), // LUi
1193 UINT64_C(1006632960), // LUi64
1194 UINT64_C(1101004800), // LUi_MM
1195 UINT64_C(2348810240), // LW
1196 UINT64_C(26624), // LW16_MM
1197 UINT64_C(2348810240), // LW64
1198 UINT64_C(3288334336), // LWC1
1199 UINT64_C(2617245696), // LWC1_MM
1200 UINT64_C(3355443200), // LWC2
1201 UINT64_C(536870912), // LWC2_MMR6
1202 UINT64_C(1228931072), // LWC2_R6
1203 UINT64_C(3422552064), // LWC3
1204 UINT64_C(2348810240), // LWDSP
1205 UINT64_C(4227858432), // LWDSP_MM
1206 UINT64_C(2080374831), // LWE
1207 UINT64_C(1610640896), // LWE_MM
1208 UINT64_C(25600), // LWGP_MM
1209 UINT64_C(2281701376), // LWL
1210 UINT64_C(2281701376), // LWL64
1211 UINT64_C(2080374809), // LWLE
1212 UINT64_C(1610638336), // LWLE_MM
1213 UINT64_C(1610612736), // LWL_MM
1214 UINT64_C(17664), // LWM16_MM
1215 UINT64_C(17410), // LWM16_MMR6
1216 UINT64_C(536891392), // LWM32_MM
1217 UINT64_C(3959947264), // LWPC
1218 UINT64_C(2013790208), // LWPC_MMR6
1219 UINT64_C(536875008), // LWP_MM
1220 UINT64_C(2550136832), // LWR
1221 UINT64_C(2550136832), // LWR64
1222 UINT64_C(2080374810), // LWRE
1223 UINT64_C(1610638848), // LWRE_MM
1224 UINT64_C(1610616832), // LWR_MM
1225 UINT64_C(18432), // LWSP_MM
1226 UINT64_C(3960471552), // LWUPC
1227 UINT64_C(1610670080), // LWU_MM
1228 UINT64_C(2080374794), // LWX
1229 UINT64_C(1275068416), // LWXC1
1230 UINT64_C(1409286216), // LWXC1_MM
1231 UINT64_C(280), // LWXS_MM
1232 UINT64_C(421), // LWX_MM
1233 UINT64_C(4227858432), // LW_MM
1234 UINT64_C(4227858432), // LW_MMR6
1235 UINT64_C(2617245696), // LWu
1236 UINT64_C(4026570752), // LbRxRyOffMemX16
1237 UINT64_C(4026572800), // LbuRxRyOffMemX16
1238 UINT64_C(4026572800), // LhRxRyOffMemX16
1239 UINT64_C(4026572800), // LhuRxRyOffMemX16
1240 UINT64_C(26624), // LiRxImm16
1241 UINT64_C(4026558464), // LiRxImmAlignX16
1242 UINT64_C(4026558464), // LiRxImmX16
1243 UINT64_C(45056), // LwRxPcTcp16
1244 UINT64_C(4026576896), // LwRxPcTcpX16
1245 UINT64_C(4026570752), // LwRxRyOffMemX16
1246 UINT64_C(4026568704), // LwRxSpImmX16
1247 UINT64_C(1879048192), // MADD
1248 UINT64_C(1176502296), // MADDF_D
1249 UINT64_C(1409287096), // MADDF_D_MMR6
1250 UINT64_C(1174405144), // MADDF_S
1251 UINT64_C(1409286584), // MADDF_S_MMR6
1252 UINT64_C(2067791900), // MADDR_Q_H
1253 UINT64_C(2069889052), // MADDR_Q_W
1254 UINT64_C(1879048193), // MADDU
1255 UINT64_C(1879048193), // MADDU_DSP
1256 UINT64_C(6844), // MADDU_DSP_MM
1257 UINT64_C(56124), // MADDU_MM
1258 UINT64_C(2021654546), // MADDV_B
1259 UINT64_C(2027946002), // MADDV_D
1260 UINT64_C(2023751698), // MADDV_H
1261 UINT64_C(2025848850), // MADDV_W
1262 UINT64_C(1275068449), // MADD_D32
1263 UINT64_C(1409286153), // MADD_D32_MM
1264 UINT64_C(1275068449), // MADD_D64
1265 UINT64_C(1879048192), // MADD_DSP
1266 UINT64_C(2748), // MADD_DSP_MM
1267 UINT64_C(52028), // MADD_MM
1268 UINT64_C(2034237468), // MADD_Q_H
1269 UINT64_C(2036334620), // MADD_Q_W
1270 UINT64_C(1275068448), // MADD_S
1271 UINT64_C(1409286145), // MADD_S_MM
1272 UINT64_C(2080375856), // MAQ_SA_W_PHL
1273 UINT64_C(14972), // MAQ_SA_W_PHL_MM
1274 UINT64_C(2080375984), // MAQ_SA_W_PHR
1275 UINT64_C(10876), // MAQ_SA_W_PHR_MM
1276 UINT64_C(2080376112), // MAQ_S_W_PHL
1277 UINT64_C(6780), // MAQ_S_W_PHL_MM
1278 UINT64_C(2080376240), // MAQ_S_W_PHR
1279 UINT64_C(2684), // MAQ_S_W_PHR_MM
1280 UINT64_C(1176502303), // MAXA_D
1281 UINT64_C(1409286699), // MAXA_D_MMR6
1282 UINT64_C(1174405151), // MAXA_S
1283 UINT64_C(1409286187), // MAXA_S_MMR6
1284 UINT64_C(2030043142), // MAXI_S_B
1285 UINT64_C(2036334598), // MAXI_S_D
1286 UINT64_C(2032140294), // MAXI_S_H
1287 UINT64_C(2034237446), // MAXI_S_W
1288 UINT64_C(2038431750), // MAXI_U_B
1289 UINT64_C(2044723206), // MAXI_U_D
1290 UINT64_C(2040528902), // MAXI_U_H
1291 UINT64_C(2042626054), // MAXI_U_W
1292 UINT64_C(2063597582), // MAX_A_B
1293 UINT64_C(2069889038), // MAX_A_D
1294 UINT64_C(2065694734), // MAX_A_H
1295 UINT64_C(2067791886), // MAX_A_W
1296 UINT64_C(1176502302), // MAX_D
1297 UINT64_C(1409286667), // MAX_D_MMR6
1298 UINT64_C(1174405150), // MAX_S
1299 UINT64_C(2030043150), // MAX_S_B
1300 UINT64_C(2036334606), // MAX_S_D
1301 UINT64_C(2032140302), // MAX_S_H
1302 UINT64_C(1409286155), // MAX_S_MMR6
1303 UINT64_C(2034237454), // MAX_S_W
1304 UINT64_C(2038431758), // MAX_U_B
1305 UINT64_C(2044723214), // MAX_U_D
1306 UINT64_C(2040528910), // MAX_U_H
1307 UINT64_C(2042626062), // MAX_U_W
1308 UINT64_C(1073741824), // MFC0
1309 UINT64_C(252), // MFC0_MMR6
1310 UINT64_C(1140850688), // MFC1
1311 UINT64_C(1140850688), // MFC1_D64
1312 UINT64_C(1409294395), // MFC1_MM
1313 UINT64_C(1409294395), // MFC1_MMR6
1314 UINT64_C(1207959552), // MFC2
1315 UINT64_C(19772), // MFC2_MMR6
1316 UINT64_C(1080033280), // MFGC0
1317 UINT64_C(1276), // MFGC0_MM
1318 UINT64_C(244), // MFHC0_MMR6
1319 UINT64_C(1147142144), // MFHC1_D32
1320 UINT64_C(1409298491), // MFHC1_D32_MM
1321 UINT64_C(1147142144), // MFHC1_D64
1322 UINT64_C(1409298491), // MFHC1_D64_MM
1323 UINT64_C(36156), // MFHC2_MMR6
1324 UINT64_C(1080034304), // MFHGC0
1325 UINT64_C(1268), // MFHGC0_MM
1326 UINT64_C(16), // MFHI
1327 UINT64_C(17920), // MFHI16_MM
1328 UINT64_C(16), // MFHI64
1329 UINT64_C(16), // MFHI_DSP
1330 UINT64_C(124), // MFHI_DSP_MM
1331 UINT64_C(3452), // MFHI_MM
1332 UINT64_C(18), // MFLO
1333 UINT64_C(17984), // MFLO16_MM
1334 UINT64_C(18), // MFLO64
1335 UINT64_C(18), // MFLO_DSP
1336 UINT64_C(4220), // MFLO_DSP_MM
1337 UINT64_C(7548), // MFLO_MM
1338 UINT64_C(1090519040), // MFTR
1339 UINT64_C(1176502301), // MINA_D
1340 UINT64_C(1409286691), // MINA_D_MMR6
1341 UINT64_C(1174405149), // MINA_S
1342 UINT64_C(1409286179), // MINA_S_MMR6
1343 UINT64_C(2046820358), // MINI_S_B
1344 UINT64_C(2053111814), // MINI_S_D
1345 UINT64_C(2048917510), // MINI_S_H
1346 UINT64_C(2051014662), // MINI_S_W
1347 UINT64_C(2055208966), // MINI_U_B
1348 UINT64_C(2061500422), // MINI_U_D
1349 UINT64_C(2057306118), // MINI_U_H
1350 UINT64_C(2059403270), // MINI_U_W
1351 UINT64_C(2071986190), // MIN_A_B
1352 UINT64_C(2078277646), // MIN_A_D
1353 UINT64_C(2074083342), // MIN_A_H
1354 UINT64_C(2076180494), // MIN_A_W
1355 UINT64_C(1176502300), // MIN_D
1356 UINT64_C(1409286659), // MIN_D_MMR6
1357 UINT64_C(1174405148), // MIN_S
1358 UINT64_C(2046820366), // MIN_S_B
1359 UINT64_C(2053111822), // MIN_S_D
1360 UINT64_C(2048917518), // MIN_S_H
1361 UINT64_C(1409286147), // MIN_S_MMR6
1362 UINT64_C(2051014670), // MIN_S_W
1363 UINT64_C(2055208974), // MIN_U_B
1364 UINT64_C(2061500430), // MIN_U_D
1365 UINT64_C(2057306126), // MIN_U_H
1366 UINT64_C(2059403278), // MIN_U_W
1367 UINT64_C(218), // MOD
1368 UINT64_C(2080375952), // MODSUB
1369 UINT64_C(661), // MODSUB_MM
1370 UINT64_C(219), // MODU
1371 UINT64_C(472), // MODU_MMR6
1372 UINT64_C(344), // MOD_MMR6
1373 UINT64_C(2063597586), // MOD_S_B
1374 UINT64_C(2069889042), // MOD_S_D
1375 UINT64_C(2065694738), // MOD_S_H
1376 UINT64_C(2067791890), // MOD_S_W
1377 UINT64_C(2071986194), // MOD_U_B
1378 UINT64_C(2078277650), // MOD_U_D
1379 UINT64_C(2074083346), // MOD_U_H
1380 UINT64_C(2076180498), // MOD_U_W
1381 UINT64_C(3072), // MOVE16_MM
1382 UINT64_C(3072), // MOVE16_MMR6
1383 UINT64_C(33792), // MOVEP_MM
1384 UINT64_C(17412), // MOVEP_MMR6
1385 UINT64_C(2025717785), // MOVE_V
1386 UINT64_C(1176502289), // MOVF_D32
1387 UINT64_C(1409286688), // MOVF_D32_MM
1388 UINT64_C(1176502289), // MOVF_D64
1389 UINT64_C(1), // MOVF_I
1390 UINT64_C(1), // MOVF_I64
1391 UINT64_C(1409286523), // MOVF_I_MM
1392 UINT64_C(1174405137), // MOVF_S
1393 UINT64_C(1409286176), // MOVF_S_MM
1394 UINT64_C(1176502291), // MOVN_I64_D64
1395 UINT64_C(11), // MOVN_I64_I
1396 UINT64_C(11), // MOVN_I64_I64
1397 UINT64_C(1174405139), // MOVN_I64_S
1398 UINT64_C(1176502291), // MOVN_I_D32
1399 UINT64_C(1409286456), // MOVN_I_D32_MM
1400 UINT64_C(1176502291), // MOVN_I_D64
1401 UINT64_C(11), // MOVN_I_I
1402 UINT64_C(11), // MOVN_I_I64
1403 UINT64_C(24), // MOVN_I_MM
1404 UINT64_C(1174405139), // MOVN_I_S
1405 UINT64_C(1409286200), // MOVN_I_S_MM
1406 UINT64_C(1176567825), // MOVT_D32
1407 UINT64_C(1409286752), // MOVT_D32_MM
1408 UINT64_C(1176567825), // MOVT_D64
1409 UINT64_C(65537), // MOVT_I
1410 UINT64_C(65537), // MOVT_I64
1411 UINT64_C(1409288571), // MOVT_I_MM
1412 UINT64_C(1174470673), // MOVT_S
1413 UINT64_C(1409286240), // MOVT_S_MM
1414 UINT64_C(1176502290), // MOVZ_I64_D64
1415 UINT64_C(10), // MOVZ_I64_I
1416 UINT64_C(10), // MOVZ_I64_I64
1417 UINT64_C(1174405138), // MOVZ_I64_S
1418 UINT64_C(1176502290), // MOVZ_I_D32
1419 UINT64_C(1409286520), // MOVZ_I_D32_MM
1420 UINT64_C(1176502290), // MOVZ_I_D64
1421 UINT64_C(10), // MOVZ_I_I
1422 UINT64_C(10), // MOVZ_I_I64
1423 UINT64_C(88), // MOVZ_I_MM
1424 UINT64_C(1174405138), // MOVZ_I_S
1425 UINT64_C(1409286264), // MOVZ_I_S_MM
1426 UINT64_C(1879048196), // MSUB
1427 UINT64_C(1176502297), // MSUBF_D
1428 UINT64_C(1409287160), // MSUBF_D_MMR6
1429 UINT64_C(1174405145), // MSUBF_S
1430 UINT64_C(1409286648), // MSUBF_S_MMR6
1431 UINT64_C(2071986204), // MSUBR_Q_H
1432 UINT64_C(2074083356), // MSUBR_Q_W
1433 UINT64_C(1879048197), // MSUBU
1434 UINT64_C(1879048197), // MSUBU_DSP
1435 UINT64_C(15036), // MSUBU_DSP_MM
1436 UINT64_C(64316), // MSUBU_MM
1437 UINT64_C(2030043154), // MSUBV_B
1438 UINT64_C(2036334610), // MSUBV_D
1439 UINT64_C(2032140306), // MSUBV_H
1440 UINT64_C(2034237458), // MSUBV_W
1441 UINT64_C(1275068457), // MSUB_D32
1442 UINT64_C(1409286185), // MSUB_D32_MM
1443 UINT64_C(1275068457), // MSUB_D64
1444 UINT64_C(1879048196), // MSUB_DSP
1445 UINT64_C(10940), // MSUB_DSP_MM
1446 UINT64_C(60220), // MSUB_MM
1447 UINT64_C(2038431772), // MSUB_Q_H
1448 UINT64_C(2040528924), // MSUB_Q_W
1449 UINT64_C(1275068456), // MSUB_S
1450 UINT64_C(1409286177), // MSUB_S_MM
1451 UINT64_C(1082130432), // MTC0
1452 UINT64_C(764), // MTC0_MMR6
1453 UINT64_C(1149239296), // MTC1
1454 UINT64_C(1149239296), // MTC1_D64
1455 UINT64_C(1409296443), // MTC1_D64_MM
1456 UINT64_C(1409296443), // MTC1_MM
1457 UINT64_C(1409296443), // MTC1_MMR6
1458 UINT64_C(1216348160), // MTC2
1459 UINT64_C(23868), // MTC2_MMR6
1460 UINT64_C(1080033792), // MTGC0
1461 UINT64_C(1788), // MTGC0_MM
1462 UINT64_C(756), // MTHC0_MMR6
1463 UINT64_C(1155530752), // MTHC1_D32
1464 UINT64_C(1409300539), // MTHC1_D32_MM
1465 UINT64_C(1155530752), // MTHC1_D64
1466 UINT64_C(1409300539), // MTHC1_D64_MM
1467 UINT64_C(40252), // MTHC2_MMR6
1468 UINT64_C(1080034816), // MTHGC0
1469 UINT64_C(1780), // MTHGC0_MM
1470 UINT64_C(17), // MTHI
1471 UINT64_C(17), // MTHI64
1472 UINT64_C(17), // MTHI_DSP
1473 UINT64_C(8316), // MTHI_DSP_MM
1474 UINT64_C(11644), // MTHI_MM
1475 UINT64_C(2080376824), // MTHLIP
1476 UINT64_C(636), // MTHLIP_MM
1477 UINT64_C(19), // MTLO
1478 UINT64_C(19), // MTLO64
1479 UINT64_C(19), // MTLO_DSP
1480 UINT64_C(12412), // MTLO_DSP_MM
1481 UINT64_C(15740), // MTLO_MM
1482 UINT64_C(1879048200), // MTM0
1483 UINT64_C(1879048204), // MTM1
1484 UINT64_C(1879048205), // MTM2
1485 UINT64_C(1879048201), // MTP0
1486 UINT64_C(1879048202), // MTP1
1487 UINT64_C(1879048203), // MTP2
1488 UINT64_C(1098907648), // MTTR
1489 UINT64_C(216), // MUH
1490 UINT64_C(217), // MUHU
1491 UINT64_C(216), // MUHU_MMR6
1492 UINT64_C(88), // MUH_MMR6
1493 UINT64_C(1879048194), // MUL
1494 UINT64_C(2080376592), // MULEQ_S_W_PHL
1495 UINT64_C(37), // MULEQ_S_W_PHL_MM
1496 UINT64_C(2080376656), // MULEQ_S_W_PHR
1497 UINT64_C(101), // MULEQ_S_W_PHR_MM
1498 UINT64_C(2080375184), // MULEU_S_PH_QBL
1499 UINT64_C(149), // MULEU_S_PH_QBL_MM
1500 UINT64_C(2080375248), // MULEU_S_PH_QBR
1501 UINT64_C(213), // MULEU_S_PH_QBR_MM
1502 UINT64_C(2080376784), // MULQ_RS_PH
1503 UINT64_C(277), // MULQ_RS_PH_MM
1504 UINT64_C(2080376280), // MULQ_RS_W
1505 UINT64_C(405), // MULQ_RS_W_MMR2
1506 UINT64_C(2080376720), // MULQ_S_PH
1507 UINT64_C(341), // MULQ_S_PH_MMR2
1508 UINT64_C(2080376216), // MULQ_S_W
1509 UINT64_C(469), // MULQ_S_W_MMR2
1510 UINT64_C(1186988058), // MULR_PS64
1511 UINT64_C(2063597596), // MULR_Q_H
1512 UINT64_C(2065694748), // MULR_Q_W
1513 UINT64_C(2080375216), // MULSAQ_S_W_PH
1514 UINT64_C(15548), // MULSAQ_S_W_PH_MM
1515 UINT64_C(2080374960), // MULSA_W_PH
1516 UINT64_C(11452), // MULSA_W_PH_MMR2
1517 UINT64_C(24), // MULT
1518 UINT64_C(25), // MULTU_DSP
1519 UINT64_C(7356), // MULTU_DSP_MM
1520 UINT64_C(24), // MULT_DSP
1521 UINT64_C(3260), // MULT_DSP_MM
1522 UINT64_C(35644), // MULT_MM
1523 UINT64_C(25), // MULTu
1524 UINT64_C(39740), // MULTu_MM
1525 UINT64_C(153), // MULU
1526 UINT64_C(152), // MULU_MMR6
1527 UINT64_C(2013265938), // MULV_B
1528 UINT64_C(2019557394), // MULV_D
1529 UINT64_C(2015363090), // MULV_H
1530 UINT64_C(2017460242), // MULV_W
1531 UINT64_C(528), // MUL_MM
1532 UINT64_C(24), // MUL_MMR6
1533 UINT64_C(2080375576), // MUL_PH
1534 UINT64_C(45), // MUL_PH_MMR2
1535 UINT64_C(2030043164), // MUL_Q_H
1536 UINT64_C(2032140316), // MUL_Q_W
1537 UINT64_C(152), // MUL_R6
1538 UINT64_C(2080375704), // MUL_S_PH
1539 UINT64_C(1069), // MUL_S_PH_MMR2
1540 UINT64_C(59408), // Mfhi16
1541 UINT64_C(59410), // Mflo16
1542 UINT64_C(25856), // Move32R16
1543 UINT64_C(26368), // MoveR3216
1544 UINT64_C(68157440), // NAL
1545 UINT64_C(2064121886), // NLOC_B
1546 UINT64_C(2064318494), // NLOC_D
1547 UINT64_C(2064187422), // NLOC_H
1548 UINT64_C(2064252958), // NLOC_W
1549 UINT64_C(2064384030), // NLZC_B
1550 UINT64_C(2064580638), // NLZC_D
1551 UINT64_C(2064449566), // NLZC_H
1552 UINT64_C(2064515102), // NLZC_W
1553 UINT64_C(1275068465), // NMADD_D32
1554 UINT64_C(1409286154), // NMADD_D32_MM
1555 UINT64_C(1275068465), // NMADD_D64
1556 UINT64_C(1275068464), // NMADD_S
1557 UINT64_C(1409286146), // NMADD_S_MM
1558 UINT64_C(1275068473), // NMSUB_D32
1559 UINT64_C(1409286186), // NMSUB_D32_MM
1560 UINT64_C(1275068473), // NMSUB_D64
1561 UINT64_C(1275068472), // NMSUB_S
1562 UINT64_C(1409286178), // NMSUB_S_MM
1563 UINT64_C(39), // NOR
1564 UINT64_C(39), // NOR64
1565 UINT64_C(2046820352), // NORI_B
1566 UINT64_C(720), // NOR_MM
1567 UINT64_C(720), // NOR_MMR6
1568 UINT64_C(2017460254), // NOR_V
1569 UINT64_C(17408), // NOT16_MM
1570 UINT64_C(17408), // NOT16_MMR6
1571 UINT64_C(59421), // NegRxRy16
1572 UINT64_C(59407), // NotRxRy16
1573 UINT64_C(37), // OR
1574 UINT64_C(17600), // OR16_MM
1575 UINT64_C(17417), // OR16_MMR6
1576 UINT64_C(37), // OR64
1577 UINT64_C(2030043136), // ORI_B
1578 UINT64_C(1342177280), // ORI_MMR6
1579 UINT64_C(656), // OR_MM
1580 UINT64_C(656), // OR_MMR6
1581 UINT64_C(2015363102), // OR_V
1582 UINT64_C(872415232), // ORi
1583 UINT64_C(872415232), // ORi64
1584 UINT64_C(1342177280), // ORi_MM
1585 UINT64_C(59405), // OrRxRxRy16
1586 UINT64_C(2080375697), // PACKRL_PH
1587 UINT64_C(429), // PACKRL_PH_MM
1588 UINT64_C(320), // PAUSE
1589 UINT64_C(10240), // PAUSE_MM
1590 UINT64_C(10240), // PAUSE_MMR6
1591 UINT64_C(2030043156), // PCKEV_B
1592 UINT64_C(2036334612), // PCKEV_D
1593 UINT64_C(2032140308), // PCKEV_H
1594 UINT64_C(2034237460), // PCKEV_W
1595 UINT64_C(2038431764), // PCKOD_B
1596 UINT64_C(2044723220), // PCKOD_D
1597 UINT64_C(2040528916), // PCKOD_H
1598 UINT64_C(2042626068), // PCKOD_W
1599 UINT64_C(2063859742), // PCNT_B
1600 UINT64_C(2064056350), // PCNT_D
1601 UINT64_C(2063925278), // PCNT_H
1602 UINT64_C(2063990814), // PCNT_W
1603 UINT64_C(2080375505), // PICK_PH
1604 UINT64_C(557), // PICK_PH_MM
1605 UINT64_C(2080374993), // PICK_QB
1606 UINT64_C(493), // PICK_QB_MM
1607 UINT64_C(1186988076), // PLL_PS64
1608 UINT64_C(1186988077), // PLU_PS64
1609 UINT64_C(1879048236), // POP
1610 UINT64_C(2080375058), // PRECEQU_PH_QBL
1611 UINT64_C(2080375186), // PRECEQU_PH_QBLA
1612 UINT64_C(29500), // PRECEQU_PH_QBLA_MM
1613 UINT64_C(28988), // PRECEQU_PH_QBL_MM
1614 UINT64_C(2080375122), // PRECEQU_PH_QBR
1615 UINT64_C(2080375250), // PRECEQU_PH_QBRA
1616 UINT64_C(37692), // PRECEQU_PH_QBRA_MM
1617 UINT64_C(37180), // PRECEQU_PH_QBR_MM
1618 UINT64_C(2080375570), // PRECEQ_W_PHL
1619 UINT64_C(20796), // PRECEQ_W_PHL_MM
1620 UINT64_C(2080375634), // PRECEQ_W_PHR
1621 UINT64_C(24892), // PRECEQ_W_PHR_MM
1622 UINT64_C(2080376594), // PRECEU_PH_QBL
1623 UINT64_C(2080376722), // PRECEU_PH_QBLA
1624 UINT64_C(45884), // PRECEU_PH_QBLA_MM
1625 UINT64_C(45372), // PRECEU_PH_QBL_MM
1626 UINT64_C(2080376658), // PRECEU_PH_QBR
1627 UINT64_C(2080376786), // PRECEU_PH_QBRA
1628 UINT64_C(54076), // PRECEU_PH_QBRA_MM
1629 UINT64_C(53564), // PRECEU_PH_QBR_MM
1630 UINT64_C(2080375761), // PRECRQU_S_QB_PH
1631 UINT64_C(365), // PRECRQU_S_QB_PH_MM
1632 UINT64_C(2080376081), // PRECRQ_PH_W
1633 UINT64_C(237), // PRECRQ_PH_W_MM
1634 UINT64_C(2080375569), // PRECRQ_QB_PH
1635 UINT64_C(173), // PRECRQ_QB_PH_MM
1636 UINT64_C(2080376145), // PRECRQ_RS_PH_W
1637 UINT64_C(301), // PRECRQ_RS_PH_W_MM
1638 UINT64_C(2080375633), // PRECR_QB_PH
1639 UINT64_C(109), // PRECR_QB_PH_MMR2
1640 UINT64_C(2080376721), // PRECR_SRA_PH_W
1641 UINT64_C(973), // PRECR_SRA_PH_W_MMR2
1642 UINT64_C(2080376785), // PRECR_SRA_R_PH_W
1643 UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2
1644 UINT64_C(3422552064), // PREF
1645 UINT64_C(2080374819), // PREFE
1646 UINT64_C(1610654720), // PREFE_MM
1647 UINT64_C(1409286560), // PREFX_MM
1648 UINT64_C(1610620928), // PREF_MM
1649 UINT64_C(1610620928), // PREF_MMR6
1650 UINT64_C(2080374837), // PREF_R6
1651 UINT64_C(2080374897), // PREPEND
1652 UINT64_C(597), // PREPEND_MMR2
1653 UINT64_C(1186988078), // PUL_PS64
1654 UINT64_C(1186988079), // PUU_PS64
1655 UINT64_C(2080376080), // RADDU_W_QB
1656 UINT64_C(61756), // RADDU_W_QB_MM
1657 UINT64_C(2080375992), // RDDSP
1658 UINT64_C(1660), // RDDSP_MM
1659 UINT64_C(2080374843), // RDHWR
1660 UINT64_C(2080374843), // RDHWR64
1661 UINT64_C(27452), // RDHWR_MM
1662 UINT64_C(448), // RDHWR_MMR6
1663 UINT64_C(57724), // RDPGPR_MMR6
1664 UINT64_C(1176502293), // RECIP_D32
1665 UINT64_C(1409307195), // RECIP_D32_MM
1666 UINT64_C(1176502293), // RECIP_D64
1667 UINT64_C(1409307195), // RECIP_D64_MM
1668 UINT64_C(1174405141), // RECIP_S
1669 UINT64_C(1409290811), // RECIP_S_MM
1670 UINT64_C(2080375506), // REPLV_PH
1671 UINT64_C(828), // REPLV_PH_MM
1672 UINT64_C(2080374994), // REPLV_QB
1673 UINT64_C(4924), // REPLV_QB_MM
1674 UINT64_C(2080375442), // REPL_PH
1675 UINT64_C(61), // REPL_PH_MM
1676 UINT64_C(2080374930), // REPL_QB
1677 UINT64_C(1532), // REPL_QB_MM
1678 UINT64_C(1176502298), // RINT_D
1679 UINT64_C(1409286688), // RINT_D_MMR6
1680 UINT64_C(1174405146), // RINT_S
1681 UINT64_C(1409286176), // RINT_S_MMR6
1682 UINT64_C(2097154), // ROTR
1683 UINT64_C(70), // ROTRV
1684 UINT64_C(208), // ROTRV_MM
1685 UINT64_C(192), // ROTR_MM
1686 UINT64_C(1176502280), // ROUND_L_D64
1687 UINT64_C(1409315643), // ROUND_L_D_MMR6
1688 UINT64_C(1174405128), // ROUND_L_S
1689 UINT64_C(1409299259), // ROUND_L_S_MMR6
1690 UINT64_C(1176502284), // ROUND_W_D32
1691 UINT64_C(1176502284), // ROUND_W_D64
1692 UINT64_C(1409317691), // ROUND_W_D_MMR6
1693 UINT64_C(1409317691), // ROUND_W_MM
1694 UINT64_C(1174405132), // ROUND_W_S
1695 UINT64_C(1409301307), // ROUND_W_S_MM
1696 UINT64_C(1409301307), // ROUND_W_S_MMR6
1697 UINT64_C(1176502294), // RSQRT_D32
1698 UINT64_C(1409303099), // RSQRT_D32_MM
1699 UINT64_C(1176502294), // RSQRT_D64
1700 UINT64_C(1409303099), // RSQRT_D64_MM
1701 UINT64_C(1174405142), // RSQRT_S
1702 UINT64_C(1409286715), // RSQRT_S_MM
1703 UINT64_C(25728), // Restore16
1704 UINT64_C(25728), // RestoreX16
1705 UINT64_C(1879048216), // SAA
1706 UINT64_C(1879048217), // SAAD
1707 UINT64_C(2020605962), // SAT_S_B
1708 UINT64_C(2013265930), // SAT_S_D
1709 UINT64_C(2019557386), // SAT_S_H
1710 UINT64_C(2017460234), // SAT_S_W
1711 UINT64_C(2028994570), // SAT_U_B
1712 UINT64_C(2021654538), // SAT_U_D
1713 UINT64_C(2027945994), // SAT_U_H
1714 UINT64_C(2025848842), // SAT_U_W
1715 UINT64_C(2684354560), // SB
1716 UINT64_C(34816), // SB16_MM
1717 UINT64_C(34816), // SB16_MMR6
1718 UINT64_C(2684354560), // SB64
1719 UINT64_C(2080374812), // SBE
1720 UINT64_C(1610655744), // SBE_MM
1721 UINT64_C(402653184), // SB_MM
1722 UINT64_C(402653184), // SB_MMR6
1723 UINT64_C(3758096384), // SC
1724 UINT64_C(3758096384), // SC64
1725 UINT64_C(2080374822), // SC64_R6
1726 UINT64_C(4026531840), // SCD
1727 UINT64_C(2080374823), // SCD_R6
1728 UINT64_C(2080374814), // SCE
1729 UINT64_C(1610656768), // SCE_MM
1730 UINT64_C(1610657792), // SC_MM
1731 UINT64_C(1610657792), // SC_MMR6
1732 UINT64_C(2080374822), // SC_R6
1733 UINT64_C(4227858432), // SD
1734 UINT64_C(1879048255), // SDBBP
1735 UINT64_C(18112), // SDBBP16_MM
1736 UINT64_C(17467), // SDBBP16_MMR6
1737 UINT64_C(56188), // SDBBP_MM
1738 UINT64_C(56188), // SDBBP_MMR6
1739 UINT64_C(14), // SDBBP_R6
1740 UINT64_C(4093640704), // SDC1
1741 UINT64_C(4093640704), // SDC164
1742 UINT64_C(3087007744), // SDC1_D64_MMR6
1743 UINT64_C(3087007744), // SDC1_MM_D32
1744 UINT64_C(3087007744), // SDC1_MM_D64
1745 UINT64_C(4160749568), // SDC2
1746 UINT64_C(536911872), // SDC2_MMR6
1747 UINT64_C(1239416832), // SDC2_R6
1748 UINT64_C(4227858432), // SDC3
1749 UINT64_C(26), // SDIV
1750 UINT64_C(43836), // SDIV_MM
1751 UINT64_C(2952790016), // SDL
1752 UINT64_C(3019898880), // SDR
1753 UINT64_C(1275068425), // SDXC1
1754 UINT64_C(1275068425), // SDXC164
1755 UINT64_C(2080375840), // SEB
1756 UINT64_C(2080375840), // SEB64
1757 UINT64_C(11068), // SEB_MM
1758 UINT64_C(2080376352), // SEH
1759 UINT64_C(2080376352), // SEH64
1760 UINT64_C(15164), // SEH_MM
1761 UINT64_C(53), // SELEQZ
1762 UINT64_C(53), // SELEQZ64
1763 UINT64_C(1176502292), // SELEQZ_D
1764 UINT64_C(1409286712), // SELEQZ_D_MMR6
1765 UINT64_C(320), // SELEQZ_MMR6
1766 UINT64_C(1174405140), // SELEQZ_S
1767 UINT64_C(1409286200), // SELEQZ_S_MMR6
1768 UINT64_C(55), // SELNEZ
1769 UINT64_C(55), // SELNEZ64
1770 UINT64_C(1176502295), // SELNEZ_D
1771 UINT64_C(1409286776), // SELNEZ_D_MMR6
1772 UINT64_C(384), // SELNEZ_MMR6
1773 UINT64_C(1174405143), // SELNEZ_S
1774 UINT64_C(1409286264), // SELNEZ_S_MMR6
1775 UINT64_C(1176502288), // SEL_D
1776 UINT64_C(1409286840), // SEL_D_MMR6
1777 UINT64_C(1174405136), // SEL_S
1778 UINT64_C(1409286328), // SEL_S_MMR6
1779 UINT64_C(1879048234), // SEQ
1780 UINT64_C(1879048238), // SEQi
1781 UINT64_C(2751463424), // SH
1782 UINT64_C(43008), // SH16_MM
1783 UINT64_C(43008), // SH16_MMR6
1784 UINT64_C(2751463424), // SH64
1785 UINT64_C(2080374813), // SHE
1786 UINT64_C(1610656256), // SHE_MM
1787 UINT64_C(2013265922), // SHF_B
1788 UINT64_C(2030043138), // SHF_H
1789 UINT64_C(2046820354), // SHF_W
1790 UINT64_C(2080376504), // SHILO
1791 UINT64_C(2080376568), // SHILOV
1792 UINT64_C(4732), // SHILOV_MM
1793 UINT64_C(29), // SHILO_MM
1794 UINT64_C(2080375443), // SHLLV_PH
1795 UINT64_C(14), // SHLLV_PH_MM
1796 UINT64_C(2080374931), // SHLLV_QB
1797 UINT64_C(917), // SHLLV_QB_MM
1798 UINT64_C(2080375699), // SHLLV_S_PH
1799 UINT64_C(1038), // SHLLV_S_PH_MM
1800 UINT64_C(2080376211), // SHLLV_S_W
1801 UINT64_C(981), // SHLLV_S_W_MM
1802 UINT64_C(2080375315), // SHLL_PH
1803 UINT64_C(949), // SHLL_PH_MM
1804 UINT64_C(2080374803), // SHLL_QB
1805 UINT64_C(2172), // SHLL_QB_MM
1806 UINT64_C(2080375571), // SHLL_S_PH
1807 UINT64_C(2997), // SHLL_S_PH_MM
1808 UINT64_C(2080376083), // SHLL_S_W
1809 UINT64_C(1013), // SHLL_S_W_MM
1810 UINT64_C(2080375507), // SHRAV_PH
1811 UINT64_C(397), // SHRAV_PH_MM
1812 UINT64_C(2080375187), // SHRAV_QB
1813 UINT64_C(461), // SHRAV_QB_MMR2
1814 UINT64_C(2080375763), // SHRAV_R_PH
1815 UINT64_C(1421), // SHRAV_R_PH_MM
1816 UINT64_C(2080375251), // SHRAV_R_QB
1817 UINT64_C(1485), // SHRAV_R_QB_MMR2
1818 UINT64_C(2080376275), // SHRAV_R_W
1819 UINT64_C(725), // SHRAV_R_W_MM
1820 UINT64_C(2080375379), // SHRA_PH
1821 UINT64_C(821), // SHRA_PH_MM
1822 UINT64_C(2080375059), // SHRA_QB
1823 UINT64_C(508), // SHRA_QB_MMR2
1824 UINT64_C(2080375635), // SHRA_R_PH
1825 UINT64_C(1845), // SHRA_R_PH_MM
1826 UINT64_C(2080375123), // SHRA_R_QB
1827 UINT64_C(4604), // SHRA_R_QB_MMR2
1828 UINT64_C(2080376147), // SHRA_R_W
1829 UINT64_C(757), // SHRA_R_W_MM
1830 UINT64_C(2080376531), // SHRLV_PH
1831 UINT64_C(789), // SHRLV_PH_MMR2
1832 UINT64_C(2080374995), // SHRLV_QB
1833 UINT64_C(853), // SHRLV_QB_MM
1834 UINT64_C(2080376403), // SHRL_PH
1835 UINT64_C(1020), // SHRL_PH_MMR2
1836 UINT64_C(2080374867), // SHRL_QB
1837 UINT64_C(6268), // SHRL_QB_MM
1838 UINT64_C(939524096), // SH_MM
1839 UINT64_C(939524096), // SH_MMR6
1840 UINT64_C(68616192), // SIGRIE
1841 UINT64_C(63), // SIGRIE_MMR6
1842 UINT64_C(2013265945), // SLDI_B
1843 UINT64_C(2016935961), // SLDI_D
1844 UINT64_C(2015363097), // SLDI_H
1845 UINT64_C(2016411673), // SLDI_W
1846 UINT64_C(2013265940), // SLD_B
1847 UINT64_C(2019557396), // SLD_D
1848 UINT64_C(2015363092), // SLD_H
1849 UINT64_C(2017460244), // SLD_W
1850 UINT64_C(0), // SLL
1851 UINT64_C(9216), // SLL16_MM
1852 UINT64_C(9216), // SLL16_MMR6
1853 UINT64_C(0), // SLL64_32
1854 UINT64_C(0), // SLL64_64
1855 UINT64_C(2020605961), // SLLI_B
1856 UINT64_C(2013265929), // SLLI_D
1857 UINT64_C(2019557385), // SLLI_H
1858 UINT64_C(2017460233), // SLLI_W
1859 UINT64_C(4), // SLLV
1860 UINT64_C(16), // SLLV_MM
1861 UINT64_C(2013265933), // SLL_B
1862 UINT64_C(2019557389), // SLL_D
1863 UINT64_C(2015363085), // SLL_H
1864 UINT64_C(0), // SLL_MM
1865 UINT64_C(0), // SLL_MMR6
1866 UINT64_C(2017460237), // SLL_W
1867 UINT64_C(42), // SLT
1868 UINT64_C(42), // SLT64
1869 UINT64_C(848), // SLT_MM
1870 UINT64_C(671088640), // SLTi
1871 UINT64_C(671088640), // SLTi64
1872 UINT64_C(2415919104), // SLTi_MM
1873 UINT64_C(738197504), // SLTiu
1874 UINT64_C(738197504), // SLTiu64
1875 UINT64_C(2952790016), // SLTiu_MM
1876 UINT64_C(43), // SLTu
1877 UINT64_C(43), // SLTu64
1878 UINT64_C(912), // SLTu_MM
1879 UINT64_C(1879048235), // SNE
1880 UINT64_C(1879048239), // SNEi
1881 UINT64_C(2017460249), // SPLATI_B
1882 UINT64_C(2021130265), // SPLATI_D
1883 UINT64_C(2019557401), // SPLATI_H
1884 UINT64_C(2020605977), // SPLATI_W
1885 UINT64_C(2021654548), // SPLAT_B
1886 UINT64_C(2027946004), // SPLAT_D
1887 UINT64_C(2023751700), // SPLAT_H
1888 UINT64_C(2025848852), // SPLAT_W
1889 UINT64_C(3), // SRA
1890 UINT64_C(2028994569), // SRAI_B
1891 UINT64_C(2021654537), // SRAI_D
1892 UINT64_C(2027945993), // SRAI_H
1893 UINT64_C(2025848841), // SRAI_W
1894 UINT64_C(2037383178), // SRARI_B
1895 UINT64_C(2030043146), // SRARI_D
1896 UINT64_C(2036334602), // SRARI_H
1897 UINT64_C(2034237450), // SRARI_W
1898 UINT64_C(2021654549), // SRAR_B
1899 UINT64_C(2027946005), // SRAR_D
1900 UINT64_C(2023751701), // SRAR_H
1901 UINT64_C(2025848853), // SRAR_W
1902 UINT64_C(7), // SRAV
1903 UINT64_C(144), // SRAV_MM
1904 UINT64_C(2021654541), // SRA_B
1905 UINT64_C(2027945997), // SRA_D
1906 UINT64_C(2023751693), // SRA_H
1907 UINT64_C(128), // SRA_MM
1908 UINT64_C(2025848845), // SRA_W
1909 UINT64_C(2), // SRL
1910 UINT64_C(9217), // SRL16_MM
1911 UINT64_C(9217), // SRL16_MMR6
1912 UINT64_C(2037383177), // SRLI_B
1913 UINT64_C(2030043145), // SRLI_D
1914 UINT64_C(2036334601), // SRLI_H
1915 UINT64_C(2034237449), // SRLI_W
1916 UINT64_C(2045771786), // SRLRI_B
1917 UINT64_C(2038431754), // SRLRI_D
1918 UINT64_C(2044723210), // SRLRI_H
1919 UINT64_C(2042626058), // SRLRI_W
1920 UINT64_C(2030043157), // SRLR_B
1921 UINT64_C(2036334613), // SRLR_D
1922 UINT64_C(2032140309), // SRLR_H
1923 UINT64_C(2034237461), // SRLR_W
1924 UINT64_C(6), // SRLV
1925 UINT64_C(80), // SRLV_MM
1926 UINT64_C(2030043149), // SRL_B
1927 UINT64_C(2036334605), // SRL_D
1928 UINT64_C(2032140301), // SRL_H
1929 UINT64_C(64), // SRL_MM
1930 UINT64_C(2034237453), // SRL_W
1931 UINT64_C(64), // SSNOP
1932 UINT64_C(2048), // SSNOP_MM
1933 UINT64_C(2048), // SSNOP_MMR6
1934 UINT64_C(2013265956), // ST_B
1935 UINT64_C(2013265959), // ST_D
1936 UINT64_C(2013265957), // ST_H
1937 UINT64_C(2013265958), // ST_W
1938 UINT64_C(34), // SUB
1939 UINT64_C(2080375384), // SUBQH_PH
1940 UINT64_C(589), // SUBQH_PH_MMR2
1941 UINT64_C(2080375512), // SUBQH_R_PH
1942 UINT64_C(1613), // SUBQH_R_PH_MMR2
1943 UINT64_C(2080376024), // SUBQH_R_W
1944 UINT64_C(1677), // SUBQH_R_W_MMR2
1945 UINT64_C(2080375896), // SUBQH_W
1946 UINT64_C(653), // SUBQH_W_MMR2
1947 UINT64_C(2080375504), // SUBQ_PH
1948 UINT64_C(525), // SUBQ_PH_MM
1949 UINT64_C(2080375760), // SUBQ_S_PH
1950 UINT64_C(1549), // SUBQ_S_PH_MM
1951 UINT64_C(2080376272), // SUBQ_S_W
1952 UINT64_C(837), // SUBQ_S_W_MM
1953 UINT64_C(2030043153), // SUBSUS_U_B
1954 UINT64_C(2036334609), // SUBSUS_U_D
1955 UINT64_C(2032140305), // SUBSUS_U_H
1956 UINT64_C(2034237457), // SUBSUS_U_W
1957 UINT64_C(2038431761), // SUBSUU_S_B
1958 UINT64_C(2044723217), // SUBSUU_S_D
1959 UINT64_C(2040528913), // SUBSUU_S_H
1960 UINT64_C(2042626065), // SUBSUU_S_W
1961 UINT64_C(2013265937), // SUBS_S_B
1962 UINT64_C(2019557393), // SUBS_S_D
1963 UINT64_C(2015363089), // SUBS_S_H
1964 UINT64_C(2017460241), // SUBS_S_W
1965 UINT64_C(2021654545), // SUBS_U_B
1966 UINT64_C(2027946001), // SUBS_U_D
1967 UINT64_C(2023751697), // SUBS_U_H
1968 UINT64_C(2025848849), // SUBS_U_W
1969 UINT64_C(1025), // SUBU16_MM
1970 UINT64_C(1025), // SUBU16_MMR6
1971 UINT64_C(2080374872), // SUBUH_QB
1972 UINT64_C(845), // SUBUH_QB_MMR2
1973 UINT64_C(2080375000), // SUBUH_R_QB
1974 UINT64_C(1869), // SUBUH_R_QB_MMR2
1975 UINT64_C(464), // SUBU_MMR6
1976 UINT64_C(2080375376), // SUBU_PH
1977 UINT64_C(781), // SUBU_PH_MMR2
1978 UINT64_C(2080374864), // SUBU_QB
1979 UINT64_C(717), // SUBU_QB_MM
1980 UINT64_C(2080375632), // SUBU_S_PH
1981 UINT64_C(1805), // SUBU_S_PH_MMR2
1982 UINT64_C(2080375120), // SUBU_S_QB
1983 UINT64_C(1741), // SUBU_S_QB_MM
1984 UINT64_C(2021654534), // SUBVI_B
1985 UINT64_C(2027945990), // SUBVI_D
1986 UINT64_C(2023751686), // SUBVI_H
1987 UINT64_C(2025848838), // SUBVI_W
1988 UINT64_C(2021654542), // SUBV_B
1989 UINT64_C(2027945998), // SUBV_D
1990 UINT64_C(2023751694), // SUBV_H
1991 UINT64_C(2025848846), // SUBV_W
1992 UINT64_C(400), // SUB_MM
1993 UINT64_C(400), // SUB_MMR6
1994 UINT64_C(35), // SUBu
1995 UINT64_C(464), // SUBu_MM
1996 UINT64_C(1275068429), // SUXC1
1997 UINT64_C(1275068429), // SUXC164
1998 UINT64_C(1409286536), // SUXC1_MM
1999 UINT64_C(2885681152), // SW
2000 UINT64_C(59392), // SW16_MM
2001 UINT64_C(59392), // SW16_MMR6
2002 UINT64_C(2885681152), // SW64
2003 UINT64_C(3825205248), // SWC1
2004 UINT64_C(2550136832), // SWC1_MM
2005 UINT64_C(3892314112), // SWC2
2006 UINT64_C(536903680), // SWC2_MMR6
2007 UINT64_C(1231028224), // SWC2_R6
2008 UINT64_C(3959422976), // SWC3
2009 UINT64_C(2885681152), // SWDSP
2010 UINT64_C(4160749568), // SWDSP_MM
2011 UINT64_C(2080374815), // SWE
2012 UINT64_C(1610657280), // SWE_MM
2013 UINT64_C(2818572288), // SWL
2014 UINT64_C(2818572288), // SWL64
2015 UINT64_C(2080374817), // SWLE
2016 UINT64_C(1610653696), // SWLE_MM
2017 UINT64_C(1610645504), // SWL_MM
2018 UINT64_C(17728), // SWM16_MM
2019 UINT64_C(17418), // SWM16_MMR6
2020 UINT64_C(536924160), // SWM32_MM
2021 UINT64_C(536907776), // SWP_MM
2022 UINT64_C(3087007744), // SWR
2023 UINT64_C(3087007744), // SWR64
2024 UINT64_C(2080374818), // SWRE
2025 UINT64_C(1610654208), // SWRE_MM
2026 UINT64_C(1610649600), // SWR_MM
2027 UINT64_C(51200), // SWSP_MM
2028 UINT64_C(51200), // SWSP_MMR6
2029 UINT64_C(1275068424), // SWXC1
2030 UINT64_C(1409286280), // SWXC1_MM
2031 UINT64_C(4160749568), // SW_MM
2032 UINT64_C(4160749568), // SW_MMR6
2033 UINT64_C(15), // SYNC
2034 UINT64_C(69140480), // SYNCI
2035 UINT64_C(1107296256), // SYNCI_MM
2036 UINT64_C(1098907648), // SYNCI_MMR6
2037 UINT64_C(27516), // SYNC_MM
2038 UINT64_C(27516), // SYNC_MMR6
2039 UINT64_C(12), // SYSCALL
2040 UINT64_C(35708), // SYSCALL_MM
2041 UINT64_C(25728), // Save16
2042 UINT64_C(25728), // SaveX16
2043 UINT64_C(4026580992), // SbRxRyOffMemX16
2044 UINT64_C(59537), // SebRx16
2045 UINT64_C(59569), // SehRx16
2046 UINT64_C(4026583040), // ShRxRyOffMemX16
2047 UINT64_C(4026544128), // SllX16
2048 UINT64_C(59396), // SllvRxRy16
2049 UINT64_C(59394), // SltRxRy16
2050 UINT64_C(20480), // SltiRxImm16
2051 UINT64_C(4026552320), // SltiRxImmX16
2052 UINT64_C(22528), // SltiuRxImm16
2053 UINT64_C(4026554368), // SltiuRxImmX16
2054 UINT64_C(59395), // SltuRxRy16
2055 UINT64_C(4026544131), // SraX16
2056 UINT64_C(59399), // SravRxRy16
2057 UINT64_C(4026544130), // SrlX16
2058 UINT64_C(59398), // SrlvRxRy16
2059 UINT64_C(57347), // SubuRxRyRz16
2060 UINT64_C(4026587136), // SwRxRyOffMemX16
2061 UINT64_C(4026585088), // SwRxSpImmX16
2062 UINT64_C(52), // TEQ
2063 UINT64_C(67895296), // TEQI
2064 UINT64_C(1103101952), // TEQI_MM
2065 UINT64_C(60), // TEQ_MM
2066 UINT64_C(48), // TGE
2067 UINT64_C(67633152), // TGEI
2068 UINT64_C(67698688), // TGEIU
2069 UINT64_C(1096810496), // TGEIU_MM
2070 UINT64_C(1092616192), // TGEI_MM
2071 UINT64_C(49), // TGEU
2072 UINT64_C(1084), // TGEU_MM
2073 UINT64_C(572), // TGE_MM
2074 UINT64_C(1107296267), // TLBGINV
2075 UINT64_C(1107296268), // TLBGINVF
2076 UINT64_C(20860), // TLBGINVF_MM
2077 UINT64_C(16764), // TLBGINV_MM
2078 UINT64_C(1107296272), // TLBGP
2079 UINT64_C(380), // TLBGP_MM
2080 UINT64_C(1107296265), // TLBGR
2081 UINT64_C(4476), // TLBGR_MM
2082 UINT64_C(1107296266), // TLBGWI
2083 UINT64_C(8572), // TLBGWI_MM
2084 UINT64_C(1107296270), // TLBGWR
2085 UINT64_C(12668), // TLBGWR_MM
2086 UINT64_C(1107296259), // TLBINV
2087 UINT64_C(1107296260), // TLBINVF
2088 UINT64_C(21372), // TLBINVF_MMR6
2089 UINT64_C(17276), // TLBINV_MMR6
2090 UINT64_C(1107296264), // TLBP
2091 UINT64_C(892), // TLBP_MM
2092 UINT64_C(1107296257), // TLBR
2093 UINT64_C(4988), // TLBR_MM
2094 UINT64_C(1107296258), // TLBWI
2095 UINT64_C(9084), // TLBWI_MM
2096 UINT64_C(1107296262), // TLBWR
2097 UINT64_C(13180), // TLBWR_MM
2098 UINT64_C(50), // TLT
2099 UINT64_C(67764224), // TLTI
2100 UINT64_C(1094713344), // TLTIU_MM
2101 UINT64_C(1090519040), // TLTI_MM
2102 UINT64_C(51), // TLTU
2103 UINT64_C(2620), // TLTU_MM
2104 UINT64_C(2108), // TLT_MM
2105 UINT64_C(54), // TNE
2106 UINT64_C(68026368), // TNEI
2107 UINT64_C(1098907648), // TNEI_MM
2108 UINT64_C(3132), // TNE_MM
2109 UINT64_C(1176502281), // TRUNC_L_D64
2110 UINT64_C(1409311547), // TRUNC_L_D_MMR6
2111 UINT64_C(1174405129), // TRUNC_L_S
2112 UINT64_C(1409295163), // TRUNC_L_S_MMR6
2113 UINT64_C(1176502285), // TRUNC_W_D32
2114 UINT64_C(1176502285), // TRUNC_W_D64
2115 UINT64_C(1409313595), // TRUNC_W_D_MMR6
2116 UINT64_C(1409313595), // TRUNC_W_MM
2117 UINT64_C(1174405133), // TRUNC_W_S
2118 UINT64_C(1409297211), // TRUNC_W_S_MM
2119 UINT64_C(1409297211), // TRUNC_W_S_MMR6
2120 UINT64_C(67829760), // TTLTIU
2121 UINT64_C(27), // UDIV
2122 UINT64_C(47932), // UDIV_MM
2123 UINT64_C(1879048209), // V3MULU
2124 UINT64_C(1879048208), // VMM0
2125 UINT64_C(1879048207), // VMULU
2126 UINT64_C(2013265941), // VSHF_B
2127 UINT64_C(2019557397), // VSHF_D
2128 UINT64_C(2015363093), // VSHF_H
2129 UINT64_C(2017460245), // VSHF_W
2130 UINT64_C(1107296288), // WAIT
2131 UINT64_C(37756), // WAIT_MM
2132 UINT64_C(37756), // WAIT_MMR6
2133 UINT64_C(2080376056), // WRDSP
2134 UINT64_C(5756), // WRDSP_MM
2135 UINT64_C(61820), // WRPGPR_MMR6
2136 UINT64_C(2080374944), // WSBH
2137 UINT64_C(31548), // WSBH_MM
2138 UINT64_C(31548), // WSBH_MMR6
2139 UINT64_C(38), // XOR
2140 UINT64_C(17472), // XOR16_MM
2141 UINT64_C(17416), // XOR16_MMR6
2142 UINT64_C(38), // XOR64
2143 UINT64_C(2063597568), // XORI_B
2144 UINT64_C(1879048192), // XORI_MMR6
2145 UINT64_C(784), // XOR_MM
2146 UINT64_C(784), // XOR_MMR6
2147 UINT64_C(2019557406), // XOR_V
2148 UINT64_C(939524096), // XORi
2149 UINT64_C(939524096), // XORi64
2150 UINT64_C(1879048192), // XORi_MM
2151 UINT64_C(59406), // XorRxRxRy16
2152 UINT64_C(2080374793), // YIELD
2153 };
2154 constexpr unsigned FirstSupportedOpcode = 781;
2155
2156 const unsigned opcode = MI.getOpcode();
2157 if (opcode < FirstSupportedOpcode)
2158 reportUnsupportedInst(Inst: MI);
2159 unsigned TableIndex = opcode - FirstSupportedOpcode;
2160 uint64_t Value = InstBits[TableIndex];
2161 uint64_t op = 0;
2162 (void)op; // suppress warning
2163 switch (opcode) {
2164 case Mips::Break16:
2165 case Mips::DERET:
2166 case Mips::DERET_MM:
2167 case Mips::DERET_MMR6:
2168 case Mips::EHB:
2169 case Mips::EHB_MM:
2170 case Mips::EHB_MMR6:
2171 case Mips::ERET:
2172 case Mips::ERETNC:
2173 case Mips::ERETNC_MMR6:
2174 case Mips::ERET_MM:
2175 case Mips::ERET_MMR6:
2176 case Mips::JrRa16:
2177 case Mips::JrcRa16:
2178 case Mips::NAL:
2179 case Mips::PAUSE:
2180 case Mips::PAUSE_MM:
2181 case Mips::PAUSE_MMR6:
2182 case Mips::Restore16:
2183 case Mips::RestoreX16:
2184 case Mips::SSNOP:
2185 case Mips::SSNOP_MM:
2186 case Mips::SSNOP_MMR6:
2187 case Mips::Save16:
2188 case Mips::SaveX16:
2189 case Mips::TLBGINV:
2190 case Mips::TLBGINVF:
2191 case Mips::TLBGINVF_MM:
2192 case Mips::TLBGINV_MM:
2193 case Mips::TLBGP:
2194 case Mips::TLBGP_MM:
2195 case Mips::TLBGR:
2196 case Mips::TLBGR_MM:
2197 case Mips::TLBGWI:
2198 case Mips::TLBGWI_MM:
2199 case Mips::TLBGWR:
2200 case Mips::TLBGWR_MM:
2201 case Mips::TLBINV:
2202 case Mips::TLBINVF:
2203 case Mips::TLBINVF_MMR6:
2204 case Mips::TLBINV_MMR6:
2205 case Mips::TLBP:
2206 case Mips::TLBP_MM:
2207 case Mips::TLBR:
2208 case Mips::TLBR_MM:
2209 case Mips::TLBWI:
2210 case Mips::TLBWI_MM:
2211 case Mips::TLBWR:
2212 case Mips::TLBWR_MM:
2213 case Mips::WAIT: {
2214 break;
2215 }
2216 case Mips::MTHLIP:
2217 case Mips::SHILOV: {
2218 // op: ac
2219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2220 Value |= (op & 0x3) << 11;
2221 // op: rs
2222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2223 Value |= (op & 0x1f) << 21;
2224 break;
2225 }
2226 case Mips::DPAQX_SA_W_PH:
2227 case Mips::DPAQX_S_W_PH:
2228 case Mips::DPAQ_SA_L_W:
2229 case Mips::DPAQ_S_W_PH:
2230 case Mips::DPAU_H_QBL:
2231 case Mips::DPAU_H_QBR:
2232 case Mips::DPAX_W_PH:
2233 case Mips::DPA_W_PH:
2234 case Mips::DPSQX_SA_W_PH:
2235 case Mips::DPSQX_S_W_PH:
2236 case Mips::DPSQ_SA_L_W:
2237 case Mips::DPSQ_S_W_PH:
2238 case Mips::DPSU_H_QBL:
2239 case Mips::DPSU_H_QBR:
2240 case Mips::DPSX_W_PH:
2241 case Mips::DPS_W_PH:
2242 case Mips::MADDU_DSP:
2243 case Mips::MADD_DSP:
2244 case Mips::MAQ_SA_W_PHL:
2245 case Mips::MAQ_SA_W_PHR:
2246 case Mips::MAQ_S_W_PHL:
2247 case Mips::MAQ_S_W_PHR:
2248 case Mips::MSUBU_DSP:
2249 case Mips::MSUB_DSP:
2250 case Mips::MULSAQ_S_W_PH:
2251 case Mips::MULSA_W_PH:
2252 case Mips::MULTU_DSP:
2253 case Mips::MULT_DSP: {
2254 // op: ac
2255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2256 Value |= (op & 0x3) << 11;
2257 // op: rs
2258 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2259 Value |= (op & 0x1f) << 21;
2260 // op: rt
2261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2262 Value |= (op & 0x1f) << 16;
2263 break;
2264 }
2265 case Mips::SHILO: {
2266 // op: ac
2267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2268 Value |= (op & 0x3) << 11;
2269 // op: shift
2270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2271 Value |= (op & 0x3f) << 20;
2272 break;
2273 }
2274 case Mips::CACHEE:
2275 case Mips::CACHE_R6:
2276 case Mips::PREFE:
2277 case Mips::PREF_R6: {
2278 // op: addr
2279 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
2280 Value |= (op & 0x1f0000) << 5;
2281 Value |= (op & 0x1ff) << 7;
2282 // op: hint
2283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2284 Value |= (op & 0x1f) << 16;
2285 break;
2286 }
2287 case Mips::SYNCI: {
2288 // op: addr
2289 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
2290 Value |= (op & 0x1f0000) << 5;
2291 Value |= (op & 0xffff);
2292 break;
2293 }
2294 case Mips::CACHE:
2295 case Mips::PREF: {
2296 // op: addr
2297 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
2298 Value |= (op & 0x1f0000) << 5;
2299 Value |= (op & 0xffff);
2300 // op: hint
2301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2302 Value |= (op & 0x1f) << 16;
2303 break;
2304 }
2305 case Mips::LBE:
2306 case Mips::LBuE:
2307 case Mips::LHE:
2308 case Mips::LHuE:
2309 case Mips::LLE:
2310 case Mips::LWE:
2311 case Mips::LWLE:
2312 case Mips::LWRE:
2313 case Mips::SBE:
2314 case Mips::SHE:
2315 case Mips::SWE:
2316 case Mips::SWLE:
2317 case Mips::SWRE: {
2318 // op: addr
2319 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
2320 Value |= (op & 0x1f0000) << 5;
2321 Value |= (op & 0x1ff) << 7;
2322 // op: rt
2323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2324 Value |= (op & 0x1f) << 16;
2325 break;
2326 }
2327 case Mips::LD_B:
2328 case Mips::ST_B: {
2329 // op: addr
2330 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
2331 Value |= (op & 0x3ff) << 16;
2332 Value |= (op & 0x1f0000) >> 5;
2333 // op: wd
2334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2335 Value |= (op & 0x1f) << 6;
2336 break;
2337 }
2338 case Mips::SCE: {
2339 // op: addr
2340 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
2341 Value |= (op & 0x1f0000) << 5;
2342 Value |= (op & 0x1ff) << 7;
2343 // op: rt
2344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2345 Value |= (op & 0x1f) << 16;
2346 break;
2347 }
2348 case Mips::LD_H:
2349 case Mips::ST_H: {
2350 // op: addr
2351 op = getMemEncoding<1>(MI, OpNo: 1, Fixups, STI);
2352 Value |= (op & 0x3ff) << 16;
2353 Value |= (op & 0x1f0000) >> 5;
2354 // op: wd
2355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2356 Value |= (op & 0x1f) << 6;
2357 break;
2358 }
2359 case Mips::LD_W:
2360 case Mips::ST_W: {
2361 // op: addr
2362 op = getMemEncoding<2>(MI, OpNo: 1, Fixups, STI);
2363 Value |= (op & 0x3ff) << 16;
2364 Value |= (op & 0x1f0000) >> 5;
2365 // op: wd
2366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2367 Value |= (op & 0x1f) << 6;
2368 break;
2369 }
2370 case Mips::LD_D:
2371 case Mips::ST_D: {
2372 // op: addr
2373 op = getMemEncoding<3>(MI, OpNo: 1, Fixups, STI);
2374 Value |= (op & 0x3ff) << 16;
2375 Value |= (op & 0x1f0000) >> 5;
2376 // op: wd
2377 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2378 Value |= (op & 0x1f) << 6;
2379 break;
2380 }
2381 case Mips::CACHE_MM:
2382 case Mips::CACHE_MMR6:
2383 case Mips::PREF_MM:
2384 case Mips::PREF_MMR6: {
2385 // op: addr
2386 op = getMemEncodingMMImm12(MI, OpNo: 0, Fixups, STI);
2387 Value |= (op & 0x1f0000);
2388 Value |= (op & 0xfff);
2389 // op: hint
2390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2391 Value |= (op & 0x1f) << 21;
2392 break;
2393 }
2394 case Mips::SYNCI_MM:
2395 case Mips::SYNCI_MMR6: {
2396 // op: addr
2397 op = getMemEncodingMMImm16(MI, OpNo: 0, Fixups, STI);
2398 Value |= (op & 0x1fffff);
2399 break;
2400 }
2401 case Mips::LBU_MMR6:
2402 case Mips::LB_MMR6: {
2403 // op: addr
2404 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
2405 Value |= (op & 0x1fffff);
2406 // op: rt
2407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2408 Value |= (op & 0x1f) << 21;
2409 break;
2410 }
2411 case Mips::CACHEE_MM:
2412 case Mips::PREFE_MM: {
2413 // op: addr
2414 op = getMemEncodingMMImm9(MI, OpNo: 0, Fixups, STI);
2415 Value |= (op & 0x1f0000);
2416 Value |= (op & 0x1ff);
2417 // op: hint
2418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2419 Value |= (op & 0x1f) << 21;
2420 break;
2421 }
2422 case Mips::HYPCALL: {
2423 // op: code_
2424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2425 Value |= (op & 0x3ff) << 11;
2426 break;
2427 }
2428 case Mips::HYPCALL_MM:
2429 case Mips::SDBBP_MM:
2430 case Mips::SDBBP_MMR6:
2431 case Mips::SYSCALL_MM:
2432 case Mips::WAIT_MM:
2433 case Mips::WAIT_MMR6: {
2434 // op: code_
2435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2436 Value |= (op & 0x3ff) << 16;
2437 break;
2438 }
2439 case Mips::BREAK16_MMR6:
2440 case Mips::SDBBP16_MMR6: {
2441 // op: code_
2442 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2443 Value |= (op & 0xf) << 6;
2444 break;
2445 }
2446 case Mips::BREAK16_MM:
2447 case Mips::SDBBP16_MM: {
2448 // op: code_
2449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2450 Value |= (op & 0xf);
2451 break;
2452 }
2453 case Mips::SIGRIE_MMR6: {
2454 // op: code_
2455 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2456 Value |= (op & 0xffff) << 6;
2457 break;
2458 }
2459 case Mips::SIGRIE: {
2460 // op: code_
2461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2462 Value |= (op & 0xffff);
2463 break;
2464 }
2465 case Mips::SDBBP:
2466 case Mips::SDBBP_R6:
2467 case Mips::SYSCALL: {
2468 // op: code_
2469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2470 Value |= (op & 0xfffff) << 6;
2471 break;
2472 }
2473 case Mips::BREAK:
2474 case Mips::BREAK_MM:
2475 case Mips::BREAK_MMR6: {
2476 // op: code_1
2477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2478 Value |= (op & 0x3ff) << 16;
2479 // op: code_2
2480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2481 Value |= (op & 0x3ff) << 6;
2482 break;
2483 }
2484 case Mips::BC2EQZ:
2485 case Mips::BC2NEZ: {
2486 // op: ct
2487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2488 Value |= (op & 0x1f) << 16;
2489 // op: offset
2490 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
2491 Value |= (op & 0xffff);
2492 break;
2493 }
2494 case Mips::BC1F:
2495 case Mips::BC1FL:
2496 case Mips::BC1T:
2497 case Mips::BC1TL: {
2498 // op: fcc
2499 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2500 Value |= (op & 0x7) << 18;
2501 // op: offset
2502 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
2503 Value |= (op & 0xffff);
2504 break;
2505 }
2506 case Mips::BC1F_MM:
2507 case Mips::BC1T_MM: {
2508 // op: fcc
2509 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2510 Value |= (op & 0x7) << 18;
2511 // op: offset
2512 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
2513 Value |= (op & 0xffff);
2514 break;
2515 }
2516 case Mips::LUXC1_MM:
2517 case Mips::LWXC1_MM: {
2518 // op: fd
2519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2520 Value |= (op & 0x1f) << 11;
2521 // op: base
2522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2523 Value |= (op & 0x1f) << 16;
2524 // op: index
2525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2526 Value |= (op & 0x1f) << 21;
2527 break;
2528 }
2529 case Mips::MOVN_I_D32_MM:
2530 case Mips::MOVN_I_S_MM:
2531 case Mips::MOVZ_I_D32_MM:
2532 case Mips::MOVZ_I_S_MM: {
2533 // op: fd
2534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2535 Value |= (op & 0x1f) << 11;
2536 // op: fs
2537 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2538 Value |= (op & 0x1f) << 16;
2539 // op: rt
2540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2541 Value |= (op & 0x1f) << 21;
2542 break;
2543 }
2544 case Mips::CEIL_W_MM:
2545 case Mips::CEIL_W_S_MM:
2546 case Mips::CVT_D32_S_MM:
2547 case Mips::CVT_D32_W_MM:
2548 case Mips::CVT_D64_S_MM:
2549 case Mips::CVT_D64_W_MM:
2550 case Mips::CVT_L_D64_MM:
2551 case Mips::CVT_L_S_MM:
2552 case Mips::CVT_S_D32_MM:
2553 case Mips::CVT_S_D64_MM:
2554 case Mips::CVT_S_W_MM:
2555 case Mips::CVT_W_D32_MM:
2556 case Mips::CVT_W_D64_MM:
2557 case Mips::CVT_W_S_MM:
2558 case Mips::FABS_D32_MM:
2559 case Mips::FABS_D64_MM:
2560 case Mips::FABS_S_MM:
2561 case Mips::FLOOR_W_MM:
2562 case Mips::FLOOR_W_S_MM:
2563 case Mips::FMOV_D32_MM:
2564 case Mips::FMOV_D64_MM:
2565 case Mips::FMOV_S_MM:
2566 case Mips::FNEG_D32_MM:
2567 case Mips::FNEG_D64_MM:
2568 case Mips::FNEG_S_MM:
2569 case Mips::FSQRT_D32_MM:
2570 case Mips::FSQRT_D64_MM:
2571 case Mips::FSQRT_S_MM:
2572 case Mips::RECIP_D32_MM:
2573 case Mips::RECIP_D64_MM:
2574 case Mips::RECIP_S_MM:
2575 case Mips::ROUND_W_MM:
2576 case Mips::ROUND_W_S_MM:
2577 case Mips::RSQRT_D32_MM:
2578 case Mips::RSQRT_D64_MM:
2579 case Mips::RSQRT_S_MM:
2580 case Mips::TRUNC_W_MM:
2581 case Mips::TRUNC_W_S_MM: {
2582 // op: fd
2583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2584 Value |= (op & 0x1f) << 21;
2585 // op: fs
2586 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2587 Value |= (op & 0x1f) << 16;
2588 break;
2589 }
2590 case Mips::MOVF_D32_MM:
2591 case Mips::MOVF_S_MM:
2592 case Mips::MOVT_D32_MM:
2593 case Mips::MOVT_S_MM: {
2594 // op: fd
2595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2596 Value |= (op & 0x1f) << 21;
2597 // op: fs
2598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2599 Value |= (op & 0x1f) << 16;
2600 // op: fcc
2601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2602 Value |= (op & 0x7) << 13;
2603 break;
2604 }
2605 case Mips::LDXC1:
2606 case Mips::LDXC164:
2607 case Mips::LUXC1:
2608 case Mips::LUXC164:
2609 case Mips::LWXC1: {
2610 // op: fd
2611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2612 Value |= (op & 0x1f) << 6;
2613 // op: base
2614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2615 Value |= (op & 0x1f) << 21;
2616 // op: index
2617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2618 Value |= (op & 0x1f) << 16;
2619 break;
2620 }
2621 case Mips::MADD_D32:
2622 case Mips::MADD_D64:
2623 case Mips::MADD_S:
2624 case Mips::MSUB_D32:
2625 case Mips::MSUB_D64:
2626 case Mips::MSUB_S:
2627 case Mips::NMADD_D32:
2628 case Mips::NMADD_D64:
2629 case Mips::NMADD_S:
2630 case Mips::NMSUB_D32:
2631 case Mips::NMSUB_D64:
2632 case Mips::NMSUB_S: {
2633 // op: fd
2634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2635 Value |= (op & 0x1f) << 6;
2636 // op: fr
2637 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2638 Value |= (op & 0x1f) << 21;
2639 // op: fs
2640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2641 Value |= (op & 0x1f) << 11;
2642 // op: ft
2643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2644 Value |= (op & 0x1f) << 16;
2645 break;
2646 }
2647 case Mips::CEIL_L_D64:
2648 case Mips::CEIL_L_S:
2649 case Mips::CEIL_W_D32:
2650 case Mips::CEIL_W_D64:
2651 case Mips::CEIL_W_S:
2652 case Mips::CVT_D32_S:
2653 case Mips::CVT_D32_W:
2654 case Mips::CVT_D64_L:
2655 case Mips::CVT_D64_S:
2656 case Mips::CVT_D64_W:
2657 case Mips::CVT_L_D64:
2658 case Mips::CVT_L_S:
2659 case Mips::CVT_PS_PW64:
2660 case Mips::CVT_PW_PS64:
2661 case Mips::CVT_S_D32:
2662 case Mips::CVT_S_D64:
2663 case Mips::CVT_S_L:
2664 case Mips::CVT_S_PL64:
2665 case Mips::CVT_S_PU64:
2666 case Mips::CVT_S_W:
2667 case Mips::CVT_W_D32:
2668 case Mips::CVT_W_D64:
2669 case Mips::CVT_W_S:
2670 case Mips::FABS_D32:
2671 case Mips::FABS_D64:
2672 case Mips::FABS_S:
2673 case Mips::FLOOR_L_D64:
2674 case Mips::FLOOR_L_S:
2675 case Mips::FLOOR_W_D32:
2676 case Mips::FLOOR_W_D64:
2677 case Mips::FLOOR_W_S:
2678 case Mips::FMOV_D32:
2679 case Mips::FMOV_D64:
2680 case Mips::FMOV_S:
2681 case Mips::FNEG_D32:
2682 case Mips::FNEG_D64:
2683 case Mips::FNEG_S:
2684 case Mips::FSQRT_D32:
2685 case Mips::FSQRT_D64:
2686 case Mips::FSQRT_S:
2687 case Mips::RECIP_D32:
2688 case Mips::RECIP_D64:
2689 case Mips::RECIP_S:
2690 case Mips::ROUND_L_D64:
2691 case Mips::ROUND_L_S:
2692 case Mips::ROUND_W_D32:
2693 case Mips::ROUND_W_D64:
2694 case Mips::ROUND_W_S:
2695 case Mips::RSQRT_D32:
2696 case Mips::RSQRT_D64:
2697 case Mips::RSQRT_S:
2698 case Mips::TRUNC_L_D64:
2699 case Mips::TRUNC_L_S:
2700 case Mips::TRUNC_W_D32:
2701 case Mips::TRUNC_W_D64:
2702 case Mips::TRUNC_W_S: {
2703 // op: fd
2704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2705 Value |= (op & 0x1f) << 6;
2706 // op: fs
2707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2708 Value |= (op & 0x1f) << 11;
2709 break;
2710 }
2711 case Mips::MOVF_D32:
2712 case Mips::MOVF_D64:
2713 case Mips::MOVF_S:
2714 case Mips::MOVT_D32:
2715 case Mips::MOVT_D64:
2716 case Mips::MOVT_S: {
2717 // op: fd
2718 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2719 Value |= (op & 0x1f) << 6;
2720 // op: fs
2721 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2722 Value |= (op & 0x1f) << 11;
2723 // op: fcc
2724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2725 Value |= (op & 0x7) << 18;
2726 break;
2727 }
2728 case Mips::ADDR_PS64:
2729 case Mips::CMP_EQ_D:
2730 case Mips::CMP_EQ_S:
2731 case Mips::CMP_F_D:
2732 case Mips::CMP_F_S:
2733 case Mips::CMP_LE_D:
2734 case Mips::CMP_LE_S:
2735 case Mips::CMP_LT_D:
2736 case Mips::CMP_LT_S:
2737 case Mips::CMP_SAF_D:
2738 case Mips::CMP_SAF_S:
2739 case Mips::CMP_SEQ_D:
2740 case Mips::CMP_SEQ_S:
2741 case Mips::CMP_SLE_D:
2742 case Mips::CMP_SLE_S:
2743 case Mips::CMP_SLT_D:
2744 case Mips::CMP_SLT_S:
2745 case Mips::CMP_SUEQ_D:
2746 case Mips::CMP_SUEQ_S:
2747 case Mips::CMP_SULE_D:
2748 case Mips::CMP_SULE_S:
2749 case Mips::CMP_SULT_D:
2750 case Mips::CMP_SULT_S:
2751 case Mips::CMP_SUN_D:
2752 case Mips::CMP_SUN_S:
2753 case Mips::CMP_UEQ_D:
2754 case Mips::CMP_UEQ_S:
2755 case Mips::CMP_ULE_D:
2756 case Mips::CMP_ULE_S:
2757 case Mips::CMP_ULT_D:
2758 case Mips::CMP_ULT_S:
2759 case Mips::CMP_UN_D:
2760 case Mips::CMP_UN_S:
2761 case Mips::CVT_PS_S64:
2762 case Mips::FADD_D32:
2763 case Mips::FADD_D64:
2764 case Mips::FADD_PS64:
2765 case Mips::FADD_S:
2766 case Mips::FDIV_D32:
2767 case Mips::FDIV_D64:
2768 case Mips::FDIV_S:
2769 case Mips::FMUL_D32:
2770 case Mips::FMUL_D64:
2771 case Mips::FMUL_PS64:
2772 case Mips::FMUL_S:
2773 case Mips::FSUB_D32:
2774 case Mips::FSUB_D64:
2775 case Mips::FSUB_PS64:
2776 case Mips::FSUB_S:
2777 case Mips::MULR_PS64:
2778 case Mips::PLL_PS64:
2779 case Mips::PLU_PS64:
2780 case Mips::PUL_PS64:
2781 case Mips::PUU_PS64: {
2782 // op: fd
2783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2784 Value |= (op & 0x1f) << 6;
2785 // op: fs
2786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2787 Value |= (op & 0x1f) << 11;
2788 // op: ft
2789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2790 Value |= (op & 0x1f) << 16;
2791 break;
2792 }
2793 case Mips::MOVN_I64_D64:
2794 case Mips::MOVN_I64_S:
2795 case Mips::MOVN_I_D32:
2796 case Mips::MOVN_I_D64:
2797 case Mips::MOVN_I_S:
2798 case Mips::MOVZ_I64_D64:
2799 case Mips::MOVZ_I64_S:
2800 case Mips::MOVZ_I_D32:
2801 case Mips::MOVZ_I_D64:
2802 case Mips::MOVZ_I_S: {
2803 // op: fd
2804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2805 Value |= (op & 0x1f) << 6;
2806 // op: fs
2807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2808 Value |= (op & 0x1f) << 11;
2809 // op: rt
2810 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2811 Value |= (op & 0x1f) << 16;
2812 break;
2813 }
2814 case Mips::SUXC1_MM:
2815 case Mips::SWXC1_MM: {
2816 // op: fs
2817 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2818 Value |= (op & 0x1f) << 11;
2819 // op: base
2820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2821 Value |= (op & 0x1f) << 16;
2822 // op: index
2823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2824 Value |= (op & 0x1f) << 21;
2825 break;
2826 }
2827 case Mips::SDXC1:
2828 case Mips::SDXC164:
2829 case Mips::SUXC1:
2830 case Mips::SUXC164:
2831 case Mips::SWXC1: {
2832 // op: fs
2833 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2834 Value |= (op & 0x1f) << 11;
2835 // op: base
2836 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2837 Value |= (op & 0x1f) << 21;
2838 // op: index
2839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2840 Value |= (op & 0x1f) << 16;
2841 break;
2842 }
2843 case Mips::FCMP_D32:
2844 case Mips::FCMP_D64:
2845 case Mips::FCMP_S32: {
2846 // op: fs
2847 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2848 Value |= (op & 0x1f) << 11;
2849 // op: ft
2850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2851 Value |= (op & 0x1f) << 16;
2852 // op: cond
2853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2854 Value |= (op & 0xf);
2855 break;
2856 }
2857 case Mips::FCMP_D32_MM:
2858 case Mips::FCMP_S32_MM: {
2859 // op: fs
2860 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2861 Value |= (op & 0x1f) << 16;
2862 // op: ft
2863 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2864 Value |= (op & 0x1f) << 21;
2865 // op: cond
2866 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2867 Value |= (op & 0xf) << 6;
2868 break;
2869 }
2870 case Mips::CLASS_D:
2871 case Mips::CLASS_S:
2872 case Mips::RINT_D:
2873 case Mips::RINT_S: {
2874 // op: fs
2875 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2876 Value |= (op & 0x1f) << 11;
2877 // op: fd
2878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2879 Value |= (op & 0x1f) << 6;
2880 break;
2881 }
2882 case Mips::C_EQ_D32:
2883 case Mips::C_EQ_D64:
2884 case Mips::C_EQ_S:
2885 case Mips::C_F_D32:
2886 case Mips::C_F_D64:
2887 case Mips::C_F_S:
2888 case Mips::C_LE_D32:
2889 case Mips::C_LE_D64:
2890 case Mips::C_LE_S:
2891 case Mips::C_LT_D32:
2892 case Mips::C_LT_D64:
2893 case Mips::C_LT_S:
2894 case Mips::C_NGE_D32:
2895 case Mips::C_NGE_D64:
2896 case Mips::C_NGE_S:
2897 case Mips::C_NGLE_D32:
2898 case Mips::C_NGLE_D64:
2899 case Mips::C_NGLE_S:
2900 case Mips::C_NGL_D32:
2901 case Mips::C_NGL_D64:
2902 case Mips::C_NGL_S:
2903 case Mips::C_NGT_D32:
2904 case Mips::C_NGT_D64:
2905 case Mips::C_NGT_S:
2906 case Mips::C_OLE_D32:
2907 case Mips::C_OLE_D64:
2908 case Mips::C_OLE_S:
2909 case Mips::C_OLT_D32:
2910 case Mips::C_OLT_D64:
2911 case Mips::C_OLT_S:
2912 case Mips::C_SEQ_D32:
2913 case Mips::C_SEQ_D64:
2914 case Mips::C_SEQ_S:
2915 case Mips::C_SF_D32:
2916 case Mips::C_SF_D64:
2917 case Mips::C_SF_S:
2918 case Mips::C_UEQ_D32:
2919 case Mips::C_UEQ_D64:
2920 case Mips::C_UEQ_S:
2921 case Mips::C_ULE_D32:
2922 case Mips::C_ULE_D64:
2923 case Mips::C_ULE_S:
2924 case Mips::C_ULT_D32:
2925 case Mips::C_ULT_D64:
2926 case Mips::C_ULT_S:
2927 case Mips::C_UN_D32:
2928 case Mips::C_UN_D64:
2929 case Mips::C_UN_S: {
2930 // op: fs
2931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2932 Value |= (op & 0x1f) << 11;
2933 // op: ft
2934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2935 Value |= (op & 0x1f) << 16;
2936 // op: fcc
2937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2938 Value |= (op & 0x7) << 8;
2939 break;
2940 }
2941 case Mips::C_EQ_D32_MM:
2942 case Mips::C_EQ_D64_MM:
2943 case Mips::C_EQ_S_MM:
2944 case Mips::C_F_D32_MM:
2945 case Mips::C_F_D64_MM:
2946 case Mips::C_F_S_MM:
2947 case Mips::C_LE_D32_MM:
2948 case Mips::C_LE_D64_MM:
2949 case Mips::C_LE_S_MM:
2950 case Mips::C_LT_D32_MM:
2951 case Mips::C_LT_D64_MM:
2952 case Mips::C_LT_S_MM:
2953 case Mips::C_NGE_D32_MM:
2954 case Mips::C_NGE_D64_MM:
2955 case Mips::C_NGE_S_MM:
2956 case Mips::C_NGLE_D32_MM:
2957 case Mips::C_NGLE_D64_MM:
2958 case Mips::C_NGLE_S_MM:
2959 case Mips::C_NGL_D32_MM:
2960 case Mips::C_NGL_D64_MM:
2961 case Mips::C_NGL_S_MM:
2962 case Mips::C_NGT_D32_MM:
2963 case Mips::C_NGT_D64_MM:
2964 case Mips::C_NGT_S_MM:
2965 case Mips::C_OLE_D32_MM:
2966 case Mips::C_OLE_D64_MM:
2967 case Mips::C_OLE_S_MM:
2968 case Mips::C_OLT_D32_MM:
2969 case Mips::C_OLT_D64_MM:
2970 case Mips::C_OLT_S_MM:
2971 case Mips::C_SEQ_D32_MM:
2972 case Mips::C_SEQ_D64_MM:
2973 case Mips::C_SEQ_S_MM:
2974 case Mips::C_SF_D32_MM:
2975 case Mips::C_SF_D64_MM:
2976 case Mips::C_SF_S_MM:
2977 case Mips::C_UEQ_D32_MM:
2978 case Mips::C_UEQ_D64_MM:
2979 case Mips::C_UEQ_S_MM:
2980 case Mips::C_ULE_D32_MM:
2981 case Mips::C_ULE_D64_MM:
2982 case Mips::C_ULE_S_MM:
2983 case Mips::C_ULT_D32_MM:
2984 case Mips::C_ULT_D64_MM:
2985 case Mips::C_ULT_S_MM:
2986 case Mips::C_UN_D32_MM:
2987 case Mips::C_UN_D64_MM:
2988 case Mips::C_UN_S_MM: {
2989 // op: fs
2990 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2991 Value |= (op & 0x1f) << 16;
2992 // op: ft
2993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2994 Value |= (op & 0x1f) << 21;
2995 // op: fcc
2996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2997 Value |= (op & 0x7) << 13;
2998 break;
2999 }
3000 case Mips::CLASS_D_MMR6:
3001 case Mips::CLASS_S_MMR6:
3002 case Mips::RINT_D_MMR6:
3003 case Mips::RINT_S_MMR6: {
3004 // op: fs
3005 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3006 Value |= (op & 0x1f) << 21;
3007 // op: fd
3008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3009 Value |= (op & 0x1f) << 16;
3010 break;
3011 }
3012 case Mips::BC1EQZ:
3013 case Mips::BC1NEZ: {
3014 // op: ft
3015 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3016 Value |= (op & 0x1f) << 16;
3017 // op: offset
3018 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3019 Value |= (op & 0xffff);
3020 break;
3021 }
3022 case Mips::LDC1_D64_MMR6:
3023 case Mips::SDC1_D64_MMR6: {
3024 // op: ft
3025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3026 Value |= (op & 0x1f) << 21;
3027 // op: addr
3028 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
3029 Value |= (op & 0x1fffff);
3030 break;
3031 }
3032 case Mips::CEIL_L_D_MMR6:
3033 case Mips::CEIL_L_S_MMR6:
3034 case Mips::CEIL_W_D_MMR6:
3035 case Mips::CEIL_W_S_MMR6:
3036 case Mips::CVT_D_L_MMR6:
3037 case Mips::CVT_L_D_MMR6:
3038 case Mips::CVT_L_S_MMR6:
3039 case Mips::CVT_S_L_MMR6:
3040 case Mips::CVT_S_W_MMR6:
3041 case Mips::CVT_W_S_MMR6:
3042 case Mips::FLOOR_L_D_MMR6:
3043 case Mips::FLOOR_L_S_MMR6:
3044 case Mips::FLOOR_W_D_MMR6:
3045 case Mips::FLOOR_W_S_MMR6:
3046 case Mips::FMOV_D_MMR6:
3047 case Mips::FMOV_S_MMR6:
3048 case Mips::FNEG_S_MMR6:
3049 case Mips::ROUND_L_D_MMR6:
3050 case Mips::ROUND_L_S_MMR6:
3051 case Mips::ROUND_W_D_MMR6:
3052 case Mips::ROUND_W_S_MMR6:
3053 case Mips::TRUNC_L_D_MMR6:
3054 case Mips::TRUNC_L_S_MMR6:
3055 case Mips::TRUNC_W_D_MMR6:
3056 case Mips::TRUNC_W_S_MMR6: {
3057 // op: ft
3058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3059 Value |= (op & 0x1f) << 21;
3060 // op: fs
3061 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3062 Value |= (op & 0x1f) << 16;
3063 break;
3064 }
3065 case Mips::FADD_S_MMR6:
3066 case Mips::FDIV_S_MMR6:
3067 case Mips::FMUL_S_MMR6:
3068 case Mips::FSUB_S_MMR6: {
3069 // op: ft
3070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3071 Value |= (op & 0x1f) << 21;
3072 // op: fs
3073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3074 Value |= (op & 0x1f) << 16;
3075 // op: fd
3076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3077 Value |= (op & 0x1f) << 11;
3078 break;
3079 }
3080 case Mips::MAXA_D:
3081 case Mips::MAXA_S:
3082 case Mips::MAX_D:
3083 case Mips::MAX_S:
3084 case Mips::MINA_D:
3085 case Mips::MINA_S:
3086 case Mips::MIN_D:
3087 case Mips::MIN_S:
3088 case Mips::SELEQZ_D:
3089 case Mips::SELEQZ_S:
3090 case Mips::SELNEZ_D:
3091 case Mips::SELNEZ_S: {
3092 // op: ft
3093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3094 Value |= (op & 0x1f) << 16;
3095 // op: fs
3096 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3097 Value |= (op & 0x1f) << 11;
3098 // op: fd
3099 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3100 Value |= (op & 0x1f) << 6;
3101 break;
3102 }
3103 case Mips::CMP_AF_D_MMR6:
3104 case Mips::CMP_AF_S_MMR6:
3105 case Mips::CMP_EQ_D_MMR6:
3106 case Mips::CMP_EQ_S_MMR6:
3107 case Mips::CMP_LE_D_MMR6:
3108 case Mips::CMP_LE_S_MMR6:
3109 case Mips::CMP_LT_D_MMR6:
3110 case Mips::CMP_LT_S_MMR6:
3111 case Mips::CMP_SAF_D_MMR6:
3112 case Mips::CMP_SAF_S_MMR6:
3113 case Mips::CMP_SEQ_D_MMR6:
3114 case Mips::CMP_SEQ_S_MMR6:
3115 case Mips::CMP_SLE_D_MMR6:
3116 case Mips::CMP_SLE_S_MMR6:
3117 case Mips::CMP_SLT_D_MMR6:
3118 case Mips::CMP_SLT_S_MMR6:
3119 case Mips::CMP_SUEQ_D_MMR6:
3120 case Mips::CMP_SUEQ_S_MMR6:
3121 case Mips::CMP_SULE_D_MMR6:
3122 case Mips::CMP_SULE_S_MMR6:
3123 case Mips::CMP_SULT_D_MMR6:
3124 case Mips::CMP_SULT_S_MMR6:
3125 case Mips::CMP_SUN_D_MMR6:
3126 case Mips::CMP_SUN_S_MMR6:
3127 case Mips::CMP_UEQ_D_MMR6:
3128 case Mips::CMP_UEQ_S_MMR6:
3129 case Mips::CMP_ULE_D_MMR6:
3130 case Mips::CMP_ULE_S_MMR6:
3131 case Mips::CMP_ULT_D_MMR6:
3132 case Mips::CMP_ULT_S_MMR6:
3133 case Mips::CMP_UN_D_MMR6:
3134 case Mips::CMP_UN_S_MMR6:
3135 case Mips::FADD_D32_MM:
3136 case Mips::FADD_D64_MM:
3137 case Mips::FADD_S_MM:
3138 case Mips::FDIV_D32_MM:
3139 case Mips::FDIV_D64_MM:
3140 case Mips::FDIV_S_MM:
3141 case Mips::FMUL_D32_MM:
3142 case Mips::FMUL_D64_MM:
3143 case Mips::FMUL_S_MM:
3144 case Mips::FSUB_D32_MM:
3145 case Mips::FSUB_D64_MM:
3146 case Mips::FSUB_S_MM:
3147 case Mips::MAXA_D_MMR6:
3148 case Mips::MAXA_S_MMR6:
3149 case Mips::MAX_D_MMR6:
3150 case Mips::MAX_S_MMR6:
3151 case Mips::MINA_D_MMR6:
3152 case Mips::MINA_S_MMR6:
3153 case Mips::MIN_D_MMR6:
3154 case Mips::MIN_S_MMR6:
3155 case Mips::SELEQZ_D_MMR6:
3156 case Mips::SELEQZ_S_MMR6:
3157 case Mips::SELNEZ_D_MMR6:
3158 case Mips::SELNEZ_S_MMR6: {
3159 // op: ft
3160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3161 Value |= (op & 0x1f) << 21;
3162 // op: fs
3163 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3164 Value |= (op & 0x1f) << 16;
3165 // op: fd
3166 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3167 Value |= (op & 0x1f) << 11;
3168 break;
3169 }
3170 case Mips::MADDF_D:
3171 case Mips::MADDF_S:
3172 case Mips::MSUBF_D:
3173 case Mips::MSUBF_S:
3174 case Mips::SEL_D:
3175 case Mips::SEL_S: {
3176 // op: ft
3177 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3178 Value |= (op & 0x1f) << 16;
3179 // op: fs
3180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3181 Value |= (op & 0x1f) << 11;
3182 // op: fd
3183 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3184 Value |= (op & 0x1f) << 6;
3185 break;
3186 }
3187 case Mips::MADDF_D_MMR6:
3188 case Mips::MADDF_S_MMR6:
3189 case Mips::MSUBF_D_MMR6:
3190 case Mips::MSUBF_S_MMR6:
3191 case Mips::SEL_D_MMR6:
3192 case Mips::SEL_S_MMR6: {
3193 // op: ft
3194 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3195 Value |= (op & 0x1f) << 21;
3196 // op: fs
3197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3198 Value |= (op & 0x1f) << 16;
3199 // op: fd
3200 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3201 Value |= (op & 0x1f) << 11;
3202 break;
3203 }
3204 case Mips::MADD_D32_MM:
3205 case Mips::MADD_S_MM:
3206 case Mips::MSUB_D32_MM:
3207 case Mips::MSUB_S_MM:
3208 case Mips::NMADD_D32_MM:
3209 case Mips::NMADD_S_MM:
3210 case Mips::NMSUB_D32_MM:
3211 case Mips::NMSUB_S_MM: {
3212 // op: ft
3213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3214 Value |= (op & 0x1f) << 21;
3215 // op: fs
3216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3217 Value |= (op & 0x1f) << 16;
3218 // op: fd
3219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3220 Value |= (op & 0x1f) << 11;
3221 // op: fr
3222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3223 Value |= (op & 0x1f) << 6;
3224 break;
3225 }
3226 case Mips::ADDVI_B:
3227 case Mips::ADDVI_D:
3228 case Mips::ADDVI_H:
3229 case Mips::ADDVI_W:
3230 case Mips::CEQI_B:
3231 case Mips::CEQI_D:
3232 case Mips::CEQI_H:
3233 case Mips::CEQI_W:
3234 case Mips::CLEI_S_B:
3235 case Mips::CLEI_S_D:
3236 case Mips::CLEI_S_H:
3237 case Mips::CLEI_S_W:
3238 case Mips::CLEI_U_B:
3239 case Mips::CLEI_U_D:
3240 case Mips::CLEI_U_H:
3241 case Mips::CLEI_U_W:
3242 case Mips::CLTI_S_B:
3243 case Mips::CLTI_S_D:
3244 case Mips::CLTI_S_H:
3245 case Mips::CLTI_S_W:
3246 case Mips::CLTI_U_B:
3247 case Mips::CLTI_U_D:
3248 case Mips::CLTI_U_H:
3249 case Mips::CLTI_U_W:
3250 case Mips::MAXI_S_B:
3251 case Mips::MAXI_S_D:
3252 case Mips::MAXI_S_H:
3253 case Mips::MAXI_S_W:
3254 case Mips::MAXI_U_B:
3255 case Mips::MAXI_U_D:
3256 case Mips::MAXI_U_H:
3257 case Mips::MAXI_U_W:
3258 case Mips::MINI_S_B:
3259 case Mips::MINI_S_D:
3260 case Mips::MINI_S_H:
3261 case Mips::MINI_S_W:
3262 case Mips::MINI_U_B:
3263 case Mips::MINI_U_D:
3264 case Mips::MINI_U_H:
3265 case Mips::MINI_U_W:
3266 case Mips::SUBVI_B:
3267 case Mips::SUBVI_D:
3268 case Mips::SUBVI_H:
3269 case Mips::SUBVI_W: {
3270 // op: imm
3271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3272 Value |= (op & 0x1f) << 16;
3273 // op: ws
3274 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3275 Value |= (op & 0x1f) << 11;
3276 // op: wd
3277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3278 Value |= (op & 0x1f) << 6;
3279 break;
3280 }
3281 case Mips::ADDIUSP_MM: {
3282 // op: imm
3283 op = getSImm9AddiuspValue(MI, OpNo: 0, Fixups, STI);
3284 Value |= (op & 0x1ff) << 1;
3285 break;
3286 }
3287 case Mips::JRCADDIUSP_MMR6: {
3288 // op: imm
3289 op = getUImm5Lsl2Encoding(MI, OpNo: 0, Fixups, STI);
3290 Value |= (op & 0x1f) << 5;
3291 break;
3292 }
3293 case Mips::JRADDIUSP: {
3294 // op: imm
3295 op = getUImm5Lsl2Encoding(MI, OpNo: 0, Fixups, STI);
3296 Value |= (op & 0x1f);
3297 break;
3298 }
3299 case Mips::Bimm16: {
3300 // op: imm11
3301 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
3302 Value |= (op & 0x7ff);
3303 break;
3304 }
3305 case Mips::AddiuRxRyOffMemX16: {
3306 // op: imm15
3307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3308 Value |= (op & 0x7f0) << 16;
3309 Value |= (op & 0x7800) << 5;
3310 Value |= (op & 0xf);
3311 // op: rx
3312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3313 Value |= (op & 0x7) << 8;
3314 // op: ry
3315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3316 Value |= (op & 0x7) << 5;
3317 break;
3318 }
3319 case Mips::BimmX16: {
3320 // op: imm16
3321 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
3322 Value |= (op & 0x7e0) << 16;
3323 Value |= (op & 0xf800) << 5;
3324 Value |= (op & 0x1f);
3325 break;
3326 }
3327 case Mips::BeqzRxImmX16:
3328 case Mips::BnezRxImmX16: {
3329 // op: imm16
3330 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3331 Value |= (op & 0x7e0) << 16;
3332 Value |= (op & 0xf800) << 5;
3333 Value |= (op & 0x1f);
3334 // op: rx
3335 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3336 Value |= (op & 0x7) << 8;
3337 break;
3338 }
3339 case Mips::AddiuSpImmX16:
3340 case Mips::BteqzX16:
3341 case Mips::BtnezX16: {
3342 // op: imm16
3343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3344 Value |= (op & 0x7e0) << 16;
3345 Value |= (op & 0xf800) << 5;
3346 Value |= (op & 0x1f);
3347 break;
3348 }
3349 case Mips::AddiuRxImmX16:
3350 case Mips::AddiuRxPcImmX16:
3351 case Mips::CmpiRxImmX16:
3352 case Mips::LiRxImmAlignX16:
3353 case Mips::LiRxImmX16:
3354 case Mips::LwRxPcTcpX16:
3355 case Mips::SltiRxImmX16:
3356 case Mips::SltiuRxImmX16: {
3357 // op: imm16
3358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3359 Value |= (op & 0x7e0) << 16;
3360 Value |= (op & 0xf800) << 5;
3361 Value |= (op & 0x1f);
3362 // op: rx
3363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3364 Value |= (op & 0x7) << 8;
3365 break;
3366 }
3367 case Mips::AddiuRxRxImmX16: {
3368 // op: imm16
3369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3370 Value |= (op & 0x7e0) << 16;
3371 Value |= (op & 0xf800) << 5;
3372 Value |= (op & 0x1f);
3373 // op: rx
3374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3375 Value |= (op & 0x7) << 8;
3376 break;
3377 }
3378 case Mips::LbRxRyOffMemX16:
3379 case Mips::LbuRxRyOffMemX16:
3380 case Mips::LhRxRyOffMemX16:
3381 case Mips::LhuRxRyOffMemX16:
3382 case Mips::LwRxRyOffMemX16:
3383 case Mips::LwRxSpImmX16:
3384 case Mips::SbRxRyOffMemX16:
3385 case Mips::ShRxRyOffMemX16:
3386 case Mips::SwRxRyOffMemX16:
3387 case Mips::SwRxSpImmX16: {
3388 // op: imm16
3389 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3390 Value |= (op & 0x7e0) << 16;
3391 Value |= (op & 0xf800) << 5;
3392 Value |= (op & 0x1f);
3393 // op: rx
3394 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3395 Value |= (op & 0x7) << 8;
3396 // op: ry
3397 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3398 Value |= (op & 0x7) << 5;
3399 break;
3400 }
3401 case Mips::Jal16:
3402 case Mips::JalB16: {
3403 // op: imm26
3404 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3405 Value |= (op & 0x1f0000) << 5;
3406 Value |= (op & 0x3e00000) >> 5;
3407 Value |= (op & 0xffff);
3408 break;
3409 }
3410 case Mips::AddiuSpImm16:
3411 case Mips::Bteqz16:
3412 case Mips::Btnez16: {
3413 // op: imm8
3414 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3415 Value |= (op & 0xff);
3416 break;
3417 }
3418 case Mips::PREFX_MM: {
3419 // op: index
3420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3421 Value |= (op & 0x1f) << 21;
3422 // op: base
3423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3424 Value |= (op & 0x1f) << 16;
3425 // op: hint
3426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3427 Value |= (op & 0x1f) << 11;
3428 break;
3429 }
3430 case Mips::LBUX_MM:
3431 case Mips::LHX_MM:
3432 case Mips::LWX_MM: {
3433 // op: index
3434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3435 Value |= (op & 0x1f) << 21;
3436 // op: base
3437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3438 Value |= (op & 0x1f) << 16;
3439 // op: rd
3440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3441 Value |= (op & 0x1f) << 11;
3442 break;
3443 }
3444 case Mips::COPY_S_D: {
3445 // op: n
3446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3447 Value |= (op & 0x1) << 16;
3448 // op: ws
3449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3450 Value |= (op & 0x1f) << 11;
3451 // op: rd
3452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3453 Value |= (op & 0x1f) << 6;
3454 break;
3455 }
3456 case Mips::SPLATI_D: {
3457 // op: n
3458 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3459 Value |= (op & 0x1) << 16;
3460 // op: ws
3461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3462 Value |= (op & 0x1f) << 11;
3463 // op: wd
3464 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3465 Value |= (op & 0x1f) << 6;
3466 break;
3467 }
3468 case Mips::INSVE_D: {
3469 // op: n
3470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3471 Value |= (op & 0x1) << 16;
3472 // op: ws
3473 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3474 Value |= (op & 0x1f) << 11;
3475 // op: wd
3476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3477 Value |= (op & 0x1f) << 6;
3478 break;
3479 }
3480 case Mips::COPY_S_W:
3481 case Mips::COPY_U_W: {
3482 // op: n
3483 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3484 Value |= (op & 0x3) << 16;
3485 // op: ws
3486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3487 Value |= (op & 0x1f) << 11;
3488 // op: rd
3489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3490 Value |= (op & 0x1f) << 6;
3491 break;
3492 }
3493 case Mips::SPLATI_W: {
3494 // op: n
3495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3496 Value |= (op & 0x3) << 16;
3497 // op: ws
3498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3499 Value |= (op & 0x1f) << 11;
3500 // op: wd
3501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3502 Value |= (op & 0x1f) << 6;
3503 break;
3504 }
3505 case Mips::INSVE_W: {
3506 // op: n
3507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3508 Value |= (op & 0x3) << 16;
3509 // op: ws
3510 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3511 Value |= (op & 0x1f) << 11;
3512 // op: wd
3513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3514 Value |= (op & 0x1f) << 6;
3515 break;
3516 }
3517 case Mips::COPY_S_H:
3518 case Mips::COPY_U_H: {
3519 // op: n
3520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3521 Value |= (op & 0x7) << 16;
3522 // op: ws
3523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3524 Value |= (op & 0x1f) << 11;
3525 // op: rd
3526 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3527 Value |= (op & 0x1f) << 6;
3528 break;
3529 }
3530 case Mips::SPLATI_H: {
3531 // op: n
3532 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3533 Value |= (op & 0x7) << 16;
3534 // op: ws
3535 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3536 Value |= (op & 0x1f) << 11;
3537 // op: wd
3538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3539 Value |= (op & 0x1f) << 6;
3540 break;
3541 }
3542 case Mips::INSVE_H: {
3543 // op: n
3544 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3545 Value |= (op & 0x7) << 16;
3546 // op: ws
3547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3548 Value |= (op & 0x1f) << 11;
3549 // op: wd
3550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3551 Value |= (op & 0x1f) << 6;
3552 break;
3553 }
3554 case Mips::COPY_S_B:
3555 case Mips::COPY_U_B: {
3556 // op: n
3557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3558 Value |= (op & 0xf) << 16;
3559 // op: ws
3560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3561 Value |= (op & 0x1f) << 11;
3562 // op: rd
3563 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3564 Value |= (op & 0x1f) << 6;
3565 break;
3566 }
3567 case Mips::SPLATI_B: {
3568 // op: n
3569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3570 Value |= (op & 0xf) << 16;
3571 // op: ws
3572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3573 Value |= (op & 0x1f) << 11;
3574 // op: wd
3575 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3576 Value |= (op & 0x1f) << 6;
3577 break;
3578 }
3579 case Mips::INSVE_B: {
3580 // op: n
3581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3582 Value |= (op & 0xf) << 16;
3583 // op: ws
3584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3585 Value |= (op & 0x1f) << 11;
3586 // op: wd
3587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3588 Value |= (op & 0x1f) << 6;
3589 break;
3590 }
3591 case Mips::INSERT_D: {
3592 // op: n
3593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3594 Value |= (op & 0x1) << 16;
3595 // op: rs
3596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3597 Value |= (op & 0x1f) << 11;
3598 // op: wd
3599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3600 Value |= (op & 0x1f) << 6;
3601 break;
3602 }
3603 case Mips::SLDI_D: {
3604 // op: n
3605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3606 Value |= (op & 0x1) << 16;
3607 // op: ws
3608 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3609 Value |= (op & 0x1f) << 11;
3610 // op: wd
3611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3612 Value |= (op & 0x1f) << 6;
3613 break;
3614 }
3615 case Mips::INSERT_W: {
3616 // op: n
3617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3618 Value |= (op & 0x3) << 16;
3619 // op: rs
3620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3621 Value |= (op & 0x1f) << 11;
3622 // op: wd
3623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3624 Value |= (op & 0x1f) << 6;
3625 break;
3626 }
3627 case Mips::SLDI_W: {
3628 // op: n
3629 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3630 Value |= (op & 0x3) << 16;
3631 // op: ws
3632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3633 Value |= (op & 0x1f) << 11;
3634 // op: wd
3635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3636 Value |= (op & 0x1f) << 6;
3637 break;
3638 }
3639 case Mips::INSERT_H: {
3640 // op: n
3641 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3642 Value |= (op & 0x7) << 16;
3643 // op: rs
3644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3645 Value |= (op & 0x1f) << 11;
3646 // op: wd
3647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3648 Value |= (op & 0x1f) << 6;
3649 break;
3650 }
3651 case Mips::SLDI_H: {
3652 // op: n
3653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3654 Value |= (op & 0x7) << 16;
3655 // op: ws
3656 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3657 Value |= (op & 0x1f) << 11;
3658 // op: wd
3659 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3660 Value |= (op & 0x1f) << 6;
3661 break;
3662 }
3663 case Mips::INSERT_B: {
3664 // op: n
3665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3666 Value |= (op & 0xf) << 16;
3667 // op: rs
3668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3669 Value |= (op & 0x1f) << 11;
3670 // op: wd
3671 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3672 Value |= (op & 0x1f) << 6;
3673 break;
3674 }
3675 case Mips::SLDI_B: {
3676 // op: n
3677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3678 Value |= (op & 0xf) << 16;
3679 // op: ws
3680 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3681 Value |= (op & 0x1f) << 11;
3682 // op: wd
3683 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3684 Value |= (op & 0x1f) << 6;
3685 break;
3686 }
3687 case Mips::BALC:
3688 case Mips::BC: {
3689 // op: offset
3690 op = getBranchTarget26OpValue(MI, OpNo: 0, Fixups, STI);
3691 Value |= (op & 0x3ffffff);
3692 break;
3693 }
3694 case Mips::BALC_MMR6:
3695 case Mips::BC_MMR6: {
3696 // op: offset
3697 op = getBranchTarget26OpValueMM(MI, OpNo: 0, Fixups, STI);
3698 Value |= (op & 0x3ffffff);
3699 break;
3700 }
3701 case Mips::BAL:
3702 case Mips::BPOSGE32: {
3703 // op: offset
3704 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
3705 Value |= (op & 0xffff);
3706 break;
3707 }
3708 case Mips::BNZ_B:
3709 case Mips::BNZ_D:
3710 case Mips::BNZ_H:
3711 case Mips::BNZ_V:
3712 case Mips::BNZ_W:
3713 case Mips::BZ_B:
3714 case Mips::BZ_D:
3715 case Mips::BZ_H:
3716 case Mips::BZ_V:
3717 case Mips::BZ_W: {
3718 // op: offset
3719 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3720 Value |= (op & 0xffff);
3721 // op: wt
3722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3723 Value |= (op & 0x1f) << 16;
3724 break;
3725 }
3726 case Mips::BPOSGE32C_MMR3: {
3727 // op: offset
3728 op = getBranchTargetOpValue1SImm16(MI, OpNo: 0, Fixups, STI);
3729 Value |= (op & 0xffff);
3730 break;
3731 }
3732 case Mips::BPOSGE32_MM: {
3733 // op: offset
3734 op = getBranchTargetOpValueMM(MI, OpNo: 0, Fixups, STI);
3735 Value |= (op & 0xffff);
3736 break;
3737 }
3738 case Mips::B16_MM:
3739 case Mips::BC16_MMR6: {
3740 // op: offset
3741 op = getBranchTargetOpValueMMPC10(MI, OpNo: 0, Fixups, STI);
3742 Value |= (op & 0x3ff);
3743 break;
3744 }
3745 case Mips::Move32R16: {
3746 // op: r32
3747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3748 Value |= (op & 0x7) << 5;
3749 Value |= (op & 0x18);
3750 // op: rz
3751 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3752 Value |= (op & 0x7);
3753 break;
3754 }
3755 case Mips::MFHI:
3756 case Mips::MFHI64:
3757 case Mips::MFLO:
3758 case Mips::MFLO64: {
3759 // op: rd
3760 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3761 Value |= (op & 0x1f) << 11;
3762 break;
3763 }
3764 case Mips::MFHI_DSP:
3765 case Mips::MFLO_DSP: {
3766 // op: rd
3767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3768 Value |= (op & 0x1f) << 11;
3769 // op: ac
3770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3771 Value |= (op & 0x3) << 21;
3772 break;
3773 }
3774 case Mips::LWXS_MM: {
3775 // op: rd
3776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3777 Value |= (op & 0x1f) << 11;
3778 // op: base
3779 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3780 Value |= (op & 0x1f) << 16;
3781 // op: index
3782 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3783 Value |= (op & 0x1f) << 21;
3784 break;
3785 }
3786 case Mips::LBUX:
3787 case Mips::LHX:
3788 case Mips::LWX: {
3789 // op: rd
3790 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3791 Value |= (op & 0x1f) << 11;
3792 // op: base
3793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3794 Value |= (op & 0x1f) << 21;
3795 // op: index
3796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3797 Value |= (op & 0x1f) << 16;
3798 break;
3799 }
3800 case Mips::REPL_PH:
3801 case Mips::REPL_PH_MM:
3802 case Mips::REPL_QB: {
3803 // op: rd
3804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3805 Value |= (op & 0x1f) << 11;
3806 // op: imm
3807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3808 Value |= (op & 0x3ff) << 16;
3809 break;
3810 }
3811 case Mips::RDDSP: {
3812 // op: rd
3813 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3814 Value |= (op & 0x1f) << 11;
3815 // op: mask
3816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3817 Value |= (op & 0x3ff) << 16;
3818 break;
3819 }
3820 case Mips::ADDQH_PH_MMR2:
3821 case Mips::ADDQH_R_PH_MMR2:
3822 case Mips::ADDQH_R_W_MMR2:
3823 case Mips::ADDQH_W_MMR2:
3824 case Mips::ADDQ_PH_MM:
3825 case Mips::ADDQ_S_PH_MM:
3826 case Mips::ADDQ_S_W_MM:
3827 case Mips::ADDSC_MM:
3828 case Mips::ADDUH_QB_MMR2:
3829 case Mips::ADDUH_R_QB_MMR2:
3830 case Mips::ADDU_PH_MMR2:
3831 case Mips::ADDU_QB_MM:
3832 case Mips::ADDU_S_PH_MMR2:
3833 case Mips::ADDU_S_QB_MM:
3834 case Mips::ADDWC_MM:
3835 case Mips::CMPGDU_EQ_QB_MMR2:
3836 case Mips::CMPGDU_LE_QB_MMR2:
3837 case Mips::CMPGDU_LT_QB_MMR2:
3838 case Mips::MODSUB_MM:
3839 case Mips::MULEQ_S_W_PHL_MM:
3840 case Mips::MULEQ_S_W_PHR_MM:
3841 case Mips::MULEU_S_PH_QBL_MM:
3842 case Mips::MULEU_S_PH_QBR_MM:
3843 case Mips::MULQ_RS_PH_MM:
3844 case Mips::MULQ_RS_W_MMR2:
3845 case Mips::MULQ_S_PH_MMR2:
3846 case Mips::MULQ_S_W_MMR2:
3847 case Mips::MUL_PH_MMR2:
3848 case Mips::MUL_S_PH_MMR2:
3849 case Mips::PACKRL_PH_MM:
3850 case Mips::PICK_PH_MM:
3851 case Mips::PICK_QB_MM:
3852 case Mips::PRECRQU_S_QB_PH_MM:
3853 case Mips::PRECRQ_PH_W_MM:
3854 case Mips::PRECRQ_QB_PH_MM:
3855 case Mips::PRECRQ_RS_PH_W_MM:
3856 case Mips::PRECR_QB_PH_MMR2:
3857 case Mips::SELEQZ_MMR6:
3858 case Mips::SELNEZ_MMR6:
3859 case Mips::SUBQH_PH_MMR2:
3860 case Mips::SUBQH_R_PH_MMR2:
3861 case Mips::SUBQH_R_W_MMR2:
3862 case Mips::SUBQH_W_MMR2:
3863 case Mips::SUBQ_PH_MM:
3864 case Mips::SUBQ_S_PH_MM:
3865 case Mips::SUBQ_S_W_MM:
3866 case Mips::SUBUH_QB_MMR2:
3867 case Mips::SUBUH_R_QB_MMR2:
3868 case Mips::SUBU_PH_MMR2:
3869 case Mips::SUBU_QB_MM:
3870 case Mips::SUBU_S_PH_MMR2:
3871 case Mips::SUBU_S_QB_MM: {
3872 // op: rd
3873 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3874 Value |= (op & 0x1f) << 11;
3875 // op: rs
3876 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3877 Value |= (op & 0x1f) << 16;
3878 // op: rt
3879 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3880 Value |= (op & 0x1f) << 21;
3881 break;
3882 }
3883 case Mips::LSA_MMR6: {
3884 // op: rd
3885 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3886 Value |= (op & 0x1f) << 11;
3887 // op: rs
3888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3889 Value |= (op & 0x1f) << 16;
3890 // op: rt
3891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3892 Value |= (op & 0x1f) << 21;
3893 // op: imm2
3894 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
3895 Value |= (op & 0x3) << 9;
3896 break;
3897 }
3898 case Mips::CLO_R6:
3899 case Mips::CLZ_R6:
3900 case Mips::DCLO_R6:
3901 case Mips::DCLZ_R6:
3902 case Mips::DPOP:
3903 case Mips::JALR:
3904 case Mips::JALR64:
3905 case Mips::JALR_HB:
3906 case Mips::JALR_HB64:
3907 case Mips::POP:
3908 case Mips::RADDU_W_QB: {
3909 // op: rd
3910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3911 Value |= (op & 0x1f) << 11;
3912 // op: rs
3913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3914 Value |= (op & 0x1f) << 21;
3915 break;
3916 }
3917 case Mips::MOVF_I:
3918 case Mips::MOVF_I64:
3919 case Mips::MOVT_I:
3920 case Mips::MOVT_I64: {
3921 // op: rd
3922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3923 Value |= (op & 0x1f) << 11;
3924 // op: rs
3925 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3926 Value |= (op & 0x1f) << 21;
3927 // op: fcc
3928 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3929 Value |= (op & 0x7) << 18;
3930 break;
3931 }
3932 case Mips::ADD:
3933 case Mips::ADDQH_PH:
3934 case Mips::ADDQH_R_PH:
3935 case Mips::ADDQH_R_W:
3936 case Mips::ADDQH_W:
3937 case Mips::ADDQ_PH:
3938 case Mips::ADDQ_S_PH:
3939 case Mips::ADDQ_S_W:
3940 case Mips::ADDSC:
3941 case Mips::ADDUH_QB:
3942 case Mips::ADDUH_R_QB:
3943 case Mips::ADDU_PH:
3944 case Mips::ADDU_QB:
3945 case Mips::ADDU_S_PH:
3946 case Mips::ADDU_S_QB:
3947 case Mips::ADDWC:
3948 case Mips::ADDu:
3949 case Mips::AND:
3950 case Mips::AND64:
3951 case Mips::BADDu:
3952 case Mips::DADD:
3953 case Mips::DADDu:
3954 case Mips::DDIV:
3955 case Mips::DDIVU:
3956 case Mips::DIV:
3957 case Mips::DIVU:
3958 case Mips::DMOD:
3959 case Mips::DMODU:
3960 case Mips::DMUH:
3961 case Mips::DMUHU:
3962 case Mips::DMUL:
3963 case Mips::DMULU:
3964 case Mips::DMUL_R6:
3965 case Mips::DSUB:
3966 case Mips::DSUBu:
3967 case Mips::MOD:
3968 case Mips::MODSUB:
3969 case Mips::MODU:
3970 case Mips::MOVN_I64_I:
3971 case Mips::MOVN_I64_I64:
3972 case Mips::MOVN_I_I:
3973 case Mips::MOVN_I_I64:
3974 case Mips::MOVZ_I64_I:
3975 case Mips::MOVZ_I64_I64:
3976 case Mips::MOVZ_I_I:
3977 case Mips::MOVZ_I_I64:
3978 case Mips::MUH:
3979 case Mips::MUHU:
3980 case Mips::MUL:
3981 case Mips::MULEQ_S_W_PHL:
3982 case Mips::MULEQ_S_W_PHR:
3983 case Mips::MULEU_S_PH_QBL:
3984 case Mips::MULEU_S_PH_QBR:
3985 case Mips::MULQ_RS_PH:
3986 case Mips::MULQ_RS_W:
3987 case Mips::MULQ_S_PH:
3988 case Mips::MULQ_S_W:
3989 case Mips::MULU:
3990 case Mips::MUL_PH:
3991 case Mips::MUL_R6:
3992 case Mips::MUL_S_PH:
3993 case Mips::NOR:
3994 case Mips::NOR64:
3995 case Mips::OR:
3996 case Mips::OR64:
3997 case Mips::SELEQZ:
3998 case Mips::SELEQZ64:
3999 case Mips::SELNEZ:
4000 case Mips::SELNEZ64:
4001 case Mips::SEQ:
4002 case Mips::SLT:
4003 case Mips::SLT64:
4004 case Mips::SLTu:
4005 case Mips::SLTu64:
4006 case Mips::SNE:
4007 case Mips::SUB:
4008 case Mips::SUBQH_PH:
4009 case Mips::SUBQH_R_PH:
4010 case Mips::SUBQH_R_W:
4011 case Mips::SUBQH_W:
4012 case Mips::SUBQ_PH:
4013 case Mips::SUBQ_S_PH:
4014 case Mips::SUBQ_S_W:
4015 case Mips::SUBUH_QB:
4016 case Mips::SUBUH_R_QB:
4017 case Mips::SUBU_PH:
4018 case Mips::SUBU_QB:
4019 case Mips::SUBU_S_PH:
4020 case Mips::SUBU_S_QB:
4021 case Mips::SUBu:
4022 case Mips::V3MULU:
4023 case Mips::VMM0:
4024 case Mips::VMULU:
4025 case Mips::XOR:
4026 case Mips::XOR64: {
4027 // op: rd
4028 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4029 Value |= (op & 0x1f) << 11;
4030 // op: rs
4031 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4032 Value |= (op & 0x1f) << 21;
4033 // op: rt
4034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4035 Value |= (op & 0x1f) << 16;
4036 break;
4037 }
4038 case Mips::ALIGN: {
4039 // op: rd
4040 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4041 Value |= (op & 0x1f) << 11;
4042 // op: rs
4043 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4044 Value |= (op & 0x1f) << 21;
4045 // op: rt
4046 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4047 Value |= (op & 0x1f) << 16;
4048 // op: bp
4049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4050 Value |= (op & 0x3) << 6;
4051 break;
4052 }
4053 case Mips::ALIGN_MMR6: {
4054 // op: rd
4055 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4056 Value |= (op & 0x1f) << 11;
4057 // op: rs
4058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4059 Value |= (op & 0x1f) << 21;
4060 // op: rt
4061 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4062 Value |= (op & 0x1f) << 16;
4063 // op: bp
4064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4065 Value |= (op & 0x3) << 9;
4066 break;
4067 }
4068 case Mips::DALIGN: {
4069 // op: rd
4070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4071 Value |= (op & 0x1f) << 11;
4072 // op: rs
4073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4074 Value |= (op & 0x1f) << 21;
4075 // op: rt
4076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4077 Value |= (op & 0x1f) << 16;
4078 // op: bp
4079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4080 Value |= (op & 0x7) << 6;
4081 break;
4082 }
4083 case Mips::DLSA_R6:
4084 case Mips::LSA_R6: {
4085 // op: rd
4086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4087 Value |= (op & 0x1f) << 11;
4088 // op: rs
4089 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4090 Value |= (op & 0x1f) << 21;
4091 // op: rt
4092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4093 Value |= (op & 0x1f) << 16;
4094 // op: imm2
4095 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
4096 Value |= (op & 0x3) << 6;
4097 break;
4098 }
4099 case Mips::SHLLV_PH_MM:
4100 case Mips::SHLLV_QB_MM:
4101 case Mips::SHLLV_S_PH_MM:
4102 case Mips::SHLLV_S_W_MM:
4103 case Mips::SHRAV_PH_MM:
4104 case Mips::SHRAV_QB_MMR2:
4105 case Mips::SHRAV_R_PH_MM:
4106 case Mips::SHRAV_R_QB_MMR2:
4107 case Mips::SHRAV_R_W_MM:
4108 case Mips::SHRLV_PH_MMR2:
4109 case Mips::SHRLV_QB_MM: {
4110 // op: rd
4111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4112 Value |= (op & 0x1f) << 11;
4113 // op: rs
4114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4115 Value |= (op & 0x1f) << 16;
4116 // op: rt
4117 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4118 Value |= (op & 0x1f) << 21;
4119 break;
4120 }
4121 case Mips::ABSQ_S_PH:
4122 case Mips::ABSQ_S_QB:
4123 case Mips::ABSQ_S_W:
4124 case Mips::BITREV:
4125 case Mips::BITSWAP:
4126 case Mips::DBITSWAP:
4127 case Mips::DSBH:
4128 case Mips::DSHD:
4129 case Mips::DSLL64_32:
4130 case Mips::PRECEQU_PH_QBL:
4131 case Mips::PRECEQU_PH_QBLA:
4132 case Mips::PRECEQU_PH_QBR:
4133 case Mips::PRECEQU_PH_QBRA:
4134 case Mips::PRECEQ_W_PHL:
4135 case Mips::PRECEQ_W_PHR:
4136 case Mips::PRECEU_PH_QBL:
4137 case Mips::PRECEU_PH_QBLA:
4138 case Mips::PRECEU_PH_QBR:
4139 case Mips::PRECEU_PH_QBRA:
4140 case Mips::REPLV_PH:
4141 case Mips::REPLV_QB:
4142 case Mips::SEB:
4143 case Mips::SEB64:
4144 case Mips::SEH:
4145 case Mips::SEH64:
4146 case Mips::SLL64_32:
4147 case Mips::SLL64_64:
4148 case Mips::WSBH: {
4149 // op: rd
4150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4151 Value |= (op & 0x1f) << 11;
4152 // op: rt
4153 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4154 Value |= (op & 0x1f) << 16;
4155 break;
4156 }
4157 case Mips::DROTRV:
4158 case Mips::DSLLV:
4159 case Mips::DSRAV:
4160 case Mips::DSRLV:
4161 case Mips::ROTRV:
4162 case Mips::SLLV:
4163 case Mips::SRAV:
4164 case Mips::SRLV: {
4165 // op: rd
4166 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4167 Value |= (op & 0x1f) << 11;
4168 // op: rt
4169 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4170 Value |= (op & 0x1f) << 16;
4171 // op: rs
4172 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4173 Value |= (op & 0x1f) << 21;
4174 break;
4175 }
4176 case Mips::SHLLV_PH:
4177 case Mips::SHLLV_QB:
4178 case Mips::SHLLV_S_PH:
4179 case Mips::SHLLV_S_W:
4180 case Mips::SHLL_PH:
4181 case Mips::SHLL_QB:
4182 case Mips::SHLL_S_PH:
4183 case Mips::SHLL_S_W:
4184 case Mips::SHRAV_PH:
4185 case Mips::SHRAV_QB:
4186 case Mips::SHRAV_R_PH:
4187 case Mips::SHRAV_R_QB:
4188 case Mips::SHRAV_R_W:
4189 case Mips::SHRA_PH:
4190 case Mips::SHRA_QB:
4191 case Mips::SHRA_R_PH:
4192 case Mips::SHRA_R_QB:
4193 case Mips::SHRA_R_W:
4194 case Mips::SHRLV_PH:
4195 case Mips::SHRLV_QB:
4196 case Mips::SHRL_PH:
4197 case Mips::SHRL_QB: {
4198 // op: rd
4199 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4200 Value |= (op & 0x1f) << 11;
4201 // op: rt
4202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4203 Value |= (op & 0x1f) << 16;
4204 // op: rs_sa
4205 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4206 Value |= (op & 0x1f) << 21;
4207 break;
4208 }
4209 case Mips::DROTR:
4210 case Mips::DROTR32:
4211 case Mips::DSLL:
4212 case Mips::DSLL32:
4213 case Mips::DSRA:
4214 case Mips::DSRA32:
4215 case Mips::DSRL:
4216 case Mips::DSRL32:
4217 case Mips::ROTR:
4218 case Mips::SLL:
4219 case Mips::SRA:
4220 case Mips::SRL: {
4221 // op: rd
4222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4223 Value |= (op & 0x1f) << 11;
4224 // op: rt
4225 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4226 Value |= (op & 0x1f) << 16;
4227 // op: shamt
4228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4229 Value |= (op & 0x1f) << 6;
4230 break;
4231 }
4232 case Mips::ROTRV_MM:
4233 case Mips::SLLV_MM:
4234 case Mips::SRAV_MM:
4235 case Mips::SRLV_MM: {
4236 // op: rd
4237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4238 Value |= (op & 0x1f) << 11;
4239 // op: rt
4240 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4241 Value |= (op & 0x1f) << 21;
4242 // op: rs
4243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4244 Value |= (op & 0x1f) << 16;
4245 break;
4246 }
4247 case Mips::ADDU_MMR6:
4248 case Mips::ADD_MMR6:
4249 case Mips::AND_MMR6:
4250 case Mips::DIVU_MMR6:
4251 case Mips::DIV_MMR6:
4252 case Mips::MODU_MMR6:
4253 case Mips::MOD_MMR6:
4254 case Mips::MUHU_MMR6:
4255 case Mips::MUH_MMR6:
4256 case Mips::MULU_MMR6:
4257 case Mips::MUL_MMR6:
4258 case Mips::NOR_MMR6:
4259 case Mips::OR_MMR6:
4260 case Mips::SUBU_MMR6:
4261 case Mips::SUB_MMR6:
4262 case Mips::XOR_MMR6: {
4263 // op: rd
4264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4265 Value |= (op & 0x1f) << 11;
4266 // op: rt
4267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4268 Value |= (op & 0x1f) << 21;
4269 // op: rs
4270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4271 Value |= (op & 0x1f) << 16;
4272 break;
4273 }
4274 case Mips::MFHI_MM:
4275 case Mips::MFLO_MM: {
4276 // op: rd
4277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4278 Value |= (op & 0x1f) << 16;
4279 break;
4280 }
4281 case Mips::BITSWAP_MMR6: {
4282 // op: rd
4283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4284 Value |= (op & 0x1f) << 16;
4285 // op: rt
4286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4287 Value |= (op & 0x1f) << 21;
4288 break;
4289 }
4290 case Mips::CLO:
4291 case Mips::CLZ:
4292 case Mips::DCLO:
4293 case Mips::DCLZ: {
4294 // op: rd
4295 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4296 Value |= (op & 0x1f) << 16;
4297 Value |= (op & 0x1f) << 11;
4298 // op: rs
4299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4300 Value |= (op & 0x1f) << 21;
4301 break;
4302 }
4303 case Mips::CLO_MM:
4304 case Mips::CLZ_MM: {
4305 // op: rd
4306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4307 Value |= (op & 0x1f) << 21;
4308 // op: rs
4309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4310 Value |= (op & 0x1f) << 16;
4311 break;
4312 }
4313 case Mips::MOVF_I_MM:
4314 case Mips::MOVT_I_MM: {
4315 // op: rd
4316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4317 Value |= (op & 0x1f) << 21;
4318 // op: rs
4319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4320 Value |= (op & 0x1f) << 16;
4321 // op: fcc
4322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4323 Value |= (op & 0x7) << 13;
4324 break;
4325 }
4326 case Mips::SEB_MM:
4327 case Mips::SEH_MM:
4328 case Mips::WSBH_MM: {
4329 // op: rd
4330 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4331 Value |= (op & 0x1f) << 21;
4332 // op: rt
4333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4334 Value |= (op & 0x1f) << 16;
4335 break;
4336 }
4337 case Mips::ROTR_MM:
4338 case Mips::SLL_MM:
4339 case Mips::SLL_MMR6:
4340 case Mips::SRA_MM:
4341 case Mips::SRL_MM: {
4342 // op: rd
4343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4344 Value |= (op & 0x1f) << 21;
4345 // op: rt
4346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4347 Value |= (op & 0x1f) << 16;
4348 // op: shamt
4349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4350 Value |= (op & 0x1f) << 11;
4351 break;
4352 }
4353 case Mips::CFCMSA: {
4354 // op: rd
4355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4356 Value |= (op & 0x1f) << 6;
4357 // op: cs
4358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4359 Value |= (op & 0x1f) << 11;
4360 break;
4361 }
4362 case Mips::MFHI16_MM:
4363 case Mips::MFLO16_MM: {
4364 // op: rd
4365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4366 Value |= (op & 0x1f);
4367 break;
4368 }
4369 case Mips::LI16_MM:
4370 case Mips::LI16_MMR6: {
4371 // op: rd
4372 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4373 Value |= (op & 0x7) << 7;
4374 // op: imm
4375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4376 Value |= (op & 0x7f);
4377 break;
4378 }
4379 case Mips::ADDIUR1SP_MM: {
4380 // op: rd
4381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4382 Value |= (op & 0x7) << 7;
4383 // op: imm
4384 op = getUImm6Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
4385 Value |= (op & 0x3f) << 1;
4386 break;
4387 }
4388 case Mips::ADDIUR2_MM: {
4389 // op: rd
4390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4391 Value |= (op & 0x7) << 7;
4392 // op: rs
4393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4394 Value |= (op & 0x7) << 4;
4395 // op: imm
4396 op = getSImm3Lsa2Value(MI, OpNo: 2, Fixups, STI);
4397 Value |= (op & 0x7) << 1;
4398 break;
4399 }
4400 case Mips::ANDI16_MM:
4401 case Mips::ANDI16_MMR6: {
4402 // op: rd
4403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4404 Value |= (op & 0x7) << 7;
4405 // op: rs
4406 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4407 Value |= (op & 0x7) << 4;
4408 // op: imm
4409 op = getUImm4AndValue(MI, OpNo: 2, Fixups, STI);
4410 Value |= (op & 0xf);
4411 break;
4412 }
4413 case Mips::SLL16_MM:
4414 case Mips::SLL16_MMR6:
4415 case Mips::SRL16_MM:
4416 case Mips::SRL16_MMR6: {
4417 // op: rd
4418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4419 Value |= (op & 0x7) << 7;
4420 // op: rt
4421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4422 Value |= (op & 0x7) << 4;
4423 // op: shamt
4424 op = getUImm3Mod8Encoding(MI, OpNo: 2, Fixups, STI);
4425 Value |= (op & 0x7) << 1;
4426 break;
4427 }
4428 case Mips::ADDU16_MM:
4429 case Mips::SUBU16_MM: {
4430 // op: rd
4431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4432 Value |= (op & 0x7) << 7;
4433 // op: rt
4434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4435 Value |= (op & 0x7) << 4;
4436 // op: rs
4437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4438 Value |= (op & 0x7) << 1;
4439 break;
4440 }
4441 case Mips::ADDIUS5_MM: {
4442 // op: rd
4443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4444 Value |= (op & 0x1f) << 5;
4445 // op: imm
4446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4447 Value |= (op & 0xf) << 1;
4448 break;
4449 }
4450 case Mips::DVP_MMR6:
4451 case Mips::EVP_MMR6:
4452 case Mips::GINVI_MMR6:
4453 case Mips::JR_MM:
4454 case Mips::MTHI_MM:
4455 case Mips::MTLO_MM: {
4456 // op: rs
4457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4458 Value |= (op & 0x1f) << 16;
4459 break;
4460 }
4461 case Mips::MFHI_DSP_MM:
4462 case Mips::MFLO_DSP_MM: {
4463 // op: rs
4464 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4465 Value |= (op & 0x1f) << 16;
4466 // op: ac
4467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4468 Value |= (op & 0x3) << 14;
4469 break;
4470 }
4471 case Mips::TEQI_MM:
4472 case Mips::TGEIU_MM:
4473 case Mips::TGEI_MM:
4474 case Mips::TLTIU_MM:
4475 case Mips::TLTI_MM:
4476 case Mips::TNEI_MM: {
4477 // op: rs
4478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4479 Value |= (op & 0x1f) << 16;
4480 // op: imm16
4481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4482 Value |= (op & 0xffff);
4483 break;
4484 }
4485 case Mips::BEQZC_MM:
4486 case Mips::BGEZALS_MM:
4487 case Mips::BGEZAL_MM:
4488 case Mips::BGEZ_MM:
4489 case Mips::BGTZ_MM:
4490 case Mips::BLEZ_MM:
4491 case Mips::BLTZALS_MM:
4492 case Mips::BLTZAL_MM:
4493 case Mips::BLTZ_MM:
4494 case Mips::BNEZC_MM: {
4495 // op: rs
4496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4497 Value |= (op & 0x1f) << 16;
4498 // op: offset
4499 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
4500 Value |= (op & 0xffff);
4501 break;
4502 }
4503 case Mips::MADDU_MM:
4504 case Mips::MADD_MM:
4505 case Mips::MSUBU_MM:
4506 case Mips::MSUB_MM:
4507 case Mips::MULT_MM:
4508 case Mips::MULTu_MM:
4509 case Mips::SDIV_MM:
4510 case Mips::UDIV_MM: {
4511 // op: rs
4512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4513 Value |= (op & 0x1f) << 16;
4514 // op: rt
4515 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4516 Value |= (op & 0x1f) << 21;
4517 break;
4518 }
4519 case Mips::TEQ_MM:
4520 case Mips::TGEU_MM:
4521 case Mips::TGE_MM:
4522 case Mips::TLTU_MM:
4523 case Mips::TLT_MM:
4524 case Mips::TNE_MM: {
4525 // op: rs
4526 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4527 Value |= (op & 0x1f) << 16;
4528 // op: rt
4529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4530 Value |= (op & 0x1f) << 21;
4531 // op: code_
4532 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4533 Value |= (op & 0xf) << 12;
4534 break;
4535 }
4536 case Mips::BEQ_MM:
4537 case Mips::BNE_MM: {
4538 // op: rs
4539 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4540 Value |= (op & 0x1f) << 16;
4541 // op: rt
4542 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4543 Value |= (op & 0x1f) << 21;
4544 // op: offset
4545 op = getBranchTargetOpValueMM(MI, OpNo: 2, Fixups, STI);
4546 Value |= (op & 0xffff);
4547 break;
4548 }
4549 case Mips::GINVT_MMR6: {
4550 // op: rs
4551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4552 Value |= (op & 0x1f) << 16;
4553 // op: type
4554 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4555 Value |= (op & 0x3) << 9;
4556 break;
4557 }
4558 case Mips::GINVI:
4559 case Mips::JR:
4560 case Mips::JR64:
4561 case Mips::JR_HB:
4562 case Mips::JR_HB64:
4563 case Mips::JR_HB64_R6:
4564 case Mips::JR_HB_R6:
4565 case Mips::MTHI:
4566 case Mips::MTHI64:
4567 case Mips::MTLO:
4568 case Mips::MTLO64:
4569 case Mips::MTM0:
4570 case Mips::MTM1:
4571 case Mips::MTM2:
4572 case Mips::MTP0:
4573 case Mips::MTP1:
4574 case Mips::MTP2: {
4575 // op: rs
4576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4577 Value |= (op & 0x1f) << 21;
4578 break;
4579 }
4580 case Mips::ALUIPC:
4581 case Mips::AUIPC: {
4582 // op: rs
4583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4584 Value |= (op & 0x1f) << 21;
4585 // op: imm
4586 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4587 Value |= (op & 0xffff);
4588 break;
4589 }
4590 case Mips::DAHI:
4591 case Mips::DATI: {
4592 // op: rs
4593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4594 Value |= (op & 0x1f) << 21;
4595 // op: imm
4596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4597 Value |= (op & 0xffff);
4598 break;
4599 }
4600 case Mips::LDPC: {
4601 // op: rs
4602 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4603 Value |= (op & 0x1f) << 21;
4604 // op: imm
4605 op = getSimm18Lsl3Encoding(MI, OpNo: 1, Fixups, STI);
4606 Value |= (op & 0x3ffff);
4607 break;
4608 }
4609 case Mips::ADDIUPC:
4610 case Mips::LWPC:
4611 case Mips::LWUPC: {
4612 // op: rs
4613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4614 Value |= (op & 0x1f) << 21;
4615 // op: imm
4616 op = getSimm19Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
4617 Value |= (op & 0x7ffff);
4618 break;
4619 }
4620 case Mips::TEQI:
4621 case Mips::TGEI:
4622 case Mips::TGEIU:
4623 case Mips::TLTI:
4624 case Mips::TNEI:
4625 case Mips::TTLTIU: {
4626 // op: rs
4627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4628 Value |= (op & 0x1f) << 21;
4629 // op: imm16
4630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4631 Value |= (op & 0xffff);
4632 break;
4633 }
4634 case Mips::WRDSP: {
4635 // op: rs
4636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4637 Value |= (op & 0x1f) << 21;
4638 // op: mask
4639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4640 Value |= (op & 0x3ff) << 11;
4641 break;
4642 }
4643 case Mips::BEQZC:
4644 case Mips::BEQZC64:
4645 case Mips::BNEZC:
4646 case Mips::BNEZC64: {
4647 // op: rs
4648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4649 Value |= (op & 0x1f) << 21;
4650 // op: offset
4651 op = getBranchTarget21OpValue(MI, OpNo: 1, Fixups, STI);
4652 Value |= (op & 0x1fffff);
4653 break;
4654 }
4655 case Mips::BEQZC_MMR6:
4656 case Mips::BNEZC_MMR6: {
4657 // op: rs
4658 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4659 Value |= (op & 0x1f) << 21;
4660 // op: offset
4661 op = getBranchTarget21OpValueMM(MI, OpNo: 1, Fixups, STI);
4662 Value |= (op & 0x1fffff);
4663 break;
4664 }
4665 case Mips::BGEZ:
4666 case Mips::BGEZ64:
4667 case Mips::BGEZAL:
4668 case Mips::BGEZALL:
4669 case Mips::BGEZL:
4670 case Mips::BGTZ:
4671 case Mips::BGTZ64:
4672 case Mips::BGTZL:
4673 case Mips::BLEZ:
4674 case Mips::BLEZ64:
4675 case Mips::BLEZL:
4676 case Mips::BLTZ:
4677 case Mips::BLTZ64:
4678 case Mips::BLTZAL:
4679 case Mips::BLTZALL:
4680 case Mips::BLTZL: {
4681 // op: rs
4682 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4683 Value |= (op & 0x1f) << 21;
4684 // op: offset
4685 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
4686 Value |= (op & 0xffff);
4687 break;
4688 }
4689 case Mips::BBIT0:
4690 case Mips::BBIT032:
4691 case Mips::BBIT1:
4692 case Mips::BBIT132: {
4693 // op: rs
4694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4695 Value |= (op & 0x1f) << 21;
4696 // op: p
4697 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4698 Value |= (op & 0x1f) << 16;
4699 // op: offset
4700 op = getBranchTargetOpValue(MI, OpNo: 2, Fixups, STI);
4701 Value |= (op & 0xffff);
4702 break;
4703 }
4704 case Mips::CMPU_EQ_QB:
4705 case Mips::CMPU_LE_QB:
4706 case Mips::CMPU_LT_QB:
4707 case Mips::CMP_EQ_PH:
4708 case Mips::CMP_LE_PH:
4709 case Mips::CMP_LT_PH:
4710 case Mips::DMULT:
4711 case Mips::DMULTu:
4712 case Mips::DSDIV:
4713 case Mips::DUDIV:
4714 case Mips::MADD:
4715 case Mips::MADDU:
4716 case Mips::MSUB:
4717 case Mips::MSUBU:
4718 case Mips::MULT:
4719 case Mips::MULTu:
4720 case Mips::SDIV:
4721 case Mips::UDIV: {
4722 // op: rs
4723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4724 Value |= (op & 0x1f) << 21;
4725 // op: rt
4726 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4727 Value |= (op & 0x1f) << 16;
4728 break;
4729 }
4730 case Mips::TEQ:
4731 case Mips::TGE:
4732 case Mips::TGEU:
4733 case Mips::TLT:
4734 case Mips::TLTU:
4735 case Mips::TNE: {
4736 // op: rs
4737 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4738 Value |= (op & 0x1f) << 21;
4739 // op: rt
4740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4741 Value |= (op & 0x1f) << 16;
4742 // op: code_
4743 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4744 Value |= (op & 0x3ff) << 6;
4745 break;
4746 }
4747 case Mips::BEQ:
4748 case Mips::BEQ64:
4749 case Mips::BEQC:
4750 case Mips::BEQC64:
4751 case Mips::BEQL:
4752 case Mips::BGEC:
4753 case Mips::BGEC64:
4754 case Mips::BGEUC:
4755 case Mips::BGEUC64:
4756 case Mips::BLTC:
4757 case Mips::BLTC64:
4758 case Mips::BLTUC:
4759 case Mips::BLTUC64:
4760 case Mips::BNE:
4761 case Mips::BNE64:
4762 case Mips::BNEC:
4763 case Mips::BNEC64:
4764 case Mips::BNEL:
4765 case Mips::BNVC:
4766 case Mips::BOVC: {
4767 // op: rs
4768 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4769 Value |= (op & 0x1f) << 21;
4770 // op: rt
4771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4772 Value |= (op & 0x1f) << 16;
4773 // op: offset
4774 op = getBranchTargetOpValue(MI, OpNo: 2, Fixups, STI);
4775 Value |= (op & 0xffff);
4776 break;
4777 }
4778 case Mips::FORK: {
4779 // op: rs
4780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4781 Value |= (op & 0x1f) << 21;
4782 // op: rt
4783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4784 Value |= (op & 0x1f) << 16;
4785 // op: rd
4786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4787 Value |= (op & 0x1f) << 11;
4788 break;
4789 }
4790 case Mips::GINVT: {
4791 // op: rs
4792 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4793 Value |= (op & 0x1f) << 21;
4794 // op: type_
4795 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4796 Value |= (op & 0x3) << 8;
4797 break;
4798 }
4799 case Mips::JALRC16_MMR6:
4800 case Mips::JRC16_MMR6: {
4801 // op: rs
4802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4803 Value |= (op & 0x1f) << 5;
4804 break;
4805 }
4806 case Mips::JALR16_MM:
4807 case Mips::JALRS16_MM:
4808 case Mips::JR16_MM:
4809 case Mips::JRC16_MM: {
4810 // op: rs
4811 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4812 Value |= (op & 0x1f);
4813 break;
4814 }
4815 case Mips::ADDIUPC_MM: {
4816 // op: rs
4817 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4818 Value |= (op & 0x7) << 23;
4819 // op: imm
4820 op = getSimm23Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
4821 Value |= (op & 0x7fffff);
4822 break;
4823 }
4824 case Mips::BEQZ16_MM:
4825 case Mips::BEQZC16_MMR6:
4826 case Mips::BNEZ16_MM:
4827 case Mips::BNEZC16_MMR6: {
4828 // op: rs
4829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4830 Value |= (op & 0x7) << 7;
4831 // op: offset
4832 op = getBranchTarget7OpValueMM(MI, OpNo: 1, Fixups, STI);
4833 Value |= (op & 0x7f);
4834 break;
4835 }
4836 case Mips::CTCMSA: {
4837 // op: rs
4838 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4839 Value |= (op & 0x1f) << 11;
4840 // op: cd
4841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4842 Value |= (op & 0x1f) << 6;
4843 break;
4844 }
4845 case Mips::FILL_B:
4846 case Mips::FILL_D:
4847 case Mips::FILL_H:
4848 case Mips::FILL_W: {
4849 // op: rs
4850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4851 Value |= (op & 0x1f) << 11;
4852 // op: wd
4853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4854 Value |= (op & 0x1f) << 6;
4855 break;
4856 }
4857 case Mips::MTHI_DSP_MM:
4858 case Mips::MTHLIP_MM:
4859 case Mips::MTLO_DSP_MM:
4860 case Mips::SHILOV_MM: {
4861 // op: rs
4862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4863 Value |= (op & 0x1f) << 16;
4864 // op: ac
4865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4866 Value |= (op & 0x3) << 14;
4867 break;
4868 }
4869 case Mips::JALRS_MM:
4870 case Mips::JALR_MM: {
4871 // op: rs
4872 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4873 Value |= (op & 0x1f) << 16;
4874 // op: rd
4875 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4876 Value |= (op & 0x1f) << 21;
4877 break;
4878 }
4879 case Mips::CLO_MMR6: {
4880 // op: rs
4881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4882 Value |= (op & 0x1f) << 16;
4883 // op: rt
4884 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4885 Value |= (op & 0x1f) << 21;
4886 break;
4887 }
4888 case Mips::AUI_MMR6: {
4889 // op: rs
4890 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4891 Value |= (op & 0x1f) << 16;
4892 // op: rt
4893 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4894 Value |= (op & 0x1f) << 21;
4895 // op: imm
4896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4897 Value |= (op & 0xffff);
4898 break;
4899 }
4900 case Mips::ADDi_MM:
4901 case Mips::ADDiu_MM:
4902 case Mips::ANDi_MM:
4903 case Mips::ORi_MM:
4904 case Mips::XORi_MM: {
4905 // op: rs
4906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4907 Value |= (op & 0x1f) << 16;
4908 // op: rt
4909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4910 Value |= (op & 0x1f) << 21;
4911 // op: imm16
4912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4913 Value |= (op & 0xffff);
4914 break;
4915 }
4916 case Mips::MTHI_DSP:
4917 case Mips::MTLO_DSP: {
4918 // op: rs
4919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4920 Value |= (op & 0x1f) << 21;
4921 // op: ac
4922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4923 Value |= (op & 0x3) << 11;
4924 break;
4925 }
4926 case Mips::YIELD: {
4927 // op: rs
4928 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4929 Value |= (op & 0x1f) << 21;
4930 // op: rd
4931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4932 Value |= (op & 0x1f) << 11;
4933 break;
4934 }
4935 case Mips::CLZ_MMR6: {
4936 // op: rs
4937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4938 Value |= (op & 0x1f) << 21;
4939 // op: rt
4940 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4941 Value |= (op & 0x1f) << 11;
4942 break;
4943 }
4944 case Mips::AUI:
4945 case Mips::DAUI: {
4946 // op: rs
4947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4948 Value |= (op & 0x1f) << 21;
4949 // op: rt
4950 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4951 Value |= (op & 0x1f) << 16;
4952 // op: imm
4953 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4954 Value |= (op & 0xffff);
4955 break;
4956 }
4957 case Mips::SEQi:
4958 case Mips::SNEi: {
4959 // op: rs
4960 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4961 Value |= (op & 0x1f) << 21;
4962 // op: rt
4963 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4964 Value |= (op & 0x1f) << 16;
4965 // op: imm10
4966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4967 Value |= (op & 0x3ff) << 6;
4968 break;
4969 }
4970 case Mips::ADDi:
4971 case Mips::ADDiu:
4972 case Mips::ANDi:
4973 case Mips::ANDi64:
4974 case Mips::DADDi:
4975 case Mips::DADDiu:
4976 case Mips::ORi:
4977 case Mips::ORi64:
4978 case Mips::XORi:
4979 case Mips::XORi64: {
4980 // op: rs
4981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4982 Value |= (op & 0x1f) << 21;
4983 // op: rt
4984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4985 Value |= (op & 0x1f) << 16;
4986 // op: imm16
4987 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4988 Value |= (op & 0xffff);
4989 break;
4990 }
4991 case Mips::PRECR_SRA_PH_W:
4992 case Mips::PRECR_SRA_R_PH_W: {
4993 // op: rs
4994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4995 Value |= (op & 0x1f) << 21;
4996 // op: rt
4997 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4998 Value |= (op & 0x1f) << 16;
4999 // op: sa
5000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5001 Value |= (op & 0x1f) << 11;
5002 break;
5003 }
5004 case Mips::CRC32B:
5005 case Mips::CRC32CB:
5006 case Mips::CRC32CD:
5007 case Mips::CRC32CH:
5008 case Mips::CRC32CW:
5009 case Mips::CRC32D:
5010 case Mips::CRC32H:
5011 case Mips::CRC32W: {
5012 // op: rs
5013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5014 Value |= (op & 0x1f) << 21;
5015 // op: rt
5016 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5017 Value |= (op & 0x1f) << 16;
5018 break;
5019 }
5020 case Mips::CMPGDU_EQ_QB:
5021 case Mips::CMPGDU_LE_QB:
5022 case Mips::CMPGDU_LT_QB:
5023 case Mips::CMPGU_EQ_QB:
5024 case Mips::CMPGU_LE_QB:
5025 case Mips::CMPGU_LT_QB:
5026 case Mips::PACKRL_PH:
5027 case Mips::PICK_PH:
5028 case Mips::PICK_QB:
5029 case Mips::PRECRQU_S_QB_PH:
5030 case Mips::PRECRQ_PH_W:
5031 case Mips::PRECRQ_QB_PH:
5032 case Mips::PRECRQ_RS_PH_W:
5033 case Mips::PRECR_QB_PH: {
5034 // op: rs
5035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5036 Value |= (op & 0x1f) << 21;
5037 // op: rt
5038 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5039 Value |= (op & 0x1f) << 16;
5040 // op: rd
5041 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5042 Value |= (op & 0x1f) << 11;
5043 break;
5044 }
5045 case Mips::DLSA:
5046 case Mips::LSA: {
5047 // op: rs
5048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5049 Value |= (op & 0x1f) << 21;
5050 // op: rt
5051 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5052 Value |= (op & 0x1f) << 16;
5053 // op: rd
5054 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5055 Value |= (op & 0x1f) << 11;
5056 // op: sa
5057 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
5058 Value |= (op & 0x3) << 6;
5059 break;
5060 }
5061 case Mips::MOVE16_MM:
5062 case Mips::MOVE16_MMR6: {
5063 // op: rs
5064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5065 Value |= (op & 0x1f);
5066 // op: rd
5067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5068 Value |= (op & 0x1f) << 5;
5069 break;
5070 }
5071 case Mips::ADDU16_MMR6:
5072 case Mips::SUBU16_MMR6: {
5073 // op: rs
5074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5075 Value |= (op & 0x7) << 7;
5076 // op: rt
5077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5078 Value |= (op & 0x7) << 4;
5079 // op: rd
5080 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5081 Value |= (op & 0x7) << 1;
5082 break;
5083 }
5084 case Mips::DI:
5085 case Mips::DI_MM:
5086 case Mips::DI_MMR6:
5087 case Mips::DMT:
5088 case Mips::DVP:
5089 case Mips::DVPE:
5090 case Mips::EI:
5091 case Mips::EI_MM:
5092 case Mips::EI_MMR6:
5093 case Mips::EMT:
5094 case Mips::EVP:
5095 case Mips::EVPE: {
5096 // op: rt
5097 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5098 Value |= (op & 0x1f) << 16;
5099 break;
5100 }
5101 case Mips::EXTP:
5102 case Mips::EXTPDP:
5103 case Mips::EXTPDPV:
5104 case Mips::EXTPV:
5105 case Mips::EXTRV_RS_W:
5106 case Mips::EXTRV_R_W:
5107 case Mips::EXTRV_S_H:
5108 case Mips::EXTRV_W:
5109 case Mips::EXTR_RS_W:
5110 case Mips::EXTR_R_W:
5111 case Mips::EXTR_S_H:
5112 case Mips::EXTR_W: {
5113 // op: rt
5114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5115 Value |= (op & 0x1f) << 16;
5116 // op: ac
5117 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5118 Value |= (op & 0x3) << 11;
5119 // op: shift_rs
5120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5121 Value |= (op & 0x1f) << 21;
5122 break;
5123 }
5124 case Mips::LL64_R6:
5125 case Mips::LLD_R6:
5126 case Mips::LL_R6: {
5127 // op: rt
5128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5129 Value |= (op & 0x1f) << 16;
5130 // op: addr
5131 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
5132 Value |= (op & 0x1f0000) << 5;
5133 Value |= (op & 0x1ff) << 7;
5134 break;
5135 }
5136 case Mips::LB:
5137 case Mips::LB64:
5138 case Mips::LBu:
5139 case Mips::LBu64:
5140 case Mips::LD:
5141 case Mips::LDC1:
5142 case Mips::LDC164:
5143 case Mips::LDC2:
5144 case Mips::LDC3:
5145 case Mips::LDL:
5146 case Mips::LDR:
5147 case Mips::LEA_ADDiu:
5148 case Mips::LEA_ADDiu64:
5149 case Mips::LH:
5150 case Mips::LH64:
5151 case Mips::LHu:
5152 case Mips::LHu64:
5153 case Mips::LL:
5154 case Mips::LL64:
5155 case Mips::LLD:
5156 case Mips::LW:
5157 case Mips::LW64:
5158 case Mips::LWC1:
5159 case Mips::LWC2:
5160 case Mips::LWC3:
5161 case Mips::LWDSP:
5162 case Mips::LWL:
5163 case Mips::LWL64:
5164 case Mips::LWR:
5165 case Mips::LWR64:
5166 case Mips::LWu:
5167 case Mips::SB:
5168 case Mips::SB64:
5169 case Mips::SD:
5170 case Mips::SDC1:
5171 case Mips::SDC164:
5172 case Mips::SDC2:
5173 case Mips::SDC3:
5174 case Mips::SDL:
5175 case Mips::SDR:
5176 case Mips::SH:
5177 case Mips::SH64:
5178 case Mips::SW:
5179 case Mips::SW64:
5180 case Mips::SWC1:
5181 case Mips::SWC2:
5182 case Mips::SWC3:
5183 case Mips::SWDSP:
5184 case Mips::SWL:
5185 case Mips::SWL64:
5186 case Mips::SWR:
5187 case Mips::SWR64: {
5188 // op: rt
5189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5190 Value |= (op & 0x1f) << 16;
5191 // op: addr
5192 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
5193 Value |= (op & 0x1f0000) << 5;
5194 Value |= (op & 0xffff);
5195 break;
5196 }
5197 case Mips::LDC2_R6:
5198 case Mips::LWC2_R6:
5199 case Mips::SDC2_R6:
5200 case Mips::SWC2_R6: {
5201 // op: rt
5202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5203 Value |= (op & 0x1f) << 16;
5204 // op: addr
5205 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
5206 Value |= (op & 0x1f0000) >> 5;
5207 Value |= (op & 0x7ff);
5208 break;
5209 }
5210 case Mips::CFC1:
5211 case Mips::DMFC1:
5212 case Mips::MFC1:
5213 case Mips::MFC1_D64:
5214 case Mips::MFHC1_D32:
5215 case Mips::MFHC1_D64: {
5216 // op: rt
5217 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5218 Value |= (op & 0x1f) << 16;
5219 // op: fs
5220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5221 Value |= (op & 0x1f) << 11;
5222 break;
5223 }
5224 case Mips::DMFC2_OCTEON:
5225 case Mips::DMTC2_OCTEON:
5226 case Mips::LUi:
5227 case Mips::LUi64:
5228 case Mips::LUi_MM: {
5229 // op: rt
5230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5231 Value |= (op & 0x1f) << 16;
5232 // op: imm16
5233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5234 Value |= (op & 0xffff);
5235 break;
5236 }
5237 case Mips::BEQZALC:
5238 case Mips::BGTZALC:
5239 case Mips::BGTZC:
5240 case Mips::BGTZC64:
5241 case Mips::BLEZALC:
5242 case Mips::BLEZC:
5243 case Mips::BLEZC64:
5244 case Mips::BNEZALC: {
5245 // op: rt
5246 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5247 Value |= (op & 0x1f) << 16;
5248 // op: offset
5249 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
5250 Value |= (op & 0xffff);
5251 break;
5252 }
5253 case Mips::BC1EQZC_MMR6:
5254 case Mips::BC1NEZC_MMR6:
5255 case Mips::BC2EQZC_MMR6:
5256 case Mips::BC2NEZC_MMR6: {
5257 // op: rt
5258 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5259 Value |= (op & 0x1f) << 16;
5260 // op: offset
5261 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
5262 Value |= (op & 0xffff);
5263 break;
5264 }
5265 case Mips::JIALC:
5266 case Mips::JIALC64:
5267 case Mips::JIALC_MMR6:
5268 case Mips::JIC:
5269 case Mips::JIC64:
5270 case Mips::JIC_MMR6: {
5271 // op: rt
5272 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5273 Value |= (op & 0x1f) << 16;
5274 // op: offset
5275 op = getJumpOffset16OpValue(MI, OpNo: 1, Fixups, STI);
5276 Value |= (op & 0xffff);
5277 break;
5278 }
5279 case Mips::RDHWR:
5280 case Mips::RDHWR64: {
5281 // op: rt
5282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5283 Value |= (op & 0x1f) << 16;
5284 // op: rd
5285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5286 Value |= (op & 0x1f) << 11;
5287 // op: sel
5288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5289 Value |= (op & 0x7) << 6;
5290 break;
5291 }
5292 case Mips::DMFC0:
5293 case Mips::DMFC2:
5294 case Mips::DMFGC0:
5295 case Mips::MFC0:
5296 case Mips::MFC2:
5297 case Mips::MFGC0:
5298 case Mips::MFHGC0: {
5299 // op: rt
5300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5301 Value |= (op & 0x1f) << 16;
5302 // op: rd
5303 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5304 Value |= (op & 0x1f) << 11;
5305 // op: sel
5306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5307 Value |= (op & 0x7);
5308 break;
5309 }
5310 case Mips::SAA:
5311 case Mips::SAAD: {
5312 // op: rt
5313 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5314 Value |= (op & 0x1f) << 16;
5315 // op: rs
5316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5317 Value |= (op & 0x1f) << 21;
5318 break;
5319 }
5320 case Mips::SLTi:
5321 case Mips::SLTi64:
5322 case Mips::SLTiu:
5323 case Mips::SLTiu64: {
5324 // op: rt
5325 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5326 Value |= (op & 0x1f) << 16;
5327 // op: rs
5328 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5329 Value |= (op & 0x1f) << 21;
5330 // op: imm16
5331 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5332 Value |= (op & 0xffff);
5333 break;
5334 }
5335 case Mips::CINS:
5336 case Mips::CINS32:
5337 case Mips::CINS64_32:
5338 case Mips::CINS_i32:
5339 case Mips::EXTS:
5340 case Mips::EXTS32: {
5341 // op: rt
5342 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5343 Value |= (op & 0x1f) << 16;
5344 // op: rs
5345 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5346 Value |= (op & 0x1f) << 21;
5347 // op: pos
5348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5349 Value |= (op & 0x1f) << 6;
5350 // op: lenm1
5351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5352 Value |= (op & 0x1f) << 11;
5353 break;
5354 }
5355 case Mips::DINS:
5356 case Mips::DINSM:
5357 case Mips::DINSU:
5358 case Mips::INS: {
5359 // op: rt
5360 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5361 Value |= (op & 0x1f) << 16;
5362 // op: rs
5363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5364 Value |= (op & 0x1f) << 21;
5365 // op: pos
5366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5367 Value |= (op & 0x1f) << 6;
5368 // op: size
5369 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
5370 Value |= (op & 0x1f) << 11;
5371 break;
5372 }
5373 case Mips::DEXT:
5374 case Mips::DEXT64_32:
5375 case Mips::DEXTM:
5376 case Mips::DEXTU:
5377 case Mips::EXT: {
5378 // op: rt
5379 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5380 Value |= (op & 0x1f) << 16;
5381 // op: rs
5382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5383 Value |= (op & 0x1f) << 21;
5384 // op: pos
5385 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5386 Value |= (op & 0x1f) << 6;
5387 // op: size
5388 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
5389 Value |= (op & 0x1f) << 11;
5390 break;
5391 }
5392 case Mips::APPEND:
5393 case Mips::BALIGN:
5394 case Mips::PREPEND: {
5395 // op: rt
5396 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5397 Value |= (op & 0x1f) << 16;
5398 // op: rs
5399 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5400 Value |= (op & 0x1f) << 21;
5401 // op: sa
5402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5403 Value |= (op & 0x1f) << 11;
5404 break;
5405 }
5406 case Mips::INSV: {
5407 // op: rt
5408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5409 Value |= (op & 0x1f) << 16;
5410 // op: rs
5411 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5412 Value |= (op & 0x1f) << 21;
5413 break;
5414 }
5415 case Mips::LBE_MM:
5416 case Mips::LBuE_MM:
5417 case Mips::LHE_MM:
5418 case Mips::LHuE_MM:
5419 case Mips::LLE_MM:
5420 case Mips::LWE_MM:
5421 case Mips::SBE_MM:
5422 case Mips::SHE_MM:
5423 case Mips::SWE_MM: {
5424 // op: rt
5425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5426 Value |= (op & 0x1f) << 21;
5427 // op: addr
5428 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
5429 Value |= (op & 0x1f0000);
5430 Value |= (op & 0x1ff);
5431 break;
5432 }
5433 case Mips::LWU_MM: {
5434 // op: rt
5435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5436 Value |= (op & 0x1f) << 21;
5437 // op: addr
5438 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
5439 Value |= (op & 0x1f0000);
5440 Value |= (op & 0xfff);
5441 break;
5442 }
5443 case Mips::LEA_ADDiu_MM:
5444 case Mips::LH_MM:
5445 case Mips::LHu_MM:
5446 case Mips::LWDSP_MM:
5447 case Mips::LW_MM:
5448 case Mips::LW_MMR6:
5449 case Mips::SB_MM:
5450 case Mips::SB_MMR6:
5451 case Mips::SH_MM:
5452 case Mips::SH_MMR6:
5453 case Mips::SWDSP_MM:
5454 case Mips::SW_MM:
5455 case Mips::SW_MMR6: {
5456 // op: rt
5457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5458 Value |= (op & 0x1f) << 21;
5459 // op: addr
5460 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
5461 Value |= (op & 0x1fffff);
5462 break;
5463 }
5464 case Mips::LWP_MM:
5465 case Mips::SWP_MM: {
5466 // op: rt
5467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5468 Value |= (op & 0x1f) << 21;
5469 // op: addr
5470 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
5471 Value |= (op & 0x1f0000);
5472 Value |= (op & 0xfff);
5473 break;
5474 }
5475 case Mips::LDC2_MMR6:
5476 case Mips::LWC2_MMR6:
5477 case Mips::SDC2_MMR6:
5478 case Mips::SWC2_MMR6: {
5479 // op: rt
5480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5481 Value |= (op & 0x1f) << 21;
5482 // op: addr
5483 op = getMemEncodingMMImm11(MI, OpNo: 1, Fixups, STI);
5484 Value |= (op & 0x1f0000);
5485 Value |= (op & 0x7ff);
5486 break;
5487 }
5488 case Mips::LL_MM:
5489 case Mips::LWL_MM:
5490 case Mips::LWR_MM:
5491 case Mips::SWL_MM:
5492 case Mips::SWR_MM: {
5493 // op: rt
5494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5495 Value |= (op & 0x1f) << 21;
5496 // op: addr
5497 op = getMemEncodingMMImm12(MI, OpNo: 1, Fixups, STI);
5498 Value |= (op & 0x1f0000);
5499 Value |= (op & 0xfff);
5500 break;
5501 }
5502 case Mips::LB_MM:
5503 case Mips::LBu_MM:
5504 case Mips::LDC1_MM_D32:
5505 case Mips::LDC1_MM_D64:
5506 case Mips::LWC1_MM:
5507 case Mips::SDC1_MM_D32:
5508 case Mips::SDC1_MM_D64:
5509 case Mips::SWC1_MM: {
5510 // op: rt
5511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5512 Value |= (op & 0x1f) << 21;
5513 // op: addr
5514 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
5515 Value |= (op & 0x1fffff);
5516 break;
5517 }
5518 case Mips::LL_MMR6:
5519 case Mips::LWLE_MM:
5520 case Mips::LWRE_MM:
5521 case Mips::SWLE_MM:
5522 case Mips::SWRE_MM: {
5523 // op: rt
5524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5525 Value |= (op & 0x1f) << 21;
5526 // op: addr
5527 op = getMemEncodingMMImm9(MI, OpNo: 1, Fixups, STI);
5528 Value |= (op & 0x1f0000);
5529 Value |= (op & 0x1ff);
5530 break;
5531 }
5532 case Mips::CFC1_MM:
5533 case Mips::MFC1_MM:
5534 case Mips::MFC1_MMR6:
5535 case Mips::MFHC1_D32_MM:
5536 case Mips::MFHC1_D64_MM: {
5537 // op: rt
5538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5539 Value |= (op & 0x1f) << 21;
5540 // op: fs
5541 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5542 Value |= (op & 0x1f) << 16;
5543 break;
5544 }
5545 case Mips::REPL_QB_MM: {
5546 // op: rt
5547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5548 Value |= (op & 0x1f) << 21;
5549 // op: imm
5550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5551 Value |= (op & 0xff) << 13;
5552 break;
5553 }
5554 case Mips::ALUIPC_MMR6:
5555 case Mips::AUIPC_MMR6: {
5556 // op: rt
5557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5558 Value |= (op & 0x1f) << 21;
5559 // op: imm
5560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5561 Value |= (op & 0xffff);
5562 break;
5563 }
5564 case Mips::EXTPDP_MM:
5565 case Mips::EXTP_MM:
5566 case Mips::EXTR_RS_W_MM:
5567 case Mips::EXTR_R_W_MM:
5568 case Mips::EXTR_S_H_MM:
5569 case Mips::EXTR_W_MM: {
5570 // op: rt
5571 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5572 Value |= (op & 0x1f) << 21;
5573 // op: imm
5574 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5575 Value |= (op & 0x1f) << 16;
5576 // op: ac
5577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5578 Value |= (op & 0x3) << 14;
5579 break;
5580 }
5581 case Mips::ADDIUPC_MMR6:
5582 case Mips::LWPC_MMR6: {
5583 // op: rt
5584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5585 Value |= (op & 0x1f) << 21;
5586 // op: imm
5587 op = getSimm19Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
5588 Value |= (op & 0x7ffff);
5589 break;
5590 }
5591 case Mips::LUI_MMR6: {
5592 // op: rt
5593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5594 Value |= (op & 0x1f) << 21;
5595 // op: imm16
5596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5597 Value |= (op & 0xffff);
5598 break;
5599 }
5600 case Mips::CFC2_MM:
5601 case Mips::MFC2_MMR6:
5602 case Mips::MFHC2_MMR6: {
5603 // op: rt
5604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5605 Value |= (op & 0x1f) << 21;
5606 // op: impl
5607 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5608 Value |= (op & 0x1f) << 16;
5609 break;
5610 }
5611 case Mips::RDDSP_MM:
5612 case Mips::WRDSP_MM: {
5613 // op: rt
5614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5615 Value |= (op & 0x1f) << 21;
5616 // op: mask
5617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5618 Value |= (op & 0x7f) << 14;
5619 break;
5620 }
5621 case Mips::BGTZC_MMR6:
5622 case Mips::BLEZC_MMR6: {
5623 // op: rt
5624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5625 Value |= (op & 0x1f) << 21;
5626 // op: offset
5627 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 1, Fixups, STI);
5628 Value |= (op & 0xffff);
5629 break;
5630 }
5631 case Mips::BEQZALC_MMR6:
5632 case Mips::BGTZALC_MMR6:
5633 case Mips::BLEZALC_MMR6:
5634 case Mips::BNEZALC_MMR6: {
5635 // op: rt
5636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5637 Value |= (op & 0x1f) << 21;
5638 // op: offset
5639 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
5640 Value |= (op & 0xffff);
5641 break;
5642 }
5643 case Mips::RDHWR_MM:
5644 case Mips::RDPGPR_MMR6: {
5645 // op: rt
5646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5647 Value |= (op & 0x1f) << 21;
5648 // op: rd
5649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5650 Value |= (op & 0x1f) << 16;
5651 break;
5652 }
5653 case Mips::ABSQ_S_PH_MM:
5654 case Mips::ABSQ_S_QB_MMR2:
5655 case Mips::ABSQ_S_W_MM:
5656 case Mips::BITREV_MM:
5657 case Mips::JALRC_HB_MMR6:
5658 case Mips::JALRC_MMR6:
5659 case Mips::PRECEQU_PH_QBLA_MM:
5660 case Mips::PRECEQU_PH_QBL_MM:
5661 case Mips::PRECEQU_PH_QBRA_MM:
5662 case Mips::PRECEQU_PH_QBR_MM:
5663 case Mips::PRECEQ_W_PHL_MM:
5664 case Mips::PRECEQ_W_PHR_MM:
5665 case Mips::PRECEU_PH_QBLA_MM:
5666 case Mips::PRECEU_PH_QBL_MM:
5667 case Mips::PRECEU_PH_QBRA_MM:
5668 case Mips::PRECEU_PH_QBR_MM:
5669 case Mips::RADDU_W_QB_MM:
5670 case Mips::REPLV_PH_MM:
5671 case Mips::REPLV_QB_MM:
5672 case Mips::WRPGPR_MMR6:
5673 case Mips::WSBH_MMR6: {
5674 // op: rt
5675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5676 Value |= (op & 0x1f) << 21;
5677 // op: rs
5678 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5679 Value |= (op & 0x1f) << 16;
5680 break;
5681 }
5682 case Mips::BALIGN_MMR2: {
5683 // op: rt
5684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5685 Value |= (op & 0x1f) << 21;
5686 // op: rs
5687 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5688 Value |= (op & 0x1f) << 16;
5689 // op: bp
5690 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5691 Value |= (op & 0x3) << 14;
5692 break;
5693 }
5694 case Mips::ADDIU_MMR6:
5695 case Mips::ANDI_MMR6:
5696 case Mips::ORI_MMR6:
5697 case Mips::SLTi_MM:
5698 case Mips::SLTiu_MM:
5699 case Mips::XORI_MMR6: {
5700 // op: rt
5701 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5702 Value |= (op & 0x1f) << 21;
5703 // op: rs
5704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5705 Value |= (op & 0x1f) << 16;
5706 // op: imm16
5707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5708 Value |= (op & 0xffff);
5709 break;
5710 }
5711 case Mips::BNVC_MMR6:
5712 case Mips::BOVC_MMR6: {
5713 // op: rt
5714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5715 Value |= (op & 0x1f) << 21;
5716 // op: rs
5717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5718 Value |= (op & 0x1f) << 16;
5719 // op: offset
5720 op = getBranchTargetOpValueMMR6(MI, OpNo: 2, Fixups, STI);
5721 Value |= (op & 0xffff);
5722 break;
5723 }
5724 case Mips::INS_MM: {
5725 // op: rt
5726 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5727 Value |= (op & 0x1f) << 21;
5728 // op: rs
5729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5730 Value |= (op & 0x1f) << 16;
5731 // op: pos
5732 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5733 Value |= (op & 0x1f) << 6;
5734 // op: size
5735 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
5736 Value |= (op & 0x1f) << 11;
5737 break;
5738 }
5739 case Mips::EXT_MM: {
5740 // op: rt
5741 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5742 Value |= (op & 0x1f) << 21;
5743 // op: rs
5744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5745 Value |= (op & 0x1f) << 16;
5746 // op: pos
5747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5748 Value |= (op & 0x1f) << 6;
5749 // op: size
5750 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
5751 Value |= (op & 0x1f) << 11;
5752 break;
5753 }
5754 case Mips::APPEND_MMR2:
5755 case Mips::PRECR_SRA_PH_W_MMR2:
5756 case Mips::PRECR_SRA_R_PH_W_MMR2:
5757 case Mips::PREPEND_MMR2:
5758 case Mips::SHLL_S_W_MM:
5759 case Mips::SHRA_R_W_MM: {
5760 // op: rt
5761 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5762 Value |= (op & 0x1f) << 21;
5763 // op: rs
5764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5765 Value |= (op & 0x1f) << 16;
5766 // op: sa
5767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5768 Value |= (op & 0x1f) << 11;
5769 break;
5770 }
5771 case Mips::SHLL_QB_MM:
5772 case Mips::SHRA_QB_MMR2:
5773 case Mips::SHRA_R_QB_MMR2:
5774 case Mips::SHRL_QB_MM: {
5775 // op: rt
5776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5777 Value |= (op & 0x1f) << 21;
5778 // op: rs
5779 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5780 Value |= (op & 0x1f) << 16;
5781 // op: sa
5782 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5783 Value |= (op & 0x7) << 13;
5784 break;
5785 }
5786 case Mips::SHLL_PH_MM:
5787 case Mips::SHLL_S_PH_MM:
5788 case Mips::SHRA_PH_MM:
5789 case Mips::SHRA_R_PH_MM:
5790 case Mips::SHRL_PH_MMR2: {
5791 // op: rt
5792 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5793 Value |= (op & 0x1f) << 21;
5794 // op: rs
5795 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5796 Value |= (op & 0x1f) << 16;
5797 // op: sa
5798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5799 Value |= (op & 0xf) << 12;
5800 break;
5801 }
5802 case Mips::MFC0_MMR6:
5803 case Mips::MFGC0_MM:
5804 case Mips::MFHC0_MMR6:
5805 case Mips::MFHGC0_MM:
5806 case Mips::RDHWR_MMR6: {
5807 // op: rt
5808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5809 Value |= (op & 0x1f) << 21;
5810 // op: rs
5811 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5812 Value |= (op & 0x1f) << 16;
5813 // op: sel
5814 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5815 Value |= (op & 0x7) << 11;
5816 break;
5817 }
5818 case Mips::INS_MMR6: {
5819 // op: rt
5820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5821 Value |= (op & 0x1f) << 21;
5822 // op: rs
5823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5824 Value |= (op & 0x1f) << 16;
5825 // op: size
5826 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
5827 Value |= (op & 0x1f) << 11;
5828 // op: pos
5829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5830 Value |= (op & 0x1f) << 6;
5831 break;
5832 }
5833 case Mips::EXT_MMR6: {
5834 // op: rt
5835 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5836 Value |= (op & 0x1f) << 21;
5837 // op: rs
5838 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5839 Value |= (op & 0x1f) << 16;
5840 // op: size
5841 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
5842 Value |= (op & 0x1f) << 11;
5843 // op: pos
5844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5845 Value |= (op & 0x1f) << 6;
5846 break;
5847 }
5848 case Mips::INSV_MM: {
5849 // op: rt
5850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5851 Value |= (op & 0x1f) << 21;
5852 // op: rs
5853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5854 Value |= (op & 0x1f) << 16;
5855 break;
5856 }
5857 case Mips::EXTPDPV_MM:
5858 case Mips::EXTPV_MM:
5859 case Mips::EXTRV_RS_W_MM:
5860 case Mips::EXTRV_R_W_MM:
5861 case Mips::EXTRV_S_H_MM:
5862 case Mips::EXTRV_W_MM: {
5863 // op: rt
5864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5865 Value |= (op & 0x1f) << 21;
5866 // op: rs
5867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5868 Value |= (op & 0x1f) << 16;
5869 // op: ac
5870 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5871 Value |= (op & 0x3) << 14;
5872 break;
5873 }
5874 case Mips::BGEZALC:
5875 case Mips::BGEZC:
5876 case Mips::BGEZC64:
5877 case Mips::BLTZALC:
5878 case Mips::BLTZC:
5879 case Mips::BLTZC64: {
5880 // op: rt
5881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5882 Value |= (op & 0x1f) << 21;
5883 Value |= (op & 0x1f) << 16;
5884 // op: offset
5885 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
5886 Value |= (op & 0xffff);
5887 break;
5888 }
5889 case Mips::BGEZC_MMR6:
5890 case Mips::BLTZC_MMR6: {
5891 // op: rt
5892 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5893 Value |= (op & 0x1f) << 21;
5894 Value |= (op & 0x1f) << 16;
5895 // op: offset
5896 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 1, Fixups, STI);
5897 Value |= (op & 0xffff);
5898 break;
5899 }
5900 case Mips::BGEZALC_MMR6:
5901 case Mips::BLTZALC_MMR6: {
5902 // op: rt
5903 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5904 Value |= (op & 0x1f) << 21;
5905 Value |= (op & 0x1f) << 16;
5906 // op: offset
5907 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
5908 Value |= (op & 0xffff);
5909 break;
5910 }
5911 case Mips::LWSP_MM:
5912 case Mips::SWSP_MM:
5913 case Mips::SWSP_MMR6: {
5914 // op: rt
5915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5916 Value |= (op & 0x1f) << 5;
5917 // op: offset
5918 op = getMemEncodingMMSPImm5Lsl2(MI, OpNo: 1, Fixups, STI);
5919 Value |= (op & 0x1f);
5920 break;
5921 }
5922 case Mips::NOT16_MM: {
5923 // op: rt
5924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5925 Value |= (op & 0x7) << 3;
5926 // op: rs
5927 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5928 Value |= (op & 0x7);
5929 break;
5930 }
5931 case Mips::LBU16_MM:
5932 case Mips::SB16_MM:
5933 case Mips::SB16_MMR6: {
5934 // op: rt
5935 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5936 Value |= (op & 0x7) << 7;
5937 // op: addr
5938 op = getMemEncodingMMImm4(MI, OpNo: 1, Fixups, STI);
5939 Value |= (op & 0x7f);
5940 break;
5941 }
5942 case Mips::LHU16_MM:
5943 case Mips::SH16_MM:
5944 case Mips::SH16_MMR6: {
5945 // op: rt
5946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5947 Value |= (op & 0x7) << 7;
5948 // op: addr
5949 op = getMemEncodingMMImm4Lsl1(MI, OpNo: 1, Fixups, STI);
5950 Value |= (op & 0x7f);
5951 break;
5952 }
5953 case Mips::LW16_MM:
5954 case Mips::SW16_MM:
5955 case Mips::SW16_MMR6: {
5956 // op: rt
5957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5958 Value |= (op & 0x7) << 7;
5959 // op: addr
5960 op = getMemEncodingMMImm4Lsl2(MI, OpNo: 1, Fixups, STI);
5961 Value |= (op & 0x7f);
5962 break;
5963 }
5964 case Mips::LWGP_MM: {
5965 // op: rt
5966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5967 Value |= (op & 0x7) << 7;
5968 // op: offset
5969 op = getMemEncodingMMGPImm7Lsl2(MI, OpNo: 1, Fixups, STI);
5970 Value |= (op & 0x7f);
5971 break;
5972 }
5973 case Mips::NOT16_MMR6: {
5974 // op: rt
5975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5976 Value |= (op & 0x7) << 7;
5977 // op: rs
5978 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5979 Value |= (op & 0x7) << 4;
5980 break;
5981 }
5982 case Mips::SC64_R6:
5983 case Mips::SCD_R6:
5984 case Mips::SC_R6: {
5985 // op: rt
5986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5987 Value |= (op & 0x1f) << 16;
5988 // op: addr
5989 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
5990 Value |= (op & 0x1f0000) << 5;
5991 Value |= (op & 0x1ff) << 7;
5992 break;
5993 }
5994 case Mips::SC:
5995 case Mips::SC64:
5996 case Mips::SCD: {
5997 // op: rt
5998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5999 Value |= (op & 0x1f) << 16;
6000 // op: addr
6001 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
6002 Value |= (op & 0x1f0000) << 5;
6003 Value |= (op & 0xffff);
6004 break;
6005 }
6006 case Mips::CTC1:
6007 case Mips::DMTC1:
6008 case Mips::MTC1:
6009 case Mips::MTC1_D64: {
6010 // op: rt
6011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6012 Value |= (op & 0x1f) << 16;
6013 // op: fs
6014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6015 Value |= (op & 0x1f) << 11;
6016 break;
6017 }
6018 case Mips::DMTC0:
6019 case Mips::DMTC2:
6020 case Mips::DMTGC0:
6021 case Mips::MTC0:
6022 case Mips::MTC2:
6023 case Mips::MTGC0:
6024 case Mips::MTHGC0: {
6025 // op: rt
6026 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6027 Value |= (op & 0x1f) << 16;
6028 // op: rd
6029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6030 Value |= (op & 0x1f) << 11;
6031 // op: sel
6032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6033 Value |= (op & 0x7);
6034 break;
6035 }
6036 case Mips::MFTR:
6037 case Mips::MTTR: {
6038 // op: rt
6039 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6040 Value |= (op & 0x1f) << 16;
6041 // op: rd
6042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6043 Value |= (op & 0x1f) << 11;
6044 // op: u
6045 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6046 Value |= (op & 0x1) << 5;
6047 // op: h
6048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6049 Value |= (op & 0x1) << 4;
6050 // op: sel
6051 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6052 Value |= (op & 0x7);
6053 break;
6054 }
6055 case Mips::SCE_MM: {
6056 // op: rt
6057 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6058 Value |= (op & 0x1f) << 21;
6059 // op: addr
6060 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
6061 Value |= (op & 0x1f0000);
6062 Value |= (op & 0x1ff);
6063 break;
6064 }
6065 case Mips::SC_MM: {
6066 // op: rt
6067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6068 Value |= (op & 0x1f) << 21;
6069 // op: addr
6070 op = getMemEncodingMMImm12(MI, OpNo: 2, Fixups, STI);
6071 Value |= (op & 0x1f0000);
6072 Value |= (op & 0xfff);
6073 break;
6074 }
6075 case Mips::SC_MMR6: {
6076 // op: rt
6077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6078 Value |= (op & 0x1f) << 21;
6079 // op: addr
6080 op = getMemEncodingMMImm9(MI, OpNo: 2, Fixups, STI);
6081 Value |= (op & 0x1f0000);
6082 Value |= (op & 0x1ff);
6083 break;
6084 }
6085 case Mips::CTC1_MM:
6086 case Mips::MTC1_D64_MM:
6087 case Mips::MTC1_MM:
6088 case Mips::MTC1_MMR6: {
6089 // op: rt
6090 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6091 Value |= (op & 0x1f) << 21;
6092 // op: fs
6093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6094 Value |= (op & 0x1f) << 16;
6095 break;
6096 }
6097 case Mips::CTC2_MM:
6098 case Mips::MTC2_MMR6:
6099 case Mips::MTHC2_MMR6: {
6100 // op: rt
6101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6102 Value |= (op & 0x1f) << 21;
6103 // op: impl
6104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6105 Value |= (op & 0x1f) << 16;
6106 break;
6107 }
6108 case Mips::CMPU_EQ_QB_MM:
6109 case Mips::CMPU_LE_QB_MM:
6110 case Mips::CMPU_LT_QB_MM:
6111 case Mips::CMP_EQ_PH_MM:
6112 case Mips::CMP_LE_PH_MM:
6113 case Mips::CMP_LT_PH_MM: {
6114 // op: rt
6115 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6116 Value |= (op & 0x1f) << 21;
6117 // op: rs
6118 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6119 Value |= (op & 0x1f) << 16;
6120 break;
6121 }
6122 case Mips::BEQC_MMR6:
6123 case Mips::BGEC_MMR6:
6124 case Mips::BGEUC_MMR6:
6125 case Mips::BLTC_MMR6:
6126 case Mips::BLTUC_MMR6:
6127 case Mips::BNEC_MMR6: {
6128 // op: rt
6129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6130 Value |= (op & 0x1f) << 21;
6131 // op: rs
6132 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6133 Value |= (op & 0x1f) << 16;
6134 // op: offset
6135 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 2, Fixups, STI);
6136 Value |= (op & 0xffff);
6137 break;
6138 }
6139 case Mips::MTC0_MMR6:
6140 case Mips::MTGC0_MM:
6141 case Mips::MTHC0_MMR6:
6142 case Mips::MTHGC0_MM: {
6143 // op: rt
6144 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6145 Value |= (op & 0x1f) << 21;
6146 // op: rs
6147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6148 Value |= (op & 0x1f) << 16;
6149 // op: sel
6150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6151 Value |= (op & 0x7) << 11;
6152 break;
6153 }
6154 case Mips::MTHC1_D32:
6155 case Mips::MTHC1_D64: {
6156 // op: rt
6157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6158 Value |= (op & 0x1f) << 16;
6159 // op: fs
6160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6161 Value |= (op & 0x1f) << 11;
6162 break;
6163 }
6164 case Mips::SPLAT_B:
6165 case Mips::SPLAT_D:
6166 case Mips::SPLAT_H:
6167 case Mips::SPLAT_W: {
6168 // op: rt
6169 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6170 Value |= (op & 0x1f) << 16;
6171 // op: ws
6172 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6173 Value |= (op & 0x1f) << 11;
6174 // op: wd
6175 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6176 Value |= (op & 0x1f) << 6;
6177 break;
6178 }
6179 case Mips::MTHC1_D32_MM:
6180 case Mips::MTHC1_D64_MM: {
6181 // op: rt
6182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6183 Value |= (op & 0x1f) << 21;
6184 // op: fs
6185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6186 Value |= (op & 0x1f) << 16;
6187 break;
6188 }
6189 case Mips::DPAQX_SA_W_PH_MMR2:
6190 case Mips::DPAQX_S_W_PH_MMR2:
6191 case Mips::DPAQ_SA_L_W_MM:
6192 case Mips::DPAQ_S_W_PH_MM:
6193 case Mips::DPAU_H_QBL_MM:
6194 case Mips::DPAU_H_QBR_MM:
6195 case Mips::DPAX_W_PH_MMR2:
6196 case Mips::DPA_W_PH_MMR2:
6197 case Mips::DPSQX_SA_W_PH_MMR2:
6198 case Mips::DPSQX_S_W_PH_MMR2:
6199 case Mips::DPSQ_SA_L_W_MM:
6200 case Mips::DPSQ_S_W_PH_MM:
6201 case Mips::DPSU_H_QBL_MM:
6202 case Mips::DPSU_H_QBR_MM:
6203 case Mips::DPSX_W_PH_MMR2:
6204 case Mips::DPS_W_PH_MMR2:
6205 case Mips::MADDU_DSP_MM:
6206 case Mips::MADD_DSP_MM:
6207 case Mips::MAQ_SA_W_PHL_MM:
6208 case Mips::MAQ_SA_W_PHR_MM:
6209 case Mips::MAQ_S_W_PHL_MM:
6210 case Mips::MAQ_S_W_PHR_MM:
6211 case Mips::MSUBU_DSP_MM:
6212 case Mips::MSUB_DSP_MM:
6213 case Mips::MULSAQ_S_W_PH_MM:
6214 case Mips::MULSA_W_PH_MMR2:
6215 case Mips::MULTU_DSP_MM:
6216 case Mips::MULT_DSP_MM: {
6217 // op: rt
6218 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6219 Value |= (op & 0x1f) << 21;
6220 // op: rs
6221 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6222 Value |= (op & 0x1f) << 16;
6223 // op: ac
6224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6225 Value |= (op & 0x3) << 14;
6226 break;
6227 }
6228 case Mips::ADD_MM:
6229 case Mips::ADDu_MM:
6230 case Mips::AND_MM:
6231 case Mips::CMPGU_EQ_QB_MM:
6232 case Mips::CMPGU_LE_QB_MM:
6233 case Mips::CMPGU_LT_QB_MM:
6234 case Mips::MOVN_I_MM:
6235 case Mips::MOVZ_I_MM:
6236 case Mips::MUL_MM:
6237 case Mips::NOR_MM:
6238 case Mips::OR_MM:
6239 case Mips::SLT_MM:
6240 case Mips::SLTu_MM:
6241 case Mips::SUB_MM:
6242 case Mips::SUBu_MM:
6243 case Mips::XOR_MM: {
6244 // op: rt
6245 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6246 Value |= (op & 0x1f) << 21;
6247 // op: rs
6248 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6249 Value |= (op & 0x1f) << 16;
6250 // op: rd
6251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6252 Value |= (op & 0x1f) << 11;
6253 break;
6254 }
6255 case Mips::AND16_MM:
6256 case Mips::OR16_MM:
6257 case Mips::XOR16_MM: {
6258 // op: rt
6259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6260 Value |= (op & 0x7) << 3;
6261 // op: rs
6262 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6263 Value |= (op & 0x7);
6264 break;
6265 }
6266 case Mips::AND16_MMR6:
6267 case Mips::OR16_MMR6:
6268 case Mips::XOR16_MMR6: {
6269 // op: rt
6270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6271 Value |= (op & 0x7) << 7;
6272 // op: rs
6273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6274 Value |= (op & 0x7) << 4;
6275 break;
6276 }
6277 case Mips::SLD_B:
6278 case Mips::SLD_D:
6279 case Mips::SLD_H:
6280 case Mips::SLD_W: {
6281 // op: rt
6282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6283 Value |= (op & 0x1f) << 16;
6284 // op: ws
6285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6286 Value |= (op & 0x1f) << 11;
6287 // op: wd
6288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6289 Value |= (op & 0x1f) << 6;
6290 break;
6291 }
6292 case Mips::MOVEP_MMR6: {
6293 // op: rt
6294 op = getMovePRegSingleOpValue(MI, OpNo: 3, Fixups, STI);
6295 Value |= (op & 0x7) << 4;
6296 // op: rs
6297 op = getMovePRegSingleOpValue(MI, OpNo: 2, Fixups, STI);
6298 Value |= (op & 0x4) << 1;
6299 Value |= (op & 0x3);
6300 break;
6301 }
6302 case Mips::MOVEP_MM: {
6303 // op: rt
6304 op = getMovePRegSingleOpValue(MI, OpNo: 3, Fixups, STI);
6305 Value |= (op & 0x7) << 4;
6306 // op: rs
6307 op = getMovePRegSingleOpValue(MI, OpNo: 2, Fixups, STI);
6308 Value |= (op & 0x7) << 1;
6309 break;
6310 }
6311 case Mips::LWM32_MM:
6312 case Mips::SWM32_MM: {
6313 // op: rt
6314 op = getRegisterListOpValue(MI, OpNo: 0, Fixups, STI);
6315 Value |= (op & 0x1f) << 21;
6316 // op: addr
6317 op = getMemEncodingMMImm12(MI, OpNo: 1, Fixups, STI);
6318 Value |= (op & 0x1f0000);
6319 Value |= (op & 0xfff);
6320 break;
6321 }
6322 case Mips::LWM16_MM:
6323 case Mips::SWM16_MM: {
6324 // op: rt
6325 op = getRegisterListOpValue16(MI, OpNo: 0, Fixups, STI);
6326 Value |= (op & 0x3) << 4;
6327 // op: addr
6328 op = getMemEncodingMMImm4sp(MI, OpNo: 1, Fixups, STI);
6329 Value |= (op & 0xf);
6330 break;
6331 }
6332 case Mips::LWM16_MMR6:
6333 case Mips::SWM16_MMR6: {
6334 // op: rt
6335 op = getRegisterListOpValue16(MI, OpNo: 0, Fixups, STI);
6336 Value |= (op & 0x3) << 8;
6337 // op: addr
6338 op = getMemEncodingMMImm4sp(MI, OpNo: 1, Fixups, STI);
6339 Value |= (op & 0xf) << 4;
6340 break;
6341 }
6342 case Mips::JrcRx16:
6343 case Mips::JumpLinkReg16:
6344 case Mips::Mfhi16:
6345 case Mips::Mflo16:
6346 case Mips::SebRx16:
6347 case Mips::SehRx16: {
6348 // op: rx
6349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6350 Value |= (op & 0x7) << 8;
6351 break;
6352 }
6353 case Mips::BeqzRxImm16:
6354 case Mips::BnezRxImm16: {
6355 // op: rx
6356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6357 Value |= (op & 0x7) << 8;
6358 // op: imm8
6359 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
6360 Value |= (op & 0xff);
6361 break;
6362 }
6363 case Mips::CmpiRxImm16:
6364 case Mips::LiRxImm16:
6365 case Mips::LwRxPcTcp16:
6366 case Mips::SltiRxImm16:
6367 case Mips::SltiuRxImm16: {
6368 // op: rx
6369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6370 Value |= (op & 0x7) << 8;
6371 // op: imm8
6372 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6373 Value |= (op & 0xff);
6374 break;
6375 }
6376 case Mips::AddiuRxRxImm16: {
6377 // op: rx
6378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6379 Value |= (op & 0x7) << 8;
6380 // op: imm8
6381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6382 Value |= (op & 0xff);
6383 break;
6384 }
6385 case Mips::CmpRxRy16:
6386 case Mips::DivRxRy16:
6387 case Mips::DivuRxRy16:
6388 case Mips::NegRxRy16:
6389 case Mips::NotRxRy16:
6390 case Mips::SltRxRy16:
6391 case Mips::SltuRxRy16: {
6392 // op: rx
6393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6394 Value |= (op & 0x7) << 8;
6395 // op: ry
6396 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6397 Value |= (op & 0x7) << 5;
6398 break;
6399 }
6400 case Mips::AndRxRxRy16:
6401 case Mips::OrRxRxRy16:
6402 case Mips::SllvRxRy16:
6403 case Mips::SravRxRy16:
6404 case Mips::SrlvRxRy16:
6405 case Mips::XorRxRxRy16: {
6406 // op: rx
6407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6408 Value |= (op & 0x7) << 8;
6409 // op: ry
6410 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6411 Value |= (op & 0x7) << 5;
6412 break;
6413 }
6414 case Mips::AdduRxRyRz16:
6415 case Mips::SubuRxRyRz16: {
6416 // op: rx
6417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6418 Value |= (op & 0x7) << 8;
6419 // op: ry
6420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6421 Value |= (op & 0x7) << 5;
6422 // op: rz
6423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6424 Value |= (op & 0x7) << 2;
6425 break;
6426 }
6427 case Mips::MoveR3216: {
6428 // op: ry
6429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6430 Value |= (op & 0xf) << 4;
6431 // op: r32
6432 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6433 Value |= (op & 0xf);
6434 break;
6435 }
6436 case Mips::LDI_B:
6437 case Mips::LDI_D:
6438 case Mips::LDI_H:
6439 case Mips::LDI_W: {
6440 // op: s10
6441 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6442 Value |= (op & 0x3ff) << 11;
6443 // op: wd
6444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6445 Value |= (op & 0x1f) << 6;
6446 break;
6447 }
6448 case Mips::SllX16:
6449 case Mips::SraX16:
6450 case Mips::SrlX16: {
6451 // op: sa6
6452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6453 Value |= (op & 0x1f) << 22;
6454 Value |= (op & 0x20) << 16;
6455 // op: rx
6456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6457 Value |= (op & 0x7) << 8;
6458 // op: ry
6459 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6460 Value |= (op & 0x7) << 5;
6461 break;
6462 }
6463 case Mips::SHILO_MM: {
6464 // op: shift
6465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6466 Value |= (op & 0x3f) << 16;
6467 // op: ac
6468 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6469 Value |= (op & 0x3) << 14;
6470 break;
6471 }
6472 case Mips::SYNC_MM:
6473 case Mips::SYNC_MMR6: {
6474 // op: stype
6475 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6476 Value |= (op & 0x1f) << 16;
6477 break;
6478 }
6479 case Mips::SYNC: {
6480 // op: stype
6481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6482 Value |= (op & 0x1f) << 6;
6483 break;
6484 }
6485 case Mips::J:
6486 case Mips::JAL:
6487 case Mips::JALX:
6488 case Mips::JALX_MM: {
6489 // op: target
6490 op = getJumpTargetOpValue(MI, OpNo: 0, Fixups, STI);
6491 Value |= (op & 0x3ffffff);
6492 break;
6493 }
6494 case Mips::JALS_MM:
6495 case Mips::JAL_MM:
6496 case Mips::J_MM: {
6497 // op: target
6498 op = getJumpTargetOpValueMM(MI, OpNo: 0, Fixups, STI);
6499 Value |= (op & 0x3ffffff);
6500 break;
6501 }
6502 case Mips::ANDI_B:
6503 case Mips::NORI_B:
6504 case Mips::ORI_B:
6505 case Mips::SHF_B:
6506 case Mips::SHF_H:
6507 case Mips::SHF_W:
6508 case Mips::XORI_B: {
6509 // op: u8
6510 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6511 Value |= (op & 0xff) << 16;
6512 // op: ws
6513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6514 Value |= (op & 0x1f) << 11;
6515 // op: wd
6516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6517 Value |= (op & 0x1f) << 6;
6518 break;
6519 }
6520 case Mips::BMNZI_B:
6521 case Mips::BMZI_B:
6522 case Mips::BSELI_B: {
6523 // op: u8
6524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6525 Value |= (op & 0xff) << 16;
6526 // op: ws
6527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6528 Value |= (op & 0x1f) << 11;
6529 // op: wd
6530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6531 Value |= (op & 0x1f) << 6;
6532 break;
6533 }
6534 case Mips::FCLASS_D:
6535 case Mips::FCLASS_W:
6536 case Mips::FEXUPL_D:
6537 case Mips::FEXUPL_W:
6538 case Mips::FEXUPR_D:
6539 case Mips::FEXUPR_W:
6540 case Mips::FFINT_S_D:
6541 case Mips::FFINT_S_W:
6542 case Mips::FFINT_U_D:
6543 case Mips::FFINT_U_W:
6544 case Mips::FFQL_D:
6545 case Mips::FFQL_W:
6546 case Mips::FFQR_D:
6547 case Mips::FFQR_W:
6548 case Mips::FLOG2_D:
6549 case Mips::FLOG2_W:
6550 case Mips::FRCP_D:
6551 case Mips::FRCP_W:
6552 case Mips::FRINT_D:
6553 case Mips::FRINT_W:
6554 case Mips::FRSQRT_D:
6555 case Mips::FRSQRT_W:
6556 case Mips::FSQRT_D:
6557 case Mips::FSQRT_W:
6558 case Mips::FTINT_S_D:
6559 case Mips::FTINT_S_W:
6560 case Mips::FTINT_U_D:
6561 case Mips::FTINT_U_W:
6562 case Mips::FTRUNC_S_D:
6563 case Mips::FTRUNC_S_W:
6564 case Mips::FTRUNC_U_D:
6565 case Mips::FTRUNC_U_W:
6566 case Mips::MOVE_V:
6567 case Mips::NLOC_B:
6568 case Mips::NLOC_D:
6569 case Mips::NLOC_H:
6570 case Mips::NLOC_W:
6571 case Mips::NLZC_B:
6572 case Mips::NLZC_D:
6573 case Mips::NLZC_H:
6574 case Mips::NLZC_W:
6575 case Mips::PCNT_B:
6576 case Mips::PCNT_D:
6577 case Mips::PCNT_H:
6578 case Mips::PCNT_W: {
6579 // op: ws
6580 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6581 Value |= (op & 0x1f) << 11;
6582 // op: wd
6583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6584 Value |= (op & 0x1f) << 6;
6585 break;
6586 }
6587 case Mips::BCLRI_W:
6588 case Mips::BNEGI_W:
6589 case Mips::BSETI_W:
6590 case Mips::SAT_S_W:
6591 case Mips::SAT_U_W:
6592 case Mips::SLLI_W:
6593 case Mips::SRAI_W:
6594 case Mips::SRARI_W:
6595 case Mips::SRLI_W:
6596 case Mips::SRLRI_W: {
6597 // op: ws
6598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6599 Value |= (op & 0x1f) << 11;
6600 // op: wd
6601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6602 Value |= (op & 0x1f) << 6;
6603 // op: m
6604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6605 Value |= (op & 0x1f) << 16;
6606 break;
6607 }
6608 case Mips::BCLRI_D:
6609 case Mips::BNEGI_D:
6610 case Mips::BSETI_D:
6611 case Mips::SAT_S_D:
6612 case Mips::SAT_U_D:
6613 case Mips::SLLI_D:
6614 case Mips::SRAI_D:
6615 case Mips::SRARI_D:
6616 case Mips::SRLI_D:
6617 case Mips::SRLRI_D: {
6618 // op: ws
6619 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6620 Value |= (op & 0x1f) << 11;
6621 // op: wd
6622 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6623 Value |= (op & 0x1f) << 6;
6624 // op: m
6625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6626 Value |= (op & 0x3f) << 16;
6627 break;
6628 }
6629 case Mips::BCLRI_B:
6630 case Mips::BNEGI_B:
6631 case Mips::BSETI_B:
6632 case Mips::SAT_S_B:
6633 case Mips::SAT_U_B:
6634 case Mips::SLLI_B:
6635 case Mips::SRAI_B:
6636 case Mips::SRARI_B:
6637 case Mips::SRLI_B:
6638 case Mips::SRLRI_B: {
6639 // op: ws
6640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6641 Value |= (op & 0x1f) << 11;
6642 // op: wd
6643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6644 Value |= (op & 0x1f) << 6;
6645 // op: m
6646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6647 Value |= (op & 0x7) << 16;
6648 break;
6649 }
6650 case Mips::BCLRI_H:
6651 case Mips::BNEGI_H:
6652 case Mips::BSETI_H:
6653 case Mips::SAT_S_H:
6654 case Mips::SAT_U_H:
6655 case Mips::SLLI_H:
6656 case Mips::SRAI_H:
6657 case Mips::SRARI_H:
6658 case Mips::SRLI_H:
6659 case Mips::SRLRI_H: {
6660 // op: ws
6661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6662 Value |= (op & 0x1f) << 11;
6663 // op: wd
6664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6665 Value |= (op & 0x1f) << 6;
6666 // op: m
6667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6668 Value |= (op & 0xf) << 16;
6669 break;
6670 }
6671 case Mips::BINSLI_W:
6672 case Mips::BINSRI_W: {
6673 // op: ws
6674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6675 Value |= (op & 0x1f) << 11;
6676 // op: wd
6677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6678 Value |= (op & 0x1f) << 6;
6679 // op: m
6680 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6681 Value |= (op & 0x1f) << 16;
6682 break;
6683 }
6684 case Mips::BINSLI_D:
6685 case Mips::BINSRI_D: {
6686 // op: ws
6687 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6688 Value |= (op & 0x1f) << 11;
6689 // op: wd
6690 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6691 Value |= (op & 0x1f) << 6;
6692 // op: m
6693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6694 Value |= (op & 0x3f) << 16;
6695 break;
6696 }
6697 case Mips::BINSLI_B:
6698 case Mips::BINSRI_B: {
6699 // op: ws
6700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6701 Value |= (op & 0x1f) << 11;
6702 // op: wd
6703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6704 Value |= (op & 0x1f) << 6;
6705 // op: m
6706 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6707 Value |= (op & 0x7) << 16;
6708 break;
6709 }
6710 case Mips::BINSLI_H:
6711 case Mips::BINSRI_H: {
6712 // op: ws
6713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6714 Value |= (op & 0x1f) << 11;
6715 // op: wd
6716 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6717 Value |= (op & 0x1f) << 6;
6718 // op: m
6719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6720 Value |= (op & 0xf) << 16;
6721 break;
6722 }
6723 case Mips::ADDS_A_B:
6724 case Mips::ADDS_A_D:
6725 case Mips::ADDS_A_H:
6726 case Mips::ADDS_A_W:
6727 case Mips::ADDS_S_B:
6728 case Mips::ADDS_S_D:
6729 case Mips::ADDS_S_H:
6730 case Mips::ADDS_S_W:
6731 case Mips::ADDS_U_B:
6732 case Mips::ADDS_U_D:
6733 case Mips::ADDS_U_H:
6734 case Mips::ADDS_U_W:
6735 case Mips::ADDV_B:
6736 case Mips::ADDV_D:
6737 case Mips::ADDV_H:
6738 case Mips::ADDV_W:
6739 case Mips::ADD_A_B:
6740 case Mips::ADD_A_D:
6741 case Mips::ADD_A_H:
6742 case Mips::ADD_A_W:
6743 case Mips::AND_V:
6744 case Mips::ASUB_S_B:
6745 case Mips::ASUB_S_D:
6746 case Mips::ASUB_S_H:
6747 case Mips::ASUB_S_W:
6748 case Mips::ASUB_U_B:
6749 case Mips::ASUB_U_D:
6750 case Mips::ASUB_U_H:
6751 case Mips::ASUB_U_W:
6752 case Mips::AVER_S_B:
6753 case Mips::AVER_S_D:
6754 case Mips::AVER_S_H:
6755 case Mips::AVER_S_W:
6756 case Mips::AVER_U_B:
6757 case Mips::AVER_U_D:
6758 case Mips::AVER_U_H:
6759 case Mips::AVER_U_W:
6760 case Mips::AVE_S_B:
6761 case Mips::AVE_S_D:
6762 case Mips::AVE_S_H:
6763 case Mips::AVE_S_W:
6764 case Mips::AVE_U_B:
6765 case Mips::AVE_U_D:
6766 case Mips::AVE_U_H:
6767 case Mips::AVE_U_W:
6768 case Mips::BCLR_B:
6769 case Mips::BCLR_D:
6770 case Mips::BCLR_H:
6771 case Mips::BCLR_W:
6772 case Mips::BNEG_B:
6773 case Mips::BNEG_D:
6774 case Mips::BNEG_H:
6775 case Mips::BNEG_W:
6776 case Mips::BSET_B:
6777 case Mips::BSET_D:
6778 case Mips::BSET_H:
6779 case Mips::BSET_W:
6780 case Mips::CEQ_B:
6781 case Mips::CEQ_D:
6782 case Mips::CEQ_H:
6783 case Mips::CEQ_W:
6784 case Mips::CLE_S_B:
6785 case Mips::CLE_S_D:
6786 case Mips::CLE_S_H:
6787 case Mips::CLE_S_W:
6788 case Mips::CLE_U_B:
6789 case Mips::CLE_U_D:
6790 case Mips::CLE_U_H:
6791 case Mips::CLE_U_W:
6792 case Mips::CLT_S_B:
6793 case Mips::CLT_S_D:
6794 case Mips::CLT_S_H:
6795 case Mips::CLT_S_W:
6796 case Mips::CLT_U_B:
6797 case Mips::CLT_U_D:
6798 case Mips::CLT_U_H:
6799 case Mips::CLT_U_W:
6800 case Mips::DIV_S_B:
6801 case Mips::DIV_S_D:
6802 case Mips::DIV_S_H:
6803 case Mips::DIV_S_W:
6804 case Mips::DIV_U_B:
6805 case Mips::DIV_U_D:
6806 case Mips::DIV_U_H:
6807 case Mips::DIV_U_W:
6808 case Mips::DOTP_S_D:
6809 case Mips::DOTP_S_H:
6810 case Mips::DOTP_S_W:
6811 case Mips::DOTP_U_D:
6812 case Mips::DOTP_U_H:
6813 case Mips::DOTP_U_W:
6814 case Mips::FADD_D:
6815 case Mips::FADD_W:
6816 case Mips::FCAF_D:
6817 case Mips::FCAF_W:
6818 case Mips::FCEQ_D:
6819 case Mips::FCEQ_W:
6820 case Mips::FCLE_D:
6821 case Mips::FCLE_W:
6822 case Mips::FCLT_D:
6823 case Mips::FCLT_W:
6824 case Mips::FCNE_D:
6825 case Mips::FCNE_W:
6826 case Mips::FCOR_D:
6827 case Mips::FCOR_W:
6828 case Mips::FCUEQ_D:
6829 case Mips::FCUEQ_W:
6830 case Mips::FCULE_D:
6831 case Mips::FCULE_W:
6832 case Mips::FCULT_D:
6833 case Mips::FCULT_W:
6834 case Mips::FCUNE_D:
6835 case Mips::FCUNE_W:
6836 case Mips::FCUN_D:
6837 case Mips::FCUN_W:
6838 case Mips::FDIV_D:
6839 case Mips::FDIV_W:
6840 case Mips::FEXDO_H:
6841 case Mips::FEXDO_W:
6842 case Mips::FEXP2_D:
6843 case Mips::FEXP2_W:
6844 case Mips::FMAX_A_D:
6845 case Mips::FMAX_A_W:
6846 case Mips::FMAX_D:
6847 case Mips::FMAX_W:
6848 case Mips::FMIN_A_D:
6849 case Mips::FMIN_A_W:
6850 case Mips::FMIN_D:
6851 case Mips::FMIN_W:
6852 case Mips::FMUL_D:
6853 case Mips::FMUL_W:
6854 case Mips::FSAF_D:
6855 case Mips::FSAF_W:
6856 case Mips::FSEQ_D:
6857 case Mips::FSEQ_W:
6858 case Mips::FSLE_D:
6859 case Mips::FSLE_W:
6860 case Mips::FSLT_D:
6861 case Mips::FSLT_W:
6862 case Mips::FSNE_D:
6863 case Mips::FSNE_W:
6864 case Mips::FSOR_D:
6865 case Mips::FSOR_W:
6866 case Mips::FSUB_D:
6867 case Mips::FSUB_W:
6868 case Mips::FSUEQ_D:
6869 case Mips::FSUEQ_W:
6870 case Mips::FSULE_D:
6871 case Mips::FSULE_W:
6872 case Mips::FSULT_D:
6873 case Mips::FSULT_W:
6874 case Mips::FSUNE_D:
6875 case Mips::FSUNE_W:
6876 case Mips::FSUN_D:
6877 case Mips::FSUN_W:
6878 case Mips::FTQ_H:
6879 case Mips::FTQ_W:
6880 case Mips::HADD_S_D:
6881 case Mips::HADD_S_H:
6882 case Mips::HADD_S_W:
6883 case Mips::HADD_U_D:
6884 case Mips::HADD_U_H:
6885 case Mips::HADD_U_W:
6886 case Mips::HSUB_S_D:
6887 case Mips::HSUB_S_H:
6888 case Mips::HSUB_S_W:
6889 case Mips::HSUB_U_D:
6890 case Mips::HSUB_U_H:
6891 case Mips::HSUB_U_W:
6892 case Mips::ILVEV_B:
6893 case Mips::ILVEV_D:
6894 case Mips::ILVEV_H:
6895 case Mips::ILVEV_W:
6896 case Mips::ILVL_B:
6897 case Mips::ILVL_D:
6898 case Mips::ILVL_H:
6899 case Mips::ILVL_W:
6900 case Mips::ILVOD_B:
6901 case Mips::ILVOD_D:
6902 case Mips::ILVOD_H:
6903 case Mips::ILVOD_W:
6904 case Mips::ILVR_B:
6905 case Mips::ILVR_D:
6906 case Mips::ILVR_H:
6907 case Mips::ILVR_W:
6908 case Mips::MAX_A_B:
6909 case Mips::MAX_A_D:
6910 case Mips::MAX_A_H:
6911 case Mips::MAX_A_W:
6912 case Mips::MAX_S_B:
6913 case Mips::MAX_S_D:
6914 case Mips::MAX_S_H:
6915 case Mips::MAX_S_W:
6916 case Mips::MAX_U_B:
6917 case Mips::MAX_U_D:
6918 case Mips::MAX_U_H:
6919 case Mips::MAX_U_W:
6920 case Mips::MIN_A_B:
6921 case Mips::MIN_A_D:
6922 case Mips::MIN_A_H:
6923 case Mips::MIN_A_W:
6924 case Mips::MIN_S_B:
6925 case Mips::MIN_S_D:
6926 case Mips::MIN_S_H:
6927 case Mips::MIN_S_W:
6928 case Mips::MIN_U_B:
6929 case Mips::MIN_U_D:
6930 case Mips::MIN_U_H:
6931 case Mips::MIN_U_W:
6932 case Mips::MOD_S_B:
6933 case Mips::MOD_S_D:
6934 case Mips::MOD_S_H:
6935 case Mips::MOD_S_W:
6936 case Mips::MOD_U_B:
6937 case Mips::MOD_U_D:
6938 case Mips::MOD_U_H:
6939 case Mips::MOD_U_W:
6940 case Mips::MULR_Q_H:
6941 case Mips::MULR_Q_W:
6942 case Mips::MULV_B:
6943 case Mips::MULV_D:
6944 case Mips::MULV_H:
6945 case Mips::MULV_W:
6946 case Mips::MUL_Q_H:
6947 case Mips::MUL_Q_W:
6948 case Mips::NOR_V:
6949 case Mips::OR_V:
6950 case Mips::PCKEV_B:
6951 case Mips::PCKEV_D:
6952 case Mips::PCKEV_H:
6953 case Mips::PCKEV_W:
6954 case Mips::PCKOD_B:
6955 case Mips::PCKOD_D:
6956 case Mips::PCKOD_H:
6957 case Mips::PCKOD_W:
6958 case Mips::SLL_B:
6959 case Mips::SLL_D:
6960 case Mips::SLL_H:
6961 case Mips::SLL_W:
6962 case Mips::SRAR_B:
6963 case Mips::SRAR_D:
6964 case Mips::SRAR_H:
6965 case Mips::SRAR_W:
6966 case Mips::SRA_B:
6967 case Mips::SRA_D:
6968 case Mips::SRA_H:
6969 case Mips::SRA_W:
6970 case Mips::SRLR_B:
6971 case Mips::SRLR_D:
6972 case Mips::SRLR_H:
6973 case Mips::SRLR_W:
6974 case Mips::SRL_B:
6975 case Mips::SRL_D:
6976 case Mips::SRL_H:
6977 case Mips::SRL_W:
6978 case Mips::SUBSUS_U_B:
6979 case Mips::SUBSUS_U_D:
6980 case Mips::SUBSUS_U_H:
6981 case Mips::SUBSUS_U_W:
6982 case Mips::SUBSUU_S_B:
6983 case Mips::SUBSUU_S_D:
6984 case Mips::SUBSUU_S_H:
6985 case Mips::SUBSUU_S_W:
6986 case Mips::SUBS_S_B:
6987 case Mips::SUBS_S_D:
6988 case Mips::SUBS_S_H:
6989 case Mips::SUBS_S_W:
6990 case Mips::SUBS_U_B:
6991 case Mips::SUBS_U_D:
6992 case Mips::SUBS_U_H:
6993 case Mips::SUBS_U_W:
6994 case Mips::SUBV_B:
6995 case Mips::SUBV_D:
6996 case Mips::SUBV_H:
6997 case Mips::SUBV_W:
6998 case Mips::XOR_V: {
6999 // op: wt
7000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7001 Value |= (op & 0x1f) << 16;
7002 // op: ws
7003 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7004 Value |= (op & 0x1f) << 11;
7005 // op: wd
7006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7007 Value |= (op & 0x1f) << 6;
7008 break;
7009 }
7010 case Mips::BINSL_B:
7011 case Mips::BINSL_D:
7012 case Mips::BINSL_H:
7013 case Mips::BINSL_W:
7014 case Mips::BINSR_B:
7015 case Mips::BINSR_D:
7016 case Mips::BINSR_H:
7017 case Mips::BINSR_W:
7018 case Mips::BMNZ_V:
7019 case Mips::BMZ_V:
7020 case Mips::BSEL_V:
7021 case Mips::DPADD_S_D:
7022 case Mips::DPADD_S_H:
7023 case Mips::DPADD_S_W:
7024 case Mips::DPADD_U_D:
7025 case Mips::DPADD_U_H:
7026 case Mips::DPADD_U_W:
7027 case Mips::DPSUB_S_D:
7028 case Mips::DPSUB_S_H:
7029 case Mips::DPSUB_S_W:
7030 case Mips::DPSUB_U_D:
7031 case Mips::DPSUB_U_H:
7032 case Mips::DPSUB_U_W:
7033 case Mips::FMADD_D:
7034 case Mips::FMADD_W:
7035 case Mips::FMSUB_D:
7036 case Mips::FMSUB_W:
7037 case Mips::MADDR_Q_H:
7038 case Mips::MADDR_Q_W:
7039 case Mips::MADDV_B:
7040 case Mips::MADDV_D:
7041 case Mips::MADDV_H:
7042 case Mips::MADDV_W:
7043 case Mips::MADD_Q_H:
7044 case Mips::MADD_Q_W:
7045 case Mips::MSUBR_Q_H:
7046 case Mips::MSUBR_Q_W:
7047 case Mips::MSUBV_B:
7048 case Mips::MSUBV_D:
7049 case Mips::MSUBV_H:
7050 case Mips::MSUBV_W:
7051 case Mips::MSUB_Q_H:
7052 case Mips::MSUB_Q_W:
7053 case Mips::VSHF_B:
7054 case Mips::VSHF_D:
7055 case Mips::VSHF_H:
7056 case Mips::VSHF_W: {
7057 // op: wt
7058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7059 Value |= (op & 0x1f) << 16;
7060 // op: ws
7061 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7062 Value |= (op & 0x1f) << 11;
7063 // op: wd
7064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7065 Value |= (op & 0x1f) << 6;
7066 break;
7067 }
7068 default:
7069 reportUnsupportedInst(Inst: MI);
7070 }
7071 return Value;
7072}
7073
7074#ifdef GET_OPERAND_BIT_OFFSET
7075#undef GET_OPERAND_BIT_OFFSET
7076
7077uint32_t MipsMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
7078 unsigned OpNum,
7079 const MCSubtargetInfo &STI) const {
7080 switch (MI.getOpcode()) {
7081 case Mips::Break16:
7082 case Mips::DERET:
7083 case Mips::DERET_MM:
7084 case Mips::DERET_MMR6:
7085 case Mips::EHB:
7086 case Mips::EHB_MM:
7087 case Mips::EHB_MMR6:
7088 case Mips::ERET:
7089 case Mips::ERETNC:
7090 case Mips::ERETNC_MMR6:
7091 case Mips::ERET_MM:
7092 case Mips::ERET_MMR6:
7093 case Mips::JrRa16:
7094 case Mips::JrcRa16:
7095 case Mips::NAL:
7096 case Mips::PAUSE:
7097 case Mips::PAUSE_MM:
7098 case Mips::PAUSE_MMR6:
7099 case Mips::Restore16:
7100 case Mips::RestoreX16:
7101 case Mips::SSNOP:
7102 case Mips::SSNOP_MM:
7103 case Mips::SSNOP_MMR6:
7104 case Mips::Save16:
7105 case Mips::SaveX16:
7106 case Mips::TLBGINV:
7107 case Mips::TLBGINVF:
7108 case Mips::TLBGINVF_MM:
7109 case Mips::TLBGINV_MM:
7110 case Mips::TLBGP:
7111 case Mips::TLBGP_MM:
7112 case Mips::TLBGR:
7113 case Mips::TLBGR_MM:
7114 case Mips::TLBGWI:
7115 case Mips::TLBGWI_MM:
7116 case Mips::TLBGWR:
7117 case Mips::TLBGWR_MM:
7118 case Mips::TLBINV:
7119 case Mips::TLBINVF:
7120 case Mips::TLBINVF_MMR6:
7121 case Mips::TLBINV_MMR6:
7122 case Mips::TLBP:
7123 case Mips::TLBP_MM:
7124 case Mips::TLBR:
7125 case Mips::TLBR_MM:
7126 case Mips::TLBWI:
7127 case Mips::TLBWI_MM:
7128 case Mips::TLBWR:
7129 case Mips::TLBWR_MM:
7130 case Mips::WAIT: {
7131 break;
7132 }
7133 case Mips::DPAQX_SA_W_PH:
7134 case Mips::DPAQX_S_W_PH:
7135 case Mips::DPAQ_SA_L_W:
7136 case Mips::DPAQ_S_W_PH:
7137 case Mips::DPAU_H_QBL:
7138 case Mips::DPAU_H_QBR:
7139 case Mips::DPAX_W_PH:
7140 case Mips::DPA_W_PH:
7141 case Mips::DPSQX_SA_W_PH:
7142 case Mips::DPSQX_S_W_PH:
7143 case Mips::DPSQ_SA_L_W:
7144 case Mips::DPSQ_S_W_PH:
7145 case Mips::DPSU_H_QBL:
7146 case Mips::DPSU_H_QBR:
7147 case Mips::DPSX_W_PH:
7148 case Mips::DPS_W_PH:
7149 case Mips::MADDU_DSP:
7150 case Mips::MADD_DSP:
7151 case Mips::MAQ_SA_W_PHL:
7152 case Mips::MAQ_SA_W_PHR:
7153 case Mips::MAQ_S_W_PHL:
7154 case Mips::MAQ_S_W_PHR:
7155 case Mips::MSUBU_DSP:
7156 case Mips::MSUB_DSP:
7157 case Mips::MULSAQ_S_W_PH:
7158 case Mips::MULSA_W_PH:
7159 case Mips::MULTU_DSP:
7160 case Mips::MULT_DSP: {
7161 switch (OpNum) {
7162 case 0:
7163 // op: ac
7164 return 11;
7165 case 1:
7166 // op: rs
7167 return 21;
7168 case 2:
7169 // op: rt
7170 return 16;
7171 }
7172 break;
7173 }
7174 case Mips::MTHLIP:
7175 case Mips::SHILOV: {
7176 switch (OpNum) {
7177 case 0:
7178 // op: ac
7179 return 11;
7180 case 1:
7181 // op: rs
7182 return 21;
7183 }
7184 break;
7185 }
7186 case Mips::SHILO: {
7187 switch (OpNum) {
7188 case 0:
7189 // op: ac
7190 return 11;
7191 case 1:
7192 // op: shift
7193 return 20;
7194 }
7195 break;
7196 }
7197 case Mips::CACHE:
7198 case Mips::PREF: {
7199 switch (OpNum) {
7200 case 0:
7201 // op: addr
7202 return 0;
7203 case 2:
7204 // op: hint
7205 return 16;
7206 }
7207 break;
7208 }
7209 case Mips::CACHEE_MM:
7210 case Mips::CACHE_MM:
7211 case Mips::CACHE_MMR6:
7212 case Mips::PREFE_MM:
7213 case Mips::PREF_MM:
7214 case Mips::PREF_MMR6: {
7215 switch (OpNum) {
7216 case 0:
7217 // op: addr
7218 return 0;
7219 case 2:
7220 // op: hint
7221 return 21;
7222 }
7223 break;
7224 }
7225 case Mips::SYNCI:
7226 case Mips::SYNCI_MM:
7227 case Mips::SYNCI_MMR6: {
7228 switch (OpNum) {
7229 case 0:
7230 // op: addr
7231 return 0;
7232 }
7233 break;
7234 }
7235 case Mips::CACHEE:
7236 case Mips::CACHE_R6:
7237 case Mips::PREFE:
7238 case Mips::PREF_R6: {
7239 switch (OpNum) {
7240 case 0:
7241 // op: addr
7242 return 7;
7243 case 2:
7244 // op: hint
7245 return 16;
7246 }
7247 break;
7248 }
7249 case Mips::BREAK16_MM:
7250 case Mips::SDBBP16_MM:
7251 case Mips::SIGRIE: {
7252 switch (OpNum) {
7253 case 0:
7254 // op: code_
7255 return 0;
7256 }
7257 break;
7258 }
7259 case Mips::HYPCALL: {
7260 switch (OpNum) {
7261 case 0:
7262 // op: code_
7263 return 11;
7264 }
7265 break;
7266 }
7267 case Mips::HYPCALL_MM:
7268 case Mips::SDBBP_MM:
7269 case Mips::SDBBP_MMR6:
7270 case Mips::SYSCALL_MM:
7271 case Mips::WAIT_MM:
7272 case Mips::WAIT_MMR6: {
7273 switch (OpNum) {
7274 case 0:
7275 // op: code_
7276 return 16;
7277 }
7278 break;
7279 }
7280 case Mips::BREAK16_MMR6:
7281 case Mips::SDBBP:
7282 case Mips::SDBBP16_MMR6:
7283 case Mips::SDBBP_R6:
7284 case Mips::SIGRIE_MMR6:
7285 case Mips::SYSCALL: {
7286 switch (OpNum) {
7287 case 0:
7288 // op: code_
7289 return 6;
7290 }
7291 break;
7292 }
7293 case Mips::BREAK:
7294 case Mips::BREAK_MM:
7295 case Mips::BREAK_MMR6: {
7296 switch (OpNum) {
7297 case 0:
7298 // op: code_1
7299 return 16;
7300 case 1:
7301 // op: code_2
7302 return 6;
7303 }
7304 break;
7305 }
7306 case Mips::BC2EQZ:
7307 case Mips::BC2NEZ: {
7308 switch (OpNum) {
7309 case 0:
7310 // op: ct
7311 return 16;
7312 case 1:
7313 // op: offset
7314 return 0;
7315 }
7316 break;
7317 }
7318 case Mips::BC1F:
7319 case Mips::BC1FL:
7320 case Mips::BC1F_MM:
7321 case Mips::BC1T:
7322 case Mips::BC1TL:
7323 case Mips::BC1T_MM: {
7324 switch (OpNum) {
7325 case 0:
7326 // op: fcc
7327 return 18;
7328 case 1:
7329 // op: offset
7330 return 0;
7331 }
7332 break;
7333 }
7334 case Mips::LUXC1_MM:
7335 case Mips::LWXC1_MM: {
7336 switch (OpNum) {
7337 case 0:
7338 // op: fd
7339 return 11;
7340 case 1:
7341 // op: base
7342 return 16;
7343 case 2:
7344 // op: index
7345 return 21;
7346 }
7347 break;
7348 }
7349 case Mips::MOVN_I_D32_MM:
7350 case Mips::MOVN_I_S_MM:
7351 case Mips::MOVZ_I_D32_MM:
7352 case Mips::MOVZ_I_S_MM: {
7353 switch (OpNum) {
7354 case 0:
7355 // op: fd
7356 return 11;
7357 case 1:
7358 // op: fs
7359 return 16;
7360 case 2:
7361 // op: rt
7362 return 21;
7363 }
7364 break;
7365 }
7366 case Mips::MOVF_D32_MM:
7367 case Mips::MOVF_S_MM:
7368 case Mips::MOVT_D32_MM:
7369 case Mips::MOVT_S_MM: {
7370 switch (OpNum) {
7371 case 0:
7372 // op: fd
7373 return 21;
7374 case 1:
7375 // op: fs
7376 return 16;
7377 case 2:
7378 // op: fcc
7379 return 13;
7380 }
7381 break;
7382 }
7383 case Mips::CEIL_W_MM:
7384 case Mips::CEIL_W_S_MM:
7385 case Mips::CVT_D32_S_MM:
7386 case Mips::CVT_D32_W_MM:
7387 case Mips::CVT_D64_S_MM:
7388 case Mips::CVT_D64_W_MM:
7389 case Mips::CVT_L_D64_MM:
7390 case Mips::CVT_L_S_MM:
7391 case Mips::CVT_S_D32_MM:
7392 case Mips::CVT_S_D64_MM:
7393 case Mips::CVT_S_W_MM:
7394 case Mips::CVT_W_D32_MM:
7395 case Mips::CVT_W_D64_MM:
7396 case Mips::CVT_W_S_MM:
7397 case Mips::FABS_D32_MM:
7398 case Mips::FABS_D64_MM:
7399 case Mips::FABS_S_MM:
7400 case Mips::FLOOR_W_MM:
7401 case Mips::FLOOR_W_S_MM:
7402 case Mips::FMOV_D32_MM:
7403 case Mips::FMOV_D64_MM:
7404 case Mips::FMOV_S_MM:
7405 case Mips::FNEG_D32_MM:
7406 case Mips::FNEG_D64_MM:
7407 case Mips::FNEG_S_MM:
7408 case Mips::FSQRT_D32_MM:
7409 case Mips::FSQRT_D64_MM:
7410 case Mips::FSQRT_S_MM:
7411 case Mips::RECIP_D32_MM:
7412 case Mips::RECIP_D64_MM:
7413 case Mips::RECIP_S_MM:
7414 case Mips::ROUND_W_MM:
7415 case Mips::ROUND_W_S_MM:
7416 case Mips::RSQRT_D32_MM:
7417 case Mips::RSQRT_D64_MM:
7418 case Mips::RSQRT_S_MM:
7419 case Mips::TRUNC_W_MM:
7420 case Mips::TRUNC_W_S_MM: {
7421 switch (OpNum) {
7422 case 0:
7423 // op: fd
7424 return 21;
7425 case 1:
7426 // op: fs
7427 return 16;
7428 }
7429 break;
7430 }
7431 case Mips::LDXC1:
7432 case Mips::LDXC164:
7433 case Mips::LUXC1:
7434 case Mips::LUXC164:
7435 case Mips::LWXC1: {
7436 switch (OpNum) {
7437 case 0:
7438 // op: fd
7439 return 6;
7440 case 1:
7441 // op: base
7442 return 21;
7443 case 2:
7444 // op: index
7445 return 16;
7446 }
7447 break;
7448 }
7449 case Mips::MADD_D32:
7450 case Mips::MADD_D64:
7451 case Mips::MADD_S:
7452 case Mips::MSUB_D32:
7453 case Mips::MSUB_D64:
7454 case Mips::MSUB_S:
7455 case Mips::NMADD_D32:
7456 case Mips::NMADD_D64:
7457 case Mips::NMADD_S:
7458 case Mips::NMSUB_D32:
7459 case Mips::NMSUB_D64:
7460 case Mips::NMSUB_S: {
7461 switch (OpNum) {
7462 case 0:
7463 // op: fd
7464 return 6;
7465 case 1:
7466 // op: fr
7467 return 21;
7468 case 2:
7469 // op: fs
7470 return 11;
7471 case 3:
7472 // op: ft
7473 return 16;
7474 }
7475 break;
7476 }
7477 case Mips::MOVF_D32:
7478 case Mips::MOVF_D64:
7479 case Mips::MOVF_S:
7480 case Mips::MOVT_D32:
7481 case Mips::MOVT_D64:
7482 case Mips::MOVT_S: {
7483 switch (OpNum) {
7484 case 0:
7485 // op: fd
7486 return 6;
7487 case 1:
7488 // op: fs
7489 return 11;
7490 case 2:
7491 // op: fcc
7492 return 18;
7493 }
7494 break;
7495 }
7496 case Mips::ADDR_PS64:
7497 case Mips::CMP_EQ_D:
7498 case Mips::CMP_EQ_S:
7499 case Mips::CMP_F_D:
7500 case Mips::CMP_F_S:
7501 case Mips::CMP_LE_D:
7502 case Mips::CMP_LE_S:
7503 case Mips::CMP_LT_D:
7504 case Mips::CMP_LT_S:
7505 case Mips::CMP_SAF_D:
7506 case Mips::CMP_SAF_S:
7507 case Mips::CMP_SEQ_D:
7508 case Mips::CMP_SEQ_S:
7509 case Mips::CMP_SLE_D:
7510 case Mips::CMP_SLE_S:
7511 case Mips::CMP_SLT_D:
7512 case Mips::CMP_SLT_S:
7513 case Mips::CMP_SUEQ_D:
7514 case Mips::CMP_SUEQ_S:
7515 case Mips::CMP_SULE_D:
7516 case Mips::CMP_SULE_S:
7517 case Mips::CMP_SULT_D:
7518 case Mips::CMP_SULT_S:
7519 case Mips::CMP_SUN_D:
7520 case Mips::CMP_SUN_S:
7521 case Mips::CMP_UEQ_D:
7522 case Mips::CMP_UEQ_S:
7523 case Mips::CMP_ULE_D:
7524 case Mips::CMP_ULE_S:
7525 case Mips::CMP_ULT_D:
7526 case Mips::CMP_ULT_S:
7527 case Mips::CMP_UN_D:
7528 case Mips::CMP_UN_S:
7529 case Mips::CVT_PS_S64:
7530 case Mips::FADD_D32:
7531 case Mips::FADD_D64:
7532 case Mips::FADD_PS64:
7533 case Mips::FADD_S:
7534 case Mips::FDIV_D32:
7535 case Mips::FDIV_D64:
7536 case Mips::FDIV_S:
7537 case Mips::FMUL_D32:
7538 case Mips::FMUL_D64:
7539 case Mips::FMUL_PS64:
7540 case Mips::FMUL_S:
7541 case Mips::FSUB_D32:
7542 case Mips::FSUB_D64:
7543 case Mips::FSUB_PS64:
7544 case Mips::FSUB_S:
7545 case Mips::MULR_PS64:
7546 case Mips::PLL_PS64:
7547 case Mips::PLU_PS64:
7548 case Mips::PUL_PS64:
7549 case Mips::PUU_PS64: {
7550 switch (OpNum) {
7551 case 0:
7552 // op: fd
7553 return 6;
7554 case 1:
7555 // op: fs
7556 return 11;
7557 case 2:
7558 // op: ft
7559 return 16;
7560 }
7561 break;
7562 }
7563 case Mips::MOVN_I64_D64:
7564 case Mips::MOVN_I64_S:
7565 case Mips::MOVN_I_D32:
7566 case Mips::MOVN_I_D64:
7567 case Mips::MOVN_I_S:
7568 case Mips::MOVZ_I64_D64:
7569 case Mips::MOVZ_I64_S:
7570 case Mips::MOVZ_I_D32:
7571 case Mips::MOVZ_I_D64:
7572 case Mips::MOVZ_I_S: {
7573 switch (OpNum) {
7574 case 0:
7575 // op: fd
7576 return 6;
7577 case 1:
7578 // op: fs
7579 return 11;
7580 case 2:
7581 // op: rt
7582 return 16;
7583 }
7584 break;
7585 }
7586 case Mips::CEIL_L_D64:
7587 case Mips::CEIL_L_S:
7588 case Mips::CEIL_W_D32:
7589 case Mips::CEIL_W_D64:
7590 case Mips::CEIL_W_S:
7591 case Mips::CVT_D32_S:
7592 case Mips::CVT_D32_W:
7593 case Mips::CVT_D64_L:
7594 case Mips::CVT_D64_S:
7595 case Mips::CVT_D64_W:
7596 case Mips::CVT_L_D64:
7597 case Mips::CVT_L_S:
7598 case Mips::CVT_PS_PW64:
7599 case Mips::CVT_PW_PS64:
7600 case Mips::CVT_S_D32:
7601 case Mips::CVT_S_D64:
7602 case Mips::CVT_S_L:
7603 case Mips::CVT_S_PL64:
7604 case Mips::CVT_S_PU64:
7605 case Mips::CVT_S_W:
7606 case Mips::CVT_W_D32:
7607 case Mips::CVT_W_D64:
7608 case Mips::CVT_W_S:
7609 case Mips::FABS_D32:
7610 case Mips::FABS_D64:
7611 case Mips::FABS_S:
7612 case Mips::FLOOR_L_D64:
7613 case Mips::FLOOR_L_S:
7614 case Mips::FLOOR_W_D32:
7615 case Mips::FLOOR_W_D64:
7616 case Mips::FLOOR_W_S:
7617 case Mips::FMOV_D32:
7618 case Mips::FMOV_D64:
7619 case Mips::FMOV_S:
7620 case Mips::FNEG_D32:
7621 case Mips::FNEG_D64:
7622 case Mips::FNEG_S:
7623 case Mips::FSQRT_D32:
7624 case Mips::FSQRT_D64:
7625 case Mips::FSQRT_S:
7626 case Mips::RECIP_D32:
7627 case Mips::RECIP_D64:
7628 case Mips::RECIP_S:
7629 case Mips::ROUND_L_D64:
7630 case Mips::ROUND_L_S:
7631 case Mips::ROUND_W_D32:
7632 case Mips::ROUND_W_D64:
7633 case Mips::ROUND_W_S:
7634 case Mips::RSQRT_D32:
7635 case Mips::RSQRT_D64:
7636 case Mips::RSQRT_S:
7637 case Mips::TRUNC_L_D64:
7638 case Mips::TRUNC_L_S:
7639 case Mips::TRUNC_W_D32:
7640 case Mips::TRUNC_W_D64:
7641 case Mips::TRUNC_W_S: {
7642 switch (OpNum) {
7643 case 0:
7644 // op: fd
7645 return 6;
7646 case 1:
7647 // op: fs
7648 return 11;
7649 }
7650 break;
7651 }
7652 case Mips::SUXC1_MM:
7653 case Mips::SWXC1_MM: {
7654 switch (OpNum) {
7655 case 0:
7656 // op: fs
7657 return 11;
7658 case 1:
7659 // op: base
7660 return 16;
7661 case 2:
7662 // op: index
7663 return 21;
7664 }
7665 break;
7666 }
7667 case Mips::SDXC1:
7668 case Mips::SDXC164:
7669 case Mips::SUXC1:
7670 case Mips::SUXC164:
7671 case Mips::SWXC1: {
7672 switch (OpNum) {
7673 case 0:
7674 // op: fs
7675 return 11;
7676 case 1:
7677 // op: base
7678 return 21;
7679 case 2:
7680 // op: index
7681 return 16;
7682 }
7683 break;
7684 }
7685 case Mips::FCMP_D32:
7686 case Mips::FCMP_D64:
7687 case Mips::FCMP_S32: {
7688 switch (OpNum) {
7689 case 0:
7690 // op: fs
7691 return 11;
7692 case 1:
7693 // op: ft
7694 return 16;
7695 case 2:
7696 // op: cond
7697 return 0;
7698 }
7699 break;
7700 }
7701 case Mips::FCMP_D32_MM:
7702 case Mips::FCMP_S32_MM: {
7703 switch (OpNum) {
7704 case 0:
7705 // op: fs
7706 return 16;
7707 case 1:
7708 // op: ft
7709 return 21;
7710 case 2:
7711 // op: cond
7712 return 6;
7713 }
7714 break;
7715 }
7716 case Mips::BC1EQZ:
7717 case Mips::BC1NEZ: {
7718 switch (OpNum) {
7719 case 0:
7720 // op: ft
7721 return 16;
7722 case 1:
7723 // op: offset
7724 return 0;
7725 }
7726 break;
7727 }
7728 case Mips::LDC1_D64_MMR6:
7729 case Mips::SDC1_D64_MMR6: {
7730 switch (OpNum) {
7731 case 0:
7732 // op: ft
7733 return 21;
7734 case 1:
7735 // op: addr
7736 return 0;
7737 }
7738 break;
7739 }
7740 case Mips::CEIL_L_D_MMR6:
7741 case Mips::CEIL_L_S_MMR6:
7742 case Mips::CEIL_W_D_MMR6:
7743 case Mips::CEIL_W_S_MMR6:
7744 case Mips::CVT_D_L_MMR6:
7745 case Mips::CVT_L_D_MMR6:
7746 case Mips::CVT_L_S_MMR6:
7747 case Mips::CVT_S_L_MMR6:
7748 case Mips::CVT_S_W_MMR6:
7749 case Mips::CVT_W_S_MMR6:
7750 case Mips::FLOOR_L_D_MMR6:
7751 case Mips::FLOOR_L_S_MMR6:
7752 case Mips::FLOOR_W_D_MMR6:
7753 case Mips::FLOOR_W_S_MMR6:
7754 case Mips::FMOV_D_MMR6:
7755 case Mips::FMOV_S_MMR6:
7756 case Mips::FNEG_S_MMR6:
7757 case Mips::ROUND_L_D_MMR6:
7758 case Mips::ROUND_L_S_MMR6:
7759 case Mips::ROUND_W_D_MMR6:
7760 case Mips::ROUND_W_S_MMR6:
7761 case Mips::TRUNC_L_D_MMR6:
7762 case Mips::TRUNC_L_S_MMR6:
7763 case Mips::TRUNC_W_D_MMR6:
7764 case Mips::TRUNC_W_S_MMR6: {
7765 switch (OpNum) {
7766 case 0:
7767 // op: ft
7768 return 21;
7769 case 1:
7770 // op: fs
7771 return 16;
7772 }
7773 break;
7774 }
7775 case Mips::JRADDIUSP: {
7776 switch (OpNum) {
7777 case 0:
7778 // op: imm
7779 return 0;
7780 }
7781 break;
7782 }
7783 case Mips::ADDIUSP_MM: {
7784 switch (OpNum) {
7785 case 0:
7786 // op: imm
7787 return 1;
7788 }
7789 break;
7790 }
7791 case Mips::JRCADDIUSP_MMR6: {
7792 switch (OpNum) {
7793 case 0:
7794 // op: imm
7795 return 5;
7796 }
7797 break;
7798 }
7799 case Mips::Bimm16: {
7800 switch (OpNum) {
7801 case 0:
7802 // op: imm11
7803 return 0;
7804 }
7805 break;
7806 }
7807 case Mips::AddiuSpImmX16:
7808 case Mips::BimmX16:
7809 case Mips::BteqzX16:
7810 case Mips::BtnezX16: {
7811 switch (OpNum) {
7812 case 0:
7813 // op: imm16
7814 return 0;
7815 }
7816 break;
7817 }
7818 case Mips::Jal16:
7819 case Mips::JalB16: {
7820 switch (OpNum) {
7821 case 0:
7822 // op: imm26
7823 return 0;
7824 }
7825 break;
7826 }
7827 case Mips::AddiuSpImm16:
7828 case Mips::Bteqz16:
7829 case Mips::Btnez16: {
7830 switch (OpNum) {
7831 case 0:
7832 // op: imm8
7833 return 0;
7834 }
7835 break;
7836 }
7837 case Mips::B16_MM:
7838 case Mips::BAL:
7839 case Mips::BALC:
7840 case Mips::BALC_MMR6:
7841 case Mips::BC:
7842 case Mips::BC16_MMR6:
7843 case Mips::BC_MMR6:
7844 case Mips::BPOSGE32:
7845 case Mips::BPOSGE32C_MMR3:
7846 case Mips::BPOSGE32_MM: {
7847 switch (OpNum) {
7848 case 0:
7849 // op: offset
7850 return 0;
7851 }
7852 break;
7853 }
7854 case Mips::Move32R16: {
7855 switch (OpNum) {
7856 case 0:
7857 // op: r32
7858 return 3;
7859 case 1:
7860 // op: rz
7861 return 0;
7862 }
7863 break;
7864 }
7865 case Mips::MFHI16_MM:
7866 case Mips::MFLO16_MM: {
7867 switch (OpNum) {
7868 case 0:
7869 // op: rd
7870 return 0;
7871 }
7872 break;
7873 }
7874 case Mips::MFHI_DSP:
7875 case Mips::MFLO_DSP: {
7876 switch (OpNum) {
7877 case 0:
7878 // op: rd
7879 return 11;
7880 case 1:
7881 // op: ac
7882 return 21;
7883 }
7884 break;
7885 }
7886 case Mips::LWXS_MM: {
7887 switch (OpNum) {
7888 case 0:
7889 // op: rd
7890 return 11;
7891 case 1:
7892 // op: base
7893 return 16;
7894 case 2:
7895 // op: index
7896 return 21;
7897 }
7898 break;
7899 }
7900 case Mips::LBUX:
7901 case Mips::LHX:
7902 case Mips::LWX: {
7903 switch (OpNum) {
7904 case 0:
7905 // op: rd
7906 return 11;
7907 case 1:
7908 // op: base
7909 return 21;
7910 case 2:
7911 // op: index
7912 return 16;
7913 }
7914 break;
7915 }
7916 case Mips::REPL_PH:
7917 case Mips::REPL_PH_MM:
7918 case Mips::REPL_QB: {
7919 switch (OpNum) {
7920 case 0:
7921 // op: rd
7922 return 11;
7923 case 1:
7924 // op: imm
7925 return 16;
7926 }
7927 break;
7928 }
7929 case Mips::RDDSP: {
7930 switch (OpNum) {
7931 case 0:
7932 // op: rd
7933 return 11;
7934 case 1:
7935 // op: mask
7936 return 16;
7937 }
7938 break;
7939 }
7940 case Mips::LSA_MMR6: {
7941 switch (OpNum) {
7942 case 0:
7943 // op: rd
7944 return 11;
7945 case 1:
7946 // op: rs
7947 return 16;
7948 case 2:
7949 // op: rt
7950 return 21;
7951 case 3:
7952 // op: imm2
7953 return 9;
7954 }
7955 break;
7956 }
7957 case Mips::ADDQH_PH_MMR2:
7958 case Mips::ADDQH_R_PH_MMR2:
7959 case Mips::ADDQH_R_W_MMR2:
7960 case Mips::ADDQH_W_MMR2:
7961 case Mips::ADDQ_PH_MM:
7962 case Mips::ADDQ_S_PH_MM:
7963 case Mips::ADDQ_S_W_MM:
7964 case Mips::ADDSC_MM:
7965 case Mips::ADDUH_QB_MMR2:
7966 case Mips::ADDUH_R_QB_MMR2:
7967 case Mips::ADDU_PH_MMR2:
7968 case Mips::ADDU_QB_MM:
7969 case Mips::ADDU_S_PH_MMR2:
7970 case Mips::ADDU_S_QB_MM:
7971 case Mips::ADDWC_MM:
7972 case Mips::CMPGDU_EQ_QB_MMR2:
7973 case Mips::CMPGDU_LE_QB_MMR2:
7974 case Mips::CMPGDU_LT_QB_MMR2:
7975 case Mips::MODSUB_MM:
7976 case Mips::MULEQ_S_W_PHL_MM:
7977 case Mips::MULEQ_S_W_PHR_MM:
7978 case Mips::MULEU_S_PH_QBL_MM:
7979 case Mips::MULEU_S_PH_QBR_MM:
7980 case Mips::MULQ_RS_PH_MM:
7981 case Mips::MULQ_RS_W_MMR2:
7982 case Mips::MULQ_S_PH_MMR2:
7983 case Mips::MULQ_S_W_MMR2:
7984 case Mips::MUL_PH_MMR2:
7985 case Mips::MUL_S_PH_MMR2:
7986 case Mips::PACKRL_PH_MM:
7987 case Mips::PICK_PH_MM:
7988 case Mips::PICK_QB_MM:
7989 case Mips::PRECRQU_S_QB_PH_MM:
7990 case Mips::PRECRQ_PH_W_MM:
7991 case Mips::PRECRQ_QB_PH_MM:
7992 case Mips::PRECRQ_RS_PH_W_MM:
7993 case Mips::PRECR_QB_PH_MMR2:
7994 case Mips::SELEQZ_MMR6:
7995 case Mips::SELNEZ_MMR6:
7996 case Mips::SUBQH_PH_MMR2:
7997 case Mips::SUBQH_R_PH_MMR2:
7998 case Mips::SUBQH_R_W_MMR2:
7999 case Mips::SUBQH_W_MMR2:
8000 case Mips::SUBQ_PH_MM:
8001 case Mips::SUBQ_S_PH_MM:
8002 case Mips::SUBQ_S_W_MM:
8003 case Mips::SUBUH_QB_MMR2:
8004 case Mips::SUBUH_R_QB_MMR2:
8005 case Mips::SUBU_PH_MMR2:
8006 case Mips::SUBU_QB_MM:
8007 case Mips::SUBU_S_PH_MMR2:
8008 case Mips::SUBU_S_QB_MM: {
8009 switch (OpNum) {
8010 case 0:
8011 // op: rd
8012 return 11;
8013 case 1:
8014 // op: rs
8015 return 16;
8016 case 2:
8017 // op: rt
8018 return 21;
8019 }
8020 break;
8021 }
8022 case Mips::MOVF_I:
8023 case Mips::MOVF_I64:
8024 case Mips::MOVT_I:
8025 case Mips::MOVT_I64: {
8026 switch (OpNum) {
8027 case 0:
8028 // op: rd
8029 return 11;
8030 case 1:
8031 // op: rs
8032 return 21;
8033 case 2:
8034 // op: fcc
8035 return 18;
8036 }
8037 break;
8038 }
8039 case Mips::ALIGN:
8040 case Mips::DALIGN: {
8041 switch (OpNum) {
8042 case 0:
8043 // op: rd
8044 return 11;
8045 case 1:
8046 // op: rs
8047 return 21;
8048 case 2:
8049 // op: rt
8050 return 16;
8051 case 3:
8052 // op: bp
8053 return 6;
8054 }
8055 break;
8056 }
8057 case Mips::ALIGN_MMR6: {
8058 switch (OpNum) {
8059 case 0:
8060 // op: rd
8061 return 11;
8062 case 1:
8063 // op: rs
8064 return 21;
8065 case 2:
8066 // op: rt
8067 return 16;
8068 case 3:
8069 // op: bp
8070 return 9;
8071 }
8072 break;
8073 }
8074 case Mips::DLSA_R6:
8075 case Mips::LSA_R6: {
8076 switch (OpNum) {
8077 case 0:
8078 // op: rd
8079 return 11;
8080 case 1:
8081 // op: rs
8082 return 21;
8083 case 2:
8084 // op: rt
8085 return 16;
8086 case 3:
8087 // op: imm2
8088 return 6;
8089 }
8090 break;
8091 }
8092 case Mips::ADD:
8093 case Mips::ADDQH_PH:
8094 case Mips::ADDQH_R_PH:
8095 case Mips::ADDQH_R_W:
8096 case Mips::ADDQH_W:
8097 case Mips::ADDQ_PH:
8098 case Mips::ADDQ_S_PH:
8099 case Mips::ADDQ_S_W:
8100 case Mips::ADDSC:
8101 case Mips::ADDUH_QB:
8102 case Mips::ADDUH_R_QB:
8103 case Mips::ADDU_PH:
8104 case Mips::ADDU_QB:
8105 case Mips::ADDU_S_PH:
8106 case Mips::ADDU_S_QB:
8107 case Mips::ADDWC:
8108 case Mips::ADDu:
8109 case Mips::AND:
8110 case Mips::AND64:
8111 case Mips::BADDu:
8112 case Mips::DADD:
8113 case Mips::DADDu:
8114 case Mips::DDIV:
8115 case Mips::DDIVU:
8116 case Mips::DIV:
8117 case Mips::DIVU:
8118 case Mips::DMOD:
8119 case Mips::DMODU:
8120 case Mips::DMUH:
8121 case Mips::DMUHU:
8122 case Mips::DMUL:
8123 case Mips::DMULU:
8124 case Mips::DMUL_R6:
8125 case Mips::DSUB:
8126 case Mips::DSUBu:
8127 case Mips::MOD:
8128 case Mips::MODSUB:
8129 case Mips::MODU:
8130 case Mips::MOVN_I64_I:
8131 case Mips::MOVN_I64_I64:
8132 case Mips::MOVN_I_I:
8133 case Mips::MOVN_I_I64:
8134 case Mips::MOVZ_I64_I:
8135 case Mips::MOVZ_I64_I64:
8136 case Mips::MOVZ_I_I:
8137 case Mips::MOVZ_I_I64:
8138 case Mips::MUH:
8139 case Mips::MUHU:
8140 case Mips::MUL:
8141 case Mips::MULEQ_S_W_PHL:
8142 case Mips::MULEQ_S_W_PHR:
8143 case Mips::MULEU_S_PH_QBL:
8144 case Mips::MULEU_S_PH_QBR:
8145 case Mips::MULQ_RS_PH:
8146 case Mips::MULQ_RS_W:
8147 case Mips::MULQ_S_PH:
8148 case Mips::MULQ_S_W:
8149 case Mips::MULU:
8150 case Mips::MUL_PH:
8151 case Mips::MUL_R6:
8152 case Mips::MUL_S_PH:
8153 case Mips::NOR:
8154 case Mips::NOR64:
8155 case Mips::OR:
8156 case Mips::OR64:
8157 case Mips::SELEQZ:
8158 case Mips::SELEQZ64:
8159 case Mips::SELNEZ:
8160 case Mips::SELNEZ64:
8161 case Mips::SEQ:
8162 case Mips::SLT:
8163 case Mips::SLT64:
8164 case Mips::SLTu:
8165 case Mips::SLTu64:
8166 case Mips::SNE:
8167 case Mips::SUB:
8168 case Mips::SUBQH_PH:
8169 case Mips::SUBQH_R_PH:
8170 case Mips::SUBQH_R_W:
8171 case Mips::SUBQH_W:
8172 case Mips::SUBQ_PH:
8173 case Mips::SUBQ_S_PH:
8174 case Mips::SUBQ_S_W:
8175 case Mips::SUBUH_QB:
8176 case Mips::SUBUH_R_QB:
8177 case Mips::SUBU_PH:
8178 case Mips::SUBU_QB:
8179 case Mips::SUBU_S_PH:
8180 case Mips::SUBU_S_QB:
8181 case Mips::SUBu:
8182 case Mips::V3MULU:
8183 case Mips::VMM0:
8184 case Mips::VMULU:
8185 case Mips::XOR:
8186 case Mips::XOR64: {
8187 switch (OpNum) {
8188 case 0:
8189 // op: rd
8190 return 11;
8191 case 1:
8192 // op: rs
8193 return 21;
8194 case 2:
8195 // op: rt
8196 return 16;
8197 }
8198 break;
8199 }
8200 case Mips::CLO:
8201 case Mips::CLO_R6:
8202 case Mips::CLZ:
8203 case Mips::CLZ_R6:
8204 case Mips::DCLO:
8205 case Mips::DCLO_R6:
8206 case Mips::DCLZ:
8207 case Mips::DCLZ_R6:
8208 case Mips::DPOP:
8209 case Mips::JALR:
8210 case Mips::JALR64:
8211 case Mips::JALR_HB:
8212 case Mips::JALR_HB64:
8213 case Mips::POP:
8214 case Mips::RADDU_W_QB: {
8215 switch (OpNum) {
8216 case 0:
8217 // op: rd
8218 return 11;
8219 case 1:
8220 // op: rs
8221 return 21;
8222 }
8223 break;
8224 }
8225 case Mips::DROTRV:
8226 case Mips::DSLLV:
8227 case Mips::DSRAV:
8228 case Mips::DSRLV:
8229 case Mips::ROTRV:
8230 case Mips::SLLV:
8231 case Mips::SRAV:
8232 case Mips::SRLV: {
8233 switch (OpNum) {
8234 case 0:
8235 // op: rd
8236 return 11;
8237 case 1:
8238 // op: rt
8239 return 16;
8240 case 2:
8241 // op: rs
8242 return 21;
8243 }
8244 break;
8245 }
8246 case Mips::SHLLV_PH:
8247 case Mips::SHLLV_QB:
8248 case Mips::SHLLV_S_PH:
8249 case Mips::SHLLV_S_W:
8250 case Mips::SHLL_PH:
8251 case Mips::SHLL_QB:
8252 case Mips::SHLL_S_PH:
8253 case Mips::SHLL_S_W:
8254 case Mips::SHRAV_PH:
8255 case Mips::SHRAV_QB:
8256 case Mips::SHRAV_R_PH:
8257 case Mips::SHRAV_R_QB:
8258 case Mips::SHRAV_R_W:
8259 case Mips::SHRA_PH:
8260 case Mips::SHRA_QB:
8261 case Mips::SHRA_R_PH:
8262 case Mips::SHRA_R_QB:
8263 case Mips::SHRA_R_W:
8264 case Mips::SHRLV_PH:
8265 case Mips::SHRLV_QB:
8266 case Mips::SHRL_PH:
8267 case Mips::SHRL_QB: {
8268 switch (OpNum) {
8269 case 0:
8270 // op: rd
8271 return 11;
8272 case 1:
8273 // op: rt
8274 return 16;
8275 case 2:
8276 // op: rs_sa
8277 return 21;
8278 }
8279 break;
8280 }
8281 case Mips::DROTR:
8282 case Mips::DROTR32:
8283 case Mips::DSLL:
8284 case Mips::DSLL32:
8285 case Mips::DSRA:
8286 case Mips::DSRA32:
8287 case Mips::DSRL:
8288 case Mips::DSRL32:
8289 case Mips::ROTR:
8290 case Mips::SLL:
8291 case Mips::SRA:
8292 case Mips::SRL: {
8293 switch (OpNum) {
8294 case 0:
8295 // op: rd
8296 return 11;
8297 case 1:
8298 // op: rt
8299 return 16;
8300 case 2:
8301 // op: shamt
8302 return 6;
8303 }
8304 break;
8305 }
8306 case Mips::ABSQ_S_PH:
8307 case Mips::ABSQ_S_QB:
8308 case Mips::ABSQ_S_W:
8309 case Mips::BITREV:
8310 case Mips::BITSWAP:
8311 case Mips::DBITSWAP:
8312 case Mips::DSBH:
8313 case Mips::DSHD:
8314 case Mips::DSLL64_32:
8315 case Mips::PRECEQU_PH_QBL:
8316 case Mips::PRECEQU_PH_QBLA:
8317 case Mips::PRECEQU_PH_QBR:
8318 case Mips::PRECEQU_PH_QBRA:
8319 case Mips::PRECEQ_W_PHL:
8320 case Mips::PRECEQ_W_PHR:
8321 case Mips::PRECEU_PH_QBL:
8322 case Mips::PRECEU_PH_QBLA:
8323 case Mips::PRECEU_PH_QBR:
8324 case Mips::PRECEU_PH_QBRA:
8325 case Mips::REPLV_PH:
8326 case Mips::REPLV_QB:
8327 case Mips::SEB:
8328 case Mips::SEB64:
8329 case Mips::SEH:
8330 case Mips::SEH64:
8331 case Mips::SLL64_32:
8332 case Mips::SLL64_64:
8333 case Mips::WSBH: {
8334 switch (OpNum) {
8335 case 0:
8336 // op: rd
8337 return 11;
8338 case 1:
8339 // op: rt
8340 return 16;
8341 }
8342 break;
8343 }
8344 case Mips::ROTRV_MM:
8345 case Mips::SLLV_MM:
8346 case Mips::SRAV_MM:
8347 case Mips::SRLV_MM: {
8348 switch (OpNum) {
8349 case 0:
8350 // op: rd
8351 return 11;
8352 case 1:
8353 // op: rt
8354 return 21;
8355 case 2:
8356 // op: rs
8357 return 16;
8358 }
8359 break;
8360 }
8361 case Mips::SHLLV_PH_MM:
8362 case Mips::SHLLV_QB_MM:
8363 case Mips::SHLLV_S_PH_MM:
8364 case Mips::SHLLV_S_W_MM:
8365 case Mips::SHRAV_PH_MM:
8366 case Mips::SHRAV_QB_MMR2:
8367 case Mips::SHRAV_R_PH_MM:
8368 case Mips::SHRAV_R_QB_MMR2:
8369 case Mips::SHRAV_R_W_MM:
8370 case Mips::SHRLV_PH_MMR2:
8371 case Mips::SHRLV_QB_MM: {
8372 switch (OpNum) {
8373 case 0:
8374 // op: rd
8375 return 11;
8376 case 2:
8377 // op: rs
8378 return 16;
8379 case 1:
8380 // op: rt
8381 return 21;
8382 }
8383 break;
8384 }
8385 case Mips::ADDU_MMR6:
8386 case Mips::ADD_MMR6:
8387 case Mips::AND_MMR6:
8388 case Mips::DIVU_MMR6:
8389 case Mips::DIV_MMR6:
8390 case Mips::MODU_MMR6:
8391 case Mips::MOD_MMR6:
8392 case Mips::MUHU_MMR6:
8393 case Mips::MUH_MMR6:
8394 case Mips::MULU_MMR6:
8395 case Mips::MUL_MMR6:
8396 case Mips::NOR_MMR6:
8397 case Mips::OR_MMR6:
8398 case Mips::SUBU_MMR6:
8399 case Mips::SUB_MMR6:
8400 case Mips::XOR_MMR6: {
8401 switch (OpNum) {
8402 case 0:
8403 // op: rd
8404 return 11;
8405 case 2:
8406 // op: rt
8407 return 21;
8408 case 1:
8409 // op: rs
8410 return 16;
8411 }
8412 break;
8413 }
8414 case Mips::MFHI:
8415 case Mips::MFHI64:
8416 case Mips::MFLO:
8417 case Mips::MFLO64: {
8418 switch (OpNum) {
8419 case 0:
8420 // op: rd
8421 return 11;
8422 }
8423 break;
8424 }
8425 case Mips::BITSWAP_MMR6: {
8426 switch (OpNum) {
8427 case 0:
8428 // op: rd
8429 return 16;
8430 case 1:
8431 // op: rt
8432 return 21;
8433 }
8434 break;
8435 }
8436 case Mips::MFHI_MM:
8437 case Mips::MFLO_MM: {
8438 switch (OpNum) {
8439 case 0:
8440 // op: rd
8441 return 16;
8442 }
8443 break;
8444 }
8445 case Mips::MOVF_I_MM:
8446 case Mips::MOVT_I_MM: {
8447 switch (OpNum) {
8448 case 0:
8449 // op: rd
8450 return 21;
8451 case 1:
8452 // op: rs
8453 return 16;
8454 case 2:
8455 // op: fcc
8456 return 13;
8457 }
8458 break;
8459 }
8460 case Mips::CLO_MM:
8461 case Mips::CLZ_MM: {
8462 switch (OpNum) {
8463 case 0:
8464 // op: rd
8465 return 21;
8466 case 1:
8467 // op: rs
8468 return 16;
8469 }
8470 break;
8471 }
8472 case Mips::ROTR_MM:
8473 case Mips::SLL_MM:
8474 case Mips::SLL_MMR6:
8475 case Mips::SRA_MM:
8476 case Mips::SRL_MM: {
8477 switch (OpNum) {
8478 case 0:
8479 // op: rd
8480 return 21;
8481 case 1:
8482 // op: rt
8483 return 16;
8484 case 2:
8485 // op: shamt
8486 return 11;
8487 }
8488 break;
8489 }
8490 case Mips::SEB_MM:
8491 case Mips::SEH_MM:
8492 case Mips::WSBH_MM: {
8493 switch (OpNum) {
8494 case 0:
8495 // op: rd
8496 return 21;
8497 case 1:
8498 // op: rt
8499 return 16;
8500 }
8501 break;
8502 }
8503 case Mips::CFCMSA: {
8504 switch (OpNum) {
8505 case 0:
8506 // op: rd
8507 return 6;
8508 case 1:
8509 // op: cs
8510 return 11;
8511 }
8512 break;
8513 }
8514 case Mips::LI16_MM:
8515 case Mips::LI16_MMR6: {
8516 switch (OpNum) {
8517 case 0:
8518 // op: rd
8519 return 7;
8520 case 1:
8521 // op: imm
8522 return 0;
8523 }
8524 break;
8525 }
8526 case Mips::ADDIUR1SP_MM: {
8527 switch (OpNum) {
8528 case 0:
8529 // op: rd
8530 return 7;
8531 case 1:
8532 // op: imm
8533 return 1;
8534 }
8535 break;
8536 }
8537 case Mips::ANDI16_MM:
8538 case Mips::ANDI16_MMR6: {
8539 switch (OpNum) {
8540 case 0:
8541 // op: rd
8542 return 7;
8543 case 1:
8544 // op: rs
8545 return 4;
8546 case 2:
8547 // op: imm
8548 return 0;
8549 }
8550 break;
8551 }
8552 case Mips::ADDIUR2_MM: {
8553 switch (OpNum) {
8554 case 0:
8555 // op: rd
8556 return 7;
8557 case 1:
8558 // op: rs
8559 return 4;
8560 case 2:
8561 // op: imm
8562 return 1;
8563 }
8564 break;
8565 }
8566 case Mips::SLL16_MM:
8567 case Mips::SLL16_MMR6:
8568 case Mips::SRL16_MM:
8569 case Mips::SRL16_MMR6: {
8570 switch (OpNum) {
8571 case 0:
8572 // op: rd
8573 return 7;
8574 case 1:
8575 // op: rt
8576 return 4;
8577 case 2:
8578 // op: shamt
8579 return 1;
8580 }
8581 break;
8582 }
8583 case Mips::ADDU16_MM:
8584 case Mips::SUBU16_MM: {
8585 switch (OpNum) {
8586 case 0:
8587 // op: rd
8588 return 7;
8589 case 2:
8590 // op: rt
8591 return 4;
8592 case 1:
8593 // op: rs
8594 return 1;
8595 }
8596 break;
8597 }
8598 case Mips::JALR16_MM:
8599 case Mips::JALRS16_MM:
8600 case Mips::JR16_MM:
8601 case Mips::JRC16_MM: {
8602 switch (OpNum) {
8603 case 0:
8604 // op: rs
8605 return 0;
8606 }
8607 break;
8608 }
8609 case Mips::MFHI_DSP_MM:
8610 case Mips::MFLO_DSP_MM: {
8611 switch (OpNum) {
8612 case 0:
8613 // op: rs
8614 return 16;
8615 case 1:
8616 // op: ac
8617 return 14;
8618 }
8619 break;
8620 }
8621 case Mips::TEQI_MM:
8622 case Mips::TGEIU_MM:
8623 case Mips::TGEI_MM:
8624 case Mips::TLTIU_MM:
8625 case Mips::TLTI_MM:
8626 case Mips::TNEI_MM: {
8627 switch (OpNum) {
8628 case 0:
8629 // op: rs
8630 return 16;
8631 case 1:
8632 // op: imm16
8633 return 0;
8634 }
8635 break;
8636 }
8637 case Mips::BEQZC_MM:
8638 case Mips::BGEZALS_MM:
8639 case Mips::BGEZAL_MM:
8640 case Mips::BGEZ_MM:
8641 case Mips::BGTZ_MM:
8642 case Mips::BLEZ_MM:
8643 case Mips::BLTZALS_MM:
8644 case Mips::BLTZAL_MM:
8645 case Mips::BLTZ_MM:
8646 case Mips::BNEZC_MM: {
8647 switch (OpNum) {
8648 case 0:
8649 // op: rs
8650 return 16;
8651 case 1:
8652 // op: offset
8653 return 0;
8654 }
8655 break;
8656 }
8657 case Mips::TEQ_MM:
8658 case Mips::TGEU_MM:
8659 case Mips::TGE_MM:
8660 case Mips::TLTU_MM:
8661 case Mips::TLT_MM:
8662 case Mips::TNE_MM: {
8663 switch (OpNum) {
8664 case 0:
8665 // op: rs
8666 return 16;
8667 case 1:
8668 // op: rt
8669 return 21;
8670 case 2:
8671 // op: code_
8672 return 12;
8673 }
8674 break;
8675 }
8676 case Mips::BEQ_MM:
8677 case Mips::BNE_MM: {
8678 switch (OpNum) {
8679 case 0:
8680 // op: rs
8681 return 16;
8682 case 1:
8683 // op: rt
8684 return 21;
8685 case 2:
8686 // op: offset
8687 return 0;
8688 }
8689 break;
8690 }
8691 case Mips::MADDU_MM:
8692 case Mips::MADD_MM:
8693 case Mips::MSUBU_MM:
8694 case Mips::MSUB_MM:
8695 case Mips::MULT_MM:
8696 case Mips::MULTu_MM:
8697 case Mips::SDIV_MM:
8698 case Mips::UDIV_MM: {
8699 switch (OpNum) {
8700 case 0:
8701 // op: rs
8702 return 16;
8703 case 1:
8704 // op: rt
8705 return 21;
8706 }
8707 break;
8708 }
8709 case Mips::GINVT_MMR6: {
8710 switch (OpNum) {
8711 case 0:
8712 // op: rs
8713 return 16;
8714 case 1:
8715 // op: type
8716 return 9;
8717 }
8718 break;
8719 }
8720 case Mips::DVP_MMR6:
8721 case Mips::EVP_MMR6:
8722 case Mips::GINVI_MMR6:
8723 case Mips::JR_MM:
8724 case Mips::MTHI_MM:
8725 case Mips::MTLO_MM: {
8726 switch (OpNum) {
8727 case 0:
8728 // op: rs
8729 return 16;
8730 }
8731 break;
8732 }
8733 case Mips::ADDIUPC:
8734 case Mips::ALUIPC:
8735 case Mips::AUIPC:
8736 case Mips::LDPC:
8737 case Mips::LWPC:
8738 case Mips::LWUPC: {
8739 switch (OpNum) {
8740 case 0:
8741 // op: rs
8742 return 21;
8743 case 1:
8744 // op: imm
8745 return 0;
8746 }
8747 break;
8748 }
8749 case Mips::TEQI:
8750 case Mips::TGEI:
8751 case Mips::TGEIU:
8752 case Mips::TLTI:
8753 case Mips::TNEI:
8754 case Mips::TTLTIU: {
8755 switch (OpNum) {
8756 case 0:
8757 // op: rs
8758 return 21;
8759 case 1:
8760 // op: imm16
8761 return 0;
8762 }
8763 break;
8764 }
8765 case Mips::WRDSP: {
8766 switch (OpNum) {
8767 case 0:
8768 // op: rs
8769 return 21;
8770 case 1:
8771 // op: mask
8772 return 11;
8773 }
8774 break;
8775 }
8776 case Mips::BEQZC:
8777 case Mips::BEQZC64:
8778 case Mips::BEQZC_MMR6:
8779 case Mips::BGEZ:
8780 case Mips::BGEZ64:
8781 case Mips::BGEZAL:
8782 case Mips::BGEZALL:
8783 case Mips::BGEZL:
8784 case Mips::BGTZ:
8785 case Mips::BGTZ64:
8786 case Mips::BGTZL:
8787 case Mips::BLEZ:
8788 case Mips::BLEZ64:
8789 case Mips::BLEZL:
8790 case Mips::BLTZ:
8791 case Mips::BLTZ64:
8792 case Mips::BLTZAL:
8793 case Mips::BLTZALL:
8794 case Mips::BLTZL:
8795 case Mips::BNEZC:
8796 case Mips::BNEZC64:
8797 case Mips::BNEZC_MMR6: {
8798 switch (OpNum) {
8799 case 0:
8800 // op: rs
8801 return 21;
8802 case 1:
8803 // op: offset
8804 return 0;
8805 }
8806 break;
8807 }
8808 case Mips::BBIT0:
8809 case Mips::BBIT032:
8810 case Mips::BBIT1:
8811 case Mips::BBIT132: {
8812 switch (OpNum) {
8813 case 0:
8814 // op: rs
8815 return 21;
8816 case 1:
8817 // op: p
8818 return 16;
8819 case 2:
8820 // op: offset
8821 return 0;
8822 }
8823 break;
8824 }
8825 case Mips::TEQ:
8826 case Mips::TGE:
8827 case Mips::TGEU:
8828 case Mips::TLT:
8829 case Mips::TLTU:
8830 case Mips::TNE: {
8831 switch (OpNum) {
8832 case 0:
8833 // op: rs
8834 return 21;
8835 case 1:
8836 // op: rt
8837 return 16;
8838 case 2:
8839 // op: code_
8840 return 6;
8841 }
8842 break;
8843 }
8844 case Mips::BEQ:
8845 case Mips::BEQ64:
8846 case Mips::BEQC:
8847 case Mips::BEQC64:
8848 case Mips::BEQL:
8849 case Mips::BGEC:
8850 case Mips::BGEC64:
8851 case Mips::BGEUC:
8852 case Mips::BGEUC64:
8853 case Mips::BLTC:
8854 case Mips::BLTC64:
8855 case Mips::BLTUC:
8856 case Mips::BLTUC64:
8857 case Mips::BNE:
8858 case Mips::BNE64:
8859 case Mips::BNEC:
8860 case Mips::BNEC64:
8861 case Mips::BNEL:
8862 case Mips::BNVC:
8863 case Mips::BOVC: {
8864 switch (OpNum) {
8865 case 0:
8866 // op: rs
8867 return 21;
8868 case 1:
8869 // op: rt
8870 return 16;
8871 case 2:
8872 // op: offset
8873 return 0;
8874 }
8875 break;
8876 }
8877 case Mips::CMPU_EQ_QB:
8878 case Mips::CMPU_LE_QB:
8879 case Mips::CMPU_LT_QB:
8880 case Mips::CMP_EQ_PH:
8881 case Mips::CMP_LE_PH:
8882 case Mips::CMP_LT_PH:
8883 case Mips::DMULT:
8884 case Mips::DMULTu:
8885 case Mips::DSDIV:
8886 case Mips::DUDIV:
8887 case Mips::MADD:
8888 case Mips::MADDU:
8889 case Mips::MSUB:
8890 case Mips::MSUBU:
8891 case Mips::MULT:
8892 case Mips::MULTu:
8893 case Mips::SDIV:
8894 case Mips::UDIV: {
8895 switch (OpNum) {
8896 case 0:
8897 // op: rs
8898 return 21;
8899 case 1:
8900 // op: rt
8901 return 16;
8902 }
8903 break;
8904 }
8905 case Mips::GINVT: {
8906 switch (OpNum) {
8907 case 0:
8908 // op: rs
8909 return 21;
8910 case 1:
8911 // op: type_
8912 return 8;
8913 }
8914 break;
8915 }
8916 case Mips::DAHI:
8917 case Mips::DATI: {
8918 switch (OpNum) {
8919 case 0:
8920 // op: rs
8921 return 21;
8922 case 2:
8923 // op: imm
8924 return 0;
8925 }
8926 break;
8927 }
8928 case Mips::FORK: {
8929 switch (OpNum) {
8930 case 0:
8931 // op: rs
8932 return 21;
8933 case 2:
8934 // op: rt
8935 return 16;
8936 case 1:
8937 // op: rd
8938 return 11;
8939 }
8940 break;
8941 }
8942 case Mips::GINVI:
8943 case Mips::JR:
8944 case Mips::JR64:
8945 case Mips::JR_HB:
8946 case Mips::JR_HB64:
8947 case Mips::JR_HB64_R6:
8948 case Mips::JR_HB_R6:
8949 case Mips::MTHI:
8950 case Mips::MTHI64:
8951 case Mips::MTLO:
8952 case Mips::MTLO64:
8953 case Mips::MTM0:
8954 case Mips::MTM1:
8955 case Mips::MTM2:
8956 case Mips::MTP0:
8957 case Mips::MTP1:
8958 case Mips::MTP2: {
8959 switch (OpNum) {
8960 case 0:
8961 // op: rs
8962 return 21;
8963 }
8964 break;
8965 }
8966 case Mips::ADDIUPC_MM: {
8967 switch (OpNum) {
8968 case 0:
8969 // op: rs
8970 return 23;
8971 case 1:
8972 // op: imm
8973 return 0;
8974 }
8975 break;
8976 }
8977 case Mips::JALRC16_MMR6:
8978 case Mips::JRC16_MMR6: {
8979 switch (OpNum) {
8980 case 0:
8981 // op: rs
8982 return 5;
8983 }
8984 break;
8985 }
8986 case Mips::BEQZ16_MM:
8987 case Mips::BEQZC16_MMR6:
8988 case Mips::BNEZ16_MM:
8989 case Mips::BNEZC16_MMR6: {
8990 switch (OpNum) {
8991 case 0:
8992 // op: rs
8993 return 7;
8994 case 1:
8995 // op: offset
8996 return 0;
8997 }
8998 break;
8999 }
9000 case Mips::EXTP:
9001 case Mips::EXTPDP:
9002 case Mips::EXTPDPV:
9003 case Mips::EXTPV:
9004 case Mips::EXTRV_RS_W:
9005 case Mips::EXTRV_R_W:
9006 case Mips::EXTRV_S_H:
9007 case Mips::EXTRV_W:
9008 case Mips::EXTR_RS_W:
9009 case Mips::EXTR_R_W:
9010 case Mips::EXTR_S_H:
9011 case Mips::EXTR_W: {
9012 switch (OpNum) {
9013 case 0:
9014 // op: rt
9015 return 16;
9016 case 1:
9017 // op: ac
9018 return 11;
9019 case 2:
9020 // op: shift_rs
9021 return 21;
9022 }
9023 break;
9024 }
9025 case Mips::LB:
9026 case Mips::LB64:
9027 case Mips::LBu:
9028 case Mips::LBu64:
9029 case Mips::LD:
9030 case Mips::LDC1:
9031 case Mips::LDC164:
9032 case Mips::LDC2:
9033 case Mips::LDC2_R6:
9034 case Mips::LDC3:
9035 case Mips::LDL:
9036 case Mips::LDR:
9037 case Mips::LEA_ADDiu:
9038 case Mips::LEA_ADDiu64:
9039 case Mips::LH:
9040 case Mips::LH64:
9041 case Mips::LHu:
9042 case Mips::LHu64:
9043 case Mips::LL:
9044 case Mips::LL64:
9045 case Mips::LLD:
9046 case Mips::LW:
9047 case Mips::LW64:
9048 case Mips::LWC1:
9049 case Mips::LWC2:
9050 case Mips::LWC2_R6:
9051 case Mips::LWC3:
9052 case Mips::LWDSP:
9053 case Mips::LWL:
9054 case Mips::LWL64:
9055 case Mips::LWR:
9056 case Mips::LWR64:
9057 case Mips::LWu:
9058 case Mips::SB:
9059 case Mips::SB64:
9060 case Mips::SD:
9061 case Mips::SDC1:
9062 case Mips::SDC164:
9063 case Mips::SDC2:
9064 case Mips::SDC2_R6:
9065 case Mips::SDC3:
9066 case Mips::SDL:
9067 case Mips::SDR:
9068 case Mips::SH:
9069 case Mips::SH64:
9070 case Mips::SW:
9071 case Mips::SW64:
9072 case Mips::SWC1:
9073 case Mips::SWC2:
9074 case Mips::SWC2_R6:
9075 case Mips::SWC3:
9076 case Mips::SWDSP:
9077 case Mips::SWL:
9078 case Mips::SWL64:
9079 case Mips::SWR:
9080 case Mips::SWR64: {
9081 switch (OpNum) {
9082 case 0:
9083 // op: rt
9084 return 16;
9085 case 1:
9086 // op: addr
9087 return 0;
9088 }
9089 break;
9090 }
9091 case Mips::LL64_R6:
9092 case Mips::LLD_R6:
9093 case Mips::LL_R6: {
9094 switch (OpNum) {
9095 case 0:
9096 // op: rt
9097 return 16;
9098 case 1:
9099 // op: addr
9100 return 7;
9101 }
9102 break;
9103 }
9104 case Mips::CFC1:
9105 case Mips::DMFC1:
9106 case Mips::MFC1:
9107 case Mips::MFC1_D64:
9108 case Mips::MFHC1_D32:
9109 case Mips::MFHC1_D64: {
9110 switch (OpNum) {
9111 case 0:
9112 // op: rt
9113 return 16;
9114 case 1:
9115 // op: fs
9116 return 11;
9117 }
9118 break;
9119 }
9120 case Mips::DMFC2_OCTEON:
9121 case Mips::DMTC2_OCTEON:
9122 case Mips::LUi:
9123 case Mips::LUi64:
9124 case Mips::LUi_MM: {
9125 switch (OpNum) {
9126 case 0:
9127 // op: rt
9128 return 16;
9129 case 1:
9130 // op: imm16
9131 return 0;
9132 }
9133 break;
9134 }
9135 case Mips::BC1EQZC_MMR6:
9136 case Mips::BC1NEZC_MMR6:
9137 case Mips::BC2EQZC_MMR6:
9138 case Mips::BC2NEZC_MMR6:
9139 case Mips::BEQZALC:
9140 case Mips::BGEZALC:
9141 case Mips::BGEZALC_MMR6:
9142 case Mips::BGEZC:
9143 case Mips::BGEZC64:
9144 case Mips::BGEZC_MMR6:
9145 case Mips::BGTZALC:
9146 case Mips::BGTZC:
9147 case Mips::BGTZC64:
9148 case Mips::BLEZALC:
9149 case Mips::BLEZC:
9150 case Mips::BLEZC64:
9151 case Mips::BLTZALC:
9152 case Mips::BLTZALC_MMR6:
9153 case Mips::BLTZC:
9154 case Mips::BLTZC64:
9155 case Mips::BLTZC_MMR6:
9156 case Mips::BNEZALC:
9157 case Mips::JIALC:
9158 case Mips::JIALC64:
9159 case Mips::JIALC_MMR6:
9160 case Mips::JIC:
9161 case Mips::JIC64:
9162 case Mips::JIC_MMR6: {
9163 switch (OpNum) {
9164 case 0:
9165 // op: rt
9166 return 16;
9167 case 1:
9168 // op: offset
9169 return 0;
9170 }
9171 break;
9172 }
9173 case Mips::DMFC0:
9174 case Mips::DMFC2:
9175 case Mips::DMFGC0:
9176 case Mips::MFC0:
9177 case Mips::MFC2:
9178 case Mips::MFGC0:
9179 case Mips::MFHGC0: {
9180 switch (OpNum) {
9181 case 0:
9182 // op: rt
9183 return 16;
9184 case 1:
9185 // op: rd
9186 return 11;
9187 case 2:
9188 // op: sel
9189 return 0;
9190 }
9191 break;
9192 }
9193 case Mips::RDHWR:
9194 case Mips::RDHWR64: {
9195 switch (OpNum) {
9196 case 0:
9197 // op: rt
9198 return 16;
9199 case 1:
9200 // op: rd
9201 return 11;
9202 case 2:
9203 // op: sel
9204 return 6;
9205 }
9206 break;
9207 }
9208 case Mips::SLTi:
9209 case Mips::SLTi64:
9210 case Mips::SLTiu:
9211 case Mips::SLTiu64: {
9212 switch (OpNum) {
9213 case 0:
9214 // op: rt
9215 return 16;
9216 case 1:
9217 // op: rs
9218 return 21;
9219 case 2:
9220 // op: imm16
9221 return 0;
9222 }
9223 break;
9224 }
9225 case Mips::CINS:
9226 case Mips::CINS32:
9227 case Mips::CINS64_32:
9228 case Mips::CINS_i32:
9229 case Mips::EXTS:
9230 case Mips::EXTS32: {
9231 switch (OpNum) {
9232 case 0:
9233 // op: rt
9234 return 16;
9235 case 1:
9236 // op: rs
9237 return 21;
9238 case 2:
9239 // op: pos
9240 return 6;
9241 case 3:
9242 // op: lenm1
9243 return 11;
9244 }
9245 break;
9246 }
9247 case Mips::DEXT:
9248 case Mips::DEXT64_32:
9249 case Mips::DEXTM:
9250 case Mips::DEXTU:
9251 case Mips::DINS:
9252 case Mips::DINSM:
9253 case Mips::DINSU:
9254 case Mips::EXT:
9255 case Mips::INS: {
9256 switch (OpNum) {
9257 case 0:
9258 // op: rt
9259 return 16;
9260 case 1:
9261 // op: rs
9262 return 21;
9263 case 2:
9264 // op: pos
9265 return 6;
9266 case 3:
9267 // op: size
9268 return 11;
9269 }
9270 break;
9271 }
9272 case Mips::APPEND:
9273 case Mips::BALIGN:
9274 case Mips::PREPEND: {
9275 switch (OpNum) {
9276 case 0:
9277 // op: rt
9278 return 16;
9279 case 1:
9280 // op: rs
9281 return 21;
9282 case 2:
9283 // op: sa
9284 return 11;
9285 }
9286 break;
9287 }
9288 case Mips::SAA:
9289 case Mips::SAAD: {
9290 switch (OpNum) {
9291 case 0:
9292 // op: rt
9293 return 16;
9294 case 1:
9295 // op: rs
9296 return 21;
9297 }
9298 break;
9299 }
9300 case Mips::INSV: {
9301 switch (OpNum) {
9302 case 0:
9303 // op: rt
9304 return 16;
9305 case 2:
9306 // op: rs
9307 return 21;
9308 }
9309 break;
9310 }
9311 case Mips::DI:
9312 case Mips::DI_MM:
9313 case Mips::DI_MMR6:
9314 case Mips::DMT:
9315 case Mips::DVP:
9316 case Mips::DVPE:
9317 case Mips::EI:
9318 case Mips::EI_MM:
9319 case Mips::EI_MMR6:
9320 case Mips::EMT:
9321 case Mips::EVP:
9322 case Mips::EVPE: {
9323 switch (OpNum) {
9324 case 0:
9325 // op: rt
9326 return 16;
9327 }
9328 break;
9329 }
9330 case Mips::LBE_MM:
9331 case Mips::LB_MM:
9332 case Mips::LBuE_MM:
9333 case Mips::LBu_MM:
9334 case Mips::LDC1_MM_D32:
9335 case Mips::LDC1_MM_D64:
9336 case Mips::LDC2_MMR6:
9337 case Mips::LEA_ADDiu_MM:
9338 case Mips::LHE_MM:
9339 case Mips::LH_MM:
9340 case Mips::LHuE_MM:
9341 case Mips::LHu_MM:
9342 case Mips::LLE_MM:
9343 case Mips::LL_MM:
9344 case Mips::LL_MMR6:
9345 case Mips::LWC1_MM:
9346 case Mips::LWC2_MMR6:
9347 case Mips::LWDSP_MM:
9348 case Mips::LWE_MM:
9349 case Mips::LWLE_MM:
9350 case Mips::LWL_MM:
9351 case Mips::LWM32_MM:
9352 case Mips::LWRE_MM:
9353 case Mips::LWR_MM:
9354 case Mips::LWU_MM:
9355 case Mips::LW_MM:
9356 case Mips::LW_MMR6:
9357 case Mips::SBE_MM:
9358 case Mips::SB_MM:
9359 case Mips::SB_MMR6:
9360 case Mips::SDC1_MM_D32:
9361 case Mips::SDC1_MM_D64:
9362 case Mips::SDC2_MMR6:
9363 case Mips::SHE_MM:
9364 case Mips::SH_MM:
9365 case Mips::SH_MMR6:
9366 case Mips::SWC1_MM:
9367 case Mips::SWC2_MMR6:
9368 case Mips::SWDSP_MM:
9369 case Mips::SWE_MM:
9370 case Mips::SWLE_MM:
9371 case Mips::SWL_MM:
9372 case Mips::SWM32_MM:
9373 case Mips::SWRE_MM:
9374 case Mips::SWR_MM:
9375 case Mips::SW_MM:
9376 case Mips::SW_MMR6: {
9377 switch (OpNum) {
9378 case 0:
9379 // op: rt
9380 return 21;
9381 case 1:
9382 // op: addr
9383 return 0;
9384 }
9385 break;
9386 }
9387 case Mips::CFC1_MM:
9388 case Mips::MFC1_MM:
9389 case Mips::MFC1_MMR6:
9390 case Mips::MFHC1_D32_MM:
9391 case Mips::MFHC1_D64_MM: {
9392 switch (OpNum) {
9393 case 0:
9394 // op: rt
9395 return 21;
9396 case 1:
9397 // op: fs
9398 return 16;
9399 }
9400 break;
9401 }
9402 case Mips::ADDIUPC_MMR6:
9403 case Mips::ALUIPC_MMR6:
9404 case Mips::AUIPC_MMR6:
9405 case Mips::LWPC_MMR6: {
9406 switch (OpNum) {
9407 case 0:
9408 // op: rt
9409 return 21;
9410 case 1:
9411 // op: imm
9412 return 0;
9413 }
9414 break;
9415 }
9416 case Mips::REPL_QB_MM: {
9417 switch (OpNum) {
9418 case 0:
9419 // op: rt
9420 return 21;
9421 case 1:
9422 // op: imm
9423 return 13;
9424 }
9425 break;
9426 }
9427 case Mips::LUI_MMR6: {
9428 switch (OpNum) {
9429 case 0:
9430 // op: rt
9431 return 21;
9432 case 1:
9433 // op: imm16
9434 return 0;
9435 }
9436 break;
9437 }
9438 case Mips::CFC2_MM:
9439 case Mips::MFC2_MMR6:
9440 case Mips::MFHC2_MMR6: {
9441 switch (OpNum) {
9442 case 0:
9443 // op: rt
9444 return 21;
9445 case 1:
9446 // op: impl
9447 return 16;
9448 }
9449 break;
9450 }
9451 case Mips::RDDSP_MM:
9452 case Mips::WRDSP_MM: {
9453 switch (OpNum) {
9454 case 0:
9455 // op: rt
9456 return 21;
9457 case 1:
9458 // op: mask
9459 return 14;
9460 }
9461 break;
9462 }
9463 case Mips::BEQZALC_MMR6:
9464 case Mips::BGTZALC_MMR6:
9465 case Mips::BGTZC_MMR6:
9466 case Mips::BLEZALC_MMR6:
9467 case Mips::BLEZC_MMR6:
9468 case Mips::BNEZALC_MMR6: {
9469 switch (OpNum) {
9470 case 0:
9471 // op: rt
9472 return 21;
9473 case 1:
9474 // op: offset
9475 return 0;
9476 }
9477 break;
9478 }
9479 case Mips::RDHWR_MM:
9480 case Mips::RDPGPR_MMR6: {
9481 switch (OpNum) {
9482 case 0:
9483 // op: rt
9484 return 21;
9485 case 1:
9486 // op: rd
9487 return 16;
9488 }
9489 break;
9490 }
9491 case Mips::BALIGN_MMR2: {
9492 switch (OpNum) {
9493 case 0:
9494 // op: rt
9495 return 21;
9496 case 1:
9497 // op: rs
9498 return 16;
9499 case 2:
9500 // op: bp
9501 return 14;
9502 }
9503 break;
9504 }
9505 case Mips::ADDIU_MMR6:
9506 case Mips::ANDI_MMR6:
9507 case Mips::ORI_MMR6:
9508 case Mips::SLTi_MM:
9509 case Mips::SLTiu_MM:
9510 case Mips::XORI_MMR6: {
9511 switch (OpNum) {
9512 case 0:
9513 // op: rt
9514 return 21;
9515 case 1:
9516 // op: rs
9517 return 16;
9518 case 2:
9519 // op: imm16
9520 return 0;
9521 }
9522 break;
9523 }
9524 case Mips::BNVC_MMR6:
9525 case Mips::BOVC_MMR6: {
9526 switch (OpNum) {
9527 case 0:
9528 // op: rt
9529 return 21;
9530 case 1:
9531 // op: rs
9532 return 16;
9533 case 2:
9534 // op: offset
9535 return 0;
9536 }
9537 break;
9538 }
9539 case Mips::EXT_MM:
9540 case Mips::INS_MM: {
9541 switch (OpNum) {
9542 case 0:
9543 // op: rt
9544 return 21;
9545 case 1:
9546 // op: rs
9547 return 16;
9548 case 2:
9549 // op: pos
9550 return 6;
9551 case 3:
9552 // op: size
9553 return 11;
9554 }
9555 break;
9556 }
9557 case Mips::APPEND_MMR2:
9558 case Mips::PRECR_SRA_PH_W_MMR2:
9559 case Mips::PRECR_SRA_R_PH_W_MMR2:
9560 case Mips::PREPEND_MMR2:
9561 case Mips::SHLL_S_W_MM:
9562 case Mips::SHRA_R_W_MM: {
9563 switch (OpNum) {
9564 case 0:
9565 // op: rt
9566 return 21;
9567 case 1:
9568 // op: rs
9569 return 16;
9570 case 2:
9571 // op: sa
9572 return 11;
9573 }
9574 break;
9575 }
9576 case Mips::SHLL_PH_MM:
9577 case Mips::SHLL_S_PH_MM:
9578 case Mips::SHRA_PH_MM:
9579 case Mips::SHRA_R_PH_MM:
9580 case Mips::SHRL_PH_MMR2: {
9581 switch (OpNum) {
9582 case 0:
9583 // op: rt
9584 return 21;
9585 case 1:
9586 // op: rs
9587 return 16;
9588 case 2:
9589 // op: sa
9590 return 12;
9591 }
9592 break;
9593 }
9594 case Mips::SHLL_QB_MM:
9595 case Mips::SHRA_QB_MMR2:
9596 case Mips::SHRA_R_QB_MMR2:
9597 case Mips::SHRL_QB_MM: {
9598 switch (OpNum) {
9599 case 0:
9600 // op: rt
9601 return 21;
9602 case 1:
9603 // op: rs
9604 return 16;
9605 case 2:
9606 // op: sa
9607 return 13;
9608 }
9609 break;
9610 }
9611 case Mips::MFC0_MMR6:
9612 case Mips::MFGC0_MM:
9613 case Mips::MFHC0_MMR6:
9614 case Mips::MFHGC0_MM:
9615 case Mips::RDHWR_MMR6: {
9616 switch (OpNum) {
9617 case 0:
9618 // op: rt
9619 return 21;
9620 case 1:
9621 // op: rs
9622 return 16;
9623 case 2:
9624 // op: sel
9625 return 11;
9626 }
9627 break;
9628 }
9629 case Mips::EXT_MMR6:
9630 case Mips::INS_MMR6: {
9631 switch (OpNum) {
9632 case 0:
9633 // op: rt
9634 return 21;
9635 case 1:
9636 // op: rs
9637 return 16;
9638 case 3:
9639 // op: size
9640 return 11;
9641 case 2:
9642 // op: pos
9643 return 6;
9644 }
9645 break;
9646 }
9647 case Mips::ABSQ_S_PH_MM:
9648 case Mips::ABSQ_S_QB_MMR2:
9649 case Mips::ABSQ_S_W_MM:
9650 case Mips::BITREV_MM:
9651 case Mips::JALRC_HB_MMR6:
9652 case Mips::JALRC_MMR6:
9653 case Mips::PRECEQU_PH_QBLA_MM:
9654 case Mips::PRECEQU_PH_QBL_MM:
9655 case Mips::PRECEQU_PH_QBRA_MM:
9656 case Mips::PRECEQU_PH_QBR_MM:
9657 case Mips::PRECEQ_W_PHL_MM:
9658 case Mips::PRECEQ_W_PHR_MM:
9659 case Mips::PRECEU_PH_QBLA_MM:
9660 case Mips::PRECEU_PH_QBL_MM:
9661 case Mips::PRECEU_PH_QBRA_MM:
9662 case Mips::PRECEU_PH_QBR_MM:
9663 case Mips::RADDU_W_QB_MM:
9664 case Mips::REPLV_PH_MM:
9665 case Mips::REPLV_QB_MM:
9666 case Mips::WRPGPR_MMR6:
9667 case Mips::WSBH_MMR6: {
9668 switch (OpNum) {
9669 case 0:
9670 // op: rt
9671 return 21;
9672 case 1:
9673 // op: rs
9674 return 16;
9675 }
9676 break;
9677 }
9678 case Mips::LWP_MM:
9679 case Mips::SWP_MM: {
9680 switch (OpNum) {
9681 case 0:
9682 // op: rt
9683 return 21;
9684 case 2:
9685 // op: addr
9686 return 0;
9687 }
9688 break;
9689 }
9690 case Mips::EXTPDP_MM:
9691 case Mips::EXTP_MM:
9692 case Mips::EXTR_RS_W_MM:
9693 case Mips::EXTR_R_W_MM:
9694 case Mips::EXTR_S_H_MM:
9695 case Mips::EXTR_W_MM: {
9696 switch (OpNum) {
9697 case 0:
9698 // op: rt
9699 return 21;
9700 case 2:
9701 // op: imm
9702 return 16;
9703 case 1:
9704 // op: ac
9705 return 14;
9706 }
9707 break;
9708 }
9709 case Mips::EXTPDPV_MM:
9710 case Mips::EXTPV_MM:
9711 case Mips::EXTRV_RS_W_MM:
9712 case Mips::EXTRV_R_W_MM:
9713 case Mips::EXTRV_S_H_MM:
9714 case Mips::EXTRV_W_MM: {
9715 switch (OpNum) {
9716 case 0:
9717 // op: rt
9718 return 21;
9719 case 2:
9720 // op: rs
9721 return 16;
9722 case 1:
9723 // op: ac
9724 return 14;
9725 }
9726 break;
9727 }
9728 case Mips::INSV_MM: {
9729 switch (OpNum) {
9730 case 0:
9731 // op: rt
9732 return 21;
9733 case 2:
9734 // op: rs
9735 return 16;
9736 }
9737 break;
9738 }
9739 case Mips::NOT16_MM: {
9740 switch (OpNum) {
9741 case 0:
9742 // op: rt
9743 return 3;
9744 case 1:
9745 // op: rs
9746 return 0;
9747 }
9748 break;
9749 }
9750 case Mips::LWM16_MM:
9751 case Mips::SWM16_MM: {
9752 switch (OpNum) {
9753 case 0:
9754 // op: rt
9755 return 4;
9756 case 1:
9757 // op: addr
9758 return 0;
9759 }
9760 break;
9761 }
9762 case Mips::LWSP_MM:
9763 case Mips::SWSP_MM:
9764 case Mips::SWSP_MMR6: {
9765 switch (OpNum) {
9766 case 0:
9767 // op: rt
9768 return 5;
9769 case 1:
9770 // op: offset
9771 return 0;
9772 }
9773 break;
9774 }
9775 case Mips::LBU16_MM:
9776 case Mips::LHU16_MM:
9777 case Mips::LW16_MM:
9778 case Mips::SB16_MM:
9779 case Mips::SB16_MMR6:
9780 case Mips::SH16_MM:
9781 case Mips::SH16_MMR6:
9782 case Mips::SW16_MM:
9783 case Mips::SW16_MMR6: {
9784 switch (OpNum) {
9785 case 0:
9786 // op: rt
9787 return 7;
9788 case 1:
9789 // op: addr
9790 return 0;
9791 }
9792 break;
9793 }
9794 case Mips::LWGP_MM: {
9795 switch (OpNum) {
9796 case 0:
9797 // op: rt
9798 return 7;
9799 case 1:
9800 // op: offset
9801 return 0;
9802 }
9803 break;
9804 }
9805 case Mips::NOT16_MMR6: {
9806 switch (OpNum) {
9807 case 0:
9808 // op: rt
9809 return 7;
9810 case 1:
9811 // op: rs
9812 return 4;
9813 }
9814 break;
9815 }
9816 case Mips::LWM16_MMR6:
9817 case Mips::SWM16_MMR6: {
9818 switch (OpNum) {
9819 case 0:
9820 // op: rt
9821 return 8;
9822 case 1:
9823 // op: addr
9824 return 4;
9825 }
9826 break;
9827 }
9828 case Mips::BeqzRxImm16:
9829 case Mips::BnezRxImm16:
9830 case Mips::CmpiRxImm16:
9831 case Mips::LiRxImm16:
9832 case Mips::LwRxPcTcp16:
9833 case Mips::SltiRxImm16:
9834 case Mips::SltiuRxImm16: {
9835 switch (OpNum) {
9836 case 0:
9837 // op: rx
9838 return 8;
9839 case 1:
9840 // op: imm8
9841 return 0;
9842 }
9843 break;
9844 }
9845 case Mips::CmpRxRy16:
9846 case Mips::DivRxRy16:
9847 case Mips::DivuRxRy16:
9848 case Mips::NegRxRy16:
9849 case Mips::NotRxRy16:
9850 case Mips::SltRxRy16:
9851 case Mips::SltuRxRy16: {
9852 switch (OpNum) {
9853 case 0:
9854 // op: rx
9855 return 8;
9856 case 1:
9857 // op: ry
9858 return 5;
9859 }
9860 break;
9861 }
9862 case Mips::AddiuRxRxImm16: {
9863 switch (OpNum) {
9864 case 0:
9865 // op: rx
9866 return 8;
9867 case 2:
9868 // op: imm8
9869 return 0;
9870 }
9871 break;
9872 }
9873 case Mips::JrcRx16:
9874 case Mips::JumpLinkReg16:
9875 case Mips::Mfhi16:
9876 case Mips::Mflo16:
9877 case Mips::SebRx16:
9878 case Mips::SehRx16: {
9879 switch (OpNum) {
9880 case 0:
9881 // op: rx
9882 return 8;
9883 }
9884 break;
9885 }
9886 case Mips::MoveR3216: {
9887 switch (OpNum) {
9888 case 0:
9889 // op: ry
9890 return 4;
9891 case 1:
9892 // op: r32
9893 return 0;
9894 }
9895 break;
9896 }
9897 case Mips::SYNC_MM:
9898 case Mips::SYNC_MMR6: {
9899 switch (OpNum) {
9900 case 0:
9901 // op: stype
9902 return 16;
9903 }
9904 break;
9905 }
9906 case Mips::SYNC: {
9907 switch (OpNum) {
9908 case 0:
9909 // op: stype
9910 return 6;
9911 }
9912 break;
9913 }
9914 case Mips::J:
9915 case Mips::JAL:
9916 case Mips::JALS_MM:
9917 case Mips::JALX:
9918 case Mips::JALX_MM:
9919 case Mips::JAL_MM:
9920 case Mips::J_MM: {
9921 switch (OpNum) {
9922 case 0:
9923 // op: target
9924 return 0;
9925 }
9926 break;
9927 }
9928 case Mips::LBU_MMR6:
9929 case Mips::LB_MMR6: {
9930 switch (OpNum) {
9931 case 1:
9932 // op: addr
9933 return 0;
9934 case 0:
9935 // op: rt
9936 return 21;
9937 }
9938 break;
9939 }
9940 case Mips::LD_B:
9941 case Mips::LD_D:
9942 case Mips::LD_H:
9943 case Mips::LD_W:
9944 case Mips::ST_B:
9945 case Mips::ST_D:
9946 case Mips::ST_H:
9947 case Mips::ST_W: {
9948 switch (OpNum) {
9949 case 1:
9950 // op: addr
9951 return 11;
9952 case 0:
9953 // op: wd
9954 return 6;
9955 }
9956 break;
9957 }
9958 case Mips::LBE:
9959 case Mips::LBuE:
9960 case Mips::LHE:
9961 case Mips::LHuE:
9962 case Mips::LLE:
9963 case Mips::LWE:
9964 case Mips::LWLE:
9965 case Mips::LWRE:
9966 case Mips::SBE:
9967 case Mips::SHE:
9968 case Mips::SWE:
9969 case Mips::SWLE:
9970 case Mips::SWRE: {
9971 switch (OpNum) {
9972 case 1:
9973 // op: addr
9974 return 7;
9975 case 0:
9976 // op: rt
9977 return 16;
9978 }
9979 break;
9980 }
9981 case Mips::CLASS_D:
9982 case Mips::CLASS_S:
9983 case Mips::RINT_D:
9984 case Mips::RINT_S: {
9985 switch (OpNum) {
9986 case 1:
9987 // op: fs
9988 return 11;
9989 case 0:
9990 // op: fd
9991 return 6;
9992 }
9993 break;
9994 }
9995 case Mips::C_EQ_D32:
9996 case Mips::C_EQ_D64:
9997 case Mips::C_EQ_S:
9998 case Mips::C_F_D32:
9999 case Mips::C_F_D64:
10000 case Mips::C_F_S:
10001 case Mips::C_LE_D32:
10002 case Mips::C_LE_D64:
10003 case Mips::C_LE_S:
10004 case Mips::C_LT_D32:
10005 case Mips::C_LT_D64:
10006 case Mips::C_LT_S:
10007 case Mips::C_NGE_D32:
10008 case Mips::C_NGE_D64:
10009 case Mips::C_NGE_S:
10010 case Mips::C_NGLE_D32:
10011 case Mips::C_NGLE_D64:
10012 case Mips::C_NGLE_S:
10013 case Mips::C_NGL_D32:
10014 case Mips::C_NGL_D64:
10015 case Mips::C_NGL_S:
10016 case Mips::C_NGT_D32:
10017 case Mips::C_NGT_D64:
10018 case Mips::C_NGT_S:
10019 case Mips::C_OLE_D32:
10020 case Mips::C_OLE_D64:
10021 case Mips::C_OLE_S:
10022 case Mips::C_OLT_D32:
10023 case Mips::C_OLT_D64:
10024 case Mips::C_OLT_S:
10025 case Mips::C_SEQ_D32:
10026 case Mips::C_SEQ_D64:
10027 case Mips::C_SEQ_S:
10028 case Mips::C_SF_D32:
10029 case Mips::C_SF_D64:
10030 case Mips::C_SF_S:
10031 case Mips::C_UEQ_D32:
10032 case Mips::C_UEQ_D64:
10033 case Mips::C_UEQ_S:
10034 case Mips::C_ULE_D32:
10035 case Mips::C_ULE_D64:
10036 case Mips::C_ULE_S:
10037 case Mips::C_ULT_D32:
10038 case Mips::C_ULT_D64:
10039 case Mips::C_ULT_S:
10040 case Mips::C_UN_D32:
10041 case Mips::C_UN_D64:
10042 case Mips::C_UN_S: {
10043 switch (OpNum) {
10044 case 1:
10045 // op: fs
10046 return 11;
10047 case 2:
10048 // op: ft
10049 return 16;
10050 case 0:
10051 // op: fcc
10052 return 8;
10053 }
10054 break;
10055 }
10056 case Mips::C_EQ_D32_MM:
10057 case Mips::C_EQ_D64_MM:
10058 case Mips::C_EQ_S_MM:
10059 case Mips::C_F_D32_MM:
10060 case Mips::C_F_D64_MM:
10061 case Mips::C_F_S_MM:
10062 case Mips::C_LE_D32_MM:
10063 case Mips::C_LE_D64_MM:
10064 case Mips::C_LE_S_MM:
10065 case Mips::C_LT_D32_MM:
10066 case Mips::C_LT_D64_MM:
10067 case Mips::C_LT_S_MM:
10068 case Mips::C_NGE_D32_MM:
10069 case Mips::C_NGE_D64_MM:
10070 case Mips::C_NGE_S_MM:
10071 case Mips::C_NGLE_D32_MM:
10072 case Mips::C_NGLE_D64_MM:
10073 case Mips::C_NGLE_S_MM:
10074 case Mips::C_NGL_D32_MM:
10075 case Mips::C_NGL_D64_MM:
10076 case Mips::C_NGL_S_MM:
10077 case Mips::C_NGT_D32_MM:
10078 case Mips::C_NGT_D64_MM:
10079 case Mips::C_NGT_S_MM:
10080 case Mips::C_OLE_D32_MM:
10081 case Mips::C_OLE_D64_MM:
10082 case Mips::C_OLE_S_MM:
10083 case Mips::C_OLT_D32_MM:
10084 case Mips::C_OLT_D64_MM:
10085 case Mips::C_OLT_S_MM:
10086 case Mips::C_SEQ_D32_MM:
10087 case Mips::C_SEQ_D64_MM:
10088 case Mips::C_SEQ_S_MM:
10089 case Mips::C_SF_D32_MM:
10090 case Mips::C_SF_D64_MM:
10091 case Mips::C_SF_S_MM:
10092 case Mips::C_UEQ_D32_MM:
10093 case Mips::C_UEQ_D64_MM:
10094 case Mips::C_UEQ_S_MM:
10095 case Mips::C_ULE_D32_MM:
10096 case Mips::C_ULE_D64_MM:
10097 case Mips::C_ULE_S_MM:
10098 case Mips::C_ULT_D32_MM:
10099 case Mips::C_ULT_D64_MM:
10100 case Mips::C_ULT_S_MM:
10101 case Mips::C_UN_D32_MM:
10102 case Mips::C_UN_D64_MM:
10103 case Mips::C_UN_S_MM: {
10104 switch (OpNum) {
10105 case 1:
10106 // op: fs
10107 return 16;
10108 case 2:
10109 // op: ft
10110 return 21;
10111 case 0:
10112 // op: fcc
10113 return 13;
10114 }
10115 break;
10116 }
10117 case Mips::CLASS_D_MMR6:
10118 case Mips::CLASS_S_MMR6:
10119 case Mips::RINT_D_MMR6:
10120 case Mips::RINT_S_MMR6: {
10121 switch (OpNum) {
10122 case 1:
10123 // op: fs
10124 return 21;
10125 case 0:
10126 // op: fd
10127 return 16;
10128 }
10129 break;
10130 }
10131 case Mips::FADD_S_MMR6:
10132 case Mips::FDIV_S_MMR6:
10133 case Mips::FMUL_S_MMR6:
10134 case Mips::FSUB_S_MMR6: {
10135 switch (OpNum) {
10136 case 1:
10137 // op: ft
10138 return 21;
10139 case 2:
10140 // op: fs
10141 return 16;
10142 case 0:
10143 // op: fd
10144 return 11;
10145 }
10146 break;
10147 }
10148 case Mips::AddiuRxImmX16:
10149 case Mips::AddiuRxPcImmX16:
10150 case Mips::BeqzRxImmX16:
10151 case Mips::BnezRxImmX16:
10152 case Mips::CmpiRxImmX16:
10153 case Mips::LiRxImmAlignX16:
10154 case Mips::LiRxImmX16:
10155 case Mips::LwRxPcTcpX16:
10156 case Mips::SltiRxImmX16:
10157 case Mips::SltiuRxImmX16: {
10158 switch (OpNum) {
10159 case 1:
10160 // op: imm16
10161 return 0;
10162 case 0:
10163 // op: rx
10164 return 8;
10165 }
10166 break;
10167 }
10168 case Mips::PREFX_MM: {
10169 switch (OpNum) {
10170 case 1:
10171 // op: index
10172 return 21;
10173 case 0:
10174 // op: base
10175 return 16;
10176 case 2:
10177 // op: hint
10178 return 11;
10179 }
10180 break;
10181 }
10182 case Mips::BNZ_B:
10183 case Mips::BNZ_D:
10184 case Mips::BNZ_H:
10185 case Mips::BNZ_V:
10186 case Mips::BNZ_W:
10187 case Mips::BZ_B:
10188 case Mips::BZ_D:
10189 case Mips::BZ_H:
10190 case Mips::BZ_V:
10191 case Mips::BZ_W: {
10192 switch (OpNum) {
10193 case 1:
10194 // op: offset
10195 return 0;
10196 case 0:
10197 // op: wt
10198 return 16;
10199 }
10200 break;
10201 }
10202 case Mips::ADDIUS5_MM: {
10203 switch (OpNum) {
10204 case 1:
10205 // op: rd
10206 return 5;
10207 case 2:
10208 // op: imm
10209 return 1;
10210 }
10211 break;
10212 }
10213 case Mips::MOVE16_MM:
10214 case Mips::MOVE16_MMR6: {
10215 switch (OpNum) {
10216 case 1:
10217 // op: rs
10218 return 0;
10219 case 0:
10220 // op: rd
10221 return 5;
10222 }
10223 break;
10224 }
10225 case Mips::CTCMSA: {
10226 switch (OpNum) {
10227 case 1:
10228 // op: rs
10229 return 11;
10230 case 0:
10231 // op: cd
10232 return 6;
10233 }
10234 break;
10235 }
10236 case Mips::FILL_B:
10237 case Mips::FILL_D:
10238 case Mips::FILL_H:
10239 case Mips::FILL_W: {
10240 switch (OpNum) {
10241 case 1:
10242 // op: rs
10243 return 11;
10244 case 0:
10245 // op: wd
10246 return 6;
10247 }
10248 break;
10249 }
10250 case Mips::MTHI_DSP_MM:
10251 case Mips::MTHLIP_MM:
10252 case Mips::MTLO_DSP_MM:
10253 case Mips::SHILOV_MM: {
10254 switch (OpNum) {
10255 case 1:
10256 // op: rs
10257 return 16;
10258 case 0:
10259 // op: ac
10260 return 14;
10261 }
10262 break;
10263 }
10264 case Mips::JALRS_MM:
10265 case Mips::JALR_MM: {
10266 switch (OpNum) {
10267 case 1:
10268 // op: rs
10269 return 16;
10270 case 0:
10271 // op: rd
10272 return 21;
10273 }
10274 break;
10275 }
10276 case Mips::AUI_MMR6: {
10277 switch (OpNum) {
10278 case 1:
10279 // op: rs
10280 return 16;
10281 case 0:
10282 // op: rt
10283 return 21;
10284 case 2:
10285 // op: imm
10286 return 0;
10287 }
10288 break;
10289 }
10290 case Mips::ADDi_MM:
10291 case Mips::ADDiu_MM:
10292 case Mips::ANDi_MM:
10293 case Mips::ORi_MM:
10294 case Mips::XORi_MM: {
10295 switch (OpNum) {
10296 case 1:
10297 // op: rs
10298 return 16;
10299 case 0:
10300 // op: rt
10301 return 21;
10302 case 2:
10303 // op: imm16
10304 return 0;
10305 }
10306 break;
10307 }
10308 case Mips::CLO_MMR6: {
10309 switch (OpNum) {
10310 case 1:
10311 // op: rs
10312 return 16;
10313 case 0:
10314 // op: rt
10315 return 21;
10316 }
10317 break;
10318 }
10319 case Mips::MTHI_DSP:
10320 case Mips::MTLO_DSP: {
10321 switch (OpNum) {
10322 case 1:
10323 // op: rs
10324 return 21;
10325 case 0:
10326 // op: ac
10327 return 11;
10328 }
10329 break;
10330 }
10331 case Mips::YIELD: {
10332 switch (OpNum) {
10333 case 1:
10334 // op: rs
10335 return 21;
10336 case 0:
10337 // op: rd
10338 return 11;
10339 }
10340 break;
10341 }
10342 case Mips::CLZ_MMR6: {
10343 switch (OpNum) {
10344 case 1:
10345 // op: rs
10346 return 21;
10347 case 0:
10348 // op: rt
10349 return 11;
10350 }
10351 break;
10352 }
10353 case Mips::AUI:
10354 case Mips::DAUI: {
10355 switch (OpNum) {
10356 case 1:
10357 // op: rs
10358 return 21;
10359 case 0:
10360 // op: rt
10361 return 16;
10362 case 2:
10363 // op: imm
10364 return 0;
10365 }
10366 break;
10367 }
10368 case Mips::SEQi:
10369 case Mips::SNEi: {
10370 switch (OpNum) {
10371 case 1:
10372 // op: rs
10373 return 21;
10374 case 0:
10375 // op: rt
10376 return 16;
10377 case 2:
10378 // op: imm10
10379 return 6;
10380 }
10381 break;
10382 }
10383 case Mips::ADDi:
10384 case Mips::ADDiu:
10385 case Mips::ANDi:
10386 case Mips::ANDi64:
10387 case Mips::DADDi:
10388 case Mips::DADDiu:
10389 case Mips::ORi:
10390 case Mips::ORi64:
10391 case Mips::XORi:
10392 case Mips::XORi64: {
10393 switch (OpNum) {
10394 case 1:
10395 // op: rs
10396 return 21;
10397 case 0:
10398 // op: rt
10399 return 16;
10400 case 2:
10401 // op: imm16
10402 return 0;
10403 }
10404 break;
10405 }
10406 case Mips::PRECR_SRA_PH_W:
10407 case Mips::PRECR_SRA_R_PH_W: {
10408 switch (OpNum) {
10409 case 1:
10410 // op: rs
10411 return 21;
10412 case 0:
10413 // op: rt
10414 return 16;
10415 case 2:
10416 // op: sa
10417 return 11;
10418 }
10419 break;
10420 }
10421 case Mips::DLSA:
10422 case Mips::LSA: {
10423 switch (OpNum) {
10424 case 1:
10425 // op: rs
10426 return 21;
10427 case 2:
10428 // op: rt
10429 return 16;
10430 case 0:
10431 // op: rd
10432 return 11;
10433 case 3:
10434 // op: sa
10435 return 6;
10436 }
10437 break;
10438 }
10439 case Mips::CMPGDU_EQ_QB:
10440 case Mips::CMPGDU_LE_QB:
10441 case Mips::CMPGDU_LT_QB:
10442 case Mips::CMPGU_EQ_QB:
10443 case Mips::CMPGU_LE_QB:
10444 case Mips::CMPGU_LT_QB:
10445 case Mips::PACKRL_PH:
10446 case Mips::PICK_PH:
10447 case Mips::PICK_QB:
10448 case Mips::PRECRQU_S_QB_PH:
10449 case Mips::PRECRQ_PH_W:
10450 case Mips::PRECRQ_QB_PH:
10451 case Mips::PRECRQ_RS_PH_W:
10452 case Mips::PRECR_QB_PH: {
10453 switch (OpNum) {
10454 case 1:
10455 // op: rs
10456 return 21;
10457 case 2:
10458 // op: rt
10459 return 16;
10460 case 0:
10461 // op: rd
10462 return 11;
10463 }
10464 break;
10465 }
10466 case Mips::CRC32B:
10467 case Mips::CRC32CB:
10468 case Mips::CRC32CD:
10469 case Mips::CRC32CH:
10470 case Mips::CRC32CW:
10471 case Mips::CRC32D:
10472 case Mips::CRC32H:
10473 case Mips::CRC32W: {
10474 switch (OpNum) {
10475 case 1:
10476 // op: rs
10477 return 21;
10478 case 2:
10479 // op: rt
10480 return 16;
10481 }
10482 break;
10483 }
10484 case Mips::ADDU16_MMR6:
10485 case Mips::SUBU16_MMR6: {
10486 switch (OpNum) {
10487 case 1:
10488 // op: rs
10489 return 7;
10490 case 2:
10491 // op: rt
10492 return 4;
10493 case 0:
10494 // op: rd
10495 return 1;
10496 }
10497 break;
10498 }
10499 case Mips::CTC1:
10500 case Mips::DMTC1:
10501 case Mips::MTC1:
10502 case Mips::MTC1_D64: {
10503 switch (OpNum) {
10504 case 1:
10505 // op: rt
10506 return 16;
10507 case 0:
10508 // op: fs
10509 return 11;
10510 }
10511 break;
10512 }
10513 case Mips::DMTC0:
10514 case Mips::DMTC2:
10515 case Mips::DMTGC0:
10516 case Mips::MTC0:
10517 case Mips::MTC2:
10518 case Mips::MTGC0:
10519 case Mips::MTHGC0: {
10520 switch (OpNum) {
10521 case 1:
10522 // op: rt
10523 return 16;
10524 case 0:
10525 // op: rd
10526 return 11;
10527 case 2:
10528 // op: sel
10529 return 0;
10530 }
10531 break;
10532 }
10533 case Mips::MFTR:
10534 case Mips::MTTR: {
10535 switch (OpNum) {
10536 case 1:
10537 // op: rt
10538 return 16;
10539 case 0:
10540 // op: rd
10541 return 11;
10542 case 2:
10543 // op: u
10544 return 5;
10545 case 4:
10546 // op: h
10547 return 4;
10548 case 3:
10549 // op: sel
10550 return 0;
10551 }
10552 break;
10553 }
10554 case Mips::SC:
10555 case Mips::SC64:
10556 case Mips::SCD: {
10557 switch (OpNum) {
10558 case 1:
10559 // op: rt
10560 return 16;
10561 case 2:
10562 // op: addr
10563 return 0;
10564 }
10565 break;
10566 }
10567 case Mips::SC64_R6:
10568 case Mips::SCD_R6:
10569 case Mips::SC_R6: {
10570 switch (OpNum) {
10571 case 1:
10572 // op: rt
10573 return 16;
10574 case 2:
10575 // op: addr
10576 return 7;
10577 }
10578 break;
10579 }
10580 case Mips::CTC1_MM:
10581 case Mips::MTC1_D64_MM:
10582 case Mips::MTC1_MM:
10583 case Mips::MTC1_MMR6: {
10584 switch (OpNum) {
10585 case 1:
10586 // op: rt
10587 return 21;
10588 case 0:
10589 // op: fs
10590 return 16;
10591 }
10592 break;
10593 }
10594 case Mips::CTC2_MM:
10595 case Mips::MTC2_MMR6:
10596 case Mips::MTHC2_MMR6: {
10597 switch (OpNum) {
10598 case 1:
10599 // op: rt
10600 return 21;
10601 case 0:
10602 // op: impl
10603 return 16;
10604 }
10605 break;
10606 }
10607 case Mips::BEQC_MMR6:
10608 case Mips::BGEC_MMR6:
10609 case Mips::BGEUC_MMR6:
10610 case Mips::BLTC_MMR6:
10611 case Mips::BLTUC_MMR6:
10612 case Mips::BNEC_MMR6: {
10613 switch (OpNum) {
10614 case 1:
10615 // op: rt
10616 return 21;
10617 case 0:
10618 // op: rs
10619 return 16;
10620 case 2:
10621 // op: offset
10622 return 0;
10623 }
10624 break;
10625 }
10626 case Mips::MTC0_MMR6:
10627 case Mips::MTGC0_MM:
10628 case Mips::MTHC0_MMR6:
10629 case Mips::MTHGC0_MM: {
10630 switch (OpNum) {
10631 case 1:
10632 // op: rt
10633 return 21;
10634 case 0:
10635 // op: rs
10636 return 16;
10637 case 2:
10638 // op: sel
10639 return 11;
10640 }
10641 break;
10642 }
10643 case Mips::CMPU_EQ_QB_MM:
10644 case Mips::CMPU_LE_QB_MM:
10645 case Mips::CMPU_LT_QB_MM:
10646 case Mips::CMP_EQ_PH_MM:
10647 case Mips::CMP_LE_PH_MM:
10648 case Mips::CMP_LT_PH_MM: {
10649 switch (OpNum) {
10650 case 1:
10651 // op: rt
10652 return 21;
10653 case 0:
10654 // op: rs
10655 return 16;
10656 }
10657 break;
10658 }
10659 case Mips::SCE_MM:
10660 case Mips::SC_MM:
10661 case Mips::SC_MMR6: {
10662 switch (OpNum) {
10663 case 1:
10664 // op: rt
10665 return 21;
10666 case 2:
10667 // op: addr
10668 return 0;
10669 }
10670 break;
10671 }
10672 case Mips::AdduRxRyRz16:
10673 case Mips::SubuRxRyRz16: {
10674 switch (OpNum) {
10675 case 1:
10676 // op: rx
10677 return 8;
10678 case 2:
10679 // op: ry
10680 return 5;
10681 case 0:
10682 // op: rz
10683 return 2;
10684 }
10685 break;
10686 }
10687 case Mips::AndRxRxRy16:
10688 case Mips::OrRxRxRy16:
10689 case Mips::SllvRxRy16:
10690 case Mips::SravRxRy16:
10691 case Mips::SrlvRxRy16:
10692 case Mips::XorRxRxRy16: {
10693 switch (OpNum) {
10694 case 1:
10695 // op: rx
10696 return 8;
10697 case 2:
10698 // op: ry
10699 return 5;
10700 }
10701 break;
10702 }
10703 case Mips::LDI_B:
10704 case Mips::LDI_D:
10705 case Mips::LDI_H:
10706 case Mips::LDI_W: {
10707 switch (OpNum) {
10708 case 1:
10709 // op: s10
10710 return 11;
10711 case 0:
10712 // op: wd
10713 return 6;
10714 }
10715 break;
10716 }
10717 case Mips::SHILO_MM: {
10718 switch (OpNum) {
10719 case 1:
10720 // op: shift
10721 return 16;
10722 case 0:
10723 // op: ac
10724 return 14;
10725 }
10726 break;
10727 }
10728 case Mips::BCLRI_B:
10729 case Mips::BCLRI_D:
10730 case Mips::BCLRI_H:
10731 case Mips::BCLRI_W:
10732 case Mips::BNEGI_B:
10733 case Mips::BNEGI_D:
10734 case Mips::BNEGI_H:
10735 case Mips::BNEGI_W:
10736 case Mips::BSETI_B:
10737 case Mips::BSETI_D:
10738 case Mips::BSETI_H:
10739 case Mips::BSETI_W:
10740 case Mips::SAT_S_B:
10741 case Mips::SAT_S_D:
10742 case Mips::SAT_S_H:
10743 case Mips::SAT_S_W:
10744 case Mips::SAT_U_B:
10745 case Mips::SAT_U_D:
10746 case Mips::SAT_U_H:
10747 case Mips::SAT_U_W:
10748 case Mips::SLLI_B:
10749 case Mips::SLLI_D:
10750 case Mips::SLLI_H:
10751 case Mips::SLLI_W:
10752 case Mips::SRAI_B:
10753 case Mips::SRAI_D:
10754 case Mips::SRAI_H:
10755 case Mips::SRAI_W:
10756 case Mips::SRARI_B:
10757 case Mips::SRARI_D:
10758 case Mips::SRARI_H:
10759 case Mips::SRARI_W:
10760 case Mips::SRLI_B:
10761 case Mips::SRLI_D:
10762 case Mips::SRLI_H:
10763 case Mips::SRLI_W:
10764 case Mips::SRLRI_B:
10765 case Mips::SRLRI_D:
10766 case Mips::SRLRI_H:
10767 case Mips::SRLRI_W: {
10768 switch (OpNum) {
10769 case 1:
10770 // op: ws
10771 return 11;
10772 case 0:
10773 // op: wd
10774 return 6;
10775 case 2:
10776 // op: m
10777 return 16;
10778 }
10779 break;
10780 }
10781 case Mips::FCLASS_D:
10782 case Mips::FCLASS_W:
10783 case Mips::FEXUPL_D:
10784 case Mips::FEXUPL_W:
10785 case Mips::FEXUPR_D:
10786 case Mips::FEXUPR_W:
10787 case Mips::FFINT_S_D:
10788 case Mips::FFINT_S_W:
10789 case Mips::FFINT_U_D:
10790 case Mips::FFINT_U_W:
10791 case Mips::FFQL_D:
10792 case Mips::FFQL_W:
10793 case Mips::FFQR_D:
10794 case Mips::FFQR_W:
10795 case Mips::FLOG2_D:
10796 case Mips::FLOG2_W:
10797 case Mips::FRCP_D:
10798 case Mips::FRCP_W:
10799 case Mips::FRINT_D:
10800 case Mips::FRINT_W:
10801 case Mips::FRSQRT_D:
10802 case Mips::FRSQRT_W:
10803 case Mips::FSQRT_D:
10804 case Mips::FSQRT_W:
10805 case Mips::FTINT_S_D:
10806 case Mips::FTINT_S_W:
10807 case Mips::FTINT_U_D:
10808 case Mips::FTINT_U_W:
10809 case Mips::FTRUNC_S_D:
10810 case Mips::FTRUNC_S_W:
10811 case Mips::FTRUNC_U_D:
10812 case Mips::FTRUNC_U_W:
10813 case Mips::MOVE_V:
10814 case Mips::NLOC_B:
10815 case Mips::NLOC_D:
10816 case Mips::NLOC_H:
10817 case Mips::NLOC_W:
10818 case Mips::NLZC_B:
10819 case Mips::NLZC_D:
10820 case Mips::NLZC_H:
10821 case Mips::NLZC_W:
10822 case Mips::PCNT_B:
10823 case Mips::PCNT_D:
10824 case Mips::PCNT_H:
10825 case Mips::PCNT_W: {
10826 switch (OpNum) {
10827 case 1:
10828 // op: ws
10829 return 11;
10830 case 0:
10831 // op: wd
10832 return 6;
10833 }
10834 break;
10835 }
10836 case Mips::SCE: {
10837 switch (OpNum) {
10838 case 2:
10839 // op: addr
10840 return 7;
10841 case 1:
10842 // op: rt
10843 return 16;
10844 }
10845 break;
10846 }
10847 case Mips::MAXA_D:
10848 case Mips::MAXA_S:
10849 case Mips::MAX_D:
10850 case Mips::MAX_S:
10851 case Mips::MINA_D:
10852 case Mips::MINA_S:
10853 case Mips::MIN_D:
10854 case Mips::MIN_S:
10855 case Mips::SELEQZ_D:
10856 case Mips::SELEQZ_S:
10857 case Mips::SELNEZ_D:
10858 case Mips::SELNEZ_S: {
10859 switch (OpNum) {
10860 case 2:
10861 // op: ft
10862 return 16;
10863 case 1:
10864 // op: fs
10865 return 11;
10866 case 0:
10867 // op: fd
10868 return 6;
10869 }
10870 break;
10871 }
10872 case Mips::CMP_AF_D_MMR6:
10873 case Mips::CMP_AF_S_MMR6:
10874 case Mips::CMP_EQ_D_MMR6:
10875 case Mips::CMP_EQ_S_MMR6:
10876 case Mips::CMP_LE_D_MMR6:
10877 case Mips::CMP_LE_S_MMR6:
10878 case Mips::CMP_LT_D_MMR6:
10879 case Mips::CMP_LT_S_MMR6:
10880 case Mips::CMP_SAF_D_MMR6:
10881 case Mips::CMP_SAF_S_MMR6:
10882 case Mips::CMP_SEQ_D_MMR6:
10883 case Mips::CMP_SEQ_S_MMR6:
10884 case Mips::CMP_SLE_D_MMR6:
10885 case Mips::CMP_SLE_S_MMR6:
10886 case Mips::CMP_SLT_D_MMR6:
10887 case Mips::CMP_SLT_S_MMR6:
10888 case Mips::CMP_SUEQ_D_MMR6:
10889 case Mips::CMP_SUEQ_S_MMR6:
10890 case Mips::CMP_SULE_D_MMR6:
10891 case Mips::CMP_SULE_S_MMR6:
10892 case Mips::CMP_SULT_D_MMR6:
10893 case Mips::CMP_SULT_S_MMR6:
10894 case Mips::CMP_SUN_D_MMR6:
10895 case Mips::CMP_SUN_S_MMR6:
10896 case Mips::CMP_UEQ_D_MMR6:
10897 case Mips::CMP_UEQ_S_MMR6:
10898 case Mips::CMP_ULE_D_MMR6:
10899 case Mips::CMP_ULE_S_MMR6:
10900 case Mips::CMP_ULT_D_MMR6:
10901 case Mips::CMP_ULT_S_MMR6:
10902 case Mips::CMP_UN_D_MMR6:
10903 case Mips::CMP_UN_S_MMR6:
10904 case Mips::FADD_D32_MM:
10905 case Mips::FADD_D64_MM:
10906 case Mips::FADD_S_MM:
10907 case Mips::FDIV_D32_MM:
10908 case Mips::FDIV_D64_MM:
10909 case Mips::FDIV_S_MM:
10910 case Mips::FMUL_D32_MM:
10911 case Mips::FMUL_D64_MM:
10912 case Mips::FMUL_S_MM:
10913 case Mips::FSUB_D32_MM:
10914 case Mips::FSUB_D64_MM:
10915 case Mips::FSUB_S_MM:
10916 case Mips::MAXA_D_MMR6:
10917 case Mips::MAXA_S_MMR6:
10918 case Mips::MAX_D_MMR6:
10919 case Mips::MAX_S_MMR6:
10920 case Mips::MINA_D_MMR6:
10921 case Mips::MINA_S_MMR6:
10922 case Mips::MIN_D_MMR6:
10923 case Mips::MIN_S_MMR6:
10924 case Mips::SELEQZ_D_MMR6:
10925 case Mips::SELEQZ_S_MMR6:
10926 case Mips::SELNEZ_D_MMR6:
10927 case Mips::SELNEZ_S_MMR6: {
10928 switch (OpNum) {
10929 case 2:
10930 // op: ft
10931 return 21;
10932 case 1:
10933 // op: fs
10934 return 16;
10935 case 0:
10936 // op: fd
10937 return 11;
10938 }
10939 break;
10940 }
10941 case Mips::ADDVI_B:
10942 case Mips::ADDVI_D:
10943 case Mips::ADDVI_H:
10944 case Mips::ADDVI_W:
10945 case Mips::CEQI_B:
10946 case Mips::CEQI_D:
10947 case Mips::CEQI_H:
10948 case Mips::CEQI_W:
10949 case Mips::CLEI_S_B:
10950 case Mips::CLEI_S_D:
10951 case Mips::CLEI_S_H:
10952 case Mips::CLEI_S_W:
10953 case Mips::CLEI_U_B:
10954 case Mips::CLEI_U_D:
10955 case Mips::CLEI_U_H:
10956 case Mips::CLEI_U_W:
10957 case Mips::CLTI_S_B:
10958 case Mips::CLTI_S_D:
10959 case Mips::CLTI_S_H:
10960 case Mips::CLTI_S_W:
10961 case Mips::CLTI_U_B:
10962 case Mips::CLTI_U_D:
10963 case Mips::CLTI_U_H:
10964 case Mips::CLTI_U_W:
10965 case Mips::MAXI_S_B:
10966 case Mips::MAXI_S_D:
10967 case Mips::MAXI_S_H:
10968 case Mips::MAXI_S_W:
10969 case Mips::MAXI_U_B:
10970 case Mips::MAXI_U_D:
10971 case Mips::MAXI_U_H:
10972 case Mips::MAXI_U_W:
10973 case Mips::MINI_S_B:
10974 case Mips::MINI_S_D:
10975 case Mips::MINI_S_H:
10976 case Mips::MINI_S_W:
10977 case Mips::MINI_U_B:
10978 case Mips::MINI_U_D:
10979 case Mips::MINI_U_H:
10980 case Mips::MINI_U_W:
10981 case Mips::SUBVI_B:
10982 case Mips::SUBVI_D:
10983 case Mips::SUBVI_H:
10984 case Mips::SUBVI_W: {
10985 switch (OpNum) {
10986 case 2:
10987 // op: imm
10988 return 16;
10989 case 1:
10990 // op: ws
10991 return 11;
10992 case 0:
10993 // op: wd
10994 return 6;
10995 }
10996 break;
10997 }
10998 case Mips::AddiuRxRyOffMemX16: {
10999 switch (OpNum) {
11000 case 2:
11001 // op: imm15
11002 return 0;
11003 case 1:
11004 // op: rx
11005 return 8;
11006 case 0:
11007 // op: ry
11008 return 5;
11009 }
11010 break;
11011 }
11012 case Mips::AddiuRxRxImmX16: {
11013 switch (OpNum) {
11014 case 2:
11015 // op: imm16
11016 return 0;
11017 case 0:
11018 // op: rx
11019 return 8;
11020 }
11021 break;
11022 }
11023 case Mips::LbRxRyOffMemX16:
11024 case Mips::LbuRxRyOffMemX16:
11025 case Mips::LhRxRyOffMemX16:
11026 case Mips::LhuRxRyOffMemX16:
11027 case Mips::LwRxRyOffMemX16:
11028 case Mips::LwRxSpImmX16:
11029 case Mips::SbRxRyOffMemX16:
11030 case Mips::ShRxRyOffMemX16:
11031 case Mips::SwRxRyOffMemX16:
11032 case Mips::SwRxSpImmX16: {
11033 switch (OpNum) {
11034 case 2:
11035 // op: imm16
11036 return 0;
11037 case 1:
11038 // op: rx
11039 return 8;
11040 case 0:
11041 // op: ry
11042 return 5;
11043 }
11044 break;
11045 }
11046 case Mips::LBUX_MM:
11047 case Mips::LHX_MM:
11048 case Mips::LWX_MM: {
11049 switch (OpNum) {
11050 case 2:
11051 // op: index
11052 return 21;
11053 case 1:
11054 // op: base
11055 return 16;
11056 case 0:
11057 // op: rd
11058 return 11;
11059 }
11060 break;
11061 }
11062 case Mips::COPY_S_B:
11063 case Mips::COPY_S_D:
11064 case Mips::COPY_S_H:
11065 case Mips::COPY_S_W:
11066 case Mips::COPY_U_B:
11067 case Mips::COPY_U_H:
11068 case Mips::COPY_U_W: {
11069 switch (OpNum) {
11070 case 2:
11071 // op: n
11072 return 16;
11073 case 1:
11074 // op: ws
11075 return 11;
11076 case 0:
11077 // op: rd
11078 return 6;
11079 }
11080 break;
11081 }
11082 case Mips::SPLATI_B:
11083 case Mips::SPLATI_D:
11084 case Mips::SPLATI_H:
11085 case Mips::SPLATI_W: {
11086 switch (OpNum) {
11087 case 2:
11088 // op: n
11089 return 16;
11090 case 1:
11091 // op: ws
11092 return 11;
11093 case 0:
11094 // op: wd
11095 return 6;
11096 }
11097 break;
11098 }
11099 case Mips::INSVE_B:
11100 case Mips::INSVE_D:
11101 case Mips::INSVE_H:
11102 case Mips::INSVE_W: {
11103 switch (OpNum) {
11104 case 2:
11105 // op: n
11106 return 16;
11107 case 3:
11108 // op: ws
11109 return 11;
11110 case 0:
11111 // op: wd
11112 return 6;
11113 }
11114 break;
11115 }
11116 case Mips::MTHC1_D32:
11117 case Mips::MTHC1_D64: {
11118 switch (OpNum) {
11119 case 2:
11120 // op: rt
11121 return 16;
11122 case 0:
11123 // op: fs
11124 return 11;
11125 }
11126 break;
11127 }
11128 case Mips::SPLAT_B:
11129 case Mips::SPLAT_D:
11130 case Mips::SPLAT_H:
11131 case Mips::SPLAT_W: {
11132 switch (OpNum) {
11133 case 2:
11134 // op: rt
11135 return 16;
11136 case 1:
11137 // op: ws
11138 return 11;
11139 case 0:
11140 // op: wd
11141 return 6;
11142 }
11143 break;
11144 }
11145 case Mips::MTHC1_D32_MM:
11146 case Mips::MTHC1_D64_MM: {
11147 switch (OpNum) {
11148 case 2:
11149 // op: rt
11150 return 21;
11151 case 0:
11152 // op: fs
11153 return 16;
11154 }
11155 break;
11156 }
11157 case Mips::DPAQX_SA_W_PH_MMR2:
11158 case Mips::DPAQX_S_W_PH_MMR2:
11159 case Mips::DPAQ_SA_L_W_MM:
11160 case Mips::DPAQ_S_W_PH_MM:
11161 case Mips::DPAU_H_QBL_MM:
11162 case Mips::DPAU_H_QBR_MM:
11163 case Mips::DPAX_W_PH_MMR2:
11164 case Mips::DPA_W_PH_MMR2:
11165 case Mips::DPSQX_SA_W_PH_MMR2:
11166 case Mips::DPSQX_S_W_PH_MMR2:
11167 case Mips::DPSQ_SA_L_W_MM:
11168 case Mips::DPSQ_S_W_PH_MM:
11169 case Mips::DPSU_H_QBL_MM:
11170 case Mips::DPSU_H_QBR_MM:
11171 case Mips::DPSX_W_PH_MMR2:
11172 case Mips::DPS_W_PH_MMR2:
11173 case Mips::MADDU_DSP_MM:
11174 case Mips::MADD_DSP_MM:
11175 case Mips::MAQ_SA_W_PHL_MM:
11176 case Mips::MAQ_SA_W_PHR_MM:
11177 case Mips::MAQ_S_W_PHL_MM:
11178 case Mips::MAQ_S_W_PHR_MM:
11179 case Mips::MSUBU_DSP_MM:
11180 case Mips::MSUB_DSP_MM:
11181 case Mips::MULSAQ_S_W_PH_MM:
11182 case Mips::MULSA_W_PH_MMR2:
11183 case Mips::MULTU_DSP_MM:
11184 case Mips::MULT_DSP_MM: {
11185 switch (OpNum) {
11186 case 2:
11187 // op: rt
11188 return 21;
11189 case 1:
11190 // op: rs
11191 return 16;
11192 case 0:
11193 // op: ac
11194 return 14;
11195 }
11196 break;
11197 }
11198 case Mips::ADD_MM:
11199 case Mips::ADDu_MM:
11200 case Mips::AND_MM:
11201 case Mips::CMPGU_EQ_QB_MM:
11202 case Mips::CMPGU_LE_QB_MM:
11203 case Mips::CMPGU_LT_QB_MM:
11204 case Mips::MOVN_I_MM:
11205 case Mips::MOVZ_I_MM:
11206 case Mips::MUL_MM:
11207 case Mips::NOR_MM:
11208 case Mips::OR_MM:
11209 case Mips::SLT_MM:
11210 case Mips::SLTu_MM:
11211 case Mips::SUB_MM:
11212 case Mips::SUBu_MM:
11213 case Mips::XOR_MM: {
11214 switch (OpNum) {
11215 case 2:
11216 // op: rt
11217 return 21;
11218 case 1:
11219 // op: rs
11220 return 16;
11221 case 0:
11222 // op: rd
11223 return 11;
11224 }
11225 break;
11226 }
11227 case Mips::AND16_MM:
11228 case Mips::OR16_MM:
11229 case Mips::XOR16_MM: {
11230 switch (OpNum) {
11231 case 2:
11232 // op: rt
11233 return 3;
11234 case 1:
11235 // op: rs
11236 return 0;
11237 }
11238 break;
11239 }
11240 case Mips::AND16_MMR6:
11241 case Mips::OR16_MMR6:
11242 case Mips::XOR16_MMR6: {
11243 switch (OpNum) {
11244 case 2:
11245 // op: rt
11246 return 7;
11247 case 1:
11248 // op: rs
11249 return 4;
11250 }
11251 break;
11252 }
11253 case Mips::SllX16:
11254 case Mips::SraX16:
11255 case Mips::SrlX16: {
11256 switch (OpNum) {
11257 case 2:
11258 // op: sa6
11259 return 21;
11260 case 0:
11261 // op: rx
11262 return 8;
11263 case 1:
11264 // op: ry
11265 return 5;
11266 }
11267 break;
11268 }
11269 case Mips::ANDI_B:
11270 case Mips::NORI_B:
11271 case Mips::ORI_B:
11272 case Mips::SHF_B:
11273 case Mips::SHF_H:
11274 case Mips::SHF_W:
11275 case Mips::XORI_B: {
11276 switch (OpNum) {
11277 case 2:
11278 // op: u8
11279 return 16;
11280 case 1:
11281 // op: ws
11282 return 11;
11283 case 0:
11284 // op: wd
11285 return 6;
11286 }
11287 break;
11288 }
11289 case Mips::BINSLI_B:
11290 case Mips::BINSLI_D:
11291 case Mips::BINSLI_H:
11292 case Mips::BINSLI_W:
11293 case Mips::BINSRI_B:
11294 case Mips::BINSRI_D:
11295 case Mips::BINSRI_H:
11296 case Mips::BINSRI_W: {
11297 switch (OpNum) {
11298 case 2:
11299 // op: ws
11300 return 11;
11301 case 0:
11302 // op: wd
11303 return 6;
11304 case 3:
11305 // op: m
11306 return 16;
11307 }
11308 break;
11309 }
11310 case Mips::ADDS_A_B:
11311 case Mips::ADDS_A_D:
11312 case Mips::ADDS_A_H:
11313 case Mips::ADDS_A_W:
11314 case Mips::ADDS_S_B:
11315 case Mips::ADDS_S_D:
11316 case Mips::ADDS_S_H:
11317 case Mips::ADDS_S_W:
11318 case Mips::ADDS_U_B:
11319 case Mips::ADDS_U_D:
11320 case Mips::ADDS_U_H:
11321 case Mips::ADDS_U_W:
11322 case Mips::ADDV_B:
11323 case Mips::ADDV_D:
11324 case Mips::ADDV_H:
11325 case Mips::ADDV_W:
11326 case Mips::ADD_A_B:
11327 case Mips::ADD_A_D:
11328 case Mips::ADD_A_H:
11329 case Mips::ADD_A_W:
11330 case Mips::AND_V:
11331 case Mips::ASUB_S_B:
11332 case Mips::ASUB_S_D:
11333 case Mips::ASUB_S_H:
11334 case Mips::ASUB_S_W:
11335 case Mips::ASUB_U_B:
11336 case Mips::ASUB_U_D:
11337 case Mips::ASUB_U_H:
11338 case Mips::ASUB_U_W:
11339 case Mips::AVER_S_B:
11340 case Mips::AVER_S_D:
11341 case Mips::AVER_S_H:
11342 case Mips::AVER_S_W:
11343 case Mips::AVER_U_B:
11344 case Mips::AVER_U_D:
11345 case Mips::AVER_U_H:
11346 case Mips::AVER_U_W:
11347 case Mips::AVE_S_B:
11348 case Mips::AVE_S_D:
11349 case Mips::AVE_S_H:
11350 case Mips::AVE_S_W:
11351 case Mips::AVE_U_B:
11352 case Mips::AVE_U_D:
11353 case Mips::AVE_U_H:
11354 case Mips::AVE_U_W:
11355 case Mips::BCLR_B:
11356 case Mips::BCLR_D:
11357 case Mips::BCLR_H:
11358 case Mips::BCLR_W:
11359 case Mips::BNEG_B:
11360 case Mips::BNEG_D:
11361 case Mips::BNEG_H:
11362 case Mips::BNEG_W:
11363 case Mips::BSET_B:
11364 case Mips::BSET_D:
11365 case Mips::BSET_H:
11366 case Mips::BSET_W:
11367 case Mips::CEQ_B:
11368 case Mips::CEQ_D:
11369 case Mips::CEQ_H:
11370 case Mips::CEQ_W:
11371 case Mips::CLE_S_B:
11372 case Mips::CLE_S_D:
11373 case Mips::CLE_S_H:
11374 case Mips::CLE_S_W:
11375 case Mips::CLE_U_B:
11376 case Mips::CLE_U_D:
11377 case Mips::CLE_U_H:
11378 case Mips::CLE_U_W:
11379 case Mips::CLT_S_B:
11380 case Mips::CLT_S_D:
11381 case Mips::CLT_S_H:
11382 case Mips::CLT_S_W:
11383 case Mips::CLT_U_B:
11384 case Mips::CLT_U_D:
11385 case Mips::CLT_U_H:
11386 case Mips::CLT_U_W:
11387 case Mips::DIV_S_B:
11388 case Mips::DIV_S_D:
11389 case Mips::DIV_S_H:
11390 case Mips::DIV_S_W:
11391 case Mips::DIV_U_B:
11392 case Mips::DIV_U_D:
11393 case Mips::DIV_U_H:
11394 case Mips::DIV_U_W:
11395 case Mips::DOTP_S_D:
11396 case Mips::DOTP_S_H:
11397 case Mips::DOTP_S_W:
11398 case Mips::DOTP_U_D:
11399 case Mips::DOTP_U_H:
11400 case Mips::DOTP_U_W:
11401 case Mips::FADD_D:
11402 case Mips::FADD_W:
11403 case Mips::FCAF_D:
11404 case Mips::FCAF_W:
11405 case Mips::FCEQ_D:
11406 case Mips::FCEQ_W:
11407 case Mips::FCLE_D:
11408 case Mips::FCLE_W:
11409 case Mips::FCLT_D:
11410 case Mips::FCLT_W:
11411 case Mips::FCNE_D:
11412 case Mips::FCNE_W:
11413 case Mips::FCOR_D:
11414 case Mips::FCOR_W:
11415 case Mips::FCUEQ_D:
11416 case Mips::FCUEQ_W:
11417 case Mips::FCULE_D:
11418 case Mips::FCULE_W:
11419 case Mips::FCULT_D:
11420 case Mips::FCULT_W:
11421 case Mips::FCUNE_D:
11422 case Mips::FCUNE_W:
11423 case Mips::FCUN_D:
11424 case Mips::FCUN_W:
11425 case Mips::FDIV_D:
11426 case Mips::FDIV_W:
11427 case Mips::FEXDO_H:
11428 case Mips::FEXDO_W:
11429 case Mips::FEXP2_D:
11430 case Mips::FEXP2_W:
11431 case Mips::FMAX_A_D:
11432 case Mips::FMAX_A_W:
11433 case Mips::FMAX_D:
11434 case Mips::FMAX_W:
11435 case Mips::FMIN_A_D:
11436 case Mips::FMIN_A_W:
11437 case Mips::FMIN_D:
11438 case Mips::FMIN_W:
11439 case Mips::FMUL_D:
11440 case Mips::FMUL_W:
11441 case Mips::FSAF_D:
11442 case Mips::FSAF_W:
11443 case Mips::FSEQ_D:
11444 case Mips::FSEQ_W:
11445 case Mips::FSLE_D:
11446 case Mips::FSLE_W:
11447 case Mips::FSLT_D:
11448 case Mips::FSLT_W:
11449 case Mips::FSNE_D:
11450 case Mips::FSNE_W:
11451 case Mips::FSOR_D:
11452 case Mips::FSOR_W:
11453 case Mips::FSUB_D:
11454 case Mips::FSUB_W:
11455 case Mips::FSUEQ_D:
11456 case Mips::FSUEQ_W:
11457 case Mips::FSULE_D:
11458 case Mips::FSULE_W:
11459 case Mips::FSULT_D:
11460 case Mips::FSULT_W:
11461 case Mips::FSUNE_D:
11462 case Mips::FSUNE_W:
11463 case Mips::FSUN_D:
11464 case Mips::FSUN_W:
11465 case Mips::FTQ_H:
11466 case Mips::FTQ_W:
11467 case Mips::HADD_S_D:
11468 case Mips::HADD_S_H:
11469 case Mips::HADD_S_W:
11470 case Mips::HADD_U_D:
11471 case Mips::HADD_U_H:
11472 case Mips::HADD_U_W:
11473 case Mips::HSUB_S_D:
11474 case Mips::HSUB_S_H:
11475 case Mips::HSUB_S_W:
11476 case Mips::HSUB_U_D:
11477 case Mips::HSUB_U_H:
11478 case Mips::HSUB_U_W:
11479 case Mips::ILVEV_B:
11480 case Mips::ILVEV_D:
11481 case Mips::ILVEV_H:
11482 case Mips::ILVEV_W:
11483 case Mips::ILVL_B:
11484 case Mips::ILVL_D:
11485 case Mips::ILVL_H:
11486 case Mips::ILVL_W:
11487 case Mips::ILVOD_B:
11488 case Mips::ILVOD_D:
11489 case Mips::ILVOD_H:
11490 case Mips::ILVOD_W:
11491 case Mips::ILVR_B:
11492 case Mips::ILVR_D:
11493 case Mips::ILVR_H:
11494 case Mips::ILVR_W:
11495 case Mips::MAX_A_B:
11496 case Mips::MAX_A_D:
11497 case Mips::MAX_A_H:
11498 case Mips::MAX_A_W:
11499 case Mips::MAX_S_B:
11500 case Mips::MAX_S_D:
11501 case Mips::MAX_S_H:
11502 case Mips::MAX_S_W:
11503 case Mips::MAX_U_B:
11504 case Mips::MAX_U_D:
11505 case Mips::MAX_U_H:
11506 case Mips::MAX_U_W:
11507 case Mips::MIN_A_B:
11508 case Mips::MIN_A_D:
11509 case Mips::MIN_A_H:
11510 case Mips::MIN_A_W:
11511 case Mips::MIN_S_B:
11512 case Mips::MIN_S_D:
11513 case Mips::MIN_S_H:
11514 case Mips::MIN_S_W:
11515 case Mips::MIN_U_B:
11516 case Mips::MIN_U_D:
11517 case Mips::MIN_U_H:
11518 case Mips::MIN_U_W:
11519 case Mips::MOD_S_B:
11520 case Mips::MOD_S_D:
11521 case Mips::MOD_S_H:
11522 case Mips::MOD_S_W:
11523 case Mips::MOD_U_B:
11524 case Mips::MOD_U_D:
11525 case Mips::MOD_U_H:
11526 case Mips::MOD_U_W:
11527 case Mips::MULR_Q_H:
11528 case Mips::MULR_Q_W:
11529 case Mips::MULV_B:
11530 case Mips::MULV_D:
11531 case Mips::MULV_H:
11532 case Mips::MULV_W:
11533 case Mips::MUL_Q_H:
11534 case Mips::MUL_Q_W:
11535 case Mips::NOR_V:
11536 case Mips::OR_V:
11537 case Mips::PCKEV_B:
11538 case Mips::PCKEV_D:
11539 case Mips::PCKEV_H:
11540 case Mips::PCKEV_W:
11541 case Mips::PCKOD_B:
11542 case Mips::PCKOD_D:
11543 case Mips::PCKOD_H:
11544 case Mips::PCKOD_W:
11545 case Mips::SLL_B:
11546 case Mips::SLL_D:
11547 case Mips::SLL_H:
11548 case Mips::SLL_W:
11549 case Mips::SRAR_B:
11550 case Mips::SRAR_D:
11551 case Mips::SRAR_H:
11552 case Mips::SRAR_W:
11553 case Mips::SRA_B:
11554 case Mips::SRA_D:
11555 case Mips::SRA_H:
11556 case Mips::SRA_W:
11557 case Mips::SRLR_B:
11558 case Mips::SRLR_D:
11559 case Mips::SRLR_H:
11560 case Mips::SRLR_W:
11561 case Mips::SRL_B:
11562 case Mips::SRL_D:
11563 case Mips::SRL_H:
11564 case Mips::SRL_W:
11565 case Mips::SUBSUS_U_B:
11566 case Mips::SUBSUS_U_D:
11567 case Mips::SUBSUS_U_H:
11568 case Mips::SUBSUS_U_W:
11569 case Mips::SUBSUU_S_B:
11570 case Mips::SUBSUU_S_D:
11571 case Mips::SUBSUU_S_H:
11572 case Mips::SUBSUU_S_W:
11573 case Mips::SUBS_S_B:
11574 case Mips::SUBS_S_D:
11575 case Mips::SUBS_S_H:
11576 case Mips::SUBS_S_W:
11577 case Mips::SUBS_U_B:
11578 case Mips::SUBS_U_D:
11579 case Mips::SUBS_U_H:
11580 case Mips::SUBS_U_W:
11581 case Mips::SUBV_B:
11582 case Mips::SUBV_D:
11583 case Mips::SUBV_H:
11584 case Mips::SUBV_W:
11585 case Mips::XOR_V: {
11586 switch (OpNum) {
11587 case 2:
11588 // op: wt
11589 return 16;
11590 case 1:
11591 // op: ws
11592 return 11;
11593 case 0:
11594 // op: wd
11595 return 6;
11596 }
11597 break;
11598 }
11599 case Mips::MADDF_D:
11600 case Mips::MADDF_S:
11601 case Mips::MSUBF_D:
11602 case Mips::MSUBF_S:
11603 case Mips::SEL_D:
11604 case Mips::SEL_S: {
11605 switch (OpNum) {
11606 case 3:
11607 // op: ft
11608 return 16;
11609 case 2:
11610 // op: fs
11611 return 11;
11612 case 0:
11613 // op: fd
11614 return 6;
11615 }
11616 break;
11617 }
11618 case Mips::MADD_D32_MM:
11619 case Mips::MADD_S_MM:
11620 case Mips::MSUB_D32_MM:
11621 case Mips::MSUB_S_MM:
11622 case Mips::NMADD_D32_MM:
11623 case Mips::NMADD_S_MM:
11624 case Mips::NMSUB_D32_MM:
11625 case Mips::NMSUB_S_MM: {
11626 switch (OpNum) {
11627 case 3:
11628 // op: ft
11629 return 21;
11630 case 2:
11631 // op: fs
11632 return 16;
11633 case 0:
11634 // op: fd
11635 return 11;
11636 case 1:
11637 // op: fr
11638 return 6;
11639 }
11640 break;
11641 }
11642 case Mips::MADDF_D_MMR6:
11643 case Mips::MADDF_S_MMR6:
11644 case Mips::MSUBF_D_MMR6:
11645 case Mips::MSUBF_S_MMR6:
11646 case Mips::SEL_D_MMR6:
11647 case Mips::SEL_S_MMR6: {
11648 switch (OpNum) {
11649 case 3:
11650 // op: ft
11651 return 21;
11652 case 2:
11653 // op: fs
11654 return 16;
11655 case 0:
11656 // op: fd
11657 return 11;
11658 }
11659 break;
11660 }
11661 case Mips::INSERT_B:
11662 case Mips::INSERT_D:
11663 case Mips::INSERT_H:
11664 case Mips::INSERT_W: {
11665 switch (OpNum) {
11666 case 3:
11667 // op: n
11668 return 16;
11669 case 2:
11670 // op: rs
11671 return 11;
11672 case 0:
11673 // op: wd
11674 return 6;
11675 }
11676 break;
11677 }
11678 case Mips::SLDI_B:
11679 case Mips::SLDI_D:
11680 case Mips::SLDI_H:
11681 case Mips::SLDI_W: {
11682 switch (OpNum) {
11683 case 3:
11684 // op: n
11685 return 16;
11686 case 2:
11687 // op: ws
11688 return 11;
11689 case 0:
11690 // op: wd
11691 return 6;
11692 }
11693 break;
11694 }
11695 case Mips::SLD_B:
11696 case Mips::SLD_D:
11697 case Mips::SLD_H:
11698 case Mips::SLD_W: {
11699 switch (OpNum) {
11700 case 3:
11701 // op: rt
11702 return 16;
11703 case 2:
11704 // op: ws
11705 return 11;
11706 case 0:
11707 // op: wd
11708 return 6;
11709 }
11710 break;
11711 }
11712 case Mips::MOVEP_MMR6: {
11713 switch (OpNum) {
11714 case 3:
11715 // op: rt
11716 return 4;
11717 case 2:
11718 // op: rs
11719 return 0;
11720 }
11721 break;
11722 }
11723 case Mips::MOVEP_MM: {
11724 switch (OpNum) {
11725 case 3:
11726 // op: rt
11727 return 4;
11728 case 2:
11729 // op: rs
11730 return 1;
11731 }
11732 break;
11733 }
11734 case Mips::BMNZI_B:
11735 case Mips::BMZI_B:
11736 case Mips::BSELI_B: {
11737 switch (OpNum) {
11738 case 3:
11739 // op: u8
11740 return 16;
11741 case 2:
11742 // op: ws
11743 return 11;
11744 case 0:
11745 // op: wd
11746 return 6;
11747 }
11748 break;
11749 }
11750 case Mips::BINSL_B:
11751 case Mips::BINSL_D:
11752 case Mips::BINSL_H:
11753 case Mips::BINSL_W:
11754 case Mips::BINSR_B:
11755 case Mips::BINSR_D:
11756 case Mips::BINSR_H:
11757 case Mips::BINSR_W:
11758 case Mips::BMNZ_V:
11759 case Mips::BMZ_V:
11760 case Mips::BSEL_V:
11761 case Mips::DPADD_S_D:
11762 case Mips::DPADD_S_H:
11763 case Mips::DPADD_S_W:
11764 case Mips::DPADD_U_D:
11765 case Mips::DPADD_U_H:
11766 case Mips::DPADD_U_W:
11767 case Mips::DPSUB_S_D:
11768 case Mips::DPSUB_S_H:
11769 case Mips::DPSUB_S_W:
11770 case Mips::DPSUB_U_D:
11771 case Mips::DPSUB_U_H:
11772 case Mips::DPSUB_U_W:
11773 case Mips::FMADD_D:
11774 case Mips::FMADD_W:
11775 case Mips::FMSUB_D:
11776 case Mips::FMSUB_W:
11777 case Mips::MADDR_Q_H:
11778 case Mips::MADDR_Q_W:
11779 case Mips::MADDV_B:
11780 case Mips::MADDV_D:
11781 case Mips::MADDV_H:
11782 case Mips::MADDV_W:
11783 case Mips::MADD_Q_H:
11784 case Mips::MADD_Q_W:
11785 case Mips::MSUBR_Q_H:
11786 case Mips::MSUBR_Q_W:
11787 case Mips::MSUBV_B:
11788 case Mips::MSUBV_D:
11789 case Mips::MSUBV_H:
11790 case Mips::MSUBV_W:
11791 case Mips::MSUB_Q_H:
11792 case Mips::MSUB_Q_W:
11793 case Mips::VSHF_B:
11794 case Mips::VSHF_D:
11795 case Mips::VSHF_H:
11796 case Mips::VSHF_W: {
11797 switch (OpNum) {
11798 case 3:
11799 // op: wt
11800 return 16;
11801 case 2:
11802 // op: ws
11803 return 11;
11804 case 0:
11805 // op: wd
11806 return 6;
11807 }
11808 break;
11809 }
11810 default:
11811 reportUnsupportedInst(MI);
11812 }
11813 reportUnsupportedOperand(MI, OpNum);
11814}
11815
11816#endif // GET_OPERAND_BIT_OFFSET
11817
11818