1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass NVPTXMCRegisterClasses[];
13
14namespace NVPTX {
15
16enum : unsigned {
17 NoRegister,
18 VRDepot = 1,
19 ENVREG0 = 2,
20 ENVREG1 = 3,
21 ENVREG2 = 4,
22 ENVREG3 = 5,
23 ENVREG4 = 6,
24 ENVREG5 = 7,
25 ENVREG6 = 8,
26 ENVREG7 = 9,
27 ENVREG8 = 10,
28 ENVREG9 = 11,
29 ENVREG10 = 12,
30 ENVREG11 = 13,
31 ENVREG12 = 14,
32 ENVREG13 = 15,
33 ENVREG14 = 16,
34 ENVREG15 = 17,
35 ENVREG16 = 18,
36 ENVREG17 = 19,
37 ENVREG18 = 20,
38 ENVREG19 = 21,
39 ENVREG20 = 22,
40 ENVREG21 = 23,
41 ENVREG22 = 24,
42 ENVREG23 = 25,
43 ENVREG24 = 26,
44 ENVREG25 = 27,
45 ENVREG26 = 28,
46 ENVREG27 = 29,
47 ENVREG28 = 30,
48 ENVREG29 = 31,
49 ENVREG30 = 32,
50 ENVREG31 = 33,
51 P0 = 34,
52 P1 = 35,
53 P2 = 36,
54 P3 = 37,
55 P4 = 38,
56 R0 = 39,
57 R1 = 40,
58 R2 = 41,
59 R3 = 42,
60 R4 = 43,
61 RL0 = 44,
62 RL1 = 45,
63 RL2 = 46,
64 RL3 = 47,
65 RL4 = 48,
66 RQ0 = 49,
67 RQ1 = 50,
68 RQ2 = 51,
69 RQ3 = 52,
70 RQ4 = 53,
71 RS0 = 54,
72 RS1 = 55,
73 RS2 = 56,
74 RS3 = 57,
75 RS4 = 58,
76 VRFrame32 = 59,
77 VRFrame64 = 60,
78 VRFrameLocal32 = 61,
79 VRFrameLocal64 = 62,
80 NUM_TARGET_REGS // 63
81};
82
83} // namespace NVPTX
84
85// Register classes
86
87namespace NVPTX {
88
89enum {
90 B1RegClassID = 0,
91 B16RegClassID = 1,
92 SpecialRegsRegClassID = 2,
93 B32RegClassID = 3,
94 B32_and_SpecialRegsRegClassID = 4,
95 B64RegClassID = 5,
96 B128RegClassID = 6,
97
98};
99
100} // namespace NVPTX
101// Register pressure sets enum.
102namespace NVPTX {
103
104enum RegisterPressureSets {
105 B32_and_SpecialRegs = 0,
106 B1 = 1,
107 B16 = 2,
108 B128 = 3,
109 B32 = 4,
110 B64 = 5,
111 SpecialRegs = 6,
112 SpecialRegs_with_B32 = 7,
113};
114
115} // namespace NVPTX
116
117} // namespace llvm
118