1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass NVPTXMCRegisterClasses[];
13
14namespace NVPTX {
15enum : unsigned {
16 NoRegister,
17 VRDepot = 1,
18 ENVREG0 = 2,
19 ENVREG1 = 3,
20 ENVREG2 = 4,
21 ENVREG3 = 5,
22 ENVREG4 = 6,
23 ENVREG5 = 7,
24 ENVREG6 = 8,
25 ENVREG7 = 9,
26 ENVREG8 = 10,
27 ENVREG9 = 11,
28 ENVREG10 = 12,
29 ENVREG11 = 13,
30 ENVREG12 = 14,
31 ENVREG13 = 15,
32 ENVREG14 = 16,
33 ENVREG15 = 17,
34 ENVREG16 = 18,
35 ENVREG17 = 19,
36 ENVREG18 = 20,
37 ENVREG19 = 21,
38 ENVREG20 = 22,
39 ENVREG21 = 23,
40 ENVREG22 = 24,
41 ENVREG23 = 25,
42 ENVREG24 = 26,
43 ENVREG25 = 27,
44 ENVREG26 = 28,
45 ENVREG27 = 29,
46 ENVREG28 = 30,
47 ENVREG29 = 31,
48 ENVREG30 = 32,
49 ENVREG31 = 33,
50 P0 = 34,
51 P1 = 35,
52 P2 = 36,
53 P3 = 37,
54 P4 = 38,
55 R0 = 39,
56 R1 = 40,
57 R2 = 41,
58 R3 = 42,
59 R4 = 43,
60 RL0 = 44,
61 RL1 = 45,
62 RL2 = 46,
63 RL3 = 47,
64 RL4 = 48,
65 RQ0 = 49,
66 RQ1 = 50,
67 RQ2 = 51,
68 RQ3 = 52,
69 RQ4 = 53,
70 RS0 = 54,
71 RS1 = 55,
72 RS2 = 56,
73 RS3 = 57,
74 RS4 = 58,
75 VRFrame32 = 59,
76 VRFrame64 = 60,
77 VRFrameLocal32 = 61,
78 VRFrameLocal64 = 62,
79 NUM_TARGET_REGS // 63
80};
81} // end namespace NVPTX
82
83// Register classes
84
85namespace NVPTX {
86enum {
87 B1RegClassID = 0,
88 B16RegClassID = 1,
89 SpecialRegsRegClassID = 2,
90 B32RegClassID = 3,
91 B32_and_SpecialRegsRegClassID = 4,
92 B64RegClassID = 5,
93 B128RegClassID = 6,
94
95};
96} // end namespace NVPTX
97
98// Register pressure sets enum.
99namespace NVPTX {
100enum RegisterPressureSets {
101 B32_and_SpecialRegs = 0,
102 B1 = 1,
103 B16 = 2,
104 B128 = 3,
105 B32 = 4,
106 B64 = 5,
107 SpecialRegs = 6,
108 SpecialRegs_with_B32 = 7,
109};
110} // end namespace NVPTX
111
112} // end namespace llvm
113
114