1//===-- NVPTXInstPrinter.cpp - PTX assembly instruction printing ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Print MCInst instructions to .ptx format.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/NVPTXInstPrinter.h"
14#include "NVPTX.h"
15#include "NVPTXUtilities.h"
16#include "llvm/ADT/StringRef.h"
17#include "llvm/IR/NVVMIntrinsicUtils.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/MCSymbol.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/FormatVariadic.h"
26#include <cctype>
27using namespace llvm;
28
29#define DEBUG_TYPE "asm-printer"
30
31#define GET_SUBTARGETINFO_ENUM
32#include "NVPTXGenSubtargetInfo.inc"
33
34#include "NVPTXGenAsmWriter.inc"
35
36static bool hasParamSubqualifiers(const MCSubtargetInfo &STI) {
37 return STI.hasFeature(Feature: NVPTX::PTX83);
38}
39
40NVPTXInstPrinter::NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
41 const MCRegisterInfo &MRI)
42 : MCInstPrinter(MAI, MII, MRI) {}
43
44void NVPTXInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {
45 // Decode the virtual register
46 // Must be kept in sync with NVPTXAsmPrinter::encodeVirtualRegister
47 unsigned RCId = (Reg.id() >> 28);
48 switch (RCId) {
49 default: report_fatal_error(reason: "Bad virtual register encoding");
50 case 0:
51 // This is actually a physical register, so defer to the autogenerated
52 // register printer
53 OS << getRegisterName(Reg);
54 return;
55 case 1:
56 OS << "%p";
57 break;
58 case 2:
59 OS << "%rs";
60 break;
61 case 3:
62 OS << "%r";
63 break;
64 case 4:
65 OS << "%rd";
66 break;
67 case 5:
68 OS << "%f";
69 break;
70 case 6:
71 OS << "%fd";
72 break;
73 case 7:
74 OS << "%rq";
75 break;
76 }
77
78 unsigned VReg = Reg.id() & 0x0FFFFFFF;
79 OS << VReg;
80}
81
82void NVPTXInstPrinter::printInst(const MCInst *MI, uint64_t Address,
83 StringRef Annot, const MCSubtargetInfo &STI,
84 raw_ostream &OS) {
85 printInstruction(MI, Address, STI, O&: OS);
86
87 // Next always print the annotation.
88 printAnnotation(OS, Annot);
89}
90
91void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
92 const MCSubtargetInfo &, raw_ostream &O) {
93 const MCOperand &Op = MI->getOperand(i: OpNo);
94 if (Op.isReg()) {
95 MCRegister Reg = Op.getReg();
96 printRegName(OS&: O, Reg);
97 } else if (Op.isImm()) {
98 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Op.getImm());
99 } else {
100 assert(Op.isExpr() && "Unknown operand kind in printOperand");
101 MAI.printExpr(O, *Op.getExpr());
102 }
103}
104
105void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum,
106 const MCSubtargetInfo &, raw_ostream &O,
107 StringRef Modifier) {
108 const MCOperand &MO = MI->getOperand(i: OpNum);
109 int64_t Imm = MO.getImm();
110
111 if (Modifier == "ftz") {
112 // FTZ flag
113 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
114 O << ".ftz";
115 return;
116 } else if (Modifier == "sat") {
117 // SAT flag
118 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
119 O << ".sat";
120 return;
121 } else if (Modifier == "satfinite") {
122 // SATFINITE flag
123 if (Imm & NVPTX::PTXCvtMode::SATFINITE_FLAG)
124 O << ".satfinite";
125 return;
126 } else if (Modifier == "relu") {
127 // RELU flag
128 if (Imm & NVPTX::PTXCvtMode::RELU_FLAG)
129 O << ".relu";
130 return;
131 } else if (Modifier == "base") {
132 // Default operand
133 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
134 default:
135 return;
136 case NVPTX::PTXCvtMode::NONE:
137 return;
138 case NVPTX::PTXCvtMode::RNI:
139 O << ".rni";
140 return;
141 case NVPTX::PTXCvtMode::RZI:
142 O << ".rzi";
143 return;
144 case NVPTX::PTXCvtMode::RMI:
145 O << ".rmi";
146 return;
147 case NVPTX::PTXCvtMode::RPI:
148 O << ".rpi";
149 return;
150 case NVPTX::PTXCvtMode::RN:
151 O << ".rn";
152 return;
153 case NVPTX::PTXCvtMode::RZ:
154 O << ".rz";
155 return;
156 case NVPTX::PTXCvtMode::RM:
157 O << ".rm";
158 return;
159 case NVPTX::PTXCvtMode::RP:
160 O << ".rp";
161 return;
162 case NVPTX::PTXCvtMode::RNA:
163 O << ".rna";
164 return;
165 case NVPTX::PTXCvtMode::RS:
166 O << ".rs";
167 return;
168 }
169 }
170 llvm_unreachable("Invalid conversion modifier");
171}
172
173void NVPTXInstPrinter::printFTZFlag(const MCInst *MI, int OpNum,
174 const MCSubtargetInfo &, raw_ostream &O) {
175 const MCOperand &MO = MI->getOperand(i: OpNum);
176 const int Imm = MO.getImm();
177 if (Imm)
178 O << ".ftz";
179}
180
181void NVPTXInstPrinter::printMultimem(const MCInst *MI, int OpNum,
182 const MCSubtargetInfo &, raw_ostream &O) {
183 const MCOperand &MO = MI->getOperand(i: OpNum);
184 if (MO.getImm())
185 O << "multimem.";
186}
187
188void NVPTXInstPrinter::printNegatedPredicate(const MCInst *MI, int OpNum,
189 const MCSubtargetInfo &,
190 raw_ostream &O) {
191 if (MI->getOperand(i: OpNum).getImm())
192 O << "!";
193}
194
195void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum,
196 const MCSubtargetInfo &, raw_ostream &O,
197 StringRef Modifier) {
198 const MCOperand &MO = MI->getOperand(i: OpNum);
199 int64_t Imm = MO.getImm();
200
201 if (Modifier == "FCmp") {
202 switch (Imm) {
203 default:
204 return;
205 case NVPTX::PTXCmpMode::EQ:
206 O << "eq";
207 return;
208 case NVPTX::PTXCmpMode::NE:
209 O << "ne";
210 return;
211 case NVPTX::PTXCmpMode::LT:
212 O << "lt";
213 return;
214 case NVPTX::PTXCmpMode::LE:
215 O << "le";
216 return;
217 case NVPTX::PTXCmpMode::GT:
218 O << "gt";
219 return;
220 case NVPTX::PTXCmpMode::GE:
221 O << "ge";
222 return;
223 case NVPTX::PTXCmpMode::EQU:
224 O << "equ";
225 return;
226 case NVPTX::PTXCmpMode::NEU:
227 O << "neu";
228 return;
229 case NVPTX::PTXCmpMode::LTU:
230 O << "ltu";
231 return;
232 case NVPTX::PTXCmpMode::LEU:
233 O << "leu";
234 return;
235 case NVPTX::PTXCmpMode::GTU:
236 O << "gtu";
237 return;
238 case NVPTX::PTXCmpMode::GEU:
239 O << "geu";
240 return;
241 case NVPTX::PTXCmpMode::NUM:
242 O << "num";
243 return;
244 case NVPTX::PTXCmpMode::NotANumber:
245 O << "nan";
246 return;
247 }
248 }
249 if (Modifier == "ICmp") {
250 switch (Imm) {
251 default:
252 llvm_unreachable("Invalid ICmp mode");
253 case NVPTX::PTXCmpMode::EQ:
254 O << "eq";
255 return;
256 case NVPTX::PTXCmpMode::NE:
257 O << "ne";
258 return;
259 case NVPTX::PTXCmpMode::LT:
260 case NVPTX::PTXCmpMode::LTU:
261 O << "lt";
262 return;
263 case NVPTX::PTXCmpMode::LE:
264 case NVPTX::PTXCmpMode::LEU:
265 O << "le";
266 return;
267 case NVPTX::PTXCmpMode::GT:
268 case NVPTX::PTXCmpMode::GTU:
269 O << "gt";
270 return;
271 case NVPTX::PTXCmpMode::GE:
272 case NVPTX::PTXCmpMode::GEU:
273 O << "ge";
274 return;
275 }
276 }
277 if (Modifier == "IType") {
278 switch (Imm) {
279 default:
280 llvm_unreachable("Invalid IType");
281 case NVPTX::PTXCmpMode::EQ:
282 case NVPTX::PTXCmpMode::NE:
283 O << "b";
284 return;
285 case NVPTX::PTXCmpMode::LT:
286 case NVPTX::PTXCmpMode::LE:
287 case NVPTX::PTXCmpMode::GT:
288 case NVPTX::PTXCmpMode::GE:
289 O << "s";
290 return;
291 case NVPTX::PTXCmpMode::LTU:
292 case NVPTX::PTXCmpMode::LEU:
293 case NVPTX::PTXCmpMode::GTU:
294 case NVPTX::PTXCmpMode::GEU:
295 O << "u";
296 return;
297 }
298 }
299 llvm_unreachable("Empty Modifier");
300}
301
302void NVPTXInstPrinter::printAtomicCode(const MCInst *MI, int OpNum,
303 const MCSubtargetInfo &STI,
304 raw_ostream &O, StringRef Modifier) {
305 const MCOperand &MO = MI->getOperand(i: OpNum);
306 int Imm = (int)MO.getImm();
307 if (Modifier == "sem") {
308 auto Ordering = NVPTX::Ordering(Imm);
309 switch (Ordering) {
310 case NVPTX::Ordering::NotAtomic:
311 return;
312 case NVPTX::Ordering::Relaxed:
313 O << ".relaxed";
314 return;
315 case NVPTX::Ordering::Acquire:
316 O << ".acquire";
317 return;
318 case NVPTX::Ordering::Release:
319 O << ".release";
320 return;
321 case NVPTX::Ordering::AcquireRelease:
322 O << ".acq_rel";
323 return;
324 case NVPTX::Ordering::SequentiallyConsistent:
325 report_fatal_error(
326 reason: "NVPTX AtomicCode Printer does not support \"seq_cst\" ordering.");
327 return;
328 case NVPTX::Ordering::Volatile:
329 O << ".volatile";
330 return;
331 case NVPTX::Ordering::RelaxedMMIO:
332 O << ".mmio.relaxed";
333 return;
334 }
335 } else if (Modifier == "scope") {
336 auto S = NVPTX::Scope(Imm);
337 switch (S) {
338 case NVPTX::Scope::Thread:
339 case NVPTX::Scope::DefaultDevice:
340 return;
341 case NVPTX::Scope::System:
342 O << ".sys";
343 return;
344 case NVPTX::Scope::Block:
345 O << ".cta";
346 return;
347 case NVPTX::Scope::Cluster:
348 O << ".cluster";
349 return;
350 case NVPTX::Scope::Device:
351 O << ".gpu";
352 return;
353 }
354 report_fatal_error(reason: formatv(
355 Fmt: "NVPTX AtomicCode Printer does not support \"{}\" scope modifier.",
356 Vals: ScopeToString(S)));
357 } else if (Modifier == "addsp") {
358 auto A = NVPTX::AddressSpace(Imm);
359 switch (A) {
360 case NVPTX::AddressSpace::Generic:
361 return;
362 case NVPTX::AddressSpace::Global:
363 case NVPTX::AddressSpace::Const:
364 case NVPTX::AddressSpace::Shared:
365 case NVPTX::AddressSpace::SharedCluster:
366 case NVPTX::AddressSpace::EntryParam:
367 case NVPTX::AddressSpace::DeviceParam:
368 case NVPTX::AddressSpace::Local:
369 O << "." << addressSpaceToString(A, UseParamSubqualifiers: hasParamSubqualifiers(STI));
370 return;
371 }
372 report_fatal_error(reason: formatv(
373 Fmt: "NVPTX AtomicCode Printer does not support \"{}\" addsp modifier.",
374 Vals: addressSpaceToString(A)));
375 } else if (Modifier == "sign") {
376 switch (Imm) {
377 case NVPTX::PTXLdStInstCode::Signed:
378 O << "s";
379 return;
380 case NVPTX::PTXLdStInstCode::Unsigned:
381 O << "u";
382 return;
383 case NVPTX::PTXLdStInstCode::Untyped:
384 O << "b";
385 return;
386 case NVPTX::PTXLdStInstCode::Float:
387 O << "f";
388 return;
389 default:
390 llvm_unreachable("Unknown register type");
391 }
392 }
393 llvm_unreachable(formatv("Unknown Modifier: {}", Modifier).str().c_str());
394}
395
396void NVPTXInstPrinter::printMmaCode(const MCInst *MI, int OpNum,
397 const MCSubtargetInfo &, raw_ostream &O,
398 StringRef Modifier) {
399 const MCOperand &MO = MI->getOperand(i: OpNum);
400 int Imm = (int)MO.getImm();
401 if (Modifier.empty() || Modifier == "version") {
402 O << Imm; // Just print out PTX version
403 return;
404 } else if (Modifier == "aligned") {
405 // PTX63 requires '.aligned' in the name of the instruction.
406 if (Imm >= 63)
407 O << ".aligned";
408 return;
409 }
410 llvm_unreachable("Unknown Modifier");
411}
412
413void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum,
414 const MCSubtargetInfo &STI,
415 raw_ostream &O, StringRef Modifier) {
416 printOperand(MI, OpNo: OpNum, STI, O);
417
418 if (Modifier == "add") {
419 O << ", ";
420 printOperand(MI, OpNo: OpNum + 1, STI, O);
421 } else {
422 if (MI->getOperand(i: OpNum + 1).isImm() &&
423 MI->getOperand(i: OpNum + 1).getImm() == 0)
424 return; // don't print ',0' or '+0'
425 O << "+";
426 printOperand(MI, OpNo: OpNum + 1, STI, O);
427 }
428}
429
430void NVPTXInstPrinter::printUsedBytesMaskPragma(const MCInst *MI, int OpNum,
431 const MCSubtargetInfo &,
432 raw_ostream &O) {
433 auto &Op = MI->getOperand(i: OpNum);
434 assert(Op.isImm() && "Invalid operand");
435 uint32_t Imm = (uint32_t)Op.getImm();
436 if (Imm != UINT32_MAX) {
437 O << ".pragma \"used_bytes_mask " << format_hex(N: Imm, Width: 1) << "\";\n\t";
438 }
439}
440
441void NVPTXInstPrinter::printRegisterOrSinkSymbol(const MCInst *MI, int OpNum,
442 const MCSubtargetInfo &STI,
443 raw_ostream &O) {
444 const MCOperand &Op = MI->getOperand(i: OpNum);
445 if (Op.isReg() && Op.getReg() == MCRegister::NoRegister)
446 O << "_";
447 else
448 printOperand(MI, OpNo: OpNum, STI, O);
449}
450
451void NVPTXInstPrinter::printHexu32imm(const MCInst *MI, int OpNum,
452 const MCSubtargetInfo &, raw_ostream &O) {
453 int64_t Imm = MI->getOperand(i: OpNum).getImm();
454 O << formatHex(Value: Imm) << "U";
455}
456
457void NVPTXInstPrinter::printPrmtMode(const MCInst *MI, int OpNum,
458 const MCSubtargetInfo &, raw_ostream &O) {
459 const MCOperand &MO = MI->getOperand(i: OpNum);
460 int64_t Imm = MO.getImm();
461
462 switch (Imm) {
463 default:
464 return;
465 case NVPTX::PTXPrmtMode::NONE:
466 return;
467 case NVPTX::PTXPrmtMode::F4E:
468 O << ".f4e";
469 return;
470 case NVPTX::PTXPrmtMode::B4E:
471 O << ".b4e";
472 return;
473 case NVPTX::PTXPrmtMode::RC8:
474 O << ".rc8";
475 return;
476 case NVPTX::PTXPrmtMode::ECL:
477 O << ".ecl";
478 return;
479 case NVPTX::PTXPrmtMode::ECR:
480 O << ".ecr";
481 return;
482 case NVPTX::PTXPrmtMode::RC16:
483 O << ".rc16";
484 return;
485 }
486}
487
488void NVPTXInstPrinter::printTmaReductionMode(const MCInst *MI, int OpNum,
489 const MCSubtargetInfo &,
490 raw_ostream &O) {
491 const MCOperand &MO = MI->getOperand(i: OpNum);
492 using RedTy = nvvm::TMAReductionOp;
493
494 switch (static_cast<RedTy>(MO.getImm())) {
495 case RedTy::ADD:
496 O << ".add";
497 return;
498 case RedTy::MIN:
499 O << ".min";
500 return;
501 case RedTy::MAX:
502 O << ".max";
503 return;
504 case RedTy::INC:
505 O << ".inc";
506 return;
507 case RedTy::DEC:
508 O << ".dec";
509 return;
510 case RedTy::AND:
511 O << ".and";
512 return;
513 case RedTy::OR:
514 O << ".or";
515 return;
516 case RedTy::XOR:
517 O << ".xor";
518 return;
519 }
520 llvm_unreachable(
521 "Invalid Reduction Op in printCpAsyncBulkTensorReductionMode");
522}
523
524void NVPTXInstPrinter::printCTAGroup(const MCInst *MI, int OpNum,
525 const MCSubtargetInfo &, raw_ostream &O) {
526 const MCOperand &MO = MI->getOperand(i: OpNum);
527 using CGTy = nvvm::CTAGroupKind;
528
529 switch (static_cast<CGTy>(MO.getImm())) {
530 case CGTy::CG_NONE:
531 O << "";
532 return;
533 case CGTy::CG_1:
534 O << ".cta_group::1";
535 return;
536 case CGTy::CG_2:
537 O << ".cta_group::2";
538 return;
539 }
540 llvm_unreachable("Invalid cta_group in printCTAGroup");
541}
542
543void NVPTXInstPrinter::printCallOperand(const MCInst *MI, int OpNum,
544 const MCSubtargetInfo &, raw_ostream &O,
545 StringRef Modifier) {
546 const MCOperand &MO = MI->getOperand(i: OpNum);
547 assert(MO.isImm() && "Invalid operand");
548 const auto Imm = MO.getImm();
549
550 if (Modifier == "RetList") {
551 assert((Imm == 1 || Imm == 0) && "Invalid return list");
552 if (Imm)
553 O << " (retval0),";
554 return;
555 }
556
557 if (Modifier == "ParamList") {
558 assert(Imm >= 0 && "Invalid parameter list");
559 interleaveComma(c: llvm::seq(Size: Imm), os&: O,
560 each_fn: [&](const auto &I) { O << "param" << I; });
561 return;
562 }
563 llvm_unreachable("Invalid modifier");
564}
565
566template <unsigned Bits>
567void NVPTXInstPrinter::printHexUImm(const MCInst *MI, int OpNum,
568 const MCSubtargetInfo &, raw_ostream &O) {
569 const MCOperand &MO = MI->getOperand(i: OpNum);
570 assert(MO.isImm() && "Expected immediate operand");
571 assert(isInt<Bits>(MO.getImm()) &&
572 "Immediate value does not fit in specified bits");
573 uint64_t Imm = MO.getImm();
574 Imm &= maskTrailingOnes<uint64_t>(N: Bits);
575 O << formatHex(Value: Imm) << "U";
576}
577