1//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in
10// the LLVM NVPTX back-end.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
15#define LLVM_LIB_TARGET_NVPTX_NVPTX_H
16
17#include "llvm/CodeGen/ISDOpcodes.h"
18#include "llvm/IR/PassManager.h"
19#include "llvm/Pass.h"
20#include "llvm/Support/AtomicOrdering.h"
21#include "llvm/Support/CodeGen.h"
22#include "llvm/Target/TargetMachine.h"
23namespace llvm {
24class FunctionPass;
25class MachineFunctionPass;
26class NVPTXTargetMachine;
27class PassRegistry;
28
29namespace NVPTXCC {
30enum CondCodes {
31 EQ,
32 NE,
33 LT,
34 LE,
35 GT,
36 GE
37};
38}
39
40FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
41 llvm::CodeGenOptLevel OptLevel);
42ModulePass *createNVPTXAssignValidGlobalNamesPass();
43ModulePass *createGenericToNVVMLegacyPass();
44ModulePass *createNVPTXCtorDtorLoweringLegacyPass();
45FunctionPass *createNVVMIntrRangePass();
46ModulePass *createNVVMReflectPass(unsigned int SmVersion);
47MachineFunctionPass *createNVPTXPrologEpilogPass();
48MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
49FunctionPass *createNVPTXImageOptimizerPass();
50FunctionPass *createNVPTXLowerArgsPass();
51FunctionPass *createNVPTXLowerAllocaPass();
52FunctionPass *createNVPTXLowerUnreachablePass(bool TrapUnreachable,
53 bool NoTrapAfterNoreturn);
54FunctionPass *createNVPTXTagInvariantLoadsPass();
55FunctionPass *createNVPTXIRPeepholePass();
56MachineFunctionPass *createNVPTXPeephole();
57MachineFunctionPass *createNVPTXProxyRegErasurePass();
58MachineFunctionPass *createNVPTXForwardParamsPass();
59
60void initializeNVVMReflectLegacyPassPass(PassRegistry &);
61void initializeGenericToNVVMLegacyPassPass(PassRegistry &);
62void initializeNVPTXAllocaHoistingPass(PassRegistry &);
63void initializeNVPTXAsmPrinterPass(PassRegistry &);
64void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &);
65void initializeNVPTXAtomicLowerPass(PassRegistry &);
66void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &);
67void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
68void initializeNVPTXLowerAllocaPass(PassRegistry &);
69void initializeNVPTXLowerUnreachablePass(PassRegistry &);
70void initializeNVPTXLowerArgsLegacyPassPass(PassRegistry &);
71void initializeNVPTXProxyRegErasurePass(PassRegistry &);
72void initializeNVPTXForwardParamsPassPass(PassRegistry &);
73void initializeNVVMIntrRangePass(PassRegistry &);
74void initializeNVVMReflectPass(PassRegistry &);
75void initializeNVPTXAAWrapperPassPass(PassRegistry &);
76void initializeNVPTXExternalAAWrapperPass(PassRegistry &);
77void initializeNVPTXPeepholePass(PassRegistry &);
78void initializeNVPTXTagInvariantLoadLegacyPassPass(PassRegistry &);
79void initializeNVPTXIRPeepholePass(PassRegistry &);
80void initializeNVPTXPrologEpilogPassPass(PassRegistry &);
81
82struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> {
83 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
84};
85
86struct NVPTXIRPeepholePass : PassInfoMixin<NVPTXIRPeepholePass> {
87 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
88};
89
90struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> {
91 NVVMReflectPass() : SmVersion(0) {}
92 NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {}
93 PreservedAnalyses run(Module &F, ModuleAnalysisManager &AM);
94
95private:
96 unsigned SmVersion;
97};
98
99struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> {
100 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
101};
102
103struct NVPTXCopyByValArgsPass : PassInfoMixin<NVPTXCopyByValArgsPass> {
104 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
105};
106
107struct NVPTXLowerArgsPass : PassInfoMixin<NVPTXLowerArgsPass> {
108private:
109 TargetMachine &TM;
110
111public:
112 NVPTXLowerArgsPass(TargetMachine &TM) : TM(TM) {};
113 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
114};
115
116struct NVPTXTagInvariantLoadsPass : PassInfoMixin<NVPTXTagInvariantLoadsPass> {
117 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
118};
119
120namespace NVPTX {
121enum DrvInterface {
122 NVCL,
123 CUDA
124};
125
126// A field inside TSFlags needs a shift and a mask. The usage is
127// always as follows :
128// ((TSFlags & fieldMask) >> fieldShift)
129// The enum keeps the mask, the shift, and all valid values of the
130// field in one place.
131enum VecInstType {
132 VecInstTypeShift = 0,
133 VecInstTypeMask = 0xF,
134
135 VecNOP = 0,
136 VecLoad = 1,
137 VecStore = 2,
138 VecBuild = 3,
139 VecShuffle = 4,
140 VecExtract = 5,
141 VecInsert = 6,
142 VecDest = 7,
143 VecOther = 15
144};
145
146enum SimpleMove {
147 SimpleMoveMask = 0x10,
148 SimpleMoveShift = 4
149};
150enum LoadStore {
151 isLoadMask = 0x20,
152 isLoadShift = 5,
153 isStoreMask = 0x40,
154 isStoreShift = 6
155};
156
157// Extends LLVM AtomicOrdering with PTX Orderings:
158using OrderingUnderlyingType = unsigned int;
159enum Ordering : OrderingUnderlyingType {
160 NotAtomic = (OrderingUnderlyingType)
161 AtomicOrdering::NotAtomic, // PTX calls these: "Weak"
162 // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed
163 Relaxed = (OrderingUnderlyingType)AtomicOrdering::Monotonic,
164 // Consume = 3, // Unimplemented in LLVM; NVPTX would map to "Acquire"
165 Acquire = (OrderingUnderlyingType)AtomicOrdering::Acquire,
166 Release = (OrderingUnderlyingType)AtomicOrdering::Release,
167 AcquireRelease = (OrderingUnderlyingType)AtomicOrdering::AcquireRelease,
168 SequentiallyConsistent =
169 (OrderingUnderlyingType)AtomicOrdering::SequentiallyConsistent,
170 Volatile = SequentiallyConsistent + 1,
171 RelaxedMMIO = Volatile + 1,
172};
173
174using ScopeUnderlyingType = unsigned int;
175enum Scope : ScopeUnderlyingType {
176 Thread = 0,
177 Block = 1,
178 Cluster = 2,
179 Device = 3,
180 System = 4,
181 DefaultDevice = 5, // For SM < 70: denotes PTX op implicit/default .gpu scope
182 LASTSCOPE = DefaultDevice
183};
184
185using AddressSpaceUnderlyingType = unsigned int;
186enum AddressSpace : AddressSpaceUnderlyingType {
187 Generic = 0,
188 Global = 1,
189 Shared = 3,
190 Const = 4,
191 Local = 5,
192 SharedCluster = 7,
193
194 // NVPTX Backend Private:
195 Param = 101
196};
197
198namespace PTXLdStInstCode {
199enum FromType { Unsigned = 0, Signed, Float, Untyped };
200} // namespace PTXLdStInstCode
201
202/// PTXCvtMode - Conversion code enumeration
203namespace PTXCvtMode {
204enum CvtMode {
205 NONE = 0,
206 RNI,
207 RZI,
208 RMI,
209 RPI,
210 RN,
211 RZ,
212 RM,
213 RP,
214 RNA,
215 RS,
216
217 BASE_MASK = 0x0F,
218 FTZ_FLAG = 0x10,
219 SAT_FLAG = 0x20,
220 RELU_FLAG = 0x40
221};
222}
223
224/// PTXCmpMode - Comparison mode enumeration
225namespace PTXCmpMode {
226enum CmpMode {
227 EQ = 0,
228 NE,
229 LT,
230 LE,
231 GT,
232 GE,
233 EQU,
234 NEU,
235 LTU,
236 LEU,
237 GTU,
238 GEU,
239 NUM,
240 // NAN is a MACRO
241 NotANumber,
242};
243}
244
245namespace PTXPrmtMode {
246enum PrmtMode {
247 NONE,
248 F4E,
249 B4E,
250 RC8,
251 ECL,
252 ECR,
253 RC16,
254};
255}
256
257enum class DivPrecisionLevel : unsigned {
258 Approx = 0,
259 Full = 1,
260 IEEE754 = 2,
261 IEEE754_NoFTZ = 3,
262};
263
264} // namespace NVPTX
265void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &);
266} // namespace llvm
267
268// Defines symbolic names for NVPTX registers. This defines a mapping from
269// register name to register number.
270#define GET_REGINFO_ENUM
271#include "NVPTXGenRegisterInfo.inc"
272
273// Defines symbolic names for the NVPTX instructions.
274#define GET_INSTRINFO_ENUM
275#define GET_INSTRINFO_MC_HELPER_DECLS
276#include "NVPTXGenInstrInfo.inc"
277
278#endif
279