1//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in
10// the LLVM NVPTX back-end.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
15#define LLVM_LIB_TARGET_NVPTX_NVPTX_H
16
17#include "llvm/IR/PassManager.h"
18#include "llvm/Pass.h"
19#include "llvm/Support/AtomicOrdering.h"
20#include "llvm/Support/CodeGen.h"
21#include "llvm/Support/NVPTXAddrSpace.h"
22#include "llvm/Target/TargetMachine.h"
23
24namespace llvm {
25class FunctionPass;
26class MachineFunctionPass;
27class NVPTXTargetMachine;
28class PassRegistry;
29
30namespace NVPTXCC {
31enum CondCodes {
32 EQ,
33 NE,
34 LT,
35 LE,
36 GT,
37 GE
38};
39}
40
41FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
42 llvm::CodeGenOptLevel OptLevel);
43ModulePass *createNVPTXAssignValidGlobalNamesPass();
44ModulePass *createGenericToNVVMLegacyPass();
45ModulePass *createNVPTXCtorDtorLoweringLegacyPass();
46FunctionPass *createNVVMIntrRangePass();
47ModulePass *createNVVMReflectPass(unsigned int SmVersion);
48MachineFunctionPass *createNVPTXPrologEpilogPass();
49MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
50FunctionPass *createNVPTXImageOptimizerPass();
51FunctionPass *createNVPTXLowerArgsPass();
52FunctionPass *createNVPTXSetByValParamAlignPass();
53FunctionPass *createNVPTXLowerAllocaPass();
54FunctionPass *createNVPTXLowerUnreachablePass(bool TrapUnreachable,
55 bool NoTrapAfterNoreturn);
56FunctionPass *createNVPTXMarkKernelPtrsGlobalPass();
57FunctionPass *createNVPTXTagInvariantLoadsPass();
58FunctionPass *createNVPTXIRPeepholePass();
59MachineFunctionPass *createNVPTXPeephole();
60MachineFunctionPass *createNVPTXProxyRegErasurePass();
61MachineFunctionPass *createNVPTXForwardParamsPass();
62
63void initializeNVVMReflectLegacyPassPass(PassRegistry &);
64void initializeGenericToNVVMLegacyPassPass(PassRegistry &);
65void initializeNVPTXAllocaHoistingPass(PassRegistry &);
66void initializeNVPTXAsmPrinterPass(PassRegistry &);
67void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &);
68void initializeNVPTXAtomicLowerPass(PassRegistry &);
69void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &);
70void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
71void initializeNVPTXLowerAllocaPass(PassRegistry &);
72void initializeNVPTXLowerUnreachablePass(PassRegistry &);
73void initializeNVPTXLowerArgsLegacyPassPass(PassRegistry &);
74void initializeNVPTXSetByValParamAlignLegacyPassPass(PassRegistry &);
75void initializeNVPTXProxyRegErasurePass(PassRegistry &);
76void initializeNVPTXForwardParamsPassPass(PassRegistry &);
77void initializeNVVMIntrRangePass(PassRegistry &);
78void initializeNVVMReflectPass(PassRegistry &);
79void initializeNVPTXAAWrapperPassPass(PassRegistry &);
80void initializeNVPTXExternalAAWrapperPass(PassRegistry &);
81void initializeNVPTXPeepholePass(PassRegistry &);
82void initializeNVPTXMarkKernelPtrsGlobalLegacyPassPass(PassRegistry &);
83void initializeNVPTXTagInvariantLoadLegacyPassPass(PassRegistry &);
84void initializeNVPTXIRPeepholePass(PassRegistry &);
85void initializeNVPTXPrologEpilogPassPass(PassRegistry &);
86
87struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> {
88 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
89};
90
91struct NVPTXIRPeepholePass : PassInfoMixin<NVPTXIRPeepholePass> {
92 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
93};
94
95struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> {
96 NVVMReflectPass() : SmVersion(0) {}
97 NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {}
98 PreservedAnalyses run(Module &F, ModuleAnalysisManager &AM);
99
100private:
101 unsigned SmVersion;
102};
103
104struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> {
105 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
106};
107
108struct NVPTXCopyByValArgsPass : PassInfoMixin<NVPTXCopyByValArgsPass> {
109 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
110};
111
112struct NVPTXSetByValParamAlignPass
113 : PassInfoMixin<NVPTXSetByValParamAlignPass> {
114 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
115};
116
117struct NVPTXLowerArgsPass : PassInfoMixin<NVPTXLowerArgsPass> {
118private:
119 TargetMachine &TM;
120
121public:
122 NVPTXLowerArgsPass(TargetMachine &TM) : TM(TM) {};
123 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
124};
125
126struct NVPTXMarkKernelPtrsGlobalPass
127 : PassInfoMixin<NVPTXMarkKernelPtrsGlobalPass> {
128 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
129};
130
131struct NVPTXTagInvariantLoadsPass : PassInfoMixin<NVPTXTagInvariantLoadsPass> {
132 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
133};
134
135namespace NVPTX {
136enum DrvInterface {
137 NVCL,
138 CUDA
139};
140
141// A field inside TSFlags needs a shift and a mask. The usage is
142// always as follows :
143// ((TSFlags & fieldMask) >> fieldShift)
144// The enum keeps the mask, the shift, and all valid values of the
145// field in one place.
146enum VecInstType {
147 VecInstTypeShift = 0,
148 VecInstTypeMask = 0xF,
149
150 VecNOP = 0,
151 VecLoad = 1,
152 VecStore = 2,
153 VecBuild = 3,
154 VecShuffle = 4,
155 VecExtract = 5,
156 VecInsert = 6,
157 VecDest = 7,
158 VecOther = 15
159};
160
161enum SimpleMove {
162 SimpleMoveMask = 0x10,
163 SimpleMoveShift = 4
164};
165enum LoadStore {
166 isLoadMask = 0x20,
167 isLoadShift = 5,
168 isStoreMask = 0x40,
169 isStoreShift = 6
170};
171
172// Extends LLVM AtomicOrdering with PTX Orderings:
173using OrderingUnderlyingType = unsigned int;
174enum Ordering : OrderingUnderlyingType {
175 NotAtomic = (OrderingUnderlyingType)
176 AtomicOrdering::NotAtomic, // PTX calls these: "Weak"
177 // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed
178 Relaxed = (OrderingUnderlyingType)AtomicOrdering::Monotonic,
179 // Consume = 3, // Unimplemented in LLVM; NVPTX would map to "Acquire"
180 Acquire = (OrderingUnderlyingType)AtomicOrdering::Acquire,
181 Release = (OrderingUnderlyingType)AtomicOrdering::Release,
182 AcquireRelease = (OrderingUnderlyingType)AtomicOrdering::AcquireRelease,
183 SequentiallyConsistent =
184 (OrderingUnderlyingType)AtomicOrdering::SequentiallyConsistent,
185 Volatile = SequentiallyConsistent + 1,
186 RelaxedMMIO = Volatile + 1,
187};
188
189using ScopeUnderlyingType = unsigned int;
190enum Scope : ScopeUnderlyingType {
191 Thread = 0,
192 Block = 1,
193 Cluster = 2,
194 Device = 3,
195 System = 4,
196 DefaultDevice = 5, // For SM < 70: denotes PTX op implicit/default .gpu scope
197 LASTSCOPE = DefaultDevice
198};
199
200using AddressSpaceUnderlyingType = unsigned int;
201enum AddressSpace : AddressSpaceUnderlyingType {
202 Generic = NVPTXAS::ADDRESS_SPACE_GENERIC,
203 Global = NVPTXAS::ADDRESS_SPACE_GLOBAL,
204 Shared = NVPTXAS::ADDRESS_SPACE_SHARED,
205 Const = NVPTXAS::ADDRESS_SPACE_CONST,
206 Local = NVPTXAS::ADDRESS_SPACE_LOCAL,
207 SharedCluster = NVPTXAS::ADDRESS_SPACE_SHARED_CLUSTER,
208 EntryParam = NVPTXAS::ADDRESS_SPACE_ENTRY_PARAM,
209
210 // DeviceParam is not a real address space, as it does not support pointers
211 // and instead can only be referenced by param+offset. For this reason it is
212 // only used in MIR as an instruction modifier and should not be used in LLVM
213 // IR.
214 DeviceParam
215};
216
217namespace PTXLdStInstCode {
218enum FromType { Unsigned = 0, Signed, Float, Untyped };
219} // namespace PTXLdStInstCode
220
221/// PTXCvtMode - Conversion code enumeration
222namespace PTXCvtMode {
223enum CvtMode {
224 NONE = 0,
225 RNI,
226 RZI,
227 RMI,
228 RPI,
229 RN,
230 RZ,
231 RM,
232 RP,
233 RNA,
234 RS,
235
236 BASE_MASK = 0x0F,
237 FTZ_FLAG = 0x10,
238 SAT_FLAG = 0x20,
239 RELU_FLAG = 0x40
240};
241}
242
243/// PTXCmpMode - Comparison mode enumeration
244namespace PTXCmpMode {
245enum CmpMode {
246 EQ = 0,
247 NE,
248 LT,
249 LE,
250 GT,
251 GE,
252 EQU,
253 NEU,
254 LTU,
255 LEU,
256 GTU,
257 GEU,
258 NUM,
259 // NAN is a MACRO
260 NotANumber,
261};
262}
263
264namespace PTXPrmtMode {
265enum PrmtMode {
266 NONE,
267 F4E,
268 B4E,
269 RC8,
270 ECL,
271 ECR,
272 RC16,
273};
274}
275
276enum class DivPrecisionLevel : unsigned {
277 Approx = 0,
278 Full = 1,
279 IEEE754 = 2,
280 IEEE754_NoFTZ = 3,
281};
282
283} // namespace NVPTX
284void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &);
285} // namespace llvm
286
287// Defines symbolic names for NVPTX registers. This defines a mapping from
288// register name to register number.
289#define GET_REGINFO_ENUM
290#include "NVPTXGenRegisterInfo.inc"
291
292// Defines symbolic names for the NVPTX instructions.
293#define GET_INSTRINFO_ENUM
294#define GET_INSTRINFO_MC_HELPER_DECLS
295#include "NVPTXGenInstrInfo.inc"
296
297#endif
298