1//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in
10// the LLVM NVPTX back-end.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
15#define LLVM_LIB_TARGET_NVPTX_NVPTX_H
16
17#include "llvm/CodeGen/ISDOpcodes.h"
18#include "llvm/IR/PassManager.h"
19#include "llvm/Pass.h"
20#include "llvm/Support/AtomicOrdering.h"
21#include "llvm/Support/CodeGen.h"
22#include "llvm/Target/TargetMachine.h"
23namespace llvm {
24class FunctionPass;
25class MachineFunctionPass;
26class NVPTXTargetMachine;
27class PassRegistry;
28
29namespace NVPTXCC {
30enum CondCodes {
31 EQ,
32 NE,
33 LT,
34 LE,
35 GT,
36 GE
37};
38}
39
40FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
41 llvm::CodeGenOptLevel OptLevel);
42ModulePass *createNVPTXAssignValidGlobalNamesPass();
43ModulePass *createGenericToNVVMLegacyPass();
44ModulePass *createNVPTXCtorDtorLoweringLegacyPass();
45FunctionPass *createNVVMIntrRangePass();
46ModulePass *createNVVMReflectPass(unsigned int SmVersion);
47MachineFunctionPass *createNVPTXPrologEpilogPass();
48MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
49FunctionPass *createNVPTXImageOptimizerPass();
50FunctionPass *createNVPTXLowerArgsPass();
51FunctionPass *createNVPTXLowerAllocaPass();
52FunctionPass *createNVPTXLowerUnreachablePass(bool TrapUnreachable,
53 bool NoTrapAfterNoreturn);
54FunctionPass *createNVPTXMarkKernelPtrsGlobalPass();
55FunctionPass *createNVPTXTagInvariantLoadsPass();
56FunctionPass *createNVPTXIRPeepholePass();
57MachineFunctionPass *createNVPTXPeephole();
58MachineFunctionPass *createNVPTXProxyRegErasurePass();
59MachineFunctionPass *createNVPTXForwardParamsPass();
60
61void initializeNVVMReflectLegacyPassPass(PassRegistry &);
62void initializeGenericToNVVMLegacyPassPass(PassRegistry &);
63void initializeNVPTXAllocaHoistingPass(PassRegistry &);
64void initializeNVPTXAsmPrinterPass(PassRegistry &);
65void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &);
66void initializeNVPTXAtomicLowerPass(PassRegistry &);
67void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &);
68void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
69void initializeNVPTXLowerAllocaPass(PassRegistry &);
70void initializeNVPTXLowerUnreachablePass(PassRegistry &);
71void initializeNVPTXLowerArgsLegacyPassPass(PassRegistry &);
72void initializeNVPTXProxyRegErasurePass(PassRegistry &);
73void initializeNVPTXForwardParamsPassPass(PassRegistry &);
74void initializeNVVMIntrRangePass(PassRegistry &);
75void initializeNVVMReflectPass(PassRegistry &);
76void initializeNVPTXAAWrapperPassPass(PassRegistry &);
77void initializeNVPTXExternalAAWrapperPass(PassRegistry &);
78void initializeNVPTXPeepholePass(PassRegistry &);
79void initializeNVPTXMarkKernelPtrsGlobalLegacyPassPass(PassRegistry &);
80void initializeNVPTXTagInvariantLoadLegacyPassPass(PassRegistry &);
81void initializeNVPTXIRPeepholePass(PassRegistry &);
82void initializeNVPTXPrologEpilogPassPass(PassRegistry &);
83
84struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> {
85 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
86};
87
88struct NVPTXIRPeepholePass : PassInfoMixin<NVPTXIRPeepholePass> {
89 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
90};
91
92struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> {
93 NVVMReflectPass() : SmVersion(0) {}
94 NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {}
95 PreservedAnalyses run(Module &F, ModuleAnalysisManager &AM);
96
97private:
98 unsigned SmVersion;
99};
100
101struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> {
102 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
103};
104
105struct NVPTXCopyByValArgsPass : PassInfoMixin<NVPTXCopyByValArgsPass> {
106 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
107};
108
109struct NVPTXLowerArgsPass : PassInfoMixin<NVPTXLowerArgsPass> {
110private:
111 TargetMachine &TM;
112
113public:
114 NVPTXLowerArgsPass(TargetMachine &TM) : TM(TM) {};
115 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
116};
117
118struct NVPTXMarkKernelPtrsGlobalPass
119 : PassInfoMixin<NVPTXMarkKernelPtrsGlobalPass> {
120 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
121};
122
123struct NVPTXTagInvariantLoadsPass : PassInfoMixin<NVPTXTagInvariantLoadsPass> {
124 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
125};
126
127namespace NVPTX {
128enum DrvInterface {
129 NVCL,
130 CUDA
131};
132
133// A field inside TSFlags needs a shift and a mask. The usage is
134// always as follows :
135// ((TSFlags & fieldMask) >> fieldShift)
136// The enum keeps the mask, the shift, and all valid values of the
137// field in one place.
138enum VecInstType {
139 VecInstTypeShift = 0,
140 VecInstTypeMask = 0xF,
141
142 VecNOP = 0,
143 VecLoad = 1,
144 VecStore = 2,
145 VecBuild = 3,
146 VecShuffle = 4,
147 VecExtract = 5,
148 VecInsert = 6,
149 VecDest = 7,
150 VecOther = 15
151};
152
153enum SimpleMove {
154 SimpleMoveMask = 0x10,
155 SimpleMoveShift = 4
156};
157enum LoadStore {
158 isLoadMask = 0x20,
159 isLoadShift = 5,
160 isStoreMask = 0x40,
161 isStoreShift = 6
162};
163
164// Extends LLVM AtomicOrdering with PTX Orderings:
165using OrderingUnderlyingType = unsigned int;
166enum Ordering : OrderingUnderlyingType {
167 NotAtomic = (OrderingUnderlyingType)
168 AtomicOrdering::NotAtomic, // PTX calls these: "Weak"
169 // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed
170 Relaxed = (OrderingUnderlyingType)AtomicOrdering::Monotonic,
171 // Consume = 3, // Unimplemented in LLVM; NVPTX would map to "Acquire"
172 Acquire = (OrderingUnderlyingType)AtomicOrdering::Acquire,
173 Release = (OrderingUnderlyingType)AtomicOrdering::Release,
174 AcquireRelease = (OrderingUnderlyingType)AtomicOrdering::AcquireRelease,
175 SequentiallyConsistent =
176 (OrderingUnderlyingType)AtomicOrdering::SequentiallyConsistent,
177 Volatile = SequentiallyConsistent + 1,
178 RelaxedMMIO = Volatile + 1,
179};
180
181using ScopeUnderlyingType = unsigned int;
182enum Scope : ScopeUnderlyingType {
183 Thread = 0,
184 Block = 1,
185 Cluster = 2,
186 Device = 3,
187 System = 4,
188 DefaultDevice = 5, // For SM < 70: denotes PTX op implicit/default .gpu scope
189 LASTSCOPE = DefaultDevice
190};
191
192using AddressSpaceUnderlyingType = unsigned int;
193enum AddressSpace : AddressSpaceUnderlyingType {
194 Generic = 0,
195 Global = 1,
196 Shared = 3,
197 Const = 4,
198 Local = 5,
199 SharedCluster = 7,
200
201 // NVPTX Backend Private:
202 Param = 101
203};
204
205namespace PTXLdStInstCode {
206enum FromType { Unsigned = 0, Signed, Float, Untyped };
207} // namespace PTXLdStInstCode
208
209/// PTXCvtMode - Conversion code enumeration
210namespace PTXCvtMode {
211enum CvtMode {
212 NONE = 0,
213 RNI,
214 RZI,
215 RMI,
216 RPI,
217 RN,
218 RZ,
219 RM,
220 RP,
221 RNA,
222 RS,
223
224 BASE_MASK = 0x0F,
225 FTZ_FLAG = 0x10,
226 SAT_FLAG = 0x20,
227 RELU_FLAG = 0x40
228};
229}
230
231/// PTXCmpMode - Comparison mode enumeration
232namespace PTXCmpMode {
233enum CmpMode {
234 EQ = 0,
235 NE,
236 LT,
237 LE,
238 GT,
239 GE,
240 EQU,
241 NEU,
242 LTU,
243 LEU,
244 GTU,
245 GEU,
246 NUM,
247 // NAN is a MACRO
248 NotANumber,
249};
250}
251
252namespace PTXPrmtMode {
253enum PrmtMode {
254 NONE,
255 F4E,
256 B4E,
257 RC8,
258 ECL,
259 ECR,
260 RC16,
261};
262}
263
264enum class DivPrecisionLevel : unsigned {
265 Approx = 0,
266 Full = 1,
267 IEEE754 = 2,
268 IEEE754_NoFTZ = 3,
269};
270
271} // namespace NVPTX
272void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &);
273} // namespace llvm
274
275// Defines symbolic names for NVPTX registers. This defines a mapping from
276// register name to register number.
277#define GET_REGINFO_ENUM
278#include "NVPTXGenRegisterInfo.inc"
279
280// Defines symbolic names for the NVPTX instructions.
281#define GET_INSTRINFO_ENUM
282#define GET_INSTRINFO_MC_HELPER_DECLS
283#include "NVPTXGenInstrInfo.inc"
284
285#endif
286