1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t NVPTXRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask NVPTXLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t NVPTXSubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char NVPTXRegStrings[] = {
30 /* 0 */ "ENVREG10\000"
31 /* 9 */ "ENVREG20\000"
32 /* 18 */ "ENVREG30\000"
33 /* 27 */ "ENVREG0\000"
34 /* 35 */ "RL0\000"
35 /* 39 */ "P0\000"
36 /* 42 */ "RQ0\000"
37 /* 46 */ "R0\000"
38 /* 49 */ "RS0\000"
39 /* 53 */ "ENVREG11\000"
40 /* 62 */ "ENVREG21\000"
41 /* 71 */ "ENVREG31\000"
42 /* 80 */ "ENVREG1\000"
43 /* 88 */ "RL1\000"
44 /* 92 */ "P1\000"
45 /* 95 */ "RQ1\000"
46 /* 99 */ "R1\000"
47 /* 102 */ "RS1\000"
48 /* 106 */ "ENVREG12\000"
49 /* 115 */ "ENVREG22\000"
50 /* 124 */ "VRFrame32\000"
51 /* 134 */ "VRFrameLocal32\000"
52 /* 149 */ "ENVREG2\000"
53 /* 157 */ "RL2\000"
54 /* 161 */ "P2\000"
55 /* 164 */ "RQ2\000"
56 /* 168 */ "R2\000"
57 /* 171 */ "RS2\000"
58 /* 175 */ "ENVREG13\000"
59 /* 184 */ "ENVREG23\000"
60 /* 193 */ "ENVREG3\000"
61 /* 201 */ "RL3\000"
62 /* 205 */ "P3\000"
63 /* 208 */ "RQ3\000"
64 /* 212 */ "R3\000"
65 /* 215 */ "RS3\000"
66 /* 219 */ "ENVREG14\000"
67 /* 228 */ "ENVREG24\000"
68 /* 237 */ "VRFrame64\000"
69 /* 247 */ "VRFrameLocal64\000"
70 /* 262 */ "ENVREG4\000"
71 /* 270 */ "RL4\000"
72 /* 274 */ "P4\000"
73 /* 277 */ "RQ4\000"
74 /* 281 */ "R4\000"
75 /* 284 */ "RS4\000"
76 /* 288 */ "ENVREG15\000"
77 /* 297 */ "ENVREG25\000"
78 /* 306 */ "ENVREG5\000"
79 /* 314 */ "ENVREG16\000"
80 /* 323 */ "ENVREG26\000"
81 /* 332 */ "ENVREG6\000"
82 /* 340 */ "ENVREG17\000"
83 /* 349 */ "ENVREG27\000"
84 /* 358 */ "ENVREG7\000"
85 /* 366 */ "ENVREG18\000"
86 /* 375 */ "ENVREG28\000"
87 /* 384 */ "ENVREG8\000"
88 /* 392 */ "ENVREG19\000"
89 /* 401 */ "ENVREG29\000"
90 /* 410 */ "ENVREG9\000"
91 /* 418 */ "VRDepot\000"
92};
93#ifdef __GNUC__
94#pragma GCC diagnostic pop
95#endif
96
97extern const MCRegisterDesc NVPTXRegDesc[] = { // Descriptors
98 { .Name: 8, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
99 { .Name: 418, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
100 { .Name: 27, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
101 { .Name: 80, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
102 { .Name: 149, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
103 { .Name: 193, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
104 { .Name: 262, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
105 { .Name: 306, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
106 { .Name: 332, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 7, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
107 { .Name: 358, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 8, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
108 { .Name: 384, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 9, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
109 { .Name: 410, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 10, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
110 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 11, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
111 { .Name: 53, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 12, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
112 { .Name: 106, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 13, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
113 { .Name: 175, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 14, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
114 { .Name: 219, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 15, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
115 { .Name: 288, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 16, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
116 { .Name: 314, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 17, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
117 { .Name: 340, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 18, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
118 { .Name: 366, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 19, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
119 { .Name: 392, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 20, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
120 { .Name: 9, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 21, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
121 { .Name: 62, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 22, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
122 { .Name: 115, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 23, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
123 { .Name: 184, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 24, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
124 { .Name: 228, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 25, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
125 { .Name: 297, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 26, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
126 { .Name: 323, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 27, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
127 { .Name: 349, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 28, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
128 { .Name: 375, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 29, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
129 { .Name: 401, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 30, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
130 { .Name: 18, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 31, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
131 { .Name: 71, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 32, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
132 { .Name: 39, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 33, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
133 { .Name: 92, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 34, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
134 { .Name: 161, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 35, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
135 { .Name: 205, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 36, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
136 { .Name: 274, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 37, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
137 { .Name: 46, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 38, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
138 { .Name: 99, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 39, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
139 { .Name: 168, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 40, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
140 { .Name: 212, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 41, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
141 { .Name: 281, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 42, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
142 { .Name: 35, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 43, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
143 { .Name: 88, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 44, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
144 { .Name: 157, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 45, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
145 { .Name: 201, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 46, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
146 { .Name: 270, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 47, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
147 { .Name: 42, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 48, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
148 { .Name: 95, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 49, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
149 { .Name: 164, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 50, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
150 { .Name: 208, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 51, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
151 { .Name: 277, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 52, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
152 { .Name: 49, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 53, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
153 { .Name: 102, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 54, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
154 { .Name: 171, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 55, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
155 { .Name: 215, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 56, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
156 { .Name: 284, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 57, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
157 { .Name: 124, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 58, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
158 { .Name: 237, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 59, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
159 { .Name: 134, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 60, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
160 { .Name: 247, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 61, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
161};
162
163extern const MCPhysReg NVPTXRegUnitRoots[][2] = {
164 { NVPTX::VRDepot },
165 { NVPTX::ENVREG0 },
166 { NVPTX::ENVREG1 },
167 { NVPTX::ENVREG2 },
168 { NVPTX::ENVREG3 },
169 { NVPTX::ENVREG4 },
170 { NVPTX::ENVREG5 },
171 { NVPTX::ENVREG6 },
172 { NVPTX::ENVREG7 },
173 { NVPTX::ENVREG8 },
174 { NVPTX::ENVREG9 },
175 { NVPTX::ENVREG10 },
176 { NVPTX::ENVREG11 },
177 { NVPTX::ENVREG12 },
178 { NVPTX::ENVREG13 },
179 { NVPTX::ENVREG14 },
180 { NVPTX::ENVREG15 },
181 { NVPTX::ENVREG16 },
182 { NVPTX::ENVREG17 },
183 { NVPTX::ENVREG18 },
184 { NVPTX::ENVREG19 },
185 { NVPTX::ENVREG20 },
186 { NVPTX::ENVREG21 },
187 { NVPTX::ENVREG22 },
188 { NVPTX::ENVREG23 },
189 { NVPTX::ENVREG24 },
190 { NVPTX::ENVREG25 },
191 { NVPTX::ENVREG26 },
192 { NVPTX::ENVREG27 },
193 { NVPTX::ENVREG28 },
194 { NVPTX::ENVREG29 },
195 { NVPTX::ENVREG30 },
196 { NVPTX::ENVREG31 },
197 { NVPTX::P0 },
198 { NVPTX::P1 },
199 { NVPTX::P2 },
200 { NVPTX::P3 },
201 { NVPTX::P4 },
202 { NVPTX::R0 },
203 { NVPTX::R1 },
204 { NVPTX::R2 },
205 { NVPTX::R3 },
206 { NVPTX::R4 },
207 { NVPTX::RL0 },
208 { NVPTX::RL1 },
209 { NVPTX::RL2 },
210 { NVPTX::RL3 },
211 { NVPTX::RL4 },
212 { NVPTX::RQ0 },
213 { NVPTX::RQ1 },
214 { NVPTX::RQ2 },
215 { NVPTX::RQ3 },
216 { NVPTX::RQ4 },
217 { NVPTX::RS0 },
218 { NVPTX::RS1 },
219 { NVPTX::RS2 },
220 { NVPTX::RS3 },
221 { NVPTX::RS4 },
222 { NVPTX::VRFrame32 },
223 { NVPTX::VRFrame64 },
224 { NVPTX::VRFrameLocal32 },
225 { NVPTX::VRFrameLocal64 },
226};
227
228// Register classes...
229
230#ifdef __GNUC__
231#pragma GCC diagnostic push
232#pragma GCC diagnostic ignored "-Woverlength-strings"
233#endif
234extern const char NVPTXRegClassStrings[] = {
235 /* 0 */ "B1\000"
236 /* 3 */ "B32\000"
237 /* 7 */ "B64\000"
238 /* 11 */ "B16\000"
239 /* 15 */ "B128\000"
240 /* 20 */ "B32_and_SpecialRegs\000"
241};
242#ifdef __GNUC__
243#pragma GCC diagnostic pop
244#endif
245
246using NVPTXRegisterClassStorage = MCRegisterClassStorage<7, 66, 18, 7, 1, 2>;
247extern const MCRegisterClassStorage<7, 66, 18, 7, 1, 2> NVPTXMCRegisterClassStorage = {
248 .Classes: {
249 {
250 offsetof(NVPTXRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
251 offsetof(NVPTXRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
252 .NameIdx: 0,
253 .RegSizeInBits: 1,
254 .RegsSize: 5,
255 .RegSetBegin: 34, /* MinRegVal */
256 .RegSetSize: 5, /* RegSetSize */
257 .ID: NVPTX::B1RegClassID,
258 .CopyCost: 1, /* CopyCost */
259 .Allocatable: true, /* Allocatable */
260 .BaseClass: false,
261 offsetof(NVPTXRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
262 offsetof(NVPTXRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
263 .LaneMask: LaneBitmask(0x0000000000000001),
264 .AllocationPriority: 0,
265 .GlobalPriority: false,
266 .TSFlags: 0x00, /* TSFlags */
267 .SpillStackID: 0, /* SpillStackID */
268 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
269 .CoveredBySubRegs: false, /* CoveredBySubRegs */
270 offsetof(NVPTXRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
271 .SuperClassesSize: 0
272 },
273 {
274 offsetof(NVPTXRegisterClassStorage, Regs[5]) - 1 * sizeof(MCRegisterClass),
275 offsetof(NVPTXRegisterClassStorage, BitSets[1]) - 1 * sizeof(MCRegisterClass),
276 .NameIdx: 11,
277 .RegSizeInBits: 16,
278 .RegsSize: 5,
279 .RegSetBegin: 54, /* MinRegVal */
280 .RegSetSize: 5, /* RegSetSize */
281 .ID: NVPTX::B16RegClassID,
282 .CopyCost: 1, /* CopyCost */
283 .Allocatable: true, /* Allocatable */
284 .BaseClass: false,
285 offsetof(NVPTXRegisterClassStorage, SubClassMasks[1]) - 1 * sizeof(MCRegisterClass),
286 offsetof(NVPTXRegisterClassStorage, SuperRegIdxSeqs[0]) - 1 * sizeof(MCRegisterClass),
287 .LaneMask: LaneBitmask(0x0000000000000001),
288 .AllocationPriority: 0,
289 .GlobalPriority: false,
290 .TSFlags: 0x00, /* TSFlags */
291 .SpillStackID: 0, /* SpillStackID */
292 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
293 .CoveredBySubRegs: false, /* CoveredBySubRegs */
294 offsetof(NVPTXRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
295 .SuperClassesSize: 0
296 },
297 {
298 offsetof(NVPTXRegisterClassStorage, Regs[10]) - 2 * sizeof(MCRegisterClass),
299 offsetof(NVPTXRegisterClassStorage, BitSets[2]) - 2 * sizeof(MCRegisterClass),
300 .NameIdx: 28,
301 .RegSizeInBits: 32,
302 .RegsSize: 35,
303 .RegSetBegin: 1, /* MinRegVal */
304 .RegSetSize: 61, /* RegSetSize */
305 .ID: NVPTX::SpecialRegsRegClassID,
306 .CopyCost: 1, /* CopyCost */
307 .Allocatable: true, /* Allocatable */
308 .BaseClass: false,
309 offsetof(NVPTXRegisterClassStorage, SubClassMasks[2]) - 2 * sizeof(MCRegisterClass),
310 offsetof(NVPTXRegisterClassStorage, SuperRegIdxSeqs[0]) - 2 * sizeof(MCRegisterClass),
311 .LaneMask: LaneBitmask(0x0000000000000001),
312 .AllocationPriority: 0,
313 .GlobalPriority: false,
314 .TSFlags: 0x00, /* TSFlags */
315 .SpillStackID: 0, /* SpillStackID */
316 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
317 .CoveredBySubRegs: false, /* CoveredBySubRegs */
318 offsetof(NVPTXRegisterClassStorage, SuperClasses[0]) - 2 * sizeof(MCRegisterClass),
319 .SuperClassesSize: 0
320 },
321 {
322 offsetof(NVPTXRegisterClassStorage, Regs[45]) - 3 * sizeof(MCRegisterClass),
323 offsetof(NVPTXRegisterClassStorage, BitSets[10]) - 3 * sizeof(MCRegisterClass),
324 .NameIdx: 3,
325 .RegSizeInBits: 32,
326 .RegsSize: 7,
327 .RegSetBegin: 39, /* MinRegVal */
328 .RegSetSize: 23, /* RegSetSize */
329 .ID: NVPTX::B32RegClassID,
330 .CopyCost: 1, /* CopyCost */
331 .Allocatable: true, /* Allocatable */
332 .BaseClass: false,
333 offsetof(NVPTXRegisterClassStorage, SubClassMasks[3]) - 3 * sizeof(MCRegisterClass),
334 offsetof(NVPTXRegisterClassStorage, SuperRegIdxSeqs[0]) - 3 * sizeof(MCRegisterClass),
335 .LaneMask: LaneBitmask(0x0000000000000001),
336 .AllocationPriority: 0,
337 .GlobalPriority: false,
338 .TSFlags: 0x00, /* TSFlags */
339 .SpillStackID: 0, /* SpillStackID */
340 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
341 .CoveredBySubRegs: false, /* CoveredBySubRegs */
342 offsetof(NVPTXRegisterClassStorage, SuperClasses[0]) - 3 * sizeof(MCRegisterClass),
343 .SuperClassesSize: 0
344 },
345 {
346 offsetof(NVPTXRegisterClassStorage, Regs[52]) - 4 * sizeof(MCRegisterClass),
347 offsetof(NVPTXRegisterClassStorage, BitSets[13]) - 4 * sizeof(MCRegisterClass),
348 .NameIdx: 20,
349 .RegSizeInBits: 32,
350 .RegsSize: 2,
351 .RegSetBegin: 59, /* MinRegVal */
352 .RegSetSize: 3, /* RegSetSize */
353 .ID: NVPTX::B32_and_SpecialRegsRegClassID,
354 .CopyCost: 1, /* CopyCost */
355 .Allocatable: true, /* Allocatable */
356 .BaseClass: false,
357 offsetof(NVPTXRegisterClassStorage, SubClassMasks[4]) - 4 * sizeof(MCRegisterClass),
358 offsetof(NVPTXRegisterClassStorage, SuperRegIdxSeqs[0]) - 4 * sizeof(MCRegisterClass),
359 .LaneMask: LaneBitmask(0x0000000000000001),
360 .AllocationPriority: 0,
361 .GlobalPriority: false,
362 .TSFlags: 0x00, /* TSFlags */
363 .SpillStackID: 0, /* SpillStackID */
364 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
365 .CoveredBySubRegs: false, /* CoveredBySubRegs */
366 offsetof(NVPTXRegisterClassStorage, SuperClasses[0]) - 4 * sizeof(MCRegisterClass),
367 .SuperClassesSize: 2
368 },
369 {
370 offsetof(NVPTXRegisterClassStorage, Regs[54]) - 5 * sizeof(MCRegisterClass),
371 offsetof(NVPTXRegisterClassStorage, BitSets[14]) - 5 * sizeof(MCRegisterClass),
372 .NameIdx: 7,
373 .RegSizeInBits: 64,
374 .RegsSize: 7,
375 .RegSetBegin: 44, /* MinRegVal */
376 .RegSetSize: 19, /* RegSetSize */
377 .ID: NVPTX::B64RegClassID,
378 .CopyCost: 1, /* CopyCost */
379 .Allocatable: true, /* Allocatable */
380 .BaseClass: false,
381 offsetof(NVPTXRegisterClassStorage, SubClassMasks[5]) - 5 * sizeof(MCRegisterClass),
382 offsetof(NVPTXRegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass),
383 .LaneMask: LaneBitmask(0x0000000000000001),
384 .AllocationPriority: 0,
385 .GlobalPriority: false,
386 .TSFlags: 0x00, /* TSFlags */
387 .SpillStackID: 0, /* SpillStackID */
388 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
389 .CoveredBySubRegs: false, /* CoveredBySubRegs */
390 offsetof(NVPTXRegisterClassStorage, SuperClasses[2]) - 5 * sizeof(MCRegisterClass),
391 .SuperClassesSize: 0
392 },
393 {
394 offsetof(NVPTXRegisterClassStorage, Regs[61]) - 6 * sizeof(MCRegisterClass),
395 offsetof(NVPTXRegisterClassStorage, BitSets[17]) - 6 * sizeof(MCRegisterClass),
396 .NameIdx: 15,
397 .RegSizeInBits: 128,
398 .RegsSize: 5,
399 .RegSetBegin: 49, /* MinRegVal */
400 .RegSetSize: 5, /* RegSetSize */
401 .ID: NVPTX::B128RegClassID,
402 .CopyCost: 1, /* CopyCost */
403 .Allocatable: true, /* Allocatable */
404 .BaseClass: false,
405 offsetof(NVPTXRegisterClassStorage, SubClassMasks[6]) - 6 * sizeof(MCRegisterClass),
406 offsetof(NVPTXRegisterClassStorage, SuperRegIdxSeqs[0]) - 6 * sizeof(MCRegisterClass),
407 .LaneMask: LaneBitmask(0x0000000000000001),
408 .AllocationPriority: 0,
409 .GlobalPriority: false,
410 .TSFlags: 0x00, /* TSFlags */
411 .SpillStackID: 0, /* SpillStackID */
412 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
413 .CoveredBySubRegs: false, /* CoveredBySubRegs */
414 offsetof(NVPTXRegisterClassStorage, SuperClasses[2]) - 6 * sizeof(MCRegisterClass),
415 .SuperClassesSize: 0
416 },
417 },
418 .Regs: {
419 /* 0 */ NVPTX::P0, NVPTX::P1, NVPTX::P2, NVPTX::P3, NVPTX::P4,
420 /* 5 */ NVPTX::RS0, NVPTX::RS1, NVPTX::RS2, NVPTX::RS3, NVPTX::RS4,
421 /* 10 */ NVPTX::VRFrame32, NVPTX::VRFrameLocal32, NVPTX::VRDepot, NVPTX::ENVREG0, NVPTX::ENVREG1, NVPTX::ENVREG2, NVPTX::ENVREG3, NVPTX::ENVREG4, NVPTX::ENVREG5, NVPTX::ENVREG6, NVPTX::ENVREG7, NVPTX::ENVREG8, NVPTX::ENVREG9, NVPTX::ENVREG10, NVPTX::ENVREG11, NVPTX::ENVREG12, NVPTX::ENVREG13, NVPTX::ENVREG14, NVPTX::ENVREG15, NVPTX::ENVREG16, NVPTX::ENVREG17, NVPTX::ENVREG18, NVPTX::ENVREG19, NVPTX::ENVREG20, NVPTX::ENVREG21, NVPTX::ENVREG22, NVPTX::ENVREG23, NVPTX::ENVREG24, NVPTX::ENVREG25, NVPTX::ENVREG26, NVPTX::ENVREG27, NVPTX::ENVREG28, NVPTX::ENVREG29, NVPTX::ENVREG30, NVPTX::ENVREG31,
422 /* 45 */ NVPTX::R0, NVPTX::R1, NVPTX::R2, NVPTX::R3, NVPTX::R4, NVPTX::VRFrame32, NVPTX::VRFrameLocal32,
423 /* 52 */ NVPTX::VRFrame32, NVPTX::VRFrameLocal32,
424 /* 54 */ NVPTX::RL0, NVPTX::RL1, NVPTX::RL2, NVPTX::RL3, NVPTX::RL4, NVPTX::VRFrame64, NVPTX::VRFrameLocal64,
425 /* 61 */ NVPTX::RQ0, NVPTX::RQ1, NVPTX::RQ2, NVPTX::RQ3, NVPTX::RQ4,
426 },
427 .BitSets: {
428 /* 0 */ 0x1f,
429 /* 1 */ 0x1f,
430 /* 2 */ 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x14,
431 /* 10 */ 0x1f, 0x00, 0x50,
432 /* 13 */ 0x05,
433 /* 14 */ 0x1f, 0x00, 0x05,
434 /* 17 */ 0x1f,
435 },
436 .SubClassMasks: {
437 // 0 B1
438 0x00000001,
439 // 1 B16
440 0x00000002,
441 // 2 SpecialRegs
442 0x00000014,
443 // 3 B32
444 0x00000018,
445 // 4 B32_and_SpecialRegs
446 0x00000010,
447 // 5 B64
448 0x00000020,
449 // 6 B128
450 0x00000040,
451 },
452 .SuperRegIdxSeqs: {
453 /* 0 */ 0,
454 },
455 .SuperClasses: {
456 /* 0 B1 */
457 /* 0 B16 */
458 /* 0 SpecialRegs */
459 /* 0 B32 */
460 /* 0 B32_and_SpecialRegs */ NVPTX::SpecialRegsRegClassID, NVPTX::B32RegClassID,
461 /* 2 B64 */
462 /* 2 B128 */
463 }
464};
465
466const MCRegisterClass &getNVPTXMCRegisterClass(unsigned RC) {
467 return NVPTXMCRegisterClassStorage.Classes[RC];
468}
469
470extern const uint16_t NVPTXRegEncodingTable[] = {
471 0,
472 0,
473 0,
474 0,
475 0,
476 0,
477 0,
478 0,
479 0,
480 0,
481 0,
482 0,
483 0,
484 0,
485 0,
486 0,
487 0,
488 0,
489 0,
490 0,
491 0,
492 0,
493 0,
494 0,
495 0,
496 0,
497 0,
498 0,
499 0,
500 0,
501 0,
502 0,
503 0,
504 0,
505 0,
506 0,
507 0,
508 0,
509 0,
510 0,
511 0,
512 0,
513 0,
514 0,
515 0,
516 0,
517 0,
518 0,
519 0,
520 0,
521 0,
522 0,
523 0,
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0,
531 0,
532 0,
533 0,
534};
535static inline void InitNVPTXMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
536 RI->InitMCRegisterInfo(D: NVPTXRegDesc, NR: 63, RA, PC, C: NVPTXMCRegisterClassStorage.Classes, NC: 7, RURoots: NVPTXRegUnitRoots, NRU: 62, DL: NVPTXRegDiffLists, RUMS: NVPTXLaneMaskLists, Strings: NVPTXRegStrings, ClassStrings: NVPTXRegClassStrings, SubIndices: NVPTXSubRegIdxLists, NumIndices: 1,
537RET: NVPTXRegEncodingTable, RUI: nullptr);
538
539}
540
541
542} // namespace llvm
543