1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<7, 66, 52, 7, 1, 2> NVPTXMCRegisterClassStorage;
12
13static const MVT::SimpleValueType NVPTXVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i128, MVT::Other,
17 /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
18 /* 10 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::f32, MVT::Other,
19 /* 17 */ MVT::i64, MVT::v2i32, MVT::v2f32, MVT::f64, MVT::Other,
20};
21static constexpr char NVPTXSubRegIndexStrings[] = {
22 /* dummy */ 0
23};
24
25
26static constexpr uint32_t NVPTXSubRegIndexNameOffsets[] = {
27 /* dummy */ 0
28};
29
30static const TargetRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRangeTable[] = {
31 { .Offset: 4294967295, .Size: 4294967295 },
32 { .Offset: 4294967295, .Size: 4294967295 },
33};
34
35
36static const LaneBitmask NVPTXSubRegIndexLaneMaskTable[] = {
37 LaneBitmask::getAll(),
38 };
39
40
41
42static const TargetRegisterInfo::RegClassInfo NVPTXRegClassInfos[] = {
43 // Mode = 0 (DefaultMode)
44 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*NVPTXVTLists+*/.VTListOffset: 0 }, // B1
45 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*NVPTXVTLists+*/.VTListOffset: 6 }, // B16
46 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 2 }, // SpecialRegs
47 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
49 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*NVPTXVTLists+*/.VTListOffset: 17 }, // B64
50 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*NVPTXVTLists+*/.VTListOffset: 4 }, // B128
51 // Mode = 1 (NVPTX64)
52 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*NVPTXVTLists+*/.VTListOffset: 0 }, // B1
53 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*NVPTXVTLists+*/.VTListOffset: 6 }, // B16
54 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 2 }, // SpecialRegs
55 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32
56 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
57 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*NVPTXVTLists+*/.VTListOffset: 17 }, // B64
58 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*NVPTXVTLists+*/.VTListOffset: 4 }, // B128
59};
60
61static const uint8_t NVPTXCostPerUseTable[] = {
620, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
63
64
65static const bool NVPTXInAllocatableClassTable[] = {
66false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
67
68
69static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
70.CostPerUse: NVPTXCostPerUseTable, .NumCosts: 1, .InAllocatableClass: NVPTXInAllocatableClassTable};
71
72/// Get the weight in units of pressure for this register class.
73const RegClassWeight &NVPTXGenRegisterInfo::
74getRegClassWeight(const TargetRegisterClass *RC) const {
75 static const RegClassWeight RCWeightTable[] = {
76 {.RegWeight: 1, .WeightLimit: 5}, // B1
77 {.RegWeight: 1, .WeightLimit: 5}, // B16
78 {.RegWeight: 1, .WeightLimit: 35}, // SpecialRegs
79 {.RegWeight: 1, .WeightLimit: 7}, // B32
80 {.RegWeight: 1, .WeightLimit: 2}, // B32_and_SpecialRegs
81 {.RegWeight: 1, .WeightLimit: 7}, // B64
82 {.RegWeight: 1, .WeightLimit: 5}, // B128
83 };
84 return RCWeightTable[RC->getID()];
85}
86
87/// Get the weight in units of pressure for this register unit.
88unsigned NVPTXGenRegisterInfo::
89getRegUnitWeight(MCRegUnit RegUnit) const {
90 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
91 // All register units have unit weight.
92 return 1;
93}
94
95
96// Get the number of dimensions of register pressure.
97unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
98 return 8;
99}
100
101// Get the name of this register unit pressure set.
102const char *NVPTXGenRegisterInfo::
103getRegPressureSetName(unsigned Idx) const {
104 static const char *PressureNameTable[] = {
105 "B32_and_SpecialRegs",
106 "B1",
107 "B16",
108 "B128",
109 "B32",
110 "B64",
111 "SpecialRegs",
112 "SpecialRegs_with_B32",
113 };
114 return PressureNameTable[Idx];
115}
116
117// Get the register unit pressure limit for this dimension.
118// This limit must be adjusted dynamically for reserved registers.
119unsigned NVPTXGenRegisterInfo::
120getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
121 static const uint8_t PressureLimitTable[] = {
122 2, // 0: B32_and_SpecialRegs
123 5, // 1: B1
124 5, // 2: B16
125 5, // 3: B128
126 7, // 4: B32
127 7, // 5: B64
128 35, // 6: SpecialRegs
129 40, // 7: SpecialRegs_with_B32
130 };
131 return PressureLimitTable[Idx];
132}
133
134/// Table of pressure sets per register class or unit.
135static const int RCSetsTable[] = {
136 /* 0 */ 1, -1,
137 /* 2 */ 2, -1,
138 /* 4 */ 3, -1,
139 /* 6 */ 5, -1,
140 /* 8 */ 4, 7, -1,
141 /* 11 */ 0, 4, 6, 7, -1,
142};
143
144/// Get the dimensions of register pressure impacted by this register class.
145/// Returns a -1 terminated array of pressure set IDs
146const int *NVPTXGenRegisterInfo::
147getRegClassPressureSets(const TargetRegisterClass *RC) const {
148 static const uint8_t RCSetStartTable[] = {
149 0,2,13,8,11,6,4,};
150 return &RCSetsTable[RCSetStartTable[RC->getID()]];
151}
152
153/// Get the dimensions of register pressure impacted by this register unit.
154/// Returns a -1 terminated array of pressure set IDs
155const int *NVPTXGenRegisterInfo::
156getRegUnitPressureSets(MCRegUnit RegUnit) const {
157 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
158 static const uint8_t RUSetStartTable[] = {
159 13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,0,0,0,0,0,8,8,8,8,8,6,6,6,6,6,4,4,4,4,4,2,2,2,2,2,11,6,11,6,};
160 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
161}
162
163
164// Register to minimal register class mapping
165
166const TargetRegisterClass *NVPTXGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
167 static const uint16_t InvalidRegClassID = UINT16_MAX;
168
169 static const uint16_t Mapping[63] = {
170 InvalidRegClassID, // NoRegister
171 NVPTX::SpecialRegsRegClassID, // VRDepot
172 NVPTX::SpecialRegsRegClassID, // ENVREG0
173 NVPTX::SpecialRegsRegClassID, // ENVREG1
174 NVPTX::SpecialRegsRegClassID, // ENVREG2
175 NVPTX::SpecialRegsRegClassID, // ENVREG3
176 NVPTX::SpecialRegsRegClassID, // ENVREG4
177 NVPTX::SpecialRegsRegClassID, // ENVREG5
178 NVPTX::SpecialRegsRegClassID, // ENVREG6
179 NVPTX::SpecialRegsRegClassID, // ENVREG7
180 NVPTX::SpecialRegsRegClassID, // ENVREG8
181 NVPTX::SpecialRegsRegClassID, // ENVREG9
182 NVPTX::SpecialRegsRegClassID, // ENVREG10
183 NVPTX::SpecialRegsRegClassID, // ENVREG11
184 NVPTX::SpecialRegsRegClassID, // ENVREG12
185 NVPTX::SpecialRegsRegClassID, // ENVREG13
186 NVPTX::SpecialRegsRegClassID, // ENVREG14
187 NVPTX::SpecialRegsRegClassID, // ENVREG15
188 NVPTX::SpecialRegsRegClassID, // ENVREG16
189 NVPTX::SpecialRegsRegClassID, // ENVREG17
190 NVPTX::SpecialRegsRegClassID, // ENVREG18
191 NVPTX::SpecialRegsRegClassID, // ENVREG19
192 NVPTX::SpecialRegsRegClassID, // ENVREG20
193 NVPTX::SpecialRegsRegClassID, // ENVREG21
194 NVPTX::SpecialRegsRegClassID, // ENVREG22
195 NVPTX::SpecialRegsRegClassID, // ENVREG23
196 NVPTX::SpecialRegsRegClassID, // ENVREG24
197 NVPTX::SpecialRegsRegClassID, // ENVREG25
198 NVPTX::SpecialRegsRegClassID, // ENVREG26
199 NVPTX::SpecialRegsRegClassID, // ENVREG27
200 NVPTX::SpecialRegsRegClassID, // ENVREG28
201 NVPTX::SpecialRegsRegClassID, // ENVREG29
202 NVPTX::SpecialRegsRegClassID, // ENVREG30
203 NVPTX::SpecialRegsRegClassID, // ENVREG31
204 NVPTX::B1RegClassID, // P0
205 NVPTX::B1RegClassID, // P1
206 NVPTX::B1RegClassID, // P2
207 NVPTX::B1RegClassID, // P3
208 NVPTX::B1RegClassID, // P4
209 NVPTX::B32RegClassID, // R0
210 NVPTX::B32RegClassID, // R1
211 NVPTX::B32RegClassID, // R2
212 NVPTX::B32RegClassID, // R3
213 NVPTX::B32RegClassID, // R4
214 NVPTX::B64RegClassID, // RL0
215 NVPTX::B64RegClassID, // RL1
216 NVPTX::B64RegClassID, // RL2
217 NVPTX::B64RegClassID, // RL3
218 NVPTX::B64RegClassID, // RL4
219 NVPTX::B128RegClassID, // RQ0
220 NVPTX::B128RegClassID, // RQ1
221 NVPTX::B128RegClassID, // RQ2
222 NVPTX::B128RegClassID, // RQ3
223 NVPTX::B128RegClassID, // RQ4
224 NVPTX::B16RegClassID, // RS0
225 NVPTX::B16RegClassID, // RS1
226 NVPTX::B16RegClassID, // RS2
227 NVPTX::B16RegClassID, // RS3
228 NVPTX::B16RegClassID, // RS4
229 NVPTX::B32_and_SpecialRegsRegClassID, // VRFrame32
230 NVPTX::B64RegClassID, // VRFrame64
231 NVPTX::B32_and_SpecialRegsRegClassID, // VRFrameLocal32
232 NVPTX::B64RegClassID, // VRFrameLocal64
233 };
234
235 assert(Reg < ArrayRef(Mapping).size());
236 unsigned RCID = Mapping[Reg.id()];
237 if (RCID == InvalidRegClassID)
238 return nullptr;
239 return &NVPTXMCRegisterClassStorage.Classes[RCID];
240}
241extern const MCRegisterDesc NVPTXRegDesc[];
242extern const int16_t NVPTXRegDiffLists[];
243extern const LaneBitmask NVPTXLaneMaskLists[];
244extern const char NVPTXRegStrings[];
245extern const char NVPTXRegClassStrings[];
246extern const MCPhysReg NVPTXRegUnitRoots[][2];
247extern const uint16_t NVPTXSubRegIdxLists[];
248extern const uint16_t NVPTXRegEncodingTable[];
249
250NVPTXGenRegisterInfo::
251NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
252 unsigned PC, unsigned HwMode)
253 : TargetRegisterInfo(&NVPTXRegInfoDesc,
254 NVPTXSubRegIndexStrings, NVPTXSubRegIndexNameOffsets,
255 NVPTXSubRegIdxRangeTable, NVPTXSubRegIndexLaneMaskTable,
256
257 LaneBitmask(0xFFFFFFFFFFFFFFFF), NVPTXRegClassInfos, NVPTXVTLists, HwMode) {
258 InitMCRegisterInfo(D: NVPTXRegDesc, NR: 63, RA, PC,
259 C: &getNVPTXMCRegisterClass(RC: 0), NC: 7, RURoots: NVPTXRegUnitRoots, NRU: 62, DL: NVPTXRegDiffLists,
260 RUMS: NVPTXLaneMaskLists, Strings: NVPTXRegStrings, ClassStrings: NVPTXRegClassStrings, SubIndices: NVPTXSubRegIdxLists, NumIndices: 1,
261 RET: NVPTXRegEncodingTable, RUI: nullptr);
262
263}
264
265
266
267ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
268 return {};
269}
270
271bool NVPTXGenRegisterInfo::
272isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
273 return
274 false;
275}
276
277bool NVPTXGenRegisterInfo::
278isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
279 return
280 false;
281}
282
283bool NVPTXGenRegisterInfo::
284isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
285 return
286 false;
287}
288
289bool NVPTXGenRegisterInfo::
290isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
291 return
292 false;
293}
294
295bool NVPTXGenRegisterInfo::
296isConstantPhysReg(MCRegister PhysReg) const {
297 return
298 false;
299}
300
301ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
302 return {};
303}
304
305const NVPTXFrameLowering *
306NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
307 return static_cast<const NVPTXFrameLowering *>(
308 MF.getSubtarget().getFrameLowering());
309}
310
311
312} // namespace llvm
313