1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass NVPTXMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i128, MVT::Other,
17 /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
18 /* 10 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::f32, MVT::Other,
19 /* 17 */ MVT::i64, MVT::v2i32, MVT::v2f32, MVT::f64, MVT::Other,
20};
21
22static const char *SubRegIndexNameTable[] = { "" };
23
24static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
25 { .Offset: 65535, .Size: 65535 },
26 { .Offset: 65535, .Size: 65535 },
27};
28
29
30static const LaneBitmask SubRegIndexLaneMaskTable[] = {
31 LaneBitmask::getAll(),
32 };
33
34
35
36static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
37 // Mode = 0 (Default)
38 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // B1
39 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 6 }, // B16
40 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // SpecialRegs
41 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // B32
42 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
43 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 17 }, // B64
44 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 4 }, // B128
45 // Mode = 1 (NVPTX64)
46 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // B1
47 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 6 }, // B16
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // SpecialRegs
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // B32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
51 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 17 }, // B64
52 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 4 }, // B128
53};
54static const uint32_t B1SubClassMask[] = {
55 0x00000001,
56};
57
58static const uint32_t B16SubClassMask[] = {
59 0x00000002,
60};
61
62static const uint32_t SpecialRegsSubClassMask[] = {
63 0x00000014,
64};
65
66static const uint32_t B32SubClassMask[] = {
67 0x00000018,
68};
69
70static const uint32_t B32_and_SpecialRegsSubClassMask[] = {
71 0x00000010,
72};
73
74static const uint32_t B64SubClassMask[] = {
75 0x00000020,
76};
77
78static const uint32_t B128SubClassMask[] = {
79 0x00000040,
80};
81
82static const uint16_t SuperRegIdxSeqs[] = {
83 /* 0 */ 0,
84};
85
86static unsigned const B32_and_SpecialRegsSuperclasses[] = {
87 NVPTX::SpecialRegsRegClassID,
88 NVPTX::B32RegClassID,
89};
90
91
92namespace NVPTX { // Register class instances
93 extern const TargetRegisterClass B1RegClass = {
94 .MC: &NVPTXMCRegisterClasses[B1RegClassID],
95 .SubClassMask: B1SubClassMask,
96 .SuperRegIndices: SuperRegIdxSeqs + 0,
97 .LaneMask: LaneBitmask(0x0000000000000001),
98 .AllocationPriority: 0,
99 .GlobalPriority: false,
100 .TSFlags: 0x00, /* TSFlags */
101 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
102 .CoveredBySubRegs: false, /* CoveredBySubRegs */
103 .SuperClasses: nullptr, .SuperClassesSize: 0,
104 .OrderFunc: nullptr
105 };
106
107 extern const TargetRegisterClass B16RegClass = {
108 .MC: &NVPTXMCRegisterClasses[B16RegClassID],
109 .SubClassMask: B16SubClassMask,
110 .SuperRegIndices: SuperRegIdxSeqs + 0,
111 .LaneMask: LaneBitmask(0x0000000000000001),
112 .AllocationPriority: 0,
113 .GlobalPriority: false,
114 .TSFlags: 0x00, /* TSFlags */
115 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
116 .CoveredBySubRegs: false, /* CoveredBySubRegs */
117 .SuperClasses: nullptr, .SuperClassesSize: 0,
118 .OrderFunc: nullptr
119 };
120
121 extern const TargetRegisterClass SpecialRegsRegClass = {
122 .MC: &NVPTXMCRegisterClasses[SpecialRegsRegClassID],
123 .SubClassMask: SpecialRegsSubClassMask,
124 .SuperRegIndices: SuperRegIdxSeqs + 0,
125 .LaneMask: LaneBitmask(0x0000000000000001),
126 .AllocationPriority: 0,
127 .GlobalPriority: false,
128 .TSFlags: 0x00, /* TSFlags */
129 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
130 .CoveredBySubRegs: false, /* CoveredBySubRegs */
131 .SuperClasses: nullptr, .SuperClassesSize: 0,
132 .OrderFunc: nullptr
133 };
134
135 extern const TargetRegisterClass B32RegClass = {
136 .MC: &NVPTXMCRegisterClasses[B32RegClassID],
137 .SubClassMask: B32SubClassMask,
138 .SuperRegIndices: SuperRegIdxSeqs + 0,
139 .LaneMask: LaneBitmask(0x0000000000000001),
140 .AllocationPriority: 0,
141 .GlobalPriority: false,
142 .TSFlags: 0x00, /* TSFlags */
143 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
144 .CoveredBySubRegs: false, /* CoveredBySubRegs */
145 .SuperClasses: nullptr, .SuperClassesSize: 0,
146 .OrderFunc: nullptr
147 };
148
149 extern const TargetRegisterClass B32_and_SpecialRegsRegClass = {
150 .MC: &NVPTXMCRegisterClasses[B32_and_SpecialRegsRegClassID],
151 .SubClassMask: B32_and_SpecialRegsSubClassMask,
152 .SuperRegIndices: SuperRegIdxSeqs + 0,
153 .LaneMask: LaneBitmask(0x0000000000000001),
154 .AllocationPriority: 0,
155 .GlobalPriority: false,
156 .TSFlags: 0x00, /* TSFlags */
157 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
158 .CoveredBySubRegs: false, /* CoveredBySubRegs */
159 .SuperClasses: B32_and_SpecialRegsSuperclasses, .SuperClassesSize: 2,
160 .OrderFunc: nullptr
161 };
162
163 extern const TargetRegisterClass B64RegClass = {
164 .MC: &NVPTXMCRegisterClasses[B64RegClassID],
165 .SubClassMask: B64SubClassMask,
166 .SuperRegIndices: SuperRegIdxSeqs + 0,
167 .LaneMask: LaneBitmask(0x0000000000000001),
168 .AllocationPriority: 0,
169 .GlobalPriority: false,
170 .TSFlags: 0x00, /* TSFlags */
171 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
172 .CoveredBySubRegs: false, /* CoveredBySubRegs */
173 .SuperClasses: nullptr, .SuperClassesSize: 0,
174 .OrderFunc: nullptr
175 };
176
177 extern const TargetRegisterClass B128RegClass = {
178 .MC: &NVPTXMCRegisterClasses[B128RegClassID],
179 .SubClassMask: B128SubClassMask,
180 .SuperRegIndices: SuperRegIdxSeqs + 0,
181 .LaneMask: LaneBitmask(0x0000000000000001),
182 .AllocationPriority: 0,
183 .GlobalPriority: false,
184 .TSFlags: 0x00, /* TSFlags */
185 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
186 .CoveredBySubRegs: false, /* CoveredBySubRegs */
187 .SuperClasses: nullptr, .SuperClassesSize: 0,
188 .OrderFunc: nullptr
189 };
190
191} // end namespace NVPTX
192
193namespace {
194 const TargetRegisterClass *const RegisterClasses[] = {
195 &NVPTX::B1RegClass,
196 &NVPTX::B16RegClass,
197 &NVPTX::SpecialRegsRegClass,
198 &NVPTX::B32RegClass,
199 &NVPTX::B32_and_SpecialRegsRegClass,
200 &NVPTX::B64RegClass,
201 &NVPTX::B128RegClass,
202 };
203} // end anonymous namespace
204
205static const uint8_t CostPerUseTable[] = {
2060, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
207
208
209static const bool InAllocatableClassTable[] = {
210false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
211
212
213static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
214.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
215
216/// Get the weight in units of pressure for this register class.
217const RegClassWeight &NVPTXGenRegisterInfo::
218getRegClassWeight(const TargetRegisterClass *RC) const {
219 static const RegClassWeight RCWeightTable[] = {
220 {.RegWeight: 1, .WeightLimit: 5}, // B1
221 {.RegWeight: 1, .WeightLimit: 5}, // B16
222 {.RegWeight: 1, .WeightLimit: 35}, // SpecialRegs
223 {.RegWeight: 1, .WeightLimit: 7}, // B32
224 {.RegWeight: 1, .WeightLimit: 2}, // B32_and_SpecialRegs
225 {.RegWeight: 1, .WeightLimit: 7}, // B64
226 {.RegWeight: 1, .WeightLimit: 5}, // B128
227 };
228 return RCWeightTable[RC->getID()];
229}
230
231/// Get the weight in units of pressure for this register unit.
232unsigned NVPTXGenRegisterInfo::
233getRegUnitWeight(MCRegUnit RegUnit) const {
234 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
235 // All register units have unit weight.
236 return 1;
237}
238
239
240// Get the number of dimensions of register pressure.
241unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
242 return 8;
243}
244
245// Get the name of this register unit pressure set.
246const char *NVPTXGenRegisterInfo::
247getRegPressureSetName(unsigned Idx) const {
248 static const char *PressureNameTable[] = {
249 "B32_and_SpecialRegs",
250 "B1",
251 "B16",
252 "B128",
253 "B32",
254 "B64",
255 "SpecialRegs",
256 "SpecialRegs_with_B32",
257 };
258 return PressureNameTable[Idx];
259}
260
261// Get the register unit pressure limit for this dimension.
262// This limit must be adjusted dynamically for reserved registers.
263unsigned NVPTXGenRegisterInfo::
264getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
265 static const uint8_t PressureLimitTable[] = {
266 2, // 0: B32_and_SpecialRegs
267 5, // 1: B1
268 5, // 2: B16
269 5, // 3: B128
270 7, // 4: B32
271 7, // 5: B64
272 35, // 6: SpecialRegs
273 40, // 7: SpecialRegs_with_B32
274 };
275 return PressureLimitTable[Idx];
276}
277
278/// Table of pressure sets per register class or unit.
279static const int RCSetsTable[] = {
280 /* 0 */ 1, -1,
281 /* 2 */ 2, -1,
282 /* 4 */ 3, -1,
283 /* 6 */ 5, -1,
284 /* 8 */ 4, 7, -1,
285 /* 11 */ 0, 4, 6, 7, -1,
286};
287
288/// Get the dimensions of register pressure impacted by this register class.
289/// Returns a -1 terminated array of pressure set IDs
290const int *NVPTXGenRegisterInfo::
291getRegClassPressureSets(const TargetRegisterClass *RC) const {
292 static const uint8_t RCSetStartTable[] = {
293 0,2,13,8,11,6,4,};
294 return &RCSetsTable[RCSetStartTable[RC->getID()]];
295}
296
297/// Get the dimensions of register pressure impacted by this register unit.
298/// Returns a -1 terminated array of pressure set IDs
299const int *NVPTXGenRegisterInfo::
300getRegUnitPressureSets(MCRegUnit RegUnit) const {
301 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
302 static const uint8_t RUSetStartTable[] = {
303 13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,0,0,0,0,0,8,8,8,8,8,6,6,6,6,6,4,4,4,4,4,2,2,2,2,2,11,6,11,6,};
304 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
305}
306
307extern const MCRegisterDesc NVPTXRegDesc[];
308extern const int16_t NVPTXRegDiffLists[];
309extern const LaneBitmask NVPTXLaneMaskLists[];
310extern const char NVPTXRegStrings[];
311extern const char NVPTXRegClassStrings[];
312extern const MCPhysReg NVPTXRegUnitRoots[][2];
313extern const uint16_t NVPTXSubRegIdxLists[];
314extern const uint16_t NVPTXRegEncodingTable[];
315NVPTXGenRegisterInfo::
316NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
317 unsigned PC, unsigned HwMode)
318 : TargetRegisterInfo(&NVPTXRegInfoDesc, RegisterClasses, RegisterClasses+7,
319 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
320 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
321 InitMCRegisterInfo(D: NVPTXRegDesc, NR: 63, RA, PC,
322 C: NVPTXMCRegisterClasses, NC: 7,
323 RURoots: NVPTXRegUnitRoots,
324 NRU: 62,
325 DL: NVPTXRegDiffLists,
326 RUMS: NVPTXLaneMaskLists,
327 Strings: NVPTXRegStrings,
328 ClassStrings: NVPTXRegClassStrings,
329 SubIndices: NVPTXSubRegIdxLists,
330 NumIndices: 1,
331 RET: NVPTXRegEncodingTable);
332
333}
334
335
336
337ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
338 return {};
339}
340
341bool NVPTXGenRegisterInfo::
342isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
343 return
344 false;
345}
346
347bool NVPTXGenRegisterInfo::
348isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
349 return
350 false;
351}
352
353bool NVPTXGenRegisterInfo::
354isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
355 return
356 false;
357}
358
359bool NVPTXGenRegisterInfo::
360isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
361 return
362 false;
363}
364
365bool NVPTXGenRegisterInfo::
366isConstantPhysReg(MCRegister PhysReg) const {
367 return
368 false;
369}
370
371ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
372 return {};
373}
374
375const NVPTXFrameLowering *
376NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
377 return static_cast<const NVPTXFrameLowering *>(
378 MF.getSubtarget().getFrameLowering());
379}
380
381} // end namespace llvm
382
383