1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<7, 66, 18, 7, 1, 2> NVPTXMCRegisterClassStorage;
12
13static const MVT::SimpleValueType NVPTXVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i128, MVT::Other,
17 /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
18 /* 10 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::f32, MVT::Other,
19 /* 17 */ MVT::i64, MVT::v2i32, MVT::v2f32, MVT::f64, MVT::Other,
20};
21static constexpr char NVPTXSubRegIndexStrings[] = {
22 /* dummy */ 0
23};
24
25
26static constexpr uint32_t NVPTXSubRegIndexNameOffsets[] = {
27 /* dummy */ 0
28};
29
30static const TargetRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRangeTable[] = {
31 { .Offset: 4294967295, .Size: 4294967295 },
32 { .Offset: 4294967295, .Size: 4294967295 },
33};
34
35
36static const LaneBitmask NVPTXSubRegIndexLaneMaskTable[] = {
37 LaneBitmask::getAll(),
38 };
39
40
41
42static const TargetRegisterInfo::RegClassInfo NVPTXRegClassInfos[] = {
43 // Mode = 0 (DefaultMode)
44 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*NVPTXVTLists+*/.VTListOffset: 0 }, // B1
45 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*NVPTXVTLists+*/.VTListOffset: 6 }, // B16
46 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 2 }, // SpecialRegs
47 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
49 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*NVPTXVTLists+*/.VTListOffset: 17 }, // B64
50 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*NVPTXVTLists+*/.VTListOffset: 4 }, // B128
51 // Mode = 1 (NVPTX64)
52 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*NVPTXVTLists+*/.VTListOffset: 0 }, // B1
53 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*NVPTXVTLists+*/.VTListOffset: 6 }, // B16
54 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 2 }, // SpecialRegs
55 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32
56 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
57 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*NVPTXVTLists+*/.VTListOffset: 17 }, // B64
58 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*NVPTXVTLists+*/.VTListOffset: 4 }, // B128
59};
60
61static const uint8_t NVPTXCostPerUseTable[] = {
620, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
63
64
65static const bool NVPTXInAllocatableClassTable[] = {
66false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
67
68
69static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
70.CostPerUse: NVPTXCostPerUseTable, .NumCosts: 1, .InAllocatableClass: NVPTXInAllocatableClassTable};
71
72/// Get the weight in units of pressure for this register class.
73const RegClassWeight &NVPTXGenRegisterInfo::
74getRegClassWeight(const TargetRegisterClass *RC) const {
75 static const RegClassWeight RCWeightTable[] = {
76 {.RegWeight: 1, .WeightLimit: 5}, // B1
77 {.RegWeight: 1, .WeightLimit: 5}, // B16
78 {.RegWeight: 1, .WeightLimit: 35}, // SpecialRegs
79 {.RegWeight: 1, .WeightLimit: 7}, // B32
80 {.RegWeight: 1, .WeightLimit: 2}, // B32_and_SpecialRegs
81 {.RegWeight: 1, .WeightLimit: 7}, // B64
82 {.RegWeight: 1, .WeightLimit: 5}, // B128
83 };
84 return RCWeightTable[RC->getID()];
85}
86
87/// Get the weight in units of pressure for this register unit.
88unsigned NVPTXGenRegisterInfo::
89getRegUnitWeight(MCRegUnit RegUnit) const {
90 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
91 // All register units have unit weight.
92 return 1;
93}
94
95
96// Get the number of dimensions of register pressure.
97unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
98 return 8;
99}
100
101// Get the name of this register unit pressure set.
102const char *NVPTXGenRegisterInfo::
103getRegPressureSetName(unsigned Idx) const {
104 static const char *PressureNameTable[] = {
105 "B32_and_SpecialRegs",
106 "B1",
107 "B16",
108 "B128",
109 "B32",
110 "B64",
111 "SpecialRegs",
112 "SpecialRegs_with_B32",
113 };
114 return PressureNameTable[Idx];
115}
116
117// Get the register unit pressure limit for this dimension.
118// This limit must be adjusted dynamically for reserved registers.
119unsigned NVPTXGenRegisterInfo::
120getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
121 static const uint8_t PressureLimitTable[] = {
122 2, // 0: B32_and_SpecialRegs
123 5, // 1: B1
124 5, // 2: B16
125 5, // 3: B128
126 7, // 4: B32
127 7, // 5: B64
128 35, // 6: SpecialRegs
129 40, // 7: SpecialRegs_with_B32
130 };
131 return PressureLimitTable[Idx];
132}
133
134/// Get the register class for this pressure set with the largest
135/// `RegClassWeight::WeightLimit`.
136const TargetRegisterClass *NVPTXGenRegisterInfo::
137getLargestRegClassForRegPressureSet(unsigned Idx) const {
138 static const uint8_t PSetRegClassTable[] = {
139 NVPTX::B32_and_SpecialRegsRegClassID, // 0: B32_and_SpecialRegs
140 NVPTX::B1RegClassID, // 1: B1
141 NVPTX::B16RegClassID, // 2: B16
142 NVPTX::B128RegClassID, // 3: B128
143 NVPTX::B32RegClassID, // 4: B32
144 NVPTX::B64RegClassID, // 5: B64
145 NVPTX::SpecialRegsRegClassID, // 6: SpecialRegs
146 NVPTX::SpecialRegsRegClassID, // 7: SpecialRegs_with_B32
147 };
148 return getRegClass(i: PSetRegClassTable[Idx]);
149}
150
151/// Table of pressure sets per register class or unit.
152static const int RCSetsTable[] = {
153 /* 0 */ 1, -1,
154 /* 2 */ 2, -1,
155 /* 4 */ 3, -1,
156 /* 6 */ 5, -1,
157 /* 8 */ 4, 7, -1,
158 /* 11 */ 0, 4, 6, 7, -1,
159};
160
161/// Get the dimensions of register pressure impacted by this register class.
162/// Returns a -1 terminated array of pressure set IDs
163const int *NVPTXGenRegisterInfo::
164getRegClassPressureSets(const TargetRegisterClass *RC) const {
165 static const uint8_t RCSetStartTable[] = {
166 0,2,13,8,11,6,4,};
167 return &RCSetsTable[RCSetStartTable[RC->getID()]];
168}
169
170/// Get the dimensions of register pressure impacted by this register unit.
171/// Returns a -1 terminated array of pressure set IDs
172const int *NVPTXGenRegisterInfo::
173getRegUnitPressureSets(MCRegUnit RegUnit) const {
174 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
175 static const uint8_t RUSetStartTable[] = {
176 13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,0,0,0,0,0,8,8,8,8,8,6,6,6,6,6,4,4,4,4,4,2,2,2,2,2,11,6,11,6,};
177 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
178}
179
180
181// Register to minimal register class mapping
182
183const TargetRegisterClass *NVPTXGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
184 static const uint16_t InvalidRegClassID = UINT16_MAX;
185
186 static const uint16_t Mapping[63] = {
187 InvalidRegClassID, // NoRegister
188 NVPTX::SpecialRegsRegClassID, // VRDepot
189 NVPTX::SpecialRegsRegClassID, // ENVREG0
190 NVPTX::SpecialRegsRegClassID, // ENVREG1
191 NVPTX::SpecialRegsRegClassID, // ENVREG2
192 NVPTX::SpecialRegsRegClassID, // ENVREG3
193 NVPTX::SpecialRegsRegClassID, // ENVREG4
194 NVPTX::SpecialRegsRegClassID, // ENVREG5
195 NVPTX::SpecialRegsRegClassID, // ENVREG6
196 NVPTX::SpecialRegsRegClassID, // ENVREG7
197 NVPTX::SpecialRegsRegClassID, // ENVREG8
198 NVPTX::SpecialRegsRegClassID, // ENVREG9
199 NVPTX::SpecialRegsRegClassID, // ENVREG10
200 NVPTX::SpecialRegsRegClassID, // ENVREG11
201 NVPTX::SpecialRegsRegClassID, // ENVREG12
202 NVPTX::SpecialRegsRegClassID, // ENVREG13
203 NVPTX::SpecialRegsRegClassID, // ENVREG14
204 NVPTX::SpecialRegsRegClassID, // ENVREG15
205 NVPTX::SpecialRegsRegClassID, // ENVREG16
206 NVPTX::SpecialRegsRegClassID, // ENVREG17
207 NVPTX::SpecialRegsRegClassID, // ENVREG18
208 NVPTX::SpecialRegsRegClassID, // ENVREG19
209 NVPTX::SpecialRegsRegClassID, // ENVREG20
210 NVPTX::SpecialRegsRegClassID, // ENVREG21
211 NVPTX::SpecialRegsRegClassID, // ENVREG22
212 NVPTX::SpecialRegsRegClassID, // ENVREG23
213 NVPTX::SpecialRegsRegClassID, // ENVREG24
214 NVPTX::SpecialRegsRegClassID, // ENVREG25
215 NVPTX::SpecialRegsRegClassID, // ENVREG26
216 NVPTX::SpecialRegsRegClassID, // ENVREG27
217 NVPTX::SpecialRegsRegClassID, // ENVREG28
218 NVPTX::SpecialRegsRegClassID, // ENVREG29
219 NVPTX::SpecialRegsRegClassID, // ENVREG30
220 NVPTX::SpecialRegsRegClassID, // ENVREG31
221 NVPTX::B1RegClassID, // P0
222 NVPTX::B1RegClassID, // P1
223 NVPTX::B1RegClassID, // P2
224 NVPTX::B1RegClassID, // P3
225 NVPTX::B1RegClassID, // P4
226 NVPTX::B32RegClassID, // R0
227 NVPTX::B32RegClassID, // R1
228 NVPTX::B32RegClassID, // R2
229 NVPTX::B32RegClassID, // R3
230 NVPTX::B32RegClassID, // R4
231 NVPTX::B64RegClassID, // RL0
232 NVPTX::B64RegClassID, // RL1
233 NVPTX::B64RegClassID, // RL2
234 NVPTX::B64RegClassID, // RL3
235 NVPTX::B64RegClassID, // RL4
236 NVPTX::B128RegClassID, // RQ0
237 NVPTX::B128RegClassID, // RQ1
238 NVPTX::B128RegClassID, // RQ2
239 NVPTX::B128RegClassID, // RQ3
240 NVPTX::B128RegClassID, // RQ4
241 NVPTX::B16RegClassID, // RS0
242 NVPTX::B16RegClassID, // RS1
243 NVPTX::B16RegClassID, // RS2
244 NVPTX::B16RegClassID, // RS3
245 NVPTX::B16RegClassID, // RS4
246 NVPTX::B32_and_SpecialRegsRegClassID, // VRFrame32
247 NVPTX::B64RegClassID, // VRFrame64
248 NVPTX::B32_and_SpecialRegsRegClassID, // VRFrameLocal32
249 NVPTX::B64RegClassID, // VRFrameLocal64
250 };
251
252 assert(Reg < ArrayRef(Mapping).size());
253 unsigned RCID = Mapping[Reg.id()];
254 if (RCID == InvalidRegClassID)
255 return nullptr;
256 return &NVPTXMCRegisterClassStorage.Classes[RCID];
257}
258extern const MCRegisterDesc NVPTXRegDesc[];
259extern const int16_t NVPTXRegDiffLists[];
260extern const LaneBitmask NVPTXLaneMaskLists[];
261extern const char NVPTXRegStrings[];
262extern const char NVPTXRegClassStrings[];
263extern const MCPhysReg NVPTXRegUnitRoots[][2];
264extern const uint16_t NVPTXSubRegIdxLists[];
265extern const uint16_t NVPTXRegEncodingTable[];
266
267NVPTXGenRegisterInfo::
268NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
269 unsigned PC, unsigned HwMode)
270 : TargetRegisterInfo(&NVPTXRegInfoDesc,
271 NVPTXSubRegIndexStrings, NVPTXSubRegIndexNameOffsets,
272 NVPTXSubRegIdxRangeTable, NVPTXSubRegIndexLaneMaskTable,
273
274 LaneBitmask(0xFFFFFFFFFFFFFFFF), NVPTXRegClassInfos, NVPTXVTLists, HwMode) {
275 InitMCRegisterInfo(D: NVPTXRegDesc, NR: 63, RA, PC,
276 C: &getNVPTXMCRegisterClass(RC: 0), NC: 7, RURoots: NVPTXRegUnitRoots, NRU: 62, DL: NVPTXRegDiffLists,
277 RUMS: NVPTXLaneMaskLists, Strings: NVPTXRegStrings, ClassStrings: NVPTXRegClassStrings, SubIndices: NVPTXSubRegIdxLists, NumIndices: 1,
278 RET: NVPTXRegEncodingTable, RUI: nullptr);
279
280}
281
282
283
284ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
285 return {};
286}
287
288bool NVPTXGenRegisterInfo::
289isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
290 return
291 false;
292}
293
294bool NVPTXGenRegisterInfo::
295isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
296 return
297 false;
298}
299
300bool NVPTXGenRegisterInfo::
301isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
302 return
303 false;
304}
305
306bool NVPTXGenRegisterInfo::
307isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
308 return
309 false;
310}
311
312bool NVPTXGenRegisterInfo::
313isConstantPhysReg(MCRegister PhysReg) const {
314 return
315 false;
316}
317
318ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
319 return {};
320}
321
322const NVPTXFrameLowering *
323NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
324 return static_cast<const NVPTXFrameLowering *>(
325 MF.getSubtarget().getFrameLowering());
326}
327
328
329} // namespace llvm
330