1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass NVPTXMCRegisterClasses[];
12
13static const MVT::SimpleValueType NVPTXVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i128, MVT::Other,
17 /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
18 /* 10 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::f32, MVT::Other,
19 /* 17 */ MVT::i64, MVT::v2i32, MVT::v2f32, MVT::f64, MVT::Other,
20};
21static constexpr char NVPTXSubRegIndexStrings[] = {
22 /* dummy */ 0
23};
24
25
26static constexpr uint32_t NVPTXSubRegIndexNameOffsets[] = {
27 /* dummy */ 0
28};
29
30static const TargetRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRangeTable[] = {
31 { .Offset: 65535, .Size: 65535 },
32 { .Offset: 65535, .Size: 65535 },
33};
34
35
36static const LaneBitmask NVPTXSubRegIndexLaneMaskTable[] = {
37 LaneBitmask::getAll(),
38 };
39
40
41
42static const TargetRegisterInfo::RegClassInfo NVPTXRegClassInfos[] = {
43 // Mode = 0 (DefaultMode)
44 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*NVPTXVTLists+*/.VTListOffset: 0 }, // B1
45 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*NVPTXVTLists+*/.VTListOffset: 6 }, // B16
46 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 2 }, // SpecialRegs
47 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
49 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*NVPTXVTLists+*/.VTListOffset: 17 }, // B64
50 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*NVPTXVTLists+*/.VTListOffset: 4 }, // B128
51 // Mode = 1 (NVPTX64)
52 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*NVPTXVTLists+*/.VTListOffset: 0 }, // B1
53 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*NVPTXVTLists+*/.VTListOffset: 6 }, // B16
54 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 2 }, // SpecialRegs
55 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32
56 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
57 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*NVPTXVTLists+*/.VTListOffset: 17 }, // B64
58 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*NVPTXVTLists+*/.VTListOffset: 4 }, // B128
59};
60static const uint32_t B1SubClassMask[] = {
61 0x00000001,
62};
63
64static const uint32_t B16SubClassMask[] = {
65 0x00000002,
66};
67
68static const uint32_t SpecialRegsSubClassMask[] = {
69 0x00000014,
70};
71
72static const uint32_t B32SubClassMask[] = {
73 0x00000018,
74};
75
76static const uint32_t B32_and_SpecialRegsSubClassMask[] = {
77 0x00000010,
78};
79
80static const uint32_t B64SubClassMask[] = {
81 0x00000020,
82};
83
84static const uint32_t B128SubClassMask[] = {
85 0x00000040,
86};
87
88static const uint16_t SuperRegIdxSeqs[] = {
89 /* 0 */ 0,
90};
91
92static unsigned const B32_and_SpecialRegsSuperclasses[] = {
93 NVPTX::SpecialRegsRegClassID,
94 NVPTX::B32RegClassID,
95};
96
97namespace NVPTX {
98
99// Register class instances.
100 extern const TargetRegisterClass B1RegClass = {
101 .MC: &NVPTXMCRegisterClasses[B1RegClassID],
102 .SubClassMask: B1SubClassMask,
103 .SuperRegIndices: SuperRegIdxSeqs + 0,
104 .LaneMask: LaneBitmask(0x0000000000000001),
105 .AllocationPriority: 0,
106 .GlobalPriority: false,
107 .TSFlags: 0x00, /* TSFlags */
108 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
109 .CoveredBySubRegs: false, /* CoveredBySubRegs */
110 .SuperClasses: nullptr, .SuperClassesSize: 0,
111 .OrderFunc: nullptr
112 };
113
114 extern const TargetRegisterClass B16RegClass = {
115 .MC: &NVPTXMCRegisterClasses[B16RegClassID],
116 .SubClassMask: B16SubClassMask,
117 .SuperRegIndices: SuperRegIdxSeqs + 0,
118 .LaneMask: LaneBitmask(0x0000000000000001),
119 .AllocationPriority: 0,
120 .GlobalPriority: false,
121 .TSFlags: 0x00, /* TSFlags */
122 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
123 .CoveredBySubRegs: false, /* CoveredBySubRegs */
124 .SuperClasses: nullptr, .SuperClassesSize: 0,
125 .OrderFunc: nullptr
126 };
127
128 extern const TargetRegisterClass SpecialRegsRegClass = {
129 .MC: &NVPTXMCRegisterClasses[SpecialRegsRegClassID],
130 .SubClassMask: SpecialRegsSubClassMask,
131 .SuperRegIndices: SuperRegIdxSeqs + 0,
132 .LaneMask: LaneBitmask(0x0000000000000001),
133 .AllocationPriority: 0,
134 .GlobalPriority: false,
135 .TSFlags: 0x00, /* TSFlags */
136 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
137 .CoveredBySubRegs: false, /* CoveredBySubRegs */
138 .SuperClasses: nullptr, .SuperClassesSize: 0,
139 .OrderFunc: nullptr
140 };
141
142 extern const TargetRegisterClass B32RegClass = {
143 .MC: &NVPTXMCRegisterClasses[B32RegClassID],
144 .SubClassMask: B32SubClassMask,
145 .SuperRegIndices: SuperRegIdxSeqs + 0,
146 .LaneMask: LaneBitmask(0x0000000000000001),
147 .AllocationPriority: 0,
148 .GlobalPriority: false,
149 .TSFlags: 0x00, /* TSFlags */
150 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
151 .CoveredBySubRegs: false, /* CoveredBySubRegs */
152 .SuperClasses: nullptr, .SuperClassesSize: 0,
153 .OrderFunc: nullptr
154 };
155
156 extern const TargetRegisterClass B32_and_SpecialRegsRegClass = {
157 .MC: &NVPTXMCRegisterClasses[B32_and_SpecialRegsRegClassID],
158 .SubClassMask: B32_and_SpecialRegsSubClassMask,
159 .SuperRegIndices: SuperRegIdxSeqs + 0,
160 .LaneMask: LaneBitmask(0x0000000000000001),
161 .AllocationPriority: 0,
162 .GlobalPriority: false,
163 .TSFlags: 0x00, /* TSFlags */
164 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
165 .CoveredBySubRegs: false, /* CoveredBySubRegs */
166 .SuperClasses: B32_and_SpecialRegsSuperclasses, .SuperClassesSize: 2,
167 .OrderFunc: nullptr
168 };
169
170 extern const TargetRegisterClass B64RegClass = {
171 .MC: &NVPTXMCRegisterClasses[B64RegClassID],
172 .SubClassMask: B64SubClassMask,
173 .SuperRegIndices: SuperRegIdxSeqs + 0,
174 .LaneMask: LaneBitmask(0x0000000000000001),
175 .AllocationPriority: 0,
176 .GlobalPriority: false,
177 .TSFlags: 0x00, /* TSFlags */
178 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
179 .CoveredBySubRegs: false, /* CoveredBySubRegs */
180 .SuperClasses: nullptr, .SuperClassesSize: 0,
181 .OrderFunc: nullptr
182 };
183
184 extern const TargetRegisterClass B128RegClass = {
185 .MC: &NVPTXMCRegisterClasses[B128RegClassID],
186 .SubClassMask: B128SubClassMask,
187 .SuperRegIndices: SuperRegIdxSeqs + 0,
188 .LaneMask: LaneBitmask(0x0000000000000001),
189 .AllocationPriority: 0,
190 .GlobalPriority: false,
191 .TSFlags: 0x00, /* TSFlags */
192 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
193 .CoveredBySubRegs: false, /* CoveredBySubRegs */
194 .SuperClasses: nullptr, .SuperClassesSize: 0,
195 .OrderFunc: nullptr
196 };
197
198
199} // namespace NVPTX
200static const TargetRegisterClass *const NVPTXRegisterClasses[] = {
201 &NVPTX::B1RegClass,
202 &NVPTX::B16RegClass,
203 &NVPTX::SpecialRegsRegClass,
204 &NVPTX::B32RegClass,
205 &NVPTX::B32_and_SpecialRegsRegClass,
206 &NVPTX::B64RegClass,
207 &NVPTX::B128RegClass,
208 };
209
210static const uint8_t NVPTXCostPerUseTable[] = {
2110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
212
213
214static const bool NVPTXInAllocatableClassTable[] = {
215false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
216
217
218static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
219.CostPerUse: NVPTXCostPerUseTable, .NumCosts: 1, .InAllocatableClass: NVPTXInAllocatableClassTable};
220
221/// Get the weight in units of pressure for this register class.
222const RegClassWeight &NVPTXGenRegisterInfo::
223getRegClassWeight(const TargetRegisterClass *RC) const {
224 static const RegClassWeight RCWeightTable[] = {
225 {.RegWeight: 1, .WeightLimit: 5}, // B1
226 {.RegWeight: 1, .WeightLimit: 5}, // B16
227 {.RegWeight: 1, .WeightLimit: 35}, // SpecialRegs
228 {.RegWeight: 1, .WeightLimit: 7}, // B32
229 {.RegWeight: 1, .WeightLimit: 2}, // B32_and_SpecialRegs
230 {.RegWeight: 1, .WeightLimit: 7}, // B64
231 {.RegWeight: 1, .WeightLimit: 5}, // B128
232 };
233 return RCWeightTable[RC->getID()];
234}
235
236/// Get the weight in units of pressure for this register unit.
237unsigned NVPTXGenRegisterInfo::
238getRegUnitWeight(MCRegUnit RegUnit) const {
239 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
240 // All register units have unit weight.
241 return 1;
242}
243
244
245// Get the number of dimensions of register pressure.
246unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
247 return 8;
248}
249
250// Get the name of this register unit pressure set.
251const char *NVPTXGenRegisterInfo::
252getRegPressureSetName(unsigned Idx) const {
253 static const char *PressureNameTable[] = {
254 "B32_and_SpecialRegs",
255 "B1",
256 "B16",
257 "B128",
258 "B32",
259 "B64",
260 "SpecialRegs",
261 "SpecialRegs_with_B32",
262 };
263 return PressureNameTable[Idx];
264}
265
266// Get the register unit pressure limit for this dimension.
267// This limit must be adjusted dynamically for reserved registers.
268unsigned NVPTXGenRegisterInfo::
269getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
270 static const uint8_t PressureLimitTable[] = {
271 2, // 0: B32_and_SpecialRegs
272 5, // 1: B1
273 5, // 2: B16
274 5, // 3: B128
275 7, // 4: B32
276 7, // 5: B64
277 35, // 6: SpecialRegs
278 40, // 7: SpecialRegs_with_B32
279 };
280 return PressureLimitTable[Idx];
281}
282
283/// Table of pressure sets per register class or unit.
284static const int RCSetsTable[] = {
285 /* 0 */ 1, -1,
286 /* 2 */ 2, -1,
287 /* 4 */ 3, -1,
288 /* 6 */ 5, -1,
289 /* 8 */ 4, 7, -1,
290 /* 11 */ 0, 4, 6, 7, -1,
291};
292
293/// Get the dimensions of register pressure impacted by this register class.
294/// Returns a -1 terminated array of pressure set IDs
295const int *NVPTXGenRegisterInfo::
296getRegClassPressureSets(const TargetRegisterClass *RC) const {
297 static const uint8_t RCSetStartTable[] = {
298 0,2,13,8,11,6,4,};
299 return &RCSetsTable[RCSetStartTable[RC->getID()]];
300}
301
302/// Get the dimensions of register pressure impacted by this register unit.
303/// Returns a -1 terminated array of pressure set IDs
304const int *NVPTXGenRegisterInfo::
305getRegUnitPressureSets(MCRegUnit RegUnit) const {
306 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
307 static const uint8_t RUSetStartTable[] = {
308 13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,0,0,0,0,0,8,8,8,8,8,6,6,6,6,6,4,4,4,4,4,2,2,2,2,2,11,6,11,6,};
309 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
310}
311
312extern const MCRegisterDesc NVPTXRegDesc[];
313extern const int16_t NVPTXRegDiffLists[];
314extern const LaneBitmask NVPTXLaneMaskLists[];
315extern const char NVPTXRegStrings[];
316extern const char NVPTXRegClassStrings[];
317extern const MCPhysReg NVPTXRegUnitRoots[][2];
318extern const uint16_t NVPTXSubRegIdxLists[];
319extern const uint16_t NVPTXRegEncodingTable[];
320
321NVPTXGenRegisterInfo::
322NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
323 unsigned PC, unsigned HwMode)
324 : TargetRegisterInfo(&NVPTXRegInfoDesc, NVPTXRegisterClasses,
325 NVPTXSubRegIndexStrings, NVPTXSubRegIndexNameOffsets,
326 NVPTXSubRegIdxRangeTable, NVPTXSubRegIndexLaneMaskTable,
327
328 LaneBitmask(0xFFFFFFFFFFFFFFFF), NVPTXRegClassInfos, NVPTXVTLists, HwMode) {
329 InitMCRegisterInfo(D: NVPTXRegDesc, NR: 63, RA, PC,
330 C: NVPTXMCRegisterClasses, NC: 7, RURoots: NVPTXRegUnitRoots, NRU: 62, DL: NVPTXRegDiffLists,
331 RUMS: NVPTXLaneMaskLists, Strings: NVPTXRegStrings, ClassStrings: NVPTXRegClassStrings, SubIndices: NVPTXSubRegIdxLists, NumIndices: 1,
332 RET: NVPTXRegEncodingTable, RUI: nullptr);
333
334}
335
336
337
338ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
339 return {};
340}
341
342bool NVPTXGenRegisterInfo::
343isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
344 return
345 false;
346}
347
348bool NVPTXGenRegisterInfo::
349isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
350 return
351 false;
352}
353
354bool NVPTXGenRegisterInfo::
355isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
356 return
357 false;
358}
359
360bool NVPTXGenRegisterInfo::
361isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
362 return
363 false;
364}
365
366bool NVPTXGenRegisterInfo::
367isConstantPhysReg(MCRegister PhysReg) const {
368 return
369 false;
370}
371
372ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
373 return {};
374}
375
376const NVPTXFrameLowering *
377NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
378 return static_cast<const NVPTXFrameLowering *>(
379 MF.getSubtarget().getFrameLowering());
380}
381
382
383} // namespace llvm
384