1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass NVPTXMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i128, MVT::Other,
17 /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
18 /* 10 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::f32, MVT::Other,
19 /* 17 */ MVT::i64, MVT::v2i32, MVT::v2f32, MVT::f64, MVT::Other,
20};
21static constexpr char NVPTXSubRegIndexStrings[] = {
22 /* dummy */ 0
23};
24
25
26static constexpr uint32_t NVPTXSubRegIndexNameOffsets[] = {
27 /* dummy */ 0
28};
29
30static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
31 { .Offset: 65535, .Size: 65535 },
32 { .Offset: 65535, .Size: 65535 },
33};
34
35
36static const LaneBitmask SubRegIndexLaneMaskTable[] = {
37 LaneBitmask::getAll(),
38 };
39
40
41
42static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
43 // Mode = 0 (DefaultMode)
44 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // B1
45 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 6 }, // B16
46 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // SpecialRegs
47 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // B32
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
49 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 17 }, // B64
50 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 4 }, // B128
51 // Mode = 1 (NVPTX64)
52 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // B1
53 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 6 }, // B16
54 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // SpecialRegs
55 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // B32
56 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
57 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 17 }, // B64
58 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 4 }, // B128
59};
60static const uint32_t B1SubClassMask[] = {
61 0x00000001,
62};
63
64static const uint32_t B16SubClassMask[] = {
65 0x00000002,
66};
67
68static const uint32_t SpecialRegsSubClassMask[] = {
69 0x00000014,
70};
71
72static const uint32_t B32SubClassMask[] = {
73 0x00000018,
74};
75
76static const uint32_t B32_and_SpecialRegsSubClassMask[] = {
77 0x00000010,
78};
79
80static const uint32_t B64SubClassMask[] = {
81 0x00000020,
82};
83
84static const uint32_t B128SubClassMask[] = {
85 0x00000040,
86};
87
88static const uint16_t SuperRegIdxSeqs[] = {
89 /* 0 */ 0,
90};
91
92static unsigned const B32_and_SpecialRegsSuperclasses[] = {
93 NVPTX::SpecialRegsRegClassID,
94 NVPTX::B32RegClassID,
95};
96
97namespace NVPTX {
98
99// Register class instances
100 extern const TargetRegisterClass B1RegClass = {
101 .MC: &NVPTXMCRegisterClasses[B1RegClassID],
102 .SubClassMask: B1SubClassMask,
103 .SuperRegIndices: SuperRegIdxSeqs + 0,
104 .LaneMask: LaneBitmask(0x0000000000000001),
105 .AllocationPriority: 0,
106 .GlobalPriority: false,
107 .TSFlags: 0x00, /* TSFlags */
108 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
109 .CoveredBySubRegs: false, /* CoveredBySubRegs */
110 .SuperClasses: nullptr, .SuperClassesSize: 0,
111 .OrderFunc: nullptr
112 };
113
114 extern const TargetRegisterClass B16RegClass = {
115 .MC: &NVPTXMCRegisterClasses[B16RegClassID],
116 .SubClassMask: B16SubClassMask,
117 .SuperRegIndices: SuperRegIdxSeqs + 0,
118 .LaneMask: LaneBitmask(0x0000000000000001),
119 .AllocationPriority: 0,
120 .GlobalPriority: false,
121 .TSFlags: 0x00, /* TSFlags */
122 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
123 .CoveredBySubRegs: false, /* CoveredBySubRegs */
124 .SuperClasses: nullptr, .SuperClassesSize: 0,
125 .OrderFunc: nullptr
126 };
127
128 extern const TargetRegisterClass SpecialRegsRegClass = {
129 .MC: &NVPTXMCRegisterClasses[SpecialRegsRegClassID],
130 .SubClassMask: SpecialRegsSubClassMask,
131 .SuperRegIndices: SuperRegIdxSeqs + 0,
132 .LaneMask: LaneBitmask(0x0000000000000001),
133 .AllocationPriority: 0,
134 .GlobalPriority: false,
135 .TSFlags: 0x00, /* TSFlags */
136 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
137 .CoveredBySubRegs: false, /* CoveredBySubRegs */
138 .SuperClasses: nullptr, .SuperClassesSize: 0,
139 .OrderFunc: nullptr
140 };
141
142 extern const TargetRegisterClass B32RegClass = {
143 .MC: &NVPTXMCRegisterClasses[B32RegClassID],
144 .SubClassMask: B32SubClassMask,
145 .SuperRegIndices: SuperRegIdxSeqs + 0,
146 .LaneMask: LaneBitmask(0x0000000000000001),
147 .AllocationPriority: 0,
148 .GlobalPriority: false,
149 .TSFlags: 0x00, /* TSFlags */
150 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
151 .CoveredBySubRegs: false, /* CoveredBySubRegs */
152 .SuperClasses: nullptr, .SuperClassesSize: 0,
153 .OrderFunc: nullptr
154 };
155
156 extern const TargetRegisterClass B32_and_SpecialRegsRegClass = {
157 .MC: &NVPTXMCRegisterClasses[B32_and_SpecialRegsRegClassID],
158 .SubClassMask: B32_and_SpecialRegsSubClassMask,
159 .SuperRegIndices: SuperRegIdxSeqs + 0,
160 .LaneMask: LaneBitmask(0x0000000000000001),
161 .AllocationPriority: 0,
162 .GlobalPriority: false,
163 .TSFlags: 0x00, /* TSFlags */
164 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
165 .CoveredBySubRegs: false, /* CoveredBySubRegs */
166 .SuperClasses: B32_and_SpecialRegsSuperclasses, .SuperClassesSize: 2,
167 .OrderFunc: nullptr
168 };
169
170 extern const TargetRegisterClass B64RegClass = {
171 .MC: &NVPTXMCRegisterClasses[B64RegClassID],
172 .SubClassMask: B64SubClassMask,
173 .SuperRegIndices: SuperRegIdxSeqs + 0,
174 .LaneMask: LaneBitmask(0x0000000000000001),
175 .AllocationPriority: 0,
176 .GlobalPriority: false,
177 .TSFlags: 0x00, /* TSFlags */
178 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
179 .CoveredBySubRegs: false, /* CoveredBySubRegs */
180 .SuperClasses: nullptr, .SuperClassesSize: 0,
181 .OrderFunc: nullptr
182 };
183
184 extern const TargetRegisterClass B128RegClass = {
185 .MC: &NVPTXMCRegisterClasses[B128RegClassID],
186 .SubClassMask: B128SubClassMask,
187 .SuperRegIndices: SuperRegIdxSeqs + 0,
188 .LaneMask: LaneBitmask(0x0000000000000001),
189 .AllocationPriority: 0,
190 .GlobalPriority: false,
191 .TSFlags: 0x00, /* TSFlags */
192 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
193 .CoveredBySubRegs: false, /* CoveredBySubRegs */
194 .SuperClasses: nullptr, .SuperClassesSize: 0,
195 .OrderFunc: nullptr
196 };
197
198
199} // namespace NVPTX
200namespace {
201
202 const TargetRegisterClass *const RegisterClasses[] = {
203 &NVPTX::B1RegClass,
204 &NVPTX::B16RegClass,
205 &NVPTX::SpecialRegsRegClass,
206 &NVPTX::B32RegClass,
207 &NVPTX::B32_and_SpecialRegsRegClass,
208 &NVPTX::B64RegClass,
209 &NVPTX::B128RegClass,
210 };
211} // namespace
212
213static const uint8_t CostPerUseTable[] = {
2140, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
215
216
217static const bool InAllocatableClassTable[] = {
218false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
219
220
221static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
222.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
223
224/// Get the weight in units of pressure for this register class.
225const RegClassWeight &NVPTXGenRegisterInfo::
226getRegClassWeight(const TargetRegisterClass *RC) const {
227 static const RegClassWeight RCWeightTable[] = {
228 {.RegWeight: 1, .WeightLimit: 5}, // B1
229 {.RegWeight: 1, .WeightLimit: 5}, // B16
230 {.RegWeight: 1, .WeightLimit: 35}, // SpecialRegs
231 {.RegWeight: 1, .WeightLimit: 7}, // B32
232 {.RegWeight: 1, .WeightLimit: 2}, // B32_and_SpecialRegs
233 {.RegWeight: 1, .WeightLimit: 7}, // B64
234 {.RegWeight: 1, .WeightLimit: 5}, // B128
235 };
236 return RCWeightTable[RC->getID()];
237}
238
239/// Get the weight in units of pressure for this register unit.
240unsigned NVPTXGenRegisterInfo::
241getRegUnitWeight(MCRegUnit RegUnit) const {
242 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
243 // All register units have unit weight.
244 return 1;
245}
246
247
248// Get the number of dimensions of register pressure.
249unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
250 return 8;
251}
252
253// Get the name of this register unit pressure set.
254const char *NVPTXGenRegisterInfo::
255getRegPressureSetName(unsigned Idx) const {
256 static const char *PressureNameTable[] = {
257 "B32_and_SpecialRegs",
258 "B1",
259 "B16",
260 "B128",
261 "B32",
262 "B64",
263 "SpecialRegs",
264 "SpecialRegs_with_B32",
265 };
266 return PressureNameTable[Idx];
267}
268
269// Get the register unit pressure limit for this dimension.
270// This limit must be adjusted dynamically for reserved registers.
271unsigned NVPTXGenRegisterInfo::
272getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
273 static const uint8_t PressureLimitTable[] = {
274 2, // 0: B32_and_SpecialRegs
275 5, // 1: B1
276 5, // 2: B16
277 5, // 3: B128
278 7, // 4: B32
279 7, // 5: B64
280 35, // 6: SpecialRegs
281 40, // 7: SpecialRegs_with_B32
282 };
283 return PressureLimitTable[Idx];
284}
285
286/// Table of pressure sets per register class or unit.
287static const int RCSetsTable[] = {
288 /* 0 */ 1, -1,
289 /* 2 */ 2, -1,
290 /* 4 */ 3, -1,
291 /* 6 */ 5, -1,
292 /* 8 */ 4, 7, -1,
293 /* 11 */ 0, 4, 6, 7, -1,
294};
295
296/// Get the dimensions of register pressure impacted by this register class.
297/// Returns a -1 terminated array of pressure set IDs
298const int *NVPTXGenRegisterInfo::
299getRegClassPressureSets(const TargetRegisterClass *RC) const {
300 static const uint8_t RCSetStartTable[] = {
301 0,2,13,8,11,6,4,};
302 return &RCSetsTable[RCSetStartTable[RC->getID()]];
303}
304
305/// Get the dimensions of register pressure impacted by this register unit.
306/// Returns a -1 terminated array of pressure set IDs
307const int *NVPTXGenRegisterInfo::
308getRegUnitPressureSets(MCRegUnit RegUnit) const {
309 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
310 static const uint8_t RUSetStartTable[] = {
311 13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,0,0,0,0,0,8,8,8,8,8,6,6,6,6,6,4,4,4,4,4,2,2,2,2,2,11,6,11,6,};
312 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
313}
314
315extern const MCRegisterDesc NVPTXRegDesc[];
316extern const int16_t NVPTXRegDiffLists[];
317extern const LaneBitmask NVPTXLaneMaskLists[];
318extern const char NVPTXRegStrings[];
319extern const char NVPTXRegClassStrings[];
320extern const MCPhysReg NVPTXRegUnitRoots[][2];
321extern const uint16_t NVPTXSubRegIdxLists[];
322extern const uint16_t NVPTXRegEncodingTable[];
323
324NVPTXGenRegisterInfo::
325NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
326 unsigned PC, unsigned HwMode)
327 : TargetRegisterInfo(&NVPTXRegInfoDesc, RegisterClasses, RegisterClasses+7,
328 NVPTXSubRegIndexStrings, NVPTXSubRegIndexNameOffsets,
329 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
330
331 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
332 InitMCRegisterInfo(D: NVPTXRegDesc, NR: 63, RA, PC,
333 C: NVPTXMCRegisterClasses, NC: 7,
334 RURoots: NVPTXRegUnitRoots,
335 NRU: 62,
336 DL: NVPTXRegDiffLists,
337 RUMS: NVPTXLaneMaskLists,
338 Strings: NVPTXRegStrings,
339 ClassStrings: NVPTXRegClassStrings,
340 SubIndices: NVPTXSubRegIdxLists,
341 NumIndices: 1,
342 RET: NVPTXRegEncodingTable,
343 RUI: nullptr);
344
345}
346
347
348
349ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
350 return {};
351}
352
353bool NVPTXGenRegisterInfo::
354isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
355 return
356 false;
357}
358
359bool NVPTXGenRegisterInfo::
360isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
361 return
362 false;
363}
364
365bool NVPTXGenRegisterInfo::
366isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
367 return
368 false;
369}
370
371bool NVPTXGenRegisterInfo::
372isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
373 return
374 false;
375}
376
377bool NVPTXGenRegisterInfo::
378isConstantPhysReg(MCRegister PhysReg) const {
379 return
380 false;
381}
382
383ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
384 return {};
385}
386
387const NVPTXFrameLowering *
388NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
389 return static_cast<const NVPTXFrameLowering *>(
390 MF.getSubtarget().getFrameLowering());
391}
392
393
394} // namespace llvm
395