1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass NVPTXMCRegisterClasses[];
12
13static const MVT::SimpleValueType NVPTXVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i128, MVT::Other,
17 /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
18 /* 10 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::f32, MVT::Other,
19 /* 17 */ MVT::i64, MVT::v2i32, MVT::v2f32, MVT::f64, MVT::Other,
20};
21static constexpr char NVPTXSubRegIndexStrings[] = {
22 /* dummy */ 0
23};
24
25
26static constexpr uint32_t NVPTXSubRegIndexNameOffsets[] = {
27 /* dummy */ 0
28};
29
30static const TargetRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRangeTable[] = {
31 { .Offset: 4294967295, .Size: 4294967295 },
32 { .Offset: 4294967295, .Size: 4294967295 },
33};
34
35
36static const LaneBitmask NVPTXSubRegIndexLaneMaskTable[] = {
37 LaneBitmask::getAll(),
38 };
39
40
41
42static const TargetRegisterInfo::RegClassInfo NVPTXRegClassInfos[] = {
43 // Mode = 0 (DefaultMode)
44 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*NVPTXVTLists+*/.VTListOffset: 0 }, // B1
45 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*NVPTXVTLists+*/.VTListOffset: 6 }, // B16
46 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 2 }, // SpecialRegs
47 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32
48 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
49 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*NVPTXVTLists+*/.VTListOffset: 17 }, // B64
50 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*NVPTXVTLists+*/.VTListOffset: 4 }, // B128
51 // Mode = 1 (NVPTX64)
52 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 8, /*NVPTXVTLists+*/.VTListOffset: 0 }, // B1
53 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*NVPTXVTLists+*/.VTListOffset: 6 }, // B16
54 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 2 }, // SpecialRegs
55 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32
56 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*NVPTXVTLists+*/.VTListOffset: 10 }, // B32_and_SpecialRegs
57 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*NVPTXVTLists+*/.VTListOffset: 17 }, // B64
58 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*NVPTXVTLists+*/.VTListOffset: 4 }, // B128
59};
60static const uint32_t B1SubClassMask[] = {
61 0x00000001,
62};
63
64static const uint32_t B16SubClassMask[] = {
65 0x00000002,
66};
67
68static const uint32_t SpecialRegsSubClassMask[] = {
69 0x00000014,
70};
71
72static const uint32_t B32SubClassMask[] = {
73 0x00000018,
74};
75
76static const uint32_t B32_and_SpecialRegsSubClassMask[] = {
77 0x00000010,
78};
79
80static const uint32_t B64SubClassMask[] = {
81 0x00000020,
82};
83
84static const uint32_t B128SubClassMask[] = {
85 0x00000040,
86};
87
88static const uint16_t SuperRegIdxSeqs[] = {
89 /* 0 */ 0,
90};
91
92static unsigned const B32_and_SpecialRegsSuperclasses[] = {
93 NVPTX::SpecialRegsRegClassID,
94 NVPTX::B32RegClassID,
95};
96
97namespace NVPTX {
98
99// Register class instances.
100 extern const TargetRegisterClass B1RegClass = {
101 .MC: &NVPTXMCRegisterClasses[B1RegClassID],
102 .SubClassMask: B1SubClassMask,
103 .SuperRegIndices: SuperRegIdxSeqs + 0,
104 .LaneMask: LaneBitmask(0x0000000000000001),
105 .AllocationPriority: 0,
106 .GlobalPriority: false,
107 .TSFlags: 0x00, /* TSFlags */
108 .SpillStackID: 0, /* SpillStackID */
109 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
110 .CoveredBySubRegs: false, /* CoveredBySubRegs */
111 .SuperClasses: nullptr, .SuperClassesSize: 0,
112 .OrderFunc: nullptr
113 };
114
115 extern const TargetRegisterClass B16RegClass = {
116 .MC: &NVPTXMCRegisterClasses[B16RegClassID],
117 .SubClassMask: B16SubClassMask,
118 .SuperRegIndices: SuperRegIdxSeqs + 0,
119 .LaneMask: LaneBitmask(0x0000000000000001),
120 .AllocationPriority: 0,
121 .GlobalPriority: false,
122 .TSFlags: 0x00, /* TSFlags */
123 .SpillStackID: 0, /* SpillStackID */
124 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
125 .CoveredBySubRegs: false, /* CoveredBySubRegs */
126 .SuperClasses: nullptr, .SuperClassesSize: 0,
127 .OrderFunc: nullptr
128 };
129
130 extern const TargetRegisterClass SpecialRegsRegClass = {
131 .MC: &NVPTXMCRegisterClasses[SpecialRegsRegClassID],
132 .SubClassMask: SpecialRegsSubClassMask,
133 .SuperRegIndices: SuperRegIdxSeqs + 0,
134 .LaneMask: LaneBitmask(0x0000000000000001),
135 .AllocationPriority: 0,
136 .GlobalPriority: false,
137 .TSFlags: 0x00, /* TSFlags */
138 .SpillStackID: 0, /* SpillStackID */
139 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
140 .CoveredBySubRegs: false, /* CoveredBySubRegs */
141 .SuperClasses: nullptr, .SuperClassesSize: 0,
142 .OrderFunc: nullptr
143 };
144
145 extern const TargetRegisterClass B32RegClass = {
146 .MC: &NVPTXMCRegisterClasses[B32RegClassID],
147 .SubClassMask: B32SubClassMask,
148 .SuperRegIndices: SuperRegIdxSeqs + 0,
149 .LaneMask: LaneBitmask(0x0000000000000001),
150 .AllocationPriority: 0,
151 .GlobalPriority: false,
152 .TSFlags: 0x00, /* TSFlags */
153 .SpillStackID: 0, /* SpillStackID */
154 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
155 .CoveredBySubRegs: false, /* CoveredBySubRegs */
156 .SuperClasses: nullptr, .SuperClassesSize: 0,
157 .OrderFunc: nullptr
158 };
159
160 extern const TargetRegisterClass B32_and_SpecialRegsRegClass = {
161 .MC: &NVPTXMCRegisterClasses[B32_and_SpecialRegsRegClassID],
162 .SubClassMask: B32_and_SpecialRegsSubClassMask,
163 .SuperRegIndices: SuperRegIdxSeqs + 0,
164 .LaneMask: LaneBitmask(0x0000000000000001),
165 .AllocationPriority: 0,
166 .GlobalPriority: false,
167 .TSFlags: 0x00, /* TSFlags */
168 .SpillStackID: 0, /* SpillStackID */
169 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
170 .CoveredBySubRegs: false, /* CoveredBySubRegs */
171 .SuperClasses: B32_and_SpecialRegsSuperclasses, .SuperClassesSize: 2,
172 .OrderFunc: nullptr
173 };
174
175 extern const TargetRegisterClass B64RegClass = {
176 .MC: &NVPTXMCRegisterClasses[B64RegClassID],
177 .SubClassMask: B64SubClassMask,
178 .SuperRegIndices: SuperRegIdxSeqs + 0,
179 .LaneMask: LaneBitmask(0x0000000000000001),
180 .AllocationPriority: 0,
181 .GlobalPriority: false,
182 .TSFlags: 0x00, /* TSFlags */
183 .SpillStackID: 0, /* SpillStackID */
184 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
185 .CoveredBySubRegs: false, /* CoveredBySubRegs */
186 .SuperClasses: nullptr, .SuperClassesSize: 0,
187 .OrderFunc: nullptr
188 };
189
190 extern const TargetRegisterClass B128RegClass = {
191 .MC: &NVPTXMCRegisterClasses[B128RegClassID],
192 .SubClassMask: B128SubClassMask,
193 .SuperRegIndices: SuperRegIdxSeqs + 0,
194 .LaneMask: LaneBitmask(0x0000000000000001),
195 .AllocationPriority: 0,
196 .GlobalPriority: false,
197 .TSFlags: 0x00, /* TSFlags */
198 .SpillStackID: 0, /* SpillStackID */
199 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
200 .CoveredBySubRegs: false, /* CoveredBySubRegs */
201 .SuperClasses: nullptr, .SuperClassesSize: 0,
202 .OrderFunc: nullptr
203 };
204
205
206} // namespace NVPTX
207static const TargetRegisterClass *const NVPTXRegisterClasses[] = {
208 &NVPTX::B1RegClass,
209 &NVPTX::B16RegClass,
210 &NVPTX::SpecialRegsRegClass,
211 &NVPTX::B32RegClass,
212 &NVPTX::B32_and_SpecialRegsRegClass,
213 &NVPTX::B64RegClass,
214 &NVPTX::B128RegClass,
215 };
216
217static const uint8_t NVPTXCostPerUseTable[] = {
2180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
219
220
221static const bool NVPTXInAllocatableClassTable[] = {
222false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
223
224
225static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
226.CostPerUse: NVPTXCostPerUseTable, .NumCosts: 1, .InAllocatableClass: NVPTXInAllocatableClassTable};
227
228/// Get the weight in units of pressure for this register class.
229const RegClassWeight &NVPTXGenRegisterInfo::
230getRegClassWeight(const TargetRegisterClass *RC) const {
231 static const RegClassWeight RCWeightTable[] = {
232 {.RegWeight: 1, .WeightLimit: 5}, // B1
233 {.RegWeight: 1, .WeightLimit: 5}, // B16
234 {.RegWeight: 1, .WeightLimit: 35}, // SpecialRegs
235 {.RegWeight: 1, .WeightLimit: 7}, // B32
236 {.RegWeight: 1, .WeightLimit: 2}, // B32_and_SpecialRegs
237 {.RegWeight: 1, .WeightLimit: 7}, // B64
238 {.RegWeight: 1, .WeightLimit: 5}, // B128
239 };
240 return RCWeightTable[RC->getID()];
241}
242
243/// Get the weight in units of pressure for this register unit.
244unsigned NVPTXGenRegisterInfo::
245getRegUnitWeight(MCRegUnit RegUnit) const {
246 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
247 // All register units have unit weight.
248 return 1;
249}
250
251
252// Get the number of dimensions of register pressure.
253unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
254 return 8;
255}
256
257// Get the name of this register unit pressure set.
258const char *NVPTXGenRegisterInfo::
259getRegPressureSetName(unsigned Idx) const {
260 static const char *PressureNameTable[] = {
261 "B32_and_SpecialRegs",
262 "B1",
263 "B16",
264 "B128",
265 "B32",
266 "B64",
267 "SpecialRegs",
268 "SpecialRegs_with_B32",
269 };
270 return PressureNameTable[Idx];
271}
272
273// Get the register unit pressure limit for this dimension.
274// This limit must be adjusted dynamically for reserved registers.
275unsigned NVPTXGenRegisterInfo::
276getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
277 static const uint8_t PressureLimitTable[] = {
278 2, // 0: B32_and_SpecialRegs
279 5, // 1: B1
280 5, // 2: B16
281 5, // 3: B128
282 7, // 4: B32
283 7, // 5: B64
284 35, // 6: SpecialRegs
285 40, // 7: SpecialRegs_with_B32
286 };
287 return PressureLimitTable[Idx];
288}
289
290/// Table of pressure sets per register class or unit.
291static const int RCSetsTable[] = {
292 /* 0 */ 1, -1,
293 /* 2 */ 2, -1,
294 /* 4 */ 3, -1,
295 /* 6 */ 5, -1,
296 /* 8 */ 4, 7, -1,
297 /* 11 */ 0, 4, 6, 7, -1,
298};
299
300/// Get the dimensions of register pressure impacted by this register class.
301/// Returns a -1 terminated array of pressure set IDs
302const int *NVPTXGenRegisterInfo::
303getRegClassPressureSets(const TargetRegisterClass *RC) const {
304 static const uint8_t RCSetStartTable[] = {
305 0,2,13,8,11,6,4,};
306 return &RCSetsTable[RCSetStartTable[RC->getID()]];
307}
308
309/// Get the dimensions of register pressure impacted by this register unit.
310/// Returns a -1 terminated array of pressure set IDs
311const int *NVPTXGenRegisterInfo::
312getRegUnitPressureSets(MCRegUnit RegUnit) const {
313 assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
314 static const uint8_t RUSetStartTable[] = {
315 13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,0,0,0,0,0,8,8,8,8,8,6,6,6,6,6,4,4,4,4,4,2,2,2,2,2,11,6,11,6,};
316 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
317}
318
319
320// Register to minimal register class mapping
321
322const TargetRegisterClass *NVPTXGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
323 static const uint16_t InvalidRegClassID = UINT16_MAX;
324
325 static const uint16_t Mapping[63] = {
326 InvalidRegClassID, // NoRegister
327 NVPTX::SpecialRegsRegClassID, // VRDepot
328 NVPTX::SpecialRegsRegClassID, // ENVREG0
329 NVPTX::SpecialRegsRegClassID, // ENVREG1
330 NVPTX::SpecialRegsRegClassID, // ENVREG2
331 NVPTX::SpecialRegsRegClassID, // ENVREG3
332 NVPTX::SpecialRegsRegClassID, // ENVREG4
333 NVPTX::SpecialRegsRegClassID, // ENVREG5
334 NVPTX::SpecialRegsRegClassID, // ENVREG6
335 NVPTX::SpecialRegsRegClassID, // ENVREG7
336 NVPTX::SpecialRegsRegClassID, // ENVREG8
337 NVPTX::SpecialRegsRegClassID, // ENVREG9
338 NVPTX::SpecialRegsRegClassID, // ENVREG10
339 NVPTX::SpecialRegsRegClassID, // ENVREG11
340 NVPTX::SpecialRegsRegClassID, // ENVREG12
341 NVPTX::SpecialRegsRegClassID, // ENVREG13
342 NVPTX::SpecialRegsRegClassID, // ENVREG14
343 NVPTX::SpecialRegsRegClassID, // ENVREG15
344 NVPTX::SpecialRegsRegClassID, // ENVREG16
345 NVPTX::SpecialRegsRegClassID, // ENVREG17
346 NVPTX::SpecialRegsRegClassID, // ENVREG18
347 NVPTX::SpecialRegsRegClassID, // ENVREG19
348 NVPTX::SpecialRegsRegClassID, // ENVREG20
349 NVPTX::SpecialRegsRegClassID, // ENVREG21
350 NVPTX::SpecialRegsRegClassID, // ENVREG22
351 NVPTX::SpecialRegsRegClassID, // ENVREG23
352 NVPTX::SpecialRegsRegClassID, // ENVREG24
353 NVPTX::SpecialRegsRegClassID, // ENVREG25
354 NVPTX::SpecialRegsRegClassID, // ENVREG26
355 NVPTX::SpecialRegsRegClassID, // ENVREG27
356 NVPTX::SpecialRegsRegClassID, // ENVREG28
357 NVPTX::SpecialRegsRegClassID, // ENVREG29
358 NVPTX::SpecialRegsRegClassID, // ENVREG30
359 NVPTX::SpecialRegsRegClassID, // ENVREG31
360 NVPTX::B1RegClassID, // P0
361 NVPTX::B1RegClassID, // P1
362 NVPTX::B1RegClassID, // P2
363 NVPTX::B1RegClassID, // P3
364 NVPTX::B1RegClassID, // P4
365 NVPTX::B32RegClassID, // R0
366 NVPTX::B32RegClassID, // R1
367 NVPTX::B32RegClassID, // R2
368 NVPTX::B32RegClassID, // R3
369 NVPTX::B32RegClassID, // R4
370 NVPTX::B64RegClassID, // RL0
371 NVPTX::B64RegClassID, // RL1
372 NVPTX::B64RegClassID, // RL2
373 NVPTX::B64RegClassID, // RL3
374 NVPTX::B64RegClassID, // RL4
375 NVPTX::B128RegClassID, // RQ0
376 NVPTX::B128RegClassID, // RQ1
377 NVPTX::B128RegClassID, // RQ2
378 NVPTX::B128RegClassID, // RQ3
379 NVPTX::B128RegClassID, // RQ4
380 NVPTX::B16RegClassID, // RS0
381 NVPTX::B16RegClassID, // RS1
382 NVPTX::B16RegClassID, // RS2
383 NVPTX::B16RegClassID, // RS3
384 NVPTX::B16RegClassID, // RS4
385 NVPTX::B32_and_SpecialRegsRegClassID, // VRFrame32
386 NVPTX::B64RegClassID, // VRFrame64
387 NVPTX::B32_and_SpecialRegsRegClassID, // VRFrameLocal32
388 NVPTX::B64RegClassID, // VRFrameLocal64
389 };
390
391 assert(Reg < ArrayRef(Mapping).size());
392 unsigned RCID = Mapping[Reg.id()];
393 if (RCID == InvalidRegClassID)
394 return nullptr;
395 return NVPTXRegisterClasses[RCID];
396}
397extern const MCRegisterDesc NVPTXRegDesc[];
398extern const int16_t NVPTXRegDiffLists[];
399extern const LaneBitmask NVPTXLaneMaskLists[];
400extern const char NVPTXRegStrings[];
401extern const char NVPTXRegClassStrings[];
402extern const MCPhysReg NVPTXRegUnitRoots[][2];
403extern const uint16_t NVPTXSubRegIdxLists[];
404extern const uint16_t NVPTXRegEncodingTable[];
405
406NVPTXGenRegisterInfo::
407NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
408 unsigned PC, unsigned HwMode)
409 : TargetRegisterInfo(&NVPTXRegInfoDesc, NVPTXRegisterClasses,
410 NVPTXSubRegIndexStrings, NVPTXSubRegIndexNameOffsets,
411 NVPTXSubRegIdxRangeTable, NVPTXSubRegIndexLaneMaskTable,
412
413 LaneBitmask(0xFFFFFFFFFFFFFFFF), NVPTXRegClassInfos, NVPTXVTLists, HwMode) {
414 InitMCRegisterInfo(D: NVPTXRegDesc, NR: 63, RA, PC,
415 C: NVPTXMCRegisterClasses, NC: 7, RURoots: NVPTXRegUnitRoots, NRU: 62, DL: NVPTXRegDiffLists,
416 RUMS: NVPTXLaneMaskLists, Strings: NVPTXRegStrings, ClassStrings: NVPTXRegClassStrings, SubIndices: NVPTXSubRegIdxLists, NumIndices: 1,
417 RET: NVPTXRegEncodingTable, RUI: nullptr);
418
419}
420
421
422
423ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
424 return {};
425}
426
427bool NVPTXGenRegisterInfo::
428isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
429 return
430 false;
431}
432
433bool NVPTXGenRegisterInfo::
434isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
435 return
436 false;
437}
438
439bool NVPTXGenRegisterInfo::
440isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
441 return
442 false;
443}
444
445bool NVPTXGenRegisterInfo::
446isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
447 return
448 false;
449}
450
451bool NVPTXGenRegisterInfo::
452isConstantPhysReg(MCRegister PhysReg) const {
453 return
454 false;
455}
456
457ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
458 return {};
459}
460
461const NVPTXFrameLowering *
462NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
463 return static_cast<const NVPTXFrameLowering *>(
464 MF.getSubtarget().getFrameLowering());
465}
466
467
468} // namespace llvm
469