1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: NVPTX.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::NVPTXISD {
14
15enum GenNodeType : unsigned {
16 BFI = ISD::BUILTIN_OP_END,
17 BUILD_VECTOR,
18 CALL,
19 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X,
20 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y,
21 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z,
22 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED,
23 CVT_E2M1X4_F32X4_RS_SF,
24 CVT_E2M3X4_F32X4_RS_SF,
25 CVT_E3M2X4_F32X4_RS_SF,
26 CVT_E4M3X4_F32X4_RS_SF,
27 CVT_E5M2X4_F32X4_RS_SF,
28 DYNAMIC_STACKALLOC,
29 DeclareArrayParam,
30 DeclareScalarParam,
31 FCOPYSIGN,
32 FMAXIMUM3,
33 FMAXNUM3,
34 FMINIMUM3,
35 FMINNUM3,
36 FSHL_CLAMP,
37 FSHR_CLAMP,
38 MUL_WIDE_SIGNED,
39 MUL_WIDE_UNSIGNED,
40 MoveParam,
41 PRMT,
42 ProxyReg,
43 RET_GLUE,
44 SHL_CLAMP,
45 SRL_CLAMP,
46 STACKRESTORE,
47 STACKSAVE,
48 ST_ASYNC_GPU_B8,
49 ST_ASYNC_MBARRIER_B128,
50 ST_ASYNC_MMIO_SYS_B8,
51 ST_ASYNC_SYS_B8,
52 SUB_RN_FTZ_SAT,
53 SUB_RN_SAT,
54 TCGEN05_LD_RED_16x32bx2_X128_F32,
55 TCGEN05_LD_RED_16x32bx2_X128_I32,
56 TCGEN05_LD_RED_16x32bx2_X16_F32,
57 TCGEN05_LD_RED_16x32bx2_X16_I32,
58 TCGEN05_LD_RED_16x32bx2_X2_F32,
59 TCGEN05_LD_RED_16x32bx2_X2_I32,
60 TCGEN05_LD_RED_16x32bx2_X32_F32,
61 TCGEN05_LD_RED_16x32bx2_X32_I32,
62 TCGEN05_LD_RED_16x32bx2_X4_F32,
63 TCGEN05_LD_RED_16x32bx2_X4_I32,
64 TCGEN05_LD_RED_16x32bx2_X64_F32,
65 TCGEN05_LD_RED_16x32bx2_X64_I32,
66 TCGEN05_LD_RED_16x32bx2_X8_F32,
67 TCGEN05_LD_RED_16x32bx2_X8_I32,
68 TCGEN05_LD_RED_32x32b_X128_F32,
69 TCGEN05_LD_RED_32x32b_X128_I32,
70 TCGEN05_LD_RED_32x32b_X16_F32,
71 TCGEN05_LD_RED_32x32b_X16_I32,
72 TCGEN05_LD_RED_32x32b_X2_F32,
73 TCGEN05_LD_RED_32x32b_X2_I32,
74 TCGEN05_LD_RED_32x32b_X32_F32,
75 TCGEN05_LD_RED_32x32b_X32_I32,
76 TCGEN05_LD_RED_32x32b_X4_F32,
77 TCGEN05_LD_RED_32x32b_X4_I32,
78 TCGEN05_LD_RED_32x32b_X64_F32,
79 TCGEN05_LD_RED_32x32b_X64_I32,
80 TCGEN05_LD_RED_32x32b_X8_F32,
81 TCGEN05_LD_RED_32x32b_X8_I32,
82 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1,
83 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B,
84 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2,
85 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B,
86 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
87 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
88 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1,
89 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2,
90 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
91 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
92 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1,
93 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
94 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2,
95 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
96 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
97 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
98 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
99 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
100 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1,
101 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
102 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B,
103 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2,
104 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
105 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B,
106 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
107 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
108 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
109 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
110};
111
112static constexpr unsigned GENERATED_OPCODE_END = TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT + 1;
113
114} // namespace llvm::NVPTXISD
115
116#endif // GET_SDNODE_ENUM
117
118#ifdef GET_SDNODE_DESC
119#undef GET_SDNODE_DESC
120
121namespace llvm {
122
123
124#ifdef __GNUC__
125#pragma GCC diagnostic push
126#pragma GCC diagnostic ignored "-Woverlength-strings"
127#endif
128static constexpr char NVPTXSDNodeNamesStorage[] =
129 "\0"
130 "NVPTXISD::BFI\0"
131 "NVPTXISD::BUILD_VECTOR\0"
132 "NVPTXISD::CALL\0"
133 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X\0"
134 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y\0"
135 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z\0"
136 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED\0"
137 "NVPTXISD::CVT_E2M1X4_F32X4_RS_SF\0"
138 "NVPTXISD::CVT_E2M3X4_F32X4_RS_SF\0"
139 "NVPTXISD::CVT_E3M2X4_F32X4_RS_SF\0"
140 "NVPTXISD::CVT_E4M3X4_F32X4_RS_SF\0"
141 "NVPTXISD::CVT_E5M2X4_F32X4_RS_SF\0"
142 "NVPTXISD::DYNAMIC_STACKALLOC\0"
143 "NVPTXISD::DeclareArrayParam\0"
144 "NVPTXISD::DeclareScalarParam\0"
145 "NVPTXISD::FCOPYSIGN\0"
146 "NVPTXISD::FMAXIMUM3\0"
147 "NVPTXISD::FMAXNUM3\0"
148 "NVPTXISD::FMINIMUM3\0"
149 "NVPTXISD::FMINNUM3\0"
150 "NVPTXISD::FSHL_CLAMP\0"
151 "NVPTXISD::FSHR_CLAMP\0"
152 "NVPTXISD::MUL_WIDE_SIGNED\0"
153 "NVPTXISD::MUL_WIDE_UNSIGNED\0"
154 "NVPTXISD::MoveParam\0"
155 "NVPTXISD::PRMT\0"
156 "NVPTXISD::ProxyReg\0"
157 "NVPTXISD::RET_GLUE\0"
158 "NVPTXISD::SHL_CLAMP\0"
159 "NVPTXISD::SRL_CLAMP\0"
160 "NVPTXISD::STACKRESTORE\0"
161 "NVPTXISD::STACKSAVE\0"
162 "NVPTXISD::ST_ASYNC_GPU_B8\0"
163 "NVPTXISD::ST_ASYNC_MBARRIER_B128\0"
164 "NVPTXISD::ST_ASYNC_MMIO_SYS_B8\0"
165 "NVPTXISD::ST_ASYNC_SYS_B8\0"
166 "NVPTXISD::SUB_RN_FTZ_SAT\0"
167 "NVPTXISD::SUB_RN_SAT\0"
168 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_F32\0"
169 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_I32\0"
170 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_F32\0"
171 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_I32\0"
172 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_F32\0"
173 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_I32\0"
174 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_F32\0"
175 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_I32\0"
176 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_F32\0"
177 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_I32\0"
178 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_F32\0"
179 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_I32\0"
180 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_F32\0"
181 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_I32\0"
182 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_F32\0"
183 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_I32\0"
184 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_F32\0"
185 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_I32\0"
186 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_F32\0"
187 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_I32\0"
188 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_F32\0"
189 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_I32\0"
190 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_F32\0"
191 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_I32\0"
192 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_F32\0"
193 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_I32\0"
194 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_F32\0"
195 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_I32\0"
196 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
197 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B\0"
198 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
199 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B\0"
200 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
201 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
202 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
203 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
204 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
205 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
206 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
207 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
208 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
209 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
210 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
211 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
212 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
213 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
214 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
215 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
216 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B\0"
217 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
218 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
219 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B\0"
220 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
221 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
222 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
223 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
224 ;
225#ifdef __GNUC__
226#pragma GCC diagnostic pop
227#endif
228
229static constexpr llvm::StringTable
230NVPTXSDNodeNames = NVPTXSDNodeNamesStorage;
231
232static const VTByHwModePair NVPTXVTByHwModeTable[] = {
233 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
234};
235
236static const SDTypeConstraint NVPTXSDTypeConstraints[] = {
237 /* 0 */ {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
238 /* 131 */ {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
239 /* 263 */ {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
240 /* 331 */ {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
241 /* 367 */ {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
242 /* 387 */ {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
243 /* 399 */ {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
244 /* 407 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
245 /* 413 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
246 /* 418 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
247 /* 435 */ {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
248 /* 453 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
249 /* 470 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
250 /* 487 */ {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
251 /* 505 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
252 /* 522 */ {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
253 /* 529 */ {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
254 /* 537 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
255 /* 546 */ {SDTCisVT, 9, 0, 0, MVT::i1}, {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
256 /* 556 */ {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i1}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
257 /* 569 */ {SDTCisVT, 13, 0, 0, MVT::i1}, {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
258 /* 583 */ {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i1}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
259 /* 604 */ {SDTCisVT, 21, 0, 0, MVT::i1}, {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
260 /* 626 */ {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i1}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
261 /* 663 */ {SDTCisVT, 37, 0, 0, MVT::i1}, {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
262 /* 701 */ {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i1}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
263 /* 770 */ {SDTCisVT, 69, 0, 0, MVT::i1}, {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
264 /* 840 */ {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i1}, {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
265 /* 973 */ {SDTCisVT, 133, 0, 0, MVT::i1}, {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
266 /* 1107 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
267 /* 1111 */ {SDTCisVT, 2, 0, 0, MVT::i1}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
268 /* 1113 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
269 /* 1118 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
270 /* 1121 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
271 /* 1128 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
272 /* 1135 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
273 /* 1139 */ {SDTCisSameNumEltsAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
274 /* 1144 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
275 /* 1147 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
276 /* 1151 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
277};
278
279static const SDNodeDesc NVPTXSDNodeDescs[] = {
280 {1, 4, 0, 0, 0, 1, 1113, 5}, // BFI
281 {1, 2, 0, 0, 0, 15, 0, 0}, // BUILD_VECTOR
282 {0, 6, 0|1<<SDNPHasChain, 0, 0, 38, 413, 5}, // CALL
283 {1, 2, 0, 0, 0, 53, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X
284 {1, 2, 0, 0, 0, 115, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y
285 {1, 2, 0, 0, 0, 177, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z
286 {1, 2, 0, 0, 0, 239, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED
287 {1, 6, 0, 0, 0, 295, 1121, 7}, // CVT_E2M1X4_F32X4_RS_SF
288 {1, 6, 0, 0, 0, 328, 1128, 7}, // CVT_E2M3X4_F32X4_RS_SF
289 {1, 6, 0, 0, 0, 361, 1128, 7}, // CVT_E3M2X4_F32X4_RS_SF
290 {1, 6, 0, 0, 0, 394, 1128, 7}, // CVT_E4M3X4_F32X4_RS_SF
291 {1, 6, 0, 0, 0, 427, 1128, 7}, // CVT_E5M2X4_F32X4_RS_SF
292 {1, 2, 0|1<<SDNPHasChain, 0, 0, 460, 1151, 3}, // DYNAMIC_STACKALLOC
293 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 489, 128, 3}, // DeclareArrayParam
294 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 517, 129, 2}, // DeclareScalarParam
295 {1, 2, 0, 0, 0, 546, 1144, 3}, // FCOPYSIGN
296 {1, 3, 0, 0, 0, 566, 1147, 4}, // FMAXIMUM3
297 {1, 3, 0, 0, 0, 586, 1147, 4}, // FMAXNUM3
298 {1, 3, 0, 0, 0, 605, 1147, 4}, // FMINIMUM3
299 {1, 3, 0, 0, 0, 625, 1147, 4}, // FMINNUM3
300 {1, 3, 0, 0, 0, 644, 1139, 5}, // FSHL_CLAMP
301 {1, 3, 0, 0, 0, 665, 1139, 5}, // FSHR_CLAMP
302 {1, 2, 0, 0, 0, 686, 1118, 3}, // MUL_WIDE_SIGNED
303 {1, 2, 0, 0, 0, 712, 1118, 3}, // MUL_WIDE_UNSIGNED
304 {1, 1, 0, 0, 0, 740, 1116, 2}, // MoveParam
305 {1, 4, 0, 0, 0, 760, 126, 5}, // PRMT
306 {1, 1, 0|1<<SDNPHasChain, 0, 0, 775, 1138, 1}, // ProxyReg
307 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 794, 0, 0}, // RET_GLUE
308 {1, 2, 0, 0, 0, 813, 1135, 4}, // SHL_CLAMP
309 {1, 2, 0, 0, 0, 833, 1135, 4}, // SRL_CLAMP
310 {0, 1, 0|1<<SDNPHasChain, 0, 0, 853, 1117, 1}, // STACKRESTORE
311 {1, 0, 0|1<<SDNPHasChain, 0, 0, 876, 1117, 1}, // STACKSAVE
312 {0, 3, 0|1<<SDNPHasChain, 0, 0, 896, 1111, 2}, // ST_ASYNC_GPU_B8
313 {0, 4, 0|1<<SDNPHasChain, 0, 0, 922, 1107, 4}, // ST_ASYNC_MBARRIER_B128
314 {0, 2, 0|1<<SDNPHasChain, 0, 0, 955, 1110, 1}, // ST_ASYNC_MMIO_SYS_B8
315 {0, 3, 0|1<<SDNPHasChain, 0, 0, 986, 1111, 2}, // ST_ASYNC_SYS_B8
316 {1, 2, 0, 0, 0, 1012, 1144, 3}, // SUB_RN_FTZ_SAT
317 {1, 2, 0, 0, 0, 1037, 1144, 3}, // SUB_RN_SAT
318 {129, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1058, 973, 134}, // TCGEN05_LD_RED_16x32bx2_X128_F32
319 {129, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1101, 131, 132}, // TCGEN05_LD_RED_16x32bx2_X128_I32
320 {17, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1144, 604, 22}, // TCGEN05_LD_RED_16x32bx2_X16_F32
321 {17, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1186, 367, 20}, // TCGEN05_LD_RED_16x32bx2_X16_I32
322 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1228, 529, 8}, // TCGEN05_LD_RED_16x32bx2_X2_F32
323 {3, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1269, 407, 6}, // TCGEN05_LD_RED_16x32bx2_X2_I32
324 {33, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1310, 663, 38}, // TCGEN05_LD_RED_16x32bx2_X32_F32
325 {33, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1352, 331, 36}, // TCGEN05_LD_RED_16x32bx2_X32_I32
326 {5, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1394, 546, 10}, // TCGEN05_LD_RED_16x32bx2_X4_F32
327 {5, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1435, 399, 8}, // TCGEN05_LD_RED_16x32bx2_X4_I32
328 {65, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1476, 770, 70}, // TCGEN05_LD_RED_16x32bx2_X64_F32
329 {65, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1518, 263, 68}, // TCGEN05_LD_RED_16x32bx2_X64_I32
330 {9, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1560, 569, 14}, // TCGEN05_LD_RED_16x32bx2_X8_F32
331 {9, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1601, 387, 12}, // TCGEN05_LD_RED_16x32bx2_X8_I32
332 {129, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1642, 840, 133}, // TCGEN05_LD_RED_32x32b_X128_F32
333 {129, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1683, 0, 131}, // TCGEN05_LD_RED_32x32b_X128_I32
334 {17, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1724, 583, 21}, // TCGEN05_LD_RED_32x32b_X16_F32
335 {17, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1764, 112, 19}, // TCGEN05_LD_RED_32x32b_X16_I32
336 {3, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1804, 522, 7}, // TCGEN05_LD_RED_32x32b_X2_F32
337 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1843, 126, 5}, // TCGEN05_LD_RED_32x32b_X2_I32
338 {33, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1882, 626, 37}, // TCGEN05_LD_RED_32x32b_X32_F32
339 {33, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1922, 96, 35}, // TCGEN05_LD_RED_32x32b_X32_I32
340 {5, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1962, 537, 9}, // TCGEN05_LD_RED_32x32b_X4_F32
341 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2001, 124, 7}, // TCGEN05_LD_RED_32x32b_X4_I32
342 {65, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2040, 701, 69}, // TCGEN05_LD_RED_32x32b_X64_F32
343 {65, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2080, 64, 67}, // TCGEN05_LD_RED_32x32b_X64_I32
344 {9, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2120, 556, 13}, // TCGEN05_LD_RED_32x32b_X8_F32
345 {9, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2159, 120, 11}, // TCGEN05_LD_RED_32x32b_X8_I32
346 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2198, 475, 12}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1
347 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2251, 475, 12}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B
348 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2317, 471, 16}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2
349 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2370, 471, 16}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B
350 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2436, 509, 13}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
351 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2497, 505, 17}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
352 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2558, 474, 13}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1
353 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2614, 470, 17}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2
354 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2670, 491, 14}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
355 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2734, 487, 18}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
356 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2798, 422, 13}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1
357 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2854, 422, 13}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
358 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2917, 418, 17}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2
359 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2973, 418, 17}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
360 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3036, 439, 14}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
361 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3100, 439, 14}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
362 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3171, 435, 18}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
363 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3235, 435, 18}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
364 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3306, 423, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1
365 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3359, 423, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
366 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3419, 423, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B
367 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3485, 419, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2
368 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3538, 419, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
369 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3598, 419, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B
370 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3664, 457, 13}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
371 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3725, 457, 13}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
372 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3793, 453, 17}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
373 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3854, 453, 17}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
374};
375
376static const SDNodeInfo NVPTXGenSDNodeInfo(
377 /*NumOpcodes=*/94, NVPTXSDNodeDescs, NVPTXSDNodeNames,
378 NVPTXVTByHwModeTable, NVPTXSDTypeConstraints);
379
380} // namespace llvm
381
382#endif // GET_SDNODE_DESC
383
384