1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: NVPTX.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::NVPTXISD {
14
15enum GenNodeType : unsigned {
16 BFI = ISD::BUILTIN_OP_END,
17 BUILD_VECTOR,
18 CALL,
19 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X,
20 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y,
21 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z,
22 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED,
23 CVT_E2M1X4_F32X4_RS_SF,
24 CVT_E2M3X4_F32X4_RS_SF,
25 CVT_E3M2X4_F32X4_RS_SF,
26 CVT_E4M3X4_F32X4_RS_SF,
27 CVT_E5M2X4_F32X4_RS_SF,
28 DYNAMIC_STACKALLOC,
29 DeclareArrayParam,
30 DeclareScalarParam,
31 FCOPYSIGN,
32 FMAXIMUM3,
33 FMAXNUM3,
34 FMINIMUM3,
35 FMINNUM3,
36 FSHL_CLAMP,
37 FSHR_CLAMP,
38 MUL_WIDE_SIGNED,
39 MUL_WIDE_UNSIGNED,
40 MoveParam,
41 PRMT,
42 ProxyReg,
43 RET_GLUE,
44 SHL_CLAMP,
45 SRL_CLAMP,
46 STACKRESTORE,
47 STACKSAVE,
48 ST_ASYNC_GPU_B8,
49 ST_ASYNC_MBARRIER_B128,
50 ST_ASYNC_MMIO_SYS_B8,
51 ST_ASYNC_SYS_B8,
52 SUB_RM,
53 SUB_RM_FTZ,
54 SUB_RN,
55 SUB_RN_FTZ,
56 SUB_RN_FTZ_SAT,
57 SUB_RN_SAT,
58 SUB_RP,
59 SUB_RP_FTZ,
60 SUB_RZ,
61 SUB_RZ_FTZ,
62 Symbol,
63 TCGEN05_LD_RED_16x32bx2_X128_F32,
64 TCGEN05_LD_RED_16x32bx2_X128_I32,
65 TCGEN05_LD_RED_16x32bx2_X16_F32,
66 TCGEN05_LD_RED_16x32bx2_X16_I32,
67 TCGEN05_LD_RED_16x32bx2_X2_F32,
68 TCGEN05_LD_RED_16x32bx2_X2_I32,
69 TCGEN05_LD_RED_16x32bx2_X32_F32,
70 TCGEN05_LD_RED_16x32bx2_X32_I32,
71 TCGEN05_LD_RED_16x32bx2_X4_F32,
72 TCGEN05_LD_RED_16x32bx2_X4_I32,
73 TCGEN05_LD_RED_16x32bx2_X64_F32,
74 TCGEN05_LD_RED_16x32bx2_X64_I32,
75 TCGEN05_LD_RED_16x32bx2_X8_F32,
76 TCGEN05_LD_RED_16x32bx2_X8_I32,
77 TCGEN05_LD_RED_32x32b_X128_F32,
78 TCGEN05_LD_RED_32x32b_X128_I32,
79 TCGEN05_LD_RED_32x32b_X16_F32,
80 TCGEN05_LD_RED_32x32b_X16_I32,
81 TCGEN05_LD_RED_32x32b_X2_F32,
82 TCGEN05_LD_RED_32x32b_X2_I32,
83 TCGEN05_LD_RED_32x32b_X32_F32,
84 TCGEN05_LD_RED_32x32b_X32_I32,
85 TCGEN05_LD_RED_32x32b_X4_F32,
86 TCGEN05_LD_RED_32x32b_X4_I32,
87 TCGEN05_LD_RED_32x32b_X64_F32,
88 TCGEN05_LD_RED_32x32b_X64_I32,
89 TCGEN05_LD_RED_32x32b_X8_F32,
90 TCGEN05_LD_RED_32x32b_X8_I32,
91 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1,
92 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B,
93 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2,
94 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B,
95 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
96 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
97 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1,
98 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2,
99 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
100 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
101 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1,
102 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
103 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2,
104 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
105 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
106 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
107 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
108 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
109 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1,
110 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
111 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B,
112 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2,
113 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
114 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B,
115 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
116 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
117 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
118 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
119};
120
121static constexpr unsigned GENERATED_OPCODE_END = TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT + 1;
122
123} // namespace llvm::NVPTXISD
124
125#endif // GET_SDNODE_ENUM
126
127#ifdef GET_SDNODE_DESC
128#undef GET_SDNODE_DESC
129
130namespace llvm {
131
132
133#ifdef __GNUC__
134#pragma GCC diagnostic push
135#pragma GCC diagnostic ignored "-Woverlength-strings"
136#endif
137static constexpr char NVPTXSDNodeNamesStorage[] =
138 "\0"
139 "NVPTXISD::BFI\0"
140 "NVPTXISD::BUILD_VECTOR\0"
141 "NVPTXISD::CALL\0"
142 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X\0"
143 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y\0"
144 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z\0"
145 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED\0"
146 "NVPTXISD::CVT_E2M1X4_F32X4_RS_SF\0"
147 "NVPTXISD::CVT_E2M3X4_F32X4_RS_SF\0"
148 "NVPTXISD::CVT_E3M2X4_F32X4_RS_SF\0"
149 "NVPTXISD::CVT_E4M3X4_F32X4_RS_SF\0"
150 "NVPTXISD::CVT_E5M2X4_F32X4_RS_SF\0"
151 "NVPTXISD::DYNAMIC_STACKALLOC\0"
152 "NVPTXISD::DeclareArrayParam\0"
153 "NVPTXISD::DeclareScalarParam\0"
154 "NVPTXISD::FCOPYSIGN\0"
155 "NVPTXISD::FMAXIMUM3\0"
156 "NVPTXISD::FMAXNUM3\0"
157 "NVPTXISD::FMINIMUM3\0"
158 "NVPTXISD::FMINNUM3\0"
159 "NVPTXISD::FSHL_CLAMP\0"
160 "NVPTXISD::FSHR_CLAMP\0"
161 "NVPTXISD::MUL_WIDE_SIGNED\0"
162 "NVPTXISD::MUL_WIDE_UNSIGNED\0"
163 "NVPTXISD::MoveParam\0"
164 "NVPTXISD::PRMT\0"
165 "NVPTXISD::ProxyReg\0"
166 "NVPTXISD::RET_GLUE\0"
167 "NVPTXISD::SHL_CLAMP\0"
168 "NVPTXISD::SRL_CLAMP\0"
169 "NVPTXISD::STACKRESTORE\0"
170 "NVPTXISD::STACKSAVE\0"
171 "NVPTXISD::ST_ASYNC_GPU_B8\0"
172 "NVPTXISD::ST_ASYNC_MBARRIER_B128\0"
173 "NVPTXISD::ST_ASYNC_MMIO_SYS_B8\0"
174 "NVPTXISD::ST_ASYNC_SYS_B8\0"
175 "NVPTXISD::SUB_RM\0"
176 "NVPTXISD::SUB_RM_FTZ\0"
177 "NVPTXISD::SUB_RN\0"
178 "NVPTXISD::SUB_RN_FTZ\0"
179 "NVPTXISD::SUB_RN_FTZ_SAT\0"
180 "NVPTXISD::SUB_RN_SAT\0"
181 "NVPTXISD::SUB_RP\0"
182 "NVPTXISD::SUB_RP_FTZ\0"
183 "NVPTXISD::SUB_RZ\0"
184 "NVPTXISD::SUB_RZ_FTZ\0"
185 "NVPTXISD::Symbol\0"
186 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_F32\0"
187 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_I32\0"
188 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_F32\0"
189 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_I32\0"
190 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_F32\0"
191 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_I32\0"
192 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_F32\0"
193 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_I32\0"
194 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_F32\0"
195 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_I32\0"
196 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_F32\0"
197 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_I32\0"
198 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_F32\0"
199 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_I32\0"
200 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_F32\0"
201 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_I32\0"
202 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_F32\0"
203 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_I32\0"
204 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_F32\0"
205 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_I32\0"
206 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_F32\0"
207 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_I32\0"
208 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_F32\0"
209 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_I32\0"
210 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_F32\0"
211 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_I32\0"
212 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_F32\0"
213 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_I32\0"
214 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
215 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B\0"
216 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
217 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B\0"
218 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
219 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
220 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
221 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
222 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
223 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
224 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
225 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
226 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
227 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
228 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
229 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
230 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
231 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
232 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
233 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
234 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B\0"
235 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
236 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
237 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B\0"
238 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
239 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
240 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
241 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
242 ;
243#ifdef __GNUC__
244#pragma GCC diagnostic pop
245#endif
246
247static constexpr llvm::StringTable
248NVPTXSDNodeNames = NVPTXSDNodeNamesStorage;
249
250static const VTByHwModePair NVPTXVTByHwModeTable[] = {
251 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
252};
253
254static const SDTypeConstraint NVPTXSDTypeConstraints[] = {
255 /* 0 */ {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
256 /* 131 */ {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
257 /* 263 */ {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
258 /* 331 */ {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
259 /* 367 */ {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
260 /* 387 */ {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
261 /* 399 */ {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
262 /* 407 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
263 /* 413 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
264 /* 418 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
265 /* 435 */ {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
266 /* 453 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
267 /* 470 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
268 /* 487 */ {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
269 /* 505 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
270 /* 522 */ {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
271 /* 529 */ {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
272 /* 537 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
273 /* 546 */ {SDTCisVT, 9, 0, 0, MVT::i1}, {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
274 /* 556 */ {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i1}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
275 /* 569 */ {SDTCisVT, 13, 0, 0, MVT::i1}, {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
276 /* 583 */ {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i1}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
277 /* 604 */ {SDTCisVT, 21, 0, 0, MVT::i1}, {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
278 /* 626 */ {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i1}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
279 /* 663 */ {SDTCisVT, 37, 0, 0, MVT::i1}, {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
280 /* 701 */ {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i1}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
281 /* 770 */ {SDTCisVT, 69, 0, 0, MVT::i1}, {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
282 /* 840 */ {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i1}, {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
283 /* 973 */ {SDTCisVT, 133, 0, 0, MVT::i1}, {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
284 /* 1107 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
285 /* 1111 */ {SDTCisVT, 2, 0, 0, MVT::i1}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
286 /* 1113 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
287 /* 1118 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
288 /* 1121 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
289 /* 1128 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
290 /* 1135 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
291 /* 1139 */ {SDTCisSameNumEltsAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
292 /* 1144 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
293 /* 1147 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
294 /* 1151 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
295};
296
297static const SDNodeDesc NVPTXSDNodeDescs[] = {
298 {1, 4, 0, 0, 0, 1, 1113, 5}, // BFI
299 {1, 2, 0, 0, 0, 15, 0, 0}, // BUILD_VECTOR
300 {0, 6, 0|1<<SDNPHasChain, 0, 0, 38, 413, 5}, // CALL
301 {1, 2, 0, 0, 0, 53, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X
302 {1, 2, 0, 0, 0, 115, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y
303 {1, 2, 0, 0, 0, 177, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z
304 {1, 2, 0, 0, 0, 239, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED
305 {1, 6, 0, 0, 0, 295, 1121, 7}, // CVT_E2M1X4_F32X4_RS_SF
306 {1, 6, 0, 0, 0, 328, 1128, 7}, // CVT_E2M3X4_F32X4_RS_SF
307 {1, 6, 0, 0, 0, 361, 1128, 7}, // CVT_E3M2X4_F32X4_RS_SF
308 {1, 6, 0, 0, 0, 394, 1128, 7}, // CVT_E4M3X4_F32X4_RS_SF
309 {1, 6, 0, 0, 0, 427, 1128, 7}, // CVT_E5M2X4_F32X4_RS_SF
310 {1, 2, 0|1<<SDNPHasChain, 0, 0, 460, 1151, 3}, // DYNAMIC_STACKALLOC
311 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 489, 128, 3}, // DeclareArrayParam
312 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 517, 129, 2}, // DeclareScalarParam
313 {1, 2, 0, 0, 0, 546, 1144, 3}, // FCOPYSIGN
314 {1, 3, 0, 0, 0, 566, 1147, 4}, // FMAXIMUM3
315 {1, 3, 0, 0, 0, 586, 1147, 4}, // FMAXNUM3
316 {1, 3, 0, 0, 0, 605, 1147, 4}, // FMINIMUM3
317 {1, 3, 0, 0, 0, 625, 1147, 4}, // FMINNUM3
318 {1, 3, 0, 0, 0, 644, 1139, 5}, // FSHL_CLAMP
319 {1, 3, 0, 0, 0, 665, 1139, 5}, // FSHR_CLAMP
320 {1, 2, 0, 0, 0, 686, 1118, 3}, // MUL_WIDE_SIGNED
321 {1, 2, 0, 0, 0, 712, 1118, 3}, // MUL_WIDE_UNSIGNED
322 {1, 1, 0, 0, 0, 740, 1116, 2}, // MoveParam
323 {1, 4, 0, 0, 0, 760, 126, 5}, // PRMT
324 {1, 1, 0|1<<SDNPHasChain, 0, 0, 775, 1138, 1}, // ProxyReg
325 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 794, 0, 0}, // RET_GLUE
326 {1, 2, 0, 0, 0, 813, 1135, 4}, // SHL_CLAMP
327 {1, 2, 0, 0, 0, 833, 1135, 4}, // SRL_CLAMP
328 {0, 1, 0|1<<SDNPHasChain, 0, 0, 853, 1117, 1}, // STACKRESTORE
329 {1, 0, 0|1<<SDNPHasChain, 0, 0, 876, 1117, 1}, // STACKSAVE
330 {0, 3, 0|1<<SDNPHasChain, 0, 0, 896, 1111, 2}, // ST_ASYNC_GPU_B8
331 {0, 4, 0|1<<SDNPHasChain, 0, 0, 922, 1107, 4}, // ST_ASYNC_MBARRIER_B128
332 {0, 2, 0|1<<SDNPHasChain, 0, 0, 955, 1110, 1}, // ST_ASYNC_MMIO_SYS_B8
333 {0, 3, 0|1<<SDNPHasChain, 0, 0, 986, 1111, 2}, // ST_ASYNC_SYS_B8
334 {1, 2, 0, 0, 0, 1012, 1144, 3}, // SUB_RM
335 {1, 2, 0, 0, 0, 1029, 1144, 3}, // SUB_RM_FTZ
336 {1, 2, 0, 0, 0, 1050, 1144, 3}, // SUB_RN
337 {1, 2, 0, 0, 0, 1067, 1144, 3}, // SUB_RN_FTZ
338 {1, 2, 0, 0, 0, 1088, 1144, 3}, // SUB_RN_FTZ_SAT
339 {1, 2, 0, 0, 0, 1113, 1144, 3}, // SUB_RN_SAT
340 {1, 2, 0, 0, 0, 1134, 1144, 3}, // SUB_RP
341 {1, 2, 0, 0, 0, 1151, 1144, 3}, // SUB_RP_FTZ
342 {1, 2, 0, 0, 0, 1172, 1144, 3}, // SUB_RZ
343 {1, 2, 0, 0, 0, 1189, 1144, 3}, // SUB_RZ_FTZ
344 {1, 1, 0, 0, 0, 1210, 1116, 2}, // Symbol
345 {129, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1227, 973, 134}, // TCGEN05_LD_RED_16x32bx2_X128_F32
346 {129, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1270, 131, 132}, // TCGEN05_LD_RED_16x32bx2_X128_I32
347 {17, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1313, 604, 22}, // TCGEN05_LD_RED_16x32bx2_X16_F32
348 {17, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1355, 367, 20}, // TCGEN05_LD_RED_16x32bx2_X16_I32
349 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1397, 529, 8}, // TCGEN05_LD_RED_16x32bx2_X2_F32
350 {3, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1438, 407, 6}, // TCGEN05_LD_RED_16x32bx2_X2_I32
351 {33, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1479, 663, 38}, // TCGEN05_LD_RED_16x32bx2_X32_F32
352 {33, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1521, 331, 36}, // TCGEN05_LD_RED_16x32bx2_X32_I32
353 {5, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1563, 546, 10}, // TCGEN05_LD_RED_16x32bx2_X4_F32
354 {5, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1604, 399, 8}, // TCGEN05_LD_RED_16x32bx2_X4_I32
355 {65, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1645, 770, 70}, // TCGEN05_LD_RED_16x32bx2_X64_F32
356 {65, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1687, 263, 68}, // TCGEN05_LD_RED_16x32bx2_X64_I32
357 {9, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1729, 569, 14}, // TCGEN05_LD_RED_16x32bx2_X8_F32
358 {9, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1770, 387, 12}, // TCGEN05_LD_RED_16x32bx2_X8_I32
359 {129, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1811, 840, 133}, // TCGEN05_LD_RED_32x32b_X128_F32
360 {129, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1852, 0, 131}, // TCGEN05_LD_RED_32x32b_X128_I32
361 {17, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1893, 583, 21}, // TCGEN05_LD_RED_32x32b_X16_F32
362 {17, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1933, 112, 19}, // TCGEN05_LD_RED_32x32b_X16_I32
363 {3, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1973, 522, 7}, // TCGEN05_LD_RED_32x32b_X2_F32
364 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2012, 126, 5}, // TCGEN05_LD_RED_32x32b_X2_I32
365 {33, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2051, 626, 37}, // TCGEN05_LD_RED_32x32b_X32_F32
366 {33, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2091, 96, 35}, // TCGEN05_LD_RED_32x32b_X32_I32
367 {5, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2131, 537, 9}, // TCGEN05_LD_RED_32x32b_X4_F32
368 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2170, 124, 7}, // TCGEN05_LD_RED_32x32b_X4_I32
369 {65, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2209, 701, 69}, // TCGEN05_LD_RED_32x32b_X64_F32
370 {65, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2249, 64, 67}, // TCGEN05_LD_RED_32x32b_X64_I32
371 {9, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2289, 556, 13}, // TCGEN05_LD_RED_32x32b_X8_F32
372 {9, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2328, 120, 11}, // TCGEN05_LD_RED_32x32b_X8_I32
373 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2367, 475, 12}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1
374 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2420, 475, 12}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B
375 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2486, 471, 16}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2
376 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2539, 471, 16}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B
377 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2605, 509, 13}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
378 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2666, 505, 17}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
379 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2727, 474, 13}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1
380 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2783, 470, 17}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2
381 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2839, 491, 14}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
382 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2903, 487, 18}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
383 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2967, 422, 13}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1
384 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3023, 422, 13}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
385 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3086, 418, 17}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2
386 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3142, 418, 17}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
387 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3205, 439, 14}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
388 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3269, 439, 14}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
389 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3340, 435, 18}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
390 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3404, 435, 18}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
391 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3475, 423, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1
392 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3528, 423, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
393 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3588, 423, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B
394 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3654, 419, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2
395 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3707, 419, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
396 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3767, 419, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B
397 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3833, 457, 13}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
398 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3894, 457, 13}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
399 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3962, 453, 17}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
400 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4023, 453, 17}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
401};
402
403static const SDNodeInfo NVPTXGenSDNodeInfo(
404 /*NumOpcodes=*/103, NVPTXSDNodeDescs, NVPTXSDNodeNames,
405 NVPTXVTByHwModeTable, NVPTXSDTypeConstraints);
406
407} // namespace llvm
408
409#endif // GET_SDNODE_DESC
410
411