1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: NVPTX.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::NVPTXISD {
14
15enum GenNodeType : unsigned {
16 BFI = ISD::BUILTIN_OP_END,
17 BUILD_VECTOR,
18 CALL,
19 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X,
20 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y,
21 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z,
22 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED,
23 CVT_E2M1X4_F32X4_RS_SF,
24 CVT_E2M3X4_F32X4_RS_SF,
25 CVT_E3M2X4_F32X4_RS_SF,
26 CVT_E4M3X4_F32X4_RS_SF,
27 CVT_E5M2X4_F32X4_RS_SF,
28 CallPrototype,
29 DYNAMIC_STACKALLOC,
30 DeclareArrayParam,
31 DeclareScalarParam,
32 FCOPYSIGN,
33 FMAXIMUM3,
34 FMAXNUM3,
35 FMINIMUM3,
36 FMINNUM3,
37 FSHL_CLAMP,
38 FSHR_CLAMP,
39 MUL_WIDE_SIGNED,
40 MUL_WIDE_UNSIGNED,
41 MoveParam,
42 PRMT,
43 ProxyReg,
44 RET_GLUE,
45 SHL_CLAMP,
46 SRL_CLAMP,
47 STACKRESTORE,
48 STACKSAVE,
49 SUB_RN_FTZ_SAT,
50 SUB_RN_SAT,
51 TCGEN05_LD_RED_16x32bx2_X128_F32,
52 TCGEN05_LD_RED_16x32bx2_X128_I32,
53 TCGEN05_LD_RED_16x32bx2_X16_F32,
54 TCGEN05_LD_RED_16x32bx2_X16_I32,
55 TCGEN05_LD_RED_16x32bx2_X2_F32,
56 TCGEN05_LD_RED_16x32bx2_X2_I32,
57 TCGEN05_LD_RED_16x32bx2_X32_F32,
58 TCGEN05_LD_RED_16x32bx2_X32_I32,
59 TCGEN05_LD_RED_16x32bx2_X4_F32,
60 TCGEN05_LD_RED_16x32bx2_X4_I32,
61 TCGEN05_LD_RED_16x32bx2_X64_F32,
62 TCGEN05_LD_RED_16x32bx2_X64_I32,
63 TCGEN05_LD_RED_16x32bx2_X8_F32,
64 TCGEN05_LD_RED_16x32bx2_X8_I32,
65 TCGEN05_LD_RED_32x32b_X128_F32,
66 TCGEN05_LD_RED_32x32b_X128_I32,
67 TCGEN05_LD_RED_32x32b_X16_F32,
68 TCGEN05_LD_RED_32x32b_X16_I32,
69 TCGEN05_LD_RED_32x32b_X2_F32,
70 TCGEN05_LD_RED_32x32b_X2_I32,
71 TCGEN05_LD_RED_32x32b_X32_F32,
72 TCGEN05_LD_RED_32x32b_X32_I32,
73 TCGEN05_LD_RED_32x32b_X4_F32,
74 TCGEN05_LD_RED_32x32b_X4_I32,
75 TCGEN05_LD_RED_32x32b_X64_F32,
76 TCGEN05_LD_RED_32x32b_X64_I32,
77 TCGEN05_LD_RED_32x32b_X8_F32,
78 TCGEN05_LD_RED_32x32b_X8_I32,
79 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1,
80 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2,
81 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
82 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
83 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1,
84 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2,
85 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
86 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
87 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1,
88 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
89 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2,
90 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
91 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
92 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
93 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
94 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
95 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1,
96 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
97 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2,
98 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
99 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
100 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
101 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
102 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
103};
104
105static constexpr unsigned GENERATED_OPCODE_END = TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT + 1;
106
107} // namespace llvm::NVPTXISD
108
109#endif // GET_SDNODE_ENUM
110
111#ifdef GET_SDNODE_DESC
112#undef GET_SDNODE_DESC
113
114namespace llvm {
115
116
117#ifdef __GNUC__
118#pragma GCC diagnostic push
119#pragma GCC diagnostic ignored "-Woverlength-strings"
120#endif
121static constexpr char NVPTXSDNodeNamesStorage[] =
122 "\0"
123 "NVPTXISD::BFI\0"
124 "NVPTXISD::BUILD_VECTOR\0"
125 "NVPTXISD::CALL\0"
126 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X\0"
127 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y\0"
128 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z\0"
129 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED\0"
130 "NVPTXISD::CVT_E2M1X4_F32X4_RS_SF\0"
131 "NVPTXISD::CVT_E2M3X4_F32X4_RS_SF\0"
132 "NVPTXISD::CVT_E3M2X4_F32X4_RS_SF\0"
133 "NVPTXISD::CVT_E4M3X4_F32X4_RS_SF\0"
134 "NVPTXISD::CVT_E5M2X4_F32X4_RS_SF\0"
135 "NVPTXISD::CallPrototype\0"
136 "NVPTXISD::DYNAMIC_STACKALLOC\0"
137 "NVPTXISD::DeclareArrayParam\0"
138 "NVPTXISD::DeclareScalarParam\0"
139 "NVPTXISD::FCOPYSIGN\0"
140 "NVPTXISD::FMAXIMUM3\0"
141 "NVPTXISD::FMAXNUM3\0"
142 "NVPTXISD::FMINIMUM3\0"
143 "NVPTXISD::FMINNUM3\0"
144 "NVPTXISD::FSHL_CLAMP\0"
145 "NVPTXISD::FSHR_CLAMP\0"
146 "NVPTXISD::MUL_WIDE_SIGNED\0"
147 "NVPTXISD::MUL_WIDE_UNSIGNED\0"
148 "NVPTXISD::MoveParam\0"
149 "NVPTXISD::PRMT\0"
150 "NVPTXISD::ProxyReg\0"
151 "NVPTXISD::RET_GLUE\0"
152 "NVPTXISD::SHL_CLAMP\0"
153 "NVPTXISD::SRL_CLAMP\0"
154 "NVPTXISD::STACKRESTORE\0"
155 "NVPTXISD::STACKSAVE\0"
156 "NVPTXISD::SUB_RN_FTZ_SAT\0"
157 "NVPTXISD::SUB_RN_SAT\0"
158 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_F32\0"
159 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_I32\0"
160 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_F32\0"
161 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_I32\0"
162 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_F32\0"
163 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_I32\0"
164 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_F32\0"
165 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_I32\0"
166 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_F32\0"
167 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_I32\0"
168 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_F32\0"
169 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_I32\0"
170 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_F32\0"
171 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_I32\0"
172 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_F32\0"
173 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_I32\0"
174 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_F32\0"
175 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_I32\0"
176 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_F32\0"
177 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_I32\0"
178 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_F32\0"
179 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_I32\0"
180 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_F32\0"
181 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_I32\0"
182 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_F32\0"
183 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_I32\0"
184 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_F32\0"
185 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_I32\0"
186 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
187 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
188 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
189 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
190 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
191 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
192 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
193 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
194 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
195 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
196 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
197 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
198 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
199 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
200 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
201 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
202 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
203 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
204 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
205 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
206 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
207 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
208 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
209 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
210 ;
211#ifdef __GNUC__
212#pragma GCC diagnostic pop
213#endif
214
215static constexpr llvm::StringTable
216NVPTXSDNodeNames = NVPTXSDNodeNamesStorage;
217
218static const VTByHwModePair NVPTXVTByHwModeTable[] = {
219 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
220};
221
222static const SDTypeConstraint NVPTXSDTypeConstraints[] = {
223 /* 0 */ {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
224 /* 131 */ {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
225 /* 263 */ {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
226 /* 331 */ {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
227 /* 367 */ {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
228 /* 387 */ {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
229 /* 399 */ {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
230 /* 407 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
231 /* 413 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
232 /* 418 */ {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
233 /* 434 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
234 /* 451 */ {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
235 /* 467 */ {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
236 /* 483 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
237 /* 500 */ {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
238 /* 516 */ {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
239 /* 523 */ {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
240 /* 531 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
241 /* 540 */ {SDTCisVT, 9, 0, 0, MVT::i1}, {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
242 /* 550 */ {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i1}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
243 /* 563 */ {SDTCisVT, 13, 0, 0, MVT::i1}, {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
244 /* 577 */ {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i1}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
245 /* 598 */ {SDTCisVT, 21, 0, 0, MVT::i1}, {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
246 /* 620 */ {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i1}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
247 /* 657 */ {SDTCisVT, 37, 0, 0, MVT::i1}, {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
248 /* 695 */ {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i1}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
249 /* 764 */ {SDTCisVT, 69, 0, 0, MVT::i1}, {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
250 /* 834 */ {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i1}, {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
251 /* 967 */ {SDTCisVT, 133, 0, 0, MVT::i1}, {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
252 /* 1101 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
253 /* 1106 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
254 /* 1109 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
255 /* 1116 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
256 /* 1123 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
257 /* 1127 */ {SDTCisSameNumEltsAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
258 /* 1132 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
259 /* 1135 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
260 /* 1139 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
261};
262
263static const SDNodeDesc NVPTXSDNodeDescs[] = {
264 {1, 4, 0, 0, 0, 1, 1101, 5}, // BFI
265 {1, 2, 0, 0, 0, 15, 0, 0}, // BUILD_VECTOR
266 {0, 6, 0|1<<SDNPHasChain, 0, 0, 38, 413, 5}, // CALL
267 {1, 2, 0, 0, 0, 53, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X
268 {1, 2, 0, 0, 0, 115, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y
269 {1, 2, 0, 0, 0, 177, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z
270 {1, 2, 0, 0, 0, 239, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED
271 {1, 6, 0, 0, 0, 295, 1109, 7}, // CVT_E2M1X4_F32X4_RS_SF
272 {1, 6, 0, 0, 0, 328, 1116, 7}, // CVT_E2M3X4_F32X4_RS_SF
273 {1, 6, 0, 0, 0, 361, 1116, 7}, // CVT_E3M2X4_F32X4_RS_SF
274 {1, 6, 0, 0, 0, 394, 1116, 7}, // CVT_E4M3X4_F32X4_RS_SF
275 {1, 6, 0, 0, 0, 427, 1116, 7}, // CVT_E5M2X4_F32X4_RS_SF
276 {0, 1, 0|1<<SDNPHasChain, 0, 0, 460, 1105, 1}, // CallPrototype
277 {1, 2, 0|1<<SDNPHasChain, 0, 0, 484, 1139, 3}, // DYNAMIC_STACKALLOC
278 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 513, 128, 3}, // DeclareArrayParam
279 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 541, 129, 2}, // DeclareScalarParam
280 {1, 2, 0, 0, 0, 570, 1132, 3}, // FCOPYSIGN
281 {1, 3, 0, 0, 0, 590, 1135, 4}, // FMAXIMUM3
282 {1, 3, 0, 0, 0, 610, 1135, 4}, // FMAXNUM3
283 {1, 3, 0, 0, 0, 629, 1135, 4}, // FMINIMUM3
284 {1, 3, 0, 0, 0, 649, 1135, 4}, // FMINNUM3
285 {1, 3, 0, 0, 0, 668, 1127, 5}, // FSHL_CLAMP
286 {1, 3, 0, 0, 0, 689, 1127, 5}, // FSHR_CLAMP
287 {1, 2, 0, 0, 0, 710, 1106, 3}, // MUL_WIDE_SIGNED
288 {1, 2, 0, 0, 0, 736, 1106, 3}, // MUL_WIDE_UNSIGNED
289 {1, 1, 0, 0, 0, 764, 1104, 2}, // MoveParam
290 {1, 4, 0, 0, 0, 784, 126, 5}, // PRMT
291 {1, 1, 0|1<<SDNPHasChain, 0, 0, 799, 1126, 1}, // ProxyReg
292 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 818, 0, 0}, // RET_GLUE
293 {1, 2, 0, 0, 0, 837, 1123, 4}, // SHL_CLAMP
294 {1, 2, 0, 0, 0, 857, 1123, 4}, // SRL_CLAMP
295 {0, 1, 0|1<<SDNPHasChain, 0, 0, 877, 1105, 1}, // STACKRESTORE
296 {1, 0, 0|1<<SDNPHasChain, 0, 0, 900, 1105, 1}, // STACKSAVE
297 {1, 2, 0, 0, 0, 920, 1132, 3}, // SUB_RN_FTZ_SAT
298 {1, 2, 0, 0, 0, 945, 1132, 3}, // SUB_RN_SAT
299 {129, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 966, 967, 134}, // TCGEN05_LD_RED_16x32bx2_X128_F32
300 {129, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1009, 131, 132}, // TCGEN05_LD_RED_16x32bx2_X128_I32
301 {17, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1052, 598, 22}, // TCGEN05_LD_RED_16x32bx2_X16_F32
302 {17, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1094, 367, 20}, // TCGEN05_LD_RED_16x32bx2_X16_I32
303 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1136, 523, 8}, // TCGEN05_LD_RED_16x32bx2_X2_F32
304 {3, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1177, 407, 6}, // TCGEN05_LD_RED_16x32bx2_X2_I32
305 {33, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1218, 657, 38}, // TCGEN05_LD_RED_16x32bx2_X32_F32
306 {33, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1260, 331, 36}, // TCGEN05_LD_RED_16x32bx2_X32_I32
307 {5, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1302, 540, 10}, // TCGEN05_LD_RED_16x32bx2_X4_F32
308 {5, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1343, 399, 8}, // TCGEN05_LD_RED_16x32bx2_X4_I32
309 {65, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1384, 764, 70}, // TCGEN05_LD_RED_16x32bx2_X64_F32
310 {65, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1426, 263, 68}, // TCGEN05_LD_RED_16x32bx2_X64_I32
311 {9, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1468, 563, 14}, // TCGEN05_LD_RED_16x32bx2_X8_F32
312 {9, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1509, 387, 12}, // TCGEN05_LD_RED_16x32bx2_X8_I32
313 {129, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1550, 834, 133}, // TCGEN05_LD_RED_32x32b_X128_F32
314 {129, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1591, 0, 131}, // TCGEN05_LD_RED_32x32b_X128_I32
315 {17, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1632, 577, 21}, // TCGEN05_LD_RED_32x32b_X16_F32
316 {17, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1672, 112, 19}, // TCGEN05_LD_RED_32x32b_X16_I32
317 {3, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1712, 516, 7}, // TCGEN05_LD_RED_32x32b_X2_F32
318 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1751, 126, 5}, // TCGEN05_LD_RED_32x32b_X2_I32
319 {33, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1790, 620, 37}, // TCGEN05_LD_RED_32x32b_X32_F32
320 {33, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1830, 96, 35}, // TCGEN05_LD_RED_32x32b_X32_I32
321 {5, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1870, 531, 9}, // TCGEN05_LD_RED_32x32b_X4_F32
322 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1909, 124, 7}, // TCGEN05_LD_RED_32x32b_X4_I32
323 {65, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1948, 695, 69}, // TCGEN05_LD_RED_32x32b_X64_F32
324 {65, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1988, 64, 67}, // TCGEN05_LD_RED_32x32b_X64_I32
325 {9, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2028, 550, 13}, // TCGEN05_LD_RED_32x32b_X8_F32
326 {9, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2067, 120, 11}, // TCGEN05_LD_RED_32x32b_X8_I32
327 {0, 11, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2106, 472, 11}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1
328 {0, 15, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2159, 468, 15}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2
329 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2212, 504, 12}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
330 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2273, 500, 16}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
331 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2334, 471, 12}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1
332 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2390, 467, 16}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2
333 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2446, 487, 13}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
334 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2510, 483, 17}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
335 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2574, 422, 12}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1
336 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2630, 422, 12}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
337 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2693, 418, 16}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2
338 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2749, 418, 16}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
339 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2812, 438, 13}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
340 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2876, 438, 13}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
341 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2947, 434, 17}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
342 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3011, 434, 17}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
343 {0, 11, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3082, 423, 11}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1
344 {0, 11, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3135, 423, 11}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
345 {0, 15, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3195, 419, 15}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2
346 {0, 15, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3248, 419, 15}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
347 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3308, 455, 12}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
348 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3369, 455, 12}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
349 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3437, 451, 16}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
350 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3498, 451, 16}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
351};
352
353static const SDNodeInfo NVPTXGenSDNodeInfo(
354 /*NumOpcodes=*/87, NVPTXSDNodeDescs, NVPTXSDNodeNames,
355 NVPTXVTByHwModeTable, NVPTXSDTypeConstraints);
356
357} // namespace llvm
358
359#endif // GET_SDNODE_DESC
360
361