1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: NVPTX.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::NVPTXISD {
14
15enum GenNodeType : unsigned {
16 BFI = ISD::BUILTIN_OP_END,
17 BUILD_VECTOR,
18 CALL,
19 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X,
20 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y,
21 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z,
22 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED,
23 CVT_E2M1X4_F32X4_RS_SF,
24 CVT_E2M3X4_F32X4_RS_SF,
25 CVT_E3M2X4_F32X4_RS_SF,
26 CVT_E4M3X4_F32X4_RS_SF,
27 CVT_E5M2X4_F32X4_RS_SF,
28 DYNAMIC_STACKALLOC,
29 DeclareArrayParam,
30 DeclareScalarParam,
31 FCOPYSIGN,
32 FMAXIMUM3,
33 FMAXNUM3,
34 FMINIMUM3,
35 FMINNUM3,
36 FSHL_CLAMP,
37 FSHR_CLAMP,
38 MUL_WIDE_SIGNED,
39 MUL_WIDE_UNSIGNED,
40 MoveParam,
41 PRMT,
42 ProxyReg,
43 RET_GLUE,
44 SHL_CLAMP,
45 SRL_CLAMP,
46 STACKRESTORE,
47 STACKSAVE,
48 ST_ASYNC_GPU_B8,
49 ST_ASYNC_MBARRIER_B128,
50 ST_ASYNC_MMIO_SYS_B8,
51 ST_ASYNC_SYS_B8,
52 SUB_RN_FTZ_SAT,
53 SUB_RN_SAT,
54 TCGEN05_LD_RED_16x32bx2_X128_F32,
55 TCGEN05_LD_RED_16x32bx2_X128_I32,
56 TCGEN05_LD_RED_16x32bx2_X16_F32,
57 TCGEN05_LD_RED_16x32bx2_X16_I32,
58 TCGEN05_LD_RED_16x32bx2_X2_F32,
59 TCGEN05_LD_RED_16x32bx2_X2_I32,
60 TCGEN05_LD_RED_16x32bx2_X32_F32,
61 TCGEN05_LD_RED_16x32bx2_X32_I32,
62 TCGEN05_LD_RED_16x32bx2_X4_F32,
63 TCGEN05_LD_RED_16x32bx2_X4_I32,
64 TCGEN05_LD_RED_16x32bx2_X64_F32,
65 TCGEN05_LD_RED_16x32bx2_X64_I32,
66 TCGEN05_LD_RED_16x32bx2_X8_F32,
67 TCGEN05_LD_RED_16x32bx2_X8_I32,
68 TCGEN05_LD_RED_32x32b_X128_F32,
69 TCGEN05_LD_RED_32x32b_X128_I32,
70 TCGEN05_LD_RED_32x32b_X16_F32,
71 TCGEN05_LD_RED_32x32b_X16_I32,
72 TCGEN05_LD_RED_32x32b_X2_F32,
73 TCGEN05_LD_RED_32x32b_X2_I32,
74 TCGEN05_LD_RED_32x32b_X32_F32,
75 TCGEN05_LD_RED_32x32b_X32_I32,
76 TCGEN05_LD_RED_32x32b_X4_F32,
77 TCGEN05_LD_RED_32x32b_X4_I32,
78 TCGEN05_LD_RED_32x32b_X64_F32,
79 TCGEN05_LD_RED_32x32b_X64_I32,
80 TCGEN05_LD_RED_32x32b_X8_F32,
81 TCGEN05_LD_RED_32x32b_X8_I32,
82 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1,
83 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2,
84 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
85 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
86 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1,
87 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2,
88 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
89 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
90 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1,
91 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
92 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2,
93 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
94 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
95 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
96 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
97 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
98 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1,
99 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
100 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2,
101 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
102 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
103 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
104 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
105 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
106};
107
108static constexpr unsigned GENERATED_OPCODE_END = TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT + 1;
109
110} // namespace llvm::NVPTXISD
111
112#endif // GET_SDNODE_ENUM
113
114#ifdef GET_SDNODE_DESC
115#undef GET_SDNODE_DESC
116
117namespace llvm {
118
119
120#ifdef __GNUC__
121#pragma GCC diagnostic push
122#pragma GCC diagnostic ignored "-Woverlength-strings"
123#endif
124static constexpr char NVPTXSDNodeNamesStorage[] =
125 "\0"
126 "NVPTXISD::BFI\0"
127 "NVPTXISD::BUILD_VECTOR\0"
128 "NVPTXISD::CALL\0"
129 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X\0"
130 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y\0"
131 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z\0"
132 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED\0"
133 "NVPTXISD::CVT_E2M1X4_F32X4_RS_SF\0"
134 "NVPTXISD::CVT_E2M3X4_F32X4_RS_SF\0"
135 "NVPTXISD::CVT_E3M2X4_F32X4_RS_SF\0"
136 "NVPTXISD::CVT_E4M3X4_F32X4_RS_SF\0"
137 "NVPTXISD::CVT_E5M2X4_F32X4_RS_SF\0"
138 "NVPTXISD::DYNAMIC_STACKALLOC\0"
139 "NVPTXISD::DeclareArrayParam\0"
140 "NVPTXISD::DeclareScalarParam\0"
141 "NVPTXISD::FCOPYSIGN\0"
142 "NVPTXISD::FMAXIMUM3\0"
143 "NVPTXISD::FMAXNUM3\0"
144 "NVPTXISD::FMINIMUM3\0"
145 "NVPTXISD::FMINNUM3\0"
146 "NVPTXISD::FSHL_CLAMP\0"
147 "NVPTXISD::FSHR_CLAMP\0"
148 "NVPTXISD::MUL_WIDE_SIGNED\0"
149 "NVPTXISD::MUL_WIDE_UNSIGNED\0"
150 "NVPTXISD::MoveParam\0"
151 "NVPTXISD::PRMT\0"
152 "NVPTXISD::ProxyReg\0"
153 "NVPTXISD::RET_GLUE\0"
154 "NVPTXISD::SHL_CLAMP\0"
155 "NVPTXISD::SRL_CLAMP\0"
156 "NVPTXISD::STACKRESTORE\0"
157 "NVPTXISD::STACKSAVE\0"
158 "NVPTXISD::ST_ASYNC_GPU_B8\0"
159 "NVPTXISD::ST_ASYNC_MBARRIER_B128\0"
160 "NVPTXISD::ST_ASYNC_MMIO_SYS_B8\0"
161 "NVPTXISD::ST_ASYNC_SYS_B8\0"
162 "NVPTXISD::SUB_RN_FTZ_SAT\0"
163 "NVPTXISD::SUB_RN_SAT\0"
164 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_F32\0"
165 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_I32\0"
166 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_F32\0"
167 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_I32\0"
168 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_F32\0"
169 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_I32\0"
170 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_F32\0"
171 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_I32\0"
172 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_F32\0"
173 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_I32\0"
174 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_F32\0"
175 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_I32\0"
176 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_F32\0"
177 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_I32\0"
178 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_F32\0"
179 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_I32\0"
180 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_F32\0"
181 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_I32\0"
182 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_F32\0"
183 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_I32\0"
184 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_F32\0"
185 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_I32\0"
186 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_F32\0"
187 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_I32\0"
188 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_F32\0"
189 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_I32\0"
190 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_F32\0"
191 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_I32\0"
192 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
193 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
194 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
195 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
196 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
197 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
198 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
199 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
200 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
201 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
202 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
203 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
204 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
205 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
206 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
207 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
208 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
209 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
210 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
211 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
212 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
213 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
214 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
215 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
216 ;
217#ifdef __GNUC__
218#pragma GCC diagnostic pop
219#endif
220
221static constexpr llvm::StringTable
222NVPTXSDNodeNames = NVPTXSDNodeNamesStorage;
223
224static const VTByHwModePair NVPTXVTByHwModeTable[] = {
225 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
226};
227
228static const SDTypeConstraint NVPTXSDTypeConstraints[] = {
229 /* 0 */ {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
230 /* 131 */ {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
231 /* 263 */ {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
232 /* 331 */ {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
233 /* 367 */ {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
234 /* 387 */ {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
235 /* 399 */ {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
236 /* 407 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
237 /* 413 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
238 /* 418 */ {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
239 /* 434 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
240 /* 451 */ {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
241 /* 467 */ {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
242 /* 483 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
243 /* 500 */ {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
244 /* 516 */ {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
245 /* 523 */ {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
246 /* 531 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
247 /* 540 */ {SDTCisVT, 9, 0, 0, MVT::i1}, {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
248 /* 550 */ {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i1}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
249 /* 563 */ {SDTCisVT, 13, 0, 0, MVT::i1}, {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
250 /* 577 */ {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i1}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
251 /* 598 */ {SDTCisVT, 21, 0, 0, MVT::i1}, {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
252 /* 620 */ {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i1}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
253 /* 657 */ {SDTCisVT, 37, 0, 0, MVT::i1}, {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
254 /* 695 */ {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i1}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
255 /* 764 */ {SDTCisVT, 69, 0, 0, MVT::i1}, {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
256 /* 834 */ {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i1}, {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
257 /* 967 */ {SDTCisVT, 133, 0, 0, MVT::i1}, {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
258 /* 1101 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
259 /* 1105 */ {SDTCisVT, 2, 0, 0, MVT::i1}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
260 /* 1107 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
261 /* 1112 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
262 /* 1115 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
263 /* 1122 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
264 /* 1129 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
265 /* 1133 */ {SDTCisSameNumEltsAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
266 /* 1138 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
267 /* 1141 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
268 /* 1145 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
269};
270
271static const SDNodeDesc NVPTXSDNodeDescs[] = {
272 {1, 4, 0, 0, 0, 1, 1107, 5}, // BFI
273 {1, 2, 0, 0, 0, 15, 0, 0}, // BUILD_VECTOR
274 {0, 6, 0|1<<SDNPHasChain, 0, 0, 38, 413, 5}, // CALL
275 {1, 2, 0, 0, 0, 53, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X
276 {1, 2, 0, 0, 0, 115, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y
277 {1, 2, 0, 0, 0, 177, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z
278 {1, 2, 0, 0, 0, 239, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED
279 {1, 6, 0, 0, 0, 295, 1115, 7}, // CVT_E2M1X4_F32X4_RS_SF
280 {1, 6, 0, 0, 0, 328, 1122, 7}, // CVT_E2M3X4_F32X4_RS_SF
281 {1, 6, 0, 0, 0, 361, 1122, 7}, // CVT_E3M2X4_F32X4_RS_SF
282 {1, 6, 0, 0, 0, 394, 1122, 7}, // CVT_E4M3X4_F32X4_RS_SF
283 {1, 6, 0, 0, 0, 427, 1122, 7}, // CVT_E5M2X4_F32X4_RS_SF
284 {1, 2, 0|1<<SDNPHasChain, 0, 0, 460, 1145, 3}, // DYNAMIC_STACKALLOC
285 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 489, 128, 3}, // DeclareArrayParam
286 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 517, 129, 2}, // DeclareScalarParam
287 {1, 2, 0, 0, 0, 546, 1138, 3}, // FCOPYSIGN
288 {1, 3, 0, 0, 0, 566, 1141, 4}, // FMAXIMUM3
289 {1, 3, 0, 0, 0, 586, 1141, 4}, // FMAXNUM3
290 {1, 3, 0, 0, 0, 605, 1141, 4}, // FMINIMUM3
291 {1, 3, 0, 0, 0, 625, 1141, 4}, // FMINNUM3
292 {1, 3, 0, 0, 0, 644, 1133, 5}, // FSHL_CLAMP
293 {1, 3, 0, 0, 0, 665, 1133, 5}, // FSHR_CLAMP
294 {1, 2, 0, 0, 0, 686, 1112, 3}, // MUL_WIDE_SIGNED
295 {1, 2, 0, 0, 0, 712, 1112, 3}, // MUL_WIDE_UNSIGNED
296 {1, 1, 0, 0, 0, 740, 1110, 2}, // MoveParam
297 {1, 4, 0, 0, 0, 760, 126, 5}, // PRMT
298 {1, 1, 0|1<<SDNPHasChain, 0, 0, 775, 1132, 1}, // ProxyReg
299 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 794, 0, 0}, // RET_GLUE
300 {1, 2, 0, 0, 0, 813, 1129, 4}, // SHL_CLAMP
301 {1, 2, 0, 0, 0, 833, 1129, 4}, // SRL_CLAMP
302 {0, 1, 0|1<<SDNPHasChain, 0, 0, 853, 1111, 1}, // STACKRESTORE
303 {1, 0, 0|1<<SDNPHasChain, 0, 0, 876, 1111, 1}, // STACKSAVE
304 {0, 3, 0|1<<SDNPHasChain, 0, 0, 896, 1105, 2}, // ST_ASYNC_GPU_B8
305 {0, 4, 0|1<<SDNPHasChain, 0, 0, 922, 1101, 4}, // ST_ASYNC_MBARRIER_B128
306 {0, 2, 0|1<<SDNPHasChain, 0, 0, 955, 1104, 1}, // ST_ASYNC_MMIO_SYS_B8
307 {0, 3, 0|1<<SDNPHasChain, 0, 0, 986, 1105, 2}, // ST_ASYNC_SYS_B8
308 {1, 2, 0, 0, 0, 1012, 1138, 3}, // SUB_RN_FTZ_SAT
309 {1, 2, 0, 0, 0, 1037, 1138, 3}, // SUB_RN_SAT
310 {129, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1058, 967, 134}, // TCGEN05_LD_RED_16x32bx2_X128_F32
311 {129, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1101, 131, 132}, // TCGEN05_LD_RED_16x32bx2_X128_I32
312 {17, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1144, 598, 22}, // TCGEN05_LD_RED_16x32bx2_X16_F32
313 {17, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1186, 367, 20}, // TCGEN05_LD_RED_16x32bx2_X16_I32
314 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1228, 523, 8}, // TCGEN05_LD_RED_16x32bx2_X2_F32
315 {3, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1269, 407, 6}, // TCGEN05_LD_RED_16x32bx2_X2_I32
316 {33, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1310, 657, 38}, // TCGEN05_LD_RED_16x32bx2_X32_F32
317 {33, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1352, 331, 36}, // TCGEN05_LD_RED_16x32bx2_X32_I32
318 {5, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1394, 540, 10}, // TCGEN05_LD_RED_16x32bx2_X4_F32
319 {5, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1435, 399, 8}, // TCGEN05_LD_RED_16x32bx2_X4_I32
320 {65, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1476, 764, 70}, // TCGEN05_LD_RED_16x32bx2_X64_F32
321 {65, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1518, 263, 68}, // TCGEN05_LD_RED_16x32bx2_X64_I32
322 {9, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1560, 563, 14}, // TCGEN05_LD_RED_16x32bx2_X8_F32
323 {9, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1601, 387, 12}, // TCGEN05_LD_RED_16x32bx2_X8_I32
324 {129, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1642, 834, 133}, // TCGEN05_LD_RED_32x32b_X128_F32
325 {129, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1683, 0, 131}, // TCGEN05_LD_RED_32x32b_X128_I32
326 {17, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1724, 577, 21}, // TCGEN05_LD_RED_32x32b_X16_F32
327 {17, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1764, 112, 19}, // TCGEN05_LD_RED_32x32b_X16_I32
328 {3, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1804, 516, 7}, // TCGEN05_LD_RED_32x32b_X2_F32
329 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1843, 126, 5}, // TCGEN05_LD_RED_32x32b_X2_I32
330 {33, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1882, 620, 37}, // TCGEN05_LD_RED_32x32b_X32_F32
331 {33, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1922, 96, 35}, // TCGEN05_LD_RED_32x32b_X32_I32
332 {5, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1962, 531, 9}, // TCGEN05_LD_RED_32x32b_X4_F32
333 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2001, 124, 7}, // TCGEN05_LD_RED_32x32b_X4_I32
334 {65, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2040, 695, 69}, // TCGEN05_LD_RED_32x32b_X64_F32
335 {65, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2080, 64, 67}, // TCGEN05_LD_RED_32x32b_X64_I32
336 {9, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2120, 550, 13}, // TCGEN05_LD_RED_32x32b_X8_F32
337 {9, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2159, 120, 11}, // TCGEN05_LD_RED_32x32b_X8_I32
338 {0, 11, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2198, 472, 11}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1
339 {0, 15, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2251, 468, 15}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2
340 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2304, 504, 12}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
341 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2365, 500, 16}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
342 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2426, 471, 12}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1
343 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2482, 467, 16}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2
344 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2538, 487, 13}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
345 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2602, 483, 17}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
346 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2666, 422, 12}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1
347 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2722, 422, 12}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
348 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2785, 418, 16}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2
349 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2841, 418, 16}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
350 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2904, 438, 13}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
351 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2968, 438, 13}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
352 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3039, 434, 17}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
353 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3103, 434, 17}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
354 {0, 11, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3174, 423, 11}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1
355 {0, 11, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3227, 423, 11}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
356 {0, 15, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3287, 419, 15}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2
357 {0, 15, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3340, 419, 15}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
358 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3400, 455, 12}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
359 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3461, 455, 12}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
360 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3529, 451, 16}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
361 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3590, 451, 16}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
362};
363
364static const SDNodeInfo NVPTXGenSDNodeInfo(
365 /*NumOpcodes=*/90, NVPTXSDNodeDescs, NVPTXSDNodeNames,
366 NVPTXVTByHwModeTable, NVPTXSDTypeConstraints);
367
368} // namespace llvm
369
370#endif // GET_SDNODE_DESC
371
372