1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: NVPTX.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::NVPTXISD {
14
15enum GenNodeType : unsigned {
16 BFI = ISD::BUILTIN_OP_END,
17 BUILD_VECTOR,
18 CALL,
19 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X,
20 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y,
21 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z,
22 CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED,
23 CVT_E2M1X4_F32X4_RS_SF,
24 CVT_E2M3X4_F32X4_RS_SF,
25 CVT_E3M2X4_F32X4_RS_SF,
26 CVT_E4M3X4_F32X4_RS_SF,
27 CVT_E5M2X4_F32X4_RS_SF,
28 DYNAMIC_STACKALLOC,
29 DeclareArrayParam,
30 DeclareScalarParam,
31 FCOPYSIGN,
32 FMAXIMUM3,
33 FMAXNUM3,
34 FMINIMUM3,
35 FMINNUM3,
36 FSHL_CLAMP,
37 FSHR_CLAMP,
38 MUL_WIDE_SIGNED,
39 MUL_WIDE_UNSIGNED,
40 MoveParam,
41 PRMT,
42 ProxyReg,
43 RET_GLUE,
44 SHL_CLAMP,
45 SPCOMPRESS_R10,
46 SPCOMPRESS_R12,
47 SPCOMPRESS_R18,
48 SPCOMPRESS_R2,
49 SPCOMPRESS_R20,
50 SPCOMPRESS_R24,
51 SPCOMPRESS_R3,
52 SPCOMPRESS_R36,
53 SPCOMPRESS_R40,
54 SPCOMPRESS_R48,
55 SPCOMPRESS_R5,
56 SPCOMPRESS_R6,
57 SPCOMPRESS_R72,
58 SPCOMPRESS_R80,
59 SPCOMPRESS_R9,
60 SPCOMPRESS_R96,
61 SPDECOMPRESS_R1,
62 SPDECOMPRESS_R128,
63 SPDECOMPRESS_R16,
64 SPDECOMPRESS_R2,
65 SPDECOMPRESS_R32,
66 SPDECOMPRESS_R4,
67 SPDECOMPRESS_R64,
68 SPDECOMPRESS_R8,
69 SRL_CLAMP,
70 STACKRESTORE,
71 STACKSAVE,
72 ST_ASYNC_GPU_B8,
73 ST_ASYNC_MBARRIER_B128,
74 ST_ASYNC_MMIO_SYS_B8,
75 ST_ASYNC_SYS_B8,
76 SUB_RM,
77 SUB_RM_FTZ,
78 SUB_RN,
79 SUB_RN_FTZ,
80 SUB_RN_FTZ_SAT,
81 SUB_RN_SAT,
82 SUB_RP,
83 SUB_RP_FTZ,
84 SUB_RZ,
85 SUB_RZ_FTZ,
86 Symbol,
87 TCGEN05_LD_RED_16x32bx2_X128_F32,
88 TCGEN05_LD_RED_16x32bx2_X128_I32,
89 TCGEN05_LD_RED_16x32bx2_X16_F32,
90 TCGEN05_LD_RED_16x32bx2_X16_I32,
91 TCGEN05_LD_RED_16x32bx2_X2_F32,
92 TCGEN05_LD_RED_16x32bx2_X2_I32,
93 TCGEN05_LD_RED_16x32bx2_X32_F32,
94 TCGEN05_LD_RED_16x32bx2_X32_I32,
95 TCGEN05_LD_RED_16x32bx2_X4_F32,
96 TCGEN05_LD_RED_16x32bx2_X4_I32,
97 TCGEN05_LD_RED_16x32bx2_X64_F32,
98 TCGEN05_LD_RED_16x32bx2_X64_I32,
99 TCGEN05_LD_RED_16x32bx2_X8_F32,
100 TCGEN05_LD_RED_16x32bx2_X8_I32,
101 TCGEN05_LD_RED_32x32b_X128_F32,
102 TCGEN05_LD_RED_32x32b_X128_I32,
103 TCGEN05_LD_RED_32x32b_X16_F32,
104 TCGEN05_LD_RED_32x32b_X16_I32,
105 TCGEN05_LD_RED_32x32b_X2_F32,
106 TCGEN05_LD_RED_32x32b_X2_I32,
107 TCGEN05_LD_RED_32x32b_X32_F32,
108 TCGEN05_LD_RED_32x32b_X32_I32,
109 TCGEN05_LD_RED_32x32b_X4_F32,
110 TCGEN05_LD_RED_32x32b_X4_I32,
111 TCGEN05_LD_RED_32x32b_X64_F32,
112 TCGEN05_LD_RED_32x32b_X64_I32,
113 TCGEN05_LD_RED_32x32b_X8_F32,
114 TCGEN05_LD_RED_32x32b_X8_I32,
115 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1,
116 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B,
117 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2,
118 TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B,
119 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
120 TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
121 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1,
122 TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2,
123 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
124 TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
125 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1,
126 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
127 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2,
128 TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
129 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
130 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
131 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
132 TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
133 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1,
134 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
135 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B,
136 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2,
137 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
138 TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B,
139 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
140 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
141 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
142 TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
143};
144
145static constexpr unsigned GENERATED_OPCODE_END = TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT + 1;
146
147} // namespace llvm::NVPTXISD
148
149#endif // GET_SDNODE_ENUM
150
151#ifdef GET_SDNODE_DESC
152#undef GET_SDNODE_DESC
153
154namespace llvm {
155
156
157#ifdef __GNUC__
158#pragma GCC diagnostic push
159#pragma GCC diagnostic ignored "-Woverlength-strings"
160#endif
161static constexpr char NVPTXSDNodeNamesStorage[] =
162 "\0"
163 "NVPTXISD::BFI\0"
164 "NVPTXISD::BUILD_VECTOR\0"
165 "NVPTXISD::CALL\0"
166 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X\0"
167 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y\0"
168 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z\0"
169 "NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED\0"
170 "NVPTXISD::CVT_E2M1X4_F32X4_RS_SF\0"
171 "NVPTXISD::CVT_E2M3X4_F32X4_RS_SF\0"
172 "NVPTXISD::CVT_E3M2X4_F32X4_RS_SF\0"
173 "NVPTXISD::CVT_E4M3X4_F32X4_RS_SF\0"
174 "NVPTXISD::CVT_E5M2X4_F32X4_RS_SF\0"
175 "NVPTXISD::DYNAMIC_STACKALLOC\0"
176 "NVPTXISD::DeclareArrayParam\0"
177 "NVPTXISD::DeclareScalarParam\0"
178 "NVPTXISD::FCOPYSIGN\0"
179 "NVPTXISD::FMAXIMUM3\0"
180 "NVPTXISD::FMAXNUM3\0"
181 "NVPTXISD::FMINIMUM3\0"
182 "NVPTXISD::FMINNUM3\0"
183 "NVPTXISD::FSHL_CLAMP\0"
184 "NVPTXISD::FSHR_CLAMP\0"
185 "NVPTXISD::MUL_WIDE_SIGNED\0"
186 "NVPTXISD::MUL_WIDE_UNSIGNED\0"
187 "NVPTXISD::MoveParam\0"
188 "NVPTXISD::PRMT\0"
189 "NVPTXISD::ProxyReg\0"
190 "NVPTXISD::RET_GLUE\0"
191 "NVPTXISD::SHL_CLAMP\0"
192 "NVPTXISD::SPCOMPRESS_R10\0"
193 "NVPTXISD::SPCOMPRESS_R12\0"
194 "NVPTXISD::SPCOMPRESS_R18\0"
195 "NVPTXISD::SPCOMPRESS_R2\0"
196 "NVPTXISD::SPCOMPRESS_R20\0"
197 "NVPTXISD::SPCOMPRESS_R24\0"
198 "NVPTXISD::SPCOMPRESS_R3\0"
199 "NVPTXISD::SPCOMPRESS_R36\0"
200 "NVPTXISD::SPCOMPRESS_R40\0"
201 "NVPTXISD::SPCOMPRESS_R48\0"
202 "NVPTXISD::SPCOMPRESS_R5\0"
203 "NVPTXISD::SPCOMPRESS_R6\0"
204 "NVPTXISD::SPCOMPRESS_R72\0"
205 "NVPTXISD::SPCOMPRESS_R80\0"
206 "NVPTXISD::SPCOMPRESS_R9\0"
207 "NVPTXISD::SPCOMPRESS_R96\0"
208 "NVPTXISD::SPDECOMPRESS_R1\0"
209 "NVPTXISD::SPDECOMPRESS_R128\0"
210 "NVPTXISD::SPDECOMPRESS_R16\0"
211 "NVPTXISD::SPDECOMPRESS_R2\0"
212 "NVPTXISD::SPDECOMPRESS_R32\0"
213 "NVPTXISD::SPDECOMPRESS_R4\0"
214 "NVPTXISD::SPDECOMPRESS_R64\0"
215 "NVPTXISD::SPDECOMPRESS_R8\0"
216 "NVPTXISD::SRL_CLAMP\0"
217 "NVPTXISD::STACKRESTORE\0"
218 "NVPTXISD::STACKSAVE\0"
219 "NVPTXISD::ST_ASYNC_GPU_B8\0"
220 "NVPTXISD::ST_ASYNC_MBARRIER_B128\0"
221 "NVPTXISD::ST_ASYNC_MMIO_SYS_B8\0"
222 "NVPTXISD::ST_ASYNC_SYS_B8\0"
223 "NVPTXISD::SUB_RM\0"
224 "NVPTXISD::SUB_RM_FTZ\0"
225 "NVPTXISD::SUB_RN\0"
226 "NVPTXISD::SUB_RN_FTZ\0"
227 "NVPTXISD::SUB_RN_FTZ_SAT\0"
228 "NVPTXISD::SUB_RN_SAT\0"
229 "NVPTXISD::SUB_RP\0"
230 "NVPTXISD::SUB_RP_FTZ\0"
231 "NVPTXISD::SUB_RZ\0"
232 "NVPTXISD::SUB_RZ_FTZ\0"
233 "NVPTXISD::Symbol\0"
234 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_F32\0"
235 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X128_I32\0"
236 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_F32\0"
237 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X16_I32\0"
238 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_F32\0"
239 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X2_I32\0"
240 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_F32\0"
241 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X32_I32\0"
242 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_F32\0"
243 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X4_I32\0"
244 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_F32\0"
245 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X64_I32\0"
246 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_F32\0"
247 "NVPTXISD::TCGEN05_LD_RED_16x32bx2_X8_I32\0"
248 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_F32\0"
249 "NVPTXISD::TCGEN05_LD_RED_32x32b_X128_I32\0"
250 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_F32\0"
251 "NVPTXISD::TCGEN05_LD_RED_32x32b_X16_I32\0"
252 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_F32\0"
253 "NVPTXISD::TCGEN05_LD_RED_32x32b_X2_I32\0"
254 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_F32\0"
255 "NVPTXISD::TCGEN05_LD_RED_32x32b_X32_I32\0"
256 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_F32\0"
257 "NVPTXISD::TCGEN05_LD_RED_32x32b_X4_I32\0"
258 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_F32\0"
259 "NVPTXISD::TCGEN05_LD_RED_32x32b_X64_I32\0"
260 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_F32\0"
261 "NVPTXISD::TCGEN05_LD_RED_32x32b_X8_I32\0"
262 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
263 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B\0"
264 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
265 "NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B\0"
266 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
267 "NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
268 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1\0"
269 "NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2\0"
270 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
271 "NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
272 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
273 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
274 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
275 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
276 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
277 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
278 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
279 "NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
280 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1\0"
281 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
282 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B\0"
283 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2\0"
284 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
285 "NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B\0"
286 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1\0"
287 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT\0"
288 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2\0"
289 "NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT\0"
290 ;
291#ifdef __GNUC__
292#pragma GCC diagnostic pop
293#endif
294
295static constexpr llvm::StringTable
296NVPTXSDNodeNames = NVPTXSDNodeNamesStorage;
297
298static const VTByHwModePair NVPTXVTByHwModeTable[] = {
299 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
300};
301
302static const SDTypeConstraint NVPTXSDTypeConstraints[] = {
303 /* 0 */ {SDTCisVT, 229, 0, 0, MVT::i32}, {SDTCisVT, 228, 0, 0, MVT::i32}, {SDTCisVT, 227, 0, 0, MVT::i32}, {SDTCisVT, 226, 0, 0, MVT::i32}, {SDTCisVT, 225, 0, 0, MVT::i32}, {SDTCisVT, 224, 0, 0, MVT::i32}, {SDTCisVT, 223, 0, 0, MVT::i32}, {SDTCisVT, 222, 0, 0, MVT::i32}, {SDTCisVT, 221, 0, 0, MVT::i32}, {SDTCisVT, 220, 0, 0, MVT::i32}, {SDTCisVT, 219, 0, 0, MVT::i32}, {SDTCisVT, 218, 0, 0, MVT::i32}, {SDTCisVT, 217, 0, 0, MVT::i32}, {SDTCisVT, 216, 0, 0, MVT::i32}, {SDTCisVT, 215, 0, 0, MVT::i32}, {SDTCisVT, 214, 0, 0, MVT::i32}, {SDTCisVT, 213, 0, 0, MVT::i32}, {SDTCisVT, 212, 0, 0, MVT::i32}, {SDTCisVT, 211, 0, 0, MVT::i32}, {SDTCisVT, 210, 0, 0, MVT::i32}, {SDTCisVT, 209, 0, 0, MVT::i32}, {SDTCisVT, 208, 0, 0, MVT::i32}, {SDTCisVT, 207, 0, 0, MVT::i32}, {SDTCisVT, 206, 0, 0, MVT::i32}, {SDTCisVT, 205, 0, 0, MVT::i32}, {SDTCisVT, 204, 0, 0, MVT::i32}, {SDTCisVT, 203, 0, 0, MVT::i32}, {SDTCisVT, 202, 0, 0, MVT::i32}, {SDTCisVT, 201, 0, 0, MVT::i32}, {SDTCisVT, 200, 0, 0, MVT::i32}, {SDTCisVT, 199, 0, 0, MVT::i32}, {SDTCisVT, 198, 0, 0, MVT::i32}, {SDTCisVT, 197, 0, 0, MVT::i32}, {SDTCisVT, 196, 0, 0, MVT::i32}, {SDTCisVT, 195, 0, 0, MVT::i32}, {SDTCisVT, 194, 0, 0, MVT::i32}, {SDTCisVT, 193, 0, 0, MVT::i32}, {SDTCisVT, 192, 0, 0, MVT::i32}, {SDTCisVT, 191, 0, 0, MVT::i32}, {SDTCisVT, 190, 0, 0, MVT::i32}, {SDTCisVT, 189, 0, 0, MVT::i32}, {SDTCisVT, 188, 0, 0, MVT::i32}, {SDTCisVT, 187, 0, 0, MVT::i32}, {SDTCisVT, 186, 0, 0, MVT::i32}, {SDTCisVT, 185, 0, 0, MVT::i32}, {SDTCisVT, 184, 0, 0, MVT::i32}, {SDTCisVT, 183, 0, 0, MVT::i32}, {SDTCisVT, 182, 0, 0, MVT::i32}, {SDTCisVT, 181, 0, 0, MVT::i32}, {SDTCisVT, 180, 0, 0, MVT::i32}, {SDTCisVT, 179, 0, 0, MVT::i32}, {SDTCisVT, 178, 0, 0, MVT::i32}, {SDTCisVT, 177, 0, 0, MVT::i32}, {SDTCisVT, 176, 0, 0, MVT::i32}, {SDTCisVT, 175, 0, 0, MVT::i32}, {SDTCisVT, 174, 0, 0, MVT::i32}, {SDTCisVT, 173, 0, 0, MVT::i32}, {SDTCisVT, 172, 0, 0, MVT::i32}, {SDTCisVT, 171, 0, 0, MVT::i32}, {SDTCisVT, 170, 0, 0, MVT::i32}, {SDTCisVT, 169, 0, 0, MVT::i32}, {SDTCisVT, 168, 0, 0, MVT::i32}, {SDTCisVT, 167, 0, 0, MVT::i32}, {SDTCisVT, 166, 0, 0, MVT::i32}, {SDTCisVT, 165, 0, 0, MVT::i32}, {SDTCisVT, 164, 0, 0, MVT::i32}, {SDTCisVT, 163, 0, 0, MVT::i32}, {SDTCisVT, 162, 0, 0, MVT::i32}, {SDTCisVT, 161, 0, 0, MVT::i32}, {SDTCisVT, 160, 0, 0, MVT::i32}, {SDTCisVT, 159, 0, 0, MVT::i32}, {SDTCisVT, 158, 0, 0, MVT::i32}, {SDTCisVT, 157, 0, 0, MVT::i32}, {SDTCisVT, 156, 0, 0, MVT::i32}, {SDTCisVT, 155, 0, 0, MVT::i32}, {SDTCisVT, 154, 0, 0, MVT::i32}, {SDTCisVT, 153, 0, 0, MVT::i32}, {SDTCisVT, 152, 0, 0, MVT::i32}, {SDTCisVT, 151, 0, 0, MVT::i32}, {SDTCisVT, 150, 0, 0, MVT::i32}, {SDTCisVT, 149, 0, 0, MVT::i32}, {SDTCisVT, 148, 0, 0, MVT::i32}, {SDTCisVT, 147, 0, 0, MVT::i32}, {SDTCisVT, 146, 0, 0, MVT::i32}, {SDTCisVT, 145, 0, 0, MVT::i32}, {SDTCisVT, 144, 0, 0, MVT::i32}, {SDTCisVT, 143, 0, 0, MVT::i32}, {SDTCisVT, 142, 0, 0, MVT::i32}, {SDTCisVT, 141, 0, 0, MVT::i32}, {SDTCisVT, 140, 0, 0, MVT::i32}, {SDTCisVT, 139, 0, 0, MVT::i32}, {SDTCisVT, 138, 0, 0, MVT::i32}, {SDTCisVT, 137, 0, 0, MVT::i32}, {SDTCisVT, 136, 0, 0, MVT::i32}, {SDTCisVT, 135, 0, 0, MVT::i32}, {SDTCisVT, 134, 0, 0, MVT::i32}, {SDTCisVT, 133, 0, 0, MVT::i32}, {SDTCisVT, 132, 0, 0, MVT::i32}, {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
304 /* 230 */ {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::i32}, {SDTCisVT, 127, 0, 0, MVT::i32}, {SDTCisVT, 126, 0, 0, MVT::i32}, {SDTCisVT, 125, 0, 0, MVT::i32}, {SDTCisVT, 124, 0, 0, MVT::i32}, {SDTCisVT, 123, 0, 0, MVT::i32}, {SDTCisVT, 122, 0, 0, MVT::i32}, {SDTCisVT, 121, 0, 0, MVT::i32}, {SDTCisVT, 120, 0, 0, MVT::i32}, {SDTCisVT, 119, 0, 0, MVT::i32}, {SDTCisVT, 118, 0, 0, MVT::i32}, {SDTCisVT, 117, 0, 0, MVT::i32}, {SDTCisVT, 116, 0, 0, MVT::i32}, {SDTCisVT, 115, 0, 0, MVT::i32}, {SDTCisVT, 114, 0, 0, MVT::i32}, {SDTCisVT, 113, 0, 0, MVT::i32}, {SDTCisVT, 112, 0, 0, MVT::i32}, {SDTCisVT, 111, 0, 0, MVT::i32}, {SDTCisVT, 110, 0, 0, MVT::i32}, {SDTCisVT, 109, 0, 0, MVT::i32}, {SDTCisVT, 108, 0, 0, MVT::i32}, {SDTCisVT, 107, 0, 0, MVT::i32}, {SDTCisVT, 106, 0, 0, MVT::i32}, {SDTCisVT, 105, 0, 0, MVT::i32}, {SDTCisVT, 104, 0, 0, MVT::i32}, {SDTCisVT, 103, 0, 0, MVT::i32}, {SDTCisVT, 102, 0, 0, MVT::i32}, {SDTCisVT, 101, 0, 0, MVT::i32}, {SDTCisVT, 100, 0, 0, MVT::i32}, {SDTCisVT, 99, 0, 0, MVT::i32}, {SDTCisVT, 98, 0, 0, MVT::i32}, {SDTCisVT, 97, 0, 0, MVT::i32}, {SDTCisVT, 96, 0, 0, MVT::i32}, {SDTCisVT, 95, 0, 0, MVT::i32}, {SDTCisVT, 94, 0, 0, MVT::i32}, {SDTCisVT, 93, 0, 0, MVT::i32}, {SDTCisVT, 92, 0, 0, MVT::i32}, {SDTCisVT, 91, 0, 0, MVT::i32}, {SDTCisVT, 90, 0, 0, MVT::i32}, {SDTCisVT, 89, 0, 0, MVT::i32}, {SDTCisVT, 88, 0, 0, MVT::i32}, {SDTCisVT, 87, 0, 0, MVT::i32}, {SDTCisVT, 86, 0, 0, MVT::i32}, {SDTCisVT, 85, 0, 0, MVT::i32}, {SDTCisVT, 84, 0, 0, MVT::i32}, {SDTCisVT, 83, 0, 0, MVT::i32}, {SDTCisVT, 82, 0, 0, MVT::i32}, {SDTCisVT, 81, 0, 0, MVT::i32}, {SDTCisVT, 80, 0, 0, MVT::i32}, {SDTCisVT, 79, 0, 0, MVT::i32}, {SDTCisVT, 78, 0, 0, MVT::i32}, {SDTCisVT, 77, 0, 0, MVT::i32}, {SDTCisVT, 76, 0, 0, MVT::i32}, {SDTCisVT, 75, 0, 0, MVT::i32}, {SDTCisVT, 74, 0, 0, MVT::i32}, {SDTCisVT, 73, 0, 0, MVT::i32}, {SDTCisVT, 72, 0, 0, MVT::i32}, {SDTCisVT, 71, 0, 0, MVT::i32}, {SDTCisVT, 70, 0, 0, MVT::i32}, {SDTCisVT, 69, 0, 0, MVT::i32}, {SDTCisVT, 68, 0, 0, MVT::i32}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
305 /* 362 */ {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::i32}, {SDTCisVT, 63, 0, 0, MVT::i32}, {SDTCisVT, 62, 0, 0, MVT::i32}, {SDTCisVT, 61, 0, 0, MVT::i32}, {SDTCisVT, 60, 0, 0, MVT::i32}, {SDTCisVT, 59, 0, 0, MVT::i32}, {SDTCisVT, 58, 0, 0, MVT::i32}, {SDTCisVT, 57, 0, 0, MVT::i32}, {SDTCisVT, 56, 0, 0, MVT::i32}, {SDTCisVT, 55, 0, 0, MVT::i32}, {SDTCisVT, 54, 0, 0, MVT::i32}, {SDTCisVT, 53, 0, 0, MVT::i32}, {SDTCisVT, 52, 0, 0, MVT::i32}, {SDTCisVT, 51, 0, 0, MVT::i32}, {SDTCisVT, 50, 0, 0, MVT::i32}, {SDTCisVT, 49, 0, 0, MVT::i32}, {SDTCisVT, 48, 0, 0, MVT::i32}, {SDTCisVT, 47, 0, 0, MVT::i32}, {SDTCisVT, 46, 0, 0, MVT::i32}, {SDTCisVT, 45, 0, 0, MVT::i32}, {SDTCisVT, 44, 0, 0, MVT::i32}, {SDTCisVT, 43, 0, 0, MVT::i32}, {SDTCisVT, 42, 0, 0, MVT::i32}, {SDTCisVT, 41, 0, 0, MVT::i32}, {SDTCisVT, 40, 0, 0, MVT::i32}, {SDTCisVT, 39, 0, 0, MVT::i32}, {SDTCisVT, 38, 0, 0, MVT::i32}, {SDTCisVT, 37, 0, 0, MVT::i32}, {SDTCisVT, 36, 0, 0, MVT::i32}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
306 /* 430 */ {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::i32}, {SDTCisVT, 31, 0, 0, MVT::i32}, {SDTCisVT, 30, 0, 0, MVT::i32}, {SDTCisVT, 29, 0, 0, MVT::i32}, {SDTCisVT, 28, 0, 0, MVT::i32}, {SDTCisVT, 27, 0, 0, MVT::i32}, {SDTCisVT, 26, 0, 0, MVT::i32}, {SDTCisVT, 25, 0, 0, MVT::i32}, {SDTCisVT, 24, 0, 0, MVT::i32}, {SDTCisVT, 23, 0, 0, MVT::i32}, {SDTCisVT, 22, 0, 0, MVT::i32}, {SDTCisVT, 21, 0, 0, MVT::i32}, {SDTCisVT, 20, 0, 0, MVT::i32}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
307 /* 466 */ {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
308 /* 486 */ {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
309 /* 498 */ {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
310 /* 506 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
311 /* 512 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
312 /* 517 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
313 /* 534 */ {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
314 /* 552 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
315 /* 569 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
316 /* 586 */ {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
317 /* 604 */ {SDTCisVT, 16, 0, 0, MVT::i32}, {SDTCisVT, 15, 0, 0, MVT::i32}, {SDTCisVT, 14, 0, 0, MVT::i32}, {SDTCisVT, 13, 0, 0, MVT::i32}, {SDTCisVT, 12, 0, 0, MVT::i32}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i32},
318 /* 621 */ {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
319 /* 628 */ {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i1}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
320 /* 636 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
321 /* 645 */ {SDTCisVT, 9, 0, 0, MVT::i1}, {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i64}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
322 /* 655 */ {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i1}, {SDTCisVT, 10, 0, 0, MVT::i32}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
323 /* 668 */ {SDTCisVT, 13, 0, 0, MVT::i1}, {SDTCisVT, 12, 0, 0, MVT::i1}, {SDTCisVT, 11, 0, 0, MVT::i32}, {SDTCisVT, 10, 0, 0, MVT::i64}, {SDTCisVT, 9, 0, 0, MVT::i32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
324 /* 682 */ {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i1}, {SDTCisVT, 18, 0, 0, MVT::i32}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
325 /* 703 */ {SDTCisVT, 21, 0, 0, MVT::i1}, {SDTCisVT, 20, 0, 0, MVT::i1}, {SDTCisVT, 19, 0, 0, MVT::i32}, {SDTCisVT, 18, 0, 0, MVT::i64}, {SDTCisVT, 17, 0, 0, MVT::i32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
326 /* 725 */ {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i1}, {SDTCisVT, 34, 0, 0, MVT::i32}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
327 /* 762 */ {SDTCisVT, 37, 0, 0, MVT::i1}, {SDTCisVT, 36, 0, 0, MVT::i1}, {SDTCisVT, 35, 0, 0, MVT::i32}, {SDTCisVT, 34, 0, 0, MVT::i64}, {SDTCisVT, 33, 0, 0, MVT::i32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
328 /* 800 */ {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i1}, {SDTCisVT, 66, 0, 0, MVT::i32}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
329 /* 869 */ {SDTCisVT, 69, 0, 0, MVT::i1}, {SDTCisVT, 68, 0, 0, MVT::i1}, {SDTCisVT, 67, 0, 0, MVT::i32}, {SDTCisVT, 66, 0, 0, MVT::i64}, {SDTCisVT, 65, 0, 0, MVT::i32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
330 /* 939 */ {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i1}, {SDTCisVT, 130, 0, 0, MVT::i32}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
331 /* 1072 */ {SDTCisVT, 133, 0, 0, MVT::i1}, {SDTCisVT, 132, 0, 0, MVT::i1}, {SDTCisVT, 131, 0, 0, MVT::i32}, {SDTCisVT, 130, 0, 0, MVT::i64}, {SDTCisVT, 129, 0, 0, MVT::i32}, {SDTCisVT, 128, 0, 0, MVT::f32}, {SDTCisVT, 127, 0, 0, MVT::f32}, {SDTCisVT, 126, 0, 0, MVT::f32}, {SDTCisVT, 125, 0, 0, MVT::f32}, {SDTCisVT, 124, 0, 0, MVT::f32}, {SDTCisVT, 123, 0, 0, MVT::f32}, {SDTCisVT, 122, 0, 0, MVT::f32}, {SDTCisVT, 121, 0, 0, MVT::f32}, {SDTCisVT, 120, 0, 0, MVT::f32}, {SDTCisVT, 119, 0, 0, MVT::f32}, {SDTCisVT, 118, 0, 0, MVT::f32}, {SDTCisVT, 117, 0, 0, MVT::f32}, {SDTCisVT, 116, 0, 0, MVT::f32}, {SDTCisVT, 115, 0, 0, MVT::f32}, {SDTCisVT, 114, 0, 0, MVT::f32}, {SDTCisVT, 113, 0, 0, MVT::f32}, {SDTCisVT, 112, 0, 0, MVT::f32}, {SDTCisVT, 111, 0, 0, MVT::f32}, {SDTCisVT, 110, 0, 0, MVT::f32}, {SDTCisVT, 109, 0, 0, MVT::f32}, {SDTCisVT, 108, 0, 0, MVT::f32}, {SDTCisVT, 107, 0, 0, MVT::f32}, {SDTCisVT, 106, 0, 0, MVT::f32}, {SDTCisVT, 105, 0, 0, MVT::f32}, {SDTCisVT, 104, 0, 0, MVT::f32}, {SDTCisVT, 103, 0, 0, MVT::f32}, {SDTCisVT, 102, 0, 0, MVT::f32}, {SDTCisVT, 101, 0, 0, MVT::f32}, {SDTCisVT, 100, 0, 0, MVT::f32}, {SDTCisVT, 99, 0, 0, MVT::f32}, {SDTCisVT, 98, 0, 0, MVT::f32}, {SDTCisVT, 97, 0, 0, MVT::f32}, {SDTCisVT, 96, 0, 0, MVT::f32}, {SDTCisVT, 95, 0, 0, MVT::f32}, {SDTCisVT, 94, 0, 0, MVT::f32}, {SDTCisVT, 93, 0, 0, MVT::f32}, {SDTCisVT, 92, 0, 0, MVT::f32}, {SDTCisVT, 91, 0, 0, MVT::f32}, {SDTCisVT, 90, 0, 0, MVT::f32}, {SDTCisVT, 89, 0, 0, MVT::f32}, {SDTCisVT, 88, 0, 0, MVT::f32}, {SDTCisVT, 87, 0, 0, MVT::f32}, {SDTCisVT, 86, 0, 0, MVT::f32}, {SDTCisVT, 85, 0, 0, MVT::f32}, {SDTCisVT, 84, 0, 0, MVT::f32}, {SDTCisVT, 83, 0, 0, MVT::f32}, {SDTCisVT, 82, 0, 0, MVT::f32}, {SDTCisVT, 81, 0, 0, MVT::f32}, {SDTCisVT, 80, 0, 0, MVT::f32}, {SDTCisVT, 79, 0, 0, MVT::f32}, {SDTCisVT, 78, 0, 0, MVT::f32}, {SDTCisVT, 77, 0, 0, MVT::f32}, {SDTCisVT, 76, 0, 0, MVT::f32}, {SDTCisVT, 75, 0, 0, MVT::f32}, {SDTCisVT, 74, 0, 0, MVT::f32}, {SDTCisVT, 73, 0, 0, MVT::f32}, {SDTCisVT, 72, 0, 0, MVT::f32}, {SDTCisVT, 71, 0, 0, MVT::f32}, {SDTCisVT, 70, 0, 0, MVT::f32}, {SDTCisVT, 69, 0, 0, MVT::f32}, {SDTCisVT, 68, 0, 0, MVT::f32}, {SDTCisVT, 67, 0, 0, MVT::f32}, {SDTCisVT, 66, 0, 0, MVT::f32}, {SDTCisVT, 65, 0, 0, MVT::f32}, {SDTCisVT, 64, 0, 0, MVT::f32}, {SDTCisVT, 63, 0, 0, MVT::f32}, {SDTCisVT, 62, 0, 0, MVT::f32}, {SDTCisVT, 61, 0, 0, MVT::f32}, {SDTCisVT, 60, 0, 0, MVT::f32}, {SDTCisVT, 59, 0, 0, MVT::f32}, {SDTCisVT, 58, 0, 0, MVT::f32}, {SDTCisVT, 57, 0, 0, MVT::f32}, {SDTCisVT, 56, 0, 0, MVT::f32}, {SDTCisVT, 55, 0, 0, MVT::f32}, {SDTCisVT, 54, 0, 0, MVT::f32}, {SDTCisVT, 53, 0, 0, MVT::f32}, {SDTCisVT, 52, 0, 0, MVT::f32}, {SDTCisVT, 51, 0, 0, MVT::f32}, {SDTCisVT, 50, 0, 0, MVT::f32}, {SDTCisVT, 49, 0, 0, MVT::f32}, {SDTCisVT, 48, 0, 0, MVT::f32}, {SDTCisVT, 47, 0, 0, MVT::f32}, {SDTCisVT, 46, 0, 0, MVT::f32}, {SDTCisVT, 45, 0, 0, MVT::f32}, {SDTCisVT, 44, 0, 0, MVT::f32}, {SDTCisVT, 43, 0, 0, MVT::f32}, {SDTCisVT, 42, 0, 0, MVT::f32}, {SDTCisVT, 41, 0, 0, MVT::f32}, {SDTCisVT, 40, 0, 0, MVT::f32}, {SDTCisVT, 39, 0, 0, MVT::f32}, {SDTCisVT, 38, 0, 0, MVT::f32}, {SDTCisVT, 37, 0, 0, MVT::f32}, {SDTCisVT, 36, 0, 0, MVT::f32}, {SDTCisVT, 35, 0, 0, MVT::f32}, {SDTCisVT, 34, 0, 0, MVT::f32}, {SDTCisVT, 33, 0, 0, MVT::f32}, {SDTCisVT, 32, 0, 0, MVT::f32}, {SDTCisVT, 31, 0, 0, MVT::f32}, {SDTCisVT, 30, 0, 0, MVT::f32}, {SDTCisVT, 29, 0, 0, MVT::f32}, {SDTCisVT, 28, 0, 0, MVT::f32}, {SDTCisVT, 27, 0, 0, MVT::f32}, {SDTCisVT, 26, 0, 0, MVT::f32}, {SDTCisVT, 25, 0, 0, MVT::f32}, {SDTCisVT, 24, 0, 0, MVT::f32}, {SDTCisVT, 23, 0, 0, MVT::f32}, {SDTCisVT, 22, 0, 0, MVT::f32}, {SDTCisVT, 21, 0, 0, MVT::f32}, {SDTCisVT, 20, 0, 0, MVT::f32}, {SDTCisVT, 19, 0, 0, MVT::f32}, {SDTCisVT, 18, 0, 0, MVT::f32}, {SDTCisVT, 17, 0, 0, MVT::f32}, {SDTCisVT, 16, 0, 0, MVT::f32}, {SDTCisVT, 15, 0, 0, MVT::f32}, {SDTCisVT, 14, 0, 0, MVT::f32}, {SDTCisVT, 13, 0, 0, MVT::f32}, {SDTCisVT, 12, 0, 0, MVT::f32}, {SDTCisVT, 11, 0, 0, MVT::f32}, {SDTCisVT, 10, 0, 0, MVT::f32}, {SDTCisVT, 9, 0, 0, MVT::f32}, {SDTCisVT, 8, 0, 0, MVT::f32}, {SDTCisVT, 7, 0, 0, MVT::f32}, {SDTCisVT, 6, 0, 0, MVT::f32}, {SDTCisVT, 5, 0, 0, MVT::f32}, {SDTCisVT, 4, 0, 0, MVT::f32}, {SDTCisVT, 3, 0, 0, MVT::f32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f32},
332 /* 1206 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
333 /* 1210 */ {SDTCisVT, 2, 0, 0, MVT::i1}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
334 /* 1212 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
335 /* 1217 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
336 /* 1220 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
337 /* 1227 */ {SDTCisInt, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
338 /* 1234 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
339 /* 1238 */ {SDTCisSameNumEltsAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
340 /* 1243 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
341 /* 1246 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
342 /* 1250 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
343};
344
345static const SDNodeDesc NVPTXSDNodeDescs[] = {
346 {1, 4, 0, 0, 0, 1, 1212, 5}, // BFI
347 {1, 2, 0, 0, 0, 15, 0, 0}, // BUILD_VECTOR
348 {0, 6, 0|1<<SDNPHasChain, 0, 0, 38, 512, 5}, // CALL
349 {1, 2, 0, 0, 0, 53, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X
350 {1, 2, 0, 0, 0, 115, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y
351 {1, 2, 0, 0, 0, 177, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z
352 {1, 2, 0, 0, 0, 239, 0, 0}, // CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED
353 {1, 6, 0, 0, 0, 295, 1220, 7}, // CVT_E2M1X4_F32X4_RS_SF
354 {1, 6, 0, 0, 0, 328, 1227, 7}, // CVT_E2M3X4_F32X4_RS_SF
355 {1, 6, 0, 0, 0, 361, 1227, 7}, // CVT_E3M2X4_F32X4_RS_SF
356 {1, 6, 0, 0, 0, 394, 1227, 7}, // CVT_E4M3X4_F32X4_RS_SF
357 {1, 6, 0, 0, 0, 427, 1227, 7}, // CVT_E5M2X4_F32X4_RS_SF
358 {1, 2, 0|1<<SDNPHasChain, 0, 0, 460, 1250, 3}, // DYNAMIC_STACKALLOC
359 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 489, 227, 3}, // DeclareArrayParam
360 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 517, 228, 2}, // DeclareScalarParam
361 {1, 2, 0, 0, 0, 546, 1243, 3}, // FCOPYSIGN
362 {1, 3, 0, 0, 0, 566, 1246, 4}, // FMAXIMUM3
363 {1, 3, 0, 0, 0, 586, 1246, 4}, // FMAXNUM3
364 {1, 3, 0, 0, 0, 605, 1246, 4}, // FMINIMUM3
365 {1, 3, 0, 0, 0, 625, 1246, 4}, // FMINNUM3
366 {1, 3, 0, 0, 0, 644, 1238, 5}, // FSHL_CLAMP
367 {1, 3, 0, 0, 0, 665, 1238, 5}, // FSHR_CLAMP
368 {1, 2, 0, 0, 0, 686, 1217, 3}, // MUL_WIDE_SIGNED
369 {1, 2, 0, 0, 0, 712, 1217, 3}, // MUL_WIDE_UNSIGNED
370 {1, 1, 0, 0, 0, 740, 1215, 2}, // MoveParam
371 {1, 4, 0, 0, 0, 760, 225, 5}, // PRMT
372 {1, 1, 0|1<<SDNPHasChain, 0, 0, 775, 1237, 1}, // ProxyReg
373 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 794, 0, 0}, // RET_GLUE
374 {1, 2, 0, 0, 0, 813, 1234, 4}, // SHL_CLAMP
375 {10, -1, 0, 0, 0, 833, 198, 32}, // SPCOMPRESS_R10
376 {12, -1, 0, 0, 0, 858, 196, 34}, // SPCOMPRESS_R12
377 {18, -1, 0, 0, 0, 883, 174, 56}, // SPCOMPRESS_R18
378 {2, -1, 0, 0, 0, 908, 220, 10}, // SPCOMPRESS_R2
379 {20, -1, 0, 0, 0, 932, 172, 58}, // SPCOMPRESS_R20
380 {24, -1, 0, 0, 0, 957, 168, 62}, // SPCOMPRESS_R24
381 {3, -1, 0, 0, 0, 982, 217, 13}, // SPCOMPRESS_R3
382 {36, -1, 0, 0, 0, 1006, 124, 106}, // SPCOMPRESS_R36
383 {40, -1, 0, 0, 0, 1031, 120, 110}, // SPCOMPRESS_R40
384 {48, -1, 0, 0, 0, 1056, 112, 118}, // SPCOMPRESS_R48
385 {5, -1, 0, 0, 0, 1081, 211, 19}, // SPCOMPRESS_R5
386 {6, -1, 0, 0, 0, 1105, 210, 20}, // SPCOMPRESS_R6
387 {72, -1, 0, 0, 0, 1129, 24, 206}, // SPCOMPRESS_R72
388 {80, -1, 0, 0, 0, 1154, 16, 214}, // SPCOMPRESS_R80
389 {9, -1, 0, 0, 0, 1179, 199, 31}, // SPCOMPRESS_R9
390 {96, -1, 0, 0, 0, 1203, 0, 230}, // SPCOMPRESS_R96
391 {1, -1, 0, 0, 0, 1228, 222, 8}, // SPDECOMPRESS_R1
392 {128, -1, 0, 0, 0, 1254, 0, 0}, // SPDECOMPRESS_R128
393 {16, -1, 0, 0, 0, 1282, 0, 0}, // SPDECOMPRESS_R16
394 {2, -1, 0, 0, 0, 1309, 221, 9}, // SPDECOMPRESS_R2
395 {32, -1, 0, 0, 0, 1335, 0, 0}, // SPDECOMPRESS_R32
396 {4, -1, 0, 0, 0, 1362, 0, 0}, // SPDECOMPRESS_R4
397 {64, -1, 0, 0, 0, 1388, 0, 0}, // SPDECOMPRESS_R64
398 {8, -1, 0, 0, 0, 1415, 0, 0}, // SPDECOMPRESS_R8
399 {1, 2, 0, 0, 0, 1441, 1234, 4}, // SRL_CLAMP
400 {0, 1, 0|1<<SDNPHasChain, 0, 0, 1461, 1216, 1}, // STACKRESTORE
401 {1, 0, 0|1<<SDNPHasChain, 0, 0, 1484, 1216, 1}, // STACKSAVE
402 {0, 3, 0|1<<SDNPHasChain, 0, 0, 1504, 1210, 2}, // ST_ASYNC_GPU_B8
403 {0, 4, 0|1<<SDNPHasChain, 0, 0, 1530, 1206, 4}, // ST_ASYNC_MBARRIER_B128
404 {0, 2, 0|1<<SDNPHasChain, 0, 0, 1563, 1209, 1}, // ST_ASYNC_MMIO_SYS_B8
405 {0, 3, 0|1<<SDNPHasChain, 0, 0, 1594, 1210, 2}, // ST_ASYNC_SYS_B8
406 {1, 2, 0, 0, 0, 1620, 1243, 3}, // SUB_RM
407 {1, 2, 0, 0, 0, 1637, 1243, 3}, // SUB_RM_FTZ
408 {1, 2, 0, 0, 0, 1658, 1243, 3}, // SUB_RN
409 {1, 2, 0, 0, 0, 1675, 1243, 3}, // SUB_RN_FTZ
410 {1, 2, 0, 0, 0, 1696, 1243, 3}, // SUB_RN_FTZ_SAT
411 {1, 2, 0, 0, 0, 1721, 1243, 3}, // SUB_RN_SAT
412 {1, 2, 0, 0, 0, 1742, 1243, 3}, // SUB_RP
413 {1, 2, 0, 0, 0, 1759, 1243, 3}, // SUB_RP_FTZ
414 {1, 2, 0, 0, 0, 1780, 1243, 3}, // SUB_RZ
415 {1, 2, 0, 0, 0, 1797, 1243, 3}, // SUB_RZ_FTZ
416 {1, 1, 0, 0, 0, 1818, 1215, 2}, // Symbol
417 {129, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1835, 1072, 134}, // TCGEN05_LD_RED_16x32bx2_X128_F32
418 {129, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1878, 230, 132}, // TCGEN05_LD_RED_16x32bx2_X128_I32
419 {17, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1921, 703, 22}, // TCGEN05_LD_RED_16x32bx2_X16_F32
420 {17, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1963, 466, 20}, // TCGEN05_LD_RED_16x32bx2_X16_I32
421 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2005, 628, 8}, // TCGEN05_LD_RED_16x32bx2_X2_F32
422 {3, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2046, 506, 6}, // TCGEN05_LD_RED_16x32bx2_X2_I32
423 {33, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2087, 762, 38}, // TCGEN05_LD_RED_16x32bx2_X32_F32
424 {33, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2129, 430, 36}, // TCGEN05_LD_RED_16x32bx2_X32_I32
425 {5, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2171, 645, 10}, // TCGEN05_LD_RED_16x32bx2_X4_F32
426 {5, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2212, 498, 8}, // TCGEN05_LD_RED_16x32bx2_X4_I32
427 {65, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2253, 869, 70}, // TCGEN05_LD_RED_16x32bx2_X64_F32
428 {65, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2295, 362, 68}, // TCGEN05_LD_RED_16x32bx2_X64_I32
429 {9, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2337, 668, 14}, // TCGEN05_LD_RED_16x32bx2_X8_F32
430 {9, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2378, 486, 12}, // TCGEN05_LD_RED_16x32bx2_X8_I32
431 {129, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2419, 939, 133}, // TCGEN05_LD_RED_32x32b_X128_F32
432 {129, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2460, 99, 131}, // TCGEN05_LD_RED_32x32b_X128_I32
433 {17, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2501, 682, 21}, // TCGEN05_LD_RED_32x32b_X16_F32
434 {17, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2541, 211, 19}, // TCGEN05_LD_RED_32x32b_X16_I32
435 {3, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2581, 621, 7}, // TCGEN05_LD_RED_32x32b_X2_F32
436 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2620, 225, 5}, // TCGEN05_LD_RED_32x32b_X2_I32
437 {33, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2659, 725, 37}, // TCGEN05_LD_RED_32x32b_X32_F32
438 {33, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2699, 195, 35}, // TCGEN05_LD_RED_32x32b_X32_I32
439 {5, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2739, 636, 9}, // TCGEN05_LD_RED_32x32b_X4_F32
440 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2778, 223, 7}, // TCGEN05_LD_RED_32x32b_X4_I32
441 {65, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2817, 800, 69}, // TCGEN05_LD_RED_32x32b_X64_F32
442 {65, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2857, 163, 67}, // TCGEN05_LD_RED_32x32b_X64_I32
443 {9, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2897, 655, 13}, // TCGEN05_LD_RED_32x32b_X8_F32
444 {9, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2936, 219, 11}, // TCGEN05_LD_RED_32x32b_X8_I32
445 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2975, 574, 12}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1
446 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3028, 574, 12}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B
447 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3094, 570, 16}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2
448 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3147, 570, 16}, // TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B
449 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3213, 608, 13}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
450 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3274, 604, 17}, // TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
451 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3335, 573, 13}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1
452 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3391, 569, 17}, // TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2
453 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3447, 590, 14}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1
454 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3511, 586, 18}, // TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2
455 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3575, 521, 13}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1
456 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3631, 521, 13}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
457 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3694, 517, 17}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2
458 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3750, 517, 17}, // TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
459 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3813, 538, 14}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
460 {0, 14, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3877, 538, 14}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
461 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3948, 534, 18}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
462 {0, 18, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4012, 534, 18}, // TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
463 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4083, 522, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1
464 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4136, 522, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT
465 {0, 12, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4196, 522, 12}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_DECOMPRESS_B
466 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4262, 518, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2
467 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4315, 518, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT
468 {0, 16, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4375, 518, 16}, // TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_DECOMPRESS_B
469 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4441, 556, 13}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1
470 {0, 13, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4502, 556, 13}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT
471 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4570, 552, 17}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2
472 {0, 17, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4631, 552, 17}, // TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT
473};
474
475static const SDNodeInfo NVPTXGenSDNodeInfo(
476 /*NumOpcodes=*/127, NVPTXSDNodeDescs, NVPTXSDNodeNames,
477 NVPTXVTByHwModeTable, NVPTXSDTypeConstraints);
478
479} // namespace llvm
480
481#endif // GET_SDNODE_DESC
482
483