1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
10#define LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
11
12#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
13
14#define GET_SDNODE_ENUM
15#include "NVPTXGenSDNodeInfo.inc"
16
17namespace llvm {
18namespace NVPTXISD {
19
20enum NodeType : unsigned {
21 SETP_F16X2 = GENERATED_OPCODE_END,
22 SETP_BF16X2,
23 UNPACK_VECTOR,
24
25 FIRST_MEMORY_OPCODE,
26
27 /// These nodes are used to lower atomic instructions with i128 type. They are
28 /// similar to the generic nodes, but the input and output values are split
29 /// into two 64-bit values.
30 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP_B128(INCHAIN, ptr, cmpLo, cmpHi,
31 /// swapLo, swapHi)
32 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP_B128(INCHAIN, ptr, amtLo, amtHi)
33 ATOMIC_CMP_SWAP_B128 = FIRST_MEMORY_OPCODE,
34 ATOMIC_SWAP_B128,
35
36 LoadV2,
37 LoadV4,
38 LoadV8,
39 MLoad,
40 LDUV2, // LDU.v2
41 LDUV4, // LDU.v4
42 StoreV2,
43 StoreV4,
44 StoreV8,
45 LAST_MEMORY_OPCODE = StoreV8,
46};
47
48} // namespace NVPTXISD
49
50class NVPTXSelectionDAGInfo : public SelectionDAGGenTargetInfo {
51public:
52 NVPTXSelectionDAGInfo();
53
54 ~NVPTXSelectionDAGInfo() override;
55
56 const char *getTargetNodeName(unsigned Opcode) const override;
57
58 bool isTargetMemoryOpcode(unsigned Opcode) const override;
59
60 void verifyTargetNode(const SelectionDAG &DAG,
61 const SDNode *N) const override;
62};
63
64} // namespace llvm
65
66#endif // LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
67