1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_CALLING_CONV_IMPL
10#undef GET_CALLING_CONV_IMPL
11
12bool llvm::CC_PPC32_SVR4(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
14 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
15bool llvm::CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
17 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
18static bool CC_PPC32_SVR4_Common(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
20 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
21bool llvm::CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
23 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
24static bool CC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
25 MVT LocVT, CCValAssign::LocInfo LocInfo,
26 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
27bool llvm::CC_PPC64_ELF(unsigned ValNo, MVT ValVT,
28 MVT LocVT, CCValAssign::LocInfo LocInfo,
29 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
30bool llvm::CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT,
31 MVT LocVT, CCValAssign::LocInfo LocInfo,
32 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
33bool llvm::RetCC_PPC(unsigned ValNo, MVT ValVT,
34 MVT LocVT, CCValAssign::LocInfo LocInfo,
35 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
36static bool RetCC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
37 MVT LocVT, CCValAssign::LocInfo LocInfo,
38 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
39bool llvm::RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT,
40 MVT LocVT, CCValAssign::LocInfo LocInfo,
41 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
42bool llvm::RetCC_PPC_Cold(unsigned ValNo, MVT ValVT,
43 MVT LocVT, CCValAssign::LocInfo LocInfo,
44 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
45
46
47bool llvm::CC_PPC32_SVR4(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
50
51 if (LocVT == MVT::v16i8 ||
52 LocVT == MVT::v8i16 ||
53 LocVT == MVT::v4i32 ||
54 LocVT == MVT::v2i64 ||
55 LocVT == MVT::v1i128 ||
56 LocVT == MVT::v4f32 ||
57 LocVT == MVT::v2f64) {
58 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
59 static const MCPhysReg RegList1[] = {
60 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
61 };
62 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
63 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
64 return false;
65 }
66 }
67 }
68
69 if (LocVT == MVT::f128) {
70 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
71 static const MCPhysReg RegList2[] = {
72 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
73 };
74 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
75 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
76 return false;
77 }
78 }
79 }
80
81 if (!CC_PPC32_SVR4_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
82 return false;
83
84 return true; // CC didn't match.
85}
86
87
88bool llvm::CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT,
89 MVT LocVT, CCValAssign::LocInfo LocInfo,
90 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
91
92 if (ArgFlags.isByVal()) {
93 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
94 return false;
95 }
96
97 if (CC_PPC32_SVR4_Custom_Dummy(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
98 return false;
99
100 return true; // CC didn't match.
101}
102
103
104static bool CC_PPC32_SVR4_Common(unsigned ValNo, MVT ValVT,
105 MVT LocVT, CCValAssign::LocInfo LocInfo,
106 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
107
108 if (LocVT == MVT::i1) {
109 LocVT = MVT::i32;
110 if (ArgFlags.isSExt())
111 LocInfo = CCValAssign::SExt;
112 else if (ArgFlags.isZExt())
113 LocInfo = CCValAssign::ZExt;
114 else
115 LocInfo = CCValAssign::AExt;
116 }
117
118 if (LocVT == MVT::i32) {
119 if (ArgFlags.isSplit()) {
120 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().useSoftFloat()) {
121 if (!OrigTy->isPPC_FP128Ty()) {
122 if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
123 return false;
124 }
125 }
126 }
127 }
128
129 if (LocVT == MVT::i32) {
130 if (ArgFlags.isSplit()) {
131 if (!State.getMachineFunction().getSubtarget<PPCSubtarget>().useSoftFloat()) {
132 if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
133 return false;
134 }
135 }
136 }
137
138 if (LocVT == MVT::f64) {
139 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasSPE()) {
140 if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
141 return false;
142 }
143 }
144
145 if (ArgFlags.isSplit()) {
146 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().useSoftFloat()) {
147 if (OrigTy->isPPC_FP128Ty()) {
148 if (CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
149 return false;
150 }
151 }
152 }
153
154 if (ArgFlags.isNest()) {
155 if (MCRegister Reg = State.AllocateReg(Reg: PPC::R11)) {
156 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
157 return false;
158 }
159 }
160
161 if (LocVT == MVT::i32) {
162 static const MCPhysReg RegList1[] = {
163 PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
164 };
165 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
166 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
167 return false;
168 }
169 }
170
171 if (LocVT == MVT::f64) {
172 if (ArgFlags.isSplit()) {
173 if (CC_PPC32_SVR4_Custom_AlignFPArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
174 return false;
175 }
176 }
177
178 if (LocVT == MVT::f32 ||
179 LocVT == MVT::f64) {
180 if (!State.getMachineFunction().getSubtarget<PPCSubtarget>().hasSPE()) {
181 static const MCPhysReg RegList2[] = {
182 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
183 };
184 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
185 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
186 return false;
187 }
188 }
189 }
190
191 if (LocVT == MVT::f64) {
192 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasSPE()) {
193 if (CC_PPC32_SPE_CustomSplitFP64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
194 return false;
195 }
196 }
197
198 if (LocVT == MVT::f32) {
199 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasSPE()) {
200 static const MCPhysReg RegList3[] = {
201 PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
202 };
203 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
204 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
205 return false;
206 }
207 }
208 }
209
210 if (LocVT == MVT::i32) {
211 if (ArgFlags.isSplit()) {
212 int64_t Offset4 = State.AllocateStack(Size: 4, Alignment: Align(8));
213 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
214 return false;
215 }
216 }
217
218 if (LocVT == MVT::i32) {
219 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4));
220 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
221 return false;
222 }
223
224 if (LocVT == MVT::f32) {
225 int64_t Offset6 = State.AllocateStack(Size: 4, Alignment: Align(4));
226 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
227 return false;
228 }
229
230 if (LocVT == MVT::f64) {
231 int64_t Offset7 = State.AllocateStack(Size: 8, Alignment: Align(8));
232 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
233 return false;
234 }
235
236 if (LocVT == MVT::v16i8 ||
237 LocVT == MVT::v8i16 ||
238 LocVT == MVT::v4i32 ||
239 LocVT == MVT::v4f32 ||
240 LocVT == MVT::v2f64 ||
241 LocVT == MVT::v2i64) {
242 int64_t Offset8 = State.AllocateStack(Size: 16, Alignment: Align(16));
243 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
244 return false;
245 }
246
247 if (LocVT == MVT::f128) {
248 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
249 int64_t Offset9 = State.AllocateStack(Size: 16, Alignment: Align(16));
250 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
251 return false;
252 }
253 }
254
255 return true; // CC didn't match.
256}
257
258
259bool llvm::CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT,
260 MVT LocVT, CCValAssign::LocInfo LocInfo,
261 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
262
263 if (!CC_PPC32_SVR4_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
264 return false;
265
266 return true; // CC didn't match.
267}
268
269
270static bool CC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
271 MVT LocVT, CCValAssign::LocInfo LocInfo,
272 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
273
274 if (CC_PPC_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
275 return false;
276
277 return true; // CC didn't match.
278}
279
280
281bool llvm::CC_PPC64_ELF(unsigned ValNo, MVT ValVT,
282 MVT LocVT, CCValAssign::LocInfo LocInfo,
283 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
284
285 if (State.getCallingConv() == CallingConv::AnyReg) {
286 if (!CC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
287 return false;
288 }
289
290 if (LocVT == MVT::i1) {
291 LocVT = MVT::i64;
292 if (ArgFlags.isSExt())
293 LocInfo = CCValAssign::SExt;
294 else if (ArgFlags.isZExt())
295 LocInfo = CCValAssign::ZExt;
296 else
297 LocInfo = CCValAssign::AExt;
298 }
299
300 if (LocVT == MVT::i8) {
301 LocVT = MVT::i64;
302 if (ArgFlags.isSExt())
303 LocInfo = CCValAssign::SExt;
304 else if (ArgFlags.isZExt())
305 LocInfo = CCValAssign::ZExt;
306 else
307 LocInfo = CCValAssign::AExt;
308 }
309
310 if (LocVT == MVT::i16) {
311 LocVT = MVT::i64;
312 if (ArgFlags.isSExt())
313 LocInfo = CCValAssign::SExt;
314 else if (ArgFlags.isZExt())
315 LocInfo = CCValAssign::ZExt;
316 else
317 LocInfo = CCValAssign::AExt;
318 }
319
320 if (LocVT == MVT::i32) {
321 LocVT = MVT::i64;
322 if (ArgFlags.isSExt())
323 LocInfo = CCValAssign::SExt;
324 else if (ArgFlags.isZExt())
325 LocInfo = CCValAssign::ZExt;
326 else
327 LocInfo = CCValAssign::AExt;
328 }
329
330 if (LocVT == MVT::i64) {
331 static const MCPhysReg RegList1[] = {
332 PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10
333 };
334 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
335 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
336 return false;
337 }
338 }
339
340 if (LocVT == MVT::f32 ||
341 LocVT == MVT::f64) {
342 if (!State.isVarArg()) {
343 if (CC_PPC64_ELF_Shadow_GPR_Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
344 return false;
345 }
346 }
347
348 if (LocVT == MVT::f32 ||
349 LocVT == MVT::f64) {
350 if (!State.isVarArg()) {
351 static const MCPhysReg RegList2[] = {
352 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
353 };
354 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
355 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
356 return false;
357 }
358 }
359 }
360
361 if (LocVT == MVT::f128) {
362 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
363 if (!State.isVarArg()) {
364 if (CC_PPC64_ELF_Shadow_GPR_Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
365 return false;
366 }
367 }
368 }
369
370 if (LocVT == MVT::f128) {
371 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
372 if (!State.isVarArg()) {
373 static const MCPhysReg RegList3[] = {
374 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
375 };
376 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
377 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
378 return false;
379 }
380 }
381 }
382 }
383
384 if (LocVT == MVT::v16i8 ||
385 LocVT == MVT::v8i16 ||
386 LocVT == MVT::v4i32 ||
387 LocVT == MVT::v2i64 ||
388 LocVT == MVT::v4f32 ||
389 LocVT == MVT::v2f64 ||
390 LocVT == MVT::v1i128) {
391 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
392 if (!State.isVarArg()) {
393 if (CC_PPC64_ELF_Shadow_GPR_Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
394 return false;
395 }
396 }
397 }
398
399 if (LocVT == MVT::v16i8 ||
400 LocVT == MVT::v8i16 ||
401 LocVT == MVT::v4i32 ||
402 LocVT == MVT::v2i64 ||
403 LocVT == MVT::v4f32 ||
404 LocVT == MVT::v2f64 ||
405 LocVT == MVT::v1i128) {
406 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
407 if (!State.isVarArg()) {
408 static const MCPhysReg RegList4[] = {
409 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
410 };
411 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
412 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
413 return false;
414 }
415 }
416 }
417 }
418
419 return true; // CC didn't match.
420}
421
422
423bool llvm::CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT,
424 MVT LocVT, CCValAssign::LocInfo LocInfo,
425 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
426
427 if (State.getCallingConv() == CallingConv::AnyReg) {
428 if (!CC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
429 return false;
430 }
431
432 if (LocVT == MVT::i1) {
433 LocVT = MVT::i64;
434 if (ArgFlags.isSExt())
435 LocInfo = CCValAssign::SExt;
436 else if (ArgFlags.isZExt())
437 LocInfo = CCValAssign::ZExt;
438 else
439 LocInfo = CCValAssign::AExt;
440 }
441
442 if (LocVT == MVT::i8) {
443 LocVT = MVT::i64;
444 if (ArgFlags.isSExt())
445 LocInfo = CCValAssign::SExt;
446 else if (ArgFlags.isZExt())
447 LocInfo = CCValAssign::ZExt;
448 else
449 LocInfo = CCValAssign::AExt;
450 }
451
452 if (LocVT == MVT::i16) {
453 LocVT = MVT::i64;
454 if (ArgFlags.isSExt())
455 LocInfo = CCValAssign::SExt;
456 else if (ArgFlags.isZExt())
457 LocInfo = CCValAssign::ZExt;
458 else
459 LocInfo = CCValAssign::AExt;
460 }
461
462 if (LocVT == MVT::i32) {
463 LocVT = MVT::i64;
464 if (ArgFlags.isSExt())
465 LocInfo = CCValAssign::SExt;
466 else if (ArgFlags.isZExt())
467 LocInfo = CCValAssign::ZExt;
468 else
469 LocInfo = CCValAssign::AExt;
470 }
471
472 if (LocVT == MVT::i64) {
473 static const MCPhysReg RegList1[] = {
474 PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10
475 };
476 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
477 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
478 return false;
479 }
480 }
481
482 if (LocVT == MVT::f32 ||
483 LocVT == MVT::f64) {
484 static const MCPhysReg RegList2[] = {
485 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
486 };
487 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
488 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
489 return false;
490 }
491 }
492
493 return true; // CC didn't match.
494}
495
496
497bool llvm::RetCC_PPC(unsigned ValNo, MVT ValVT,
498 MVT LocVT, CCValAssign::LocInfo LocInfo,
499 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
500
501 if (State.getCallingConv() == CallingConv::AnyReg) {
502 if (!RetCC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
503 return false;
504 }
505
506 if (LocVT == MVT::i32 ||
507 LocVT == MVT::i1) {
508 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().isPPC64()) {
509 LocVT = MVT::i64;
510 if (ArgFlags.isSExt())
511 LocInfo = CCValAssign::SExt;
512 else if (ArgFlags.isZExt())
513 LocInfo = CCValAssign::ZExt;
514 else
515 LocInfo = CCValAssign::AExt;
516 }
517 }
518
519 if (LocVT == MVT::i1) {
520 if (!State.getMachineFunction().getSubtarget<PPCSubtarget>().isPPC64()) {
521 LocVT = MVT::i32;
522 if (ArgFlags.isSExt())
523 LocInfo = CCValAssign::SExt;
524 else if (ArgFlags.isZExt())
525 LocInfo = CCValAssign::ZExt;
526 else
527 LocInfo = CCValAssign::AExt;
528 }
529 }
530
531 if (LocVT == MVT::i32) {
532 static const MCPhysReg RegList1[] = {
533 PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
534 };
535 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
536 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
537 return false;
538 }
539 }
540
541 if (LocVT == MVT::i64) {
542 static const MCPhysReg RegList2[] = {
543 PPC::X3, PPC::X4, PPC::X5, PPC::X6
544 };
545 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
546 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
547 return false;
548 }
549 }
550
551 if (LocVT == MVT::i128) {
552 static const MCPhysReg RegList3[] = {
553 PPC::X3, PPC::X4, PPC::X5, PPC::X6
554 };
555 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
556 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
557 return false;
558 }
559 }
560
561 if (!State.getMachineFunction().getSubtarget<PPCSubtarget>().hasSPE()) {
562 if (LocVT == MVT::f32) {
563 static const MCPhysReg RegList4[] = {
564 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
565 };
566 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
567 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
568 return false;
569 }
570 }
571 }
572
573 if (!State.getMachineFunction().getSubtarget<PPCSubtarget>().hasSPE()) {
574 if (LocVT == MVT::f64) {
575 static const MCPhysReg RegList5[] = {
576 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
577 };
578 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
579 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
580 return false;
581 }
582 }
583 }
584
585 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasSPE()) {
586 if (LocVT == MVT::f32) {
587 static const MCPhysReg RegList6[] = {
588 PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
589 };
590 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
591 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
592 return false;
593 }
594 }
595 }
596
597 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasSPE()) {
598 if (LocVT == MVT::f64) {
599 if (CC_PPC32_SPE_RetF64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
600 return false;
601 }
602 }
603
604 if (LocVT == MVT::f128) {
605 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
606 static const MCPhysReg RegList7[] = {
607 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9
608 };
609 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
610 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
611 return false;
612 }
613 }
614 }
615
616 if (LocVT == MVT::v16i8 ||
617 LocVT == MVT::v8i16 ||
618 LocVT == MVT::v4i32 ||
619 LocVT == MVT::v2i64 ||
620 LocVT == MVT::v1i128 ||
621 LocVT == MVT::v4f32 ||
622 LocVT == MVT::v2f64) {
623 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
624 static const MCPhysReg RegList8[] = {
625 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9
626 };
627 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
628 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
629 return false;
630 }
631 }
632 }
633
634 return true; // CC didn't match.
635}
636
637
638static bool RetCC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
639 MVT LocVT, CCValAssign::LocInfo LocInfo,
640 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
641
642 if (CC_PPC_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
643 return false;
644
645 return true; // CC didn't match.
646}
647
648
649bool llvm::RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT,
650 MVT LocVT, CCValAssign::LocInfo LocInfo,
651 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
652
653 if (State.getCallingConv() == CallingConv::AnyReg) {
654 if (!RetCC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
655 return false;
656 }
657
658 if (LocVT == MVT::i1) {
659 LocVT = MVT::i64;
660 if (ArgFlags.isSExt())
661 LocInfo = CCValAssign::SExt;
662 else if (ArgFlags.isZExt())
663 LocInfo = CCValAssign::ZExt;
664 else
665 LocInfo = CCValAssign::AExt;
666 }
667
668 if (LocVT == MVT::i8) {
669 LocVT = MVT::i64;
670 if (ArgFlags.isSExt())
671 LocInfo = CCValAssign::SExt;
672 else if (ArgFlags.isZExt())
673 LocInfo = CCValAssign::ZExt;
674 else
675 LocInfo = CCValAssign::AExt;
676 }
677
678 if (LocVT == MVT::i16) {
679 LocVT = MVT::i64;
680 if (ArgFlags.isSExt())
681 LocInfo = CCValAssign::SExt;
682 else if (ArgFlags.isZExt())
683 LocInfo = CCValAssign::ZExt;
684 else
685 LocInfo = CCValAssign::AExt;
686 }
687
688 if (LocVT == MVT::i32) {
689 LocVT = MVT::i64;
690 if (ArgFlags.isSExt())
691 LocInfo = CCValAssign::SExt;
692 else if (ArgFlags.isZExt())
693 LocInfo = CCValAssign::ZExt;
694 else
695 LocInfo = CCValAssign::AExt;
696 }
697
698 if (LocVT == MVT::i64) {
699 static const MCPhysReg RegList1[] = {
700 PPC::X3, PPC::X4, PPC::X5, PPC::X6
701 };
702 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
703 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
704 return false;
705 }
706 }
707
708 if (LocVT == MVT::i128) {
709 static const MCPhysReg RegList2[] = {
710 PPC::X3, PPC::X4, PPC::X5, PPC::X6
711 };
712 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
713 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
714 return false;
715 }
716 }
717
718 if (LocVT == MVT::f32) {
719 static const MCPhysReg RegList3[] = {
720 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
721 };
722 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
723 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
724 return false;
725 }
726 }
727
728 if (LocVT == MVT::f64) {
729 static const MCPhysReg RegList4[] = {
730 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
731 };
732 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
733 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
734 return false;
735 }
736 }
737
738 if (LocVT == MVT::f128) {
739 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
740 static const MCPhysReg RegList5[] = {
741 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9
742 };
743 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
744 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
745 return false;
746 }
747 }
748 }
749
750 if (LocVT == MVT::v16i8 ||
751 LocVT == MVT::v8i16 ||
752 LocVT == MVT::v4i32 ||
753 LocVT == MVT::v2i64 ||
754 LocVT == MVT::v1i128 ||
755 LocVT == MVT::v4f32 ||
756 LocVT == MVT::v2f64) {
757 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
758 static const MCPhysReg RegList6[] = {
759 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9
760 };
761 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
762 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
763 return false;
764 }
765 }
766 }
767
768 return true; // CC didn't match.
769}
770
771
772bool llvm::RetCC_PPC_Cold(unsigned ValNo, MVT ValVT,
773 MVT LocVT, CCValAssign::LocInfo LocInfo,
774 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
775
776 if (LocVT == MVT::i32 ||
777 LocVT == MVT::i1) {
778 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().isPPC64()) {
779 LocVT = MVT::i64;
780 if (ArgFlags.isSExt())
781 LocInfo = CCValAssign::SExt;
782 else if (ArgFlags.isZExt())
783 LocInfo = CCValAssign::ZExt;
784 else
785 LocInfo = CCValAssign::AExt;
786 }
787 }
788
789 if (LocVT == MVT::i1) {
790 if (!State.getMachineFunction().getSubtarget<PPCSubtarget>().isPPC64()) {
791 LocVT = MVT::i32;
792 if (ArgFlags.isSExt())
793 LocInfo = CCValAssign::SExt;
794 else if (ArgFlags.isZExt())
795 LocInfo = CCValAssign::ZExt;
796 else
797 LocInfo = CCValAssign::AExt;
798 }
799 }
800
801 if (LocVT == MVT::i32) {
802 if (MCRegister Reg = State.AllocateReg(Reg: PPC::R3)) {
803 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
804 return false;
805 }
806 }
807
808 if (LocVT == MVT::i64) {
809 if (MCRegister Reg = State.AllocateReg(Reg: PPC::X3)) {
810 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
811 return false;
812 }
813 }
814
815 if (LocVT == MVT::i128) {
816 if (MCRegister Reg = State.AllocateReg(Reg: PPC::X3)) {
817 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
818 return false;
819 }
820 }
821
822 if (LocVT == MVT::f32) {
823 if (MCRegister Reg = State.AllocateReg(Reg: PPC::F1)) {
824 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
825 return false;
826 }
827 }
828
829 if (LocVT == MVT::f64) {
830 if (MCRegister Reg = State.AllocateReg(Reg: PPC::F1)) {
831 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
832 return false;
833 }
834 }
835
836 if (LocVT == MVT::f128) {
837 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
838 if (MCRegister Reg = State.AllocateReg(Reg: PPC::V2)) {
839 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
840 return false;
841 }
842 }
843 }
844
845 if (LocVT == MVT::v16i8 ||
846 LocVT == MVT::v8i16 ||
847 LocVT == MVT::v4i32 ||
848 LocVT == MVT::v2i64 ||
849 LocVT == MVT::v1i128 ||
850 LocVT == MVT::v4f32 ||
851 LocVT == MVT::v2f64) {
852 if (State.getMachineFunction().getSubtarget<PPCSubtarget>().hasAltivec()) {
853 if (MCRegister Reg = State.AllocateReg(Reg: PPC::V2)) {
854 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
855 return false;
856 }
857 }
858 }
859
860 return true; // CC didn't match.
861}
862
863#endif // GET_CALLING_CONV_IMPL
864
865#ifdef GET_CC_REGISTER_LISTS
866#undef GET_CC_REGISTER_LISTS
867
868const MCRegister CC_PPC32_SVR4_ArgRegs[] = { PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9 };
869const MCRegister CC_PPC32_SVR4_ByVal_ArgRegs[] = { 0 };
870const MCRegister CC_PPC32_SVR4_Common_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::R10, PPC::R11, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9 };
871const MCRegister CC_PPC32_SVR4_VarArg_ArgRegs[] = { 0 };
872const MCRegister CC_PPC64_AnyReg_ArgRegs[] = { 0 };
873const MCRegister CC_PPC64_ELF_ArgRegs[] = { PPC::F1, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::X10, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9 };
874const MCRegister CC_PPC64_ELF_FIS_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::X10, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9 };
875const MCRegister RetCC_PPC_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::R10, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::X3, PPC::X4, PPC::X5, PPC::X6 };
876const MCRegister RetCC_PPC64_AnyReg_ArgRegs[] = { 0 };
877const MCRegister RetCC_PPC64_ELF_FIS_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::X3, PPC::X4, PPC::X5, PPC::X6 };
878const MCRegister RetCC_PPC_Cold_ArgRegs[] = { PPC::F1, PPC::R3, PPC::V2, PPC::X3 };
879
880#endif // GET_CC_REGISTER_LISTS
881
882