1//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14#define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15
16#include "PPCFrameLowering.h"
17#include "PPCISelLowering.h"
18#include "PPCInstrInfo.h"
19#include "llvm/CodeGen/GlobalISel/CallLowering.h"
20#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
21#include "llvm/CodeGen/RegisterBankInfo.h"
22#include "llvm/CodeGen/TargetSubtargetInfo.h"
23#include "llvm/IR/DataLayout.h"
24#include "llvm/MC/MCInstrItineraries.h"
25#include "llvm/TargetParser/Triple.h"
26
27#define GET_SUBTARGETINFO_HEADER
28#include "PPCGenSubtargetInfo.inc"
29
30// GCC #defines PPC on Linux but we use it as our namespace name
31#undef PPC
32
33namespace llvm {
34class SelectionDAGTargetInfo;
35class StringRef;
36
37namespace PPC {
38 // -m directive values.
39enum {
40 DIR_NONE,
41 DIR_32,
42 DIR_440,
43 DIR_601,
44 DIR_602,
45 DIR_603,
46 DIR_7400,
47 DIR_750,
48 DIR_970,
49 DIR_A2,
50 DIR_E500,
51 DIR_E500mc,
52 DIR_E5500,
53 DIR_PWR3,
54 DIR_PWR4,
55 DIR_PWR5,
56 DIR_PWR5X,
57 DIR_PWR6,
58 DIR_PWR6X,
59 DIR_PWR7,
60 DIR_PWR8,
61 DIR_PWR9,
62 DIR_PWR10,
63 DIR_PWR11,
64 DIR_PWR_FUTURE,
65 DIR_64
66};
67}
68
69class GlobalValue;
70
71class PPCSubtarget : public PPCGenSubtargetInfo {
72public:
73 enum POPCNTDKind {
74 POPCNTD_Unavailable,
75 POPCNTD_Slow,
76 POPCNTD_Fast
77 };
78
79protected:
80 /// stackAlignment - The minimum alignment known to hold of the stack frame on
81 /// entry to the function and which must be maintained by every function.
82 Align StackAlignment;
83
84 /// Selected instruction itineraries (one entry per itinerary class.)
85 InstrItineraryData InstrItins;
86
87// Bool members corresponding to the SubtargetFeatures defined in tablegen.
88#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
89 bool ATTRIBUTE = DEFAULT;
90#include "PPCGenSubtargetInfo.inc"
91
92 /// Which cpu directive was used.
93 unsigned CPUDirective;
94
95 bool IsLittleEndian;
96
97 /// The selected ABI variant.
98 PPCABI TargetABI = PPC_ABI_UNKNOWN;
99
100 POPCNTDKind HasPOPCNTD;
101
102 const PPCTargetMachine &TM;
103 PPCFrameLowering FrameLowering;
104 PPCInstrInfo InstrInfo;
105 PPCTargetLowering TLInfo;
106
107 // SelectionDAGISel related APIs.
108 std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
109
110 /// GlobalISel related APIs.
111 std::unique_ptr<CallLowering> CallLoweringInfo;
112 std::unique_ptr<LegalizerInfo> Legalizer;
113 std::unique_ptr<RegisterBankInfo> RegBankInfo;
114 std::unique_ptr<InstructionSelector> InstSelector;
115
116public:
117 /// This constructor initializes the data members to match that
118 /// of the specified triple.
119 ///
120 PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
121 StringRef ABIName, const PPCTargetMachine &TM);
122
123 ~PPCSubtarget() override;
124
125 /// ParseSubtargetFeatures - Parses features string setting specified
126 /// subtarget options. Definition of function is auto generated by tblgen.
127 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
128
129 /// getStackAlignment - Returns the minimum alignment known to hold of the
130 /// stack frame on entry to the function and which must be maintained by every
131 /// function for this subtarget.
132 Align getStackAlignment() const { return StackAlignment; }
133
134 /// getCPUDirective - Returns the -m directive specified for the cpu.
135 ///
136 unsigned getCPUDirective() const { return CPUDirective; }
137
138 /// getInstrItins - Return the instruction itineraries based on subtarget
139 /// selection.
140 const InstrItineraryData *getInstrItineraryData() const override {
141 return &InstrItins;
142 }
143
144 const PPCFrameLowering *getFrameLowering() const override {
145 return &FrameLowering;
146 }
147 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
148 const PPCTargetLowering *getTargetLowering() const override {
149 return &TLInfo;
150 }
151
152 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
153
154 const PPCRegisterInfo *getRegisterInfo() const override {
155 return &getInstrInfo()->getRegisterInfo();
156 }
157 const PPCTargetMachine &getTargetMachine() const { return TM; }
158
159 /// initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and
160 /// feature string so that we can use initializer lists for subtarget
161 /// initialization.
162 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU,
163 StringRef TuneCPU,
164 StringRef FS);
165
166private:
167 void initializeEnvironment();
168 void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
169
170public:
171 // useSoftFloat - Return true if soft-float option is turned on.
172 bool useSoftFloat() const {
173 if (isAIXABI() && !HasHardFloat)
174 report_fatal_error(reason: "soft-float is not yet supported on AIX.");
175 return !HasHardFloat;
176 }
177
178 // isLittleEndian - True if generating little-endian code
179 bool isLittleEndian() const { return IsLittleEndian; }
180
181// Getters for SubtargetFeatures defined in tablegen.
182#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
183 bool GETTER() const { return ATTRIBUTE; }
184#include "PPCGenSubtargetInfo.inc"
185
186 Align getPlatformStackAlignment() const {
187 return Align(16);
188 }
189
190 unsigned getRedZoneSize() const {
191 if (isPPC64())
192 // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
193 return 288;
194
195 // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
196 // PPC32 SVR4ABI has no redzone.
197 return isAIXABI() ? 220 : 0;
198 }
199
200 bool needsSwapsForVSXMemOps() const {
201 return hasVSX() && isLittleEndian() && !hasP9Vector();
202 }
203
204 POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
205
206 bool isTargetELF() const { return getTargetTriple().isOSBinFormatELF(); }
207 bool isTargetMachO() const { return getTargetTriple().isOSBinFormatMachO(); }
208 bool isTargetLinux() const { return getTargetTriple().isOSLinux(); }
209
210 bool isAIXABI() const { return getTargetTriple().isOSAIX(); }
211 bool isSVR4ABI() const { return !isAIXABI(); }
212 bool isELFv2ABI() const;
213
214 /// Returns true when the AIX extended Altivec ABI ("vec-extabi") is in
215 /// effect, allowing use of the nonvolatile vector registers.
216 bool isAIXExtendedAltivecABI() const {
217 return TargetABI == PPC_ABI_AIX_EXTABI;
218 }
219
220 bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
221 bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
222 bool isUsingPCRelativeCalls() const;
223
224 /// Originally, this function return hasISEL(). Now we always enable it,
225 /// but may expand the ISEL instruction later.
226 bool enableEarlyIfConversion() const override { return true; }
227
228 /// Scheduling customization.
229 bool enableMachineScheduler() const override;
230 /// Pipeliner customization.
231 bool enableMachinePipeliner() const override;
232 /// Machine Pipeliner customization
233 bool useDFAforSMS() const override;
234 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
235 bool enablePostRAScheduler() const override;
236 AntiDepBreakMode getAntiDepBreakMode() const override;
237 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
238
239 void overrideSchedPolicy(MachineSchedPolicy &Policy,
240 const SchedRegion &Region) const override;
241
242 bool useAA() const override;
243
244 bool enableSubRegLiveness() const override;
245
246 bool enableSpillageCopyElimination() const override { return true; }
247
248 /// True if the GV will be accessed via an indirect symbol.
249 bool isGVIndirectSymbol(const GlobalValue *GV) const;
250
251 MVT getScalarIntVT() const { return isPPC64() ? MVT::i64 : MVT::i32; }
252
253 /// Calculates the effective code model for argument GV.
254 CodeModel::Model getCodeModel(const TargetMachine &TM,
255 const GlobalValue *GV) const;
256
257 /// True if the ABI is descriptor based.
258 bool usesFunctionDescriptors() const {
259 // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
260 // v1 ABI uses descriptors.
261 return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
262 }
263
264 unsigned descriptorTOCAnchorOffset() const {
265 assert(usesFunctionDescriptors() &&
266 "Should only be called when the target uses descriptors.");
267 return IsPPC64 ? 8 : 4;
268 }
269
270 unsigned descriptorEnvironmentPointerOffset() const {
271 assert(usesFunctionDescriptors() &&
272 "Should only be called when the target uses descriptors.");
273 return IsPPC64 ? 16 : 8;
274 }
275
276 MCRegister getEnvironmentPointerRegister() const {
277 assert(usesFunctionDescriptors() &&
278 "Should only be called when the target uses descriptors.");
279 return IsPPC64 ? PPC::X11 : PPC::R11;
280 }
281
282 MCRegister getTOCPointerRegister() const {
283 assert((is64BitELFABI() || isAIXABI()) &&
284 "Should only be called when the target is a TOC based ABI.");
285 return IsPPC64 ? PPC::X2 : PPC::R2;
286 }
287
288 MCRegister getThreadPointerRegister() const {
289 assert((is64BitELFABI() || isAIXABI()) &&
290 "Should only be called for targets with a thread pointer register.");
291 return IsPPC64 ? PPC::X13 : PPC::R13;
292 }
293
294 MCRegister getStackPointerRegister() const {
295 return IsPPC64 ? PPC::X1 : PPC::R1;
296 }
297
298 MCRegister getGlueCodeDescriptorRegister() const {
299 return IsPPC64 ? PPC::X11 : PPC::R11;
300 }
301
302 bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
303
304 bool isPredictableSelectIsExpensive() const {
305 return PredictableSelectIsExpensive;
306 }
307
308 // Select allocation orders of GPRC and G8RC. It should be strictly consistent
309 // with corresponding AltOrders in PPCRegisterInfo.td.
310 unsigned getGPRAllocationOrderIdx() const {
311 if (is64BitELFABI())
312 return 1;
313 if (isAIXABI())
314 return 2;
315 return 0;
316 }
317
318 // GlobalISEL
319 const CallLowering *getCallLowering() const override;
320 const RegisterBankInfo *getRegBankInfo() const override;
321 const LegalizerInfo *getLegalizerInfo() const override;
322 InstructionSelector *getInstructionSelector() const override;
323};
324} // End llvm namespace
325
326#endif
327