1//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15
16#include "MCTargetDesc/PPCMCTargetDesc.h"
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "llvm/ADT/SmallSet.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21
22#define GET_INSTRINFO_HEADER
23#include "PPCGenInstrInfo.inc"
24
25namespace llvm {
26
27// Instructions that have an immediate form might be convertible to that
28// form if the correct input is a result of a load immediate. In order to
29// know whether the transformation is special, we might need to know some
30// of the details of the two forms.
31struct ImmInstrInfo {
32 // Is the immediate field in the immediate form signed or unsigned?
33 uint64_t SignedImm : 1;
34 // Does the immediate need to be a multiple of some value?
35 uint64_t ImmMustBeMultipleOf : 5;
36 // Is R0/X0 treated specially by the original r+r instruction?
37 // If so, in which operand?
38 uint64_t ZeroIsSpecialOrig : 3;
39 // Is R0/X0 treated specially by the new r+i instruction?
40 // If so, in which operand?
41 uint64_t ZeroIsSpecialNew : 3;
42 // Is the operation commutative?
43 uint64_t IsCommutative : 1;
44 // The operand number to check for add-immediate def.
45 uint64_t OpNoForForwarding : 3;
46 // The operand number for the immediate.
47 uint64_t ImmOpNo : 3;
48 // The opcode of the new instruction.
49 uint64_t ImmOpcode : 16;
50 // The size of the immediate.
51 uint64_t ImmWidth : 5;
52 // The immediate should be truncated to N bits.
53 uint64_t TruncateImmTo : 5;
54 // Is the instruction summing the operand
55 uint64_t IsSummingOperands : 1;
56};
57
58// Information required to convert an instruction to just a materialized
59// immediate.
60struct LoadImmediateInfo {
61 unsigned Imm : 16;
62 unsigned Is64Bit : 1;
63 unsigned SetCR : 1;
64};
65
66// Index into the OpcodesForSpill array.
67enum SpillOpcodeKey {
68 SOK_Int4Spill,
69 SOK_Int8Spill,
70 SOK_Float8Spill,
71 SOK_Float4Spill,
72 SOK_CRSpill,
73 SOK_CRBitSpill,
74 SOK_VRVectorSpill,
75 SOK_VSXVectorSpill,
76 SOK_VectorFloat8Spill,
77 SOK_VectorFloat4Spill,
78 SOK_SpillToVSR,
79 SOK_PairedVecSpill,
80 SOK_AccumulatorSpill,
81 SOK_UAccumulatorSpill,
82 SOK_WAccumulatorSpill,
83 SOK_DMRpSpill,
84 SOK_DMRSpill,
85 SOK_SPESpill,
86 SOK_PairedG8Spill,
87 SOK_LastOpcodeSpill // This must be last on the enum.
88};
89
90// PPC MachineCombiner patterns
91enum PPCMachineCombinerPattern : unsigned {
92 // These are patterns matched by the PowerPC to reassociate FMA chains.
93 REASSOC_XY_AMM_BMM = MachineCombinerPattern::TARGET_PATTERN_START,
94 REASSOC_XMM_AMM_BMM,
95
96 // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
97 // reduce register pressure.
98 REASSOC_XY_BCA,
99 REASSOC_XY_BAC,
100
101};
102
103// Define list of load and store spill opcodes.
104#define NoInstr PPC::INSTRUCTION_LIST_END
105#define Pwr8LoadOpcodes \
106 {PPC::LWZ, \
107 PPC::LD, \
108 PPC::LFD, \
109 PPC::LFS, \
110 PPC::RESTORE_CR, \
111 PPC::RESTORE_CRBIT, \
112 PPC::LVX, \
113 PPC::LXVD2X, \
114 PPC::LXSDX, \
115 PPC::LXSSPX, \
116 PPC::SPILLTOVSR_LD, \
117 NoInstr, \
118 NoInstr, \
119 NoInstr, \
120 NoInstr, \
121 NoInstr, \
122 NoInstr, \
123 PPC::EVLDD, \
124 PPC::RESTORE_QUADWORD}
125
126#define Pwr9LoadOpcodes \
127 {PPC::LWZ, \
128 PPC::LD, \
129 PPC::LFD, \
130 PPC::LFS, \
131 PPC::RESTORE_CR, \
132 PPC::RESTORE_CRBIT, \
133 PPC::LVX, \
134 PPC::LXV, \
135 PPC::DFLOADf64, \
136 PPC::DFLOADf32, \
137 PPC::SPILLTOVSR_LD, \
138 NoInstr, \
139 NoInstr, \
140 NoInstr, \
141 NoInstr, \
142 NoInstr, \
143 NoInstr, \
144 NoInstr, \
145 PPC::RESTORE_QUADWORD}
146
147#define Pwr10LoadOpcodes \
148 {PPC::LWZ, \
149 PPC::LD, \
150 PPC::LFD, \
151 PPC::LFS, \
152 PPC::RESTORE_CR, \
153 PPC::RESTORE_CRBIT, \
154 PPC::LVX, \
155 PPC::LXV, \
156 PPC::DFLOADf64, \
157 PPC::DFLOADf32, \
158 PPC::SPILLTOVSR_LD, \
159 PPC::LXVP, \
160 PPC::RESTORE_ACC, \
161 PPC::RESTORE_UACC, \
162 NoInstr, \
163 NoInstr, \
164 NoInstr, \
165 NoInstr, \
166 PPC::RESTORE_QUADWORD}
167
168#define FutureLoadOpcodes \
169 {PPC::LWZ, \
170 PPC::LD, \
171 PPC::LFD, \
172 PPC::LFS, \
173 PPC::RESTORE_CR, \
174 PPC::RESTORE_CRBIT, \
175 PPC::LVX, \
176 PPC::LXV, \
177 PPC::DFLOADf64, \
178 PPC::DFLOADf32, \
179 PPC::SPILLTOVSR_LD, \
180 PPC::LXVP, \
181 PPC::RESTORE_ACC, \
182 PPC::RESTORE_UACC, \
183 PPC::RESTORE_WACC, \
184 PPC::RESTORE_DMRP, \
185 PPC::RESTORE_DMR, \
186 NoInstr, \
187 PPC::RESTORE_QUADWORD}
188
189#define Pwr8StoreOpcodes \
190 {PPC::STW, \
191 PPC::STD, \
192 PPC::STFD, \
193 PPC::STFS, \
194 PPC::SPILL_CR, \
195 PPC::SPILL_CRBIT, \
196 PPC::STVX, \
197 PPC::STXVD2X, \
198 PPC::STXSDX, \
199 PPC::STXSSPX, \
200 PPC::SPILLTOVSR_ST, \
201 NoInstr, \
202 NoInstr, \
203 NoInstr, \
204 NoInstr, \
205 NoInstr, \
206 NoInstr, \
207 PPC::EVSTDD, \
208 PPC::SPILL_QUADWORD}
209
210#define Pwr9StoreOpcodes \
211 {PPC::STW, \
212 PPC::STD, \
213 PPC::STFD, \
214 PPC::STFS, \
215 PPC::SPILL_CR, \
216 PPC::SPILL_CRBIT, \
217 PPC::STVX, \
218 PPC::STXV, \
219 PPC::DFSTOREf64, \
220 PPC::DFSTOREf32, \
221 PPC::SPILLTOVSR_ST, \
222 NoInstr, \
223 NoInstr, \
224 NoInstr, \
225 NoInstr, \
226 NoInstr, \
227 NoInstr, \
228 NoInstr, \
229 PPC::SPILL_QUADWORD}
230
231#define Pwr10StoreOpcodes \
232 {PPC::STW, \
233 PPC::STD, \
234 PPC::STFD, \
235 PPC::STFS, \
236 PPC::SPILL_CR, \
237 PPC::SPILL_CRBIT, \
238 PPC::STVX, \
239 PPC::STXV, \
240 PPC::DFSTOREf64, \
241 PPC::DFSTOREf32, \
242 PPC::SPILLTOVSR_ST, \
243 PPC::STXVP, \
244 PPC::SPILL_ACC, \
245 PPC::SPILL_UACC, \
246 NoInstr, \
247 NoInstr, \
248 NoInstr, \
249 NoInstr, \
250 PPC::SPILL_QUADWORD}
251
252#define FutureStoreOpcodes \
253 {PPC::STW, \
254 PPC::STD, \
255 PPC::STFD, \
256 PPC::STFS, \
257 PPC::SPILL_CR, \
258 PPC::SPILL_CRBIT, \
259 PPC::STVX, \
260 PPC::STXV, \
261 PPC::DFSTOREf64, \
262 PPC::DFSTOREf32, \
263 PPC::SPILLTOVSR_ST, \
264 PPC::STXVP, \
265 PPC::SPILL_ACC, \
266 PPC::SPILL_UACC, \
267 PPC::SPILL_WACC, \
268 PPC::SPILL_DMRP, \
269 PPC::SPILL_DMR, \
270 NoInstr, \
271 PPC::SPILL_QUADWORD}
272
273// Initialize arrays for load and store spill opcodes on supported subtargets.
274#define StoreOpcodesForSpill \
275 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }
276#define LoadOpcodesForSpill \
277 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }
278
279class PPCSubtarget;
280class PPCInstrInfo : public PPCGenInstrInfo {
281 const PPCSubtarget &Subtarget;
282 const PPCRegisterInfo RI;
283 const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
284 StoreOpcodesForSpill;
285 const unsigned LoadSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
286 LoadOpcodesForSpill;
287
288 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
289 int FrameIdx, const TargetRegisterClass *RC,
290 SmallVectorImpl<MachineInstr *> &NewMIs) const;
291 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
292 unsigned DestReg, int FrameIdx,
293 const TargetRegisterClass *RC,
294 SmallVectorImpl<MachineInstr *> &NewMIs) const;
295
296 // Replace the instruction with single LI if possible. \p DefMI must be LI or
297 // LI8.
298 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
299 unsigned OpNoForForwarding, MachineInstr **KilledDef,
300 SmallSet<Register, 4> *RegsToUpdate = nullptr) const;
301 // If the inst is imm-form and its register operand is produced by a ADDI, put
302 // the imm into the inst directly and remove the ADDI if possible.
303 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
304 unsigned OpNoForForwarding) const;
305 // If the inst is x-form and has imm-form and one of its operand is produced
306 // by a LI, put the imm into the inst directly and remove the LI if possible.
307 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
308 unsigned ConstantOpNo,
309 MachineInstr &DefMI) const;
310 // If the inst is x-form and has imm-form and one of its operand is produced
311 // by an add-immediate, try to transform it when possible.
312 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
313 unsigned ConstantOpNo, MachineInstr &DefMI,
314 bool KillDefMI) const;
315 // Try to find that, if the instruction 'MI' contains any operand that
316 // could be forwarded from some inst that feeds it. If yes, return the
317 // Def of that operand. And OpNoForForwarding is the operand index in
318 // the 'MI' for that 'Def'. If we see another use of this Def between
319 // the Def and the MI, SeenIntermediateUse becomes 'true'.
320 MachineInstr *getForwardingDefMI(MachineInstr &MI,
321 unsigned &OpNoForForwarding,
322 bool &SeenIntermediateUse) const;
323
324 // Can the user MI have it's source at index \p OpNoForForwarding
325 // forwarded from an add-immediate that feeds it?
326 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
327 unsigned OpNoForForwarding) const;
328 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
329 const ImmInstrInfo &III,
330 MachineOperand *&ImmMO,
331 MachineOperand *&RegMO) const;
332 bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
333 const MachineInstr &DefMI,
334 const ImmInstrInfo &III,
335 int64_t &Imm,
336 int64_t BaseImm = 0) const;
337 bool isRegElgibleForForwarding(const MachineOperand &RegMO,
338 const MachineInstr &DefMI,
339 const MachineInstr &MI, bool KillDefMI,
340 bool &IsFwdFeederRegKilled,
341 bool &SeenIntermediateUse) const;
342 unsigned getSpillTarget() const;
343 ArrayRef<unsigned> getStoreOpcodesForSpillArray() const;
344 ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
345 unsigned getSpillIndex(const TargetRegisterClass *RC) const;
346 int16_t getFMAOpIdxInfo(unsigned Opcode) const;
347 void reassociateFMA(MachineInstr &Root, unsigned Pattern,
348 SmallVectorImpl<MachineInstr *> &InsInstrs,
349 SmallVectorImpl<MachineInstr *> &DelInstrs,
350 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const;
351 Register
352 generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
353 SmallVectorImpl<MachineInstr *> &InsInstrs) const;
354 virtual void anchor();
355
356protected:
357 /// Commutes the operands in the given instruction.
358 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
359 ///
360 /// Do not call this method for a non-commutable instruction or for
361 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
362 /// Even though the instruction is commutable, the method may still
363 /// fail to commute the operands, null pointer is returned in such cases.
364 ///
365 /// For example, we can commute rlwimi instructions, but only if the
366 /// rotate amt is zero. We also have to munge the immediates a bit.
367 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
368 unsigned OpIdx1,
369 unsigned OpIdx2) const override;
370
371public:
372 explicit PPCInstrInfo(const PPCSubtarget &STI);
373
374 bool isLoadFromConstantPool(MachineInstr *I) const;
375 const Constant *getConstantFromConstantPool(MachineInstr *I) const;
376
377 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
378 /// such, whenever a client has an instance of instruction info, it should
379 /// always be able to get register info as well (through this method).
380 ///
381 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
382
383 const TargetRegisterClass *
384 getInlineAsmMemoryOperandRegClass(InlineAsm::ConstraintCode C) const override;
385
386 bool isXFormMemOp(unsigned Opcode) const {
387 return get(Opcode).TSFlags & PPCII::XFormMemOp;
388 }
389 bool isPrefixed(unsigned Opcode) const {
390 return get(Opcode).TSFlags & PPCII::Prefixed;
391 }
392 bool isSExt32To64(unsigned Opcode) const {
393 return get(Opcode).TSFlags & PPCII::SExt32To64;
394 }
395 bool isZExt32To64(unsigned Opcode) const {
396 return get(Opcode).TSFlags & PPCII::ZExt32To64;
397 }
398 bool isMemriOp(unsigned Opcode) const {
399 return get(Opcode).TSFlags & PPCII::MemriOp;
400 }
401
402 static bool isSameClassPhysRegCopy(unsigned Opcode) {
403 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
404 PPC::VOR, PPC::XXLOR, PPC::XXLORf,
405 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
406 PPC::EVOR, -1U};
407 for (int i = 0; CopyOpcodes[i] != -1U; i++)
408 if (Opcode == CopyOpcodes[i])
409 return true;
410 return false;
411 }
412
413 static bool hasPCRelFlag(unsigned TF) {
414 return TF == PPCII::MO_PCREL_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
415 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
416 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
417 TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG ||
418 TF == PPCII::MO_GOT_PCREL_FLAG;
419 }
420
421 static bool hasGOTFlag(unsigned TF) {
422 return TF == PPCII::MO_GOT_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
423 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
424 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
425 TF == PPCII::MO_GOT_PCREL_FLAG;
426 }
427
428 static bool hasTLSFlag(unsigned TF) {
429 return TF == PPCII::MO_TLSGD_FLAG || TF == PPCII::MO_TPREL_FLAG ||
430 TF == PPCII::MO_TLSLD_FLAG || TF == PPCII::MO_TLSGDM_FLAG ||
431 TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
432 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
433 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG || TF == PPCII::MO_TPREL_LO ||
434 TF == PPCII::MO_TPREL_HA || TF == PPCII::MO_DTPREL_LO ||
435 TF == PPCII::MO_TLSLD_LO || TF == PPCII::MO_TLS ||
436 TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG;
437 }
438
439 ScheduleHazardRecognizer *
440 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
441 const ScheduleDAG *DAG) const override;
442 ScheduleHazardRecognizer *
443 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
444 const ScheduleDAG *DAG) const override;
445
446 unsigned getInstrLatency(const InstrItineraryData *ItinData,
447 const MachineInstr &MI,
448 unsigned *PredCost = nullptr) const override;
449
450 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
451 const MachineInstr &DefMI,
452 unsigned DefIdx,
453 const MachineInstr &UseMI,
454 unsigned UseIdx) const override;
455 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
456 SDNode *DefNode, unsigned DefIdx,
457 SDNode *UseNode,
458 unsigned UseIdx) const override {
459 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
460 UseNode, UseIdx);
461 }
462
463 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
464 const MachineInstr &DefMI,
465 unsigned DefIdx) const override {
466 // Machine LICM should hoist all instructions in low-register-pressure
467 // situations; none are sufficiently free to justify leaving in a loop
468 // body.
469 return false;
470 }
471
472 bool useMachineCombiner() const override {
473 return true;
474 }
475
476 /// When getMachineCombinerPatterns() finds patterns, this function generates
477 /// the instructions that could replace the original code sequence
478 void genAlternativeCodeSequence(
479 MachineInstr &Root, unsigned Pattern,
480 SmallVectorImpl<MachineInstr *> &InsInstrs,
481 SmallVectorImpl<MachineInstr *> &DelInstrs,
482 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
483
484 /// Return true when there is potentially a faster code sequence for a fma
485 /// chain ending in \p Root. All potential patterns are output in the \p
486 /// P array.
487 bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
488 bool DoRegPressureReduce) const;
489
490 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
491
492 /// Return true when there is potentially a faster code sequence
493 /// for an instruction chain ending in <Root>. All potential patterns are
494 /// output in the <Pattern> array.
495 bool getMachineCombinerPatterns(MachineInstr &Root,
496 SmallVectorImpl<unsigned> &Patterns,
497 bool DoRegPressureReduce) const override;
498
499 /// On PowerPC, we leverage machine combiner pass to reduce register pressure
500 /// when the register pressure is high for one BB.
501 /// Return true if register pressure for \p MBB is high and ABI is supported
502 /// to reduce register pressure. Otherwise return false.
503 bool shouldReduceRegisterPressure(
504 const MachineBasicBlock *MBB,
505 const RegisterClassInfo *RegClassInfo) const override;
506
507 /// Fixup the placeholders we put in genAlternativeCodeSequence() for
508 /// MachineCombiner.
509 void
510 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
511 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
512
513 bool isAssociativeAndCommutative(const MachineInstr &Inst,
514 bool Invert) const override;
515
516 /// On PowerPC, we try to reassociate FMA chain which will increase
517 /// instruction size. Set extension resource length limit to 1 for edge case.
518 /// Resource Length is calculated by scaled resource usage in getCycles().
519 /// Because of the division in getCycles(), it returns different cycles due to
520 /// legacy scaled resource usage. So new resource length may be same with
521 /// legacy or 1 bigger than legacy.
522 /// We need to execlude the 1 bigger case even the resource length is not
523 /// perserved for more FMA chain reassociations on PowerPC.
524 int getExtendResourceLenLimit() const override { return 1; }
525
526 // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
527 // and clears nuw, nsw, and exact flags.
528 using TargetInstrInfo::setSpecialOperandAttr;
529 void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const;
530
531 bool isCoalescableExtInstr(const MachineInstr &MI,
532 Register &SrcReg, Register &DstReg,
533 unsigned &SubIdx) const override;
534 Register isLoadFromStackSlot(const MachineInstr &MI,
535 int &FrameIndex) const override;
536 bool isReMaterializableImpl(const MachineInstr &MI) const override;
537 Register isStoreToStackSlot(const MachineInstr &MI,
538 int &FrameIndex) const override;
539
540 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
541 unsigned &SrcOpIdx2) const override;
542
543 void insertNoop(MachineBasicBlock &MBB,
544 MachineBasicBlock::iterator MI) const override;
545
546
547 // Branch analysis.
548 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
549 MachineBasicBlock *&FBB,
550 SmallVectorImpl<MachineOperand> &Cond,
551 bool AllowModify) const override;
552 unsigned removeBranch(MachineBasicBlock &MBB,
553 int *BytesRemoved = nullptr) const override;
554 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
555 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
556 const DebugLoc &DL,
557 int *BytesAdded = nullptr) const override;
558
559 // Select analysis.
560 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
561 Register, Register, Register, int &, int &,
562 int &) const override;
563 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
564 const DebugLoc &DL, Register DstReg,
565 ArrayRef<MachineOperand> Cond, Register TrueReg,
566 Register FalseReg) const override;
567
568 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
569 const DebugLoc &DL, Register DestReg, Register SrcReg,
570 bool KillSrc, bool RenamableDest = false,
571 bool RenamableSrc = false) const override;
572
573 void storeRegToStackSlot(
574 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
575 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
576
577 Register VReg,
578 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
579
580 // Emits a register spill without updating the register class for vector
581 // registers. This ensures that when we spill a vector register the
582 // element order in the register is the same as it was in memory.
583 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB,
584 MachineBasicBlock::iterator MBBI,
585 unsigned SrcReg, bool isKill, int FrameIndex,
586 const TargetRegisterClass *RC) const;
587
588 void loadRegFromStackSlot(
589 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
590 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
591 Register VReg, unsigned SubReg = 0,
592 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
593
594 // Emits a register reload without updating the register class for vector
595 // registers. This ensures that when we reload a vector register the
596 // element order in the register is the same as it was in memory.
597 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB,
598 MachineBasicBlock::iterator MBBI,
599 unsigned DestReg, int FrameIndex,
600 const TargetRegisterClass *RC) const;
601
602 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
603
604 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
605
606 bool
607 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
608
609 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
610 MachineRegisterInfo *MRI) const override;
611
612 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
613 Register Reg) const;
614
615 // If conversion by predication (only supported by some branch instructions).
616 // All of the profitability checks always return true; it is always
617 // profitable to use the predicated branches.
618 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
619 unsigned NumCycles, unsigned ExtraPredCycles,
620 BranchProbability Probability) const override {
621 return true;
622 }
623
624 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
625 unsigned NumT, unsigned ExtraT,
626 MachineBasicBlock &FMBB,
627 unsigned NumF, unsigned ExtraF,
628 BranchProbability Probability) const override;
629
630 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
631 BranchProbability Probability) const override {
632 return true;
633 }
634
635 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
636 MachineBasicBlock &FMBB) const override {
637 return false;
638 }
639
640 // Predication support.
641 bool isPredicated(const MachineInstr &MI) const override;
642
643 bool isSchedulingBoundary(const MachineInstr &MI,
644 const MachineBasicBlock *MBB,
645 const MachineFunction &MF) const override;
646
647 bool PredicateInstruction(MachineInstr &MI,
648 ArrayRef<MachineOperand> Pred) const override;
649
650 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
651 ArrayRef<MachineOperand> Pred2) const override;
652
653 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
654 bool SkipDead) const override;
655
656 // Comparison optimization.
657
658 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
659 Register &SrcReg2, int64_t &Mask,
660 int64_t &Value) const override;
661
662 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
663 Register SrcReg2, int64_t Mask, int64_t Value,
664 const MachineRegisterInfo *MRI) const override;
665
666
667 /// Return true if get the base operand, byte offset of an instruction and
668 /// the memory width. Width is the size of memory that is being
669 /// loaded/stored (e.g. 1, 2, 4, 8).
670 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
671 const MachineOperand *&BaseOp,
672 int64_t &Offset, LocationSize &Width) const;
673
674 bool optimizeCmpPostRA(MachineInstr &MI) const;
675
676 /// Get the base operand and byte offset of an instruction that reads/writes
677 /// memory.
678 bool getMemOperandsWithOffsetWidth(
679 const MachineInstr &LdSt,
680 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
681 bool &OffsetIsScalable, LocationSize &Width) const override;
682
683 /// Returns true if the two given memory operations should be scheduled
684 /// adjacent.
685 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
686 int64_t Offset1, bool OffsetIsScalable1,
687 ArrayRef<const MachineOperand *> BaseOps2,
688 int64_t Offset2, bool OffsetIsScalable2,
689 unsigned ClusterSize,
690 unsigned NumBytes) const override;
691
692 /// Return true if two MIs access different memory addresses and false
693 /// otherwise
694 bool
695 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
696 const MachineInstr &MIb) const override;
697
698 /// GetInstSize - Return the number of bytes of code the specified
699 /// instruction may be. This returns the maximum number of bytes.
700 ///
701 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
702
703 InstSizeVerifyMode
704 getInstSizeVerifyMode(const MachineInstr &MI) const override;
705
706 MCInst getNop() const override;
707
708 std::pair<unsigned, unsigned>
709 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
710
711 ArrayRef<std::pair<unsigned, const char *>>
712 getSerializableDirectMachineOperandTargetFlags() const override;
713
714 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
715 bool expandVSXMemPseudo(MachineInstr &MI) const;
716
717 // Lower pseudo instructions after register allocation.
718 bool expandPostRAPseudo(MachineInstr &MI) const override;
719 bool expandAMOCSNEPseudo(MachineInstr &MI) const;
720
721 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
722 static int getRecordFormOpcode(unsigned Opcode);
723
724 bool isTOCSaveMI(const MachineInstr &MI) const;
725
726 std::pair<bool, bool>
727 isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
728 const MachineRegisterInfo *MRI) const;
729
730 // Return true if the register is sign-extended from 32 to 64 bits.
731 bool isSignExtended(const unsigned Reg,
732 const MachineRegisterInfo *MRI) const {
733 return isSignOrZeroExtended(Reg, BinOpDepth: 0, MRI).first;
734 }
735
736 // Return true if the register is zero-extended from 32 to 64 bits.
737 bool isZeroExtended(const unsigned Reg,
738 const MachineRegisterInfo *MRI) const {
739 return isSignOrZeroExtended(Reg, BinOpDepth: 0, MRI).second;
740 }
741 void promoteInstr32To64ForElimEXTSW(const Register &Reg,
742 MachineRegisterInfo *MRI,
743 unsigned BinOpDepth) const;
744
745 bool convertToImmediateForm(MachineInstr &MI,
746 SmallSet<Register, 4> &RegsToUpdate,
747 MachineInstr **KilledDef = nullptr) const;
748 bool foldFrameOffset(MachineInstr &MI) const;
749 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
750 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
751 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
752 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
753 unsigned &XFormOpcode,
754 int64_t &OffsetOfImmInstr,
755 ImmInstrInfo &III) const;
756 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
757 MachineInstr *&ADDIMI, int64_t &OffsetAddi,
758 int64_t OffsetImm) const;
759
760 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
761 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
762 int64_t Imm) const;
763
764 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
765 bool PostRA) const;
766
767 // In PostRA phase, try to find instruction defines \p Reg before \p MI.
768 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
769 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
770 bool &SeenIntermediateUse) const;
771
772 // Materialize immediate after RA.
773 void materializeImmPostRA(MachineBasicBlock &MBB,
774 MachineBasicBlock::iterator MBBI,
775 const DebugLoc &DL, Register Reg,
776 int64_t Imm) const;
777
778 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
779 bool isBDNZ(unsigned Opcode) const;
780
781 /// Find the hardware loop instruction used to set-up the specified loop.
782 /// On PPC, we have two instructions used to set-up the hardware loop
783 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
784 /// instructions to indicate the end of a loop.
785 MachineInstr *
786 findLoopInstr(MachineBasicBlock &PreHeader,
787 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
788
789 /// Analyze loop L, which must be a single-basic-block loop, and if the
790 /// conditions can be understood enough produce a PipelinerLoopInfo object.
791 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
792 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
793};
794
795}
796
797#endif
798