1//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15
16#include "MCTargetDesc/PPCMCTargetDesc.h"
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "llvm/ADT/SmallSet.h"
20#include "llvm/CodeGen/LiveVariables.h"
21#include "llvm/CodeGen/TargetInstrInfo.h"
22
23#define GET_INSTRINFO_HEADER
24#include "PPCGenInstrInfo.inc"
25
26namespace llvm {
27
28// Instructions that have an immediate form might be convertible to that
29// form if the correct input is a result of a load immediate. In order to
30// know whether the transformation is special, we might need to know some
31// of the details of the two forms.
32struct ImmInstrInfo {
33 // Is the immediate field in the immediate form signed or unsigned?
34 uint64_t SignedImm : 1;
35 // Does the immediate need to be a multiple of some value?
36 uint64_t ImmMustBeMultipleOf : 5;
37 // Is R0/X0 treated specially by the original r+r instruction?
38 // If so, in which operand?
39 uint64_t ZeroIsSpecialOrig : 3;
40 // Is R0/X0 treated specially by the new r+i instruction?
41 // If so, in which operand?
42 uint64_t ZeroIsSpecialNew : 3;
43 // Is the operation commutative?
44 uint64_t IsCommutative : 1;
45 // The operand number to check for add-immediate def.
46 uint64_t OpNoForForwarding : 3;
47 // The operand number for the immediate.
48 uint64_t ImmOpNo : 3;
49 // The opcode of the new instruction.
50 uint64_t ImmOpcode : 16;
51 // The size of the immediate.
52 uint64_t ImmWidth : 5;
53 // The immediate should be truncated to N bits.
54 uint64_t TruncateImmTo : 5;
55 // Is the instruction summing the operand
56 uint64_t IsSummingOperands : 1;
57};
58
59// Information required to convert an instruction to just a materialized
60// immediate.
61struct LoadImmediateInfo {
62 unsigned Imm : 16;
63 unsigned Is64Bit : 1;
64 unsigned SetCR : 1;
65};
66
67// Index into the OpcodesForSpill array.
68enum SpillOpcodeKey {
69 SOK_Int4Spill,
70 SOK_Int8Spill,
71 SOK_Float8Spill,
72 SOK_Float4Spill,
73 SOK_CRSpill,
74 SOK_CRBitSpill,
75 SOK_VRVectorSpill,
76 SOK_VSXVectorSpill,
77 SOK_VectorFloat8Spill,
78 SOK_VectorFloat4Spill,
79 SOK_SpillToVSR,
80 SOK_PairedVecSpill,
81 SOK_AccumulatorSpill,
82 SOK_UAccumulatorSpill,
83 SOK_WAccumulatorSpill,
84 SOK_DMRpSpill,
85 SOK_DMRSpill,
86 SOK_SPESpill,
87 SOK_PairedG8Spill,
88 SOK_LastOpcodeSpill // This must be last on the enum.
89};
90
91// PPC MachineCombiner patterns
92enum PPCMachineCombinerPattern : unsigned {
93 // These are patterns matched by the PowerPC to reassociate FMA chains.
94 REASSOC_XY_AMM_BMM = MachineCombinerPattern::TARGET_PATTERN_START,
95 REASSOC_XMM_AMM_BMM,
96
97 // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
98 // reduce register pressure.
99 REASSOC_XY_BCA,
100 REASSOC_XY_BAC,
101
102};
103
104// Define list of load and store spill opcodes.
105#define NoInstr PPC::INSTRUCTION_LIST_END
106#define Pwr8LoadOpcodes \
107 {PPC::LWZ, \
108 PPC::LD, \
109 PPC::LFD, \
110 PPC::LFS, \
111 PPC::RESTORE_CR, \
112 PPC::RESTORE_CRBIT, \
113 PPC::LVX, \
114 PPC::LXVD2X, \
115 PPC::LXSDX, \
116 PPC::LXSSPX, \
117 PPC::SPILLTOVSR_LD, \
118 NoInstr, \
119 NoInstr, \
120 NoInstr, \
121 NoInstr, \
122 NoInstr, \
123 NoInstr, \
124 PPC::EVLDD, \
125 PPC::RESTORE_QUADWORD}
126
127#define Pwr9LoadOpcodes \
128 {PPC::LWZ, \
129 PPC::LD, \
130 PPC::LFD, \
131 PPC::LFS, \
132 PPC::RESTORE_CR, \
133 PPC::RESTORE_CRBIT, \
134 PPC::LVX, \
135 PPC::LXV, \
136 PPC::DFLOADf64, \
137 PPC::DFLOADf32, \
138 PPC::SPILLTOVSR_LD, \
139 NoInstr, \
140 NoInstr, \
141 NoInstr, \
142 NoInstr, \
143 NoInstr, \
144 NoInstr, \
145 NoInstr, \
146 PPC::RESTORE_QUADWORD}
147
148#define Pwr10LoadOpcodes \
149 {PPC::LWZ, \
150 PPC::LD, \
151 PPC::LFD, \
152 PPC::LFS, \
153 PPC::RESTORE_CR, \
154 PPC::RESTORE_CRBIT, \
155 PPC::LVX, \
156 PPC::LXV, \
157 PPC::DFLOADf64, \
158 PPC::DFLOADf32, \
159 PPC::SPILLTOVSR_LD, \
160 PPC::LXVP, \
161 PPC::RESTORE_ACC, \
162 PPC::RESTORE_UACC, \
163 NoInstr, \
164 NoInstr, \
165 NoInstr, \
166 NoInstr, \
167 PPC::RESTORE_QUADWORD}
168
169#define FutureLoadOpcodes \
170 {PPC::LWZ, \
171 PPC::LD, \
172 PPC::LFD, \
173 PPC::LFS, \
174 PPC::RESTORE_CR, \
175 PPC::RESTORE_CRBIT, \
176 PPC::LVX, \
177 PPC::LXV, \
178 PPC::DFLOADf64, \
179 PPC::DFLOADf32, \
180 PPC::SPILLTOVSR_LD, \
181 PPC::LXVP, \
182 PPC::RESTORE_ACC, \
183 PPC::RESTORE_UACC, \
184 PPC::RESTORE_WACC, \
185 PPC::RESTORE_DMRP, \
186 PPC::RESTORE_DMR, \
187 NoInstr, \
188 PPC::RESTORE_QUADWORD}
189
190#define Pwr8StoreOpcodes \
191 {PPC::STW, \
192 PPC::STD, \
193 PPC::STFD, \
194 PPC::STFS, \
195 PPC::SPILL_CR, \
196 PPC::SPILL_CRBIT, \
197 PPC::STVX, \
198 PPC::STXVD2X, \
199 PPC::STXSDX, \
200 PPC::STXSSPX, \
201 PPC::SPILLTOVSR_ST, \
202 NoInstr, \
203 NoInstr, \
204 NoInstr, \
205 NoInstr, \
206 NoInstr, \
207 NoInstr, \
208 PPC::EVSTDD, \
209 PPC::SPILL_QUADWORD}
210
211#define Pwr9StoreOpcodes \
212 {PPC::STW, \
213 PPC::STD, \
214 PPC::STFD, \
215 PPC::STFS, \
216 PPC::SPILL_CR, \
217 PPC::SPILL_CRBIT, \
218 PPC::STVX, \
219 PPC::STXV, \
220 PPC::DFSTOREf64, \
221 PPC::DFSTOREf32, \
222 PPC::SPILLTOVSR_ST, \
223 NoInstr, \
224 NoInstr, \
225 NoInstr, \
226 NoInstr, \
227 NoInstr, \
228 NoInstr, \
229 NoInstr, \
230 PPC::SPILL_QUADWORD}
231
232#define Pwr10StoreOpcodes \
233 {PPC::STW, \
234 PPC::STD, \
235 PPC::STFD, \
236 PPC::STFS, \
237 PPC::SPILL_CR, \
238 PPC::SPILL_CRBIT, \
239 PPC::STVX, \
240 PPC::STXV, \
241 PPC::DFSTOREf64, \
242 PPC::DFSTOREf32, \
243 PPC::SPILLTOVSR_ST, \
244 PPC::STXVP, \
245 PPC::SPILL_ACC, \
246 PPC::SPILL_UACC, \
247 NoInstr, \
248 NoInstr, \
249 NoInstr, \
250 NoInstr, \
251 PPC::SPILL_QUADWORD}
252
253#define FutureStoreOpcodes \
254 {PPC::STW, \
255 PPC::STD, \
256 PPC::STFD, \
257 PPC::STFS, \
258 PPC::SPILL_CR, \
259 PPC::SPILL_CRBIT, \
260 PPC::STVX, \
261 PPC::STXV, \
262 PPC::DFSTOREf64, \
263 PPC::DFSTOREf32, \
264 PPC::SPILLTOVSR_ST, \
265 PPC::STXVP, \
266 PPC::SPILL_ACC, \
267 PPC::SPILL_UACC, \
268 PPC::SPILL_WACC, \
269 PPC::SPILL_DMRP, \
270 PPC::SPILL_DMR, \
271 NoInstr, \
272 PPC::SPILL_QUADWORD}
273
274// Initialize arrays for load and store spill opcodes on supported subtargets.
275#define StoreOpcodesForSpill \
276 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }
277#define LoadOpcodesForSpill \
278 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }
279
280class PPCSubtarget;
281class PPCInstrInfo : public PPCGenInstrInfo {
282 const PPCSubtarget &Subtarget;
283 const PPCRegisterInfo RI;
284 const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
285 StoreOpcodesForSpill;
286 const unsigned LoadSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
287 LoadOpcodesForSpill;
288
289 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
290 int FrameIdx, const TargetRegisterClass *RC,
291 SmallVectorImpl<MachineInstr *> &NewMIs) const;
292 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
293 unsigned DestReg, int FrameIdx,
294 const TargetRegisterClass *RC,
295 SmallVectorImpl<MachineInstr *> &NewMIs) const;
296
297 // Replace the instruction with single LI if possible. \p DefMI must be LI or
298 // LI8.
299 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
300 unsigned OpNoForForwarding, MachineInstr **KilledDef,
301 SmallSet<Register, 4> *RegsToUpdate = nullptr) const;
302 // If the inst is imm-form and its register operand is produced by a ADDI, put
303 // the imm into the inst directly and remove the ADDI if possible.
304 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
305 unsigned OpNoForForwarding) const;
306 // If the inst is x-form and has imm-form and one of its operand is produced
307 // by a LI, put the imm into the inst directly and remove the LI if possible.
308 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
309 unsigned ConstantOpNo,
310 MachineInstr &DefMI) const;
311 // If the inst is x-form and has imm-form and one of its operand is produced
312 // by an add-immediate, try to transform it when possible.
313 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
314 unsigned ConstantOpNo, MachineInstr &DefMI,
315 bool KillDefMI) const;
316 // Try to find that, if the instruction 'MI' contains any operand that
317 // could be forwarded from some inst that feeds it. If yes, return the
318 // Def of that operand. And OpNoForForwarding is the operand index in
319 // the 'MI' for that 'Def'. If we see another use of this Def between
320 // the Def and the MI, SeenIntermediateUse becomes 'true'.
321 MachineInstr *getForwardingDefMI(MachineInstr &MI,
322 unsigned &OpNoForForwarding,
323 bool &SeenIntermediateUse) const;
324
325 // Can the user MI have it's source at index \p OpNoForForwarding
326 // forwarded from an add-immediate that feeds it?
327 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
328 unsigned OpNoForForwarding) const;
329 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
330 const ImmInstrInfo &III,
331 MachineOperand *&ImmMO,
332 MachineOperand *&RegMO) const;
333 bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
334 const MachineInstr &DefMI,
335 const ImmInstrInfo &III,
336 int64_t &Imm,
337 int64_t BaseImm = 0) const;
338 bool isRegElgibleForForwarding(const MachineOperand &RegMO,
339 const MachineInstr &DefMI,
340 const MachineInstr &MI, bool KillDefMI,
341 bool &IsFwdFeederRegKilled,
342 bool &SeenIntermediateUse) const;
343 unsigned getSpillTarget() const;
344 ArrayRef<unsigned> getStoreOpcodesForSpillArray() const;
345 ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
346 unsigned getSpillIndex(const TargetRegisterClass *RC) const;
347 int16_t getFMAOpIdxInfo(unsigned Opcode) const;
348 void reassociateFMA(MachineInstr &Root, unsigned Pattern,
349 SmallVectorImpl<MachineInstr *> &InsInstrs,
350 SmallVectorImpl<MachineInstr *> &DelInstrs,
351 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const;
352 Register
353 generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
354 SmallVectorImpl<MachineInstr *> &InsInstrs) const;
355 virtual void anchor();
356
357protected:
358 /// Commutes the operands in the given instruction.
359 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
360 ///
361 /// Do not call this method for a non-commutable instruction or for
362 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
363 /// Even though the instruction is commutable, the method may still
364 /// fail to commute the operands, null pointer is returned in such cases.
365 ///
366 /// For example, we can commute rlwimi instructions, but only if the
367 /// rotate amt is zero. We also have to munge the immediates a bit.
368 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
369 unsigned OpIdx1,
370 unsigned OpIdx2) const override;
371
372public:
373 explicit PPCInstrInfo(const PPCSubtarget &STI);
374
375 bool isLoadFromConstantPool(MachineInstr *I) const;
376 const Constant *getConstantFromConstantPool(MachineInstr *I) const;
377
378 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
379 /// such, whenever a client has an instance of instruction info, it should
380 /// always be able to get register info as well (through this method).
381 ///
382 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
383
384 const TargetRegisterClass *
385 getInlineAsmMemoryOperandRegClass(InlineAsm::ConstraintCode C) const override;
386
387 bool isXFormMemOp(unsigned Opcode) const {
388 return get(Opcode).TSFlags & PPCII::XFormMemOp;
389 }
390 bool isPrefixed(unsigned Opcode) const {
391 return get(Opcode).TSFlags & PPCII::Prefixed;
392 }
393 bool isSExt32To64(unsigned Opcode) const {
394 return get(Opcode).TSFlags & PPCII::SExt32To64;
395 }
396 bool isZExt32To64(unsigned Opcode) const {
397 return get(Opcode).TSFlags & PPCII::ZExt32To64;
398 }
399 bool isMemriOp(unsigned Opcode) const {
400 return get(Opcode).TSFlags & PPCII::MemriOp;
401 }
402
403 static bool isSameClassPhysRegCopy(unsigned Opcode) {
404 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
405 PPC::VOR, PPC::XXLOR, PPC::XXLORf,
406 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
407 PPC::EVOR, -1U};
408 for (int i = 0; CopyOpcodes[i] != -1U; i++)
409 if (Opcode == CopyOpcodes[i])
410 return true;
411 return false;
412 }
413
414 static bool hasPCRelFlag(unsigned TF) {
415 return TF == PPCII::MO_PCREL_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
416 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
417 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
418 TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG ||
419 TF == PPCII::MO_GOT_PCREL_FLAG;
420 }
421
422 static bool hasGOTFlag(unsigned TF) {
423 return TF == PPCII::MO_GOT_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
424 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
425 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
426 TF == PPCII::MO_GOT_PCREL_FLAG;
427 }
428
429 static bool hasTLSFlag(unsigned TF) {
430 return TF == PPCII::MO_TLSGD_FLAG || TF == PPCII::MO_TPREL_FLAG ||
431 TF == PPCII::MO_TLSLD_FLAG || TF == PPCII::MO_TLSGDM_FLAG ||
432 TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
433 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
434 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG || TF == PPCII::MO_TPREL_LO ||
435 TF == PPCII::MO_TPREL_HA || TF == PPCII::MO_DTPREL_LO ||
436 TF == PPCII::MO_TLSLD_LO || TF == PPCII::MO_TLS ||
437 TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG;
438 }
439
440 ScheduleHazardRecognizer *
441 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
442 const ScheduleDAG *DAG) const override;
443 ScheduleHazardRecognizer *
444 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
445 const ScheduleDAG *DAG) const override;
446
447 unsigned getInstrLatency(const InstrItineraryData *ItinData,
448 const MachineInstr &MI,
449 unsigned *PredCost = nullptr) const override;
450
451 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
452 const MachineInstr &DefMI,
453 unsigned DefIdx,
454 const MachineInstr &UseMI,
455 unsigned UseIdx) const override;
456 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
457 SDNode *DefNode, unsigned DefIdx,
458 SDNode *UseNode,
459 unsigned UseIdx) const override {
460 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
461 UseNode, UseIdx);
462 }
463
464 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
465 const MachineInstr &DefMI,
466 unsigned DefIdx) const override {
467 // Machine LICM should hoist all instructions in low-register-pressure
468 // situations; none are sufficiently free to justify leaving in a loop
469 // body.
470 return false;
471 }
472
473 bool useMachineCombiner() const override {
474 return true;
475 }
476
477 /// When getMachineCombinerPatterns() finds patterns, this function generates
478 /// the instructions that could replace the original code sequence
479 void genAlternativeCodeSequence(
480 MachineInstr &Root, unsigned Pattern,
481 SmallVectorImpl<MachineInstr *> &InsInstrs,
482 SmallVectorImpl<MachineInstr *> &DelInstrs,
483 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
484
485 /// Return true when there is potentially a faster code sequence for a fma
486 /// chain ending in \p Root. All potential patterns are output in the \p
487 /// P array.
488 bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
489 bool DoRegPressureReduce) const;
490
491 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
492
493 /// Return true when there is potentially a faster code sequence
494 /// for an instruction chain ending in <Root>. All potential patterns are
495 /// output in the <Pattern> array.
496 bool getMachineCombinerPatterns(MachineInstr &Root,
497 SmallVectorImpl<unsigned> &Patterns,
498 bool DoRegPressureReduce) const override;
499
500 /// On PowerPC, we leverage machine combiner pass to reduce register pressure
501 /// when the register pressure is high for one BB.
502 /// Return true if register pressure for \p MBB is high and ABI is supported
503 /// to reduce register pressure. Otherwise return false.
504 bool shouldReduceRegisterPressure(
505 const MachineBasicBlock *MBB,
506 const RegisterClassInfo *RegClassInfo) const override;
507
508 /// Fixup the placeholders we put in genAlternativeCodeSequence() for
509 /// MachineCombiner.
510 void
511 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
512 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
513
514 bool isAssociativeAndCommutative(const MachineInstr &Inst,
515 bool Invert) const override;
516
517 /// On PowerPC, we try to reassociate FMA chain which will increase
518 /// instruction size. Set extension resource length limit to 1 for edge case.
519 /// Resource Length is calculated by scaled resource usage in getCycles().
520 /// Because of the division in getCycles(), it returns different cycles due to
521 /// legacy scaled resource usage. So new resource length may be same with
522 /// legacy or 1 bigger than legacy.
523 /// We need to execlude the 1 bigger case even the resource length is not
524 /// perserved for more FMA chain reassociations on PowerPC.
525 int getExtendResourceLenLimit() const override { return 1; }
526
527 // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
528 // and clears nuw, nsw, and exact flags.
529 using TargetInstrInfo::setSpecialOperandAttr;
530 void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const;
531
532 bool isCoalescableExtInstr(const MachineInstr &MI,
533 Register &SrcReg, Register &DstReg,
534 unsigned &SubIdx) const override;
535 Register isLoadFromStackSlot(const MachineInstr &MI,
536 int &FrameIndex) const override;
537 bool isReMaterializableImpl(const MachineInstr &MI) const override;
538 Register isStoreToStackSlot(const MachineInstr &MI,
539 int &FrameIndex) const override;
540
541 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
542 unsigned &SrcOpIdx2) const override;
543
544 void insertNoop(MachineBasicBlock &MBB,
545 MachineBasicBlock::iterator MI) const override;
546
547
548 // Branch analysis.
549 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
550 MachineBasicBlock *&FBB,
551 SmallVectorImpl<MachineOperand> &Cond,
552 bool AllowModify) const override;
553 unsigned removeBranch(MachineBasicBlock &MBB,
554 int *BytesRemoved = nullptr) const override;
555 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
556 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
557 const DebugLoc &DL,
558 int *BytesAdded = nullptr) const override;
559
560 // Select analysis.
561 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
562 Register, Register, Register, int &, int &,
563 int &) const override;
564 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
565 const DebugLoc &DL, Register DstReg,
566 ArrayRef<MachineOperand> Cond, Register TrueReg,
567 Register FalseReg) const override;
568
569 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
570 const DebugLoc &DL, Register DestReg, Register SrcReg,
571 bool KillSrc, bool RenamableDest = false,
572 bool RenamableSrc = false) const override;
573
574 void storeRegToStackSlot(
575 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
576 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
577
578 Register VReg,
579 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
580
581 // Emits a register spill without updating the register class for vector
582 // registers. This ensures that when we spill a vector register the
583 // element order in the register is the same as it was in memory.
584 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB,
585 MachineBasicBlock::iterator MBBI,
586 unsigned SrcReg, bool isKill, int FrameIndex,
587 const TargetRegisterClass *RC) const;
588
589 void loadRegFromStackSlot(
590 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
591 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
592 Register VReg, unsigned SubReg = 0,
593 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
594
595 // Emits a register reload without updating the register class for vector
596 // registers. This ensures that when we reload a vector register the
597 // element order in the register is the same as it was in memory.
598 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB,
599 MachineBasicBlock::iterator MBBI,
600 unsigned DestReg, int FrameIndex,
601 const TargetRegisterClass *RC) const;
602
603 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
604
605 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
606
607 bool
608 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
609
610 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
611 MachineRegisterInfo *MRI) const override;
612
613 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
614 Register Reg) const;
615
616 // If conversion by predication (only supported by some branch instructions).
617 // All of the profitability checks always return true; it is always
618 // profitable to use the predicated branches.
619 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
620 unsigned NumCycles, unsigned ExtraPredCycles,
621 BranchProbability Probability) const override {
622 return true;
623 }
624
625 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
626 unsigned NumT, unsigned ExtraT,
627 MachineBasicBlock &FMBB,
628 unsigned NumF, unsigned ExtraF,
629 BranchProbability Probability) const override;
630
631 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
632 BranchProbability Probability) const override {
633 return true;
634 }
635
636 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
637 MachineBasicBlock &FMBB) const override {
638 return false;
639 }
640
641 // Predication support.
642 bool isPredicated(const MachineInstr &MI) const override;
643
644 bool isSchedulingBoundary(const MachineInstr &MI,
645 const MachineBasicBlock *MBB,
646 const MachineFunction &MF) const override;
647
648 bool PredicateInstruction(MachineInstr &MI,
649 ArrayRef<MachineOperand> Pred) const override;
650
651 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
652 ArrayRef<MachineOperand> Pred2) const override;
653
654 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
655 bool SkipDead) const override;
656
657 // Comparison optimization.
658
659 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
660 Register &SrcReg2, int64_t &Mask,
661 int64_t &Value) const override;
662
663 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
664 Register SrcReg2, int64_t Mask, int64_t Value,
665 const MachineRegisterInfo *MRI) const override;
666
667
668 /// Return true if get the base operand, byte offset of an instruction and
669 /// the memory width. Width is the size of memory that is being
670 /// loaded/stored (e.g. 1, 2, 4, 8).
671 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
672 const MachineOperand *&BaseOp,
673 int64_t &Offset, LocationSize &Width,
674 const TargetRegisterInfo *TRI) const;
675
676 bool optimizeCmpPostRA(MachineInstr &MI) const;
677
678 /// Get the base operand and byte offset of an instruction that reads/writes
679 /// memory.
680 bool getMemOperandsWithOffsetWidth(
681 const MachineInstr &LdSt,
682 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
683 bool &OffsetIsScalable, LocationSize &Width,
684 const TargetRegisterInfo *TRI) const override;
685
686 /// Returns true if the two given memory operations should be scheduled
687 /// adjacent.
688 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
689 int64_t Offset1, bool OffsetIsScalable1,
690 ArrayRef<const MachineOperand *> BaseOps2,
691 int64_t Offset2, bool OffsetIsScalable2,
692 unsigned ClusterSize,
693 unsigned NumBytes) const override;
694
695 /// Return true if two MIs access different memory addresses and false
696 /// otherwise
697 bool
698 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
699 const MachineInstr &MIb) const override;
700
701 /// GetInstSize - Return the number of bytes of code the specified
702 /// instruction may be. This returns the maximum number of bytes.
703 ///
704 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
705
706 InstSizeVerifyMode
707 getInstSizeVerifyMode(const MachineInstr &MI) const override;
708
709 MCInst getNop() const override;
710
711 std::pair<unsigned, unsigned>
712 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
713
714 ArrayRef<std::pair<unsigned, const char *>>
715 getSerializableDirectMachineOperandTargetFlags() const override;
716
717 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
718 bool expandVSXMemPseudo(MachineInstr &MI) const;
719
720 // Lower pseudo instructions after register allocation.
721 bool expandPostRAPseudo(MachineInstr &MI) const override;
722 bool expandAMOCSNEPseudo(MachineInstr &MI) const;
723
724 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
725 static int getRecordFormOpcode(unsigned Opcode);
726
727 bool isTOCSaveMI(const MachineInstr &MI) const;
728
729 std::pair<bool, bool>
730 isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
731 const MachineRegisterInfo *MRI) const;
732
733 // Return true if the register is sign-extended from 32 to 64 bits.
734 bool isSignExtended(const unsigned Reg,
735 const MachineRegisterInfo *MRI) const {
736 return isSignOrZeroExtended(Reg, BinOpDepth: 0, MRI).first;
737 }
738
739 // Return true if the register is zero-extended from 32 to 64 bits.
740 bool isZeroExtended(const unsigned Reg,
741 const MachineRegisterInfo *MRI) const {
742 return isSignOrZeroExtended(Reg, BinOpDepth: 0, MRI).second;
743 }
744 void promoteInstr32To64ForElimEXTSW(const Register &Reg,
745 MachineRegisterInfo *MRI,
746 unsigned BinOpDepth,
747 LiveVariables *LV) const;
748
749 bool convertToImmediateForm(MachineInstr &MI,
750 SmallSet<Register, 4> &RegsToUpdate,
751 MachineInstr **KilledDef = nullptr) const;
752 bool foldFrameOffset(MachineInstr &MI) const;
753 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
754 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
755 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
756 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
757 unsigned &XFormOpcode,
758 int64_t &OffsetOfImmInstr,
759 ImmInstrInfo &III) const;
760 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
761 MachineInstr *&ADDIMI, int64_t &OffsetAddi,
762 int64_t OffsetImm) const;
763
764 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
765 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
766 int64_t Imm) const;
767
768 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
769 bool PostRA) const;
770
771 // In PostRA phase, try to find instruction defines \p Reg before \p MI.
772 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
773 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
774 bool &SeenIntermediateUse) const;
775
776 // Materialize immediate after RA.
777 void materializeImmPostRA(MachineBasicBlock &MBB,
778 MachineBasicBlock::iterator MBBI,
779 const DebugLoc &DL, Register Reg,
780 int64_t Imm) const;
781
782 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
783 bool isBDNZ(unsigned Opcode) const;
784
785 /// Find the hardware loop instruction used to set-up the specified loop.
786 /// On PPC, we have two instructions used to set-up the hardware loop
787 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
788 /// instructions to indicate the end of a loop.
789 MachineInstr *
790 findLoopInstr(MachineBasicBlock &PreHeader,
791 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
792
793 /// Analyze loop L, which must be a single-basic-block loop, and if the
794 /// conditions can be understood enough produce a PipelinerLoopInfo object.
795 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
796 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
797};
798
799}
800
801#endif
802