RISCVGenCompressInstEmitter.inc source code [llvm_projects/build/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Compress instruction Source Fragment \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| From: RISCV.td \|
7	\| \|
8	\===----------------------------------------------------------------------===/
9
10	#ifdef GEN_COMPRESS_INSTR
11	#undef GEN_COMPRESS_INSTR
12
13	static bool RISCVValidateMCOperandForCompress(const MCOperand &MCOp,
14	const MCSubtargetInfo &STI,
15	unsigned PredicateIndex) {
16	switch (PredicateIndex) {
17	default:
18	llvm_unreachable("Unknown MCOperandPredicate kind");
19	break;
20	case `1`: {
21	// uimm10_lsb00nonzero
22	int64_t Imm;
23	if (!MCOp.evaluateAsConstantImm(Imm))
24	return false;
25	return isShiftedUInt<`8`, `2`>(x: Imm) && (Imm != `0`);
26	}
27	case `2`: {
28	// simm6nonzero
29	int64_t Imm;
30	if (MCOp.evaluateAsConstantImm(Imm))
31	return (Imm != `0`) && isInt<`6`>(x: Imm);
32	return MCOp.isBareSymbolRef();
33	}
34	case `3`: {
35	// simm6
36	int64_t Imm;
37	if (MCOp.evaluateAsConstantImm(Imm))
38	return isInt<`6`>(x: Imm);
39	return MCOp.isBareSymbolRef();
40	}
41	case `4`: {
42	// simm10_lsb0000nonzero
43	int64_t Imm;
44	if (!MCOp.evaluateAsConstantImm(Imm))
45	return false;
46	return isShiftedInt<`6`, `4`>(x: Imm) && (Imm != `0`);
47	}
48	case `5`: {
49	// bare_simm9_lsb0
50	int64_t Imm;
51	if (MCOp.evaluateAsConstantImm(Imm))
52	return isShiftedInt<`8`, `1`>(x: Imm);
53	return MCOp.isBareSymbolRef();
54	}
55	case `6`: {
56	// uimmlog2xlennonzero
57	int64_t Imm;
58	if (!MCOp.evaluateAsConstantImm(Imm))
59	return false;
60	if (STI.getTargetTriple().isArch64Bit())
61	return isUInt<`6`>(x: Imm) && (Imm != `0`);
62	return isUInt<`5`>(x: Imm) && (Imm != `0`);
63	}
64	case `7`: {
65	// uimm8_lsb000
66	int64_t Imm;
67	if (!MCOp.evaluateAsConstantImm(Imm))
68	return false;
69	return isShiftedUInt<`5`, `3`>(x: Imm);
70	}
71	case `8`: {
72	// uimm8_lsb000_optional
73	int64_t Imm;
74	if (!MCOp.evaluateAsConstantImm(Imm))
75	return false;
76	return isShiftedUInt<`5`, `3`>(x: Imm);
77	}
78	case `9`: {
79	// uimm9_lsb000
80	int64_t Imm;
81	if (!MCOp.evaluateAsConstantImm(Imm))
82	return false;
83	return isShiftedUInt<`6`, `3`>(x: Imm);
84	}
85	case `10`: {
86	// uimm9_lsb000_optional
87	int64_t Imm;
88	if (!MCOp.evaluateAsConstantImm(Imm))
89	return false;
90	return isShiftedUInt<`6`, `3`>(x: Imm);
91	}
92	case `11`: {
93	// uimm7_lsb00
94	int64_t Imm;
95	if (!MCOp.evaluateAsConstantImm(Imm))
96	return false;
97	return isShiftedUInt<`5`, `2`>(x: Imm);
98	}
99	case `12`: {
100	// uimm7_lsb00_optional
101	int64_t Imm;
102	if (!MCOp.evaluateAsConstantImm(Imm))
103	return false;
104	return isShiftedUInt<`5`, `2`>(x: Imm);
105	}
106	case `13`: {
107	// uimm8_lsb00
108	int64_t Imm;
109	if (!MCOp.evaluateAsConstantImm(Imm))
110	return false;
111	return isShiftedUInt<`6`, `2`>(x: Imm);
112	}
113	case `14`: {
114	// uimm8_lsb00_optional
115	int64_t Imm;
116	if (!MCOp.evaluateAsConstantImm(Imm))
117	return false;
118	return isShiftedUInt<`6`, `2`>(x: Imm);
119	}
120	case `15`: {
121	// bare_simm12_lsb0
122	int64_t Imm;
123	if (MCOp.evaluateAsConstantImm(Imm))
124	return isShiftedInt<`11`, `1`>(x: Imm);
125	return MCOp.isBareSymbolRef();
126	}
127	case `16`: {
128	// uimm2
129	int64_t Imm;
130	if (!MCOp.evaluateAsConstantImm(Imm))
131	return false;
132	return isUInt<`2`>(x: Imm);
133	}
134	case `17`: {
135	// uimm2_optional
136	int64_t Imm;
137	if (!MCOp.evaluateAsConstantImm(Imm))
138	return false;
139	return isUInt<`2`>(x: Imm);
140	}
141	case `18`: {
142	// uimm5
143	int64_t Imm;
144	if (!MCOp.evaluateAsConstantImm(Imm))
145	return false;
146	return isUInt<`5`>(x: Imm);
147	}
148	case `19`: {
149	// uimm5_optional
150	int64_t Imm;
151	if (!MCOp.evaluateAsConstantImm(Imm))
152	return false;
153	return isUInt<`5`>(x: Imm);
154	}
155	case `20`: {
156	// uimm4
157	int64_t Imm;
158	if (!MCOp.evaluateAsConstantImm(Imm))
159	return false;
160	return isUInt<`4`>(x: Imm);
161	}
162	case `21`: {
163	// uimm4_optional
164	int64_t Imm;
165	if (!MCOp.evaluateAsConstantImm(Imm))
166	return false;
167	return isUInt<`4`>(x: Imm);
168	}
169	case `22`: {
170	// uimm2_lsb0
171	int64_t Imm;
172	if (!MCOp.evaluateAsConstantImm(Imm))
173	return false;
174	return isShiftedUInt<`1`, `1`>(x: Imm);
175	}
176	case `23`: {
177	// uimm2_lsb0_optional
178	int64_t Imm;
179	if (!MCOp.evaluateAsConstantImm(Imm))
180	return false;
181	return isShiftedUInt<`1`, `1`>(x: Imm);
182	}
183	case `24`: {
184	// uimm6_lsb0
185	int64_t Imm;
186	if (!MCOp.evaluateAsConstantImm(Imm))
187	return false;
188	return isShiftedUInt<`5`, `1`>(x: Imm);
189	}
190	case `25`: {
191	// uimm6_lsb0_optional
192	int64_t Imm;
193	if (!MCOp.evaluateAsConstantImm(Imm))
194	return false;
195	return isShiftedUInt<`5`, `1`>(x: Imm);
196	}
197	case `26`: {
198	// uimm5_lsb0
199	int64_t Imm;
200	if (!MCOp.evaluateAsConstantImm(Imm))
201	return false;
202	return isShiftedUInt<`4`, `1`>(x: Imm);
203	}
204	case `27`: {
205	// uimm5_lsb0_optional
206	int64_t Imm;
207	if (!MCOp.evaluateAsConstantImm(Imm))
208	return false;
209	return isShiftedUInt<`4`, `1`>(x: Imm);
210	}
211	case `28`: {
212	// c_lui_imm
213	int64_t Imm;
214	if (!MCOp.evaluateAsConstantImm(Imm))
215	return false;
216	return (Imm != `0`) && (isUInt<`5`>(x: Imm) \|\|
217	(Imm >= `0xfffe0` && Imm <= `0xfffff`));
218	}
219	case `29`: {
220	// uimm5ge6_plus1
221	int64_t Imm;
222	if (!MCOp.evaluateAsConstantImm(Imm))
223	return false;
224	return Imm >= `6` && Imm <= `32`;
225	}
226	case `30`: {
227	// simm12_lo
228	int64_t Imm;
229	if (MCOp.evaluateAsConstantImm(Imm))
230	return isInt<`12`>(x: Imm);
231	return MCOp.isBareSymbolRef();
232	}
233	case `31`: {
234	// simm5nonzero
235	int64_t Imm;
236	if (!MCOp.evaluateAsConstantImm(Imm))
237	return false;
238	return (Imm != `0`) && isInt<`5`>(x: Imm);
239	}
240	case `32`: {
241	// bare_simm13_lsb0
242	int64_t Imm;
243	if (MCOp.evaluateAsConstantImm(Imm))
244	return isShiftedInt<`12`, `1`>(x: Imm);
245	return MCOp.isBareSymbolRef();
246	}
247	case `33`: {
248	// uimm5nonzero
249	int64_t Imm;
250	if (!MCOp.evaluateAsConstantImm(Imm))
251	return false;
252	return (Imm != `0`) && isUInt<`5`>(x: Imm);;
253	}
254	case `34`: {
255	// simm21_lsb0_jal
256	int64_t Imm;
257	if (MCOp.evaluateAsConstantImm(Imm))
258	return isShiftedInt<`20`, `1`>(x: Imm);
259	return MCOp.isBareSymbolRef();
260	}
261	case `35`: {
262	// simm12_lo_optional
263	int64_t Imm;
264	if (MCOp.evaluateAsConstantImm(Imm))
265	return isInt<`12`>(x: Imm);
266	return MCOp.isBareSymbolRef();
267	}
268	case `36`: {
269	// simm20_li
270	int64_t Imm;
271	if (MCOp.evaluateAsConstantImm(Imm))
272	return isInt<`20`>(x: Imm);
273	return MCOp.isBareSymbolRef();
274	}
275	case `37`: {
276	// uimm5slist
277	int64_t Imm;
278	if (!MCOp.evaluateAsConstantImm(Imm))
279	return false;
280	return ((Imm == `0`) \|\| (Imm == `1`) \|\|
281	(Imm == `2`) \|\| (Imm == `4`) \|\|
282	(Imm == `8`) \|\| (Imm == `16`) \|\|
283	(Imm == `15`) \|\| (Imm == `31`));
284	}
285	case `38`: {
286	// uimmlog2xlen
287	int64_t Imm;
288	if (!MCOp.evaluateAsConstantImm(Imm))
289	return false;
290	if (STI.getTargetTriple().isArch64Bit())
291	return isUInt<`6`>(x: Imm);
292	return isUInt<`5`>(x: Imm);
293	}
294	}
295	}
296
297	static bool compressInst(MCInst &OutInst,
298	const MCInst &MI,
299	const MCSubtargetInfo &STI) {
300	switch (MI.getOpcode()) {
301	default: return false;
302	case RISCV::ADD: {
303	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
304	MI.getOperand(i: `1`).isReg() &&
305	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
306	MI.getOperand(i: `0`).isReg() &&
307	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
308	MI.getOperand(i: `2`).isReg() &&
309	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
310	// c.mv $rs1, $rs2
311	OutInst.setOpcode(RISCV::C_MV);
312	// Operand: rs1
313	OutInst.addOperand(Op: MI.getOperand(i: `0`));
314	// Operand: rs2
315	OutInst.addOperand(Op: MI.getOperand(i: `2`));
316	OutInst.setLoc(MI.getLoc());
317	return true;
318	} // if
319	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
320	MI.getOperand(i: `2`).isReg() &&
321	(MI.getOperand(i: `2`).getReg() == RISCV::X0) &&
322	MI.getOperand(i: `0`).isReg() &&
323	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
324	MI.getOperand(i: `1`).isReg() &&
325	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
326	// c.mv $rs1, $rs2
327	OutInst.setOpcode(RISCV::C_MV);
328	// Operand: rs1
329	OutInst.addOperand(Op: MI.getOperand(i: `0`));
330	// Operand: rs2
331	OutInst.addOperand(Op: MI.getOperand(i: `1`));
332	OutInst.setLoc(MI.getLoc());
333	return true;
334	} // if
335	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
336	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
337	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
338	MI.getOperand(i: `1`).isReg() &&
339	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
340	MI.getOperand(i: `2`).isReg() &&
341	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
342	// c.add $rs1, $rs2
343	OutInst.setOpcode(RISCV::C_ADD);
344	// Operand: rd
345	OutInst.addOperand(Op: MI.getOperand(i: `1`));
346	// Operand: rs1
347	OutInst.addOperand(Op: MI.getOperand(i: `1`));
348	// Operand: rs2
349	OutInst.addOperand(Op: MI.getOperand(i: `2`));
350	OutInst.setLoc(MI.getLoc());
351	return true;
352	} // if
353	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
354	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
355	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
356	MI.getOperand(i: `2`).isReg() &&
357	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
358	MI.getOperand(i: `1`).isReg() &&
359	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
360	// c.add $rs1, $rs2
361	OutInst.setOpcode(RISCV::C_ADD);
362	// Operand: rd
363	OutInst.addOperand(Op: MI.getOperand(i: `2`));
364	// Operand: rs1
365	OutInst.addOperand(Op: MI.getOperand(i: `2`));
366	// Operand: rs2
367	OutInst.addOperand(Op: MI.getOperand(i: `1`));
368	OutInst.setLoc(MI.getLoc());
369	return true;
370	} // if
371	break;
372	} // case ADD
373	case RISCV::ADDI: {
374	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
375	MI.getOperand(i: `0`).isReg() &&
376	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
377	MI.getOperand(i: `1`).isReg() &&
378	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
379	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1` / uimm10_lsb00nonzero /)) {
380	// c.addi4spn $rd, $rs1, $imm
381	OutInst.setOpcode(RISCV::C_ADDI4SPN);
382	// Operand: rd
383	OutInst.addOperand(Op: MI.getOperand(i: `0`));
384	// Operand: rs1
385	OutInst.addOperand(Op: MI.getOperand(i: `1`));
386	// Operand: imm
387	OutInst.addOperand(Op: MI.getOperand(i: `2`));
388	OutInst.setLoc(MI.getLoc());
389	return true;
390	} // if
391	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
392	MI.getOperand(i: `0`).isReg() &&
393	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
394	MI.getOperand(i: `1`).isReg() &&
395	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
396	MI.getOperand(i: `2`).isImm() &&
397	(MI.getOperand(i: `2`).getImm() == `0`)) {
398	// c.nop
399	OutInst.setOpcode(RISCV::C_NOP);
400	OutInst.setLoc(MI.getLoc());
401	return true;
402	} // if
403	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
404	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
405	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
406	MI.getOperand(i: `1`).isReg() &&
407	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
408	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm6nonzero /) &&
409	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
410	// c.addi $rd, $imm
411	OutInst.setOpcode(RISCV::C_ADDI);
412	// Operand: rd_wb
413	OutInst.addOperand(Op: MI.getOperand(i: `1`));
414	// Operand: rd
415	OutInst.addOperand(Op: MI.getOperand(i: `1`));
416	// Operand: imm
417	OutInst.addOperand(Op: MI.getOperand(i: `2`));
418	OutInst.setLoc(MI.getLoc());
419	return true;
420	} // if
421	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
422	MI.getOperand(i: `1`).isReg() &&
423	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
424	MI.getOperand(i: `0`).isReg() &&
425	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
426	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
427	// c.li $rd, $imm
428	OutInst.setOpcode(RISCV::C_LI);
429	// Operand: rd
430	OutInst.addOperand(Op: MI.getOperand(i: `0`));
431	// Operand: imm
432	OutInst.addOperand(Op: MI.getOperand(i: `2`));
433	OutInst.setLoc(MI.getLoc());
434	return true;
435	} // if
436	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
437	MI.getOperand(i: `0`).isReg() &&
438	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
439	MI.getOperand(i: `1`).isReg() &&
440	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
441	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4` / simm10_lsb0000nonzero /)) {
442	// c.addi16sp $rd, $imm
443	OutInst.setOpcode(RISCV::C_ADDI16SP);
444	// Operand: rd_wb
445	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
446	// Operand: rd
447	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
448	// Operand: imm
449	OutInst.addOperand(Op: MI.getOperand(i: `2`));
450	OutInst.setLoc(MI.getLoc());
451	return true;
452	} // if
453	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
454	MI.getOperand(i: `2`).isImm() &&
455	(MI.getOperand(i: `2`).getImm() == `0`) &&
456	MI.getOperand(i: `0`).isReg() &&
457	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
458	MI.getOperand(i: `1`).isReg() &&
459	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
460	// c.mv $rs1, $rs2
461	OutInst.setOpcode(RISCV::C_MV);
462	// Operand: rs1
463	OutInst.addOperand(Op: MI.getOperand(i: `0`));
464	// Operand: rs2
465	OutInst.addOperand(Op: MI.getOperand(i: `1`));
466	OutInst.setLoc(MI.getLoc());
467	return true;
468	} // if
469	break;
470	} // case ADDI
471	case RISCV::ADDIW: {
472	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
473	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
474	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
475	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
476	MI.getOperand(i: `1`).isReg() &&
477	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
478	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
479	// c.addiw $rd, $imm
480	OutInst.setOpcode(RISCV::C_ADDIW);
481	// Operand: rd_wb
482	OutInst.addOperand(Op: MI.getOperand(i: `1`));
483	// Operand: rd
484	OutInst.addOperand(Op: MI.getOperand(i: `1`));
485	// Operand: imm
486	OutInst.addOperand(Op: MI.getOperand(i: `2`));
487	OutInst.setLoc(MI.getLoc());
488	return true;
489	} // if
490	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
491	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
492	MI.getOperand(i: `1`).isReg() &&
493	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
494	MI.getOperand(i: `0`).isReg() &&
495	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
496	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
497	// c.li $rd, $imm
498	OutInst.setOpcode(RISCV::C_LI);
499	// Operand: rd
500	OutInst.addOperand(Op: MI.getOperand(i: `0`));
501	// Operand: imm
502	OutInst.addOperand(Op: MI.getOperand(i: `2`));
503	OutInst.setLoc(MI.getLoc());
504	return true;
505	} // if
506	break;
507	} // case ADDIW
508	case RISCV::ADDW: {
509	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
510	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
511	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
512	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
513	MI.getOperand(i: `1`).isReg() &&
514	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
515	MI.getOperand(i: `2`).isReg() &&
516	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
517	// c.addw $rd, $rs2
518	OutInst.setOpcode(RISCV::C_ADDW);
519	// Operand: rd_wb
520	OutInst.addOperand(Op: MI.getOperand(i: `1`));
521	// Operand: rd
522	OutInst.addOperand(Op: MI.getOperand(i: `1`));
523	// Operand: rs2
524	OutInst.addOperand(Op: MI.getOperand(i: `2`));
525	OutInst.setLoc(MI.getLoc());
526	return true;
527	} // if
528	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
529	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
530	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
531	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
532	MI.getOperand(i: `2`).isReg() &&
533	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
534	MI.getOperand(i: `1`).isReg() &&
535	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
536	// c.addw $rd, $rs2
537	OutInst.setOpcode(RISCV::C_ADDW);
538	// Operand: rd_wb
539	OutInst.addOperand(Op: MI.getOperand(i: `2`));
540	// Operand: rd
541	OutInst.addOperand(Op: MI.getOperand(i: `2`));
542	// Operand: rs2
543	OutInst.addOperand(Op: MI.getOperand(i: `1`));
544	OutInst.setLoc(MI.getLoc());
545	return true;
546	} // if
547	break;
548	} // case ADDW
549	case RISCV::ADD_UW: {
550	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
551	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
552	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
553	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
554	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
555	MI.getOperand(i: `2`).isReg() &&
556	(MI.getOperand(i: `2`).getReg() == RISCV::X0) &&
557	MI.getOperand(i: `1`).isReg() &&
558	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
559	// c.zext.w $rd
560	OutInst.setOpcode(RISCV::C_ZEXT_W);
561	// Operand: rd_wb
562	OutInst.addOperand(Op: MI.getOperand(i: `1`));
563	// Operand: rd
564	OutInst.addOperand(Op: MI.getOperand(i: `1`));
565	OutInst.setLoc(MI.getLoc());
566	return true;
567	} // if
568	break;
569	} // case ADD_UW
570	case RISCV::AND: {
571	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
572	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
573	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
574	MI.getOperand(i: `1`).isReg() &&
575	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
576	MI.getOperand(i: `2`).isReg() &&
577	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
578	// c.and $rd, $rs2
579	OutInst.setOpcode(RISCV::C_AND);
580	// Operand: rd_wb
581	OutInst.addOperand(Op: MI.getOperand(i: `1`));
582	// Operand: rd
583	OutInst.addOperand(Op: MI.getOperand(i: `1`));
584	// Operand: rs2
585	OutInst.addOperand(Op: MI.getOperand(i: `2`));
586	OutInst.setLoc(MI.getLoc());
587	return true;
588	} // if
589	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
590	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
591	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
592	MI.getOperand(i: `2`).isReg() &&
593	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
594	MI.getOperand(i: `1`).isReg() &&
595	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
596	// c.and $rd, $rs2
597	OutInst.setOpcode(RISCV::C_AND);
598	// Operand: rd_wb
599	OutInst.addOperand(Op: MI.getOperand(i: `2`));
600	// Operand: rd
601	OutInst.addOperand(Op: MI.getOperand(i: `2`));
602	// Operand: rs2
603	OutInst.addOperand(Op: MI.getOperand(i: `1`));
604	OutInst.setLoc(MI.getLoc());
605	return true;
606	} // if
607	break;
608	} // case AND
609	case RISCV::ANDI: {
610	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
611	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
612	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
613	MI.getOperand(i: `1`).isReg() &&
614	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
615	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
616	// c.andi $rs1, $imm
617	OutInst.setOpcode(RISCV::C_ANDI);
618	// Operand: rd
619	OutInst.addOperand(Op: MI.getOperand(i: `1`));
620	// Operand: rs1
621	OutInst.addOperand(Op: MI.getOperand(i: `1`));
622	// Operand: imm
623	OutInst.addOperand(Op: MI.getOperand(i: `2`));
624	OutInst.setLoc(MI.getLoc());
625	return true;
626	} // if
627	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
628	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
629	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
630	MI.getOperand(i: `2`).isImm() &&
631	(MI.getOperand(i: `2`).getImm() == `255`) &&
632	MI.getOperand(i: `1`).isReg() &&
633	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
634	// c.zext.b $rd
635	OutInst.setOpcode(RISCV::C_ZEXT_B);
636	// Operand: rd_wb
637	OutInst.addOperand(Op: MI.getOperand(i: `1`));
638	// Operand: rd
639	OutInst.addOperand(Op: MI.getOperand(i: `1`));
640	OutInst.setLoc(MI.getLoc());
641	return true;
642	} // if
643	break;
644	} // case ANDI
645	case RISCV::BEQ: {
646	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
647	MI.getOperand(i: `1`).isReg() &&
648	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
649	MI.getOperand(i: `0`).isReg() &&
650	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
651	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / bare_simm9_lsb0 /)) {
652	// c.beqz $rs1, $imm
653	OutInst.setOpcode(RISCV::C_BEQZ);
654	// Operand: rs1
655	OutInst.addOperand(Op: MI.getOperand(i: `0`));
656	// Operand: imm
657	OutInst.addOperand(Op: MI.getOperand(i: `2`));
658	OutInst.setLoc(MI.getLoc());
659	return true;
660	} // if
661	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
662	MI.getOperand(i: `0`).isReg() &&
663	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
664	MI.getOperand(i: `1`).isReg() &&
665	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
666	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / bare_simm9_lsb0 /)) {
667	// c.beqz $rs1, $imm
668	OutInst.setOpcode(RISCV::C_BEQZ);
669	// Operand: rs1
670	OutInst.addOperand(Op: MI.getOperand(i: `1`));
671	// Operand: imm
672	OutInst.addOperand(Op: MI.getOperand(i: `2`));
673	OutInst.setLoc(MI.getLoc());
674	return true;
675	} // if
676	break;
677	} // case BEQ
678	case RISCV::BEXTI: {
679	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
680	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
681	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
682	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
683	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
684	MI.getOperand(i: `1`).isReg() &&
685	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
686	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /)) {
687	// qc.c.bexti $rs1, $shamt
688	OutInst.setOpcode(RISCV::QC_C_BEXTI);
689	// Operand: rd
690	OutInst.addOperand(Op: MI.getOperand(i: `1`));
691	// Operand: rs1
692	OutInst.addOperand(Op: MI.getOperand(i: `1`));
693	// Operand: shamt
694	OutInst.addOperand(Op: MI.getOperand(i: `2`));
695	OutInst.setLoc(MI.getLoc());
696	return true;
697	} // if
698	break;
699	} // case BEXTI
700	case RISCV::BNE: {
701	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
702	MI.getOperand(i: `1`).isReg() &&
703	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
704	MI.getOperand(i: `0`).isReg() &&
705	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
706	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / bare_simm9_lsb0 /)) {
707	// c.bnez $rs1, $imm
708	OutInst.setOpcode(RISCV::C_BNEZ);
709	// Operand: rs1
710	OutInst.addOperand(Op: MI.getOperand(i: `0`));
711	// Operand: imm
712	OutInst.addOperand(Op: MI.getOperand(i: `2`));
713	OutInst.setLoc(MI.getLoc());
714	return true;
715	} // if
716	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
717	MI.getOperand(i: `0`).isReg() &&
718	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
719	MI.getOperand(i: `1`).isReg() &&
720	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
721	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / bare_simm9_lsb0 /)) {
722	// c.bnez $rs1, $imm
723	OutInst.setOpcode(RISCV::C_BNEZ);
724	// Operand: rs1
725	OutInst.addOperand(Op: MI.getOperand(i: `1`));
726	// Operand: imm
727	OutInst.addOperand(Op: MI.getOperand(i: `2`));
728	OutInst.setLoc(MI.getLoc());
729	return true;
730	} // if
731	break;
732	} // case BNE
733	case RISCV::BSETI: {
734	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
735	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
736	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
737	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
738	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
739	MI.getOperand(i: `1`).isReg() &&
740	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
741	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /)) {
742	// qc.c.bseti $rs1, $shamt
743	OutInst.setOpcode(RISCV::QC_C_BSETI);
744	// Operand: rd
745	OutInst.addOperand(Op: MI.getOperand(i: `1`));
746	// Operand: rs1
747	OutInst.addOperand(Op: MI.getOperand(i: `1`));
748	// Operand: shamt
749	OutInst.addOperand(Op: MI.getOperand(i: `2`));
750	OutInst.setLoc(MI.getLoc());
751	return true;
752	} // if
753	break;
754	} // case BSETI
755	case RISCV::EBREAK: {
756	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) {
757	// c.ebreak
758	OutInst.setOpcode(RISCV::C_EBREAK);
759	OutInst.setLoc(MI.getLoc());
760	return true;
761	} // if
762	break;
763	} // case EBREAK
764	case RISCV::FLD: {
765	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
766	MI.getOperand(i: `0`).isReg() &&
767	getRISCVMCRegisterClass(RC: RISCV::FPR64CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
768	MI.getOperand(i: `1`).isReg() &&
769	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
770	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /) &&
771	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000_optional /)) {
772	// c.fld $rd, ${imm}(${rs1})
773	OutInst.setOpcode(RISCV::C_FLD);
774	// Operand: rd
775	OutInst.addOperand(Op: MI.getOperand(i: `0`));
776	// Operand: rs1
777	OutInst.addOperand(Op: MI.getOperand(i: `1`));
778	// Operand: imm
779	OutInst.addOperand(Op: MI.getOperand(i: `2`));
780	OutInst.setLoc(MI.getLoc());
781	return true;
782	} // if
783	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
784	MI.getOperand(i: `0`).isReg() &&
785	getRISCVMCRegisterClass(RC: RISCV::FPR64RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
786	MI.getOperand(i: `1`).isReg() &&
787	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
788	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
789	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000_optional /)) {
790	// c.fldsp $rd, ${imm}(${rs1})
791	OutInst.setOpcode(RISCV::C_FLDSP);
792	// Operand: rd
793	OutInst.addOperand(Op: MI.getOperand(i: `0`));
794	// Operand: rs1
795	OutInst.addOperand(Op: MI.getOperand(i: `1`));
796	// Operand: imm
797	OutInst.addOperand(Op: MI.getOperand(i: `2`));
798	OutInst.setLoc(MI.getLoc());
799	return true;
800	} // if
801	break;
802	} // case FLD
803	case RISCV::FLW: {
804	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
805	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
806	MI.getOperand(i: `0`).isReg() &&
807	getRISCVMCRegisterClass(RC: RISCV::FPR32CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
808	MI.getOperand(i: `1`).isReg() &&
809	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
810	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
811	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm7_lsb00_optional /)) {
812	// c.flw $rd, ${imm}(${rs1})
813	OutInst.setOpcode(RISCV::C_FLW);
814	// Operand: rd
815	OutInst.addOperand(Op: MI.getOperand(i: `0`));
816	// Operand: rs1
817	OutInst.addOperand(Op: MI.getOperand(i: `1`));
818	// Operand: imm
819	OutInst.addOperand(Op: MI.getOperand(i: `2`));
820	OutInst.setLoc(MI.getLoc());
821	return true;
822	} // if
823	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
824	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
825	MI.getOperand(i: `0`).isReg() &&
826	getRISCVMCRegisterClass(RC: RISCV::FPR32RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
827	MI.getOperand(i: `1`).isReg() &&
828	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
829	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm8_lsb00 /) &&
830	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm8_lsb00_optional /)) {
831	// c.flwsp $rd, ${imm}(${rs1})
832	OutInst.setOpcode(RISCV::C_FLWSP);
833	// Operand: rd
834	OutInst.addOperand(Op: MI.getOperand(i: `0`));
835	// Operand: rs1
836	OutInst.addOperand(Op: MI.getOperand(i: `1`));
837	// Operand: imm
838	OutInst.addOperand(Op: MI.getOperand(i: `2`));
839	OutInst.setLoc(MI.getLoc());
840	return true;
841	} // if
842	break;
843	} // case FLW
844	case RISCV::FSD: {
845	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
846	MI.getOperand(i: `0`).isReg() &&
847	getRISCVMCRegisterClass(RC: RISCV::FPR64CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
848	MI.getOperand(i: `1`).isReg() &&
849	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
850	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /) &&
851	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000_optional /)) {
852	// c.fsd $rs2, ${imm}(${rs1})
853	OutInst.setOpcode(RISCV::C_FSD);
854	// Operand: rs2
855	OutInst.addOperand(Op: MI.getOperand(i: `0`));
856	// Operand: rs1
857	OutInst.addOperand(Op: MI.getOperand(i: `1`));
858	// Operand: imm
859	OutInst.addOperand(Op: MI.getOperand(i: `2`));
860	OutInst.setLoc(MI.getLoc());
861	return true;
862	} // if
863	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
864	MI.getOperand(i: `0`).isReg() &&
865	getRISCVMCRegisterClass(RC: RISCV::FPR64RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
866	MI.getOperand(i: `1`).isReg() &&
867	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
868	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
869	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000_optional /)) {
870	// c.fsdsp $rs2, ${imm}(${rs1})
871	OutInst.setOpcode(RISCV::C_FSDSP);
872	// Operand: rs2
873	OutInst.addOperand(Op: MI.getOperand(i: `0`));
874	// Operand: rs1
875	OutInst.addOperand(Op: MI.getOperand(i: `1`));
876	// Operand: imm
877	OutInst.addOperand(Op: MI.getOperand(i: `2`));
878	OutInst.setLoc(MI.getLoc());
879	return true;
880	} // if
881	break;
882	} // case FSD
883	case RISCV::FSW: {
884	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
885	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
886	MI.getOperand(i: `0`).isReg() &&
887	getRISCVMCRegisterClass(RC: RISCV::FPR32CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
888	MI.getOperand(i: `1`).isReg() &&
889	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
890	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
891	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm7_lsb00_optional /)) {
892	// c.fsw $rs2, ${imm}(${rs1})
893	OutInst.setOpcode(RISCV::C_FSW);
894	// Operand: rs2
895	OutInst.addOperand(Op: MI.getOperand(i: `0`));
896	// Operand: rs1
897	OutInst.addOperand(Op: MI.getOperand(i: `1`));
898	// Operand: imm
899	OutInst.addOperand(Op: MI.getOperand(i: `2`));
900	OutInst.setLoc(MI.getLoc());
901	return true;
902	} // if
903	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
904	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
905	MI.getOperand(i: `0`).isReg() &&
906	getRISCVMCRegisterClass(RC: RISCV::FPR32RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
907	MI.getOperand(i: `1`).isReg() &&
908	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
909	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm8_lsb00 /) &&
910	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm8_lsb00_optional /)) {
911	// c.fswsp $rs2, ${imm}(${rs1})
912	OutInst.setOpcode(RISCV::C_FSWSP);
913	// Operand: rs2
914	OutInst.addOperand(Op: MI.getOperand(i: `0`));
915	// Operand: rs1
916	OutInst.addOperand(Op: MI.getOperand(i: `1`));
917	// Operand: imm
918	OutInst.addOperand(Op: MI.getOperand(i: `2`));
919	OutInst.setLoc(MI.getLoc());
920	return true;
921	} // if
922	break;
923	} // case FSW
924	case RISCV::JAL: {
925	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
926	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
927	MI.getOperand(i: `0`).isReg() &&
928	(MI.getOperand(i: `0`).getReg() == RISCV::X1) &&
929	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `15` / bare_simm12_lsb0 /)) {
930	// c.jal $offset
931	OutInst.setOpcode(RISCV::C_JAL);
932	// Operand: offset
933	OutInst.addOperand(Op: MI.getOperand(i: `1`));
934	OutInst.setLoc(MI.getLoc());
935	return true;
936	} // if
937	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
938	MI.getOperand(i: `0`).isReg() &&
939	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
940	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `15` / bare_simm12_lsb0 /)) {
941	// c.j $offset
942	OutInst.setOpcode(RISCV::C_J);
943	// Operand: offset
944	OutInst.addOperand(Op: MI.getOperand(i: `1`));
945	OutInst.setLoc(MI.getLoc());
946	return true;
947	} // if
948	break;
949	} // case JAL
950	case RISCV::JALR: {
951	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
952	MI.getOperand(i: `0`).isReg() &&
953	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
954	MI.getOperand(i: `2`).isImm() &&
955	(MI.getOperand(i: `2`).getImm() == `0`) &&
956	MI.getOperand(i: `1`).isReg() &&
957	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
958	// c.jr $rs1
959	OutInst.setOpcode(RISCV::C_JR);
960	// Operand: rs1
961	OutInst.addOperand(Op: MI.getOperand(i: `1`));
962	OutInst.setLoc(MI.getLoc());
963	return true;
964	} // if
965	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
966	MI.getOperand(i: `0`).isReg() &&
967	(MI.getOperand(i: `0`).getReg() == RISCV::X1) &&
968	MI.getOperand(i: `2`).isImm() &&
969	(MI.getOperand(i: `2`).getImm() == `0`) &&
970	MI.getOperand(i: `1`).isReg() &&
971	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
972	// c.jalr $rs1
973	OutInst.setOpcode(RISCV::C_JALR);
974	// Operand: rs1
975	OutInst.addOperand(Op: MI.getOperand(i: `1`));
976	OutInst.setLoc(MI.getLoc());
977	return true;
978	} // if
979	break;
980	} // case JALR
981	case RISCV::LBU: {
982	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
983	MI.getOperand(i: `0`).isReg() &&
984	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
985	MI.getOperand(i: `1`).isReg() &&
986	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
987	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm2 /) &&
988	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `17` / uimm2_optional /)) {
989	// c.lbu $rd, ${imm}(${rs1})
990	OutInst.setOpcode(RISCV::C_LBU);
991	// Operand: rd
992	OutInst.addOperand(Op: MI.getOperand(i: `0`));
993	// Operand: rs1
994	OutInst.addOperand(Op: MI.getOperand(i: `1`));
995	// Operand: imm
996	OutInst.addOperand(Op: MI.getOperand(i: `2`));
997	OutInst.setLoc(MI.getLoc());
998	return true;
999	} // if
1000	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1001	MI.getOperand(i: `0`).isReg() &&
1002	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1003	MI.getOperand(i: `1`).isReg() &&
1004	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1005	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `18` / uimm5 /) &&
1006	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19` / uimm5_optional /)) {
1007	// qk.c.lbu $rd, ${imm}(${rs1})
1008	OutInst.setOpcode(RISCV::QK_C_LBU);
1009	// Operand: rd
1010	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1011	// Operand: rs1
1012	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1013	// Operand: imm
1014	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1015	OutInst.setLoc(MI.getLoc());
1016	return true;
1017	} // if
1018	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1019	MI.getOperand(i: `0`).isReg() &&
1020	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1021	MI.getOperand(i: `1`).isReg() &&
1022	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1023	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimm4 /) &&
1024	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21` / uimm4_optional /)) {
1025	// qk.c.lbusp $rd_rs2, ${imm}(${rs1})
1026	OutInst.setOpcode(RISCV::QK_C_LBUSP);
1027	// Operand: rd_rs2
1028	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1029	// Operand: rs1
1030	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1031	// Operand: imm
1032	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1033	OutInst.setLoc(MI.getLoc());
1034	return true;
1035	} // if
1036	break;
1037	} // case LBU
1038	case RISCV::LD: {
1039	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1040	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1041	MI.getOperand(i: `0`).isReg() &&
1042	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1043	MI.getOperand(i: `1`).isReg() &&
1044	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1045	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /) &&
1046	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000_optional /)) {
1047	// c.ld $rd, ${imm}(${rs1})
1048	OutInst.setOpcode(RISCV::C_LD);
1049	// Operand: rd
1050	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1051	// Operand: rs1
1052	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1053	// Operand: imm
1054	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1055	OutInst.setLoc(MI.getLoc());
1056	return true;
1057	} // if
1058	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1059	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1060	MI.getOperand(i: `0`).isReg() &&
1061	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1062	MI.getOperand(i: `1`).isReg() &&
1063	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1064	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
1065	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000_optional /)) {
1066	// c.ldsp $rd, ${imm}(${rs1})
1067	OutInst.setOpcode(RISCV::C_LDSP);
1068	// Operand: rd
1069	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1070	// Operand: rs1
1071	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1072	// Operand: imm
1073	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1074	OutInst.setLoc(MI.getLoc());
1075	return true;
1076	} // if
1077	break;
1078	} // case LD
1079	case RISCV::LD_RV32: {
1080	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
1081	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1082	MI.getOperand(i: `0`).isReg() &&
1083	getRISCVMCRegisterClass(RC: RISCV::GPRPairNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1084	MI.getOperand(i: `1`).isReg() &&
1085	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1086	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
1087	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000_optional /)) {
1088	// c.ldsp $rd, ${imm}(${rs1})
1089	OutInst.setOpcode(RISCV::C_LDSP_RV32);
1090	// Operand: rd
1091	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1092	// Operand: rs1
1093	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1094	// Operand: imm
1095	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1096	OutInst.setLoc(MI.getLoc());
1097	return true;
1098	} // if
1099	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
1100	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1101	MI.getOperand(i: `0`).isReg() &&
1102	getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1103	MI.getOperand(i: `1`).isReg() &&
1104	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1105	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /) &&
1106	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000_optional /)) {
1107	// c.ld $rd, ${imm}(${rs1})
1108	OutInst.setOpcode(RISCV::C_LD_RV32);
1109	// Operand: rd
1110	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1111	// Operand: rs1
1112	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1113	// Operand: imm
1114	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1115	OutInst.setLoc(MI.getLoc());
1116	return true;
1117	} // if
1118	break;
1119	} // case LD_RV32
1120	case RISCV::LH: {
1121	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1122	MI.getOperand(i: `0`).isReg() &&
1123	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1124	MI.getOperand(i: `1`).isReg() &&
1125	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1126	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm2_lsb0 /) &&
1127	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm2_lsb0_optional /)) {
1128	// c.lh $rd, ${imm}(${rs1})
1129	OutInst.setOpcode(RISCV::C_LH);
1130	// Operand: rd
1131	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1132	// Operand: rs1
1133	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1134	// Operand: imm
1135	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1136	OutInst.setLoc(MI.getLoc());
1137	return true;
1138	} // if
1139	break;
1140	} // case LH
1141	case RISCV::LHU: {
1142	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1143	MI.getOperand(i: `0`).isReg() &&
1144	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1145	MI.getOperand(i: `1`).isReg() &&
1146	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1147	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm2_lsb0 /) &&
1148	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm2_lsb0_optional /)) {
1149	// c.lhu $rd, ${imm}(${rs1})
1150	OutInst.setOpcode(RISCV::C_LHU);
1151	// Operand: rd
1152	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1153	// Operand: rs1
1154	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1155	// Operand: imm
1156	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1157	OutInst.setLoc(MI.getLoc());
1158	return true;
1159	} // if
1160	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1161	MI.getOperand(i: `0`).isReg() &&
1162	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1163	MI.getOperand(i: `1`).isReg() &&
1164	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1165	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24` / uimm6_lsb0 /) &&
1166	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `25` / uimm6_lsb0_optional /)) {
1167	// qk.c.lhu $rd, ${imm}(${rs1})
1168	OutInst.setOpcode(RISCV::QK_C_LHU);
1169	// Operand: rd
1170	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1171	// Operand: rs1
1172	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1173	// Operand: imm
1174	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1175	OutInst.setLoc(MI.getLoc());
1176	return true;
1177	} // if
1178	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1179	MI.getOperand(i: `0`).isReg() &&
1180	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1181	MI.getOperand(i: `1`).isReg() &&
1182	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1183	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `26` / uimm5_lsb0 /) &&
1184	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimm5_lsb0_optional /)) {
1185	// qk.c.lhusp $rd_rs2, ${imm}(${rs1})
1186	OutInst.setOpcode(RISCV::QK_C_LHUSP);
1187	// Operand: rd_rs2
1188	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1189	// Operand: rs1
1190	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1191	// Operand: imm
1192	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1193	OutInst.setLoc(MI.getLoc());
1194	return true;
1195	} // if
1196	break;
1197	} // case LHU
1198	case RISCV::LH_INX: {
1199	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1200	MI.getOperand(i: `0`).isReg() &&
1201	getRISCVMCRegisterClass(RC: RISCV::GPRF16CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1202	MI.getOperand(i: `1`).isReg() &&
1203	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1204	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm2_lsb0 /) &&
1205	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm2_lsb0_optional /)) {
1206	// c.lh $rd, ${imm}(${rs1})
1207	OutInst.setOpcode(RISCV::C_LH_INX);
1208	// Operand: rd
1209	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1210	// Operand: rs1
1211	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1212	// Operand: imm
1213	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1214	OutInst.setLoc(MI.getLoc());
1215	return true;
1216	} // if
1217	break;
1218	} // case LH_INX
1219	case RISCV::LUI: {
1220	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1221	MI.getOperand(i: `0`).isReg() &&
1222	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0X2RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1223	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `28` / c_lui_imm /)) {
1224	// c.lui $rd, $imm
1225	OutInst.setOpcode(RISCV::C_LUI);
1226	// Operand: rd
1227	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1228	// Operand: imm
1229	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1230	OutInst.setLoc(MI.getLoc());
1231	return true;
1232	} // if
1233	break;
1234	} // case LUI
1235	case RISCV::LW: {
1236	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1237	MI.getOperand(i: `0`).isReg() &&
1238	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1239	MI.getOperand(i: `1`).isReg() &&
1240	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1241	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
1242	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm7_lsb00_optional /)) {
1243	// c.lw $rd, ${imm}(${rs1})
1244	OutInst.setOpcode(RISCV::C_LW);
1245	// Operand: rd
1246	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1247	// Operand: rs1
1248	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1249	// Operand: imm
1250	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1251	OutInst.setLoc(MI.getLoc());
1252	return true;
1253	} // if
1254	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1255	MI.getOperand(i: `0`).isReg() &&
1256	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1257	MI.getOperand(i: `1`).isReg() &&
1258	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1259	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm8_lsb00 /) &&
1260	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm8_lsb00_optional /)) {
1261	// c.lwsp $rd, ${imm}(${rs1})
1262	OutInst.setOpcode(RISCV::C_LWSP);
1263	// Operand: rd
1264	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1265	// Operand: rs1
1266	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1267	// Operand: imm
1268	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1269	OutInst.setLoc(MI.getLoc());
1270	return true;
1271	} // if
1272	break;
1273	} // case LW
1274	case RISCV::LW_INX: {
1275	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1276	MI.getOperand(i: `0`).isReg() &&
1277	getRISCVMCRegisterClass(RC: RISCV::GPRF32CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1278	MI.getOperand(i: `1`).isReg() &&
1279	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1280	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
1281	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm7_lsb00_optional /)) {
1282	// c.lw $rd, ${imm}(${rs1})
1283	OutInst.setOpcode(RISCV::C_LW_INX);
1284	// Operand: rd
1285	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1286	// Operand: rs1
1287	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1288	// Operand: imm
1289	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1290	OutInst.setLoc(MI.getLoc());
1291	return true;
1292	} // if
1293	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1294	MI.getOperand(i: `0`).isReg() &&
1295	getRISCVMCRegisterClass(RC: RISCV::GPRF32NoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1296	MI.getOperand(i: `1`).isReg() &&
1297	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1298	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm8_lsb00 /) &&
1299	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm8_lsb00_optional /)) {
1300	// c.lwsp $rd, ${imm}(${rs1})
1301	OutInst.setOpcode(RISCV::C_LWSP_INX);
1302	// Operand: rd
1303	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1304	// Operand: rs1
1305	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1306	// Operand: imm
1307	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1308	OutInst.setLoc(MI.getLoc());
1309	return true;
1310	} // if
1311	break;
1312	} // case LW_INX
1313	case RISCV::MUL: {
1314	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1315	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
1316	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1317	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1318	MI.getOperand(i: `1`).isReg() &&
1319	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1320	MI.getOperand(i: `2`).isReg() &&
1321	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
1322	// c.mul $rd, $rs2
1323	OutInst.setOpcode(RISCV::C_MUL);
1324	// Operand: rd_wb
1325	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1326	// Operand: rd
1327	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1328	// Operand: rs2
1329	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1330	OutInst.setLoc(MI.getLoc());
1331	return true;
1332	} // if
1333	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1334	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
1335	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
1336	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1337	MI.getOperand(i: `2`).isReg() &&
1338	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
1339	MI.getOperand(i: `1`).isReg() &&
1340	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
1341	// c.mul $rd, $rs2
1342	OutInst.setOpcode(RISCV::C_MUL);
1343	// Operand: rd_wb
1344	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1345	// Operand: rd
1346	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1347	// Operand: rs2
1348	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1349	OutInst.setLoc(MI.getLoc());
1350	return true;
1351	} // if
1352	break;
1353	} // case MUL
1354	case RISCV::OR: {
1355	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1356	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1357	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1358	MI.getOperand(i: `1`).isReg() &&
1359	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1360	MI.getOperand(i: `2`).isReg() &&
1361	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
1362	// c.or $rd, $rs2
1363	OutInst.setOpcode(RISCV::C_OR);
1364	// Operand: rd_wb
1365	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1366	// Operand: rd
1367	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1368	// Operand: rs2
1369	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1370	OutInst.setLoc(MI.getLoc());
1371	return true;
1372	} // if
1373	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1374	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
1375	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1376	MI.getOperand(i: `2`).isReg() &&
1377	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
1378	MI.getOperand(i: `1`).isReg() &&
1379	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
1380	// c.or $rd, $rs2
1381	OutInst.setOpcode(RISCV::C_OR);
1382	// Operand: rd_wb
1383	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1384	// Operand: rd
1385	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1386	// Operand: rs2
1387	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1388	OutInst.setLoc(MI.getLoc());
1389	return true;
1390	} // if
1391	break;
1392	} // case OR
1393	case RISCV::QC_EXTU: {
1394	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
1395	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1396	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1397	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1398	MI.getOperand(i: `3`).isImm() &&
1399	(MI.getOperand(i: `3`).getImm() == `0`) &&
1400	MI.getOperand(i: `1`).isReg() &&
1401	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1402	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `29` / uimm5ge6_plus1 /)) {
1403	// qc.c.extu $rd, $width
1404	OutInst.setOpcode(RISCV::QC_C_EXTU);
1405	// Operand: rd_wb
1406	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1407	// Operand: rd
1408	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1409	// Operand: width
1410	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1411	OutInst.setLoc(MI.getLoc());
1412	return true;
1413	} // if
1414	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
1415	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
1416	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1417	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1418	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1419	MI.getOperand(i: `2`).isImm() &&
1420	(MI.getOperand(i: `2`).getImm() == `1`) &&
1421	MI.getOperand(i: `1`).isReg() &&
1422	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1423	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `3`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /)) {
1424	// qc.c.bexti $rs1, $shamt
1425	OutInst.setOpcode(RISCV::QC_C_BEXTI);
1426	// Operand: rd
1427	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1428	// Operand: rs1
1429	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1430	// Operand: shamt
1431	OutInst.addOperand(Op: MI.getOperand(i: `3`));
1432	OutInst.setLoc(MI.getLoc());
1433	return true;
1434	} // if
1435	break;
1436	} // case QC_EXTU
1437	case RISCV::QC_E_ADDAI: {
1438	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1439	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1440	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1441	MI.getOperand(i: `0`).isReg() &&
1442	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1443	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm6nonzero /) &&
1444	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
1445	// c.addi $rd, $imm
1446	OutInst.setOpcode(RISCV::C_ADDI);
1447	// Operand: rd_wb
1448	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1449	// Operand: rd
1450	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1451	// Operand: imm
1452	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1453	OutInst.setLoc(MI.getLoc());
1454	return true;
1455	} // if
1456	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1457	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1458	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1459	MI.getOperand(i: `0`).isReg() &&
1460	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
1461	MI.getOperand(i: `1`).isReg() &&
1462	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
1463	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4` / simm10_lsb0000nonzero /)) {
1464	// c.addi16sp $rd, $imm
1465	OutInst.setOpcode(RISCV::C_ADDI16SP);
1466	// Operand: rd_wb
1467	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1468	// Operand: rd
1469	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1470	// Operand: imm
1471	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1472	OutInst.setLoc(MI.getLoc());
1473	return true;
1474	} // if
1475	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1476	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1477	MI.getOperand(i: `0`).isReg() &&
1478	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1479	MI.getOperand(i: `0`).isReg() &&
1480	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1481	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /)) {
1482	// addi $rd, $rs1, $imm12
1483	OutInst.setOpcode(RISCV::ADDI);
1484	// Operand: rd
1485	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1486	// Operand: rs1
1487	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1488	// Operand: imm12
1489	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1490	OutInst.setLoc(MI.getLoc());
1491	return true;
1492	} // if
1493	break;
1494	} // case QC_E_ADDAI
1495	case RISCV::QC_E_ADDI: {
1496	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1497	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1498	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1499	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1500	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1501	MI.getOperand(i: `1`).isReg() &&
1502	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1503	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm6nonzero /) &&
1504	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
1505	// c.addi $rd, $imm
1506	OutInst.setOpcode(RISCV::C_ADDI);
1507	// Operand: rd_wb
1508	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1509	// Operand: rd
1510	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1511	// Operand: imm
1512	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1513	OutInst.setLoc(MI.getLoc());
1514	return true;
1515	} // if
1516	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1517	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1518	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1519	MI.getOperand(i: `2`).isImm() &&
1520	(MI.getOperand(i: `2`).getImm() == `0`) &&
1521	MI.getOperand(i: `0`).isReg() &&
1522	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1523	MI.getOperand(i: `1`).isReg() &&
1524	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
1525	// c.mv $rs1, $rs2
1526	OutInst.setOpcode(RISCV::C_MV);
1527	// Operand: rs1
1528	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1529	// Operand: rs2
1530	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1531	OutInst.setLoc(MI.getLoc());
1532	return true;
1533	} // if
1534	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1535	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1536	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1537	MI.getOperand(i: `0`).isReg() &&
1538	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
1539	MI.getOperand(i: `1`).isReg() &&
1540	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
1541	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4` / simm10_lsb0000nonzero /)) {
1542	// c.addi16sp $rd, $imm
1543	OutInst.setOpcode(RISCV::C_ADDI16SP);
1544	// Operand: rd_wb
1545	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1546	// Operand: rd
1547	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1548	// Operand: imm
1549	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1550	OutInst.setLoc(MI.getLoc());
1551	return true;
1552	} // if
1553	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1554	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1555	MI.getOperand(i: `0`).isReg() &&
1556	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1557	MI.getOperand(i: `1`).isReg() &&
1558	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1559	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /)) {
1560	// addi $rd, $rs1, $imm12
1561	OutInst.setOpcode(RISCV::ADDI);
1562	// Operand: rd
1563	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1564	// Operand: rs1
1565	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1566	// Operand: imm12
1567	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1568	OutInst.setLoc(MI.getLoc());
1569	return true;
1570	} // if
1571	break;
1572	} // case QC_E_ADDI
1573	case RISCV::QC_E_ANDAI: {
1574	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1575	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1576	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1577	MI.getOperand(i: `0`).isReg() &&
1578	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1579	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
1580	// c.andi $rs1, $imm
1581	OutInst.setOpcode(RISCV::C_ANDI);
1582	// Operand: rd
1583	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1584	// Operand: rs1
1585	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1586	// Operand: imm
1587	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1588	OutInst.setLoc(MI.getLoc());
1589	return true;
1590	} // if
1591	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1592	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1593	MI.getOperand(i: `0`).isReg() &&
1594	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1595	MI.getOperand(i: `0`).isReg() &&
1596	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1597	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /)) {
1598	// andi $rd, $rs1, $imm12
1599	OutInst.setOpcode(RISCV::ANDI);
1600	// Operand: rd
1601	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1602	// Operand: rs1
1603	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1604	// Operand: imm12
1605	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1606	OutInst.setLoc(MI.getLoc());
1607	return true;
1608	} // if
1609	break;
1610	} // case QC_E_ANDAI
1611	case RISCV::QC_E_ANDI: {
1612	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1613	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1614	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1615	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1616	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1617	MI.getOperand(i: `1`).isReg() &&
1618	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1619	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
1620	// c.andi $rs1, $imm
1621	OutInst.setOpcode(RISCV::C_ANDI);
1622	// Operand: rd
1623	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1624	// Operand: rs1
1625	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1626	// Operand: imm
1627	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1628	OutInst.setLoc(MI.getLoc());
1629	return true;
1630	} // if
1631	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1632	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1633	MI.getOperand(i: `0`).isReg() &&
1634	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1635	MI.getOperand(i: `1`).isReg() &&
1636	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1637	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /)) {
1638	// andi $rd, $rs1, $imm12
1639	OutInst.setOpcode(RISCV::ANDI);
1640	// Operand: rd
1641	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1642	// Operand: rs1
1643	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1644	// Operand: imm12
1645	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1646	OutInst.setLoc(MI.getLoc());
1647	return true;
1648	} // if
1649	break;
1650	} // case QC_E_ANDI
1651	case RISCV::QC_E_BEQI: {
1652	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1653	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1654	MI.getOperand(i: `0`).isReg() &&
1655	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1656	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `31` / simm5nonzero /) &&
1657	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `32` / bare_simm13_lsb0 /)) {
1658	// qc.beqi $rs1, $rs2, $imm12
1659	OutInst.setOpcode(RISCV::QC_BEQI);
1660	// Operand: rs1
1661	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1662	// Operand: rs2
1663	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1664	// Operand: imm12
1665	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1666	OutInst.setLoc(MI.getLoc());
1667	return true;
1668	} // if
1669	break;
1670	} // case QC_E_BEQI
1671	case RISCV::QC_E_BGEI: {
1672	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1673	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1674	MI.getOperand(i: `0`).isReg() &&
1675	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1676	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `31` / simm5nonzero /) &&
1677	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `32` / bare_simm13_lsb0 /)) {
1678	// qc.bgei $rs1, $rs2, $imm12
1679	OutInst.setOpcode(RISCV::QC_BGEI);
1680	// Operand: rs1
1681	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1682	// Operand: rs2
1683	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1684	// Operand: imm12
1685	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1686	OutInst.setLoc(MI.getLoc());
1687	return true;
1688	} // if
1689	break;
1690	} // case QC_E_BGEI
1691	case RISCV::QC_E_BGEUI: {
1692	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1693	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1694	MI.getOperand(i: `0`).isReg() &&
1695	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1696	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `33` / uimm5nonzero /) &&
1697	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `32` / bare_simm13_lsb0 /)) {
1698	// qc.bgeui $rs1, $rs2, $imm12
1699	OutInst.setOpcode(RISCV::QC_BGEUI);
1700	// Operand: rs1
1701	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1702	// Operand: rs2
1703	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1704	// Operand: imm12
1705	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1706	OutInst.setLoc(MI.getLoc());
1707	return true;
1708	} // if
1709	break;
1710	} // case QC_E_BGEUI
1711	case RISCV::QC_E_BLTI: {
1712	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1713	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1714	MI.getOperand(i: `0`).isReg() &&
1715	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1716	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `31` / simm5nonzero /) &&
1717	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `32` / bare_simm13_lsb0 /)) {
1718	// qc.blti $rs1, $rs2, $imm12
1719	OutInst.setOpcode(RISCV::QC_BLTI);
1720	// Operand: rs1
1721	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1722	// Operand: rs2
1723	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1724	// Operand: imm12
1725	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1726	OutInst.setLoc(MI.getLoc());
1727	return true;
1728	} // if
1729	break;
1730	} // case QC_E_BLTI
1731	case RISCV::QC_E_BLTUI: {
1732	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1733	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1734	MI.getOperand(i: `0`).isReg() &&
1735	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1736	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `33` / uimm5nonzero /) &&
1737	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `32` / bare_simm13_lsb0 /)) {
1738	// qc.bltui $rs1, $rs2, $imm12
1739	OutInst.setOpcode(RISCV::QC_BLTUI);
1740	// Operand: rs1
1741	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1742	// Operand: rs2
1743	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1744	// Operand: imm12
1745	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1746	OutInst.setLoc(MI.getLoc());
1747	return true;
1748	} // if
1749	break;
1750	} // case QC_E_BLTUI
1751	case RISCV::QC_E_BNEI: {
1752	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1753	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1754	MI.getOperand(i: `0`).isReg() &&
1755	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1756	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `31` / simm5nonzero /) &&
1757	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `32` / bare_simm13_lsb0 /)) {
1758	// qc.bnei $rs1, $rs2, $imm12
1759	OutInst.setOpcode(RISCV::QC_BNEI);
1760	// Operand: rs1
1761	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1762	// Operand: rs2
1763	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1764	// Operand: imm12
1765	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1766	OutInst.setLoc(MI.getLoc());
1767	return true;
1768	} // if
1769	break;
1770	} // case QC_E_BNEI
1771	case RISCV::QC_E_J: {
1772	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1773	STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1774	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1775	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `15` / bare_simm12_lsb0 /)) {
1776	// c.j $offset
1777	OutInst.setOpcode(RISCV::C_J);
1778	// Operand: offset
1779	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1780	OutInst.setLoc(MI.getLoc());
1781	return true;
1782	} // if
1783	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1784	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1785	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `34` / simm21_lsb0_jal /)) {
1786	// jal $rd, $imm20
1787	OutInst.setOpcode(RISCV::JAL);
1788	// Operand: rd
1789	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
1790	// Operand: imm20
1791	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1792	OutInst.setLoc(MI.getLoc());
1793	return true;
1794	} // if
1795	break;
1796	} // case QC_E_J
1797	case RISCV::QC_E_JAL: {
1798	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1799	STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1800	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1801	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `15` / bare_simm12_lsb0 /)) {
1802	// c.jal $offset
1803	OutInst.setOpcode(RISCV::C_JAL);
1804	// Operand: offset
1805	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1806	OutInst.setLoc(MI.getLoc());
1807	return true;
1808	} // if
1809	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1810	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1811	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `34` / simm21_lsb0_jal /)) {
1812	// jal $rd, $imm20
1813	OutInst.setOpcode(RISCV::JAL);
1814	// Operand: rd
1815	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
1816	// Operand: imm20
1817	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1818	OutInst.setLoc(MI.getLoc());
1819	return true;
1820	} // if
1821	break;
1822	} // case QC_E_JAL
1823	case RISCV::QC_E_LB: {
1824	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1825	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1826	MI.getOperand(i: `0`).isReg() &&
1827	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1828	MI.getOperand(i: `1`).isReg() &&
1829	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1830	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /) &&
1831	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `35` / simm12_lo_optional /)) {
1832	// lb $rd, ${imm12}(${rs1})
1833	OutInst.setOpcode(RISCV::LB);
1834	// Operand: rd
1835	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1836	// Operand: rs1
1837	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1838	// Operand: imm12
1839	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1840	OutInst.setLoc(MI.getLoc());
1841	return true;
1842	} // if
1843	break;
1844	} // case QC_E_LB
1845	case RISCV::QC_E_LBU: {
1846	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1847	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1848	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1849	MI.getOperand(i: `0`).isReg() &&
1850	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1851	MI.getOperand(i: `1`).isReg() &&
1852	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1853	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm2 /) &&
1854	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `17` / uimm2_optional /)) {
1855	// c.lbu $rd, ${imm}(${rs1})
1856	OutInst.setOpcode(RISCV::C_LBU);
1857	// Operand: rd
1858	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1859	// Operand: rs1
1860	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1861	// Operand: imm
1862	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1863	OutInst.setLoc(MI.getLoc());
1864	return true;
1865	} // if
1866	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1867	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1868	MI.getOperand(i: `0`).isReg() &&
1869	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1870	MI.getOperand(i: `1`).isReg() &&
1871	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1872	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /) &&
1873	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `35` / simm12_lo_optional /)) {
1874	// lbu $rd, ${imm12}(${rs1})
1875	OutInst.setOpcode(RISCV::LBU);
1876	// Operand: rd
1877	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1878	// Operand: rs1
1879	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1880	// Operand: imm12
1881	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1882	OutInst.setLoc(MI.getLoc());
1883	return true;
1884	} // if
1885	break;
1886	} // case QC_E_LBU
1887	case RISCV::QC_E_LH: {
1888	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1889	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1890	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1891	MI.getOperand(i: `0`).isReg() &&
1892	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1893	MI.getOperand(i: `1`).isReg() &&
1894	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1895	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm2_lsb0 /) &&
1896	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm2_lsb0_optional /)) {
1897	// c.lh $rd, ${imm}(${rs1})
1898	OutInst.setOpcode(RISCV::C_LH);
1899	// Operand: rd
1900	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1901	// Operand: rs1
1902	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1903	// Operand: imm
1904	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1905	OutInst.setLoc(MI.getLoc());
1906	return true;
1907	} // if
1908	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1909	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1910	MI.getOperand(i: `0`).isReg() &&
1911	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1912	MI.getOperand(i: `1`).isReg() &&
1913	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1914	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /) &&
1915	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `35` / simm12_lo_optional /)) {
1916	// lh $rd, ${imm12}(${rs1})
1917	OutInst.setOpcode(RISCV::LH);
1918	// Operand: rd
1919	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1920	// Operand: rs1
1921	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1922	// Operand: imm12
1923	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1924	OutInst.setLoc(MI.getLoc());
1925	return true;
1926	} // if
1927	break;
1928	} // case QC_E_LH
1929	case RISCV::QC_E_LHU: {
1930	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1931	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1932	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1933	MI.getOperand(i: `0`).isReg() &&
1934	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1935	MI.getOperand(i: `1`).isReg() &&
1936	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1937	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm2_lsb0 /) &&
1938	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm2_lsb0_optional /)) {
1939	// c.lhu $rd, ${imm}(${rs1})
1940	OutInst.setOpcode(RISCV::C_LHU);
1941	// Operand: rd
1942	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1943	// Operand: rs1
1944	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1945	// Operand: imm
1946	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1947	OutInst.setLoc(MI.getLoc());
1948	return true;
1949	} // if
1950	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1951	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1952	MI.getOperand(i: `0`).isReg() &&
1953	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1954	MI.getOperand(i: `1`).isReg() &&
1955	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1956	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /) &&
1957	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `35` / simm12_lo_optional /)) {
1958	// lhu $rd, ${imm12}(${rs1})
1959	OutInst.setOpcode(RISCV::LHU);
1960	// Operand: rd
1961	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1962	// Operand: rs1
1963	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1964	// Operand: imm12
1965	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1966	OutInst.setLoc(MI.getLoc());
1967	return true;
1968	} // if
1969	break;
1970	} // case QC_E_LHU
1971	case RISCV::QC_E_LI: {
1972	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
1973	STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
1974	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1975	MI.getOperand(i: `0`).isReg() &&
1976	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1977	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `3` / simm6 /)) {
1978	// c.li $rd, $imm
1979	OutInst.setOpcode(RISCV::C_LI);
1980	// Operand: rd
1981	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1982	// Operand: imm
1983	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1984	OutInst.setLoc(MI.getLoc());
1985	return true;
1986	} // if
1987	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
1988	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1989	MI.getOperand(i: `0`).isReg() &&
1990	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1991	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `36` / simm20_li /)) {
1992	// qc.li $rd, $imm20
1993	OutInst.setOpcode(RISCV::QC_LI);
1994	// Operand: rd
1995	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1996	// Operand: imm20
1997	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1998	OutInst.setLoc(MI.getLoc());
1999	return true;
2000	} // if
2001	break;
2002	} // case QC_E_LI
2003	case RISCV::QC_E_LW: {
2004	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2005	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2006	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2007	MI.getOperand(i: `0`).isReg() &&
2008	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2009	MI.getOperand(i: `1`).isReg() &&
2010	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2011	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
2012	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm7_lsb00_optional /)) {
2013	// c.lw $rd, ${imm}(${rs1})
2014	OutInst.setOpcode(RISCV::C_LW);
2015	// Operand: rd
2016	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2017	// Operand: rs1
2018	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2019	// Operand: imm
2020	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2021	OutInst.setLoc(MI.getLoc());
2022	return true;
2023	} // if
2024	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2025	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2026	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2027	MI.getOperand(i: `0`).isReg() &&
2028	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2029	MI.getOperand(i: `1`).isReg() &&
2030	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2031	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm8_lsb00 /) &&
2032	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm8_lsb00_optional /)) {
2033	// c.lwsp $rd, ${imm}(${rs1})
2034	OutInst.setOpcode(RISCV::C_LWSP);
2035	// Operand: rd
2036	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2037	// Operand: rs1
2038	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2039	// Operand: imm
2040	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2041	OutInst.setLoc(MI.getLoc());
2042	return true;
2043	} // if
2044	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2045	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2046	MI.getOperand(i: `0`).isReg() &&
2047	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2048	MI.getOperand(i: `1`).isReg() &&
2049	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2050	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /) &&
2051	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `35` / simm12_lo_optional /)) {
2052	// lw $rd, ${imm12}(${rs1})
2053	OutInst.setOpcode(RISCV::LW);
2054	// Operand: rd
2055	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2056	// Operand: rs1
2057	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2058	// Operand: imm12
2059	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2060	OutInst.setLoc(MI.getLoc());
2061	return true;
2062	} // if
2063	break;
2064	} // case QC_E_LW
2065	case RISCV::QC_E_ORAI: {
2066	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
2067	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2068	MI.getOperand(i: `0`).isReg() &&
2069	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2070	MI.getOperand(i: `0`).isReg() &&
2071	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2072	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /)) {
2073	// ori $rd, $rs1, $imm12
2074	OutInst.setOpcode(RISCV::ORI);
2075	// Operand: rd
2076	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2077	// Operand: rs1
2078	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2079	// Operand: imm12
2080	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2081	OutInst.setLoc(MI.getLoc());
2082	return true;
2083	} // if
2084	break;
2085	} // case QC_E_ORAI
2086	case RISCV::QC_E_ORI: {
2087	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
2088	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2089	MI.getOperand(i: `0`).isReg() &&
2090	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2091	MI.getOperand(i: `1`).isReg() &&
2092	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2093	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /)) {
2094	// ori $rd, $rs1, $imm12
2095	OutInst.setOpcode(RISCV::ORI);
2096	// Operand: rd
2097	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2098	// Operand: rs1
2099	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2100	// Operand: imm12
2101	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2102	OutInst.setLoc(MI.getLoc());
2103	return true;
2104	} // if
2105	break;
2106	} // case QC_E_ORI
2107	case RISCV::QC_E_SB: {
2108	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2109	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2110	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2111	MI.getOperand(i: `0`).isReg() &&
2112	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2113	MI.getOperand(i: `1`).isReg() &&
2114	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2115	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm2 /) &&
2116	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `17` / uimm2_optional /)) {
2117	// c.sb $rs2, ${imm}(${rs1})
2118	OutInst.setOpcode(RISCV::C_SB);
2119	// Operand: rs2
2120	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2121	// Operand: rs1
2122	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2123	// Operand: imm
2124	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2125	OutInst.setLoc(MI.getLoc());
2126	return true;
2127	} // if
2128	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2129	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2130	MI.getOperand(i: `0`).isReg() &&
2131	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2132	MI.getOperand(i: `1`).isReg() &&
2133	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2134	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /) &&
2135	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `35` / simm12_lo_optional /)) {
2136	// sb $rs2, ${imm12}(${rs1})
2137	OutInst.setOpcode(RISCV::SB);
2138	// Operand: rs2
2139	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2140	// Operand: rs1
2141	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2142	// Operand: imm12
2143	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2144	OutInst.setLoc(MI.getLoc());
2145	return true;
2146	} // if
2147	break;
2148	} // case QC_E_SB
2149	case RISCV::QC_E_SH: {
2150	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2151	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2152	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2153	MI.getOperand(i: `0`).isReg() &&
2154	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2155	MI.getOperand(i: `1`).isReg() &&
2156	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2157	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm2_lsb0 /) &&
2158	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm2_lsb0_optional /)) {
2159	// c.sh $rs2, ${imm}(${rs1})
2160	OutInst.setOpcode(RISCV::C_SH);
2161	// Operand: rs2
2162	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2163	// Operand: rs1
2164	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2165	// Operand: imm
2166	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2167	OutInst.setLoc(MI.getLoc());
2168	return true;
2169	} // if
2170	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2171	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2172	MI.getOperand(i: `0`).isReg() &&
2173	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2174	MI.getOperand(i: `1`).isReg() &&
2175	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2176	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /) &&
2177	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `35` / simm12_lo_optional /)) {
2178	// sh $rs2, ${imm12}(${rs1})
2179	OutInst.setOpcode(RISCV::SH);
2180	// Operand: rs2
2181	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2182	// Operand: rs1
2183	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2184	// Operand: imm12
2185	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2186	OutInst.setLoc(MI.getLoc());
2187	return true;
2188	} // if
2189	break;
2190	} // case QC_E_SH
2191	case RISCV::QC_E_SW: {
2192	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2193	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2194	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2195	MI.getOperand(i: `0`).isReg() &&
2196	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2197	MI.getOperand(i: `1`).isReg() &&
2198	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2199	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
2200	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm7_lsb00_optional /)) {
2201	// c.sw $rs2, ${imm}(${rs1})
2202	OutInst.setOpcode(RISCV::C_SW);
2203	// Operand: rs2
2204	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2205	// Operand: rs1
2206	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2207	// Operand: imm
2208	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2209	OutInst.setLoc(MI.getLoc());
2210	return true;
2211	} // if
2212	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2213	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2214	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2215	MI.getOperand(i: `0`).isReg() &&
2216	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2217	MI.getOperand(i: `1`).isReg() &&
2218	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2219	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm8_lsb00 /) &&
2220	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm8_lsb00_optional /)) {
2221	// c.swsp $rs2, ${imm}(${rs1})
2222	OutInst.setOpcode(RISCV::C_SWSP);
2223	// Operand: rs2
2224	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2225	// Operand: rs1
2226	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2227	// Operand: imm
2228	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2229	OutInst.setLoc(MI.getLoc());
2230	return true;
2231	} // if
2232	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2233	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2234	MI.getOperand(i: `0`).isReg() &&
2235	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2236	MI.getOperand(i: `1`).isReg() &&
2237	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2238	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /) &&
2239	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `35` / simm12_lo_optional /)) {
2240	// sw $rs2, ${imm12}(${rs1})
2241	OutInst.setOpcode(RISCV::SW);
2242	// Operand: rs2
2243	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2244	// Operand: rs1
2245	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2246	// Operand: imm12
2247	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2248	OutInst.setLoc(MI.getLoc());
2249	return true;
2250	} // if
2251	break;
2252	} // case QC_E_SW
2253	case RISCV::QC_E_XORAI: {
2254	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
2255	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2256	MI.getOperand(i: `0`).isReg() &&
2257	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2258	MI.getOperand(i: `0`).isReg() &&
2259	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2260	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /)) {
2261	// xori $rd, $rs1, $imm12
2262	OutInst.setOpcode(RISCV::XORI);
2263	// Operand: rd
2264	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2265	// Operand: rs1
2266	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2267	// Operand: imm12
2268	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2269	OutInst.setLoc(MI.getLoc());
2270	return true;
2271	} // if
2272	break;
2273	} // case QC_E_XORAI
2274	case RISCV::QC_E_XORI: {
2275	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
2276	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2277	MI.getOperand(i: `0`).isReg() &&
2278	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2279	MI.getOperand(i: `1`).isReg() &&
2280	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2281	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `30` / simm12_lo /)) {
2282	// xori $rd, $rs1, $imm12
2283	OutInst.setOpcode(RISCV::XORI);
2284	// Operand: rd
2285	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2286	// Operand: rs1
2287	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2288	// Operand: imm12
2289	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2290	OutInst.setLoc(MI.getLoc());
2291	return true;
2292	} // if
2293	break;
2294	} // case QC_E_XORI
2295	case RISCV::QC_LI: {
2296	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2297	STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
2298	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2299	MI.getOperand(i: `0`).isReg() &&
2300	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2301	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `3` / simm6 /)) {
2302	// c.li $rd, $imm
2303	OutInst.setOpcode(RISCV::C_LI);
2304	// Operand: rd
2305	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2306	// Operand: imm
2307	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2308	OutInst.setLoc(MI.getLoc());
2309	return true;
2310	} // if
2311	break;
2312	} // case QC_LI
2313	case RISCV::QC_MULIADD: {
2314	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2315	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2316	MI.getOperand(i: `0`).isReg() &&
2317	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2318	MI.getOperand(i: `2`).isReg() &&
2319	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2320	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `3`), STI, PredicateIndex: `18` / uimm5 /)) {
2321	// qc.c.muliadd $rd, $rs1, $uimm
2322	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2323	// Operand: rd_wb
2324	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2325	// Operand: rd
2326	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2327	// Operand: rs1
2328	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2329	// Operand: uimm
2330	OutInst.addOperand(Op: MI.getOperand(i: `3`));
2331	OutInst.setLoc(MI.getLoc());
2332	return true;
2333	} // if
2334	break;
2335	} // case QC_MULIADD
2336	case RISCV::QC_MVEQI: {
2337	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
2338	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2339	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2340	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2341	MI.getOperand(i: `3`).isImm() &&
2342	(MI.getOperand(i: `3`).getImm() == `0`) &&
2343	MI.getOperand(i: `2`).isReg() &&
2344	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2345	MI.getOperand(i: `4`).isReg() &&
2346	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `4`).getReg())) {
2347	// qc.c.mveqz $rd, $rs1
2348	OutInst.setOpcode(RISCV::QC_C_MVEQZ);
2349	// Operand: rd_wb
2350	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2351	// Operand: rd
2352	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2353	// Operand: rs1
2354	OutInst.addOperand(Op: MI.getOperand(i: `4`));
2355	OutInst.setLoc(MI.getLoc());
2356	return true;
2357	} // if
2358	break;
2359	} // case QC_MVEQI
2360	case RISCV::QC_MVLTUI: {
2361	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
2362	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2363	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2364	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2365	MI.getOperand(i: `3`).isImm() &&
2366	(MI.getOperand(i: `3`).getImm() == `1`) &&
2367	MI.getOperand(i: `2`).isReg() &&
2368	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2369	MI.getOperand(i: `4`).isReg() &&
2370	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `4`).getReg())) {
2371	// qc.c.mveqz $rd, $rs1
2372	OutInst.setOpcode(RISCV::QC_C_MVEQZ);
2373	// Operand: rd_wb
2374	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2375	// Operand: rd
2376	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2377	// Operand: rs1
2378	OutInst.addOperand(Op: MI.getOperand(i: `4`));
2379	OutInst.setLoc(MI.getLoc());
2380	return true;
2381	} // if
2382	break;
2383	} // case QC_MVLTUI
2384	case RISCV::QC_SHLADD: {
2385	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2386	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2387	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2388	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2389	MI.getOperand(i: `3`).isImm() &&
2390	(MI.getOperand(i: `3`).getImm() == `4`) &&
2391	MI.getOperand(i: `2`).isReg() &&
2392	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2393	MI.getOperand(i: `1`).isReg() &&
2394	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2395	RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: `16`), STI, PredicateIndex: `18` / uimm5 /)) {
2396	// qc.c.muliadd $rd, $rs1, $uimm
2397	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2398	// Operand: rd_wb
2399	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2400	// Operand: rd
2401	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2402	// Operand: rs1
2403	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2404	// Operand: uimm
2405	OutInst.addOperand(Op: MCOperand::createImm(Val: `16`));
2406	OutInst.setLoc(MI.getLoc());
2407	return true;
2408	} // if
2409	break;
2410	} // case QC_SHLADD
2411	case RISCV::QC_SYNC: {
2412	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2413	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2414	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `37` / uimm5slist /)) {
2415	// qc.c.sync $slist
2416	OutInst.setOpcode(RISCV::QC_C_SYNC);
2417	// Operand: slist
2418	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2419	OutInst.setLoc(MI.getLoc());
2420	return true;
2421	} // if
2422	break;
2423	} // case QC_SYNC
2424	case RISCV::QC_SYNCR: {
2425	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2426	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2427	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `37` / uimm5slist /)) {
2428	// qc.c.syncr $slist
2429	OutInst.setOpcode(RISCV::QC_C_SYNCR);
2430	// Operand: slist
2431	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2432	OutInst.setLoc(MI.getLoc());
2433	return true;
2434	} // if
2435	break;
2436	} // case QC_SYNCR
2437	case RISCV::QC_SYNCWF: {
2438	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2439	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2440	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `37` / uimm5slist /)) {
2441	// qc.c.syncwf $slist
2442	OutInst.setOpcode(RISCV::QC_C_SYNCWF);
2443	// Operand: slist
2444	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2445	OutInst.setLoc(MI.getLoc());
2446	return true;
2447	} // if
2448	break;
2449	} // case QC_SYNCWF
2450	case RISCV::QC_SYNCWL: {
2451	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2452	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2453	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `37` / uimm5slist /)) {
2454	// qc.c.syncwl $slist
2455	OutInst.setOpcode(RISCV::QC_C_SYNCWL);
2456	// Operand: slist
2457	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2458	OutInst.setLoc(MI.getLoc());
2459	return true;
2460	} // if
2461	break;
2462	} // case QC_SYNCWL
2463	case RISCV::SB: {
2464	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2465	MI.getOperand(i: `0`).isReg() &&
2466	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2467	MI.getOperand(i: `1`).isReg() &&
2468	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2469	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm2 /) &&
2470	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `17` / uimm2_optional /)) {
2471	// c.sb $rs2, ${imm}(${rs1})
2472	OutInst.setOpcode(RISCV::C_SB);
2473	// Operand: rs2
2474	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2475	// Operand: rs1
2476	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2477	// Operand: imm
2478	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2479	OutInst.setLoc(MI.getLoc());
2480	return true;
2481	} // if
2482	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2483	MI.getOperand(i: `0`).isReg() &&
2484	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2485	MI.getOperand(i: `1`).isReg() &&
2486	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2487	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `18` / uimm5 /) &&
2488	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19` / uimm5_optional /)) {
2489	// qk.c.sb $rs2, ${imm}(${rs1})
2490	OutInst.setOpcode(RISCV::QK_C_SB);
2491	// Operand: rs2
2492	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2493	// Operand: rs1
2494	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2495	// Operand: imm
2496	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2497	OutInst.setLoc(MI.getLoc());
2498	return true;
2499	} // if
2500	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2501	MI.getOperand(i: `0`).isReg() &&
2502	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2503	MI.getOperand(i: `1`).isReg() &&
2504	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2505	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimm4 /) &&
2506	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21` / uimm4_optional /)) {
2507	// qk.c.sbsp $rd_rs2, ${imm}(${rs1})
2508	OutInst.setOpcode(RISCV::QK_C_SBSP);
2509	// Operand: rd_rs2
2510	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2511	// Operand: rs1
2512	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2513	// Operand: imm
2514	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2515	OutInst.setLoc(MI.getLoc());
2516	return true;
2517	} // if
2518	break;
2519	} // case SB
2520	case RISCV::SD: {
2521	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2522	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2523	MI.getOperand(i: `0`).isReg() &&
2524	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2525	MI.getOperand(i: `1`).isReg() &&
2526	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2527	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /) &&
2528	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000_optional /)) {
2529	// c.sd $rs2, ${imm}(${rs1})
2530	OutInst.setOpcode(RISCV::C_SD);
2531	// Operand: rs2
2532	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2533	// Operand: rs1
2534	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2535	// Operand: imm
2536	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2537	OutInst.setLoc(MI.getLoc());
2538	return true;
2539	} // if
2540	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2541	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2542	MI.getOperand(i: `0`).isReg() &&
2543	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2544	MI.getOperand(i: `1`).isReg() &&
2545	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2546	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
2547	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000_optional /)) {
2548	// c.sdsp $rs2, ${imm}(${rs1})
2549	OutInst.setOpcode(RISCV::C_SDSP);
2550	// Operand: rs2
2551	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2552	// Operand: rs1
2553	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2554	// Operand: imm
2555	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2556	OutInst.setLoc(MI.getLoc());
2557	return true;
2558	} // if
2559	break;
2560	} // case SD
2561	case RISCV::SD_RV32: {
2562	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
2563	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2564	MI.getOperand(i: `0`).isReg() &&
2565	getRISCVMCRegisterClass(RC: RISCV::GPRPairRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2566	MI.getOperand(i: `1`).isReg() &&
2567	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2568	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
2569	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000_optional /)) {
2570	// c.sdsp $rs2, ${imm}(${rs1})
2571	OutInst.setOpcode(RISCV::C_SDSP_RV32);
2572	// Operand: rs2
2573	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2574	// Operand: rs1
2575	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2576	// Operand: imm
2577	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2578	OutInst.setLoc(MI.getLoc());
2579	return true;
2580	} // if
2581	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
2582	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2583	MI.getOperand(i: `0`).isReg() &&
2584	getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2585	MI.getOperand(i: `1`).isReg() &&
2586	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2587	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /) &&
2588	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000_optional /)) {
2589	// c.sd $rs2, ${imm}(${rs1})
2590	OutInst.setOpcode(RISCV::C_SD_RV32);
2591	// Operand: rs2
2592	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2593	// Operand: rs1
2594	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2595	// Operand: imm
2596	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2597	OutInst.setLoc(MI.getLoc());
2598	return true;
2599	} // if
2600	break;
2601	} // case SD_RV32
2602	case RISCV::SEXT_B: {
2603	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2604	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2605	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2606	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2607	MI.getOperand(i: `1`).isReg() &&
2608	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
2609	// c.sext.b $rd
2610	OutInst.setOpcode(RISCV::C_SEXT_B);
2611	// Operand: rd_wb
2612	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2613	// Operand: rd
2614	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2615	OutInst.setLoc(MI.getLoc());
2616	return true;
2617	} // if
2618	break;
2619	} // case SEXT_B
2620	case RISCV::SEXT_H: {
2621	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2622	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2623	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2624	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2625	MI.getOperand(i: `1`).isReg() &&
2626	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
2627	// c.sext.h $rd
2628	OutInst.setOpcode(RISCV::C_SEXT_H);
2629	// Operand: rd_wb
2630	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2631	// Operand: rd
2632	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2633	OutInst.setLoc(MI.getLoc());
2634	return true;
2635	} // if
2636	break;
2637	} // case SEXT_H
2638	case RISCV::SH: {
2639	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2640	MI.getOperand(i: `0`).isReg() &&
2641	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2642	MI.getOperand(i: `1`).isReg() &&
2643	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2644	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm2_lsb0 /) &&
2645	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm2_lsb0_optional /)) {
2646	// c.sh $rs2, ${imm}(${rs1})
2647	OutInst.setOpcode(RISCV::C_SH);
2648	// Operand: rs2
2649	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2650	// Operand: rs1
2651	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2652	// Operand: imm
2653	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2654	OutInst.setLoc(MI.getLoc());
2655	return true;
2656	} // if
2657	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2658	MI.getOperand(i: `0`).isReg() &&
2659	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2660	MI.getOperand(i: `1`).isReg() &&
2661	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2662	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24` / uimm6_lsb0 /) &&
2663	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `25` / uimm6_lsb0_optional /)) {
2664	// qk.c.sh $rs2, ${imm}(${rs1})
2665	OutInst.setOpcode(RISCV::QK_C_SH);
2666	// Operand: rs2
2667	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2668	// Operand: rs1
2669	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2670	// Operand: imm
2671	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2672	OutInst.setLoc(MI.getLoc());
2673	return true;
2674	} // if
2675	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2676	MI.getOperand(i: `0`).isReg() &&
2677	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2678	MI.getOperand(i: `1`).isReg() &&
2679	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2680	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `26` / uimm5_lsb0 /) &&
2681	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimm5_lsb0_optional /)) {
2682	// qk.c.shsp $rd_rs2, ${imm}(${rs1})
2683	OutInst.setOpcode(RISCV::QK_C_SHSP);
2684	// Operand: rd_rs2
2685	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2686	// Operand: rs1
2687	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2688	// Operand: imm
2689	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2690	OutInst.setLoc(MI.getLoc());
2691	return true;
2692	} // if
2693	break;
2694	} // case SH
2695	case RISCV::SH1ADD: {
2696	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2697	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2698	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2699	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2700	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2701	MI.getOperand(i: `2`).isReg() &&
2702	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2703	MI.getOperand(i: `1`).isReg() &&
2704	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2705	RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: `2`), STI, PredicateIndex: `18` / uimm5 /)) {
2706	// qc.c.muliadd $rd, $rs1, $uimm
2707	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2708	// Operand: rd_wb
2709	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2710	// Operand: rd
2711	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2712	// Operand: rs1
2713	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2714	// Operand: uimm
2715	OutInst.addOperand(Op: MCOperand::createImm(Val: `2`));
2716	OutInst.setLoc(MI.getLoc());
2717	return true;
2718	} // if
2719	break;
2720	} // case SH1ADD
2721	case RISCV::SH2ADD: {
2722	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2723	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2724	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2725	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2726	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2727	MI.getOperand(i: `2`).isReg() &&
2728	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2729	MI.getOperand(i: `1`).isReg() &&
2730	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2731	RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: `4`), STI, PredicateIndex: `18` / uimm5 /)) {
2732	// qc.c.muliadd $rd, $rs1, $uimm
2733	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2734	// Operand: rd_wb
2735	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2736	// Operand: rd
2737	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2738	// Operand: rs1
2739	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2740	// Operand: uimm
2741	OutInst.addOperand(Op: MCOperand::createImm(Val: `4`));
2742	OutInst.setLoc(MI.getLoc());
2743	return true;
2744	} // if
2745	break;
2746	} // case SH2ADD
2747	case RISCV::SH3ADD: {
2748	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2749	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2750	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2751	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2752	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2753	MI.getOperand(i: `2`).isReg() &&
2754	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2755	MI.getOperand(i: `1`).isReg() &&
2756	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2757	RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: `8`), STI, PredicateIndex: `18` / uimm5 /)) {
2758	// qc.c.muliadd $rd, $rs1, $uimm
2759	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2760	// Operand: rd_wb
2761	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2762	// Operand: rd
2763	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2764	// Operand: rs1
2765	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2766	// Operand: uimm
2767	OutInst.addOperand(Op: MCOperand::createImm(Val: `8`));
2768	OutInst.setLoc(MI.getLoc());
2769	return true;
2770	} // if
2771	break;
2772	} // case SH3ADD
2773	case RISCV::SH_INX: {
2774	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2775	MI.getOperand(i: `0`).isReg() &&
2776	getRISCVMCRegisterClass(RC: RISCV::GPRF16CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2777	MI.getOperand(i: `1`).isReg() &&
2778	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2779	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm2_lsb0 /) &&
2780	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm2_lsb0_optional /)) {
2781	// c.sh $rs2, ${imm}(${rs1})
2782	OutInst.setOpcode(RISCV::C_SH_INX);
2783	// Operand: rs2
2784	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2785	// Operand: rs1
2786	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2787	// Operand: imm
2788	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2789	OutInst.setLoc(MI.getLoc());
2790	return true;
2791	} // if
2792	break;
2793	} // case SH_INX
2794	case RISCV::SLLI: {
2795	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2796	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2797	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2798	MI.getOperand(i: `1`).isReg() &&
2799	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2800	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /) &&
2801	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `38` / uimmlog2xlen /)) {
2802	// c.slli $rd, $imm
2803	OutInst.setOpcode(RISCV::C_SLLI);
2804	// Operand: rd_wb
2805	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2806	// Operand: rd
2807	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2808	// Operand: imm
2809	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2810	OutInst.setLoc(MI.getLoc());
2811	return true;
2812	} // if
2813	break;
2814	} // case SLLI
2815	case RISCV::SRAI: {
2816	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2817	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2818	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2819	MI.getOperand(i: `1`).isReg() &&
2820	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2821	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /) &&
2822	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `38` / uimmlog2xlen /)) {
2823	// c.srai $rs1, $imm
2824	OutInst.setOpcode(RISCV::C_SRAI);
2825	// Operand: rd
2826	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2827	// Operand: rs1
2828	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2829	// Operand: imm
2830	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2831	OutInst.setLoc(MI.getLoc());
2832	return true;
2833	} // if
2834	break;
2835	} // case SRAI
2836	case RISCV::SRLI: {
2837	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2838	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2839	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2840	MI.getOperand(i: `1`).isReg() &&
2841	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2842	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /) &&
2843	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `38` / uimmlog2xlen /)) {
2844	// c.srli $rs1, $imm
2845	OutInst.setOpcode(RISCV::C_SRLI);
2846	// Operand: rd
2847	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2848	// Operand: rs1
2849	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2850	// Operand: imm
2851	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2852	OutInst.setLoc(MI.getLoc());
2853	return true;
2854	} // if
2855	break;
2856	} // case SRLI
2857	case RISCV::SSPOPCHK: {
2858	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2859	MI.getOperand(i: `0`).isReg() &&
2860	(MI.getOperand(i: `0`).getReg() == RISCV::X5)) {
2861	// c.sspopchk $rs1
2862	OutInst.setOpcode(RISCV::C_SSPOPCHK);
2863	// Operand: rs1
2864	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
2865	OutInst.setLoc(MI.getLoc());
2866	return true;
2867	} // if
2868	break;
2869	} // case SSPOPCHK
2870	case RISCV::SSPUSH: {
2871	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2872	MI.getOperand(i: `0`).isReg() &&
2873	(MI.getOperand(i: `0`).getReg() == RISCV::X1)) {
2874	// c.sspush $rs1
2875	OutInst.setOpcode(RISCV::C_SSPUSH);
2876	// Operand: rs1
2877	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
2878	OutInst.setLoc(MI.getLoc());
2879	return true;
2880	} // if
2881	break;
2882	} // case SSPUSH
2883	case RISCV::SUB: {
2884	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2885	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2886	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2887	MI.getOperand(i: `1`).isReg() &&
2888	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2889	MI.getOperand(i: `2`).isReg() &&
2890	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
2891	// c.sub $rd, $rs2
2892	OutInst.setOpcode(RISCV::C_SUB);
2893	// Operand: rd_wb
2894	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2895	// Operand: rd
2896	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2897	// Operand: rs2
2898	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2899	OutInst.setLoc(MI.getLoc());
2900	return true;
2901	} // if
2902	break;
2903	} // case SUB
2904	case RISCV::SUBW: {
2905	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2906	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2907	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2908	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2909	MI.getOperand(i: `1`).isReg() &&
2910	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2911	MI.getOperand(i: `2`).isReg() &&
2912	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
2913	// c.subw $rd, $rs2
2914	OutInst.setOpcode(RISCV::C_SUBW);
2915	// Operand: rd_wb
2916	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2917	// Operand: rd
2918	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2919	// Operand: rs2
2920	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2921	OutInst.setLoc(MI.getLoc());
2922	return true;
2923	} // if
2924	break;
2925	} // case SUBW
2926	case RISCV::SW: {
2927	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2928	MI.getOperand(i: `0`).isReg() &&
2929	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2930	MI.getOperand(i: `1`).isReg() &&
2931	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2932	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
2933	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm7_lsb00_optional /)) {
2934	// c.sw $rs2, ${imm}(${rs1})
2935	OutInst.setOpcode(RISCV::C_SW);
2936	// Operand: rs2
2937	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2938	// Operand: rs1
2939	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2940	// Operand: imm
2941	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2942	OutInst.setLoc(MI.getLoc());
2943	return true;
2944	} // if
2945	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2946	MI.getOperand(i: `0`).isReg() &&
2947	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2948	MI.getOperand(i: `1`).isReg() &&
2949	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2950	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm8_lsb00 /) &&
2951	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm8_lsb00_optional /)) {
2952	// c.swsp $rs2, ${imm}(${rs1})
2953	OutInst.setOpcode(RISCV::C_SWSP);
2954	// Operand: rs2
2955	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2956	// Operand: rs1
2957	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2958	// Operand: imm
2959	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2960	OutInst.setLoc(MI.getLoc());
2961	return true;
2962	} // if
2963	break;
2964	} // case SW
2965	case RISCV::SW_INX: {
2966	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2967	MI.getOperand(i: `0`).isReg() &&
2968	getRISCVMCRegisterClass(RC: RISCV::GPRF32CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2969	MI.getOperand(i: `1`).isReg() &&
2970	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2971	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
2972	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm7_lsb00_optional /)) {
2973	// c.sw $rs2, ${imm}(${rs1})
2974	OutInst.setOpcode(RISCV::C_SW_INX);
2975	// Operand: rs2
2976	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2977	// Operand: rs1
2978	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2979	// Operand: imm
2980	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2981	OutInst.setLoc(MI.getLoc());
2982	return true;
2983	} // if
2984	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
2985	MI.getOperand(i: `0`).isReg() &&
2986	getRISCVMCRegisterClass(RC: RISCV::GPRF32RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2987	MI.getOperand(i: `1`).isReg() &&
2988	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2989	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm8_lsb00 /) &&
2990	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm8_lsb00_optional /)) {
2991	// c.swsp $rs2, ${imm}(${rs1})
2992	OutInst.setOpcode(RISCV::C_SWSP_INX);
2993	// Operand: rs2
2994	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2995	// Operand: rs1
2996	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2997	// Operand: imm
2998	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2999	OutInst.setLoc(MI.getLoc());
3000	return true;
3001	} // if
3002	break;
3003	} // case SW_INX
3004	case RISCV::UNIMP: {
3005	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) {
3006	// c.unimp
3007	OutInst.setOpcode(RISCV::C_UNIMP);
3008	OutInst.setLoc(MI.getLoc());
3009	return true;
3010	} // if
3011	break;
3012	} // case UNIMP
3013	case RISCV::XOR: {
3014	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3015	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
3016	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
3017	MI.getOperand(i: `1`).isReg() &&
3018	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3019	MI.getOperand(i: `2`).isReg() &&
3020	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
3021	// c.xor $rd, $rs2
3022	OutInst.setOpcode(RISCV::C_XOR);
3023	// Operand: rd_wb
3024	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3025	// Operand: rd
3026	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3027	// Operand: rs2
3028	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3029	OutInst.setLoc(MI.getLoc());
3030	return true;
3031	} // if
3032	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3033	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
3034	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
3035	MI.getOperand(i: `2`).isReg() &&
3036	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg()) &&
3037	MI.getOperand(i: `1`).isReg() &&
3038	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
3039	// c.xor $rd, $rs2
3040	OutInst.setOpcode(RISCV::C_XOR);
3041	// Operand: rd_wb
3042	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3043	// Operand: rd
3044	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3045	// Operand: rs2
3046	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3047	OutInst.setLoc(MI.getLoc());
3048	return true;
3049	} // if
3050	break;
3051	} // case XOR
3052	case RISCV::XORI: {
3053	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3054	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
3055	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
3056	MI.getOperand(i: `2`).isImm() &&
3057	(MI.getOperand(i: `2`).getImm() == -`1`) &&
3058	MI.getOperand(i: `1`).isReg() &&
3059	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
3060	// c.not $rd
3061	OutInst.setOpcode(RISCV::C_NOT);
3062	// Operand: rd_wb
3063	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3064	// Operand: rd
3065	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3066	OutInst.setLoc(MI.getLoc());
3067	return true;
3068	} // if
3069	break;
3070	} // case XORI
3071	case RISCV::ZEXT_H_RV32: {
3072	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3073	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3074	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
3075	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
3076	MI.getOperand(i: `1`).isReg() &&
3077	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
3078	// c.zext.h $rd
3079	OutInst.setOpcode(RISCV::C_ZEXT_H);
3080	// Operand: rd_wb
3081	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3082	// Operand: rd
3083	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3084	OutInst.setLoc(MI.getLoc());
3085	return true;
3086	} // if
3087	break;
3088	} // case ZEXT_H_RV32
3089	case RISCV::ZEXT_H_RV64: {
3090	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3091	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3092	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
3093	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
3094	MI.getOperand(i: `1`).isReg() &&
3095	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg())) {
3096	// c.zext.h $rd
3097	OutInst.setOpcode(RISCV::C_ZEXT_H);
3098	// Operand: rd_wb
3099	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3100	// Operand: rd
3101	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3102	OutInst.setLoc(MI.getLoc());
3103	return true;
3104	} // if
3105	break;
3106	} // case ZEXT_H_RV64
3107	} // switch
3108	return false;
3109	}
3110
3111	#endif // GEN_COMPRESS_INSTR
3112
3113	#ifdef GEN_UNCOMPRESS_INSTR
3114	#undef GEN_UNCOMPRESS_INSTR
3115
3116	static bool RISCVValidateMCOperandForUncompress(const MCOperand &MCOp,
3117	const MCSubtargetInfo &STI,
3118	unsigned PredicateIndex) {
3119	switch (PredicateIndex) {
3120	default:
3121	llvm_unreachable("Unknown MCOperandPredicate kind");
3122	break;
3123	case `1`: {
3124	// simm6nonzero
3125	int64_t Imm;
3126	if (MCOp.evaluateAsConstantImm(Imm))
3127	return (Imm != `0`) && isInt<`6`>(x: Imm);
3128	return MCOp.isBareSymbolRef();
3129	}
3130	case `2`: {
3131	// simm12_lo
3132	int64_t Imm;
3133	if (MCOp.evaluateAsConstantImm(Imm))
3134	return isInt<`12`>(x: Imm);
3135	return MCOp.isBareSymbolRef();
3136	}
3137	case `3`: {
3138	// simm10_lsb0000nonzero
3139	int64_t Imm;
3140	if (!MCOp.evaluateAsConstantImm(Imm))
3141	return false;
3142	return isShiftedInt<`6`, `4`>(x: Imm) && (Imm != `0`);
3143	}
3144	case `4`: {
3145	// uimm10_lsb00nonzero
3146	int64_t Imm;
3147	if (!MCOp.evaluateAsConstantImm(Imm))
3148	return false;
3149	return isShiftedUInt<`8`, `2`>(x: Imm) && (Imm != `0`);
3150	}
3151	case `5`: {
3152	// simm6
3153	int64_t Imm;
3154	if (MCOp.evaluateAsConstantImm(Imm))
3155	return isInt<`6`>(x: Imm);
3156	return MCOp.isBareSymbolRef();
3157	}
3158	case `6`: {
3159	// bare_simm9_lsb0
3160	int64_t Imm;
3161	if (MCOp.evaluateAsConstantImm(Imm))
3162	return isShiftedInt<`8`, `1`>(x: Imm);
3163	return MCOp.isBareSymbolRef();
3164	}
3165	case `7`: {
3166	// bare_simm13_lsb0
3167	int64_t Imm;
3168	if (MCOp.evaluateAsConstantImm(Imm))
3169	return isShiftedInt<`12`, `1`>(x: Imm);
3170	return MCOp.isBareSymbolRef();
3171	}
3172	case `8`: {
3173	// uimm8_lsb000
3174	int64_t Imm;
3175	if (!MCOp.evaluateAsConstantImm(Imm))
3176	return false;
3177	return isShiftedUInt<`5`, `3`>(x: Imm);
3178	}
3179	case `9`: {
3180	// simm12_lo_optional
3181	int64_t Imm;
3182	if (MCOp.evaluateAsConstantImm(Imm))
3183	return isInt<`12`>(x: Imm);
3184	return MCOp.isBareSymbolRef();
3185	}
3186	case `10`: {
3187	// uimm9_lsb000
3188	int64_t Imm;
3189	if (!MCOp.evaluateAsConstantImm(Imm))
3190	return false;
3191	return isShiftedUInt<`6`, `3`>(x: Imm);
3192	}
3193	case `11`: {
3194	// uimm7_lsb00
3195	int64_t Imm;
3196	if (!MCOp.evaluateAsConstantImm(Imm))
3197	return false;
3198	return isShiftedUInt<`5`, `2`>(x: Imm);
3199	}
3200	case `12`: {
3201	// uimm8_lsb00
3202	int64_t Imm;
3203	if (!MCOp.evaluateAsConstantImm(Imm))
3204	return false;
3205	return isShiftedUInt<`6`, `2`>(x: Imm);
3206	}
3207	case `13`: {
3208	// bare_simm12_lsb0
3209	int64_t Imm;
3210	if (MCOp.evaluateAsConstantImm(Imm))
3211	return isShiftedInt<`11`, `1`>(x: Imm);
3212	return MCOp.isBareSymbolRef();
3213	}
3214	case `14`: {
3215	// simm21_lsb0_jal
3216	int64_t Imm;
3217	if (MCOp.evaluateAsConstantImm(Imm))
3218	return isShiftedInt<`20`, `1`>(x: Imm);
3219	return MCOp.isBareSymbolRef();
3220	}
3221	case `15`: {
3222	// uimm2
3223	int64_t Imm;
3224	if (!MCOp.evaluateAsConstantImm(Imm))
3225	return false;
3226	return isUInt<`2`>(x: Imm);
3227	}
3228	case `16`: {
3229	// uimm2_lsb0
3230	int64_t Imm;
3231	if (!MCOp.evaluateAsConstantImm(Imm))
3232	return false;
3233	return isShiftedUInt<`1`, `1`>(x: Imm);
3234	}
3235	case `17`: {
3236	// simm20_li
3237	int64_t Imm;
3238	if (MCOp.evaluateAsConstantImm(Imm))
3239	return isInt<`20`>(x: Imm);
3240	return MCOp.isBareSymbolRef();
3241	}
3242	case `18`: {
3243	// c_lui_imm
3244	int64_t Imm;
3245	if (!MCOp.evaluateAsConstantImm(Imm))
3246	return false;
3247	return (Imm != `0`) && (isUInt<`5`>(x: Imm) \|\|
3248	(Imm >= `0xfffe0` && Imm <= `0xfffff`));
3249	}
3250	case `19`: {
3251	// uimm20_lui
3252	int64_t Imm;
3253	if (MCOp.evaluateAsConstantImm(Imm))
3254	return isUInt<`20`>(x: Imm);
3255	return MCOp.isBareSymbolRef();
3256	}
3257	case `20`: {
3258	// uimmlog2xlennonzero
3259	int64_t Imm;
3260	if (!MCOp.evaluateAsConstantImm(Imm))
3261	return false;
3262	if (STI.getTargetTriple().isArch64Bit())
3263	return isUInt<`6`>(x: Imm) && (Imm != `0`);
3264	return isUInt<`5`>(x: Imm) && (Imm != `0`);
3265	}
3266	case `21`: {
3267	// uimmlog2xlen
3268	int64_t Imm;
3269	if (!MCOp.evaluateAsConstantImm(Imm))
3270	return false;
3271	if (STI.getTargetTriple().isArch64Bit())
3272	return isUInt<`6`>(x: Imm);
3273	return isUInt<`5`>(x: Imm);
3274	}
3275	case `22`: {
3276	// uimm5ge6_plus1
3277	int64_t Imm;
3278	if (!MCOp.evaluateAsConstantImm(Imm))
3279	return false;
3280	return Imm >= `6` && Imm <= `32`;
3281	}
3282	case `23`: {
3283	// uimm5_plus1
3284	int64_t Imm;
3285	if (!MCOp.evaluateAsConstantImm(Imm))
3286	return false;
3287	return Imm > `0` && isUInt<`5`>(x: Imm - `1`);
3288	}
3289	case `24`: {
3290	// uimm5
3291	int64_t Imm;
3292	if (!MCOp.evaluateAsConstantImm(Imm))
3293	return false;
3294	return isUInt<`5`>(x: Imm);
3295	}
3296	case `25`: {
3297	// simm5
3298	int64_t Imm;
3299	if (MCOp.evaluateAsConstantImm(Imm))
3300	return isInt<`5`>(x: Imm);
3301	return MCOp.isBareSymbolRef();
3302	}
3303	case `26`: {
3304	// uimm5slist
3305	int64_t Imm;
3306	if (!MCOp.evaluateAsConstantImm(Imm))
3307	return false;
3308	return ((Imm == `0`) \|\| (Imm == `1`) \|\|
3309	(Imm == `2`) \|\| (Imm == `4`) \|\|
3310	(Imm == `8`) \|\| (Imm == `16`) \|\|
3311	(Imm == `15`) \|\| (Imm == `31`));
3312	}
3313	case `27`: {
3314	// uimm4
3315	int64_t Imm;
3316	if (!MCOp.evaluateAsConstantImm(Imm))
3317	return false;
3318	return isUInt<`4`>(x: Imm);
3319	}
3320	case `28`: {
3321	// uimm6_lsb0
3322	int64_t Imm;
3323	if (!MCOp.evaluateAsConstantImm(Imm))
3324	return false;
3325	return isShiftedUInt<`5`, `1`>(x: Imm);
3326	}
3327	case `29`: {
3328	// uimm5_lsb0
3329	int64_t Imm;
3330	if (!MCOp.evaluateAsConstantImm(Imm))
3331	return false;
3332	return isShiftedUInt<`4`, `1`>(x: Imm);
3333	}
3334	}
3335	}
3336
3337	static bool uncompressInst(MCInst &OutInst,
3338	const MCInst &MI,
3339	const MCSubtargetInfo &STI) {
3340	switch (MI.getOpcode()) {
3341	default: return false;
3342	case RISCV::C_ADD: {
3343	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3344	MI.getOperand(i: `0`).isReg() &&
3345	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3346	MI.getOperand(i: `0`).isReg() &&
3347	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3348	MI.getOperand(i: `2`).isReg() &&
3349	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
3350	// add $rd, $rs1, $rs2
3351	OutInst.setOpcode(RISCV::ADD);
3352	// Operand: rd
3353	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3354	// Operand: rs1
3355	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3356	// Operand: rs2
3357	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3358	OutInst.setLoc(MI.getLoc());
3359	return true;
3360	} // if
3361	break;
3362	} // case C_ADD
3363	case RISCV::C_ADDI: {
3364	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3365	MI.getOperand(i: `0`).isReg() &&
3366	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3367	MI.getOperand(i: `0`).isReg() &&
3368	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3369	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1` / simm6nonzero /) &&
3370	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3371	// addi $rd, $rs1, $imm12
3372	OutInst.setOpcode(RISCV::ADDI);
3373	// Operand: rd
3374	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3375	// Operand: rs1
3376	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3377	// Operand: imm12
3378	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3379	OutInst.setLoc(MI.getLoc());
3380	return true;
3381	} // if
3382	break;
3383	} // case C_ADDI
3384	case RISCV::C_ADDI16SP: {
3385	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3386	MI.getOperand(i: `0`).isReg() &&
3387	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
3388	MI.getOperand(i: `1`).isReg() &&
3389	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
3390	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm10_lsb0000nonzero /) &&
3391	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3392	// addi $rd, $rs1, $imm12
3393	OutInst.setOpcode(RISCV::ADDI);
3394	// Operand: rd
3395	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
3396	// Operand: rs1
3397	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
3398	// Operand: imm12
3399	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3400	OutInst.setLoc(MI.getLoc());
3401	return true;
3402	} // if
3403	break;
3404	} // case C_ADDI16SP
3405	case RISCV::C_ADDI4SPN: {
3406	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3407	MI.getOperand(i: `0`).isReg() &&
3408	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3409	MI.getOperand(i: `1`).isReg() &&
3410	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3411	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4` / uimm10_lsb00nonzero /) &&
3412	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3413	// addi $rd, $rs1, $imm12
3414	OutInst.setOpcode(RISCV::ADDI);
3415	// Operand: rd
3416	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3417	// Operand: rs1
3418	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3419	// Operand: imm12
3420	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3421	OutInst.setLoc(MI.getLoc());
3422	return true;
3423	} // if
3424	break;
3425	} // case C_ADDI4SPN
3426	case RISCV::C_ADDIW: {
3427	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3428	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3429	MI.getOperand(i: `0`).isReg() &&
3430	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3431	MI.getOperand(i: `0`).isReg() &&
3432	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3433	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / simm6 /) &&
3434	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3435	// addiw $rd, $rs1, $imm12
3436	OutInst.setOpcode(RISCV::ADDIW);
3437	// Operand: rd
3438	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3439	// Operand: rs1
3440	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3441	// Operand: imm12
3442	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3443	OutInst.setLoc(MI.getLoc());
3444	return true;
3445	} // if
3446	break;
3447	} // case C_ADDIW
3448	case RISCV::C_ADDW: {
3449	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3450	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3451	MI.getOperand(i: `0`).isReg() &&
3452	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3453	MI.getOperand(i: `0`).isReg() &&
3454	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3455	MI.getOperand(i: `2`).isReg() &&
3456	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
3457	// addw $rd, $rs1, $rs2
3458	OutInst.setOpcode(RISCV::ADDW);
3459	// Operand: rd
3460	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3461	// Operand: rs1
3462	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3463	// Operand: rs2
3464	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3465	OutInst.setLoc(MI.getLoc());
3466	return true;
3467	} // if
3468	break;
3469	} // case C_ADDW
3470	case RISCV::C_AND: {
3471	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3472	MI.getOperand(i: `0`).isReg() &&
3473	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3474	MI.getOperand(i: `0`).isReg() &&
3475	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3476	MI.getOperand(i: `2`).isReg() &&
3477	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
3478	// and $rd, $rs1, $rs2
3479	OutInst.setOpcode(RISCV::AND);
3480	// Operand: rd
3481	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3482	// Operand: rs1
3483	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3484	// Operand: rs2
3485	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3486	OutInst.setLoc(MI.getLoc());
3487	return true;
3488	} // if
3489	break;
3490	} // case C_AND
3491	case RISCV::C_ANDI: {
3492	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3493	MI.getOperand(i: `0`).isReg() &&
3494	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3495	MI.getOperand(i: `0`).isReg() &&
3496	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3497	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / simm6 /) &&
3498	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3499	// andi $rd, $rs1, $imm12
3500	OutInst.setOpcode(RISCV::ANDI);
3501	// Operand: rd
3502	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3503	// Operand: rs1
3504	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3505	// Operand: imm12
3506	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3507	OutInst.setLoc(MI.getLoc());
3508	return true;
3509	} // if
3510	break;
3511	} // case C_ANDI
3512	case RISCV::C_BEQZ: {
3513	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3514	MI.getOperand(i: `0`).isReg() &&
3515	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3516	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `6` / bare_simm9_lsb0 /) &&
3517	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `7` / bare_simm13_lsb0 /)) {
3518	// beq $rs1, $rs2, $imm12
3519	OutInst.setOpcode(RISCV::BEQ);
3520	// Operand: rs1
3521	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3522	// Operand: rs2
3523	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3524	// Operand: imm12
3525	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3526	OutInst.setLoc(MI.getLoc());
3527	return true;
3528	} // if
3529	break;
3530	} // case C_BEQZ
3531	case RISCV::C_BNEZ: {
3532	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3533	MI.getOperand(i: `0`).isReg() &&
3534	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3535	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `6` / bare_simm9_lsb0 /) &&
3536	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `7` / bare_simm13_lsb0 /)) {
3537	// bne $rs1, $rs2, $imm12
3538	OutInst.setOpcode(RISCV::BNE);
3539	// Operand: rs1
3540	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3541	// Operand: rs2
3542	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3543	// Operand: imm12
3544	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3545	OutInst.setLoc(MI.getLoc());
3546	return true;
3547	} // if
3548	break;
3549	} // case C_BNEZ
3550	case RISCV::C_EBREAK: {
3551	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) {
3552	// ebreak
3553	OutInst.setOpcode(RISCV::EBREAK);
3554	OutInst.setLoc(MI.getLoc());
3555	return true;
3556	} // if
3557	break;
3558	} // case C_EBREAK
3559	case RISCV::C_FLD: {
3560	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3561	STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
3562	MI.getOperand(i: `0`).isReg() &&
3563	getRISCVMCRegisterClass(RC: RISCV::FPR64CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3564	MI.getOperand(i: `1`).isReg() &&
3565	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3566	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
3567	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3568	// fld $rd, ${imm12}(${rs1})
3569	OutInst.setOpcode(RISCV::FLD);
3570	// Operand: rd
3571	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3572	// Operand: rs1
3573	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3574	// Operand: imm12
3575	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3576	OutInst.setLoc(MI.getLoc());
3577	return true;
3578	} // if
3579	break;
3580	} // case C_FLD
3581	case RISCV::C_FLDSP: {
3582	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3583	STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
3584	MI.getOperand(i: `0`).isReg() &&
3585	getRISCVMCRegisterClass(RC: RISCV::FPR64RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3586	MI.getOperand(i: `1`).isReg() &&
3587	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3588	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000 /) &&
3589	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3590	// fld $rd, ${imm12}(${rs1})
3591	OutInst.setOpcode(RISCV::FLD);
3592	// Operand: rd
3593	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3594	// Operand: rs1
3595	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3596	// Operand: imm12
3597	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3598	OutInst.setLoc(MI.getLoc());
3599	return true;
3600	} // if
3601	break;
3602	} // case C_FLDSP
3603	case RISCV::C_FLW: {
3604	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3605	STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
3606	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3607	MI.getOperand(i: `0`).isReg() &&
3608	getRISCVMCRegisterClass(RC: RISCV::FPR32CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3609	MI.getOperand(i: `1`).isReg() &&
3610	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3611	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
3612	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3613	// flw $rd, ${imm12}(${rs1})
3614	OutInst.setOpcode(RISCV::FLW);
3615	// Operand: rd
3616	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3617	// Operand: rs1
3618	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3619	// Operand: imm12
3620	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3621	OutInst.setLoc(MI.getLoc());
3622	return true;
3623	} // if
3624	break;
3625	} // case C_FLW
3626	case RISCV::C_FLWSP: {
3627	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3628	STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
3629	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3630	MI.getOperand(i: `0`).isReg() &&
3631	getRISCVMCRegisterClass(RC: RISCV::FPR32RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3632	MI.getOperand(i: `1`).isReg() &&
3633	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3634	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm8_lsb00 /) &&
3635	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3636	// flw $rd, ${imm12}(${rs1})
3637	OutInst.setOpcode(RISCV::FLW);
3638	// Operand: rd
3639	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3640	// Operand: rs1
3641	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3642	// Operand: imm12
3643	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3644	OutInst.setLoc(MI.getLoc());
3645	return true;
3646	} // if
3647	break;
3648	} // case C_FLWSP
3649	case RISCV::C_FSD: {
3650	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3651	STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
3652	MI.getOperand(i: `0`).isReg() &&
3653	getRISCVMCRegisterClass(RC: RISCV::FPR64CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3654	MI.getOperand(i: `1`).isReg() &&
3655	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3656	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
3657	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3658	// fsd $rs2, ${imm12}(${rs1})
3659	OutInst.setOpcode(RISCV::FSD);
3660	// Operand: rs2
3661	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3662	// Operand: rs1
3663	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3664	// Operand: imm12
3665	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3666	OutInst.setLoc(MI.getLoc());
3667	return true;
3668	} // if
3669	break;
3670	} // case C_FSD
3671	case RISCV::C_FSDSP: {
3672	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3673	STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
3674	MI.getOperand(i: `0`).isReg() &&
3675	getRISCVMCRegisterClass(RC: RISCV::FPR64RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3676	MI.getOperand(i: `1`).isReg() &&
3677	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3678	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000 /) &&
3679	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3680	// fsd $rs2, ${imm12}(${rs1})
3681	OutInst.setOpcode(RISCV::FSD);
3682	// Operand: rs2
3683	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3684	// Operand: rs1
3685	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3686	// Operand: imm12
3687	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3688	OutInst.setLoc(MI.getLoc());
3689	return true;
3690	} // if
3691	break;
3692	} // case C_FSDSP
3693	case RISCV::C_FSW: {
3694	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3695	STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
3696	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3697	MI.getOperand(i: `0`).isReg() &&
3698	getRISCVMCRegisterClass(RC: RISCV::FPR32CRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3699	MI.getOperand(i: `1`).isReg() &&
3700	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3701	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
3702	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3703	// fsw $rs2, ${imm12}(${rs1})
3704	OutInst.setOpcode(RISCV::FSW);
3705	// Operand: rs2
3706	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3707	// Operand: rs1
3708	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3709	// Operand: imm12
3710	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3711	OutInst.setLoc(MI.getLoc());
3712	return true;
3713	} // if
3714	break;
3715	} // case C_FSW
3716	case RISCV::C_FSWSP: {
3717	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3718	STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
3719	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3720	MI.getOperand(i: `0`).isReg() &&
3721	getRISCVMCRegisterClass(RC: RISCV::FPR32RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3722	MI.getOperand(i: `1`).isReg() &&
3723	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3724	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm8_lsb00 /) &&
3725	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3726	// fsw $rs2, ${imm12}(${rs1})
3727	OutInst.setOpcode(RISCV::FSW);
3728	// Operand: rs2
3729	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3730	// Operand: rs1
3731	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3732	// Operand: imm12
3733	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3734	OutInst.setLoc(MI.getLoc());
3735	return true;
3736	} // if
3737	break;
3738	} // case C_FSWSP
3739	case RISCV::C_J: {
3740	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3741	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `13` / bare_simm12_lsb0 /) &&
3742	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `14` / simm21_lsb0_jal /)) {
3743	// jal $rd, $imm20
3744	OutInst.setOpcode(RISCV::JAL);
3745	// Operand: rd
3746	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3747	// Operand: imm20
3748	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3749	OutInst.setLoc(MI.getLoc());
3750	return true;
3751	} // if
3752	break;
3753	} // case C_J
3754	case RISCV::C_JAL: {
3755	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3756	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3757	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `13` / bare_simm12_lsb0 /) &&
3758	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `14` / simm21_lsb0_jal /)) {
3759	// jal $rd, $imm20
3760	OutInst.setOpcode(RISCV::JAL);
3761	// Operand: rd
3762	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
3763	// Operand: imm20
3764	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3765	OutInst.setLoc(MI.getLoc());
3766	return true;
3767	} // if
3768	break;
3769	} // case C_JAL
3770	case RISCV::C_JALR: {
3771	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3772	MI.getOperand(i: `0`).isReg() &&
3773	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3774	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3775	// jalr $rd, ${imm12}(${rs1})
3776	OutInst.setOpcode(RISCV::JALR);
3777	// Operand: rd
3778	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
3779	// Operand: rs1
3780	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3781	// Operand: imm12
3782	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3783	OutInst.setLoc(MI.getLoc());
3784	return true;
3785	} // if
3786	break;
3787	} // case C_JALR
3788	case RISCV::C_JR: {
3789	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3790	MI.getOperand(i: `0`).isReg() &&
3791	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3792	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3793	// jalr $rd, ${imm12}(${rs1})
3794	OutInst.setOpcode(RISCV::JALR);
3795	// Operand: rd
3796	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3797	// Operand: rs1
3798	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3799	// Operand: imm12
3800	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3801	OutInst.setLoc(MI.getLoc());
3802	return true;
3803	} // if
3804	break;
3805	} // case C_JR
3806	case RISCV::C_LBU: {
3807	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3808	MI.getOperand(i: `0`).isReg() &&
3809	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3810	MI.getOperand(i: `1`).isReg() &&
3811	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3812	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2 /) &&
3813	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3814	// lbu $rd, ${imm12}(${rs1})
3815	OutInst.setOpcode(RISCV::LBU);
3816	// Operand: rd
3817	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3818	// Operand: rs1
3819	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3820	// Operand: imm12
3821	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3822	OutInst.setLoc(MI.getLoc());
3823	return true;
3824	} // if
3825	break;
3826	} // case C_LBU
3827	case RISCV::C_LD: {
3828	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3829	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3830	MI.getOperand(i: `0`).isReg() &&
3831	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3832	MI.getOperand(i: `1`).isReg() &&
3833	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3834	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
3835	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3836	// ld $rd, ${imm12}(${rs1})
3837	OutInst.setOpcode(RISCV::LD);
3838	// Operand: rd
3839	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3840	// Operand: rs1
3841	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3842	// Operand: imm12
3843	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3844	OutInst.setLoc(MI.getLoc());
3845	return true;
3846	} // if
3847	break;
3848	} // case C_LD
3849	case RISCV::C_LDSP: {
3850	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3851	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3852	MI.getOperand(i: `0`).isReg() &&
3853	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3854	MI.getOperand(i: `1`).isReg() &&
3855	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3856	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000 /) &&
3857	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3858	// ld $rd, ${imm12}(${rs1})
3859	OutInst.setOpcode(RISCV::LD);
3860	// Operand: rd
3861	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3862	// Operand: rs1
3863	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3864	// Operand: imm12
3865	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3866	OutInst.setLoc(MI.getLoc());
3867	return true;
3868	} // if
3869	break;
3870	} // case C_LDSP
3871	case RISCV::C_LDSP_RV32: {
3872	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
3873	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
3874	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3875	MI.getOperand(i: `0`).isReg() &&
3876	getRISCVMCRegisterClass(RC: RISCV::GPRPairNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3877	MI.getOperand(i: `1`).isReg() &&
3878	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3879	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000 /) &&
3880	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3881	// ld $rd, ${imm12}(${rs1})
3882	OutInst.setOpcode(RISCV::LD_RV32);
3883	// Operand: rd
3884	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3885	// Operand: rs1
3886	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3887	// Operand: imm12
3888	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3889	OutInst.setLoc(MI.getLoc());
3890	return true;
3891	} // if
3892	break;
3893	} // case C_LDSP_RV32
3894	case RISCV::C_LD_RV32: {
3895	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
3896	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
3897	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3898	MI.getOperand(i: `0`).isReg() &&
3899	getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3900	MI.getOperand(i: `1`).isReg() &&
3901	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3902	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
3903	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3904	// ld $rd, ${imm12}(${rs1})
3905	OutInst.setOpcode(RISCV::LD_RV32);
3906	// Operand: rd
3907	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3908	// Operand: rs1
3909	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3910	// Operand: imm12
3911	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3912	OutInst.setLoc(MI.getLoc());
3913	return true;
3914	} // if
3915	break;
3916	} // case C_LD_RV32
3917	case RISCV::C_LH: {
3918	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3919	MI.getOperand(i: `0`).isReg() &&
3920	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3921	MI.getOperand(i: `1`).isReg() &&
3922	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3923	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm2_lsb0 /) &&
3924	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3925	// lh $rd, ${imm12}(${rs1})
3926	OutInst.setOpcode(RISCV::LH);
3927	// Operand: rd
3928	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3929	// Operand: rs1
3930	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3931	// Operand: imm12
3932	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3933	OutInst.setLoc(MI.getLoc());
3934	return true;
3935	} // if
3936	break;
3937	} // case C_LH
3938	case RISCV::C_LHU: {
3939	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3940	MI.getOperand(i: `0`).isReg() &&
3941	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3942	MI.getOperand(i: `1`).isReg() &&
3943	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3944	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm2_lsb0 /) &&
3945	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
3946	// lhu $rd, ${imm12}(${rs1})
3947	OutInst.setOpcode(RISCV::LHU);
3948	// Operand: rd
3949	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3950	// Operand: rs1
3951	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3952	// Operand: imm12
3953	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3954	OutInst.setLoc(MI.getLoc());
3955	return true;
3956	} // if
3957	break;
3958	} // case C_LHU
3959	case RISCV::C_LI: {
3960	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3961	MI.getOperand(i: `0`).isReg() &&
3962	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3963	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `5` / simm6 /) &&
3964	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `2` / simm12_lo /)) {
3965	// addi $rd, $rs1, $imm12
3966	OutInst.setOpcode(RISCV::ADDI);
3967	// Operand: rd
3968	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3969	// Operand: rs1
3970	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3971	// Operand: imm12
3972	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3973	OutInst.setLoc(MI.getLoc());
3974	return true;
3975	} // if
3976	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
3977	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3978	MI.getOperand(i: `0`).isReg() &&
3979	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3980	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `5` / simm6 /) &&
3981	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `17` / simm20_li /)) {
3982	// qc.li $rd, $imm20
3983	OutInst.setOpcode(RISCV::QC_LI);
3984	// Operand: rd
3985	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3986	// Operand: imm20
3987	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3988	OutInst.setLoc(MI.getLoc());
3989	return true;
3990	} // if
3991	break;
3992	} // case C_LI
3993	case RISCV::C_LUI: {
3994	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
3995	MI.getOperand(i: `0`).isReg() &&
3996	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0X2RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3997	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `18` / c_lui_imm /) &&
3998	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `19` / uimm20_lui /)) {
3999	// lui $rd, $imm20
4000	OutInst.setOpcode(RISCV::LUI);
4001	// Operand: rd
4002	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4003	// Operand: imm20
4004	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4005	OutInst.setLoc(MI.getLoc());
4006	return true;
4007	} // if
4008	break;
4009	} // case C_LUI
4010	case RISCV::C_LW: {
4011	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4012	MI.getOperand(i: `0`).isReg() &&
4013	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4014	MI.getOperand(i: `1`).isReg() &&
4015	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4016	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
4017	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4018	// lw $rd, ${imm12}(${rs1})
4019	OutInst.setOpcode(RISCV::LW);
4020	// Operand: rd
4021	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4022	// Operand: rs1
4023	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4024	// Operand: imm12
4025	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4026	OutInst.setLoc(MI.getLoc());
4027	return true;
4028	} // if
4029	break;
4030	} // case C_LW
4031	case RISCV::C_LWSP: {
4032	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4033	MI.getOperand(i: `0`).isReg() &&
4034	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4035	MI.getOperand(i: `1`).isReg() &&
4036	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4037	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm8_lsb00 /) &&
4038	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4039	// lw $rd, ${imm12}(${rs1})
4040	OutInst.setOpcode(RISCV::LW);
4041	// Operand: rd
4042	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4043	// Operand: rs1
4044	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4045	// Operand: imm12
4046	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4047	OutInst.setLoc(MI.getLoc());
4048	return true;
4049	} // if
4050	break;
4051	} // case C_LWSP
4052	case RISCV::C_MUL: {
4053	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4054	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
4055	MI.getOperand(i: `0`).isReg() &&
4056	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4057	MI.getOperand(i: `0`).isReg() &&
4058	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4059	MI.getOperand(i: `2`).isReg() &&
4060	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
4061	// mul $rd, $rs1, $rs2
4062	OutInst.setOpcode(RISCV::MUL);
4063	// Operand: rd
4064	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4065	// Operand: rs1
4066	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4067	// Operand: rs2
4068	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4069	OutInst.setLoc(MI.getLoc());
4070	return true;
4071	} // if
4072	break;
4073	} // case C_MUL
4074	case RISCV::C_MV: {
4075	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4076	MI.getOperand(i: `0`).isReg() &&
4077	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4078	MI.getOperand(i: `1`).isReg() &&
4079	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4080	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `2` / simm12_lo /)) {
4081	// addi $rd, $rs1, $imm12
4082	OutInst.setOpcode(RISCV::ADDI);
4083	// Operand: rd
4084	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4085	// Operand: rs1
4086	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4087	// Operand: imm12
4088	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
4089	OutInst.setLoc(MI.getLoc());
4090	return true;
4091	} // if
4092	break;
4093	} // case C_MV
4094	case RISCV::C_NOP: {
4095	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4096	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `2` / simm12_lo /)) {
4097	// addi $rd, $rs1, $imm12
4098	OutInst.setOpcode(RISCV::ADDI);
4099	// Operand: rd
4100	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
4101	// Operand: rs1
4102	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
4103	// Operand: imm12
4104	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
4105	OutInst.setLoc(MI.getLoc());
4106	return true;
4107	} // if
4108	break;
4109	} // case C_NOP
4110	case RISCV::C_NOT: {
4111	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4112	MI.getOperand(i: `0`).isReg() &&
4113	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4114	MI.getOperand(i: `0`).isReg() &&
4115	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4116	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: -`1`), STI, PredicateIndex: `2` / simm12_lo /)) {
4117	// xori $rd, $rs1, $imm12
4118	OutInst.setOpcode(RISCV::XORI);
4119	// Operand: rd
4120	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4121	// Operand: rs1
4122	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4123	// Operand: imm12
4124	OutInst.addOperand(Op: MCOperand::createImm(Val: -`1`));
4125	OutInst.setLoc(MI.getLoc());
4126	return true;
4127	} // if
4128	break;
4129	} // case C_NOT
4130	case RISCV::C_OR: {
4131	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4132	MI.getOperand(i: `0`).isReg() &&
4133	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4134	MI.getOperand(i: `0`).isReg() &&
4135	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4136	MI.getOperand(i: `2`).isReg() &&
4137	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
4138	// or $rd, $rs1, $rs2
4139	OutInst.setOpcode(RISCV::OR);
4140	// Operand: rd
4141	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4142	// Operand: rs1
4143	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4144	// Operand: rs2
4145	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4146	OutInst.setLoc(MI.getLoc());
4147	return true;
4148	} // if
4149	break;
4150	} // case C_OR
4151	case RISCV::C_SB: {
4152	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4153	MI.getOperand(i: `0`).isReg() &&
4154	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4155	MI.getOperand(i: `1`).isReg() &&
4156	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4157	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2 /) &&
4158	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4159	// sb $rs2, ${imm12}(${rs1})
4160	OutInst.setOpcode(RISCV::SB);
4161	// Operand: rs2
4162	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4163	// Operand: rs1
4164	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4165	// Operand: imm12
4166	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4167	OutInst.setLoc(MI.getLoc());
4168	return true;
4169	} // if
4170	break;
4171	} // case C_SB
4172	case RISCV::C_SD: {
4173	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4174	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4175	MI.getOperand(i: `0`).isReg() &&
4176	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4177	MI.getOperand(i: `1`).isReg() &&
4178	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4179	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
4180	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4181	// sd $rs2, ${imm12}(${rs1})
4182	OutInst.setOpcode(RISCV::SD);
4183	// Operand: rs2
4184	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4185	// Operand: rs1
4186	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4187	// Operand: imm12
4188	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4189	OutInst.setLoc(MI.getLoc());
4190	return true;
4191	} // if
4192	break;
4193	} // case C_SD
4194	case RISCV::C_SDSP: {
4195	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4196	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4197	MI.getOperand(i: `0`).isReg() &&
4198	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4199	MI.getOperand(i: `1`).isReg() &&
4200	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4201	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000 /) &&
4202	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4203	// sd $rs2, ${imm12}(${rs1})
4204	OutInst.setOpcode(RISCV::SD);
4205	// Operand: rs2
4206	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4207	// Operand: rs1
4208	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4209	// Operand: imm12
4210	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4211	OutInst.setLoc(MI.getLoc());
4212	return true;
4213	} // if
4214	break;
4215	} // case C_SDSP
4216	case RISCV::C_SDSP_RV32: {
4217	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
4218	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
4219	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4220	MI.getOperand(i: `0`).isReg() &&
4221	getRISCVMCRegisterClass(RC: RISCV::GPRPairRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4222	MI.getOperand(i: `1`).isReg() &&
4223	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4224	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm9_lsb000 /) &&
4225	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4226	// sd $rs2, ${imm12}(${rs1})
4227	OutInst.setOpcode(RISCV::SD_RV32);
4228	// Operand: rs2
4229	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4230	// Operand: rs1
4231	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4232	// Operand: imm12
4233	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4234	OutInst.setLoc(MI.getLoc());
4235	return true;
4236	} // if
4237	break;
4238	} // case C_SDSP_RV32
4239	case RISCV::C_SD_RV32: {
4240	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
4241	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
4242	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4243	MI.getOperand(i: `0`).isReg() &&
4244	getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4245	MI.getOperand(i: `1`).isReg() &&
4246	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4247	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
4248	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4249	// sd $rs2, ${imm12}(${rs1})
4250	OutInst.setOpcode(RISCV::SD_RV32);
4251	// Operand: rs2
4252	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4253	// Operand: rs1
4254	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4255	// Operand: imm12
4256	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4257	OutInst.setLoc(MI.getLoc());
4258	return true;
4259	} // if
4260	break;
4261	} // case C_SD_RV32
4262	case RISCV::C_SEXT_B: {
4263	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4264	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4265	MI.getOperand(i: `0`).isReg() &&
4266	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4267	MI.getOperand(i: `0`).isReg() &&
4268	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg())) {
4269	// sext.b $rd, $rs1
4270	OutInst.setOpcode(RISCV::SEXT_B);
4271	// Operand: rd
4272	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4273	// Operand: rs1
4274	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4275	OutInst.setLoc(MI.getLoc());
4276	return true;
4277	} // if
4278	break;
4279	} // case C_SEXT_B
4280	case RISCV::C_SEXT_H: {
4281	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4282	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4283	MI.getOperand(i: `0`).isReg() &&
4284	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4285	MI.getOperand(i: `0`).isReg() &&
4286	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg())) {
4287	// sext.h $rd, $rs1
4288	OutInst.setOpcode(RISCV::SEXT_H);
4289	// Operand: rd
4290	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4291	// Operand: rs1
4292	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4293	OutInst.setLoc(MI.getLoc());
4294	return true;
4295	} // if
4296	break;
4297	} // case C_SEXT_H
4298	case RISCV::C_SH: {
4299	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4300	MI.getOperand(i: `0`).isReg() &&
4301	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4302	MI.getOperand(i: `1`).isReg() &&
4303	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4304	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm2_lsb0 /) &&
4305	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4306	// sh $rs2, ${imm12}(${rs1})
4307	OutInst.setOpcode(RISCV::SH);
4308	// Operand: rs2
4309	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4310	// Operand: rs1
4311	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4312	// Operand: imm12
4313	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4314	OutInst.setLoc(MI.getLoc());
4315	return true;
4316	} // if
4317	break;
4318	} // case C_SH
4319	case RISCV::C_SLLI: {
4320	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4321	MI.getOperand(i: `0`).isReg() &&
4322	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4323	MI.getOperand(i: `0`).isReg() &&
4324	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4325	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlennonzero /) &&
4326	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21` / uimmlog2xlen /)) {
4327	// slli $rd, $rs1, $shamt
4328	OutInst.setOpcode(RISCV::SLLI);
4329	// Operand: rd
4330	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4331	// Operand: rs1
4332	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4333	// Operand: shamt
4334	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4335	OutInst.setLoc(MI.getLoc());
4336	return true;
4337	} // if
4338	break;
4339	} // case C_SLLI
4340	case RISCV::C_SRAI: {
4341	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4342	MI.getOperand(i: `0`).isReg() &&
4343	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4344	MI.getOperand(i: `0`).isReg() &&
4345	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4346	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlennonzero /) &&
4347	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21` / uimmlog2xlen /)) {
4348	// srai $rd, $rs1, $shamt
4349	OutInst.setOpcode(RISCV::SRAI);
4350	// Operand: rd
4351	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4352	// Operand: rs1
4353	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4354	// Operand: shamt
4355	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4356	OutInst.setLoc(MI.getLoc());
4357	return true;
4358	} // if
4359	break;
4360	} // case C_SRAI
4361	case RISCV::C_SRLI: {
4362	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4363	MI.getOperand(i: `0`).isReg() &&
4364	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4365	MI.getOperand(i: `0`).isReg() &&
4366	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4367	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlennonzero /) &&
4368	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21` / uimmlog2xlen /)) {
4369	// srli $rd, $rs1, $shamt
4370	OutInst.setOpcode(RISCV::SRLI);
4371	// Operand: rd
4372	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4373	// Operand: rs1
4374	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4375	// Operand: shamt
4376	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4377	OutInst.setLoc(MI.getLoc());
4378	return true;
4379	} // if
4380	break;
4381	} // case C_SRLI
4382	case RISCV::C_SSPOPCHK: {
4383	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
4384	STI.getFeatureBits()[RISCV::FeatureStdExtZimop] &&
4385	MI.getOperand(i: `0`).isReg() &&
4386	(MI.getOperand(i: `0`).getReg() == RISCV::X5)) {
4387	// sspopchk $rs1
4388	OutInst.setOpcode(RISCV::SSPOPCHK);
4389	// Operand: rs1
4390	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
4391	OutInst.setLoc(MI.getLoc());
4392	return true;
4393	} // if
4394	break;
4395	} // case C_SSPOPCHK
4396	case RISCV::C_SSPUSH: {
4397	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
4398	STI.getFeatureBits()[RISCV::FeatureStdExtZimop] &&
4399	MI.getOperand(i: `0`).isReg() &&
4400	(MI.getOperand(i: `0`).getReg() == RISCV::X1)) {
4401	// sspush $rs2
4402	OutInst.setOpcode(RISCV::SSPUSH);
4403	// Operand: rs2
4404	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
4405	OutInst.setLoc(MI.getLoc());
4406	return true;
4407	} // if
4408	break;
4409	} // case C_SSPUSH
4410	case RISCV::C_SUB: {
4411	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4412	MI.getOperand(i: `0`).isReg() &&
4413	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4414	MI.getOperand(i: `0`).isReg() &&
4415	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4416	MI.getOperand(i: `2`).isReg() &&
4417	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
4418	// sub $rd, $rs1, $rs2
4419	OutInst.setOpcode(RISCV::SUB);
4420	// Operand: rd
4421	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4422	// Operand: rs1
4423	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4424	// Operand: rs2
4425	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4426	OutInst.setLoc(MI.getLoc());
4427	return true;
4428	} // if
4429	break;
4430	} // case C_SUB
4431	case RISCV::C_SUBW: {
4432	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4433	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4434	MI.getOperand(i: `0`).isReg() &&
4435	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4436	MI.getOperand(i: `0`).isReg() &&
4437	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4438	MI.getOperand(i: `2`).isReg() &&
4439	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
4440	// subw $rd, $rs1, $rs2
4441	OutInst.setOpcode(RISCV::SUBW);
4442	// Operand: rd
4443	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4444	// Operand: rs1
4445	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4446	// Operand: rs2
4447	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4448	OutInst.setLoc(MI.getLoc());
4449	return true;
4450	} // if
4451	break;
4452	} // case C_SUBW
4453	case RISCV::C_SW: {
4454	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4455	MI.getOperand(i: `0`).isReg() &&
4456	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4457	MI.getOperand(i: `1`).isReg() &&
4458	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4459	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm7_lsb00 /) &&
4460	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4461	// sw $rs2, ${imm12}(${rs1})
4462	OutInst.setOpcode(RISCV::SW);
4463	// Operand: rs2
4464	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4465	// Operand: rs1
4466	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4467	// Operand: imm12
4468	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4469	OutInst.setLoc(MI.getLoc());
4470	return true;
4471	} // if
4472	break;
4473	} // case C_SW
4474	case RISCV::C_SWSP: {
4475	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4476	MI.getOperand(i: `0`).isReg() &&
4477	getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4478	MI.getOperand(i: `1`).isReg() &&
4479	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4480	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm8_lsb00 /) &&
4481	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4482	// sw $rs2, ${imm12}(${rs1})
4483	OutInst.setOpcode(RISCV::SW);
4484	// Operand: rs2
4485	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4486	// Operand: rs1
4487	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4488	// Operand: imm12
4489	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4490	OutInst.setLoc(MI.getLoc());
4491	return true;
4492	} // if
4493	break;
4494	} // case C_SWSP
4495	case RISCV::C_UNIMP: {
4496	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) {
4497	// unimp
4498	OutInst.setOpcode(RISCV::UNIMP);
4499	OutInst.setLoc(MI.getLoc());
4500	return true;
4501	} // if
4502	break;
4503	} // case C_UNIMP
4504	case RISCV::C_XOR: {
4505	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
4506	MI.getOperand(i: `0`).isReg() &&
4507	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4508	MI.getOperand(i: `0`).isReg() &&
4509	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4510	MI.getOperand(i: `2`).isReg() &&
4511	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
4512	// xor $rd, $rs1, $rs2
4513	OutInst.setOpcode(RISCV::XOR);
4514	// Operand: rd
4515	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4516	// Operand: rs1
4517	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4518	// Operand: rs2
4519	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4520	OutInst.setLoc(MI.getLoc());
4521	return true;
4522	} // if
4523	break;
4524	} // case C_XOR
4525	case RISCV::C_ZEXT_B: {
4526	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4527	MI.getOperand(i: `0`).isReg() &&
4528	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4529	MI.getOperand(i: `0`).isReg() &&
4530	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4531	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `255`), STI, PredicateIndex: `2` / simm12_lo /)) {
4532	// andi $rd, $rs1, $imm12
4533	OutInst.setOpcode(RISCV::ANDI);
4534	// Operand: rd
4535	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4536	// Operand: rs1
4537	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4538	// Operand: imm12
4539	OutInst.addOperand(Op: MCOperand::createImm(Val: `255`));
4540	OutInst.setLoc(MI.getLoc());
4541	return true;
4542	} // if
4543	break;
4544	} // case C_ZEXT_B
4545	case RISCV::C_ZEXT_H: {
4546	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4547	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4548	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4549	(STI.getFeatureBits()[RISCV::FeatureStdExtZbb] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZbkb]) &&
4550	MI.getOperand(i: `0`).isReg() &&
4551	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4552	MI.getOperand(i: `0`).isReg() &&
4553	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg())) {
4554	// zext.h $rd, $rs1
4555	OutInst.setOpcode(RISCV::ZEXT_H_RV32);
4556	// Operand: rd
4557	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4558	// Operand: rs1
4559	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4560	OutInst.setLoc(MI.getLoc());
4561	return true;
4562	} // if
4563	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4564	STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4565	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4566	(STI.getFeatureBits()[RISCV::FeatureStdExtZbb] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZbkb]) &&
4567	MI.getOperand(i: `0`).isReg() &&
4568	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4569	MI.getOperand(i: `0`).isReg() &&
4570	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg())) {
4571	// zext.h $rd, $rs1
4572	OutInst.setOpcode(RISCV::ZEXT_H_RV64);
4573	// Operand: rd
4574	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4575	// Operand: rs1
4576	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4577	OutInst.setLoc(MI.getLoc());
4578	return true;
4579	} // if
4580	break;
4581	} // case C_ZEXT_H
4582	case RISCV::C_ZEXT_W: {
4583	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4584	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
4585	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4586	MI.getOperand(i: `0`).isReg() &&
4587	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4588	MI.getOperand(i: `0`).isReg() &&
4589	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg())) {
4590	// add.uw $rd, $rs1, $rs2
4591	OutInst.setOpcode(RISCV::ADD_UW);
4592	// Operand: rd
4593	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4594	// Operand: rs1
4595	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4596	// Operand: rs2
4597	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
4598	OutInst.setLoc(MI.getLoc());
4599	return true;
4600	} // if
4601	break;
4602	} // case C_ZEXT_W
4603	case RISCV::QC_C_BEXTI: {
4604	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
4605	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4606	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4607	MI.getOperand(i: `0`).isReg() &&
4608	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4609	MI.getOperand(i: `0`).isReg() &&
4610	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4611	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlennonzero /) &&
4612	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21` / uimmlog2xlen /)) {
4613	// bexti $rd, $rs1, $shamt
4614	OutInst.setOpcode(RISCV::BEXTI);
4615	// Operand: rd
4616	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4617	// Operand: rs1
4618	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4619	// Operand: shamt
4620	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4621	OutInst.setLoc(MI.getLoc());
4622	return true;
4623	} // if
4624	break;
4625	} // case QC_C_BEXTI
4626	case RISCV::QC_C_BSETI: {
4627	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
4628	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4629	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4630	MI.getOperand(i: `0`).isReg() &&
4631	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4632	MI.getOperand(i: `0`).isReg() &&
4633	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4634	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlennonzero /) &&
4635	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21` / uimmlog2xlen /)) {
4636	// bseti $rd, $rs1, $shamt
4637	OutInst.setOpcode(RISCV::BSETI);
4638	// Operand: rd
4639	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4640	// Operand: rs1
4641	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4642	// Operand: shamt
4643	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4644	OutInst.setLoc(MI.getLoc());
4645	return true;
4646	} // if
4647	break;
4648	} // case QC_C_BSETI
4649	case RISCV::QC_C_EXTU: {
4650	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4651	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4652	MI.getOperand(i: `0`).isReg() &&
4653	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4654	MI.getOperand(i: `0`).isReg() &&
4655	getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4656	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm5ge6_plus1 /) &&
4657	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm5_plus1 /) &&
4658	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `24` / uimm5 /)) {
4659	// qc.extu $rd, $rs1, $width, $shamt
4660	OutInst.setOpcode(RISCV::QC_EXTU);
4661	// Operand: rd
4662	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4663	// Operand: rs1
4664	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4665	// Operand: width
4666	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4667	// Operand: shamt
4668	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
4669	OutInst.setLoc(MI.getLoc());
4670	return true;
4671	} // if
4672	break;
4673	} // case QC_C_EXTU
4674	case RISCV::QC_C_MVEQZ: {
4675	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
4676	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4677	MI.getOperand(i: `0`).isReg() &&
4678	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4679	MI.getOperand(i: `0`).isReg() &&
4680	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4681	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `25` / simm5 /) &&
4682	MI.getOperand(i: `2`).isReg() &&
4683	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `2`).getReg())) {
4684	// qc.mveqi $rd, $rs1, $imm, $rs3
4685	OutInst.setOpcode(RISCV::QC_MVEQI);
4686	// Operand: rd_wb
4687	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4688	// Operand: rd
4689	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4690	// Operand: rs1
4691	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4692	// Operand: imm
4693	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
4694	// Operand: rs3
4695	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4696	OutInst.setLoc(MI.getLoc());
4697	return true;
4698	} // if
4699	break;
4700	} // case QC_C_MVEQZ
4701	case RISCV::QC_C_SYNC: {
4702	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4703	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4704	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26` / uimm5slist /) &&
4705	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `24` / uimm5 /)) {
4706	// qc.sync $imm5
4707	OutInst.setOpcode(RISCV::QC_SYNC);
4708	// Operand: imm5
4709	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4710	OutInst.setLoc(MI.getLoc());
4711	return true;
4712	} // if
4713	break;
4714	} // case QC_C_SYNC
4715	case RISCV::QC_C_SYNCR: {
4716	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4717	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4718	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26` / uimm5slist /) &&
4719	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `24` / uimm5 /)) {
4720	// qc.syncr $imm5
4721	OutInst.setOpcode(RISCV::QC_SYNCR);
4722	// Operand: imm5
4723	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4724	OutInst.setLoc(MI.getLoc());
4725	return true;
4726	} // if
4727	break;
4728	} // case QC_C_SYNCR
4729	case RISCV::QC_C_SYNCWF: {
4730	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4731	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4732	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26` / uimm5slist /) &&
4733	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `24` / uimm5 /)) {
4734	// qc.syncwf $imm5
4735	OutInst.setOpcode(RISCV::QC_SYNCWF);
4736	// Operand: imm5
4737	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4738	OutInst.setLoc(MI.getLoc());
4739	return true;
4740	} // if
4741	break;
4742	} // case QC_C_SYNCWF
4743	case RISCV::QC_C_SYNCWL: {
4744	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4745	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4746	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26` / uimm5slist /) &&
4747	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `24` / uimm5 /)) {
4748	// qc.syncwl $imm5
4749	OutInst.setOpcode(RISCV::QC_SYNCWL);
4750	// Operand: imm5
4751	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4752	OutInst.setLoc(MI.getLoc());
4753	return true;
4754	} // if
4755	break;
4756	} // case QC_C_SYNCWL
4757	case RISCV::QK_C_LBU: {
4758	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4759	MI.getOperand(i: `0`).isReg() &&
4760	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4761	MI.getOperand(i: `1`).isReg() &&
4762	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4763	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24` / uimm5 /) &&
4764	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4765	// lbu $rd, ${imm12}(${rs1})
4766	OutInst.setOpcode(RISCV::LBU);
4767	// Operand: rd
4768	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4769	// Operand: rs1
4770	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4771	// Operand: imm12
4772	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4773	OutInst.setLoc(MI.getLoc());
4774	return true;
4775	} // if
4776	break;
4777	} // case QK_C_LBU
4778	case RISCV::QK_C_LBUSP: {
4779	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4780	MI.getOperand(i: `0`).isReg() &&
4781	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4782	MI.getOperand(i: `1`).isReg() &&
4783	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4784	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimm4 /) &&
4785	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4786	// lbu $rd, ${imm12}(${rs1})
4787	OutInst.setOpcode(RISCV::LBU);
4788	// Operand: rd
4789	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4790	// Operand: rs1
4791	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4792	// Operand: imm12
4793	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4794	OutInst.setLoc(MI.getLoc());
4795	return true;
4796	} // if
4797	break;
4798	} // case QK_C_LBUSP
4799	case RISCV::QK_C_LHU: {
4800	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4801	MI.getOperand(i: `0`).isReg() &&
4802	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4803	MI.getOperand(i: `1`).isReg() &&
4804	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4805	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `28` / uimm6_lsb0 /) &&
4806	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4807	// lhu $rd, ${imm12}(${rs1})
4808	OutInst.setOpcode(RISCV::LHU);
4809	// Operand: rd
4810	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4811	// Operand: rs1
4812	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4813	// Operand: imm12
4814	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4815	OutInst.setLoc(MI.getLoc());
4816	return true;
4817	} // if
4818	break;
4819	} // case QK_C_LHU
4820	case RISCV::QK_C_LHUSP: {
4821	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4822	MI.getOperand(i: `0`).isReg() &&
4823	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4824	MI.getOperand(i: `1`).isReg() &&
4825	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4826	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `29` / uimm5_lsb0 /) &&
4827	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4828	// lhu $rd, ${imm12}(${rs1})
4829	OutInst.setOpcode(RISCV::LHU);
4830	// Operand: rd
4831	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4832	// Operand: rs1
4833	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4834	// Operand: imm12
4835	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4836	OutInst.setLoc(MI.getLoc());
4837	return true;
4838	} // if
4839	break;
4840	} // case QK_C_LHUSP
4841	case RISCV::QK_C_SB: {
4842	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4843	MI.getOperand(i: `0`).isReg() &&
4844	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4845	MI.getOperand(i: `1`).isReg() &&
4846	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4847	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24` / uimm5 /) &&
4848	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4849	// sb $rs2, ${imm12}(${rs1})
4850	OutInst.setOpcode(RISCV::SB);
4851	// Operand: rs2
4852	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4853	// Operand: rs1
4854	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4855	// Operand: imm12
4856	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4857	OutInst.setLoc(MI.getLoc());
4858	return true;
4859	} // if
4860	break;
4861	} // case QK_C_SB
4862	case RISCV::QK_C_SBSP: {
4863	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4864	MI.getOperand(i: `0`).isReg() &&
4865	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4866	MI.getOperand(i: `1`).isReg() &&
4867	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4868	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimm4 /) &&
4869	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4870	// sb $rs2, ${imm12}(${rs1})
4871	OutInst.setOpcode(RISCV::SB);
4872	// Operand: rs2
4873	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4874	// Operand: rs1
4875	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4876	// Operand: imm12
4877	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4878	OutInst.setLoc(MI.getLoc());
4879	return true;
4880	} // if
4881	break;
4882	} // case QK_C_SBSP
4883	case RISCV::QK_C_SH: {
4884	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4885	MI.getOperand(i: `0`).isReg() &&
4886	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4887	MI.getOperand(i: `1`).isReg() &&
4888	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4889	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `28` / uimm6_lsb0 /) &&
4890	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4891	// sh $rs2, ${imm12}(${rs1})
4892	OutInst.setOpcode(RISCV::SH);
4893	// Operand: rs2
4894	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4895	// Operand: rs1
4896	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4897	// Operand: imm12
4898	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4899	OutInst.setLoc(MI.getLoc());
4900	return true;
4901	} // if
4902	break;
4903	} // case QK_C_SH
4904	case RISCV::QK_C_SHSP: {
4905	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4906	MI.getOperand(i: `0`).isReg() &&
4907	getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4908	MI.getOperand(i: `1`).isReg() &&
4909	getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4910	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `29` / uimm5_lsb0 /) &&
4911	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / simm12_lo_optional /)) {
4912	// sh $rs2, ${imm12}(${rs1})
4913	OutInst.setOpcode(RISCV::SH);
4914	// Operand: rs2
4915	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4916	// Operand: rs1
4917	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4918	// Operand: imm12
4919	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4920	OutInst.setLoc(MI.getLoc());
4921	return true;
4922	} // if
4923	break;
4924	} // case QK_C_SHSP
4925	} // switch
4926	return false;
4927	}
4928
4929	#endif // GEN_UNCOMPRESS_INSTR
4930
4931	#ifdef GEN_CHECK_COMPRESS_INSTR
4932	#undef GEN_CHECK_COMPRESS_INSTR
4933
4934	static bool RISCVValidateMachineOperand(const MachineOperand &MO,
4935	const RISCVSubtarget *Subtarget,
4936	unsigned PredicateIndex) {
4937	int64_t Imm = MO.getImm();
4938	switch (PredicateIndex) {
4939	default:
4940	llvm_unreachable("Unknown ImmLeaf Predicate kind");
4941	break;
4942	case `1`: {
4943	// simm6nonzero
4944	return (Imm != `0`) && isInt<`6`>(Imm);
4945	}
4946	case `2`: {
4947	// simm6
4948	return isInt<`6`>(Imm);
4949	}
4950	case `3`: {
4951	// simm10_lsb0000nonzero
4952	return (Imm != `0`) && isShiftedInt<`6`, `4`>(Imm);
4953	}
4954	case `4`: {
4955	// uimm10_lsb00nonzero
4956	return isShiftedUInt<`8`, `2`>(Imm) && (Imm != `0`);
4957	}
4958	case `5`: {
4959	// bare_simm9_lsb0
4960	return isShiftedInt<`8`, `1`>(Imm);
4961	}
4962	case `6`: {
4963	// uimmlog2xlennonzero
4964	if (Subtarget->is64Bit())
4965	return isUInt<`6`>(Imm) && (Imm != `0`);
4966	return isUInt<`5`>(Imm) && (Imm != `0`);
4967	}
4968	case `7`: {
4969	// uimm8_lsb000
4970	return isShiftedUInt<`5`, `3`>(Imm);
4971	}
4972	case `8`: {
4973	// uimm8_lsb000_optional
4974	return isShiftedUInt<`5`, `3`>(Imm);
4975	}
4976	case `9`: {
4977	// uimm9_lsb000
4978	return isShiftedUInt<`6`, `3`>(Imm);
4979	}
4980	case `10`: {
4981	// uimm9_lsb000_optional
4982	return isShiftedUInt<`6`, `3`>(Imm);
4983	}
4984	case `11`: {
4985	// uimm7_lsb00
4986	return isShiftedUInt<`5`, `2`>(Imm);
4987	}
4988	case `12`: {
4989	// uimm7_lsb00_optional
4990	return isShiftedUInt<`5`, `2`>(Imm);
4991	}
4992	case `13`: {
4993	// uimm8_lsb00
4994	return isShiftedUInt<`6`, `2`>(Imm);
4995	}
4996	case `14`: {
4997	// uimm8_lsb00_optional
4998	return isShiftedUInt<`6`, `2`>(Imm);
4999	}
5000	case `15`: {
5001	// bare_simm12_lsb0
5002	return isShiftedInt<`11`, `1`>(Imm);
5003	}
5004	case `16`: {
5005	// uimm2
5006	return isUInt<`2`>(Imm);
5007	}
5008	case `17`: {
5009	// uimm2_optional
5010	return isUInt<`2`>(Imm);
5011	}
5012	case `18`: {
5013	// uimm5
5014	return isUInt<`5`>(Imm);
5015	}
5016	case `19`: {
5017	// uimm5_optional
5018	return isUInt<`5`>(Imm);
5019	}
5020	case `20`: {
5021	// uimm4
5022	return isUInt<`4`>(Imm);
5023	}
5024	case `21`: {
5025	// uimm4_optional
5026	return isUInt<`4`>(Imm);
5027	}
5028	case `22`: {
5029	// uimm2_lsb0
5030	return isShiftedUInt<`1`, `1`>(Imm);
5031	}
5032	case `23`: {
5033	// uimm2_lsb0_optional
5034	return isShiftedUInt<`1`, `1`>(Imm);
5035	}
5036	case `24`: {
5037	// uimm6_lsb0
5038	return isShiftedUInt<`5`, `1`>(Imm);
5039	}
5040	case `25`: {
5041	// uimm6_lsb0_optional
5042	return isShiftedUInt<`5`, `1`>(Imm);
5043	}
5044	case `26`: {
5045	// uimm5_lsb0
5046	return isShiftedUInt<`4`, `1`>(Imm);
5047	}
5048	case `27`: {
5049	// uimm5_lsb0_optional
5050	return isShiftedUInt<`4`, `1`>(Imm);
5051	}
5052	case `28`: {
5053	// c_lui_imm
5054	return (Imm != `0`) &&
5055	(isUInt<`5`>(Imm) \|\|
5056	(Imm >= `0xfffe0` && Imm <= `0xfffff`));
5057	}
5058	case `29`: {
5059	// uimm5ge6_plus1
5060	return Imm >= `6` && Imm <= `32`;
5061	}
5062	case `30`: {
5063	// simm12_lo
5064	return isInt<`12`>(Imm);
5065	}
5066	case `31`: {
5067	// simm5nonzero
5068	return (Imm != `0`) && isInt<`5`>(Imm);
5069	}
5070	case `32`: {
5071	// bare_simm13_lsb0
5072	return isShiftedInt<`12`, `1`>(Imm);
5073	}
5074	case `33`: {
5075	// uimm5nonzero
5076	return (Imm != `0`) && isUInt<`5`>(Imm);
5077	}
5078	case `34`: {
5079	// simm21_lsb0_jal
5080	return isShiftedInt<`20`, `1`>(Imm);
5081	}
5082	case `35`: {
5083	// simm12_lo_optional
5084	return isInt<`12`>(Imm);
5085	}
5086	case `36`: {
5087	// simm20_li
5088	return isInt<`20`>(Imm);
5089	}
5090	case `37`: {
5091	// uimm5slist
5092	return ((Imm == `0`) \|\|
5093	(Imm == `1`) \|\|
5094	(Imm == `2`) \|\|
5095	(Imm == `4`) \|\|
5096	(Imm == `8`) \|\|
5097	(Imm == `16`) \|\|
5098	(Imm == `15`) \|\|
5099	(Imm == `31`));
5100	}
5101	case `38`: {
5102	// uimmlog2xlen
5103	if (Subtarget->is64Bit())
5104	return isUInt<`6`>(Imm);
5105	return isUInt<`5`>(Imm);
5106	}
5107	}
5108	}
5109
5110	static bool isCompressibleInst(const MachineInstr &MI,
5111	const RISCVSubtarget &STI) {
5112	switch (MI.getOpcode()) {
5113	default: return false;
5114	case RISCV::ADD: {
5115	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5116	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5117	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5118	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5119	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
5120	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5121	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`2`).getReg())) {
5122	// c.add $rs1, $rs2
5123	// Operand: rd
5124	// Operand: rs1
5125	// Operand: rs2
5126	return true;
5127	} // if
5128	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5129	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5130	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5131	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5132	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`2`).getReg()) &&
5133	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5134	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg())) {
5135	// c.add $rs1, $rs2
5136	// Operand: rd
5137	// Operand: rs1
5138	// Operand: rs2
5139	return true;
5140	} // if
5141	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5142	MI.getOperand(`1`).isReg() &&
5143	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5144	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5145	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5146	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5147	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`2`).getReg())) {
5148	// c.mv $rs1, $rs2
5149	// Operand: rs1
5150	// Operand: rs2
5151	return true;
5152	} // if
5153	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5154	MI.getOperand(`2`).isReg() &&
5155	(MI.getOperand(`2`).getReg() == RISCV::X0) &&
5156	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5157	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5158	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5159	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg())) {
5160	// c.mv $rs1, $rs2
5161	// Operand: rs1
5162	// Operand: rs2
5163	return true;
5164	} // if
5165	break;
5166	} // case ADD
5167	case RISCV::ADDI: {
5168	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5169	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5170	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5171	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5172	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
5173	MI.getOperand(`2`).isImm() &&
5174	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `1` / simm6nonzero /) &&
5175	MI.getOperand(`2`).isImm() &&
5176	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5177	// c.addi $rd, $imm
5178	// Operand: rd_wb
5179	// Operand: rd
5180	// Operand: imm
5181	return true;
5182	} // if
5183	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5184	MI.getOperand(`0`).isReg() &&
5185	(MI.getOperand(`0`).getReg() == RISCV::X2) &&
5186	MI.getOperand(`1`).isReg() &&
5187	(MI.getOperand(`1`).getReg() == RISCV::X2) &&
5188	MI.getOperand(`2`).isImm() &&
5189	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `3` / simm10_lsb0000nonzero /)) {
5190	// c.addi16sp $rd, $imm
5191	// Operand: rd_wb
5192	// Operand: rd
5193	// Operand: imm
5194	return true;
5195	} // if
5196	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5197	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5198	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5199	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5200	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5201	MI.getOperand(`2`).isImm() &&
5202	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `4` / uimm10_lsb00nonzero /)) {
5203	// c.addi4spn $rd, $rs1, $imm
5204	// Operand: rd
5205	// Operand: rs1
5206	// Operand: imm
5207	return true;
5208	} // if
5209	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5210	MI.getOperand(`1`).isReg() &&
5211	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5212	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5213	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5214	MI.getOperand(`2`).isImm() &&
5215	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5216	// c.li $rd, $imm
5217	// Operand: rd
5218	// Operand: imm
5219	return true;
5220	} // if
5221	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5222	MI.getOperand(`2`).isImm() &&
5223	(MI.getOperand(`2`).getImm() == `0`) &&
5224	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5225	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5226	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5227	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg())) {
5228	// c.mv $rs1, $rs2
5229	// Operand: rs1
5230	// Operand: rs2
5231	return true;
5232	} // if
5233	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5234	MI.getOperand(`0`).isReg() &&
5235	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5236	MI.getOperand(`1`).isReg() &&
5237	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5238	MI.getOperand(`2`).isImm() &&
5239	(MI.getOperand(`2`).getImm() == `0`)) {
5240	// c.nop
5241	return true;
5242	} // if
5243	break;
5244	} // case ADDI
5245	case RISCV::ADDIW: {
5246	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5247	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5248	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5249	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5250	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5251	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
5252	MI.getOperand(`2`).isImm() &&
5253	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5254	// c.addiw $rd, $imm
5255	// Operand: rd_wb
5256	// Operand: rd
5257	// Operand: imm
5258	return true;
5259	} // if
5260	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5261	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5262	MI.getOperand(`1`).isReg() &&
5263	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5264	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5265	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5266	MI.getOperand(`2`).isImm() &&
5267	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5268	// c.li $rd, $imm
5269	// Operand: rd
5270	// Operand: imm
5271	return true;
5272	} // if
5273	break;
5274	} // case ADDIW
5275	case RISCV::ADDW: {
5276	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5277	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5278	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5279	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5280	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5281	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5282	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5283	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg())) {
5284	// c.addw $rd, $rs2
5285	// Operand: rd_wb
5286	// Operand: rd
5287	// Operand: rs2
5288	return true;
5289	} // if
5290	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5291	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5292	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5293	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5294	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5295	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
5296	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5297	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
5298	// c.addw $rd, $rs2
5299	// Operand: rd_wb
5300	// Operand: rd
5301	// Operand: rs2
5302	return true;
5303	} // if
5304	break;
5305	} // case ADDW
5306	case RISCV::ADD_UW: {
5307	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5308	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
5309	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5310	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5311	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5312	MI.getOperand(`2`).isReg() &&
5313	(MI.getOperand(`2`).getReg() == RISCV::X0) &&
5314	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5315	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
5316	// c.zext.w $rd
5317	// Operand: rd_wb
5318	// Operand: rd
5319	return true;
5320	} // if
5321	break;
5322	} // case ADD_UW
5323	case RISCV::AND: {
5324	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5325	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5326	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5327	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5328	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5329	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5330	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg())) {
5331	// c.and $rd, $rs2
5332	// Operand: rd_wb
5333	// Operand: rd
5334	// Operand: rs2
5335	return true;
5336	} // if
5337	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5338	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5339	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5340	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5341	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
5342	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5343	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
5344	// c.and $rd, $rs2
5345	// Operand: rd_wb
5346	// Operand: rd
5347	// Operand: rs2
5348	return true;
5349	} // if
5350	break;
5351	} // case AND
5352	case RISCV::ANDI: {
5353	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5354	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5355	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5356	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5357	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5358	MI.getOperand(`2`).isImm() &&
5359	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5360	// c.andi $rs1, $imm
5361	// Operand: rd
5362	// Operand: rs1
5363	// Operand: imm
5364	return true;
5365	} // if
5366	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5367	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5368	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5369	MI.getOperand(`2`).isImm() &&
5370	(MI.getOperand(`2`).getImm() == `255`) &&
5371	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5372	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
5373	// c.zext.b $rd
5374	// Operand: rd_wb
5375	// Operand: rd
5376	return true;
5377	} // if
5378	break;
5379	} // case ANDI
5380	case RISCV::BEQ: {
5381	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5382	MI.getOperand(`1`).isReg() &&
5383	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5384	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5385	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5386	MI.getOperand(`2`).isImm() &&
5387	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5` / bare_simm9_lsb0 /)) {
5388	// c.beqz $rs1, $imm
5389	// Operand: rs1
5390	// Operand: imm
5391	return true;
5392	} // if
5393	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5394	MI.getOperand(`0`).isReg() &&
5395	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5396	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5397	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5398	MI.getOperand(`2`).isImm() &&
5399	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5` / bare_simm9_lsb0 /)) {
5400	// c.beqz $rs1, $imm
5401	// Operand: rs1
5402	// Operand: imm
5403	return true;
5404	} // if
5405	break;
5406	} // case BEQ
5407	case RISCV::BEXTI: {
5408	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
5409	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
5410	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5411	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5412	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5413	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5414	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5415	MI.getOperand(`2`).isImm() &&
5416	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /)) {
5417	// qc.c.bexti $rs1, $shamt
5418	// Operand: rd
5419	// Operand: rs1
5420	// Operand: shamt
5421	return true;
5422	} // if
5423	break;
5424	} // case BEXTI
5425	case RISCV::BNE: {
5426	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5427	MI.getOperand(`1`).isReg() &&
5428	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5429	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5430	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5431	MI.getOperand(`2`).isImm() &&
5432	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5` / bare_simm9_lsb0 /)) {
5433	// c.bnez $rs1, $imm
5434	// Operand: rs1
5435	// Operand: imm
5436	return true;
5437	} // if
5438	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5439	MI.getOperand(`0`).isReg() &&
5440	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5441	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5442	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5443	MI.getOperand(`2`).isImm() &&
5444	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5` / bare_simm9_lsb0 /)) {
5445	// c.bnez $rs1, $imm
5446	// Operand: rs1
5447	// Operand: imm
5448	return true;
5449	} // if
5450	break;
5451	} // case BNE
5452	case RISCV::BSETI: {
5453	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
5454	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
5455	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5456	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5457	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5458	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5459	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5460	MI.getOperand(`2`).isImm() &&
5461	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /)) {
5462	// qc.c.bseti $rs1, $shamt
5463	// Operand: rd
5464	// Operand: rs1
5465	// Operand: shamt
5466	return true;
5467	} // if
5468	break;
5469	} // case BSETI
5470	case RISCV::EBREAK: {
5471	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) {
5472	// c.ebreak
5473	return true;
5474	} // if
5475	break;
5476	} // case EBREAK
5477	case RISCV::FLD: {
5478	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
5479	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5480	getRISCVMCRegisterClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5481	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5482	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5483	MI.getOperand(`2`).isImm() &&
5484	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /) &&
5485	MI.getOperand(`2`).isImm() &&
5486	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm8_lsb000_optional /)) {
5487	// c.fld $rd, ${imm}(${rs1})
5488	// Operand: rd
5489	// Operand: rs1
5490	// Operand: imm
5491	return true;
5492	} // if
5493	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
5494	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5495	getRISCVMCRegisterClass(RISCV::FPR64RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5496	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5497	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5498	MI.getOperand(`2`).isImm() &&
5499	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm9_lsb000 /) &&
5500	MI.getOperand(`2`).isImm() &&
5501	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm9_lsb000_optional /)) {
5502	// c.fldsp $rd, ${imm}(${rs1})
5503	// Operand: rd
5504	// Operand: rs1
5505	// Operand: imm
5506	return true;
5507	} // if
5508	break;
5509	} // case FLD
5510	case RISCV::FLW: {
5511	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
5512	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5513	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5514	getRISCVMCRegisterClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5515	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5516	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5517	MI.getOperand(`2`).isImm() &&
5518	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `11` / uimm7_lsb00 /) &&
5519	MI.getOperand(`2`).isImm() &&
5520	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm7_lsb00_optional /)) {
5521	// c.flw $rd, ${imm}(${rs1})
5522	// Operand: rd
5523	// Operand: rs1
5524	// Operand: imm
5525	return true;
5526	} // if
5527	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
5528	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5529	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5530	getRISCVMCRegisterClass(RISCV::FPR32RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5531	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5532	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5533	MI.getOperand(`2`).isImm() &&
5534	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm8_lsb00 /) &&
5535	MI.getOperand(`2`).isImm() &&
5536	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm8_lsb00_optional /)) {
5537	// c.flwsp $rd, ${imm}(${rs1})
5538	// Operand: rd
5539	// Operand: rs1
5540	// Operand: imm
5541	return true;
5542	} // if
5543	break;
5544	} // case FLW
5545	case RISCV::FSD: {
5546	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
5547	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5548	getRISCVMCRegisterClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5549	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5550	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5551	MI.getOperand(`2`).isImm() &&
5552	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /) &&
5553	MI.getOperand(`2`).isImm() &&
5554	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm8_lsb000_optional /)) {
5555	// c.fsd $rs2, ${imm}(${rs1})
5556	// Operand: rs2
5557	// Operand: rs1
5558	// Operand: imm
5559	return true;
5560	} // if
5561	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] &&
5562	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5563	getRISCVMCRegisterClass(RISCV::FPR64RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5564	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5565	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5566	MI.getOperand(`2`).isImm() &&
5567	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm9_lsb000 /) &&
5568	MI.getOperand(`2`).isImm() &&
5569	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm9_lsb000_optional /)) {
5570	// c.fsdsp $rs2, ${imm}(${rs1})
5571	// Operand: rs2
5572	// Operand: rs1
5573	// Operand: imm
5574	return true;
5575	} // if
5576	break;
5577	} // case FSD
5578	case RISCV::FSW: {
5579	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
5580	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5581	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5582	getRISCVMCRegisterClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5583	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5584	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5585	MI.getOperand(`2`).isImm() &&
5586	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `11` / uimm7_lsb00 /) &&
5587	MI.getOperand(`2`).isImm() &&
5588	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm7_lsb00_optional /)) {
5589	// c.fsw $rs2, ${imm}(${rs1})
5590	// Operand: rs2
5591	// Operand: rs1
5592	// Operand: imm
5593	return true;
5594	} // if
5595	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] &&
5596	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5597	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5598	getRISCVMCRegisterClass(RISCV::FPR32RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5599	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5600	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5601	MI.getOperand(`2`).isImm() &&
5602	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm8_lsb00 /) &&
5603	MI.getOperand(`2`).isImm() &&
5604	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm8_lsb00_optional /)) {
5605	// c.fswsp $rs2, ${imm}(${rs1})
5606	// Operand: rs2
5607	// Operand: rs1
5608	// Operand: imm
5609	return true;
5610	} // if
5611	break;
5612	} // case FSW
5613	case RISCV::JAL: {
5614	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5615	MI.getOperand(`0`).isReg() &&
5616	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5617	MI.getOperand(`1`).isImm() &&
5618	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `15` / bare_simm12_lsb0 /)) {
5619	// c.j $offset
5620	// Operand: offset
5621	return true;
5622	} // if
5623	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5624	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5625	MI.getOperand(`0`).isReg() &&
5626	(MI.getOperand(`0`).getReg() == RISCV::X1) &&
5627	MI.getOperand(`1`).isImm() &&
5628	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `15` / bare_simm12_lsb0 /)) {
5629	// c.jal $offset
5630	// Operand: offset
5631	return true;
5632	} // if
5633	break;
5634	} // case JAL
5635	case RISCV::JALR: {
5636	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5637	MI.getOperand(`0`).isReg() &&
5638	(MI.getOperand(`0`).getReg() == RISCV::X1) &&
5639	MI.getOperand(`2`).isImm() &&
5640	(MI.getOperand(`2`).getImm() == `0`) &&
5641	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5642	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg())) {
5643	// c.jalr $rs1
5644	// Operand: rs1
5645	return true;
5646	} // if
5647	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5648	MI.getOperand(`0`).isReg() &&
5649	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5650	MI.getOperand(`2`).isImm() &&
5651	(MI.getOperand(`2`).getImm() == `0`) &&
5652	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5653	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg())) {
5654	// c.jr $rs1
5655	// Operand: rs1
5656	return true;
5657	} // if
5658	break;
5659	} // case JALR
5660	case RISCV::LBU: {
5661	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5662	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5663	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5664	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5665	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5666	MI.getOperand(`2`).isImm() &&
5667	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `16` / uimm2 /) &&
5668	MI.getOperand(`2`).isImm() &&
5669	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `17` / uimm2_optional /)) {
5670	// c.lbu $rd, ${imm}(${rs1})
5671	// Operand: rd
5672	// Operand: rs1
5673	// Operand: imm
5674	return true;
5675	} // if
5676	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5677	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5678	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5679	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5680	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5681	MI.getOperand(`2`).isImm() &&
5682	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `18` / uimm5 /) &&
5683	MI.getOperand(`2`).isImm() &&
5684	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `19` / uimm5_optional /)) {
5685	// qk.c.lbu $rd, ${imm}(${rs1})
5686	// Operand: rd
5687	// Operand: rs1
5688	// Operand: imm
5689	return true;
5690	} // if
5691	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5692	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5693	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5694	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5695	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5696	MI.getOperand(`2`).isImm() &&
5697	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / uimm4 /) &&
5698	MI.getOperand(`2`).isImm() &&
5699	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `21` / uimm4_optional /)) {
5700	// qk.c.lbusp $rd_rs2, ${imm}(${rs1})
5701	// Operand: rd_rs2
5702	// Operand: rs1
5703	// Operand: imm
5704	return true;
5705	} // if
5706	break;
5707	} // case LBU
5708	case RISCV::LD: {
5709	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5710	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5711	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5712	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5713	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5714	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5715	MI.getOperand(`2`).isImm() &&
5716	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /) &&
5717	MI.getOperand(`2`).isImm() &&
5718	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm8_lsb000_optional /)) {
5719	// c.ld $rd, ${imm}(${rs1})
5720	// Operand: rd
5721	// Operand: rs1
5722	// Operand: imm
5723	return true;
5724	} // if
5725	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5726	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5727	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5728	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5729	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5730	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5731	MI.getOperand(`2`).isImm() &&
5732	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm9_lsb000 /) &&
5733	MI.getOperand(`2`).isImm() &&
5734	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm9_lsb000_optional /)) {
5735	// c.ldsp $rd, ${imm}(${rs1})
5736	// Operand: rd
5737	// Operand: rs1
5738	// Operand: imm
5739	return true;
5740	} // if
5741	break;
5742	} // case LD
5743	case RISCV::LD_RV32: {
5744	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
5745	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5746	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5747	getRISCVMCRegisterClass(RISCV::GPRPairNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5748	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5749	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5750	MI.getOperand(`2`).isImm() &&
5751	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm9_lsb000 /) &&
5752	MI.getOperand(`2`).isImm() &&
5753	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm9_lsb000_optional /)) {
5754	// c.ldsp $rd, ${imm}(${rs1})
5755	// Operand: rd
5756	// Operand: rs1
5757	// Operand: imm
5758	return true;
5759	} // if
5760	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
5761	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5762	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5763	getRISCVMCRegisterClass(RISCV::GPRPairCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5764	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5765	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5766	MI.getOperand(`2`).isImm() &&
5767	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /) &&
5768	MI.getOperand(`2`).isImm() &&
5769	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm8_lsb000_optional /)) {
5770	// c.ld $rd, ${imm}(${rs1})
5771	// Operand: rd
5772	// Operand: rs1
5773	// Operand: imm
5774	return true;
5775	} // if
5776	break;
5777	} // case LD_RV32
5778	case RISCV::LH: {
5779	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5780	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5781	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5782	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5783	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5784	MI.getOperand(`2`).isImm() &&
5785	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / uimm2_lsb0 /) &&
5786	MI.getOperand(`2`).isImm() &&
5787	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `23` / uimm2_lsb0_optional /)) {
5788	// c.lh $rd, ${imm}(${rs1})
5789	// Operand: rd
5790	// Operand: rs1
5791	// Operand: imm
5792	return true;
5793	} // if
5794	break;
5795	} // case LH
5796	case RISCV::LHU: {
5797	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5798	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5799	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5800	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5801	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5802	MI.getOperand(`2`).isImm() &&
5803	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / uimm2_lsb0 /) &&
5804	MI.getOperand(`2`).isImm() &&
5805	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `23` / uimm2_lsb0_optional /)) {
5806	// c.lhu $rd, ${imm}(${rs1})
5807	// Operand: rd
5808	// Operand: rs1
5809	// Operand: imm
5810	return true;
5811	} // if
5812	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5813	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5814	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5815	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5816	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5817	MI.getOperand(`2`).isImm() &&
5818	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24` / uimm6_lsb0 /) &&
5819	MI.getOperand(`2`).isImm() &&
5820	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `25` / uimm6_lsb0_optional /)) {
5821	// qk.c.lhu $rd, ${imm}(${rs1})
5822	// Operand: rd
5823	// Operand: rs1
5824	// Operand: imm
5825	return true;
5826	} // if
5827	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5828	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5829	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5830	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5831	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5832	MI.getOperand(`2`).isImm() &&
5833	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `26` / uimm5_lsb0 /) &&
5834	MI.getOperand(`2`).isImm() &&
5835	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `27` / uimm5_lsb0_optional /)) {
5836	// qk.c.lhusp $rd_rs2, ${imm}(${rs1})
5837	// Operand: rd_rs2
5838	// Operand: rs1
5839	// Operand: imm
5840	return true;
5841	} // if
5842	break;
5843	} // case LHU
5844	case RISCV::LH_INX: {
5845	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5846	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5847	getRISCVMCRegisterClass(RISCV::GPRF16CRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5848	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5849	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5850	MI.getOperand(`2`).isImm() &&
5851	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / uimm2_lsb0 /) &&
5852	MI.getOperand(`2`).isImm() &&
5853	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `23` / uimm2_lsb0_optional /)) {
5854	// c.lh $rd, ${imm}(${rs1})
5855	// Operand: rd
5856	// Operand: rs1
5857	// Operand: imm
5858	return true;
5859	} // if
5860	break;
5861	} // case LH_INX
5862	case RISCV::LUI: {
5863	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5864	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5865	getRISCVMCRegisterClass(RISCV::GPRNoX0X2RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5866	MI.getOperand(`1`).isImm() &&
5867	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `28` / c_lui_imm /)) {
5868	// c.lui $rd, $imm
5869	// Operand: rd
5870	// Operand: imm
5871	return true;
5872	} // if
5873	break;
5874	} // case LUI
5875	case RISCV::LW: {
5876	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5877	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5878	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5879	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5880	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5881	MI.getOperand(`2`).isImm() &&
5882	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `11` / uimm7_lsb00 /) &&
5883	MI.getOperand(`2`).isImm() &&
5884	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm7_lsb00_optional /)) {
5885	// c.lw $rd, ${imm}(${rs1})
5886	// Operand: rd
5887	// Operand: rs1
5888	// Operand: imm
5889	return true;
5890	} // if
5891	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5892	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5893	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5894	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5895	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5896	MI.getOperand(`2`).isImm() &&
5897	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm8_lsb00 /) &&
5898	MI.getOperand(`2`).isImm() &&
5899	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm8_lsb00_optional /)) {
5900	// c.lwsp $rd, ${imm}(${rs1})
5901	// Operand: rd
5902	// Operand: rs1
5903	// Operand: imm
5904	return true;
5905	} // if
5906	break;
5907	} // case LW
5908	case RISCV::LW_INX: {
5909	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5910	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5911	getRISCVMCRegisterClass(RISCV::GPRF32NoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
5912	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5913	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5914	MI.getOperand(`2`).isImm() &&
5915	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm8_lsb00 /) &&
5916	MI.getOperand(`2`).isImm() &&
5917	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm8_lsb00_optional /)) {
5918	// c.lwsp $rd, ${imm}(${rs1})
5919	// Operand: rd
5920	// Operand: rs1
5921	// Operand: imm
5922	return true;
5923	} // if
5924	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5925	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5926	getRISCVMCRegisterClass(RISCV::GPRF32CRegClassID).contains(MI.getOperand(`0`).getReg()) &&
5927	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5928	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5929	MI.getOperand(`2`).isImm() &&
5930	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `11` / uimm7_lsb00 /) &&
5931	MI.getOperand(`2`).isImm() &&
5932	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm7_lsb00_optional /)) {
5933	// c.lw $rd, ${imm}(${rs1})
5934	// Operand: rd
5935	// Operand: rs1
5936	// Operand: imm
5937	return true;
5938	} // if
5939	break;
5940	} // case LW_INX
5941	case RISCV::MUL: {
5942	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5943	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
5944	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5945	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5946	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5947	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5948	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5949	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg())) {
5950	// c.mul $rd, $rs2
5951	// Operand: rd_wb
5952	// Operand: rd
5953	// Operand: rs2
5954	return true;
5955	} // if
5956	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5957	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
5958	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5959	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5960	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5961	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
5962	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5963	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
5964	// c.mul $rd, $rs2
5965	// Operand: rd_wb
5966	// Operand: rd
5967	// Operand: rs2
5968	return true;
5969	} // if
5970	break;
5971	} // case MUL
5972	case RISCV::OR: {
5973	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5974	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5975	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5976	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5977	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
5978	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5979	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg())) {
5980	// c.or $rd, $rs2
5981	// Operand: rd_wb
5982	// Operand: rd
5983	// Operand: rs2
5984	return true;
5985	} // if
5986	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
5987	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5988	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5989	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5990	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
5991	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5992	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
5993	// c.or $rd, $rs2
5994	// Operand: rd_wb
5995	// Operand: rd
5996	// Operand: rs2
5997	return true;
5998	} // if
5999	break;
6000	} // case OR
6001	case RISCV::QC_EXTU: {
6002	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
6003	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
6004	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6005	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6006	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6007	MI.getOperand(`2`).isImm() &&
6008	(MI.getOperand(`2`).getImm() == `1`) &&
6009	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6010	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6011	MI.getOperand(`3`).isImm() &&
6012	RISCVValidateMachineOperand(MI.getOperand(`3`), &STI, `6` / uimmlog2xlennonzero /)) {
6013	// qc.c.bexti $rs1, $shamt
6014	// Operand: rd
6015	// Operand: rs1
6016	// Operand: shamt
6017	return true;
6018	} // if
6019	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
6020	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6021	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6022	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6023	MI.getOperand(`3`).isImm() &&
6024	(MI.getOperand(`3`).getImm() == `0`) &&
6025	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6026	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
6027	MI.getOperand(`2`).isImm() &&
6028	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `29` / uimm5ge6_plus1 /)) {
6029	// qc.c.extu $rd, $width
6030	// Operand: rd_wb
6031	// Operand: rd
6032	// Operand: width
6033	return true;
6034	} // if
6035	break;
6036	} // case QC_EXTU
6037	case RISCV::QC_E_ADDAI: {
6038	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6039	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6040	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6041	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6042	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6043	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6044	MI.getOperand(`2`).isImm() &&
6045	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /)) {
6046	// addi $rd, $rs1, $imm12
6047	// Operand: rd
6048	// Operand: rs1
6049	// Operand: imm12
6050	return true;
6051	} // if
6052	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6053	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6054	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6055	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6056	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6057	MI.getOperand(`2`).isImm() &&
6058	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `1` / simm6nonzero /) &&
6059	MI.getOperand(`2`).isImm() &&
6060	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
6061	// c.addi $rd, $imm
6062	// Operand: rd_wb
6063	// Operand: rd
6064	// Operand: imm
6065	return true;
6066	} // if
6067	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6068	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6069	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6070	MI.getOperand(`0`).isReg() &&
6071	(MI.getOperand(`0`).getReg() == RISCV::X2) &&
6072	MI.getOperand(`1`).isReg() &&
6073	(MI.getOperand(`1`).getReg() == RISCV::X2) &&
6074	MI.getOperand(`2`).isImm() &&
6075	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `3` / simm10_lsb0000nonzero /)) {
6076	// c.addi16sp $rd, $imm
6077	// Operand: rd_wb
6078	// Operand: rd
6079	// Operand: imm
6080	return true;
6081	} // if
6082	break;
6083	} // case QC_E_ADDAI
6084	case RISCV::QC_E_ADDI: {
6085	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6086	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6087	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6088	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6089	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6090	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
6091	MI.getOperand(`2`).isImm() &&
6092	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /)) {
6093	// addi $rd, $rs1, $imm12
6094	// Operand: rd
6095	// Operand: rs1
6096	// Operand: imm12
6097	return true;
6098	} // if
6099	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6100	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6101	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6102	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6103	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6104	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6105	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
6106	MI.getOperand(`2`).isImm() &&
6107	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `1` / simm6nonzero /) &&
6108	MI.getOperand(`2`).isImm() &&
6109	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
6110	// c.addi $rd, $imm
6111	// Operand: rd_wb
6112	// Operand: rd
6113	// Operand: imm
6114	return true;
6115	} // if
6116	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6117	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6118	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6119	MI.getOperand(`0`).isReg() &&
6120	(MI.getOperand(`0`).getReg() == RISCV::X2) &&
6121	MI.getOperand(`1`).isReg() &&
6122	(MI.getOperand(`1`).getReg() == RISCV::X2) &&
6123	MI.getOperand(`2`).isImm() &&
6124	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `3` / simm10_lsb0000nonzero /)) {
6125	// c.addi16sp $rd, $imm
6126	// Operand: rd_wb
6127	// Operand: rd
6128	// Operand: imm
6129	return true;
6130	} // if
6131	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6132	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6133	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6134	MI.getOperand(`2`).isImm() &&
6135	(MI.getOperand(`2`).getImm() == `0`) &&
6136	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6137	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6138	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6139	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg())) {
6140	// c.mv $rs1, $rs2
6141	// Operand: rs1
6142	// Operand: rs2
6143	return true;
6144	} // if
6145	break;
6146	} // case QC_E_ADDI
6147	case RISCV::QC_E_ANDAI: {
6148	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6149	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6150	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6151	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6152	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6153	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6154	MI.getOperand(`2`).isImm() &&
6155	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /)) {
6156	// andi $rd, $rs1, $imm12
6157	// Operand: rd
6158	// Operand: rs1
6159	// Operand: imm12
6160	return true;
6161	} // if
6162	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6163	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6164	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6165	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6166	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6167	MI.getOperand(`2`).isImm() &&
6168	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
6169	// c.andi $rs1, $imm
6170	// Operand: rd
6171	// Operand: rs1
6172	// Operand: imm
6173	return true;
6174	} // if
6175	break;
6176	} // case QC_E_ANDAI
6177	case RISCV::QC_E_ANDI: {
6178	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6179	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6180	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6181	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6182	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6183	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
6184	MI.getOperand(`2`).isImm() &&
6185	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /)) {
6186	// andi $rd, $rs1, $imm12
6187	// Operand: rd
6188	// Operand: rs1
6189	// Operand: imm12
6190	return true;
6191	} // if
6192	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6193	STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6194	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6195	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6196	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6197	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6198	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6199	MI.getOperand(`2`).isImm() &&
6200	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
6201	// c.andi $rs1, $imm
6202	// Operand: rd
6203	// Operand: rs1
6204	// Operand: imm
6205	return true;
6206	} // if
6207	break;
6208	} // case QC_E_ANDI
6209	case RISCV::QC_E_BEQI: {
6210	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6211	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6212	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6213	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6214	MI.getOperand(`1`).isImm() &&
6215	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `31` / simm5nonzero /) &&
6216	MI.getOperand(`2`).isImm() &&
6217	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `32` / bare_simm13_lsb0 /)) {
6218	// qc.beqi $rs1, $rs2, $imm12
6219	// Operand: rs1
6220	// Operand: rs2
6221	// Operand: imm12
6222	return true;
6223	} // if
6224	break;
6225	} // case QC_E_BEQI
6226	case RISCV::QC_E_BGEI: {
6227	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6228	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6229	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6230	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6231	MI.getOperand(`1`).isImm() &&
6232	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `31` / simm5nonzero /) &&
6233	MI.getOperand(`2`).isImm() &&
6234	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `32` / bare_simm13_lsb0 /)) {
6235	// qc.bgei $rs1, $rs2, $imm12
6236	// Operand: rs1
6237	// Operand: rs2
6238	// Operand: imm12
6239	return true;
6240	} // if
6241	break;
6242	} // case QC_E_BGEI
6243	case RISCV::QC_E_BGEUI: {
6244	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6245	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6246	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6247	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6248	MI.getOperand(`1`).isImm() &&
6249	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `33` / uimm5nonzero /) &&
6250	MI.getOperand(`2`).isImm() &&
6251	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `32` / bare_simm13_lsb0 /)) {
6252	// qc.bgeui $rs1, $rs2, $imm12
6253	// Operand: rs1
6254	// Operand: rs2
6255	// Operand: imm12
6256	return true;
6257	} // if
6258	break;
6259	} // case QC_E_BGEUI
6260	case RISCV::QC_E_BLTI: {
6261	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6262	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6263	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6264	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6265	MI.getOperand(`1`).isImm() &&
6266	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `31` / simm5nonzero /) &&
6267	MI.getOperand(`2`).isImm() &&
6268	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `32` / bare_simm13_lsb0 /)) {
6269	// qc.blti $rs1, $rs2, $imm12
6270	// Operand: rs1
6271	// Operand: rs2
6272	// Operand: imm12
6273	return true;
6274	} // if
6275	break;
6276	} // case QC_E_BLTI
6277	case RISCV::QC_E_BLTUI: {
6278	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6279	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6280	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6281	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6282	MI.getOperand(`1`).isImm() &&
6283	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `33` / uimm5nonzero /) &&
6284	MI.getOperand(`2`).isImm() &&
6285	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `32` / bare_simm13_lsb0 /)) {
6286	// qc.bltui $rs1, $rs2, $imm12
6287	// Operand: rs1
6288	// Operand: rs2
6289	// Operand: imm12
6290	return true;
6291	} // if
6292	break;
6293	} // case QC_E_BLTUI
6294	case RISCV::QC_E_BNEI: {
6295	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6296	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6297	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6298	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6299	MI.getOperand(`1`).isImm() &&
6300	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `31` / simm5nonzero /) &&
6301	MI.getOperand(`2`).isImm() &&
6302	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `32` / bare_simm13_lsb0 /)) {
6303	// qc.bnei $rs1, $rs2, $imm12
6304	// Operand: rs1
6305	// Operand: rs2
6306	// Operand: imm12
6307	return true;
6308	} // if
6309	break;
6310	} // case QC_E_BNEI
6311	case RISCV::QC_E_J: {
6312	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6313	STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
6314	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6315	MI.getOperand(`0`).isImm() &&
6316	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `15` / bare_simm12_lsb0 /)) {
6317	// c.j $offset
6318	// Operand: offset
6319	return true;
6320	} // if
6321	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
6322	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6323	MI.getOperand(`0`).isImm() &&
6324	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `34` / simm21_lsb0_jal /)) {
6325	// jal $rd, $imm20
6326	// Operand: rd
6327	// Operand: imm20
6328	return true;
6329	} // if
6330	break;
6331	} // case QC_E_J
6332	case RISCV::QC_E_JAL: {
6333	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6334	STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
6335	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6336	MI.getOperand(`0`).isImm() &&
6337	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `15` / bare_simm12_lsb0 /)) {
6338	// c.jal $offset
6339	// Operand: offset
6340	return true;
6341	} // if
6342	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
6343	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6344	MI.getOperand(`0`).isImm() &&
6345	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `34` / simm21_lsb0_jal /)) {
6346	// jal $rd, $imm20
6347	// Operand: rd
6348	// Operand: imm20
6349	return true;
6350	} // if
6351	break;
6352	} // case QC_E_JAL
6353	case RISCV::QC_E_LB: {
6354	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6355	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6356	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6357	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6358	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6359	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6360	MI.getOperand(`2`).isImm() &&
6361	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /) &&
6362	MI.getOperand(`2`).isImm() &&
6363	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `35` / simm12_lo_optional /)) {
6364	// lb $rd, ${imm12}(${rs1})
6365	// Operand: rd
6366	// Operand: rs1
6367	// Operand: imm12
6368	return true;
6369	} // if
6370	break;
6371	} // case QC_E_LB
6372	case RISCV::QC_E_LBU: {
6373	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6374	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6375	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6376	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6377	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6378	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6379	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6380	MI.getOperand(`2`).isImm() &&
6381	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `16` / uimm2 /) &&
6382	MI.getOperand(`2`).isImm() &&
6383	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `17` / uimm2_optional /)) {
6384	// c.lbu $rd, ${imm}(${rs1})
6385	// Operand: rd
6386	// Operand: rs1
6387	// Operand: imm
6388	return true;
6389	} // if
6390	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6391	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6392	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6393	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6394	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6395	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6396	MI.getOperand(`2`).isImm() &&
6397	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /) &&
6398	MI.getOperand(`2`).isImm() &&
6399	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `35` / simm12_lo_optional /)) {
6400	// lbu $rd, ${imm12}(${rs1})
6401	// Operand: rd
6402	// Operand: rs1
6403	// Operand: imm12
6404	return true;
6405	} // if
6406	break;
6407	} // case QC_E_LBU
6408	case RISCV::QC_E_LH: {
6409	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6410	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6411	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6412	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6413	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6414	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6415	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6416	MI.getOperand(`2`).isImm() &&
6417	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / uimm2_lsb0 /) &&
6418	MI.getOperand(`2`).isImm() &&
6419	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `23` / uimm2_lsb0_optional /)) {
6420	// c.lh $rd, ${imm}(${rs1})
6421	// Operand: rd
6422	// Operand: rs1
6423	// Operand: imm
6424	return true;
6425	} // if
6426	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6427	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6428	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6429	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6430	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6431	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6432	MI.getOperand(`2`).isImm() &&
6433	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /) &&
6434	MI.getOperand(`2`).isImm() &&
6435	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `35` / simm12_lo_optional /)) {
6436	// lh $rd, ${imm12}(${rs1})
6437	// Operand: rd
6438	// Operand: rs1
6439	// Operand: imm12
6440	return true;
6441	} // if
6442	break;
6443	} // case QC_E_LH
6444	case RISCV::QC_E_LHU: {
6445	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6446	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6447	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6448	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6449	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6450	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6451	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6452	MI.getOperand(`2`).isImm() &&
6453	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / uimm2_lsb0 /) &&
6454	MI.getOperand(`2`).isImm() &&
6455	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `23` / uimm2_lsb0_optional /)) {
6456	// c.lhu $rd, ${imm}(${rs1})
6457	// Operand: rd
6458	// Operand: rs1
6459	// Operand: imm
6460	return true;
6461	} // if
6462	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6463	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6464	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6465	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6466	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6467	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6468	MI.getOperand(`2`).isImm() &&
6469	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /) &&
6470	MI.getOperand(`2`).isImm() &&
6471	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `35` / simm12_lo_optional /)) {
6472	// lhu $rd, ${imm12}(${rs1})
6473	// Operand: rd
6474	// Operand: rs1
6475	// Operand: imm12
6476	return true;
6477	} // if
6478	break;
6479	} // case QC_E_LHU
6480	case RISCV::QC_E_LI: {
6481	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6482	STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
6483	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6484	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6485	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6486	MI.getOperand(`1`).isImm() &&
6487	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `2` / simm6 /)) {
6488	// c.li $rd, $imm
6489	// Operand: rd
6490	// Operand: imm
6491	return true;
6492	} // if
6493	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
6494	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6495	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6496	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6497	MI.getOperand(`1`).isImm() &&
6498	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `36` / simm20_li /)) {
6499	// qc.li $rd, $imm20
6500	// Operand: rd
6501	// Operand: imm20
6502	return true;
6503	} // if
6504	break;
6505	} // case QC_E_LI
6506	case RISCV::QC_E_LW: {
6507	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6508	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6509	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6510	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6511	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6512	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6513	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6514	MI.getOperand(`2`).isImm() &&
6515	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `11` / uimm7_lsb00 /) &&
6516	MI.getOperand(`2`).isImm() &&
6517	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm7_lsb00_optional /)) {
6518	// c.lw $rd, ${imm}(${rs1})
6519	// Operand: rd
6520	// Operand: rs1
6521	// Operand: imm
6522	return true;
6523	} // if
6524	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6525	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6526	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6527	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6528	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6529	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6530	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6531	MI.getOperand(`2`).isImm() &&
6532	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm8_lsb00 /) &&
6533	MI.getOperand(`2`).isImm() &&
6534	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm8_lsb00_optional /)) {
6535	// c.lwsp $rd, ${imm}(${rs1})
6536	// Operand: rd
6537	// Operand: rs1
6538	// Operand: imm
6539	return true;
6540	} // if
6541	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6542	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6543	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6544	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6545	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6546	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6547	MI.getOperand(`2`).isImm() &&
6548	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /) &&
6549	MI.getOperand(`2`).isImm() &&
6550	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `35` / simm12_lo_optional /)) {
6551	// lw $rd, ${imm12}(${rs1})
6552	// Operand: rd
6553	// Operand: rs1
6554	// Operand: imm12
6555	return true;
6556	} // if
6557	break;
6558	} // case QC_E_LW
6559	case RISCV::QC_E_ORAI: {
6560	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6561	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6562	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6563	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6564	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6565	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6566	MI.getOperand(`2`).isImm() &&
6567	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /)) {
6568	// ori $rd, $rs1, $imm12
6569	// Operand: rd
6570	// Operand: rs1
6571	// Operand: imm12
6572	return true;
6573	} // if
6574	break;
6575	} // case QC_E_ORAI
6576	case RISCV::QC_E_ORI: {
6577	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6578	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6579	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6580	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6581	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6582	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
6583	MI.getOperand(`2`).isImm() &&
6584	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /)) {
6585	// ori $rd, $rs1, $imm12
6586	// Operand: rd
6587	// Operand: rs1
6588	// Operand: imm12
6589	return true;
6590	} // if
6591	break;
6592	} // case QC_E_ORI
6593	case RISCV::QC_E_SB: {
6594	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6595	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6596	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6597	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6598	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6599	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6600	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6601	MI.getOperand(`2`).isImm() &&
6602	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `16` / uimm2 /) &&
6603	MI.getOperand(`2`).isImm() &&
6604	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `17` / uimm2_optional /)) {
6605	// c.sb $rs2, ${imm}(${rs1})
6606	// Operand: rs2
6607	// Operand: rs1
6608	// Operand: imm
6609	return true;
6610	} // if
6611	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6612	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6613	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6614	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6615	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6616	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6617	MI.getOperand(`2`).isImm() &&
6618	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /) &&
6619	MI.getOperand(`2`).isImm() &&
6620	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `35` / simm12_lo_optional /)) {
6621	// sb $rs2, ${imm12}(${rs1})
6622	// Operand: rs2
6623	// Operand: rs1
6624	// Operand: imm12
6625	return true;
6626	} // if
6627	break;
6628	} // case QC_E_SB
6629	case RISCV::QC_E_SH: {
6630	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6631	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6632	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6633	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6634	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6635	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6636	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6637	MI.getOperand(`2`).isImm() &&
6638	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / uimm2_lsb0 /) &&
6639	MI.getOperand(`2`).isImm() &&
6640	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `23` / uimm2_lsb0_optional /)) {
6641	// c.sh $rs2, ${imm}(${rs1})
6642	// Operand: rs2
6643	// Operand: rs1
6644	// Operand: imm
6645	return true;
6646	} // if
6647	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6648	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6649	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6650	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6651	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6652	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6653	MI.getOperand(`2`).isImm() &&
6654	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /) &&
6655	MI.getOperand(`2`).isImm() &&
6656	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `35` / simm12_lo_optional /)) {
6657	// sh $rs2, ${imm12}(${rs1})
6658	// Operand: rs2
6659	// Operand: rs1
6660	// Operand: imm12
6661	return true;
6662	} // if
6663	break;
6664	} // case QC_E_SH
6665	case RISCV::QC_E_SW: {
6666	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6667	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6668	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6669	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6670	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6671	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6672	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6673	MI.getOperand(`2`).isImm() &&
6674	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `11` / uimm7_lsb00 /) &&
6675	MI.getOperand(`2`).isImm() &&
6676	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm7_lsb00_optional /)) {
6677	// c.sw $rs2, ${imm}(${rs1})
6678	// Operand: rs2
6679	// Operand: rs1
6680	// Operand: imm
6681	return true;
6682	} // if
6683	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6684	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6685	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6686	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6687	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6688	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6689	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6690	MI.getOperand(`2`).isImm() &&
6691	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm8_lsb00 /) &&
6692	MI.getOperand(`2`).isImm() &&
6693	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm8_lsb00_optional /)) {
6694	// c.swsp $rs2, ${imm}(${rs1})
6695	// Operand: rs2
6696	// Operand: rs1
6697	// Operand: imm
6698	return true;
6699	} // if
6700	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6701	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6702	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6703	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6704	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6705	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6706	MI.getOperand(`2`).isImm() &&
6707	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /) &&
6708	MI.getOperand(`2`).isImm() &&
6709	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `35` / simm12_lo_optional /)) {
6710	// sw $rs2, ${imm12}(${rs1})
6711	// Operand: rs2
6712	// Operand: rs1
6713	// Operand: imm12
6714	return true;
6715	} // if
6716	break;
6717	} // case QC_E_SW
6718	case RISCV::QC_E_XORAI: {
6719	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6720	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6721	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6722	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6723	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6724	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6725	MI.getOperand(`2`).isImm() &&
6726	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /)) {
6727	// xori $rd, $rs1, $imm12
6728	// Operand: rd
6729	// Operand: rs1
6730	// Operand: imm12
6731	return true;
6732	} // if
6733	break;
6734	} // case QC_E_XORAI
6735	case RISCV::QC_E_XORI: {
6736	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6737	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6738	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6739	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6740	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6741	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
6742	MI.getOperand(`2`).isImm() &&
6743	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `30` / simm12_lo /)) {
6744	// xori $rd, $rs1, $imm12
6745	// Operand: rd
6746	// Operand: rs1
6747	// Operand: imm12
6748	return true;
6749	} // if
6750	break;
6751	} // case QC_E_XORI
6752	case RISCV::QC_LI: {
6753	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6754	STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
6755	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6756	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6757	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`0`).getReg()) &&
6758	MI.getOperand(`1`).isImm() &&
6759	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `2` / simm6 /)) {
6760	// c.li $rd, $imm
6761	// Operand: rd
6762	// Operand: imm
6763	return true;
6764	} // if
6765	break;
6766	} // case QC_LI
6767	case RISCV::QC_MULIADD: {
6768	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
6769	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6770	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6771	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6772	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6773	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
6774	MI.getOperand(`3`).isImm() &&
6775	RISCVValidateMachineOperand(MI.getOperand(`3`), &STI, `18` / uimm5 /)) {
6776	// qc.c.muliadd $rd, $rs1, $uimm
6777	// Operand: rd_wb
6778	// Operand: rd
6779	// Operand: rs1
6780	// Operand: uimm
6781	return true;
6782	} // if
6783	break;
6784	} // case QC_MULIADD
6785	case RISCV::QC_MVEQI: {
6786	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
6787	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6788	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
6789	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6790	MI.getOperand(`3`).isImm() &&
6791	(MI.getOperand(`3`).getImm() == `0`) &&
6792	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6793	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
6794	MI.getOperand(`4`).isReg() && MI.getOperand(`4`).getReg().isPhysical() &&
6795	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`4`).getReg())) {
6796	// qc.c.mveqz $rd, $rs1
6797	// Operand: rd_wb
6798	// Operand: rd
6799	// Operand: rs1
6800	return true;
6801	} // if
6802	break;
6803	} // case QC_MVEQI
6804	case RISCV::QC_MVLTUI: {
6805	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
6806	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6807	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
6808	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6809	MI.getOperand(`3`).isImm() &&
6810	(MI.getOperand(`3`).getImm() == `1`) &&
6811	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6812	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
6813	MI.getOperand(`4`).isReg() && MI.getOperand(`4`).getReg().isPhysical() &&
6814	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`4`).getReg())) {
6815	// qc.c.mveqz $rd, $rs1
6816	// Operand: rd_wb
6817	// Operand: rd
6818	// Operand: rs1
6819	return true;
6820	} // if
6821	break;
6822	} // case QC_MVLTUI
6823	case RISCV::QC_SHLADD: {
6824	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
6825	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6826	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
6827	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6828	MI.getOperand(`3`).isImm() &&
6829	(MI.getOperand(`3`).getImm() == `4`) &&
6830	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6831	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
6832	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6833	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6834	RISCVValidateMachineOperand(MachineOperand::CreateImm(`16`), &STI, `18` / uimm5 /)) {
6835	// qc.c.muliadd $rd, $rs1, $uimm
6836	// Operand: rd_wb
6837	// Operand: rd
6838	// Operand: rs1
6839	// Operand: uimm
6840	return true;
6841	} // if
6842	break;
6843	} // case QC_SHLADD
6844	case RISCV::QC_SYNC: {
6845	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
6846	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6847	MI.getOperand(`0`).isImm() &&
6848	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `37` / uimm5slist /)) {
6849	// qc.c.sync $slist
6850	// Operand: slist
6851	return true;
6852	} // if
6853	break;
6854	} // case QC_SYNC
6855	case RISCV::QC_SYNCR: {
6856	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
6857	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6858	MI.getOperand(`0`).isImm() &&
6859	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `37` / uimm5slist /)) {
6860	// qc.c.syncr $slist
6861	// Operand: slist
6862	return true;
6863	} // if
6864	break;
6865	} // case QC_SYNCR
6866	case RISCV::QC_SYNCWF: {
6867	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
6868	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6869	MI.getOperand(`0`).isImm() &&
6870	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `37` / uimm5slist /)) {
6871	// qc.c.syncwf $slist
6872	// Operand: slist
6873	return true;
6874	} // if
6875	break;
6876	} // case QC_SYNCWF
6877	case RISCV::QC_SYNCWL: {
6878	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
6879	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6880	MI.getOperand(`0`).isImm() &&
6881	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `37` / uimm5slist /)) {
6882	// qc.c.syncwl $slist
6883	// Operand: slist
6884	return true;
6885	} // if
6886	break;
6887	} // case QC_SYNCWL
6888	case RISCV::SB: {
6889	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6890	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6891	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6892	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6893	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6894	MI.getOperand(`2`).isImm() &&
6895	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `16` / uimm2 /) &&
6896	MI.getOperand(`2`).isImm() &&
6897	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `17` / uimm2_optional /)) {
6898	// c.sb $rs2, ${imm}(${rs1})
6899	// Operand: rs2
6900	// Operand: rs1
6901	// Operand: imm
6902	return true;
6903	} // if
6904	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
6905	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6906	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6907	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6908	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6909	MI.getOperand(`2`).isImm() &&
6910	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `18` / uimm5 /) &&
6911	MI.getOperand(`2`).isImm() &&
6912	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `19` / uimm5_optional /)) {
6913	// qk.c.sb $rs2, ${imm}(${rs1})
6914	// Operand: rs2
6915	// Operand: rs1
6916	// Operand: imm
6917	return true;
6918	} // if
6919	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
6920	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6921	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6922	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6923	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6924	MI.getOperand(`2`).isImm() &&
6925	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / uimm4 /) &&
6926	MI.getOperand(`2`).isImm() &&
6927	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `21` / uimm4_optional /)) {
6928	// qk.c.sbsp $rd_rs2, ${imm}(${rs1})
6929	// Operand: rd_rs2
6930	// Operand: rs1
6931	// Operand: imm
6932	return true;
6933	} // if
6934	break;
6935	} // case SB
6936	case RISCV::SD: {
6937	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
6938	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6939	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6940	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6941	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6942	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6943	MI.getOperand(`2`).isImm() &&
6944	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /) &&
6945	MI.getOperand(`2`).isImm() &&
6946	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm8_lsb000_optional /)) {
6947	// c.sd $rs2, ${imm}(${rs1})
6948	// Operand: rs2
6949	// Operand: rs1
6950	// Operand: imm
6951	return true;
6952	} // if
6953	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
6954	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
6955	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6956	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6957	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6958	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6959	MI.getOperand(`2`).isImm() &&
6960	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm9_lsb000 /) &&
6961	MI.getOperand(`2`).isImm() &&
6962	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm9_lsb000_optional /)) {
6963	// c.sdsp $rs2, ${imm}(${rs1})
6964	// Operand: rs2
6965	// Operand: rs1
6966	// Operand: imm
6967	return true;
6968	} // if
6969	break;
6970	} // case SD
6971	case RISCV::SD_RV32: {
6972	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
6973	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6974	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6975	getRISCVMCRegisterClass(RISCV::GPRPairRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6976	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6977	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6978	MI.getOperand(`2`).isImm() &&
6979	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm9_lsb000 /) &&
6980	MI.getOperand(`2`).isImm() &&
6981	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm9_lsb000_optional /)) {
6982	// c.sdsp $rs2, ${imm}(${rs1})
6983	// Operand: rs2
6984	// Operand: rs1
6985	// Operand: imm
6986	return true;
6987	} // if
6988	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
6989	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6990	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6991	getRISCVMCRegisterClass(RISCV::GPRPairCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
6992	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6993	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
6994	MI.getOperand(`2`).isImm() &&
6995	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /) &&
6996	MI.getOperand(`2`).isImm() &&
6997	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm8_lsb000_optional /)) {
6998	// c.sd $rs2, ${imm}(${rs1})
6999	// Operand: rs2
7000	// Operand: rs1
7001	// Operand: imm
7002	return true;
7003	} // if
7004	break;
7005	} // case SD_RV32
7006	case RISCV::SEXT_B: {
7007	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
7008	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7009	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7010	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7011	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7012	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
7013	// c.sext.b $rd
7014	// Operand: rd_wb
7015	// Operand: rd
7016	return true;
7017	} // if
7018	break;
7019	} // case SEXT_B
7020	case RISCV::SEXT_H: {
7021	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
7022	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7023	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7024	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7025	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7026	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
7027	// c.sext.h $rd
7028	// Operand: rd_wb
7029	// Operand: rd
7030	return true;
7031	} // if
7032	break;
7033	} // case SEXT_H
7034	case RISCV::SH: {
7035	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7036	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
7037	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
7038	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7039	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7040	MI.getOperand(`2`).isImm() &&
7041	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / uimm2_lsb0 /) &&
7042	MI.getOperand(`2`).isImm() &&
7043	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `23` / uimm2_lsb0_optional /)) {
7044	// c.sh $rs2, ${imm}(${rs1})
7045	// Operand: rs2
7046	// Operand: rs1
7047	// Operand: imm
7048	return true;
7049	} // if
7050	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
7051	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
7052	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
7053	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7054	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7055	MI.getOperand(`2`).isImm() &&
7056	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24` / uimm6_lsb0 /) &&
7057	MI.getOperand(`2`).isImm() &&
7058	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `25` / uimm6_lsb0_optional /)) {
7059	// qk.c.sh $rs2, ${imm}(${rs1})
7060	// Operand: rs2
7061	// Operand: rs1
7062	// Operand: imm
7063	return true;
7064	} // if
7065	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
7066	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
7067	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
7068	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7069	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7070	MI.getOperand(`2`).isImm() &&
7071	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `26` / uimm5_lsb0 /) &&
7072	MI.getOperand(`2`).isImm() &&
7073	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `27` / uimm5_lsb0_optional /)) {
7074	// qk.c.shsp $rd_rs2, ${imm}(${rs1})
7075	// Operand: rd_rs2
7076	// Operand: rs1
7077	// Operand: imm
7078	return true;
7079	} // if
7080	break;
7081	} // case SH
7082	case RISCV::SH1ADD: {
7083	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
7084	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
7085	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
7086	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
7087	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
7088	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7089	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
7090	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7091	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7092	RISCVValidateMachineOperand(MachineOperand::CreateImm(`2`), &STI, `18` / uimm5 /)) {
7093	// qc.c.muliadd $rd, $rs1, $uimm
7094	// Operand: rd_wb
7095	// Operand: rd
7096	// Operand: rs1
7097	// Operand: uimm
7098	return true;
7099	} // if
7100	break;
7101	} // case SH1ADD
7102	case RISCV::SH2ADD: {
7103	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
7104	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
7105	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
7106	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
7107	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
7108	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7109	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
7110	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7111	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7112	RISCVValidateMachineOperand(MachineOperand::CreateImm(`4`), &STI, `18` / uimm5 /)) {
7113	// qc.c.muliadd $rd, $rs1, $uimm
7114	// Operand: rd_wb
7115	// Operand: rd
7116	// Operand: rs1
7117	// Operand: uimm
7118	return true;
7119	} // if
7120	break;
7121	} // case SH2ADD
7122	case RISCV::SH3ADD: {
7123	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
7124	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
7125	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
7126	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
7127	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
7128	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7129	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
7130	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7131	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7132	RISCVValidateMachineOperand(MachineOperand::CreateImm(`8`), &STI, `18` / uimm5 /)) {
7133	// qc.c.muliadd $rd, $rs1, $uimm
7134	// Operand: rd_wb
7135	// Operand: rd
7136	// Operand: rs1
7137	// Operand: uimm
7138	return true;
7139	} // if
7140	break;
7141	} // case SH3ADD
7142	case RISCV::SH_INX: {
7143	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7144	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
7145	getRISCVMCRegisterClass(RISCV::GPRF16CRegClassID).contains(MI.getOperand(`0`).getReg()) &&
7146	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7147	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7148	MI.getOperand(`2`).isImm() &&
7149	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / uimm2_lsb0 /) &&
7150	MI.getOperand(`2`).isImm() &&
7151	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `23` / uimm2_lsb0_optional /)) {
7152	// c.sh $rs2, ${imm}(${rs1})
7153	// Operand: rs2
7154	// Operand: rs1
7155	// Operand: imm
7156	return true;
7157	} // if
7158	break;
7159	} // case SH_INX
7160	case RISCV::SLLI: {
7161	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7162	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7163	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7164	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7165	getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(`1`).getReg()) &&
7166	MI.getOperand(`2`).isImm() &&
7167	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /) &&
7168	MI.getOperand(`2`).isImm() &&
7169	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `38` / uimmlog2xlen /)) {
7170	// c.slli $rd, $imm
7171	// Operand: rd_wb
7172	// Operand: rd
7173	// Operand: imm
7174	return true;
7175	} // if
7176	break;
7177	} // case SLLI
7178	case RISCV::SRAI: {
7179	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7180	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7181	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7182	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7183	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7184	MI.getOperand(`2`).isImm() &&
7185	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /) &&
7186	MI.getOperand(`2`).isImm() &&
7187	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `38` / uimmlog2xlen /)) {
7188	// c.srai $rs1, $imm
7189	// Operand: rd
7190	// Operand: rs1
7191	// Operand: imm
7192	return true;
7193	} // if
7194	break;
7195	} // case SRAI
7196	case RISCV::SRLI: {
7197	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7198	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7199	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7200	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7201	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7202	MI.getOperand(`2`).isImm() &&
7203	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /) &&
7204	MI.getOperand(`2`).isImm() &&
7205	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `38` / uimmlog2xlen /)) {
7206	// c.srli $rs1, $imm
7207	// Operand: rd
7208	// Operand: rs1
7209	// Operand: imm
7210	return true;
7211	} // if
7212	break;
7213	} // case SRLI
7214	case RISCV::SSPOPCHK: {
7215	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
7216	MI.getOperand(`0`).isReg() &&
7217	(MI.getOperand(`0`).getReg() == RISCV::X5)) {
7218	// c.sspopchk $rs1
7219	// Operand: rs1
7220	return true;
7221	} // if
7222	break;
7223	} // case SSPOPCHK
7224	case RISCV::SSPUSH: {
7225	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
7226	MI.getOperand(`0`).isReg() &&
7227	(MI.getOperand(`0`).getReg() == RISCV::X1)) {
7228	// c.sspush $rs1
7229	// Operand: rs1
7230	return true;
7231	} // if
7232	break;
7233	} // case SSPUSH
7234	case RISCV::SUB: {
7235	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7236	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7237	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7238	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7239	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7240	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7241	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg())) {
7242	// c.sub $rd, $rs2
7243	// Operand: rd_wb
7244	// Operand: rd
7245	// Operand: rs2
7246	return true;
7247	} // if
7248	break;
7249	} // case SUB
7250	case RISCV::SUBW: {
7251	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
7252	STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7253	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7254	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7255	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7256	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7257	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7258	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg())) {
7259	// c.subw $rd, $rs2
7260	// Operand: rd_wb
7261	// Operand: rd
7262	// Operand: rs2
7263	return true;
7264	} // if
7265	break;
7266	} // case SUBW
7267	case RISCV::SW: {
7268	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7269	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
7270	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`0`).getReg()) &&
7271	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7272	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7273	MI.getOperand(`2`).isImm() &&
7274	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `11` / uimm7_lsb00 /) &&
7275	MI.getOperand(`2`).isImm() &&
7276	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm7_lsb00_optional /)) {
7277	// c.sw $rs2, ${imm}(${rs1})
7278	// Operand: rs2
7279	// Operand: rs1
7280	// Operand: imm
7281	return true;
7282	} // if
7283	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7284	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
7285	getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(`0`).getReg()) &&
7286	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7287	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7288	MI.getOperand(`2`).isImm() &&
7289	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm8_lsb00 /) &&
7290	MI.getOperand(`2`).isImm() &&
7291	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm8_lsb00_optional /)) {
7292	// c.swsp $rs2, ${imm}(${rs1})
7293	// Operand: rs2
7294	// Operand: rs1
7295	// Operand: imm
7296	return true;
7297	} // if
7298	break;
7299	} // case SW
7300	case RISCV::SW_INX: {
7301	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7302	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
7303	getRISCVMCRegisterClass(RISCV::GPRF32RegClassID).contains(MI.getOperand(`0`).getReg()) &&
7304	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7305	getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7306	MI.getOperand(`2`).isImm() &&
7307	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm8_lsb00 /) &&
7308	MI.getOperand(`2`).isImm() &&
7309	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm8_lsb00_optional /)) {
7310	// c.swsp $rs2, ${imm}(${rs1})
7311	// Operand: rs2
7312	// Operand: rs1
7313	// Operand: imm
7314	return true;
7315	} // if
7316	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7317	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
7318	getRISCVMCRegisterClass(RISCV::GPRF32CRegClassID).contains(MI.getOperand(`0`).getReg()) &&
7319	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7320	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7321	MI.getOperand(`2`).isImm() &&
7322	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `11` / uimm7_lsb00 /) &&
7323	MI.getOperand(`2`).isImm() &&
7324	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm7_lsb00_optional /)) {
7325	// c.sw $rs2, ${imm}(${rs1})
7326	// Operand: rs2
7327	// Operand: rs1
7328	// Operand: imm
7329	return true;
7330	} // if
7331	break;
7332	} // case SW_INX
7333	case RISCV::UNIMP: {
7334	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) {
7335	// c.unimp
7336	return true;
7337	} // if
7338	break;
7339	} // case UNIMP
7340	case RISCV::XOR: {
7341	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7342	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7343	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7344	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7345	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg()) &&
7346	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7347	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg())) {
7348	// c.xor $rd, $rs2
7349	// Operand: rd_wb
7350	// Operand: rd
7351	// Operand: rs2
7352	return true;
7353	} // if
7354	if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] &&
7355	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
7356	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
7357	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7358	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`2`).getReg()) &&
7359	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7360	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
7361	// c.xor $rd, $rs2
7362	// Operand: rd_wb
7363	// Operand: rd
7364	// Operand: rs2
7365	return true;
7366	} // if
7367	break;
7368	} // case XOR
7369	case RISCV::XORI: {
7370	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7371	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7372	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7373	MI.getOperand(`2`).isImm() &&
7374	(MI.getOperand(`2`).getImm() == -`1`) &&
7375	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7376	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
7377	// c.not $rd
7378	// Operand: rd_wb
7379	// Operand: rd
7380	return true;
7381	} // if
7382	break;
7383	} // case XORI
7384	case RISCV::ZEXT_H_RV32: {
7385	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
7386	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7387	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7388	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7389	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7390	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
7391	// c.zext.h $rd
7392	// Operand: rd_wb
7393	// Operand: rd
7394	return true;
7395	} // if
7396	break;
7397	} // case ZEXT_H_RV32
7398	case RISCV::ZEXT_H_RV64: {
7399	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
7400	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7401	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7402	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7403	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7404	getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(`1`).getReg())) {
7405	// c.zext.h $rd
7406	// Operand: rd_wb
7407	// Operand: rd
7408	return true;
7409	} // if
7410	break;
7411	} // case ZEXT_H_RV64
7412	} // switch
7413	return false;
7414	}
7415
7416	#endif // GEN_CHECK_COMPRESS_INSTR
7417
7418

Browse the source code of llvm_projects/build/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc