RISCVGenCompressInstEmitter.inc source code [llvm_projects/build/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Compress instruction Source Fragment \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| From: RISCV.td \|
7	\| \|
8	\===----------------------------------------------------------------------===/
9
10	#ifdef GEN_COMPRESS_INSTR
11	#undef GEN_COMPRESS_INSTR
12
13	static bool RISCVValidateMCOperandForCompress(const MCOperand &MCOp,
14	const MCSubtargetInfo &STI,
15	unsigned PredicateIndex) {
16	switch (PredicateIndex) {
17	default:
18	llvm_unreachable("Unknown MCOperandPredicate kind");
19	break;
20	case `1`: {
21	// uimm10_lsb00nonzero
22	int64_t Imm;
23	if (!MCOp.evaluateAsConstantImm(Imm))
24	return false;
25	return isShiftedUInt<`8`, `2`>(x: Imm) && (Imm != `0`);
26	}
27	case `2`: {
28	// simm6nonzero
29	int64_t Imm;
30	if (MCOp.evaluateAsConstantImm(Imm))
31	return (Imm != `0`) && isInt<`6`>(x: Imm);
32	return MCOp.isBareSymbolRef();
33	}
34	case `3`: {
35	// simm6
36	int64_t Imm;
37	if (MCOp.evaluateAsConstantImm(Imm))
38	return isInt<`6`>(x: Imm);
39	return MCOp.isBareSymbolRef();
40	}
41	case `4`: {
42	// simm10_lsb0000nonzero
43	int64_t Imm;
44	if (!MCOp.evaluateAsConstantImm(Imm))
45	return false;
46	return isShiftedInt<`6`, `4`>(x: Imm) && (Imm != `0`);
47	}
48	case `5`: {
49	// bare_simm9_lsb0
50	int64_t Imm;
51	if (MCOp.evaluateAsConstantImm(Imm))
52	return isShiftedInt<`8`, `1`>(x: Imm);
53	return MCOp.isBareSymbolRef();
54	}
55	case `6`: {
56	// uimmlog2xlennonzero
57	int64_t Imm;
58	if (!MCOp.evaluateAsConstantImm(Imm))
59	return false;
60	if (STI.getTargetTriple().isArch64Bit())
61	return isUInt<`6`>(x: Imm) && (Imm != `0`);
62	return isUInt<`5`>(x: Imm) && (Imm != `0`);
63	}
64	case `7`: {
65	// uimm8_lsb000
66	int64_t Imm;
67	if (!MCOp.evaluateAsConstantImm(Imm))
68	return false;
69	return isShiftedUInt<`5`, `3`>(x: Imm);
70	}
71	case `8`: {
72	// uimm9_lsb000
73	int64_t Imm;
74	if (!MCOp.evaluateAsConstantImm(Imm))
75	return false;
76	return isShiftedUInt<`6`, `3`>(x: Imm);
77	}
78	case `9`: {
79	// uimm7_lsb00
80	int64_t Imm;
81	if (!MCOp.evaluateAsConstantImm(Imm))
82	return false;
83	return isShiftedUInt<`5`, `2`>(x: Imm);
84	}
85	case `10`: {
86	// uimm8_lsb00
87	int64_t Imm;
88	if (!MCOp.evaluateAsConstantImm(Imm))
89	return false;
90	return isShiftedUInt<`6`, `2`>(x: Imm);
91	}
92	case `11`: {
93	// bare_simm12_lsb0
94	int64_t Imm;
95	if (MCOp.evaluateAsConstantImm(Imm))
96	return isShiftedInt<`11`, `1`>(x: Imm);
97	return MCOp.isBareSymbolRef();
98	}
99	case `12`: {
100	// uimm2
101	int64_t Imm;
102	if (!MCOp.evaluateAsConstantImm(Imm))
103	return false;
104	return isUInt<`2`>(x: Imm);
105	}
106	case `13`: {
107	// uimm5
108	int64_t Imm;
109	if (!MCOp.evaluateAsConstantImm(Imm))
110	return false;
111	return isUInt<`5`>(x: Imm);
112	}
113	case `14`: {
114	// uimm4
115	int64_t Imm;
116	if (!MCOp.evaluateAsConstantImm(Imm))
117	return false;
118	return isUInt<`4`>(x: Imm);
119	}
120	case `15`: {
121	// uimm2_lsb0
122	int64_t Imm;
123	if (!MCOp.evaluateAsConstantImm(Imm))
124	return false;
125	return isShiftedUInt<`1`, `1`>(x: Imm);
126	}
127	case `16`: {
128	// uimm6_lsb0
129	int64_t Imm;
130	if (!MCOp.evaluateAsConstantImm(Imm))
131	return false;
132	return isShiftedUInt<`5`, `1`>(x: Imm);
133	}
134	case `17`: {
135	// uimm5_lsb0
136	int64_t Imm;
137	if (!MCOp.evaluateAsConstantImm(Imm))
138	return false;
139	return isShiftedUInt<`4`, `1`>(x: Imm);
140	}
141	case `18`: {
142	// c_lui_imm
143	int64_t Imm;
144	if (!MCOp.evaluateAsConstantImm(Imm))
145	return false;
146	return (Imm != `0`) && (isUInt<`5`>(x: Imm) \|\|
147	(Imm >= `0xfffe0` && Imm <= `0xfffff`));
148	}
149	case `19`: {
150	// uimm5ge6_plus1
151	int64_t Imm;
152	if (!MCOp.evaluateAsConstantImm(Imm))
153	return false;
154	return Imm >= `6` && Imm <= `32`;
155	}
156	case `20`: {
157	// simm12_lo
158	int64_t Imm;
159	if (MCOp.evaluateAsConstantImm(Imm))
160	return isInt<`12`>(x: Imm);
161	return MCOp.isBareSymbolRef();
162	}
163	case `21`: {
164	// simm5nonzero
165	int64_t Imm;
166	if (!MCOp.evaluateAsConstantImm(Imm))
167	return false;
168	return (Imm != `0`) && isInt<`5`>(x: Imm);
169	}
170	case `22`: {
171	// bare_simm13_lsb0
172	int64_t Imm;
173	if (MCOp.evaluateAsConstantImm(Imm))
174	return isShiftedInt<`12`, `1`>(x: Imm);
175	return MCOp.isBareSymbolRef();
176	}
177	case `23`: {
178	// uimm5nonzero
179	int64_t Imm;
180	if (!MCOp.evaluateAsConstantImm(Imm))
181	return false;
182	return (Imm != `0`) && isUInt<`5`>(x: Imm);;
183	}
184	case `24`: {
185	// simm21_lsb0_jal
186	int64_t Imm;
187	if (MCOp.evaluateAsConstantImm(Imm))
188	return isShiftedInt<`20`, `1`>(x: Imm);
189	return MCOp.isBareSymbolRef();
190	}
191	case `25`: {
192	// simm20_li
193	int64_t Imm;
194	if (MCOp.evaluateAsConstantImm(Imm))
195	return isInt<`20`>(x: Imm);
196	return MCOp.isBareSymbolRef();
197	}
198	case `26`: {
199	// uimm5slist
200	int64_t Imm;
201	if (!MCOp.evaluateAsConstantImm(Imm))
202	return false;
203	return ((Imm == `0`) \|\| (Imm == `1`) \|\|
204	(Imm == `2`) \|\| (Imm == `4`) \|\|
205	(Imm == `8`) \|\| (Imm == `16`) \|\|
206	(Imm == `15`) \|\| (Imm == `31`));
207	}
208	case `27`: {
209	// uimmlog2xlen
210	int64_t Imm;
211	if (!MCOp.evaluateAsConstantImm(Imm))
212	return false;
213	if (STI.getTargetTriple().isArch64Bit())
214	return isUInt<`6`>(x: Imm);
215	return isUInt<`5`>(x: Imm);
216	}
217	}
218	}
219
220	static bool compressInst(MCInst &OutInst,
221	const MCInst &MI,
222	const MCSubtargetInfo &STI) {
223	switch (MI.getOpcode()) {
224	default: return false;
225	case RISCV::ADD: {
226	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
227	MI.getOperand(i: `1`).isReg() &&
228	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
229	MI.getOperand(i: `0`).isReg() &&
230	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
231	MI.getOperand(i: `2`).isReg() &&
232	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
233	// c.mv $rs1, $rs2
234	OutInst.setOpcode(RISCV::C_MV);
235	// Operand: rs1
236	OutInst.addOperand(Op: MI.getOperand(i: `0`));
237	// Operand: rs2
238	OutInst.addOperand(Op: MI.getOperand(i: `2`));
239	OutInst.setLoc(MI.getLoc());
240	return true;
241	} // if
242	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
243	MI.getOperand(i: `2`).isReg() &&
244	(MI.getOperand(i: `2`).getReg() == RISCV::X0) &&
245	MI.getOperand(i: `0`).isReg() &&
246	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
247	MI.getOperand(i: `1`).isReg() &&
248	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
249	// c.mv $rs1, $rs2
250	OutInst.setOpcode(RISCV::C_MV);
251	// Operand: rs1
252	OutInst.addOperand(Op: MI.getOperand(i: `0`));
253	// Operand: rs2
254	OutInst.addOperand(Op: MI.getOperand(i: `1`));
255	OutInst.setLoc(MI.getLoc());
256	return true;
257	} // if
258	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
259	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
260	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
261	MI.getOperand(i: `1`).isReg() &&
262	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
263	MI.getOperand(i: `2`).isReg() &&
264	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
265	// c.add $rs1, $rs2
266	OutInst.setOpcode(RISCV::C_ADD);
267	// Operand: rd
268	OutInst.addOperand(Op: MI.getOperand(i: `1`));
269	// Operand: rs1
270	OutInst.addOperand(Op: MI.getOperand(i: `1`));
271	// Operand: rs2
272	OutInst.addOperand(Op: MI.getOperand(i: `2`));
273	OutInst.setLoc(MI.getLoc());
274	return true;
275	} // if
276	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
277	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
278	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
279	MI.getOperand(i: `2`).isReg() &&
280	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
281	MI.getOperand(i: `1`).isReg() &&
282	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
283	// c.add $rs1, $rs2
284	OutInst.setOpcode(RISCV::C_ADD);
285	// Operand: rd
286	OutInst.addOperand(Op: MI.getOperand(i: `2`));
287	// Operand: rs1
288	OutInst.addOperand(Op: MI.getOperand(i: `2`));
289	// Operand: rs2
290	OutInst.addOperand(Op: MI.getOperand(i: `1`));
291	OutInst.setLoc(MI.getLoc());
292	return true;
293	} // if
294	break;
295	} // case ADD
296	case RISCV::ADDI: {
297	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
298	MI.getOperand(i: `0`).isReg() &&
299	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
300	MI.getOperand(i: `1`).isReg() &&
301	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
302	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1` / uimm10_lsb00nonzero /)) {
303	// c.addi4spn $rd, $rs1, $imm
304	OutInst.setOpcode(RISCV::C_ADDI4SPN);
305	// Operand: rd
306	OutInst.addOperand(Op: MI.getOperand(i: `0`));
307	// Operand: rs1
308	OutInst.addOperand(Op: MI.getOperand(i: `1`));
309	// Operand: imm
310	OutInst.addOperand(Op: MI.getOperand(i: `2`));
311	OutInst.setLoc(MI.getLoc());
312	return true;
313	} // if
314	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
315	MI.getOperand(i: `0`).isReg() &&
316	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
317	MI.getOperand(i: `1`).isReg() &&
318	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
319	MI.getOperand(i: `2`).isImm() &&
320	(MI.getOperand(i: `2`).getImm() == `0`)) {
321	// c.nop
322	OutInst.setOpcode(RISCV::C_NOP);
323	OutInst.setLoc(MI.getLoc());
324	return true;
325	} // if
326	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
327	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
328	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
329	MI.getOperand(i: `1`).isReg() &&
330	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
331	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm6nonzero /) &&
332	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
333	// c.addi $rd, $imm
334	OutInst.setOpcode(RISCV::C_ADDI);
335	// Operand: rd_wb
336	OutInst.addOperand(Op: MI.getOperand(i: `1`));
337	// Operand: rd
338	OutInst.addOperand(Op: MI.getOperand(i: `1`));
339	// Operand: imm
340	OutInst.addOperand(Op: MI.getOperand(i: `2`));
341	OutInst.setLoc(MI.getLoc());
342	return true;
343	} // if
344	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
345	MI.getOperand(i: `1`).isReg() &&
346	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
347	MI.getOperand(i: `0`).isReg() &&
348	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
349	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
350	// c.li $rd, $imm
351	OutInst.setOpcode(RISCV::C_LI);
352	// Operand: rd
353	OutInst.addOperand(Op: MI.getOperand(i: `0`));
354	// Operand: imm
355	OutInst.addOperand(Op: MI.getOperand(i: `2`));
356	OutInst.setLoc(MI.getLoc());
357	return true;
358	} // if
359	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
360	MI.getOperand(i: `0`).isReg() &&
361	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
362	MI.getOperand(i: `1`).isReg() &&
363	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
364	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4` / simm10_lsb0000nonzero /)) {
365	// c.addi16sp $rd, $imm
366	OutInst.setOpcode(RISCV::C_ADDI16SP);
367	// Operand: rd_wb
368	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
369	// Operand: rd
370	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
371	// Operand: imm
372	OutInst.addOperand(Op: MI.getOperand(i: `2`));
373	OutInst.setLoc(MI.getLoc());
374	return true;
375	} // if
376	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
377	MI.getOperand(i: `2`).isImm() &&
378	(MI.getOperand(i: `2`).getImm() == `0`) &&
379	MI.getOperand(i: `0`).isReg() &&
380	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
381	MI.getOperand(i: `1`).isReg() &&
382	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
383	// c.mv $rs1, $rs2
384	OutInst.setOpcode(RISCV::C_MV);
385	// Operand: rs1
386	OutInst.addOperand(Op: MI.getOperand(i: `0`));
387	// Operand: rs2
388	OutInst.addOperand(Op: MI.getOperand(i: `1`));
389	OutInst.setLoc(MI.getLoc());
390	return true;
391	} // if
392	break;
393	} // case ADDI
394	case RISCV::ADDIW: {
395	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
396	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
397	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
398	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
399	MI.getOperand(i: `1`).isReg() &&
400	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
401	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
402	// c.addiw $rd, $imm
403	OutInst.setOpcode(RISCV::C_ADDIW);
404	// Operand: rd_wb
405	OutInst.addOperand(Op: MI.getOperand(i: `1`));
406	// Operand: rd
407	OutInst.addOperand(Op: MI.getOperand(i: `1`));
408	// Operand: imm
409	OutInst.addOperand(Op: MI.getOperand(i: `2`));
410	OutInst.setLoc(MI.getLoc());
411	return true;
412	} // if
413	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
414	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
415	MI.getOperand(i: `1`).isReg() &&
416	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
417	MI.getOperand(i: `0`).isReg() &&
418	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
419	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
420	// c.li $rd, $imm
421	OutInst.setOpcode(RISCV::C_LI);
422	// Operand: rd
423	OutInst.addOperand(Op: MI.getOperand(i: `0`));
424	// Operand: imm
425	OutInst.addOperand(Op: MI.getOperand(i: `2`));
426	OutInst.setLoc(MI.getLoc());
427	return true;
428	} // if
429	break;
430	} // case ADDIW
431	case RISCV::ADDW: {
432	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
433	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
434	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
435	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
436	MI.getOperand(i: `1`).isReg() &&
437	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
438	MI.getOperand(i: `2`).isReg() &&
439	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
440	// c.addw $rd, $rs2
441	OutInst.setOpcode(RISCV::C_ADDW);
442	// Operand: rd_wb
443	OutInst.addOperand(Op: MI.getOperand(i: `1`));
444	// Operand: rd
445	OutInst.addOperand(Op: MI.getOperand(i: `1`));
446	// Operand: rs2
447	OutInst.addOperand(Op: MI.getOperand(i: `2`));
448	OutInst.setLoc(MI.getLoc());
449	return true;
450	} // if
451	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
452	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
453	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
454	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
455	MI.getOperand(i: `2`).isReg() &&
456	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
457	MI.getOperand(i: `1`).isReg() &&
458	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
459	// c.addw $rd, $rs2
460	OutInst.setOpcode(RISCV::C_ADDW);
461	// Operand: rd_wb
462	OutInst.addOperand(Op: MI.getOperand(i: `2`));
463	// Operand: rd
464	OutInst.addOperand(Op: MI.getOperand(i: `2`));
465	// Operand: rs2
466	OutInst.addOperand(Op: MI.getOperand(i: `1`));
467	OutInst.setLoc(MI.getLoc());
468	return true;
469	} // if
470	break;
471	} // case ADDW
472	case RISCV::ADD_UW: {
473	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
474	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
475	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
476	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
477	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
478	MI.getOperand(i: `2`).isReg() &&
479	(MI.getOperand(i: `2`).getReg() == RISCV::X0) &&
480	MI.getOperand(i: `1`).isReg() &&
481	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
482	// c.zext.w $rd
483	OutInst.setOpcode(RISCV::C_ZEXT_W);
484	// Operand: rd_wb
485	OutInst.addOperand(Op: MI.getOperand(i: `1`));
486	// Operand: rd
487	OutInst.addOperand(Op: MI.getOperand(i: `1`));
488	OutInst.setLoc(MI.getLoc());
489	return true;
490	} // if
491	break;
492	} // case ADD_UW
493	case RISCV::AND: {
494	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
495	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
496	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
497	MI.getOperand(i: `1`).isReg() &&
498	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
499	MI.getOperand(i: `2`).isReg() &&
500	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
501	// c.and $rd, $rs2
502	OutInst.setOpcode(RISCV::C_AND);
503	// Operand: rd_wb
504	OutInst.addOperand(Op: MI.getOperand(i: `1`));
505	// Operand: rd
506	OutInst.addOperand(Op: MI.getOperand(i: `1`));
507	// Operand: rs2
508	OutInst.addOperand(Op: MI.getOperand(i: `2`));
509	OutInst.setLoc(MI.getLoc());
510	return true;
511	} // if
512	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
513	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
514	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
515	MI.getOperand(i: `2`).isReg() &&
516	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
517	MI.getOperand(i: `1`).isReg() &&
518	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
519	// c.and $rd, $rs2
520	OutInst.setOpcode(RISCV::C_AND);
521	// Operand: rd_wb
522	OutInst.addOperand(Op: MI.getOperand(i: `2`));
523	// Operand: rd
524	OutInst.addOperand(Op: MI.getOperand(i: `2`));
525	// Operand: rs2
526	OutInst.addOperand(Op: MI.getOperand(i: `1`));
527	OutInst.setLoc(MI.getLoc());
528	return true;
529	} // if
530	break;
531	} // case AND
532	case RISCV::ANDI: {
533	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
534	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
535	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
536	MI.getOperand(i: `1`).isReg() &&
537	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
538	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
539	// c.andi $rs1, $imm
540	OutInst.setOpcode(RISCV::C_ANDI);
541	// Operand: rd
542	OutInst.addOperand(Op: MI.getOperand(i: `1`));
543	// Operand: rs1
544	OutInst.addOperand(Op: MI.getOperand(i: `1`));
545	// Operand: imm
546	OutInst.addOperand(Op: MI.getOperand(i: `2`));
547	OutInst.setLoc(MI.getLoc());
548	return true;
549	} // if
550	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
551	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
552	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
553	MI.getOperand(i: `2`).isImm() &&
554	(MI.getOperand(i: `2`).getImm() == `255`) &&
555	MI.getOperand(i: `1`).isReg() &&
556	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
557	// c.zext.b $rd
558	OutInst.setOpcode(RISCV::C_ZEXT_B);
559	// Operand: rd_wb
560	OutInst.addOperand(Op: MI.getOperand(i: `1`));
561	// Operand: rd
562	OutInst.addOperand(Op: MI.getOperand(i: `1`));
563	OutInst.setLoc(MI.getLoc());
564	return true;
565	} // if
566	break;
567	} // case ANDI
568	case RISCV::BEQ: {
569	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
570	MI.getOperand(i: `1`).isReg() &&
571	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
572	MI.getOperand(i: `0`).isReg() &&
573	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
574	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / bare_simm9_lsb0 /)) {
575	// c.beqz $rs1, $imm
576	OutInst.setOpcode(RISCV::C_BEQZ);
577	// Operand: rs1
578	OutInst.addOperand(Op: MI.getOperand(i: `0`));
579	// Operand: imm
580	OutInst.addOperand(Op: MI.getOperand(i: `2`));
581	OutInst.setLoc(MI.getLoc());
582	return true;
583	} // if
584	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
585	MI.getOperand(i: `0`).isReg() &&
586	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
587	MI.getOperand(i: `1`).isReg() &&
588	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
589	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / bare_simm9_lsb0 /)) {
590	// c.beqz $rs1, $imm
591	OutInst.setOpcode(RISCV::C_BEQZ);
592	// Operand: rs1
593	OutInst.addOperand(Op: MI.getOperand(i: `1`));
594	// Operand: imm
595	OutInst.addOperand(Op: MI.getOperand(i: `2`));
596	OutInst.setLoc(MI.getLoc());
597	return true;
598	} // if
599	break;
600	} // case BEQ
601	case RISCV::BEXTI: {
602	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
603	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
604	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
605	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
606	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
607	MI.getOperand(i: `1`).isReg() &&
608	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
609	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /)) {
610	// qc.c.bexti $rs1, $shamt
611	OutInst.setOpcode(RISCV::QC_C_BEXTI);
612	// Operand: rd
613	OutInst.addOperand(Op: MI.getOperand(i: `1`));
614	// Operand: rs1
615	OutInst.addOperand(Op: MI.getOperand(i: `1`));
616	// Operand: shamt
617	OutInst.addOperand(Op: MI.getOperand(i: `2`));
618	OutInst.setLoc(MI.getLoc());
619	return true;
620	} // if
621	break;
622	} // case BEXTI
623	case RISCV::BNE: {
624	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
625	MI.getOperand(i: `1`).isReg() &&
626	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
627	MI.getOperand(i: `0`).isReg() &&
628	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
629	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / bare_simm9_lsb0 /)) {
630	// c.bnez $rs1, $imm
631	OutInst.setOpcode(RISCV::C_BNEZ);
632	// Operand: rs1
633	OutInst.addOperand(Op: MI.getOperand(i: `0`));
634	// Operand: imm
635	OutInst.addOperand(Op: MI.getOperand(i: `2`));
636	OutInst.setLoc(MI.getLoc());
637	return true;
638	} // if
639	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
640	MI.getOperand(i: `0`).isReg() &&
641	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
642	MI.getOperand(i: `1`).isReg() &&
643	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
644	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / bare_simm9_lsb0 /)) {
645	// c.bnez $rs1, $imm
646	OutInst.setOpcode(RISCV::C_BNEZ);
647	// Operand: rs1
648	OutInst.addOperand(Op: MI.getOperand(i: `1`));
649	// Operand: imm
650	OutInst.addOperand(Op: MI.getOperand(i: `2`));
651	OutInst.setLoc(MI.getLoc());
652	return true;
653	} // if
654	break;
655	} // case BNE
656	case RISCV::BSETI: {
657	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
658	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
659	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
660	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
661	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
662	MI.getOperand(i: `1`).isReg() &&
663	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
664	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /)) {
665	// qc.c.bseti $rs1, $shamt
666	OutInst.setOpcode(RISCV::QC_C_BSETI);
667	// Operand: rd
668	OutInst.addOperand(Op: MI.getOperand(i: `1`));
669	// Operand: rs1
670	OutInst.addOperand(Op: MI.getOperand(i: `1`));
671	// Operand: shamt
672	OutInst.addOperand(Op: MI.getOperand(i: `2`));
673	OutInst.setLoc(MI.getLoc());
674	return true;
675	} // if
676	break;
677	} // case BSETI
678	case RISCV::EBREAK: {
679	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
680	// c.ebreak
681	OutInst.setOpcode(RISCV::C_EBREAK);
682	OutInst.setLoc(MI.getLoc());
683	return true;
684	} // if
685	break;
686	} // case EBREAK
687	case RISCV::FLD: {
688	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
689	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
690	MI.getOperand(i: `0`).isReg() &&
691	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
692	MI.getOperand(i: `1`).isReg() &&
693	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
694	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /)) {
695	// c.fld $rd, ${imm}(${rs1})
696	OutInst.setOpcode(RISCV::C_FLD);
697	// Operand: rd
698	OutInst.addOperand(Op: MI.getOperand(i: `0`));
699	// Operand: rs1
700	OutInst.addOperand(Op: MI.getOperand(i: `1`));
701	// Operand: imm
702	OutInst.addOperand(Op: MI.getOperand(i: `2`));
703	OutInst.setLoc(MI.getLoc());
704	return true;
705	} // if
706	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
707	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
708	MI.getOperand(i: `0`).isReg() &&
709	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
710	MI.getOperand(i: `1`).isReg() &&
711	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
712	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm9_lsb000 /)) {
713	// c.fldsp $rd, ${imm}(${rs1})
714	OutInst.setOpcode(RISCV::C_FLDSP);
715	// Operand: rd
716	OutInst.addOperand(Op: MI.getOperand(i: `0`));
717	// Operand: rs1
718	OutInst.addOperand(Op: MI.getOperand(i: `1`));
719	// Operand: imm
720	OutInst.addOperand(Op: MI.getOperand(i: `2`));
721	OutInst.setLoc(MI.getLoc());
722	return true;
723	} // if
724	break;
725	} // case FLD
726	case RISCV::FLW: {
727	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
728	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
729	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
730	MI.getOperand(i: `0`).isReg() &&
731	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
732	MI.getOperand(i: `1`).isReg() &&
733	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
734	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm7_lsb00 /)) {
735	// c.flw $rd, ${imm}(${rs1})
736	OutInst.setOpcode(RISCV::C_FLW);
737	// Operand: rd
738	OutInst.addOperand(Op: MI.getOperand(i: `0`));
739	// Operand: rs1
740	OutInst.addOperand(Op: MI.getOperand(i: `1`));
741	// Operand: imm
742	OutInst.addOperand(Op: MI.getOperand(i: `2`));
743	OutInst.setLoc(MI.getLoc());
744	return true;
745	} // if
746	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
747	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
748	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
749	MI.getOperand(i: `0`).isReg() &&
750	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
751	MI.getOperand(i: `1`).isReg() &&
752	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
753	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm8_lsb00 /)) {
754	// c.flwsp $rd, ${imm}(${rs1})
755	OutInst.setOpcode(RISCV::C_FLWSP);
756	// Operand: rd
757	OutInst.addOperand(Op: MI.getOperand(i: `0`));
758	// Operand: rs1
759	OutInst.addOperand(Op: MI.getOperand(i: `1`));
760	// Operand: imm
761	OutInst.addOperand(Op: MI.getOperand(i: `2`));
762	OutInst.setLoc(MI.getLoc());
763	return true;
764	} // if
765	break;
766	} // case FLW
767	case RISCV::FSD: {
768	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
769	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
770	MI.getOperand(i: `0`).isReg() &&
771	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
772	MI.getOperand(i: `1`).isReg() &&
773	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
774	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /)) {
775	// c.fsd $rs2, ${imm}(${rs1})
776	OutInst.setOpcode(RISCV::C_FSD);
777	// Operand: rs2
778	OutInst.addOperand(Op: MI.getOperand(i: `0`));
779	// Operand: rs1
780	OutInst.addOperand(Op: MI.getOperand(i: `1`));
781	// Operand: imm
782	OutInst.addOperand(Op: MI.getOperand(i: `2`));
783	OutInst.setLoc(MI.getLoc());
784	return true;
785	} // if
786	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
787	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
788	MI.getOperand(i: `0`).isReg() &&
789	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
790	MI.getOperand(i: `1`).isReg() &&
791	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
792	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm9_lsb000 /)) {
793	// c.fsdsp $rs2, ${imm}(${rs1})
794	OutInst.setOpcode(RISCV::C_FSDSP);
795	// Operand: rs2
796	OutInst.addOperand(Op: MI.getOperand(i: `0`));
797	// Operand: rs1
798	OutInst.addOperand(Op: MI.getOperand(i: `1`));
799	// Operand: imm
800	OutInst.addOperand(Op: MI.getOperand(i: `2`));
801	OutInst.setLoc(MI.getLoc());
802	return true;
803	} // if
804	break;
805	} // case FSD
806	case RISCV::FSW: {
807	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
808	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
809	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
810	MI.getOperand(i: `0`).isReg() &&
811	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
812	MI.getOperand(i: `1`).isReg() &&
813	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
814	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm7_lsb00 /)) {
815	// c.fsw $rs2, ${imm}(${rs1})
816	OutInst.setOpcode(RISCV::C_FSW);
817	// Operand: rs2
818	OutInst.addOperand(Op: MI.getOperand(i: `0`));
819	// Operand: rs1
820	OutInst.addOperand(Op: MI.getOperand(i: `1`));
821	// Operand: imm
822	OutInst.addOperand(Op: MI.getOperand(i: `2`));
823	OutInst.setLoc(MI.getLoc());
824	return true;
825	} // if
826	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
827	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
828	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
829	MI.getOperand(i: `0`).isReg() &&
830	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
831	MI.getOperand(i: `1`).isReg() &&
832	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
833	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm8_lsb00 /)) {
834	// c.fswsp $rs2, ${imm}(${rs1})
835	OutInst.setOpcode(RISCV::C_FSWSP);
836	// Operand: rs2
837	OutInst.addOperand(Op: MI.getOperand(i: `0`));
838	// Operand: rs1
839	OutInst.addOperand(Op: MI.getOperand(i: `1`));
840	// Operand: imm
841	OutInst.addOperand(Op: MI.getOperand(i: `2`));
842	OutInst.setLoc(MI.getLoc());
843	return true;
844	} // if
845	break;
846	} // case FSW
847	case RISCV::JAL: {
848	if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
849	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
850	MI.getOperand(i: `0`).isReg() &&
851	(MI.getOperand(i: `0`).getReg() == RISCV::X1) &&
852	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `11` / bare_simm12_lsb0 /)) {
853	// c.jal $offset
854	OutInst.setOpcode(RISCV::C_JAL);
855	// Operand: offset
856	OutInst.addOperand(Op: MI.getOperand(i: `1`));
857	OutInst.setLoc(MI.getLoc());
858	return true;
859	} // if
860	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
861	MI.getOperand(i: `0`).isReg() &&
862	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
863	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `11` / bare_simm12_lsb0 /)) {
864	// c.j $offset
865	OutInst.setOpcode(RISCV::C_J);
866	// Operand: offset
867	OutInst.addOperand(Op: MI.getOperand(i: `1`));
868	OutInst.setLoc(MI.getLoc());
869	return true;
870	} // if
871	break;
872	} // case JAL
873	case RISCV::JALR: {
874	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
875	MI.getOperand(i: `0`).isReg() &&
876	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
877	MI.getOperand(i: `2`).isImm() &&
878	(MI.getOperand(i: `2`).getImm() == `0`) &&
879	MI.getOperand(i: `1`).isReg() &&
880	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
881	// c.jr $rs1
882	OutInst.setOpcode(RISCV::C_JR);
883	// Operand: rs1
884	OutInst.addOperand(Op: MI.getOperand(i: `1`));
885	OutInst.setLoc(MI.getLoc());
886	return true;
887	} // if
888	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
889	MI.getOperand(i: `0`).isReg() &&
890	(MI.getOperand(i: `0`).getReg() == RISCV::X1) &&
891	MI.getOperand(i: `2`).isImm() &&
892	(MI.getOperand(i: `2`).getImm() == `0`) &&
893	MI.getOperand(i: `1`).isReg() &&
894	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
895	// c.jalr $rs1
896	OutInst.setOpcode(RISCV::C_JALR);
897	// Operand: rs1
898	OutInst.addOperand(Op: MI.getOperand(i: `1`));
899	OutInst.setLoc(MI.getLoc());
900	return true;
901	} // if
902	break;
903	} // case JALR
904	case RISCV::LBU: {
905	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
906	MI.getOperand(i: `0`).isReg() &&
907	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
908	MI.getOperand(i: `1`).isReg() &&
909	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
910	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm2 /)) {
911	// c.lbu $rd, ${imm}(${rs1})
912	OutInst.setOpcode(RISCV::C_LBU);
913	// Operand: rd
914	OutInst.addOperand(Op: MI.getOperand(i: `0`));
915	// Operand: rs1
916	OutInst.addOperand(Op: MI.getOperand(i: `1`));
917	// Operand: imm
918	OutInst.addOperand(Op: MI.getOperand(i: `2`));
919	OutInst.setLoc(MI.getLoc());
920	return true;
921	} // if
922	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
923	MI.getOperand(i: `0`).isReg() &&
924	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
925	MI.getOperand(i: `1`).isReg() &&
926	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
927	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm5 /)) {
928	// qk.c.lbu $rd, ${imm}(${rs1})
929	OutInst.setOpcode(RISCV::QK_C_LBU);
930	// Operand: rd
931	OutInst.addOperand(Op: MI.getOperand(i: `0`));
932	// Operand: rs1
933	OutInst.addOperand(Op: MI.getOperand(i: `1`));
934	// Operand: imm
935	OutInst.addOperand(Op: MI.getOperand(i: `2`));
936	OutInst.setLoc(MI.getLoc());
937	return true;
938	} // if
939	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
940	MI.getOperand(i: `0`).isReg() &&
941	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
942	MI.getOperand(i: `1`).isReg() &&
943	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
944	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm4 /)) {
945	// qk.c.lbusp $rd_rs2, ${imm}(${rs1})
946	OutInst.setOpcode(RISCV::QK_C_LBUSP);
947	// Operand: rd_rs2
948	OutInst.addOperand(Op: MI.getOperand(i: `0`));
949	// Operand: rs1
950	OutInst.addOperand(Op: MI.getOperand(i: `1`));
951	// Operand: imm
952	OutInst.addOperand(Op: MI.getOperand(i: `2`));
953	OutInst.setLoc(MI.getLoc());
954	return true;
955	} // if
956	break;
957	} // case LBU
958	case RISCV::LD: {
959	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
960	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
961	MI.getOperand(i: `0`).isReg() &&
962	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
963	MI.getOperand(i: `1`).isReg() &&
964	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
965	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /)) {
966	// c.ld $rd, ${imm}(${rs1})
967	OutInst.setOpcode(RISCV::C_LD);
968	// Operand: rd
969	OutInst.addOperand(Op: MI.getOperand(i: `0`));
970	// Operand: rs1
971	OutInst.addOperand(Op: MI.getOperand(i: `1`));
972	// Operand: imm
973	OutInst.addOperand(Op: MI.getOperand(i: `2`));
974	OutInst.setLoc(MI.getLoc());
975	return true;
976	} // if
977	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
978	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
979	MI.getOperand(i: `0`).isReg() &&
980	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
981	MI.getOperand(i: `1`).isReg() &&
982	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
983	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm9_lsb000 /)) {
984	// c.ldsp $rd, ${imm}(${rs1})
985	OutInst.setOpcode(RISCV::C_LDSP);
986	// Operand: rd
987	OutInst.addOperand(Op: MI.getOperand(i: `0`));
988	// Operand: rs1
989	OutInst.addOperand(Op: MI.getOperand(i: `1`));
990	// Operand: imm
991	OutInst.addOperand(Op: MI.getOperand(i: `2`));
992	OutInst.setLoc(MI.getLoc());
993	return true;
994	} // if
995	break;
996	} // case LD
997	case RISCV::LD_RV32: {
998	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
999	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1000	MI.getOperand(i: `0`).isReg() &&
1001	RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1002	MI.getOperand(i: `1`).isReg() &&
1003	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1004	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm9_lsb000 /)) {
1005	// c.ldsp $rd, ${imm}(${rs1})
1006	OutInst.setOpcode(RISCV::C_LDSP_RV32);
1007	// Operand: rd
1008	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1009	// Operand: rs1
1010	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1011	// Operand: imm
1012	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1013	OutInst.setLoc(MI.getLoc());
1014	return true;
1015	} // if
1016	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
1017	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1018	MI.getOperand(i: `0`).isReg() &&
1019	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1020	MI.getOperand(i: `1`).isReg() &&
1021	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1022	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /)) {
1023	// c.ld $rd, ${imm}(${rs1})
1024	OutInst.setOpcode(RISCV::C_LD_RV32);
1025	// Operand: rd
1026	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1027	// Operand: rs1
1028	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1029	// Operand: imm
1030	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1031	OutInst.setLoc(MI.getLoc());
1032	return true;
1033	} // if
1034	break;
1035	} // case LD_RV32
1036	case RISCV::LH: {
1037	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1038	MI.getOperand(i: `0`).isReg() &&
1039	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1040	MI.getOperand(i: `1`).isReg() &&
1041	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1042	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /)) {
1043	// c.lh $rd, ${imm}(${rs1})
1044	OutInst.setOpcode(RISCV::C_LH);
1045	// Operand: rd
1046	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1047	// Operand: rs1
1048	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1049	// Operand: imm
1050	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1051	OutInst.setLoc(MI.getLoc());
1052	return true;
1053	} // if
1054	break;
1055	} // case LH
1056	case RISCV::LHU: {
1057	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1058	MI.getOperand(i: `0`).isReg() &&
1059	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1060	MI.getOperand(i: `1`).isReg() &&
1061	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1062	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /)) {
1063	// c.lhu $rd, ${imm}(${rs1})
1064	OutInst.setOpcode(RISCV::C_LHU);
1065	// Operand: rd
1066	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1067	// Operand: rs1
1068	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1069	// Operand: imm
1070	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1071	OutInst.setLoc(MI.getLoc());
1072	return true;
1073	} // if
1074	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1075	MI.getOperand(i: `0`).isReg() &&
1076	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1077	MI.getOperand(i: `1`).isReg() &&
1078	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1079	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm6_lsb0 /)) {
1080	// qk.c.lhu $rd, ${imm}(${rs1})
1081	OutInst.setOpcode(RISCV::QK_C_LHU);
1082	// Operand: rd
1083	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1084	// Operand: rs1
1085	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1086	// Operand: imm
1087	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1088	OutInst.setLoc(MI.getLoc());
1089	return true;
1090	} // if
1091	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1092	MI.getOperand(i: `0`).isReg() &&
1093	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1094	MI.getOperand(i: `1`).isReg() &&
1095	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1096	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `17` / uimm5_lsb0 /)) {
1097	// qk.c.lhusp $rd_rs2, ${imm}(${rs1})
1098	OutInst.setOpcode(RISCV::QK_C_LHUSP);
1099	// Operand: rd_rs2
1100	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1101	// Operand: rs1
1102	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1103	// Operand: imm
1104	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1105	OutInst.setLoc(MI.getLoc());
1106	return true;
1107	} // if
1108	break;
1109	} // case LHU
1110	case RISCV::LH_INX: {
1111	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1112	MI.getOperand(i: `0`).isReg() &&
1113	RISCVMCRegisterClasses[RISCV::GPRF16CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1114	MI.getOperand(i: `1`).isReg() &&
1115	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1116	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /)) {
1117	// c.lh $rd, ${imm}(${rs1})
1118	OutInst.setOpcode(RISCV::C_LH_INX);
1119	// Operand: rd
1120	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1121	// Operand: rs1
1122	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1123	// Operand: imm
1124	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1125	OutInst.setLoc(MI.getLoc());
1126	return true;
1127	} // if
1128	break;
1129	} // case LH_INX
1130	case RISCV::LUI: {
1131	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1132	MI.getOperand(i: `0`).isReg() &&
1133	RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1134	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `18` / c_lui_imm /)) {
1135	// c.lui $rd, $imm
1136	OutInst.setOpcode(RISCV::C_LUI);
1137	// Operand: rd
1138	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1139	// Operand: imm
1140	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1141	OutInst.setLoc(MI.getLoc());
1142	return true;
1143	} // if
1144	break;
1145	} // case LUI
1146	case RISCV::LW: {
1147	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1148	MI.getOperand(i: `0`).isReg() &&
1149	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1150	MI.getOperand(i: `1`).isReg() &&
1151	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1152	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm7_lsb00 /)) {
1153	// c.lw $rd, ${imm}(${rs1})
1154	OutInst.setOpcode(RISCV::C_LW);
1155	// Operand: rd
1156	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1157	// Operand: rs1
1158	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1159	// Operand: imm
1160	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1161	OutInst.setLoc(MI.getLoc());
1162	return true;
1163	} // if
1164	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1165	MI.getOperand(i: `0`).isReg() &&
1166	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1167	MI.getOperand(i: `1`).isReg() &&
1168	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1169	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm8_lsb00 /)) {
1170	// c.lwsp $rd, ${imm}(${rs1})
1171	OutInst.setOpcode(RISCV::C_LWSP);
1172	// Operand: rd
1173	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1174	// Operand: rs1
1175	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1176	// Operand: imm
1177	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1178	OutInst.setLoc(MI.getLoc());
1179	return true;
1180	} // if
1181	break;
1182	} // case LW
1183	case RISCV::LW_INX: {
1184	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1185	MI.getOperand(i: `0`).isReg() &&
1186	RISCVMCRegisterClasses[RISCV::GPRF32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1187	MI.getOperand(i: `1`).isReg() &&
1188	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1189	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm7_lsb00 /)) {
1190	// c.lw $rd, ${imm}(${rs1})
1191	OutInst.setOpcode(RISCV::C_LW_INX);
1192	// Operand: rd
1193	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1194	// Operand: rs1
1195	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1196	// Operand: imm
1197	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1198	OutInst.setLoc(MI.getLoc());
1199	return true;
1200	} // if
1201	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1202	MI.getOperand(i: `0`).isReg() &&
1203	RISCVMCRegisterClasses[RISCV::GPRF32NoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1204	MI.getOperand(i: `1`).isReg() &&
1205	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1206	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm8_lsb00 /)) {
1207	// c.lwsp $rd, ${imm}(${rs1})
1208	OutInst.setOpcode(RISCV::C_LWSP_INX);
1209	// Operand: rd
1210	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1211	// Operand: rs1
1212	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1213	// Operand: imm
1214	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1215	OutInst.setLoc(MI.getLoc());
1216	return true;
1217	} // if
1218	break;
1219	} // case LW_INX
1220	case RISCV::MUL: {
1221	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1222	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
1223	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1224	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1225	MI.getOperand(i: `1`).isReg() &&
1226	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1227	MI.getOperand(i: `2`).isReg() &&
1228	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
1229	// c.mul $rd, $rs2
1230	OutInst.setOpcode(RISCV::C_MUL);
1231	// Operand: rd_wb
1232	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1233	// Operand: rd
1234	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1235	// Operand: rs2
1236	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1237	OutInst.setLoc(MI.getLoc());
1238	return true;
1239	} // if
1240	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1241	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
1242	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
1243	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1244	MI.getOperand(i: `2`).isReg() &&
1245	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
1246	MI.getOperand(i: `1`).isReg() &&
1247	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
1248	// c.mul $rd, $rs2
1249	OutInst.setOpcode(RISCV::C_MUL);
1250	// Operand: rd_wb
1251	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1252	// Operand: rd
1253	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1254	// Operand: rs2
1255	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1256	OutInst.setLoc(MI.getLoc());
1257	return true;
1258	} // if
1259	break;
1260	} // case MUL
1261	case RISCV::OR: {
1262	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1263	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1264	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1265	MI.getOperand(i: `1`).isReg() &&
1266	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1267	MI.getOperand(i: `2`).isReg() &&
1268	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
1269	// c.or $rd, $rs2
1270	OutInst.setOpcode(RISCV::C_OR);
1271	// Operand: rd_wb
1272	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1273	// Operand: rd
1274	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1275	// Operand: rs2
1276	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1277	OutInst.setLoc(MI.getLoc());
1278	return true;
1279	} // if
1280	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1281	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
1282	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1283	MI.getOperand(i: `2`).isReg() &&
1284	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
1285	MI.getOperand(i: `1`).isReg() &&
1286	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
1287	// c.or $rd, $rs2
1288	OutInst.setOpcode(RISCV::C_OR);
1289	// Operand: rd_wb
1290	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1291	// Operand: rd
1292	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1293	// Operand: rs2
1294	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1295	OutInst.setLoc(MI.getLoc());
1296	return true;
1297	} // if
1298	break;
1299	} // case OR
1300	case RISCV::QC_EXTU: {
1301	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
1302	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1303	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1304	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1305	MI.getOperand(i: `3`).isImm() &&
1306	(MI.getOperand(i: `3`).getImm() == `0`) &&
1307	MI.getOperand(i: `1`).isReg() &&
1308	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1309	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19` / uimm5ge6_plus1 /)) {
1310	// qc.c.extu $rd, $width
1311	OutInst.setOpcode(RISCV::QC_C_EXTU);
1312	// Operand: rd_wb
1313	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1314	// Operand: rd
1315	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1316	// Operand: width
1317	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1318	OutInst.setLoc(MI.getLoc());
1319	return true;
1320	} // if
1321	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
1322	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
1323	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1324	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1325	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1326	MI.getOperand(i: `2`).isImm() &&
1327	(MI.getOperand(i: `2`).getImm() == `1`) &&
1328	MI.getOperand(i: `1`).isReg() &&
1329	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1330	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `3`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /)) {
1331	// qc.c.bexti $rs1, $shamt
1332	OutInst.setOpcode(RISCV::QC_C_BEXTI);
1333	// Operand: rd
1334	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1335	// Operand: rs1
1336	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1337	// Operand: shamt
1338	OutInst.addOperand(Op: MI.getOperand(i: `3`));
1339	OutInst.setLoc(MI.getLoc());
1340	return true;
1341	} // if
1342	break;
1343	} // case QC_EXTU
1344	case RISCV::QC_E_ADDAI: {
1345	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1346	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1347	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1348	MI.getOperand(i: `0`).isReg() &&
1349	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1350	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm6nonzero /) &&
1351	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
1352	// c.addi $rd, $imm
1353	OutInst.setOpcode(RISCV::C_ADDI);
1354	// Operand: rd_wb
1355	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1356	// Operand: rd
1357	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1358	// Operand: imm
1359	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1360	OutInst.setLoc(MI.getLoc());
1361	return true;
1362	} // if
1363	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1364	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1365	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1366	MI.getOperand(i: `0`).isReg() &&
1367	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
1368	MI.getOperand(i: `1`).isReg() &&
1369	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
1370	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4` / simm10_lsb0000nonzero /)) {
1371	// c.addi16sp $rd, $imm
1372	OutInst.setOpcode(RISCV::C_ADDI16SP);
1373	// Operand: rd_wb
1374	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1375	// Operand: rd
1376	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1377	// Operand: imm
1378	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1379	OutInst.setLoc(MI.getLoc());
1380	return true;
1381	} // if
1382	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1383	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1384	MI.getOperand(i: `0`).isReg() &&
1385	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1386	MI.getOperand(i: `0`).isReg() &&
1387	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1388	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1389	// addi $rd, $rs1, $imm12
1390	OutInst.setOpcode(RISCV::ADDI);
1391	// Operand: rd
1392	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1393	// Operand: rs1
1394	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1395	// Operand: imm12
1396	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1397	OutInst.setLoc(MI.getLoc());
1398	return true;
1399	} // if
1400	break;
1401	} // case QC_E_ADDAI
1402	case RISCV::QC_E_ADDI: {
1403	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1404	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1405	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1406	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1407	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1408	MI.getOperand(i: `1`).isReg() &&
1409	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1410	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm6nonzero /) &&
1411	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
1412	// c.addi $rd, $imm
1413	OutInst.setOpcode(RISCV::C_ADDI);
1414	// Operand: rd_wb
1415	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1416	// Operand: rd
1417	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1418	// Operand: imm
1419	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1420	OutInst.setLoc(MI.getLoc());
1421	return true;
1422	} // if
1423	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1424	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1425	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1426	MI.getOperand(i: `2`).isImm() &&
1427	(MI.getOperand(i: `2`).getImm() == `0`) &&
1428	MI.getOperand(i: `0`).isReg() &&
1429	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1430	MI.getOperand(i: `1`).isReg() &&
1431	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
1432	// c.mv $rs1, $rs2
1433	OutInst.setOpcode(RISCV::C_MV);
1434	// Operand: rs1
1435	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1436	// Operand: rs2
1437	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1438	OutInst.setLoc(MI.getLoc());
1439	return true;
1440	} // if
1441	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1442	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1443	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1444	MI.getOperand(i: `0`).isReg() &&
1445	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
1446	MI.getOperand(i: `1`).isReg() &&
1447	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
1448	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4` / simm10_lsb0000nonzero /)) {
1449	// c.addi16sp $rd, $imm
1450	OutInst.setOpcode(RISCV::C_ADDI16SP);
1451	// Operand: rd_wb
1452	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1453	// Operand: rd
1454	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1455	// Operand: imm
1456	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1457	OutInst.setLoc(MI.getLoc());
1458	return true;
1459	} // if
1460	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1461	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1462	MI.getOperand(i: `0`).isReg() &&
1463	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1464	MI.getOperand(i: `1`).isReg() &&
1465	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1466	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1467	// addi $rd, $rs1, $imm12
1468	OutInst.setOpcode(RISCV::ADDI);
1469	// Operand: rd
1470	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1471	// Operand: rs1
1472	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1473	// Operand: imm12
1474	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1475	OutInst.setLoc(MI.getLoc());
1476	return true;
1477	} // if
1478	break;
1479	} // case QC_E_ADDI
1480	case RISCV::QC_E_ANDAI: {
1481	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1482	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1483	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1484	MI.getOperand(i: `0`).isReg() &&
1485	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1486	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
1487	// c.andi $rs1, $imm
1488	OutInst.setOpcode(RISCV::C_ANDI);
1489	// Operand: rd
1490	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1491	// Operand: rs1
1492	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1493	// Operand: imm
1494	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1495	OutInst.setLoc(MI.getLoc());
1496	return true;
1497	} // if
1498	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1499	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1500	MI.getOperand(i: `0`).isReg() &&
1501	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1502	MI.getOperand(i: `0`).isReg() &&
1503	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1504	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1505	// andi $rd, $rs1, $imm12
1506	OutInst.setOpcode(RISCV::ANDI);
1507	// Operand: rd
1508	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1509	// Operand: rs1
1510	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1511	// Operand: imm12
1512	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1513	OutInst.setLoc(MI.getLoc());
1514	return true;
1515	} // if
1516	break;
1517	} // case QC_E_ANDAI
1518	case RISCV::QC_E_ANDI: {
1519	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1520	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1521	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1522	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
1523	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1524	MI.getOperand(i: `1`).isReg() &&
1525	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1526	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm6 /)) {
1527	// c.andi $rs1, $imm
1528	OutInst.setOpcode(RISCV::C_ANDI);
1529	// Operand: rd
1530	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1531	// Operand: rs1
1532	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1533	// Operand: imm
1534	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1535	OutInst.setLoc(MI.getLoc());
1536	return true;
1537	} // if
1538	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1539	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1540	MI.getOperand(i: `0`).isReg() &&
1541	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1542	MI.getOperand(i: `1`).isReg() &&
1543	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1544	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1545	// andi $rd, $rs1, $imm12
1546	OutInst.setOpcode(RISCV::ANDI);
1547	// Operand: rd
1548	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1549	// Operand: rs1
1550	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1551	// Operand: imm12
1552	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1553	OutInst.setLoc(MI.getLoc());
1554	return true;
1555	} // if
1556	break;
1557	} // case QC_E_ANDI
1558	case RISCV::QC_E_BEQI: {
1559	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1560	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1561	MI.getOperand(i: `0`).isReg() &&
1562	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1563	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `21` / simm5nonzero /) &&
1564	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / bare_simm13_lsb0 /)) {
1565	// qc.beqi $rs1, $rs2, $imm12
1566	OutInst.setOpcode(RISCV::QC_BEQI);
1567	// Operand: rs1
1568	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1569	// Operand: rs2
1570	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1571	// Operand: imm12
1572	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1573	OutInst.setLoc(MI.getLoc());
1574	return true;
1575	} // if
1576	break;
1577	} // case QC_E_BEQI
1578	case RISCV::QC_E_BGEI: {
1579	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1580	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1581	MI.getOperand(i: `0`).isReg() &&
1582	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1583	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `21` / simm5nonzero /) &&
1584	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / bare_simm13_lsb0 /)) {
1585	// qc.bgei $rs1, $rs2, $imm12
1586	OutInst.setOpcode(RISCV::QC_BGEI);
1587	// Operand: rs1
1588	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1589	// Operand: rs2
1590	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1591	// Operand: imm12
1592	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1593	OutInst.setLoc(MI.getLoc());
1594	return true;
1595	} // if
1596	break;
1597	} // case QC_E_BGEI
1598	case RISCV::QC_E_BGEUI: {
1599	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1600	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1601	MI.getOperand(i: `0`).isReg() &&
1602	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1603	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `23` / uimm5nonzero /) &&
1604	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / bare_simm13_lsb0 /)) {
1605	// qc.bgeui $rs1, $rs2, $imm12
1606	OutInst.setOpcode(RISCV::QC_BGEUI);
1607	// Operand: rs1
1608	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1609	// Operand: rs2
1610	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1611	// Operand: imm12
1612	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1613	OutInst.setLoc(MI.getLoc());
1614	return true;
1615	} // if
1616	break;
1617	} // case QC_E_BGEUI
1618	case RISCV::QC_E_BLTI: {
1619	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1620	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1621	MI.getOperand(i: `0`).isReg() &&
1622	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1623	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `21` / simm5nonzero /) &&
1624	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / bare_simm13_lsb0 /)) {
1625	// qc.blti $rs1, $rs2, $imm12
1626	OutInst.setOpcode(RISCV::QC_BLTI);
1627	// Operand: rs1
1628	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1629	// Operand: rs2
1630	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1631	// Operand: imm12
1632	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1633	OutInst.setLoc(MI.getLoc());
1634	return true;
1635	} // if
1636	break;
1637	} // case QC_E_BLTI
1638	case RISCV::QC_E_BLTUI: {
1639	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1640	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1641	MI.getOperand(i: `0`).isReg() &&
1642	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1643	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `23` / uimm5nonzero /) &&
1644	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / bare_simm13_lsb0 /)) {
1645	// qc.bltui $rs1, $rs2, $imm12
1646	OutInst.setOpcode(RISCV::QC_BLTUI);
1647	// Operand: rs1
1648	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1649	// Operand: rs2
1650	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1651	// Operand: imm12
1652	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1653	OutInst.setLoc(MI.getLoc());
1654	return true;
1655	} // if
1656	break;
1657	} // case QC_E_BLTUI
1658	case RISCV::QC_E_BNEI: {
1659	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1660	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1661	MI.getOperand(i: `0`).isReg() &&
1662	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1663	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `21` / simm5nonzero /) &&
1664	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / bare_simm13_lsb0 /)) {
1665	// qc.bnei $rs1, $rs2, $imm12
1666	OutInst.setOpcode(RISCV::QC_BNEI);
1667	// Operand: rs1
1668	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1669	// Operand: rs2
1670	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1671	// Operand: imm12
1672	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1673	OutInst.setLoc(MI.getLoc());
1674	return true;
1675	} // if
1676	break;
1677	} // case QC_E_BNEI
1678	case RISCV::QC_E_J: {
1679	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1680	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1681	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1682	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `11` / bare_simm12_lsb0 /)) {
1683	// c.j $offset
1684	OutInst.setOpcode(RISCV::C_J);
1685	// Operand: offset
1686	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1687	OutInst.setLoc(MI.getLoc());
1688	return true;
1689	} // if
1690	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1691	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1692	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `24` / simm21_lsb0_jal /)) {
1693	// jal $rd, $imm20
1694	OutInst.setOpcode(RISCV::JAL);
1695	// Operand: rd
1696	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
1697	// Operand: imm20
1698	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1699	OutInst.setLoc(MI.getLoc());
1700	return true;
1701	} // if
1702	break;
1703	} // case QC_E_J
1704	case RISCV::QC_E_JAL: {
1705	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1706	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1707	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1708	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `11` / bare_simm12_lsb0 /)) {
1709	// c.jal $offset
1710	OutInst.setOpcode(RISCV::C_JAL);
1711	// Operand: offset
1712	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1713	OutInst.setLoc(MI.getLoc());
1714	return true;
1715	} // if
1716	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1717	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1718	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `24` / simm21_lsb0_jal /)) {
1719	// jal $rd, $imm20
1720	OutInst.setOpcode(RISCV::JAL);
1721	// Operand: rd
1722	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
1723	// Operand: imm20
1724	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1725	OutInst.setLoc(MI.getLoc());
1726	return true;
1727	} // if
1728	break;
1729	} // case QC_E_JAL
1730	case RISCV::QC_E_LB: {
1731	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1732	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1733	MI.getOperand(i: `0`).isReg() &&
1734	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1735	MI.getOperand(i: `1`).isReg() &&
1736	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1737	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1738	// lb $rd, ${imm12}(${rs1})
1739	OutInst.setOpcode(RISCV::LB);
1740	// Operand: rd
1741	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1742	// Operand: rs1
1743	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1744	// Operand: imm12
1745	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1746	OutInst.setLoc(MI.getLoc());
1747	return true;
1748	} // if
1749	break;
1750	} // case QC_E_LB
1751	case RISCV::QC_E_LBU: {
1752	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1753	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1754	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1755	MI.getOperand(i: `0`).isReg() &&
1756	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1757	MI.getOperand(i: `1`).isReg() &&
1758	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1759	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm2 /)) {
1760	// c.lbu $rd, ${imm}(${rs1})
1761	OutInst.setOpcode(RISCV::C_LBU);
1762	// Operand: rd
1763	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1764	// Operand: rs1
1765	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1766	// Operand: imm
1767	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1768	OutInst.setLoc(MI.getLoc());
1769	return true;
1770	} // if
1771	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1772	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1773	MI.getOperand(i: `0`).isReg() &&
1774	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1775	MI.getOperand(i: `1`).isReg() &&
1776	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1777	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1778	// lbu $rd, ${imm12}(${rs1})
1779	OutInst.setOpcode(RISCV::LBU);
1780	// Operand: rd
1781	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1782	// Operand: rs1
1783	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1784	// Operand: imm12
1785	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1786	OutInst.setLoc(MI.getLoc());
1787	return true;
1788	} // if
1789	break;
1790	} // case QC_E_LBU
1791	case RISCV::QC_E_LH: {
1792	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1793	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1794	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1795	MI.getOperand(i: `0`).isReg() &&
1796	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1797	MI.getOperand(i: `1`).isReg() &&
1798	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1799	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /)) {
1800	// c.lh $rd, ${imm}(${rs1})
1801	OutInst.setOpcode(RISCV::C_LH);
1802	// Operand: rd
1803	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1804	// Operand: rs1
1805	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1806	// Operand: imm
1807	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1808	OutInst.setLoc(MI.getLoc());
1809	return true;
1810	} // if
1811	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1812	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1813	MI.getOperand(i: `0`).isReg() &&
1814	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1815	MI.getOperand(i: `1`).isReg() &&
1816	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1817	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1818	// lh $rd, ${imm12}(${rs1})
1819	OutInst.setOpcode(RISCV::LH);
1820	// Operand: rd
1821	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1822	// Operand: rs1
1823	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1824	// Operand: imm12
1825	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1826	OutInst.setLoc(MI.getLoc());
1827	return true;
1828	} // if
1829	break;
1830	} // case QC_E_LH
1831	case RISCV::QC_E_LHU: {
1832	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1833	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1834	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1835	MI.getOperand(i: `0`).isReg() &&
1836	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1837	MI.getOperand(i: `1`).isReg() &&
1838	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1839	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /)) {
1840	// c.lhu $rd, ${imm}(${rs1})
1841	OutInst.setOpcode(RISCV::C_LHU);
1842	// Operand: rd
1843	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1844	// Operand: rs1
1845	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1846	// Operand: imm
1847	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1848	OutInst.setLoc(MI.getLoc());
1849	return true;
1850	} // if
1851	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1852	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1853	MI.getOperand(i: `0`).isReg() &&
1854	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1855	MI.getOperand(i: `1`).isReg() &&
1856	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1857	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1858	// lhu $rd, ${imm12}(${rs1})
1859	OutInst.setOpcode(RISCV::LHU);
1860	// Operand: rd
1861	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1862	// Operand: rs1
1863	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1864	// Operand: imm12
1865	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1866	OutInst.setLoc(MI.getLoc());
1867	return true;
1868	} // if
1869	break;
1870	} // case QC_E_LHU
1871	case RISCV::QC_E_LI: {
1872	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
1873	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1874	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1875	MI.getOperand(i: `0`).isReg() &&
1876	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1877	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `3` / simm6 /)) {
1878	// c.li $rd, $imm
1879	OutInst.setOpcode(RISCV::C_LI);
1880	// Operand: rd
1881	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1882	// Operand: imm
1883	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1884	OutInst.setLoc(MI.getLoc());
1885	return true;
1886	} // if
1887	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
1888	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1889	MI.getOperand(i: `0`).isReg() &&
1890	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1891	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `25` / simm20_li /)) {
1892	// qc.li $rd, $imm20
1893	OutInst.setOpcode(RISCV::QC_LI);
1894	// Operand: rd
1895	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1896	// Operand: imm20
1897	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1898	OutInst.setLoc(MI.getLoc());
1899	return true;
1900	} // if
1901	break;
1902	} // case QC_E_LI
1903	case RISCV::QC_E_LW: {
1904	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1905	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1906	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1907	MI.getOperand(i: `0`).isReg() &&
1908	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1909	MI.getOperand(i: `1`).isReg() &&
1910	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1911	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm7_lsb00 /)) {
1912	// c.lw $rd, ${imm}(${rs1})
1913	OutInst.setOpcode(RISCV::C_LW);
1914	// Operand: rd
1915	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1916	// Operand: rs1
1917	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1918	// Operand: imm
1919	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1920	OutInst.setLoc(MI.getLoc());
1921	return true;
1922	} // if
1923	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1924	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1925	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1926	MI.getOperand(i: `0`).isReg() &&
1927	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1928	MI.getOperand(i: `1`).isReg() &&
1929	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1930	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm8_lsb00 /)) {
1931	// c.lwsp $rd, ${imm}(${rs1})
1932	OutInst.setOpcode(RISCV::C_LWSP);
1933	// Operand: rd
1934	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1935	// Operand: rs1
1936	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1937	// Operand: imm
1938	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1939	OutInst.setLoc(MI.getLoc());
1940	return true;
1941	} // if
1942	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1943	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1944	MI.getOperand(i: `0`).isReg() &&
1945	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1946	MI.getOperand(i: `1`).isReg() &&
1947	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1948	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1949	// lw $rd, ${imm12}(${rs1})
1950	OutInst.setOpcode(RISCV::LW);
1951	// Operand: rd
1952	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1953	// Operand: rs1
1954	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1955	// Operand: imm12
1956	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1957	OutInst.setLoc(MI.getLoc());
1958	return true;
1959	} // if
1960	break;
1961	} // case QC_E_LW
1962	case RISCV::QC_E_ORAI: {
1963	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1964	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1965	MI.getOperand(i: `0`).isReg() &&
1966	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1967	MI.getOperand(i: `0`).isReg() &&
1968	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1969	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1970	// ori $rd, $rs1, $imm12
1971	OutInst.setOpcode(RISCV::ORI);
1972	// Operand: rd
1973	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1974	// Operand: rs1
1975	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1976	// Operand: imm12
1977	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1978	OutInst.setLoc(MI.getLoc());
1979	return true;
1980	} // if
1981	break;
1982	} // case QC_E_ORAI
1983	case RISCV::QC_E_ORI: {
1984	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1985	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1986	MI.getOperand(i: `0`).isReg() &&
1987	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1988	MI.getOperand(i: `1`).isReg() &&
1989	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1990	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
1991	// ori $rd, $rs1, $imm12
1992	OutInst.setOpcode(RISCV::ORI);
1993	// Operand: rd
1994	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1995	// Operand: rs1
1996	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1997	// Operand: imm12
1998	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1999	OutInst.setLoc(MI.getLoc());
2000	return true;
2001	} // if
2002	break;
2003	} // case QC_E_ORI
2004	case RISCV::QC_E_SB: {
2005	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2006	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2007	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2008	MI.getOperand(i: `0`).isReg() &&
2009	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2010	MI.getOperand(i: `1`).isReg() &&
2011	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2012	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm2 /)) {
2013	// c.sb $rs2, ${imm}(${rs1})
2014	OutInst.setOpcode(RISCV::C_SB);
2015	// Operand: rs2
2016	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2017	// Operand: rs1
2018	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2019	// Operand: imm
2020	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2021	OutInst.setLoc(MI.getLoc());
2022	return true;
2023	} // if
2024	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2025	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2026	MI.getOperand(i: `0`).isReg() &&
2027	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2028	MI.getOperand(i: `1`).isReg() &&
2029	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2030	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
2031	// sb $rs2, ${imm12}(${rs1})
2032	OutInst.setOpcode(RISCV::SB);
2033	// Operand: rs2
2034	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2035	// Operand: rs1
2036	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2037	// Operand: imm12
2038	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2039	OutInst.setLoc(MI.getLoc());
2040	return true;
2041	} // if
2042	break;
2043	} // case QC_E_SB
2044	case RISCV::QC_E_SH: {
2045	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2046	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2047	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2048	MI.getOperand(i: `0`).isReg() &&
2049	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2050	MI.getOperand(i: `1`).isReg() &&
2051	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2052	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /)) {
2053	// c.sh $rs2, ${imm}(${rs1})
2054	OutInst.setOpcode(RISCV::C_SH);
2055	// Operand: rs2
2056	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2057	// Operand: rs1
2058	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2059	// Operand: imm
2060	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2061	OutInst.setLoc(MI.getLoc());
2062	return true;
2063	} // if
2064	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2065	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2066	MI.getOperand(i: `0`).isReg() &&
2067	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2068	MI.getOperand(i: `1`).isReg() &&
2069	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2070	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
2071	// sh $rs2, ${imm12}(${rs1})
2072	OutInst.setOpcode(RISCV::SH);
2073	// Operand: rs2
2074	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2075	// Operand: rs1
2076	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2077	// Operand: imm12
2078	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2079	OutInst.setLoc(MI.getLoc());
2080	return true;
2081	} // if
2082	break;
2083	} // case QC_E_SH
2084	case RISCV::QC_E_SW: {
2085	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2086	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2087	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2088	MI.getOperand(i: `0`).isReg() &&
2089	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2090	MI.getOperand(i: `1`).isReg() &&
2091	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2092	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm7_lsb00 /)) {
2093	// c.sw $rs2, ${imm}(${rs1})
2094	OutInst.setOpcode(RISCV::C_SW);
2095	// Operand: rs2
2096	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2097	// Operand: rs1
2098	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2099	// Operand: imm
2100	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2101	OutInst.setLoc(MI.getLoc());
2102	return true;
2103	} // if
2104	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2105	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2106	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2107	MI.getOperand(i: `0`).isReg() &&
2108	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2109	MI.getOperand(i: `1`).isReg() &&
2110	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2111	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm8_lsb00 /)) {
2112	// c.swsp $rs2, ${imm}(${rs1})
2113	OutInst.setOpcode(RISCV::C_SWSP);
2114	// Operand: rs2
2115	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2116	// Operand: rs1
2117	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2118	// Operand: imm
2119	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2120	OutInst.setLoc(MI.getLoc());
2121	return true;
2122	} // if
2123	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
2124	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2125	MI.getOperand(i: `0`).isReg() &&
2126	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2127	MI.getOperand(i: `1`).isReg() &&
2128	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2129	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
2130	// sw $rs2, ${imm12}(${rs1})
2131	OutInst.setOpcode(RISCV::SW);
2132	// Operand: rs2
2133	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2134	// Operand: rs1
2135	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2136	// Operand: imm12
2137	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2138	OutInst.setLoc(MI.getLoc());
2139	return true;
2140	} // if
2141	break;
2142	} // case QC_E_SW
2143	case RISCV::QC_E_XORAI: {
2144	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
2145	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2146	MI.getOperand(i: `0`).isReg() &&
2147	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2148	MI.getOperand(i: `0`).isReg() &&
2149	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2150	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
2151	// xori $rd, $rs1, $imm12
2152	OutInst.setOpcode(RISCV::XORI);
2153	// Operand: rd
2154	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2155	// Operand: rs1
2156	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2157	// Operand: imm12
2158	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2159	OutInst.setLoc(MI.getLoc());
2160	return true;
2161	} // if
2162	break;
2163	} // case QC_E_XORAI
2164	case RISCV::QC_E_XORI: {
2165	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
2166	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2167	MI.getOperand(i: `0`).isReg() &&
2168	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2169	MI.getOperand(i: `1`).isReg() &&
2170	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2171	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / simm12_lo /)) {
2172	// xori $rd, $rs1, $imm12
2173	OutInst.setOpcode(RISCV::XORI);
2174	// Operand: rd
2175	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2176	// Operand: rs1
2177	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2178	// Operand: imm12
2179	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2180	OutInst.setLoc(MI.getLoc());
2181	return true;
2182	} // if
2183	break;
2184	} // case QC_E_XORI
2185	case RISCV::QC_LI: {
2186	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
2187	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2188	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2189	MI.getOperand(i: `0`).isReg() &&
2190	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2191	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `3` / simm6 /)) {
2192	// c.li $rd, $imm
2193	OutInst.setOpcode(RISCV::C_LI);
2194	// Operand: rd
2195	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2196	// Operand: imm
2197	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2198	OutInst.setLoc(MI.getLoc());
2199	return true;
2200	} // if
2201	break;
2202	} // case QC_LI
2203	case RISCV::QC_MULIADD: {
2204	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2205	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2206	MI.getOperand(i: `0`).isReg() &&
2207	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2208	MI.getOperand(i: `2`).isReg() &&
2209	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2210	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `3`), STI, PredicateIndex: `13` / uimm5 /)) {
2211	// qc.c.muliadd $rd, $rs1, $uimm
2212	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2213	// Operand: rd_wb
2214	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2215	// Operand: rd
2216	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2217	// Operand: rs1
2218	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2219	// Operand: uimm
2220	OutInst.addOperand(Op: MI.getOperand(i: `3`));
2221	OutInst.setLoc(MI.getLoc());
2222	return true;
2223	} // if
2224	break;
2225	} // case QC_MULIADD
2226	case RISCV::QC_MVEQI: {
2227	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
2228	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2229	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2230	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2231	MI.getOperand(i: `3`).isImm() &&
2232	(MI.getOperand(i: `3`).getImm() == `0`) &&
2233	MI.getOperand(i: `2`).isReg() &&
2234	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2235	MI.getOperand(i: `4`).isReg() &&
2236	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `4`).getReg())) {
2237	// qc.c.mveqz $rd, $rs1
2238	OutInst.setOpcode(RISCV::QC_C_MVEQZ);
2239	// Operand: rd_wb
2240	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2241	// Operand: rd
2242	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2243	// Operand: rs1
2244	OutInst.addOperand(Op: MI.getOperand(i: `4`));
2245	OutInst.setLoc(MI.getLoc());
2246	return true;
2247	} // if
2248	break;
2249	} // case QC_MVEQI
2250	case RISCV::QC_MVLTUI: {
2251	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
2252	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2253	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2254	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2255	MI.getOperand(i: `3`).isImm() &&
2256	(MI.getOperand(i: `3`).getImm() == `1`) &&
2257	MI.getOperand(i: `2`).isReg() &&
2258	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2259	MI.getOperand(i: `4`).isReg() &&
2260	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `4`).getReg())) {
2261	// qc.c.mveqz $rd, $rs1
2262	OutInst.setOpcode(RISCV::QC_C_MVEQZ);
2263	// Operand: rd_wb
2264	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2265	// Operand: rd
2266	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2267	// Operand: rs1
2268	OutInst.addOperand(Op: MI.getOperand(i: `4`));
2269	OutInst.setLoc(MI.getLoc());
2270	return true;
2271	} // if
2272	break;
2273	} // case QC_MVLTUI
2274	case RISCV::QC_SYNC: {
2275	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2276	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2277	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26` / uimm5slist /)) {
2278	// qc.c.sync $slist
2279	OutInst.setOpcode(RISCV::QC_C_SYNC);
2280	// Operand: slist
2281	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2282	OutInst.setLoc(MI.getLoc());
2283	return true;
2284	} // if
2285	break;
2286	} // case QC_SYNC
2287	case RISCV::QC_SYNCR: {
2288	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2289	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2290	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26` / uimm5slist /)) {
2291	// qc.c.syncr $slist
2292	OutInst.setOpcode(RISCV::QC_C_SYNCR);
2293	// Operand: slist
2294	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2295	OutInst.setLoc(MI.getLoc());
2296	return true;
2297	} // if
2298	break;
2299	} // case QC_SYNCR
2300	case RISCV::QC_SYNCWF: {
2301	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2302	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2303	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26` / uimm5slist /)) {
2304	// qc.c.syncwf $slist
2305	OutInst.setOpcode(RISCV::QC_C_SYNCWF);
2306	// Operand: slist
2307	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2308	OutInst.setLoc(MI.getLoc());
2309	return true;
2310	} // if
2311	break;
2312	} // case QC_SYNCWF
2313	case RISCV::QC_SYNCWL: {
2314	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2315	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2316	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26` / uimm5slist /)) {
2317	// qc.c.syncwl $slist
2318	OutInst.setOpcode(RISCV::QC_C_SYNCWL);
2319	// Operand: slist
2320	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2321	OutInst.setLoc(MI.getLoc());
2322	return true;
2323	} // if
2324	break;
2325	} // case QC_SYNCWL
2326	case RISCV::SB: {
2327	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2328	MI.getOperand(i: `0`).isReg() &&
2329	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2330	MI.getOperand(i: `1`).isReg() &&
2331	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2332	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12` / uimm2 /)) {
2333	// c.sb $rs2, ${imm}(${rs1})
2334	OutInst.setOpcode(RISCV::C_SB);
2335	// Operand: rs2
2336	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2337	// Operand: rs1
2338	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2339	// Operand: imm
2340	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2341	OutInst.setLoc(MI.getLoc());
2342	return true;
2343	} // if
2344	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2345	MI.getOperand(i: `0`).isReg() &&
2346	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2347	MI.getOperand(i: `1`).isReg() &&
2348	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2349	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13` / uimm5 /)) {
2350	// qk.c.sb $rs2, ${imm}(${rs1})
2351	OutInst.setOpcode(RISCV::QK_C_SB);
2352	// Operand: rs2
2353	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2354	// Operand: rs1
2355	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2356	// Operand: imm
2357	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2358	OutInst.setLoc(MI.getLoc());
2359	return true;
2360	} // if
2361	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2362	MI.getOperand(i: `0`).isReg() &&
2363	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2364	MI.getOperand(i: `1`).isReg() &&
2365	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2366	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm4 /)) {
2367	// qk.c.sbsp $rd_rs2, ${imm}(${rs1})
2368	OutInst.setOpcode(RISCV::QK_C_SBSP);
2369	// Operand: rd_rs2
2370	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2371	// Operand: rs1
2372	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2373	// Operand: imm
2374	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2375	OutInst.setLoc(MI.getLoc());
2376	return true;
2377	} // if
2378	break;
2379	} // case SB
2380	case RISCV::SD: {
2381	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2382	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2383	MI.getOperand(i: `0`).isReg() &&
2384	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2385	MI.getOperand(i: `1`).isReg() &&
2386	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2387	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /)) {
2388	// c.sd $rs2, ${imm}(${rs1})
2389	OutInst.setOpcode(RISCV::C_SD);
2390	// Operand: rs2
2391	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2392	// Operand: rs1
2393	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2394	// Operand: imm
2395	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2396	OutInst.setLoc(MI.getLoc());
2397	return true;
2398	} // if
2399	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2400	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2401	MI.getOperand(i: `0`).isReg() &&
2402	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2403	MI.getOperand(i: `1`).isReg() &&
2404	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2405	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm9_lsb000 /)) {
2406	// c.sdsp $rs2, ${imm}(${rs1})
2407	OutInst.setOpcode(RISCV::C_SDSP);
2408	// Operand: rs2
2409	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2410	// Operand: rs1
2411	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2412	// Operand: imm
2413	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2414	OutInst.setLoc(MI.getLoc());
2415	return true;
2416	} // if
2417	break;
2418	} // case SD
2419	case RISCV::SD_RV32: {
2420	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
2421	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2422	MI.getOperand(i: `0`).isReg() &&
2423	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2424	MI.getOperand(i: `1`).isReg() &&
2425	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2426	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm9_lsb000 /)) {
2427	// c.sdsp $rs2, ${imm}(${rs1})
2428	OutInst.setOpcode(RISCV::C_SDSP_RV32);
2429	// Operand: rs2
2430	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2431	// Operand: rs1
2432	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2433	// Operand: imm
2434	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2435	OutInst.setLoc(MI.getLoc());
2436	return true;
2437	} // if
2438	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
2439	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2440	MI.getOperand(i: `0`).isReg() &&
2441	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2442	MI.getOperand(i: `1`).isReg() &&
2443	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2444	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7` / uimm8_lsb000 /)) {
2445	// c.sd $rs2, ${imm}(${rs1})
2446	OutInst.setOpcode(RISCV::C_SD_RV32);
2447	// Operand: rs2
2448	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2449	// Operand: rs1
2450	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2451	// Operand: imm
2452	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2453	OutInst.setLoc(MI.getLoc());
2454	return true;
2455	} // if
2456	break;
2457	} // case SD_RV32
2458	case RISCV::SEXT_B: {
2459	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2460	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2461	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2462	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2463	MI.getOperand(i: `1`).isReg() &&
2464	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2465	// c.sext.b $rd
2466	OutInst.setOpcode(RISCV::C_SEXT_B);
2467	// Operand: rd_wb
2468	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2469	// Operand: rd
2470	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2471	OutInst.setLoc(MI.getLoc());
2472	return true;
2473	} // if
2474	break;
2475	} // case SEXT_B
2476	case RISCV::SEXT_H: {
2477	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2478	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2479	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2480	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2481	MI.getOperand(i: `1`).isReg() &&
2482	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2483	// c.sext.h $rd
2484	OutInst.setOpcode(RISCV::C_SEXT_H);
2485	// Operand: rd_wb
2486	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2487	// Operand: rd
2488	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2489	OutInst.setLoc(MI.getLoc());
2490	return true;
2491	} // if
2492	break;
2493	} // case SEXT_H
2494	case RISCV::SH: {
2495	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2496	MI.getOperand(i: `0`).isReg() &&
2497	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2498	MI.getOperand(i: `1`).isReg() &&
2499	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2500	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /)) {
2501	// c.sh $rs2, ${imm}(${rs1})
2502	OutInst.setOpcode(RISCV::C_SH);
2503	// Operand: rs2
2504	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2505	// Operand: rs1
2506	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2507	// Operand: imm
2508	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2509	OutInst.setLoc(MI.getLoc());
2510	return true;
2511	} // if
2512	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2513	MI.getOperand(i: `0`).isReg() &&
2514	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2515	MI.getOperand(i: `1`).isReg() &&
2516	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2517	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16` / uimm6_lsb0 /)) {
2518	// qk.c.sh $rs2, ${imm}(${rs1})
2519	OutInst.setOpcode(RISCV::QK_C_SH);
2520	// Operand: rs2
2521	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2522	// Operand: rs1
2523	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2524	// Operand: imm
2525	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2526	OutInst.setLoc(MI.getLoc());
2527	return true;
2528	} // if
2529	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2530	MI.getOperand(i: `0`).isReg() &&
2531	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2532	MI.getOperand(i: `1`).isReg() &&
2533	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2534	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `17` / uimm5_lsb0 /)) {
2535	// qk.c.shsp $rd_rs2, ${imm}(${rs1})
2536	OutInst.setOpcode(RISCV::QK_C_SHSP);
2537	// Operand: rd_rs2
2538	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2539	// Operand: rs1
2540	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2541	// Operand: imm
2542	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2543	OutInst.setLoc(MI.getLoc());
2544	return true;
2545	} // if
2546	break;
2547	} // case SH
2548	case RISCV::SH1ADD: {
2549	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2550	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2551	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2552	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2553	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2554	MI.getOperand(i: `2`).isReg() &&
2555	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2556	MI.getOperand(i: `1`).isReg() &&
2557	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2558	RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: `2`), STI, PredicateIndex: `13` / uimm5 /)) {
2559	// qc.c.muliadd $rd, $rs1, $uimm
2560	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2561	// Operand: rd_wb
2562	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2563	// Operand: rd
2564	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2565	// Operand: rs1
2566	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2567	// Operand: uimm
2568	OutInst.addOperand(Op: MCOperand::createImm(Val: `2`));
2569	OutInst.setLoc(MI.getLoc());
2570	return true;
2571	} // if
2572	break;
2573	} // case SH1ADD
2574	case RISCV::SH2ADD: {
2575	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2576	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2577	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2578	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2579	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2580	MI.getOperand(i: `2`).isReg() &&
2581	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2582	MI.getOperand(i: `1`).isReg() &&
2583	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2584	RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: `4`), STI, PredicateIndex: `13` / uimm5 /)) {
2585	// qc.c.muliadd $rd, $rs1, $uimm
2586	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2587	// Operand: rd_wb
2588	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2589	// Operand: rd
2590	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2591	// Operand: rs1
2592	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2593	// Operand: uimm
2594	OutInst.addOperand(Op: MCOperand::createImm(Val: `4`));
2595	OutInst.setLoc(MI.getLoc());
2596	return true;
2597	} // if
2598	break;
2599	} // case SH2ADD
2600	case RISCV::SH3ADD: {
2601	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2602	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
2603	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2604	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2605	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2606	MI.getOperand(i: `2`).isReg() &&
2607	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2608	MI.getOperand(i: `1`).isReg() &&
2609	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2610	RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: `8`), STI, PredicateIndex: `13` / uimm5 /)) {
2611	// qc.c.muliadd $rd, $rs1, $uimm
2612	OutInst.setOpcode(RISCV::QC_C_MULIADD);
2613	// Operand: rd_wb
2614	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2615	// Operand: rd
2616	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2617	// Operand: rs1
2618	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2619	// Operand: uimm
2620	OutInst.addOperand(Op: MCOperand::createImm(Val: `8`));
2621	OutInst.setLoc(MI.getLoc());
2622	return true;
2623	} // if
2624	break;
2625	} // case SH3ADD
2626	case RISCV::SH_INX: {
2627	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2628	MI.getOperand(i: `0`).isReg() &&
2629	RISCVMCRegisterClasses[RISCV::GPRF16CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2630	MI.getOperand(i: `1`).isReg() &&
2631	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2632	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /)) {
2633	// c.sh $rs2, ${imm}(${rs1})
2634	OutInst.setOpcode(RISCV::C_SH_INX);
2635	// Operand: rs2
2636	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2637	// Operand: rs1
2638	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2639	// Operand: imm
2640	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2641	OutInst.setLoc(MI.getLoc());
2642	return true;
2643	} // if
2644	break;
2645	} // case SH_INX
2646	case RISCV::SLLI: {
2647	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2648	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2649	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2650	MI.getOperand(i: `1`).isReg() &&
2651	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2652	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /) &&
2653	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimmlog2xlen /)) {
2654	// c.slli $rd, $imm
2655	OutInst.setOpcode(RISCV::C_SLLI);
2656	// Operand: rd_wb
2657	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2658	// Operand: rd
2659	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2660	// Operand: imm
2661	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2662	OutInst.setLoc(MI.getLoc());
2663	return true;
2664	} // if
2665	break;
2666	} // case SLLI
2667	case RISCV::SRAI: {
2668	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2669	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2670	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2671	MI.getOperand(i: `1`).isReg() &&
2672	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2673	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /) &&
2674	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimmlog2xlen /)) {
2675	// c.srai $rs1, $imm
2676	OutInst.setOpcode(RISCV::C_SRAI);
2677	// Operand: rd
2678	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2679	// Operand: rs1
2680	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2681	// Operand: imm
2682	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2683	OutInst.setLoc(MI.getLoc());
2684	return true;
2685	} // if
2686	break;
2687	} // case SRAI
2688	case RISCV::SRLI: {
2689	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2690	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2691	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2692	MI.getOperand(i: `1`).isReg() &&
2693	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2694	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6` / uimmlog2xlennonzero /) &&
2695	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimmlog2xlen /)) {
2696	// c.srli $rs1, $imm
2697	OutInst.setOpcode(RISCV::C_SRLI);
2698	// Operand: rd
2699	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2700	// Operand: rs1
2701	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2702	// Operand: imm
2703	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2704	OutInst.setLoc(MI.getLoc());
2705	return true;
2706	} // if
2707	break;
2708	} // case SRLI
2709	case RISCV::SSPOPCHK: {
2710	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2711	MI.getOperand(i: `0`).isReg() &&
2712	(MI.getOperand(i: `0`).getReg() == RISCV::X5)) {
2713	// c.sspopchk $rs1
2714	OutInst.setOpcode(RISCV::C_SSPOPCHK);
2715	// Operand: rs1
2716	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
2717	OutInst.setLoc(MI.getLoc());
2718	return true;
2719	} // if
2720	break;
2721	} // case SSPOPCHK
2722	case RISCV::SSPUSH: {
2723	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2724	MI.getOperand(i: `0`).isReg() &&
2725	(MI.getOperand(i: `0`).getReg() == RISCV::X1)) {
2726	// c.sspush $rs1
2727	OutInst.setOpcode(RISCV::C_SSPUSH);
2728	// Operand: rs1
2729	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
2730	OutInst.setLoc(MI.getLoc());
2731	return true;
2732	} // if
2733	break;
2734	} // case SSPUSH
2735	case RISCV::SUB: {
2736	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2737	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2738	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2739	MI.getOperand(i: `1`).isReg() &&
2740	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2741	MI.getOperand(i: `2`).isReg() &&
2742	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2743	// c.sub $rd, $rs2
2744	OutInst.setOpcode(RISCV::C_SUB);
2745	// Operand: rd_wb
2746	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2747	// Operand: rd
2748	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2749	// Operand: rs2
2750	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2751	OutInst.setLoc(MI.getLoc());
2752	return true;
2753	} // if
2754	break;
2755	} // case SUB
2756	case RISCV::SUBW: {
2757	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2758	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2759	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2760	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2761	MI.getOperand(i: `1`).isReg() &&
2762	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2763	MI.getOperand(i: `2`).isReg() &&
2764	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2765	// c.subw $rd, $rs2
2766	OutInst.setOpcode(RISCV::C_SUBW);
2767	// Operand: rd_wb
2768	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2769	// Operand: rd
2770	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2771	// Operand: rs2
2772	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2773	OutInst.setLoc(MI.getLoc());
2774	return true;
2775	} // if
2776	break;
2777	} // case SUBW
2778	case RISCV::SW: {
2779	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2780	MI.getOperand(i: `0`).isReg() &&
2781	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2782	MI.getOperand(i: `1`).isReg() &&
2783	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2784	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm7_lsb00 /)) {
2785	// c.sw $rs2, ${imm}(${rs1})
2786	OutInst.setOpcode(RISCV::C_SW);
2787	// Operand: rs2
2788	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2789	// Operand: rs1
2790	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2791	// Operand: imm
2792	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2793	OutInst.setLoc(MI.getLoc());
2794	return true;
2795	} // if
2796	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2797	MI.getOperand(i: `0`).isReg() &&
2798	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2799	MI.getOperand(i: `1`).isReg() &&
2800	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2801	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm8_lsb00 /)) {
2802	// c.swsp $rs2, ${imm}(${rs1})
2803	OutInst.setOpcode(RISCV::C_SWSP);
2804	// Operand: rs2
2805	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2806	// Operand: rs1
2807	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2808	// Operand: imm
2809	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2810	OutInst.setLoc(MI.getLoc());
2811	return true;
2812	} // if
2813	break;
2814	} // case SW
2815	case RISCV::SW_INX: {
2816	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2817	MI.getOperand(i: `0`).isReg() &&
2818	RISCVMCRegisterClasses[RISCV::GPRF32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2819	MI.getOperand(i: `1`).isReg() &&
2820	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2821	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm7_lsb00 /)) {
2822	// c.sw $rs2, ${imm}(${rs1})
2823	OutInst.setOpcode(RISCV::C_SW_INX);
2824	// Operand: rs2
2825	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2826	// Operand: rs1
2827	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2828	// Operand: imm
2829	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2830	OutInst.setLoc(MI.getLoc());
2831	return true;
2832	} // if
2833	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2834	MI.getOperand(i: `0`).isReg() &&
2835	RISCVMCRegisterClasses[RISCV::GPRF32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2836	MI.getOperand(i: `1`).isReg() &&
2837	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2838	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm8_lsb00 /)) {
2839	// c.swsp $rs2, ${imm}(${rs1})
2840	OutInst.setOpcode(RISCV::C_SWSP_INX);
2841	// Operand: rs2
2842	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2843	// Operand: rs1
2844	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2845	// Operand: imm
2846	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2847	OutInst.setLoc(MI.getLoc());
2848	return true;
2849	} // if
2850	break;
2851	} // case SW_INX
2852	case RISCV::UNIMP: {
2853	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
2854	// c.unimp
2855	OutInst.setOpcode(RISCV::C_UNIMP);
2856	OutInst.setLoc(MI.getLoc());
2857	return true;
2858	} // if
2859	break;
2860	} // case UNIMP
2861	case RISCV::XOR: {
2862	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2863	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2864	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2865	MI.getOperand(i: `1`).isReg() &&
2866	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2867	MI.getOperand(i: `2`).isReg() &&
2868	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2869	// c.xor $rd, $rs2
2870	OutInst.setOpcode(RISCV::C_XOR);
2871	// Operand: rd_wb
2872	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2873	// Operand: rd
2874	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2875	// Operand: rs2
2876	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2877	OutInst.setLoc(MI.getLoc());
2878	return true;
2879	} // if
2880	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2881	MI.getOperand(i: `2`).isReg() && MI.getOperand(i: `0`).isReg() &&
2882	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2883	MI.getOperand(i: `2`).isReg() &&
2884	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2885	MI.getOperand(i: `1`).isReg() &&
2886	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2887	// c.xor $rd, $rs2
2888	OutInst.setOpcode(RISCV::C_XOR);
2889	// Operand: rd_wb
2890	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2891	// Operand: rd
2892	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2893	// Operand: rs2
2894	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2895	OutInst.setLoc(MI.getLoc());
2896	return true;
2897	} // if
2898	break;
2899	} // case XOR
2900	case RISCV::XORI: {
2901	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2902	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2903	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2904	MI.getOperand(i: `2`).isImm() &&
2905	(MI.getOperand(i: `2`).getImm() == -`1`) &&
2906	MI.getOperand(i: `1`).isReg() &&
2907	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2908	// c.not $rd
2909	OutInst.setOpcode(RISCV::C_NOT);
2910	// Operand: rd_wb
2911	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2912	// Operand: rd
2913	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2914	OutInst.setLoc(MI.getLoc());
2915	return true;
2916	} // if
2917	break;
2918	} // case XORI
2919	case RISCV::ZEXT_H_RV32: {
2920	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2921	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2922	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2923	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2924	MI.getOperand(i: `1`).isReg() &&
2925	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2926	// c.zext.h $rd
2927	OutInst.setOpcode(RISCV::C_ZEXT_H);
2928	// Operand: rd_wb
2929	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2930	// Operand: rd
2931	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2932	OutInst.setLoc(MI.getLoc());
2933	return true;
2934	} // if
2935	break;
2936	} // case ZEXT_H_RV32
2937	case RISCV::ZEXT_H_RV64: {
2938	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2939	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2940	MI.getOperand(i: `1`).isReg() && MI.getOperand(i: `0`).isReg() &&
2941	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2942	MI.getOperand(i: `1`).isReg() &&
2943	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2944	// c.zext.h $rd
2945	OutInst.setOpcode(RISCV::C_ZEXT_H);
2946	// Operand: rd_wb
2947	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2948	// Operand: rd
2949	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2950	OutInst.setLoc(MI.getLoc());
2951	return true;
2952	} // if
2953	break;
2954	} // case ZEXT_H_RV64
2955	} // switch
2956	return false;
2957	}
2958
2959	#endif // GEN_COMPRESS_INSTR
2960
2961	#ifdef GEN_UNCOMPRESS_INSTR
2962	#undef GEN_UNCOMPRESS_INSTR
2963
2964	static bool RISCVValidateMCOperandForUncompress(const MCOperand &MCOp,
2965	const MCSubtargetInfo &STI,
2966	unsigned PredicateIndex) {
2967	switch (PredicateIndex) {
2968	default:
2969	llvm_unreachable("Unknown MCOperandPredicate kind");
2970	break;
2971	case `1`: {
2972	// simm6nonzero
2973	int64_t Imm;
2974	if (MCOp.evaluateAsConstantImm(Imm))
2975	return (Imm != `0`) && isInt<`6`>(x: Imm);
2976	return MCOp.isBareSymbolRef();
2977	}
2978	case `2`: {
2979	// simm12_lo
2980	int64_t Imm;
2981	if (MCOp.evaluateAsConstantImm(Imm))
2982	return isInt<`12`>(x: Imm);
2983	return MCOp.isBareSymbolRef();
2984	}
2985	case `3`: {
2986	// simm10_lsb0000nonzero
2987	int64_t Imm;
2988	if (!MCOp.evaluateAsConstantImm(Imm))
2989	return false;
2990	return isShiftedInt<`6`, `4`>(x: Imm) && (Imm != `0`);
2991	}
2992	case `4`: {
2993	// uimm10_lsb00nonzero
2994	int64_t Imm;
2995	if (!MCOp.evaluateAsConstantImm(Imm))
2996	return false;
2997	return isShiftedUInt<`8`, `2`>(x: Imm) && (Imm != `0`);
2998	}
2999	case `5`: {
3000	// simm6
3001	int64_t Imm;
3002	if (MCOp.evaluateAsConstantImm(Imm))
3003	return isInt<`6`>(x: Imm);
3004	return MCOp.isBareSymbolRef();
3005	}
3006	case `6`: {
3007	// bare_simm9_lsb0
3008	int64_t Imm;
3009	if (MCOp.evaluateAsConstantImm(Imm))
3010	return isShiftedInt<`8`, `1`>(x: Imm);
3011	return MCOp.isBareSymbolRef();
3012	}
3013	case `7`: {
3014	// bare_simm13_lsb0
3015	int64_t Imm;
3016	if (MCOp.evaluateAsConstantImm(Imm))
3017	return isShiftedInt<`12`, `1`>(x: Imm);
3018	return MCOp.isBareSymbolRef();
3019	}
3020	case `8`: {
3021	// uimm8_lsb000
3022	int64_t Imm;
3023	if (!MCOp.evaluateAsConstantImm(Imm))
3024	return false;
3025	return isShiftedUInt<`5`, `3`>(x: Imm);
3026	}
3027	case `9`: {
3028	// uimm9_lsb000
3029	int64_t Imm;
3030	if (!MCOp.evaluateAsConstantImm(Imm))
3031	return false;
3032	return isShiftedUInt<`6`, `3`>(x: Imm);
3033	}
3034	case `10`: {
3035	// uimm7_lsb00
3036	int64_t Imm;
3037	if (!MCOp.evaluateAsConstantImm(Imm))
3038	return false;
3039	return isShiftedUInt<`5`, `2`>(x: Imm);
3040	}
3041	case `11`: {
3042	// uimm8_lsb00
3043	int64_t Imm;
3044	if (!MCOp.evaluateAsConstantImm(Imm))
3045	return false;
3046	return isShiftedUInt<`6`, `2`>(x: Imm);
3047	}
3048	case `12`: {
3049	// bare_simm12_lsb0
3050	int64_t Imm;
3051	if (MCOp.evaluateAsConstantImm(Imm))
3052	return isShiftedInt<`11`, `1`>(x: Imm);
3053	return MCOp.isBareSymbolRef();
3054	}
3055	case `13`: {
3056	// simm21_lsb0_jal
3057	int64_t Imm;
3058	if (MCOp.evaluateAsConstantImm(Imm))
3059	return isShiftedInt<`20`, `1`>(x: Imm);
3060	return MCOp.isBareSymbolRef();
3061	}
3062	case `14`: {
3063	// uimm2
3064	int64_t Imm;
3065	if (!MCOp.evaluateAsConstantImm(Imm))
3066	return false;
3067	return isUInt<`2`>(x: Imm);
3068	}
3069	case `15`: {
3070	// uimm2_lsb0
3071	int64_t Imm;
3072	if (!MCOp.evaluateAsConstantImm(Imm))
3073	return false;
3074	return isShiftedUInt<`1`, `1`>(x: Imm);
3075	}
3076	case `16`: {
3077	// simm20_li
3078	int64_t Imm;
3079	if (MCOp.evaluateAsConstantImm(Imm))
3080	return isInt<`20`>(x: Imm);
3081	return MCOp.isBareSymbolRef();
3082	}
3083	case `17`: {
3084	// c_lui_imm
3085	int64_t Imm;
3086	if (!MCOp.evaluateAsConstantImm(Imm))
3087	return false;
3088	return (Imm != `0`) && (isUInt<`5`>(x: Imm) \|\|
3089	(Imm >= `0xfffe0` && Imm <= `0xfffff`));
3090	}
3091	case `18`: {
3092	// uimm20_lui
3093	int64_t Imm;
3094	if (MCOp.evaluateAsConstantImm(Imm))
3095	return isUInt<`20`>(x: Imm);
3096	return MCOp.isBareSymbolRef();
3097	}
3098	case `19`: {
3099	// uimmlog2xlennonzero
3100	int64_t Imm;
3101	if (!MCOp.evaluateAsConstantImm(Imm))
3102	return false;
3103	if (STI.getTargetTriple().isArch64Bit())
3104	return isUInt<`6`>(x: Imm) && (Imm != `0`);
3105	return isUInt<`5`>(x: Imm) && (Imm != `0`);
3106	}
3107	case `20`: {
3108	// uimmlog2xlen
3109	int64_t Imm;
3110	if (!MCOp.evaluateAsConstantImm(Imm))
3111	return false;
3112	if (STI.getTargetTriple().isArch64Bit())
3113	return isUInt<`6`>(x: Imm);
3114	return isUInt<`5`>(x: Imm);
3115	}
3116	case `21`: {
3117	// uimm5ge6_plus1
3118	int64_t Imm;
3119	if (!MCOp.evaluateAsConstantImm(Imm))
3120	return false;
3121	return Imm >= `6` && Imm <= `32`;
3122	}
3123	case `22`: {
3124	// uimm5_plus1
3125	int64_t Imm;
3126	if (!MCOp.evaluateAsConstantImm(Imm))
3127	return false;
3128	return Imm >= `1` && Imm <= `32`;
3129	}
3130	case `23`: {
3131	// uimm5
3132	int64_t Imm;
3133	if (!MCOp.evaluateAsConstantImm(Imm))
3134	return false;
3135	return isUInt<`5`>(x: Imm);
3136	}
3137	case `24`: {
3138	// simm5
3139	int64_t Imm;
3140	if (MCOp.evaluateAsConstantImm(Imm))
3141	return isInt<`5`>(x: Imm);
3142	return MCOp.isBareSymbolRef();
3143	}
3144	case `25`: {
3145	// uimm5slist
3146	int64_t Imm;
3147	if (!MCOp.evaluateAsConstantImm(Imm))
3148	return false;
3149	return ((Imm == `0`) \|\| (Imm == `1`) \|\|
3150	(Imm == `2`) \|\| (Imm == `4`) \|\|
3151	(Imm == `8`) \|\| (Imm == `16`) \|\|
3152	(Imm == `15`) \|\| (Imm == `31`));
3153	}
3154	case `26`: {
3155	// uimm4
3156	int64_t Imm;
3157	if (!MCOp.evaluateAsConstantImm(Imm))
3158	return false;
3159	return isUInt<`4`>(x: Imm);
3160	}
3161	case `27`: {
3162	// uimm6_lsb0
3163	int64_t Imm;
3164	if (!MCOp.evaluateAsConstantImm(Imm))
3165	return false;
3166	return isShiftedUInt<`5`, `1`>(x: Imm);
3167	}
3168	case `28`: {
3169	// uimm5_lsb0
3170	int64_t Imm;
3171	if (!MCOp.evaluateAsConstantImm(Imm))
3172	return false;
3173	return isShiftedUInt<`4`, `1`>(x: Imm);
3174	}
3175	}
3176	}
3177
3178	static bool uncompressInst(MCInst &OutInst,
3179	const MCInst &MI,
3180	const MCSubtargetInfo &STI) {
3181	switch (MI.getOpcode()) {
3182	default: return false;
3183	case RISCV::C_ADD: {
3184	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3185	MI.getOperand(i: `0`).isReg() &&
3186	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3187	MI.getOperand(i: `0`).isReg() &&
3188	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3189	MI.getOperand(i: `2`).isReg() &&
3190	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3191	// add $rd, $rs1, $rs2
3192	OutInst.setOpcode(RISCV::ADD);
3193	// Operand: rd
3194	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3195	// Operand: rs1
3196	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3197	// Operand: rs2
3198	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3199	OutInst.setLoc(MI.getLoc());
3200	return true;
3201	} // if
3202	break;
3203	} // case C_ADD
3204	case RISCV::C_ADDI: {
3205	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3206	MI.getOperand(i: `0`).isReg() &&
3207	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3208	MI.getOperand(i: `0`).isReg() &&
3209	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3210	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1` / simm6nonzero /) &&
3211	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3212	// addi $rd, $rs1, $imm12
3213	OutInst.setOpcode(RISCV::ADDI);
3214	// Operand: rd
3215	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3216	// Operand: rs1
3217	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3218	// Operand: imm12
3219	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3220	OutInst.setLoc(MI.getLoc());
3221	return true;
3222	} // if
3223	break;
3224	} // case C_ADDI
3225	case RISCV::C_ADDI16SP: {
3226	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3227	MI.getOperand(i: `0`).isReg() &&
3228	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
3229	MI.getOperand(i: `1`).isReg() &&
3230	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
3231	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3` / simm10_lsb0000nonzero /) &&
3232	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3233	// addi $rd, $rs1, $imm12
3234	OutInst.setOpcode(RISCV::ADDI);
3235	// Operand: rd
3236	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
3237	// Operand: rs1
3238	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
3239	// Operand: imm12
3240	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3241	OutInst.setLoc(MI.getLoc());
3242	return true;
3243	} // if
3244	break;
3245	} // case C_ADDI16SP
3246	case RISCV::C_ADDI4SPN: {
3247	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3248	MI.getOperand(i: `0`).isReg() &&
3249	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3250	MI.getOperand(i: `1`).isReg() &&
3251	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3252	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4` / uimm10_lsb00nonzero /) &&
3253	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3254	// addi $rd, $rs1, $imm12
3255	OutInst.setOpcode(RISCV::ADDI);
3256	// Operand: rd
3257	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3258	// Operand: rs1
3259	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3260	// Operand: imm12
3261	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3262	OutInst.setLoc(MI.getLoc());
3263	return true;
3264	} // if
3265	break;
3266	} // case C_ADDI4SPN
3267	case RISCV::C_ADDIW: {
3268	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3269	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3270	MI.getOperand(i: `0`).isReg() &&
3271	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3272	MI.getOperand(i: `0`).isReg() &&
3273	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3274	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / simm6 /) &&
3275	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3276	// addiw $rd, $rs1, $imm12
3277	OutInst.setOpcode(RISCV::ADDIW);
3278	// Operand: rd
3279	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3280	// Operand: rs1
3281	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3282	// Operand: imm12
3283	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3284	OutInst.setLoc(MI.getLoc());
3285	return true;
3286	} // if
3287	break;
3288	} // case C_ADDIW
3289	case RISCV::C_ADDW: {
3290	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3291	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3292	MI.getOperand(i: `0`).isReg() &&
3293	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3294	MI.getOperand(i: `0`).isReg() &&
3295	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3296	MI.getOperand(i: `2`).isReg() &&
3297	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3298	// addw $rd, $rs1, $rs2
3299	OutInst.setOpcode(RISCV::ADDW);
3300	// Operand: rd
3301	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3302	// Operand: rs1
3303	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3304	// Operand: rs2
3305	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3306	OutInst.setLoc(MI.getLoc());
3307	return true;
3308	} // if
3309	break;
3310	} // case C_ADDW
3311	case RISCV::C_AND: {
3312	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3313	MI.getOperand(i: `0`).isReg() &&
3314	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3315	MI.getOperand(i: `0`).isReg() &&
3316	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3317	MI.getOperand(i: `2`).isReg() &&
3318	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3319	// and $rd, $rs1, $rs2
3320	OutInst.setOpcode(RISCV::AND);
3321	// Operand: rd
3322	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3323	// Operand: rs1
3324	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3325	// Operand: rs2
3326	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3327	OutInst.setLoc(MI.getLoc());
3328	return true;
3329	} // if
3330	break;
3331	} // case C_AND
3332	case RISCV::C_ANDI: {
3333	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3334	MI.getOperand(i: `0`).isReg() &&
3335	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3336	MI.getOperand(i: `0`).isReg() &&
3337	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3338	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5` / simm6 /) &&
3339	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3340	// andi $rd, $rs1, $imm12
3341	OutInst.setOpcode(RISCV::ANDI);
3342	// Operand: rd
3343	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3344	// Operand: rs1
3345	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3346	// Operand: imm12
3347	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3348	OutInst.setLoc(MI.getLoc());
3349	return true;
3350	} // if
3351	break;
3352	} // case C_ANDI
3353	case RISCV::C_BEQZ: {
3354	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3355	MI.getOperand(i: `0`).isReg() &&
3356	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3357	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `6` / bare_simm9_lsb0 /) &&
3358	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `7` / bare_simm13_lsb0 /)) {
3359	// beq $rs1, $rs2, $imm12
3360	OutInst.setOpcode(RISCV::BEQ);
3361	// Operand: rs1
3362	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3363	// Operand: rs2
3364	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3365	// Operand: imm12
3366	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3367	OutInst.setLoc(MI.getLoc());
3368	return true;
3369	} // if
3370	break;
3371	} // case C_BEQZ
3372	case RISCV::C_BNEZ: {
3373	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3374	MI.getOperand(i: `0`).isReg() &&
3375	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3376	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `6` / bare_simm9_lsb0 /) &&
3377	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `7` / bare_simm13_lsb0 /)) {
3378	// bne $rs1, $rs2, $imm12
3379	OutInst.setOpcode(RISCV::BNE);
3380	// Operand: rs1
3381	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3382	// Operand: rs2
3383	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3384	// Operand: imm12
3385	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3386	OutInst.setLoc(MI.getLoc());
3387	return true;
3388	} // if
3389	break;
3390	} // case C_BNEZ
3391	case RISCV::C_EBREAK: {
3392	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
3393	// ebreak
3394	OutInst.setOpcode(RISCV::EBREAK);
3395	OutInst.setLoc(MI.getLoc());
3396	return true;
3397	} // if
3398	break;
3399	} // case C_EBREAK
3400	case RISCV::C_FLD: {
3401	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3402	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3403	MI.getOperand(i: `0`).isReg() &&
3404	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3405	MI.getOperand(i: `1`).isReg() &&
3406	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3407	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
3408	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3409	// fld $rd, ${imm12}(${rs1})
3410	OutInst.setOpcode(RISCV::FLD);
3411	// Operand: rd
3412	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3413	// Operand: rs1
3414	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3415	// Operand: imm12
3416	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3417	OutInst.setLoc(MI.getLoc());
3418	return true;
3419	} // if
3420	break;
3421	} // case C_FLD
3422	case RISCV::C_FLDSP: {
3423	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3424	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3425	MI.getOperand(i: `0`).isReg() &&
3426	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3427	MI.getOperand(i: `1`).isReg() &&
3428	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3429	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
3430	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3431	// fld $rd, ${imm12}(${rs1})
3432	OutInst.setOpcode(RISCV::FLD);
3433	// Operand: rd
3434	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3435	// Operand: rs1
3436	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3437	// Operand: imm12
3438	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3439	OutInst.setLoc(MI.getLoc());
3440	return true;
3441	} // if
3442	break;
3443	} // case C_FLDSP
3444	case RISCV::C_FLW: {
3445	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3446	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3447	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3448	MI.getOperand(i: `0`).isReg() &&
3449	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3450	MI.getOperand(i: `1`).isReg() &&
3451	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3452	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm7_lsb00 /) &&
3453	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3454	// flw $rd, ${imm12}(${rs1})
3455	OutInst.setOpcode(RISCV::FLW);
3456	// Operand: rd
3457	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3458	// Operand: rs1
3459	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3460	// Operand: imm12
3461	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3462	OutInst.setLoc(MI.getLoc());
3463	return true;
3464	} // if
3465	break;
3466	} // case C_FLW
3467	case RISCV::C_FLWSP: {
3468	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3469	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3470	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3471	MI.getOperand(i: `0`).isReg() &&
3472	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3473	MI.getOperand(i: `1`).isReg() &&
3474	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3475	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm8_lsb00 /) &&
3476	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3477	// flw $rd, ${imm12}(${rs1})
3478	OutInst.setOpcode(RISCV::FLW);
3479	// Operand: rd
3480	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3481	// Operand: rs1
3482	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3483	// Operand: imm12
3484	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3485	OutInst.setLoc(MI.getLoc());
3486	return true;
3487	} // if
3488	break;
3489	} // case C_FLWSP
3490	case RISCV::C_FSD: {
3491	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3492	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3493	MI.getOperand(i: `0`).isReg() &&
3494	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3495	MI.getOperand(i: `1`).isReg() &&
3496	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3497	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
3498	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3499	// fsd $rs2, ${imm12}(${rs1})
3500	OutInst.setOpcode(RISCV::FSD);
3501	// Operand: rs2
3502	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3503	// Operand: rs1
3504	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3505	// Operand: imm12
3506	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3507	OutInst.setLoc(MI.getLoc());
3508	return true;
3509	} // if
3510	break;
3511	} // case C_FSD
3512	case RISCV::C_FSDSP: {
3513	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3514	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3515	MI.getOperand(i: `0`).isReg() &&
3516	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3517	MI.getOperand(i: `1`).isReg() &&
3518	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3519	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
3520	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3521	// fsd $rs2, ${imm12}(${rs1})
3522	OutInst.setOpcode(RISCV::FSD);
3523	// Operand: rs2
3524	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3525	// Operand: rs1
3526	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3527	// Operand: imm12
3528	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3529	OutInst.setLoc(MI.getLoc());
3530	return true;
3531	} // if
3532	break;
3533	} // case C_FSDSP
3534	case RISCV::C_FSW: {
3535	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3536	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3537	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3538	MI.getOperand(i: `0`).isReg() &&
3539	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3540	MI.getOperand(i: `1`).isReg() &&
3541	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3542	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm7_lsb00 /) &&
3543	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3544	// fsw $rs2, ${imm12}(${rs1})
3545	OutInst.setOpcode(RISCV::FSW);
3546	// Operand: rs2
3547	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3548	// Operand: rs1
3549	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3550	// Operand: imm12
3551	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3552	OutInst.setLoc(MI.getLoc());
3553	return true;
3554	} // if
3555	break;
3556	} // case C_FSW
3557	case RISCV::C_FSWSP: {
3558	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3559	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3560	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3561	MI.getOperand(i: `0`).isReg() &&
3562	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3563	MI.getOperand(i: `1`).isReg() &&
3564	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3565	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm8_lsb00 /) &&
3566	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3567	// fsw $rs2, ${imm12}(${rs1})
3568	OutInst.setOpcode(RISCV::FSW);
3569	// Operand: rs2
3570	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3571	// Operand: rs1
3572	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3573	// Operand: imm12
3574	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3575	OutInst.setLoc(MI.getLoc());
3576	return true;
3577	} // if
3578	break;
3579	} // case C_FSWSP
3580	case RISCV::C_J: {
3581	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3582	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `12` / bare_simm12_lsb0 /) &&
3583	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `13` / simm21_lsb0_jal /)) {
3584	// jal $rd, $imm20
3585	OutInst.setOpcode(RISCV::JAL);
3586	// Operand: rd
3587	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3588	// Operand: imm20
3589	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3590	OutInst.setLoc(MI.getLoc());
3591	return true;
3592	} // if
3593	break;
3594	} // case C_J
3595	case RISCV::C_JAL: {
3596	if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3597	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3598	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `12` / bare_simm12_lsb0 /) &&
3599	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `13` / simm21_lsb0_jal /)) {
3600	// jal $rd, $imm20
3601	OutInst.setOpcode(RISCV::JAL);
3602	// Operand: rd
3603	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
3604	// Operand: imm20
3605	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3606	OutInst.setLoc(MI.getLoc());
3607	return true;
3608	} // if
3609	break;
3610	} // case C_JAL
3611	case RISCV::C_JALR: {
3612	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3613	MI.getOperand(i: `0`).isReg() &&
3614	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3615	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `2` / simm12_lo /)) {
3616	// jalr $rd, ${imm12}(${rs1})
3617	OutInst.setOpcode(RISCV::JALR);
3618	// Operand: rd
3619	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
3620	// Operand: rs1
3621	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3622	// Operand: imm12
3623	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3624	OutInst.setLoc(MI.getLoc());
3625	return true;
3626	} // if
3627	break;
3628	} // case C_JALR
3629	case RISCV::C_JR: {
3630	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3631	MI.getOperand(i: `0`).isReg() &&
3632	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3633	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `2` / simm12_lo /)) {
3634	// jalr $rd, ${imm12}(${rs1})
3635	OutInst.setOpcode(RISCV::JALR);
3636	// Operand: rd
3637	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3638	// Operand: rs1
3639	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3640	// Operand: imm12
3641	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3642	OutInst.setLoc(MI.getLoc());
3643	return true;
3644	} // if
3645	break;
3646	} // case C_JR
3647	case RISCV::C_LBU: {
3648	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3649	MI.getOperand(i: `0`).isReg() &&
3650	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3651	MI.getOperand(i: `1`).isReg() &&
3652	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3653	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm2 /) &&
3654	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3655	// lbu $rd, ${imm12}(${rs1})
3656	OutInst.setOpcode(RISCV::LBU);
3657	// Operand: rd
3658	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3659	// Operand: rs1
3660	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3661	// Operand: imm12
3662	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3663	OutInst.setLoc(MI.getLoc());
3664	return true;
3665	} // if
3666	break;
3667	} // case C_LBU
3668	case RISCV::C_LD: {
3669	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3670	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3671	MI.getOperand(i: `0`).isReg() &&
3672	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3673	MI.getOperand(i: `1`).isReg() &&
3674	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3675	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
3676	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3677	// ld $rd, ${imm12}(${rs1})
3678	OutInst.setOpcode(RISCV::LD);
3679	// Operand: rd
3680	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3681	// Operand: rs1
3682	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3683	// Operand: imm12
3684	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3685	OutInst.setLoc(MI.getLoc());
3686	return true;
3687	} // if
3688	break;
3689	} // case C_LD
3690	case RISCV::C_LDSP: {
3691	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3692	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3693	MI.getOperand(i: `0`).isReg() &&
3694	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3695	MI.getOperand(i: `1`).isReg() &&
3696	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3697	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
3698	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3699	// ld $rd, ${imm12}(${rs1})
3700	OutInst.setOpcode(RISCV::LD);
3701	// Operand: rd
3702	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3703	// Operand: rs1
3704	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3705	// Operand: imm12
3706	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3707	OutInst.setLoc(MI.getLoc());
3708	return true;
3709	} // if
3710	break;
3711	} // case C_LDSP
3712	case RISCV::C_LDSP_RV32: {
3713	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
3714	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
3715	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3716	MI.getOperand(i: `0`).isReg() &&
3717	RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3718	MI.getOperand(i: `1`).isReg() &&
3719	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3720	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
3721	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3722	// ld $rd, ${imm12}(${rs1})
3723	OutInst.setOpcode(RISCV::LD_RV32);
3724	// Operand: rd
3725	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3726	// Operand: rs1
3727	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3728	// Operand: imm12
3729	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3730	OutInst.setLoc(MI.getLoc());
3731	return true;
3732	} // if
3733	break;
3734	} // case C_LDSP_RV32
3735	case RISCV::C_LD_RV32: {
3736	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
3737	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
3738	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3739	MI.getOperand(i: `0`).isReg() &&
3740	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3741	MI.getOperand(i: `1`).isReg() &&
3742	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3743	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
3744	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3745	// ld $rd, ${imm12}(${rs1})
3746	OutInst.setOpcode(RISCV::LD_RV32);
3747	// Operand: rd
3748	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3749	// Operand: rs1
3750	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3751	// Operand: imm12
3752	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3753	OutInst.setLoc(MI.getLoc());
3754	return true;
3755	} // if
3756	break;
3757	} // case C_LD_RV32
3758	case RISCV::C_LH: {
3759	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3760	MI.getOperand(i: `0`).isReg() &&
3761	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3762	MI.getOperand(i: `1`).isReg() &&
3763	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3764	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /) &&
3765	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3766	// lh $rd, ${imm12}(${rs1})
3767	OutInst.setOpcode(RISCV::LH);
3768	// Operand: rd
3769	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3770	// Operand: rs1
3771	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3772	// Operand: imm12
3773	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3774	OutInst.setLoc(MI.getLoc());
3775	return true;
3776	} // if
3777	break;
3778	} // case C_LH
3779	case RISCV::C_LHU: {
3780	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3781	MI.getOperand(i: `0`).isReg() &&
3782	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3783	MI.getOperand(i: `1`).isReg() &&
3784	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3785	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /) &&
3786	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3787	// lhu $rd, ${imm12}(${rs1})
3788	OutInst.setOpcode(RISCV::LHU);
3789	// Operand: rd
3790	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3791	// Operand: rs1
3792	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3793	// Operand: imm12
3794	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3795	OutInst.setLoc(MI.getLoc());
3796	return true;
3797	} // if
3798	break;
3799	} // case C_LHU
3800	case RISCV::C_LI: {
3801	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3802	MI.getOperand(i: `0`).isReg() &&
3803	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3804	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `5` / simm6 /) &&
3805	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `2` / simm12_lo /)) {
3806	// addi $rd, $rs1, $imm12
3807	OutInst.setOpcode(RISCV::ADDI);
3808	// Operand: rd
3809	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3810	// Operand: rs1
3811	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3812	// Operand: imm12
3813	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3814	OutInst.setLoc(MI.getLoc());
3815	return true;
3816	} // if
3817	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
3818	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3819	MI.getOperand(i: `0`).isReg() &&
3820	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3821	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `5` / simm6 /) &&
3822	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `16` / simm20_li /)) {
3823	// qc.li $rd, $imm20
3824	OutInst.setOpcode(RISCV::QC_LI);
3825	// Operand: rd
3826	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3827	// Operand: imm20
3828	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3829	OutInst.setLoc(MI.getLoc());
3830	return true;
3831	} // if
3832	break;
3833	} // case C_LI
3834	case RISCV::C_LUI: {
3835	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3836	MI.getOperand(i: `0`).isReg() &&
3837	RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3838	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `17` / c_lui_imm /) &&
3839	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `18` / uimm20_lui /)) {
3840	// lui $rd, $imm20
3841	OutInst.setOpcode(RISCV::LUI);
3842	// Operand: rd
3843	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3844	// Operand: imm20
3845	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3846	OutInst.setLoc(MI.getLoc());
3847	return true;
3848	} // if
3849	break;
3850	} // case C_LUI
3851	case RISCV::C_LW: {
3852	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3853	MI.getOperand(i: `0`).isReg() &&
3854	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3855	MI.getOperand(i: `1`).isReg() &&
3856	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3857	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm7_lsb00 /) &&
3858	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3859	// lw $rd, ${imm12}(${rs1})
3860	OutInst.setOpcode(RISCV::LW);
3861	// Operand: rd
3862	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3863	// Operand: rs1
3864	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3865	// Operand: imm12
3866	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3867	OutInst.setLoc(MI.getLoc());
3868	return true;
3869	} // if
3870	break;
3871	} // case C_LW
3872	case RISCV::C_LWSP: {
3873	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3874	MI.getOperand(i: `0`).isReg() &&
3875	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3876	MI.getOperand(i: `1`).isReg() &&
3877	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3878	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm8_lsb00 /) &&
3879	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
3880	// lw $rd, ${imm12}(${rs1})
3881	OutInst.setOpcode(RISCV::LW);
3882	// Operand: rd
3883	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3884	// Operand: rs1
3885	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3886	// Operand: imm12
3887	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3888	OutInst.setLoc(MI.getLoc());
3889	return true;
3890	} // if
3891	break;
3892	} // case C_LWSP
3893	case RISCV::C_MUL: {
3894	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3895	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
3896	MI.getOperand(i: `0`).isReg() &&
3897	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3898	MI.getOperand(i: `0`).isReg() &&
3899	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3900	MI.getOperand(i: `2`).isReg() &&
3901	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3902	// mul $rd, $rs1, $rs2
3903	OutInst.setOpcode(RISCV::MUL);
3904	// Operand: rd
3905	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3906	// Operand: rs1
3907	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3908	// Operand: rs2
3909	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3910	OutInst.setLoc(MI.getLoc());
3911	return true;
3912	} // if
3913	break;
3914	} // case C_MUL
3915	case RISCV::C_MV: {
3916	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3917	MI.getOperand(i: `0`).isReg() &&
3918	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3919	MI.getOperand(i: `1`).isReg() &&
3920	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3921	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `2` / simm12_lo /)) {
3922	// addi $rd, $rs1, $imm12
3923	OutInst.setOpcode(RISCV::ADDI);
3924	// Operand: rd
3925	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3926	// Operand: rs1
3927	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3928	// Operand: imm12
3929	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3930	OutInst.setLoc(MI.getLoc());
3931	return true;
3932	} // if
3933	break;
3934	} // case C_MV
3935	case RISCV::C_NOP: {
3936	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3937	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `2` / simm12_lo /)) {
3938	// addi $rd, $rs1, $imm12
3939	OutInst.setOpcode(RISCV::ADDI);
3940	// Operand: rd
3941	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3942	// Operand: rs1
3943	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3944	// Operand: imm12
3945	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3946	OutInst.setLoc(MI.getLoc());
3947	return true;
3948	} // if
3949	break;
3950	} // case C_NOP
3951	case RISCV::C_NOT: {
3952	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3953	MI.getOperand(i: `0`).isReg() &&
3954	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3955	MI.getOperand(i: `0`).isReg() &&
3956	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3957	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: -`1`), STI, PredicateIndex: `2` / simm12_lo /)) {
3958	// xori $rd, $rs1, $imm12
3959	OutInst.setOpcode(RISCV::XORI);
3960	// Operand: rd
3961	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3962	// Operand: rs1
3963	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3964	// Operand: imm12
3965	OutInst.addOperand(Op: MCOperand::createImm(Val: -`1`));
3966	OutInst.setLoc(MI.getLoc());
3967	return true;
3968	} // if
3969	break;
3970	} // case C_NOT
3971	case RISCV::C_OR: {
3972	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3973	MI.getOperand(i: `0`).isReg() &&
3974	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3975	MI.getOperand(i: `0`).isReg() &&
3976	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3977	MI.getOperand(i: `2`).isReg() &&
3978	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3979	// or $rd, $rs1, $rs2
3980	OutInst.setOpcode(RISCV::OR);
3981	// Operand: rd
3982	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3983	// Operand: rs1
3984	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3985	// Operand: rs2
3986	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3987	OutInst.setLoc(MI.getLoc());
3988	return true;
3989	} // if
3990	break;
3991	} // case C_OR
3992	case RISCV::C_SB: {
3993	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3994	MI.getOperand(i: `0`).isReg() &&
3995	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3996	MI.getOperand(i: `1`).isReg() &&
3997	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3998	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14` / uimm2 /) &&
3999	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4000	// sb $rs2, ${imm12}(${rs1})
4001	OutInst.setOpcode(RISCV::SB);
4002	// Operand: rs2
4003	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4004	// Operand: rs1
4005	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4006	// Operand: imm12
4007	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4008	OutInst.setLoc(MI.getLoc());
4009	return true;
4010	} // if
4011	break;
4012	} // case C_SB
4013	case RISCV::C_SD: {
4014	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4015	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4016	MI.getOperand(i: `0`).isReg() &&
4017	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4018	MI.getOperand(i: `1`).isReg() &&
4019	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4020	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
4021	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4022	// sd $rs2, ${imm12}(${rs1})
4023	OutInst.setOpcode(RISCV::SD);
4024	// Operand: rs2
4025	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4026	// Operand: rs1
4027	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4028	// Operand: imm12
4029	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4030	OutInst.setLoc(MI.getLoc());
4031	return true;
4032	} // if
4033	break;
4034	} // case C_SD
4035	case RISCV::C_SDSP: {
4036	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4037	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4038	MI.getOperand(i: `0`).isReg() &&
4039	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4040	MI.getOperand(i: `1`).isReg() &&
4041	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4042	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
4043	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4044	// sd $rs2, ${imm12}(${rs1})
4045	OutInst.setOpcode(RISCV::SD);
4046	// Operand: rs2
4047	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4048	// Operand: rs1
4049	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4050	// Operand: imm12
4051	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4052	OutInst.setLoc(MI.getLoc());
4053	return true;
4054	} // if
4055	break;
4056	} // case C_SDSP
4057	case RISCV::C_SDSP_RV32: {
4058	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
4059	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
4060	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4061	MI.getOperand(i: `0`).isReg() &&
4062	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4063	MI.getOperand(i: `1`).isReg() &&
4064	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4065	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9` / uimm9_lsb000 /) &&
4066	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4067	// sd $rs2, ${imm12}(${rs1})
4068	OutInst.setOpcode(RISCV::SD_RV32);
4069	// Operand: rs2
4070	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4071	// Operand: rs1
4072	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4073	// Operand: imm12
4074	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4075	OutInst.setLoc(MI.getLoc());
4076	return true;
4077	} // if
4078	break;
4079	} // case C_SDSP_RV32
4080	case RISCV::C_SD_RV32: {
4081	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
4082	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
4083	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4084	MI.getOperand(i: `0`).isReg() &&
4085	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4086	MI.getOperand(i: `1`).isReg() &&
4087	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4088	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8` / uimm8_lsb000 /) &&
4089	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4090	// sd $rs2, ${imm12}(${rs1})
4091	OutInst.setOpcode(RISCV::SD_RV32);
4092	// Operand: rs2
4093	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4094	// Operand: rs1
4095	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4096	// Operand: imm12
4097	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4098	OutInst.setLoc(MI.getLoc());
4099	return true;
4100	} // if
4101	break;
4102	} // case C_SD_RV32
4103	case RISCV::C_SEXT_B: {
4104	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4105	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4106	MI.getOperand(i: `0`).isReg() &&
4107	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4108	MI.getOperand(i: `0`).isReg() &&
4109	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
4110	// sext.b $rd, $rs1
4111	OutInst.setOpcode(RISCV::SEXT_B);
4112	// Operand: rd
4113	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4114	// Operand: rs1
4115	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4116	OutInst.setLoc(MI.getLoc());
4117	return true;
4118	} // if
4119	break;
4120	} // case C_SEXT_B
4121	case RISCV::C_SEXT_H: {
4122	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4123	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4124	MI.getOperand(i: `0`).isReg() &&
4125	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4126	MI.getOperand(i: `0`).isReg() &&
4127	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
4128	// sext.h $rd, $rs1
4129	OutInst.setOpcode(RISCV::SEXT_H);
4130	// Operand: rd
4131	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4132	// Operand: rs1
4133	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4134	OutInst.setLoc(MI.getLoc());
4135	return true;
4136	} // if
4137	break;
4138	} // case C_SEXT_H
4139	case RISCV::C_SH: {
4140	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4141	MI.getOperand(i: `0`).isReg() &&
4142	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4143	MI.getOperand(i: `1`).isReg() &&
4144	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4145	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15` / uimm2_lsb0 /) &&
4146	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4147	// sh $rs2, ${imm12}(${rs1})
4148	OutInst.setOpcode(RISCV::SH);
4149	// Operand: rs2
4150	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4151	// Operand: rs1
4152	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4153	// Operand: imm12
4154	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4155	OutInst.setLoc(MI.getLoc());
4156	return true;
4157	} // if
4158	break;
4159	} // case C_SH
4160	case RISCV::C_SLLI: {
4161	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4162	MI.getOperand(i: `0`).isReg() &&
4163	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4164	MI.getOperand(i: `0`).isReg() &&
4165	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4166	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19` / uimmlog2xlennonzero /) &&
4167	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlen /)) {
4168	// slli $rd, $rs1, $shamt
4169	OutInst.setOpcode(RISCV::SLLI);
4170	// Operand: rd
4171	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4172	// Operand: rs1
4173	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4174	// Operand: shamt
4175	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4176	OutInst.setLoc(MI.getLoc());
4177	return true;
4178	} // if
4179	break;
4180	} // case C_SLLI
4181	case RISCV::C_SRAI: {
4182	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4183	MI.getOperand(i: `0`).isReg() &&
4184	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4185	MI.getOperand(i: `0`).isReg() &&
4186	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4187	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19` / uimmlog2xlennonzero /) &&
4188	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlen /)) {
4189	// srai $rd, $rs1, $shamt
4190	OutInst.setOpcode(RISCV::SRAI);
4191	// Operand: rd
4192	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4193	// Operand: rs1
4194	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4195	// Operand: shamt
4196	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4197	OutInst.setLoc(MI.getLoc());
4198	return true;
4199	} // if
4200	break;
4201	} // case C_SRAI
4202	case RISCV::C_SRLI: {
4203	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4204	MI.getOperand(i: `0`).isReg() &&
4205	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4206	MI.getOperand(i: `0`).isReg() &&
4207	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4208	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19` / uimmlog2xlennonzero /) &&
4209	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlen /)) {
4210	// srli $rd, $rs1, $shamt
4211	OutInst.setOpcode(RISCV::SRLI);
4212	// Operand: rd
4213	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4214	// Operand: rs1
4215	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4216	// Operand: shamt
4217	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4218	OutInst.setLoc(MI.getLoc());
4219	return true;
4220	} // if
4221	break;
4222	} // case C_SRLI
4223	case RISCV::C_SSPOPCHK: {
4224	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
4225	STI.getFeatureBits()[RISCV::FeatureStdExtZimop] &&
4226	MI.getOperand(i: `0`).isReg() &&
4227	(MI.getOperand(i: `0`).getReg() == RISCV::X5)) {
4228	// sspopchk $rs1
4229	OutInst.setOpcode(RISCV::SSPOPCHK);
4230	// Operand: rs1
4231	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
4232	OutInst.setLoc(MI.getLoc());
4233	return true;
4234	} // if
4235	break;
4236	} // case C_SSPOPCHK
4237	case RISCV::C_SSPUSH: {
4238	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
4239	STI.getFeatureBits()[RISCV::FeatureStdExtZimop] &&
4240	MI.getOperand(i: `0`).isReg() &&
4241	(MI.getOperand(i: `0`).getReg() == RISCV::X1)) {
4242	// sspush $rs2
4243	OutInst.setOpcode(RISCV::SSPUSH);
4244	// Operand: rs2
4245	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
4246	OutInst.setLoc(MI.getLoc());
4247	return true;
4248	} // if
4249	break;
4250	} // case C_SSPUSH
4251	case RISCV::C_SUB: {
4252	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4253	MI.getOperand(i: `0`).isReg() &&
4254	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4255	MI.getOperand(i: `0`).isReg() &&
4256	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4257	MI.getOperand(i: `2`).isReg() &&
4258	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
4259	// sub $rd, $rs1, $rs2
4260	OutInst.setOpcode(RISCV::SUB);
4261	// Operand: rd
4262	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4263	// Operand: rs1
4264	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4265	// Operand: rs2
4266	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4267	OutInst.setLoc(MI.getLoc());
4268	return true;
4269	} // if
4270	break;
4271	} // case C_SUB
4272	case RISCV::C_SUBW: {
4273	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4274	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4275	MI.getOperand(i: `0`).isReg() &&
4276	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4277	MI.getOperand(i: `0`).isReg() &&
4278	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4279	MI.getOperand(i: `2`).isReg() &&
4280	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
4281	// subw $rd, $rs1, $rs2
4282	OutInst.setOpcode(RISCV::SUBW);
4283	// Operand: rd
4284	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4285	// Operand: rs1
4286	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4287	// Operand: rs2
4288	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4289	OutInst.setLoc(MI.getLoc());
4290	return true;
4291	} // if
4292	break;
4293	} // case C_SUBW
4294	case RISCV::C_SW: {
4295	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4296	MI.getOperand(i: `0`).isReg() &&
4297	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4298	MI.getOperand(i: `1`).isReg() &&
4299	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4300	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10` / uimm7_lsb00 /) &&
4301	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4302	// sw $rs2, ${imm12}(${rs1})
4303	OutInst.setOpcode(RISCV::SW);
4304	// Operand: rs2
4305	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4306	// Operand: rs1
4307	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4308	// Operand: imm12
4309	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4310	OutInst.setLoc(MI.getLoc());
4311	return true;
4312	} // if
4313	break;
4314	} // case C_SW
4315	case RISCV::C_SWSP: {
4316	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4317	MI.getOperand(i: `0`).isReg() &&
4318	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4319	MI.getOperand(i: `1`).isReg() &&
4320	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4321	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `11` / uimm8_lsb00 /) &&
4322	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4323	// sw $rs2, ${imm12}(${rs1})
4324	OutInst.setOpcode(RISCV::SW);
4325	// Operand: rs2
4326	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4327	// Operand: rs1
4328	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4329	// Operand: imm12
4330	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4331	OutInst.setLoc(MI.getLoc());
4332	return true;
4333	} // if
4334	break;
4335	} // case C_SWSP
4336	case RISCV::C_UNIMP: {
4337	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
4338	// unimp
4339	OutInst.setOpcode(RISCV::UNIMP);
4340	OutInst.setLoc(MI.getLoc());
4341	return true;
4342	} // if
4343	break;
4344	} // case C_UNIMP
4345	case RISCV::C_XOR: {
4346	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4347	MI.getOperand(i: `0`).isReg() &&
4348	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4349	MI.getOperand(i: `0`).isReg() &&
4350	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4351	MI.getOperand(i: `2`).isReg() &&
4352	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
4353	// xor $rd, $rs1, $rs2
4354	OutInst.setOpcode(RISCV::XOR);
4355	// Operand: rd
4356	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4357	// Operand: rs1
4358	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4359	// Operand: rs2
4360	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4361	OutInst.setLoc(MI.getLoc());
4362	return true;
4363	} // if
4364	break;
4365	} // case C_XOR
4366	case RISCV::C_ZEXT_B: {
4367	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4368	MI.getOperand(i: `0`).isReg() &&
4369	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4370	MI.getOperand(i: `0`).isReg() &&
4371	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4372	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `255`), STI, PredicateIndex: `2` / simm12_lo /)) {
4373	// andi $rd, $rs1, $imm12
4374	OutInst.setOpcode(RISCV::ANDI);
4375	// Operand: rd
4376	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4377	// Operand: rs1
4378	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4379	// Operand: imm12
4380	OutInst.addOperand(Op: MCOperand::createImm(Val: `255`));
4381	OutInst.setLoc(MI.getLoc());
4382	return true;
4383	} // if
4384	break;
4385	} // case C_ZEXT_B
4386	case RISCV::C_ZEXT_H: {
4387	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4388	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4389	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4390	MI.getOperand(i: `0`).isReg() &&
4391	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4392	MI.getOperand(i: `0`).isReg() &&
4393	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
4394	// zext.h $rd, $rs1
4395	OutInst.setOpcode(RISCV::ZEXT_H_RV32);
4396	// Operand: rd
4397	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4398	// Operand: rs1
4399	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4400	OutInst.setLoc(MI.getLoc());
4401	return true;
4402	} // if
4403	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4404	STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4405	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4406	MI.getOperand(i: `0`).isReg() &&
4407	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4408	MI.getOperand(i: `0`).isReg() &&
4409	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
4410	// zext.h $rd, $rs1
4411	OutInst.setOpcode(RISCV::ZEXT_H_RV64);
4412	// Operand: rd
4413	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4414	// Operand: rs1
4415	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4416	OutInst.setLoc(MI.getLoc());
4417	return true;
4418	} // if
4419	break;
4420	} // case C_ZEXT_H
4421	case RISCV::C_ZEXT_W: {
4422	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4423	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
4424	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4425	MI.getOperand(i: `0`).isReg() &&
4426	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4427	MI.getOperand(i: `0`).isReg() &&
4428	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
4429	// add.uw $rd, $rs1, $rs2
4430	OutInst.setOpcode(RISCV::ADD_UW);
4431	// Operand: rd
4432	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4433	// Operand: rs1
4434	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4435	// Operand: rs2
4436	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
4437	OutInst.setLoc(MI.getLoc());
4438	return true;
4439	} // if
4440	break;
4441	} // case C_ZEXT_W
4442	case RISCV::QC_C_BEXTI: {
4443	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
4444	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4445	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4446	MI.getOperand(i: `0`).isReg() &&
4447	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4448	MI.getOperand(i: `0`).isReg() &&
4449	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4450	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19` / uimmlog2xlennonzero /) &&
4451	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlen /)) {
4452	// bexti $rd, $rs1, $shamt
4453	OutInst.setOpcode(RISCV::BEXTI);
4454	// Operand: rd
4455	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4456	// Operand: rs1
4457	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4458	// Operand: shamt
4459	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4460	OutInst.setLoc(MI.getLoc());
4461	return true;
4462	} // if
4463	break;
4464	} // case QC_C_BEXTI
4465	case RISCV::QC_C_BSETI: {
4466	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
4467	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4468	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4469	MI.getOperand(i: `0`).isReg() &&
4470	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4471	MI.getOperand(i: `0`).isReg() &&
4472	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4473	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19` / uimmlog2xlennonzero /) &&
4474	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `20` / uimmlog2xlen /)) {
4475	// bseti $rd, $rs1, $shamt
4476	OutInst.setOpcode(RISCV::BSETI);
4477	// Operand: rd
4478	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4479	// Operand: rs1
4480	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4481	// Operand: shamt
4482	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4483	OutInst.setLoc(MI.getLoc());
4484	return true;
4485	} // if
4486	break;
4487	} // case QC_C_BSETI
4488	case RISCV::QC_C_EXTU: {
4489	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4490	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4491	MI.getOperand(i: `0`).isReg() &&
4492	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4493	MI.getOperand(i: `0`).isReg() &&
4494	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4495	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21` / uimm5ge6_plus1 /) &&
4496	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `22` / uimm5_plus1 /) &&
4497	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `23` / uimm5 /)) {
4498	// qc.extu $rd, $rs1, $width, $shamt
4499	OutInst.setOpcode(RISCV::QC_EXTU);
4500	// Operand: rd
4501	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4502	// Operand: rs1
4503	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4504	// Operand: width
4505	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4506	// Operand: shamt
4507	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
4508	OutInst.setLoc(MI.getLoc());
4509	return true;
4510	} // if
4511	break;
4512	} // case QC_C_EXTU
4513	case RISCV::QC_C_MVEQZ: {
4514	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
4515	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4516	MI.getOperand(i: `0`).isReg() &&
4517	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4518	MI.getOperand(i: `0`).isReg() &&
4519	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4520	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `24` / simm5 /) &&
4521	MI.getOperand(i: `2`).isReg() &&
4522	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
4523	// qc.mveqi $rd, $rs1, $imm, $rs3
4524	OutInst.setOpcode(RISCV::QC_MVEQI);
4525	// Operand: rd_wb
4526	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4527	// Operand: rd
4528	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4529	// Operand: rs1
4530	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4531	// Operand: imm
4532	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
4533	// Operand: rs3
4534	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4535	OutInst.setLoc(MI.getLoc());
4536	return true;
4537	} // if
4538	break;
4539	} // case QC_C_MVEQZ
4540	case RISCV::QC_C_SYNC: {
4541	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4542	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4543	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `25` / uimm5slist /) &&
4544	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `23` / uimm5 /)) {
4545	// qc.sync $imm5
4546	OutInst.setOpcode(RISCV::QC_SYNC);
4547	// Operand: imm5
4548	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4549	OutInst.setLoc(MI.getLoc());
4550	return true;
4551	} // if
4552	break;
4553	} // case QC_C_SYNC
4554	case RISCV::QC_C_SYNCR: {
4555	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4556	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4557	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `25` / uimm5slist /) &&
4558	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `23` / uimm5 /)) {
4559	// qc.syncr $imm5
4560	OutInst.setOpcode(RISCV::QC_SYNCR);
4561	// Operand: imm5
4562	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4563	OutInst.setLoc(MI.getLoc());
4564	return true;
4565	} // if
4566	break;
4567	} // case QC_C_SYNCR
4568	case RISCV::QC_C_SYNCWF: {
4569	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4570	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4571	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `25` / uimm5slist /) &&
4572	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `23` / uimm5 /)) {
4573	// qc.syncwf $imm5
4574	OutInst.setOpcode(RISCV::QC_SYNCWF);
4575	// Operand: imm5
4576	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4577	OutInst.setLoc(MI.getLoc());
4578	return true;
4579	} // if
4580	break;
4581	} // case QC_C_SYNCWF
4582	case RISCV::QC_C_SYNCWL: {
4583	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4584	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4585	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `25` / uimm5slist /) &&
4586	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `23` / uimm5 /)) {
4587	// qc.syncwl $imm5
4588	OutInst.setOpcode(RISCV::QC_SYNCWL);
4589	// Operand: imm5
4590	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4591	OutInst.setLoc(MI.getLoc());
4592	return true;
4593	} // if
4594	break;
4595	} // case QC_C_SYNCWL
4596	case RISCV::QK_C_LBU: {
4597	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4598	MI.getOperand(i: `0`).isReg() &&
4599	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4600	MI.getOperand(i: `1`).isReg() &&
4601	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4602	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm5 /) &&
4603	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4604	// lbu $rd, ${imm12}(${rs1})
4605	OutInst.setOpcode(RISCV::LBU);
4606	// Operand: rd
4607	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4608	// Operand: rs1
4609	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4610	// Operand: imm12
4611	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4612	OutInst.setLoc(MI.getLoc());
4613	return true;
4614	} // if
4615	break;
4616	} // case QK_C_LBU
4617	case RISCV::QK_C_LBUSP: {
4618	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4619	MI.getOperand(i: `0`).isReg() &&
4620	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4621	MI.getOperand(i: `1`).isReg() &&
4622	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4623	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `26` / uimm4 /) &&
4624	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4625	// lbu $rd, ${imm12}(${rs1})
4626	OutInst.setOpcode(RISCV::LBU);
4627	// Operand: rd
4628	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4629	// Operand: rs1
4630	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4631	// Operand: imm12
4632	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4633	OutInst.setLoc(MI.getLoc());
4634	return true;
4635	} // if
4636	break;
4637	} // case QK_C_LBUSP
4638	case RISCV::QK_C_LHU: {
4639	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4640	MI.getOperand(i: `0`).isReg() &&
4641	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4642	MI.getOperand(i: `1`).isReg() &&
4643	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4644	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimm6_lsb0 /) &&
4645	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4646	// lhu $rd, ${imm12}(${rs1})
4647	OutInst.setOpcode(RISCV::LHU);
4648	// Operand: rd
4649	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4650	// Operand: rs1
4651	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4652	// Operand: imm12
4653	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4654	OutInst.setLoc(MI.getLoc());
4655	return true;
4656	} // if
4657	break;
4658	} // case QK_C_LHU
4659	case RISCV::QK_C_LHUSP: {
4660	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4661	MI.getOperand(i: `0`).isReg() &&
4662	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4663	MI.getOperand(i: `1`).isReg() &&
4664	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4665	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `28` / uimm5_lsb0 /) &&
4666	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4667	// lhu $rd, ${imm12}(${rs1})
4668	OutInst.setOpcode(RISCV::LHU);
4669	// Operand: rd
4670	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4671	// Operand: rs1
4672	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4673	// Operand: imm12
4674	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4675	OutInst.setLoc(MI.getLoc());
4676	return true;
4677	} // if
4678	break;
4679	} // case QK_C_LHUSP
4680	case RISCV::QK_C_SB: {
4681	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4682	MI.getOperand(i: `0`).isReg() &&
4683	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4684	MI.getOperand(i: `1`).isReg() &&
4685	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4686	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `23` / uimm5 /) &&
4687	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4688	// sb $rs2, ${imm12}(${rs1})
4689	OutInst.setOpcode(RISCV::SB);
4690	// Operand: rs2
4691	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4692	// Operand: rs1
4693	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4694	// Operand: imm12
4695	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4696	OutInst.setLoc(MI.getLoc());
4697	return true;
4698	} // if
4699	break;
4700	} // case QK_C_SB
4701	case RISCV::QK_C_SBSP: {
4702	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4703	MI.getOperand(i: `0`).isReg() &&
4704	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4705	MI.getOperand(i: `1`).isReg() &&
4706	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4707	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `26` / uimm4 /) &&
4708	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4709	// sb $rs2, ${imm12}(${rs1})
4710	OutInst.setOpcode(RISCV::SB);
4711	// Operand: rs2
4712	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4713	// Operand: rs1
4714	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4715	// Operand: imm12
4716	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4717	OutInst.setLoc(MI.getLoc());
4718	return true;
4719	} // if
4720	break;
4721	} // case QK_C_SBSP
4722	case RISCV::QK_C_SH: {
4723	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4724	MI.getOperand(i: `0`).isReg() &&
4725	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4726	MI.getOperand(i: `1`).isReg() &&
4727	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4728	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `27` / uimm6_lsb0 /) &&
4729	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4730	// sh $rs2, ${imm12}(${rs1})
4731	OutInst.setOpcode(RISCV::SH);
4732	// Operand: rs2
4733	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4734	// Operand: rs1
4735	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4736	// Operand: imm12
4737	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4738	OutInst.setLoc(MI.getLoc());
4739	return true;
4740	} // if
4741	break;
4742	} // case QK_C_SH
4743	case RISCV::QK_C_SHSP: {
4744	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4745	MI.getOperand(i: `0`).isReg() &&
4746	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4747	MI.getOperand(i: `1`).isReg() &&
4748	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4749	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `28` / uimm5_lsb0 /) &&
4750	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2` / simm12_lo /)) {
4751	// sh $rs2, ${imm12}(${rs1})
4752	OutInst.setOpcode(RISCV::SH);
4753	// Operand: rs2
4754	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4755	// Operand: rs1
4756	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4757	// Operand: imm12
4758	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4759	OutInst.setLoc(MI.getLoc());
4760	return true;
4761	} // if
4762	break;
4763	} // case QK_C_SHSP
4764	} // switch
4765	return false;
4766	}
4767
4768	#endif // GEN_UNCOMPRESS_INSTR
4769
4770	#ifdef GEN_CHECK_COMPRESS_INSTR
4771	#undef GEN_CHECK_COMPRESS_INSTR
4772
4773	static bool RISCVValidateMachineOperand(const MachineOperand &MO,
4774	const RISCVSubtarget *Subtarget,
4775	unsigned PredicateIndex) {
4776	int64_t Imm = MO.getImm();
4777	switch (PredicateIndex) {
4778	default:
4779	llvm_unreachable("Unknown ImmLeaf Predicate kind");
4780	break;
4781	case `1`: {
4782	// simm6nonzero
4783	return (Imm != `0`) && isInt<`6`>(Imm);
4784	}
4785	case `2`: {
4786	// simm6
4787	return isInt<`6`>(Imm);
4788	}
4789	case `3`: {
4790	// simm10_lsb0000nonzero
4791	return (Imm != `0`) && isShiftedInt<`6`, `4`>(Imm);
4792	}
4793	case `4`: {
4794	// uimm10_lsb00nonzero
4795	return isShiftedUInt<`8`, `2`>(Imm) && (Imm != `0`);
4796	}
4797	case `5`: {
4798	// bare_simm9_lsb0
4799	return isShiftedInt<`8`, `1`>(Imm);
4800	}
4801	case `6`: {
4802	// uimmlog2xlennonzero
4803	if (Subtarget->is64Bit())
4804	return isUInt<`6`>(Imm) && (Imm != `0`);
4805	return isUInt<`5`>(Imm) && (Imm != `0`);
4806	}
4807	case `7`: {
4808	// uimm8_lsb000
4809	return isShiftedUInt<`5`, `3`>(Imm);
4810	}
4811	case `8`: {
4812	// uimm9_lsb000
4813	return isShiftedUInt<`6`, `3`>(Imm);
4814	}
4815	case `9`: {
4816	// uimm7_lsb00
4817	return isShiftedUInt<`5`, `2`>(Imm);
4818	}
4819	case `10`: {
4820	// uimm8_lsb00
4821	return isShiftedUInt<`6`, `2`>(Imm);
4822	}
4823	case `11`: {
4824	// bare_simm12_lsb0
4825	return isShiftedInt<`11`, `1`>(Imm);
4826	}
4827	case `12`: {
4828	// uimm2
4829	return isUInt<`2`>(Imm);
4830	}
4831	case `13`: {
4832	// uimm5
4833	return isUInt<`5`>(Imm);
4834	}
4835	case `14`: {
4836	// uimm4
4837	return isUInt<`4`>(Imm);
4838	}
4839	case `15`: {
4840	// uimm2_lsb0
4841	return isShiftedUInt<`1`, `1`>(Imm);
4842	}
4843	case `16`: {
4844	// uimm6_lsb0
4845	return isShiftedUInt<`5`, `1`>(Imm);
4846	}
4847	case `17`: {
4848	// uimm5_lsb0
4849	return isShiftedUInt<`4`, `1`>(Imm);
4850	}
4851	case `18`: {
4852	// c_lui_imm
4853	return (Imm != `0`) &&
4854	(isUInt<`5`>(Imm) \|\|
4855	(Imm >= `0xfffe0` && Imm <= `0xfffff`));
4856	}
4857	case `19`: {
4858	// uimm5ge6_plus1
4859	return Imm >= `6` && Imm <= `32`;
4860	}
4861	case `20`: {
4862	// simm12_lo
4863	return isInt<`12`>(Imm);
4864	}
4865	case `21`: {
4866	// simm5nonzero
4867	return (Imm != `0`) && isInt<`5`>(Imm);
4868	}
4869	case `22`: {
4870	// bare_simm13_lsb0
4871	return isShiftedInt<`12`, `1`>(Imm);
4872	}
4873	case `23`: {
4874	// uimm5nonzero
4875	return (Imm != `0`) && isUInt<`5`>(Imm);
4876	}
4877	case `24`: {
4878	// simm21_lsb0_jal
4879	return isShiftedInt<`20`, `1`>(Imm);
4880	}
4881	case `25`: {
4882	// simm20_li
4883	return isInt<`20`>(Imm);
4884	}
4885	case `26`: {
4886	// uimm5slist
4887	return ((Imm == `0`) \|\|
4888	(Imm == `1`) \|\|
4889	(Imm == `2`) \|\|
4890	(Imm == `4`) \|\|
4891	(Imm == `8`) \|\|
4892	(Imm == `16`) \|\|
4893	(Imm == `15`) \|\|
4894	(Imm == `31`));
4895	}
4896	case `27`: {
4897	// uimmlog2xlen
4898	if (Subtarget->is64Bit())
4899	return isUInt<`6`>(Imm);
4900	return isUInt<`5`>(Imm);
4901	}
4902	}
4903	}
4904
4905	static bool isCompressibleInst(const MachineInstr &MI,
4906	const RISCVSubtarget &STI) {
4907	switch (MI.getOpcode()) {
4908	default: return false;
4909	case RISCV::ADD: {
4910	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4911	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
4912	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4913	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4914	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
4915	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4916	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`2`).getReg())) {
4917	// c.add $rs1, $rs2
4918	// Operand: rd
4919	// Operand: rs1
4920	// Operand: rs2
4921	return true;
4922	} // if
4923	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4924	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
4925	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
4926	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4927	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`2`).getReg()) &&
4928	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4929	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
4930	// c.add $rs1, $rs2
4931	// Operand: rd
4932	// Operand: rs1
4933	// Operand: rs2
4934	return true;
4935	} // if
4936	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4937	MI.getOperand(`1`).isReg() &&
4938	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
4939	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4940	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4941	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4942	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`2`).getReg())) {
4943	// c.mv $rs1, $rs2
4944	// Operand: rs1
4945	// Operand: rs2
4946	return true;
4947	} // if
4948	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4949	MI.getOperand(`2`).isReg() &&
4950	(MI.getOperand(`2`).getReg() == RISCV::X0) &&
4951	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4952	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4953	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4954	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
4955	// c.mv $rs1, $rs2
4956	// Operand: rs1
4957	// Operand: rs2
4958	return true;
4959	} // if
4960	break;
4961	} // case ADD
4962	case RISCV::ADDI: {
4963	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4964	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
4965	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4966	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4967	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
4968	MI.getOperand(`2`).isImm() &&
4969	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `1` / simm6nonzero /) &&
4970	MI.getOperand(`2`).isImm() &&
4971	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
4972	// c.addi $rd, $imm
4973	// Operand: rd_wb
4974	// Operand: rd
4975	// Operand: imm
4976	return true;
4977	} // if
4978	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4979	MI.getOperand(`0`).isReg() &&
4980	(MI.getOperand(`0`).getReg() == RISCV::X2) &&
4981	MI.getOperand(`1`).isReg() &&
4982	(MI.getOperand(`1`).getReg() == RISCV::X2) &&
4983	MI.getOperand(`2`).isImm() &&
4984	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `3` / simm10_lsb0000nonzero /)) {
4985	// c.addi16sp $rd, $imm
4986	// Operand: rd_wb
4987	// Operand: rd
4988	// Operand: imm
4989	return true;
4990	} // if
4991	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4992	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4993	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4994	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4995	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4996	MI.getOperand(`2`).isImm() &&
4997	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `4` / uimm10_lsb00nonzero /)) {
4998	// c.addi4spn $rd, $rs1, $imm
4999	// Operand: rd
5000	// Operand: rs1
5001	// Operand: imm
5002	return true;
5003	} // if
5004	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5005	MI.getOperand(`1`).isReg() &&
5006	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5007	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5008	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5009	MI.getOperand(`2`).isImm() &&
5010	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5011	// c.li $rd, $imm
5012	// Operand: rd
5013	// Operand: imm
5014	return true;
5015	} // if
5016	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5017	MI.getOperand(`2`).isImm() &&
5018	(MI.getOperand(`2`).getImm() == `0`) &&
5019	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5020	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5021	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5022	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
5023	// c.mv $rs1, $rs2
5024	// Operand: rs1
5025	// Operand: rs2
5026	return true;
5027	} // if
5028	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5029	MI.getOperand(`0`).isReg() &&
5030	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5031	MI.getOperand(`1`).isReg() &&
5032	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5033	MI.getOperand(`2`).isImm() &&
5034	(MI.getOperand(`2`).getImm() == `0`)) {
5035	// c.nop
5036	return true;
5037	} // if
5038	break;
5039	} // case ADDI
5040	case RISCV::ADDIW: {
5041	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5042	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5043	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5044	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5045	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5046	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
5047	MI.getOperand(`2`).isImm() &&
5048	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5049	// c.addiw $rd, $imm
5050	// Operand: rd_wb
5051	// Operand: rd
5052	// Operand: imm
5053	return true;
5054	} // if
5055	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5056	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5057	MI.getOperand(`1`).isReg() &&
5058	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5059	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5060	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5061	MI.getOperand(`2`).isImm() &&
5062	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5063	// c.li $rd, $imm
5064	// Operand: rd
5065	// Operand: imm
5066	return true;
5067	} // if
5068	break;
5069	} // case ADDIW
5070	case RISCV::ADDW: {
5071	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5072	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5073	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5074	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5075	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5076	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5077	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5078	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
5079	// c.addw $rd, $rs2
5080	// Operand: rd_wb
5081	// Operand: rd
5082	// Operand: rs2
5083	return true;
5084	} // if
5085	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5086	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5087	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5088	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5089	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5090	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5091	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5092	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
5093	// c.addw $rd, $rs2
5094	// Operand: rd_wb
5095	// Operand: rd
5096	// Operand: rs2
5097	return true;
5098	} // if
5099	break;
5100	} // case ADDW
5101	case RISCV::ADD_UW: {
5102	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5103	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
5104	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5105	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5106	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5107	MI.getOperand(`2`).isReg() &&
5108	(MI.getOperand(`2`).getReg() == RISCV::X0) &&
5109	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5110	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
5111	// c.zext.w $rd
5112	// Operand: rd_wb
5113	// Operand: rd
5114	return true;
5115	} // if
5116	break;
5117	} // case ADD_UW
5118	case RISCV::AND: {
5119	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5120	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5121	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5122	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5123	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5124	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5125	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
5126	// c.and $rd, $rs2
5127	// Operand: rd_wb
5128	// Operand: rd
5129	// Operand: rs2
5130	return true;
5131	} // if
5132	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5133	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5134	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5135	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5136	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5137	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5138	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
5139	// c.and $rd, $rs2
5140	// Operand: rd_wb
5141	// Operand: rd
5142	// Operand: rs2
5143	return true;
5144	} // if
5145	break;
5146	} // case AND
5147	case RISCV::ANDI: {
5148	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5149	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5150	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5151	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5152	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5153	MI.getOperand(`2`).isImm() &&
5154	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5155	// c.andi $rs1, $imm
5156	// Operand: rd
5157	// Operand: rs1
5158	// Operand: imm
5159	return true;
5160	} // if
5161	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5162	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5163	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5164	MI.getOperand(`2`).isImm() &&
5165	(MI.getOperand(`2`).getImm() == `255`) &&
5166	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5167	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
5168	// c.zext.b $rd
5169	// Operand: rd_wb
5170	// Operand: rd
5171	return true;
5172	} // if
5173	break;
5174	} // case ANDI
5175	case RISCV::BEQ: {
5176	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5177	MI.getOperand(`1`).isReg() &&
5178	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5179	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5180	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5181	MI.getOperand(`2`).isImm() &&
5182	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5` / bare_simm9_lsb0 /)) {
5183	// c.beqz $rs1, $imm
5184	// Operand: rs1
5185	// Operand: imm
5186	return true;
5187	} // if
5188	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5189	MI.getOperand(`0`).isReg() &&
5190	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5191	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5192	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5193	MI.getOperand(`2`).isImm() &&
5194	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5` / bare_simm9_lsb0 /)) {
5195	// c.beqz $rs1, $imm
5196	// Operand: rs1
5197	// Operand: imm
5198	return true;
5199	} // if
5200	break;
5201	} // case BEQ
5202	case RISCV::BEXTI: {
5203	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
5204	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
5205	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5206	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5207	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5208	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5209	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5210	MI.getOperand(`2`).isImm() &&
5211	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /)) {
5212	// qc.c.bexti $rs1, $shamt
5213	// Operand: rd
5214	// Operand: rs1
5215	// Operand: shamt
5216	return true;
5217	} // if
5218	break;
5219	} // case BEXTI
5220	case RISCV::BNE: {
5221	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5222	MI.getOperand(`1`).isReg() &&
5223	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
5224	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5225	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5226	MI.getOperand(`2`).isImm() &&
5227	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5` / bare_simm9_lsb0 /)) {
5228	// c.bnez $rs1, $imm
5229	// Operand: rs1
5230	// Operand: imm
5231	return true;
5232	} // if
5233	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5234	MI.getOperand(`0`).isReg() &&
5235	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5236	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5237	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5238	MI.getOperand(`2`).isImm() &&
5239	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5` / bare_simm9_lsb0 /)) {
5240	// c.bnez $rs1, $imm
5241	// Operand: rs1
5242	// Operand: imm
5243	return true;
5244	} // if
5245	break;
5246	} // case BNE
5247	case RISCV::BSETI: {
5248	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
5249	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
5250	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5251	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5252	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5253	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5254	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5255	MI.getOperand(`2`).isImm() &&
5256	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /)) {
5257	// qc.c.bseti $rs1, $shamt
5258	// Operand: rd
5259	// Operand: rs1
5260	// Operand: shamt
5261	return true;
5262	} // if
5263	break;
5264	} // case BSETI
5265	case RISCV::EBREAK: {
5266	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
5267	// c.ebreak
5268	return true;
5269	} // if
5270	break;
5271	} // case EBREAK
5272	case RISCV::FLD: {
5273	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
5274	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
5275	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5276	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5277	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5278	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5279	MI.getOperand(`2`).isImm() &&
5280	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /)) {
5281	// c.fld $rd, ${imm}(${rs1})
5282	// Operand: rd
5283	// Operand: rs1
5284	// Operand: imm
5285	return true;
5286	} // if
5287	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
5288	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
5289	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5290	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5291	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5292	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5293	MI.getOperand(`2`).isImm() &&
5294	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm9_lsb000 /)) {
5295	// c.fldsp $rd, ${imm}(${rs1})
5296	// Operand: rd
5297	// Operand: rs1
5298	// Operand: imm
5299	return true;
5300	} // if
5301	break;
5302	} // case FLD
5303	case RISCV::FLW: {
5304	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
5305	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5306	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
5307	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5308	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5309	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5310	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5311	MI.getOperand(`2`).isImm() &&
5312	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm7_lsb00 /)) {
5313	// c.flw $rd, ${imm}(${rs1})
5314	// Operand: rd
5315	// Operand: rs1
5316	// Operand: imm
5317	return true;
5318	} // if
5319	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
5320	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5321	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
5322	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5323	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5324	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5325	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5326	MI.getOperand(`2`).isImm() &&
5327	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm8_lsb00 /)) {
5328	// c.flwsp $rd, ${imm}(${rs1})
5329	// Operand: rd
5330	// Operand: rs1
5331	// Operand: imm
5332	return true;
5333	} // if
5334	break;
5335	} // case FLW
5336	case RISCV::FSD: {
5337	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
5338	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
5339	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5340	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5341	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5342	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5343	MI.getOperand(`2`).isImm() &&
5344	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /)) {
5345	// c.fsd $rs2, ${imm}(${rs1})
5346	// Operand: rs2
5347	// Operand: rs1
5348	// Operand: imm
5349	return true;
5350	} // if
5351	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
5352	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
5353	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5354	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5355	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5356	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5357	MI.getOperand(`2`).isImm() &&
5358	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm9_lsb000 /)) {
5359	// c.fsdsp $rs2, ${imm}(${rs1})
5360	// Operand: rs2
5361	// Operand: rs1
5362	// Operand: imm
5363	return true;
5364	} // if
5365	break;
5366	} // case FSD
5367	case RISCV::FSW: {
5368	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
5369	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5370	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
5371	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5372	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5373	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5374	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5375	MI.getOperand(`2`).isImm() &&
5376	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm7_lsb00 /)) {
5377	// c.fsw $rs2, ${imm}(${rs1})
5378	// Operand: rs2
5379	// Operand: rs1
5380	// Operand: imm
5381	return true;
5382	} // if
5383	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
5384	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5385	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
5386	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5387	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5388	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5389	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5390	MI.getOperand(`2`).isImm() &&
5391	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm8_lsb00 /)) {
5392	// c.fswsp $rs2, ${imm}(${rs1})
5393	// Operand: rs2
5394	// Operand: rs1
5395	// Operand: imm
5396	return true;
5397	} // if
5398	break;
5399	} // case FSW
5400	case RISCV::JAL: {
5401	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5402	MI.getOperand(`0`).isReg() &&
5403	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5404	MI.getOperand(`1`).isImm() &&
5405	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `11` / bare_simm12_lsb0 /)) {
5406	// c.j $offset
5407	// Operand: offset
5408	return true;
5409	} // if
5410	if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5411	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5412	MI.getOperand(`0`).isReg() &&
5413	(MI.getOperand(`0`).getReg() == RISCV::X1) &&
5414	MI.getOperand(`1`).isImm() &&
5415	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `11` / bare_simm12_lsb0 /)) {
5416	// c.jal $offset
5417	// Operand: offset
5418	return true;
5419	} // if
5420	break;
5421	} // case JAL
5422	case RISCV::JALR: {
5423	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5424	MI.getOperand(`0`).isReg() &&
5425	(MI.getOperand(`0`).getReg() == RISCV::X1) &&
5426	MI.getOperand(`2`).isImm() &&
5427	(MI.getOperand(`2`).getImm() == `0`) &&
5428	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5429	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
5430	// c.jalr $rs1
5431	// Operand: rs1
5432	return true;
5433	} // if
5434	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5435	MI.getOperand(`0`).isReg() &&
5436	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
5437	MI.getOperand(`2`).isImm() &&
5438	(MI.getOperand(`2`).getImm() == `0`) &&
5439	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5440	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
5441	// c.jr $rs1
5442	// Operand: rs1
5443	return true;
5444	} // if
5445	break;
5446	} // case JALR
5447	case RISCV::LBU: {
5448	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5449	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5450	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5451	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5452	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5453	MI.getOperand(`2`).isImm() &&
5454	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm2 /)) {
5455	// c.lbu $rd, ${imm}(${rs1})
5456	// Operand: rd
5457	// Operand: rs1
5458	// Operand: imm
5459	return true;
5460	} // if
5461	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5462	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5463	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5464	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5465	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5466	MI.getOperand(`2`).isImm() &&
5467	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm5 /)) {
5468	// qk.c.lbu $rd, ${imm}(${rs1})
5469	// Operand: rd
5470	// Operand: rs1
5471	// Operand: imm
5472	return true;
5473	} // if
5474	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5475	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5476	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5477	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5478	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5479	MI.getOperand(`2`).isImm() &&
5480	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm4 /)) {
5481	// qk.c.lbusp $rd_rs2, ${imm}(${rs1})
5482	// Operand: rd_rs2
5483	// Operand: rs1
5484	// Operand: imm
5485	return true;
5486	} // if
5487	break;
5488	} // case LBU
5489	case RISCV::LD: {
5490	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5491	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5492	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5493	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5494	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5495	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5496	MI.getOperand(`2`).isImm() &&
5497	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /)) {
5498	// c.ld $rd, ${imm}(${rs1})
5499	// Operand: rd
5500	// Operand: rs1
5501	// Operand: imm
5502	return true;
5503	} // if
5504	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5505	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5506	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5507	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5508	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5509	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5510	MI.getOperand(`2`).isImm() &&
5511	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm9_lsb000 /)) {
5512	// c.ldsp $rd, ${imm}(${rs1})
5513	// Operand: rd
5514	// Operand: rs1
5515	// Operand: imm
5516	return true;
5517	} // if
5518	break;
5519	} // case LD
5520	case RISCV::LD_RV32: {
5521	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
5522	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5523	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5524	RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5525	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5526	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5527	MI.getOperand(`2`).isImm() &&
5528	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm9_lsb000 /)) {
5529	// c.ldsp $rd, ${imm}(${rs1})
5530	// Operand: rd
5531	// Operand: rs1
5532	// Operand: imm
5533	return true;
5534	} // if
5535	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
5536	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5537	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5538	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5539	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5540	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5541	MI.getOperand(`2`).isImm() &&
5542	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /)) {
5543	// c.ld $rd, ${imm}(${rs1})
5544	// Operand: rd
5545	// Operand: rs1
5546	// Operand: imm
5547	return true;
5548	} // if
5549	break;
5550	} // case LD_RV32
5551	case RISCV::LH: {
5552	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5553	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5554	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5555	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5556	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5557	MI.getOperand(`2`).isImm() &&
5558	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15` / uimm2_lsb0 /)) {
5559	// c.lh $rd, ${imm}(${rs1})
5560	// Operand: rd
5561	// Operand: rs1
5562	// Operand: imm
5563	return true;
5564	} // if
5565	break;
5566	} // case LH
5567	case RISCV::LHU: {
5568	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5569	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5570	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5571	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5572	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5573	MI.getOperand(`2`).isImm() &&
5574	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15` / uimm2_lsb0 /)) {
5575	// c.lhu $rd, ${imm}(${rs1})
5576	// Operand: rd
5577	// Operand: rs1
5578	// Operand: imm
5579	return true;
5580	} // if
5581	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5582	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5583	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5584	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5585	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5586	MI.getOperand(`2`).isImm() &&
5587	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `16` / uimm6_lsb0 /)) {
5588	// qk.c.lhu $rd, ${imm}(${rs1})
5589	// Operand: rd
5590	// Operand: rs1
5591	// Operand: imm
5592	return true;
5593	} // if
5594	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5595	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5596	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5597	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5598	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5599	MI.getOperand(`2`).isImm() &&
5600	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `17` / uimm5_lsb0 /)) {
5601	// qk.c.lhusp $rd_rs2, ${imm}(${rs1})
5602	// Operand: rd_rs2
5603	// Operand: rs1
5604	// Operand: imm
5605	return true;
5606	} // if
5607	break;
5608	} // case LHU
5609	case RISCV::LH_INX: {
5610	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5611	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5612	RISCVMCRegisterClasses[RISCV::GPRF16CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5613	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5614	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5615	MI.getOperand(`2`).isImm() &&
5616	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15` / uimm2_lsb0 /)) {
5617	// c.lh $rd, ${imm}(${rs1})
5618	// Operand: rd
5619	// Operand: rs1
5620	// Operand: imm
5621	return true;
5622	} // if
5623	break;
5624	} // case LH_INX
5625	case RISCV::LUI: {
5626	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5627	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5628	RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5629	MI.getOperand(`1`).isImm() &&
5630	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `18` / c_lui_imm /)) {
5631	// c.lui $rd, $imm
5632	// Operand: rd
5633	// Operand: imm
5634	return true;
5635	} // if
5636	break;
5637	} // case LUI
5638	case RISCV::LW: {
5639	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5640	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5641	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5642	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5643	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5644	MI.getOperand(`2`).isImm() &&
5645	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm7_lsb00 /)) {
5646	// c.lw $rd, ${imm}(${rs1})
5647	// Operand: rd
5648	// Operand: rs1
5649	// Operand: imm
5650	return true;
5651	} // if
5652	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5653	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5654	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5655	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5656	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5657	MI.getOperand(`2`).isImm() &&
5658	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm8_lsb00 /)) {
5659	// c.lwsp $rd, ${imm}(${rs1})
5660	// Operand: rd
5661	// Operand: rs1
5662	// Operand: imm
5663	return true;
5664	} // if
5665	break;
5666	} // case LW
5667	case RISCV::LW_INX: {
5668	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5669	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5670	RISCVMCRegisterClasses[RISCV::GPRF32NoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5671	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5672	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5673	MI.getOperand(`2`).isImm() &&
5674	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm8_lsb00 /)) {
5675	// c.lwsp $rd, ${imm}(${rs1})
5676	// Operand: rd
5677	// Operand: rs1
5678	// Operand: imm
5679	return true;
5680	} // if
5681	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5682	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5683	RISCVMCRegisterClasses[RISCV::GPRF32CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5684	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5685	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5686	MI.getOperand(`2`).isImm() &&
5687	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm7_lsb00 /)) {
5688	// c.lw $rd, ${imm}(${rs1})
5689	// Operand: rd
5690	// Operand: rs1
5691	// Operand: imm
5692	return true;
5693	} // if
5694	break;
5695	} // case LW_INX
5696	case RISCV::MUL: {
5697	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5698	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
5699	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5700	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5701	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5702	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5703	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5704	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
5705	// c.mul $rd, $rs2
5706	// Operand: rd_wb
5707	// Operand: rd
5708	// Operand: rs2
5709	return true;
5710	} // if
5711	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5712	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
5713	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5714	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5715	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5716	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5717	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5718	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
5719	// c.mul $rd, $rs2
5720	// Operand: rd_wb
5721	// Operand: rd
5722	// Operand: rs2
5723	return true;
5724	} // if
5725	break;
5726	} // case MUL
5727	case RISCV::OR: {
5728	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5729	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5730	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5731	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5732	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5733	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5734	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
5735	// c.or $rd, $rs2
5736	// Operand: rd_wb
5737	// Operand: rd
5738	// Operand: rs2
5739	return true;
5740	} // if
5741	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5742	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
5743	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5744	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5745	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5746	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5747	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
5748	// c.or $rd, $rs2
5749	// Operand: rd_wb
5750	// Operand: rd
5751	// Operand: rs2
5752	return true;
5753	} // if
5754	break;
5755	} // case OR
5756	case RISCV::QC_EXTU: {
5757	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
5758	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
5759	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5760	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5761	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5762	MI.getOperand(`2`).isImm() &&
5763	(MI.getOperand(`2`).getImm() == `1`) &&
5764	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5765	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5766	MI.getOperand(`3`).isImm() &&
5767	RISCVValidateMachineOperand(MI.getOperand(`3`), &STI, `6` / uimmlog2xlennonzero /)) {
5768	// qc.c.bexti $rs1, $shamt
5769	// Operand: rd
5770	// Operand: rs1
5771	// Operand: shamt
5772	return true;
5773	} // if
5774	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
5775	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5776	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5777	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5778	MI.getOperand(`3`).isImm() &&
5779	(MI.getOperand(`3`).getImm() == `0`) &&
5780	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5781	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
5782	MI.getOperand(`2`).isImm() &&
5783	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `19` / uimm5ge6_plus1 /)) {
5784	// qc.c.extu $rd, $width
5785	// Operand: rd_wb
5786	// Operand: rd
5787	// Operand: width
5788	return true;
5789	} // if
5790	break;
5791	} // case QC_EXTU
5792	case RISCV::QC_E_ADDAI: {
5793	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5794	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5795	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5796	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5797	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5798	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5799	MI.getOperand(`2`).isImm() &&
5800	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
5801	// addi $rd, $rs1, $imm12
5802	// Operand: rd
5803	// Operand: rs1
5804	// Operand: imm12
5805	return true;
5806	} // if
5807	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5808	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5809	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5810	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5811	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5812	MI.getOperand(`2`).isImm() &&
5813	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `1` / simm6nonzero /) &&
5814	MI.getOperand(`2`).isImm() &&
5815	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5816	// c.addi $rd, $imm
5817	// Operand: rd_wb
5818	// Operand: rd
5819	// Operand: imm
5820	return true;
5821	} // if
5822	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5823	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5824	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5825	MI.getOperand(`0`).isReg() &&
5826	(MI.getOperand(`0`).getReg() == RISCV::X2) &&
5827	MI.getOperand(`1`).isReg() &&
5828	(MI.getOperand(`1`).getReg() == RISCV::X2) &&
5829	MI.getOperand(`2`).isImm() &&
5830	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `3` / simm10_lsb0000nonzero /)) {
5831	// c.addi16sp $rd, $imm
5832	// Operand: rd_wb
5833	// Operand: rd
5834	// Operand: imm
5835	return true;
5836	} // if
5837	break;
5838	} // case QC_E_ADDAI
5839	case RISCV::QC_E_ADDI: {
5840	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5841	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5842	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5843	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5844	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5845	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
5846	MI.getOperand(`2`).isImm() &&
5847	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
5848	// addi $rd, $rs1, $imm12
5849	// Operand: rd
5850	// Operand: rs1
5851	// Operand: imm12
5852	return true;
5853	} // if
5854	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5855	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5856	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5857	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5858	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5859	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5860	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
5861	MI.getOperand(`2`).isImm() &&
5862	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `1` / simm6nonzero /) &&
5863	MI.getOperand(`2`).isImm() &&
5864	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5865	// c.addi $rd, $imm
5866	// Operand: rd_wb
5867	// Operand: rd
5868	// Operand: imm
5869	return true;
5870	} // if
5871	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5872	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5873	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5874	MI.getOperand(`0`).isReg() &&
5875	(MI.getOperand(`0`).getReg() == RISCV::X2) &&
5876	MI.getOperand(`1`).isReg() &&
5877	(MI.getOperand(`1`).getReg() == RISCV::X2) &&
5878	MI.getOperand(`2`).isImm() &&
5879	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `3` / simm10_lsb0000nonzero /)) {
5880	// c.addi16sp $rd, $imm
5881	// Operand: rd_wb
5882	// Operand: rd
5883	// Operand: imm
5884	return true;
5885	} // if
5886	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5887	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5888	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5889	MI.getOperand(`2`).isImm() &&
5890	(MI.getOperand(`2`).getImm() == `0`) &&
5891	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5892	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5893	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5894	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
5895	// c.mv $rs1, $rs2
5896	// Operand: rs1
5897	// Operand: rs2
5898	return true;
5899	} // if
5900	break;
5901	} // case QC_E_ADDI
5902	case RISCV::QC_E_ANDAI: {
5903	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5904	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5905	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5906	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5907	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5908	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5909	MI.getOperand(`2`).isImm() &&
5910	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
5911	// andi $rd, $rs1, $imm12
5912	// Operand: rd
5913	// Operand: rs1
5914	// Operand: imm12
5915	return true;
5916	} // if
5917	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5918	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5919	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5920	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5921	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5922	MI.getOperand(`2`).isImm() &&
5923	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5924	// c.andi $rs1, $imm
5925	// Operand: rd
5926	// Operand: rs1
5927	// Operand: imm
5928	return true;
5929	} // if
5930	break;
5931	} // case QC_E_ANDAI
5932	case RISCV::QC_E_ANDI: {
5933	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5934	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5935	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5936	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5937	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5938	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
5939	MI.getOperand(`2`).isImm() &&
5940	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
5941	// andi $rd, $rs1, $imm12
5942	// Operand: rd
5943	// Operand: rs1
5944	// Operand: imm12
5945	return true;
5946	} // if
5947	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5948	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5949	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5950	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
5951	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5952	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5953	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5954	MI.getOperand(`2`).isImm() &&
5955	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2` / simm6 /)) {
5956	// c.andi $rs1, $imm
5957	// Operand: rd
5958	// Operand: rs1
5959	// Operand: imm
5960	return true;
5961	} // if
5962	break;
5963	} // case QC_E_ANDI
5964	case RISCV::QC_E_BEQI: {
5965	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
5966	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5967	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5968	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5969	MI.getOperand(`1`).isImm() &&
5970	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `21` / simm5nonzero /) &&
5971	MI.getOperand(`2`).isImm() &&
5972	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / bare_simm13_lsb0 /)) {
5973	// qc.beqi $rs1, $rs2, $imm12
5974	// Operand: rs1
5975	// Operand: rs2
5976	// Operand: imm12
5977	return true;
5978	} // if
5979	break;
5980	} // case QC_E_BEQI
5981	case RISCV::QC_E_BGEI: {
5982	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
5983	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5984	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5985	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5986	MI.getOperand(`1`).isImm() &&
5987	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `21` / simm5nonzero /) &&
5988	MI.getOperand(`2`).isImm() &&
5989	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / bare_simm13_lsb0 /)) {
5990	// qc.bgei $rs1, $rs2, $imm12
5991	// Operand: rs1
5992	// Operand: rs2
5993	// Operand: imm12
5994	return true;
5995	} // if
5996	break;
5997	} // case QC_E_BGEI
5998	case RISCV::QC_E_BGEUI: {
5999	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6000	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6001	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6002	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6003	MI.getOperand(`1`).isImm() &&
6004	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `23` / uimm5nonzero /) &&
6005	MI.getOperand(`2`).isImm() &&
6006	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / bare_simm13_lsb0 /)) {
6007	// qc.bgeui $rs1, $rs2, $imm12
6008	// Operand: rs1
6009	// Operand: rs2
6010	// Operand: imm12
6011	return true;
6012	} // if
6013	break;
6014	} // case QC_E_BGEUI
6015	case RISCV::QC_E_BLTI: {
6016	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6017	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6018	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6019	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6020	MI.getOperand(`1`).isImm() &&
6021	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `21` / simm5nonzero /) &&
6022	MI.getOperand(`2`).isImm() &&
6023	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / bare_simm13_lsb0 /)) {
6024	// qc.blti $rs1, $rs2, $imm12
6025	// Operand: rs1
6026	// Operand: rs2
6027	// Operand: imm12
6028	return true;
6029	} // if
6030	break;
6031	} // case QC_E_BLTI
6032	case RISCV::QC_E_BLTUI: {
6033	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6034	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6035	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6036	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6037	MI.getOperand(`1`).isImm() &&
6038	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `23` / uimm5nonzero /) &&
6039	MI.getOperand(`2`).isImm() &&
6040	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / bare_simm13_lsb0 /)) {
6041	// qc.bltui $rs1, $rs2, $imm12
6042	// Operand: rs1
6043	// Operand: rs2
6044	// Operand: imm12
6045	return true;
6046	} // if
6047	break;
6048	} // case QC_E_BLTUI
6049	case RISCV::QC_E_BNEI: {
6050	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
6051	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6052	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6053	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6054	MI.getOperand(`1`).isImm() &&
6055	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `21` / simm5nonzero /) &&
6056	MI.getOperand(`2`).isImm() &&
6057	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `22` / bare_simm13_lsb0 /)) {
6058	// qc.bnei $rs1, $rs2, $imm12
6059	// Operand: rs1
6060	// Operand: rs2
6061	// Operand: imm12
6062	return true;
6063	} // if
6064	break;
6065	} // case QC_E_BNEI
6066	case RISCV::QC_E_J: {
6067	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
6068	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6069	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6070	MI.getOperand(`0`).isImm() &&
6071	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `11` / bare_simm12_lsb0 /)) {
6072	// c.j $offset
6073	// Operand: offset
6074	return true;
6075	} // if
6076	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
6077	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6078	MI.getOperand(`0`).isImm() &&
6079	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `24` / simm21_lsb0_jal /)) {
6080	// jal $rd, $imm20
6081	// Operand: rd
6082	// Operand: imm20
6083	return true;
6084	} // if
6085	break;
6086	} // case QC_E_J
6087	case RISCV::QC_E_JAL: {
6088	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
6089	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6090	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6091	MI.getOperand(`0`).isImm() &&
6092	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `11` / bare_simm12_lsb0 /)) {
6093	// c.jal $offset
6094	// Operand: offset
6095	return true;
6096	} // if
6097	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
6098	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6099	MI.getOperand(`0`).isImm() &&
6100	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `24` / simm21_lsb0_jal /)) {
6101	// jal $rd, $imm20
6102	// Operand: rd
6103	// Operand: imm20
6104	return true;
6105	} // if
6106	break;
6107	} // case QC_E_JAL
6108	case RISCV::QC_E_LB: {
6109	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6110	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6111	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6112	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6113	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6114	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6115	MI.getOperand(`2`).isImm() &&
6116	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6117	// lb $rd, ${imm12}(${rs1})
6118	// Operand: rd
6119	// Operand: rs1
6120	// Operand: imm12
6121	return true;
6122	} // if
6123	break;
6124	} // case QC_E_LB
6125	case RISCV::QC_E_LBU: {
6126	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6127	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6128	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6129	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6130	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6131	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6132	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6133	MI.getOperand(`2`).isImm() &&
6134	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm2 /)) {
6135	// c.lbu $rd, ${imm}(${rs1})
6136	// Operand: rd
6137	// Operand: rs1
6138	// Operand: imm
6139	return true;
6140	} // if
6141	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6142	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6143	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6144	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6145	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6146	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6147	MI.getOperand(`2`).isImm() &&
6148	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6149	// lbu $rd, ${imm12}(${rs1})
6150	// Operand: rd
6151	// Operand: rs1
6152	// Operand: imm12
6153	return true;
6154	} // if
6155	break;
6156	} // case QC_E_LBU
6157	case RISCV::QC_E_LH: {
6158	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6159	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6160	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6161	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6162	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6163	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6164	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6165	MI.getOperand(`2`).isImm() &&
6166	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15` / uimm2_lsb0 /)) {
6167	// c.lh $rd, ${imm}(${rs1})
6168	// Operand: rd
6169	// Operand: rs1
6170	// Operand: imm
6171	return true;
6172	} // if
6173	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6174	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6175	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6176	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6177	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6178	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6179	MI.getOperand(`2`).isImm() &&
6180	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6181	// lh $rd, ${imm12}(${rs1})
6182	// Operand: rd
6183	// Operand: rs1
6184	// Operand: imm12
6185	return true;
6186	} // if
6187	break;
6188	} // case QC_E_LH
6189	case RISCV::QC_E_LHU: {
6190	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6191	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6192	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6193	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6194	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6195	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6196	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6197	MI.getOperand(`2`).isImm() &&
6198	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15` / uimm2_lsb0 /)) {
6199	// c.lhu $rd, ${imm}(${rs1})
6200	// Operand: rd
6201	// Operand: rs1
6202	// Operand: imm
6203	return true;
6204	} // if
6205	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6206	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6207	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6208	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6209	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6210	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6211	MI.getOperand(`2`).isImm() &&
6212	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6213	// lhu $rd, ${imm12}(${rs1})
6214	// Operand: rd
6215	// Operand: rs1
6216	// Operand: imm12
6217	return true;
6218	} // if
6219	break;
6220	} // case QC_E_LHU
6221	case RISCV::QC_E_LI: {
6222	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
6223	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6224	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6225	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6226	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6227	MI.getOperand(`1`).isImm() &&
6228	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `2` / simm6 /)) {
6229	// c.li $rd, $imm
6230	// Operand: rd
6231	// Operand: imm
6232	return true;
6233	} // if
6234	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
6235	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6236	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6237	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6238	MI.getOperand(`1`).isImm() &&
6239	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `25` / simm20_li /)) {
6240	// qc.li $rd, $imm20
6241	// Operand: rd
6242	// Operand: imm20
6243	return true;
6244	} // if
6245	break;
6246	} // case QC_E_LI
6247	case RISCV::QC_E_LW: {
6248	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6249	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6250	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6251	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6252	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6253	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6254	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6255	MI.getOperand(`2`).isImm() &&
6256	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm7_lsb00 /)) {
6257	// c.lw $rd, ${imm}(${rs1})
6258	// Operand: rd
6259	// Operand: rs1
6260	// Operand: imm
6261	return true;
6262	} // if
6263	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6264	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6265	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6266	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6267	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6268	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6269	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6270	MI.getOperand(`2`).isImm() &&
6271	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm8_lsb00 /)) {
6272	// c.lwsp $rd, ${imm}(${rs1})
6273	// Operand: rd
6274	// Operand: rs1
6275	// Operand: imm
6276	return true;
6277	} // if
6278	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6279	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6280	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6281	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6282	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6283	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6284	MI.getOperand(`2`).isImm() &&
6285	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6286	// lw $rd, ${imm12}(${rs1})
6287	// Operand: rd
6288	// Operand: rs1
6289	// Operand: imm12
6290	return true;
6291	} // if
6292	break;
6293	} // case QC_E_LW
6294	case RISCV::QC_E_ORAI: {
6295	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6296	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6297	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6298	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6299	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6300	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6301	MI.getOperand(`2`).isImm() &&
6302	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6303	// ori $rd, $rs1, $imm12
6304	// Operand: rd
6305	// Operand: rs1
6306	// Operand: imm12
6307	return true;
6308	} // if
6309	break;
6310	} // case QC_E_ORAI
6311	case RISCV::QC_E_ORI: {
6312	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6313	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6314	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6315	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6316	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6317	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
6318	MI.getOperand(`2`).isImm() &&
6319	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6320	// ori $rd, $rs1, $imm12
6321	// Operand: rd
6322	// Operand: rs1
6323	// Operand: imm12
6324	return true;
6325	} // if
6326	break;
6327	} // case QC_E_ORI
6328	case RISCV::QC_E_SB: {
6329	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6330	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6331	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6332	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6333	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6334	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6335	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6336	MI.getOperand(`2`).isImm() &&
6337	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm2 /)) {
6338	// c.sb $rs2, ${imm}(${rs1})
6339	// Operand: rs2
6340	// Operand: rs1
6341	// Operand: imm
6342	return true;
6343	} // if
6344	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6345	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6346	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6347	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6348	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6349	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6350	MI.getOperand(`2`).isImm() &&
6351	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6352	// sb $rs2, ${imm12}(${rs1})
6353	// Operand: rs2
6354	// Operand: rs1
6355	// Operand: imm12
6356	return true;
6357	} // if
6358	break;
6359	} // case QC_E_SB
6360	case RISCV::QC_E_SH: {
6361	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6362	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6363	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6364	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6365	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6366	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6367	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6368	MI.getOperand(`2`).isImm() &&
6369	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15` / uimm2_lsb0 /)) {
6370	// c.sh $rs2, ${imm}(${rs1})
6371	// Operand: rs2
6372	// Operand: rs1
6373	// Operand: imm
6374	return true;
6375	} // if
6376	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6377	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6378	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6379	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6380	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6381	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6382	MI.getOperand(`2`).isImm() &&
6383	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6384	// sh $rs2, ${imm12}(${rs1})
6385	// Operand: rs2
6386	// Operand: rs1
6387	// Operand: imm12
6388	return true;
6389	} // if
6390	break;
6391	} // case QC_E_SH
6392	case RISCV::QC_E_SW: {
6393	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6394	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6395	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6396	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6397	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6398	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6399	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6400	MI.getOperand(`2`).isImm() &&
6401	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm7_lsb00 /)) {
6402	// c.sw $rs2, ${imm}(${rs1})
6403	// Operand: rs2
6404	// Operand: rs1
6405	// Operand: imm
6406	return true;
6407	} // if
6408	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6409	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6410	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6411	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6412	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6413	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6414	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6415	MI.getOperand(`2`).isImm() &&
6416	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm8_lsb00 /)) {
6417	// c.swsp $rs2, ${imm}(${rs1})
6418	// Operand: rs2
6419	// Operand: rs1
6420	// Operand: imm
6421	return true;
6422	} // if
6423	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
6424	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6425	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6426	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6427	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6428	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6429	MI.getOperand(`2`).isImm() &&
6430	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6431	// sw $rs2, ${imm12}(${rs1})
6432	// Operand: rs2
6433	// Operand: rs1
6434	// Operand: imm12
6435	return true;
6436	} // if
6437	break;
6438	} // case QC_E_SW
6439	case RISCV::QC_E_XORAI: {
6440	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6441	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6442	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6443	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6444	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6445	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6446	MI.getOperand(`2`).isImm() &&
6447	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6448	// xori $rd, $rs1, $imm12
6449	// Operand: rd
6450	// Operand: rs1
6451	// Operand: imm12
6452	return true;
6453	} // if
6454	break;
6455	} // case QC_E_XORAI
6456	case RISCV::QC_E_XORI: {
6457	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
6458	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6459	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6460	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6461	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6462	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
6463	MI.getOperand(`2`).isImm() &&
6464	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `20` / simm12_lo /)) {
6465	// xori $rd, $rs1, $imm12
6466	// Operand: rd
6467	// Operand: rs1
6468	// Operand: imm12
6469	return true;
6470	} // if
6471	break;
6472	} // case QC_E_XORI
6473	case RISCV::QC_LI: {
6474	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
6475	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6476	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6477	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6478	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6479	MI.getOperand(`1`).isImm() &&
6480	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `2` / simm6 /)) {
6481	// c.li $rd, $imm
6482	// Operand: rd
6483	// Operand: imm
6484	return true;
6485	} // if
6486	break;
6487	} // case QC_LI
6488	case RISCV::QC_MULIADD: {
6489	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
6490	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6491	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6492	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6493	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6494	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
6495	MI.getOperand(`3`).isImm() &&
6496	RISCVValidateMachineOperand(MI.getOperand(`3`), &STI, `13` / uimm5 /)) {
6497	// qc.c.muliadd $rd, $rs1, $uimm
6498	// Operand: rd_wb
6499	// Operand: rd
6500	// Operand: rs1
6501	// Operand: uimm
6502	return true;
6503	} // if
6504	break;
6505	} // case QC_MULIADD
6506	case RISCV::QC_MVEQI: {
6507	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
6508	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6509	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
6510	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6511	MI.getOperand(`3`).isImm() &&
6512	(MI.getOperand(`3`).getImm() == `0`) &&
6513	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6514	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
6515	MI.getOperand(`4`).isReg() && MI.getOperand(`4`).getReg().isPhysical() &&
6516	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`4`).getReg())) {
6517	// qc.c.mveqz $rd, $rs1
6518	// Operand: rd_wb
6519	// Operand: rd
6520	// Operand: rs1
6521	return true;
6522	} // if
6523	break;
6524	} // case QC_MVEQI
6525	case RISCV::QC_MVLTUI: {
6526	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
6527	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6528	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
6529	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6530	MI.getOperand(`3`).isImm() &&
6531	(MI.getOperand(`3`).getImm() == `1`) &&
6532	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6533	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
6534	MI.getOperand(`4`).isReg() && MI.getOperand(`4`).getReg().isPhysical() &&
6535	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`4`).getReg())) {
6536	// qc.c.mveqz $rd, $rs1
6537	// Operand: rd_wb
6538	// Operand: rd
6539	// Operand: rs1
6540	return true;
6541	} // if
6542	break;
6543	} // case QC_MVLTUI
6544	case RISCV::QC_SYNC: {
6545	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
6546	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6547	MI.getOperand(`0`).isImm() &&
6548	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `26` / uimm5slist /)) {
6549	// qc.c.sync $slist
6550	// Operand: slist
6551	return true;
6552	} // if
6553	break;
6554	} // case QC_SYNC
6555	case RISCV::QC_SYNCR: {
6556	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
6557	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6558	MI.getOperand(`0`).isImm() &&
6559	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `26` / uimm5slist /)) {
6560	// qc.c.syncr $slist
6561	// Operand: slist
6562	return true;
6563	} // if
6564	break;
6565	} // case QC_SYNCR
6566	case RISCV::QC_SYNCWF: {
6567	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
6568	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6569	MI.getOperand(`0`).isImm() &&
6570	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `26` / uimm5slist /)) {
6571	// qc.c.syncwf $slist
6572	// Operand: slist
6573	return true;
6574	} // if
6575	break;
6576	} // case QC_SYNCWF
6577	case RISCV::QC_SYNCWL: {
6578	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
6579	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6580	MI.getOperand(`0`).isImm() &&
6581	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `26` / uimm5slist /)) {
6582	// qc.c.syncwl $slist
6583	// Operand: slist
6584	return true;
6585	} // if
6586	break;
6587	} // case QC_SYNCWL
6588	case RISCV::SB: {
6589	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6590	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6591	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6592	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6593	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6594	MI.getOperand(`2`).isImm() &&
6595	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12` / uimm2 /)) {
6596	// c.sb $rs2, ${imm}(${rs1})
6597	// Operand: rs2
6598	// Operand: rs1
6599	// Operand: imm
6600	return true;
6601	} // if
6602	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
6603	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6604	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6605	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6606	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6607	MI.getOperand(`2`).isImm() &&
6608	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13` / uimm5 /)) {
6609	// qk.c.sb $rs2, ${imm}(${rs1})
6610	// Operand: rs2
6611	// Operand: rs1
6612	// Operand: imm
6613	return true;
6614	} // if
6615	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
6616	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6617	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6618	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6619	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6620	MI.getOperand(`2`).isImm() &&
6621	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14` / uimm4 /)) {
6622	// qk.c.sbsp $rd_rs2, ${imm}(${rs1})
6623	// Operand: rd_rs2
6624	// Operand: rs1
6625	// Operand: imm
6626	return true;
6627	} // if
6628	break;
6629	} // case SB
6630	case RISCV::SD: {
6631	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
6632	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6633	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6634	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6635	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6636	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6637	MI.getOperand(`2`).isImm() &&
6638	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /)) {
6639	// c.sd $rs2, ${imm}(${rs1})
6640	// Operand: rs2
6641	// Operand: rs1
6642	// Operand: imm
6643	return true;
6644	} // if
6645	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
6646	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6647	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6648	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6649	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6650	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6651	MI.getOperand(`2`).isImm() &&
6652	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm9_lsb000 /)) {
6653	// c.sdsp $rs2, ${imm}(${rs1})
6654	// Operand: rs2
6655	// Operand: rs1
6656	// Operand: imm
6657	return true;
6658	} // if
6659	break;
6660	} // case SD
6661	case RISCV::SD_RV32: {
6662	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
6663	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6664	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6665	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6666	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6667	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6668	MI.getOperand(`2`).isImm() &&
6669	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8` / uimm9_lsb000 /)) {
6670	// c.sdsp $rs2, ${imm}(${rs1})
6671	// Operand: rs2
6672	// Operand: rs1
6673	// Operand: imm
6674	return true;
6675	} // if
6676	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
6677	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6678	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6679	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6680	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6681	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6682	MI.getOperand(`2`).isImm() &&
6683	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7` / uimm8_lsb000 /)) {
6684	// c.sd $rs2, ${imm}(${rs1})
6685	// Operand: rs2
6686	// Operand: rs1
6687	// Operand: imm
6688	return true;
6689	} // if
6690	break;
6691	} // case SD_RV32
6692	case RISCV::SEXT_B: {
6693	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
6694	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6695	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6696	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6697	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6698	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
6699	// c.sext.b $rd
6700	// Operand: rd_wb
6701	// Operand: rd
6702	return true;
6703	} // if
6704	break;
6705	} // case SEXT_B
6706	case RISCV::SEXT_H: {
6707	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
6708	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6709	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6710	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6711	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6712	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
6713	// c.sext.h $rd
6714	// Operand: rd_wb
6715	// Operand: rd
6716	return true;
6717	} // if
6718	break;
6719	} // case SEXT_H
6720	case RISCV::SH: {
6721	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6722	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6723	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6724	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6725	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6726	MI.getOperand(`2`).isImm() &&
6727	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15` / uimm2_lsb0 /)) {
6728	// c.sh $rs2, ${imm}(${rs1})
6729	// Operand: rs2
6730	// Operand: rs1
6731	// Operand: imm
6732	return true;
6733	} // if
6734	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
6735	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6736	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6737	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6738	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6739	MI.getOperand(`2`).isImm() &&
6740	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `16` / uimm6_lsb0 /)) {
6741	// qk.c.sh $rs2, ${imm}(${rs1})
6742	// Operand: rs2
6743	// Operand: rs1
6744	// Operand: imm
6745	return true;
6746	} // if
6747	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
6748	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6749	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6750	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6751	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6752	MI.getOperand(`2`).isImm() &&
6753	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `17` / uimm5_lsb0 /)) {
6754	// qk.c.shsp $rd_rs2, ${imm}(${rs1})
6755	// Operand: rd_rs2
6756	// Operand: rs1
6757	// Operand: imm
6758	return true;
6759	} // if
6760	break;
6761	} // case SH
6762	case RISCV::SH1ADD: {
6763	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
6764	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
6765	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6766	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
6767	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6768	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6769	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
6770	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6771	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6772	RISCVValidateMachineOperand(MachineOperand::CreateImm(`2`), &STI, `13` / uimm5 /)) {
6773	// qc.c.muliadd $rd, $rs1, $uimm
6774	// Operand: rd_wb
6775	// Operand: rd
6776	// Operand: rs1
6777	// Operand: uimm
6778	return true;
6779	} // if
6780	break;
6781	} // case SH1ADD
6782	case RISCV::SH2ADD: {
6783	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
6784	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
6785	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6786	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
6787	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6788	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6789	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
6790	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6791	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6792	RISCVValidateMachineOperand(MachineOperand::CreateImm(`4`), &STI, `13` / uimm5 /)) {
6793	// qc.c.muliadd $rd, $rs1, $uimm
6794	// Operand: rd_wb
6795	// Operand: rd
6796	// Operand: rs1
6797	// Operand: uimm
6798	return true;
6799	} // if
6800	break;
6801	} // case SH2ADD
6802	case RISCV::SH3ADD: {
6803	if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
6804	STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
6805	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6806	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
6807	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6808	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6809	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
6810	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6811	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6812	RISCVValidateMachineOperand(MachineOperand::CreateImm(`8`), &STI, `13` / uimm5 /)) {
6813	// qc.c.muliadd $rd, $rs1, $uimm
6814	// Operand: rd_wb
6815	// Operand: rd
6816	// Operand: rs1
6817	// Operand: uimm
6818	return true;
6819	} // if
6820	break;
6821	} // case SH3ADD
6822	case RISCV::SH_INX: {
6823	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6824	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6825	RISCVMCRegisterClasses[RISCV::GPRF16CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6826	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6827	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6828	MI.getOperand(`2`).isImm() &&
6829	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15` / uimm2_lsb0 /)) {
6830	// c.sh $rs2, ${imm}(${rs1})
6831	// Operand: rs2
6832	// Operand: rs1
6833	// Operand: imm
6834	return true;
6835	} // if
6836	break;
6837	} // case SH_INX
6838	case RISCV::SLLI: {
6839	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6840	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6841	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6842	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6843	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
6844	MI.getOperand(`2`).isImm() &&
6845	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /) &&
6846	MI.getOperand(`2`).isImm() &&
6847	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `27` / uimmlog2xlen /)) {
6848	// c.slli $rd, $imm
6849	// Operand: rd_wb
6850	// Operand: rd
6851	// Operand: imm
6852	return true;
6853	} // if
6854	break;
6855	} // case SLLI
6856	case RISCV::SRAI: {
6857	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6858	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6859	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6860	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6861	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6862	MI.getOperand(`2`).isImm() &&
6863	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /) &&
6864	MI.getOperand(`2`).isImm() &&
6865	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `27` / uimmlog2xlen /)) {
6866	// c.srai $rs1, $imm
6867	// Operand: rd
6868	// Operand: rs1
6869	// Operand: imm
6870	return true;
6871	} // if
6872	break;
6873	} // case SRAI
6874	case RISCV::SRLI: {
6875	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6876	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6877	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6878	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6879	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6880	MI.getOperand(`2`).isImm() &&
6881	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6` / uimmlog2xlennonzero /) &&
6882	MI.getOperand(`2`).isImm() &&
6883	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `27` / uimmlog2xlen /)) {
6884	// c.srli $rs1, $imm
6885	// Operand: rd
6886	// Operand: rs1
6887	// Operand: imm
6888	return true;
6889	} // if
6890	break;
6891	} // case SRLI
6892	case RISCV::SSPOPCHK: {
6893	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
6894	MI.getOperand(`0`).isReg() &&
6895	(MI.getOperand(`0`).getReg() == RISCV::X5)) {
6896	// c.sspopchk $rs1
6897	// Operand: rs1
6898	return true;
6899	} // if
6900	break;
6901	} // case SSPOPCHK
6902	case RISCV::SSPUSH: {
6903	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
6904	MI.getOperand(`0`).isReg() &&
6905	(MI.getOperand(`0`).getReg() == RISCV::X1)) {
6906	// c.sspush $rs1
6907	// Operand: rs1
6908	return true;
6909	} // if
6910	break;
6911	} // case SSPUSH
6912	case RISCV::SUB: {
6913	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6914	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6915	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6916	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6917	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6918	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6919	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
6920	// c.sub $rd, $rs2
6921	// Operand: rd_wb
6922	// Operand: rd
6923	// Operand: rs2
6924	return true;
6925	} // if
6926	break;
6927	} // case SUB
6928	case RISCV::SUBW: {
6929	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
6930	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6931	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
6932	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6933	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6934	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6935	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6936	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
6937	// c.subw $rd, $rs2
6938	// Operand: rd_wb
6939	// Operand: rd
6940	// Operand: rs2
6941	return true;
6942	} // if
6943	break;
6944	} // case SUBW
6945	case RISCV::SW: {
6946	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6947	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6948	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6949	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6950	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6951	MI.getOperand(`2`).isImm() &&
6952	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm7_lsb00 /)) {
6953	// c.sw $rs2, ${imm}(${rs1})
6954	// Operand: rs2
6955	// Operand: rs1
6956	// Operand: imm
6957	return true;
6958	} // if
6959	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6960	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6961	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6962	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6963	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6964	MI.getOperand(`2`).isImm() &&
6965	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm8_lsb00 /)) {
6966	// c.swsp $rs2, ${imm}(${rs1})
6967	// Operand: rs2
6968	// Operand: rs1
6969	// Operand: imm
6970	return true;
6971	} // if
6972	break;
6973	} // case SW
6974	case RISCV::SW_INX: {
6975	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6976	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6977	RISCVMCRegisterClasses[RISCV::GPRF32RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6978	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6979	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6980	MI.getOperand(`2`).isImm() &&
6981	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10` / uimm8_lsb00 /)) {
6982	// c.swsp $rs2, ${imm}(${rs1})
6983	// Operand: rs2
6984	// Operand: rs1
6985	// Operand: imm
6986	return true;
6987	} // if
6988	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6989	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6990	RISCVMCRegisterClasses[RISCV::GPRF32CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6991	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6992	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6993	MI.getOperand(`2`).isImm() &&
6994	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9` / uimm7_lsb00 /)) {
6995	// c.sw $rs2, ${imm}(${rs1})
6996	// Operand: rs2
6997	// Operand: rs1
6998	// Operand: imm
6999	return true;
7000	} // if
7001	break;
7002	} // case SW_INX
7003	case RISCV::UNIMP: {
7004	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
7005	// c.unimp
7006	return true;
7007	} // if
7008	break;
7009	} // case UNIMP
7010	case RISCV::XOR: {
7011	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
7012	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7013	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7014	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7015	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
7016	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7017	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
7018	// c.xor $rd, $rs2
7019	// Operand: rd_wb
7020	// Operand: rd
7021	// Operand: rs2
7022	return true;
7023	} // if
7024	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
7025	MI.getOperand(`2`).isReg() && MI.getOperand(`0`).isReg() &&
7026	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
7027	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
7028	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
7029	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7030	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
7031	// c.xor $rd, $rs2
7032	// Operand: rd_wb
7033	// Operand: rd
7034	// Operand: rs2
7035	return true;
7036	} // if
7037	break;
7038	} // case XOR
7039	case RISCV::XORI: {
7040	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7041	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7042	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7043	MI.getOperand(`2`).isImm() &&
7044	(MI.getOperand(`2`).getImm() == -`1`) &&
7045	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7046	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
7047	// c.not $rd
7048	// Operand: rd_wb
7049	// Operand: rd
7050	return true;
7051	} // if
7052	break;
7053	} // case XORI
7054	case RISCV::ZEXT_H_RV32: {
7055	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
7056	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7057	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7058	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7059	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7060	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
7061	// c.zext.h $rd
7062	// Operand: rd_wb
7063	// Operand: rd
7064	return true;
7065	} // if
7066	break;
7067	} // case ZEXT_H_RV32
7068	case RISCV::ZEXT_H_RV64: {
7069	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
7070	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
7071	MI.getOperand(`1`).isReg() && MI.getOperand(`0`).isReg() &&
7072	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
7073	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
7074	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
7075	// c.zext.h $rd
7076	// Operand: rd_wb
7077	// Operand: rd
7078	return true;
7079	} // if
7080	break;
7081	} // case ZEXT_H_RV64
7082	} // switch
7083	return false;
7084	}
7085
7086	#endif // GEN_CHECK_COMPRESS_INSTR
7087
7088

Browse the source code of llvm_projects/build/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc