| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Compress instruction Source Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* From: RISCV.td *| |
| 7 | |* *| |
| 8 | \*===----------------------------------------------------------------------===*/ |
| 9 | |
| 10 | #ifdef GEN_COMPRESS_INSTR |
| 11 | #undef GEN_COMPRESS_INSTR |
| 12 | |
| 13 | static bool RISCVValidateMCOperandForCompress(const MCOperand &MCOp, |
| 14 | const MCSubtargetInfo &STI, |
| 15 | unsigned PredicateIndex) { |
| 16 | switch (PredicateIndex) { |
| 17 | default: |
| 18 | llvm_unreachable("Unknown MCOperandPredicate kind"); |
| 19 | break; |
| 20 | case 1: { |
| 21 | // uimm10_lsb00nonzero |
| 22 | int64_t Imm; |
| 23 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 24 | return false; |
| 25 | return isShiftedUInt<8, 2>(x: Imm) && (Imm != 0); |
| 26 | } |
| 27 | case 2: { |
| 28 | // simm6nonzero |
| 29 | int64_t Imm; |
| 30 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 31 | return (Imm != 0) && isInt<6>(x: Imm); |
| 32 | return MCOp.isBareSymbolRef(); |
| 33 | } |
| 34 | case 3: { |
| 35 | // simm6 |
| 36 | int64_t Imm; |
| 37 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 38 | return isInt<6>(x: Imm); |
| 39 | return MCOp.isBareSymbolRef(); |
| 40 | } |
| 41 | case 4: { |
| 42 | // simm10_lsb0000nonzero |
| 43 | int64_t Imm; |
| 44 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 45 | return false; |
| 46 | return isShiftedInt<6, 4>(x: Imm) && (Imm != 0); |
| 47 | } |
| 48 | case 5: { |
| 49 | // bare_simm9_lsb0 |
| 50 | int64_t Imm; |
| 51 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 52 | return isShiftedInt<8, 1>(x: Imm); |
| 53 | return MCOp.isBareSymbolRef(); |
| 54 | } |
| 55 | case 6: { |
| 56 | // uimmlog2xlennonzero |
| 57 | int64_t Imm; |
| 58 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 59 | return false; |
| 60 | if (STI.getTargetTriple().isArch64Bit()) |
| 61 | return isUInt<6>(x: Imm) && (Imm != 0); |
| 62 | return isUInt<5>(x: Imm) && (Imm != 0); |
| 63 | } |
| 64 | case 7: { |
| 65 | // uimm8_lsb000 |
| 66 | int64_t Imm; |
| 67 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 68 | return false; |
| 69 | return isShiftedUInt<5, 3>(x: Imm); |
| 70 | } |
| 71 | case 8: { |
| 72 | // uimm8_lsb000_optional |
| 73 | int64_t Imm; |
| 74 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 75 | return false; |
| 76 | return isShiftedUInt<5, 3>(x: Imm); |
| 77 | } |
| 78 | case 9: { |
| 79 | // uimm9_lsb000 |
| 80 | int64_t Imm; |
| 81 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 82 | return false; |
| 83 | return isShiftedUInt<6, 3>(x: Imm); |
| 84 | } |
| 85 | case 10: { |
| 86 | // uimm9_lsb000_optional |
| 87 | int64_t Imm; |
| 88 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 89 | return false; |
| 90 | return isShiftedUInt<6, 3>(x: Imm); |
| 91 | } |
| 92 | case 11: { |
| 93 | // uimm7_lsb00 |
| 94 | int64_t Imm; |
| 95 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 96 | return false; |
| 97 | return isShiftedUInt<5, 2>(x: Imm); |
| 98 | } |
| 99 | case 12: { |
| 100 | // uimm7_lsb00_optional |
| 101 | int64_t Imm; |
| 102 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 103 | return false; |
| 104 | return isShiftedUInt<5, 2>(x: Imm); |
| 105 | } |
| 106 | case 13: { |
| 107 | // uimm8_lsb00 |
| 108 | int64_t Imm; |
| 109 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 110 | return false; |
| 111 | return isShiftedUInt<6, 2>(x: Imm); |
| 112 | } |
| 113 | case 14: { |
| 114 | // uimm8_lsb00_optional |
| 115 | int64_t Imm; |
| 116 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 117 | return false; |
| 118 | return isShiftedUInt<6, 2>(x: Imm); |
| 119 | } |
| 120 | case 15: { |
| 121 | // bare_simm12_lsb0 |
| 122 | int64_t Imm; |
| 123 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 124 | return isShiftedInt<11, 1>(x: Imm); |
| 125 | return MCOp.isBareSymbolRef(); |
| 126 | } |
| 127 | case 16: { |
| 128 | // uimm2 |
| 129 | int64_t Imm; |
| 130 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 131 | return false; |
| 132 | return isUInt<2>(x: Imm); |
| 133 | } |
| 134 | case 17: { |
| 135 | // uimm2_optional |
| 136 | int64_t Imm; |
| 137 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 138 | return false; |
| 139 | return isUInt<2>(x: Imm); |
| 140 | } |
| 141 | case 18: { |
| 142 | // uimm5 |
| 143 | int64_t Imm; |
| 144 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 145 | return false; |
| 146 | return isUInt<5>(x: Imm); |
| 147 | } |
| 148 | case 19: { |
| 149 | // uimm4 |
| 150 | int64_t Imm; |
| 151 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 152 | return false; |
| 153 | return isUInt<4>(x: Imm); |
| 154 | } |
| 155 | case 20: { |
| 156 | // uimm2_lsb0 |
| 157 | int64_t Imm; |
| 158 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 159 | return false; |
| 160 | return isShiftedUInt<1, 1>(x: Imm); |
| 161 | } |
| 162 | case 21: { |
| 163 | // uimm2_lsb0_optional |
| 164 | int64_t Imm; |
| 165 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 166 | return false; |
| 167 | return isShiftedUInt<1, 1>(x: Imm); |
| 168 | } |
| 169 | case 22: { |
| 170 | // uimm6_lsb0 |
| 171 | int64_t Imm; |
| 172 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 173 | return false; |
| 174 | return isShiftedUInt<5, 1>(x: Imm); |
| 175 | } |
| 176 | case 23: { |
| 177 | // uimm5_lsb0 |
| 178 | int64_t Imm; |
| 179 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 180 | return false; |
| 181 | return isShiftedUInt<4, 1>(x: Imm); |
| 182 | } |
| 183 | case 24: { |
| 184 | // c_lui_imm |
| 185 | int64_t Imm; |
| 186 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 187 | return false; |
| 188 | return (Imm != 0) && (isUInt<5>(x: Imm) || |
| 189 | (Imm >= 0xfffe0 && Imm <= 0xfffff)); |
| 190 | } |
| 191 | case 25: { |
| 192 | // uimm5ge6_plus1 |
| 193 | int64_t Imm; |
| 194 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 195 | return false; |
| 196 | return Imm >= 6 && Imm <= 32; |
| 197 | } |
| 198 | case 26: { |
| 199 | // simm12_lo |
| 200 | int64_t Imm; |
| 201 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 202 | return isInt<12>(x: Imm); |
| 203 | return MCOp.isBareSymbolRef(); |
| 204 | } |
| 205 | case 27: { |
| 206 | // simm5nonzero |
| 207 | int64_t Imm; |
| 208 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 209 | return false; |
| 210 | return (Imm != 0) && isInt<5>(x: Imm); |
| 211 | } |
| 212 | case 28: { |
| 213 | // bare_simm13_lsb0 |
| 214 | int64_t Imm; |
| 215 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 216 | return isShiftedInt<12, 1>(x: Imm); |
| 217 | return MCOp.isBareSymbolRef(); |
| 218 | } |
| 219 | case 29: { |
| 220 | // uimm5nonzero |
| 221 | int64_t Imm; |
| 222 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 223 | return false; |
| 224 | return (Imm != 0) && isUInt<5>(x: Imm);; |
| 225 | } |
| 226 | case 30: { |
| 227 | // simm21_lsb0_jal |
| 228 | int64_t Imm; |
| 229 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 230 | return isShiftedInt<20, 1>(x: Imm); |
| 231 | return MCOp.isBareSymbolRef(); |
| 232 | } |
| 233 | case 31: { |
| 234 | // simm12_lo_optional |
| 235 | int64_t Imm; |
| 236 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 237 | return isInt<12>(x: Imm); |
| 238 | return MCOp.isBareSymbolRef(); |
| 239 | } |
| 240 | case 32: { |
| 241 | // simm20_li |
| 242 | int64_t Imm; |
| 243 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 244 | return isInt<20>(x: Imm); |
| 245 | return MCOp.isBareSymbolRef(); |
| 246 | } |
| 247 | case 33: { |
| 248 | // uimm5slist |
| 249 | int64_t Imm; |
| 250 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 251 | return false; |
| 252 | return ((Imm == 0) || (Imm == 1) || |
| 253 | (Imm == 2) || (Imm == 4) || |
| 254 | (Imm == 8) || (Imm == 16) || |
| 255 | (Imm == 15) || (Imm == 31)); |
| 256 | } |
| 257 | case 34: { |
| 258 | // uimmlog2xlen |
| 259 | int64_t Imm; |
| 260 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 261 | return false; |
| 262 | if (STI.getTargetTriple().isArch64Bit()) |
| 263 | return isUInt<6>(x: Imm); |
| 264 | return isUInt<5>(x: Imm); |
| 265 | } |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | static bool compressInst(MCInst &OutInst, |
| 270 | const MCInst &MI, |
| 271 | const MCSubtargetInfo &STI) { |
| 272 | switch (MI.getOpcode()) { |
| 273 | default: return false; |
| 274 | case RISCV::ADD: { |
| 275 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 276 | MI.getOperand(i: 1).isReg() && |
| 277 | (MI.getOperand(i: 1).getReg() == RISCV::X0) && |
| 278 | MI.getOperand(i: 0).isReg() && |
| 279 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 280 | MI.getOperand(i: 2).isReg() && |
| 281 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 282 | // c.mv $rs1, $rs2 |
| 283 | OutInst.setOpcode(RISCV::C_MV); |
| 284 | // Operand: rs1 |
| 285 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 286 | // Operand: rs2 |
| 287 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 288 | OutInst.setLoc(MI.getLoc()); |
| 289 | return true; |
| 290 | } // if |
| 291 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 292 | MI.getOperand(i: 2).isReg() && |
| 293 | (MI.getOperand(i: 2).getReg() == RISCV::X0) && |
| 294 | MI.getOperand(i: 0).isReg() && |
| 295 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 296 | MI.getOperand(i: 1).isReg() && |
| 297 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 298 | // c.mv $rs1, $rs2 |
| 299 | OutInst.setOpcode(RISCV::C_MV); |
| 300 | // Operand: rs1 |
| 301 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 302 | // Operand: rs2 |
| 303 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 304 | OutInst.setLoc(MI.getLoc()); |
| 305 | return true; |
| 306 | } // if |
| 307 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 308 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 309 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 310 | MI.getOperand(i: 1).isReg() && |
| 311 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 312 | MI.getOperand(i: 2).isReg() && |
| 313 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 314 | // c.add $rs1, $rs2 |
| 315 | OutInst.setOpcode(RISCV::C_ADD); |
| 316 | // Operand: rd |
| 317 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 318 | // Operand: rs1 |
| 319 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 320 | // Operand: rs2 |
| 321 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 322 | OutInst.setLoc(MI.getLoc()); |
| 323 | return true; |
| 324 | } // if |
| 325 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 326 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 327 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 328 | MI.getOperand(i: 2).isReg() && |
| 329 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 330 | MI.getOperand(i: 1).isReg() && |
| 331 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 332 | // c.add $rs1, $rs2 |
| 333 | OutInst.setOpcode(RISCV::C_ADD); |
| 334 | // Operand: rd |
| 335 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 336 | // Operand: rs1 |
| 337 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 338 | // Operand: rs2 |
| 339 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 340 | OutInst.setLoc(MI.getLoc()); |
| 341 | return true; |
| 342 | } // if |
| 343 | break; |
| 344 | } // case ADD |
| 345 | case RISCV::ADDI: { |
| 346 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 347 | MI.getOperand(i: 0).isReg() && |
| 348 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 349 | MI.getOperand(i: 1).isReg() && |
| 350 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 351 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1 /* uimm10_lsb00nonzero */)) { |
| 352 | // c.addi4spn $rd, $rs1, $imm |
| 353 | OutInst.setOpcode(RISCV::C_ADDI4SPN); |
| 354 | // Operand: rd |
| 355 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 356 | // Operand: rs1 |
| 357 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 358 | // Operand: imm |
| 359 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 360 | OutInst.setLoc(MI.getLoc()); |
| 361 | return true; |
| 362 | } // if |
| 363 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 364 | MI.getOperand(i: 0).isReg() && |
| 365 | (MI.getOperand(i: 0).getReg() == RISCV::X0) && |
| 366 | MI.getOperand(i: 1).isReg() && |
| 367 | (MI.getOperand(i: 1).getReg() == RISCV::X0) && |
| 368 | MI.getOperand(i: 2).isImm() && |
| 369 | (MI.getOperand(i: 2).getImm() == 0)) { |
| 370 | // c.nop |
| 371 | OutInst.setOpcode(RISCV::C_NOP); |
| 372 | OutInst.setLoc(MI.getLoc()); |
| 373 | return true; |
| 374 | } // if |
| 375 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 376 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 377 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 378 | MI.getOperand(i: 1).isReg() && |
| 379 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 380 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2 /* simm6nonzero */) && |
| 381 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 382 | // c.addi $rd, $imm |
| 383 | OutInst.setOpcode(RISCV::C_ADDI); |
| 384 | // Operand: rd_wb |
| 385 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 386 | // Operand: rd |
| 387 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 388 | // Operand: imm |
| 389 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 390 | OutInst.setLoc(MI.getLoc()); |
| 391 | return true; |
| 392 | } // if |
| 393 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 394 | MI.getOperand(i: 1).isReg() && |
| 395 | (MI.getOperand(i: 1).getReg() == RISCV::X0) && |
| 396 | MI.getOperand(i: 0).isReg() && |
| 397 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 398 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 399 | // c.li $rd, $imm |
| 400 | OutInst.setOpcode(RISCV::C_LI); |
| 401 | // Operand: rd |
| 402 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 403 | // Operand: imm |
| 404 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 405 | OutInst.setLoc(MI.getLoc()); |
| 406 | return true; |
| 407 | } // if |
| 408 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 409 | MI.getOperand(i: 0).isReg() && |
| 410 | (MI.getOperand(i: 0).getReg() == RISCV::X2) && |
| 411 | MI.getOperand(i: 1).isReg() && |
| 412 | (MI.getOperand(i: 1).getReg() == RISCV::X2) && |
| 413 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 4 /* simm10_lsb0000nonzero */)) { |
| 414 | // c.addi16sp $rd, $imm |
| 415 | OutInst.setOpcode(RISCV::C_ADDI16SP); |
| 416 | // Operand: rd_wb |
| 417 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2)); |
| 418 | // Operand: rd |
| 419 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2)); |
| 420 | // Operand: imm |
| 421 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 422 | OutInst.setLoc(MI.getLoc()); |
| 423 | return true; |
| 424 | } // if |
| 425 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 426 | MI.getOperand(i: 2).isImm() && |
| 427 | (MI.getOperand(i: 2).getImm() == 0) && |
| 428 | MI.getOperand(i: 0).isReg() && |
| 429 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 430 | MI.getOperand(i: 1).isReg() && |
| 431 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 432 | // c.mv $rs1, $rs2 |
| 433 | OutInst.setOpcode(RISCV::C_MV); |
| 434 | // Operand: rs1 |
| 435 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 436 | // Operand: rs2 |
| 437 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 438 | OutInst.setLoc(MI.getLoc()); |
| 439 | return true; |
| 440 | } // if |
| 441 | break; |
| 442 | } // case ADDI |
| 443 | case RISCV::ADDIW: { |
| 444 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 445 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 446 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 447 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 448 | MI.getOperand(i: 1).isReg() && |
| 449 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 450 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 451 | // c.addiw $rd, $imm |
| 452 | OutInst.setOpcode(RISCV::C_ADDIW); |
| 453 | // Operand: rd_wb |
| 454 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 455 | // Operand: rd |
| 456 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 457 | // Operand: imm |
| 458 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 459 | OutInst.setLoc(MI.getLoc()); |
| 460 | return true; |
| 461 | } // if |
| 462 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 463 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 464 | MI.getOperand(i: 1).isReg() && |
| 465 | (MI.getOperand(i: 1).getReg() == RISCV::X0) && |
| 466 | MI.getOperand(i: 0).isReg() && |
| 467 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 468 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 469 | // c.li $rd, $imm |
| 470 | OutInst.setOpcode(RISCV::C_LI); |
| 471 | // Operand: rd |
| 472 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 473 | // Operand: imm |
| 474 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 475 | OutInst.setLoc(MI.getLoc()); |
| 476 | return true; |
| 477 | } // if |
| 478 | break; |
| 479 | } // case ADDIW |
| 480 | case RISCV::ADDW: { |
| 481 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 482 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 483 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 484 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 485 | MI.getOperand(i: 1).isReg() && |
| 486 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 487 | MI.getOperand(i: 2).isReg() && |
| 488 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 489 | // c.addw $rd, $rs2 |
| 490 | OutInst.setOpcode(RISCV::C_ADDW); |
| 491 | // Operand: rd_wb |
| 492 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 493 | // Operand: rd |
| 494 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 495 | // Operand: rs2 |
| 496 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 497 | OutInst.setLoc(MI.getLoc()); |
| 498 | return true; |
| 499 | } // if |
| 500 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 501 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 502 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 503 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 504 | MI.getOperand(i: 2).isReg() && |
| 505 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 506 | MI.getOperand(i: 1).isReg() && |
| 507 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 508 | // c.addw $rd, $rs2 |
| 509 | OutInst.setOpcode(RISCV::C_ADDW); |
| 510 | // Operand: rd_wb |
| 511 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 512 | // Operand: rd |
| 513 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 514 | // Operand: rs2 |
| 515 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 516 | OutInst.setLoc(MI.getLoc()); |
| 517 | return true; |
| 518 | } // if |
| 519 | break; |
| 520 | } // case ADDW |
| 521 | case RISCV::ADD_UW: { |
| 522 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 523 | STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 524 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 525 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 526 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 527 | MI.getOperand(i: 2).isReg() && |
| 528 | (MI.getOperand(i: 2).getReg() == RISCV::X0) && |
| 529 | MI.getOperand(i: 1).isReg() && |
| 530 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 531 | // c.zext.w $rd |
| 532 | OutInst.setOpcode(RISCV::C_ZEXT_W); |
| 533 | // Operand: rd_wb |
| 534 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 535 | // Operand: rd |
| 536 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 537 | OutInst.setLoc(MI.getLoc()); |
| 538 | return true; |
| 539 | } // if |
| 540 | break; |
| 541 | } // case ADD_UW |
| 542 | case RISCV::AND: { |
| 543 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 544 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 545 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 546 | MI.getOperand(i: 1).isReg() && |
| 547 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 548 | MI.getOperand(i: 2).isReg() && |
| 549 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 550 | // c.and $rd, $rs2 |
| 551 | OutInst.setOpcode(RISCV::C_AND); |
| 552 | // Operand: rd_wb |
| 553 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 554 | // Operand: rd |
| 555 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 556 | // Operand: rs2 |
| 557 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 558 | OutInst.setLoc(MI.getLoc()); |
| 559 | return true; |
| 560 | } // if |
| 561 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 562 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 563 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 564 | MI.getOperand(i: 2).isReg() && |
| 565 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 566 | MI.getOperand(i: 1).isReg() && |
| 567 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 568 | // c.and $rd, $rs2 |
| 569 | OutInst.setOpcode(RISCV::C_AND); |
| 570 | // Operand: rd_wb |
| 571 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 572 | // Operand: rd |
| 573 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 574 | // Operand: rs2 |
| 575 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 576 | OutInst.setLoc(MI.getLoc()); |
| 577 | return true; |
| 578 | } // if |
| 579 | break; |
| 580 | } // case AND |
| 581 | case RISCV::ANDI: { |
| 582 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 583 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 584 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 585 | MI.getOperand(i: 1).isReg() && |
| 586 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 587 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 588 | // c.andi $rs1, $imm |
| 589 | OutInst.setOpcode(RISCV::C_ANDI); |
| 590 | // Operand: rd |
| 591 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 592 | // Operand: rs1 |
| 593 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 594 | // Operand: imm |
| 595 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 596 | OutInst.setLoc(MI.getLoc()); |
| 597 | return true; |
| 598 | } // if |
| 599 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 600 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 601 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 602 | MI.getOperand(i: 2).isImm() && |
| 603 | (MI.getOperand(i: 2).getImm() == 255) && |
| 604 | MI.getOperand(i: 1).isReg() && |
| 605 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 606 | // c.zext.b $rd |
| 607 | OutInst.setOpcode(RISCV::C_ZEXT_B); |
| 608 | // Operand: rd_wb |
| 609 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 610 | // Operand: rd |
| 611 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 612 | OutInst.setLoc(MI.getLoc()); |
| 613 | return true; |
| 614 | } // if |
| 615 | break; |
| 616 | } // case ANDI |
| 617 | case RISCV::BEQ: { |
| 618 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 619 | MI.getOperand(i: 1).isReg() && |
| 620 | (MI.getOperand(i: 1).getReg() == RISCV::X0) && |
| 621 | MI.getOperand(i: 0).isReg() && |
| 622 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 623 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5 /* bare_simm9_lsb0 */)) { |
| 624 | // c.beqz $rs1, $imm |
| 625 | OutInst.setOpcode(RISCV::C_BEQZ); |
| 626 | // Operand: rs1 |
| 627 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 628 | // Operand: imm |
| 629 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 630 | OutInst.setLoc(MI.getLoc()); |
| 631 | return true; |
| 632 | } // if |
| 633 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 634 | MI.getOperand(i: 0).isReg() && |
| 635 | (MI.getOperand(i: 0).getReg() == RISCV::X0) && |
| 636 | MI.getOperand(i: 1).isReg() && |
| 637 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 638 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5 /* bare_simm9_lsb0 */)) { |
| 639 | // c.beqz $rs1, $imm |
| 640 | OutInst.setOpcode(RISCV::C_BEQZ); |
| 641 | // Operand: rs1 |
| 642 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 643 | // Operand: imm |
| 644 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 645 | OutInst.setLoc(MI.getLoc()); |
| 646 | return true; |
| 647 | } // if |
| 648 | break; |
| 649 | } // case BEQ |
| 650 | case RISCV::BEXTI: { |
| 651 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] && |
| 652 | STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 653 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 654 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 655 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 656 | MI.getOperand(i: 1).isReg() && |
| 657 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 658 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6 /* uimmlog2xlennonzero */)) { |
| 659 | // qc.c.bexti $rs1, $shamt |
| 660 | OutInst.setOpcode(RISCV::QC_C_BEXTI); |
| 661 | // Operand: rd |
| 662 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 663 | // Operand: rs1 |
| 664 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 665 | // Operand: shamt |
| 666 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 667 | OutInst.setLoc(MI.getLoc()); |
| 668 | return true; |
| 669 | } // if |
| 670 | break; |
| 671 | } // case BEXTI |
| 672 | case RISCV::BNE: { |
| 673 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 674 | MI.getOperand(i: 1).isReg() && |
| 675 | (MI.getOperand(i: 1).getReg() == RISCV::X0) && |
| 676 | MI.getOperand(i: 0).isReg() && |
| 677 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 678 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5 /* bare_simm9_lsb0 */)) { |
| 679 | // c.bnez $rs1, $imm |
| 680 | OutInst.setOpcode(RISCV::C_BNEZ); |
| 681 | // Operand: rs1 |
| 682 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 683 | // Operand: imm |
| 684 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 685 | OutInst.setLoc(MI.getLoc()); |
| 686 | return true; |
| 687 | } // if |
| 688 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 689 | MI.getOperand(i: 0).isReg() && |
| 690 | (MI.getOperand(i: 0).getReg() == RISCV::X0) && |
| 691 | MI.getOperand(i: 1).isReg() && |
| 692 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 693 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5 /* bare_simm9_lsb0 */)) { |
| 694 | // c.bnez $rs1, $imm |
| 695 | OutInst.setOpcode(RISCV::C_BNEZ); |
| 696 | // Operand: rs1 |
| 697 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 698 | // Operand: imm |
| 699 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 700 | OutInst.setLoc(MI.getLoc()); |
| 701 | return true; |
| 702 | } // if |
| 703 | break; |
| 704 | } // case BNE |
| 705 | case RISCV::BSETI: { |
| 706 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] && |
| 707 | STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 708 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 709 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 710 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 711 | MI.getOperand(i: 1).isReg() && |
| 712 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 713 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6 /* uimmlog2xlennonzero */)) { |
| 714 | // qc.c.bseti $rs1, $shamt |
| 715 | OutInst.setOpcode(RISCV::QC_C_BSETI); |
| 716 | // Operand: rd |
| 717 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 718 | // Operand: rs1 |
| 719 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 720 | // Operand: shamt |
| 721 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 722 | OutInst.setLoc(MI.getLoc()); |
| 723 | return true; |
| 724 | } // if |
| 725 | break; |
| 726 | } // case BSETI |
| 727 | case RISCV::EBREAK: { |
| 728 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) { |
| 729 | // c.ebreak |
| 730 | OutInst.setOpcode(RISCV::C_EBREAK); |
| 731 | OutInst.setLoc(MI.getLoc()); |
| 732 | return true; |
| 733 | } // if |
| 734 | break; |
| 735 | } // case EBREAK |
| 736 | case RISCV::FLD: { |
| 737 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 738 | MI.getOperand(i: 0).isReg() && |
| 739 | getRISCVMCRegisterClass(RC: RISCV::FPR64CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 740 | MI.getOperand(i: 1).isReg() && |
| 741 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 742 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7 /* uimm8_lsb000 */) && |
| 743 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000_optional */)) { |
| 744 | // c.fld $rd, ${imm}(${rs1}) |
| 745 | OutInst.setOpcode(RISCV::C_FLD); |
| 746 | // Operand: rd |
| 747 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 748 | // Operand: rs1 |
| 749 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 750 | // Operand: imm |
| 751 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 752 | OutInst.setLoc(MI.getLoc()); |
| 753 | return true; |
| 754 | } // if |
| 755 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 756 | MI.getOperand(i: 0).isReg() && |
| 757 | getRISCVMCRegisterClass(RC: RISCV::FPR64RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 758 | MI.getOperand(i: 1).isReg() && |
| 759 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 760 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* uimm9_lsb000 */) && |
| 761 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000_optional */)) { |
| 762 | // c.fldsp $rd, ${imm}(${rs1}) |
| 763 | OutInst.setOpcode(RISCV::C_FLDSP); |
| 764 | // Operand: rd |
| 765 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 766 | // Operand: rs1 |
| 767 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 768 | // Operand: imm |
| 769 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 770 | OutInst.setLoc(MI.getLoc()); |
| 771 | return true; |
| 772 | } // if |
| 773 | break; |
| 774 | } // case FLD |
| 775 | case RISCV::FLW: { |
| 776 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 777 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 778 | MI.getOperand(i: 0).isReg() && |
| 779 | getRISCVMCRegisterClass(RC: RISCV::FPR32CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 780 | MI.getOperand(i: 1).isReg() && |
| 781 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 782 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 783 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm7_lsb00_optional */)) { |
| 784 | // c.flw $rd, ${imm}(${rs1}) |
| 785 | OutInst.setOpcode(RISCV::C_FLW); |
| 786 | // Operand: rd |
| 787 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 788 | // Operand: rs1 |
| 789 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 790 | // Operand: imm |
| 791 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 792 | OutInst.setLoc(MI.getLoc()); |
| 793 | return true; |
| 794 | } // if |
| 795 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 796 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 797 | MI.getOperand(i: 0).isReg() && |
| 798 | getRISCVMCRegisterClass(RC: RISCV::FPR32RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 799 | MI.getOperand(i: 1).isReg() && |
| 800 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 801 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13 /* uimm8_lsb00 */) && |
| 802 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14 /* uimm8_lsb00_optional */)) { |
| 803 | // c.flwsp $rd, ${imm}(${rs1}) |
| 804 | OutInst.setOpcode(RISCV::C_FLWSP); |
| 805 | // Operand: rd |
| 806 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 807 | // Operand: rs1 |
| 808 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 809 | // Operand: imm |
| 810 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 811 | OutInst.setLoc(MI.getLoc()); |
| 812 | return true; |
| 813 | } // if |
| 814 | break; |
| 815 | } // case FLW |
| 816 | case RISCV::FSD: { |
| 817 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 818 | MI.getOperand(i: 0).isReg() && |
| 819 | getRISCVMCRegisterClass(RC: RISCV::FPR64CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 820 | MI.getOperand(i: 1).isReg() && |
| 821 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 822 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7 /* uimm8_lsb000 */) && |
| 823 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000_optional */)) { |
| 824 | // c.fsd $rs2, ${imm}(${rs1}) |
| 825 | OutInst.setOpcode(RISCV::C_FSD); |
| 826 | // Operand: rs2 |
| 827 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 828 | // Operand: rs1 |
| 829 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 830 | // Operand: imm |
| 831 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 832 | OutInst.setLoc(MI.getLoc()); |
| 833 | return true; |
| 834 | } // if |
| 835 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 836 | MI.getOperand(i: 0).isReg() && |
| 837 | getRISCVMCRegisterClass(RC: RISCV::FPR64RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 838 | MI.getOperand(i: 1).isReg() && |
| 839 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 840 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* uimm9_lsb000 */) && |
| 841 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000_optional */)) { |
| 842 | // c.fsdsp $rs2, ${imm}(${rs1}) |
| 843 | OutInst.setOpcode(RISCV::C_FSDSP); |
| 844 | // Operand: rs2 |
| 845 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 846 | // Operand: rs1 |
| 847 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 848 | // Operand: imm |
| 849 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 850 | OutInst.setLoc(MI.getLoc()); |
| 851 | return true; |
| 852 | } // if |
| 853 | break; |
| 854 | } // case FSD |
| 855 | case RISCV::FSW: { |
| 856 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 857 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 858 | MI.getOperand(i: 0).isReg() && |
| 859 | getRISCVMCRegisterClass(RC: RISCV::FPR32CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 860 | MI.getOperand(i: 1).isReg() && |
| 861 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 862 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 863 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm7_lsb00_optional */)) { |
| 864 | // c.fsw $rs2, ${imm}(${rs1}) |
| 865 | OutInst.setOpcode(RISCV::C_FSW); |
| 866 | // Operand: rs2 |
| 867 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 868 | // Operand: rs1 |
| 869 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 870 | // Operand: imm |
| 871 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 872 | OutInst.setLoc(MI.getLoc()); |
| 873 | return true; |
| 874 | } // if |
| 875 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 876 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 877 | MI.getOperand(i: 0).isReg() && |
| 878 | getRISCVMCRegisterClass(RC: RISCV::FPR32RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 879 | MI.getOperand(i: 1).isReg() && |
| 880 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 881 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13 /* uimm8_lsb00 */) && |
| 882 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14 /* uimm8_lsb00_optional */)) { |
| 883 | // c.fswsp $rs2, ${imm}(${rs1}) |
| 884 | OutInst.setOpcode(RISCV::C_FSWSP); |
| 885 | // Operand: rs2 |
| 886 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 887 | // Operand: rs1 |
| 888 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 889 | // Operand: imm |
| 890 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 891 | OutInst.setLoc(MI.getLoc()); |
| 892 | return true; |
| 893 | } // if |
| 894 | break; |
| 895 | } // case FSW |
| 896 | case RISCV::JAL: { |
| 897 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 898 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 899 | MI.getOperand(i: 0).isReg() && |
| 900 | (MI.getOperand(i: 0).getReg() == RISCV::X1) && |
| 901 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 15 /* bare_simm12_lsb0 */)) { |
| 902 | // c.jal $offset |
| 903 | OutInst.setOpcode(RISCV::C_JAL); |
| 904 | // Operand: offset |
| 905 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 906 | OutInst.setLoc(MI.getLoc()); |
| 907 | return true; |
| 908 | } // if |
| 909 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 910 | MI.getOperand(i: 0).isReg() && |
| 911 | (MI.getOperand(i: 0).getReg() == RISCV::X0) && |
| 912 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 15 /* bare_simm12_lsb0 */)) { |
| 913 | // c.j $offset |
| 914 | OutInst.setOpcode(RISCV::C_J); |
| 915 | // Operand: offset |
| 916 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 917 | OutInst.setLoc(MI.getLoc()); |
| 918 | return true; |
| 919 | } // if |
| 920 | break; |
| 921 | } // case JAL |
| 922 | case RISCV::JALR: { |
| 923 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 924 | MI.getOperand(i: 0).isReg() && |
| 925 | (MI.getOperand(i: 0).getReg() == RISCV::X0) && |
| 926 | MI.getOperand(i: 2).isImm() && |
| 927 | (MI.getOperand(i: 2).getImm() == 0) && |
| 928 | MI.getOperand(i: 1).isReg() && |
| 929 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 930 | // c.jr $rs1 |
| 931 | OutInst.setOpcode(RISCV::C_JR); |
| 932 | // Operand: rs1 |
| 933 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 934 | OutInst.setLoc(MI.getLoc()); |
| 935 | return true; |
| 936 | } // if |
| 937 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 938 | MI.getOperand(i: 0).isReg() && |
| 939 | (MI.getOperand(i: 0).getReg() == RISCV::X1) && |
| 940 | MI.getOperand(i: 2).isImm() && |
| 941 | (MI.getOperand(i: 2).getImm() == 0) && |
| 942 | MI.getOperand(i: 1).isReg() && |
| 943 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 944 | // c.jalr $rs1 |
| 945 | OutInst.setOpcode(RISCV::C_JALR); |
| 946 | // Operand: rs1 |
| 947 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 948 | OutInst.setLoc(MI.getLoc()); |
| 949 | return true; |
| 950 | } // if |
| 951 | break; |
| 952 | } // case JALR |
| 953 | case RISCV::LBU: { |
| 954 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 955 | MI.getOperand(i: 0).isReg() && |
| 956 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 957 | MI.getOperand(i: 1).isReg() && |
| 958 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 959 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16 /* uimm2 */) && |
| 960 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 17 /* uimm2_optional */)) { |
| 961 | // c.lbu $rd, ${imm}(${rs1}) |
| 962 | OutInst.setOpcode(RISCV::C_LBU); |
| 963 | // Operand: rd |
| 964 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 965 | // Operand: rs1 |
| 966 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 967 | // Operand: imm |
| 968 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 969 | OutInst.setLoc(MI.getLoc()); |
| 970 | return true; |
| 971 | } // if |
| 972 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 973 | MI.getOperand(i: 0).isReg() && |
| 974 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 975 | MI.getOperand(i: 1).isReg() && |
| 976 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 977 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 18 /* uimm5 */)) { |
| 978 | // qk.c.lbu $rd, ${imm}(${rs1}) |
| 979 | OutInst.setOpcode(RISCV::QK_C_LBU); |
| 980 | // Operand: rd |
| 981 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 982 | // Operand: rs1 |
| 983 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 984 | // Operand: imm |
| 985 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 986 | OutInst.setLoc(MI.getLoc()); |
| 987 | return true; |
| 988 | } // if |
| 989 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 990 | MI.getOperand(i: 0).isReg() && |
| 991 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 992 | MI.getOperand(i: 1).isReg() && |
| 993 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 994 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 19 /* uimm4 */)) { |
| 995 | // qk.c.lbusp $rd_rs2, ${imm}(${rs1}) |
| 996 | OutInst.setOpcode(RISCV::QK_C_LBUSP); |
| 997 | // Operand: rd_rs2 |
| 998 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 999 | // Operand: rs1 |
| 1000 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1001 | // Operand: imm |
| 1002 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1003 | OutInst.setLoc(MI.getLoc()); |
| 1004 | return true; |
| 1005 | } // if |
| 1006 | break; |
| 1007 | } // case LBU |
| 1008 | case RISCV::LD: { |
| 1009 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1010 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1011 | MI.getOperand(i: 0).isReg() && |
| 1012 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1013 | MI.getOperand(i: 1).isReg() && |
| 1014 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1015 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7 /* uimm8_lsb000 */) && |
| 1016 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000_optional */)) { |
| 1017 | // c.ld $rd, ${imm}(${rs1}) |
| 1018 | OutInst.setOpcode(RISCV::C_LD); |
| 1019 | // Operand: rd |
| 1020 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1021 | // Operand: rs1 |
| 1022 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1023 | // Operand: imm |
| 1024 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1025 | OutInst.setLoc(MI.getLoc()); |
| 1026 | return true; |
| 1027 | } // if |
| 1028 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1029 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1030 | MI.getOperand(i: 0).isReg() && |
| 1031 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1032 | MI.getOperand(i: 1).isReg() && |
| 1033 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1034 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* uimm9_lsb000 */) && |
| 1035 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000_optional */)) { |
| 1036 | // c.ldsp $rd, ${imm}(${rs1}) |
| 1037 | OutInst.setOpcode(RISCV::C_LDSP); |
| 1038 | // Operand: rd |
| 1039 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1040 | // Operand: rs1 |
| 1041 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1042 | // Operand: imm |
| 1043 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1044 | OutInst.setLoc(MI.getLoc()); |
| 1045 | return true; |
| 1046 | } // if |
| 1047 | break; |
| 1048 | } // case LD |
| 1049 | case RISCV::LD_RV32: { |
| 1050 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 1051 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1052 | MI.getOperand(i: 0).isReg() && |
| 1053 | getRISCVMCRegisterClass(RC: RISCV::GPRPairNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1054 | MI.getOperand(i: 1).isReg() && |
| 1055 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1056 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* uimm9_lsb000 */) && |
| 1057 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000_optional */)) { |
| 1058 | // c.ldsp $rd, ${imm}(${rs1}) |
| 1059 | OutInst.setOpcode(RISCV::C_LDSP_RV32); |
| 1060 | // Operand: rd |
| 1061 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1062 | // Operand: rs1 |
| 1063 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1064 | // Operand: imm |
| 1065 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1066 | OutInst.setLoc(MI.getLoc()); |
| 1067 | return true; |
| 1068 | } // if |
| 1069 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 1070 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1071 | MI.getOperand(i: 0).isReg() && |
| 1072 | getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1073 | MI.getOperand(i: 1).isReg() && |
| 1074 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1075 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7 /* uimm8_lsb000 */) && |
| 1076 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000_optional */)) { |
| 1077 | // c.ld $rd, ${imm}(${rs1}) |
| 1078 | OutInst.setOpcode(RISCV::C_LD_RV32); |
| 1079 | // Operand: rd |
| 1080 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1081 | // Operand: rs1 |
| 1082 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1083 | // Operand: imm |
| 1084 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1085 | OutInst.setLoc(MI.getLoc()); |
| 1086 | return true; |
| 1087 | } // if |
| 1088 | break; |
| 1089 | } // case LD_RV32 |
| 1090 | case RISCV::LH: { |
| 1091 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 1092 | MI.getOperand(i: 0).isReg() && |
| 1093 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1094 | MI.getOperand(i: 1).isReg() && |
| 1095 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1096 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimm2_lsb0 */) && |
| 1097 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimm2_lsb0_optional */)) { |
| 1098 | // c.lh $rd, ${imm}(${rs1}) |
| 1099 | OutInst.setOpcode(RISCV::C_LH); |
| 1100 | // Operand: rd |
| 1101 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1102 | // Operand: rs1 |
| 1103 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1104 | // Operand: imm |
| 1105 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1106 | OutInst.setLoc(MI.getLoc()); |
| 1107 | return true; |
| 1108 | } // if |
| 1109 | break; |
| 1110 | } // case LH |
| 1111 | case RISCV::LHU: { |
| 1112 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 1113 | MI.getOperand(i: 0).isReg() && |
| 1114 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1115 | MI.getOperand(i: 1).isReg() && |
| 1116 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1117 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimm2_lsb0 */) && |
| 1118 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimm2_lsb0_optional */)) { |
| 1119 | // c.lhu $rd, ${imm}(${rs1}) |
| 1120 | OutInst.setOpcode(RISCV::C_LHU); |
| 1121 | // Operand: rd |
| 1122 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1123 | // Operand: rs1 |
| 1124 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1125 | // Operand: imm |
| 1126 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1127 | OutInst.setLoc(MI.getLoc()); |
| 1128 | return true; |
| 1129 | } // if |
| 1130 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 1131 | MI.getOperand(i: 0).isReg() && |
| 1132 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1133 | MI.getOperand(i: 1).isReg() && |
| 1134 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1135 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 22 /* uimm6_lsb0 */)) { |
| 1136 | // qk.c.lhu $rd, ${imm}(${rs1}) |
| 1137 | OutInst.setOpcode(RISCV::QK_C_LHU); |
| 1138 | // Operand: rd |
| 1139 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1140 | // Operand: rs1 |
| 1141 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1142 | // Operand: imm |
| 1143 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1144 | OutInst.setLoc(MI.getLoc()); |
| 1145 | return true; |
| 1146 | } // if |
| 1147 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 1148 | MI.getOperand(i: 0).isReg() && |
| 1149 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1150 | MI.getOperand(i: 1).isReg() && |
| 1151 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1152 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 23 /* uimm5_lsb0 */)) { |
| 1153 | // qk.c.lhusp $rd_rs2, ${imm}(${rs1}) |
| 1154 | OutInst.setOpcode(RISCV::QK_C_LHUSP); |
| 1155 | // Operand: rd_rs2 |
| 1156 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1157 | // Operand: rs1 |
| 1158 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1159 | // Operand: imm |
| 1160 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1161 | OutInst.setLoc(MI.getLoc()); |
| 1162 | return true; |
| 1163 | } // if |
| 1164 | break; |
| 1165 | } // case LHU |
| 1166 | case RISCV::LH_INX: { |
| 1167 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 1168 | MI.getOperand(i: 0).isReg() && |
| 1169 | getRISCVMCRegisterClass(RC: RISCV::GPRF16CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1170 | MI.getOperand(i: 1).isReg() && |
| 1171 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1172 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimm2_lsb0 */) && |
| 1173 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimm2_lsb0_optional */)) { |
| 1174 | // c.lh $rd, ${imm}(${rs1}) |
| 1175 | OutInst.setOpcode(RISCV::C_LH_INX); |
| 1176 | // Operand: rd |
| 1177 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1178 | // Operand: rs1 |
| 1179 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1180 | // Operand: imm |
| 1181 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1182 | OutInst.setLoc(MI.getLoc()); |
| 1183 | return true; |
| 1184 | } // if |
| 1185 | break; |
| 1186 | } // case LH_INX |
| 1187 | case RISCV::LUI: { |
| 1188 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1189 | MI.getOperand(i: 0).isReg() && |
| 1190 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0X2RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1191 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 24 /* c_lui_imm */)) { |
| 1192 | // c.lui $rd, $imm |
| 1193 | OutInst.setOpcode(RISCV::C_LUI); |
| 1194 | // Operand: rd |
| 1195 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1196 | // Operand: imm |
| 1197 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1198 | OutInst.setLoc(MI.getLoc()); |
| 1199 | return true; |
| 1200 | } // if |
| 1201 | break; |
| 1202 | } // case LUI |
| 1203 | case RISCV::LW: { |
| 1204 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1205 | MI.getOperand(i: 0).isReg() && |
| 1206 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1207 | MI.getOperand(i: 1).isReg() && |
| 1208 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1209 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 1210 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm7_lsb00_optional */)) { |
| 1211 | // c.lw $rd, ${imm}(${rs1}) |
| 1212 | OutInst.setOpcode(RISCV::C_LW); |
| 1213 | // Operand: rd |
| 1214 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1215 | // Operand: rs1 |
| 1216 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1217 | // Operand: imm |
| 1218 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1219 | OutInst.setLoc(MI.getLoc()); |
| 1220 | return true; |
| 1221 | } // if |
| 1222 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1223 | MI.getOperand(i: 0).isReg() && |
| 1224 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1225 | MI.getOperand(i: 1).isReg() && |
| 1226 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1227 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13 /* uimm8_lsb00 */) && |
| 1228 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14 /* uimm8_lsb00_optional */)) { |
| 1229 | // c.lwsp $rd, ${imm}(${rs1}) |
| 1230 | OutInst.setOpcode(RISCV::C_LWSP); |
| 1231 | // Operand: rd |
| 1232 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1233 | // Operand: rs1 |
| 1234 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1235 | // Operand: imm |
| 1236 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1237 | OutInst.setLoc(MI.getLoc()); |
| 1238 | return true; |
| 1239 | } // if |
| 1240 | break; |
| 1241 | } // case LW |
| 1242 | case RISCV::LW_INX: { |
| 1243 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1244 | MI.getOperand(i: 0).isReg() && |
| 1245 | getRISCVMCRegisterClass(RC: RISCV::GPRF32CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1246 | MI.getOperand(i: 1).isReg() && |
| 1247 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1248 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 1249 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm7_lsb00_optional */)) { |
| 1250 | // c.lw $rd, ${imm}(${rs1}) |
| 1251 | OutInst.setOpcode(RISCV::C_LW_INX); |
| 1252 | // Operand: rd |
| 1253 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1254 | // Operand: rs1 |
| 1255 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1256 | // Operand: imm |
| 1257 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1258 | OutInst.setLoc(MI.getLoc()); |
| 1259 | return true; |
| 1260 | } // if |
| 1261 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1262 | MI.getOperand(i: 0).isReg() && |
| 1263 | getRISCVMCRegisterClass(RC: RISCV::GPRF32NoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1264 | MI.getOperand(i: 1).isReg() && |
| 1265 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1266 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13 /* uimm8_lsb00 */) && |
| 1267 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14 /* uimm8_lsb00_optional */)) { |
| 1268 | // c.lwsp $rd, ${imm}(${rs1}) |
| 1269 | OutInst.setOpcode(RISCV::C_LWSP_INX); |
| 1270 | // Operand: rd |
| 1271 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1272 | // Operand: rs1 |
| 1273 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1274 | // Operand: imm |
| 1275 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1276 | OutInst.setLoc(MI.getLoc()); |
| 1277 | return true; |
| 1278 | } // if |
| 1279 | break; |
| 1280 | } // case LW_INX |
| 1281 | case RISCV::MUL: { |
| 1282 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 1283 | STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] && |
| 1284 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 1285 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 1286 | MI.getOperand(i: 1).isReg() && |
| 1287 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1288 | MI.getOperand(i: 2).isReg() && |
| 1289 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 1290 | // c.mul $rd, $rs2 |
| 1291 | OutInst.setOpcode(RISCV::C_MUL); |
| 1292 | // Operand: rd_wb |
| 1293 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1294 | // Operand: rd |
| 1295 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1296 | // Operand: rs2 |
| 1297 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1298 | OutInst.setLoc(MI.getLoc()); |
| 1299 | return true; |
| 1300 | } // if |
| 1301 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 1302 | STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] && |
| 1303 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 1304 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 1305 | MI.getOperand(i: 2).isReg() && |
| 1306 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 1307 | MI.getOperand(i: 1).isReg() && |
| 1308 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 1309 | // c.mul $rd, $rs2 |
| 1310 | OutInst.setOpcode(RISCV::C_MUL); |
| 1311 | // Operand: rd_wb |
| 1312 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1313 | // Operand: rd |
| 1314 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1315 | // Operand: rs2 |
| 1316 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1317 | OutInst.setLoc(MI.getLoc()); |
| 1318 | return true; |
| 1319 | } // if |
| 1320 | break; |
| 1321 | } // case MUL |
| 1322 | case RISCV::OR: { |
| 1323 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1324 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 1325 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 1326 | MI.getOperand(i: 1).isReg() && |
| 1327 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1328 | MI.getOperand(i: 2).isReg() && |
| 1329 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 1330 | // c.or $rd, $rs2 |
| 1331 | OutInst.setOpcode(RISCV::C_OR); |
| 1332 | // Operand: rd_wb |
| 1333 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1334 | // Operand: rd |
| 1335 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1336 | // Operand: rs2 |
| 1337 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1338 | OutInst.setLoc(MI.getLoc()); |
| 1339 | return true; |
| 1340 | } // if |
| 1341 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1342 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 1343 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 1344 | MI.getOperand(i: 2).isReg() && |
| 1345 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 1346 | MI.getOperand(i: 1).isReg() && |
| 1347 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 1348 | // c.or $rd, $rs2 |
| 1349 | OutInst.setOpcode(RISCV::C_OR); |
| 1350 | // Operand: rd_wb |
| 1351 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1352 | // Operand: rd |
| 1353 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1354 | // Operand: rs2 |
| 1355 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1356 | OutInst.setLoc(MI.getLoc()); |
| 1357 | return true; |
| 1358 | } // if |
| 1359 | break; |
| 1360 | } // case OR |
| 1361 | case RISCV::QC_EXTU: { |
| 1362 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 1363 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1364 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 1365 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 1366 | MI.getOperand(i: 3).isImm() && |
| 1367 | (MI.getOperand(i: 3).getImm() == 0) && |
| 1368 | MI.getOperand(i: 1).isReg() && |
| 1369 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1370 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 25 /* uimm5ge6_plus1 */)) { |
| 1371 | // qc.c.extu $rd, $width |
| 1372 | OutInst.setOpcode(RISCV::QC_C_EXTU); |
| 1373 | // Operand: rd_wb |
| 1374 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1375 | // Operand: rd |
| 1376 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1377 | // Operand: width |
| 1378 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1379 | OutInst.setLoc(MI.getLoc()); |
| 1380 | return true; |
| 1381 | } // if |
| 1382 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] && |
| 1383 | STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 1384 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1385 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 1386 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 1387 | MI.getOperand(i: 2).isImm() && |
| 1388 | (MI.getOperand(i: 2).getImm() == 1) && |
| 1389 | MI.getOperand(i: 1).isReg() && |
| 1390 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1391 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 3), STI, PredicateIndex: 6 /* uimmlog2xlennonzero */)) { |
| 1392 | // qc.c.bexti $rs1, $shamt |
| 1393 | OutInst.setOpcode(RISCV::QC_C_BEXTI); |
| 1394 | // Operand: rd |
| 1395 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1396 | // Operand: rs1 |
| 1397 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1398 | // Operand: shamt |
| 1399 | OutInst.addOperand(Op: MI.getOperand(i: 3)); |
| 1400 | OutInst.setLoc(MI.getLoc()); |
| 1401 | return true; |
| 1402 | } // if |
| 1403 | break; |
| 1404 | } // case QC_EXTU |
| 1405 | case RISCV::QC_E_ADDAI: { |
| 1406 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1407 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1408 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1409 | MI.getOperand(i: 0).isReg() && |
| 1410 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1411 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2 /* simm6nonzero */) && |
| 1412 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 1413 | // c.addi $rd, $imm |
| 1414 | OutInst.setOpcode(RISCV::C_ADDI); |
| 1415 | // Operand: rd_wb |
| 1416 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1417 | // Operand: rd |
| 1418 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1419 | // Operand: imm |
| 1420 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1421 | OutInst.setLoc(MI.getLoc()); |
| 1422 | return true; |
| 1423 | } // if |
| 1424 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1425 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1426 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1427 | MI.getOperand(i: 0).isReg() && |
| 1428 | (MI.getOperand(i: 0).getReg() == RISCV::X2) && |
| 1429 | MI.getOperand(i: 1).isReg() && |
| 1430 | (MI.getOperand(i: 1).getReg() == RISCV::X2) && |
| 1431 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 4 /* simm10_lsb0000nonzero */)) { |
| 1432 | // c.addi16sp $rd, $imm |
| 1433 | OutInst.setOpcode(RISCV::C_ADDI16SP); |
| 1434 | // Operand: rd_wb |
| 1435 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2)); |
| 1436 | // Operand: rd |
| 1437 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2)); |
| 1438 | // Operand: imm |
| 1439 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1440 | OutInst.setLoc(MI.getLoc()); |
| 1441 | return true; |
| 1442 | } // if |
| 1443 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1444 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1445 | MI.getOperand(i: 0).isReg() && |
| 1446 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1447 | MI.getOperand(i: 0).isReg() && |
| 1448 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1449 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */)) { |
| 1450 | // addi $rd, $rs1, $imm12 |
| 1451 | OutInst.setOpcode(RISCV::ADDI); |
| 1452 | // Operand: rd |
| 1453 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1454 | // Operand: rs1 |
| 1455 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1456 | // Operand: imm12 |
| 1457 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1458 | OutInst.setLoc(MI.getLoc()); |
| 1459 | return true; |
| 1460 | } // if |
| 1461 | break; |
| 1462 | } // case QC_E_ADDAI |
| 1463 | case RISCV::QC_E_ADDI: { |
| 1464 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1465 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1466 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1467 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 1468 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 1469 | MI.getOperand(i: 1).isReg() && |
| 1470 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1471 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2 /* simm6nonzero */) && |
| 1472 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 1473 | // c.addi $rd, $imm |
| 1474 | OutInst.setOpcode(RISCV::C_ADDI); |
| 1475 | // Operand: rd_wb |
| 1476 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1477 | // Operand: rd |
| 1478 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1479 | // Operand: imm |
| 1480 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1481 | OutInst.setLoc(MI.getLoc()); |
| 1482 | return true; |
| 1483 | } // if |
| 1484 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1485 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1486 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1487 | MI.getOperand(i: 2).isImm() && |
| 1488 | (MI.getOperand(i: 2).getImm() == 0) && |
| 1489 | MI.getOperand(i: 0).isReg() && |
| 1490 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1491 | MI.getOperand(i: 1).isReg() && |
| 1492 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 1493 | // c.mv $rs1, $rs2 |
| 1494 | OutInst.setOpcode(RISCV::C_MV); |
| 1495 | // Operand: rs1 |
| 1496 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1497 | // Operand: rs2 |
| 1498 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1499 | OutInst.setLoc(MI.getLoc()); |
| 1500 | return true; |
| 1501 | } // if |
| 1502 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1503 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1504 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1505 | MI.getOperand(i: 0).isReg() && |
| 1506 | (MI.getOperand(i: 0).getReg() == RISCV::X2) && |
| 1507 | MI.getOperand(i: 1).isReg() && |
| 1508 | (MI.getOperand(i: 1).getReg() == RISCV::X2) && |
| 1509 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 4 /* simm10_lsb0000nonzero */)) { |
| 1510 | // c.addi16sp $rd, $imm |
| 1511 | OutInst.setOpcode(RISCV::C_ADDI16SP); |
| 1512 | // Operand: rd_wb |
| 1513 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2)); |
| 1514 | // Operand: rd |
| 1515 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2)); |
| 1516 | // Operand: imm |
| 1517 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1518 | OutInst.setLoc(MI.getLoc()); |
| 1519 | return true; |
| 1520 | } // if |
| 1521 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1522 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1523 | MI.getOperand(i: 0).isReg() && |
| 1524 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1525 | MI.getOperand(i: 1).isReg() && |
| 1526 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1527 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */)) { |
| 1528 | // addi $rd, $rs1, $imm12 |
| 1529 | OutInst.setOpcode(RISCV::ADDI); |
| 1530 | // Operand: rd |
| 1531 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1532 | // Operand: rs1 |
| 1533 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1534 | // Operand: imm12 |
| 1535 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1536 | OutInst.setLoc(MI.getLoc()); |
| 1537 | return true; |
| 1538 | } // if |
| 1539 | break; |
| 1540 | } // case QC_E_ADDI |
| 1541 | case RISCV::QC_E_ANDAI: { |
| 1542 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1543 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1544 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1545 | MI.getOperand(i: 0).isReg() && |
| 1546 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1547 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 1548 | // c.andi $rs1, $imm |
| 1549 | OutInst.setOpcode(RISCV::C_ANDI); |
| 1550 | // Operand: rd |
| 1551 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1552 | // Operand: rs1 |
| 1553 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1554 | // Operand: imm |
| 1555 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1556 | OutInst.setLoc(MI.getLoc()); |
| 1557 | return true; |
| 1558 | } // if |
| 1559 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1560 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1561 | MI.getOperand(i: 0).isReg() && |
| 1562 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1563 | MI.getOperand(i: 0).isReg() && |
| 1564 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1565 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */)) { |
| 1566 | // andi $rd, $rs1, $imm12 |
| 1567 | OutInst.setOpcode(RISCV::ANDI); |
| 1568 | // Operand: rd |
| 1569 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1570 | // Operand: rs1 |
| 1571 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1572 | // Operand: imm12 |
| 1573 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1574 | OutInst.setLoc(MI.getLoc()); |
| 1575 | return true; |
| 1576 | } // if |
| 1577 | break; |
| 1578 | } // case QC_E_ANDAI |
| 1579 | case RISCV::QC_E_ANDI: { |
| 1580 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1581 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1582 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1583 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 1584 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 1585 | MI.getOperand(i: 1).isReg() && |
| 1586 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1587 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm6 */)) { |
| 1588 | // c.andi $rs1, $imm |
| 1589 | OutInst.setOpcode(RISCV::C_ANDI); |
| 1590 | // Operand: rd |
| 1591 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1592 | // Operand: rs1 |
| 1593 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1594 | // Operand: imm |
| 1595 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1596 | OutInst.setLoc(MI.getLoc()); |
| 1597 | return true; |
| 1598 | } // if |
| 1599 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 1600 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1601 | MI.getOperand(i: 0).isReg() && |
| 1602 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1603 | MI.getOperand(i: 1).isReg() && |
| 1604 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1605 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */)) { |
| 1606 | // andi $rd, $rs1, $imm12 |
| 1607 | OutInst.setOpcode(RISCV::ANDI); |
| 1608 | // Operand: rd |
| 1609 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1610 | // Operand: rs1 |
| 1611 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1612 | // Operand: imm12 |
| 1613 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1614 | OutInst.setLoc(MI.getLoc()); |
| 1615 | return true; |
| 1616 | } // if |
| 1617 | break; |
| 1618 | } // case QC_E_ANDI |
| 1619 | case RISCV::QC_E_BEQI: { |
| 1620 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 1621 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1622 | MI.getOperand(i: 0).isReg() && |
| 1623 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1624 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 27 /* simm5nonzero */) && |
| 1625 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 28 /* bare_simm13_lsb0 */)) { |
| 1626 | // qc.beqi $rs1, $rs2, $imm12 |
| 1627 | OutInst.setOpcode(RISCV::QC_BEQI); |
| 1628 | // Operand: rs1 |
| 1629 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1630 | // Operand: rs2 |
| 1631 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1632 | // Operand: imm12 |
| 1633 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1634 | OutInst.setLoc(MI.getLoc()); |
| 1635 | return true; |
| 1636 | } // if |
| 1637 | break; |
| 1638 | } // case QC_E_BEQI |
| 1639 | case RISCV::QC_E_BGEI: { |
| 1640 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 1641 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1642 | MI.getOperand(i: 0).isReg() && |
| 1643 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1644 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 27 /* simm5nonzero */) && |
| 1645 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 28 /* bare_simm13_lsb0 */)) { |
| 1646 | // qc.bgei $rs1, $rs2, $imm12 |
| 1647 | OutInst.setOpcode(RISCV::QC_BGEI); |
| 1648 | // Operand: rs1 |
| 1649 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1650 | // Operand: rs2 |
| 1651 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1652 | // Operand: imm12 |
| 1653 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1654 | OutInst.setLoc(MI.getLoc()); |
| 1655 | return true; |
| 1656 | } // if |
| 1657 | break; |
| 1658 | } // case QC_E_BGEI |
| 1659 | case RISCV::QC_E_BGEUI: { |
| 1660 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 1661 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1662 | MI.getOperand(i: 0).isReg() && |
| 1663 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1664 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 29 /* uimm5nonzero */) && |
| 1665 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 28 /* bare_simm13_lsb0 */)) { |
| 1666 | // qc.bgeui $rs1, $rs2, $imm12 |
| 1667 | OutInst.setOpcode(RISCV::QC_BGEUI); |
| 1668 | // Operand: rs1 |
| 1669 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1670 | // Operand: rs2 |
| 1671 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1672 | // Operand: imm12 |
| 1673 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1674 | OutInst.setLoc(MI.getLoc()); |
| 1675 | return true; |
| 1676 | } // if |
| 1677 | break; |
| 1678 | } // case QC_E_BGEUI |
| 1679 | case RISCV::QC_E_BLTI: { |
| 1680 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 1681 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1682 | MI.getOperand(i: 0).isReg() && |
| 1683 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1684 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 27 /* simm5nonzero */) && |
| 1685 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 28 /* bare_simm13_lsb0 */)) { |
| 1686 | // qc.blti $rs1, $rs2, $imm12 |
| 1687 | OutInst.setOpcode(RISCV::QC_BLTI); |
| 1688 | // Operand: rs1 |
| 1689 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1690 | // Operand: rs2 |
| 1691 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1692 | // Operand: imm12 |
| 1693 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1694 | OutInst.setLoc(MI.getLoc()); |
| 1695 | return true; |
| 1696 | } // if |
| 1697 | break; |
| 1698 | } // case QC_E_BLTI |
| 1699 | case RISCV::QC_E_BLTUI: { |
| 1700 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 1701 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1702 | MI.getOperand(i: 0).isReg() && |
| 1703 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1704 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 29 /* uimm5nonzero */) && |
| 1705 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 28 /* bare_simm13_lsb0 */)) { |
| 1706 | // qc.bltui $rs1, $rs2, $imm12 |
| 1707 | OutInst.setOpcode(RISCV::QC_BLTUI); |
| 1708 | // Operand: rs1 |
| 1709 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1710 | // Operand: rs2 |
| 1711 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1712 | // Operand: imm12 |
| 1713 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1714 | OutInst.setLoc(MI.getLoc()); |
| 1715 | return true; |
| 1716 | } // if |
| 1717 | break; |
| 1718 | } // case QC_E_BLTUI |
| 1719 | case RISCV::QC_E_BNEI: { |
| 1720 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 1721 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1722 | MI.getOperand(i: 0).isReg() && |
| 1723 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1724 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 27 /* simm5nonzero */) && |
| 1725 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 28 /* bare_simm13_lsb0 */)) { |
| 1726 | // qc.bnei $rs1, $rs2, $imm12 |
| 1727 | OutInst.setOpcode(RISCV::QC_BNEI); |
| 1728 | // Operand: rs1 |
| 1729 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1730 | // Operand: rs2 |
| 1731 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1732 | // Operand: imm12 |
| 1733 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1734 | OutInst.setLoc(MI.getLoc()); |
| 1735 | return true; |
| 1736 | } // if |
| 1737 | break; |
| 1738 | } // case QC_E_BNEI |
| 1739 | case RISCV::QC_E_J: { |
| 1740 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1741 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] && |
| 1742 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1743 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 15 /* bare_simm12_lsb0 */)) { |
| 1744 | // c.j $offset |
| 1745 | OutInst.setOpcode(RISCV::C_J); |
| 1746 | // Operand: offset |
| 1747 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1748 | OutInst.setLoc(MI.getLoc()); |
| 1749 | return true; |
| 1750 | } // if |
| 1751 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] && |
| 1752 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1753 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 30 /* simm21_lsb0_jal */)) { |
| 1754 | // jal $rd, $imm20 |
| 1755 | OutInst.setOpcode(RISCV::JAL); |
| 1756 | // Operand: rd |
| 1757 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 1758 | // Operand: imm20 |
| 1759 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1760 | OutInst.setLoc(MI.getLoc()); |
| 1761 | return true; |
| 1762 | } // if |
| 1763 | break; |
| 1764 | } // case QC_E_J |
| 1765 | case RISCV::QC_E_JAL: { |
| 1766 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1767 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] && |
| 1768 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1769 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 15 /* bare_simm12_lsb0 */)) { |
| 1770 | // c.jal $offset |
| 1771 | OutInst.setOpcode(RISCV::C_JAL); |
| 1772 | // Operand: offset |
| 1773 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1774 | OutInst.setLoc(MI.getLoc()); |
| 1775 | return true; |
| 1776 | } // if |
| 1777 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] && |
| 1778 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1779 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 30 /* simm21_lsb0_jal */)) { |
| 1780 | // jal $rd, $imm20 |
| 1781 | OutInst.setOpcode(RISCV::JAL); |
| 1782 | // Operand: rd |
| 1783 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1)); |
| 1784 | // Operand: imm20 |
| 1785 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1786 | OutInst.setLoc(MI.getLoc()); |
| 1787 | return true; |
| 1788 | } // if |
| 1789 | break; |
| 1790 | } // case QC_E_JAL |
| 1791 | case RISCV::QC_E_LB: { |
| 1792 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1793 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1794 | MI.getOperand(i: 0).isReg() && |
| 1795 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1796 | MI.getOperand(i: 1).isReg() && |
| 1797 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1798 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */) && |
| 1799 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 31 /* simm12_lo_optional */)) { |
| 1800 | // lb $rd, ${imm12}(${rs1}) |
| 1801 | OutInst.setOpcode(RISCV::LB); |
| 1802 | // Operand: rd |
| 1803 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1804 | // Operand: rs1 |
| 1805 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1806 | // Operand: imm12 |
| 1807 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1808 | OutInst.setLoc(MI.getLoc()); |
| 1809 | return true; |
| 1810 | } // if |
| 1811 | break; |
| 1812 | } // case QC_E_LB |
| 1813 | case RISCV::QC_E_LBU: { |
| 1814 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 1815 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1816 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1817 | MI.getOperand(i: 0).isReg() && |
| 1818 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1819 | MI.getOperand(i: 1).isReg() && |
| 1820 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1821 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16 /* uimm2 */) && |
| 1822 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 17 /* uimm2_optional */)) { |
| 1823 | // c.lbu $rd, ${imm}(${rs1}) |
| 1824 | OutInst.setOpcode(RISCV::C_LBU); |
| 1825 | // Operand: rd |
| 1826 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1827 | // Operand: rs1 |
| 1828 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1829 | // Operand: imm |
| 1830 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1831 | OutInst.setLoc(MI.getLoc()); |
| 1832 | return true; |
| 1833 | } // if |
| 1834 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1835 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1836 | MI.getOperand(i: 0).isReg() && |
| 1837 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1838 | MI.getOperand(i: 1).isReg() && |
| 1839 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1840 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */) && |
| 1841 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 31 /* simm12_lo_optional */)) { |
| 1842 | // lbu $rd, ${imm12}(${rs1}) |
| 1843 | OutInst.setOpcode(RISCV::LBU); |
| 1844 | // Operand: rd |
| 1845 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1846 | // Operand: rs1 |
| 1847 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1848 | // Operand: imm12 |
| 1849 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1850 | OutInst.setLoc(MI.getLoc()); |
| 1851 | return true; |
| 1852 | } // if |
| 1853 | break; |
| 1854 | } // case QC_E_LBU |
| 1855 | case RISCV::QC_E_LH: { |
| 1856 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 1857 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1858 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1859 | MI.getOperand(i: 0).isReg() && |
| 1860 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1861 | MI.getOperand(i: 1).isReg() && |
| 1862 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1863 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimm2_lsb0 */) && |
| 1864 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimm2_lsb0_optional */)) { |
| 1865 | // c.lh $rd, ${imm}(${rs1}) |
| 1866 | OutInst.setOpcode(RISCV::C_LH); |
| 1867 | // Operand: rd |
| 1868 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1869 | // Operand: rs1 |
| 1870 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1871 | // Operand: imm |
| 1872 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1873 | OutInst.setLoc(MI.getLoc()); |
| 1874 | return true; |
| 1875 | } // if |
| 1876 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1877 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1878 | MI.getOperand(i: 0).isReg() && |
| 1879 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1880 | MI.getOperand(i: 1).isReg() && |
| 1881 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1882 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */) && |
| 1883 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 31 /* simm12_lo_optional */)) { |
| 1884 | // lh $rd, ${imm12}(${rs1}) |
| 1885 | OutInst.setOpcode(RISCV::LH); |
| 1886 | // Operand: rd |
| 1887 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1888 | // Operand: rs1 |
| 1889 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1890 | // Operand: imm12 |
| 1891 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1892 | OutInst.setLoc(MI.getLoc()); |
| 1893 | return true; |
| 1894 | } // if |
| 1895 | break; |
| 1896 | } // case QC_E_LH |
| 1897 | case RISCV::QC_E_LHU: { |
| 1898 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 1899 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1900 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1901 | MI.getOperand(i: 0).isReg() && |
| 1902 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1903 | MI.getOperand(i: 1).isReg() && |
| 1904 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1905 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimm2_lsb0 */) && |
| 1906 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimm2_lsb0_optional */)) { |
| 1907 | // c.lhu $rd, ${imm}(${rs1}) |
| 1908 | OutInst.setOpcode(RISCV::C_LHU); |
| 1909 | // Operand: rd |
| 1910 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1911 | // Operand: rs1 |
| 1912 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1913 | // Operand: imm |
| 1914 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1915 | OutInst.setLoc(MI.getLoc()); |
| 1916 | return true; |
| 1917 | } // if |
| 1918 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1919 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1920 | MI.getOperand(i: 0).isReg() && |
| 1921 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1922 | MI.getOperand(i: 1).isReg() && |
| 1923 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1924 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */) && |
| 1925 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 31 /* simm12_lo_optional */)) { |
| 1926 | // lhu $rd, ${imm12}(${rs1}) |
| 1927 | OutInst.setOpcode(RISCV::LHU); |
| 1928 | // Operand: rd |
| 1929 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1930 | // Operand: rs1 |
| 1931 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1932 | // Operand: imm12 |
| 1933 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1934 | OutInst.setLoc(MI.getLoc()); |
| 1935 | return true; |
| 1936 | } // if |
| 1937 | break; |
| 1938 | } // case QC_E_LHU |
| 1939 | case RISCV::QC_E_LI: { |
| 1940 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1941 | STI.getFeatureBits()[RISCV::FeatureVendorXqcili] && |
| 1942 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1943 | MI.getOperand(i: 0).isReg() && |
| 1944 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1945 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 3 /* simm6 */)) { |
| 1946 | // c.li $rd, $imm |
| 1947 | OutInst.setOpcode(RISCV::C_LI); |
| 1948 | // Operand: rd |
| 1949 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1950 | // Operand: imm |
| 1951 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1952 | OutInst.setLoc(MI.getLoc()); |
| 1953 | return true; |
| 1954 | } // if |
| 1955 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] && |
| 1956 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1957 | MI.getOperand(i: 0).isReg() && |
| 1958 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1959 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 32 /* simm20_li */)) { |
| 1960 | // qc.li $rd, $imm20 |
| 1961 | OutInst.setOpcode(RISCV::QC_LI); |
| 1962 | // Operand: rd |
| 1963 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1964 | // Operand: imm20 |
| 1965 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1966 | OutInst.setLoc(MI.getLoc()); |
| 1967 | return true; |
| 1968 | } // if |
| 1969 | break; |
| 1970 | } // case QC_E_LI |
| 1971 | case RISCV::QC_E_LW: { |
| 1972 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1973 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1974 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1975 | MI.getOperand(i: 0).isReg() && |
| 1976 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1977 | MI.getOperand(i: 1).isReg() && |
| 1978 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1979 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 1980 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm7_lsb00_optional */)) { |
| 1981 | // c.lw $rd, ${imm}(${rs1}) |
| 1982 | OutInst.setOpcode(RISCV::C_LW); |
| 1983 | // Operand: rd |
| 1984 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 1985 | // Operand: rs1 |
| 1986 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 1987 | // Operand: imm |
| 1988 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 1989 | OutInst.setLoc(MI.getLoc()); |
| 1990 | return true; |
| 1991 | } // if |
| 1992 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 1993 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 1994 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 1995 | MI.getOperand(i: 0).isReg() && |
| 1996 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 1997 | MI.getOperand(i: 1).isReg() && |
| 1998 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 1999 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13 /* uimm8_lsb00 */) && |
| 2000 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14 /* uimm8_lsb00_optional */)) { |
| 2001 | // c.lwsp $rd, ${imm}(${rs1}) |
| 2002 | OutInst.setOpcode(RISCV::C_LWSP); |
| 2003 | // Operand: rd |
| 2004 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2005 | // Operand: rs1 |
| 2006 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2007 | // Operand: imm |
| 2008 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2009 | OutInst.setLoc(MI.getLoc()); |
| 2010 | return true; |
| 2011 | } // if |
| 2012 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 2013 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2014 | MI.getOperand(i: 0).isReg() && |
| 2015 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2016 | MI.getOperand(i: 1).isReg() && |
| 2017 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2018 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */) && |
| 2019 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 31 /* simm12_lo_optional */)) { |
| 2020 | // lw $rd, ${imm12}(${rs1}) |
| 2021 | OutInst.setOpcode(RISCV::LW); |
| 2022 | // Operand: rd |
| 2023 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2024 | // Operand: rs1 |
| 2025 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2026 | // Operand: imm12 |
| 2027 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2028 | OutInst.setLoc(MI.getLoc()); |
| 2029 | return true; |
| 2030 | } // if |
| 2031 | break; |
| 2032 | } // case QC_E_LW |
| 2033 | case RISCV::QC_E_ORAI: { |
| 2034 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 2035 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2036 | MI.getOperand(i: 0).isReg() && |
| 2037 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2038 | MI.getOperand(i: 0).isReg() && |
| 2039 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2040 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */)) { |
| 2041 | // ori $rd, $rs1, $imm12 |
| 2042 | OutInst.setOpcode(RISCV::ORI); |
| 2043 | // Operand: rd |
| 2044 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2045 | // Operand: rs1 |
| 2046 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2047 | // Operand: imm12 |
| 2048 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2049 | OutInst.setLoc(MI.getLoc()); |
| 2050 | return true; |
| 2051 | } // if |
| 2052 | break; |
| 2053 | } // case QC_E_ORAI |
| 2054 | case RISCV::QC_E_ORI: { |
| 2055 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 2056 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2057 | MI.getOperand(i: 0).isReg() && |
| 2058 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2059 | MI.getOperand(i: 1).isReg() && |
| 2060 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2061 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */)) { |
| 2062 | // ori $rd, $rs1, $imm12 |
| 2063 | OutInst.setOpcode(RISCV::ORI); |
| 2064 | // Operand: rd |
| 2065 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2066 | // Operand: rs1 |
| 2067 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2068 | // Operand: imm12 |
| 2069 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2070 | OutInst.setLoc(MI.getLoc()); |
| 2071 | return true; |
| 2072 | } // if |
| 2073 | break; |
| 2074 | } // case QC_E_ORI |
| 2075 | case RISCV::QC_E_SB: { |
| 2076 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 2077 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 2078 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2079 | MI.getOperand(i: 0).isReg() && |
| 2080 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2081 | MI.getOperand(i: 1).isReg() && |
| 2082 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2083 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16 /* uimm2 */) && |
| 2084 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 17 /* uimm2_optional */)) { |
| 2085 | // c.sb $rs2, ${imm}(${rs1}) |
| 2086 | OutInst.setOpcode(RISCV::C_SB); |
| 2087 | // Operand: rs2 |
| 2088 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2089 | // Operand: rs1 |
| 2090 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2091 | // Operand: imm |
| 2092 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2093 | OutInst.setLoc(MI.getLoc()); |
| 2094 | return true; |
| 2095 | } // if |
| 2096 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 2097 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2098 | MI.getOperand(i: 0).isReg() && |
| 2099 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2100 | MI.getOperand(i: 1).isReg() && |
| 2101 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2102 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */) && |
| 2103 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 31 /* simm12_lo_optional */)) { |
| 2104 | // sb $rs2, ${imm12}(${rs1}) |
| 2105 | OutInst.setOpcode(RISCV::SB); |
| 2106 | // Operand: rs2 |
| 2107 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2108 | // Operand: rs1 |
| 2109 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2110 | // Operand: imm12 |
| 2111 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2112 | OutInst.setLoc(MI.getLoc()); |
| 2113 | return true; |
| 2114 | } // if |
| 2115 | break; |
| 2116 | } // case QC_E_SB |
| 2117 | case RISCV::QC_E_SH: { |
| 2118 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 2119 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 2120 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2121 | MI.getOperand(i: 0).isReg() && |
| 2122 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2123 | MI.getOperand(i: 1).isReg() && |
| 2124 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2125 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimm2_lsb0 */) && |
| 2126 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimm2_lsb0_optional */)) { |
| 2127 | // c.sh $rs2, ${imm}(${rs1}) |
| 2128 | OutInst.setOpcode(RISCV::C_SH); |
| 2129 | // Operand: rs2 |
| 2130 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2131 | // Operand: rs1 |
| 2132 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2133 | // Operand: imm |
| 2134 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2135 | OutInst.setLoc(MI.getLoc()); |
| 2136 | return true; |
| 2137 | } // if |
| 2138 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 2139 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2140 | MI.getOperand(i: 0).isReg() && |
| 2141 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2142 | MI.getOperand(i: 1).isReg() && |
| 2143 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2144 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */) && |
| 2145 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 31 /* simm12_lo_optional */)) { |
| 2146 | // sh $rs2, ${imm12}(${rs1}) |
| 2147 | OutInst.setOpcode(RISCV::SH); |
| 2148 | // Operand: rs2 |
| 2149 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2150 | // Operand: rs1 |
| 2151 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2152 | // Operand: imm12 |
| 2153 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2154 | OutInst.setLoc(MI.getLoc()); |
| 2155 | return true; |
| 2156 | } // if |
| 2157 | break; |
| 2158 | } // case QC_E_SH |
| 2159 | case RISCV::QC_E_SW: { |
| 2160 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2161 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 2162 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2163 | MI.getOperand(i: 0).isReg() && |
| 2164 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2165 | MI.getOperand(i: 1).isReg() && |
| 2166 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2167 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 2168 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm7_lsb00_optional */)) { |
| 2169 | // c.sw $rs2, ${imm}(${rs1}) |
| 2170 | OutInst.setOpcode(RISCV::C_SW); |
| 2171 | // Operand: rs2 |
| 2172 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2173 | // Operand: rs1 |
| 2174 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2175 | // Operand: imm |
| 2176 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2177 | OutInst.setLoc(MI.getLoc()); |
| 2178 | return true; |
| 2179 | } // if |
| 2180 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2181 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 2182 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2183 | MI.getOperand(i: 0).isReg() && |
| 2184 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2185 | MI.getOperand(i: 1).isReg() && |
| 2186 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2187 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13 /* uimm8_lsb00 */) && |
| 2188 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14 /* uimm8_lsb00_optional */)) { |
| 2189 | // c.swsp $rs2, ${imm}(${rs1}) |
| 2190 | OutInst.setOpcode(RISCV::C_SWSP); |
| 2191 | // Operand: rs2 |
| 2192 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2193 | // Operand: rs1 |
| 2194 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2195 | // Operand: imm |
| 2196 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2197 | OutInst.setLoc(MI.getLoc()); |
| 2198 | return true; |
| 2199 | } // if |
| 2200 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 2201 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2202 | MI.getOperand(i: 0).isReg() && |
| 2203 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2204 | MI.getOperand(i: 1).isReg() && |
| 2205 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2206 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */) && |
| 2207 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 31 /* simm12_lo_optional */)) { |
| 2208 | // sw $rs2, ${imm12}(${rs1}) |
| 2209 | OutInst.setOpcode(RISCV::SW); |
| 2210 | // Operand: rs2 |
| 2211 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2212 | // Operand: rs1 |
| 2213 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2214 | // Operand: imm12 |
| 2215 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2216 | OutInst.setLoc(MI.getLoc()); |
| 2217 | return true; |
| 2218 | } // if |
| 2219 | break; |
| 2220 | } // case QC_E_SW |
| 2221 | case RISCV::QC_E_XORAI: { |
| 2222 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 2223 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2224 | MI.getOperand(i: 0).isReg() && |
| 2225 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2226 | MI.getOperand(i: 0).isReg() && |
| 2227 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2228 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */)) { |
| 2229 | // xori $rd, $rs1, $imm12 |
| 2230 | OutInst.setOpcode(RISCV::XORI); |
| 2231 | // Operand: rd |
| 2232 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2233 | // Operand: rs1 |
| 2234 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2235 | // Operand: imm12 |
| 2236 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2237 | OutInst.setLoc(MI.getLoc()); |
| 2238 | return true; |
| 2239 | } // if |
| 2240 | break; |
| 2241 | } // case QC_E_XORAI |
| 2242 | case RISCV::QC_E_XORI: { |
| 2243 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 2244 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2245 | MI.getOperand(i: 0).isReg() && |
| 2246 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2247 | MI.getOperand(i: 1).isReg() && |
| 2248 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2249 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 26 /* simm12_lo */)) { |
| 2250 | // xori $rd, $rs1, $imm12 |
| 2251 | OutInst.setOpcode(RISCV::XORI); |
| 2252 | // Operand: rd |
| 2253 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2254 | // Operand: rs1 |
| 2255 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2256 | // Operand: imm12 |
| 2257 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2258 | OutInst.setLoc(MI.getLoc()); |
| 2259 | return true; |
| 2260 | } // if |
| 2261 | break; |
| 2262 | } // case QC_E_XORI |
| 2263 | case RISCV::QC_LI: { |
| 2264 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2265 | STI.getFeatureBits()[RISCV::FeatureVendorXqcili] && |
| 2266 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2267 | MI.getOperand(i: 0).isReg() && |
| 2268 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2269 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 3 /* simm6 */)) { |
| 2270 | // c.li $rd, $imm |
| 2271 | OutInst.setOpcode(RISCV::C_LI); |
| 2272 | // Operand: rd |
| 2273 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2274 | // Operand: imm |
| 2275 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2276 | OutInst.setLoc(MI.getLoc()); |
| 2277 | return true; |
| 2278 | } // if |
| 2279 | break; |
| 2280 | } // case QC_LI |
| 2281 | case RISCV::QC_MULIADD: { |
| 2282 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 2283 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2284 | MI.getOperand(i: 0).isReg() && |
| 2285 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2286 | MI.getOperand(i: 2).isReg() && |
| 2287 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 2288 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 3), STI, PredicateIndex: 18 /* uimm5 */)) { |
| 2289 | // qc.c.muliadd $rd, $rs1, $uimm |
| 2290 | OutInst.setOpcode(RISCV::QC_C_MULIADD); |
| 2291 | // Operand: rd_wb |
| 2292 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2293 | // Operand: rd |
| 2294 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2295 | // Operand: rs1 |
| 2296 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2297 | // Operand: uimm |
| 2298 | OutInst.addOperand(Op: MI.getOperand(i: 3)); |
| 2299 | OutInst.setLoc(MI.getLoc()); |
| 2300 | return true; |
| 2301 | } // if |
| 2302 | break; |
| 2303 | } // case QC_MULIADD |
| 2304 | case RISCV::QC_MVEQI: { |
| 2305 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] && |
| 2306 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2307 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 2308 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2309 | MI.getOperand(i: 3).isImm() && |
| 2310 | (MI.getOperand(i: 3).getImm() == 0) && |
| 2311 | MI.getOperand(i: 2).isReg() && |
| 2312 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 2313 | MI.getOperand(i: 4).isReg() && |
| 2314 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 4).getReg())) { |
| 2315 | // qc.c.mveqz $rd, $rs1 |
| 2316 | OutInst.setOpcode(RISCV::QC_C_MVEQZ); |
| 2317 | // Operand: rd_wb |
| 2318 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2319 | // Operand: rd |
| 2320 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2321 | // Operand: rs1 |
| 2322 | OutInst.addOperand(Op: MI.getOperand(i: 4)); |
| 2323 | OutInst.setLoc(MI.getLoc()); |
| 2324 | return true; |
| 2325 | } // if |
| 2326 | break; |
| 2327 | } // case QC_MVEQI |
| 2328 | case RISCV::QC_MVLTUI: { |
| 2329 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] && |
| 2330 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2331 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 2332 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2333 | MI.getOperand(i: 3).isImm() && |
| 2334 | (MI.getOperand(i: 3).getImm() == 1) && |
| 2335 | MI.getOperand(i: 2).isReg() && |
| 2336 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 2337 | MI.getOperand(i: 4).isReg() && |
| 2338 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 4).getReg())) { |
| 2339 | // qc.c.mveqz $rd, $rs1 |
| 2340 | OutInst.setOpcode(RISCV::QC_C_MVEQZ); |
| 2341 | // Operand: rd_wb |
| 2342 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2343 | // Operand: rd |
| 2344 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2345 | // Operand: rs1 |
| 2346 | OutInst.addOperand(Op: MI.getOperand(i: 4)); |
| 2347 | OutInst.setLoc(MI.getLoc()); |
| 2348 | return true; |
| 2349 | } // if |
| 2350 | break; |
| 2351 | } // case QC_MVLTUI |
| 2352 | case RISCV::QC_SHLADD: { |
| 2353 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 2354 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2355 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 2356 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2357 | MI.getOperand(i: 3).isImm() && |
| 2358 | (MI.getOperand(i: 3).getImm() == 4) && |
| 2359 | MI.getOperand(i: 2).isReg() && |
| 2360 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 2361 | MI.getOperand(i: 1).isReg() && |
| 2362 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2363 | RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: 16), STI, PredicateIndex: 18 /* uimm5 */)) { |
| 2364 | // qc.c.muliadd $rd, $rs1, $uimm |
| 2365 | OutInst.setOpcode(RISCV::QC_C_MULIADD); |
| 2366 | // Operand: rd_wb |
| 2367 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2368 | // Operand: rd |
| 2369 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2370 | // Operand: rs1 |
| 2371 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2372 | // Operand: uimm |
| 2373 | OutInst.addOperand(Op: MCOperand::createImm(Val: 16)); |
| 2374 | OutInst.setLoc(MI.getLoc()); |
| 2375 | return true; |
| 2376 | } // if |
| 2377 | break; |
| 2378 | } // case QC_SHLADD |
| 2379 | case RISCV::QC_SYNC: { |
| 2380 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 2381 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2382 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 33 /* uimm5slist */)) { |
| 2383 | // qc.c.sync $slist |
| 2384 | OutInst.setOpcode(RISCV::QC_C_SYNC); |
| 2385 | // Operand: slist |
| 2386 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2387 | OutInst.setLoc(MI.getLoc()); |
| 2388 | return true; |
| 2389 | } // if |
| 2390 | break; |
| 2391 | } // case QC_SYNC |
| 2392 | case RISCV::QC_SYNCR: { |
| 2393 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 2394 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2395 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 33 /* uimm5slist */)) { |
| 2396 | // qc.c.syncr $slist |
| 2397 | OutInst.setOpcode(RISCV::QC_C_SYNCR); |
| 2398 | // Operand: slist |
| 2399 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2400 | OutInst.setLoc(MI.getLoc()); |
| 2401 | return true; |
| 2402 | } // if |
| 2403 | break; |
| 2404 | } // case QC_SYNCR |
| 2405 | case RISCV::QC_SYNCWF: { |
| 2406 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 2407 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2408 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 33 /* uimm5slist */)) { |
| 2409 | // qc.c.syncwf $slist |
| 2410 | OutInst.setOpcode(RISCV::QC_C_SYNCWF); |
| 2411 | // Operand: slist |
| 2412 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2413 | OutInst.setLoc(MI.getLoc()); |
| 2414 | return true; |
| 2415 | } // if |
| 2416 | break; |
| 2417 | } // case QC_SYNCWF |
| 2418 | case RISCV::QC_SYNCWL: { |
| 2419 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 2420 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2421 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 33 /* uimm5slist */)) { |
| 2422 | // qc.c.syncwl $slist |
| 2423 | OutInst.setOpcode(RISCV::QC_C_SYNCWL); |
| 2424 | // Operand: slist |
| 2425 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2426 | OutInst.setLoc(MI.getLoc()); |
| 2427 | return true; |
| 2428 | } // if |
| 2429 | break; |
| 2430 | } // case QC_SYNCWL |
| 2431 | case RISCV::SB: { |
| 2432 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 2433 | MI.getOperand(i: 0).isReg() && |
| 2434 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2435 | MI.getOperand(i: 1).isReg() && |
| 2436 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2437 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16 /* uimm2 */) && |
| 2438 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 17 /* uimm2_optional */)) { |
| 2439 | // c.sb $rs2, ${imm}(${rs1}) |
| 2440 | OutInst.setOpcode(RISCV::C_SB); |
| 2441 | // Operand: rs2 |
| 2442 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2443 | // Operand: rs1 |
| 2444 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2445 | // Operand: imm |
| 2446 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2447 | OutInst.setLoc(MI.getLoc()); |
| 2448 | return true; |
| 2449 | } // if |
| 2450 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 2451 | MI.getOperand(i: 0).isReg() && |
| 2452 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2453 | MI.getOperand(i: 1).isReg() && |
| 2454 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2455 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 18 /* uimm5 */)) { |
| 2456 | // qk.c.sb $rs2, ${imm}(${rs1}) |
| 2457 | OutInst.setOpcode(RISCV::QK_C_SB); |
| 2458 | // Operand: rs2 |
| 2459 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2460 | // Operand: rs1 |
| 2461 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2462 | // Operand: imm |
| 2463 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2464 | OutInst.setLoc(MI.getLoc()); |
| 2465 | return true; |
| 2466 | } // if |
| 2467 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 2468 | MI.getOperand(i: 0).isReg() && |
| 2469 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2470 | MI.getOperand(i: 1).isReg() && |
| 2471 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2472 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 19 /* uimm4 */)) { |
| 2473 | // qk.c.sbsp $rd_rs2, ${imm}(${rs1}) |
| 2474 | OutInst.setOpcode(RISCV::QK_C_SBSP); |
| 2475 | // Operand: rd_rs2 |
| 2476 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2477 | // Operand: rs1 |
| 2478 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2479 | // Operand: imm |
| 2480 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2481 | OutInst.setLoc(MI.getLoc()); |
| 2482 | return true; |
| 2483 | } // if |
| 2484 | break; |
| 2485 | } // case SB |
| 2486 | case RISCV::SD: { |
| 2487 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2488 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2489 | MI.getOperand(i: 0).isReg() && |
| 2490 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2491 | MI.getOperand(i: 1).isReg() && |
| 2492 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2493 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7 /* uimm8_lsb000 */) && |
| 2494 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000_optional */)) { |
| 2495 | // c.sd $rs2, ${imm}(${rs1}) |
| 2496 | OutInst.setOpcode(RISCV::C_SD); |
| 2497 | // Operand: rs2 |
| 2498 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2499 | // Operand: rs1 |
| 2500 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2501 | // Operand: imm |
| 2502 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2503 | OutInst.setLoc(MI.getLoc()); |
| 2504 | return true; |
| 2505 | } // if |
| 2506 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2507 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2508 | MI.getOperand(i: 0).isReg() && |
| 2509 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2510 | MI.getOperand(i: 1).isReg() && |
| 2511 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2512 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* uimm9_lsb000 */) && |
| 2513 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000_optional */)) { |
| 2514 | // c.sdsp $rs2, ${imm}(${rs1}) |
| 2515 | OutInst.setOpcode(RISCV::C_SDSP); |
| 2516 | // Operand: rs2 |
| 2517 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2518 | // Operand: rs1 |
| 2519 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2520 | // Operand: imm |
| 2521 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2522 | OutInst.setLoc(MI.getLoc()); |
| 2523 | return true; |
| 2524 | } // if |
| 2525 | break; |
| 2526 | } // case SD |
| 2527 | case RISCV::SD_RV32: { |
| 2528 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 2529 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2530 | MI.getOperand(i: 0).isReg() && |
| 2531 | getRISCVMCRegisterClass(RC: RISCV::GPRPairRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2532 | MI.getOperand(i: 1).isReg() && |
| 2533 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2534 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* uimm9_lsb000 */) && |
| 2535 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000_optional */)) { |
| 2536 | // c.sdsp $rs2, ${imm}(${rs1}) |
| 2537 | OutInst.setOpcode(RISCV::C_SDSP_RV32); |
| 2538 | // Operand: rs2 |
| 2539 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2540 | // Operand: rs1 |
| 2541 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2542 | // Operand: imm |
| 2543 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2544 | OutInst.setLoc(MI.getLoc()); |
| 2545 | return true; |
| 2546 | } // if |
| 2547 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 2548 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2549 | MI.getOperand(i: 0).isReg() && |
| 2550 | getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2551 | MI.getOperand(i: 1).isReg() && |
| 2552 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2553 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7 /* uimm8_lsb000 */) && |
| 2554 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000_optional */)) { |
| 2555 | // c.sd $rs2, ${imm}(${rs1}) |
| 2556 | OutInst.setOpcode(RISCV::C_SD_RV32); |
| 2557 | // Operand: rs2 |
| 2558 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2559 | // Operand: rs1 |
| 2560 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2561 | // Operand: imm |
| 2562 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2563 | OutInst.setLoc(MI.getLoc()); |
| 2564 | return true; |
| 2565 | } // if |
| 2566 | break; |
| 2567 | } // case SD_RV32 |
| 2568 | case RISCV::SEXT_B: { |
| 2569 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 2570 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 2571 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 2572 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2573 | MI.getOperand(i: 1).isReg() && |
| 2574 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 2575 | // c.sext.b $rd |
| 2576 | OutInst.setOpcode(RISCV::C_SEXT_B); |
| 2577 | // Operand: rd_wb |
| 2578 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2579 | // Operand: rd |
| 2580 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2581 | OutInst.setLoc(MI.getLoc()); |
| 2582 | return true; |
| 2583 | } // if |
| 2584 | break; |
| 2585 | } // case SEXT_B |
| 2586 | case RISCV::SEXT_H: { |
| 2587 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 2588 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 2589 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 2590 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2591 | MI.getOperand(i: 1).isReg() && |
| 2592 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 2593 | // c.sext.h $rd |
| 2594 | OutInst.setOpcode(RISCV::C_SEXT_H); |
| 2595 | // Operand: rd_wb |
| 2596 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2597 | // Operand: rd |
| 2598 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2599 | OutInst.setLoc(MI.getLoc()); |
| 2600 | return true; |
| 2601 | } // if |
| 2602 | break; |
| 2603 | } // case SEXT_H |
| 2604 | case RISCV::SH: { |
| 2605 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 2606 | MI.getOperand(i: 0).isReg() && |
| 2607 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2608 | MI.getOperand(i: 1).isReg() && |
| 2609 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2610 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimm2_lsb0 */) && |
| 2611 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimm2_lsb0_optional */)) { |
| 2612 | // c.sh $rs2, ${imm}(${rs1}) |
| 2613 | OutInst.setOpcode(RISCV::C_SH); |
| 2614 | // Operand: rs2 |
| 2615 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2616 | // Operand: rs1 |
| 2617 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2618 | // Operand: imm |
| 2619 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2620 | OutInst.setLoc(MI.getLoc()); |
| 2621 | return true; |
| 2622 | } // if |
| 2623 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 2624 | MI.getOperand(i: 0).isReg() && |
| 2625 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2626 | MI.getOperand(i: 1).isReg() && |
| 2627 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2628 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 22 /* uimm6_lsb0 */)) { |
| 2629 | // qk.c.sh $rs2, ${imm}(${rs1}) |
| 2630 | OutInst.setOpcode(RISCV::QK_C_SH); |
| 2631 | // Operand: rs2 |
| 2632 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2633 | // Operand: rs1 |
| 2634 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2635 | // Operand: imm |
| 2636 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2637 | OutInst.setLoc(MI.getLoc()); |
| 2638 | return true; |
| 2639 | } // if |
| 2640 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 2641 | MI.getOperand(i: 0).isReg() && |
| 2642 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2643 | MI.getOperand(i: 1).isReg() && |
| 2644 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2645 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 23 /* uimm5_lsb0 */)) { |
| 2646 | // qk.c.shsp $rd_rs2, ${imm}(${rs1}) |
| 2647 | OutInst.setOpcode(RISCV::QK_C_SHSP); |
| 2648 | // Operand: rd_rs2 |
| 2649 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2650 | // Operand: rs1 |
| 2651 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2652 | // Operand: imm |
| 2653 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2654 | OutInst.setLoc(MI.getLoc()); |
| 2655 | return true; |
| 2656 | } // if |
| 2657 | break; |
| 2658 | } // case SH |
| 2659 | case RISCV::SH1ADD: { |
| 2660 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 2661 | STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 2662 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2663 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 2664 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2665 | MI.getOperand(i: 2).isReg() && |
| 2666 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 2667 | MI.getOperand(i: 1).isReg() && |
| 2668 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2669 | RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: 2), STI, PredicateIndex: 18 /* uimm5 */)) { |
| 2670 | // qc.c.muliadd $rd, $rs1, $uimm |
| 2671 | OutInst.setOpcode(RISCV::QC_C_MULIADD); |
| 2672 | // Operand: rd_wb |
| 2673 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2674 | // Operand: rd |
| 2675 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2676 | // Operand: rs1 |
| 2677 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2678 | // Operand: uimm |
| 2679 | OutInst.addOperand(Op: MCOperand::createImm(Val: 2)); |
| 2680 | OutInst.setLoc(MI.getLoc()); |
| 2681 | return true; |
| 2682 | } // if |
| 2683 | break; |
| 2684 | } // case SH1ADD |
| 2685 | case RISCV::SH2ADD: { |
| 2686 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 2687 | STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 2688 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2689 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 2690 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2691 | MI.getOperand(i: 2).isReg() && |
| 2692 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 2693 | MI.getOperand(i: 1).isReg() && |
| 2694 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2695 | RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: 4), STI, PredicateIndex: 18 /* uimm5 */)) { |
| 2696 | // qc.c.muliadd $rd, $rs1, $uimm |
| 2697 | OutInst.setOpcode(RISCV::QC_C_MULIADD); |
| 2698 | // Operand: rd_wb |
| 2699 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2700 | // Operand: rd |
| 2701 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2702 | // Operand: rs1 |
| 2703 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2704 | // Operand: uimm |
| 2705 | OutInst.addOperand(Op: MCOperand::createImm(Val: 4)); |
| 2706 | OutInst.setLoc(MI.getLoc()); |
| 2707 | return true; |
| 2708 | } // if |
| 2709 | break; |
| 2710 | } // case SH2ADD |
| 2711 | case RISCV::SH3ADD: { |
| 2712 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 2713 | STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 2714 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2715 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 2716 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2717 | MI.getOperand(i: 2).isReg() && |
| 2718 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 2719 | MI.getOperand(i: 1).isReg() && |
| 2720 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2721 | RISCVValidateMCOperandForCompress(MCOp: MCOperand::createImm(Val: 8), STI, PredicateIndex: 18 /* uimm5 */)) { |
| 2722 | // qc.c.muliadd $rd, $rs1, $uimm |
| 2723 | OutInst.setOpcode(RISCV::QC_C_MULIADD); |
| 2724 | // Operand: rd_wb |
| 2725 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2726 | // Operand: rd |
| 2727 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2728 | // Operand: rs1 |
| 2729 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2730 | // Operand: uimm |
| 2731 | OutInst.addOperand(Op: MCOperand::createImm(Val: 8)); |
| 2732 | OutInst.setLoc(MI.getLoc()); |
| 2733 | return true; |
| 2734 | } // if |
| 2735 | break; |
| 2736 | } // case SH3ADD |
| 2737 | case RISCV::SH_INX: { |
| 2738 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 2739 | MI.getOperand(i: 0).isReg() && |
| 2740 | getRISCVMCRegisterClass(RC: RISCV::GPRF16CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2741 | MI.getOperand(i: 1).isReg() && |
| 2742 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2743 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimm2_lsb0 */) && |
| 2744 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimm2_lsb0_optional */)) { |
| 2745 | // c.sh $rs2, ${imm}(${rs1}) |
| 2746 | OutInst.setOpcode(RISCV::C_SH_INX); |
| 2747 | // Operand: rs2 |
| 2748 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2749 | // Operand: rs1 |
| 2750 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2751 | // Operand: imm |
| 2752 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2753 | OutInst.setLoc(MI.getLoc()); |
| 2754 | return true; |
| 2755 | } // if |
| 2756 | break; |
| 2757 | } // case SH_INX |
| 2758 | case RISCV::SLLI: { |
| 2759 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2760 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 2761 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2762 | MI.getOperand(i: 1).isReg() && |
| 2763 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2764 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6 /* uimmlog2xlennonzero */) && |
| 2765 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 34 /* uimmlog2xlen */)) { |
| 2766 | // c.slli $rd, $imm |
| 2767 | OutInst.setOpcode(RISCV::C_SLLI); |
| 2768 | // Operand: rd_wb |
| 2769 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2770 | // Operand: rd |
| 2771 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2772 | // Operand: imm |
| 2773 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2774 | OutInst.setLoc(MI.getLoc()); |
| 2775 | return true; |
| 2776 | } // if |
| 2777 | break; |
| 2778 | } // case SLLI |
| 2779 | case RISCV::SRAI: { |
| 2780 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2781 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 2782 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2783 | MI.getOperand(i: 1).isReg() && |
| 2784 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2785 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6 /* uimmlog2xlennonzero */) && |
| 2786 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 34 /* uimmlog2xlen */)) { |
| 2787 | // c.srai $rs1, $imm |
| 2788 | OutInst.setOpcode(RISCV::C_SRAI); |
| 2789 | // Operand: rd |
| 2790 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2791 | // Operand: rs1 |
| 2792 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2793 | // Operand: imm |
| 2794 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2795 | OutInst.setLoc(MI.getLoc()); |
| 2796 | return true; |
| 2797 | } // if |
| 2798 | break; |
| 2799 | } // case SRAI |
| 2800 | case RISCV::SRLI: { |
| 2801 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2802 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 2803 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2804 | MI.getOperand(i: 1).isReg() && |
| 2805 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2806 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6 /* uimmlog2xlennonzero */) && |
| 2807 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 34 /* uimmlog2xlen */)) { |
| 2808 | // c.srli $rs1, $imm |
| 2809 | OutInst.setOpcode(RISCV::C_SRLI); |
| 2810 | // Operand: rd |
| 2811 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2812 | // Operand: rs1 |
| 2813 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2814 | // Operand: imm |
| 2815 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2816 | OutInst.setLoc(MI.getLoc()); |
| 2817 | return true; |
| 2818 | } // if |
| 2819 | break; |
| 2820 | } // case SRLI |
| 2821 | case RISCV::SSPOPCHK: { |
| 2822 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] && |
| 2823 | MI.getOperand(i: 0).isReg() && |
| 2824 | (MI.getOperand(i: 0).getReg() == RISCV::X5)) { |
| 2825 | // c.sspopchk $rs1 |
| 2826 | OutInst.setOpcode(RISCV::C_SSPOPCHK); |
| 2827 | // Operand: rs1 |
| 2828 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5)); |
| 2829 | OutInst.setLoc(MI.getLoc()); |
| 2830 | return true; |
| 2831 | } // if |
| 2832 | break; |
| 2833 | } // case SSPOPCHK |
| 2834 | case RISCV::SSPUSH: { |
| 2835 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] && |
| 2836 | MI.getOperand(i: 0).isReg() && |
| 2837 | (MI.getOperand(i: 0).getReg() == RISCV::X1)) { |
| 2838 | // c.sspush $rs1 |
| 2839 | OutInst.setOpcode(RISCV::C_SSPUSH); |
| 2840 | // Operand: rs1 |
| 2841 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1)); |
| 2842 | OutInst.setLoc(MI.getLoc()); |
| 2843 | return true; |
| 2844 | } // if |
| 2845 | break; |
| 2846 | } // case SSPUSH |
| 2847 | case RISCV::SUB: { |
| 2848 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2849 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 2850 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2851 | MI.getOperand(i: 1).isReg() && |
| 2852 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2853 | MI.getOperand(i: 2).isReg() && |
| 2854 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 2855 | // c.sub $rd, $rs2 |
| 2856 | OutInst.setOpcode(RISCV::C_SUB); |
| 2857 | // Operand: rd_wb |
| 2858 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2859 | // Operand: rd |
| 2860 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2861 | // Operand: rs2 |
| 2862 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2863 | OutInst.setLoc(MI.getLoc()); |
| 2864 | return true; |
| 2865 | } // if |
| 2866 | break; |
| 2867 | } // case SUB |
| 2868 | case RISCV::SUBW: { |
| 2869 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 2870 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2871 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 2872 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2873 | MI.getOperand(i: 1).isReg() && |
| 2874 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2875 | MI.getOperand(i: 2).isReg() && |
| 2876 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 2877 | // c.subw $rd, $rs2 |
| 2878 | OutInst.setOpcode(RISCV::C_SUBW); |
| 2879 | // Operand: rd_wb |
| 2880 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2881 | // Operand: rd |
| 2882 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2883 | // Operand: rs2 |
| 2884 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2885 | OutInst.setLoc(MI.getLoc()); |
| 2886 | return true; |
| 2887 | } // if |
| 2888 | break; |
| 2889 | } // case SUBW |
| 2890 | case RISCV::SW: { |
| 2891 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2892 | MI.getOperand(i: 0).isReg() && |
| 2893 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2894 | MI.getOperand(i: 1).isReg() && |
| 2895 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2896 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 2897 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm7_lsb00_optional */)) { |
| 2898 | // c.sw $rs2, ${imm}(${rs1}) |
| 2899 | OutInst.setOpcode(RISCV::C_SW); |
| 2900 | // Operand: rs2 |
| 2901 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2902 | // Operand: rs1 |
| 2903 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2904 | // Operand: imm |
| 2905 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2906 | OutInst.setLoc(MI.getLoc()); |
| 2907 | return true; |
| 2908 | } // if |
| 2909 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2910 | MI.getOperand(i: 0).isReg() && |
| 2911 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2912 | MI.getOperand(i: 1).isReg() && |
| 2913 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2914 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13 /* uimm8_lsb00 */) && |
| 2915 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14 /* uimm8_lsb00_optional */)) { |
| 2916 | // c.swsp $rs2, ${imm}(${rs1}) |
| 2917 | OutInst.setOpcode(RISCV::C_SWSP); |
| 2918 | // Operand: rs2 |
| 2919 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2920 | // Operand: rs1 |
| 2921 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2922 | // Operand: imm |
| 2923 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2924 | OutInst.setLoc(MI.getLoc()); |
| 2925 | return true; |
| 2926 | } // if |
| 2927 | break; |
| 2928 | } // case SW |
| 2929 | case RISCV::SW_INX: { |
| 2930 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2931 | MI.getOperand(i: 0).isReg() && |
| 2932 | getRISCVMCRegisterClass(RC: RISCV::GPRF32CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2933 | MI.getOperand(i: 1).isReg() && |
| 2934 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2935 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 2936 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm7_lsb00_optional */)) { |
| 2937 | // c.sw $rs2, ${imm}(${rs1}) |
| 2938 | OutInst.setOpcode(RISCV::C_SW_INX); |
| 2939 | // Operand: rs2 |
| 2940 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2941 | // Operand: rs1 |
| 2942 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2943 | // Operand: imm |
| 2944 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2945 | OutInst.setLoc(MI.getLoc()); |
| 2946 | return true; |
| 2947 | } // if |
| 2948 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2949 | MI.getOperand(i: 0).isReg() && |
| 2950 | getRISCVMCRegisterClass(RC: RISCV::GPRF32RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 2951 | MI.getOperand(i: 1).isReg() && |
| 2952 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2953 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13 /* uimm8_lsb00 */) && |
| 2954 | RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14 /* uimm8_lsb00_optional */)) { |
| 2955 | // c.swsp $rs2, ${imm}(${rs1}) |
| 2956 | OutInst.setOpcode(RISCV::C_SWSP_INX); |
| 2957 | // Operand: rs2 |
| 2958 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 2959 | // Operand: rs1 |
| 2960 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2961 | // Operand: imm |
| 2962 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2963 | OutInst.setLoc(MI.getLoc()); |
| 2964 | return true; |
| 2965 | } // if |
| 2966 | break; |
| 2967 | } // case SW_INX |
| 2968 | case RISCV::UNIMP: { |
| 2969 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) { |
| 2970 | // c.unimp |
| 2971 | OutInst.setOpcode(RISCV::C_UNIMP); |
| 2972 | OutInst.setLoc(MI.getLoc()); |
| 2973 | return true; |
| 2974 | } // if |
| 2975 | break; |
| 2976 | } // case UNIMP |
| 2977 | case RISCV::XOR: { |
| 2978 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2979 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 2980 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2981 | MI.getOperand(i: 1).isReg() && |
| 2982 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 2983 | MI.getOperand(i: 2).isReg() && |
| 2984 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 2985 | // c.xor $rd, $rs2 |
| 2986 | OutInst.setOpcode(RISCV::C_XOR); |
| 2987 | // Operand: rd_wb |
| 2988 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2989 | // Operand: rd |
| 2990 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 2991 | // Operand: rs2 |
| 2992 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 2993 | OutInst.setLoc(MI.getLoc()); |
| 2994 | return true; |
| 2995 | } // if |
| 2996 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 2997 | MI.getOperand(i: 2).isReg() && MI.getOperand(i: 0).isReg() && |
| 2998 | (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) && |
| 2999 | MI.getOperand(i: 2).isReg() && |
| 3000 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg()) && |
| 3001 | MI.getOperand(i: 1).isReg() && |
| 3002 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 3003 | // c.xor $rd, $rs2 |
| 3004 | OutInst.setOpcode(RISCV::C_XOR); |
| 3005 | // Operand: rd_wb |
| 3006 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3007 | // Operand: rd |
| 3008 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3009 | // Operand: rs2 |
| 3010 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3011 | OutInst.setLoc(MI.getLoc()); |
| 3012 | return true; |
| 3013 | } // if |
| 3014 | break; |
| 3015 | } // case XOR |
| 3016 | case RISCV::XORI: { |
| 3017 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 3018 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 3019 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 3020 | MI.getOperand(i: 2).isImm() && |
| 3021 | (MI.getOperand(i: 2).getImm() == -1) && |
| 3022 | MI.getOperand(i: 1).isReg() && |
| 3023 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 3024 | // c.not $rd |
| 3025 | OutInst.setOpcode(RISCV::C_NOT); |
| 3026 | // Operand: rd_wb |
| 3027 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3028 | // Operand: rd |
| 3029 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3030 | OutInst.setLoc(MI.getLoc()); |
| 3031 | return true; |
| 3032 | } // if |
| 3033 | break; |
| 3034 | } // case XORI |
| 3035 | case RISCV::ZEXT_H_RV32: { |
| 3036 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 3037 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 3038 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 3039 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 3040 | MI.getOperand(i: 1).isReg() && |
| 3041 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 3042 | // c.zext.h $rd |
| 3043 | OutInst.setOpcode(RISCV::C_ZEXT_H); |
| 3044 | // Operand: rd_wb |
| 3045 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3046 | // Operand: rd |
| 3047 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3048 | OutInst.setLoc(MI.getLoc()); |
| 3049 | return true; |
| 3050 | } // if |
| 3051 | break; |
| 3052 | } // case ZEXT_H_RV32 |
| 3053 | case RISCV::ZEXT_H_RV64: { |
| 3054 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 3055 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 3056 | MI.getOperand(i: 1).isReg() && MI.getOperand(i: 0).isReg() && |
| 3057 | (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) && |
| 3058 | MI.getOperand(i: 1).isReg() && |
| 3059 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg())) { |
| 3060 | // c.zext.h $rd |
| 3061 | OutInst.setOpcode(RISCV::C_ZEXT_H); |
| 3062 | // Operand: rd_wb |
| 3063 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3064 | // Operand: rd |
| 3065 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3066 | OutInst.setLoc(MI.getLoc()); |
| 3067 | return true; |
| 3068 | } // if |
| 3069 | break; |
| 3070 | } // case ZEXT_H_RV64 |
| 3071 | } // switch |
| 3072 | return false; |
| 3073 | } |
| 3074 | |
| 3075 | #endif // GEN_COMPRESS_INSTR |
| 3076 | |
| 3077 | #ifdef GEN_UNCOMPRESS_INSTR |
| 3078 | #undef GEN_UNCOMPRESS_INSTR |
| 3079 | |
| 3080 | static bool RISCVValidateMCOperandForUncompress(const MCOperand &MCOp, |
| 3081 | const MCSubtargetInfo &STI, |
| 3082 | unsigned PredicateIndex) { |
| 3083 | switch (PredicateIndex) { |
| 3084 | default: |
| 3085 | llvm_unreachable("Unknown MCOperandPredicate kind"); |
| 3086 | break; |
| 3087 | case 1: { |
| 3088 | // simm6nonzero |
| 3089 | int64_t Imm; |
| 3090 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3091 | return (Imm != 0) && isInt<6>(x: Imm); |
| 3092 | return MCOp.isBareSymbolRef(); |
| 3093 | } |
| 3094 | case 2: { |
| 3095 | // simm12_lo |
| 3096 | int64_t Imm; |
| 3097 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3098 | return isInt<12>(x: Imm); |
| 3099 | return MCOp.isBareSymbolRef(); |
| 3100 | } |
| 3101 | case 3: { |
| 3102 | // simm10_lsb0000nonzero |
| 3103 | int64_t Imm; |
| 3104 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3105 | return false; |
| 3106 | return isShiftedInt<6, 4>(x: Imm) && (Imm != 0); |
| 3107 | } |
| 3108 | case 4: { |
| 3109 | // uimm10_lsb00nonzero |
| 3110 | int64_t Imm; |
| 3111 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3112 | return false; |
| 3113 | return isShiftedUInt<8, 2>(x: Imm) && (Imm != 0); |
| 3114 | } |
| 3115 | case 5: { |
| 3116 | // simm6 |
| 3117 | int64_t Imm; |
| 3118 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3119 | return isInt<6>(x: Imm); |
| 3120 | return MCOp.isBareSymbolRef(); |
| 3121 | } |
| 3122 | case 6: { |
| 3123 | // bare_simm9_lsb0 |
| 3124 | int64_t Imm; |
| 3125 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3126 | return isShiftedInt<8, 1>(x: Imm); |
| 3127 | return MCOp.isBareSymbolRef(); |
| 3128 | } |
| 3129 | case 7: { |
| 3130 | // bare_simm13_lsb0 |
| 3131 | int64_t Imm; |
| 3132 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3133 | return isShiftedInt<12, 1>(x: Imm); |
| 3134 | return MCOp.isBareSymbolRef(); |
| 3135 | } |
| 3136 | case 8: { |
| 3137 | // uimm8_lsb000 |
| 3138 | int64_t Imm; |
| 3139 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3140 | return false; |
| 3141 | return isShiftedUInt<5, 3>(x: Imm); |
| 3142 | } |
| 3143 | case 9: { |
| 3144 | // simm12_lo_optional |
| 3145 | int64_t Imm; |
| 3146 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3147 | return isInt<12>(x: Imm); |
| 3148 | return MCOp.isBareSymbolRef(); |
| 3149 | } |
| 3150 | case 10: { |
| 3151 | // uimm9_lsb000 |
| 3152 | int64_t Imm; |
| 3153 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3154 | return false; |
| 3155 | return isShiftedUInt<6, 3>(x: Imm); |
| 3156 | } |
| 3157 | case 11: { |
| 3158 | // uimm7_lsb00 |
| 3159 | int64_t Imm; |
| 3160 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3161 | return false; |
| 3162 | return isShiftedUInt<5, 2>(x: Imm); |
| 3163 | } |
| 3164 | case 12: { |
| 3165 | // uimm8_lsb00 |
| 3166 | int64_t Imm; |
| 3167 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3168 | return false; |
| 3169 | return isShiftedUInt<6, 2>(x: Imm); |
| 3170 | } |
| 3171 | case 13: { |
| 3172 | // bare_simm12_lsb0 |
| 3173 | int64_t Imm; |
| 3174 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3175 | return isShiftedInt<11, 1>(x: Imm); |
| 3176 | return MCOp.isBareSymbolRef(); |
| 3177 | } |
| 3178 | case 14: { |
| 3179 | // simm21_lsb0_jal |
| 3180 | int64_t Imm; |
| 3181 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3182 | return isShiftedInt<20, 1>(x: Imm); |
| 3183 | return MCOp.isBareSymbolRef(); |
| 3184 | } |
| 3185 | case 15: { |
| 3186 | // uimm2 |
| 3187 | int64_t Imm; |
| 3188 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3189 | return false; |
| 3190 | return isUInt<2>(x: Imm); |
| 3191 | } |
| 3192 | case 16: { |
| 3193 | // uimm2_lsb0 |
| 3194 | int64_t Imm; |
| 3195 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3196 | return false; |
| 3197 | return isShiftedUInt<1, 1>(x: Imm); |
| 3198 | } |
| 3199 | case 17: { |
| 3200 | // simm20_li |
| 3201 | int64_t Imm; |
| 3202 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3203 | return isInt<20>(x: Imm); |
| 3204 | return MCOp.isBareSymbolRef(); |
| 3205 | } |
| 3206 | case 18: { |
| 3207 | // c_lui_imm |
| 3208 | int64_t Imm; |
| 3209 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3210 | return false; |
| 3211 | return (Imm != 0) && (isUInt<5>(x: Imm) || |
| 3212 | (Imm >= 0xfffe0 && Imm <= 0xfffff)); |
| 3213 | } |
| 3214 | case 19: { |
| 3215 | // uimm20_lui |
| 3216 | int64_t Imm; |
| 3217 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3218 | return isUInt<20>(x: Imm); |
| 3219 | return MCOp.isBareSymbolRef(); |
| 3220 | } |
| 3221 | case 20: { |
| 3222 | // uimmlog2xlennonzero |
| 3223 | int64_t Imm; |
| 3224 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3225 | return false; |
| 3226 | if (STI.getTargetTriple().isArch64Bit()) |
| 3227 | return isUInt<6>(x: Imm) && (Imm != 0); |
| 3228 | return isUInt<5>(x: Imm) && (Imm != 0); |
| 3229 | } |
| 3230 | case 21: { |
| 3231 | // uimmlog2xlen |
| 3232 | int64_t Imm; |
| 3233 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3234 | return false; |
| 3235 | if (STI.getTargetTriple().isArch64Bit()) |
| 3236 | return isUInt<6>(x: Imm); |
| 3237 | return isUInt<5>(x: Imm); |
| 3238 | } |
| 3239 | case 22: { |
| 3240 | // uimm5ge6_plus1 |
| 3241 | int64_t Imm; |
| 3242 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3243 | return false; |
| 3244 | return Imm >= 6 && Imm <= 32; |
| 3245 | } |
| 3246 | case 23: { |
| 3247 | // uimm5_plus1 |
| 3248 | int64_t Imm; |
| 3249 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3250 | return false; |
| 3251 | return Imm > 0 && isUInt<5>(x: Imm - 1); |
| 3252 | } |
| 3253 | case 24: { |
| 3254 | // uimm5 |
| 3255 | int64_t Imm; |
| 3256 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3257 | return false; |
| 3258 | return isUInt<5>(x: Imm); |
| 3259 | } |
| 3260 | case 25: { |
| 3261 | // simm5 |
| 3262 | int64_t Imm; |
| 3263 | if (MCOp.evaluateAsConstantImm(Imm)) |
| 3264 | return isInt<5>(x: Imm); |
| 3265 | return MCOp.isBareSymbolRef(); |
| 3266 | } |
| 3267 | case 26: { |
| 3268 | // uimm5slist |
| 3269 | int64_t Imm; |
| 3270 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3271 | return false; |
| 3272 | return ((Imm == 0) || (Imm == 1) || |
| 3273 | (Imm == 2) || (Imm == 4) || |
| 3274 | (Imm == 8) || (Imm == 16) || |
| 3275 | (Imm == 15) || (Imm == 31)); |
| 3276 | } |
| 3277 | case 27: { |
| 3278 | // uimm4 |
| 3279 | int64_t Imm; |
| 3280 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3281 | return false; |
| 3282 | return isUInt<4>(x: Imm); |
| 3283 | } |
| 3284 | case 28: { |
| 3285 | // uimm6_lsb0 |
| 3286 | int64_t Imm; |
| 3287 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3288 | return false; |
| 3289 | return isShiftedUInt<5, 1>(x: Imm); |
| 3290 | } |
| 3291 | case 29: { |
| 3292 | // uimm5_lsb0 |
| 3293 | int64_t Imm; |
| 3294 | if (!MCOp.evaluateAsConstantImm(Imm)) |
| 3295 | return false; |
| 3296 | return isShiftedUInt<4, 1>(x: Imm); |
| 3297 | } |
| 3298 | } |
| 3299 | } |
| 3300 | |
| 3301 | static bool uncompressInst(MCInst &OutInst, |
| 3302 | const MCInst &MI, |
| 3303 | const MCSubtargetInfo &STI) { |
| 3304 | switch (MI.getOpcode()) { |
| 3305 | default: return false; |
| 3306 | case RISCV::C_ADD: { |
| 3307 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3308 | MI.getOperand(i: 0).isReg() && |
| 3309 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3310 | MI.getOperand(i: 0).isReg() && |
| 3311 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3312 | MI.getOperand(i: 2).isReg() && |
| 3313 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 3314 | // add $rd, $rs1, $rs2 |
| 3315 | OutInst.setOpcode(RISCV::ADD); |
| 3316 | // Operand: rd |
| 3317 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3318 | // Operand: rs1 |
| 3319 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3320 | // Operand: rs2 |
| 3321 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3322 | OutInst.setLoc(MI.getLoc()); |
| 3323 | return true; |
| 3324 | } // if |
| 3325 | break; |
| 3326 | } // case C_ADD |
| 3327 | case RISCV::C_ADDI: { |
| 3328 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3329 | MI.getOperand(i: 0).isReg() && |
| 3330 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3331 | MI.getOperand(i: 0).isReg() && |
| 3332 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3333 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1 /* simm6nonzero */) && |
| 3334 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 3335 | // addi $rd, $rs1, $imm12 |
| 3336 | OutInst.setOpcode(RISCV::ADDI); |
| 3337 | // Operand: rd |
| 3338 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3339 | // Operand: rs1 |
| 3340 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3341 | // Operand: imm12 |
| 3342 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3343 | OutInst.setLoc(MI.getLoc()); |
| 3344 | return true; |
| 3345 | } // if |
| 3346 | break; |
| 3347 | } // case C_ADDI |
| 3348 | case RISCV::C_ADDI16SP: { |
| 3349 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3350 | MI.getOperand(i: 0).isReg() && |
| 3351 | (MI.getOperand(i: 0).getReg() == RISCV::X2) && |
| 3352 | MI.getOperand(i: 1).isReg() && |
| 3353 | (MI.getOperand(i: 1).getReg() == RISCV::X2) && |
| 3354 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3 /* simm10_lsb0000nonzero */) && |
| 3355 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 3356 | // addi $rd, $rs1, $imm12 |
| 3357 | OutInst.setOpcode(RISCV::ADDI); |
| 3358 | // Operand: rd |
| 3359 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2)); |
| 3360 | // Operand: rs1 |
| 3361 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2)); |
| 3362 | // Operand: imm12 |
| 3363 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3364 | OutInst.setLoc(MI.getLoc()); |
| 3365 | return true; |
| 3366 | } // if |
| 3367 | break; |
| 3368 | } // case C_ADDI16SP |
| 3369 | case RISCV::C_ADDI4SPN: { |
| 3370 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3371 | MI.getOperand(i: 0).isReg() && |
| 3372 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3373 | MI.getOperand(i: 1).isReg() && |
| 3374 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3375 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 4 /* uimm10_lsb00nonzero */) && |
| 3376 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 3377 | // addi $rd, $rs1, $imm12 |
| 3378 | OutInst.setOpcode(RISCV::ADDI); |
| 3379 | // Operand: rd |
| 3380 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3381 | // Operand: rs1 |
| 3382 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3383 | // Operand: imm12 |
| 3384 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3385 | OutInst.setLoc(MI.getLoc()); |
| 3386 | return true; |
| 3387 | } // if |
| 3388 | break; |
| 3389 | } // case C_ADDI4SPN |
| 3390 | case RISCV::C_ADDIW: { |
| 3391 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3392 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3393 | MI.getOperand(i: 0).isReg() && |
| 3394 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3395 | MI.getOperand(i: 0).isReg() && |
| 3396 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3397 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5 /* simm6 */) && |
| 3398 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 3399 | // addiw $rd, $rs1, $imm12 |
| 3400 | OutInst.setOpcode(RISCV::ADDIW); |
| 3401 | // Operand: rd |
| 3402 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3403 | // Operand: rs1 |
| 3404 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3405 | // Operand: imm12 |
| 3406 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3407 | OutInst.setLoc(MI.getLoc()); |
| 3408 | return true; |
| 3409 | } // if |
| 3410 | break; |
| 3411 | } // case C_ADDIW |
| 3412 | case RISCV::C_ADDW: { |
| 3413 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3414 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3415 | MI.getOperand(i: 0).isReg() && |
| 3416 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3417 | MI.getOperand(i: 0).isReg() && |
| 3418 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3419 | MI.getOperand(i: 2).isReg() && |
| 3420 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 3421 | // addw $rd, $rs1, $rs2 |
| 3422 | OutInst.setOpcode(RISCV::ADDW); |
| 3423 | // Operand: rd |
| 3424 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3425 | // Operand: rs1 |
| 3426 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3427 | // Operand: rs2 |
| 3428 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3429 | OutInst.setLoc(MI.getLoc()); |
| 3430 | return true; |
| 3431 | } // if |
| 3432 | break; |
| 3433 | } // case C_ADDW |
| 3434 | case RISCV::C_AND: { |
| 3435 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3436 | MI.getOperand(i: 0).isReg() && |
| 3437 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3438 | MI.getOperand(i: 0).isReg() && |
| 3439 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3440 | MI.getOperand(i: 2).isReg() && |
| 3441 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 3442 | // and $rd, $rs1, $rs2 |
| 3443 | OutInst.setOpcode(RISCV::AND); |
| 3444 | // Operand: rd |
| 3445 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3446 | // Operand: rs1 |
| 3447 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3448 | // Operand: rs2 |
| 3449 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3450 | OutInst.setLoc(MI.getLoc()); |
| 3451 | return true; |
| 3452 | } // if |
| 3453 | break; |
| 3454 | } // case C_AND |
| 3455 | case RISCV::C_ANDI: { |
| 3456 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3457 | MI.getOperand(i: 0).isReg() && |
| 3458 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3459 | MI.getOperand(i: 0).isReg() && |
| 3460 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3461 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5 /* simm6 */) && |
| 3462 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 3463 | // andi $rd, $rs1, $imm12 |
| 3464 | OutInst.setOpcode(RISCV::ANDI); |
| 3465 | // Operand: rd |
| 3466 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3467 | // Operand: rs1 |
| 3468 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3469 | // Operand: imm12 |
| 3470 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3471 | OutInst.setLoc(MI.getLoc()); |
| 3472 | return true; |
| 3473 | } // if |
| 3474 | break; |
| 3475 | } // case C_ANDI |
| 3476 | case RISCV::C_BEQZ: { |
| 3477 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3478 | MI.getOperand(i: 0).isReg() && |
| 3479 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3480 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 6 /* bare_simm9_lsb0 */) && |
| 3481 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 7 /* bare_simm13_lsb0 */)) { |
| 3482 | // beq $rs1, $rs2, $imm12 |
| 3483 | OutInst.setOpcode(RISCV::BEQ); |
| 3484 | // Operand: rs1 |
| 3485 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3486 | // Operand: rs2 |
| 3487 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 3488 | // Operand: imm12 |
| 3489 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3490 | OutInst.setLoc(MI.getLoc()); |
| 3491 | return true; |
| 3492 | } // if |
| 3493 | break; |
| 3494 | } // case C_BEQZ |
| 3495 | case RISCV::C_BNEZ: { |
| 3496 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3497 | MI.getOperand(i: 0).isReg() && |
| 3498 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3499 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 6 /* bare_simm9_lsb0 */) && |
| 3500 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 7 /* bare_simm13_lsb0 */)) { |
| 3501 | // bne $rs1, $rs2, $imm12 |
| 3502 | OutInst.setOpcode(RISCV::BNE); |
| 3503 | // Operand: rs1 |
| 3504 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3505 | // Operand: rs2 |
| 3506 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 3507 | // Operand: imm12 |
| 3508 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3509 | OutInst.setLoc(MI.getLoc()); |
| 3510 | return true; |
| 3511 | } // if |
| 3512 | break; |
| 3513 | } // case C_BNEZ |
| 3514 | case RISCV::C_EBREAK: { |
| 3515 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) { |
| 3516 | // ebreak |
| 3517 | OutInst.setOpcode(RISCV::EBREAK); |
| 3518 | OutInst.setLoc(MI.getLoc()); |
| 3519 | return true; |
| 3520 | } // if |
| 3521 | break; |
| 3522 | } // case C_EBREAK |
| 3523 | case RISCV::C_FLD: { |
| 3524 | if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && |
| 3525 | STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 3526 | MI.getOperand(i: 0).isReg() && |
| 3527 | getRISCVMCRegisterClass(RC: RISCV::FPR64CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3528 | MI.getOperand(i: 1).isReg() && |
| 3529 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3530 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000 */) && |
| 3531 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3532 | // fld $rd, ${imm12}(${rs1}) |
| 3533 | OutInst.setOpcode(RISCV::FLD); |
| 3534 | // Operand: rd |
| 3535 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3536 | // Operand: rs1 |
| 3537 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3538 | // Operand: imm12 |
| 3539 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3540 | OutInst.setLoc(MI.getLoc()); |
| 3541 | return true; |
| 3542 | } // if |
| 3543 | break; |
| 3544 | } // case C_FLD |
| 3545 | case RISCV::C_FLDSP: { |
| 3546 | if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && |
| 3547 | STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 3548 | MI.getOperand(i: 0).isReg() && |
| 3549 | getRISCVMCRegisterClass(RC: RISCV::FPR64RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3550 | MI.getOperand(i: 1).isReg() && |
| 3551 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3552 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000 */) && |
| 3553 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3554 | // fld $rd, ${imm12}(${rs1}) |
| 3555 | OutInst.setOpcode(RISCV::FLD); |
| 3556 | // Operand: rd |
| 3557 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3558 | // Operand: rs1 |
| 3559 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3560 | // Operand: imm12 |
| 3561 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3562 | OutInst.setLoc(MI.getLoc()); |
| 3563 | return true; |
| 3564 | } // if |
| 3565 | break; |
| 3566 | } // case C_FLDSP |
| 3567 | case RISCV::C_FLW: { |
| 3568 | if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && |
| 3569 | STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 3570 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3571 | MI.getOperand(i: 0).isReg() && |
| 3572 | getRISCVMCRegisterClass(RC: RISCV::FPR32CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3573 | MI.getOperand(i: 1).isReg() && |
| 3574 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3575 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 3576 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3577 | // flw $rd, ${imm12}(${rs1}) |
| 3578 | OutInst.setOpcode(RISCV::FLW); |
| 3579 | // Operand: rd |
| 3580 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3581 | // Operand: rs1 |
| 3582 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3583 | // Operand: imm12 |
| 3584 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3585 | OutInst.setLoc(MI.getLoc()); |
| 3586 | return true; |
| 3587 | } // if |
| 3588 | break; |
| 3589 | } // case C_FLW |
| 3590 | case RISCV::C_FLWSP: { |
| 3591 | if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && |
| 3592 | STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 3593 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3594 | MI.getOperand(i: 0).isReg() && |
| 3595 | getRISCVMCRegisterClass(RC: RISCV::FPR32RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3596 | MI.getOperand(i: 1).isReg() && |
| 3597 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3598 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm8_lsb00 */) && |
| 3599 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3600 | // flw $rd, ${imm12}(${rs1}) |
| 3601 | OutInst.setOpcode(RISCV::FLW); |
| 3602 | // Operand: rd |
| 3603 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3604 | // Operand: rs1 |
| 3605 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3606 | // Operand: imm12 |
| 3607 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3608 | OutInst.setLoc(MI.getLoc()); |
| 3609 | return true; |
| 3610 | } // if |
| 3611 | break; |
| 3612 | } // case C_FLWSP |
| 3613 | case RISCV::C_FSD: { |
| 3614 | if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && |
| 3615 | STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 3616 | MI.getOperand(i: 0).isReg() && |
| 3617 | getRISCVMCRegisterClass(RC: RISCV::FPR64CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3618 | MI.getOperand(i: 1).isReg() && |
| 3619 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3620 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000 */) && |
| 3621 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3622 | // fsd $rs2, ${imm12}(${rs1}) |
| 3623 | OutInst.setOpcode(RISCV::FSD); |
| 3624 | // Operand: rs2 |
| 3625 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3626 | // Operand: rs1 |
| 3627 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3628 | // Operand: imm12 |
| 3629 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3630 | OutInst.setLoc(MI.getLoc()); |
| 3631 | return true; |
| 3632 | } // if |
| 3633 | break; |
| 3634 | } // case C_FSD |
| 3635 | case RISCV::C_FSDSP: { |
| 3636 | if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && |
| 3637 | STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 3638 | MI.getOperand(i: 0).isReg() && |
| 3639 | getRISCVMCRegisterClass(RC: RISCV::FPR64RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3640 | MI.getOperand(i: 1).isReg() && |
| 3641 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3642 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000 */) && |
| 3643 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3644 | // fsd $rs2, ${imm12}(${rs1}) |
| 3645 | OutInst.setOpcode(RISCV::FSD); |
| 3646 | // Operand: rs2 |
| 3647 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3648 | // Operand: rs1 |
| 3649 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3650 | // Operand: imm12 |
| 3651 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3652 | OutInst.setLoc(MI.getLoc()); |
| 3653 | return true; |
| 3654 | } // if |
| 3655 | break; |
| 3656 | } // case C_FSDSP |
| 3657 | case RISCV::C_FSW: { |
| 3658 | if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && |
| 3659 | STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 3660 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3661 | MI.getOperand(i: 0).isReg() && |
| 3662 | getRISCVMCRegisterClass(RC: RISCV::FPR32CRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3663 | MI.getOperand(i: 1).isReg() && |
| 3664 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3665 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 3666 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3667 | // fsw $rs2, ${imm12}(${rs1}) |
| 3668 | OutInst.setOpcode(RISCV::FSW); |
| 3669 | // Operand: rs2 |
| 3670 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3671 | // Operand: rs1 |
| 3672 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3673 | // Operand: imm12 |
| 3674 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3675 | OutInst.setLoc(MI.getLoc()); |
| 3676 | return true; |
| 3677 | } // if |
| 3678 | break; |
| 3679 | } // case C_FSW |
| 3680 | case RISCV::C_FSWSP: { |
| 3681 | if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && |
| 3682 | STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 3683 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3684 | MI.getOperand(i: 0).isReg() && |
| 3685 | getRISCVMCRegisterClass(RC: RISCV::FPR32RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3686 | MI.getOperand(i: 1).isReg() && |
| 3687 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3688 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm8_lsb00 */) && |
| 3689 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3690 | // fsw $rs2, ${imm12}(${rs1}) |
| 3691 | OutInst.setOpcode(RISCV::FSW); |
| 3692 | // Operand: rs2 |
| 3693 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3694 | // Operand: rs1 |
| 3695 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3696 | // Operand: imm12 |
| 3697 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3698 | OutInst.setLoc(MI.getLoc()); |
| 3699 | return true; |
| 3700 | } // if |
| 3701 | break; |
| 3702 | } // case C_FSWSP |
| 3703 | case RISCV::C_J: { |
| 3704 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3705 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 13 /* bare_simm12_lsb0 */) && |
| 3706 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 14 /* simm21_lsb0_jal */)) { |
| 3707 | // jal $rd, $imm20 |
| 3708 | OutInst.setOpcode(RISCV::JAL); |
| 3709 | // Operand: rd |
| 3710 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 3711 | // Operand: imm20 |
| 3712 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3713 | OutInst.setLoc(MI.getLoc()); |
| 3714 | return true; |
| 3715 | } // if |
| 3716 | break; |
| 3717 | } // case C_J |
| 3718 | case RISCV::C_JAL: { |
| 3719 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3720 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3721 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 13 /* bare_simm12_lsb0 */) && |
| 3722 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 14 /* simm21_lsb0_jal */)) { |
| 3723 | // jal $rd, $imm20 |
| 3724 | OutInst.setOpcode(RISCV::JAL); |
| 3725 | // Operand: rd |
| 3726 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1)); |
| 3727 | // Operand: imm20 |
| 3728 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3729 | OutInst.setLoc(MI.getLoc()); |
| 3730 | return true; |
| 3731 | } // if |
| 3732 | break; |
| 3733 | } // case C_JAL |
| 3734 | case RISCV::C_JALR: { |
| 3735 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3736 | MI.getOperand(i: 0).isReg() && |
| 3737 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3738 | RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3739 | // jalr $rd, ${imm12}(${rs1}) |
| 3740 | OutInst.setOpcode(RISCV::JALR); |
| 3741 | // Operand: rd |
| 3742 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1)); |
| 3743 | // Operand: rs1 |
| 3744 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3745 | // Operand: imm12 |
| 3746 | OutInst.addOperand(Op: MCOperand::createImm(Val: 0)); |
| 3747 | OutInst.setLoc(MI.getLoc()); |
| 3748 | return true; |
| 3749 | } // if |
| 3750 | break; |
| 3751 | } // case C_JALR |
| 3752 | case RISCV::C_JR: { |
| 3753 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3754 | MI.getOperand(i: 0).isReg() && |
| 3755 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3756 | RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3757 | // jalr $rd, ${imm12}(${rs1}) |
| 3758 | OutInst.setOpcode(RISCV::JALR); |
| 3759 | // Operand: rd |
| 3760 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 3761 | // Operand: rs1 |
| 3762 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3763 | // Operand: imm12 |
| 3764 | OutInst.addOperand(Op: MCOperand::createImm(Val: 0)); |
| 3765 | OutInst.setLoc(MI.getLoc()); |
| 3766 | return true; |
| 3767 | } // if |
| 3768 | break; |
| 3769 | } // case C_JR |
| 3770 | case RISCV::C_LBU: { |
| 3771 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 3772 | MI.getOperand(i: 0).isReg() && |
| 3773 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3774 | MI.getOperand(i: 1).isReg() && |
| 3775 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3776 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 15 /* uimm2 */) && |
| 3777 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3778 | // lbu $rd, ${imm12}(${rs1}) |
| 3779 | OutInst.setOpcode(RISCV::LBU); |
| 3780 | // Operand: rd |
| 3781 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3782 | // Operand: rs1 |
| 3783 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3784 | // Operand: imm12 |
| 3785 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3786 | OutInst.setLoc(MI.getLoc()); |
| 3787 | return true; |
| 3788 | } // if |
| 3789 | break; |
| 3790 | } // case C_LBU |
| 3791 | case RISCV::C_LD: { |
| 3792 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3793 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3794 | MI.getOperand(i: 0).isReg() && |
| 3795 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3796 | MI.getOperand(i: 1).isReg() && |
| 3797 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3798 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000 */) && |
| 3799 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3800 | // ld $rd, ${imm12}(${rs1}) |
| 3801 | OutInst.setOpcode(RISCV::LD); |
| 3802 | // Operand: rd |
| 3803 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3804 | // Operand: rs1 |
| 3805 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3806 | // Operand: imm12 |
| 3807 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3808 | OutInst.setLoc(MI.getLoc()); |
| 3809 | return true; |
| 3810 | } // if |
| 3811 | break; |
| 3812 | } // case C_LD |
| 3813 | case RISCV::C_LDSP: { |
| 3814 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3815 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3816 | MI.getOperand(i: 0).isReg() && |
| 3817 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3818 | MI.getOperand(i: 1).isReg() && |
| 3819 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3820 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000 */) && |
| 3821 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3822 | // ld $rd, ${imm12}(${rs1}) |
| 3823 | OutInst.setOpcode(RISCV::LD); |
| 3824 | // Operand: rd |
| 3825 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3826 | // Operand: rs1 |
| 3827 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3828 | // Operand: imm12 |
| 3829 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3830 | OutInst.setLoc(MI.getLoc()); |
| 3831 | return true; |
| 3832 | } // if |
| 3833 | break; |
| 3834 | } // case C_LDSP |
| 3835 | case RISCV::C_LDSP_RV32: { |
| 3836 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 3837 | STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] && |
| 3838 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3839 | MI.getOperand(i: 0).isReg() && |
| 3840 | getRISCVMCRegisterClass(RC: RISCV::GPRPairNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3841 | MI.getOperand(i: 1).isReg() && |
| 3842 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3843 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000 */) && |
| 3844 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3845 | // ld $rd, ${imm12}(${rs1}) |
| 3846 | OutInst.setOpcode(RISCV::LD_RV32); |
| 3847 | // Operand: rd |
| 3848 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3849 | // Operand: rs1 |
| 3850 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3851 | // Operand: imm12 |
| 3852 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3853 | OutInst.setLoc(MI.getLoc()); |
| 3854 | return true; |
| 3855 | } // if |
| 3856 | break; |
| 3857 | } // case C_LDSP_RV32 |
| 3858 | case RISCV::C_LD_RV32: { |
| 3859 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 3860 | STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] && |
| 3861 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3862 | MI.getOperand(i: 0).isReg() && |
| 3863 | getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3864 | MI.getOperand(i: 1).isReg() && |
| 3865 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3866 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000 */) && |
| 3867 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3868 | // ld $rd, ${imm12}(${rs1}) |
| 3869 | OutInst.setOpcode(RISCV::LD_RV32); |
| 3870 | // Operand: rd |
| 3871 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3872 | // Operand: rs1 |
| 3873 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3874 | // Operand: imm12 |
| 3875 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3876 | OutInst.setLoc(MI.getLoc()); |
| 3877 | return true; |
| 3878 | } // if |
| 3879 | break; |
| 3880 | } // case C_LD_RV32 |
| 3881 | case RISCV::C_LH: { |
| 3882 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 3883 | MI.getOperand(i: 0).isReg() && |
| 3884 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3885 | MI.getOperand(i: 1).isReg() && |
| 3886 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3887 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16 /* uimm2_lsb0 */) && |
| 3888 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3889 | // lh $rd, ${imm12}(${rs1}) |
| 3890 | OutInst.setOpcode(RISCV::LH); |
| 3891 | // Operand: rd |
| 3892 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3893 | // Operand: rs1 |
| 3894 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3895 | // Operand: imm12 |
| 3896 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3897 | OutInst.setLoc(MI.getLoc()); |
| 3898 | return true; |
| 3899 | } // if |
| 3900 | break; |
| 3901 | } // case C_LH |
| 3902 | case RISCV::C_LHU: { |
| 3903 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 3904 | MI.getOperand(i: 0).isReg() && |
| 3905 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3906 | MI.getOperand(i: 1).isReg() && |
| 3907 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3908 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16 /* uimm2_lsb0 */) && |
| 3909 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3910 | // lhu $rd, ${imm12}(${rs1}) |
| 3911 | OutInst.setOpcode(RISCV::LHU); |
| 3912 | // Operand: rd |
| 3913 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3914 | // Operand: rs1 |
| 3915 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3916 | // Operand: imm12 |
| 3917 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3918 | OutInst.setLoc(MI.getLoc()); |
| 3919 | return true; |
| 3920 | } // if |
| 3921 | break; |
| 3922 | } // case C_LHU |
| 3923 | case RISCV::C_LI: { |
| 3924 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3925 | MI.getOperand(i: 0).isReg() && |
| 3926 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3927 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 5 /* simm6 */) && |
| 3928 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 3929 | // addi $rd, $rs1, $imm12 |
| 3930 | OutInst.setOpcode(RISCV::ADDI); |
| 3931 | // Operand: rd |
| 3932 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3933 | // Operand: rs1 |
| 3934 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 3935 | // Operand: imm12 |
| 3936 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3937 | OutInst.setLoc(MI.getLoc()); |
| 3938 | return true; |
| 3939 | } // if |
| 3940 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] && |
| 3941 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 3942 | MI.getOperand(i: 0).isReg() && |
| 3943 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3944 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 5 /* simm6 */) && |
| 3945 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 17 /* simm20_li */)) { |
| 3946 | // qc.li $rd, $imm20 |
| 3947 | OutInst.setOpcode(RISCV::QC_LI); |
| 3948 | // Operand: rd |
| 3949 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3950 | // Operand: imm20 |
| 3951 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3952 | OutInst.setLoc(MI.getLoc()); |
| 3953 | return true; |
| 3954 | } // if |
| 3955 | break; |
| 3956 | } // case C_LI |
| 3957 | case RISCV::C_LUI: { |
| 3958 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3959 | MI.getOperand(i: 0).isReg() && |
| 3960 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0X2RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3961 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 18 /* c_lui_imm */) && |
| 3962 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 19 /* uimm20_lui */)) { |
| 3963 | // lui $rd, $imm20 |
| 3964 | OutInst.setOpcode(RISCV::LUI); |
| 3965 | // Operand: rd |
| 3966 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3967 | // Operand: imm20 |
| 3968 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3969 | OutInst.setLoc(MI.getLoc()); |
| 3970 | return true; |
| 3971 | } // if |
| 3972 | break; |
| 3973 | } // case C_LUI |
| 3974 | case RISCV::C_LW: { |
| 3975 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3976 | MI.getOperand(i: 0).isReg() && |
| 3977 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3978 | MI.getOperand(i: 1).isReg() && |
| 3979 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 3980 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 3981 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 3982 | // lw $rd, ${imm12}(${rs1}) |
| 3983 | OutInst.setOpcode(RISCV::LW); |
| 3984 | // Operand: rd |
| 3985 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 3986 | // Operand: rs1 |
| 3987 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 3988 | // Operand: imm12 |
| 3989 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 3990 | OutInst.setLoc(MI.getLoc()); |
| 3991 | return true; |
| 3992 | } // if |
| 3993 | break; |
| 3994 | } // case C_LW |
| 3995 | case RISCV::C_LWSP: { |
| 3996 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 3997 | MI.getOperand(i: 0).isReg() && |
| 3998 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 3999 | MI.getOperand(i: 1).isReg() && |
| 4000 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4001 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm8_lsb00 */) && |
| 4002 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4003 | // lw $rd, ${imm12}(${rs1}) |
| 4004 | OutInst.setOpcode(RISCV::LW); |
| 4005 | // Operand: rd |
| 4006 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4007 | // Operand: rs1 |
| 4008 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4009 | // Operand: imm12 |
| 4010 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4011 | OutInst.setLoc(MI.getLoc()); |
| 4012 | return true; |
| 4013 | } // if |
| 4014 | break; |
| 4015 | } // case C_LWSP |
| 4016 | case RISCV::C_MUL: { |
| 4017 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4018 | STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] && |
| 4019 | MI.getOperand(i: 0).isReg() && |
| 4020 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4021 | MI.getOperand(i: 0).isReg() && |
| 4022 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4023 | MI.getOperand(i: 2).isReg() && |
| 4024 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 4025 | // mul $rd, $rs1, $rs2 |
| 4026 | OutInst.setOpcode(RISCV::MUL); |
| 4027 | // Operand: rd |
| 4028 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4029 | // Operand: rs1 |
| 4030 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4031 | // Operand: rs2 |
| 4032 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4033 | OutInst.setLoc(MI.getLoc()); |
| 4034 | return true; |
| 4035 | } // if |
| 4036 | break; |
| 4037 | } // case C_MUL |
| 4038 | case RISCV::C_MV: { |
| 4039 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4040 | MI.getOperand(i: 0).isReg() && |
| 4041 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4042 | MI.getOperand(i: 1).isReg() && |
| 4043 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4044 | RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 4045 | // addi $rd, $rs1, $imm12 |
| 4046 | OutInst.setOpcode(RISCV::ADDI); |
| 4047 | // Operand: rd |
| 4048 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4049 | // Operand: rs1 |
| 4050 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4051 | // Operand: imm12 |
| 4052 | OutInst.addOperand(Op: MCOperand::createImm(Val: 0)); |
| 4053 | OutInst.setLoc(MI.getLoc()); |
| 4054 | return true; |
| 4055 | } // if |
| 4056 | break; |
| 4057 | } // case C_MV |
| 4058 | case RISCV::C_NOP: { |
| 4059 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4060 | RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 4061 | // addi $rd, $rs1, $imm12 |
| 4062 | OutInst.setOpcode(RISCV::ADDI); |
| 4063 | // Operand: rd |
| 4064 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 4065 | // Operand: rs1 |
| 4066 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 4067 | // Operand: imm12 |
| 4068 | OutInst.addOperand(Op: MCOperand::createImm(Val: 0)); |
| 4069 | OutInst.setLoc(MI.getLoc()); |
| 4070 | return true; |
| 4071 | } // if |
| 4072 | break; |
| 4073 | } // case C_NOP |
| 4074 | case RISCV::C_NOT: { |
| 4075 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4076 | MI.getOperand(i: 0).isReg() && |
| 4077 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4078 | MI.getOperand(i: 0).isReg() && |
| 4079 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4080 | RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: -1), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 4081 | // xori $rd, $rs1, $imm12 |
| 4082 | OutInst.setOpcode(RISCV::XORI); |
| 4083 | // Operand: rd |
| 4084 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4085 | // Operand: rs1 |
| 4086 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4087 | // Operand: imm12 |
| 4088 | OutInst.addOperand(Op: MCOperand::createImm(Val: -1)); |
| 4089 | OutInst.setLoc(MI.getLoc()); |
| 4090 | return true; |
| 4091 | } // if |
| 4092 | break; |
| 4093 | } // case C_NOT |
| 4094 | case RISCV::C_OR: { |
| 4095 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4096 | MI.getOperand(i: 0).isReg() && |
| 4097 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4098 | MI.getOperand(i: 0).isReg() && |
| 4099 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4100 | MI.getOperand(i: 2).isReg() && |
| 4101 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 4102 | // or $rd, $rs1, $rs2 |
| 4103 | OutInst.setOpcode(RISCV::OR); |
| 4104 | // Operand: rd |
| 4105 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4106 | // Operand: rs1 |
| 4107 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4108 | // Operand: rs2 |
| 4109 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4110 | OutInst.setLoc(MI.getLoc()); |
| 4111 | return true; |
| 4112 | } // if |
| 4113 | break; |
| 4114 | } // case C_OR |
| 4115 | case RISCV::C_SB: { |
| 4116 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4117 | MI.getOperand(i: 0).isReg() && |
| 4118 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4119 | MI.getOperand(i: 1).isReg() && |
| 4120 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4121 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 15 /* uimm2 */) && |
| 4122 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4123 | // sb $rs2, ${imm12}(${rs1}) |
| 4124 | OutInst.setOpcode(RISCV::SB); |
| 4125 | // Operand: rs2 |
| 4126 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4127 | // Operand: rs1 |
| 4128 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4129 | // Operand: imm12 |
| 4130 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4131 | OutInst.setLoc(MI.getLoc()); |
| 4132 | return true; |
| 4133 | } // if |
| 4134 | break; |
| 4135 | } // case C_SB |
| 4136 | case RISCV::C_SD: { |
| 4137 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4138 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4139 | MI.getOperand(i: 0).isReg() && |
| 4140 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4141 | MI.getOperand(i: 1).isReg() && |
| 4142 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4143 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000 */) && |
| 4144 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4145 | // sd $rs2, ${imm12}(${rs1}) |
| 4146 | OutInst.setOpcode(RISCV::SD); |
| 4147 | // Operand: rs2 |
| 4148 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4149 | // Operand: rs1 |
| 4150 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4151 | // Operand: imm12 |
| 4152 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4153 | OutInst.setLoc(MI.getLoc()); |
| 4154 | return true; |
| 4155 | } // if |
| 4156 | break; |
| 4157 | } // case C_SD |
| 4158 | case RISCV::C_SDSP: { |
| 4159 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4160 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4161 | MI.getOperand(i: 0).isReg() && |
| 4162 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4163 | MI.getOperand(i: 1).isReg() && |
| 4164 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4165 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000 */) && |
| 4166 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4167 | // sd $rs2, ${imm12}(${rs1}) |
| 4168 | OutInst.setOpcode(RISCV::SD); |
| 4169 | // Operand: rs2 |
| 4170 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4171 | // Operand: rs1 |
| 4172 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4173 | // Operand: imm12 |
| 4174 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4175 | OutInst.setLoc(MI.getLoc()); |
| 4176 | return true; |
| 4177 | } // if |
| 4178 | break; |
| 4179 | } // case C_SDSP |
| 4180 | case RISCV::C_SDSP_RV32: { |
| 4181 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 4182 | STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] && |
| 4183 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4184 | MI.getOperand(i: 0).isReg() && |
| 4185 | getRISCVMCRegisterClass(RC: RISCV::GPRPairRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4186 | MI.getOperand(i: 1).isReg() && |
| 4187 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4188 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 10 /* uimm9_lsb000 */) && |
| 4189 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4190 | // sd $rs2, ${imm12}(${rs1}) |
| 4191 | OutInst.setOpcode(RISCV::SD_RV32); |
| 4192 | // Operand: rs2 |
| 4193 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4194 | // Operand: rs1 |
| 4195 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4196 | // Operand: imm12 |
| 4197 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4198 | OutInst.setLoc(MI.getLoc()); |
| 4199 | return true; |
| 4200 | } // if |
| 4201 | break; |
| 4202 | } // case C_SDSP_RV32 |
| 4203 | case RISCV::C_SD_RV32: { |
| 4204 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 4205 | STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] && |
| 4206 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4207 | MI.getOperand(i: 0).isReg() && |
| 4208 | getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4209 | MI.getOperand(i: 1).isReg() && |
| 4210 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4211 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8 /* uimm8_lsb000 */) && |
| 4212 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4213 | // sd $rs2, ${imm12}(${rs1}) |
| 4214 | OutInst.setOpcode(RISCV::SD_RV32); |
| 4215 | // Operand: rs2 |
| 4216 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4217 | // Operand: rs1 |
| 4218 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4219 | // Operand: imm12 |
| 4220 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4221 | OutInst.setLoc(MI.getLoc()); |
| 4222 | return true; |
| 4223 | } // if |
| 4224 | break; |
| 4225 | } // case C_SD_RV32 |
| 4226 | case RISCV::C_SEXT_B: { |
| 4227 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 4228 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4229 | MI.getOperand(i: 0).isReg() && |
| 4230 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4231 | MI.getOperand(i: 0).isReg() && |
| 4232 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg())) { |
| 4233 | // sext.b $rd, $rs1 |
| 4234 | OutInst.setOpcode(RISCV::SEXT_B); |
| 4235 | // Operand: rd |
| 4236 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4237 | // Operand: rs1 |
| 4238 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4239 | OutInst.setLoc(MI.getLoc()); |
| 4240 | return true; |
| 4241 | } // if |
| 4242 | break; |
| 4243 | } // case C_SEXT_B |
| 4244 | case RISCV::C_SEXT_H: { |
| 4245 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 4246 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4247 | MI.getOperand(i: 0).isReg() && |
| 4248 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4249 | MI.getOperand(i: 0).isReg() && |
| 4250 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg())) { |
| 4251 | // sext.h $rd, $rs1 |
| 4252 | OutInst.setOpcode(RISCV::SEXT_H); |
| 4253 | // Operand: rd |
| 4254 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4255 | // Operand: rs1 |
| 4256 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4257 | OutInst.setLoc(MI.getLoc()); |
| 4258 | return true; |
| 4259 | } // if |
| 4260 | break; |
| 4261 | } // case C_SEXT_H |
| 4262 | case RISCV::C_SH: { |
| 4263 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4264 | MI.getOperand(i: 0).isReg() && |
| 4265 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4266 | MI.getOperand(i: 1).isReg() && |
| 4267 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4268 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16 /* uimm2_lsb0 */) && |
| 4269 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4270 | // sh $rs2, ${imm12}(${rs1}) |
| 4271 | OutInst.setOpcode(RISCV::SH); |
| 4272 | // Operand: rs2 |
| 4273 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4274 | // Operand: rs1 |
| 4275 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4276 | // Operand: imm12 |
| 4277 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4278 | OutInst.setLoc(MI.getLoc()); |
| 4279 | return true; |
| 4280 | } // if |
| 4281 | break; |
| 4282 | } // case C_SH |
| 4283 | case RISCV::C_SLLI: { |
| 4284 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4285 | MI.getOperand(i: 0).isReg() && |
| 4286 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4287 | MI.getOperand(i: 0).isReg() && |
| 4288 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4289 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimmlog2xlennonzero */) && |
| 4290 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimmlog2xlen */)) { |
| 4291 | // slli $rd, $rs1, $shamt |
| 4292 | OutInst.setOpcode(RISCV::SLLI); |
| 4293 | // Operand: rd |
| 4294 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4295 | // Operand: rs1 |
| 4296 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4297 | // Operand: shamt |
| 4298 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4299 | OutInst.setLoc(MI.getLoc()); |
| 4300 | return true; |
| 4301 | } // if |
| 4302 | break; |
| 4303 | } // case C_SLLI |
| 4304 | case RISCV::C_SRAI: { |
| 4305 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4306 | MI.getOperand(i: 0).isReg() && |
| 4307 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4308 | MI.getOperand(i: 0).isReg() && |
| 4309 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4310 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimmlog2xlennonzero */) && |
| 4311 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimmlog2xlen */)) { |
| 4312 | // srai $rd, $rs1, $shamt |
| 4313 | OutInst.setOpcode(RISCV::SRAI); |
| 4314 | // Operand: rd |
| 4315 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4316 | // Operand: rs1 |
| 4317 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4318 | // Operand: shamt |
| 4319 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4320 | OutInst.setLoc(MI.getLoc()); |
| 4321 | return true; |
| 4322 | } // if |
| 4323 | break; |
| 4324 | } // case C_SRAI |
| 4325 | case RISCV::C_SRLI: { |
| 4326 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4327 | MI.getOperand(i: 0).isReg() && |
| 4328 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4329 | MI.getOperand(i: 0).isReg() && |
| 4330 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4331 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimmlog2xlennonzero */) && |
| 4332 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimmlog2xlen */)) { |
| 4333 | // srli $rd, $rs1, $shamt |
| 4334 | OutInst.setOpcode(RISCV::SRLI); |
| 4335 | // Operand: rd |
| 4336 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4337 | // Operand: rs1 |
| 4338 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4339 | // Operand: shamt |
| 4340 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4341 | OutInst.setLoc(MI.getLoc()); |
| 4342 | return true; |
| 4343 | } // if |
| 4344 | break; |
| 4345 | } // case C_SRLI |
| 4346 | case RISCV::C_SSPOPCHK: { |
| 4347 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] && |
| 4348 | STI.getFeatureBits()[RISCV::FeatureStdExtZimop] && |
| 4349 | MI.getOperand(i: 0).isReg() && |
| 4350 | (MI.getOperand(i: 0).getReg() == RISCV::X5)) { |
| 4351 | // sspopchk $rs1 |
| 4352 | OutInst.setOpcode(RISCV::SSPOPCHK); |
| 4353 | // Operand: rs1 |
| 4354 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5)); |
| 4355 | OutInst.setLoc(MI.getLoc()); |
| 4356 | return true; |
| 4357 | } // if |
| 4358 | break; |
| 4359 | } // case C_SSPOPCHK |
| 4360 | case RISCV::C_SSPUSH: { |
| 4361 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] && |
| 4362 | STI.getFeatureBits()[RISCV::FeatureStdExtZimop] && |
| 4363 | MI.getOperand(i: 0).isReg() && |
| 4364 | (MI.getOperand(i: 0).getReg() == RISCV::X1)) { |
| 4365 | // sspush $rs2 |
| 4366 | OutInst.setOpcode(RISCV::SSPUSH); |
| 4367 | // Operand: rs2 |
| 4368 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1)); |
| 4369 | OutInst.setLoc(MI.getLoc()); |
| 4370 | return true; |
| 4371 | } // if |
| 4372 | break; |
| 4373 | } // case C_SSPUSH |
| 4374 | case RISCV::C_SUB: { |
| 4375 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4376 | MI.getOperand(i: 0).isReg() && |
| 4377 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4378 | MI.getOperand(i: 0).isReg() && |
| 4379 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4380 | MI.getOperand(i: 2).isReg() && |
| 4381 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 4382 | // sub $rd, $rs1, $rs2 |
| 4383 | OutInst.setOpcode(RISCV::SUB); |
| 4384 | // Operand: rd |
| 4385 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4386 | // Operand: rs1 |
| 4387 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4388 | // Operand: rs2 |
| 4389 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4390 | OutInst.setLoc(MI.getLoc()); |
| 4391 | return true; |
| 4392 | } // if |
| 4393 | break; |
| 4394 | } // case C_SUB |
| 4395 | case RISCV::C_SUBW: { |
| 4396 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4397 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4398 | MI.getOperand(i: 0).isReg() && |
| 4399 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4400 | MI.getOperand(i: 0).isReg() && |
| 4401 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4402 | MI.getOperand(i: 2).isReg() && |
| 4403 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 4404 | // subw $rd, $rs1, $rs2 |
| 4405 | OutInst.setOpcode(RISCV::SUBW); |
| 4406 | // Operand: rd |
| 4407 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4408 | // Operand: rs1 |
| 4409 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4410 | // Operand: rs2 |
| 4411 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4412 | OutInst.setLoc(MI.getLoc()); |
| 4413 | return true; |
| 4414 | } // if |
| 4415 | break; |
| 4416 | } // case C_SUBW |
| 4417 | case RISCV::C_SW: { |
| 4418 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4419 | MI.getOperand(i: 0).isReg() && |
| 4420 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4421 | MI.getOperand(i: 1).isReg() && |
| 4422 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4423 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11 /* uimm7_lsb00 */) && |
| 4424 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4425 | // sw $rs2, ${imm12}(${rs1}) |
| 4426 | OutInst.setOpcode(RISCV::SW); |
| 4427 | // Operand: rs2 |
| 4428 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4429 | // Operand: rs1 |
| 4430 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4431 | // Operand: imm12 |
| 4432 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4433 | OutInst.setLoc(MI.getLoc()); |
| 4434 | return true; |
| 4435 | } // if |
| 4436 | break; |
| 4437 | } // case C_SW |
| 4438 | case RISCV::C_SWSP: { |
| 4439 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4440 | MI.getOperand(i: 0).isReg() && |
| 4441 | getRISCVMCRegisterClass(RC: RISCV::GPRRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4442 | MI.getOperand(i: 1).isReg() && |
| 4443 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4444 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12 /* uimm8_lsb00 */) && |
| 4445 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4446 | // sw $rs2, ${imm12}(${rs1}) |
| 4447 | OutInst.setOpcode(RISCV::SW); |
| 4448 | // Operand: rs2 |
| 4449 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4450 | // Operand: rs1 |
| 4451 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4452 | // Operand: imm12 |
| 4453 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4454 | OutInst.setLoc(MI.getLoc()); |
| 4455 | return true; |
| 4456 | } // if |
| 4457 | break; |
| 4458 | } // case C_SWSP |
| 4459 | case RISCV::C_UNIMP: { |
| 4460 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) { |
| 4461 | // unimp |
| 4462 | OutInst.setOpcode(RISCV::UNIMP); |
| 4463 | OutInst.setLoc(MI.getLoc()); |
| 4464 | return true; |
| 4465 | } // if |
| 4466 | break; |
| 4467 | } // case C_UNIMP |
| 4468 | case RISCV::C_XOR: { |
| 4469 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 4470 | MI.getOperand(i: 0).isReg() && |
| 4471 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4472 | MI.getOperand(i: 0).isReg() && |
| 4473 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4474 | MI.getOperand(i: 2).isReg() && |
| 4475 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 4476 | // xor $rd, $rs1, $rs2 |
| 4477 | OutInst.setOpcode(RISCV::XOR); |
| 4478 | // Operand: rd |
| 4479 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4480 | // Operand: rs1 |
| 4481 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4482 | // Operand: rs2 |
| 4483 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4484 | OutInst.setLoc(MI.getLoc()); |
| 4485 | return true; |
| 4486 | } // if |
| 4487 | break; |
| 4488 | } // case C_XOR |
| 4489 | case RISCV::C_ZEXT_B: { |
| 4490 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4491 | MI.getOperand(i: 0).isReg() && |
| 4492 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4493 | MI.getOperand(i: 0).isReg() && |
| 4494 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4495 | RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 255), STI, PredicateIndex: 2 /* simm12_lo */)) { |
| 4496 | // andi $rd, $rs1, $imm12 |
| 4497 | OutInst.setOpcode(RISCV::ANDI); |
| 4498 | // Operand: rd |
| 4499 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4500 | // Operand: rs1 |
| 4501 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4502 | // Operand: imm12 |
| 4503 | OutInst.addOperand(Op: MCOperand::createImm(Val: 255)); |
| 4504 | OutInst.setLoc(MI.getLoc()); |
| 4505 | return true; |
| 4506 | } // if |
| 4507 | break; |
| 4508 | } // case C_ZEXT_B |
| 4509 | case RISCV::C_ZEXT_H: { |
| 4510 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 4511 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4512 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4513 | (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] || STI.getFeatureBits()[RISCV::FeatureStdExtZbkb]) && |
| 4514 | MI.getOperand(i: 0).isReg() && |
| 4515 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4516 | MI.getOperand(i: 0).isReg() && |
| 4517 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg())) { |
| 4518 | // zext.h $rd, $rs1 |
| 4519 | OutInst.setOpcode(RISCV::ZEXT_H_RV32); |
| 4520 | // Operand: rd |
| 4521 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4522 | // Operand: rs1 |
| 4523 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4524 | OutInst.setLoc(MI.getLoc()); |
| 4525 | return true; |
| 4526 | } // if |
| 4527 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4528 | STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 4529 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4530 | (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] || STI.getFeatureBits()[RISCV::FeatureStdExtZbkb]) && |
| 4531 | MI.getOperand(i: 0).isReg() && |
| 4532 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4533 | MI.getOperand(i: 0).isReg() && |
| 4534 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg())) { |
| 4535 | // zext.h $rd, $rs1 |
| 4536 | OutInst.setOpcode(RISCV::ZEXT_H_RV64); |
| 4537 | // Operand: rd |
| 4538 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4539 | // Operand: rs1 |
| 4540 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4541 | OutInst.setLoc(MI.getLoc()); |
| 4542 | return true; |
| 4543 | } // if |
| 4544 | break; |
| 4545 | } // case C_ZEXT_H |
| 4546 | case RISCV::C_ZEXT_W: { |
| 4547 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4548 | STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 4549 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 4550 | MI.getOperand(i: 0).isReg() && |
| 4551 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4552 | MI.getOperand(i: 0).isReg() && |
| 4553 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg())) { |
| 4554 | // add.uw $rd, $rs1, $rs2 |
| 4555 | OutInst.setOpcode(RISCV::ADD_UW); |
| 4556 | // Operand: rd |
| 4557 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4558 | // Operand: rs1 |
| 4559 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4560 | // Operand: rs2 |
| 4561 | OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0)); |
| 4562 | OutInst.setLoc(MI.getLoc()); |
| 4563 | return true; |
| 4564 | } // if |
| 4565 | break; |
| 4566 | } // case C_ZEXT_W |
| 4567 | case RISCV::QC_C_BEXTI: { |
| 4568 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] && |
| 4569 | STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 4570 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4571 | MI.getOperand(i: 0).isReg() && |
| 4572 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4573 | MI.getOperand(i: 0).isReg() && |
| 4574 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4575 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimmlog2xlennonzero */) && |
| 4576 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimmlog2xlen */)) { |
| 4577 | // bexti $rd, $rs1, $shamt |
| 4578 | OutInst.setOpcode(RISCV::BEXTI); |
| 4579 | // Operand: rd |
| 4580 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4581 | // Operand: rs1 |
| 4582 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4583 | // Operand: shamt |
| 4584 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4585 | OutInst.setLoc(MI.getLoc()); |
| 4586 | return true; |
| 4587 | } // if |
| 4588 | break; |
| 4589 | } // case QC_C_BEXTI |
| 4590 | case RISCV::QC_C_BSETI: { |
| 4591 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] && |
| 4592 | STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 4593 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4594 | MI.getOperand(i: 0).isReg() && |
| 4595 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4596 | MI.getOperand(i: 0).isReg() && |
| 4597 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4598 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 20 /* uimmlog2xlennonzero */) && |
| 4599 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 21 /* uimmlog2xlen */)) { |
| 4600 | // bseti $rd, $rs1, $shamt |
| 4601 | OutInst.setOpcode(RISCV::BSETI); |
| 4602 | // Operand: rd |
| 4603 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4604 | // Operand: rs1 |
| 4605 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4606 | // Operand: shamt |
| 4607 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4608 | OutInst.setLoc(MI.getLoc()); |
| 4609 | return true; |
| 4610 | } // if |
| 4611 | break; |
| 4612 | } // case QC_C_BSETI |
| 4613 | case RISCV::QC_C_EXTU: { |
| 4614 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 4615 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4616 | MI.getOperand(i: 0).isReg() && |
| 4617 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4618 | MI.getOperand(i: 0).isReg() && |
| 4619 | getRISCVMCRegisterClass(RC: RISCV::GPRNoX0RegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4620 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 22 /* uimm5ge6_plus1 */) && |
| 4621 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 23 /* uimm5_plus1 */) && |
| 4622 | RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 24 /* uimm5 */)) { |
| 4623 | // qc.extu $rd, $rs1, $width, $shamt |
| 4624 | OutInst.setOpcode(RISCV::QC_EXTU); |
| 4625 | // Operand: rd |
| 4626 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4627 | // Operand: rs1 |
| 4628 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4629 | // Operand: width |
| 4630 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4631 | // Operand: shamt |
| 4632 | OutInst.addOperand(Op: MCOperand::createImm(Val: 0)); |
| 4633 | OutInst.setLoc(MI.getLoc()); |
| 4634 | return true; |
| 4635 | } // if |
| 4636 | break; |
| 4637 | } // case QC_C_EXTU |
| 4638 | case RISCV::QC_C_MVEQZ: { |
| 4639 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] && |
| 4640 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4641 | MI.getOperand(i: 0).isReg() && |
| 4642 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4643 | MI.getOperand(i: 0).isReg() && |
| 4644 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4645 | RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 25 /* simm5 */) && |
| 4646 | MI.getOperand(i: 2).isReg() && |
| 4647 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 2).getReg())) { |
| 4648 | // qc.mveqi $rd, $rs1, $imm, $rs3 |
| 4649 | OutInst.setOpcode(RISCV::QC_MVEQI); |
| 4650 | // Operand: rd_wb |
| 4651 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4652 | // Operand: rd |
| 4653 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4654 | // Operand: rs1 |
| 4655 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4656 | // Operand: imm |
| 4657 | OutInst.addOperand(Op: MCOperand::createImm(Val: 0)); |
| 4658 | // Operand: rs3 |
| 4659 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4660 | OutInst.setLoc(MI.getLoc()); |
| 4661 | return true; |
| 4662 | } // if |
| 4663 | break; |
| 4664 | } // case QC_C_MVEQZ |
| 4665 | case RISCV::QC_C_SYNC: { |
| 4666 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 4667 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4668 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 26 /* uimm5slist */) && |
| 4669 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 24 /* uimm5 */)) { |
| 4670 | // qc.sync $imm5 |
| 4671 | OutInst.setOpcode(RISCV::QC_SYNC); |
| 4672 | // Operand: imm5 |
| 4673 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4674 | OutInst.setLoc(MI.getLoc()); |
| 4675 | return true; |
| 4676 | } // if |
| 4677 | break; |
| 4678 | } // case QC_C_SYNC |
| 4679 | case RISCV::QC_C_SYNCR: { |
| 4680 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 4681 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4682 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 26 /* uimm5slist */) && |
| 4683 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 24 /* uimm5 */)) { |
| 4684 | // qc.syncr $imm5 |
| 4685 | OutInst.setOpcode(RISCV::QC_SYNCR); |
| 4686 | // Operand: imm5 |
| 4687 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4688 | OutInst.setLoc(MI.getLoc()); |
| 4689 | return true; |
| 4690 | } // if |
| 4691 | break; |
| 4692 | } // case QC_C_SYNCR |
| 4693 | case RISCV::QC_C_SYNCWF: { |
| 4694 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 4695 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4696 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 26 /* uimm5slist */) && |
| 4697 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 24 /* uimm5 */)) { |
| 4698 | // qc.syncwf $imm5 |
| 4699 | OutInst.setOpcode(RISCV::QC_SYNCWF); |
| 4700 | // Operand: imm5 |
| 4701 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4702 | OutInst.setLoc(MI.getLoc()); |
| 4703 | return true; |
| 4704 | } // if |
| 4705 | break; |
| 4706 | } // case QC_C_SYNCWF |
| 4707 | case RISCV::QC_C_SYNCWL: { |
| 4708 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 4709 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 4710 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 26 /* uimm5slist */) && |
| 4711 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 24 /* uimm5 */)) { |
| 4712 | // qc.syncwl $imm5 |
| 4713 | OutInst.setOpcode(RISCV::QC_SYNCWL); |
| 4714 | // Operand: imm5 |
| 4715 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4716 | OutInst.setLoc(MI.getLoc()); |
| 4717 | return true; |
| 4718 | } // if |
| 4719 | break; |
| 4720 | } // case QC_C_SYNCWL |
| 4721 | case RISCV::QK_C_LBU: { |
| 4722 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 4723 | MI.getOperand(i: 0).isReg() && |
| 4724 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4725 | MI.getOperand(i: 1).isReg() && |
| 4726 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4727 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 24 /* uimm5 */) && |
| 4728 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4729 | // lbu $rd, ${imm12}(${rs1}) |
| 4730 | OutInst.setOpcode(RISCV::LBU); |
| 4731 | // Operand: rd |
| 4732 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4733 | // Operand: rs1 |
| 4734 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4735 | // Operand: imm12 |
| 4736 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4737 | OutInst.setLoc(MI.getLoc()); |
| 4738 | return true; |
| 4739 | } // if |
| 4740 | break; |
| 4741 | } // case QK_C_LBU |
| 4742 | case RISCV::QK_C_LBUSP: { |
| 4743 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 4744 | MI.getOperand(i: 0).isReg() && |
| 4745 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4746 | MI.getOperand(i: 1).isReg() && |
| 4747 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4748 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 27 /* uimm4 */) && |
| 4749 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4750 | // lbu $rd, ${imm12}(${rs1}) |
| 4751 | OutInst.setOpcode(RISCV::LBU); |
| 4752 | // Operand: rd |
| 4753 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4754 | // Operand: rs1 |
| 4755 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4756 | // Operand: imm12 |
| 4757 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4758 | OutInst.setLoc(MI.getLoc()); |
| 4759 | return true; |
| 4760 | } // if |
| 4761 | break; |
| 4762 | } // case QK_C_LBUSP |
| 4763 | case RISCV::QK_C_LHU: { |
| 4764 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 4765 | MI.getOperand(i: 0).isReg() && |
| 4766 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4767 | MI.getOperand(i: 1).isReg() && |
| 4768 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4769 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 28 /* uimm6_lsb0 */) && |
| 4770 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4771 | // lhu $rd, ${imm12}(${rs1}) |
| 4772 | OutInst.setOpcode(RISCV::LHU); |
| 4773 | // Operand: rd |
| 4774 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4775 | // Operand: rs1 |
| 4776 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4777 | // Operand: imm12 |
| 4778 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4779 | OutInst.setLoc(MI.getLoc()); |
| 4780 | return true; |
| 4781 | } // if |
| 4782 | break; |
| 4783 | } // case QK_C_LHU |
| 4784 | case RISCV::QK_C_LHUSP: { |
| 4785 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 4786 | MI.getOperand(i: 0).isReg() && |
| 4787 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4788 | MI.getOperand(i: 1).isReg() && |
| 4789 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4790 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 29 /* uimm5_lsb0 */) && |
| 4791 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4792 | // lhu $rd, ${imm12}(${rs1}) |
| 4793 | OutInst.setOpcode(RISCV::LHU); |
| 4794 | // Operand: rd |
| 4795 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4796 | // Operand: rs1 |
| 4797 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4798 | // Operand: imm12 |
| 4799 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4800 | OutInst.setLoc(MI.getLoc()); |
| 4801 | return true; |
| 4802 | } // if |
| 4803 | break; |
| 4804 | } // case QK_C_LHUSP |
| 4805 | case RISCV::QK_C_SB: { |
| 4806 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 4807 | MI.getOperand(i: 0).isReg() && |
| 4808 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4809 | MI.getOperand(i: 1).isReg() && |
| 4810 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4811 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 24 /* uimm5 */) && |
| 4812 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4813 | // sb $rs2, ${imm12}(${rs1}) |
| 4814 | OutInst.setOpcode(RISCV::SB); |
| 4815 | // Operand: rs2 |
| 4816 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4817 | // Operand: rs1 |
| 4818 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4819 | // Operand: imm12 |
| 4820 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4821 | OutInst.setLoc(MI.getLoc()); |
| 4822 | return true; |
| 4823 | } // if |
| 4824 | break; |
| 4825 | } // case QK_C_SB |
| 4826 | case RISCV::QK_C_SBSP: { |
| 4827 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 4828 | MI.getOperand(i: 0).isReg() && |
| 4829 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4830 | MI.getOperand(i: 1).isReg() && |
| 4831 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4832 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 27 /* uimm4 */) && |
| 4833 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4834 | // sb $rs2, ${imm12}(${rs1}) |
| 4835 | OutInst.setOpcode(RISCV::SB); |
| 4836 | // Operand: rs2 |
| 4837 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4838 | // Operand: rs1 |
| 4839 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4840 | // Operand: imm12 |
| 4841 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4842 | OutInst.setLoc(MI.getLoc()); |
| 4843 | return true; |
| 4844 | } // if |
| 4845 | break; |
| 4846 | } // case QK_C_SBSP |
| 4847 | case RISCV::QK_C_SH: { |
| 4848 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 4849 | MI.getOperand(i: 0).isReg() && |
| 4850 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4851 | MI.getOperand(i: 1).isReg() && |
| 4852 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4853 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 28 /* uimm6_lsb0 */) && |
| 4854 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4855 | // sh $rs2, ${imm12}(${rs1}) |
| 4856 | OutInst.setOpcode(RISCV::SH); |
| 4857 | // Operand: rs2 |
| 4858 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4859 | // Operand: rs1 |
| 4860 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4861 | // Operand: imm12 |
| 4862 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4863 | OutInst.setLoc(MI.getLoc()); |
| 4864 | return true; |
| 4865 | } // if |
| 4866 | break; |
| 4867 | } // case QK_C_SH |
| 4868 | case RISCV::QK_C_SHSP: { |
| 4869 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 4870 | MI.getOperand(i: 0).isReg() && |
| 4871 | getRISCVMCRegisterClass(RC: RISCV::GPRCRegClassID).contains(Reg: MI.getOperand(i: 0).getReg()) && |
| 4872 | MI.getOperand(i: 1).isReg() && |
| 4873 | getRISCVMCRegisterClass(RC: RISCV::SPRegClassID).contains(Reg: MI.getOperand(i: 1).getReg()) && |
| 4874 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 29 /* uimm5_lsb0 */) && |
| 4875 | RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9 /* simm12_lo_optional */)) { |
| 4876 | // sh $rs2, ${imm12}(${rs1}) |
| 4877 | OutInst.setOpcode(RISCV::SH); |
| 4878 | // Operand: rs2 |
| 4879 | OutInst.addOperand(Op: MI.getOperand(i: 0)); |
| 4880 | // Operand: rs1 |
| 4881 | OutInst.addOperand(Op: MI.getOperand(i: 1)); |
| 4882 | // Operand: imm12 |
| 4883 | OutInst.addOperand(Op: MI.getOperand(i: 2)); |
| 4884 | OutInst.setLoc(MI.getLoc()); |
| 4885 | return true; |
| 4886 | } // if |
| 4887 | break; |
| 4888 | } // case QK_C_SHSP |
| 4889 | } // switch |
| 4890 | return false; |
| 4891 | } |
| 4892 | |
| 4893 | #endif // GEN_UNCOMPRESS_INSTR |
| 4894 | |
| 4895 | #ifdef GEN_CHECK_COMPRESS_INSTR |
| 4896 | #undef GEN_CHECK_COMPRESS_INSTR |
| 4897 | |
| 4898 | static bool RISCVValidateMachineOperand(const MachineOperand &MO, |
| 4899 | const RISCVSubtarget *Subtarget, |
| 4900 | unsigned PredicateIndex) { |
| 4901 | int64_t Imm = MO.getImm(); |
| 4902 | switch (PredicateIndex) { |
| 4903 | default: |
| 4904 | llvm_unreachable("Unknown ImmLeaf Predicate kind"); |
| 4905 | break; |
| 4906 | case 1: { |
| 4907 | // simm6nonzero |
| 4908 | return (Imm != 0) && isInt<6>(Imm); |
| 4909 | } |
| 4910 | case 2: { |
| 4911 | // simm6 |
| 4912 | return isInt<6>(Imm); |
| 4913 | } |
| 4914 | case 3: { |
| 4915 | // simm10_lsb0000nonzero |
| 4916 | return (Imm != 0) && isShiftedInt<6, 4>(Imm); |
| 4917 | } |
| 4918 | case 4: { |
| 4919 | // uimm10_lsb00nonzero |
| 4920 | return isShiftedUInt<8, 2>(Imm) && (Imm != 0); |
| 4921 | } |
| 4922 | case 5: { |
| 4923 | // bare_simm9_lsb0 |
| 4924 | return isShiftedInt<8, 1>(Imm); |
| 4925 | } |
| 4926 | case 6: { |
| 4927 | // uimmlog2xlennonzero |
| 4928 | if (Subtarget->is64Bit()) |
| 4929 | return isUInt<6>(Imm) && (Imm != 0); |
| 4930 | return isUInt<5>(Imm) && (Imm != 0); |
| 4931 | } |
| 4932 | case 7: { |
| 4933 | // uimm8_lsb000 |
| 4934 | return isShiftedUInt<5, 3>(Imm); |
| 4935 | } |
| 4936 | case 8: { |
| 4937 | // uimm8_lsb000_optional |
| 4938 | return isShiftedUInt<5, 3>(Imm); |
| 4939 | } |
| 4940 | case 9: { |
| 4941 | // uimm9_lsb000 |
| 4942 | return isShiftedUInt<6, 3>(Imm); |
| 4943 | } |
| 4944 | case 10: { |
| 4945 | // uimm9_lsb000_optional |
| 4946 | return isShiftedUInt<6, 3>(Imm); |
| 4947 | } |
| 4948 | case 11: { |
| 4949 | // uimm7_lsb00 |
| 4950 | return isShiftedUInt<5, 2>(Imm); |
| 4951 | } |
| 4952 | case 12: { |
| 4953 | // uimm7_lsb00_optional |
| 4954 | return isShiftedUInt<5, 2>(Imm); |
| 4955 | } |
| 4956 | case 13: { |
| 4957 | // uimm8_lsb00 |
| 4958 | return isShiftedUInt<6, 2>(Imm); |
| 4959 | } |
| 4960 | case 14: { |
| 4961 | // uimm8_lsb00_optional |
| 4962 | return isShiftedUInt<6, 2>(Imm); |
| 4963 | } |
| 4964 | case 15: { |
| 4965 | // bare_simm12_lsb0 |
| 4966 | return isShiftedInt<11, 1>(Imm); |
| 4967 | } |
| 4968 | case 16: { |
| 4969 | // uimm2 |
| 4970 | return isUInt<2>(Imm); |
| 4971 | } |
| 4972 | case 17: { |
| 4973 | // uimm2_optional |
| 4974 | return isUInt<2>(Imm); |
| 4975 | } |
| 4976 | case 18: { |
| 4977 | // uimm5 |
| 4978 | return isUInt<5>(Imm); |
| 4979 | } |
| 4980 | case 19: { |
| 4981 | // uimm4 |
| 4982 | return isUInt<4>(Imm); |
| 4983 | } |
| 4984 | case 20: { |
| 4985 | // uimm2_lsb0 |
| 4986 | return isShiftedUInt<1, 1>(Imm); |
| 4987 | } |
| 4988 | case 21: { |
| 4989 | // uimm2_lsb0_optional |
| 4990 | return isShiftedUInt<1, 1>(Imm); |
| 4991 | } |
| 4992 | case 22: { |
| 4993 | // uimm6_lsb0 |
| 4994 | return isShiftedUInt<5, 1>(Imm); |
| 4995 | } |
| 4996 | case 23: { |
| 4997 | // uimm5_lsb0 |
| 4998 | return isShiftedUInt<4, 1>(Imm); |
| 4999 | } |
| 5000 | case 24: { |
| 5001 | // c_lui_imm |
| 5002 | return (Imm != 0) && |
| 5003 | (isUInt<5>(Imm) || |
| 5004 | (Imm >= 0xfffe0 && Imm <= 0xfffff)); |
| 5005 | } |
| 5006 | case 25: { |
| 5007 | // uimm5ge6_plus1 |
| 5008 | return Imm >= 6 && Imm <= 32; |
| 5009 | } |
| 5010 | case 26: { |
| 5011 | // simm12_lo |
| 5012 | return isInt<12>(Imm); |
| 5013 | } |
| 5014 | case 27: { |
| 5015 | // simm5nonzero |
| 5016 | return (Imm != 0) && isInt<5>(Imm); |
| 5017 | } |
| 5018 | case 28: { |
| 5019 | // bare_simm13_lsb0 |
| 5020 | return isShiftedInt<12, 1>(Imm); |
| 5021 | } |
| 5022 | case 29: { |
| 5023 | // uimm5nonzero |
| 5024 | return (Imm != 0) && isUInt<5>(Imm); |
| 5025 | } |
| 5026 | case 30: { |
| 5027 | // simm21_lsb0_jal |
| 5028 | return isShiftedInt<20, 1>(Imm); |
| 5029 | } |
| 5030 | case 31: { |
| 5031 | // simm12_lo_optional |
| 5032 | return isInt<12>(Imm); |
| 5033 | } |
| 5034 | case 32: { |
| 5035 | // simm20_li |
| 5036 | return isInt<20>(Imm); |
| 5037 | } |
| 5038 | case 33: { |
| 5039 | // uimm5slist |
| 5040 | return ((Imm == 0) || |
| 5041 | (Imm == 1) || |
| 5042 | (Imm == 2) || |
| 5043 | (Imm == 4) || |
| 5044 | (Imm == 8) || |
| 5045 | (Imm == 16) || |
| 5046 | (Imm == 15) || |
| 5047 | (Imm == 31)); |
| 5048 | } |
| 5049 | case 34: { |
| 5050 | // uimmlog2xlen |
| 5051 | if (Subtarget->is64Bit()) |
| 5052 | return isUInt<6>(Imm); |
| 5053 | return isUInt<5>(Imm); |
| 5054 | } |
| 5055 | } |
| 5056 | } |
| 5057 | |
| 5058 | static bool isCompressibleInst(const MachineInstr &MI, |
| 5059 | const RISCVSubtarget &STI) { |
| 5060 | switch (MI.getOpcode()) { |
| 5061 | default: return false; |
| 5062 | case RISCV::ADD: { |
| 5063 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5064 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5065 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5066 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5067 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 5068 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5069 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg())) { |
| 5070 | // c.add $rs1, $rs2 |
| 5071 | // Operand: rd |
| 5072 | // Operand: rs1 |
| 5073 | // Operand: rs2 |
| 5074 | return true; |
| 5075 | } // if |
| 5076 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5077 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 5078 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 5079 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5080 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()) && |
| 5081 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5082 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) { |
| 5083 | // c.add $rs1, $rs2 |
| 5084 | // Operand: rd |
| 5085 | // Operand: rs1 |
| 5086 | // Operand: rs2 |
| 5087 | return true; |
| 5088 | } // if |
| 5089 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5090 | MI.getOperand(1).isReg() && |
| 5091 | (MI.getOperand(1).getReg() == RISCV::X0) && |
| 5092 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5093 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5094 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5095 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg())) { |
| 5096 | // c.mv $rs1, $rs2 |
| 5097 | // Operand: rs1 |
| 5098 | // Operand: rs2 |
| 5099 | return true; |
| 5100 | } // if |
| 5101 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5102 | MI.getOperand(2).isReg() && |
| 5103 | (MI.getOperand(2).getReg() == RISCV::X0) && |
| 5104 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5105 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5106 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5107 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) { |
| 5108 | // c.mv $rs1, $rs2 |
| 5109 | // Operand: rs1 |
| 5110 | // Operand: rs2 |
| 5111 | return true; |
| 5112 | } // if |
| 5113 | break; |
| 5114 | } // case ADD |
| 5115 | case RISCV::ADDI: { |
| 5116 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5117 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5118 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5119 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5120 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 5121 | MI.getOperand(2).isImm() && |
| 5122 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6nonzero */) && |
| 5123 | MI.getOperand(2).isImm() && |
| 5124 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 5125 | // c.addi $rd, $imm |
| 5126 | // Operand: rd_wb |
| 5127 | // Operand: rd |
| 5128 | // Operand: imm |
| 5129 | return true; |
| 5130 | } // if |
| 5131 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5132 | MI.getOperand(0).isReg() && |
| 5133 | (MI.getOperand(0).getReg() == RISCV::X2) && |
| 5134 | MI.getOperand(1).isReg() && |
| 5135 | (MI.getOperand(1).getReg() == RISCV::X2) && |
| 5136 | MI.getOperand(2).isImm() && |
| 5137 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 3 /* simm10_lsb0000nonzero */)) { |
| 5138 | // c.addi16sp $rd, $imm |
| 5139 | // Operand: rd_wb |
| 5140 | // Operand: rd |
| 5141 | // Operand: imm |
| 5142 | return true; |
| 5143 | } // if |
| 5144 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5145 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5146 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5147 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5148 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5149 | MI.getOperand(2).isImm() && |
| 5150 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4 /* uimm10_lsb00nonzero */)) { |
| 5151 | // c.addi4spn $rd, $rs1, $imm |
| 5152 | // Operand: rd |
| 5153 | // Operand: rs1 |
| 5154 | // Operand: imm |
| 5155 | return true; |
| 5156 | } // if |
| 5157 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5158 | MI.getOperand(1).isReg() && |
| 5159 | (MI.getOperand(1).getReg() == RISCV::X0) && |
| 5160 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5161 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5162 | MI.getOperand(2).isImm() && |
| 5163 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 5164 | // c.li $rd, $imm |
| 5165 | // Operand: rd |
| 5166 | // Operand: imm |
| 5167 | return true; |
| 5168 | } // if |
| 5169 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5170 | MI.getOperand(2).isImm() && |
| 5171 | (MI.getOperand(2).getImm() == 0) && |
| 5172 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5173 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5174 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5175 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) { |
| 5176 | // c.mv $rs1, $rs2 |
| 5177 | // Operand: rs1 |
| 5178 | // Operand: rs2 |
| 5179 | return true; |
| 5180 | } // if |
| 5181 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5182 | MI.getOperand(0).isReg() && |
| 5183 | (MI.getOperand(0).getReg() == RISCV::X0) && |
| 5184 | MI.getOperand(1).isReg() && |
| 5185 | (MI.getOperand(1).getReg() == RISCV::X0) && |
| 5186 | MI.getOperand(2).isImm() && |
| 5187 | (MI.getOperand(2).getImm() == 0)) { |
| 5188 | // c.nop |
| 5189 | return true; |
| 5190 | } // if |
| 5191 | break; |
| 5192 | } // case ADDI |
| 5193 | case RISCV::ADDIW: { |
| 5194 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5195 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5196 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5197 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5198 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5199 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 5200 | MI.getOperand(2).isImm() && |
| 5201 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 5202 | // c.addiw $rd, $imm |
| 5203 | // Operand: rd_wb |
| 5204 | // Operand: rd |
| 5205 | // Operand: imm |
| 5206 | return true; |
| 5207 | } // if |
| 5208 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5209 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5210 | MI.getOperand(1).isReg() && |
| 5211 | (MI.getOperand(1).getReg() == RISCV::X0) && |
| 5212 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5213 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5214 | MI.getOperand(2).isImm() && |
| 5215 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 5216 | // c.li $rd, $imm |
| 5217 | // Operand: rd |
| 5218 | // Operand: imm |
| 5219 | return true; |
| 5220 | } // if |
| 5221 | break; |
| 5222 | } // case ADDIW |
| 5223 | case RISCV::ADDW: { |
| 5224 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5225 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5226 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5227 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5228 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5229 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5230 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5231 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) { |
| 5232 | // c.addw $rd, $rs2 |
| 5233 | // Operand: rd_wb |
| 5234 | // Operand: rd |
| 5235 | // Operand: rs2 |
| 5236 | return true; |
| 5237 | } // if |
| 5238 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5239 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5240 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 5241 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 5242 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5243 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 5244 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5245 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 5246 | // c.addw $rd, $rs2 |
| 5247 | // Operand: rd_wb |
| 5248 | // Operand: rd |
| 5249 | // Operand: rs2 |
| 5250 | return true; |
| 5251 | } // if |
| 5252 | break; |
| 5253 | } // case ADDW |
| 5254 | case RISCV::ADD_UW: { |
| 5255 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5256 | STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 5257 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 5258 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5259 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5260 | MI.getOperand(2).isReg() && |
| 5261 | (MI.getOperand(2).getReg() == RISCV::X0) && |
| 5262 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5263 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 5264 | // c.zext.w $rd |
| 5265 | // Operand: rd_wb |
| 5266 | // Operand: rd |
| 5267 | return true; |
| 5268 | } // if |
| 5269 | break; |
| 5270 | } // case ADD_UW |
| 5271 | case RISCV::AND: { |
| 5272 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5273 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5274 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5275 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5276 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5277 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5278 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) { |
| 5279 | // c.and $rd, $rs2 |
| 5280 | // Operand: rd_wb |
| 5281 | // Operand: rd |
| 5282 | // Operand: rs2 |
| 5283 | return true; |
| 5284 | } // if |
| 5285 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5286 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 5287 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 5288 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5289 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 5290 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5291 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 5292 | // c.and $rd, $rs2 |
| 5293 | // Operand: rd_wb |
| 5294 | // Operand: rd |
| 5295 | // Operand: rs2 |
| 5296 | return true; |
| 5297 | } // if |
| 5298 | break; |
| 5299 | } // case AND |
| 5300 | case RISCV::ANDI: { |
| 5301 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5302 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5303 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5304 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5305 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5306 | MI.getOperand(2).isImm() && |
| 5307 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 5308 | // c.andi $rs1, $imm |
| 5309 | // Operand: rd |
| 5310 | // Operand: rs1 |
| 5311 | // Operand: imm |
| 5312 | return true; |
| 5313 | } // if |
| 5314 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 5315 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5316 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5317 | MI.getOperand(2).isImm() && |
| 5318 | (MI.getOperand(2).getImm() == 255) && |
| 5319 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5320 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 5321 | // c.zext.b $rd |
| 5322 | // Operand: rd_wb |
| 5323 | // Operand: rd |
| 5324 | return true; |
| 5325 | } // if |
| 5326 | break; |
| 5327 | } // case ANDI |
| 5328 | case RISCV::BEQ: { |
| 5329 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5330 | MI.getOperand(1).isReg() && |
| 5331 | (MI.getOperand(1).getReg() == RISCV::X0) && |
| 5332 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5333 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5334 | MI.getOperand(2).isImm() && |
| 5335 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5 /* bare_simm9_lsb0 */)) { |
| 5336 | // c.beqz $rs1, $imm |
| 5337 | // Operand: rs1 |
| 5338 | // Operand: imm |
| 5339 | return true; |
| 5340 | } // if |
| 5341 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5342 | MI.getOperand(0).isReg() && |
| 5343 | (MI.getOperand(0).getReg() == RISCV::X0) && |
| 5344 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5345 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5346 | MI.getOperand(2).isImm() && |
| 5347 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5 /* bare_simm9_lsb0 */)) { |
| 5348 | // c.beqz $rs1, $imm |
| 5349 | // Operand: rs1 |
| 5350 | // Operand: imm |
| 5351 | return true; |
| 5352 | } // if |
| 5353 | break; |
| 5354 | } // case BEQ |
| 5355 | case RISCV::BEXTI: { |
| 5356 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] && |
| 5357 | STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 5358 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5359 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5360 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5361 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5362 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5363 | MI.getOperand(2).isImm() && |
| 5364 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6 /* uimmlog2xlennonzero */)) { |
| 5365 | // qc.c.bexti $rs1, $shamt |
| 5366 | // Operand: rd |
| 5367 | // Operand: rs1 |
| 5368 | // Operand: shamt |
| 5369 | return true; |
| 5370 | } // if |
| 5371 | break; |
| 5372 | } // case BEXTI |
| 5373 | case RISCV::BNE: { |
| 5374 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5375 | MI.getOperand(1).isReg() && |
| 5376 | (MI.getOperand(1).getReg() == RISCV::X0) && |
| 5377 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5378 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5379 | MI.getOperand(2).isImm() && |
| 5380 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5 /* bare_simm9_lsb0 */)) { |
| 5381 | // c.bnez $rs1, $imm |
| 5382 | // Operand: rs1 |
| 5383 | // Operand: imm |
| 5384 | return true; |
| 5385 | } // if |
| 5386 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5387 | MI.getOperand(0).isReg() && |
| 5388 | (MI.getOperand(0).getReg() == RISCV::X0) && |
| 5389 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5390 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5391 | MI.getOperand(2).isImm() && |
| 5392 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5 /* bare_simm9_lsb0 */)) { |
| 5393 | // c.bnez $rs1, $imm |
| 5394 | // Operand: rs1 |
| 5395 | // Operand: imm |
| 5396 | return true; |
| 5397 | } // if |
| 5398 | break; |
| 5399 | } // case BNE |
| 5400 | case RISCV::BSETI: { |
| 5401 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] && |
| 5402 | STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 5403 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5404 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5405 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5406 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5407 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5408 | MI.getOperand(2).isImm() && |
| 5409 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6 /* uimmlog2xlennonzero */)) { |
| 5410 | // qc.c.bseti $rs1, $shamt |
| 5411 | // Operand: rd |
| 5412 | // Operand: rs1 |
| 5413 | // Operand: shamt |
| 5414 | return true; |
| 5415 | } // if |
| 5416 | break; |
| 5417 | } // case BSETI |
| 5418 | case RISCV::EBREAK: { |
| 5419 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) { |
| 5420 | // c.ebreak |
| 5421 | return true; |
| 5422 | } // if |
| 5423 | break; |
| 5424 | } // case EBREAK |
| 5425 | case RISCV::FLD: { |
| 5426 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 5427 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5428 | getRISCVMCRegisterClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5429 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5430 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5431 | MI.getOperand(2).isImm() && |
| 5432 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7 /* uimm8_lsb000 */) && |
| 5433 | MI.getOperand(2).isImm() && |
| 5434 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8 /* uimm8_lsb000_optional */)) { |
| 5435 | // c.fld $rd, ${imm}(${rs1}) |
| 5436 | // Operand: rd |
| 5437 | // Operand: rs1 |
| 5438 | // Operand: imm |
| 5439 | return true; |
| 5440 | } // if |
| 5441 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 5442 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5443 | getRISCVMCRegisterClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5444 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5445 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5446 | MI.getOperand(2).isImm() && |
| 5447 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9 /* uimm9_lsb000 */) && |
| 5448 | MI.getOperand(2).isImm() && |
| 5449 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 10 /* uimm9_lsb000_optional */)) { |
| 5450 | // c.fldsp $rd, ${imm}(${rs1}) |
| 5451 | // Operand: rd |
| 5452 | // Operand: rs1 |
| 5453 | // Operand: imm |
| 5454 | return true; |
| 5455 | } // if |
| 5456 | break; |
| 5457 | } // case FLD |
| 5458 | case RISCV::FLW: { |
| 5459 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 5460 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5461 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5462 | getRISCVMCRegisterClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5463 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5464 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5465 | MI.getOperand(2).isImm() && |
| 5466 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11 /* uimm7_lsb00 */) && |
| 5467 | MI.getOperand(2).isImm() && |
| 5468 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12 /* uimm7_lsb00_optional */)) { |
| 5469 | // c.flw $rd, ${imm}(${rs1}) |
| 5470 | // Operand: rd |
| 5471 | // Operand: rs1 |
| 5472 | // Operand: imm |
| 5473 | return true; |
| 5474 | } // if |
| 5475 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 5476 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5477 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5478 | getRISCVMCRegisterClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5479 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5480 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5481 | MI.getOperand(2).isImm() && |
| 5482 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13 /* uimm8_lsb00 */) && |
| 5483 | MI.getOperand(2).isImm() && |
| 5484 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14 /* uimm8_lsb00_optional */)) { |
| 5485 | // c.flwsp $rd, ${imm}(${rs1}) |
| 5486 | // Operand: rd |
| 5487 | // Operand: rs1 |
| 5488 | // Operand: imm |
| 5489 | return true; |
| 5490 | } // if |
| 5491 | break; |
| 5492 | } // case FLW |
| 5493 | case RISCV::FSD: { |
| 5494 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 5495 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5496 | getRISCVMCRegisterClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5497 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5498 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5499 | MI.getOperand(2).isImm() && |
| 5500 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7 /* uimm8_lsb000 */) && |
| 5501 | MI.getOperand(2).isImm() && |
| 5502 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8 /* uimm8_lsb000_optional */)) { |
| 5503 | // c.fsd $rs2, ${imm}(${rs1}) |
| 5504 | // Operand: rs2 |
| 5505 | // Operand: rs1 |
| 5506 | // Operand: imm |
| 5507 | return true; |
| 5508 | } // if |
| 5509 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcd] && |
| 5510 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5511 | getRISCVMCRegisterClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5512 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5513 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5514 | MI.getOperand(2).isImm() && |
| 5515 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9 /* uimm9_lsb000 */) && |
| 5516 | MI.getOperand(2).isImm() && |
| 5517 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 10 /* uimm9_lsb000_optional */)) { |
| 5518 | // c.fsdsp $rs2, ${imm}(${rs1}) |
| 5519 | // Operand: rs2 |
| 5520 | // Operand: rs1 |
| 5521 | // Operand: imm |
| 5522 | return true; |
| 5523 | } // if |
| 5524 | break; |
| 5525 | } // case FSD |
| 5526 | case RISCV::FSW: { |
| 5527 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 5528 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5529 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5530 | getRISCVMCRegisterClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5531 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5532 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5533 | MI.getOperand(2).isImm() && |
| 5534 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11 /* uimm7_lsb00 */) && |
| 5535 | MI.getOperand(2).isImm() && |
| 5536 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12 /* uimm7_lsb00_optional */)) { |
| 5537 | // c.fsw $rs2, ${imm}(${rs1}) |
| 5538 | // Operand: rs2 |
| 5539 | // Operand: rs1 |
| 5540 | // Operand: imm |
| 5541 | return true; |
| 5542 | } // if |
| 5543 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcf] && |
| 5544 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5545 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5546 | getRISCVMCRegisterClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5547 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5548 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5549 | MI.getOperand(2).isImm() && |
| 5550 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13 /* uimm8_lsb00 */) && |
| 5551 | MI.getOperand(2).isImm() && |
| 5552 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14 /* uimm8_lsb00_optional */)) { |
| 5553 | // c.fswsp $rs2, ${imm}(${rs1}) |
| 5554 | // Operand: rs2 |
| 5555 | // Operand: rs1 |
| 5556 | // Operand: imm |
| 5557 | return true; |
| 5558 | } // if |
| 5559 | break; |
| 5560 | } // case FSW |
| 5561 | case RISCV::JAL: { |
| 5562 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5563 | MI.getOperand(0).isReg() && |
| 5564 | (MI.getOperand(0).getReg() == RISCV::X0) && |
| 5565 | MI.getOperand(1).isImm() && |
| 5566 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 15 /* bare_simm12_lsb0 */)) { |
| 5567 | // c.j $offset |
| 5568 | // Operand: offset |
| 5569 | return true; |
| 5570 | } // if |
| 5571 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5572 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5573 | MI.getOperand(0).isReg() && |
| 5574 | (MI.getOperand(0).getReg() == RISCV::X1) && |
| 5575 | MI.getOperand(1).isImm() && |
| 5576 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 15 /* bare_simm12_lsb0 */)) { |
| 5577 | // c.jal $offset |
| 5578 | // Operand: offset |
| 5579 | return true; |
| 5580 | } // if |
| 5581 | break; |
| 5582 | } // case JAL |
| 5583 | case RISCV::JALR: { |
| 5584 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5585 | MI.getOperand(0).isReg() && |
| 5586 | (MI.getOperand(0).getReg() == RISCV::X1) && |
| 5587 | MI.getOperand(2).isImm() && |
| 5588 | (MI.getOperand(2).getImm() == 0) && |
| 5589 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5590 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) { |
| 5591 | // c.jalr $rs1 |
| 5592 | // Operand: rs1 |
| 5593 | return true; |
| 5594 | } // if |
| 5595 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5596 | MI.getOperand(0).isReg() && |
| 5597 | (MI.getOperand(0).getReg() == RISCV::X0) && |
| 5598 | MI.getOperand(2).isImm() && |
| 5599 | (MI.getOperand(2).getImm() == 0) && |
| 5600 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5601 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) { |
| 5602 | // c.jr $rs1 |
| 5603 | // Operand: rs1 |
| 5604 | return true; |
| 5605 | } // if |
| 5606 | break; |
| 5607 | } // case JALR |
| 5608 | case RISCV::LBU: { |
| 5609 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 5610 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5611 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5612 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5613 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5614 | MI.getOperand(2).isImm() && |
| 5615 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 16 /* uimm2 */) && |
| 5616 | MI.getOperand(2).isImm() && |
| 5617 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 17 /* uimm2_optional */)) { |
| 5618 | // c.lbu $rd, ${imm}(${rs1}) |
| 5619 | // Operand: rd |
| 5620 | // Operand: rs1 |
| 5621 | // Operand: imm |
| 5622 | return true; |
| 5623 | } // if |
| 5624 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 5625 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5626 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5627 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5628 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5629 | MI.getOperand(2).isImm() && |
| 5630 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 18 /* uimm5 */)) { |
| 5631 | // qk.c.lbu $rd, ${imm}(${rs1}) |
| 5632 | // Operand: rd |
| 5633 | // Operand: rs1 |
| 5634 | // Operand: imm |
| 5635 | return true; |
| 5636 | } // if |
| 5637 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 5638 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5639 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5640 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5641 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5642 | MI.getOperand(2).isImm() && |
| 5643 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 19 /* uimm4 */)) { |
| 5644 | // qk.c.lbusp $rd_rs2, ${imm}(${rs1}) |
| 5645 | // Operand: rd_rs2 |
| 5646 | // Operand: rs1 |
| 5647 | // Operand: imm |
| 5648 | return true; |
| 5649 | } // if |
| 5650 | break; |
| 5651 | } // case LBU |
| 5652 | case RISCV::LD: { |
| 5653 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5654 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5655 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5656 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5657 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5658 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5659 | MI.getOperand(2).isImm() && |
| 5660 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7 /* uimm8_lsb000 */) && |
| 5661 | MI.getOperand(2).isImm() && |
| 5662 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8 /* uimm8_lsb000_optional */)) { |
| 5663 | // c.ld $rd, ${imm}(${rs1}) |
| 5664 | // Operand: rd |
| 5665 | // Operand: rs1 |
| 5666 | // Operand: imm |
| 5667 | return true; |
| 5668 | } // if |
| 5669 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5670 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5671 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5672 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5673 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5674 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5675 | MI.getOperand(2).isImm() && |
| 5676 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9 /* uimm9_lsb000 */) && |
| 5677 | MI.getOperand(2).isImm() && |
| 5678 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 10 /* uimm9_lsb000_optional */)) { |
| 5679 | // c.ldsp $rd, ${imm}(${rs1}) |
| 5680 | // Operand: rd |
| 5681 | // Operand: rs1 |
| 5682 | // Operand: imm |
| 5683 | return true; |
| 5684 | } // if |
| 5685 | break; |
| 5686 | } // case LD |
| 5687 | case RISCV::LD_RV32: { |
| 5688 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 5689 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5690 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5691 | getRISCVMCRegisterClass(RISCV::GPRPairNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5692 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5693 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5694 | MI.getOperand(2).isImm() && |
| 5695 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9 /* uimm9_lsb000 */) && |
| 5696 | MI.getOperand(2).isImm() && |
| 5697 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 10 /* uimm9_lsb000_optional */)) { |
| 5698 | // c.ldsp $rd, ${imm}(${rs1}) |
| 5699 | // Operand: rd |
| 5700 | // Operand: rs1 |
| 5701 | // Operand: imm |
| 5702 | return true; |
| 5703 | } // if |
| 5704 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 5705 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5706 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5707 | getRISCVMCRegisterClass(RISCV::GPRPairCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5708 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5709 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5710 | MI.getOperand(2).isImm() && |
| 5711 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7 /* uimm8_lsb000 */) && |
| 5712 | MI.getOperand(2).isImm() && |
| 5713 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8 /* uimm8_lsb000_optional */)) { |
| 5714 | // c.ld $rd, ${imm}(${rs1}) |
| 5715 | // Operand: rd |
| 5716 | // Operand: rs1 |
| 5717 | // Operand: imm |
| 5718 | return true; |
| 5719 | } // if |
| 5720 | break; |
| 5721 | } // case LD_RV32 |
| 5722 | case RISCV::LH: { |
| 5723 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 5724 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5725 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5726 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5727 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5728 | MI.getOperand(2).isImm() && |
| 5729 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 20 /* uimm2_lsb0 */) && |
| 5730 | MI.getOperand(2).isImm() && |
| 5731 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 21 /* uimm2_lsb0_optional */)) { |
| 5732 | // c.lh $rd, ${imm}(${rs1}) |
| 5733 | // Operand: rd |
| 5734 | // Operand: rs1 |
| 5735 | // Operand: imm |
| 5736 | return true; |
| 5737 | } // if |
| 5738 | break; |
| 5739 | } // case LH |
| 5740 | case RISCV::LHU: { |
| 5741 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 5742 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5743 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5744 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5745 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5746 | MI.getOperand(2).isImm() && |
| 5747 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 20 /* uimm2_lsb0 */) && |
| 5748 | MI.getOperand(2).isImm() && |
| 5749 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 21 /* uimm2_lsb0_optional */)) { |
| 5750 | // c.lhu $rd, ${imm}(${rs1}) |
| 5751 | // Operand: rd |
| 5752 | // Operand: rs1 |
| 5753 | // Operand: imm |
| 5754 | return true; |
| 5755 | } // if |
| 5756 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 5757 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5758 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5759 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5760 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5761 | MI.getOperand(2).isImm() && |
| 5762 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 22 /* uimm6_lsb0 */)) { |
| 5763 | // qk.c.lhu $rd, ${imm}(${rs1}) |
| 5764 | // Operand: rd |
| 5765 | // Operand: rs1 |
| 5766 | // Operand: imm |
| 5767 | return true; |
| 5768 | } // if |
| 5769 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 5770 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5771 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5772 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5773 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5774 | MI.getOperand(2).isImm() && |
| 5775 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 23 /* uimm5_lsb0 */)) { |
| 5776 | // qk.c.lhusp $rd_rs2, ${imm}(${rs1}) |
| 5777 | // Operand: rd_rs2 |
| 5778 | // Operand: rs1 |
| 5779 | // Operand: imm |
| 5780 | return true; |
| 5781 | } // if |
| 5782 | break; |
| 5783 | } // case LHU |
| 5784 | case RISCV::LH_INX: { |
| 5785 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 5786 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5787 | getRISCVMCRegisterClass(RISCV::GPRF16CRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5788 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5789 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5790 | MI.getOperand(2).isImm() && |
| 5791 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 20 /* uimm2_lsb0 */) && |
| 5792 | MI.getOperand(2).isImm() && |
| 5793 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 21 /* uimm2_lsb0_optional */)) { |
| 5794 | // c.lh $rd, ${imm}(${rs1}) |
| 5795 | // Operand: rd |
| 5796 | // Operand: rs1 |
| 5797 | // Operand: imm |
| 5798 | return true; |
| 5799 | } // if |
| 5800 | break; |
| 5801 | } // case LH_INX |
| 5802 | case RISCV::LUI: { |
| 5803 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5804 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5805 | getRISCVMCRegisterClass(RISCV::GPRNoX0X2RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5806 | MI.getOperand(1).isImm() && |
| 5807 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 24 /* c_lui_imm */)) { |
| 5808 | // c.lui $rd, $imm |
| 5809 | // Operand: rd |
| 5810 | // Operand: imm |
| 5811 | return true; |
| 5812 | } // if |
| 5813 | break; |
| 5814 | } // case LUI |
| 5815 | case RISCV::LW: { |
| 5816 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5817 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5818 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5819 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5820 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5821 | MI.getOperand(2).isImm() && |
| 5822 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11 /* uimm7_lsb00 */) && |
| 5823 | MI.getOperand(2).isImm() && |
| 5824 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12 /* uimm7_lsb00_optional */)) { |
| 5825 | // c.lw $rd, ${imm}(${rs1}) |
| 5826 | // Operand: rd |
| 5827 | // Operand: rs1 |
| 5828 | // Operand: imm |
| 5829 | return true; |
| 5830 | } // if |
| 5831 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5832 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5833 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5834 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5835 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5836 | MI.getOperand(2).isImm() && |
| 5837 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13 /* uimm8_lsb00 */) && |
| 5838 | MI.getOperand(2).isImm() && |
| 5839 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14 /* uimm8_lsb00_optional */)) { |
| 5840 | // c.lwsp $rd, ${imm}(${rs1}) |
| 5841 | // Operand: rd |
| 5842 | // Operand: rs1 |
| 5843 | // Operand: imm |
| 5844 | return true; |
| 5845 | } // if |
| 5846 | break; |
| 5847 | } // case LW |
| 5848 | case RISCV::LW_INX: { |
| 5849 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5850 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5851 | getRISCVMCRegisterClass(RISCV::GPRF32NoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5852 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5853 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5854 | MI.getOperand(2).isImm() && |
| 5855 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13 /* uimm8_lsb00 */) && |
| 5856 | MI.getOperand(2).isImm() && |
| 5857 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14 /* uimm8_lsb00_optional */)) { |
| 5858 | // c.lwsp $rd, ${imm}(${rs1}) |
| 5859 | // Operand: rd |
| 5860 | // Operand: rs1 |
| 5861 | // Operand: imm |
| 5862 | return true; |
| 5863 | } // if |
| 5864 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5865 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5866 | getRISCVMCRegisterClass(RISCV::GPRF32CRegClassID).contains(MI.getOperand(0).getReg()) && |
| 5867 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5868 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5869 | MI.getOperand(2).isImm() && |
| 5870 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11 /* uimm7_lsb00 */) && |
| 5871 | MI.getOperand(2).isImm() && |
| 5872 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12 /* uimm7_lsb00_optional */)) { |
| 5873 | // c.lw $rd, ${imm}(${rs1}) |
| 5874 | // Operand: rd |
| 5875 | // Operand: rs1 |
| 5876 | // Operand: imm |
| 5877 | return true; |
| 5878 | } // if |
| 5879 | break; |
| 5880 | } // case LW_INX |
| 5881 | case RISCV::MUL: { |
| 5882 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 5883 | STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] && |
| 5884 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5885 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5886 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5887 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5888 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5889 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) { |
| 5890 | // c.mul $rd, $rs2 |
| 5891 | // Operand: rd_wb |
| 5892 | // Operand: rd |
| 5893 | // Operand: rs2 |
| 5894 | return true; |
| 5895 | } // if |
| 5896 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 5897 | STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] && |
| 5898 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 5899 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 5900 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5901 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 5902 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5903 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 5904 | // c.mul $rd, $rs2 |
| 5905 | // Operand: rd_wb |
| 5906 | // Operand: rd |
| 5907 | // Operand: rs2 |
| 5908 | return true; |
| 5909 | } // if |
| 5910 | break; |
| 5911 | } // case MUL |
| 5912 | case RISCV::OR: { |
| 5913 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5914 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5915 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5916 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5917 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5918 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5919 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) { |
| 5920 | // c.or $rd, $rs2 |
| 5921 | // Operand: rd_wb |
| 5922 | // Operand: rd |
| 5923 | // Operand: rs2 |
| 5924 | return true; |
| 5925 | } // if |
| 5926 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5927 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 5928 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 5929 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 5930 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 5931 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5932 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 5933 | // c.or $rd, $rs2 |
| 5934 | // Operand: rd_wb |
| 5935 | // Operand: rd |
| 5936 | // Operand: rs2 |
| 5937 | return true; |
| 5938 | } // if |
| 5939 | break; |
| 5940 | } // case OR |
| 5941 | case RISCV::QC_EXTU: { |
| 5942 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] && |
| 5943 | STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 5944 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5945 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5946 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5947 | MI.getOperand(2).isImm() && |
| 5948 | (MI.getOperand(2).getImm() == 1) && |
| 5949 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5950 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 5951 | MI.getOperand(3).isImm() && |
| 5952 | RISCVValidateMachineOperand(MI.getOperand(3), &STI, 6 /* uimmlog2xlennonzero */)) { |
| 5953 | // qc.c.bexti $rs1, $shamt |
| 5954 | // Operand: rd |
| 5955 | // Operand: rs1 |
| 5956 | // Operand: shamt |
| 5957 | return true; |
| 5958 | } // if |
| 5959 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] && |
| 5960 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5961 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 5962 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 5963 | MI.getOperand(3).isImm() && |
| 5964 | (MI.getOperand(3).getImm() == 0) && |
| 5965 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 5966 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 5967 | MI.getOperand(2).isImm() && |
| 5968 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 25 /* uimm5ge6_plus1 */)) { |
| 5969 | // qc.c.extu $rd, $width |
| 5970 | // Operand: rd_wb |
| 5971 | // Operand: rd |
| 5972 | // Operand: width |
| 5973 | return true; |
| 5974 | } // if |
| 5975 | break; |
| 5976 | } // case QC_EXTU |
| 5977 | case RISCV::QC_E_ADDAI: { |
| 5978 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 5979 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5980 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5981 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5982 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5983 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5984 | MI.getOperand(2).isImm() && |
| 5985 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */)) { |
| 5986 | // addi $rd, $rs1, $imm12 |
| 5987 | // Operand: rd |
| 5988 | // Operand: rs1 |
| 5989 | // Operand: imm12 |
| 5990 | return true; |
| 5991 | } // if |
| 5992 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 5993 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 5994 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 5995 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 5996 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 5997 | MI.getOperand(2).isImm() && |
| 5998 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6nonzero */) && |
| 5999 | MI.getOperand(2).isImm() && |
| 6000 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 6001 | // c.addi $rd, $imm |
| 6002 | // Operand: rd_wb |
| 6003 | // Operand: rd |
| 6004 | // Operand: imm |
| 6005 | return true; |
| 6006 | } // if |
| 6007 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6008 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6009 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6010 | MI.getOperand(0).isReg() && |
| 6011 | (MI.getOperand(0).getReg() == RISCV::X2) && |
| 6012 | MI.getOperand(1).isReg() && |
| 6013 | (MI.getOperand(1).getReg() == RISCV::X2) && |
| 6014 | MI.getOperand(2).isImm() && |
| 6015 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 3 /* simm10_lsb0000nonzero */)) { |
| 6016 | // c.addi16sp $rd, $imm |
| 6017 | // Operand: rd_wb |
| 6018 | // Operand: rd |
| 6019 | // Operand: imm |
| 6020 | return true; |
| 6021 | } // if |
| 6022 | break; |
| 6023 | } // case QC_E_ADDAI |
| 6024 | case RISCV::QC_E_ADDI: { |
| 6025 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6026 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6027 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6028 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6029 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6030 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 6031 | MI.getOperand(2).isImm() && |
| 6032 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */)) { |
| 6033 | // addi $rd, $rs1, $imm12 |
| 6034 | // Operand: rd |
| 6035 | // Operand: rs1 |
| 6036 | // Operand: imm12 |
| 6037 | return true; |
| 6038 | } // if |
| 6039 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6040 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6041 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6042 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 6043 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 6044 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6045 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 6046 | MI.getOperand(2).isImm() && |
| 6047 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6nonzero */) && |
| 6048 | MI.getOperand(2).isImm() && |
| 6049 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 6050 | // c.addi $rd, $imm |
| 6051 | // Operand: rd_wb |
| 6052 | // Operand: rd |
| 6053 | // Operand: imm |
| 6054 | return true; |
| 6055 | } // if |
| 6056 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6057 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6058 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6059 | MI.getOperand(0).isReg() && |
| 6060 | (MI.getOperand(0).getReg() == RISCV::X2) && |
| 6061 | MI.getOperand(1).isReg() && |
| 6062 | (MI.getOperand(1).getReg() == RISCV::X2) && |
| 6063 | MI.getOperand(2).isImm() && |
| 6064 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 3 /* simm10_lsb0000nonzero */)) { |
| 6065 | // c.addi16sp $rd, $imm |
| 6066 | // Operand: rd_wb |
| 6067 | // Operand: rd |
| 6068 | // Operand: imm |
| 6069 | return true; |
| 6070 | } // if |
| 6071 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6072 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6073 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6074 | MI.getOperand(2).isImm() && |
| 6075 | (MI.getOperand(2).getImm() == 0) && |
| 6076 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6077 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6078 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6079 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) { |
| 6080 | // c.mv $rs1, $rs2 |
| 6081 | // Operand: rs1 |
| 6082 | // Operand: rs2 |
| 6083 | return true; |
| 6084 | } // if |
| 6085 | break; |
| 6086 | } // case QC_E_ADDI |
| 6087 | case RISCV::QC_E_ANDAI: { |
| 6088 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6089 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6090 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6091 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6092 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6093 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6094 | MI.getOperand(2).isImm() && |
| 6095 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */)) { |
| 6096 | // andi $rd, $rs1, $imm12 |
| 6097 | // Operand: rd |
| 6098 | // Operand: rs1 |
| 6099 | // Operand: imm12 |
| 6100 | return true; |
| 6101 | } // if |
| 6102 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6103 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6104 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6105 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6106 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6107 | MI.getOperand(2).isImm() && |
| 6108 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 6109 | // c.andi $rs1, $imm |
| 6110 | // Operand: rd |
| 6111 | // Operand: rs1 |
| 6112 | // Operand: imm |
| 6113 | return true; |
| 6114 | } // if |
| 6115 | break; |
| 6116 | } // case QC_E_ANDAI |
| 6117 | case RISCV::QC_E_ANDI: { |
| 6118 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6119 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6120 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6121 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6122 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6123 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 6124 | MI.getOperand(2).isImm() && |
| 6125 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */)) { |
| 6126 | // andi $rd, $rs1, $imm12 |
| 6127 | // Operand: rd |
| 6128 | // Operand: rs1 |
| 6129 | // Operand: imm12 |
| 6130 | return true; |
| 6131 | } // if |
| 6132 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6133 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6134 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6135 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 6136 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 6137 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6138 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6139 | MI.getOperand(2).isImm() && |
| 6140 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2 /* simm6 */)) { |
| 6141 | // c.andi $rs1, $imm |
| 6142 | // Operand: rd |
| 6143 | // Operand: rs1 |
| 6144 | // Operand: imm |
| 6145 | return true; |
| 6146 | } // if |
| 6147 | break; |
| 6148 | } // case QC_E_ANDI |
| 6149 | case RISCV::QC_E_BEQI: { |
| 6150 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 6151 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6152 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6153 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6154 | MI.getOperand(1).isImm() && |
| 6155 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 27 /* simm5nonzero */) && |
| 6156 | MI.getOperand(2).isImm() && |
| 6157 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 28 /* bare_simm13_lsb0 */)) { |
| 6158 | // qc.beqi $rs1, $rs2, $imm12 |
| 6159 | // Operand: rs1 |
| 6160 | // Operand: rs2 |
| 6161 | // Operand: imm12 |
| 6162 | return true; |
| 6163 | } // if |
| 6164 | break; |
| 6165 | } // case QC_E_BEQI |
| 6166 | case RISCV::QC_E_BGEI: { |
| 6167 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 6168 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6169 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6170 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6171 | MI.getOperand(1).isImm() && |
| 6172 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 27 /* simm5nonzero */) && |
| 6173 | MI.getOperand(2).isImm() && |
| 6174 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 28 /* bare_simm13_lsb0 */)) { |
| 6175 | // qc.bgei $rs1, $rs2, $imm12 |
| 6176 | // Operand: rs1 |
| 6177 | // Operand: rs2 |
| 6178 | // Operand: imm12 |
| 6179 | return true; |
| 6180 | } // if |
| 6181 | break; |
| 6182 | } // case QC_E_BGEI |
| 6183 | case RISCV::QC_E_BGEUI: { |
| 6184 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 6185 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6186 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6187 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6188 | MI.getOperand(1).isImm() && |
| 6189 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 29 /* uimm5nonzero */) && |
| 6190 | MI.getOperand(2).isImm() && |
| 6191 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 28 /* bare_simm13_lsb0 */)) { |
| 6192 | // qc.bgeui $rs1, $rs2, $imm12 |
| 6193 | // Operand: rs1 |
| 6194 | // Operand: rs2 |
| 6195 | // Operand: imm12 |
| 6196 | return true; |
| 6197 | } // if |
| 6198 | break; |
| 6199 | } // case QC_E_BGEUI |
| 6200 | case RISCV::QC_E_BLTI: { |
| 6201 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 6202 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6203 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6204 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6205 | MI.getOperand(1).isImm() && |
| 6206 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 27 /* simm5nonzero */) && |
| 6207 | MI.getOperand(2).isImm() && |
| 6208 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 28 /* bare_simm13_lsb0 */)) { |
| 6209 | // qc.blti $rs1, $rs2, $imm12 |
| 6210 | // Operand: rs1 |
| 6211 | // Operand: rs2 |
| 6212 | // Operand: imm12 |
| 6213 | return true; |
| 6214 | } // if |
| 6215 | break; |
| 6216 | } // case QC_E_BLTI |
| 6217 | case RISCV::QC_E_BLTUI: { |
| 6218 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 6219 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6220 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6221 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6222 | MI.getOperand(1).isImm() && |
| 6223 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 29 /* uimm5nonzero */) && |
| 6224 | MI.getOperand(2).isImm() && |
| 6225 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 28 /* bare_simm13_lsb0 */)) { |
| 6226 | // qc.bltui $rs1, $rs2, $imm12 |
| 6227 | // Operand: rs1 |
| 6228 | // Operand: rs2 |
| 6229 | // Operand: imm12 |
| 6230 | return true; |
| 6231 | } // if |
| 6232 | break; |
| 6233 | } // case QC_E_BLTUI |
| 6234 | case RISCV::QC_E_BNEI: { |
| 6235 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] && |
| 6236 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6237 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6238 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6239 | MI.getOperand(1).isImm() && |
| 6240 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 27 /* simm5nonzero */) && |
| 6241 | MI.getOperand(2).isImm() && |
| 6242 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 28 /* bare_simm13_lsb0 */)) { |
| 6243 | // qc.bnei $rs1, $rs2, $imm12 |
| 6244 | // Operand: rs1 |
| 6245 | // Operand: rs2 |
| 6246 | // Operand: imm12 |
| 6247 | return true; |
| 6248 | } // if |
| 6249 | break; |
| 6250 | } // case QC_E_BNEI |
| 6251 | case RISCV::QC_E_J: { |
| 6252 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6253 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] && |
| 6254 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6255 | MI.getOperand(0).isImm() && |
| 6256 | RISCVValidateMachineOperand(MI.getOperand(0), &STI, 15 /* bare_simm12_lsb0 */)) { |
| 6257 | // c.j $offset |
| 6258 | // Operand: offset |
| 6259 | return true; |
| 6260 | } // if |
| 6261 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] && |
| 6262 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6263 | MI.getOperand(0).isImm() && |
| 6264 | RISCVValidateMachineOperand(MI.getOperand(0), &STI, 30 /* simm21_lsb0_jal */)) { |
| 6265 | // jal $rd, $imm20 |
| 6266 | // Operand: rd |
| 6267 | // Operand: imm20 |
| 6268 | return true; |
| 6269 | } // if |
| 6270 | break; |
| 6271 | } // case QC_E_J |
| 6272 | case RISCV::QC_E_JAL: { |
| 6273 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6274 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] && |
| 6275 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6276 | MI.getOperand(0).isImm() && |
| 6277 | RISCVValidateMachineOperand(MI.getOperand(0), &STI, 15 /* bare_simm12_lsb0 */)) { |
| 6278 | // c.jal $offset |
| 6279 | // Operand: offset |
| 6280 | return true; |
| 6281 | } // if |
| 6282 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] && |
| 6283 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6284 | MI.getOperand(0).isImm() && |
| 6285 | RISCVValidateMachineOperand(MI.getOperand(0), &STI, 30 /* simm21_lsb0_jal */)) { |
| 6286 | // jal $rd, $imm20 |
| 6287 | // Operand: rd |
| 6288 | // Operand: imm20 |
| 6289 | return true; |
| 6290 | } // if |
| 6291 | break; |
| 6292 | } // case QC_E_JAL |
| 6293 | case RISCV::QC_E_LB: { |
| 6294 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6295 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6296 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6297 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6298 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6299 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6300 | MI.getOperand(2).isImm() && |
| 6301 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */) && |
| 6302 | MI.getOperand(2).isImm() && |
| 6303 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 31 /* simm12_lo_optional */)) { |
| 6304 | // lb $rd, ${imm12}(${rs1}) |
| 6305 | // Operand: rd |
| 6306 | // Operand: rs1 |
| 6307 | // Operand: imm12 |
| 6308 | return true; |
| 6309 | } // if |
| 6310 | break; |
| 6311 | } // case QC_E_LB |
| 6312 | case RISCV::QC_E_LBU: { |
| 6313 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6314 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6315 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6316 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6317 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6318 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6319 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6320 | MI.getOperand(2).isImm() && |
| 6321 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 16 /* uimm2 */) && |
| 6322 | MI.getOperand(2).isImm() && |
| 6323 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 17 /* uimm2_optional */)) { |
| 6324 | // c.lbu $rd, ${imm}(${rs1}) |
| 6325 | // Operand: rd |
| 6326 | // Operand: rs1 |
| 6327 | // Operand: imm |
| 6328 | return true; |
| 6329 | } // if |
| 6330 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6331 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6332 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6333 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6334 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6335 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6336 | MI.getOperand(2).isImm() && |
| 6337 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */) && |
| 6338 | MI.getOperand(2).isImm() && |
| 6339 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 31 /* simm12_lo_optional */)) { |
| 6340 | // lbu $rd, ${imm12}(${rs1}) |
| 6341 | // Operand: rd |
| 6342 | // Operand: rs1 |
| 6343 | // Operand: imm12 |
| 6344 | return true; |
| 6345 | } // if |
| 6346 | break; |
| 6347 | } // case QC_E_LBU |
| 6348 | case RISCV::QC_E_LH: { |
| 6349 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6350 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6351 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6352 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6353 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6354 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6355 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6356 | MI.getOperand(2).isImm() && |
| 6357 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 20 /* uimm2_lsb0 */) && |
| 6358 | MI.getOperand(2).isImm() && |
| 6359 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 21 /* uimm2_lsb0_optional */)) { |
| 6360 | // c.lh $rd, ${imm}(${rs1}) |
| 6361 | // Operand: rd |
| 6362 | // Operand: rs1 |
| 6363 | // Operand: imm |
| 6364 | return true; |
| 6365 | } // if |
| 6366 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6367 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6368 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6369 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6370 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6371 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6372 | MI.getOperand(2).isImm() && |
| 6373 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */) && |
| 6374 | MI.getOperand(2).isImm() && |
| 6375 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 31 /* simm12_lo_optional */)) { |
| 6376 | // lh $rd, ${imm12}(${rs1}) |
| 6377 | // Operand: rd |
| 6378 | // Operand: rs1 |
| 6379 | // Operand: imm12 |
| 6380 | return true; |
| 6381 | } // if |
| 6382 | break; |
| 6383 | } // case QC_E_LH |
| 6384 | case RISCV::QC_E_LHU: { |
| 6385 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6386 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6387 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6388 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6389 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6390 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6391 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6392 | MI.getOperand(2).isImm() && |
| 6393 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 20 /* uimm2_lsb0 */) && |
| 6394 | MI.getOperand(2).isImm() && |
| 6395 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 21 /* uimm2_lsb0_optional */)) { |
| 6396 | // c.lhu $rd, ${imm}(${rs1}) |
| 6397 | // Operand: rd |
| 6398 | // Operand: rs1 |
| 6399 | // Operand: imm |
| 6400 | return true; |
| 6401 | } // if |
| 6402 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6403 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6404 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6405 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6406 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6407 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6408 | MI.getOperand(2).isImm() && |
| 6409 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */) && |
| 6410 | MI.getOperand(2).isImm() && |
| 6411 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 31 /* simm12_lo_optional */)) { |
| 6412 | // lhu $rd, ${imm12}(${rs1}) |
| 6413 | // Operand: rd |
| 6414 | // Operand: rs1 |
| 6415 | // Operand: imm12 |
| 6416 | return true; |
| 6417 | } // if |
| 6418 | break; |
| 6419 | } // case QC_E_LHU |
| 6420 | case RISCV::QC_E_LI: { |
| 6421 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6422 | STI.getFeatureBits()[RISCV::FeatureVendorXqcili] && |
| 6423 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6424 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6425 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6426 | MI.getOperand(1).isImm() && |
| 6427 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 2 /* simm6 */)) { |
| 6428 | // c.li $rd, $imm |
| 6429 | // Operand: rd |
| 6430 | // Operand: imm |
| 6431 | return true; |
| 6432 | } // if |
| 6433 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] && |
| 6434 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6435 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6436 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6437 | MI.getOperand(1).isImm() && |
| 6438 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 32 /* simm20_li */)) { |
| 6439 | // qc.li $rd, $imm20 |
| 6440 | // Operand: rd |
| 6441 | // Operand: imm20 |
| 6442 | return true; |
| 6443 | } // if |
| 6444 | break; |
| 6445 | } // case QC_E_LI |
| 6446 | case RISCV::QC_E_LW: { |
| 6447 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6448 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6449 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6450 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6451 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6452 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6453 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6454 | MI.getOperand(2).isImm() && |
| 6455 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11 /* uimm7_lsb00 */) && |
| 6456 | MI.getOperand(2).isImm() && |
| 6457 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12 /* uimm7_lsb00_optional */)) { |
| 6458 | // c.lw $rd, ${imm}(${rs1}) |
| 6459 | // Operand: rd |
| 6460 | // Operand: rs1 |
| 6461 | // Operand: imm |
| 6462 | return true; |
| 6463 | } // if |
| 6464 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6465 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6466 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6467 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6468 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6469 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6470 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6471 | MI.getOperand(2).isImm() && |
| 6472 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13 /* uimm8_lsb00 */) && |
| 6473 | MI.getOperand(2).isImm() && |
| 6474 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14 /* uimm8_lsb00_optional */)) { |
| 6475 | // c.lwsp $rd, ${imm}(${rs1}) |
| 6476 | // Operand: rd |
| 6477 | // Operand: rs1 |
| 6478 | // Operand: imm |
| 6479 | return true; |
| 6480 | } // if |
| 6481 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6482 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6483 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6484 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6485 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6486 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6487 | MI.getOperand(2).isImm() && |
| 6488 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */) && |
| 6489 | MI.getOperand(2).isImm() && |
| 6490 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 31 /* simm12_lo_optional */)) { |
| 6491 | // lw $rd, ${imm12}(${rs1}) |
| 6492 | // Operand: rd |
| 6493 | // Operand: rs1 |
| 6494 | // Operand: imm12 |
| 6495 | return true; |
| 6496 | } // if |
| 6497 | break; |
| 6498 | } // case QC_E_LW |
| 6499 | case RISCV::QC_E_ORAI: { |
| 6500 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6501 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6502 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6503 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6504 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6505 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6506 | MI.getOperand(2).isImm() && |
| 6507 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */)) { |
| 6508 | // ori $rd, $rs1, $imm12 |
| 6509 | // Operand: rd |
| 6510 | // Operand: rs1 |
| 6511 | // Operand: imm12 |
| 6512 | return true; |
| 6513 | } // if |
| 6514 | break; |
| 6515 | } // case QC_E_ORAI |
| 6516 | case RISCV::QC_E_ORI: { |
| 6517 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6518 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6519 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6520 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6521 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6522 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 6523 | MI.getOperand(2).isImm() && |
| 6524 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */)) { |
| 6525 | // ori $rd, $rs1, $imm12 |
| 6526 | // Operand: rd |
| 6527 | // Operand: rs1 |
| 6528 | // Operand: imm12 |
| 6529 | return true; |
| 6530 | } // if |
| 6531 | break; |
| 6532 | } // case QC_E_ORI |
| 6533 | case RISCV::QC_E_SB: { |
| 6534 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6535 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6536 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6537 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6538 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6539 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6540 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6541 | MI.getOperand(2).isImm() && |
| 6542 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 16 /* uimm2 */) && |
| 6543 | MI.getOperand(2).isImm() && |
| 6544 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 17 /* uimm2_optional */)) { |
| 6545 | // c.sb $rs2, ${imm}(${rs1}) |
| 6546 | // Operand: rs2 |
| 6547 | // Operand: rs1 |
| 6548 | // Operand: imm |
| 6549 | return true; |
| 6550 | } // if |
| 6551 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6552 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6553 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6554 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6555 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6556 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6557 | MI.getOperand(2).isImm() && |
| 6558 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */) && |
| 6559 | MI.getOperand(2).isImm() && |
| 6560 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 31 /* simm12_lo_optional */)) { |
| 6561 | // sb $rs2, ${imm12}(${rs1}) |
| 6562 | // Operand: rs2 |
| 6563 | // Operand: rs1 |
| 6564 | // Operand: imm12 |
| 6565 | return true; |
| 6566 | } // if |
| 6567 | break; |
| 6568 | } // case QC_E_SB |
| 6569 | case RISCV::QC_E_SH: { |
| 6570 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6571 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6572 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6573 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6574 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6575 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6576 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6577 | MI.getOperand(2).isImm() && |
| 6578 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 20 /* uimm2_lsb0 */) && |
| 6579 | MI.getOperand(2).isImm() && |
| 6580 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 21 /* uimm2_lsb0_optional */)) { |
| 6581 | // c.sh $rs2, ${imm}(${rs1}) |
| 6582 | // Operand: rs2 |
| 6583 | // Operand: rs1 |
| 6584 | // Operand: imm |
| 6585 | return true; |
| 6586 | } // if |
| 6587 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6588 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6589 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6590 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6591 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6592 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6593 | MI.getOperand(2).isImm() && |
| 6594 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */) && |
| 6595 | MI.getOperand(2).isImm() && |
| 6596 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 31 /* simm12_lo_optional */)) { |
| 6597 | // sh $rs2, ${imm12}(${rs1}) |
| 6598 | // Operand: rs2 |
| 6599 | // Operand: rs1 |
| 6600 | // Operand: imm12 |
| 6601 | return true; |
| 6602 | } // if |
| 6603 | break; |
| 6604 | } // case QC_E_SH |
| 6605 | case RISCV::QC_E_SW: { |
| 6606 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6607 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6608 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6609 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6610 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6611 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6612 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6613 | MI.getOperand(2).isImm() && |
| 6614 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11 /* uimm7_lsb00 */) && |
| 6615 | MI.getOperand(2).isImm() && |
| 6616 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12 /* uimm7_lsb00_optional */)) { |
| 6617 | // c.sw $rs2, ${imm}(${rs1}) |
| 6618 | // Operand: rs2 |
| 6619 | // Operand: rs1 |
| 6620 | // Operand: imm |
| 6621 | return true; |
| 6622 | } // if |
| 6623 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6624 | STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6625 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6626 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6627 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6628 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6629 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6630 | MI.getOperand(2).isImm() && |
| 6631 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13 /* uimm8_lsb00 */) && |
| 6632 | MI.getOperand(2).isImm() && |
| 6633 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14 /* uimm8_lsb00_optional */)) { |
| 6634 | // c.swsp $rs2, ${imm}(${rs1}) |
| 6635 | // Operand: rs2 |
| 6636 | // Operand: rs1 |
| 6637 | // Operand: imm |
| 6638 | return true; |
| 6639 | } // if |
| 6640 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] && |
| 6641 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6642 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6643 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6644 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6645 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6646 | MI.getOperand(2).isImm() && |
| 6647 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */) && |
| 6648 | MI.getOperand(2).isImm() && |
| 6649 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 31 /* simm12_lo_optional */)) { |
| 6650 | // sw $rs2, ${imm12}(${rs1}) |
| 6651 | // Operand: rs2 |
| 6652 | // Operand: rs1 |
| 6653 | // Operand: imm12 |
| 6654 | return true; |
| 6655 | } // if |
| 6656 | break; |
| 6657 | } // case QC_E_SW |
| 6658 | case RISCV::QC_E_XORAI: { |
| 6659 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6660 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6661 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6662 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6663 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6664 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6665 | MI.getOperand(2).isImm() && |
| 6666 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */)) { |
| 6667 | // xori $rd, $rs1, $imm12 |
| 6668 | // Operand: rd |
| 6669 | // Operand: rs1 |
| 6670 | // Operand: imm12 |
| 6671 | return true; |
| 6672 | } // if |
| 6673 | break; |
| 6674 | } // case QC_E_XORAI |
| 6675 | case RISCV::QC_E_XORI: { |
| 6676 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] && |
| 6677 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6678 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6679 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6680 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6681 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 6682 | MI.getOperand(2).isImm() && |
| 6683 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 26 /* simm12_lo */)) { |
| 6684 | // xori $rd, $rs1, $imm12 |
| 6685 | // Operand: rd |
| 6686 | // Operand: rs1 |
| 6687 | // Operand: imm12 |
| 6688 | return true; |
| 6689 | } // if |
| 6690 | break; |
| 6691 | } // case QC_E_XORI |
| 6692 | case RISCV::QC_LI: { |
| 6693 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6694 | STI.getFeatureBits()[RISCV::FeatureVendorXqcili] && |
| 6695 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6696 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6697 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg()) && |
| 6698 | MI.getOperand(1).isImm() && |
| 6699 | RISCVValidateMachineOperand(MI.getOperand(1), &STI, 2 /* simm6 */)) { |
| 6700 | // c.li $rd, $imm |
| 6701 | // Operand: rd |
| 6702 | // Operand: imm |
| 6703 | return true; |
| 6704 | } // if |
| 6705 | break; |
| 6706 | } // case QC_LI |
| 6707 | case RISCV::QC_MULIADD: { |
| 6708 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 6709 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6710 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6711 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6712 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 6713 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 6714 | MI.getOperand(3).isImm() && |
| 6715 | RISCVValidateMachineOperand(MI.getOperand(3), &STI, 18 /* uimm5 */)) { |
| 6716 | // qc.c.muliadd $rd, $rs1, $uimm |
| 6717 | // Operand: rd_wb |
| 6718 | // Operand: rd |
| 6719 | // Operand: rs1 |
| 6720 | // Operand: uimm |
| 6721 | return true; |
| 6722 | } // if |
| 6723 | break; |
| 6724 | } // case QC_MULIADD |
| 6725 | case RISCV::QC_MVEQI: { |
| 6726 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] && |
| 6727 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6728 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 6729 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 6730 | MI.getOperand(3).isImm() && |
| 6731 | (MI.getOperand(3).getImm() == 0) && |
| 6732 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 6733 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 6734 | MI.getOperand(4).isReg() && MI.getOperand(4).getReg().isPhysical() && |
| 6735 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(4).getReg())) { |
| 6736 | // qc.c.mveqz $rd, $rs1 |
| 6737 | // Operand: rd_wb |
| 6738 | // Operand: rd |
| 6739 | // Operand: rs1 |
| 6740 | return true; |
| 6741 | } // if |
| 6742 | break; |
| 6743 | } // case QC_MVEQI |
| 6744 | case RISCV::QC_MVLTUI: { |
| 6745 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] && |
| 6746 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6747 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 6748 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 6749 | MI.getOperand(3).isImm() && |
| 6750 | (MI.getOperand(3).getImm() == 1) && |
| 6751 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 6752 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 6753 | MI.getOperand(4).isReg() && MI.getOperand(4).getReg().isPhysical() && |
| 6754 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(4).getReg())) { |
| 6755 | // qc.c.mveqz $rd, $rs1 |
| 6756 | // Operand: rd_wb |
| 6757 | // Operand: rd |
| 6758 | // Operand: rs1 |
| 6759 | return true; |
| 6760 | } // if |
| 6761 | break; |
| 6762 | } // case QC_MVLTUI |
| 6763 | case RISCV::QC_SHLADD: { |
| 6764 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 6765 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6766 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 6767 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 6768 | MI.getOperand(3).isImm() && |
| 6769 | (MI.getOperand(3).getImm() == 4) && |
| 6770 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 6771 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 6772 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6773 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6774 | RISCVValidateMachineOperand(MachineOperand::CreateImm(16), &STI, 18 /* uimm5 */)) { |
| 6775 | // qc.c.muliadd $rd, $rs1, $uimm |
| 6776 | // Operand: rd_wb |
| 6777 | // Operand: rd |
| 6778 | // Operand: rs1 |
| 6779 | // Operand: uimm |
| 6780 | return true; |
| 6781 | } // if |
| 6782 | break; |
| 6783 | } // case QC_SHLADD |
| 6784 | case RISCV::QC_SYNC: { |
| 6785 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 6786 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6787 | MI.getOperand(0).isImm() && |
| 6788 | RISCVValidateMachineOperand(MI.getOperand(0), &STI, 33 /* uimm5slist */)) { |
| 6789 | // qc.c.sync $slist |
| 6790 | // Operand: slist |
| 6791 | return true; |
| 6792 | } // if |
| 6793 | break; |
| 6794 | } // case QC_SYNC |
| 6795 | case RISCV::QC_SYNCR: { |
| 6796 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 6797 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6798 | MI.getOperand(0).isImm() && |
| 6799 | RISCVValidateMachineOperand(MI.getOperand(0), &STI, 33 /* uimm5slist */)) { |
| 6800 | // qc.c.syncr $slist |
| 6801 | // Operand: slist |
| 6802 | return true; |
| 6803 | } // if |
| 6804 | break; |
| 6805 | } // case QC_SYNCR |
| 6806 | case RISCV::QC_SYNCWF: { |
| 6807 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 6808 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6809 | MI.getOperand(0).isImm() && |
| 6810 | RISCVValidateMachineOperand(MI.getOperand(0), &STI, 33 /* uimm5slist */)) { |
| 6811 | // qc.c.syncwf $slist |
| 6812 | // Operand: slist |
| 6813 | return true; |
| 6814 | } // if |
| 6815 | break; |
| 6816 | } // case QC_SYNCWF |
| 6817 | case RISCV::QC_SYNCWL: { |
| 6818 | if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] && |
| 6819 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6820 | MI.getOperand(0).isImm() && |
| 6821 | RISCVValidateMachineOperand(MI.getOperand(0), &STI, 33 /* uimm5slist */)) { |
| 6822 | // qc.c.syncwl $slist |
| 6823 | // Operand: slist |
| 6824 | return true; |
| 6825 | } // if |
| 6826 | break; |
| 6827 | } // case QC_SYNCWL |
| 6828 | case RISCV::SB: { |
| 6829 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6830 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6831 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6832 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6833 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6834 | MI.getOperand(2).isImm() && |
| 6835 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 16 /* uimm2 */) && |
| 6836 | MI.getOperand(2).isImm() && |
| 6837 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 17 /* uimm2_optional */)) { |
| 6838 | // c.sb $rs2, ${imm}(${rs1}) |
| 6839 | // Operand: rs2 |
| 6840 | // Operand: rs1 |
| 6841 | // Operand: imm |
| 6842 | return true; |
| 6843 | } // if |
| 6844 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 6845 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6846 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6847 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6848 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6849 | MI.getOperand(2).isImm() && |
| 6850 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 18 /* uimm5 */)) { |
| 6851 | // qk.c.sb $rs2, ${imm}(${rs1}) |
| 6852 | // Operand: rs2 |
| 6853 | // Operand: rs1 |
| 6854 | // Operand: imm |
| 6855 | return true; |
| 6856 | } // if |
| 6857 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 6858 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6859 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6860 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6861 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6862 | MI.getOperand(2).isImm() && |
| 6863 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 19 /* uimm4 */)) { |
| 6864 | // qk.c.sbsp $rd_rs2, ${imm}(${rs1}) |
| 6865 | // Operand: rd_rs2 |
| 6866 | // Operand: rs1 |
| 6867 | // Operand: imm |
| 6868 | return true; |
| 6869 | } // if |
| 6870 | break; |
| 6871 | } // case SB |
| 6872 | case RISCV::SD: { |
| 6873 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6874 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6875 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6876 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6877 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6878 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6879 | MI.getOperand(2).isImm() && |
| 6880 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7 /* uimm8_lsb000 */) && |
| 6881 | MI.getOperand(2).isImm() && |
| 6882 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8 /* uimm8_lsb000_optional */)) { |
| 6883 | // c.sd $rs2, ${imm}(${rs1}) |
| 6884 | // Operand: rs2 |
| 6885 | // Operand: rs1 |
| 6886 | // Operand: imm |
| 6887 | return true; |
| 6888 | } // if |
| 6889 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6890 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 6891 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6892 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6893 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6894 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6895 | MI.getOperand(2).isImm() && |
| 6896 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9 /* uimm9_lsb000 */) && |
| 6897 | MI.getOperand(2).isImm() && |
| 6898 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 10 /* uimm9_lsb000_optional */)) { |
| 6899 | // c.sdsp $rs2, ${imm}(${rs1}) |
| 6900 | // Operand: rs2 |
| 6901 | // Operand: rs1 |
| 6902 | // Operand: imm |
| 6903 | return true; |
| 6904 | } // if |
| 6905 | break; |
| 6906 | } // case SD |
| 6907 | case RISCV::SD_RV32: { |
| 6908 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 6909 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6910 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6911 | getRISCVMCRegisterClass(RISCV::GPRPairRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6912 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6913 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6914 | MI.getOperand(2).isImm() && |
| 6915 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9 /* uimm9_lsb000 */) && |
| 6916 | MI.getOperand(2).isImm() && |
| 6917 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 10 /* uimm9_lsb000_optional */)) { |
| 6918 | // c.sdsp $rs2, ${imm}(${rs1}) |
| 6919 | // Operand: rs2 |
| 6920 | // Operand: rs1 |
| 6921 | // Operand: imm |
| 6922 | return true; |
| 6923 | } // if |
| 6924 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] && |
| 6925 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 6926 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6927 | getRISCVMCRegisterClass(RISCV::GPRPairCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6928 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6929 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6930 | MI.getOperand(2).isImm() && |
| 6931 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7 /* uimm8_lsb000 */) && |
| 6932 | MI.getOperand(2).isImm() && |
| 6933 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8 /* uimm8_lsb000_optional */)) { |
| 6934 | // c.sd $rs2, ${imm}(${rs1}) |
| 6935 | // Operand: rs2 |
| 6936 | // Operand: rs1 |
| 6937 | // Operand: imm |
| 6938 | return true; |
| 6939 | } // if |
| 6940 | break; |
| 6941 | } // case SD_RV32 |
| 6942 | case RISCV::SEXT_B: { |
| 6943 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 6944 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6945 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 6946 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 6947 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6948 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 6949 | // c.sext.b $rd |
| 6950 | // Operand: rd_wb |
| 6951 | // Operand: rd |
| 6952 | return true; |
| 6953 | } // if |
| 6954 | break; |
| 6955 | } // case SEXT_B |
| 6956 | case RISCV::SEXT_H: { |
| 6957 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 6958 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6959 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 6960 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 6961 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6962 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 6963 | // c.sext.h $rd |
| 6964 | // Operand: rd_wb |
| 6965 | // Operand: rd |
| 6966 | return true; |
| 6967 | } // if |
| 6968 | break; |
| 6969 | } // case SEXT_H |
| 6970 | case RISCV::SH: { |
| 6971 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 6972 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6973 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6974 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6975 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6976 | MI.getOperand(2).isImm() && |
| 6977 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 20 /* uimm2_lsb0 */) && |
| 6978 | MI.getOperand(2).isImm() && |
| 6979 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 21 /* uimm2_lsb0_optional */)) { |
| 6980 | // c.sh $rs2, ${imm}(${rs1}) |
| 6981 | // Operand: rs2 |
| 6982 | // Operand: rs1 |
| 6983 | // Operand: imm |
| 6984 | return true; |
| 6985 | } // if |
| 6986 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 6987 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 6988 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 6989 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 6990 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 6991 | MI.getOperand(2).isImm() && |
| 6992 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 22 /* uimm6_lsb0 */)) { |
| 6993 | // qk.c.sh $rs2, ${imm}(${rs1}) |
| 6994 | // Operand: rs2 |
| 6995 | // Operand: rs1 |
| 6996 | // Operand: imm |
| 6997 | return true; |
| 6998 | } // if |
| 6999 | if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] && |
| 7000 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 7001 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 7002 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7003 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7004 | MI.getOperand(2).isImm() && |
| 7005 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 23 /* uimm5_lsb0 */)) { |
| 7006 | // qk.c.shsp $rd_rs2, ${imm}(${rs1}) |
| 7007 | // Operand: rd_rs2 |
| 7008 | // Operand: rs1 |
| 7009 | // Operand: imm |
| 7010 | return true; |
| 7011 | } // if |
| 7012 | break; |
| 7013 | } // case SH |
| 7014 | case RISCV::SH1ADD: { |
| 7015 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 7016 | STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 7017 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 7018 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 7019 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 7020 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 7021 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 7022 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7023 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7024 | RISCVValidateMachineOperand(MachineOperand::CreateImm(2), &STI, 18 /* uimm5 */)) { |
| 7025 | // qc.c.muliadd $rd, $rs1, $uimm |
| 7026 | // Operand: rd_wb |
| 7027 | // Operand: rd |
| 7028 | // Operand: rs1 |
| 7029 | // Operand: uimm |
| 7030 | return true; |
| 7031 | } // if |
| 7032 | break; |
| 7033 | } // case SH1ADD |
| 7034 | case RISCV::SH2ADD: { |
| 7035 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 7036 | STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 7037 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 7038 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 7039 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 7040 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 7041 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 7042 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7043 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7044 | RISCVValidateMachineOperand(MachineOperand::CreateImm(4), &STI, 18 /* uimm5 */)) { |
| 7045 | // qc.c.muliadd $rd, $rs1, $uimm |
| 7046 | // Operand: rd_wb |
| 7047 | // Operand: rd |
| 7048 | // Operand: rs1 |
| 7049 | // Operand: uimm |
| 7050 | return true; |
| 7051 | } // if |
| 7052 | break; |
| 7053 | } // case SH2ADD |
| 7054 | case RISCV::SH3ADD: { |
| 7055 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZba] && |
| 7056 | STI.getFeatureBits()[RISCV::FeatureVendorXqciac] && |
| 7057 | !STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 7058 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 7059 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 7060 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 7061 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 7062 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7063 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7064 | RISCVValidateMachineOperand(MachineOperand::CreateImm(8), &STI, 18 /* uimm5 */)) { |
| 7065 | // qc.c.muliadd $rd, $rs1, $uimm |
| 7066 | // Operand: rd_wb |
| 7067 | // Operand: rd |
| 7068 | // Operand: rs1 |
| 7069 | // Operand: uimm |
| 7070 | return true; |
| 7071 | } // if |
| 7072 | break; |
| 7073 | } // case SH3ADD |
| 7074 | case RISCV::SH_INX: { |
| 7075 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 7076 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 7077 | getRISCVMCRegisterClass(RISCV::GPRF16CRegClassID).contains(MI.getOperand(0).getReg()) && |
| 7078 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7079 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7080 | MI.getOperand(2).isImm() && |
| 7081 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 20 /* uimm2_lsb0 */) && |
| 7082 | MI.getOperand(2).isImm() && |
| 7083 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 21 /* uimm2_lsb0_optional */)) { |
| 7084 | // c.sh $rs2, ${imm}(${rs1}) |
| 7085 | // Operand: rs2 |
| 7086 | // Operand: rs1 |
| 7087 | // Operand: imm |
| 7088 | return true; |
| 7089 | } // if |
| 7090 | break; |
| 7091 | } // case SH_INX |
| 7092 | case RISCV::SLLI: { |
| 7093 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7094 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7095 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7096 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7097 | getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()) && |
| 7098 | MI.getOperand(2).isImm() && |
| 7099 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6 /* uimmlog2xlennonzero */) && |
| 7100 | MI.getOperand(2).isImm() && |
| 7101 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 34 /* uimmlog2xlen */)) { |
| 7102 | // c.slli $rd, $imm |
| 7103 | // Operand: rd_wb |
| 7104 | // Operand: rd |
| 7105 | // Operand: imm |
| 7106 | return true; |
| 7107 | } // if |
| 7108 | break; |
| 7109 | } // case SLLI |
| 7110 | case RISCV::SRAI: { |
| 7111 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7112 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7113 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7114 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7115 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7116 | MI.getOperand(2).isImm() && |
| 7117 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6 /* uimmlog2xlennonzero */) && |
| 7118 | MI.getOperand(2).isImm() && |
| 7119 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 34 /* uimmlog2xlen */)) { |
| 7120 | // c.srai $rs1, $imm |
| 7121 | // Operand: rd |
| 7122 | // Operand: rs1 |
| 7123 | // Operand: imm |
| 7124 | return true; |
| 7125 | } // if |
| 7126 | break; |
| 7127 | } // case SRAI |
| 7128 | case RISCV::SRLI: { |
| 7129 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7130 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7131 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7132 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7133 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7134 | MI.getOperand(2).isImm() && |
| 7135 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6 /* uimmlog2xlennonzero */) && |
| 7136 | MI.getOperand(2).isImm() && |
| 7137 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 34 /* uimmlog2xlen */)) { |
| 7138 | // c.srli $rs1, $imm |
| 7139 | // Operand: rd |
| 7140 | // Operand: rs1 |
| 7141 | // Operand: imm |
| 7142 | return true; |
| 7143 | } // if |
| 7144 | break; |
| 7145 | } // case SRLI |
| 7146 | case RISCV::SSPOPCHK: { |
| 7147 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] && |
| 7148 | MI.getOperand(0).isReg() && |
| 7149 | (MI.getOperand(0).getReg() == RISCV::X5)) { |
| 7150 | // c.sspopchk $rs1 |
| 7151 | // Operand: rs1 |
| 7152 | return true; |
| 7153 | } // if |
| 7154 | break; |
| 7155 | } // case SSPOPCHK |
| 7156 | case RISCV::SSPUSH: { |
| 7157 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] && |
| 7158 | MI.getOperand(0).isReg() && |
| 7159 | (MI.getOperand(0).getReg() == RISCV::X1)) { |
| 7160 | // c.sspush $rs1 |
| 7161 | // Operand: rs1 |
| 7162 | return true; |
| 7163 | } // if |
| 7164 | break; |
| 7165 | } // case SSPUSH |
| 7166 | case RISCV::SUB: { |
| 7167 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7168 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7169 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7170 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7171 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7172 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 7173 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) { |
| 7174 | // c.sub $rd, $rs2 |
| 7175 | // Operand: rd_wb |
| 7176 | // Operand: rd |
| 7177 | // Operand: rs2 |
| 7178 | return true; |
| 7179 | } // if |
| 7180 | break; |
| 7181 | } // case SUB |
| 7182 | case RISCV::SUBW: { |
| 7183 | if (STI.getFeatureBits()[RISCV::Feature64Bit] && |
| 7184 | STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7185 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7186 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7187 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7188 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7189 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 7190 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) { |
| 7191 | // c.subw $rd, $rs2 |
| 7192 | // Operand: rd_wb |
| 7193 | // Operand: rd |
| 7194 | // Operand: rs2 |
| 7195 | return true; |
| 7196 | } // if |
| 7197 | break; |
| 7198 | } // case SUBW |
| 7199 | case RISCV::SW: { |
| 7200 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7201 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 7202 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg()) && |
| 7203 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7204 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7205 | MI.getOperand(2).isImm() && |
| 7206 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11 /* uimm7_lsb00 */) && |
| 7207 | MI.getOperand(2).isImm() && |
| 7208 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12 /* uimm7_lsb00_optional */)) { |
| 7209 | // c.sw $rs2, ${imm}(${rs1}) |
| 7210 | // Operand: rs2 |
| 7211 | // Operand: rs1 |
| 7212 | // Operand: imm |
| 7213 | return true; |
| 7214 | } // if |
| 7215 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7216 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 7217 | getRISCVMCRegisterClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()) && |
| 7218 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7219 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7220 | MI.getOperand(2).isImm() && |
| 7221 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13 /* uimm8_lsb00 */) && |
| 7222 | MI.getOperand(2).isImm() && |
| 7223 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14 /* uimm8_lsb00_optional */)) { |
| 7224 | // c.swsp $rs2, ${imm}(${rs1}) |
| 7225 | // Operand: rs2 |
| 7226 | // Operand: rs1 |
| 7227 | // Operand: imm |
| 7228 | return true; |
| 7229 | } // if |
| 7230 | break; |
| 7231 | } // case SW |
| 7232 | case RISCV::SW_INX: { |
| 7233 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7234 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 7235 | getRISCVMCRegisterClass(RISCV::GPRF32RegClassID).contains(MI.getOperand(0).getReg()) && |
| 7236 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7237 | getRISCVMCRegisterClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7238 | MI.getOperand(2).isImm() && |
| 7239 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13 /* uimm8_lsb00 */) && |
| 7240 | MI.getOperand(2).isImm() && |
| 7241 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14 /* uimm8_lsb00_optional */)) { |
| 7242 | // c.swsp $rs2, ${imm}(${rs1}) |
| 7243 | // Operand: rs2 |
| 7244 | // Operand: rs1 |
| 7245 | // Operand: imm |
| 7246 | return true; |
| 7247 | } // if |
| 7248 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7249 | MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() && |
| 7250 | getRISCVMCRegisterClass(RISCV::GPRF32CRegClassID).contains(MI.getOperand(0).getReg()) && |
| 7251 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7252 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7253 | MI.getOperand(2).isImm() && |
| 7254 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11 /* uimm7_lsb00 */) && |
| 7255 | MI.getOperand(2).isImm() && |
| 7256 | RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12 /* uimm7_lsb00_optional */)) { |
| 7257 | // c.sw $rs2, ${imm}(${rs1}) |
| 7258 | // Operand: rs2 |
| 7259 | // Operand: rs1 |
| 7260 | // Operand: imm |
| 7261 | return true; |
| 7262 | } // if |
| 7263 | break; |
| 7264 | } // case SW_INX |
| 7265 | case RISCV::UNIMP: { |
| 7266 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca]) { |
| 7267 | // c.unimp |
| 7268 | return true; |
| 7269 | } // if |
| 7270 | break; |
| 7271 | } // case UNIMP |
| 7272 | case RISCV::XOR: { |
| 7273 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7274 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7275 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7276 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7277 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()) && |
| 7278 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 7279 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) { |
| 7280 | // c.xor $rd, $rs2 |
| 7281 | // Operand: rd_wb |
| 7282 | // Operand: rd |
| 7283 | // Operand: rs2 |
| 7284 | return true; |
| 7285 | } // if |
| 7286 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZca] && |
| 7287 | MI.getOperand(2).isReg() && MI.getOperand(0).isReg() && |
| 7288 | (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && |
| 7289 | MI.getOperand(2).isReg() && MI.getOperand(2).getReg().isPhysical() && |
| 7290 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()) && |
| 7291 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7292 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 7293 | // c.xor $rd, $rs2 |
| 7294 | // Operand: rd_wb |
| 7295 | // Operand: rd |
| 7296 | // Operand: rs2 |
| 7297 | return true; |
| 7298 | } // if |
| 7299 | break; |
| 7300 | } // case XOR |
| 7301 | case RISCV::XORI: { |
| 7302 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 7303 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7304 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7305 | MI.getOperand(2).isImm() && |
| 7306 | (MI.getOperand(2).getImm() == -1) && |
| 7307 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7308 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 7309 | // c.not $rd |
| 7310 | // Operand: rd_wb |
| 7311 | // Operand: rd |
| 7312 | return true; |
| 7313 | } // if |
| 7314 | break; |
| 7315 | } // case XORI |
| 7316 | case RISCV::ZEXT_H_RV32: { |
| 7317 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 7318 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 7319 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7320 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7321 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7322 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 7323 | // c.zext.h $rd |
| 7324 | // Operand: rd_wb |
| 7325 | // Operand: rd |
| 7326 | return true; |
| 7327 | } // if |
| 7328 | break; |
| 7329 | } // case ZEXT_H_RV32 |
| 7330 | case RISCV::ZEXT_H_RV64: { |
| 7331 | if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] && |
| 7332 | STI.getFeatureBits()[RISCV::FeatureStdExtZcb] && |
| 7333 | MI.getOperand(1).isReg() && MI.getOperand(0).isReg() && |
| 7334 | (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && |
| 7335 | MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && |
| 7336 | getRISCVMCRegisterClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) { |
| 7337 | // c.zext.h $rd |
| 7338 | // Operand: rd_wb |
| 7339 | // Operand: rd |
| 7340 | return true; |
| 7341 | } // if |
| 7342 | break; |
| 7343 | } // case ZEXT_H_RV64 |
| 7344 | } // switch |
| 7345 | return false; |
| 7346 | } |
| 7347 | |
| 7348 | #endif // GEN_CHECK_COMPRESS_INSTR |
| 7349 | |
| 7350 |
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