1//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVBaseInfo.h"
15#include "RISCVInstrInfo.h"
16#include "llvm/MC/MCInst.h"
17#include "llvm/MC/MCRegisterInfo.h"
18#include "llvm/MC/MCSubtargetInfo.h"
19#include "llvm/Support/raw_ostream.h"
20#include "llvm/TargetParser/TargetParser.h"
21#include "llvm/TargetParser/Triple.h"
22
23namespace llvm {
24
25extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
26
27namespace RISCVSysReg {
28#define GET_SysRegsList_IMPL
29#include "RISCVGenSearchableTables.inc"
30} // namespace RISCVSysReg
31
32namespace RISCVInsnOpcode {
33#define GET_RISCVOpcodesList_IMPL
34#include "RISCVGenSearchableTables.inc"
35} // namespace RISCVInsnOpcode
36
37namespace RISCVVInversePseudosTable {
38using namespace RISCV;
39#define GET_RISCVVInversePseudosTable_IMPL
40#include "RISCVGenSearchableTables.inc"
41} // namespace RISCVVInversePseudosTable
42
43namespace RISCV {
44#define GET_RISCVVSSEGTable_IMPL
45#define GET_RISCVVLSEGTable_IMPL
46#define GET_RISCVVLXSEGTable_IMPL
47#define GET_RISCVVSXSEGTable_IMPL
48#define GET_RISCVVLETable_IMPL
49#define GET_RISCVVSETable_IMPL
50#define GET_RISCVVLXTable_IMPL
51#define GET_RISCVVSXTable_IMPL
52#define GET_RISCVNDSVLNTable_IMPL
53#include "RISCVGenSearchableTables.inc"
54} // namespace RISCV
55
56namespace RISCVABI {
57ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
58 StringRef ABIName) {
59 auto TargetABI = getTargetABI(ABIName);
60 bool IsRV64 = TT.isArch64Bit();
61 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE];
62
63 if (!ABIName.empty() && TargetABI == ABI_Unknown) {
64 errs()
65 << "'" << ABIName
66 << "' is not a recognized ABI for this target (ignoring target-abi)\n";
67 } else if (ABIName.starts_with(Prefix: "ilp32") && IsRV64) {
68 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
69 "target-abi)\n";
70 TargetABI = ABI_Unknown;
71 } else if (ABIName.starts_with(Prefix: "lp64") && !IsRV64) {
72 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
73 "target-abi)\n";
74 TargetABI = ABI_Unknown;
75 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&
76 TargetABI != ABI_Unknown) {
77 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
78 errs()
79 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
80 TargetABI = ABI_Unknown;
81 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
82 TargetABI != ABI_Unknown) {
83 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
84 errs()
85 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
86 TargetABI = ABI_Unknown;
87 }
88
89 if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
90 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
91 FeatureBits[RISCV::FeatureStdExtD])
92 reportFatalUsageError(reason: "ILP32E cannot be used with the D ISA extension");
93
94 if (TargetABI != ABI_Unknown)
95 return TargetABI;
96
97 // If no explicit ABI is given, try to compute the default ABI.
98 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
99 if (!ISAInfo)
100 reportFatalUsageError(Err: ISAInfo.takeError());
101 return getTargetABI(ABIName: (*ISAInfo)->computeDefaultABI());
102}
103
104ABI getTargetABI(StringRef ABIName) {
105 auto TargetABI = StringSwitch<ABI>(ABIName)
106 .Case(S: "ilp32", Value: ABI_ILP32)
107 .Case(S: "ilp32f", Value: ABI_ILP32F)
108 .Case(S: "ilp32d", Value: ABI_ILP32D)
109 .Case(S: "ilp32e", Value: ABI_ILP32E)
110 .Case(S: "lp64", Value: ABI_LP64)
111 .Case(S: "lp64f", Value: ABI_LP64F)
112 .Case(S: "lp64d", Value: ABI_LP64D)
113 .Case(S: "lp64e", Value: ABI_LP64E)
114 .Default(Value: ABI_Unknown);
115 return TargetABI;
116}
117
118// To avoid the BP value clobbered by a function call, we need to choose a
119// callee saved register to save the value. RV32E only has X8 and X9 as callee
120// saved registers and X8 will be used as fp. So we choose X9 as bp.
121MCRegister getBPReg() { return RISCV::X9; }
122
123// Returns the register holding shadow call stack pointer.
124MCRegister getSCSPReg() { return RISCV::X3; }
125
126} // namespace RISCVABI
127
128namespace RISCVFeatures {
129
130void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
131 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
132 reportFatalUsageError(reason: "RV64 target requires an RV64 CPU");
133 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
134 reportFatalUsageError(reason: "RV32 target requires an RV32 CPU");
135 if (FeatureBits[RISCV::Feature32Bit] &&
136 FeatureBits[RISCV::Feature64Bit])
137 reportFatalUsageError(reason: "RV32 and RV64 can't be combined");
138}
139
140llvm::Expected<std::unique_ptr<RISCVISAInfo>>
141parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
142 unsigned XLen = IsRV64 ? 64 : 32;
143 std::vector<std::string> FeatureVector;
144 // Convert FeatureBitset to FeatureVector.
145 for (auto Feature : RISCVFeatureKV) {
146 if (FeatureBits[Feature.Value] &&
147 llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext: Feature.Key))
148 FeatureVector.push_back(x: std::string("+") + Feature.Key);
149 }
150 return llvm::RISCVISAInfo::parseFeatures(XLen, Features: FeatureVector);
151}
152
153} // namespace RISCVFeatures
154
155// Include the auto-generated portion of the compress emitter.
156#define GEN_UNCOMPRESS_INSTR
157#define GEN_COMPRESS_INSTR
158#include "RISCVGenCompressInstEmitter.inc"
159
160bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
161 const MCSubtargetInfo &STI) {
162 return compressInst(OutInst, MI, STI);
163}
164
165bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
166 const MCSubtargetInfo &STI) {
167 return uncompressInst(OutInst, MI, STI);
168}
169
170// Lookup table for fli.s for entries 2-31.
171static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
172 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
173 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
174 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
175 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
176 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
177 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
178 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
179 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
180 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
181 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
182};
183
184int RISCVLoadFPImm::getLoadFPImm(APFloat FPImm) {
185 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
186 &FPImm.getSemantics() == &APFloat::IEEEdouble() ||
187 &FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
188 "Unexpected semantics");
189
190 // Handle the minimum normalized value which is different for each type.
191 if (FPImm.isSmallestNormalized() && !FPImm.isNegative())
192 return 1;
193
194 // Convert to single precision to use its lookup table.
195 bool LosesInfo;
196 APFloat::opStatus Status = FPImm.convert(
197 ToSemantics: APFloat::IEEEsingle(), RM: APFloat::rmNearestTiesToEven, losesInfo: &LosesInfo);
198 if (Status != APFloat::opOK || LosesInfo)
199 return -1;
200
201 APInt Imm = FPImm.bitcastToAPInt();
202
203 if (Imm.extractBitsAsZExtValue(numBits: 21, bitPosition: 0) != 0)
204 return -1;
205
206 bool Sign = Imm.extractBitsAsZExtValue(numBits: 1, bitPosition: 31);
207 uint8_t Mantissa = Imm.extractBitsAsZExtValue(numBits: 2, bitPosition: 21);
208 uint8_t Exp = Imm.extractBitsAsZExtValue(numBits: 8, bitPosition: 23);
209
210 auto EMI = llvm::lower_bound(Range: LoadFP32ImmArr, Value: std::make_pair(x&: Exp, y&: Mantissa));
211 if (EMI == std::end(arr: LoadFP32ImmArr) || EMI->first != Exp ||
212 EMI->second != Mantissa)
213 return -1;
214
215 // Table doesn't have entry 0 or 1.
216 int Entry = std::distance(first: std::begin(arr: LoadFP32ImmArr), last: EMI) + 2;
217
218 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
219 if (Sign) {
220 if (Entry == 16)
221 return 0;
222 return -1;
223 }
224
225 return Entry;
226}
227
228float RISCVLoadFPImm::getFPImm(unsigned Imm) {
229 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
230
231 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
232 uint32_t Sign = 0;
233 if (Imm == 0) {
234 Sign = 0b1;
235 Imm = 16;
236 }
237
238 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
239 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
240
241 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
242 return bit_cast<float>(from: I);
243}
244
245void RISCVZC::printRegList(unsigned RlistEncode, raw_ostream &OS) {
246 assert(RlistEncode >= RLISTENCODE::RA &&
247 RlistEncode <= RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
248 OS << "{ra";
249 if (RlistEncode > RISCVZC::RA) {
250 OS << ", s0";
251 if (RlistEncode == RISCVZC::RA_S0_S11)
252 OS << "-s11";
253 else if (RlistEncode > RISCVZC::RA_S0 && RlistEncode <= RISCVZC::RA_S0_S11)
254 OS << "-s" << (RlistEncode - RISCVZC::RA_S0);
255 }
256 OS << "}";
257}
258
259} // namespace llvm
260