1//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVBaseInfo.h"
15#include "RISCVInstrInfo.h"
16#include "RISCVMCAsmInfo.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCRegisterInfo.h"
19#include "llvm/MC/MCSubtargetInfo.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/TargetParser/TargetParser.h"
22#include "llvm/TargetParser/Triple.h"
23
24namespace llvm {
25
26namespace RISCVSysReg {
27#define GET_SysRegsList_IMPL
28#include "RISCVGenSearchableTables.inc"
29} // namespace RISCVSysReg
30
31namespace RISCVInsnOpcode {
32#define GET_RISCVOpcodesList_IMPL
33#include "RISCVGenSearchableTables.inc"
34} // namespace RISCVInsnOpcode
35
36namespace RISCVVInversePseudosTable {
37using namespace RISCV;
38#define GET_RISCVVInversePseudosTable_IMPL
39#include "RISCVGenSearchableTables.inc"
40} // namespace RISCVVInversePseudosTable
41
42namespace RISCV {
43#define GET_RISCVVSSEGTable_IMPL
44#define GET_RISCVVLSEGTable_IMPL
45#define GET_RISCVVLXSEGTable_IMPL
46#define GET_RISCVVSXSEGTable_IMPL
47#define GET_RISCVVLETable_IMPL
48#define GET_RISCVVSETable_IMPL
49#define GET_RISCVVLXTable_IMPL
50#define GET_RISCVVSXTable_IMPL
51#define GET_RISCVNDSVLNTable_IMPL
52#include "RISCVGenSearchableTables.inc"
53} // namespace RISCV
54
55namespace RISCVABI {
56ABI computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName) {
57 const Triple &TT = STI.getTargetTriple();
58 const FeatureBitset &FeatureBits = STI.getFeatureBits();
59 auto TargetABI = getTargetABI(ABIName);
60 bool IsRV64 = TT.isArch64Bit();
61 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE];
62 bool IsXCheriot = FeatureBits[RISCV::FeatureVendorXCheriot];
63
64 if (!ABIName.empty() && TargetABI == ABI_Unknown) {
65 errs()
66 << "'" << ABIName
67 << "' is not a recognized ABI for this target (ignoring target-abi)\n";
68 } else if (ABIName.starts_with(Prefix: "ilp32") && IsRV64) {
69 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
70 "target-abi)\n";
71 TargetABI = ABI_Unknown;
72 } else if (ABIName.starts_with(Prefix: "lp64") && !IsRV64) {
73 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
74 "target-abi)\n";
75 TargetABI = ABI_Unknown;
76 } else if (!IsRV64 && IsRVE && !IsXCheriot && TargetABI != ABI_ILP32E &&
77 TargetABI != ABI_Unknown) {
78 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
79 errs()
80 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
81 TargetABI = ABI_Unknown;
82 } else if (!IsRV64 && IsRVE && IsXCheriot && TargetABI != ABI_CHERIOT &&
83 TargetABI != ABI_Unknown) {
84 errs() << "Only the cheriot ABI is supported for XCheriot (ignoring "
85 "target-abi)\n";
86 TargetABI = ABI_Unknown;
87 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
88 TargetABI != ABI_Unknown) {
89 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
90 errs()
91 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
92 TargetABI = ABI_Unknown;
93 }
94
95 if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
96 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
97 FeatureBits[RISCV::FeatureStdExtD])
98 reportFatalUsageError(reason: "ILP32E cannot be used with the D ISA extension");
99
100 if (TargetABI != ABI_Unknown)
101 return TargetABI;
102
103 // If no explicit ABI is given, try to compute the default ABI.
104 auto ISAInfo = RISCVFeatures::parseFeatureBits(STI);
105 if (!ISAInfo)
106 reportFatalUsageError(Err: ISAInfo.takeError());
107 return getTargetABI(ABIName: (*ISAInfo)->computeDefaultABI());
108}
109
110ABI getTargetABI(StringRef ABIName) {
111 auto TargetABI = StringSwitch<ABI>(ABIName)
112 .Case(S: "ilp32", Value: ABI_ILP32)
113 .Case(S: "ilp32f", Value: ABI_ILP32F)
114 .Case(S: "ilp32d", Value: ABI_ILP32D)
115 .Case(S: "ilp32e", Value: ABI_ILP32E)
116 .Case(S: "il32pc64", Value: ABI_IL32PC64)
117 .Case(S: "il32pc64f", Value: ABI_IL32PC64F)
118 .Case(S: "il32pc64d", Value: ABI_IL32PC64D)
119 .Case(S: "il32pc64e", Value: ABI_IL32PC64E)
120 .Case(S: "lp64", Value: ABI_LP64)
121 .Case(S: "lp64f", Value: ABI_LP64F)
122 .Case(S: "lp64d", Value: ABI_LP64D)
123 .Case(S: "lp64e", Value: ABI_LP64E)
124 .Case(S: "l64pc128", Value: ABI_L64PC128)
125 .Case(S: "l64pc128f", Value: ABI_L64PC128F)
126 .Case(S: "l64pc128d", Value: ABI_L64PC128D)
127 .Case(S: "cheriot", Value: ABI_CHERIOT)
128 .Default(Value: ABI_Unknown);
129 return TargetABI;
130}
131
132// To avoid the BP value clobbered by a function call, we need to choose a
133// callee saved register to save the value. RV32E only has X8 and X9 as callee
134// saved registers and X8 will be used as fp. So we choose X9 as bp.
135MCRegister getBPReg() { return RISCV::X9; }
136
137// Returns the register holding shadow call stack pointer.
138MCRegister getSCSPReg() { return RISCV::X3; }
139
140} // namespace RISCVABI
141
142namespace RISCVFeatures {
143
144void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
145 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
146 reportFatalUsageError(reason: "RV64 target requires an RV64 CPU");
147 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
148 reportFatalUsageError(reason: "RV32 target requires an RV32 CPU");
149 if (FeatureBits[RISCV::Feature32Bit] &&
150 FeatureBits[RISCV::Feature64Bit])
151 reportFatalUsageError(reason: "RV32 and RV64 can't be combined");
152}
153
154llvm::Expected<std::unique_ptr<RISCVISAInfo>>
155parseFeatureBits(const MCSubtargetInfo &STI) {
156 const FeatureBitset &FeatureBits = STI.getFeatureBits();
157 unsigned XLen = FeatureBits[RISCV::Feature64Bit] ? 64 : 32;
158 std::vector<std::string> FeatureVector;
159 // Convert FeatureBitset to FeatureVector.
160 for (const auto &Feature : STI.getAllProcessorFeatures()) {
161 if (FeatureBits[Feature.Value] &&
162 llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext: Feature.key()))
163 FeatureVector.push_back(x: std::string("+") + Feature.key());
164 }
165 return llvm::RISCVISAInfo::parseFeatures(XLen, Features: FeatureVector);
166}
167
168} // namespace RISCVFeatures
169
170// Include the auto-generated portion of the compress emitter.
171#define GEN_UNCOMPRESS_INSTR
172#define GEN_COMPRESS_INSTR
173#include "RISCVGenCompressInstEmitter.inc"
174
175bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
176 const MCSubtargetInfo &STI) {
177 return compressInst(OutInst, MI, STI);
178}
179
180bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
181 const MCSubtargetInfo &STI) {
182 return uncompressInst(OutInst, MI, STI);
183}
184
185// Lookup table for fli.s for entries 2-31.
186static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
187 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
188 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
189 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
190 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
191 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
192 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
193 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
194 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
195 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
196 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
197};
198
199int RISCVLoadFPImm::getLoadFPImm(APFloat FPImm) {
200 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
201 &FPImm.getSemantics() == &APFloat::IEEEdouble() ||
202 &FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
203 "Unexpected semantics");
204
205 // Handle the minimum normalized value which is different for each type.
206 if (FPImm.isSmallestNormalized() && !FPImm.isNegative())
207 return 1;
208
209 // Convert to single precision to use its lookup table.
210 bool LosesInfo;
211 APFloat::opStatus Status = FPImm.convert(
212 ToSemantics: APFloat::IEEEsingle(), RM: APFloat::rmNearestTiesToEven, losesInfo: &LosesInfo);
213 if (Status != APFloat::opOK || LosesInfo)
214 return -1;
215
216 APInt Imm = FPImm.bitcastToAPInt();
217
218 if (Imm.extractBitsAsZExtValue(numBits: 21, bitPosition: 0) != 0)
219 return -1;
220
221 bool Sign = Imm.extractBitsAsZExtValue(numBits: 1, bitPosition: 31);
222 uint8_t Mantissa = Imm.extractBitsAsZExtValue(numBits: 2, bitPosition: 21);
223 uint8_t Exp = Imm.extractBitsAsZExtValue(numBits: 8, bitPosition: 23);
224
225 auto EMI = llvm::lower_bound(Range: LoadFP32ImmArr, Value: std::make_pair(x&: Exp, y&: Mantissa));
226 if (EMI == std::end(arr: LoadFP32ImmArr) || EMI->first != Exp ||
227 EMI->second != Mantissa)
228 return -1;
229
230 // Table doesn't have entry 0 or 1.
231 int Entry = std::distance(first: std::begin(arr: LoadFP32ImmArr), last: EMI) + 2;
232
233 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
234 if (Sign) {
235 if (Entry == 16)
236 return 0;
237 return -1;
238 }
239
240 return Entry;
241}
242
243float RISCVLoadFPImm::getFPImm(unsigned Imm) {
244 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
245
246 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
247 uint32_t Sign = 0;
248 if (Imm == 0) {
249 Sign = 0b1;
250 Imm = 16;
251 }
252
253 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
254 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
255
256 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
257 return bit_cast<float>(from: I);
258}
259
260void RISCVZC::printRegList(unsigned RlistEncode, raw_ostream &OS) {
261 assert(RlistEncode >= RLISTENCODE::RA &&
262 RlistEncode <= RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
263 OS << "{ra";
264 if (RlistEncode > RISCVZC::RA) {
265 OS << ", s0";
266 if (RlistEncode == RISCVZC::RA_S0_S11)
267 OS << "-s11";
268 else if (RlistEncode > RISCVZC::RA_S0 && RlistEncode <= RISCVZC::RA_S0_S11)
269 OS << "-s" << (RlistEncode - RISCVZC::RA_S0);
270 }
271 OS << "}";
272}
273
274} // namespace llvm
275