1//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVBaseInfo.h"
15#include "RISCVMCAsmInfo.h"
16#include "llvm/MC/MCInst.h"
17#include "llvm/MC/MCRegisterInfo.h"
18#include "llvm/MC/MCSubtargetInfo.h"
19#include "llvm/Support/raw_ostream.h"
20#include "llvm/TargetParser/Triple.h"
21
22namespace llvm {
23
24namespace RISCVSysReg {
25#define GET_SysRegsList_IMPL
26#include "RISCVGenSearchableTables.inc"
27} // namespace RISCVSysReg
28
29namespace RISCVInsnOpcode {
30#define GET_RISCVOpcodesList_IMPL
31#include "RISCVGenSearchableTables.inc"
32} // namespace RISCVInsnOpcode
33
34namespace RISCVVInversePseudosTable {
35using namespace RISCV;
36#define GET_RISCVVInversePseudosTable_IMPL
37#include "RISCVGenSearchableTables.inc"
38} // namespace RISCVVInversePseudosTable
39
40namespace RISCV {
41#define GET_RISCVVSSEGTable_IMPL
42#define GET_RISCVVLSEGTable_IMPL
43#define GET_RISCVVLXSEGTable_IMPL
44#define GET_RISCVVSXSEGTable_IMPL
45#define GET_RISCVVLETable_IMPL
46#define GET_RISCVVSETable_IMPL
47#define GET_RISCVVLXTable_IMPL
48#define GET_RISCVVSXTable_IMPL
49#define GET_RISCVNDSVLNTable_IMPL
50#include "RISCVGenSearchableTables.inc"
51} // namespace RISCV
52
53namespace RISCVABI {
54Expected<ABI> computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName) {
55 const Triple &TT = STI.getTargetTriple();
56 const FeatureBitset &FeatureBits = STI.getFeatureBits();
57 auto TargetABI = getTargetABI(ABIName);
58 bool IsRV64 = TT.isArch64Bit();
59 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE];
60 bool IsXCheriot = FeatureBits[RISCV::FeatureVendorXCheriot];
61
62 if (!ABIName.empty() && TargetABI == ABI_Unknown) {
63 return createStringError(S: Twine("'") + ABIName +
64 "' is not a recognized ABI for this target");
65 }
66 if (IsRV64 &&
67 (ABIName.starts_with(Prefix: "ilp32") || ABIName.starts_with(Prefix: "il32pc64"))) {
68 return createStringError(
69 Fmt: "32-bit ABIs are not supported for 64-bit targets");
70 }
71 if (!IsRV64 &&
72 (ABIName.starts_with(Prefix: "lp64") || ABIName.starts_with(Prefix: "l64pc128"))) {
73 return createStringError(
74 Fmt: "64-bit ABIs are not supported for 32-bit targets");
75 }
76 if (ABIName.ends_with(Suffix: 'f') && !FeatureBits[RISCV::FeatureStdExtF]) {
77 return createStringError(
78 Fmt: "hard-float 'f' ABI can't be used for a target that doesn't "
79 "support the F instruction set extension");
80 }
81 if (ABIName.ends_with(Suffix: 'd') && !FeatureBits[RISCV::FeatureStdExtD]) {
82 return createStringError(
83 Fmt: "hard-float 'd' ABI can't be used for a target that doesn't "
84 "support the D instruction set extension");
85 }
86 if (!FeatureBits[RISCV::FeatureStdExtY] &&
87 (ABIName.starts_with(Prefix: "il32pc64") || ABIName.starts_with(Prefix: "l64pc128"))) {
88 return createStringError(S: Twine('\'') + ABIName +
89 "' ABI is only supported for RVY targets");
90 }
91 if (!IsRV64 && IsRVE && !IsXCheriot && TargetABI != ABI_ILP32E &&
92 TargetABI != ABI_Unknown) {
93 return createStringError(Fmt: "only the ilp32e ABI is supported for RV32E");
94 }
95 if (!IsRV64 && IsRVE && IsXCheriot && TargetABI != ABI_CHERIOT &&
96 TargetABI != ABI_Unknown) {
97 return createStringError(Fmt: "only the cheriot ABI is supported for XCheriot");
98 }
99 if (IsRV64 && IsRVE && TargetABI != ABI_LP64E && TargetABI != ABI_Unknown) {
100 return createStringError(Fmt: "only the lp64e ABI is supported for RV64E");
101 }
102
103 // Unconditionally fatal: no sensible default ABI to fall back to here.
104 if ((TargetABI == ABI_ILP32E ||
105 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
106 FeatureBits[RISCV::FeatureStdExtD])
107 reportFatalUsageError(reason: "ILP32E cannot be used with the D ISA extension");
108
109 if (TargetABI != ABI_Unknown)
110 return TargetABI;
111
112 // If no explicit ABI is given, try to compute the default ABI.
113 auto ISAInfo = RISCVFeatures::parseFeatureBits(STI);
114 if (!ISAInfo)
115 reportFatalUsageError(Err: ISAInfo.takeError());
116 return getTargetABI(ABIName: (*ISAInfo)->computeDefaultABI());
117}
118
119ABI getTargetABI(StringRef ABIName) {
120 auto TargetABI = StringSwitch<ABI>(ABIName)
121 .Case(S: "ilp32", Value: ABI_ILP32)
122 .Case(S: "ilp32f", Value: ABI_ILP32F)
123 .Case(S: "ilp32d", Value: ABI_ILP32D)
124 .Case(S: "ilp32e", Value: ABI_ILP32E)
125 .Case(S: "il32pc64", Value: ABI_IL32PC64)
126 .Case(S: "il32pc64f", Value: ABI_IL32PC64F)
127 .Case(S: "il32pc64d", Value: ABI_IL32PC64D)
128 .Case(S: "il32pc64e", Value: ABI_IL32PC64E)
129 .Case(S: "lp64", Value: ABI_LP64)
130 .Case(S: "lp64f", Value: ABI_LP64F)
131 .Case(S: "lp64d", Value: ABI_LP64D)
132 .Case(S: "lp64e", Value: ABI_LP64E)
133 .Case(S: "l64pc128", Value: ABI_L64PC128)
134 .Case(S: "l64pc128f", Value: ABI_L64PC128F)
135 .Case(S: "l64pc128d", Value: ABI_L64PC128D)
136 .Case(S: "cheriot", Value: ABI_CHERIOT)
137 .Default(Value: ABI_Unknown);
138 return TargetABI;
139}
140
141// To avoid the BP value clobbered by a function call, we need to choose a
142// callee saved register to save the value. RV32E only has X8 and X9 as callee
143// saved registers and X8 will be used as fp. So we choose X9 as bp.
144MCRegister getBPReg() { return RISCV::X9; }
145
146// Returns the register holding shadow call stack pointer.
147MCRegister getSCSPReg() { return RISCV::X3; }
148
149} // namespace RISCVABI
150
151namespace RISCVFeatures {
152
153void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
154 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
155 reportFatalUsageError(reason: "RV64 target requires an RV64 CPU");
156 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
157 reportFatalUsageError(reason: "RV32 target requires an RV32 CPU");
158 if (FeatureBits[RISCV::Feature32Bit] &&
159 FeatureBits[RISCV::Feature64Bit])
160 reportFatalUsageError(reason: "RV32 and RV64 can't be combined");
161}
162
163llvm::Expected<std::unique_ptr<RISCVISAInfo>>
164parseFeatureBits(const MCSubtargetInfo &STI) {
165 const FeatureBitset &FeatureBits = STI.getFeatureBits();
166 unsigned XLen = FeatureBits[RISCV::Feature64Bit] ? 64 : 32;
167 std::vector<std::string> FeatureVector;
168 // Convert FeatureBitset to FeatureVector.
169 for (const auto &Feature : STI.getAllProcessorFeatures()) {
170 if (FeatureBits[Feature.Value] &&
171 llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext: Feature.key()))
172 FeatureVector.push_back(x: std::string("+") + Feature.key());
173 }
174 return llvm::RISCVISAInfo::parseFeatures(XLen, Features: FeatureVector);
175}
176
177} // namespace RISCVFeatures
178
179// Include the auto-generated portion of the compress emitter.
180#define GEN_UNCOMPRESS_INSTR
181#define GEN_COMPRESS_INSTR
182#include "RISCVGenCompressInstEmitter.inc"
183
184bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
185 const MCSubtargetInfo &STI) {
186 return compressInst(OutInst, MI, STI);
187}
188
189bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
190 const MCSubtargetInfo &STI) {
191 return uncompressInst(OutInst, MI, STI);
192}
193
194// Lookup table for fli.s for entries 2-31.
195static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
196 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
197 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
198 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
199 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
200 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
201 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
202 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
203 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
204 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
205 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
206};
207
208int RISCVLoadFPImm::getLoadFPImm(APFloat FPImm) {
209 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
210 &FPImm.getSemantics() == &APFloat::IEEEdouble() ||
211 &FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
212 "Unexpected semantics");
213
214 // Handle the minimum normalized value which is different for each type.
215 if (FPImm.isSmallestNormalized() && !FPImm.isNegative())
216 return 1;
217
218 // Convert to single precision to use its lookup table.
219 bool LosesInfo;
220 APFloat::opStatus Status = FPImm.convert(
221 ToSemantics: APFloat::IEEEsingle(), RM: APFloat::rmNearestTiesToEven, losesInfo: &LosesInfo);
222 if (Status != APFloat::opOK || LosesInfo)
223 return -1;
224
225 APInt Imm = FPImm.bitcastToAPInt();
226
227 if (Imm.extractBitsAsZExtValue(numBits: 21, bitPosition: 0) != 0)
228 return -1;
229
230 bool Sign = Imm.extractBitsAsZExtValue(numBits: 1, bitPosition: 31);
231 uint8_t Mantissa = Imm.extractBitsAsZExtValue(numBits: 2, bitPosition: 21);
232 uint8_t Exp = Imm.extractBitsAsZExtValue(numBits: 8, bitPosition: 23);
233
234 auto EMI = llvm::lower_bound(Range: LoadFP32ImmArr, Value: std::make_pair(x&: Exp, y&: Mantissa));
235 if (EMI == std::end(arr: LoadFP32ImmArr) || EMI->first != Exp ||
236 EMI->second != Mantissa)
237 return -1;
238
239 // Table doesn't have entry 0 or 1.
240 int Entry = std::distance(first: std::begin(arr: LoadFP32ImmArr), last: EMI) + 2;
241
242 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
243 if (Sign) {
244 if (Entry == 16)
245 return 0;
246 return -1;
247 }
248
249 return Entry;
250}
251
252float RISCVLoadFPImm::getFPImm(unsigned Imm) {
253 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
254
255 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
256 uint32_t Sign = 0;
257 if (Imm == 0) {
258 Sign = 0b1;
259 Imm = 16;
260 }
261
262 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
263 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
264
265 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
266 return bit_cast<float>(from: I);
267}
268
269void RISCVZC::printRegList(unsigned RlistEncode, raw_ostream &OS) {
270 assert(RlistEncode >= RLISTENCODE::RA &&
271 RlistEncode <= RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
272 OS << "{ra";
273 if (RlistEncode > RISCVZC::RA) {
274 OS << ", s0";
275 if (RlistEncode == RISCVZC::RA_S0_S11)
276 OS << "-s11";
277 else if (RlistEncode > RISCVZC::RA_S0 && RlistEncode <= RISCVZC::RA_S0_S11)
278 OS << "-s" << (RlistEncode - RISCVZC::RA_S0);
279 }
280 OS << "}";
281}
282
283} // namespace llvm
284