1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/TargetParser/RISCVISAInfo.h"
23#include "llvm/TargetParser/RISCVTargetParser.h"
24#include "llvm/TargetParser/SubtargetFeature.h"
25
26namespace llvm {
27
28namespace RISCVOp {
29enum OperandType : unsigned {
30 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
31 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
32 OPERAND_UIMM2,
33 OPERAND_UIMM2_LSB0,
34 OPERAND_UIMM3,
35 OPERAND_UIMM4,
36 OPERAND_UIMM5,
37 OPERAND_UIMM5_NONZERO,
38 OPERAND_UIMM5_GT3,
39 OPERAND_UIMM5_PLUS1,
40 OPERAND_UIMM5_GE6_PLUS1,
41 OPERAND_UIMM5_LSB0,
42 OPERAND_UIMM5_SLIST,
43 OPERAND_UIMM6,
44 OPERAND_UIMM6_LSB0,
45 OPERAND_UIMM7,
46 OPERAND_UIMM7_LSB00,
47 OPERAND_UIMM7_LSB000,
48 OPERAND_UIMM8_LSB00,
49 OPERAND_UIMM8,
50 OPERAND_UIMM8_LSB000,
51 OPERAND_UIMM8_GE32,
52 OPERAND_UIMM9_LSB000,
53 OPERAND_UIMM9,
54 OPERAND_UIMM10,
55 OPERAND_UIMM10_LSB00_NONZERO,
56 OPERAND_UIMM11,
57 OPERAND_UIMM12,
58 OPERAND_UIMM14_LSB00,
59 OPERAND_UIMM16,
60 OPERAND_UIMM16_NONZERO,
61 OPERAND_UIMMLOG2XLEN,
62 OPERAND_UIMMLOG2XLEN_NONZERO,
63 OPERAND_UIMM32,
64 OPERAND_UIMM48,
65 OPERAND_UIMM64,
66 OPERAND_THREE,
67 OPERAND_FOUR,
68 OPERAND_IMM5_ZIBI,
69 OPERAND_SIMM5,
70 OPERAND_SIMM5_NONZERO,
71 OPERAND_SIMM5_PLUS1,
72 OPERAND_SIMM6,
73 OPERAND_SIMM6_NONZERO,
74 OPERAND_SIMM8,
75 OPERAND_SIMM10,
76 OPERAND_SIMM10_LSB0000_NONZERO,
77 OPERAND_SIMM10_UNSIGNED,
78 OPERAND_SIMM11,
79 OPERAND_SIMM12_LSB00000,
80 OPERAND_SIMM16,
81 OPERAND_SIMM16_NONZERO,
82 OPERAND_SIMM20,
83 OPERAND_SIMM20_LI,
84 OPERAND_SIMM26,
85 OPERAND_CLUI_IMM,
86 OPERAND_VTYPEI10,
87 OPERAND_VTYPEI11,
88 OPERAND_RVKRNUM,
89 OPERAND_RVKRNUM_0_7,
90 OPERAND_RVKRNUM_1_10,
91 OPERAND_RVKRNUM_2_14,
92 OPERAND_RLIST,
93 OPERAND_RLIST_S0,
94 OPERAND_STACKADJ,
95 // Operand is a 3-bit rounding mode, '111' indicates FRM register.
96 // Represents 'frm' argument passing to floating-point operations.
97 OPERAND_FRMARG,
98 // Operand is a 3-bit rounding mode where only RTZ is valid.
99 OPERAND_RTZARG,
100 // Condition code used by select and short forward branch pseudos.
101 OPERAND_COND_CODE,
102 // Ordering for atomic pseudos.
103 OPERAND_ATOMIC_ORDERING,
104 // Vector policy operand.
105 OPERAND_VEC_POLICY,
106 // Vector SEW operand. Stores in log2(SEW).
107 OPERAND_SEW,
108 // Special SEW for mask only instructions. Always 0.
109 OPERAND_SEW_MASK,
110 // Vector rounding mode for VXRM or FRM.
111 OPERAND_VEC_RM,
112 // Vtype operand for XSfmm extension.
113 OPERAND_XSFMM_VTYPE,
114 // XSfmm twiden operand.
115 OPERAND_XSFMM_TWIDEN,
116 OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_TWIDEN,
117
118 OPERAND_UIMM20_LUI,
119 OPERAND_UIMM20_AUIPC,
120
121 // Simm12 or constant pool, global, basicblock, etc.
122 OPERAND_SIMM12_LO,
123
124 OPERAND_BARE_SIMM32,
125
126 // Operand is either a register or uimm5, this is used by V extension pseudo
127 // instructions to represent a value that be passed as AVL to either vsetvli
128 // or vsetivli.
129 OPERAND_AVL,
130
131 // Operand is either a register or imm, this is used by short forward branch
132 // (SFB) pseudos to enable SFB with branches on reg-reg and reg-imm compares.
133 OPERAND_SFB_RHS,
134
135 // Operand is a branch opcode, this too is used by SFB pseudos.
136 OPERAND_BCC_OPCODE,
137
138 OPERAND_VMASK,
139};
140} // namespace RISCVOp
141
142// RISCVII - This namespace holds all of the target specific flags that
143// instruction info tracks. All definitions must match RISCVInstrFormats.td.
144namespace RISCVII {
145enum {
146 InstFormatPseudo = 0,
147 InstFormatR = 1,
148 InstFormatR4 = 2,
149 InstFormatI = 3,
150 InstFormatS = 4,
151 InstFormatB = 5,
152 InstFormatU = 6,
153 InstFormatJ = 7,
154 InstFormatCR = 8,
155 InstFormatCI = 9,
156 InstFormatCSS = 10,
157 InstFormatCIW = 11,
158 InstFormatCL = 12,
159 InstFormatCS = 13,
160 InstFormatCA = 14,
161 InstFormatCB = 15,
162 InstFormatCJ = 16,
163 InstFormatCU = 17,
164 InstFormatCLB = 18,
165 InstFormatCLH = 19,
166 InstFormatCSB = 20,
167 InstFormatCSH = 21,
168 InstFormatQC_EAI = 22,
169 InstFormatQC_EI = 23,
170 InstFormatQC_EB = 24,
171 InstFormatQC_EJ = 25,
172 InstFormatQC_ES = 26,
173 InstFormatNDS_BRANCH_10 = 27,
174 InstFormatOther = 31,
175
176 InstFormatMask = 31,
177 InstFormatShift = 0,
178
179 RVVConstraintShift = InstFormatShift + 5,
180 VS2Constraint = 0b001 << RVVConstraintShift,
181 VS1Constraint = 0b010 << RVVConstraintShift,
182 VMConstraint = 0b100 << RVVConstraintShift,
183 RVVConstraintMask = 0b111 << RVVConstraintShift,
184
185 VLMulShift = RVVConstraintShift + 3,
186 VLMulMask = 0b111 << VLMulShift,
187
188 // Is this a _TIED vector pseudo instruction. For these instructions we
189 // shouldn't skip the tied operand when converting to MC instructions.
190 IsTiedPseudoShift = VLMulShift + 3,
191 IsTiedPseudoMask = 1 << IsTiedPseudoShift,
192
193 // Does this instruction have a SEW operand. It will be the last explicit
194 // operand unless there is a vector policy operand. Used by RVV Pseudos.
195 HasSEWOpShift = IsTiedPseudoShift + 1,
196 HasSEWOpMask = 1 << HasSEWOpShift,
197
198 // Does this instruction have a VL operand. It will be the second to last
199 // explicit operand unless there is a vector policy operand. Used by RVV
200 // Pseudos.
201 HasVLOpShift = HasSEWOpShift + 1,
202 HasVLOpMask = 1 << HasVLOpShift,
203
204 // Does this instruction have a vector policy operand. It will be the last
205 // explicit operand. Used by RVV Pseudos.
206 HasVecPolicyOpShift = HasVLOpShift + 1,
207 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
208
209 // Is this instruction a vector widening reduction instruction. Used by RVV
210 // Pseudos.
211 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
212 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
213
214 // Does this instruction care about mask policy. If it is not, the mask policy
215 // could be either agnostic or undisturbed. For example, unmasked, store, and
216 // reduction operations result would not be affected by mask policy, so
217 // compiler has free to select either one.
218 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
219 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
220
221 // Indicates that the result can be considered sign extended from bit 31. Some
222 // instructions with this flag aren't W instructions, but are either sign
223 // extended from a smaller size, always outputs a small integer, or put zeros
224 // in bits 63:31. Used by the SExtWRemoval pass.
225 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
226 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
227
228 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
229 HasRoundModeOpMask = 1 << HasRoundModeOpShift,
230
231 UsesVXRMShift = HasRoundModeOpShift + 1,
232 UsesVXRMMask = 1 << UsesVXRMShift,
233
234 // Indicates whether these instructions can partially overlap between source
235 // registers and destination registers according to the vector spec.
236 // 0 -> not a vector pseudo
237 // 1 -> default value for vector pseudos. not widening or narrowing.
238 // 2 -> narrowing case
239 // 3 -> widening case
240 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
241 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
242
243 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,
244 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,
245
246 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
247 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,
248
249 // Indicates the EEW of a vector instruction's destination operand.
250 // 0 -> 1
251 // 1 -> SEW
252 // 2 -> SEW * 2
253 // 3 -> SEW * 4
254 DestEEWShift = ElementsDependOnMaskShift + 1,
255 DestEEWMask = 3ULL << DestEEWShift,
256
257 ReadsPastVLShift = DestEEWShift + 2,
258 ReadsPastVLMask = 1ULL << ReadsPastVLShift,
259
260 // 0 -> Don't care about altfmt bit in VTYPE.
261 // 1 -> Is not altfmt.
262 // 2 -> Is altfmt(BF16).
263 AltFmtTypeShift = ReadsPastVLShift + 1,
264 AltFmtTypeMask = 3ULL << AltFmtTypeShift,
265
266 // XSfmmbase
267 HasTWidenOpShift = AltFmtTypeShift + 2,
268 HasTWidenOpMask = 1ULL << HasTWidenOpShift,
269
270 HasTMOpShift = HasTWidenOpShift + 1,
271 HasTMOpMask = 1ULL << HasTMOpShift,
272
273 HasTKOpShift = HasTMOpShift + 1,
274 HasTKOpMask = 1ULL << HasTKOpShift,
275};
276
277// Helper functions to read TSFlags.
278/// \returns the format of the instruction.
279static inline unsigned getFormat(uint64_t TSFlags) {
280 return (TSFlags & InstFormatMask) >> InstFormatShift;
281}
282/// \returns the LMUL for the instruction.
283static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
284 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
285}
286/// \returns true if this a _TIED pseudo.
287static inline bool isTiedPseudo(uint64_t TSFlags) {
288 return TSFlags & IsTiedPseudoMask;
289}
290/// \returns true if there is a SEW operand for the instruction.
291static inline bool hasSEWOp(uint64_t TSFlags) {
292 return TSFlags & HasSEWOpMask;
293}
294/// \returns true if there is a VL operand for the instruction.
295static inline bool hasVLOp(uint64_t TSFlags) {
296 return TSFlags & HasVLOpMask;
297}
298/// \returns true if there is a vector policy operand for this instruction.
299static inline bool hasVecPolicyOp(uint64_t TSFlags) {
300 return TSFlags & HasVecPolicyOpMask;
301}
302/// \returns true if it is a vector widening reduction instruction.
303static inline bool isRVVWideningReduction(uint64_t TSFlags) {
304 return TSFlags & IsRVVWideningReductionMask;
305}
306/// \returns true if mask policy is valid for the instruction.
307static inline bool usesMaskPolicy(uint64_t TSFlags) {
308 return TSFlags & UsesMaskPolicyMask;
309}
310
311/// \returns true if there is a rounding mode operand for this instruction
312static inline bool hasRoundModeOp(uint64_t TSFlags) {
313 return TSFlags & HasRoundModeOpMask;
314}
315
316enum class AltFmtType { DontCare, NotAltFmt, AltFmt };
317static inline AltFmtType getAltFmtType(uint64_t TSFlags) {
318 return static_cast<AltFmtType>((TSFlags & AltFmtTypeMask) >> AltFmtTypeShift);
319}
320
321/// \returns true if this instruction uses vxrm
322static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
323
324/// \returns true if the elements in the body are affected by VL,
325/// e.g. vslide1down.vx/vredsum.vs/viota.m
326static inline bool elementsDependOnVL(uint64_t TSFlags) {
327 return TSFlags & ElementsDependOnVLMask;
328}
329
330/// \returns true if the elements in the body are affected by the mask,
331/// e.g. vredsum.vs/viota.m
332static inline bool elementsDependOnMask(uint64_t TSFlags) {
333 return TSFlags & ElementsDependOnMaskMask;
334}
335
336/// \returns true if the instruction may read elements past VL, e.g.
337/// vslidedown/vrgather
338static inline bool readsPastVL(uint64_t TSFlags) {
339 return TSFlags & ReadsPastVLMask;
340}
341
342// XSfmmbase
343static inline bool hasTWidenOp(uint64_t TSFlags) {
344 return TSFlags & HasTWidenOpMask;
345}
346
347static inline bool hasTMOp(uint64_t TSFlags) { return TSFlags & HasTMOpMask; }
348
349static inline bool hasTKOp(uint64_t TSFlags) { return TSFlags & HasTKOpMask; }
350
351static inline unsigned getTWidenOpNum(const MCInstrDesc &Desc) {
352 assert(hasTWidenOp(Desc.TSFlags));
353 return Desc.getNumOperands() - 1;
354}
355
356static inline unsigned getTNOpNum(const MCInstrDesc &Desc) {
357 const uint64_t TSFlags = Desc.TSFlags;
358 assert(hasTWidenOp(TSFlags) && hasVLOp(TSFlags));
359 unsigned Offset = 3;
360 if (hasTKOp(TSFlags))
361 Offset = 4;
362 return Desc.getNumOperands() - Offset;
363}
364
365static inline unsigned getTMOpNum(const MCInstrDesc &Desc) {
366 const uint64_t TSFlags = Desc.TSFlags;
367 assert(hasTWidenOp(TSFlags) && hasTMOp(TSFlags));
368 if (hasTKOp(TSFlags))
369 return Desc.getNumOperands() - 5;
370 // vtzero.t
371 return Desc.getNumOperands() - 4;
372}
373
374static inline unsigned getTKOpNum(const MCInstrDesc &Desc) {
375 [[maybe_unused]] const uint64_t TSFlags = Desc.TSFlags;
376 assert(hasTWidenOp(TSFlags) && hasTKOp(TSFlags));
377 return Desc.getNumOperands() - 3;
378}
379
380static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
381 const uint64_t TSFlags = Desc.TSFlags;
382 // This method is only called if we expect to have a VL operand, and all
383 // instructions with VL also have SEW.
384 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
385 // In Xsfmmbase, TN is an alias for VL, so here we use the same TSFlags bit.
386 if (hasTWidenOp(TSFlags))
387 return getTNOpNum(Desc);
388 unsigned Offset = 2;
389 if (hasVecPolicyOp(TSFlags))
390 Offset = 3;
391 return Desc.getNumOperands() - Offset;
392}
393
394static inline MCRegister
395getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
396 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
397 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
398 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
399}
400
401static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
402 const uint64_t TSFlags = Desc.TSFlags;
403 assert(hasSEWOp(TSFlags));
404 unsigned Offset = 1;
405 if (hasVecPolicyOp(TSFlags) || hasTWidenOp(TSFlags))
406 Offset = 2;
407 return Desc.getNumOperands() - Offset;
408}
409
410static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
411 assert(hasVecPolicyOp(Desc.TSFlags));
412 return Desc.getNumOperands() - 1;
413}
414
415/// \returns the index to the rounding mode immediate value if any, otherwise
416/// returns -1.
417static inline int getFRMOpNum(const MCInstrDesc &Desc) {
418 const uint64_t TSFlags = Desc.TSFlags;
419 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
420 return -1;
421
422 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
423 assert(Idx >= 0 && "No rm operand?");
424 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
425 "Operand has wrong type");
426
427 return Idx;
428}
429
430/// \returns the index to the rounding mode immediate value if any, otherwise
431/// returns -1.
432static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
433 const uint64_t TSFlags = Desc.TSFlags;
434 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
435 return -1;
436
437 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
438 assert(Idx >= 0 && "No rm operand?");
439 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
440 "Operand has wrong type");
441
442 return Idx;
443}
444
445// Is the first def operand tied to the first use operand. This is true for
446// vector pseudo instructions that have a merge operand for tail/mask
447// undisturbed. It's also true for vector FMA instructions where one of the
448// operands is also the destination register.
449static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
450 return Desc.getNumDefs() < Desc.getNumOperands() &&
451 Desc.getOperandConstraint(OpNum: Desc.getNumDefs(), Constraint: MCOI::TIED_TO) == 0;
452}
453
454// RISC-V Specific Machine Operand Flags
455enum {
456 MO_None = 0,
457 MO_CALL = 1,
458 MO_LO = 3,
459 MO_HI = 4,
460 MO_PCREL_LO = 5,
461 MO_PCREL_HI = 6,
462 MO_GOT_HI = 7,
463 MO_TPREL_LO = 8,
464 MO_TPREL_HI = 9,
465 MO_TPREL_ADD = 10,
466 MO_TLS_GOT_HI = 11,
467 MO_TLS_GD_HI = 12,
468 MO_TLSDESC_HI = 13,
469 MO_TLSDESC_LOAD_LO = 14,
470 MO_TLSDESC_ADD_LO = 15,
471 MO_TLSDESC_CALL = 16,
472
473 // Used to differentiate between target-specific "direct" flags and "bitmask"
474 // flags. A machine operand can only have one "direct" flag, but can have
475 // multiple "bitmask" flags.
476 MO_DIRECT_FLAG_MASK = 31
477};
478} // namespace RISCVII
479
480// Describes the predecessor/successor bits used in the FENCE instruction.
481namespace RISCVFenceField {
482enum FenceField {
483 I = 8,
484 O = 4,
485 R = 2,
486 W = 1
487};
488}
489
490// Describes the supported floating point rounding mode encodings.
491namespace RISCVFPRndMode {
492enum RoundingMode {
493 RNE = 0,
494 RTZ = 1,
495 RDN = 2,
496 RUP = 3,
497 RMM = 4,
498 DYN = 7,
499 Invalid
500};
501
502inline static StringRef roundingModeToString(RoundingMode RndMode) {
503 switch (RndMode) {
504 default:
505 llvm_unreachable("Unknown floating point rounding mode");
506 case RISCVFPRndMode::RNE:
507 return "rne";
508 case RISCVFPRndMode::RTZ:
509 return "rtz";
510 case RISCVFPRndMode::RDN:
511 return "rdn";
512 case RISCVFPRndMode::RUP:
513 return "rup";
514 case RISCVFPRndMode::RMM:
515 return "rmm";
516 case RISCVFPRndMode::DYN:
517 return "dyn";
518 }
519}
520
521inline static RoundingMode stringToRoundingMode(StringRef Str) {
522 return StringSwitch<RoundingMode>(Str)
523 .Case(S: "rne", Value: RISCVFPRndMode::RNE)
524 .Case(S: "rtz", Value: RISCVFPRndMode::RTZ)
525 .Case(S: "rdn", Value: RISCVFPRndMode::RDN)
526 .Case(S: "rup", Value: RISCVFPRndMode::RUP)
527 .Case(S: "rmm", Value: RISCVFPRndMode::RMM)
528 .Case(S: "dyn", Value: RISCVFPRndMode::DYN)
529 .Default(Value: RISCVFPRndMode::Invalid);
530}
531
532inline static bool isValidRoundingMode(unsigned Mode) {
533 switch (Mode) {
534 default:
535 return false;
536 case RISCVFPRndMode::RNE:
537 case RISCVFPRndMode::RTZ:
538 case RISCVFPRndMode::RDN:
539 case RISCVFPRndMode::RUP:
540 case RISCVFPRndMode::RMM:
541 case RISCVFPRndMode::DYN:
542 return true;
543 }
544}
545} // namespace RISCVFPRndMode
546
547namespace RISCVVXRndMode {
548enum RoundingMode {
549 RNU = 0,
550 RNE = 1,
551 RDN = 2,
552 ROD = 3,
553 Invalid
554};
555
556inline static StringRef roundingModeToString(RoundingMode RndMode) {
557 switch (RndMode) {
558 default:
559 llvm_unreachable("Unknown vector fixed-point rounding mode");
560 case RISCVVXRndMode::RNU:
561 return "rnu";
562 case RISCVVXRndMode::RNE:
563 return "rne";
564 case RISCVVXRndMode::RDN:
565 return "rdn";
566 case RISCVVXRndMode::ROD:
567 return "rod";
568 }
569}
570
571inline static RoundingMode stringToRoundingMode(StringRef Str) {
572 return StringSwitch<RoundingMode>(Str)
573 .Case(S: "rnu", Value: RISCVVXRndMode::RNU)
574 .Case(S: "rne", Value: RISCVVXRndMode::RNE)
575 .Case(S: "rdn", Value: RISCVVXRndMode::RDN)
576 .Case(S: "rod", Value: RISCVVXRndMode::ROD)
577 .Default(Value: RISCVVXRndMode::Invalid);
578}
579
580inline static bool isValidRoundingMode(unsigned Mode) {
581 switch (Mode) {
582 default:
583 return false;
584 case RISCVVXRndMode::RNU:
585 case RISCVVXRndMode::RNE:
586 case RISCVVXRndMode::RDN:
587 case RISCVVXRndMode::ROD:
588 return true;
589 }
590}
591} // namespace RISCVVXRndMode
592
593namespace RISCVExceptFlags {
594enum ExceptionFlag {
595 NX = 0x01, // Inexact
596 UF = 0x02, // Underflow
597 OF = 0x04, // Overflow
598 DZ = 0x08, // Divide by zero
599 NV = 0x10, // Invalid operation
600 ALL = 0x1F // Mask for all accrued exception flags
601};
602}
603
604//===----------------------------------------------------------------------===//
605// Floating-point Immediates
606//
607
608namespace RISCVLoadFPImm {
609float getFPImm(unsigned Imm);
610
611/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
612/// immediate value. If the value cannot be represented as a 5-bit binary
613/// encoding, then return -1.
614int getLoadFPImm(APFloat FPImm);
615} // namespace RISCVLoadFPImm
616
617namespace RISCVSysReg {
618struct SysReg {
619 const char Name[32];
620 unsigned Encoding;
621 // FIXME: add these additional fields when needed.
622 // Privilege Access: Read, Write, Read-Only.
623 // unsigned ReadWrite;
624 // Privilege Mode: User, System or Machine.
625 // unsigned Mode;
626 // Check field name.
627 // unsigned Extra;
628 // Register number without the privilege bits.
629 // unsigned Number;
630 FeatureBitset FeaturesRequired;
631 bool IsRV32Only;
632 bool IsAltName;
633 bool IsDeprecatedName;
634
635 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
636 // Not in 32-bit mode.
637 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
638 return false;
639 // No required feature associated with the system register.
640 if (FeaturesRequired.none())
641 return true;
642 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
643 }
644};
645
646#define GET_SysRegEncodings_DECL
647#define GET_SysRegsList_DECL
648#include "RISCVGenSearchableTables.inc"
649} // end namespace RISCVSysReg
650
651namespace RISCVInsnOpcode {
652struct RISCVOpcode {
653 char Name[10];
654 uint8_t Value;
655};
656
657#define GET_RISCVOpcodesList_DECL
658#include "RISCVGenSearchableTables.inc"
659} // end namespace RISCVInsnOpcode
660
661namespace RISCVABI {
662
663enum ABI {
664 ABI_ILP32,
665 ABI_ILP32F,
666 ABI_ILP32D,
667 ABI_ILP32E,
668 ABI_LP64,
669 ABI_LP64F,
670 ABI_LP64D,
671 ABI_LP64E,
672 ABI_Unknown
673};
674
675// Returns the target ABI, or else a StringError if the requested ABIName is
676// not supported for the given TT and FeatureBits combination.
677ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
678 StringRef ABIName);
679
680ABI getTargetABI(StringRef ABIName);
681
682// Returns the register used to hold the stack pointer after realignment.
683MCRegister getBPReg();
684
685// Returns the register holding shadow call stack pointer.
686MCRegister getSCSPReg();
687
688} // namespace RISCVABI
689
690namespace RISCVFeatures {
691
692// Validates if the given combination of features are valid for the target
693// triple. Exits with report_fatal_error if not.
694void validate(const Triple &TT, const FeatureBitset &FeatureBits);
695
696llvm::Expected<std::unique_ptr<RISCVISAInfo>>
697parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
698
699} // namespace RISCVFeatures
700
701namespace RISCVRVC {
702bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
703bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
704} // namespace RISCVRVC
705
706namespace RISCVZC {
707enum RLISTENCODE {
708 RA = 4,
709 RA_S0,
710 RA_S0_S1,
711 RA_S0_S2,
712 RA_S0_S3,
713 RA_S0_S4,
714 RA_S0_S5,
715 RA_S0_S6,
716 RA_S0_S7,
717 RA_S0_S8,
718 RA_S0_S9,
719 // note - to include s10, s11 must also be included
720 RA_S0_S11,
721 INVALID_RLIST,
722};
723
724inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
725 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
726 switch (EndReg.id()) {
727 case RISCV::X1:
728 return RLISTENCODE::RA;
729 case RISCV::X8:
730 return RLISTENCODE::RA_S0;
731 case RISCV::X9:
732 return RLISTENCODE::RA_S0_S1;
733 case RISCV::X18:
734 return RLISTENCODE::RA_S0_S2;
735 case RISCV::X19:
736 return RLISTENCODE::RA_S0_S3;
737 case RISCV::X20:
738 return RLISTENCODE::RA_S0_S4;
739 case RISCV::X21:
740 return RLISTENCODE::RA_S0_S5;
741 case RISCV::X22:
742 return RLISTENCODE::RA_S0_S6;
743 case RISCV::X23:
744 return RLISTENCODE::RA_S0_S7;
745 case RISCV::X24:
746 return RLISTENCODE::RA_S0_S8;
747 case RISCV::X25:
748 return RLISTENCODE::RA_S0_S9;
749 case RISCV::X27:
750 return RLISTENCODE::RA_S0_S11;
751 default:
752 llvm_unreachable("Undefined input.");
753 }
754}
755
756inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
757 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
758 "Unexpected number of registers");
759 if (NumRegs == 13)
760 return RLISTENCODE::RA_S0_S11;
761
762 return RLISTENCODE::RA + (NumRegs - 1);
763}
764
765inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
766 assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&
767 "Invalid Rlist");
768 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;
769 // s10 and s11 are saved together.
770 if (RlistVal == RLISTENCODE::RA_S0_S11)
771 ++NumRegs;
772
773 unsigned RegSize = IsRV64 ? 8 : 4;
774 return alignTo(Value: NumRegs * RegSize, Align: 16);
775}
776
777void printRegList(unsigned RlistEncode, raw_ostream &OS);
778} // namespace RISCVZC
779
780namespace RISCVVInversePseudosTable {
781struct PseudoInfo {
782 uint16_t Pseudo;
783 uint16_t BaseInstr;
784 uint16_t VLMul : 3;
785 uint16_t SEW : 8;
786 uint16_t IsAltFmt : 1;
787};
788
789#define GET_RISCVVInversePseudosTable_DECL
790#include "RISCVGenSearchableTables.inc"
791
792inline const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul,
793 uint8_t SEW, bool IsAltFmt = false) {
794 return getBaseInfoImpl(BaseInstr, VLMul, SEW, IsAltFmt);
795}
796} // namespace RISCVVInversePseudosTable
797
798namespace RISCV {
799struct VLSEGPseudo {
800 uint16_t NF : 4;
801 uint16_t Masked : 1;
802 uint16_t Strided : 1;
803 uint16_t FF : 1;
804 uint16_t Log2SEW : 3;
805 uint16_t LMUL : 3;
806 uint16_t Pseudo;
807};
808
809struct VLXSEGPseudo {
810 uint16_t NF : 4;
811 uint16_t Masked : 1;
812 uint16_t Ordered : 1;
813 uint16_t Log2SEW : 3;
814 uint16_t LMUL : 3;
815 uint16_t IndexLMUL : 3;
816 uint16_t Pseudo;
817};
818
819struct VSSEGPseudo {
820 uint16_t NF : 4;
821 uint16_t Masked : 1;
822 uint16_t Strided : 1;
823 uint16_t Log2SEW : 3;
824 uint16_t LMUL : 3;
825 uint16_t Pseudo;
826};
827
828struct VSXSEGPseudo {
829 uint16_t NF : 4;
830 uint16_t Masked : 1;
831 uint16_t Ordered : 1;
832 uint16_t Log2SEW : 3;
833 uint16_t LMUL : 3;
834 uint16_t IndexLMUL : 3;
835 uint16_t Pseudo;
836};
837
838struct VLEPseudo {
839 uint16_t Masked : 1;
840 uint16_t Strided : 1;
841 uint16_t FF : 1;
842 uint16_t Log2SEW : 3;
843 uint16_t LMUL : 3;
844 uint16_t Pseudo;
845};
846
847struct VSEPseudo {
848 uint16_t Masked : 1;
849 uint16_t Strided : 1;
850 uint16_t Log2SEW : 3;
851 uint16_t LMUL : 3;
852 uint16_t Pseudo;
853};
854
855struct VLX_VSXPseudo {
856 uint16_t Masked : 1;
857 uint16_t Ordered : 1;
858 uint16_t Log2SEW : 3;
859 uint16_t LMUL : 3;
860 uint16_t IndexLMUL : 3;
861 uint16_t Pseudo;
862};
863
864struct NDSVLNPseudo {
865 uint16_t Masked : 1;
866 uint16_t Unsigned : 1;
867 uint16_t Log2SEW : 3;
868 uint16_t LMUL : 3;
869 uint16_t Pseudo;
870};
871
872#define GET_RISCVVSSEGTable_DECL
873#define GET_RISCVVLSEGTable_DECL
874#define GET_RISCVVLXSEGTable_DECL
875#define GET_RISCVVSXSEGTable_DECL
876#define GET_RISCVVLETable_DECL
877#define GET_RISCVVSETable_DECL
878#define GET_RISCVVLXTable_DECL
879#define GET_RISCVVSXTable_DECL
880#define GET_RISCVNDSVLNTable_DECL
881#include "RISCVGenSearchableTables.inc"
882} // namespace RISCV
883
884} // namespace llvm
885
886#endif
887