1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/ADT/StringTable.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/TargetParser/RISCVISAInfo.h"
24#include "llvm/TargetParser/RISCVTargetParser.h"
25#include "llvm/TargetParser/SubtargetFeature.h"
26
27namespace llvm {
28
29class MCSubtargetInfo;
30
31namespace RISCVOp {
32enum OperandType : unsigned {
33 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
34 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
35 OPERAND_UIMM2,
36 OPERAND_UIMM2_LSB0,
37 OPERAND_UIMM3,
38 OPERAND_UIMM4,
39 OPERAND_UIMM4_PLUS1,
40 OPERAND_UIMM5,
41 OPERAND_UIMM5_NONZERO,
42 OPERAND_UIMM5_GT3,
43 OPERAND_UIMM5_PLUS1,
44 OPERAND_UIMM5_GE6_PLUS1,
45 OPERAND_UIMM5_LSB0,
46 OPERAND_UIMM5_SLIST,
47 OPERAND_UIMM6,
48 OPERAND_UIMM6_PLUS1,
49 OPERAND_UIMM6_LSB0,
50 OPERAND_UIMM7,
51 OPERAND_UIMM7_LSB00,
52 OPERAND_UIMM7_LSB000,
53 OPERAND_UIMM7_EQ_XLEN,
54 OPERAND_UIMM8_LSB00,
55 OPERAND_UIMM8,
56 OPERAND_UIMM8_LSB000,
57 OPERAND_UIMM8_GE32,
58 OPERAND_UIMM9,
59 OPERAND_UIMM9_LSB000,
60 OPERAND_UIMM9_YBNDSWI,
61 OPERAND_UIMM10,
62 OPERAND_UIMM10_LSB00_NONZERO,
63 OPERAND_UIMM11,
64 OPERAND_UIMM12,
65 OPERAND_UIMM14_LSB00,
66 OPERAND_UIMM16,
67 OPERAND_UIMM16_NONZERO,
68 OPERAND_UIMMLOG2XLEN,
69 OPERAND_UIMMLOG2XLEN_NONZERO,
70 OPERAND_UIMM32,
71 OPERAND_UIMM48,
72 OPERAND_UIMM64,
73 OPERAND_THREE,
74 OPERAND_FOUR,
75 OPERAND_IMM5_ZIBI,
76 OPERAND_SIMM5,
77 OPERAND_SIMM5_NONZERO,
78 OPERAND_SIMM5_PLUS1,
79 OPERAND_SIMM6,
80 OPERAND_SIMM6_NONZERO,
81 OPERAND_SIMM8,
82 OPERAND_SIMM10,
83 OPERAND_SIMM10_LSB0000_NONZERO,
84 OPERAND_SIMM10_UNSIGNED,
85 OPERAND_SIMM11,
86 OPERAND_SIMM12,
87 OPERAND_SIMM12_LSB00000,
88 OPERAND_SIMM16,
89 OPERAND_SIMM16_NONZERO,
90 OPERAND_SIMM20,
91 OPERAND_SIMM20_LI,
92 OPERAND_SIMM26,
93 OPERAND_CLUI_IMM,
94 OPERAND_VTYPEI10,
95 OPERAND_VTYPEI11,
96 OPERAND_RVKRNUM,
97 OPERAND_RVKRNUM_0_7,
98 OPERAND_RVKRNUM_1_10,
99 OPERAND_RVKRNUM_2_14,
100 OPERAND_RLIST,
101 OPERAND_RLIST_S0,
102 OPERAND_STACKADJ,
103 // Operand is a 3-bit rounding mode, '111' indicates FRM register.
104 // Represents 'frm' argument passing to floating-point operations.
105 OPERAND_FRMARG,
106 // Operand is a 3-bit rounding mode where only RTZ is valid.
107 OPERAND_RTZARG,
108 // Condition code used by select and short forward branch pseudos.
109 OPERAND_COND_CODE,
110 // Ordering for atomic pseudos.
111 OPERAND_ATOMIC_ORDERING,
112 // Vector policy operand.
113 OPERAND_VEC_POLICY,
114 // Vector SEW operand. Stores in log2(SEW).
115 OPERAND_SEW,
116 // Special SEW for mask only instructions. Always 0.
117 OPERAND_SEW_MASK,
118 // Vector rounding mode for VXRM or FRM.
119 OPERAND_VEC_RM,
120 // Vtype operand for XSfmm extension.
121 OPERAND_XSFMM_VTYPE,
122 // XSfmm twiden operand.
123 OPERAND_XSFMM_TWIDEN,
124 OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_TWIDEN,
125
126 OPERAND_UIMM20_LUI,
127 OPERAND_UIMM20_AUIPC,
128
129 // Simm12 or constant pool, global, basicblock, etc.
130 OPERAND_SIMM12_LO,
131
132 OPERAND_BARE_SIMM32,
133
134 // Operand is either a register or uimm5, this is used by V extension pseudo
135 // instructions to represent a value that be passed as AVL to either vsetvli
136 // or vsetivli.
137 OPERAND_AVL,
138
139 // Operand is either a register or imm, this is used by short forward branch
140 // (SFB) pseudos to enable SFB with branches on reg-reg and reg-imm compares.
141 OPERAND_SFB_RHS,
142
143 // Operand is a branch opcode, this too is used by SFB pseudos.
144 OPERAND_BCC_OPCODE,
145
146 OPERAND_VMASK,
147};
148} // namespace RISCVOp
149
150// RISCVII - This namespace holds all of the target specific flags that
151// instruction info tracks. All definitions must match RISCVInstrFormats.td.
152namespace RISCVII {
153enum {
154 InstFormatPseudo = 0,
155 InstFormatR = 1,
156 InstFormatR4 = 2,
157 InstFormatI = 3,
158 InstFormatS = 4,
159 InstFormatB = 5,
160 InstFormatU = 6,
161 InstFormatJ = 7,
162 InstFormatCR = 8,
163 InstFormatCI = 9,
164 InstFormatCSS = 10,
165 InstFormatCIW = 11,
166 InstFormatCL = 12,
167 InstFormatCS = 13,
168 InstFormatCA = 14,
169 InstFormatCB = 15,
170 InstFormatCJ = 16,
171 InstFormatCU = 17,
172 InstFormatCLB = 18,
173 InstFormatCLH = 19,
174 InstFormatCSB = 20,
175 InstFormatCSH = 21,
176 InstFormatQC_EAI = 22,
177 InstFormatQC_EI = 23,
178 InstFormatQC_EB = 24,
179 InstFormatQC_EJ = 25,
180 InstFormatQC_ES = 26,
181 InstFormatNDS_BRANCH_10 = 27,
182 InstFormatOther = 31,
183
184 InstFormatMask = 31,
185 InstFormatShift = 0,
186
187 RVVConstraintShift = InstFormatShift + 5,
188 VS2Constraint = 0b001 << RVVConstraintShift,
189 VS1Constraint = 0b010 << RVVConstraintShift,
190 VMConstraint = 0b100 << RVVConstraintShift,
191 RVVConstraintMask = 0b111 << RVVConstraintShift,
192
193 VLMulShift = RVVConstraintShift + 3,
194 VLMulMask = 0b111 << VLMulShift,
195
196 // Is this a _TIED vector pseudo instruction. For these instructions we
197 // shouldn't skip the tied operand when converting to MC instructions.
198 IsTiedPseudoShift = VLMulShift + 3,
199 IsTiedPseudoMask = 1 << IsTiedPseudoShift,
200
201 // Does this instruction have a SEW operand. It will be the last explicit
202 // operand unless there is a vector policy operand. Used by RVV Pseudos.
203 HasSEWOpShift = IsTiedPseudoShift + 1,
204 HasSEWOpMask = 1 << HasSEWOpShift,
205
206 // Does this instruction have a VL operand. It will be the second to last
207 // explicit operand unless there is a vector policy operand. Used by RVV
208 // Pseudos.
209 HasVLOpShift = HasSEWOpShift + 1,
210 HasVLOpMask = 1 << HasVLOpShift,
211
212 // Does this instruction have a vector policy operand. It will be the last
213 // explicit operand. Used by RVV Pseudos.
214 HasVecPolicyOpShift = HasVLOpShift + 1,
215 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
216
217 // Is this instruction a vector widening reduction instruction. Used by RVV
218 // Pseudos.
219 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
220 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
221
222 // Does this instruction care about mask policy. If it is not, the mask policy
223 // could be either agnostic or undisturbed. For example, unmasked, store, and
224 // reduction operations result would not be affected by mask policy, so
225 // compiler has free to select either one.
226 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
227 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
228
229 // Indicates that the result can be considered sign extended from bit 31. Some
230 // instructions with this flag aren't W instructions, but are either sign
231 // extended from a smaller size, always outputs a small integer, or put zeros
232 // in bits 63:31. Used by the SExtWRemoval pass.
233 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
234 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
235
236 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
237 HasRoundModeOpMask = 1 << HasRoundModeOpShift,
238
239 UsesVXRMShift = HasRoundModeOpShift + 1,
240 UsesVXRMMask = 1 << UsesVXRMShift,
241
242 // Indicates whether these instructions can partially overlap between source
243 // registers and destination registers according to the vector spec.
244 // 0 -> not a vector pseudo
245 // 1 -> default value for vector pseudos. not widening or narrowing.
246 // 2 -> narrowing case
247 // 3 -> widening case
248 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
249 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
250
251 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,
252 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,
253
254 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
255 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,
256
257 // Indicates the EEW of a vector instruction's destination operand.
258 // 0 -> 1
259 // 1 -> SEW
260 // 2 -> SEW * 2
261 // 3 -> SEW * 4
262 DestEEWShift = ElementsDependOnMaskShift + 1,
263 DestEEWMask = 3ULL << DestEEWShift,
264
265 ReadsPastVLShift = DestEEWShift + 2,
266 ReadsPastVLMask = 1ULL << ReadsPastVLShift,
267
268 // 0 -> Don't care about altfmt bit in VTYPE.
269 // 1 -> Is not altfmt.
270 // 2 -> Is altfmt(BF16).
271 AltFmtTypeShift = ReadsPastVLShift + 1,
272 AltFmtTypeMask = 3ULL << AltFmtTypeShift,
273
274 // XSfmmbase
275 HasTWidenOpShift = AltFmtTypeShift + 2,
276 HasTWidenOpMask = 1ULL << HasTWidenOpShift,
277
278 HasTMOpShift = HasTWidenOpShift + 1,
279 HasTMOpMask = 1ULL << HasTMOpShift,
280
281 HasTKOpShift = HasTMOpShift + 1,
282 HasTKOpMask = 1ULL << HasTKOpShift,
283};
284
285// Helper functions to read TSFlags.
286/// \returns the format of the instruction.
287static inline unsigned getFormat(uint64_t TSFlags) {
288 return (TSFlags & InstFormatMask) >> InstFormatShift;
289}
290/// \returns the LMUL for the instruction.
291static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
292 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
293}
294/// \returns true if this a _TIED pseudo.
295static inline bool isTiedPseudo(uint64_t TSFlags) {
296 return TSFlags & IsTiedPseudoMask;
297}
298/// \returns true if there is a SEW operand for the instruction.
299static inline bool hasSEWOp(uint64_t TSFlags) {
300 return TSFlags & HasSEWOpMask;
301}
302/// \returns true if there is a VL operand for the instruction.
303static inline bool hasVLOp(uint64_t TSFlags) {
304 return TSFlags & HasVLOpMask;
305}
306/// \returns true if there is a vector policy operand for this instruction.
307static inline bool hasVecPolicyOp(uint64_t TSFlags) {
308 return TSFlags & HasVecPolicyOpMask;
309}
310/// \returns true if it is a vector widening reduction instruction.
311static inline bool isRVVWideningReduction(uint64_t TSFlags) {
312 return TSFlags & IsRVVWideningReductionMask;
313}
314/// \returns true if mask policy is valid for the instruction.
315static inline bool usesMaskPolicy(uint64_t TSFlags) {
316 return TSFlags & UsesMaskPolicyMask;
317}
318
319/// \returns true if there is a rounding mode operand for this instruction
320static inline bool hasRoundModeOp(uint64_t TSFlags) {
321 return TSFlags & HasRoundModeOpMask;
322}
323
324enum class AltFmtType { DontCare, NotAltFmt, AltFmt };
325static inline AltFmtType getAltFmtType(uint64_t TSFlags) {
326 return static_cast<AltFmtType>((TSFlags & AltFmtTypeMask) >> AltFmtTypeShift);
327}
328
329/// \returns true if this instruction uses vxrm
330static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
331
332/// \returns true if the elements in the body are affected by VL,
333/// e.g. vslide1down.vx/vredsum.vs/viota.m
334static inline bool elementsDependOnVL(uint64_t TSFlags) {
335 return TSFlags & ElementsDependOnVLMask;
336}
337
338/// \returns true if the elements in the body are affected by the mask,
339/// e.g. vredsum.vs/viota.m
340static inline bool elementsDependOnMask(uint64_t TSFlags) {
341 return TSFlags & ElementsDependOnMaskMask;
342}
343
344/// \returns true if the instruction may read elements past VL, e.g.
345/// vslidedown/vrgather
346static inline bool readsPastVL(uint64_t TSFlags) {
347 return TSFlags & ReadsPastVLMask;
348}
349
350// XSfmmbase
351static inline bool hasTWidenOp(uint64_t TSFlags) {
352 return TSFlags & HasTWidenOpMask;
353}
354
355static inline bool hasTMOp(uint64_t TSFlags) { return TSFlags & HasTMOpMask; }
356
357static inline bool hasTKOp(uint64_t TSFlags) { return TSFlags & HasTKOpMask; }
358
359static inline unsigned getTWidenOpNum(const MCInstrDesc &Desc) {
360 assert(hasTWidenOp(Desc.TSFlags));
361 return Desc.getNumOperands() - 1;
362}
363
364static inline unsigned getTNOpNum(const MCInstrDesc &Desc) {
365 const uint64_t TSFlags = Desc.TSFlags;
366 assert(hasTWidenOp(TSFlags) && hasVLOp(TSFlags));
367 unsigned Offset = 3;
368 if (hasTKOp(TSFlags))
369 Offset = 4;
370 return Desc.getNumOperands() - Offset;
371}
372
373static inline unsigned getTMOpNum(const MCInstrDesc &Desc) {
374 const uint64_t TSFlags = Desc.TSFlags;
375 assert(hasTWidenOp(TSFlags) && hasTMOp(TSFlags));
376 if (hasTKOp(TSFlags))
377 return Desc.getNumOperands() - 5;
378 // vtzero.t
379 return Desc.getNumOperands() - 4;
380}
381
382static inline unsigned getTKOpNum(const MCInstrDesc &Desc) {
383 [[maybe_unused]] const uint64_t TSFlags = Desc.TSFlags;
384 assert(hasTWidenOp(TSFlags) && hasTKOp(TSFlags));
385 return Desc.getNumOperands() - 3;
386}
387
388static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
389 const uint64_t TSFlags = Desc.TSFlags;
390 // This method is only called if we expect to have a VL operand, and all
391 // instructions with VL also have SEW.
392 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
393 // In Xsfmmbase, TN is an alias for VL, so here we use the same TSFlags bit.
394 if (hasTWidenOp(TSFlags))
395 return getTNOpNum(Desc);
396 unsigned Offset = 2;
397 if (hasVecPolicyOp(TSFlags))
398 Offset = 3;
399 return Desc.getNumOperands() - Offset;
400}
401
402static inline MCRegister
403getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
404 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
405 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
406 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
407}
408
409static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
410 const uint64_t TSFlags = Desc.TSFlags;
411 assert(hasSEWOp(TSFlags));
412 unsigned Offset = 1;
413 if (hasVecPolicyOp(TSFlags) || hasTWidenOp(TSFlags))
414 Offset = 2;
415 return Desc.getNumOperands() - Offset;
416}
417
418static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
419 assert(hasVecPolicyOp(Desc.TSFlags));
420 return Desc.getNumOperands() - 1;
421}
422
423/// \returns the index to the rounding mode immediate value if any, otherwise
424/// returns -1.
425static inline int getFRMOpNum(const MCInstrDesc &Desc) {
426 const uint64_t TSFlags = Desc.TSFlags;
427 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
428 return -1;
429
430 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
431 assert(Idx >= 0 && "No rm operand?");
432 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
433 "Operand has wrong type");
434
435 return Idx;
436}
437
438/// \returns the index to the rounding mode immediate value if any, otherwise
439/// returns -1.
440static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
441 const uint64_t TSFlags = Desc.TSFlags;
442 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
443 return -1;
444
445 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
446 assert(Idx >= 0 && "No rm operand?");
447 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
448 "Operand has wrong type");
449
450 return Idx;
451}
452
453// Is the first def operand tied to the first use operand. This is true for
454// vector pseudo instructions that have a merge operand for tail/mask
455// undisturbed. It's also true for vector FMA instructions where one of the
456// operands is also the destination register.
457static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
458 return Desc.getNumDefs() < Desc.getNumOperands() &&
459 Desc.getOperandConstraint(OpNum: Desc.getNumDefs(), Constraint: MCOI::TIED_TO) == 0;
460}
461
462// RISC-V Specific Machine Operand Flags
463enum {
464 MO_None = 0,
465 MO_CALL = 1,
466 MO_LO = 3,
467 MO_HI = 4,
468 MO_PCREL_LO = 5,
469 MO_PCREL_HI = 6,
470 MO_GOT_HI = 7,
471 MO_TPREL_LO = 8,
472 MO_TPREL_HI = 9,
473 MO_TPREL_ADD = 10,
474 MO_TLS_GOT_HI = 11,
475 MO_TLS_GD_HI = 12,
476 MO_TLSDESC_HI = 13,
477 MO_TLSDESC_LOAD_LO = 14,
478 MO_TLSDESC_ADD_LO = 15,
479 MO_TLSDESC_CALL = 16,
480 MO_QC_ACCESS = 17,
481
482 // Used to differentiate between target-specific "direct" flags and "bitmask"
483 // flags. A machine operand can only have one "direct" flag, but can have
484 // multiple "bitmask" flags.
485 MO_DIRECT_FLAG_MASK = 31
486};
487} // namespace RISCVII
488
489// Describes the predecessor/successor bits used in the FENCE instruction.
490namespace RISCVFenceField {
491enum FenceField {
492 I = 8,
493 O = 4,
494 R = 2,
495 W = 1
496};
497}
498
499// Describes the supported floating point rounding mode encodings.
500namespace RISCVFPRndMode {
501enum RoundingMode {
502 RNE = 0,
503 RTZ = 1,
504 RDN = 2,
505 RUP = 3,
506 RMM = 4,
507 DYN = 7,
508 Invalid
509};
510
511inline static StringRef roundingModeToString(RoundingMode RndMode) {
512 switch (RndMode) {
513 default:
514 llvm_unreachable("Unknown floating point rounding mode");
515 case RISCVFPRndMode::RNE:
516 return "rne";
517 case RISCVFPRndMode::RTZ:
518 return "rtz";
519 case RISCVFPRndMode::RDN:
520 return "rdn";
521 case RISCVFPRndMode::RUP:
522 return "rup";
523 case RISCVFPRndMode::RMM:
524 return "rmm";
525 case RISCVFPRndMode::DYN:
526 return "dyn";
527 }
528}
529
530inline static RoundingMode stringToRoundingMode(StringRef Str) {
531 return StringSwitch<RoundingMode>(Str)
532 .Case(S: "rne", Value: RISCVFPRndMode::RNE)
533 .Case(S: "rtz", Value: RISCVFPRndMode::RTZ)
534 .Case(S: "rdn", Value: RISCVFPRndMode::RDN)
535 .Case(S: "rup", Value: RISCVFPRndMode::RUP)
536 .Case(S: "rmm", Value: RISCVFPRndMode::RMM)
537 .Case(S: "dyn", Value: RISCVFPRndMode::DYN)
538 .Default(Value: RISCVFPRndMode::Invalid);
539}
540
541inline static bool isValidRoundingMode(unsigned Mode) {
542 switch (Mode) {
543 default:
544 return false;
545 case RISCVFPRndMode::RNE:
546 case RISCVFPRndMode::RTZ:
547 case RISCVFPRndMode::RDN:
548 case RISCVFPRndMode::RUP:
549 case RISCVFPRndMode::RMM:
550 case RISCVFPRndMode::DYN:
551 return true;
552 }
553}
554} // namespace RISCVFPRndMode
555
556namespace RISCVVXRndMode {
557enum RoundingMode {
558 RNU = 0,
559 RNE = 1,
560 RDN = 2,
561 ROD = 3,
562 Invalid
563};
564
565inline static StringRef roundingModeToString(RoundingMode RndMode) {
566 switch (RndMode) {
567 default:
568 llvm_unreachable("Unknown vector fixed-point rounding mode");
569 case RISCVVXRndMode::RNU:
570 return "rnu";
571 case RISCVVXRndMode::RNE:
572 return "rne";
573 case RISCVVXRndMode::RDN:
574 return "rdn";
575 case RISCVVXRndMode::ROD:
576 return "rod";
577 }
578}
579
580inline static RoundingMode stringToRoundingMode(StringRef Str) {
581 return StringSwitch<RoundingMode>(Str)
582 .Case(S: "rnu", Value: RISCVVXRndMode::RNU)
583 .Case(S: "rne", Value: RISCVVXRndMode::RNE)
584 .Case(S: "rdn", Value: RISCVVXRndMode::RDN)
585 .Case(S: "rod", Value: RISCVVXRndMode::ROD)
586 .Default(Value: RISCVVXRndMode::Invalid);
587}
588
589inline static bool isValidRoundingMode(unsigned Mode) {
590 switch (Mode) {
591 default:
592 return false;
593 case RISCVVXRndMode::RNU:
594 case RISCVVXRndMode::RNE:
595 case RISCVVXRndMode::RDN:
596 case RISCVVXRndMode::ROD:
597 return true;
598 }
599}
600} // namespace RISCVVXRndMode
601
602namespace RISCVExceptFlags {
603enum ExceptionFlag {
604 NX = 0x01, // Inexact
605 UF = 0x02, // Underflow
606 OF = 0x04, // Overflow
607 DZ = 0x08, // Divide by zero
608 NV = 0x10, // Invalid operation
609 ALL = 0x1F // Mask for all accrued exception flags
610};
611}
612
613//===----------------------------------------------------------------------===//
614// Floating-point Immediates
615//
616
617namespace RISCVLoadFPImm {
618float getFPImm(unsigned Imm);
619
620/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
621/// immediate value. If the value cannot be represented as a 5-bit binary
622/// encoding, then return -1.
623int getLoadFPImm(APFloat FPImm);
624} // namespace RISCVLoadFPImm
625
626namespace RISCVSysReg {
627struct SysReg {
628 StringTable::Offset Name;
629 unsigned Encoding;
630 // FIXME: add these additional fields when needed.
631 // Privilege Access: Read, Write, Read-Only.
632 // unsigned ReadWrite;
633 // Privilege Mode: User, System or Machine.
634 // unsigned Mode;
635 // Check field name.
636 // unsigned Extra;
637 // Register number without the privilege bits.
638 // unsigned Number;
639 FeatureBitset FeaturesRequired;
640 bool IsRV32Only;
641 bool IsAltName;
642 bool IsDeprecatedName;
643
644 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
645 // Not in 32-bit mode.
646 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
647 return false;
648 // No required feature associated with the system register.
649 if (FeaturesRequired.none())
650 return true;
651 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
652 }
653};
654
655#define GET_SysRegEncodings_DECL
656#define GET_SysRegsList_DECL
657#include "RISCVGenSearchableTables.inc"
658} // end namespace RISCVSysReg
659
660namespace RISCVInsnOpcode {
661struct RISCVOpcode {
662 StringTable::Offset Name;
663 uint8_t Value;
664};
665
666#define GET_RISCVOpcodesList_DECL
667#include "RISCVGenSearchableTables.inc"
668} // end namespace RISCVInsnOpcode
669
670namespace RISCVABI {
671
672enum ABI {
673 ABI_ILP32,
674 ABI_ILP32F,
675 ABI_ILP32D,
676 ABI_ILP32E,
677 ABI_IL32PC64,
678 ABI_IL32PC64F,
679 ABI_IL32PC64D,
680 ABI_IL32PC64E,
681 ABI_LP64,
682 ABI_LP64F,
683 ABI_LP64D,
684 ABI_LP64E,
685 ABI_L64PC128,
686 ABI_L64PC128F,
687 ABI_L64PC128D,
688 ABI_CHERIOT,
689 ABI_Unknown
690};
691
692// Returns the target ABI, or else a StringError if the requested ABIName is
693// not supported for the subtargets triple and FeatureBits combination.
694ABI computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName);
695
696ABI getTargetABI(StringRef ABIName);
697
698// Returns the register used to hold the stack pointer after realignment.
699MCRegister getBPReg();
700
701// Returns the register holding shadow call stack pointer.
702MCRegister getSCSPReg();
703
704} // namespace RISCVABI
705
706namespace RISCVFeatures {
707
708// Validates if the given combination of features are valid for the target
709// triple. Exits with report_fatal_error if not.
710void validate(const Triple &TT, const FeatureBitset &FeatureBits);
711
712llvm::Expected<std::unique_ptr<RISCVISAInfo>>
713parseFeatureBits(const MCSubtargetInfo &STI);
714
715} // namespace RISCVFeatures
716
717namespace RISCVRVC {
718bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
719bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
720} // namespace RISCVRVC
721
722namespace RISCVZC {
723enum RLISTENCODE {
724 RA = 4,
725 RA_S0,
726 RA_S0_S1,
727 RA_S0_S2,
728 RA_S0_S3,
729 RA_S0_S4,
730 RA_S0_S5,
731 RA_S0_S6,
732 RA_S0_S7,
733 RA_S0_S8,
734 RA_S0_S9,
735 // note - to include s10, s11 must also be included
736 RA_S0_S11,
737 INVALID_RLIST,
738};
739
740inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
741 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
742 switch (EndReg.id()) {
743 case RISCV::X1:
744 return RLISTENCODE::RA;
745 case RISCV::X8:
746 return RLISTENCODE::RA_S0;
747 case RISCV::X9:
748 return RLISTENCODE::RA_S0_S1;
749 case RISCV::X18:
750 return RLISTENCODE::RA_S0_S2;
751 case RISCV::X19:
752 return RLISTENCODE::RA_S0_S3;
753 case RISCV::X20:
754 return RLISTENCODE::RA_S0_S4;
755 case RISCV::X21:
756 return RLISTENCODE::RA_S0_S5;
757 case RISCV::X22:
758 return RLISTENCODE::RA_S0_S6;
759 case RISCV::X23:
760 return RLISTENCODE::RA_S0_S7;
761 case RISCV::X24:
762 return RLISTENCODE::RA_S0_S8;
763 case RISCV::X25:
764 return RLISTENCODE::RA_S0_S9;
765 case RISCV::X27:
766 return RLISTENCODE::RA_S0_S11;
767 default:
768 llvm_unreachable("Undefined input.");
769 }
770}
771
772inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
773 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
774 "Unexpected number of registers");
775 if (NumRegs == 13)
776 return RLISTENCODE::RA_S0_S11;
777
778 return RLISTENCODE::RA + (NumRegs - 1);
779}
780
781inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
782 assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&
783 "Invalid Rlist");
784 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;
785 // s10 and s11 are saved together.
786 if (RlistVal == RLISTENCODE::RA_S0_S11)
787 ++NumRegs;
788
789 unsigned RegSize = IsRV64 ? 8 : 4;
790 return alignTo(Value: NumRegs * RegSize, Align: 16);
791}
792
793void printRegList(unsigned RlistEncode, raw_ostream &OS);
794} // namespace RISCVZC
795
796namespace RISCVVInversePseudosTable {
797struct PseudoInfo {
798 uint16_t Pseudo;
799 uint16_t BaseInstr;
800 uint16_t VLMul : 3;
801 uint16_t SEW : 8;
802 uint16_t IsAltFmt : 1;
803};
804
805#define GET_RISCVVInversePseudosTable_DECL
806#include "RISCVGenSearchableTables.inc"
807
808inline const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul,
809 uint8_t SEW, bool IsAltFmt = false) {
810 return getBaseInfoImpl(BaseInstr, VLMul, SEW, IsAltFmt);
811}
812} // namespace RISCVVInversePseudosTable
813
814namespace RISCV {
815struct VLSEGPseudo {
816 uint16_t NF : 4;
817 uint16_t Masked : 1;
818 uint16_t Strided : 1;
819 uint16_t FF : 1;
820 uint16_t Log2SEW : 3;
821 uint16_t LMUL : 3;
822 uint16_t Pseudo;
823};
824
825struct VLXSEGPseudo {
826 uint16_t NF : 4;
827 uint16_t Masked : 1;
828 uint16_t Ordered : 1;
829 uint16_t Log2SEW : 3;
830 uint16_t LMUL : 3;
831 uint16_t IndexLMUL : 3;
832 uint16_t Pseudo;
833};
834
835struct VSSEGPseudo {
836 uint16_t NF : 4;
837 uint16_t Masked : 1;
838 uint16_t Strided : 1;
839 uint16_t Log2SEW : 3;
840 uint16_t LMUL : 3;
841 uint16_t Pseudo;
842};
843
844struct VSXSEGPseudo {
845 uint16_t NF : 4;
846 uint16_t Masked : 1;
847 uint16_t Ordered : 1;
848 uint16_t Log2SEW : 3;
849 uint16_t LMUL : 3;
850 uint16_t IndexLMUL : 3;
851 uint16_t Pseudo;
852};
853
854struct VLEPseudo {
855 uint16_t Masked : 1;
856 uint16_t Strided : 1;
857 uint16_t FF : 1;
858 uint16_t Log2SEW : 3;
859 uint16_t LMUL : 3;
860 uint16_t Pseudo;
861};
862
863struct VSEPseudo {
864 uint16_t Masked : 1;
865 uint16_t Strided : 1;
866 uint16_t Log2SEW : 3;
867 uint16_t LMUL : 3;
868 uint16_t Pseudo;
869};
870
871struct VLX_VSXPseudo {
872 uint16_t Masked : 1;
873 uint16_t Ordered : 1;
874 uint16_t Log2SEW : 3;
875 uint16_t LMUL : 3;
876 uint16_t IndexLMUL : 3;
877 uint16_t Pseudo;
878};
879
880struct NDSVLNPseudo {
881 uint16_t Masked : 1;
882 uint16_t Unsigned : 1;
883 uint16_t Log2SEW : 3;
884 uint16_t LMUL : 3;
885 uint16_t Pseudo;
886};
887
888#define GET_RISCVVSSEGTable_DECL
889#define GET_RISCVVLSEGTable_DECL
890#define GET_RISCVVLXSEGTable_DECL
891#define GET_RISCVVSXSEGTable_DECL
892#define GET_RISCVVLETable_DECL
893#define GET_RISCVVSETable_DECL
894#define GET_RISCVVLXTable_DECL
895#define GET_RISCVVSXTable_DECL
896#define GET_RISCVNDSVLNTable_DECL
897#include "RISCVGenSearchableTables.inc"
898
899inline bool isValidYBNDSWImm(int64_t Imm) {
900 return (Imm >= 1 && Imm <= 255) ||
901 (Imm >= 256 && Imm <= 504 && (Imm % 8) == 0) ||
902 (Imm >= 512 && Imm <= 4096 && (Imm % 16) == 0);
903}
904} // namespace RISCV
905
906} // namespace llvm
907
908#endif
909