1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/ADT/StringTable.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/TargetParser/RISCVISAInfo.h"
24#include "llvm/TargetParser/RISCVTargetParser.h"
25#include "llvm/TargetParser/SubtargetFeature.h"
26
27namespace llvm {
28
29class MCSubtargetInfo;
30
31namespace RISCVOp {
32enum OperandType : unsigned {
33 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
34 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
35 OPERAND_UIMM2,
36 OPERAND_UIMM2_LSB0,
37 OPERAND_UIMM3,
38 OPERAND_UIMM4,
39 OPERAND_UIMM4_PLUS1,
40 OPERAND_UIMM5,
41 OPERAND_UIMM5_NONZERO,
42 OPERAND_UIMM5_GT3,
43 OPERAND_UIMM5_PLUS1,
44 OPERAND_UIMM5_GE6_PLUS1,
45 OPERAND_UIMM5_LSB0,
46 OPERAND_UIMM5_SLIST,
47 OPERAND_UIMM6,
48 OPERAND_UIMM6_PLUS1,
49 OPERAND_UIMM6_LSB0,
50 OPERAND_UIMM6_LSB000,
51 OPERAND_UIMM7,
52 OPERAND_UIMM7_LSB00,
53 OPERAND_UIMM7_LSB000,
54 OPERAND_UIMM7_EQ_XLEN,
55 OPERAND_UIMM8_LSB00,
56 OPERAND_UIMM8,
57 OPERAND_UIMM8_LSB000,
58 OPERAND_UIMM8_GE32,
59 OPERAND_UIMM9,
60 OPERAND_UIMM9_LSB000,
61 OPERAND_UIMM9_YBNDSWI,
62 OPERAND_UIMM10,
63 OPERAND_UIMM10_LSB00_NONZERO,
64 OPERAND_UIMM11,
65 OPERAND_UIMM12,
66 OPERAND_UIMM14_LSB00,
67 OPERAND_UIMM16,
68 OPERAND_UIMM16_NONZERO,
69 OPERAND_UIMMLOG2XLEN,
70 OPERAND_UIMMLOG2XLEN_NONZERO,
71 OPERAND_UIMM32,
72 OPERAND_UIMM48,
73 OPERAND_UIMM64,
74 OPERAND_THREE,
75 OPERAND_FOUR,
76 OPERAND_IMM5_ZIBI,
77 OPERAND_SIMM5,
78 OPERAND_SIMM5_NONZERO,
79 OPERAND_SIMM5_PLUS1,
80 OPERAND_SIMM6,
81 OPERAND_SIMM6_NONZERO,
82 OPERAND_SIMM8,
83 OPERAND_SIMM10,
84 OPERAND_SIMM10_LSB0000_NONZERO,
85 OPERAND_SIMM10_UNSIGNED,
86 OPERAND_SIMM11,
87 OPERAND_SIMM12,
88 OPERAND_SIMM12_LSB00000,
89 OPERAND_SIMM16,
90 OPERAND_SIMM16_NONZERO,
91 OPERAND_SIMM20,
92 OPERAND_SIMM20_LI,
93 OPERAND_SIMM26,
94 OPERAND_CLUI_IMM,
95 OPERAND_VTYPEI10,
96 OPERAND_VTYPEI11,
97 OPERAND_RVKRNUM,
98 OPERAND_RVKRNUM_0_7,
99 OPERAND_RVKRNUM_1_10,
100 OPERAND_RVKRNUM_2_14,
101 OPERAND_RLIST,
102 OPERAND_RLIST_S0,
103 OPERAND_STACKADJ,
104 // Operand is a 3-bit rounding mode, '111' indicates FRM register.
105 // Represents 'frm' argument passing to floating-point operations.
106 OPERAND_FRMARG,
107 // Operand is a 3-bit rounding mode where only RTZ is valid.
108 OPERAND_RTZARG,
109 // Condition code used by select and short forward branch pseudos.
110 OPERAND_COND_CODE,
111 // Ordering for atomic pseudos.
112 OPERAND_ATOMIC_ORDERING,
113 // Vector policy operand.
114 OPERAND_VEC_POLICY,
115 // Vector SEW operand. Stores in log2(SEW).
116 OPERAND_SEW,
117 // Special SEW for mask only instructions. Always 0.
118 OPERAND_SEW_MASK,
119 // Vector rounding mode for VXRM or FRM.
120 OPERAND_VEC_RM,
121 // Vtype operand for XSfmm extension.
122 OPERAND_XSFMM_VTYPE,
123 // XSfmm twiden operand.
124 OPERAND_XSFMM_TWIDEN,
125 OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_TWIDEN,
126
127 OPERAND_UIMM20_LUI,
128 OPERAND_UIMM20_AUIPC,
129
130 // Simm12 or constant pool, global, basicblock, etc.
131 OPERAND_SIMM12_LO,
132
133 OPERAND_BARE_SIMM32,
134
135 // Operand is either a register or uimm5, this is used by V extension pseudo
136 // instructions to represent a value that be passed as AVL to either vsetvli
137 // or vsetivli.
138 OPERAND_AVL,
139
140 // Operand is either a register or imm, this is used by short forward branch
141 // (SFB) pseudos to enable SFB with branches on reg-reg and reg-imm compares.
142 OPERAND_SFB_RHS,
143
144 // Operand is a branch opcode, this too is used by SFB pseudos.
145 OPERAND_BCC_OPCODE,
146
147 OPERAND_VMASK,
148 OPERAND_SMTVType,
149 OPERAND_SMTI8,
150};
151} // namespace RISCVOp
152
153// RISCVII - This namespace holds all of the target specific flags that
154// instruction info tracks. All definitions must match RISCVInstrFormats.td.
155namespace RISCVII {
156enum : uint64_t {
157 InstFormatPseudo = 0,
158 InstFormatR = 1,
159 InstFormatR4 = 2,
160 InstFormatI = 3,
161 InstFormatS = 4,
162 InstFormatB = 5,
163 InstFormatU = 6,
164 InstFormatJ = 7,
165 InstFormatCR = 8,
166 InstFormatCI = 9,
167 InstFormatCSS = 10,
168 InstFormatCIW = 11,
169 InstFormatCL = 12,
170 InstFormatCS = 13,
171 InstFormatCA = 14,
172 InstFormatCB = 15,
173 InstFormatCJ = 16,
174 InstFormatCU = 17,
175 InstFormatCLB = 18,
176 InstFormatCLH = 19,
177 InstFormatCSB = 20,
178 InstFormatCSH = 21,
179 InstFormatQC_EAI = 22,
180 InstFormatQC_EI = 23,
181 InstFormatQC_EB = 24,
182 InstFormatQC_EJ = 25,
183 InstFormatQC_ES = 26,
184 InstFormatNDS_BRANCH_10 = 27,
185 InstFormatOther = 31,
186
187 InstFormatMask = 31,
188 InstFormatShift = 0,
189
190 RVVConstraintShift = InstFormatShift + 5,
191 VS2Constraint = 0b001 << RVVConstraintShift,
192 VS1Constraint = 0b010 << RVVConstraintShift,
193 VMConstraint = 0b100 << RVVConstraintShift,
194 RVVConstraintMask = 0b111 << RVVConstraintShift,
195
196 VLMulShift = RVVConstraintShift + 3,
197 VLMulMask = 0b111 << VLMulShift,
198
199 // Is this a _TIED vector pseudo instruction. For these instructions we
200 // shouldn't skip the tied operand when converting to MC instructions.
201 IsTiedPseudoShift = VLMulShift + 3,
202 IsTiedPseudoMask = 1 << IsTiedPseudoShift,
203
204 // Does this instruction have a SEW operand. It will be the last explicit
205 // operand unless there is a vector policy operand. Used by RVV Pseudos.
206 HasSEWOpShift = IsTiedPseudoShift + 1,
207 HasSEWOpMask = 1 << HasSEWOpShift,
208
209 // Does this instruction have a VL operand. It will be the second to last
210 // explicit operand unless there is a vector policy operand. Used by RVV
211 // Pseudos.
212 HasVLOpShift = HasSEWOpShift + 1,
213 HasVLOpMask = 1 << HasVLOpShift,
214
215 // Does this instruction have a vector policy operand. It will be the last
216 // explicit operand. Used by RVV Pseudos.
217 HasVecPolicyOpShift = HasVLOpShift + 1,
218 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
219
220 // Is this instruction a vector widening reduction instruction. Used by RVV
221 // Pseudos.
222 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
223 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
224
225 // Does this instruction care about mask policy. If it is not, the mask policy
226 // could be either agnostic or undisturbed. For example, unmasked, store, and
227 // reduction operations result would not be affected by mask policy, so
228 // compiler has free to select either one.
229 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
230 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
231
232 // Indicates that the result can be considered sign extended from bit 31. Some
233 // instructions with this flag aren't W instructions, but are either sign
234 // extended from a smaller size, always outputs a small integer, or put zeros
235 // in bits 63:31. Used by the SExtWRemoval pass.
236 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
237 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
238
239 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
240 HasRoundModeOpMask = 1 << HasRoundModeOpShift,
241
242 UsesVXRMShift = HasRoundModeOpShift + 1,
243 UsesVXRMMask = 1 << UsesVXRMShift,
244
245 // Indicates whether these instructions can partially overlap between source
246 // registers and destination registers according to the vector spec.
247 // 0 -> not a vector pseudo
248 // 1 -> default value for vector pseudos. not widening or narrowing.
249 // 2 -> narrowing case
250 // 3 -> widening case
251 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
252 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
253
254 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,
255 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,
256
257 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
258 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,
259
260 // Indicates the EEW of a vector instruction's destination operand.
261 // 0 -> 1
262 // 1 -> SEW
263 // 2 -> SEW * 2
264 // 3 -> SEW * 4
265 DestEEWShift = ElementsDependOnMaskShift + 1,
266 DestEEWMask = 3ULL << DestEEWShift,
267
268 ReadsPastVLShift = DestEEWShift + 2,
269 ReadsPastVLMask = 1ULL << ReadsPastVLShift,
270
271 // 0 -> Don't care about altfmt bit in VTYPE.
272 // 1 -> Is not altfmt.
273 // 2 -> Is altfmt(BF16).
274 AltFmtTypeShift = ReadsPastVLShift + 1,
275 AltFmtTypeMask = 3ULL << AltFmtTypeShift,
276
277 // XSfmmbase
278 HasTWidenOpShift = AltFmtTypeShift + 2,
279 HasTWidenOpMask = 1ULL << HasTWidenOpShift,
280
281 HasTMOpShift = HasTWidenOpShift + 1,
282 HasTMOpMask = 1ULL << HasTMOpShift,
283
284 HasTKOpShift = HasTMOpShift + 1,
285 HasTKOpMask = 1ULL << HasTKOpShift,
286
287 SMTConstraintShift = HasTKOpShift + 1,
288 SMTConstraintMask = 1ULL << SMTConstraintShift,
289};
290
291// Helper functions to read TSFlags.
292/// \returns the format of the instruction.
293static inline unsigned getFormat(uint64_t TSFlags) {
294 return (TSFlags & InstFormatMask) >> InstFormatShift;
295}
296/// \returns the LMUL for the instruction.
297static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
298 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
299}
300/// \returns true if this a _TIED pseudo.
301static inline bool isTiedPseudo(uint64_t TSFlags) {
302 return TSFlags & IsTiedPseudoMask;
303}
304/// \returns true if there is a SEW operand for the instruction.
305static inline bool hasSEWOp(uint64_t TSFlags) {
306 return TSFlags & HasSEWOpMask;
307}
308/// \returns true if there is a VL operand for the instruction.
309static inline bool hasVLOp(uint64_t TSFlags) {
310 return TSFlags & HasVLOpMask;
311}
312/// \returns true if there is a vector policy operand for this instruction.
313static inline bool hasVecPolicyOp(uint64_t TSFlags) {
314 return TSFlags & HasVecPolicyOpMask;
315}
316/// \returns true if it is a vector widening reduction instruction.
317static inline bool isRVVWideningReduction(uint64_t TSFlags) {
318 return TSFlags & IsRVVWideningReductionMask;
319}
320/// \returns true if mask policy is valid for the instruction.
321static inline bool usesMaskPolicy(uint64_t TSFlags) {
322 return TSFlags & UsesMaskPolicyMask;
323}
324
325/// \returns true if there is a rounding mode operand for this instruction
326static inline bool hasRoundModeOp(uint64_t TSFlags) {
327 return TSFlags & HasRoundModeOpMask;
328}
329
330enum class AltFmtType { DontCare, NotAltFmt, AltFmt };
331static inline AltFmtType getAltFmtType(uint64_t TSFlags) {
332 return static_cast<AltFmtType>((TSFlags & AltFmtTypeMask) >> AltFmtTypeShift);
333}
334
335/// \returns true if this instruction uses vxrm
336static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
337
338/// \returns true if the elements in the body are affected by VL,
339/// e.g. vslide1down.vx/vredsum.vs/viota.m
340static inline bool elementsDependOnVL(uint64_t TSFlags) {
341 return TSFlags & ElementsDependOnVLMask;
342}
343
344/// \returns true if the elements in the body are affected by the mask,
345/// e.g. vredsum.vs/viota.m
346static inline bool elementsDependOnMask(uint64_t TSFlags) {
347 return TSFlags & ElementsDependOnMaskMask;
348}
349
350/// \returns true if the instruction may read elements past VL, e.g.
351/// vslidedown/vrgather
352static inline bool readsPastVL(uint64_t TSFlags) {
353 return TSFlags & ReadsPastVLMask;
354}
355
356// XSfmmbase
357static inline bool hasTWidenOp(uint64_t TSFlags) {
358 return TSFlags & HasTWidenOpMask;
359}
360
361static inline bool hasTMOp(uint64_t TSFlags) { return TSFlags & HasTMOpMask; }
362
363static inline bool hasTKOp(uint64_t TSFlags) { return TSFlags & HasTKOpMask; }
364
365static inline unsigned getTWidenOpNum(const MCInstrDesc &Desc) {
366 assert(hasTWidenOp(Desc.TSFlags));
367 return Desc.getNumOperands() - 1;
368}
369
370static inline unsigned getTNOpNum(const MCInstrDesc &Desc) {
371 const uint64_t TSFlags = Desc.TSFlags;
372 assert(hasTWidenOp(TSFlags) && hasVLOp(TSFlags));
373 unsigned Offset = 3;
374 if (hasTKOp(TSFlags))
375 Offset = 4;
376 return Desc.getNumOperands() - Offset;
377}
378
379static inline unsigned getTMOpNum(const MCInstrDesc &Desc) {
380 const uint64_t TSFlags = Desc.TSFlags;
381 assert(hasTWidenOp(TSFlags) && hasTMOp(TSFlags));
382 if (hasTKOp(TSFlags))
383 return Desc.getNumOperands() - 5;
384 // vtzero.t
385 return Desc.getNumOperands() - 4;
386}
387
388static inline unsigned getTKOpNum(const MCInstrDesc &Desc) {
389 [[maybe_unused]] const uint64_t TSFlags = Desc.TSFlags;
390 assert(hasTWidenOp(TSFlags) && hasTKOp(TSFlags));
391 return Desc.getNumOperands() - 3;
392}
393
394static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
395 const uint64_t TSFlags = Desc.TSFlags;
396 // This method is only called if we expect to have a VL operand, and all
397 // instructions with VL also have SEW.
398 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
399 // In Xsfmmbase, TN is an alias for VL, so here we use the same TSFlags bit.
400 if (hasTWidenOp(TSFlags))
401 return getTNOpNum(Desc);
402 unsigned Offset = 2;
403 if (hasVecPolicyOp(TSFlags))
404 Offset = 3;
405 return Desc.getNumOperands() - Offset;
406}
407
408static inline MCRegister
409getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
410 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
411 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
412 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
413}
414
415static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
416 const uint64_t TSFlags = Desc.TSFlags;
417 assert(hasSEWOp(TSFlags));
418 unsigned Offset = 1;
419 if (hasVecPolicyOp(TSFlags) || hasTWidenOp(TSFlags))
420 Offset = 2;
421 return Desc.getNumOperands() - Offset;
422}
423
424static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
425 assert(hasVecPolicyOp(Desc.TSFlags));
426 return Desc.getNumOperands() - 1;
427}
428
429/// \returns the index to the rounding mode immediate value if any, otherwise
430/// returns -1.
431static inline int getFRMOpNum(const MCInstrDesc &Desc) {
432 const uint64_t TSFlags = Desc.TSFlags;
433 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
434 return -1;
435
436 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
437 assert(Idx >= 0 && "No rm operand?");
438 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
439 "Operand has wrong type");
440
441 return Idx;
442}
443
444/// \returns the index to the rounding mode immediate value if any, otherwise
445/// returns -1.
446static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
447 const uint64_t TSFlags = Desc.TSFlags;
448 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
449 return -1;
450
451 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
452 assert(Idx >= 0 && "No rm operand?");
453 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
454 "Operand has wrong type");
455
456 return Idx;
457}
458
459// Is the first def operand tied to the first use operand. This is true for
460// vector pseudo instructions that have a merge operand for tail/mask
461// undisturbed. It's also true for vector FMA instructions where one of the
462// operands is also the destination register.
463static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
464 return Desc.getNumDefs() < Desc.getNumOperands() &&
465 Desc.getOperandConstraint(OpNum: Desc.getNumDefs(), Constraint: MCOI::TIED_TO) == 0;
466}
467
468// RISC-V Specific Machine Operand Flags
469enum {
470 MO_None = 0,
471 MO_CALL = 1,
472 MO_LO = 3,
473 MO_HI = 4,
474 MO_PCREL_LO = 5,
475 MO_PCREL_HI = 6,
476 MO_GOT_HI = 7,
477 MO_TPREL_LO = 8,
478 MO_TPREL_HI = 9,
479 MO_TPREL_ADD = 10,
480 MO_TLS_GOT_HI = 11,
481 MO_TLS_GD_HI = 12,
482 MO_TLSDESC_HI = 13,
483 MO_TLSDESC_LOAD_LO = 14,
484 MO_TLSDESC_ADD_LO = 15,
485 MO_TLSDESC_CALL = 16,
486 MO_QC_ACCESS = 17,
487
488 // Used to differentiate between target-specific "direct" flags and "bitmask"
489 // flags. A machine operand can only have one "direct" flag, but can have
490 // multiple "bitmask" flags.
491 MO_DIRECT_FLAG_MASK = 31
492};
493} // namespace RISCVII
494
495// Describes the predecessor/successor bits used in the FENCE instruction.
496namespace RISCVFenceField {
497enum FenceField {
498 I = 8,
499 O = 4,
500 R = 2,
501 W = 1
502};
503}
504
505// Describes the supported floating point rounding mode encodings.
506namespace RISCVFPRndMode {
507enum RoundingMode {
508 RNE = 0,
509 RTZ = 1,
510 RDN = 2,
511 RUP = 3,
512 RMM = 4,
513 DYN = 7,
514 Invalid
515};
516
517inline static StringRef roundingModeToString(RoundingMode RndMode) {
518 switch (RndMode) {
519 default:
520 llvm_unreachable("Unknown floating point rounding mode");
521 case RISCVFPRndMode::RNE:
522 return "rne";
523 case RISCVFPRndMode::RTZ:
524 return "rtz";
525 case RISCVFPRndMode::RDN:
526 return "rdn";
527 case RISCVFPRndMode::RUP:
528 return "rup";
529 case RISCVFPRndMode::RMM:
530 return "rmm";
531 case RISCVFPRndMode::DYN:
532 return "dyn";
533 }
534}
535
536inline static RoundingMode stringToRoundingMode(StringRef Str) {
537 return StringSwitch<RoundingMode>(Str)
538 .Case(S: "rne", Value: RISCVFPRndMode::RNE)
539 .Case(S: "rtz", Value: RISCVFPRndMode::RTZ)
540 .Case(S: "rdn", Value: RISCVFPRndMode::RDN)
541 .Case(S: "rup", Value: RISCVFPRndMode::RUP)
542 .Case(S: "rmm", Value: RISCVFPRndMode::RMM)
543 .Case(S: "dyn", Value: RISCVFPRndMode::DYN)
544 .Default(Value: RISCVFPRndMode::Invalid);
545}
546
547inline static bool isValidRoundingMode(unsigned Mode) {
548 switch (Mode) {
549 default:
550 return false;
551 case RISCVFPRndMode::RNE:
552 case RISCVFPRndMode::RTZ:
553 case RISCVFPRndMode::RDN:
554 case RISCVFPRndMode::RUP:
555 case RISCVFPRndMode::RMM:
556 case RISCVFPRndMode::DYN:
557 return true;
558 }
559}
560} // namespace RISCVFPRndMode
561
562namespace XSMTVTypeMode {
563enum SMTVTypeMode {
564 // Define the different SMT VType modes here
565 SMT_I4 = 2,
566 SMT_I8 = 3,
567 Invalid
568};
569
570inline static StringRef SMTVTypeModeToString(SMTVTypeMode TypeMode) {
571 switch (TypeMode) {
572 default:
573 llvm_unreachable("Unknown VType mode of SpacemiT Integer Matrix");
574 case XSMTVTypeMode::SMT_I4:
575 return "i4";
576 case XSMTVTypeMode::SMT_I8:
577 return "i8";
578 }
579}
580
581inline static SMTVTypeMode stringToSMTVTypeMode(StringRef Str) {
582 return StringSwitch<SMTVTypeMode>(Str)
583 .Case(S: "i4", Value: XSMTVTypeMode::SMT_I4)
584 .Case(S: "i8", Value: XSMTVTypeMode::SMT_I8)
585 .Default(Value: XSMTVTypeMode::Invalid);
586}
587
588inline static bool isValidSMTVTypeMode(unsigned Mode) {
589 switch (Mode) {
590 default:
591 return false;
592 case XSMTVTypeMode::SMT_I4:
593 case XSMTVTypeMode::SMT_I8:
594 return true;
595 }
596}
597
598} // namespace XSMTVTypeMode
599
600namespace RISCVVXRndMode {
601enum RoundingMode {
602 RNU = 0,
603 RNE = 1,
604 RDN = 2,
605 ROD = 3,
606 Invalid
607};
608
609inline static StringRef roundingModeToString(RoundingMode RndMode) {
610 switch (RndMode) {
611 default:
612 llvm_unreachable("Unknown vector fixed-point rounding mode");
613 case RISCVVXRndMode::RNU:
614 return "rnu";
615 case RISCVVXRndMode::RNE:
616 return "rne";
617 case RISCVVXRndMode::RDN:
618 return "rdn";
619 case RISCVVXRndMode::ROD:
620 return "rod";
621 }
622}
623
624inline static RoundingMode stringToRoundingMode(StringRef Str) {
625 return StringSwitch<RoundingMode>(Str)
626 .Case(S: "rnu", Value: RISCVVXRndMode::RNU)
627 .Case(S: "rne", Value: RISCVVXRndMode::RNE)
628 .Case(S: "rdn", Value: RISCVVXRndMode::RDN)
629 .Case(S: "rod", Value: RISCVVXRndMode::ROD)
630 .Default(Value: RISCVVXRndMode::Invalid);
631}
632
633inline static bool isValidRoundingMode(unsigned Mode) {
634 switch (Mode) {
635 default:
636 return false;
637 case RISCVVXRndMode::RNU:
638 case RISCVVXRndMode::RNE:
639 case RISCVVXRndMode::RDN:
640 case RISCVVXRndMode::ROD:
641 return true;
642 }
643}
644} // namespace RISCVVXRndMode
645
646namespace RISCVExceptFlags {
647enum ExceptionFlag {
648 NX = 0x01, // Inexact
649 UF = 0x02, // Underflow
650 OF = 0x04, // Overflow
651 DZ = 0x08, // Divide by zero
652 NV = 0x10, // Invalid operation
653 ALL = 0x1F // Mask for all accrued exception flags
654};
655}
656
657//===----------------------------------------------------------------------===//
658// Floating-point Immediates
659//
660
661namespace RISCVLoadFPImm {
662float getFPImm(unsigned Imm);
663
664/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
665/// immediate value. If the value cannot be represented as a 5-bit binary
666/// encoding, then return -1.
667int getLoadFPImm(APFloat FPImm);
668} // namespace RISCVLoadFPImm
669
670namespace RISCVSysReg {
671struct SysReg {
672 StringTable::Offset Name;
673 unsigned Encoding;
674 // FIXME: add these additional fields when needed.
675 // Privilege Access: Read, Write, Read-Only.
676 // unsigned ReadWrite;
677 // Privilege Mode: User, System or Machine.
678 // unsigned Mode;
679 // Check field name.
680 // unsigned Extra;
681 // Register number without the privilege bits.
682 // unsigned Number;
683 FeatureBitset FeaturesRequired;
684 bool IsRV32Only;
685 bool IsAltName;
686 bool IsDeprecatedName;
687
688 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
689 // Not in 32-bit mode.
690 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
691 return false;
692 // No required feature associated with the system register.
693 if (FeaturesRequired.none())
694 return true;
695 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
696 }
697};
698
699#define GET_SysRegEncodings_DECL
700#define GET_SysRegsList_DECL
701#include "RISCVGenSearchableTables.inc"
702} // end namespace RISCVSysReg
703
704namespace RISCVInsnOpcode {
705struct RISCVOpcode {
706 StringTable::Offset Name;
707 uint8_t Value;
708};
709
710#define GET_RISCVOpcodesList_DECL
711#include "RISCVGenSearchableTables.inc"
712} // end namespace RISCVInsnOpcode
713
714namespace RISCVABI {
715
716enum ABI {
717 ABI_ILP32,
718 ABI_ILP32F,
719 ABI_ILP32D,
720 ABI_ILP32E,
721 ABI_IL32PC64,
722 ABI_IL32PC64F,
723 ABI_IL32PC64D,
724 ABI_IL32PC64E,
725 ABI_LP64,
726 ABI_LP64F,
727 ABI_LP64D,
728 ABI_LP64E,
729 ABI_L64PC128,
730 ABI_L64PC128F,
731 ABI_L64PC128D,
732 ABI_CHERIOT,
733 ABI_Unknown
734};
735
736// Returns the target ABI, or else a StringError if the requested ABIName is
737// not supported for the subtargets triple and FeatureBits combination.
738ABI computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName);
739
740ABI getTargetABI(StringRef ABIName);
741
742// Returns the register used to hold the stack pointer after realignment.
743MCRegister getBPReg();
744
745// Returns the register holding shadow call stack pointer.
746MCRegister getSCSPReg();
747
748} // namespace RISCVABI
749
750namespace RISCVFeatures {
751
752// Validates if the given combination of features are valid for the target
753// triple. Exits with report_fatal_error if not.
754void validate(const Triple &TT, const FeatureBitset &FeatureBits);
755
756llvm::Expected<std::unique_ptr<RISCVISAInfo>>
757parseFeatureBits(const MCSubtargetInfo &STI);
758
759} // namespace RISCVFeatures
760
761namespace RISCVRVC {
762bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
763bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
764} // namespace RISCVRVC
765
766namespace RISCVZC {
767enum RLISTENCODE {
768 RA = 4,
769 RA_S0,
770 RA_S0_S1,
771 RA_S0_S2,
772 RA_S0_S3,
773 RA_S0_S4,
774 RA_S0_S5,
775 RA_S0_S6,
776 RA_S0_S7,
777 RA_S0_S8,
778 RA_S0_S9,
779 // note - to include s10, s11 must also be included
780 RA_S0_S11,
781 INVALID_RLIST,
782};
783
784inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
785 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
786 switch (EndReg.id()) {
787 case RISCV::X1:
788 return RLISTENCODE::RA;
789 case RISCV::X8:
790 return RLISTENCODE::RA_S0;
791 case RISCV::X9:
792 return RLISTENCODE::RA_S0_S1;
793 case RISCV::X18:
794 return RLISTENCODE::RA_S0_S2;
795 case RISCV::X19:
796 return RLISTENCODE::RA_S0_S3;
797 case RISCV::X20:
798 return RLISTENCODE::RA_S0_S4;
799 case RISCV::X21:
800 return RLISTENCODE::RA_S0_S5;
801 case RISCV::X22:
802 return RLISTENCODE::RA_S0_S6;
803 case RISCV::X23:
804 return RLISTENCODE::RA_S0_S7;
805 case RISCV::X24:
806 return RLISTENCODE::RA_S0_S8;
807 case RISCV::X25:
808 return RLISTENCODE::RA_S0_S9;
809 case RISCV::X27:
810 return RLISTENCODE::RA_S0_S11;
811 default:
812 llvm_unreachable("Undefined input.");
813 }
814}
815
816inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
817 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
818 "Unexpected number of registers");
819 if (NumRegs == 13)
820 return RLISTENCODE::RA_S0_S11;
821
822 return RLISTENCODE::RA + (NumRegs - 1);
823}
824
825inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
826 assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&
827 "Invalid Rlist");
828 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;
829 // s10 and s11 are saved together.
830 if (RlistVal == RLISTENCODE::RA_S0_S11)
831 ++NumRegs;
832
833 unsigned RegSize = IsRV64 ? 8 : 4;
834 return alignTo(Value: NumRegs * RegSize, Align: 16);
835}
836
837void printRegList(unsigned RlistEncode, raw_ostream &OS);
838} // namespace RISCVZC
839
840namespace RISCVVInversePseudosTable {
841struct PseudoInfo {
842 uint16_t Pseudo;
843 uint16_t BaseInstr;
844 uint16_t VLMul : 3;
845 uint16_t SEW : 8;
846 uint16_t IsAltFmt : 1;
847};
848
849#define GET_RISCVVInversePseudosTable_DECL
850#include "RISCVGenSearchableTables.inc"
851
852inline const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul,
853 uint8_t SEW, bool IsAltFmt = false) {
854 return getBaseInfoImpl(BaseInstr, VLMul, SEW, IsAltFmt);
855}
856} // namespace RISCVVInversePseudosTable
857
858namespace RISCV {
859struct VLSEGPseudo {
860 uint16_t NF : 4;
861 uint16_t Masked : 1;
862 uint16_t Strided : 1;
863 uint16_t FF : 1;
864 uint16_t Log2SEW : 3;
865 uint16_t LMUL : 3;
866 uint16_t Pseudo;
867};
868
869struct VLXSEGPseudo {
870 uint16_t NF : 4;
871 uint16_t Masked : 1;
872 uint16_t Ordered : 1;
873 uint16_t Log2SEW : 3;
874 uint16_t LMUL : 3;
875 uint16_t IndexLMUL : 3;
876 uint16_t Pseudo;
877};
878
879struct VSSEGPseudo {
880 uint16_t NF : 4;
881 uint16_t Masked : 1;
882 uint16_t Strided : 1;
883 uint16_t Log2SEW : 3;
884 uint16_t LMUL : 3;
885 uint16_t Pseudo;
886};
887
888struct VSXSEGPseudo {
889 uint16_t NF : 4;
890 uint16_t Masked : 1;
891 uint16_t Ordered : 1;
892 uint16_t Log2SEW : 3;
893 uint16_t LMUL : 3;
894 uint16_t IndexLMUL : 3;
895 uint16_t Pseudo;
896};
897
898struct VLEPseudo {
899 uint16_t Masked : 1;
900 uint16_t Strided : 1;
901 uint16_t FF : 1;
902 uint16_t Log2SEW : 3;
903 uint16_t LMUL : 3;
904 uint16_t Pseudo;
905};
906
907struct VSEPseudo {
908 uint16_t Masked : 1;
909 uint16_t Strided : 1;
910 uint16_t Log2SEW : 3;
911 uint16_t LMUL : 3;
912 uint16_t Pseudo;
913};
914
915struct VLX_VSXPseudo {
916 uint16_t Masked : 1;
917 uint16_t Ordered : 1;
918 uint16_t Log2SEW : 3;
919 uint16_t LMUL : 3;
920 uint16_t IndexLMUL : 3;
921 uint16_t Pseudo;
922};
923
924struct NDSVLNPseudo {
925 uint16_t Masked : 1;
926 uint16_t Unsigned : 1;
927 uint16_t Log2SEW : 3;
928 uint16_t LMUL : 3;
929 uint16_t Pseudo;
930};
931
932#define GET_RISCVVSSEGTable_DECL
933#define GET_RISCVVLSEGTable_DECL
934#define GET_RISCVVLXSEGTable_DECL
935#define GET_RISCVVSXSEGTable_DECL
936#define GET_RISCVVLETable_DECL
937#define GET_RISCVVSETable_DECL
938#define GET_RISCVVLXTable_DECL
939#define GET_RISCVVSXTable_DECL
940#define GET_RISCVNDSVLNTable_DECL
941#include "RISCVGenSearchableTables.inc"
942
943inline bool isValidYBNDSWImm(int64_t Imm) {
944 return (Imm >= 1 && Imm <= 255) ||
945 (Imm >= 256 && Imm <= 504 && (Imm % 8) == 0) ||
946 (Imm >= 512 && Imm <= 4096 && (Imm % 16) == 0);
947}
948} // namespace RISCV
949
950} // namespace llvm
951
952#endif
953