1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/TargetParser/RISCVISAInfo.h"
23#include "llvm/TargetParser/RISCVTargetParser.h"
24#include "llvm/TargetParser/SubtargetFeature.h"
25
26namespace llvm {
27
28namespace RISCVOp {
29enum OperandType : unsigned {
30 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
31 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
32 OPERAND_UIMM2,
33 OPERAND_UIMM2_LSB0,
34 OPERAND_UIMM3,
35 OPERAND_UIMM4,
36 OPERAND_UIMM4_PLUS1,
37 OPERAND_UIMM5,
38 OPERAND_UIMM5_NONZERO,
39 OPERAND_UIMM5_GT3,
40 OPERAND_UIMM5_PLUS1,
41 OPERAND_UIMM5_GE6_PLUS1,
42 OPERAND_UIMM5_LSB0,
43 OPERAND_UIMM5_SLIST,
44 OPERAND_UIMM6,
45 OPERAND_UIMM6_PLUS1,
46 OPERAND_UIMM6_LSB0,
47 OPERAND_UIMM7,
48 OPERAND_UIMM7_LSB00,
49 OPERAND_UIMM7_LSB000,
50 OPERAND_UIMM8_LSB00,
51 OPERAND_UIMM8,
52 OPERAND_UIMM8_LSB000,
53 OPERAND_UIMM8_GE32,
54 OPERAND_UIMM9_LSB000,
55 OPERAND_UIMM9,
56 OPERAND_UIMM10,
57 OPERAND_UIMM10_LSB00_NONZERO,
58 OPERAND_UIMM11,
59 OPERAND_UIMM12,
60 OPERAND_UIMM14_LSB00,
61 OPERAND_UIMM16,
62 OPERAND_UIMM16_NONZERO,
63 OPERAND_UIMMLOG2XLEN,
64 OPERAND_UIMMLOG2XLEN_NONZERO,
65 OPERAND_UIMM32,
66 OPERAND_UIMM48,
67 OPERAND_UIMM64,
68 OPERAND_THREE,
69 OPERAND_FOUR,
70 OPERAND_IMM5_ZIBI,
71 OPERAND_SIMM5,
72 OPERAND_SIMM5_NONZERO,
73 OPERAND_SIMM5_PLUS1,
74 OPERAND_SIMM6,
75 OPERAND_SIMM6_NONZERO,
76 OPERAND_SIMM8,
77 OPERAND_SIMM10,
78 OPERAND_SIMM10_LSB0000_NONZERO,
79 OPERAND_SIMM10_UNSIGNED,
80 OPERAND_SIMM11,
81 OPERAND_SIMM12_LSB00000,
82 OPERAND_SIMM16,
83 OPERAND_SIMM16_NONZERO,
84 OPERAND_SIMM20,
85 OPERAND_SIMM20_LI,
86 OPERAND_SIMM26,
87 OPERAND_CLUI_IMM,
88 OPERAND_VTYPEI10,
89 OPERAND_VTYPEI11,
90 OPERAND_RVKRNUM,
91 OPERAND_RVKRNUM_0_7,
92 OPERAND_RVKRNUM_1_10,
93 OPERAND_RVKRNUM_2_14,
94 OPERAND_RLIST,
95 OPERAND_RLIST_S0,
96 OPERAND_STACKADJ,
97 // Operand is a 3-bit rounding mode, '111' indicates FRM register.
98 // Represents 'frm' argument passing to floating-point operations.
99 OPERAND_FRMARG,
100 // Operand is a 3-bit rounding mode where only RTZ is valid.
101 OPERAND_RTZARG,
102 // Condition code used by select and short forward branch pseudos.
103 OPERAND_COND_CODE,
104 // Ordering for atomic pseudos.
105 OPERAND_ATOMIC_ORDERING,
106 // Vector policy operand.
107 OPERAND_VEC_POLICY,
108 // Vector SEW operand. Stores in log2(SEW).
109 OPERAND_SEW,
110 // Special SEW for mask only instructions. Always 0.
111 OPERAND_SEW_MASK,
112 // Vector rounding mode for VXRM or FRM.
113 OPERAND_VEC_RM,
114 // Vtype operand for XSfmm extension.
115 OPERAND_XSFMM_VTYPE,
116 // XSfmm twiden operand.
117 OPERAND_XSFMM_TWIDEN,
118 OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_TWIDEN,
119
120 OPERAND_UIMM20_LUI,
121 OPERAND_UIMM20_AUIPC,
122
123 // Simm12 or constant pool, global, basicblock, etc.
124 OPERAND_SIMM12_LO,
125
126 OPERAND_BARE_SIMM32,
127
128 // Operand is either a register or uimm5, this is used by V extension pseudo
129 // instructions to represent a value that be passed as AVL to either vsetvli
130 // or vsetivli.
131 OPERAND_AVL,
132
133 // Operand is either a register or imm, this is used by short forward branch
134 // (SFB) pseudos to enable SFB with branches on reg-reg and reg-imm compares.
135 OPERAND_SFB_RHS,
136
137 // Operand is a branch opcode, this too is used by SFB pseudos.
138 OPERAND_BCC_OPCODE,
139
140 OPERAND_VMASK,
141};
142} // namespace RISCVOp
143
144// RISCVII - This namespace holds all of the target specific flags that
145// instruction info tracks. All definitions must match RISCVInstrFormats.td.
146namespace RISCVII {
147enum {
148 InstFormatPseudo = 0,
149 InstFormatR = 1,
150 InstFormatR4 = 2,
151 InstFormatI = 3,
152 InstFormatS = 4,
153 InstFormatB = 5,
154 InstFormatU = 6,
155 InstFormatJ = 7,
156 InstFormatCR = 8,
157 InstFormatCI = 9,
158 InstFormatCSS = 10,
159 InstFormatCIW = 11,
160 InstFormatCL = 12,
161 InstFormatCS = 13,
162 InstFormatCA = 14,
163 InstFormatCB = 15,
164 InstFormatCJ = 16,
165 InstFormatCU = 17,
166 InstFormatCLB = 18,
167 InstFormatCLH = 19,
168 InstFormatCSB = 20,
169 InstFormatCSH = 21,
170 InstFormatQC_EAI = 22,
171 InstFormatQC_EI = 23,
172 InstFormatQC_EB = 24,
173 InstFormatQC_EJ = 25,
174 InstFormatQC_ES = 26,
175 InstFormatNDS_BRANCH_10 = 27,
176 InstFormatOther = 31,
177
178 InstFormatMask = 31,
179 InstFormatShift = 0,
180
181 RVVConstraintShift = InstFormatShift + 5,
182 VS2Constraint = 0b001 << RVVConstraintShift,
183 VS1Constraint = 0b010 << RVVConstraintShift,
184 VMConstraint = 0b100 << RVVConstraintShift,
185 RVVConstraintMask = 0b111 << RVVConstraintShift,
186
187 VLMulShift = RVVConstraintShift + 3,
188 VLMulMask = 0b111 << VLMulShift,
189
190 // Is this a _TIED vector pseudo instruction. For these instructions we
191 // shouldn't skip the tied operand when converting to MC instructions.
192 IsTiedPseudoShift = VLMulShift + 3,
193 IsTiedPseudoMask = 1 << IsTiedPseudoShift,
194
195 // Does this instruction have a SEW operand. It will be the last explicit
196 // operand unless there is a vector policy operand. Used by RVV Pseudos.
197 HasSEWOpShift = IsTiedPseudoShift + 1,
198 HasSEWOpMask = 1 << HasSEWOpShift,
199
200 // Does this instruction have a VL operand. It will be the second to last
201 // explicit operand unless there is a vector policy operand. Used by RVV
202 // Pseudos.
203 HasVLOpShift = HasSEWOpShift + 1,
204 HasVLOpMask = 1 << HasVLOpShift,
205
206 // Does this instruction have a vector policy operand. It will be the last
207 // explicit operand. Used by RVV Pseudos.
208 HasVecPolicyOpShift = HasVLOpShift + 1,
209 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
210
211 // Is this instruction a vector widening reduction instruction. Used by RVV
212 // Pseudos.
213 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
214 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
215
216 // Does this instruction care about mask policy. If it is not, the mask policy
217 // could be either agnostic or undisturbed. For example, unmasked, store, and
218 // reduction operations result would not be affected by mask policy, so
219 // compiler has free to select either one.
220 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
221 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
222
223 // Indicates that the result can be considered sign extended from bit 31. Some
224 // instructions with this flag aren't W instructions, but are either sign
225 // extended from a smaller size, always outputs a small integer, or put zeros
226 // in bits 63:31. Used by the SExtWRemoval pass.
227 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
228 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
229
230 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
231 HasRoundModeOpMask = 1 << HasRoundModeOpShift,
232
233 UsesVXRMShift = HasRoundModeOpShift + 1,
234 UsesVXRMMask = 1 << UsesVXRMShift,
235
236 // Indicates whether these instructions can partially overlap between source
237 // registers and destination registers according to the vector spec.
238 // 0 -> not a vector pseudo
239 // 1 -> default value for vector pseudos. not widening or narrowing.
240 // 2 -> narrowing case
241 // 3 -> widening case
242 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
243 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
244
245 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,
246 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,
247
248 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
249 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,
250
251 // Indicates the EEW of a vector instruction's destination operand.
252 // 0 -> 1
253 // 1 -> SEW
254 // 2 -> SEW * 2
255 // 3 -> SEW * 4
256 DestEEWShift = ElementsDependOnMaskShift + 1,
257 DestEEWMask = 3ULL << DestEEWShift,
258
259 ReadsPastVLShift = DestEEWShift + 2,
260 ReadsPastVLMask = 1ULL << ReadsPastVLShift,
261
262 // 0 -> Don't care about altfmt bit in VTYPE.
263 // 1 -> Is not altfmt.
264 // 2 -> Is altfmt(BF16).
265 AltFmtTypeShift = ReadsPastVLShift + 1,
266 AltFmtTypeMask = 3ULL << AltFmtTypeShift,
267
268 // XSfmmbase
269 HasTWidenOpShift = AltFmtTypeShift + 2,
270 HasTWidenOpMask = 1ULL << HasTWidenOpShift,
271
272 HasTMOpShift = HasTWidenOpShift + 1,
273 HasTMOpMask = 1ULL << HasTMOpShift,
274
275 HasTKOpShift = HasTMOpShift + 1,
276 HasTKOpMask = 1ULL << HasTKOpShift,
277};
278
279// Helper functions to read TSFlags.
280/// \returns the format of the instruction.
281static inline unsigned getFormat(uint64_t TSFlags) {
282 return (TSFlags & InstFormatMask) >> InstFormatShift;
283}
284/// \returns the LMUL for the instruction.
285static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
286 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
287}
288/// \returns true if this a _TIED pseudo.
289static inline bool isTiedPseudo(uint64_t TSFlags) {
290 return TSFlags & IsTiedPseudoMask;
291}
292/// \returns true if there is a SEW operand for the instruction.
293static inline bool hasSEWOp(uint64_t TSFlags) {
294 return TSFlags & HasSEWOpMask;
295}
296/// \returns true if there is a VL operand for the instruction.
297static inline bool hasVLOp(uint64_t TSFlags) {
298 return TSFlags & HasVLOpMask;
299}
300/// \returns true if there is a vector policy operand for this instruction.
301static inline bool hasVecPolicyOp(uint64_t TSFlags) {
302 return TSFlags & HasVecPolicyOpMask;
303}
304/// \returns true if it is a vector widening reduction instruction.
305static inline bool isRVVWideningReduction(uint64_t TSFlags) {
306 return TSFlags & IsRVVWideningReductionMask;
307}
308/// \returns true if mask policy is valid for the instruction.
309static inline bool usesMaskPolicy(uint64_t TSFlags) {
310 return TSFlags & UsesMaskPolicyMask;
311}
312
313/// \returns true if there is a rounding mode operand for this instruction
314static inline bool hasRoundModeOp(uint64_t TSFlags) {
315 return TSFlags & HasRoundModeOpMask;
316}
317
318enum class AltFmtType { DontCare, NotAltFmt, AltFmt };
319static inline AltFmtType getAltFmtType(uint64_t TSFlags) {
320 return static_cast<AltFmtType>((TSFlags & AltFmtTypeMask) >> AltFmtTypeShift);
321}
322
323/// \returns true if this instruction uses vxrm
324static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
325
326/// \returns true if the elements in the body are affected by VL,
327/// e.g. vslide1down.vx/vredsum.vs/viota.m
328static inline bool elementsDependOnVL(uint64_t TSFlags) {
329 return TSFlags & ElementsDependOnVLMask;
330}
331
332/// \returns true if the elements in the body are affected by the mask,
333/// e.g. vredsum.vs/viota.m
334static inline bool elementsDependOnMask(uint64_t TSFlags) {
335 return TSFlags & ElementsDependOnMaskMask;
336}
337
338/// \returns true if the instruction may read elements past VL, e.g.
339/// vslidedown/vrgather
340static inline bool readsPastVL(uint64_t TSFlags) {
341 return TSFlags & ReadsPastVLMask;
342}
343
344// XSfmmbase
345static inline bool hasTWidenOp(uint64_t TSFlags) {
346 return TSFlags & HasTWidenOpMask;
347}
348
349static inline bool hasTMOp(uint64_t TSFlags) { return TSFlags & HasTMOpMask; }
350
351static inline bool hasTKOp(uint64_t TSFlags) { return TSFlags & HasTKOpMask; }
352
353static inline unsigned getTWidenOpNum(const MCInstrDesc &Desc) {
354 assert(hasTWidenOp(Desc.TSFlags));
355 return Desc.getNumOperands() - 1;
356}
357
358static inline unsigned getTNOpNum(const MCInstrDesc &Desc) {
359 const uint64_t TSFlags = Desc.TSFlags;
360 assert(hasTWidenOp(TSFlags) && hasVLOp(TSFlags));
361 unsigned Offset = 3;
362 if (hasTKOp(TSFlags))
363 Offset = 4;
364 return Desc.getNumOperands() - Offset;
365}
366
367static inline unsigned getTMOpNum(const MCInstrDesc &Desc) {
368 const uint64_t TSFlags = Desc.TSFlags;
369 assert(hasTWidenOp(TSFlags) && hasTMOp(TSFlags));
370 if (hasTKOp(TSFlags))
371 return Desc.getNumOperands() - 5;
372 // vtzero.t
373 return Desc.getNumOperands() - 4;
374}
375
376static inline unsigned getTKOpNum(const MCInstrDesc &Desc) {
377 [[maybe_unused]] const uint64_t TSFlags = Desc.TSFlags;
378 assert(hasTWidenOp(TSFlags) && hasTKOp(TSFlags));
379 return Desc.getNumOperands() - 3;
380}
381
382static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
383 const uint64_t TSFlags = Desc.TSFlags;
384 // This method is only called if we expect to have a VL operand, and all
385 // instructions with VL also have SEW.
386 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
387 // In Xsfmmbase, TN is an alias for VL, so here we use the same TSFlags bit.
388 if (hasTWidenOp(TSFlags))
389 return getTNOpNum(Desc);
390 unsigned Offset = 2;
391 if (hasVecPolicyOp(TSFlags))
392 Offset = 3;
393 return Desc.getNumOperands() - Offset;
394}
395
396static inline MCRegister
397getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
398 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
399 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
400 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
401}
402
403static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
404 const uint64_t TSFlags = Desc.TSFlags;
405 assert(hasSEWOp(TSFlags));
406 unsigned Offset = 1;
407 if (hasVecPolicyOp(TSFlags) || hasTWidenOp(TSFlags))
408 Offset = 2;
409 return Desc.getNumOperands() - Offset;
410}
411
412static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
413 assert(hasVecPolicyOp(Desc.TSFlags));
414 return Desc.getNumOperands() - 1;
415}
416
417/// \returns the index to the rounding mode immediate value if any, otherwise
418/// returns -1.
419static inline int getFRMOpNum(const MCInstrDesc &Desc) {
420 const uint64_t TSFlags = Desc.TSFlags;
421 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
422 return -1;
423
424 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
425 assert(Idx >= 0 && "No rm operand?");
426 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
427 "Operand has wrong type");
428
429 return Idx;
430}
431
432/// \returns the index to the rounding mode immediate value if any, otherwise
433/// returns -1.
434static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
435 const uint64_t TSFlags = Desc.TSFlags;
436 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
437 return -1;
438
439 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
440 assert(Idx >= 0 && "No rm operand?");
441 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
442 "Operand has wrong type");
443
444 return Idx;
445}
446
447// Is the first def operand tied to the first use operand. This is true for
448// vector pseudo instructions that have a merge operand for tail/mask
449// undisturbed. It's also true for vector FMA instructions where one of the
450// operands is also the destination register.
451static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
452 return Desc.getNumDefs() < Desc.getNumOperands() &&
453 Desc.getOperandConstraint(OpNum: Desc.getNumDefs(), Constraint: MCOI::TIED_TO) == 0;
454}
455
456// RISC-V Specific Machine Operand Flags
457enum {
458 MO_None = 0,
459 MO_CALL = 1,
460 MO_LO = 3,
461 MO_HI = 4,
462 MO_PCREL_LO = 5,
463 MO_PCREL_HI = 6,
464 MO_GOT_HI = 7,
465 MO_TPREL_LO = 8,
466 MO_TPREL_HI = 9,
467 MO_TPREL_ADD = 10,
468 MO_TLS_GOT_HI = 11,
469 MO_TLS_GD_HI = 12,
470 MO_TLSDESC_HI = 13,
471 MO_TLSDESC_LOAD_LO = 14,
472 MO_TLSDESC_ADD_LO = 15,
473 MO_TLSDESC_CALL = 16,
474
475 // Used to differentiate between target-specific "direct" flags and "bitmask"
476 // flags. A machine operand can only have one "direct" flag, but can have
477 // multiple "bitmask" flags.
478 MO_DIRECT_FLAG_MASK = 31
479};
480} // namespace RISCVII
481
482// Describes the predecessor/successor bits used in the FENCE instruction.
483namespace RISCVFenceField {
484enum FenceField {
485 I = 8,
486 O = 4,
487 R = 2,
488 W = 1
489};
490}
491
492// Describes the supported floating point rounding mode encodings.
493namespace RISCVFPRndMode {
494enum RoundingMode {
495 RNE = 0,
496 RTZ = 1,
497 RDN = 2,
498 RUP = 3,
499 RMM = 4,
500 DYN = 7,
501 Invalid
502};
503
504inline static StringRef roundingModeToString(RoundingMode RndMode) {
505 switch (RndMode) {
506 default:
507 llvm_unreachable("Unknown floating point rounding mode");
508 case RISCVFPRndMode::RNE:
509 return "rne";
510 case RISCVFPRndMode::RTZ:
511 return "rtz";
512 case RISCVFPRndMode::RDN:
513 return "rdn";
514 case RISCVFPRndMode::RUP:
515 return "rup";
516 case RISCVFPRndMode::RMM:
517 return "rmm";
518 case RISCVFPRndMode::DYN:
519 return "dyn";
520 }
521}
522
523inline static RoundingMode stringToRoundingMode(StringRef Str) {
524 return StringSwitch<RoundingMode>(Str)
525 .Case(S: "rne", Value: RISCVFPRndMode::RNE)
526 .Case(S: "rtz", Value: RISCVFPRndMode::RTZ)
527 .Case(S: "rdn", Value: RISCVFPRndMode::RDN)
528 .Case(S: "rup", Value: RISCVFPRndMode::RUP)
529 .Case(S: "rmm", Value: RISCVFPRndMode::RMM)
530 .Case(S: "dyn", Value: RISCVFPRndMode::DYN)
531 .Default(Value: RISCVFPRndMode::Invalid);
532}
533
534inline static bool isValidRoundingMode(unsigned Mode) {
535 switch (Mode) {
536 default:
537 return false;
538 case RISCVFPRndMode::RNE:
539 case RISCVFPRndMode::RTZ:
540 case RISCVFPRndMode::RDN:
541 case RISCVFPRndMode::RUP:
542 case RISCVFPRndMode::RMM:
543 case RISCVFPRndMode::DYN:
544 return true;
545 }
546}
547} // namespace RISCVFPRndMode
548
549namespace RISCVVXRndMode {
550enum RoundingMode {
551 RNU = 0,
552 RNE = 1,
553 RDN = 2,
554 ROD = 3,
555 Invalid
556};
557
558inline static StringRef roundingModeToString(RoundingMode RndMode) {
559 switch (RndMode) {
560 default:
561 llvm_unreachable("Unknown vector fixed-point rounding mode");
562 case RISCVVXRndMode::RNU:
563 return "rnu";
564 case RISCVVXRndMode::RNE:
565 return "rne";
566 case RISCVVXRndMode::RDN:
567 return "rdn";
568 case RISCVVXRndMode::ROD:
569 return "rod";
570 }
571}
572
573inline static RoundingMode stringToRoundingMode(StringRef Str) {
574 return StringSwitch<RoundingMode>(Str)
575 .Case(S: "rnu", Value: RISCVVXRndMode::RNU)
576 .Case(S: "rne", Value: RISCVVXRndMode::RNE)
577 .Case(S: "rdn", Value: RISCVVXRndMode::RDN)
578 .Case(S: "rod", Value: RISCVVXRndMode::ROD)
579 .Default(Value: RISCVVXRndMode::Invalid);
580}
581
582inline static bool isValidRoundingMode(unsigned Mode) {
583 switch (Mode) {
584 default:
585 return false;
586 case RISCVVXRndMode::RNU:
587 case RISCVVXRndMode::RNE:
588 case RISCVVXRndMode::RDN:
589 case RISCVVXRndMode::ROD:
590 return true;
591 }
592}
593} // namespace RISCVVXRndMode
594
595namespace RISCVExceptFlags {
596enum ExceptionFlag {
597 NX = 0x01, // Inexact
598 UF = 0x02, // Underflow
599 OF = 0x04, // Overflow
600 DZ = 0x08, // Divide by zero
601 NV = 0x10, // Invalid operation
602 ALL = 0x1F // Mask for all accrued exception flags
603};
604}
605
606//===----------------------------------------------------------------------===//
607// Floating-point Immediates
608//
609
610namespace RISCVLoadFPImm {
611float getFPImm(unsigned Imm);
612
613/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
614/// immediate value. If the value cannot be represented as a 5-bit binary
615/// encoding, then return -1.
616int getLoadFPImm(APFloat FPImm);
617} // namespace RISCVLoadFPImm
618
619namespace RISCVSysReg {
620struct SysReg {
621 const char Name[32];
622 unsigned Encoding;
623 // FIXME: add these additional fields when needed.
624 // Privilege Access: Read, Write, Read-Only.
625 // unsigned ReadWrite;
626 // Privilege Mode: User, System or Machine.
627 // unsigned Mode;
628 // Check field name.
629 // unsigned Extra;
630 // Register number without the privilege bits.
631 // unsigned Number;
632 FeatureBitset FeaturesRequired;
633 bool IsRV32Only;
634 bool IsAltName;
635 bool IsDeprecatedName;
636
637 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
638 // Not in 32-bit mode.
639 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
640 return false;
641 // No required feature associated with the system register.
642 if (FeaturesRequired.none())
643 return true;
644 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
645 }
646};
647
648#define GET_SysRegEncodings_DECL
649#define GET_SysRegsList_DECL
650#include "RISCVGenSearchableTables.inc"
651} // end namespace RISCVSysReg
652
653namespace RISCVInsnOpcode {
654struct RISCVOpcode {
655 char Name[10];
656 uint8_t Value;
657};
658
659#define GET_RISCVOpcodesList_DECL
660#include "RISCVGenSearchableTables.inc"
661} // end namespace RISCVInsnOpcode
662
663namespace RISCVABI {
664
665enum ABI {
666 ABI_ILP32,
667 ABI_ILP32F,
668 ABI_ILP32D,
669 ABI_ILP32E,
670 ABI_LP64,
671 ABI_LP64F,
672 ABI_LP64D,
673 ABI_LP64E,
674 ABI_Unknown
675};
676
677// Returns the target ABI, or else a StringError if the requested ABIName is
678// not supported for the given TT and FeatureBits combination.
679ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
680 StringRef ABIName);
681
682ABI getTargetABI(StringRef ABIName);
683
684// Returns the register used to hold the stack pointer after realignment.
685MCRegister getBPReg();
686
687// Returns the register holding shadow call stack pointer.
688MCRegister getSCSPReg();
689
690} // namespace RISCVABI
691
692namespace RISCVFeatures {
693
694// Validates if the given combination of features are valid for the target
695// triple. Exits with report_fatal_error if not.
696void validate(const Triple &TT, const FeatureBitset &FeatureBits);
697
698llvm::Expected<std::unique_ptr<RISCVISAInfo>>
699parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
700
701} // namespace RISCVFeatures
702
703namespace RISCVRVC {
704bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
705bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
706} // namespace RISCVRVC
707
708namespace RISCVZC {
709enum RLISTENCODE {
710 RA = 4,
711 RA_S0,
712 RA_S0_S1,
713 RA_S0_S2,
714 RA_S0_S3,
715 RA_S0_S4,
716 RA_S0_S5,
717 RA_S0_S6,
718 RA_S0_S7,
719 RA_S0_S8,
720 RA_S0_S9,
721 // note - to include s10, s11 must also be included
722 RA_S0_S11,
723 INVALID_RLIST,
724};
725
726inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
727 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
728 switch (EndReg.id()) {
729 case RISCV::X1:
730 return RLISTENCODE::RA;
731 case RISCV::X8:
732 return RLISTENCODE::RA_S0;
733 case RISCV::X9:
734 return RLISTENCODE::RA_S0_S1;
735 case RISCV::X18:
736 return RLISTENCODE::RA_S0_S2;
737 case RISCV::X19:
738 return RLISTENCODE::RA_S0_S3;
739 case RISCV::X20:
740 return RLISTENCODE::RA_S0_S4;
741 case RISCV::X21:
742 return RLISTENCODE::RA_S0_S5;
743 case RISCV::X22:
744 return RLISTENCODE::RA_S0_S6;
745 case RISCV::X23:
746 return RLISTENCODE::RA_S0_S7;
747 case RISCV::X24:
748 return RLISTENCODE::RA_S0_S8;
749 case RISCV::X25:
750 return RLISTENCODE::RA_S0_S9;
751 case RISCV::X27:
752 return RLISTENCODE::RA_S0_S11;
753 default:
754 llvm_unreachable("Undefined input.");
755 }
756}
757
758inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
759 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
760 "Unexpected number of registers");
761 if (NumRegs == 13)
762 return RLISTENCODE::RA_S0_S11;
763
764 return RLISTENCODE::RA + (NumRegs - 1);
765}
766
767inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
768 assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&
769 "Invalid Rlist");
770 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;
771 // s10 and s11 are saved together.
772 if (RlistVal == RLISTENCODE::RA_S0_S11)
773 ++NumRegs;
774
775 unsigned RegSize = IsRV64 ? 8 : 4;
776 return alignTo(Value: NumRegs * RegSize, Align: 16);
777}
778
779void printRegList(unsigned RlistEncode, raw_ostream &OS);
780} // namespace RISCVZC
781
782namespace RISCVVInversePseudosTable {
783struct PseudoInfo {
784 uint16_t Pseudo;
785 uint16_t BaseInstr;
786 uint16_t VLMul : 3;
787 uint16_t SEW : 8;
788 uint16_t IsAltFmt : 1;
789};
790
791#define GET_RISCVVInversePseudosTable_DECL
792#include "RISCVGenSearchableTables.inc"
793
794inline const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul,
795 uint8_t SEW, bool IsAltFmt = false) {
796 return getBaseInfoImpl(BaseInstr, VLMul, SEW, IsAltFmt);
797}
798} // namespace RISCVVInversePseudosTable
799
800namespace RISCV {
801struct VLSEGPseudo {
802 uint16_t NF : 4;
803 uint16_t Masked : 1;
804 uint16_t Strided : 1;
805 uint16_t FF : 1;
806 uint16_t Log2SEW : 3;
807 uint16_t LMUL : 3;
808 uint16_t Pseudo;
809};
810
811struct VLXSEGPseudo {
812 uint16_t NF : 4;
813 uint16_t Masked : 1;
814 uint16_t Ordered : 1;
815 uint16_t Log2SEW : 3;
816 uint16_t LMUL : 3;
817 uint16_t IndexLMUL : 3;
818 uint16_t Pseudo;
819};
820
821struct VSSEGPseudo {
822 uint16_t NF : 4;
823 uint16_t Masked : 1;
824 uint16_t Strided : 1;
825 uint16_t Log2SEW : 3;
826 uint16_t LMUL : 3;
827 uint16_t Pseudo;
828};
829
830struct VSXSEGPseudo {
831 uint16_t NF : 4;
832 uint16_t Masked : 1;
833 uint16_t Ordered : 1;
834 uint16_t Log2SEW : 3;
835 uint16_t LMUL : 3;
836 uint16_t IndexLMUL : 3;
837 uint16_t Pseudo;
838};
839
840struct VLEPseudo {
841 uint16_t Masked : 1;
842 uint16_t Strided : 1;
843 uint16_t FF : 1;
844 uint16_t Log2SEW : 3;
845 uint16_t LMUL : 3;
846 uint16_t Pseudo;
847};
848
849struct VSEPseudo {
850 uint16_t Masked : 1;
851 uint16_t Strided : 1;
852 uint16_t Log2SEW : 3;
853 uint16_t LMUL : 3;
854 uint16_t Pseudo;
855};
856
857struct VLX_VSXPseudo {
858 uint16_t Masked : 1;
859 uint16_t Ordered : 1;
860 uint16_t Log2SEW : 3;
861 uint16_t LMUL : 3;
862 uint16_t IndexLMUL : 3;
863 uint16_t Pseudo;
864};
865
866struct NDSVLNPseudo {
867 uint16_t Masked : 1;
868 uint16_t Unsigned : 1;
869 uint16_t Log2SEW : 3;
870 uint16_t LMUL : 3;
871 uint16_t Pseudo;
872};
873
874#define GET_RISCVVSSEGTable_DECL
875#define GET_RISCVVLSEGTable_DECL
876#define GET_RISCVVLXSEGTable_DECL
877#define GET_RISCVVSXSEGTable_DECL
878#define GET_RISCVVLETable_DECL
879#define GET_RISCVVSETable_DECL
880#define GET_RISCVVLXTable_DECL
881#define GET_RISCVVSXTable_DECL
882#define GET_RISCVNDSVLNTable_DECL
883#include "RISCVGenSearchableTables.inc"
884} // namespace RISCV
885
886} // namespace llvm
887
888#endif
889