1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/ADT/StringTable.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/Support/Error.h"
24#include "llvm/TargetParser/RISCVISAInfo.h"
25#include "llvm/TargetParser/RISCVTargetParser.h"
26#include "llvm/TargetParser/SubtargetFeature.h"
27
28namespace llvm {
29
30class MCSubtargetInfo;
31
32namespace RISCVOp {
33enum OperandType : unsigned {
34 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
35 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
36 OPERAND_UIMM2,
37 OPERAND_UIMM2_LSB0,
38 OPERAND_UIMM3,
39 OPERAND_UIMM4,
40 OPERAND_UIMM4_PLUS1,
41 OPERAND_UIMM5,
42 OPERAND_UIMM5_NONZERO,
43 OPERAND_UIMM5_GT3,
44 OPERAND_UIMM5_PLUS1,
45 OPERAND_UIMM5_GE6_PLUS1,
46 OPERAND_UIMM5_LSB0,
47 OPERAND_UIMM5_SLIST,
48 OPERAND_UIMM6,
49 OPERAND_UIMM6_PLUS1,
50 OPERAND_UIMM6_LSB0,
51 OPERAND_UIMM6_LSB000,
52 OPERAND_UIMM7,
53 OPERAND_UIMM7_LSB00,
54 OPERAND_UIMM7_LSB000,
55 OPERAND_UIMM7_EQ_XLEN,
56 OPERAND_UIMM8_LSB00,
57 OPERAND_UIMM8,
58 OPERAND_UIMM8_LSB000,
59 OPERAND_UIMM8_GE32,
60 OPERAND_UIMM9,
61 OPERAND_UIMM9_LSB000,
62 OPERAND_UIMM9_YBNDSWI,
63 OPERAND_UIMM10,
64 OPERAND_UIMM10_LSB00_NONZERO,
65 OPERAND_UIMM11,
66 OPERAND_UIMM12,
67 OPERAND_UIMM14_LSB00,
68 OPERAND_UIMM16,
69 OPERAND_UIMM16_NONZERO,
70 OPERAND_UIMMLOG2XLEN,
71 OPERAND_UIMMLOG2XLEN_NONZERO,
72 OPERAND_UIMM32,
73 OPERAND_UIMM48,
74 OPERAND_UIMM64,
75 OPERAND_THREE,
76 OPERAND_FOUR,
77 OPERAND_IMM5_ZIBI,
78 OPERAND_SIMM5,
79 OPERAND_SIMM5_NONZERO,
80 OPERAND_SIMM5_PLUS1,
81 OPERAND_SIMM6,
82 OPERAND_SIMM6_NONZERO,
83 OPERAND_SIMM8,
84 OPERAND_SIMM10,
85 OPERAND_SIMM10_LSB0000_NONZERO,
86 OPERAND_SIMM10_UNSIGNED,
87 OPERAND_SIMM11,
88 OPERAND_SIMM12,
89 OPERAND_SIMM12_LSB00000,
90 OPERAND_SIMM16,
91 OPERAND_SIMM16_NONZERO,
92 OPERAND_SIMM20,
93 OPERAND_SIMM20_LI,
94 OPERAND_SIMM26,
95 OPERAND_CLUI_IMM,
96 OPERAND_VTYPEI10,
97 OPERAND_VTYPEI11,
98 OPERAND_RVKRNUM,
99 OPERAND_RVKRNUM_0_7,
100 OPERAND_RVKRNUM_1_10,
101 OPERAND_RVKRNUM_2_14,
102 OPERAND_RLIST,
103 OPERAND_RLIST_S0,
104 OPERAND_STACKADJ,
105 // Operand is a 3-bit rounding mode, '111' indicates FRM register.
106 // Represents 'frm' argument passing to floating-point operations.
107 OPERAND_FRMARG,
108 // Operand is a 3-bit rounding mode where only RTZ is valid.
109 OPERAND_RTZARG,
110 // Condition code used by select and short forward branch pseudos.
111 OPERAND_COND_CODE,
112 // Ordering for atomic pseudos.
113 OPERAND_ATOMIC_ORDERING,
114 // Vector policy operand.
115 OPERAND_VEC_POLICY,
116 // Vector SEW operand. Stores in log2(SEW).
117 OPERAND_SEW,
118 // Special SEW for mask only instructions. Always 0.
119 OPERAND_SEW_MASK,
120 // Vector rounding mode for VXRM or FRM.
121 OPERAND_VEC_RM,
122 // Vtype operand for XSfmm extension.
123 OPERAND_XSFMM_VTYPE,
124 // XSfmm twiden operand.
125 OPERAND_XSFMM_TWIDEN,
126 OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_TWIDEN,
127
128 OPERAND_UIMM20_LUI,
129 OPERAND_UIMM20_AUIPC,
130
131 // Simm12 or constant pool, global, basicblock, etc.
132 OPERAND_SIMM12_LO,
133
134 OPERAND_BARE_SIMM32,
135
136 // Operand is either a register or uimm5, this is used by V extension pseudo
137 // instructions to represent a value that be passed as AVL to either vsetvli
138 // or vsetivli.
139 OPERAND_AVL,
140
141 // Operand is either a register or imm, this is used by short forward branch
142 // (SFB) pseudos to enable SFB with branches on reg-reg and reg-imm compares.
143 OPERAND_SFB_RHS,
144
145 // Operand is a branch opcode, this too is used by SFB pseudos.
146 OPERAND_BCC_OPCODE,
147
148 OPERAND_VMASK,
149 OPERAND_SMTVType,
150 OPERAND_SMTI8,
151};
152} // namespace RISCVOp
153
154// RISCVII - This namespace holds all of the target specific flags that
155// instruction info tracks. All definitions must match RISCVInstrFormats.td.
156namespace RISCVII {
157enum : uint64_t {
158 InstFormatPseudo = 0,
159 InstFormatR = 1,
160 InstFormatR4 = 2,
161 InstFormatI = 3,
162 InstFormatS = 4,
163 InstFormatB = 5,
164 InstFormatU = 6,
165 InstFormatJ = 7,
166 InstFormatCR = 8,
167 InstFormatCI = 9,
168 InstFormatCSS = 10,
169 InstFormatCIW = 11,
170 InstFormatCL = 12,
171 InstFormatCS = 13,
172 InstFormatCA = 14,
173 InstFormatCB = 15,
174 InstFormatCJ = 16,
175 InstFormatCU = 17,
176 InstFormatCLB = 18,
177 InstFormatCLH = 19,
178 InstFormatCSB = 20,
179 InstFormatCSH = 21,
180 InstFormatQC_EAI = 22,
181 InstFormatQC_EI = 23,
182 InstFormatQC_EB = 24,
183 InstFormatQC_EJ = 25,
184 InstFormatQC_ES = 26,
185 InstFormatNDS_BRANCH_10 = 27,
186 InstFormatOther = 31,
187
188 InstFormatMask = 31,
189 InstFormatShift = 0,
190
191 RVVConstraintShift = InstFormatShift + 5,
192 VS2Constraint = 0b001 << RVVConstraintShift,
193 VS1Constraint = 0b010 << RVVConstraintShift,
194 VMConstraint = 0b100 << RVVConstraintShift,
195 RVVConstraintMask = 0b111 << RVVConstraintShift,
196
197 VLMulShift = RVVConstraintShift + 3,
198 VLMulMask = 0b111 << VLMulShift,
199
200 // Is this a _TIED vector pseudo instruction. For these instructions we
201 // shouldn't skip the tied operand when converting to MC instructions.
202 IsTiedPseudoShift = VLMulShift + 3,
203 IsTiedPseudoMask = 1 << IsTiedPseudoShift,
204
205 // Does this instruction have a SEW operand. It will be the last explicit
206 // operand unless there is a vector policy operand. Used by RVV Pseudos.
207 HasSEWOpShift = IsTiedPseudoShift + 1,
208 HasSEWOpMask = 1 << HasSEWOpShift,
209
210 // Does this instruction have a VL operand. It will be the second to last
211 // explicit operand unless there is a vector policy operand. Used by RVV
212 // Pseudos.
213 HasVLOpShift = HasSEWOpShift + 1,
214 HasVLOpMask = 1 << HasVLOpShift,
215
216 // Does this instruction have a vector policy operand. It will be the last
217 // explicit operand. Used by RVV Pseudos.
218 HasVecPolicyOpShift = HasVLOpShift + 1,
219 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
220
221 // Is this instruction a vector widening reduction instruction. Used by RVV
222 // Pseudos.
223 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
224 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
225
226 // Does this instruction care about mask policy. If it is not, the mask policy
227 // could be either agnostic or undisturbed. For example, unmasked, store, and
228 // reduction operations result would not be affected by mask policy, so
229 // compiler has free to select either one.
230 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
231 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
232
233 // Indicates that the result can be considered sign extended from bit 31. Some
234 // instructions with this flag aren't W instructions, but are either sign
235 // extended from a smaller size, always outputs a small integer, or put zeros
236 // in bits 63:31. Used by the SExtWRemoval pass.
237 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
238 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
239
240 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
241 HasRoundModeOpMask = 1 << HasRoundModeOpShift,
242
243 UsesVXRMShift = HasRoundModeOpShift + 1,
244 UsesVXRMMask = 1 << UsesVXRMShift,
245
246 // Indicates whether these instructions can partially overlap between source
247 // registers and destination registers according to the vector spec.
248 // 0 -> not a vector pseudo
249 // 1 -> default value for vector pseudos. not widening or narrowing.
250 // 2 -> narrowing case
251 // 3 -> widening case
252 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
253 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
254
255 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,
256 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,
257
258 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
259 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,
260
261 // Indicates the EEW of a vector instruction's destination operand.
262 // 0 -> 1
263 // 1 -> SEW
264 // 2 -> SEW * 2
265 // 3 -> SEW * 4
266 DestEEWShift = ElementsDependOnMaskShift + 1,
267 DestEEWMask = 3ULL << DestEEWShift,
268
269 ReadsPastVLShift = DestEEWShift + 2,
270 ReadsPastVLMask = 1ULL << ReadsPastVLShift,
271
272 // 0 -> Don't care about altfmt bit in VTYPE.
273 // 1 -> Is not altfmt.
274 // 2 -> Is altfmt(BF16).
275 AltFmtTypeShift = ReadsPastVLShift + 1,
276 AltFmtTypeMask = 3ULL << AltFmtTypeShift,
277
278 // XSfmmbase
279 HasTWidenOpShift = AltFmtTypeShift + 2,
280 HasTWidenOpMask = 1ULL << HasTWidenOpShift,
281
282 HasTMOpShift = HasTWidenOpShift + 1,
283 HasTMOpMask = 1ULL << HasTMOpShift,
284
285 HasTKOpShift = HasTMOpShift + 1,
286 HasTKOpMask = 1ULL << HasTKOpShift,
287
288 SMTConstraintShift = HasTKOpShift + 1,
289 SMTConstraintMask = 1ULL << SMTConstraintShift,
290};
291
292// Helper functions to read TSFlags.
293/// \returns the format of the instruction.
294static inline unsigned getFormat(uint64_t TSFlags) {
295 return (TSFlags & InstFormatMask) >> InstFormatShift;
296}
297/// \returns the LMUL for the instruction.
298static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
299 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
300}
301/// \returns true if this a _TIED pseudo.
302static inline bool isTiedPseudo(uint64_t TSFlags) {
303 return TSFlags & IsTiedPseudoMask;
304}
305/// \returns true if there is a SEW operand for the instruction.
306static inline bool hasSEWOp(uint64_t TSFlags) {
307 return TSFlags & HasSEWOpMask;
308}
309/// \returns true if there is a VL operand for the instruction.
310static inline bool hasVLOp(uint64_t TSFlags) {
311 return TSFlags & HasVLOpMask;
312}
313/// \returns true if there is a vector policy operand for this instruction.
314static inline bool hasVecPolicyOp(uint64_t TSFlags) {
315 return TSFlags & HasVecPolicyOpMask;
316}
317/// \returns true if it is a vector widening reduction instruction.
318static inline bool isRVVWideningReduction(uint64_t TSFlags) {
319 return TSFlags & IsRVVWideningReductionMask;
320}
321/// \returns true if mask policy is valid for the instruction.
322static inline bool usesMaskPolicy(uint64_t TSFlags) {
323 return TSFlags & UsesMaskPolicyMask;
324}
325
326/// \returns true if there is a rounding mode operand for this instruction
327static inline bool hasRoundModeOp(uint64_t TSFlags) {
328 return TSFlags & HasRoundModeOpMask;
329}
330
331enum class AltFmtType { DontCare, NotAltFmt, AltFmt };
332static inline AltFmtType getAltFmtType(uint64_t TSFlags) {
333 return static_cast<AltFmtType>((TSFlags & AltFmtTypeMask) >> AltFmtTypeShift);
334}
335
336/// \returns true if this instruction uses vxrm
337static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
338
339/// \returns true if the elements in the body are affected by VL,
340/// e.g. vslide1down.vx/vredsum.vs/viota.m
341static inline bool elementsDependOnVL(uint64_t TSFlags) {
342 return TSFlags & ElementsDependOnVLMask;
343}
344
345/// \returns true if the elements in the body are affected by the mask,
346/// e.g. vredsum.vs/viota.m
347static inline bool elementsDependOnMask(uint64_t TSFlags) {
348 return TSFlags & ElementsDependOnMaskMask;
349}
350
351/// \returns true if the instruction may read elements past VL, e.g.
352/// vslidedown/vrgather
353static inline bool readsPastVL(uint64_t TSFlags) {
354 return TSFlags & ReadsPastVLMask;
355}
356
357// XSfmmbase
358static inline bool hasTWidenOp(uint64_t TSFlags) {
359 return TSFlags & HasTWidenOpMask;
360}
361
362static inline bool hasTMOp(uint64_t TSFlags) { return TSFlags & HasTMOpMask; }
363
364static inline bool hasTKOp(uint64_t TSFlags) { return TSFlags & HasTKOpMask; }
365
366static inline unsigned getTWidenOpNum(const MCInstrDesc &Desc) {
367 assert(hasTWidenOp(Desc.TSFlags));
368 return Desc.getNumOperands() - 1;
369}
370
371static inline unsigned getTNOpNum(const MCInstrDesc &Desc) {
372 const uint64_t TSFlags = Desc.TSFlags;
373 assert(hasTWidenOp(TSFlags) && hasVLOp(TSFlags));
374 unsigned Offset = 3;
375 if (hasTKOp(TSFlags))
376 Offset = 4;
377 return Desc.getNumOperands() - Offset;
378}
379
380static inline unsigned getTMOpNum(const MCInstrDesc &Desc) {
381 const uint64_t TSFlags = Desc.TSFlags;
382 assert(hasTWidenOp(TSFlags) && hasTMOp(TSFlags));
383 if (hasTKOp(TSFlags))
384 return Desc.getNumOperands() - 5;
385 // vtzero.t
386 return Desc.getNumOperands() - 4;
387}
388
389static inline unsigned getTKOpNum(const MCInstrDesc &Desc) {
390 [[maybe_unused]] const uint64_t TSFlags = Desc.TSFlags;
391 assert(hasTWidenOp(TSFlags) && hasTKOp(TSFlags));
392 return Desc.getNumOperands() - 3;
393}
394
395static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
396 const uint64_t TSFlags = Desc.TSFlags;
397 // This method is only called if we expect to have a VL operand, and all
398 // instructions with VL also have SEW.
399 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
400 // In Xsfmmbase, TN is an alias for VL, so here we use the same TSFlags bit.
401 if (hasTWidenOp(TSFlags))
402 return getTNOpNum(Desc);
403 unsigned Offset = 2;
404 if (hasVecPolicyOp(TSFlags))
405 Offset = 3;
406 return Desc.getNumOperands() - Offset;
407}
408
409static inline MCRegister
410getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
411 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
412 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
413 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
414}
415
416static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
417 const uint64_t TSFlags = Desc.TSFlags;
418 assert(hasSEWOp(TSFlags));
419 unsigned Offset = 1;
420 if (hasVecPolicyOp(TSFlags) || hasTWidenOp(TSFlags))
421 Offset = 2;
422 return Desc.getNumOperands() - Offset;
423}
424
425static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
426 assert(hasVecPolicyOp(Desc.TSFlags));
427 return Desc.getNumOperands() - 1;
428}
429
430/// \returns the index to the rounding mode immediate value if any, otherwise
431/// returns -1.
432static inline int getFRMOpNum(const MCInstrDesc &Desc) {
433 const uint64_t TSFlags = Desc.TSFlags;
434 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
435 return -1;
436
437 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
438 assert(Idx >= 0 && "No rm operand?");
439 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
440 "Operand has wrong type");
441
442 return Idx;
443}
444
445/// \returns the index to the rounding mode immediate value if any, otherwise
446/// returns -1.
447static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
448 const uint64_t TSFlags = Desc.TSFlags;
449 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
450 return -1;
451
452 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
453 assert(Idx >= 0 && "No rm operand?");
454 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
455 "Operand has wrong type");
456
457 return Idx;
458}
459
460// Is the first def operand tied to the first use operand. This is true for
461// vector pseudo instructions that have a merge operand for tail/mask
462// undisturbed. It's also true for vector FMA instructions where one of the
463// operands is also the destination register.
464static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
465 return Desc.getNumDefs() < Desc.getNumOperands() &&
466 Desc.getOperandConstraint(OpNum: Desc.getNumDefs(), Constraint: MCOI::TIED_TO) == 0;
467}
468
469// RISC-V Specific Machine Operand Flags
470enum {
471 MO_None = 0,
472 MO_CALL = 1,
473 MO_LO = 3,
474 MO_HI = 4,
475 MO_PCREL_LO = 5,
476 MO_PCREL_HI = 6,
477 MO_GOT_HI = 7,
478 MO_TPREL_LO = 8,
479 MO_TPREL_HI = 9,
480 MO_TPREL_ADD = 10,
481 MO_TLS_GOT_HI = 11,
482 MO_TLS_GD_HI = 12,
483 MO_TLSDESC_HI = 13,
484 MO_TLSDESC_LOAD_LO = 14,
485 MO_TLSDESC_ADD_LO = 15,
486 MO_TLSDESC_CALL = 16,
487 MO_QC_ACCESS = 17,
488
489 // Used to differentiate between target-specific "direct" flags and "bitmask"
490 // flags. A machine operand can only have one "direct" flag, but can have
491 // multiple "bitmask" flags.
492 MO_DIRECT_FLAG_MASK = 31
493};
494} // namespace RISCVII
495
496// Describes the predecessor/successor bits used in the FENCE instruction.
497namespace RISCVFenceField {
498enum FenceField {
499 I = 8,
500 O = 4,
501 R = 2,
502 W = 1
503};
504}
505
506// Describes the supported floating point rounding mode encodings.
507namespace RISCVFPRndMode {
508enum RoundingMode {
509 RNE = 0,
510 RTZ = 1,
511 RDN = 2,
512 RUP = 3,
513 RMM = 4,
514 DYN = 7,
515 Invalid
516};
517
518inline static StringRef roundingModeToString(RoundingMode RndMode) {
519 switch (RndMode) {
520 default:
521 llvm_unreachable("Unknown floating point rounding mode");
522 case RISCVFPRndMode::RNE:
523 return "rne";
524 case RISCVFPRndMode::RTZ:
525 return "rtz";
526 case RISCVFPRndMode::RDN:
527 return "rdn";
528 case RISCVFPRndMode::RUP:
529 return "rup";
530 case RISCVFPRndMode::RMM:
531 return "rmm";
532 case RISCVFPRndMode::DYN:
533 return "dyn";
534 }
535}
536
537inline static RoundingMode stringToRoundingMode(StringRef Str) {
538 return StringSwitch<RoundingMode>(Str)
539 .Case(S: "rne", Value: RISCVFPRndMode::RNE)
540 .Case(S: "rtz", Value: RISCVFPRndMode::RTZ)
541 .Case(S: "rdn", Value: RISCVFPRndMode::RDN)
542 .Case(S: "rup", Value: RISCVFPRndMode::RUP)
543 .Case(S: "rmm", Value: RISCVFPRndMode::RMM)
544 .Case(S: "dyn", Value: RISCVFPRndMode::DYN)
545 .Default(Value: RISCVFPRndMode::Invalid);
546}
547
548inline static bool isValidRoundingMode(unsigned Mode) {
549 switch (Mode) {
550 default:
551 return false;
552 case RISCVFPRndMode::RNE:
553 case RISCVFPRndMode::RTZ:
554 case RISCVFPRndMode::RDN:
555 case RISCVFPRndMode::RUP:
556 case RISCVFPRndMode::RMM:
557 case RISCVFPRndMode::DYN:
558 return true;
559 }
560}
561} // namespace RISCVFPRndMode
562
563namespace XSMTVTypeMode {
564enum SMTVTypeMode {
565 // Define the different SMT VType modes here
566 SMT_I4 = 2,
567 SMT_I8 = 3,
568 Invalid
569};
570
571inline static StringRef SMTVTypeModeToString(SMTVTypeMode TypeMode) {
572 switch (TypeMode) {
573 default:
574 llvm_unreachable("Unknown VType mode of SpacemiT Integer Matrix");
575 case XSMTVTypeMode::SMT_I4:
576 return "i4";
577 case XSMTVTypeMode::SMT_I8:
578 return "i8";
579 }
580}
581
582inline static SMTVTypeMode stringToSMTVTypeMode(StringRef Str) {
583 return StringSwitch<SMTVTypeMode>(Str)
584 .Case(S: "i4", Value: XSMTVTypeMode::SMT_I4)
585 .Case(S: "i8", Value: XSMTVTypeMode::SMT_I8)
586 .Default(Value: XSMTVTypeMode::Invalid);
587}
588
589inline static bool isValidSMTVTypeMode(unsigned Mode) {
590 switch (Mode) {
591 default:
592 return false;
593 case XSMTVTypeMode::SMT_I4:
594 case XSMTVTypeMode::SMT_I8:
595 return true;
596 }
597}
598
599} // namespace XSMTVTypeMode
600
601namespace RISCVVXRndMode {
602enum RoundingMode {
603 RNU = 0,
604 RNE = 1,
605 RDN = 2,
606 ROD = 3,
607 Invalid
608};
609
610inline static StringRef roundingModeToString(RoundingMode RndMode) {
611 switch (RndMode) {
612 default:
613 llvm_unreachable("Unknown vector fixed-point rounding mode");
614 case RISCVVXRndMode::RNU:
615 return "rnu";
616 case RISCVVXRndMode::RNE:
617 return "rne";
618 case RISCVVXRndMode::RDN:
619 return "rdn";
620 case RISCVVXRndMode::ROD:
621 return "rod";
622 }
623}
624
625inline static RoundingMode stringToRoundingMode(StringRef Str) {
626 return StringSwitch<RoundingMode>(Str)
627 .Case(S: "rnu", Value: RISCVVXRndMode::RNU)
628 .Case(S: "rne", Value: RISCVVXRndMode::RNE)
629 .Case(S: "rdn", Value: RISCVVXRndMode::RDN)
630 .Case(S: "rod", Value: RISCVVXRndMode::ROD)
631 .Default(Value: RISCVVXRndMode::Invalid);
632}
633
634inline static bool isValidRoundingMode(unsigned Mode) {
635 switch (Mode) {
636 default:
637 return false;
638 case RISCVVXRndMode::RNU:
639 case RISCVVXRndMode::RNE:
640 case RISCVVXRndMode::RDN:
641 case RISCVVXRndMode::ROD:
642 return true;
643 }
644}
645} // namespace RISCVVXRndMode
646
647namespace RISCVExceptFlags {
648enum ExceptionFlag {
649 NX = 0x01, // Inexact
650 UF = 0x02, // Underflow
651 OF = 0x04, // Overflow
652 DZ = 0x08, // Divide by zero
653 NV = 0x10, // Invalid operation
654 ALL = 0x1F // Mask for all accrued exception flags
655};
656}
657
658//===----------------------------------------------------------------------===//
659// Floating-point Immediates
660//
661
662namespace RISCVLoadFPImm {
663float getFPImm(unsigned Imm);
664
665/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
666/// immediate value. If the value cannot be represented as a 5-bit binary
667/// encoding, then return -1.
668int getLoadFPImm(APFloat FPImm);
669} // namespace RISCVLoadFPImm
670
671namespace RISCVSysReg {
672struct SysReg {
673 StringTable::Offset Name;
674 unsigned Encoding;
675 // FIXME: add these additional fields when needed.
676 // Privilege Access: Read, Write, Read-Only.
677 // unsigned ReadWrite;
678 // Privilege Mode: User, System or Machine.
679 // unsigned Mode;
680 // Check field name.
681 // unsigned Extra;
682 // Register number without the privilege bits.
683 // unsigned Number;
684 FeatureBitset FeaturesRequired;
685 bool IsRV32Only;
686 bool IsAltName;
687 bool IsDeprecatedName;
688
689 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
690 // Not in 32-bit mode.
691 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
692 return false;
693 // No required feature associated with the system register.
694 if (FeaturesRequired.none())
695 return true;
696 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
697 }
698};
699
700#define GET_SysRegEncodings_DECL
701#define GET_SysRegsList_DECL
702#include "RISCVGenSearchableTables.inc"
703} // end namespace RISCVSysReg
704
705namespace RISCVInsnOpcode {
706struct RISCVOpcode {
707 StringTable::Offset Name;
708 uint8_t Value;
709};
710
711#define GET_RISCVOpcodesList_DECL
712#include "RISCVGenSearchableTables.inc"
713} // end namespace RISCVInsnOpcode
714
715namespace RISCVABI {
716
717enum ABI {
718 ABI_ILP32,
719 ABI_ILP32F,
720 ABI_ILP32D,
721 ABI_ILP32E,
722 ABI_IL32PC64,
723 ABI_IL32PC64F,
724 ABI_IL32PC64D,
725 ABI_IL32PC64E,
726 ABI_LP64,
727 ABI_LP64F,
728 ABI_LP64D,
729 ABI_LP64E,
730 ABI_L64PC128,
731 ABI_L64PC128F,
732 ABI_L64PC128D,
733 ABI_CHERIOT,
734 ABI_Unknown
735};
736
737// Returns the target ABI, or else a StringError if the requested ABIName is
738// not supported for the subtarget's triple and FeatureBits combination.
739Expected<ABI> computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName);
740
741ABI getTargetABI(StringRef ABIName);
742
743// Returns the register used to hold the stack pointer after realignment.
744MCRegister getBPReg();
745
746// Returns the register holding shadow call stack pointer.
747MCRegister getSCSPReg();
748
749} // namespace RISCVABI
750
751namespace RISCVFeatures {
752
753// Validates if the given combination of features are valid for the target
754// triple. Exits with report_fatal_error if not.
755void validate(const Triple &TT, const FeatureBitset &FeatureBits);
756
757llvm::Expected<std::unique_ptr<RISCVISAInfo>>
758parseFeatureBits(const MCSubtargetInfo &STI);
759
760} // namespace RISCVFeatures
761
762namespace RISCVRVC {
763bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
764bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
765} // namespace RISCVRVC
766
767namespace RISCVZC {
768enum RLISTENCODE {
769 RA = 4,
770 RA_S0,
771 RA_S0_S1,
772 RA_S0_S2,
773 RA_S0_S3,
774 RA_S0_S4,
775 RA_S0_S5,
776 RA_S0_S6,
777 RA_S0_S7,
778 RA_S0_S8,
779 RA_S0_S9,
780 // note - to include s10, s11 must also be included
781 RA_S0_S11,
782 INVALID_RLIST,
783};
784
785inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
786 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
787 switch (EndReg.id()) {
788 case RISCV::X1:
789 return RLISTENCODE::RA;
790 case RISCV::X8:
791 return RLISTENCODE::RA_S0;
792 case RISCV::X9:
793 return RLISTENCODE::RA_S0_S1;
794 case RISCV::X18:
795 return RLISTENCODE::RA_S0_S2;
796 case RISCV::X19:
797 return RLISTENCODE::RA_S0_S3;
798 case RISCV::X20:
799 return RLISTENCODE::RA_S0_S4;
800 case RISCV::X21:
801 return RLISTENCODE::RA_S0_S5;
802 case RISCV::X22:
803 return RLISTENCODE::RA_S0_S6;
804 case RISCV::X23:
805 return RLISTENCODE::RA_S0_S7;
806 case RISCV::X24:
807 return RLISTENCODE::RA_S0_S8;
808 case RISCV::X25:
809 return RLISTENCODE::RA_S0_S9;
810 case RISCV::X27:
811 return RLISTENCODE::RA_S0_S11;
812 default:
813 llvm_unreachable("Undefined input.");
814 }
815}
816
817inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
818 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
819 "Unexpected number of registers");
820 if (NumRegs == 13)
821 return RLISTENCODE::RA_S0_S11;
822
823 return RLISTENCODE::RA + (NumRegs - 1);
824}
825
826inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
827 assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&
828 "Invalid Rlist");
829 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;
830 // s10 and s11 are saved together.
831 if (RlistVal == RLISTENCODE::RA_S0_S11)
832 ++NumRegs;
833
834 unsigned RegSize = IsRV64 ? 8 : 4;
835 return alignTo(Value: NumRegs * RegSize, Align: 16);
836}
837
838void printRegList(unsigned RlistEncode, raw_ostream &OS);
839} // namespace RISCVZC
840
841namespace RISCVVInversePseudosTable {
842struct PseudoInfo {
843 uint16_t Pseudo;
844 uint16_t BaseInstr;
845 uint16_t VLMul : 3;
846 uint16_t SEW : 8;
847 uint16_t IsAltFmt : 1;
848};
849
850#define GET_RISCVVInversePseudosTable_DECL
851#include "RISCVGenSearchableTables.inc"
852
853inline const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul,
854 uint8_t SEW, bool IsAltFmt = false) {
855 return getBaseInfoImpl(BaseInstr, VLMul, SEW, IsAltFmt);
856}
857} // namespace RISCVVInversePseudosTable
858
859namespace RISCV {
860struct VLSEGPseudo {
861 uint16_t NF : 4;
862 uint16_t Masked : 1;
863 uint16_t Strided : 1;
864 uint16_t FF : 1;
865 uint16_t Log2SEW : 3;
866 uint16_t LMUL : 3;
867 uint16_t Pseudo;
868};
869
870struct VLXSEGPseudo {
871 uint16_t NF : 4;
872 uint16_t Masked : 1;
873 uint16_t Ordered : 1;
874 uint16_t Log2SEW : 3;
875 uint16_t LMUL : 3;
876 uint16_t IndexLMUL : 3;
877 uint16_t Pseudo;
878};
879
880struct VSSEGPseudo {
881 uint16_t NF : 4;
882 uint16_t Masked : 1;
883 uint16_t Strided : 1;
884 uint16_t Log2SEW : 3;
885 uint16_t LMUL : 3;
886 uint16_t Pseudo;
887};
888
889struct VSXSEGPseudo {
890 uint16_t NF : 4;
891 uint16_t Masked : 1;
892 uint16_t Ordered : 1;
893 uint16_t Log2SEW : 3;
894 uint16_t LMUL : 3;
895 uint16_t IndexLMUL : 3;
896 uint16_t Pseudo;
897};
898
899struct VLEPseudo {
900 uint16_t Masked : 1;
901 uint16_t Strided : 1;
902 uint16_t FF : 1;
903 uint16_t Log2SEW : 3;
904 uint16_t LMUL : 3;
905 uint16_t Pseudo;
906};
907
908struct VSEPseudo {
909 uint16_t Masked : 1;
910 uint16_t Strided : 1;
911 uint16_t Log2SEW : 3;
912 uint16_t LMUL : 3;
913 uint16_t Pseudo;
914};
915
916struct VLX_VSXPseudo {
917 uint16_t Masked : 1;
918 uint16_t Ordered : 1;
919 uint16_t Log2SEW : 3;
920 uint16_t LMUL : 3;
921 uint16_t IndexLMUL : 3;
922 uint16_t Pseudo;
923};
924
925struct NDSVLNPseudo {
926 uint16_t Masked : 1;
927 uint16_t Unsigned : 1;
928 uint16_t Log2SEW : 3;
929 uint16_t LMUL : 3;
930 uint16_t Pseudo;
931};
932
933#define GET_RISCVVSSEGTable_DECL
934#define GET_RISCVVLSEGTable_DECL
935#define GET_RISCVVLXSEGTable_DECL
936#define GET_RISCVVSXSEGTable_DECL
937#define GET_RISCVVLETable_DECL
938#define GET_RISCVVSETable_DECL
939#define GET_RISCVVLXTable_DECL
940#define GET_RISCVVSXTable_DECL
941#define GET_RISCVNDSVLNTable_DECL
942#include "RISCVGenSearchableTables.inc"
943
944inline bool isValidYBNDSWImm(int64_t Imm) {
945 return (Imm >= 1 && Imm <= 255) ||
946 (Imm >= 256 && Imm <= 504 && (Imm % 8) == 0) ||
947 (Imm >= 512 && Imm <= 4096 && (Imm % 16) == 0);
948}
949} // namespace RISCV
950
951} // namespace llvm
952
953#endif
954