1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/TargetParser/RISCVISAInfo.h"
23#include "llvm/TargetParser/RISCVTargetParser.h"
24#include "llvm/TargetParser/SubtargetFeature.h"
25
26namespace llvm {
27
28namespace RISCVOp {
29enum OperandType : unsigned {
30 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
31 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
32 OPERAND_UIMM2,
33 OPERAND_UIMM2_LSB0,
34 OPERAND_UIMM3,
35 OPERAND_UIMM4,
36 OPERAND_UIMM5,
37 OPERAND_UIMM5_NONZERO,
38 OPERAND_UIMM5_GT3,
39 OPERAND_UIMM5_PLUS1,
40 OPERAND_UIMM5_GE6_PLUS1,
41 OPERAND_UIMM5_LSB0,
42 OPERAND_UIMM5_SLIST,
43 OPERAND_UIMM6,
44 OPERAND_UIMM6_LSB0,
45 OPERAND_UIMM7,
46 OPERAND_UIMM7_LSB00,
47 OPERAND_UIMM7_LSB000,
48 OPERAND_UIMM8_LSB00,
49 OPERAND_UIMM8,
50 OPERAND_UIMM8_LSB000,
51 OPERAND_UIMM8_GE32,
52 OPERAND_UIMM9_LSB000,
53 OPERAND_UIMM9,
54 OPERAND_UIMM10,
55 OPERAND_UIMM10_LSB00_NONZERO,
56 OPERAND_UIMM11,
57 OPERAND_UIMM12,
58 OPERAND_UIMM14_LSB00,
59 OPERAND_UIMM16,
60 OPERAND_UIMM16_NONZERO,
61 OPERAND_UIMMLOG2XLEN,
62 OPERAND_UIMMLOG2XLEN_NONZERO,
63 OPERAND_UIMM32,
64 OPERAND_UIMM48,
65 OPERAND_UIMM64,
66 OPERAND_THREE,
67 OPERAND_FOUR,
68 OPERAND_IMM5_ZIBI,
69 OPERAND_SIMM5,
70 OPERAND_SIMM5_NONZERO,
71 OPERAND_SIMM5_PLUS1,
72 OPERAND_SIMM6,
73 OPERAND_SIMM6_NONZERO,
74 OPERAND_SIMM8_UNSIGNED,
75 OPERAND_SIMM10,
76 OPERAND_SIMM10_LSB0000_NONZERO,
77 OPERAND_SIMM10_UNSIGNED,
78 OPERAND_SIMM11,
79 OPERAND_SIMM12_LSB00000,
80 OPERAND_SIMM16,
81 OPERAND_SIMM16_NONZERO,
82 OPERAND_SIMM20,
83 OPERAND_SIMM20_LI,
84 OPERAND_SIMM26,
85 OPERAND_CLUI_IMM,
86 OPERAND_VTYPEI10,
87 OPERAND_VTYPEI11,
88 OPERAND_RVKRNUM,
89 OPERAND_RVKRNUM_0_7,
90 OPERAND_RVKRNUM_1_10,
91 OPERAND_RVKRNUM_2_14,
92 OPERAND_RLIST,
93 OPERAND_RLIST_S0,
94 OPERAND_STACKADJ,
95 // Operand is a 3-bit rounding mode, '111' indicates FRM register.
96 // Represents 'frm' argument passing to floating-point operations.
97 OPERAND_FRMARG,
98 // Operand is a 3-bit rounding mode where only RTZ is valid.
99 OPERAND_RTZARG,
100 // Condition code used by select and short forward branch pseudos.
101 OPERAND_COND_CODE,
102 // Ordering for atomic pseudos.
103 OPERAND_ATOMIC_ORDERING,
104 // Vector policy operand.
105 OPERAND_VEC_POLICY,
106 // Vector SEW operand. Stores in log2(SEW).
107 OPERAND_SEW,
108 // Special SEW for mask only instructions. Always 0.
109 OPERAND_SEW_MASK,
110 // Vector rounding mode for VXRM or FRM.
111 OPERAND_VEC_RM,
112 // Vtype operand for XSfmm extension.
113 OPERAND_XSFMM_VTYPE,
114 // XSfmm twiden operand.
115 OPERAND_XSFMM_TWIDEN,
116 OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_TWIDEN,
117
118 OPERAND_UIMM20_LUI,
119 OPERAND_UIMM20_AUIPC,
120
121 // Simm12 or constant pool, global, basicblock, etc.
122 OPERAND_SIMM12_LO,
123
124 OPERAND_BARE_SIMM32,
125
126 // Operand is either a register or uimm5, this is used by V extension pseudo
127 // instructions to represent a value that be passed as AVL to either vsetvli
128 // or vsetivli.
129 OPERAND_AVL,
130
131 OPERAND_VMASK,
132};
133} // namespace RISCVOp
134
135// RISCVII - This namespace holds all of the target specific flags that
136// instruction info tracks. All definitions must match RISCVInstrFormats.td.
137namespace RISCVII {
138enum {
139 InstFormatPseudo = 0,
140 InstFormatR = 1,
141 InstFormatR4 = 2,
142 InstFormatI = 3,
143 InstFormatS = 4,
144 InstFormatB = 5,
145 InstFormatU = 6,
146 InstFormatJ = 7,
147 InstFormatCR = 8,
148 InstFormatCI = 9,
149 InstFormatCSS = 10,
150 InstFormatCIW = 11,
151 InstFormatCL = 12,
152 InstFormatCS = 13,
153 InstFormatCA = 14,
154 InstFormatCB = 15,
155 InstFormatCJ = 16,
156 InstFormatCU = 17,
157 InstFormatCLB = 18,
158 InstFormatCLH = 19,
159 InstFormatCSB = 20,
160 InstFormatCSH = 21,
161 InstFormatQC_EAI = 22,
162 InstFormatQC_EI = 23,
163 InstFormatQC_EB = 24,
164 InstFormatQC_EJ = 25,
165 InstFormatQC_ES = 26,
166 InstFormatNDS_BRANCH_10 = 27,
167 InstFormatOther = 31,
168
169 InstFormatMask = 31,
170 InstFormatShift = 0,
171
172 RVVConstraintShift = InstFormatShift + 5,
173 VS2Constraint = 0b001 << RVVConstraintShift,
174 VS1Constraint = 0b010 << RVVConstraintShift,
175 VMConstraint = 0b100 << RVVConstraintShift,
176 RVVConstraintMask = 0b111 << RVVConstraintShift,
177
178 VLMulShift = RVVConstraintShift + 3,
179 VLMulMask = 0b111 << VLMulShift,
180
181 // Is this a _TIED vector pseudo instruction. For these instructions we
182 // shouldn't skip the tied operand when converting to MC instructions.
183 IsTiedPseudoShift = VLMulShift + 3,
184 IsTiedPseudoMask = 1 << IsTiedPseudoShift,
185
186 // Does this instruction have a SEW operand. It will be the last explicit
187 // operand unless there is a vector policy operand. Used by RVV Pseudos.
188 HasSEWOpShift = IsTiedPseudoShift + 1,
189 HasSEWOpMask = 1 << HasSEWOpShift,
190
191 // Does this instruction have a VL operand. It will be the second to last
192 // explicit operand unless there is a vector policy operand. Used by RVV
193 // Pseudos.
194 HasVLOpShift = HasSEWOpShift + 1,
195 HasVLOpMask = 1 << HasVLOpShift,
196
197 // Does this instruction have a vector policy operand. It will be the last
198 // explicit operand. Used by RVV Pseudos.
199 HasVecPolicyOpShift = HasVLOpShift + 1,
200 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
201
202 // Is this instruction a vector widening reduction instruction. Used by RVV
203 // Pseudos.
204 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
205 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
206
207 // Does this instruction care about mask policy. If it is not, the mask policy
208 // could be either agnostic or undisturbed. For example, unmasked, store, and
209 // reduction operations result would not be affected by mask policy, so
210 // compiler has free to select either one.
211 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
212 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
213
214 // Indicates that the result can be considered sign extended from bit 31. Some
215 // instructions with this flag aren't W instructions, but are either sign
216 // extended from a smaller size, always outputs a small integer, or put zeros
217 // in bits 63:31. Used by the SExtWRemoval pass.
218 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
219 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
220
221 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
222 HasRoundModeOpMask = 1 << HasRoundModeOpShift,
223
224 UsesVXRMShift = HasRoundModeOpShift + 1,
225 UsesVXRMMask = 1 << UsesVXRMShift,
226
227 // Indicates whether these instructions can partially overlap between source
228 // registers and destination registers according to the vector spec.
229 // 0 -> not a vector pseudo
230 // 1 -> default value for vector pseudos. not widening or narrowing.
231 // 2 -> narrowing case
232 // 3 -> widening case
233 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
234 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
235
236 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,
237 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,
238
239 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
240 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,
241
242 // Indicates the EEW of a vector instruction's destination operand.
243 // 0 -> 1
244 // 1 -> SEW
245 // 2 -> SEW * 2
246 // 3 -> SEW * 4
247 DestEEWShift = ElementsDependOnMaskShift + 1,
248 DestEEWMask = 3ULL << DestEEWShift,
249
250 ReadsPastVLShift = DestEEWShift + 2,
251 ReadsPastVLMask = 1ULL << ReadsPastVLShift,
252
253 // 0 -> Don't care about altfmt bit in VTYPE.
254 // 1 -> Is not altfmt.
255 // 2 -> Is altfmt(BF16).
256 AltFmtTypeShift = ReadsPastVLShift + 1,
257 AltFmtTypeMask = 3ULL << AltFmtTypeShift,
258
259 // XSfmmbase
260 HasTWidenOpShift = AltFmtTypeShift + 2,
261 HasTWidenOpMask = 1ULL << HasTWidenOpShift,
262
263 HasTMOpShift = HasTWidenOpShift + 1,
264 HasTMOpMask = 1ULL << HasTMOpShift,
265
266 HasTKOpShift = HasTMOpShift + 1,
267 HasTKOpMask = 1ULL << HasTKOpShift,
268};
269
270// Helper functions to read TSFlags.
271/// \returns the format of the instruction.
272static inline unsigned getFormat(uint64_t TSFlags) {
273 return (TSFlags & InstFormatMask) >> InstFormatShift;
274}
275/// \returns the LMUL for the instruction.
276static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
277 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
278}
279/// \returns true if this a _TIED pseudo.
280static inline bool isTiedPseudo(uint64_t TSFlags) {
281 return TSFlags & IsTiedPseudoMask;
282}
283/// \returns true if there is a SEW operand for the instruction.
284static inline bool hasSEWOp(uint64_t TSFlags) {
285 return TSFlags & HasSEWOpMask;
286}
287/// \returns true if there is a VL operand for the instruction.
288static inline bool hasVLOp(uint64_t TSFlags) {
289 return TSFlags & HasVLOpMask;
290}
291/// \returns true if there is a vector policy operand for this instruction.
292static inline bool hasVecPolicyOp(uint64_t TSFlags) {
293 return TSFlags & HasVecPolicyOpMask;
294}
295/// \returns true if it is a vector widening reduction instruction.
296static inline bool isRVVWideningReduction(uint64_t TSFlags) {
297 return TSFlags & IsRVVWideningReductionMask;
298}
299/// \returns true if mask policy is valid for the instruction.
300static inline bool usesMaskPolicy(uint64_t TSFlags) {
301 return TSFlags & UsesMaskPolicyMask;
302}
303
304/// \returns true if there is a rounding mode operand for this instruction
305static inline bool hasRoundModeOp(uint64_t TSFlags) {
306 return TSFlags & HasRoundModeOpMask;
307}
308
309enum class AltFmtType { DontCare, NotAltFmt, AltFmt };
310static inline AltFmtType getAltFmtType(uint64_t TSFlags) {
311 return static_cast<AltFmtType>((TSFlags & AltFmtTypeMask) >> AltFmtTypeShift);
312}
313
314/// \returns true if this instruction uses vxrm
315static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
316
317/// \returns true if the elements in the body are affected by VL,
318/// e.g. vslide1down.vx/vredsum.vs/viota.m
319static inline bool elementsDependOnVL(uint64_t TSFlags) {
320 return TSFlags & ElementsDependOnVLMask;
321}
322
323/// \returns true if the elements in the body are affected by the mask,
324/// e.g. vredsum.vs/viota.m
325static inline bool elementsDependOnMask(uint64_t TSFlags) {
326 return TSFlags & ElementsDependOnMaskMask;
327}
328
329/// \returns true if the instruction may read elements past VL, e.g.
330/// vslidedown/vrgather
331static inline bool readsPastVL(uint64_t TSFlags) {
332 return TSFlags & ReadsPastVLMask;
333}
334
335// XSfmmbase
336static inline bool hasTWidenOp(uint64_t TSFlags) {
337 return TSFlags & HasTWidenOpMask;
338}
339
340static inline bool hasTMOp(uint64_t TSFlags) { return TSFlags & HasTMOpMask; }
341
342static inline bool hasTKOp(uint64_t TSFlags) { return TSFlags & HasTKOpMask; }
343
344static inline unsigned getTWidenOpNum(const MCInstrDesc &Desc) {
345 assert(hasTWidenOp(Desc.TSFlags));
346 return Desc.getNumOperands() - 1;
347}
348
349static inline unsigned getTNOpNum(const MCInstrDesc &Desc) {
350 const uint64_t TSFlags = Desc.TSFlags;
351 assert(hasTWidenOp(TSFlags) && hasVLOp(TSFlags));
352 unsigned Offset = 3;
353 if (hasTKOp(TSFlags))
354 Offset = 4;
355 return Desc.getNumOperands() - Offset;
356}
357
358static inline unsigned getTMOpNum(const MCInstrDesc &Desc) {
359 const uint64_t TSFlags = Desc.TSFlags;
360 assert(hasTWidenOp(TSFlags) && hasTMOp(TSFlags));
361 if (hasTKOp(TSFlags))
362 return Desc.getNumOperands() - 5;
363 // vtzero.t
364 return Desc.getNumOperands() - 4;
365}
366
367static inline unsigned getTKOpNum(const MCInstrDesc &Desc) {
368 [[maybe_unused]] const uint64_t TSFlags = Desc.TSFlags;
369 assert(hasTWidenOp(TSFlags) && hasTKOp(TSFlags));
370 return Desc.getNumOperands() - 3;
371}
372
373static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
374 const uint64_t TSFlags = Desc.TSFlags;
375 // This method is only called if we expect to have a VL operand, and all
376 // instructions with VL also have SEW.
377 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
378 // In Xsfmmbase, TN is an alias for VL, so here we use the same TSFlags bit.
379 if (hasTWidenOp(TSFlags))
380 return getTNOpNum(Desc);
381 unsigned Offset = 2;
382 if (hasVecPolicyOp(TSFlags))
383 Offset = 3;
384 return Desc.getNumOperands() - Offset;
385}
386
387static inline MCRegister
388getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
389 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
390 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
391 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
392}
393
394static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
395 const uint64_t TSFlags = Desc.TSFlags;
396 assert(hasSEWOp(TSFlags));
397 unsigned Offset = 1;
398 if (hasVecPolicyOp(TSFlags) || hasTWidenOp(TSFlags))
399 Offset = 2;
400 return Desc.getNumOperands() - Offset;
401}
402
403static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
404 assert(hasVecPolicyOp(Desc.TSFlags));
405 return Desc.getNumOperands() - 1;
406}
407
408/// \returns the index to the rounding mode immediate value if any, otherwise
409/// returns -1.
410static inline int getFRMOpNum(const MCInstrDesc &Desc) {
411 const uint64_t TSFlags = Desc.TSFlags;
412 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
413 return -1;
414
415 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
416 assert(Idx >= 0 && "No rm operand?");
417 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
418 "Operand has wrong type");
419
420 return Idx;
421}
422
423/// \returns the index to the rounding mode immediate value if any, otherwise
424/// returns -1.
425static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
426 const uint64_t TSFlags = Desc.TSFlags;
427 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
428 return -1;
429
430 int Idx = RISCV::getNamedOperandIdx(Opcode: Desc.getOpcode(), Name: RISCV::OpName::rm);
431 assert(Idx >= 0 && "No rm operand?");
432 assert(Desc.operands()[Idx].OperandType == RISCVOp::OPERAND_VEC_RM &&
433 "Operand has wrong type");
434
435 return Idx;
436}
437
438// Is the first def operand tied to the first use operand. This is true for
439// vector pseudo instructions that have a merge operand for tail/mask
440// undisturbed. It's also true for vector FMA instructions where one of the
441// operands is also the destination register.
442static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
443 return Desc.getNumDefs() < Desc.getNumOperands() &&
444 Desc.getOperandConstraint(OpNum: Desc.getNumDefs(), Constraint: MCOI::TIED_TO) == 0;
445}
446
447// RISC-V Specific Machine Operand Flags
448enum {
449 MO_None = 0,
450 MO_CALL = 1,
451 MO_LO = 3,
452 MO_HI = 4,
453 MO_PCREL_LO = 5,
454 MO_PCREL_HI = 6,
455 MO_GOT_HI = 7,
456 MO_TPREL_LO = 8,
457 MO_TPREL_HI = 9,
458 MO_TPREL_ADD = 10,
459 MO_TLS_GOT_HI = 11,
460 MO_TLS_GD_HI = 12,
461 MO_TLSDESC_HI = 13,
462 MO_TLSDESC_LOAD_LO = 14,
463 MO_TLSDESC_ADD_LO = 15,
464 MO_TLSDESC_CALL = 16,
465
466 // Used to differentiate between target-specific "direct" flags and "bitmask"
467 // flags. A machine operand can only have one "direct" flag, but can have
468 // multiple "bitmask" flags.
469 MO_DIRECT_FLAG_MASK = 31
470};
471} // namespace RISCVII
472
473// Describes the predecessor/successor bits used in the FENCE instruction.
474namespace RISCVFenceField {
475enum FenceField {
476 I = 8,
477 O = 4,
478 R = 2,
479 W = 1
480};
481}
482
483// Describes the supported floating point rounding mode encodings.
484namespace RISCVFPRndMode {
485enum RoundingMode {
486 RNE = 0,
487 RTZ = 1,
488 RDN = 2,
489 RUP = 3,
490 RMM = 4,
491 DYN = 7,
492 Invalid
493};
494
495inline static StringRef roundingModeToString(RoundingMode RndMode) {
496 switch (RndMode) {
497 default:
498 llvm_unreachable("Unknown floating point rounding mode");
499 case RISCVFPRndMode::RNE:
500 return "rne";
501 case RISCVFPRndMode::RTZ:
502 return "rtz";
503 case RISCVFPRndMode::RDN:
504 return "rdn";
505 case RISCVFPRndMode::RUP:
506 return "rup";
507 case RISCVFPRndMode::RMM:
508 return "rmm";
509 case RISCVFPRndMode::DYN:
510 return "dyn";
511 }
512}
513
514inline static RoundingMode stringToRoundingMode(StringRef Str) {
515 return StringSwitch<RoundingMode>(Str)
516 .Case(S: "rne", Value: RISCVFPRndMode::RNE)
517 .Case(S: "rtz", Value: RISCVFPRndMode::RTZ)
518 .Case(S: "rdn", Value: RISCVFPRndMode::RDN)
519 .Case(S: "rup", Value: RISCVFPRndMode::RUP)
520 .Case(S: "rmm", Value: RISCVFPRndMode::RMM)
521 .Case(S: "dyn", Value: RISCVFPRndMode::DYN)
522 .Default(Value: RISCVFPRndMode::Invalid);
523}
524
525inline static bool isValidRoundingMode(unsigned Mode) {
526 switch (Mode) {
527 default:
528 return false;
529 case RISCVFPRndMode::RNE:
530 case RISCVFPRndMode::RTZ:
531 case RISCVFPRndMode::RDN:
532 case RISCVFPRndMode::RUP:
533 case RISCVFPRndMode::RMM:
534 case RISCVFPRndMode::DYN:
535 return true;
536 }
537}
538} // namespace RISCVFPRndMode
539
540namespace RISCVVXRndMode {
541enum RoundingMode {
542 RNU = 0,
543 RNE = 1,
544 RDN = 2,
545 ROD = 3,
546 Invalid
547};
548
549inline static StringRef roundingModeToString(RoundingMode RndMode) {
550 switch (RndMode) {
551 default:
552 llvm_unreachable("Unknown vector fixed-point rounding mode");
553 case RISCVVXRndMode::RNU:
554 return "rnu";
555 case RISCVVXRndMode::RNE:
556 return "rne";
557 case RISCVVXRndMode::RDN:
558 return "rdn";
559 case RISCVVXRndMode::ROD:
560 return "rod";
561 }
562}
563
564inline static RoundingMode stringToRoundingMode(StringRef Str) {
565 return StringSwitch<RoundingMode>(Str)
566 .Case(S: "rnu", Value: RISCVVXRndMode::RNU)
567 .Case(S: "rne", Value: RISCVVXRndMode::RNE)
568 .Case(S: "rdn", Value: RISCVVXRndMode::RDN)
569 .Case(S: "rod", Value: RISCVVXRndMode::ROD)
570 .Default(Value: RISCVVXRndMode::Invalid);
571}
572
573inline static bool isValidRoundingMode(unsigned Mode) {
574 switch (Mode) {
575 default:
576 return false;
577 case RISCVVXRndMode::RNU:
578 case RISCVVXRndMode::RNE:
579 case RISCVVXRndMode::RDN:
580 case RISCVVXRndMode::ROD:
581 return true;
582 }
583}
584} // namespace RISCVVXRndMode
585
586namespace RISCVExceptFlags {
587enum ExceptionFlag {
588 NX = 0x01, // Inexact
589 UF = 0x02, // Underflow
590 OF = 0x04, // Overflow
591 DZ = 0x08, // Divide by zero
592 NV = 0x10, // Invalid operation
593 ALL = 0x1F // Mask for all accrued exception flags
594};
595}
596
597//===----------------------------------------------------------------------===//
598// Floating-point Immediates
599//
600
601namespace RISCVLoadFPImm {
602float getFPImm(unsigned Imm);
603
604/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
605/// immediate value. If the value cannot be represented as a 5-bit binary
606/// encoding, then return -1.
607int getLoadFPImm(APFloat FPImm);
608} // namespace RISCVLoadFPImm
609
610namespace RISCVSysReg {
611struct SysReg {
612 const char Name[32];
613 unsigned Encoding;
614 // FIXME: add these additional fields when needed.
615 // Privilege Access: Read, Write, Read-Only.
616 // unsigned ReadWrite;
617 // Privilege Mode: User, System or Machine.
618 // unsigned Mode;
619 // Check field name.
620 // unsigned Extra;
621 // Register number without the privilege bits.
622 // unsigned Number;
623 FeatureBitset FeaturesRequired;
624 bool IsRV32Only;
625 bool IsAltName;
626 bool IsDeprecatedName;
627
628 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
629 // Not in 32-bit mode.
630 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
631 return false;
632 // No required feature associated with the system register.
633 if (FeaturesRequired.none())
634 return true;
635 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
636 }
637};
638
639#define GET_SysRegEncodings_DECL
640#define GET_SysRegsList_DECL
641#include "RISCVGenSearchableTables.inc"
642} // end namespace RISCVSysReg
643
644namespace RISCVInsnOpcode {
645struct RISCVOpcode {
646 char Name[10];
647 uint8_t Value;
648};
649
650#define GET_RISCVOpcodesList_DECL
651#include "RISCVGenSearchableTables.inc"
652} // end namespace RISCVInsnOpcode
653
654namespace RISCVABI {
655
656enum ABI {
657 ABI_ILP32,
658 ABI_ILP32F,
659 ABI_ILP32D,
660 ABI_ILP32E,
661 ABI_LP64,
662 ABI_LP64F,
663 ABI_LP64D,
664 ABI_LP64E,
665 ABI_Unknown
666};
667
668// Returns the target ABI, or else a StringError if the requested ABIName is
669// not supported for the given TT and FeatureBits combination.
670ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
671 StringRef ABIName);
672
673ABI getTargetABI(StringRef ABIName);
674
675// Returns the register used to hold the stack pointer after realignment.
676MCRegister getBPReg();
677
678// Returns the register holding shadow call stack pointer.
679MCRegister getSCSPReg();
680
681} // namespace RISCVABI
682
683namespace RISCVFeatures {
684
685// Validates if the given combination of features are valid for the target
686// triple. Exits with report_fatal_error if not.
687void validate(const Triple &TT, const FeatureBitset &FeatureBits);
688
689llvm::Expected<std::unique_ptr<RISCVISAInfo>>
690parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
691
692} // namespace RISCVFeatures
693
694namespace RISCVRVC {
695bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
696bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
697} // namespace RISCVRVC
698
699namespace RISCVZC {
700enum RLISTENCODE {
701 RA = 4,
702 RA_S0,
703 RA_S0_S1,
704 RA_S0_S2,
705 RA_S0_S3,
706 RA_S0_S4,
707 RA_S0_S5,
708 RA_S0_S6,
709 RA_S0_S7,
710 RA_S0_S8,
711 RA_S0_S9,
712 // note - to include s10, s11 must also be included
713 RA_S0_S11,
714 INVALID_RLIST,
715};
716
717inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
718 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
719 switch (EndReg.id()) {
720 case RISCV::X1:
721 return RLISTENCODE::RA;
722 case RISCV::X8:
723 return RLISTENCODE::RA_S0;
724 case RISCV::X9:
725 return RLISTENCODE::RA_S0_S1;
726 case RISCV::X18:
727 return RLISTENCODE::RA_S0_S2;
728 case RISCV::X19:
729 return RLISTENCODE::RA_S0_S3;
730 case RISCV::X20:
731 return RLISTENCODE::RA_S0_S4;
732 case RISCV::X21:
733 return RLISTENCODE::RA_S0_S5;
734 case RISCV::X22:
735 return RLISTENCODE::RA_S0_S6;
736 case RISCV::X23:
737 return RLISTENCODE::RA_S0_S7;
738 case RISCV::X24:
739 return RLISTENCODE::RA_S0_S8;
740 case RISCV::X25:
741 return RLISTENCODE::RA_S0_S9;
742 case RISCV::X27:
743 return RLISTENCODE::RA_S0_S11;
744 default:
745 llvm_unreachable("Undefined input.");
746 }
747}
748
749inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
750 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
751 "Unexpected number of registers");
752 if (NumRegs == 13)
753 return RLISTENCODE::RA_S0_S11;
754
755 return RLISTENCODE::RA + (NumRegs - 1);
756}
757
758inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
759 assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&
760 "Invalid Rlist");
761 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;
762 // s10 and s11 are saved together.
763 if (RlistVal == RLISTENCODE::RA_S0_S11)
764 ++NumRegs;
765
766 unsigned RegSize = IsRV64 ? 8 : 4;
767 return alignTo(Value: NumRegs * RegSize, Align: 16);
768}
769
770void printRegList(unsigned RlistEncode, raw_ostream &OS);
771} // namespace RISCVZC
772
773namespace RISCVVInversePseudosTable {
774struct PseudoInfo {
775 uint16_t Pseudo;
776 uint16_t BaseInstr;
777 uint16_t VLMul : 3;
778 uint16_t SEW : 8;
779 uint16_t IsAltFmt : 1;
780};
781
782#define GET_RISCVVInversePseudosTable_DECL
783#include "RISCVGenSearchableTables.inc"
784
785inline const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul,
786 uint8_t SEW, bool IsAltFmt = false) {
787 return getBaseInfoImpl(BaseInstr, VLMul, SEW, IsAltFmt);
788}
789} // namespace RISCVVInversePseudosTable
790
791namespace RISCV {
792struct VLSEGPseudo {
793 uint16_t NF : 4;
794 uint16_t Masked : 1;
795 uint16_t Strided : 1;
796 uint16_t FF : 1;
797 uint16_t Log2SEW : 3;
798 uint16_t LMUL : 3;
799 uint16_t Pseudo;
800};
801
802struct VLXSEGPseudo {
803 uint16_t NF : 4;
804 uint16_t Masked : 1;
805 uint16_t Ordered : 1;
806 uint16_t Log2SEW : 3;
807 uint16_t LMUL : 3;
808 uint16_t IndexLMUL : 3;
809 uint16_t Pseudo;
810};
811
812struct VSSEGPseudo {
813 uint16_t NF : 4;
814 uint16_t Masked : 1;
815 uint16_t Strided : 1;
816 uint16_t Log2SEW : 3;
817 uint16_t LMUL : 3;
818 uint16_t Pseudo;
819};
820
821struct VSXSEGPseudo {
822 uint16_t NF : 4;
823 uint16_t Masked : 1;
824 uint16_t Ordered : 1;
825 uint16_t Log2SEW : 3;
826 uint16_t LMUL : 3;
827 uint16_t IndexLMUL : 3;
828 uint16_t Pseudo;
829};
830
831struct VLEPseudo {
832 uint16_t Masked : 1;
833 uint16_t Strided : 1;
834 uint16_t FF : 1;
835 uint16_t Log2SEW : 3;
836 uint16_t LMUL : 3;
837 uint16_t Pseudo;
838};
839
840struct VSEPseudo {
841 uint16_t Masked : 1;
842 uint16_t Strided : 1;
843 uint16_t Log2SEW : 3;
844 uint16_t LMUL : 3;
845 uint16_t Pseudo;
846};
847
848struct VLX_VSXPseudo {
849 uint16_t Masked : 1;
850 uint16_t Ordered : 1;
851 uint16_t Log2SEW : 3;
852 uint16_t LMUL : 3;
853 uint16_t IndexLMUL : 3;
854 uint16_t Pseudo;
855};
856
857struct NDSVLNPseudo {
858 uint16_t Masked : 1;
859 uint16_t Unsigned : 1;
860 uint16_t Log2SEW : 3;
861 uint16_t LMUL : 3;
862 uint16_t Pseudo;
863};
864
865#define GET_RISCVVSSEGTable_DECL
866#define GET_RISCVVLSEGTable_DECL
867#define GET_RISCVVLXSEGTable_DECL
868#define GET_RISCVVSXSEGTable_DECL
869#define GET_RISCVVLETable_DECL
870#define GET_RISCVVSETable_DECL
871#define GET_RISCVVLXTable_DECL
872#define GET_RISCVVSXTable_DECL
873#define GET_RISCVNDSVLNTable_DECL
874#include "RISCVGenSearchableTables.inc"
875} // namespace RISCV
876
877} // namespace llvm
878
879#endif
880