1//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15
16#include "RISCV.h"
17#include "RISCVRegisterInfo.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19#include "llvm/IR/DiagnosticInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "RISCVGenInstrInfo.inc"
23#include "RISCVGenRegisterInfo.inc"
24
25namespace llvm {
26
27// If Value is of the form C1<<C2, where C1 = 3, 5 or 9,
28// returns log2(C1 - 1) and assigns Shift = C2.
29// Otherwise, returns 0.
30template <typename T> int isShifted359(T Value, int &Shift) {
31 if (Value == 0)
32 return 0;
33 Shift = llvm::countr_zero(Value);
34 switch (Value >> Shift) {
35 case 3:
36 return 1;
37 case 5:
38 return 2;
39 case 9:
40 return 3;
41 default:
42 return 0;
43 }
44}
45
46class RISCVSubtarget;
47
48static const MachineMemOperand::Flags MONontemporalBit0 =
49 MachineMemOperand::MOTargetFlag1;
50static const MachineMemOperand::Flags MONontemporalBit1 =
51 MachineMemOperand::MOTargetFlag2;
52
53namespace RISCVCC {
54
55enum CondCode {
56 COND_EQ,
57 COND_NE,
58 COND_LT,
59 COND_GE,
60 COND_LTU,
61 COND_GEU,
62 COND_INVALID
63};
64
65CondCode getInverseBranchCondition(CondCode);
66unsigned getInverseBranchOpcode(unsigned BCC);
67unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
68
69} // end of namespace RISCVCC
70
71// RISCV MachineCombiner patterns
72enum RISCVMachineCombinerPattern : unsigned {
73 FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START,
74 FMADD_XA,
75 FMSUB,
76 FNMSUB,
77 SHXADD_ADD_SLLI_OP1,
78 SHXADD_ADD_SLLI_OP2,
79};
80
81class RISCVInstrInfo : public RISCVGenInstrInfo {
82 const RISCVRegisterInfo RegInfo;
83
84public:
85 explicit RISCVInstrInfo(const RISCVSubtarget &STI);
86
87 const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
88
89 const TargetRegisterClass *getInlineAsmMemoryOperandRegClass(
90 InlineAsm::ConstraintCode C) const override {
91 return &RISCV::GPRRegClass;
92 }
93
94 MCInst getNop() const override;
95
96 Register isLoadFromStackSlot(const MachineInstr &MI,
97 int &FrameIndex) const override;
98 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
99 TypeSize &MemBytes) const override;
100 Register isStoreToStackSlot(const MachineInstr &MI,
101 int &FrameIndex) const override;
102 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
103 TypeSize &MemBytes) const override;
104
105 bool isReMaterializableImpl(const MachineInstr &MI) const override;
106
107 bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
108 return MI.getOpcode() == RISCV::ADDI && MI.getOperand(i: 1).isReg() &&
109 MI.getOperand(i: 1).getReg() == RISCV::X0;
110 }
111
112 void copyPhysRegVector(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
114 MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
115 const TargetRegisterClass *RegClass) const;
116 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
117 const DebugLoc &DL, Register DstReg, Register SrcReg,
118 bool KillSrc, bool RenamableDest = false,
119 bool RenamableSrc = false) const override;
120
121 void storeRegToStackSlot(
122 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
123 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
124
125 Register VReg,
126 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
127
128 void loadRegFromStackSlot(
129 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
130 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
131 unsigned SubReg = 0,
132 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
133
134 using TargetInstrInfo::foldMemoryOperandImpl;
135 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
136 ArrayRef<unsigned> Ops, int FrameIndex,
137 MachineInstr *&CopyMI,
138 LiveIntervals *LIS = nullptr,
139 VirtRegMap *VRM = nullptr) const override;
140
141 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
142 ArrayRef<unsigned> Ops,
143 MachineInstr &LoadMI,
144 MachineInstr *&CopyMI,
145 LiveIntervals *LIS = nullptr,
146 VirtRegMap *VRM = nullptr) const override;
147
148 // Materializes the given integer Val into DstReg.
149 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
150 const DebugLoc &DL, Register DstReg, uint64_t Val,
151 MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
152 bool DstRenamable = false, bool DstIsDead = false) const;
153
154 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
155
156 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
157 MachineBasicBlock *&FBB,
158 SmallVectorImpl<MachineOperand> &Cond,
159 bool AllowModify) const override;
160
161 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
162 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
163 const DebugLoc &dl,
164 int *BytesAdded = nullptr) const override;
165
166 void insertIndirectBranch(MachineBasicBlock &MBB,
167 MachineBasicBlock &NewDestBB,
168 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
169 int64_t BrOffset, RegScavenger *RS) const override;
170
171 unsigned removeBranch(MachineBasicBlock &MBB,
172 int *BytesRemoved = nullptr) const override;
173
174 bool
175 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
176
177 bool optimizeCondBranch(MachineInstr &MI) const override;
178
179 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
180
181 bool isBranchOffsetInRange(unsigned BranchOpc,
182 int64_t BrOffset) const override;
183
184 MachineInstr *optimizeSelect(MachineInstr &MI,
185 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
186 bool) const override;
187
188 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
189
190 std::optional<DestSourcePair>
191 isCopyInstrImpl(const MachineInstr &MI) const override;
192
193 bool verifyInstruction(const MachineInstr &MI,
194 StringRef &ErrInfo) const override;
195
196 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
197 const MachineInstr &AddrI,
198 ExtAddrMode &AM) const override;
199
200 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
201 const ExtAddrMode &AM) const override;
202
203 bool getMemOperandsWithOffsetWidth(
204 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
205 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
206 const TargetRegisterInfo *TRI) const override;
207
208 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
209 int64_t Offset1, bool OffsetIsScalable1,
210 ArrayRef<const MachineOperand *> BaseOps2,
211 int64_t Offset2, bool OffsetIsScalable2,
212 unsigned ClusterSize,
213 unsigned NumBytes) const override;
214
215 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
216 const MachineOperand *&BaseOp,
217 int64_t &Offset, LocationSize &Width,
218 const TargetRegisterInfo *TRI) const;
219
220 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
221 const MachineInstr &MIb) const override;
222
223
224 std::pair<unsigned, unsigned>
225 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
226
227 ArrayRef<std::pair<unsigned, const char *>>
228 getSerializableDirectMachineOperandTargetFlags() const override;
229
230 // Return true if the function can safely be outlined from.
231 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
232 bool OutlineFromLinkOnceODRs) const override;
233
234 // Return true if MBB is safe to outline from, and return any target-specific
235 // information in Flags.
236 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
237 unsigned &Flags) const override;
238
239 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
240
241 // Return true if the candidate should be discarded from outlining.
242 bool analyzeCandidate(outliner::Candidate &C) const;
243 // Calculate target-specific information for a set of outlining candidates.
244 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
245 getOutliningCandidateInfo(
246 const MachineModuleInfo &MMI,
247 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
248 unsigned MinRepeats) const override;
249
250 // Return if/how a given MachineInstr should be outlined.
251 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
252 MachineBasicBlock::iterator &MBBI,
253 unsigned Flags) const override;
254
255 // Insert a custom frame for outlined functions.
256 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
257 const outliner::OutlinedFunction &OF) const override;
258
259 // Insert a call to an outlined function into a given basic block.
260 MachineBasicBlock::iterator
261 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator &It, MachineFunction &MF,
263 outliner::Candidate &C) const override;
264
265 void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator Iter, DebugLoc &DL,
267 bool AllowSideEffects = true) const override;
268
269 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
270 Register Reg) const override;
271
272 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
273 unsigned &SrcOpIdx2) const override;
274 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
275 unsigned OpIdx1,
276 unsigned OpIdx2) const override;
277
278 bool simplifyInstruction(MachineInstr &MI) const override;
279
280 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
281 LiveIntervals *LIS) const override;
282
283 // MIR printer helper function to annotate Operands with a comment.
284 std::string
285 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
286 unsigned OpIdx,
287 const TargetRegisterInfo *TRI) const override;
288
289 /// Generate code to multiply the value in DestReg by Amt - handles all
290 /// the common optimizations for this idiom, and supports fallback for
291 /// subtargets which don't support multiply instructions.
292 void mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
293 MachineBasicBlock::iterator II, const DebugLoc &DL,
294 Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const;
295
296 bool useMachineCombiner() const override { return true; }
297
298 MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
299
300 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
301
302 bool getMachineCombinerPatterns(MachineInstr &Root,
303 SmallVectorImpl<unsigned> &Patterns,
304 bool DoRegPressureReduce) const override;
305
306 void
307 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
308 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
309
310 void genAlternativeCodeSequence(
311 MachineInstr &Root, unsigned Pattern,
312 SmallVectorImpl<MachineInstr *> &InsInstrs,
313 SmallVectorImpl<MachineInstr *> &DelInstrs,
314 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
315
316 bool hasReassociableOperands(const MachineInstr &Inst,
317 const MachineBasicBlock *MBB) const override;
318
319 bool hasReassociableSibling(const MachineInstr &Inst,
320 bool &Commuted) const override;
321
322 bool isAssociativeAndCommutative(const MachineInstr &Inst,
323 bool Invert) const override;
324
325 std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
326
327 void getReassociateOperandIndices(
328 const MachineInstr &Root, unsigned Pattern,
329 std::array<unsigned, 5> &OperandIndices) const override;
330
331 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
332 getSerializableMachineMemOperandTargetFlags() const override;
333
334 unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
335
336 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
337 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
338
339 bool isHighLatencyDef(int Opc) const override;
340
341 InstSizeVerifyMode
342 getInstSizeVerifyMode(const MachineInstr &MI) const override {
343 // FIXME: These Xqci instructions can compress from a 6 byte to a 4 byte
344 // instruction but getInstSizeInBytes unilaterally returns 2 for any
345 // compressible instruction.
346 switch (MI.getOpcode()) {
347 case RISCV::QC_E_LW:
348 case RISCV::QC_E_LB:
349 case RISCV::QC_E_LH:
350 case RISCV::QC_E_LBU:
351 case RISCV::QC_E_LHU:
352 case RISCV::QC_E_SW:
353 case RISCV::QC_E_SB:
354 case RISCV::QC_E_SH:
355 case RISCV::QC_E_JAL:
356 case RISCV::QC_E_J:
357 case RISCV::QC_E_LI:
358 case RISCV::QC_E_ADDI:
359 case RISCV::QC_E_ANDI:
360 case RISCV::QC_E_ORI:
361 case RISCV::QC_E_XORI:
362 case RISCV::QC_E_ADDAI:
363 case RISCV::QC_E_ANDAI:
364 case RISCV::QC_E_ORAI:
365 case RISCV::QC_E_XORAI:
366 case RISCV::QC_E_BEQI:
367 case RISCV::QC_E_BNEI:
368 case RISCV::QC_E_BLTI:
369 case RISCV::QC_E_BGEUI:
370 case RISCV::QC_E_BLTUI:
371 case RISCV::QC_E_BGEI:
372 return InstSizeVerifyMode::NoVerify;
373 default:
374 return InstSizeVerifyMode::AllowOverEstimate;
375 }
376 }
377
378 /// Return true if \p MI is a COPY to a vector register of a specific \p LMul,
379 /// or any kind of vector registers when \p LMul is zero.
380 bool isVRegCopy(const MachineInstr *MI, unsigned LMul = 0) const;
381
382 /// Return true if the instruction requires an NTL hint to be emitted.
383 bool requiresNTLHint(const MachineInstr &MI) const;
384
385 /// Return true if moving \p From down to \p To won't cause any physical
386 /// register reads or writes to be clobbered and no visible side effects are
387 /// affected. From and To must be in the same block.
388 static bool isSafeToMove(const MachineInstr &From,
389 const MachineBasicBlock::iterator &To);
390
391 /// Return true if pairing the given load or store may be paired with another.
392 static bool isPairableLdStInstOpc(unsigned Opc);
393
394 static bool isLdStSafeToPair(const MachineInstr &LdSt,
395 const TargetRegisterInfo *TRI);
396#define GET_INSTRINFO_HELPER_DECLS
397#include "RISCVGenInstrInfo.inc"
398
399 static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc);
400
401 /// Return the result of the evaluation of C0 CC C1, where CC is a
402 /// RISCVCC::CondCode.
403 static bool evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0, int64_t C1);
404
405 /// Return true if the operand is a load immediate instruction and
406 /// sets Imm to the immediate value.
407 static bool isFromLoadImm(const MachineRegisterInfo &MRI,
408 const MachineOperand &Op, int64_t &Imm);
409
410protected:
411 const RISCVSubtarget &STI;
412
413private:
414 bool isVectorAssociativeAndCommutative(const MachineInstr &MI,
415 bool Invert = false) const;
416 bool areRVVInstsReassociable(const MachineInstr &MI1,
417 const MachineInstr &MI2) const;
418 bool hasReassociableVectorSibling(const MachineInstr &Inst,
419 bool &Commuted) const;
420};
421
422namespace RISCV {
423
424// Returns true if the given MI is an RVV instruction opcode for which we may
425// expect to see a FrameIndex operand.
426bool isRVVSpill(const MachineInstr &MI);
427
428/// Return true if \p MI is a copy that will be lowered to one or more vmvNr.vs.
429bool isVectorCopy(const TargetRegisterInfo *TRI, const MachineInstr &MI);
430
431std::optional<std::pair<unsigned, unsigned>>
432isRVVSpillForZvlsseg(unsigned Opcode);
433
434// Return true if both input instructions have equal rounding mode. If at least
435// one of the instructions does not have rounding mode, false will be returned.
436bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
437
438// If \p Opcode is a .vx vector instruction, returns the lower number of bits
439// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
440// returns null.
441std::optional<unsigned> getVectorLowDemandedScalarBits(unsigned Opcode,
442 unsigned Log2SEW);
443
444// Returns the MC opcode of RVV pseudo instruction.
445unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);
446
447// For a (non-pseudo) RVV instruction \p Desc and the given \p Log2SEW, returns
448// the log2 EEW of the destination operand.
449unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);
450
451// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
452static constexpr int64_t VLMaxSentinel = -1LL;
453
454/// Given two VL operands, do we know that LHS <= RHS?
455bool isVLKnownLE(const MachineRegisterInfo &MRI, const MachineOperand &LHS,
456 const MachineOperand &RHS);
457
458// Mask assignments for floating-point
459static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
460static constexpr unsigned FPMASK_Negative_Normal = 0x002;
461static constexpr unsigned FPMASK_Negative_Subnormal = 0x004;
462static constexpr unsigned FPMASK_Negative_Zero = 0x008;
463static constexpr unsigned FPMASK_Positive_Zero = 0x010;
464static constexpr unsigned FPMASK_Positive_Subnormal = 0x020;
465static constexpr unsigned FPMASK_Positive_Normal = 0x040;
466static constexpr unsigned FPMASK_Positive_Infinity = 0x080;
467static constexpr unsigned FPMASK_Signaling_NaN = 0x100;
468static constexpr unsigned FPMASK_Quiet_NaN = 0x200;
469} // namespace RISCV
470
471namespace RISCVVPseudosTable {
472
473struct PseudoInfo {
474 uint16_t Pseudo;
475 uint16_t BaseInstr;
476 uint16_t VLMul : 3;
477 uint16_t SEW : 8;
478 uint16_t IsAltFmt : 1;
479};
480
481#define GET_RISCVVPseudosTable_DECL
482#include "RISCVGenSearchableTables.inc"
483
484} // end namespace RISCVVPseudosTable
485
486namespace RISCV {
487
488struct RISCVMaskedPseudoInfo {
489 uint16_t MaskedPseudo;
490 uint16_t UnmaskedPseudo;
491 uint8_t MaskOpIdx;
492};
493#define GET_RISCVMaskedPseudosTable_DECL
494#include "RISCVGenSearchableTables.inc"
495} // end namespace RISCV
496
497} // end namespace llvm
498#endif
499