1//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15
16#include "RISCV.h"
17#include "RISCVRegisterInfo.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19#include "llvm/IR/DiagnosticInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "RISCVGenInstrInfo.inc"
23#include "RISCVGenRegisterInfo.inc"
24
25namespace llvm {
26
27// If Value is of the form C1<<C2, where C1 = 3, 5 or 9,
28// returns log2(C1 - 1) and assigns Shift = C2.
29// Otherwise, returns 0.
30template <typename T> int isShifted359(T Value, int &Shift) {
31 if (Value == 0)
32 return 0;
33 Shift = llvm::countr_zero(Value);
34 switch (Value >> Shift) {
35 case 3:
36 return 1;
37 case 5:
38 return 2;
39 case 9:
40 return 3;
41 default:
42 return 0;
43 }
44}
45
46class RISCVSubtarget;
47
48static const MachineMemOperand::Flags MONontemporalBit0 =
49 MachineMemOperand::MOTargetFlag1;
50static const MachineMemOperand::Flags MONontemporalBit1 =
51 MachineMemOperand::MOTargetFlag2;
52
53namespace RISCVCC {
54
55enum CondCode {
56 COND_EQ,
57 COND_NE,
58 COND_LT,
59 COND_GE,
60 COND_LTU,
61 COND_GEU,
62 COND_INVALID
63};
64
65CondCode getInverseBranchCondition(CondCode);
66unsigned getInverseBranchOpcode(unsigned BCC);
67unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
68
69} // end of namespace RISCVCC
70
71// RISCV MachineCombiner patterns
72enum RISCVMachineCombinerPattern : unsigned {
73 FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START,
74 FMADD_XA,
75 FMSUB,
76 FNMSUB,
77 SHXADD_ADD_SLLI_OP1,
78 SHXADD_ADD_SLLI_OP2,
79};
80
81class RISCVInstrInfo : public RISCVGenInstrInfo {
82 const RISCVRegisterInfo RegInfo;
83
84public:
85 explicit RISCVInstrInfo(const RISCVSubtarget &STI);
86
87 const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
88
89 MCInst getNop() const override;
90
91 Register isLoadFromStackSlot(const MachineInstr &MI,
92 int &FrameIndex) const override;
93 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
94 TypeSize &MemBytes) const override;
95 Register isStoreToStackSlot(const MachineInstr &MI,
96 int &FrameIndex) const override;
97 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
98 TypeSize &MemBytes) const override;
99
100 bool isReMaterializableImpl(const MachineInstr &MI) const override;
101
102 bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
103 return MI.getOpcode() == RISCV::ADDI && MI.getOperand(i: 1).isReg() &&
104 MI.getOperand(i: 1).getReg() == RISCV::X0;
105 }
106
107 void copyPhysRegVector(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
109 MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
110 const TargetRegisterClass *RegClass) const;
111 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
112 const DebugLoc &DL, Register DstReg, Register SrcReg,
113 bool KillSrc, bool RenamableDest = false,
114 bool RenamableSrc = false) const override;
115
116 void storeRegToStackSlot(
117 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
118 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
119
120 Register VReg,
121 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
122
123 void loadRegFromStackSlot(
124 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
125 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
126 unsigned SubReg = 0,
127 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
128
129 using TargetInstrInfo::foldMemoryOperandImpl;
130 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
131 ArrayRef<unsigned> Ops, int FrameIndex,
132 MachineInstr *&CopyMI,
133 LiveIntervals *LIS = nullptr,
134 VirtRegMap *VRM = nullptr) const override;
135
136 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
137 ArrayRef<unsigned> Ops,
138 MachineInstr &LoadMI,
139 MachineInstr *&CopyMI,
140 LiveIntervals *LIS = nullptr,
141 VirtRegMap *VRM = nullptr) const override;
142
143 // Materializes the given integer Val into DstReg.
144 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
145 const DebugLoc &DL, Register DstReg, uint64_t Val,
146 MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
147 bool DstRenamable = false, bool DstIsDead = false) const;
148
149 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
150
151 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
152 MachineBasicBlock *&FBB,
153 SmallVectorImpl<MachineOperand> &Cond,
154 bool AllowModify) const override;
155
156 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
157 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
158 const DebugLoc &dl,
159 int *BytesAdded = nullptr) const override;
160
161 void insertIndirectBranch(MachineBasicBlock &MBB,
162 MachineBasicBlock &NewDestBB,
163 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
164 int64_t BrOffset, RegScavenger *RS) const override;
165
166 unsigned removeBranch(MachineBasicBlock &MBB,
167 int *BytesRemoved = nullptr) const override;
168
169 bool
170 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
171
172 bool optimizeCondBranch(MachineInstr &MI) const override;
173
174 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
175
176 bool isBranchOffsetInRange(unsigned BranchOpc,
177 int64_t BrOffset) const override;
178
179 MachineInstr *optimizeSelect(MachineInstr &MI,
180 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
181 bool) const override;
182
183 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
184
185 std::optional<DestSourcePair>
186 isCopyInstrImpl(const MachineInstr &MI) const override;
187
188 bool verifyInstruction(const MachineInstr &MI,
189 StringRef &ErrInfo) const override;
190
191 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
192 const MachineInstr &AddrI,
193 ExtAddrMode &AM) const override;
194
195 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
196 const ExtAddrMode &AM) const override;
197
198 bool getMemOperandsWithOffsetWidth(
199 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
200 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
201 const TargetRegisterInfo *TRI) const override;
202
203 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
204 int64_t Offset1, bool OffsetIsScalable1,
205 ArrayRef<const MachineOperand *> BaseOps2,
206 int64_t Offset2, bool OffsetIsScalable2,
207 unsigned ClusterSize,
208 unsigned NumBytes) const override;
209
210 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
211 const MachineOperand *&BaseOp,
212 int64_t &Offset, LocationSize &Width,
213 const TargetRegisterInfo *TRI) const;
214
215 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
216 const MachineInstr &MIb) const override;
217
218
219 std::pair<unsigned, unsigned>
220 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
221
222 ArrayRef<std::pair<unsigned, const char *>>
223 getSerializableDirectMachineOperandTargetFlags() const override;
224
225 // Return true if the function can safely be outlined from.
226 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
227 bool OutlineFromLinkOnceODRs) const override;
228
229 // Return true if MBB is safe to outline from, and return any target-specific
230 // information in Flags.
231 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
232 unsigned &Flags) const override;
233
234 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
235
236 // Return true if the candidate should be discarded from outlining.
237 bool analyzeCandidate(outliner::Candidate &C) const;
238 // Calculate target-specific information for a set of outlining candidates.
239 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
240 getOutliningCandidateInfo(
241 const MachineModuleInfo &MMI,
242 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
243 unsigned MinRepeats) const override;
244
245 // Return if/how a given MachineInstr should be outlined.
246 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
247 MachineBasicBlock::iterator &MBBI,
248 unsigned Flags) const override;
249
250 // Insert a custom frame for outlined functions.
251 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
252 const outliner::OutlinedFunction &OF) const override;
253
254 // Insert a call to an outlined function into a given basic block.
255 MachineBasicBlock::iterator
256 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
257 MachineBasicBlock::iterator &It, MachineFunction &MF,
258 outliner::Candidate &C) const override;
259
260 void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
261 MachineBasicBlock::iterator Iter, DebugLoc &DL,
262 bool AllowSideEffects = true) const override;
263
264 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
265 Register Reg) const override;
266
267 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
268 unsigned &SrcOpIdx2) const override;
269 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
270 unsigned OpIdx1,
271 unsigned OpIdx2) const override;
272
273 bool simplifyInstruction(MachineInstr &MI) const override;
274
275 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
276 LiveIntervals *LIS) const override;
277
278 // MIR printer helper function to annotate Operands with a comment.
279 std::string
280 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
281 unsigned OpIdx,
282 const TargetRegisterInfo *TRI) const override;
283
284 /// Generate code to multiply the value in DestReg by Amt - handles all
285 /// the common optimizations for this idiom, and supports fallback for
286 /// subtargets which don't support multiply instructions.
287 void mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
288 MachineBasicBlock::iterator II, const DebugLoc &DL,
289 Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const;
290
291 bool useMachineCombiner() const override { return true; }
292
293 MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
294
295 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
296
297 bool getMachineCombinerPatterns(MachineInstr &Root,
298 SmallVectorImpl<unsigned> &Patterns,
299 bool DoRegPressureReduce) const override;
300
301 void
302 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
303 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
304
305 void genAlternativeCodeSequence(
306 MachineInstr &Root, unsigned Pattern,
307 SmallVectorImpl<MachineInstr *> &InsInstrs,
308 SmallVectorImpl<MachineInstr *> &DelInstrs,
309 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
310
311 bool hasReassociableOperands(const MachineInstr &Inst,
312 const MachineBasicBlock *MBB) const override;
313
314 bool hasReassociableSibling(const MachineInstr &Inst,
315 bool &Commuted) const override;
316
317 bool isAssociativeAndCommutative(const MachineInstr &Inst,
318 bool Invert) const override;
319
320 std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
321
322 void getReassociateOperandIndices(
323 const MachineInstr &Root, unsigned Pattern,
324 std::array<unsigned, 5> &OperandIndices) const override;
325
326 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
327 getSerializableMachineMemOperandTargetFlags() const override;
328
329 unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
330
331 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
332 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
333
334 bool isHighLatencyDef(int Opc) const override;
335
336 /// Return true if \p MI is a COPY to a vector register of a specific \p LMul,
337 /// or any kind of vector registers when \p LMul is zero.
338 bool isVRegCopy(const MachineInstr *MI, unsigned LMul = 0) const;
339
340 /// Return true if the instruction requires an NTL hint to be emitted.
341 bool requiresNTLHint(const MachineInstr &MI) const;
342
343 /// Return true if moving \p From down to \p To won't cause any physical
344 /// register reads or writes to be clobbered and no visible side effects are
345 /// affected. From and To must be in the same block.
346 static bool isSafeToMove(const MachineInstr &From,
347 const MachineBasicBlock::iterator &To);
348
349 /// Return true if pairing the given load or store may be paired with another.
350 static bool isPairableLdStInstOpc(unsigned Opc);
351
352 static bool isLdStSafeToPair(const MachineInstr &LdSt,
353 const TargetRegisterInfo *TRI);
354#define GET_INSTRINFO_HELPER_DECLS
355#include "RISCVGenInstrInfo.inc"
356
357 static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc);
358
359 /// Return the result of the evaluation of C0 CC C1, where CC is a
360 /// RISCVCC::CondCode.
361 static bool evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0, int64_t C1);
362
363 /// Return true if the operand is a load immediate instruction and
364 /// sets Imm to the immediate value.
365 static bool isFromLoadImm(const MachineRegisterInfo &MRI,
366 const MachineOperand &Op, int64_t &Imm);
367
368protected:
369 const RISCVSubtarget &STI;
370
371private:
372 bool isVectorAssociativeAndCommutative(const MachineInstr &MI,
373 bool Invert = false) const;
374 bool areRVVInstsReassociable(const MachineInstr &MI1,
375 const MachineInstr &MI2) const;
376 bool hasReassociableVectorSibling(const MachineInstr &Inst,
377 bool &Commuted) const;
378};
379
380namespace RISCV {
381
382// Returns true if the given MI is an RVV instruction opcode for which we may
383// expect to see a FrameIndex operand.
384bool isRVVSpill(const MachineInstr &MI);
385
386/// Return true if \p MI is a copy that will be lowered to one or more vmvNr.vs.
387bool isVectorCopy(const TargetRegisterInfo *TRI, const MachineInstr &MI);
388
389std::optional<std::pair<unsigned, unsigned>>
390isRVVSpillForZvlsseg(unsigned Opcode);
391
392// Return true if both input instructions have equal rounding mode. If at least
393// one of the instructions does not have rounding mode, false will be returned.
394bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
395
396// If \p Opcode is a .vx vector instruction, returns the lower number of bits
397// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
398// returns null.
399std::optional<unsigned> getVectorLowDemandedScalarBits(unsigned Opcode,
400 unsigned Log2SEW);
401
402// Returns the MC opcode of RVV pseudo instruction.
403unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);
404
405// For a (non-pseudo) RVV instruction \p Desc and the given \p Log2SEW, returns
406// the log2 EEW of the destination operand.
407unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);
408
409// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
410static constexpr int64_t VLMaxSentinel = -1LL;
411
412/// Given two VL operands, do we know that LHS <= RHS?
413bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS);
414
415// Mask assignments for floating-point
416static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
417static constexpr unsigned FPMASK_Negative_Normal = 0x002;
418static constexpr unsigned FPMASK_Negative_Subnormal = 0x004;
419static constexpr unsigned FPMASK_Negative_Zero = 0x008;
420static constexpr unsigned FPMASK_Positive_Zero = 0x010;
421static constexpr unsigned FPMASK_Positive_Subnormal = 0x020;
422static constexpr unsigned FPMASK_Positive_Normal = 0x040;
423static constexpr unsigned FPMASK_Positive_Infinity = 0x080;
424static constexpr unsigned FPMASK_Signaling_NaN = 0x100;
425static constexpr unsigned FPMASK_Quiet_NaN = 0x200;
426} // namespace RISCV
427
428namespace RISCVVPseudosTable {
429
430struct PseudoInfo {
431 uint16_t Pseudo;
432 uint16_t BaseInstr;
433 uint16_t VLMul : 3;
434 uint16_t SEW : 8;
435 uint16_t IsAltFmt : 1;
436};
437
438#define GET_RISCVVPseudosTable_DECL
439#include "RISCVGenSearchableTables.inc"
440
441} // end namespace RISCVVPseudosTable
442
443namespace RISCV {
444
445struct RISCVMaskedPseudoInfo {
446 uint16_t MaskedPseudo;
447 uint16_t UnmaskedPseudo;
448 uint8_t MaskOpIdx;
449};
450#define GET_RISCVMaskedPseudosTable_DECL
451#include "RISCVGenSearchableTables.inc"
452} // end namespace RISCV
453
454} // end namespace llvm
455#endif
456