1//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15
16#include "RISCV.h"
17#include "RISCVRegisterInfo.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19#include "llvm/IR/DiagnosticInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "RISCVGenInstrInfo.inc"
23#include "RISCVGenRegisterInfo.inc"
24
25namespace llvm {
26
27// If Value is of the form C1<<C2, where C1 = 3, 5 or 9,
28// returns log2(C1 - 1) and assigns Shift = C2.
29// Otherwise, returns 0.
30template <typename T> int isShifted359(T Value, int &Shift) {
31 if (Value == 0)
32 return 0;
33 Shift = llvm::countr_zero(Value);
34 switch (Value >> Shift) {
35 case 3:
36 return 1;
37 case 5:
38 return 2;
39 case 9:
40 return 3;
41 default:
42 return 0;
43 }
44}
45
46class RISCVSubtarget;
47
48static const MachineMemOperand::Flags MONontemporalBit0 =
49 MachineMemOperand::MOTargetFlag1;
50static const MachineMemOperand::Flags MONontemporalBit1 =
51 MachineMemOperand::MOTargetFlag2;
52
53namespace RISCVCC {
54
55enum CondCode {
56 COND_EQ,
57 COND_NE,
58 COND_LT,
59 COND_GE,
60 COND_LTU,
61 COND_GEU,
62 COND_INVALID
63};
64
65CondCode getInverseBranchCondition(CondCode);
66unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
67
68} // end of namespace RISCVCC
69
70// RISCV MachineCombiner patterns
71enum RISCVMachineCombinerPattern : unsigned {
72 FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START,
73 FMADD_XA,
74 FMSUB,
75 FNMSUB,
76 SHXADD_ADD_SLLI_OP1,
77 SHXADD_ADD_SLLI_OP2,
78};
79
80class RISCVInstrInfo : public RISCVGenInstrInfo {
81 const RISCVRegisterInfo RegInfo;
82
83public:
84 explicit RISCVInstrInfo(const RISCVSubtarget &STI);
85
86 const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
87
88 MCInst getNop() const override;
89
90 Register isLoadFromStackSlot(const MachineInstr &MI,
91 int &FrameIndex) const override;
92 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
93 TypeSize &MemBytes) const override;
94 Register isStoreToStackSlot(const MachineInstr &MI,
95 int &FrameIndex) const override;
96 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
97 TypeSize &MemBytes) const override;
98
99 bool isReMaterializableImpl(const MachineInstr &MI) const override;
100
101 bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
102 return MI.getOpcode() == RISCV::ADDI && MI.getOperand(i: 1).isReg() &&
103 MI.getOperand(i: 1).getReg() == RISCV::X0;
104 }
105
106 void copyPhysRegVector(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
108 MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
109 const TargetRegisterClass *RegClass) const;
110 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
111 const DebugLoc &DL, Register DstReg, Register SrcReg,
112 bool KillSrc, bool RenamableDest = false,
113 bool RenamableSrc = false) const override;
114
115 void storeRegToStackSlot(
116 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
117 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
118
119 Register VReg,
120 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
121
122 void loadRegFromStackSlot(
123 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
124 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
125 unsigned SubReg = 0,
126 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
127
128 using TargetInstrInfo::foldMemoryOperandImpl;
129 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
130 ArrayRef<unsigned> Ops,
131 MachineBasicBlock::iterator InsertPt,
132 int FrameIndex,
133 LiveIntervals *LIS = nullptr,
134 VirtRegMap *VRM = nullptr) const override;
135
136 MachineInstr *foldMemoryOperandImpl(
137 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
138 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
139 LiveIntervals *LIS = nullptr) const override;
140
141 // Materializes the given integer Val into DstReg.
142 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
143 const DebugLoc &DL, Register DstReg, uint64_t Val,
144 MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
145 bool DstRenamable = false, bool DstIsDead = false) const;
146
147 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
148
149 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
150 MachineBasicBlock *&FBB,
151 SmallVectorImpl<MachineOperand> &Cond,
152 bool AllowModify) const override;
153
154 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
155 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
156 const DebugLoc &dl,
157 int *BytesAdded = nullptr) const override;
158
159 void insertIndirectBranch(MachineBasicBlock &MBB,
160 MachineBasicBlock &NewDestBB,
161 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
162 int64_t BrOffset, RegScavenger *RS) const override;
163
164 unsigned removeBranch(MachineBasicBlock &MBB,
165 int *BytesRemoved = nullptr) const override;
166
167 bool
168 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
169
170 bool optimizeCondBranch(MachineInstr &MI) const override;
171
172 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
173
174 bool isBranchOffsetInRange(unsigned BranchOpc,
175 int64_t BrOffset) const override;
176
177 MachineInstr *optimizeSelect(MachineInstr &MI,
178 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
179 bool) const override;
180
181 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
182
183 std::optional<DestSourcePair>
184 isCopyInstrImpl(const MachineInstr &MI) const override;
185
186 bool verifyInstruction(const MachineInstr &MI,
187 StringRef &ErrInfo) const override;
188
189 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
190 const MachineInstr &AddrI,
191 ExtAddrMode &AM) const override;
192
193 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
194 const ExtAddrMode &AM) const override;
195
196 bool getMemOperandsWithOffsetWidth(
197 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
198 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
199 const TargetRegisterInfo *TRI) const override;
200
201 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
202 int64_t Offset1, bool OffsetIsScalable1,
203 ArrayRef<const MachineOperand *> BaseOps2,
204 int64_t Offset2, bool OffsetIsScalable2,
205 unsigned ClusterSize,
206 unsigned NumBytes) const override;
207
208 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
209 const MachineOperand *&BaseOp,
210 int64_t &Offset, LocationSize &Width,
211 const TargetRegisterInfo *TRI) const;
212
213 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
214 const MachineInstr &MIb) const override;
215
216
217 std::pair<unsigned, unsigned>
218 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
219
220 ArrayRef<std::pair<unsigned, const char *>>
221 getSerializableDirectMachineOperandTargetFlags() const override;
222
223 // Return true if the function can safely be outlined from.
224 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
225 bool OutlineFromLinkOnceODRs) const override;
226
227 // Return true if MBB is safe to outline from, and return any target-specific
228 // information in Flags.
229 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
230 unsigned &Flags) const override;
231
232 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
233
234 bool analyzeCandidate(outliner::Candidate &C) const;
235 // Calculate target-specific information for a set of outlining candidates.
236 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
237 getOutliningCandidateInfo(
238 const MachineModuleInfo &MMI,
239 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
240 unsigned MinRepeats) const override;
241
242 // Return if/how a given MachineInstr should be outlined.
243 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
244 MachineBasicBlock::iterator &MBBI,
245 unsigned Flags) const override;
246
247 // Insert a custom frame for outlined functions.
248 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
249 const outliner::OutlinedFunction &OF) const override;
250
251 // Insert a call to an outlined function into a given basic block.
252 MachineBasicBlock::iterator
253 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
254 MachineBasicBlock::iterator &It, MachineFunction &MF,
255 outliner::Candidate &C) const override;
256
257 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
258 Register Reg) const override;
259
260 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
261 unsigned &SrcOpIdx2) const override;
262 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
263 unsigned OpIdx1,
264 unsigned OpIdx2) const override;
265
266 bool simplifyInstruction(MachineInstr &MI) const override;
267
268 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
269 LiveIntervals *LIS) const override;
270
271 // MIR printer helper function to annotate Operands with a comment.
272 std::string
273 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
274 unsigned OpIdx,
275 const TargetRegisterInfo *TRI) const override;
276
277 /// Generate code to multiply the value in DestReg by Amt - handles all
278 /// the common optimizations for this idiom, and supports fallback for
279 /// subtargets which don't support multiply instructions.
280 void mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
281 MachineBasicBlock::iterator II, const DebugLoc &DL,
282 Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const;
283
284 bool useMachineCombiner() const override { return true; }
285
286 MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
287
288 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
289
290 bool getMachineCombinerPatterns(MachineInstr &Root,
291 SmallVectorImpl<unsigned> &Patterns,
292 bool DoRegPressureReduce) const override;
293
294 void
295 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
296 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
297
298 void genAlternativeCodeSequence(
299 MachineInstr &Root, unsigned Pattern,
300 SmallVectorImpl<MachineInstr *> &InsInstrs,
301 SmallVectorImpl<MachineInstr *> &DelInstrs,
302 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
303
304 bool hasReassociableOperands(const MachineInstr &Inst,
305 const MachineBasicBlock *MBB) const override;
306
307 bool hasReassociableSibling(const MachineInstr &Inst,
308 bool &Commuted) const override;
309
310 bool isAssociativeAndCommutative(const MachineInstr &Inst,
311 bool Invert) const override;
312
313 std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
314
315 void getReassociateOperandIndices(
316 const MachineInstr &Root, unsigned Pattern,
317 std::array<unsigned, 5> &OperandIndices) const override;
318
319 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
320 getSerializableMachineMemOperandTargetFlags() const override;
321
322 unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
323
324 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
325 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
326
327 bool isHighLatencyDef(int Opc) const override;
328
329 /// Return true if \p MI is a COPY to a vector register of a specific \p LMul,
330 /// or any kind of vector registers when \p LMul is zero.
331 bool isVRegCopy(const MachineInstr *MI, unsigned LMul = 0) const;
332
333 /// Return true if pairing the given load or store may be paired with another.
334 static bool isPairableLdStInstOpc(unsigned Opc);
335
336 static bool isLdStSafeToPair(const MachineInstr &LdSt,
337 const TargetRegisterInfo *TRI);
338#define GET_INSTRINFO_HELPER_DECLS
339#include "RISCVGenInstrInfo.inc"
340
341 static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc);
342
343 /// Return the result of the evaluation of C0 CC C1, where CC is a
344 /// RISCVCC::CondCode.
345 static bool evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0, int64_t C1);
346
347 /// Return true if the operand is a load immediate instruction and
348 /// sets Imm to the immediate value.
349 static bool isFromLoadImm(const MachineRegisterInfo &MRI,
350 const MachineOperand &Op, int64_t &Imm);
351
352protected:
353 const RISCVSubtarget &STI;
354
355private:
356 unsigned getInstBundleLength(const MachineInstr &MI) const;
357
358 bool isVectorAssociativeAndCommutative(const MachineInstr &MI,
359 bool Invert = false) const;
360 bool areRVVInstsReassociable(const MachineInstr &MI1,
361 const MachineInstr &MI2) const;
362 bool hasReassociableVectorSibling(const MachineInstr &Inst,
363 bool &Commuted) const;
364};
365
366namespace RISCV {
367
368// Returns true if the given MI is an RVV instruction opcode for which we may
369// expect to see a FrameIndex operand.
370bool isRVVSpill(const MachineInstr &MI);
371
372/// Return true if \p MI is a copy that will be lowered to one or more vmvNr.vs.
373bool isVectorCopy(const TargetRegisterInfo *TRI, const MachineInstr &MI);
374
375std::optional<std::pair<unsigned, unsigned>>
376isRVVSpillForZvlsseg(unsigned Opcode);
377
378// Return true if both input instructions have equal rounding mode. If at least
379// one of the instructions does not have rounding mode, false will be returned.
380bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
381
382// If \p Opcode is a .vx vector instruction, returns the lower number of bits
383// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
384// returns null.
385std::optional<unsigned> getVectorLowDemandedScalarBits(unsigned Opcode,
386 unsigned Log2SEW);
387
388// Returns the MC opcode of RVV pseudo instruction.
389unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);
390
391// For a (non-pseudo) RVV instruction \p Desc and the given \p Log2SEW, returns
392// the log2 EEW of the destination operand.
393unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);
394
395// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
396static constexpr int64_t VLMaxSentinel = -1LL;
397
398/// Given two VL operands, do we know that LHS <= RHS?
399bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS);
400
401// Mask assignments for floating-point
402static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
403static constexpr unsigned FPMASK_Negative_Normal = 0x002;
404static constexpr unsigned FPMASK_Negative_Subnormal = 0x004;
405static constexpr unsigned FPMASK_Negative_Zero = 0x008;
406static constexpr unsigned FPMASK_Positive_Zero = 0x010;
407static constexpr unsigned FPMASK_Positive_Subnormal = 0x020;
408static constexpr unsigned FPMASK_Positive_Normal = 0x040;
409static constexpr unsigned FPMASK_Positive_Infinity = 0x080;
410static constexpr unsigned FPMASK_Signaling_NaN = 0x100;
411static constexpr unsigned FPMASK_Quiet_NaN = 0x200;
412} // namespace RISCV
413
414namespace RISCVVPseudosTable {
415
416struct PseudoInfo {
417 uint16_t Pseudo;
418 uint16_t BaseInstr;
419 uint16_t VLMul : 3;
420 uint16_t SEW : 8;
421 uint16_t IsAltFmt : 1;
422};
423
424#define GET_RISCVVPseudosTable_DECL
425#include "RISCVGenSearchableTables.inc"
426
427} // end namespace RISCVVPseudosTable
428
429namespace RISCV {
430
431struct RISCVMaskedPseudoInfo {
432 uint16_t MaskedPseudo;
433 uint16_t UnmaskedPseudo;
434 uint8_t MaskOpIdx;
435};
436#define GET_RISCVMaskedPseudosTable_DECL
437#include "RISCVGenSearchableTables.inc"
438} // end namespace RISCV
439
440} // end namespace llvm
441#endif
442