1//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15
16#include "RISCV.h"
17#include "RISCVRegisterInfo.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19#include "llvm/IR/DiagnosticInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "RISCVGenInstrInfo.inc"
23#include "RISCVGenRegisterInfo.inc"
24
25namespace llvm {
26
27// If Value is of the form C1<<C2, where C1 = 3, 5 or 9,
28// returns log2(C1 - 1) and assigns Shift = C2.
29// Otherwise, returns 0.
30template <typename T> int isShifted359(T Value, int &Shift) {
31 if (Value == 0)
32 return 0;
33 Shift = llvm::countr_zero(Value);
34 switch (Value >> Shift) {
35 case 3:
36 return 1;
37 case 5:
38 return 2;
39 case 9:
40 return 3;
41 default:
42 return 0;
43 }
44}
45
46class RISCVSubtarget;
47
48static const MachineMemOperand::Flags MONontemporalBit0 =
49 MachineMemOperand::MOTargetFlag1;
50static const MachineMemOperand::Flags MONontemporalBit1 =
51 MachineMemOperand::MOTargetFlag2;
52
53namespace RISCVCC {
54
55enum CondCode {
56 COND_EQ,
57 COND_NE,
58 COND_LT,
59 COND_GE,
60 COND_LTU,
61 COND_GEU,
62 COND_INVALID
63};
64
65CondCode getInverseBranchCondition(CondCode);
66unsigned getInverseBranchOpcode(unsigned BCC);
67unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
68
69} // end of namespace RISCVCC
70
71// RISCV MachineCombiner patterns
72enum RISCVMachineCombinerPattern : unsigned {
73 FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START,
74 FMADD_XA,
75 FMSUB,
76 FNMSUB,
77 SHXADD_ADD_SLLI_OP1,
78 SHXADD_ADD_SLLI_OP2,
79};
80
81class RISCVInstrInfo : public RISCVGenInstrInfo {
82 const RISCVRegisterInfo RegInfo;
83
84public:
85 explicit RISCVInstrInfo(const RISCVSubtarget &STI);
86
87 const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
88
89 const TargetRegisterClass *getInlineAsmMemoryOperandRegClass(
90 InlineAsm::ConstraintCode C) const override {
91 return &RISCV::GPRRegClass;
92 }
93
94 MCInst getNop() const override;
95
96 Register isLoadFromStackSlot(const MachineInstr &MI,
97 int &FrameIndex) const override;
98 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
99 TypeSize &MemBytes) const override;
100 Register isStoreToStackSlot(const MachineInstr &MI,
101 int &FrameIndex) const override;
102 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
103 TypeSize &MemBytes) const override;
104
105 bool isReMaterializableImpl(const MachineInstr &MI) const override;
106
107 bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
108 return MI.getOpcode() == RISCV::ADDI && MI.getOperand(i: 1).isReg() &&
109 MI.getOperand(i: 1).getReg() == RISCV::X0;
110 }
111
112 void copyPhysRegVector(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
114 MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
115 const TargetRegisterClass *RegClass) const;
116 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
117 const DebugLoc &DL, Register DstReg, Register SrcReg,
118 bool KillSrc, bool RenamableDest = false,
119 bool RenamableSrc = false) const override;
120
121 void storeRegToStackSlot(
122 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
123 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
124
125 Register VReg,
126 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
127
128 void loadRegFromStackSlot(
129 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
130 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
131 unsigned SubReg = 0,
132 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
133
134 using TargetInstrInfo::foldMemoryOperandImpl;
135 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
136 ArrayRef<unsigned> Ops, int FrameIndex,
137 MachineInstr *&CopyMI,
138 LiveIntervals *LIS = nullptr,
139 VirtRegMap *VRM = nullptr) const override;
140
141 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
142 ArrayRef<unsigned> Ops,
143 MachineInstr &LoadMI,
144 MachineInstr *&CopyMI,
145 LiveIntervals *LIS = nullptr,
146 VirtRegMap *VRM = nullptr) const override;
147
148 // Materializes the given integer Val into DstReg.
149 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
150 const DebugLoc &DL, Register DstReg, uint64_t Val,
151 MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
152 bool DstRenamable = false, bool DstIsDead = false) const;
153
154 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
155
156 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
157 MachineBasicBlock *&FBB,
158 SmallVectorImpl<MachineOperand> &Cond,
159 bool AllowModify) const override;
160
161 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
162 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
163 const DebugLoc &dl,
164 int *BytesAdded = nullptr) const override;
165
166 void insertIndirectBranch(MachineBasicBlock &MBB,
167 MachineBasicBlock &NewDestBB,
168 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
169 int64_t BrOffset, RegScavenger *RS) const override;
170
171 unsigned removeBranch(MachineBasicBlock &MBB,
172 int *BytesRemoved = nullptr) const override;
173
174 bool
175 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
176
177 bool optimizeCondBranch(MachineInstr &MI) const override;
178
179 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
180
181 bool isBranchOffsetInRange(unsigned BranchOpc,
182 int64_t BrOffset) const override;
183
184 int getJumpTableIndex(const MachineInstr &MI) const override;
185
186 MachineInstr *optimizeSelect(MachineInstr &MI,
187 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
188 bool) const override;
189
190 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
191
192 std::optional<DestSourcePair>
193 isCopyInstrImpl(const MachineInstr &MI) const override;
194
195 bool verifyInstruction(const MachineInstr &MI,
196 StringRef &ErrInfo) const override;
197
198 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
199 const MachineInstr &AddrI,
200 ExtAddrMode &AM) const override;
201
202 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
203 const ExtAddrMode &AM) const override;
204
205 bool getMemOperandsWithOffsetWidth(
206 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
207 int64_t &Offset, bool &OffsetIsScalable,
208 LocationSize &Width) const override;
209
210 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
211 int64_t Offset1, bool OffsetIsScalable1,
212 ArrayRef<const MachineOperand *> BaseOps2,
213 int64_t Offset2, bool OffsetIsScalable2,
214 unsigned ClusterSize,
215 unsigned NumBytes) const override;
216
217 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
218 const MachineOperand *&BaseOp,
219 int64_t &Offset, LocationSize &Width) const;
220
221 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
222 const MachineInstr &MIb) const override;
223
224
225 std::pair<unsigned, unsigned>
226 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
227
228 ArrayRef<std::pair<unsigned, const char *>>
229 getSerializableDirectMachineOperandTargetFlags() const override;
230
231 // Return true if the function can safely be outlined from.
232 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
233 bool OutlineFromLinkOnceODRs) const override;
234
235 // Return true if MBB is safe to outline from, and return any target-specific
236 // information in Flags.
237 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
238 unsigned &Flags) const override;
239
240 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
241
242 // Return true if the candidate should be discarded from outlining.
243 bool analyzeCandidate(outliner::Candidate &C) const;
244 // Calculate target-specific information for a set of outlining candidates.
245 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
246 getOutliningCandidateInfo(
247 const MachineModuleInfo &MMI,
248 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
249 unsigned MinRepeats) const override;
250
251 // Return if/how a given MachineInstr should be outlined.
252 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
253 MachineBasicBlock::iterator &MBBI,
254 unsigned Flags) const override;
255
256 // Insert a custom frame for outlined functions.
257 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
258 const outliner::OutlinedFunction &OF) const override;
259
260 // Insert a call to an outlined function into a given basic block.
261 MachineBasicBlock::iterator
262 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
263 MachineBasicBlock::iterator &It, MachineFunction &MF,
264 outliner::Candidate &C) const override;
265
266 void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
267 MachineBasicBlock::iterator Iter, DebugLoc &DL,
268 bool AllowSideEffects = true) const override;
269
270 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
271 Register Reg) const override;
272
273 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
274 unsigned &SrcOpIdx2) const override;
275 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
276 unsigned OpIdx1,
277 unsigned OpIdx2) const override;
278
279 bool simplifyInstruction(MachineInstr &MI) const override;
280
281 MachineInstr *convertToThreeAddress(MachineInstr &MI,
282 LiveIntervals *LIS) const override;
283
284 // MIR printer helper function to annotate Operands with a comment.
285 std::string createMIROperandComment(const MachineInstr &MI,
286 const MachineOperand &Op,
287 unsigned OpIdx) const override;
288
289 /// Generate code to multiply the value in DestReg by Amt - handles all
290 /// the common optimizations for this idiom, and supports fallback for
291 /// subtargets which don't support multiply instructions.
292 void mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
293 MachineBasicBlock::iterator II, const DebugLoc &DL,
294 Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const;
295
296 bool useMachineCombiner() const override { return true; }
297
298 MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
299
300 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
301
302 bool getMachineCombinerPatterns(MachineInstr &Root,
303 SmallVectorImpl<unsigned> &Patterns,
304 bool DoRegPressureReduce) const override;
305
306 void
307 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
308 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
309
310 void genAlternativeCodeSequence(
311 MachineInstr &Root, unsigned Pattern,
312 SmallVectorImpl<MachineInstr *> &InsInstrs,
313 SmallVectorImpl<MachineInstr *> &DelInstrs,
314 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
315
316 bool hasReassociableOperands(const MachineInstr &Inst,
317 const MachineBasicBlock *MBB) const override;
318
319 bool hasReassociableSibling(const MachineInstr &Inst,
320 bool &Commuted) const override;
321
322 bool isAssociativeAndCommutative(const MachineInstr &Inst,
323 bool Invert) const override;
324
325 std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
326
327 void getReassociateOperandIndices(
328 const MachineInstr &Root, unsigned Pattern,
329 std::array<unsigned, 5> &OperandIndices) const override;
330
331 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
332 getSerializableMachineMemOperandTargetFlags() const override;
333
334 unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
335
336 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
337 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
338
339 bool isHighLatencyDef(int Opc) const override;
340
341 /// Return true if \p MI is a COPY to a vector register of a specific \p LMul,
342 /// or any kind of vector registers when \p LMul is zero.
343 bool isVRegCopy(const MachineInstr *MI, unsigned LMul = 0) const;
344
345 /// Return true if the instruction requires an NTL hint to be emitted.
346 bool requiresNTLHint(const MachineInstr &MI) const;
347
348 /// Return true if moving \p From down to \p To won't cause any physical
349 /// register reads or writes to be clobbered and no visible side effects are
350 /// affected. From and To must be in the same block.
351 static bool isSafeToMove(const MachineInstr &From,
352 const MachineBasicBlock::iterator &To);
353
354 /// Return true if pairing the given load or store may be paired with another.
355 static bool isPairableLdStInstOpc(unsigned Opc);
356
357 static bool isLdStSafeToPair(const MachineInstr &LdSt,
358 const TargetRegisterInfo *TRI);
359#define GET_INSTRINFO_HELPER_DECLS
360#include "RISCVGenInstrInfo.inc"
361
362 static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc);
363
364 /// Return the result of the evaluation of C0 CC C1, where CC is a
365 /// RISCVCC::CondCode.
366 static bool evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0, int64_t C1);
367
368 /// Return true if the operand is a load immediate instruction and
369 /// sets Imm to the immediate value.
370 static bool isFromLoadImm(const MachineRegisterInfo &MRI,
371 const MachineOperand &Op, int64_t &Imm);
372
373protected:
374 const RISCVSubtarget &STI;
375
376private:
377 bool isVectorAssociativeAndCommutative(const MachineInstr &MI,
378 bool Invert = false) const;
379 bool areRVVInstsReassociable(const MachineInstr &MI1,
380 const MachineInstr &MI2) const;
381 bool hasReassociableVectorSibling(const MachineInstr &Inst,
382 bool &Commuted) const;
383};
384
385namespace RISCV {
386
387// Returns true if the given MI is an RVV instruction opcode for which we may
388// expect to see a FrameIndex operand.
389bool isRVVSpill(const MachineInstr &MI);
390
391/// Return true if \p MI is a copy that will be lowered to one or more vmvNr.vs.
392bool isVectorCopy(const TargetRegisterInfo *TRI, const MachineInstr &MI);
393
394std::optional<std::pair<unsigned, unsigned>>
395isRVVSpillForZvlsseg(unsigned Opcode);
396
397// Return true if both input instructions have equal rounding mode. If at least
398// one of the instructions does not have rounding mode, false will be returned.
399bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
400
401// If \p Opcode is a .vx vector instruction, returns the lower number of bits
402// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
403// returns null.
404std::optional<unsigned> getVectorLowDemandedScalarBits(unsigned Opcode,
405 unsigned Log2SEW);
406
407// Returns the MC opcode of RVV pseudo instruction.
408unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);
409
410// For a (non-pseudo) RVV instruction \p Desc and the given \p Log2SEW, returns
411// the log2 EEW of the destination operand.
412unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);
413
414// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
415static constexpr int64_t VLMaxSentinel = -1LL;
416
417/// Given two VL operands, do we know that LHS <= RHS?
418bool isVLKnownLE(const MachineRegisterInfo &MRI, const MachineOperand &LHS,
419 const MachineOperand &RHS);
420
421// Mask assignments for floating-point
422static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
423static constexpr unsigned FPMASK_Negative_Normal = 0x002;
424static constexpr unsigned FPMASK_Negative_Subnormal = 0x004;
425static constexpr unsigned FPMASK_Negative_Zero = 0x008;
426static constexpr unsigned FPMASK_Positive_Zero = 0x010;
427static constexpr unsigned FPMASK_Positive_Subnormal = 0x020;
428static constexpr unsigned FPMASK_Positive_Normal = 0x040;
429static constexpr unsigned FPMASK_Positive_Infinity = 0x080;
430static constexpr unsigned FPMASK_Signaling_NaN = 0x100;
431static constexpr unsigned FPMASK_Quiet_NaN = 0x200;
432} // namespace RISCV
433
434namespace RISCVVPseudosTable {
435
436struct PseudoInfo {
437 uint16_t Pseudo;
438 uint16_t BaseInstr;
439 uint16_t VLMul : 3;
440 uint16_t SEW : 8;
441 uint16_t IsAltFmt : 1;
442};
443
444#define GET_RISCVVPseudosTable_DECL
445#include "RISCVGenSearchableTables.inc"
446
447} // end namespace RISCVVPseudosTable
448
449namespace RISCV {
450
451struct RISCVMaskedPseudoInfo {
452 uint16_t MaskedPseudo;
453 uint16_t UnmaskedPseudo;
454 uint8_t MaskOpIdx;
455};
456#define GET_RISCVMaskedPseudosTable_DECL
457#include "RISCVGenSearchableTables.inc"
458} // end namespace RISCV
459
460} // end namespace llvm
461#endif
462