1//===-- RISCVRegisterInfo.h - RISC-V Register Information Impl --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
15
16#include "llvm/CodeGen/TargetRegisterInfo.h"
17#include "llvm/TargetParser/RISCVTargetParser.h"
18
19#define GET_REGINFO_HEADER
20#include "RISCVGenRegisterInfo.inc"
21
22namespace llvm {
23
24namespace RISCVRI {
25enum : uint8_t {
26 // The IsVRegClass value of this RegisterClass.
27 IsVRegClassShift = 0,
28 IsVRegClassShiftMask = 0b1 << IsVRegClassShift,
29 // The VLMul value of this RegisterClass. This value is valid iff IsVRegClass
30 // is true.
31 VLMulShift = IsVRegClassShift + 1,
32 VLMulShiftMask = 0b11 << VLMulShift,
33
34 // The NF value of this RegisterClass. This value is valid iff IsVRegClass is
35 // true.
36 NFShift = VLMulShift + 2,
37 NFShiftMask = 0b111 << NFShift,
38};
39
40/// Register allocation hints for Zilsd register pairs
41enum {
42 // Used for Zilsd LD/SD register pairs
43 RegPairOdd = 1,
44 RegPairEven = 2,
45};
46
47/// \returns the IsVRegClass for the register class.
48static inline bool isVRegClass(uint8_t TSFlags) {
49 return (TSFlags & IsVRegClassShiftMask) >> IsVRegClassShift;
50}
51
52/// \returns the LMUL for the register class.
53static inline RISCVVType::VLMUL getLMul(uint8_t TSFlags) {
54 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulShiftMask) >>
55 VLMulShift);
56}
57
58/// \returns the NF for the register class.
59static inline unsigned getNF(uint8_t TSFlags) {
60 return static_cast<unsigned>((TSFlags & NFShiftMask) >> NFShift) + 1;
61}
62} // namespace RISCVRI
63
64struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
65
66 RISCVRegisterInfo(unsigned HwMode);
67
68 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
69 CallingConv::ID) const override;
70
71 unsigned getCSRCost() const override {
72 // The cost will be compared against BlockFrequency where entry has the
73 // value of 1 << 14. A value of 5 will choose to spill or split cold
74 // path instead of using a callee-saved register.
75 return 5;
76 }
77
78 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
79
80 const TargetRegisterClass *
81 getConstrainedRegClassForReg(Register Reg,
82 const MachineRegisterInfo &MRI) const override;
83
84 const TargetRegisterClass *
85 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, bool Is64Bit) const;
86
87 const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const override;
88
89 BitVector getReservedRegs(const MachineFunction &MF) const override;
90 bool isAsmClobberable(const MachineFunction &MF,
91 MCRegister PhysReg) const override;
92
93 const uint32_t *getNoPreservedMask() const override;
94
95 // Update DestReg to have the value SrcReg plus an offset. This is
96 // used during frame layout, and we may need to ensure that if we
97 // split the offset internally that the DestReg is always aligned,
98 // assuming that source reg was.
99 void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
100 const DebugLoc &DL, Register DestReg, Register SrcReg,
101 StackOffset Offset, MachineInstr::MIFlag Flag,
102 MaybeAlign RequiredAlign) const;
103
104 bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
105 unsigned FIOperandNum,
106 RegScavenger *RS = nullptr) const override;
107
108 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
109
110 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
111
112 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
113 int64_t Offset) const override;
114
115 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
116 int64_t Offset) const override;
117
118 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
119 int64_t Offset) const override;
120
121 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
122 int Idx) const override;
123
124 void lowerSegmentSpillReload(MachineBasicBlock::iterator II,
125 bool IsSpill) const;
126
127 Register getFrameRegister(const MachineFunction &MF) const override;
128
129 bool isArgumentRegister(const MachineFunction &MF,
130 MCRegister Reg) const override;
131
132 StringRef getRegAsmName(MCRegister Reg) const override;
133
134 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
135 return true;
136 }
137
138 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
139 return true;
140 }
141
142 const TargetRegisterClass *
143 getPointerRegClass(unsigned Kind = 0) const override {
144 return &RISCV::GPRRegClass;
145 }
146
147 const TargetRegisterClass *
148 getLargestLegalSuperClass(const TargetRegisterClass *RC,
149 const MachineFunction &) const override;
150
151 void getOffsetOpcodes(const StackOffset &Offset,
152 SmallVectorImpl<uint64_t> &Ops) const override;
153
154 unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
155
156 float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override;
157
158 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
159 SmallVectorImpl<MCPhysReg> &Hints,
160 const MachineFunction &MF, const VirtRegMap *VRM,
161 const LiveRegMatrix *Matrix) const override;
162
163 void updateRegAllocHint(Register Reg, Register NewReg,
164 MachineFunction &MF) const override;
165
166 Register findVRegWithEncoding(const TargetRegisterClass &RegClass,
167 uint16_t Encoding) const;
168
169 static bool isVRRegClass(const TargetRegisterClass *RC) {
170 return RISCVRI::isVRegClass(TSFlags: RC->TSFlags) &&
171 RISCVRI::getNF(TSFlags: RC->TSFlags) == 1;
172 }
173
174 static bool isVRNRegClass(const TargetRegisterClass *RC) {
175 return RISCVRI::isVRegClass(TSFlags: RC->TSFlags) && RISCVRI::getNF(TSFlags: RC->TSFlags) > 1;
176 }
177
178 static bool isRVVRegClass(const TargetRegisterClass *RC) {
179 return RISCVRI::isVRegClass(TSFlags: RC->TSFlags);
180 }
181
182 static bool isFPRegister(MCRegister Reg) {
183 return RISCV::FPR16RegClass.contains(Reg) ||
184 RISCV::FPR32RegClass.contains(Reg) ||
185 RISCV::FPR64RegClass.contains(Reg) ||
186 RISCV::FPR128RegClass.contains(Reg);
187 }
188};
189} // namespace llvm
190
191#endif
192