1//===-- RISCVCallLowering.cpp - Call lowering -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCVCallLowering.h"
16#include "RISCVCallingConv.h"
17#include "RISCVISelLowering.h"
18#include "RISCVMachineFunctionInfo.h"
19#include "RISCVSubtarget.h"
20#include "llvm/CodeGen/Analysis.h"
21#include "llvm/CodeGen/FunctionLoweringInfo.h"
22#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include <functional>
25
26using namespace llvm;
27
28namespace {
29
30struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
31 RISCVOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
32 MachineInstrBuilder MIB)
33 : OutgoingValueHandler(B, MRI), MIB(MIB),
34 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {}
35 Register getStackAddress(uint64_t MemSize, int64_t Offset,
36 MachinePointerInfo &MPO,
37 ISD::ArgFlagsTy Flags) override {
38 MachineFunction &MF = MIRBuilder.getMF();
39 LLT p0 = LLT::pointer(AddressSpace: 0, SizeInBits: Subtarget.getXLen());
40 LLT sXLen = LLT::scalar(SizeInBits: Subtarget.getXLen());
41
42 if (!SPReg)
43 SPReg = MIRBuilder.buildCopy(Res: p0, Op: Register(RISCV::X2)).getReg(Idx: 0);
44
45 auto OffsetReg = MIRBuilder.buildConstant(Res: sXLen, Val: Offset);
46
47 auto AddrReg = MIRBuilder.buildPtrAdd(Res: p0, Op0: SPReg, Op1: OffsetReg);
48
49 MPO = MachinePointerInfo::getStack(MF, Offset);
50 return AddrReg.getReg(Idx: 0);
51 }
52
53 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
54 const MachinePointerInfo &MPO,
55 const CCValAssign &VA) override {
56 MachineFunction &MF = MIRBuilder.getMF();
57 uint64_t LocMemOffset = VA.getLocMemOffset();
58
59 // TODO: Move StackAlignment to subtarget and share with FrameLowering.
60 auto MMO =
61 MF.getMachineMemOperand(PtrInfo: MPO, f: MachineMemOperand::MOStore, MemTy,
62 base_alignment: commonAlignment(A: Align(16), Offset: LocMemOffset));
63
64 Register ExtReg = extendRegister(ValReg: ValVReg, VA);
65 MIRBuilder.buildStore(Val: ExtReg, Addr, MMO&: *MMO);
66 }
67
68 void assignValueToReg(Register ValVReg, Register PhysReg,
69 const CCValAssign &VA,
70 ISD::ArgFlagsTy Flags = {}) override {
71 Register ExtReg = extendRegister(ValReg: ValVReg, VA);
72 MIRBuilder.buildCopy(Res: PhysReg, Op: ExtReg);
73 MIB.addUse(RegNo: PhysReg, Flags: RegState::Implicit);
74 }
75
76 unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
77 ArrayRef<CCValAssign> VAs,
78 std::function<void()> *Thunk) override {
79 const CCValAssign &VA = VAs[0];
80 bool NarrowValWideLoc =
81 (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) ||
82 (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16);
83 bool FixedLenVecInScalableVec =
84 VA.getValVT().isFixedLengthVector() && VA.getLocVT().isScalableVector();
85 if (NarrowValWideLoc || FixedLenVecInScalableVec) {
86 Register PhysReg = VA.getLocReg();
87
88 std::function<void()> AssignFunc;
89 if (NarrowValWideLoc) {
90 AssignFunc = [=]() {
91 auto Trunc = MIRBuilder.buildAnyExt(Res: LLT(VA.getLocVT()), Op: Arg.Regs[0]);
92 MIRBuilder.buildCopy(Res: PhysReg, Op: Trunc);
93 MIB.addUse(RegNo: PhysReg, Flags: RegState::Implicit);
94 };
95 } else if (FixedLenVecInScalableVec) {
96 AssignFunc = [=]() {
97 auto SubVec = MIRBuilder.buildInsertSubvector(
98 Res: LLT(VA.getLocVT()), Src0: MIRBuilder.buildUndef(Res: LLT(VA.getLocVT())),
99 Src1: Arg.Regs[0], Index: 0);
100 MIRBuilder.buildCopy(Res: PhysReg, Op: SubVec);
101 MIB.addUse(RegNo: PhysReg, Flags: RegState::Implicit);
102 };
103 } else
104 llvm_unreachable(
105 "A narrower value must be passed in a wider register or a fixed "
106 "length vector in a scalable vector register.");
107
108 if (Thunk) {
109 *Thunk = std::move(AssignFunc);
110 return 1;
111 }
112
113 AssignFunc();
114 return 1;
115 }
116
117 assert(VAs.size() >= 2 && "Expected at least 2 VAs.");
118 const CCValAssign &VAHi = VAs[1];
119
120 assert(VAHi.needsCustom() && "Value doesn't need custom handling");
121 assert(VA.getValNo() == VAHi.getValNo() &&
122 "Values belong to different arguments");
123
124 assert(VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
125 VA.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
126 "unexpected custom value");
127
128 Register NewRegs[] = {MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32)),
129 MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32))};
130 MIRBuilder.buildUnmerge(Res: NewRegs, Op: Arg.Regs[0]);
131
132 if (VAHi.isMemLoc()) {
133 LLT MemTy(VAHi.getLocVT());
134
135 MachinePointerInfo MPO;
136 Register StackAddr = getStackAddress(
137 MemSize: MemTy.getSizeInBytes(), Offset: VAHi.getLocMemOffset(), MPO, Flags: Arg.Flags[0]);
138
139 assignValueToAddress(ValVReg: NewRegs[1], Addr: StackAddr, MemTy, MPO,
140 VA: const_cast<CCValAssign &>(VAHi));
141 }
142
143 auto assignFunc = [=]() {
144 assignValueToReg(ValVReg: NewRegs[0], PhysReg: VA.getLocReg(), VA);
145 if (VAHi.isRegLoc())
146 assignValueToReg(ValVReg: NewRegs[1], PhysReg: VAHi.getLocReg(), VA: VAHi);
147 };
148
149 if (Thunk) {
150 *Thunk = std::move(assignFunc);
151 return 2;
152 }
153
154 assignFunc();
155 return 2;
156 }
157
158private:
159 MachineInstrBuilder MIB;
160
161 // Cache the SP register vreg if we need it more than once in this call site.
162 Register SPReg;
163
164 const RISCVSubtarget &Subtarget;
165};
166
167struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
168 RISCVIncomingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
169 : IncomingValueHandler(B, MRI),
170 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {}
171
172 Register getStackAddress(uint64_t MemSize, int64_t Offset,
173 MachinePointerInfo &MPO,
174 ISD::ArgFlagsTy Flags) override {
175 MachineFrameInfo &MFI = MIRBuilder.getMF().getFrameInfo();
176
177 int FI = MFI.CreateFixedObject(Size: MemSize, SPOffset: Offset, /*Immutable=*/IsImmutable: true);
178 MPO = MachinePointerInfo::getFixedStack(MF&: MIRBuilder.getMF(), FI);
179 return MIRBuilder.buildFrameIndex(Res: LLT::pointer(AddressSpace: 0, SizeInBits: Subtarget.getXLen()), Idx: FI)
180 .getReg(Idx: 0);
181 }
182
183 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
184 const MachinePointerInfo &MPO,
185 const CCValAssign &VA) override {
186 MachineFunction &MF = MIRBuilder.getMF();
187 auto MMO = MF.getMachineMemOperand(PtrInfo: MPO, f: MachineMemOperand::MOLoad, MemTy,
188 base_alignment: inferAlignFromPtrInfo(MF, MPO));
189 MIRBuilder.buildLoad(Res: ValVReg, Addr, MMO&: *MMO);
190 }
191
192 void assignValueToReg(Register ValVReg, Register PhysReg,
193 const CCValAssign &VA,
194 ISD::ArgFlagsTy Flags = {}) override {
195 markPhysRegUsed(PhysReg);
196 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
197 }
198
199 unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
200 ArrayRef<CCValAssign> VAs,
201 std::function<void()> *Thunk) override {
202 const CCValAssign &VA = VAs[0];
203 bool NarrowValWideLoc =
204 (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) ||
205 (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16);
206 bool FixedLenVecInScalableVec =
207 VA.getValVT().isFixedLengthVector() && VA.getLocVT().isScalableVector();
208 if (NarrowValWideLoc || FixedLenVecInScalableVec) {
209 Register PhysReg = VA.getLocReg();
210
211 markPhysRegUsed(PhysReg);
212
213 LLT LocTy(VA.getLocVT());
214 auto Copy = MIRBuilder.buildCopy(Res: LocTy, Op: PhysReg);
215
216 if (NarrowValWideLoc)
217 MIRBuilder.buildTrunc(Res: Arg.Regs[0], Op: Copy.getReg(Idx: 0));
218 else if (FixedLenVecInScalableVec)
219 MIRBuilder.buildExtractSubvector(Res: Arg.Regs[0], Src: Copy.getReg(Idx: 0), Index: 0);
220 else
221 llvm_unreachable(
222 "A narrower value must be passed in a wider register or a fixed "
223 "length vector in a scalable vector register.");
224 return 1;
225 }
226
227 assert(VAs.size() >= 2 && "Expected at least 2 VAs.");
228 const CCValAssign &VAHi = VAs[1];
229
230 assert(VAHi.needsCustom() && "Value doesn't need custom handling");
231 assert(VA.getValNo() == VAHi.getValNo() &&
232 "Values belong to different arguments");
233
234 assert(VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
235 VA.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
236 "unexpected custom value");
237
238 Register NewRegs[] = {MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32)),
239 MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32))};
240
241 if (VAHi.isMemLoc()) {
242 LLT MemTy(VAHi.getLocVT());
243
244 MachinePointerInfo MPO;
245 Register StackAddr = getStackAddress(
246 MemSize: MemTy.getSizeInBytes(), Offset: VAHi.getLocMemOffset(), MPO, Flags: Arg.Flags[0]);
247
248 assignValueToAddress(ValVReg: NewRegs[1], Addr: StackAddr, MemTy, MPO,
249 VA: const_cast<CCValAssign &>(VAHi));
250 }
251
252 assignValueToReg(ValVReg: NewRegs[0], PhysReg: VA.getLocReg(), VA);
253 if (VAHi.isRegLoc())
254 assignValueToReg(ValVReg: NewRegs[1], PhysReg: VAHi.getLocReg(), VA: VAHi);
255
256 MIRBuilder.buildMergeLikeInstr(Res: Arg.Regs[0], Ops: NewRegs);
257
258 return 2;
259 }
260
261 /// How the physical register gets marked varies between formal
262 /// parameters (it's a basic-block live-in), and a call instruction
263 /// (it's an implicit-def of the BL).
264 virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
265
266private:
267 const RISCVSubtarget &Subtarget;
268};
269
270struct RISCVFormalArgHandler : public RISCVIncomingValueHandler {
271 RISCVFormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
272 : RISCVIncomingValueHandler(B, MRI) {}
273
274 void markPhysRegUsed(MCRegister PhysReg) override {
275 MIRBuilder.getMRI()->addLiveIn(Reg: PhysReg);
276 MIRBuilder.getMBB().addLiveIn(PhysReg);
277 }
278};
279
280struct RISCVCallReturnHandler : public RISCVIncomingValueHandler {
281 RISCVCallReturnHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
282 MachineInstrBuilder &MIB)
283 : RISCVIncomingValueHandler(B, MRI), MIB(MIB) {}
284
285 void markPhysRegUsed(MCRegister PhysReg) override {
286 MIB.addDef(RegNo: PhysReg, Flags: RegState::Implicit);
287 }
288
289 MachineInstrBuilder MIB;
290};
291
292} // namespace
293
294RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
295 : CallLowering(&TLI) {}
296
297/// Return true if scalable vector with ScalarTy is legal for lowering.
298static bool isLegalElementTypeForRVV(Type *EltTy,
299 const RISCVSubtarget &Subtarget) {
300 if (EltTy->isPointerTy())
301 return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true;
302 if (EltTy->isIntegerTy(BitWidth: 1) || EltTy->isIntegerTy(BitWidth: 8) ||
303 EltTy->isIntegerTy(BitWidth: 16) || EltTy->isIntegerTy(BitWidth: 32))
304 return true;
305 if (EltTy->isIntegerTy(BitWidth: 64))
306 return Subtarget.hasVInstructionsI64();
307 if (EltTy->isHalfTy())
308 return Subtarget.hasVInstructionsF16Minimal();
309 if (EltTy->isBFloatTy())
310 return Subtarget.hasVInstructionsBF16Minimal();
311 if (EltTy->isFloatTy())
312 return Subtarget.hasVInstructionsF32();
313 if (EltTy->isDoubleTy())
314 return Subtarget.hasVInstructionsF64();
315 return false;
316}
317
318// TODO: Support all argument types.
319// TODO: Remove IsLowerArgs argument by adding support for vectors in lowerCall.
320static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
321 bool IsLowerArgs = false) {
322 if (T->isIntegerTy())
323 return true;
324 if (T->isHalfTy() || T->isFloatTy() || T->isDoubleTy() || T->isFP128Ty())
325 return true;
326 if (T->isPointerTy())
327 return true;
328 if (T->isArrayTy())
329 return isSupportedArgumentType(T: T->getArrayElementType(), Subtarget,
330 IsLowerArgs);
331 // TODO: Support fixed vector types.
332 if (IsLowerArgs && T->isVectorTy() && Subtarget.hasVInstructions() &&
333 T->isScalableTy() &&
334 isLegalElementTypeForRVV(EltTy: T->getScalarType(), Subtarget))
335 return true;
336 if (T->isVectorTy() && !T->isScalableTy())
337 return true;
338
339 return false;
340}
341
342// TODO: Only integer, pointer and aggregate types are supported now.
343// TODO: Remove IsLowerRetVal argument by adding support for vectors in
344// lowerCall.
345static bool isSupportedReturnType(Type *T, const RISCVSubtarget &Subtarget,
346 bool IsLowerRetVal = false) {
347 if (T->isIntegerTy() || T->isFloatingPointTy() || T->isPointerTy())
348 return true;
349
350 if (T->isArrayTy())
351 return isSupportedReturnType(T: T->getArrayElementType(), Subtarget);
352
353 if (T->isStructTy()) {
354 auto StructT = cast<StructType>(Val: T);
355 for (unsigned i = 0, e = StructT->getNumElements(); i != e; ++i)
356 if (!isSupportedReturnType(T: StructT->getElementType(N: i), Subtarget))
357 return false;
358 return true;
359 }
360
361 if (IsLowerRetVal && T->isVectorTy() && Subtarget.hasVInstructions() &&
362 T->isScalableTy() &&
363 isLegalElementTypeForRVV(EltTy: T->getScalarType(), Subtarget))
364 return true;
365 if (T->isVectorTy() && !T->isScalableTy())
366 return true;
367
368 return false;
369}
370
371bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
372 const Value *Val, ArrayRef<Register> VRegs,
373 FunctionLoweringInfo &FLI) const {
374 assert(!Val == VRegs.empty() && "Return value without a vreg");
375 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Opcode: RISCV::PseudoRET);
376
377 if (!FLI.CanLowerReturn) {
378 insertSRetStores(MIRBuilder, RetTy: Val->getType(), VRegs, DemoteReg: FLI.DemoteRegister);
379 } else if (!VRegs.empty()) {
380 const RISCVSubtarget &Subtarget =
381 MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
382 if (!isSupportedReturnType(T: Val->getType(), Subtarget,
383 /*IsLowerRetVal=*/true))
384 return false;
385
386 MachineFunction &MF = MIRBuilder.getMF();
387 const DataLayout &DL = MF.getDataLayout();
388 const Function &F = MF.getFunction();
389 CallingConv::ID CC = F.getCallingConv();
390
391 ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
392 setArgFlags(Arg&: OrigRetInfo, OpIdx: AttributeList::ReturnIndex, DL, FuncInfo: F);
393
394 SmallVector<ArgInfo, 4> SplitRetInfos;
395 splitToValueTypes(OrigArgInfo: OrigRetInfo, SplitArgs&: SplitRetInfos, DL, CallConv: CC);
396
397 OutgoingValueAssigner Assigner(RetCC_RISCV);
398 RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);
399
400 SmallVector<CCValAssign, 16> RetLocs;
401 CCState CCInfo(CC, F.isVarArg(), MF, RetLocs, F.getContext());
402 if (!determineAssignments(Assigner, Args&: SplitRetInfos, CCInfo) ||
403 !handleAssignments(Handler, Args&: SplitRetInfos, CCState&: CCInfo, ArgLocs&: RetLocs, MIRBuilder))
404 return false;
405
406 if (any_of(Range&: RetLocs, P: [](CCValAssign &VA) {
407 return VA.getLocVT().isScalableVector();
408 }))
409 MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
410 }
411
412 MIRBuilder.insertInstr(MIB: Ret);
413 return true;
414}
415
416bool RISCVCallLowering::canLowerReturn(MachineFunction &MF,
417 CallingConv::ID CallConv,
418 SmallVectorImpl<BaseArgInfo> &Outs,
419 bool IsVarArg) const {
420 SmallVector<CCValAssign, 16> RetLocs;
421 CCState CCInfo(CallConv, IsVarArg, MF, RetLocs,
422 MF.getFunction().getContext());
423
424 return checkReturn(CCInfo, Outs, Fn: RetCC_RISCV);
425}
426
427/// If there are varargs that were passed in a0-a7, the data in those registers
428/// must be copied to the varargs save area on the stack.
429void RISCVCallLowering::saveVarArgRegisters(
430 MachineIRBuilder &MIRBuilder, CallLowering::IncomingValueHandler &Handler,
431 IncomingValueAssigner &Assigner, CCState &CCInfo) const {
432 MachineFunction &MF = MIRBuilder.getMF();
433 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
434 unsigned XLenInBytes = Subtarget.getXLen() / 8;
435 ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(STI: Subtarget);
436 MachineRegisterInfo &MRI = MF.getRegInfo();
437 unsigned Idx = CCInfo.getFirstUnallocated(Regs: ArgRegs);
438 MachineFrameInfo &MFI = MF.getFrameInfo();
439 RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
440
441 // Size of the vararg save area. For now, the varargs save area is either
442 // zero or large enough to hold a0-a7.
443 int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
444 int FI;
445
446 // If all registers are allocated, then all varargs must be passed on the
447 // stack and we don't need to save any argregs.
448 if (VarArgsSaveSize == 0) {
449 int VaArgOffset = Assigner.StackSize;
450 FI = MFI.CreateFixedObject(Size: XLenInBytes, SPOffset: VaArgOffset, IsImmutable: true);
451 } else {
452 int VaArgOffset = -VarArgsSaveSize;
453 FI = MFI.CreateFixedObject(Size: VarArgsSaveSize, SPOffset: VaArgOffset, IsImmutable: true);
454
455 // If saving an odd number of registers then create an extra stack slot to
456 // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures
457 // offsets to even-numbered registered remain 2*XLEN-aligned.
458 if (Idx % 2) {
459 MFI.CreateFixedObject(Size: XLenInBytes,
460 SPOffset: VaArgOffset - static_cast<int>(XLenInBytes), IsImmutable: true);
461 VarArgsSaveSize += XLenInBytes;
462 }
463
464 const LLT p0 = LLT::pointer(AddressSpace: MF.getDataLayout().getAllocaAddrSpace(),
465 SizeInBits: Subtarget.getXLen());
466 const LLT sXLen = LLT::scalar(SizeInBits: Subtarget.getXLen());
467
468 auto FIN = MIRBuilder.buildFrameIndex(Res: p0, Idx: FI);
469 auto Offset = MIRBuilder.buildConstant(
470 Res: MRI.createGenericVirtualRegister(Ty: sXLen), Val: XLenInBytes);
471
472 // Copy the integer registers that may have been used for passing varargs
473 // to the vararg save area.
474 const MVT XLenVT = Subtarget.getXLenVT();
475 for (unsigned I = Idx; I < ArgRegs.size(); ++I) {
476 const Register VReg = MRI.createGenericVirtualRegister(Ty: sXLen);
477 Handler.assignValueToReg(
478 ValVReg: VReg, PhysReg: ArgRegs[I],
479 VA: CCValAssign::getReg(ValNo: I + MF.getFunction().getNumOperands(), ValVT: XLenVT,
480 Reg: ArgRegs[I], LocVT: XLenVT, HTP: CCValAssign::Full));
481 auto MPO =
482 MachinePointerInfo::getFixedStack(MF, FI, Offset: (I - Idx) * XLenInBytes);
483 MIRBuilder.buildStore(Val: VReg, Addr: FIN, PtrInfo: MPO, Alignment: inferAlignFromPtrInfo(MF, MPO));
484 FIN = MIRBuilder.buildPtrAdd(Res: MRI.createGenericVirtualRegister(Ty: p0),
485 Op0: FIN.getReg(Idx: 0), Op1: Offset);
486 }
487 }
488
489 // Record the frame index of the first variable argument which is a value
490 // necessary to G_VASTART.
491 RVFI->setVarArgsFrameIndex(FI);
492 RVFI->setVarArgsSaveSize(VarArgsSaveSize);
493}
494
495bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
496 const Function &F,
497 ArrayRef<ArrayRef<Register>> VRegs,
498 FunctionLoweringInfo &FLI) const {
499 MachineFunction &MF = MIRBuilder.getMF();
500
501 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
502 for (auto &Arg : F.args()) {
503 if (!isSupportedArgumentType(T: Arg.getType(), Subtarget,
504 /*IsLowerArgs=*/true))
505 return false;
506 }
507
508 MachineRegisterInfo &MRI = MF.getRegInfo();
509 const DataLayout &DL = MF.getDataLayout();
510 CallingConv::ID CC = F.getCallingConv();
511
512 SmallVector<ArgInfo, 32> SplitArgInfos;
513
514 // Insert the hidden sret parameter if the return value won't fit in the
515 // return registers.
516 if (!FLI.CanLowerReturn)
517 insertSRetIncomingArgument(F, SplitArgs&: SplitArgInfos, DemoteReg&: FLI.DemoteRegister, MRI, DL);
518
519 unsigned Index = 0;
520 for (auto &Arg : F.args()) {
521 // Construct the ArgInfo object from destination register and argument type.
522 ArgInfo AInfo(VRegs[Index], Arg.getType(), Index);
523 setArgFlags(Arg&: AInfo, OpIdx: Index + AttributeList::FirstArgIndex, DL, FuncInfo: F);
524
525 // Handle any required merging from split value types from physical
526 // registers into the desired VReg. ArgInfo objects are constructed
527 // correspondingly and appended to SplitArgInfos.
528 splitToValueTypes(OrigArgInfo: AInfo, SplitArgs&: SplitArgInfos, DL, CallConv: CC);
529
530 ++Index;
531 }
532
533 IncomingValueAssigner Assigner(CC_RISCV);
534 RISCVFormalArgHandler Handler(MIRBuilder, MF.getRegInfo());
535
536 SmallVector<CCValAssign, 16> ArgLocs;
537 CCState CCInfo(CC, F.isVarArg(), MIRBuilder.getMF(), ArgLocs, F.getContext());
538 if (!determineAssignments(Assigner, Args&: SplitArgInfos, CCInfo) ||
539 !handleAssignments(Handler, Args&: SplitArgInfos, CCState&: CCInfo, ArgLocs, MIRBuilder))
540 return false;
541
542 if (any_of(Range&: ArgLocs,
543 P: [](CCValAssign &VA) { return VA.getLocVT().isScalableVector(); }))
544 MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
545
546 if (F.isVarArg())
547 saveVarArgRegisters(MIRBuilder, Handler, Assigner, CCInfo);
548
549 return true;
550}
551
552bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
553 CallLoweringInfo &Info) const {
554 MachineFunction &MF = MIRBuilder.getMF();
555 const DataLayout &DL = MF.getDataLayout();
556 CallingConv::ID CC = Info.CallConv;
557
558 const RISCVSubtarget &Subtarget =
559 MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
560 for (auto &AInfo : Info.OrigArgs) {
561 if (!isSupportedArgumentType(T: AInfo.Ty, Subtarget))
562 return false;
563 if (AInfo.Flags[0].isByVal())
564 return false;
565 }
566
567 if (!Info.OrigRet.Ty->isVoidTy() &&
568 !isSupportedReturnType(T: Info.OrigRet.Ty, Subtarget))
569 return false;
570
571 MachineInstrBuilder CallSeqStart =
572 MIRBuilder.buildInstr(Opcode: RISCV::ADJCALLSTACKDOWN);
573
574 SmallVector<ArgInfo, 32> SplitArgInfos;
575 for (auto &AInfo : Info.OrigArgs) {
576 // Handle any required unmerging of split value types from a given VReg into
577 // physical registers. ArgInfo objects are constructed correspondingly and
578 // appended to SplitArgInfos.
579 splitToValueTypes(OrigArgInfo: AInfo, SplitArgs&: SplitArgInfos, DL, CallConv: CC);
580 }
581
582 // TODO: Support tail calls.
583 Info.IsTailCall = false;
584
585 // Select the recommended relocation type R_RISCV_CALL_PLT.
586 if (!Info.Callee.isReg())
587 Info.Callee.setTargetFlags(RISCVII::MO_CALL);
588
589 MachineInstrBuilder Call =
590 MIRBuilder
591 .buildInstrNoInsert(Opcode: Info.Callee.isReg() ? RISCV::PseudoCALLIndirect
592 : RISCV::PseudoCALL)
593 .add(MO: Info.Callee);
594 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
595 Call.addRegMask(Mask: TRI->getCallPreservedMask(MF, Info.CallConv));
596
597 OutgoingValueAssigner ArgAssigner(CC_RISCV);
598 RISCVOutgoingValueHandler ArgHandler(MIRBuilder, MF.getRegInfo(), Call);
599 if (!determineAndHandleAssignments(Handler&: ArgHandler, Assigner&: ArgAssigner, Args&: SplitArgInfos,
600 MIRBuilder, CallConv: CC, IsVarArg: Info.IsVarArg))
601 return false;
602
603 MIRBuilder.insertInstr(MIB: Call);
604
605 CallSeqStart.addImm(Val: ArgAssigner.StackSize).addImm(Val: 0);
606 MIRBuilder.buildInstr(Opcode: RISCV::ADJCALLSTACKUP)
607 .addImm(Val: ArgAssigner.StackSize)
608 .addImm(Val: 0);
609
610 // If Callee is a reg, since it is used by a target specific
611 // instruction, it must have a register class matching the
612 // constraint of that instruction.
613 if (Call->getOperand(i: 0).isReg())
614 constrainOperandRegClass(MF, TRI: *TRI, MRI&: MF.getRegInfo(),
615 TII: *Subtarget.getInstrInfo(),
616 RBI: *Subtarget.getRegBankInfo(), InsertPt&: *Call,
617 II: Call->getDesc(), RegMO&: Call->getOperand(i: 0), OpIdx: 0);
618
619 if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
620 SmallVector<ArgInfo, 4> SplitRetInfos;
621 splitToValueTypes(OrigArgInfo: Info.OrigRet, SplitArgs&: SplitRetInfos, DL, CallConv: CC);
622
623 IncomingValueAssigner RetAssigner(RetCC_RISCV);
624 RISCVCallReturnHandler RetHandler(MIRBuilder, MF.getRegInfo(), Call);
625 if (!determineAndHandleAssignments(Handler&: RetHandler, Assigner&: RetAssigner, Args&: SplitRetInfos,
626 MIRBuilder, CallConv: CC, IsVarArg: Info.IsVarArg))
627 return false;
628 }
629
630 if (!Info.CanLowerReturn)
631 insertSRetLoads(MIRBuilder, RetTy: Info.OrigRet.Ty, VRegs: Info.OrigRet.Regs,
632 DemoteReg: Info.DemoteRegister, FI: Info.DemoteStackIndex);
633
634 return true;
635}
636