1//===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that RISC-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16
17#include "RISCV.h"
18#include "RISCVCallingConv.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/TargetLowering.h"
22#include <optional>
23
24namespace llvm {
25class InstructionCost;
26class RISCVSubtarget;
27struct RISCVRegisterInfo;
28
29class RISCVTargetLowering : public TargetLowering {
30 const RISCVSubtarget &Subtarget;
31
32public:
33 explicit RISCVTargetLowering(const TargetMachine &TM,
34 const RISCVSubtarget &STI);
35
36 const RISCVSubtarget &getSubtarget() const { return Subtarget; }
37
38 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
39 const CallBase &I, MachineFunction &MF,
40 unsigned Intrinsic) const override;
41 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
42 unsigned AS,
43 Instruction *I = nullptr) const override;
44 bool isLegalICmpImmediate(int64_t Imm) const override;
45 bool isLegalAddImmediate(int64_t Imm) const override;
46 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
47 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
48 bool isTruncateFree(SDValue Val, EVT VT2) const override;
49 bool isZExtFree(SDValue Val, EVT VT2) const override;
50 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
51 bool signExtendConstant(const ConstantInt *CI) const override;
52 bool isCheapToSpeculateCttz(Type *Ty) const override;
53 bool isCheapToSpeculateCtlz(Type *Ty) const override;
54 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
55 bool hasAndNotCompare(SDValue Y) const override;
56 bool hasAndNot(SDValue Y) const override;
57 bool hasBitTest(SDValue X, SDValue Y) const override;
58 bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
59 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
60 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
61 SelectionDAG &DAG) const override;
62 bool shouldScalarizeBinop(SDValue VecOp) const override;
63 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
64 int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
65 bool isFPImmLegal(const APFloat &Imm, EVT VT,
66 bool ForCodeSize) const override;
67 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
68 unsigned Index) const override;
69
70 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
71
72 bool preferScalarizeSplat(SDNode *N) const override;
73
74 void finalizeLowering(MachineFunction &MF) const override;
75
76 /// Customize the preferred legalization strategy for certain types.
77 LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
78
79 /// Return the register type for a given MVT, ensuring vectors are treated
80 /// as a series of gpr sized integers.
81 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
82 EVT VT) const override;
83
84 /// Return the number of registers for a given MVT, for inline assembly
85 unsigned
86 getNumRegisters(LLVMContext &Context, EVT VT,
87 std::optional<MVT> RegisterVT = std::nullopt) const override;
88
89 /// Return the number of registers for a given MVT, ensuring vectors are
90 /// treated as a series of gpr sized integers.
91 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
92 CallingConv::ID CC,
93 EVT VT) const override;
94
95 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT,
96 unsigned SelectOpcode, SDValue X,
97 SDValue Y) const override;
98
99 /// Return true if the given shuffle mask can be codegen'd directly, or if it
100 /// should be stack expanded.
101 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
102
103 bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
104 // If the pair to store is a mixture of float and int values, we will
105 // save two bitwise instructions and one float-to-int instruction and
106 // increase one store instruction. There is potentially a more
107 // significant benefit because it avoids the float->int domain switch
108 // for input value. So It is more likely a win.
109 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
110 (LTy.isInteger() && HTy.isFloatingPoint()))
111 return true;
112 // If the pair only contains int values, we will save two bitwise
113 // instructions and increase one store instruction (costing one more
114 // store buffer). Since the benefit is more blurred we leave such a pair
115 // out until we get testcase to prove it is a win.
116 return false;
117 }
118
119 bool
120 shouldExpandBuildVectorWithShuffles(EVT VT,
121 unsigned DefinedValues) const override;
122
123 bool shouldExpandCttzElements(EVT VT) const override;
124
125 /// Return the cost of LMUL for linear operations.
126 InstructionCost getLMULCost(MVT VT) const;
127
128 InstructionCost getVRGatherVVCost(MVT VT) const;
129 InstructionCost getVRGatherVICost(MVT VT) const;
130 InstructionCost getVSlideVXCost(MVT VT) const;
131 InstructionCost getVSlideVICost(MVT VT) const;
132
133 // Provide custom lowering hooks for some operations.
134 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
135 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
136 SelectionDAG &DAG) const override;
137
138 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
139
140 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
141 const APInt &DemandedElts,
142 TargetLoweringOpt &TLO) const override;
143
144 void computeKnownBitsForTargetNode(const SDValue Op,
145 KnownBits &Known,
146 const APInt &DemandedElts,
147 const SelectionDAG &DAG,
148 unsigned Depth) const override;
149
150 void computeKnownBitsForTargetInstr(GISelValueTracking &Analysis, Register R,
151 KnownBits &Known,
152 const APInt &DemandedElts,
153 const MachineRegisterInfo &MRI,
154 unsigned Depth = 0) const override;
155 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
156 const APInt &DemandedElts,
157 const SelectionDAG &DAG,
158 unsigned Depth) const override;
159
160 bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits,
161 const APInt &DemandedElts,
162 KnownBits &Known,
163 TargetLoweringOpt &TLO,
164 unsigned Depth) const override;
165
166 bool canCreateUndefOrPoisonForTargetNode(
167 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
168 UndefPoisonKind Kind, bool ConsiderFlags, unsigned Depth) const override;
169
170 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
171
172 MachineMemOperand::Flags
173 getTargetMMOFlags(const Instruction &I) const override;
174
175 MachineMemOperand::Flags
176 getTargetMMOFlags(const MemSDNode &Node) const override;
177
178 bool
179 areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX,
180 const MemSDNode &NodeY) const override;
181
182 ConstraintType getConstraintType(StringRef Constraint) const override;
183
184 InlineAsm::ConstraintCode
185 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
186
187 std::pair<unsigned, const TargetRegisterClass *>
188 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
189 StringRef Constraint, MVT VT) const override;
190
191 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
192 std::vector<SDValue> &Ops,
193 SelectionDAG &DAG) const override;
194
195 MachineBasicBlock *
196 EmitInstrWithCustomInserter(MachineInstr &MI,
197 MachineBasicBlock *BB) const override;
198
199 void AdjustInstrPostInstrSelection(MachineInstr &MI,
200 SDNode *Node) const override;
201
202 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
203 EVT VT) const override;
204
205 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
206 bool MathUsed) const override {
207 if (VT == MVT::i8 || VT == MVT::i16)
208 return false;
209
210 return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
211 }
212
213 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
214 unsigned AddrSpace) const override {
215 // If we can replace 4 or more scalar stores, there will be a reduction
216 // in instructions even after we add a vector constant load.
217 return NumElem >= 4;
218 }
219
220 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
221 return VT.isScalarInteger();
222 }
223 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
224
225 bool isCtpopFast(EVT VT) const override;
226
227 unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override;
228
229 bool preferZeroCompareBranch() const override { return true; }
230
231 // Note that one specific case requires fence insertion for an
232 // AtomicCmpXchgInst but is handled via the RISCVZacasABIFix pass rather
233 // than this hook due to limitations in the interface here.
234 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
235
236 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
237 AtomicOrdering Ord) const override;
238 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
239 AtomicOrdering Ord) const override;
240
241 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
242 EVT VT) const override;
243
244 ISD::NodeType getExtendForAtomicOps() const override {
245 return ISD::SIGN_EXTEND;
246 }
247
248 ISD::NodeType getExtendForAtomicCmpSwapArg() const override;
249 ISD::NodeType getExtendForAtomicRMWArg(unsigned Op) const override;
250
251 bool shouldTransformSignedTruncationCheck(EVT XVT,
252 unsigned KeptBits) const override;
253
254 TargetLowering::ShiftLegalizationStrategy
255 preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
256 unsigned ExpansionFactor) const override {
257 if (DAG.getMachineFunction().getFunction().hasMinSize())
258 return ShiftLegalizationStrategy::LowerToLibcall;
259 return TargetLowering::preferredShiftLegalizationStrategy(DAG, N,
260 ExpansionFactor);
261 }
262
263 bool isDesirableToCommuteWithShift(const SDNode *N,
264 CombineLevel Level) const override;
265
266 /// If a physical register, this returns the register that receives the
267 /// exception address on entry to an EH pad.
268 Register
269 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
270
271 /// If a physical register, this returns the register that receives the
272 /// exception typeid on entry to a landing pad.
273 Register
274 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
275
276 bool shouldExtendTypeInLibCall(EVT Type) const override;
277 bool shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const override;
278
279 /// Returns the register with the specified architectural or ABI name. This
280 /// method is necessary to lower the llvm.read_register.* and
281 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
282 /// with the clang -ffixed-xX flag for access to be allowed.
283 Register getRegisterByName(const char *RegName, LLT VT,
284 const MachineFunction &MF) const override;
285
286 // Lower incoming arguments, copy physregs into vregs
287 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
288 bool IsVarArg,
289 const SmallVectorImpl<ISD::InputArg> &Ins,
290 const SDLoc &DL, SelectionDAG &DAG,
291 SmallVectorImpl<SDValue> &InVals) const override;
292 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
293 bool IsVarArg,
294 const SmallVectorImpl<ISD::OutputArg> &Outs,
295 LLVMContext &Context, const Type *RetTy) const override;
296 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
297 const SmallVectorImpl<ISD::OutputArg> &Outs,
298 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
299 SelectionDAG &DAG) const override;
300 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
301 SmallVectorImpl<SDValue> &InVals) const override;
302
303 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
304 Type *Ty) const override;
305 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
306 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
307 bool shouldConsiderGEPOffsetSplit() const override { return true; }
308
309 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
310 SDValue C) const override;
311
312 bool isMulAddWithConstProfitable(SDValue AddNode,
313 SDValue ConstNode) const override;
314
315 TargetLowering::AtomicExpansionKind
316 shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override;
317 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI,
318 Value *AlignedAddr, Value *Incr,
319 Value *Mask, Value *ShiftAmt,
320 AtomicOrdering Ord) const override;
321 TargetLowering::AtomicExpansionKind
322 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *CI) const override;
323 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder,
324 AtomicCmpXchgInst *CI,
325 Value *AlignedAddr, Value *CmpVal,
326 Value *NewVal, Value *Mask,
327 AtomicOrdering Ord) const override;
328
329 /// Returns true if the target allows unaligned memory accesses of the
330 /// specified type.
331 bool allowsMisalignedMemoryAccesses(
332 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
333 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
334 unsigned *Fast = nullptr) const override;
335
336 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
337 const AttributeList &FuncAttributes) const override;
338
339 bool splitValueIntoRegisterParts(
340 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
341 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
342 const override;
343
344 SDValue joinRegisterPartsIntoValue(
345 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
346 unsigned NumParts, MVT PartVT, EVT ValueVT,
347 std::optional<CallingConv::ID> CC) const override;
348
349 // Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
350 SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
351
352 static RISCVVType::VLMUL getLMUL(MVT VT);
353 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
354 unsigned MinSize) {
355 // Original equation:
356 // VLMAX = (VectorBits / EltSize) * LMUL
357 // where LMUL = MinSize / RISCV::RVVBitsPerBlock
358 // The following equations have been reordered to prevent loss of precision
359 // when calculating fractional LMUL.
360 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
361 }
362
363 // Return inclusive (low, high) bounds on the value of VLMAX for the
364 // given scalable container type given known bounds on VLEN.
365 static std::pair<unsigned, unsigned>
366 computeVLMAXBounds(MVT ContainerVT, const RISCVSubtarget &Subtarget);
367
368 /// Given a vector (either fixed or scalable), return the scalable vector
369 /// corresponding to a vector register (i.e. an m1 register group).
370 static MVT getM1VT(MVT VT) {
371 unsigned EltSizeInBits = VT.getVectorElementType().getSizeInBits();
372 assert(EltSizeInBits <= RISCV::RVVBitsPerBlock && "Unexpected vector MVT");
373 return MVT::getScalableVectorVT(VT: VT.getVectorElementType(),
374 NumElements: RISCV::RVVBitsPerBlock / EltSizeInBits);
375 }
376
377 static unsigned getRegClassIDForLMUL(RISCVVType::VLMUL LMul);
378 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
379 static unsigned getRegClassIDForVecVT(MVT VT);
380 static std::pair<unsigned, unsigned>
381 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
382 unsigned InsertExtractIdx,
383 const RISCVRegisterInfo *TRI);
384 MVT getContainerForFixedLengthVector(MVT VT) const;
385
386 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
387
388 bool isLegalElementTypeForRVV(EVT ScalarTy) const;
389
390 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
391
392 unsigned getJumpTableEncoding() const override;
393
394 const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
395 const MachineBasicBlock *MBB,
396 unsigned uid,
397 MCContext &Ctx) const override;
398
399 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
400 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const;
401 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
402 ISD::MemIndexedMode &AM,
403 SelectionDAG &DAG) const override;
404 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
405 SDValue &Offset, ISD::MemIndexedMode &AM,
406 SelectionDAG &DAG) const override;
407
408 bool isLegalScaleForGatherScatter(uint64_t Scale,
409 uint64_t ElemSize) const override {
410 // Scaled addressing not supported on indexed load/stores
411 return Scale == 1;
412 }
413
414 /// If the target has a standard location for the stack protector cookie,
415 /// returns the address of that location. Otherwise, returns nullptr.
416 Value *getIRStackGuard(IRBuilderBase &IRB,
417 const LibcallLoweringInfo &Libcalls) const override;
418
419 /// Returns whether or not generating a interleaved load/store intrinsic for
420 /// this type will be legal.
421 bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
422 Align Alignment, unsigned AddrSpace,
423 const DataLayout &) const;
424
425 /// Return true if a stride load store of the given result type and
426 /// alignment is legal.
427 bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const;
428
429 /// Return true if a fault-only-first load of the given result type and
430 /// alignment is legal.
431 bool isLegalFirstFaultLoad(EVT DataType, Align Alignment) const;
432
433 unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
434
435 bool fallBackToDAGISel(const Instruction &Inst) const override;
436
437 bool lowerInterleavedLoad(Instruction *Load, Value *Mask,
438 ArrayRef<ShuffleVectorInst *> Shuffles,
439 ArrayRef<unsigned> Indices, unsigned Factor,
440 const APInt &GapMask) const override;
441
442 bool lowerInterleavedStore(Instruction *Store, Value *Mask,
443 ShuffleVectorInst *SVI, unsigned Factor,
444 const APInt &GapMask) const override;
445
446 bool lowerDeinterleaveIntrinsicToLoad(Instruction *Load, Value *Mask,
447 IntrinsicInst *DI,
448 const APInt &GapMask) const override;
449
450 bool lowerInterleaveIntrinsicToStore(
451 Instruction *Store, Value *Mask,
452 ArrayRef<Value *> InterleaveValues) const override;
453
454 bool supportKCFIBundles() const override { return true; }
455
456 SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr,
457 int JTI, SelectionDAG &DAG) const override;
458
459 MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB,
460 MachineBasicBlock::instr_iterator &MBBI,
461 const TargetInstrInfo *TII) const override;
462
463 /// True if stack clash protection is enabled for this functions.
464 bool hasInlineStackProbe(const MachineFunction &MF) const override;
465
466 unsigned getStackProbeSize(const MachineFunction &MF, Align StackAlign) const;
467
468 MachineBasicBlock *emitDynamicProbedAlloc(MachineInstr &MI,
469 MachineBasicBlock *MBB) const;
470
471 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
472
473 bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
474
475 /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
476 /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
477 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
478 SDValue N1) const override;
479
480 /// Match a mask which "spreads" the leading elements of a vector evenly
481 /// across the result. Factor is the spread amount, and Index is the
482 /// offset applied.
483 static bool isSpreadMask(ArrayRef<int> Mask, unsigned Factor,
484 unsigned &Index);
485
486private:
487 template <class NodeTy>
488 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
489 bool IsExternWeak = false) const;
490 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
491 bool UseGOT) const;
492 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
493 SDValue getTLSDescAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
494
495 SDValue lowerConstantFP(SDValue Op, SelectionDAG &DAG) const;
496 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
497 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
498 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
499 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
500 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
501 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
502 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
503 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
504 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
505 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
506 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
507 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
508 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
509 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
510 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
511 int64_t ExtTrueVal) const;
512 SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
513 SDValue lowerVectorTrunc(SDValue Op, SelectionDAG &DAG) const;
514 SDValue lowerVectorFPExtendOrRound(SDValue Op, SelectionDAG &DAG) const;
515 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
516 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
520 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
521 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
522 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
523 bool IsVP) const;
524 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
525 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
526 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
527 SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
528 SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
529 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
530 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
531 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
532 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
533 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
534 SDValue lowerLoadFF(SDValue Op, SelectionDAG &DAG) const;
535 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
536 SDValue lowerVectorCompress(SDValue Op, SelectionDAG &DAG) const;
537 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
538 SelectionDAG &DAG) const;
539 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
540 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
541 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
542 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
543 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
544 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
545 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const;
546 SDValue lowerVPMergeMask(SDValue Op, SelectionDAG &DAG) const;
547 SDValue lowerVPSpliceExperimental(SDValue Op, SelectionDAG &DAG) const;
548 SDValue lowerVPReverseExperimental(SDValue Op, SelectionDAG &DAG) const;
549 SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
550 SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
551 SDValue lowerVPCttzElements(SDValue Op, SelectionDAG &DAG) const;
552 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
553 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
554 SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
555 SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
556 SDValue lowerRESET_FPENV(SDValue Op, SelectionDAG &DAG) const;
557 SDValue lowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
558 SDValue lowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
559 SDValue lowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
560
561 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
562 SDValue lowerCTLZ_CTTZ_ZERO_POISON(SDValue Op, SelectionDAG &DAG) const;
563
564 SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
565
566 SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
567
568 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
569
570 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
571 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
572
573 SDValue expandUnalignedVPLoad(SDValue Op, SelectionDAG &DAG) const;
574 SDValue expandUnalignedVPStore(SDValue Op, SelectionDAG &DAG) const;
575
576 SDValue lowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
577 SDValue lowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
578 SDValue lowerPARTIAL_REDUCE_MLA(SDValue Op, SelectionDAG &DAG) const;
579 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
580
581 SDValue lowerXAndesBfHCvtBFloat16Load(SDValue Op, SelectionDAG &DAG) const;
582 SDValue lowerXAndesBfHCvtBFloat16Store(SDValue Op, SelectionDAG &DAG) const;
583
584 bool isEligibleForTailCallOptimization(
585 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
586 const SmallVector<CCValAssign, 16> &ArgLocs) const;
587
588 /// Generate error diagnostics if any register used by CC has been marked
589 /// reserved.
590 void validateCCReservedRegs(
591 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
592 MachineFunction &MF) const;
593
594 bool useRVVForFixedLengthVectorVT(MVT VT) const;
595
596 MVT getVPExplicitVectorLengthTy() const override;
597
598 bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,
599 bool IsScalable) const override;
600
601 /// RVV code generation for fixed length vectors does not lower all
602 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
603 /// merge. However, merging them creates a BUILD_VECTOR that is just as
604 /// illegal as the original, thus leading to an infinite legalisation loop.
605 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
606 /// this override can be removed.
607 bool mergeStoresAfterLegalization(EVT VT) const override;
608
609 /// Disable normalizing
610 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
611 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
612 /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
613 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT, EVT) const override {
614 return false;
615 }
616
617 /// Disables storing and loading vectors by default when there are function
618 /// calls between the load and store, since these are more expensive than just
619 /// using scalars
620 bool shouldMergeStoreOfLoadsOverCall(EVT SrcVT, EVT MergedVT) const override {
621 return !MergedVT.isVector() || SrcVT.isVector();
622 }
623
624 /// For available scheduling models FDIV + two independent FMULs are much
625 /// faster than two FDIVs.
626 unsigned combineRepeatedFPDivisors() const override;
627
628 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
629 SmallVectorImpl<SDNode *> &Created) const override;
630
631 bool shouldFoldSelectWithSingleBitTest(EVT VT,
632 const APInt &AndMask) const override;
633
634 unsigned getMinimumJumpTableEntries() const override;
635
636 SDValue emitFlushICache(SelectionDAG &DAG, SDValue InChain, SDValue Start,
637 SDValue End, SDValue Flags, SDLoc DL) const;
638
639 std::pair<const TargetRegisterClass *, uint8_t>
640 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override;
641};
642
643namespace RISCVVIntrinsicsTable {
644
645struct RISCVVIntrinsicInfo {
646 unsigned IntrinsicID;
647 uint8_t ScalarOperand;
648 uint8_t VLOperand;
649 bool IsFPIntrinsic;
650 bool hasScalarOperand() const {
651 // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
652 return ScalarOperand != 0xF;
653 }
654 bool hasVLOperand() const {
655 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
656 return VLOperand != 0x1F;
657 }
658};
659
660using namespace RISCV;
661
662#define GET_RISCVVIntrinsicsTable_DECL
663#include "RISCVGenSearchableTables.inc"
664#undef GET_RISCVVIntrinsicsTable_DECL
665
666} // end namespace RISCVVIntrinsicsTable
667
668} // end namespace llvm
669
670#endif
671