1//===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that RISC-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16
17#include "RISCV.h"
18#include "RISCVCallingConv.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/TargetLowering.h"
22#include <optional>
23
24namespace llvm {
25class InstructionCost;
26class RISCVSubtarget;
27struct RISCVRegisterInfo;
28
29class RISCVTargetLowering : public TargetLowering {
30 const RISCVSubtarget &Subtarget;
31
32public:
33 explicit RISCVTargetLowering(const TargetMachine &TM,
34 const RISCVSubtarget &STI);
35
36 const RISCVSubtarget &getSubtarget() const { return Subtarget; }
37
38 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
39 const CallBase &I, MachineFunction &MF,
40 unsigned Intrinsic) const override;
41 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
42 unsigned AS,
43 Instruction *I = nullptr) const override;
44 bool isLegalICmpImmediate(int64_t Imm) const override;
45 bool isLegalAddImmediate(int64_t Imm) const override;
46 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
47 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
48 bool isTruncateFree(SDValue Val, EVT VT2) const override;
49 bool isZExtFree(SDValue Val, EVT VT2) const override;
50 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
51 bool signExtendConstant(const ConstantInt *CI) const override;
52 bool isCheapToSpeculateCttz(Type *Ty) const override;
53 bool isCheapToSpeculateCtlz(Type *Ty) const override;
54 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
55 bool hasAndNotCompare(SDValue Y) const override;
56 bool hasAndNot(SDValue Y) const override;
57 bool hasBitTest(SDValue X, SDValue Y) const override;
58 bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
59 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
60 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
61 SelectionDAG &DAG) const override;
62 bool shouldScalarizeBinop(SDValue VecOp) const override;
63 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
64 int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
65 bool isFPImmLegal(const APFloat &Imm, EVT VT,
66 bool ForCodeSize) const override;
67 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
68 unsigned Index) const override;
69
70 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
71
72 bool preferScalarizeSplat(SDNode *N) const override;
73
74 void finalizeLowering(MachineFunction &MF) const override;
75
76 /// Customize the preferred legalization strategy for certain types.
77 LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
78
79 /// Return the register type for a given MVT, ensuring vectors are treated
80 /// as a series of gpr sized integers.
81 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
82 EVT VT) const override;
83
84 /// Return the number of registers for a given MVT, for inline assembly
85 unsigned
86 getNumRegisters(LLVMContext &Context, EVT VT,
87 std::optional<MVT> RegisterVT = std::nullopt) const override;
88
89 /// Return the number of registers for a given MVT, ensuring vectors are
90 /// treated as a series of gpr sized integers.
91 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
92 CallingConv::ID CC,
93 EVT VT) const override;
94
95 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT,
96 unsigned SelectOpcode, SDValue X,
97 SDValue Y) const override;
98
99 /// Return true if the given shuffle mask can be codegen'd directly, or if it
100 /// should be stack expanded.
101 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
102
103 bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
104 // If the pair to store is a mixture of float and int values, we will
105 // save two bitwise instructions and one float-to-int instruction and
106 // increase one store instruction. There is potentially a more
107 // significant benefit because it avoids the float->int domain switch
108 // for input value. So It is more likely a win.
109 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
110 (LTy.isInteger() && HTy.isFloatingPoint()))
111 return true;
112 // If the pair only contains int values, we will save two bitwise
113 // instructions and increase one store instruction (costing one more
114 // store buffer). Since the benefit is more blurred we leave such a pair
115 // out until we get testcase to prove it is a win.
116 return false;
117 }
118
119 bool
120 shouldExpandBuildVectorWithShuffles(EVT VT,
121 unsigned DefinedValues) const override;
122
123 bool shouldExpandCttzElements(EVT VT) const override;
124
125 /// Return the cost of LMUL for linear operations.
126 InstructionCost getLMULCost(MVT VT) const;
127
128 InstructionCost getVRGatherVVCost(MVT VT) const;
129 InstructionCost getVRGatherVICost(MVT VT) const;
130 InstructionCost getVSlideVXCost(MVT VT) const;
131 InstructionCost getVSlideVICost(MVT VT) const;
132
133 // Provide custom lowering hooks for some operations.
134 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
135 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
136 SelectionDAG &DAG) const override;
137
138 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
139
140 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
141 const APInt &DemandedElts,
142 TargetLoweringOpt &TLO) const override;
143
144 void computeKnownBitsForTargetNode(const SDValue Op,
145 KnownBits &Known,
146 const APInt &DemandedElts,
147 const SelectionDAG &DAG,
148 unsigned Depth) const override;
149 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
150 const APInt &DemandedElts,
151 const SelectionDAG &DAG,
152 unsigned Depth) const override;
153
154 bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits,
155 const APInt &DemandedElts,
156 KnownBits &Known,
157 TargetLoweringOpt &TLO,
158 unsigned Depth) const override;
159
160 bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
161 const APInt &DemandedElts,
162 const SelectionDAG &DAG,
163 bool PoisonOnly, bool ConsiderFlags,
164 unsigned Depth) const override;
165
166 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
167
168 MachineMemOperand::Flags
169 getTargetMMOFlags(const Instruction &I) const override;
170
171 MachineMemOperand::Flags
172 getTargetMMOFlags(const MemSDNode &Node) const override;
173
174 bool
175 areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX,
176 const MemSDNode &NodeY) const override;
177
178 ConstraintType getConstraintType(StringRef Constraint) const override;
179
180 InlineAsm::ConstraintCode
181 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
182
183 std::pair<unsigned, const TargetRegisterClass *>
184 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
185 StringRef Constraint, MVT VT) const override;
186
187 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
188 std::vector<SDValue> &Ops,
189 SelectionDAG &DAG) const override;
190
191 MachineBasicBlock *
192 EmitInstrWithCustomInserter(MachineInstr &MI,
193 MachineBasicBlock *BB) const override;
194
195 void AdjustInstrPostInstrSelection(MachineInstr &MI,
196 SDNode *Node) const override;
197
198 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
199 EVT VT) const override;
200
201 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
202 bool MathUsed) const override {
203 if (VT == MVT::i8 || VT == MVT::i16)
204 return false;
205
206 return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
207 }
208
209 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
210 unsigned AddrSpace) const override {
211 // If we can replace 4 or more scalar stores, there will be a reduction
212 // in instructions even after we add a vector constant load.
213 return NumElem >= 4;
214 }
215
216 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
217 return VT.isScalarInteger();
218 }
219 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
220
221 bool isCtpopFast(EVT VT) const override;
222
223 unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override;
224
225 bool preferZeroCompareBranch() const override { return true; }
226
227 // Note that one specific case requires fence insertion for an
228 // AtomicCmpXchgInst but is handled via the RISCVZacasABIFix pass rather
229 // than this hook due to limitations in the interface here.
230 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
231
232 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
233 AtomicOrdering Ord) const override;
234 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
235 AtomicOrdering Ord) const override;
236
237 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
238 EVT VT) const override;
239
240 ISD::NodeType getExtendForAtomicOps() const override {
241 return ISD::SIGN_EXTEND;
242 }
243
244 ISD::NodeType getExtendForAtomicCmpSwapArg() const override;
245 ISD::NodeType getExtendForAtomicRMWArg(unsigned Op) const override;
246
247 bool shouldTransformSignedTruncationCheck(EVT XVT,
248 unsigned KeptBits) const override;
249
250 TargetLowering::ShiftLegalizationStrategy
251 preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
252 unsigned ExpansionFactor) const override {
253 if (DAG.getMachineFunction().getFunction().hasMinSize())
254 return ShiftLegalizationStrategy::LowerToLibcall;
255 return TargetLowering::preferredShiftLegalizationStrategy(DAG, N,
256 ExpansionFactor);
257 }
258
259 bool isDesirableToCommuteWithShift(const SDNode *N,
260 CombineLevel Level) const override;
261
262 /// If a physical register, this returns the register that receives the
263 /// exception address on entry to an EH pad.
264 Register
265 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
266
267 /// If a physical register, this returns the register that receives the
268 /// exception typeid on entry to a landing pad.
269 Register
270 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
271
272 bool shouldExtendTypeInLibCall(EVT Type) const override;
273 bool shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const override;
274
275 /// Returns the register with the specified architectural or ABI name. This
276 /// method is necessary to lower the llvm.read_register.* and
277 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
278 /// with the clang -ffixed-xX flag for access to be allowed.
279 Register getRegisterByName(const char *RegName, LLT VT,
280 const MachineFunction &MF) const override;
281
282 // Lower incoming arguments, copy physregs into vregs
283 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
284 bool IsVarArg,
285 const SmallVectorImpl<ISD::InputArg> &Ins,
286 const SDLoc &DL, SelectionDAG &DAG,
287 SmallVectorImpl<SDValue> &InVals) const override;
288 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
289 bool IsVarArg,
290 const SmallVectorImpl<ISD::OutputArg> &Outs,
291 LLVMContext &Context, const Type *RetTy) const override;
292 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
293 const SmallVectorImpl<ISD::OutputArg> &Outs,
294 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
295 SelectionDAG &DAG) const override;
296 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
297 SmallVectorImpl<SDValue> &InVals) const override;
298
299 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
300 Type *Ty) const override;
301 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
302 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
303 bool shouldConsiderGEPOffsetSplit() const override { return true; }
304
305 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
306 SDValue C) const override;
307
308 bool isMulAddWithConstProfitable(SDValue AddNode,
309 SDValue ConstNode) const override;
310
311 TargetLowering::AtomicExpansionKind
312 shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override;
313 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI,
314 Value *AlignedAddr, Value *Incr,
315 Value *Mask, Value *ShiftAmt,
316 AtomicOrdering Ord) const override;
317 TargetLowering::AtomicExpansionKind
318 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *CI) const override;
319 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder,
320 AtomicCmpXchgInst *CI,
321 Value *AlignedAddr, Value *CmpVal,
322 Value *NewVal, Value *Mask,
323 AtomicOrdering Ord) const override;
324
325 /// Returns true if the target allows unaligned memory accesses of the
326 /// specified type.
327 bool allowsMisalignedMemoryAccesses(
328 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
329 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
330 unsigned *Fast = nullptr) const override;
331
332 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
333 const AttributeList &FuncAttributes) const override;
334
335 bool splitValueIntoRegisterParts(
336 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
337 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
338 const override;
339
340 SDValue joinRegisterPartsIntoValue(
341 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
342 unsigned NumParts, MVT PartVT, EVT ValueVT,
343 std::optional<CallingConv::ID> CC) const override;
344
345 // Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
346 SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
347
348 static RISCVVType::VLMUL getLMUL(MVT VT);
349 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
350 unsigned MinSize) {
351 // Original equation:
352 // VLMAX = (VectorBits / EltSize) * LMUL
353 // where LMUL = MinSize / RISCV::RVVBitsPerBlock
354 // The following equations have been reordered to prevent loss of precision
355 // when calculating fractional LMUL.
356 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
357 }
358
359 // Return inclusive (low, high) bounds on the value of VLMAX for the
360 // given scalable container type given known bounds on VLEN.
361 static std::pair<unsigned, unsigned>
362 computeVLMAXBounds(MVT ContainerVT, const RISCVSubtarget &Subtarget);
363
364 /// Given a vector (either fixed or scalable), return the scalable vector
365 /// corresponding to a vector register (i.e. an m1 register group).
366 static MVT getM1VT(MVT VT) {
367 unsigned EltSizeInBits = VT.getVectorElementType().getSizeInBits();
368 assert(EltSizeInBits <= RISCV::RVVBitsPerBlock && "Unexpected vector MVT");
369 return MVT::getScalableVectorVT(VT: VT.getVectorElementType(),
370 NumElements: RISCV::RVVBitsPerBlock / EltSizeInBits);
371 }
372
373 static unsigned getRegClassIDForLMUL(RISCVVType::VLMUL LMul);
374 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
375 static unsigned getRegClassIDForVecVT(MVT VT);
376 static std::pair<unsigned, unsigned>
377 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
378 unsigned InsertExtractIdx,
379 const RISCVRegisterInfo *TRI);
380 MVT getContainerForFixedLengthVector(MVT VT) const;
381
382 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
383
384 bool isLegalElementTypeForRVV(EVT ScalarTy) const;
385
386 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
387
388 unsigned getJumpTableEncoding() const override;
389
390 const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
391 const MachineBasicBlock *MBB,
392 unsigned uid,
393 MCContext &Ctx) const override;
394
395 bool isVScaleKnownToBeAPowerOfTwo() const override;
396
397 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
398 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const;
399 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
400 ISD::MemIndexedMode &AM,
401 SelectionDAG &DAG) const override;
402 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
403 SDValue &Offset, ISD::MemIndexedMode &AM,
404 SelectionDAG &DAG) const override;
405
406 bool isLegalScaleForGatherScatter(uint64_t Scale,
407 uint64_t ElemSize) const override {
408 // Scaled addressing not supported on indexed load/stores
409 return Scale == 1;
410 }
411
412 /// If the target has a standard location for the stack protector cookie,
413 /// returns the address of that location. Otherwise, returns nullptr.
414 Value *getIRStackGuard(IRBuilderBase &IRB,
415 const LibcallLoweringInfo &Libcalls) const override;
416
417 /// Returns whether or not generating a interleaved load/store intrinsic for
418 /// this type will be legal.
419 bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
420 Align Alignment, unsigned AddrSpace,
421 const DataLayout &) const;
422
423 /// Return true if a stride load store of the given result type and
424 /// alignment is legal.
425 bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const;
426
427 /// Return true if a fault-only-first load of the given result type and
428 /// alignment is legal.
429 bool isLegalFirstFaultLoad(EVT DataType, Align Alignment) const;
430
431 unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
432
433 bool fallBackToDAGISel(const Instruction &Inst) const override;
434
435 bool lowerInterleavedLoad(Instruction *Load, Value *Mask,
436 ArrayRef<ShuffleVectorInst *> Shuffles,
437 ArrayRef<unsigned> Indices, unsigned Factor,
438 const APInt &GapMask) const override;
439
440 bool lowerInterleavedStore(Instruction *Store, Value *Mask,
441 ShuffleVectorInst *SVI, unsigned Factor,
442 const APInt &GapMask) const override;
443
444 bool lowerDeinterleaveIntrinsicToLoad(Instruction *Load, Value *Mask,
445 IntrinsicInst *DI) const override;
446
447 bool lowerInterleaveIntrinsicToStore(
448 Instruction *Store, Value *Mask,
449 ArrayRef<Value *> InterleaveValues) const override;
450
451 bool supportKCFIBundles() const override { return true; }
452
453 SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr,
454 int JTI, SelectionDAG &DAG) const override;
455
456 MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB,
457 MachineBasicBlock::instr_iterator &MBBI,
458 const TargetInstrInfo *TII) const override;
459
460 /// True if stack clash protection is enabled for this functions.
461 bool hasInlineStackProbe(const MachineFunction &MF) const override;
462
463 unsigned getStackProbeSize(const MachineFunction &MF, Align StackAlign) const;
464
465 MachineBasicBlock *emitDynamicProbedAlloc(MachineInstr &MI,
466 MachineBasicBlock *MBB) const;
467
468 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
469
470 bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
471
472 /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
473 /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
474 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
475 SDValue N1) const override;
476
477 /// Match a mask which "spreads" the leading elements of a vector evenly
478 /// across the result. Factor is the spread amount, and Index is the
479 /// offset applied.
480 static bool isSpreadMask(ArrayRef<int> Mask, unsigned Factor,
481 unsigned &Index);
482
483private:
484 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
485 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
486 RISCVCCAssignFn Fn) const;
487 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
488 const SmallVectorImpl<ISD::OutputArg> &Outs,
489 bool IsRet, CallLoweringInfo *CLI,
490 RISCVCCAssignFn Fn) const;
491
492 template <class NodeTy>
493 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
494 bool IsExternWeak = false) const;
495 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
496 bool UseGOT) const;
497 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
498 SDValue getTLSDescAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
499
500 SDValue lowerConstantFP(SDValue Op, SelectionDAG &DAG) const;
501 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
502 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
503 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
504 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
505 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
506 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
507 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
508 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
509 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
510 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
511 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
512 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
513 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
514 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
515 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
516 int64_t ExtTrueVal) const;
517 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
518 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
519 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
520 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
521 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
522 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
523 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
524 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
525 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
526 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
527 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
528 bool IsVP) const;
529 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
530 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
531 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
532 SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
533 SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
534 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
535 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
536 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
537 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
538 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
539 SDValue lowerLoadFF(SDValue Op, SelectionDAG &DAG) const;
540 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
541 SDValue lowerVectorCompress(SDValue Op, SelectionDAG &DAG) const;
542 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
543 SelectionDAG &DAG) const;
544 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
545 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
546 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
547 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
548 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
549 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
550 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const;
551 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG) const;
552 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
553 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
554 SDValue lowerVPMergeMask(SDValue Op, SelectionDAG &DAG) const;
555 SDValue lowerVPSpliceExperimental(SDValue Op, SelectionDAG &DAG) const;
556 SDValue lowerVPReverseExperimental(SDValue Op, SelectionDAG &DAG) const;
557 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG) const;
558 SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
559 SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
560 SDValue lowerVPCttzElements(SDValue Op, SelectionDAG &DAG) const;
561 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
562 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
563 SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
564 SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
565 SDValue lowerRESET_FPENV(SDValue Op, SelectionDAG &DAG) const;
566 SDValue lowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
567 SDValue lowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
568 SDValue lowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
569
570 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
571 SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
572
573 SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
574
575 SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
576
577 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
578
579 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
580 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
581
582 SDValue expandUnalignedVPLoad(SDValue Op, SelectionDAG &DAG) const;
583 SDValue expandUnalignedVPStore(SDValue Op, SelectionDAG &DAG) const;
584
585 SDValue lowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
586 SDValue lowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
587 SDValue lowerPARTIAL_REDUCE_MLA(SDValue Op, SelectionDAG &DAG) const;
588
589 SDValue lowerXAndesBfHCvtBFloat16Load(SDValue Op, SelectionDAG &DAG) const;
590 SDValue lowerXAndesBfHCvtBFloat16Store(SDValue Op, SelectionDAG &DAG) const;
591
592 bool isEligibleForTailCallOptimization(
593 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
594 const SmallVector<CCValAssign, 16> &ArgLocs) const;
595
596 /// Generate error diagnostics if any register used by CC has been marked
597 /// reserved.
598 void validateCCReservedRegs(
599 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
600 MachineFunction &MF) const;
601
602 bool useRVVForFixedLengthVectorVT(MVT VT) const;
603
604 MVT getVPExplicitVectorLengthTy() const override;
605
606 bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,
607 bool IsScalable) const override;
608
609 /// RVV code generation for fixed length vectors does not lower all
610 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
611 /// merge. However, merging them creates a BUILD_VECTOR that is just as
612 /// illegal as the original, thus leading to an infinite legalisation loop.
613 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
614 /// this override can be removed.
615 bool mergeStoresAfterLegalization(EVT VT) const override;
616
617 /// Disable normalizing
618 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
619 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
620 /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
621 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
622 return false;
623 }
624
625 /// Disables storing and loading vectors by default when there are function
626 /// calls between the load and store, since these are more expensive than just
627 /// using scalars
628 bool shouldMergeStoreOfLoadsOverCall(EVT SrcVT, EVT MergedVT) const override {
629 return !MergedVT.isVector() || SrcVT.isVector();
630 }
631
632 /// For available scheduling models FDIV + two independent FMULs are much
633 /// faster than two FDIVs.
634 unsigned combineRepeatedFPDivisors() const override;
635
636 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
637 SmallVectorImpl<SDNode *> &Created) const override;
638
639 bool shouldFoldSelectWithSingleBitTest(EVT VT,
640 const APInt &AndMask) const override;
641
642 unsigned getMinimumJumpTableEntries() const override;
643
644 SDValue emitFlushICache(SelectionDAG &DAG, SDValue InChain, SDValue Start,
645 SDValue End, SDValue Flags, SDLoc DL) const;
646
647 std::pair<const TargetRegisterClass *, uint8_t>
648 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override;
649};
650
651namespace RISCVVIntrinsicsTable {
652
653struct RISCVVIntrinsicInfo {
654 unsigned IntrinsicID;
655 uint8_t ScalarOperand;
656 uint8_t VLOperand;
657 bool IsFPIntrinsic;
658 bool hasScalarOperand() const {
659 // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
660 return ScalarOperand != 0xF;
661 }
662 bool hasVLOperand() const {
663 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
664 return VLOperand != 0x1F;
665 }
666};
667
668using namespace RISCV;
669
670#define GET_RISCVVIntrinsicsTable_DECL
671#include "RISCVGenSearchableTables.inc"
672#undef GET_RISCVVIntrinsicsTable_DECL
673
674} // end namespace RISCVVIntrinsicsTable
675
676} // end namespace llvm
677
678#endif
679