1//=- RISCVMachineFunctionInfo.h - RISC-V machine function info ----*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISCV-specific per-machine-function information.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
15
16#include "RISCVSubtarget.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/CodeGen/MIRYamlMapping.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21
22namespace llvm {
23
24class RISCVMachineFunctionInfo;
25
26namespace yaml {
27struct RISCVMachineFunctionInfo final : public yaml::MachineFunctionInfo {
28 int VarArgsFrameIndex;
29 int VarArgsSaveSize;
30
31 RISCVMachineFunctionInfo() = default;
32 RISCVMachineFunctionInfo(const llvm::RISCVMachineFunctionInfo &MFI);
33
34 void mappingImpl(yaml::IO &YamlIO) override;
35 ~RISCVMachineFunctionInfo() override = default;
36};
37
38template <> struct MappingTraits<RISCVMachineFunctionInfo> {
39 static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI) {
40 YamlIO.mapOptional(Key: "varArgsFrameIndex", Val&: MFI.VarArgsFrameIndex);
41 YamlIO.mapOptional(Key: "varArgsSaveSize", Val&: MFI.VarArgsSaveSize);
42 }
43};
44} // end namespace yaml
45
46/// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo
47/// and contains private RISCV-specific information for each MachineFunction.
48class RISCVMachineFunctionInfo : public MachineFunctionInfo {
49private:
50 /// FrameIndex for start of varargs area
51 int VarArgsFrameIndex = 0;
52 /// Size of the save area used for varargs
53 int VarArgsSaveSize = 0;
54 /// FrameIndex used for transferring values between 64-bit FPRs and a pair
55 /// of 32-bit GPRs via the stack.
56 int MoveF64FrameIndex = -1;
57 /// FrameIndex of the spill slot for the scratch register in BranchRelaxation.
58 int BranchRelaxationScratchFrameIndex = -1;
59 /// Size of any opaque stack adjustment due to save/restore libcalls.
60 unsigned LibCallStackSize = 0;
61 /// Size of RVV stack.
62 uint64_t RVVStackSize = 0;
63 /// Alignment of RVV stack.
64 Align RVVStackAlign;
65 /// Padding required to keep RVV stack aligned within the main stack.
66 uint64_t RVVPadding = 0;
67 /// Size of stack frame to save callee saved registers
68 unsigned CalleeSavedStackSize = 0;
69
70 /// Incoming indirect argument pointers saved as virtual registers, keyed by
71 /// formal parameter index. Used for musttail forwarding of indirect args.
72 /// Virtual registers (not SDValues) are used because the SelectionDAG is
73 /// cleared between basic blocks, and musttail calls may be in non-entry
74 /// blocks.
75 DenseMap<unsigned, Register> IncomingIndirectArgs;
76
77 /// Is there any vector argument or return?
78 bool IsVectorCall = false;
79
80 /// Registers that have been sign extended from i32.
81 SmallVector<Register, 8> SExt32Registers;
82
83 /// Size of stack frame for Zcmp PUSH/POP
84 unsigned RVPushStackSize = 0;
85 unsigned RVPushRegs = 0;
86
87 /// Size of any opaque stack adjustment due to QCI Interrupt instructions.
88 unsigned QCIInterruptStackSize = 0;
89
90 /// Store Frame Indexes for Interrupt-Related CSR Spills.
91 SmallVector<int, 2> InterruptCSRFrameIndexes;
92
93 int64_t StackProbeSize = 0;
94
95 /// Does it probe the stack for a dynamic allocation?
96 bool HasDynamicAllocation = false;
97
98 /// Whether the function has cf-protection-branch module flag set.
99 bool CFProtectionBranch = false;
100
101public:
102 RISCVMachineFunctionInfo(const Function &F, const RISCVSubtarget *STI);
103
104 MachineFunctionInfo *
105 clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
106 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
107 const override;
108
109 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
110 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
111
112 unsigned getVarArgsSaveSize() const { return VarArgsSaveSize; }
113 void setVarArgsSaveSize(int Size) { VarArgsSaveSize = Size; }
114
115 int getMoveF64FrameIndex(MachineFunction &MF) {
116 if (MoveF64FrameIndex == -1)
117 MoveF64FrameIndex =
118 MF.getFrameInfo().CreateStackObject(Size: 8, Alignment: Align(8), isSpillSlot: false);
119 return MoveF64FrameIndex;
120 }
121
122 int getBranchRelaxationScratchFrameIndex() const {
123 return BranchRelaxationScratchFrameIndex;
124 }
125 void setBranchRelaxationScratchFrameIndex(int Index) {
126 BranchRelaxationScratchFrameIndex = Index;
127 }
128
129 unsigned getReservedSpillsSize() const {
130 return LibCallStackSize + RVPushStackSize + QCIInterruptStackSize;
131 }
132
133 unsigned getLibCallStackSize() const { return LibCallStackSize; }
134 void setLibCallStackSize(unsigned Size) { LibCallStackSize = Size; }
135
136 bool useSaveRestoreLibCalls(const MachineFunction &MF) const {
137 // We cannot use fixed locations for the callee saved spill slots if the
138 // function uses a varargs save area, or is an interrupt handler.
139 return !isPushable(MF) &&
140 MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
141 VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall() &&
142 !MF.getFunction().hasFnAttribute(Kind: "interrupt");
143 }
144
145 uint64_t getRVVStackSize() const { return RVVStackSize; }
146 void setRVVStackSize(uint64_t Size) { RVVStackSize = Size; }
147
148 Align getRVVStackAlign() const { return RVVStackAlign; }
149 void setRVVStackAlign(Align StackAlign) { RVVStackAlign = StackAlign; }
150
151 uint64_t getRVVPadding() const { return RVVPadding; }
152 void setRVVPadding(uint64_t Padding) { RVVPadding = Padding; }
153
154 unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
155 void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
156
157 void setIncomingIndirectArg(unsigned ArgIndex, Register Reg) {
158 IncomingIndirectArgs[ArgIndex] = Reg;
159 }
160 Register getIncomingIndirectArg(unsigned ArgIndex) const {
161 auto It = IncomingIndirectArgs.find(Val: ArgIndex);
162 assert(It != IncomingIndirectArgs.end() && "No incoming indirect arg");
163 return It->second;
164 }
165
166 enum class ShadowStackKind { None = 0, Hardware, Software };
167
168 ShadowStackKind getShadowStackKind(const MachineFunction &MF) const;
169 bool hasShadowStack(const MachineFunction &MF) const {
170 return getShadowStackKind(MF) != ShadowStackKind::None;
171 }
172
173 enum class PushPopKind { None = 0, StdExtZcmp, VendorXqccmp };
174
175 PushPopKind getPushPopKind(const MachineFunction &MF) const;
176
177 bool isPushable(const MachineFunction &MF) const {
178 return getPushPopKind(MF) != PushPopKind::None;
179 }
180
181 unsigned getRVPushRegs() const { return RVPushRegs; }
182 void setRVPushRegs(unsigned Regs) { RVPushRegs = Regs; }
183
184 unsigned getRVPushStackSize() const { return RVPushStackSize; }
185 void setRVPushStackSize(unsigned Size) { RVPushStackSize = Size; }
186
187 enum class InterruptStackKind {
188 None = 0,
189 QCINest,
190 QCINoNest,
191 SiFiveCLICPreemptible,
192 SiFiveCLICStackSwap,
193 SiFiveCLICPreemptibleStackSwap
194 };
195
196 InterruptStackKind getInterruptStackKind(const MachineFunction &MF) const;
197
198 bool useQCIInterrupt(const MachineFunction &MF) const {
199 InterruptStackKind Kind = getInterruptStackKind(MF);
200 return Kind == InterruptStackKind::QCINest ||
201 Kind == InterruptStackKind::QCINoNest;
202 }
203
204 unsigned getQCIInterruptStackSize() const { return QCIInterruptStackSize; }
205 void setQCIInterruptStackSize(unsigned Size) { QCIInterruptStackSize = Size; }
206
207 bool useSiFiveInterrupt(const MachineFunction &MF) const {
208 InterruptStackKind Kind = getInterruptStackKind(MF);
209 return Kind == InterruptStackKind::SiFiveCLICPreemptible ||
210 Kind == InterruptStackKind::SiFiveCLICStackSwap ||
211 Kind == InterruptStackKind::SiFiveCLICPreemptibleStackSwap;
212 }
213
214 bool isSiFivePreemptibleInterrupt(const MachineFunction &MF) const {
215 InterruptStackKind Kind = getInterruptStackKind(MF);
216 return Kind == InterruptStackKind::SiFiveCLICPreemptible ||
217 Kind == InterruptStackKind::SiFiveCLICPreemptibleStackSwap;
218 }
219
220 bool isSiFiveStackSwapInterrupt(const MachineFunction &MF) const {
221 InterruptStackKind Kind = getInterruptStackKind(MF);
222 return Kind == InterruptStackKind::SiFiveCLICStackSwap ||
223 Kind == InterruptStackKind::SiFiveCLICPreemptibleStackSwap;
224 }
225
226 void pushInterruptCSRFrameIndex(int FI) {
227 InterruptCSRFrameIndexes.push_back(Elt: FI);
228 }
229 int getInterruptCSRFrameIndex(size_t Idx) const {
230 return InterruptCSRFrameIndexes[Idx];
231 }
232
233 // Some Stack Management Variants automatically update FP in a frame-pointer
234 // convention compatible way - which means we don't need to manually update
235 // the FP, but we still need to emit the correct CFI information for
236 // calculating the CFA based on FP.
237 bool hasImplicitFPUpdates(const MachineFunction &MF) const;
238
239 void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI);
240
241 void addSExt32Register(Register Reg);
242 bool isSExt32Register(Register Reg) const;
243
244 bool isVectorCall() const { return IsVectorCall; }
245 void setIsVectorCall() { IsVectorCall = true; }
246
247 bool hasDynamicAllocation() const { return HasDynamicAllocation; }
248 void setDynamicAllocation() { HasDynamicAllocation = true; }
249
250 bool hasCFProtectionBranch() const { return CFProtectionBranch; }
251};
252
253} // end namespace llvm
254
255#endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
256