1//=- RISCVMachineFunctionInfo.h - RISC-V machine function info ----*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISCV-specific per-machine-function information.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
15
16#include "RISCVSubtarget.h"
17#include "llvm/CodeGen/MIRYamlMapping.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20
21namespace llvm {
22
23class RISCVMachineFunctionInfo;
24
25namespace yaml {
26struct RISCVMachineFunctionInfo final : public yaml::MachineFunctionInfo {
27 int VarArgsFrameIndex;
28 int VarArgsSaveSize;
29
30 RISCVMachineFunctionInfo() = default;
31 RISCVMachineFunctionInfo(const llvm::RISCVMachineFunctionInfo &MFI);
32
33 void mappingImpl(yaml::IO &YamlIO) override;
34 ~RISCVMachineFunctionInfo() override = default;
35};
36
37template <> struct MappingTraits<RISCVMachineFunctionInfo> {
38 static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI) {
39 YamlIO.mapOptional(Key: "varArgsFrameIndex", Val&: MFI.VarArgsFrameIndex);
40 YamlIO.mapOptional(Key: "varArgsSaveSize", Val&: MFI.VarArgsSaveSize);
41 }
42};
43} // end namespace yaml
44
45/// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo
46/// and contains private RISCV-specific information for each MachineFunction.
47class RISCVMachineFunctionInfo : public MachineFunctionInfo {
48private:
49 /// FrameIndex for start of varargs area
50 int VarArgsFrameIndex = 0;
51 /// Size of the save area used for varargs
52 int VarArgsSaveSize = 0;
53 /// FrameIndex used for transferring values between 64-bit FPRs and a pair
54 /// of 32-bit GPRs via the stack.
55 int MoveF64FrameIndex = -1;
56 /// FrameIndex of the spill slot for the scratch register in BranchRelaxation.
57 int BranchRelaxationScratchFrameIndex = -1;
58 /// Size of any opaque stack adjustment due to save/restore libcalls.
59 unsigned LibCallStackSize = 0;
60 /// Size of RVV stack.
61 uint64_t RVVStackSize = 0;
62 /// Alignment of RVV stack.
63 Align RVVStackAlign;
64 /// Padding required to keep RVV stack aligned within the main stack.
65 uint64_t RVVPadding = 0;
66 /// Size of stack frame to save callee saved registers
67 unsigned CalleeSavedStackSize = 0;
68
69 /// amount of bytes on stack consumed by the arguments being passed on the
70 /// stack
71 unsigned ArgumentStackSize = 0;
72
73 /// Incoming ByVal arguments
74 SmallVector<SDValue, 8> IncomingByValArgs;
75
76 /// Is there any vector argument or return?
77 bool IsVectorCall = false;
78
79 /// Registers that have been sign extended from i32.
80 SmallVector<Register, 8> SExt32Registers;
81
82 /// Size of stack frame for Zcmp PUSH/POP
83 unsigned RVPushStackSize = 0;
84 unsigned RVPushRegs = 0;
85
86 /// Size of any opaque stack adjustment due to QCI Interrupt instructions.
87 unsigned QCIInterruptStackSize = 0;
88
89 /// Store Frame Indexes for Interrupt-Related CSR Spills.
90 SmallVector<int, 2> InterruptCSRFrameIndexes;
91
92 int64_t StackProbeSize = 0;
93
94 /// Does it probe the stack for a dynamic allocation?
95 bool HasDynamicAllocation = false;
96
97public:
98 RISCVMachineFunctionInfo(const Function &F, const RISCVSubtarget *STI);
99
100 MachineFunctionInfo *
101 clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
102 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
103 const override;
104
105 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
106 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
107
108 unsigned getVarArgsSaveSize() const { return VarArgsSaveSize; }
109 void setVarArgsSaveSize(int Size) { VarArgsSaveSize = Size; }
110
111 int getMoveF64FrameIndex(MachineFunction &MF) {
112 if (MoveF64FrameIndex == -1)
113 MoveF64FrameIndex =
114 MF.getFrameInfo().CreateStackObject(Size: 8, Alignment: Align(8), isSpillSlot: false);
115 return MoveF64FrameIndex;
116 }
117
118 int getBranchRelaxationScratchFrameIndex() const {
119 return BranchRelaxationScratchFrameIndex;
120 }
121 void setBranchRelaxationScratchFrameIndex(int Index) {
122 BranchRelaxationScratchFrameIndex = Index;
123 }
124
125 unsigned getReservedSpillsSize() const {
126 return LibCallStackSize + RVPushStackSize + QCIInterruptStackSize;
127 }
128
129 unsigned getLibCallStackSize() const { return LibCallStackSize; }
130 void setLibCallStackSize(unsigned Size) { LibCallStackSize = Size; }
131
132 bool useSaveRestoreLibCalls(const MachineFunction &MF) const {
133 // We cannot use fixed locations for the callee saved spill slots if the
134 // function uses a varargs save area, or is an interrupt handler.
135 return !isPushable(MF) &&
136 MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
137 VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall() &&
138 !MF.getFunction().hasFnAttribute(Kind: "interrupt");
139 }
140
141 uint64_t getRVVStackSize() const { return RVVStackSize; }
142 void setRVVStackSize(uint64_t Size) { RVVStackSize = Size; }
143
144 Align getRVVStackAlign() const { return RVVStackAlign; }
145 void setRVVStackAlign(Align StackAlign) { RVVStackAlign = StackAlign; }
146
147 uint64_t getRVVPadding() const { return RVVPadding; }
148 void setRVVPadding(uint64_t Padding) { RVVPadding = Padding; }
149
150 unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
151 void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
152
153 unsigned getArgumentStackSize() const { return ArgumentStackSize; }
154 void setArgumentStackSize(unsigned size) { ArgumentStackSize = size; }
155
156 void addIncomingByValArgs(SDValue Val) { IncomingByValArgs.push_back(Elt: Val); }
157 SDValue getIncomingByValArgs(unsigned Idx) { return IncomingByValArgs[Idx]; }
158 unsigned getIncomingByValArgsSize() const { return IncomingByValArgs.size(); }
159
160 enum class PushPopKind { None = 0, StdExtZcmp, VendorXqccmp };
161
162 PushPopKind getPushPopKind(const MachineFunction &MF) const;
163
164 bool isPushable(const MachineFunction &MF) const {
165 return getPushPopKind(MF) != PushPopKind::None;
166 }
167
168 unsigned getRVPushRegs() const { return RVPushRegs; }
169 void setRVPushRegs(unsigned Regs) { RVPushRegs = Regs; }
170
171 unsigned getRVPushStackSize() const { return RVPushStackSize; }
172 void setRVPushStackSize(unsigned Size) { RVPushStackSize = Size; }
173
174 enum class InterruptStackKind {
175 None = 0,
176 QCINest,
177 QCINoNest,
178 SiFiveCLICPreemptible,
179 SiFiveCLICStackSwap,
180 SiFiveCLICPreemptibleStackSwap
181 };
182
183 InterruptStackKind getInterruptStackKind(const MachineFunction &MF) const;
184
185 bool useQCIInterrupt(const MachineFunction &MF) const {
186 InterruptStackKind Kind = getInterruptStackKind(MF);
187 return Kind == InterruptStackKind::QCINest ||
188 Kind == InterruptStackKind::QCINoNest;
189 }
190
191 unsigned getQCIInterruptStackSize() const { return QCIInterruptStackSize; }
192 void setQCIInterruptStackSize(unsigned Size) { QCIInterruptStackSize = Size; }
193
194 bool useSiFiveInterrupt(const MachineFunction &MF) const {
195 InterruptStackKind Kind = getInterruptStackKind(MF);
196 return Kind == InterruptStackKind::SiFiveCLICPreemptible ||
197 Kind == InterruptStackKind::SiFiveCLICStackSwap ||
198 Kind == InterruptStackKind::SiFiveCLICPreemptibleStackSwap;
199 }
200
201 bool isSiFivePreemptibleInterrupt(const MachineFunction &MF) const {
202 InterruptStackKind Kind = getInterruptStackKind(MF);
203 return Kind == InterruptStackKind::SiFiveCLICPreemptible ||
204 Kind == InterruptStackKind::SiFiveCLICPreemptibleStackSwap;
205 }
206
207 bool isSiFiveStackSwapInterrupt(const MachineFunction &MF) const {
208 InterruptStackKind Kind = getInterruptStackKind(MF);
209 return Kind == InterruptStackKind::SiFiveCLICStackSwap ||
210 Kind == InterruptStackKind::SiFiveCLICPreemptibleStackSwap;
211 }
212
213 void pushInterruptCSRFrameIndex(int FI) {
214 InterruptCSRFrameIndexes.push_back(Elt: FI);
215 }
216 int getInterruptCSRFrameIndex(size_t Idx) const {
217 return InterruptCSRFrameIndexes[Idx];
218 }
219
220 // Some Stack Management Variants automatically update FP in a frame-pointer
221 // convention compatible way - which means we don't need to manually update
222 // the FP, but we still need to emit the correct CFI information for
223 // calculating the CFA based on FP.
224 bool hasImplicitFPUpdates(const MachineFunction &MF) const;
225
226 void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI);
227
228 void addSExt32Register(Register Reg);
229 bool isSExt32Register(Register Reg) const;
230
231 bool isVectorCall() const { return IsVectorCall; }
232 void setIsVectorCall() { IsVectorCall = true; }
233
234 bool hasDynamicAllocation() const { return HasDynamicAllocation; }
235 void setDynamicAllocation() { HasDynamicAllocation = true; }
236};
237
238} // end namespace llvm
239
240#endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
241