| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t RISCVMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(2583691323), // AADD |
| 14 | UINT64_C(3120562235), // AADDU |
| 15 | UINT64_C(1617956883), // ABS |
| 16 | UINT64_C(1617956891), // ABSW |
| 17 | UINT64_C(51), // ADD |
| 18 | UINT64_C(2248171547), // ADDD |
| 19 | UINT64_C(19), // ADDI |
| 20 | UINT64_C(27), // ADDIW |
| 21 | UINT64_C(59), // ADDW |
| 22 | UINT64_C(134217787), // ADD_UW |
| 23 | UINT64_C(704643123), // AES32DSI |
| 24 | UINT64_C(771751987), // AES32DSMI |
| 25 | UINT64_C(570425395), // AES32ESI |
| 26 | UINT64_C(637534259), // AES32ESMI |
| 27 | UINT64_C(973078579), // AES64DS |
| 28 | UINT64_C(1040187443), // AES64DSM |
| 29 | UINT64_C(838860851), // AES64ES |
| 30 | UINT64_C(905969715), // AES64ESM |
| 31 | UINT64_C(805310483), // AES64IM |
| 32 | UINT64_C(822087699), // AES64KS1I |
| 33 | UINT64_C(2113929267), // AES64KS2 |
| 34 | UINT64_C(33566779), // AIF_AMOADDG_D |
| 35 | UINT64_C(33562683), // AIF_AMOADDG_W |
| 36 | UINT64_C(12347), // AIF_AMOADDL_D |
| 37 | UINT64_C(8251), // AIF_AMOADDL_W |
| 38 | UINT64_C(1644179515), // AIF_AMOANDG_D |
| 39 | UINT64_C(1644175419), // AIF_AMOANDG_W |
| 40 | UINT64_C(1610625083), // AIF_AMOANDL_D |
| 41 | UINT64_C(1610620987), // AIF_AMOANDL_W |
| 42 | UINT64_C(4060098619), // AIF_AMOCMPSWAPG_D |
| 43 | UINT64_C(4060094523), // AIF_AMOCMPSWAPG_W |
| 44 | UINT64_C(4026544187), // AIF_AMOCMPSWAPL_D |
| 45 | UINT64_C(4026540091), // AIF_AMOCMPSWAPL_W |
| 46 | UINT64_C(2717921339), // AIF_AMOMAXG_D |
| 47 | UINT64_C(2717917243), // AIF_AMOMAXG_W |
| 48 | UINT64_C(2684366907), // AIF_AMOMAXL_D |
| 49 | UINT64_C(2684362811), // AIF_AMOMAXL_W |
| 50 | UINT64_C(3791663163), // AIF_AMOMAXUG_D |
| 51 | UINT64_C(3791659067), // AIF_AMOMAXUG_W |
| 52 | UINT64_C(3758108731), // AIF_AMOMAXUL_D |
| 53 | UINT64_C(3758104635), // AIF_AMOMAXUL_W |
| 54 | UINT64_C(2181050427), // AIF_AMOMING_D |
| 55 | UINT64_C(2181046331), // AIF_AMOMING_W |
| 56 | UINT64_C(2147495995), // AIF_AMOMINL_D |
| 57 | UINT64_C(2147491899), // AIF_AMOMINL_W |
| 58 | UINT64_C(3254792251), // AIF_AMOMINUG_D |
| 59 | UINT64_C(3254788155), // AIF_AMOMINUG_W |
| 60 | UINT64_C(3221237819), // AIF_AMOMINUL_D |
| 61 | UINT64_C(3221233723), // AIF_AMOMINUL_W |
| 62 | UINT64_C(1107308603), // AIF_AMOORG_D |
| 63 | UINT64_C(1107304507), // AIF_AMOORG_W |
| 64 | UINT64_C(1073754171), // AIF_AMOORL_D |
| 65 | UINT64_C(1073750075), // AIF_AMOORL_W |
| 66 | UINT64_C(167784507), // AIF_AMOSWAPG_D |
| 67 | UINT64_C(167780411), // AIF_AMOSWAPG_W |
| 68 | UINT64_C(134230075), // AIF_AMOSWAPL_D |
| 69 | UINT64_C(134225979), // AIF_AMOSWAPL_W |
| 70 | UINT64_C(570437691), // AIF_AMOXORG_D |
| 71 | UINT64_C(570433595), // AIF_AMOXORG_W |
| 72 | UINT64_C(536883259), // AIF_AMOXORL_D |
| 73 | UINT64_C(536879163), // AIF_AMOXORL_W |
| 74 | UINT64_C(2147512379), // AIF_BITMIXB |
| 75 | UINT64_C(2281705595), // AIF_CUBEFACEIDX_PS |
| 76 | UINT64_C(2281701499), // AIF_CUBEFACE_PS |
| 77 | UINT64_C(2281709691), // AIF_CUBESGNSC_PS |
| 78 | UINT64_C(2281713787), // AIF_CUBESGNTC_PS |
| 79 | UINT64_C(67108927), // AIF_FADDI_PI |
| 80 | UINT64_C(100663419), // AIF_FADD_PI |
| 81 | UINT64_C(123), // AIF_FADD_PS |
| 82 | UINT64_C(2248163339), // AIF_FAMOADDG_PI |
| 83 | UINT64_C(100679691), // AIF_FAMOADDL_PI |
| 84 | UINT64_C(2516598795), // AIF_FAMOANDG_PI |
| 85 | UINT64_C(369115147), // AIF_FAMOANDL_PI |
| 86 | UINT64_C(3053469707), // AIF_FAMOMAXG_PI |
| 87 | UINT64_C(2818588683), // AIF_FAMOMAXG_PS |
| 88 | UINT64_C(905986059), // AIF_FAMOMAXL_PI |
| 89 | UINT64_C(671105035), // AIF_FAMOMAXL_PS |
| 90 | UINT64_C(3321905163), // AIF_FAMOMAXUG_PI |
| 91 | UINT64_C(1174421515), // AIF_FAMOMAXUL_PI |
| 92 | UINT64_C(2919251979), // AIF_FAMOMING_PI |
| 93 | UINT64_C(2952806411), // AIF_FAMOMING_PS |
| 94 | UINT64_C(771768331), // AIF_FAMOMINL_PI |
| 95 | UINT64_C(805322763), // AIF_FAMOMINL_PS |
| 96 | UINT64_C(3187687435), // AIF_FAMOMINUG_PI |
| 97 | UINT64_C(1040203787), // AIF_FAMOMINUL_PI |
| 98 | UINT64_C(2650816523), // AIF_FAMOORG_PI |
| 99 | UINT64_C(503332875), // AIF_FAMOORL_PI |
| 100 | UINT64_C(2382381067), // AIF_FAMOSWAPG_PI |
| 101 | UINT64_C(234897419), // AIF_FAMOSWAPL_PI |
| 102 | UINT64_C(2785034251), // AIF_FAMOXORG_PI |
| 103 | UINT64_C(637550603), // AIF_FAMOXORL_PI |
| 104 | UINT64_C(67113023), // AIF_FANDI_PI |
| 105 | UINT64_C(100692091), // AIF_FAND_PI |
| 106 | UINT64_C(95), // AIF_FBCI_PI |
| 107 | UINT64_C(31), // AIF_FBCI_PS |
| 108 | UINT64_C(12299), // AIF_FBCX_PS |
| 109 | UINT64_C(11), // AIF_FBC_PS |
| 110 | UINT64_C(3758100603), // AIF_FCLASS_PS |
| 111 | UINT64_C(119), // AIF_FCMOVM_PS |
| 112 | UINT64_C(67117119), // AIF_FCMOV_PS |
| 113 | UINT64_C(3635413115), // AIF_FCVT_F10_PS |
| 114 | UINT64_C(3632267387), // AIF_FCVT_F11_PS |
| 115 | UINT64_C(3633315963), // AIF_FCVT_F16_PS |
| 116 | UINT64_C(3498049659), // AIF_FCVT_PS_F10 |
| 117 | UINT64_C(3499098235), // AIF_FCVT_PS_F11 |
| 118 | UINT64_C(3500146811), // AIF_FCVT_PS_F16 |
| 119 | UINT64_C(3489661051), // AIF_FCVT_PS_PW |
| 120 | UINT64_C(3490709627), // AIF_FCVT_PS_PWU |
| 121 | UINT64_C(3491758203), // AIF_FCVT_PS_RAST |
| 122 | UINT64_C(3515875451), // AIF_FCVT_PS_SN16 |
| 123 | UINT64_C(3517972603), // AIF_FCVT_PS_SN8 |
| 124 | UINT64_C(3508535419), // AIF_FCVT_PS_UN10 |
| 125 | UINT64_C(3507486843), // AIF_FCVT_PS_UN16 |
| 126 | UINT64_C(3513778299), // AIF_FCVT_PS_UN2 |
| 127 | UINT64_C(3506438267), // AIF_FCVT_PS_UN24 |
| 128 | UINT64_C(3509583995), // AIF_FCVT_PS_UN8 |
| 129 | UINT64_C(3222274171), // AIF_FCVT_PWU_PS |
| 130 | UINT64_C(3221225595), // AIF_FCVT_PW_PS |
| 131 | UINT64_C(3223322747), // AIF_FCVT_RAST_PS |
| 132 | UINT64_C(3650093179), // AIF_FCVT_SN16_PS |
| 133 | UINT64_C(3652190331), // AIF_FCVT_SN8_PS |
| 134 | UINT64_C(3642753147), // AIF_FCVT_UN10_PS |
| 135 | UINT64_C(3641704571), // AIF_FCVT_UN16_PS |
| 136 | UINT64_C(3640655995), // AIF_FCVT_UN24_PS |
| 137 | UINT64_C(3647996027), // AIF_FCVT_UN2_PS |
| 138 | UINT64_C(3643801723), // AIF_FCVT_UN8_PS |
| 139 | UINT64_C(503320699), // AIF_FDIVU_PI |
| 140 | UINT64_C(503316603), // AIF_FDIV_PI |
| 141 | UINT64_C(402653307), // AIF_FDIV_PS |
| 142 | UINT64_C(2684379259), // AIF_FEQM_PS |
| 143 | UINT64_C(2785026171), // AIF_FEQ_PI |
| 144 | UINT64_C(2684362875), // AIF_FEQ_PS |
| 145 | UINT64_C(1480589435), // AIF_FEXP_PS |
| 146 | UINT64_C(1478492283), // AIF_FFRC_PS |
| 147 | UINT64_C(134221835), // AIF_FG32B_PS |
| 148 | UINT64_C(268439563), // AIF_FG32H_PS |
| 149 | UINT64_C(536875019), // AIF_FG32W_PS |
| 150 | UINT64_C(2181066763), // AIF_FGBG_PS |
| 151 | UINT64_C(2147512331), // AIF_FGBL_PS |
| 152 | UINT64_C(1207963659), // AIF_FGB_PS |
| 153 | UINT64_C(2315284491), // AIF_FGHG_PS |
| 154 | UINT64_C(2281730059), // AIF_FGHL_PS |
| 155 | UINT64_C(1342181387), // AIF_FGH_PS |
| 156 | UINT64_C(2449502219), // AIF_FGWG_PS |
| 157 | UINT64_C(2415947787), // AIF_FGWL_PS |
| 158 | UINT64_C(1610616843), // AIF_FGW_PS |
| 159 | UINT64_C(2684371067), // AIF_FLEM_PS |
| 160 | UINT64_C(2785017979), // AIF_FLE_PI |
| 161 | UINT64_C(2684354683), // AIF_FLE_PS |
| 162 | UINT64_C(1479540859), // AIF_FLOG_PS |
| 163 | UINT64_C(20487), // AIF_FLQ2 |
| 164 | UINT64_C(1040187515), // AIF_FLTM_PI |
| 165 | UINT64_C(2684375163), // AIF_FLTM_PS |
| 166 | UINT64_C(2785030267), // AIF_FLTU_PI |
| 167 | UINT64_C(2785022075), // AIF_FLT_PI |
| 168 | UINT64_C(2684358779), // AIF_FLT_PS |
| 169 | UINT64_C(302018571), // AIF_FLWG_PS |
| 170 | UINT64_C(268464139), // AIF_FLWL_PS |
| 171 | UINT64_C(8203), // AIF_FLW_PS |
| 172 | UINT64_C(91), // AIF_FMADD_PS |
| 173 | UINT64_C(771764347), // AIF_FMAXU_PI |
| 174 | UINT64_C(771756155), // AIF_FMAX_PI |
| 175 | UINT64_C(671092859), // AIF_FMAX_PS |
| 176 | UINT64_C(771760251), // AIF_FMINU_PI |
| 177 | UINT64_C(771752059), // AIF_FMIN_PI |
| 178 | UINT64_C(671088763), // AIF_FMIN_PS |
| 179 | UINT64_C(33554523), // AIF_FMSUB_PS |
| 180 | UINT64_C(369107067), // AIF_FMULHU_PI |
| 181 | UINT64_C(369102971), // AIF_FMULH_PI |
| 182 | UINT64_C(369098875), // AIF_FMUL_PI |
| 183 | UINT64_C(268435579), // AIF_FMUL_PS |
| 184 | UINT64_C(3758104699), // AIF_FMVS_X_PS |
| 185 | UINT64_C(3758096507), // AIF_FMVZ_X_PS |
| 186 | UINT64_C(100663387), // AIF_FNMADD_PS |
| 187 | UINT64_C(67108955), // AIF_FNMSUB_PS |
| 188 | UINT64_C(100671611), // AIF_FNOT_PI |
| 189 | UINT64_C(100687995), // AIF_FOR_PI |
| 190 | UINT64_C(637534331), // AIF_FPACKREPB_PI |
| 191 | UINT64_C(637538427), // AIF_FPACKREPH_PI |
| 192 | UINT64_C(805306491), // AIF_FRCP_FIX_RAST |
| 193 | UINT64_C(1483735163), // AIF_FRCP_PS |
| 194 | UINT64_C(503328891), // AIF_FREMU_PI |
| 195 | UINT64_C(503324795), // AIF_FREM_PI |
| 196 | UINT64_C(1477443707), // AIF_FROUND_PS |
| 197 | UINT64_C(1484783739), // AIF_FRSQ_PS |
| 198 | UINT64_C(100675707), // AIF_FSAT8_PI |
| 199 | UINT64_C(101724283), // AIF_FSATU8_PI |
| 200 | UINT64_C(2281705483), // AIF_FSC32B_PS |
| 201 | UINT64_C(2415923211), // AIF_FSC32H_PS |
| 202 | UINT64_C(2684358667), // AIF_FSC32W_PS |
| 203 | UINT64_C(3254808587), // AIF_FSCBG_PS |
| 204 | UINT64_C(3221254155), // AIF_FSCBL_PS |
| 205 | UINT64_C(3355447307), // AIF_FSCB_PS |
| 206 | UINT64_C(3389026315), // AIF_FSCHG_PS |
| 207 | UINT64_C(3355471883), // AIF_FSCHL_PS |
| 208 | UINT64_C(3489665035), // AIF_FSCH_PS |
| 209 | UINT64_C(3523244043), // AIF_FSCWG_PS |
| 210 | UINT64_C(3489689611), // AIF_FSCWL_PS |
| 211 | UINT64_C(3758100491), // AIF_FSCW_PS |
| 212 | UINT64_C(2785034363), // AIF_FSETM_PI |
| 213 | UINT64_C(536875131), // AIF_FSGNJN_PS |
| 214 | UINT64_C(536879227), // AIF_FSGNJX_PS |
| 215 | UINT64_C(536871035), // AIF_FSGNJ_PS |
| 216 | UINT64_C(1482686587), // AIF_FSIN_PS |
| 217 | UINT64_C(1308627067), // AIF_FSLLI_PI |
| 218 | UINT64_C(100667515), // AIF_FSLL_PI |
| 219 | UINT64_C(20519), // AIF_FSQ2 |
| 220 | UINT64_C(1476395131), // AIF_FSQRT_PS |
| 221 | UINT64_C(1308651643), // AIF_FSRAI_PI |
| 222 | UINT64_C(234901627), // AIF_FSRA_PI |
| 223 | UINT64_C(1308643451), // AIF_FSRLI_PI |
| 224 | UINT64_C(100683899), // AIF_FSRL_PI |
| 225 | UINT64_C(234881147), // AIF_FSUB_PI |
| 226 | UINT64_C(134217851), // AIF_FSUB_PS |
| 227 | UINT64_C(1375760395), // AIF_FSWG_PS |
| 228 | UINT64_C(3858759803), // AIF_FSWIZZ_PS |
| 229 | UINT64_C(1342205963), // AIF_FSWL_PS |
| 230 | UINT64_C(24587), // AIF_FSW_PS |
| 231 | UINT64_C(100679803), // AIF_FXOR_PI |
| 232 | UINT64_C(1711304827), // AIF_MASKAND |
| 233 | UINT64_C(1711284347), // AIF_MASKNOT |
| 234 | UINT64_C(1711300731), // AIF_MASKOR |
| 235 | UINT64_C(1375731835), // AIF_MASKPOPC |
| 236 | UINT64_C(1409286267), // AIF_MASKPOPCZ |
| 237 | UINT64_C(1577058427), // AIF_MASKPOPC_ET_RAST |
| 238 | UINT64_C(1711292539), // AIF_MASKXOR |
| 239 | UINT64_C(3590328443), // AIF_MOVA_M_X |
| 240 | UINT64_C(3590324347), // AIF_MOVA_X_M |
| 241 | UINT64_C(1442840699), // AIF_MOV_M_X |
| 242 | UINT64_C(2147508283), // AIF_PACKB |
| 243 | UINT64_C(302002235), // AIF_SBG |
| 244 | UINT64_C(268447803), // AIF_SBL |
| 245 | UINT64_C(436219963), // AIF_SHG |
| 246 | UINT64_C(402665531), // AIF_SHL |
| 247 | UINT64_C(47), // AMOADD_B |
| 248 | UINT64_C(67108911), // AMOADD_B_AQ |
| 249 | UINT64_C(100663343), // AMOADD_B_AQRL |
| 250 | UINT64_C(33554479), // AMOADD_B_RL |
| 251 | UINT64_C(12335), // AMOADD_D |
| 252 | UINT64_C(67121199), // AMOADD_D_AQ |
| 253 | UINT64_C(100675631), // AMOADD_D_AQRL |
| 254 | UINT64_C(33566767), // AMOADD_D_RL |
| 255 | UINT64_C(4143), // AMOADD_H |
| 256 | UINT64_C(67113007), // AMOADD_H_AQ |
| 257 | UINT64_C(100667439), // AMOADD_H_AQRL |
| 258 | UINT64_C(33558575), // AMOADD_H_RL |
| 259 | UINT64_C(8239), // AMOADD_W |
| 260 | UINT64_C(67117103), // AMOADD_W_AQ |
| 261 | UINT64_C(100671535), // AMOADD_W_AQRL |
| 262 | UINT64_C(33562671), // AMOADD_W_RL |
| 263 | UINT64_C(1610612783), // AMOAND_B |
| 264 | UINT64_C(1677721647), // AMOAND_B_AQ |
| 265 | UINT64_C(1711276079), // AMOAND_B_AQRL |
| 266 | UINT64_C(1644167215), // AMOAND_B_RL |
| 267 | UINT64_C(1610625071), // AMOAND_D |
| 268 | UINT64_C(1677733935), // AMOAND_D_AQ |
| 269 | UINT64_C(1711288367), // AMOAND_D_AQRL |
| 270 | UINT64_C(1644179503), // AMOAND_D_RL |
| 271 | UINT64_C(1610616879), // AMOAND_H |
| 272 | UINT64_C(1677725743), // AMOAND_H_AQ |
| 273 | UINT64_C(1711280175), // AMOAND_H_AQRL |
| 274 | UINT64_C(1644171311), // AMOAND_H_RL |
| 275 | UINT64_C(1610620975), // AMOAND_W |
| 276 | UINT64_C(1677729839), // AMOAND_W_AQ |
| 277 | UINT64_C(1711284271), // AMOAND_W_AQRL |
| 278 | UINT64_C(1644175407), // AMOAND_W_RL |
| 279 | UINT64_C(671088687), // AMOCAS_B |
| 280 | UINT64_C(738197551), // AMOCAS_B_AQ |
| 281 | UINT64_C(771751983), // AMOCAS_B_AQRL |
| 282 | UINT64_C(704643119), // AMOCAS_B_RL |
| 283 | UINT64_C(671100975), // AMOCAS_D_RV32 |
| 284 | UINT64_C(738209839), // AMOCAS_D_RV32_AQ |
| 285 | UINT64_C(771764271), // AMOCAS_D_RV32_AQRL |
| 286 | UINT64_C(704655407), // AMOCAS_D_RV32_RL |
| 287 | UINT64_C(671100975), // AMOCAS_D_RV64 |
| 288 | UINT64_C(738209839), // AMOCAS_D_RV64_AQ |
| 289 | UINT64_C(771764271), // AMOCAS_D_RV64_AQRL |
| 290 | UINT64_C(704655407), // AMOCAS_D_RV64_RL |
| 291 | UINT64_C(671092783), // AMOCAS_H |
| 292 | UINT64_C(738201647), // AMOCAS_H_AQ |
| 293 | UINT64_C(771756079), // AMOCAS_H_AQRL |
| 294 | UINT64_C(704647215), // AMOCAS_H_RL |
| 295 | UINT64_C(671105071), // AMOCAS_Q |
| 296 | UINT64_C(738213935), // AMOCAS_Q_AQ |
| 297 | UINT64_C(771768367), // AMOCAS_Q_AQRL |
| 298 | UINT64_C(704659503), // AMOCAS_Q_RL |
| 299 | UINT64_C(671096879), // AMOCAS_W |
| 300 | UINT64_C(738205743), // AMOCAS_W_AQ |
| 301 | UINT64_C(771760175), // AMOCAS_W_AQRL |
| 302 | UINT64_C(704651311), // AMOCAS_W_RL |
| 303 | UINT64_C(3758096431), // AMOMAXU_B |
| 304 | UINT64_C(3825205295), // AMOMAXU_B_AQ |
| 305 | UINT64_C(3858759727), // AMOMAXU_B_AQRL |
| 306 | UINT64_C(3791650863), // AMOMAXU_B_RL |
| 307 | UINT64_C(3758108719), // AMOMAXU_D |
| 308 | UINT64_C(3825217583), // AMOMAXU_D_AQ |
| 309 | UINT64_C(3858772015), // AMOMAXU_D_AQRL |
| 310 | UINT64_C(3791663151), // AMOMAXU_D_RL |
| 311 | UINT64_C(3758100527), // AMOMAXU_H |
| 312 | UINT64_C(3825209391), // AMOMAXU_H_AQ |
| 313 | UINT64_C(3858763823), // AMOMAXU_H_AQRL |
| 314 | UINT64_C(3791654959), // AMOMAXU_H_RL |
| 315 | UINT64_C(3758104623), // AMOMAXU_W |
| 316 | UINT64_C(3825213487), // AMOMAXU_W_AQ |
| 317 | UINT64_C(3858767919), // AMOMAXU_W_AQRL |
| 318 | UINT64_C(3791659055), // AMOMAXU_W_RL |
| 319 | UINT64_C(2684354607), // AMOMAX_B |
| 320 | UINT64_C(2751463471), // AMOMAX_B_AQ |
| 321 | UINT64_C(2785017903), // AMOMAX_B_AQRL |
| 322 | UINT64_C(2717909039), // AMOMAX_B_RL |
| 323 | UINT64_C(2684366895), // AMOMAX_D |
| 324 | UINT64_C(2751475759), // AMOMAX_D_AQ |
| 325 | UINT64_C(2785030191), // AMOMAX_D_AQRL |
| 326 | UINT64_C(2717921327), // AMOMAX_D_RL |
| 327 | UINT64_C(2684358703), // AMOMAX_H |
| 328 | UINT64_C(2751467567), // AMOMAX_H_AQ |
| 329 | UINT64_C(2785021999), // AMOMAX_H_AQRL |
| 330 | UINT64_C(2717913135), // AMOMAX_H_RL |
| 331 | UINT64_C(2684362799), // AMOMAX_W |
| 332 | UINT64_C(2751471663), // AMOMAX_W_AQ |
| 333 | UINT64_C(2785026095), // AMOMAX_W_AQRL |
| 334 | UINT64_C(2717917231), // AMOMAX_W_RL |
| 335 | UINT64_C(3221225519), // AMOMINU_B |
| 336 | UINT64_C(3288334383), // AMOMINU_B_AQ |
| 337 | UINT64_C(3321888815), // AMOMINU_B_AQRL |
| 338 | UINT64_C(3254779951), // AMOMINU_B_RL |
| 339 | UINT64_C(3221237807), // AMOMINU_D |
| 340 | UINT64_C(3288346671), // AMOMINU_D_AQ |
| 341 | UINT64_C(3321901103), // AMOMINU_D_AQRL |
| 342 | UINT64_C(3254792239), // AMOMINU_D_RL |
| 343 | UINT64_C(3221229615), // AMOMINU_H |
| 344 | UINT64_C(3288338479), // AMOMINU_H_AQ |
| 345 | UINT64_C(3321892911), // AMOMINU_H_AQRL |
| 346 | UINT64_C(3254784047), // AMOMINU_H_RL |
| 347 | UINT64_C(3221233711), // AMOMINU_W |
| 348 | UINT64_C(3288342575), // AMOMINU_W_AQ |
| 349 | UINT64_C(3321897007), // AMOMINU_W_AQRL |
| 350 | UINT64_C(3254788143), // AMOMINU_W_RL |
| 351 | UINT64_C(2147483695), // AMOMIN_B |
| 352 | UINT64_C(2214592559), // AMOMIN_B_AQ |
| 353 | UINT64_C(2248146991), // AMOMIN_B_AQRL |
| 354 | UINT64_C(2181038127), // AMOMIN_B_RL |
| 355 | UINT64_C(2147495983), // AMOMIN_D |
| 356 | UINT64_C(2214604847), // AMOMIN_D_AQ |
| 357 | UINT64_C(2248159279), // AMOMIN_D_AQRL |
| 358 | UINT64_C(2181050415), // AMOMIN_D_RL |
| 359 | UINT64_C(2147487791), // AMOMIN_H |
| 360 | UINT64_C(2214596655), // AMOMIN_H_AQ |
| 361 | UINT64_C(2248151087), // AMOMIN_H_AQRL |
| 362 | UINT64_C(2181042223), // AMOMIN_H_RL |
| 363 | UINT64_C(2147491887), // AMOMIN_W |
| 364 | UINT64_C(2214600751), // AMOMIN_W_AQ |
| 365 | UINT64_C(2248155183), // AMOMIN_W_AQRL |
| 366 | UINT64_C(2181046319), // AMOMIN_W_RL |
| 367 | UINT64_C(1073741871), // AMOOR_B |
| 368 | UINT64_C(1140850735), // AMOOR_B_AQ |
| 369 | UINT64_C(1174405167), // AMOOR_B_AQRL |
| 370 | UINT64_C(1107296303), // AMOOR_B_RL |
| 371 | UINT64_C(1073754159), // AMOOR_D |
| 372 | UINT64_C(1140863023), // AMOOR_D_AQ |
| 373 | UINT64_C(1174417455), // AMOOR_D_AQRL |
| 374 | UINT64_C(1107308591), // AMOOR_D_RL |
| 375 | UINT64_C(1073745967), // AMOOR_H |
| 376 | UINT64_C(1140854831), // AMOOR_H_AQ |
| 377 | UINT64_C(1174409263), // AMOOR_H_AQRL |
| 378 | UINT64_C(1107300399), // AMOOR_H_RL |
| 379 | UINT64_C(1073750063), // AMOOR_W |
| 380 | UINT64_C(1140858927), // AMOOR_W_AQ |
| 381 | UINT64_C(1174413359), // AMOOR_W_AQRL |
| 382 | UINT64_C(1107304495), // AMOOR_W_RL |
| 383 | UINT64_C(134217775), // AMOSWAP_B |
| 384 | UINT64_C(201326639), // AMOSWAP_B_AQ |
| 385 | UINT64_C(234881071), // AMOSWAP_B_AQRL |
| 386 | UINT64_C(167772207), // AMOSWAP_B_RL |
| 387 | UINT64_C(134230063), // AMOSWAP_D |
| 388 | UINT64_C(201338927), // AMOSWAP_D_AQ |
| 389 | UINT64_C(234893359), // AMOSWAP_D_AQRL |
| 390 | UINT64_C(167784495), // AMOSWAP_D_RL |
| 391 | UINT64_C(134221871), // AMOSWAP_H |
| 392 | UINT64_C(201330735), // AMOSWAP_H_AQ |
| 393 | UINT64_C(234885167), // AMOSWAP_H_AQRL |
| 394 | UINT64_C(167776303), // AMOSWAP_H_RL |
| 395 | UINT64_C(134225967), // AMOSWAP_W |
| 396 | UINT64_C(201334831), // AMOSWAP_W_AQ |
| 397 | UINT64_C(234889263), // AMOSWAP_W_AQRL |
| 398 | UINT64_C(167780399), // AMOSWAP_W_RL |
| 399 | UINT64_C(536870959), // AMOXOR_B |
| 400 | UINT64_C(603979823), // AMOXOR_B_AQ |
| 401 | UINT64_C(637534255), // AMOXOR_B_AQRL |
| 402 | UINT64_C(570425391), // AMOXOR_B_RL |
| 403 | UINT64_C(536883247), // AMOXOR_D |
| 404 | UINT64_C(603992111), // AMOXOR_D_AQ |
| 405 | UINT64_C(637546543), // AMOXOR_D_AQRL |
| 406 | UINT64_C(570437679), // AMOXOR_D_RL |
| 407 | UINT64_C(536875055), // AMOXOR_H |
| 408 | UINT64_C(603983919), // AMOXOR_H_AQ |
| 409 | UINT64_C(637538351), // AMOXOR_H_AQRL |
| 410 | UINT64_C(570429487), // AMOXOR_H_RL |
| 411 | UINT64_C(536879151), // AMOXOR_W |
| 412 | UINT64_C(603988015), // AMOXOR_W_AQ |
| 413 | UINT64_C(637542447), // AMOXOR_W_AQRL |
| 414 | UINT64_C(570433583), // AMOXOR_W_RL |
| 415 | UINT64_C(28723), // AND |
| 416 | UINT64_C(28691), // ANDI |
| 417 | UINT64_C(1073770547), // ANDN |
| 418 | UINT64_C(3657433147), // ASUB |
| 419 | UINT64_C(4194304059), // ASUBU |
| 420 | UINT64_C(23), // AUIPC |
| 421 | UINT64_C(1207963699), // BCLR |
| 422 | UINT64_C(1207963667), // BCLRI |
| 423 | UINT64_C(99), // BEQ |
| 424 | UINT64_C(8291), // BEQI |
| 425 | UINT64_C(1207980083), // BEXT |
| 426 | UINT64_C(1207980051), // BEXTI |
| 427 | UINT64_C(20579), // BGE |
| 428 | UINT64_C(28771), // BGEU |
| 429 | UINT64_C(1744834611), // BINV |
| 430 | UINT64_C(1744834579), // BINVI |
| 431 | UINT64_C(16483), // BLT |
| 432 | UINT64_C(24675), // BLTU |
| 433 | UINT64_C(4195), // BNE |
| 434 | UINT64_C(12387), // BNEI |
| 435 | UINT64_C(1752190995), // BREV8 |
| 436 | UINT64_C(671092787), // BSET |
| 437 | UINT64_C(671092755), // BSETI |
| 438 | UINT64_C(1056783), // CBO_CLEAN |
| 439 | UINT64_C(2105359), // CBO_FLUSH |
| 440 | UINT64_C(8207), // CBO_INVAL |
| 441 | UINT64_C(4202511), // CBO_ZERO |
| 442 | UINT64_C(167776307), // CLMUL |
| 443 | UINT64_C(167784499), // CLMULH |
| 444 | UINT64_C(167780403), // CLMULR |
| 445 | UINT64_C(1613762579), // CLS |
| 446 | UINT64_C(1613762587), // CLSW |
| 447 | UINT64_C(1610616851), // CLZ |
| 448 | UINT64_C(1610616859), // CLZW |
| 449 | UINT64_C(40962), // CM_JALT |
| 450 | UINT64_C(40962), // CM_JT |
| 451 | UINT64_C(44130), // CM_MVA01S |
| 452 | UINT64_C(44066), // CM_MVSA01 |
| 453 | UINT64_C(47618), // CM_POP |
| 454 | UINT64_C(48642), // CM_POPRET |
| 455 | UINT64_C(48130), // CM_POPRETZ |
| 456 | UINT64_C(47106), // CM_PUSH |
| 457 | UINT64_C(1612714003), // CPOP |
| 458 | UINT64_C(1612714011), // CPOPW |
| 459 | UINT64_C(12403), // CSRRC |
| 460 | UINT64_C(28787), // CSRRCI |
| 461 | UINT64_C(8307), // CSRRS |
| 462 | UINT64_C(24691), // CSRRSI |
| 463 | UINT64_C(4211), // CSRRW |
| 464 | UINT64_C(20595), // CSRRWI |
| 465 | UINT64_C(1611665427), // CTZ |
| 466 | UINT64_C(1611665435), // CTZW |
| 467 | UINT64_C(1342189611), // CV_ABS |
| 468 | UINT64_C(1879052411), // CV_ABS_B |
| 469 | UINT64_C(1879048315), // CV_ABS_H |
| 470 | UINT64_C(8283), // CV_ADDN |
| 471 | UINT64_C(2147495979), // CV_ADDNR |
| 472 | UINT64_C(2147491931), // CV_ADDRN |
| 473 | UINT64_C(2214604843), // CV_ADDRNR |
| 474 | UINT64_C(1073750107), // CV_ADDUN |
| 475 | UINT64_C(2181050411), // CV_ADDUNR |
| 476 | UINT64_C(3221233755), // CV_ADDURN |
| 477 | UINT64_C(2248159275), // CV_ADDURNR |
| 478 | UINT64_C(4219), // CV_ADD_B |
| 479 | UINT64_C(1811947643), // CV_ADD_DIV2 |
| 480 | UINT64_C(1811955835), // CV_ADD_DIV4 |
| 481 | UINT64_C(1811964027), // CV_ADD_DIV8 |
| 482 | UINT64_C(123), // CV_ADD_H |
| 483 | UINT64_C(28795), // CV_ADD_SCI_B |
| 484 | UINT64_C(24699), // CV_ADD_SCI_H |
| 485 | UINT64_C(20603), // CV_ADD_SC_B |
| 486 | UINT64_C(16507), // CV_ADD_SC_H |
| 487 | UINT64_C(1744834683), // CV_AND_B |
| 488 | UINT64_C(1744830587), // CV_AND_H |
| 489 | UINT64_C(1744859259), // CV_AND_SCI_B |
| 490 | UINT64_C(1744855163), // CV_AND_SCI_H |
| 491 | UINT64_C(1744851067), // CV_AND_SC_B |
| 492 | UINT64_C(1744846971), // CV_AND_SC_H |
| 493 | UINT64_C(402657403), // CV_AVGU_B |
| 494 | UINT64_C(402653307), // CV_AVGU_H |
| 495 | UINT64_C(402681979), // CV_AVGU_SCI_B |
| 496 | UINT64_C(402677883), // CV_AVGU_SCI_H |
| 497 | UINT64_C(402673787), // CV_AVGU_SC_B |
| 498 | UINT64_C(402669691), // CV_AVGU_SC_H |
| 499 | UINT64_C(268439675), // CV_AVG_B |
| 500 | UINT64_C(268435579), // CV_AVG_H |
| 501 | UINT64_C(268464251), // CV_AVG_SCI_B |
| 502 | UINT64_C(268460155), // CV_AVG_SCI_H |
| 503 | UINT64_C(268456059), // CV_AVG_SC_B |
| 504 | UINT64_C(268451963), // CV_AVG_SC_H |
| 505 | UINT64_C(4187), // CV_BCLR |
| 506 | UINT64_C(939536427), // CV_BCLRR |
| 507 | UINT64_C(24587), // CV_BEQIMM |
| 508 | UINT64_C(3221229659), // CV_BITREV |
| 509 | UINT64_C(28683), // CV_BNEIMM |
| 510 | UINT64_C(1073746011), // CV_BSET |
| 511 | UINT64_C(973090859), // CV_BSETR |
| 512 | UINT64_C(1174417451), // CV_CLB |
| 513 | UINT64_C(1879060523), // CV_CLIP |
| 514 | UINT64_C(1946169387), // CV_CLIPR |
| 515 | UINT64_C(1912614955), // CV_CLIPU |
| 516 | UINT64_C(1979723819), // CV_CLIPUR |
| 517 | UINT64_C(67113083), // CV_CMPEQ_B |
| 518 | UINT64_C(67108987), // CV_CMPEQ_H |
| 519 | UINT64_C(67137659), // CV_CMPEQ_SCI_B |
| 520 | UINT64_C(67133563), // CV_CMPEQ_SCI_H |
| 521 | UINT64_C(67129467), // CV_CMPEQ_SC_B |
| 522 | UINT64_C(67125371), // CV_CMPEQ_SC_H |
| 523 | UINT64_C(1006637179), // CV_CMPGEU_B |
| 524 | UINT64_C(1006633083), // CV_CMPGEU_H |
| 525 | UINT64_C(1006661755), // CV_CMPGEU_SCI_B |
| 526 | UINT64_C(1006657659), // CV_CMPGEU_SCI_H |
| 527 | UINT64_C(1006653563), // CV_CMPGEU_SC_B |
| 528 | UINT64_C(1006649467), // CV_CMPGEU_SC_H |
| 529 | UINT64_C(469766267), // CV_CMPGE_B |
| 530 | UINT64_C(469762171), // CV_CMPGE_H |
| 531 | UINT64_C(469790843), // CV_CMPGE_SCI_B |
| 532 | UINT64_C(469786747), // CV_CMPGE_SCI_H |
| 533 | UINT64_C(469782651), // CV_CMPGE_SC_B |
| 534 | UINT64_C(469778555), // CV_CMPGE_SC_H |
| 535 | UINT64_C(872419451), // CV_CMPGTU_B |
| 536 | UINT64_C(872415355), // CV_CMPGTU_H |
| 537 | UINT64_C(872444027), // CV_CMPGTU_SCI_B |
| 538 | UINT64_C(872439931), // CV_CMPGTU_SCI_H |
| 539 | UINT64_C(872435835), // CV_CMPGTU_SC_B |
| 540 | UINT64_C(872431739), // CV_CMPGTU_SC_H |
| 541 | UINT64_C(335548539), // CV_CMPGT_B |
| 542 | UINT64_C(335544443), // CV_CMPGT_H |
| 543 | UINT64_C(335573115), // CV_CMPGT_SCI_B |
| 544 | UINT64_C(335569019), // CV_CMPGT_SCI_H |
| 545 | UINT64_C(335564923), // CV_CMPGT_SC_B |
| 546 | UINT64_C(335560827), // CV_CMPGT_SC_H |
| 547 | UINT64_C(1275072635), // CV_CMPLEU_B |
| 548 | UINT64_C(1275068539), // CV_CMPLEU_H |
| 549 | UINT64_C(1275097211), // CV_CMPLEU_SCI_B |
| 550 | UINT64_C(1275093115), // CV_CMPLEU_SCI_H |
| 551 | UINT64_C(1275089019), // CV_CMPLEU_SC_B |
| 552 | UINT64_C(1275084923), // CV_CMPLEU_SC_H |
| 553 | UINT64_C(738201723), // CV_CMPLE_B |
| 554 | UINT64_C(738197627), // CV_CMPLE_H |
| 555 | UINT64_C(738226299), // CV_CMPLE_SCI_B |
| 556 | UINT64_C(738222203), // CV_CMPLE_SCI_H |
| 557 | UINT64_C(738218107), // CV_CMPLE_SC_B |
| 558 | UINT64_C(738214011), // CV_CMPLE_SC_H |
| 559 | UINT64_C(1140854907), // CV_CMPLTU_B |
| 560 | UINT64_C(1140850811), // CV_CMPLTU_H |
| 561 | UINT64_C(1140879483), // CV_CMPLTU_SCI_B |
| 562 | UINT64_C(1140875387), // CV_CMPLTU_SCI_H |
| 563 | UINT64_C(1140871291), // CV_CMPLTU_SC_B |
| 564 | UINT64_C(1140867195), // CV_CMPLTU_SC_H |
| 565 | UINT64_C(603983995), // CV_CMPLT_B |
| 566 | UINT64_C(603979899), // CV_CMPLT_H |
| 567 | UINT64_C(604008571), // CV_CMPLT_SCI_B |
| 568 | UINT64_C(604004475), // CV_CMPLT_SCI_H |
| 569 | UINT64_C(604000379), // CV_CMPLT_SC_B |
| 570 | UINT64_C(603996283), // CV_CMPLT_SC_H |
| 571 | UINT64_C(201330811), // CV_CMPNE_B |
| 572 | UINT64_C(201326715), // CV_CMPNE_H |
| 573 | UINT64_C(201355387), // CV_CMPNE_SCI_B |
| 574 | UINT64_C(201351291), // CV_CMPNE_SCI_H |
| 575 | UINT64_C(201347195), // CV_CMPNE_SC_B |
| 576 | UINT64_C(201343099), // CV_CMPNE_SC_H |
| 577 | UINT64_C(1207971883), // CV_CNT |
| 578 | UINT64_C(1543503995), // CV_CPLXCONJ |
| 579 | UINT64_C(1442840699), // CV_CPLXMUL_I |
| 580 | UINT64_C(1442848891), // CV_CPLXMUL_I_DIV2 |
| 581 | UINT64_C(1442857083), // CV_CPLXMUL_I_DIV4 |
| 582 | UINT64_C(1442865275), // CV_CPLXMUL_I_DIV8 |
| 583 | UINT64_C(1409286267), // CV_CPLXMUL_R |
| 584 | UINT64_C(1409294459), // CV_CPLXMUL_R_DIV2 |
| 585 | UINT64_C(1409302651), // CV_CPLXMUL_R_DIV4 |
| 586 | UINT64_C(1409310843), // CV_CPLXMUL_R_DIV8 |
| 587 | UINT64_C(2415923323), // CV_DOTSP_B |
| 588 | UINT64_C(2415919227), // CV_DOTSP_H |
| 589 | UINT64_C(2415947899), // CV_DOTSP_SCI_B |
| 590 | UINT64_C(2415943803), // CV_DOTSP_SCI_H |
| 591 | UINT64_C(2415939707), // CV_DOTSP_SC_B |
| 592 | UINT64_C(2415935611), // CV_DOTSP_SC_H |
| 593 | UINT64_C(2147487867), // CV_DOTUP_B |
| 594 | UINT64_C(2147483771), // CV_DOTUP_H |
| 595 | UINT64_C(2147512443), // CV_DOTUP_SCI_B |
| 596 | UINT64_C(2147508347), // CV_DOTUP_SCI_H |
| 597 | UINT64_C(2147504251), // CV_DOTUP_SC_B |
| 598 | UINT64_C(2147500155), // CV_DOTUP_SC_H |
| 599 | UINT64_C(2281705595), // CV_DOTUSP_B |
| 600 | UINT64_C(2281701499), // CV_DOTUSP_H |
| 601 | UINT64_C(2281730171), // CV_DOTUSP_SCI_B |
| 602 | UINT64_C(2281726075), // CV_DOTUSP_SCI_H |
| 603 | UINT64_C(2281721979), // CV_DOTUSP_SC_B |
| 604 | UINT64_C(2281717883), // CV_DOTUSP_SC_H |
| 605 | UINT64_C(12299), // CV_ELW |
| 606 | UINT64_C(1677733931), // CV_EXTBS |
| 607 | UINT64_C(1711288363), // CV_EXTBZ |
| 608 | UINT64_C(1610625067), // CV_EXTHS |
| 609 | UINT64_C(1644179499), // CV_EXTHZ |
| 610 | UINT64_C(91), // CV_EXTRACT |
| 611 | UINT64_C(805318699), // CV_EXTRACTR |
| 612 | UINT64_C(1073741915), // CV_EXTRACTU |
| 613 | UINT64_C(838873131), // CV_EXTRACTUR |
| 614 | UINT64_C(3087020155), // CV_EXTRACTU_B |
| 615 | UINT64_C(3087016059), // CV_EXTRACTU_H |
| 616 | UINT64_C(3087011963), // CV_EXTRACT_B |
| 617 | UINT64_C(3087007867), // CV_EXTRACT_H |
| 618 | UINT64_C(1107308587), // CV_FF1 |
| 619 | UINT64_C(1140863019), // CV_FL1 |
| 620 | UINT64_C(2147483739), // CV_INSERT |
| 621 | UINT64_C(872427563), // CV_INSERTR |
| 622 | UINT64_C(3087028347), // CV_INSERT_B |
| 623 | UINT64_C(3087024251), // CV_INSERT_H |
| 624 | UINT64_C(16395), // CV_LBU_ri_inc |
| 625 | UINT64_C(402665515), // CV_LBU_rr |
| 626 | UINT64_C(268447787), // CV_LBU_rr_inc |
| 627 | UINT64_C(11), // CV_LB_ri_inc |
| 628 | UINT64_C(134230059), // CV_LB_rr |
| 629 | UINT64_C(12331), // CV_LB_rr_inc |
| 630 | UINT64_C(20491), // CV_LHU_ri_inc |
| 631 | UINT64_C(436219947), // CV_LHU_rr |
| 632 | UINT64_C(302002219), // CV_LHU_rr_inc |
| 633 | UINT64_C(4107), // CV_LH_ri_inc |
| 634 | UINT64_C(167784491), // CV_LH_rr |
| 635 | UINT64_C(33566763), // CV_LH_rr_inc |
| 636 | UINT64_C(8203), // CV_LW_ri_inc |
| 637 | UINT64_C(201338923), // CV_LW_rr |
| 638 | UINT64_C(67121195), // CV_LW_rr_inc |
| 639 | UINT64_C(2415931435), // CV_MAC |
| 640 | UINT64_C(1073766491), // CV_MACHHSN |
| 641 | UINT64_C(3221250139), // CV_MACHHSRN |
| 642 | UINT64_C(1073770587), // CV_MACHHUN |
| 643 | UINT64_C(3221254235), // CV_MACHHURN |
| 644 | UINT64_C(24667), // CV_MACSN |
| 645 | UINT64_C(2147508315), // CV_MACSRN |
| 646 | UINT64_C(28763), // CV_MACUN |
| 647 | UINT64_C(2147512411), // CV_MACURN |
| 648 | UINT64_C(1509961771), // CV_MAX |
| 649 | UINT64_C(1543516203), // CV_MAXU |
| 650 | UINT64_C(939528315), // CV_MAXU_B |
| 651 | UINT64_C(939524219), // CV_MAXU_H |
| 652 | UINT64_C(939552891), // CV_MAXU_SCI_B |
| 653 | UINT64_C(939548795), // CV_MAXU_SCI_H |
| 654 | UINT64_C(939544699), // CV_MAXU_SC_B |
| 655 | UINT64_C(939540603), // CV_MAXU_SC_H |
| 656 | UINT64_C(805310587), // CV_MAX_B |
| 657 | UINT64_C(805306491), // CV_MAX_H |
| 658 | UINT64_C(805335163), // CV_MAX_SCI_B |
| 659 | UINT64_C(805331067), // CV_MAX_SCI_H |
| 660 | UINT64_C(805326971), // CV_MAX_SC_B |
| 661 | UINT64_C(805322875), // CV_MAX_SC_H |
| 662 | UINT64_C(1442852907), // CV_MIN |
| 663 | UINT64_C(1476407339), // CV_MINU |
| 664 | UINT64_C(671092859), // CV_MINU_B |
| 665 | UINT64_C(671088763), // CV_MINU_H |
| 666 | UINT64_C(671117435), // CV_MINU_SCI_B |
| 667 | UINT64_C(671113339), // CV_MINU_SCI_H |
| 668 | UINT64_C(671109243), // CV_MINU_SC_B |
| 669 | UINT64_C(671105147), // CV_MINU_SC_H |
| 670 | UINT64_C(536875131), // CV_MIN_B |
| 671 | UINT64_C(536871035), // CV_MIN_H |
| 672 | UINT64_C(536899707), // CV_MIN_SCI_B |
| 673 | UINT64_C(536895611), // CV_MIN_SCI_H |
| 674 | UINT64_C(536891515), // CV_MIN_SC_B |
| 675 | UINT64_C(536887419), // CV_MIN_SC_H |
| 676 | UINT64_C(2449485867), // CV_MSU |
| 677 | UINT64_C(1073758299), // CV_MULHHSN |
| 678 | UINT64_C(3221241947), // CV_MULHHSRN |
| 679 | UINT64_C(1073762395), // CV_MULHHUN |
| 680 | UINT64_C(3221246043), // CV_MULHHURN |
| 681 | UINT64_C(16475), // CV_MULSN |
| 682 | UINT64_C(2147500123), // CV_MULSRN |
| 683 | UINT64_C(20571), // CV_MULUN |
| 684 | UINT64_C(2147504219), // CV_MULURN |
| 685 | UINT64_C(1476399227), // CV_OR_B |
| 686 | UINT64_C(1476395131), // CV_OR_H |
| 687 | UINT64_C(1476423803), // CV_OR_SCI_B |
| 688 | UINT64_C(1476419707), // CV_OR_SCI_H |
| 689 | UINT64_C(1476415611), // CV_OR_SC_B |
| 690 | UINT64_C(1476411515), // CV_OR_SC_H |
| 691 | UINT64_C(4026531963), // CV_PACK |
| 692 | UINT64_C(4194308219), // CV_PACKHI_B |
| 693 | UINT64_C(4160753787), // CV_PACKLO_B |
| 694 | UINT64_C(4060086395), // CV_PACK_H |
| 695 | UINT64_C(1073754155), // CV_ROR |
| 696 | UINT64_C(43), // CV_SB_ri_inc |
| 697 | UINT64_C(671100971), // CV_SB_rr |
| 698 | UINT64_C(536883243), // CV_SB_rr_inc |
| 699 | UINT64_C(2818576507), // CV_SDOTSP_B |
| 700 | UINT64_C(2818572411), // CV_SDOTSP_H |
| 701 | UINT64_C(2818601083), // CV_SDOTSP_SCI_B |
| 702 | UINT64_C(2818596987), // CV_SDOTSP_SCI_H |
| 703 | UINT64_C(2818592891), // CV_SDOTSP_SC_B |
| 704 | UINT64_C(2818588795), // CV_SDOTSP_SC_H |
| 705 | UINT64_C(2550141051), // CV_SDOTUP_B |
| 706 | UINT64_C(2550136955), // CV_SDOTUP_H |
| 707 | UINT64_C(2550165627), // CV_SDOTUP_SCI_B |
| 708 | UINT64_C(2550161531), // CV_SDOTUP_SCI_H |
| 709 | UINT64_C(2550157435), // CV_SDOTUP_SC_B |
| 710 | UINT64_C(2550153339), // CV_SDOTUP_SC_H |
| 711 | UINT64_C(2684358779), // CV_SDOTUSP_B |
| 712 | UINT64_C(2684354683), // CV_SDOTUSP_H |
| 713 | UINT64_C(2684383355), // CV_SDOTUSP_SCI_B |
| 714 | UINT64_C(2684379259), // CV_SDOTUSP_SCI_H |
| 715 | UINT64_C(2684375163), // CV_SDOTUSP_SC_B |
| 716 | UINT64_C(2684371067), // CV_SDOTUSP_SC_H |
| 717 | UINT64_C(3758100603), // CV_SHUFFLE2_B |
| 718 | UINT64_C(3758096507), // CV_SHUFFLE2_H |
| 719 | UINT64_C(3221254267), // CV_SHUFFLEI0_SCI_B |
| 720 | UINT64_C(3355471995), // CV_SHUFFLEI1_SCI_B |
| 721 | UINT64_C(3489689723), // CV_SHUFFLEI2_SCI_B |
| 722 | UINT64_C(3623907451), // CV_SHUFFLEI3_SCI_B |
| 723 | UINT64_C(3221229691), // CV_SHUFFLE_B |
| 724 | UINT64_C(3221225595), // CV_SHUFFLE_H |
| 725 | UINT64_C(3221250171), // CV_SHUFFLE_SCI_H |
| 726 | UINT64_C(4139), // CV_SH_ri_inc |
| 727 | UINT64_C(704655403), // CV_SH_rr |
| 728 | UINT64_C(570437675), // CV_SH_rr_inc |
| 729 | UINT64_C(1375744043), // CV_SLE |
| 730 | UINT64_C(1409298475), // CV_SLEU |
| 731 | UINT64_C(1342181499), // CV_SLL_B |
| 732 | UINT64_C(1342177403), // CV_SLL_H |
| 733 | UINT64_C(1342206075), // CV_SLL_SCI_B |
| 734 | UINT64_C(1342201979), // CV_SLL_SCI_H |
| 735 | UINT64_C(1342197883), // CV_SLL_SC_B |
| 736 | UINT64_C(1342193787), // CV_SLL_SC_H |
| 737 | UINT64_C(1207963771), // CV_SRA_B |
| 738 | UINT64_C(1207959675), // CV_SRA_H |
| 739 | UINT64_C(1207988347), // CV_SRA_SCI_B |
| 740 | UINT64_C(1207984251), // CV_SRA_SCI_H |
| 741 | UINT64_C(1207980155), // CV_SRA_SC_B |
| 742 | UINT64_C(1207976059), // CV_SRA_SC_H |
| 743 | UINT64_C(1073746043), // CV_SRL_B |
| 744 | UINT64_C(1073741947), // CV_SRL_H |
| 745 | UINT64_C(1073770619), // CV_SRL_SCI_B |
| 746 | UINT64_C(1073766523), // CV_SRL_SCI_H |
| 747 | UINT64_C(1073762427), // CV_SRL_SC_B |
| 748 | UINT64_C(1073758331), // CV_SRL_SC_H |
| 749 | UINT64_C(12379), // CV_SUBN |
| 750 | UINT64_C(2281713707), // CV_SUBNR |
| 751 | UINT64_C(2147496027), // CV_SUBRN |
| 752 | UINT64_C(2348822571), // CV_SUBRNR |
| 753 | UINT64_C(1677721723), // CV_SUBROTMJ |
| 754 | UINT64_C(1677729915), // CV_SUBROTMJ_DIV2 |
| 755 | UINT64_C(1677738107), // CV_SUBROTMJ_DIV4 |
| 756 | UINT64_C(1677746299), // CV_SUBROTMJ_DIV8 |
| 757 | UINT64_C(1073754203), // CV_SUBUN |
| 758 | UINT64_C(2315268139), // CV_SUBUNR |
| 759 | UINT64_C(3221237851), // CV_SUBURN |
| 760 | UINT64_C(2382377003), // CV_SUBURNR |
| 761 | UINT64_C(134221947), // CV_SUB_B |
| 762 | UINT64_C(1946165371), // CV_SUB_DIV2 |
| 763 | UINT64_C(1946173563), // CV_SUB_DIV4 |
| 764 | UINT64_C(1946181755), // CV_SUB_DIV8 |
| 765 | UINT64_C(134217851), // CV_SUB_H |
| 766 | UINT64_C(134246523), // CV_SUB_SCI_B |
| 767 | UINT64_C(134242427), // CV_SUB_SCI_H |
| 768 | UINT64_C(134238331), // CV_SUB_SC_B |
| 769 | UINT64_C(134234235), // CV_SUB_SC_H |
| 770 | UINT64_C(8235), // CV_SW_ri_inc |
| 771 | UINT64_C(738209835), // CV_SW_rr |
| 772 | UINT64_C(603992107), // CV_SW_rr_inc |
| 773 | UINT64_C(1610616955), // CV_XOR_B |
| 774 | UINT64_C(1610612859), // CV_XOR_H |
| 775 | UINT64_C(1610641531), // CV_XOR_SCI_B |
| 776 | UINT64_C(1610637435), // CV_XOR_SCI_H |
| 777 | UINT64_C(1610633339), // CV_XOR_SC_B |
| 778 | UINT64_C(1610629243), // CV_XOR_SC_H |
| 779 | UINT64_C(234901555), // CZERO_EQZ |
| 780 | UINT64_C(234909747), // CZERO_NEZ |
| 781 | UINT64_C(36866), // C_ADD |
| 782 | UINT64_C(1), // C_ADDI |
| 783 | UINT64_C(24833), // C_ADDI16SP |
| 784 | UINT64_C(0), // C_ADDI4SPN |
| 785 | UINT64_C(8193), // C_ADDIW |
| 786 | UINT64_C(39969), // C_ADDW |
| 787 | UINT64_C(35937), // C_AND |
| 788 | UINT64_C(34817), // C_ANDI |
| 789 | UINT64_C(49153), // C_BEQZ |
| 790 | UINT64_C(57345), // C_BNEZ |
| 791 | UINT64_C(36866), // C_EBREAK |
| 792 | UINT64_C(8192), // C_FLD |
| 793 | UINT64_C(8194), // C_FLDSP |
| 794 | UINT64_C(24576), // C_FLW |
| 795 | UINT64_C(24578), // C_FLWSP |
| 796 | UINT64_C(40960), // C_FSD |
| 797 | UINT64_C(40962), // C_FSDSP |
| 798 | UINT64_C(57344), // C_FSW |
| 799 | UINT64_C(57346), // C_FSWSP |
| 800 | UINT64_C(40961), // C_J |
| 801 | UINT64_C(8193), // C_JAL |
| 802 | UINT64_C(36866), // C_JALR |
| 803 | UINT64_C(32770), // C_JR |
| 804 | UINT64_C(32768), // C_LBU |
| 805 | UINT64_C(24576), // C_LD |
| 806 | UINT64_C(24578), // C_LDSP |
| 807 | UINT64_C(24578), // C_LDSP_RV32 |
| 808 | UINT64_C(24576), // C_LD_RV32 |
| 809 | UINT64_C(33856), // C_LH |
| 810 | UINT64_C(33792), // C_LHU |
| 811 | UINT64_C(33856), // C_LH_INX |
| 812 | UINT64_C(16385), // C_LI |
| 813 | UINT64_C(24577), // C_LUI |
| 814 | UINT64_C(16384), // C_LW |
| 815 | UINT64_C(16386), // C_LWSP |
| 816 | UINT64_C(16386), // C_LWSP_INX |
| 817 | UINT64_C(16384), // C_LW_INX |
| 818 | UINT64_C(25985), // C_MOP_11 |
| 819 | UINT64_C(26241), // C_MOP_13 |
| 820 | UINT64_C(26497), // C_MOP_15 |
| 821 | UINT64_C(24961), // C_MOP_3 |
| 822 | UINT64_C(25473), // C_MOP_7 |
| 823 | UINT64_C(25729), // C_MOP_9 |
| 824 | UINT64_C(40001), // C_MUL |
| 825 | UINT64_C(32770), // C_MV |
| 826 | UINT64_C(1), // C_NOP |
| 827 | UINT64_C(1), // C_NOP_HINT |
| 828 | UINT64_C(40053), // C_NOT |
| 829 | UINT64_C(35905), // C_OR |
| 830 | UINT64_C(34816), // C_SB |
| 831 | UINT64_C(57344), // C_SD |
| 832 | UINT64_C(57346), // C_SDSP |
| 833 | UINT64_C(57346), // C_SDSP_RV32 |
| 834 | UINT64_C(57344), // C_SD_RV32 |
| 835 | UINT64_C(40037), // C_SEXT_B |
| 836 | UINT64_C(40045), // C_SEXT_H |
| 837 | UINT64_C(35840), // C_SH |
| 838 | UINT64_C(35840), // C_SH_INX |
| 839 | UINT64_C(2), // C_SLLI |
| 840 | UINT64_C(33793), // C_SRAI |
| 841 | UINT64_C(32769), // C_SRLI |
| 842 | UINT64_C(25217), // C_SSPOPCHK |
| 843 | UINT64_C(24705), // C_SSPUSH |
| 844 | UINT64_C(35841), // C_SUB |
| 845 | UINT64_C(39937), // C_SUBW |
| 846 | UINT64_C(49152), // C_SW |
| 847 | UINT64_C(49154), // C_SWSP |
| 848 | UINT64_C(49154), // C_SWSP_INX |
| 849 | UINT64_C(49152), // C_SW_INX |
| 850 | UINT64_C(0), // C_UNIMP |
| 851 | UINT64_C(35873), // C_XOR |
| 852 | UINT64_C(40033), // C_ZEXT_B |
| 853 | UINT64_C(40041), // C_ZEXT_H |
| 854 | UINT64_C(40049), // C_ZEXT_W |
| 855 | UINT64_C(33570867), // DIV |
| 856 | UINT64_C(33574963), // DIVU |
| 857 | UINT64_C(33574971), // DIVUW |
| 858 | UINT64_C(33570875), // DIVW |
| 859 | UINT64_C(2065694835), // DRET |
| 860 | UINT64_C(1048691), // EBREAK |
| 861 | UINT64_C(115), // ECALL |
| 862 | UINT64_C(33554515), // FADD_D |
| 863 | UINT64_C(33554515), // FADD_D_IN32X |
| 864 | UINT64_C(33554515), // FADD_D_INX |
| 865 | UINT64_C(67108947), // FADD_H |
| 866 | UINT64_C(67108947), // FADD_H_INX |
| 867 | UINT64_C(100663379), // FADD_Q |
| 868 | UINT64_C(83), // FADD_S |
| 869 | UINT64_C(83), // FADD_S_INX |
| 870 | UINT64_C(3791654995), // FCLASS_D |
| 871 | UINT64_C(3791654995), // FCLASS_D_IN32X |
| 872 | UINT64_C(3791654995), // FCLASS_D_INX |
| 873 | UINT64_C(3825209427), // FCLASS_H |
| 874 | UINT64_C(3825209427), // FCLASS_H_INX |
| 875 | UINT64_C(3858763859), // FCLASS_Q |
| 876 | UINT64_C(3758100563), // FCLASS_S |
| 877 | UINT64_C(3758100563), // FCLASS_S_INX |
| 878 | UINT64_C(3263172691), // FCVTMOD_W_D |
| 879 | UINT64_C(1149239379), // FCVT_BF16_S |
| 880 | UINT64_C(1109393491), // FCVT_D_H |
| 881 | UINT64_C(1109393491), // FCVT_D_H_IN32X |
| 882 | UINT64_C(1109393491), // FCVT_D_H_INX |
| 883 | UINT64_C(3525312595), // FCVT_D_L |
| 884 | UINT64_C(3526361171), // FCVT_D_LU |
| 885 | UINT64_C(3526361171), // FCVT_D_LU_INX |
| 886 | UINT64_C(3525312595), // FCVT_D_L_INX |
| 887 | UINT64_C(1110442067), // FCVT_D_Q |
| 888 | UINT64_C(1107296339), // FCVT_D_S |
| 889 | UINT64_C(1107296339), // FCVT_D_S_IN32X |
| 890 | UINT64_C(1107296339), // FCVT_D_S_INX |
| 891 | UINT64_C(3523215443), // FCVT_D_W |
| 892 | UINT64_C(3524264019), // FCVT_D_WU |
| 893 | UINT64_C(3524264019), // FCVT_D_WU_IN32X |
| 894 | UINT64_C(3524264019), // FCVT_D_WU_INX |
| 895 | UINT64_C(3523215443), // FCVT_D_W_IN32X |
| 896 | UINT64_C(3523215443), // FCVT_D_W_INX |
| 897 | UINT64_C(1141899347), // FCVT_H_D |
| 898 | UINT64_C(1141899347), // FCVT_H_D_IN32X |
| 899 | UINT64_C(1141899347), // FCVT_H_D_INX |
| 900 | UINT64_C(3558867027), // FCVT_H_L |
| 901 | UINT64_C(3559915603), // FCVT_H_LU |
| 902 | UINT64_C(3559915603), // FCVT_H_LU_INX |
| 903 | UINT64_C(3558867027), // FCVT_H_L_INX |
| 904 | UINT64_C(1140850771), // FCVT_H_S |
| 905 | UINT64_C(1140850771), // FCVT_H_S_INX |
| 906 | UINT64_C(3556769875), // FCVT_H_W |
| 907 | UINT64_C(3557818451), // FCVT_H_WU |
| 908 | UINT64_C(3557818451), // FCVT_H_WU_INX |
| 909 | UINT64_C(3556769875), // FCVT_H_W_INX |
| 910 | UINT64_C(3257925715), // FCVT_LU_D |
| 911 | UINT64_C(3257925715), // FCVT_LU_D_INX |
| 912 | UINT64_C(3291480147), // FCVT_LU_H |
| 913 | UINT64_C(3291480147), // FCVT_LU_H_INX |
| 914 | UINT64_C(3325034579), // FCVT_LU_Q |
| 915 | UINT64_C(3224371283), // FCVT_LU_S |
| 916 | UINT64_C(3224371283), // FCVT_LU_S_INX |
| 917 | UINT64_C(3256877139), // FCVT_L_D |
| 918 | UINT64_C(3256877139), // FCVT_L_D_INX |
| 919 | UINT64_C(3290431571), // FCVT_L_H |
| 920 | UINT64_C(3290431571), // FCVT_L_H_INX |
| 921 | UINT64_C(3323986003), // FCVT_L_Q |
| 922 | UINT64_C(3223322707), // FCVT_L_S |
| 923 | UINT64_C(3223322707), // FCVT_L_S_INX |
| 924 | UINT64_C(1175453779), // FCVT_Q_D |
| 925 | UINT64_C(3592421459), // FCVT_Q_L |
| 926 | UINT64_C(3593470035), // FCVT_Q_LU |
| 927 | UINT64_C(1174405203), // FCVT_Q_S |
| 928 | UINT64_C(3590324307), // FCVT_Q_W |
| 929 | UINT64_C(3591372883), // FCVT_Q_WU |
| 930 | UINT64_C(1080033363), // FCVT_S_BF16 |
| 931 | UINT64_C(1074790483), // FCVT_S_D |
| 932 | UINT64_C(1074790483), // FCVT_S_D_IN32X |
| 933 | UINT64_C(1074790483), // FCVT_S_D_INX |
| 934 | UINT64_C(1075839059), // FCVT_S_H |
| 935 | UINT64_C(1075839059), // FCVT_S_H_INX |
| 936 | UINT64_C(3491758163), // FCVT_S_L |
| 937 | UINT64_C(3492806739), // FCVT_S_LU |
| 938 | UINT64_C(3492806739), // FCVT_S_LU_INX |
| 939 | UINT64_C(3491758163), // FCVT_S_L_INX |
| 940 | UINT64_C(1076887635), // FCVT_S_Q |
| 941 | UINT64_C(3489661011), // FCVT_S_W |
| 942 | UINT64_C(3490709587), // FCVT_S_WU |
| 943 | UINT64_C(3490709587), // FCVT_S_WU_INX |
| 944 | UINT64_C(3489661011), // FCVT_S_W_INX |
| 945 | UINT64_C(3255828563), // FCVT_WU_D |
| 946 | UINT64_C(3255828563), // FCVT_WU_D_IN32X |
| 947 | UINT64_C(3255828563), // FCVT_WU_D_INX |
| 948 | UINT64_C(3289382995), // FCVT_WU_H |
| 949 | UINT64_C(3289382995), // FCVT_WU_H_INX |
| 950 | UINT64_C(3322937427), // FCVT_WU_Q |
| 951 | UINT64_C(3222274131), // FCVT_WU_S |
| 952 | UINT64_C(3222274131), // FCVT_WU_S_INX |
| 953 | UINT64_C(3254779987), // FCVT_W_D |
| 954 | UINT64_C(3254779987), // FCVT_W_D_IN32X |
| 955 | UINT64_C(3254779987), // FCVT_W_D_INX |
| 956 | UINT64_C(3288334419), // FCVT_W_H |
| 957 | UINT64_C(3288334419), // FCVT_W_H_INX |
| 958 | UINT64_C(3321888851), // FCVT_W_Q |
| 959 | UINT64_C(3221225555), // FCVT_W_S |
| 960 | UINT64_C(3221225555), // FCVT_W_S_INX |
| 961 | UINT64_C(436207699), // FDIV_D |
| 962 | UINT64_C(436207699), // FDIV_D_IN32X |
| 963 | UINT64_C(436207699), // FDIV_D_INX |
| 964 | UINT64_C(469762131), // FDIV_H |
| 965 | UINT64_C(469762131), // FDIV_H_INX |
| 966 | UINT64_C(503316563), // FDIV_Q |
| 967 | UINT64_C(402653267), // FDIV_S |
| 968 | UINT64_C(402653267), // FDIV_S_INX |
| 969 | UINT64_C(15), // FENCE |
| 970 | UINT64_C(4111), // FENCE_I |
| 971 | UINT64_C(2200961039), // FENCE_TSO |
| 972 | UINT64_C(2717917267), // FEQ_D |
| 973 | UINT64_C(2717917267), // FEQ_D_IN32X |
| 974 | UINT64_C(2717917267), // FEQ_D_INX |
| 975 | UINT64_C(2751471699), // FEQ_H |
| 976 | UINT64_C(2751471699), // FEQ_H_INX |
| 977 | UINT64_C(2785026131), // FEQ_Q |
| 978 | UINT64_C(2684362835), // FEQ_S |
| 979 | UINT64_C(2684362835), // FEQ_S_INX |
| 980 | UINT64_C(12295), // FLD |
| 981 | UINT64_C(2717925459), // FLEQ_D |
| 982 | UINT64_C(2751479891), // FLEQ_H |
| 983 | UINT64_C(2785034323), // FLEQ_Q |
| 984 | UINT64_C(2684371027), // FLEQ_S |
| 985 | UINT64_C(2717909075), // FLE_D |
| 986 | UINT64_C(2717909075), // FLE_D_IN32X |
| 987 | UINT64_C(2717909075), // FLE_D_INX |
| 988 | UINT64_C(2751463507), // FLE_H |
| 989 | UINT64_C(2751463507), // FLE_H_INX |
| 990 | UINT64_C(2785017939), // FLE_Q |
| 991 | UINT64_C(2684354643), // FLE_S |
| 992 | UINT64_C(2684354643), // FLE_S_INX |
| 993 | UINT64_C(4103), // FLH |
| 994 | UINT64_C(4061134931), // FLI_D |
| 995 | UINT64_C(4094689363), // FLI_H |
| 996 | UINT64_C(4128243795), // FLI_Q |
| 997 | UINT64_C(4027580499), // FLI_S |
| 998 | UINT64_C(16391), // FLQ |
| 999 | UINT64_C(2717929555), // FLTQ_D |
| 1000 | UINT64_C(2751483987), // FLTQ_H |
| 1001 | UINT64_C(2785038419), // FLTQ_Q |
| 1002 | UINT64_C(2684375123), // FLTQ_S |
| 1003 | UINT64_C(2717913171), // FLT_D |
| 1004 | UINT64_C(2717913171), // FLT_D_IN32X |
| 1005 | UINT64_C(2717913171), // FLT_D_INX |
| 1006 | UINT64_C(2751467603), // FLT_H |
| 1007 | UINT64_C(2751467603), // FLT_H_INX |
| 1008 | UINT64_C(2785022035), // FLT_Q |
| 1009 | UINT64_C(2684358739), // FLT_S |
| 1010 | UINT64_C(2684358739), // FLT_S_INX |
| 1011 | UINT64_C(8199), // FLW |
| 1012 | UINT64_C(33554499), // FMADD_D |
| 1013 | UINT64_C(33554499), // FMADD_D_IN32X |
| 1014 | UINT64_C(33554499), // FMADD_D_INX |
| 1015 | UINT64_C(67108931), // FMADD_H |
| 1016 | UINT64_C(67108931), // FMADD_H_INX |
| 1017 | UINT64_C(100663363), // FMADD_Q |
| 1018 | UINT64_C(67), // FMADD_S |
| 1019 | UINT64_C(67), // FMADD_S_INX |
| 1020 | UINT64_C(704655443), // FMAXM_D |
| 1021 | UINT64_C(738209875), // FMAXM_H |
| 1022 | UINT64_C(771764307), // FMAXM_Q |
| 1023 | UINT64_C(671101011), // FMAXM_S |
| 1024 | UINT64_C(704647251), // FMAX_D |
| 1025 | UINT64_C(704647251), // FMAX_D_IN32X |
| 1026 | UINT64_C(704647251), // FMAX_D_INX |
| 1027 | UINT64_C(738201683), // FMAX_H |
| 1028 | UINT64_C(738201683), // FMAX_H_INX |
| 1029 | UINT64_C(771756115), // FMAX_Q |
| 1030 | UINT64_C(671092819), // FMAX_S |
| 1031 | UINT64_C(671092819), // FMAX_S_INX |
| 1032 | UINT64_C(704651347), // FMINM_D |
| 1033 | UINT64_C(738205779), // FMINM_H |
| 1034 | UINT64_C(771760211), // FMINM_Q |
| 1035 | UINT64_C(671096915), // FMINM_S |
| 1036 | UINT64_C(704643155), // FMIN_D |
| 1037 | UINT64_C(704643155), // FMIN_D_IN32X |
| 1038 | UINT64_C(704643155), // FMIN_D_INX |
| 1039 | UINT64_C(738197587), // FMIN_H |
| 1040 | UINT64_C(738197587), // FMIN_H_INX |
| 1041 | UINT64_C(771752019), // FMIN_Q |
| 1042 | UINT64_C(671088723), // FMIN_S |
| 1043 | UINT64_C(671088723), // FMIN_S_INX |
| 1044 | UINT64_C(33554503), // FMSUB_D |
| 1045 | UINT64_C(33554503), // FMSUB_D_IN32X |
| 1046 | UINT64_C(33554503), // FMSUB_D_INX |
| 1047 | UINT64_C(67108935), // FMSUB_H |
| 1048 | UINT64_C(67108935), // FMSUB_H_INX |
| 1049 | UINT64_C(100663367), // FMSUB_Q |
| 1050 | UINT64_C(71), // FMSUB_S |
| 1051 | UINT64_C(71), // FMSUB_S_INX |
| 1052 | UINT64_C(301989971), // FMUL_D |
| 1053 | UINT64_C(301989971), // FMUL_D_IN32X |
| 1054 | UINT64_C(301989971), // FMUL_D_INX |
| 1055 | UINT64_C(335544403), // FMUL_H |
| 1056 | UINT64_C(335544403), // FMUL_H_INX |
| 1057 | UINT64_C(369098835), // FMUL_Q |
| 1058 | UINT64_C(268435539), // FMUL_S |
| 1059 | UINT64_C(268435539), // FMUL_S_INX |
| 1060 | UINT64_C(3792699475), // FMVH_X_D |
| 1061 | UINT64_C(3859808339), // FMVH_X_Q |
| 1062 | UINT64_C(2986344531), // FMVP_D_X |
| 1063 | UINT64_C(3053453395), // FMVP_Q_X |
| 1064 | UINT64_C(4060086355), // FMV_D_X |
| 1065 | UINT64_C(4093640787), // FMV_H_X |
| 1066 | UINT64_C(4026531923), // FMV_W_X |
| 1067 | UINT64_C(3791650899), // FMV_X_D |
| 1068 | UINT64_C(3825205331), // FMV_X_H |
| 1069 | UINT64_C(3758096467), // FMV_X_W |
| 1070 | UINT64_C(3758096467), // FMV_X_W_FPR64 |
| 1071 | UINT64_C(33554511), // FNMADD_D |
| 1072 | UINT64_C(33554511), // FNMADD_D_IN32X |
| 1073 | UINT64_C(33554511), // FNMADD_D_INX |
| 1074 | UINT64_C(67108943), // FNMADD_H |
| 1075 | UINT64_C(67108943), // FNMADD_H_INX |
| 1076 | UINT64_C(100663375), // FNMADD_Q |
| 1077 | UINT64_C(79), // FNMADD_S |
| 1078 | UINT64_C(79), // FNMADD_S_INX |
| 1079 | UINT64_C(33554507), // FNMSUB_D |
| 1080 | UINT64_C(33554507), // FNMSUB_D_IN32X |
| 1081 | UINT64_C(33554507), // FNMSUB_D_INX |
| 1082 | UINT64_C(67108939), // FNMSUB_H |
| 1083 | UINT64_C(67108939), // FNMSUB_H_INX |
| 1084 | UINT64_C(100663371), // FNMSUB_Q |
| 1085 | UINT64_C(75), // FNMSUB_S |
| 1086 | UINT64_C(75), // FNMSUB_S_INX |
| 1087 | UINT64_C(1112539219), // FROUNDNX_D |
| 1088 | UINT64_C(1146093651), // FROUNDNX_H |
| 1089 | UINT64_C(1179648083), // FROUNDNX_Q |
| 1090 | UINT64_C(1078984787), // FROUNDNX_S |
| 1091 | UINT64_C(1111490643), // FROUND_D |
| 1092 | UINT64_C(1145045075), // FROUND_H |
| 1093 | UINT64_C(1178599507), // FROUND_Q |
| 1094 | UINT64_C(1077936211), // FROUND_S |
| 1095 | UINT64_C(12327), // FSD |
| 1096 | UINT64_C(570429523), // FSGNJN_D |
| 1097 | UINT64_C(570429523), // FSGNJN_D_IN32X |
| 1098 | UINT64_C(570429523), // FSGNJN_D_INX |
| 1099 | UINT64_C(603983955), // FSGNJN_H |
| 1100 | UINT64_C(603983955), // FSGNJN_H_INX |
| 1101 | UINT64_C(637538387), // FSGNJN_Q |
| 1102 | UINT64_C(536875091), // FSGNJN_S |
| 1103 | UINT64_C(536875091), // FSGNJN_S_INX |
| 1104 | UINT64_C(570433619), // FSGNJX_D |
| 1105 | UINT64_C(570433619), // FSGNJX_D_IN32X |
| 1106 | UINT64_C(570433619), // FSGNJX_D_INX |
| 1107 | UINT64_C(603988051), // FSGNJX_H |
| 1108 | UINT64_C(603988051), // FSGNJX_H_INX |
| 1109 | UINT64_C(637542483), // FSGNJX_Q |
| 1110 | UINT64_C(536879187), // FSGNJX_S |
| 1111 | UINT64_C(536879187), // FSGNJX_S_INX |
| 1112 | UINT64_C(570425427), // FSGNJ_D |
| 1113 | UINT64_C(570425427), // FSGNJ_D_IN32X |
| 1114 | UINT64_C(570425427), // FSGNJ_D_INX |
| 1115 | UINT64_C(603979859), // FSGNJ_H |
| 1116 | UINT64_C(603979859), // FSGNJ_H_INX |
| 1117 | UINT64_C(637534291), // FSGNJ_Q |
| 1118 | UINT64_C(536870995), // FSGNJ_S |
| 1119 | UINT64_C(536870995), // FSGNJ_S_INX |
| 1120 | UINT64_C(4135), // FSH |
| 1121 | UINT64_C(16423), // FSQ |
| 1122 | UINT64_C(1509949523), // FSQRT_D |
| 1123 | UINT64_C(1509949523), // FSQRT_D_IN32X |
| 1124 | UINT64_C(1509949523), // FSQRT_D_INX |
| 1125 | UINT64_C(1543503955), // FSQRT_H |
| 1126 | UINT64_C(1543503955), // FSQRT_H_INX |
| 1127 | UINT64_C(1577058387), // FSQRT_Q |
| 1128 | UINT64_C(1476395091), // FSQRT_S |
| 1129 | UINT64_C(1476395091), // FSQRT_S_INX |
| 1130 | UINT64_C(167772243), // FSUB_D |
| 1131 | UINT64_C(167772243), // FSUB_D_IN32X |
| 1132 | UINT64_C(167772243), // FSUB_D_INX |
| 1133 | UINT64_C(201326675), // FSUB_H |
| 1134 | UINT64_C(201326675), // FSUB_H_INX |
| 1135 | UINT64_C(234881107), // FSUB_Q |
| 1136 | UINT64_C(134217811), // FSUB_S |
| 1137 | UINT64_C(134217811), // FSUB_S_INX |
| 1138 | UINT64_C(8231), // FSW |
| 1139 | UINT64_C(1644167283), // HFENCE_GVMA |
| 1140 | UINT64_C(570425459), // HFENCE_VVMA |
| 1141 | UINT64_C(1711276147), // HINVAL_GVMA |
| 1142 | UINT64_C(637534323), // HINVAL_VVMA |
| 1143 | UINT64_C(1680883827), // HLVX_HU |
| 1144 | UINT64_C(1747992691), // HLVX_WU |
| 1145 | UINT64_C(1610629235), // HLV_B |
| 1146 | UINT64_C(1611677811), // HLV_BU |
| 1147 | UINT64_C(1811955827), // HLV_D |
| 1148 | UINT64_C(1677738099), // HLV_H |
| 1149 | UINT64_C(1678786675), // HLV_HU |
| 1150 | UINT64_C(1744846963), // HLV_W |
| 1151 | UINT64_C(1745895539), // HLV_WU |
| 1152 | UINT64_C(1644183667), // HSV_B |
| 1153 | UINT64_C(1845510259), // HSV_D |
| 1154 | UINT64_C(1711292531), // HSV_H |
| 1155 | UINT64_C(1778401395), // HSV_W |
| 1156 | UINT64_C(0), // Insn16 |
| 1157 | UINT64_C(0), // Insn32 |
| 1158 | UINT64_C(0), // Insn48 |
| 1159 | UINT64_C(0), // Insn64 |
| 1160 | UINT64_C(0), // InsnB |
| 1161 | UINT64_C(0), // InsnCA |
| 1162 | UINT64_C(0), // InsnCB |
| 1163 | UINT64_C(0), // InsnCI |
| 1164 | UINT64_C(0), // InsnCIW |
| 1165 | UINT64_C(0), // InsnCJ |
| 1166 | UINT64_C(0), // InsnCL |
| 1167 | UINT64_C(0), // InsnCR |
| 1168 | UINT64_C(0), // InsnCS |
| 1169 | UINT64_C(0), // InsnCSS |
| 1170 | UINT64_C(0), // InsnI |
| 1171 | UINT64_C(0), // InsnI_Mem |
| 1172 | UINT64_C(0), // InsnJ |
| 1173 | UINT64_C(0), // InsnQC_EAI |
| 1174 | UINT64_C(0), // InsnQC_EB |
| 1175 | UINT64_C(0), // InsnQC_EI |
| 1176 | UINT64_C(0), // InsnQC_EI_Mem |
| 1177 | UINT64_C(0), // InsnQC_EJ |
| 1178 | UINT64_C(0), // InsnQC_ES |
| 1179 | UINT64_C(0), // InsnR |
| 1180 | UINT64_C(0), // InsnR4 |
| 1181 | UINT64_C(0), // InsnS |
| 1182 | UINT64_C(0), // InsnU |
| 1183 | UINT64_C(111), // JAL |
| 1184 | UINT64_C(103), // JALR |
| 1185 | UINT64_C(3), // LB |
| 1186 | UINT64_C(16387), // LBU |
| 1187 | UINT64_C(872415279), // LB_AQ |
| 1188 | UINT64_C(905969711), // LB_AQRL |
| 1189 | UINT64_C(12291), // LD |
| 1190 | UINT64_C(872427567), // LD_AQ |
| 1191 | UINT64_C(905981999), // LD_AQRL |
| 1192 | UINT64_C(12291), // LD_RV32 |
| 1193 | UINT64_C(4099), // LH |
| 1194 | UINT64_C(20483), // LHU |
| 1195 | UINT64_C(872419375), // LH_AQ |
| 1196 | UINT64_C(905973807), // LH_AQRL |
| 1197 | UINT64_C(4099), // LH_INX |
| 1198 | UINT64_C(268447791), // LR_D |
| 1199 | UINT64_C(335556655), // LR_D_AQ |
| 1200 | UINT64_C(369111087), // LR_D_AQRL |
| 1201 | UINT64_C(302002223), // LR_D_RL |
| 1202 | UINT64_C(268443695), // LR_W |
| 1203 | UINT64_C(335552559), // LR_W_AQ |
| 1204 | UINT64_C(369106991), // LR_W_AQRL |
| 1205 | UINT64_C(301998127), // LR_W_RL |
| 1206 | UINT64_C(55), // LUI |
| 1207 | UINT64_C(8195), // LW |
| 1208 | UINT64_C(24579), // LWU |
| 1209 | UINT64_C(872423471), // LW_AQ |
| 1210 | UINT64_C(905977903), // LW_AQRL |
| 1211 | UINT64_C(8195), // LW_INX |
| 1212 | UINT64_C(3925880891), // MACCSU_H00 |
| 1213 | UINT64_C(4194316347), // MACCSU_H11 |
| 1214 | UINT64_C(3992989755), // MACCSU_W00 |
| 1215 | UINT64_C(4261425211), // MACCSU_W11 |
| 1216 | UINT64_C(2852139067), // MACCU_H00 |
| 1217 | UINT64_C(3120566331), // MACCU_H01 |
| 1218 | UINT64_C(3120574523), // MACCU_H11 |
| 1219 | UINT64_C(2919247931), // MACCU_W00 |
| 1220 | UINT64_C(3187675195), // MACCU_W01 |
| 1221 | UINT64_C(3187683387), // MACCU_W11 |
| 1222 | UINT64_C(2315268155), // MACC_H00 |
| 1223 | UINT64_C(2583695419), // MACC_H01 |
| 1224 | UINT64_C(2583703611), // MACC_H11 |
| 1225 | UINT64_C(2382377019), // MACC_W00 |
| 1226 | UINT64_C(2650804283), // MACC_W01 |
| 1227 | UINT64_C(2650812475), // MACC_W11 |
| 1228 | UINT64_C(167796787), // MAX |
| 1229 | UINT64_C(167800883), // MAXU |
| 1230 | UINT64_C(2885685307), // MERGE |
| 1231 | UINT64_C(2315284539), // MHACC |
| 1232 | UINT64_C(3389026363), // MHACCSU |
| 1233 | UINT64_C(2919264315), // MHACCSU_H0 |
| 1234 | UINT64_C(3187699771), // MHACCSU_H1 |
| 1235 | UINT64_C(2583719995), // MHACCU |
| 1236 | UINT64_C(2852155451), // MHACC_H0 |
| 1237 | UINT64_C(3120590907), // MHACC_H1 |
| 1238 | UINT64_C(2382393403), // MHRACC |
| 1239 | UINT64_C(3456135227), // MHRACCSU |
| 1240 | UINT64_C(2650828859), // MHRACCU |
| 1241 | UINT64_C(167788595), // MIN |
| 1242 | UINT64_C(167792691), // MINU |
| 1243 | UINT64_C(100675595), // MIPS_CCMOV |
| 1244 | UINT64_C(3149843), // MIPS_EHB |
| 1245 | UINT64_C(1052691), // MIPS_IHB |
| 1246 | UINT64_C(16395), // MIPS_LDP |
| 1247 | UINT64_C(1064971), // MIPS_LWP |
| 1248 | UINT64_C(5246995), // MIPS_PAUSE |
| 1249 | UINT64_C(11), // MIPS_PREF |
| 1250 | UINT64_C(20491), // MIPS_SDP |
| 1251 | UINT64_C(20619), // MIPS_SWP |
| 1252 | UINT64_C(1881145459), // MNRET |
| 1253 | UINT64_C(2181054579), // MOP_RR_0 |
| 1254 | UINT64_C(2248163443), // MOP_RR_1 |
| 1255 | UINT64_C(2315272307), // MOP_RR_2 |
| 1256 | UINT64_C(2382381171), // MOP_RR_3 |
| 1257 | UINT64_C(3254796403), // MOP_RR_4 |
| 1258 | UINT64_C(3321905267), // MOP_RR_5 |
| 1259 | UINT64_C(3389014131), // MOP_RR_6 |
| 1260 | UINT64_C(3456122995), // MOP_RR_7 |
| 1261 | UINT64_C(2176860275), // MOP_R_0 |
| 1262 | UINT64_C(2177908851), // MOP_R_1 |
| 1263 | UINT64_C(2313175155), // MOP_R_10 |
| 1264 | UINT64_C(2314223731), // MOP_R_11 |
| 1265 | UINT64_C(2378186867), // MOP_R_12 |
| 1266 | UINT64_C(2379235443), // MOP_R_13 |
| 1267 | UINT64_C(2380284019), // MOP_R_14 |
| 1268 | UINT64_C(2381332595), // MOP_R_15 |
| 1269 | UINT64_C(3250602099), // MOP_R_16 |
| 1270 | UINT64_C(3251650675), // MOP_R_17 |
| 1271 | UINT64_C(3252699251), // MOP_R_18 |
| 1272 | UINT64_C(3253747827), // MOP_R_19 |
| 1273 | UINT64_C(2178957427), // MOP_R_2 |
| 1274 | UINT64_C(3317710963), // MOP_R_20 |
| 1275 | UINT64_C(3318759539), // MOP_R_21 |
| 1276 | UINT64_C(3319808115), // MOP_R_22 |
| 1277 | UINT64_C(3320856691), // MOP_R_23 |
| 1278 | UINT64_C(3384819827), // MOP_R_24 |
| 1279 | UINT64_C(3385868403), // MOP_R_25 |
| 1280 | UINT64_C(3386916979), // MOP_R_26 |
| 1281 | UINT64_C(3387965555), // MOP_R_27 |
| 1282 | UINT64_C(3451928691), // MOP_R_28 |
| 1283 | UINT64_C(3452977267), // MOP_R_29 |
| 1284 | UINT64_C(2180006003), // MOP_R_3 |
| 1285 | UINT64_C(3454025843), // MOP_R_30 |
| 1286 | UINT64_C(3455074419), // MOP_R_31 |
| 1287 | UINT64_C(2243969139), // MOP_R_4 |
| 1288 | UINT64_C(2245017715), // MOP_R_5 |
| 1289 | UINT64_C(2246066291), // MOP_R_6 |
| 1290 | UINT64_C(2247114867), // MOP_R_7 |
| 1291 | UINT64_C(2311078003), // MOP_R_8 |
| 1292 | UINT64_C(2312126579), // MOP_R_9 |
| 1293 | UINT64_C(3892342843), // MQACC_H00 |
| 1294 | UINT64_C(4160770107), // MQACC_H01 |
| 1295 | UINT64_C(4160778299), // MQACC_H11 |
| 1296 | UINT64_C(3925897275), // MQACC_W00 |
| 1297 | UINT64_C(4194324539), // MQACC_W01 |
| 1298 | UINT64_C(4194332731), // MQACC_W11 |
| 1299 | UINT64_C(3959451707), // MQRACC_H00 |
| 1300 | UINT64_C(4227878971), // MQRACC_H01 |
| 1301 | UINT64_C(4227887163), // MQRACC_H11 |
| 1302 | UINT64_C(3993006139), // MQRACC_W00 |
| 1303 | UINT64_C(4261433403), // MQRACC_W01 |
| 1304 | UINT64_C(4261441595), // MQRACC_W11 |
| 1305 | UINT64_C(2113937563), // MQRWACC |
| 1306 | UINT64_C(2046828699), // MQWACC |
| 1307 | UINT64_C(807403635), // MRET |
| 1308 | UINT64_C(3254804539), // MSEQ |
| 1309 | UINT64_C(3523239995), // MSLT |
| 1310 | UINT64_C(3657457723), // MSLTU |
| 1311 | UINT64_C(33554483), // MUL |
| 1312 | UINT64_C(33558579), // MULH |
| 1313 | UINT64_C(2248175675), // MULHR |
| 1314 | UINT64_C(3321917499), // MULHRSU |
| 1315 | UINT64_C(2516611131), // MULHRU |
| 1316 | UINT64_C(33562675), // MULHSU |
| 1317 | UINT64_C(2785046587), // MULHSU_H0 |
| 1318 | UINT64_C(3053482043), // MULHSU_H1 |
| 1319 | UINT64_C(33566771), // MULHU |
| 1320 | UINT64_C(2717937723), // MULH_H0 |
| 1321 | UINT64_C(2986373179), // MULH_H1 |
| 1322 | UINT64_C(3523244091), // MULQ |
| 1323 | UINT64_C(3590352955), // MULQR |
| 1324 | UINT64_C(3791663163), // MULSU_H00 |
| 1325 | UINT64_C(4060098619), // MULSU_H11 |
| 1326 | UINT64_C(3858772027), // MULSU_W00 |
| 1327 | UINT64_C(4127207483), // MULSU_W11 |
| 1328 | UINT64_C(2717921339), // MULU_H00 |
| 1329 | UINT64_C(2986348603), // MULU_H01 |
| 1330 | UINT64_C(2986356795), // MULU_H11 |
| 1331 | UINT64_C(2785030203), // MULU_W00 |
| 1332 | UINT64_C(3053457467), // MULU_W01 |
| 1333 | UINT64_C(3053465659), // MULU_W11 |
| 1334 | UINT64_C(33554491), // MULW |
| 1335 | UINT64_C(2181050427), // MUL_H00 |
| 1336 | UINT64_C(2449477691), // MUL_H01 |
| 1337 | UINT64_C(2449485883), // MUL_H11 |
| 1338 | UINT64_C(2248159291), // MUL_W00 |
| 1339 | UINT64_C(2516586555), // MUL_W01 |
| 1340 | UINT64_C(2516594747), // MUL_W11 |
| 1341 | UINT64_C(2818576443), // MVM |
| 1342 | UINT64_C(2852130875), // MVMN |
| 1343 | UINT64_C(1845542939), // NCLIP |
| 1344 | UINT64_C(1677770779), // NCLIPI |
| 1345 | UINT64_C(604028955), // NCLIPIU |
| 1346 | UINT64_C(2113978395), // NCLIPR |
| 1347 | UINT64_C(1946206235), // NCLIPRI |
| 1348 | UINT64_C(872464411), // NCLIPRIU |
| 1349 | UINT64_C(1040236571), // NCLIPRU |
| 1350 | UINT64_C(771801115), // NCLIPU |
| 1351 | UINT64_C(4107), // NDS_ADDIGP |
| 1352 | UINT64_C(28763), // NDS_BBC |
| 1353 | UINT64_C(1073770587), // NDS_BBS |
| 1354 | UINT64_C(20571), // NDS_BEQC |
| 1355 | UINT64_C(12379), // NDS_BFOS |
| 1356 | UINT64_C(8283), // NDS_BFOZ |
| 1357 | UINT64_C(24667), // NDS_BNEC |
| 1358 | UINT64_C(114779), // NDS_FCVT_BF16_S |
| 1359 | UINT64_C(82011), // NDS_FCVT_S_BF16 |
| 1360 | UINT64_C(536871003), // NDS_FFB |
| 1361 | UINT64_C(603979867), // NDS_FFMISM |
| 1362 | UINT64_C(570425435), // NDS_FFZMISM |
| 1363 | UINT64_C(637534299), // NDS_FLMISM |
| 1364 | UINT64_C(4026531923), // NDS_FMV_BF16_X |
| 1365 | UINT64_C(3758096467), // NDS_FMV_X_BF16 |
| 1366 | UINT64_C(11), // NDS_LBGP |
| 1367 | UINT64_C(8203), // NDS_LBUGP |
| 1368 | UINT64_C(12331), // NDS_LDGP |
| 1369 | UINT64_C(268435547), // NDS_LEA_B_ZE |
| 1370 | UINT64_C(234881115), // NDS_LEA_D |
| 1371 | UINT64_C(369098843), // NDS_LEA_D_ZE |
| 1372 | UINT64_C(167772251), // NDS_LEA_H |
| 1373 | UINT64_C(301989979), // NDS_LEA_H_ZE |
| 1374 | UINT64_C(201326683), // NDS_LEA_W |
| 1375 | UINT64_C(335544411), // NDS_LEA_W_ZE |
| 1376 | UINT64_C(4139), // NDS_LHGP |
| 1377 | UINT64_C(20523), // NDS_LHUGP |
| 1378 | UINT64_C(8235), // NDS_LWGP |
| 1379 | UINT64_C(24619), // NDS_LWUGP |
| 1380 | UINT64_C(12299), // NDS_SBGP |
| 1381 | UINT64_C(28715), // NDS_SDGP |
| 1382 | UINT64_C(43), // NDS_SHGP |
| 1383 | UINT64_C(16427), // NDS_SWGP |
| 1384 | UINT64_C(335560795), // NDS_VD4DOTSU_VV |
| 1385 | UINT64_C(268451931), // NDS_VD4DOTS_VV |
| 1386 | UINT64_C(469778523), // NDS_VD4DOTU_VV |
| 1387 | UINT64_C(49243), // NDS_VFNCVT_BF16_S |
| 1388 | UINT64_C(201343067), // NDS_VFPMADB_VF |
| 1389 | UINT64_C(134234203), // NDS_VFPMADT_VF |
| 1390 | UINT64_C(213083), // NDS_VFWCVT_F_B |
| 1391 | UINT64_C(245851), // NDS_VFWCVT_F_BU |
| 1392 | UINT64_C(147547), // NDS_VFWCVT_F_N |
| 1393 | UINT64_C(180315), // NDS_VFWCVT_F_NU |
| 1394 | UINT64_C(16475), // NDS_VFWCVT_S_BF16 |
| 1395 | UINT64_C(100679771), // NDS_VLE4_V |
| 1396 | UINT64_C(69222491), // NDS_VLN8_V |
| 1397 | UINT64_C(70271067), // NDS_VLNU8_V |
| 1398 | UINT64_C(1308672027), // NSRA |
| 1399 | UINT64_C(1140899867), // NSRAI |
| 1400 | UINT64_C(1577107483), // NSRAR |
| 1401 | UINT64_C(1409335323), // NSRARI |
| 1402 | UINT64_C(234930203), // NSRL |
| 1403 | UINT64_C(67158043), // NSRLI |
| 1404 | UINT64_C(24627), // OR |
| 1405 | UINT64_C(678449171), // ORC_B |
| 1406 | UINT64_C(24595), // ORI |
| 1407 | UINT64_C(1073766451), // ORN |
| 1408 | UINT64_C(3154116667), // PAADDU_B |
| 1409 | UINT64_C(3154141211), // PAADDU_DB |
| 1410 | UINT64_C(3087032347), // PAADDU_DH |
| 1411 | UINT64_C(3120586779), // PAADDU_DW |
| 1412 | UINT64_C(3087007803), // PAADDU_H |
| 1413 | UINT64_C(3120562235), // PAADDU_W |
| 1414 | UINT64_C(2617245755), // PAADD_B |
| 1415 | UINT64_C(2617270299), // PAADD_DB |
| 1416 | UINT64_C(2550161435), // PAADD_DH |
| 1417 | UINT64_C(2583715867), // PAADD_DW |
| 1418 | UINT64_C(2550136891), // PAADD_H |
| 1419 | UINT64_C(2583691323), // PAADD_W |
| 1420 | UINT64_C(2551242779), // PAAS_DHX |
| 1421 | UINT64_C(2550161467), // PAAS_HX |
| 1422 | UINT64_C(2583715899), // PAAS_WX |
| 1423 | UINT64_C(3154120763), // PABDSUMAU_B |
| 1424 | UINT64_C(3019903035), // PABDSUMU_B |
| 1425 | UINT64_C(3959423035), // PABDU_B |
| 1426 | UINT64_C(3959447579), // PABDU_DB |
| 1427 | UINT64_C(3892338715), // PABDU_DH |
| 1428 | UINT64_C(3892314171), // PABDU_H |
| 1429 | UINT64_C(3422552123), // PABD_B |
| 1430 | UINT64_C(3422576667), // PABD_DB |
| 1431 | UINT64_C(3355467803), // PABD_DH |
| 1432 | UINT64_C(3355443259), // PABD_H |
| 1433 | UINT64_C(134234163), // PACK |
| 1434 | UINT64_C(134246451), // PACKH |
| 1435 | UINT64_C(134234171), // PACKW |
| 1436 | UINT64_C(2214592571), // PADD_B |
| 1437 | UINT64_C(2617253915), // PADD_BS |
| 1438 | UINT64_C(2214617115), // PADD_DB |
| 1439 | UINT64_C(469786651), // PADD_DBS |
| 1440 | UINT64_C(2147508251), // PADD_DH |
| 1441 | UINT64_C(402677787), // PADD_DHS |
| 1442 | UINT64_C(2181062683), // PADD_DW |
| 1443 | UINT64_C(436232219), // PADD_DWS |
| 1444 | UINT64_C(2147483707), // PADD_H |
| 1445 | UINT64_C(2550145051), // PADD_HS |
| 1446 | UINT64_C(2181038139), // PADD_W |
| 1447 | UINT64_C(2583699483), // PADD_WS |
| 1448 | UINT64_C(2618351643), // PASA_DHX |
| 1449 | UINT64_C(2617270331), // PASA_HX |
| 1450 | UINT64_C(2650824763), // PASA_WX |
| 1451 | UINT64_C(4227858491), // PASUBU_B |
| 1452 | UINT64_C(4227883035), // PASUBU_DB |
| 1453 | UINT64_C(4160774171), // PASUBU_DH |
| 1454 | UINT64_C(4194328603), // PASUBU_DW |
| 1455 | UINT64_C(4160749627), // PASUBU_H |
| 1456 | UINT64_C(4194304059), // PASUBU_W |
| 1457 | UINT64_C(3690987579), // PASUB_B |
| 1458 | UINT64_C(3691012123), // PASUB_DB |
| 1459 | UINT64_C(3623903259), // PASUB_DH |
| 1460 | UINT64_C(3657457691), // PASUB_DW |
| 1461 | UINT64_C(3623878715), // PASUB_H |
| 1462 | UINT64_C(3657433147), // PASUB_W |
| 1463 | UINT64_C(2148589595), // PAS_DHX |
| 1464 | UINT64_C(2147508283), // PAS_HX |
| 1465 | UINT64_C(2181062715), // PAS_WX |
| 1466 | UINT64_C(3019907099), // PLI_B |
| 1467 | UINT64_C(872423451), // PLI_DB |
| 1468 | UINT64_C(805314587), // PLI_DH |
| 1469 | UINT64_C(2952798235), // PLI_H |
| 1470 | UINT64_C(2986352667), // PLI_W |
| 1471 | UINT64_C(1879056411), // PLUI_DH |
| 1472 | UINT64_C(4026540059), // PLUI_H |
| 1473 | UINT64_C(4060094491), // PLUI_W |
| 1474 | UINT64_C(3892334651), // PM2ADDASU_H |
| 1475 | UINT64_C(3925889083), // PM2ADDASU_W |
| 1476 | UINT64_C(2818592827), // PM2ADDAU_H |
| 1477 | UINT64_C(2852147259), // PM2ADDAU_W |
| 1478 | UINT64_C(2281721915), // PM2ADDA_H |
| 1479 | UINT64_C(2550157371), // PM2ADDA_HX |
| 1480 | UINT64_C(2315276347), // PM2ADDA_W |
| 1481 | UINT64_C(2583711803), // PM2ADDA_WX |
| 1482 | UINT64_C(3758116923), // PM2ADDSU_H |
| 1483 | UINT64_C(3791671355), // PM2ADDSU_W |
| 1484 | UINT64_C(2684375099), // PM2ADDU_H |
| 1485 | UINT64_C(2717929531), // PM2ADDU_W |
| 1486 | UINT64_C(2147504187), // PM2ADD_H |
| 1487 | UINT64_C(2415939643), // PM2ADD_HX |
| 1488 | UINT64_C(2181058619), // PM2ADD_W |
| 1489 | UINT64_C(2449494075), // PM2ADD_WX |
| 1490 | UINT64_C(3288354875), // PM2SADD_H |
| 1491 | UINT64_C(3556790331), // PM2SADD_HX |
| 1492 | UINT64_C(3355463739), // PM2SUBA_H |
| 1493 | UINT64_C(3623899195), // PM2SUBA_HX |
| 1494 | UINT64_C(3389018171), // PM2SUBA_W |
| 1495 | UINT64_C(3657453627), // PM2SUBA_WX |
| 1496 | UINT64_C(3221246011), // PM2SUB_H |
| 1497 | UINT64_C(3489681467), // PM2SUB_HX |
| 1498 | UINT64_C(3254800443), // PM2SUB_W |
| 1499 | UINT64_C(3523235899), // PM2SUB_WX |
| 1500 | UINT64_C(1845502107), // PM2WADDASU_H |
| 1501 | UINT64_C(771760283), // PM2WADDAU_H |
| 1502 | UINT64_C(234889371), // PM2WADDA_H |
| 1503 | UINT64_C(503324827), // PM2WADDA_HX |
| 1504 | UINT64_C(1711284379), // PM2WADDSU_H |
| 1505 | UINT64_C(637542555), // PM2WADDU_H |
| 1506 | UINT64_C(100671643), // PM2WADD_H |
| 1507 | UINT64_C(369107099), // PM2WADD_HX |
| 1508 | UINT64_C(1308631195), // PM2WSUBA_H |
| 1509 | UINT64_C(1577066651), // PM2WSUBA_HX |
| 1510 | UINT64_C(1174413467), // PM2WSUB_H |
| 1511 | UINT64_C(1442848923), // PM2WSUB_HX |
| 1512 | UINT64_C(3959443515), // PM4ADDASU_B |
| 1513 | UINT64_C(3992997947), // PM4ADDASU_H |
| 1514 | UINT64_C(2885701691), // PM4ADDAU_B |
| 1515 | UINT64_C(2919256123), // PM4ADDAU_H |
| 1516 | UINT64_C(2348830779), // PM4ADDA_B |
| 1517 | UINT64_C(2382385211), // PM4ADDA_H |
| 1518 | UINT64_C(3825225787), // PM4ADDSU_B |
| 1519 | UINT64_C(3858780219), // PM4ADDSU_H |
| 1520 | UINT64_C(2751483963), // PM4ADDU_B |
| 1521 | UINT64_C(2785038395), // PM4ADDU_H |
| 1522 | UINT64_C(2214613051), // PM4ADD_B |
| 1523 | UINT64_C(2248167483), // PM4ADD_H |
| 1524 | UINT64_C(3925880891), // PMACCSU_W_H00 |
| 1525 | UINT64_C(4194316347), // PMACCSU_W_H11 |
| 1526 | UINT64_C(2852139067), // PMACCU_W_H00 |
| 1527 | UINT64_C(3120566331), // PMACCU_W_H01 |
| 1528 | UINT64_C(3120574523), // PMACCU_W_H11 |
| 1529 | UINT64_C(2315268155), // PMACC_W_H00 |
| 1530 | UINT64_C(2583695419), // PMACC_W_H01 |
| 1531 | UINT64_C(2583703611), // PMACC_W_H11 |
| 1532 | UINT64_C(4227883067), // PMAXU_B |
| 1533 | UINT64_C(4228964379), // PMAXU_DB |
| 1534 | UINT64_C(4161855515), // PMAXU_DH |
| 1535 | UINT64_C(4195409947), // PMAXU_DW |
| 1536 | UINT64_C(4160774203), // PMAXU_H |
| 1537 | UINT64_C(4194328635), // PMAXU_W |
| 1538 | UINT64_C(4093665339), // PMAX_B |
| 1539 | UINT64_C(4094746651), // PMAX_DB |
| 1540 | UINT64_C(4027637787), // PMAX_DH |
| 1541 | UINT64_C(4061192219), // PMAX_DW |
| 1542 | UINT64_C(4026556475), // PMAX_H |
| 1543 | UINT64_C(4060110907), // PMAX_W |
| 1544 | UINT64_C(3355471931), // PMHACCSU_H |
| 1545 | UINT64_C(2885709883), // PMHACCSU_H_B0 |
| 1546 | UINT64_C(3154145339), // PMHACCSU_H_B1 |
| 1547 | UINT64_C(3389026363), // PMHACCSU_W |
| 1548 | UINT64_C(2919264315), // PMHACCSU_W_H0 |
| 1549 | UINT64_C(3187699771), // PMHACCSU_W_H1 |
| 1550 | UINT64_C(2550165563), // PMHACCU_H |
| 1551 | UINT64_C(2583719995), // PMHACCU_W |
| 1552 | UINT64_C(2281730107), // PMHACC_H |
| 1553 | UINT64_C(2818601019), // PMHACC_H_B0 |
| 1554 | UINT64_C(3087036475), // PMHACC_H_B1 |
| 1555 | UINT64_C(2315284539), // PMHACC_W |
| 1556 | UINT64_C(2852155451), // PMHACC_W_H0 |
| 1557 | UINT64_C(3120590907), // PMHACC_W_H1 |
| 1558 | UINT64_C(3422580795), // PMHRACCSU_H |
| 1559 | UINT64_C(3456135227), // PMHRACCSU_W |
| 1560 | UINT64_C(2617274427), // PMHRACCU_H |
| 1561 | UINT64_C(2650828859), // PMHRACCU_W |
| 1562 | UINT64_C(2348838971), // PMHRACC_H |
| 1563 | UINT64_C(2382393403), // PMHRACC_W |
| 1564 | UINT64_C(3959447611), // PMINU_B |
| 1565 | UINT64_C(3960528923), // PMINU_DB |
| 1566 | UINT64_C(3893420059), // PMINU_DH |
| 1567 | UINT64_C(3926974491), // PMINU_DW |
| 1568 | UINT64_C(3892338747), // PMINU_H |
| 1569 | UINT64_C(3925893179), // PMINU_W |
| 1570 | UINT64_C(3825229883), // PMIN_B |
| 1571 | UINT64_C(3826311195), // PMIN_DB |
| 1572 | UINT64_C(3759202331), // PMIN_DH |
| 1573 | UINT64_C(3792756763), // PMIN_DW |
| 1574 | UINT64_C(3758121019), // PMIN_H |
| 1575 | UINT64_C(3791675451), // PMIN_W |
| 1576 | UINT64_C(3087028283), // PMQ2ADDA_H |
| 1577 | UINT64_C(3120582715), // PMQ2ADDA_W |
| 1578 | UINT64_C(2952810555), // PMQ2ADD_H |
| 1579 | UINT64_C(2986364987), // PMQ2ADD_W |
| 1580 | UINT64_C(3892342843), // PMQACC_W_H00 |
| 1581 | UINT64_C(4160770107), // PMQACC_W_H01 |
| 1582 | UINT64_C(4160778299), // PMQACC_W_H11 |
| 1583 | UINT64_C(3154137147), // PMQR2ADDA_H |
| 1584 | UINT64_C(3187691579), // PMQR2ADDA_W |
| 1585 | UINT64_C(3019919419), // PMQR2ADD_H |
| 1586 | UINT64_C(3053473851), // PMQR2ADD_W |
| 1587 | UINT64_C(3959451707), // PMQRACC_W_H00 |
| 1588 | UINT64_C(4227878971), // PMQRACC_W_H01 |
| 1589 | UINT64_C(4227887163), // PMQRACC_W_H11 |
| 1590 | UINT64_C(2080383131), // PMQRWACC_H |
| 1591 | UINT64_C(2013274267), // PMQWACC_H |
| 1592 | UINT64_C(3288358971), // PMSEQ_B |
| 1593 | UINT64_C(3289440283), // PMSEQ_DB |
| 1594 | UINT64_C(3222331419), // PMSEQ_DH |
| 1595 | UINT64_C(3255885851), // PMSEQ_DW |
| 1596 | UINT64_C(3221250107), // PMSEQ_H |
| 1597 | UINT64_C(3254804539), // PMSEQ_W |
| 1598 | UINT64_C(3691012155), // PMSLTU_B |
| 1599 | UINT64_C(3692093467), // PMSLTU_DB |
| 1600 | UINT64_C(3624984603), // PMSLTU_DH |
| 1601 | UINT64_C(3658539035), // PMSLTU_DW |
| 1602 | UINT64_C(3623903291), // PMSLTU_H |
| 1603 | UINT64_C(3657457723), // PMSLTU_W |
| 1604 | UINT64_C(3556794427), // PMSLT_B |
| 1605 | UINT64_C(3557875739), // PMSLT_DB |
| 1606 | UINT64_C(3490766875), // PMSLT_DH |
| 1607 | UINT64_C(3524321307), // PMSLT_DW |
| 1608 | UINT64_C(3489685563), // PMSLT_H |
| 1609 | UINT64_C(3523239995), // PMSLT_W |
| 1610 | UINT64_C(3288363067), // PMULHRSU_H |
| 1611 | UINT64_C(3321917499), // PMULHRSU_W |
| 1612 | UINT64_C(2483056699), // PMULHRU_H |
| 1613 | UINT64_C(2516611131), // PMULHRU_W |
| 1614 | UINT64_C(2214621243), // PMULHR_H |
| 1615 | UINT64_C(2248175675), // PMULHR_W |
| 1616 | UINT64_C(3221254203), // PMULHSU_H |
| 1617 | UINT64_C(2751492155), // PMULHSU_H_B0 |
| 1618 | UINT64_C(3019927611), // PMULHSU_H_B1 |
| 1619 | UINT64_C(3254808635), // PMULHSU_W |
| 1620 | UINT64_C(2785046587), // PMULHSU_W_H0 |
| 1621 | UINT64_C(3053482043), // PMULHSU_W_H1 |
| 1622 | UINT64_C(2415947835), // PMULHU_H |
| 1623 | UINT64_C(2449502267), // PMULHU_W |
| 1624 | UINT64_C(2147512379), // PMULH_H |
| 1625 | UINT64_C(2684383291), // PMULH_H_B0 |
| 1626 | UINT64_C(2952818747), // PMULH_H_B1 |
| 1627 | UINT64_C(2181066811), // PMULH_W |
| 1628 | UINT64_C(2717937723), // PMULH_W_H0 |
| 1629 | UINT64_C(2986373179), // PMULH_W_H1 |
| 1630 | UINT64_C(3556798523), // PMULQR_H |
| 1631 | UINT64_C(3590352955), // PMULQR_W |
| 1632 | UINT64_C(3489689659), // PMULQ_H |
| 1633 | UINT64_C(3523244091), // PMULQ_W |
| 1634 | UINT64_C(3758108731), // PMULSU_H_B00 |
| 1635 | UINT64_C(4026544187), // PMULSU_H_B11 |
| 1636 | UINT64_C(3791663163), // PMULSU_W_H00 |
| 1637 | UINT64_C(4060098619), // PMULSU_W_H11 |
| 1638 | UINT64_C(2684366907), // PMULU_H_B00 |
| 1639 | UINT64_C(2952794171), // PMULU_H_B01 |
| 1640 | UINT64_C(2952802363), // PMULU_H_B11 |
| 1641 | UINT64_C(2717921339), // PMULU_W_H00 |
| 1642 | UINT64_C(2986348603), // PMULU_W_H01 |
| 1643 | UINT64_C(2986356795), // PMULU_W_H11 |
| 1644 | UINT64_C(2147495995), // PMUL_H_B00 |
| 1645 | UINT64_C(2415923259), // PMUL_H_B01 |
| 1646 | UINT64_C(2415931451), // PMUL_H_B11 |
| 1647 | UINT64_C(2181050427), // PMUL_W_H00 |
| 1648 | UINT64_C(2449477691), // PMUL_W_H01 |
| 1649 | UINT64_C(2449485883), // PMUL_W_H11 |
| 1650 | UINT64_C(553697307), // PNCLIPIU_B |
| 1651 | UINT64_C(570474523), // PNCLIPIU_H |
| 1652 | UINT64_C(1627439131), // PNCLIPI_B |
| 1653 | UINT64_C(1644216347), // PNCLIPI_H |
| 1654 | UINT64_C(822132763), // PNCLIPRIU_B |
| 1655 | UINT64_C(838909979), // PNCLIPRIU_H |
| 1656 | UINT64_C(1895874587), // PNCLIPRI_B |
| 1657 | UINT64_C(1912651803), // PNCLIPRI_H |
| 1658 | UINT64_C(939573275), // PNCLIPRU_BS |
| 1659 | UINT64_C(973127707), // PNCLIPRU_HS |
| 1660 | UINT64_C(2013315099), // PNCLIPR_BS |
| 1661 | UINT64_C(2046869531), // PNCLIPR_HS |
| 1662 | UINT64_C(671137819), // PNCLIPU_BS |
| 1663 | UINT64_C(704692251), // PNCLIPU_HS |
| 1664 | UINT64_C(1744879643), // PNCLIP_BS |
| 1665 | UINT64_C(1778434075), // PNCLIP_HS |
| 1666 | UINT64_C(1090568219), // PNSRAI_B |
| 1667 | UINT64_C(1107345435), // PNSRAI_H |
| 1668 | UINT64_C(1359003675), // PNSRARI_B |
| 1669 | UINT64_C(1375780891), // PNSRARI_H |
| 1670 | UINT64_C(1476444187), // PNSRAR_BS |
| 1671 | UINT64_C(1509998619), // PNSRAR_HS |
| 1672 | UINT64_C(1208008731), // PNSRA_BS |
| 1673 | UINT64_C(1241563163), // PNSRA_HS |
| 1674 | UINT64_C(16826395), // PNSRLI_B |
| 1675 | UINT64_C(33603611), // PNSRLI_H |
| 1676 | UINT64_C(134266907), // PNSRL_BS |
| 1677 | UINT64_C(167821339), // PNSRL_HS |
| 1678 | UINT64_C(2415935547), // PPAIREO_B |
| 1679 | UINT64_C(2415976475), // PPAIREO_DB |
| 1680 | UINT64_C(2449530907), // PPAIREO_DH |
| 1681 | UINT64_C(2449489979), // PPAIREO_H |
| 1682 | UINT64_C(2516598843), // PPAIREO_W |
| 1683 | UINT64_C(2147500091), // PPAIRE_B |
| 1684 | UINT64_C(2147541019), // PPAIRE_DB |
| 1685 | UINT64_C(2181095451), // PPAIRE_DH |
| 1686 | UINT64_C(2181054523), // PPAIRE_H |
| 1687 | UINT64_C(2684371003), // PPAIROE_B |
| 1688 | UINT64_C(2684411931), // PPAIROE_DB |
| 1689 | UINT64_C(2717966363), // PPAIROE_DH |
| 1690 | UINT64_C(2717925435), // PPAIROE_H |
| 1691 | UINT64_C(2785034299), // PPAIROE_W |
| 1692 | UINT64_C(2952806459), // PPAIRO_B |
| 1693 | UINT64_C(2952847387), // PPAIRO_DB |
| 1694 | UINT64_C(2986401819), // PPAIRO_DH |
| 1695 | UINT64_C(2986360891), // PPAIRO_H |
| 1696 | UINT64_C(3053469755), // PPAIRO_W |
| 1697 | UINT64_C(3154133019), // PREDSUMU_BS |
| 1698 | UINT64_C(1006649371), // PREDSUMU_DBS |
| 1699 | UINT64_C(939540507), // PREDSUMU_DHS |
| 1700 | UINT64_C(3087024155), // PREDSUMU_HS |
| 1701 | UINT64_C(3120578587), // PREDSUMU_WS |
| 1702 | UINT64_C(2617262107), // PREDSUM_BS |
| 1703 | UINT64_C(469778459), // PREDSUM_DBS |
| 1704 | UINT64_C(402669595), // PREDSUM_DHS |
| 1705 | UINT64_C(2550153243), // PREDSUM_HS |
| 1706 | UINT64_C(2583707675), // PREDSUM_WS |
| 1707 | UINT64_C(24595), // PREFETCH_I |
| 1708 | UINT64_C(1073171), // PREFETCH_R |
| 1709 | UINT64_C(3170323), // PREFETCH_W |
| 1710 | UINT64_C(3832553499), // PSABS_B |
| 1711 | UINT64_C(1685086235), // PSABS_DB |
| 1712 | UINT64_C(1617977371), // PSABS_DH |
| 1713 | UINT64_C(3765444635), // PSABS_H |
| 1714 | UINT64_C(3019898939), // PSADDU_B |
| 1715 | UINT64_C(3019923483), // PSADDU_DB |
| 1716 | UINT64_C(2952814619), // PSADDU_DH |
| 1717 | UINT64_C(2986369051), // PSADDU_DW |
| 1718 | UINT64_C(2952790075), // PSADDU_H |
| 1719 | UINT64_C(2986344507), // PSADDU_W |
| 1720 | UINT64_C(2483028027), // PSADD_B |
| 1721 | UINT64_C(2483052571), // PSADD_DB |
| 1722 | UINT64_C(2415943707), // PSADD_DH |
| 1723 | UINT64_C(2449498139), // PSADD_DW |
| 1724 | UINT64_C(2415919163), // PSADD_H |
| 1725 | UINT64_C(2449473595), // PSADD_W |
| 1726 | UINT64_C(2417025051), // PSAS_DHX |
| 1727 | UINT64_C(2415943739), // PSAS_HX |
| 1728 | UINT64_C(2449498171), // PSAS_WX |
| 1729 | UINT64_C(1627447323), // PSATI_DH |
| 1730 | UINT64_C(1644224539), // PSATI_DW |
| 1731 | UINT64_C(3774890011), // PSATI_H |
| 1732 | UINT64_C(3791667227), // PSATI_W |
| 1733 | UINT64_C(2215698459), // PSA_DHX |
| 1734 | UINT64_C(2214617147), // PSA_HX |
| 1735 | UINT64_C(2248171579), // PSA_WX |
| 1736 | UINT64_C(1614831643), // PSEXT_DH_B |
| 1737 | UINT64_C(1648386075), // PSEXT_DW_B |
| 1738 | UINT64_C(1649434651), // PSEXT_DW_H |
| 1739 | UINT64_C(3762298907), // PSEXT_H_B |
| 1740 | UINT64_C(3795853339), // PSEXT_W_B |
| 1741 | UINT64_C(3796901915), // PSEXT_W_H |
| 1742 | UINT64_C(2685427739), // PSH1ADD_DH |
| 1743 | UINT64_C(2718982171), // PSH1ADD_DW |
| 1744 | UINT64_C(2684362811), // PSH1ADD_H |
| 1745 | UINT64_C(2717917243), // PSH1ADD_W |
| 1746 | UINT64_C(2155880475), // PSLLI_B |
| 1747 | UINT64_C(8413211), // PSLLI_DB |
| 1748 | UINT64_C(16801819), // PSLLI_DH |
| 1749 | UINT64_C(33579035), // PSLLI_DW |
| 1750 | UINT64_C(2164269083), // PSLLI_H |
| 1751 | UINT64_C(2181046299), // PSLLI_W |
| 1752 | UINT64_C(2348818459), // PSLL_BS |
| 1753 | UINT64_C(201351195), // PSLL_DBS |
| 1754 | UINT64_C(134242331), // PSLL_DHS |
| 1755 | UINT64_C(167796763), // PSLL_DWS |
| 1756 | UINT64_C(2281709595), // PSLL_HS |
| 1757 | UINT64_C(2315264027), // PSLL_WS |
| 1758 | UINT64_C(3229630491), // PSRAI_B |
| 1759 | UINT64_C(1082187803), // PSRAI_DB |
| 1760 | UINT64_C(1090576411), // PSRAI_DH |
| 1761 | UINT64_C(1107353627), // PSRAI_DW |
| 1762 | UINT64_C(3238019099), // PSRAI_H |
| 1763 | UINT64_C(3254796315), // PSRAI_W |
| 1764 | UINT64_C(1359011867), // PSRARI_DH |
| 1765 | UINT64_C(1375789083), // PSRARI_DW |
| 1766 | UINT64_C(3506454555), // PSRARI_H |
| 1767 | UINT64_C(3523231771), // PSRARI_W |
| 1768 | UINT64_C(3422568475), // PSRA_BS |
| 1769 | UINT64_C(1275125787), // PSRA_DBS |
| 1770 | UINT64_C(1208016923), // PSRA_DHS |
| 1771 | UINT64_C(1241571355), // PSRA_DWS |
| 1772 | UINT64_C(3355459611), // PSRA_HS |
| 1773 | UINT64_C(3389014043), // PSRA_WS |
| 1774 | UINT64_C(2155888667), // PSRLI_B |
| 1775 | UINT64_C(8445979), // PSRLI_DB |
| 1776 | UINT64_C(16834587), // PSRLI_DH |
| 1777 | UINT64_C(33611803), // PSRLI_DW |
| 1778 | UINT64_C(2164277275), // PSRLI_H |
| 1779 | UINT64_C(2181054491), // PSRLI_W |
| 1780 | UINT64_C(2348826651), // PSRL_BS |
| 1781 | UINT64_C(201383963), // PSRL_DBS |
| 1782 | UINT64_C(134275099), // PSRL_DHS |
| 1783 | UINT64_C(167829531), // PSRL_DWS |
| 1784 | UINT64_C(2281717787), // PSRL_HS |
| 1785 | UINT64_C(2315272219), // PSRL_WS |
| 1786 | UINT64_C(2484133915), // PSSA_DHX |
| 1787 | UINT64_C(2483052603), // PSSA_HX |
| 1788 | UINT64_C(2516607035), // PSSA_WX |
| 1789 | UINT64_C(2953863195), // PSSH1SADD_DH |
| 1790 | UINT64_C(2987417627), // PSSH1SADD_DW |
| 1791 | UINT64_C(2952798267), // PSSH1SADD_H |
| 1792 | UINT64_C(2986352699), // PSSH1SADD_W |
| 1793 | UINT64_C(2013290523), // PSSHAR_DHS |
| 1794 | UINT64_C(2046844955), // PSSHAR_DWS |
| 1795 | UINT64_C(4160757787), // PSSHAR_HS |
| 1796 | UINT64_C(4194312219), // PSSHAR_WS |
| 1797 | UINT64_C(1744855067), // PSSHA_DHS |
| 1798 | UINT64_C(1778409499), // PSSHA_DWS |
| 1799 | UINT64_C(3892322331), // PSSHA_HS |
| 1800 | UINT64_C(3925876763), // PSSHA_WS |
| 1801 | UINT64_C(1358979099), // PSSLAI_DH |
| 1802 | UINT64_C(1375756315), // PSSLAI_DW |
| 1803 | UINT64_C(3506446363), // PSSLAI_H |
| 1804 | UINT64_C(3523223579), // PSSLAI_W |
| 1805 | UINT64_C(4093640763), // PSSUBU_B |
| 1806 | UINT64_C(4093665307), // PSSUBU_DB |
| 1807 | UINT64_C(4026556443), // PSSUBU_DH |
| 1808 | UINT64_C(4060110875), // PSSUBU_DW |
| 1809 | UINT64_C(4026531899), // PSSUBU_H |
| 1810 | UINT64_C(4060086331), // PSSUBU_W |
| 1811 | UINT64_C(3556769851), // PSSUB_B |
| 1812 | UINT64_C(3556794395), // PSSUB_DB |
| 1813 | UINT64_C(3489685531), // PSSUB_DH |
| 1814 | UINT64_C(3523239963), // PSSUB_DW |
| 1815 | UINT64_C(3489660987), // PSSUB_H |
| 1816 | UINT64_C(3523215419), // PSSUB_W |
| 1817 | UINT64_C(3288334395), // PSUB_B |
| 1818 | UINT64_C(3288358939), // PSUB_DB |
| 1819 | UINT64_C(3221250075), // PSUB_DH |
| 1820 | UINT64_C(3254804507), // PSUB_DW |
| 1821 | UINT64_C(3221225531), // PSUB_H |
| 1822 | UINT64_C(3254779963), // PSUB_W |
| 1823 | UINT64_C(553705499), // PUSATI_DH |
| 1824 | UINT64_C(570482715), // PUSATI_DW |
| 1825 | UINT64_C(2701148187), // PUSATI_H |
| 1826 | UINT64_C(2717925403), // PUSATI_W |
| 1827 | UINT64_C(469770395), // PWADDAU_B |
| 1828 | UINT64_C(402661531), // PWADDAU_H |
| 1829 | UINT64_C(201334939), // PWADDA_B |
| 1830 | UINT64_C(134226075), // PWADDA_H |
| 1831 | UINT64_C(335552667), // PWADDU_B |
| 1832 | UINT64_C(268443803), // PWADDU_H |
| 1833 | UINT64_C(67117211), // PWADD_B |
| 1834 | UINT64_C(8347), // PWADD_H |
| 1835 | UINT64_C(1744838811), // PWMACCSU_H |
| 1836 | UINT64_C(939532443), // PWMACCU_H |
| 1837 | UINT64_C(671096987), // PWMACC_H |
| 1838 | UINT64_C(1677729947), // PWMULSU_B |
| 1839 | UINT64_C(1610621083), // PWMULSU_H |
| 1840 | UINT64_C(872423579), // PWMULU_B |
| 1841 | UINT64_C(805314715), // PWMULU_H |
| 1842 | UINT64_C(603988123), // PWMUL_B |
| 1843 | UINT64_C(536879259), // PWMUL_H |
| 1844 | UINT64_C(1090527259), // PWSLAI_B |
| 1845 | UINT64_C(1107304475), // PWSLAI_H |
| 1846 | UINT64_C(1207967771), // PWSLA_BS |
| 1847 | UINT64_C(1241522203), // PWSLA_HS |
| 1848 | UINT64_C(16785435), // PWSLLI_B |
| 1849 | UINT64_C(33562651), // PWSLLI_H |
| 1850 | UINT64_C(134225947), // PWSLL_BS |
| 1851 | UINT64_C(167780379), // PWSLL_HS |
| 1852 | UINT64_C(1543512219), // PWSUBAU_B |
| 1853 | UINT64_C(1476403355), // PWSUBAU_H |
| 1854 | UINT64_C(1275076763), // PWSUBA_B |
| 1855 | UINT64_C(1207967899), // PWSUBA_H |
| 1856 | UINT64_C(1409294491), // PWSUBU_B |
| 1857 | UINT64_C(1342185627), // PWSUBU_H |
| 1858 | UINT64_C(1140859035), // PWSUB_B |
| 1859 | UINT64_C(1073750171), // PWSUB_H |
| 1860 | UINT64_C(469774347), // QC_ADDSAT |
| 1861 | UINT64_C(503328779), // QC_ADDUSAT |
| 1862 | UINT64_C(123), // QC_BEQI |
| 1863 | UINT64_C(20603), // QC_BGEI |
| 1864 | UINT64_C(28795), // QC_BGEUI |
| 1865 | UINT64_C(16507), // QC_BLTI |
| 1866 | UINT64_C(24699), // QC_BLTUI |
| 1867 | UINT64_C(4219), // QC_BNEI |
| 1868 | UINT64_C(201338891), // QC_BREV32 |
| 1869 | UINT64_C(134230027), // QC_CLO |
| 1870 | UINT64_C(3456106611), // QC_CLRINTI |
| 1871 | UINT64_C(44130), // QC_CM_MVA01S |
| 1872 | UINT64_C(44066), // QC_CM_MVSA01 |
| 1873 | UINT64_C(47618), // QC_CM_POP |
| 1874 | UINT64_C(48642), // QC_CM_POPRET |
| 1875 | UINT64_C(48130), // QC_CM_POPRETZ |
| 1876 | UINT64_C(47106), // QC_CM_PUSH |
| 1877 | UINT64_C(47362), // QC_CM_PUSHFP |
| 1878 | UINT64_C(12299), // QC_COMPRESS2 |
| 1879 | UINT64_C(33566731), // QC_COMPRESS3 |
| 1880 | UINT64_C(2348810355), // QC_CSRRWR |
| 1881 | UINT64_C(2382364787), // QC_CSRRWRI |
| 1882 | UINT64_C(167784459), // QC_CTO |
| 1883 | UINT64_C(36865), // QC_C_BEXTI |
| 1884 | UINT64_C(37889), // QC_C_BSETI |
| 1885 | UINT64_C(4110), // QC_C_CLRINT |
| 1886 | UINT64_C(6930), // QC_C_DI |
| 1887 | UINT64_C(4098), // QC_C_DIR |
| 1888 | UINT64_C(7058), // QC_C_EI |
| 1889 | UINT64_C(4102), // QC_C_EIR |
| 1890 | UINT64_C(4098), // QC_C_EXTU |
| 1891 | UINT64_C(6162), // QC_C_MIENTER |
| 1892 | UINT64_C(6290), // QC_C_MIENTER_NEST |
| 1893 | UINT64_C(6674), // QC_C_MILEAVERET |
| 1894 | UINT64_C(6546), // QC_C_MNRET |
| 1895 | UINT64_C(6418), // QC_C_MRET |
| 1896 | UINT64_C(8194), // QC_C_MULIADD |
| 1897 | UINT64_C(44034), // QC_C_MVEQZ |
| 1898 | UINT64_C(4106), // QC_C_SETINT |
| 1899 | UINT64_C(32769), // QC_C_SYNC |
| 1900 | UINT64_C(33793), // QC_C_SYNCR |
| 1901 | UINT64_C(36865), // QC_C_SYNCWF |
| 1902 | UINT64_C(37889), // QC_C_SYNCWL |
| 1903 | UINT64_C(67121163), // QC_EXPAND2 |
| 1904 | UINT64_C(100675595), // QC_EXPAND3 |
| 1905 | UINT64_C(1073750027), // QC_EXT |
| 1906 | UINT64_C(3221233675), // QC_EXTD |
| 1907 | UINT64_C(268447755), // QC_EXTDPR |
| 1908 | UINT64_C(302002187), // QC_EXTDPRH |
| 1909 | UINT64_C(167784459), // QC_EXTDR |
| 1910 | UINT64_C(2147491851), // QC_EXTDU |
| 1911 | UINT64_C(201338891), // QC_EXTDUPR |
| 1912 | UINT64_C(234893323), // QC_EXTDUPRH |
| 1913 | UINT64_C(134230027), // QC_EXTDUR |
| 1914 | UINT64_C(8203), // QC_EXTU |
| 1915 | UINT64_C(8223), // QC_E_ADDAI |
| 1916 | UINT64_C(2147495967), // QC_E_ADDI |
| 1917 | UINT64_C(40991), // QC_E_ANDAI |
| 1918 | UINT64_C(3221237791), // QC_E_ANDI |
| 1919 | UINT64_C(25182239), // QC_E_BEQI |
| 1920 | UINT64_C(30425119), // QC_E_BGEI |
| 1921 | UINT64_C(32522271), // QC_E_BGEUI |
| 1922 | UINT64_C(29376543), // QC_E_BLTI |
| 1923 | UINT64_C(31473695), // QC_E_BLTUI |
| 1924 | UINT64_C(26230815), // QC_E_BNEI |
| 1925 | UINT64_C(16415), // QC_E_J |
| 1926 | UINT64_C(49183), // QC_E_JAL |
| 1927 | UINT64_C(20511), // QC_E_LB |
| 1928 | UINT64_C(1073762335), // QC_E_LBU |
| 1929 | UINT64_C(2147504159), // QC_E_LH |
| 1930 | UINT64_C(3221245983), // QC_E_LHU |
| 1931 | UINT64_C(31), // QC_E_LI |
| 1932 | UINT64_C(24607), // QC_E_LW |
| 1933 | UINT64_C(36895), // QC_E_ORAI |
| 1934 | UINT64_C(1073754143), // QC_E_ORI |
| 1935 | UINT64_C(1073766431), // QC_E_SB |
| 1936 | UINT64_C(2147508255), // QC_E_SH |
| 1937 | UINT64_C(3221250079), // QC_E_SW |
| 1938 | UINT64_C(4127), // QC_E_XORAI |
| 1939 | UINT64_C(12319), // QC_E_XORI |
| 1940 | UINT64_C(1073745931), // QC_INSB |
| 1941 | UINT64_C(2147487755), // QC_INSBH |
| 1942 | UINT64_C(33566731), // QC_INSBHR |
| 1943 | UINT64_C(4107), // QC_INSBI |
| 1944 | UINT64_C(67121163), // QC_INSBPR |
| 1945 | UINT64_C(100675595), // QC_INSBPRH |
| 1946 | UINT64_C(12299), // QC_INSBR |
| 1947 | UINT64_C(2147483659), // QC_INSBRI |
| 1948 | UINT64_C(20491), // QC_INW |
| 1949 | UINT64_C(27), // QC_LI |
| 1950 | UINT64_C(33554523), // QC_LIEQ |
| 1951 | UINT64_C(100663387), // QC_LIEQI |
| 1952 | UINT64_C(33575003), // QC_LIGE |
| 1953 | UINT64_C(100683867), // QC_LIGEI |
| 1954 | UINT64_C(33583195), // QC_LIGEU |
| 1955 | UINT64_C(100692059), // QC_LIGEUI |
| 1956 | UINT64_C(33570907), // QC_LILT |
| 1957 | UINT64_C(100679771), // QC_LILTI |
| 1958 | UINT64_C(33579099), // QC_LILTU |
| 1959 | UINT64_C(100687963), // QC_LILTUI |
| 1960 | UINT64_C(33558619), // QC_LINE |
| 1961 | UINT64_C(100667483), // QC_LINEI |
| 1962 | UINT64_C(2147512331), // QC_LRB |
| 1963 | UINT64_C(2952818699), // QC_LRBU |
| 1964 | UINT64_C(2415947787), // QC_LRH |
| 1965 | UINT64_C(3221254155), // QC_LRHU |
| 1966 | UINT64_C(2684383243), // QC_LRW |
| 1967 | UINT64_C(28683), // QC_LWM |
| 1968 | UINT64_C(1073770507), // QC_LWMI |
| 1969 | UINT64_C(24587), // QC_MULIADD |
| 1970 | UINT64_C(91), // QC_MVEQ |
| 1971 | UINT64_C(67108955), // QC_MVEQI |
| 1972 | UINT64_C(20571), // QC_MVGE |
| 1973 | UINT64_C(67129435), // QC_MVGEI |
| 1974 | UINT64_C(28763), // QC_MVGEU |
| 1975 | UINT64_C(67137627), // QC_MVGEUI |
| 1976 | UINT64_C(16475), // QC_MVLT |
| 1977 | UINT64_C(67125339), // QC_MVLTI |
| 1978 | UINT64_C(24667), // QC_MVLTU |
| 1979 | UINT64_C(67133531), // QC_MVLTUI |
| 1980 | UINT64_C(4187), // QC_MVNE |
| 1981 | UINT64_C(67113051), // QC_MVNEI |
| 1982 | UINT64_C(234893323), // QC_NORM |
| 1983 | UINT64_C(302002187), // QC_NORMEU |
| 1984 | UINT64_C(268447755), // QC_NORMU |
| 1985 | UINT64_C(16395), // QC_OUTW |
| 1986 | UINT64_C(1073750035), // QC_PPUTCI |
| 1987 | UINT64_C(67117147), // QC_SELECTEQI |
| 1988 | UINT64_C(33562715), // QC_SELECTIEQ |
| 1989 | UINT64_C(100671579), // QC_SELECTIEQI |
| 1990 | UINT64_C(8283), // QC_SELECTIIEQ |
| 1991 | UINT64_C(12379), // QC_SELECTIINE |
| 1992 | UINT64_C(33566811), // QC_SELECTINE |
| 1993 | UINT64_C(100675675), // QC_SELECTINEI |
| 1994 | UINT64_C(67121243), // QC_SELECTNEI |
| 1995 | UINT64_C(3422552179), // QC_SETINTI |
| 1996 | UINT64_C(2147512363), // QC_SETWM |
| 1997 | UINT64_C(3221254187), // QC_SETWMI |
| 1998 | UINT64_C(1073754123), // QC_SHLADD |
| 1999 | UINT64_C(335556619), // QC_SHLSAT |
| 2000 | UINT64_C(402665483), // QC_SHLUSAT |
| 2001 | UINT64_C(3489685547), // QC_SRB |
| 2002 | UINT64_C(3758121003), // QC_SRH |
| 2003 | UINT64_C(4026556459), // QC_SRW |
| 2004 | UINT64_C(536883211), // QC_SUBSAT |
| 2005 | UINT64_C(570437643), // QC_SUBUSAT |
| 2006 | UINT64_C(28715), // QC_SWM |
| 2007 | UINT64_C(1073770539), // QC_SWMI |
| 2008 | UINT64_C(268447763), // QC_SYNC |
| 2009 | UINT64_C(536883219), // QC_SYNCR |
| 2010 | UINT64_C(1073754131), // QC_SYNCWF |
| 2011 | UINT64_C(2147495955), // QC_SYNCWL |
| 2012 | UINT64_C(603992075), // QC_WRAP |
| 2013 | UINT64_C(11), // QC_WRAPI |
| 2014 | UINT64_C(8192), // QK_C_LBU |
| 2015 | UINT64_C(32768), // QK_C_LBUSP |
| 2016 | UINT64_C(8194), // QK_C_LHU |
| 2017 | UINT64_C(32800), // QK_C_LHUSP |
| 2018 | UINT64_C(40960), // QK_C_SB |
| 2019 | UINT64_C(32832), // QK_C_SBSP |
| 2020 | UINT64_C(40962), // QK_C_SH |
| 2021 | UINT64_C(32864), // QK_C_SHSP |
| 2022 | UINT64_C(33579059), // REM |
| 2023 | UINT64_C(33583155), // REMU |
| 2024 | UINT64_C(33583163), // REMUW |
| 2025 | UINT64_C(33579067), // REMW |
| 2026 | UINT64_C(1795182611), // REV16 |
| 2027 | UINT64_C(1770016787), // REV8_RV32 |
| 2028 | UINT64_C(1803571219), // REV8_RV64 |
| 2029 | UINT64_C(1777356819), // REV_RV32 |
| 2030 | UINT64_C(1810911251), // REV_RV64 |
| 2031 | UINT64_C(1577066587), // RI_VEXTRACT |
| 2032 | UINT64_C(1073766491), // RI_VINSERT |
| 2033 | UINT64_C(536871003), // RI_VUNZIP2A_VV |
| 2034 | UINT64_C(1610612827), // RI_VUNZIP2B_VV |
| 2035 | UINT64_C(28763), // RI_VZERO |
| 2036 | UINT64_C(268435547), // RI_VZIP2A_VV |
| 2037 | UINT64_C(1342177371), // RI_VZIP2B_VV |
| 2038 | UINT64_C(805306459), // RI_VZIPEVEN_VV |
| 2039 | UINT64_C(1879048283), // RI_VZIPODD_VV |
| 2040 | UINT64_C(1610616883), // ROL |
| 2041 | UINT64_C(1610616891), // ROLW |
| 2042 | UINT64_C(1610633267), // ROR |
| 2043 | UINT64_C(1610633235), // RORI |
| 2044 | UINT64_C(1610633243), // RORIW |
| 2045 | UINT64_C(1610633275), // RORW |
| 2046 | UINT64_C(2449473595), // SADD |
| 2047 | UINT64_C(2986344507), // SADDU |
| 2048 | UINT64_C(3791667227), // SATI_RV32 |
| 2049 | UINT64_C(3825221659), // SATI_RV64 |
| 2050 | UINT64_C(35), // SB |
| 2051 | UINT64_C(1040187439), // SB_AQRL |
| 2052 | UINT64_C(973078575), // SB_RL |
| 2053 | UINT64_C(272629875), // SCTRCLR |
| 2054 | UINT64_C(402665519), // SC_D |
| 2055 | UINT64_C(469774383), // SC_D_AQ |
| 2056 | UINT64_C(503328815), // SC_D_AQRL |
| 2057 | UINT64_C(436219951), // SC_D_RL |
| 2058 | UINT64_C(402661423), // SC_W |
| 2059 | UINT64_C(469770287), // SC_W_AQ |
| 2060 | UINT64_C(503324719), // SC_W_AQRL |
| 2061 | UINT64_C(436215855), // SC_W_RL |
| 2062 | UINT64_C(12323), // SD |
| 2063 | UINT64_C(1040199727), // SD_AQRL |
| 2064 | UINT64_C(973090863), // SD_RL |
| 2065 | UINT64_C(12323), // SD_RV32 |
| 2066 | UINT64_C(1614811155), // SEXT_B |
| 2067 | UINT64_C(1615859731), // SEXT_H |
| 2068 | UINT64_C(403701875), // SFENCE_INVAL_IR |
| 2069 | UINT64_C(301990003), // SFENCE_VMA |
| 2070 | UINT64_C(402653299), // SFENCE_W_INVAL |
| 2071 | UINT64_C(4229955699), // SF_CDISCARD_D_L1 |
| 2072 | UINT64_C(810549363), // SF_CEASE |
| 2073 | UINT64_C(4227858547), // SF_CFLUSH_D_L1 |
| 2074 | UINT64_C(4261417207), // SF_MM_E4M3_E4M3 |
| 2075 | UINT64_C(4261417079), // SF_MM_E4M3_E5M2 |
| 2076 | UINT64_C(4194308343), // SF_MM_E5M2_E4M3 |
| 2077 | UINT64_C(4194308215), // SF_MM_E5M2_E5M2 |
| 2078 | UINT64_C(4060090487), // SF_MM_F_F |
| 2079 | UINT64_C(4127195383), // SF_MM_S_S |
| 2080 | UINT64_C(4127195255), // SF_MM_S_U |
| 2081 | UINT64_C(4060086519), // SF_MM_U_S |
| 2082 | UINT64_C(4060086391), // SF_MM_U_U |
| 2083 | UINT64_C(704663643), // SF_VC_FV |
| 2084 | UINT64_C(2852147291), // SF_VC_FVV |
| 2085 | UINT64_C(4194324571), // SF_VC_FVW |
| 2086 | UINT64_C(33566811), // SF_VC_I |
| 2087 | UINT64_C(570437723), // SF_VC_IV |
| 2088 | UINT64_C(2717921371), // SF_VC_IVV |
| 2089 | UINT64_C(4060098651), // SF_VC_IVW |
| 2090 | UINT64_C(570425435), // SF_VC_VV |
| 2091 | UINT64_C(2717909083), // SF_VC_VVV |
| 2092 | UINT64_C(4060086363), // SF_VC_VVW |
| 2093 | UINT64_C(671109211), // SF_VC_V_FV |
| 2094 | UINT64_C(2818592859), // SF_VC_V_FVV |
| 2095 | UINT64_C(4160770139), // SF_VC_V_FVW |
| 2096 | UINT64_C(12379), // SF_VC_V_I |
| 2097 | UINT64_C(536883291), // SF_VC_V_IV |
| 2098 | UINT64_C(2684366939), // SF_VC_V_IVV |
| 2099 | UINT64_C(4026544219), // SF_VC_V_IVW |
| 2100 | UINT64_C(536871003), // SF_VC_V_VV |
| 2101 | UINT64_C(2684354651), // SF_VC_V_VVV |
| 2102 | UINT64_C(4026531931), // SF_VC_V_VVW |
| 2103 | UINT64_C(16475), // SF_VC_V_X |
| 2104 | UINT64_C(536887387), // SF_VC_V_XV |
| 2105 | UINT64_C(2684371035), // SF_VC_V_XVV |
| 2106 | UINT64_C(4026548315), // SF_VC_V_XVW |
| 2107 | UINT64_C(33570907), // SF_VC_X |
| 2108 | UINT64_C(570441819), // SF_VC_XV |
| 2109 | UINT64_C(2717925467), // SF_VC_XVV |
| 2110 | UINT64_C(4060102747), // SF_VC_XVW |
| 2111 | UINT64_C(1275269207), // SF_VFEXPA_V |
| 2112 | UINT64_C(1275301975), // SF_VFEXP_V |
| 2113 | UINT64_C(2281721947), // SF_VFNRCLIP_XU_F_QF |
| 2114 | UINT64_C(2348830811), // SF_VFNRCLIP_X_F_QF |
| 2115 | UINT64_C(4060090459), // SF_VFWMACC_4x4x4 |
| 2116 | UINT64_C(838889479), // SF_VLTE16 |
| 2117 | UINT64_C(1375760391), // SF_VLTE32 |
| 2118 | UINT64_C(1912631303), // SF_VLTE64 |
| 2119 | UINT64_C(302018567), // SF_VLTE8 |
| 2120 | UINT64_C(3187679323), // SF_VQMACCSU_2x8x2 |
| 2121 | UINT64_C(4261421147), // SF_VQMACCSU_4x8x4 |
| 2122 | UINT64_C(3120570459), // SF_VQMACCUS_2x8x2 |
| 2123 | UINT64_C(4194312283), // SF_VQMACCUS_4x8x4 |
| 2124 | UINT64_C(2986352731), // SF_VQMACCU_2x8x2 |
| 2125 | UINT64_C(4060094555), // SF_VQMACCU_4x8x4 |
| 2126 | UINT64_C(3053461595), // SF_VQMACC_2x8x2 |
| 2127 | UINT64_C(4127203419), // SF_VQMACC_4x8x4 |
| 2128 | UINT64_C(2216718423), // SF_VSETTK |
| 2129 | UINT64_C(2215669847), // SF_VSETTM |
| 2130 | UINT64_C(2214621271), // SF_VSETTN |
| 2131 | UINT64_C(838889511), // SF_VSTE16 |
| 2132 | UINT64_C(1375760423), // SF_VSTE32 |
| 2133 | UINT64_C(1912631335), // SF_VSTE64 |
| 2134 | UINT64_C(302018599), // SF_VSTE8 |
| 2135 | UINT64_C(1136681047), // SF_VTDISCARD |
| 2136 | UINT64_C(1577082967), // SF_VTMV_T_V |
| 2137 | UINT64_C(1139826775), // SF_VTMV_V_T |
| 2138 | UINT64_C(1138778199), // SF_VTZERO_T |
| 2139 | UINT64_C(4131), // SH |
| 2140 | UINT64_C(536879155), // SH1ADD |
| 2141 | UINT64_C(536879163), // SH1ADD_UW |
| 2142 | UINT64_C(536887347), // SH2ADD |
| 2143 | UINT64_C(536887355), // SH2ADD_UW |
| 2144 | UINT64_C(536895539), // SH3ADD |
| 2145 | UINT64_C(536895547), // SH3ADD_UW |
| 2146 | UINT64_C(3992985627), // SHA |
| 2147 | UINT64_C(270536723), // SHA256SIG0 |
| 2148 | UINT64_C(271585299), // SHA256SIG1 |
| 2149 | UINT64_C(268439571), // SHA256SUM0 |
| 2150 | UINT64_C(269488147), // SHA256SUM1 |
| 2151 | UINT64_C(274731027), // SHA512SIG0 |
| 2152 | UINT64_C(1543503923), // SHA512SIG0H |
| 2153 | UINT64_C(1409286195), // SHA512SIG0L |
| 2154 | UINT64_C(275779603), // SHA512SIG1 |
| 2155 | UINT64_C(1577058355), // SHA512SIG1H |
| 2156 | UINT64_C(1442840627), // SHA512SIG1L |
| 2157 | UINT64_C(272633875), // SHA512SUM0 |
| 2158 | UINT64_C(1342177331), // SHA512SUM0R |
| 2159 | UINT64_C(273682451), // SHA512SUM1 |
| 2160 | UINT64_C(1375731763), // SHA512SUM1R |
| 2161 | UINT64_C(4261421083), // SHAR |
| 2162 | UINT64_C(1040191535), // SH_AQRL |
| 2163 | UINT64_C(4131), // SH_INX |
| 2164 | UINT64_C(973082671), // SH_RL |
| 2165 | UINT64_C(369098867), // SINVAL_VMA |
| 2166 | UINT64_C(4147), // SLL |
| 2167 | UINT64_C(4115), // SLLI |
| 2168 | UINT64_C(4123), // SLLIW |
| 2169 | UINT64_C(134221851), // SLLI_UW |
| 2170 | UINT64_C(4155), // SLLW |
| 2171 | UINT64_C(8243), // SLT |
| 2172 | UINT64_C(8211), // SLTI |
| 2173 | UINT64_C(12307), // SLTIU |
| 2174 | UINT64_C(12339), // SLTU |
| 2175 | UINT64_C(2382368827), // SLX |
| 2176 | UINT64_C(276828179), // SM3P0 |
| 2177 | UINT64_C(277876755), // SM3P1 |
| 2178 | UINT64_C(805306419), // SM4ED |
| 2179 | UINT64_C(872415283), // SM4KS |
| 2180 | UINT64_C(3791663147), // SMT_VMADOT |
| 2181 | UINT64_C(3858772011), // SMT_VMADOT1 |
| 2182 | UINT64_C(3858767915), // SMT_VMADOT1SU |
| 2183 | UINT64_C(3858759723), // SMT_VMADOT1U |
| 2184 | UINT64_C(3858763819), // SMT_VMADOT1US |
| 2185 | UINT64_C(3858788395), // SMT_VMADOT2 |
| 2186 | UINT64_C(3858784299), // SMT_VMADOT2SU |
| 2187 | UINT64_C(3858776107), // SMT_VMADOT2U |
| 2188 | UINT64_C(3858780203), // SMT_VMADOT2US |
| 2189 | UINT64_C(3858804779), // SMT_VMADOT3 |
| 2190 | UINT64_C(3858800683), // SMT_VMADOT3SU |
| 2191 | UINT64_C(3858792491), // SMT_VMADOT3U |
| 2192 | UINT64_C(3858796587), // SMT_VMADOT3US |
| 2193 | UINT64_C(3791659051), // SMT_VMADOTSU |
| 2194 | UINT64_C(3791650859), // SMT_VMADOTU |
| 2195 | UINT64_C(3791654955), // SMT_VMADOTUS |
| 2196 | UINT64_C(1073762355), // SRA |
| 2197 | UINT64_C(1073762323), // SRAI |
| 2198 | UINT64_C(1073762331), // SRAIW |
| 2199 | UINT64_C(3523231771), // SRARI_RV32 |
| 2200 | UINT64_C(3556786203), // SRARI_RV64 |
| 2201 | UINT64_C(1073762363), // SRAW |
| 2202 | UINT64_C(270532723), // SRET |
| 2203 | UINT64_C(20531), // SRL |
| 2204 | UINT64_C(20499), // SRLI |
| 2205 | UINT64_C(20507), // SRLIW |
| 2206 | UINT64_C(20539), // SRLW |
| 2207 | UINT64_C(2919239739), // SRX |
| 2208 | UINT64_C(1207971887), // SSAMOSWAP_D |
| 2209 | UINT64_C(1275080751), // SSAMOSWAP_D_AQ |
| 2210 | UINT64_C(1308635183), // SSAMOSWAP_D_AQRL |
| 2211 | UINT64_C(1241526319), // SSAMOSWAP_D_RL |
| 2212 | UINT64_C(1207967791), // SSAMOSWAP_W |
| 2213 | UINT64_C(1275076655), // SSAMOSWAP_W_AQ |
| 2214 | UINT64_C(1308631087), // SSAMOSWAP_W_AQRL |
| 2215 | UINT64_C(1241522223), // SSAMOSWAP_W_RL |
| 2216 | UINT64_C(2986352699), // SSH1SADD |
| 2217 | UINT64_C(3925876763), // SSHA |
| 2218 | UINT64_C(4194312219), // SSHAR |
| 2219 | UINT64_C(3523223579), // SSLAI |
| 2220 | UINT64_C(3451928691), // SSPOPCHK |
| 2221 | UINT64_C(3456122995), // SSPUSH |
| 2222 | UINT64_C(3451928691), // SSRDP |
| 2223 | UINT64_C(3523215419), // SSUB |
| 2224 | UINT64_C(4060086331), // SSUBU |
| 2225 | UINT64_C(1073741875), // SUB |
| 2226 | UINT64_C(3321913371), // SUBD |
| 2227 | UINT64_C(1073741883), // SUBW |
| 2228 | UINT64_C(8227), // SW |
| 2229 | UINT64_C(1040195631), // SW_AQRL |
| 2230 | UINT64_C(8227), // SW_INX |
| 2231 | UINT64_C(973086767), // SW_RL |
| 2232 | UINT64_C(4107), // TH_ADDSL |
| 2233 | UINT64_C(1048587), // TH_DCACHE_CALL |
| 2234 | UINT64_C(3145739), // TH_DCACHE_CIALL |
| 2235 | UINT64_C(45088779), // TH_DCACHE_CIPA |
| 2236 | UINT64_C(36700171), // TH_DCACHE_CISW |
| 2237 | UINT64_C(40894475), // TH_DCACHE_CIVA |
| 2238 | UINT64_C(42991627), // TH_DCACHE_CPA |
| 2239 | UINT64_C(41943051), // TH_DCACHE_CPAL1 |
| 2240 | UINT64_C(34603019), // TH_DCACHE_CSW |
| 2241 | UINT64_C(38797323), // TH_DCACHE_CVA |
| 2242 | UINT64_C(37748747), // TH_DCACHE_CVAL1 |
| 2243 | UINT64_C(2097163), // TH_DCACHE_IALL |
| 2244 | UINT64_C(44040203), // TH_DCACHE_IPA |
| 2245 | UINT64_C(35651595), // TH_DCACHE_ISW |
| 2246 | UINT64_C(39845899), // TH_DCACHE_IVA |
| 2247 | UINT64_C(8203), // TH_EXT |
| 2248 | UINT64_C(12299), // TH_EXTU |
| 2249 | UINT64_C(2214596619), // TH_FF0 |
| 2250 | UINT64_C(2248151051), // TH_FF1 |
| 2251 | UINT64_C(1610637323), // TH_FLRD |
| 2252 | UINT64_C(1073766411), // TH_FLRW |
| 2253 | UINT64_C(1879072779), // TH_FLURD |
| 2254 | UINT64_C(1342201867), // TH_FLURW |
| 2255 | UINT64_C(1610641419), // TH_FSRD |
| 2256 | UINT64_C(1073770507), // TH_FSRW |
| 2257 | UINT64_C(1879076875), // TH_FSURD |
| 2258 | UINT64_C(1342205963), // TH_FSURW |
| 2259 | UINT64_C(16777227), // TH_ICACHE_IALL |
| 2260 | UINT64_C(17825803), // TH_ICACHE_IALLS |
| 2261 | UINT64_C(58720267), // TH_ICACHE_IPA |
| 2262 | UINT64_C(50331659), // TH_ICACHE_IVA |
| 2263 | UINT64_C(22020107), // TH_L2CACHE_CALL |
| 2264 | UINT64_C(24117259), // TH_L2CACHE_CIALL |
| 2265 | UINT64_C(23068683), // TH_L2CACHE_IALL |
| 2266 | UINT64_C(402669579), // TH_LBIA |
| 2267 | UINT64_C(134234123), // TH_LBIB |
| 2268 | UINT64_C(2550153227), // TH_LBUIA |
| 2269 | UINT64_C(2281717771), // TH_LBUIB |
| 2270 | UINT64_C(4160765963), // TH_LDD |
| 2271 | UINT64_C(2013282315), // TH_LDIA |
| 2272 | UINT64_C(1744846859), // TH_LDIB |
| 2273 | UINT64_C(939540491), // TH_LHIA |
| 2274 | UINT64_C(671105035), // TH_LHIB |
| 2275 | UINT64_C(3087024139), // TH_LHUIA |
| 2276 | UINT64_C(2818588683), // TH_LHUIB |
| 2277 | UINT64_C(16395), // TH_LRB |
| 2278 | UINT64_C(2147500043), // TH_LRBU |
| 2279 | UINT64_C(1610629131), // TH_LRD |
| 2280 | UINT64_C(536887307), // TH_LRH |
| 2281 | UINT64_C(2684370955), // TH_LRHU |
| 2282 | UINT64_C(1073758219), // TH_LRW |
| 2283 | UINT64_C(3221241867), // TH_LRWU |
| 2284 | UINT64_C(268451851), // TH_LURB |
| 2285 | UINT64_C(2415935499), // TH_LURBU |
| 2286 | UINT64_C(1879064587), // TH_LURD |
| 2287 | UINT64_C(805322763), // TH_LURH |
| 2288 | UINT64_C(2952806411), // TH_LURHU |
| 2289 | UINT64_C(1342193675), // TH_LURW |
| 2290 | UINT64_C(3489677323), // TH_LURWU |
| 2291 | UINT64_C(3758112779), // TH_LWD |
| 2292 | UINT64_C(1476411403), // TH_LWIA |
| 2293 | UINT64_C(1207975947), // TH_LWIB |
| 2294 | UINT64_C(4026548235), // TH_LWUD |
| 2295 | UINT64_C(3623895051), // TH_LWUIA |
| 2296 | UINT64_C(3355459595), // TH_LWUIB |
| 2297 | UINT64_C(536875019), // TH_MULA |
| 2298 | UINT64_C(671092747), // TH_MULAH |
| 2299 | UINT64_C(603983883), // TH_MULAW |
| 2300 | UINT64_C(570429451), // TH_MULS |
| 2301 | UINT64_C(704647179), // TH_MULSH |
| 2302 | UINT64_C(637538315), // TH_MULSW |
| 2303 | UINT64_C(1073745931), // TH_MVEQZ |
| 2304 | UINT64_C(1107300363), // TH_MVNEZ |
| 2305 | UINT64_C(2181042187), // TH_REV |
| 2306 | UINT64_C(2415923211), // TH_REVW |
| 2307 | UINT64_C(402673675), // TH_SBIA |
| 2308 | UINT64_C(134238219), // TH_SBIB |
| 2309 | UINT64_C(4160770059), // TH_SDD |
| 2310 | UINT64_C(2013286411), // TH_SDIA |
| 2311 | UINT64_C(1744850955), // TH_SDIB |
| 2312 | UINT64_C(67108875), // TH_SFENCE_VMAS |
| 2313 | UINT64_C(939544587), // TH_SHIA |
| 2314 | UINT64_C(671109131), // TH_SHIB |
| 2315 | UINT64_C(20491), // TH_SRB |
| 2316 | UINT64_C(1610633227), // TH_SRD |
| 2317 | UINT64_C(536891403), // TH_SRH |
| 2318 | UINT64_C(268439563), // TH_SRRI |
| 2319 | UINT64_C(335548427), // TH_SRRIW |
| 2320 | UINT64_C(1073762315), // TH_SRW |
| 2321 | UINT64_C(268455947), // TH_SURB |
| 2322 | UINT64_C(1879068683), // TH_SURD |
| 2323 | UINT64_C(805326859), // TH_SURH |
| 2324 | UINT64_C(1342197771), // TH_SURW |
| 2325 | UINT64_C(3758116875), // TH_SWD |
| 2326 | UINT64_C(1476415499), // TH_SWIA |
| 2327 | UINT64_C(1207980043), // TH_SWIB |
| 2328 | UINT64_C(25165835), // TH_SYNC |
| 2329 | UINT64_C(27262987), // TH_SYNC_I |
| 2330 | UINT64_C(28311563), // TH_SYNC_IS |
| 2331 | UINT64_C(26214411), // TH_SYNC_S |
| 2332 | UINT64_C(2281705483), // TH_TST |
| 2333 | UINT64_C(2147487755), // TH_TSTNBZ |
| 2334 | UINT64_C(2415943691), // TH_VMAQASU_VV |
| 2335 | UINT64_C(2483052555), // TH_VMAQASU_VX |
| 2336 | UINT64_C(2617270283), // TH_VMAQAUS_VX |
| 2337 | UINT64_C(2281725963), // TH_VMAQAU_VV |
| 2338 | UINT64_C(2348834827), // TH_VMAQAU_VX |
| 2339 | UINT64_C(2147508235), // TH_VMAQA_VV |
| 2340 | UINT64_C(2214617099), // TH_VMAQA_VX |
| 2341 | UINT64_C(3221229683), // UNIMP |
| 2342 | UINT64_C(3858767931), // UNZIP16HP |
| 2343 | UINT64_C(3791659067), // UNZIP16P |
| 2344 | UINT64_C(3825213499), // UNZIP8HP |
| 2345 | UINT64_C(3758104635), // UNZIP8P |
| 2346 | UINT64_C(149966867), // UNZIP_RV32 |
| 2347 | UINT64_C(2717925403), // USATI_RV32 |
| 2348 | UINT64_C(2751479835), // USATI_RV64 |
| 2349 | UINT64_C(536879191), // VAADDU_VV |
| 2350 | UINT64_C(536895575), // VAADDU_VX |
| 2351 | UINT64_C(603988055), // VAADD_VV |
| 2352 | UINT64_C(604004439), // VAADD_VX |
| 2353 | UINT64_C(1275076695), // VABDU_VV |
| 2354 | UINT64_C(1140858967), // VABD_VV |
| 2355 | UINT64_C(1208492119), // VABS_V |
| 2356 | UINT64_C(1073754199), // VADC_VIM |
| 2357 | UINT64_C(1073741911), // VADC_VVM |
| 2358 | UINT64_C(1073758295), // VADC_VXM |
| 2359 | UINT64_C(12375), // VADD_VI |
| 2360 | UINT64_C(87), // VADD_VV |
| 2361 | UINT64_C(16471), // VADD_VX |
| 2362 | UINT64_C(2785058935), // VAESDF_VS |
| 2363 | UINT64_C(2717950071), // VAESDF_VV |
| 2364 | UINT64_C(2785026167), // VAESDM_VS |
| 2365 | UINT64_C(2717917303), // VAESDM_VV |
| 2366 | UINT64_C(2785124471), // VAESEF_VS |
| 2367 | UINT64_C(2718015607), // VAESEF_VV |
| 2368 | UINT64_C(2785091703), // VAESEM_VS |
| 2369 | UINT64_C(2717982839), // VAESEM_VV |
| 2370 | UINT64_C(2315264119), // VAESKF1_VI |
| 2371 | UINT64_C(2852135031), // VAESKF2_VI |
| 2372 | UINT64_C(2785255543), // VAESZ_VS |
| 2373 | UINT64_C(67108951), // VANDN_VV |
| 2374 | UINT64_C(67125335), // VANDN_VX |
| 2375 | UINT64_C(603992151), // VAND_VI |
| 2376 | UINT64_C(603979863), // VAND_VV |
| 2377 | UINT64_C(603996247), // VAND_VX |
| 2378 | UINT64_C(671096919), // VASUBU_VV |
| 2379 | UINT64_C(671113303), // VASUBU_VX |
| 2380 | UINT64_C(738205783), // VASUB_VV |
| 2381 | UINT64_C(738222167), // VASUB_VX |
| 2382 | UINT64_C(1208229975), // VBREV8_V |
| 2383 | UINT64_C(1208295511), // VBREV_V |
| 2384 | UINT64_C(872423511), // VCLMULH_VV |
| 2385 | UINT64_C(872439895), // VCLMULH_VX |
| 2386 | UINT64_C(805314647), // VCLMUL_VV |
| 2387 | UINT64_C(805331031), // VCLMUL_VX |
| 2388 | UINT64_C(1208361047), // VCLZ_V |
| 2389 | UINT64_C(1577066583), // VCOMPRESS_VM |
| 2390 | UINT64_C(1074274391), // VCPOP_M |
| 2391 | UINT64_C(1208426583), // VCPOP_V |
| 2392 | UINT64_C(1208393815), // VCTZ_V |
| 2393 | UINT64_C(2147491927), // VDIVU_VV |
| 2394 | UINT64_C(2147508311), // VDIVU_VX |
| 2395 | UINT64_C(2214600791), // VDIV_VV |
| 2396 | UINT64_C(2214617175), // VDIV_VX |
| 2397 | UINT64_C(2818580567), // VDOTA4SU_VV |
| 2398 | UINT64_C(2818596951), // VDOTA4SU_VX |
| 2399 | UINT64_C(3087032407), // VDOTA4US_VX |
| 2400 | UINT64_C(2684362839), // VDOTA4U_VV |
| 2401 | UINT64_C(2684379223), // VDOTA4U_VX |
| 2402 | UINT64_C(2952798295), // VDOTA4_VV |
| 2403 | UINT64_C(2952814679), // VDOTA4_VX |
| 2404 | UINT64_C(20567), // VFADD_VF |
| 2405 | UINT64_C(4183), // VFADD_VV |
| 2406 | UINT64_C(1275596887), // VFCLASS_V |
| 2407 | UINT64_C(1208029271), // VFCVT_F_XU_V |
| 2408 | UINT64_C(1208062039), // VFCVT_F_X_V |
| 2409 | UINT64_C(1208160343), // VFCVT_RTZ_XU_F_V |
| 2410 | UINT64_C(1208193111), // VFCVT_RTZ_X_F_V |
| 2411 | UINT64_C(1207963735), // VFCVT_XU_F_V |
| 2412 | UINT64_C(1207996503), // VFCVT_X_F_V |
| 2413 | UINT64_C(2147504215), // VFDIV_VF |
| 2414 | UINT64_C(2147487831), // VFDIV_VV |
| 2415 | UINT64_C(1074307159), // VFIRST_M |
| 2416 | UINT64_C(2952810583), // VFMACC_VF |
| 2417 | UINT64_C(2952794199), // VFMACC_VV |
| 2418 | UINT64_C(2684375127), // VFMADD_VF |
| 2419 | UINT64_C(2684358743), // VFMADD_VV |
| 2420 | UINT64_C(402673751), // VFMAX_VF |
| 2421 | UINT64_C(402657367), // VFMAX_VV |
| 2422 | UINT64_C(1543524439), // VFMERGE_VFM |
| 2423 | UINT64_C(268456023), // VFMIN_VF |
| 2424 | UINT64_C(268439639), // VFMIN_VV |
| 2425 | UINT64_C(3087028311), // VFMSAC_VF |
| 2426 | UINT64_C(3087011927), // VFMSAC_VV |
| 2427 | UINT64_C(2818592855), // VFMSUB_VF |
| 2428 | UINT64_C(2818576471), // VFMSUB_VV |
| 2429 | UINT64_C(2415939671), // VFMUL_VF |
| 2430 | UINT64_C(2415923287), // VFMUL_VV |
| 2431 | UINT64_C(1107300439), // VFMV_F_S |
| 2432 | UINT64_C(1107316823), // VFMV_S_F |
| 2433 | UINT64_C(1577078871), // VFMV_V_F |
| 2434 | UINT64_C(1208914007), // VFNCVTBF16_F_F_W |
| 2435 | UINT64_C(1208979543), // VFNCVTBF16_SAT_F_F_W |
| 2436 | UINT64_C(1208782935), // VFNCVT_F_F_Q |
| 2437 | UINT64_C(1208619095), // VFNCVT_F_F_W |
| 2438 | UINT64_C(1208553559), // VFNCVT_F_XU_W |
| 2439 | UINT64_C(1208586327), // VFNCVT_F_X_W |
| 2440 | UINT64_C(1208651863), // VFNCVT_ROD_F_F_W |
| 2441 | UINT64_C(1208684631), // VFNCVT_RTZ_XU_F_W |
| 2442 | UINT64_C(1208717399), // VFNCVT_RTZ_X_F_W |
| 2443 | UINT64_C(1208848471), // VFNCVT_SAT_F_F_Q |
| 2444 | UINT64_C(1208488023), // VFNCVT_XU_F_W |
| 2445 | UINT64_C(1208520791), // VFNCVT_X_F_W |
| 2446 | UINT64_C(3019919447), // VFNMACC_VF |
| 2447 | UINT64_C(3019903063), // VFNMACC_VV |
| 2448 | UINT64_C(2751483991), // VFNMADD_VF |
| 2449 | UINT64_C(2751467607), // VFNMADD_VV |
| 2450 | UINT64_C(3154137175), // VFNMSAC_VF |
| 2451 | UINT64_C(3154120791), // VFNMSAC_VV |
| 2452 | UINT64_C(2885701719), // VFNMSUB_VF |
| 2453 | UINT64_C(2885685335), // VFNMSUB_VV |
| 2454 | UINT64_C(2214613079), // VFRDIV_VF |
| 2455 | UINT64_C(1275236439), // VFREC7_V |
| 2456 | UINT64_C(469766231), // VFREDMAX_VS |
| 2457 | UINT64_C(335548503), // VFREDMIN_VS |
| 2458 | UINT64_C(201330775), // VFREDOSUM_VS |
| 2459 | UINT64_C(67113047), // VFREDUSUM_VS |
| 2460 | UINT64_C(1275203671), // VFRSQRT7_V |
| 2461 | UINT64_C(2617266263), // VFRSUB_VF |
| 2462 | UINT64_C(604000343), // VFSGNJN_VF |
| 2463 | UINT64_C(603983959), // VFSGNJN_VV |
| 2464 | UINT64_C(671109207), // VFSGNJX_VF |
| 2465 | UINT64_C(671092823), // VFSGNJX_VV |
| 2466 | UINT64_C(536891479), // VFSGNJ_VF |
| 2467 | UINT64_C(536875095), // VFSGNJ_VV |
| 2468 | UINT64_C(1006653527), // VFSLIDE1DOWN_VF |
| 2469 | UINT64_C(939544663), // VFSLIDE1UP_VF |
| 2470 | UINT64_C(1275072599), // VFSQRT_V |
| 2471 | UINT64_C(134238295), // VFSUB_VF |
| 2472 | UINT64_C(134221911), // VFSUB_VV |
| 2473 | UINT64_C(3221246039), // VFWADD_VF |
| 2474 | UINT64_C(3221229655), // VFWADD_VV |
| 2475 | UINT64_C(3489681495), // VFWADD_WF |
| 2476 | UINT64_C(3489665111), // VFWADD_WV |
| 2477 | UINT64_C(1208389719), // VFWCVTBF16_F_F_V |
| 2478 | UINT64_C(1208356951), // VFWCVT_F_F_V |
| 2479 | UINT64_C(1208291415), // VFWCVT_F_XU_V |
| 2480 | UINT64_C(1208324183), // VFWCVT_F_X_V |
| 2481 | UINT64_C(1208422487), // VFWCVT_RTZ_XU_F_V |
| 2482 | UINT64_C(1208455255), // VFWCVT_RTZ_X_F_V |
| 2483 | UINT64_C(1208225879), // VFWCVT_XU_F_V |
| 2484 | UINT64_C(1208258647), // VFWCVT_X_F_V |
| 2485 | UINT64_C(3959443543), // VFWMACCBF16_VF |
| 2486 | UINT64_C(3959427159), // VFWMACCBF16_VV |
| 2487 | UINT64_C(4026552407), // VFWMACC_VF |
| 2488 | UINT64_C(4026536023), // VFWMACC_VV |
| 2489 | UINT64_C(4160770135), // VFWMSAC_VF |
| 2490 | UINT64_C(4160753751), // VFWMSAC_VV |
| 2491 | UINT64_C(3758116951), // VFWMUL_VF |
| 2492 | UINT64_C(3758100567), // VFWMUL_VV |
| 2493 | UINT64_C(4093661271), // VFWNMACC_VF |
| 2494 | UINT64_C(4093644887), // VFWNMACC_VV |
| 2495 | UINT64_C(4227878999), // VFWNMSAC_VF |
| 2496 | UINT64_C(4227862615), // VFWNMSAC_VV |
| 2497 | UINT64_C(3422556247), // VFWREDOSUM_VS |
| 2498 | UINT64_C(3288338519), // VFWREDUSUM_VS |
| 2499 | UINT64_C(3355463767), // VFWSUB_VF |
| 2500 | UINT64_C(3355447383), // VFWSUB_VV |
| 2501 | UINT64_C(3623899223), // VFWSUB_WF |
| 2502 | UINT64_C(3623882839), // VFWSUB_WV |
| 2503 | UINT64_C(2382372983), // VGHSH_VS |
| 2504 | UINT64_C(2986352759), // VGHSH_VV |
| 2505 | UINT64_C(2785583223), // VGMUL_VS |
| 2506 | UINT64_C(2718474359), // VGMUL_VV |
| 2507 | UINT64_C(1342742615), // VID_V |
| 2508 | UINT64_C(1342709847), // VIOTA_M |
| 2509 | UINT64_C(41963527), // VL1RE16_V |
| 2510 | UINT64_C(41967623), // VL1RE32_V |
| 2511 | UINT64_C(41971719), // VL1RE64_V |
| 2512 | UINT64_C(41943047), // VL1RE8_V |
| 2513 | UINT64_C(578834439), // VL2RE16_V |
| 2514 | UINT64_C(578838535), // VL2RE32_V |
| 2515 | UINT64_C(578842631), // VL2RE64_V |
| 2516 | UINT64_C(578813959), // VL2RE8_V |
| 2517 | UINT64_C(1652576263), // VL4RE16_V |
| 2518 | UINT64_C(1652580359), // VL4RE32_V |
| 2519 | UINT64_C(1652584455), // VL4RE64_V |
| 2520 | UINT64_C(1652555783), // VL4RE8_V |
| 2521 | UINT64_C(3800059911), // VL8RE16_V |
| 2522 | UINT64_C(3800064007), // VL8RE32_V |
| 2523 | UINT64_C(3800068103), // VL8RE64_V |
| 2524 | UINT64_C(3800039431), // VL8RE8_V |
| 2525 | UINT64_C(16797703), // VLE16FF_V |
| 2526 | UINT64_C(20487), // VLE16_V |
| 2527 | UINT64_C(16801799), // VLE32FF_V |
| 2528 | UINT64_C(24583), // VLE32_V |
| 2529 | UINT64_C(16805895), // VLE64FF_V |
| 2530 | UINT64_C(28679), // VLE64_V |
| 2531 | UINT64_C(16777223), // VLE8FF_V |
| 2532 | UINT64_C(7), // VLE8_V |
| 2533 | UINT64_C(45088775), // VLM_V |
| 2534 | UINT64_C(201347079), // VLOXEI16_V |
| 2535 | UINT64_C(201351175), // VLOXEI32_V |
| 2536 | UINT64_C(201355271), // VLOXEI64_V |
| 2537 | UINT64_C(201326599), // VLOXEI8_V |
| 2538 | UINT64_C(738217991), // VLOXSEG2EI16_V |
| 2539 | UINT64_C(738222087), // VLOXSEG2EI32_V |
| 2540 | UINT64_C(738226183), // VLOXSEG2EI64_V |
| 2541 | UINT64_C(738197511), // VLOXSEG2EI8_V |
| 2542 | UINT64_C(1275088903), // VLOXSEG3EI16_V |
| 2543 | UINT64_C(1275092999), // VLOXSEG3EI32_V |
| 2544 | UINT64_C(1275097095), // VLOXSEG3EI64_V |
| 2545 | UINT64_C(1275068423), // VLOXSEG3EI8_V |
| 2546 | UINT64_C(1811959815), // VLOXSEG4EI16_V |
| 2547 | UINT64_C(1811963911), // VLOXSEG4EI32_V |
| 2548 | UINT64_C(1811968007), // VLOXSEG4EI64_V |
| 2549 | UINT64_C(1811939335), // VLOXSEG4EI8_V |
| 2550 | UINT64_C(2348830727), // VLOXSEG5EI16_V |
| 2551 | UINT64_C(2348834823), // VLOXSEG5EI32_V |
| 2552 | UINT64_C(2348838919), // VLOXSEG5EI64_V |
| 2553 | UINT64_C(2348810247), // VLOXSEG5EI8_V |
| 2554 | UINT64_C(2885701639), // VLOXSEG6EI16_V |
| 2555 | UINT64_C(2885705735), // VLOXSEG6EI32_V |
| 2556 | UINT64_C(2885709831), // VLOXSEG6EI64_V |
| 2557 | UINT64_C(2885681159), // VLOXSEG6EI8_V |
| 2558 | UINT64_C(3422572551), // VLOXSEG7EI16_V |
| 2559 | UINT64_C(3422576647), // VLOXSEG7EI32_V |
| 2560 | UINT64_C(3422580743), // VLOXSEG7EI64_V |
| 2561 | UINT64_C(3422552071), // VLOXSEG7EI8_V |
| 2562 | UINT64_C(3959443463), // VLOXSEG8EI16_V |
| 2563 | UINT64_C(3959447559), // VLOXSEG8EI32_V |
| 2564 | UINT64_C(3959451655), // VLOXSEG8EI64_V |
| 2565 | UINT64_C(3959422983), // VLOXSEG8EI8_V |
| 2566 | UINT64_C(134238215), // VLSE16_V |
| 2567 | UINT64_C(134242311), // VLSE32_V |
| 2568 | UINT64_C(134246407), // VLSE64_V |
| 2569 | UINT64_C(134217735), // VLSE8_V |
| 2570 | UINT64_C(553668615), // VLSEG2E16FF_V |
| 2571 | UINT64_C(536891399), // VLSEG2E16_V |
| 2572 | UINT64_C(553672711), // VLSEG2E32FF_V |
| 2573 | UINT64_C(536895495), // VLSEG2E32_V |
| 2574 | UINT64_C(553676807), // VLSEG2E64FF_V |
| 2575 | UINT64_C(536899591), // VLSEG2E64_V |
| 2576 | UINT64_C(553648135), // VLSEG2E8FF_V |
| 2577 | UINT64_C(536870919), // VLSEG2E8_V |
| 2578 | UINT64_C(1090539527), // VLSEG3E16FF_V |
| 2579 | UINT64_C(1073762311), // VLSEG3E16_V |
| 2580 | UINT64_C(1090543623), // VLSEG3E32FF_V |
| 2581 | UINT64_C(1073766407), // VLSEG3E32_V |
| 2582 | UINT64_C(1090547719), // VLSEG3E64FF_V |
| 2583 | UINT64_C(1073770503), // VLSEG3E64_V |
| 2584 | UINT64_C(1090519047), // VLSEG3E8FF_V |
| 2585 | UINT64_C(1073741831), // VLSEG3E8_V |
| 2586 | UINT64_C(1627410439), // VLSEG4E16FF_V |
| 2587 | UINT64_C(1610633223), // VLSEG4E16_V |
| 2588 | UINT64_C(1627414535), // VLSEG4E32FF_V |
| 2589 | UINT64_C(1610637319), // VLSEG4E32_V |
| 2590 | UINT64_C(1627418631), // VLSEG4E64FF_V |
| 2591 | UINT64_C(1610641415), // VLSEG4E64_V |
| 2592 | UINT64_C(1627389959), // VLSEG4E8FF_V |
| 2593 | UINT64_C(1610612743), // VLSEG4E8_V |
| 2594 | UINT64_C(2164281351), // VLSEG5E16FF_V |
| 2595 | UINT64_C(2147504135), // VLSEG5E16_V |
| 2596 | UINT64_C(2164285447), // VLSEG5E32FF_V |
| 2597 | UINT64_C(2147508231), // VLSEG5E32_V |
| 2598 | UINT64_C(2164289543), // VLSEG5E64FF_V |
| 2599 | UINT64_C(2147512327), // VLSEG5E64_V |
| 2600 | UINT64_C(2164260871), // VLSEG5E8FF_V |
| 2601 | UINT64_C(2147483655), // VLSEG5E8_V |
| 2602 | UINT64_C(2701152263), // VLSEG6E16FF_V |
| 2603 | UINT64_C(2684375047), // VLSEG6E16_V |
| 2604 | UINT64_C(2701156359), // VLSEG6E32FF_V |
| 2605 | UINT64_C(2684379143), // VLSEG6E32_V |
| 2606 | UINT64_C(2701160455), // VLSEG6E64FF_V |
| 2607 | UINT64_C(2684383239), // VLSEG6E64_V |
| 2608 | UINT64_C(2701131783), // VLSEG6E8FF_V |
| 2609 | UINT64_C(2684354567), // VLSEG6E8_V |
| 2610 | UINT64_C(3238023175), // VLSEG7E16FF_V |
| 2611 | UINT64_C(3221245959), // VLSEG7E16_V |
| 2612 | UINT64_C(3238027271), // VLSEG7E32FF_V |
| 2613 | UINT64_C(3221250055), // VLSEG7E32_V |
| 2614 | UINT64_C(3238031367), // VLSEG7E64FF_V |
| 2615 | UINT64_C(3221254151), // VLSEG7E64_V |
| 2616 | UINT64_C(3238002695), // VLSEG7E8FF_V |
| 2617 | UINT64_C(3221225479), // VLSEG7E8_V |
| 2618 | UINT64_C(3774894087), // VLSEG8E16FF_V |
| 2619 | UINT64_C(3758116871), // VLSEG8E16_V |
| 2620 | UINT64_C(3774898183), // VLSEG8E32FF_V |
| 2621 | UINT64_C(3758120967), // VLSEG8E32_V |
| 2622 | UINT64_C(3774902279), // VLSEG8E64FF_V |
| 2623 | UINT64_C(3758125063), // VLSEG8E64_V |
| 2624 | UINT64_C(3774873607), // VLSEG8E8FF_V |
| 2625 | UINT64_C(3758096391), // VLSEG8E8_V |
| 2626 | UINT64_C(671109127), // VLSSEG2E16_V |
| 2627 | UINT64_C(671113223), // VLSSEG2E32_V |
| 2628 | UINT64_C(671117319), // VLSSEG2E64_V |
| 2629 | UINT64_C(671088647), // VLSSEG2E8_V |
| 2630 | UINT64_C(1207980039), // VLSSEG3E16_V |
| 2631 | UINT64_C(1207984135), // VLSSEG3E32_V |
| 2632 | UINT64_C(1207988231), // VLSSEG3E64_V |
| 2633 | UINT64_C(1207959559), // VLSSEG3E8_V |
| 2634 | UINT64_C(1744850951), // VLSSEG4E16_V |
| 2635 | UINT64_C(1744855047), // VLSSEG4E32_V |
| 2636 | UINT64_C(1744859143), // VLSSEG4E64_V |
| 2637 | UINT64_C(1744830471), // VLSSEG4E8_V |
| 2638 | UINT64_C(2281721863), // VLSSEG5E16_V |
| 2639 | UINT64_C(2281725959), // VLSSEG5E32_V |
| 2640 | UINT64_C(2281730055), // VLSSEG5E64_V |
| 2641 | UINT64_C(2281701383), // VLSSEG5E8_V |
| 2642 | UINT64_C(2818592775), // VLSSEG6E16_V |
| 2643 | UINT64_C(2818596871), // VLSSEG6E32_V |
| 2644 | UINT64_C(2818600967), // VLSSEG6E64_V |
| 2645 | UINT64_C(2818572295), // VLSSEG6E8_V |
| 2646 | UINT64_C(3355463687), // VLSSEG7E16_V |
| 2647 | UINT64_C(3355467783), // VLSSEG7E32_V |
| 2648 | UINT64_C(3355471879), // VLSSEG7E64_V |
| 2649 | UINT64_C(3355443207), // VLSSEG7E8_V |
| 2650 | UINT64_C(3892334599), // VLSSEG8E16_V |
| 2651 | UINT64_C(3892338695), // VLSSEG8E32_V |
| 2652 | UINT64_C(3892342791), // VLSSEG8E64_V |
| 2653 | UINT64_C(3892314119), // VLSSEG8E8_V |
| 2654 | UINT64_C(67129351), // VLUXEI16_V |
| 2655 | UINT64_C(67133447), // VLUXEI32_V |
| 2656 | UINT64_C(67137543), // VLUXEI64_V |
| 2657 | UINT64_C(67108871), // VLUXEI8_V |
| 2658 | UINT64_C(604000263), // VLUXSEG2EI16_V |
| 2659 | UINT64_C(604004359), // VLUXSEG2EI32_V |
| 2660 | UINT64_C(604008455), // VLUXSEG2EI64_V |
| 2661 | UINT64_C(603979783), // VLUXSEG2EI8_V |
| 2662 | UINT64_C(1140871175), // VLUXSEG3EI16_V |
| 2663 | UINT64_C(1140875271), // VLUXSEG3EI32_V |
| 2664 | UINT64_C(1140879367), // VLUXSEG3EI64_V |
| 2665 | UINT64_C(1140850695), // VLUXSEG3EI8_V |
| 2666 | UINT64_C(1677742087), // VLUXSEG4EI16_V |
| 2667 | UINT64_C(1677746183), // VLUXSEG4EI32_V |
| 2668 | UINT64_C(1677750279), // VLUXSEG4EI64_V |
| 2669 | UINT64_C(1677721607), // VLUXSEG4EI8_V |
| 2670 | UINT64_C(2214612999), // VLUXSEG5EI16_V |
| 2671 | UINT64_C(2214617095), // VLUXSEG5EI32_V |
| 2672 | UINT64_C(2214621191), // VLUXSEG5EI64_V |
| 2673 | UINT64_C(2214592519), // VLUXSEG5EI8_V |
| 2674 | UINT64_C(2751483911), // VLUXSEG6EI16_V |
| 2675 | UINT64_C(2751488007), // VLUXSEG6EI32_V |
| 2676 | UINT64_C(2751492103), // VLUXSEG6EI64_V |
| 2677 | UINT64_C(2751463431), // VLUXSEG6EI8_V |
| 2678 | UINT64_C(3288354823), // VLUXSEG7EI16_V |
| 2679 | UINT64_C(3288358919), // VLUXSEG7EI32_V |
| 2680 | UINT64_C(3288363015), // VLUXSEG7EI64_V |
| 2681 | UINT64_C(3288334343), // VLUXSEG7EI8_V |
| 2682 | UINT64_C(3825225735), // VLUXSEG8EI16_V |
| 2683 | UINT64_C(3825229831), // VLUXSEG8EI32_V |
| 2684 | UINT64_C(3825233927), // VLUXSEG8EI64_V |
| 2685 | UINT64_C(3825205255), // VLUXSEG8EI8_V |
| 2686 | UINT64_C(3019907159), // VMACC_VV |
| 2687 | UINT64_C(3019923543), // VMACC_VX |
| 2688 | UINT64_C(1174417495), // VMADC_VI |
| 2689 | UINT64_C(1140863063), // VMADC_VIM |
| 2690 | UINT64_C(1174405207), // VMADC_VV |
| 2691 | UINT64_C(1140850775), // VMADC_VVM |
| 2692 | UINT64_C(1174421591), // VMADC_VX |
| 2693 | UINT64_C(1140867159), // VMADC_VXM |
| 2694 | UINT64_C(2751471703), // VMADD_VV |
| 2695 | UINT64_C(2751488087), // VMADD_VX |
| 2696 | UINT64_C(1644175447), // VMANDN_MM |
| 2697 | UINT64_C(1711284311), // VMAND_MM |
| 2698 | UINT64_C(402653271), // VMAXU_VV |
| 2699 | UINT64_C(402669655), // VMAXU_VX |
| 2700 | UINT64_C(469762135), // VMAX_VV |
| 2701 | UINT64_C(469778519), // VMAX_VX |
| 2702 | UINT64_C(1543516247), // VMERGE_VIM |
| 2703 | UINT64_C(1543503959), // VMERGE_VVM |
| 2704 | UINT64_C(1543520343), // VMERGE_VXM |
| 2705 | UINT64_C(1610633303), // VMFEQ_VF |
| 2706 | UINT64_C(1610616919), // VMFEQ_VV |
| 2707 | UINT64_C(2080395351), // VMFGE_VF |
| 2708 | UINT64_C(1946177623), // VMFGT_VF |
| 2709 | UINT64_C(1677742167), // VMFLE_VF |
| 2710 | UINT64_C(1677725783), // VMFLE_VV |
| 2711 | UINT64_C(1811959895), // VMFLT_VF |
| 2712 | UINT64_C(1811943511), // VMFLT_VV |
| 2713 | UINT64_C(1879068759), // VMFNE_VF |
| 2714 | UINT64_C(1879052375), // VMFNE_VV |
| 2715 | UINT64_C(268435543), // VMINU_VV |
| 2716 | UINT64_C(268451927), // VMINU_VX |
| 2717 | UINT64_C(335544407), // VMIN_VV |
| 2718 | UINT64_C(335560791), // VMIN_VX |
| 2719 | UINT64_C(1979719767), // VMNAND_MM |
| 2720 | UINT64_C(2046828631), // VMNOR_MM |
| 2721 | UINT64_C(1912610903), // VMORN_MM |
| 2722 | UINT64_C(1778393175), // VMOR_MM |
| 2723 | UINT64_C(1308622935), // VMSBC_VV |
| 2724 | UINT64_C(1275068503), // VMSBC_VVM |
| 2725 | UINT64_C(1308639319), // VMSBC_VX |
| 2726 | UINT64_C(1275084887), // VMSBC_VXM |
| 2727 | UINT64_C(1342218327), // VMSBF_M |
| 2728 | UINT64_C(1610625111), // VMSEQ_VI |
| 2729 | UINT64_C(1610612823), // VMSEQ_VV |
| 2730 | UINT64_C(1610629207), // VMSEQ_VX |
| 2731 | UINT64_C(2013278295), // VMSGTU_VI |
| 2732 | UINT64_C(2013282391), // VMSGTU_VX |
| 2733 | UINT64_C(2080387159), // VMSGT_VI |
| 2734 | UINT64_C(2080391255), // VMSGT_VX |
| 2735 | UINT64_C(1342283863), // VMSIF_M |
| 2736 | UINT64_C(1879060567), // VMSLEU_VI |
| 2737 | UINT64_C(1879048279), // VMSLEU_VV |
| 2738 | UINT64_C(1879064663), // VMSLEU_VX |
| 2739 | UINT64_C(1946169431), // VMSLE_VI |
| 2740 | UINT64_C(1946157143), // VMSLE_VV |
| 2741 | UINT64_C(1946173527), // VMSLE_VX |
| 2742 | UINT64_C(1744830551), // VMSLTU_VV |
| 2743 | UINT64_C(1744846935), // VMSLTU_VX |
| 2744 | UINT64_C(1811939415), // VMSLT_VV |
| 2745 | UINT64_C(1811955799), // VMSLT_VX |
| 2746 | UINT64_C(1677733975), // VMSNE_VI |
| 2747 | UINT64_C(1677721687), // VMSNE_VV |
| 2748 | UINT64_C(1677738071), // VMSNE_VX |
| 2749 | UINT64_C(1342251095), // VMSOF_M |
| 2750 | UINT64_C(2550145111), // VMULHSU_VV |
| 2751 | UINT64_C(2550161495), // VMULHSU_VX |
| 2752 | UINT64_C(2415927383), // VMULHU_VV |
| 2753 | UINT64_C(2415943767), // VMULHU_VX |
| 2754 | UINT64_C(2617253975), // VMULH_VV |
| 2755 | UINT64_C(2617270359), // VMULH_VX |
| 2756 | UINT64_C(2483036247), // VMUL_VV |
| 2757 | UINT64_C(2483052631), // VMUL_VX |
| 2758 | UINT64_C(2650812503), // VMV1R_V |
| 2759 | UINT64_C(2650845271), // VMV2R_V |
| 2760 | UINT64_C(2650910807), // VMV4R_V |
| 2761 | UINT64_C(2651041879), // VMV8R_V |
| 2762 | UINT64_C(1107320919), // VMV_S_X |
| 2763 | UINT64_C(1577070679), // VMV_V_I |
| 2764 | UINT64_C(1577058391), // VMV_V_V |
| 2765 | UINT64_C(1577074775), // VMV_V_X |
| 2766 | UINT64_C(1107304535), // VMV_X_S |
| 2767 | UINT64_C(2113937495), // VMXNOR_MM |
| 2768 | UINT64_C(1845502039), // VMXOR_MM |
| 2769 | UINT64_C(3087020119), // VNCLIPU_WI |
| 2770 | UINT64_C(3087007831), // VNCLIPU_WV |
| 2771 | UINT64_C(3087024215), // VNCLIPU_WX |
| 2772 | UINT64_C(3154128983), // VNCLIP_WI |
| 2773 | UINT64_C(3154116695), // VNCLIP_WV |
| 2774 | UINT64_C(3154133079), // VNCLIP_WX |
| 2775 | UINT64_C(3154124887), // VNMSAC_VV |
| 2776 | UINT64_C(3154141271), // VNMSAC_VX |
| 2777 | UINT64_C(2885689431), // VNMSUB_VV |
| 2778 | UINT64_C(2885705815), // VNMSUB_VX |
| 2779 | UINT64_C(3019911255), // VNSRA_WI |
| 2780 | UINT64_C(3019898967), // VNSRA_WV |
| 2781 | UINT64_C(3019915351), // VNSRA_WX |
| 2782 | UINT64_C(2952802391), // VNSRL_WI |
| 2783 | UINT64_C(2952790103), // VNSRL_WV |
| 2784 | UINT64_C(2952806487), // VNSRL_WX |
| 2785 | UINT64_C(671101015), // VOR_VI |
| 2786 | UINT64_C(671088727), // VOR_VV |
| 2787 | UINT64_C(671105111), // VOR_VX |
| 2788 | UINT64_C(1006633047), // VPAIRE_VV |
| 2789 | UINT64_C(1006641239), // VPAIRO_VV |
| 2790 | UINT64_C(67117143), // VREDAND_VS |
| 2791 | UINT64_C(402661463), // VREDMAXU_VS |
| 2792 | UINT64_C(469770327), // VREDMAX_VS |
| 2793 | UINT64_C(268443735), // VREDMINU_VS |
| 2794 | UINT64_C(335552599), // VREDMIN_VS |
| 2795 | UINT64_C(134226007), // VREDOR_VS |
| 2796 | UINT64_C(8279), // VREDSUM_VS |
| 2797 | UINT64_C(201334871), // VREDXOR_VS |
| 2798 | UINT64_C(2281709655), // VREMU_VV |
| 2799 | UINT64_C(2281726039), // VREMU_VX |
| 2800 | UINT64_C(2348818519), // VREM_VV |
| 2801 | UINT64_C(2348834903), // VREM_VX |
| 2802 | UINT64_C(1208262743), // VREV8_V |
| 2803 | UINT64_C(939524183), // VRGATHEREI16_VV |
| 2804 | UINT64_C(805318743), // VRGATHER_VI |
| 2805 | UINT64_C(805306455), // VRGATHER_VV |
| 2806 | UINT64_C(805322839), // VRGATHER_VX |
| 2807 | UINT64_C(1409286231), // VROL_VV |
| 2808 | UINT64_C(1409302615), // VROL_VX |
| 2809 | UINT64_C(1342189655), // VROR_VI |
| 2810 | UINT64_C(1342177367), // VROR_VV |
| 2811 | UINT64_C(1342193751), // VROR_VX |
| 2812 | UINT64_C(201338967), // VRSUB_VI |
| 2813 | UINT64_C(201343063), // VRSUB_VX |
| 2814 | UINT64_C(41943079), // VS1R_V |
| 2815 | UINT64_C(578813991), // VS2R_V |
| 2816 | UINT64_C(1652555815), // VS4R_V |
| 2817 | UINT64_C(3800039463), // VS8R_V |
| 2818 | UINT64_C(2147496023), // VSADDU_VI |
| 2819 | UINT64_C(2147483735), // VSADDU_VV |
| 2820 | UINT64_C(2147500119), // VSADDU_VX |
| 2821 | UINT64_C(2214604887), // VSADD_VI |
| 2822 | UINT64_C(2214592599), // VSADD_VV |
| 2823 | UINT64_C(2214608983), // VSADD_VX |
| 2824 | UINT64_C(1207959639), // VSBC_VVM |
| 2825 | UINT64_C(1207976023), // VSBC_VXM |
| 2826 | UINT64_C(20519), // VSE16_V |
| 2827 | UINT64_C(24615), // VSE32_V |
| 2828 | UINT64_C(28711), // VSE64_V |
| 2829 | UINT64_C(39), // VSE8_V |
| 2830 | UINT64_C(3221254231), // VSETIVLI |
| 2831 | UINT64_C(2147512407), // VSETVL |
| 2832 | UINT64_C(28759), // VSETVLI |
| 2833 | UINT64_C(1208197207), // VSEXT_VF2 |
| 2834 | UINT64_C(1208131671), // VSEXT_VF4 |
| 2835 | UINT64_C(1208066135), // VSEXT_VF8 |
| 2836 | UINT64_C(3120570487), // VSHA2CH_VV |
| 2837 | UINT64_C(3187679351), // VSHA2CL_VV |
| 2838 | UINT64_C(3053461623), // VSHA2MS_VV |
| 2839 | UINT64_C(1006657623), // VSLIDE1DOWN_VX |
| 2840 | UINT64_C(939548759), // VSLIDE1UP_VX |
| 2841 | UINT64_C(1006645335), // VSLIDEDOWN_VI |
| 2842 | UINT64_C(1006649431), // VSLIDEDOWN_VX |
| 2843 | UINT64_C(939536471), // VSLIDEUP_VI |
| 2844 | UINT64_C(939540567), // VSLIDEUP_VX |
| 2845 | UINT64_C(2483040343), // VSLL_VI |
| 2846 | UINT64_C(2483028055), // VSLL_VV |
| 2847 | UINT64_C(2483044439), // VSLL_VX |
| 2848 | UINT64_C(2919243895), // VSM3C_VI |
| 2849 | UINT64_C(2181046391), // VSM3ME_VV |
| 2850 | UINT64_C(2248155255), // VSM4K_VI |
| 2851 | UINT64_C(2785550455), // VSM4R_VS |
| 2852 | UINT64_C(2718441591), // VSM4R_VV |
| 2853 | UINT64_C(2617245783), // VSMUL_VV |
| 2854 | UINT64_C(2617262167), // VSMUL_VX |
| 2855 | UINT64_C(45088807), // VSM_V |
| 2856 | UINT64_C(201347111), // VSOXEI16_V |
| 2857 | UINT64_C(201351207), // VSOXEI32_V |
| 2858 | UINT64_C(201355303), // VSOXEI64_V |
| 2859 | UINT64_C(201326631), // VSOXEI8_V |
| 2860 | UINT64_C(738218023), // VSOXSEG2EI16_V |
| 2861 | UINT64_C(738222119), // VSOXSEG2EI32_V |
| 2862 | UINT64_C(738226215), // VSOXSEG2EI64_V |
| 2863 | UINT64_C(738197543), // VSOXSEG2EI8_V |
| 2864 | UINT64_C(1275088935), // VSOXSEG3EI16_V |
| 2865 | UINT64_C(1275093031), // VSOXSEG3EI32_V |
| 2866 | UINT64_C(1275097127), // VSOXSEG3EI64_V |
| 2867 | UINT64_C(1275068455), // VSOXSEG3EI8_V |
| 2868 | UINT64_C(1811959847), // VSOXSEG4EI16_V |
| 2869 | UINT64_C(1811963943), // VSOXSEG4EI32_V |
| 2870 | UINT64_C(1811968039), // VSOXSEG4EI64_V |
| 2871 | UINT64_C(1811939367), // VSOXSEG4EI8_V |
| 2872 | UINT64_C(2348830759), // VSOXSEG5EI16_V |
| 2873 | UINT64_C(2348834855), // VSOXSEG5EI32_V |
| 2874 | UINT64_C(2348838951), // VSOXSEG5EI64_V |
| 2875 | UINT64_C(2348810279), // VSOXSEG5EI8_V |
| 2876 | UINT64_C(2885701671), // VSOXSEG6EI16_V |
| 2877 | UINT64_C(2885705767), // VSOXSEG6EI32_V |
| 2878 | UINT64_C(2885709863), // VSOXSEG6EI64_V |
| 2879 | UINT64_C(2885681191), // VSOXSEG6EI8_V |
| 2880 | UINT64_C(3422572583), // VSOXSEG7EI16_V |
| 2881 | UINT64_C(3422576679), // VSOXSEG7EI32_V |
| 2882 | UINT64_C(3422580775), // VSOXSEG7EI64_V |
| 2883 | UINT64_C(3422552103), // VSOXSEG7EI8_V |
| 2884 | UINT64_C(3959443495), // VSOXSEG8EI16_V |
| 2885 | UINT64_C(3959447591), // VSOXSEG8EI32_V |
| 2886 | UINT64_C(3959451687), // VSOXSEG8EI64_V |
| 2887 | UINT64_C(3959423015), // VSOXSEG8EI8_V |
| 2888 | UINT64_C(2751475799), // VSRA_VI |
| 2889 | UINT64_C(2751463511), // VSRA_VV |
| 2890 | UINT64_C(2751479895), // VSRA_VX |
| 2891 | UINT64_C(2684366935), // VSRL_VI |
| 2892 | UINT64_C(2684354647), // VSRL_VV |
| 2893 | UINT64_C(2684371031), // VSRL_VX |
| 2894 | UINT64_C(134238247), // VSSE16_V |
| 2895 | UINT64_C(134242343), // VSSE32_V |
| 2896 | UINT64_C(134246439), // VSSE64_V |
| 2897 | UINT64_C(134217767), // VSSE8_V |
| 2898 | UINT64_C(536891431), // VSSEG2E16_V |
| 2899 | UINT64_C(536895527), // VSSEG2E32_V |
| 2900 | UINT64_C(536899623), // VSSEG2E64_V |
| 2901 | UINT64_C(536870951), // VSSEG2E8_V |
| 2902 | UINT64_C(1073762343), // VSSEG3E16_V |
| 2903 | UINT64_C(1073766439), // VSSEG3E32_V |
| 2904 | UINT64_C(1073770535), // VSSEG3E64_V |
| 2905 | UINT64_C(1073741863), // VSSEG3E8_V |
| 2906 | UINT64_C(1610633255), // VSSEG4E16_V |
| 2907 | UINT64_C(1610637351), // VSSEG4E32_V |
| 2908 | UINT64_C(1610641447), // VSSEG4E64_V |
| 2909 | UINT64_C(1610612775), // VSSEG4E8_V |
| 2910 | UINT64_C(2147504167), // VSSEG5E16_V |
| 2911 | UINT64_C(2147508263), // VSSEG5E32_V |
| 2912 | UINT64_C(2147512359), // VSSEG5E64_V |
| 2913 | UINT64_C(2147483687), // VSSEG5E8_V |
| 2914 | UINT64_C(2684375079), // VSSEG6E16_V |
| 2915 | UINT64_C(2684379175), // VSSEG6E32_V |
| 2916 | UINT64_C(2684383271), // VSSEG6E64_V |
| 2917 | UINT64_C(2684354599), // VSSEG6E8_V |
| 2918 | UINT64_C(3221245991), // VSSEG7E16_V |
| 2919 | UINT64_C(3221250087), // VSSEG7E32_V |
| 2920 | UINT64_C(3221254183), // VSSEG7E64_V |
| 2921 | UINT64_C(3221225511), // VSSEG7E8_V |
| 2922 | UINT64_C(3758116903), // VSSEG8E16_V |
| 2923 | UINT64_C(3758120999), // VSSEG8E32_V |
| 2924 | UINT64_C(3758125095), // VSSEG8E64_V |
| 2925 | UINT64_C(3758096423), // VSSEG8E8_V |
| 2926 | UINT64_C(2885693527), // VSSRA_VI |
| 2927 | UINT64_C(2885681239), // VSSRA_VV |
| 2928 | UINT64_C(2885697623), // VSSRA_VX |
| 2929 | UINT64_C(2818584663), // VSSRL_VI |
| 2930 | UINT64_C(2818572375), // VSSRL_VV |
| 2931 | UINT64_C(2818588759), // VSSRL_VX |
| 2932 | UINT64_C(671109159), // VSSSEG2E16_V |
| 2933 | UINT64_C(671113255), // VSSSEG2E32_V |
| 2934 | UINT64_C(671117351), // VSSSEG2E64_V |
| 2935 | UINT64_C(671088679), // VSSSEG2E8_V |
| 2936 | UINT64_C(1207980071), // VSSSEG3E16_V |
| 2937 | UINT64_C(1207984167), // VSSSEG3E32_V |
| 2938 | UINT64_C(1207988263), // VSSSEG3E64_V |
| 2939 | UINT64_C(1207959591), // VSSSEG3E8_V |
| 2940 | UINT64_C(1744850983), // VSSSEG4E16_V |
| 2941 | UINT64_C(1744855079), // VSSSEG4E32_V |
| 2942 | UINT64_C(1744859175), // VSSSEG4E64_V |
| 2943 | UINT64_C(1744830503), // VSSSEG4E8_V |
| 2944 | UINT64_C(2281721895), // VSSSEG5E16_V |
| 2945 | UINT64_C(2281725991), // VSSSEG5E32_V |
| 2946 | UINT64_C(2281730087), // VSSSEG5E64_V |
| 2947 | UINT64_C(2281701415), // VSSSEG5E8_V |
| 2948 | UINT64_C(2818592807), // VSSSEG6E16_V |
| 2949 | UINT64_C(2818596903), // VSSSEG6E32_V |
| 2950 | UINT64_C(2818600999), // VSSSEG6E64_V |
| 2951 | UINT64_C(2818572327), // VSSSEG6E8_V |
| 2952 | UINT64_C(3355463719), // VSSSEG7E16_V |
| 2953 | UINT64_C(3355467815), // VSSSEG7E32_V |
| 2954 | UINT64_C(3355471911), // VSSSEG7E64_V |
| 2955 | UINT64_C(3355443239), // VSSSEG7E8_V |
| 2956 | UINT64_C(3892334631), // VSSSEG8E16_V |
| 2957 | UINT64_C(3892338727), // VSSSEG8E32_V |
| 2958 | UINT64_C(3892342823), // VSSSEG8E64_V |
| 2959 | UINT64_C(3892314151), // VSSSEG8E8_V |
| 2960 | UINT64_C(2281701463), // VSSUBU_VV |
| 2961 | UINT64_C(2281717847), // VSSUBU_VX |
| 2962 | UINT64_C(2348810327), // VSSUB_VV |
| 2963 | UINT64_C(2348826711), // VSSUB_VX |
| 2964 | UINT64_C(134217815), // VSUB_VV |
| 2965 | UINT64_C(134234199), // VSUB_VX |
| 2966 | UINT64_C(67129383), // VSUXEI16_V |
| 2967 | UINT64_C(67133479), // VSUXEI32_V |
| 2968 | UINT64_C(67137575), // VSUXEI64_V |
| 2969 | UINT64_C(67108903), // VSUXEI8_V |
| 2970 | UINT64_C(604000295), // VSUXSEG2EI16_V |
| 2971 | UINT64_C(604004391), // VSUXSEG2EI32_V |
| 2972 | UINT64_C(604008487), // VSUXSEG2EI64_V |
| 2973 | UINT64_C(603979815), // VSUXSEG2EI8_V |
| 2974 | UINT64_C(1140871207), // VSUXSEG3EI16_V |
| 2975 | UINT64_C(1140875303), // VSUXSEG3EI32_V |
| 2976 | UINT64_C(1140879399), // VSUXSEG3EI64_V |
| 2977 | UINT64_C(1140850727), // VSUXSEG3EI8_V |
| 2978 | UINT64_C(1677742119), // VSUXSEG4EI16_V |
| 2979 | UINT64_C(1677746215), // VSUXSEG4EI32_V |
| 2980 | UINT64_C(1677750311), // VSUXSEG4EI64_V |
| 2981 | UINT64_C(1677721639), // VSUXSEG4EI8_V |
| 2982 | UINT64_C(2214613031), // VSUXSEG5EI16_V |
| 2983 | UINT64_C(2214617127), // VSUXSEG5EI32_V |
| 2984 | UINT64_C(2214621223), // VSUXSEG5EI64_V |
| 2985 | UINT64_C(2214592551), // VSUXSEG5EI8_V |
| 2986 | UINT64_C(2751483943), // VSUXSEG6EI16_V |
| 2987 | UINT64_C(2751488039), // VSUXSEG6EI32_V |
| 2988 | UINT64_C(2751492135), // VSUXSEG6EI64_V |
| 2989 | UINT64_C(2751463463), // VSUXSEG6EI8_V |
| 2990 | UINT64_C(3288354855), // VSUXSEG7EI16_V |
| 2991 | UINT64_C(3288358951), // VSUXSEG7EI32_V |
| 2992 | UINT64_C(3288363047), // VSUXSEG7EI64_V |
| 2993 | UINT64_C(3288334375), // VSUXSEG7EI8_V |
| 2994 | UINT64_C(3825225767), // VSUXSEG8EI16_V |
| 2995 | UINT64_C(3825229863), // VSUXSEG8EI32_V |
| 2996 | UINT64_C(3825233959), // VSUXSEG8EI64_V |
| 2997 | UINT64_C(3825205287), // VSUXSEG8EI8_V |
| 2998 | UINT64_C(24699), // VT_MASKC |
| 2999 | UINT64_C(28795), // VT_MASKCN |
| 3000 | UINT64_C(1208328279), // VUNZIPE_V |
| 3001 | UINT64_C(1208459351), // VUNZIPO_V |
| 3002 | UINT64_C(1476403287), // VWABDAU_VV |
| 3003 | UINT64_C(1409294423), // VWABDA_VV |
| 3004 | UINT64_C(3221233751), // VWADDU_VV |
| 3005 | UINT64_C(3221250135), // VWADDU_VX |
| 3006 | UINT64_C(3489669207), // VWADDU_WV |
| 3007 | UINT64_C(3489685591), // VWADDU_WX |
| 3008 | UINT64_C(3288342615), // VWADD_VV |
| 3009 | UINT64_C(3288358999), // VWADD_VX |
| 3010 | UINT64_C(3556778071), // VWADD_WV |
| 3011 | UINT64_C(3556794455), // VWADD_WX |
| 3012 | UINT64_C(4227866711), // VWMACCSU_VV |
| 3013 | UINT64_C(4227883095), // VWMACCSU_VX |
| 3014 | UINT64_C(4160774231), // VWMACCUS_VX |
| 3015 | UINT64_C(4026540119), // VWMACCU_VV |
| 3016 | UINT64_C(4026556503), // VWMACCU_VX |
| 3017 | UINT64_C(4093648983), // VWMACC_VV |
| 3018 | UINT64_C(4093665367), // VWMACC_VX |
| 3019 | UINT64_C(3892322391), // VWMULSU_VV |
| 3020 | UINT64_C(3892338775), // VWMULSU_VX |
| 3021 | UINT64_C(3758104663), // VWMULU_VV |
| 3022 | UINT64_C(3758121047), // VWMULU_VX |
| 3023 | UINT64_C(3959431255), // VWMUL_VV |
| 3024 | UINT64_C(3959447639), // VWMUL_VX |
| 3025 | UINT64_C(3221225559), // VWREDSUMU_VS |
| 3026 | UINT64_C(3288334423), // VWREDSUM_VS |
| 3027 | UINT64_C(3556782167), // VWSLL_VI |
| 3028 | UINT64_C(3556769879), // VWSLL_VV |
| 3029 | UINT64_C(3556786263), // VWSLL_VX |
| 3030 | UINT64_C(3355451479), // VWSUBU_VV |
| 3031 | UINT64_C(3355467863), // VWSUBU_VX |
| 3032 | UINT64_C(3623886935), // VWSUBU_WV |
| 3033 | UINT64_C(3623903319), // VWSUBU_WX |
| 3034 | UINT64_C(3422560343), // VWSUB_VV |
| 3035 | UINT64_C(3422576727), // VWSUB_VX |
| 3036 | UINT64_C(3690995799), // VWSUB_WV |
| 3037 | UINT64_C(3691012183), // VWSUB_WX |
| 3038 | UINT64_C(738209879), // VXOR_VI |
| 3039 | UINT64_C(738197591), // VXOR_VV |
| 3040 | UINT64_C(738213975), // VXOR_VX |
| 3041 | UINT64_C(1208164439), // VZEXT_VF2 |
| 3042 | UINT64_C(1208098903), // VZEXT_VF4 |
| 3043 | UINT64_C(1208033367), // VZEXT_VF8 |
| 3044 | UINT64_C(4160757847), // VZIP_VV |
| 3045 | UINT64_C(33562779), // WADD |
| 3046 | UINT64_C(167780507), // WADDA |
| 3047 | UINT64_C(436215963), // WADDAU |
| 3048 | UINT64_C(301998235), // WADDU |
| 3049 | UINT64_C(273678451), // WFI |
| 3050 | UINT64_C(704651419), // WMACC |
| 3051 | UINT64_C(1778393243), // WMACCSU |
| 3052 | UINT64_C(973086875), // WMACCU |
| 3053 | UINT64_C(570433691), // WMUL |
| 3054 | UINT64_C(1644175515), // WMULSU |
| 3055 | UINT64_C(838869147), // WMULU |
| 3056 | UINT64_C(13631603), // WRS_NTO |
| 3057 | UINT64_C(30408819), // WRS_STO |
| 3058 | UINT64_C(1308631067), // WSLA |
| 3059 | UINT64_C(1140858907), // WSLAI |
| 3060 | UINT64_C(234889243), // WSLL |
| 3061 | UINT64_C(67117083), // WSLLI |
| 3062 | UINT64_C(1107304603), // WSUB |
| 3063 | UINT64_C(1241522331), // WSUBA |
| 3064 | UINT64_C(1509957787), // WSUBAU |
| 3065 | UINT64_C(1375740059), // WSUBU |
| 3066 | UINT64_C(2046828571), // WZIP16P |
| 3067 | UINT64_C(2013274139), // WZIP8P |
| 3068 | UINT64_C(1073758259), // XNOR |
| 3069 | UINT64_C(16435), // XOR |
| 3070 | UINT64_C(16403), // XORI |
| 3071 | UINT64_C(671096883), // XPERM4 |
| 3072 | UINT64_C(671105075), // XPERM8 |
| 3073 | UINT64_C(134234163), // ZEXT_H_RV32 |
| 3074 | UINT64_C(134234171), // ZEXT_H_RV64 |
| 3075 | UINT64_C(4127203387), // ZIP16HP |
| 3076 | UINT64_C(4060094523), // ZIP16P |
| 3077 | UINT64_C(4093648955), // ZIP8HP |
| 3078 | UINT64_C(4026540091), // ZIP8P |
| 3079 | UINT64_C(149950483), // ZIP_RV32 |
| 3080 | }; |
| 3081 | constexpr unsigned FirstSupportedOpcode = 13729; |
| 3082 | |
| 3083 | const unsigned opcode = MI.getOpcode(); |
| 3084 | if (opcode < FirstSupportedOpcode) |
| 3085 | reportUnsupportedInst(Inst: MI); |
| 3086 | unsigned TableIndex = opcode - FirstSupportedOpcode; |
| 3087 | uint64_t Value = InstBits[TableIndex]; |
| 3088 | uint64_t op = 0; |
| 3089 | (void)op; // suppress warning |
| 3090 | switch (opcode) { |
| 3091 | case RISCV::C_EBREAK: |
| 3092 | case RISCV::C_MOP_11: |
| 3093 | case RISCV::C_MOP_13: |
| 3094 | case RISCV::C_MOP_15: |
| 3095 | case RISCV::C_MOP_3: |
| 3096 | case RISCV::C_MOP_7: |
| 3097 | case RISCV::C_MOP_9: |
| 3098 | case RISCV::C_NOP: |
| 3099 | case RISCV::C_SSPOPCHK: |
| 3100 | case RISCV::C_SSPUSH: |
| 3101 | case RISCV::C_UNIMP: |
| 3102 | case RISCV::DRET: |
| 3103 | case RISCV::EBREAK: |
| 3104 | case RISCV::ECALL: |
| 3105 | case RISCV::FENCE_I: |
| 3106 | case RISCV::FENCE_TSO: |
| 3107 | case RISCV::MIPS_EHB: |
| 3108 | case RISCV::MIPS_IHB: |
| 3109 | case RISCV::MIPS_PAUSE: |
| 3110 | case RISCV::MNRET: |
| 3111 | case RISCV::MRET: |
| 3112 | case RISCV::QC_C_DI: |
| 3113 | case RISCV::QC_C_EI: |
| 3114 | case RISCV::QC_C_MIENTER: |
| 3115 | case RISCV::QC_C_MIENTER_NEST: |
| 3116 | case RISCV::QC_C_MILEAVERET: |
| 3117 | case RISCV::QC_C_MNRET: |
| 3118 | case RISCV::QC_C_MRET: |
| 3119 | case RISCV::SCTRCLR: |
| 3120 | case RISCV::SFENCE_INVAL_IR: |
| 3121 | case RISCV::SFENCE_W_INVAL: |
| 3122 | case RISCV::SF_CEASE: |
| 3123 | case RISCV::SF_VTDISCARD: |
| 3124 | case RISCV::SRET: |
| 3125 | case RISCV::TH_DCACHE_CALL: |
| 3126 | case RISCV::TH_DCACHE_CIALL: |
| 3127 | case RISCV::TH_DCACHE_IALL: |
| 3128 | case RISCV::TH_ICACHE_IALL: |
| 3129 | case RISCV::TH_ICACHE_IALLS: |
| 3130 | case RISCV::TH_L2CACHE_CALL: |
| 3131 | case RISCV::TH_L2CACHE_CIALL: |
| 3132 | case RISCV::TH_L2CACHE_IALL: |
| 3133 | case RISCV::TH_SYNC: |
| 3134 | case RISCV::TH_SYNC_I: |
| 3135 | case RISCV::TH_SYNC_IS: |
| 3136 | case RISCV::TH_SYNC_S: |
| 3137 | case RISCV::UNIMP: |
| 3138 | case RISCV::WFI: |
| 3139 | case RISCV::WRS_NTO: |
| 3140 | case RISCV::WRS_STO: { |
| 3141 | break; |
| 3142 | } |
| 3143 | case RISCV::AIF_FSWG_PS: |
| 3144 | case RISCV::AIF_FSWL_PS: { |
| 3145 | // op: fs3 |
| 3146 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3147 | Value |= (op & 0x1f) << 7; |
| 3148 | // op: rs1 |
| 3149 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3150 | Value |= (op & 0x1f) << 15; |
| 3151 | break; |
| 3152 | } |
| 3153 | case RISCV::C_NOP_HINT: { |
| 3154 | // op: imm |
| 3155 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3156 | Value |= (op & 0x20) << 7; |
| 3157 | Value |= (op & 0x1f) << 2; |
| 3158 | break; |
| 3159 | } |
| 3160 | case RISCV::C_LI: |
| 3161 | case RISCV::C_LUI: { |
| 3162 | // op: imm |
| 3163 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3164 | Value |= (op & 0x20) << 7; |
| 3165 | Value |= (op & 0x1f) << 2; |
| 3166 | // op: rd |
| 3167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3168 | Value |= (op & 0x1f) << 7; |
| 3169 | break; |
| 3170 | } |
| 3171 | case RISCV::RI_VEXTRACT: { |
| 3172 | // op: imm |
| 3173 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3174 | Value |= (op & 0x1f) << 15; |
| 3175 | // op: vs2 |
| 3176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3177 | Value |= (op & 0x1f) << 20; |
| 3178 | // op: rd |
| 3179 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3180 | Value |= (op & 0x1f) << 7; |
| 3181 | break; |
| 3182 | } |
| 3183 | case RISCV::AIF_FSLLI_PI: |
| 3184 | case RISCV::AIF_FSRAI_PI: |
| 3185 | case RISCV::AIF_FSRLI_PI: { |
| 3186 | // op: imm |
| 3187 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3188 | Value |= (op & 0x1f) << 20; |
| 3189 | // op: rs1 |
| 3190 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3191 | Value |= (op & 0x1f) << 15; |
| 3192 | // op: rd |
| 3193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3194 | Value |= (op & 0x1f) << 7; |
| 3195 | break; |
| 3196 | } |
| 3197 | case RISCV::C_FLDSP: |
| 3198 | case RISCV::C_LDSP: |
| 3199 | case RISCV::C_LDSP_RV32: { |
| 3200 | // op: imm |
| 3201 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3202 | Value |= (op & 0x20) << 7; |
| 3203 | Value |= (op & 0x18) << 2; |
| 3204 | Value |= (op & 0x1c0) >> 4; |
| 3205 | // op: rd |
| 3206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3207 | Value |= (op & 0x1f) << 7; |
| 3208 | break; |
| 3209 | } |
| 3210 | case RISCV::C_FLWSP: |
| 3211 | case RISCV::C_LWSP: |
| 3212 | case RISCV::C_LWSP_INX: { |
| 3213 | // op: imm |
| 3214 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3215 | Value |= (op & 0x20) << 7; |
| 3216 | Value |= (op & 0x1c) << 2; |
| 3217 | Value |= (op & 0xc0) >> 4; |
| 3218 | // op: rd |
| 3219 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3220 | Value |= (op & 0x1f) << 7; |
| 3221 | break; |
| 3222 | } |
| 3223 | case RISCV::C_ADDI: |
| 3224 | case RISCV::C_ADDIW: { |
| 3225 | // op: imm |
| 3226 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3227 | Value |= (op & 0x20) << 7; |
| 3228 | Value |= (op & 0x1f) << 2; |
| 3229 | // op: rd |
| 3230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3231 | Value |= (op & 0x1f) << 7; |
| 3232 | break; |
| 3233 | } |
| 3234 | case RISCV::C_ANDI: { |
| 3235 | // op: imm |
| 3236 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3237 | Value |= (op & 0x20) << 7; |
| 3238 | Value |= (op & 0x1f) << 2; |
| 3239 | // op: rs1 |
| 3240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3241 | Value |= (op & 0x7) << 7; |
| 3242 | break; |
| 3243 | } |
| 3244 | case RISCV::C_ADDI16SP: { |
| 3245 | // op: imm |
| 3246 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3247 | Value |= (op & 0x200) << 3; |
| 3248 | Value |= (op & 0x10) << 2; |
| 3249 | Value |= (op & 0x40) >> 1; |
| 3250 | Value |= (op & 0x180) >> 4; |
| 3251 | Value |= (op & 0x20) >> 3; |
| 3252 | break; |
| 3253 | } |
| 3254 | case RISCV::C_ADDI4SPN: { |
| 3255 | // op: imm |
| 3256 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3257 | Value |= (op & 0x30) << 7; |
| 3258 | Value |= (op & 0x3c0) << 1; |
| 3259 | Value |= (op & 0x4) << 4; |
| 3260 | Value |= (op & 0x8) << 2; |
| 3261 | // op: rd |
| 3262 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3263 | Value |= (op & 0x7) << 2; |
| 3264 | break; |
| 3265 | } |
| 3266 | case RISCV::C_FSDSP: |
| 3267 | case RISCV::C_SDSP: |
| 3268 | case RISCV::C_SDSP_RV32: { |
| 3269 | // op: imm |
| 3270 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3271 | Value |= (op & 0x38) << 7; |
| 3272 | Value |= (op & 0x1c0) << 1; |
| 3273 | // op: rs2 |
| 3274 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3275 | Value |= (op & 0x1f) << 2; |
| 3276 | break; |
| 3277 | } |
| 3278 | case RISCV::C_FSWSP: |
| 3279 | case RISCV::C_SWSP: |
| 3280 | case RISCV::C_SWSP_INX: { |
| 3281 | // op: imm |
| 3282 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3283 | Value |= (op & 0x3c) << 7; |
| 3284 | Value |= (op & 0xc0) << 1; |
| 3285 | // op: rs2 |
| 3286 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3287 | Value |= (op & 0x1f) << 2; |
| 3288 | break; |
| 3289 | } |
| 3290 | case RISCV::AIF_FADDI_PI: |
| 3291 | case RISCV::AIF_FANDI_PI: { |
| 3292 | // op: imm |
| 3293 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3294 | Value |= (op & 0x3e0) << 22; |
| 3295 | Value |= (op & 0x1f) << 20; |
| 3296 | // op: rs1 |
| 3297 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3298 | Value |= (op & 0x1f) << 15; |
| 3299 | // op: rd |
| 3300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3301 | Value |= (op & 0x1f) << 7; |
| 3302 | break; |
| 3303 | } |
| 3304 | case RISCV::AIF_MOV_M_X: { |
| 3305 | // op: imm |
| 3306 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3307 | Value |= (op & 0xf8) << 17; |
| 3308 | Value |= (op & 0x7) << 12; |
| 3309 | // op: rs1 |
| 3310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3311 | Value |= (op & 0x1f) << 15; |
| 3312 | // op: rd |
| 3313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3314 | Value |= (op & 0x7) << 7; |
| 3315 | break; |
| 3316 | } |
| 3317 | case RISCV::RI_VINSERT: { |
| 3318 | // op: imm |
| 3319 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3320 | Value |= (op & 0x1f) << 20; |
| 3321 | // op: rs1 |
| 3322 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3323 | Value |= (op & 0x1f) << 15; |
| 3324 | // op: vd |
| 3325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3326 | Value |= (op & 0x1f) << 7; |
| 3327 | break; |
| 3328 | } |
| 3329 | case RISCV::AIF_MASKPOPC_ET_RAST: { |
| 3330 | // op: imm |
| 3331 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3332 | Value |= (op & 0xc) << 21; |
| 3333 | Value |= (op & 0x3) << 18; |
| 3334 | // op: rs2 |
| 3335 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3336 | Value |= (op & 0x7) << 20; |
| 3337 | // op: rs1 |
| 3338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3339 | Value |= (op & 0x7) << 15; |
| 3340 | // op: rd |
| 3341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3342 | Value |= (op & 0x1f) << 7; |
| 3343 | break; |
| 3344 | } |
| 3345 | case RISCV::C_BEQZ: |
| 3346 | case RISCV::C_BNEZ: { |
| 3347 | // op: imm |
| 3348 | op = getImmOpValueAsrN<1>(MI, OpNo: 1, Fixups, STI); |
| 3349 | Value |= (op & 0x80) << 5; |
| 3350 | Value |= (op & 0xc) << 8; |
| 3351 | Value |= (op & 0x60); |
| 3352 | Value |= (op & 0x3) << 3; |
| 3353 | Value |= (op & 0x10) >> 2; |
| 3354 | // op: rs1 |
| 3355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3356 | Value |= (op & 0x7) << 7; |
| 3357 | break; |
| 3358 | } |
| 3359 | case RISCV::C_SLLI: { |
| 3360 | // op: imm |
| 3361 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3362 | Value |= (op & 0x20) << 7; |
| 3363 | Value |= (op & 0x1f) << 2; |
| 3364 | // op: rd |
| 3365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3366 | Value |= (op & 0x1f) << 7; |
| 3367 | break; |
| 3368 | } |
| 3369 | case RISCV::C_SRAI: |
| 3370 | case RISCV::C_SRLI: { |
| 3371 | // op: imm |
| 3372 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3373 | Value |= (op & 0x20) << 7; |
| 3374 | Value |= (op & 0x1f) << 2; |
| 3375 | // op: rs1 |
| 3376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3377 | Value |= (op & 0x7) << 7; |
| 3378 | break; |
| 3379 | } |
| 3380 | case RISCV::QC_CLRINTI: |
| 3381 | case RISCV::QC_SETINTI: { |
| 3382 | // op: imm10 |
| 3383 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3384 | Value |= (op & 0x3ff) << 15; |
| 3385 | break; |
| 3386 | } |
| 3387 | case RISCV::NDS_BEQC: |
| 3388 | case RISCV::NDS_BNEC: { |
| 3389 | // op: imm10 |
| 3390 | op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI); |
| 3391 | Value |= (op & 0x200) << 22; |
| 3392 | Value |= (op & 0x1f0) << 21; |
| 3393 | Value |= (op & 0xf) << 8; |
| 3394 | // op: rs1 |
| 3395 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3396 | Value |= (op & 0x1f) << 15; |
| 3397 | // op: cimm |
| 3398 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3399 | Value |= (op & 0x40) << 24; |
| 3400 | Value |= (op & 0x1f) << 20; |
| 3401 | Value |= (op & 0x20) << 2; |
| 3402 | break; |
| 3403 | } |
| 3404 | case RISCV::NDS_BBC: |
| 3405 | case RISCV::NDS_BBS: { |
| 3406 | // op: imm10 |
| 3407 | op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI); |
| 3408 | Value |= (op & 0x200) << 22; |
| 3409 | Value |= (op & 0x1f0) << 21; |
| 3410 | Value |= (op & 0xf) << 8; |
| 3411 | // op: rs1 |
| 3412 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3413 | Value |= (op & 0x1f) << 15; |
| 3414 | // op: cimm |
| 3415 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3416 | Value |= (op & 0x1f) << 20; |
| 3417 | Value |= (op & 0x20) << 2; |
| 3418 | break; |
| 3419 | } |
| 3420 | case RISCV::PREFETCH_I: |
| 3421 | case RISCV::PREFETCH_R: |
| 3422 | case RISCV::PREFETCH_W: { |
| 3423 | // op: imm12 |
| 3424 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3425 | Value |= (op & 0xfe0) << 20; |
| 3426 | // op: rs1 |
| 3427 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3428 | Value |= (op & 0x1f) << 15; |
| 3429 | break; |
| 3430 | } |
| 3431 | case RISCV::AIF_FSQ2: |
| 3432 | case RISCV::AIF_FSW_PS: { |
| 3433 | // op: imm12 |
| 3434 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3435 | Value |= (op & 0xfe0) << 20; |
| 3436 | Value |= (op & 0x1f) << 7; |
| 3437 | // op: rs2 |
| 3438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3439 | Value |= (op & 0x1f) << 20; |
| 3440 | // op: rs1 |
| 3441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3442 | Value |= (op & 0x1f) << 15; |
| 3443 | break; |
| 3444 | } |
| 3445 | case RISCV::FSD: |
| 3446 | case RISCV::FSH: |
| 3447 | case RISCV::FSQ: |
| 3448 | case RISCV::FSW: |
| 3449 | case RISCV::SB: |
| 3450 | case RISCV::SD: |
| 3451 | case RISCV::SD_RV32: |
| 3452 | case RISCV::SH: |
| 3453 | case RISCV::SH_INX: |
| 3454 | case RISCV::SW: |
| 3455 | case RISCV::SW_INX: { |
| 3456 | // op: imm12 |
| 3457 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3458 | Value |= (op & 0xfe0) << 20; |
| 3459 | Value |= (op & 0x1f) << 7; |
| 3460 | // op: rs2 |
| 3461 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3462 | Value |= (op & 0x1f) << 20; |
| 3463 | // op: rs1 |
| 3464 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3465 | Value |= (op & 0x1f) << 15; |
| 3466 | break; |
| 3467 | } |
| 3468 | case RISCV::CV_SB_ri_inc: |
| 3469 | case RISCV::CV_SH_ri_inc: |
| 3470 | case RISCV::CV_SW_ri_inc: { |
| 3471 | // op: imm12 |
| 3472 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3473 | Value |= (op & 0xfe0) << 20; |
| 3474 | Value |= (op & 0x1f) << 7; |
| 3475 | // op: rs2 |
| 3476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3477 | Value |= (op & 0x1f) << 20; |
| 3478 | // op: rs1 |
| 3479 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3480 | Value |= (op & 0x1f) << 15; |
| 3481 | break; |
| 3482 | } |
| 3483 | case RISCV::BEQI: |
| 3484 | case RISCV::BNEI: { |
| 3485 | // op: imm12 |
| 3486 | op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI); |
| 3487 | Value |= (op & 0x800) << 20; |
| 3488 | Value |= (op & 0x3f0) << 21; |
| 3489 | Value |= (op & 0xf) << 8; |
| 3490 | Value |= (op & 0x400) >> 3; |
| 3491 | // op: cimm |
| 3492 | op = getImmOpValueZibi(MI, OpNo: 1, Fixups, STI); |
| 3493 | Value |= (op & 0x1f) << 20; |
| 3494 | // op: rs1 |
| 3495 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3496 | Value |= (op & 0x1f) << 15; |
| 3497 | break; |
| 3498 | } |
| 3499 | case RISCV::CV_BEQIMM: |
| 3500 | case RISCV::CV_BNEIMM: { |
| 3501 | // op: imm12 |
| 3502 | op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI); |
| 3503 | Value |= (op & 0x800) << 20; |
| 3504 | Value |= (op & 0x3f0) << 21; |
| 3505 | Value |= (op & 0xf) << 8; |
| 3506 | Value |= (op & 0x400) >> 3; |
| 3507 | // op: rs1 |
| 3508 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3509 | Value |= (op & 0x1f) << 15; |
| 3510 | // op: imm5 |
| 3511 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3512 | Value |= (op & 0x1f) << 20; |
| 3513 | break; |
| 3514 | } |
| 3515 | case RISCV::BEQ: |
| 3516 | case RISCV::BGE: |
| 3517 | case RISCV::BGEU: |
| 3518 | case RISCV::BLT: |
| 3519 | case RISCV::BLTU: |
| 3520 | case RISCV::BNE: |
| 3521 | case RISCV::QC_BEQI: |
| 3522 | case RISCV::QC_BGEI: |
| 3523 | case RISCV::QC_BGEUI: |
| 3524 | case RISCV::QC_BLTI: |
| 3525 | case RISCV::QC_BLTUI: |
| 3526 | case RISCV::QC_BNEI: { |
| 3527 | // op: imm12 |
| 3528 | op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI); |
| 3529 | Value |= (op & 0x800) << 20; |
| 3530 | Value |= (op & 0x3f0) << 21; |
| 3531 | Value |= (op & 0xf) << 8; |
| 3532 | Value |= (op & 0x400) >> 3; |
| 3533 | // op: rs2 |
| 3534 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3535 | Value |= (op & 0x1f) << 20; |
| 3536 | // op: rs1 |
| 3537 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3538 | Value |= (op & 0x1f) << 15; |
| 3539 | break; |
| 3540 | } |
| 3541 | case RISCV::NDS_SHGP: { |
| 3542 | // op: imm17 |
| 3543 | op = getImmOpValueAsrN<1>(MI, OpNo: 1, Fixups, STI); |
| 3544 | Value |= (op & 0x10000) << 15; |
| 3545 | Value |= (op & 0x3f0) << 21; |
| 3546 | Value |= (op & 0x3800) << 6; |
| 3547 | Value |= (op & 0xc000) << 1; |
| 3548 | Value |= (op & 0xf) << 8; |
| 3549 | Value |= (op & 0x400) >> 3; |
| 3550 | // op: rs2 |
| 3551 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3552 | Value |= (op & 0x1f) << 20; |
| 3553 | break; |
| 3554 | } |
| 3555 | case RISCV::NDS_LHGP: |
| 3556 | case RISCV::NDS_LHUGP: { |
| 3557 | // op: imm17 |
| 3558 | op = getImmOpValueAsrN<1>(MI, OpNo: 1, Fixups, STI); |
| 3559 | Value |= (op & 0x10000) << 15; |
| 3560 | Value |= (op & 0x3ff) << 21; |
| 3561 | Value |= (op & 0x400) << 10; |
| 3562 | Value |= (op & 0x3800) << 6; |
| 3563 | Value |= (op & 0xc000) << 1; |
| 3564 | // op: rd |
| 3565 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3566 | Value |= (op & 0x1f) << 7; |
| 3567 | break; |
| 3568 | } |
| 3569 | case RISCV::NDS_SWGP: { |
| 3570 | // op: imm17 |
| 3571 | op = getImmOpValueAsrN<2>(MI, OpNo: 1, Fixups, STI); |
| 3572 | Value |= (op & 0x10000) << 15; |
| 3573 | Value |= (op & 0x1f8) << 22; |
| 3574 | Value |= (op & 0x1c00) << 7; |
| 3575 | Value |= (op & 0x6000) << 2; |
| 3576 | Value |= (op & 0x7) << 9; |
| 3577 | Value |= (op & 0x8000) >> 7; |
| 3578 | Value |= (op & 0x200) >> 2; |
| 3579 | // op: rs2 |
| 3580 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3581 | Value |= (op & 0x1f) << 20; |
| 3582 | break; |
| 3583 | } |
| 3584 | case RISCV::NDS_LWGP: |
| 3585 | case RISCV::NDS_LWUGP: { |
| 3586 | // op: imm17 |
| 3587 | op = getImmOpValueAsrN<2>(MI, OpNo: 1, Fixups, STI); |
| 3588 | Value |= (op & 0x10000) << 15; |
| 3589 | Value |= (op & 0x1ff) << 22; |
| 3590 | Value |= (op & 0x8000) << 6; |
| 3591 | Value |= (op & 0x200) << 11; |
| 3592 | Value |= (op & 0x1c00) << 7; |
| 3593 | Value |= (op & 0x6000) << 2; |
| 3594 | // op: rd |
| 3595 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3596 | Value |= (op & 0x1f) << 7; |
| 3597 | break; |
| 3598 | } |
| 3599 | case RISCV::NDS_SDGP: { |
| 3600 | // op: imm17 |
| 3601 | op = getImmOpValueAsrN<3>(MI, OpNo: 1, Fixups, STI); |
| 3602 | Value |= (op & 0x10000) << 15; |
| 3603 | Value |= (op & 0xfc) << 23; |
| 3604 | Value |= (op & 0xe00) << 8; |
| 3605 | Value |= (op & 0x3000) << 3; |
| 3606 | Value |= (op & 0x3) << 10; |
| 3607 | Value |= (op & 0xc000) >> 6; |
| 3608 | Value |= (op & 0x100) >> 1; |
| 3609 | // op: rs2 |
| 3610 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3611 | Value |= (op & 0x1f) << 20; |
| 3612 | break; |
| 3613 | } |
| 3614 | case RISCV::NDS_LDGP: { |
| 3615 | // op: imm17 |
| 3616 | op = getImmOpValueAsrN<3>(MI, OpNo: 1, Fixups, STI); |
| 3617 | Value |= (op & 0x10000) << 15; |
| 3618 | Value |= (op & 0xff) << 23; |
| 3619 | Value |= (op & 0xc000) << 7; |
| 3620 | Value |= (op & 0x100) << 12; |
| 3621 | Value |= (op & 0xe00) << 8; |
| 3622 | Value |= (op & 0x3000) << 3; |
| 3623 | // op: rd |
| 3624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3625 | Value |= (op & 0x1f) << 7; |
| 3626 | break; |
| 3627 | } |
| 3628 | case RISCV::NDS_SBGP: { |
| 3629 | // op: imm18 |
| 3630 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3631 | Value |= (op & 0x20000) << 14; |
| 3632 | Value |= (op & 0x7e0) << 20; |
| 3633 | Value |= (op & 0x7000) << 5; |
| 3634 | Value |= (op & 0x18000); |
| 3635 | Value |= (op & 0x1) << 14; |
| 3636 | Value |= (op & 0x1e) << 7; |
| 3637 | Value |= (op & 0x800) >> 4; |
| 3638 | // op: rs2 |
| 3639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3640 | Value |= (op & 0x1f) << 20; |
| 3641 | break; |
| 3642 | } |
| 3643 | case RISCV::NDS_ADDIGP: |
| 3644 | case RISCV::NDS_LBGP: |
| 3645 | case RISCV::NDS_LBUGP: { |
| 3646 | // op: imm18 |
| 3647 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3648 | Value |= (op & 0x20000) << 14; |
| 3649 | Value |= (op & 0x7fe) << 20; |
| 3650 | Value |= (op & 0x800) << 9; |
| 3651 | Value |= (op & 0x7000) << 5; |
| 3652 | Value |= (op & 0x18000); |
| 3653 | Value |= (op & 0x1) << 14; |
| 3654 | // op: rd |
| 3655 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3656 | Value |= (op & 0x1f) << 7; |
| 3657 | break; |
| 3658 | } |
| 3659 | case RISCV::QC_LI: { |
| 3660 | // op: imm20 |
| 3661 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3662 | Value |= (op & 0x80000) << 12; |
| 3663 | Value |= (op & 0x7fff) << 16; |
| 3664 | Value |= (op & 0x78000) >> 3; |
| 3665 | // op: rd |
| 3666 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3667 | Value |= (op & 0x1f) << 7; |
| 3668 | break; |
| 3669 | } |
| 3670 | case RISCV::AIF_FBCI_PI: |
| 3671 | case RISCV::AIF_FBCI_PS: |
| 3672 | case RISCV::AUIPC: |
| 3673 | case RISCV::LUI: { |
| 3674 | // op: imm20 |
| 3675 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3676 | Value |= (op & 0xfffff) << 12; |
| 3677 | // op: rd |
| 3678 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3679 | Value |= (op & 0x1f) << 7; |
| 3680 | break; |
| 3681 | } |
| 3682 | case RISCV::JAL: { |
| 3683 | // op: imm20 |
| 3684 | op = getImmOpValueAsrN<1>(MI, OpNo: 1, Fixups, STI); |
| 3685 | Value |= (op & 0x80000) << 12; |
| 3686 | Value |= (op & 0x3ff) << 21; |
| 3687 | Value |= (op & 0x400) << 10; |
| 3688 | Value |= (op & 0x7f800) << 1; |
| 3689 | // op: rd |
| 3690 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3691 | Value |= (op & 0x1f) << 7; |
| 3692 | break; |
| 3693 | } |
| 3694 | case RISCV::QC_E_J: |
| 3695 | case RISCV::QC_E_JAL: { |
| 3696 | // op: imm31 |
| 3697 | op = getImmOpValueAsrN<1>(MI, OpNo: 0, Fixups, STI); |
| 3698 | Value |= (op & 0x7fff8000) << 17; |
| 3699 | Value |= (op & 0x800) << 20; |
| 3700 | Value |= (op & 0x3f0) << 21; |
| 3701 | Value |= (op & 0x7000) << 5; |
| 3702 | Value |= (op & 0xf) << 8; |
| 3703 | Value |= (op & 0x400) >> 3; |
| 3704 | break; |
| 3705 | } |
| 3706 | case RISCV::QC_SYNC: |
| 3707 | case RISCV::QC_SYNCR: |
| 3708 | case RISCV::QC_SYNCWF: |
| 3709 | case RISCV::QC_SYNCWL: { |
| 3710 | // op: imm5 |
| 3711 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3712 | Value |= (op & 0x1f) << 20; |
| 3713 | break; |
| 3714 | } |
| 3715 | case RISCV::MIPS_SDP: { |
| 3716 | // op: imm7 |
| 3717 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3718 | Value |= (op & 0x60) << 20; |
| 3719 | Value |= (op & 0x18) << 7; |
| 3720 | // op: rs3 |
| 3721 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3722 | Value |= (op & 0x1f) << 27; |
| 3723 | // op: rs2 |
| 3724 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3725 | Value |= (op & 0x1f) << 20; |
| 3726 | // op: rs1 |
| 3727 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3728 | Value |= (op & 0x1f) << 15; |
| 3729 | break; |
| 3730 | } |
| 3731 | case RISCV::MIPS_SWP: { |
| 3732 | // op: imm7 |
| 3733 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3734 | Value |= (op & 0x60) << 20; |
| 3735 | Value |= (op & 0x1c) << 7; |
| 3736 | // op: rs3 |
| 3737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3738 | Value |= (op & 0x1f) << 27; |
| 3739 | // op: rs2 |
| 3740 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3741 | Value |= (op & 0x1f) << 20; |
| 3742 | // op: rs1 |
| 3743 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3744 | Value |= (op & 0x1f) << 15; |
| 3745 | break; |
| 3746 | } |
| 3747 | case RISCV::MIPS_LDP: { |
| 3748 | // op: imm7 |
| 3749 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3750 | Value |= (op & 0x78) << 20; |
| 3751 | // op: rs1 |
| 3752 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3753 | Value |= (op & 0x1f) << 15; |
| 3754 | // op: rd1 |
| 3755 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3756 | Value |= (op & 0x1f) << 7; |
| 3757 | // op: rd2 |
| 3758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3759 | Value |= (op & 0x1f) << 27; |
| 3760 | break; |
| 3761 | } |
| 3762 | case RISCV::MIPS_LWP: { |
| 3763 | // op: imm7 |
| 3764 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3765 | Value |= (op & 0x7c) << 20; |
| 3766 | // op: rs1 |
| 3767 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3768 | Value |= (op & 0x1f) << 15; |
| 3769 | // op: rd1 |
| 3770 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3771 | Value |= (op & 0x1f) << 7; |
| 3772 | // op: rd2 |
| 3773 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3774 | Value |= (op & 0x1f) << 27; |
| 3775 | break; |
| 3776 | } |
| 3777 | case RISCV::QC_PPUTCI: { |
| 3778 | // op: imm8 |
| 3779 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3780 | Value |= (op & 0xff) << 20; |
| 3781 | break; |
| 3782 | } |
| 3783 | case RISCV::MIPS_PREF: { |
| 3784 | // op: imm9 |
| 3785 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3786 | Value |= (op & 0x1ff) << 20; |
| 3787 | // op: rs1 |
| 3788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3789 | Value |= (op & 0x1f) << 15; |
| 3790 | // op: hint |
| 3791 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3792 | Value |= (op & 0x1f) << 7; |
| 3793 | break; |
| 3794 | } |
| 3795 | case RISCV::CM_JT: { |
| 3796 | // op: index |
| 3797 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3798 | Value |= (op & 0x1f) << 2; |
| 3799 | break; |
| 3800 | } |
| 3801 | case RISCV::CM_JALT: { |
| 3802 | // op: index |
| 3803 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3804 | Value |= (op & 0xff) << 2; |
| 3805 | break; |
| 3806 | } |
| 3807 | case RISCV::C_J: |
| 3808 | case RISCV::C_JAL: { |
| 3809 | // op: offset |
| 3810 | op = getImmOpValueAsrN<1>(MI, OpNo: 0, Fixups, STI); |
| 3811 | Value |= (op & 0x400) << 2; |
| 3812 | Value |= (op & 0x8) << 8; |
| 3813 | Value |= (op & 0x180) << 2; |
| 3814 | Value |= (op & 0x200) >> 1; |
| 3815 | Value |= (op & 0x20) << 2; |
| 3816 | Value |= (op & 0x40); |
| 3817 | Value |= (op & 0x7) << 3; |
| 3818 | Value |= (op & 0x10) >> 2; |
| 3819 | break; |
| 3820 | } |
| 3821 | case RISCV::InsnCJ: { |
| 3822 | // op: opcode |
| 3823 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3824 | Value |= (op & 0x3); |
| 3825 | // op: funct3 |
| 3826 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3827 | Value |= (op & 0x7) << 13; |
| 3828 | // op: imm11 |
| 3829 | op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI); |
| 3830 | Value |= (op & 0x400) << 2; |
| 3831 | Value |= (op & 0x8) << 8; |
| 3832 | Value |= (op & 0x180) << 2; |
| 3833 | Value |= (op & 0x200) >> 1; |
| 3834 | Value |= (op & 0x20) << 2; |
| 3835 | Value |= (op & 0x40); |
| 3836 | Value |= (op & 0x7) << 3; |
| 3837 | Value |= (op & 0x10) >> 2; |
| 3838 | break; |
| 3839 | } |
| 3840 | case RISCV::InsnCS: { |
| 3841 | // op: opcode |
| 3842 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3843 | Value |= (op & 0x3); |
| 3844 | // op: funct3 |
| 3845 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3846 | Value |= (op & 0x7) << 13; |
| 3847 | // op: imm5 |
| 3848 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 3849 | Value |= (op & 0x1c) << 8; |
| 3850 | Value |= (op & 0x3) << 5; |
| 3851 | // op: rs2 |
| 3852 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3853 | Value |= (op & 0x7) << 2; |
| 3854 | // op: rs1 |
| 3855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3856 | Value |= (op & 0x7) << 7; |
| 3857 | break; |
| 3858 | } |
| 3859 | case RISCV::InsnCSS: { |
| 3860 | // op: opcode |
| 3861 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3862 | Value |= (op & 0x3); |
| 3863 | // op: funct3 |
| 3864 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3865 | Value |= (op & 0x7) << 13; |
| 3866 | // op: imm6 |
| 3867 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3868 | Value |= (op & 0x3f) << 7; |
| 3869 | // op: rs2 |
| 3870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3871 | Value |= (op & 0x1f) << 2; |
| 3872 | break; |
| 3873 | } |
| 3874 | case RISCV::InsnCB: { |
| 3875 | // op: opcode |
| 3876 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3877 | Value |= (op & 0x3); |
| 3878 | // op: funct3 |
| 3879 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3880 | Value |= (op & 0x7) << 13; |
| 3881 | // op: imm8 |
| 3882 | op = getImmOpValueAsrN<1>(MI, OpNo: 3, Fixups, STI); |
| 3883 | Value |= (op & 0x80) << 5; |
| 3884 | Value |= (op & 0xc) << 8; |
| 3885 | Value |= (op & 0x60); |
| 3886 | Value |= (op & 0x3) << 3; |
| 3887 | Value |= (op & 0x10) >> 2; |
| 3888 | // op: rs1 |
| 3889 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3890 | Value |= (op & 0x7) << 7; |
| 3891 | break; |
| 3892 | } |
| 3893 | case RISCV::InsnQC_EJ: { |
| 3894 | // op: opcode |
| 3895 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3896 | Value |= (op & 0x7f); |
| 3897 | // op: func3 |
| 3898 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3899 | Value |= (op & 0x7) << 12; |
| 3900 | // op: func2 |
| 3901 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3902 | Value |= (op & 0x3) << 15; |
| 3903 | // op: func5 |
| 3904 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 3905 | Value |= (op & 0x1f) << 20; |
| 3906 | // op: imm31 |
| 3907 | op = getImmOpValueAsrN<1>(MI, OpNo: 4, Fixups, STI); |
| 3908 | Value |= (op & 0x7fff8000) << 17; |
| 3909 | Value |= (op & 0x800) << 20; |
| 3910 | Value |= (op & 0x3f0) << 21; |
| 3911 | Value |= (op & 0x7000) << 5; |
| 3912 | Value |= (op & 0xf) << 8; |
| 3913 | Value |= (op & 0x400) >> 3; |
| 3914 | break; |
| 3915 | } |
| 3916 | case RISCV::InsnQC_ES: { |
| 3917 | // op: opcode |
| 3918 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3919 | Value |= (op & 0x7f); |
| 3920 | // op: func3 |
| 3921 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3922 | Value |= (op & 0x7) << 12; |
| 3923 | // op: func2 |
| 3924 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3925 | Value |= (op & 0x3) << 30; |
| 3926 | // op: rs1 |
| 3927 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3928 | Value |= (op & 0x1f) << 15; |
| 3929 | // op: rs2 |
| 3930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3931 | Value |= (op & 0x1f) << 20; |
| 3932 | // op: imm26 |
| 3933 | op = getImmOpValue(MI, OpNo: 5, Fixups, STI); |
| 3934 | Value |= (op & 0x3fffc00) << 22; |
| 3935 | Value |= (op & 0x3e0) << 20; |
| 3936 | Value |= (op & 0x1f) << 7; |
| 3937 | break; |
| 3938 | } |
| 3939 | case RISCV::InsnQC_EB: { |
| 3940 | // op: opcode |
| 3941 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3942 | Value |= (op & 0x7f); |
| 3943 | // op: func3 |
| 3944 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3945 | Value |= (op & 0x7) << 12; |
| 3946 | // op: func5 |
| 3947 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 3948 | Value |= (op & 0x1f) << 20; |
| 3949 | // op: rs1 |
| 3950 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3951 | Value |= (op & 0x1f) << 15; |
| 3952 | // op: imm12 |
| 3953 | op = getImmOpValueAsrN<1>(MI, OpNo: 5, Fixups, STI); |
| 3954 | Value |= (op & 0x800) << 20; |
| 3955 | Value |= (op & 0x3f0) << 21; |
| 3956 | Value |= (op & 0xf) << 8; |
| 3957 | Value |= (op & 0x400) >> 3; |
| 3958 | // op: imm16 |
| 3959 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 3960 | Value |= (op & 0xffff) << 32; |
| 3961 | break; |
| 3962 | } |
| 3963 | case RISCV::InsnS: { |
| 3964 | // op: opcode |
| 3965 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3966 | Value |= (op & 0x7f); |
| 3967 | // op: funct3 |
| 3968 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3969 | Value |= (op & 0x7) << 12; |
| 3970 | // op: imm12 |
| 3971 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 3972 | Value |= (op & 0xfe0) << 20; |
| 3973 | Value |= (op & 0x1f) << 7; |
| 3974 | // op: rs2 |
| 3975 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3976 | Value |= (op & 0x1f) << 20; |
| 3977 | // op: rs1 |
| 3978 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3979 | Value |= (op & 0x1f) << 15; |
| 3980 | break; |
| 3981 | } |
| 3982 | case RISCV::InsnB: { |
| 3983 | // op: opcode |
| 3984 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 3985 | Value |= (op & 0x7f); |
| 3986 | // op: funct3 |
| 3987 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 3988 | Value |= (op & 0x7) << 12; |
| 3989 | // op: imm12 |
| 3990 | op = getImmOpValueAsrN<1>(MI, OpNo: 4, Fixups, STI); |
| 3991 | Value |= (op & 0x800) << 20; |
| 3992 | Value |= (op & 0x3f0) << 21; |
| 3993 | Value |= (op & 0xf) << 8; |
| 3994 | Value |= (op & 0x400) >> 3; |
| 3995 | // op: rs2 |
| 3996 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3997 | Value |= (op & 0x1f) << 20; |
| 3998 | // op: rs1 |
| 3999 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4000 | Value |= (op & 0x1f) << 15; |
| 4001 | break; |
| 4002 | } |
| 4003 | case RISCV::InsnCL: { |
| 4004 | // op: opcode |
| 4005 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4006 | Value |= (op & 0x3); |
| 4007 | // op: funct3 |
| 4008 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4009 | Value |= (op & 0x7) << 13; |
| 4010 | // op: imm5 |
| 4011 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 4012 | Value |= (op & 0x1c) << 8; |
| 4013 | Value |= (op & 0x3) << 5; |
| 4014 | // op: rd |
| 4015 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4016 | Value |= (op & 0x7) << 2; |
| 4017 | // op: rs1 |
| 4018 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4019 | Value |= (op & 0x7) << 7; |
| 4020 | break; |
| 4021 | } |
| 4022 | case RISCV::InsnCI: { |
| 4023 | // op: opcode |
| 4024 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4025 | Value |= (op & 0x3); |
| 4026 | // op: funct3 |
| 4027 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4028 | Value |= (op & 0x7) << 13; |
| 4029 | // op: imm6 |
| 4030 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 4031 | Value |= (op & 0x20) << 7; |
| 4032 | Value |= (op & 0x1f) << 2; |
| 4033 | // op: rd |
| 4034 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4035 | Value |= (op & 0x1f) << 7; |
| 4036 | break; |
| 4037 | } |
| 4038 | case RISCV::InsnCIW: { |
| 4039 | // op: opcode |
| 4040 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4041 | Value |= (op & 0x3); |
| 4042 | // op: funct3 |
| 4043 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4044 | Value |= (op & 0x7) << 13; |
| 4045 | // op: imm8 |
| 4046 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 4047 | Value |= (op & 0xff) << 5; |
| 4048 | // op: rd |
| 4049 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4050 | Value |= (op & 0x7) << 2; |
| 4051 | break; |
| 4052 | } |
| 4053 | case RISCV::InsnCR: { |
| 4054 | // op: opcode |
| 4055 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4056 | Value |= (op & 0x3); |
| 4057 | // op: funct4 |
| 4058 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4059 | Value |= (op & 0xf) << 12; |
| 4060 | // op: rs2 |
| 4061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4062 | Value |= (op & 0x1f) << 2; |
| 4063 | // op: rd |
| 4064 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4065 | Value |= (op & 0x1f) << 7; |
| 4066 | break; |
| 4067 | } |
| 4068 | case RISCV::InsnCA: { |
| 4069 | // op: opcode |
| 4070 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4071 | Value |= (op & 0x3); |
| 4072 | // op: funct6 |
| 4073 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4074 | Value |= (op & 0x3f) << 10; |
| 4075 | // op: funct2 |
| 4076 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 4077 | Value |= (op & 0x3) << 5; |
| 4078 | // op: rd |
| 4079 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4080 | Value |= (op & 0x7) << 7; |
| 4081 | // op: rs2 |
| 4082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4083 | Value |= (op & 0x7) << 2; |
| 4084 | break; |
| 4085 | } |
| 4086 | case RISCV::InsnQC_EAI: { |
| 4087 | // op: opcode |
| 4088 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4089 | Value |= (op & 0x7f); |
| 4090 | // op: func3 |
| 4091 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4092 | Value |= (op & 0x7) << 12; |
| 4093 | // op: func1 |
| 4094 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 4095 | Value |= (op & 0x1) << 15; |
| 4096 | // op: rd |
| 4097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4098 | Value |= (op & 0x1f) << 7; |
| 4099 | // op: imm32 |
| 4100 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 4101 | Value |= (op & 0xffffffff) << 16; |
| 4102 | break; |
| 4103 | } |
| 4104 | case RISCV::InsnQC_EI: |
| 4105 | case RISCV::InsnQC_EI_Mem: { |
| 4106 | // op: opcode |
| 4107 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4108 | Value |= (op & 0x7f); |
| 4109 | // op: func3 |
| 4110 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4111 | Value |= (op & 0x7) << 12; |
| 4112 | // op: func2 |
| 4113 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 4114 | Value |= (op & 0x3) << 30; |
| 4115 | // op: rd |
| 4116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4117 | Value |= (op & 0x1f) << 7; |
| 4118 | // op: rs1 |
| 4119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4120 | Value |= (op & 0x1f) << 15; |
| 4121 | // op: imm26 |
| 4122 | op = getImmOpValue(MI, OpNo: 5, Fixups, STI); |
| 4123 | Value |= (op & 0x3fffc00) << 22; |
| 4124 | Value |= (op & 0x3ff) << 20; |
| 4125 | break; |
| 4126 | } |
| 4127 | case RISCV::InsnR4: { |
| 4128 | // op: opcode |
| 4129 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4130 | Value |= (op & 0x7f); |
| 4131 | // op: funct2 |
| 4132 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 4133 | Value |= (op & 0x3) << 25; |
| 4134 | // op: funct3 |
| 4135 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4136 | Value |= (op & 0x7) << 12; |
| 4137 | // op: rs3 |
| 4138 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 4139 | Value |= (op & 0x1f) << 27; |
| 4140 | // op: rs2 |
| 4141 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 4142 | Value |= (op & 0x1f) << 20; |
| 4143 | // op: rs1 |
| 4144 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4145 | Value |= (op & 0x1f) << 15; |
| 4146 | // op: rd |
| 4147 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4148 | Value |= (op & 0x1f) << 7; |
| 4149 | break; |
| 4150 | } |
| 4151 | case RISCV::InsnI: |
| 4152 | case RISCV::InsnI_Mem: { |
| 4153 | // op: opcode |
| 4154 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4155 | Value |= (op & 0x7f); |
| 4156 | // op: funct3 |
| 4157 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4158 | Value |= (op & 0x7) << 12; |
| 4159 | // op: imm12 |
| 4160 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 4161 | Value |= (op & 0xfff) << 20; |
| 4162 | // op: rs1 |
| 4163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4164 | Value |= (op & 0x1f) << 15; |
| 4165 | // op: rd |
| 4166 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4167 | Value |= (op & 0x1f) << 7; |
| 4168 | break; |
| 4169 | } |
| 4170 | case RISCV::InsnR: { |
| 4171 | // op: opcode |
| 4172 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4173 | Value |= (op & 0x7f); |
| 4174 | // op: funct7 |
| 4175 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 4176 | Value |= (op & 0x7f) << 25; |
| 4177 | // op: funct3 |
| 4178 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4179 | Value |= (op & 0x7) << 12; |
| 4180 | // op: rs2 |
| 4181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 4182 | Value |= (op & 0x1f) << 20; |
| 4183 | // op: rs1 |
| 4184 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4185 | Value |= (op & 0x1f) << 15; |
| 4186 | // op: rd |
| 4187 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4188 | Value |= (op & 0x1f) << 7; |
| 4189 | break; |
| 4190 | } |
| 4191 | case RISCV::InsnU: { |
| 4192 | // op: opcode |
| 4193 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4194 | Value |= (op & 0x7f); |
| 4195 | // op: imm20 |
| 4196 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4197 | Value |= (op & 0xfffff) << 12; |
| 4198 | // op: rd |
| 4199 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4200 | Value |= (op & 0x1f) << 7; |
| 4201 | break; |
| 4202 | } |
| 4203 | case RISCV::InsnJ: { |
| 4204 | // op: opcode |
| 4205 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4206 | Value |= (op & 0x7f); |
| 4207 | // op: imm20 |
| 4208 | op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI); |
| 4209 | Value |= (op & 0xfffff) << 12; |
| 4210 | // op: rd |
| 4211 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4212 | Value |= (op & 0x1f) << 7; |
| 4213 | break; |
| 4214 | } |
| 4215 | case RISCV::FENCE: { |
| 4216 | // op: pred |
| 4217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4218 | Value |= (op & 0xf) << 24; |
| 4219 | // op: succ |
| 4220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4221 | Value |= (op & 0xf) << 20; |
| 4222 | break; |
| 4223 | } |
| 4224 | case RISCV::PLUI_DH: { |
| 4225 | // op: rd |
| 4226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4227 | Value |= (op & 0x1e) << 7; |
| 4228 | // op: imm10 |
| 4229 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4230 | Value |= (op & 0x1) << 24; |
| 4231 | Value |= (op & 0x3fe) << 14; |
| 4232 | break; |
| 4233 | } |
| 4234 | case RISCV::PLI_DH: { |
| 4235 | // op: rd |
| 4236 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4237 | Value |= (op & 0x1e) << 7; |
| 4238 | // op: imm10 |
| 4239 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4240 | Value |= (op & 0x1ff) << 16; |
| 4241 | Value |= (op & 0x200) << 6; |
| 4242 | break; |
| 4243 | } |
| 4244 | case RISCV::PLI_DB: { |
| 4245 | // op: rd |
| 4246 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4247 | Value |= (op & 0x1e) << 7; |
| 4248 | // op: imm8 |
| 4249 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4250 | Value |= (op & 0xff) << 16; |
| 4251 | break; |
| 4252 | } |
| 4253 | case RISCV::AIF_MOVA_X_M: |
| 4254 | case RISCV::QC_C_DIR: |
| 4255 | case RISCV::SSRDP: { |
| 4256 | // op: rd |
| 4257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4258 | Value |= (op & 0x1f) << 7; |
| 4259 | break; |
| 4260 | } |
| 4261 | case RISCV::QC_E_LI: { |
| 4262 | // op: rd |
| 4263 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4264 | Value |= (op & 0x1f) << 7; |
| 4265 | // op: imm |
| 4266 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4267 | Value |= (op & 0xffffffff) << 16; |
| 4268 | break; |
| 4269 | } |
| 4270 | case RISCV::FLI_D: |
| 4271 | case RISCV::FLI_H: |
| 4272 | case RISCV::FLI_Q: |
| 4273 | case RISCV::FLI_S: { |
| 4274 | // op: rd |
| 4275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4276 | Value |= (op & 0x1f) << 7; |
| 4277 | // op: imm |
| 4278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4279 | Value |= (op & 0x1f) << 15; |
| 4280 | break; |
| 4281 | } |
| 4282 | case RISCV::PLUI_H: |
| 4283 | case RISCV::PLUI_W: { |
| 4284 | // op: rd |
| 4285 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4286 | Value |= (op & 0x1f) << 7; |
| 4287 | // op: imm10 |
| 4288 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4289 | Value |= (op & 0x1) << 24; |
| 4290 | Value |= (op & 0x3fe) << 14; |
| 4291 | break; |
| 4292 | } |
| 4293 | case RISCV::PLI_H: |
| 4294 | case RISCV::PLI_W: { |
| 4295 | // op: rd |
| 4296 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4297 | Value |= (op & 0x1f) << 7; |
| 4298 | // op: imm10 |
| 4299 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4300 | Value |= (op & 0x1ff) << 16; |
| 4301 | Value |= (op & 0x200) << 6; |
| 4302 | break; |
| 4303 | } |
| 4304 | case RISCV::PLI_B: { |
| 4305 | // op: rd |
| 4306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4307 | Value |= (op & 0x1f) << 7; |
| 4308 | // op: imm8 |
| 4309 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4310 | Value |= (op & 0xff) << 16; |
| 4311 | break; |
| 4312 | } |
| 4313 | case RISCV::AIF_FMVS_X_PS: |
| 4314 | case RISCV::AIF_FMVZ_X_PS: { |
| 4315 | // op: rd |
| 4316 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4317 | Value |= (op & 0x1f) << 7; |
| 4318 | // op: rs1 |
| 4319 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4320 | Value |= (op & 0x1f) << 15; |
| 4321 | // op: idx |
| 4322 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4323 | Value |= (op & 0x7) << 20; |
| 4324 | break; |
| 4325 | } |
| 4326 | case RISCV::QC_E_ADDI: |
| 4327 | case RISCV::QC_E_ANDI: |
| 4328 | case RISCV::QC_E_LB: |
| 4329 | case RISCV::QC_E_LBU: |
| 4330 | case RISCV::QC_E_LH: |
| 4331 | case RISCV::QC_E_LHU: |
| 4332 | case RISCV::QC_E_LW: |
| 4333 | case RISCV::QC_E_ORI: |
| 4334 | case RISCV::QC_E_XORI: { |
| 4335 | // op: rd |
| 4336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4337 | Value |= (op & 0x1f) << 7; |
| 4338 | // op: rs1 |
| 4339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4340 | Value |= (op & 0x1f) << 15; |
| 4341 | // op: imm |
| 4342 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4343 | Value |= (op & 0x3fffc00) << 22; |
| 4344 | Value |= (op & 0x3ff) << 20; |
| 4345 | break; |
| 4346 | } |
| 4347 | case RISCV::AIF_FSWIZZ_PS: { |
| 4348 | // op: rd |
| 4349 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4350 | Value |= (op & 0x1f) << 7; |
| 4351 | // op: rs1 |
| 4352 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4353 | Value |= (op & 0x1f) << 15; |
| 4354 | // op: imm |
| 4355 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4356 | Value |= (op & 0xf8) << 17; |
| 4357 | Value |= (op & 0x7) << 12; |
| 4358 | break; |
| 4359 | } |
| 4360 | case RISCV::NDS_BFOS: |
| 4361 | case RISCV::NDS_BFOZ: { |
| 4362 | // op: rd |
| 4363 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4364 | Value |= (op & 0x1f) << 7; |
| 4365 | // op: rs1 |
| 4366 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4367 | Value |= (op & 0x1f) << 15; |
| 4368 | // op: msb |
| 4369 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4370 | Value |= (op & 0x3f) << 26; |
| 4371 | // op: lsb |
| 4372 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4373 | Value |= (op & 0x3f) << 20; |
| 4374 | break; |
| 4375 | } |
| 4376 | case RISCV::AIF_FCVT_PS_PW: |
| 4377 | case RISCV::AIF_FCVT_PS_PWU: |
| 4378 | case RISCV::AIF_FCVT_PWU_PS: |
| 4379 | case RISCV::AIF_FCVT_PW_PS: { |
| 4380 | // op: rd |
| 4381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4382 | Value |= (op & 0x1f) << 7; |
| 4383 | // op: rs1 |
| 4384 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4385 | Value |= (op & 0x1f) << 15; |
| 4386 | // op: rm |
| 4387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4388 | Value |= (op & 0x7) << 12; |
| 4389 | break; |
| 4390 | } |
| 4391 | case RISCV::AIF_FADD_PS: |
| 4392 | case RISCV::AIF_FDIV_PS: |
| 4393 | case RISCV::AIF_FMUL_PS: |
| 4394 | case RISCV::AIF_FSUB_PS: { |
| 4395 | // op: rd |
| 4396 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4397 | Value |= (op & 0x1f) << 7; |
| 4398 | // op: rs1 |
| 4399 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4400 | Value |= (op & 0x1f) << 15; |
| 4401 | // op: rs2 |
| 4402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4403 | Value |= (op & 0x1f) << 20; |
| 4404 | // op: rm |
| 4405 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4406 | Value |= (op & 0x7) << 12; |
| 4407 | break; |
| 4408 | } |
| 4409 | case RISCV::AIF_FCMOV_PS: { |
| 4410 | // op: rd |
| 4411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4412 | Value |= (op & 0x1f) << 7; |
| 4413 | // op: rs1 |
| 4414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4415 | Value |= (op & 0x1f) << 15; |
| 4416 | // op: rs2 |
| 4417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4418 | Value |= (op & 0x1f) << 20; |
| 4419 | // op: rs3 |
| 4420 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4421 | Value |= (op & 0x1f) << 27; |
| 4422 | break; |
| 4423 | } |
| 4424 | case RISCV::AIF_FMADD_PS: |
| 4425 | case RISCV::AIF_FMSUB_PS: |
| 4426 | case RISCV::AIF_FNMADD_PS: |
| 4427 | case RISCV::AIF_FNMSUB_PS: { |
| 4428 | // op: rd |
| 4429 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4430 | Value |= (op & 0x1f) << 7; |
| 4431 | // op: rs1 |
| 4432 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4433 | Value |= (op & 0x1f) << 15; |
| 4434 | // op: rs2 |
| 4435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4436 | Value |= (op & 0x1f) << 20; |
| 4437 | // op: rs3 |
| 4438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4439 | Value |= (op & 0x1f) << 27; |
| 4440 | // op: rm |
| 4441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4442 | Value |= (op & 0x7) << 12; |
| 4443 | break; |
| 4444 | } |
| 4445 | case RISCV::VSETIVLI: { |
| 4446 | // op: rd |
| 4447 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4448 | Value |= (op & 0x1f) << 7; |
| 4449 | // op: uimm |
| 4450 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 4451 | Value |= (op & 0x1f) << 15; |
| 4452 | // op: vtypei |
| 4453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4454 | Value |= (op & 0x3ff) << 20; |
| 4455 | break; |
| 4456 | } |
| 4457 | case RISCV::VCPOP_M: |
| 4458 | case RISCV::VFIRST_M: { |
| 4459 | // op: rd |
| 4460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4461 | Value |= (op & 0x1f) << 7; |
| 4462 | // op: vm |
| 4463 | op = getVMaskReg(MI, OpNo: 2, Fixups, STI); |
| 4464 | Value |= (op & 0x1) << 25; |
| 4465 | // op: vs2 |
| 4466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4467 | Value |= (op & 0x1f) << 20; |
| 4468 | break; |
| 4469 | } |
| 4470 | case RISCV::VFMV_F_S: |
| 4471 | case RISCV::VMV_X_S: { |
| 4472 | // op: rd |
| 4473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4474 | Value |= (op & 0x1f) << 7; |
| 4475 | // op: vs2 |
| 4476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4477 | Value |= (op & 0x1f) << 20; |
| 4478 | break; |
| 4479 | } |
| 4480 | case RISCV::QK_C_LBU: { |
| 4481 | // op: rd |
| 4482 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4483 | Value |= (op & 0x7) << 2; |
| 4484 | // op: rs1 |
| 4485 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4486 | Value |= (op & 0x7) << 7; |
| 4487 | // op: imm |
| 4488 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4489 | Value |= (op & 0x1) << 12; |
| 4490 | Value |= (op & 0x18) << 7; |
| 4491 | Value |= (op & 0x6) << 4; |
| 4492 | break; |
| 4493 | } |
| 4494 | case RISCV::C_LBU: { |
| 4495 | // op: rd |
| 4496 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4497 | Value |= (op & 0x7) << 2; |
| 4498 | // op: rs1 |
| 4499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4500 | Value |= (op & 0x7) << 7; |
| 4501 | // op: imm |
| 4502 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4503 | Value |= (op & 0x1) << 6; |
| 4504 | Value |= (op & 0x2) << 4; |
| 4505 | break; |
| 4506 | } |
| 4507 | case RISCV::C_LH: |
| 4508 | case RISCV::C_LHU: |
| 4509 | case RISCV::C_LH_INX: { |
| 4510 | // op: rd |
| 4511 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4512 | Value |= (op & 0x7) << 2; |
| 4513 | // op: rs1 |
| 4514 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4515 | Value |= (op & 0x7) << 7; |
| 4516 | // op: imm |
| 4517 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4518 | Value |= (op & 0x2) << 4; |
| 4519 | break; |
| 4520 | } |
| 4521 | case RISCV::C_FLW: |
| 4522 | case RISCV::C_LW: |
| 4523 | case RISCV::C_LW_INX: { |
| 4524 | // op: rd |
| 4525 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4526 | Value |= (op & 0x7) << 2; |
| 4527 | // op: rs1 |
| 4528 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4529 | Value |= (op & 0x7) << 7; |
| 4530 | // op: imm |
| 4531 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4532 | Value |= (op & 0x38) << 7; |
| 4533 | Value |= (op & 0x4) << 4; |
| 4534 | Value |= (op & 0x40) >> 1; |
| 4535 | break; |
| 4536 | } |
| 4537 | case RISCV::QK_C_LHU: { |
| 4538 | // op: rd |
| 4539 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4540 | Value |= (op & 0x7) << 2; |
| 4541 | // op: rs1 |
| 4542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4543 | Value |= (op & 0x7) << 7; |
| 4544 | // op: imm |
| 4545 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4546 | Value |= (op & 0x38) << 7; |
| 4547 | Value |= (op & 0x6) << 4; |
| 4548 | break; |
| 4549 | } |
| 4550 | case RISCV::C_FLD: |
| 4551 | case RISCV::C_LD: |
| 4552 | case RISCV::C_LD_RV32: { |
| 4553 | // op: rd |
| 4554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4555 | Value |= (op & 0x7) << 2; |
| 4556 | // op: rs1 |
| 4557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4558 | Value |= (op & 0x7) << 7; |
| 4559 | // op: imm |
| 4560 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4561 | Value |= (op & 0x38) << 7; |
| 4562 | Value |= (op & 0xc0) >> 1; |
| 4563 | break; |
| 4564 | } |
| 4565 | case RISCV::SF_VTZERO_T: { |
| 4566 | // op: rd |
| 4567 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4568 | Value |= (op & 0xf) << 8; |
| 4569 | break; |
| 4570 | } |
| 4571 | case RISCV::QC_E_ADDAI: |
| 4572 | case RISCV::QC_E_ANDAI: |
| 4573 | case RISCV::QC_E_ORAI: |
| 4574 | case RISCV::QC_E_XORAI: { |
| 4575 | // op: rd |
| 4576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4577 | Value |= (op & 0x1f) << 7; |
| 4578 | // op: imm |
| 4579 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4580 | Value |= (op & 0xffffffff) << 16; |
| 4581 | break; |
| 4582 | } |
| 4583 | case RISCV::QC_INSBI: { |
| 4584 | // op: rd |
| 4585 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4586 | Value |= (op & 0x1f) << 7; |
| 4587 | // op: imm5 |
| 4588 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4589 | Value |= (op & 0x1f) << 15; |
| 4590 | // op: shamt |
| 4591 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 4592 | Value |= (op & 0x1f) << 20; |
| 4593 | // op: width |
| 4594 | op = getImmOpValueMinus1(MI, OpNo: 3, Fixups, STI); |
| 4595 | Value |= (op & 0x1f) << 25; |
| 4596 | break; |
| 4597 | } |
| 4598 | case RISCV::QC_C_EXTU: { |
| 4599 | // op: rd |
| 4600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4601 | Value |= (op & 0x1f) << 7; |
| 4602 | // op: width |
| 4603 | op = getImmOpValueMinus1(MI, OpNo: 2, Fixups, STI); |
| 4604 | Value |= (op & 0x1f) << 2; |
| 4605 | break; |
| 4606 | } |
| 4607 | case RISCV::QC_C_MVEQZ: { |
| 4608 | // op: rd |
| 4609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4610 | Value |= (op & 0x7) << 2; |
| 4611 | // op: rs1 |
| 4612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4613 | Value |= (op & 0x7) << 7; |
| 4614 | break; |
| 4615 | } |
| 4616 | case RISCV::QC_C_MULIADD: { |
| 4617 | // op: rd |
| 4618 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4619 | Value |= (op & 0x7) << 2; |
| 4620 | // op: rs1 |
| 4621 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4622 | Value |= (op & 0x7) << 7; |
| 4623 | // op: uimm |
| 4624 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 4625 | Value |= (op & 0xe) << 9; |
| 4626 | Value |= (op & 0x1) << 6; |
| 4627 | Value |= (op & 0x10) << 1; |
| 4628 | break; |
| 4629 | } |
| 4630 | case RISCV::C_NOT: |
| 4631 | case RISCV::C_SEXT_B: |
| 4632 | case RISCV::C_SEXT_H: |
| 4633 | case RISCV::C_ZEXT_B: |
| 4634 | case RISCV::C_ZEXT_H: |
| 4635 | case RISCV::C_ZEXT_W: { |
| 4636 | // op: rd |
| 4637 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4638 | Value |= (op & 0x7) << 7; |
| 4639 | break; |
| 4640 | } |
| 4641 | case RISCV::QK_C_LHUSP: |
| 4642 | case RISCV::QK_C_SHSP: { |
| 4643 | // op: rd_rs2 |
| 4644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4645 | Value |= (op & 0x7) << 2; |
| 4646 | // op: imm |
| 4647 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4648 | Value |= (op & 0xe) << 7; |
| 4649 | Value |= (op & 0x10) << 3; |
| 4650 | break; |
| 4651 | } |
| 4652 | case RISCV::QK_C_LBUSP: |
| 4653 | case RISCV::QK_C_SBSP: { |
| 4654 | // op: rd_rs2 |
| 4655 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4656 | Value |= (op & 0x7) << 2; |
| 4657 | // op: imm |
| 4658 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4659 | Value |= (op & 0xf) << 7; |
| 4660 | break; |
| 4661 | } |
| 4662 | case RISCV::CM_POP: |
| 4663 | case RISCV::CM_POPRET: |
| 4664 | case RISCV::CM_POPRETZ: |
| 4665 | case RISCV::CM_PUSH: |
| 4666 | case RISCV::QC_CM_POP: |
| 4667 | case RISCV::QC_CM_POPRET: |
| 4668 | case RISCV::QC_CM_POPRETZ: |
| 4669 | case RISCV::QC_CM_PUSH: { |
| 4670 | // op: rlist |
| 4671 | op = getRlistOpValue(MI, OpNo: 0, Fixups, STI); |
| 4672 | Value |= (op & 0xf) << 4; |
| 4673 | // op: stackadj |
| 4674 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4675 | Value |= (op & 0x30) >> 2; |
| 4676 | break; |
| 4677 | } |
| 4678 | case RISCV::QC_CM_PUSHFP: { |
| 4679 | // op: rlist |
| 4680 | op = getRlistS0OpValue(MI, OpNo: 0, Fixups, STI); |
| 4681 | Value |= (op & 0xf) << 4; |
| 4682 | // op: stackadj |
| 4683 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4684 | Value |= (op & 0x30) >> 2; |
| 4685 | break; |
| 4686 | } |
| 4687 | case RISCV::CSRRCI: |
| 4688 | case RISCV::CSRRSI: |
| 4689 | case RISCV::CSRRWI: { |
| 4690 | // op: rs1 |
| 4691 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4692 | Value |= (op & 0x1f) << 15; |
| 4693 | // op: rd |
| 4694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4695 | Value |= (op & 0x1f) << 7; |
| 4696 | // op: imm12 |
| 4697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4698 | Value |= (op & 0xfff) << 20; |
| 4699 | break; |
| 4700 | } |
| 4701 | case RISCV::AIF_MOVA_M_X: |
| 4702 | case RISCV::CBO_CLEAN: |
| 4703 | case RISCV::CBO_FLUSH: |
| 4704 | case RISCV::CBO_INVAL: |
| 4705 | case RISCV::CBO_ZERO: |
| 4706 | case RISCV::SF_CDISCARD_D_L1: |
| 4707 | case RISCV::SF_CFLUSH_D_L1: |
| 4708 | case RISCV::SSPOPCHK: |
| 4709 | case RISCV::TH_DCACHE_CIPA: |
| 4710 | case RISCV::TH_DCACHE_CISW: |
| 4711 | case RISCV::TH_DCACHE_CIVA: |
| 4712 | case RISCV::TH_DCACHE_CPA: |
| 4713 | case RISCV::TH_DCACHE_CPAL1: |
| 4714 | case RISCV::TH_DCACHE_CSW: |
| 4715 | case RISCV::TH_DCACHE_CVA: |
| 4716 | case RISCV::TH_DCACHE_CVAL1: |
| 4717 | case RISCV::TH_DCACHE_IPA: |
| 4718 | case RISCV::TH_DCACHE_ISW: |
| 4719 | case RISCV::TH_DCACHE_IVA: |
| 4720 | case RISCV::TH_ICACHE_IPA: |
| 4721 | case RISCV::TH_ICACHE_IVA: { |
| 4722 | // op: rs1 |
| 4723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4724 | Value |= (op & 0x1f) << 15; |
| 4725 | break; |
| 4726 | } |
| 4727 | case RISCV::QC_E_BEQI: |
| 4728 | case RISCV::QC_E_BGEI: |
| 4729 | case RISCV::QC_E_BGEUI: |
| 4730 | case RISCV::QC_E_BLTI: |
| 4731 | case RISCV::QC_E_BLTUI: |
| 4732 | case RISCV::QC_E_BNEI: { |
| 4733 | // op: rs1 |
| 4734 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4735 | Value |= (op & 0x1f) << 15; |
| 4736 | // op: imm16 |
| 4737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4738 | Value |= (op & 0xffff) << 32; |
| 4739 | // op: imm12 |
| 4740 | op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI); |
| 4741 | Value |= (op & 0x800) << 20; |
| 4742 | Value |= (op & 0x3f0) << 21; |
| 4743 | Value |= (op & 0xf) << 8; |
| 4744 | Value |= (op & 0x400) >> 3; |
| 4745 | break; |
| 4746 | } |
| 4747 | case RISCV::C_JALR: |
| 4748 | case RISCV::C_JR: |
| 4749 | case RISCV::QC_C_CLRINT: |
| 4750 | case RISCV::QC_C_EIR: |
| 4751 | case RISCV::QC_C_SETINT: { |
| 4752 | // op: rs1 |
| 4753 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4754 | Value |= (op & 0x1f) << 7; |
| 4755 | break; |
| 4756 | } |
| 4757 | case RISCV::C_MV: { |
| 4758 | // op: rs1 |
| 4759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4760 | Value |= (op & 0x1f) << 7; |
| 4761 | // op: rs2 |
| 4762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4763 | Value |= (op & 0x1f) << 2; |
| 4764 | break; |
| 4765 | } |
| 4766 | case RISCV::PSABS_DB: |
| 4767 | case RISCV::PSABS_DH: |
| 4768 | case RISCV::PSEXT_DH_B: |
| 4769 | case RISCV::PSEXT_DW_B: |
| 4770 | case RISCV::PSEXT_DW_H: { |
| 4771 | // op: rs1 |
| 4772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4773 | Value |= (op & 0x1e) << 15; |
| 4774 | // op: rd |
| 4775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4776 | Value |= (op & 0x1e) << 7; |
| 4777 | break; |
| 4778 | } |
| 4779 | case RISCV::ADDD: |
| 4780 | case RISCV::PAADDU_DB: |
| 4781 | case RISCV::PAADDU_DH: |
| 4782 | case RISCV::PAADDU_DW: |
| 4783 | case RISCV::PAADD_DB: |
| 4784 | case RISCV::PAADD_DH: |
| 4785 | case RISCV::PAADD_DW: |
| 4786 | case RISCV::PAAS_DHX: |
| 4787 | case RISCV::PABDU_DB: |
| 4788 | case RISCV::PABDU_DH: |
| 4789 | case RISCV::PABD_DB: |
| 4790 | case RISCV::PABD_DH: |
| 4791 | case RISCV::PADD_DB: |
| 4792 | case RISCV::PADD_DH: |
| 4793 | case RISCV::PADD_DW: |
| 4794 | case RISCV::PASA_DHX: |
| 4795 | case RISCV::PASUBU_DB: |
| 4796 | case RISCV::PASUBU_DH: |
| 4797 | case RISCV::PASUBU_DW: |
| 4798 | case RISCV::PASUB_DB: |
| 4799 | case RISCV::PASUB_DH: |
| 4800 | case RISCV::PASUB_DW: |
| 4801 | case RISCV::PAS_DHX: |
| 4802 | case RISCV::PMAXU_DB: |
| 4803 | case RISCV::PMAXU_DH: |
| 4804 | case RISCV::PMAXU_DW: |
| 4805 | case RISCV::PMAX_DB: |
| 4806 | case RISCV::PMAX_DH: |
| 4807 | case RISCV::PMAX_DW: |
| 4808 | case RISCV::PMINU_DB: |
| 4809 | case RISCV::PMINU_DH: |
| 4810 | case RISCV::PMINU_DW: |
| 4811 | case RISCV::PMIN_DB: |
| 4812 | case RISCV::PMIN_DH: |
| 4813 | case RISCV::PMIN_DW: |
| 4814 | case RISCV::PMSEQ_DB: |
| 4815 | case RISCV::PMSEQ_DH: |
| 4816 | case RISCV::PMSEQ_DW: |
| 4817 | case RISCV::PMSLTU_DB: |
| 4818 | case RISCV::PMSLTU_DH: |
| 4819 | case RISCV::PMSLTU_DW: |
| 4820 | case RISCV::PMSLT_DB: |
| 4821 | case RISCV::PMSLT_DH: |
| 4822 | case RISCV::PMSLT_DW: |
| 4823 | case RISCV::PPAIREO_DB: |
| 4824 | case RISCV::PPAIREO_DH: |
| 4825 | case RISCV::PPAIRE_DB: |
| 4826 | case RISCV::PPAIRE_DH: |
| 4827 | case RISCV::PPAIROE_DB: |
| 4828 | case RISCV::PPAIROE_DH: |
| 4829 | case RISCV::PPAIRO_DB: |
| 4830 | case RISCV::PPAIRO_DH: |
| 4831 | case RISCV::PSADDU_DB: |
| 4832 | case RISCV::PSADDU_DH: |
| 4833 | case RISCV::PSADDU_DW: |
| 4834 | case RISCV::PSADD_DB: |
| 4835 | case RISCV::PSADD_DH: |
| 4836 | case RISCV::PSADD_DW: |
| 4837 | case RISCV::PSAS_DHX: |
| 4838 | case RISCV::PSA_DHX: |
| 4839 | case RISCV::PSH1ADD_DH: |
| 4840 | case RISCV::PSH1ADD_DW: |
| 4841 | case RISCV::PSSA_DHX: |
| 4842 | case RISCV::PSSH1SADD_DH: |
| 4843 | case RISCV::PSSH1SADD_DW: |
| 4844 | case RISCV::PSSUBU_DB: |
| 4845 | case RISCV::PSSUBU_DH: |
| 4846 | case RISCV::PSSUBU_DW: |
| 4847 | case RISCV::PSSUB_DB: |
| 4848 | case RISCV::PSSUB_DH: |
| 4849 | case RISCV::PSSUB_DW: |
| 4850 | case RISCV::PSUB_DB: |
| 4851 | case RISCV::PSUB_DH: |
| 4852 | case RISCV::PSUB_DW: |
| 4853 | case RISCV::SUBD: { |
| 4854 | // op: rs1 |
| 4855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4856 | Value |= (op & 0x1e) << 15; |
| 4857 | // op: rd |
| 4858 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4859 | Value |= (op & 0x1e) << 7; |
| 4860 | // op: rs2 |
| 4861 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4862 | Value |= (op & 0x1e) << 20; |
| 4863 | break; |
| 4864 | } |
| 4865 | case RISCV::PADD_DBS: |
| 4866 | case RISCV::PADD_DHS: |
| 4867 | case RISCV::PADD_DWS: |
| 4868 | case RISCV::PSLL_DBS: |
| 4869 | case RISCV::PSLL_DHS: |
| 4870 | case RISCV::PSLL_DWS: |
| 4871 | case RISCV::PSRA_DBS: |
| 4872 | case RISCV::PSRA_DHS: |
| 4873 | case RISCV::PSRA_DWS: |
| 4874 | case RISCV::PSRL_DBS: |
| 4875 | case RISCV::PSRL_DHS: |
| 4876 | case RISCV::PSRL_DWS: |
| 4877 | case RISCV::PSSHAR_DHS: |
| 4878 | case RISCV::PSSHAR_DWS: |
| 4879 | case RISCV::PSSHA_DHS: |
| 4880 | case RISCV::PSSHA_DWS: { |
| 4881 | // op: rs1 |
| 4882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4883 | Value |= (op & 0x1e) << 15; |
| 4884 | // op: rd |
| 4885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4886 | Value |= (op & 0x1e) << 7; |
| 4887 | // op: rs2 |
| 4888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4889 | Value |= (op & 0x1f) << 20; |
| 4890 | break; |
| 4891 | } |
| 4892 | case RISCV::PSATI_DW: |
| 4893 | case RISCV::PSLLI_DW: |
| 4894 | case RISCV::PSRAI_DW: |
| 4895 | case RISCV::PSRARI_DW: |
| 4896 | case RISCV::PSRLI_DW: |
| 4897 | case RISCV::PSSLAI_DW: |
| 4898 | case RISCV::PUSATI_DW: { |
| 4899 | // op: rs1 |
| 4900 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4901 | Value |= (op & 0x1e) << 15; |
| 4902 | // op: rd |
| 4903 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4904 | Value |= (op & 0x1e) << 7; |
| 4905 | // op: shamt |
| 4906 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4907 | Value |= (op & 0x1f) << 20; |
| 4908 | break; |
| 4909 | } |
| 4910 | case RISCV::PSLLI_DB: |
| 4911 | case RISCV::PSRAI_DB: |
| 4912 | case RISCV::PSRLI_DB: { |
| 4913 | // op: rs1 |
| 4914 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4915 | Value |= (op & 0x1e) << 15; |
| 4916 | // op: rd |
| 4917 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4918 | Value |= (op & 0x1e) << 7; |
| 4919 | // op: shamt |
| 4920 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4921 | Value |= (op & 0x7) << 20; |
| 4922 | break; |
| 4923 | } |
| 4924 | case RISCV::PSATI_DH: |
| 4925 | case RISCV::PSLLI_DH: |
| 4926 | case RISCV::PSRAI_DH: |
| 4927 | case RISCV::PSRARI_DH: |
| 4928 | case RISCV::PSRLI_DH: |
| 4929 | case RISCV::PSSLAI_DH: |
| 4930 | case RISCV::PUSATI_DH: { |
| 4931 | // op: rs1 |
| 4932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4933 | Value |= (op & 0x1e) << 15; |
| 4934 | // op: rd |
| 4935 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4936 | Value |= (op & 0x1e) << 7; |
| 4937 | // op: shamt |
| 4938 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4939 | Value |= (op & 0xf) << 20; |
| 4940 | break; |
| 4941 | } |
| 4942 | case RISCV::NCLIP: |
| 4943 | case RISCV::NCLIPR: |
| 4944 | case RISCV::NCLIPRU: |
| 4945 | case RISCV::NCLIPU: |
| 4946 | case RISCV::NSRA: |
| 4947 | case RISCV::NSRAR: |
| 4948 | case RISCV::NSRL: |
| 4949 | case RISCV::PNCLIPRU_BS: |
| 4950 | case RISCV::PNCLIPRU_HS: |
| 4951 | case RISCV::PNCLIPR_BS: |
| 4952 | case RISCV::PNCLIPR_HS: |
| 4953 | case RISCV::PNCLIPU_BS: |
| 4954 | case RISCV::PNCLIPU_HS: |
| 4955 | case RISCV::PNCLIP_BS: |
| 4956 | case RISCV::PNCLIP_HS: |
| 4957 | case RISCV::PNSRAR_BS: |
| 4958 | case RISCV::PNSRAR_HS: |
| 4959 | case RISCV::PNSRA_BS: |
| 4960 | case RISCV::PNSRA_HS: |
| 4961 | case RISCV::PNSRL_BS: |
| 4962 | case RISCV::PNSRL_HS: |
| 4963 | case RISCV::PREDSUMU_DBS: |
| 4964 | case RISCV::PREDSUMU_DHS: |
| 4965 | case RISCV::PREDSUM_DBS: |
| 4966 | case RISCV::PREDSUM_DHS: { |
| 4967 | // op: rs1 |
| 4968 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4969 | Value |= (op & 0x1e) << 15; |
| 4970 | // op: rd |
| 4971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4972 | Value |= (op & 0x1f) << 7; |
| 4973 | // op: rs2 |
| 4974 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4975 | Value |= (op & 0x1f) << 20; |
| 4976 | break; |
| 4977 | } |
| 4978 | case RISCV::PNCLIPIU_H: |
| 4979 | case RISCV::PNCLIPI_H: |
| 4980 | case RISCV::PNCLIPRIU_H: |
| 4981 | case RISCV::PNCLIPRI_H: |
| 4982 | case RISCV::PNSRAI_H: |
| 4983 | case RISCV::PNSRARI_H: |
| 4984 | case RISCV::PNSRLI_H: { |
| 4985 | // op: rs1 |
| 4986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4987 | Value |= (op & 0x1e) << 15; |
| 4988 | // op: rd |
| 4989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4990 | Value |= (op & 0x1f) << 7; |
| 4991 | // op: shamt |
| 4992 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 4993 | Value |= (op & 0x1f) << 20; |
| 4994 | break; |
| 4995 | } |
| 4996 | case RISCV::NCLIPI: |
| 4997 | case RISCV::NCLIPIU: |
| 4998 | case RISCV::NCLIPRI: |
| 4999 | case RISCV::NCLIPRIU: |
| 5000 | case RISCV::NSRAI: |
| 5001 | case RISCV::NSRARI: |
| 5002 | case RISCV::NSRLI: { |
| 5003 | // op: rs1 |
| 5004 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5005 | Value |= (op & 0x1e) << 15; |
| 5006 | // op: rd |
| 5007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5008 | Value |= (op & 0x1f) << 7; |
| 5009 | // op: shamt |
| 5010 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5011 | Value |= (op & 0x3f) << 20; |
| 5012 | break; |
| 5013 | } |
| 5014 | case RISCV::PNCLIPIU_B: |
| 5015 | case RISCV::PNCLIPI_B: |
| 5016 | case RISCV::PNCLIPRIU_B: |
| 5017 | case RISCV::PNCLIPRI_B: |
| 5018 | case RISCV::PNSRAI_B: |
| 5019 | case RISCV::PNSRARI_B: |
| 5020 | case RISCV::PNSRLI_B: { |
| 5021 | // op: rs1 |
| 5022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5023 | Value |= (op & 0x1e) << 15; |
| 5024 | // op: rd |
| 5025 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5026 | Value |= (op & 0x1f) << 7; |
| 5027 | // op: shamt |
| 5028 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5029 | Value |= (op & 0xf) << 20; |
| 5030 | break; |
| 5031 | } |
| 5032 | case RISCV::FCVT_BF16_S: |
| 5033 | case RISCV::FCVT_D_H: |
| 5034 | case RISCV::FCVT_D_H_IN32X: |
| 5035 | case RISCV::FCVT_D_H_INX: |
| 5036 | case RISCV::FCVT_D_L: |
| 5037 | case RISCV::FCVT_D_LU: |
| 5038 | case RISCV::FCVT_D_LU_INX: |
| 5039 | case RISCV::FCVT_D_L_INX: |
| 5040 | case RISCV::FCVT_D_Q: |
| 5041 | case RISCV::FCVT_D_S: |
| 5042 | case RISCV::FCVT_D_S_IN32X: |
| 5043 | case RISCV::FCVT_D_S_INX: |
| 5044 | case RISCV::FCVT_D_W: |
| 5045 | case RISCV::FCVT_D_WU: |
| 5046 | case RISCV::FCVT_D_WU_IN32X: |
| 5047 | case RISCV::FCVT_D_WU_INX: |
| 5048 | case RISCV::FCVT_D_W_IN32X: |
| 5049 | case RISCV::FCVT_D_W_INX: |
| 5050 | case RISCV::FCVT_H_D: |
| 5051 | case RISCV::FCVT_H_D_IN32X: |
| 5052 | case RISCV::FCVT_H_D_INX: |
| 5053 | case RISCV::FCVT_H_L: |
| 5054 | case RISCV::FCVT_H_LU: |
| 5055 | case RISCV::FCVT_H_LU_INX: |
| 5056 | case RISCV::FCVT_H_L_INX: |
| 5057 | case RISCV::FCVT_H_S: |
| 5058 | case RISCV::FCVT_H_S_INX: |
| 5059 | case RISCV::FCVT_H_W: |
| 5060 | case RISCV::FCVT_H_WU: |
| 5061 | case RISCV::FCVT_H_WU_INX: |
| 5062 | case RISCV::FCVT_H_W_INX: |
| 5063 | case RISCV::FCVT_LU_D: |
| 5064 | case RISCV::FCVT_LU_D_INX: |
| 5065 | case RISCV::FCVT_LU_H: |
| 5066 | case RISCV::FCVT_LU_H_INX: |
| 5067 | case RISCV::FCVT_LU_Q: |
| 5068 | case RISCV::FCVT_LU_S: |
| 5069 | case RISCV::FCVT_LU_S_INX: |
| 5070 | case RISCV::FCVT_L_D: |
| 5071 | case RISCV::FCVT_L_D_INX: |
| 5072 | case RISCV::FCVT_L_H: |
| 5073 | case RISCV::FCVT_L_H_INX: |
| 5074 | case RISCV::FCVT_L_Q: |
| 5075 | case RISCV::FCVT_L_S: |
| 5076 | case RISCV::FCVT_L_S_INX: |
| 5077 | case RISCV::FCVT_Q_D: |
| 5078 | case RISCV::FCVT_Q_L: |
| 5079 | case RISCV::FCVT_Q_LU: |
| 5080 | case RISCV::FCVT_Q_S: |
| 5081 | case RISCV::FCVT_Q_W: |
| 5082 | case RISCV::FCVT_Q_WU: |
| 5083 | case RISCV::FCVT_S_BF16: |
| 5084 | case RISCV::FCVT_S_D: |
| 5085 | case RISCV::FCVT_S_D_IN32X: |
| 5086 | case RISCV::FCVT_S_D_INX: |
| 5087 | case RISCV::FCVT_S_H: |
| 5088 | case RISCV::FCVT_S_H_INX: |
| 5089 | case RISCV::FCVT_S_L: |
| 5090 | case RISCV::FCVT_S_LU: |
| 5091 | case RISCV::FCVT_S_LU_INX: |
| 5092 | case RISCV::FCVT_S_L_INX: |
| 5093 | case RISCV::FCVT_S_Q: |
| 5094 | case RISCV::FCVT_S_W: |
| 5095 | case RISCV::FCVT_S_WU: |
| 5096 | case RISCV::FCVT_S_WU_INX: |
| 5097 | case RISCV::FCVT_S_W_INX: |
| 5098 | case RISCV::FCVT_WU_D: |
| 5099 | case RISCV::FCVT_WU_D_IN32X: |
| 5100 | case RISCV::FCVT_WU_D_INX: |
| 5101 | case RISCV::FCVT_WU_H: |
| 5102 | case RISCV::FCVT_WU_H_INX: |
| 5103 | case RISCV::FCVT_WU_Q: |
| 5104 | case RISCV::FCVT_WU_S: |
| 5105 | case RISCV::FCVT_WU_S_INX: |
| 5106 | case RISCV::FCVT_W_D: |
| 5107 | case RISCV::FCVT_W_D_IN32X: |
| 5108 | case RISCV::FCVT_W_D_INX: |
| 5109 | case RISCV::FCVT_W_H: |
| 5110 | case RISCV::FCVT_W_H_INX: |
| 5111 | case RISCV::FCVT_W_Q: |
| 5112 | case RISCV::FCVT_W_S: |
| 5113 | case RISCV::FCVT_W_S_INX: |
| 5114 | case RISCV::FROUNDNX_D: |
| 5115 | case RISCV::FROUNDNX_H: |
| 5116 | case RISCV::FROUNDNX_Q: |
| 5117 | case RISCV::FROUNDNX_S: |
| 5118 | case RISCV::FROUND_D: |
| 5119 | case RISCV::FROUND_H: |
| 5120 | case RISCV::FROUND_Q: |
| 5121 | case RISCV::FROUND_S: |
| 5122 | case RISCV::FSQRT_D: |
| 5123 | case RISCV::FSQRT_D_IN32X: |
| 5124 | case RISCV::FSQRT_D_INX: |
| 5125 | case RISCV::FSQRT_H: |
| 5126 | case RISCV::FSQRT_H_INX: |
| 5127 | case RISCV::FSQRT_Q: |
| 5128 | case RISCV::FSQRT_S: |
| 5129 | case RISCV::FSQRT_S_INX: { |
| 5130 | // op: rs1 |
| 5131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5132 | Value |= (op & 0x1f) << 15; |
| 5133 | // op: frm |
| 5134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5135 | Value |= (op & 0x7) << 12; |
| 5136 | // op: rd |
| 5137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5138 | Value |= (op & 0x1f) << 7; |
| 5139 | break; |
| 5140 | } |
| 5141 | case RISCV::PWSLAI_H: |
| 5142 | case RISCV::PWSLLI_H: { |
| 5143 | // op: rs1 |
| 5144 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5145 | Value |= (op & 0x1f) << 15; |
| 5146 | // op: rd |
| 5147 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5148 | Value |= (op & 0x1e) << 7; |
| 5149 | // op: shamt |
| 5150 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5151 | Value |= (op & 0x1f) << 20; |
| 5152 | break; |
| 5153 | } |
| 5154 | case RISCV::WSLAI: |
| 5155 | case RISCV::WSLLI: { |
| 5156 | // op: rs1 |
| 5157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5158 | Value |= (op & 0x1f) << 15; |
| 5159 | // op: rd |
| 5160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5161 | Value |= (op & 0x1e) << 7; |
| 5162 | // op: shamt |
| 5163 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5164 | Value |= (op & 0x3f) << 20; |
| 5165 | break; |
| 5166 | } |
| 5167 | case RISCV::PWSLAI_B: |
| 5168 | case RISCV::PWSLLI_B: { |
| 5169 | // op: rs1 |
| 5170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5171 | Value |= (op & 0x1f) << 15; |
| 5172 | // op: rd |
| 5173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5174 | Value |= (op & 0x1e) << 7; |
| 5175 | // op: shamt |
| 5176 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5177 | Value |= (op & 0xf) << 20; |
| 5178 | break; |
| 5179 | } |
| 5180 | case RISCV::ABS: |
| 5181 | case RISCV::ABSW: |
| 5182 | case RISCV::AES64IM: |
| 5183 | case RISCV::AIF_FBCX_PS: |
| 5184 | case RISCV::AIF_FCLASS_PS: |
| 5185 | case RISCV::AIF_FCVT_F10_PS: |
| 5186 | case RISCV::AIF_FCVT_F11_PS: |
| 5187 | case RISCV::AIF_FCVT_F16_PS: |
| 5188 | case RISCV::AIF_FCVT_PS_F10: |
| 5189 | case RISCV::AIF_FCVT_PS_F11: |
| 5190 | case RISCV::AIF_FCVT_PS_F16: |
| 5191 | case RISCV::AIF_FCVT_PS_RAST: |
| 5192 | case RISCV::AIF_FCVT_PS_SN16: |
| 5193 | case RISCV::AIF_FCVT_PS_SN8: |
| 5194 | case RISCV::AIF_FCVT_PS_UN10: |
| 5195 | case RISCV::AIF_FCVT_PS_UN16: |
| 5196 | case RISCV::AIF_FCVT_PS_UN2: |
| 5197 | case RISCV::AIF_FCVT_PS_UN24: |
| 5198 | case RISCV::AIF_FCVT_PS_UN8: |
| 5199 | case RISCV::AIF_FCVT_RAST_PS: |
| 5200 | case RISCV::AIF_FCVT_SN16_PS: |
| 5201 | case RISCV::AIF_FCVT_SN8_PS: |
| 5202 | case RISCV::AIF_FCVT_UN10_PS: |
| 5203 | case RISCV::AIF_FCVT_UN16_PS: |
| 5204 | case RISCV::AIF_FCVT_UN24_PS: |
| 5205 | case RISCV::AIF_FCVT_UN2_PS: |
| 5206 | case RISCV::AIF_FCVT_UN8_PS: |
| 5207 | case RISCV::AIF_FEXP_PS: |
| 5208 | case RISCV::AIF_FFRC_PS: |
| 5209 | case RISCV::AIF_FLOG_PS: |
| 5210 | case RISCV::AIF_FLWG_PS: |
| 5211 | case RISCV::AIF_FLWL_PS: |
| 5212 | case RISCV::AIF_FNOT_PI: |
| 5213 | case RISCV::AIF_FPACKREPB_PI: |
| 5214 | case RISCV::AIF_FPACKREPH_PI: |
| 5215 | case RISCV::AIF_FRCP_PS: |
| 5216 | case RISCV::AIF_FRSQ_PS: |
| 5217 | case RISCV::AIF_FSAT8_PI: |
| 5218 | case RISCV::AIF_FSATU8_PI: |
| 5219 | case RISCV::AIF_FSETM_PI: |
| 5220 | case RISCV::AIF_FSIN_PS: |
| 5221 | case RISCV::AIF_FSQRT_PS: |
| 5222 | case RISCV::BREV8: |
| 5223 | case RISCV::CLS: |
| 5224 | case RISCV::CLSW: |
| 5225 | case RISCV::CLZ: |
| 5226 | case RISCV::CLZW: |
| 5227 | case RISCV::CPOP: |
| 5228 | case RISCV::CPOPW: |
| 5229 | case RISCV::CTZ: |
| 5230 | case RISCV::CTZW: |
| 5231 | case RISCV::CV_ABS: |
| 5232 | case RISCV::CV_ABS_B: |
| 5233 | case RISCV::CV_ABS_H: |
| 5234 | case RISCV::CV_CLB: |
| 5235 | case RISCV::CV_CNT: |
| 5236 | case RISCV::CV_CPLXCONJ: |
| 5237 | case RISCV::CV_EXTBS: |
| 5238 | case RISCV::CV_EXTBZ: |
| 5239 | case RISCV::CV_EXTHS: |
| 5240 | case RISCV::CV_EXTHZ: |
| 5241 | case RISCV::CV_FF1: |
| 5242 | case RISCV::CV_FL1: |
| 5243 | case RISCV::FCLASS_D: |
| 5244 | case RISCV::FCLASS_D_IN32X: |
| 5245 | case RISCV::FCLASS_D_INX: |
| 5246 | case RISCV::FCLASS_H: |
| 5247 | case RISCV::FCLASS_H_INX: |
| 5248 | case RISCV::FCLASS_Q: |
| 5249 | case RISCV::FCLASS_S: |
| 5250 | case RISCV::FCLASS_S_INX: |
| 5251 | case RISCV::FCVTMOD_W_D: |
| 5252 | case RISCV::FMVH_X_D: |
| 5253 | case RISCV::FMVH_X_Q: |
| 5254 | case RISCV::FMV_D_X: |
| 5255 | case RISCV::FMV_H_X: |
| 5256 | case RISCV::FMV_W_X: |
| 5257 | case RISCV::FMV_X_D: |
| 5258 | case RISCV::FMV_X_H: |
| 5259 | case RISCV::FMV_X_W: |
| 5260 | case RISCV::FMV_X_W_FPR64: |
| 5261 | case RISCV::HLVX_HU: |
| 5262 | case RISCV::HLVX_WU: |
| 5263 | case RISCV::HLV_B: |
| 5264 | case RISCV::HLV_BU: |
| 5265 | case RISCV::HLV_D: |
| 5266 | case RISCV::HLV_H: |
| 5267 | case RISCV::HLV_HU: |
| 5268 | case RISCV::HLV_W: |
| 5269 | case RISCV::HLV_WU: |
| 5270 | case RISCV::LB_AQ: |
| 5271 | case RISCV::LB_AQRL: |
| 5272 | case RISCV::LD_AQ: |
| 5273 | case RISCV::LD_AQRL: |
| 5274 | case RISCV::LH_AQ: |
| 5275 | case RISCV::LH_AQRL: |
| 5276 | case RISCV::LR_D: |
| 5277 | case RISCV::LR_D_AQ: |
| 5278 | case RISCV::LR_D_AQRL: |
| 5279 | case RISCV::LR_D_RL: |
| 5280 | case RISCV::LR_W: |
| 5281 | case RISCV::LR_W_AQ: |
| 5282 | case RISCV::LR_W_AQRL: |
| 5283 | case RISCV::LR_W_RL: |
| 5284 | case RISCV::LW_AQ: |
| 5285 | case RISCV::LW_AQRL: |
| 5286 | case RISCV::MOP_R_0: |
| 5287 | case RISCV::MOP_R_1: |
| 5288 | case RISCV::MOP_R_10: |
| 5289 | case RISCV::MOP_R_11: |
| 5290 | case RISCV::MOP_R_12: |
| 5291 | case RISCV::MOP_R_13: |
| 5292 | case RISCV::MOP_R_14: |
| 5293 | case RISCV::MOP_R_15: |
| 5294 | case RISCV::MOP_R_16: |
| 5295 | case RISCV::MOP_R_17: |
| 5296 | case RISCV::MOP_R_18: |
| 5297 | case RISCV::MOP_R_19: |
| 5298 | case RISCV::MOP_R_2: |
| 5299 | case RISCV::MOP_R_20: |
| 5300 | case RISCV::MOP_R_21: |
| 5301 | case RISCV::MOP_R_22: |
| 5302 | case RISCV::MOP_R_23: |
| 5303 | case RISCV::MOP_R_24: |
| 5304 | case RISCV::MOP_R_25: |
| 5305 | case RISCV::MOP_R_26: |
| 5306 | case RISCV::MOP_R_27: |
| 5307 | case RISCV::MOP_R_28: |
| 5308 | case RISCV::MOP_R_29: |
| 5309 | case RISCV::MOP_R_3: |
| 5310 | case RISCV::MOP_R_30: |
| 5311 | case RISCV::MOP_R_31: |
| 5312 | case RISCV::MOP_R_4: |
| 5313 | case RISCV::MOP_R_5: |
| 5314 | case RISCV::MOP_R_6: |
| 5315 | case RISCV::MOP_R_7: |
| 5316 | case RISCV::MOP_R_8: |
| 5317 | case RISCV::MOP_R_9: |
| 5318 | case RISCV::NDS_FMV_BF16_X: |
| 5319 | case RISCV::NDS_FMV_X_BF16: |
| 5320 | case RISCV::ORC_B: |
| 5321 | case RISCV::PSABS_B: |
| 5322 | case RISCV::PSABS_H: |
| 5323 | case RISCV::PSEXT_H_B: |
| 5324 | case RISCV::PSEXT_W_B: |
| 5325 | case RISCV::PSEXT_W_H: |
| 5326 | case RISCV::QC_BREV32: |
| 5327 | case RISCV::QC_CLO: |
| 5328 | case RISCV::QC_COMPRESS2: |
| 5329 | case RISCV::QC_COMPRESS3: |
| 5330 | case RISCV::QC_CTO: |
| 5331 | case RISCV::QC_EXPAND2: |
| 5332 | case RISCV::QC_EXPAND3: |
| 5333 | case RISCV::QC_NORM: |
| 5334 | case RISCV::QC_NORMEU: |
| 5335 | case RISCV::QC_NORMU: |
| 5336 | case RISCV::REV16: |
| 5337 | case RISCV::REV8_RV32: |
| 5338 | case RISCV::REV8_RV64: |
| 5339 | case RISCV::REV_RV32: |
| 5340 | case RISCV::REV_RV64: |
| 5341 | case RISCV::SEXT_B: |
| 5342 | case RISCV::SEXT_H: |
| 5343 | case RISCV::SF_VSETTK: |
| 5344 | case RISCV::SF_VSETTM: |
| 5345 | case RISCV::SF_VSETTN: |
| 5346 | case RISCV::SHA256SIG0: |
| 5347 | case RISCV::SHA256SIG1: |
| 5348 | case RISCV::SHA256SUM0: |
| 5349 | case RISCV::SHA256SUM1: |
| 5350 | case RISCV::SHA512SIG0: |
| 5351 | case RISCV::SHA512SIG1: |
| 5352 | case RISCV::SHA512SUM0: |
| 5353 | case RISCV::SHA512SUM1: |
| 5354 | case RISCV::SM3P0: |
| 5355 | case RISCV::SM3P1: |
| 5356 | case RISCV::TH_FF0: |
| 5357 | case RISCV::TH_FF1: |
| 5358 | case RISCV::TH_REV: |
| 5359 | case RISCV::TH_REVW: |
| 5360 | case RISCV::TH_TSTNBZ: |
| 5361 | case RISCV::UNZIP_RV32: |
| 5362 | case RISCV::ZEXT_H_RV32: |
| 5363 | case RISCV::ZEXT_H_RV64: |
| 5364 | case RISCV::ZIP_RV32: { |
| 5365 | // op: rs1 |
| 5366 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5367 | Value |= (op & 0x1f) << 15; |
| 5368 | // op: rd |
| 5369 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5370 | Value |= (op & 0x1f) << 7; |
| 5371 | break; |
| 5372 | } |
| 5373 | case RISCV::QC_WRAPI: { |
| 5374 | // op: rs1 |
| 5375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5376 | Value |= (op & 0x1f) << 15; |
| 5377 | // op: rd |
| 5378 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5379 | Value |= (op & 0x1f) << 7; |
| 5380 | // op: imm11 |
| 5381 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5382 | Value |= (op & 0x7ff) << 20; |
| 5383 | break; |
| 5384 | } |
| 5385 | case RISCV::ADDI: |
| 5386 | case RISCV::ADDIW: |
| 5387 | case RISCV::ANDI: |
| 5388 | case RISCV::CV_ELW: |
| 5389 | case RISCV::FLD: |
| 5390 | case RISCV::FLH: |
| 5391 | case RISCV::FLQ: |
| 5392 | case RISCV::FLW: |
| 5393 | case RISCV::JALR: |
| 5394 | case RISCV::LB: |
| 5395 | case RISCV::LBU: |
| 5396 | case RISCV::LD: |
| 5397 | case RISCV::LD_RV32: |
| 5398 | case RISCV::LH: |
| 5399 | case RISCV::LHU: |
| 5400 | case RISCV::LH_INX: |
| 5401 | case RISCV::LW: |
| 5402 | case RISCV::LWU: |
| 5403 | case RISCV::LW_INX: |
| 5404 | case RISCV::ORI: |
| 5405 | case RISCV::SLTI: |
| 5406 | case RISCV::SLTIU: |
| 5407 | case RISCV::XORI: { |
| 5408 | // op: rs1 |
| 5409 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5410 | Value |= (op & 0x1f) << 15; |
| 5411 | // op: rd |
| 5412 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5413 | Value |= (op & 0x1f) << 7; |
| 5414 | // op: imm12 |
| 5415 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5416 | Value |= (op & 0xfff) << 20; |
| 5417 | break; |
| 5418 | } |
| 5419 | case RISCV::QC_INW: { |
| 5420 | // op: rs1 |
| 5421 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5422 | Value |= (op & 0x1f) << 15; |
| 5423 | // op: rd |
| 5424 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5425 | Value |= (op & 0x1f) << 7; |
| 5426 | // op: imm14 |
| 5427 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5428 | Value |= (op & 0x3ffc) << 18; |
| 5429 | break; |
| 5430 | } |
| 5431 | case RISCV::CV_CLIP: |
| 5432 | case RISCV::CV_CLIPU: { |
| 5433 | // op: rs1 |
| 5434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5435 | Value |= (op & 0x1f) << 15; |
| 5436 | // op: rd |
| 5437 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5438 | Value |= (op & 0x1f) << 7; |
| 5439 | // op: imm5 |
| 5440 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5441 | Value |= (op & 0x1f) << 20; |
| 5442 | break; |
| 5443 | } |
| 5444 | case RISCV::CV_ADD_SCI_B: |
| 5445 | case RISCV::CV_ADD_SCI_H: |
| 5446 | case RISCV::CV_AND_SCI_B: |
| 5447 | case RISCV::CV_AND_SCI_H: |
| 5448 | case RISCV::CV_AVGU_SCI_B: |
| 5449 | case RISCV::CV_AVGU_SCI_H: |
| 5450 | case RISCV::CV_AVG_SCI_B: |
| 5451 | case RISCV::CV_AVG_SCI_H: |
| 5452 | case RISCV::CV_CMPEQ_SCI_B: |
| 5453 | case RISCV::CV_CMPEQ_SCI_H: |
| 5454 | case RISCV::CV_CMPGEU_SCI_B: |
| 5455 | case RISCV::CV_CMPGEU_SCI_H: |
| 5456 | case RISCV::CV_CMPGE_SCI_B: |
| 5457 | case RISCV::CV_CMPGE_SCI_H: |
| 5458 | case RISCV::CV_CMPGTU_SCI_B: |
| 5459 | case RISCV::CV_CMPGTU_SCI_H: |
| 5460 | case RISCV::CV_CMPGT_SCI_B: |
| 5461 | case RISCV::CV_CMPGT_SCI_H: |
| 5462 | case RISCV::CV_CMPLEU_SCI_B: |
| 5463 | case RISCV::CV_CMPLEU_SCI_H: |
| 5464 | case RISCV::CV_CMPLE_SCI_B: |
| 5465 | case RISCV::CV_CMPLE_SCI_H: |
| 5466 | case RISCV::CV_CMPLTU_SCI_B: |
| 5467 | case RISCV::CV_CMPLTU_SCI_H: |
| 5468 | case RISCV::CV_CMPLT_SCI_B: |
| 5469 | case RISCV::CV_CMPLT_SCI_H: |
| 5470 | case RISCV::CV_CMPNE_SCI_B: |
| 5471 | case RISCV::CV_CMPNE_SCI_H: |
| 5472 | case RISCV::CV_DOTSP_SCI_B: |
| 5473 | case RISCV::CV_DOTSP_SCI_H: |
| 5474 | case RISCV::CV_DOTUP_SCI_B: |
| 5475 | case RISCV::CV_DOTUP_SCI_H: |
| 5476 | case RISCV::CV_DOTUSP_SCI_B: |
| 5477 | case RISCV::CV_DOTUSP_SCI_H: |
| 5478 | case RISCV::CV_EXTRACTU_B: |
| 5479 | case RISCV::CV_EXTRACTU_H: |
| 5480 | case RISCV::CV_EXTRACT_B: |
| 5481 | case RISCV::CV_EXTRACT_H: |
| 5482 | case RISCV::CV_MAXU_SCI_B: |
| 5483 | case RISCV::CV_MAXU_SCI_H: |
| 5484 | case RISCV::CV_MAX_SCI_B: |
| 5485 | case RISCV::CV_MAX_SCI_H: |
| 5486 | case RISCV::CV_MINU_SCI_B: |
| 5487 | case RISCV::CV_MINU_SCI_H: |
| 5488 | case RISCV::CV_MIN_SCI_B: |
| 5489 | case RISCV::CV_MIN_SCI_H: |
| 5490 | case RISCV::CV_OR_SCI_B: |
| 5491 | case RISCV::CV_OR_SCI_H: |
| 5492 | case RISCV::CV_SHUFFLEI0_SCI_B: |
| 5493 | case RISCV::CV_SHUFFLEI1_SCI_B: |
| 5494 | case RISCV::CV_SHUFFLEI2_SCI_B: |
| 5495 | case RISCV::CV_SHUFFLEI3_SCI_B: |
| 5496 | case RISCV::CV_SHUFFLE_SCI_H: |
| 5497 | case RISCV::CV_SLL_SCI_B: |
| 5498 | case RISCV::CV_SLL_SCI_H: |
| 5499 | case RISCV::CV_SRA_SCI_B: |
| 5500 | case RISCV::CV_SRA_SCI_H: |
| 5501 | case RISCV::CV_SRL_SCI_B: |
| 5502 | case RISCV::CV_SRL_SCI_H: |
| 5503 | case RISCV::CV_SUB_SCI_B: |
| 5504 | case RISCV::CV_SUB_SCI_H: |
| 5505 | case RISCV::CV_XOR_SCI_B: |
| 5506 | case RISCV::CV_XOR_SCI_H: { |
| 5507 | // op: rs1 |
| 5508 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5509 | Value |= (op & 0x1f) << 15; |
| 5510 | // op: rd |
| 5511 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5512 | Value |= (op & 0x1f) << 7; |
| 5513 | // op: imm6 |
| 5514 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5515 | Value |= (op & 0x1) << 25; |
| 5516 | Value |= (op & 0x3e) << 19; |
| 5517 | break; |
| 5518 | } |
| 5519 | case RISCV::CV_BCLR: |
| 5520 | case RISCV::CV_BITREV: |
| 5521 | case RISCV::CV_BSET: |
| 5522 | case RISCV::CV_EXTRACT: |
| 5523 | case RISCV::CV_EXTRACTU: { |
| 5524 | // op: rs1 |
| 5525 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5526 | Value |= (op & 0x1f) << 15; |
| 5527 | // op: rd |
| 5528 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5529 | Value |= (op & 0x1f) << 7; |
| 5530 | // op: is3 |
| 5531 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5532 | Value |= (op & 0x1f) << 25; |
| 5533 | // op: is2 |
| 5534 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 5535 | Value |= (op & 0x1f) << 20; |
| 5536 | break; |
| 5537 | } |
| 5538 | case RISCV::TH_EXT: |
| 5539 | case RISCV::TH_EXTU: { |
| 5540 | // op: rs1 |
| 5541 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5542 | Value |= (op & 0x1f) << 15; |
| 5543 | // op: rd |
| 5544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5545 | Value |= (op & 0x1f) << 7; |
| 5546 | // op: msb |
| 5547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5548 | Value |= (op & 0x3f) << 26; |
| 5549 | // op: lsb |
| 5550 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5551 | Value |= (op & 0x3f) << 20; |
| 5552 | break; |
| 5553 | } |
| 5554 | case RISCV::AES64KS1I: { |
| 5555 | // op: rs1 |
| 5556 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5557 | Value |= (op & 0x1f) << 15; |
| 5558 | // op: rd |
| 5559 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5560 | Value |= (op & 0x1f) << 7; |
| 5561 | // op: rnum |
| 5562 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5563 | Value |= (op & 0xf) << 20; |
| 5564 | break; |
| 5565 | } |
| 5566 | case RISCV::PSATI_W: |
| 5567 | case RISCV::PSLLI_W: |
| 5568 | case RISCV::PSRAI_W: |
| 5569 | case RISCV::PSRARI_W: |
| 5570 | case RISCV::PSRLI_W: |
| 5571 | case RISCV::PSSLAI_W: |
| 5572 | case RISCV::PUSATI_W: |
| 5573 | case RISCV::RORIW: |
| 5574 | case RISCV::SATI_RV32: |
| 5575 | case RISCV::SLLIW: |
| 5576 | case RISCV::SRAIW: |
| 5577 | case RISCV::SRARI_RV32: |
| 5578 | case RISCV::SRLIW: |
| 5579 | case RISCV::SSLAI: |
| 5580 | case RISCV::TH_SRRIW: |
| 5581 | case RISCV::USATI_RV32: { |
| 5582 | // op: rs1 |
| 5583 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5584 | Value |= (op & 0x1f) << 15; |
| 5585 | // op: rd |
| 5586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5587 | Value |= (op & 0x1f) << 7; |
| 5588 | // op: shamt |
| 5589 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5590 | Value |= (op & 0x1f) << 20; |
| 5591 | break; |
| 5592 | } |
| 5593 | case RISCV::SATI_RV64: |
| 5594 | case RISCV::SRARI_RV64: |
| 5595 | case RISCV::USATI_RV64: { |
| 5596 | // op: rs1 |
| 5597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5598 | Value |= (op & 0x1f) << 15; |
| 5599 | // op: rd |
| 5600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5601 | Value |= (op & 0x1f) << 7; |
| 5602 | // op: shamt |
| 5603 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5604 | Value |= (op & 0x3f) << 20; |
| 5605 | break; |
| 5606 | } |
| 5607 | case RISCV::PSLLI_B: |
| 5608 | case RISCV::PSRAI_B: |
| 5609 | case RISCV::PSRLI_B: { |
| 5610 | // op: rs1 |
| 5611 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5612 | Value |= (op & 0x1f) << 15; |
| 5613 | // op: rd |
| 5614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5615 | Value |= (op & 0x1f) << 7; |
| 5616 | // op: shamt |
| 5617 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5618 | Value |= (op & 0x7) << 20; |
| 5619 | break; |
| 5620 | } |
| 5621 | case RISCV::PSATI_H: |
| 5622 | case RISCV::PSLLI_H: |
| 5623 | case RISCV::PSRAI_H: |
| 5624 | case RISCV::PSRARI_H: |
| 5625 | case RISCV::PSRLI_H: |
| 5626 | case RISCV::PSSLAI_H: |
| 5627 | case RISCV::PUSATI_H: { |
| 5628 | // op: rs1 |
| 5629 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5630 | Value |= (op & 0x1f) << 15; |
| 5631 | // op: rd |
| 5632 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5633 | Value |= (op & 0x1f) << 7; |
| 5634 | // op: shamt |
| 5635 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5636 | Value |= (op & 0xf) << 20; |
| 5637 | break; |
| 5638 | } |
| 5639 | case RISCV::QC_EXT: |
| 5640 | case RISCV::QC_EXTD: |
| 5641 | case RISCV::QC_EXTDU: |
| 5642 | case RISCV::QC_EXTU: { |
| 5643 | // op: rs1 |
| 5644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5645 | Value |= (op & 0x1f) << 15; |
| 5646 | // op: rd |
| 5647 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5648 | Value |= (op & 0x1f) << 7; |
| 5649 | // op: shamt |
| 5650 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 5651 | Value |= (op & 0x1f) << 20; |
| 5652 | // op: width |
| 5653 | op = getImmOpValueMinus1(MI, OpNo: 2, Fixups, STI); |
| 5654 | Value |= (op & 0x1f) << 25; |
| 5655 | break; |
| 5656 | } |
| 5657 | case RISCV::BCLRI: |
| 5658 | case RISCV::BEXTI: |
| 5659 | case RISCV::BINVI: |
| 5660 | case RISCV::BSETI: |
| 5661 | case RISCV::RORI: |
| 5662 | case RISCV::SLLI: |
| 5663 | case RISCV::SLLI_UW: |
| 5664 | case RISCV::SRAI: |
| 5665 | case RISCV::SRLI: |
| 5666 | case RISCV::TH_SRRI: |
| 5667 | case RISCV::TH_TST: { |
| 5668 | // op: rs1 |
| 5669 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5670 | Value |= (op & 0x1f) << 15; |
| 5671 | // op: rd |
| 5672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5673 | Value |= (op & 0x1f) << 7; |
| 5674 | // op: shamt |
| 5675 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5676 | Value |= (op & 0x3f) << 20; |
| 5677 | break; |
| 5678 | } |
| 5679 | case RISCV::VSETVLI: { |
| 5680 | // op: rs1 |
| 5681 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5682 | Value |= (op & 0x1f) << 15; |
| 5683 | // op: rd |
| 5684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5685 | Value |= (op & 0x1f) << 7; |
| 5686 | // op: vtypei |
| 5687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5688 | Value |= (op & 0x7ff) << 20; |
| 5689 | break; |
| 5690 | } |
| 5691 | case RISCV::AIF_FROUND_PS: { |
| 5692 | // op: rs1 |
| 5693 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5694 | Value |= (op & 0x1f) << 15; |
| 5695 | // op: rm |
| 5696 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5697 | Value |= (op & 0x7) << 12; |
| 5698 | // op: rd |
| 5699 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5700 | Value |= (op & 0x1f) << 7; |
| 5701 | break; |
| 5702 | } |
| 5703 | case RISCV::QC_E_SB: |
| 5704 | case RISCV::QC_E_SH: |
| 5705 | case RISCV::QC_E_SW: { |
| 5706 | // op: rs1 |
| 5707 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5708 | Value |= (op & 0x1f) << 15; |
| 5709 | // op: rs2 |
| 5710 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5711 | Value |= (op & 0x1f) << 20; |
| 5712 | // op: imm |
| 5713 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5714 | Value |= (op & 0x3fffc00) << 22; |
| 5715 | Value |= (op & 0x3e0) << 20; |
| 5716 | Value |= (op & 0x1f) << 7; |
| 5717 | break; |
| 5718 | } |
| 5719 | case RISCV::CV_SB_rr: |
| 5720 | case RISCV::CV_SH_rr: |
| 5721 | case RISCV::CV_SW_rr: { |
| 5722 | // op: rs1 |
| 5723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5724 | Value |= (op & 0x1f) << 15; |
| 5725 | // op: rs2 |
| 5726 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5727 | Value |= (op & 0x1f) << 20; |
| 5728 | // op: rs3 |
| 5729 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5730 | Value |= (op & 0x1f) << 7; |
| 5731 | break; |
| 5732 | } |
| 5733 | case RISCV::QC_OUTW: { |
| 5734 | // op: rs1 |
| 5735 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5736 | Value |= (op & 0x1f) << 15; |
| 5737 | // op: rs2 |
| 5738 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5739 | Value |= (op & 0x1f) << 7; |
| 5740 | // op: imm14 |
| 5741 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 5742 | Value |= (op & 0x3ffc) << 18; |
| 5743 | break; |
| 5744 | } |
| 5745 | case RISCV::AIF_FSC32B_PS: |
| 5746 | case RISCV::AIF_FSC32H_PS: |
| 5747 | case RISCV::AIF_FSC32W_PS: |
| 5748 | case RISCV::AIF_FSCBG_PS: |
| 5749 | case RISCV::AIF_FSCBL_PS: |
| 5750 | case RISCV::AIF_FSCB_PS: |
| 5751 | case RISCV::AIF_FSCHG_PS: |
| 5752 | case RISCV::AIF_FSCHL_PS: |
| 5753 | case RISCV::AIF_FSCH_PS: |
| 5754 | case RISCV::AIF_FSCWG_PS: |
| 5755 | case RISCV::AIF_FSCWL_PS: |
| 5756 | case RISCV::AIF_FSCW_PS: { |
| 5757 | // op: rs1 |
| 5758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5759 | Value |= (op & 0x1f) << 15; |
| 5760 | // op: rs2 |
| 5761 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5762 | Value |= (op & 0x1f) << 20; |
| 5763 | // op: rs3 |
| 5764 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5765 | Value |= (op & 0x1f) << 7; |
| 5766 | break; |
| 5767 | } |
| 5768 | case RISCV::NDS_VLE4_V: |
| 5769 | case RISCV::SF_VTMV_V_T: |
| 5770 | case RISCV::VL1RE16_V: |
| 5771 | case RISCV::VL1RE32_V: |
| 5772 | case RISCV::VL1RE64_V: |
| 5773 | case RISCV::VL1RE8_V: |
| 5774 | case RISCV::VL2RE16_V: |
| 5775 | case RISCV::VL2RE32_V: |
| 5776 | case RISCV::VL2RE64_V: |
| 5777 | case RISCV::VL2RE8_V: |
| 5778 | case RISCV::VL4RE16_V: |
| 5779 | case RISCV::VL4RE32_V: |
| 5780 | case RISCV::VL4RE64_V: |
| 5781 | case RISCV::VL4RE8_V: |
| 5782 | case RISCV::VL8RE16_V: |
| 5783 | case RISCV::VL8RE32_V: |
| 5784 | case RISCV::VL8RE64_V: |
| 5785 | case RISCV::VL8RE8_V: |
| 5786 | case RISCV::VLM_V: { |
| 5787 | // op: rs1 |
| 5788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5789 | Value |= (op & 0x1f) << 15; |
| 5790 | // op: vd |
| 5791 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5792 | Value |= (op & 0x1f) << 7; |
| 5793 | break; |
| 5794 | } |
| 5795 | case RISCV::NDS_VLN8_V: |
| 5796 | case RISCV::NDS_VLNU8_V: |
| 5797 | case RISCV::VLE16FF_V: |
| 5798 | case RISCV::VLE16_V: |
| 5799 | case RISCV::VLE32FF_V: |
| 5800 | case RISCV::VLE32_V: |
| 5801 | case RISCV::VLE64FF_V: |
| 5802 | case RISCV::VLE64_V: |
| 5803 | case RISCV::VLE8FF_V: |
| 5804 | case RISCV::VLE8_V: |
| 5805 | case RISCV::VLSEG2E16FF_V: |
| 5806 | case RISCV::VLSEG2E16_V: |
| 5807 | case RISCV::VLSEG2E32FF_V: |
| 5808 | case RISCV::VLSEG2E32_V: |
| 5809 | case RISCV::VLSEG2E64FF_V: |
| 5810 | case RISCV::VLSEG2E64_V: |
| 5811 | case RISCV::VLSEG2E8FF_V: |
| 5812 | case RISCV::VLSEG2E8_V: |
| 5813 | case RISCV::VLSEG3E16FF_V: |
| 5814 | case RISCV::VLSEG3E16_V: |
| 5815 | case RISCV::VLSEG3E32FF_V: |
| 5816 | case RISCV::VLSEG3E32_V: |
| 5817 | case RISCV::VLSEG3E64FF_V: |
| 5818 | case RISCV::VLSEG3E64_V: |
| 5819 | case RISCV::VLSEG3E8FF_V: |
| 5820 | case RISCV::VLSEG3E8_V: |
| 5821 | case RISCV::VLSEG4E16FF_V: |
| 5822 | case RISCV::VLSEG4E16_V: |
| 5823 | case RISCV::VLSEG4E32FF_V: |
| 5824 | case RISCV::VLSEG4E32_V: |
| 5825 | case RISCV::VLSEG4E64FF_V: |
| 5826 | case RISCV::VLSEG4E64_V: |
| 5827 | case RISCV::VLSEG4E8FF_V: |
| 5828 | case RISCV::VLSEG4E8_V: |
| 5829 | case RISCV::VLSEG5E16FF_V: |
| 5830 | case RISCV::VLSEG5E16_V: |
| 5831 | case RISCV::VLSEG5E32FF_V: |
| 5832 | case RISCV::VLSEG5E32_V: |
| 5833 | case RISCV::VLSEG5E64FF_V: |
| 5834 | case RISCV::VLSEG5E64_V: |
| 5835 | case RISCV::VLSEG5E8FF_V: |
| 5836 | case RISCV::VLSEG5E8_V: |
| 5837 | case RISCV::VLSEG6E16FF_V: |
| 5838 | case RISCV::VLSEG6E16_V: |
| 5839 | case RISCV::VLSEG6E32FF_V: |
| 5840 | case RISCV::VLSEG6E32_V: |
| 5841 | case RISCV::VLSEG6E64FF_V: |
| 5842 | case RISCV::VLSEG6E64_V: |
| 5843 | case RISCV::VLSEG6E8FF_V: |
| 5844 | case RISCV::VLSEG6E8_V: |
| 5845 | case RISCV::VLSEG7E16FF_V: |
| 5846 | case RISCV::VLSEG7E16_V: |
| 5847 | case RISCV::VLSEG7E32FF_V: |
| 5848 | case RISCV::VLSEG7E32_V: |
| 5849 | case RISCV::VLSEG7E64FF_V: |
| 5850 | case RISCV::VLSEG7E64_V: |
| 5851 | case RISCV::VLSEG7E8FF_V: |
| 5852 | case RISCV::VLSEG7E8_V: |
| 5853 | case RISCV::VLSEG8E16FF_V: |
| 5854 | case RISCV::VLSEG8E16_V: |
| 5855 | case RISCV::VLSEG8E32FF_V: |
| 5856 | case RISCV::VLSEG8E32_V: |
| 5857 | case RISCV::VLSEG8E64FF_V: |
| 5858 | case RISCV::VLSEG8E64_V: |
| 5859 | case RISCV::VLSEG8E8FF_V: |
| 5860 | case RISCV::VLSEG8E8_V: { |
| 5861 | // op: rs1 |
| 5862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5863 | Value |= (op & 0x1f) << 15; |
| 5864 | // op: vd |
| 5865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5866 | Value |= (op & 0x1f) << 7; |
| 5867 | // op: vm |
| 5868 | op = getVMaskReg(MI, OpNo: 2, Fixups, STI); |
| 5869 | Value |= (op & 0x1) << 25; |
| 5870 | break; |
| 5871 | } |
| 5872 | case RISCV::VLSE16_V: |
| 5873 | case RISCV::VLSE32_V: |
| 5874 | case RISCV::VLSE64_V: |
| 5875 | case RISCV::VLSE8_V: |
| 5876 | case RISCV::VLSSEG2E16_V: |
| 5877 | case RISCV::VLSSEG2E32_V: |
| 5878 | case RISCV::VLSSEG2E64_V: |
| 5879 | case RISCV::VLSSEG2E8_V: |
| 5880 | case RISCV::VLSSEG3E16_V: |
| 5881 | case RISCV::VLSSEG3E32_V: |
| 5882 | case RISCV::VLSSEG3E64_V: |
| 5883 | case RISCV::VLSSEG3E8_V: |
| 5884 | case RISCV::VLSSEG4E16_V: |
| 5885 | case RISCV::VLSSEG4E32_V: |
| 5886 | case RISCV::VLSSEG4E64_V: |
| 5887 | case RISCV::VLSSEG4E8_V: |
| 5888 | case RISCV::VLSSEG5E16_V: |
| 5889 | case RISCV::VLSSEG5E32_V: |
| 5890 | case RISCV::VLSSEG5E64_V: |
| 5891 | case RISCV::VLSSEG5E8_V: |
| 5892 | case RISCV::VLSSEG6E16_V: |
| 5893 | case RISCV::VLSSEG6E32_V: |
| 5894 | case RISCV::VLSSEG6E64_V: |
| 5895 | case RISCV::VLSSEG6E8_V: |
| 5896 | case RISCV::VLSSEG7E16_V: |
| 5897 | case RISCV::VLSSEG7E32_V: |
| 5898 | case RISCV::VLSSEG7E64_V: |
| 5899 | case RISCV::VLSSEG7E8_V: |
| 5900 | case RISCV::VLSSEG8E16_V: |
| 5901 | case RISCV::VLSSEG8E32_V: |
| 5902 | case RISCV::VLSSEG8E64_V: |
| 5903 | case RISCV::VLSSEG8E8_V: { |
| 5904 | // op: rs1 |
| 5905 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5906 | Value |= (op & 0x1f) << 15; |
| 5907 | // op: vd |
| 5908 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5909 | Value |= (op & 0x1f) << 7; |
| 5910 | // op: vm |
| 5911 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 5912 | Value |= (op & 0x1) << 25; |
| 5913 | // op: rs2 |
| 5914 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5915 | Value |= (op & 0x1f) << 20; |
| 5916 | break; |
| 5917 | } |
| 5918 | case RISCV::VLOXEI16_V: |
| 5919 | case RISCV::VLOXEI32_V: |
| 5920 | case RISCV::VLOXEI64_V: |
| 5921 | case RISCV::VLOXEI8_V: |
| 5922 | case RISCV::VLOXSEG2EI16_V: |
| 5923 | case RISCV::VLOXSEG2EI32_V: |
| 5924 | case RISCV::VLOXSEG2EI64_V: |
| 5925 | case RISCV::VLOXSEG2EI8_V: |
| 5926 | case RISCV::VLOXSEG3EI16_V: |
| 5927 | case RISCV::VLOXSEG3EI32_V: |
| 5928 | case RISCV::VLOXSEG3EI64_V: |
| 5929 | case RISCV::VLOXSEG3EI8_V: |
| 5930 | case RISCV::VLOXSEG4EI16_V: |
| 5931 | case RISCV::VLOXSEG4EI32_V: |
| 5932 | case RISCV::VLOXSEG4EI64_V: |
| 5933 | case RISCV::VLOXSEG4EI8_V: |
| 5934 | case RISCV::VLOXSEG5EI16_V: |
| 5935 | case RISCV::VLOXSEG5EI32_V: |
| 5936 | case RISCV::VLOXSEG5EI64_V: |
| 5937 | case RISCV::VLOXSEG5EI8_V: |
| 5938 | case RISCV::VLOXSEG6EI16_V: |
| 5939 | case RISCV::VLOXSEG6EI32_V: |
| 5940 | case RISCV::VLOXSEG6EI64_V: |
| 5941 | case RISCV::VLOXSEG6EI8_V: |
| 5942 | case RISCV::VLOXSEG7EI16_V: |
| 5943 | case RISCV::VLOXSEG7EI32_V: |
| 5944 | case RISCV::VLOXSEG7EI64_V: |
| 5945 | case RISCV::VLOXSEG7EI8_V: |
| 5946 | case RISCV::VLOXSEG8EI16_V: |
| 5947 | case RISCV::VLOXSEG8EI32_V: |
| 5948 | case RISCV::VLOXSEG8EI64_V: |
| 5949 | case RISCV::VLOXSEG8EI8_V: |
| 5950 | case RISCV::VLUXEI16_V: |
| 5951 | case RISCV::VLUXEI32_V: |
| 5952 | case RISCV::VLUXEI64_V: |
| 5953 | case RISCV::VLUXEI8_V: |
| 5954 | case RISCV::VLUXSEG2EI16_V: |
| 5955 | case RISCV::VLUXSEG2EI32_V: |
| 5956 | case RISCV::VLUXSEG2EI64_V: |
| 5957 | case RISCV::VLUXSEG2EI8_V: |
| 5958 | case RISCV::VLUXSEG3EI16_V: |
| 5959 | case RISCV::VLUXSEG3EI32_V: |
| 5960 | case RISCV::VLUXSEG3EI64_V: |
| 5961 | case RISCV::VLUXSEG3EI8_V: |
| 5962 | case RISCV::VLUXSEG4EI16_V: |
| 5963 | case RISCV::VLUXSEG4EI32_V: |
| 5964 | case RISCV::VLUXSEG4EI64_V: |
| 5965 | case RISCV::VLUXSEG4EI8_V: |
| 5966 | case RISCV::VLUXSEG5EI16_V: |
| 5967 | case RISCV::VLUXSEG5EI32_V: |
| 5968 | case RISCV::VLUXSEG5EI64_V: |
| 5969 | case RISCV::VLUXSEG5EI8_V: |
| 5970 | case RISCV::VLUXSEG6EI16_V: |
| 5971 | case RISCV::VLUXSEG6EI32_V: |
| 5972 | case RISCV::VLUXSEG6EI64_V: |
| 5973 | case RISCV::VLUXSEG6EI8_V: |
| 5974 | case RISCV::VLUXSEG7EI16_V: |
| 5975 | case RISCV::VLUXSEG7EI32_V: |
| 5976 | case RISCV::VLUXSEG7EI64_V: |
| 5977 | case RISCV::VLUXSEG7EI8_V: |
| 5978 | case RISCV::VLUXSEG8EI16_V: |
| 5979 | case RISCV::VLUXSEG8EI32_V: |
| 5980 | case RISCV::VLUXSEG8EI64_V: |
| 5981 | case RISCV::VLUXSEG8EI8_V: { |
| 5982 | // op: rs1 |
| 5983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5984 | Value |= (op & 0x1f) << 15; |
| 5985 | // op: vd |
| 5986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5987 | Value |= (op & 0x1f) << 7; |
| 5988 | // op: vm |
| 5989 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 5990 | Value |= (op & 0x1) << 25; |
| 5991 | // op: vs2 |
| 5992 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5993 | Value |= (op & 0x1f) << 20; |
| 5994 | break; |
| 5995 | } |
| 5996 | case RISCV::VS1R_V: |
| 5997 | case RISCV::VS2R_V: |
| 5998 | case RISCV::VS4R_V: |
| 5999 | case RISCV::VS8R_V: |
| 6000 | case RISCV::VSM_V: { |
| 6001 | // op: rs1 |
| 6002 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6003 | Value |= (op & 0x1f) << 15; |
| 6004 | // op: vs3 |
| 6005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6006 | Value |= (op & 0x1f) << 7; |
| 6007 | break; |
| 6008 | } |
| 6009 | case RISCV::VSE16_V: |
| 6010 | case RISCV::VSE32_V: |
| 6011 | case RISCV::VSE64_V: |
| 6012 | case RISCV::VSE8_V: |
| 6013 | case RISCV::VSSEG2E16_V: |
| 6014 | case RISCV::VSSEG2E32_V: |
| 6015 | case RISCV::VSSEG2E64_V: |
| 6016 | case RISCV::VSSEG2E8_V: |
| 6017 | case RISCV::VSSEG3E16_V: |
| 6018 | case RISCV::VSSEG3E32_V: |
| 6019 | case RISCV::VSSEG3E64_V: |
| 6020 | case RISCV::VSSEG3E8_V: |
| 6021 | case RISCV::VSSEG4E16_V: |
| 6022 | case RISCV::VSSEG4E32_V: |
| 6023 | case RISCV::VSSEG4E64_V: |
| 6024 | case RISCV::VSSEG4E8_V: |
| 6025 | case RISCV::VSSEG5E16_V: |
| 6026 | case RISCV::VSSEG5E32_V: |
| 6027 | case RISCV::VSSEG5E64_V: |
| 6028 | case RISCV::VSSEG5E8_V: |
| 6029 | case RISCV::VSSEG6E16_V: |
| 6030 | case RISCV::VSSEG6E32_V: |
| 6031 | case RISCV::VSSEG6E64_V: |
| 6032 | case RISCV::VSSEG6E8_V: |
| 6033 | case RISCV::VSSEG7E16_V: |
| 6034 | case RISCV::VSSEG7E32_V: |
| 6035 | case RISCV::VSSEG7E64_V: |
| 6036 | case RISCV::VSSEG7E8_V: |
| 6037 | case RISCV::VSSEG8E16_V: |
| 6038 | case RISCV::VSSEG8E32_V: |
| 6039 | case RISCV::VSSEG8E64_V: |
| 6040 | case RISCV::VSSEG8E8_V: { |
| 6041 | // op: rs1 |
| 6042 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6043 | Value |= (op & 0x1f) << 15; |
| 6044 | // op: vs3 |
| 6045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6046 | Value |= (op & 0x1f) << 7; |
| 6047 | // op: vm |
| 6048 | op = getVMaskReg(MI, OpNo: 2, Fixups, STI); |
| 6049 | Value |= (op & 0x1) << 25; |
| 6050 | break; |
| 6051 | } |
| 6052 | case RISCV::VSSE16_V: |
| 6053 | case RISCV::VSSE32_V: |
| 6054 | case RISCV::VSSE64_V: |
| 6055 | case RISCV::VSSE8_V: |
| 6056 | case RISCV::VSSSEG2E16_V: |
| 6057 | case RISCV::VSSSEG2E32_V: |
| 6058 | case RISCV::VSSSEG2E64_V: |
| 6059 | case RISCV::VSSSEG2E8_V: |
| 6060 | case RISCV::VSSSEG3E16_V: |
| 6061 | case RISCV::VSSSEG3E32_V: |
| 6062 | case RISCV::VSSSEG3E64_V: |
| 6063 | case RISCV::VSSSEG3E8_V: |
| 6064 | case RISCV::VSSSEG4E16_V: |
| 6065 | case RISCV::VSSSEG4E32_V: |
| 6066 | case RISCV::VSSSEG4E64_V: |
| 6067 | case RISCV::VSSSEG4E8_V: |
| 6068 | case RISCV::VSSSEG5E16_V: |
| 6069 | case RISCV::VSSSEG5E32_V: |
| 6070 | case RISCV::VSSSEG5E64_V: |
| 6071 | case RISCV::VSSSEG5E8_V: |
| 6072 | case RISCV::VSSSEG6E16_V: |
| 6073 | case RISCV::VSSSEG6E32_V: |
| 6074 | case RISCV::VSSSEG6E64_V: |
| 6075 | case RISCV::VSSSEG6E8_V: |
| 6076 | case RISCV::VSSSEG7E16_V: |
| 6077 | case RISCV::VSSSEG7E32_V: |
| 6078 | case RISCV::VSSSEG7E64_V: |
| 6079 | case RISCV::VSSSEG7E8_V: |
| 6080 | case RISCV::VSSSEG8E16_V: |
| 6081 | case RISCV::VSSSEG8E32_V: |
| 6082 | case RISCV::VSSSEG8E64_V: |
| 6083 | case RISCV::VSSSEG8E8_V: { |
| 6084 | // op: rs1 |
| 6085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6086 | Value |= (op & 0x1f) << 15; |
| 6087 | // op: vs3 |
| 6088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6089 | Value |= (op & 0x1f) << 7; |
| 6090 | // op: vm |
| 6091 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 6092 | Value |= (op & 0x1) << 25; |
| 6093 | // op: rs2 |
| 6094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6095 | Value |= (op & 0x1f) << 20; |
| 6096 | break; |
| 6097 | } |
| 6098 | case RISCV::VSOXEI16_V: |
| 6099 | case RISCV::VSOXEI32_V: |
| 6100 | case RISCV::VSOXEI64_V: |
| 6101 | case RISCV::VSOXEI8_V: |
| 6102 | case RISCV::VSOXSEG2EI16_V: |
| 6103 | case RISCV::VSOXSEG2EI32_V: |
| 6104 | case RISCV::VSOXSEG2EI64_V: |
| 6105 | case RISCV::VSOXSEG2EI8_V: |
| 6106 | case RISCV::VSOXSEG3EI16_V: |
| 6107 | case RISCV::VSOXSEG3EI32_V: |
| 6108 | case RISCV::VSOXSEG3EI64_V: |
| 6109 | case RISCV::VSOXSEG3EI8_V: |
| 6110 | case RISCV::VSOXSEG4EI16_V: |
| 6111 | case RISCV::VSOXSEG4EI32_V: |
| 6112 | case RISCV::VSOXSEG4EI64_V: |
| 6113 | case RISCV::VSOXSEG4EI8_V: |
| 6114 | case RISCV::VSOXSEG5EI16_V: |
| 6115 | case RISCV::VSOXSEG5EI32_V: |
| 6116 | case RISCV::VSOXSEG5EI64_V: |
| 6117 | case RISCV::VSOXSEG5EI8_V: |
| 6118 | case RISCV::VSOXSEG6EI16_V: |
| 6119 | case RISCV::VSOXSEG6EI32_V: |
| 6120 | case RISCV::VSOXSEG6EI64_V: |
| 6121 | case RISCV::VSOXSEG6EI8_V: |
| 6122 | case RISCV::VSOXSEG7EI16_V: |
| 6123 | case RISCV::VSOXSEG7EI32_V: |
| 6124 | case RISCV::VSOXSEG7EI64_V: |
| 6125 | case RISCV::VSOXSEG7EI8_V: |
| 6126 | case RISCV::VSOXSEG8EI16_V: |
| 6127 | case RISCV::VSOXSEG8EI32_V: |
| 6128 | case RISCV::VSOXSEG8EI64_V: |
| 6129 | case RISCV::VSOXSEG8EI8_V: |
| 6130 | case RISCV::VSUXEI16_V: |
| 6131 | case RISCV::VSUXEI32_V: |
| 6132 | case RISCV::VSUXEI64_V: |
| 6133 | case RISCV::VSUXEI8_V: |
| 6134 | case RISCV::VSUXSEG2EI16_V: |
| 6135 | case RISCV::VSUXSEG2EI32_V: |
| 6136 | case RISCV::VSUXSEG2EI64_V: |
| 6137 | case RISCV::VSUXSEG2EI8_V: |
| 6138 | case RISCV::VSUXSEG3EI16_V: |
| 6139 | case RISCV::VSUXSEG3EI32_V: |
| 6140 | case RISCV::VSUXSEG3EI64_V: |
| 6141 | case RISCV::VSUXSEG3EI8_V: |
| 6142 | case RISCV::VSUXSEG4EI16_V: |
| 6143 | case RISCV::VSUXSEG4EI32_V: |
| 6144 | case RISCV::VSUXSEG4EI64_V: |
| 6145 | case RISCV::VSUXSEG4EI8_V: |
| 6146 | case RISCV::VSUXSEG5EI16_V: |
| 6147 | case RISCV::VSUXSEG5EI32_V: |
| 6148 | case RISCV::VSUXSEG5EI64_V: |
| 6149 | case RISCV::VSUXSEG5EI8_V: |
| 6150 | case RISCV::VSUXSEG6EI16_V: |
| 6151 | case RISCV::VSUXSEG6EI32_V: |
| 6152 | case RISCV::VSUXSEG6EI64_V: |
| 6153 | case RISCV::VSUXSEG6EI8_V: |
| 6154 | case RISCV::VSUXSEG7EI16_V: |
| 6155 | case RISCV::VSUXSEG7EI32_V: |
| 6156 | case RISCV::VSUXSEG7EI64_V: |
| 6157 | case RISCV::VSUXSEG7EI8_V: |
| 6158 | case RISCV::VSUXSEG8EI16_V: |
| 6159 | case RISCV::VSUXSEG8EI32_V: |
| 6160 | case RISCV::VSUXSEG8EI64_V: |
| 6161 | case RISCV::VSUXSEG8EI8_V: { |
| 6162 | // op: rs1 |
| 6163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6164 | Value |= (op & 0x1f) << 15; |
| 6165 | // op: vs3 |
| 6166 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6167 | Value |= (op & 0x1f) << 7; |
| 6168 | // op: vm |
| 6169 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 6170 | Value |= (op & 0x1) << 25; |
| 6171 | // op: vs2 |
| 6172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6173 | Value |= (op & 0x1f) << 20; |
| 6174 | break; |
| 6175 | } |
| 6176 | case RISCV::C_ADD: { |
| 6177 | // op: rs1 |
| 6178 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6179 | Value |= (op & 0x1f) << 7; |
| 6180 | // op: rs2 |
| 6181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6182 | Value |= (op & 0x1f) << 2; |
| 6183 | break; |
| 6184 | } |
| 6185 | case RISCV::AIF_MASKPOPC: |
| 6186 | case RISCV::AIF_MASKPOPCZ: { |
| 6187 | // op: rs1 |
| 6188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6189 | Value |= (op & 0x7) << 15; |
| 6190 | // op: rd |
| 6191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6192 | Value |= (op & 0x1f) << 7; |
| 6193 | break; |
| 6194 | } |
| 6195 | case RISCV::AIF_MASKNOT: { |
| 6196 | // op: rs1 |
| 6197 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6198 | Value |= (op & 0x7) << 15; |
| 6199 | // op: rd |
| 6200 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6201 | Value |= (op & 0x7) << 7; |
| 6202 | break; |
| 6203 | } |
| 6204 | case RISCV::QC_C_BEXTI: |
| 6205 | case RISCV::QC_C_BSETI: { |
| 6206 | // op: rs1 |
| 6207 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6208 | Value |= (op & 0x7) << 7; |
| 6209 | // op: shamt |
| 6210 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6211 | Value |= (op & 0x1f) << 2; |
| 6212 | break; |
| 6213 | } |
| 6214 | case RISCV::AIF_FBC_PS: |
| 6215 | case RISCV::AIF_FLQ2: |
| 6216 | case RISCV::AIF_FLW_PS: { |
| 6217 | // op: rs1 |
| 6218 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6219 | Value |= (op & 0x1f) << 15; |
| 6220 | // op: rd |
| 6221 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6222 | Value |= (op & 0x1f) << 7; |
| 6223 | // op: imm12 |
| 6224 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 6225 | Value |= (op & 0xfff) << 20; |
| 6226 | break; |
| 6227 | } |
| 6228 | case RISCV::CV_LBU_ri_inc: |
| 6229 | case RISCV::CV_LB_ri_inc: |
| 6230 | case RISCV::CV_LHU_ri_inc: |
| 6231 | case RISCV::CV_LH_ri_inc: |
| 6232 | case RISCV::CV_LW_ri_inc: { |
| 6233 | // op: rs1 |
| 6234 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6235 | Value |= (op & 0x1f) << 15; |
| 6236 | // op: rd |
| 6237 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6238 | Value |= (op & 0x1f) << 7; |
| 6239 | // op: imm12 |
| 6240 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6241 | Value |= (op & 0xfff) << 20; |
| 6242 | break; |
| 6243 | } |
| 6244 | case RISCV::CSRRC: |
| 6245 | case RISCV::CSRRS: |
| 6246 | case RISCV::CSRRW: { |
| 6247 | // op: rs1 |
| 6248 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6249 | Value |= (op & 0x1f) << 15; |
| 6250 | // op: rd |
| 6251 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6252 | Value |= (op & 0x1f) << 7; |
| 6253 | // op: imm12 |
| 6254 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6255 | Value |= (op & 0xfff) << 20; |
| 6256 | break; |
| 6257 | } |
| 6258 | case RISCV::TH_LBIA: |
| 6259 | case RISCV::TH_LBIB: |
| 6260 | case RISCV::TH_LBUIA: |
| 6261 | case RISCV::TH_LBUIB: |
| 6262 | case RISCV::TH_LDIA: |
| 6263 | case RISCV::TH_LDIB: |
| 6264 | case RISCV::TH_LHIA: |
| 6265 | case RISCV::TH_LHIB: |
| 6266 | case RISCV::TH_LHUIA: |
| 6267 | case RISCV::TH_LHUIB: |
| 6268 | case RISCV::TH_LWIA: |
| 6269 | case RISCV::TH_LWIB: |
| 6270 | case RISCV::TH_LWUIA: |
| 6271 | case RISCV::TH_LWUIB: { |
| 6272 | // op: rs1 |
| 6273 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6274 | Value |= (op & 0x1f) << 15; |
| 6275 | // op: rd |
| 6276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6277 | Value |= (op & 0x1f) << 7; |
| 6278 | // op: simm5 |
| 6279 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6280 | Value |= (op & 0x1f) << 20; |
| 6281 | // op: uimm2 |
| 6282 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 6283 | Value |= (op & 0x3) << 25; |
| 6284 | break; |
| 6285 | } |
| 6286 | case RISCV::QC_INSBRI: { |
| 6287 | // op: rs1 |
| 6288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6289 | Value |= (op & 0x1f) << 15; |
| 6290 | // op: rd |
| 6291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6292 | Value |= (op & 0x1f) << 7; |
| 6293 | // op: imm11 |
| 6294 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6295 | Value |= (op & 0x7ff) << 20; |
| 6296 | break; |
| 6297 | } |
| 6298 | case RISCV::QC_MULIADD: { |
| 6299 | // op: rs1 |
| 6300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6301 | Value |= (op & 0x1f) << 15; |
| 6302 | // op: rd |
| 6303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6304 | Value |= (op & 0x1f) << 7; |
| 6305 | // op: imm12 |
| 6306 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6307 | Value |= (op & 0xfff) << 20; |
| 6308 | break; |
| 6309 | } |
| 6310 | case RISCV::CV_INSERT_B: |
| 6311 | case RISCV::CV_INSERT_H: |
| 6312 | case RISCV::CV_SDOTSP_SCI_B: |
| 6313 | case RISCV::CV_SDOTSP_SCI_H: |
| 6314 | case RISCV::CV_SDOTUP_SCI_B: |
| 6315 | case RISCV::CV_SDOTUP_SCI_H: |
| 6316 | case RISCV::CV_SDOTUSP_SCI_B: |
| 6317 | case RISCV::CV_SDOTUSP_SCI_H: { |
| 6318 | // op: rs1 |
| 6319 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6320 | Value |= (op & 0x1f) << 15; |
| 6321 | // op: rd |
| 6322 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6323 | Value |= (op & 0x1f) << 7; |
| 6324 | // op: imm6 |
| 6325 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6326 | Value |= (op & 0x1) << 25; |
| 6327 | Value |= (op & 0x3e) << 19; |
| 6328 | break; |
| 6329 | } |
| 6330 | case RISCV::CV_INSERT: { |
| 6331 | // op: rs1 |
| 6332 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6333 | Value |= (op & 0x1f) << 15; |
| 6334 | // op: rd |
| 6335 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6336 | Value |= (op & 0x1f) << 7; |
| 6337 | // op: is3 |
| 6338 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6339 | Value |= (op & 0x1f) << 25; |
| 6340 | // op: is2 |
| 6341 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 6342 | Value |= (op & 0x1f) << 20; |
| 6343 | break; |
| 6344 | } |
| 6345 | case RISCV::QC_INSB: |
| 6346 | case RISCV::QC_INSBH: { |
| 6347 | // op: rs1 |
| 6348 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6349 | Value |= (op & 0x1f) << 15; |
| 6350 | // op: rd |
| 6351 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6352 | Value |= (op & 0x1f) << 7; |
| 6353 | // op: shamt |
| 6354 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 6355 | Value |= (op & 0x1f) << 20; |
| 6356 | // op: width |
| 6357 | op = getImmOpValueMinus1(MI, OpNo: 3, Fixups, STI); |
| 6358 | Value |= (op & 0x1f) << 25; |
| 6359 | break; |
| 6360 | } |
| 6361 | case RISCV::QC_SELECTIIEQ: |
| 6362 | case RISCV::QC_SELECTIINE: { |
| 6363 | // op: rs1 |
| 6364 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6365 | Value |= (op & 0x1f) << 15; |
| 6366 | // op: rd |
| 6367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6368 | Value |= (op & 0x1f) << 7; |
| 6369 | // op: simm1 |
| 6370 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6371 | Value |= (op & 0x1f) << 20; |
| 6372 | // op: simm2 |
| 6373 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 6374 | Value |= (op & 0x1f) << 27; |
| 6375 | break; |
| 6376 | } |
| 6377 | case RISCV::TH_SBIA: |
| 6378 | case RISCV::TH_SBIB: |
| 6379 | case RISCV::TH_SDIA: |
| 6380 | case RISCV::TH_SDIB: |
| 6381 | case RISCV::TH_SHIA: |
| 6382 | case RISCV::TH_SHIB: |
| 6383 | case RISCV::TH_SWIA: |
| 6384 | case RISCV::TH_SWIB: { |
| 6385 | // op: rs1 |
| 6386 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6387 | Value |= (op & 0x1f) << 15; |
| 6388 | // op: rd |
| 6389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6390 | Value |= (op & 0x1f) << 7; |
| 6391 | // op: simm5 |
| 6392 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6393 | Value |= (op & 0x1f) << 20; |
| 6394 | // op: uimm2 |
| 6395 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 6396 | Value |= (op & 0x3) << 25; |
| 6397 | break; |
| 6398 | } |
| 6399 | case RISCV::QC_LIEQI: |
| 6400 | case RISCV::QC_LIGEI: |
| 6401 | case RISCV::QC_LIGEUI: |
| 6402 | case RISCV::QC_LILTI: |
| 6403 | case RISCV::QC_LILTUI: |
| 6404 | case RISCV::QC_LINEI: { |
| 6405 | // op: rs2 |
| 6406 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6407 | Value |= (op & 0x1f) << 20; |
| 6408 | // op: rs1 |
| 6409 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6410 | Value |= (op & 0x1f) << 15; |
| 6411 | // op: rd |
| 6412 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6413 | Value |= (op & 0x1f) << 7; |
| 6414 | // op: simm |
| 6415 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 6416 | Value |= (op & 0x1f) << 27; |
| 6417 | break; |
| 6418 | } |
| 6419 | case RISCV::SSPUSH: { |
| 6420 | // op: rs2 |
| 6421 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6422 | Value |= (op & 0x1f) << 20; |
| 6423 | break; |
| 6424 | } |
| 6425 | case RISCV::AIF_SBG: |
| 6426 | case RISCV::AIF_SBL: |
| 6427 | case RISCV::AIF_SHG: |
| 6428 | case RISCV::AIF_SHL: |
| 6429 | case RISCV::HSV_B: |
| 6430 | case RISCV::HSV_D: |
| 6431 | case RISCV::HSV_H: |
| 6432 | case RISCV::HSV_W: |
| 6433 | case RISCV::SB_AQRL: |
| 6434 | case RISCV::SB_RL: |
| 6435 | case RISCV::SD_AQRL: |
| 6436 | case RISCV::SD_RL: |
| 6437 | case RISCV::SF_VLTE16: |
| 6438 | case RISCV::SF_VLTE32: |
| 6439 | case RISCV::SF_VLTE64: |
| 6440 | case RISCV::SF_VLTE8: |
| 6441 | case RISCV::SF_VSTE16: |
| 6442 | case RISCV::SF_VSTE32: |
| 6443 | case RISCV::SF_VSTE64: |
| 6444 | case RISCV::SF_VSTE8: |
| 6445 | case RISCV::SH_AQRL: |
| 6446 | case RISCV::SH_RL: |
| 6447 | case RISCV::SW_AQRL: |
| 6448 | case RISCV::SW_RL: { |
| 6449 | // op: rs2 |
| 6450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6451 | Value |= (op & 0x1f) << 20; |
| 6452 | // op: rs1 |
| 6453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6454 | Value |= (op & 0x1f) << 15; |
| 6455 | break; |
| 6456 | } |
| 6457 | case RISCV::QK_C_SB: { |
| 6458 | // op: rs2 |
| 6459 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6460 | Value |= (op & 0x7) << 2; |
| 6461 | // op: rs1 |
| 6462 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6463 | Value |= (op & 0x7) << 7; |
| 6464 | // op: imm |
| 6465 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 6466 | Value |= (op & 0x1) << 12; |
| 6467 | Value |= (op & 0x18) << 7; |
| 6468 | Value |= (op & 0x6) << 4; |
| 6469 | break; |
| 6470 | } |
| 6471 | case RISCV::C_SB: { |
| 6472 | // op: rs2 |
| 6473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6474 | Value |= (op & 0x7) << 2; |
| 6475 | // op: rs1 |
| 6476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6477 | Value |= (op & 0x7) << 7; |
| 6478 | // op: imm |
| 6479 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 6480 | Value |= (op & 0x1) << 6; |
| 6481 | Value |= (op & 0x2) << 4; |
| 6482 | break; |
| 6483 | } |
| 6484 | case RISCV::C_SH: |
| 6485 | case RISCV::C_SH_INX: { |
| 6486 | // op: rs2 |
| 6487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6488 | Value |= (op & 0x7) << 2; |
| 6489 | // op: rs1 |
| 6490 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6491 | Value |= (op & 0x7) << 7; |
| 6492 | // op: imm |
| 6493 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 6494 | Value |= (op & 0x2) << 4; |
| 6495 | break; |
| 6496 | } |
| 6497 | case RISCV::C_FSW: |
| 6498 | case RISCV::C_SW: |
| 6499 | case RISCV::C_SW_INX: { |
| 6500 | // op: rs2 |
| 6501 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6502 | Value |= (op & 0x7) << 2; |
| 6503 | // op: rs1 |
| 6504 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6505 | Value |= (op & 0x7) << 7; |
| 6506 | // op: imm |
| 6507 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 6508 | Value |= (op & 0x38) << 7; |
| 6509 | Value |= (op & 0x4) << 4; |
| 6510 | Value |= (op & 0x40) >> 1; |
| 6511 | break; |
| 6512 | } |
| 6513 | case RISCV::QK_C_SH: { |
| 6514 | // op: rs2 |
| 6515 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6516 | Value |= (op & 0x7) << 2; |
| 6517 | // op: rs1 |
| 6518 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6519 | Value |= (op & 0x7) << 7; |
| 6520 | // op: imm |
| 6521 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 6522 | Value |= (op & 0x38) << 7; |
| 6523 | Value |= (op & 0x6) << 4; |
| 6524 | break; |
| 6525 | } |
| 6526 | case RISCV::C_FSD: |
| 6527 | case RISCV::C_SD: |
| 6528 | case RISCV::C_SD_RV32: { |
| 6529 | // op: rs2 |
| 6530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6531 | Value |= (op & 0x7) << 2; |
| 6532 | // op: rs1 |
| 6533 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6534 | Value |= (op & 0x7) << 7; |
| 6535 | // op: imm |
| 6536 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 6537 | Value |= (op & 0x38) << 7; |
| 6538 | Value |= (op & 0xc0) >> 1; |
| 6539 | break; |
| 6540 | } |
| 6541 | case RISCV::NDS_FCVT_BF16_S: |
| 6542 | case RISCV::NDS_FCVT_S_BF16: { |
| 6543 | // op: rs2 |
| 6544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6545 | Value |= (op & 0x1f) << 20; |
| 6546 | // op: rd |
| 6547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6548 | Value |= (op & 0x1f) << 7; |
| 6549 | break; |
| 6550 | } |
| 6551 | case RISCV::HFENCE_GVMA: |
| 6552 | case RISCV::HFENCE_VVMA: |
| 6553 | case RISCV::HINVAL_GVMA: |
| 6554 | case RISCV::HINVAL_VVMA: |
| 6555 | case RISCV::SFENCE_VMA: |
| 6556 | case RISCV::SF_VTMV_T_V: |
| 6557 | case RISCV::SINVAL_VMA: |
| 6558 | case RISCV::TH_SFENCE_VMAS: { |
| 6559 | // op: rs2 |
| 6560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6561 | Value |= (op & 0x1f) << 20; |
| 6562 | // op: rs1 |
| 6563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6564 | Value |= (op & 0x1f) << 15; |
| 6565 | break; |
| 6566 | } |
| 6567 | case RISCV::AIF_AMOADDG_D: |
| 6568 | case RISCV::AIF_AMOADDG_W: |
| 6569 | case RISCV::AIF_AMOADDL_D: |
| 6570 | case RISCV::AIF_AMOADDL_W: |
| 6571 | case RISCV::AIF_AMOANDG_D: |
| 6572 | case RISCV::AIF_AMOANDG_W: |
| 6573 | case RISCV::AIF_AMOANDL_D: |
| 6574 | case RISCV::AIF_AMOANDL_W: |
| 6575 | case RISCV::AIF_AMOCMPSWAPG_D: |
| 6576 | case RISCV::AIF_AMOCMPSWAPG_W: |
| 6577 | case RISCV::AIF_AMOCMPSWAPL_D: |
| 6578 | case RISCV::AIF_AMOCMPSWAPL_W: |
| 6579 | case RISCV::AIF_AMOMAXG_D: |
| 6580 | case RISCV::AIF_AMOMAXG_W: |
| 6581 | case RISCV::AIF_AMOMAXL_D: |
| 6582 | case RISCV::AIF_AMOMAXL_W: |
| 6583 | case RISCV::AIF_AMOMAXUG_D: |
| 6584 | case RISCV::AIF_AMOMAXUG_W: |
| 6585 | case RISCV::AIF_AMOMAXUL_D: |
| 6586 | case RISCV::AIF_AMOMAXUL_W: |
| 6587 | case RISCV::AIF_AMOMING_D: |
| 6588 | case RISCV::AIF_AMOMING_W: |
| 6589 | case RISCV::AIF_AMOMINL_D: |
| 6590 | case RISCV::AIF_AMOMINL_W: |
| 6591 | case RISCV::AIF_AMOMINUG_D: |
| 6592 | case RISCV::AIF_AMOMINUG_W: |
| 6593 | case RISCV::AIF_AMOMINUL_D: |
| 6594 | case RISCV::AIF_AMOMINUL_W: |
| 6595 | case RISCV::AIF_AMOORG_D: |
| 6596 | case RISCV::AIF_AMOORG_W: |
| 6597 | case RISCV::AIF_AMOORL_D: |
| 6598 | case RISCV::AIF_AMOORL_W: |
| 6599 | case RISCV::AIF_AMOSWAPG_D: |
| 6600 | case RISCV::AIF_AMOSWAPG_W: |
| 6601 | case RISCV::AIF_AMOSWAPL_D: |
| 6602 | case RISCV::AIF_AMOSWAPL_W: |
| 6603 | case RISCV::AIF_AMOXORG_D: |
| 6604 | case RISCV::AIF_AMOXORG_W: |
| 6605 | case RISCV::AIF_AMOXORL_D: |
| 6606 | case RISCV::AIF_AMOXORL_W: |
| 6607 | case RISCV::AMOADD_B: |
| 6608 | case RISCV::AMOADD_B_AQ: |
| 6609 | case RISCV::AMOADD_B_AQRL: |
| 6610 | case RISCV::AMOADD_B_RL: |
| 6611 | case RISCV::AMOADD_D: |
| 6612 | case RISCV::AMOADD_D_AQ: |
| 6613 | case RISCV::AMOADD_D_AQRL: |
| 6614 | case RISCV::AMOADD_D_RL: |
| 6615 | case RISCV::AMOADD_H: |
| 6616 | case RISCV::AMOADD_H_AQ: |
| 6617 | case RISCV::AMOADD_H_AQRL: |
| 6618 | case RISCV::AMOADD_H_RL: |
| 6619 | case RISCV::AMOADD_W: |
| 6620 | case RISCV::AMOADD_W_AQ: |
| 6621 | case RISCV::AMOADD_W_AQRL: |
| 6622 | case RISCV::AMOADD_W_RL: |
| 6623 | case RISCV::AMOAND_B: |
| 6624 | case RISCV::AMOAND_B_AQ: |
| 6625 | case RISCV::AMOAND_B_AQRL: |
| 6626 | case RISCV::AMOAND_B_RL: |
| 6627 | case RISCV::AMOAND_D: |
| 6628 | case RISCV::AMOAND_D_AQ: |
| 6629 | case RISCV::AMOAND_D_AQRL: |
| 6630 | case RISCV::AMOAND_D_RL: |
| 6631 | case RISCV::AMOAND_H: |
| 6632 | case RISCV::AMOAND_H_AQ: |
| 6633 | case RISCV::AMOAND_H_AQRL: |
| 6634 | case RISCV::AMOAND_H_RL: |
| 6635 | case RISCV::AMOAND_W: |
| 6636 | case RISCV::AMOAND_W_AQ: |
| 6637 | case RISCV::AMOAND_W_AQRL: |
| 6638 | case RISCV::AMOAND_W_RL: |
| 6639 | case RISCV::AMOMAXU_B: |
| 6640 | case RISCV::AMOMAXU_B_AQ: |
| 6641 | case RISCV::AMOMAXU_B_AQRL: |
| 6642 | case RISCV::AMOMAXU_B_RL: |
| 6643 | case RISCV::AMOMAXU_D: |
| 6644 | case RISCV::AMOMAXU_D_AQ: |
| 6645 | case RISCV::AMOMAXU_D_AQRL: |
| 6646 | case RISCV::AMOMAXU_D_RL: |
| 6647 | case RISCV::AMOMAXU_H: |
| 6648 | case RISCV::AMOMAXU_H_AQ: |
| 6649 | case RISCV::AMOMAXU_H_AQRL: |
| 6650 | case RISCV::AMOMAXU_H_RL: |
| 6651 | case RISCV::AMOMAXU_W: |
| 6652 | case RISCV::AMOMAXU_W_AQ: |
| 6653 | case RISCV::AMOMAXU_W_AQRL: |
| 6654 | case RISCV::AMOMAXU_W_RL: |
| 6655 | case RISCV::AMOMAX_B: |
| 6656 | case RISCV::AMOMAX_B_AQ: |
| 6657 | case RISCV::AMOMAX_B_AQRL: |
| 6658 | case RISCV::AMOMAX_B_RL: |
| 6659 | case RISCV::AMOMAX_D: |
| 6660 | case RISCV::AMOMAX_D_AQ: |
| 6661 | case RISCV::AMOMAX_D_AQRL: |
| 6662 | case RISCV::AMOMAX_D_RL: |
| 6663 | case RISCV::AMOMAX_H: |
| 6664 | case RISCV::AMOMAX_H_AQ: |
| 6665 | case RISCV::AMOMAX_H_AQRL: |
| 6666 | case RISCV::AMOMAX_H_RL: |
| 6667 | case RISCV::AMOMAX_W: |
| 6668 | case RISCV::AMOMAX_W_AQ: |
| 6669 | case RISCV::AMOMAX_W_AQRL: |
| 6670 | case RISCV::AMOMAX_W_RL: |
| 6671 | case RISCV::AMOMINU_B: |
| 6672 | case RISCV::AMOMINU_B_AQ: |
| 6673 | case RISCV::AMOMINU_B_AQRL: |
| 6674 | case RISCV::AMOMINU_B_RL: |
| 6675 | case RISCV::AMOMINU_D: |
| 6676 | case RISCV::AMOMINU_D_AQ: |
| 6677 | case RISCV::AMOMINU_D_AQRL: |
| 6678 | case RISCV::AMOMINU_D_RL: |
| 6679 | case RISCV::AMOMINU_H: |
| 6680 | case RISCV::AMOMINU_H_AQ: |
| 6681 | case RISCV::AMOMINU_H_AQRL: |
| 6682 | case RISCV::AMOMINU_H_RL: |
| 6683 | case RISCV::AMOMINU_W: |
| 6684 | case RISCV::AMOMINU_W_AQ: |
| 6685 | case RISCV::AMOMINU_W_AQRL: |
| 6686 | case RISCV::AMOMINU_W_RL: |
| 6687 | case RISCV::AMOMIN_B: |
| 6688 | case RISCV::AMOMIN_B_AQ: |
| 6689 | case RISCV::AMOMIN_B_AQRL: |
| 6690 | case RISCV::AMOMIN_B_RL: |
| 6691 | case RISCV::AMOMIN_D: |
| 6692 | case RISCV::AMOMIN_D_AQ: |
| 6693 | case RISCV::AMOMIN_D_AQRL: |
| 6694 | case RISCV::AMOMIN_D_RL: |
| 6695 | case RISCV::AMOMIN_H: |
| 6696 | case RISCV::AMOMIN_H_AQ: |
| 6697 | case RISCV::AMOMIN_H_AQRL: |
| 6698 | case RISCV::AMOMIN_H_RL: |
| 6699 | case RISCV::AMOMIN_W: |
| 6700 | case RISCV::AMOMIN_W_AQ: |
| 6701 | case RISCV::AMOMIN_W_AQRL: |
| 6702 | case RISCV::AMOMIN_W_RL: |
| 6703 | case RISCV::AMOOR_B: |
| 6704 | case RISCV::AMOOR_B_AQ: |
| 6705 | case RISCV::AMOOR_B_AQRL: |
| 6706 | case RISCV::AMOOR_B_RL: |
| 6707 | case RISCV::AMOOR_D: |
| 6708 | case RISCV::AMOOR_D_AQ: |
| 6709 | case RISCV::AMOOR_D_AQRL: |
| 6710 | case RISCV::AMOOR_D_RL: |
| 6711 | case RISCV::AMOOR_H: |
| 6712 | case RISCV::AMOOR_H_AQ: |
| 6713 | case RISCV::AMOOR_H_AQRL: |
| 6714 | case RISCV::AMOOR_H_RL: |
| 6715 | case RISCV::AMOOR_W: |
| 6716 | case RISCV::AMOOR_W_AQ: |
| 6717 | case RISCV::AMOOR_W_AQRL: |
| 6718 | case RISCV::AMOOR_W_RL: |
| 6719 | case RISCV::AMOSWAP_B: |
| 6720 | case RISCV::AMOSWAP_B_AQ: |
| 6721 | case RISCV::AMOSWAP_B_AQRL: |
| 6722 | case RISCV::AMOSWAP_B_RL: |
| 6723 | case RISCV::AMOSWAP_D: |
| 6724 | case RISCV::AMOSWAP_D_AQ: |
| 6725 | case RISCV::AMOSWAP_D_AQRL: |
| 6726 | case RISCV::AMOSWAP_D_RL: |
| 6727 | case RISCV::AMOSWAP_H: |
| 6728 | case RISCV::AMOSWAP_H_AQ: |
| 6729 | case RISCV::AMOSWAP_H_AQRL: |
| 6730 | case RISCV::AMOSWAP_H_RL: |
| 6731 | case RISCV::AMOSWAP_W: |
| 6732 | case RISCV::AMOSWAP_W_AQ: |
| 6733 | case RISCV::AMOSWAP_W_AQRL: |
| 6734 | case RISCV::AMOSWAP_W_RL: |
| 6735 | case RISCV::AMOXOR_B: |
| 6736 | case RISCV::AMOXOR_B_AQ: |
| 6737 | case RISCV::AMOXOR_B_AQRL: |
| 6738 | case RISCV::AMOXOR_B_RL: |
| 6739 | case RISCV::AMOXOR_D: |
| 6740 | case RISCV::AMOXOR_D_AQ: |
| 6741 | case RISCV::AMOXOR_D_AQRL: |
| 6742 | case RISCV::AMOXOR_D_RL: |
| 6743 | case RISCV::AMOXOR_H: |
| 6744 | case RISCV::AMOXOR_H_AQ: |
| 6745 | case RISCV::AMOXOR_H_AQRL: |
| 6746 | case RISCV::AMOXOR_H_RL: |
| 6747 | case RISCV::AMOXOR_W: |
| 6748 | case RISCV::AMOXOR_W_AQ: |
| 6749 | case RISCV::AMOXOR_W_AQRL: |
| 6750 | case RISCV::AMOXOR_W_RL: |
| 6751 | case RISCV::NDS_LEA_B_ZE: |
| 6752 | case RISCV::NDS_LEA_D: |
| 6753 | case RISCV::NDS_LEA_D_ZE: |
| 6754 | case RISCV::NDS_LEA_H: |
| 6755 | case RISCV::NDS_LEA_H_ZE: |
| 6756 | case RISCV::NDS_LEA_W: |
| 6757 | case RISCV::NDS_LEA_W_ZE: |
| 6758 | case RISCV::SC_D: |
| 6759 | case RISCV::SC_D_AQ: |
| 6760 | case RISCV::SC_D_AQRL: |
| 6761 | case RISCV::SC_D_RL: |
| 6762 | case RISCV::SC_W: |
| 6763 | case RISCV::SC_W_AQ: |
| 6764 | case RISCV::SC_W_AQRL: |
| 6765 | case RISCV::SC_W_RL: |
| 6766 | case RISCV::SSAMOSWAP_D: |
| 6767 | case RISCV::SSAMOSWAP_D_AQ: |
| 6768 | case RISCV::SSAMOSWAP_D_AQRL: |
| 6769 | case RISCV::SSAMOSWAP_D_RL: |
| 6770 | case RISCV::SSAMOSWAP_W: |
| 6771 | case RISCV::SSAMOSWAP_W_AQ: |
| 6772 | case RISCV::SSAMOSWAP_W_AQRL: |
| 6773 | case RISCV::SSAMOSWAP_W_RL: { |
| 6774 | // op: rs2 |
| 6775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6776 | Value |= (op & 0x1f) << 20; |
| 6777 | // op: rs1 |
| 6778 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6779 | Value |= (op & 0x1f) << 15; |
| 6780 | // op: rd |
| 6781 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6782 | Value |= (op & 0x1f) << 7; |
| 6783 | break; |
| 6784 | } |
| 6785 | case RISCV::TH_LDD: |
| 6786 | case RISCV::TH_LWD: |
| 6787 | case RISCV::TH_LWUD: |
| 6788 | case RISCV::TH_SDD: |
| 6789 | case RISCV::TH_SWD: { |
| 6790 | // op: rs2 |
| 6791 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6792 | Value |= (op & 0x1f) << 20; |
| 6793 | // op: rs1 |
| 6794 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6795 | Value |= (op & 0x1f) << 15; |
| 6796 | // op: rd |
| 6797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6798 | Value |= (op & 0x1f) << 7; |
| 6799 | // op: uimm2 |
| 6800 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 6801 | Value |= (op & 0x3) << 25; |
| 6802 | break; |
| 6803 | } |
| 6804 | case RISCV::CM_MVA01S: |
| 6805 | case RISCV::CM_MVSA01: |
| 6806 | case RISCV::QC_CM_MVA01S: |
| 6807 | case RISCV::QC_CM_MVSA01: { |
| 6808 | // op: rs2 |
| 6809 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6810 | Value |= (op & 0x7) << 2; |
| 6811 | // op: rs1 |
| 6812 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6813 | Value |= (op & 0x7) << 7; |
| 6814 | break; |
| 6815 | } |
| 6816 | case RISCV::QC_CSRRWRI: { |
| 6817 | // op: rs2 |
| 6818 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6819 | Value |= (op & 0x1f) << 20; |
| 6820 | // op: rs1 |
| 6821 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 6822 | Value |= (op & 0x1f) << 15; |
| 6823 | // op: rd |
| 6824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6825 | Value |= (op & 0x1f) << 7; |
| 6826 | break; |
| 6827 | } |
| 6828 | case RISCV::FADD_D: |
| 6829 | case RISCV::FADD_D_IN32X: |
| 6830 | case RISCV::FADD_D_INX: |
| 6831 | case RISCV::FADD_H: |
| 6832 | case RISCV::FADD_H_INX: |
| 6833 | case RISCV::FADD_Q: |
| 6834 | case RISCV::FADD_S: |
| 6835 | case RISCV::FADD_S_INX: |
| 6836 | case RISCV::FDIV_D: |
| 6837 | case RISCV::FDIV_D_IN32X: |
| 6838 | case RISCV::FDIV_D_INX: |
| 6839 | case RISCV::FDIV_H: |
| 6840 | case RISCV::FDIV_H_INX: |
| 6841 | case RISCV::FDIV_Q: |
| 6842 | case RISCV::FDIV_S: |
| 6843 | case RISCV::FDIV_S_INX: |
| 6844 | case RISCV::FMUL_D: |
| 6845 | case RISCV::FMUL_D_IN32X: |
| 6846 | case RISCV::FMUL_D_INX: |
| 6847 | case RISCV::FMUL_H: |
| 6848 | case RISCV::FMUL_H_INX: |
| 6849 | case RISCV::FMUL_Q: |
| 6850 | case RISCV::FMUL_S: |
| 6851 | case RISCV::FMUL_S_INX: |
| 6852 | case RISCV::FSUB_D: |
| 6853 | case RISCV::FSUB_D_IN32X: |
| 6854 | case RISCV::FSUB_D_INX: |
| 6855 | case RISCV::FSUB_H: |
| 6856 | case RISCV::FSUB_H_INX: |
| 6857 | case RISCV::FSUB_Q: |
| 6858 | case RISCV::FSUB_S: |
| 6859 | case RISCV::FSUB_S_INX: { |
| 6860 | // op: rs2 |
| 6861 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6862 | Value |= (op & 0x1f) << 20; |
| 6863 | // op: rs1 |
| 6864 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6865 | Value |= (op & 0x1f) << 15; |
| 6866 | // op: frm |
| 6867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6868 | Value |= (op & 0x7) << 12; |
| 6869 | // op: rd |
| 6870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6871 | Value |= (op & 0x1f) << 7; |
| 6872 | break; |
| 6873 | } |
| 6874 | case RISCV::PM2WADDSU_H: |
| 6875 | case RISCV::PM2WADDU_H: |
| 6876 | case RISCV::PM2WADD_H: |
| 6877 | case RISCV::PM2WADD_HX: |
| 6878 | case RISCV::PM2WSUB_H: |
| 6879 | case RISCV::PM2WSUB_HX: |
| 6880 | case RISCV::PWADDU_B: |
| 6881 | case RISCV::PWADDU_H: |
| 6882 | case RISCV::PWADD_B: |
| 6883 | case RISCV::PWADD_H: |
| 6884 | case RISCV::PWMULSU_B: |
| 6885 | case RISCV::PWMULSU_H: |
| 6886 | case RISCV::PWMULU_B: |
| 6887 | case RISCV::PWMULU_H: |
| 6888 | case RISCV::PWMUL_B: |
| 6889 | case RISCV::PWMUL_H: |
| 6890 | case RISCV::PWSLA_BS: |
| 6891 | case RISCV::PWSLA_HS: |
| 6892 | case RISCV::PWSLL_BS: |
| 6893 | case RISCV::PWSLL_HS: |
| 6894 | case RISCV::PWSUBU_B: |
| 6895 | case RISCV::PWSUBU_H: |
| 6896 | case RISCV::PWSUB_B: |
| 6897 | case RISCV::PWSUB_H: |
| 6898 | case RISCV::WADD: |
| 6899 | case RISCV::WADDU: |
| 6900 | case RISCV::WMUL: |
| 6901 | case RISCV::WMULSU: |
| 6902 | case RISCV::WMULU: |
| 6903 | case RISCV::WSLA: |
| 6904 | case RISCV::WSLL: |
| 6905 | case RISCV::WSUB: |
| 6906 | case RISCV::WSUBU: |
| 6907 | case RISCV::WZIP16P: |
| 6908 | case RISCV::WZIP8P: { |
| 6909 | // op: rs2 |
| 6910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6911 | Value |= (op & 0x1f) << 20; |
| 6912 | // op: rs1 |
| 6913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6914 | Value |= (op & 0x1f) << 15; |
| 6915 | // op: rd |
| 6916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6917 | Value |= (op & 0x1e) << 7; |
| 6918 | break; |
| 6919 | } |
| 6920 | case RISCV::AADD: |
| 6921 | case RISCV::AADDU: |
| 6922 | case RISCV::ADD: |
| 6923 | case RISCV::ADDW: |
| 6924 | case RISCV::ADD_UW: |
| 6925 | case RISCV::AES64DS: |
| 6926 | case RISCV::AES64DSM: |
| 6927 | case RISCV::AES64ES: |
| 6928 | case RISCV::AES64ESM: |
| 6929 | case RISCV::AES64KS2: |
| 6930 | case RISCV::AIF_BITMIXB: |
| 6931 | case RISCV::AIF_CUBEFACEIDX_PS: |
| 6932 | case RISCV::AIF_CUBEFACE_PS: |
| 6933 | case RISCV::AIF_CUBESGNSC_PS: |
| 6934 | case RISCV::AIF_CUBESGNTC_PS: |
| 6935 | case RISCV::AIF_FADD_PI: |
| 6936 | case RISCV::AIF_FAMOADDG_PI: |
| 6937 | case RISCV::AIF_FAMOADDL_PI: |
| 6938 | case RISCV::AIF_FAMOANDG_PI: |
| 6939 | case RISCV::AIF_FAMOANDL_PI: |
| 6940 | case RISCV::AIF_FAMOMAXG_PI: |
| 6941 | case RISCV::AIF_FAMOMAXG_PS: |
| 6942 | case RISCV::AIF_FAMOMAXL_PI: |
| 6943 | case RISCV::AIF_FAMOMAXL_PS: |
| 6944 | case RISCV::AIF_FAMOMAXUG_PI: |
| 6945 | case RISCV::AIF_FAMOMAXUL_PI: |
| 6946 | case RISCV::AIF_FAMOMING_PI: |
| 6947 | case RISCV::AIF_FAMOMING_PS: |
| 6948 | case RISCV::AIF_FAMOMINL_PI: |
| 6949 | case RISCV::AIF_FAMOMINL_PS: |
| 6950 | case RISCV::AIF_FAMOMINUG_PI: |
| 6951 | case RISCV::AIF_FAMOMINUL_PI: |
| 6952 | case RISCV::AIF_FAMOORG_PI: |
| 6953 | case RISCV::AIF_FAMOORL_PI: |
| 6954 | case RISCV::AIF_FAMOSWAPG_PI: |
| 6955 | case RISCV::AIF_FAMOSWAPL_PI: |
| 6956 | case RISCV::AIF_FAMOXORG_PI: |
| 6957 | case RISCV::AIF_FAMOXORL_PI: |
| 6958 | case RISCV::AIF_FAND_PI: |
| 6959 | case RISCV::AIF_FCMOVM_PS: |
| 6960 | case RISCV::AIF_FDIVU_PI: |
| 6961 | case RISCV::AIF_FDIV_PI: |
| 6962 | case RISCV::AIF_FEQM_PS: |
| 6963 | case RISCV::AIF_FEQ_PI: |
| 6964 | case RISCV::AIF_FEQ_PS: |
| 6965 | case RISCV::AIF_FG32B_PS: |
| 6966 | case RISCV::AIF_FG32H_PS: |
| 6967 | case RISCV::AIF_FG32W_PS: |
| 6968 | case RISCV::AIF_FGBG_PS: |
| 6969 | case RISCV::AIF_FGBL_PS: |
| 6970 | case RISCV::AIF_FGB_PS: |
| 6971 | case RISCV::AIF_FGHG_PS: |
| 6972 | case RISCV::AIF_FGHL_PS: |
| 6973 | case RISCV::AIF_FGH_PS: |
| 6974 | case RISCV::AIF_FGWG_PS: |
| 6975 | case RISCV::AIF_FGWL_PS: |
| 6976 | case RISCV::AIF_FGW_PS: |
| 6977 | case RISCV::AIF_FLEM_PS: |
| 6978 | case RISCV::AIF_FLE_PI: |
| 6979 | case RISCV::AIF_FLE_PS: |
| 6980 | case RISCV::AIF_FLTM_PI: |
| 6981 | case RISCV::AIF_FLTM_PS: |
| 6982 | case RISCV::AIF_FLTU_PI: |
| 6983 | case RISCV::AIF_FLT_PI: |
| 6984 | case RISCV::AIF_FLT_PS: |
| 6985 | case RISCV::AIF_FMAXU_PI: |
| 6986 | case RISCV::AIF_FMAX_PI: |
| 6987 | case RISCV::AIF_FMAX_PS: |
| 6988 | case RISCV::AIF_FMINU_PI: |
| 6989 | case RISCV::AIF_FMIN_PI: |
| 6990 | case RISCV::AIF_FMIN_PS: |
| 6991 | case RISCV::AIF_FMULHU_PI: |
| 6992 | case RISCV::AIF_FMULH_PI: |
| 6993 | case RISCV::AIF_FMUL_PI: |
| 6994 | case RISCV::AIF_FOR_PI: |
| 6995 | case RISCV::AIF_FRCP_FIX_RAST: |
| 6996 | case RISCV::AIF_FREMU_PI: |
| 6997 | case RISCV::AIF_FREM_PI: |
| 6998 | case RISCV::AIF_FSGNJN_PS: |
| 6999 | case RISCV::AIF_FSGNJX_PS: |
| 7000 | case RISCV::AIF_FSGNJ_PS: |
| 7001 | case RISCV::AIF_FSLL_PI: |
| 7002 | case RISCV::AIF_FSRA_PI: |
| 7003 | case RISCV::AIF_FSRL_PI: |
| 7004 | case RISCV::AIF_FSUB_PI: |
| 7005 | case RISCV::AIF_FXOR_PI: |
| 7006 | case RISCV::AIF_PACKB: |
| 7007 | case RISCV::AND: |
| 7008 | case RISCV::ANDN: |
| 7009 | case RISCV::ASUB: |
| 7010 | case RISCV::ASUBU: |
| 7011 | case RISCV::BCLR: |
| 7012 | case RISCV::BEXT: |
| 7013 | case RISCV::BINV: |
| 7014 | case RISCV::BSET: |
| 7015 | case RISCV::CLMUL: |
| 7016 | case RISCV::CLMULH: |
| 7017 | case RISCV::CLMULR: |
| 7018 | case RISCV::CV_ADD_B: |
| 7019 | case RISCV::CV_ADD_DIV2: |
| 7020 | case RISCV::CV_ADD_DIV4: |
| 7021 | case RISCV::CV_ADD_DIV8: |
| 7022 | case RISCV::CV_ADD_H: |
| 7023 | case RISCV::CV_ADD_SC_B: |
| 7024 | case RISCV::CV_ADD_SC_H: |
| 7025 | case RISCV::CV_AND_B: |
| 7026 | case RISCV::CV_AND_H: |
| 7027 | case RISCV::CV_AND_SC_B: |
| 7028 | case RISCV::CV_AND_SC_H: |
| 7029 | case RISCV::CV_AVGU_B: |
| 7030 | case RISCV::CV_AVGU_H: |
| 7031 | case RISCV::CV_AVGU_SC_B: |
| 7032 | case RISCV::CV_AVGU_SC_H: |
| 7033 | case RISCV::CV_AVG_B: |
| 7034 | case RISCV::CV_AVG_H: |
| 7035 | case RISCV::CV_AVG_SC_B: |
| 7036 | case RISCV::CV_AVG_SC_H: |
| 7037 | case RISCV::CV_BCLRR: |
| 7038 | case RISCV::CV_BSETR: |
| 7039 | case RISCV::CV_CLIPR: |
| 7040 | case RISCV::CV_CLIPUR: |
| 7041 | case RISCV::CV_CMPEQ_B: |
| 7042 | case RISCV::CV_CMPEQ_H: |
| 7043 | case RISCV::CV_CMPEQ_SC_B: |
| 7044 | case RISCV::CV_CMPEQ_SC_H: |
| 7045 | case RISCV::CV_CMPGEU_B: |
| 7046 | case RISCV::CV_CMPGEU_H: |
| 7047 | case RISCV::CV_CMPGEU_SC_B: |
| 7048 | case RISCV::CV_CMPGEU_SC_H: |
| 7049 | case RISCV::CV_CMPGE_B: |
| 7050 | case RISCV::CV_CMPGE_H: |
| 7051 | case RISCV::CV_CMPGE_SC_B: |
| 7052 | case RISCV::CV_CMPGE_SC_H: |
| 7053 | case RISCV::CV_CMPGTU_B: |
| 7054 | case RISCV::CV_CMPGTU_H: |
| 7055 | case RISCV::CV_CMPGTU_SC_B: |
| 7056 | case RISCV::CV_CMPGTU_SC_H: |
| 7057 | case RISCV::CV_CMPGT_B: |
| 7058 | case RISCV::CV_CMPGT_H: |
| 7059 | case RISCV::CV_CMPGT_SC_B: |
| 7060 | case RISCV::CV_CMPGT_SC_H: |
| 7061 | case RISCV::CV_CMPLEU_B: |
| 7062 | case RISCV::CV_CMPLEU_H: |
| 7063 | case RISCV::CV_CMPLEU_SC_B: |
| 7064 | case RISCV::CV_CMPLEU_SC_H: |
| 7065 | case RISCV::CV_CMPLE_B: |
| 7066 | case RISCV::CV_CMPLE_H: |
| 7067 | case RISCV::CV_CMPLE_SC_B: |
| 7068 | case RISCV::CV_CMPLE_SC_H: |
| 7069 | case RISCV::CV_CMPLTU_B: |
| 7070 | case RISCV::CV_CMPLTU_H: |
| 7071 | case RISCV::CV_CMPLTU_SC_B: |
| 7072 | case RISCV::CV_CMPLTU_SC_H: |
| 7073 | case RISCV::CV_CMPLT_B: |
| 7074 | case RISCV::CV_CMPLT_H: |
| 7075 | case RISCV::CV_CMPLT_SC_B: |
| 7076 | case RISCV::CV_CMPLT_SC_H: |
| 7077 | case RISCV::CV_CMPNE_B: |
| 7078 | case RISCV::CV_CMPNE_H: |
| 7079 | case RISCV::CV_CMPNE_SC_B: |
| 7080 | case RISCV::CV_CMPNE_SC_H: |
| 7081 | case RISCV::CV_DOTSP_B: |
| 7082 | case RISCV::CV_DOTSP_H: |
| 7083 | case RISCV::CV_DOTSP_SC_B: |
| 7084 | case RISCV::CV_DOTSP_SC_H: |
| 7085 | case RISCV::CV_DOTUP_B: |
| 7086 | case RISCV::CV_DOTUP_H: |
| 7087 | case RISCV::CV_DOTUP_SC_B: |
| 7088 | case RISCV::CV_DOTUP_SC_H: |
| 7089 | case RISCV::CV_DOTUSP_B: |
| 7090 | case RISCV::CV_DOTUSP_H: |
| 7091 | case RISCV::CV_DOTUSP_SC_B: |
| 7092 | case RISCV::CV_DOTUSP_SC_H: |
| 7093 | case RISCV::CV_EXTRACTR: |
| 7094 | case RISCV::CV_EXTRACTUR: |
| 7095 | case RISCV::CV_LBU_rr: |
| 7096 | case RISCV::CV_LB_rr: |
| 7097 | case RISCV::CV_LHU_rr: |
| 7098 | case RISCV::CV_LH_rr: |
| 7099 | case RISCV::CV_LW_rr: |
| 7100 | case RISCV::CV_MAX: |
| 7101 | case RISCV::CV_MAXU: |
| 7102 | case RISCV::CV_MAXU_B: |
| 7103 | case RISCV::CV_MAXU_H: |
| 7104 | case RISCV::CV_MAXU_SC_B: |
| 7105 | case RISCV::CV_MAXU_SC_H: |
| 7106 | case RISCV::CV_MAX_B: |
| 7107 | case RISCV::CV_MAX_H: |
| 7108 | case RISCV::CV_MAX_SC_B: |
| 7109 | case RISCV::CV_MAX_SC_H: |
| 7110 | case RISCV::CV_MIN: |
| 7111 | case RISCV::CV_MINU: |
| 7112 | case RISCV::CV_MINU_B: |
| 7113 | case RISCV::CV_MINU_H: |
| 7114 | case RISCV::CV_MINU_SC_B: |
| 7115 | case RISCV::CV_MINU_SC_H: |
| 7116 | case RISCV::CV_MIN_B: |
| 7117 | case RISCV::CV_MIN_H: |
| 7118 | case RISCV::CV_MIN_SC_B: |
| 7119 | case RISCV::CV_MIN_SC_H: |
| 7120 | case RISCV::CV_OR_B: |
| 7121 | case RISCV::CV_OR_H: |
| 7122 | case RISCV::CV_OR_SC_B: |
| 7123 | case RISCV::CV_OR_SC_H: |
| 7124 | case RISCV::CV_PACK: |
| 7125 | case RISCV::CV_PACK_H: |
| 7126 | case RISCV::CV_ROR: |
| 7127 | case RISCV::CV_SHUFFLE_B: |
| 7128 | case RISCV::CV_SHUFFLE_H: |
| 7129 | case RISCV::CV_SLE: |
| 7130 | case RISCV::CV_SLEU: |
| 7131 | case RISCV::CV_SLL_B: |
| 7132 | case RISCV::CV_SLL_H: |
| 7133 | case RISCV::CV_SLL_SC_B: |
| 7134 | case RISCV::CV_SLL_SC_H: |
| 7135 | case RISCV::CV_SRA_B: |
| 7136 | case RISCV::CV_SRA_H: |
| 7137 | case RISCV::CV_SRA_SC_B: |
| 7138 | case RISCV::CV_SRA_SC_H: |
| 7139 | case RISCV::CV_SRL_B: |
| 7140 | case RISCV::CV_SRL_H: |
| 7141 | case RISCV::CV_SRL_SC_B: |
| 7142 | case RISCV::CV_SRL_SC_H: |
| 7143 | case RISCV::CV_SUBROTMJ: |
| 7144 | case RISCV::CV_SUBROTMJ_DIV2: |
| 7145 | case RISCV::CV_SUBROTMJ_DIV4: |
| 7146 | case RISCV::CV_SUBROTMJ_DIV8: |
| 7147 | case RISCV::CV_SUB_B: |
| 7148 | case RISCV::CV_SUB_DIV2: |
| 7149 | case RISCV::CV_SUB_DIV4: |
| 7150 | case RISCV::CV_SUB_DIV8: |
| 7151 | case RISCV::CV_SUB_H: |
| 7152 | case RISCV::CV_SUB_SC_B: |
| 7153 | case RISCV::CV_SUB_SC_H: |
| 7154 | case RISCV::CV_XOR_B: |
| 7155 | case RISCV::CV_XOR_H: |
| 7156 | case RISCV::CV_XOR_SC_B: |
| 7157 | case RISCV::CV_XOR_SC_H: |
| 7158 | case RISCV::CZERO_EQZ: |
| 7159 | case RISCV::CZERO_NEZ: |
| 7160 | case RISCV::DIV: |
| 7161 | case RISCV::DIVU: |
| 7162 | case RISCV::DIVUW: |
| 7163 | case RISCV::DIVW: |
| 7164 | case RISCV::FEQ_D: |
| 7165 | case RISCV::FEQ_D_IN32X: |
| 7166 | case RISCV::FEQ_D_INX: |
| 7167 | case RISCV::FEQ_H: |
| 7168 | case RISCV::FEQ_H_INX: |
| 7169 | case RISCV::FEQ_Q: |
| 7170 | case RISCV::FEQ_S: |
| 7171 | case RISCV::FEQ_S_INX: |
| 7172 | case RISCV::FLEQ_D: |
| 7173 | case RISCV::FLEQ_H: |
| 7174 | case RISCV::FLEQ_Q: |
| 7175 | case RISCV::FLEQ_S: |
| 7176 | case RISCV::FLE_D: |
| 7177 | case RISCV::FLE_D_IN32X: |
| 7178 | case RISCV::FLE_D_INX: |
| 7179 | case RISCV::FLE_H: |
| 7180 | case RISCV::FLE_H_INX: |
| 7181 | case RISCV::FLE_Q: |
| 7182 | case RISCV::FLE_S: |
| 7183 | case RISCV::FLE_S_INX: |
| 7184 | case RISCV::FLTQ_D: |
| 7185 | case RISCV::FLTQ_H: |
| 7186 | case RISCV::FLTQ_Q: |
| 7187 | case RISCV::FLTQ_S: |
| 7188 | case RISCV::FLT_D: |
| 7189 | case RISCV::FLT_D_IN32X: |
| 7190 | case RISCV::FLT_D_INX: |
| 7191 | case RISCV::FLT_H: |
| 7192 | case RISCV::FLT_H_INX: |
| 7193 | case RISCV::FLT_Q: |
| 7194 | case RISCV::FLT_S: |
| 7195 | case RISCV::FLT_S_INX: |
| 7196 | case RISCV::FMAXM_D: |
| 7197 | case RISCV::FMAXM_H: |
| 7198 | case RISCV::FMAXM_Q: |
| 7199 | case RISCV::FMAXM_S: |
| 7200 | case RISCV::FMAX_D: |
| 7201 | case RISCV::FMAX_D_IN32X: |
| 7202 | case RISCV::FMAX_D_INX: |
| 7203 | case RISCV::FMAX_H: |
| 7204 | case RISCV::FMAX_H_INX: |
| 7205 | case RISCV::FMAX_Q: |
| 7206 | case RISCV::FMAX_S: |
| 7207 | case RISCV::FMAX_S_INX: |
| 7208 | case RISCV::FMINM_D: |
| 7209 | case RISCV::FMINM_H: |
| 7210 | case RISCV::FMINM_Q: |
| 7211 | case RISCV::FMINM_S: |
| 7212 | case RISCV::FMIN_D: |
| 7213 | case RISCV::FMIN_D_IN32X: |
| 7214 | case RISCV::FMIN_D_INX: |
| 7215 | case RISCV::FMIN_H: |
| 7216 | case RISCV::FMIN_H_INX: |
| 7217 | case RISCV::FMIN_Q: |
| 7218 | case RISCV::FMIN_S: |
| 7219 | case RISCV::FMIN_S_INX: |
| 7220 | case RISCV::FMVP_D_X: |
| 7221 | case RISCV::FMVP_Q_X: |
| 7222 | case RISCV::FSGNJN_D: |
| 7223 | case RISCV::FSGNJN_D_IN32X: |
| 7224 | case RISCV::FSGNJN_D_INX: |
| 7225 | case RISCV::FSGNJN_H: |
| 7226 | case RISCV::FSGNJN_H_INX: |
| 7227 | case RISCV::FSGNJN_Q: |
| 7228 | case RISCV::FSGNJN_S: |
| 7229 | case RISCV::FSGNJN_S_INX: |
| 7230 | case RISCV::FSGNJX_D: |
| 7231 | case RISCV::FSGNJX_D_IN32X: |
| 7232 | case RISCV::FSGNJX_D_INX: |
| 7233 | case RISCV::FSGNJX_H: |
| 7234 | case RISCV::FSGNJX_H_INX: |
| 7235 | case RISCV::FSGNJX_Q: |
| 7236 | case RISCV::FSGNJX_S: |
| 7237 | case RISCV::FSGNJX_S_INX: |
| 7238 | case RISCV::FSGNJ_D: |
| 7239 | case RISCV::FSGNJ_D_IN32X: |
| 7240 | case RISCV::FSGNJ_D_INX: |
| 7241 | case RISCV::FSGNJ_H: |
| 7242 | case RISCV::FSGNJ_H_INX: |
| 7243 | case RISCV::FSGNJ_Q: |
| 7244 | case RISCV::FSGNJ_S: |
| 7245 | case RISCV::FSGNJ_S_INX: |
| 7246 | case RISCV::MAX: |
| 7247 | case RISCV::MAXU: |
| 7248 | case RISCV::MIN: |
| 7249 | case RISCV::MINU: |
| 7250 | case RISCV::MOP_RR_0: |
| 7251 | case RISCV::MOP_RR_1: |
| 7252 | case RISCV::MOP_RR_2: |
| 7253 | case RISCV::MOP_RR_3: |
| 7254 | case RISCV::MOP_RR_4: |
| 7255 | case RISCV::MOP_RR_5: |
| 7256 | case RISCV::MOP_RR_6: |
| 7257 | case RISCV::MOP_RR_7: |
| 7258 | case RISCV::MSEQ: |
| 7259 | case RISCV::MSLT: |
| 7260 | case RISCV::MSLTU: |
| 7261 | case RISCV::MUL: |
| 7262 | case RISCV::MULH: |
| 7263 | case RISCV::MULHR: |
| 7264 | case RISCV::MULHRSU: |
| 7265 | case RISCV::MULHRU: |
| 7266 | case RISCV::MULHSU: |
| 7267 | case RISCV::MULHSU_H0: |
| 7268 | case RISCV::MULHSU_H1: |
| 7269 | case RISCV::MULHU: |
| 7270 | case RISCV::MULH_H0: |
| 7271 | case RISCV::MULH_H1: |
| 7272 | case RISCV::MULQ: |
| 7273 | case RISCV::MULQR: |
| 7274 | case RISCV::MULSU_H00: |
| 7275 | case RISCV::MULSU_H11: |
| 7276 | case RISCV::MULSU_W00: |
| 7277 | case RISCV::MULSU_W11: |
| 7278 | case RISCV::MULU_H00: |
| 7279 | case RISCV::MULU_H01: |
| 7280 | case RISCV::MULU_H11: |
| 7281 | case RISCV::MULU_W00: |
| 7282 | case RISCV::MULU_W01: |
| 7283 | case RISCV::MULU_W11: |
| 7284 | case RISCV::MULW: |
| 7285 | case RISCV::MUL_H00: |
| 7286 | case RISCV::MUL_H01: |
| 7287 | case RISCV::MUL_H11: |
| 7288 | case RISCV::MUL_W00: |
| 7289 | case RISCV::MUL_W01: |
| 7290 | case RISCV::MUL_W11: |
| 7291 | case RISCV::NDS_FFB: |
| 7292 | case RISCV::NDS_FFMISM: |
| 7293 | case RISCV::NDS_FFZMISM: |
| 7294 | case RISCV::NDS_FLMISM: |
| 7295 | case RISCV::OR: |
| 7296 | case RISCV::ORN: |
| 7297 | case RISCV::PAADDU_B: |
| 7298 | case RISCV::PAADDU_H: |
| 7299 | case RISCV::PAADDU_W: |
| 7300 | case RISCV::PAADD_B: |
| 7301 | case RISCV::PAADD_H: |
| 7302 | case RISCV::PAADD_W: |
| 7303 | case RISCV::PAAS_HX: |
| 7304 | case RISCV::PAAS_WX: |
| 7305 | case RISCV::PABDSUMU_B: |
| 7306 | case RISCV::PABDU_B: |
| 7307 | case RISCV::PABDU_H: |
| 7308 | case RISCV::PABD_B: |
| 7309 | case RISCV::PABD_H: |
| 7310 | case RISCV::PACK: |
| 7311 | case RISCV::PACKH: |
| 7312 | case RISCV::PACKW: |
| 7313 | case RISCV::PADD_B: |
| 7314 | case RISCV::PADD_BS: |
| 7315 | case RISCV::PADD_H: |
| 7316 | case RISCV::PADD_HS: |
| 7317 | case RISCV::PADD_W: |
| 7318 | case RISCV::PADD_WS: |
| 7319 | case RISCV::PASA_HX: |
| 7320 | case RISCV::PASA_WX: |
| 7321 | case RISCV::PASUBU_B: |
| 7322 | case RISCV::PASUBU_H: |
| 7323 | case RISCV::PASUBU_W: |
| 7324 | case RISCV::PASUB_B: |
| 7325 | case RISCV::PASUB_H: |
| 7326 | case RISCV::PASUB_W: |
| 7327 | case RISCV::PAS_HX: |
| 7328 | case RISCV::PAS_WX: |
| 7329 | case RISCV::PM2ADDSU_H: |
| 7330 | case RISCV::PM2ADDSU_W: |
| 7331 | case RISCV::PM2ADDU_H: |
| 7332 | case RISCV::PM2ADDU_W: |
| 7333 | case RISCV::PM2ADD_H: |
| 7334 | case RISCV::PM2ADD_HX: |
| 7335 | case RISCV::PM2ADD_W: |
| 7336 | case RISCV::PM2ADD_WX: |
| 7337 | case RISCV::PM2SADD_H: |
| 7338 | case RISCV::PM2SADD_HX: |
| 7339 | case RISCV::PM2SUB_H: |
| 7340 | case RISCV::PM2SUB_HX: |
| 7341 | case RISCV::PM2SUB_W: |
| 7342 | case RISCV::PM2SUB_WX: |
| 7343 | case RISCV::PM4ADDSU_B: |
| 7344 | case RISCV::PM4ADDSU_H: |
| 7345 | case RISCV::PM4ADDU_B: |
| 7346 | case RISCV::PM4ADDU_H: |
| 7347 | case RISCV::PM4ADD_B: |
| 7348 | case RISCV::PM4ADD_H: |
| 7349 | case RISCV::PMAXU_B: |
| 7350 | case RISCV::PMAXU_H: |
| 7351 | case RISCV::PMAXU_W: |
| 7352 | case RISCV::PMAX_B: |
| 7353 | case RISCV::PMAX_H: |
| 7354 | case RISCV::PMAX_W: |
| 7355 | case RISCV::PMINU_B: |
| 7356 | case RISCV::PMINU_H: |
| 7357 | case RISCV::PMINU_W: |
| 7358 | case RISCV::PMIN_B: |
| 7359 | case RISCV::PMIN_H: |
| 7360 | case RISCV::PMIN_W: |
| 7361 | case RISCV::PMQ2ADD_H: |
| 7362 | case RISCV::PMQ2ADD_W: |
| 7363 | case RISCV::PMQR2ADD_H: |
| 7364 | case RISCV::PMQR2ADD_W: |
| 7365 | case RISCV::PMSEQ_B: |
| 7366 | case RISCV::PMSEQ_H: |
| 7367 | case RISCV::PMSEQ_W: |
| 7368 | case RISCV::PMSLTU_B: |
| 7369 | case RISCV::PMSLTU_H: |
| 7370 | case RISCV::PMSLTU_W: |
| 7371 | case RISCV::PMSLT_B: |
| 7372 | case RISCV::PMSLT_H: |
| 7373 | case RISCV::PMSLT_W: |
| 7374 | case RISCV::PMULHRSU_H: |
| 7375 | case RISCV::PMULHRSU_W: |
| 7376 | case RISCV::PMULHRU_H: |
| 7377 | case RISCV::PMULHRU_W: |
| 7378 | case RISCV::PMULHR_H: |
| 7379 | case RISCV::PMULHR_W: |
| 7380 | case RISCV::PMULHSU_H: |
| 7381 | case RISCV::PMULHSU_H_B0: |
| 7382 | case RISCV::PMULHSU_H_B1: |
| 7383 | case RISCV::PMULHSU_W: |
| 7384 | case RISCV::PMULHSU_W_H0: |
| 7385 | case RISCV::PMULHSU_W_H1: |
| 7386 | case RISCV::PMULHU_H: |
| 7387 | case RISCV::PMULHU_W: |
| 7388 | case RISCV::PMULH_H: |
| 7389 | case RISCV::PMULH_H_B0: |
| 7390 | case RISCV::PMULH_H_B1: |
| 7391 | case RISCV::PMULH_W: |
| 7392 | case RISCV::PMULH_W_H0: |
| 7393 | case RISCV::PMULH_W_H1: |
| 7394 | case RISCV::PMULQR_H: |
| 7395 | case RISCV::PMULQR_W: |
| 7396 | case RISCV::PMULQ_H: |
| 7397 | case RISCV::PMULQ_W: |
| 7398 | case RISCV::PMULSU_H_B00: |
| 7399 | case RISCV::PMULSU_H_B11: |
| 7400 | case RISCV::PMULSU_W_H00: |
| 7401 | case RISCV::PMULSU_W_H11: |
| 7402 | case RISCV::PMULU_H_B00: |
| 7403 | case RISCV::PMULU_H_B01: |
| 7404 | case RISCV::PMULU_H_B11: |
| 7405 | case RISCV::PMULU_W_H00: |
| 7406 | case RISCV::PMULU_W_H01: |
| 7407 | case RISCV::PMULU_W_H11: |
| 7408 | case RISCV::PMUL_H_B00: |
| 7409 | case RISCV::PMUL_H_B01: |
| 7410 | case RISCV::PMUL_H_B11: |
| 7411 | case RISCV::PMUL_W_H00: |
| 7412 | case RISCV::PMUL_W_H01: |
| 7413 | case RISCV::PMUL_W_H11: |
| 7414 | case RISCV::PPAIREO_B: |
| 7415 | case RISCV::PPAIREO_H: |
| 7416 | case RISCV::PPAIREO_W: |
| 7417 | case RISCV::PPAIRE_B: |
| 7418 | case RISCV::PPAIRE_H: |
| 7419 | case RISCV::PPAIROE_B: |
| 7420 | case RISCV::PPAIROE_H: |
| 7421 | case RISCV::PPAIROE_W: |
| 7422 | case RISCV::PPAIRO_B: |
| 7423 | case RISCV::PPAIRO_H: |
| 7424 | case RISCV::PPAIRO_W: |
| 7425 | case RISCV::PREDSUMU_BS: |
| 7426 | case RISCV::PREDSUMU_HS: |
| 7427 | case RISCV::PREDSUMU_WS: |
| 7428 | case RISCV::PREDSUM_BS: |
| 7429 | case RISCV::PREDSUM_HS: |
| 7430 | case RISCV::PREDSUM_WS: |
| 7431 | case RISCV::PSADDU_B: |
| 7432 | case RISCV::PSADDU_H: |
| 7433 | case RISCV::PSADDU_W: |
| 7434 | case RISCV::PSADD_B: |
| 7435 | case RISCV::PSADD_H: |
| 7436 | case RISCV::PSADD_W: |
| 7437 | case RISCV::PSAS_HX: |
| 7438 | case RISCV::PSAS_WX: |
| 7439 | case RISCV::PSA_HX: |
| 7440 | case RISCV::PSA_WX: |
| 7441 | case RISCV::PSH1ADD_H: |
| 7442 | case RISCV::PSH1ADD_W: |
| 7443 | case RISCV::PSLL_BS: |
| 7444 | case RISCV::PSLL_HS: |
| 7445 | case RISCV::PSLL_WS: |
| 7446 | case RISCV::PSRA_BS: |
| 7447 | case RISCV::PSRA_HS: |
| 7448 | case RISCV::PSRA_WS: |
| 7449 | case RISCV::PSRL_BS: |
| 7450 | case RISCV::PSRL_HS: |
| 7451 | case RISCV::PSRL_WS: |
| 7452 | case RISCV::PSSA_HX: |
| 7453 | case RISCV::PSSA_WX: |
| 7454 | case RISCV::PSSH1SADD_H: |
| 7455 | case RISCV::PSSH1SADD_W: |
| 7456 | case RISCV::PSSHAR_HS: |
| 7457 | case RISCV::PSSHAR_WS: |
| 7458 | case RISCV::PSSHA_HS: |
| 7459 | case RISCV::PSSHA_WS: |
| 7460 | case RISCV::PSSUBU_B: |
| 7461 | case RISCV::PSSUBU_H: |
| 7462 | case RISCV::PSSUBU_W: |
| 7463 | case RISCV::PSSUB_B: |
| 7464 | case RISCV::PSSUB_H: |
| 7465 | case RISCV::PSSUB_W: |
| 7466 | case RISCV::PSUB_B: |
| 7467 | case RISCV::PSUB_H: |
| 7468 | case RISCV::PSUB_W: |
| 7469 | case RISCV::QC_ADDSAT: |
| 7470 | case RISCV::QC_ADDUSAT: |
| 7471 | case RISCV::QC_CSRRWR: |
| 7472 | case RISCV::QC_EXTDPR: |
| 7473 | case RISCV::QC_EXTDPRH: |
| 7474 | case RISCV::QC_EXTDR: |
| 7475 | case RISCV::QC_EXTDUPR: |
| 7476 | case RISCV::QC_EXTDUPRH: |
| 7477 | case RISCV::QC_EXTDUR: |
| 7478 | case RISCV::QC_SHLSAT: |
| 7479 | case RISCV::QC_SHLUSAT: |
| 7480 | case RISCV::QC_SUBSAT: |
| 7481 | case RISCV::QC_SUBUSAT: |
| 7482 | case RISCV::QC_WRAP: |
| 7483 | case RISCV::REM: |
| 7484 | case RISCV::REMU: |
| 7485 | case RISCV::REMUW: |
| 7486 | case RISCV::REMW: |
| 7487 | case RISCV::ROL: |
| 7488 | case RISCV::ROLW: |
| 7489 | case RISCV::ROR: |
| 7490 | case RISCV::RORW: |
| 7491 | case RISCV::SADD: |
| 7492 | case RISCV::SADDU: |
| 7493 | case RISCV::SH1ADD: |
| 7494 | case RISCV::SH1ADD_UW: |
| 7495 | case RISCV::SH2ADD: |
| 7496 | case RISCV::SH2ADD_UW: |
| 7497 | case RISCV::SH3ADD: |
| 7498 | case RISCV::SH3ADD_UW: |
| 7499 | case RISCV::SHA: |
| 7500 | case RISCV::SHA512SIG0H: |
| 7501 | case RISCV::SHA512SIG0L: |
| 7502 | case RISCV::SHA512SIG1H: |
| 7503 | case RISCV::SHA512SIG1L: |
| 7504 | case RISCV::SHA512SUM0R: |
| 7505 | case RISCV::SHA512SUM1R: |
| 7506 | case RISCV::SHAR: |
| 7507 | case RISCV::SLL: |
| 7508 | case RISCV::SLLW: |
| 7509 | case RISCV::SLT: |
| 7510 | case RISCV::SLTU: |
| 7511 | case RISCV::SRA: |
| 7512 | case RISCV::SRAW: |
| 7513 | case RISCV::SRL: |
| 7514 | case RISCV::SRLW: |
| 7515 | case RISCV::SSH1SADD: |
| 7516 | case RISCV::SSHA: |
| 7517 | case RISCV::SSHAR: |
| 7518 | case RISCV::SSUB: |
| 7519 | case RISCV::SSUBU: |
| 7520 | case RISCV::SUB: |
| 7521 | case RISCV::SUBW: |
| 7522 | case RISCV::UNZIP16HP: |
| 7523 | case RISCV::UNZIP16P: |
| 7524 | case RISCV::UNZIP8HP: |
| 7525 | case RISCV::UNZIP8P: |
| 7526 | case RISCV::VSETVL: |
| 7527 | case RISCV::VT_MASKC: |
| 7528 | case RISCV::VT_MASKCN: |
| 7529 | case RISCV::XNOR: |
| 7530 | case RISCV::XOR: |
| 7531 | case RISCV::XPERM4: |
| 7532 | case RISCV::XPERM8: |
| 7533 | case RISCV::ZIP16HP: |
| 7534 | case RISCV::ZIP16P: |
| 7535 | case RISCV::ZIP8HP: |
| 7536 | case RISCV::ZIP8P: { |
| 7537 | // op: rs2 |
| 7538 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7539 | Value |= (op & 0x1f) << 20; |
| 7540 | // op: rs1 |
| 7541 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7542 | Value |= (op & 0x1f) << 15; |
| 7543 | // op: rd |
| 7544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7545 | Value |= (op & 0x1f) << 7; |
| 7546 | break; |
| 7547 | } |
| 7548 | case RISCV::AES32DSI: |
| 7549 | case RISCV::AES32DSMI: |
| 7550 | case RISCV::AES32ESI: |
| 7551 | case RISCV::AES32ESMI: |
| 7552 | case RISCV::SM4ED: |
| 7553 | case RISCV::SM4KS: { |
| 7554 | // op: rs2 |
| 7555 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7556 | Value |= (op & 0x1f) << 20; |
| 7557 | // op: rs1 |
| 7558 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7559 | Value |= (op & 0x1f) << 15; |
| 7560 | // op: rd |
| 7561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7562 | Value |= (op & 0x1f) << 7; |
| 7563 | // op: bs |
| 7564 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7565 | Value |= (op & 0x3) << 30; |
| 7566 | break; |
| 7567 | } |
| 7568 | case RISCV::QC_LWM: |
| 7569 | case RISCV::QC_LWMI: |
| 7570 | case RISCV::QC_SETWM: |
| 7571 | case RISCV::QC_SETWMI: |
| 7572 | case RISCV::QC_SWM: |
| 7573 | case RISCV::QC_SWMI: { |
| 7574 | // op: rs2 |
| 7575 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7576 | Value |= (op & 0x1f) << 20; |
| 7577 | // op: rs1 |
| 7578 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7579 | Value |= (op & 0x1f) << 15; |
| 7580 | // op: rd |
| 7581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7582 | Value |= (op & 0x1f) << 7; |
| 7583 | // op: imm |
| 7584 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 7585 | Value |= (op & 0x7c) << 23; |
| 7586 | break; |
| 7587 | } |
| 7588 | case RISCV::CV_ADDN: |
| 7589 | case RISCV::CV_ADDRN: |
| 7590 | case RISCV::CV_ADDUN: |
| 7591 | case RISCV::CV_ADDURN: |
| 7592 | case RISCV::CV_MULHHSN: |
| 7593 | case RISCV::CV_MULHHSRN: |
| 7594 | case RISCV::CV_MULHHUN: |
| 7595 | case RISCV::CV_MULHHURN: |
| 7596 | case RISCV::CV_MULSN: |
| 7597 | case RISCV::CV_MULSRN: |
| 7598 | case RISCV::CV_MULUN: |
| 7599 | case RISCV::CV_MULURN: |
| 7600 | case RISCV::CV_SUBN: |
| 7601 | case RISCV::CV_SUBRN: |
| 7602 | case RISCV::CV_SUBUN: |
| 7603 | case RISCV::CV_SUBURN: { |
| 7604 | // op: rs2 |
| 7605 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7606 | Value |= (op & 0x1f) << 20; |
| 7607 | // op: rs1 |
| 7608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7609 | Value |= (op & 0x1f) << 15; |
| 7610 | // op: rd |
| 7611 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7612 | Value |= (op & 0x1f) << 7; |
| 7613 | // op: imm5 |
| 7614 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 7615 | Value |= (op & 0x1f) << 25; |
| 7616 | break; |
| 7617 | } |
| 7618 | case RISCV::QC_LRB: |
| 7619 | case RISCV::QC_LRBU: |
| 7620 | case RISCV::QC_LRH: |
| 7621 | case RISCV::QC_LRHU: |
| 7622 | case RISCV::QC_LRW: |
| 7623 | case RISCV::QC_SRB: |
| 7624 | case RISCV::QC_SRH: |
| 7625 | case RISCV::QC_SRW: { |
| 7626 | // op: rs2 |
| 7627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7628 | Value |= (op & 0x1f) << 20; |
| 7629 | // op: rs1 |
| 7630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7631 | Value |= (op & 0x1f) << 15; |
| 7632 | // op: rd |
| 7633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7634 | Value |= (op & 0x1f) << 7; |
| 7635 | // op: shamt |
| 7636 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 7637 | Value |= (op & 0x7) << 25; |
| 7638 | break; |
| 7639 | } |
| 7640 | case RISCV::QC_SHLADD: { |
| 7641 | // op: rs2 |
| 7642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7643 | Value |= (op & 0x1f) << 20; |
| 7644 | // op: rs1 |
| 7645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7646 | Value |= (op & 0x1f) << 15; |
| 7647 | // op: rd |
| 7648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7649 | Value |= (op & 0x1f) << 7; |
| 7650 | // op: shamt |
| 7651 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7652 | Value |= (op & 0x1f) << 25; |
| 7653 | break; |
| 7654 | } |
| 7655 | case RISCV::TH_ADDSL: |
| 7656 | case RISCV::TH_FLRD: |
| 7657 | case RISCV::TH_FLRW: |
| 7658 | case RISCV::TH_FLURD: |
| 7659 | case RISCV::TH_FLURW: |
| 7660 | case RISCV::TH_FSRD: |
| 7661 | case RISCV::TH_FSRW: |
| 7662 | case RISCV::TH_FSURD: |
| 7663 | case RISCV::TH_FSURW: |
| 7664 | case RISCV::TH_LRB: |
| 7665 | case RISCV::TH_LRBU: |
| 7666 | case RISCV::TH_LRD: |
| 7667 | case RISCV::TH_LRH: |
| 7668 | case RISCV::TH_LRHU: |
| 7669 | case RISCV::TH_LRW: |
| 7670 | case RISCV::TH_LRWU: |
| 7671 | case RISCV::TH_LURB: |
| 7672 | case RISCV::TH_LURBU: |
| 7673 | case RISCV::TH_LURD: |
| 7674 | case RISCV::TH_LURH: |
| 7675 | case RISCV::TH_LURHU: |
| 7676 | case RISCV::TH_LURW: |
| 7677 | case RISCV::TH_LURWU: |
| 7678 | case RISCV::TH_SRB: |
| 7679 | case RISCV::TH_SRD: |
| 7680 | case RISCV::TH_SRH: |
| 7681 | case RISCV::TH_SRW: |
| 7682 | case RISCV::TH_SURB: |
| 7683 | case RISCV::TH_SURD: |
| 7684 | case RISCV::TH_SURH: |
| 7685 | case RISCV::TH_SURW: { |
| 7686 | // op: rs2 |
| 7687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7688 | Value |= (op & 0x1f) << 20; |
| 7689 | // op: rs1 |
| 7690 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7691 | Value |= (op & 0x1f) << 15; |
| 7692 | // op: rd |
| 7693 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7694 | Value |= (op & 0x1f) << 7; |
| 7695 | // op: uimm2 |
| 7696 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 7697 | Value |= (op & 0x3) << 25; |
| 7698 | break; |
| 7699 | } |
| 7700 | case RISCV::AMOCAS_B: |
| 7701 | case RISCV::AMOCAS_B_AQ: |
| 7702 | case RISCV::AMOCAS_B_AQRL: |
| 7703 | case RISCV::AMOCAS_B_RL: |
| 7704 | case RISCV::AMOCAS_D_RV32: |
| 7705 | case RISCV::AMOCAS_D_RV32_AQ: |
| 7706 | case RISCV::AMOCAS_D_RV32_AQRL: |
| 7707 | case RISCV::AMOCAS_D_RV32_RL: |
| 7708 | case RISCV::AMOCAS_D_RV64: |
| 7709 | case RISCV::AMOCAS_D_RV64_AQ: |
| 7710 | case RISCV::AMOCAS_D_RV64_AQRL: |
| 7711 | case RISCV::AMOCAS_D_RV64_RL: |
| 7712 | case RISCV::AMOCAS_H: |
| 7713 | case RISCV::AMOCAS_H_AQ: |
| 7714 | case RISCV::AMOCAS_H_AQRL: |
| 7715 | case RISCV::AMOCAS_H_RL: |
| 7716 | case RISCV::AMOCAS_Q: |
| 7717 | case RISCV::AMOCAS_Q_AQ: |
| 7718 | case RISCV::AMOCAS_Q_AQRL: |
| 7719 | case RISCV::AMOCAS_Q_RL: |
| 7720 | case RISCV::AMOCAS_W: |
| 7721 | case RISCV::AMOCAS_W_AQ: |
| 7722 | case RISCV::AMOCAS_W_AQRL: |
| 7723 | case RISCV::AMOCAS_W_RL: { |
| 7724 | // op: rs2 |
| 7725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7726 | Value |= (op & 0x1f) << 20; |
| 7727 | // op: rs1 |
| 7728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7729 | Value |= (op & 0x1f) << 15; |
| 7730 | // op: rd |
| 7731 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7732 | Value |= (op & 0x1f) << 7; |
| 7733 | break; |
| 7734 | } |
| 7735 | case RISCV::AIF_MASKAND: |
| 7736 | case RISCV::AIF_MASKOR: |
| 7737 | case RISCV::AIF_MASKXOR: { |
| 7738 | // op: rs2 |
| 7739 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7740 | Value |= (op & 0x7) << 20; |
| 7741 | // op: rs1 |
| 7742 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7743 | Value |= (op & 0x7) << 15; |
| 7744 | // op: rd |
| 7745 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7746 | Value |= (op & 0x7) << 7; |
| 7747 | break; |
| 7748 | } |
| 7749 | case RISCV::C_ADDW: |
| 7750 | case RISCV::C_AND: |
| 7751 | case RISCV::C_MUL: |
| 7752 | case RISCV::C_OR: |
| 7753 | case RISCV::C_SUB: |
| 7754 | case RISCV::C_SUBW: |
| 7755 | case RISCV::C_XOR: { |
| 7756 | // op: rs2 |
| 7757 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7758 | Value |= (op & 0x7) << 2; |
| 7759 | // op: rd |
| 7760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7761 | Value |= (op & 0x7) << 7; |
| 7762 | break; |
| 7763 | } |
| 7764 | case RISCV::QC_SELECTIEQI: |
| 7765 | case RISCV::QC_SELECTINEI: { |
| 7766 | // op: rs2 |
| 7767 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7768 | Value |= (op & 0x1f) << 20; |
| 7769 | // op: rd |
| 7770 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7771 | Value |= (op & 0x1f) << 7; |
| 7772 | // op: imm |
| 7773 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 7774 | Value |= (op & 0x1f) << 15; |
| 7775 | // op: simm2 |
| 7776 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 7777 | Value |= (op & 0x1f) << 27; |
| 7778 | break; |
| 7779 | } |
| 7780 | case RISCV::CV_LBU_rr_inc: |
| 7781 | case RISCV::CV_LB_rr_inc: |
| 7782 | case RISCV::CV_LHU_rr_inc: |
| 7783 | case RISCV::CV_LH_rr_inc: |
| 7784 | case RISCV::CV_LW_rr_inc: { |
| 7785 | // op: rs2 |
| 7786 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7787 | Value |= (op & 0x1f) << 20; |
| 7788 | // op: rs1 |
| 7789 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7790 | Value |= (op & 0x1f) << 15; |
| 7791 | // op: rd |
| 7792 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7793 | Value |= (op & 0x1f) << 7; |
| 7794 | break; |
| 7795 | } |
| 7796 | case RISCV::MQRWACC: |
| 7797 | case RISCV::MQWACC: |
| 7798 | case RISCV::PM2WADDASU_H: |
| 7799 | case RISCV::PM2WADDAU_H: |
| 7800 | case RISCV::PM2WADDA_H: |
| 7801 | case RISCV::PM2WADDA_HX: |
| 7802 | case RISCV::PM2WSUBA_H: |
| 7803 | case RISCV::PM2WSUBA_HX: |
| 7804 | case RISCV::PMQRWACC_H: |
| 7805 | case RISCV::PMQWACC_H: |
| 7806 | case RISCV::PWADDAU_B: |
| 7807 | case RISCV::PWADDAU_H: |
| 7808 | case RISCV::PWADDA_B: |
| 7809 | case RISCV::PWADDA_H: |
| 7810 | case RISCV::PWMACCSU_H: |
| 7811 | case RISCV::PWMACCU_H: |
| 7812 | case RISCV::PWMACC_H: |
| 7813 | case RISCV::PWSUBAU_B: |
| 7814 | case RISCV::PWSUBAU_H: |
| 7815 | case RISCV::PWSUBA_B: |
| 7816 | case RISCV::PWSUBA_H: |
| 7817 | case RISCV::WADDA: |
| 7818 | case RISCV::WADDAU: |
| 7819 | case RISCV::WMACC: |
| 7820 | case RISCV::WMACCSU: |
| 7821 | case RISCV::WMACCU: |
| 7822 | case RISCV::WSUBA: |
| 7823 | case RISCV::WSUBAU: { |
| 7824 | // op: rs2 |
| 7825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7826 | Value |= (op & 0x1f) << 20; |
| 7827 | // op: rs1 |
| 7828 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7829 | Value |= (op & 0x1f) << 15; |
| 7830 | // op: rd |
| 7831 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7832 | Value |= (op & 0x1e) << 7; |
| 7833 | break; |
| 7834 | } |
| 7835 | case RISCV::CV_ADDNR: |
| 7836 | case RISCV::CV_ADDRNR: |
| 7837 | case RISCV::CV_ADDUNR: |
| 7838 | case RISCV::CV_ADDURNR: |
| 7839 | case RISCV::CV_CPLXMUL_I: |
| 7840 | case RISCV::CV_CPLXMUL_I_DIV2: |
| 7841 | case RISCV::CV_CPLXMUL_I_DIV4: |
| 7842 | case RISCV::CV_CPLXMUL_I_DIV8: |
| 7843 | case RISCV::CV_CPLXMUL_R: |
| 7844 | case RISCV::CV_CPLXMUL_R_DIV2: |
| 7845 | case RISCV::CV_CPLXMUL_R_DIV4: |
| 7846 | case RISCV::CV_CPLXMUL_R_DIV8: |
| 7847 | case RISCV::CV_INSERTR: |
| 7848 | case RISCV::CV_MAC: |
| 7849 | case RISCV::CV_MSU: |
| 7850 | case RISCV::CV_PACKHI_B: |
| 7851 | case RISCV::CV_PACKLO_B: |
| 7852 | case RISCV::CV_SDOTSP_B: |
| 7853 | case RISCV::CV_SDOTSP_H: |
| 7854 | case RISCV::CV_SDOTSP_SC_B: |
| 7855 | case RISCV::CV_SDOTSP_SC_H: |
| 7856 | case RISCV::CV_SDOTUP_B: |
| 7857 | case RISCV::CV_SDOTUP_H: |
| 7858 | case RISCV::CV_SDOTUP_SC_B: |
| 7859 | case RISCV::CV_SDOTUP_SC_H: |
| 7860 | case RISCV::CV_SDOTUSP_B: |
| 7861 | case RISCV::CV_SDOTUSP_H: |
| 7862 | case RISCV::CV_SDOTUSP_SC_B: |
| 7863 | case RISCV::CV_SDOTUSP_SC_H: |
| 7864 | case RISCV::CV_SHUFFLE2_B: |
| 7865 | case RISCV::CV_SHUFFLE2_H: |
| 7866 | case RISCV::CV_SUBNR: |
| 7867 | case RISCV::CV_SUBRNR: |
| 7868 | case RISCV::CV_SUBUNR: |
| 7869 | case RISCV::CV_SUBURNR: |
| 7870 | case RISCV::MACCSU_H00: |
| 7871 | case RISCV::MACCSU_H11: |
| 7872 | case RISCV::MACCSU_W00: |
| 7873 | case RISCV::MACCSU_W11: |
| 7874 | case RISCV::MACCU_H00: |
| 7875 | case RISCV::MACCU_H01: |
| 7876 | case RISCV::MACCU_H11: |
| 7877 | case RISCV::MACCU_W00: |
| 7878 | case RISCV::MACCU_W01: |
| 7879 | case RISCV::MACCU_W11: |
| 7880 | case RISCV::MACC_H00: |
| 7881 | case RISCV::MACC_H01: |
| 7882 | case RISCV::MACC_H11: |
| 7883 | case RISCV::MACC_W00: |
| 7884 | case RISCV::MACC_W01: |
| 7885 | case RISCV::MACC_W11: |
| 7886 | case RISCV::MERGE: |
| 7887 | case RISCV::MHACC: |
| 7888 | case RISCV::MHACCSU: |
| 7889 | case RISCV::MHACCSU_H0: |
| 7890 | case RISCV::MHACCSU_H1: |
| 7891 | case RISCV::MHACCU: |
| 7892 | case RISCV::MHACC_H0: |
| 7893 | case RISCV::MHACC_H1: |
| 7894 | case RISCV::MHRACC: |
| 7895 | case RISCV::MHRACCSU: |
| 7896 | case RISCV::MHRACCU: |
| 7897 | case RISCV::MQACC_H00: |
| 7898 | case RISCV::MQACC_H01: |
| 7899 | case RISCV::MQACC_H11: |
| 7900 | case RISCV::MQACC_W00: |
| 7901 | case RISCV::MQACC_W01: |
| 7902 | case RISCV::MQACC_W11: |
| 7903 | case RISCV::MQRACC_H00: |
| 7904 | case RISCV::MQRACC_H01: |
| 7905 | case RISCV::MQRACC_H11: |
| 7906 | case RISCV::MQRACC_W00: |
| 7907 | case RISCV::MQRACC_W01: |
| 7908 | case RISCV::MQRACC_W11: |
| 7909 | case RISCV::MVM: |
| 7910 | case RISCV::MVMN: |
| 7911 | case RISCV::PABDSUMAU_B: |
| 7912 | case RISCV::PM2ADDASU_H: |
| 7913 | case RISCV::PM2ADDASU_W: |
| 7914 | case RISCV::PM2ADDAU_H: |
| 7915 | case RISCV::PM2ADDAU_W: |
| 7916 | case RISCV::PM2ADDA_H: |
| 7917 | case RISCV::PM2ADDA_HX: |
| 7918 | case RISCV::PM2ADDA_W: |
| 7919 | case RISCV::PM2ADDA_WX: |
| 7920 | case RISCV::PM2SUBA_H: |
| 7921 | case RISCV::PM2SUBA_HX: |
| 7922 | case RISCV::PM2SUBA_W: |
| 7923 | case RISCV::PM2SUBA_WX: |
| 7924 | case RISCV::PM4ADDASU_B: |
| 7925 | case RISCV::PM4ADDASU_H: |
| 7926 | case RISCV::PM4ADDAU_B: |
| 7927 | case RISCV::PM4ADDAU_H: |
| 7928 | case RISCV::PM4ADDA_B: |
| 7929 | case RISCV::PM4ADDA_H: |
| 7930 | case RISCV::PMACCSU_W_H00: |
| 7931 | case RISCV::PMACCSU_W_H11: |
| 7932 | case RISCV::PMACCU_W_H00: |
| 7933 | case RISCV::PMACCU_W_H01: |
| 7934 | case RISCV::PMACCU_W_H11: |
| 7935 | case RISCV::PMACC_W_H00: |
| 7936 | case RISCV::PMACC_W_H01: |
| 7937 | case RISCV::PMACC_W_H11: |
| 7938 | case RISCV::PMHACCSU_H: |
| 7939 | case RISCV::PMHACCSU_H_B0: |
| 7940 | case RISCV::PMHACCSU_H_B1: |
| 7941 | case RISCV::PMHACCSU_W: |
| 7942 | case RISCV::PMHACCSU_W_H0: |
| 7943 | case RISCV::PMHACCSU_W_H1: |
| 7944 | case RISCV::PMHACCU_H: |
| 7945 | case RISCV::PMHACCU_W: |
| 7946 | case RISCV::PMHACC_H: |
| 7947 | case RISCV::PMHACC_H_B0: |
| 7948 | case RISCV::PMHACC_H_B1: |
| 7949 | case RISCV::PMHACC_W: |
| 7950 | case RISCV::PMHACC_W_H0: |
| 7951 | case RISCV::PMHACC_W_H1: |
| 7952 | case RISCV::PMHRACCSU_H: |
| 7953 | case RISCV::PMHRACCSU_W: |
| 7954 | case RISCV::PMHRACCU_H: |
| 7955 | case RISCV::PMHRACCU_W: |
| 7956 | case RISCV::PMHRACC_H: |
| 7957 | case RISCV::PMHRACC_W: |
| 7958 | case RISCV::PMQ2ADDA_H: |
| 7959 | case RISCV::PMQ2ADDA_W: |
| 7960 | case RISCV::PMQACC_W_H00: |
| 7961 | case RISCV::PMQACC_W_H01: |
| 7962 | case RISCV::PMQACC_W_H11: |
| 7963 | case RISCV::PMQR2ADDA_H: |
| 7964 | case RISCV::PMQR2ADDA_W: |
| 7965 | case RISCV::PMQRACC_W_H00: |
| 7966 | case RISCV::PMQRACC_W_H01: |
| 7967 | case RISCV::PMQRACC_W_H11: |
| 7968 | case RISCV::QC_INSBHR: |
| 7969 | case RISCV::QC_INSBPR: |
| 7970 | case RISCV::QC_INSBPRH: |
| 7971 | case RISCV::QC_INSBR: |
| 7972 | case RISCV::SLX: |
| 7973 | case RISCV::SRX: |
| 7974 | case RISCV::TH_MULA: |
| 7975 | case RISCV::TH_MULAH: |
| 7976 | case RISCV::TH_MULAW: |
| 7977 | case RISCV::TH_MULS: |
| 7978 | case RISCV::TH_MULSH: |
| 7979 | case RISCV::TH_MULSW: |
| 7980 | case RISCV::TH_MVEQZ: |
| 7981 | case RISCV::TH_MVNEZ: { |
| 7982 | // op: rs2 |
| 7983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7984 | Value |= (op & 0x1f) << 20; |
| 7985 | // op: rs1 |
| 7986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7987 | Value |= (op & 0x1f) << 15; |
| 7988 | // op: rd |
| 7989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7990 | Value |= (op & 0x1f) << 7; |
| 7991 | break; |
| 7992 | } |
| 7993 | case RISCV::CV_MACHHSN: |
| 7994 | case RISCV::CV_MACHHSRN: |
| 7995 | case RISCV::CV_MACHHUN: |
| 7996 | case RISCV::CV_MACHHURN: |
| 7997 | case RISCV::CV_MACSN: |
| 7998 | case RISCV::CV_MACSRN: |
| 7999 | case RISCV::CV_MACUN: |
| 8000 | case RISCV::CV_MACURN: { |
| 8001 | // op: rs2 |
| 8002 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8003 | Value |= (op & 0x1f) << 20; |
| 8004 | // op: rs1 |
| 8005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8006 | Value |= (op & 0x1f) << 15; |
| 8007 | // op: rd |
| 8008 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8009 | Value |= (op & 0x1f) << 7; |
| 8010 | // op: imm5 |
| 8011 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 8012 | Value |= (op & 0x1f) << 25; |
| 8013 | break; |
| 8014 | } |
| 8015 | case RISCV::QC_LIEQ: |
| 8016 | case RISCV::QC_LIGE: |
| 8017 | case RISCV::QC_LIGEU: |
| 8018 | case RISCV::QC_LILT: |
| 8019 | case RISCV::QC_LILTU: |
| 8020 | case RISCV::QC_LINE: { |
| 8021 | // op: rs2 |
| 8022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8023 | Value |= (op & 0x1f) << 20; |
| 8024 | // op: rs1 |
| 8025 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8026 | Value |= (op & 0x1f) << 15; |
| 8027 | // op: rd |
| 8028 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8029 | Value |= (op & 0x1f) << 7; |
| 8030 | // op: simm |
| 8031 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 8032 | Value |= (op & 0x1f) << 27; |
| 8033 | break; |
| 8034 | } |
| 8035 | case RISCV::QC_SELECTIEQ: |
| 8036 | case RISCV::QC_SELECTINE: { |
| 8037 | // op: rs2 |
| 8038 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8039 | Value |= (op & 0x1f) << 20; |
| 8040 | // op: rs1 |
| 8041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8042 | Value |= (op & 0x1f) << 15; |
| 8043 | // op: rd |
| 8044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8045 | Value |= (op & 0x1f) << 7; |
| 8046 | // op: simm2 |
| 8047 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 8048 | Value |= (op & 0x1f) << 27; |
| 8049 | break; |
| 8050 | } |
| 8051 | case RISCV::FMADD_D: |
| 8052 | case RISCV::FMADD_D_IN32X: |
| 8053 | case RISCV::FMADD_D_INX: |
| 8054 | case RISCV::FMADD_H: |
| 8055 | case RISCV::FMADD_H_INX: |
| 8056 | case RISCV::FMADD_Q: |
| 8057 | case RISCV::FMADD_S: |
| 8058 | case RISCV::FMADD_S_INX: |
| 8059 | case RISCV::FMSUB_D: |
| 8060 | case RISCV::FMSUB_D_IN32X: |
| 8061 | case RISCV::FMSUB_D_INX: |
| 8062 | case RISCV::FMSUB_H: |
| 8063 | case RISCV::FMSUB_H_INX: |
| 8064 | case RISCV::FMSUB_Q: |
| 8065 | case RISCV::FMSUB_S: |
| 8066 | case RISCV::FMSUB_S_INX: |
| 8067 | case RISCV::FNMADD_D: |
| 8068 | case RISCV::FNMADD_D_IN32X: |
| 8069 | case RISCV::FNMADD_D_INX: |
| 8070 | case RISCV::FNMADD_H: |
| 8071 | case RISCV::FNMADD_H_INX: |
| 8072 | case RISCV::FNMADD_Q: |
| 8073 | case RISCV::FNMADD_S: |
| 8074 | case RISCV::FNMADD_S_INX: |
| 8075 | case RISCV::FNMSUB_D: |
| 8076 | case RISCV::FNMSUB_D_IN32X: |
| 8077 | case RISCV::FNMSUB_D_INX: |
| 8078 | case RISCV::FNMSUB_H: |
| 8079 | case RISCV::FNMSUB_H_INX: |
| 8080 | case RISCV::FNMSUB_Q: |
| 8081 | case RISCV::FNMSUB_S: |
| 8082 | case RISCV::FNMSUB_S_INX: { |
| 8083 | // op: rs3 |
| 8084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8085 | Value |= (op & 0x1f) << 27; |
| 8086 | // op: rs2 |
| 8087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8088 | Value |= (op & 0x1f) << 20; |
| 8089 | // op: rs1 |
| 8090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8091 | Value |= (op & 0x1f) << 15; |
| 8092 | // op: frm |
| 8093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8094 | Value |= (op & 0x7) << 12; |
| 8095 | // op: rd |
| 8096 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8097 | Value |= (op & 0x1f) << 7; |
| 8098 | break; |
| 8099 | } |
| 8100 | case RISCV::MIPS_CCMOV: { |
| 8101 | // op: rs3 |
| 8102 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8103 | Value |= (op & 0x1f) << 27; |
| 8104 | // op: rs2 |
| 8105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8106 | Value |= (op & 0x1f) << 20; |
| 8107 | // op: rs1 |
| 8108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8109 | Value |= (op & 0x1f) << 15; |
| 8110 | // op: rd |
| 8111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8112 | Value |= (op & 0x1f) << 7; |
| 8113 | break; |
| 8114 | } |
| 8115 | case RISCV::CV_SB_rr_inc: |
| 8116 | case RISCV::CV_SH_rr_inc: |
| 8117 | case RISCV::CV_SW_rr_inc: { |
| 8118 | // op: rs3 |
| 8119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8120 | Value |= (op & 0x1f) << 7; |
| 8121 | // op: rs2 |
| 8122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8123 | Value |= (op & 0x1f) << 20; |
| 8124 | // op: rs1 |
| 8125 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8126 | Value |= (op & 0x1f) << 15; |
| 8127 | break; |
| 8128 | } |
| 8129 | case RISCV::QC_MVEQI: |
| 8130 | case RISCV::QC_MVGEI: |
| 8131 | case RISCV::QC_MVGEUI: |
| 8132 | case RISCV::QC_MVLTI: |
| 8133 | case RISCV::QC_MVLTUI: |
| 8134 | case RISCV::QC_MVNEI: { |
| 8135 | // op: rs3 |
| 8136 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8137 | Value |= (op & 0x1f) << 27; |
| 8138 | // op: rs1 |
| 8139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8140 | Value |= (op & 0x1f) << 15; |
| 8141 | // op: rd |
| 8142 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8143 | Value |= (op & 0x1f) << 7; |
| 8144 | // op: imm |
| 8145 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 8146 | Value |= (op & 0x1f) << 20; |
| 8147 | break; |
| 8148 | } |
| 8149 | case RISCV::QC_SELECTEQI: |
| 8150 | case RISCV::QC_SELECTNEI: { |
| 8151 | // op: rs3 |
| 8152 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8153 | Value |= (op & 0x1f) << 27; |
| 8154 | // op: rs2 |
| 8155 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8156 | Value |= (op & 0x1f) << 20; |
| 8157 | // op: rd |
| 8158 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8159 | Value |= (op & 0x1f) << 7; |
| 8160 | // op: imm |
| 8161 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 8162 | Value |= (op & 0x1f) << 15; |
| 8163 | break; |
| 8164 | } |
| 8165 | case RISCV::QC_MVEQ: |
| 8166 | case RISCV::QC_MVGE: |
| 8167 | case RISCV::QC_MVGEU: |
| 8168 | case RISCV::QC_MVLT: |
| 8169 | case RISCV::QC_MVLTU: |
| 8170 | case RISCV::QC_MVNE: { |
| 8171 | // op: rs3 |
| 8172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8173 | Value |= (op & 0x1f) << 27; |
| 8174 | // op: rs2 |
| 8175 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8176 | Value |= (op & 0x1f) << 20; |
| 8177 | // op: rs1 |
| 8178 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8179 | Value |= (op & 0x1f) << 15; |
| 8180 | // op: rd |
| 8181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8182 | Value |= (op & 0x1f) << 7; |
| 8183 | break; |
| 8184 | } |
| 8185 | case RISCV::QC_C_SYNC: |
| 8186 | case RISCV::QC_C_SYNCR: |
| 8187 | case RISCV::QC_C_SYNCWF: |
| 8188 | case RISCV::QC_C_SYNCWL: { |
| 8189 | // op: slist |
| 8190 | op = getImmOpValueSlist(MI, OpNo: 0, Fixups, STI); |
| 8191 | Value |= (op & 0x7) << 7; |
| 8192 | break; |
| 8193 | } |
| 8194 | case RISCV::Insn16: { |
| 8195 | // op: value |
| 8196 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 8197 | Value |= (op & 0xffff); |
| 8198 | break; |
| 8199 | } |
| 8200 | case RISCV::Insn32: { |
| 8201 | // op: value |
| 8202 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 8203 | Value |= (op & 0xffffffff); |
| 8204 | break; |
| 8205 | } |
| 8206 | case RISCV::Insn48: { |
| 8207 | // op: value |
| 8208 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 8209 | Value |= (op & 0xffffffffffff); |
| 8210 | break; |
| 8211 | } |
| 8212 | case RISCV::Insn64: { |
| 8213 | // op: value |
| 8214 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 8215 | Value |= (op & 0xffffffffffffffff); |
| 8216 | break; |
| 8217 | } |
| 8218 | case RISCV::RI_VZERO: { |
| 8219 | // op: vd |
| 8220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8221 | Value |= (op & 0x1f) << 7; |
| 8222 | break; |
| 8223 | } |
| 8224 | case RISCV::VMV_V_I: { |
| 8225 | // op: vd |
| 8226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8227 | Value |= (op & 0x1f) << 7; |
| 8228 | // op: imm |
| 8229 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 8230 | Value |= (op & 0x1f) << 15; |
| 8231 | break; |
| 8232 | } |
| 8233 | case RISCV::VFMV_V_F: |
| 8234 | case RISCV::VMV_V_X: { |
| 8235 | // op: vd |
| 8236 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8237 | Value |= (op & 0x1f) << 7; |
| 8238 | // op: rs1 |
| 8239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8240 | Value |= (op & 0x1f) << 15; |
| 8241 | break; |
| 8242 | } |
| 8243 | case RISCV::VID_V: { |
| 8244 | // op: vd |
| 8245 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8246 | Value |= (op & 0x1f) << 7; |
| 8247 | // op: vm |
| 8248 | op = getVMaskReg(MI, OpNo: 1, Fixups, STI); |
| 8249 | Value |= (op & 0x1) << 25; |
| 8250 | break; |
| 8251 | } |
| 8252 | case RISCV::SF_VFEXPA_V: |
| 8253 | case RISCV::SF_VFEXP_V: |
| 8254 | case RISCV::VABS_V: |
| 8255 | case RISCV::VBREV8_V: |
| 8256 | case RISCV::VBREV_V: |
| 8257 | case RISCV::VCLZ_V: |
| 8258 | case RISCV::VCPOP_V: |
| 8259 | case RISCV::VCTZ_V: |
| 8260 | case RISCV::VFCLASS_V: |
| 8261 | case RISCV::VFCVT_F_XU_V: |
| 8262 | case RISCV::VFCVT_F_X_V: |
| 8263 | case RISCV::VFCVT_RTZ_XU_F_V: |
| 8264 | case RISCV::VFCVT_RTZ_X_F_V: |
| 8265 | case RISCV::VFCVT_XU_F_V: |
| 8266 | case RISCV::VFCVT_X_F_V: |
| 8267 | case RISCV::VFNCVTBF16_F_F_W: |
| 8268 | case RISCV::VFNCVTBF16_SAT_F_F_W: |
| 8269 | case RISCV::VFNCVT_F_F_Q: |
| 8270 | case RISCV::VFNCVT_F_F_W: |
| 8271 | case RISCV::VFNCVT_F_XU_W: |
| 8272 | case RISCV::VFNCVT_F_X_W: |
| 8273 | case RISCV::VFNCVT_ROD_F_F_W: |
| 8274 | case RISCV::VFNCVT_RTZ_XU_F_W: |
| 8275 | case RISCV::VFNCVT_RTZ_X_F_W: |
| 8276 | case RISCV::VFNCVT_SAT_F_F_Q: |
| 8277 | case RISCV::VFNCVT_XU_F_W: |
| 8278 | case RISCV::VFNCVT_X_F_W: |
| 8279 | case RISCV::VFREC7_V: |
| 8280 | case RISCV::VFRSQRT7_V: |
| 8281 | case RISCV::VFSQRT_V: |
| 8282 | case RISCV::VFWCVTBF16_F_F_V: |
| 8283 | case RISCV::VFWCVT_F_F_V: |
| 8284 | case RISCV::VFWCVT_F_XU_V: |
| 8285 | case RISCV::VFWCVT_F_X_V: |
| 8286 | case RISCV::VFWCVT_RTZ_XU_F_V: |
| 8287 | case RISCV::VFWCVT_RTZ_X_F_V: |
| 8288 | case RISCV::VFWCVT_XU_F_V: |
| 8289 | case RISCV::VFWCVT_X_F_V: |
| 8290 | case RISCV::VIOTA_M: |
| 8291 | case RISCV::VMSBF_M: |
| 8292 | case RISCV::VMSIF_M: |
| 8293 | case RISCV::VMSOF_M: |
| 8294 | case RISCV::VREV8_V: |
| 8295 | case RISCV::VSEXT_VF2: |
| 8296 | case RISCV::VSEXT_VF4: |
| 8297 | case RISCV::VSEXT_VF8: |
| 8298 | case RISCV::VUNZIPE_V: |
| 8299 | case RISCV::VUNZIPO_V: |
| 8300 | case RISCV::VZEXT_VF2: |
| 8301 | case RISCV::VZEXT_VF4: |
| 8302 | case RISCV::VZEXT_VF8: { |
| 8303 | // op: vd |
| 8304 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8305 | Value |= (op & 0x1f) << 7; |
| 8306 | // op: vm |
| 8307 | op = getVMaskReg(MI, OpNo: 2, Fixups, STI); |
| 8308 | Value |= (op & 0x1) << 25; |
| 8309 | // op: vs2 |
| 8310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8311 | Value |= (op & 0x1f) << 20; |
| 8312 | break; |
| 8313 | } |
| 8314 | case RISCV::VADD_VI: |
| 8315 | case RISCV::VAND_VI: |
| 8316 | case RISCV::VMSEQ_VI: |
| 8317 | case RISCV::VMSGTU_VI: |
| 8318 | case RISCV::VMSGT_VI: |
| 8319 | case RISCV::VMSLEU_VI: |
| 8320 | case RISCV::VMSLE_VI: |
| 8321 | case RISCV::VMSNE_VI: |
| 8322 | case RISCV::VNCLIPU_WI: |
| 8323 | case RISCV::VNCLIP_WI: |
| 8324 | case RISCV::VNSRA_WI: |
| 8325 | case RISCV::VNSRL_WI: |
| 8326 | case RISCV::VOR_VI: |
| 8327 | case RISCV::VRGATHER_VI: |
| 8328 | case RISCV::VRSUB_VI: |
| 8329 | case RISCV::VSADDU_VI: |
| 8330 | case RISCV::VSADD_VI: |
| 8331 | case RISCV::VSLIDEDOWN_VI: |
| 8332 | case RISCV::VSLIDEUP_VI: |
| 8333 | case RISCV::VSLL_VI: |
| 8334 | case RISCV::VSRA_VI: |
| 8335 | case RISCV::VSRL_VI: |
| 8336 | case RISCV::VSSRA_VI: |
| 8337 | case RISCV::VSSRL_VI: |
| 8338 | case RISCV::VWSLL_VI: |
| 8339 | case RISCV::VXOR_VI: { |
| 8340 | // op: vd |
| 8341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8342 | Value |= (op & 0x1f) << 7; |
| 8343 | // op: vm |
| 8344 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 8345 | Value |= (op & 0x1) << 25; |
| 8346 | // op: vs2 |
| 8347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8348 | Value |= (op & 0x1f) << 20; |
| 8349 | // op: imm |
| 8350 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 8351 | Value |= (op & 0x1f) << 15; |
| 8352 | break; |
| 8353 | } |
| 8354 | case RISCV::VROR_VI: { |
| 8355 | // op: vd |
| 8356 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8357 | Value |= (op & 0x1f) << 7; |
| 8358 | // op: vm |
| 8359 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 8360 | Value |= (op & 0x1) << 25; |
| 8361 | // op: vs2 |
| 8362 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8363 | Value |= (op & 0x1f) << 20; |
| 8364 | // op: imm |
| 8365 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 8366 | Value |= (op & 0x20) << 21; |
| 8367 | Value |= (op & 0x1f) << 15; |
| 8368 | break; |
| 8369 | } |
| 8370 | case RISCV::SF_VFNRCLIP_XU_F_QF: |
| 8371 | case RISCV::SF_VFNRCLIP_X_F_QF: |
| 8372 | case RISCV::VAADDU_VX: |
| 8373 | case RISCV::VAADD_VX: |
| 8374 | case RISCV::VADD_VX: |
| 8375 | case RISCV::VANDN_VX: |
| 8376 | case RISCV::VAND_VX: |
| 8377 | case RISCV::VASUBU_VX: |
| 8378 | case RISCV::VASUB_VX: |
| 8379 | case RISCV::VCLMULH_VX: |
| 8380 | case RISCV::VCLMUL_VX: |
| 8381 | case RISCV::VDIVU_VX: |
| 8382 | case RISCV::VDIV_VX: |
| 8383 | case RISCV::VFADD_VF: |
| 8384 | case RISCV::VFDIV_VF: |
| 8385 | case RISCV::VFMAX_VF: |
| 8386 | case RISCV::VFMIN_VF: |
| 8387 | case RISCV::VFMUL_VF: |
| 8388 | case RISCV::VFRDIV_VF: |
| 8389 | case RISCV::VFRSUB_VF: |
| 8390 | case RISCV::VFSGNJN_VF: |
| 8391 | case RISCV::VFSGNJX_VF: |
| 8392 | case RISCV::VFSGNJ_VF: |
| 8393 | case RISCV::VFSLIDE1DOWN_VF: |
| 8394 | case RISCV::VFSLIDE1UP_VF: |
| 8395 | case RISCV::VFSUB_VF: |
| 8396 | case RISCV::VFWADD_VF: |
| 8397 | case RISCV::VFWADD_WF: |
| 8398 | case RISCV::VFWMUL_VF: |
| 8399 | case RISCV::VFWSUB_VF: |
| 8400 | case RISCV::VFWSUB_WF: |
| 8401 | case RISCV::VMAXU_VX: |
| 8402 | case RISCV::VMAX_VX: |
| 8403 | case RISCV::VMFEQ_VF: |
| 8404 | case RISCV::VMFGE_VF: |
| 8405 | case RISCV::VMFGT_VF: |
| 8406 | case RISCV::VMFLE_VF: |
| 8407 | case RISCV::VMFLT_VF: |
| 8408 | case RISCV::VMFNE_VF: |
| 8409 | case RISCV::VMINU_VX: |
| 8410 | case RISCV::VMIN_VX: |
| 8411 | case RISCV::VMSEQ_VX: |
| 8412 | case RISCV::VMSGTU_VX: |
| 8413 | case RISCV::VMSGT_VX: |
| 8414 | case RISCV::VMSLEU_VX: |
| 8415 | case RISCV::VMSLE_VX: |
| 8416 | case RISCV::VMSLTU_VX: |
| 8417 | case RISCV::VMSLT_VX: |
| 8418 | case RISCV::VMSNE_VX: |
| 8419 | case RISCV::VMULHSU_VX: |
| 8420 | case RISCV::VMULHU_VX: |
| 8421 | case RISCV::VMULH_VX: |
| 8422 | case RISCV::VMUL_VX: |
| 8423 | case RISCV::VNCLIPU_WX: |
| 8424 | case RISCV::VNCLIP_WX: |
| 8425 | case RISCV::VNSRA_WX: |
| 8426 | case RISCV::VNSRL_WX: |
| 8427 | case RISCV::VOR_VX: |
| 8428 | case RISCV::VREMU_VX: |
| 8429 | case RISCV::VREM_VX: |
| 8430 | case RISCV::VRGATHER_VX: |
| 8431 | case RISCV::VROL_VX: |
| 8432 | case RISCV::VROR_VX: |
| 8433 | case RISCV::VRSUB_VX: |
| 8434 | case RISCV::VSADDU_VX: |
| 8435 | case RISCV::VSADD_VX: |
| 8436 | case RISCV::VSLIDE1DOWN_VX: |
| 8437 | case RISCV::VSLIDE1UP_VX: |
| 8438 | case RISCV::VSLIDEDOWN_VX: |
| 8439 | case RISCV::VSLIDEUP_VX: |
| 8440 | case RISCV::VSLL_VX: |
| 8441 | case RISCV::VSMUL_VX: |
| 8442 | case RISCV::VSRA_VX: |
| 8443 | case RISCV::VSRL_VX: |
| 8444 | case RISCV::VSSRA_VX: |
| 8445 | case RISCV::VSSRL_VX: |
| 8446 | case RISCV::VSSUBU_VX: |
| 8447 | case RISCV::VSSUB_VX: |
| 8448 | case RISCV::VSUB_VX: |
| 8449 | case RISCV::VWADDU_VX: |
| 8450 | case RISCV::VWADDU_WX: |
| 8451 | case RISCV::VWADD_VX: |
| 8452 | case RISCV::VWADD_WX: |
| 8453 | case RISCV::VWMULSU_VX: |
| 8454 | case RISCV::VWMULU_VX: |
| 8455 | case RISCV::VWMUL_VX: |
| 8456 | case RISCV::VWSLL_VX: |
| 8457 | case RISCV::VWSUBU_VX: |
| 8458 | case RISCV::VWSUBU_WX: |
| 8459 | case RISCV::VWSUB_VX: |
| 8460 | case RISCV::VWSUB_WX: |
| 8461 | case RISCV::VXOR_VX: { |
| 8462 | // op: vd |
| 8463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8464 | Value |= (op & 0x1f) << 7; |
| 8465 | // op: vm |
| 8466 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 8467 | Value |= (op & 0x1) << 25; |
| 8468 | // op: vs2 |
| 8469 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8470 | Value |= (op & 0x1f) << 20; |
| 8471 | // op: rs1 |
| 8472 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8473 | Value |= (op & 0x1f) << 15; |
| 8474 | break; |
| 8475 | } |
| 8476 | case RISCV::RI_VUNZIP2A_VV: |
| 8477 | case RISCV::RI_VUNZIP2B_VV: |
| 8478 | case RISCV::RI_VZIP2A_VV: |
| 8479 | case RISCV::RI_VZIP2B_VV: |
| 8480 | case RISCV::RI_VZIPEVEN_VV: |
| 8481 | case RISCV::RI_VZIPODD_VV: |
| 8482 | case RISCV::VAADDU_VV: |
| 8483 | case RISCV::VAADD_VV: |
| 8484 | case RISCV::VABDU_VV: |
| 8485 | case RISCV::VABD_VV: |
| 8486 | case RISCV::VADD_VV: |
| 8487 | case RISCV::VANDN_VV: |
| 8488 | case RISCV::VAND_VV: |
| 8489 | case RISCV::VASUBU_VV: |
| 8490 | case RISCV::VASUB_VV: |
| 8491 | case RISCV::VCLMULH_VV: |
| 8492 | case RISCV::VCLMUL_VV: |
| 8493 | case RISCV::VDIVU_VV: |
| 8494 | case RISCV::VDIV_VV: |
| 8495 | case RISCV::VFADD_VV: |
| 8496 | case RISCV::VFDIV_VV: |
| 8497 | case RISCV::VFMAX_VV: |
| 8498 | case RISCV::VFMIN_VV: |
| 8499 | case RISCV::VFMUL_VV: |
| 8500 | case RISCV::VFREDMAX_VS: |
| 8501 | case RISCV::VFREDMIN_VS: |
| 8502 | case RISCV::VFREDOSUM_VS: |
| 8503 | case RISCV::VFREDUSUM_VS: |
| 8504 | case RISCV::VFSGNJN_VV: |
| 8505 | case RISCV::VFSGNJX_VV: |
| 8506 | case RISCV::VFSGNJ_VV: |
| 8507 | case RISCV::VFSUB_VV: |
| 8508 | case RISCV::VFWADD_VV: |
| 8509 | case RISCV::VFWADD_WV: |
| 8510 | case RISCV::VFWMUL_VV: |
| 8511 | case RISCV::VFWREDOSUM_VS: |
| 8512 | case RISCV::VFWREDUSUM_VS: |
| 8513 | case RISCV::VFWSUB_VV: |
| 8514 | case RISCV::VFWSUB_WV: |
| 8515 | case RISCV::VMAXU_VV: |
| 8516 | case RISCV::VMAX_VV: |
| 8517 | case RISCV::VMFEQ_VV: |
| 8518 | case RISCV::VMFLE_VV: |
| 8519 | case RISCV::VMFLT_VV: |
| 8520 | case RISCV::VMFNE_VV: |
| 8521 | case RISCV::VMINU_VV: |
| 8522 | case RISCV::VMIN_VV: |
| 8523 | case RISCV::VMSEQ_VV: |
| 8524 | case RISCV::VMSLEU_VV: |
| 8525 | case RISCV::VMSLE_VV: |
| 8526 | case RISCV::VMSLTU_VV: |
| 8527 | case RISCV::VMSLT_VV: |
| 8528 | case RISCV::VMSNE_VV: |
| 8529 | case RISCV::VMULHSU_VV: |
| 8530 | case RISCV::VMULHU_VV: |
| 8531 | case RISCV::VMULH_VV: |
| 8532 | case RISCV::VMUL_VV: |
| 8533 | case RISCV::VNCLIPU_WV: |
| 8534 | case RISCV::VNCLIP_WV: |
| 8535 | case RISCV::VNSRA_WV: |
| 8536 | case RISCV::VNSRL_WV: |
| 8537 | case RISCV::VOR_VV: |
| 8538 | case RISCV::VPAIRE_VV: |
| 8539 | case RISCV::VPAIRO_VV: |
| 8540 | case RISCV::VREDAND_VS: |
| 8541 | case RISCV::VREDMAXU_VS: |
| 8542 | case RISCV::VREDMAX_VS: |
| 8543 | case RISCV::VREDMINU_VS: |
| 8544 | case RISCV::VREDMIN_VS: |
| 8545 | case RISCV::VREDOR_VS: |
| 8546 | case RISCV::VREDSUM_VS: |
| 8547 | case RISCV::VREDXOR_VS: |
| 8548 | case RISCV::VREMU_VV: |
| 8549 | case RISCV::VREM_VV: |
| 8550 | case RISCV::VRGATHEREI16_VV: |
| 8551 | case RISCV::VRGATHER_VV: |
| 8552 | case RISCV::VROL_VV: |
| 8553 | case RISCV::VROR_VV: |
| 8554 | case RISCV::VSADDU_VV: |
| 8555 | case RISCV::VSADD_VV: |
| 8556 | case RISCV::VSLL_VV: |
| 8557 | case RISCV::VSMUL_VV: |
| 8558 | case RISCV::VSRA_VV: |
| 8559 | case RISCV::VSRL_VV: |
| 8560 | case RISCV::VSSRA_VV: |
| 8561 | case RISCV::VSSRL_VV: |
| 8562 | case RISCV::VSSUBU_VV: |
| 8563 | case RISCV::VSSUB_VV: |
| 8564 | case RISCV::VSUB_VV: |
| 8565 | case RISCV::VWABDAU_VV: |
| 8566 | case RISCV::VWABDA_VV: |
| 8567 | case RISCV::VWADDU_VV: |
| 8568 | case RISCV::VWADDU_WV: |
| 8569 | case RISCV::VWADD_VV: |
| 8570 | case RISCV::VWADD_WV: |
| 8571 | case RISCV::VWMULSU_VV: |
| 8572 | case RISCV::VWMULU_VV: |
| 8573 | case RISCV::VWMUL_VV: |
| 8574 | case RISCV::VWREDSUMU_VS: |
| 8575 | case RISCV::VWREDSUM_VS: |
| 8576 | case RISCV::VWSLL_VV: |
| 8577 | case RISCV::VWSUBU_VV: |
| 8578 | case RISCV::VWSUBU_WV: |
| 8579 | case RISCV::VWSUB_VV: |
| 8580 | case RISCV::VWSUB_WV: |
| 8581 | case RISCV::VXOR_VV: |
| 8582 | case RISCV::VZIP_VV: { |
| 8583 | // op: vd |
| 8584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8585 | Value |= (op & 0x1f) << 7; |
| 8586 | // op: vm |
| 8587 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 8588 | Value |= (op & 0x1) << 25; |
| 8589 | // op: vs2 |
| 8590 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8591 | Value |= (op & 0x1f) << 20; |
| 8592 | // op: vs1 |
| 8593 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8594 | Value |= (op & 0x1f) << 15; |
| 8595 | break; |
| 8596 | } |
| 8597 | case RISCV::VMV_V_V: { |
| 8598 | // op: vd |
| 8599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8600 | Value |= (op & 0x1f) << 7; |
| 8601 | // op: vs1 |
| 8602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8603 | Value |= (op & 0x1f) << 15; |
| 8604 | break; |
| 8605 | } |
| 8606 | case RISCV::VMV1R_V: |
| 8607 | case RISCV::VMV2R_V: |
| 8608 | case RISCV::VMV4R_V: |
| 8609 | case RISCV::VMV8R_V: { |
| 8610 | // op: vd |
| 8611 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8612 | Value |= (op & 0x1f) << 7; |
| 8613 | // op: vs2 |
| 8614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8615 | Value |= (op & 0x1f) << 20; |
| 8616 | break; |
| 8617 | } |
| 8618 | case RISCV::VADC_VIM: |
| 8619 | case RISCV::VAESKF1_VI: |
| 8620 | case RISCV::VMADC_VI: |
| 8621 | case RISCV::VMADC_VIM: |
| 8622 | case RISCV::VMERGE_VIM: |
| 8623 | case RISCV::VSM4K_VI: { |
| 8624 | // op: vd |
| 8625 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8626 | Value |= (op & 0x1f) << 7; |
| 8627 | // op: vs2 |
| 8628 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8629 | Value |= (op & 0x1f) << 20; |
| 8630 | // op: imm |
| 8631 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 8632 | Value |= (op & 0x1f) << 15; |
| 8633 | break; |
| 8634 | } |
| 8635 | case RISCV::VADC_VXM: |
| 8636 | case RISCV::VFMERGE_VFM: |
| 8637 | case RISCV::VMADC_VX: |
| 8638 | case RISCV::VMADC_VXM: |
| 8639 | case RISCV::VMERGE_VXM: |
| 8640 | case RISCV::VMSBC_VX: |
| 8641 | case RISCV::VMSBC_VXM: |
| 8642 | case RISCV::VSBC_VXM: { |
| 8643 | // op: vd |
| 8644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8645 | Value |= (op & 0x1f) << 7; |
| 8646 | // op: vs2 |
| 8647 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8648 | Value |= (op & 0x1f) << 20; |
| 8649 | // op: rs1 |
| 8650 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8651 | Value |= (op & 0x1f) << 15; |
| 8652 | break; |
| 8653 | } |
| 8654 | case RISCV::VADC_VVM: |
| 8655 | case RISCV::VCOMPRESS_VM: |
| 8656 | case RISCV::VMADC_VV: |
| 8657 | case RISCV::VMADC_VVM: |
| 8658 | case RISCV::VMANDN_MM: |
| 8659 | case RISCV::VMAND_MM: |
| 8660 | case RISCV::VMERGE_VVM: |
| 8661 | case RISCV::VMNAND_MM: |
| 8662 | case RISCV::VMNOR_MM: |
| 8663 | case RISCV::VMORN_MM: |
| 8664 | case RISCV::VMOR_MM: |
| 8665 | case RISCV::VMSBC_VV: |
| 8666 | case RISCV::VMSBC_VVM: |
| 8667 | case RISCV::VMXNOR_MM: |
| 8668 | case RISCV::VMXOR_MM: |
| 8669 | case RISCV::VSBC_VVM: |
| 8670 | case RISCV::VSM3ME_VV: { |
| 8671 | // op: vd |
| 8672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8673 | Value |= (op & 0x1f) << 7; |
| 8674 | // op: vs2 |
| 8675 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8676 | Value |= (op & 0x1f) << 20; |
| 8677 | // op: vs1 |
| 8678 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8679 | Value |= (op & 0x1f) << 15; |
| 8680 | break; |
| 8681 | } |
| 8682 | case RISCV::VFMV_S_F: |
| 8683 | case RISCV::VMV_S_X: { |
| 8684 | // op: vd |
| 8685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8686 | Value |= (op & 0x1f) << 7; |
| 8687 | // op: rs1 |
| 8688 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8689 | Value |= (op & 0x1f) << 15; |
| 8690 | break; |
| 8691 | } |
| 8692 | case RISCV::VDOTA4SU_VX: |
| 8693 | case RISCV::VDOTA4US_VX: |
| 8694 | case RISCV::VDOTA4U_VX: |
| 8695 | case RISCV::VDOTA4_VX: { |
| 8696 | // op: vd |
| 8697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8698 | Value |= (op & 0x1f) << 7; |
| 8699 | // op: vm |
| 8700 | op = getVMaskReg(MI, OpNo: 4, Fixups, STI); |
| 8701 | Value |= (op & 0x1) << 25; |
| 8702 | // op: vs2 |
| 8703 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8704 | Value |= (op & 0x1f) << 20; |
| 8705 | // op: rs1 |
| 8706 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8707 | Value |= (op & 0x1f) << 15; |
| 8708 | break; |
| 8709 | } |
| 8710 | case RISCV::VDOTA4SU_VV: |
| 8711 | case RISCV::VDOTA4U_VV: |
| 8712 | case RISCV::VDOTA4_VV: { |
| 8713 | // op: vd |
| 8714 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8715 | Value |= (op & 0x1f) << 7; |
| 8716 | // op: vm |
| 8717 | op = getVMaskReg(MI, OpNo: 4, Fixups, STI); |
| 8718 | Value |= (op & 0x1) << 25; |
| 8719 | // op: vs2 |
| 8720 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8721 | Value |= (op & 0x1f) << 20; |
| 8722 | // op: vs1 |
| 8723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8724 | Value |= (op & 0x1f) << 15; |
| 8725 | break; |
| 8726 | } |
| 8727 | case RISCV::TH_VMAQASU_VX: |
| 8728 | case RISCV::TH_VMAQAUS_VX: |
| 8729 | case RISCV::TH_VMAQAU_VX: |
| 8730 | case RISCV::TH_VMAQA_VX: |
| 8731 | case RISCV::VFMACC_VF: |
| 8732 | case RISCV::VFMADD_VF: |
| 8733 | case RISCV::VFMSAC_VF: |
| 8734 | case RISCV::VFMSUB_VF: |
| 8735 | case RISCV::VFNMACC_VF: |
| 8736 | case RISCV::VFNMADD_VF: |
| 8737 | case RISCV::VFNMSAC_VF: |
| 8738 | case RISCV::VFNMSUB_VF: |
| 8739 | case RISCV::VFWMACCBF16_VF: |
| 8740 | case RISCV::VFWMACC_VF: |
| 8741 | case RISCV::VFWMSAC_VF: |
| 8742 | case RISCV::VFWNMACC_VF: |
| 8743 | case RISCV::VFWNMSAC_VF: |
| 8744 | case RISCV::VMACC_VX: |
| 8745 | case RISCV::VMADD_VX: |
| 8746 | case RISCV::VNMSAC_VX: |
| 8747 | case RISCV::VNMSUB_VX: |
| 8748 | case RISCV::VWMACCSU_VX: |
| 8749 | case RISCV::VWMACCUS_VX: |
| 8750 | case RISCV::VWMACCU_VX: |
| 8751 | case RISCV::VWMACC_VX: { |
| 8752 | // op: vd |
| 8753 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8754 | Value |= (op & 0x1f) << 7; |
| 8755 | // op: vm |
| 8756 | op = getVMaskReg(MI, OpNo: 4, Fixups, STI); |
| 8757 | Value |= (op & 0x1) << 25; |
| 8758 | // op: vs2 |
| 8759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8760 | Value |= (op & 0x1f) << 20; |
| 8761 | // op: rs1 |
| 8762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8763 | Value |= (op & 0x1f) << 15; |
| 8764 | break; |
| 8765 | } |
| 8766 | case RISCV::TH_VMAQASU_VV: |
| 8767 | case RISCV::TH_VMAQAU_VV: |
| 8768 | case RISCV::TH_VMAQA_VV: |
| 8769 | case RISCV::VFMACC_VV: |
| 8770 | case RISCV::VFMADD_VV: |
| 8771 | case RISCV::VFMSAC_VV: |
| 8772 | case RISCV::VFMSUB_VV: |
| 8773 | case RISCV::VFNMACC_VV: |
| 8774 | case RISCV::VFNMADD_VV: |
| 8775 | case RISCV::VFNMSAC_VV: |
| 8776 | case RISCV::VFNMSUB_VV: |
| 8777 | case RISCV::VFWMACCBF16_VV: |
| 8778 | case RISCV::VFWMACC_VV: |
| 8779 | case RISCV::VFWMSAC_VV: |
| 8780 | case RISCV::VFWNMACC_VV: |
| 8781 | case RISCV::VFWNMSAC_VV: |
| 8782 | case RISCV::VMACC_VV: |
| 8783 | case RISCV::VMADD_VV: |
| 8784 | case RISCV::VNMSAC_VV: |
| 8785 | case RISCV::VNMSUB_VV: |
| 8786 | case RISCV::VWMACCSU_VV: |
| 8787 | case RISCV::VWMACCU_VV: |
| 8788 | case RISCV::VWMACC_VV: { |
| 8789 | // op: vd |
| 8790 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8791 | Value |= (op & 0x1f) << 7; |
| 8792 | // op: vm |
| 8793 | op = getVMaskReg(MI, OpNo: 4, Fixups, STI); |
| 8794 | Value |= (op & 0x1) << 25; |
| 8795 | // op: vs2 |
| 8796 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8797 | Value |= (op & 0x1f) << 20; |
| 8798 | // op: vs1 |
| 8799 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8800 | Value |= (op & 0x1f) << 15; |
| 8801 | break; |
| 8802 | } |
| 8803 | case RISCV::SMT_VMADOT1: |
| 8804 | case RISCV::SMT_VMADOT1SU: |
| 8805 | case RISCV::SMT_VMADOT1U: |
| 8806 | case RISCV::SMT_VMADOT1US: |
| 8807 | case RISCV::SMT_VMADOT2: |
| 8808 | case RISCV::SMT_VMADOT2SU: |
| 8809 | case RISCV::SMT_VMADOT2U: |
| 8810 | case RISCV::SMT_VMADOT2US: |
| 8811 | case RISCV::SMT_VMADOT3: |
| 8812 | case RISCV::SMT_VMADOT3SU: |
| 8813 | case RISCV::SMT_VMADOT3U: |
| 8814 | case RISCV::SMT_VMADOT3US: { |
| 8815 | // op: vd |
| 8816 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8817 | Value |= (op & 0x1f) << 7; |
| 8818 | // op: vs1 |
| 8819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8820 | Value |= (op & 0x1e) << 15; |
| 8821 | // op: vs2 |
| 8822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8823 | Value |= (op & 0x1f) << 20; |
| 8824 | break; |
| 8825 | } |
| 8826 | case RISCV::SMT_VMADOT: |
| 8827 | case RISCV::SMT_VMADOTSU: |
| 8828 | case RISCV::SMT_VMADOTU: |
| 8829 | case RISCV::SMT_VMADOTUS: { |
| 8830 | // op: vd |
| 8831 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8832 | Value |= (op & 0x1f) << 7; |
| 8833 | // op: vs1 |
| 8834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8835 | Value |= (op & 0x1f) << 15; |
| 8836 | // op: vs2 |
| 8837 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8838 | Value |= (op & 0x1f) << 20; |
| 8839 | break; |
| 8840 | } |
| 8841 | case RISCV::VAESDF_VS: |
| 8842 | case RISCV::VAESDF_VV: |
| 8843 | case RISCV::VAESDM_VS: |
| 8844 | case RISCV::VAESDM_VV: |
| 8845 | case RISCV::VAESEF_VS: |
| 8846 | case RISCV::VAESEF_VV: |
| 8847 | case RISCV::VAESEM_VS: |
| 8848 | case RISCV::VAESEM_VV: |
| 8849 | case RISCV::VAESZ_VS: |
| 8850 | case RISCV::VGMUL_VS: |
| 8851 | case RISCV::VGMUL_VV: |
| 8852 | case RISCV::VSM4R_VS: |
| 8853 | case RISCV::VSM4R_VV: { |
| 8854 | // op: vd |
| 8855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8856 | Value |= (op & 0x1f) << 7; |
| 8857 | // op: vs2 |
| 8858 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8859 | Value |= (op & 0x1f) << 20; |
| 8860 | break; |
| 8861 | } |
| 8862 | case RISCV::VAESKF2_VI: |
| 8863 | case RISCV::VSM3C_VI: { |
| 8864 | // op: vd |
| 8865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8866 | Value |= (op & 0x1f) << 7; |
| 8867 | // op: vs2 |
| 8868 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8869 | Value |= (op & 0x1f) << 20; |
| 8870 | // op: imm |
| 8871 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 8872 | Value |= (op & 0x1f) << 15; |
| 8873 | break; |
| 8874 | } |
| 8875 | case RISCV::VGHSH_VS: |
| 8876 | case RISCV::VGHSH_VV: |
| 8877 | case RISCV::VSHA2CH_VV: |
| 8878 | case RISCV::VSHA2CL_VV: |
| 8879 | case RISCV::VSHA2MS_VV: { |
| 8880 | // op: vd |
| 8881 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8882 | Value |= (op & 0x1f) << 7; |
| 8883 | // op: vs2 |
| 8884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8885 | Value |= (op & 0x1f) << 20; |
| 8886 | // op: vs1 |
| 8887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8888 | Value |= (op & 0x1f) << 15; |
| 8889 | break; |
| 8890 | } |
| 8891 | case RISCV::SF_VFWMACC_4x4x4: |
| 8892 | case RISCV::SF_VQMACCSU_2x8x2: |
| 8893 | case RISCV::SF_VQMACCSU_4x8x4: |
| 8894 | case RISCV::SF_VQMACCUS_2x8x2: |
| 8895 | case RISCV::SF_VQMACCUS_4x8x4: |
| 8896 | case RISCV::SF_VQMACCU_2x8x2: |
| 8897 | case RISCV::SF_VQMACCU_4x8x4: |
| 8898 | case RISCV::SF_VQMACC_2x8x2: |
| 8899 | case RISCV::SF_VQMACC_4x8x4: { |
| 8900 | // op: vd |
| 8901 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8902 | Value |= (op & 0x1f) << 7; |
| 8903 | // op: vs2 |
| 8904 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8905 | Value |= (op & 0x1f) << 20; |
| 8906 | // op: vs1 |
| 8907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8908 | Value |= (op & 0x1f) << 15; |
| 8909 | break; |
| 8910 | } |
| 8911 | case RISCV::NDS_VFWCVT_F_B: |
| 8912 | case RISCV::NDS_VFWCVT_F_BU: |
| 8913 | case RISCV::NDS_VFWCVT_F_N: |
| 8914 | case RISCV::NDS_VFWCVT_F_NU: { |
| 8915 | // op: vs |
| 8916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8917 | Value |= (op & 0x1f) << 20; |
| 8918 | // op: vd |
| 8919 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8920 | Value |= (op & 0x1f) << 7; |
| 8921 | // op: vm |
| 8922 | op = getVMaskReg(MI, OpNo: 2, Fixups, STI); |
| 8923 | Value |= (op & 0x1) << 25; |
| 8924 | break; |
| 8925 | } |
| 8926 | case RISCV::SF_VC_I: { |
| 8927 | // op: vs2 |
| 8928 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 8929 | Value |= (op & 0x1f) << 20; |
| 8930 | // op: vd |
| 8931 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 8932 | Value |= (op & 0x1f) << 7; |
| 8933 | // op: imm |
| 8934 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 8935 | Value |= (op & 0x1f) << 15; |
| 8936 | // op: funct6_lo2 |
| 8937 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 8938 | Value |= (op & 0x3) << 26; |
| 8939 | break; |
| 8940 | } |
| 8941 | case RISCV::SF_VC_X: { |
| 8942 | // op: vs2 |
| 8943 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 8944 | Value |= (op & 0x1f) << 20; |
| 8945 | // op: vd |
| 8946 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 8947 | Value |= (op & 0x1f) << 7; |
| 8948 | // op: rs1 |
| 8949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8950 | Value |= (op & 0x1f) << 15; |
| 8951 | // op: funct6_lo2 |
| 8952 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 8953 | Value |= (op & 0x3) << 26; |
| 8954 | break; |
| 8955 | } |
| 8956 | case RISCV::SF_VC_V_I: { |
| 8957 | // op: vs2 |
| 8958 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 8959 | Value |= (op & 0x1f) << 20; |
| 8960 | // op: vd |
| 8961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8962 | Value |= (op & 0x1f) << 7; |
| 8963 | // op: imm |
| 8964 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 8965 | Value |= (op & 0x1f) << 15; |
| 8966 | // op: funct6_lo2 |
| 8967 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 8968 | Value |= (op & 0x3) << 26; |
| 8969 | break; |
| 8970 | } |
| 8971 | case RISCV::SF_VC_V_X: { |
| 8972 | // op: vs2 |
| 8973 | op = getImmOpValue(MI, OpNo: 2, Fixups, STI); |
| 8974 | Value |= (op & 0x1f) << 20; |
| 8975 | // op: vd |
| 8976 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8977 | Value |= (op & 0x1f) << 7; |
| 8978 | // op: rs1 |
| 8979 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8980 | Value |= (op & 0x1f) << 15; |
| 8981 | // op: funct6_lo2 |
| 8982 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 8983 | Value |= (op & 0x3) << 26; |
| 8984 | break; |
| 8985 | } |
| 8986 | case RISCV::NDS_VFPMADB_VF: |
| 8987 | case RISCV::NDS_VFPMADT_VF: { |
| 8988 | // op: vs2 |
| 8989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8990 | Value |= (op & 0x1f) << 20; |
| 8991 | // op: rs1 |
| 8992 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8993 | Value |= (op & 0x1f) << 15; |
| 8994 | // op: vd |
| 8995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8996 | Value |= (op & 0x1f) << 7; |
| 8997 | // op: vm |
| 8998 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 8999 | Value |= (op & 0x1) << 25; |
| 9000 | break; |
| 9001 | } |
| 9002 | case RISCV::NDS_VFNCVT_BF16_S: |
| 9003 | case RISCV::NDS_VFWCVT_S_BF16: { |
| 9004 | // op: vs2 |
| 9005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9006 | Value |= (op & 0x1f) << 20; |
| 9007 | // op: vd |
| 9008 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9009 | Value |= (op & 0x1f) << 7; |
| 9010 | break; |
| 9011 | } |
| 9012 | case RISCV::SF_MM_E4M3_E4M3: |
| 9013 | case RISCV::SF_MM_E4M3_E5M2: |
| 9014 | case RISCV::SF_MM_E5M2_E4M3: |
| 9015 | case RISCV::SF_MM_E5M2_E5M2: |
| 9016 | case RISCV::SF_MM_S_S: |
| 9017 | case RISCV::SF_MM_S_U: |
| 9018 | case RISCV::SF_MM_U_S: |
| 9019 | case RISCV::SF_MM_U_U: { |
| 9020 | // op: vs2 |
| 9021 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9022 | Value |= (op & 0x1f) << 20; |
| 9023 | // op: vs1 |
| 9024 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9025 | Value |= (op & 0x1f) << 15; |
| 9026 | // op: rd |
| 9027 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9028 | Value |= (op & 0xc) << 8; |
| 9029 | break; |
| 9030 | } |
| 9031 | case RISCV::SF_MM_F_F: { |
| 9032 | // op: vs2 |
| 9033 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9034 | Value |= (op & 0x1f) << 20; |
| 9035 | // op: vs1 |
| 9036 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9037 | Value |= (op & 0x1f) << 15; |
| 9038 | // op: rd |
| 9039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9040 | Value |= (op & 0xe) << 8; |
| 9041 | break; |
| 9042 | } |
| 9043 | case RISCV::SF_VC_IV: { |
| 9044 | // op: vs2 |
| 9045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9046 | Value |= (op & 0x1f) << 20; |
| 9047 | // op: vd |
| 9048 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9049 | Value |= (op & 0x1f) << 7; |
| 9050 | // op: imm |
| 9051 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 9052 | Value |= (op & 0x1f) << 15; |
| 9053 | // op: funct6_lo2 |
| 9054 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 9055 | Value |= (op & 0x3) << 26; |
| 9056 | break; |
| 9057 | } |
| 9058 | case RISCV::SF_VC_FV: { |
| 9059 | // op: vs2 |
| 9060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9061 | Value |= (op & 0x1f) << 20; |
| 9062 | // op: vd |
| 9063 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9064 | Value |= (op & 0x1f) << 7; |
| 9065 | // op: rs1 |
| 9066 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9067 | Value |= (op & 0x1f) << 15; |
| 9068 | // op: funct6_lo1 |
| 9069 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 9070 | Value |= (op & 0x1) << 26; |
| 9071 | break; |
| 9072 | } |
| 9073 | case RISCV::SF_VC_XV: { |
| 9074 | // op: vs2 |
| 9075 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9076 | Value |= (op & 0x1f) << 20; |
| 9077 | // op: vd |
| 9078 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9079 | Value |= (op & 0x1f) << 7; |
| 9080 | // op: rs1 |
| 9081 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9082 | Value |= (op & 0x1f) << 15; |
| 9083 | // op: funct6_lo2 |
| 9084 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 9085 | Value |= (op & 0x3) << 26; |
| 9086 | break; |
| 9087 | } |
| 9088 | case RISCV::SF_VC_VV: { |
| 9089 | // op: vs2 |
| 9090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9091 | Value |= (op & 0x1f) << 20; |
| 9092 | // op: vd |
| 9093 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9094 | Value |= (op & 0x1f) << 7; |
| 9095 | // op: vs1 |
| 9096 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9097 | Value |= (op & 0x1f) << 15; |
| 9098 | // op: funct6_lo2 |
| 9099 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 9100 | Value |= (op & 0x3) << 26; |
| 9101 | break; |
| 9102 | } |
| 9103 | case RISCV::SF_VC_V_IV: { |
| 9104 | // op: vs2 |
| 9105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9106 | Value |= (op & 0x1f) << 20; |
| 9107 | // op: vd |
| 9108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9109 | Value |= (op & 0x1f) << 7; |
| 9110 | // op: imm |
| 9111 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 9112 | Value |= (op & 0x1f) << 15; |
| 9113 | // op: funct6_lo2 |
| 9114 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9115 | Value |= (op & 0x3) << 26; |
| 9116 | break; |
| 9117 | } |
| 9118 | case RISCV::SF_VC_V_FV: { |
| 9119 | // op: vs2 |
| 9120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9121 | Value |= (op & 0x1f) << 20; |
| 9122 | // op: vd |
| 9123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9124 | Value |= (op & 0x1f) << 7; |
| 9125 | // op: rs1 |
| 9126 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9127 | Value |= (op & 0x1f) << 15; |
| 9128 | // op: funct6_lo1 |
| 9129 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9130 | Value |= (op & 0x1) << 26; |
| 9131 | break; |
| 9132 | } |
| 9133 | case RISCV::SF_VC_V_XV: { |
| 9134 | // op: vs2 |
| 9135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9136 | Value |= (op & 0x1f) << 20; |
| 9137 | // op: vd |
| 9138 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9139 | Value |= (op & 0x1f) << 7; |
| 9140 | // op: rs1 |
| 9141 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9142 | Value |= (op & 0x1f) << 15; |
| 9143 | // op: funct6_lo2 |
| 9144 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9145 | Value |= (op & 0x3) << 26; |
| 9146 | break; |
| 9147 | } |
| 9148 | case RISCV::SF_VC_V_VV: { |
| 9149 | // op: vs2 |
| 9150 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9151 | Value |= (op & 0x1f) << 20; |
| 9152 | // op: vd |
| 9153 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9154 | Value |= (op & 0x1f) << 7; |
| 9155 | // op: vs1 |
| 9156 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9157 | Value |= (op & 0x1f) << 15; |
| 9158 | // op: funct6_lo2 |
| 9159 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9160 | Value |= (op & 0x3) << 26; |
| 9161 | break; |
| 9162 | } |
| 9163 | case RISCV::SF_VC_IVV: |
| 9164 | case RISCV::SF_VC_IVW: { |
| 9165 | // op: vs2 |
| 9166 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9167 | Value |= (op & 0x1f) << 20; |
| 9168 | // op: vd |
| 9169 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9170 | Value |= (op & 0x1f) << 7; |
| 9171 | // op: imm |
| 9172 | op = getImmOpValue(MI, OpNo: 3, Fixups, STI); |
| 9173 | Value |= (op & 0x1f) << 15; |
| 9174 | // op: funct6_lo2 |
| 9175 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 9176 | Value |= (op & 0x3) << 26; |
| 9177 | break; |
| 9178 | } |
| 9179 | case RISCV::SF_VC_FVV: |
| 9180 | case RISCV::SF_VC_FVW: { |
| 9181 | // op: vs2 |
| 9182 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9183 | Value |= (op & 0x1f) << 20; |
| 9184 | // op: vd |
| 9185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9186 | Value |= (op & 0x1f) << 7; |
| 9187 | // op: rs1 |
| 9188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9189 | Value |= (op & 0x1f) << 15; |
| 9190 | // op: funct6_lo1 |
| 9191 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 9192 | Value |= (op & 0x1) << 26; |
| 9193 | break; |
| 9194 | } |
| 9195 | case RISCV::SF_VC_XVV: |
| 9196 | case RISCV::SF_VC_XVW: { |
| 9197 | // op: vs2 |
| 9198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9199 | Value |= (op & 0x1f) << 20; |
| 9200 | // op: vd |
| 9201 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9202 | Value |= (op & 0x1f) << 7; |
| 9203 | // op: rs1 |
| 9204 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9205 | Value |= (op & 0x1f) << 15; |
| 9206 | // op: funct6_lo2 |
| 9207 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 9208 | Value |= (op & 0x3) << 26; |
| 9209 | break; |
| 9210 | } |
| 9211 | case RISCV::SF_VC_VVV: |
| 9212 | case RISCV::SF_VC_VVW: { |
| 9213 | // op: vs2 |
| 9214 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9215 | Value |= (op & 0x1f) << 20; |
| 9216 | // op: vd |
| 9217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9218 | Value |= (op & 0x1f) << 7; |
| 9219 | // op: vs1 |
| 9220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9221 | Value |= (op & 0x1f) << 15; |
| 9222 | // op: funct6_lo2 |
| 9223 | op = getImmOpValue(MI, OpNo: 0, Fixups, STI); |
| 9224 | Value |= (op & 0x3) << 26; |
| 9225 | break; |
| 9226 | } |
| 9227 | case RISCV::NDS_VD4DOTSU_VV: |
| 9228 | case RISCV::NDS_VD4DOTS_VV: |
| 9229 | case RISCV::NDS_VD4DOTU_VV: { |
| 9230 | // op: vs2 |
| 9231 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9232 | Value |= (op & 0x1f) << 20; |
| 9233 | // op: vs1 |
| 9234 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9235 | Value |= (op & 0x1f) << 15; |
| 9236 | // op: vd |
| 9237 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9238 | Value |= (op & 0x1f) << 7; |
| 9239 | // op: vm |
| 9240 | op = getVMaskReg(MI, OpNo: 3, Fixups, STI); |
| 9241 | Value |= (op & 0x1) << 25; |
| 9242 | break; |
| 9243 | } |
| 9244 | case RISCV::SF_VC_V_IVV: |
| 9245 | case RISCV::SF_VC_V_IVW: { |
| 9246 | // op: vs2 |
| 9247 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9248 | Value |= (op & 0x1f) << 20; |
| 9249 | // op: vd |
| 9250 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9251 | Value |= (op & 0x1f) << 7; |
| 9252 | // op: imm |
| 9253 | op = getImmOpValue(MI, OpNo: 4, Fixups, STI); |
| 9254 | Value |= (op & 0x1f) << 15; |
| 9255 | // op: funct6_lo2 |
| 9256 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9257 | Value |= (op & 0x3) << 26; |
| 9258 | break; |
| 9259 | } |
| 9260 | case RISCV::SF_VC_V_FVV: |
| 9261 | case RISCV::SF_VC_V_FVW: { |
| 9262 | // op: vs2 |
| 9263 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9264 | Value |= (op & 0x1f) << 20; |
| 9265 | // op: vd |
| 9266 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9267 | Value |= (op & 0x1f) << 7; |
| 9268 | // op: rs1 |
| 9269 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9270 | Value |= (op & 0x1f) << 15; |
| 9271 | // op: funct6_lo1 |
| 9272 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9273 | Value |= (op & 0x1) << 26; |
| 9274 | break; |
| 9275 | } |
| 9276 | case RISCV::SF_VC_V_XVV: |
| 9277 | case RISCV::SF_VC_V_XVW: { |
| 9278 | // op: vs2 |
| 9279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9280 | Value |= (op & 0x1f) << 20; |
| 9281 | // op: vd |
| 9282 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9283 | Value |= (op & 0x1f) << 7; |
| 9284 | // op: rs1 |
| 9285 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9286 | Value |= (op & 0x1f) << 15; |
| 9287 | // op: funct6_lo2 |
| 9288 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9289 | Value |= (op & 0x3) << 26; |
| 9290 | break; |
| 9291 | } |
| 9292 | case RISCV::SF_VC_V_VVV: |
| 9293 | case RISCV::SF_VC_V_VVW: { |
| 9294 | // op: vs2 |
| 9295 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9296 | Value |= (op & 0x1f) << 20; |
| 9297 | // op: vd |
| 9298 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9299 | Value |= (op & 0x1f) << 7; |
| 9300 | // op: vs1 |
| 9301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9302 | Value |= (op & 0x1f) << 15; |
| 9303 | // op: funct6_lo2 |
| 9304 | op = getImmOpValue(MI, OpNo: 1, Fixups, STI); |
| 9305 | Value |= (op & 0x3) << 26; |
| 9306 | break; |
| 9307 | } |
| 9308 | default: |
| 9309 | reportUnsupportedInst(Inst: MI); |
| 9310 | } |
| 9311 | return Value; |
| 9312 | } |
| 9313 | |
| 9314 | #ifdef GET_OPERAND_BIT_OFFSET |
| 9315 | #undef GET_OPERAND_BIT_OFFSET |
| 9316 | |
| 9317 | uint32_t RISCVMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
| 9318 | unsigned OpNum, |
| 9319 | const MCSubtargetInfo &STI) const { |
| 9320 | switch (MI.getOpcode()) { |
| 9321 | case RISCV::C_EBREAK: |
| 9322 | case RISCV::C_MOP_11: |
| 9323 | case RISCV::C_MOP_13: |
| 9324 | case RISCV::C_MOP_15: |
| 9325 | case RISCV::C_MOP_3: |
| 9326 | case RISCV::C_MOP_7: |
| 9327 | case RISCV::C_MOP_9: |
| 9328 | case RISCV::C_NOP: |
| 9329 | case RISCV::C_SSPOPCHK: |
| 9330 | case RISCV::C_SSPUSH: |
| 9331 | case RISCV::C_UNIMP: |
| 9332 | case RISCV::DRET: |
| 9333 | case RISCV::EBREAK: |
| 9334 | case RISCV::ECALL: |
| 9335 | case RISCV::FENCE_I: |
| 9336 | case RISCV::FENCE_TSO: |
| 9337 | case RISCV::MIPS_EHB: |
| 9338 | case RISCV::MIPS_IHB: |
| 9339 | case RISCV::MIPS_PAUSE: |
| 9340 | case RISCV::MNRET: |
| 9341 | case RISCV::MRET: |
| 9342 | case RISCV::QC_C_DI: |
| 9343 | case RISCV::QC_C_EI: |
| 9344 | case RISCV::QC_C_MIENTER: |
| 9345 | case RISCV::QC_C_MIENTER_NEST: |
| 9346 | case RISCV::QC_C_MILEAVERET: |
| 9347 | case RISCV::QC_C_MNRET: |
| 9348 | case RISCV::QC_C_MRET: |
| 9349 | case RISCV::SCTRCLR: |
| 9350 | case RISCV::SFENCE_INVAL_IR: |
| 9351 | case RISCV::SFENCE_W_INVAL: |
| 9352 | case RISCV::SF_CEASE: |
| 9353 | case RISCV::SF_VTDISCARD: |
| 9354 | case RISCV::SRET: |
| 9355 | case RISCV::TH_DCACHE_CALL: |
| 9356 | case RISCV::TH_DCACHE_CIALL: |
| 9357 | case RISCV::TH_DCACHE_IALL: |
| 9358 | case RISCV::TH_ICACHE_IALL: |
| 9359 | case RISCV::TH_ICACHE_IALLS: |
| 9360 | case RISCV::TH_L2CACHE_CALL: |
| 9361 | case RISCV::TH_L2CACHE_CIALL: |
| 9362 | case RISCV::TH_L2CACHE_IALL: |
| 9363 | case RISCV::TH_SYNC: |
| 9364 | case RISCV::TH_SYNC_I: |
| 9365 | case RISCV::TH_SYNC_IS: |
| 9366 | case RISCV::TH_SYNC_S: |
| 9367 | case RISCV::UNIMP: |
| 9368 | case RISCV::WFI: |
| 9369 | case RISCV::WRS_NTO: |
| 9370 | case RISCV::WRS_STO: { |
| 9371 | break; |
| 9372 | } |
| 9373 | case RISCV::AIF_FSWG_PS: |
| 9374 | case RISCV::AIF_FSWL_PS: { |
| 9375 | switch (OpNum) { |
| 9376 | case 0: |
| 9377 | // op: fs3 |
| 9378 | return 7; |
| 9379 | case 1: |
| 9380 | // op: rs1 |
| 9381 | return 15; |
| 9382 | } |
| 9383 | break; |
| 9384 | } |
| 9385 | case RISCV::C_NOP_HINT: { |
| 9386 | switch (OpNum) { |
| 9387 | case 0: |
| 9388 | // op: imm |
| 9389 | return 2; |
| 9390 | } |
| 9391 | break; |
| 9392 | } |
| 9393 | case RISCV::QC_CLRINTI: |
| 9394 | case RISCV::QC_SETINTI: { |
| 9395 | switch (OpNum) { |
| 9396 | case 0: |
| 9397 | // op: imm10 |
| 9398 | return 15; |
| 9399 | } |
| 9400 | break; |
| 9401 | } |
| 9402 | case RISCV::QC_E_J: |
| 9403 | case RISCV::QC_E_JAL: { |
| 9404 | switch (OpNum) { |
| 9405 | case 0: |
| 9406 | // op: imm31 |
| 9407 | return 7; |
| 9408 | } |
| 9409 | break; |
| 9410 | } |
| 9411 | case RISCV::QC_SYNC: |
| 9412 | case RISCV::QC_SYNCR: |
| 9413 | case RISCV::QC_SYNCWF: |
| 9414 | case RISCV::QC_SYNCWL: { |
| 9415 | switch (OpNum) { |
| 9416 | case 0: |
| 9417 | // op: imm5 |
| 9418 | return 20; |
| 9419 | } |
| 9420 | break; |
| 9421 | } |
| 9422 | case RISCV::QC_PPUTCI: { |
| 9423 | switch (OpNum) { |
| 9424 | case 0: |
| 9425 | // op: imm8 |
| 9426 | return 20; |
| 9427 | } |
| 9428 | break; |
| 9429 | } |
| 9430 | case RISCV::CM_JALT: |
| 9431 | case RISCV::CM_JT: { |
| 9432 | switch (OpNum) { |
| 9433 | case 0: |
| 9434 | // op: index |
| 9435 | return 2; |
| 9436 | } |
| 9437 | break; |
| 9438 | } |
| 9439 | case RISCV::C_J: |
| 9440 | case RISCV::C_JAL: { |
| 9441 | switch (OpNum) { |
| 9442 | case 0: |
| 9443 | // op: offset |
| 9444 | return 2; |
| 9445 | } |
| 9446 | break; |
| 9447 | } |
| 9448 | case RISCV::InsnQC_EJ: { |
| 9449 | switch (OpNum) { |
| 9450 | case 0: |
| 9451 | // op: opcode |
| 9452 | return 0; |
| 9453 | case 1: |
| 9454 | // op: func3 |
| 9455 | return 12; |
| 9456 | case 2: |
| 9457 | // op: func2 |
| 9458 | return 15; |
| 9459 | case 3: |
| 9460 | // op: func5 |
| 9461 | return 20; |
| 9462 | case 4: |
| 9463 | // op: imm31 |
| 9464 | return 7; |
| 9465 | } |
| 9466 | break; |
| 9467 | } |
| 9468 | case RISCV::InsnQC_ES: { |
| 9469 | switch (OpNum) { |
| 9470 | case 0: |
| 9471 | // op: opcode |
| 9472 | return 0; |
| 9473 | case 1: |
| 9474 | // op: func3 |
| 9475 | return 12; |
| 9476 | case 2: |
| 9477 | // op: func2 |
| 9478 | return 30; |
| 9479 | case 4: |
| 9480 | // op: rs1 |
| 9481 | return 15; |
| 9482 | case 3: |
| 9483 | // op: rs2 |
| 9484 | return 20; |
| 9485 | case 5: |
| 9486 | // op: imm26 |
| 9487 | return 7; |
| 9488 | } |
| 9489 | break; |
| 9490 | } |
| 9491 | case RISCV::InsnQC_EB: { |
| 9492 | switch (OpNum) { |
| 9493 | case 0: |
| 9494 | // op: opcode |
| 9495 | return 0; |
| 9496 | case 1: |
| 9497 | // op: func3 |
| 9498 | return 12; |
| 9499 | case 2: |
| 9500 | // op: func5 |
| 9501 | return 20; |
| 9502 | case 3: |
| 9503 | // op: rs1 |
| 9504 | return 15; |
| 9505 | case 5: |
| 9506 | // op: imm12 |
| 9507 | return 7; |
| 9508 | case 4: |
| 9509 | // op: imm16 |
| 9510 | return 32; |
| 9511 | } |
| 9512 | break; |
| 9513 | } |
| 9514 | case RISCV::InsnS: { |
| 9515 | switch (OpNum) { |
| 9516 | case 0: |
| 9517 | // op: opcode |
| 9518 | return 0; |
| 9519 | case 1: |
| 9520 | // op: funct3 |
| 9521 | return 12; |
| 9522 | case 4: |
| 9523 | // op: imm12 |
| 9524 | return 7; |
| 9525 | case 2: |
| 9526 | // op: rs2 |
| 9527 | return 20; |
| 9528 | case 3: |
| 9529 | // op: rs1 |
| 9530 | return 15; |
| 9531 | } |
| 9532 | break; |
| 9533 | } |
| 9534 | case RISCV::InsnB: { |
| 9535 | switch (OpNum) { |
| 9536 | case 0: |
| 9537 | // op: opcode |
| 9538 | return 0; |
| 9539 | case 1: |
| 9540 | // op: funct3 |
| 9541 | return 12; |
| 9542 | case 4: |
| 9543 | // op: imm12 |
| 9544 | return 7; |
| 9545 | case 3: |
| 9546 | // op: rs2 |
| 9547 | return 20; |
| 9548 | case 2: |
| 9549 | // op: rs1 |
| 9550 | return 15; |
| 9551 | } |
| 9552 | break; |
| 9553 | } |
| 9554 | case RISCV::InsnCJ: { |
| 9555 | switch (OpNum) { |
| 9556 | case 0: |
| 9557 | // op: opcode |
| 9558 | return 0; |
| 9559 | case 1: |
| 9560 | // op: funct3 |
| 9561 | return 13; |
| 9562 | case 2: |
| 9563 | // op: imm11 |
| 9564 | return 2; |
| 9565 | } |
| 9566 | break; |
| 9567 | } |
| 9568 | case RISCV::InsnCSS: { |
| 9569 | switch (OpNum) { |
| 9570 | case 0: |
| 9571 | // op: opcode |
| 9572 | return 0; |
| 9573 | case 1: |
| 9574 | // op: funct3 |
| 9575 | return 13; |
| 9576 | case 3: |
| 9577 | // op: imm6 |
| 9578 | return 7; |
| 9579 | case 2: |
| 9580 | // op: rs2 |
| 9581 | return 2; |
| 9582 | } |
| 9583 | break; |
| 9584 | } |
| 9585 | case RISCV::InsnCB: { |
| 9586 | switch (OpNum) { |
| 9587 | case 0: |
| 9588 | // op: opcode |
| 9589 | return 0; |
| 9590 | case 1: |
| 9591 | // op: funct3 |
| 9592 | return 13; |
| 9593 | case 3: |
| 9594 | // op: imm8 |
| 9595 | return 2; |
| 9596 | case 2: |
| 9597 | // op: rs1 |
| 9598 | return 7; |
| 9599 | } |
| 9600 | break; |
| 9601 | } |
| 9602 | case RISCV::InsnCS: { |
| 9603 | switch (OpNum) { |
| 9604 | case 0: |
| 9605 | // op: opcode |
| 9606 | return 0; |
| 9607 | case 1: |
| 9608 | // op: funct3 |
| 9609 | return 13; |
| 9610 | case 4: |
| 9611 | // op: imm5 |
| 9612 | return 5; |
| 9613 | case 2: |
| 9614 | // op: rs2 |
| 9615 | return 2; |
| 9616 | case 3: |
| 9617 | // op: rs1 |
| 9618 | return 7; |
| 9619 | } |
| 9620 | break; |
| 9621 | } |
| 9622 | case RISCV::FENCE: { |
| 9623 | switch (OpNum) { |
| 9624 | case 0: |
| 9625 | // op: pred |
| 9626 | return 24; |
| 9627 | case 1: |
| 9628 | // op: succ |
| 9629 | return 20; |
| 9630 | } |
| 9631 | break; |
| 9632 | } |
| 9633 | case RISCV::C_FLD: |
| 9634 | case RISCV::C_FLW: |
| 9635 | case RISCV::C_LBU: |
| 9636 | case RISCV::C_LD: |
| 9637 | case RISCV::C_LD_RV32: |
| 9638 | case RISCV::C_LH: |
| 9639 | case RISCV::C_LHU: |
| 9640 | case RISCV::C_LH_INX: |
| 9641 | case RISCV::C_LW: |
| 9642 | case RISCV::C_LW_INX: |
| 9643 | case RISCV::QK_C_LBU: |
| 9644 | case RISCV::QK_C_LHU: { |
| 9645 | switch (OpNum) { |
| 9646 | case 0: |
| 9647 | // op: rd |
| 9648 | return 2; |
| 9649 | case 1: |
| 9650 | // op: rs1 |
| 9651 | return 7; |
| 9652 | case 2: |
| 9653 | // op: imm |
| 9654 | return 5; |
| 9655 | } |
| 9656 | break; |
| 9657 | } |
| 9658 | case RISCV::FLI_D: |
| 9659 | case RISCV::FLI_H: |
| 9660 | case RISCV::FLI_Q: |
| 9661 | case RISCV::FLI_S: { |
| 9662 | switch (OpNum) { |
| 9663 | case 0: |
| 9664 | // op: rd |
| 9665 | return 7; |
| 9666 | case 1: |
| 9667 | // op: imm |
| 9668 | return 15; |
| 9669 | } |
| 9670 | break; |
| 9671 | } |
| 9672 | case RISCV::QC_E_LI: { |
| 9673 | switch (OpNum) { |
| 9674 | case 0: |
| 9675 | // op: rd |
| 9676 | return 7; |
| 9677 | case 1: |
| 9678 | // op: imm |
| 9679 | return 16; |
| 9680 | } |
| 9681 | break; |
| 9682 | } |
| 9683 | case RISCV::PLI_H: |
| 9684 | case RISCV::PLI_W: |
| 9685 | case RISCV::PLUI_H: |
| 9686 | case RISCV::PLUI_W: { |
| 9687 | switch (OpNum) { |
| 9688 | case 0: |
| 9689 | // op: rd |
| 9690 | return 7; |
| 9691 | case 1: |
| 9692 | // op: imm10 |
| 9693 | return 15; |
| 9694 | } |
| 9695 | break; |
| 9696 | } |
| 9697 | case RISCV::PLI_B: { |
| 9698 | switch (OpNum) { |
| 9699 | case 0: |
| 9700 | // op: rd |
| 9701 | return 7; |
| 9702 | case 1: |
| 9703 | // op: imm8 |
| 9704 | return 16; |
| 9705 | } |
| 9706 | break; |
| 9707 | } |
| 9708 | case RISCV::AIF_FMVS_X_PS: |
| 9709 | case RISCV::AIF_FMVZ_X_PS: { |
| 9710 | switch (OpNum) { |
| 9711 | case 0: |
| 9712 | // op: rd |
| 9713 | return 7; |
| 9714 | case 1: |
| 9715 | // op: rs1 |
| 9716 | return 15; |
| 9717 | case 2: |
| 9718 | // op: idx |
| 9719 | return 20; |
| 9720 | } |
| 9721 | break; |
| 9722 | } |
| 9723 | case RISCV::AIF_FSWIZZ_PS: { |
| 9724 | switch (OpNum) { |
| 9725 | case 0: |
| 9726 | // op: rd |
| 9727 | return 7; |
| 9728 | case 1: |
| 9729 | // op: rs1 |
| 9730 | return 15; |
| 9731 | case 2: |
| 9732 | // op: imm |
| 9733 | return 12; |
| 9734 | } |
| 9735 | break; |
| 9736 | } |
| 9737 | case RISCV::QC_E_ADDI: |
| 9738 | case RISCV::QC_E_ANDI: |
| 9739 | case RISCV::QC_E_LB: |
| 9740 | case RISCV::QC_E_LBU: |
| 9741 | case RISCV::QC_E_LH: |
| 9742 | case RISCV::QC_E_LHU: |
| 9743 | case RISCV::QC_E_LW: |
| 9744 | case RISCV::QC_E_ORI: |
| 9745 | case RISCV::QC_E_XORI: { |
| 9746 | switch (OpNum) { |
| 9747 | case 0: |
| 9748 | // op: rd |
| 9749 | return 7; |
| 9750 | case 1: |
| 9751 | // op: rs1 |
| 9752 | return 15; |
| 9753 | case 2: |
| 9754 | // op: imm |
| 9755 | return 20; |
| 9756 | } |
| 9757 | break; |
| 9758 | } |
| 9759 | case RISCV::NDS_BFOS: |
| 9760 | case RISCV::NDS_BFOZ: { |
| 9761 | switch (OpNum) { |
| 9762 | case 0: |
| 9763 | // op: rd |
| 9764 | return 7; |
| 9765 | case 1: |
| 9766 | // op: rs1 |
| 9767 | return 15; |
| 9768 | case 2: |
| 9769 | // op: msb |
| 9770 | return 26; |
| 9771 | case 3: |
| 9772 | // op: lsb |
| 9773 | return 20; |
| 9774 | } |
| 9775 | break; |
| 9776 | } |
| 9777 | case RISCV::AIF_FCVT_PS_PW: |
| 9778 | case RISCV::AIF_FCVT_PS_PWU: |
| 9779 | case RISCV::AIF_FCVT_PWU_PS: |
| 9780 | case RISCV::AIF_FCVT_PW_PS: { |
| 9781 | switch (OpNum) { |
| 9782 | case 0: |
| 9783 | // op: rd |
| 9784 | return 7; |
| 9785 | case 1: |
| 9786 | // op: rs1 |
| 9787 | return 15; |
| 9788 | case 2: |
| 9789 | // op: rm |
| 9790 | return 12; |
| 9791 | } |
| 9792 | break; |
| 9793 | } |
| 9794 | case RISCV::AIF_FADD_PS: |
| 9795 | case RISCV::AIF_FDIV_PS: |
| 9796 | case RISCV::AIF_FMUL_PS: |
| 9797 | case RISCV::AIF_FSUB_PS: { |
| 9798 | switch (OpNum) { |
| 9799 | case 0: |
| 9800 | // op: rd |
| 9801 | return 7; |
| 9802 | case 1: |
| 9803 | // op: rs1 |
| 9804 | return 15; |
| 9805 | case 2: |
| 9806 | // op: rs2 |
| 9807 | return 20; |
| 9808 | case 3: |
| 9809 | // op: rm |
| 9810 | return 12; |
| 9811 | } |
| 9812 | break; |
| 9813 | } |
| 9814 | case RISCV::AIF_FMADD_PS: |
| 9815 | case RISCV::AIF_FMSUB_PS: |
| 9816 | case RISCV::AIF_FNMADD_PS: |
| 9817 | case RISCV::AIF_FNMSUB_PS: { |
| 9818 | switch (OpNum) { |
| 9819 | case 0: |
| 9820 | // op: rd |
| 9821 | return 7; |
| 9822 | case 1: |
| 9823 | // op: rs1 |
| 9824 | return 15; |
| 9825 | case 2: |
| 9826 | // op: rs2 |
| 9827 | return 20; |
| 9828 | case 3: |
| 9829 | // op: rs3 |
| 9830 | return 27; |
| 9831 | case 4: |
| 9832 | // op: rm |
| 9833 | return 12; |
| 9834 | } |
| 9835 | break; |
| 9836 | } |
| 9837 | case RISCV::AIF_FCMOV_PS: { |
| 9838 | switch (OpNum) { |
| 9839 | case 0: |
| 9840 | // op: rd |
| 9841 | return 7; |
| 9842 | case 1: |
| 9843 | // op: rs1 |
| 9844 | return 15; |
| 9845 | case 2: |
| 9846 | // op: rs2 |
| 9847 | return 20; |
| 9848 | case 3: |
| 9849 | // op: rs3 |
| 9850 | return 27; |
| 9851 | } |
| 9852 | break; |
| 9853 | } |
| 9854 | case RISCV::VSETIVLI: { |
| 9855 | switch (OpNum) { |
| 9856 | case 0: |
| 9857 | // op: rd |
| 9858 | return 7; |
| 9859 | case 1: |
| 9860 | // op: uimm |
| 9861 | return 15; |
| 9862 | case 2: |
| 9863 | // op: vtypei |
| 9864 | return 20; |
| 9865 | } |
| 9866 | break; |
| 9867 | } |
| 9868 | case RISCV::VFMV_F_S: |
| 9869 | case RISCV::VMV_X_S: { |
| 9870 | switch (OpNum) { |
| 9871 | case 0: |
| 9872 | // op: rd |
| 9873 | return 7; |
| 9874 | case 1: |
| 9875 | // op: vs2 |
| 9876 | return 20; |
| 9877 | } |
| 9878 | break; |
| 9879 | } |
| 9880 | case RISCV::VCPOP_M: |
| 9881 | case RISCV::VFIRST_M: { |
| 9882 | switch (OpNum) { |
| 9883 | case 0: |
| 9884 | // op: rd |
| 9885 | return 7; |
| 9886 | case 2: |
| 9887 | // op: vm |
| 9888 | return 25; |
| 9889 | case 1: |
| 9890 | // op: vs2 |
| 9891 | return 20; |
| 9892 | } |
| 9893 | break; |
| 9894 | } |
| 9895 | case RISCV::AIF_MOVA_X_M: |
| 9896 | case RISCV::QC_C_DIR: |
| 9897 | case RISCV::SSRDP: { |
| 9898 | switch (OpNum) { |
| 9899 | case 0: |
| 9900 | // op: rd |
| 9901 | return 7; |
| 9902 | } |
| 9903 | break; |
| 9904 | } |
| 9905 | case RISCV::PLI_DH: |
| 9906 | case RISCV::PLUI_DH: { |
| 9907 | switch (OpNum) { |
| 9908 | case 0: |
| 9909 | // op: rd |
| 9910 | return 8; |
| 9911 | case 1: |
| 9912 | // op: imm10 |
| 9913 | return 15; |
| 9914 | } |
| 9915 | break; |
| 9916 | } |
| 9917 | case RISCV::PLI_DB: { |
| 9918 | switch (OpNum) { |
| 9919 | case 0: |
| 9920 | // op: rd |
| 9921 | return 8; |
| 9922 | case 1: |
| 9923 | // op: imm8 |
| 9924 | return 16; |
| 9925 | } |
| 9926 | break; |
| 9927 | } |
| 9928 | case RISCV::SF_VTZERO_T: { |
| 9929 | switch (OpNum) { |
| 9930 | case 0: |
| 9931 | // op: rd |
| 9932 | return 8; |
| 9933 | } |
| 9934 | break; |
| 9935 | } |
| 9936 | case RISCV::QK_C_LBUSP: |
| 9937 | case RISCV::QK_C_LHUSP: |
| 9938 | case RISCV::QK_C_SBSP: |
| 9939 | case RISCV::QK_C_SHSP: { |
| 9940 | switch (OpNum) { |
| 9941 | case 0: |
| 9942 | // op: rd_rs2 |
| 9943 | return 2; |
| 9944 | case 2: |
| 9945 | // op: imm |
| 9946 | return 7; |
| 9947 | } |
| 9948 | break; |
| 9949 | } |
| 9950 | case RISCV::CM_POP: |
| 9951 | case RISCV::CM_POPRET: |
| 9952 | case RISCV::CM_POPRETZ: |
| 9953 | case RISCV::CM_PUSH: |
| 9954 | case RISCV::QC_CM_POP: |
| 9955 | case RISCV::QC_CM_POPRET: |
| 9956 | case RISCV::QC_CM_POPRETZ: |
| 9957 | case RISCV::QC_CM_PUSH: |
| 9958 | case RISCV::QC_CM_PUSHFP: { |
| 9959 | switch (OpNum) { |
| 9960 | case 0: |
| 9961 | // op: rlist |
| 9962 | return 4; |
| 9963 | case 1: |
| 9964 | // op: stackadj |
| 9965 | return 2; |
| 9966 | } |
| 9967 | break; |
| 9968 | } |
| 9969 | case RISCV::QC_E_BEQI: |
| 9970 | case RISCV::QC_E_BGEI: |
| 9971 | case RISCV::QC_E_BGEUI: |
| 9972 | case RISCV::QC_E_BLTI: |
| 9973 | case RISCV::QC_E_BLTUI: |
| 9974 | case RISCV::QC_E_BNEI: { |
| 9975 | switch (OpNum) { |
| 9976 | case 0: |
| 9977 | // op: rs1 |
| 9978 | return 15; |
| 9979 | case 1: |
| 9980 | // op: imm16 |
| 9981 | return 32; |
| 9982 | case 2: |
| 9983 | // op: imm12 |
| 9984 | return 7; |
| 9985 | } |
| 9986 | break; |
| 9987 | } |
| 9988 | case RISCV::AIF_MOVA_M_X: |
| 9989 | case RISCV::CBO_CLEAN: |
| 9990 | case RISCV::CBO_FLUSH: |
| 9991 | case RISCV::CBO_INVAL: |
| 9992 | case RISCV::CBO_ZERO: |
| 9993 | case RISCV::SF_CDISCARD_D_L1: |
| 9994 | case RISCV::SF_CFLUSH_D_L1: |
| 9995 | case RISCV::SSPOPCHK: |
| 9996 | case RISCV::TH_DCACHE_CIPA: |
| 9997 | case RISCV::TH_DCACHE_CISW: |
| 9998 | case RISCV::TH_DCACHE_CIVA: |
| 9999 | case RISCV::TH_DCACHE_CPA: |
| 10000 | case RISCV::TH_DCACHE_CPAL1: |
| 10001 | case RISCV::TH_DCACHE_CSW: |
| 10002 | case RISCV::TH_DCACHE_CVA: |
| 10003 | case RISCV::TH_DCACHE_CVAL1: |
| 10004 | case RISCV::TH_DCACHE_IPA: |
| 10005 | case RISCV::TH_DCACHE_ISW: |
| 10006 | case RISCV::TH_DCACHE_IVA: |
| 10007 | case RISCV::TH_ICACHE_IPA: |
| 10008 | case RISCV::TH_ICACHE_IVA: { |
| 10009 | switch (OpNum) { |
| 10010 | case 0: |
| 10011 | // op: rs1 |
| 10012 | return 15; |
| 10013 | } |
| 10014 | break; |
| 10015 | } |
| 10016 | case RISCV::C_MV: { |
| 10017 | switch (OpNum) { |
| 10018 | case 0: |
| 10019 | // op: rs1 |
| 10020 | return 7; |
| 10021 | case 1: |
| 10022 | // op: rs2 |
| 10023 | return 2; |
| 10024 | } |
| 10025 | break; |
| 10026 | } |
| 10027 | case RISCV::C_JALR: |
| 10028 | case RISCV::C_JR: |
| 10029 | case RISCV::QC_C_CLRINT: |
| 10030 | case RISCV::QC_C_EIR: |
| 10031 | case RISCV::QC_C_SETINT: { |
| 10032 | switch (OpNum) { |
| 10033 | case 0: |
| 10034 | // op: rs1 |
| 10035 | return 7; |
| 10036 | } |
| 10037 | break; |
| 10038 | } |
| 10039 | case RISCV::AIF_SBG: |
| 10040 | case RISCV::AIF_SBL: |
| 10041 | case RISCV::AIF_SHG: |
| 10042 | case RISCV::AIF_SHL: |
| 10043 | case RISCV::HSV_B: |
| 10044 | case RISCV::HSV_D: |
| 10045 | case RISCV::HSV_H: |
| 10046 | case RISCV::HSV_W: |
| 10047 | case RISCV::SB_AQRL: |
| 10048 | case RISCV::SB_RL: |
| 10049 | case RISCV::SD_AQRL: |
| 10050 | case RISCV::SD_RL: |
| 10051 | case RISCV::SF_VLTE16: |
| 10052 | case RISCV::SF_VLTE32: |
| 10053 | case RISCV::SF_VLTE64: |
| 10054 | case RISCV::SF_VLTE8: |
| 10055 | case RISCV::SF_VSTE16: |
| 10056 | case RISCV::SF_VSTE32: |
| 10057 | case RISCV::SF_VSTE64: |
| 10058 | case RISCV::SF_VSTE8: |
| 10059 | case RISCV::SH_AQRL: |
| 10060 | case RISCV::SH_RL: |
| 10061 | case RISCV::SW_AQRL: |
| 10062 | case RISCV::SW_RL: { |
| 10063 | switch (OpNum) { |
| 10064 | case 0: |
| 10065 | // op: rs2 |
| 10066 | return 20; |
| 10067 | case 1: |
| 10068 | // op: rs1 |
| 10069 | return 15; |
| 10070 | } |
| 10071 | break; |
| 10072 | } |
| 10073 | case RISCV::SSPUSH: { |
| 10074 | switch (OpNum) { |
| 10075 | case 0: |
| 10076 | // op: rs2 |
| 10077 | return 20; |
| 10078 | } |
| 10079 | break; |
| 10080 | } |
| 10081 | case RISCV::C_FSD: |
| 10082 | case RISCV::C_FSW: |
| 10083 | case RISCV::C_SB: |
| 10084 | case RISCV::C_SD: |
| 10085 | case RISCV::C_SD_RV32: |
| 10086 | case RISCV::C_SH: |
| 10087 | case RISCV::C_SH_INX: |
| 10088 | case RISCV::C_SW: |
| 10089 | case RISCV::C_SW_INX: |
| 10090 | case RISCV::QK_C_SB: |
| 10091 | case RISCV::QK_C_SH: { |
| 10092 | switch (OpNum) { |
| 10093 | case 0: |
| 10094 | // op: rs2 |
| 10095 | return 2; |
| 10096 | case 1: |
| 10097 | // op: rs1 |
| 10098 | return 7; |
| 10099 | case 2: |
| 10100 | // op: imm |
| 10101 | return 5; |
| 10102 | } |
| 10103 | break; |
| 10104 | } |
| 10105 | case RISCV::QC_C_SYNC: |
| 10106 | case RISCV::QC_C_SYNCR: |
| 10107 | case RISCV::QC_C_SYNCWF: |
| 10108 | case RISCV::QC_C_SYNCWL: { |
| 10109 | switch (OpNum) { |
| 10110 | case 0: |
| 10111 | // op: slist |
| 10112 | return 7; |
| 10113 | } |
| 10114 | break; |
| 10115 | } |
| 10116 | case RISCV::Insn16: |
| 10117 | case RISCV::Insn32: |
| 10118 | case RISCV::Insn48: |
| 10119 | case RISCV::Insn64: { |
| 10120 | switch (OpNum) { |
| 10121 | case 0: |
| 10122 | // op: value |
| 10123 | return 0; |
| 10124 | } |
| 10125 | break; |
| 10126 | } |
| 10127 | case RISCV::VMV_V_I: { |
| 10128 | switch (OpNum) { |
| 10129 | case 0: |
| 10130 | // op: vd |
| 10131 | return 7; |
| 10132 | case 1: |
| 10133 | // op: imm |
| 10134 | return 15; |
| 10135 | } |
| 10136 | break; |
| 10137 | } |
| 10138 | case RISCV::VFMV_V_F: |
| 10139 | case RISCV::VMV_V_X: { |
| 10140 | switch (OpNum) { |
| 10141 | case 0: |
| 10142 | // op: vd |
| 10143 | return 7; |
| 10144 | case 1: |
| 10145 | // op: rs1 |
| 10146 | return 15; |
| 10147 | } |
| 10148 | break; |
| 10149 | } |
| 10150 | case RISCV::VID_V: { |
| 10151 | switch (OpNum) { |
| 10152 | case 0: |
| 10153 | // op: vd |
| 10154 | return 7; |
| 10155 | case 1: |
| 10156 | // op: vm |
| 10157 | return 25; |
| 10158 | } |
| 10159 | break; |
| 10160 | } |
| 10161 | case RISCV::VMV_V_V: { |
| 10162 | switch (OpNum) { |
| 10163 | case 0: |
| 10164 | // op: vd |
| 10165 | return 7; |
| 10166 | case 1: |
| 10167 | // op: vs1 |
| 10168 | return 15; |
| 10169 | } |
| 10170 | break; |
| 10171 | } |
| 10172 | case RISCV::VADC_VIM: |
| 10173 | case RISCV::VAESKF1_VI: |
| 10174 | case RISCV::VMADC_VI: |
| 10175 | case RISCV::VMADC_VIM: |
| 10176 | case RISCV::VMERGE_VIM: |
| 10177 | case RISCV::VSM4K_VI: { |
| 10178 | switch (OpNum) { |
| 10179 | case 0: |
| 10180 | // op: vd |
| 10181 | return 7; |
| 10182 | case 1: |
| 10183 | // op: vs2 |
| 10184 | return 20; |
| 10185 | case 2: |
| 10186 | // op: imm |
| 10187 | return 15; |
| 10188 | } |
| 10189 | break; |
| 10190 | } |
| 10191 | case RISCV::VADC_VXM: |
| 10192 | case RISCV::VFMERGE_VFM: |
| 10193 | case RISCV::VMADC_VX: |
| 10194 | case RISCV::VMADC_VXM: |
| 10195 | case RISCV::VMERGE_VXM: |
| 10196 | case RISCV::VMSBC_VX: |
| 10197 | case RISCV::VMSBC_VXM: |
| 10198 | case RISCV::VSBC_VXM: { |
| 10199 | switch (OpNum) { |
| 10200 | case 0: |
| 10201 | // op: vd |
| 10202 | return 7; |
| 10203 | case 1: |
| 10204 | // op: vs2 |
| 10205 | return 20; |
| 10206 | case 2: |
| 10207 | // op: rs1 |
| 10208 | return 15; |
| 10209 | } |
| 10210 | break; |
| 10211 | } |
| 10212 | case RISCV::VADC_VVM: |
| 10213 | case RISCV::VCOMPRESS_VM: |
| 10214 | case RISCV::VMADC_VV: |
| 10215 | case RISCV::VMADC_VVM: |
| 10216 | case RISCV::VMANDN_MM: |
| 10217 | case RISCV::VMAND_MM: |
| 10218 | case RISCV::VMERGE_VVM: |
| 10219 | case RISCV::VMNAND_MM: |
| 10220 | case RISCV::VMNOR_MM: |
| 10221 | case RISCV::VMORN_MM: |
| 10222 | case RISCV::VMOR_MM: |
| 10223 | case RISCV::VMSBC_VV: |
| 10224 | case RISCV::VMSBC_VVM: |
| 10225 | case RISCV::VMXNOR_MM: |
| 10226 | case RISCV::VMXOR_MM: |
| 10227 | case RISCV::VSBC_VVM: |
| 10228 | case RISCV::VSM3ME_VV: { |
| 10229 | switch (OpNum) { |
| 10230 | case 0: |
| 10231 | // op: vd |
| 10232 | return 7; |
| 10233 | case 1: |
| 10234 | // op: vs2 |
| 10235 | return 20; |
| 10236 | case 2: |
| 10237 | // op: vs1 |
| 10238 | return 15; |
| 10239 | } |
| 10240 | break; |
| 10241 | } |
| 10242 | case RISCV::VMV1R_V: |
| 10243 | case RISCV::VMV2R_V: |
| 10244 | case RISCV::VMV4R_V: |
| 10245 | case RISCV::VMV8R_V: { |
| 10246 | switch (OpNum) { |
| 10247 | case 0: |
| 10248 | // op: vd |
| 10249 | return 7; |
| 10250 | case 1: |
| 10251 | // op: vs2 |
| 10252 | return 20; |
| 10253 | } |
| 10254 | break; |
| 10255 | } |
| 10256 | case RISCV::SF_VFEXPA_V: |
| 10257 | case RISCV::SF_VFEXP_V: |
| 10258 | case RISCV::VABS_V: |
| 10259 | case RISCV::VBREV8_V: |
| 10260 | case RISCV::VBREV_V: |
| 10261 | case RISCV::VCLZ_V: |
| 10262 | case RISCV::VCPOP_V: |
| 10263 | case RISCV::VCTZ_V: |
| 10264 | case RISCV::VFCLASS_V: |
| 10265 | case RISCV::VFCVT_F_XU_V: |
| 10266 | case RISCV::VFCVT_F_X_V: |
| 10267 | case RISCV::VFCVT_RTZ_XU_F_V: |
| 10268 | case RISCV::VFCVT_RTZ_X_F_V: |
| 10269 | case RISCV::VFCVT_XU_F_V: |
| 10270 | case RISCV::VFCVT_X_F_V: |
| 10271 | case RISCV::VFNCVTBF16_F_F_W: |
| 10272 | case RISCV::VFNCVTBF16_SAT_F_F_W: |
| 10273 | case RISCV::VFNCVT_F_F_Q: |
| 10274 | case RISCV::VFNCVT_F_F_W: |
| 10275 | case RISCV::VFNCVT_F_XU_W: |
| 10276 | case RISCV::VFNCVT_F_X_W: |
| 10277 | case RISCV::VFNCVT_ROD_F_F_W: |
| 10278 | case RISCV::VFNCVT_RTZ_XU_F_W: |
| 10279 | case RISCV::VFNCVT_RTZ_X_F_W: |
| 10280 | case RISCV::VFNCVT_SAT_F_F_Q: |
| 10281 | case RISCV::VFNCVT_XU_F_W: |
| 10282 | case RISCV::VFNCVT_X_F_W: |
| 10283 | case RISCV::VFREC7_V: |
| 10284 | case RISCV::VFRSQRT7_V: |
| 10285 | case RISCV::VFSQRT_V: |
| 10286 | case RISCV::VFWCVTBF16_F_F_V: |
| 10287 | case RISCV::VFWCVT_F_F_V: |
| 10288 | case RISCV::VFWCVT_F_XU_V: |
| 10289 | case RISCV::VFWCVT_F_X_V: |
| 10290 | case RISCV::VFWCVT_RTZ_XU_F_V: |
| 10291 | case RISCV::VFWCVT_RTZ_X_F_V: |
| 10292 | case RISCV::VFWCVT_XU_F_V: |
| 10293 | case RISCV::VFWCVT_X_F_V: |
| 10294 | case RISCV::VIOTA_M: |
| 10295 | case RISCV::VMSBF_M: |
| 10296 | case RISCV::VMSIF_M: |
| 10297 | case RISCV::VMSOF_M: |
| 10298 | case RISCV::VREV8_V: |
| 10299 | case RISCV::VSEXT_VF2: |
| 10300 | case RISCV::VSEXT_VF4: |
| 10301 | case RISCV::VSEXT_VF8: |
| 10302 | case RISCV::VUNZIPE_V: |
| 10303 | case RISCV::VUNZIPO_V: |
| 10304 | case RISCV::VZEXT_VF2: |
| 10305 | case RISCV::VZEXT_VF4: |
| 10306 | case RISCV::VZEXT_VF8: { |
| 10307 | switch (OpNum) { |
| 10308 | case 0: |
| 10309 | // op: vd |
| 10310 | return 7; |
| 10311 | case 2: |
| 10312 | // op: vm |
| 10313 | return 25; |
| 10314 | case 1: |
| 10315 | // op: vs2 |
| 10316 | return 20; |
| 10317 | } |
| 10318 | break; |
| 10319 | } |
| 10320 | case RISCV::VADD_VI: |
| 10321 | case RISCV::VAND_VI: |
| 10322 | case RISCV::VMSEQ_VI: |
| 10323 | case RISCV::VMSGTU_VI: |
| 10324 | case RISCV::VMSGT_VI: |
| 10325 | case RISCV::VMSLEU_VI: |
| 10326 | case RISCV::VMSLE_VI: |
| 10327 | case RISCV::VMSNE_VI: |
| 10328 | case RISCV::VNCLIPU_WI: |
| 10329 | case RISCV::VNCLIP_WI: |
| 10330 | case RISCV::VNSRA_WI: |
| 10331 | case RISCV::VNSRL_WI: |
| 10332 | case RISCV::VOR_VI: |
| 10333 | case RISCV::VRGATHER_VI: |
| 10334 | case RISCV::VROR_VI: |
| 10335 | case RISCV::VRSUB_VI: |
| 10336 | case RISCV::VSADDU_VI: |
| 10337 | case RISCV::VSADD_VI: |
| 10338 | case RISCV::VSLIDEDOWN_VI: |
| 10339 | case RISCV::VSLIDEUP_VI: |
| 10340 | case RISCV::VSLL_VI: |
| 10341 | case RISCV::VSRA_VI: |
| 10342 | case RISCV::VSRL_VI: |
| 10343 | case RISCV::VSSRA_VI: |
| 10344 | case RISCV::VSSRL_VI: |
| 10345 | case RISCV::VWSLL_VI: |
| 10346 | case RISCV::VXOR_VI: { |
| 10347 | switch (OpNum) { |
| 10348 | case 0: |
| 10349 | // op: vd |
| 10350 | return 7; |
| 10351 | case 3: |
| 10352 | // op: vm |
| 10353 | return 25; |
| 10354 | case 1: |
| 10355 | // op: vs2 |
| 10356 | return 20; |
| 10357 | case 2: |
| 10358 | // op: imm |
| 10359 | return 15; |
| 10360 | } |
| 10361 | break; |
| 10362 | } |
| 10363 | case RISCV::SF_VFNRCLIP_XU_F_QF: |
| 10364 | case RISCV::SF_VFNRCLIP_X_F_QF: |
| 10365 | case RISCV::VAADDU_VX: |
| 10366 | case RISCV::VAADD_VX: |
| 10367 | case RISCV::VADD_VX: |
| 10368 | case RISCV::VANDN_VX: |
| 10369 | case RISCV::VAND_VX: |
| 10370 | case RISCV::VASUBU_VX: |
| 10371 | case RISCV::VASUB_VX: |
| 10372 | case RISCV::VCLMULH_VX: |
| 10373 | case RISCV::VCLMUL_VX: |
| 10374 | case RISCV::VDIVU_VX: |
| 10375 | case RISCV::VDIV_VX: |
| 10376 | case RISCV::VFADD_VF: |
| 10377 | case RISCV::VFDIV_VF: |
| 10378 | case RISCV::VFMAX_VF: |
| 10379 | case RISCV::VFMIN_VF: |
| 10380 | case RISCV::VFMUL_VF: |
| 10381 | case RISCV::VFRDIV_VF: |
| 10382 | case RISCV::VFRSUB_VF: |
| 10383 | case RISCV::VFSGNJN_VF: |
| 10384 | case RISCV::VFSGNJX_VF: |
| 10385 | case RISCV::VFSGNJ_VF: |
| 10386 | case RISCV::VFSLIDE1DOWN_VF: |
| 10387 | case RISCV::VFSLIDE1UP_VF: |
| 10388 | case RISCV::VFSUB_VF: |
| 10389 | case RISCV::VFWADD_VF: |
| 10390 | case RISCV::VFWADD_WF: |
| 10391 | case RISCV::VFWMUL_VF: |
| 10392 | case RISCV::VFWSUB_VF: |
| 10393 | case RISCV::VFWSUB_WF: |
| 10394 | case RISCV::VMAXU_VX: |
| 10395 | case RISCV::VMAX_VX: |
| 10396 | case RISCV::VMFEQ_VF: |
| 10397 | case RISCV::VMFGE_VF: |
| 10398 | case RISCV::VMFGT_VF: |
| 10399 | case RISCV::VMFLE_VF: |
| 10400 | case RISCV::VMFLT_VF: |
| 10401 | case RISCV::VMFNE_VF: |
| 10402 | case RISCV::VMINU_VX: |
| 10403 | case RISCV::VMIN_VX: |
| 10404 | case RISCV::VMSEQ_VX: |
| 10405 | case RISCV::VMSGTU_VX: |
| 10406 | case RISCV::VMSGT_VX: |
| 10407 | case RISCV::VMSLEU_VX: |
| 10408 | case RISCV::VMSLE_VX: |
| 10409 | case RISCV::VMSLTU_VX: |
| 10410 | case RISCV::VMSLT_VX: |
| 10411 | case RISCV::VMSNE_VX: |
| 10412 | case RISCV::VMULHSU_VX: |
| 10413 | case RISCV::VMULHU_VX: |
| 10414 | case RISCV::VMULH_VX: |
| 10415 | case RISCV::VMUL_VX: |
| 10416 | case RISCV::VNCLIPU_WX: |
| 10417 | case RISCV::VNCLIP_WX: |
| 10418 | case RISCV::VNSRA_WX: |
| 10419 | case RISCV::VNSRL_WX: |
| 10420 | case RISCV::VOR_VX: |
| 10421 | case RISCV::VREMU_VX: |
| 10422 | case RISCV::VREM_VX: |
| 10423 | case RISCV::VRGATHER_VX: |
| 10424 | case RISCV::VROL_VX: |
| 10425 | case RISCV::VROR_VX: |
| 10426 | case RISCV::VRSUB_VX: |
| 10427 | case RISCV::VSADDU_VX: |
| 10428 | case RISCV::VSADD_VX: |
| 10429 | case RISCV::VSLIDE1DOWN_VX: |
| 10430 | case RISCV::VSLIDE1UP_VX: |
| 10431 | case RISCV::VSLIDEDOWN_VX: |
| 10432 | case RISCV::VSLIDEUP_VX: |
| 10433 | case RISCV::VSLL_VX: |
| 10434 | case RISCV::VSMUL_VX: |
| 10435 | case RISCV::VSRA_VX: |
| 10436 | case RISCV::VSRL_VX: |
| 10437 | case RISCV::VSSRA_VX: |
| 10438 | case RISCV::VSSRL_VX: |
| 10439 | case RISCV::VSSUBU_VX: |
| 10440 | case RISCV::VSSUB_VX: |
| 10441 | case RISCV::VSUB_VX: |
| 10442 | case RISCV::VWADDU_VX: |
| 10443 | case RISCV::VWADDU_WX: |
| 10444 | case RISCV::VWADD_VX: |
| 10445 | case RISCV::VWADD_WX: |
| 10446 | case RISCV::VWMULSU_VX: |
| 10447 | case RISCV::VWMULU_VX: |
| 10448 | case RISCV::VWMUL_VX: |
| 10449 | case RISCV::VWSLL_VX: |
| 10450 | case RISCV::VWSUBU_VX: |
| 10451 | case RISCV::VWSUBU_WX: |
| 10452 | case RISCV::VWSUB_VX: |
| 10453 | case RISCV::VWSUB_WX: |
| 10454 | case RISCV::VXOR_VX: { |
| 10455 | switch (OpNum) { |
| 10456 | case 0: |
| 10457 | // op: vd |
| 10458 | return 7; |
| 10459 | case 3: |
| 10460 | // op: vm |
| 10461 | return 25; |
| 10462 | case 1: |
| 10463 | // op: vs2 |
| 10464 | return 20; |
| 10465 | case 2: |
| 10466 | // op: rs1 |
| 10467 | return 15; |
| 10468 | } |
| 10469 | break; |
| 10470 | } |
| 10471 | case RISCV::RI_VUNZIP2A_VV: |
| 10472 | case RISCV::RI_VUNZIP2B_VV: |
| 10473 | case RISCV::RI_VZIP2A_VV: |
| 10474 | case RISCV::RI_VZIP2B_VV: |
| 10475 | case RISCV::RI_VZIPEVEN_VV: |
| 10476 | case RISCV::RI_VZIPODD_VV: |
| 10477 | case RISCV::VAADDU_VV: |
| 10478 | case RISCV::VAADD_VV: |
| 10479 | case RISCV::VABDU_VV: |
| 10480 | case RISCV::VABD_VV: |
| 10481 | case RISCV::VADD_VV: |
| 10482 | case RISCV::VANDN_VV: |
| 10483 | case RISCV::VAND_VV: |
| 10484 | case RISCV::VASUBU_VV: |
| 10485 | case RISCV::VASUB_VV: |
| 10486 | case RISCV::VCLMULH_VV: |
| 10487 | case RISCV::VCLMUL_VV: |
| 10488 | case RISCV::VDIVU_VV: |
| 10489 | case RISCV::VDIV_VV: |
| 10490 | case RISCV::VFADD_VV: |
| 10491 | case RISCV::VFDIV_VV: |
| 10492 | case RISCV::VFMAX_VV: |
| 10493 | case RISCV::VFMIN_VV: |
| 10494 | case RISCV::VFMUL_VV: |
| 10495 | case RISCV::VFREDMAX_VS: |
| 10496 | case RISCV::VFREDMIN_VS: |
| 10497 | case RISCV::VFREDOSUM_VS: |
| 10498 | case RISCV::VFREDUSUM_VS: |
| 10499 | case RISCV::VFSGNJN_VV: |
| 10500 | case RISCV::VFSGNJX_VV: |
| 10501 | case RISCV::VFSGNJ_VV: |
| 10502 | case RISCV::VFSUB_VV: |
| 10503 | case RISCV::VFWADD_VV: |
| 10504 | case RISCV::VFWADD_WV: |
| 10505 | case RISCV::VFWMUL_VV: |
| 10506 | case RISCV::VFWREDOSUM_VS: |
| 10507 | case RISCV::VFWREDUSUM_VS: |
| 10508 | case RISCV::VFWSUB_VV: |
| 10509 | case RISCV::VFWSUB_WV: |
| 10510 | case RISCV::VMAXU_VV: |
| 10511 | case RISCV::VMAX_VV: |
| 10512 | case RISCV::VMFEQ_VV: |
| 10513 | case RISCV::VMFLE_VV: |
| 10514 | case RISCV::VMFLT_VV: |
| 10515 | case RISCV::VMFNE_VV: |
| 10516 | case RISCV::VMINU_VV: |
| 10517 | case RISCV::VMIN_VV: |
| 10518 | case RISCV::VMSEQ_VV: |
| 10519 | case RISCV::VMSLEU_VV: |
| 10520 | case RISCV::VMSLE_VV: |
| 10521 | case RISCV::VMSLTU_VV: |
| 10522 | case RISCV::VMSLT_VV: |
| 10523 | case RISCV::VMSNE_VV: |
| 10524 | case RISCV::VMULHSU_VV: |
| 10525 | case RISCV::VMULHU_VV: |
| 10526 | case RISCV::VMULH_VV: |
| 10527 | case RISCV::VMUL_VV: |
| 10528 | case RISCV::VNCLIPU_WV: |
| 10529 | case RISCV::VNCLIP_WV: |
| 10530 | case RISCV::VNSRA_WV: |
| 10531 | case RISCV::VNSRL_WV: |
| 10532 | case RISCV::VOR_VV: |
| 10533 | case RISCV::VPAIRE_VV: |
| 10534 | case RISCV::VPAIRO_VV: |
| 10535 | case RISCV::VREDAND_VS: |
| 10536 | case RISCV::VREDMAXU_VS: |
| 10537 | case RISCV::VREDMAX_VS: |
| 10538 | case RISCV::VREDMINU_VS: |
| 10539 | case RISCV::VREDMIN_VS: |
| 10540 | case RISCV::VREDOR_VS: |
| 10541 | case RISCV::VREDSUM_VS: |
| 10542 | case RISCV::VREDXOR_VS: |
| 10543 | case RISCV::VREMU_VV: |
| 10544 | case RISCV::VREM_VV: |
| 10545 | case RISCV::VRGATHEREI16_VV: |
| 10546 | case RISCV::VRGATHER_VV: |
| 10547 | case RISCV::VROL_VV: |
| 10548 | case RISCV::VROR_VV: |
| 10549 | case RISCV::VSADDU_VV: |
| 10550 | case RISCV::VSADD_VV: |
| 10551 | case RISCV::VSLL_VV: |
| 10552 | case RISCV::VSMUL_VV: |
| 10553 | case RISCV::VSRA_VV: |
| 10554 | case RISCV::VSRL_VV: |
| 10555 | case RISCV::VSSRA_VV: |
| 10556 | case RISCV::VSSRL_VV: |
| 10557 | case RISCV::VSSUBU_VV: |
| 10558 | case RISCV::VSSUB_VV: |
| 10559 | case RISCV::VSUB_VV: |
| 10560 | case RISCV::VWABDAU_VV: |
| 10561 | case RISCV::VWABDA_VV: |
| 10562 | case RISCV::VWADDU_VV: |
| 10563 | case RISCV::VWADDU_WV: |
| 10564 | case RISCV::VWADD_VV: |
| 10565 | case RISCV::VWADD_WV: |
| 10566 | case RISCV::VWMULSU_VV: |
| 10567 | case RISCV::VWMULU_VV: |
| 10568 | case RISCV::VWMUL_VV: |
| 10569 | case RISCV::VWREDSUMU_VS: |
| 10570 | case RISCV::VWREDSUM_VS: |
| 10571 | case RISCV::VWSLL_VV: |
| 10572 | case RISCV::VWSUBU_VV: |
| 10573 | case RISCV::VWSUBU_WV: |
| 10574 | case RISCV::VWSUB_VV: |
| 10575 | case RISCV::VWSUB_WV: |
| 10576 | case RISCV::VXOR_VV: |
| 10577 | case RISCV::VZIP_VV: { |
| 10578 | switch (OpNum) { |
| 10579 | case 0: |
| 10580 | // op: vd |
| 10581 | return 7; |
| 10582 | case 3: |
| 10583 | // op: vm |
| 10584 | return 25; |
| 10585 | case 1: |
| 10586 | // op: vs2 |
| 10587 | return 20; |
| 10588 | case 2: |
| 10589 | // op: vs1 |
| 10590 | return 15; |
| 10591 | } |
| 10592 | break; |
| 10593 | } |
| 10594 | case RISCV::RI_VZERO: { |
| 10595 | switch (OpNum) { |
| 10596 | case 0: |
| 10597 | // op: vd |
| 10598 | return 7; |
| 10599 | } |
| 10600 | break; |
| 10601 | } |
| 10602 | case RISCV::C_LI: |
| 10603 | case RISCV::C_LUI: { |
| 10604 | switch (OpNum) { |
| 10605 | case 1: |
| 10606 | // op: imm |
| 10607 | return 2; |
| 10608 | case 0: |
| 10609 | // op: rd |
| 10610 | return 7; |
| 10611 | } |
| 10612 | break; |
| 10613 | } |
| 10614 | case RISCV::C_BEQZ: |
| 10615 | case RISCV::C_BNEZ: { |
| 10616 | switch (OpNum) { |
| 10617 | case 1: |
| 10618 | // op: imm |
| 10619 | return 2; |
| 10620 | case 0: |
| 10621 | // op: rs1 |
| 10622 | return 7; |
| 10623 | } |
| 10624 | break; |
| 10625 | } |
| 10626 | case RISCV::PREFETCH_I: |
| 10627 | case RISCV::PREFETCH_R: |
| 10628 | case RISCV::PREFETCH_W: { |
| 10629 | switch (OpNum) { |
| 10630 | case 1: |
| 10631 | // op: imm12 |
| 10632 | return 25; |
| 10633 | case 0: |
| 10634 | // op: rs1 |
| 10635 | return 15; |
| 10636 | } |
| 10637 | break; |
| 10638 | } |
| 10639 | case RISCV::AIF_FSQ2: |
| 10640 | case RISCV::AIF_FSW_PS: { |
| 10641 | switch (OpNum) { |
| 10642 | case 1: |
| 10643 | // op: imm12 |
| 10644 | return 7; |
| 10645 | case 0: |
| 10646 | // op: rs2 |
| 10647 | return 20; |
| 10648 | case 2: |
| 10649 | // op: rs1 |
| 10650 | return 15; |
| 10651 | } |
| 10652 | break; |
| 10653 | } |
| 10654 | case RISCV::NDS_LDGP: |
| 10655 | case RISCV::NDS_LHGP: |
| 10656 | case RISCV::NDS_LHUGP: |
| 10657 | case RISCV::NDS_LWGP: |
| 10658 | case RISCV::NDS_LWUGP: { |
| 10659 | switch (OpNum) { |
| 10660 | case 1: |
| 10661 | // op: imm17 |
| 10662 | return 15; |
| 10663 | case 0: |
| 10664 | // op: rd |
| 10665 | return 7; |
| 10666 | } |
| 10667 | break; |
| 10668 | } |
| 10669 | case RISCV::NDS_SDGP: |
| 10670 | case RISCV::NDS_SHGP: |
| 10671 | case RISCV::NDS_SWGP: { |
| 10672 | switch (OpNum) { |
| 10673 | case 1: |
| 10674 | // op: imm17 |
| 10675 | return 7; |
| 10676 | case 0: |
| 10677 | // op: rs2 |
| 10678 | return 20; |
| 10679 | } |
| 10680 | break; |
| 10681 | } |
| 10682 | case RISCV::NDS_ADDIGP: |
| 10683 | case RISCV::NDS_LBGP: |
| 10684 | case RISCV::NDS_LBUGP: { |
| 10685 | switch (OpNum) { |
| 10686 | case 1: |
| 10687 | // op: imm18 |
| 10688 | return 14; |
| 10689 | case 0: |
| 10690 | // op: rd |
| 10691 | return 7; |
| 10692 | } |
| 10693 | break; |
| 10694 | } |
| 10695 | case RISCV::NDS_SBGP: { |
| 10696 | switch (OpNum) { |
| 10697 | case 1: |
| 10698 | // op: imm18 |
| 10699 | return 7; |
| 10700 | case 0: |
| 10701 | // op: rs2 |
| 10702 | return 20; |
| 10703 | } |
| 10704 | break; |
| 10705 | } |
| 10706 | case RISCV::AIF_FBCI_PI: |
| 10707 | case RISCV::AIF_FBCI_PS: |
| 10708 | case RISCV::AUIPC: |
| 10709 | case RISCV::JAL: |
| 10710 | case RISCV::LUI: |
| 10711 | case RISCV::QC_LI: { |
| 10712 | switch (OpNum) { |
| 10713 | case 1: |
| 10714 | // op: imm20 |
| 10715 | return 12; |
| 10716 | case 0: |
| 10717 | // op: rd |
| 10718 | return 7; |
| 10719 | } |
| 10720 | break; |
| 10721 | } |
| 10722 | case RISCV::MIPS_PREF: { |
| 10723 | switch (OpNum) { |
| 10724 | case 1: |
| 10725 | // op: imm9 |
| 10726 | return 20; |
| 10727 | case 0: |
| 10728 | // op: rs1 |
| 10729 | return 15; |
| 10730 | case 2: |
| 10731 | // op: hint |
| 10732 | return 7; |
| 10733 | } |
| 10734 | break; |
| 10735 | } |
| 10736 | case RISCV::InsnQC_EAI: { |
| 10737 | switch (OpNum) { |
| 10738 | case 1: |
| 10739 | // op: opcode |
| 10740 | return 0; |
| 10741 | case 2: |
| 10742 | // op: func3 |
| 10743 | return 12; |
| 10744 | case 3: |
| 10745 | // op: func1 |
| 10746 | return 15; |
| 10747 | case 0: |
| 10748 | // op: rd |
| 10749 | return 7; |
| 10750 | case 4: |
| 10751 | // op: imm32 |
| 10752 | return 16; |
| 10753 | } |
| 10754 | break; |
| 10755 | } |
| 10756 | case RISCV::InsnQC_EI: |
| 10757 | case RISCV::InsnQC_EI_Mem: { |
| 10758 | switch (OpNum) { |
| 10759 | case 1: |
| 10760 | // op: opcode |
| 10761 | return 0; |
| 10762 | case 2: |
| 10763 | // op: func3 |
| 10764 | return 12; |
| 10765 | case 3: |
| 10766 | // op: func2 |
| 10767 | return 30; |
| 10768 | case 0: |
| 10769 | // op: rd |
| 10770 | return 7; |
| 10771 | case 4: |
| 10772 | // op: rs1 |
| 10773 | return 15; |
| 10774 | case 5: |
| 10775 | // op: imm26 |
| 10776 | return 20; |
| 10777 | } |
| 10778 | break; |
| 10779 | } |
| 10780 | case RISCV::InsnI: |
| 10781 | case RISCV::InsnI_Mem: { |
| 10782 | switch (OpNum) { |
| 10783 | case 1: |
| 10784 | // op: opcode |
| 10785 | return 0; |
| 10786 | case 2: |
| 10787 | // op: funct3 |
| 10788 | return 12; |
| 10789 | case 4: |
| 10790 | // op: imm12 |
| 10791 | return 20; |
| 10792 | case 3: |
| 10793 | // op: rs1 |
| 10794 | return 15; |
| 10795 | case 0: |
| 10796 | // op: rd |
| 10797 | return 7; |
| 10798 | } |
| 10799 | break; |
| 10800 | } |
| 10801 | case RISCV::InsnCI: { |
| 10802 | switch (OpNum) { |
| 10803 | case 1: |
| 10804 | // op: opcode |
| 10805 | return 0; |
| 10806 | case 2: |
| 10807 | // op: funct3 |
| 10808 | return 13; |
| 10809 | case 3: |
| 10810 | // op: imm6 |
| 10811 | return 2; |
| 10812 | case 0: |
| 10813 | // op: rd |
| 10814 | return 7; |
| 10815 | } |
| 10816 | break; |
| 10817 | } |
| 10818 | case RISCV::InsnCIW: { |
| 10819 | switch (OpNum) { |
| 10820 | case 1: |
| 10821 | // op: opcode |
| 10822 | return 0; |
| 10823 | case 2: |
| 10824 | // op: funct3 |
| 10825 | return 13; |
| 10826 | case 3: |
| 10827 | // op: imm8 |
| 10828 | return 5; |
| 10829 | case 0: |
| 10830 | // op: rd |
| 10831 | return 2; |
| 10832 | } |
| 10833 | break; |
| 10834 | } |
| 10835 | case RISCV::InsnCL: { |
| 10836 | switch (OpNum) { |
| 10837 | case 1: |
| 10838 | // op: opcode |
| 10839 | return 0; |
| 10840 | case 2: |
| 10841 | // op: funct3 |
| 10842 | return 13; |
| 10843 | case 4: |
| 10844 | // op: imm5 |
| 10845 | return 5; |
| 10846 | case 0: |
| 10847 | // op: rd |
| 10848 | return 2; |
| 10849 | case 3: |
| 10850 | // op: rs1 |
| 10851 | return 7; |
| 10852 | } |
| 10853 | break; |
| 10854 | } |
| 10855 | case RISCV::InsnCR: { |
| 10856 | switch (OpNum) { |
| 10857 | case 1: |
| 10858 | // op: opcode |
| 10859 | return 0; |
| 10860 | case 2: |
| 10861 | // op: funct4 |
| 10862 | return 12; |
| 10863 | case 3: |
| 10864 | // op: rs2 |
| 10865 | return 2; |
| 10866 | case 0: |
| 10867 | // op: rd |
| 10868 | return 7; |
| 10869 | } |
| 10870 | break; |
| 10871 | } |
| 10872 | case RISCV::InsnCA: { |
| 10873 | switch (OpNum) { |
| 10874 | case 1: |
| 10875 | // op: opcode |
| 10876 | return 0; |
| 10877 | case 2: |
| 10878 | // op: funct6 |
| 10879 | return 10; |
| 10880 | case 3: |
| 10881 | // op: funct2 |
| 10882 | return 5; |
| 10883 | case 0: |
| 10884 | // op: rd |
| 10885 | return 7; |
| 10886 | case 4: |
| 10887 | // op: rs2 |
| 10888 | return 2; |
| 10889 | } |
| 10890 | break; |
| 10891 | } |
| 10892 | case RISCV::InsnJ: |
| 10893 | case RISCV::InsnU: { |
| 10894 | switch (OpNum) { |
| 10895 | case 1: |
| 10896 | // op: opcode |
| 10897 | return 0; |
| 10898 | case 2: |
| 10899 | // op: imm20 |
| 10900 | return 12; |
| 10901 | case 0: |
| 10902 | // op: rd |
| 10903 | return 7; |
| 10904 | } |
| 10905 | break; |
| 10906 | } |
| 10907 | case RISCV::InsnR4: { |
| 10908 | switch (OpNum) { |
| 10909 | case 1: |
| 10910 | // op: opcode |
| 10911 | return 0; |
| 10912 | case 3: |
| 10913 | // op: funct2 |
| 10914 | return 25; |
| 10915 | case 2: |
| 10916 | // op: funct3 |
| 10917 | return 12; |
| 10918 | case 6: |
| 10919 | // op: rs3 |
| 10920 | return 27; |
| 10921 | case 5: |
| 10922 | // op: rs2 |
| 10923 | return 20; |
| 10924 | case 4: |
| 10925 | // op: rs1 |
| 10926 | return 15; |
| 10927 | case 0: |
| 10928 | // op: rd |
| 10929 | return 7; |
| 10930 | } |
| 10931 | break; |
| 10932 | } |
| 10933 | case RISCV::InsnR: { |
| 10934 | switch (OpNum) { |
| 10935 | case 1: |
| 10936 | // op: opcode |
| 10937 | return 0; |
| 10938 | case 3: |
| 10939 | // op: funct7 |
| 10940 | return 25; |
| 10941 | case 2: |
| 10942 | // op: funct3 |
| 10943 | return 12; |
| 10944 | case 5: |
| 10945 | // op: rs2 |
| 10946 | return 20; |
| 10947 | case 4: |
| 10948 | // op: rs1 |
| 10949 | return 15; |
| 10950 | case 0: |
| 10951 | // op: rd |
| 10952 | return 7; |
| 10953 | } |
| 10954 | break; |
| 10955 | } |
| 10956 | case RISCV::QC_C_MULIADD: { |
| 10957 | switch (OpNum) { |
| 10958 | case 1: |
| 10959 | // op: rd |
| 10960 | return 2; |
| 10961 | case 2: |
| 10962 | // op: rs1 |
| 10963 | return 7; |
| 10964 | case 3: |
| 10965 | // op: uimm |
| 10966 | return 5; |
| 10967 | } |
| 10968 | break; |
| 10969 | } |
| 10970 | case RISCV::QC_C_MVEQZ: { |
| 10971 | switch (OpNum) { |
| 10972 | case 1: |
| 10973 | // op: rd |
| 10974 | return 2; |
| 10975 | case 2: |
| 10976 | // op: rs1 |
| 10977 | return 7; |
| 10978 | } |
| 10979 | break; |
| 10980 | } |
| 10981 | case RISCV::QC_E_ADDAI: |
| 10982 | case RISCV::QC_E_ANDAI: |
| 10983 | case RISCV::QC_E_ORAI: |
| 10984 | case RISCV::QC_E_XORAI: { |
| 10985 | switch (OpNum) { |
| 10986 | case 1: |
| 10987 | // op: rd |
| 10988 | return 7; |
| 10989 | case 2: |
| 10990 | // op: imm |
| 10991 | return 16; |
| 10992 | } |
| 10993 | break; |
| 10994 | } |
| 10995 | case RISCV::QC_INSBI: { |
| 10996 | switch (OpNum) { |
| 10997 | case 1: |
| 10998 | // op: rd |
| 10999 | return 7; |
| 11000 | case 2: |
| 11001 | // op: imm5 |
| 11002 | return 15; |
| 11003 | case 4: |
| 11004 | // op: shamt |
| 11005 | return 20; |
| 11006 | case 3: |
| 11007 | // op: width |
| 11008 | return 25; |
| 11009 | } |
| 11010 | break; |
| 11011 | } |
| 11012 | case RISCV::QC_C_EXTU: { |
| 11013 | switch (OpNum) { |
| 11014 | case 1: |
| 11015 | // op: rd |
| 11016 | return 7; |
| 11017 | case 2: |
| 11018 | // op: width |
| 11019 | return 2; |
| 11020 | } |
| 11021 | break; |
| 11022 | } |
| 11023 | case RISCV::C_NOT: |
| 11024 | case RISCV::C_SEXT_B: |
| 11025 | case RISCV::C_SEXT_H: |
| 11026 | case RISCV::C_ZEXT_B: |
| 11027 | case RISCV::C_ZEXT_H: |
| 11028 | case RISCV::C_ZEXT_W: { |
| 11029 | switch (OpNum) { |
| 11030 | case 1: |
| 11031 | // op: rd |
| 11032 | return 7; |
| 11033 | } |
| 11034 | break; |
| 11035 | } |
| 11036 | case RISCV::QC_WRAPI: { |
| 11037 | switch (OpNum) { |
| 11038 | case 1: |
| 11039 | // op: rs1 |
| 11040 | return 15; |
| 11041 | case 0: |
| 11042 | // op: rd |
| 11043 | return 7; |
| 11044 | case 2: |
| 11045 | // op: imm11 |
| 11046 | return 20; |
| 11047 | } |
| 11048 | break; |
| 11049 | } |
| 11050 | case RISCV::ADDI: |
| 11051 | case RISCV::ADDIW: |
| 11052 | case RISCV::ANDI: |
| 11053 | case RISCV::CV_ELW: |
| 11054 | case RISCV::FLD: |
| 11055 | case RISCV::FLH: |
| 11056 | case RISCV::FLQ: |
| 11057 | case RISCV::FLW: |
| 11058 | case RISCV::JALR: |
| 11059 | case RISCV::LB: |
| 11060 | case RISCV::LBU: |
| 11061 | case RISCV::LD: |
| 11062 | case RISCV::LD_RV32: |
| 11063 | case RISCV::LH: |
| 11064 | case RISCV::LHU: |
| 11065 | case RISCV::LH_INX: |
| 11066 | case RISCV::LW: |
| 11067 | case RISCV::LWU: |
| 11068 | case RISCV::LW_INX: |
| 11069 | case RISCV::ORI: |
| 11070 | case RISCV::SLTI: |
| 11071 | case RISCV::SLTIU: |
| 11072 | case RISCV::XORI: { |
| 11073 | switch (OpNum) { |
| 11074 | case 1: |
| 11075 | // op: rs1 |
| 11076 | return 15; |
| 11077 | case 0: |
| 11078 | // op: rd |
| 11079 | return 7; |
| 11080 | case 2: |
| 11081 | // op: imm12 |
| 11082 | return 20; |
| 11083 | } |
| 11084 | break; |
| 11085 | } |
| 11086 | case RISCV::QC_INW: { |
| 11087 | switch (OpNum) { |
| 11088 | case 1: |
| 11089 | // op: rs1 |
| 11090 | return 15; |
| 11091 | case 0: |
| 11092 | // op: rd |
| 11093 | return 7; |
| 11094 | case 2: |
| 11095 | // op: imm14 |
| 11096 | return 20; |
| 11097 | } |
| 11098 | break; |
| 11099 | } |
| 11100 | case RISCV::CV_CLIP: |
| 11101 | case RISCV::CV_CLIPU: { |
| 11102 | switch (OpNum) { |
| 11103 | case 1: |
| 11104 | // op: rs1 |
| 11105 | return 15; |
| 11106 | case 0: |
| 11107 | // op: rd |
| 11108 | return 7; |
| 11109 | case 2: |
| 11110 | // op: imm5 |
| 11111 | return 20; |
| 11112 | } |
| 11113 | break; |
| 11114 | } |
| 11115 | case RISCV::CV_ADD_SCI_B: |
| 11116 | case RISCV::CV_ADD_SCI_H: |
| 11117 | case RISCV::CV_AND_SCI_B: |
| 11118 | case RISCV::CV_AND_SCI_H: |
| 11119 | case RISCV::CV_AVGU_SCI_B: |
| 11120 | case RISCV::CV_AVGU_SCI_H: |
| 11121 | case RISCV::CV_AVG_SCI_B: |
| 11122 | case RISCV::CV_AVG_SCI_H: |
| 11123 | case RISCV::CV_CMPEQ_SCI_B: |
| 11124 | case RISCV::CV_CMPEQ_SCI_H: |
| 11125 | case RISCV::CV_CMPGEU_SCI_B: |
| 11126 | case RISCV::CV_CMPGEU_SCI_H: |
| 11127 | case RISCV::CV_CMPGE_SCI_B: |
| 11128 | case RISCV::CV_CMPGE_SCI_H: |
| 11129 | case RISCV::CV_CMPGTU_SCI_B: |
| 11130 | case RISCV::CV_CMPGTU_SCI_H: |
| 11131 | case RISCV::CV_CMPGT_SCI_B: |
| 11132 | case RISCV::CV_CMPGT_SCI_H: |
| 11133 | case RISCV::CV_CMPLEU_SCI_B: |
| 11134 | case RISCV::CV_CMPLEU_SCI_H: |
| 11135 | case RISCV::CV_CMPLE_SCI_B: |
| 11136 | case RISCV::CV_CMPLE_SCI_H: |
| 11137 | case RISCV::CV_CMPLTU_SCI_B: |
| 11138 | case RISCV::CV_CMPLTU_SCI_H: |
| 11139 | case RISCV::CV_CMPLT_SCI_B: |
| 11140 | case RISCV::CV_CMPLT_SCI_H: |
| 11141 | case RISCV::CV_CMPNE_SCI_B: |
| 11142 | case RISCV::CV_CMPNE_SCI_H: |
| 11143 | case RISCV::CV_DOTSP_SCI_B: |
| 11144 | case RISCV::CV_DOTSP_SCI_H: |
| 11145 | case RISCV::CV_DOTUP_SCI_B: |
| 11146 | case RISCV::CV_DOTUP_SCI_H: |
| 11147 | case RISCV::CV_DOTUSP_SCI_B: |
| 11148 | case RISCV::CV_DOTUSP_SCI_H: |
| 11149 | case RISCV::CV_EXTRACTU_B: |
| 11150 | case RISCV::CV_EXTRACTU_H: |
| 11151 | case RISCV::CV_EXTRACT_B: |
| 11152 | case RISCV::CV_EXTRACT_H: |
| 11153 | case RISCV::CV_MAXU_SCI_B: |
| 11154 | case RISCV::CV_MAXU_SCI_H: |
| 11155 | case RISCV::CV_MAX_SCI_B: |
| 11156 | case RISCV::CV_MAX_SCI_H: |
| 11157 | case RISCV::CV_MINU_SCI_B: |
| 11158 | case RISCV::CV_MINU_SCI_H: |
| 11159 | case RISCV::CV_MIN_SCI_B: |
| 11160 | case RISCV::CV_MIN_SCI_H: |
| 11161 | case RISCV::CV_OR_SCI_B: |
| 11162 | case RISCV::CV_OR_SCI_H: |
| 11163 | case RISCV::CV_SHUFFLEI0_SCI_B: |
| 11164 | case RISCV::CV_SHUFFLEI1_SCI_B: |
| 11165 | case RISCV::CV_SHUFFLEI2_SCI_B: |
| 11166 | case RISCV::CV_SHUFFLEI3_SCI_B: |
| 11167 | case RISCV::CV_SHUFFLE_SCI_H: |
| 11168 | case RISCV::CV_SLL_SCI_B: |
| 11169 | case RISCV::CV_SLL_SCI_H: |
| 11170 | case RISCV::CV_SRA_SCI_B: |
| 11171 | case RISCV::CV_SRA_SCI_H: |
| 11172 | case RISCV::CV_SRL_SCI_B: |
| 11173 | case RISCV::CV_SRL_SCI_H: |
| 11174 | case RISCV::CV_SUB_SCI_B: |
| 11175 | case RISCV::CV_SUB_SCI_H: |
| 11176 | case RISCV::CV_XOR_SCI_B: |
| 11177 | case RISCV::CV_XOR_SCI_H: { |
| 11178 | switch (OpNum) { |
| 11179 | case 1: |
| 11180 | // op: rs1 |
| 11181 | return 15; |
| 11182 | case 0: |
| 11183 | // op: rd |
| 11184 | return 7; |
| 11185 | case 2: |
| 11186 | // op: imm6 |
| 11187 | return 20; |
| 11188 | } |
| 11189 | break; |
| 11190 | } |
| 11191 | case RISCV::CV_BCLR: |
| 11192 | case RISCV::CV_BITREV: |
| 11193 | case RISCV::CV_BSET: |
| 11194 | case RISCV::CV_EXTRACT: |
| 11195 | case RISCV::CV_EXTRACTU: { |
| 11196 | switch (OpNum) { |
| 11197 | case 1: |
| 11198 | // op: rs1 |
| 11199 | return 15; |
| 11200 | case 0: |
| 11201 | // op: rd |
| 11202 | return 7; |
| 11203 | case 2: |
| 11204 | // op: is3 |
| 11205 | return 25; |
| 11206 | case 3: |
| 11207 | // op: is2 |
| 11208 | return 20; |
| 11209 | } |
| 11210 | break; |
| 11211 | } |
| 11212 | case RISCV::TH_EXT: |
| 11213 | case RISCV::TH_EXTU: { |
| 11214 | switch (OpNum) { |
| 11215 | case 1: |
| 11216 | // op: rs1 |
| 11217 | return 15; |
| 11218 | case 0: |
| 11219 | // op: rd |
| 11220 | return 7; |
| 11221 | case 2: |
| 11222 | // op: msb |
| 11223 | return 26; |
| 11224 | case 3: |
| 11225 | // op: lsb |
| 11226 | return 20; |
| 11227 | } |
| 11228 | break; |
| 11229 | } |
| 11230 | case RISCV::AES64KS1I: { |
| 11231 | switch (OpNum) { |
| 11232 | case 1: |
| 11233 | // op: rs1 |
| 11234 | return 15; |
| 11235 | case 0: |
| 11236 | // op: rd |
| 11237 | return 7; |
| 11238 | case 2: |
| 11239 | // op: rnum |
| 11240 | return 20; |
| 11241 | } |
| 11242 | break; |
| 11243 | } |
| 11244 | case RISCV::BCLRI: |
| 11245 | case RISCV::BEXTI: |
| 11246 | case RISCV::BINVI: |
| 11247 | case RISCV::BSETI: |
| 11248 | case RISCV::PSATI_H: |
| 11249 | case RISCV::PSATI_W: |
| 11250 | case RISCV::PSLLI_B: |
| 11251 | case RISCV::PSLLI_H: |
| 11252 | case RISCV::PSLLI_W: |
| 11253 | case RISCV::PSRAI_B: |
| 11254 | case RISCV::PSRAI_H: |
| 11255 | case RISCV::PSRAI_W: |
| 11256 | case RISCV::PSRARI_H: |
| 11257 | case RISCV::PSRARI_W: |
| 11258 | case RISCV::PSRLI_B: |
| 11259 | case RISCV::PSRLI_H: |
| 11260 | case RISCV::PSRLI_W: |
| 11261 | case RISCV::PSSLAI_H: |
| 11262 | case RISCV::PSSLAI_W: |
| 11263 | case RISCV::PUSATI_H: |
| 11264 | case RISCV::PUSATI_W: |
| 11265 | case RISCV::RORI: |
| 11266 | case RISCV::RORIW: |
| 11267 | case RISCV::SATI_RV32: |
| 11268 | case RISCV::SATI_RV64: |
| 11269 | case RISCV::SLLI: |
| 11270 | case RISCV::SLLIW: |
| 11271 | case RISCV::SLLI_UW: |
| 11272 | case RISCV::SRAI: |
| 11273 | case RISCV::SRAIW: |
| 11274 | case RISCV::SRARI_RV32: |
| 11275 | case RISCV::SRARI_RV64: |
| 11276 | case RISCV::SRLI: |
| 11277 | case RISCV::SRLIW: |
| 11278 | case RISCV::SSLAI: |
| 11279 | case RISCV::TH_SRRI: |
| 11280 | case RISCV::TH_SRRIW: |
| 11281 | case RISCV::TH_TST: |
| 11282 | case RISCV::USATI_RV32: |
| 11283 | case RISCV::USATI_RV64: { |
| 11284 | switch (OpNum) { |
| 11285 | case 1: |
| 11286 | // op: rs1 |
| 11287 | return 15; |
| 11288 | case 0: |
| 11289 | // op: rd |
| 11290 | return 7; |
| 11291 | case 2: |
| 11292 | // op: shamt |
| 11293 | return 20; |
| 11294 | } |
| 11295 | break; |
| 11296 | } |
| 11297 | case RISCV::VSETVLI: { |
| 11298 | switch (OpNum) { |
| 11299 | case 1: |
| 11300 | // op: rs1 |
| 11301 | return 15; |
| 11302 | case 0: |
| 11303 | // op: rd |
| 11304 | return 7; |
| 11305 | case 2: |
| 11306 | // op: vtypei |
| 11307 | return 20; |
| 11308 | } |
| 11309 | break; |
| 11310 | } |
| 11311 | case RISCV::QC_EXT: |
| 11312 | case RISCV::QC_EXTD: |
| 11313 | case RISCV::QC_EXTDU: |
| 11314 | case RISCV::QC_EXTU: { |
| 11315 | switch (OpNum) { |
| 11316 | case 1: |
| 11317 | // op: rs1 |
| 11318 | return 15; |
| 11319 | case 0: |
| 11320 | // op: rd |
| 11321 | return 7; |
| 11322 | case 3: |
| 11323 | // op: shamt |
| 11324 | return 20; |
| 11325 | case 2: |
| 11326 | // op: width |
| 11327 | return 25; |
| 11328 | } |
| 11329 | break; |
| 11330 | } |
| 11331 | case RISCV::ABS: |
| 11332 | case RISCV::ABSW: |
| 11333 | case RISCV::AES64IM: |
| 11334 | case RISCV::AIF_FBCX_PS: |
| 11335 | case RISCV::AIF_FCLASS_PS: |
| 11336 | case RISCV::AIF_FCVT_F10_PS: |
| 11337 | case RISCV::AIF_FCVT_F11_PS: |
| 11338 | case RISCV::AIF_FCVT_F16_PS: |
| 11339 | case RISCV::AIF_FCVT_PS_F10: |
| 11340 | case RISCV::AIF_FCVT_PS_F11: |
| 11341 | case RISCV::AIF_FCVT_PS_F16: |
| 11342 | case RISCV::AIF_FCVT_PS_RAST: |
| 11343 | case RISCV::AIF_FCVT_PS_SN16: |
| 11344 | case RISCV::AIF_FCVT_PS_SN8: |
| 11345 | case RISCV::AIF_FCVT_PS_UN10: |
| 11346 | case RISCV::AIF_FCVT_PS_UN16: |
| 11347 | case RISCV::AIF_FCVT_PS_UN2: |
| 11348 | case RISCV::AIF_FCVT_PS_UN24: |
| 11349 | case RISCV::AIF_FCVT_PS_UN8: |
| 11350 | case RISCV::AIF_FCVT_RAST_PS: |
| 11351 | case RISCV::AIF_FCVT_SN16_PS: |
| 11352 | case RISCV::AIF_FCVT_SN8_PS: |
| 11353 | case RISCV::AIF_FCVT_UN10_PS: |
| 11354 | case RISCV::AIF_FCVT_UN16_PS: |
| 11355 | case RISCV::AIF_FCVT_UN24_PS: |
| 11356 | case RISCV::AIF_FCVT_UN2_PS: |
| 11357 | case RISCV::AIF_FCVT_UN8_PS: |
| 11358 | case RISCV::AIF_FEXP_PS: |
| 11359 | case RISCV::AIF_FFRC_PS: |
| 11360 | case RISCV::AIF_FLOG_PS: |
| 11361 | case RISCV::AIF_FLWG_PS: |
| 11362 | case RISCV::AIF_FLWL_PS: |
| 11363 | case RISCV::AIF_FNOT_PI: |
| 11364 | case RISCV::AIF_FPACKREPB_PI: |
| 11365 | case RISCV::AIF_FPACKREPH_PI: |
| 11366 | case RISCV::AIF_FRCP_PS: |
| 11367 | case RISCV::AIF_FRSQ_PS: |
| 11368 | case RISCV::AIF_FSAT8_PI: |
| 11369 | case RISCV::AIF_FSATU8_PI: |
| 11370 | case RISCV::AIF_FSETM_PI: |
| 11371 | case RISCV::AIF_FSIN_PS: |
| 11372 | case RISCV::AIF_FSQRT_PS: |
| 11373 | case RISCV::AIF_MASKNOT: |
| 11374 | case RISCV::AIF_MASKPOPC: |
| 11375 | case RISCV::AIF_MASKPOPCZ: |
| 11376 | case RISCV::BREV8: |
| 11377 | case RISCV::CLS: |
| 11378 | case RISCV::CLSW: |
| 11379 | case RISCV::CLZ: |
| 11380 | case RISCV::CLZW: |
| 11381 | case RISCV::CPOP: |
| 11382 | case RISCV::CPOPW: |
| 11383 | case RISCV::CTZ: |
| 11384 | case RISCV::CTZW: |
| 11385 | case RISCV::CV_ABS: |
| 11386 | case RISCV::CV_ABS_B: |
| 11387 | case RISCV::CV_ABS_H: |
| 11388 | case RISCV::CV_CLB: |
| 11389 | case RISCV::CV_CNT: |
| 11390 | case RISCV::CV_CPLXCONJ: |
| 11391 | case RISCV::CV_EXTBS: |
| 11392 | case RISCV::CV_EXTBZ: |
| 11393 | case RISCV::CV_EXTHS: |
| 11394 | case RISCV::CV_EXTHZ: |
| 11395 | case RISCV::CV_FF1: |
| 11396 | case RISCV::CV_FL1: |
| 11397 | case RISCV::FCLASS_D: |
| 11398 | case RISCV::FCLASS_D_IN32X: |
| 11399 | case RISCV::FCLASS_D_INX: |
| 11400 | case RISCV::FCLASS_H: |
| 11401 | case RISCV::FCLASS_H_INX: |
| 11402 | case RISCV::FCLASS_Q: |
| 11403 | case RISCV::FCLASS_S: |
| 11404 | case RISCV::FCLASS_S_INX: |
| 11405 | case RISCV::FCVTMOD_W_D: |
| 11406 | case RISCV::FMVH_X_D: |
| 11407 | case RISCV::FMVH_X_Q: |
| 11408 | case RISCV::FMV_D_X: |
| 11409 | case RISCV::FMV_H_X: |
| 11410 | case RISCV::FMV_W_X: |
| 11411 | case RISCV::FMV_X_D: |
| 11412 | case RISCV::FMV_X_H: |
| 11413 | case RISCV::FMV_X_W: |
| 11414 | case RISCV::FMV_X_W_FPR64: |
| 11415 | case RISCV::HLVX_HU: |
| 11416 | case RISCV::HLVX_WU: |
| 11417 | case RISCV::HLV_B: |
| 11418 | case RISCV::HLV_BU: |
| 11419 | case RISCV::HLV_D: |
| 11420 | case RISCV::HLV_H: |
| 11421 | case RISCV::HLV_HU: |
| 11422 | case RISCV::HLV_W: |
| 11423 | case RISCV::HLV_WU: |
| 11424 | case RISCV::LB_AQ: |
| 11425 | case RISCV::LB_AQRL: |
| 11426 | case RISCV::LD_AQ: |
| 11427 | case RISCV::LD_AQRL: |
| 11428 | case RISCV::LH_AQ: |
| 11429 | case RISCV::LH_AQRL: |
| 11430 | case RISCV::LR_D: |
| 11431 | case RISCV::LR_D_AQ: |
| 11432 | case RISCV::LR_D_AQRL: |
| 11433 | case RISCV::LR_D_RL: |
| 11434 | case RISCV::LR_W: |
| 11435 | case RISCV::LR_W_AQ: |
| 11436 | case RISCV::LR_W_AQRL: |
| 11437 | case RISCV::LR_W_RL: |
| 11438 | case RISCV::LW_AQ: |
| 11439 | case RISCV::LW_AQRL: |
| 11440 | case RISCV::MOP_R_0: |
| 11441 | case RISCV::MOP_R_1: |
| 11442 | case RISCV::MOP_R_10: |
| 11443 | case RISCV::MOP_R_11: |
| 11444 | case RISCV::MOP_R_12: |
| 11445 | case RISCV::MOP_R_13: |
| 11446 | case RISCV::MOP_R_14: |
| 11447 | case RISCV::MOP_R_15: |
| 11448 | case RISCV::MOP_R_16: |
| 11449 | case RISCV::MOP_R_17: |
| 11450 | case RISCV::MOP_R_18: |
| 11451 | case RISCV::MOP_R_19: |
| 11452 | case RISCV::MOP_R_2: |
| 11453 | case RISCV::MOP_R_20: |
| 11454 | case RISCV::MOP_R_21: |
| 11455 | case RISCV::MOP_R_22: |
| 11456 | case RISCV::MOP_R_23: |
| 11457 | case RISCV::MOP_R_24: |
| 11458 | case RISCV::MOP_R_25: |
| 11459 | case RISCV::MOP_R_26: |
| 11460 | case RISCV::MOP_R_27: |
| 11461 | case RISCV::MOP_R_28: |
| 11462 | case RISCV::MOP_R_29: |
| 11463 | case RISCV::MOP_R_3: |
| 11464 | case RISCV::MOP_R_30: |
| 11465 | case RISCV::MOP_R_31: |
| 11466 | case RISCV::MOP_R_4: |
| 11467 | case RISCV::MOP_R_5: |
| 11468 | case RISCV::MOP_R_6: |
| 11469 | case RISCV::MOP_R_7: |
| 11470 | case RISCV::MOP_R_8: |
| 11471 | case RISCV::MOP_R_9: |
| 11472 | case RISCV::NDS_FMV_BF16_X: |
| 11473 | case RISCV::NDS_FMV_X_BF16: |
| 11474 | case RISCV::ORC_B: |
| 11475 | case RISCV::PSABS_B: |
| 11476 | case RISCV::PSABS_H: |
| 11477 | case RISCV::PSEXT_H_B: |
| 11478 | case RISCV::PSEXT_W_B: |
| 11479 | case RISCV::PSEXT_W_H: |
| 11480 | case RISCV::QC_BREV32: |
| 11481 | case RISCV::QC_CLO: |
| 11482 | case RISCV::QC_COMPRESS2: |
| 11483 | case RISCV::QC_COMPRESS3: |
| 11484 | case RISCV::QC_CTO: |
| 11485 | case RISCV::QC_EXPAND2: |
| 11486 | case RISCV::QC_EXPAND3: |
| 11487 | case RISCV::QC_NORM: |
| 11488 | case RISCV::QC_NORMEU: |
| 11489 | case RISCV::QC_NORMU: |
| 11490 | case RISCV::REV16: |
| 11491 | case RISCV::REV8_RV32: |
| 11492 | case RISCV::REV8_RV64: |
| 11493 | case RISCV::REV_RV32: |
| 11494 | case RISCV::REV_RV64: |
| 11495 | case RISCV::SEXT_B: |
| 11496 | case RISCV::SEXT_H: |
| 11497 | case RISCV::SF_VSETTK: |
| 11498 | case RISCV::SF_VSETTM: |
| 11499 | case RISCV::SF_VSETTN: |
| 11500 | case RISCV::SHA256SIG0: |
| 11501 | case RISCV::SHA256SIG1: |
| 11502 | case RISCV::SHA256SUM0: |
| 11503 | case RISCV::SHA256SUM1: |
| 11504 | case RISCV::SHA512SIG0: |
| 11505 | case RISCV::SHA512SIG1: |
| 11506 | case RISCV::SHA512SUM0: |
| 11507 | case RISCV::SHA512SUM1: |
| 11508 | case RISCV::SM3P0: |
| 11509 | case RISCV::SM3P1: |
| 11510 | case RISCV::TH_FF0: |
| 11511 | case RISCV::TH_FF1: |
| 11512 | case RISCV::TH_REV: |
| 11513 | case RISCV::TH_REVW: |
| 11514 | case RISCV::TH_TSTNBZ: |
| 11515 | case RISCV::UNZIP_RV32: |
| 11516 | case RISCV::ZEXT_H_RV32: |
| 11517 | case RISCV::ZEXT_H_RV64: |
| 11518 | case RISCV::ZIP_RV32: { |
| 11519 | switch (OpNum) { |
| 11520 | case 1: |
| 11521 | // op: rs1 |
| 11522 | return 15; |
| 11523 | case 0: |
| 11524 | // op: rd |
| 11525 | return 7; |
| 11526 | } |
| 11527 | break; |
| 11528 | } |
| 11529 | case RISCV::PWSLAI_B: |
| 11530 | case RISCV::PWSLAI_H: |
| 11531 | case RISCV::PWSLLI_B: |
| 11532 | case RISCV::PWSLLI_H: |
| 11533 | case RISCV::WSLAI: |
| 11534 | case RISCV::WSLLI: { |
| 11535 | switch (OpNum) { |
| 11536 | case 1: |
| 11537 | // op: rs1 |
| 11538 | return 15; |
| 11539 | case 0: |
| 11540 | // op: rd |
| 11541 | return 8; |
| 11542 | case 2: |
| 11543 | // op: shamt |
| 11544 | return 20; |
| 11545 | } |
| 11546 | break; |
| 11547 | } |
| 11548 | case RISCV::QC_E_SB: |
| 11549 | case RISCV::QC_E_SH: |
| 11550 | case RISCV::QC_E_SW: { |
| 11551 | switch (OpNum) { |
| 11552 | case 1: |
| 11553 | // op: rs1 |
| 11554 | return 15; |
| 11555 | case 0: |
| 11556 | // op: rs2 |
| 11557 | return 20; |
| 11558 | case 2: |
| 11559 | // op: imm |
| 11560 | return 7; |
| 11561 | } |
| 11562 | break; |
| 11563 | } |
| 11564 | case RISCV::CV_SB_rr: |
| 11565 | case RISCV::CV_SH_rr: |
| 11566 | case RISCV::CV_SW_rr: { |
| 11567 | switch (OpNum) { |
| 11568 | case 1: |
| 11569 | // op: rs1 |
| 11570 | return 15; |
| 11571 | case 0: |
| 11572 | // op: rs2 |
| 11573 | return 20; |
| 11574 | case 2: |
| 11575 | // op: rs3 |
| 11576 | return 7; |
| 11577 | } |
| 11578 | break; |
| 11579 | } |
| 11580 | case RISCV::QC_OUTW: { |
| 11581 | switch (OpNum) { |
| 11582 | case 1: |
| 11583 | // op: rs1 |
| 11584 | return 15; |
| 11585 | case 0: |
| 11586 | // op: rs2 |
| 11587 | return 7; |
| 11588 | case 2: |
| 11589 | // op: imm14 |
| 11590 | return 20; |
| 11591 | } |
| 11592 | break; |
| 11593 | } |
| 11594 | case RISCV::NDS_VLN8_V: |
| 11595 | case RISCV::NDS_VLNU8_V: |
| 11596 | case RISCV::VLE16FF_V: |
| 11597 | case RISCV::VLE16_V: |
| 11598 | case RISCV::VLE32FF_V: |
| 11599 | case RISCV::VLE32_V: |
| 11600 | case RISCV::VLE64FF_V: |
| 11601 | case RISCV::VLE64_V: |
| 11602 | case RISCV::VLE8FF_V: |
| 11603 | case RISCV::VLE8_V: |
| 11604 | case RISCV::VLSEG2E16FF_V: |
| 11605 | case RISCV::VLSEG2E16_V: |
| 11606 | case RISCV::VLSEG2E32FF_V: |
| 11607 | case RISCV::VLSEG2E32_V: |
| 11608 | case RISCV::VLSEG2E64FF_V: |
| 11609 | case RISCV::VLSEG2E64_V: |
| 11610 | case RISCV::VLSEG2E8FF_V: |
| 11611 | case RISCV::VLSEG2E8_V: |
| 11612 | case RISCV::VLSEG3E16FF_V: |
| 11613 | case RISCV::VLSEG3E16_V: |
| 11614 | case RISCV::VLSEG3E32FF_V: |
| 11615 | case RISCV::VLSEG3E32_V: |
| 11616 | case RISCV::VLSEG3E64FF_V: |
| 11617 | case RISCV::VLSEG3E64_V: |
| 11618 | case RISCV::VLSEG3E8FF_V: |
| 11619 | case RISCV::VLSEG3E8_V: |
| 11620 | case RISCV::VLSEG4E16FF_V: |
| 11621 | case RISCV::VLSEG4E16_V: |
| 11622 | case RISCV::VLSEG4E32FF_V: |
| 11623 | case RISCV::VLSEG4E32_V: |
| 11624 | case RISCV::VLSEG4E64FF_V: |
| 11625 | case RISCV::VLSEG4E64_V: |
| 11626 | case RISCV::VLSEG4E8FF_V: |
| 11627 | case RISCV::VLSEG4E8_V: |
| 11628 | case RISCV::VLSEG5E16FF_V: |
| 11629 | case RISCV::VLSEG5E16_V: |
| 11630 | case RISCV::VLSEG5E32FF_V: |
| 11631 | case RISCV::VLSEG5E32_V: |
| 11632 | case RISCV::VLSEG5E64FF_V: |
| 11633 | case RISCV::VLSEG5E64_V: |
| 11634 | case RISCV::VLSEG5E8FF_V: |
| 11635 | case RISCV::VLSEG5E8_V: |
| 11636 | case RISCV::VLSEG6E16FF_V: |
| 11637 | case RISCV::VLSEG6E16_V: |
| 11638 | case RISCV::VLSEG6E32FF_V: |
| 11639 | case RISCV::VLSEG6E32_V: |
| 11640 | case RISCV::VLSEG6E64FF_V: |
| 11641 | case RISCV::VLSEG6E64_V: |
| 11642 | case RISCV::VLSEG6E8FF_V: |
| 11643 | case RISCV::VLSEG6E8_V: |
| 11644 | case RISCV::VLSEG7E16FF_V: |
| 11645 | case RISCV::VLSEG7E16_V: |
| 11646 | case RISCV::VLSEG7E32FF_V: |
| 11647 | case RISCV::VLSEG7E32_V: |
| 11648 | case RISCV::VLSEG7E64FF_V: |
| 11649 | case RISCV::VLSEG7E64_V: |
| 11650 | case RISCV::VLSEG7E8FF_V: |
| 11651 | case RISCV::VLSEG7E8_V: |
| 11652 | case RISCV::VLSEG8E16FF_V: |
| 11653 | case RISCV::VLSEG8E16_V: |
| 11654 | case RISCV::VLSEG8E32FF_V: |
| 11655 | case RISCV::VLSEG8E32_V: |
| 11656 | case RISCV::VLSEG8E64FF_V: |
| 11657 | case RISCV::VLSEG8E64_V: |
| 11658 | case RISCV::VLSEG8E8FF_V: |
| 11659 | case RISCV::VLSEG8E8_V: { |
| 11660 | switch (OpNum) { |
| 11661 | case 1: |
| 11662 | // op: rs1 |
| 11663 | return 15; |
| 11664 | case 0: |
| 11665 | // op: vd |
| 11666 | return 7; |
| 11667 | case 2: |
| 11668 | // op: vm |
| 11669 | return 25; |
| 11670 | } |
| 11671 | break; |
| 11672 | } |
| 11673 | case RISCV::VLSE16_V: |
| 11674 | case RISCV::VLSE32_V: |
| 11675 | case RISCV::VLSE64_V: |
| 11676 | case RISCV::VLSE8_V: |
| 11677 | case RISCV::VLSSEG2E16_V: |
| 11678 | case RISCV::VLSSEG2E32_V: |
| 11679 | case RISCV::VLSSEG2E64_V: |
| 11680 | case RISCV::VLSSEG2E8_V: |
| 11681 | case RISCV::VLSSEG3E16_V: |
| 11682 | case RISCV::VLSSEG3E32_V: |
| 11683 | case RISCV::VLSSEG3E64_V: |
| 11684 | case RISCV::VLSSEG3E8_V: |
| 11685 | case RISCV::VLSSEG4E16_V: |
| 11686 | case RISCV::VLSSEG4E32_V: |
| 11687 | case RISCV::VLSSEG4E64_V: |
| 11688 | case RISCV::VLSSEG4E8_V: |
| 11689 | case RISCV::VLSSEG5E16_V: |
| 11690 | case RISCV::VLSSEG5E32_V: |
| 11691 | case RISCV::VLSSEG5E64_V: |
| 11692 | case RISCV::VLSSEG5E8_V: |
| 11693 | case RISCV::VLSSEG6E16_V: |
| 11694 | case RISCV::VLSSEG6E32_V: |
| 11695 | case RISCV::VLSSEG6E64_V: |
| 11696 | case RISCV::VLSSEG6E8_V: |
| 11697 | case RISCV::VLSSEG7E16_V: |
| 11698 | case RISCV::VLSSEG7E32_V: |
| 11699 | case RISCV::VLSSEG7E64_V: |
| 11700 | case RISCV::VLSSEG7E8_V: |
| 11701 | case RISCV::VLSSEG8E16_V: |
| 11702 | case RISCV::VLSSEG8E32_V: |
| 11703 | case RISCV::VLSSEG8E64_V: |
| 11704 | case RISCV::VLSSEG8E8_V: { |
| 11705 | switch (OpNum) { |
| 11706 | case 1: |
| 11707 | // op: rs1 |
| 11708 | return 15; |
| 11709 | case 0: |
| 11710 | // op: vd |
| 11711 | return 7; |
| 11712 | case 3: |
| 11713 | // op: vm |
| 11714 | return 25; |
| 11715 | case 2: |
| 11716 | // op: rs2 |
| 11717 | return 20; |
| 11718 | } |
| 11719 | break; |
| 11720 | } |
| 11721 | case RISCV::VLOXEI16_V: |
| 11722 | case RISCV::VLOXEI32_V: |
| 11723 | case RISCV::VLOXEI64_V: |
| 11724 | case RISCV::VLOXEI8_V: |
| 11725 | case RISCV::VLOXSEG2EI16_V: |
| 11726 | case RISCV::VLOXSEG2EI32_V: |
| 11727 | case RISCV::VLOXSEG2EI64_V: |
| 11728 | case RISCV::VLOXSEG2EI8_V: |
| 11729 | case RISCV::VLOXSEG3EI16_V: |
| 11730 | case RISCV::VLOXSEG3EI32_V: |
| 11731 | case RISCV::VLOXSEG3EI64_V: |
| 11732 | case RISCV::VLOXSEG3EI8_V: |
| 11733 | case RISCV::VLOXSEG4EI16_V: |
| 11734 | case RISCV::VLOXSEG4EI32_V: |
| 11735 | case RISCV::VLOXSEG4EI64_V: |
| 11736 | case RISCV::VLOXSEG4EI8_V: |
| 11737 | case RISCV::VLOXSEG5EI16_V: |
| 11738 | case RISCV::VLOXSEG5EI32_V: |
| 11739 | case RISCV::VLOXSEG5EI64_V: |
| 11740 | case RISCV::VLOXSEG5EI8_V: |
| 11741 | case RISCV::VLOXSEG6EI16_V: |
| 11742 | case RISCV::VLOXSEG6EI32_V: |
| 11743 | case RISCV::VLOXSEG6EI64_V: |
| 11744 | case RISCV::VLOXSEG6EI8_V: |
| 11745 | case RISCV::VLOXSEG7EI16_V: |
| 11746 | case RISCV::VLOXSEG7EI32_V: |
| 11747 | case RISCV::VLOXSEG7EI64_V: |
| 11748 | case RISCV::VLOXSEG7EI8_V: |
| 11749 | case RISCV::VLOXSEG8EI16_V: |
| 11750 | case RISCV::VLOXSEG8EI32_V: |
| 11751 | case RISCV::VLOXSEG8EI64_V: |
| 11752 | case RISCV::VLOXSEG8EI8_V: |
| 11753 | case RISCV::VLUXEI16_V: |
| 11754 | case RISCV::VLUXEI32_V: |
| 11755 | case RISCV::VLUXEI64_V: |
| 11756 | case RISCV::VLUXEI8_V: |
| 11757 | case RISCV::VLUXSEG2EI16_V: |
| 11758 | case RISCV::VLUXSEG2EI32_V: |
| 11759 | case RISCV::VLUXSEG2EI64_V: |
| 11760 | case RISCV::VLUXSEG2EI8_V: |
| 11761 | case RISCV::VLUXSEG3EI16_V: |
| 11762 | case RISCV::VLUXSEG3EI32_V: |
| 11763 | case RISCV::VLUXSEG3EI64_V: |
| 11764 | case RISCV::VLUXSEG3EI8_V: |
| 11765 | case RISCV::VLUXSEG4EI16_V: |
| 11766 | case RISCV::VLUXSEG4EI32_V: |
| 11767 | case RISCV::VLUXSEG4EI64_V: |
| 11768 | case RISCV::VLUXSEG4EI8_V: |
| 11769 | case RISCV::VLUXSEG5EI16_V: |
| 11770 | case RISCV::VLUXSEG5EI32_V: |
| 11771 | case RISCV::VLUXSEG5EI64_V: |
| 11772 | case RISCV::VLUXSEG5EI8_V: |
| 11773 | case RISCV::VLUXSEG6EI16_V: |
| 11774 | case RISCV::VLUXSEG6EI32_V: |
| 11775 | case RISCV::VLUXSEG6EI64_V: |
| 11776 | case RISCV::VLUXSEG6EI8_V: |
| 11777 | case RISCV::VLUXSEG7EI16_V: |
| 11778 | case RISCV::VLUXSEG7EI32_V: |
| 11779 | case RISCV::VLUXSEG7EI64_V: |
| 11780 | case RISCV::VLUXSEG7EI8_V: |
| 11781 | case RISCV::VLUXSEG8EI16_V: |
| 11782 | case RISCV::VLUXSEG8EI32_V: |
| 11783 | case RISCV::VLUXSEG8EI64_V: |
| 11784 | case RISCV::VLUXSEG8EI8_V: { |
| 11785 | switch (OpNum) { |
| 11786 | case 1: |
| 11787 | // op: rs1 |
| 11788 | return 15; |
| 11789 | case 0: |
| 11790 | // op: vd |
| 11791 | return 7; |
| 11792 | case 3: |
| 11793 | // op: vm |
| 11794 | return 25; |
| 11795 | case 2: |
| 11796 | // op: vs2 |
| 11797 | return 20; |
| 11798 | } |
| 11799 | break; |
| 11800 | } |
| 11801 | case RISCV::NDS_VLE4_V: |
| 11802 | case RISCV::SF_VTMV_V_T: |
| 11803 | case RISCV::VL1RE16_V: |
| 11804 | case RISCV::VL1RE32_V: |
| 11805 | case RISCV::VL1RE64_V: |
| 11806 | case RISCV::VL1RE8_V: |
| 11807 | case RISCV::VL2RE16_V: |
| 11808 | case RISCV::VL2RE32_V: |
| 11809 | case RISCV::VL2RE64_V: |
| 11810 | case RISCV::VL2RE8_V: |
| 11811 | case RISCV::VL4RE16_V: |
| 11812 | case RISCV::VL4RE32_V: |
| 11813 | case RISCV::VL4RE64_V: |
| 11814 | case RISCV::VL4RE8_V: |
| 11815 | case RISCV::VL8RE16_V: |
| 11816 | case RISCV::VL8RE32_V: |
| 11817 | case RISCV::VL8RE64_V: |
| 11818 | case RISCV::VL8RE8_V: |
| 11819 | case RISCV::VLM_V: { |
| 11820 | switch (OpNum) { |
| 11821 | case 1: |
| 11822 | // op: rs1 |
| 11823 | return 15; |
| 11824 | case 0: |
| 11825 | // op: vd |
| 11826 | return 7; |
| 11827 | } |
| 11828 | break; |
| 11829 | } |
| 11830 | case RISCV::VSE16_V: |
| 11831 | case RISCV::VSE32_V: |
| 11832 | case RISCV::VSE64_V: |
| 11833 | case RISCV::VSE8_V: |
| 11834 | case RISCV::VSSEG2E16_V: |
| 11835 | case RISCV::VSSEG2E32_V: |
| 11836 | case RISCV::VSSEG2E64_V: |
| 11837 | case RISCV::VSSEG2E8_V: |
| 11838 | case RISCV::VSSEG3E16_V: |
| 11839 | case RISCV::VSSEG3E32_V: |
| 11840 | case RISCV::VSSEG3E64_V: |
| 11841 | case RISCV::VSSEG3E8_V: |
| 11842 | case RISCV::VSSEG4E16_V: |
| 11843 | case RISCV::VSSEG4E32_V: |
| 11844 | case RISCV::VSSEG4E64_V: |
| 11845 | case RISCV::VSSEG4E8_V: |
| 11846 | case RISCV::VSSEG5E16_V: |
| 11847 | case RISCV::VSSEG5E32_V: |
| 11848 | case RISCV::VSSEG5E64_V: |
| 11849 | case RISCV::VSSEG5E8_V: |
| 11850 | case RISCV::VSSEG6E16_V: |
| 11851 | case RISCV::VSSEG6E32_V: |
| 11852 | case RISCV::VSSEG6E64_V: |
| 11853 | case RISCV::VSSEG6E8_V: |
| 11854 | case RISCV::VSSEG7E16_V: |
| 11855 | case RISCV::VSSEG7E32_V: |
| 11856 | case RISCV::VSSEG7E64_V: |
| 11857 | case RISCV::VSSEG7E8_V: |
| 11858 | case RISCV::VSSEG8E16_V: |
| 11859 | case RISCV::VSSEG8E32_V: |
| 11860 | case RISCV::VSSEG8E64_V: |
| 11861 | case RISCV::VSSEG8E8_V: { |
| 11862 | switch (OpNum) { |
| 11863 | case 1: |
| 11864 | // op: rs1 |
| 11865 | return 15; |
| 11866 | case 0: |
| 11867 | // op: vs3 |
| 11868 | return 7; |
| 11869 | case 2: |
| 11870 | // op: vm |
| 11871 | return 25; |
| 11872 | } |
| 11873 | break; |
| 11874 | } |
| 11875 | case RISCV::VSSE16_V: |
| 11876 | case RISCV::VSSE32_V: |
| 11877 | case RISCV::VSSE64_V: |
| 11878 | case RISCV::VSSE8_V: |
| 11879 | case RISCV::VSSSEG2E16_V: |
| 11880 | case RISCV::VSSSEG2E32_V: |
| 11881 | case RISCV::VSSSEG2E64_V: |
| 11882 | case RISCV::VSSSEG2E8_V: |
| 11883 | case RISCV::VSSSEG3E16_V: |
| 11884 | case RISCV::VSSSEG3E32_V: |
| 11885 | case RISCV::VSSSEG3E64_V: |
| 11886 | case RISCV::VSSSEG3E8_V: |
| 11887 | case RISCV::VSSSEG4E16_V: |
| 11888 | case RISCV::VSSSEG4E32_V: |
| 11889 | case RISCV::VSSSEG4E64_V: |
| 11890 | case RISCV::VSSSEG4E8_V: |
| 11891 | case RISCV::VSSSEG5E16_V: |
| 11892 | case RISCV::VSSSEG5E32_V: |
| 11893 | case RISCV::VSSSEG5E64_V: |
| 11894 | case RISCV::VSSSEG5E8_V: |
| 11895 | case RISCV::VSSSEG6E16_V: |
| 11896 | case RISCV::VSSSEG6E32_V: |
| 11897 | case RISCV::VSSSEG6E64_V: |
| 11898 | case RISCV::VSSSEG6E8_V: |
| 11899 | case RISCV::VSSSEG7E16_V: |
| 11900 | case RISCV::VSSSEG7E32_V: |
| 11901 | case RISCV::VSSSEG7E64_V: |
| 11902 | case RISCV::VSSSEG7E8_V: |
| 11903 | case RISCV::VSSSEG8E16_V: |
| 11904 | case RISCV::VSSSEG8E32_V: |
| 11905 | case RISCV::VSSSEG8E64_V: |
| 11906 | case RISCV::VSSSEG8E8_V: { |
| 11907 | switch (OpNum) { |
| 11908 | case 1: |
| 11909 | // op: rs1 |
| 11910 | return 15; |
| 11911 | case 0: |
| 11912 | // op: vs3 |
| 11913 | return 7; |
| 11914 | case 3: |
| 11915 | // op: vm |
| 11916 | return 25; |
| 11917 | case 2: |
| 11918 | // op: rs2 |
| 11919 | return 20; |
| 11920 | } |
| 11921 | break; |
| 11922 | } |
| 11923 | case RISCV::VSOXEI16_V: |
| 11924 | case RISCV::VSOXEI32_V: |
| 11925 | case RISCV::VSOXEI64_V: |
| 11926 | case RISCV::VSOXEI8_V: |
| 11927 | case RISCV::VSOXSEG2EI16_V: |
| 11928 | case RISCV::VSOXSEG2EI32_V: |
| 11929 | case RISCV::VSOXSEG2EI64_V: |
| 11930 | case RISCV::VSOXSEG2EI8_V: |
| 11931 | case RISCV::VSOXSEG3EI16_V: |
| 11932 | case RISCV::VSOXSEG3EI32_V: |
| 11933 | case RISCV::VSOXSEG3EI64_V: |
| 11934 | case RISCV::VSOXSEG3EI8_V: |
| 11935 | case RISCV::VSOXSEG4EI16_V: |
| 11936 | case RISCV::VSOXSEG4EI32_V: |
| 11937 | case RISCV::VSOXSEG4EI64_V: |
| 11938 | case RISCV::VSOXSEG4EI8_V: |
| 11939 | case RISCV::VSOXSEG5EI16_V: |
| 11940 | case RISCV::VSOXSEG5EI32_V: |
| 11941 | case RISCV::VSOXSEG5EI64_V: |
| 11942 | case RISCV::VSOXSEG5EI8_V: |
| 11943 | case RISCV::VSOXSEG6EI16_V: |
| 11944 | case RISCV::VSOXSEG6EI32_V: |
| 11945 | case RISCV::VSOXSEG6EI64_V: |
| 11946 | case RISCV::VSOXSEG6EI8_V: |
| 11947 | case RISCV::VSOXSEG7EI16_V: |
| 11948 | case RISCV::VSOXSEG7EI32_V: |
| 11949 | case RISCV::VSOXSEG7EI64_V: |
| 11950 | case RISCV::VSOXSEG7EI8_V: |
| 11951 | case RISCV::VSOXSEG8EI16_V: |
| 11952 | case RISCV::VSOXSEG8EI32_V: |
| 11953 | case RISCV::VSOXSEG8EI64_V: |
| 11954 | case RISCV::VSOXSEG8EI8_V: |
| 11955 | case RISCV::VSUXEI16_V: |
| 11956 | case RISCV::VSUXEI32_V: |
| 11957 | case RISCV::VSUXEI64_V: |
| 11958 | case RISCV::VSUXEI8_V: |
| 11959 | case RISCV::VSUXSEG2EI16_V: |
| 11960 | case RISCV::VSUXSEG2EI32_V: |
| 11961 | case RISCV::VSUXSEG2EI64_V: |
| 11962 | case RISCV::VSUXSEG2EI8_V: |
| 11963 | case RISCV::VSUXSEG3EI16_V: |
| 11964 | case RISCV::VSUXSEG3EI32_V: |
| 11965 | case RISCV::VSUXSEG3EI64_V: |
| 11966 | case RISCV::VSUXSEG3EI8_V: |
| 11967 | case RISCV::VSUXSEG4EI16_V: |
| 11968 | case RISCV::VSUXSEG4EI32_V: |
| 11969 | case RISCV::VSUXSEG4EI64_V: |
| 11970 | case RISCV::VSUXSEG4EI8_V: |
| 11971 | case RISCV::VSUXSEG5EI16_V: |
| 11972 | case RISCV::VSUXSEG5EI32_V: |
| 11973 | case RISCV::VSUXSEG5EI64_V: |
| 11974 | case RISCV::VSUXSEG5EI8_V: |
| 11975 | case RISCV::VSUXSEG6EI16_V: |
| 11976 | case RISCV::VSUXSEG6EI32_V: |
| 11977 | case RISCV::VSUXSEG6EI64_V: |
| 11978 | case RISCV::VSUXSEG6EI8_V: |
| 11979 | case RISCV::VSUXSEG7EI16_V: |
| 11980 | case RISCV::VSUXSEG7EI32_V: |
| 11981 | case RISCV::VSUXSEG7EI64_V: |
| 11982 | case RISCV::VSUXSEG7EI8_V: |
| 11983 | case RISCV::VSUXSEG8EI16_V: |
| 11984 | case RISCV::VSUXSEG8EI32_V: |
| 11985 | case RISCV::VSUXSEG8EI64_V: |
| 11986 | case RISCV::VSUXSEG8EI8_V: { |
| 11987 | switch (OpNum) { |
| 11988 | case 1: |
| 11989 | // op: rs1 |
| 11990 | return 15; |
| 11991 | case 0: |
| 11992 | // op: vs3 |
| 11993 | return 7; |
| 11994 | case 3: |
| 11995 | // op: vm |
| 11996 | return 25; |
| 11997 | case 2: |
| 11998 | // op: vs2 |
| 11999 | return 20; |
| 12000 | } |
| 12001 | break; |
| 12002 | } |
| 12003 | case RISCV::VS1R_V: |
| 12004 | case RISCV::VS2R_V: |
| 12005 | case RISCV::VS4R_V: |
| 12006 | case RISCV::VS8R_V: |
| 12007 | case RISCV::VSM_V: { |
| 12008 | switch (OpNum) { |
| 12009 | case 1: |
| 12010 | // op: rs1 |
| 12011 | return 15; |
| 12012 | case 0: |
| 12013 | // op: vs3 |
| 12014 | return 7; |
| 12015 | } |
| 12016 | break; |
| 12017 | } |
| 12018 | case RISCV::FCVT_BF16_S: |
| 12019 | case RISCV::FCVT_D_H: |
| 12020 | case RISCV::FCVT_D_H_IN32X: |
| 12021 | case RISCV::FCVT_D_H_INX: |
| 12022 | case RISCV::FCVT_D_L: |
| 12023 | case RISCV::FCVT_D_LU: |
| 12024 | case RISCV::FCVT_D_LU_INX: |
| 12025 | case RISCV::FCVT_D_L_INX: |
| 12026 | case RISCV::FCVT_D_Q: |
| 12027 | case RISCV::FCVT_D_S: |
| 12028 | case RISCV::FCVT_D_S_IN32X: |
| 12029 | case RISCV::FCVT_D_S_INX: |
| 12030 | case RISCV::FCVT_D_W: |
| 12031 | case RISCV::FCVT_D_WU: |
| 12032 | case RISCV::FCVT_D_WU_IN32X: |
| 12033 | case RISCV::FCVT_D_WU_INX: |
| 12034 | case RISCV::FCVT_D_W_IN32X: |
| 12035 | case RISCV::FCVT_D_W_INX: |
| 12036 | case RISCV::FCVT_H_D: |
| 12037 | case RISCV::FCVT_H_D_IN32X: |
| 12038 | case RISCV::FCVT_H_D_INX: |
| 12039 | case RISCV::FCVT_H_L: |
| 12040 | case RISCV::FCVT_H_LU: |
| 12041 | case RISCV::FCVT_H_LU_INX: |
| 12042 | case RISCV::FCVT_H_L_INX: |
| 12043 | case RISCV::FCVT_H_S: |
| 12044 | case RISCV::FCVT_H_S_INX: |
| 12045 | case RISCV::FCVT_H_W: |
| 12046 | case RISCV::FCVT_H_WU: |
| 12047 | case RISCV::FCVT_H_WU_INX: |
| 12048 | case RISCV::FCVT_H_W_INX: |
| 12049 | case RISCV::FCVT_LU_D: |
| 12050 | case RISCV::FCVT_LU_D_INX: |
| 12051 | case RISCV::FCVT_LU_H: |
| 12052 | case RISCV::FCVT_LU_H_INX: |
| 12053 | case RISCV::FCVT_LU_Q: |
| 12054 | case RISCV::FCVT_LU_S: |
| 12055 | case RISCV::FCVT_LU_S_INX: |
| 12056 | case RISCV::FCVT_L_D: |
| 12057 | case RISCV::FCVT_L_D_INX: |
| 12058 | case RISCV::FCVT_L_H: |
| 12059 | case RISCV::FCVT_L_H_INX: |
| 12060 | case RISCV::FCVT_L_Q: |
| 12061 | case RISCV::FCVT_L_S: |
| 12062 | case RISCV::FCVT_L_S_INX: |
| 12063 | case RISCV::FCVT_Q_D: |
| 12064 | case RISCV::FCVT_Q_L: |
| 12065 | case RISCV::FCVT_Q_LU: |
| 12066 | case RISCV::FCVT_Q_S: |
| 12067 | case RISCV::FCVT_Q_W: |
| 12068 | case RISCV::FCVT_Q_WU: |
| 12069 | case RISCV::FCVT_S_BF16: |
| 12070 | case RISCV::FCVT_S_D: |
| 12071 | case RISCV::FCVT_S_D_IN32X: |
| 12072 | case RISCV::FCVT_S_D_INX: |
| 12073 | case RISCV::FCVT_S_H: |
| 12074 | case RISCV::FCVT_S_H_INX: |
| 12075 | case RISCV::FCVT_S_L: |
| 12076 | case RISCV::FCVT_S_LU: |
| 12077 | case RISCV::FCVT_S_LU_INX: |
| 12078 | case RISCV::FCVT_S_L_INX: |
| 12079 | case RISCV::FCVT_S_Q: |
| 12080 | case RISCV::FCVT_S_W: |
| 12081 | case RISCV::FCVT_S_WU: |
| 12082 | case RISCV::FCVT_S_WU_INX: |
| 12083 | case RISCV::FCVT_S_W_INX: |
| 12084 | case RISCV::FCVT_WU_D: |
| 12085 | case RISCV::FCVT_WU_D_IN32X: |
| 12086 | case RISCV::FCVT_WU_D_INX: |
| 12087 | case RISCV::FCVT_WU_H: |
| 12088 | case RISCV::FCVT_WU_H_INX: |
| 12089 | case RISCV::FCVT_WU_Q: |
| 12090 | case RISCV::FCVT_WU_S: |
| 12091 | case RISCV::FCVT_WU_S_INX: |
| 12092 | case RISCV::FCVT_W_D: |
| 12093 | case RISCV::FCVT_W_D_IN32X: |
| 12094 | case RISCV::FCVT_W_D_INX: |
| 12095 | case RISCV::FCVT_W_H: |
| 12096 | case RISCV::FCVT_W_H_INX: |
| 12097 | case RISCV::FCVT_W_Q: |
| 12098 | case RISCV::FCVT_W_S: |
| 12099 | case RISCV::FCVT_W_S_INX: |
| 12100 | case RISCV::FROUNDNX_D: |
| 12101 | case RISCV::FROUNDNX_H: |
| 12102 | case RISCV::FROUNDNX_Q: |
| 12103 | case RISCV::FROUNDNX_S: |
| 12104 | case RISCV::FROUND_D: |
| 12105 | case RISCV::FROUND_H: |
| 12106 | case RISCV::FROUND_Q: |
| 12107 | case RISCV::FROUND_S: |
| 12108 | case RISCV::FSQRT_D: |
| 12109 | case RISCV::FSQRT_D_IN32X: |
| 12110 | case RISCV::FSQRT_D_INX: |
| 12111 | case RISCV::FSQRT_H: |
| 12112 | case RISCV::FSQRT_H_INX: |
| 12113 | case RISCV::FSQRT_Q: |
| 12114 | case RISCV::FSQRT_S: |
| 12115 | case RISCV::FSQRT_S_INX: { |
| 12116 | switch (OpNum) { |
| 12117 | case 1: |
| 12118 | // op: rs1 |
| 12119 | return 15; |
| 12120 | case 2: |
| 12121 | // op: frm |
| 12122 | return 12; |
| 12123 | case 0: |
| 12124 | // op: rd |
| 12125 | return 7; |
| 12126 | } |
| 12127 | break; |
| 12128 | } |
| 12129 | case RISCV::AIF_FROUND_PS: { |
| 12130 | switch (OpNum) { |
| 12131 | case 1: |
| 12132 | // op: rs1 |
| 12133 | return 15; |
| 12134 | case 2: |
| 12135 | // op: rm |
| 12136 | return 12; |
| 12137 | case 0: |
| 12138 | // op: rd |
| 12139 | return 7; |
| 12140 | } |
| 12141 | break; |
| 12142 | } |
| 12143 | case RISCV::AIF_FSC32B_PS: |
| 12144 | case RISCV::AIF_FSC32H_PS: |
| 12145 | case RISCV::AIF_FSC32W_PS: |
| 12146 | case RISCV::AIF_FSCBG_PS: |
| 12147 | case RISCV::AIF_FSCBL_PS: |
| 12148 | case RISCV::AIF_FSCB_PS: |
| 12149 | case RISCV::AIF_FSCHG_PS: |
| 12150 | case RISCV::AIF_FSCHL_PS: |
| 12151 | case RISCV::AIF_FSCH_PS: |
| 12152 | case RISCV::AIF_FSCWG_PS: |
| 12153 | case RISCV::AIF_FSCWL_PS: |
| 12154 | case RISCV::AIF_FSCW_PS: { |
| 12155 | switch (OpNum) { |
| 12156 | case 1: |
| 12157 | // op: rs1 |
| 12158 | return 15; |
| 12159 | case 2: |
| 12160 | // op: rs2 |
| 12161 | return 20; |
| 12162 | case 0: |
| 12163 | // op: rs3 |
| 12164 | return 7; |
| 12165 | } |
| 12166 | break; |
| 12167 | } |
| 12168 | case RISCV::NCLIP: |
| 12169 | case RISCV::NCLIPR: |
| 12170 | case RISCV::NCLIPRU: |
| 12171 | case RISCV::NCLIPU: |
| 12172 | case RISCV::NSRA: |
| 12173 | case RISCV::NSRAR: |
| 12174 | case RISCV::NSRL: |
| 12175 | case RISCV::PNCLIPRU_BS: |
| 12176 | case RISCV::PNCLIPRU_HS: |
| 12177 | case RISCV::PNCLIPR_BS: |
| 12178 | case RISCV::PNCLIPR_HS: |
| 12179 | case RISCV::PNCLIPU_BS: |
| 12180 | case RISCV::PNCLIPU_HS: |
| 12181 | case RISCV::PNCLIP_BS: |
| 12182 | case RISCV::PNCLIP_HS: |
| 12183 | case RISCV::PNSRAR_BS: |
| 12184 | case RISCV::PNSRAR_HS: |
| 12185 | case RISCV::PNSRA_BS: |
| 12186 | case RISCV::PNSRA_HS: |
| 12187 | case RISCV::PNSRL_BS: |
| 12188 | case RISCV::PNSRL_HS: |
| 12189 | case RISCV::PREDSUMU_DBS: |
| 12190 | case RISCV::PREDSUMU_DHS: |
| 12191 | case RISCV::PREDSUM_DBS: |
| 12192 | case RISCV::PREDSUM_DHS: { |
| 12193 | switch (OpNum) { |
| 12194 | case 1: |
| 12195 | // op: rs1 |
| 12196 | return 16; |
| 12197 | case 0: |
| 12198 | // op: rd |
| 12199 | return 7; |
| 12200 | case 2: |
| 12201 | // op: rs2 |
| 12202 | return 20; |
| 12203 | } |
| 12204 | break; |
| 12205 | } |
| 12206 | case RISCV::NCLIPI: |
| 12207 | case RISCV::NCLIPIU: |
| 12208 | case RISCV::NCLIPRI: |
| 12209 | case RISCV::NCLIPRIU: |
| 12210 | case RISCV::NSRAI: |
| 12211 | case RISCV::NSRARI: |
| 12212 | case RISCV::NSRLI: |
| 12213 | case RISCV::PNCLIPIU_B: |
| 12214 | case RISCV::PNCLIPIU_H: |
| 12215 | case RISCV::PNCLIPI_B: |
| 12216 | case RISCV::PNCLIPI_H: |
| 12217 | case RISCV::PNCLIPRIU_B: |
| 12218 | case RISCV::PNCLIPRIU_H: |
| 12219 | case RISCV::PNCLIPRI_B: |
| 12220 | case RISCV::PNCLIPRI_H: |
| 12221 | case RISCV::PNSRAI_B: |
| 12222 | case RISCV::PNSRAI_H: |
| 12223 | case RISCV::PNSRARI_B: |
| 12224 | case RISCV::PNSRARI_H: |
| 12225 | case RISCV::PNSRLI_B: |
| 12226 | case RISCV::PNSRLI_H: { |
| 12227 | switch (OpNum) { |
| 12228 | case 1: |
| 12229 | // op: rs1 |
| 12230 | return 16; |
| 12231 | case 0: |
| 12232 | // op: rd |
| 12233 | return 7; |
| 12234 | case 2: |
| 12235 | // op: shamt |
| 12236 | return 20; |
| 12237 | } |
| 12238 | break; |
| 12239 | } |
| 12240 | case RISCV::PADD_DBS: |
| 12241 | case RISCV::PADD_DHS: |
| 12242 | case RISCV::PADD_DWS: |
| 12243 | case RISCV::PSLL_DBS: |
| 12244 | case RISCV::PSLL_DHS: |
| 12245 | case RISCV::PSLL_DWS: |
| 12246 | case RISCV::PSRA_DBS: |
| 12247 | case RISCV::PSRA_DHS: |
| 12248 | case RISCV::PSRA_DWS: |
| 12249 | case RISCV::PSRL_DBS: |
| 12250 | case RISCV::PSRL_DHS: |
| 12251 | case RISCV::PSRL_DWS: |
| 12252 | case RISCV::PSSHAR_DHS: |
| 12253 | case RISCV::PSSHAR_DWS: |
| 12254 | case RISCV::PSSHA_DHS: |
| 12255 | case RISCV::PSSHA_DWS: { |
| 12256 | switch (OpNum) { |
| 12257 | case 1: |
| 12258 | // op: rs1 |
| 12259 | return 16; |
| 12260 | case 0: |
| 12261 | // op: rd |
| 12262 | return 8; |
| 12263 | case 2: |
| 12264 | // op: rs2 |
| 12265 | return 20; |
| 12266 | } |
| 12267 | break; |
| 12268 | } |
| 12269 | case RISCV::ADDD: |
| 12270 | case RISCV::PAADDU_DB: |
| 12271 | case RISCV::PAADDU_DH: |
| 12272 | case RISCV::PAADDU_DW: |
| 12273 | case RISCV::PAADD_DB: |
| 12274 | case RISCV::PAADD_DH: |
| 12275 | case RISCV::PAADD_DW: |
| 12276 | case RISCV::PAAS_DHX: |
| 12277 | case RISCV::PABDU_DB: |
| 12278 | case RISCV::PABDU_DH: |
| 12279 | case RISCV::PABD_DB: |
| 12280 | case RISCV::PABD_DH: |
| 12281 | case RISCV::PADD_DB: |
| 12282 | case RISCV::PADD_DH: |
| 12283 | case RISCV::PADD_DW: |
| 12284 | case RISCV::PASA_DHX: |
| 12285 | case RISCV::PASUBU_DB: |
| 12286 | case RISCV::PASUBU_DH: |
| 12287 | case RISCV::PASUBU_DW: |
| 12288 | case RISCV::PASUB_DB: |
| 12289 | case RISCV::PASUB_DH: |
| 12290 | case RISCV::PASUB_DW: |
| 12291 | case RISCV::PAS_DHX: |
| 12292 | case RISCV::PMAXU_DB: |
| 12293 | case RISCV::PMAXU_DH: |
| 12294 | case RISCV::PMAXU_DW: |
| 12295 | case RISCV::PMAX_DB: |
| 12296 | case RISCV::PMAX_DH: |
| 12297 | case RISCV::PMAX_DW: |
| 12298 | case RISCV::PMINU_DB: |
| 12299 | case RISCV::PMINU_DH: |
| 12300 | case RISCV::PMINU_DW: |
| 12301 | case RISCV::PMIN_DB: |
| 12302 | case RISCV::PMIN_DH: |
| 12303 | case RISCV::PMIN_DW: |
| 12304 | case RISCV::PMSEQ_DB: |
| 12305 | case RISCV::PMSEQ_DH: |
| 12306 | case RISCV::PMSEQ_DW: |
| 12307 | case RISCV::PMSLTU_DB: |
| 12308 | case RISCV::PMSLTU_DH: |
| 12309 | case RISCV::PMSLTU_DW: |
| 12310 | case RISCV::PMSLT_DB: |
| 12311 | case RISCV::PMSLT_DH: |
| 12312 | case RISCV::PMSLT_DW: |
| 12313 | case RISCV::PPAIREO_DB: |
| 12314 | case RISCV::PPAIREO_DH: |
| 12315 | case RISCV::PPAIRE_DB: |
| 12316 | case RISCV::PPAIRE_DH: |
| 12317 | case RISCV::PPAIROE_DB: |
| 12318 | case RISCV::PPAIROE_DH: |
| 12319 | case RISCV::PPAIRO_DB: |
| 12320 | case RISCV::PPAIRO_DH: |
| 12321 | case RISCV::PSADDU_DB: |
| 12322 | case RISCV::PSADDU_DH: |
| 12323 | case RISCV::PSADDU_DW: |
| 12324 | case RISCV::PSADD_DB: |
| 12325 | case RISCV::PSADD_DH: |
| 12326 | case RISCV::PSADD_DW: |
| 12327 | case RISCV::PSAS_DHX: |
| 12328 | case RISCV::PSA_DHX: |
| 12329 | case RISCV::PSH1ADD_DH: |
| 12330 | case RISCV::PSH1ADD_DW: |
| 12331 | case RISCV::PSSA_DHX: |
| 12332 | case RISCV::PSSH1SADD_DH: |
| 12333 | case RISCV::PSSH1SADD_DW: |
| 12334 | case RISCV::PSSUBU_DB: |
| 12335 | case RISCV::PSSUBU_DH: |
| 12336 | case RISCV::PSSUBU_DW: |
| 12337 | case RISCV::PSSUB_DB: |
| 12338 | case RISCV::PSSUB_DH: |
| 12339 | case RISCV::PSSUB_DW: |
| 12340 | case RISCV::PSUB_DB: |
| 12341 | case RISCV::PSUB_DH: |
| 12342 | case RISCV::PSUB_DW: |
| 12343 | case RISCV::SUBD: { |
| 12344 | switch (OpNum) { |
| 12345 | case 1: |
| 12346 | // op: rs1 |
| 12347 | return 16; |
| 12348 | case 0: |
| 12349 | // op: rd |
| 12350 | return 8; |
| 12351 | case 2: |
| 12352 | // op: rs2 |
| 12353 | return 21; |
| 12354 | } |
| 12355 | break; |
| 12356 | } |
| 12357 | case RISCV::PSATI_DH: |
| 12358 | case RISCV::PSATI_DW: |
| 12359 | case RISCV::PSLLI_DB: |
| 12360 | case RISCV::PSLLI_DH: |
| 12361 | case RISCV::PSLLI_DW: |
| 12362 | case RISCV::PSRAI_DB: |
| 12363 | case RISCV::PSRAI_DH: |
| 12364 | case RISCV::PSRAI_DW: |
| 12365 | case RISCV::PSRARI_DH: |
| 12366 | case RISCV::PSRARI_DW: |
| 12367 | case RISCV::PSRLI_DB: |
| 12368 | case RISCV::PSRLI_DH: |
| 12369 | case RISCV::PSRLI_DW: |
| 12370 | case RISCV::PSSLAI_DH: |
| 12371 | case RISCV::PSSLAI_DW: |
| 12372 | case RISCV::PUSATI_DH: |
| 12373 | case RISCV::PUSATI_DW: { |
| 12374 | switch (OpNum) { |
| 12375 | case 1: |
| 12376 | // op: rs1 |
| 12377 | return 16; |
| 12378 | case 0: |
| 12379 | // op: rd |
| 12380 | return 8; |
| 12381 | case 2: |
| 12382 | // op: shamt |
| 12383 | return 20; |
| 12384 | } |
| 12385 | break; |
| 12386 | } |
| 12387 | case RISCV::PSABS_DB: |
| 12388 | case RISCV::PSABS_DH: |
| 12389 | case RISCV::PSEXT_DH_B: |
| 12390 | case RISCV::PSEXT_DW_B: |
| 12391 | case RISCV::PSEXT_DW_H: { |
| 12392 | switch (OpNum) { |
| 12393 | case 1: |
| 12394 | // op: rs1 |
| 12395 | return 16; |
| 12396 | case 0: |
| 12397 | // op: rd |
| 12398 | return 8; |
| 12399 | } |
| 12400 | break; |
| 12401 | } |
| 12402 | case RISCV::C_ADD: { |
| 12403 | switch (OpNum) { |
| 12404 | case 1: |
| 12405 | // op: rs1 |
| 12406 | return 7; |
| 12407 | case 2: |
| 12408 | // op: rs2 |
| 12409 | return 2; |
| 12410 | } |
| 12411 | break; |
| 12412 | } |
| 12413 | case RISCV::QC_C_BEXTI: |
| 12414 | case RISCV::QC_C_BSETI: { |
| 12415 | switch (OpNum) { |
| 12416 | case 1: |
| 12417 | // op: rs1 |
| 12418 | return 7; |
| 12419 | case 2: |
| 12420 | // op: shamt |
| 12421 | return 2; |
| 12422 | } |
| 12423 | break; |
| 12424 | } |
| 12425 | case RISCV::NDS_FCVT_BF16_S: |
| 12426 | case RISCV::NDS_FCVT_S_BF16: { |
| 12427 | switch (OpNum) { |
| 12428 | case 1: |
| 12429 | // op: rs2 |
| 12430 | return 20; |
| 12431 | case 0: |
| 12432 | // op: rd |
| 12433 | return 7; |
| 12434 | } |
| 12435 | break; |
| 12436 | } |
| 12437 | case RISCV::HFENCE_GVMA: |
| 12438 | case RISCV::HFENCE_VVMA: |
| 12439 | case RISCV::HINVAL_GVMA: |
| 12440 | case RISCV::HINVAL_VVMA: |
| 12441 | case RISCV::SFENCE_VMA: |
| 12442 | case RISCV::SF_VTMV_T_V: |
| 12443 | case RISCV::SINVAL_VMA: |
| 12444 | case RISCV::TH_SFENCE_VMAS: { |
| 12445 | switch (OpNum) { |
| 12446 | case 1: |
| 12447 | // op: rs2 |
| 12448 | return 20; |
| 12449 | case 0: |
| 12450 | // op: rs1 |
| 12451 | return 15; |
| 12452 | } |
| 12453 | break; |
| 12454 | } |
| 12455 | case RISCV::TH_LDD: |
| 12456 | case RISCV::TH_LWD: |
| 12457 | case RISCV::TH_LWUD: |
| 12458 | case RISCV::TH_SDD: |
| 12459 | case RISCV::TH_SWD: { |
| 12460 | switch (OpNum) { |
| 12461 | case 1: |
| 12462 | // op: rs2 |
| 12463 | return 20; |
| 12464 | case 2: |
| 12465 | // op: rs1 |
| 12466 | return 15; |
| 12467 | case 0: |
| 12468 | // op: rd |
| 12469 | return 7; |
| 12470 | case 3: |
| 12471 | // op: uimm2 |
| 12472 | return 25; |
| 12473 | } |
| 12474 | break; |
| 12475 | } |
| 12476 | case RISCV::AIF_AMOADDG_D: |
| 12477 | case RISCV::AIF_AMOADDG_W: |
| 12478 | case RISCV::AIF_AMOADDL_D: |
| 12479 | case RISCV::AIF_AMOADDL_W: |
| 12480 | case RISCV::AIF_AMOANDG_D: |
| 12481 | case RISCV::AIF_AMOANDG_W: |
| 12482 | case RISCV::AIF_AMOANDL_D: |
| 12483 | case RISCV::AIF_AMOANDL_W: |
| 12484 | case RISCV::AIF_AMOCMPSWAPG_D: |
| 12485 | case RISCV::AIF_AMOCMPSWAPG_W: |
| 12486 | case RISCV::AIF_AMOCMPSWAPL_D: |
| 12487 | case RISCV::AIF_AMOCMPSWAPL_W: |
| 12488 | case RISCV::AIF_AMOMAXG_D: |
| 12489 | case RISCV::AIF_AMOMAXG_W: |
| 12490 | case RISCV::AIF_AMOMAXL_D: |
| 12491 | case RISCV::AIF_AMOMAXL_W: |
| 12492 | case RISCV::AIF_AMOMAXUG_D: |
| 12493 | case RISCV::AIF_AMOMAXUG_W: |
| 12494 | case RISCV::AIF_AMOMAXUL_D: |
| 12495 | case RISCV::AIF_AMOMAXUL_W: |
| 12496 | case RISCV::AIF_AMOMING_D: |
| 12497 | case RISCV::AIF_AMOMING_W: |
| 12498 | case RISCV::AIF_AMOMINL_D: |
| 12499 | case RISCV::AIF_AMOMINL_W: |
| 12500 | case RISCV::AIF_AMOMINUG_D: |
| 12501 | case RISCV::AIF_AMOMINUG_W: |
| 12502 | case RISCV::AIF_AMOMINUL_D: |
| 12503 | case RISCV::AIF_AMOMINUL_W: |
| 12504 | case RISCV::AIF_AMOORG_D: |
| 12505 | case RISCV::AIF_AMOORG_W: |
| 12506 | case RISCV::AIF_AMOORL_D: |
| 12507 | case RISCV::AIF_AMOORL_W: |
| 12508 | case RISCV::AIF_AMOSWAPG_D: |
| 12509 | case RISCV::AIF_AMOSWAPG_W: |
| 12510 | case RISCV::AIF_AMOSWAPL_D: |
| 12511 | case RISCV::AIF_AMOSWAPL_W: |
| 12512 | case RISCV::AIF_AMOXORG_D: |
| 12513 | case RISCV::AIF_AMOXORG_W: |
| 12514 | case RISCV::AIF_AMOXORL_D: |
| 12515 | case RISCV::AIF_AMOXORL_W: |
| 12516 | case RISCV::AMOADD_B: |
| 12517 | case RISCV::AMOADD_B_AQ: |
| 12518 | case RISCV::AMOADD_B_AQRL: |
| 12519 | case RISCV::AMOADD_B_RL: |
| 12520 | case RISCV::AMOADD_D: |
| 12521 | case RISCV::AMOADD_D_AQ: |
| 12522 | case RISCV::AMOADD_D_AQRL: |
| 12523 | case RISCV::AMOADD_D_RL: |
| 12524 | case RISCV::AMOADD_H: |
| 12525 | case RISCV::AMOADD_H_AQ: |
| 12526 | case RISCV::AMOADD_H_AQRL: |
| 12527 | case RISCV::AMOADD_H_RL: |
| 12528 | case RISCV::AMOADD_W: |
| 12529 | case RISCV::AMOADD_W_AQ: |
| 12530 | case RISCV::AMOADD_W_AQRL: |
| 12531 | case RISCV::AMOADD_W_RL: |
| 12532 | case RISCV::AMOAND_B: |
| 12533 | case RISCV::AMOAND_B_AQ: |
| 12534 | case RISCV::AMOAND_B_AQRL: |
| 12535 | case RISCV::AMOAND_B_RL: |
| 12536 | case RISCV::AMOAND_D: |
| 12537 | case RISCV::AMOAND_D_AQ: |
| 12538 | case RISCV::AMOAND_D_AQRL: |
| 12539 | case RISCV::AMOAND_D_RL: |
| 12540 | case RISCV::AMOAND_H: |
| 12541 | case RISCV::AMOAND_H_AQ: |
| 12542 | case RISCV::AMOAND_H_AQRL: |
| 12543 | case RISCV::AMOAND_H_RL: |
| 12544 | case RISCV::AMOAND_W: |
| 12545 | case RISCV::AMOAND_W_AQ: |
| 12546 | case RISCV::AMOAND_W_AQRL: |
| 12547 | case RISCV::AMOAND_W_RL: |
| 12548 | case RISCV::AMOMAXU_B: |
| 12549 | case RISCV::AMOMAXU_B_AQ: |
| 12550 | case RISCV::AMOMAXU_B_AQRL: |
| 12551 | case RISCV::AMOMAXU_B_RL: |
| 12552 | case RISCV::AMOMAXU_D: |
| 12553 | case RISCV::AMOMAXU_D_AQ: |
| 12554 | case RISCV::AMOMAXU_D_AQRL: |
| 12555 | case RISCV::AMOMAXU_D_RL: |
| 12556 | case RISCV::AMOMAXU_H: |
| 12557 | case RISCV::AMOMAXU_H_AQ: |
| 12558 | case RISCV::AMOMAXU_H_AQRL: |
| 12559 | case RISCV::AMOMAXU_H_RL: |
| 12560 | case RISCV::AMOMAXU_W: |
| 12561 | case RISCV::AMOMAXU_W_AQ: |
| 12562 | case RISCV::AMOMAXU_W_AQRL: |
| 12563 | case RISCV::AMOMAXU_W_RL: |
| 12564 | case RISCV::AMOMAX_B: |
| 12565 | case RISCV::AMOMAX_B_AQ: |
| 12566 | case RISCV::AMOMAX_B_AQRL: |
| 12567 | case RISCV::AMOMAX_B_RL: |
| 12568 | case RISCV::AMOMAX_D: |
| 12569 | case RISCV::AMOMAX_D_AQ: |
| 12570 | case RISCV::AMOMAX_D_AQRL: |
| 12571 | case RISCV::AMOMAX_D_RL: |
| 12572 | case RISCV::AMOMAX_H: |
| 12573 | case RISCV::AMOMAX_H_AQ: |
| 12574 | case RISCV::AMOMAX_H_AQRL: |
| 12575 | case RISCV::AMOMAX_H_RL: |
| 12576 | case RISCV::AMOMAX_W: |
| 12577 | case RISCV::AMOMAX_W_AQ: |
| 12578 | case RISCV::AMOMAX_W_AQRL: |
| 12579 | case RISCV::AMOMAX_W_RL: |
| 12580 | case RISCV::AMOMINU_B: |
| 12581 | case RISCV::AMOMINU_B_AQ: |
| 12582 | case RISCV::AMOMINU_B_AQRL: |
| 12583 | case RISCV::AMOMINU_B_RL: |
| 12584 | case RISCV::AMOMINU_D: |
| 12585 | case RISCV::AMOMINU_D_AQ: |
| 12586 | case RISCV::AMOMINU_D_AQRL: |
| 12587 | case RISCV::AMOMINU_D_RL: |
| 12588 | case RISCV::AMOMINU_H: |
| 12589 | case RISCV::AMOMINU_H_AQ: |
| 12590 | case RISCV::AMOMINU_H_AQRL: |
| 12591 | case RISCV::AMOMINU_H_RL: |
| 12592 | case RISCV::AMOMINU_W: |
| 12593 | case RISCV::AMOMINU_W_AQ: |
| 12594 | case RISCV::AMOMINU_W_AQRL: |
| 12595 | case RISCV::AMOMINU_W_RL: |
| 12596 | case RISCV::AMOMIN_B: |
| 12597 | case RISCV::AMOMIN_B_AQ: |
| 12598 | case RISCV::AMOMIN_B_AQRL: |
| 12599 | case RISCV::AMOMIN_B_RL: |
| 12600 | case RISCV::AMOMIN_D: |
| 12601 | case RISCV::AMOMIN_D_AQ: |
| 12602 | case RISCV::AMOMIN_D_AQRL: |
| 12603 | case RISCV::AMOMIN_D_RL: |
| 12604 | case RISCV::AMOMIN_H: |
| 12605 | case RISCV::AMOMIN_H_AQ: |
| 12606 | case RISCV::AMOMIN_H_AQRL: |
| 12607 | case RISCV::AMOMIN_H_RL: |
| 12608 | case RISCV::AMOMIN_W: |
| 12609 | case RISCV::AMOMIN_W_AQ: |
| 12610 | case RISCV::AMOMIN_W_AQRL: |
| 12611 | case RISCV::AMOMIN_W_RL: |
| 12612 | case RISCV::AMOOR_B: |
| 12613 | case RISCV::AMOOR_B_AQ: |
| 12614 | case RISCV::AMOOR_B_AQRL: |
| 12615 | case RISCV::AMOOR_B_RL: |
| 12616 | case RISCV::AMOOR_D: |
| 12617 | case RISCV::AMOOR_D_AQ: |
| 12618 | case RISCV::AMOOR_D_AQRL: |
| 12619 | case RISCV::AMOOR_D_RL: |
| 12620 | case RISCV::AMOOR_H: |
| 12621 | case RISCV::AMOOR_H_AQ: |
| 12622 | case RISCV::AMOOR_H_AQRL: |
| 12623 | case RISCV::AMOOR_H_RL: |
| 12624 | case RISCV::AMOOR_W: |
| 12625 | case RISCV::AMOOR_W_AQ: |
| 12626 | case RISCV::AMOOR_W_AQRL: |
| 12627 | case RISCV::AMOOR_W_RL: |
| 12628 | case RISCV::AMOSWAP_B: |
| 12629 | case RISCV::AMOSWAP_B_AQ: |
| 12630 | case RISCV::AMOSWAP_B_AQRL: |
| 12631 | case RISCV::AMOSWAP_B_RL: |
| 12632 | case RISCV::AMOSWAP_D: |
| 12633 | case RISCV::AMOSWAP_D_AQ: |
| 12634 | case RISCV::AMOSWAP_D_AQRL: |
| 12635 | case RISCV::AMOSWAP_D_RL: |
| 12636 | case RISCV::AMOSWAP_H: |
| 12637 | case RISCV::AMOSWAP_H_AQ: |
| 12638 | case RISCV::AMOSWAP_H_AQRL: |
| 12639 | case RISCV::AMOSWAP_H_RL: |
| 12640 | case RISCV::AMOSWAP_W: |
| 12641 | case RISCV::AMOSWAP_W_AQ: |
| 12642 | case RISCV::AMOSWAP_W_AQRL: |
| 12643 | case RISCV::AMOSWAP_W_RL: |
| 12644 | case RISCV::AMOXOR_B: |
| 12645 | case RISCV::AMOXOR_B_AQ: |
| 12646 | case RISCV::AMOXOR_B_AQRL: |
| 12647 | case RISCV::AMOXOR_B_RL: |
| 12648 | case RISCV::AMOXOR_D: |
| 12649 | case RISCV::AMOXOR_D_AQ: |
| 12650 | case RISCV::AMOXOR_D_AQRL: |
| 12651 | case RISCV::AMOXOR_D_RL: |
| 12652 | case RISCV::AMOXOR_H: |
| 12653 | case RISCV::AMOXOR_H_AQ: |
| 12654 | case RISCV::AMOXOR_H_AQRL: |
| 12655 | case RISCV::AMOXOR_H_RL: |
| 12656 | case RISCV::AMOXOR_W: |
| 12657 | case RISCV::AMOXOR_W_AQ: |
| 12658 | case RISCV::AMOXOR_W_AQRL: |
| 12659 | case RISCV::AMOXOR_W_RL: |
| 12660 | case RISCV::NDS_LEA_B_ZE: |
| 12661 | case RISCV::NDS_LEA_D: |
| 12662 | case RISCV::NDS_LEA_D_ZE: |
| 12663 | case RISCV::NDS_LEA_H: |
| 12664 | case RISCV::NDS_LEA_H_ZE: |
| 12665 | case RISCV::NDS_LEA_W: |
| 12666 | case RISCV::NDS_LEA_W_ZE: |
| 12667 | case RISCV::SC_D: |
| 12668 | case RISCV::SC_D_AQ: |
| 12669 | case RISCV::SC_D_AQRL: |
| 12670 | case RISCV::SC_D_RL: |
| 12671 | case RISCV::SC_W: |
| 12672 | case RISCV::SC_W_AQ: |
| 12673 | case RISCV::SC_W_AQRL: |
| 12674 | case RISCV::SC_W_RL: |
| 12675 | case RISCV::SSAMOSWAP_D: |
| 12676 | case RISCV::SSAMOSWAP_D_AQ: |
| 12677 | case RISCV::SSAMOSWAP_D_AQRL: |
| 12678 | case RISCV::SSAMOSWAP_D_RL: |
| 12679 | case RISCV::SSAMOSWAP_W: |
| 12680 | case RISCV::SSAMOSWAP_W_AQ: |
| 12681 | case RISCV::SSAMOSWAP_W_AQRL: |
| 12682 | case RISCV::SSAMOSWAP_W_RL: { |
| 12683 | switch (OpNum) { |
| 12684 | case 1: |
| 12685 | // op: rs2 |
| 12686 | return 20; |
| 12687 | case 2: |
| 12688 | // op: rs1 |
| 12689 | return 15; |
| 12690 | case 0: |
| 12691 | // op: rd |
| 12692 | return 7; |
| 12693 | } |
| 12694 | break; |
| 12695 | } |
| 12696 | case RISCV::CM_MVA01S: |
| 12697 | case RISCV::CM_MVSA01: |
| 12698 | case RISCV::QC_CM_MVA01S: |
| 12699 | case RISCV::QC_CM_MVSA01: { |
| 12700 | switch (OpNum) { |
| 12701 | case 1: |
| 12702 | // op: rs2 |
| 12703 | return 2; |
| 12704 | case 0: |
| 12705 | // op: rs1 |
| 12706 | return 7; |
| 12707 | } |
| 12708 | break; |
| 12709 | } |
| 12710 | case RISCV::VFMV_S_F: |
| 12711 | case RISCV::VMV_S_X: { |
| 12712 | switch (OpNum) { |
| 12713 | case 1: |
| 12714 | // op: vd |
| 12715 | return 7; |
| 12716 | case 2: |
| 12717 | // op: rs1 |
| 12718 | return 15; |
| 12719 | } |
| 12720 | break; |
| 12721 | } |
| 12722 | case RISCV::SMT_VMADOT: |
| 12723 | case RISCV::SMT_VMADOTSU: |
| 12724 | case RISCV::SMT_VMADOTU: |
| 12725 | case RISCV::SMT_VMADOTUS: { |
| 12726 | switch (OpNum) { |
| 12727 | case 1: |
| 12728 | // op: vd |
| 12729 | return 7; |
| 12730 | case 2: |
| 12731 | // op: vs1 |
| 12732 | return 15; |
| 12733 | case 3: |
| 12734 | // op: vs2 |
| 12735 | return 20; |
| 12736 | } |
| 12737 | break; |
| 12738 | } |
| 12739 | case RISCV::SMT_VMADOT1: |
| 12740 | case RISCV::SMT_VMADOT1SU: |
| 12741 | case RISCV::SMT_VMADOT1U: |
| 12742 | case RISCV::SMT_VMADOT1US: |
| 12743 | case RISCV::SMT_VMADOT2: |
| 12744 | case RISCV::SMT_VMADOT2SU: |
| 12745 | case RISCV::SMT_VMADOT2U: |
| 12746 | case RISCV::SMT_VMADOT2US: |
| 12747 | case RISCV::SMT_VMADOT3: |
| 12748 | case RISCV::SMT_VMADOT3SU: |
| 12749 | case RISCV::SMT_VMADOT3U: |
| 12750 | case RISCV::SMT_VMADOT3US: { |
| 12751 | switch (OpNum) { |
| 12752 | case 1: |
| 12753 | // op: vd |
| 12754 | return 7; |
| 12755 | case 2: |
| 12756 | // op: vs1 |
| 12757 | return 16; |
| 12758 | case 3: |
| 12759 | // op: vs2 |
| 12760 | return 20; |
| 12761 | } |
| 12762 | break; |
| 12763 | } |
| 12764 | case RISCV::VAESKF2_VI: |
| 12765 | case RISCV::VSM3C_VI: { |
| 12766 | switch (OpNum) { |
| 12767 | case 1: |
| 12768 | // op: vd |
| 12769 | return 7; |
| 12770 | case 2: |
| 12771 | // op: vs2 |
| 12772 | return 20; |
| 12773 | case 3: |
| 12774 | // op: imm |
| 12775 | return 15; |
| 12776 | } |
| 12777 | break; |
| 12778 | } |
| 12779 | case RISCV::VGHSH_VS: |
| 12780 | case RISCV::VGHSH_VV: |
| 12781 | case RISCV::VSHA2CH_VV: |
| 12782 | case RISCV::VSHA2CL_VV: |
| 12783 | case RISCV::VSHA2MS_VV: { |
| 12784 | switch (OpNum) { |
| 12785 | case 1: |
| 12786 | // op: vd |
| 12787 | return 7; |
| 12788 | case 2: |
| 12789 | // op: vs2 |
| 12790 | return 20; |
| 12791 | case 3: |
| 12792 | // op: vs1 |
| 12793 | return 15; |
| 12794 | } |
| 12795 | break; |
| 12796 | } |
| 12797 | case RISCV::VAESDF_VS: |
| 12798 | case RISCV::VAESDF_VV: |
| 12799 | case RISCV::VAESDM_VS: |
| 12800 | case RISCV::VAESDM_VV: |
| 12801 | case RISCV::VAESEF_VS: |
| 12802 | case RISCV::VAESEF_VV: |
| 12803 | case RISCV::VAESEM_VS: |
| 12804 | case RISCV::VAESEM_VV: |
| 12805 | case RISCV::VAESZ_VS: |
| 12806 | case RISCV::VGMUL_VS: |
| 12807 | case RISCV::VGMUL_VV: |
| 12808 | case RISCV::VSM4R_VS: |
| 12809 | case RISCV::VSM4R_VV: { |
| 12810 | switch (OpNum) { |
| 12811 | case 1: |
| 12812 | // op: vd |
| 12813 | return 7; |
| 12814 | case 2: |
| 12815 | // op: vs2 |
| 12816 | return 20; |
| 12817 | } |
| 12818 | break; |
| 12819 | } |
| 12820 | case RISCV::SF_VFWMACC_4x4x4: |
| 12821 | case RISCV::SF_VQMACCSU_2x8x2: |
| 12822 | case RISCV::SF_VQMACCSU_4x8x4: |
| 12823 | case RISCV::SF_VQMACCUS_2x8x2: |
| 12824 | case RISCV::SF_VQMACCUS_4x8x4: |
| 12825 | case RISCV::SF_VQMACCU_2x8x2: |
| 12826 | case RISCV::SF_VQMACCU_4x8x4: |
| 12827 | case RISCV::SF_VQMACC_2x8x2: |
| 12828 | case RISCV::SF_VQMACC_4x8x4: { |
| 12829 | switch (OpNum) { |
| 12830 | case 1: |
| 12831 | // op: vd |
| 12832 | return 7; |
| 12833 | case 3: |
| 12834 | // op: vs2 |
| 12835 | return 20; |
| 12836 | case 2: |
| 12837 | // op: vs1 |
| 12838 | return 15; |
| 12839 | } |
| 12840 | break; |
| 12841 | } |
| 12842 | case RISCV::VDOTA4SU_VX: |
| 12843 | case RISCV::VDOTA4US_VX: |
| 12844 | case RISCV::VDOTA4U_VX: |
| 12845 | case RISCV::VDOTA4_VX: { |
| 12846 | switch (OpNum) { |
| 12847 | case 1: |
| 12848 | // op: vd |
| 12849 | return 7; |
| 12850 | case 4: |
| 12851 | // op: vm |
| 12852 | return 25; |
| 12853 | case 2: |
| 12854 | // op: vs2 |
| 12855 | return 20; |
| 12856 | case 3: |
| 12857 | // op: rs1 |
| 12858 | return 15; |
| 12859 | } |
| 12860 | break; |
| 12861 | } |
| 12862 | case RISCV::VDOTA4SU_VV: |
| 12863 | case RISCV::VDOTA4U_VV: |
| 12864 | case RISCV::VDOTA4_VV: { |
| 12865 | switch (OpNum) { |
| 12866 | case 1: |
| 12867 | // op: vd |
| 12868 | return 7; |
| 12869 | case 4: |
| 12870 | // op: vm |
| 12871 | return 25; |
| 12872 | case 2: |
| 12873 | // op: vs2 |
| 12874 | return 20; |
| 12875 | case 3: |
| 12876 | // op: vs1 |
| 12877 | return 15; |
| 12878 | } |
| 12879 | break; |
| 12880 | } |
| 12881 | case RISCV::TH_VMAQASU_VX: |
| 12882 | case RISCV::TH_VMAQAUS_VX: |
| 12883 | case RISCV::TH_VMAQAU_VX: |
| 12884 | case RISCV::TH_VMAQA_VX: |
| 12885 | case RISCV::VFMACC_VF: |
| 12886 | case RISCV::VFMADD_VF: |
| 12887 | case RISCV::VFMSAC_VF: |
| 12888 | case RISCV::VFMSUB_VF: |
| 12889 | case RISCV::VFNMACC_VF: |
| 12890 | case RISCV::VFNMADD_VF: |
| 12891 | case RISCV::VFNMSAC_VF: |
| 12892 | case RISCV::VFNMSUB_VF: |
| 12893 | case RISCV::VFWMACCBF16_VF: |
| 12894 | case RISCV::VFWMACC_VF: |
| 12895 | case RISCV::VFWMSAC_VF: |
| 12896 | case RISCV::VFWNMACC_VF: |
| 12897 | case RISCV::VFWNMSAC_VF: |
| 12898 | case RISCV::VMACC_VX: |
| 12899 | case RISCV::VMADD_VX: |
| 12900 | case RISCV::VNMSAC_VX: |
| 12901 | case RISCV::VNMSUB_VX: |
| 12902 | case RISCV::VWMACCSU_VX: |
| 12903 | case RISCV::VWMACCUS_VX: |
| 12904 | case RISCV::VWMACCU_VX: |
| 12905 | case RISCV::VWMACC_VX: { |
| 12906 | switch (OpNum) { |
| 12907 | case 1: |
| 12908 | // op: vd |
| 12909 | return 7; |
| 12910 | case 4: |
| 12911 | // op: vm |
| 12912 | return 25; |
| 12913 | case 3: |
| 12914 | // op: vs2 |
| 12915 | return 20; |
| 12916 | case 2: |
| 12917 | // op: rs1 |
| 12918 | return 15; |
| 12919 | } |
| 12920 | break; |
| 12921 | } |
| 12922 | case RISCV::TH_VMAQASU_VV: |
| 12923 | case RISCV::TH_VMAQAU_VV: |
| 12924 | case RISCV::TH_VMAQA_VV: |
| 12925 | case RISCV::VFMACC_VV: |
| 12926 | case RISCV::VFMADD_VV: |
| 12927 | case RISCV::VFMSAC_VV: |
| 12928 | case RISCV::VFMSUB_VV: |
| 12929 | case RISCV::VFNMACC_VV: |
| 12930 | case RISCV::VFNMADD_VV: |
| 12931 | case RISCV::VFNMSAC_VV: |
| 12932 | case RISCV::VFNMSUB_VV: |
| 12933 | case RISCV::VFWMACCBF16_VV: |
| 12934 | case RISCV::VFWMACC_VV: |
| 12935 | case RISCV::VFWMSAC_VV: |
| 12936 | case RISCV::VFWNMACC_VV: |
| 12937 | case RISCV::VFWNMSAC_VV: |
| 12938 | case RISCV::VMACC_VV: |
| 12939 | case RISCV::VMADD_VV: |
| 12940 | case RISCV::VNMSAC_VV: |
| 12941 | case RISCV::VNMSUB_VV: |
| 12942 | case RISCV::VWMACCSU_VV: |
| 12943 | case RISCV::VWMACCU_VV: |
| 12944 | case RISCV::VWMACC_VV: { |
| 12945 | switch (OpNum) { |
| 12946 | case 1: |
| 12947 | // op: vd |
| 12948 | return 7; |
| 12949 | case 4: |
| 12950 | // op: vm |
| 12951 | return 25; |
| 12952 | case 3: |
| 12953 | // op: vs2 |
| 12954 | return 20; |
| 12955 | case 2: |
| 12956 | // op: vs1 |
| 12957 | return 15; |
| 12958 | } |
| 12959 | break; |
| 12960 | } |
| 12961 | case RISCV::NDS_VFWCVT_F_B: |
| 12962 | case RISCV::NDS_VFWCVT_F_BU: |
| 12963 | case RISCV::NDS_VFWCVT_F_N: |
| 12964 | case RISCV::NDS_VFWCVT_F_NU: { |
| 12965 | switch (OpNum) { |
| 12966 | case 1: |
| 12967 | // op: vs |
| 12968 | return 20; |
| 12969 | case 0: |
| 12970 | // op: vd |
| 12971 | return 7; |
| 12972 | case 2: |
| 12973 | // op: vm |
| 12974 | return 25; |
| 12975 | } |
| 12976 | break; |
| 12977 | } |
| 12978 | case RISCV::NDS_VFNCVT_BF16_S: |
| 12979 | case RISCV::NDS_VFWCVT_S_BF16: { |
| 12980 | switch (OpNum) { |
| 12981 | case 1: |
| 12982 | // op: vs2 |
| 12983 | return 20; |
| 12984 | case 0: |
| 12985 | // op: vd |
| 12986 | return 7; |
| 12987 | } |
| 12988 | break; |
| 12989 | } |
| 12990 | case RISCV::NDS_VFPMADB_VF: |
| 12991 | case RISCV::NDS_VFPMADT_VF: { |
| 12992 | switch (OpNum) { |
| 12993 | case 1: |
| 12994 | // op: vs2 |
| 12995 | return 20; |
| 12996 | case 2: |
| 12997 | // op: rs1 |
| 12998 | return 15; |
| 12999 | case 0: |
| 13000 | // op: vd |
| 13001 | return 7; |
| 13002 | case 3: |
| 13003 | // op: vm |
| 13004 | return 25; |
| 13005 | } |
| 13006 | break; |
| 13007 | } |
| 13008 | case RISCV::SF_VC_I: { |
| 13009 | switch (OpNum) { |
| 13010 | case 1: |
| 13011 | // op: vs2 |
| 13012 | return 20; |
| 13013 | case 2: |
| 13014 | // op: vd |
| 13015 | return 7; |
| 13016 | case 3: |
| 13017 | // op: imm |
| 13018 | return 15; |
| 13019 | case 0: |
| 13020 | // op: funct6_lo2 |
| 13021 | return 26; |
| 13022 | } |
| 13023 | break; |
| 13024 | } |
| 13025 | case RISCV::SF_VC_X: { |
| 13026 | switch (OpNum) { |
| 13027 | case 1: |
| 13028 | // op: vs2 |
| 13029 | return 20; |
| 13030 | case 2: |
| 13031 | // op: vd |
| 13032 | return 7; |
| 13033 | case 3: |
| 13034 | // op: rs1 |
| 13035 | return 15; |
| 13036 | case 0: |
| 13037 | // op: funct6_lo2 |
| 13038 | return 26; |
| 13039 | } |
| 13040 | break; |
| 13041 | } |
| 13042 | case RISCV::SF_MM_E4M3_E4M3: |
| 13043 | case RISCV::SF_MM_E4M3_E5M2: |
| 13044 | case RISCV::SF_MM_E5M2_E4M3: |
| 13045 | case RISCV::SF_MM_E5M2_E5M2: |
| 13046 | case RISCV::SF_MM_S_S: |
| 13047 | case RISCV::SF_MM_S_U: |
| 13048 | case RISCV::SF_MM_U_S: |
| 13049 | case RISCV::SF_MM_U_U: { |
| 13050 | switch (OpNum) { |
| 13051 | case 1: |
| 13052 | // op: vs2 |
| 13053 | return 20; |
| 13054 | case 2: |
| 13055 | // op: vs1 |
| 13056 | return 15; |
| 13057 | case 0: |
| 13058 | // op: rd |
| 13059 | return 10; |
| 13060 | } |
| 13061 | break; |
| 13062 | } |
| 13063 | case RISCV::SF_MM_F_F: { |
| 13064 | switch (OpNum) { |
| 13065 | case 1: |
| 13066 | // op: vs2 |
| 13067 | return 20; |
| 13068 | case 2: |
| 13069 | // op: vs1 |
| 13070 | return 15; |
| 13071 | case 0: |
| 13072 | // op: rd |
| 13073 | return 9; |
| 13074 | } |
| 13075 | break; |
| 13076 | } |
| 13077 | case RISCV::AIF_MOV_M_X: { |
| 13078 | switch (OpNum) { |
| 13079 | case 2: |
| 13080 | // op: imm |
| 13081 | return 12; |
| 13082 | case 1: |
| 13083 | // op: rs1 |
| 13084 | return 15; |
| 13085 | case 0: |
| 13086 | // op: rd |
| 13087 | return 7; |
| 13088 | } |
| 13089 | break; |
| 13090 | } |
| 13091 | case RISCV::RI_VEXTRACT: { |
| 13092 | switch (OpNum) { |
| 13093 | case 2: |
| 13094 | // op: imm |
| 13095 | return 15; |
| 13096 | case 1: |
| 13097 | // op: vs2 |
| 13098 | return 20; |
| 13099 | case 0: |
| 13100 | // op: rd |
| 13101 | return 7; |
| 13102 | } |
| 13103 | break; |
| 13104 | } |
| 13105 | case RISCV::AIF_FADDI_PI: |
| 13106 | case RISCV::AIF_FANDI_PI: |
| 13107 | case RISCV::AIF_FSLLI_PI: |
| 13108 | case RISCV::AIF_FSRAI_PI: |
| 13109 | case RISCV::AIF_FSRLI_PI: { |
| 13110 | switch (OpNum) { |
| 13111 | case 2: |
| 13112 | // op: imm |
| 13113 | return 20; |
| 13114 | case 1: |
| 13115 | // op: rs1 |
| 13116 | return 15; |
| 13117 | case 0: |
| 13118 | // op: rd |
| 13119 | return 7; |
| 13120 | } |
| 13121 | break; |
| 13122 | } |
| 13123 | case RISCV::C_FLDSP: |
| 13124 | case RISCV::C_FLWSP: |
| 13125 | case RISCV::C_LDSP: |
| 13126 | case RISCV::C_LDSP_RV32: |
| 13127 | case RISCV::C_LWSP: |
| 13128 | case RISCV::C_LWSP_INX: { |
| 13129 | switch (OpNum) { |
| 13130 | case 2: |
| 13131 | // op: imm |
| 13132 | return 2; |
| 13133 | case 0: |
| 13134 | // op: rd |
| 13135 | return 7; |
| 13136 | } |
| 13137 | break; |
| 13138 | } |
| 13139 | case RISCV::C_ADDI: |
| 13140 | case RISCV::C_ADDIW: |
| 13141 | case RISCV::C_SLLI: { |
| 13142 | switch (OpNum) { |
| 13143 | case 2: |
| 13144 | // op: imm |
| 13145 | return 2; |
| 13146 | case 1: |
| 13147 | // op: rd |
| 13148 | return 7; |
| 13149 | } |
| 13150 | break; |
| 13151 | } |
| 13152 | case RISCV::C_ANDI: |
| 13153 | case RISCV::C_SRAI: |
| 13154 | case RISCV::C_SRLI: { |
| 13155 | switch (OpNum) { |
| 13156 | case 2: |
| 13157 | // op: imm |
| 13158 | return 2; |
| 13159 | case 1: |
| 13160 | // op: rs1 |
| 13161 | return 7; |
| 13162 | } |
| 13163 | break; |
| 13164 | } |
| 13165 | case RISCV::C_ADDI16SP: { |
| 13166 | switch (OpNum) { |
| 13167 | case 2: |
| 13168 | // op: imm |
| 13169 | return 2; |
| 13170 | } |
| 13171 | break; |
| 13172 | } |
| 13173 | case RISCV::C_ADDI4SPN: { |
| 13174 | switch (OpNum) { |
| 13175 | case 2: |
| 13176 | // op: imm |
| 13177 | return 5; |
| 13178 | case 0: |
| 13179 | // op: rd |
| 13180 | return 2; |
| 13181 | } |
| 13182 | break; |
| 13183 | } |
| 13184 | case RISCV::C_FSDSP: |
| 13185 | case RISCV::C_FSWSP: |
| 13186 | case RISCV::C_SDSP: |
| 13187 | case RISCV::C_SDSP_RV32: |
| 13188 | case RISCV::C_SWSP: |
| 13189 | case RISCV::C_SWSP_INX: { |
| 13190 | switch (OpNum) { |
| 13191 | case 2: |
| 13192 | // op: imm |
| 13193 | return 7; |
| 13194 | case 0: |
| 13195 | // op: rs2 |
| 13196 | return 2; |
| 13197 | } |
| 13198 | break; |
| 13199 | } |
| 13200 | case RISCV::NDS_BBC: |
| 13201 | case RISCV::NDS_BBS: |
| 13202 | case RISCV::NDS_BEQC: |
| 13203 | case RISCV::NDS_BNEC: { |
| 13204 | switch (OpNum) { |
| 13205 | case 2: |
| 13206 | // op: imm10 |
| 13207 | return 8; |
| 13208 | case 0: |
| 13209 | // op: rs1 |
| 13210 | return 15; |
| 13211 | case 1: |
| 13212 | // op: cimm |
| 13213 | return 7; |
| 13214 | } |
| 13215 | break; |
| 13216 | } |
| 13217 | case RISCV::CV_BEQIMM: |
| 13218 | case RISCV::CV_BNEIMM: { |
| 13219 | switch (OpNum) { |
| 13220 | case 2: |
| 13221 | // op: imm12 |
| 13222 | return 7; |
| 13223 | case 0: |
| 13224 | // op: rs1 |
| 13225 | return 15; |
| 13226 | case 1: |
| 13227 | // op: imm5 |
| 13228 | return 20; |
| 13229 | } |
| 13230 | break; |
| 13231 | } |
| 13232 | case RISCV::FSD: |
| 13233 | case RISCV::FSH: |
| 13234 | case RISCV::FSQ: |
| 13235 | case RISCV::FSW: |
| 13236 | case RISCV::SB: |
| 13237 | case RISCV::SD: |
| 13238 | case RISCV::SD_RV32: |
| 13239 | case RISCV::SH: |
| 13240 | case RISCV::SH_INX: |
| 13241 | case RISCV::SW: |
| 13242 | case RISCV::SW_INX: { |
| 13243 | switch (OpNum) { |
| 13244 | case 2: |
| 13245 | // op: imm12 |
| 13246 | return 7; |
| 13247 | case 0: |
| 13248 | // op: rs2 |
| 13249 | return 20; |
| 13250 | case 1: |
| 13251 | // op: rs1 |
| 13252 | return 15; |
| 13253 | } |
| 13254 | break; |
| 13255 | } |
| 13256 | case RISCV::BEQI: |
| 13257 | case RISCV::BNEI: { |
| 13258 | switch (OpNum) { |
| 13259 | case 2: |
| 13260 | // op: imm12 |
| 13261 | return 7; |
| 13262 | case 1: |
| 13263 | // op: cimm |
| 13264 | return 20; |
| 13265 | case 0: |
| 13266 | // op: rs1 |
| 13267 | return 15; |
| 13268 | } |
| 13269 | break; |
| 13270 | } |
| 13271 | case RISCV::BEQ: |
| 13272 | case RISCV::BGE: |
| 13273 | case RISCV::BGEU: |
| 13274 | case RISCV::BLT: |
| 13275 | case RISCV::BLTU: |
| 13276 | case RISCV::BNE: |
| 13277 | case RISCV::QC_BEQI: |
| 13278 | case RISCV::QC_BGEI: |
| 13279 | case RISCV::QC_BGEUI: |
| 13280 | case RISCV::QC_BLTI: |
| 13281 | case RISCV::QC_BLTUI: |
| 13282 | case RISCV::QC_BNEI: { |
| 13283 | switch (OpNum) { |
| 13284 | case 2: |
| 13285 | // op: imm12 |
| 13286 | return 7; |
| 13287 | case 1: |
| 13288 | // op: rs2 |
| 13289 | return 20; |
| 13290 | case 0: |
| 13291 | // op: rs1 |
| 13292 | return 15; |
| 13293 | } |
| 13294 | break; |
| 13295 | } |
| 13296 | case RISCV::AIF_FBC_PS: |
| 13297 | case RISCV::AIF_FLQ2: |
| 13298 | case RISCV::AIF_FLW_PS: |
| 13299 | case RISCV::CSRRC: |
| 13300 | case RISCV::CSRRCI: |
| 13301 | case RISCV::CSRRS: |
| 13302 | case RISCV::CSRRSI: |
| 13303 | case RISCV::CSRRW: |
| 13304 | case RISCV::CSRRWI: { |
| 13305 | switch (OpNum) { |
| 13306 | case 2: |
| 13307 | // op: rs1 |
| 13308 | return 15; |
| 13309 | case 0: |
| 13310 | // op: rd |
| 13311 | return 7; |
| 13312 | case 1: |
| 13313 | // op: imm12 |
| 13314 | return 20; |
| 13315 | } |
| 13316 | break; |
| 13317 | } |
| 13318 | case RISCV::CV_LBU_ri_inc: |
| 13319 | case RISCV::CV_LB_ri_inc: |
| 13320 | case RISCV::CV_LHU_ri_inc: |
| 13321 | case RISCV::CV_LH_ri_inc: |
| 13322 | case RISCV::CV_LW_ri_inc: { |
| 13323 | switch (OpNum) { |
| 13324 | case 2: |
| 13325 | // op: rs1 |
| 13326 | return 15; |
| 13327 | case 0: |
| 13328 | // op: rd |
| 13329 | return 7; |
| 13330 | case 3: |
| 13331 | // op: imm12 |
| 13332 | return 20; |
| 13333 | } |
| 13334 | break; |
| 13335 | } |
| 13336 | case RISCV::TH_LBIA: |
| 13337 | case RISCV::TH_LBIB: |
| 13338 | case RISCV::TH_LBUIA: |
| 13339 | case RISCV::TH_LBUIB: |
| 13340 | case RISCV::TH_LDIA: |
| 13341 | case RISCV::TH_LDIB: |
| 13342 | case RISCV::TH_LHIA: |
| 13343 | case RISCV::TH_LHIB: |
| 13344 | case RISCV::TH_LHUIA: |
| 13345 | case RISCV::TH_LHUIB: |
| 13346 | case RISCV::TH_LWIA: |
| 13347 | case RISCV::TH_LWIB: |
| 13348 | case RISCV::TH_LWUIA: |
| 13349 | case RISCV::TH_LWUIB: { |
| 13350 | switch (OpNum) { |
| 13351 | case 2: |
| 13352 | // op: rs1 |
| 13353 | return 15; |
| 13354 | case 0: |
| 13355 | // op: rd |
| 13356 | return 7; |
| 13357 | case 3: |
| 13358 | // op: simm5 |
| 13359 | return 20; |
| 13360 | case 4: |
| 13361 | // op: uimm2 |
| 13362 | return 25; |
| 13363 | } |
| 13364 | break; |
| 13365 | } |
| 13366 | case RISCV::QC_INSBRI: { |
| 13367 | switch (OpNum) { |
| 13368 | case 2: |
| 13369 | // op: rs1 |
| 13370 | return 15; |
| 13371 | case 1: |
| 13372 | // op: rd |
| 13373 | return 7; |
| 13374 | case 3: |
| 13375 | // op: imm11 |
| 13376 | return 20; |
| 13377 | } |
| 13378 | break; |
| 13379 | } |
| 13380 | case RISCV::QC_MULIADD: { |
| 13381 | switch (OpNum) { |
| 13382 | case 2: |
| 13383 | // op: rs1 |
| 13384 | return 15; |
| 13385 | case 1: |
| 13386 | // op: rd |
| 13387 | return 7; |
| 13388 | case 3: |
| 13389 | // op: imm12 |
| 13390 | return 20; |
| 13391 | } |
| 13392 | break; |
| 13393 | } |
| 13394 | case RISCV::CV_INSERT_B: |
| 13395 | case RISCV::CV_INSERT_H: |
| 13396 | case RISCV::CV_SDOTSP_SCI_B: |
| 13397 | case RISCV::CV_SDOTSP_SCI_H: |
| 13398 | case RISCV::CV_SDOTUP_SCI_B: |
| 13399 | case RISCV::CV_SDOTUP_SCI_H: |
| 13400 | case RISCV::CV_SDOTUSP_SCI_B: |
| 13401 | case RISCV::CV_SDOTUSP_SCI_H: { |
| 13402 | switch (OpNum) { |
| 13403 | case 2: |
| 13404 | // op: rs1 |
| 13405 | return 15; |
| 13406 | case 1: |
| 13407 | // op: rd |
| 13408 | return 7; |
| 13409 | case 3: |
| 13410 | // op: imm6 |
| 13411 | return 20; |
| 13412 | } |
| 13413 | break; |
| 13414 | } |
| 13415 | case RISCV::CV_INSERT: { |
| 13416 | switch (OpNum) { |
| 13417 | case 2: |
| 13418 | // op: rs1 |
| 13419 | return 15; |
| 13420 | case 1: |
| 13421 | // op: rd |
| 13422 | return 7; |
| 13423 | case 3: |
| 13424 | // op: is3 |
| 13425 | return 25; |
| 13426 | case 4: |
| 13427 | // op: is2 |
| 13428 | return 20; |
| 13429 | } |
| 13430 | break; |
| 13431 | } |
| 13432 | case RISCV::QC_SELECTIIEQ: |
| 13433 | case RISCV::QC_SELECTIINE: { |
| 13434 | switch (OpNum) { |
| 13435 | case 2: |
| 13436 | // op: rs1 |
| 13437 | return 15; |
| 13438 | case 1: |
| 13439 | // op: rd |
| 13440 | return 7; |
| 13441 | case 3: |
| 13442 | // op: simm1 |
| 13443 | return 20; |
| 13444 | case 4: |
| 13445 | // op: simm2 |
| 13446 | return 27; |
| 13447 | } |
| 13448 | break; |
| 13449 | } |
| 13450 | case RISCV::TH_SBIA: |
| 13451 | case RISCV::TH_SBIB: |
| 13452 | case RISCV::TH_SDIA: |
| 13453 | case RISCV::TH_SDIB: |
| 13454 | case RISCV::TH_SHIA: |
| 13455 | case RISCV::TH_SHIB: |
| 13456 | case RISCV::TH_SWIA: |
| 13457 | case RISCV::TH_SWIB: { |
| 13458 | switch (OpNum) { |
| 13459 | case 2: |
| 13460 | // op: rs1 |
| 13461 | return 15; |
| 13462 | case 1: |
| 13463 | // op: rd |
| 13464 | return 7; |
| 13465 | case 3: |
| 13466 | // op: simm5 |
| 13467 | return 20; |
| 13468 | case 4: |
| 13469 | // op: uimm2 |
| 13470 | return 25; |
| 13471 | } |
| 13472 | break; |
| 13473 | } |
| 13474 | case RISCV::QC_INSB: |
| 13475 | case RISCV::QC_INSBH: { |
| 13476 | switch (OpNum) { |
| 13477 | case 2: |
| 13478 | // op: rs1 |
| 13479 | return 15; |
| 13480 | case 1: |
| 13481 | // op: rd |
| 13482 | return 7; |
| 13483 | case 4: |
| 13484 | // op: shamt |
| 13485 | return 20; |
| 13486 | case 3: |
| 13487 | // op: width |
| 13488 | return 25; |
| 13489 | } |
| 13490 | break; |
| 13491 | } |
| 13492 | case RISCV::AES32DSI: |
| 13493 | case RISCV::AES32DSMI: |
| 13494 | case RISCV::AES32ESI: |
| 13495 | case RISCV::AES32ESMI: |
| 13496 | case RISCV::SM4ED: |
| 13497 | case RISCV::SM4KS: { |
| 13498 | switch (OpNum) { |
| 13499 | case 2: |
| 13500 | // op: rs2 |
| 13501 | return 20; |
| 13502 | case 1: |
| 13503 | // op: rs1 |
| 13504 | return 15; |
| 13505 | case 0: |
| 13506 | // op: rd |
| 13507 | return 7; |
| 13508 | case 3: |
| 13509 | // op: bs |
| 13510 | return 30; |
| 13511 | } |
| 13512 | break; |
| 13513 | } |
| 13514 | case RISCV::QC_LWM: |
| 13515 | case RISCV::QC_LWMI: |
| 13516 | case RISCV::QC_SETWM: |
| 13517 | case RISCV::QC_SETWMI: |
| 13518 | case RISCV::QC_SWM: |
| 13519 | case RISCV::QC_SWMI: { |
| 13520 | switch (OpNum) { |
| 13521 | case 2: |
| 13522 | // op: rs2 |
| 13523 | return 20; |
| 13524 | case 1: |
| 13525 | // op: rs1 |
| 13526 | return 15; |
| 13527 | case 0: |
| 13528 | // op: rd |
| 13529 | return 7; |
| 13530 | case 3: |
| 13531 | // op: imm |
| 13532 | return 25; |
| 13533 | } |
| 13534 | break; |
| 13535 | } |
| 13536 | case RISCV::CV_ADDN: |
| 13537 | case RISCV::CV_ADDRN: |
| 13538 | case RISCV::CV_ADDUN: |
| 13539 | case RISCV::CV_ADDURN: |
| 13540 | case RISCV::CV_MULHHSN: |
| 13541 | case RISCV::CV_MULHHSRN: |
| 13542 | case RISCV::CV_MULHHUN: |
| 13543 | case RISCV::CV_MULHHURN: |
| 13544 | case RISCV::CV_MULSN: |
| 13545 | case RISCV::CV_MULSRN: |
| 13546 | case RISCV::CV_MULUN: |
| 13547 | case RISCV::CV_MULURN: |
| 13548 | case RISCV::CV_SUBN: |
| 13549 | case RISCV::CV_SUBRN: |
| 13550 | case RISCV::CV_SUBUN: |
| 13551 | case RISCV::CV_SUBURN: { |
| 13552 | switch (OpNum) { |
| 13553 | case 2: |
| 13554 | // op: rs2 |
| 13555 | return 20; |
| 13556 | case 1: |
| 13557 | // op: rs1 |
| 13558 | return 15; |
| 13559 | case 0: |
| 13560 | // op: rd |
| 13561 | return 7; |
| 13562 | case 3: |
| 13563 | // op: imm5 |
| 13564 | return 25; |
| 13565 | } |
| 13566 | break; |
| 13567 | } |
| 13568 | case RISCV::QC_LRB: |
| 13569 | case RISCV::QC_LRBU: |
| 13570 | case RISCV::QC_LRH: |
| 13571 | case RISCV::QC_LRHU: |
| 13572 | case RISCV::QC_LRW: |
| 13573 | case RISCV::QC_SHLADD: |
| 13574 | case RISCV::QC_SRB: |
| 13575 | case RISCV::QC_SRH: |
| 13576 | case RISCV::QC_SRW: { |
| 13577 | switch (OpNum) { |
| 13578 | case 2: |
| 13579 | // op: rs2 |
| 13580 | return 20; |
| 13581 | case 1: |
| 13582 | // op: rs1 |
| 13583 | return 15; |
| 13584 | case 0: |
| 13585 | // op: rd |
| 13586 | return 7; |
| 13587 | case 3: |
| 13588 | // op: shamt |
| 13589 | return 25; |
| 13590 | } |
| 13591 | break; |
| 13592 | } |
| 13593 | case RISCV::TH_ADDSL: |
| 13594 | case RISCV::TH_FLRD: |
| 13595 | case RISCV::TH_FLRW: |
| 13596 | case RISCV::TH_FLURD: |
| 13597 | case RISCV::TH_FLURW: |
| 13598 | case RISCV::TH_FSRD: |
| 13599 | case RISCV::TH_FSRW: |
| 13600 | case RISCV::TH_FSURD: |
| 13601 | case RISCV::TH_FSURW: |
| 13602 | case RISCV::TH_LRB: |
| 13603 | case RISCV::TH_LRBU: |
| 13604 | case RISCV::TH_LRD: |
| 13605 | case RISCV::TH_LRH: |
| 13606 | case RISCV::TH_LRHU: |
| 13607 | case RISCV::TH_LRW: |
| 13608 | case RISCV::TH_LRWU: |
| 13609 | case RISCV::TH_LURB: |
| 13610 | case RISCV::TH_LURBU: |
| 13611 | case RISCV::TH_LURD: |
| 13612 | case RISCV::TH_LURH: |
| 13613 | case RISCV::TH_LURHU: |
| 13614 | case RISCV::TH_LURW: |
| 13615 | case RISCV::TH_LURWU: |
| 13616 | case RISCV::TH_SRB: |
| 13617 | case RISCV::TH_SRD: |
| 13618 | case RISCV::TH_SRH: |
| 13619 | case RISCV::TH_SRW: |
| 13620 | case RISCV::TH_SURB: |
| 13621 | case RISCV::TH_SURD: |
| 13622 | case RISCV::TH_SURH: |
| 13623 | case RISCV::TH_SURW: { |
| 13624 | switch (OpNum) { |
| 13625 | case 2: |
| 13626 | // op: rs2 |
| 13627 | return 20; |
| 13628 | case 1: |
| 13629 | // op: rs1 |
| 13630 | return 15; |
| 13631 | case 0: |
| 13632 | // op: rd |
| 13633 | return 7; |
| 13634 | case 3: |
| 13635 | // op: uimm2 |
| 13636 | return 25; |
| 13637 | } |
| 13638 | break; |
| 13639 | } |
| 13640 | case RISCV::AADD: |
| 13641 | case RISCV::AADDU: |
| 13642 | case RISCV::ADD: |
| 13643 | case RISCV::ADDW: |
| 13644 | case RISCV::ADD_UW: |
| 13645 | case RISCV::AES64DS: |
| 13646 | case RISCV::AES64DSM: |
| 13647 | case RISCV::AES64ES: |
| 13648 | case RISCV::AES64ESM: |
| 13649 | case RISCV::AES64KS2: |
| 13650 | case RISCV::AIF_BITMIXB: |
| 13651 | case RISCV::AIF_CUBEFACEIDX_PS: |
| 13652 | case RISCV::AIF_CUBEFACE_PS: |
| 13653 | case RISCV::AIF_CUBESGNSC_PS: |
| 13654 | case RISCV::AIF_CUBESGNTC_PS: |
| 13655 | case RISCV::AIF_FADD_PI: |
| 13656 | case RISCV::AIF_FAMOADDG_PI: |
| 13657 | case RISCV::AIF_FAMOADDL_PI: |
| 13658 | case RISCV::AIF_FAMOANDG_PI: |
| 13659 | case RISCV::AIF_FAMOANDL_PI: |
| 13660 | case RISCV::AIF_FAMOMAXG_PI: |
| 13661 | case RISCV::AIF_FAMOMAXG_PS: |
| 13662 | case RISCV::AIF_FAMOMAXL_PI: |
| 13663 | case RISCV::AIF_FAMOMAXL_PS: |
| 13664 | case RISCV::AIF_FAMOMAXUG_PI: |
| 13665 | case RISCV::AIF_FAMOMAXUL_PI: |
| 13666 | case RISCV::AIF_FAMOMING_PI: |
| 13667 | case RISCV::AIF_FAMOMING_PS: |
| 13668 | case RISCV::AIF_FAMOMINL_PI: |
| 13669 | case RISCV::AIF_FAMOMINL_PS: |
| 13670 | case RISCV::AIF_FAMOMINUG_PI: |
| 13671 | case RISCV::AIF_FAMOMINUL_PI: |
| 13672 | case RISCV::AIF_FAMOORG_PI: |
| 13673 | case RISCV::AIF_FAMOORL_PI: |
| 13674 | case RISCV::AIF_FAMOSWAPG_PI: |
| 13675 | case RISCV::AIF_FAMOSWAPL_PI: |
| 13676 | case RISCV::AIF_FAMOXORG_PI: |
| 13677 | case RISCV::AIF_FAMOXORL_PI: |
| 13678 | case RISCV::AIF_FAND_PI: |
| 13679 | case RISCV::AIF_FCMOVM_PS: |
| 13680 | case RISCV::AIF_FDIVU_PI: |
| 13681 | case RISCV::AIF_FDIV_PI: |
| 13682 | case RISCV::AIF_FEQM_PS: |
| 13683 | case RISCV::AIF_FEQ_PI: |
| 13684 | case RISCV::AIF_FEQ_PS: |
| 13685 | case RISCV::AIF_FG32B_PS: |
| 13686 | case RISCV::AIF_FG32H_PS: |
| 13687 | case RISCV::AIF_FG32W_PS: |
| 13688 | case RISCV::AIF_FGBG_PS: |
| 13689 | case RISCV::AIF_FGBL_PS: |
| 13690 | case RISCV::AIF_FGB_PS: |
| 13691 | case RISCV::AIF_FGHG_PS: |
| 13692 | case RISCV::AIF_FGHL_PS: |
| 13693 | case RISCV::AIF_FGH_PS: |
| 13694 | case RISCV::AIF_FGWG_PS: |
| 13695 | case RISCV::AIF_FGWL_PS: |
| 13696 | case RISCV::AIF_FGW_PS: |
| 13697 | case RISCV::AIF_FLEM_PS: |
| 13698 | case RISCV::AIF_FLE_PI: |
| 13699 | case RISCV::AIF_FLE_PS: |
| 13700 | case RISCV::AIF_FLTM_PI: |
| 13701 | case RISCV::AIF_FLTM_PS: |
| 13702 | case RISCV::AIF_FLTU_PI: |
| 13703 | case RISCV::AIF_FLT_PI: |
| 13704 | case RISCV::AIF_FLT_PS: |
| 13705 | case RISCV::AIF_FMAXU_PI: |
| 13706 | case RISCV::AIF_FMAX_PI: |
| 13707 | case RISCV::AIF_FMAX_PS: |
| 13708 | case RISCV::AIF_FMINU_PI: |
| 13709 | case RISCV::AIF_FMIN_PI: |
| 13710 | case RISCV::AIF_FMIN_PS: |
| 13711 | case RISCV::AIF_FMULHU_PI: |
| 13712 | case RISCV::AIF_FMULH_PI: |
| 13713 | case RISCV::AIF_FMUL_PI: |
| 13714 | case RISCV::AIF_FOR_PI: |
| 13715 | case RISCV::AIF_FRCP_FIX_RAST: |
| 13716 | case RISCV::AIF_FREMU_PI: |
| 13717 | case RISCV::AIF_FREM_PI: |
| 13718 | case RISCV::AIF_FSGNJN_PS: |
| 13719 | case RISCV::AIF_FSGNJX_PS: |
| 13720 | case RISCV::AIF_FSGNJ_PS: |
| 13721 | case RISCV::AIF_FSLL_PI: |
| 13722 | case RISCV::AIF_FSRA_PI: |
| 13723 | case RISCV::AIF_FSRL_PI: |
| 13724 | case RISCV::AIF_FSUB_PI: |
| 13725 | case RISCV::AIF_FXOR_PI: |
| 13726 | case RISCV::AIF_MASKAND: |
| 13727 | case RISCV::AIF_MASKOR: |
| 13728 | case RISCV::AIF_MASKXOR: |
| 13729 | case RISCV::AIF_PACKB: |
| 13730 | case RISCV::AND: |
| 13731 | case RISCV::ANDN: |
| 13732 | case RISCV::ASUB: |
| 13733 | case RISCV::ASUBU: |
| 13734 | case RISCV::BCLR: |
| 13735 | case RISCV::BEXT: |
| 13736 | case RISCV::BINV: |
| 13737 | case RISCV::BSET: |
| 13738 | case RISCV::CLMUL: |
| 13739 | case RISCV::CLMULH: |
| 13740 | case RISCV::CLMULR: |
| 13741 | case RISCV::CV_ADD_B: |
| 13742 | case RISCV::CV_ADD_DIV2: |
| 13743 | case RISCV::CV_ADD_DIV4: |
| 13744 | case RISCV::CV_ADD_DIV8: |
| 13745 | case RISCV::CV_ADD_H: |
| 13746 | case RISCV::CV_ADD_SC_B: |
| 13747 | case RISCV::CV_ADD_SC_H: |
| 13748 | case RISCV::CV_AND_B: |
| 13749 | case RISCV::CV_AND_H: |
| 13750 | case RISCV::CV_AND_SC_B: |
| 13751 | case RISCV::CV_AND_SC_H: |
| 13752 | case RISCV::CV_AVGU_B: |
| 13753 | case RISCV::CV_AVGU_H: |
| 13754 | case RISCV::CV_AVGU_SC_B: |
| 13755 | case RISCV::CV_AVGU_SC_H: |
| 13756 | case RISCV::CV_AVG_B: |
| 13757 | case RISCV::CV_AVG_H: |
| 13758 | case RISCV::CV_AVG_SC_B: |
| 13759 | case RISCV::CV_AVG_SC_H: |
| 13760 | case RISCV::CV_BCLRR: |
| 13761 | case RISCV::CV_BSETR: |
| 13762 | case RISCV::CV_CLIPR: |
| 13763 | case RISCV::CV_CLIPUR: |
| 13764 | case RISCV::CV_CMPEQ_B: |
| 13765 | case RISCV::CV_CMPEQ_H: |
| 13766 | case RISCV::CV_CMPEQ_SC_B: |
| 13767 | case RISCV::CV_CMPEQ_SC_H: |
| 13768 | case RISCV::CV_CMPGEU_B: |
| 13769 | case RISCV::CV_CMPGEU_H: |
| 13770 | case RISCV::CV_CMPGEU_SC_B: |
| 13771 | case RISCV::CV_CMPGEU_SC_H: |
| 13772 | case RISCV::CV_CMPGE_B: |
| 13773 | case RISCV::CV_CMPGE_H: |
| 13774 | case RISCV::CV_CMPGE_SC_B: |
| 13775 | case RISCV::CV_CMPGE_SC_H: |
| 13776 | case RISCV::CV_CMPGTU_B: |
| 13777 | case RISCV::CV_CMPGTU_H: |
| 13778 | case RISCV::CV_CMPGTU_SC_B: |
| 13779 | case RISCV::CV_CMPGTU_SC_H: |
| 13780 | case RISCV::CV_CMPGT_B: |
| 13781 | case RISCV::CV_CMPGT_H: |
| 13782 | case RISCV::CV_CMPGT_SC_B: |
| 13783 | case RISCV::CV_CMPGT_SC_H: |
| 13784 | case RISCV::CV_CMPLEU_B: |
| 13785 | case RISCV::CV_CMPLEU_H: |
| 13786 | case RISCV::CV_CMPLEU_SC_B: |
| 13787 | case RISCV::CV_CMPLEU_SC_H: |
| 13788 | case RISCV::CV_CMPLE_B: |
| 13789 | case RISCV::CV_CMPLE_H: |
| 13790 | case RISCV::CV_CMPLE_SC_B: |
| 13791 | case RISCV::CV_CMPLE_SC_H: |
| 13792 | case RISCV::CV_CMPLTU_B: |
| 13793 | case RISCV::CV_CMPLTU_H: |
| 13794 | case RISCV::CV_CMPLTU_SC_B: |
| 13795 | case RISCV::CV_CMPLTU_SC_H: |
| 13796 | case RISCV::CV_CMPLT_B: |
| 13797 | case RISCV::CV_CMPLT_H: |
| 13798 | case RISCV::CV_CMPLT_SC_B: |
| 13799 | case RISCV::CV_CMPLT_SC_H: |
| 13800 | case RISCV::CV_CMPNE_B: |
| 13801 | case RISCV::CV_CMPNE_H: |
| 13802 | case RISCV::CV_CMPNE_SC_B: |
| 13803 | case RISCV::CV_CMPNE_SC_H: |
| 13804 | case RISCV::CV_DOTSP_B: |
| 13805 | case RISCV::CV_DOTSP_H: |
| 13806 | case RISCV::CV_DOTSP_SC_B: |
| 13807 | case RISCV::CV_DOTSP_SC_H: |
| 13808 | case RISCV::CV_DOTUP_B: |
| 13809 | case RISCV::CV_DOTUP_H: |
| 13810 | case RISCV::CV_DOTUP_SC_B: |
| 13811 | case RISCV::CV_DOTUP_SC_H: |
| 13812 | case RISCV::CV_DOTUSP_B: |
| 13813 | case RISCV::CV_DOTUSP_H: |
| 13814 | case RISCV::CV_DOTUSP_SC_B: |
| 13815 | case RISCV::CV_DOTUSP_SC_H: |
| 13816 | case RISCV::CV_EXTRACTR: |
| 13817 | case RISCV::CV_EXTRACTUR: |
| 13818 | case RISCV::CV_LBU_rr: |
| 13819 | case RISCV::CV_LB_rr: |
| 13820 | case RISCV::CV_LHU_rr: |
| 13821 | case RISCV::CV_LH_rr: |
| 13822 | case RISCV::CV_LW_rr: |
| 13823 | case RISCV::CV_MAX: |
| 13824 | case RISCV::CV_MAXU: |
| 13825 | case RISCV::CV_MAXU_B: |
| 13826 | case RISCV::CV_MAXU_H: |
| 13827 | case RISCV::CV_MAXU_SC_B: |
| 13828 | case RISCV::CV_MAXU_SC_H: |
| 13829 | case RISCV::CV_MAX_B: |
| 13830 | case RISCV::CV_MAX_H: |
| 13831 | case RISCV::CV_MAX_SC_B: |
| 13832 | case RISCV::CV_MAX_SC_H: |
| 13833 | case RISCV::CV_MIN: |
| 13834 | case RISCV::CV_MINU: |
| 13835 | case RISCV::CV_MINU_B: |
| 13836 | case RISCV::CV_MINU_H: |
| 13837 | case RISCV::CV_MINU_SC_B: |
| 13838 | case RISCV::CV_MINU_SC_H: |
| 13839 | case RISCV::CV_MIN_B: |
| 13840 | case RISCV::CV_MIN_H: |
| 13841 | case RISCV::CV_MIN_SC_B: |
| 13842 | case RISCV::CV_MIN_SC_H: |
| 13843 | case RISCV::CV_OR_B: |
| 13844 | case RISCV::CV_OR_H: |
| 13845 | case RISCV::CV_OR_SC_B: |
| 13846 | case RISCV::CV_OR_SC_H: |
| 13847 | case RISCV::CV_PACK: |
| 13848 | case RISCV::CV_PACK_H: |
| 13849 | case RISCV::CV_ROR: |
| 13850 | case RISCV::CV_SHUFFLE_B: |
| 13851 | case RISCV::CV_SHUFFLE_H: |
| 13852 | case RISCV::CV_SLE: |
| 13853 | case RISCV::CV_SLEU: |
| 13854 | case RISCV::CV_SLL_B: |
| 13855 | case RISCV::CV_SLL_H: |
| 13856 | case RISCV::CV_SLL_SC_B: |
| 13857 | case RISCV::CV_SLL_SC_H: |
| 13858 | case RISCV::CV_SRA_B: |
| 13859 | case RISCV::CV_SRA_H: |
| 13860 | case RISCV::CV_SRA_SC_B: |
| 13861 | case RISCV::CV_SRA_SC_H: |
| 13862 | case RISCV::CV_SRL_B: |
| 13863 | case RISCV::CV_SRL_H: |
| 13864 | case RISCV::CV_SRL_SC_B: |
| 13865 | case RISCV::CV_SRL_SC_H: |
| 13866 | case RISCV::CV_SUBROTMJ: |
| 13867 | case RISCV::CV_SUBROTMJ_DIV2: |
| 13868 | case RISCV::CV_SUBROTMJ_DIV4: |
| 13869 | case RISCV::CV_SUBROTMJ_DIV8: |
| 13870 | case RISCV::CV_SUB_B: |
| 13871 | case RISCV::CV_SUB_DIV2: |
| 13872 | case RISCV::CV_SUB_DIV4: |
| 13873 | case RISCV::CV_SUB_DIV8: |
| 13874 | case RISCV::CV_SUB_H: |
| 13875 | case RISCV::CV_SUB_SC_B: |
| 13876 | case RISCV::CV_SUB_SC_H: |
| 13877 | case RISCV::CV_XOR_B: |
| 13878 | case RISCV::CV_XOR_H: |
| 13879 | case RISCV::CV_XOR_SC_B: |
| 13880 | case RISCV::CV_XOR_SC_H: |
| 13881 | case RISCV::CZERO_EQZ: |
| 13882 | case RISCV::CZERO_NEZ: |
| 13883 | case RISCV::DIV: |
| 13884 | case RISCV::DIVU: |
| 13885 | case RISCV::DIVUW: |
| 13886 | case RISCV::DIVW: |
| 13887 | case RISCV::FEQ_D: |
| 13888 | case RISCV::FEQ_D_IN32X: |
| 13889 | case RISCV::FEQ_D_INX: |
| 13890 | case RISCV::FEQ_H: |
| 13891 | case RISCV::FEQ_H_INX: |
| 13892 | case RISCV::FEQ_Q: |
| 13893 | case RISCV::FEQ_S: |
| 13894 | case RISCV::FEQ_S_INX: |
| 13895 | case RISCV::FLEQ_D: |
| 13896 | case RISCV::FLEQ_H: |
| 13897 | case RISCV::FLEQ_Q: |
| 13898 | case RISCV::FLEQ_S: |
| 13899 | case RISCV::FLE_D: |
| 13900 | case RISCV::FLE_D_IN32X: |
| 13901 | case RISCV::FLE_D_INX: |
| 13902 | case RISCV::FLE_H: |
| 13903 | case RISCV::FLE_H_INX: |
| 13904 | case RISCV::FLE_Q: |
| 13905 | case RISCV::FLE_S: |
| 13906 | case RISCV::FLE_S_INX: |
| 13907 | case RISCV::FLTQ_D: |
| 13908 | case RISCV::FLTQ_H: |
| 13909 | case RISCV::FLTQ_Q: |
| 13910 | case RISCV::FLTQ_S: |
| 13911 | case RISCV::FLT_D: |
| 13912 | case RISCV::FLT_D_IN32X: |
| 13913 | case RISCV::FLT_D_INX: |
| 13914 | case RISCV::FLT_H: |
| 13915 | case RISCV::FLT_H_INX: |
| 13916 | case RISCV::FLT_Q: |
| 13917 | case RISCV::FLT_S: |
| 13918 | case RISCV::FLT_S_INX: |
| 13919 | case RISCV::FMAXM_D: |
| 13920 | case RISCV::FMAXM_H: |
| 13921 | case RISCV::FMAXM_Q: |
| 13922 | case RISCV::FMAXM_S: |
| 13923 | case RISCV::FMAX_D: |
| 13924 | case RISCV::FMAX_D_IN32X: |
| 13925 | case RISCV::FMAX_D_INX: |
| 13926 | case RISCV::FMAX_H: |
| 13927 | case RISCV::FMAX_H_INX: |
| 13928 | case RISCV::FMAX_Q: |
| 13929 | case RISCV::FMAX_S: |
| 13930 | case RISCV::FMAX_S_INX: |
| 13931 | case RISCV::FMINM_D: |
| 13932 | case RISCV::FMINM_H: |
| 13933 | case RISCV::FMINM_Q: |
| 13934 | case RISCV::FMINM_S: |
| 13935 | case RISCV::FMIN_D: |
| 13936 | case RISCV::FMIN_D_IN32X: |
| 13937 | case RISCV::FMIN_D_INX: |
| 13938 | case RISCV::FMIN_H: |
| 13939 | case RISCV::FMIN_H_INX: |
| 13940 | case RISCV::FMIN_Q: |
| 13941 | case RISCV::FMIN_S: |
| 13942 | case RISCV::FMIN_S_INX: |
| 13943 | case RISCV::FMVP_D_X: |
| 13944 | case RISCV::FMVP_Q_X: |
| 13945 | case RISCV::FSGNJN_D: |
| 13946 | case RISCV::FSGNJN_D_IN32X: |
| 13947 | case RISCV::FSGNJN_D_INX: |
| 13948 | case RISCV::FSGNJN_H: |
| 13949 | case RISCV::FSGNJN_H_INX: |
| 13950 | case RISCV::FSGNJN_Q: |
| 13951 | case RISCV::FSGNJN_S: |
| 13952 | case RISCV::FSGNJN_S_INX: |
| 13953 | case RISCV::FSGNJX_D: |
| 13954 | case RISCV::FSGNJX_D_IN32X: |
| 13955 | case RISCV::FSGNJX_D_INX: |
| 13956 | case RISCV::FSGNJX_H: |
| 13957 | case RISCV::FSGNJX_H_INX: |
| 13958 | case RISCV::FSGNJX_Q: |
| 13959 | case RISCV::FSGNJX_S: |
| 13960 | case RISCV::FSGNJX_S_INX: |
| 13961 | case RISCV::FSGNJ_D: |
| 13962 | case RISCV::FSGNJ_D_IN32X: |
| 13963 | case RISCV::FSGNJ_D_INX: |
| 13964 | case RISCV::FSGNJ_H: |
| 13965 | case RISCV::FSGNJ_H_INX: |
| 13966 | case RISCV::FSGNJ_Q: |
| 13967 | case RISCV::FSGNJ_S: |
| 13968 | case RISCV::FSGNJ_S_INX: |
| 13969 | case RISCV::MAX: |
| 13970 | case RISCV::MAXU: |
| 13971 | case RISCV::MIN: |
| 13972 | case RISCV::MINU: |
| 13973 | case RISCV::MOP_RR_0: |
| 13974 | case RISCV::MOP_RR_1: |
| 13975 | case RISCV::MOP_RR_2: |
| 13976 | case RISCV::MOP_RR_3: |
| 13977 | case RISCV::MOP_RR_4: |
| 13978 | case RISCV::MOP_RR_5: |
| 13979 | case RISCV::MOP_RR_6: |
| 13980 | case RISCV::MOP_RR_7: |
| 13981 | case RISCV::MSEQ: |
| 13982 | case RISCV::MSLT: |
| 13983 | case RISCV::MSLTU: |
| 13984 | case RISCV::MUL: |
| 13985 | case RISCV::MULH: |
| 13986 | case RISCV::MULHR: |
| 13987 | case RISCV::MULHRSU: |
| 13988 | case RISCV::MULHRU: |
| 13989 | case RISCV::MULHSU: |
| 13990 | case RISCV::MULHSU_H0: |
| 13991 | case RISCV::MULHSU_H1: |
| 13992 | case RISCV::MULHU: |
| 13993 | case RISCV::MULH_H0: |
| 13994 | case RISCV::MULH_H1: |
| 13995 | case RISCV::MULQ: |
| 13996 | case RISCV::MULQR: |
| 13997 | case RISCV::MULSU_H00: |
| 13998 | case RISCV::MULSU_H11: |
| 13999 | case RISCV::MULSU_W00: |
| 14000 | case RISCV::MULSU_W11: |
| 14001 | case RISCV::MULU_H00: |
| 14002 | case RISCV::MULU_H01: |
| 14003 | case RISCV::MULU_H11: |
| 14004 | case RISCV::MULU_W00: |
| 14005 | case RISCV::MULU_W01: |
| 14006 | case RISCV::MULU_W11: |
| 14007 | case RISCV::MULW: |
| 14008 | case RISCV::MUL_H00: |
| 14009 | case RISCV::MUL_H01: |
| 14010 | case RISCV::MUL_H11: |
| 14011 | case RISCV::MUL_W00: |
| 14012 | case RISCV::MUL_W01: |
| 14013 | case RISCV::MUL_W11: |
| 14014 | case RISCV::NDS_FFB: |
| 14015 | case RISCV::NDS_FFMISM: |
| 14016 | case RISCV::NDS_FFZMISM: |
| 14017 | case RISCV::NDS_FLMISM: |
| 14018 | case RISCV::OR: |
| 14019 | case RISCV::ORN: |
| 14020 | case RISCV::PAADDU_B: |
| 14021 | case RISCV::PAADDU_H: |
| 14022 | case RISCV::PAADDU_W: |
| 14023 | case RISCV::PAADD_B: |
| 14024 | case RISCV::PAADD_H: |
| 14025 | case RISCV::PAADD_W: |
| 14026 | case RISCV::PAAS_HX: |
| 14027 | case RISCV::PAAS_WX: |
| 14028 | case RISCV::PABDSUMU_B: |
| 14029 | case RISCV::PABDU_B: |
| 14030 | case RISCV::PABDU_H: |
| 14031 | case RISCV::PABD_B: |
| 14032 | case RISCV::PABD_H: |
| 14033 | case RISCV::PACK: |
| 14034 | case RISCV::PACKH: |
| 14035 | case RISCV::PACKW: |
| 14036 | case RISCV::PADD_B: |
| 14037 | case RISCV::PADD_BS: |
| 14038 | case RISCV::PADD_H: |
| 14039 | case RISCV::PADD_HS: |
| 14040 | case RISCV::PADD_W: |
| 14041 | case RISCV::PADD_WS: |
| 14042 | case RISCV::PASA_HX: |
| 14043 | case RISCV::PASA_WX: |
| 14044 | case RISCV::PASUBU_B: |
| 14045 | case RISCV::PASUBU_H: |
| 14046 | case RISCV::PASUBU_W: |
| 14047 | case RISCV::PASUB_B: |
| 14048 | case RISCV::PASUB_H: |
| 14049 | case RISCV::PASUB_W: |
| 14050 | case RISCV::PAS_HX: |
| 14051 | case RISCV::PAS_WX: |
| 14052 | case RISCV::PM2ADDSU_H: |
| 14053 | case RISCV::PM2ADDSU_W: |
| 14054 | case RISCV::PM2ADDU_H: |
| 14055 | case RISCV::PM2ADDU_W: |
| 14056 | case RISCV::PM2ADD_H: |
| 14057 | case RISCV::PM2ADD_HX: |
| 14058 | case RISCV::PM2ADD_W: |
| 14059 | case RISCV::PM2ADD_WX: |
| 14060 | case RISCV::PM2SADD_H: |
| 14061 | case RISCV::PM2SADD_HX: |
| 14062 | case RISCV::PM2SUB_H: |
| 14063 | case RISCV::PM2SUB_HX: |
| 14064 | case RISCV::PM2SUB_W: |
| 14065 | case RISCV::PM2SUB_WX: |
| 14066 | case RISCV::PM4ADDSU_B: |
| 14067 | case RISCV::PM4ADDSU_H: |
| 14068 | case RISCV::PM4ADDU_B: |
| 14069 | case RISCV::PM4ADDU_H: |
| 14070 | case RISCV::PM4ADD_B: |
| 14071 | case RISCV::PM4ADD_H: |
| 14072 | case RISCV::PMAXU_B: |
| 14073 | case RISCV::PMAXU_H: |
| 14074 | case RISCV::PMAXU_W: |
| 14075 | case RISCV::PMAX_B: |
| 14076 | case RISCV::PMAX_H: |
| 14077 | case RISCV::PMAX_W: |
| 14078 | case RISCV::PMINU_B: |
| 14079 | case RISCV::PMINU_H: |
| 14080 | case RISCV::PMINU_W: |
| 14081 | case RISCV::PMIN_B: |
| 14082 | case RISCV::PMIN_H: |
| 14083 | case RISCV::PMIN_W: |
| 14084 | case RISCV::PMQ2ADD_H: |
| 14085 | case RISCV::PMQ2ADD_W: |
| 14086 | case RISCV::PMQR2ADD_H: |
| 14087 | case RISCV::PMQR2ADD_W: |
| 14088 | case RISCV::PMSEQ_B: |
| 14089 | case RISCV::PMSEQ_H: |
| 14090 | case RISCV::PMSEQ_W: |
| 14091 | case RISCV::PMSLTU_B: |
| 14092 | case RISCV::PMSLTU_H: |
| 14093 | case RISCV::PMSLTU_W: |
| 14094 | case RISCV::PMSLT_B: |
| 14095 | case RISCV::PMSLT_H: |
| 14096 | case RISCV::PMSLT_W: |
| 14097 | case RISCV::PMULHRSU_H: |
| 14098 | case RISCV::PMULHRSU_W: |
| 14099 | case RISCV::PMULHRU_H: |
| 14100 | case RISCV::PMULHRU_W: |
| 14101 | case RISCV::PMULHR_H: |
| 14102 | case RISCV::PMULHR_W: |
| 14103 | case RISCV::PMULHSU_H: |
| 14104 | case RISCV::PMULHSU_H_B0: |
| 14105 | case RISCV::PMULHSU_H_B1: |
| 14106 | case RISCV::PMULHSU_W: |
| 14107 | case RISCV::PMULHSU_W_H0: |
| 14108 | case RISCV::PMULHSU_W_H1: |
| 14109 | case RISCV::PMULHU_H: |
| 14110 | case RISCV::PMULHU_W: |
| 14111 | case RISCV::PMULH_H: |
| 14112 | case RISCV::PMULH_H_B0: |
| 14113 | case RISCV::PMULH_H_B1: |
| 14114 | case RISCV::PMULH_W: |
| 14115 | case RISCV::PMULH_W_H0: |
| 14116 | case RISCV::PMULH_W_H1: |
| 14117 | case RISCV::PMULQR_H: |
| 14118 | case RISCV::PMULQR_W: |
| 14119 | case RISCV::PMULQ_H: |
| 14120 | case RISCV::PMULQ_W: |
| 14121 | case RISCV::PMULSU_H_B00: |
| 14122 | case RISCV::PMULSU_H_B11: |
| 14123 | case RISCV::PMULSU_W_H00: |
| 14124 | case RISCV::PMULSU_W_H11: |
| 14125 | case RISCV::PMULU_H_B00: |
| 14126 | case RISCV::PMULU_H_B01: |
| 14127 | case RISCV::PMULU_H_B11: |
| 14128 | case RISCV::PMULU_W_H00: |
| 14129 | case RISCV::PMULU_W_H01: |
| 14130 | case RISCV::PMULU_W_H11: |
| 14131 | case RISCV::PMUL_H_B00: |
| 14132 | case RISCV::PMUL_H_B01: |
| 14133 | case RISCV::PMUL_H_B11: |
| 14134 | case RISCV::PMUL_W_H00: |
| 14135 | case RISCV::PMUL_W_H01: |
| 14136 | case RISCV::PMUL_W_H11: |
| 14137 | case RISCV::PPAIREO_B: |
| 14138 | case RISCV::PPAIREO_H: |
| 14139 | case RISCV::PPAIREO_W: |
| 14140 | case RISCV::PPAIRE_B: |
| 14141 | case RISCV::PPAIRE_H: |
| 14142 | case RISCV::PPAIROE_B: |
| 14143 | case RISCV::PPAIROE_H: |
| 14144 | case RISCV::PPAIROE_W: |
| 14145 | case RISCV::PPAIRO_B: |
| 14146 | case RISCV::PPAIRO_H: |
| 14147 | case RISCV::PPAIRO_W: |
| 14148 | case RISCV::PREDSUMU_BS: |
| 14149 | case RISCV::PREDSUMU_HS: |
| 14150 | case RISCV::PREDSUMU_WS: |
| 14151 | case RISCV::PREDSUM_BS: |
| 14152 | case RISCV::PREDSUM_HS: |
| 14153 | case RISCV::PREDSUM_WS: |
| 14154 | case RISCV::PSADDU_B: |
| 14155 | case RISCV::PSADDU_H: |
| 14156 | case RISCV::PSADDU_W: |
| 14157 | case RISCV::PSADD_B: |
| 14158 | case RISCV::PSADD_H: |
| 14159 | case RISCV::PSADD_W: |
| 14160 | case RISCV::PSAS_HX: |
| 14161 | case RISCV::PSAS_WX: |
| 14162 | case RISCV::PSA_HX: |
| 14163 | case RISCV::PSA_WX: |
| 14164 | case RISCV::PSH1ADD_H: |
| 14165 | case RISCV::PSH1ADD_W: |
| 14166 | case RISCV::PSLL_BS: |
| 14167 | case RISCV::PSLL_HS: |
| 14168 | case RISCV::PSLL_WS: |
| 14169 | case RISCV::PSRA_BS: |
| 14170 | case RISCV::PSRA_HS: |
| 14171 | case RISCV::PSRA_WS: |
| 14172 | case RISCV::PSRL_BS: |
| 14173 | case RISCV::PSRL_HS: |
| 14174 | case RISCV::PSRL_WS: |
| 14175 | case RISCV::PSSA_HX: |
| 14176 | case RISCV::PSSA_WX: |
| 14177 | case RISCV::PSSH1SADD_H: |
| 14178 | case RISCV::PSSH1SADD_W: |
| 14179 | case RISCV::PSSHAR_HS: |
| 14180 | case RISCV::PSSHAR_WS: |
| 14181 | case RISCV::PSSHA_HS: |
| 14182 | case RISCV::PSSHA_WS: |
| 14183 | case RISCV::PSSUBU_B: |
| 14184 | case RISCV::PSSUBU_H: |
| 14185 | case RISCV::PSSUBU_W: |
| 14186 | case RISCV::PSSUB_B: |
| 14187 | case RISCV::PSSUB_H: |
| 14188 | case RISCV::PSSUB_W: |
| 14189 | case RISCV::PSUB_B: |
| 14190 | case RISCV::PSUB_H: |
| 14191 | case RISCV::PSUB_W: |
| 14192 | case RISCV::QC_ADDSAT: |
| 14193 | case RISCV::QC_ADDUSAT: |
| 14194 | case RISCV::QC_CSRRWR: |
| 14195 | case RISCV::QC_CSRRWRI: |
| 14196 | case RISCV::QC_EXTDPR: |
| 14197 | case RISCV::QC_EXTDPRH: |
| 14198 | case RISCV::QC_EXTDR: |
| 14199 | case RISCV::QC_EXTDUPR: |
| 14200 | case RISCV::QC_EXTDUPRH: |
| 14201 | case RISCV::QC_EXTDUR: |
| 14202 | case RISCV::QC_SHLSAT: |
| 14203 | case RISCV::QC_SHLUSAT: |
| 14204 | case RISCV::QC_SUBSAT: |
| 14205 | case RISCV::QC_SUBUSAT: |
| 14206 | case RISCV::QC_WRAP: |
| 14207 | case RISCV::REM: |
| 14208 | case RISCV::REMU: |
| 14209 | case RISCV::REMUW: |
| 14210 | case RISCV::REMW: |
| 14211 | case RISCV::ROL: |
| 14212 | case RISCV::ROLW: |
| 14213 | case RISCV::ROR: |
| 14214 | case RISCV::RORW: |
| 14215 | case RISCV::SADD: |
| 14216 | case RISCV::SADDU: |
| 14217 | case RISCV::SH1ADD: |
| 14218 | case RISCV::SH1ADD_UW: |
| 14219 | case RISCV::SH2ADD: |
| 14220 | case RISCV::SH2ADD_UW: |
| 14221 | case RISCV::SH3ADD: |
| 14222 | case RISCV::SH3ADD_UW: |
| 14223 | case RISCV::SHA: |
| 14224 | case RISCV::SHA512SIG0H: |
| 14225 | case RISCV::SHA512SIG0L: |
| 14226 | case RISCV::SHA512SIG1H: |
| 14227 | case RISCV::SHA512SIG1L: |
| 14228 | case RISCV::SHA512SUM0R: |
| 14229 | case RISCV::SHA512SUM1R: |
| 14230 | case RISCV::SHAR: |
| 14231 | case RISCV::SLL: |
| 14232 | case RISCV::SLLW: |
| 14233 | case RISCV::SLT: |
| 14234 | case RISCV::SLTU: |
| 14235 | case RISCV::SRA: |
| 14236 | case RISCV::SRAW: |
| 14237 | case RISCV::SRL: |
| 14238 | case RISCV::SRLW: |
| 14239 | case RISCV::SSH1SADD: |
| 14240 | case RISCV::SSHA: |
| 14241 | case RISCV::SSHAR: |
| 14242 | case RISCV::SSUB: |
| 14243 | case RISCV::SSUBU: |
| 14244 | case RISCV::SUB: |
| 14245 | case RISCV::SUBW: |
| 14246 | case RISCV::UNZIP16HP: |
| 14247 | case RISCV::UNZIP16P: |
| 14248 | case RISCV::UNZIP8HP: |
| 14249 | case RISCV::UNZIP8P: |
| 14250 | case RISCV::VSETVL: |
| 14251 | case RISCV::VT_MASKC: |
| 14252 | case RISCV::VT_MASKCN: |
| 14253 | case RISCV::XNOR: |
| 14254 | case RISCV::XOR: |
| 14255 | case RISCV::XPERM4: |
| 14256 | case RISCV::XPERM8: |
| 14257 | case RISCV::ZIP16HP: |
| 14258 | case RISCV::ZIP16P: |
| 14259 | case RISCV::ZIP8HP: |
| 14260 | case RISCV::ZIP8P: { |
| 14261 | switch (OpNum) { |
| 14262 | case 2: |
| 14263 | // op: rs2 |
| 14264 | return 20; |
| 14265 | case 1: |
| 14266 | // op: rs1 |
| 14267 | return 15; |
| 14268 | case 0: |
| 14269 | // op: rd |
| 14270 | return 7; |
| 14271 | } |
| 14272 | break; |
| 14273 | } |
| 14274 | case RISCV::PM2WADDSU_H: |
| 14275 | case RISCV::PM2WADDU_H: |
| 14276 | case RISCV::PM2WADD_H: |
| 14277 | case RISCV::PM2WADD_HX: |
| 14278 | case RISCV::PM2WSUB_H: |
| 14279 | case RISCV::PM2WSUB_HX: |
| 14280 | case RISCV::PWADDU_B: |
| 14281 | case RISCV::PWADDU_H: |
| 14282 | case RISCV::PWADD_B: |
| 14283 | case RISCV::PWADD_H: |
| 14284 | case RISCV::PWMULSU_B: |
| 14285 | case RISCV::PWMULSU_H: |
| 14286 | case RISCV::PWMULU_B: |
| 14287 | case RISCV::PWMULU_H: |
| 14288 | case RISCV::PWMUL_B: |
| 14289 | case RISCV::PWMUL_H: |
| 14290 | case RISCV::PWSLA_BS: |
| 14291 | case RISCV::PWSLA_HS: |
| 14292 | case RISCV::PWSLL_BS: |
| 14293 | case RISCV::PWSLL_HS: |
| 14294 | case RISCV::PWSUBU_B: |
| 14295 | case RISCV::PWSUBU_H: |
| 14296 | case RISCV::PWSUB_B: |
| 14297 | case RISCV::PWSUB_H: |
| 14298 | case RISCV::WADD: |
| 14299 | case RISCV::WADDU: |
| 14300 | case RISCV::WMUL: |
| 14301 | case RISCV::WMULSU: |
| 14302 | case RISCV::WMULU: |
| 14303 | case RISCV::WSLA: |
| 14304 | case RISCV::WSLL: |
| 14305 | case RISCV::WSUB: |
| 14306 | case RISCV::WSUBU: |
| 14307 | case RISCV::WZIP16P: |
| 14308 | case RISCV::WZIP8P: { |
| 14309 | switch (OpNum) { |
| 14310 | case 2: |
| 14311 | // op: rs2 |
| 14312 | return 20; |
| 14313 | case 1: |
| 14314 | // op: rs1 |
| 14315 | return 15; |
| 14316 | case 0: |
| 14317 | // op: rd |
| 14318 | return 8; |
| 14319 | } |
| 14320 | break; |
| 14321 | } |
| 14322 | case RISCV::FADD_D: |
| 14323 | case RISCV::FADD_D_IN32X: |
| 14324 | case RISCV::FADD_D_INX: |
| 14325 | case RISCV::FADD_H: |
| 14326 | case RISCV::FADD_H_INX: |
| 14327 | case RISCV::FADD_Q: |
| 14328 | case RISCV::FADD_S: |
| 14329 | case RISCV::FADD_S_INX: |
| 14330 | case RISCV::FDIV_D: |
| 14331 | case RISCV::FDIV_D_IN32X: |
| 14332 | case RISCV::FDIV_D_INX: |
| 14333 | case RISCV::FDIV_H: |
| 14334 | case RISCV::FDIV_H_INX: |
| 14335 | case RISCV::FDIV_Q: |
| 14336 | case RISCV::FDIV_S: |
| 14337 | case RISCV::FDIV_S_INX: |
| 14338 | case RISCV::FMUL_D: |
| 14339 | case RISCV::FMUL_D_IN32X: |
| 14340 | case RISCV::FMUL_D_INX: |
| 14341 | case RISCV::FMUL_H: |
| 14342 | case RISCV::FMUL_H_INX: |
| 14343 | case RISCV::FMUL_Q: |
| 14344 | case RISCV::FMUL_S: |
| 14345 | case RISCV::FMUL_S_INX: |
| 14346 | case RISCV::FSUB_D: |
| 14347 | case RISCV::FSUB_D_IN32X: |
| 14348 | case RISCV::FSUB_D_INX: |
| 14349 | case RISCV::FSUB_H: |
| 14350 | case RISCV::FSUB_H_INX: |
| 14351 | case RISCV::FSUB_Q: |
| 14352 | case RISCV::FSUB_S: |
| 14353 | case RISCV::FSUB_S_INX: { |
| 14354 | switch (OpNum) { |
| 14355 | case 2: |
| 14356 | // op: rs2 |
| 14357 | return 20; |
| 14358 | case 1: |
| 14359 | // op: rs1 |
| 14360 | return 15; |
| 14361 | case 3: |
| 14362 | // op: frm |
| 14363 | return 12; |
| 14364 | case 0: |
| 14365 | // op: rd |
| 14366 | return 7; |
| 14367 | } |
| 14368 | break; |
| 14369 | } |
| 14370 | case RISCV::AMOCAS_B: |
| 14371 | case RISCV::AMOCAS_B_AQ: |
| 14372 | case RISCV::AMOCAS_B_AQRL: |
| 14373 | case RISCV::AMOCAS_B_RL: |
| 14374 | case RISCV::AMOCAS_D_RV32: |
| 14375 | case RISCV::AMOCAS_D_RV32_AQ: |
| 14376 | case RISCV::AMOCAS_D_RV32_AQRL: |
| 14377 | case RISCV::AMOCAS_D_RV32_RL: |
| 14378 | case RISCV::AMOCAS_D_RV64: |
| 14379 | case RISCV::AMOCAS_D_RV64_AQ: |
| 14380 | case RISCV::AMOCAS_D_RV64_AQRL: |
| 14381 | case RISCV::AMOCAS_D_RV64_RL: |
| 14382 | case RISCV::AMOCAS_H: |
| 14383 | case RISCV::AMOCAS_H_AQ: |
| 14384 | case RISCV::AMOCAS_H_AQRL: |
| 14385 | case RISCV::AMOCAS_H_RL: |
| 14386 | case RISCV::AMOCAS_Q: |
| 14387 | case RISCV::AMOCAS_Q_AQ: |
| 14388 | case RISCV::AMOCAS_Q_AQRL: |
| 14389 | case RISCV::AMOCAS_Q_RL: |
| 14390 | case RISCV::AMOCAS_W: |
| 14391 | case RISCV::AMOCAS_W_AQ: |
| 14392 | case RISCV::AMOCAS_W_AQRL: |
| 14393 | case RISCV::AMOCAS_W_RL: { |
| 14394 | switch (OpNum) { |
| 14395 | case 2: |
| 14396 | // op: rs2 |
| 14397 | return 20; |
| 14398 | case 3: |
| 14399 | // op: rs1 |
| 14400 | return 15; |
| 14401 | case 1: |
| 14402 | // op: rd |
| 14403 | return 7; |
| 14404 | } |
| 14405 | break; |
| 14406 | } |
| 14407 | case RISCV::C_ADDW: |
| 14408 | case RISCV::C_AND: |
| 14409 | case RISCV::C_MUL: |
| 14410 | case RISCV::C_OR: |
| 14411 | case RISCV::C_SUB: |
| 14412 | case RISCV::C_SUBW: |
| 14413 | case RISCV::C_XOR: { |
| 14414 | switch (OpNum) { |
| 14415 | case 2: |
| 14416 | // op: rs2 |
| 14417 | return 2; |
| 14418 | case 1: |
| 14419 | // op: rd |
| 14420 | return 7; |
| 14421 | } |
| 14422 | break; |
| 14423 | } |
| 14424 | case RISCV::SF_VC_V_I: |
| 14425 | case RISCV::SF_VC_V_IV: { |
| 14426 | switch (OpNum) { |
| 14427 | case 2: |
| 14428 | // op: vs2 |
| 14429 | return 20; |
| 14430 | case 0: |
| 14431 | // op: vd |
| 14432 | return 7; |
| 14433 | case 3: |
| 14434 | // op: imm |
| 14435 | return 15; |
| 14436 | case 1: |
| 14437 | // op: funct6_lo2 |
| 14438 | return 26; |
| 14439 | } |
| 14440 | break; |
| 14441 | } |
| 14442 | case RISCV::SF_VC_V_FV: { |
| 14443 | switch (OpNum) { |
| 14444 | case 2: |
| 14445 | // op: vs2 |
| 14446 | return 20; |
| 14447 | case 0: |
| 14448 | // op: vd |
| 14449 | return 7; |
| 14450 | case 3: |
| 14451 | // op: rs1 |
| 14452 | return 15; |
| 14453 | case 1: |
| 14454 | // op: funct6_lo1 |
| 14455 | return 26; |
| 14456 | } |
| 14457 | break; |
| 14458 | } |
| 14459 | case RISCV::SF_VC_V_X: |
| 14460 | case RISCV::SF_VC_V_XV: { |
| 14461 | switch (OpNum) { |
| 14462 | case 2: |
| 14463 | // op: vs2 |
| 14464 | return 20; |
| 14465 | case 0: |
| 14466 | // op: vd |
| 14467 | return 7; |
| 14468 | case 3: |
| 14469 | // op: rs1 |
| 14470 | return 15; |
| 14471 | case 1: |
| 14472 | // op: funct6_lo2 |
| 14473 | return 26; |
| 14474 | } |
| 14475 | break; |
| 14476 | } |
| 14477 | case RISCV::SF_VC_V_VV: { |
| 14478 | switch (OpNum) { |
| 14479 | case 2: |
| 14480 | // op: vs2 |
| 14481 | return 20; |
| 14482 | case 0: |
| 14483 | // op: vd |
| 14484 | return 7; |
| 14485 | case 3: |
| 14486 | // op: vs1 |
| 14487 | return 15; |
| 14488 | case 1: |
| 14489 | // op: funct6_lo2 |
| 14490 | return 26; |
| 14491 | } |
| 14492 | break; |
| 14493 | } |
| 14494 | case RISCV::SF_VC_IV: |
| 14495 | case RISCV::SF_VC_IVV: |
| 14496 | case RISCV::SF_VC_IVW: { |
| 14497 | switch (OpNum) { |
| 14498 | case 2: |
| 14499 | // op: vs2 |
| 14500 | return 20; |
| 14501 | case 1: |
| 14502 | // op: vd |
| 14503 | return 7; |
| 14504 | case 3: |
| 14505 | // op: imm |
| 14506 | return 15; |
| 14507 | case 0: |
| 14508 | // op: funct6_lo2 |
| 14509 | return 26; |
| 14510 | } |
| 14511 | break; |
| 14512 | } |
| 14513 | case RISCV::SF_VC_FV: |
| 14514 | case RISCV::SF_VC_FVV: |
| 14515 | case RISCV::SF_VC_FVW: { |
| 14516 | switch (OpNum) { |
| 14517 | case 2: |
| 14518 | // op: vs2 |
| 14519 | return 20; |
| 14520 | case 1: |
| 14521 | // op: vd |
| 14522 | return 7; |
| 14523 | case 3: |
| 14524 | // op: rs1 |
| 14525 | return 15; |
| 14526 | case 0: |
| 14527 | // op: funct6_lo1 |
| 14528 | return 26; |
| 14529 | } |
| 14530 | break; |
| 14531 | } |
| 14532 | case RISCV::SF_VC_XV: |
| 14533 | case RISCV::SF_VC_XVV: |
| 14534 | case RISCV::SF_VC_XVW: { |
| 14535 | switch (OpNum) { |
| 14536 | case 2: |
| 14537 | // op: vs2 |
| 14538 | return 20; |
| 14539 | case 1: |
| 14540 | // op: vd |
| 14541 | return 7; |
| 14542 | case 3: |
| 14543 | // op: rs1 |
| 14544 | return 15; |
| 14545 | case 0: |
| 14546 | // op: funct6_lo2 |
| 14547 | return 26; |
| 14548 | } |
| 14549 | break; |
| 14550 | } |
| 14551 | case RISCV::SF_VC_VV: |
| 14552 | case RISCV::SF_VC_VVV: |
| 14553 | case RISCV::SF_VC_VVW: { |
| 14554 | switch (OpNum) { |
| 14555 | case 2: |
| 14556 | // op: vs2 |
| 14557 | return 20; |
| 14558 | case 1: |
| 14559 | // op: vd |
| 14560 | return 7; |
| 14561 | case 3: |
| 14562 | // op: vs1 |
| 14563 | return 15; |
| 14564 | case 0: |
| 14565 | // op: funct6_lo2 |
| 14566 | return 26; |
| 14567 | } |
| 14568 | break; |
| 14569 | } |
| 14570 | case RISCV::NDS_VD4DOTSU_VV: |
| 14571 | case RISCV::NDS_VD4DOTS_VV: |
| 14572 | case RISCV::NDS_VD4DOTU_VV: { |
| 14573 | switch (OpNum) { |
| 14574 | case 2: |
| 14575 | // op: vs2 |
| 14576 | return 20; |
| 14577 | case 1: |
| 14578 | // op: vs1 |
| 14579 | return 15; |
| 14580 | case 0: |
| 14581 | // op: vd |
| 14582 | return 7; |
| 14583 | case 3: |
| 14584 | // op: vm |
| 14585 | return 25; |
| 14586 | } |
| 14587 | break; |
| 14588 | } |
| 14589 | case RISCV::AIF_MASKPOPC_ET_RAST: { |
| 14590 | switch (OpNum) { |
| 14591 | case 3: |
| 14592 | // op: imm |
| 14593 | return 18; |
| 14594 | case 2: |
| 14595 | // op: rs2 |
| 14596 | return 20; |
| 14597 | case 1: |
| 14598 | // op: rs1 |
| 14599 | return 15; |
| 14600 | case 0: |
| 14601 | // op: rd |
| 14602 | return 7; |
| 14603 | } |
| 14604 | break; |
| 14605 | } |
| 14606 | case RISCV::RI_VINSERT: { |
| 14607 | switch (OpNum) { |
| 14608 | case 3: |
| 14609 | // op: imm |
| 14610 | return 20; |
| 14611 | case 2: |
| 14612 | // op: rs1 |
| 14613 | return 15; |
| 14614 | case 1: |
| 14615 | // op: vd |
| 14616 | return 7; |
| 14617 | } |
| 14618 | break; |
| 14619 | } |
| 14620 | case RISCV::CV_SB_ri_inc: |
| 14621 | case RISCV::CV_SH_ri_inc: |
| 14622 | case RISCV::CV_SW_ri_inc: { |
| 14623 | switch (OpNum) { |
| 14624 | case 3: |
| 14625 | // op: imm12 |
| 14626 | return 7; |
| 14627 | case 1: |
| 14628 | // op: rs2 |
| 14629 | return 20; |
| 14630 | case 2: |
| 14631 | // op: rs1 |
| 14632 | return 15; |
| 14633 | } |
| 14634 | break; |
| 14635 | } |
| 14636 | case RISCV::MIPS_SDP: { |
| 14637 | switch (OpNum) { |
| 14638 | case 3: |
| 14639 | // op: imm7 |
| 14640 | return 10; |
| 14641 | case 1: |
| 14642 | // op: rs3 |
| 14643 | return 27; |
| 14644 | case 0: |
| 14645 | // op: rs2 |
| 14646 | return 20; |
| 14647 | case 2: |
| 14648 | // op: rs1 |
| 14649 | return 15; |
| 14650 | } |
| 14651 | break; |
| 14652 | } |
| 14653 | case RISCV::MIPS_LWP: { |
| 14654 | switch (OpNum) { |
| 14655 | case 3: |
| 14656 | // op: imm7 |
| 14657 | return 22; |
| 14658 | case 2: |
| 14659 | // op: rs1 |
| 14660 | return 15; |
| 14661 | case 0: |
| 14662 | // op: rd1 |
| 14663 | return 7; |
| 14664 | case 1: |
| 14665 | // op: rd2 |
| 14666 | return 27; |
| 14667 | } |
| 14668 | break; |
| 14669 | } |
| 14670 | case RISCV::MIPS_LDP: { |
| 14671 | switch (OpNum) { |
| 14672 | case 3: |
| 14673 | // op: imm7 |
| 14674 | return 23; |
| 14675 | case 2: |
| 14676 | // op: rs1 |
| 14677 | return 15; |
| 14678 | case 0: |
| 14679 | // op: rd1 |
| 14680 | return 7; |
| 14681 | case 1: |
| 14682 | // op: rd2 |
| 14683 | return 27; |
| 14684 | } |
| 14685 | break; |
| 14686 | } |
| 14687 | case RISCV::MIPS_SWP: { |
| 14688 | switch (OpNum) { |
| 14689 | case 3: |
| 14690 | // op: imm7 |
| 14691 | return 9; |
| 14692 | case 1: |
| 14693 | // op: rs3 |
| 14694 | return 27; |
| 14695 | case 0: |
| 14696 | // op: rs2 |
| 14697 | return 20; |
| 14698 | case 2: |
| 14699 | // op: rs1 |
| 14700 | return 15; |
| 14701 | } |
| 14702 | break; |
| 14703 | } |
| 14704 | case RISCV::QC_SELECTIEQI: |
| 14705 | case RISCV::QC_SELECTINEI: { |
| 14706 | switch (OpNum) { |
| 14707 | case 3: |
| 14708 | // op: rs2 |
| 14709 | return 20; |
| 14710 | case 1: |
| 14711 | // op: rd |
| 14712 | return 7; |
| 14713 | case 2: |
| 14714 | // op: imm |
| 14715 | return 15; |
| 14716 | case 4: |
| 14717 | // op: simm2 |
| 14718 | return 27; |
| 14719 | } |
| 14720 | break; |
| 14721 | } |
| 14722 | case RISCV::CV_LBU_rr_inc: |
| 14723 | case RISCV::CV_LB_rr_inc: |
| 14724 | case RISCV::CV_LHU_rr_inc: |
| 14725 | case RISCV::CV_LH_rr_inc: |
| 14726 | case RISCV::CV_LW_rr_inc: { |
| 14727 | switch (OpNum) { |
| 14728 | case 3: |
| 14729 | // op: rs2 |
| 14730 | return 20; |
| 14731 | case 2: |
| 14732 | // op: rs1 |
| 14733 | return 15; |
| 14734 | case 0: |
| 14735 | // op: rd |
| 14736 | return 7; |
| 14737 | } |
| 14738 | break; |
| 14739 | } |
| 14740 | case RISCV::CV_MACHHSN: |
| 14741 | case RISCV::CV_MACHHSRN: |
| 14742 | case RISCV::CV_MACHHUN: |
| 14743 | case RISCV::CV_MACHHURN: |
| 14744 | case RISCV::CV_MACSN: |
| 14745 | case RISCV::CV_MACSRN: |
| 14746 | case RISCV::CV_MACUN: |
| 14747 | case RISCV::CV_MACURN: { |
| 14748 | switch (OpNum) { |
| 14749 | case 3: |
| 14750 | // op: rs2 |
| 14751 | return 20; |
| 14752 | case 2: |
| 14753 | // op: rs1 |
| 14754 | return 15; |
| 14755 | case 1: |
| 14756 | // op: rd |
| 14757 | return 7; |
| 14758 | case 4: |
| 14759 | // op: imm5 |
| 14760 | return 25; |
| 14761 | } |
| 14762 | break; |
| 14763 | } |
| 14764 | case RISCV::QC_LIEQ: |
| 14765 | case RISCV::QC_LIEQI: |
| 14766 | case RISCV::QC_LIGE: |
| 14767 | case RISCV::QC_LIGEI: |
| 14768 | case RISCV::QC_LIGEU: |
| 14769 | case RISCV::QC_LIGEUI: |
| 14770 | case RISCV::QC_LILT: |
| 14771 | case RISCV::QC_LILTI: |
| 14772 | case RISCV::QC_LILTU: |
| 14773 | case RISCV::QC_LILTUI: |
| 14774 | case RISCV::QC_LINE: |
| 14775 | case RISCV::QC_LINEI: { |
| 14776 | switch (OpNum) { |
| 14777 | case 3: |
| 14778 | // op: rs2 |
| 14779 | return 20; |
| 14780 | case 2: |
| 14781 | // op: rs1 |
| 14782 | return 15; |
| 14783 | case 1: |
| 14784 | // op: rd |
| 14785 | return 7; |
| 14786 | case 4: |
| 14787 | // op: simm |
| 14788 | return 27; |
| 14789 | } |
| 14790 | break; |
| 14791 | } |
| 14792 | case RISCV::QC_SELECTIEQ: |
| 14793 | case RISCV::QC_SELECTINE: { |
| 14794 | switch (OpNum) { |
| 14795 | case 3: |
| 14796 | // op: rs2 |
| 14797 | return 20; |
| 14798 | case 2: |
| 14799 | // op: rs1 |
| 14800 | return 15; |
| 14801 | case 1: |
| 14802 | // op: rd |
| 14803 | return 7; |
| 14804 | case 4: |
| 14805 | // op: simm2 |
| 14806 | return 27; |
| 14807 | } |
| 14808 | break; |
| 14809 | } |
| 14810 | case RISCV::CV_ADDNR: |
| 14811 | case RISCV::CV_ADDRNR: |
| 14812 | case RISCV::CV_ADDUNR: |
| 14813 | case RISCV::CV_ADDURNR: |
| 14814 | case RISCV::CV_CPLXMUL_I: |
| 14815 | case RISCV::CV_CPLXMUL_I_DIV2: |
| 14816 | case RISCV::CV_CPLXMUL_I_DIV4: |
| 14817 | case RISCV::CV_CPLXMUL_I_DIV8: |
| 14818 | case RISCV::CV_CPLXMUL_R: |
| 14819 | case RISCV::CV_CPLXMUL_R_DIV2: |
| 14820 | case RISCV::CV_CPLXMUL_R_DIV4: |
| 14821 | case RISCV::CV_CPLXMUL_R_DIV8: |
| 14822 | case RISCV::CV_INSERTR: |
| 14823 | case RISCV::CV_MAC: |
| 14824 | case RISCV::CV_MSU: |
| 14825 | case RISCV::CV_PACKHI_B: |
| 14826 | case RISCV::CV_PACKLO_B: |
| 14827 | case RISCV::CV_SDOTSP_B: |
| 14828 | case RISCV::CV_SDOTSP_H: |
| 14829 | case RISCV::CV_SDOTSP_SC_B: |
| 14830 | case RISCV::CV_SDOTSP_SC_H: |
| 14831 | case RISCV::CV_SDOTUP_B: |
| 14832 | case RISCV::CV_SDOTUP_H: |
| 14833 | case RISCV::CV_SDOTUP_SC_B: |
| 14834 | case RISCV::CV_SDOTUP_SC_H: |
| 14835 | case RISCV::CV_SDOTUSP_B: |
| 14836 | case RISCV::CV_SDOTUSP_H: |
| 14837 | case RISCV::CV_SDOTUSP_SC_B: |
| 14838 | case RISCV::CV_SDOTUSP_SC_H: |
| 14839 | case RISCV::CV_SHUFFLE2_B: |
| 14840 | case RISCV::CV_SHUFFLE2_H: |
| 14841 | case RISCV::CV_SUBNR: |
| 14842 | case RISCV::CV_SUBRNR: |
| 14843 | case RISCV::CV_SUBUNR: |
| 14844 | case RISCV::CV_SUBURNR: |
| 14845 | case RISCV::MACCSU_H00: |
| 14846 | case RISCV::MACCSU_H11: |
| 14847 | case RISCV::MACCSU_W00: |
| 14848 | case RISCV::MACCSU_W11: |
| 14849 | case RISCV::MACCU_H00: |
| 14850 | case RISCV::MACCU_H01: |
| 14851 | case RISCV::MACCU_H11: |
| 14852 | case RISCV::MACCU_W00: |
| 14853 | case RISCV::MACCU_W01: |
| 14854 | case RISCV::MACCU_W11: |
| 14855 | case RISCV::MACC_H00: |
| 14856 | case RISCV::MACC_H01: |
| 14857 | case RISCV::MACC_H11: |
| 14858 | case RISCV::MACC_W00: |
| 14859 | case RISCV::MACC_W01: |
| 14860 | case RISCV::MACC_W11: |
| 14861 | case RISCV::MERGE: |
| 14862 | case RISCV::MHACC: |
| 14863 | case RISCV::MHACCSU: |
| 14864 | case RISCV::MHACCSU_H0: |
| 14865 | case RISCV::MHACCSU_H1: |
| 14866 | case RISCV::MHACCU: |
| 14867 | case RISCV::MHACC_H0: |
| 14868 | case RISCV::MHACC_H1: |
| 14869 | case RISCV::MHRACC: |
| 14870 | case RISCV::MHRACCSU: |
| 14871 | case RISCV::MHRACCU: |
| 14872 | case RISCV::MQACC_H00: |
| 14873 | case RISCV::MQACC_H01: |
| 14874 | case RISCV::MQACC_H11: |
| 14875 | case RISCV::MQACC_W00: |
| 14876 | case RISCV::MQACC_W01: |
| 14877 | case RISCV::MQACC_W11: |
| 14878 | case RISCV::MQRACC_H00: |
| 14879 | case RISCV::MQRACC_H01: |
| 14880 | case RISCV::MQRACC_H11: |
| 14881 | case RISCV::MQRACC_W00: |
| 14882 | case RISCV::MQRACC_W01: |
| 14883 | case RISCV::MQRACC_W11: |
| 14884 | case RISCV::MVM: |
| 14885 | case RISCV::MVMN: |
| 14886 | case RISCV::PABDSUMAU_B: |
| 14887 | case RISCV::PM2ADDASU_H: |
| 14888 | case RISCV::PM2ADDASU_W: |
| 14889 | case RISCV::PM2ADDAU_H: |
| 14890 | case RISCV::PM2ADDAU_W: |
| 14891 | case RISCV::PM2ADDA_H: |
| 14892 | case RISCV::PM2ADDA_HX: |
| 14893 | case RISCV::PM2ADDA_W: |
| 14894 | case RISCV::PM2ADDA_WX: |
| 14895 | case RISCV::PM2SUBA_H: |
| 14896 | case RISCV::PM2SUBA_HX: |
| 14897 | case RISCV::PM2SUBA_W: |
| 14898 | case RISCV::PM2SUBA_WX: |
| 14899 | case RISCV::PM4ADDASU_B: |
| 14900 | case RISCV::PM4ADDASU_H: |
| 14901 | case RISCV::PM4ADDAU_B: |
| 14902 | case RISCV::PM4ADDAU_H: |
| 14903 | case RISCV::PM4ADDA_B: |
| 14904 | case RISCV::PM4ADDA_H: |
| 14905 | case RISCV::PMACCSU_W_H00: |
| 14906 | case RISCV::PMACCSU_W_H11: |
| 14907 | case RISCV::PMACCU_W_H00: |
| 14908 | case RISCV::PMACCU_W_H01: |
| 14909 | case RISCV::PMACCU_W_H11: |
| 14910 | case RISCV::PMACC_W_H00: |
| 14911 | case RISCV::PMACC_W_H01: |
| 14912 | case RISCV::PMACC_W_H11: |
| 14913 | case RISCV::PMHACCSU_H: |
| 14914 | case RISCV::PMHACCSU_H_B0: |
| 14915 | case RISCV::PMHACCSU_H_B1: |
| 14916 | case RISCV::PMHACCSU_W: |
| 14917 | case RISCV::PMHACCSU_W_H0: |
| 14918 | case RISCV::PMHACCSU_W_H1: |
| 14919 | case RISCV::PMHACCU_H: |
| 14920 | case RISCV::PMHACCU_W: |
| 14921 | case RISCV::PMHACC_H: |
| 14922 | case RISCV::PMHACC_H_B0: |
| 14923 | case RISCV::PMHACC_H_B1: |
| 14924 | case RISCV::PMHACC_W: |
| 14925 | case RISCV::PMHACC_W_H0: |
| 14926 | case RISCV::PMHACC_W_H1: |
| 14927 | case RISCV::PMHRACCSU_H: |
| 14928 | case RISCV::PMHRACCSU_W: |
| 14929 | case RISCV::PMHRACCU_H: |
| 14930 | case RISCV::PMHRACCU_W: |
| 14931 | case RISCV::PMHRACC_H: |
| 14932 | case RISCV::PMHRACC_W: |
| 14933 | case RISCV::PMQ2ADDA_H: |
| 14934 | case RISCV::PMQ2ADDA_W: |
| 14935 | case RISCV::PMQACC_W_H00: |
| 14936 | case RISCV::PMQACC_W_H01: |
| 14937 | case RISCV::PMQACC_W_H11: |
| 14938 | case RISCV::PMQR2ADDA_H: |
| 14939 | case RISCV::PMQR2ADDA_W: |
| 14940 | case RISCV::PMQRACC_W_H00: |
| 14941 | case RISCV::PMQRACC_W_H01: |
| 14942 | case RISCV::PMQRACC_W_H11: |
| 14943 | case RISCV::QC_INSBHR: |
| 14944 | case RISCV::QC_INSBPR: |
| 14945 | case RISCV::QC_INSBPRH: |
| 14946 | case RISCV::QC_INSBR: |
| 14947 | case RISCV::SLX: |
| 14948 | case RISCV::SRX: |
| 14949 | case RISCV::TH_MULA: |
| 14950 | case RISCV::TH_MULAH: |
| 14951 | case RISCV::TH_MULAW: |
| 14952 | case RISCV::TH_MULS: |
| 14953 | case RISCV::TH_MULSH: |
| 14954 | case RISCV::TH_MULSW: |
| 14955 | case RISCV::TH_MVEQZ: |
| 14956 | case RISCV::TH_MVNEZ: { |
| 14957 | switch (OpNum) { |
| 14958 | case 3: |
| 14959 | // op: rs2 |
| 14960 | return 20; |
| 14961 | case 2: |
| 14962 | // op: rs1 |
| 14963 | return 15; |
| 14964 | case 1: |
| 14965 | // op: rd |
| 14966 | return 7; |
| 14967 | } |
| 14968 | break; |
| 14969 | } |
| 14970 | case RISCV::MQRWACC: |
| 14971 | case RISCV::MQWACC: |
| 14972 | case RISCV::PM2WADDASU_H: |
| 14973 | case RISCV::PM2WADDAU_H: |
| 14974 | case RISCV::PM2WADDA_H: |
| 14975 | case RISCV::PM2WADDA_HX: |
| 14976 | case RISCV::PM2WSUBA_H: |
| 14977 | case RISCV::PM2WSUBA_HX: |
| 14978 | case RISCV::PMQRWACC_H: |
| 14979 | case RISCV::PMQWACC_H: |
| 14980 | case RISCV::PWADDAU_B: |
| 14981 | case RISCV::PWADDAU_H: |
| 14982 | case RISCV::PWADDA_B: |
| 14983 | case RISCV::PWADDA_H: |
| 14984 | case RISCV::PWMACCSU_H: |
| 14985 | case RISCV::PWMACCU_H: |
| 14986 | case RISCV::PWMACC_H: |
| 14987 | case RISCV::PWSUBAU_B: |
| 14988 | case RISCV::PWSUBAU_H: |
| 14989 | case RISCV::PWSUBA_B: |
| 14990 | case RISCV::PWSUBA_H: |
| 14991 | case RISCV::WADDA: |
| 14992 | case RISCV::WADDAU: |
| 14993 | case RISCV::WMACC: |
| 14994 | case RISCV::WMACCSU: |
| 14995 | case RISCV::WMACCU: |
| 14996 | case RISCV::WSUBA: |
| 14997 | case RISCV::WSUBAU: { |
| 14998 | switch (OpNum) { |
| 14999 | case 3: |
| 15000 | // op: rs2 |
| 15001 | return 20; |
| 15002 | case 2: |
| 15003 | // op: rs1 |
| 15004 | return 15; |
| 15005 | case 1: |
| 15006 | // op: rd |
| 15007 | return 8; |
| 15008 | } |
| 15009 | break; |
| 15010 | } |
| 15011 | case RISCV::MIPS_CCMOV: { |
| 15012 | switch (OpNum) { |
| 15013 | case 3: |
| 15014 | // op: rs3 |
| 15015 | return 27; |
| 15016 | case 2: |
| 15017 | // op: rs2 |
| 15018 | return 20; |
| 15019 | case 1: |
| 15020 | // op: rs1 |
| 15021 | return 15; |
| 15022 | case 0: |
| 15023 | // op: rd |
| 15024 | return 7; |
| 15025 | } |
| 15026 | break; |
| 15027 | } |
| 15028 | case RISCV::FMADD_D: |
| 15029 | case RISCV::FMADD_D_IN32X: |
| 15030 | case RISCV::FMADD_D_INX: |
| 15031 | case RISCV::FMADD_H: |
| 15032 | case RISCV::FMADD_H_INX: |
| 15033 | case RISCV::FMADD_Q: |
| 15034 | case RISCV::FMADD_S: |
| 15035 | case RISCV::FMADD_S_INX: |
| 15036 | case RISCV::FMSUB_D: |
| 15037 | case RISCV::FMSUB_D_IN32X: |
| 15038 | case RISCV::FMSUB_D_INX: |
| 15039 | case RISCV::FMSUB_H: |
| 15040 | case RISCV::FMSUB_H_INX: |
| 15041 | case RISCV::FMSUB_Q: |
| 15042 | case RISCV::FMSUB_S: |
| 15043 | case RISCV::FMSUB_S_INX: |
| 15044 | case RISCV::FNMADD_D: |
| 15045 | case RISCV::FNMADD_D_IN32X: |
| 15046 | case RISCV::FNMADD_D_INX: |
| 15047 | case RISCV::FNMADD_H: |
| 15048 | case RISCV::FNMADD_H_INX: |
| 15049 | case RISCV::FNMADD_Q: |
| 15050 | case RISCV::FNMADD_S: |
| 15051 | case RISCV::FNMADD_S_INX: |
| 15052 | case RISCV::FNMSUB_D: |
| 15053 | case RISCV::FNMSUB_D_IN32X: |
| 15054 | case RISCV::FNMSUB_D_INX: |
| 15055 | case RISCV::FNMSUB_H: |
| 15056 | case RISCV::FNMSUB_H_INX: |
| 15057 | case RISCV::FNMSUB_Q: |
| 15058 | case RISCV::FNMSUB_S: |
| 15059 | case RISCV::FNMSUB_S_INX: { |
| 15060 | switch (OpNum) { |
| 15061 | case 3: |
| 15062 | // op: rs3 |
| 15063 | return 27; |
| 15064 | case 2: |
| 15065 | // op: rs2 |
| 15066 | return 20; |
| 15067 | case 1: |
| 15068 | // op: rs1 |
| 15069 | return 15; |
| 15070 | case 4: |
| 15071 | // op: frm |
| 15072 | return 12; |
| 15073 | case 0: |
| 15074 | // op: rd |
| 15075 | return 7; |
| 15076 | } |
| 15077 | break; |
| 15078 | } |
| 15079 | case RISCV::CV_SB_rr_inc: |
| 15080 | case RISCV::CV_SH_rr_inc: |
| 15081 | case RISCV::CV_SW_rr_inc: { |
| 15082 | switch (OpNum) { |
| 15083 | case 3: |
| 15084 | // op: rs3 |
| 15085 | return 7; |
| 15086 | case 1: |
| 15087 | // op: rs2 |
| 15088 | return 20; |
| 15089 | case 2: |
| 15090 | // op: rs1 |
| 15091 | return 15; |
| 15092 | } |
| 15093 | break; |
| 15094 | } |
| 15095 | case RISCV::SF_VC_V_IVV: |
| 15096 | case RISCV::SF_VC_V_IVW: { |
| 15097 | switch (OpNum) { |
| 15098 | case 3: |
| 15099 | // op: vs2 |
| 15100 | return 20; |
| 15101 | case 2: |
| 15102 | // op: vd |
| 15103 | return 7; |
| 15104 | case 4: |
| 15105 | // op: imm |
| 15106 | return 15; |
| 15107 | case 1: |
| 15108 | // op: funct6_lo2 |
| 15109 | return 26; |
| 15110 | } |
| 15111 | break; |
| 15112 | } |
| 15113 | case RISCV::SF_VC_V_FVV: |
| 15114 | case RISCV::SF_VC_V_FVW: { |
| 15115 | switch (OpNum) { |
| 15116 | case 3: |
| 15117 | // op: vs2 |
| 15118 | return 20; |
| 15119 | case 2: |
| 15120 | // op: vd |
| 15121 | return 7; |
| 15122 | case 4: |
| 15123 | // op: rs1 |
| 15124 | return 15; |
| 15125 | case 1: |
| 15126 | // op: funct6_lo1 |
| 15127 | return 26; |
| 15128 | } |
| 15129 | break; |
| 15130 | } |
| 15131 | case RISCV::SF_VC_V_XVV: |
| 15132 | case RISCV::SF_VC_V_XVW: { |
| 15133 | switch (OpNum) { |
| 15134 | case 3: |
| 15135 | // op: vs2 |
| 15136 | return 20; |
| 15137 | case 2: |
| 15138 | // op: vd |
| 15139 | return 7; |
| 15140 | case 4: |
| 15141 | // op: rs1 |
| 15142 | return 15; |
| 15143 | case 1: |
| 15144 | // op: funct6_lo2 |
| 15145 | return 26; |
| 15146 | } |
| 15147 | break; |
| 15148 | } |
| 15149 | case RISCV::SF_VC_V_VVV: |
| 15150 | case RISCV::SF_VC_V_VVW: { |
| 15151 | switch (OpNum) { |
| 15152 | case 3: |
| 15153 | // op: vs2 |
| 15154 | return 20; |
| 15155 | case 2: |
| 15156 | // op: vd |
| 15157 | return 7; |
| 15158 | case 4: |
| 15159 | // op: vs1 |
| 15160 | return 15; |
| 15161 | case 1: |
| 15162 | // op: funct6_lo2 |
| 15163 | return 26; |
| 15164 | } |
| 15165 | break; |
| 15166 | } |
| 15167 | case RISCV::QC_MVEQI: |
| 15168 | case RISCV::QC_MVGEI: |
| 15169 | case RISCV::QC_MVGEUI: |
| 15170 | case RISCV::QC_MVLTI: |
| 15171 | case RISCV::QC_MVLTUI: |
| 15172 | case RISCV::QC_MVNEI: { |
| 15173 | switch (OpNum) { |
| 15174 | case 4: |
| 15175 | // op: rs3 |
| 15176 | return 27; |
| 15177 | case 2: |
| 15178 | // op: rs1 |
| 15179 | return 15; |
| 15180 | case 1: |
| 15181 | // op: rd |
| 15182 | return 7; |
| 15183 | case 3: |
| 15184 | // op: imm |
| 15185 | return 20; |
| 15186 | } |
| 15187 | break; |
| 15188 | } |
| 15189 | case RISCV::QC_SELECTEQI: |
| 15190 | case RISCV::QC_SELECTNEI: { |
| 15191 | switch (OpNum) { |
| 15192 | case 4: |
| 15193 | // op: rs3 |
| 15194 | return 27; |
| 15195 | case 3: |
| 15196 | // op: rs2 |
| 15197 | return 20; |
| 15198 | case 1: |
| 15199 | // op: rd |
| 15200 | return 7; |
| 15201 | case 2: |
| 15202 | // op: imm |
| 15203 | return 15; |
| 15204 | } |
| 15205 | break; |
| 15206 | } |
| 15207 | case RISCV::QC_MVEQ: |
| 15208 | case RISCV::QC_MVGE: |
| 15209 | case RISCV::QC_MVGEU: |
| 15210 | case RISCV::QC_MVLT: |
| 15211 | case RISCV::QC_MVLTU: |
| 15212 | case RISCV::QC_MVNE: { |
| 15213 | switch (OpNum) { |
| 15214 | case 4: |
| 15215 | // op: rs3 |
| 15216 | return 27; |
| 15217 | case 3: |
| 15218 | // op: rs2 |
| 15219 | return 20; |
| 15220 | case 2: |
| 15221 | // op: rs1 |
| 15222 | return 15; |
| 15223 | case 1: |
| 15224 | // op: rd |
| 15225 | return 7; |
| 15226 | } |
| 15227 | break; |
| 15228 | } |
| 15229 | default: |
| 15230 | reportUnsupportedInst(MI); |
| 15231 | } |
| 15232 | reportUnsupportedOperand(MI, OpNum); |
| 15233 | } |
| 15234 | |
| 15235 | #endif // GET_OPERAND_BIT_OFFSET |
| 15236 | |
| 15237 |
Generated while processing llvm_projects/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Generated on 2026-Mar-17 from project llvm_projects revision f28ef6899
Powered by 
Code Browser 2.1
Generator usage only permitted with license.