1//===-- RISCVMCCodeEmitter.cpp - Convert RISC-V code to machine code ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVFixupKinds.h"
15#include "MCTargetDesc/RISCVMCAsmInfo.h"
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCCodeEmitter.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstBuilder.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Support/Casting.h"
29#include "llvm/Support/EndianStream.h"
30
31using namespace llvm;
32
33#define DEBUG_TYPE "mccodeemitter"
34
35STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
36STATISTIC(MCNumFixups, "Number of MC fixups created");
37
38namespace {
39class RISCVMCCodeEmitter : public MCCodeEmitter {
40 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
41 void operator=(const RISCVMCCodeEmitter &) = delete;
42 MCContext &Ctx;
43 MCInstrInfo const &MCII;
44
45public:
46 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
47 : Ctx(ctx), MCII(MCII) {}
48
49 ~RISCVMCCodeEmitter() override = default;
50
51 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
52 SmallVectorImpl<MCFixup> &Fixups,
53 const MCSubtargetInfo &STI) const override;
54
55 void expandFunctionCall(const MCInst &MI, SmallVectorImpl<char> &CB,
56 SmallVectorImpl<MCFixup> &Fixups,
57 const MCSubtargetInfo &STI) const;
58
59 void expandTLSDESCCall(const MCInst &MI, SmallVectorImpl<char> &CB,
60 SmallVectorImpl<MCFixup> &Fixups,
61 const MCSubtargetInfo &STI) const;
62
63 void expandAddTPRel(const MCInst &MI, SmallVectorImpl<char> &CB,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const;
66
67 void expandLongCondBr(const MCInst &MI, SmallVectorImpl<char> &CB,
68 SmallVectorImpl<MCFixup> &Fixups,
69 const MCSubtargetInfo &STI) const;
70
71 void expandQCLongCondBrImm(const MCInst &MI, SmallVectorImpl<char> &CB,
72 SmallVectorImpl<MCFixup> &Fixups,
73 const MCSubtargetInfo &STI, unsigned Size) const;
74
75 /// TableGen'erated function for getting the binary encoding for an
76 /// instruction.
77 uint64_t getBinaryCodeForInstr(const MCInst &MI,
78 SmallVectorImpl<MCFixup> &Fixups,
79 const MCSubtargetInfo &STI) const;
80
81 /// Return binary encoding of operand. If the machine operand requires
82 /// relocation, record the relocation and return zero.
83 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
84 SmallVectorImpl<MCFixup> &Fixups,
85 const MCSubtargetInfo &STI) const;
86
87 uint64_t getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
88 SmallVectorImpl<MCFixup> &Fixups,
89 const MCSubtargetInfo &STI) const;
90
91 uint64_t getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
92 SmallVectorImpl<MCFixup> &Fixups,
93 const MCSubtargetInfo &STI) const;
94
95 template <unsigned N>
96 unsigned getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
97 SmallVectorImpl<MCFixup> &Fixups,
98 const MCSubtargetInfo &STI) const;
99
100 uint64_t getImmOpValueZibi(const MCInst &MI, unsigned OpNo,
101 SmallVectorImpl<MCFixup> &Fixups,
102 const MCSubtargetInfo &STI) const;
103
104 uint64_t getImmOpValue(const MCInst &MI, unsigned OpNo,
105 SmallVectorImpl<MCFixup> &Fixups,
106 const MCSubtargetInfo &STI) const;
107
108 unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
109 SmallVectorImpl<MCFixup> &Fixups,
110 const MCSubtargetInfo &STI) const;
111
112 unsigned getRlistOpValue(const MCInst &MI, unsigned OpNo,
113 SmallVectorImpl<MCFixup> &Fixups,
114 const MCSubtargetInfo &STI) const;
115
116 unsigned getRlistS0OpValue(const MCInst &MI, unsigned OpNo,
117 SmallVectorImpl<MCFixup> &Fixups,
118 const MCSubtargetInfo &STI) const;
119};
120} // end anonymous namespace
121
122MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
123 MCContext &Ctx) {
124 return new RISCVMCCodeEmitter(Ctx, MCII);
125}
126
127static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
128 const MCExpr *Value, uint16_t Kind) {
129 bool PCRel = false;
130 switch (Kind) {
131 case ELF::R_RISCV_CALL_PLT:
132 case RISCV::fixup_riscv_pcrel_hi20:
133 case RISCV::fixup_riscv_pcrel_lo12_i:
134 case RISCV::fixup_riscv_pcrel_lo12_s:
135 case RISCV::fixup_riscv_jal:
136 case RISCV::fixup_riscv_branch:
137 case RISCV::fixup_riscv_rvc_jump:
138 case RISCV::fixup_riscv_rvc_branch:
139 case RISCV::fixup_riscv_call:
140 case RISCV::fixup_riscv_call_plt:
141 case RISCV::fixup_riscv_qc_e_branch:
142 case RISCV::fixup_riscv_qc_e_call_plt:
143 case RISCV::fixup_riscv_nds_branch_10:
144 PCRel = true;
145 }
146 Fixups.push_back(Elt: MCFixup::create(Offset, Value, Kind, PCRel));
147}
148
149// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
150// relocation types. We expand those pseudo-instructions while encoding them,
151// meaning AUIPC and JALR won't go through RISC-V MC to MC compressed
152// instruction transformation. This is acceptable because AUIPC has no 16-bit
153// form and C_JALR has no immediate operand field. We let linker relaxation
154// deal with it. When linker relaxation is enabled, AUIPC and JALR have a
155// chance to relax to JAL.
156// If the C extension is enabled, JAL has a chance relax to C_JAL.
157void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI,
158 SmallVectorImpl<char> &CB,
159 SmallVectorImpl<MCFixup> &Fixups,
160 const MCSubtargetInfo &STI) const {
161 MCInst TmpInst;
162 MCOperand Func;
163 MCRegister Ra;
164 if (MI.getOpcode() == RISCV::PseudoTAIL) {
165 Func = MI.getOperand(i: 0);
166 Ra = RISCVII::getTailExpandUseRegNo(FeatureBits: STI.getFeatureBits());
167 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
168 Func = MI.getOperand(i: 1);
169 Ra = MI.getOperand(i: 0).getReg();
170 } else if (MI.getOpcode() == RISCV::PseudoCALL) {
171 Func = MI.getOperand(i: 0);
172 Ra = RISCV::X1;
173 } else if (MI.getOpcode() == RISCV::PseudoJump) {
174 Func = MI.getOperand(i: 1);
175 Ra = MI.getOperand(i: 0).getReg();
176 }
177 uint32_t Binary;
178
179 assert(Func.isExpr() && "Expected expression");
180
181 const MCExpr *CallExpr = Func.getExpr();
182
183 if (STI.getTargetTriple().isOSBinFormatMachO()) {
184 MCOperand FuncOp = MCOperand::createExpr(Val: CallExpr);
185 if (MI.getOpcode() == RISCV::PseudoTAIL ||
186 MI.getOpcode() == RISCV::PseudoJump)
187 // Emit JAL X0, Func
188 TmpInst = MCInstBuilder(RISCV::JAL).addReg(Reg: RISCV::X0).addOperand(Op: FuncOp);
189 else
190 // Emit JAL Ra, Func
191 TmpInst = MCInstBuilder(RISCV::JAL).addReg(Reg: Ra).addOperand(Op: FuncOp);
192 Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
193 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
194 return;
195 }
196 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
197 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Reg: Ra).addExpr(Val: CallExpr);
198 Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
199 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
200
201 if (MI.getOpcode() == RISCV::PseudoTAIL ||
202 MI.getOpcode() == RISCV::PseudoJump)
203 // Emit JALR X0, Ra, 0
204 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Reg: RISCV::X0).addReg(Reg: Ra).addImm(Val: 0);
205 else
206 // Emit JALR Ra, Ra, 0
207 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Reg: Ra).addReg(Reg: Ra).addImm(Val: 0);
208 Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
209 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
210}
211
212void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
213 SmallVectorImpl<char> &CB,
214 SmallVectorImpl<MCFixup> &Fixups,
215 const MCSubtargetInfo &STI) const {
216 MCOperand SrcSymbol = MI.getOperand(i: 3);
217 assert(SrcSymbol.isExpr() &&
218 "Expected expression as first input to TLSDESCCALL");
219 const auto *Expr = dyn_cast<MCSpecifierExpr>(Val: SrcSymbol.getExpr());
220 MCRegister Link = MI.getOperand(i: 0).getReg();
221 MCRegister Dest = MI.getOperand(i: 1).getReg();
222 int64_t Imm = MI.getOperand(i: 2).getImm();
223 addFixup(Fixups, Offset: 0, Value: Expr, Kind: ELF::R_RISCV_TLSDESC_CALL);
224 MCInst Call =
225 MCInstBuilder(RISCV::JALR).addReg(Reg: Link).addReg(Reg: Dest).addImm(Val: Imm);
226
227 uint32_t Binary = getBinaryCodeForInstr(MI: Call, Fixups, STI);
228 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
229}
230
231// Expand PseudoAddTPRel to a simple ADD with the correct relocation.
232void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
233 SmallVectorImpl<char> &CB,
234 SmallVectorImpl<MCFixup> &Fixups,
235 const MCSubtargetInfo &STI) const {
236 MCOperand DestReg = MI.getOperand(i: 0);
237 MCOperand SrcReg = MI.getOperand(i: 1);
238 MCOperand TPReg = MI.getOperand(i: 2);
239 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
240 "Expected thread pointer as second input to TP-relative add");
241
242 MCOperand SrcSymbol = MI.getOperand(i: 3);
243 assert(SrcSymbol.isExpr() &&
244 "Expected expression as third input to TP-relative add");
245
246 const auto *Expr = dyn_cast<MCSpecifierExpr>(Val: SrcSymbol.getExpr());
247 assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
248 "Expected tprel_add relocation on TP-relative symbol");
249
250 addFixup(Fixups, Offset: 0, Value: Expr, Kind: ELF::R_RISCV_TPREL_ADD);
251 if (STI.hasFeature(Feature: RISCV::FeatureRelax))
252 Fixups.back().setLinkerRelaxable();
253
254 // Emit a normal ADD instruction with the given operands.
255 MCInst TmpInst = MCInstBuilder(RISCV::ADD)
256 .addOperand(Op: DestReg)
257 .addOperand(Op: SrcReg)
258 .addOperand(Op: TPReg);
259 uint32_t Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
260 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
261}
262
263static unsigned getInvertedBranchOp(unsigned BrOp) {
264 switch (BrOp) {
265 default:
266 llvm_unreachable("Unexpected branch opcode!");
267 case RISCV::PseudoLongBEQ:
268 return RISCV::BNE;
269 case RISCV::PseudoLongBNE:
270 return RISCV::BEQ;
271 case RISCV::PseudoLongBEQI:
272 return RISCV::BNEI;
273 case RISCV::PseudoLongBNEI:
274 return RISCV::BEQI;
275 case RISCV::PseudoLongBLT:
276 return RISCV::BGE;
277 case RISCV::PseudoLongBGE:
278 return RISCV::BLT;
279 case RISCV::PseudoLongBLTU:
280 return RISCV::BGEU;
281 case RISCV::PseudoLongBGEU:
282 return RISCV::BLTU;
283 case RISCV::PseudoLongQC_BEQI:
284 return RISCV::QC_BNEI;
285 case RISCV::PseudoLongQC_BNEI:
286 return RISCV::QC_BEQI;
287 case RISCV::PseudoLongQC_BLTI:
288 return RISCV::QC_BGEI;
289 case RISCV::PseudoLongQC_BGEI:
290 return RISCV::QC_BLTI;
291 case RISCV::PseudoLongQC_BLTUI:
292 return RISCV::QC_BGEUI;
293 case RISCV::PseudoLongQC_BGEUI:
294 return RISCV::QC_BLTUI;
295 case RISCV::PseudoLongQC_E_BEQI:
296 return RISCV::QC_E_BNEI;
297 case RISCV::PseudoLongQC_E_BNEI:
298 return RISCV::QC_E_BEQI;
299 case RISCV::PseudoLongQC_E_BLTI:
300 return RISCV::QC_E_BGEI;
301 case RISCV::PseudoLongQC_E_BGEI:
302 return RISCV::QC_E_BLTI;
303 case RISCV::PseudoLongQC_E_BLTUI:
304 return RISCV::QC_E_BGEUI;
305 case RISCV::PseudoLongQC_E_BGEUI:
306 return RISCV::QC_E_BLTUI;
307 }
308}
309
310// Expand PseudoLongBxx to an inverted conditional branch and an unconditional
311// jump.
312void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
313 SmallVectorImpl<char> &CB,
314 SmallVectorImpl<MCFixup> &Fixups,
315 const MCSubtargetInfo &STI) const {
316 MCRegister SrcReg1 = MI.getOperand(i: 0).getReg();
317 const MCOperand &Src2 = MI.getOperand(i: 1);
318 const MCOperand &SrcSymbol = MI.getOperand(i: 2);
319 unsigned Opcode = MI.getOpcode();
320 bool IsEqTest =
321 Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ;
322
323 bool UseCompressedBr = false;
324 if (IsEqTest && STI.hasFeature(Feature: RISCV::FeatureStdExtZca)) {
325 MCRegister SrcReg2 = Src2.getReg();
326 if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 &&
327 SrcReg2.id() == RISCV::X0) {
328 UseCompressedBr = true;
329 } else if (RISCV::X8 <= SrcReg2.id() && SrcReg2.id() <= RISCV::X15 &&
330 SrcReg1.id() == RISCV::X0) {
331 std::swap(a&: SrcReg1, b&: SrcReg2);
332 UseCompressedBr = true;
333 }
334 }
335
336 uint32_t Offset;
337 if (UseCompressedBr) {
338 unsigned InvOpc =
339 Opcode == RISCV::PseudoLongBNE ? RISCV::C_BEQZ : RISCV::C_BNEZ;
340 MCInst TmpInst = MCInstBuilder(InvOpc).addReg(Reg: SrcReg1).addImm(Val: 6);
341 uint16_t Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
342 support::endian::write<uint16_t>(Out&: CB, V: Binary, E: llvm::endianness::little);
343 Offset = 2;
344 } else {
345 unsigned InvOpc = getInvertedBranchOp(BrOp: Opcode);
346 MCInst TmpInst =
347 MCInstBuilder(InvOpc).addReg(Reg: SrcReg1).addOperand(Op: Src2).addImm(Val: 8);
348 uint32_t Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
349 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
350 Offset = 4;
351 }
352
353 // Save the number fixups.
354 size_t FixupStartIndex = Fixups.size();
355
356 // Emit an unconditional jump to the destination.
357 MCInst TmpInst =
358 MCInstBuilder(RISCV::JAL).addReg(Reg: RISCV::X0).addOperand(Op: SrcSymbol);
359 uint32_t Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
360 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
361
362 // Drop any fixup added so we can add the correct one.
363 Fixups.resize(N: FixupStartIndex);
364
365 if (SrcSymbol.isExpr()) {
366 addFixup(Fixups, Offset, Value: SrcSymbol.getExpr(), Kind: RISCV::fixup_riscv_jal);
367 if (STI.hasFeature(Feature: RISCV::FeatureRelax))
368 Fixups.back().setLinkerRelaxable();
369 }
370}
371
372// Expand PseudoLongQC_(E_)Bxxx to an inverted conditional branch and an
373// unconditional jump.
374void RISCVMCCodeEmitter::expandQCLongCondBrImm(const MCInst &MI,
375 SmallVectorImpl<char> &CB,
376 SmallVectorImpl<MCFixup> &Fixups,
377 const MCSubtargetInfo &STI,
378 unsigned Size) const {
379 MCRegister SrcReg1 = MI.getOperand(i: 0).getReg();
380 auto BrImm = MI.getOperand(i: 1).getImm();
381 MCOperand SrcSymbol = MI.getOperand(i: 2);
382 unsigned Opcode = MI.getOpcode();
383 uint32_t Offset;
384 unsigned InvOpc = getInvertedBranchOp(BrOp: Opcode);
385 // Emit inverted conditional branch with offset:
386 // 8 (QC.BXXX(4) + JAL(4))
387 // or
388 // 10 (QC.E.BXXX(6) + JAL(4)).
389 if (Size == 4) {
390 MCInst TmpBr =
391 MCInstBuilder(InvOpc).addReg(Reg: SrcReg1).addImm(Val: BrImm).addImm(Val: 8);
392 uint32_t BrBinary = getBinaryCodeForInstr(MI: TmpBr, Fixups, STI);
393 support::endian::write(Out&: CB, V: BrBinary, E: llvm::endianness::little);
394 } else {
395 MCInst TmpBr =
396 MCInstBuilder(InvOpc).addReg(Reg: SrcReg1).addImm(Val: BrImm).addImm(Val: 10);
397 uint64_t BrBinary =
398 getBinaryCodeForInstr(MI: TmpBr, Fixups, STI) & 0xffff'ffff'ffffu;
399 SmallVector<char, 8> Encoding;
400 support::endian::write(Out&: Encoding, V: BrBinary, E: llvm::endianness::little);
401 assert(Encoding[6] == 0 && Encoding[7] == 0 &&
402 "Unexpected encoding for 48-bit instruction");
403 Encoding.truncate(N: 6);
404 CB.append(RHS: Encoding);
405 }
406 Offset = Size;
407 // Save the number fixups.
408 size_t FixupStartIndex = Fixups.size();
409 // Emit an unconditional jump to the destination.
410 MCInst TmpJ =
411 MCInstBuilder(RISCV::JAL).addReg(Reg: RISCV::X0).addOperand(Op: SrcSymbol);
412 uint32_t JBinary = getBinaryCodeForInstr(MI: TmpJ, Fixups, STI);
413 support::endian::write(Out&: CB, V: JBinary, E: llvm::endianness::little);
414 // Drop any fixup added so we can add the correct one.
415 Fixups.resize(N: FixupStartIndex);
416 if (SrcSymbol.isExpr()) {
417 addFixup(Fixups, Offset, Value: SrcSymbol.getExpr(), Kind: RISCV::fixup_riscv_jal);
418 if (STI.hasFeature(Feature: RISCV::FeatureRelax))
419 Fixups.back().setLinkerRelaxable();
420 }
421}
422
423void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI,
424 SmallVectorImpl<char> &CB,
425 SmallVectorImpl<MCFixup> &Fixups,
426 const MCSubtargetInfo &STI) const {
427 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
428 // Get byte count of instruction.
429 unsigned Size = Desc.getSize();
430
431 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
432 // expanded instructions for each pseudo is correct in the Size field of the
433 // tablegen definition for the pseudo.
434 switch (MI.getOpcode()) {
435 default:
436 break;
437 case RISCV::PseudoCALLReg:
438 case RISCV::PseudoCALL:
439 case RISCV::PseudoTAIL:
440 case RISCV::PseudoJump:
441 expandFunctionCall(MI, CB, Fixups, STI);
442 MCNumEmitted += 2;
443 return;
444 case RISCV::PseudoAddTPRel:
445 expandAddTPRel(MI, CB, Fixups, STI);
446 MCNumEmitted += 1;
447 return;
448 case RISCV::PseudoLongBEQ:
449 case RISCV::PseudoLongBNE:
450 case RISCV::PseudoLongBEQI:
451 case RISCV::PseudoLongBNEI:
452 case RISCV::PseudoLongBLT:
453 case RISCV::PseudoLongBGE:
454 case RISCV::PseudoLongBLTU:
455 case RISCV::PseudoLongBGEU:
456 expandLongCondBr(MI, CB, Fixups, STI);
457 MCNumEmitted += 2;
458 return;
459 case RISCV::PseudoLongQC_BEQI:
460 case RISCV::PseudoLongQC_BNEI:
461 case RISCV::PseudoLongQC_BLTI:
462 case RISCV::PseudoLongQC_BGEI:
463 case RISCV::PseudoLongQC_BLTUI:
464 case RISCV::PseudoLongQC_BGEUI:
465 expandQCLongCondBrImm(MI, CB, Fixups, STI, Size: 4);
466 MCNumEmitted += 2;
467 return;
468 case RISCV::PseudoLongQC_E_BEQI:
469 case RISCV::PseudoLongQC_E_BNEI:
470 case RISCV::PseudoLongQC_E_BLTI:
471 case RISCV::PseudoLongQC_E_BGEI:
472 case RISCV::PseudoLongQC_E_BLTUI:
473 case RISCV::PseudoLongQC_E_BGEUI:
474 expandQCLongCondBrImm(MI, CB, Fixups, STI, Size: 6);
475 MCNumEmitted += 2;
476 return;
477 case RISCV::PseudoTLSDESCCall:
478 expandTLSDESCCall(MI, CB, Fixups, STI);
479 MCNumEmitted += 1;
480 return;
481 }
482
483 switch (Size) {
484 default:
485 llvm_unreachable("Unhandled encodeInstruction length!");
486 case 2: {
487 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
488 support::endian::write<uint16_t>(Out&: CB, V: Bits, E: llvm::endianness::little);
489 break;
490 }
491 case 4: {
492 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
493 support::endian::write(Out&: CB, V: Bits, E: llvm::endianness::little);
494 break;
495 }
496 case 6: {
497 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI) & 0xffff'ffff'ffffu;
498 SmallVector<char, 8> Encoding;
499 support::endian::write(Out&: Encoding, V: Bits, E: llvm::endianness::little);
500 assert(Encoding[6] == 0 && Encoding[7] == 0 &&
501 "Unexpected encoding for 48-bit instruction");
502 Encoding.truncate(N: 6);
503 CB.append(RHS: Encoding);
504 break;
505 }
506 case 8: {
507 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
508 support::endian::write(Out&: CB, V: Bits, E: llvm::endianness::little);
509 break;
510 }
511 }
512
513 ++MCNumEmitted; // Keep track of the # of mi's emitted.
514}
515
516uint64_t
517RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
518 SmallVectorImpl<MCFixup> &Fixups,
519 const MCSubtargetInfo &STI) const {
520
521 if (MO.isReg())
522 return Ctx.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
523
524 if (MO.isImm())
525 return MO.getImm();
526
527 llvm_unreachable("Unhandled expression!");
528 return 0;
529}
530
531uint64_t
532RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
533 SmallVectorImpl<MCFixup> &Fixups,
534 const MCSubtargetInfo &STI) const {
535 const MCOperand &MO = MI.getOperand(i: OpNo);
536
537 if (MO.isImm()) {
538 uint64_t Res = MO.getImm();
539 return (Res - 1);
540 }
541
542 llvm_unreachable("Unhandled expression!");
543 return 0;
544}
545
546uint64_t
547RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
548 SmallVectorImpl<MCFixup> &Fixups,
549 const MCSubtargetInfo &STI) const {
550 const MCOperand &MO = MI.getOperand(i: OpNo);
551 assert(MO.isImm() && "Slist operand must be immediate");
552
553 uint64_t Res = MO.getImm();
554 switch (Res) {
555 case 0:
556 return 0;
557 case 1:
558 return 1;
559 case 2:
560 return 2;
561 case 4:
562 return 3;
563 case 8:
564 return 4;
565 case 16:
566 return 5;
567 case 15:
568 return 6;
569 case 31:
570 return 7;
571 default:
572 llvm_unreachable("Unhandled Slist value!");
573 }
574}
575
576template <unsigned N>
577unsigned
578RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
579 SmallVectorImpl<MCFixup> &Fixups,
580 const MCSubtargetInfo &STI) const {
581 const MCOperand &MO = MI.getOperand(i: OpNo);
582
583 if (MO.isImm()) {
584 uint64_t Res = MO.getImm();
585 assert((Res & ((1 << N) - 1)) == 0 && "LSB is non-zero");
586 return Res >> N;
587 }
588
589 return getImmOpValue(MI, OpNo, Fixups, STI);
590}
591
592uint64_t
593RISCVMCCodeEmitter::getImmOpValueZibi(const MCInst &MI, unsigned OpNo,
594 SmallVectorImpl<MCFixup> &Fixups,
595 const MCSubtargetInfo &STI) const {
596 const MCOperand &MO = MI.getOperand(i: OpNo);
597 assert(MO.isImm() && "Zibi operand must be an immediate");
598 int64_t Res = MO.getImm();
599 if (Res == -1)
600 return 0;
601
602 return Res;
603}
604
605uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
606 SmallVectorImpl<MCFixup> &Fixups,
607 const MCSubtargetInfo &STI) const {
608 bool EnableRelax = STI.hasFeature(Feature: RISCV::FeatureRelax);
609 const MCOperand &MO = MI.getOperand(i: OpNo);
610
611 MCInstrDesc const &Desc = MCII.get(Opcode: MI.getOpcode());
612 unsigned MIFrm = RISCVII::getFormat(TSFlags: Desc.TSFlags);
613
614 // If the destination is an immediate, there is nothing to do.
615 if (MO.isImm())
616 return MO.getImm();
617
618 assert(MO.isExpr() &&
619 "getImmOpValue expects only expressions or immediates");
620 const MCExpr *Expr = MO.getExpr();
621 MCExpr::ExprKind Kind = Expr->getKind();
622
623 // `RelaxCandidate` must be set to `true` in two cases:
624 // - The fixup's relocation gets a R_RISCV_RELAX relocation
625 // - The underlying instruction may be relaxed to an instruction that gets a
626 // `R_RISCV_RELAX` relocation.
627 //
628 // The actual emission of `R_RISCV_RELAX` will be handled in
629 // `RISCVAsmBackend::applyFixup`.
630 bool RelaxCandidate = false;
631 auto AsmRelaxToLinkerRelaxable = [&]() -> void {
632 if (!STI.hasFeature(Feature: RISCV::FeatureExactAssembly))
633 RelaxCandidate = true;
634 };
635
636 unsigned FixupKind = RISCV::fixup_riscv_invalid;
637 if (Kind == MCExpr::Specifier) {
638 const auto *RVExpr = cast<MCSpecifierExpr>(Val: Expr);
639 FixupKind = RVExpr->getSpecifier();
640 switch (RVExpr->getSpecifier()) {
641 default:
642 assert(FixupKind && FixupKind < FirstTargetFixupKind &&
643 "invalid specifier");
644 break;
645 case ELF::R_RISCV_TPREL_ADD:
646 // tprel_add is only used to indicate that a relocation should be emitted
647 // for an add instruction used in TP-relative addressing. It should not be
648 // expanded as if representing an actual instruction operand and so to
649 // encounter it here is an error.
650 llvm_unreachable(
651 "ELF::R_RISCV_TPREL_ADD should not represent an instruction operand");
652 case RISCV::S_LO:
653 if (MIFrm == RISCVII::InstFormatI)
654 FixupKind = RISCV::fixup_riscv_lo12_i;
655 else if (MIFrm == RISCVII::InstFormatS)
656 FixupKind = RISCV::fixup_riscv_lo12_s;
657 else
658 llvm_unreachable("VK_LO used with unexpected instruction format");
659 RelaxCandidate = true;
660 break;
661 case ELF::R_RISCV_HI20:
662 FixupKind = RISCV::fixup_riscv_hi20;
663 RelaxCandidate = true;
664 break;
665 case RISCV::S_PCREL_LO:
666 if (MIFrm == RISCVII::InstFormatI)
667 FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
668 else if (MIFrm == RISCVII::InstFormatS)
669 FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
670 else
671 llvm_unreachable("VK_PCREL_LO used with unexpected instruction format");
672 RelaxCandidate = true;
673 break;
674 case RISCV::S_PCREL_HI:
675 FixupKind = RISCV::fixup_riscv_pcrel_hi20;
676 RelaxCandidate = true;
677 break;
678 case RISCV::S_GOT_HI:
679 FixupKind = ELF::R_RISCV_GOT_HI20;
680 RelaxCandidate = true;
681 break;
682 case RISCV::S_TPREL_LO:
683 if (MIFrm == RISCVII::InstFormatI)
684 FixupKind = ELF::R_RISCV_TPREL_LO12_I;
685 else if (MIFrm == RISCVII::InstFormatS)
686 FixupKind = ELF::R_RISCV_TPREL_LO12_S;
687 else
688 llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
689 RelaxCandidate = true;
690 break;
691 case RISCV::S_CALL_PLT:
692 if (Ctx.getTargetTriple().isOSBinFormatMachO()) {
693 FixupKind = RISCV::fixup_riscv_jal;
694 break;
695 }
696 FixupKind = RISCV::fixup_riscv_call_plt;
697 RelaxCandidate = true;
698 break;
699 case RISCV::S_QC_ABS20:
700 FixupKind = RISCV::fixup_riscv_qc_abs20_u;
701 RelaxCandidate = true;
702 break;
703 case ELF::R_RISCV_GOT_HI20:
704 case ELF::R_RISCV_TPREL_HI20:
705 case ELF::R_RISCV_TLSDESC_HI20:
706 RelaxCandidate = true;
707 break;
708 }
709 } else if (Kind == MCExpr::SymbolRef || Kind == MCExpr::Binary) {
710 // FIXME: Sub kind binary exprs have chance of underflow.
711 if (MIFrm == RISCVII::InstFormatJ) {
712 FixupKind = RISCV::fixup_riscv_jal;
713 RelaxCandidate = true;
714 } else if (MIFrm == RISCVII::InstFormatB) {
715 FixupKind = RISCV::fixup_riscv_branch;
716 // Relaxes to B<cc>; JAL, with fixup_riscv_jal
717 AsmRelaxToLinkerRelaxable();
718 } else if (MIFrm == RISCVII::InstFormatCJ) {
719 FixupKind = RISCV::fixup_riscv_rvc_jump;
720 // Relaxes to JAL with fixup_riscv_jal
721 AsmRelaxToLinkerRelaxable();
722 } else if (MIFrm == RISCVII::InstFormatCB) {
723 FixupKind = RISCV::fixup_riscv_rvc_branch;
724 // Relaxes to B<cc>; JAL, with fixup_riscv_jal
725 AsmRelaxToLinkerRelaxable();
726 } else if (MIFrm == RISCVII::InstFormatCI) {
727 FixupKind = RISCV::fixup_riscv_rvc_imm;
728 // Relaxes to `QC.E.LI` with fixup_riscv_qc_e_32
729 if (STI.hasFeature(Feature: RISCV::FeatureVendorXqcili))
730 AsmRelaxToLinkerRelaxable();
731 } else if (MIFrm == RISCVII::InstFormatI) {
732 FixupKind = RISCV::fixup_riscv_12_i;
733 } else if (MIFrm == RISCVII::InstFormatQC_EB) {
734 FixupKind = RISCV::fixup_riscv_qc_e_branch;
735 // Relaxes to QC.E.B<cc>I; JAL, with fixup_riscv_jal
736 AsmRelaxToLinkerRelaxable();
737 } else if (MIFrm == RISCVII::InstFormatQC_EAI) {
738 FixupKind = RISCV::fixup_riscv_qc_e_32;
739 RelaxCandidate = true;
740 } else if (MIFrm == RISCVII::InstFormatQC_EJ) {
741 FixupKind = RISCV::fixup_riscv_qc_e_call_plt;
742 RelaxCandidate = true;
743 } else if (MIFrm == RISCVII::InstFormatNDS_BRANCH_10) {
744 FixupKind = RISCV::fixup_riscv_nds_branch_10;
745 }
746 }
747
748 assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
749
750 addFixup(Fixups, Offset: 0, Value: Expr, Kind: FixupKind);
751 // If linker relaxation is enabled and supported by this relocation, set a bit
752 // so that the assembler knows the size of the instruction is not fixed/known,
753 // and the relocation will need a R_RISCV_RELAX relocation.
754 if (EnableRelax && RelaxCandidate)
755 Fixups.back().setLinkerRelaxable();
756 ++MCNumFixups;
757
758 return 0;
759}
760
761unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
762 SmallVectorImpl<MCFixup> &Fixups,
763 const MCSubtargetInfo &STI) const {
764 MCOperand MO = MI.getOperand(i: OpNo);
765 assert(MO.isReg() && "Expected a register.");
766
767 switch (MO.getReg().id()) {
768 default:
769 llvm_unreachable("Invalid mask register.");
770 case RISCV::V0:
771 return 0;
772 case RISCV::NoRegister:
773 return 1;
774 }
775}
776
777unsigned RISCVMCCodeEmitter::getRlistOpValue(const MCInst &MI, unsigned OpNo,
778 SmallVectorImpl<MCFixup> &Fixups,
779 const MCSubtargetInfo &STI) const {
780 const MCOperand &MO = MI.getOperand(i: OpNo);
781 assert(MO.isImm() && "Rlist operand must be immediate");
782 auto Imm = MO.getImm();
783 assert(Imm >= 4 && "EABI is currently not implemented");
784 return Imm;
785}
786unsigned
787RISCVMCCodeEmitter::getRlistS0OpValue(const MCInst &MI, unsigned OpNo,
788 SmallVectorImpl<MCFixup> &Fixups,
789 const MCSubtargetInfo &STI) const {
790 const MCOperand &MO = MI.getOperand(i: OpNo);
791 assert(MO.isImm() && "Rlist operand must be immediate");
792 auto Imm = MO.getImm();
793 assert(Imm >= 4 && "EABI is currently not implemented");
794 assert(Imm != RISCVZC::RA && "Rlist operand must include s0");
795 return Imm;
796}
797
798#include "RISCVGenMCCodeEmitter.inc"
799