1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Macro Fusion Predicators *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_RISCV_MACRO_FUSION_PRED_DECL
10#undef GET_RISCV_MACRO_FUSION_PRED_DECL
11
12namespace llvm {
13
14bool isTuneADDILoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
15bool isTuneADDLoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
16bool isTuneAUIPCADDIFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
17bool isTuneAUIPCLoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
18bool isTuneBFExtFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
19bool isTuneFusionAddMem(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
20bool isTuneFusionLogicImmReg(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
21bool isTuneFusionLogicRegImm(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
22bool isTuneFusionLogicRegReg(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
23bool isTuneFusionMulAdd(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
24bool isTuneFusionShiftBitExtract(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
25bool isTuneLDADDFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
26bool isTuneLUIADDIFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
27bool isTuneLUILoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
28bool isTuneSHXADDLoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
29bool isTuneShiftedZExtWFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
30bool isTuneZExtHFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
31bool isTuneZExtWFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
32
33} // namespace llvm
34
35#endif // GET_RISCV_MACRO_FUSION_PRED_DECL
36
37
38#ifdef GET_RISCV_MACRO_FUSION_PRED_IMPL
39#undef GET_RISCV_MACRO_FUSION_PRED_IMPL
40
41namespace llvm {
42
43bool isTuneADDILoadFusion(
44 const TargetInstrInfo &TII,
45 const TargetSubtargetInfo &STI,
46 const MachineInstr *FirstMI,
47 const MachineInstr &SecondMI) {
48 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
49 {
50 const MachineInstr *MI = &SecondMI;
51 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
52 return false;
53 }
54 if (!FirstMI)
55 return true;
56 {
57 const MachineInstr *MI = FirstMI;
58 if (( MI->getOpcode() != RISCV::ADDI ))
59 return false;
60 }
61 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
62 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
63 return false;
64 }
65 {
66 Register FirstDest = FirstMI->getOperand(0).getReg();
67 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
68 return false;
69 }
70 if (!(FirstMI->getOperand(0).isReg() &&
71 SecondMI.getOperand(1).isReg() &&
72 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
73 return false;
74 return true;
75}
76bool isTuneADDLoadFusion(
77 const TargetInstrInfo &TII,
78 const TargetSubtargetInfo &STI,
79 const MachineInstr *FirstMI,
80 const MachineInstr &SecondMI) {
81 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
82 {
83 const MachineInstr *MI = &SecondMI;
84 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
85 return false;
86 }
87 if (!FirstMI)
88 return true;
89 {
90 const MachineInstr *MI = FirstMI;
91 if (!llvm::is_contained({RISCV::ADD, RISCV::ADD_UW}, MI->getOpcode()))
92 return false;
93 }
94 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
95 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
96 return false;
97 }
98 {
99 Register FirstDest = FirstMI->getOperand(0).getReg();
100 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
101 return false;
102 }
103 if (!(FirstMI->getOperand(0).isReg() &&
104 SecondMI.getOperand(1).isReg() &&
105 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
106 return false;
107 return true;
108}
109bool isTuneAUIPCADDIFusion(
110 const TargetInstrInfo &TII,
111 const TargetSubtargetInfo &STI,
112 const MachineInstr *FirstMI,
113 const MachineInstr &SecondMI) {
114 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
115 {
116 const MachineInstr *MI = &SecondMI;
117 if (( MI->getOpcode() != RISCV::ADDI ))
118 return false;
119 }
120 if (!FirstMI)
121 return true;
122 {
123 const MachineInstr *MI = FirstMI;
124 if (( MI->getOpcode() != RISCV::AUIPC ))
125 return false;
126 }
127 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
128 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
129 return false;
130 }
131 {
132 Register FirstDest = FirstMI->getOperand(0).getReg();
133 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
134 return false;
135 }
136 if (!(FirstMI->getOperand(0).isReg() &&
137 SecondMI.getOperand(1).isReg() &&
138 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
139 return false;
140 return true;
141}
142bool isTuneAUIPCLoadFusion(
143 const TargetInstrInfo &TII,
144 const TargetSubtargetInfo &STI,
145 const MachineInstr *FirstMI,
146 const MachineInstr &SecondMI) {
147 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
148 {
149 const MachineInstr *MI = &SecondMI;
150 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
151 return false;
152 }
153 if (!FirstMI)
154 return true;
155 {
156 const MachineInstr *MI = FirstMI;
157 if (( MI->getOpcode() != RISCV::AUIPC ))
158 return false;
159 }
160 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
161 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
162 return false;
163 }
164 {
165 Register FirstDest = FirstMI->getOperand(0).getReg();
166 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
167 return false;
168 }
169 if (!(FirstMI->getOperand(0).isReg() &&
170 SecondMI.getOperand(1).isReg() &&
171 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
172 return false;
173 return true;
174}
175bool isTuneBFExtFusion(
176 const TargetInstrInfo &TII,
177 const TargetSubtargetInfo &STI,
178 const MachineInstr *FirstMI,
179 const MachineInstr &SecondMI) {
180 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
181 {
182 const MachineInstr *MI = &SecondMI;
183 if (( MI->getOpcode() != RISCV::SRLI ))
184 return false;
185 }
186 if (!FirstMI)
187 return true;
188 {
189 const MachineInstr *MI = FirstMI;
190 if (( MI->getOpcode() != RISCV::SLLI ))
191 return false;
192 }
193 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
194 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
195 return false;
196 }
197 {
198 Register FirstDest = FirstMI->getOperand(0).getReg();
199 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
200 return false;
201 }
202 if (!(FirstMI->getOperand(0).isReg() &&
203 SecondMI.getOperand(1).isReg() &&
204 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
205 return false;
206 return true;
207}
208bool isTuneFusionAddMem(
209 const TargetInstrInfo &TII,
210 const TargetSubtargetInfo &STI,
211 const MachineInstr *FirstMI,
212 const MachineInstr &SecondMI) {
213 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
214 {
215 const MachineInstr *MI = &SecondMI;
216 if (!(
217 llvm::is_contained({RISCV::LB, RISCV::LBU, RISCV::LH, RISCV::LHU, RISCV::LW, RISCV::LWU, RISCV::LD, RISCV::FLH, RISCV::FLW, RISCV::FLD, RISCV::SB, RISCV::SH, RISCV::SW, RISCV::SD, RISCV::FSH, RISCV::FSW, RISCV::FSD}, MI->getOpcode())
218 && MI->getOperand(2).isImm()
219 && MI->getOperand(2).getImm() == 0
220 ))
221 return false;
222 }
223 if (!FirstMI)
224 return true;
225 {
226 const MachineInstr *MI = FirstMI;
227 if (!(
228 ( MI->getOpcode() == RISCV::ADD )
229 && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()
230 && MI->getOperand(0).getReg() != MI->getOperand(2).getReg()
231 ))
232 return false;
233 }
234 if (!(FirstMI->getOperand(0).isReg() &&
235 SecondMI.getOperand(1).isReg() &&
236 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
237 return false;
238 return true;
239}
240bool isTuneFusionLogicImmReg(
241 const TargetInstrInfo &TII,
242 const TargetSubtargetInfo &STI,
243 const MachineInstr *FirstMI,
244 const MachineInstr &SecondMI) {
245 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
246 {
247 const MachineInstr *MI = &SecondMI;
248 if (!llvm::is_contained({RISCV::AND, RISCV::OR, RISCV::XOR}, MI->getOpcode()))
249 return false;
250 }
251 if (!FirstMI)
252 return true;
253 {
254 const MachineInstr *MI = FirstMI;
255 if (!llvm::is_contained({RISCV::ANDI, RISCV::ORI, RISCV::XORI}, MI->getOpcode()))
256 return false;
257 }
258 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
259 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) {
260 if (!SecondMI.getDesc().isCommutable())
261 return false;
262 unsigned SrcOpIdx1 = 1, SrcOpIdx2 = TargetInstrInfo::CommuteAnyOperandIndex;
263 if (TII.findCommutedOpIndices(SecondMI, SrcOpIdx1, SrcOpIdx2))
264 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(SrcOpIdx2).getReg())
265 return false;
266 }
267 }
268 {
269 Register FirstDest = FirstMI->getOperand(0).getReg();
270 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
271 return false;
272 }
273 if (!(FirstMI->getOperand(0).isReg() &&
274 SecondMI.getOperand(1).isReg() &&
275 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) {
276 if (!SecondMI.getDesc().isCommutable())
277 return false;
278 unsigned SrcOpIdx1 = 1, SrcOpIdx2 = TargetInstrInfo::CommuteAnyOperandIndex;
279 if (TII.findCommutedOpIndices(SecondMI, SrcOpIdx1, SrcOpIdx2))
280 if (FirstMI->getOperand(0).getReg() != SecondMI.getOperand(SrcOpIdx2).getReg())
281 return false;
282 }
283 return true;
284}
285bool isTuneFusionLogicRegImm(
286 const TargetInstrInfo &TII,
287 const TargetSubtargetInfo &STI,
288 const MachineInstr *FirstMI,
289 const MachineInstr &SecondMI) {
290 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
291 {
292 const MachineInstr *MI = &SecondMI;
293 if (!llvm::is_contained({RISCV::ANDI, RISCV::ORI, RISCV::XORI}, MI->getOpcode()))
294 return false;
295 }
296 if (!FirstMI)
297 return true;
298 {
299 const MachineInstr *MI = FirstMI;
300 if (!llvm::is_contained({RISCV::AND, RISCV::OR, RISCV::XOR}, MI->getOpcode()))
301 return false;
302 }
303 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
304 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
305 return false;
306 }
307 {
308 Register FirstDest = FirstMI->getOperand(0).getReg();
309 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
310 return false;
311 }
312 if (!(FirstMI->getOperand(0).isReg() &&
313 SecondMI.getOperand(1).isReg() &&
314 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
315 return false;
316 return true;
317}
318bool isTuneFusionLogicRegReg(
319 const TargetInstrInfo &TII,
320 const TargetSubtargetInfo &STI,
321 const MachineInstr *FirstMI,
322 const MachineInstr &SecondMI) {
323 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
324 {
325 const MachineInstr *MI = &SecondMI;
326 if (!llvm::is_contained({RISCV::AND, RISCV::OR, RISCV::XOR}, MI->getOpcode()))
327 return false;
328 }
329 if (!FirstMI)
330 return true;
331 {
332 const MachineInstr *MI = FirstMI;
333 if (!llvm::is_contained({RISCV::AND, RISCV::OR, RISCV::XOR}, MI->getOpcode()))
334 return false;
335 }
336 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
337 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) {
338 if (!SecondMI.getDesc().isCommutable())
339 return false;
340 unsigned SrcOpIdx1 = 1, SrcOpIdx2 = TargetInstrInfo::CommuteAnyOperandIndex;
341 if (TII.findCommutedOpIndices(SecondMI, SrcOpIdx1, SrcOpIdx2))
342 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(SrcOpIdx2).getReg())
343 return false;
344 }
345 }
346 {
347 Register FirstDest = FirstMI->getOperand(0).getReg();
348 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
349 return false;
350 }
351 if (!(FirstMI->getOperand(0).isReg() &&
352 SecondMI.getOperand(1).isReg() &&
353 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) {
354 if (!SecondMI.getDesc().isCommutable())
355 return false;
356 unsigned SrcOpIdx1 = 1, SrcOpIdx2 = TargetInstrInfo::CommuteAnyOperandIndex;
357 if (TII.findCommutedOpIndices(SecondMI, SrcOpIdx1, SrcOpIdx2))
358 if (FirstMI->getOperand(0).getReg() != SecondMI.getOperand(SrcOpIdx2).getReg())
359 return false;
360 }
361 return true;
362}
363bool isTuneFusionMulAdd(
364 const TargetInstrInfo &TII,
365 const TargetSubtargetInfo &STI,
366 const MachineInstr *FirstMI,
367 const MachineInstr &SecondMI) {
368 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
369 {
370 const MachineInstr *MI = &SecondMI;
371 if (!llvm::is_contained({RISCV::ADD, RISCV::ADDW}, MI->getOpcode()))
372 return false;
373 }
374 if (!FirstMI)
375 return true;
376 {
377 const MachineInstr *MI = FirstMI;
378 if (!llvm::is_contained({RISCV::MUL, RISCV::MULW}, MI->getOpcode()))
379 return false;
380 }
381 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
382 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
383 return false;
384 }
385 {
386 Register FirstDest = FirstMI->getOperand(0).getReg();
387 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
388 return false;
389 }
390 if (!(FirstMI->getOperand(0).isReg() &&
391 SecondMI.getOperand(1).isReg() &&
392 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
393 return false;
394
395 if ((FirstMI->getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask) !=
396 (SecondMI.getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask))
397 return false;
398 {
399 const MachineInstr *MI = &SecondMI;
400 if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg())
401 return false;
402 }
403 return true;
404}
405bool isTuneFusionShiftBitExtract(
406 const TargetInstrInfo &TII,
407 const TargetSubtargetInfo &STI,
408 const MachineInstr *FirstMI,
409 const MachineInstr &SecondMI) {
410 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
411 {
412 const MachineInstr *MI = &SecondMI;
413 if (!llvm::is_contained({RISCV::SRLI, RISCV::SRLIW, RISCV::SRAI, RISCV::SRAIW}, MI->getOpcode()))
414 return false;
415 }
416 if (!FirstMI)
417 return true;
418 {
419 const MachineInstr *MI = FirstMI;
420 if (!llvm::is_contained({RISCV::SLLI, RISCV::SLLIW}, MI->getOpcode()))
421 return false;
422 }
423 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
424 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
425 return false;
426 }
427 {
428 Register FirstDest = FirstMI->getOperand(0).getReg();
429 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
430 return false;
431 }
432 if (!(FirstMI->getOperand(0).isReg() &&
433 SecondMI.getOperand(1).isReg() &&
434 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
435 return false;
436
437 if ((FirstMI->getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask) !=
438 (SecondMI.getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask))
439 return false;
440
441 if (!(FirstMI->getOperand(2).isImm() &&
442 SecondMI.getOperand(2).isImm() &&
443 FirstMI->getOperand(2).getImm() <=
444 SecondMI.getOperand(2).getImm()))
445 return false;
446 return true;
447}
448bool isTuneLDADDFusion(
449 const TargetInstrInfo &TII,
450 const TargetSubtargetInfo &STI,
451 const MachineInstr *FirstMI,
452 const MachineInstr &SecondMI) {
453 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
454 {
455 const MachineInstr *MI = &SecondMI;
456 if (!(
457 ( MI->getOpcode() == RISCV::LD )
458 && MI->getOperand(2).isImm()
459 && MI->getOperand(2).getImm() == 0
460 ))
461 return false;
462 }
463 if (!FirstMI)
464 return true;
465 {
466 const MachineInstr *MI = FirstMI;
467 if (( MI->getOpcode() != RISCV::ADD ))
468 return false;
469 }
470 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
471 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
472 return false;
473 }
474 {
475 Register FirstDest = FirstMI->getOperand(0).getReg();
476 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
477 return false;
478 }
479 if (!(FirstMI->getOperand(0).isReg() &&
480 SecondMI.getOperand(1).isReg() &&
481 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
482 return false;
483 return true;
484}
485bool isTuneLUIADDIFusion(
486 const TargetInstrInfo &TII,
487 const TargetSubtargetInfo &STI,
488 const MachineInstr *FirstMI,
489 const MachineInstr &SecondMI) {
490 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
491 {
492 const MachineInstr *MI = &SecondMI;
493 if (!llvm::is_contained({RISCV::ADDI, RISCV::ADDIW}, MI->getOpcode()))
494 return false;
495 }
496 if (!FirstMI)
497 return true;
498 {
499 const MachineInstr *MI = FirstMI;
500 if (( MI->getOpcode() != RISCV::LUI ))
501 return false;
502 }
503 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
504 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
505 return false;
506 }
507 {
508 Register FirstDest = FirstMI->getOperand(0).getReg();
509 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
510 return false;
511 }
512 if (!(FirstMI->getOperand(0).isReg() &&
513 SecondMI.getOperand(1).isReg() &&
514 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
515 return false;
516 return true;
517}
518bool isTuneLUILoadFusion(
519 const TargetInstrInfo &TII,
520 const TargetSubtargetInfo &STI,
521 const MachineInstr *FirstMI,
522 const MachineInstr &SecondMI) {
523 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
524 {
525 const MachineInstr *MI = &SecondMI;
526 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
527 return false;
528 }
529 if (!FirstMI)
530 return true;
531 {
532 const MachineInstr *MI = FirstMI;
533 if (( MI->getOpcode() != RISCV::LUI ))
534 return false;
535 }
536 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
537 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
538 return false;
539 }
540 {
541 Register FirstDest = FirstMI->getOperand(0).getReg();
542 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
543 return false;
544 }
545 if (!(FirstMI->getOperand(0).isReg() &&
546 SecondMI.getOperand(1).isReg() &&
547 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
548 return false;
549 return true;
550}
551bool isTuneSHXADDLoadFusion(
552 const TargetInstrInfo &TII,
553 const TargetSubtargetInfo &STI,
554 const MachineInstr *FirstMI,
555 const MachineInstr &SecondMI) {
556 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
557 {
558 const MachineInstr *MI = &SecondMI;
559 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
560 return false;
561 }
562 if (!FirstMI)
563 return true;
564 {
565 const MachineInstr *MI = FirstMI;
566 if (!llvm::is_contained({RISCV::SH1ADD, RISCV::SH2ADD, RISCV::SH3ADD, RISCV::SH1ADD_UW, RISCV::SH2ADD_UW, RISCV::SH3ADD_UW}, MI->getOpcode()))
567 return false;
568 }
569 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
570 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
571 return false;
572 }
573 {
574 Register FirstDest = FirstMI->getOperand(0).getReg();
575 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
576 return false;
577 }
578 if (!(FirstMI->getOperand(0).isReg() &&
579 SecondMI.getOperand(1).isReg() &&
580 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
581 return false;
582 return true;
583}
584bool isTuneShiftedZExtWFusion(
585 const TargetInstrInfo &TII,
586 const TargetSubtargetInfo &STI,
587 const MachineInstr *FirstMI,
588 const MachineInstr &SecondMI) {
589 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
590 {
591 const MachineInstr *MI = &SecondMI;
592 if (!(
593 ( MI->getOpcode() == RISCV::SRLI )
594 && MI->getOperand(2).isImm()
595 && (
596 MI->getOperand(2).getImm() >= 0
597 && MI->getOperand(2).getImm() <= 31
598 )
599 ))
600 return false;
601 }
602 if (!FirstMI)
603 return true;
604 {
605 const MachineInstr *MI = FirstMI;
606 if (!(
607 ( MI->getOpcode() == RISCV::SLLI )
608 && MI->getOperand(2).isImm()
609 && MI->getOperand(2).getImm() == 32
610 ))
611 return false;
612 }
613 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
614 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
615 return false;
616 }
617 {
618 Register FirstDest = FirstMI->getOperand(0).getReg();
619 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
620 return false;
621 }
622 if (!(FirstMI->getOperand(0).isReg() &&
623 SecondMI.getOperand(1).isReg() &&
624 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
625 return false;
626 return true;
627}
628bool isTuneZExtHFusion(
629 const TargetInstrInfo &TII,
630 const TargetSubtargetInfo &STI,
631 const MachineInstr *FirstMI,
632 const MachineInstr &SecondMI) {
633 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
634 {
635 const MachineInstr *MI = &SecondMI;
636 if (!(
637 ( MI->getOpcode() == RISCV::SRLI )
638 && MI->getOperand(2).isImm()
639 && MI->getOperand(2).getImm() == 48
640 ))
641 return false;
642 }
643 if (!FirstMI)
644 return true;
645 {
646 const MachineInstr *MI = FirstMI;
647 if (!(
648 ( MI->getOpcode() == RISCV::SLLI )
649 && MI->getOperand(2).isImm()
650 && MI->getOperand(2).getImm() == 48
651 ))
652 return false;
653 }
654 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
655 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
656 return false;
657 }
658 {
659 Register FirstDest = FirstMI->getOperand(0).getReg();
660 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
661 return false;
662 }
663 if (!(FirstMI->getOperand(0).isReg() &&
664 SecondMI.getOperand(1).isReg() &&
665 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
666 return false;
667 return true;
668}
669bool isTuneZExtWFusion(
670 const TargetInstrInfo &TII,
671 const TargetSubtargetInfo &STI,
672 const MachineInstr *FirstMI,
673 const MachineInstr &SecondMI) {
674 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
675 {
676 const MachineInstr *MI = &SecondMI;
677 if (!(
678 ( MI->getOpcode() == RISCV::SRLI )
679 && MI->getOperand(2).isImm()
680 && MI->getOperand(2).getImm() == 32
681 ))
682 return false;
683 }
684 if (!FirstMI)
685 return true;
686 {
687 const MachineInstr *MI = FirstMI;
688 if (!(
689 ( MI->getOpcode() == RISCV::SLLI )
690 && MI->getOperand(2).isImm()
691 && MI->getOperand(2).getImm() == 32
692 ))
693 return false;
694 }
695 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
696 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
697 return false;
698 }
699 {
700 Register FirstDest = FirstMI->getOperand(0).getReg();
701 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
702 return false;
703 }
704 if (!(FirstMI->getOperand(0).isReg() &&
705 SecondMI.getOperand(1).isReg() &&
706 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
707 return false;
708 return true;
709}
710
711} // namespace llvm
712
713#endif // GET_RISCV_MACRO_FUSION_PRED_IMPL
714
715