1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Macro Fusion Predicators *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_RISCV_MACRO_FUSION_PRED_DECL
10#undef GET_RISCV_MACRO_FUSION_PRED_DECL
11
12namespace llvm {
13bool isTuneADDILoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
14bool isTuneADDLoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
15bool isTuneAUIPCADDIFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
16bool isTuneAUIPCLoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
17bool isTuneBFExtFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
18bool isTuneLDADDFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
19bool isTuneLUIADDIFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
20bool isTuneLUILoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
21bool isTuneSHXADDLoadFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
22bool isTuneShiftedZExtWFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
23bool isTuneZExtHFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
24bool isTuneZExtWFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
25} // end namespace llvm
26
27#endif
28
29#ifdef GET_RISCV_MACRO_FUSION_PRED_IMPL
30#undef GET_RISCV_MACRO_FUSION_PRED_IMPL
31
32namespace llvm {
33bool isTuneADDILoadFusion(
34 const TargetInstrInfo &TII,
35 const TargetSubtargetInfo &STI,
36 const MachineInstr *FirstMI,
37 const MachineInstr &SecondMI) {
38 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
39 {
40 const MachineInstr *MI = &SecondMI;
41 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
42 return false;
43 }
44 if (!FirstMI)
45 return true;
46 {
47 const MachineInstr *MI = FirstMI;
48 if (( MI->getOpcode() != RISCV::ADDI ))
49 return false;
50 }
51 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
52 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
53 return false;
54 }
55 {
56 Register FirstDest = FirstMI->getOperand(0).getReg();
57 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
58 return false;
59 }
60 if (!(FirstMI->getOperand(0).isReg() &&
61 SecondMI.getOperand(1).isReg() &&
62 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
63 return false;
64 return true;
65}
66bool isTuneADDLoadFusion(
67 const TargetInstrInfo &TII,
68 const TargetSubtargetInfo &STI,
69 const MachineInstr *FirstMI,
70 const MachineInstr &SecondMI) {
71 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
72 {
73 const MachineInstr *MI = &SecondMI;
74 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
75 return false;
76 }
77 if (!FirstMI)
78 return true;
79 {
80 const MachineInstr *MI = FirstMI;
81 if (!llvm::is_contained({RISCV::ADD, RISCV::ADD_UW}, MI->getOpcode()))
82 return false;
83 }
84 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
85 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
86 return false;
87 }
88 {
89 Register FirstDest = FirstMI->getOperand(0).getReg();
90 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
91 return false;
92 }
93 if (!(FirstMI->getOperand(0).isReg() &&
94 SecondMI.getOperand(1).isReg() &&
95 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
96 return false;
97 return true;
98}
99bool isTuneAUIPCADDIFusion(
100 const TargetInstrInfo &TII,
101 const TargetSubtargetInfo &STI,
102 const MachineInstr *FirstMI,
103 const MachineInstr &SecondMI) {
104 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
105 {
106 const MachineInstr *MI = &SecondMI;
107 if (( MI->getOpcode() != RISCV::ADDI ))
108 return false;
109 }
110 if (!FirstMI)
111 return true;
112 {
113 const MachineInstr *MI = FirstMI;
114 if (( MI->getOpcode() != RISCV::AUIPC ))
115 return false;
116 }
117 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
118 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
119 return false;
120 }
121 {
122 Register FirstDest = FirstMI->getOperand(0).getReg();
123 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
124 return false;
125 }
126 if (!(FirstMI->getOperand(0).isReg() &&
127 SecondMI.getOperand(1).isReg() &&
128 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
129 return false;
130 return true;
131}
132bool isTuneAUIPCLoadFusion(
133 const TargetInstrInfo &TII,
134 const TargetSubtargetInfo &STI,
135 const MachineInstr *FirstMI,
136 const MachineInstr &SecondMI) {
137 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
138 {
139 const MachineInstr *MI = &SecondMI;
140 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
141 return false;
142 }
143 if (!FirstMI)
144 return true;
145 {
146 const MachineInstr *MI = FirstMI;
147 if (( MI->getOpcode() != RISCV::AUIPC ))
148 return false;
149 }
150 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
151 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
152 return false;
153 }
154 {
155 Register FirstDest = FirstMI->getOperand(0).getReg();
156 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
157 return false;
158 }
159 if (!(FirstMI->getOperand(0).isReg() &&
160 SecondMI.getOperand(1).isReg() &&
161 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
162 return false;
163 return true;
164}
165bool isTuneBFExtFusion(
166 const TargetInstrInfo &TII,
167 const TargetSubtargetInfo &STI,
168 const MachineInstr *FirstMI,
169 const MachineInstr &SecondMI) {
170 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
171 {
172 const MachineInstr *MI = &SecondMI;
173 if (( MI->getOpcode() != RISCV::SRLI ))
174 return false;
175 }
176 if (!FirstMI)
177 return true;
178 {
179 const MachineInstr *MI = FirstMI;
180 if (( MI->getOpcode() != RISCV::SLLI ))
181 return false;
182 }
183 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
184 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
185 return false;
186 }
187 {
188 Register FirstDest = FirstMI->getOperand(0).getReg();
189 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
190 return false;
191 }
192 if (!(FirstMI->getOperand(0).isReg() &&
193 SecondMI.getOperand(1).isReg() &&
194 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
195 return false;
196 return true;
197}
198bool isTuneLDADDFusion(
199 const TargetInstrInfo &TII,
200 const TargetSubtargetInfo &STI,
201 const MachineInstr *FirstMI,
202 const MachineInstr &SecondMI) {
203 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
204 {
205 const MachineInstr *MI = &SecondMI;
206 if (!(
207 ( MI->getOpcode() == RISCV::LD )
208 && MI->getOperand(2).isImm()
209 && MI->getOperand(2).getImm() == 0
210 ))
211 return false;
212 }
213 if (!FirstMI)
214 return true;
215 {
216 const MachineInstr *MI = FirstMI;
217 if (( MI->getOpcode() != RISCV::ADD ))
218 return false;
219 }
220 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
221 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
222 return false;
223 }
224 {
225 Register FirstDest = FirstMI->getOperand(0).getReg();
226 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
227 return false;
228 }
229 if (!(FirstMI->getOperand(0).isReg() &&
230 SecondMI.getOperand(1).isReg() &&
231 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
232 return false;
233 return true;
234}
235bool isTuneLUIADDIFusion(
236 const TargetInstrInfo &TII,
237 const TargetSubtargetInfo &STI,
238 const MachineInstr *FirstMI,
239 const MachineInstr &SecondMI) {
240 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
241 {
242 const MachineInstr *MI = &SecondMI;
243 if (!llvm::is_contained({RISCV::ADDI, RISCV::ADDIW}, MI->getOpcode()))
244 return false;
245 }
246 if (!FirstMI)
247 return true;
248 {
249 const MachineInstr *MI = FirstMI;
250 if (( MI->getOpcode() != RISCV::LUI ))
251 return false;
252 }
253 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
254 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
255 return false;
256 }
257 {
258 Register FirstDest = FirstMI->getOperand(0).getReg();
259 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
260 return false;
261 }
262 if (!(FirstMI->getOperand(0).isReg() &&
263 SecondMI.getOperand(1).isReg() &&
264 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
265 return false;
266 return true;
267}
268bool isTuneLUILoadFusion(
269 const TargetInstrInfo &TII,
270 const TargetSubtargetInfo &STI,
271 const MachineInstr *FirstMI,
272 const MachineInstr &SecondMI) {
273 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
274 {
275 const MachineInstr *MI = &SecondMI;
276 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
277 return false;
278 }
279 if (!FirstMI)
280 return true;
281 {
282 const MachineInstr *MI = FirstMI;
283 if (( MI->getOpcode() != RISCV::LUI ))
284 return false;
285 }
286 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
287 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
288 return false;
289 }
290 {
291 Register FirstDest = FirstMI->getOperand(0).getReg();
292 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
293 return false;
294 }
295 if (!(FirstMI->getOperand(0).isReg() &&
296 SecondMI.getOperand(1).isReg() &&
297 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
298 return false;
299 return true;
300}
301bool isTuneSHXADDLoadFusion(
302 const TargetInstrInfo &TII,
303 const TargetSubtargetInfo &STI,
304 const MachineInstr *FirstMI,
305 const MachineInstr &SecondMI) {
306 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
307 {
308 const MachineInstr *MI = &SecondMI;
309 if (!llvm::is_contained({RISCV::LB, RISCV::LH, RISCV::LW, RISCV::LD, RISCV::LBU, RISCV::LHU, RISCV::LWU}, MI->getOpcode()))
310 return false;
311 }
312 if (!FirstMI)
313 return true;
314 {
315 const MachineInstr *MI = FirstMI;
316 if (!llvm::is_contained({RISCV::SH1ADD, RISCV::SH2ADD, RISCV::SH3ADD, RISCV::SH1ADD_UW, RISCV::SH2ADD_UW, RISCV::SH3ADD_UW}, MI->getOpcode()))
317 return false;
318 }
319 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
320 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
321 return false;
322 }
323 {
324 Register FirstDest = FirstMI->getOperand(0).getReg();
325 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
326 return false;
327 }
328 if (!(FirstMI->getOperand(0).isReg() &&
329 SecondMI.getOperand(1).isReg() &&
330 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
331 return false;
332 return true;
333}
334bool isTuneShiftedZExtWFusion(
335 const TargetInstrInfo &TII,
336 const TargetSubtargetInfo &STI,
337 const MachineInstr *FirstMI,
338 const MachineInstr &SecondMI) {
339 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
340 {
341 const MachineInstr *MI = &SecondMI;
342 if (!(
343 ( MI->getOpcode() == RISCV::SRLI )
344 && MI->getOperand(2).isImm()
345 && (
346 MI->getOperand(2).getImm() >= 0
347 && MI->getOperand(2).getImm() <= 31
348 )
349 ))
350 return false;
351 }
352 if (!FirstMI)
353 return true;
354 {
355 const MachineInstr *MI = FirstMI;
356 if (!(
357 ( MI->getOpcode() == RISCV::SLLI )
358 && MI->getOperand(2).isImm()
359 && MI->getOperand(2).getImm() == 32
360 ))
361 return false;
362 }
363 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
364 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
365 return false;
366 }
367 {
368 Register FirstDest = FirstMI->getOperand(0).getReg();
369 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
370 return false;
371 }
372 if (!(FirstMI->getOperand(0).isReg() &&
373 SecondMI.getOperand(1).isReg() &&
374 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
375 return false;
376 return true;
377}
378bool isTuneZExtHFusion(
379 const TargetInstrInfo &TII,
380 const TargetSubtargetInfo &STI,
381 const MachineInstr *FirstMI,
382 const MachineInstr &SecondMI) {
383 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
384 {
385 const MachineInstr *MI = &SecondMI;
386 if (!(
387 ( MI->getOpcode() == RISCV::SRLI )
388 && MI->getOperand(2).isImm()
389 && MI->getOperand(2).getImm() == 48
390 ))
391 return false;
392 }
393 if (!FirstMI)
394 return true;
395 {
396 const MachineInstr *MI = FirstMI;
397 if (!(
398 ( MI->getOpcode() == RISCV::SLLI )
399 && MI->getOperand(2).isImm()
400 && MI->getOperand(2).getImm() == 48
401 ))
402 return false;
403 }
404 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
405 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
406 return false;
407 }
408 {
409 Register FirstDest = FirstMI->getOperand(0).getReg();
410 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
411 return false;
412 }
413 if (!(FirstMI->getOperand(0).isReg() &&
414 SecondMI.getOperand(1).isReg() &&
415 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
416 return false;
417 return true;
418}
419bool isTuneZExtWFusion(
420 const TargetInstrInfo &TII,
421 const TargetSubtargetInfo &STI,
422 const MachineInstr *FirstMI,
423 const MachineInstr &SecondMI) {
424 [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo();
425 {
426 const MachineInstr *MI = &SecondMI;
427 if (!(
428 ( MI->getOpcode() == RISCV::SRLI )
429 && MI->getOperand(2).isImm()
430 && MI->getOperand(2).getImm() == 32
431 ))
432 return false;
433 }
434 if (!FirstMI)
435 return true;
436 {
437 const MachineInstr *MI = FirstMI;
438 if (!(
439 ( MI->getOpcode() == RISCV::SLLI )
440 && MI->getOperand(2).isImm()
441 && MI->getOperand(2).getImm() == 32
442 ))
443 return false;
444 }
445 if (!SecondMI.getOperand(0).getReg().isVirtual()) {
446 if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
447 return false;
448 }
449 {
450 Register FirstDest = FirstMI->getOperand(0).getReg();
451 if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
452 return false;
453 }
454 if (!(FirstMI->getOperand(0).isReg() &&
455 SecondMI.getOperand(1).isReg() &&
456 FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
457 return false;
458 return true;
459}
460} // end namespace llvm
461
462#endif
463