1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::RISCV {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 FPRBRegBankID = 0,
17 GPRBRegBankID = 1,
18 VRBRegBankID = 2,
19 NumRegisterBanks,
20};
21
22} // namespace llvm::RISCV
23
24#endif // GET_REGBANK_DECLARATIONS
25
26#ifdef GET_TARGET_REGBANK_CLASS
27#undef GET_TARGET_REGBANK_CLASS
28
29private:
30 static const RegisterBank *RegBanks[];
31 static const unsigned Sizes[];
32
33public:
34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
35protected:
36 RISCVGenRegisterBankInfo(unsigned HwMode = 0);
37
38
39#endif // GET_TARGET_REGBANK_CLASS
40
41#ifdef GET_TARGET_REGBANK_IMPL
42#undef GET_TARGET_REGBANK_IMPL
43
44namespace llvm {
45
46namespace RISCV {
47
48const uint32_t FPRBRegBankCoverageData[] = {
49 // 0-31
50 (1u << (RISCV::FPR16RegClassID - 0)) |
51 (1u << (RISCV::FPR32RegClassID - 0)) |
52 (1u << (RISCV::FPR16CRegClassID - 0)) |
53 (1u << (RISCV::FPR32CRegClassID - 0)) |
54 0,
55 // 32-63
56 0,
57 // 64-95
58 (1u << (RISCV::FPR64RegClassID - 64)) |
59 (1u << (RISCV::FPR64CRegClassID - 64)) |
60 0,
61 // 96-127
62 0,
63 // 128-159
64 0,
65};
66const uint32_t GPRBRegBankCoverageData[] = {
67 // 0-31
68 (1u << (RISCV::GPRRegClassID - 0)) |
69 (1u << (RISCV::GPRF16RegClassID - 0)) |
70 (1u << (RISCV::GPRF32RegClassID - 0)) |
71 (1u << (RISCV::GPRNoX0RegClassID - 0)) |
72 (1u << (RISCV::GPRF16NoX0RegClassID - 0)) |
73 (1u << (RISCV::GPRF32NoX0RegClassID - 0)) |
74 (1u << (RISCV::GPRNoX0X2RegClassID - 0)) |
75 (1u << (RISCV::GPRNoX0X2_and_GPRNoX31RegClassID - 0)) |
76 (1u << (RISCV::GPRJALR_and_GPRNoX31RegClassID - 0)) |
77 (1u << (RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID - 0)) |
78 (1u << (RISCV::GPRNoX31_and_GPRTCNonX7RegClassID - 0)) |
79 (1u << (RISCV::GPRF16CRegClassID - 0)) |
80 (1u << (RISCV::GPRF32CRegClassID - 0)) |
81 (1u << (RISCV::GPRCRegClassID - 0)) |
82 (1u << (RISCV::SR07RegClassID - 0)) |
83 (1u << (RISCV::GPRNoX31_and_GPRTCRegClassID - 0)) |
84 (1u << (RISCV::GPRJALRRegClassID - 0)) |
85 (1u << (RISCV::GPRJALRNonX7RegClassID - 0)) |
86 (1u << (RISCV::GPRTCNonX7RegClassID - 0)) |
87 (1u << (RISCV::GPRTCRegClassID - 0)) |
88 (1u << (RISCV::GPRNoX0_and_GPRNoX31RegClassID - 0)) |
89 (1u << (RISCV::GPRNoX2RegClassID - 0)) |
90 (1u << (RISCV::GPRNoX2_and_GPRNoX31RegClassID - 0)) |
91 (1u << (RISCV::GPRNoX31RegClassID - 0)) |
92 0,
93 // 32-63
94 (1u << (RISCV::GPRC_and_GPRTCRegClassID - 32)) |
95 (1u << (RISCV::GPRC_and_SR07RegClassID - 32)) |
96 (1u << (RISCV::GPRX7RegClassID - 32)) |
97 (1u << (RISCV::GPRX1X5RegClassID - 32)) |
98 (1u << (RISCV::GPRX1RegClassID - 32)) |
99 (1u << (RISCV::GPRX5RegClassID - 32)) |
100 (1u << (RISCV::SPRegClassID - 32)) |
101 (1u << (RISCV::GPRX0RegClassID - 32)) |
102 0,
103 // 64-95
104 0,
105 // 96-127
106 0,
107 // 128-159
108 0,
109};
110const uint32_t VRBRegBankCoverageData[] = {
111 // 0-31
112 0,
113 // 32-63
114 0,
115 // 64-95
116 (1u << (RISCV::VRRegClassID - 64)) |
117 (1u << (RISCV::ZZZ_VMRegClassID - 64)) |
118 (1u << (RISCV::ZZZ_VRMF2RegClassID - 64)) |
119 (1u << (RISCV::ZZZ_VRMF4RegClassID - 64)) |
120 (1u << (RISCV::ZZZ_VRMF8RegClassID - 64)) |
121 (1u << (RISCV::VRNoV0RegClassID - 64)) |
122 (1u << (RISCV::ZZZ_VMNoV0RegClassID - 64)) |
123 (1u << (RISCV::ZZZ_VRMF2NoV0RegClassID - 64)) |
124 (1u << (RISCV::ZZZ_VRMF4NoV0RegClassID - 64)) |
125 (1u << (RISCV::ZZZ_VRMF8NoV0RegClassID - 64)) |
126 0,
127 // 96-127
128 (1u << (RISCV::VRM2RegClassID - 96)) |
129 (1u << (RISCV::VRM2NoV0RegClassID - 96)) |
130 (1u << (RISCV::VRM4RegClassID - 96)) |
131 (1u << (RISCV::VRM4NoV0RegClassID - 96)) |
132 (1u << (RISCV::VMV0RegClassID - 96)) |
133 (1u << (RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID - 96)) |
134 (1u << (RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 96)) |
135 0,
136 // 128-159
137 (1u << (RISCV::VRM8RegClassID - 128)) |
138 (1u << (RISCV::VRM8NoV0RegClassID - 128)) |
139 (1u << (RISCV::VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 128)) |
140 0,
141};
142
143constexpr RegisterBank FPRBRegBank(/* ID */ RISCV::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 151);
144constexpr RegisterBank GPRBRegBank(/* ID */ RISCV::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 151);
145constexpr RegisterBank VRBRegBank(/* ID */ RISCV::VRBRegBankID, /* Name */ "VRB", /* CoveredRegClasses */ VRBRegBankCoverageData, /* NumRegClasses */ 151);
146
147} // namespace RISCV
148
149const RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = {
150 &RISCV::FPRBRegBank,
151 &RISCV::GPRBRegBank,
152 &RISCV::VRBRegBank,
153};
154
155const unsigned RISCVGenRegisterBankInfo::Sizes[] = {
156 // Mode = 0 (Default)
157 64,
158 32,
159 512,
160 // Mode = 1 (RV64)
161 64,
162 64,
163 512,
164};
165
166RISCVGenRegisterBankInfo::RISCVGenRegisterBankInfo(unsigned HwMode)
167 : RegisterBankInfo(RegBanks, RISCV::NumRegisterBanks, Sizes, HwMode) {
168 // Assert that RegBank indices match their ID's
169#ifndef NDEBUG
170 for (auto RB : enumerate(RegBanks))
171 assert(RB.index() == RB.value()->getID() && "Index != ID");
172#endif // NDEBUG
173}
174
175const RegisterBank &
176RISCVGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
177 constexpr uint32_t InvalidRegBankID = uint32_t(RISCV::InvalidRegBankID) & 3;
178 static const uint32_t RegClass2RegBank[10] = {
179 (uint32_t(InvalidRegBankID) << 0) |
180 (uint32_t(InvalidRegBankID) << 2) |
181 (uint32_t(RISCV::FPRBRegBankID) << 4) | // FPR16RegClassID
182 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRF16RegClassID
183 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRF16NoX0RegClassID
184 (uint32_t(RISCV::FPRBRegBankID) << 10) | // FPR16CRegClassID
185 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRF16CRegClassID
186 (uint32_t(InvalidRegBankID) << 14) |
187 (uint32_t(RISCV::FPRBRegBankID) << 16) | // FPR32RegClassID
188 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRRegClassID
189 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRF32RegClassID
190 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRF32NoX0RegClassID
191 (uint32_t(RISCV::GPRBRegBankID) << 24) | // GPRNoX0RegClassID
192 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRNoX2RegClassID
193 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRNoX31RegClassID
194 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRNoX0X2RegClassID
195 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRNoX0_and_GPRNoX31RegClassID
196 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRNoX2_and_GPRNoX31RegClassID
197 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRNoX0X2_and_GPRNoX31RegClassID
198 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRJALRRegClassID
199 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRJALRNonX7RegClassID
200 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRJALR_and_GPRNoX31RegClassID
201 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRJALRNonX7_and_GPRNoX31RegClassID
202 (uint32_t(InvalidRegBankID) << 14) |
203 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRTCRegClassID
204 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRNoX31_and_GPRTCRegClassID
205 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRTCNonX7RegClassID
206 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRNoX31_and_GPRTCNonX7RegClassID
207 (uint32_t(RISCV::FPRBRegBankID) << 24) | // FPR32CRegClassID
208 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRCRegClassID
209 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRF32CRegClassID
210 (uint32_t(RISCV::GPRBRegBankID) << 30), // SR07RegClassID
211 (uint32_t(InvalidRegBankID) << 0) |
212 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRC_and_GPRTCRegClassID
213 (uint32_t(InvalidRegBankID) << 4) |
214 (uint32_t(InvalidRegBankID) << 6) |
215 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRC_and_SR07RegClassID
216 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRX1X5RegClassID
217 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRX0RegClassID
218 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRX1RegClassID
219 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRX5RegClassID
220 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRX7RegClassID
221 (uint32_t(RISCV::GPRBRegBankID) << 20) | // SPRegClassID
222 (uint32_t(InvalidRegBankID) << 22) |
223 (uint32_t(InvalidRegBankID) << 24) |
224 (uint32_t(InvalidRegBankID) << 26) |
225 (uint32_t(InvalidRegBankID) << 28) |
226 (uint32_t(InvalidRegBankID) << 30),
227 (uint32_t(InvalidRegBankID) << 0) |
228 (uint32_t(InvalidRegBankID) << 2) |
229 (uint32_t(InvalidRegBankID) << 4) |
230 (uint32_t(InvalidRegBankID) << 6) |
231 (uint32_t(InvalidRegBankID) << 8) |
232 (uint32_t(InvalidRegBankID) << 10) |
233 (uint32_t(InvalidRegBankID) << 12) |
234 (uint32_t(InvalidRegBankID) << 14) |
235 (uint32_t(InvalidRegBankID) << 16) |
236 (uint32_t(InvalidRegBankID) << 18) |
237 (uint32_t(InvalidRegBankID) << 20) |
238 (uint32_t(InvalidRegBankID) << 22) |
239 (uint32_t(InvalidRegBankID) << 24) |
240 (uint32_t(InvalidRegBankID) << 26) |
241 (uint32_t(InvalidRegBankID) << 28) |
242 (uint32_t(InvalidRegBankID) << 30),
243 (uint32_t(InvalidRegBankID) << 0) |
244 (uint32_t(InvalidRegBankID) << 2) |
245 (uint32_t(RISCV::FPRBRegBankID) << 4) | // FPR64RegClassID
246 (uint32_t(RISCV::VRBRegBankID) << 6) | // VRRegClassID
247 (uint32_t(InvalidRegBankID) << 8) |
248 (uint32_t(RISCV::VRBRegBankID) << 10) | // ZZZ_VMRegClassID
249 (uint32_t(RISCV::VRBRegBankID) << 12) | // ZZZ_VRMF2RegClassID
250 (uint32_t(RISCV::VRBRegBankID) << 14) | // ZZZ_VRMF4RegClassID
251 (uint32_t(RISCV::VRBRegBankID) << 16) | // ZZZ_VRMF8RegClassID
252 (uint32_t(RISCV::VRBRegBankID) << 18) | // VRNoV0RegClassID
253 (uint32_t(InvalidRegBankID) << 20) |
254 (uint32_t(InvalidRegBankID) << 22) |
255 (uint32_t(InvalidRegBankID) << 24) |
256 (uint32_t(RISCV::VRBRegBankID) << 26) | // ZZZ_VMNoV0RegClassID
257 (uint32_t(RISCV::VRBRegBankID) << 28) | // ZZZ_VRMF2NoV0RegClassID
258 (uint32_t(RISCV::VRBRegBankID) << 30), // ZZZ_VRMF4NoV0RegClassID
259 (uint32_t(RISCV::VRBRegBankID) << 0) | // ZZZ_VRMF8NoV0RegClassID
260 (uint32_t(InvalidRegBankID) << 2) |
261 (uint32_t(InvalidRegBankID) << 4) |
262 (uint32_t(InvalidRegBankID) << 6) |
263 (uint32_t(InvalidRegBankID) << 8) |
264 (uint32_t(InvalidRegBankID) << 10) |
265 (uint32_t(InvalidRegBankID) << 12) |
266 (uint32_t(InvalidRegBankID) << 14) |
267 (uint32_t(InvalidRegBankID) << 16) |
268 (uint32_t(InvalidRegBankID) << 18) |
269 (uint32_t(InvalidRegBankID) << 20) |
270 (uint32_t(InvalidRegBankID) << 22) |
271 (uint32_t(InvalidRegBankID) << 24) |
272 (uint32_t(RISCV::FPRBRegBankID) << 26) | // FPR64CRegClassID
273 (uint32_t(InvalidRegBankID) << 28) |
274 (uint32_t(InvalidRegBankID) << 30),
275 (uint32_t(InvalidRegBankID) << 0) |
276 (uint32_t(InvalidRegBankID) << 2) |
277 (uint32_t(InvalidRegBankID) << 4) |
278 (uint32_t(RISCV::VRBRegBankID) << 6) | // VMV0RegClassID
279 (uint32_t(InvalidRegBankID) << 8) |
280 (uint32_t(InvalidRegBankID) << 10) |
281 (uint32_t(InvalidRegBankID) << 12) |
282 (uint32_t(InvalidRegBankID) << 14) |
283 (uint32_t(InvalidRegBankID) << 16) |
284 (uint32_t(InvalidRegBankID) << 18) |
285 (uint32_t(InvalidRegBankID) << 20) |
286 (uint32_t(RISCV::VRBRegBankID) << 22) | // VRM2RegClassID
287 (uint32_t(RISCV::VRBRegBankID) << 24) | // VRM2NoV0RegClassID
288 (uint32_t(RISCV::VRBRegBankID) << 26) | // VRM2_with_sub_vrm1_0_in_VMV0RegClassID
289 (uint32_t(InvalidRegBankID) << 28) |
290 (uint32_t(InvalidRegBankID) << 30),
291 (uint32_t(InvalidRegBankID) << 0) |
292 (uint32_t(InvalidRegBankID) << 2) |
293 (uint32_t(InvalidRegBankID) << 4) |
294 (uint32_t(InvalidRegBankID) << 6) |
295 (uint32_t(InvalidRegBankID) << 8) |
296 (uint32_t(InvalidRegBankID) << 10) |
297 (uint32_t(InvalidRegBankID) << 12) |
298 (uint32_t(InvalidRegBankID) << 14) |
299 (uint32_t(RISCV::VRBRegBankID) << 16) | // VRM4RegClassID
300 (uint32_t(RISCV::VRBRegBankID) << 18) | // VRM4NoV0RegClassID
301 (uint32_t(RISCV::VRBRegBankID) << 20) | // VRM4_with_sub_vrm1_0_in_VMV0RegClassID
302 (uint32_t(InvalidRegBankID) << 22) |
303 (uint32_t(InvalidRegBankID) << 24) |
304 (uint32_t(InvalidRegBankID) << 26) |
305 (uint32_t(InvalidRegBankID) << 28) |
306 (uint32_t(InvalidRegBankID) << 30),
307 (uint32_t(InvalidRegBankID) << 0) |
308 (uint32_t(InvalidRegBankID) << 2) |
309 (uint32_t(InvalidRegBankID) << 4) |
310 (uint32_t(InvalidRegBankID) << 6) |
311 (uint32_t(InvalidRegBankID) << 8) |
312 (uint32_t(InvalidRegBankID) << 10) |
313 (uint32_t(InvalidRegBankID) << 12) |
314 (uint32_t(InvalidRegBankID) << 14) |
315 (uint32_t(InvalidRegBankID) << 16) |
316 (uint32_t(InvalidRegBankID) << 18) |
317 (uint32_t(InvalidRegBankID) << 20) |
318 (uint32_t(InvalidRegBankID) << 22) |
319 (uint32_t(InvalidRegBankID) << 24) |
320 (uint32_t(InvalidRegBankID) << 26) |
321 (uint32_t(InvalidRegBankID) << 28) |
322 (uint32_t(InvalidRegBankID) << 30),
323 (uint32_t(InvalidRegBankID) << 0) |
324 (uint32_t(RISCV::VRBRegBankID) << 2) | // VRM8RegClassID
325 (uint32_t(RISCV::VRBRegBankID) << 4) | // VRM8NoV0RegClassID
326 (uint32_t(RISCV::VRBRegBankID) << 6) // VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID
327 };
328 const unsigned RegClassID = RC.getID();
329 if (LLVM_LIKELY(RegClassID < 148)) {
330 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
331 if (RegBankID != InvalidRegBankID)
332 return getRegBank(RegBankID);
333 }
334 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
335}
336
337} // namespace llvm
338
339#endif // GET_TARGET_REGBANK_IMPL
340
341