1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::RISCV {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 FPRBRegBankID = 0,
17 GPRBRegBankID = 1,
18 VRBRegBankID = 2,
19 NumRegisterBanks,
20};
21
22} // namespace llvm::RISCV
23
24#endif // GET_REGBANK_DECLARATIONS
25
26#ifdef GET_TARGET_REGBANK_CLASS
27#undef GET_TARGET_REGBANK_CLASS
28
29private:
30 static const RegisterBank *RegBanks[];
31 static const unsigned Sizes[];
32
33public:
34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
35protected:
36 RISCVGenRegisterBankInfo(unsigned HwMode = 0);
37
38
39#endif // GET_TARGET_REGBANK_CLASS
40
41#ifdef GET_TARGET_REGBANK_IMPL
42#undef GET_TARGET_REGBANK_IMPL
43
44namespace llvm {
45
46namespace RISCV {
47
48const uint32_t FPRBRegBankCoverageData[] = {
49 // 0-31
50 (1u << (RISCV::FPR16RegClassID - 0)) |
51 (1u << (RISCV::FPR32RegClassID - 0)) |
52 (1u << (RISCV::FPR16CRegClassID - 0)) |
53 (1u << (RISCV::FPR32CRegClassID - 0)) |
54 0,
55 // 32-63
56 0,
57 // 64-95
58 (1u << (RISCV::FPR64RegClassID - 64)) |
59 (1u << (RISCV::FPR64CRegClassID - 64)) |
60 0,
61 // 96-127
62 0,
63 // 128-159
64 0,
65};
66const uint32_t GPRBRegBankCoverageData[] = {
67 // 0-31
68 (1u << (RISCV::GPRRegClassID - 0)) |
69 (1u << (RISCV::GPRF16RegClassID - 0)) |
70 (1u << (RISCV::GPRF32RegClassID - 0)) |
71 (1u << (RISCV::GPRNoX0RegClassID - 0)) |
72 (1u << (RISCV::GPRF16NoX0RegClassID - 0)) |
73 (1u << (RISCV::GPRF32NoX0RegClassID - 0)) |
74 (1u << (RISCV::GPRNoX0X2RegClassID - 0)) |
75 (1u << (RISCV::GPRNoX0X2_and_GPRNoX31RegClassID - 0)) |
76 (1u << (RISCV::GPRJALR_and_GPRNoX31RegClassID - 0)) |
77 (1u << (RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID - 0)) |
78 (1u << (RISCV::GPRNoX31_and_GPRTCNonX7RegClassID - 0)) |
79 (1u << (RISCV::GPRF16CRegClassID - 0)) |
80 (1u << (RISCV::GPRF32CRegClassID - 0)) |
81 (1u << (RISCV::GPRCRegClassID - 0)) |
82 (1u << (RISCV::GPRNoX31_and_GPRTCRegClassID - 0)) |
83 (1u << (RISCV::GPRJALRRegClassID - 0)) |
84 (1u << (RISCV::GPRJALRNonX7RegClassID - 0)) |
85 (1u << (RISCV::GPRTCNonX7RegClassID - 0)) |
86 (1u << (RISCV::GPRTCRegClassID - 0)) |
87 (1u << (RISCV::GPRNoX0_and_GPRNoX31RegClassID - 0)) |
88 (1u << (RISCV::GPRNoX2RegClassID - 0)) |
89 (1u << (RISCV::GPRNoX2_and_GPRNoX31RegClassID - 0)) |
90 (1u << (RISCV::GPRF16X0RegClassID - 0)) |
91 (1u << (RISCV::GPRNoX31RegClassID - 0)) |
92 (1u << (RISCV::GPRAllRegClassID - 0)) |
93 0,
94 // 32-63
95 (1u << (RISCV::GPRC_and_GPRTCRegClassID - 32)) |
96 (1u << (RISCV::GPRC_and_SR07RegClassID - 32)) |
97 (1u << (RISCV::SR07RegClassID - 32)) |
98 (1u << (RISCV::GPRX7RegClassID - 32)) |
99 (1u << (RISCV::GPRX1X5RegClassID - 32)) |
100 (1u << (RISCV::GPRX1RegClassID - 32)) |
101 (1u << (RISCV::GPRX5RegClassID - 32)) |
102 (1u << (RISCV::SPRegClassID - 32)) |
103 (1u << (RISCV::GPRX0RegClassID - 32)) |
104 (1u << (RISCV::GPRF32X0RegClassID - 32)) |
105 (1u << (RISCV::GPRPairRegClassID - 32)) |
106 (1u << (RISCV::GPRPairNoX0RegClassID - 32)) |
107 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID - 32)) |
108 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID - 32)) |
109 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID - 32)) |
110 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID - 32)) |
111 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7RegClassID - 32)) |
112 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID - 32)) |
113 (1u << (RISCV::GPRPairCRegClassID - 32)) |
114 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_SR07RegClassID - 32)) |
115 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRTCNonX7RegClassID - 32)) |
116 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID - 32)) |
117 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID - 32)) |
118 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID - 32)) |
119 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID - 32)) |
120 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID - 32)) |
121 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID - 32)) |
122 (1u << (RISCV::GPRPair_with_sub_16_in_GPRF16X0RegClassID - 32)) |
123 0,
124 // 64-95
125 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClassID - 64)) |
126 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRX7RegClassID - 64)) |
127 (1u << (RISCV::GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClassID - 64)) |
128 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_SPRegClassID - 64)) |
129 0,
130 // 96-127
131 0,
132 // 128-159
133 0,
134};
135const uint32_t VRBRegBankCoverageData[] = {
136 // 0-31
137 0,
138 // 32-63
139 0,
140 // 64-95
141 (1u << (RISCV::VRRegClassID - 64)) |
142 (1u << (RISCV::ZZZ_VMRegClassID - 64)) |
143 (1u << (RISCV::ZZZ_VRMF2RegClassID - 64)) |
144 (1u << (RISCV::ZZZ_VRMF4RegClassID - 64)) |
145 (1u << (RISCV::ZZZ_VRMF8RegClassID - 64)) |
146 (1u << (RISCV::VRNoV0RegClassID - 64)) |
147 (1u << (RISCV::ZZZ_VMNoV0RegClassID - 64)) |
148 (1u << (RISCV::ZZZ_VRMF2NoV0RegClassID - 64)) |
149 (1u << (RISCV::ZZZ_VRMF4NoV0RegClassID - 64)) |
150 (1u << (RISCV::ZZZ_VRMF8NoV0RegClassID - 64)) |
151 0,
152 // 96-127
153 (1u << (RISCV::VRM2RegClassID - 96)) |
154 (1u << (RISCV::VRM2NoV0RegClassID - 96)) |
155 (1u << (RISCV::VRM4RegClassID - 96)) |
156 (1u << (RISCV::VRM4NoV0RegClassID - 96)) |
157 (1u << (RISCV::VMV0RegClassID - 96)) |
158 (1u << (RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID - 96)) |
159 (1u << (RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 96)) |
160 0,
161 // 128-159
162 (1u << (RISCV::VRM8RegClassID - 128)) |
163 (1u << (RISCV::VRM8NoV0RegClassID - 128)) |
164 (1u << (RISCV::VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 128)) |
165 0,
166};
167
168constexpr RegisterBank FPRBRegBank(/* ID */ RISCV::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 153);
169constexpr RegisterBank GPRBRegBank(/* ID */ RISCV::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 153);
170constexpr RegisterBank VRBRegBank(/* ID */ RISCV::VRBRegBankID, /* Name */ "VRB", /* CoveredRegClasses */ VRBRegBankCoverageData, /* NumRegClasses */ 153);
171
172} // namespace RISCV
173
174const RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = {
175 &RISCV::FPRBRegBank,
176 &RISCV::GPRBRegBank,
177 &RISCV::VRBRegBank,
178};
179
180const unsigned RISCVGenRegisterBankInfo::Sizes[] = {
181 // Mode = 0 (DefaultMode)
182 64,
183 64,
184 512,
185 // Mode = 1 (RV64)
186 64,
187 128,
188 512,
189};
190
191RISCVGenRegisterBankInfo::RISCVGenRegisterBankInfo(unsigned HwMode)
192 : RegisterBankInfo(RegBanks, RISCV::NumRegisterBanks, Sizes, HwMode) {
193 // Assert that RegBank indices match their ID's
194#ifndef NDEBUG
195 for (auto RB : enumerate(RegBanks))
196 assert(RB.index() == RB.value()->getID() && "Index != ID");
197#endif // NDEBUG
198}
199
200const RegisterBank &
201RISCVGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
202 constexpr uint32_t InvalidRegBankID = uint32_t(RISCV::InvalidRegBankID) & 3;
203 static const uint32_t RegClass2RegBank[10] = {
204 (uint32_t(InvalidRegBankID) << 0) |
205 (uint32_t(InvalidRegBankID) << 2) |
206 (uint32_t(RISCV::FPRBRegBankID) << 4) | // FPR16RegClassID
207 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRF16RegClassID
208 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRF16NoX0RegClassID
209 (uint32_t(RISCV::FPRBRegBankID) << 10) | // FPR16CRegClassID
210 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRF16CRegClassID
211 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRF16X0RegClassID
212 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRAllRegClassID
213 (uint32_t(RISCV::FPRBRegBankID) << 18) | // FPR32RegClassID
214 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRRegClassID
215 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRF32RegClassID
216 (uint32_t(RISCV::GPRBRegBankID) << 24) | // GPRF32NoX0RegClassID
217 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRNoX0RegClassID
218 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRNoX2RegClassID
219 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRNoX31RegClassID
220 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRNoX0X2RegClassID
221 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRNoX0_and_GPRNoX31RegClassID
222 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRNoX2_and_GPRNoX31RegClassID
223 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRNoX0X2_and_GPRNoX31RegClassID
224 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRJALRRegClassID
225 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRJALRNonX7RegClassID
226 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRJALR_and_GPRNoX31RegClassID
227 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRJALRNonX7_and_GPRNoX31RegClassID
228 (uint32_t(InvalidRegBankID) << 16) |
229 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRTCRegClassID
230 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRNoX31_and_GPRTCRegClassID
231 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRTCNonX7RegClassID
232 (uint32_t(RISCV::GPRBRegBankID) << 24) | // GPRNoX31_and_GPRTCNonX7RegClassID
233 (uint32_t(RISCV::FPRBRegBankID) << 26) | // FPR32CRegClassID
234 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRCRegClassID
235 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRF32CRegClassID
236 (uint32_t(RISCV::GPRBRegBankID) << 0) | // SR07RegClassID
237 (uint32_t(InvalidRegBankID) << 2) |
238 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRC_and_GPRTCRegClassID
239 (uint32_t(InvalidRegBankID) << 6) |
240 (uint32_t(InvalidRegBankID) << 8) |
241 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRC_and_SR07RegClassID
242 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRX1X5RegClassID
243 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRF32X0RegClassID
244 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRX0RegClassID
245 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRX1RegClassID
246 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRX5RegClassID
247 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRX7RegClassID
248 (uint32_t(RISCV::GPRBRegBankID) << 24) | // SPRegClassID
249 (uint32_t(InvalidRegBankID) << 26) |
250 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRPairRegClassID
251 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRPairNoX0RegClassID
252 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID
253 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID
254 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID
255 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID
256 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID
257 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID
258 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID
259 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID
260 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRPair_with_sub_gpr_even_in_GPRTCRegClassID
261 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID
262 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRPair_with_sub_gpr_odd_in_GPRTCNonX7RegClassID
263 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7RegClassID
264 (uint32_t(RISCV::GPRBRegBankID) << 24) | // GPRPairCRegClassID
265 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRPair_with_sub_gpr_even_in_SR07RegClassID
266 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID
267 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRPair_with_sub_16_in_GPRF16X0RegClassID
268 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClassID
269 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRPair_with_sub_gpr_even_in_SPRegClassID
270 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClassID
271 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRPair_with_sub_gpr_odd_in_GPRX7RegClassID
272 (uint32_t(RISCV::FPRBRegBankID) << 8) | // FPR64RegClassID
273 (uint32_t(RISCV::VRBRegBankID) << 10) | // VRRegClassID
274 (uint32_t(InvalidRegBankID) << 12) |
275 (uint32_t(RISCV::VRBRegBankID) << 14) | // ZZZ_VMRegClassID
276 (uint32_t(RISCV::VRBRegBankID) << 16) | // ZZZ_VRMF2RegClassID
277 (uint32_t(RISCV::VRBRegBankID) << 18) | // ZZZ_VRMF4RegClassID
278 (uint32_t(RISCV::VRBRegBankID) << 20) | // ZZZ_VRMF8RegClassID
279 (uint32_t(RISCV::VRBRegBankID) << 22) | // VRNoV0RegClassID
280 (uint32_t(InvalidRegBankID) << 24) |
281 (uint32_t(InvalidRegBankID) << 26) |
282 (uint32_t(InvalidRegBankID) << 28) |
283 (uint32_t(RISCV::VRBRegBankID) << 30), // ZZZ_VMNoV0RegClassID
284 (uint32_t(RISCV::VRBRegBankID) << 0) | // ZZZ_VRMF2NoV0RegClassID
285 (uint32_t(RISCV::VRBRegBankID) << 2) | // ZZZ_VRMF4NoV0RegClassID
286 (uint32_t(RISCV::VRBRegBankID) << 4) | // ZZZ_VRMF8NoV0RegClassID
287 (uint32_t(InvalidRegBankID) << 6) |
288 (uint32_t(InvalidRegBankID) << 8) |
289 (uint32_t(InvalidRegBankID) << 10) |
290 (uint32_t(InvalidRegBankID) << 12) |
291 (uint32_t(InvalidRegBankID) << 14) |
292 (uint32_t(InvalidRegBankID) << 16) |
293 (uint32_t(InvalidRegBankID) << 18) |
294 (uint32_t(InvalidRegBankID) << 20) |
295 (uint32_t(InvalidRegBankID) << 22) |
296 (uint32_t(InvalidRegBankID) << 24) |
297 (uint32_t(InvalidRegBankID) << 26) |
298 (uint32_t(InvalidRegBankID) << 28) |
299 (uint32_t(RISCV::FPRBRegBankID) << 30), // FPR64CRegClassID
300 (uint32_t(InvalidRegBankID) << 0) |
301 (uint32_t(InvalidRegBankID) << 2) |
302 (uint32_t(InvalidRegBankID) << 4) |
303 (uint32_t(InvalidRegBankID) << 6) |
304 (uint32_t(InvalidRegBankID) << 8) |
305 (uint32_t(RISCV::VRBRegBankID) << 10) | // VMV0RegClassID
306 (uint32_t(InvalidRegBankID) << 12) |
307 (uint32_t(InvalidRegBankID) << 14) |
308 (uint32_t(InvalidRegBankID) << 16) |
309 (uint32_t(InvalidRegBankID) << 18) |
310 (uint32_t(InvalidRegBankID) << 20) |
311 (uint32_t(InvalidRegBankID) << 22) |
312 (uint32_t(InvalidRegBankID) << 24) |
313 (uint32_t(RISCV::VRBRegBankID) << 26) | // VRM2RegClassID
314 (uint32_t(RISCV::VRBRegBankID) << 28) | // VRM2NoV0RegClassID
315 (uint32_t(RISCV::VRBRegBankID) << 30), // VRM2_with_sub_vrm1_0_in_VMV0RegClassID
316 (uint32_t(InvalidRegBankID) << 0) |
317 (uint32_t(InvalidRegBankID) << 2) |
318 (uint32_t(InvalidRegBankID) << 4) |
319 (uint32_t(InvalidRegBankID) << 6) |
320 (uint32_t(InvalidRegBankID) << 8) |
321 (uint32_t(InvalidRegBankID) << 10) |
322 (uint32_t(InvalidRegBankID) << 12) |
323 (uint32_t(InvalidRegBankID) << 14) |
324 (uint32_t(InvalidRegBankID) << 16) |
325 (uint32_t(InvalidRegBankID) << 18) |
326 (uint32_t(RISCV::VRBRegBankID) << 20) | // VRM4RegClassID
327 (uint32_t(RISCV::VRBRegBankID) << 22) | // VRM4NoV0RegClassID
328 (uint32_t(RISCV::VRBRegBankID) << 24) | // VRM4_with_sub_vrm1_0_in_VMV0RegClassID
329 (uint32_t(InvalidRegBankID) << 26) |
330 (uint32_t(InvalidRegBankID) << 28) |
331 (uint32_t(InvalidRegBankID) << 30),
332 (uint32_t(InvalidRegBankID) << 0) |
333 (uint32_t(InvalidRegBankID) << 2) |
334 (uint32_t(InvalidRegBankID) << 4) |
335 (uint32_t(InvalidRegBankID) << 6) |
336 (uint32_t(InvalidRegBankID) << 8) |
337 (uint32_t(InvalidRegBankID) << 10) |
338 (uint32_t(InvalidRegBankID) << 12) |
339 (uint32_t(InvalidRegBankID) << 14) |
340 (uint32_t(InvalidRegBankID) << 16) |
341 (uint32_t(InvalidRegBankID) << 18) |
342 (uint32_t(InvalidRegBankID) << 20) |
343 (uint32_t(InvalidRegBankID) << 22) |
344 (uint32_t(InvalidRegBankID) << 24) |
345 (uint32_t(InvalidRegBankID) << 26) |
346 (uint32_t(InvalidRegBankID) << 28) |
347 (uint32_t(InvalidRegBankID) << 30),
348 (uint32_t(InvalidRegBankID) << 0) |
349 (uint32_t(InvalidRegBankID) << 2) |
350 (uint32_t(InvalidRegBankID) << 4) |
351 (uint32_t(RISCV::VRBRegBankID) << 6) | // VRM8RegClassID
352 (uint32_t(RISCV::VRBRegBankID) << 8) | // VRM8NoV0RegClassID
353 (uint32_t(RISCV::VRBRegBankID) << 10) // VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID
354 };
355 const unsigned RegClassID = RC.getID();
356 if (LLVM_LIKELY(RegClassID < 150)) {
357 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
358 if (RegBankID != InvalidRegBankID)
359 return getRegBank(RegBankID);
360 }
361 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
362}
363
364} // namespace llvm
365
366#endif // GET_TARGET_REGBANK_IMPL
367
368