1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::RISCV {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 FPRBRegBankID = 0,
17 GPRBRegBankID = 1,
18 VRBRegBankID = 2,
19 NumRegisterBanks,
20};
21
22} // namespace llvm::RISCV
23
24#endif // GET_REGBANK_DECLARATIONS
25
26#ifdef GET_TARGET_REGBANK_CLASS
27#undef GET_TARGET_REGBANK_CLASS
28
29private:
30 static const RegisterBank *RegBanks[];
31 static const unsigned Sizes[];
32
33public:
34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
35protected:
36 RISCVGenRegisterBankInfo(unsigned HwMode = 0);
37
38
39#endif // GET_TARGET_REGBANK_CLASS
40
41#ifdef GET_TARGET_REGBANK_IMPL
42#undef GET_TARGET_REGBANK_IMPL
43
44namespace llvm {
45
46namespace RISCV {
47
48const uint32_t FPRBRegBankCoverageData[] = {
49 // 0-31
50 (1u << (RISCV::FPR16RegClassID - 0)) |
51 (1u << (RISCV::FPR32RegClassID - 0)) |
52 (1u << (RISCV::FPR16CRegClassID - 0)) |
53 (1u << (RISCV::FPR32CRegClassID - 0)) |
54 0,
55 // 32-63
56 0,
57 // 64-95
58 (1u << (RISCV::FPR64RegClassID - 64)) |
59 (1u << (RISCV::FPR64CRegClassID - 64)) |
60 0,
61 // 96-127
62 0,
63 // 128-159
64 0,
65};
66const uint32_t GPRBRegBankCoverageData[] = {
67 // 0-31
68 (1u << (RISCV::GPRRegClassID - 0)) |
69 (1u << (RISCV::GPRF16RegClassID - 0)) |
70 (1u << (RISCV::GPRF32RegClassID - 0)) |
71 (1u << (RISCV::GPRNoX0RegClassID - 0)) |
72 (1u << (RISCV::GPRF16NoX0RegClassID - 0)) |
73 (1u << (RISCV::GPRF32NoX0RegClassID - 0)) |
74 (1u << (RISCV::GPRNoX0X2RegClassID - 0)) |
75 (1u << (RISCV::GPRNoX0X2_and_GPRNoX31RegClassID - 0)) |
76 (1u << (RISCV::GPRJALR_and_GPRNoX31RegClassID - 0)) |
77 (1u << (RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID - 0)) |
78 (1u << (RISCV::GPRNoX31_and_GPRTCNonX7RegClassID - 0)) |
79 (1u << (RISCV::GPRF16CRegClassID - 0)) |
80 (1u << (RISCV::GPRF32CRegClassID - 0)) |
81 (1u << (RISCV::GPRCRegClassID - 0)) |
82 (1u << (RISCV::GPRS07RegClassID - 0)) |
83 (1u << (RISCV::GPRNoX31_and_GPRTCRegClassID - 0)) |
84 (1u << (RISCV::GPRJALRRegClassID - 0)) |
85 (1u << (RISCV::GPRJALRNonX7RegClassID - 0)) |
86 (1u << (RISCV::GPRTCNonX7RegClassID - 0)) |
87 (1u << (RISCV::GPRTCRegClassID - 0)) |
88 (1u << (RISCV::GPRNoX0_and_GPRNoX31RegClassID - 0)) |
89 (1u << (RISCV::GPRNoX2RegClassID - 0)) |
90 (1u << (RISCV::GPRNoX2_and_GPRNoX31RegClassID - 0)) |
91 (1u << (RISCV::GPRF16X0RegClassID - 0)) |
92 (1u << (RISCV::GPRNoX31RegClassID - 0)) |
93 0,
94 // 32-63
95 (1u << (RISCV::GPRC_and_GPRTCRegClassID - 32)) |
96 (1u << (RISCV::GPRC_and_GPRS07RegClassID - 32)) |
97 (1u << (RISCV::GPRX7RegClassID - 32)) |
98 (1u << (RISCV::GPRX1X5RegClassID - 32)) |
99 (1u << (RISCV::GPRX1RegClassID - 32)) |
100 (1u << (RISCV::GPRX5RegClassID - 32)) |
101 (1u << (RISCV::SPRegClassID - 32)) |
102 (1u << (RISCV::GPRX0RegClassID - 32)) |
103 (1u << (RISCV::GPRF32X0RegClassID - 32)) |
104 (1u << (RISCV::GPRPairRegClassID - 32)) |
105 (1u << (RISCV::GPRPairNoX0RegClassID - 32)) |
106 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRNoX31RegClassID - 32)) |
107 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPairNoX0_with_sub_gpr_odd_in_GPRNoX31RegClassID - 32)) |
108 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID - 32)) |
109 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID - 32)) |
110 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7RegClassID - 32)) |
111 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID - 32)) |
112 (1u << (RISCV::GPRPairCRegClassID - 32)) |
113 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRS07RegClassID - 32)) |
114 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID - 32)) |
115 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRX7RegClassID - 32)) |
116 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRX1X5RegClassID - 32)) |
117 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID - 32)) |
118 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID - 32)) |
119 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID - 32)) |
120 (1u << (RISCV::GPRPairNoX0_with_sub_gpr_odd_in_GPRTCNonX7RegClassID - 32)) |
121 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID - 32)) |
122 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID - 32)) |
123 0,
124 // 64-95
125 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_GPRS07RegClassID - 64)) |
126 (1u << (RISCV::GPRPair_with_sub_gpr_even_in_SPRegClassID - 64)) |
127 (1u << (RISCV::GPRPair_with_sub_16_in_GPRF16X0RegClassID - 64)) |
128 0,
129 // 96-127
130 0,
131 // 128-159
132 0,
133};
134const uint32_t VRBRegBankCoverageData[] = {
135 // 0-31
136 0,
137 // 32-63
138 0,
139 // 64-95
140 (1u << (RISCV::VRRegClassID - 64)) |
141 (1u << (RISCV::ZZZ_VMRegClassID - 64)) |
142 (1u << (RISCV::ZZZ_VRMF2RegClassID - 64)) |
143 (1u << (RISCV::ZZZ_VRMF4RegClassID - 64)) |
144 (1u << (RISCV::ZZZ_VRMF8RegClassID - 64)) |
145 (1u << (RISCV::VRNoV0RegClassID - 64)) |
146 (1u << (RISCV::ZZZ_VMNoV0RegClassID - 64)) |
147 (1u << (RISCV::ZZZ_VRMF2NoV0RegClassID - 64)) |
148 (1u << (RISCV::ZZZ_VRMF4NoV0RegClassID - 64)) |
149 (1u << (RISCV::ZZZ_VRMF8NoV0RegClassID - 64)) |
150 0,
151 // 96-127
152 (1u << (RISCV::VRM2RegClassID - 96)) |
153 (1u << (RISCV::VRM2NoV0RegClassID - 96)) |
154 (1u << (RISCV::VRM4RegClassID - 96)) |
155 (1u << (RISCV::VRM4NoV0RegClassID - 96)) |
156 (1u << (RISCV::VMV0RegClassID - 96)) |
157 (1u << (RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID - 96)) |
158 (1u << (RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 96)) |
159 0,
160 // 128-159
161 (1u << (RISCV::VRM8RegClassID - 128)) |
162 (1u << (RISCV::VRM8NoV0RegClassID - 128)) |
163 (1u << (RISCV::VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 128)) |
164 0,
165};
166
167constexpr RegisterBank FPRBRegBank(/* ID */ RISCV::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 152);
168constexpr RegisterBank GPRBRegBank(/* ID */ RISCV::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 152);
169constexpr RegisterBank VRBRegBank(/* ID */ RISCV::VRBRegBankID, /* Name */ "VRB", /* CoveredRegClasses */ VRBRegBankCoverageData, /* NumRegClasses */ 152);
170
171} // namespace RISCV
172
173const RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = {
174 &RISCV::FPRBRegBank,
175 &RISCV::GPRBRegBank,
176 &RISCV::VRBRegBank,
177};
178
179const unsigned RISCVGenRegisterBankInfo::Sizes[] = {
180 // Mode = 0 (DefaultMode)
181 64,
182 64,
183 512,
184 // Mode = 1 (RV64)
185 64,
186 128,
187 512,
188};
189
190RISCVGenRegisterBankInfo::RISCVGenRegisterBankInfo(unsigned HwMode)
191 : RegisterBankInfo(RegBanks, RISCV::NumRegisterBanks, Sizes, HwMode) {
192 // Assert that RegBank indices match their ID's
193#ifndef NDEBUG
194 for (auto RB : enumerate(RegBanks))
195 assert(RB.index() == RB.value()->getID() && "Index != ID");
196#endif // NDEBUG
197}
198
199const RegisterBank &
200RISCVGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
201 constexpr uint32_t InvalidRegBankID = uint32_t(RISCV::InvalidRegBankID) & 3;
202 static const uint32_t RegClass2RegBank[10] = {
203 (uint32_t(InvalidRegBankID) << 0) |
204 (uint32_t(InvalidRegBankID) << 2) |
205 (uint32_t(RISCV::FPRBRegBankID) << 4) | // FPR16RegClassID
206 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRF16RegClassID
207 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRF16NoX0RegClassID
208 (uint32_t(RISCV::FPRBRegBankID) << 10) | // FPR16CRegClassID
209 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRF16CRegClassID
210 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRF16X0RegClassID
211 (uint32_t(RISCV::FPRBRegBankID) << 16) | // FPR32RegClassID
212 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRRegClassID
213 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRF32RegClassID
214 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRF32NoX0RegClassID
215 (uint32_t(RISCV::GPRBRegBankID) << 24) | // GPRNoX0RegClassID
216 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRNoX2RegClassID
217 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRNoX31RegClassID
218 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRNoX0X2RegClassID
219 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRNoX0_and_GPRNoX31RegClassID
220 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRNoX2_and_GPRNoX31RegClassID
221 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRNoX0X2_and_GPRNoX31RegClassID
222 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRJALRRegClassID
223 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRJALRNonX7RegClassID
224 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRJALR_and_GPRNoX31RegClassID
225 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRJALRNonX7_and_GPRNoX31RegClassID
226 (uint32_t(InvalidRegBankID) << 14) |
227 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRTCRegClassID
228 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRNoX31_and_GPRTCRegClassID
229 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRTCNonX7RegClassID
230 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRNoX31_and_GPRTCNonX7RegClassID
231 (uint32_t(RISCV::FPRBRegBankID) << 24) | // FPR32CRegClassID
232 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRCRegClassID
233 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRF32CRegClassID
234 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRS07RegClassID
235 (uint32_t(InvalidRegBankID) << 0) |
236 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRC_and_GPRTCRegClassID
237 (uint32_t(InvalidRegBankID) << 4) |
238 (uint32_t(InvalidRegBankID) << 6) |
239 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRC_and_GPRS07RegClassID
240 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRX1X5RegClassID
241 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRF32X0RegClassID
242 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRX0RegClassID
243 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRX1RegClassID
244 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRX5RegClassID
245 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRX7RegClassID
246 (uint32_t(RISCV::GPRBRegBankID) << 22) | // SPRegClassID
247 (uint32_t(InvalidRegBankID) << 24) |
248 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRPairRegClassID
249 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRPairNoX0RegClassID
250 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID
251 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRPairNoX0_with_sub_gpr_odd_in_GPRNoX31RegClassID
252 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID
253 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID
254 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPairNoX0_with_sub_gpr_odd_in_GPRNoX31RegClassID
255 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRPairNoX0_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID
256 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRPairNoX0_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID
257 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRPairNoX0_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID
258 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRPair_with_sub_gpr_even_in_GPRTCRegClassID
259 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRPairNoX0_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID
260 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRPairNoX0_with_sub_gpr_odd_in_GPRTCNonX7RegClassID
261 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRPairNoX0_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7RegClassID
262 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRPairCRegClassID
263 (uint32_t(RISCV::GPRBRegBankID) << 24) | // GPRPair_with_sub_gpr_even_in_GPRS07RegClassID
264 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID
265 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRPairNoX0_with_sub_gpr_odd_in_GPRX1X5RegClassID
266 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRPairNoX0_with_sub_gpr_odd_in_GPRX7RegClassID
267 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRPair_with_sub_16_in_GPRF16X0RegClassID
268 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRS07RegClassID
269 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRPair_with_sub_gpr_even_in_SPRegClassID
270 (uint32_t(RISCV::FPRBRegBankID) << 6) | // FPR64RegClassID
271 (uint32_t(RISCV::VRBRegBankID) << 8) | // VRRegClassID
272 (uint32_t(InvalidRegBankID) << 10) |
273 (uint32_t(RISCV::VRBRegBankID) << 12) | // ZZZ_VMRegClassID
274 (uint32_t(RISCV::VRBRegBankID) << 14) | // ZZZ_VRMF2RegClassID
275 (uint32_t(RISCV::VRBRegBankID) << 16) | // ZZZ_VRMF4RegClassID
276 (uint32_t(RISCV::VRBRegBankID) << 18) | // ZZZ_VRMF8RegClassID
277 (uint32_t(RISCV::VRBRegBankID) << 20) | // VRNoV0RegClassID
278 (uint32_t(InvalidRegBankID) << 22) |
279 (uint32_t(InvalidRegBankID) << 24) |
280 (uint32_t(InvalidRegBankID) << 26) |
281 (uint32_t(RISCV::VRBRegBankID) << 28) | // ZZZ_VMNoV0RegClassID
282 (uint32_t(RISCV::VRBRegBankID) << 30), // ZZZ_VRMF2NoV0RegClassID
283 (uint32_t(RISCV::VRBRegBankID) << 0) | // ZZZ_VRMF4NoV0RegClassID
284 (uint32_t(RISCV::VRBRegBankID) << 2) | // ZZZ_VRMF8NoV0RegClassID
285 (uint32_t(InvalidRegBankID) << 4) |
286 (uint32_t(InvalidRegBankID) << 6) |
287 (uint32_t(InvalidRegBankID) << 8) |
288 (uint32_t(InvalidRegBankID) << 10) |
289 (uint32_t(InvalidRegBankID) << 12) |
290 (uint32_t(InvalidRegBankID) << 14) |
291 (uint32_t(InvalidRegBankID) << 16) |
292 (uint32_t(InvalidRegBankID) << 18) |
293 (uint32_t(InvalidRegBankID) << 20) |
294 (uint32_t(InvalidRegBankID) << 22) |
295 (uint32_t(InvalidRegBankID) << 24) |
296 (uint32_t(InvalidRegBankID) << 26) |
297 (uint32_t(RISCV::FPRBRegBankID) << 28) | // FPR64CRegClassID
298 (uint32_t(InvalidRegBankID) << 30),
299 (uint32_t(InvalidRegBankID) << 0) |
300 (uint32_t(InvalidRegBankID) << 2) |
301 (uint32_t(InvalidRegBankID) << 4) |
302 (uint32_t(InvalidRegBankID) << 6) |
303 (uint32_t(RISCV::VRBRegBankID) << 8) | // VMV0RegClassID
304 (uint32_t(InvalidRegBankID) << 10) |
305 (uint32_t(InvalidRegBankID) << 12) |
306 (uint32_t(InvalidRegBankID) << 14) |
307 (uint32_t(InvalidRegBankID) << 16) |
308 (uint32_t(InvalidRegBankID) << 18) |
309 (uint32_t(InvalidRegBankID) << 20) |
310 (uint32_t(InvalidRegBankID) << 22) |
311 (uint32_t(RISCV::VRBRegBankID) << 24) | // VRM2RegClassID
312 (uint32_t(RISCV::VRBRegBankID) << 26) | // VRM2NoV0RegClassID
313 (uint32_t(RISCV::VRBRegBankID) << 28) | // VRM2_with_sub_vrm1_0_in_VMV0RegClassID
314 (uint32_t(InvalidRegBankID) << 30),
315 (uint32_t(InvalidRegBankID) << 0) |
316 (uint32_t(InvalidRegBankID) << 2) |
317 (uint32_t(InvalidRegBankID) << 4) |
318 (uint32_t(InvalidRegBankID) << 6) |
319 (uint32_t(InvalidRegBankID) << 8) |
320 (uint32_t(InvalidRegBankID) << 10) |
321 (uint32_t(InvalidRegBankID) << 12) |
322 (uint32_t(InvalidRegBankID) << 14) |
323 (uint32_t(InvalidRegBankID) << 16) |
324 (uint32_t(RISCV::VRBRegBankID) << 18) | // VRM4RegClassID
325 (uint32_t(RISCV::VRBRegBankID) << 20) | // VRM4NoV0RegClassID
326 (uint32_t(RISCV::VRBRegBankID) << 22) | // VRM4_with_sub_vrm1_0_in_VMV0RegClassID
327 (uint32_t(InvalidRegBankID) << 24) |
328 (uint32_t(InvalidRegBankID) << 26) |
329 (uint32_t(InvalidRegBankID) << 28) |
330 (uint32_t(InvalidRegBankID) << 30),
331 (uint32_t(InvalidRegBankID) << 0) |
332 (uint32_t(InvalidRegBankID) << 2) |
333 (uint32_t(InvalidRegBankID) << 4) |
334 (uint32_t(InvalidRegBankID) << 6) |
335 (uint32_t(InvalidRegBankID) << 8) |
336 (uint32_t(InvalidRegBankID) << 10) |
337 (uint32_t(InvalidRegBankID) << 12) |
338 (uint32_t(InvalidRegBankID) << 14) |
339 (uint32_t(InvalidRegBankID) << 16) |
340 (uint32_t(InvalidRegBankID) << 18) |
341 (uint32_t(InvalidRegBankID) << 20) |
342 (uint32_t(InvalidRegBankID) << 22) |
343 (uint32_t(InvalidRegBankID) << 24) |
344 (uint32_t(InvalidRegBankID) << 26) |
345 (uint32_t(InvalidRegBankID) << 28) |
346 (uint32_t(InvalidRegBankID) << 30),
347 (uint32_t(InvalidRegBankID) << 0) |
348 (uint32_t(InvalidRegBankID) << 2) |
349 (uint32_t(RISCV::VRBRegBankID) << 4) | // VRM8RegClassID
350 (uint32_t(RISCV::VRBRegBankID) << 6) | // VRM8NoV0RegClassID
351 (uint32_t(RISCV::VRBRegBankID) << 8) // VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID
352 };
353 const unsigned RegClassID = RC.getID();
354 if (LLVM_LIKELY(RegClassID < 149)) {
355 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
356 if (RegBankID != InvalidRegBankID)
357 return getRegBank(RegBankID);
358 }
359 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
360}
361
362} // namespace llvm
363
364#endif // GET_TARGET_REGBANK_IMPL
365
366