| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* MC Register Information *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | namespace llvm { |
| 10 | |
| 11 | extern const int16_t RISCVRegDiffLists[] = { |
| 12 | /* 0 */ -192, 193, -33, -217, 0, |
| 13 | /* 5 */ -105, 0, |
| 14 | /* 7 */ -103, 0, |
| 15 | /* 9 */ -101, 0, |
| 16 | /* 11 */ -99, 0, |
| 17 | /* 13 */ -97, 0, |
| 18 | /* 15 */ -95, 0, |
| 19 | /* 17 */ 25, -106, -86, 0, |
| 20 | /* 21 */ 317, -1, -3, 49, 52, 43, -80, 121, 27, 26, 25, -148, 42, -86, 0, |
| 21 | /* 36 */ 321, 1, 1, 71, 52, 43, -80, 121, 27, 26, 25, -148, 42, -86, 0, |
| 22 | /* 51 */ -1, -3, 64, 51, 42, -86, 0, |
| 23 | /* 58 */ 1, 1, 86, 51, 42, -86, 0, |
| 24 | /* 65 */ -104, -85, 0, |
| 25 | /* 68 */ -102, -84, 0, |
| 26 | /* 71 */ -100, -83, 0, |
| 27 | /* 74 */ -98, -82, 0, |
| 28 | /* 77 */ -96, -81, 0, |
| 29 | /* 80 */ -530, 1, 1, 1, 1, 390, 52, 43, -125, 53, -52, 96, -43, -52, 0, |
| 30 | /* 95 */ -502, 1, 1, 1, 1, 359, 53, 44, -96, 53, -52, 96, -43, -52, 0, |
| 31 | /* 110 */ -88, -321, 1, 323, -322, 1, 391, 52, 43, -125, 53, -52, 0, |
| 32 | /* 123 */ -557, 1, 1, 1, 1, 1, 389, 52, 43, -125, 53, -52, 165, -69, 42, -85, 44, -96, 53, -52, 0, |
| 33 | /* 144 */ -530, 1, 1, 1, 1, 1, 358, 53, 44, -96, 53, -52, 137, -41, 42, -85, 44, -96, 53, -52, 0, |
| 34 | /* 165 */ -583, 1, 1, 1, 1, 1, 1, 388, 52, 43, -125, 53, -52, 165, 27, -96, 42, 28, -113, 44, 42, -138, 53, 44, -96, 53, -52, 0, |
| 35 | /* 193 */ -557, 1, 1, 1, 1, 1, 1, 357, 53, 44, -96, 53, -52, 137, 28, -69, 42, 28, -113, 44, 42, -138, 53, 44, -96, 53, -52, 0, |
| 36 | /* 221 */ -608, 1, 1, 1, 1, 1, 1, 1, 387, 52, 43, -125, 53, -52, 165, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 0, |
| 37 | /* 257 */ -583, 1, 1, 1, 1, 1, 1, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, -96, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 0, |
| 38 | /* 293 */ -71, -322, 1, 322, -321, 1, 360, 53, 44, -96, 53, -52, 0, |
| 39 | /* 306 */ -71, -321, 1, 322, -321, 1, 360, 53, 44, -96, 53, -52, 0, |
| 40 | /* 319 */ -70, -320, 1, 322, -321, 1, 360, 53, 44, -96, 53, -52, 0, |
| 41 | /* 332 */ -70, -321, 1, 321, -320, 1, 360, 53, 44, -96, 53, -52, 0, |
| 42 | /* 345 */ -68, -321, 1, 321, -320, 1, 360, 53, 44, -96, 53, -52, 0, |
| 43 | /* 358 */ -68, -320, 1, 321, -320, 1, 360, 53, 44, -96, 53, -52, 0, |
| 44 | /* 371 */ -67, -319, 1, 321, -320, 1, 360, 53, 44, -96, 53, -52, 0, |
| 45 | /* 384 */ -67, -320, 1, 320, -319, 1, 360, 53, 44, -96, 53, -52, 0, |
| 46 | /* 397 */ -65, -320, 1, 320, -319, 1, 360, 53, 44, -96, 53, -52, 0, |
| 47 | /* 410 */ -65, -319, 1, 320, -319, 1, 360, 53, 44, -96, 53, -52, 0, |
| 48 | /* 423 */ -64, -318, 1, 320, -319, 1, 360, 53, 44, -96, 53, -52, 0, |
| 49 | /* 436 */ -64, -319, 1, 319, -318, 1, 360, 53, 44, -96, 53, -52, 0, |
| 50 | /* 449 */ -62, -319, 1, 319, -318, 1, 360, 53, 44, -96, 53, -52, 0, |
| 51 | /* 462 */ -62, -318, 1, 319, -318, 1, 360, 53, 44, -96, 53, -52, 0, |
| 52 | /* 475 */ -489, 1, 1, 1, 391, 52, -82, 53, -52, 0, |
| 53 | /* 485 */ -460, 1, 1, 1, 360, 53, -52, 53, -52, 0, |
| 54 | /* 495 */ -94, -1, -321, 1, 323, -322, 1, 323, -1, -321, 1, 322, -321, 1, 387, 52, 43, -125, 53, -52, 165, 27, 26, 25, -147, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 40, 51, 42, -107, 52, -51, 0, |
| 55 | /* 544 */ -72, -1, -318, 1, 320, -319, 1, 320, -1, -318, 1, 319, -318, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 13, 52, 43, -94, 52, -51, 0, |
| 56 | /* 593 */ -74, -1, -319, 1, 320, -319, 1, 320, -1, -318, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 15, 52, 43, -94, 52, -51, 0, |
| 57 | /* 642 */ -77, -1, -319, 1, 321, -320, 1, 321, -1, -319, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 17, 52, 43, -94, 52, -51, 0, |
| 58 | /* 691 */ -79, -1, -320, 1, 321, -320, 1, 321, -1, -319, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 19, 52, 43, -94, 52, -51, 0, |
| 59 | /* 740 */ -82, -1, -320, 1, 322, -321, 1, 322, -1, -320, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 21, 52, 43, -94, 52, -51, 0, |
| 60 | /* 789 */ -84, -1, -321, 1, 322, -321, 1, 322, -1, -320, 1, 322, -321, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 23, 52, 43, -94, 52, -51, 0, |
| 61 | /* 838 */ -181, -321, 1, 323, -322, 1, 322, -321, 1, 322, -321, 1, 387, 52, 43, -125, 53, -52, 165, 27, 26, 25, -147, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 40, 51, -65, 52, -51, 0, |
| 62 | /* 884 */ -159, -318, 1, 320, -319, 1, 319, -318, 1, 319, -318, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 13, 52, -51, 52, -51, 0, |
| 63 | /* 930 */ -159, -319, 1, 319, -318, 1, 320, -319, 1, 319, -318, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 14, 52, -51, 52, -51, 0, |
| 64 | /* 976 */ -160, -319, 1, 320, -319, 1, 319, -318, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 15, 52, -51, 52, -51, 0, |
| 65 | /* 1022 */ -160, -320, 1, 320, -319, 1, 320, -319, 1, 319, -318, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 16, 52, -51, 52, -51, 0, |
| 66 | /* 1068 */ -162, -319, 1, 321, -320, 1, 320, -319, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 17, 52, -51, 52, -51, 0, |
| 67 | /* 1114 */ -162, -320, 1, 320, -319, 1, 321, -320, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 18, 52, -51, 52, -51, 0, |
| 68 | /* 1160 */ -163, -320, 1, 321, -320, 1, 320, -319, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 19, 52, -51, 52, -51, 0, |
| 69 | /* 1206 */ -163, -321, 1, 321, -320, 1, 321, -320, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 20, 52, -51, 52, -51, 0, |
| 70 | /* 1252 */ -165, -320, 1, 322, -321, 1, 321, -320, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 21, 52, -51, 52, -51, 0, |
| 71 | /* 1298 */ -165, -321, 1, 321, -320, 1, 322, -321, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 22, 52, -51, 52, -51, 0, |
| 72 | /* 1344 */ -166, -321, 1, 322, -321, 1, 321, -320, 1, 322, -321, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 23, 52, -51, 52, -51, 0, |
| 73 | /* 1390 */ -166, -322, 1, 322, -321, 1, 322, -321, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 24, 52, -51, 52, -51, 0, |
| 74 | /* 1436 */ -225, 193, -33, 0, |
| 75 | /* 1440 */ -315, 193, -33, -159, 193, -33, 0, |
| 76 | /* 1447 */ -314, 193, -33, -159, 193, -33, 0, |
| 77 | /* 1454 */ -313, 193, -33, -159, 193, -33, 0, |
| 78 | /* 1461 */ -312, 193, -33, -159, 193, -33, 0, |
| 79 | /* 1468 */ -311, 193, -33, -159, 193, -33, 0, |
| 80 | /* 1475 */ -310, 193, -33, -159, 193, -33, 0, |
| 81 | /* 1482 */ -309, 193, -33, -159, 193, -33, 0, |
| 82 | /* 1489 */ -308, 193, -33, -159, 193, -33, 0, |
| 83 | /* 1496 */ -307, 193, -33, -159, 193, -33, 0, |
| 84 | /* 1503 */ -306, 193, -33, -159, 193, -33, 0, |
| 85 | /* 1510 */ -305, 193, -33, -159, 193, -33, 0, |
| 86 | /* 1517 */ -304, 193, -33, -159, 193, -33, 0, |
| 87 | /* 1524 */ -303, 193, -33, -159, 193, -33, 0, |
| 88 | /* 1531 */ -302, 193, -33, -159, 193, -33, 0, |
| 89 | /* 1538 */ -301, 193, -33, -159, 193, -33, 0, |
| 90 | /* 1545 */ -446, 1, 1, 392, -30, 0, |
| 91 | /* 1551 */ -139, -321, 1, 323, -322, 1, 322, -321, 1, 389, 52, 43, -125, 53, -52, 165, 27, -96, 42, -85, 44, -96, 53, -52, 42, -14, 0, |
| 92 | /* 1578 */ -394, 1, 0, |
| 93 | /* 1581 */ -363, 1, 0, |
| 94 | /* 1584 */ -1, -321, 1, 323, -322, 1, 0, |
| 95 | /* 1591 */ -1, -1, -321, 1, 323, -322, 1, 323, -1, -321, 1, 322, -321, 1, 0, |
| 96 | /* 1606 */ -1, -320, 1, 322, -321, 1, 0, |
| 97 | /* 1613 */ -1, -1, -320, 1, 322, -321, 1, 322, -1, -320, 1, 321, -320, 1, 0, |
| 98 | /* 1628 */ -1, -319, 1, 321, -320, 1, 0, |
| 99 | /* 1635 */ -1, -1, -319, 1, 321, -320, 1, 321, -1, -319, 1, 320, -319, 1, 0, |
| 100 | /* 1650 */ -1, -318, 1, 320, -319, 1, 0, |
| 101 | /* 1657 */ -1, -1, -318, 1, 320, -319, 1, 320, -1, -318, 1, 319, -318, 1, 0, |
| 102 | /* 1672 */ 1, 1, 1, 1, 1, 1, 1, 0, |
| 103 | /* 1680 */ -114, -319, 1, 319, -318, 1, 319, -318, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 14, 1, 0, |
| 104 | /* 1707 */ -116, -318, 1, 320, -319, 1, 319, -318, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 15, 1, 0, |
| 105 | /* 1734 */ -116, -319, 1, 319, -318, 1, 320, -319, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 16, 1, 0, |
| 106 | /* 1761 */ -117, -319, 1, 320, -319, 1, 319, -318, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 17, 1, 0, |
| 107 | /* 1788 */ -117, -320, 1, 320, -319, 1, 320, -319, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 18, 1, 0, |
| 108 | /* 1815 */ -119, -319, 1, 321, -320, 1, 320, -319, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 19, 1, 0, |
| 109 | /* 1842 */ -119, -320, 1, 320, -319, 1, 321, -320, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 20, 1, 0, |
| 110 | /* 1869 */ -120, -320, 1, 321, -320, 1, 320, -319, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 21, 1, 0, |
| 111 | /* 1896 */ -120, -321, 1, 321, -320, 1, 321, -320, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 22, 1, 0, |
| 112 | /* 1923 */ -122, -320, 1, 322, -321, 1, 321, -320, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 23, 1, 0, |
| 113 | /* 1950 */ -122, -321, 1, 321, -320, 1, 322, -321, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 24, 1, 0, |
| 114 | /* 1977 */ -123, -321, 1, 322, -321, 1, 321, -320, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 25, 1, 0, |
| 115 | /* 2004 */ -123, -322, 1, 322, -321, 1, 322, -321, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 26, 1, 0, |
| 116 | /* 2031 */ 1, 70, 1, 0, |
| 117 | /* 2035 */ 1, 75, 1, 0, |
| 118 | /* 2039 */ -3, 76, 1, 0, |
| 119 | /* 2043 */ 1, 80, 1, 0, |
| 120 | /* 2047 */ -3, 81, 1, 0, |
| 121 | /* 2051 */ -416, 1, 1, 361, 1, 0, |
| 122 | /* 2057 */ 321, -2, 1, 42, 1, 51, 1, 43, -70, 28, 44, -71, 68, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 92, 2, 2, 2, 0, |
| 123 | /* 2107 */ 320, -1, -3, 46, 1, 51, 43, -68, 26, 1, 43, -69, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0, |
| 124 | /* 2157 */ 320, 1, 1, 40, 1, 51, 1, 43, -69, 27, 44, -70, 67, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 100, 28, 27, 26, -141, 43, -82, 122, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0, |
| 125 | /* 2207 */ 52, 1, 43, -69, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 123, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0, |
| 126 | /* 2242 */ 320, -1, -3, 46, 1, 51, 1, 43, -72, 30, 44, -73, 70, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 94, 2, 2, 2, 0, |
| 127 | /* 2292 */ 320, 1, -3, 44, 1, 51, 1, 43, -71, 29, 44, -72, 69, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 103, 28, 27, 26, -143, 43, -83, 125, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0, |
| 128 | /* 2342 */ 320, -2, 1, 43, 1, 51, 43, -70, 28, 1, 43, -71, 110, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0, |
| 129 | /* 2392 */ 52, 1, 43, -71, 70, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0, |
| 130 | /* 2427 */ 319, 1, 1, 41, 1, 51, 43, -69, 27, 1, 43, -70, 109, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 149, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 2, 0, |
| 131 | /* 2477 */ 52, 1, 43, -70, 69, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 126, 26, 1, 25, -97, 94, 2, 2, 2, 0, |
| 132 | /* 2513 */ 320, -2, 1, 43, 1, 51, 1, 43, -74, 32, 44, -75, 72, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 96, 2, 2, 2, 0, |
| 133 | /* 2563 */ 319, 1, 1, 41, 1, 51, 1, 43, -73, 31, 44, -74, 71, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 106, 28, 27, 26, -145, 43, -84, 128, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0, |
| 134 | /* 2613 */ 319, -1, -3, 47, 1, 51, 43, -72, 30, 1, 43, -73, 112, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0, |
| 135 | /* 2663 */ 52, 1, 43, -73, 72, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0, |
| 136 | /* 2698 */ 319, 1, -3, 45, 1, 51, 43, -71, 29, 1, 43, -72, 111, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 152, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 2, 0, |
| 137 | /* 2748 */ 52, 1, 43, -72, 71, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 129, 26, 1, 25, -99, 96, 2, 2, 2, 0, |
| 138 | /* 2784 */ 319, -1, -3, 47, 1, 51, 1, 43, -76, 34, 44, -77, 74, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 98, 2, 2, 2, 0, |
| 139 | /* 2834 */ 319, 1, -3, 45, 1, 51, 1, 43, -75, 33, 44, -76, 73, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 109, 28, 27, 26, -147, 43, -85, 131, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0, |
| 140 | /* 2884 */ 319, -2, 1, 44, 1, 51, 43, -74, 32, 1, 43, -75, 114, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0, |
| 141 | /* 2934 */ 52, 1, 43, -75, 74, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0, |
| 142 | /* 2969 */ 318, 1, 1, 42, 1, 51, 43, -73, 31, 1, 43, -74, 113, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 155, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 2, 0, |
| 143 | /* 3019 */ 52, 1, 43, -74, 73, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 132, 26, 1, 25, -101, 98, 2, 2, 2, 0, |
| 144 | /* 3055 */ 318, 1, 1, 42, 1, 51, 1, 43, -77, 35, 44, -78, 75, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 112, 28, 27, 26, -149, 43, -86, 134, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0, |
| 145 | /* 3105 */ 318, -1, -3, 48, 1, 51, 43, -76, 34, 1, 43, -77, 116, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0, |
| 146 | /* 3155 */ 52, 1, 43, -77, 76, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0, |
| 147 | /* 3190 */ 318, 1, -3, 46, 1, 51, 43, -75, 33, 1, 43, -76, 115, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 158, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 2, 0, |
| 148 | /* 3240 */ 52, 1, 43, -76, 75, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 135, 26, 1, 25, -103, 100, 2, 2, 2, 0, |
| 149 | /* 3276 */ 321, -1, -3, 45, 1, 51, 1, 43, -68, 26, 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0, |
| 150 | /* 3325 */ 52, 43, -68, 26, 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0, |
| 151 | /* 3364 */ 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 123, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0, |
| 152 | /* 3392 */ 52, 43, -70, 28, 44, -71, 110, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 94, 2, 2, 0, |
| 153 | /* 3431 */ 44, -71, 70, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 94, 2, 2, 0, |
| 154 | /* 3459 */ 52, 43, -69, 27, 44, -70, 109, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 100, 28, 27, 26, -141, 43, -82, 149, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 0, |
| 155 | /* 3498 */ 43, -69, 110, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 150, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 0, |
| 156 | /* 3526 */ 44, -70, 69, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 100, 28, 27, 26, -141, 43, -82, 126, 26, 1, 25, -97, 94, 2, 2, 0, |
| 157 | /* 3555 */ 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 127, 26, 1, 25, -97, 94, 2, 2, 0, |
| 158 | /* 3574 */ 52, 1, 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0, |
| 159 | /* 3609 */ 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0, |
| 160 | /* 3638 */ 320, 1, -3, 44, 1, 51, 43, -67, 25, 1, 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 93, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0, |
| 161 | /* 3684 */ 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 123, 26, 1, 25, -95, 94, 2, 2, 0, |
| 162 | /* 3703 */ 52, 43, -72, 30, 44, -73, 112, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 96, 2, 2, 0, |
| 163 | /* 3742 */ 44, -73, 72, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 96, 2, 2, 0, |
| 164 | /* 3770 */ 52, 43, -71, 29, 44, -72, 111, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 103, 28, 27, 26, -143, 43, -83, 152, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 0, |
| 165 | /* 3809 */ 43, -71, 112, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 153, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 0, |
| 166 | /* 3837 */ 44, -72, 71, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 103, 28, 27, 26, -143, 43, -83, 129, 26, 1, 25, -99, 96, 2, 2, 0, |
| 167 | /* 3866 */ 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 130, 26, 1, 25, -99, 96, 2, 2, 0, |
| 168 | /* 3885 */ 43, -70, 111, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 126, 26, 1, 25, -97, 96, 2, 2, 0, |
| 169 | /* 3914 */ 52, 43, -74, 32, 44, -75, 114, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 98, 2, 2, 0, |
| 170 | /* 3953 */ 44, -75, 74, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 98, 2, 2, 0, |
| 171 | /* 3981 */ 52, 43, -73, 31, 44, -74, 113, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 106, 28, 27, 26, -145, 43, -84, 155, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 0, |
| 172 | /* 4020 */ 43, -73, 114, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 156, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 0, |
| 173 | /* 4048 */ 44, -74, 73, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 106, 28, 27, 26, -145, 43, -84, 132, 26, 1, 25, -101, 98, 2, 2, 0, |
| 174 | /* 4077 */ 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 133, 26, 1, 25, -101, 98, 2, 2, 0, |
| 175 | /* 4096 */ 43, -72, 113, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 129, 26, 1, 25, -99, 98, 2, 2, 0, |
| 176 | /* 4125 */ 52, 43, -76, 34, 44, -77, 116, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 100, 2, 2, 0, |
| 177 | /* 4164 */ 44, -77, 76, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 100, 2, 2, 0, |
| 178 | /* 4192 */ 52, 43, -75, 33, 44, -76, 115, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 109, 28, 27, 26, -147, 43, -85, 158, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 0, |
| 179 | /* 4231 */ 43, -75, 116, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 159, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 0, |
| 180 | /* 4259 */ 44, -76, 75, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 109, 28, 27, 26, -147, 43, -85, 135, 26, 1, 25, -103, 100, 2, 2, 0, |
| 181 | /* 4288 */ 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 136, 26, 1, 25, -103, 100, 2, 2, 0, |
| 182 | /* 4307 */ 43, -74, 115, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 132, 26, 1, 25, -101, 100, 2, 2, 0, |
| 183 | /* 4336 */ 317, 1, 1, 43, 1, 51, 43, -77, 35, 1, 43, -78, 117, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 161, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0, |
| 184 | /* 4385 */ 52, 43, -77, 35, 44, -78, 117, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 112, 28, 27, 26, -149, 43, -86, 161, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0, |
| 185 | /* 4424 */ 43, -77, 118, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 162, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0, |
| 186 | /* 4452 */ 319, -2, 1, 44, 1, 51, 1, 43, -78, 36, 44, -79, 76, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0, |
| 187 | /* 4498 */ 52, 1, 43, -78, 77, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0, |
| 188 | /* 4533 */ 44, -78, 77, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 112, 28, 27, 26, -149, 43, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0, |
| 189 | /* 4562 */ 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 139, 26, 1, 25, -105, 102, 2, 2, 0, |
| 190 | /* 4581 */ 43, -76, 117, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 135, 26, 1, 25, -103, 102, 2, 2, 0, |
| 191 | /* 4610 */ -1, -3, 73, 1, 51, 1, 42, -81, 37, 55, -86, 74, 2, 0, |
| 192 | /* 4624 */ 1, 1, 67, 1, 50, 1, 42, -81, 40, 43, -82, 79, 2, 0, |
| 193 | /* 4638 */ 1, -3, 69, 1, 50, 1, 42, -82, 41, 43, -83, 80, 2, 0, |
| 194 | /* 4652 */ 51, 1, 42, -81, 80, 2, 0, |
| 195 | /* 4659 */ 1, 1, 64, 1, 50, 1, 42, -83, 42, 43, -84, 81, 2, 0, |
| 196 | /* 4673 */ -2, 1, 68, 1, 50, 42, -81, 40, 1, 42, -82, 81, 2, 0, |
| 197 | /* 4687 */ 51, 1, 42, -82, 81, 2, 0, |
| 198 | /* 4694 */ 1, -3, 66, 1, 50, 1, 42, -84, 43, 43, -85, 82, 2, 0, |
| 199 | /* 4708 */ -1, -3, 70, 1, 50, 42, -82, 41, 1, 42, -83, 82, 2, 0, |
| 200 | /* 4722 */ 51, 1, 42, -83, 82, 2, 0, |
| 201 | /* 4729 */ 1, 1, 61, 1, 50, 1, 42, -85, 44, 43, -86, 83, 2, 0, |
| 202 | /* 4743 */ -2, 1, 65, 1, 50, 42, -83, 42, 1, 42, -84, 83, 2, 0, |
| 203 | /* 4757 */ 51, 1, 42, -84, 83, 2, 0, |
| 204 | /* 4764 */ -1, -3, 67, 1, 50, 42, -84, 43, 1, 42, -85, 84, 2, 0, |
| 205 | /* 4778 */ 51, 1, 42, -85, 84, 2, 0, |
| 206 | /* 4785 */ -69, 110, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 150, 25, -95, 73, 26, -97, 94, 2, 0, |
| 207 | /* 4807 */ 27, 26, -25, 26, 25, -138, 42, -81, 153, 26, -97, 94, 2, 0, |
| 208 | /* 4821 */ 44, -68, 110, 28, 27, 26, -139, 43, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 209 | /* 4849 */ -68, 110, 28, 27, 26, -139, 43, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 210 | /* 4872 */ 321, 1, -3, 43, 1, 51, 1, 43, -67, 25, 44, -68, 110, 28, 27, 26, -139, 43, -81, 51, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 211 | /* 4915 */ 321, -2, 1, 42, 1, 52, 1, 43, -67, 22, 72, -80, 52, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 212 | /* 4951 */ 52, 1, 43, -67, 66, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 213 | /* 4979 */ 52, 43, -67, 25, 44, -68, 110, 28, 27, 26, -139, 43, -81, 93, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 214 | /* 5014 */ 43, -67, 108, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 215 | /* 5038 */ 28, 27, 26, -139, 43, -81, 123, 26, 1, 25, -95, 94, 2, 0, |
| 216 | /* 5052 */ -71, 112, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 153, 25, -97, 75, 26, -99, 96, 2, 0, |
| 217 | /* 5074 */ 27, 26, -25, 26, 25, -140, 42, -82, 156, 26, -99, 96, 2, 0, |
| 218 | /* 5088 */ -70, 111, 27, 26, 25, -138, 42, -81, 100, 28, 27, 26, -141, 43, -82, 126, 26, 1, 25, -97, 96, 2, 0, |
| 219 | /* 5111 */ 27, 26, 25, -138, 42, -81, 127, 26, 1, 25, -97, 96, 2, 0, |
| 220 | /* 5125 */ 27, 1, 26, 1, 25, -139, 43, -81, 150, 25, -95, 96, 2, 0, |
| 221 | /* 5139 */ -73, 114, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 156, 25, -99, 77, 26, -101, 98, 2, 0, |
| 222 | /* 5161 */ 27, 26, -25, 26, 25, -142, 42, -83, 159, 26, -101, 98, 2, 0, |
| 223 | /* 5175 */ -72, 113, 27, 26, 25, -140, 42, -82, 103, 28, 27, 26, -143, 43, -83, 129, 26, 1, 25, -99, 98, 2, 0, |
| 224 | /* 5198 */ 27, 26, 25, -140, 42, -82, 130, 26, 1, 25, -99, 98, 2, 0, |
| 225 | /* 5212 */ 27, 1, 26, 1, 25, -141, 43, -82, 153, 25, -97, 98, 2, 0, |
| 226 | /* 5226 */ -75, 116, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 159, 25, -101, 79, 26, -103, 100, 2, 0, |
| 227 | /* 5248 */ 27, 26, -25, 26, 25, -144, 42, -84, 162, 26, -103, 100, 2, 0, |
| 228 | /* 5262 */ -74, 115, 27, 26, 25, -142, 42, -83, 106, 28, 27, 26, -145, 43, -84, 132, 26, 1, 25, -101, 100, 2, 0, |
| 229 | /* 5285 */ 27, 26, 25, -142, 42, -83, 133, 26, 1, 25, -101, 100, 2, 0, |
| 230 | /* 5299 */ 27, 1, 26, 1, 25, -143, 43, -83, 156, 25, -99, 100, 2, 0, |
| 231 | /* 5313 */ -77, 118, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 162, 25, -103, 81, 26, -105, 102, 2, 0, |
| 232 | /* 5335 */ 27, 26, -25, 26, 25, -146, 42, -85, 165, 26, -105, 102, 2, 0, |
| 233 | /* 5349 */ -76, 117, 27, 26, 25, -144, 42, -84, 109, 28, 27, 26, -147, 43, -85, 135, 26, 1, 25, -103, 102, 2, 0, |
| 234 | /* 5372 */ 27, 26, 25, -144, 42, -84, 136, 26, 1, 25, -103, 102, 2, 0, |
| 235 | /* 5386 */ 27, 1, 26, 1, 25, -145, 43, -84, 159, 25, -101, 102, 2, 0, |
| 236 | /* 5400 */ 52, 43, -78, 36, 44, -79, 118, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 237 | /* 5435 */ 44, -79, 78, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 238 | /* 5459 */ 318, -2, 1, 45, 1, 51, 43, -78, 36, 1, 43, -79, 118, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 239 | /* 5502 */ 318, 1, -3, 46, 1, 51, 1, 43, -79, 37, 44, -80, 77, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 240 | /* 5538 */ 52, 1, 43, -79, 78, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 241 | /* 5566 */ 43, -78, 119, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 242 | /* 5594 */ -78, 119, 27, 26, 25, -146, 42, -85, 112, 28, 27, 26, -149, 43, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 243 | /* 5617 */ 27, 26, 25, -146, 42, -85, 139, 26, 1, 25, -105, 104, 2, 0, |
| 244 | /* 5631 */ 27, 1, 26, 1, 25, -147, 43, -85, 162, 25, -103, 104, 2, 0, |
| 245 | /* 5645 */ 26, 1, 25, -96, -81, 176, 2, 0, |
| 246 | /* 5653 */ 26, 1, 25, -98, -82, 179, 2, 0, |
| 247 | /* 5661 */ 26, 1, 25, -100, -83, 182, 2, 0, |
| 248 | /* 5669 */ 26, 1, 25, -102, -84, 185, 2, 0, |
| 249 | /* 5677 */ 26, 1, 25, -104, -85, 188, 2, 0, |
| 250 | /* 5685 */ -3, 87, 6, 0, |
| 251 | /* 5689 */ -129, -96, 32, 32, 0, |
| 252 | /* 5694 */ 33, -193, 192, 33, 0, |
| 253 | /* 5699 */ 57, 0, |
| 254 | /* 5701 */ -3, 71, 0, |
| 255 | /* 5704 */ 1, -3, 72, 1, 52, 43, -81, 50, -13, 55, -86, 74, 0, |
| 256 | /* 5717 */ -2, 1, 72, 14, 51, -13, 55, -86, 74, 0, |
| 257 | /* 5727 */ 65, -13, 55, -86, 74, 0, |
| 258 | /* 5733 */ 52, 43, -81, 37, 55, -86, 74, 0, |
| 259 | /* 5741 */ 33, -193, 225, 75, 0, |
| 260 | /* 5746 */ 33, -193, 225, 76, 0, |
| 261 | /* 5751 */ 33, -193, 225, 77, 0, |
| 262 | /* 5756 */ 33, -193, 225, 78, 0, |
| 263 | /* 5761 */ 33, -193, 225, 79, 0, |
| 264 | /* 5766 */ 43, -81, 80, 0, |
| 265 | /* 5770 */ 33, -193, 225, 80, 0, |
| 266 | /* 5775 */ 51, 42, -81, 40, 43, -82, 81, 0, |
| 267 | /* 5783 */ 33, -193, 225, 81, 0, |
| 268 | /* 5788 */ 51, 42, -82, 41, 43, -83, 82, 0, |
| 269 | /* 5796 */ 42, -81, 82, 0, |
| 270 | /* 5800 */ 33, -193, 225, 82, 0, |
| 271 | /* 5805 */ 51, 42, -83, 42, 43, -84, 83, 0, |
| 272 | /* 5813 */ 42, -82, 83, 0, |
| 273 | /* 5817 */ 33, -193, 225, 83, 0, |
| 274 | /* 5822 */ 51, 42, -84, 43, 43, -85, 84, 0, |
| 275 | /* 5830 */ 42, -83, 84, 0, |
| 276 | /* 5834 */ 33, -193, 225, 84, 0, |
| 277 | /* 5839 */ -2, 1, 62, 1, 50, 42, -85, 44, 1, 42, -86, 85, 0, |
| 278 | /* 5852 */ 1, -3, 63, 1, 50, 1, 42, -86, 85, 0, |
| 279 | /* 5862 */ 51, 1, 42, -86, 85, 0, |
| 280 | /* 5868 */ 51, 42, -85, 44, 43, -86, 85, 0, |
| 281 | /* 5876 */ 42, -84, 85, 0, |
| 282 | /* 5880 */ 33, -193, 225, 85, 0, |
| 283 | /* 5885 */ 42, -85, 86, 0, |
| 284 | /* 5889 */ 33, -193, 225, 86, 0, |
| 285 | /* 5894 */ 33, -193, 225, 87, 0, |
| 286 | /* 5899 */ 33, -193, 225, 88, 0, |
| 287 | /* 5904 */ 33, -193, 225, 89, 0, |
| 288 | /* 5909 */ 33, -193, 225, 90, 0, |
| 289 | /* 5914 */ 1, 93, 0, |
| 290 | /* 5917 */ 27, 52, -51, 26, 50, -161, 55, -86, 143, 26, -95, 94, 0, |
| 291 | /* 5930 */ 322, -2, 1, 41, 1, 53, 44, -67, 51, -29, 72, -80, 52, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0, |
| 292 | /* 5961 */ 53, 44, -67, 22, 72, -80, 52, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0, |
| 293 | /* 5986 */ 44, -67, 66, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0, |
| 294 | /* 6007 */ -67, 108, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0, |
| 295 | /* 6025 */ 26, 25, -138, 42, -81, 153, 26, -97, 96, 0, |
| 296 | /* 6035 */ 27, 26, -139, 43, -81, 150, 25, -95, 96, 0, |
| 297 | /* 6045 */ 26, 25, -140, 42, -82, 156, 26, -99, 98, 0, |
| 298 | /* 6055 */ 27, 26, -141, 43, -82, 153, 25, -97, 98, 0, |
| 299 | /* 6065 */ 26, 25, -142, 42, -83, 159, 26, -101, 100, 0, |
| 300 | /* 6075 */ 27, 26, -143, 43, -83, 156, 25, -99, 100, 0, |
| 301 | /* 6085 */ 26, 25, -144, 42, -84, 162, 26, -103, 102, 0, |
| 302 | /* 6095 */ 27, 26, -145, 43, -84, 159, 25, -101, 102, 0, |
| 303 | /* 6105 */ 26, 25, -146, 42, -85, 165, 26, -105, 104, 0, |
| 304 | /* 6115 */ 27, 26, -147, 43, -85, 162, 25, -103, 104, 0, |
| 305 | /* 6125 */ -79, 120, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0, |
| 306 | /* 6143 */ 317, 1, -3, 47, 1, 51, 43, -79, 37, 1, 43, -80, 119, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0, |
| 307 | /* 6174 */ 52, 43, -79, 37, 44, -80, 119, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0, |
| 308 | /* 6199 */ 43, -79, 120, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0, |
| 309 | /* 6220 */ 27, 1, 26, 1, 25, -149, 43, -86, 165, 25, -105, 106, 0, |
| 310 | /* 6233 */ 27, 26, -149, 43, -86, 165, 25, -105, 106, 0, |
| 311 | /* 6243 */ -32, -32, 96, 129, 0, |
| 312 | /* 6248 */ 52, -25, 50, -106, -86, 168, 0, |
| 313 | /* 6255 */ 320, 1, 1, 41, 30, 52, -29, 72, -80, 52, 69, -27, 54, -26, 52, -25, 50, -148, 42, -86, 168, 0, |
| 314 | /* 6277 */ 82, -29, 72, -80, 52, 69, -27, 54, -26, 52, -25, 50, -148, 42, -86, 168, 0, |
| 315 | /* 6294 */ 26, -96, -81, 176, 0, |
| 316 | /* 6299 */ 25, -96, -81, 178, 0, |
| 317 | /* 6304 */ 26, -98, -82, 179, 0, |
| 318 | /* 6309 */ 25, -98, -82, 181, 0, |
| 319 | /* 6314 */ 26, -100, -83, 182, 0, |
| 320 | /* 6319 */ 25, -100, -83, 184, 0, |
| 321 | /* 6324 */ 26, -102, -84, 185, 0, |
| 322 | /* 6329 */ 25, -102, -84, 187, 0, |
| 323 | /* 6334 */ 26, -104, -85, 188, 0, |
| 324 | /* 6339 */ 25, -104, -85, 190, 0, |
| 325 | /* 6344 */ 26, 1, 25, -106, -86, 191, 0, |
| 326 | /* 6351 */ 26, -106, -86, 191, 0, |
| 327 | /* 6356 */ 27, 26, -25, 26, 25, -148, 42, -86, 191, 0, |
| 328 | /* 6366 */ 318, -1, -3, 48, 1, 51, 1, 43, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0, |
| 329 | /* 6388 */ 52, 1, 43, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0, |
| 330 | /* 6405 */ 44, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0, |
| 331 | /* 6420 */ 33, -193, 225, 0, |
| 332 | /* 6424 */ 249, 0, |
| 333 | }; |
| 334 | |
| 335 | extern const LaneBitmask RISCVLaneMaskLists[] = { |
| 336 | /* 0 */ LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000001), |
| 337 | /* 2 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), |
| 338 | /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), |
| 339 | /* 7 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), |
| 340 | /* 11 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), |
| 341 | /* 16 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), |
| 342 | /* 22 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), |
| 343 | /* 29 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), |
| 344 | /* 37 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000200), |
| 345 | /* 39 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), |
| 346 | }; |
| 347 | |
| 348 | extern const uint16_t RISCVSubRegIdxLists[] = { |
| 349 | /* 0 */ 4, 3, 2, 1, |
| 350 | /* 4 */ 5, 2, 1, |
| 351 | /* 7 */ 6, 2, 1, 7, |
| 352 | /* 11 */ 8, 9, |
| 353 | /* 13 */ 16, 8, 9, 17, 10, 11, |
| 354 | /* 19 */ 20, 16, 8, 9, 17, 10, 11, 21, 18, 12, 13, 19, 14, 15, |
| 355 | /* 33 */ 6, 2, 1, 7, 23, 22, |
| 356 | /* 39 */ 8, 9, 10, 24, 27, |
| 357 | /* 44 */ 8, 9, 10, 11, 24, 25, 27, 28, 29, |
| 358 | /* 53 */ 16, 8, 9, 17, 10, 11, 24, 25, 26, 27, 28, 29, |
| 359 | /* 65 */ 8, 9, 10, 11, 12, 24, 25, 26, 27, 28, 29, 34, 38, 42, |
| 360 | /* 79 */ 8, 9, 10, 11, 12, 13, 24, 25, 26, 27, 28, 29, 30, 34, 35, 38, 39, 42, 43, 46, |
| 361 | /* 99 */ 8, 9, 10, 11, 12, 13, 14, 24, 25, 26, 27, 28, 29, 30, 31, 34, 35, 36, 38, 39, 40, 42, 43, 44, 46, 47, 49, |
| 362 | /* 126 */ 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, |
| 363 | /* 161 */ 16, 8, 9, 17, 10, 11, 18, 12, 13, 24, 25, 26, 27, 28, 29, 30, 31, 34, 35, 38, 39, 42, 43, 46, 52, 55, |
| 364 | /* 187 */ 16, 8, 9, 17, 10, 11, 18, 12, 13, 19, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 55, 56, 57, |
| 365 | /* 232 */ 20, 16, 8, 9, 17, 10, 11, 21, 18, 12, 13, 19, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, |
| 366 | }; |
| 367 | |
| 368 | |
| 369 | #ifdef __GNUC__ |
| 370 | #pragma GCC diagnostic push |
| 371 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 372 | #endif |
| 373 | extern const char RISCVRegStrings[] = { |
| 374 | /* 0 */ "T10\000" |
| 375 | /* 4 */ "V3_V4_V5_V6_V7_V8_V9_V10\000" |
| 376 | /* 29 */ "X10\000" |
| 377 | /* 33 */ "V13_V14_V15_V16_V17_V18_V19_V20\000" |
| 378 | /* 65 */ "X20\000" |
| 379 | /* 69 */ "V23_V24_V25_V26_V27_V28_V29_V30\000" |
| 380 | /* 101 */ "X30\000" |
| 381 | /* 105 */ "M0\000" |
| 382 | /* 108 */ "T0\000" |
| 383 | /* 111 */ "V0\000" |
| 384 | /* 114 */ "DUMMY_REG_PAIR_WITH_X0\000" |
| 385 | /* 137 */ "T11\000" |
| 386 | /* 141 */ "V4_V5_V6_V7_V8_V9_V10_V11\000" |
| 387 | /* 167 */ "X10_X11\000" |
| 388 | /* 175 */ "V14_V15_V16_V17_V18_V19_V20_V21\000" |
| 389 | /* 207 */ "X20_X21\000" |
| 390 | /* 215 */ "V24_V25_V26_V27_V28_V29_V30_V31\000" |
| 391 | /* 247 */ "X30_X31\000" |
| 392 | /* 255 */ "M1\000" |
| 393 | /* 258 */ "T1\000" |
| 394 | /* 261 */ "V0_V1\000" |
| 395 | /* 267 */ "X1\000" |
| 396 | /* 270 */ "T12\000" |
| 397 | /* 274 */ "V5_V6_V7_V8_V9_V10_V11_V12\000" |
| 398 | /* 301 */ "X12\000" |
| 399 | /* 305 */ "V15_V16_V17_V18_V19_V20_V21_V22\000" |
| 400 | /* 337 */ "X22\000" |
| 401 | /* 341 */ "V4M2_V6M2_V8M2_V10M2\000" |
| 402 | /* 362 */ "V14M2_V16M2_V18M2_V20M2\000" |
| 403 | /* 386 */ "V24M2_V26M2_V28M2_V30M2\000" |
| 404 | /* 410 */ "V0M2\000" |
| 405 | /* 415 */ "V6M2_V8M2_V10M2_V12M2\000" |
| 406 | /* 437 */ "V16M2_V18M2_V20M2_V22M2\000" |
| 407 | /* 461 */ "V0M2_V2M2\000" |
| 408 | /* 471 */ "V8M2_V10M2_V12M2_V14M2\000" |
| 409 | /* 494 */ "V18M2_V20M2_V22M2_V24M2\000" |
| 410 | /* 518 */ "V0M2_V2M2_V4M2\000" |
| 411 | /* 533 */ "V10M2_V12M2_V14M2_V16M2\000" |
| 412 | /* 557 */ "V20M2_V22M2_V24M2_V26M2\000" |
| 413 | /* 581 */ "V0M2_V2M2_V4M2_V6M2\000" |
| 414 | /* 601 */ "V12M2_V14M2_V16M2_V18M2\000" |
| 415 | /* 625 */ "V22M2_V24M2_V26M2_V28M2\000" |
| 416 | /* 649 */ "V2M2_V4M2_V6M2_V8M2\000" |
| 417 | /* 669 */ "F10_Q2\000" |
| 418 | /* 676 */ "F20_Q2\000" |
| 419 | /* 683 */ "F30_Q2\000" |
| 420 | /* 690 */ "F0_Q2\000" |
| 421 | /* 696 */ "F11_Q2\000" |
| 422 | /* 703 */ "F21_Q2\000" |
| 423 | /* 710 */ "F31_Q2\000" |
| 424 | /* 717 */ "F1_Q2\000" |
| 425 | /* 723 */ "F12_Q2\000" |
| 426 | /* 730 */ "F22_Q2\000" |
| 427 | /* 737 */ "F2_Q2\000" |
| 428 | /* 743 */ "F13_Q2\000" |
| 429 | /* 750 */ "F23_Q2\000" |
| 430 | /* 757 */ "F3_Q2\000" |
| 431 | /* 763 */ "F14_Q2\000" |
| 432 | /* 770 */ "F24_Q2\000" |
| 433 | /* 777 */ "F4_Q2\000" |
| 434 | /* 783 */ "F15_Q2\000" |
| 435 | /* 790 */ "F25_Q2\000" |
| 436 | /* 797 */ "F5_Q2\000" |
| 437 | /* 803 */ "F16_Q2\000" |
| 438 | /* 810 */ "F26_Q2\000" |
| 439 | /* 817 */ "F6_Q2\000" |
| 440 | /* 823 */ "F17_Q2\000" |
| 441 | /* 830 */ "F27_Q2\000" |
| 442 | /* 837 */ "F7_Q2\000" |
| 443 | /* 843 */ "F18_Q2\000" |
| 444 | /* 850 */ "F28_Q2\000" |
| 445 | /* 857 */ "F8_Q2\000" |
| 446 | /* 863 */ "F19_Q2\000" |
| 447 | /* 870 */ "F29_Q2\000" |
| 448 | /* 877 */ "F9_Q2\000" |
| 449 | /* 883 */ "T2\000" |
| 450 | /* 886 */ "V0_V1_V2\000" |
| 451 | /* 895 */ "X2\000" |
| 452 | /* 898 */ "T13\000" |
| 453 | /* 902 */ "V6_V7_V8_V9_V10_V11_V12_V13\000" |
| 454 | /* 930 */ "X12_X13\000" |
| 455 | /* 938 */ "V16_V17_V18_V19_V20_V21_V22_V23\000" |
| 456 | /* 970 */ "X22_X23\000" |
| 457 | /* 978 */ "M3\000" |
| 458 | /* 981 */ "T3\000" |
| 459 | /* 984 */ "V0_V1_V2_V3\000" |
| 460 | /* 996 */ "X2_X3\000" |
| 461 | /* 1002 */ "T14\000" |
| 462 | /* 1006 */ "V7_V8_V9_V10_V11_V12_V13_V14\000" |
| 463 | /* 1035 */ "X14\000" |
| 464 | /* 1039 */ "V17_V18_V19_V20_V21_V22_V23_V24\000" |
| 465 | /* 1071 */ "X24\000" |
| 466 | /* 1075 */ "V16M4_V20M4\000" |
| 467 | /* 1087 */ "V0M4\000" |
| 468 | /* 1092 */ "V8M4_V12M4\000" |
| 469 | /* 1103 */ "V20M4_V24M4\000" |
| 470 | /* 1115 */ "V0M4_V4M4\000" |
| 471 | /* 1125 */ "V12M4_V16M4\000" |
| 472 | /* 1137 */ "V24M4_V28M4\000" |
| 473 | /* 1149 */ "V4M4_V8M4\000" |
| 474 | /* 1159 */ "T4\000" |
| 475 | /* 1162 */ "V0_V1_V2_V3_V4\000" |
| 476 | /* 1177 */ "X4\000" |
| 477 | /* 1180 */ "T15\000" |
| 478 | /* 1184 */ "V8_V9_V10_V11_V12_V13_V14_V15\000" |
| 479 | /* 1214 */ "X14_X15\000" |
| 480 | /* 1222 */ "V18_V19_V20_V21_V22_V23_V24_V25\000" |
| 481 | /* 1254 */ "X24_X25\000" |
| 482 | /* 1262 */ "M5\000" |
| 483 | /* 1265 */ "T5\000" |
| 484 | /* 1268 */ "V0_V1_V2_V3_V4_V5\000" |
| 485 | /* 1286 */ "X4_X5\000" |
| 486 | /* 1292 */ "V9_V10_V11_V12_V13_V14_V15_V16\000" |
| 487 | /* 1323 */ "X16\000" |
| 488 | /* 1327 */ "V19_V20_V21_V22_V23_V24_V25_V26\000" |
| 489 | /* 1359 */ "X26\000" |
| 490 | /* 1363 */ "M6\000" |
| 491 | /* 1366 */ "T6\000" |
| 492 | /* 1369 */ "V0_V1_V2_V3_V4_V5_V6\000" |
| 493 | /* 1390 */ "X6\000" |
| 494 | /* 1393 */ "V10_V11_V12_V13_V14_V15_V16_V17\000" |
| 495 | /* 1425 */ "X16_X17\000" |
| 496 | /* 1433 */ "V20_V21_V22_V23_V24_V25_V26_V27\000" |
| 497 | /* 1465 */ "X26_X27\000" |
| 498 | /* 1473 */ "M7\000" |
| 499 | /* 1476 */ "T7\000" |
| 500 | /* 1479 */ "V0_V1_V2_V3_V4_V5_V6_V7\000" |
| 501 | /* 1503 */ "X6_X7\000" |
| 502 | /* 1509 */ "V11_V12_V13_V14_V15_V16_V17_V18\000" |
| 503 | /* 1541 */ "X18\000" |
| 504 | /* 1545 */ "V21_V22_V23_V24_V25_V26_V27_V28\000" |
| 505 | /* 1577 */ "X28\000" |
| 506 | /* 1581 */ "V0M8\000" |
| 507 | /* 1586 */ "V24M8\000" |
| 508 | /* 1592 */ "V16M8\000" |
| 509 | /* 1598 */ "V8M8\000" |
| 510 | /* 1603 */ "T8\000" |
| 511 | /* 1606 */ "V1_V2_V3_V4_V5_V6_V7_V8\000" |
| 512 | /* 1630 */ "X8\000" |
| 513 | /* 1633 */ "V12_V13_V14_V15_V16_V17_V18_V19\000" |
| 514 | /* 1665 */ "X18_X19\000" |
| 515 | /* 1673 */ "V22_V23_V24_V25_V26_V27_V28_V29\000" |
| 516 | /* 1705 */ "X28_X29\000" |
| 517 | /* 1713 */ "T9\000" |
| 518 | /* 1716 */ "V2_V3_V4_V5_V6_V7_V8_V9\000" |
| 519 | /* 1740 */ "X8_X9\000" |
| 520 | /* 1746 */ "VLENB\000" |
| 521 | /* 1752 */ "F10_D\000" |
| 522 | /* 1758 */ "F20_D\000" |
| 523 | /* 1764 */ "F30_D\000" |
| 524 | /* 1770 */ "F0_D\000" |
| 525 | /* 1775 */ "F11_D\000" |
| 526 | /* 1781 */ "F21_D\000" |
| 527 | /* 1787 */ "F31_D\000" |
| 528 | /* 1793 */ "F1_D\000" |
| 529 | /* 1798 */ "F12_D\000" |
| 530 | /* 1804 */ "F22_D\000" |
| 531 | /* 1810 */ "F2_D\000" |
| 532 | /* 1815 */ "F13_D\000" |
| 533 | /* 1821 */ "F23_D\000" |
| 534 | /* 1827 */ "F3_D\000" |
| 535 | /* 1832 */ "F14_D\000" |
| 536 | /* 1838 */ "F24_D\000" |
| 537 | /* 1844 */ "F4_D\000" |
| 538 | /* 1849 */ "F15_D\000" |
| 539 | /* 1855 */ "F25_D\000" |
| 540 | /* 1861 */ "F5_D\000" |
| 541 | /* 1866 */ "F16_D\000" |
| 542 | /* 1872 */ "F26_D\000" |
| 543 | /* 1878 */ "F6_D\000" |
| 544 | /* 1883 */ "F17_D\000" |
| 545 | /* 1889 */ "F27_D\000" |
| 546 | /* 1895 */ "F7_D\000" |
| 547 | /* 1900 */ "F18_D\000" |
| 548 | /* 1906 */ "F28_D\000" |
| 549 | /* 1912 */ "F8_D\000" |
| 550 | /* 1917 */ "F19_D\000" |
| 551 | /* 1923 */ "F29_D\000" |
| 552 | /* 1929 */ "F9_D\000" |
| 553 | /* 1934 */ "VTYPE\000" |
| 554 | /* 1940 */ "SF_VCIX_STATE\000" |
| 555 | /* 1954 */ "F10_F\000" |
| 556 | /* 1960 */ "F20_F\000" |
| 557 | /* 1966 */ "F30_F\000" |
| 558 | /* 1972 */ "F0_F\000" |
| 559 | /* 1977 */ "F11_F\000" |
| 560 | /* 1983 */ "F21_F\000" |
| 561 | /* 1989 */ "F31_F\000" |
| 562 | /* 1995 */ "F1_F\000" |
| 563 | /* 2000 */ "F12_F\000" |
| 564 | /* 2006 */ "F22_F\000" |
| 565 | /* 2012 */ "F2_F\000" |
| 566 | /* 2017 */ "F13_F\000" |
| 567 | /* 2023 */ "F23_F\000" |
| 568 | /* 2029 */ "F3_F\000" |
| 569 | /* 2034 */ "F14_F\000" |
| 570 | /* 2040 */ "F24_F\000" |
| 571 | /* 2046 */ "F4_F\000" |
| 572 | /* 2051 */ "F15_F\000" |
| 573 | /* 2057 */ "F25_F\000" |
| 574 | /* 2063 */ "F5_F\000" |
| 575 | /* 2068 */ "F16_F\000" |
| 576 | /* 2074 */ "F26_F\000" |
| 577 | /* 2080 */ "F6_F\000" |
| 578 | /* 2085 */ "F17_F\000" |
| 579 | /* 2091 */ "F27_F\000" |
| 580 | /* 2097 */ "F7_F\000" |
| 581 | /* 2102 */ "F18_F\000" |
| 582 | /* 2108 */ "F28_F\000" |
| 583 | /* 2114 */ "F8_F\000" |
| 584 | /* 2119 */ "F19_F\000" |
| 585 | /* 2125 */ "F29_F\000" |
| 586 | /* 2131 */ "F9_F\000" |
| 587 | /* 2136 */ "F10_H\000" |
| 588 | /* 2142 */ "X10_H\000" |
| 589 | /* 2148 */ "F20_H\000" |
| 590 | /* 2154 */ "X20_H\000" |
| 591 | /* 2160 */ "F30_H\000" |
| 592 | /* 2166 */ "X30_H\000" |
| 593 | /* 2172 */ "F0_H\000" |
| 594 | /* 2177 */ "X0_H\000" |
| 595 | /* 2182 */ "F11_H\000" |
| 596 | /* 2188 */ "X11_H\000" |
| 597 | /* 2194 */ "F21_H\000" |
| 598 | /* 2200 */ "X21_H\000" |
| 599 | /* 2206 */ "F31_H\000" |
| 600 | /* 2212 */ "X31_H\000" |
| 601 | /* 2218 */ "F1_H\000" |
| 602 | /* 2223 */ "X1_H\000" |
| 603 | /* 2228 */ "F12_H\000" |
| 604 | /* 2234 */ "X12_H\000" |
| 605 | /* 2240 */ "F22_H\000" |
| 606 | /* 2246 */ "X22_H\000" |
| 607 | /* 2252 */ "F2_H\000" |
| 608 | /* 2257 */ "X2_H\000" |
| 609 | /* 2262 */ "F13_H\000" |
| 610 | /* 2268 */ "X13_H\000" |
| 611 | /* 2274 */ "F23_H\000" |
| 612 | /* 2280 */ "X23_H\000" |
| 613 | /* 2286 */ "F3_H\000" |
| 614 | /* 2291 */ "X3_H\000" |
| 615 | /* 2296 */ "F14_H\000" |
| 616 | /* 2302 */ "X14_H\000" |
| 617 | /* 2308 */ "F24_H\000" |
| 618 | /* 2314 */ "X24_H\000" |
| 619 | /* 2320 */ "F4_H\000" |
| 620 | /* 2325 */ "X4_H\000" |
| 621 | /* 2330 */ "F15_H\000" |
| 622 | /* 2336 */ "X15_H\000" |
| 623 | /* 2342 */ "F25_H\000" |
| 624 | /* 2348 */ "X25_H\000" |
| 625 | /* 2354 */ "F5_H\000" |
| 626 | /* 2359 */ "X5_H\000" |
| 627 | /* 2364 */ "F16_H\000" |
| 628 | /* 2370 */ "X16_H\000" |
| 629 | /* 2376 */ "F26_H\000" |
| 630 | /* 2382 */ "X26_H\000" |
| 631 | /* 2388 */ "F6_H\000" |
| 632 | /* 2393 */ "X6_H\000" |
| 633 | /* 2398 */ "F17_H\000" |
| 634 | /* 2404 */ "X17_H\000" |
| 635 | /* 2410 */ "F27_H\000" |
| 636 | /* 2416 */ "X27_H\000" |
| 637 | /* 2422 */ "F7_H\000" |
| 638 | /* 2427 */ "X7_H\000" |
| 639 | /* 2432 */ "F18_H\000" |
| 640 | /* 2438 */ "X18_H\000" |
| 641 | /* 2444 */ "F28_H\000" |
| 642 | /* 2450 */ "X28_H\000" |
| 643 | /* 2456 */ "F8_H\000" |
| 644 | /* 2461 */ "X8_H\000" |
| 645 | /* 2466 */ "F19_H\000" |
| 646 | /* 2472 */ "X19_H\000" |
| 647 | /* 2478 */ "F29_H\000" |
| 648 | /* 2484 */ "X29_H\000" |
| 649 | /* 2490 */ "F9_H\000" |
| 650 | /* 2495 */ "X9_H\000" |
| 651 | /* 2500 */ "VL\000" |
| 652 | /* 2503 */ "FRM\000" |
| 653 | /* 2507 */ "VXRM\000" |
| 654 | /* 2512 */ "SSP\000" |
| 655 | /* 2516 */ "F10_Q\000" |
| 656 | /* 2522 */ "F20_Q\000" |
| 657 | /* 2528 */ "F30_Q\000" |
| 658 | /* 2534 */ "F0_Q\000" |
| 659 | /* 2539 */ "F11_Q\000" |
| 660 | /* 2545 */ "F21_Q\000" |
| 661 | /* 2551 */ "F31_Q\000" |
| 662 | /* 2557 */ "F1_Q\000" |
| 663 | /* 2562 */ "F12_Q\000" |
| 664 | /* 2568 */ "F22_Q\000" |
| 665 | /* 2574 */ "F2_Q\000" |
| 666 | /* 2579 */ "F13_Q\000" |
| 667 | /* 2585 */ "F23_Q\000" |
| 668 | /* 2591 */ "F3_Q\000" |
| 669 | /* 2596 */ "F14_Q\000" |
| 670 | /* 2602 */ "F24_Q\000" |
| 671 | /* 2608 */ "F4_Q\000" |
| 672 | /* 2613 */ "F15_Q\000" |
| 673 | /* 2619 */ "F25_Q\000" |
| 674 | /* 2625 */ "F5_Q\000" |
| 675 | /* 2630 */ "F16_Q\000" |
| 676 | /* 2636 */ "F26_Q\000" |
| 677 | /* 2642 */ "F6_Q\000" |
| 678 | /* 2647 */ "F17_Q\000" |
| 679 | /* 2653 */ "F27_Q\000" |
| 680 | /* 2659 */ "F7_Q\000" |
| 681 | /* 2664 */ "F18_Q\000" |
| 682 | /* 2670 */ "F28_Q\000" |
| 683 | /* 2676 */ "F8_Q\000" |
| 684 | /* 2681 */ "F19_Q\000" |
| 685 | /* 2687 */ "F29_Q\000" |
| 686 | /* 2693 */ "F9_Q\000" |
| 687 | /* 2698 */ "FCSR\000" |
| 688 | /* 2703 */ "FFLAGS\000" |
| 689 | /* 2710 */ "VXSAT\000" |
| 690 | /* 2716 */ "X10_W\000" |
| 691 | /* 2722 */ "X20_W\000" |
| 692 | /* 2728 */ "X30_W\000" |
| 693 | /* 2734 */ "X0_W\000" |
| 694 | /* 2739 */ "X11_W\000" |
| 695 | /* 2745 */ "X21_W\000" |
| 696 | /* 2751 */ "X31_W\000" |
| 697 | /* 2757 */ "X1_W\000" |
| 698 | /* 2762 */ "X12_W\000" |
| 699 | /* 2768 */ "X22_W\000" |
| 700 | /* 2774 */ "X2_W\000" |
| 701 | /* 2779 */ "X13_W\000" |
| 702 | /* 2785 */ "X23_W\000" |
| 703 | /* 2791 */ "X3_W\000" |
| 704 | /* 2796 */ "X14_W\000" |
| 705 | /* 2802 */ "X24_W\000" |
| 706 | /* 2808 */ "X4_W\000" |
| 707 | /* 2813 */ "X15_W\000" |
| 708 | /* 2819 */ "X25_W\000" |
| 709 | /* 2825 */ "X5_W\000" |
| 710 | /* 2830 */ "X16_W\000" |
| 711 | /* 2836 */ "X26_W\000" |
| 712 | /* 2842 */ "X6_W\000" |
| 713 | /* 2847 */ "X17_W\000" |
| 714 | /* 2853 */ "X27_W\000" |
| 715 | /* 2859 */ "X7_W\000" |
| 716 | /* 2864 */ "X18_W\000" |
| 717 | /* 2870 */ "X28_W\000" |
| 718 | /* 2876 */ "X8_W\000" |
| 719 | /* 2881 */ "X19_W\000" |
| 720 | /* 2887 */ "X29_W\000" |
| 721 | /* 2893 */ "X9_W\000" |
| 722 | /* 2898 */ "X10_Y\000" |
| 723 | /* 2904 */ "X20_Y\000" |
| 724 | /* 2910 */ "X30_Y\000" |
| 725 | /* 2916 */ "X0_Y\000" |
| 726 | /* 2921 */ "X11_Y\000" |
| 727 | /* 2927 */ "X21_Y\000" |
| 728 | /* 2933 */ "X31_Y\000" |
| 729 | /* 2939 */ "X1_Y\000" |
| 730 | /* 2944 */ "X12_Y\000" |
| 731 | /* 2950 */ "X22_Y\000" |
| 732 | /* 2956 */ "X2_Y\000" |
| 733 | /* 2961 */ "X13_Y\000" |
| 734 | /* 2967 */ "X23_Y\000" |
| 735 | /* 2973 */ "X3_Y\000" |
| 736 | /* 2978 */ "X14_Y\000" |
| 737 | /* 2984 */ "X24_Y\000" |
| 738 | /* 2990 */ "X4_Y\000" |
| 739 | /* 2995 */ "X15_Y\000" |
| 740 | /* 3001 */ "X25_Y\000" |
| 741 | /* 3007 */ "X5_Y\000" |
| 742 | /* 3012 */ "X16_Y\000" |
| 743 | /* 3018 */ "X26_Y\000" |
| 744 | /* 3024 */ "X6_Y\000" |
| 745 | /* 3029 */ "X17_Y\000" |
| 746 | /* 3035 */ "X27_Y\000" |
| 747 | /* 3041 */ "X7_Y\000" |
| 748 | /* 3046 */ "X18_Y\000" |
| 749 | /* 3052 */ "X28_Y\000" |
| 750 | /* 3058 */ "X8_Y\000" |
| 751 | /* 3063 */ "X19_Y\000" |
| 752 | /* 3069 */ "X29_Y\000" |
| 753 | /* 3075 */ "X9_Y\000" |
| 754 | /* 3080 */ "X0_Pair\000" |
| 755 | }; |
| 756 | #ifdef __GNUC__ |
| 757 | #pragma GCC diagnostic pop |
| 758 | #endif |
| 759 | |
| 760 | extern const MCRegisterDesc RISCVRegDesc[] = { // Descriptors |
| 761 | { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 762 | { .Name: 2698, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16384, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 763 | { .Name: 2703, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16385, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 764 | { .Name: 2503, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16386, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 765 | { .Name: 1940, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16387, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 766 | { .Name: 2512, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16388, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 767 | { .Name: 2500, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16389, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 768 | { .Name: 1746, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16390, .RegUnitLaneMasks: 39, .IsConstant: 1, .IsArtificial: 0 }, |
| 769 | { .Name: 1934, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16391, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 770 | { .Name: 2507, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16392, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 771 | { .Name: 2710, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16393, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 772 | { .Name: 114, .SubRegs: 4, .SuperRegs: 6424, .SubRegIndices: 4, .RegUnits: 16394, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 773 | { .Name: 105, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16395, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 774 | { .Name: 255, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16396, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 775 | { .Name: 359, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16397, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 776 | { .Name: 978, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16398, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 777 | { .Name: 1084, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16399, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 778 | { .Name: 1262, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16400, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 779 | { .Name: 1363, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16401, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 780 | { .Name: 1473, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16402, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 781 | { .Name: 108, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16403, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 782 | { .Name: 258, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16404, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 783 | { .Name: 883, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16405, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 784 | { .Name: 981, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16406, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 785 | { .Name: 1159, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16407, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 786 | { .Name: 1265, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16408, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 787 | { .Name: 1366, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16409, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 788 | { .Name: 1476, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16410, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 789 | { .Name: 1603, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16411, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 790 | { .Name: 1713, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16412, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 791 | { .Name: 0, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16413, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 792 | { .Name: 137, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16414, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 793 | { .Name: 270, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16415, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 794 | { .Name: 898, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16416, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 795 | { .Name: 1002, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16417, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 796 | { .Name: 1180, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16418, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 797 | { .Name: 111, .SubRegs: 4, .SuperRegs: 36, .SubRegIndices: 4, .RegUnits: 16419, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 798 | { .Name: 264, .SubRegs: 4, .SuperRegs: 6255, .SubRegIndices: 4, .RegUnits: 16420, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 799 | { .Name: 892, .SubRegs: 4, .SuperRegs: 5930, .SubRegIndices: 4, .RegUnits: 16421, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 800 | { .Name: 993, .SubRegs: 4, .SuperRegs: 4915, .SubRegIndices: 4, .RegUnits: 16422, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 801 | { .Name: 1174, .SubRegs: 4, .SuperRegs: 4872, .SubRegIndices: 4, .RegUnits: 16423, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 802 | { .Name: 1283, .SubRegs: 4, .SuperRegs: 3638, .SubRegIndices: 4, .RegUnits: 16424, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 803 | { .Name: 1387, .SubRegs: 4, .SuperRegs: 3276, .SubRegIndices: 4, .RegUnits: 16425, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 804 | { .Name: 1500, .SubRegs: 4, .SuperRegs: 2107, .SubRegIndices: 4, .RegUnits: 16426, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 805 | { .Name: 1627, .SubRegs: 4, .SuperRegs: 2157, .SubRegIndices: 4, .RegUnits: 16427, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 806 | { .Name: 1737, .SubRegs: 4, .SuperRegs: 2427, .SubRegIndices: 4, .RegUnits: 16428, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 807 | { .Name: 25, .SubRegs: 4, .SuperRegs: 2057, .SubRegIndices: 4, .RegUnits: 16429, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 808 | { .Name: 163, .SubRegs: 4, .SuperRegs: 2342, .SubRegIndices: 4, .RegUnits: 16430, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 809 | { .Name: 297, .SubRegs: 4, .SuperRegs: 2292, .SubRegIndices: 4, .RegUnits: 16431, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 810 | { .Name: 926, .SubRegs: 4, .SuperRegs: 2698, .SubRegIndices: 4, .RegUnits: 16432, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 811 | { .Name: 1031, .SubRegs: 4, .SuperRegs: 2242, .SubRegIndices: 4, .RegUnits: 16433, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 812 | { .Name: 1210, .SubRegs: 4, .SuperRegs: 2613, .SubRegIndices: 4, .RegUnits: 16434, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 813 | { .Name: 1319, .SubRegs: 4, .SuperRegs: 2563, .SubRegIndices: 4, .RegUnits: 16435, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 814 | { .Name: 1421, .SubRegs: 4, .SuperRegs: 2969, .SubRegIndices: 4, .RegUnits: 16436, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 815 | { .Name: 1537, .SubRegs: 4, .SuperRegs: 2513, .SubRegIndices: 4, .RegUnits: 16437, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 816 | { .Name: 1661, .SubRegs: 4, .SuperRegs: 2884, .SubRegIndices: 4, .RegUnits: 16438, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 817 | { .Name: 61, .SubRegs: 4, .SuperRegs: 2834, .SubRegIndices: 4, .RegUnits: 16439, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 818 | { .Name: 203, .SubRegs: 4, .SuperRegs: 3190, .SubRegIndices: 4, .RegUnits: 16440, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 819 | { .Name: 333, .SubRegs: 4, .SuperRegs: 2784, .SubRegIndices: 4, .RegUnits: 16441, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 820 | { .Name: 966, .SubRegs: 4, .SuperRegs: 3105, .SubRegIndices: 4, .RegUnits: 16442, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 821 | { .Name: 1067, .SubRegs: 4, .SuperRegs: 3055, .SubRegIndices: 4, .RegUnits: 16443, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 822 | { .Name: 1250, .SubRegs: 4, .SuperRegs: 4336, .SubRegIndices: 4, .RegUnits: 16444, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 823 | { .Name: 1355, .SubRegs: 4, .SuperRegs: 4452, .SubRegIndices: 4, .RegUnits: 16445, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 824 | { .Name: 1461, .SubRegs: 4, .SuperRegs: 5459, .SubRegIndices: 4, .RegUnits: 16446, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 825 | { .Name: 1573, .SubRegs: 4, .SuperRegs: 5502, .SubRegIndices: 4, .RegUnits: 16447, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 826 | { .Name: 1701, .SubRegs: 4, .SuperRegs: 6143, .SubRegIndices: 4, .RegUnits: 16448, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 827 | { .Name: 97, .SubRegs: 4, .SuperRegs: 6366, .SubRegIndices: 4, .RegUnits: 16449, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 828 | { .Name: 243, .SubRegs: 4, .SuperRegs: 21, .SubRegIndices: 4, .RegUnits: 16450, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 829 | { .Name: 134, .SubRegs: 1437, .SuperRegs: 5696, .SubRegIndices: 2, .RegUnits: 16451, .RegUnitLaneMasks: 1, .IsConstant: 1, .IsArtificial: 0 }, |
| 830 | { .Name: 267, .SubRegs: 1437, .SuperRegs: 6422, .SubRegIndices: 2, .RegUnits: 16452, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 831 | { .Name: 895, .SubRegs: 1437, .SuperRegs: 5911, .SubRegIndices: 2, .RegUnits: 16453, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 832 | { .Name: 999, .SubRegs: 1437, .SuperRegs: 5906, .SubRegIndices: 2, .RegUnits: 16454, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 833 | { .Name: 1177, .SubRegs: 1437, .SuperRegs: 5906, .SubRegIndices: 2, .RegUnits: 16455, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 834 | { .Name: 1289, .SubRegs: 1437, .SuperRegs: 5901, .SubRegIndices: 2, .RegUnits: 16456, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 835 | { .Name: 1390, .SubRegs: 1437, .SuperRegs: 5901, .SubRegIndices: 2, .RegUnits: 16457, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 836 | { .Name: 1506, .SubRegs: 1437, .SuperRegs: 5896, .SubRegIndices: 2, .RegUnits: 16458, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 837 | { .Name: 1630, .SubRegs: 1437, .SuperRegs: 5896, .SubRegIndices: 2, .RegUnits: 16459, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 838 | { .Name: 1743, .SubRegs: 1437, .SuperRegs: 5891, .SubRegIndices: 2, .RegUnits: 16460, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 839 | { .Name: 29, .SubRegs: 1437, .SuperRegs: 5891, .SubRegIndices: 2, .RegUnits: 16461, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 840 | { .Name: 171, .SubRegs: 1437, .SuperRegs: 5882, .SubRegIndices: 2, .RegUnits: 16462, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 841 | { .Name: 301, .SubRegs: 1437, .SuperRegs: 5882, .SubRegIndices: 2, .RegUnits: 16463, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 842 | { .Name: 934, .SubRegs: 1437, .SuperRegs: 5836, .SubRegIndices: 2, .RegUnits: 16464, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 843 | { .Name: 1035, .SubRegs: 1437, .SuperRegs: 5836, .SubRegIndices: 2, .RegUnits: 16465, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 844 | { .Name: 1218, .SubRegs: 1437, .SuperRegs: 5819, .SubRegIndices: 2, .RegUnits: 16466, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 845 | { .Name: 1323, .SubRegs: 1437, .SuperRegs: 5819, .SubRegIndices: 2, .RegUnits: 16467, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 846 | { .Name: 1429, .SubRegs: 1437, .SuperRegs: 5802, .SubRegIndices: 2, .RegUnits: 16468, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 847 | { .Name: 1541, .SubRegs: 1437, .SuperRegs: 5802, .SubRegIndices: 2, .RegUnits: 16469, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 848 | { .Name: 1669, .SubRegs: 1437, .SuperRegs: 5785, .SubRegIndices: 2, .RegUnits: 16470, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 849 | { .Name: 65, .SubRegs: 1437, .SuperRegs: 5785, .SubRegIndices: 2, .RegUnits: 16471, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 850 | { .Name: 211, .SubRegs: 1437, .SuperRegs: 5772, .SubRegIndices: 2, .RegUnits: 16472, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 851 | { .Name: 337, .SubRegs: 1437, .SuperRegs: 5772, .SubRegIndices: 2, .RegUnits: 16473, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 852 | { .Name: 974, .SubRegs: 1437, .SuperRegs: 5763, .SubRegIndices: 2, .RegUnits: 16474, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 853 | { .Name: 1071, .SubRegs: 1437, .SuperRegs: 5763, .SubRegIndices: 2, .RegUnits: 16475, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 854 | { .Name: 1258, .SubRegs: 1437, .SuperRegs: 5758, .SubRegIndices: 2, .RegUnits: 16476, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 855 | { .Name: 1359, .SubRegs: 1437, .SuperRegs: 5758, .SubRegIndices: 2, .RegUnits: 16477, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 856 | { .Name: 1469, .SubRegs: 1437, .SuperRegs: 5753, .SubRegIndices: 2, .RegUnits: 16478, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 857 | { .Name: 1577, .SubRegs: 1437, .SuperRegs: 5753, .SubRegIndices: 2, .RegUnits: 16479, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 858 | { .Name: 1709, .SubRegs: 1437, .SuperRegs: 5748, .SubRegIndices: 2, .RegUnits: 16480, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 859 | { .Name: 101, .SubRegs: 1437, .SuperRegs: 5748, .SubRegIndices: 2, .RegUnits: 16481, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 860 | { .Name: 251, .SubRegs: 1437, .SuperRegs: 5743, .SubRegIndices: 2, .RegUnits: 16482, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 861 | { .Name: 1770, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16483, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 862 | { .Name: 1793, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16484, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 863 | { .Name: 1810, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16485, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 864 | { .Name: 1827, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16486, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 865 | { .Name: 1844, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16487, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 866 | { .Name: 1861, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16488, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 867 | { .Name: 1878, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16489, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 868 | { .Name: 1895, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16490, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 869 | { .Name: 1912, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16491, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 870 | { .Name: 1929, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16492, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 871 | { .Name: 1752, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16493, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 872 | { .Name: 1775, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16494, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 873 | { .Name: 1798, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16495, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 874 | { .Name: 1815, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16496, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 875 | { .Name: 1832, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16497, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 876 | { .Name: 1849, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16498, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 877 | { .Name: 1866, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16499, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 878 | { .Name: 1883, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16500, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 879 | { .Name: 1900, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16501, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 880 | { .Name: 1917, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16502, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 881 | { .Name: 1758, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16503, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 882 | { .Name: 1781, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16504, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 883 | { .Name: 1804, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16505, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 884 | { .Name: 1821, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16506, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 885 | { .Name: 1838, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16507, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 886 | { .Name: 1855, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16508, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 887 | { .Name: 1872, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16509, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 888 | { .Name: 1889, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16510, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 889 | { .Name: 1906, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16511, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 890 | { .Name: 1923, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16512, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 891 | { .Name: 1764, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16513, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 892 | { .Name: 1787, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16514, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 893 | { .Name: 1972, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16483, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 894 | { .Name: 1995, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16484, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 895 | { .Name: 2012, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16485, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 896 | { .Name: 2029, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16486, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 897 | { .Name: 2046, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16487, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 898 | { .Name: 2063, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16488, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 899 | { .Name: 2080, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16489, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 900 | { .Name: 2097, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16490, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 901 | { .Name: 2114, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16491, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 902 | { .Name: 2131, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16492, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 903 | { .Name: 1954, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16493, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 904 | { .Name: 1977, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16494, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 905 | { .Name: 2000, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16495, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 906 | { .Name: 2017, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16496, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 907 | { .Name: 2034, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16497, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 908 | { .Name: 2051, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16498, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 909 | { .Name: 2068, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16499, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 910 | { .Name: 2085, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16500, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 911 | { .Name: 2102, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16501, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 912 | { .Name: 2119, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16502, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 913 | { .Name: 1960, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16503, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 914 | { .Name: 1983, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16504, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 915 | { .Name: 2006, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16505, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 916 | { .Name: 2023, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16506, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 917 | { .Name: 2040, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16507, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 918 | { .Name: 2057, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16508, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 919 | { .Name: 2074, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16509, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 920 | { .Name: 2091, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16510, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 921 | { .Name: 2108, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16511, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 922 | { .Name: 2125, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16512, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 923 | { .Name: 1966, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16513, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 924 | { .Name: 1989, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16514, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 925 | { .Name: 2172, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16483, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 926 | { .Name: 2218, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16484, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 927 | { .Name: 2252, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16485, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 928 | { .Name: 2286, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16486, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 929 | { .Name: 2320, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16487, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 930 | { .Name: 2354, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16488, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 931 | { .Name: 2388, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16489, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 932 | { .Name: 2422, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16490, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 933 | { .Name: 2456, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16491, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 934 | { .Name: 2490, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16492, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 935 | { .Name: 2136, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16493, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 936 | { .Name: 2182, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16494, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 937 | { .Name: 2228, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16495, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 938 | { .Name: 2262, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16496, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 939 | { .Name: 2296, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16497, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 940 | { .Name: 2330, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16498, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 941 | { .Name: 2364, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16499, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 942 | { .Name: 2398, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16500, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 943 | { .Name: 2432, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16501, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 944 | { .Name: 2466, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16502, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 945 | { .Name: 2148, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16503, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 946 | { .Name: 2194, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16504, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 947 | { .Name: 2240, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16505, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 948 | { .Name: 2274, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16506, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 949 | { .Name: 2308, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16507, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 950 | { .Name: 2342, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16508, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 951 | { .Name: 2376, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16509, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 952 | { .Name: 2410, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16510, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 953 | { .Name: 2444, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16511, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 954 | { .Name: 2478, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16512, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 955 | { .Name: 2160, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16513, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 956 | { .Name: 2206, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16514, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 957 | { .Name: 2534, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16483, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 958 | { .Name: 2557, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16484, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 959 | { .Name: 2574, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16485, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 960 | { .Name: 2591, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16486, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 961 | { .Name: 2608, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16487, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 962 | { .Name: 2625, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16488, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 963 | { .Name: 2642, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16489, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 964 | { .Name: 2659, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16490, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 965 | { .Name: 2676, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16491, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 966 | { .Name: 2693, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16492, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 967 | { .Name: 2516, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16493, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 968 | { .Name: 2539, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16494, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 969 | { .Name: 2562, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16495, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 970 | { .Name: 2579, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16496, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 971 | { .Name: 2596, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16497, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 972 | { .Name: 2613, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16498, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 973 | { .Name: 2630, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16499, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 974 | { .Name: 2647, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16500, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 975 | { .Name: 2664, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16501, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 976 | { .Name: 2681, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16502, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 977 | { .Name: 2522, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16503, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 978 | { .Name: 2545, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16504, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 979 | { .Name: 2568, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16505, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 980 | { .Name: 2585, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16506, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 981 | { .Name: 2602, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16507, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 982 | { .Name: 2619, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16508, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 983 | { .Name: 2636, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16509, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 984 | { .Name: 2653, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16510, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 985 | { .Name: 2670, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16511, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 986 | { .Name: 2687, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16512, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 987 | { .Name: 2528, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16513, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 988 | { .Name: 2551, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16514, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 989 | { .Name: 2177, .SubRegs: 4, .SuperRegs: 5694, .SubRegIndices: 4, .RegUnits: 16451, .RegUnitLaneMasks: 39, .IsConstant: 1, .IsArtificial: 0 }, |
| 990 | { .Name: 2223, .SubRegs: 4, .SuperRegs: 6420, .SubRegIndices: 4, .RegUnits: 16452, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 991 | { .Name: 2257, .SubRegs: 4, .SuperRegs: 5909, .SubRegIndices: 4, .RegUnits: 16453, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 992 | { .Name: 2291, .SubRegs: 4, .SuperRegs: 5904, .SubRegIndices: 4, .RegUnits: 16454, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 993 | { .Name: 2325, .SubRegs: 4, .SuperRegs: 5904, .SubRegIndices: 4, .RegUnits: 16455, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 994 | { .Name: 2359, .SubRegs: 4, .SuperRegs: 5899, .SubRegIndices: 4, .RegUnits: 16456, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 995 | { .Name: 2393, .SubRegs: 4, .SuperRegs: 5899, .SubRegIndices: 4, .RegUnits: 16457, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 996 | { .Name: 2427, .SubRegs: 4, .SuperRegs: 5894, .SubRegIndices: 4, .RegUnits: 16458, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 997 | { .Name: 2461, .SubRegs: 4, .SuperRegs: 5894, .SubRegIndices: 4, .RegUnits: 16459, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 998 | { .Name: 2495, .SubRegs: 4, .SuperRegs: 5889, .SubRegIndices: 4, .RegUnits: 16460, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 999 | { .Name: 2142, .SubRegs: 4, .SuperRegs: 5889, .SubRegIndices: 4, .RegUnits: 16461, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1000 | { .Name: 2188, .SubRegs: 4, .SuperRegs: 5880, .SubRegIndices: 4, .RegUnits: 16462, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1001 | { .Name: 2234, .SubRegs: 4, .SuperRegs: 5880, .SubRegIndices: 4, .RegUnits: 16463, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1002 | { .Name: 2268, .SubRegs: 4, .SuperRegs: 5834, .SubRegIndices: 4, .RegUnits: 16464, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1003 | { .Name: 2302, .SubRegs: 4, .SuperRegs: 5834, .SubRegIndices: 4, .RegUnits: 16465, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1004 | { .Name: 2336, .SubRegs: 4, .SuperRegs: 5817, .SubRegIndices: 4, .RegUnits: 16466, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1005 | { .Name: 2370, .SubRegs: 4, .SuperRegs: 5817, .SubRegIndices: 4, .RegUnits: 16467, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1006 | { .Name: 2404, .SubRegs: 4, .SuperRegs: 5800, .SubRegIndices: 4, .RegUnits: 16468, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1007 | { .Name: 2438, .SubRegs: 4, .SuperRegs: 5800, .SubRegIndices: 4, .RegUnits: 16469, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1008 | { .Name: 2472, .SubRegs: 4, .SuperRegs: 5783, .SubRegIndices: 4, .RegUnits: 16470, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1009 | { .Name: 2154, .SubRegs: 4, .SuperRegs: 5783, .SubRegIndices: 4, .RegUnits: 16471, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1010 | { .Name: 2200, .SubRegs: 4, .SuperRegs: 5770, .SubRegIndices: 4, .RegUnits: 16472, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1011 | { .Name: 2246, .SubRegs: 4, .SuperRegs: 5770, .SubRegIndices: 4, .RegUnits: 16473, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1012 | { .Name: 2280, .SubRegs: 4, .SuperRegs: 5761, .SubRegIndices: 4, .RegUnits: 16474, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1013 | { .Name: 2314, .SubRegs: 4, .SuperRegs: 5761, .SubRegIndices: 4, .RegUnits: 16475, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1014 | { .Name: 2348, .SubRegs: 4, .SuperRegs: 5756, .SubRegIndices: 4, .RegUnits: 16476, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1015 | { .Name: 2382, .SubRegs: 4, .SuperRegs: 5756, .SubRegIndices: 4, .RegUnits: 16477, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1016 | { .Name: 2416, .SubRegs: 4, .SuperRegs: 5751, .SubRegIndices: 4, .RegUnits: 16478, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1017 | { .Name: 2450, .SubRegs: 4, .SuperRegs: 5751, .SubRegIndices: 4, .RegUnits: 16479, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1018 | { .Name: 2484, .SubRegs: 4, .SuperRegs: 5746, .SubRegIndices: 4, .RegUnits: 16480, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1019 | { .Name: 2166, .SubRegs: 4, .SuperRegs: 5746, .SubRegIndices: 4, .RegUnits: 16481, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1020 | { .Name: 2212, .SubRegs: 4, .SuperRegs: 5741, .SubRegIndices: 4, .RegUnits: 16482, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1021 | { .Name: 3080, .SubRegs: 0, .SuperRegs: 4, .SubRegIndices: 7, .RegUnits: 23343114, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1022 | { .Name: 2734, .SubRegs: 1438, .SuperRegs: 5695, .SubRegIndices: 3, .RegUnits: 16451, .RegUnitLaneMasks: 1, .IsConstant: 1, .IsArtificial: 0 }, |
| 1023 | { .Name: 2757, .SubRegs: 1438, .SuperRegs: 6421, .SubRegIndices: 3, .RegUnits: 16452, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1024 | { .Name: 2774, .SubRegs: 1438, .SuperRegs: 5910, .SubRegIndices: 3, .RegUnits: 16453, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1025 | { .Name: 2791, .SubRegs: 1438, .SuperRegs: 5905, .SubRegIndices: 3, .RegUnits: 16454, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1026 | { .Name: 2808, .SubRegs: 1438, .SuperRegs: 5905, .SubRegIndices: 3, .RegUnits: 16455, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1027 | { .Name: 2825, .SubRegs: 1438, .SuperRegs: 5900, .SubRegIndices: 3, .RegUnits: 16456, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1028 | { .Name: 2842, .SubRegs: 1438, .SuperRegs: 5900, .SubRegIndices: 3, .RegUnits: 16457, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1029 | { .Name: 2859, .SubRegs: 1438, .SuperRegs: 5895, .SubRegIndices: 3, .RegUnits: 16458, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1030 | { .Name: 2876, .SubRegs: 1438, .SuperRegs: 5895, .SubRegIndices: 3, .RegUnits: 16459, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1031 | { .Name: 2893, .SubRegs: 1438, .SuperRegs: 5890, .SubRegIndices: 3, .RegUnits: 16460, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1032 | { .Name: 2716, .SubRegs: 1438, .SuperRegs: 5890, .SubRegIndices: 3, .RegUnits: 16461, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1033 | { .Name: 2739, .SubRegs: 1438, .SuperRegs: 5881, .SubRegIndices: 3, .RegUnits: 16462, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1034 | { .Name: 2762, .SubRegs: 1438, .SuperRegs: 5881, .SubRegIndices: 3, .RegUnits: 16463, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1035 | { .Name: 2779, .SubRegs: 1438, .SuperRegs: 5835, .SubRegIndices: 3, .RegUnits: 16464, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1036 | { .Name: 2796, .SubRegs: 1438, .SuperRegs: 5835, .SubRegIndices: 3, .RegUnits: 16465, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1037 | { .Name: 2813, .SubRegs: 1438, .SuperRegs: 5818, .SubRegIndices: 3, .RegUnits: 16466, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1038 | { .Name: 2830, .SubRegs: 1438, .SuperRegs: 5818, .SubRegIndices: 3, .RegUnits: 16467, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1039 | { .Name: 2847, .SubRegs: 1438, .SuperRegs: 5801, .SubRegIndices: 3, .RegUnits: 16468, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1040 | { .Name: 2864, .SubRegs: 1438, .SuperRegs: 5801, .SubRegIndices: 3, .RegUnits: 16469, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1041 | { .Name: 2881, .SubRegs: 1438, .SuperRegs: 5784, .SubRegIndices: 3, .RegUnits: 16470, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1042 | { .Name: 2722, .SubRegs: 1438, .SuperRegs: 5784, .SubRegIndices: 3, .RegUnits: 16471, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1043 | { .Name: 2745, .SubRegs: 1438, .SuperRegs: 5771, .SubRegIndices: 3, .RegUnits: 16472, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1044 | { .Name: 2768, .SubRegs: 1438, .SuperRegs: 5771, .SubRegIndices: 3, .RegUnits: 16473, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1045 | { .Name: 2785, .SubRegs: 1438, .SuperRegs: 5762, .SubRegIndices: 3, .RegUnits: 16474, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1046 | { .Name: 2802, .SubRegs: 1438, .SuperRegs: 5762, .SubRegIndices: 3, .RegUnits: 16475, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1047 | { .Name: 2819, .SubRegs: 1438, .SuperRegs: 5757, .SubRegIndices: 3, .RegUnits: 16476, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1048 | { .Name: 2836, .SubRegs: 1438, .SuperRegs: 5757, .SubRegIndices: 3, .RegUnits: 16477, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1049 | { .Name: 2853, .SubRegs: 1438, .SuperRegs: 5752, .SubRegIndices: 3, .RegUnits: 16478, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1050 | { .Name: 2870, .SubRegs: 1438, .SuperRegs: 5752, .SubRegIndices: 3, .RegUnits: 16479, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1051 | { .Name: 2887, .SubRegs: 1438, .SuperRegs: 5747, .SubRegIndices: 3, .RegUnits: 16480, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1052 | { .Name: 2728, .SubRegs: 1438, .SuperRegs: 5747, .SubRegIndices: 3, .RegUnits: 16481, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1053 | { .Name: 2751, .SubRegs: 1438, .SuperRegs: 5742, .SubRegIndices: 3, .RegUnits: 16482, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1054 | { .Name: 2916, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16451, .RegUnitLaneMasks: 1, .IsConstant: 1, .IsArtificial: 0 }, |
| 1055 | { .Name: 2939, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16452, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1056 | { .Name: 2956, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16453, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1057 | { .Name: 2973, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16454, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1058 | { .Name: 2990, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16455, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1059 | { .Name: 3007, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16456, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1060 | { .Name: 3024, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16457, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1061 | { .Name: 3041, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16458, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1062 | { .Name: 3058, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16459, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1063 | { .Name: 3075, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16460, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1064 | { .Name: 2898, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16461, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1065 | { .Name: 2921, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16462, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1066 | { .Name: 2944, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16463, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1067 | { .Name: 2961, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16464, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1068 | { .Name: 2978, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16465, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1069 | { .Name: 2995, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16466, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1070 | { .Name: 3012, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16467, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1071 | { .Name: 3029, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16468, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1072 | { .Name: 3046, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16469, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1073 | { .Name: 3063, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16470, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1074 | { .Name: 2904, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16471, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1075 | { .Name: 2927, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16472, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1076 | { .Name: 2950, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16473, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1077 | { .Name: 2967, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16474, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1078 | { .Name: 2984, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16475, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1079 | { .Name: 3001, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16476, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1080 | { .Name: 3018, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16477, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1081 | { .Name: 3035, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16478, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1082 | { .Name: 3052, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16479, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1083 | { .Name: 3069, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16480, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1084 | { .Name: 2910, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16481, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1085 | { .Name: 2933, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16482, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1086 | { .Name: 690, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16483, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1087 | { .Name: 717, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16484, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1088 | { .Name: 737, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16485, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1089 | { .Name: 757, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16486, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1090 | { .Name: 777, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16487, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1091 | { .Name: 797, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16488, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1092 | { .Name: 817, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16489, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1093 | { .Name: 837, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16490, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1094 | { .Name: 857, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16491, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1095 | { .Name: 877, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16492, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1096 | { .Name: 669, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16493, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1097 | { .Name: 696, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16494, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1098 | { .Name: 723, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16495, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1099 | { .Name: 743, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16496, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1100 | { .Name: 763, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16497, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1101 | { .Name: 783, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16498, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1102 | { .Name: 803, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16499, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1103 | { .Name: 823, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16500, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1104 | { .Name: 843, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16501, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1105 | { .Name: 863, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16502, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1106 | { .Name: 676, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16503, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1107 | { .Name: 703, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16504, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1108 | { .Name: 730, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16505, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1109 | { .Name: 750, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16506, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1110 | { .Name: 770, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16507, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1111 | { .Name: 790, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16508, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1112 | { .Name: 810, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16509, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1113 | { .Name: 830, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16510, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1114 | { .Name: 850, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16511, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1115 | { .Name: 870, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16512, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1116 | { .Name: 683, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16513, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1117 | { .Name: 710, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16514, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1118 | { .Name: 410, .SubRegs: 1603, .SuperRegs: 58, .SubRegIndices: 11, .RegUnits: 6467619, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1119 | { .Name: 1087, .SubRegs: 1584, .SuperRegs: 5914, .SubRegIndices: 13, .RegUnits: 6864931, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1120 | { .Name: 1581, .SubRegs: 1591, .SuperRegs: 4, .SubRegIndices: 19, .RegUnits: 6848547, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1121 | { .Name: 466, .SubRegs: 1588, .SuperRegs: 5717, .SubRegIndices: 11, .RegUnits: 6467621, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1122 | { .Name: 528, .SubRegs: 1603, .SuperRegs: 5704, .SubRegIndices: 11, .RegUnits: 6467623, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1123 | { .Name: 1120, .SubRegs: 1599, .SuperRegs: 5685, .SubRegIndices: 13, .RegUnits: 6864935, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1124 | { .Name: 596, .SubRegs: 1603, .SuperRegs: 4610, .SubRegIndices: 11, .RegUnits: 6467625, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1125 | { .Name: 664, .SubRegs: 1625, .SuperRegs: 4624, .SubRegIndices: 11, .RegUnits: 6467627, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1126 | { .Name: 1154, .SubRegs: 1606, .SuperRegs: 2043, .SubRegIndices: 13, .RegUnits: 6864939, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1127 | { .Name: 1598, .SubRegs: 1613, .SuperRegs: 4, .SubRegIndices: 19, .RegUnits: 6848555, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1128 | { .Name: 356, .SubRegs: 1603, .SuperRegs: 4673, .SubRegIndices: 11, .RegUnits: 6467629, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1129 | { .Name: 431, .SubRegs: 1625, .SuperRegs: 4638, .SubRegIndices: 11, .RegUnits: 6467631, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1130 | { .Name: 1097, .SubRegs: 1621, .SuperRegs: 2047, .SubRegIndices: 13, .RegUnits: 6864943, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1131 | { .Name: 488, .SubRegs: 1625, .SuperRegs: 4708, .SubRegIndices: 11, .RegUnits: 6467633, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1132 | { .Name: 551, .SubRegs: 1647, .SuperRegs: 4659, .SubRegIndices: 11, .RegUnits: 6467635, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1133 | { .Name: 1131, .SubRegs: 1628, .SuperRegs: 2035, .SubRegIndices: 13, .RegUnits: 6864947, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1134 | { .Name: 1592, .SubRegs: 1635, .SuperRegs: 4, .SubRegIndices: 19, .RegUnits: 6848563, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1135 | { .Name: 619, .SubRegs: 1625, .SuperRegs: 4743, .SubRegIndices: 11, .RegUnits: 6467637, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1136 | { .Name: 380, .SubRegs: 1647, .SuperRegs: 4694, .SubRegIndices: 11, .RegUnits: 6467639, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1137 | { .Name: 1081, .SubRegs: 1643, .SuperRegs: 2039, .SubRegIndices: 13, .RegUnits: 6864951, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1138 | { .Name: 455, .SubRegs: 1647, .SuperRegs: 4764, .SubRegIndices: 11, .RegUnits: 6467641, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1139 | { .Name: 512, .SubRegs: 1669, .SuperRegs: 4729, .SubRegIndices: 11, .RegUnits: 6467643, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1140 | { .Name: 1109, .SubRegs: 1650, .SuperRegs: 2031, .SubRegIndices: 13, .RegUnits: 6864955, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1141 | { .Name: 1586, .SubRegs: 1657, .SuperRegs: 4, .SubRegIndices: 19, .RegUnits: 6848571, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1142 | { .Name: 575, .SubRegs: 1647, .SuperRegs: 5839, .SubRegIndices: 11, .RegUnits: 6467645, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1143 | { .Name: 643, .SubRegs: 1669, .SuperRegs: 5852, .SubRegIndices: 11, .RegUnits: 6467647, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1144 | { .Name: 1143, .SubRegs: 1665, .SuperRegs: 5701, .SubRegIndices: 13, .RegUnits: 6864959, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1145 | { .Name: 404, .SubRegs: 1669, .SuperRegs: 51, .SubRegIndices: 11, .RegUnits: 6467649, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1146 | { .Name: 996, .SubRegs: 1440, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467653, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1147 | { .Name: 1286, .SubRegs: 1447, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467655, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1148 | { .Name: 1503, .SubRegs: 1454, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467657, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1149 | { .Name: 1740, .SubRegs: 1461, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467659, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1150 | { .Name: 167, .SubRegs: 1468, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467661, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1151 | { .Name: 930, .SubRegs: 1475, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467663, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1152 | { .Name: 1214, .SubRegs: 1482, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467665, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1153 | { .Name: 1425, .SubRegs: 1489, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467667, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1154 | { .Name: 1665, .SubRegs: 1496, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467669, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1155 | { .Name: 207, .SubRegs: 1503, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467671, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1156 | { .Name: 970, .SubRegs: 1510, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467673, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1157 | { .Name: 1254, .SubRegs: 1517, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467675, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1158 | { .Name: 1465, .SubRegs: 1524, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467677, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1159 | { .Name: 1705, .SubRegs: 1531, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467679, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1160 | { .Name: 247, .SubRegs: 1538, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467681, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1161 | { .Name: 889, .SubRegs: 1581, .SuperRegs: 6277, .SubRegIndices: 11, .RegUnits: 6467620, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1162 | { .Name: 990, .SubRegs: 1581, .SuperRegs: 5961, .SubRegIndices: 11, .RegUnits: 6467621, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1163 | { .Name: 1171, .SubRegs: 1581, .SuperRegs: 4951, .SubRegIndices: 11, .RegUnits: 6467622, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1164 | { .Name: 1280, .SubRegs: 1581, .SuperRegs: 4979, .SubRegIndices: 11, .RegUnits: 6467623, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1165 | { .Name: 1384, .SubRegs: 1581, .SuperRegs: 3574, .SubRegIndices: 11, .RegUnits: 6467624, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1166 | { .Name: 1497, .SubRegs: 1581, .SuperRegs: 3325, .SubRegIndices: 11, .RegUnits: 6467625, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1167 | { .Name: 1624, .SubRegs: 1581, .SuperRegs: 2207, .SubRegIndices: 11, .RegUnits: 6467626, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1168 | { .Name: 1734, .SubRegs: 1581, .SuperRegs: 3459, .SubRegIndices: 11, .RegUnits: 6467627, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1169 | { .Name: 22, .SubRegs: 1581, .SuperRegs: 2477, .SubRegIndices: 11, .RegUnits: 6467628, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1170 | { .Name: 159, .SubRegs: 1581, .SuperRegs: 3392, .SubRegIndices: 11, .RegUnits: 6467629, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1171 | { .Name: 293, .SubRegs: 1581, .SuperRegs: 2392, .SubRegIndices: 11, .RegUnits: 6467630, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1172 | { .Name: 922, .SubRegs: 1581, .SuperRegs: 3770, .SubRegIndices: 11, .RegUnits: 6467631, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1173 | { .Name: 1027, .SubRegs: 1581, .SuperRegs: 2748, .SubRegIndices: 11, .RegUnits: 6467632, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1174 | { .Name: 1206, .SubRegs: 1581, .SuperRegs: 3703, .SubRegIndices: 11, .RegUnits: 6467633, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1175 | { .Name: 1315, .SubRegs: 1581, .SuperRegs: 2663, .SubRegIndices: 11, .RegUnits: 6467634, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1176 | { .Name: 1417, .SubRegs: 1581, .SuperRegs: 3981, .SubRegIndices: 11, .RegUnits: 6467635, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1177 | { .Name: 1533, .SubRegs: 1581, .SuperRegs: 3019, .SubRegIndices: 11, .RegUnits: 6467636, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1178 | { .Name: 1657, .SubRegs: 1581, .SuperRegs: 3914, .SubRegIndices: 11, .RegUnits: 6467637, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1179 | { .Name: 57, .SubRegs: 1581, .SuperRegs: 2934, .SubRegIndices: 11, .RegUnits: 6467638, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1180 | { .Name: 199, .SubRegs: 1581, .SuperRegs: 4192, .SubRegIndices: 11, .RegUnits: 6467639, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1181 | { .Name: 329, .SubRegs: 1581, .SuperRegs: 3240, .SubRegIndices: 11, .RegUnits: 6467640, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1182 | { .Name: 962, .SubRegs: 1581, .SuperRegs: 4125, .SubRegIndices: 11, .RegUnits: 6467641, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1183 | { .Name: 1063, .SubRegs: 1581, .SuperRegs: 3155, .SubRegIndices: 11, .RegUnits: 6467642, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1184 | { .Name: 1246, .SubRegs: 1581, .SuperRegs: 4385, .SubRegIndices: 11, .RegUnits: 6467643, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1185 | { .Name: 1351, .SubRegs: 1581, .SuperRegs: 4498, .SubRegIndices: 11, .RegUnits: 6467644, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1186 | { .Name: 1457, .SubRegs: 1581, .SuperRegs: 5400, .SubRegIndices: 11, .RegUnits: 6467645, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1187 | { .Name: 1569, .SubRegs: 1581, .SuperRegs: 5538, .SubRegIndices: 11, .RegUnits: 6467646, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1188 | { .Name: 1697, .SubRegs: 1581, .SuperRegs: 6174, .SubRegIndices: 11, .RegUnits: 6467647, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1189 | { .Name: 93, .SubRegs: 1581, .SuperRegs: 6388, .SubRegIndices: 11, .RegUnits: 6467648, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1190 | { .Name: 239, .SubRegs: 1581, .SuperRegs: 25, .SubRegIndices: 11, .RegUnits: 6467649, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1191 | { .Name: 261, .SubRegs: 1578, .SuperRegs: 25, .SubRegIndices: 11, .RegUnits: 6467619, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1192 | { .Name: 523, .SubRegs: 293, .SuperRegs: 5727, .SubRegIndices: 53, .RegUnits: 6864933, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1193 | { .Name: 591, .SubRegs: 306, .SuperRegs: 5733, .SubRegIndices: 53, .RegUnits: 6864935, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1194 | { .Name: 659, .SubRegs: 332, .SuperRegs: 4652, .SubRegIndices: 53, .RegUnits: 6864937, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1195 | { .Name: 351, .SubRegs: 319, .SuperRegs: 5775, .SubRegIndices: 53, .RegUnits: 6864939, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1196 | { .Name: 425, .SubRegs: 345, .SuperRegs: 4687, .SubRegIndices: 53, .RegUnits: 6864941, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1197 | { .Name: 482, .SubRegs: 358, .SuperRegs: 5788, .SubRegIndices: 53, .RegUnits: 6864943, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1198 | { .Name: 545, .SubRegs: 384, .SuperRegs: 4722, .SubRegIndices: 53, .RegUnits: 6864945, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1199 | { .Name: 613, .SubRegs: 371, .SuperRegs: 5805, .SubRegIndices: 53, .RegUnits: 6864947, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1200 | { .Name: 374, .SubRegs: 397, .SuperRegs: 4757, .SubRegIndices: 53, .RegUnits: 6864949, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1201 | { .Name: 449, .SubRegs: 410, .SuperRegs: 5822, .SubRegIndices: 53, .RegUnits: 6864951, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1202 | { .Name: 506, .SubRegs: 436, .SuperRegs: 4778, .SubRegIndices: 53, .RegUnits: 6864953, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1203 | { .Name: 569, .SubRegs: 423, .SuperRegs: 5868, .SubRegIndices: 53, .RegUnits: 6864955, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1204 | { .Name: 637, .SubRegs: 449, .SuperRegs: 5862, .SubRegIndices: 53, .RegUnits: 6864957, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1205 | { .Name: 398, .SubRegs: 462, .SuperRegs: 54, .SubRegIndices: 53, .RegUnits: 6864959, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1206 | { .Name: 461, .SubRegs: 110, .SuperRegs: 54, .SubRegIndices: 53, .RegUnits: 6864931, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1207 | { .Name: 1149, .SubRegs: 789, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848551, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1208 | { .Name: 1092, .SubRegs: 740, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848555, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1209 | { .Name: 1125, .SubRegs: 691, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848559, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1210 | { .Name: 1075, .SubRegs: 642, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848563, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1211 | { .Name: 1103, .SubRegs: 593, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848567, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1212 | { .Name: 1137, .SubRegs: 544, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848571, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1213 | { .Name: 1115, .SubRegs: 495, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848547, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1214 | { .Name: 987, .SubRegs: 2051, .SuperRegs: 6262, .SubRegIndices: 39, .RegUnits: 6869028, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1215 | { .Name: 1168, .SubRegs: 2051, .SuperRegs: 5986, .SubRegIndices: 39, .RegUnits: 6869029, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1216 | { .Name: 1277, .SubRegs: 2051, .SuperRegs: 5014, .SubRegIndices: 39, .RegUnits: 6869030, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1217 | { .Name: 1381, .SubRegs: 2051, .SuperRegs: 4821, .SubRegIndices: 39, .RegUnits: 6869031, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1218 | { .Name: 1494, .SubRegs: 2051, .SuperRegs: 3609, .SubRegIndices: 39, .RegUnits: 6869032, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1219 | { .Name: 1621, .SubRegs: 2051, .SuperRegs: 3364, .SubRegIndices: 39, .RegUnits: 6869033, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1220 | { .Name: 1731, .SubRegs: 2051, .SuperRegs: 3498, .SubRegIndices: 39, .RegUnits: 6869034, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1221 | { .Name: 19, .SubRegs: 2051, .SuperRegs: 3526, .SubRegIndices: 39, .RegUnits: 6869035, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1222 | { .Name: 156, .SubRegs: 2051, .SuperRegs: 3885, .SubRegIndices: 39, .RegUnits: 6869036, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1223 | { .Name: 289, .SubRegs: 2051, .SuperRegs: 3431, .SubRegIndices: 39, .RegUnits: 6869037, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1224 | { .Name: 918, .SubRegs: 2051, .SuperRegs: 3809, .SubRegIndices: 39, .RegUnits: 6869038, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1225 | { .Name: 1023, .SubRegs: 2051, .SuperRegs: 3837, .SubRegIndices: 39, .RegUnits: 6869039, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1226 | { .Name: 1202, .SubRegs: 2051, .SuperRegs: 4096, .SubRegIndices: 39, .RegUnits: 6869040, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1227 | { .Name: 1311, .SubRegs: 2051, .SuperRegs: 3742, .SubRegIndices: 39, .RegUnits: 6869041, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1228 | { .Name: 1413, .SubRegs: 2051, .SuperRegs: 4020, .SubRegIndices: 39, .RegUnits: 6869042, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1229 | { .Name: 1529, .SubRegs: 2051, .SuperRegs: 4048, .SubRegIndices: 39, .RegUnits: 6869043, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1230 | { .Name: 1653, .SubRegs: 2051, .SuperRegs: 4307, .SubRegIndices: 39, .RegUnits: 6869044, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1231 | { .Name: 53, .SubRegs: 2051, .SuperRegs: 3953, .SubRegIndices: 39, .RegUnits: 6869045, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1232 | { .Name: 195, .SubRegs: 2051, .SuperRegs: 4231, .SubRegIndices: 39, .RegUnits: 6869046, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1233 | { .Name: 325, .SubRegs: 2051, .SuperRegs: 4259, .SubRegIndices: 39, .RegUnits: 6869047, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1234 | { .Name: 958, .SubRegs: 2051, .SuperRegs: 4581, .SubRegIndices: 39, .RegUnits: 6869048, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1235 | { .Name: 1059, .SubRegs: 2051, .SuperRegs: 4164, .SubRegIndices: 39, .RegUnits: 6869049, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1236 | { .Name: 1242, .SubRegs: 2051, .SuperRegs: 4424, .SubRegIndices: 39, .RegUnits: 6869050, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1237 | { .Name: 1347, .SubRegs: 2051, .SuperRegs: 4533, .SubRegIndices: 39, .RegUnits: 6869051, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1238 | { .Name: 1453, .SubRegs: 2051, .SuperRegs: 5566, .SubRegIndices: 39, .RegUnits: 6869052, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1239 | { .Name: 1565, .SubRegs: 2051, .SuperRegs: 5435, .SubRegIndices: 39, .RegUnits: 6869053, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1240 | { .Name: 1693, .SubRegs: 2051, .SuperRegs: 6199, .SubRegIndices: 39, .RegUnits: 6869054, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1241 | { .Name: 89, .SubRegs: 2051, .SuperRegs: 6405, .SubRegIndices: 39, .RegUnits: 6869055, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1242 | { .Name: 235, .SubRegs: 2051, .SuperRegs: 26, .SubRegIndices: 39, .RegUnits: 6869056, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1243 | { .Name: 886, .SubRegs: 1545, .SuperRegs: 26, .SubRegIndices: 39, .RegUnits: 6869027, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1244 | { .Name: 586, .SubRegs: 2004, .SuperRegs: 5713, .SubRegIndices: 161, .RegUnits: 6856741, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1245 | { .Name: 654, .SubRegs: 1977, .SuperRegs: 5766, .SubRegIndices: 161, .RegUnits: 6856743, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1246 | { .Name: 346, .SubRegs: 1950, .SuperRegs: 5796, .SubRegIndices: 161, .RegUnits: 6856745, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1247 | { .Name: 420, .SubRegs: 1923, .SuperRegs: 5779, .SubRegIndices: 161, .RegUnits: 6856747, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1248 | { .Name: 476, .SubRegs: 1896, .SuperRegs: 5813, .SubRegIndices: 161, .RegUnits: 6856749, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1249 | { .Name: 539, .SubRegs: 1869, .SuperRegs: 5792, .SubRegIndices: 161, .RegUnits: 6856751, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1250 | { .Name: 607, .SubRegs: 1842, .SuperRegs: 5830, .SubRegIndices: 161, .RegUnits: 6856753, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1251 | { .Name: 368, .SubRegs: 1815, .SuperRegs: 5809, .SubRegIndices: 161, .RegUnits: 6856755, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1252 | { .Name: 443, .SubRegs: 1788, .SuperRegs: 5876, .SubRegIndices: 161, .RegUnits: 6856757, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1253 | { .Name: 500, .SubRegs: 1761, .SuperRegs: 5826, .SubRegIndices: 161, .RegUnits: 6856759, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1254 | { .Name: 563, .SubRegs: 1734, .SuperRegs: 5885, .SubRegIndices: 161, .RegUnits: 6856761, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1255 | { .Name: 631, .SubRegs: 1707, .SuperRegs: 5872, .SubRegIndices: 161, .RegUnits: 6856763, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1256 | { .Name: 392, .SubRegs: 1680, .SuperRegs: 33, .SubRegIndices: 161, .RegUnits: 6856765, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1257 | { .Name: 518, .SubRegs: 1551, .SuperRegs: 33, .SubRegIndices: 161, .RegUnits: 6856739, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1258 | { .Name: 1165, .SubRegs: 485, .SuperRegs: 6265, .SubRegIndices: 44, .RegUnits: 6864932, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1259 | { .Name: 1274, .SubRegs: 485, .SuperRegs: 6007, .SubRegIndices: 44, .RegUnits: 6864933, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1260 | { .Name: 1378, .SubRegs: 485, .SuperRegs: 4831, .SubRegIndices: 44, .RegUnits: 6864934, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1261 | { .Name: 1491, .SubRegs: 485, .SuperRegs: 4849, .SubRegIndices: 44, .RegUnits: 6864935, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1262 | { .Name: 1618, .SubRegs: 485, .SuperRegs: 3684, .SubRegIndices: 44, .RegUnits: 6864936, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1263 | { .Name: 1728, .SubRegs: 485, .SuperRegs: 4785, .SubRegIndices: 44, .RegUnits: 6864937, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1264 | { .Name: 16, .SubRegs: 485, .SuperRegs: 3555, .SubRegIndices: 44, .RegUnits: 6864938, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1265 | { .Name: 153, .SubRegs: 485, .SuperRegs: 5088, .SubRegIndices: 44, .RegUnits: 6864939, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1266 | { .Name: 286, .SubRegs: 485, .SuperRegs: 3895, .SubRegIndices: 44, .RegUnits: 6864940, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1267 | { .Name: 914, .SubRegs: 485, .SuperRegs: 5052, .SubRegIndices: 44, .RegUnits: 6864941, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1268 | { .Name: 1019, .SubRegs: 485, .SuperRegs: 3866, .SubRegIndices: 44, .RegUnits: 6864942, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1269 | { .Name: 1198, .SubRegs: 485, .SuperRegs: 5175, .SubRegIndices: 44, .RegUnits: 6864943, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1270 | { .Name: 1307, .SubRegs: 485, .SuperRegs: 4106, .SubRegIndices: 44, .RegUnits: 6864944, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1271 | { .Name: 1409, .SubRegs: 485, .SuperRegs: 5139, .SubRegIndices: 44, .RegUnits: 6864945, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1272 | { .Name: 1525, .SubRegs: 485, .SuperRegs: 4077, .SubRegIndices: 44, .RegUnits: 6864946, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1273 | { .Name: 1649, .SubRegs: 485, .SuperRegs: 5262, .SubRegIndices: 44, .RegUnits: 6864947, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1274 | { .Name: 49, .SubRegs: 485, .SuperRegs: 4317, .SubRegIndices: 44, .RegUnits: 6864948, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1275 | { .Name: 191, .SubRegs: 485, .SuperRegs: 5226, .SubRegIndices: 44, .RegUnits: 6864949, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1276 | { .Name: 321, .SubRegs: 485, .SuperRegs: 4288, .SubRegIndices: 44, .RegUnits: 6864950, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1277 | { .Name: 954, .SubRegs: 485, .SuperRegs: 5349, .SubRegIndices: 44, .RegUnits: 6864951, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1278 | { .Name: 1055, .SubRegs: 485, .SuperRegs: 4591, .SubRegIndices: 44, .RegUnits: 6864952, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1279 | { .Name: 1238, .SubRegs: 485, .SuperRegs: 5313, .SubRegIndices: 44, .RegUnits: 6864953, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1280 | { .Name: 1343, .SubRegs: 485, .SuperRegs: 4562, .SubRegIndices: 44, .RegUnits: 6864954, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1281 | { .Name: 1449, .SubRegs: 485, .SuperRegs: 5594, .SubRegIndices: 44, .RegUnits: 6864955, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1282 | { .Name: 1561, .SubRegs: 485, .SuperRegs: 5576, .SubRegIndices: 44, .RegUnits: 6864956, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1283 | { .Name: 1689, .SubRegs: 485, .SuperRegs: 6125, .SubRegIndices: 44, .RegUnits: 6864957, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1284 | { .Name: 85, .SubRegs: 485, .SuperRegs: 6376, .SubRegIndices: 44, .RegUnits: 6864958, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1285 | { .Name: 231, .SubRegs: 485, .SuperRegs: 27, .SubRegIndices: 44, .RegUnits: 6864959, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1286 | { .Name: 984, .SubRegs: 475, .SuperRegs: 27, .SubRegIndices: 44, .RegUnits: 6864931, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1287 | { .Name: 649, .SubRegs: 1390, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848549, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1288 | { .Name: 341, .SubRegs: 1344, .SuperRegs: 78, .SubRegIndices: 187, .RegUnits: 6848551, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1289 | { .Name: 415, .SubRegs: 1298, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848553, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1290 | { .Name: 471, .SubRegs: 1252, .SuperRegs: 75, .SubRegIndices: 187, .RegUnits: 6848555, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1291 | { .Name: 533, .SubRegs: 1206, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848557, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1292 | { .Name: 601, .SubRegs: 1160, .SuperRegs: 72, .SubRegIndices: 187, .RegUnits: 6848559, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1293 | { .Name: 362, .SubRegs: 1114, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848561, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1294 | { .Name: 437, .SubRegs: 1068, .SuperRegs: 69, .SubRegIndices: 187, .RegUnits: 6848563, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1295 | { .Name: 494, .SubRegs: 1022, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848565, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1296 | { .Name: 557, .SubRegs: 976, .SuperRegs: 66, .SubRegIndices: 187, .RegUnits: 6848567, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1297 | { .Name: 625, .SubRegs: 930, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848569, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1298 | { .Name: 386, .SubRegs: 884, .SuperRegs: 19, .SubRegIndices: 187, .RegUnits: 6848571, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1299 | { .Name: 581, .SubRegs: 838, .SuperRegs: 19, .SubRegIndices: 187, .RegUnits: 6848547, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1300 | { .Name: 1271, .SubRegs: 95, .SuperRegs: 6267, .SubRegIndices: 65, .RegUnits: 6860836, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1301 | { .Name: 1375, .SubRegs: 95, .SuperRegs: 5917, .SubRegIndices: 65, .RegUnits: 6860837, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1302 | { .Name: 1488, .SubRegs: 95, .SuperRegs: 4835, .SubRegIndices: 65, .RegUnits: 6860838, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1303 | { .Name: 1615, .SubRegs: 95, .SuperRegs: 5038, .SubRegIndices: 65, .RegUnits: 6860839, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1304 | { .Name: 1725, .SubRegs: 95, .SuperRegs: 5125, .SubRegIndices: 65, .RegUnits: 6860840, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1305 | { .Name: 13, .SubRegs: 95, .SuperRegs: 4807, .SubRegIndices: 65, .RegUnits: 6860841, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1306 | { .Name: 150, .SubRegs: 95, .SuperRegs: 5111, .SubRegIndices: 65, .RegUnits: 6860842, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1307 | { .Name: 283, .SubRegs: 95, .SuperRegs: 5097, .SubRegIndices: 65, .RegUnits: 6860843, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1308 | { .Name: 911, .SubRegs: 95, .SuperRegs: 5212, .SubRegIndices: 65, .RegUnits: 6860844, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1309 | { .Name: 1015, .SubRegs: 95, .SuperRegs: 5074, .SubRegIndices: 65, .RegUnits: 6860845, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1310 | { .Name: 1194, .SubRegs: 95, .SuperRegs: 5198, .SubRegIndices: 65, .RegUnits: 6860846, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1311 | { .Name: 1303, .SubRegs: 95, .SuperRegs: 5184, .SubRegIndices: 65, .RegUnits: 6860847, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1312 | { .Name: 1405, .SubRegs: 95, .SuperRegs: 5299, .SubRegIndices: 65, .RegUnits: 6860848, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1313 | { .Name: 1521, .SubRegs: 95, .SuperRegs: 5161, .SubRegIndices: 65, .RegUnits: 6860849, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1314 | { .Name: 1645, .SubRegs: 95, .SuperRegs: 5285, .SubRegIndices: 65, .RegUnits: 6860850, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1315 | { .Name: 45, .SubRegs: 95, .SuperRegs: 5271, .SubRegIndices: 65, .RegUnits: 6860851, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1316 | { .Name: 187, .SubRegs: 95, .SuperRegs: 5386, .SubRegIndices: 65, .RegUnits: 6860852, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1317 | { .Name: 317, .SubRegs: 95, .SuperRegs: 5248, .SubRegIndices: 65, .RegUnits: 6860853, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1318 | { .Name: 950, .SubRegs: 95, .SuperRegs: 5372, .SubRegIndices: 65, .RegUnits: 6860854, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1319 | { .Name: 1051, .SubRegs: 95, .SuperRegs: 5358, .SubRegIndices: 65, .RegUnits: 6860855, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1320 | { .Name: 1234, .SubRegs: 95, .SuperRegs: 5631, .SubRegIndices: 65, .RegUnits: 6860856, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1321 | { .Name: 1339, .SubRegs: 95, .SuperRegs: 5335, .SubRegIndices: 65, .RegUnits: 6860857, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1322 | { .Name: 1445, .SubRegs: 95, .SuperRegs: 5617, .SubRegIndices: 65, .RegUnits: 6860858, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1323 | { .Name: 1557, .SubRegs: 95, .SuperRegs: 5603, .SubRegIndices: 65, .RegUnits: 6860859, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1324 | { .Name: 1685, .SubRegs: 95, .SuperRegs: 6220, .SubRegIndices: 65, .RegUnits: 6860860, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1325 | { .Name: 81, .SubRegs: 95, .SuperRegs: 6356, .SubRegIndices: 65, .RegUnits: 6860861, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1326 | { .Name: 227, .SubRegs: 95, .SuperRegs: 29, .SubRegIndices: 65, .RegUnits: 6860862, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1327 | { .Name: 1162, .SubRegs: 80, .SuperRegs: 29, .SubRegIndices: 65, .RegUnits: 6860835, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1328 | { .Name: 1372, .SubRegs: 144, .SuperRegs: 6248, .SubRegIndices: 79, .RegUnits: 6856740, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1329 | { .Name: 1485, .SubRegs: 144, .SuperRegs: 5920, .SubRegIndices: 79, .RegUnits: 6856741, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1330 | { .Name: 1612, .SubRegs: 144, .SuperRegs: 4842, .SubRegIndices: 79, .RegUnits: 6856742, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1331 | { .Name: 1722, .SubRegs: 144, .SuperRegs: 6035, .SubRegIndices: 79, .RegUnits: 6856743, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1332 | { .Name: 10, .SubRegs: 144, .SuperRegs: 5645, .SubRegIndices: 79, .RegUnits: 6856744, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1333 | { .Name: 147, .SubRegs: 144, .SuperRegs: 6025, .SubRegIndices: 79, .RegUnits: 6856745, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1334 | { .Name: 280, .SubRegs: 144, .SuperRegs: 5104, .SubRegIndices: 79, .RegUnits: 6856746, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1335 | { .Name: 908, .SubRegs: 144, .SuperRegs: 6055, .SubRegIndices: 79, .RegUnits: 6856747, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1336 | { .Name: 1012, .SubRegs: 144, .SuperRegs: 5653, .SubRegIndices: 79, .RegUnits: 6856748, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1337 | { .Name: 1190, .SubRegs: 144, .SuperRegs: 6045, .SubRegIndices: 79, .RegUnits: 6856749, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1338 | { .Name: 1299, .SubRegs: 144, .SuperRegs: 5191, .SubRegIndices: 79, .RegUnits: 6856750, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1339 | { .Name: 1401, .SubRegs: 144, .SuperRegs: 6075, .SubRegIndices: 79, .RegUnits: 6856751, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1340 | { .Name: 1517, .SubRegs: 144, .SuperRegs: 5661, .SubRegIndices: 79, .RegUnits: 6856752, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1341 | { .Name: 1641, .SubRegs: 144, .SuperRegs: 6065, .SubRegIndices: 79, .RegUnits: 6856753, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1342 | { .Name: 41, .SubRegs: 144, .SuperRegs: 5278, .SubRegIndices: 79, .RegUnits: 6856754, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1343 | { .Name: 183, .SubRegs: 144, .SuperRegs: 6095, .SubRegIndices: 79, .RegUnits: 6856755, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1344 | { .Name: 313, .SubRegs: 144, .SuperRegs: 5669, .SubRegIndices: 79, .RegUnits: 6856756, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1345 | { .Name: 946, .SubRegs: 144, .SuperRegs: 6085, .SubRegIndices: 79, .RegUnits: 6856757, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1346 | { .Name: 1047, .SubRegs: 144, .SuperRegs: 5365, .SubRegIndices: 79, .RegUnits: 6856758, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1347 | { .Name: 1230, .SubRegs: 144, .SuperRegs: 6115, .SubRegIndices: 79, .RegUnits: 6856759, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1348 | { .Name: 1335, .SubRegs: 144, .SuperRegs: 5677, .SubRegIndices: 79, .RegUnits: 6856760, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1349 | { .Name: 1441, .SubRegs: 144, .SuperRegs: 6105, .SubRegIndices: 79, .RegUnits: 6856761, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1350 | { .Name: 1553, .SubRegs: 144, .SuperRegs: 5428, .SubRegIndices: 79, .RegUnits: 6856762, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1351 | { .Name: 1681, .SubRegs: 144, .SuperRegs: 6233, .SubRegIndices: 79, .RegUnits: 6856763, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1352 | { .Name: 77, .SubRegs: 144, .SuperRegs: 6344, .SubRegIndices: 79, .RegUnits: 6856764, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1353 | { .Name: 223, .SubRegs: 144, .SuperRegs: 30, .SubRegIndices: 79, .RegUnits: 6856765, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1354 | { .Name: 1268, .SubRegs: 123, .SuperRegs: 30, .SubRegIndices: 79, .RegUnits: 6856739, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1355 | { .Name: 1482, .SubRegs: 193, .SuperRegs: 6250, .SubRegIndices: 99, .RegUnits: 6852644, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1356 | { .Name: 1609, .SubRegs: 193, .SuperRegs: 5926, .SubRegIndices: 99, .RegUnits: 6852645, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1357 | { .Name: 1719, .SubRegs: 193, .SuperRegs: 6041, .SubRegIndices: 99, .RegUnits: 6852646, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1358 | { .Name: 7, .SubRegs: 193, .SuperRegs: 6294, .SubRegIndices: 99, .RegUnits: 6852647, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1359 | { .Name: 144, .SubRegs: 193, .SuperRegs: 6299, .SubRegIndices: 99, .RegUnits: 6852648, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1360 | { .Name: 277, .SubRegs: 193, .SuperRegs: 6031, .SubRegIndices: 99, .RegUnits: 6852649, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1361 | { .Name: 905, .SubRegs: 193, .SuperRegs: 6061, .SubRegIndices: 99, .RegUnits: 6852650, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1362 | { .Name: 1009, .SubRegs: 193, .SuperRegs: 6304, .SubRegIndices: 99, .RegUnits: 6852651, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1363 | { .Name: 1187, .SubRegs: 193, .SuperRegs: 6309, .SubRegIndices: 99, .RegUnits: 6852652, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1364 | { .Name: 1295, .SubRegs: 193, .SuperRegs: 6051, .SubRegIndices: 99, .RegUnits: 6852653, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1365 | { .Name: 1397, .SubRegs: 193, .SuperRegs: 6081, .SubRegIndices: 99, .RegUnits: 6852654, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1366 | { .Name: 1513, .SubRegs: 193, .SuperRegs: 6314, .SubRegIndices: 99, .RegUnits: 6852655, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1367 | { .Name: 1637, .SubRegs: 193, .SuperRegs: 6319, .SubRegIndices: 99, .RegUnits: 6852656, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1368 | { .Name: 37, .SubRegs: 193, .SuperRegs: 6071, .SubRegIndices: 99, .RegUnits: 6852657, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1369 | { .Name: 179, .SubRegs: 193, .SuperRegs: 6101, .SubRegIndices: 99, .RegUnits: 6852658, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1370 | { .Name: 309, .SubRegs: 193, .SuperRegs: 6324, .SubRegIndices: 99, .RegUnits: 6852659, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1371 | { .Name: 942, .SubRegs: 193, .SuperRegs: 6329, .SubRegIndices: 99, .RegUnits: 6852660, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1372 | { .Name: 1043, .SubRegs: 193, .SuperRegs: 6091, .SubRegIndices: 99, .RegUnits: 6852661, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1373 | { .Name: 1226, .SubRegs: 193, .SuperRegs: 6121, .SubRegIndices: 99, .RegUnits: 6852662, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1374 | { .Name: 1331, .SubRegs: 193, .SuperRegs: 6334, .SubRegIndices: 99, .RegUnits: 6852663, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1375 | { .Name: 1437, .SubRegs: 193, .SuperRegs: 6339, .SubRegIndices: 99, .RegUnits: 6852664, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1376 | { .Name: 1549, .SubRegs: 193, .SuperRegs: 6111, .SubRegIndices: 99, .RegUnits: 6852665, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1377 | { .Name: 1677, .SubRegs: 193, .SuperRegs: 6139, .SubRegIndices: 99, .RegUnits: 6852666, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1378 | { .Name: 73, .SubRegs: 193, .SuperRegs: 6351, .SubRegIndices: 99, .RegUnits: 6852667, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1379 | { .Name: 219, .SubRegs: 193, .SuperRegs: 17, .SubRegIndices: 99, .RegUnits: 6852668, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1380 | { .Name: 1369, .SubRegs: 165, .SuperRegs: 17, .SubRegIndices: 99, .RegUnits: 6852643, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1381 | { .Name: 1606, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848548, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1382 | { .Name: 1716, .SubRegs: 257, .SuperRegs: 15, .SubRegIndices: 126, .RegUnits: 6848549, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1383 | { .Name: 4, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848550, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1384 | { .Name: 141, .SubRegs: 257, .SuperRegs: 77, .SubRegIndices: 126, .RegUnits: 6848551, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1385 | { .Name: 274, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848552, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1386 | { .Name: 902, .SubRegs: 257, .SuperRegs: 13, .SubRegIndices: 126, .RegUnits: 6848553, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1387 | { .Name: 1006, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848554, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1388 | { .Name: 1184, .SubRegs: 257, .SuperRegs: 74, .SubRegIndices: 126, .RegUnits: 6848555, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1389 | { .Name: 1292, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848556, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1390 | { .Name: 1393, .SubRegs: 257, .SuperRegs: 11, .SubRegIndices: 126, .RegUnits: 6848557, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1391 | { .Name: 1509, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848558, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1392 | { .Name: 1633, .SubRegs: 257, .SuperRegs: 71, .SubRegIndices: 126, .RegUnits: 6848559, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1393 | { .Name: 33, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848560, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1394 | { .Name: 175, .SubRegs: 257, .SuperRegs: 9, .SubRegIndices: 126, .RegUnits: 6848561, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1395 | { .Name: 305, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848562, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1396 | { .Name: 938, .SubRegs: 257, .SuperRegs: 68, .SubRegIndices: 126, .RegUnits: 6848563, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1397 | { .Name: 1039, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848564, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1398 | { .Name: 1222, .SubRegs: 257, .SuperRegs: 7, .SubRegIndices: 126, .RegUnits: 6848565, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1399 | { .Name: 1327, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848566, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1400 | { .Name: 1433, .SubRegs: 257, .SuperRegs: 65, .SubRegIndices: 126, .RegUnits: 6848567, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1401 | { .Name: 1545, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848568, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1402 | { .Name: 1673, .SubRegs: 257, .SuperRegs: 5, .SubRegIndices: 126, .RegUnits: 6848569, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1403 | { .Name: 69, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848570, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1404 | { .Name: 215, .SubRegs: 257, .SuperRegs: 18, .SubRegIndices: 126, .RegUnits: 6848571, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1405 | { .Name: 1479, .SubRegs: 221, .SuperRegs: 18, .SubRegIndices: 126, .RegUnits: 6848547, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1406 | }; |
| 1407 | |
| 1408 | extern const MCPhysReg RISCVRegUnitRoots[][2] = { |
| 1409 | { RISCV::FCSR }, |
| 1410 | { RISCV::FFLAGS }, |
| 1411 | { RISCV::FRM }, |
| 1412 | { RISCV::SF_VCIX_STATE }, |
| 1413 | { RISCV::SSP }, |
| 1414 | { RISCV::VL }, |
| 1415 | { RISCV::VLENB }, |
| 1416 | { RISCV::VTYPE }, |
| 1417 | { RISCV::VXRM }, |
| 1418 | { RISCV::VXSAT }, |
| 1419 | { RISCV::DUMMY_REG_PAIR_WITH_X0 }, |
| 1420 | { RISCV::M0 }, |
| 1421 | { RISCV::M1 }, |
| 1422 | { RISCV::M2 }, |
| 1423 | { RISCV::M3 }, |
| 1424 | { RISCV::M4 }, |
| 1425 | { RISCV::M5 }, |
| 1426 | { RISCV::M6 }, |
| 1427 | { RISCV::M7 }, |
| 1428 | { RISCV::T0 }, |
| 1429 | { RISCV::T1 }, |
| 1430 | { RISCV::T2 }, |
| 1431 | { RISCV::T3 }, |
| 1432 | { RISCV::T4 }, |
| 1433 | { RISCV::T5 }, |
| 1434 | { RISCV::T6 }, |
| 1435 | { RISCV::T7 }, |
| 1436 | { RISCV::T8 }, |
| 1437 | { RISCV::T9 }, |
| 1438 | { RISCV::T10 }, |
| 1439 | { RISCV::T11 }, |
| 1440 | { RISCV::T12 }, |
| 1441 | { RISCV::T13 }, |
| 1442 | { RISCV::T14 }, |
| 1443 | { RISCV::T15 }, |
| 1444 | { RISCV::V0 }, |
| 1445 | { RISCV::V1 }, |
| 1446 | { RISCV::V2 }, |
| 1447 | { RISCV::V3 }, |
| 1448 | { RISCV::V4 }, |
| 1449 | { RISCV::V5 }, |
| 1450 | { RISCV::V6 }, |
| 1451 | { RISCV::V7 }, |
| 1452 | { RISCV::V8 }, |
| 1453 | { RISCV::V9 }, |
| 1454 | { RISCV::V10 }, |
| 1455 | { RISCV::V11 }, |
| 1456 | { RISCV::V12 }, |
| 1457 | { RISCV::V13 }, |
| 1458 | { RISCV::V14 }, |
| 1459 | { RISCV::V15 }, |
| 1460 | { RISCV::V16 }, |
| 1461 | { RISCV::V17 }, |
| 1462 | { RISCV::V18 }, |
| 1463 | { RISCV::V19 }, |
| 1464 | { RISCV::V20 }, |
| 1465 | { RISCV::V21 }, |
| 1466 | { RISCV::V22 }, |
| 1467 | { RISCV::V23 }, |
| 1468 | { RISCV::V24 }, |
| 1469 | { RISCV::V25 }, |
| 1470 | { RISCV::V26 }, |
| 1471 | { RISCV::V27 }, |
| 1472 | { RISCV::V28 }, |
| 1473 | { RISCV::V29 }, |
| 1474 | { RISCV::V30 }, |
| 1475 | { RISCV::V31 }, |
| 1476 | { RISCV::X0_H }, |
| 1477 | { RISCV::X1_H }, |
| 1478 | { RISCV::X2_H }, |
| 1479 | { RISCV::X3_H }, |
| 1480 | { RISCV::X4_H }, |
| 1481 | { RISCV::X5_H }, |
| 1482 | { RISCV::X6_H }, |
| 1483 | { RISCV::X7_H }, |
| 1484 | { RISCV::X8_H }, |
| 1485 | { RISCV::X9_H }, |
| 1486 | { RISCV::X10_H }, |
| 1487 | { RISCV::X11_H }, |
| 1488 | { RISCV::X12_H }, |
| 1489 | { RISCV::X13_H }, |
| 1490 | { RISCV::X14_H }, |
| 1491 | { RISCV::X15_H }, |
| 1492 | { RISCV::X16_H }, |
| 1493 | { RISCV::X17_H }, |
| 1494 | { RISCV::X18_H }, |
| 1495 | { RISCV::X19_H }, |
| 1496 | { RISCV::X20_H }, |
| 1497 | { RISCV::X21_H }, |
| 1498 | { RISCV::X22_H }, |
| 1499 | { RISCV::X23_H }, |
| 1500 | { RISCV::X24_H }, |
| 1501 | { RISCV::X25_H }, |
| 1502 | { RISCV::X26_H }, |
| 1503 | { RISCV::X27_H }, |
| 1504 | { RISCV::X28_H }, |
| 1505 | { RISCV::X29_H }, |
| 1506 | { RISCV::X30_H }, |
| 1507 | { RISCV::X31_H }, |
| 1508 | { RISCV::F0_H }, |
| 1509 | { RISCV::F1_H }, |
| 1510 | { RISCV::F2_H }, |
| 1511 | { RISCV::F3_H }, |
| 1512 | { RISCV::F4_H }, |
| 1513 | { RISCV::F5_H }, |
| 1514 | { RISCV::F6_H }, |
| 1515 | { RISCV::F7_H }, |
| 1516 | { RISCV::F8_H }, |
| 1517 | { RISCV::F9_H }, |
| 1518 | { RISCV::F10_H }, |
| 1519 | { RISCV::F11_H }, |
| 1520 | { RISCV::F12_H }, |
| 1521 | { RISCV::F13_H }, |
| 1522 | { RISCV::F14_H }, |
| 1523 | { RISCV::F15_H }, |
| 1524 | { RISCV::F16_H }, |
| 1525 | { RISCV::F17_H }, |
| 1526 | { RISCV::F18_H }, |
| 1527 | { RISCV::F19_H }, |
| 1528 | { RISCV::F20_H }, |
| 1529 | { RISCV::F21_H }, |
| 1530 | { RISCV::F22_H }, |
| 1531 | { RISCV::F23_H }, |
| 1532 | { RISCV::F24_H }, |
| 1533 | { RISCV::F25_H }, |
| 1534 | { RISCV::F26_H }, |
| 1535 | { RISCV::F27_H }, |
| 1536 | { RISCV::F28_H }, |
| 1537 | { RISCV::F29_H }, |
| 1538 | { RISCV::F30_H }, |
| 1539 | { RISCV::F31_H }, |
| 1540 | }; |
| 1541 | |
| 1542 | // Register classes... |
| 1543 | |
| 1544 | #ifdef __GNUC__ |
| 1545 | #pragma GCC diagnostic push |
| 1546 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 1547 | #endif |
| 1548 | extern const char RISCVRegClassStrings[] = { |
| 1549 | /* 0 */ "MR0\000" |
| 1550 | /* 4 */ "VRN2M1_with_sub_vrm1_0_in_VMV0\000" |
| 1551 | /* 35 */ "VRN3M1_with_sub_vrm1_0_in_VMV0\000" |
| 1552 | /* 66 */ "VRN4M1_with_sub_vrm1_0_in_VMV0\000" |
| 1553 | /* 97 */ "VRN5M1_with_sub_vrm1_0_in_VMV0\000" |
| 1554 | /* 128 */ "VRN6M1_with_sub_vrm1_0_in_VMV0\000" |
| 1555 | /* 159 */ "VRN7M1_with_sub_vrm1_0_in_VMV0\000" |
| 1556 | /* 190 */ "VRN8M1_with_sub_vrm1_0_in_VMV0\000" |
| 1557 | /* 221 */ "VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0\000" |
| 1558 | /* 276 */ "VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0\000" |
| 1559 | /* 331 */ "VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0\000" |
| 1560 | /* 386 */ "VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0\000" |
| 1561 | /* 441 */ "VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0\000" |
| 1562 | /* 494 */ "VRN2M1NoV0\000" |
| 1563 | /* 505 */ "VRN3M1NoV0\000" |
| 1564 | /* 516 */ "VRN4M1NoV0\000" |
| 1565 | /* 527 */ "VRN5M1NoV0\000" |
| 1566 | /* 538 */ "VRN6M1NoV0\000" |
| 1567 | /* 549 */ "VRN7M1NoV0\000" |
| 1568 | /* 560 */ "VRN8M1NoV0\000" |
| 1569 | /* 571 */ "ZZZ_VRMF2NoV0\000" |
| 1570 | /* 585 */ "VRN2M2NoV0\000" |
| 1571 | /* 596 */ "VRN3M2NoV0\000" |
| 1572 | /* 607 */ "VRN4M2NoV0\000" |
| 1573 | /* 618 */ "VRM2NoV0\000" |
| 1574 | /* 627 */ "ZZZ_VRMF4NoV0\000" |
| 1575 | /* 641 */ "VRN2M4NoV0\000" |
| 1576 | /* 652 */ "VRM4NoV0\000" |
| 1577 | /* 661 */ "ZZZ_VRMF8NoV0\000" |
| 1578 | /* 675 */ "VRM8NoV0\000" |
| 1579 | /* 684 */ "ZZZ_VMNoV0\000" |
| 1580 | /* 695 */ "VRNoV0\000" |
| 1581 | /* 702 */ "GPRF32X0\000" |
| 1582 | /* 711 */ "YGPR_with_sub_16_in_GPRF16X0\000" |
| 1583 | /* 740 */ "GPRPair_with_sub_16_in_GPRF16X0\000" |
| 1584 | /* 772 */ "GPRX0\000" |
| 1585 | /* 778 */ "GPRF32NoX0\000" |
| 1586 | /* 789 */ "YGPR_with_sub_16_in_GPRF16NoX0\000" |
| 1587 | /* 820 */ "GPRNoX0\000" |
| 1588 | /* 828 */ "GPRPairNoX0\000" |
| 1589 | /* 840 */ "YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31\000" |
| 1590 | /* 887 */ "YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31\000" |
| 1591 | /* 936 */ "YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31\000" |
| 1592 | /* 983 */ "GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31\000" |
| 1593 | /* 1037 */ "YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31\000" |
| 1594 | /* 1089 */ "GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31\000" |
| 1595 | /* 1138 */ "YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31\000" |
| 1596 | /* 1185 */ "GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31\000" |
| 1597 | /* 1265 */ "YGPR_with_sub_cap_addr_in_GPRNoX31\000" |
| 1598 | /* 1300 */ "anonymous_15061\000" |
| 1599 | /* 1316 */ "VRN2M1\000" |
| 1600 | /* 1323 */ "VRN3M1\000" |
| 1601 | /* 1330 */ "VRN4M1\000" |
| 1602 | /* 1337 */ "VRN5M1\000" |
| 1603 | /* 1344 */ "VRN6M1\000" |
| 1604 | /* 1351 */ "VRN7M1\000" |
| 1605 | /* 1358 */ "VRN8M1\000" |
| 1606 | /* 1365 */ "YGPR_with_sub_cap_addr_in_GPRX1\000" |
| 1607 | /* 1397 */ "GPRF32\000" |
| 1608 | /* 1404 */ "FPR32\000" |
| 1609 | /* 1410 */ "ZZZ_VRMF2\000" |
| 1610 | /* 1420 */ "VRN2M2\000" |
| 1611 | /* 1427 */ "VRN3M2\000" |
| 1612 | /* 1434 */ "VRN4M2\000" |
| 1613 | /* 1441 */ "TRM2\000" |
| 1614 | /* 1446 */ "VRM2\000" |
| 1615 | /* 1451 */ "GPRPair_with_sub_gpr_even_in_GPRNoX0X2\000" |
| 1616 | /* 1490 */ "YGPR_with_sub_cap_addr_in_GPRNoX0X2\000" |
| 1617 | /* 1526 */ "GPRPair_with_sub_gpr_even_in_GPRNoX2\000" |
| 1618 | /* 1563 */ "YGPR_with_sub_cap_addr_in_GPRNoX2\000" |
| 1619 | /* 1597 */ "FPR64\000" |
| 1620 | /* 1603 */ "ZZZ_VRMF4\000" |
| 1621 | /* 1613 */ "VRN2M4\000" |
| 1622 | /* 1620 */ "TRM4\000" |
| 1623 | /* 1625 */ "VRM4\000" |
| 1624 | /* 1630 */ "GPRPair_with_sub_gpr_odd_in_GPRX1X5\000" |
| 1625 | /* 1666 */ "YGPR_with_sub_cap_addr_in_GPRX1X5\000" |
| 1626 | /* 1700 */ "YGPR_with_sub_cap_addr_in_GPRX5\000" |
| 1627 | /* 1732 */ "GPRF16\000" |
| 1628 | /* 1739 */ "FPR16\000" |
| 1629 | /* 1745 */ "FPR256\000" |
| 1630 | /* 1752 */ "GPRPair_with_sub_gpr_even_in_GPRC_and_GPRS07\000" |
| 1631 | /* 1797 */ "YGPR_with_sub_cap_addr_in_GPRC_and_GPRS07\000" |
| 1632 | /* 1839 */ "GPRPair_with_sub_gpr_even_in_GPRS07\000" |
| 1633 | /* 1875 */ "YGPR_with_sub_cap_addr_in_GPRS07\000" |
| 1634 | /* 1908 */ "GPRPair_with_sub_gpr_odd_in_GPRX7\000" |
| 1635 | /* 1942 */ "YGPR_with_sub_cap_addr_in_GPRX7\000" |
| 1636 | /* 1974 */ "GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7\000" |
| 1637 | /* 2026 */ "YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7\000" |
| 1638 | /* 2076 */ "GPRPair_with_sub_gpr_odd_in_GPRTCNonX7\000" |
| 1639 | /* 2115 */ "YGPR_with_sub_cap_addr_in_GPRTCNonX7\000" |
| 1640 | /* 2152 */ "GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7\000" |
| 1641 | /* 2193 */ "YGPR_with_sub_cap_addr_in_GPRJALRNonX7\000" |
| 1642 | /* 2232 */ "FPR128\000" |
| 1643 | /* 2239 */ "ZZZ_VRMF8\000" |
| 1644 | /* 2249 */ "VRM8\000" |
| 1645 | /* 2254 */ "GPRF32C\000" |
| 1646 | /* 2262 */ "FPR32C\000" |
| 1647 | /* 2269 */ "FPR64C\000" |
| 1648 | /* 2276 */ "YGPR_with_sub_16_in_GPRF16C\000" |
| 1649 | /* 2304 */ "FPR256_with_sub_16_in_FPR16C\000" |
| 1650 | /* 2333 */ "FPR128_with_sub_16_in_FPR16C\000" |
| 1651 | /* 2362 */ "GPRC\000" |
| 1652 | /* 2367 */ "GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTC\000" |
| 1653 | /* 2414 */ "YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTC\000" |
| 1654 | /* 2459 */ "GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC\000" |
| 1655 | /* 2503 */ "YGPR_with_sub_cap_addr_in_GPRC_and_GPRTC\000" |
| 1656 | /* 2544 */ "GPRPair_with_sub_gpr_even_in_GPRTC\000" |
| 1657 | /* 2579 */ "YGPR_with_sub_cap_addr_in_GPRTC\000" |
| 1658 | /* 2611 */ "GPRPairC\000" |
| 1659 | /* 2620 */ "ZZZ_VM\000" |
| 1660 | /* 2627 */ "GPRPair_with_sub_gpr_even_in_SP\000" |
| 1661 | /* 2659 */ "YGPR_with_sub_cap_addr_in_SP\000" |
| 1662 | /* 2688 */ "GPRPair_with_sub_gpr_even_in_GPRJALR\000" |
| 1663 | /* 2725 */ "YGPR_with_sub_cap_addr_in_GPRJALR\000" |
| 1664 | /* 2759 */ "MR\000" |
| 1665 | /* 2762 */ "YGPR\000" |
| 1666 | /* 2767 */ "VCSR\000" |
| 1667 | /* 2772 */ "TR\000" |
| 1668 | /* 2775 */ "VR\000" |
| 1669 | /* 2778 */ "GPRAll\000" |
| 1670 | /* 2785 */ "GPRPair\000" |
| 1671 | }; |
| 1672 | #ifdef __GNUC__ |
| 1673 | #pragma GCC diagnostic pop |
| 1674 | #endif |
| 1675 | |
| 1676 | using RISCVRegisterClassStorage = MCRegisterClassStorage<153, 2309, 429, 2110, 109, 646>; |
| 1677 | extern const MCRegisterClassStorage<153, 2309, 429, 2110, 109, 646> RISCVMCRegisterClassStorage = { |
| 1678 | .Classes: { |
| 1679 | { |
| 1680 | offsetof(RISCVRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass), |
| 1681 | offsetof(RISCVRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass), |
| 1682 | .NameIdx: 2759, |
| 1683 | .RegSizeInBits: 8, |
| 1684 | .RegsSize: 8, |
| 1685 | .RegSetBegin: 12, /* MinRegVal */ |
| 1686 | .RegSetSize: 8, /* RegSetSize */ |
| 1687 | .ID: RISCV::MRRegClassID, |
| 1688 | .CopyCost: 1, /* CopyCost */ |
| 1689 | .Allocatable: true, /* Allocatable */ |
| 1690 | .BaseClass: false, |
| 1691 | offsetof(RISCVRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass), |
| 1692 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 0 * sizeof(MCRegisterClass), |
| 1693 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1694 | .AllocationPriority: 0, |
| 1695 | .GlobalPriority: false, |
| 1696 | .TSFlags: 0x00, /* TSFlags */ |
| 1697 | .SpillStackID: 0, /* SpillStackID */ |
| 1698 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1699 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1700 | offsetof(RISCVRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass), |
| 1701 | .SuperClassesSize: 0 |
| 1702 | }, |
| 1703 | { |
| 1704 | offsetof(RISCVRegisterClassStorage, Regs[8]) - 1 * sizeof(MCRegisterClass), |
| 1705 | offsetof(RISCVRegisterClassStorage, BitSets[1]) - 1 * sizeof(MCRegisterClass), |
| 1706 | .NameIdx: 0, |
| 1707 | .RegSizeInBits: 8, |
| 1708 | .RegsSize: 1, |
| 1709 | .RegSetBegin: 12, /* MinRegVal */ |
| 1710 | .RegSetSize: 1, /* RegSetSize */ |
| 1711 | .ID: RISCV::MR0RegClassID, |
| 1712 | .CopyCost: 1, /* CopyCost */ |
| 1713 | .Allocatable: true, /* Allocatable */ |
| 1714 | .BaseClass: false, |
| 1715 | offsetof(RISCVRegisterClassStorage, SubClassMasks[5]) - 1 * sizeof(MCRegisterClass), |
| 1716 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 1 * sizeof(MCRegisterClass), |
| 1717 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1718 | .AllocationPriority: 0, |
| 1719 | .GlobalPriority: false, |
| 1720 | .TSFlags: 0x00, /* TSFlags */ |
| 1721 | .SpillStackID: 0, /* SpillStackID */ |
| 1722 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1723 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1724 | offsetof(RISCVRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass), |
| 1725 | .SuperClassesSize: 1 |
| 1726 | }, |
| 1727 | { |
| 1728 | offsetof(RISCVRegisterClassStorage, Regs[9]) - 2 * sizeof(MCRegisterClass), |
| 1729 | offsetof(RISCVRegisterClassStorage, BitSets[2]) - 2 * sizeof(MCRegisterClass), |
| 1730 | .NameIdx: 1739, |
| 1731 | .RegSizeInBits: 16, |
| 1732 | .RegsSize: 32, |
| 1733 | .RegSetBegin: 164, /* MinRegVal */ |
| 1734 | .RegSetSize: 32, /* RegSetSize */ |
| 1735 | .ID: RISCV::FPR16RegClassID, |
| 1736 | .CopyCost: 1, /* CopyCost */ |
| 1737 | .Allocatable: true, /* Allocatable */ |
| 1738 | .BaseClass: false, |
| 1739 | offsetof(RISCVRegisterClassStorage, SubClassMasks[10]) - 2 * sizeof(MCRegisterClass), |
| 1740 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[0]) - 2 * sizeof(MCRegisterClass), |
| 1741 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1742 | .AllocationPriority: 0, |
| 1743 | .GlobalPriority: false, |
| 1744 | .TSFlags: 0x00, /* TSFlags */ |
| 1745 | .SpillStackID: 0, /* SpillStackID */ |
| 1746 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1747 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1748 | offsetof(RISCVRegisterClassStorage, SuperClasses[1]) - 2 * sizeof(MCRegisterClass), |
| 1749 | .SuperClassesSize: 0 |
| 1750 | }, |
| 1751 | { |
| 1752 | offsetof(RISCVRegisterClassStorage, Regs[41]) - 3 * sizeof(MCRegisterClass), |
| 1753 | offsetof(RISCVRegisterClassStorage, BitSets[6]) - 3 * sizeof(MCRegisterClass), |
| 1754 | .NameIdx: 1732, |
| 1755 | .RegSizeInBits: 16, |
| 1756 | .RegsSize: 32, |
| 1757 | .RegSetBegin: 228, /* MinRegVal */ |
| 1758 | .RegSetSize: 32, /* RegSetSize */ |
| 1759 | .ID: RISCV::GPRF16RegClassID, |
| 1760 | .CopyCost: 1, /* CopyCost */ |
| 1761 | .Allocatable: true, /* Allocatable */ |
| 1762 | .BaseClass: false, |
| 1763 | offsetof(RISCVRegisterClassStorage, SubClassMasks[20]) - 3 * sizeof(MCRegisterClass), |
| 1764 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[43]) - 3 * sizeof(MCRegisterClass), |
| 1765 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1766 | .AllocationPriority: 0, |
| 1767 | .GlobalPriority: false, |
| 1768 | .TSFlags: 0x00, /* TSFlags */ |
| 1769 | .SpillStackID: 0, /* SpillStackID */ |
| 1770 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1771 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1772 | offsetof(RISCVRegisterClassStorage, SuperClasses[1]) - 3 * sizeof(MCRegisterClass), |
| 1773 | .SuperClassesSize: 0 |
| 1774 | }, |
| 1775 | { |
| 1776 | offsetof(RISCVRegisterClassStorage, Regs[73]) - 4 * sizeof(MCRegisterClass), |
| 1777 | offsetof(RISCVRegisterClassStorage, BitSets[10]) - 4 * sizeof(MCRegisterClass), |
| 1778 | .NameIdx: 809, |
| 1779 | .RegSizeInBits: 16, |
| 1780 | .RegsSize: 31, |
| 1781 | .RegSetBegin: 229, /* MinRegVal */ |
| 1782 | .RegSetSize: 31, /* RegSetSize */ |
| 1783 | .ID: RISCV::GPRF16NoX0RegClassID, |
| 1784 | .CopyCost: 1, /* CopyCost */ |
| 1785 | .Allocatable: true, /* Allocatable */ |
| 1786 | .BaseClass: false, |
| 1787 | offsetof(RISCVRegisterClassStorage, SubClassMasks[35]) - 4 * sizeof(MCRegisterClass), |
| 1788 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[43]) - 4 * sizeof(MCRegisterClass), |
| 1789 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1790 | .AllocationPriority: 0, |
| 1791 | .GlobalPriority: false, |
| 1792 | .TSFlags: 0x00, /* TSFlags */ |
| 1793 | .SpillStackID: 0, /* SpillStackID */ |
| 1794 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1795 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1796 | offsetof(RISCVRegisterClassStorage, SuperClasses[1]) - 4 * sizeof(MCRegisterClass), |
| 1797 | .SuperClassesSize: 1 |
| 1798 | }, |
| 1799 | { |
| 1800 | offsetof(RISCVRegisterClassStorage, Regs[104]) - 5 * sizeof(MCRegisterClass), |
| 1801 | offsetof(RISCVRegisterClassStorage, BitSets[14]) - 5 * sizeof(MCRegisterClass), |
| 1802 | .NameIdx: 2326, |
| 1803 | .RegSizeInBits: 16, |
| 1804 | .RegsSize: 8, |
| 1805 | .RegSetBegin: 172, /* MinRegVal */ |
| 1806 | .RegSetSize: 8, /* RegSetSize */ |
| 1807 | .ID: RISCV::FPR16CRegClassID, |
| 1808 | .CopyCost: 1, /* CopyCost */ |
| 1809 | .Allocatable: true, /* Allocatable */ |
| 1810 | .BaseClass: false, |
| 1811 | offsetof(RISCVRegisterClassStorage, SubClassMasks[50]) - 5 * sizeof(MCRegisterClass), |
| 1812 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass), |
| 1813 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1814 | .AllocationPriority: 0, |
| 1815 | .GlobalPriority: false, |
| 1816 | .TSFlags: 0x00, /* TSFlags */ |
| 1817 | .SpillStackID: 0, /* SpillStackID */ |
| 1818 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1819 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1820 | offsetof(RISCVRegisterClassStorage, SuperClasses[2]) - 5 * sizeof(MCRegisterClass), |
| 1821 | .SuperClassesSize: 1 |
| 1822 | }, |
| 1823 | { |
| 1824 | offsetof(RISCVRegisterClassStorage, Regs[112]) - 6 * sizeof(MCRegisterClass), |
| 1825 | offsetof(RISCVRegisterClassStorage, BitSets[15]) - 6 * sizeof(MCRegisterClass), |
| 1826 | .NameIdx: 2296, |
| 1827 | .RegSizeInBits: 16, |
| 1828 | .RegsSize: 8, |
| 1829 | .RegSetBegin: 236, /* MinRegVal */ |
| 1830 | .RegSetSize: 8, /* RegSetSize */ |
| 1831 | .ID: RISCV::GPRF16CRegClassID, |
| 1832 | .CopyCost: 1, /* CopyCost */ |
| 1833 | .Allocatable: true, /* Allocatable */ |
| 1834 | .BaseClass: false, |
| 1835 | offsetof(RISCVRegisterClassStorage, SubClassMasks[60]) - 6 * sizeof(MCRegisterClass), |
| 1836 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[43]) - 6 * sizeof(MCRegisterClass), |
| 1837 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1838 | .AllocationPriority: 0, |
| 1839 | .GlobalPriority: false, |
| 1840 | .TSFlags: 0x00, /* TSFlags */ |
| 1841 | .SpillStackID: 0, /* SpillStackID */ |
| 1842 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1843 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1844 | offsetof(RISCVRegisterClassStorage, SuperClasses[3]) - 6 * sizeof(MCRegisterClass), |
| 1845 | .SuperClassesSize: 2 |
| 1846 | }, |
| 1847 | { |
| 1848 | offsetof(RISCVRegisterClassStorage, Regs[120]) - 7 * sizeof(MCRegisterClass), |
| 1849 | offsetof(RISCVRegisterClassStorage, BitSets[16]) - 7 * sizeof(MCRegisterClass), |
| 1850 | .NameIdx: 731, |
| 1851 | .RegSizeInBits: 16, |
| 1852 | .RegsSize: 1, |
| 1853 | .RegSetBegin: 228, /* MinRegVal */ |
| 1854 | .RegSetSize: 1, /* RegSetSize */ |
| 1855 | .ID: RISCV::GPRF16X0RegClassID, |
| 1856 | .CopyCost: 1, /* CopyCost */ |
| 1857 | .Allocatable: true, /* Allocatable */ |
| 1858 | .BaseClass: false, |
| 1859 | offsetof(RISCVRegisterClassStorage, SubClassMasks[75]) - 7 * sizeof(MCRegisterClass), |
| 1860 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[0]) - 7 * sizeof(MCRegisterClass), |
| 1861 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1862 | .AllocationPriority: 0, |
| 1863 | .GlobalPriority: false, |
| 1864 | .TSFlags: 0x00, /* TSFlags */ |
| 1865 | .SpillStackID: 0, /* SpillStackID */ |
| 1866 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1867 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1868 | offsetof(RISCVRegisterClassStorage, SuperClasses[5]) - 7 * sizeof(MCRegisterClass), |
| 1869 | .SuperClassesSize: 1 |
| 1870 | }, |
| 1871 | { |
| 1872 | offsetof(RISCVRegisterClassStorage, Regs[121]) - 8 * sizeof(MCRegisterClass), |
| 1873 | offsetof(RISCVRegisterClassStorage, BitSets[17]) - 8 * sizeof(MCRegisterClass), |
| 1874 | .NameIdx: 2778, |
| 1875 | .RegSizeInBits: 0, |
| 1876 | .RegsSize: 33, |
| 1877 | .RegSetBegin: 11, /* MinRegVal */ |
| 1878 | .RegSetSize: 89, /* RegSetSize */ |
| 1879 | .ID: RISCV::GPRAllRegClassID, |
| 1880 | .CopyCost: 1, /* CopyCost */ |
| 1881 | .Allocatable: true, /* Allocatable */ |
| 1882 | .BaseClass: false, |
| 1883 | offsetof(RISCVRegisterClassStorage, SubClassMasks[85]) - 8 * sizeof(MCRegisterClass), |
| 1884 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 8 * sizeof(MCRegisterClass), |
| 1885 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1886 | .AllocationPriority: 0, |
| 1887 | .GlobalPriority: false, |
| 1888 | .TSFlags: 0x00, /* TSFlags */ |
| 1889 | .SpillStackID: 0, /* SpillStackID */ |
| 1890 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1891 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1892 | offsetof(RISCVRegisterClassStorage, SuperClasses[6]) - 8 * sizeof(MCRegisterClass), |
| 1893 | .SuperClassesSize: 0 |
| 1894 | }, |
| 1895 | { |
| 1896 | offsetof(RISCVRegisterClassStorage, Regs[154]) - 9 * sizeof(MCRegisterClass), |
| 1897 | offsetof(RISCVRegisterClassStorage, BitSets[29]) - 9 * sizeof(MCRegisterClass), |
| 1898 | .NameIdx: 1404, |
| 1899 | .RegSizeInBits: 32, |
| 1900 | .RegsSize: 32, |
| 1901 | .RegSetBegin: 132, /* MinRegVal */ |
| 1902 | .RegSetSize: 32, /* RegSetSize */ |
| 1903 | .ID: RISCV::FPR32RegClassID, |
| 1904 | .CopyCost: 1, /* CopyCost */ |
| 1905 | .Allocatable: true, /* Allocatable */ |
| 1906 | .BaseClass: false, |
| 1907 | offsetof(RISCVRegisterClassStorage, SubClassMasks[105]) - 9 * sizeof(MCRegisterClass), |
| 1908 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[2]) - 9 * sizeof(MCRegisterClass), |
| 1909 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1910 | .AllocationPriority: 0, |
| 1911 | .GlobalPriority: false, |
| 1912 | .TSFlags: 0x00, /* TSFlags */ |
| 1913 | .SpillStackID: 0, /* SpillStackID */ |
| 1914 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1915 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1916 | offsetof(RISCVRegisterClassStorage, SuperClasses[6]) - 9 * sizeof(MCRegisterClass), |
| 1917 | .SuperClassesSize: 0 |
| 1918 | }, |
| 1919 | { |
| 1920 | offsetof(RISCVRegisterClassStorage, Regs[186]) - 10 * sizeof(MCRegisterClass), |
| 1921 | offsetof(RISCVRegisterClassStorage, BitSets[33]) - 10 * sizeof(MCRegisterClass), |
| 1922 | .NameIdx: 2763, |
| 1923 | .RegSizeInBits: 0, |
| 1924 | .RegsSize: 32, |
| 1925 | .RegSetBegin: 68, /* MinRegVal */ |
| 1926 | .RegSetSize: 32, /* RegSetSize */ |
| 1927 | .ID: RISCV::GPRRegClassID, |
| 1928 | .CopyCost: 1, /* CopyCost */ |
| 1929 | .Allocatable: true, /* Allocatable */ |
| 1930 | .BaseClass: false, |
| 1931 | offsetof(RISCVRegisterClassStorage, SubClassMasks[115]) - 10 * sizeof(MCRegisterClass), |
| 1932 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 10 * sizeof(MCRegisterClass), |
| 1933 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1934 | .AllocationPriority: 0, |
| 1935 | .GlobalPriority: false, |
| 1936 | .TSFlags: 0x00, /* TSFlags */ |
| 1937 | .SpillStackID: 0, /* SpillStackID */ |
| 1938 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1939 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1940 | offsetof(RISCVRegisterClassStorage, SuperClasses[6]) - 10 * sizeof(MCRegisterClass), |
| 1941 | .SuperClassesSize: 1 |
| 1942 | }, |
| 1943 | { |
| 1944 | offsetof(RISCVRegisterClassStorage, Regs[218]) - 11 * sizeof(MCRegisterClass), |
| 1945 | offsetof(RISCVRegisterClassStorage, BitSets[37]) - 11 * sizeof(MCRegisterClass), |
| 1946 | .NameIdx: 1397, |
| 1947 | .RegSizeInBits: 32, |
| 1948 | .RegsSize: 32, |
| 1949 | .RegSetBegin: 261, /* MinRegVal */ |
| 1950 | .RegSetSize: 32, /* RegSetSize */ |
| 1951 | .ID: RISCV::GPRF32RegClassID, |
| 1952 | .CopyCost: 1, /* CopyCost */ |
| 1953 | .Allocatable: true, /* Allocatable */ |
| 1954 | .BaseClass: false, |
| 1955 | offsetof(RISCVRegisterClassStorage, SubClassMasks[135]) - 11 * sizeof(MCRegisterClass), |
| 1956 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[46]) - 11 * sizeof(MCRegisterClass), |
| 1957 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1958 | .AllocationPriority: 0, |
| 1959 | .GlobalPriority: false, |
| 1960 | .TSFlags: 0x00, /* TSFlags */ |
| 1961 | .SpillStackID: 0, /* SpillStackID */ |
| 1962 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1963 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1964 | offsetof(RISCVRegisterClassStorage, SuperClasses[7]) - 11 * sizeof(MCRegisterClass), |
| 1965 | .SuperClassesSize: 0 |
| 1966 | }, |
| 1967 | { |
| 1968 | offsetof(RISCVRegisterClassStorage, Regs[250]) - 12 * sizeof(MCRegisterClass), |
| 1969 | offsetof(RISCVRegisterClassStorage, BitSets[41]) - 12 * sizeof(MCRegisterClass), |
| 1970 | .NameIdx: 778, |
| 1971 | .RegSizeInBits: 32, |
| 1972 | .RegsSize: 31, |
| 1973 | .RegSetBegin: 262, /* MinRegVal */ |
| 1974 | .RegSetSize: 31, /* RegSetSize */ |
| 1975 | .ID: RISCV::GPRF32NoX0RegClassID, |
| 1976 | .CopyCost: 1, /* CopyCost */ |
| 1977 | .Allocatable: true, /* Allocatable */ |
| 1978 | .BaseClass: false, |
| 1979 | offsetof(RISCVRegisterClassStorage, SubClassMasks[150]) - 12 * sizeof(MCRegisterClass), |
| 1980 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[46]) - 12 * sizeof(MCRegisterClass), |
| 1981 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 1982 | .AllocationPriority: 0, |
| 1983 | .GlobalPriority: false, |
| 1984 | .TSFlags: 0x00, /* TSFlags */ |
| 1985 | .SpillStackID: 0, /* SpillStackID */ |
| 1986 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 1987 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 1988 | offsetof(RISCVRegisterClassStorage, SuperClasses[7]) - 12 * sizeof(MCRegisterClass), |
| 1989 | .SuperClassesSize: 1 |
| 1990 | }, |
| 1991 | { |
| 1992 | offsetof(RISCVRegisterClassStorage, Regs[281]) - 13 * sizeof(MCRegisterClass), |
| 1993 | offsetof(RISCVRegisterClassStorage, BitSets[45]) - 13 * sizeof(MCRegisterClass), |
| 1994 | .NameIdx: 820, |
| 1995 | .RegSizeInBits: 0, |
| 1996 | .RegsSize: 31, |
| 1997 | .RegSetBegin: 69, /* MinRegVal */ |
| 1998 | .RegSetSize: 31, /* RegSetSize */ |
| 1999 | .ID: RISCV::GPRNoX0RegClassID, |
| 2000 | .CopyCost: 1, /* CopyCost */ |
| 2001 | .Allocatable: true, /* Allocatable */ |
| 2002 | .BaseClass: false, |
| 2003 | offsetof(RISCVRegisterClassStorage, SubClassMasks[165]) - 13 * sizeof(MCRegisterClass), |
| 2004 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 13 * sizeof(MCRegisterClass), |
| 2005 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2006 | .AllocationPriority: 0, |
| 2007 | .GlobalPriority: false, |
| 2008 | .TSFlags: 0x00, /* TSFlags */ |
| 2009 | .SpillStackID: 0, /* SpillStackID */ |
| 2010 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2011 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2012 | offsetof(RISCVRegisterClassStorage, SuperClasses[8]) - 13 * sizeof(MCRegisterClass), |
| 2013 | .SuperClassesSize: 2 |
| 2014 | }, |
| 2015 | { |
| 2016 | offsetof(RISCVRegisterClassStorage, Regs[312]) - 14 * sizeof(MCRegisterClass), |
| 2017 | offsetof(RISCVRegisterClassStorage, BitSets[49]) - 14 * sizeof(MCRegisterClass), |
| 2018 | .NameIdx: 1555, |
| 2019 | .RegSizeInBits: 0, |
| 2020 | .RegsSize: 31, |
| 2021 | .RegSetBegin: 68, /* MinRegVal */ |
| 2022 | .RegSetSize: 32, /* RegSetSize */ |
| 2023 | .ID: RISCV::GPRNoX2RegClassID, |
| 2024 | .CopyCost: 1, /* CopyCost */ |
| 2025 | .Allocatable: true, /* Allocatable */ |
| 2026 | .BaseClass: false, |
| 2027 | offsetof(RISCVRegisterClassStorage, SubClassMasks[185]) - 14 * sizeof(MCRegisterClass), |
| 2028 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 14 * sizeof(MCRegisterClass), |
| 2029 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2030 | .AllocationPriority: 0, |
| 2031 | .GlobalPriority: false, |
| 2032 | .TSFlags: 0x00, /* TSFlags */ |
| 2033 | .SpillStackID: 0, /* SpillStackID */ |
| 2034 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2035 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2036 | offsetof(RISCVRegisterClassStorage, SuperClasses[10]) - 14 * sizeof(MCRegisterClass), |
| 2037 | .SuperClassesSize: 2 |
| 2038 | }, |
| 2039 | { |
| 2040 | offsetof(RISCVRegisterClassStorage, Regs[343]) - 15 * sizeof(MCRegisterClass), |
| 2041 | offsetof(RISCVRegisterClassStorage, BitSets[53]) - 15 * sizeof(MCRegisterClass), |
| 2042 | .NameIdx: 878, |
| 2043 | .RegSizeInBits: 0, |
| 2044 | .RegsSize: 31, |
| 2045 | .RegSetBegin: 68, /* MinRegVal */ |
| 2046 | .RegSetSize: 31, /* RegSetSize */ |
| 2047 | .ID: RISCV::GPRNoX31RegClassID, |
| 2048 | .CopyCost: 1, /* CopyCost */ |
| 2049 | .Allocatable: true, /* Allocatable */ |
| 2050 | .BaseClass: false, |
| 2051 | offsetof(RISCVRegisterClassStorage, SubClassMasks[205]) - 15 * sizeof(MCRegisterClass), |
| 2052 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 15 * sizeof(MCRegisterClass), |
| 2053 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2054 | .AllocationPriority: 0, |
| 2055 | .GlobalPriority: false, |
| 2056 | .TSFlags: 0x00, /* TSFlags */ |
| 2057 | .SpillStackID: 0, /* SpillStackID */ |
| 2058 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2059 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2060 | offsetof(RISCVRegisterClassStorage, SuperClasses[12]) - 15 * sizeof(MCRegisterClass), |
| 2061 | .SuperClassesSize: 2 |
| 2062 | }, |
| 2063 | { |
| 2064 | offsetof(RISCVRegisterClassStorage, Regs[374]) - 16 * sizeof(MCRegisterClass), |
| 2065 | offsetof(RISCVRegisterClassStorage, BitSets[57]) - 16 * sizeof(MCRegisterClass), |
| 2066 | .NameIdx: 1480, |
| 2067 | .RegSizeInBits: 0, |
| 2068 | .RegsSize: 30, |
| 2069 | .RegSetBegin: 69, /* MinRegVal */ |
| 2070 | .RegSetSize: 31, /* RegSetSize */ |
| 2071 | .ID: RISCV::GPRNoX0X2RegClassID, |
| 2072 | .CopyCost: 1, /* CopyCost */ |
| 2073 | .Allocatable: true, /* Allocatable */ |
| 2074 | .BaseClass: false, |
| 2075 | offsetof(RISCVRegisterClassStorage, SubClassMasks[225]) - 16 * sizeof(MCRegisterClass), |
| 2076 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 16 * sizeof(MCRegisterClass), |
| 2077 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2078 | .AllocationPriority: 0, |
| 2079 | .GlobalPriority: false, |
| 2080 | .TSFlags: 0x00, /* TSFlags */ |
| 2081 | .SpillStackID: 0, /* SpillStackID */ |
| 2082 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2083 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2084 | offsetof(RISCVRegisterClassStorage, SuperClasses[14]) - 16 * sizeof(MCRegisterClass), |
| 2085 | .SuperClassesSize: 4 |
| 2086 | }, |
| 2087 | { |
| 2088 | offsetof(RISCVRegisterClassStorage, Regs[404]) - 17 * sizeof(MCRegisterClass), |
| 2089 | offsetof(RISCVRegisterClassStorage, BitSets[61]) - 17 * sizeof(MCRegisterClass), |
| 2090 | .NameIdx: 866, |
| 2091 | .RegSizeInBits: 0, |
| 2092 | .RegsSize: 30, |
| 2093 | .RegSetBegin: 69, /* MinRegVal */ |
| 2094 | .RegSetSize: 30, /* RegSetSize */ |
| 2095 | .ID: RISCV::GPRNoX0_and_GPRNoX31RegClassID, |
| 2096 | .CopyCost: 1, /* CopyCost */ |
| 2097 | .Allocatable: true, /* Allocatable */ |
| 2098 | .BaseClass: false, |
| 2099 | offsetof(RISCVRegisterClassStorage, SubClassMasks[245]) - 17 * sizeof(MCRegisterClass), |
| 2100 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 17 * sizeof(MCRegisterClass), |
| 2101 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2102 | .AllocationPriority: 0, |
| 2103 | .GlobalPriority: false, |
| 2104 | .TSFlags: 0x00, /* TSFlags */ |
| 2105 | .SpillStackID: 0, /* SpillStackID */ |
| 2106 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2107 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2108 | offsetof(RISCVRegisterClassStorage, SuperClasses[18]) - 17 * sizeof(MCRegisterClass), |
| 2109 | .SuperClassesSize: 4 |
| 2110 | }, |
| 2111 | { |
| 2112 | offsetof(RISCVRegisterClassStorage, Regs[434]) - 18 * sizeof(MCRegisterClass), |
| 2113 | offsetof(RISCVRegisterClassStorage, BitSets[65]) - 18 * sizeof(MCRegisterClass), |
| 2114 | .NameIdx: 962, |
| 2115 | .RegSizeInBits: 0, |
| 2116 | .RegsSize: 30, |
| 2117 | .RegSetBegin: 68, /* MinRegVal */ |
| 2118 | .RegSetSize: 31, /* RegSetSize */ |
| 2119 | .ID: RISCV::GPRNoX2_and_GPRNoX31RegClassID, |
| 2120 | .CopyCost: 1, /* CopyCost */ |
| 2121 | .Allocatable: true, /* Allocatable */ |
| 2122 | .BaseClass: false, |
| 2123 | offsetof(RISCVRegisterClassStorage, SubClassMasks[265]) - 18 * sizeof(MCRegisterClass), |
| 2124 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 18 * sizeof(MCRegisterClass), |
| 2125 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2126 | .AllocationPriority: 0, |
| 2127 | .GlobalPriority: false, |
| 2128 | .TSFlags: 0x00, /* TSFlags */ |
| 2129 | .SpillStackID: 0, /* SpillStackID */ |
| 2130 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2131 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2132 | offsetof(RISCVRegisterClassStorage, SuperClasses[22]) - 18 * sizeof(MCRegisterClass), |
| 2133 | .SuperClassesSize: 4 |
| 2134 | }, |
| 2135 | { |
| 2136 | offsetof(RISCVRegisterClassStorage, Regs[464]) - 19 * sizeof(MCRegisterClass), |
| 2137 | offsetof(RISCVRegisterClassStorage, BitSets[69]) - 19 * sizeof(MCRegisterClass), |
| 2138 | .NameIdx: 913, |
| 2139 | .RegSizeInBits: 0, |
| 2140 | .RegsSize: 29, |
| 2141 | .RegSetBegin: 69, /* MinRegVal */ |
| 2142 | .RegSetSize: 30, /* RegSetSize */ |
| 2143 | .ID: RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, |
| 2144 | .CopyCost: 1, /* CopyCost */ |
| 2145 | .Allocatable: true, /* Allocatable */ |
| 2146 | .BaseClass: false, |
| 2147 | offsetof(RISCVRegisterClassStorage, SubClassMasks[285]) - 19 * sizeof(MCRegisterClass), |
| 2148 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 19 * sizeof(MCRegisterClass), |
| 2149 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2150 | .AllocationPriority: 0, |
| 2151 | .GlobalPriority: false, |
| 2152 | .TSFlags: 0x00, /* TSFlags */ |
| 2153 | .SpillStackID: 0, /* SpillStackID */ |
| 2154 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2155 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2156 | offsetof(RISCVRegisterClassStorage, SuperClasses[26]) - 19 * sizeof(MCRegisterClass), |
| 2157 | .SuperClassesSize: 8 |
| 2158 | }, |
| 2159 | { |
| 2160 | offsetof(RISCVRegisterClassStorage, Regs[493]) - 20 * sizeof(MCRegisterClass), |
| 2161 | offsetof(RISCVRegisterClassStorage, BitSets[73]) - 20 * sizeof(MCRegisterClass), |
| 2162 | .NameIdx: 2717, |
| 2163 | .RegSizeInBits: 0, |
| 2164 | .RegsSize: 26, |
| 2165 | .RegSetBegin: 74, /* MinRegVal */ |
| 2166 | .RegSetSize: 26, /* RegSetSize */ |
| 2167 | .ID: RISCV::GPRJALRRegClassID, |
| 2168 | .CopyCost: 1, /* CopyCost */ |
| 2169 | .Allocatable: true, /* Allocatable */ |
| 2170 | .BaseClass: false, |
| 2171 | offsetof(RISCVRegisterClassStorage, SubClassMasks[305]) - 20 * sizeof(MCRegisterClass), |
| 2172 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 20 * sizeof(MCRegisterClass), |
| 2173 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2174 | .AllocationPriority: 0, |
| 2175 | .GlobalPriority: false, |
| 2176 | .TSFlags: 0x00, /* TSFlags */ |
| 2177 | .SpillStackID: 0, /* SpillStackID */ |
| 2178 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2179 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2180 | offsetof(RISCVRegisterClassStorage, SuperClasses[34]) - 20 * sizeof(MCRegisterClass), |
| 2181 | .SuperClassesSize: 5 |
| 2182 | }, |
| 2183 | { |
| 2184 | offsetof(RISCVRegisterClassStorage, Regs[519]) - 21 * sizeof(MCRegisterClass), |
| 2185 | offsetof(RISCVRegisterClassStorage, BitSets[77]) - 21 * sizeof(MCRegisterClass), |
| 2186 | .NameIdx: 2180, |
| 2187 | .RegSizeInBits: 0, |
| 2188 | .RegsSize: 25, |
| 2189 | .RegSetBegin: 74, /* MinRegVal */ |
| 2190 | .RegSetSize: 26, /* RegSetSize */ |
| 2191 | .ID: RISCV::GPRJALRNonX7RegClassID, |
| 2192 | .CopyCost: 1, /* CopyCost */ |
| 2193 | .Allocatable: true, /* Allocatable */ |
| 2194 | .BaseClass: false, |
| 2195 | offsetof(RISCVRegisterClassStorage, SubClassMasks[325]) - 21 * sizeof(MCRegisterClass), |
| 2196 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 21 * sizeof(MCRegisterClass), |
| 2197 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2198 | .AllocationPriority: 0, |
| 2199 | .GlobalPriority: false, |
| 2200 | .TSFlags: 0x00, /* TSFlags */ |
| 2201 | .SpillStackID: 0, /* SpillStackID */ |
| 2202 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2203 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2204 | offsetof(RISCVRegisterClassStorage, SuperClasses[39]) - 21 * sizeof(MCRegisterClass), |
| 2205 | .SuperClassesSize: 6 |
| 2206 | }, |
| 2207 | { |
| 2208 | offsetof(RISCVRegisterClassStorage, Regs[544]) - 22 * sizeof(MCRegisterClass), |
| 2209 | offsetof(RISCVRegisterClassStorage, BitSets[81]) - 22 * sizeof(MCRegisterClass), |
| 2210 | .NameIdx: 1117, |
| 2211 | .RegSizeInBits: 0, |
| 2212 | .RegsSize: 25, |
| 2213 | .RegSetBegin: 74, /* MinRegVal */ |
| 2214 | .RegSetSize: 25, /* RegSetSize */ |
| 2215 | .ID: RISCV::GPRJALR_and_GPRNoX31RegClassID, |
| 2216 | .CopyCost: 1, /* CopyCost */ |
| 2217 | .Allocatable: true, /* Allocatable */ |
| 2218 | .BaseClass: false, |
| 2219 | offsetof(RISCVRegisterClassStorage, SubClassMasks[345]) - 22 * sizeof(MCRegisterClass), |
| 2220 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 22 * sizeof(MCRegisterClass), |
| 2221 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2222 | .AllocationPriority: 0, |
| 2223 | .GlobalPriority: false, |
| 2224 | .TSFlags: 0x00, /* TSFlags */ |
| 2225 | .SpillStackID: 0, /* SpillStackID */ |
| 2226 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2227 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2228 | offsetof(RISCVRegisterClassStorage, SuperClasses[45]) - 22 * sizeof(MCRegisterClass), |
| 2229 | .SuperClassesSize: 10 |
| 2230 | }, |
| 2231 | { |
| 2232 | offsetof(RISCVRegisterClassStorage, Regs[569]) - 23 * sizeof(MCRegisterClass), |
| 2233 | offsetof(RISCVRegisterClassStorage, BitSets[85]) - 23 * sizeof(MCRegisterClass), |
| 2234 | .NameIdx: 1011, |
| 2235 | .RegSizeInBits: 0, |
| 2236 | .RegsSize: 24, |
| 2237 | .RegSetBegin: 74, /* MinRegVal */ |
| 2238 | .RegSetSize: 25, /* RegSetSize */ |
| 2239 | .ID: RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 2240 | .CopyCost: 1, /* CopyCost */ |
| 2241 | .Allocatable: true, /* Allocatable */ |
| 2242 | .BaseClass: false, |
| 2243 | offsetof(RISCVRegisterClassStorage, SubClassMasks[365]) - 23 * sizeof(MCRegisterClass), |
| 2244 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 23 * sizeof(MCRegisterClass), |
| 2245 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2246 | .AllocationPriority: 0, |
| 2247 | .GlobalPriority: false, |
| 2248 | .TSFlags: 0x00, /* TSFlags */ |
| 2249 | .SpillStackID: 0, /* SpillStackID */ |
| 2250 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2251 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2252 | offsetof(RISCVRegisterClassStorage, SuperClasses[55]) - 23 * sizeof(MCRegisterClass), |
| 2253 | .SuperClassesSize: 12 |
| 2254 | }, |
| 2255 | { |
| 2256 | offsetof(RISCVRegisterClassStorage, Regs[593]) - 24 * sizeof(MCRegisterClass), |
| 2257 | offsetof(RISCVRegisterClassStorage, BitSets[89]) - 24 * sizeof(MCRegisterClass), |
| 2258 | .NameIdx: 2772, |
| 2259 | .RegSizeInBits: 0, |
| 2260 | .RegsSize: 16, |
| 2261 | .RegSetBegin: 20, /* MinRegVal */ |
| 2262 | .RegSetSize: 16, /* RegSetSize */ |
| 2263 | .ID: RISCV::TRRegClassID, |
| 2264 | .CopyCost: 1, /* CopyCost */ |
| 2265 | .Allocatable: true, /* Allocatable */ |
| 2266 | .BaseClass: false, |
| 2267 | offsetof(RISCVRegisterClassStorage, SubClassMasks[385]) - 24 * sizeof(MCRegisterClass), |
| 2268 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 24 * sizeof(MCRegisterClass), |
| 2269 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2270 | .AllocationPriority: 0, |
| 2271 | .GlobalPriority: false, |
| 2272 | .TSFlags: 0x00, /* TSFlags */ |
| 2273 | .SpillStackID: 0, /* SpillStackID */ |
| 2274 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2275 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2276 | offsetof(RISCVRegisterClassStorage, SuperClasses[67]) - 24 * sizeof(MCRegisterClass), |
| 2277 | .SuperClassesSize: 0 |
| 2278 | }, |
| 2279 | { |
| 2280 | offsetof(RISCVRegisterClassStorage, Regs[609]) - 25 * sizeof(MCRegisterClass), |
| 2281 | offsetof(RISCVRegisterClassStorage, BitSets[91]) - 25 * sizeof(MCRegisterClass), |
| 2282 | .NameIdx: 2408, |
| 2283 | .RegSizeInBits: 0, |
| 2284 | .RegsSize: 14, |
| 2285 | .RegSetBegin: 74, /* MinRegVal */ |
| 2286 | .RegSetSize: 26, /* RegSetSize */ |
| 2287 | .ID: RISCV::GPRTCRegClassID, |
| 2288 | .CopyCost: 1, /* CopyCost */ |
| 2289 | .Allocatable: true, /* Allocatable */ |
| 2290 | .BaseClass: false, |
| 2291 | offsetof(RISCVRegisterClassStorage, SubClassMasks[390]) - 25 * sizeof(MCRegisterClass), |
| 2292 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 25 * sizeof(MCRegisterClass), |
| 2293 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2294 | .AllocationPriority: 0, |
| 2295 | .GlobalPriority: false, |
| 2296 | .TSFlags: 0x00, /* TSFlags */ |
| 2297 | .SpillStackID: 0, /* SpillStackID */ |
| 2298 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2299 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2300 | offsetof(RISCVRegisterClassStorage, SuperClasses[67]) - 25 * sizeof(MCRegisterClass), |
| 2301 | .SuperClassesSize: 6 |
| 2302 | }, |
| 2303 | { |
| 2304 | offsetof(RISCVRegisterClassStorage, Regs[623]) - 26 * sizeof(MCRegisterClass), |
| 2305 | offsetof(RISCVRegisterClassStorage, BitSets[95]) - 26 * sizeof(MCRegisterClass), |
| 2306 | .NameIdx: 2395, |
| 2307 | .RegSizeInBits: 0, |
| 2308 | .RegsSize: 13, |
| 2309 | .RegSetBegin: 74, /* MinRegVal */ |
| 2310 | .RegSetSize: 25, /* RegSetSize */ |
| 2311 | .ID: RISCV::GPRNoX31_and_GPRTCRegClassID, |
| 2312 | .CopyCost: 1, /* CopyCost */ |
| 2313 | .Allocatable: true, /* Allocatable */ |
| 2314 | .BaseClass: false, |
| 2315 | offsetof(RISCVRegisterClassStorage, SubClassMasks[410]) - 26 * sizeof(MCRegisterClass), |
| 2316 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 26 * sizeof(MCRegisterClass), |
| 2317 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2318 | .AllocationPriority: 0, |
| 2319 | .GlobalPriority: false, |
| 2320 | .TSFlags: 0x00, /* TSFlags */ |
| 2321 | .SpillStackID: 0, /* SpillStackID */ |
| 2322 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2323 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2324 | offsetof(RISCVRegisterClassStorage, SuperClasses[73]) - 26 * sizeof(MCRegisterClass), |
| 2325 | .SuperClassesSize: 12 |
| 2326 | }, |
| 2327 | { |
| 2328 | offsetof(RISCVRegisterClassStorage, Regs[636]) - 27 * sizeof(MCRegisterClass), |
| 2329 | offsetof(RISCVRegisterClassStorage, BitSets[99]) - 27 * sizeof(MCRegisterClass), |
| 2330 | .NameIdx: 2015, |
| 2331 | .RegSizeInBits: 0, |
| 2332 | .RegsSize: 13, |
| 2333 | .RegSetBegin: 74, /* MinRegVal */ |
| 2334 | .RegSetSize: 26, /* RegSetSize */ |
| 2335 | .ID: RISCV::GPRTCNonX7RegClassID, |
| 2336 | .CopyCost: 1, /* CopyCost */ |
| 2337 | .Allocatable: true, /* Allocatable */ |
| 2338 | .BaseClass: false, |
| 2339 | offsetof(RISCVRegisterClassStorage, SubClassMasks[430]) - 27 * sizeof(MCRegisterClass), |
| 2340 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 27 * sizeof(MCRegisterClass), |
| 2341 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2342 | .AllocationPriority: 0, |
| 2343 | .GlobalPriority: false, |
| 2344 | .TSFlags: 0x00, /* TSFlags */ |
| 2345 | .SpillStackID: 0, /* SpillStackID */ |
| 2346 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2347 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2348 | offsetof(RISCVRegisterClassStorage, SuperClasses[85]) - 27 * sizeof(MCRegisterClass), |
| 2349 | .SuperClassesSize: 8 |
| 2350 | }, |
| 2351 | { |
| 2352 | offsetof(RISCVRegisterClassStorage, Regs[649]) - 28 * sizeof(MCRegisterClass), |
| 2353 | offsetof(RISCVRegisterClassStorage, BitSets[103]) - 28 * sizeof(MCRegisterClass), |
| 2354 | .NameIdx: 2002, |
| 2355 | .RegSizeInBits: 0, |
| 2356 | .RegsSize: 12, |
| 2357 | .RegSetBegin: 74, /* MinRegVal */ |
| 2358 | .RegSetSize: 25, /* RegSetSize */ |
| 2359 | .ID: RISCV::GPRNoX31_and_GPRTCNonX7RegClassID, |
| 2360 | .CopyCost: 1, /* CopyCost */ |
| 2361 | .Allocatable: true, /* Allocatable */ |
| 2362 | .BaseClass: false, |
| 2363 | offsetof(RISCVRegisterClassStorage, SubClassMasks[450]) - 28 * sizeof(MCRegisterClass), |
| 2364 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 28 * sizeof(MCRegisterClass), |
| 2365 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2366 | .AllocationPriority: 0, |
| 2367 | .GlobalPriority: false, |
| 2368 | .TSFlags: 0x00, /* TSFlags */ |
| 2369 | .SpillStackID: 0, /* SpillStackID */ |
| 2370 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2371 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2372 | offsetof(RISCVRegisterClassStorage, SuperClasses[93]) - 28 * sizeof(MCRegisterClass), |
| 2373 | .SuperClassesSize: 16 |
| 2374 | }, |
| 2375 | { |
| 2376 | offsetof(RISCVRegisterClassStorage, Regs[661]) - 29 * sizeof(MCRegisterClass), |
| 2377 | offsetof(RISCVRegisterClassStorage, BitSets[107]) - 29 * sizeof(MCRegisterClass), |
| 2378 | .NameIdx: 2262, |
| 2379 | .RegSizeInBits: 32, |
| 2380 | .RegsSize: 8, |
| 2381 | .RegSetBegin: 140, /* MinRegVal */ |
| 2382 | .RegSetSize: 8, /* RegSetSize */ |
| 2383 | .ID: RISCV::FPR32CRegClassID, |
| 2384 | .CopyCost: 1, /* CopyCost */ |
| 2385 | .Allocatable: true, /* Allocatable */ |
| 2386 | .BaseClass: false, |
| 2387 | offsetof(RISCVRegisterClassStorage, SubClassMasks[470]) - 29 * sizeof(MCRegisterClass), |
| 2388 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[2]) - 29 * sizeof(MCRegisterClass), |
| 2389 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2390 | .AllocationPriority: 0, |
| 2391 | .GlobalPriority: false, |
| 2392 | .TSFlags: 0x00, /* TSFlags */ |
| 2393 | .SpillStackID: 0, /* SpillStackID */ |
| 2394 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2395 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2396 | offsetof(RISCVRegisterClassStorage, SuperClasses[109]) - 29 * sizeof(MCRegisterClass), |
| 2397 | .SuperClassesSize: 1 |
| 2398 | }, |
| 2399 | { |
| 2400 | offsetof(RISCVRegisterClassStorage, Regs[669]) - 30 * sizeof(MCRegisterClass), |
| 2401 | offsetof(RISCVRegisterClassStorage, BitSets[108]) - 30 * sizeof(MCRegisterClass), |
| 2402 | .NameIdx: 2362, |
| 2403 | .RegSizeInBits: 0, |
| 2404 | .RegsSize: 8, |
| 2405 | .RegSetBegin: 76, /* MinRegVal */ |
| 2406 | .RegSetSize: 8, /* RegSetSize */ |
| 2407 | .ID: RISCV::GPRCRegClassID, |
| 2408 | .CopyCost: 1, /* CopyCost */ |
| 2409 | .Allocatable: true, /* Allocatable */ |
| 2410 | .BaseClass: false, |
| 2411 | offsetof(RISCVRegisterClassStorage, SubClassMasks[480]) - 30 * sizeof(MCRegisterClass), |
| 2412 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 30 * sizeof(MCRegisterClass), |
| 2413 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2414 | .AllocationPriority: 0, |
| 2415 | .GlobalPriority: false, |
| 2416 | .TSFlags: 0x00, /* TSFlags */ |
| 2417 | .SpillStackID: 0, /* SpillStackID */ |
| 2418 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2419 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2420 | offsetof(RISCVRegisterClassStorage, SuperClasses[110]) - 30 * sizeof(MCRegisterClass), |
| 2421 | .SuperClassesSize: 13 |
| 2422 | }, |
| 2423 | { |
| 2424 | offsetof(RISCVRegisterClassStorage, Regs[677]) - 31 * sizeof(MCRegisterClass), |
| 2425 | offsetof(RISCVRegisterClassStorage, BitSets[109]) - 31 * sizeof(MCRegisterClass), |
| 2426 | .NameIdx: 2254, |
| 2427 | .RegSizeInBits: 32, |
| 2428 | .RegsSize: 8, |
| 2429 | .RegSetBegin: 269, /* MinRegVal */ |
| 2430 | .RegSetSize: 8, /* RegSetSize */ |
| 2431 | .ID: RISCV::GPRF32CRegClassID, |
| 2432 | .CopyCost: 1, /* CopyCost */ |
| 2433 | .Allocatable: true, /* Allocatable */ |
| 2434 | .BaseClass: false, |
| 2435 | offsetof(RISCVRegisterClassStorage, SubClassMasks[500]) - 31 * sizeof(MCRegisterClass), |
| 2436 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[46]) - 31 * sizeof(MCRegisterClass), |
| 2437 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2438 | .AllocationPriority: 0, |
| 2439 | .GlobalPriority: false, |
| 2440 | .TSFlags: 0x00, /* TSFlags */ |
| 2441 | .SpillStackID: 0, /* SpillStackID */ |
| 2442 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2443 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2444 | offsetof(RISCVRegisterClassStorage, SuperClasses[123]) - 31 * sizeof(MCRegisterClass), |
| 2445 | .SuperClassesSize: 2 |
| 2446 | }, |
| 2447 | { |
| 2448 | offsetof(RISCVRegisterClassStorage, Regs[685]) - 32 * sizeof(MCRegisterClass), |
| 2449 | offsetof(RISCVRegisterClassStorage, BitSets[110]) - 32 * sizeof(MCRegisterClass), |
| 2450 | .NameIdx: 1790, |
| 2451 | .RegSizeInBits: 0, |
| 2452 | .RegsSize: 8, |
| 2453 | .RegSetBegin: 76, /* MinRegVal */ |
| 2454 | .RegSetSize: 16, /* RegSetSize */ |
| 2455 | .ID: RISCV::GPRS07RegClassID, |
| 2456 | .CopyCost: 1, /* CopyCost */ |
| 2457 | .Allocatable: true, /* Allocatable */ |
| 2458 | .BaseClass: false, |
| 2459 | offsetof(RISCVRegisterClassStorage, SubClassMasks[515]) - 32 * sizeof(MCRegisterClass), |
| 2460 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 32 * sizeof(MCRegisterClass), |
| 2461 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2462 | .AllocationPriority: 0, |
| 2463 | .GlobalPriority: false, |
| 2464 | .TSFlags: 0x00, /* TSFlags */ |
| 2465 | .SpillStackID: 0, /* SpillStackID */ |
| 2466 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2467 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2468 | offsetof(RISCVRegisterClassStorage, SuperClasses[125]) - 32 * sizeof(MCRegisterClass), |
| 2469 | .SuperClassesSize: 13 |
| 2470 | }, |
| 2471 | { |
| 2472 | offsetof(RISCVRegisterClassStorage, Regs[693]) - 33 * sizeof(MCRegisterClass), |
| 2473 | offsetof(RISCVRegisterClassStorage, BitSets[112]) - 33 * sizeof(MCRegisterClass), |
| 2474 | .NameIdx: 1441, |
| 2475 | .RegSizeInBits: 0, |
| 2476 | .RegsSize: 8, |
| 2477 | .RegSetBegin: 20, /* MinRegVal */ |
| 2478 | .RegSetSize: 15, /* RegSetSize */ |
| 2479 | .ID: RISCV::TRM2RegClassID, |
| 2480 | .CopyCost: 1, /* CopyCost */ |
| 2481 | .Allocatable: true, /* Allocatable */ |
| 2482 | .BaseClass: false, |
| 2483 | offsetof(RISCVRegisterClassStorage, SubClassMasks[535]) - 33 * sizeof(MCRegisterClass), |
| 2484 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 33 * sizeof(MCRegisterClass), |
| 2485 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2486 | .AllocationPriority: 0, |
| 2487 | .GlobalPriority: false, |
| 2488 | .TSFlags: 0x00, /* TSFlags */ |
| 2489 | .SpillStackID: 0, /* SpillStackID */ |
| 2490 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2491 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2492 | offsetof(RISCVRegisterClassStorage, SuperClasses[138]) - 33 * sizeof(MCRegisterClass), |
| 2493 | .SuperClassesSize: 1 |
| 2494 | }, |
| 2495 | { |
| 2496 | offsetof(RISCVRegisterClassStorage, Regs[701]) - 34 * sizeof(MCRegisterClass), |
| 2497 | offsetof(RISCVRegisterClassStorage, BitSets[114]) - 34 * sizeof(MCRegisterClass), |
| 2498 | .NameIdx: 2488, |
| 2499 | .RegSizeInBits: 0, |
| 2500 | .RegsSize: 6, |
| 2501 | .RegSetBegin: 78, /* MinRegVal */ |
| 2502 | .RegSetSize: 6, /* RegSetSize */ |
| 2503 | .ID: RISCV::GPRC_and_GPRTCRegClassID, |
| 2504 | .CopyCost: 1, /* CopyCost */ |
| 2505 | .Allocatable: true, /* Allocatable */ |
| 2506 | .BaseClass: false, |
| 2507 | offsetof(RISCVRegisterClassStorage, SubClassMasks[540]) - 34 * sizeof(MCRegisterClass), |
| 2508 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 34 * sizeof(MCRegisterClass), |
| 2509 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2510 | .AllocationPriority: 0, |
| 2511 | .GlobalPriority: false, |
| 2512 | .TSFlags: 0x00, /* TSFlags */ |
| 2513 | .SpillStackID: 0, /* SpillStackID */ |
| 2514 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2515 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2516 | offsetof(RISCVRegisterClassStorage, SuperClasses[139]) - 34 * sizeof(MCRegisterClass), |
| 2517 | .SuperClassesSize: 18 |
| 2518 | }, |
| 2519 | { |
| 2520 | offsetof(RISCVRegisterClassStorage, Regs[707]) - 35 * sizeof(MCRegisterClass), |
| 2521 | offsetof(RISCVRegisterClassStorage, BitSets[115]) - 35 * sizeof(MCRegisterClass), |
| 2522 | .NameIdx: 1620, |
| 2523 | .RegSizeInBits: 0, |
| 2524 | .RegsSize: 4, |
| 2525 | .RegSetBegin: 20, /* MinRegVal */ |
| 2526 | .RegSetSize: 13, /* RegSetSize */ |
| 2527 | .ID: RISCV::TRM4RegClassID, |
| 2528 | .CopyCost: 1, /* CopyCost */ |
| 2529 | .Allocatable: true, /* Allocatable */ |
| 2530 | .BaseClass: false, |
| 2531 | offsetof(RISCVRegisterClassStorage, SubClassMasks[560]) - 35 * sizeof(MCRegisterClass), |
| 2532 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 35 * sizeof(MCRegisterClass), |
| 2533 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2534 | .AllocationPriority: 0, |
| 2535 | .GlobalPriority: false, |
| 2536 | .TSFlags: 0x00, /* TSFlags */ |
| 2537 | .SpillStackID: 0, /* SpillStackID */ |
| 2538 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2539 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2540 | offsetof(RISCVRegisterClassStorage, SuperClasses[157]) - 35 * sizeof(MCRegisterClass), |
| 2541 | .SuperClassesSize: 2 |
| 2542 | }, |
| 2543 | { |
| 2544 | offsetof(RISCVRegisterClassStorage, Regs[711]) - 36 * sizeof(MCRegisterClass), |
| 2545 | offsetof(RISCVRegisterClassStorage, BitSets[117]) - 36 * sizeof(MCRegisterClass), |
| 2546 | .NameIdx: 2767, |
| 2547 | .RegSizeInBits: 0, |
| 2548 | .RegsSize: 3, |
| 2549 | .RegSetBegin: 6, /* MinRegVal */ |
| 2550 | .RegSetSize: 3, /* RegSetSize */ |
| 2551 | .ID: RISCV::VCSRRegClassID, |
| 2552 | .CopyCost: 1, /* CopyCost */ |
| 2553 | .Allocatable: false, /* Allocatable */ |
| 2554 | .BaseClass: false, |
| 2555 | offsetof(RISCVRegisterClassStorage, SubClassMasks[565]) - 36 * sizeof(MCRegisterClass), |
| 2556 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 36 * sizeof(MCRegisterClass), |
| 2557 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2558 | .AllocationPriority: 0, |
| 2559 | .GlobalPriority: false, |
| 2560 | .TSFlags: 0x00, /* TSFlags */ |
| 2561 | .SpillStackID: 0, /* SpillStackID */ |
| 2562 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2563 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2564 | offsetof(RISCVRegisterClassStorage, SuperClasses[159]) - 36 * sizeof(MCRegisterClass), |
| 2565 | .SuperClassesSize: 0 |
| 2566 | }, |
| 2567 | { |
| 2568 | offsetof(RISCVRegisterClassStorage, Regs[714]) - 37 * sizeof(MCRegisterClass), |
| 2569 | offsetof(RISCVRegisterClassStorage, BitSets[118]) - 37 * sizeof(MCRegisterClass), |
| 2570 | .NameIdx: 1781, |
| 2571 | .RegSizeInBits: 0, |
| 2572 | .RegsSize: 2, |
| 2573 | .RegSetBegin: 76, /* MinRegVal */ |
| 2574 | .RegSetSize: 2, /* RegSetSize */ |
| 2575 | .ID: RISCV::GPRC_and_GPRS07RegClassID, |
| 2576 | .CopyCost: 1, /* CopyCost */ |
| 2577 | .Allocatable: true, /* Allocatable */ |
| 2578 | .BaseClass: false, |
| 2579 | offsetof(RISCVRegisterClassStorage, SubClassMasks[570]) - 37 * sizeof(MCRegisterClass), |
| 2580 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[16]) - 37 * sizeof(MCRegisterClass), |
| 2581 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2582 | .AllocationPriority: 0, |
| 2583 | .GlobalPriority: false, |
| 2584 | .TSFlags: 0x00, /* TSFlags */ |
| 2585 | .SpillStackID: 0, /* SpillStackID */ |
| 2586 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2587 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2588 | offsetof(RISCVRegisterClassStorage, SuperClasses[159]) - 37 * sizeof(MCRegisterClass), |
| 2589 | .SuperClassesSize: 15 |
| 2590 | }, |
| 2591 | { |
| 2592 | offsetof(RISCVRegisterClassStorage, Regs[716]) - 38 * sizeof(MCRegisterClass), |
| 2593 | offsetof(RISCVRegisterClassStorage, BitSets[119]) - 38 * sizeof(MCRegisterClass), |
| 2594 | .NameIdx: 1658, |
| 2595 | .RegSizeInBits: 0, |
| 2596 | .RegsSize: 2, |
| 2597 | .RegSetBegin: 69, /* MinRegVal */ |
| 2598 | .RegSetSize: 5, /* RegSetSize */ |
| 2599 | .ID: RISCV::GPRX1X5RegClassID, |
| 2600 | .CopyCost: 1, /* CopyCost */ |
| 2601 | .Allocatable: true, /* Allocatable */ |
| 2602 | .BaseClass: false, |
| 2603 | offsetof(RISCVRegisterClassStorage, SubClassMasks[590]) - 38 * sizeof(MCRegisterClass), |
| 2604 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[13]) - 38 * sizeof(MCRegisterClass), |
| 2605 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2606 | .AllocationPriority: 0, |
| 2607 | .GlobalPriority: false, |
| 2608 | .TSFlags: 0x00, /* TSFlags */ |
| 2609 | .SpillStackID: 0, /* SpillStackID */ |
| 2610 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2611 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2612 | offsetof(RISCVRegisterClassStorage, SuperClasses[174]) - 38 * sizeof(MCRegisterClass), |
| 2613 | .SuperClassesSize: 9 |
| 2614 | }, |
| 2615 | { |
| 2616 | offsetof(RISCVRegisterClassStorage, Regs[718]) - 39 * sizeof(MCRegisterClass), |
| 2617 | offsetof(RISCVRegisterClassStorage, BitSets[120]) - 39 * sizeof(MCRegisterClass), |
| 2618 | .NameIdx: 702, |
| 2619 | .RegSizeInBits: 32, |
| 2620 | .RegsSize: 1, |
| 2621 | .RegSetBegin: 261, /* MinRegVal */ |
| 2622 | .RegSetSize: 1, /* RegSetSize */ |
| 2623 | .ID: RISCV::GPRF32X0RegClassID, |
| 2624 | .CopyCost: 1, /* CopyCost */ |
| 2625 | .Allocatable: true, /* Allocatable */ |
| 2626 | .BaseClass: false, |
| 2627 | offsetof(RISCVRegisterClassStorage, SubClassMasks[605]) - 39 * sizeof(MCRegisterClass), |
| 2628 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[2]) - 39 * sizeof(MCRegisterClass), |
| 2629 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2630 | .AllocationPriority: 0, |
| 2631 | .GlobalPriority: false, |
| 2632 | .TSFlags: 0x00, /* TSFlags */ |
| 2633 | .SpillStackID: 0, /* SpillStackID */ |
| 2634 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2635 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2636 | offsetof(RISCVRegisterClassStorage, SuperClasses[183]) - 39 * sizeof(MCRegisterClass), |
| 2637 | .SuperClassesSize: 1 |
| 2638 | }, |
| 2639 | { |
| 2640 | offsetof(RISCVRegisterClassStorage, Regs[719]) - 40 * sizeof(MCRegisterClass), |
| 2641 | offsetof(RISCVRegisterClassStorage, BitSets[121]) - 40 * sizeof(MCRegisterClass), |
| 2642 | .NameIdx: 772, |
| 2643 | .RegSizeInBits: 0, |
| 2644 | .RegsSize: 1, |
| 2645 | .RegSetBegin: 68, /* MinRegVal */ |
| 2646 | .RegSetSize: 1, /* RegSetSize */ |
| 2647 | .ID: RISCV::GPRX0RegClassID, |
| 2648 | .CopyCost: 1, /* CopyCost */ |
| 2649 | .Allocatable: true, /* Allocatable */ |
| 2650 | .BaseClass: false, |
| 2651 | offsetof(RISCVRegisterClassStorage, SubClassMasks[615]) - 40 * sizeof(MCRegisterClass), |
| 2652 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[10]) - 40 * sizeof(MCRegisterClass), |
| 2653 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2654 | .AllocationPriority: 0, |
| 2655 | .GlobalPriority: false, |
| 2656 | .TSFlags: 0x00, /* TSFlags */ |
| 2657 | .SpillStackID: 0, /* SpillStackID */ |
| 2658 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2659 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2660 | offsetof(RISCVRegisterClassStorage, SuperClasses[184]) - 40 * sizeof(MCRegisterClass), |
| 2661 | .SuperClassesSize: 5 |
| 2662 | }, |
| 2663 | { |
| 2664 | offsetof(RISCVRegisterClassStorage, Regs[720]) - 41 * sizeof(MCRegisterClass), |
| 2665 | offsetof(RISCVRegisterClassStorage, BitSets[122]) - 41 * sizeof(MCRegisterClass), |
| 2666 | .NameIdx: 1391, |
| 2667 | .RegSizeInBits: 0, |
| 2668 | .RegsSize: 1, |
| 2669 | .RegSetBegin: 69, /* MinRegVal */ |
| 2670 | .RegSetSize: 1, /* RegSetSize */ |
| 2671 | .ID: RISCV::GPRX1RegClassID, |
| 2672 | .CopyCost: 1, /* CopyCost */ |
| 2673 | .Allocatable: true, /* Allocatable */ |
| 2674 | .BaseClass: false, |
| 2675 | offsetof(RISCVRegisterClassStorage, SubClassMasks[630]) - 41 * sizeof(MCRegisterClass), |
| 2676 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[8]) - 41 * sizeof(MCRegisterClass), |
| 2677 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2678 | .AllocationPriority: 0, |
| 2679 | .GlobalPriority: false, |
| 2680 | .TSFlags: 0x00, /* TSFlags */ |
| 2681 | .SpillStackID: 0, /* SpillStackID */ |
| 2682 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2683 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2684 | offsetof(RISCVRegisterClassStorage, SuperClasses[189]) - 41 * sizeof(MCRegisterClass), |
| 2685 | .SuperClassesSize: 10 |
| 2686 | }, |
| 2687 | { |
| 2688 | offsetof(RISCVRegisterClassStorage, Regs[721]) - 42 * sizeof(MCRegisterClass), |
| 2689 | offsetof(RISCVRegisterClassStorage, BitSets[123]) - 42 * sizeof(MCRegisterClass), |
| 2690 | .NameIdx: 1726, |
| 2691 | .RegSizeInBits: 0, |
| 2692 | .RegsSize: 1, |
| 2693 | .RegSetBegin: 73, /* MinRegVal */ |
| 2694 | .RegSetSize: 1, /* RegSetSize */ |
| 2695 | .ID: RISCV::GPRX5RegClassID, |
| 2696 | .CopyCost: 1, /* CopyCost */ |
| 2697 | .Allocatable: true, /* Allocatable */ |
| 2698 | .BaseClass: false, |
| 2699 | offsetof(RISCVRegisterClassStorage, SubClassMasks[640]) - 42 * sizeof(MCRegisterClass), |
| 2700 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[13]) - 42 * sizeof(MCRegisterClass), |
| 2701 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2702 | .AllocationPriority: 0, |
| 2703 | .GlobalPriority: false, |
| 2704 | .TSFlags: 0x00, /* TSFlags */ |
| 2705 | .SpillStackID: 0, /* SpillStackID */ |
| 2706 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2707 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2708 | offsetof(RISCVRegisterClassStorage, SuperClasses[199]) - 42 * sizeof(MCRegisterClass), |
| 2709 | .SuperClassesSize: 10 |
| 2710 | }, |
| 2711 | { |
| 2712 | offsetof(RISCVRegisterClassStorage, Regs[722]) - 43 * sizeof(MCRegisterClass), |
| 2713 | offsetof(RISCVRegisterClassStorage, BitSets[124]) - 43 * sizeof(MCRegisterClass), |
| 2714 | .NameIdx: 1936, |
| 2715 | .RegSizeInBits: 0, |
| 2716 | .RegsSize: 1, |
| 2717 | .RegSetBegin: 75, /* MinRegVal */ |
| 2718 | .RegSetSize: 1, /* RegSetSize */ |
| 2719 | .ID: RISCV::GPRX7RegClassID, |
| 2720 | .CopyCost: 1, /* CopyCost */ |
| 2721 | .Allocatable: true, /* Allocatable */ |
| 2722 | .BaseClass: false, |
| 2723 | offsetof(RISCVRegisterClassStorage, SubClassMasks[655]) - 43 * sizeof(MCRegisterClass), |
| 2724 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[13]) - 43 * sizeof(MCRegisterClass), |
| 2725 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2726 | .AllocationPriority: 0, |
| 2727 | .GlobalPriority: false, |
| 2728 | .TSFlags: 0x00, /* TSFlags */ |
| 2729 | .SpillStackID: 0, /* SpillStackID */ |
| 2730 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2731 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2732 | offsetof(RISCVRegisterClassStorage, SuperClasses[209]) - 43 * sizeof(MCRegisterClass), |
| 2733 | .SuperClassesSize: 13 |
| 2734 | }, |
| 2735 | { |
| 2736 | offsetof(RISCVRegisterClassStorage, Regs[723]) - 44 * sizeof(MCRegisterClass), |
| 2737 | offsetof(RISCVRegisterClassStorage, BitSets[125]) - 44 * sizeof(MCRegisterClass), |
| 2738 | .NameIdx: 2656, |
| 2739 | .RegSizeInBits: 0, |
| 2740 | .RegsSize: 1, |
| 2741 | .RegSetBegin: 70, /* MinRegVal */ |
| 2742 | .RegSetSize: 1, /* RegSetSize */ |
| 2743 | .ID: RISCV::SPRegClassID, |
| 2744 | .CopyCost: 1, /* CopyCost */ |
| 2745 | .Allocatable: true, /* Allocatable */ |
| 2746 | .BaseClass: false, |
| 2747 | offsetof(RISCVRegisterClassStorage, SubClassMasks[670]) - 44 * sizeof(MCRegisterClass), |
| 2748 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[10]) - 44 * sizeof(MCRegisterClass), |
| 2749 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2750 | .AllocationPriority: 0, |
| 2751 | .GlobalPriority: false, |
| 2752 | .TSFlags: 0x00, /* TSFlags */ |
| 2753 | .SpillStackID: 0, /* SpillStackID */ |
| 2754 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2755 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2756 | offsetof(RISCVRegisterClassStorage, SuperClasses[222]) - 44 * sizeof(MCRegisterClass), |
| 2757 | .SuperClassesSize: 5 |
| 2758 | }, |
| 2759 | { |
| 2760 | offsetof(RISCVRegisterClassStorage, Regs[724]) - 45 * sizeof(MCRegisterClass), |
| 2761 | offsetof(RISCVRegisterClassStorage, BitSets[126]) - 45 * sizeof(MCRegisterClass), |
| 2762 | .NameIdx: 1300, |
| 2763 | .RegSizeInBits: 0, |
| 2764 | .RegsSize: 1, |
| 2765 | .RegSetBegin: 4, /* MinRegVal */ |
| 2766 | .RegSetSize: 1, /* RegSetSize */ |
| 2767 | .ID: RISCV::anonymous_15061RegClassID, |
| 2768 | .CopyCost: 1, /* CopyCost */ |
| 2769 | .Allocatable: false, /* Allocatable */ |
| 2770 | .BaseClass: false, |
| 2771 | offsetof(RISCVRegisterClassStorage, SubClassMasks[685]) - 45 * sizeof(MCRegisterClass), |
| 2772 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 45 * sizeof(MCRegisterClass), |
| 2773 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 2774 | .AllocationPriority: 0, |
| 2775 | .GlobalPriority: false, |
| 2776 | .TSFlags: 0x00, /* TSFlags */ |
| 2777 | .SpillStackID: 0, /* SpillStackID */ |
| 2778 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 2779 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 2780 | offsetof(RISCVRegisterClassStorage, SuperClasses[227]) - 45 * sizeof(MCRegisterClass), |
| 2781 | .SuperClassesSize: 0 |
| 2782 | }, |
| 2783 | { |
| 2784 | offsetof(RISCVRegisterClassStorage, Regs[725]) - 46 * sizeof(MCRegisterClass), |
| 2785 | offsetof(RISCVRegisterClassStorage, BitSets[127]) - 46 * sizeof(MCRegisterClass), |
| 2786 | .NameIdx: 2785, |
| 2787 | .RegSizeInBits: 0, |
| 2788 | .RegsSize: 16, |
| 2789 | .RegSetBegin: 260, /* MinRegVal */ |
| 2790 | .RegSetSize: 140, /* RegSetSize */ |
| 2791 | .ID: RISCV::GPRPairRegClassID, |
| 2792 | .CopyCost: 2, /* CopyCost */ |
| 2793 | .Allocatable: true, /* Allocatable */ |
| 2794 | .BaseClass: false, |
| 2795 | offsetof(RISCVRegisterClassStorage, SubClassMasks[690]) - 46 * sizeof(MCRegisterClass), |
| 2796 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 46 * sizeof(MCRegisterClass), |
| 2797 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2798 | .AllocationPriority: 0, |
| 2799 | .GlobalPriority: false, |
| 2800 | .TSFlags: 0x00, /* TSFlags */ |
| 2801 | .SpillStackID: 0, /* SpillStackID */ |
| 2802 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2803 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2804 | offsetof(RISCVRegisterClassStorage, SuperClasses[227]) - 46 * sizeof(MCRegisterClass), |
| 2805 | .SuperClassesSize: 0 |
| 2806 | }, |
| 2807 | { |
| 2808 | offsetof(RISCVRegisterClassStorage, Regs[741]) - 47 * sizeof(MCRegisterClass), |
| 2809 | offsetof(RISCVRegisterClassStorage, BitSets[145]) - 47 * sizeof(MCRegisterClass), |
| 2810 | .NameIdx: 828, |
| 2811 | .RegSizeInBits: 0, |
| 2812 | .RegsSize: 15, |
| 2813 | .RegSetBegin: 385, /* MinRegVal */ |
| 2814 | .RegSetSize: 15, /* RegSetSize */ |
| 2815 | .ID: RISCV::GPRPairNoX0RegClassID, |
| 2816 | .CopyCost: 2, /* CopyCost */ |
| 2817 | .Allocatable: true, /* Allocatable */ |
| 2818 | .BaseClass: false, |
| 2819 | offsetof(RISCVRegisterClassStorage, SubClassMasks[695]) - 47 * sizeof(MCRegisterClass), |
| 2820 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 47 * sizeof(MCRegisterClass), |
| 2821 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2822 | .AllocationPriority: 0, |
| 2823 | .GlobalPriority: false, |
| 2824 | .TSFlags: 0x00, /* TSFlags */ |
| 2825 | .SpillStackID: 0, /* SpillStackID */ |
| 2826 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2827 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2828 | offsetof(RISCVRegisterClassStorage, SuperClasses[227]) - 47 * sizeof(MCRegisterClass), |
| 2829 | .SuperClassesSize: 1 |
| 2830 | }, |
| 2831 | { |
| 2832 | offsetof(RISCVRegisterClassStorage, Regs[756]) - 48 * sizeof(MCRegisterClass), |
| 2833 | offsetof(RISCVRegisterClassStorage, BitSets[147]) - 48 * sizeof(MCRegisterClass), |
| 2834 | .NameIdx: 1526, |
| 2835 | .RegSizeInBits: 0, |
| 2836 | .RegsSize: 15, |
| 2837 | .RegSetBegin: 260, /* MinRegVal */ |
| 2838 | .RegSetSize: 140, /* RegSetSize */ |
| 2839 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, |
| 2840 | .CopyCost: 2, /* CopyCost */ |
| 2841 | .Allocatable: true, /* Allocatable */ |
| 2842 | .BaseClass: false, |
| 2843 | offsetof(RISCVRegisterClassStorage, SubClassMasks[700]) - 48 * sizeof(MCRegisterClass), |
| 2844 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 48 * sizeof(MCRegisterClass), |
| 2845 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2846 | .AllocationPriority: 0, |
| 2847 | .GlobalPriority: false, |
| 2848 | .TSFlags: 0x00, /* TSFlags */ |
| 2849 | .SpillStackID: 0, /* SpillStackID */ |
| 2850 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2851 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2852 | offsetof(RISCVRegisterClassStorage, SuperClasses[228]) - 48 * sizeof(MCRegisterClass), |
| 2853 | .SuperClassesSize: 1 |
| 2854 | }, |
| 2855 | { |
| 2856 | offsetof(RISCVRegisterClassStorage, Regs[771]) - 49 * sizeof(MCRegisterClass), |
| 2857 | offsetof(RISCVRegisterClassStorage, BitSets[165]) - 49 * sizeof(MCRegisterClass), |
| 2858 | .NameIdx: 1451, |
| 2859 | .RegSizeInBits: 0, |
| 2860 | .RegsSize: 14, |
| 2861 | .RegSetBegin: 386, /* MinRegVal */ |
| 2862 | .RegSetSize: 14, /* RegSetSize */ |
| 2863 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, |
| 2864 | .CopyCost: 2, /* CopyCost */ |
| 2865 | .Allocatable: true, /* Allocatable */ |
| 2866 | .BaseClass: false, |
| 2867 | offsetof(RISCVRegisterClassStorage, SubClassMasks[705]) - 49 * sizeof(MCRegisterClass), |
| 2868 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 49 * sizeof(MCRegisterClass), |
| 2869 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2870 | .AllocationPriority: 0, |
| 2871 | .GlobalPriority: false, |
| 2872 | .TSFlags: 0x00, /* TSFlags */ |
| 2873 | .SpillStackID: 0, /* SpillStackID */ |
| 2874 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2875 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2876 | offsetof(RISCVRegisterClassStorage, SuperClasses[229]) - 49 * sizeof(MCRegisterClass), |
| 2877 | .SuperClassesSize: 3 |
| 2878 | }, |
| 2879 | { |
| 2880 | offsetof(RISCVRegisterClassStorage, Regs[785]) - 50 * sizeof(MCRegisterClass), |
| 2881 | offsetof(RISCVRegisterClassStorage, BitSets[167]) - 50 * sizeof(MCRegisterClass), |
| 2882 | .NameIdx: 1228, |
| 2883 | .RegSizeInBits: 0, |
| 2884 | .RegsSize: 14, |
| 2885 | .RegSetBegin: 385, /* MinRegVal */ |
| 2886 | .RegSetSize: 14, /* RegSetSize */ |
| 2887 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, |
| 2888 | .CopyCost: 2, /* CopyCost */ |
| 2889 | .Allocatable: true, /* Allocatable */ |
| 2890 | .BaseClass: false, |
| 2891 | offsetof(RISCVRegisterClassStorage, SubClassMasks[710]) - 50 * sizeof(MCRegisterClass), |
| 2892 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 50 * sizeof(MCRegisterClass), |
| 2893 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2894 | .AllocationPriority: 0, |
| 2895 | .GlobalPriority: false, |
| 2896 | .TSFlags: 0x00, /* TSFlags */ |
| 2897 | .SpillStackID: 0, /* SpillStackID */ |
| 2898 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2899 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2900 | offsetof(RISCVRegisterClassStorage, SuperClasses[232]) - 50 * sizeof(MCRegisterClass), |
| 2901 | .SuperClassesSize: 2 |
| 2902 | }, |
| 2903 | { |
| 2904 | offsetof(RISCVRegisterClassStorage, Regs[799]) - 51 * sizeof(MCRegisterClass), |
| 2905 | offsetof(RISCVRegisterClassStorage, BitSets[169]) - 51 * sizeof(MCRegisterClass), |
| 2906 | .NameIdx: 2688, |
| 2907 | .RegSizeInBits: 0, |
| 2908 | .RegsSize: 13, |
| 2909 | .RegSetBegin: 387, /* MinRegVal */ |
| 2910 | .RegSetSize: 13, /* RegSetSize */ |
| 2911 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, |
| 2912 | .CopyCost: 2, /* CopyCost */ |
| 2913 | .Allocatable: true, /* Allocatable */ |
| 2914 | .BaseClass: false, |
| 2915 | offsetof(RISCVRegisterClassStorage, SubClassMasks[715]) - 51 * sizeof(MCRegisterClass), |
| 2916 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 51 * sizeof(MCRegisterClass), |
| 2917 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2918 | .AllocationPriority: 0, |
| 2919 | .GlobalPriority: false, |
| 2920 | .TSFlags: 0x00, /* TSFlags */ |
| 2921 | .SpillStackID: 0, /* SpillStackID */ |
| 2922 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2923 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2924 | offsetof(RISCVRegisterClassStorage, SuperClasses[234]) - 51 * sizeof(MCRegisterClass), |
| 2925 | .SuperClassesSize: 4 |
| 2926 | }, |
| 2927 | { |
| 2928 | offsetof(RISCVRegisterClassStorage, Regs[812]) - 52 * sizeof(MCRegisterClass), |
| 2929 | offsetof(RISCVRegisterClassStorage, BitSets[171]) - 52 * sizeof(MCRegisterClass), |
| 2930 | .NameIdx: 1185, |
| 2931 | .RegSizeInBits: 0, |
| 2932 | .RegsSize: 13, |
| 2933 | .RegSetBegin: 386, /* MinRegVal */ |
| 2934 | .RegSetSize: 13, /* RegSetSize */ |
| 2935 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, |
| 2936 | .CopyCost: 2, /* CopyCost */ |
| 2937 | .Allocatable: true, /* Allocatable */ |
| 2938 | .BaseClass: false, |
| 2939 | offsetof(RISCVRegisterClassStorage, SubClassMasks[720]) - 52 * sizeof(MCRegisterClass), |
| 2940 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 52 * sizeof(MCRegisterClass), |
| 2941 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2942 | .AllocationPriority: 0, |
| 2943 | .GlobalPriority: false, |
| 2944 | .TSFlags: 0x00, /* TSFlags */ |
| 2945 | .SpillStackID: 0, /* SpillStackID */ |
| 2946 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2947 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2948 | offsetof(RISCVRegisterClassStorage, SuperClasses[238]) - 52 * sizeof(MCRegisterClass), |
| 2949 | .SuperClassesSize: 5 |
| 2950 | }, |
| 2951 | { |
| 2952 | offsetof(RISCVRegisterClassStorage, Regs[825]) - 53 * sizeof(MCRegisterClass), |
| 2953 | offsetof(RISCVRegisterClassStorage, BitSets[173]) - 53 * sizeof(MCRegisterClass), |
| 2954 | .NameIdx: 2152, |
| 2955 | .RegSizeInBits: 0, |
| 2956 | .RegsSize: 12, |
| 2957 | .RegSetBegin: 388, /* MinRegVal */ |
| 2958 | .RegSetSize: 12, /* RegSetSize */ |
| 2959 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, |
| 2960 | .CopyCost: 2, /* CopyCost */ |
| 2961 | .Allocatable: true, /* Allocatable */ |
| 2962 | .BaseClass: false, |
| 2963 | offsetof(RISCVRegisterClassStorage, SubClassMasks[725]) - 53 * sizeof(MCRegisterClass), |
| 2964 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 53 * sizeof(MCRegisterClass), |
| 2965 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2966 | .AllocationPriority: 0, |
| 2967 | .GlobalPriority: false, |
| 2968 | .TSFlags: 0x00, /* TSFlags */ |
| 2969 | .SpillStackID: 0, /* SpillStackID */ |
| 2970 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2971 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2972 | offsetof(RISCVRegisterClassStorage, SuperClasses[243]) - 53 * sizeof(MCRegisterClass), |
| 2973 | .SuperClassesSize: 5 |
| 2974 | }, |
| 2975 | { |
| 2976 | offsetof(RISCVRegisterClassStorage, Regs[837]) - 54 * sizeof(MCRegisterClass), |
| 2977 | offsetof(RISCVRegisterClassStorage, BitSets[175]) - 54 * sizeof(MCRegisterClass), |
| 2978 | .NameIdx: 1089, |
| 2979 | .RegSizeInBits: 0, |
| 2980 | .RegsSize: 12, |
| 2981 | .RegSetBegin: 387, /* MinRegVal */ |
| 2982 | .RegSetSize: 12, /* RegSetSize */ |
| 2983 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, |
| 2984 | .CopyCost: 2, /* CopyCost */ |
| 2985 | .Allocatable: true, /* Allocatable */ |
| 2986 | .BaseClass: false, |
| 2987 | offsetof(RISCVRegisterClassStorage, SubClassMasks[730]) - 54 * sizeof(MCRegisterClass), |
| 2988 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 54 * sizeof(MCRegisterClass), |
| 2989 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 2990 | .AllocationPriority: 0, |
| 2991 | .GlobalPriority: false, |
| 2992 | .TSFlags: 0x00, /* TSFlags */ |
| 2993 | .SpillStackID: 0, /* SpillStackID */ |
| 2994 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 2995 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 2996 | offsetof(RISCVRegisterClassStorage, SuperClasses[248]) - 54 * sizeof(MCRegisterClass), |
| 2997 | .SuperClassesSize: 7 |
| 2998 | }, |
| 2999 | { |
| 3000 | offsetof(RISCVRegisterClassStorage, Regs[849]) - 55 * sizeof(MCRegisterClass), |
| 3001 | offsetof(RISCVRegisterClassStorage, BitSets[177]) - 55 * sizeof(MCRegisterClass), |
| 3002 | .NameIdx: 983, |
| 3003 | .RegSizeInBits: 0, |
| 3004 | .RegsSize: 11, |
| 3005 | .RegSetBegin: 388, /* MinRegVal */ |
| 3006 | .RegSetSize: 11, /* RegSetSize */ |
| 3007 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 3008 | .CopyCost: 2, /* CopyCost */ |
| 3009 | .Allocatable: true, /* Allocatable */ |
| 3010 | .BaseClass: false, |
| 3011 | offsetof(RISCVRegisterClassStorage, SubClassMasks[735]) - 55 * sizeof(MCRegisterClass), |
| 3012 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 55 * sizeof(MCRegisterClass), |
| 3013 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3014 | .AllocationPriority: 0, |
| 3015 | .GlobalPriority: false, |
| 3016 | .TSFlags: 0x00, /* TSFlags */ |
| 3017 | .SpillStackID: 0, /* SpillStackID */ |
| 3018 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3019 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3020 | offsetof(RISCVRegisterClassStorage, SuperClasses[255]) - 55 * sizeof(MCRegisterClass), |
| 3021 | .SuperClassesSize: 9 |
| 3022 | }, |
| 3023 | { |
| 3024 | offsetof(RISCVRegisterClassStorage, Regs[860]) - 56 * sizeof(MCRegisterClass), |
| 3025 | offsetof(RISCVRegisterClassStorage, BitSets[179]) - 56 * sizeof(MCRegisterClass), |
| 3026 | .NameIdx: 2544, |
| 3027 | .RegSizeInBits: 0, |
| 3028 | .RegsSize: 7, |
| 3029 | .RegSetBegin: 387, /* MinRegVal */ |
| 3030 | .RegSetSize: 13, /* RegSetSize */ |
| 3031 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID, |
| 3032 | .CopyCost: 2, /* CopyCost */ |
| 3033 | .Allocatable: true, /* Allocatable */ |
| 3034 | .BaseClass: false, |
| 3035 | offsetof(RISCVRegisterClassStorage, SubClassMasks[740]) - 56 * sizeof(MCRegisterClass), |
| 3036 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 56 * sizeof(MCRegisterClass), |
| 3037 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3038 | .AllocationPriority: 0, |
| 3039 | .GlobalPriority: false, |
| 3040 | .TSFlags: 0x00, /* TSFlags */ |
| 3041 | .SpillStackID: 0, /* SpillStackID */ |
| 3042 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3043 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3044 | offsetof(RISCVRegisterClassStorage, SuperClasses[264]) - 56 * sizeof(MCRegisterClass), |
| 3045 | .SuperClassesSize: 5 |
| 3046 | }, |
| 3047 | { |
| 3048 | offsetof(RISCVRegisterClassStorage, Regs[867]) - 57 * sizeof(MCRegisterClass), |
| 3049 | offsetof(RISCVRegisterClassStorage, BitSets[181]) - 57 * sizeof(MCRegisterClass), |
| 3050 | .NameIdx: 2367, |
| 3051 | .RegSizeInBits: 0, |
| 3052 | .RegsSize: 6, |
| 3053 | .RegSetBegin: 387, /* MinRegVal */ |
| 3054 | .RegSetSize: 12, /* RegSetSize */ |
| 3055 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID, |
| 3056 | .CopyCost: 2, /* CopyCost */ |
| 3057 | .Allocatable: true, /* Allocatable */ |
| 3058 | .BaseClass: false, |
| 3059 | offsetof(RISCVRegisterClassStorage, SubClassMasks[745]) - 57 * sizeof(MCRegisterClass), |
| 3060 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 57 * sizeof(MCRegisterClass), |
| 3061 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3062 | .AllocationPriority: 0, |
| 3063 | .GlobalPriority: false, |
| 3064 | .TSFlags: 0x00, /* TSFlags */ |
| 3065 | .SpillStackID: 0, /* SpillStackID */ |
| 3066 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3067 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3068 | offsetof(RISCVRegisterClassStorage, SuperClasses[269]) - 57 * sizeof(MCRegisterClass), |
| 3069 | .SuperClassesSize: 9 |
| 3070 | }, |
| 3071 | { |
| 3072 | offsetof(RISCVRegisterClassStorage, Regs[873]) - 58 * sizeof(MCRegisterClass), |
| 3073 | offsetof(RISCVRegisterClassStorage, BitSets[183]) - 58 * sizeof(MCRegisterClass), |
| 3074 | .NameIdx: 2076, |
| 3075 | .RegSizeInBits: 0, |
| 3076 | .RegsSize: 6, |
| 3077 | .RegSetBegin: 389, /* MinRegVal */ |
| 3078 | .RegSetSize: 11, /* RegSetSize */ |
| 3079 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRTCNonX7RegClassID, |
| 3080 | .CopyCost: 2, /* CopyCost */ |
| 3081 | .Allocatable: true, /* Allocatable */ |
| 3082 | .BaseClass: false, |
| 3083 | offsetof(RISCVRegisterClassStorage, SubClassMasks[750]) - 58 * sizeof(MCRegisterClass), |
| 3084 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 58 * sizeof(MCRegisterClass), |
| 3085 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3086 | .AllocationPriority: 0, |
| 3087 | .GlobalPriority: false, |
| 3088 | .TSFlags: 0x00, /* TSFlags */ |
| 3089 | .SpillStackID: 0, /* SpillStackID */ |
| 3090 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3091 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3092 | offsetof(RISCVRegisterClassStorage, SuperClasses[278]) - 58 * sizeof(MCRegisterClass), |
| 3093 | .SuperClassesSize: 7 |
| 3094 | }, |
| 3095 | { |
| 3096 | offsetof(RISCVRegisterClassStorage, Regs[879]) - 59 * sizeof(MCRegisterClass), |
| 3097 | offsetof(RISCVRegisterClassStorage, BitSets[185]) - 59 * sizeof(MCRegisterClass), |
| 3098 | .NameIdx: 1974, |
| 3099 | .RegSizeInBits: 0, |
| 3100 | .RegsSize: 5, |
| 3101 | .RegSetBegin: 389, /* MinRegVal */ |
| 3102 | .RegSetSize: 10, /* RegSetSize */ |
| 3103 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7RegClassID, |
| 3104 | .CopyCost: 2, /* CopyCost */ |
| 3105 | .Allocatable: true, /* Allocatable */ |
| 3106 | .BaseClass: false, |
| 3107 | offsetof(RISCVRegisterClassStorage, SubClassMasks[755]) - 59 * sizeof(MCRegisterClass), |
| 3108 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 59 * sizeof(MCRegisterClass), |
| 3109 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3110 | .AllocationPriority: 0, |
| 3111 | .GlobalPriority: false, |
| 3112 | .TSFlags: 0x00, /* TSFlags */ |
| 3113 | .SpillStackID: 0, /* SpillStackID */ |
| 3114 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3115 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3116 | offsetof(RISCVRegisterClassStorage, SuperClasses[285]) - 59 * sizeof(MCRegisterClass), |
| 3117 | .SuperClassesSize: 13 |
| 3118 | }, |
| 3119 | { |
| 3120 | offsetof(RISCVRegisterClassStorage, Regs[884]) - 60 * sizeof(MCRegisterClass), |
| 3121 | offsetof(RISCVRegisterClassStorage, BitSets[187]) - 60 * sizeof(MCRegisterClass), |
| 3122 | .NameIdx: 2611, |
| 3123 | .RegSizeInBits: 0, |
| 3124 | .RegsSize: 4, |
| 3125 | .RegSetBegin: 388, /* MinRegVal */ |
| 3126 | .RegSetSize: 4, /* RegSetSize */ |
| 3127 | .ID: RISCV::GPRPairCRegClassID, |
| 3128 | .CopyCost: 2, /* CopyCost */ |
| 3129 | .Allocatable: true, /* Allocatable */ |
| 3130 | .BaseClass: false, |
| 3131 | offsetof(RISCVRegisterClassStorage, SubClassMasks[760]) - 60 * sizeof(MCRegisterClass), |
| 3132 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 60 * sizeof(MCRegisterClass), |
| 3133 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3134 | .AllocationPriority: 0, |
| 3135 | .GlobalPriority: false, |
| 3136 | .TSFlags: 0x00, /* TSFlags */ |
| 3137 | .SpillStackID: 0, /* SpillStackID */ |
| 3138 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3139 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3140 | offsetof(RISCVRegisterClassStorage, SuperClasses[298]) - 60 * sizeof(MCRegisterClass), |
| 3141 | .SuperClassesSize: 10 |
| 3142 | }, |
| 3143 | { |
| 3144 | offsetof(RISCVRegisterClassStorage, Regs[888]) - 61 * sizeof(MCRegisterClass), |
| 3145 | offsetof(RISCVRegisterClassStorage, BitSets[188]) - 61 * sizeof(MCRegisterClass), |
| 3146 | .NameIdx: 1839, |
| 3147 | .RegSizeInBits: 0, |
| 3148 | .RegsSize: 4, |
| 3149 | .RegSetBegin: 388, /* MinRegVal */ |
| 3150 | .RegSetSize: 8, /* RegSetSize */ |
| 3151 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRS07RegClassID, |
| 3152 | .CopyCost: 2, /* CopyCost */ |
| 3153 | .Allocatable: true, /* Allocatable */ |
| 3154 | .BaseClass: false, |
| 3155 | offsetof(RISCVRegisterClassStorage, SubClassMasks[765]) - 61 * sizeof(MCRegisterClass), |
| 3156 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 61 * sizeof(MCRegisterClass), |
| 3157 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3158 | .AllocationPriority: 0, |
| 3159 | .GlobalPriority: false, |
| 3160 | .TSFlags: 0x00, /* TSFlags */ |
| 3161 | .SpillStackID: 0, /* SpillStackID */ |
| 3162 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3163 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3164 | offsetof(RISCVRegisterClassStorage, SuperClasses[308]) - 61 * sizeof(MCRegisterClass), |
| 3165 | .SuperClassesSize: 10 |
| 3166 | }, |
| 3167 | { |
| 3168 | offsetof(RISCVRegisterClassStorage, Regs[892]) - 62 * sizeof(MCRegisterClass), |
| 3169 | offsetof(RISCVRegisterClassStorage, BitSets[189]) - 62 * sizeof(MCRegisterClass), |
| 3170 | .NameIdx: 2459, |
| 3171 | .RegSizeInBits: 0, |
| 3172 | .RegsSize: 3, |
| 3173 | .RegSetBegin: 389, /* MinRegVal */ |
| 3174 | .RegSetSize: 3, /* RegSetSize */ |
| 3175 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID, |
| 3176 | .CopyCost: 2, /* CopyCost */ |
| 3177 | .Allocatable: true, /* Allocatable */ |
| 3178 | .BaseClass: false, |
| 3179 | offsetof(RISCVRegisterClassStorage, SubClassMasks[770]) - 62 * sizeof(MCRegisterClass), |
| 3180 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 62 * sizeof(MCRegisterClass), |
| 3181 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3182 | .AllocationPriority: 0, |
| 3183 | .GlobalPriority: false, |
| 3184 | .TSFlags: 0x00, /* TSFlags */ |
| 3185 | .SpillStackID: 0, /* SpillStackID */ |
| 3186 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3187 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3188 | offsetof(RISCVRegisterClassStorage, SuperClasses[318]) - 62 * sizeof(MCRegisterClass), |
| 3189 | .SuperClassesSize: 15 |
| 3190 | }, |
| 3191 | { |
| 3192 | offsetof(RISCVRegisterClassStorage, Regs[895]) - 63 * sizeof(MCRegisterClass), |
| 3193 | offsetof(RISCVRegisterClassStorage, BitSets[190]) - 63 * sizeof(MCRegisterClass), |
| 3194 | .NameIdx: 740, |
| 3195 | .RegSizeInBits: 0, |
| 3196 | .RegsSize: 1, |
| 3197 | .RegSetBegin: 260, /* MinRegVal */ |
| 3198 | .RegSetSize: 1, /* RegSetSize */ |
| 3199 | .ID: RISCV::GPRPair_with_sub_16_in_GPRF16X0RegClassID, |
| 3200 | .CopyCost: 2, /* CopyCost */ |
| 3201 | .Allocatable: true, /* Allocatable */ |
| 3202 | .BaseClass: false, |
| 3203 | offsetof(RISCVRegisterClassStorage, SubClassMasks[775]) - 63 * sizeof(MCRegisterClass), |
| 3204 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 63 * sizeof(MCRegisterClass), |
| 3205 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3206 | .AllocationPriority: 0, |
| 3207 | .GlobalPriority: false, |
| 3208 | .TSFlags: 0x00, /* TSFlags */ |
| 3209 | .SpillStackID: 0, /* SpillStackID */ |
| 3210 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3211 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3212 | offsetof(RISCVRegisterClassStorage, SuperClasses[333]) - 63 * sizeof(MCRegisterClass), |
| 3213 | .SuperClassesSize: 2 |
| 3214 | }, |
| 3215 | { |
| 3216 | offsetof(RISCVRegisterClassStorage, Regs[896]) - 64 * sizeof(MCRegisterClass), |
| 3217 | offsetof(RISCVRegisterClassStorage, BitSets[191]) - 64 * sizeof(MCRegisterClass), |
| 3218 | .NameIdx: 1752, |
| 3219 | .RegSizeInBits: 0, |
| 3220 | .RegsSize: 1, |
| 3221 | .RegSetBegin: 388, /* MinRegVal */ |
| 3222 | .RegSetSize: 1, /* RegSetSize */ |
| 3223 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_GPRS07RegClassID, |
| 3224 | .CopyCost: 2, /* CopyCost */ |
| 3225 | .Allocatable: true, /* Allocatable */ |
| 3226 | .BaseClass: false, |
| 3227 | offsetof(RISCVRegisterClassStorage, SubClassMasks[780]) - 64 * sizeof(MCRegisterClass), |
| 3228 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 64 * sizeof(MCRegisterClass), |
| 3229 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3230 | .AllocationPriority: 0, |
| 3231 | .GlobalPriority: false, |
| 3232 | .TSFlags: 0x00, /* TSFlags */ |
| 3233 | .SpillStackID: 0, /* SpillStackID */ |
| 3234 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3235 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3236 | offsetof(RISCVRegisterClassStorage, SuperClasses[335]) - 64 * sizeof(MCRegisterClass), |
| 3237 | .SuperClassesSize: 12 |
| 3238 | }, |
| 3239 | { |
| 3240 | offsetof(RISCVRegisterClassStorage, Regs[897]) - 65 * sizeof(MCRegisterClass), |
| 3241 | offsetof(RISCVRegisterClassStorage, BitSets[192]) - 65 * sizeof(MCRegisterClass), |
| 3242 | .NameIdx: 2627, |
| 3243 | .RegSizeInBits: 0, |
| 3244 | .RegsSize: 1, |
| 3245 | .RegSetBegin: 385, /* MinRegVal */ |
| 3246 | .RegSetSize: 1, /* RegSetSize */ |
| 3247 | .ID: RISCV::GPRPair_with_sub_gpr_even_in_SPRegClassID, |
| 3248 | .CopyCost: 2, /* CopyCost */ |
| 3249 | .Allocatable: true, /* Allocatable */ |
| 3250 | .BaseClass: false, |
| 3251 | offsetof(RISCVRegisterClassStorage, SubClassMasks[785]) - 65 * sizeof(MCRegisterClass), |
| 3252 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 65 * sizeof(MCRegisterClass), |
| 3253 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3254 | .AllocationPriority: 0, |
| 3255 | .GlobalPriority: false, |
| 3256 | .TSFlags: 0x00, /* TSFlags */ |
| 3257 | .SpillStackID: 0, /* SpillStackID */ |
| 3258 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3259 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3260 | offsetof(RISCVRegisterClassStorage, SuperClasses[347]) - 65 * sizeof(MCRegisterClass), |
| 3261 | .SuperClassesSize: 3 |
| 3262 | }, |
| 3263 | { |
| 3264 | offsetof(RISCVRegisterClassStorage, Regs[898]) - 66 * sizeof(MCRegisterClass), |
| 3265 | offsetof(RISCVRegisterClassStorage, BitSets[193]) - 66 * sizeof(MCRegisterClass), |
| 3266 | .NameIdx: 1630, |
| 3267 | .RegSizeInBits: 0, |
| 3268 | .RegsSize: 1, |
| 3269 | .RegSetBegin: 386, /* MinRegVal */ |
| 3270 | .RegSetSize: 1, /* RegSetSize */ |
| 3271 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClassID, |
| 3272 | .CopyCost: 2, /* CopyCost */ |
| 3273 | .Allocatable: true, /* Allocatable */ |
| 3274 | .BaseClass: false, |
| 3275 | offsetof(RISCVRegisterClassStorage, SubClassMasks[790]) - 66 * sizeof(MCRegisterClass), |
| 3276 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 66 * sizeof(MCRegisterClass), |
| 3277 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3278 | .AllocationPriority: 0, |
| 3279 | .GlobalPriority: false, |
| 3280 | .TSFlags: 0x00, /* TSFlags */ |
| 3281 | .SpillStackID: 0, /* SpillStackID */ |
| 3282 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3283 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3284 | offsetof(RISCVRegisterClassStorage, SuperClasses[350]) - 66 * sizeof(MCRegisterClass), |
| 3285 | .SuperClassesSize: 6 |
| 3286 | }, |
| 3287 | { |
| 3288 | offsetof(RISCVRegisterClassStorage, Regs[899]) - 67 * sizeof(MCRegisterClass), |
| 3289 | offsetof(RISCVRegisterClassStorage, BitSets[194]) - 67 * sizeof(MCRegisterClass), |
| 3290 | .NameIdx: 1908, |
| 3291 | .RegSizeInBits: 0, |
| 3292 | .RegsSize: 1, |
| 3293 | .RegSetBegin: 387, /* MinRegVal */ |
| 3294 | .RegSetSize: 1, /* RegSetSize */ |
| 3295 | .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRX7RegClassID, |
| 3296 | .CopyCost: 2, /* CopyCost */ |
| 3297 | .Allocatable: true, /* Allocatable */ |
| 3298 | .BaseClass: false, |
| 3299 | offsetof(RISCVRegisterClassStorage, SubClassMasks[795]) - 67 * sizeof(MCRegisterClass), |
| 3300 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 67 * sizeof(MCRegisterClass), |
| 3301 | .LaneMask: LaneBitmask(0x0000000000000201), |
| 3302 | .AllocationPriority: 0, |
| 3303 | .GlobalPriority: false, |
| 3304 | .TSFlags: 0x00, /* TSFlags */ |
| 3305 | .SpillStackID: 0, /* SpillStackID */ |
| 3306 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 3307 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 3308 | offsetof(RISCVRegisterClassStorage, SuperClasses[356]) - 67 * sizeof(MCRegisterClass), |
| 3309 | .SuperClassesSize: 10 |
| 3310 | }, |
| 3311 | { |
| 3312 | offsetof(RISCVRegisterClassStorage, Regs[900]) - 68 * sizeof(MCRegisterClass), |
| 3313 | offsetof(RISCVRegisterClassStorage, BitSets[195]) - 68 * sizeof(MCRegisterClass), |
| 3314 | .NameIdx: 1597, |
| 3315 | .RegSizeInBits: 64, |
| 3316 | .RegsSize: 32, |
| 3317 | .RegSetBegin: 100, /* MinRegVal */ |
| 3318 | .RegSetSize: 32, /* RegSetSize */ |
| 3319 | .ID: RISCV::FPR64RegClassID, |
| 3320 | .CopyCost: 1, /* CopyCost */ |
| 3321 | .Allocatable: true, /* Allocatable */ |
| 3322 | .BaseClass: false, |
| 3323 | offsetof(RISCVRegisterClassStorage, SubClassMasks[800]) - 68 * sizeof(MCRegisterClass), |
| 3324 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[4]) - 68 * sizeof(MCRegisterClass), |
| 3325 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3326 | .AllocationPriority: 0, |
| 3327 | .GlobalPriority: false, |
| 3328 | .TSFlags: 0x00, /* TSFlags */ |
| 3329 | .SpillStackID: 0, /* SpillStackID */ |
| 3330 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3331 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3332 | offsetof(RISCVRegisterClassStorage, SuperClasses[366]) - 68 * sizeof(MCRegisterClass), |
| 3333 | .SuperClassesSize: 0 |
| 3334 | }, |
| 3335 | { |
| 3336 | offsetof(RISCVRegisterClassStorage, Regs[932]) - 69 * sizeof(MCRegisterClass), |
| 3337 | offsetof(RISCVRegisterClassStorage, BitSets[199]) - 69 * sizeof(MCRegisterClass), |
| 3338 | .NameIdx: 2775, |
| 3339 | .RegSizeInBits: 64, |
| 3340 | .RegsSize: 32, |
| 3341 | .RegSetBegin: 36, /* MinRegVal */ |
| 3342 | .RegSetSize: 32, /* RegSetSize */ |
| 3343 | .ID: RISCV::VRRegClassID, |
| 3344 | .CopyCost: 1, /* CopyCost */ |
| 3345 | .Allocatable: true, /* Allocatable */ |
| 3346 | .BaseClass: false, |
| 3347 | offsetof(RISCVRegisterClassStorage, SubClassMasks[810]) - 69 * sizeof(MCRegisterClass), |
| 3348 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 69 * sizeof(MCRegisterClass), |
| 3349 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3350 | .AllocationPriority: 0, |
| 3351 | .GlobalPriority: false, |
| 3352 | .TSFlags: 0x01, /* TSFlags */ |
| 3353 | .SpillStackID: 0, /* SpillStackID */ |
| 3354 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3355 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3356 | offsetof(RISCVRegisterClassStorage, SuperClasses[366]) - 69 * sizeof(MCRegisterClass), |
| 3357 | .SuperClassesSize: 0 |
| 3358 | }, |
| 3359 | { |
| 3360 | offsetof(RISCVRegisterClassStorage, Regs[964]) - 70 * sizeof(MCRegisterClass), |
| 3361 | offsetof(RISCVRegisterClassStorage, BitSets[203]) - 70 * sizeof(MCRegisterClass), |
| 3362 | .NameIdx: 2762, |
| 3363 | .RegSizeInBits: 0, |
| 3364 | .RegsSize: 32, |
| 3365 | .RegSetBegin: 293, /* MinRegVal */ |
| 3366 | .RegSetSize: 32, /* RegSetSize */ |
| 3367 | .ID: RISCV::YGPRRegClassID, |
| 3368 | .CopyCost: 1, /* CopyCost */ |
| 3369 | .Allocatable: true, /* Allocatable */ |
| 3370 | .BaseClass: false, |
| 3371 | offsetof(RISCVRegisterClassStorage, SubClassMasks[855]) - 70 * sizeof(MCRegisterClass), |
| 3372 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 70 * sizeof(MCRegisterClass), |
| 3373 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3374 | .AllocationPriority: 0, |
| 3375 | .GlobalPriority: false, |
| 3376 | .TSFlags: 0x00, /* TSFlags */ |
| 3377 | .SpillStackID: 0, /* SpillStackID */ |
| 3378 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3379 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3380 | offsetof(RISCVRegisterClassStorage, SuperClasses[366]) - 70 * sizeof(MCRegisterClass), |
| 3381 | .SuperClassesSize: 0 |
| 3382 | }, |
| 3383 | { |
| 3384 | offsetof(RISCVRegisterClassStorage, Regs[996]) - 71 * sizeof(MCRegisterClass), |
| 3385 | offsetof(RISCVRegisterClassStorage, BitSets[207]) - 71 * sizeof(MCRegisterClass), |
| 3386 | .NameIdx: 2620, |
| 3387 | .RegSizeInBits: 64, |
| 3388 | .RegsSize: 32, |
| 3389 | .RegSetBegin: 36, /* MinRegVal */ |
| 3390 | .RegSetSize: 32, /* RegSetSize */ |
| 3391 | .ID: RISCV::ZZZ_VMRegClassID, |
| 3392 | .CopyCost: 1, /* CopyCost */ |
| 3393 | .Allocatable: true, /* Allocatable */ |
| 3394 | .BaseClass: false, |
| 3395 | offsetof(RISCVRegisterClassStorage, SubClassMasks[860]) - 71 * sizeof(MCRegisterClass), |
| 3396 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 71 * sizeof(MCRegisterClass), |
| 3397 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3398 | .AllocationPriority: 0, |
| 3399 | .GlobalPriority: false, |
| 3400 | .TSFlags: 0x01, /* TSFlags */ |
| 3401 | .SpillStackID: 0, /* SpillStackID */ |
| 3402 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3403 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3404 | offsetof(RISCVRegisterClassStorage, SuperClasses[366]) - 71 * sizeof(MCRegisterClass), |
| 3405 | .SuperClassesSize: 4 |
| 3406 | }, |
| 3407 | { |
| 3408 | offsetof(RISCVRegisterClassStorage, Regs[1028]) - 72 * sizeof(MCRegisterClass), |
| 3409 | offsetof(RISCVRegisterClassStorage, BitSets[211]) - 72 * sizeof(MCRegisterClass), |
| 3410 | .NameIdx: 1410, |
| 3411 | .RegSizeInBits: 64, |
| 3412 | .RegsSize: 32, |
| 3413 | .RegSetBegin: 36, /* MinRegVal */ |
| 3414 | .RegSetSize: 32, /* RegSetSize */ |
| 3415 | .ID: RISCV::ZZZ_VRMF2RegClassID, |
| 3416 | .CopyCost: 1, /* CopyCost */ |
| 3417 | .Allocatable: true, /* Allocatable */ |
| 3418 | .BaseClass: false, |
| 3419 | offsetof(RISCVRegisterClassStorage, SubClassMasks[905]) - 72 * sizeof(MCRegisterClass), |
| 3420 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 72 * sizeof(MCRegisterClass), |
| 3421 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3422 | .AllocationPriority: 0, |
| 3423 | .GlobalPriority: false, |
| 3424 | .TSFlags: 0x01, /* TSFlags */ |
| 3425 | .SpillStackID: 0, /* SpillStackID */ |
| 3426 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3427 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3428 | offsetof(RISCVRegisterClassStorage, SuperClasses[370]) - 72 * sizeof(MCRegisterClass), |
| 3429 | .SuperClassesSize: 4 |
| 3430 | }, |
| 3431 | { |
| 3432 | offsetof(RISCVRegisterClassStorage, Regs[1060]) - 73 * sizeof(MCRegisterClass), |
| 3433 | offsetof(RISCVRegisterClassStorage, BitSets[215]) - 73 * sizeof(MCRegisterClass), |
| 3434 | .NameIdx: 1603, |
| 3435 | .RegSizeInBits: 64, |
| 3436 | .RegsSize: 32, |
| 3437 | .RegSetBegin: 36, /* MinRegVal */ |
| 3438 | .RegSetSize: 32, /* RegSetSize */ |
| 3439 | .ID: RISCV::ZZZ_VRMF4RegClassID, |
| 3440 | .CopyCost: 1, /* CopyCost */ |
| 3441 | .Allocatable: true, /* Allocatable */ |
| 3442 | .BaseClass: false, |
| 3443 | offsetof(RISCVRegisterClassStorage, SubClassMasks[950]) - 73 * sizeof(MCRegisterClass), |
| 3444 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 73 * sizeof(MCRegisterClass), |
| 3445 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3446 | .AllocationPriority: 0, |
| 3447 | .GlobalPriority: false, |
| 3448 | .TSFlags: 0x01, /* TSFlags */ |
| 3449 | .SpillStackID: 0, /* SpillStackID */ |
| 3450 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3451 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3452 | offsetof(RISCVRegisterClassStorage, SuperClasses[374]) - 73 * sizeof(MCRegisterClass), |
| 3453 | .SuperClassesSize: 4 |
| 3454 | }, |
| 3455 | { |
| 3456 | offsetof(RISCVRegisterClassStorage, Regs[1092]) - 74 * sizeof(MCRegisterClass), |
| 3457 | offsetof(RISCVRegisterClassStorage, BitSets[219]) - 74 * sizeof(MCRegisterClass), |
| 3458 | .NameIdx: 2239, |
| 3459 | .RegSizeInBits: 64, |
| 3460 | .RegsSize: 32, |
| 3461 | .RegSetBegin: 36, /* MinRegVal */ |
| 3462 | .RegSetSize: 32, /* RegSetSize */ |
| 3463 | .ID: RISCV::ZZZ_VRMF8RegClassID, |
| 3464 | .CopyCost: 1, /* CopyCost */ |
| 3465 | .Allocatable: true, /* Allocatable */ |
| 3466 | .BaseClass: false, |
| 3467 | offsetof(RISCVRegisterClassStorage, SubClassMasks[995]) - 74 * sizeof(MCRegisterClass), |
| 3468 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 74 * sizeof(MCRegisterClass), |
| 3469 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3470 | .AllocationPriority: 0, |
| 3471 | .GlobalPriority: false, |
| 3472 | .TSFlags: 0x01, /* TSFlags */ |
| 3473 | .SpillStackID: 0, /* SpillStackID */ |
| 3474 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3475 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3476 | offsetof(RISCVRegisterClassStorage, SuperClasses[378]) - 74 * sizeof(MCRegisterClass), |
| 3477 | .SuperClassesSize: 4 |
| 3478 | }, |
| 3479 | { |
| 3480 | offsetof(RISCVRegisterClassStorage, Regs[1124]) - 75 * sizeof(MCRegisterClass), |
| 3481 | offsetof(RISCVRegisterClassStorage, BitSets[223]) - 75 * sizeof(MCRegisterClass), |
| 3482 | .NameIdx: 695, |
| 3483 | .RegSizeInBits: 64, |
| 3484 | .RegsSize: 31, |
| 3485 | .RegSetBegin: 37, /* MinRegVal */ |
| 3486 | .RegSetSize: 31, /* RegSetSize */ |
| 3487 | .ID: RISCV::VRNoV0RegClassID, |
| 3488 | .CopyCost: 1, /* CopyCost */ |
| 3489 | .Allocatable: true, /* Allocatable */ |
| 3490 | .BaseClass: false, |
| 3491 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1040]) - 75 * sizeof(MCRegisterClass), |
| 3492 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 75 * sizeof(MCRegisterClass), |
| 3493 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3494 | .AllocationPriority: 0, |
| 3495 | .GlobalPriority: false, |
| 3496 | .TSFlags: 0x01, /* TSFlags */ |
| 3497 | .SpillStackID: 0, /* SpillStackID */ |
| 3498 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3499 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3500 | offsetof(RISCVRegisterClassStorage, SuperClasses[382]) - 75 * sizeof(MCRegisterClass), |
| 3501 | .SuperClassesSize: 5 |
| 3502 | }, |
| 3503 | { |
| 3504 | offsetof(RISCVRegisterClassStorage, Regs[1155]) - 76 * sizeof(MCRegisterClass), |
| 3505 | offsetof(RISCVRegisterClassStorage, BitSets[227]) - 76 * sizeof(MCRegisterClass), |
| 3506 | .NameIdx: 789, |
| 3507 | .RegSizeInBits: 0, |
| 3508 | .RegsSize: 31, |
| 3509 | .RegSetBegin: 294, /* MinRegVal */ |
| 3510 | .RegSetSize: 31, /* RegSetSize */ |
| 3511 | .ID: RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, |
| 3512 | .CopyCost: 1, /* CopyCost */ |
| 3513 | .Allocatable: true, /* Allocatable */ |
| 3514 | .BaseClass: false, |
| 3515 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1085]) - 76 * sizeof(MCRegisterClass), |
| 3516 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 76 * sizeof(MCRegisterClass), |
| 3517 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3518 | .AllocationPriority: 0, |
| 3519 | .GlobalPriority: false, |
| 3520 | .TSFlags: 0x00, /* TSFlags */ |
| 3521 | .SpillStackID: 0, /* SpillStackID */ |
| 3522 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3523 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3524 | offsetof(RISCVRegisterClassStorage, SuperClasses[387]) - 76 * sizeof(MCRegisterClass), |
| 3525 | .SuperClassesSize: 1 |
| 3526 | }, |
| 3527 | { |
| 3528 | offsetof(RISCVRegisterClassStorage, Regs[1186]) - 77 * sizeof(MCRegisterClass), |
| 3529 | offsetof(RISCVRegisterClassStorage, BitSets[231]) - 77 * sizeof(MCRegisterClass), |
| 3530 | .NameIdx: 1563, |
| 3531 | .RegSizeInBits: 0, |
| 3532 | .RegsSize: 31, |
| 3533 | .RegSetBegin: 293, /* MinRegVal */ |
| 3534 | .RegSetSize: 32, /* RegSetSize */ |
| 3535 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, |
| 3536 | .CopyCost: 1, /* CopyCost */ |
| 3537 | .Allocatable: true, /* Allocatable */ |
| 3538 | .BaseClass: false, |
| 3539 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1090]) - 77 * sizeof(MCRegisterClass), |
| 3540 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 77 * sizeof(MCRegisterClass), |
| 3541 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3542 | .AllocationPriority: 0, |
| 3543 | .GlobalPriority: false, |
| 3544 | .TSFlags: 0x00, /* TSFlags */ |
| 3545 | .SpillStackID: 0, /* SpillStackID */ |
| 3546 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3547 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3548 | offsetof(RISCVRegisterClassStorage, SuperClasses[388]) - 77 * sizeof(MCRegisterClass), |
| 3549 | .SuperClassesSize: 1 |
| 3550 | }, |
| 3551 | { |
| 3552 | offsetof(RISCVRegisterClassStorage, Regs[1217]) - 78 * sizeof(MCRegisterClass), |
| 3553 | offsetof(RISCVRegisterClassStorage, BitSets[235]) - 78 * sizeof(MCRegisterClass), |
| 3554 | .NameIdx: 1265, |
| 3555 | .RegSizeInBits: 0, |
| 3556 | .RegsSize: 31, |
| 3557 | .RegSetBegin: 293, /* MinRegVal */ |
| 3558 | .RegSetSize: 31, /* RegSetSize */ |
| 3559 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, |
| 3560 | .CopyCost: 1, /* CopyCost */ |
| 3561 | .Allocatable: true, /* Allocatable */ |
| 3562 | .BaseClass: false, |
| 3563 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1095]) - 78 * sizeof(MCRegisterClass), |
| 3564 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 78 * sizeof(MCRegisterClass), |
| 3565 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3566 | .AllocationPriority: 0, |
| 3567 | .GlobalPriority: false, |
| 3568 | .TSFlags: 0x00, /* TSFlags */ |
| 3569 | .SpillStackID: 0, /* SpillStackID */ |
| 3570 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3571 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3572 | offsetof(RISCVRegisterClassStorage, SuperClasses[389]) - 78 * sizeof(MCRegisterClass), |
| 3573 | .SuperClassesSize: 1 |
| 3574 | }, |
| 3575 | { |
| 3576 | offsetof(RISCVRegisterClassStorage, Regs[1248]) - 79 * sizeof(MCRegisterClass), |
| 3577 | offsetof(RISCVRegisterClassStorage, BitSets[239]) - 79 * sizeof(MCRegisterClass), |
| 3578 | .NameIdx: 684, |
| 3579 | .RegSizeInBits: 64, |
| 3580 | .RegsSize: 31, |
| 3581 | .RegSetBegin: 37, /* MinRegVal */ |
| 3582 | .RegSetSize: 31, /* RegSetSize */ |
| 3583 | .ID: RISCV::ZZZ_VMNoV0RegClassID, |
| 3584 | .CopyCost: 1, /* CopyCost */ |
| 3585 | .Allocatable: true, /* Allocatable */ |
| 3586 | .BaseClass: false, |
| 3587 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1100]) - 79 * sizeof(MCRegisterClass), |
| 3588 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 79 * sizeof(MCRegisterClass), |
| 3589 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3590 | .AllocationPriority: 0, |
| 3591 | .GlobalPriority: false, |
| 3592 | .TSFlags: 0x01, /* TSFlags */ |
| 3593 | .SpillStackID: 0, /* SpillStackID */ |
| 3594 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3595 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3596 | offsetof(RISCVRegisterClassStorage, SuperClasses[390]) - 79 * sizeof(MCRegisterClass), |
| 3597 | .SuperClassesSize: 9 |
| 3598 | }, |
| 3599 | { |
| 3600 | offsetof(RISCVRegisterClassStorage, Regs[1279]) - 80 * sizeof(MCRegisterClass), |
| 3601 | offsetof(RISCVRegisterClassStorage, BitSets[243]) - 80 * sizeof(MCRegisterClass), |
| 3602 | .NameIdx: 571, |
| 3603 | .RegSizeInBits: 64, |
| 3604 | .RegsSize: 31, |
| 3605 | .RegSetBegin: 37, /* MinRegVal */ |
| 3606 | .RegSetSize: 31, /* RegSetSize */ |
| 3607 | .ID: RISCV::ZZZ_VRMF2NoV0RegClassID, |
| 3608 | .CopyCost: 1, /* CopyCost */ |
| 3609 | .Allocatable: true, /* Allocatable */ |
| 3610 | .BaseClass: false, |
| 3611 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1145]) - 80 * sizeof(MCRegisterClass), |
| 3612 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 80 * sizeof(MCRegisterClass), |
| 3613 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3614 | .AllocationPriority: 0, |
| 3615 | .GlobalPriority: false, |
| 3616 | .TSFlags: 0x01, /* TSFlags */ |
| 3617 | .SpillStackID: 0, /* SpillStackID */ |
| 3618 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3619 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3620 | offsetof(RISCVRegisterClassStorage, SuperClasses[399]) - 80 * sizeof(MCRegisterClass), |
| 3621 | .SuperClassesSize: 9 |
| 3622 | }, |
| 3623 | { |
| 3624 | offsetof(RISCVRegisterClassStorage, Regs[1310]) - 81 * sizeof(MCRegisterClass), |
| 3625 | offsetof(RISCVRegisterClassStorage, BitSets[247]) - 81 * sizeof(MCRegisterClass), |
| 3626 | .NameIdx: 627, |
| 3627 | .RegSizeInBits: 64, |
| 3628 | .RegsSize: 31, |
| 3629 | .RegSetBegin: 37, /* MinRegVal */ |
| 3630 | .RegSetSize: 31, /* RegSetSize */ |
| 3631 | .ID: RISCV::ZZZ_VRMF4NoV0RegClassID, |
| 3632 | .CopyCost: 1, /* CopyCost */ |
| 3633 | .Allocatable: true, /* Allocatable */ |
| 3634 | .BaseClass: false, |
| 3635 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1190]) - 81 * sizeof(MCRegisterClass), |
| 3636 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 81 * sizeof(MCRegisterClass), |
| 3637 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3638 | .AllocationPriority: 0, |
| 3639 | .GlobalPriority: false, |
| 3640 | .TSFlags: 0x01, /* TSFlags */ |
| 3641 | .SpillStackID: 0, /* SpillStackID */ |
| 3642 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3643 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3644 | offsetof(RISCVRegisterClassStorage, SuperClasses[408]) - 81 * sizeof(MCRegisterClass), |
| 3645 | .SuperClassesSize: 9 |
| 3646 | }, |
| 3647 | { |
| 3648 | offsetof(RISCVRegisterClassStorage, Regs[1341]) - 82 * sizeof(MCRegisterClass), |
| 3649 | offsetof(RISCVRegisterClassStorage, BitSets[251]) - 82 * sizeof(MCRegisterClass), |
| 3650 | .NameIdx: 661, |
| 3651 | .RegSizeInBits: 64, |
| 3652 | .RegsSize: 31, |
| 3653 | .RegSetBegin: 37, /* MinRegVal */ |
| 3654 | .RegSetSize: 31, /* RegSetSize */ |
| 3655 | .ID: RISCV::ZZZ_VRMF8NoV0RegClassID, |
| 3656 | .CopyCost: 1, /* CopyCost */ |
| 3657 | .Allocatable: true, /* Allocatable */ |
| 3658 | .BaseClass: false, |
| 3659 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1235]) - 82 * sizeof(MCRegisterClass), |
| 3660 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[22]) - 82 * sizeof(MCRegisterClass), |
| 3661 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3662 | .AllocationPriority: 0, |
| 3663 | .GlobalPriority: false, |
| 3664 | .TSFlags: 0x01, /* TSFlags */ |
| 3665 | .SpillStackID: 0, /* SpillStackID */ |
| 3666 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3667 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3668 | offsetof(RISCVRegisterClassStorage, SuperClasses[417]) - 82 * sizeof(MCRegisterClass), |
| 3669 | .SuperClassesSize: 9 |
| 3670 | }, |
| 3671 | { |
| 3672 | offsetof(RISCVRegisterClassStorage, Regs[1372]) - 83 * sizeof(MCRegisterClass), |
| 3673 | offsetof(RISCVRegisterClassStorage, BitSets[255]) - 83 * sizeof(MCRegisterClass), |
| 3674 | .NameIdx: 1490, |
| 3675 | .RegSizeInBits: 0, |
| 3676 | .RegsSize: 30, |
| 3677 | .RegSetBegin: 294, /* MinRegVal */ |
| 3678 | .RegSetSize: 31, /* RegSetSize */ |
| 3679 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, |
| 3680 | .CopyCost: 1, /* CopyCost */ |
| 3681 | .Allocatable: true, /* Allocatable */ |
| 3682 | .BaseClass: false, |
| 3683 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1280]) - 83 * sizeof(MCRegisterClass), |
| 3684 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 83 * sizeof(MCRegisterClass), |
| 3685 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3686 | .AllocationPriority: 0, |
| 3687 | .GlobalPriority: false, |
| 3688 | .TSFlags: 0x00, /* TSFlags */ |
| 3689 | .SpillStackID: 0, /* SpillStackID */ |
| 3690 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3691 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3692 | offsetof(RISCVRegisterClassStorage, SuperClasses[426]) - 83 * sizeof(MCRegisterClass), |
| 3693 | .SuperClassesSize: 3 |
| 3694 | }, |
| 3695 | { |
| 3696 | offsetof(RISCVRegisterClassStorage, Regs[1402]) - 84 * sizeof(MCRegisterClass), |
| 3697 | offsetof(RISCVRegisterClassStorage, BitSets[259]) - 84 * sizeof(MCRegisterClass), |
| 3698 | .NameIdx: 840, |
| 3699 | .RegSizeInBits: 0, |
| 3700 | .RegsSize: 30, |
| 3701 | .RegSetBegin: 294, /* MinRegVal */ |
| 3702 | .RegSetSize: 30, /* RegSetSize */ |
| 3703 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, |
| 3704 | .CopyCost: 1, /* CopyCost */ |
| 3705 | .Allocatable: true, /* Allocatable */ |
| 3706 | .BaseClass: false, |
| 3707 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1285]) - 84 * sizeof(MCRegisterClass), |
| 3708 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 84 * sizeof(MCRegisterClass), |
| 3709 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3710 | .AllocationPriority: 0, |
| 3711 | .GlobalPriority: false, |
| 3712 | .TSFlags: 0x00, /* TSFlags */ |
| 3713 | .SpillStackID: 0, /* SpillStackID */ |
| 3714 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3715 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3716 | offsetof(RISCVRegisterClassStorage, SuperClasses[429]) - 84 * sizeof(MCRegisterClass), |
| 3717 | .SuperClassesSize: 3 |
| 3718 | }, |
| 3719 | { |
| 3720 | offsetof(RISCVRegisterClassStorage, Regs[1432]) - 85 * sizeof(MCRegisterClass), |
| 3721 | offsetof(RISCVRegisterClassStorage, BitSets[263]) - 85 * sizeof(MCRegisterClass), |
| 3722 | .NameIdx: 936, |
| 3723 | .RegSizeInBits: 0, |
| 3724 | .RegsSize: 30, |
| 3725 | .RegSetBegin: 293, /* MinRegVal */ |
| 3726 | .RegSetSize: 31, /* RegSetSize */ |
| 3727 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, |
| 3728 | .CopyCost: 1, /* CopyCost */ |
| 3729 | .Allocatable: true, /* Allocatable */ |
| 3730 | .BaseClass: false, |
| 3731 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1290]) - 85 * sizeof(MCRegisterClass), |
| 3732 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 85 * sizeof(MCRegisterClass), |
| 3733 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3734 | .AllocationPriority: 0, |
| 3735 | .GlobalPriority: false, |
| 3736 | .TSFlags: 0x00, /* TSFlags */ |
| 3737 | .SpillStackID: 0, /* SpillStackID */ |
| 3738 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3739 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3740 | offsetof(RISCVRegisterClassStorage, SuperClasses[432]) - 85 * sizeof(MCRegisterClass), |
| 3741 | .SuperClassesSize: 3 |
| 3742 | }, |
| 3743 | { |
| 3744 | offsetof(RISCVRegisterClassStorage, Regs[1462]) - 86 * sizeof(MCRegisterClass), |
| 3745 | offsetof(RISCVRegisterClassStorage, BitSets[267]) - 86 * sizeof(MCRegisterClass), |
| 3746 | .NameIdx: 887, |
| 3747 | .RegSizeInBits: 0, |
| 3748 | .RegsSize: 29, |
| 3749 | .RegSetBegin: 294, /* MinRegVal */ |
| 3750 | .RegSetSize: 30, /* RegSetSize */ |
| 3751 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, |
| 3752 | .CopyCost: 1, /* CopyCost */ |
| 3753 | .Allocatable: true, /* Allocatable */ |
| 3754 | .BaseClass: false, |
| 3755 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1295]) - 86 * sizeof(MCRegisterClass), |
| 3756 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 86 * sizeof(MCRegisterClass), |
| 3757 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3758 | .AllocationPriority: 0, |
| 3759 | .GlobalPriority: false, |
| 3760 | .TSFlags: 0x00, /* TSFlags */ |
| 3761 | .SpillStackID: 0, /* SpillStackID */ |
| 3762 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3763 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3764 | offsetof(RISCVRegisterClassStorage, SuperClasses[435]) - 86 * sizeof(MCRegisterClass), |
| 3765 | .SuperClassesSize: 7 |
| 3766 | }, |
| 3767 | { |
| 3768 | offsetof(RISCVRegisterClassStorage, Regs[1491]) - 87 * sizeof(MCRegisterClass), |
| 3769 | offsetof(RISCVRegisterClassStorage, BitSets[271]) - 87 * sizeof(MCRegisterClass), |
| 3770 | .NameIdx: 2725, |
| 3771 | .RegSizeInBits: 0, |
| 3772 | .RegsSize: 26, |
| 3773 | .RegSetBegin: 299, /* MinRegVal */ |
| 3774 | .RegSetSize: 26, /* RegSetSize */ |
| 3775 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, |
| 3776 | .CopyCost: 1, /* CopyCost */ |
| 3777 | .Allocatable: true, /* Allocatable */ |
| 3778 | .BaseClass: false, |
| 3779 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1300]) - 87 * sizeof(MCRegisterClass), |
| 3780 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 87 * sizeof(MCRegisterClass), |
| 3781 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3782 | .AllocationPriority: 0, |
| 3783 | .GlobalPriority: false, |
| 3784 | .TSFlags: 0x00, /* TSFlags */ |
| 3785 | .SpillStackID: 0, /* SpillStackID */ |
| 3786 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3787 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3788 | offsetof(RISCVRegisterClassStorage, SuperClasses[442]) - 87 * sizeof(MCRegisterClass), |
| 3789 | .SuperClassesSize: 4 |
| 3790 | }, |
| 3791 | { |
| 3792 | offsetof(RISCVRegisterClassStorage, Regs[1517]) - 88 * sizeof(MCRegisterClass), |
| 3793 | offsetof(RISCVRegisterClassStorage, BitSets[275]) - 88 * sizeof(MCRegisterClass), |
| 3794 | .NameIdx: 2193, |
| 3795 | .RegSizeInBits: 0, |
| 3796 | .RegsSize: 25, |
| 3797 | .RegSetBegin: 299, /* MinRegVal */ |
| 3798 | .RegSetSize: 26, /* RegSetSize */ |
| 3799 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, |
| 3800 | .CopyCost: 1, /* CopyCost */ |
| 3801 | .Allocatable: true, /* Allocatable */ |
| 3802 | .BaseClass: false, |
| 3803 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1305]) - 88 * sizeof(MCRegisterClass), |
| 3804 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 88 * sizeof(MCRegisterClass), |
| 3805 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3806 | .AllocationPriority: 0, |
| 3807 | .GlobalPriority: false, |
| 3808 | .TSFlags: 0x00, /* TSFlags */ |
| 3809 | .SpillStackID: 0, /* SpillStackID */ |
| 3810 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3811 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3812 | offsetof(RISCVRegisterClassStorage, SuperClasses[446]) - 88 * sizeof(MCRegisterClass), |
| 3813 | .SuperClassesSize: 5 |
| 3814 | }, |
| 3815 | { |
| 3816 | offsetof(RISCVRegisterClassStorage, Regs[1542]) - 89 * sizeof(MCRegisterClass), |
| 3817 | offsetof(RISCVRegisterClassStorage, BitSets[279]) - 89 * sizeof(MCRegisterClass), |
| 3818 | .NameIdx: 1138, |
| 3819 | .RegSizeInBits: 0, |
| 3820 | .RegsSize: 25, |
| 3821 | .RegSetBegin: 299, /* MinRegVal */ |
| 3822 | .RegSetSize: 25, /* RegSetSize */ |
| 3823 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, |
| 3824 | .CopyCost: 1, /* CopyCost */ |
| 3825 | .Allocatable: true, /* Allocatable */ |
| 3826 | .BaseClass: false, |
| 3827 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1310]) - 89 * sizeof(MCRegisterClass), |
| 3828 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 89 * sizeof(MCRegisterClass), |
| 3829 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3830 | .AllocationPriority: 0, |
| 3831 | .GlobalPriority: false, |
| 3832 | .TSFlags: 0x00, /* TSFlags */ |
| 3833 | .SpillStackID: 0, /* SpillStackID */ |
| 3834 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3835 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3836 | offsetof(RISCVRegisterClassStorage, SuperClasses[451]) - 89 * sizeof(MCRegisterClass), |
| 3837 | .SuperClassesSize: 9 |
| 3838 | }, |
| 3839 | { |
| 3840 | offsetof(RISCVRegisterClassStorage, Regs[1567]) - 90 * sizeof(MCRegisterClass), |
| 3841 | offsetof(RISCVRegisterClassStorage, BitSets[283]) - 90 * sizeof(MCRegisterClass), |
| 3842 | .NameIdx: 1037, |
| 3843 | .RegSizeInBits: 0, |
| 3844 | .RegsSize: 24, |
| 3845 | .RegSetBegin: 299, /* MinRegVal */ |
| 3846 | .RegSetSize: 25, /* RegSetSize */ |
| 3847 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 3848 | .CopyCost: 1, /* CopyCost */ |
| 3849 | .Allocatable: true, /* Allocatable */ |
| 3850 | .BaseClass: false, |
| 3851 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1315]) - 90 * sizeof(MCRegisterClass), |
| 3852 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 90 * sizeof(MCRegisterClass), |
| 3853 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3854 | .AllocationPriority: 0, |
| 3855 | .GlobalPriority: false, |
| 3856 | .TSFlags: 0x00, /* TSFlags */ |
| 3857 | .SpillStackID: 0, /* SpillStackID */ |
| 3858 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3859 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3860 | offsetof(RISCVRegisterClassStorage, SuperClasses[460]) - 90 * sizeof(MCRegisterClass), |
| 3861 | .SuperClassesSize: 11 |
| 3862 | }, |
| 3863 | { |
| 3864 | offsetof(RISCVRegisterClassStorage, Regs[1591]) - 91 * sizeof(MCRegisterClass), |
| 3865 | offsetof(RISCVRegisterClassStorage, BitSets[287]) - 91 * sizeof(MCRegisterClass), |
| 3866 | .NameIdx: 2579, |
| 3867 | .RegSizeInBits: 0, |
| 3868 | .RegsSize: 14, |
| 3869 | .RegSetBegin: 299, /* MinRegVal */ |
| 3870 | .RegSetSize: 26, /* RegSetSize */ |
| 3871 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRTCRegClassID, |
| 3872 | .CopyCost: 1, /* CopyCost */ |
| 3873 | .Allocatable: true, /* Allocatable */ |
| 3874 | .BaseClass: false, |
| 3875 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1320]) - 91 * sizeof(MCRegisterClass), |
| 3876 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 91 * sizeof(MCRegisterClass), |
| 3877 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3878 | .AllocationPriority: 0, |
| 3879 | .GlobalPriority: false, |
| 3880 | .TSFlags: 0x00, /* TSFlags */ |
| 3881 | .SpillStackID: 0, /* SpillStackID */ |
| 3882 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3883 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3884 | offsetof(RISCVRegisterClassStorage, SuperClasses[471]) - 91 * sizeof(MCRegisterClass), |
| 3885 | .SuperClassesSize: 5 |
| 3886 | }, |
| 3887 | { |
| 3888 | offsetof(RISCVRegisterClassStorage, Regs[1605]) - 92 * sizeof(MCRegisterClass), |
| 3889 | offsetof(RISCVRegisterClassStorage, BitSets[291]) - 92 * sizeof(MCRegisterClass), |
| 3890 | .NameIdx: 2414, |
| 3891 | .RegSizeInBits: 0, |
| 3892 | .RegsSize: 13, |
| 3893 | .RegSetBegin: 299, /* MinRegVal */ |
| 3894 | .RegSetSize: 25, /* RegSetSize */ |
| 3895 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCRegClassID, |
| 3896 | .CopyCost: 1, /* CopyCost */ |
| 3897 | .Allocatable: true, /* Allocatable */ |
| 3898 | .BaseClass: false, |
| 3899 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1325]) - 92 * sizeof(MCRegisterClass), |
| 3900 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 92 * sizeof(MCRegisterClass), |
| 3901 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3902 | .AllocationPriority: 0, |
| 3903 | .GlobalPriority: false, |
| 3904 | .TSFlags: 0x00, /* TSFlags */ |
| 3905 | .SpillStackID: 0, /* SpillStackID */ |
| 3906 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3907 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3908 | offsetof(RISCVRegisterClassStorage, SuperClasses[476]) - 92 * sizeof(MCRegisterClass), |
| 3909 | .SuperClassesSize: 11 |
| 3910 | }, |
| 3911 | { |
| 3912 | offsetof(RISCVRegisterClassStorage, Regs[1618]) - 93 * sizeof(MCRegisterClass), |
| 3913 | offsetof(RISCVRegisterClassStorage, BitSets[295]) - 93 * sizeof(MCRegisterClass), |
| 3914 | .NameIdx: 2115, |
| 3915 | .RegSizeInBits: 0, |
| 3916 | .RegsSize: 13, |
| 3917 | .RegSetBegin: 299, /* MinRegVal */ |
| 3918 | .RegSetSize: 26, /* RegSetSize */ |
| 3919 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRTCNonX7RegClassID, |
| 3920 | .CopyCost: 1, /* CopyCost */ |
| 3921 | .Allocatable: true, /* Allocatable */ |
| 3922 | .BaseClass: false, |
| 3923 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1330]) - 93 * sizeof(MCRegisterClass), |
| 3924 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 93 * sizeof(MCRegisterClass), |
| 3925 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3926 | .AllocationPriority: 0, |
| 3927 | .GlobalPriority: false, |
| 3928 | .TSFlags: 0x00, /* TSFlags */ |
| 3929 | .SpillStackID: 0, /* SpillStackID */ |
| 3930 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3931 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3932 | offsetof(RISCVRegisterClassStorage, SuperClasses[487]) - 93 * sizeof(MCRegisterClass), |
| 3933 | .SuperClassesSize: 7 |
| 3934 | }, |
| 3935 | { |
| 3936 | offsetof(RISCVRegisterClassStorage, Regs[1631]) - 94 * sizeof(MCRegisterClass), |
| 3937 | offsetof(RISCVRegisterClassStorage, BitSets[299]) - 94 * sizeof(MCRegisterClass), |
| 3938 | .NameIdx: 2026, |
| 3939 | .RegSizeInBits: 0, |
| 3940 | .RegsSize: 12, |
| 3941 | .RegSetBegin: 299, /* MinRegVal */ |
| 3942 | .RegSetSize: 25, /* RegSetSize */ |
| 3943 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7RegClassID, |
| 3944 | .CopyCost: 1, /* CopyCost */ |
| 3945 | .Allocatable: true, /* Allocatable */ |
| 3946 | .BaseClass: false, |
| 3947 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1335]) - 94 * sizeof(MCRegisterClass), |
| 3948 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 94 * sizeof(MCRegisterClass), |
| 3949 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3950 | .AllocationPriority: 0, |
| 3951 | .GlobalPriority: false, |
| 3952 | .TSFlags: 0x00, /* TSFlags */ |
| 3953 | .SpillStackID: 0, /* SpillStackID */ |
| 3954 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3955 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3956 | offsetof(RISCVRegisterClassStorage, SuperClasses[494]) - 94 * sizeof(MCRegisterClass), |
| 3957 | .SuperClassesSize: 15 |
| 3958 | }, |
| 3959 | { |
| 3960 | offsetof(RISCVRegisterClassStorage, Regs[1643]) - 95 * sizeof(MCRegisterClass), |
| 3961 | offsetof(RISCVRegisterClassStorage, BitSets[303]) - 95 * sizeof(MCRegisterClass), |
| 3962 | .NameIdx: 2269, |
| 3963 | .RegSizeInBits: 64, |
| 3964 | .RegsSize: 8, |
| 3965 | .RegSetBegin: 108, /* MinRegVal */ |
| 3966 | .RegSetSize: 8, /* RegSetSize */ |
| 3967 | .ID: RISCV::FPR64CRegClassID, |
| 3968 | .CopyCost: 1, /* CopyCost */ |
| 3969 | .Allocatable: true, /* Allocatable */ |
| 3970 | .BaseClass: false, |
| 3971 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1340]) - 95 * sizeof(MCRegisterClass), |
| 3972 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[4]) - 95 * sizeof(MCRegisterClass), |
| 3973 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3974 | .AllocationPriority: 0, |
| 3975 | .GlobalPriority: false, |
| 3976 | .TSFlags: 0x00, /* TSFlags */ |
| 3977 | .SpillStackID: 0, /* SpillStackID */ |
| 3978 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 3979 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 3980 | offsetof(RISCVRegisterClassStorage, SuperClasses[509]) - 95 * sizeof(MCRegisterClass), |
| 3981 | .SuperClassesSize: 1 |
| 3982 | }, |
| 3983 | { |
| 3984 | offsetof(RISCVRegisterClassStorage, Regs[1651]) - 96 * sizeof(MCRegisterClass), |
| 3985 | offsetof(RISCVRegisterClassStorage, BitSets[304]) - 96 * sizeof(MCRegisterClass), |
| 3986 | .NameIdx: 2276, |
| 3987 | .RegSizeInBits: 0, |
| 3988 | .RegsSize: 8, |
| 3989 | .RegSetBegin: 301, /* MinRegVal */ |
| 3990 | .RegSetSize: 8, /* RegSetSize */ |
| 3991 | .ID: RISCV::YGPR_with_sub_16_in_GPRF16CRegClassID, |
| 3992 | .CopyCost: 1, /* CopyCost */ |
| 3993 | .Allocatable: true, /* Allocatable */ |
| 3994 | .BaseClass: false, |
| 3995 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1350]) - 96 * sizeof(MCRegisterClass), |
| 3996 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 96 * sizeof(MCRegisterClass), |
| 3997 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 3998 | .AllocationPriority: 0, |
| 3999 | .GlobalPriority: false, |
| 4000 | .TSFlags: 0x00, /* TSFlags */ |
| 4001 | .SpillStackID: 0, /* SpillStackID */ |
| 4002 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4003 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4004 | offsetof(RISCVRegisterClassStorage, SuperClasses[510]) - 96 * sizeof(MCRegisterClass), |
| 4005 | .SuperClassesSize: 12 |
| 4006 | }, |
| 4007 | { |
| 4008 | offsetof(RISCVRegisterClassStorage, Regs[1659]) - 97 * sizeof(MCRegisterClass), |
| 4009 | offsetof(RISCVRegisterClassStorage, BitSets[305]) - 97 * sizeof(MCRegisterClass), |
| 4010 | .NameIdx: 1875, |
| 4011 | .RegSizeInBits: 0, |
| 4012 | .RegsSize: 8, |
| 4013 | .RegSetBegin: 301, /* MinRegVal */ |
| 4014 | .RegSetSize: 16, /* RegSetSize */ |
| 4015 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRS07RegClassID, |
| 4016 | .CopyCost: 1, /* CopyCost */ |
| 4017 | .Allocatable: true, /* Allocatable */ |
| 4018 | .BaseClass: false, |
| 4019 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1355]) - 97 * sizeof(MCRegisterClass), |
| 4020 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 97 * sizeof(MCRegisterClass), |
| 4021 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4022 | .AllocationPriority: 0, |
| 4023 | .GlobalPriority: false, |
| 4024 | .TSFlags: 0x00, /* TSFlags */ |
| 4025 | .SpillStackID: 0, /* SpillStackID */ |
| 4026 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4027 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4028 | offsetof(RISCVRegisterClassStorage, SuperClasses[522]) - 97 * sizeof(MCRegisterClass), |
| 4029 | .SuperClassesSize: 12 |
| 4030 | }, |
| 4031 | { |
| 4032 | offsetof(RISCVRegisterClassStorage, Regs[1667]) - 98 * sizeof(MCRegisterClass), |
| 4033 | offsetof(RISCVRegisterClassStorage, BitSets[307]) - 98 * sizeof(MCRegisterClass), |
| 4034 | .NameIdx: 2503, |
| 4035 | .RegSizeInBits: 0, |
| 4036 | .RegsSize: 6, |
| 4037 | .RegSetBegin: 303, /* MinRegVal */ |
| 4038 | .RegSetSize: 6, /* RegSetSize */ |
| 4039 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRC_and_GPRTCRegClassID, |
| 4040 | .CopyCost: 1, /* CopyCost */ |
| 4041 | .Allocatable: true, /* Allocatable */ |
| 4042 | .BaseClass: false, |
| 4043 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1360]) - 98 * sizeof(MCRegisterClass), |
| 4044 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 98 * sizeof(MCRegisterClass), |
| 4045 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4046 | .AllocationPriority: 0, |
| 4047 | .GlobalPriority: false, |
| 4048 | .TSFlags: 0x00, /* TSFlags */ |
| 4049 | .SpillStackID: 0, /* SpillStackID */ |
| 4050 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4051 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4052 | offsetof(RISCVRegisterClassStorage, SuperClasses[534]) - 98 * sizeof(MCRegisterClass), |
| 4053 | .SuperClassesSize: 17 |
| 4054 | }, |
| 4055 | { |
| 4056 | offsetof(RISCVRegisterClassStorage, Regs[1673]) - 99 * sizeof(MCRegisterClass), |
| 4057 | offsetof(RISCVRegisterClassStorage, BitSets[308]) - 99 * sizeof(MCRegisterClass), |
| 4058 | .NameIdx: 1797, |
| 4059 | .RegSizeInBits: 0, |
| 4060 | .RegsSize: 2, |
| 4061 | .RegSetBegin: 301, /* MinRegVal */ |
| 4062 | .RegSetSize: 2, /* RegSetSize */ |
| 4063 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRC_and_GPRS07RegClassID, |
| 4064 | .CopyCost: 1, /* CopyCost */ |
| 4065 | .Allocatable: true, /* Allocatable */ |
| 4066 | .BaseClass: false, |
| 4067 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1365]) - 99 * sizeof(MCRegisterClass), |
| 4068 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 99 * sizeof(MCRegisterClass), |
| 4069 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4070 | .AllocationPriority: 0, |
| 4071 | .GlobalPriority: false, |
| 4072 | .TSFlags: 0x00, /* TSFlags */ |
| 4073 | .SpillStackID: 0, /* SpillStackID */ |
| 4074 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4075 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4076 | offsetof(RISCVRegisterClassStorage, SuperClasses[551]) - 99 * sizeof(MCRegisterClass), |
| 4077 | .SuperClassesSize: 14 |
| 4078 | }, |
| 4079 | { |
| 4080 | offsetof(RISCVRegisterClassStorage, Regs[1675]) - 100 * sizeof(MCRegisterClass), |
| 4081 | offsetof(RISCVRegisterClassStorage, BitSets[309]) - 100 * sizeof(MCRegisterClass), |
| 4082 | .NameIdx: 1666, |
| 4083 | .RegSizeInBits: 0, |
| 4084 | .RegsSize: 2, |
| 4085 | .RegSetBegin: 294, /* MinRegVal */ |
| 4086 | .RegSetSize: 5, /* RegSetSize */ |
| 4087 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX1X5RegClassID, |
| 4088 | .CopyCost: 1, /* CopyCost */ |
| 4089 | .Allocatable: true, /* Allocatable */ |
| 4090 | .BaseClass: false, |
| 4091 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1370]) - 100 * sizeof(MCRegisterClass), |
| 4092 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 100 * sizeof(MCRegisterClass), |
| 4093 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4094 | .AllocationPriority: 0, |
| 4095 | .GlobalPriority: false, |
| 4096 | .TSFlags: 0x00, /* TSFlags */ |
| 4097 | .SpillStackID: 0, /* SpillStackID */ |
| 4098 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4099 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4100 | offsetof(RISCVRegisterClassStorage, SuperClasses[565]) - 100 * sizeof(MCRegisterClass), |
| 4101 | .SuperClassesSize: 8 |
| 4102 | }, |
| 4103 | { |
| 4104 | offsetof(RISCVRegisterClassStorage, Regs[1677]) - 101 * sizeof(MCRegisterClass), |
| 4105 | offsetof(RISCVRegisterClassStorage, BitSets[310]) - 101 * sizeof(MCRegisterClass), |
| 4106 | .NameIdx: 30, |
| 4107 | .RegSizeInBits: 64, |
| 4108 | .RegsSize: 1, |
| 4109 | .RegSetBegin: 36, /* MinRegVal */ |
| 4110 | .RegSetSize: 1, /* RegSetSize */ |
| 4111 | .ID: RISCV::VMV0RegClassID, |
| 4112 | .CopyCost: 1, /* CopyCost */ |
| 4113 | .Allocatable: true, /* Allocatable */ |
| 4114 | .BaseClass: false, |
| 4115 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1375]) - 101 * sizeof(MCRegisterClass), |
| 4116 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[20]) - 101 * sizeof(MCRegisterClass), |
| 4117 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4118 | .AllocationPriority: 0, |
| 4119 | .GlobalPriority: false, |
| 4120 | .TSFlags: 0x01, /* TSFlags */ |
| 4121 | .SpillStackID: 0, /* SpillStackID */ |
| 4122 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4123 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4124 | offsetof(RISCVRegisterClassStorage, SuperClasses[573]) - 101 * sizeof(MCRegisterClass), |
| 4125 | .SuperClassesSize: 5 |
| 4126 | }, |
| 4127 | { |
| 4128 | offsetof(RISCVRegisterClassStorage, Regs[1678]) - 102 * sizeof(MCRegisterClass), |
| 4129 | offsetof(RISCVRegisterClassStorage, BitSets[311]) - 102 * sizeof(MCRegisterClass), |
| 4130 | .NameIdx: 711, |
| 4131 | .RegSizeInBits: 0, |
| 4132 | .RegsSize: 1, |
| 4133 | .RegSetBegin: 293, /* MinRegVal */ |
| 4134 | .RegSetSize: 1, /* RegSetSize */ |
| 4135 | .ID: RISCV::YGPR_with_sub_16_in_GPRF16X0RegClassID, |
| 4136 | .CopyCost: 1, /* CopyCost */ |
| 4137 | .Allocatable: true, /* Allocatable */ |
| 4138 | .BaseClass: false, |
| 4139 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1385]) - 102 * sizeof(MCRegisterClass), |
| 4140 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 102 * sizeof(MCRegisterClass), |
| 4141 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4142 | .AllocationPriority: 0, |
| 4143 | .GlobalPriority: false, |
| 4144 | .TSFlags: 0x00, /* TSFlags */ |
| 4145 | .SpillStackID: 0, /* SpillStackID */ |
| 4146 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4147 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4148 | offsetof(RISCVRegisterClassStorage, SuperClasses[578]) - 102 * sizeof(MCRegisterClass), |
| 4149 | .SuperClassesSize: 4 |
| 4150 | }, |
| 4151 | { |
| 4152 | offsetof(RISCVRegisterClassStorage, Regs[1679]) - 103 * sizeof(MCRegisterClass), |
| 4153 | offsetof(RISCVRegisterClassStorage, BitSets[312]) - 103 * sizeof(MCRegisterClass), |
| 4154 | .NameIdx: 1365, |
| 4155 | .RegSizeInBits: 0, |
| 4156 | .RegsSize: 1, |
| 4157 | .RegSetBegin: 294, /* MinRegVal */ |
| 4158 | .RegSetSize: 1, /* RegSetSize */ |
| 4159 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX1RegClassID, |
| 4160 | .CopyCost: 1, /* CopyCost */ |
| 4161 | .Allocatable: true, /* Allocatable */ |
| 4162 | .BaseClass: false, |
| 4163 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1390]) - 103 * sizeof(MCRegisterClass), |
| 4164 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 103 * sizeof(MCRegisterClass), |
| 4165 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4166 | .AllocationPriority: 0, |
| 4167 | .GlobalPriority: false, |
| 4168 | .TSFlags: 0x00, /* TSFlags */ |
| 4169 | .SpillStackID: 0, /* SpillStackID */ |
| 4170 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4171 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4172 | offsetof(RISCVRegisterClassStorage, SuperClasses[582]) - 103 * sizeof(MCRegisterClass), |
| 4173 | .SuperClassesSize: 9 |
| 4174 | }, |
| 4175 | { |
| 4176 | offsetof(RISCVRegisterClassStorage, Regs[1680]) - 104 * sizeof(MCRegisterClass), |
| 4177 | offsetof(RISCVRegisterClassStorage, BitSets[313]) - 104 * sizeof(MCRegisterClass), |
| 4178 | .NameIdx: 1700, |
| 4179 | .RegSizeInBits: 0, |
| 4180 | .RegsSize: 1, |
| 4181 | .RegSetBegin: 298, /* MinRegVal */ |
| 4182 | .RegSetSize: 1, /* RegSetSize */ |
| 4183 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX5RegClassID, |
| 4184 | .CopyCost: 1, /* CopyCost */ |
| 4185 | .Allocatable: true, /* Allocatable */ |
| 4186 | .BaseClass: false, |
| 4187 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1395]) - 104 * sizeof(MCRegisterClass), |
| 4188 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 104 * sizeof(MCRegisterClass), |
| 4189 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4190 | .AllocationPriority: 0, |
| 4191 | .GlobalPriority: false, |
| 4192 | .TSFlags: 0x00, /* TSFlags */ |
| 4193 | .SpillStackID: 0, /* SpillStackID */ |
| 4194 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4195 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4196 | offsetof(RISCVRegisterClassStorage, SuperClasses[591]) - 104 * sizeof(MCRegisterClass), |
| 4197 | .SuperClassesSize: 9 |
| 4198 | }, |
| 4199 | { |
| 4200 | offsetof(RISCVRegisterClassStorage, Regs[1681]) - 105 * sizeof(MCRegisterClass), |
| 4201 | offsetof(RISCVRegisterClassStorage, BitSets[314]) - 105 * sizeof(MCRegisterClass), |
| 4202 | .NameIdx: 1942, |
| 4203 | .RegSizeInBits: 0, |
| 4204 | .RegsSize: 1, |
| 4205 | .RegSetBegin: 300, /* MinRegVal */ |
| 4206 | .RegSetSize: 1, /* RegSetSize */ |
| 4207 | .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX7RegClassID, |
| 4208 | .CopyCost: 1, /* CopyCost */ |
| 4209 | .Allocatable: true, /* Allocatable */ |
| 4210 | .BaseClass: false, |
| 4211 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1400]) - 105 * sizeof(MCRegisterClass), |
| 4212 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 105 * sizeof(MCRegisterClass), |
| 4213 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4214 | .AllocationPriority: 0, |
| 4215 | .GlobalPriority: false, |
| 4216 | .TSFlags: 0x00, /* TSFlags */ |
| 4217 | .SpillStackID: 0, /* SpillStackID */ |
| 4218 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4219 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4220 | offsetof(RISCVRegisterClassStorage, SuperClasses[600]) - 105 * sizeof(MCRegisterClass), |
| 4221 | .SuperClassesSize: 12 |
| 4222 | }, |
| 4223 | { |
| 4224 | offsetof(RISCVRegisterClassStorage, Regs[1682]) - 106 * sizeof(MCRegisterClass), |
| 4225 | offsetof(RISCVRegisterClassStorage, BitSets[315]) - 106 * sizeof(MCRegisterClass), |
| 4226 | .NameIdx: 2659, |
| 4227 | .RegSizeInBits: 0, |
| 4228 | .RegsSize: 1, |
| 4229 | .RegSetBegin: 295, /* MinRegVal */ |
| 4230 | .RegSetSize: 1, /* RegSetSize */ |
| 4231 | .ID: RISCV::YGPR_with_sub_cap_addr_in_SPRegClassID, |
| 4232 | .CopyCost: 1, /* CopyCost */ |
| 4233 | .Allocatable: true, /* Allocatable */ |
| 4234 | .BaseClass: false, |
| 4235 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1405]) - 106 * sizeof(MCRegisterClass), |
| 4236 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 106 * sizeof(MCRegisterClass), |
| 4237 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4238 | .AllocationPriority: 0, |
| 4239 | .GlobalPriority: false, |
| 4240 | .TSFlags: 0x00, /* TSFlags */ |
| 4241 | .SpillStackID: 0, /* SpillStackID */ |
| 4242 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4243 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4244 | offsetof(RISCVRegisterClassStorage, SuperClasses[612]) - 106 * sizeof(MCRegisterClass), |
| 4245 | .SuperClassesSize: 4 |
| 4246 | }, |
| 4247 | { |
| 4248 | offsetof(RISCVRegisterClassStorage, Regs[1683]) - 107 * sizeof(MCRegisterClass), |
| 4249 | offsetof(RISCVRegisterClassStorage, BitSets[316]) - 107 * sizeof(MCRegisterClass), |
| 4250 | .NameIdx: 1316, |
| 4251 | .RegSizeInBits: 128, |
| 4252 | .RegsSize: 31, |
| 4253 | .RegSetBegin: 400, /* MinRegVal */ |
| 4254 | .RegSetSize: 31, /* RegSetSize */ |
| 4255 | .ID: RISCV::VRN2M1RegClassID, |
| 4256 | .CopyCost: 2, /* CopyCost */ |
| 4257 | .Allocatable: true, /* Allocatable */ |
| 4258 | .BaseClass: false, |
| 4259 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1410]) - 107 * sizeof(MCRegisterClass), |
| 4260 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[88]) - 107 * sizeof(MCRegisterClass), |
| 4261 | .LaneMask: LaneBitmask(0x0000000000000006), |
| 4262 | .AllocationPriority: 0, |
| 4263 | .GlobalPriority: false, |
| 4264 | .TSFlags: 0x09, /* TSFlags */ |
| 4265 | .SpillStackID: 0, /* SpillStackID */ |
| 4266 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4267 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4268 | offsetof(RISCVRegisterClassStorage, SuperClasses[616]) - 107 * sizeof(MCRegisterClass), |
| 4269 | .SuperClassesSize: 0 |
| 4270 | }, |
| 4271 | { |
| 4272 | offsetof(RISCVRegisterClassStorage, Regs[1714]) - 108 * sizeof(MCRegisterClass), |
| 4273 | offsetof(RISCVRegisterClassStorage, BitSets[320]) - 108 * sizeof(MCRegisterClass), |
| 4274 | .NameIdx: 494, |
| 4275 | .RegSizeInBits: 128, |
| 4276 | .RegsSize: 30, |
| 4277 | .RegSetBegin: 400, /* MinRegVal */ |
| 4278 | .RegSetSize: 30, /* RegSetSize */ |
| 4279 | .ID: RISCV::VRN2M1NoV0RegClassID, |
| 4280 | .CopyCost: 2, /* CopyCost */ |
| 4281 | .Allocatable: true, /* Allocatable */ |
| 4282 | .BaseClass: false, |
| 4283 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1450]) - 108 * sizeof(MCRegisterClass), |
| 4284 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[88]) - 108 * sizeof(MCRegisterClass), |
| 4285 | .LaneMask: LaneBitmask(0x0000000000000006), |
| 4286 | .AllocationPriority: 0, |
| 4287 | .GlobalPriority: false, |
| 4288 | .TSFlags: 0x09, /* TSFlags */ |
| 4289 | .SpillStackID: 0, /* SpillStackID */ |
| 4290 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4291 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4292 | offsetof(RISCVRegisterClassStorage, SuperClasses[616]) - 108 * sizeof(MCRegisterClass), |
| 4293 | .SuperClassesSize: 1 |
| 4294 | }, |
| 4295 | { |
| 4296 | offsetof(RISCVRegisterClassStorage, Regs[1744]) - 109 * sizeof(MCRegisterClass), |
| 4297 | offsetof(RISCVRegisterClassStorage, BitSets[324]) - 109 * sizeof(MCRegisterClass), |
| 4298 | .NameIdx: 1446, |
| 4299 | .RegSizeInBits: 128, |
| 4300 | .RegsSize: 16, |
| 4301 | .RegSetBegin: 357, /* MinRegVal */ |
| 4302 | .RegSetSize: 28, /* RegSetSize */ |
| 4303 | .ID: RISCV::VRM2RegClassID, |
| 4304 | .CopyCost: 2, /* CopyCost */ |
| 4305 | .Allocatable: true, /* Allocatable */ |
| 4306 | .BaseClass: false, |
| 4307 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1490]) - 109 * sizeof(MCRegisterClass), |
| 4308 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[33]) - 109 * sizeof(MCRegisterClass), |
| 4309 | .LaneMask: LaneBitmask(0x0000000000000006), |
| 4310 | .AllocationPriority: 2, |
| 4311 | .GlobalPriority: false, |
| 4312 | .TSFlags: 0x03, /* TSFlags */ |
| 4313 | .SpillStackID: 0, /* SpillStackID */ |
| 4314 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4315 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4316 | offsetof(RISCVRegisterClassStorage, SuperClasses[617]) - 109 * sizeof(MCRegisterClass), |
| 4317 | .SuperClassesSize: 0 |
| 4318 | }, |
| 4319 | { |
| 4320 | offsetof(RISCVRegisterClassStorage, Regs[1760]) - 110 * sizeof(MCRegisterClass), |
| 4321 | offsetof(RISCVRegisterClassStorage, BitSets[328]) - 110 * sizeof(MCRegisterClass), |
| 4322 | .NameIdx: 618, |
| 4323 | .RegSizeInBits: 128, |
| 4324 | .RegsSize: 15, |
| 4325 | .RegSetBegin: 360, /* MinRegVal */ |
| 4326 | .RegSetSize: 25, /* RegSetSize */ |
| 4327 | .ID: RISCV::VRM2NoV0RegClassID, |
| 4328 | .CopyCost: 2, /* CopyCost */ |
| 4329 | .Allocatable: true, /* Allocatable */ |
| 4330 | .BaseClass: false, |
| 4331 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1515]) - 110 * sizeof(MCRegisterClass), |
| 4332 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[33]) - 110 * sizeof(MCRegisterClass), |
| 4333 | .LaneMask: LaneBitmask(0x0000000000000006), |
| 4334 | .AllocationPriority: 2, |
| 4335 | .GlobalPriority: false, |
| 4336 | .TSFlags: 0x03, /* TSFlags */ |
| 4337 | .SpillStackID: 0, /* SpillStackID */ |
| 4338 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4339 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4340 | offsetof(RISCVRegisterClassStorage, SuperClasses[617]) - 110 * sizeof(MCRegisterClass), |
| 4341 | .SuperClassesSize: 1 |
| 4342 | }, |
| 4343 | { |
| 4344 | offsetof(RISCVRegisterClassStorage, Regs[1775]) - 111 * sizeof(MCRegisterClass), |
| 4345 | offsetof(RISCVRegisterClassStorage, BitSets[332]) - 111 * sizeof(MCRegisterClass), |
| 4346 | .NameIdx: 247, |
| 4347 | .RegSizeInBits: 128, |
| 4348 | .RegsSize: 1, |
| 4349 | .RegSetBegin: 357, /* MinRegVal */ |
| 4350 | .RegSetSize: 1, /* RegSetSize */ |
| 4351 | .ID: RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4352 | .CopyCost: 2, /* CopyCost */ |
| 4353 | .Allocatable: true, /* Allocatable */ |
| 4354 | .BaseClass: false, |
| 4355 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1540]) - 111 * sizeof(MCRegisterClass), |
| 4356 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[31]) - 111 * sizeof(MCRegisterClass), |
| 4357 | .LaneMask: LaneBitmask(0x0000000000000006), |
| 4358 | .AllocationPriority: 2, |
| 4359 | .GlobalPriority: false, |
| 4360 | .TSFlags: 0x03, /* TSFlags */ |
| 4361 | .SpillStackID: 0, /* SpillStackID */ |
| 4362 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4363 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4364 | offsetof(RISCVRegisterClassStorage, SuperClasses[618]) - 111 * sizeof(MCRegisterClass), |
| 4365 | .SuperClassesSize: 1 |
| 4366 | }, |
| 4367 | { |
| 4368 | offsetof(RISCVRegisterClassStorage, Regs[1776]) - 112 * sizeof(MCRegisterClass), |
| 4369 | offsetof(RISCVRegisterClassStorage, BitSets[333]) - 112 * sizeof(MCRegisterClass), |
| 4370 | .NameIdx: 4, |
| 4371 | .RegSizeInBits: 128, |
| 4372 | .RegsSize: 1, |
| 4373 | .RegSetBegin: 430, /* MinRegVal */ |
| 4374 | .RegSetSize: 1, /* RegSetSize */ |
| 4375 | .ID: RISCV::VRN2M1_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4376 | .CopyCost: 2, /* CopyCost */ |
| 4377 | .Allocatable: true, /* Allocatable */ |
| 4378 | .BaseClass: false, |
| 4379 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1550]) - 112 * sizeof(MCRegisterClass), |
| 4380 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[49]) - 112 * sizeof(MCRegisterClass), |
| 4381 | .LaneMask: LaneBitmask(0x0000000000000006), |
| 4382 | .AllocationPriority: 0, |
| 4383 | .GlobalPriority: false, |
| 4384 | .TSFlags: 0x09, /* TSFlags */ |
| 4385 | .SpillStackID: 0, /* SpillStackID */ |
| 4386 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4387 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4388 | offsetof(RISCVRegisterClassStorage, SuperClasses[619]) - 112 * sizeof(MCRegisterClass), |
| 4389 | .SuperClassesSize: 1 |
| 4390 | }, |
| 4391 | { |
| 4392 | offsetof(RISCVRegisterClassStorage, Regs[1777]) - 113 * sizeof(MCRegisterClass), |
| 4393 | offsetof(RISCVRegisterClassStorage, BitSets[334]) - 113 * sizeof(MCRegisterClass), |
| 4394 | .NameIdx: 2232, |
| 4395 | .RegSizeInBits: 128, |
| 4396 | .RegsSize: 32, |
| 4397 | .RegSetBegin: 196, /* MinRegVal */ |
| 4398 | .RegSetSize: 32, /* RegSetSize */ |
| 4399 | .ID: RISCV::FPR128RegClassID, |
| 4400 | .CopyCost: 1, /* CopyCost */ |
| 4401 | .Allocatable: true, /* Allocatable */ |
| 4402 | .BaseClass: false, |
| 4403 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1560]) - 113 * sizeof(MCRegisterClass), |
| 4404 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[6]) - 113 * sizeof(MCRegisterClass), |
| 4405 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4406 | .AllocationPriority: 0, |
| 4407 | .GlobalPriority: false, |
| 4408 | .TSFlags: 0x00, /* TSFlags */ |
| 4409 | .SpillStackID: 0, /* SpillStackID */ |
| 4410 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4411 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4412 | offsetof(RISCVRegisterClassStorage, SuperClasses[620]) - 113 * sizeof(MCRegisterClass), |
| 4413 | .SuperClassesSize: 0 |
| 4414 | }, |
| 4415 | { |
| 4416 | offsetof(RISCVRegisterClassStorage, Regs[1809]) - 114 * sizeof(MCRegisterClass), |
| 4417 | offsetof(RISCVRegisterClassStorage, BitSets[338]) - 114 * sizeof(MCRegisterClass), |
| 4418 | .NameIdx: 2333, |
| 4419 | .RegSizeInBits: 128, |
| 4420 | .RegsSize: 8, |
| 4421 | .RegSetBegin: 204, /* MinRegVal */ |
| 4422 | .RegSetSize: 8, /* RegSetSize */ |
| 4423 | .ID: RISCV::FPR128_with_sub_16_in_FPR16CRegClassID, |
| 4424 | .CopyCost: 1, /* CopyCost */ |
| 4425 | .Allocatable: true, /* Allocatable */ |
| 4426 | .BaseClass: false, |
| 4427 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1570]) - 114 * sizeof(MCRegisterClass), |
| 4428 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[6]) - 114 * sizeof(MCRegisterClass), |
| 4429 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4430 | .AllocationPriority: 0, |
| 4431 | .GlobalPriority: false, |
| 4432 | .TSFlags: 0x00, /* TSFlags */ |
| 4433 | .SpillStackID: 0, /* SpillStackID */ |
| 4434 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4435 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4436 | offsetof(RISCVRegisterClassStorage, SuperClasses[620]) - 114 * sizeof(MCRegisterClass), |
| 4437 | .SuperClassesSize: 1 |
| 4438 | }, |
| 4439 | { |
| 4440 | offsetof(RISCVRegisterClassStorage, Regs[1817]) - 115 * sizeof(MCRegisterClass), |
| 4441 | offsetof(RISCVRegisterClassStorage, BitSets[339]) - 115 * sizeof(MCRegisterClass), |
| 4442 | .NameIdx: 1323, |
| 4443 | .RegSizeInBits: 192, |
| 4444 | .RegsSize: 30, |
| 4445 | .RegSetBegin: 453, /* MinRegVal */ |
| 4446 | .RegSetSize: 30, /* RegSetSize */ |
| 4447 | .ID: RISCV::VRN3M1RegClassID, |
| 4448 | .CopyCost: 3, /* CopyCost */ |
| 4449 | .Allocatable: true, /* Allocatable */ |
| 4450 | .BaseClass: false, |
| 4451 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1580]) - 115 * sizeof(MCRegisterClass), |
| 4452 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[81]) - 115 * sizeof(MCRegisterClass), |
| 4453 | .LaneMask: LaneBitmask(0x000000000000000E), |
| 4454 | .AllocationPriority: 0, |
| 4455 | .GlobalPriority: false, |
| 4456 | .TSFlags: 0x11, /* TSFlags */ |
| 4457 | .SpillStackID: 0, /* SpillStackID */ |
| 4458 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4459 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4460 | offsetof(RISCVRegisterClassStorage, SuperClasses[621]) - 115 * sizeof(MCRegisterClass), |
| 4461 | .SuperClassesSize: 0 |
| 4462 | }, |
| 4463 | { |
| 4464 | offsetof(RISCVRegisterClassStorage, Regs[1847]) - 116 * sizeof(MCRegisterClass), |
| 4465 | offsetof(RISCVRegisterClassStorage, BitSets[343]) - 116 * sizeof(MCRegisterClass), |
| 4466 | .NameIdx: 505, |
| 4467 | .RegSizeInBits: 192, |
| 4468 | .RegsSize: 29, |
| 4469 | .RegSetBegin: 453, /* MinRegVal */ |
| 4470 | .RegSetSize: 29, /* RegSetSize */ |
| 4471 | .ID: RISCV::VRN3M1NoV0RegClassID, |
| 4472 | .CopyCost: 3, /* CopyCost */ |
| 4473 | .Allocatable: true, /* Allocatable */ |
| 4474 | .BaseClass: false, |
| 4475 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1615]) - 116 * sizeof(MCRegisterClass), |
| 4476 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[81]) - 116 * sizeof(MCRegisterClass), |
| 4477 | .LaneMask: LaneBitmask(0x000000000000000E), |
| 4478 | .AllocationPriority: 0, |
| 4479 | .GlobalPriority: false, |
| 4480 | .TSFlags: 0x11, /* TSFlags */ |
| 4481 | .SpillStackID: 0, /* SpillStackID */ |
| 4482 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4483 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4484 | offsetof(RISCVRegisterClassStorage, SuperClasses[621]) - 116 * sizeof(MCRegisterClass), |
| 4485 | .SuperClassesSize: 1 |
| 4486 | }, |
| 4487 | { |
| 4488 | offsetof(RISCVRegisterClassStorage, Regs[1876]) - 117 * sizeof(MCRegisterClass), |
| 4489 | offsetof(RISCVRegisterClassStorage, BitSets[347]) - 117 * sizeof(MCRegisterClass), |
| 4490 | .NameIdx: 35, |
| 4491 | .RegSizeInBits: 192, |
| 4492 | .RegsSize: 1, |
| 4493 | .RegSetBegin: 482, /* MinRegVal */ |
| 4494 | .RegSetSize: 1, /* RegSetSize */ |
| 4495 | .ID: RISCV::VRN3M1_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4496 | .CopyCost: 3, /* CopyCost */ |
| 4497 | .Allocatable: true, /* Allocatable */ |
| 4498 | .BaseClass: false, |
| 4499 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1650]) - 117 * sizeof(MCRegisterClass), |
| 4500 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[51]) - 117 * sizeof(MCRegisterClass), |
| 4501 | .LaneMask: LaneBitmask(0x000000000000000E), |
| 4502 | .AllocationPriority: 0, |
| 4503 | .GlobalPriority: false, |
| 4504 | .TSFlags: 0x11, /* TSFlags */ |
| 4505 | .SpillStackID: 0, /* SpillStackID */ |
| 4506 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4507 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4508 | offsetof(RISCVRegisterClassStorage, SuperClasses[622]) - 117 * sizeof(MCRegisterClass), |
| 4509 | .SuperClassesSize: 1 |
| 4510 | }, |
| 4511 | { |
| 4512 | offsetof(RISCVRegisterClassStorage, Regs[1877]) - 118 * sizeof(MCRegisterClass), |
| 4513 | offsetof(RISCVRegisterClassStorage, BitSets[348]) - 118 * sizeof(MCRegisterClass), |
| 4514 | .NameIdx: 1330, |
| 4515 | .RegSizeInBits: 256, |
| 4516 | .RegsSize: 29, |
| 4517 | .RegSetBegin: 497, /* MinRegVal */ |
| 4518 | .RegSetSize: 29, /* RegSetSize */ |
| 4519 | .ID: RISCV::VRN4M1RegClassID, |
| 4520 | .CopyCost: 4, /* CopyCost */ |
| 4521 | .Allocatable: true, /* Allocatable */ |
| 4522 | .BaseClass: false, |
| 4523 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1660]) - 118 * sizeof(MCRegisterClass), |
| 4524 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[75]) - 118 * sizeof(MCRegisterClass), |
| 4525 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4526 | .AllocationPriority: 0, |
| 4527 | .GlobalPriority: false, |
| 4528 | .TSFlags: 0x19, /* TSFlags */ |
| 4529 | .SpillStackID: 0, /* SpillStackID */ |
| 4530 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4531 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4532 | offsetof(RISCVRegisterClassStorage, SuperClasses[623]) - 118 * sizeof(MCRegisterClass), |
| 4533 | .SuperClassesSize: 0 |
| 4534 | }, |
| 4535 | { |
| 4536 | offsetof(RISCVRegisterClassStorage, Regs[1906]) - 119 * sizeof(MCRegisterClass), |
| 4537 | offsetof(RISCVRegisterClassStorage, BitSets[352]) - 119 * sizeof(MCRegisterClass), |
| 4538 | .NameIdx: 516, |
| 4539 | .RegSizeInBits: 256, |
| 4540 | .RegsSize: 28, |
| 4541 | .RegSetBegin: 497, /* MinRegVal */ |
| 4542 | .RegSetSize: 28, /* RegSetSize */ |
| 4543 | .ID: RISCV::VRN4M1NoV0RegClassID, |
| 4544 | .CopyCost: 4, /* CopyCost */ |
| 4545 | .Allocatable: true, /* Allocatable */ |
| 4546 | .BaseClass: false, |
| 4547 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1690]) - 119 * sizeof(MCRegisterClass), |
| 4548 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[75]) - 119 * sizeof(MCRegisterClass), |
| 4549 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4550 | .AllocationPriority: 0, |
| 4551 | .GlobalPriority: false, |
| 4552 | .TSFlags: 0x19, /* TSFlags */ |
| 4553 | .SpillStackID: 0, /* SpillStackID */ |
| 4554 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4555 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4556 | offsetof(RISCVRegisterClassStorage, SuperClasses[623]) - 119 * sizeof(MCRegisterClass), |
| 4557 | .SuperClassesSize: 1 |
| 4558 | }, |
| 4559 | { |
| 4560 | offsetof(RISCVRegisterClassStorage, Regs[1934]) - 120 * sizeof(MCRegisterClass), |
| 4561 | offsetof(RISCVRegisterClassStorage, BitSets[356]) - 120 * sizeof(MCRegisterClass), |
| 4562 | .NameIdx: 1420, |
| 4563 | .RegSizeInBits: 256, |
| 4564 | .RegsSize: 15, |
| 4565 | .RegSetBegin: 431, /* MinRegVal */ |
| 4566 | .RegSetSize: 15, /* RegSetSize */ |
| 4567 | .ID: RISCV::VRN2M2RegClassID, |
| 4568 | .CopyCost: 4, /* CopyCost */ |
| 4569 | .Allocatable: true, /* Allocatable */ |
| 4570 | .BaseClass: false, |
| 4571 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1720]) - 120 * sizeof(MCRegisterClass), |
| 4572 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[105]) - 120 * sizeof(MCRegisterClass), |
| 4573 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4574 | .AllocationPriority: 2, |
| 4575 | .GlobalPriority: false, |
| 4576 | .TSFlags: 0x0b, /* TSFlags */ |
| 4577 | .SpillStackID: 0, /* SpillStackID */ |
| 4578 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4579 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4580 | offsetof(RISCVRegisterClassStorage, SuperClasses[624]) - 120 * sizeof(MCRegisterClass), |
| 4581 | .SuperClassesSize: 0 |
| 4582 | }, |
| 4583 | { |
| 4584 | offsetof(RISCVRegisterClassStorage, Regs[1949]) - 121 * sizeof(MCRegisterClass), |
| 4585 | offsetof(RISCVRegisterClassStorage, BitSets[358]) - 121 * sizeof(MCRegisterClass), |
| 4586 | .NameIdx: 585, |
| 4587 | .RegSizeInBits: 256, |
| 4588 | .RegsSize: 14, |
| 4589 | .RegSetBegin: 431, /* MinRegVal */ |
| 4590 | .RegSetSize: 14, /* RegSetSize */ |
| 4591 | .ID: RISCV::VRN2M2NoV0RegClassID, |
| 4592 | .CopyCost: 4, /* CopyCost */ |
| 4593 | .Allocatable: true, /* Allocatable */ |
| 4594 | .BaseClass: false, |
| 4595 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1740]) - 121 * sizeof(MCRegisterClass), |
| 4596 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[105]) - 121 * sizeof(MCRegisterClass), |
| 4597 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4598 | .AllocationPriority: 2, |
| 4599 | .GlobalPriority: false, |
| 4600 | .TSFlags: 0x0b, /* TSFlags */ |
| 4601 | .SpillStackID: 0, /* SpillStackID */ |
| 4602 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4603 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4604 | offsetof(RISCVRegisterClassStorage, SuperClasses[624]) - 121 * sizeof(MCRegisterClass), |
| 4605 | .SuperClassesSize: 1 |
| 4606 | }, |
| 4607 | { |
| 4608 | offsetof(RISCVRegisterClassStorage, Regs[1963]) - 122 * sizeof(MCRegisterClass), |
| 4609 | offsetof(RISCVRegisterClassStorage, BitSets[360]) - 122 * sizeof(MCRegisterClass), |
| 4610 | .NameIdx: 1625, |
| 4611 | .RegSizeInBits: 256, |
| 4612 | .RegsSize: 8, |
| 4613 | .RegSetBegin: 358, /* MinRegVal */ |
| 4614 | .RegSetSize: 26, /* RegSetSize */ |
| 4615 | .ID: RISCV::VRM4RegClassID, |
| 4616 | .CopyCost: 4, /* CopyCost */ |
| 4617 | .Allocatable: true, /* Allocatable */ |
| 4618 | .BaseClass: false, |
| 4619 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1760]) - 122 * sizeof(MCRegisterClass), |
| 4620 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[40]) - 122 * sizeof(MCRegisterClass), |
| 4621 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4622 | .AllocationPriority: 4, |
| 4623 | .GlobalPriority: false, |
| 4624 | .TSFlags: 0x05, /* TSFlags */ |
| 4625 | .SpillStackID: 0, /* SpillStackID */ |
| 4626 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4627 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4628 | offsetof(RISCVRegisterClassStorage, SuperClasses[625]) - 122 * sizeof(MCRegisterClass), |
| 4629 | .SuperClassesSize: 0 |
| 4630 | }, |
| 4631 | { |
| 4632 | offsetof(RISCVRegisterClassStorage, Regs[1971]) - 123 * sizeof(MCRegisterClass), |
| 4633 | offsetof(RISCVRegisterClassStorage, BitSets[364]) - 123 * sizeof(MCRegisterClass), |
| 4634 | .NameIdx: 652, |
| 4635 | .RegSizeInBits: 256, |
| 4636 | .RegsSize: 7, |
| 4637 | .RegSetBegin: 362, /* MinRegVal */ |
| 4638 | .RegSetSize: 22, /* RegSetSize */ |
| 4639 | .ID: RISCV::VRM4NoV0RegClassID, |
| 4640 | .CopyCost: 4, /* CopyCost */ |
| 4641 | .Allocatable: true, /* Allocatable */ |
| 4642 | .BaseClass: false, |
| 4643 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1775]) - 123 * sizeof(MCRegisterClass), |
| 4644 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[40]) - 123 * sizeof(MCRegisterClass), |
| 4645 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4646 | .AllocationPriority: 4, |
| 4647 | .GlobalPriority: false, |
| 4648 | .TSFlags: 0x05, /* TSFlags */ |
| 4649 | .SpillStackID: 0, /* SpillStackID */ |
| 4650 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4651 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4652 | offsetof(RISCVRegisterClassStorage, SuperClasses[625]) - 123 * sizeof(MCRegisterClass), |
| 4653 | .SuperClassesSize: 1 |
| 4654 | }, |
| 4655 | { |
| 4656 | offsetof(RISCVRegisterClassStorage, Regs[1978]) - 124 * sizeof(MCRegisterClass), |
| 4657 | offsetof(RISCVRegisterClassStorage, BitSets[367]) - 124 * sizeof(MCRegisterClass), |
| 4658 | .NameIdx: 412, |
| 4659 | .RegSizeInBits: 256, |
| 4660 | .RegsSize: 1, |
| 4661 | .RegSetBegin: 358, /* MinRegVal */ |
| 4662 | .RegSetSize: 1, /* RegSetSize */ |
| 4663 | .ID: RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4664 | .CopyCost: 4, /* CopyCost */ |
| 4665 | .Allocatable: true, /* Allocatable */ |
| 4666 | .BaseClass: false, |
| 4667 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1790]) - 124 * sizeof(MCRegisterClass), |
| 4668 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[38]) - 124 * sizeof(MCRegisterClass), |
| 4669 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4670 | .AllocationPriority: 4, |
| 4671 | .GlobalPriority: false, |
| 4672 | .TSFlags: 0x05, /* TSFlags */ |
| 4673 | .SpillStackID: 0, /* SpillStackID */ |
| 4674 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4675 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4676 | offsetof(RISCVRegisterClassStorage, SuperClasses[626]) - 124 * sizeof(MCRegisterClass), |
| 4677 | .SuperClassesSize: 1 |
| 4678 | }, |
| 4679 | { |
| 4680 | offsetof(RISCVRegisterClassStorage, Regs[1979]) - 125 * sizeof(MCRegisterClass), |
| 4681 | offsetof(RISCVRegisterClassStorage, BitSets[368]) - 125 * sizeof(MCRegisterClass), |
| 4682 | .NameIdx: 221, |
| 4683 | .RegSizeInBits: 256, |
| 4684 | .RegsSize: 1, |
| 4685 | .RegSetBegin: 445, /* MinRegVal */ |
| 4686 | .RegSetSize: 1, /* RegSetSize */ |
| 4687 | .ID: RISCV::VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4688 | .CopyCost: 4, /* CopyCost */ |
| 4689 | .Allocatable: true, /* Allocatable */ |
| 4690 | .BaseClass: false, |
| 4691 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1800]) - 125 * sizeof(MCRegisterClass), |
| 4692 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[96]) - 125 * sizeof(MCRegisterClass), |
| 4693 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4694 | .AllocationPriority: 2, |
| 4695 | .GlobalPriority: false, |
| 4696 | .TSFlags: 0x0b, /* TSFlags */ |
| 4697 | .SpillStackID: 0, /* SpillStackID */ |
| 4698 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4699 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4700 | offsetof(RISCVRegisterClassStorage, SuperClasses[627]) - 125 * sizeof(MCRegisterClass), |
| 4701 | .SuperClassesSize: 1 |
| 4702 | }, |
| 4703 | { |
| 4704 | offsetof(RISCVRegisterClassStorage, Regs[1980]) - 126 * sizeof(MCRegisterClass), |
| 4705 | offsetof(RISCVRegisterClassStorage, BitSets[369]) - 126 * sizeof(MCRegisterClass), |
| 4706 | .NameIdx: 66, |
| 4707 | .RegSizeInBits: 256, |
| 4708 | .RegsSize: 1, |
| 4709 | .RegSetBegin: 525, /* MinRegVal */ |
| 4710 | .RegSetSize: 1, /* RegSetSize */ |
| 4711 | .ID: RISCV::VRN4M1_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4712 | .CopyCost: 4, /* CopyCost */ |
| 4713 | .Allocatable: true, /* Allocatable */ |
| 4714 | .BaseClass: false, |
| 4715 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1810]) - 126 * sizeof(MCRegisterClass), |
| 4716 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[53]) - 126 * sizeof(MCRegisterClass), |
| 4717 | .LaneMask: LaneBitmask(0x000000000000001E), |
| 4718 | .AllocationPriority: 0, |
| 4719 | .GlobalPriority: false, |
| 4720 | .TSFlags: 0x19, /* TSFlags */ |
| 4721 | .SpillStackID: 0, /* SpillStackID */ |
| 4722 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4723 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4724 | offsetof(RISCVRegisterClassStorage, SuperClasses[628]) - 126 * sizeof(MCRegisterClass), |
| 4725 | .SuperClassesSize: 1 |
| 4726 | }, |
| 4727 | { |
| 4728 | offsetof(RISCVRegisterClassStorage, Regs[1981]) - 127 * sizeof(MCRegisterClass), |
| 4729 | offsetof(RISCVRegisterClassStorage, BitSets[370]) - 127 * sizeof(MCRegisterClass), |
| 4730 | .NameIdx: 1745, |
| 4731 | .RegSizeInBits: 256, |
| 4732 | .RegsSize: 32, |
| 4733 | .RegSetBegin: 325, /* MinRegVal */ |
| 4734 | .RegSetSize: 32, /* RegSetSize */ |
| 4735 | .ID: RISCV::FPR256RegClassID, |
| 4736 | .CopyCost: 1, /* CopyCost */ |
| 4737 | .Allocatable: true, /* Allocatable */ |
| 4738 | .BaseClass: false, |
| 4739 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1820]) - 127 * sizeof(MCRegisterClass), |
| 4740 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 127 * sizeof(MCRegisterClass), |
| 4741 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4742 | .AllocationPriority: 0, |
| 4743 | .GlobalPriority: false, |
| 4744 | .TSFlags: 0x00, /* TSFlags */ |
| 4745 | .SpillStackID: 0, /* SpillStackID */ |
| 4746 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4747 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4748 | offsetof(RISCVRegisterClassStorage, SuperClasses[629]) - 127 * sizeof(MCRegisterClass), |
| 4749 | .SuperClassesSize: 0 |
| 4750 | }, |
| 4751 | { |
| 4752 | offsetof(RISCVRegisterClassStorage, Regs[2013]) - 128 * sizeof(MCRegisterClass), |
| 4753 | offsetof(RISCVRegisterClassStorage, BitSets[374]) - 128 * sizeof(MCRegisterClass), |
| 4754 | .NameIdx: 2304, |
| 4755 | .RegSizeInBits: 256, |
| 4756 | .RegsSize: 8, |
| 4757 | .RegSetBegin: 333, /* MinRegVal */ |
| 4758 | .RegSetSize: 8, /* RegSetSize */ |
| 4759 | .ID: RISCV::FPR256_with_sub_16_in_FPR16CRegClassID, |
| 4760 | .CopyCost: 1, /* CopyCost */ |
| 4761 | .Allocatable: true, /* Allocatable */ |
| 4762 | .BaseClass: false, |
| 4763 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1825]) - 128 * sizeof(MCRegisterClass), |
| 4764 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 128 * sizeof(MCRegisterClass), |
| 4765 | .LaneMask: LaneBitmask(0x0000000000000001), |
| 4766 | .AllocationPriority: 0, |
| 4767 | .GlobalPriority: false, |
| 4768 | .TSFlags: 0x00, /* TSFlags */ |
| 4769 | .SpillStackID: 0, /* SpillStackID */ |
| 4770 | .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */ |
| 4771 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 4772 | offsetof(RISCVRegisterClassStorage, SuperClasses[629]) - 128 * sizeof(MCRegisterClass), |
| 4773 | .SuperClassesSize: 1 |
| 4774 | }, |
| 4775 | { |
| 4776 | offsetof(RISCVRegisterClassStorage, Regs[2021]) - 129 * sizeof(MCRegisterClass), |
| 4777 | offsetof(RISCVRegisterClassStorage, BitSets[375]) - 129 * sizeof(MCRegisterClass), |
| 4778 | .NameIdx: 1337, |
| 4779 | .RegSizeInBits: 320, |
| 4780 | .RegsSize: 28, |
| 4781 | .RegSetBegin: 539, /* MinRegVal */ |
| 4782 | .RegSetSize: 28, /* RegSetSize */ |
| 4783 | .ID: RISCV::VRN5M1RegClassID, |
| 4784 | .CopyCost: 5, /* CopyCost */ |
| 4785 | .Allocatable: true, /* Allocatable */ |
| 4786 | .BaseClass: false, |
| 4787 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1830]) - 129 * sizeof(MCRegisterClass), |
| 4788 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[70]) - 129 * sizeof(MCRegisterClass), |
| 4789 | .LaneMask: LaneBitmask(0x000000000000003E), |
| 4790 | .AllocationPriority: 0, |
| 4791 | .GlobalPriority: false, |
| 4792 | .TSFlags: 0x21, /* TSFlags */ |
| 4793 | .SpillStackID: 0, /* SpillStackID */ |
| 4794 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4795 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4796 | offsetof(RISCVRegisterClassStorage, SuperClasses[630]) - 129 * sizeof(MCRegisterClass), |
| 4797 | .SuperClassesSize: 0 |
| 4798 | }, |
| 4799 | { |
| 4800 | offsetof(RISCVRegisterClassStorage, Regs[2049]) - 130 * sizeof(MCRegisterClass), |
| 4801 | offsetof(RISCVRegisterClassStorage, BitSets[379]) - 130 * sizeof(MCRegisterClass), |
| 4802 | .NameIdx: 527, |
| 4803 | .RegSizeInBits: 320, |
| 4804 | .RegsSize: 27, |
| 4805 | .RegSetBegin: 539, /* MinRegVal */ |
| 4806 | .RegSetSize: 27, /* RegSetSize */ |
| 4807 | .ID: RISCV::VRN5M1NoV0RegClassID, |
| 4808 | .CopyCost: 5, /* CopyCost */ |
| 4809 | .Allocatable: true, /* Allocatable */ |
| 4810 | .BaseClass: false, |
| 4811 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1855]) - 130 * sizeof(MCRegisterClass), |
| 4812 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[70]) - 130 * sizeof(MCRegisterClass), |
| 4813 | .LaneMask: LaneBitmask(0x000000000000003E), |
| 4814 | .AllocationPriority: 0, |
| 4815 | .GlobalPriority: false, |
| 4816 | .TSFlags: 0x21, /* TSFlags */ |
| 4817 | .SpillStackID: 0, /* SpillStackID */ |
| 4818 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4819 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4820 | offsetof(RISCVRegisterClassStorage, SuperClasses[630]) - 130 * sizeof(MCRegisterClass), |
| 4821 | .SuperClassesSize: 1 |
| 4822 | }, |
| 4823 | { |
| 4824 | offsetof(RISCVRegisterClassStorage, Regs[2076]) - 131 * sizeof(MCRegisterClass), |
| 4825 | offsetof(RISCVRegisterClassStorage, BitSets[383]) - 131 * sizeof(MCRegisterClass), |
| 4826 | .NameIdx: 97, |
| 4827 | .RegSizeInBits: 320, |
| 4828 | .RegsSize: 1, |
| 4829 | .RegSetBegin: 566, /* MinRegVal */ |
| 4830 | .RegSetSize: 1, /* RegSetSize */ |
| 4831 | .ID: RISCV::VRN5M1_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4832 | .CopyCost: 5, /* CopyCost */ |
| 4833 | .Allocatable: true, /* Allocatable */ |
| 4834 | .BaseClass: false, |
| 4835 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1880]) - 131 * sizeof(MCRegisterClass), |
| 4836 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[55]) - 131 * sizeof(MCRegisterClass), |
| 4837 | .LaneMask: LaneBitmask(0x000000000000003E), |
| 4838 | .AllocationPriority: 0, |
| 4839 | .GlobalPriority: false, |
| 4840 | .TSFlags: 0x21, /* TSFlags */ |
| 4841 | .SpillStackID: 0, /* SpillStackID */ |
| 4842 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4843 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4844 | offsetof(RISCVRegisterClassStorage, SuperClasses[631]) - 131 * sizeof(MCRegisterClass), |
| 4845 | .SuperClassesSize: 1 |
| 4846 | }, |
| 4847 | { |
| 4848 | offsetof(RISCVRegisterClassStorage, Regs[2077]) - 132 * sizeof(MCRegisterClass), |
| 4849 | offsetof(RISCVRegisterClassStorage, BitSets[384]) - 132 * sizeof(MCRegisterClass), |
| 4850 | .NameIdx: 1344, |
| 4851 | .RegSizeInBits: 384, |
| 4852 | .RegsSize: 27, |
| 4853 | .RegSetBegin: 567, /* MinRegVal */ |
| 4854 | .RegSetSize: 27, /* RegSetSize */ |
| 4855 | .ID: RISCV::VRN6M1RegClassID, |
| 4856 | .CopyCost: 6, /* CopyCost */ |
| 4857 | .Allocatable: true, /* Allocatable */ |
| 4858 | .BaseClass: false, |
| 4859 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1890]) - 132 * sizeof(MCRegisterClass), |
| 4860 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[66]) - 132 * sizeof(MCRegisterClass), |
| 4861 | .LaneMask: LaneBitmask(0x000000000000007E), |
| 4862 | .AllocationPriority: 0, |
| 4863 | .GlobalPriority: false, |
| 4864 | .TSFlags: 0x29, /* TSFlags */ |
| 4865 | .SpillStackID: 0, /* SpillStackID */ |
| 4866 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4867 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4868 | offsetof(RISCVRegisterClassStorage, SuperClasses[632]) - 132 * sizeof(MCRegisterClass), |
| 4869 | .SuperClassesSize: 0 |
| 4870 | }, |
| 4871 | { |
| 4872 | offsetof(RISCVRegisterClassStorage, Regs[2104]) - 133 * sizeof(MCRegisterClass), |
| 4873 | offsetof(RISCVRegisterClassStorage, BitSets[388]) - 133 * sizeof(MCRegisterClass), |
| 4874 | .NameIdx: 538, |
| 4875 | .RegSizeInBits: 384, |
| 4876 | .RegsSize: 26, |
| 4877 | .RegSetBegin: 567, /* MinRegVal */ |
| 4878 | .RegSetSize: 26, /* RegSetSize */ |
| 4879 | .ID: RISCV::VRN6M1NoV0RegClassID, |
| 4880 | .CopyCost: 6, /* CopyCost */ |
| 4881 | .Allocatable: true, /* Allocatable */ |
| 4882 | .BaseClass: false, |
| 4883 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1910]) - 133 * sizeof(MCRegisterClass), |
| 4884 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[66]) - 133 * sizeof(MCRegisterClass), |
| 4885 | .LaneMask: LaneBitmask(0x000000000000007E), |
| 4886 | .AllocationPriority: 0, |
| 4887 | .GlobalPriority: false, |
| 4888 | .TSFlags: 0x29, /* TSFlags */ |
| 4889 | .SpillStackID: 0, /* SpillStackID */ |
| 4890 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4891 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4892 | offsetof(RISCVRegisterClassStorage, SuperClasses[632]) - 133 * sizeof(MCRegisterClass), |
| 4893 | .SuperClassesSize: 1 |
| 4894 | }, |
| 4895 | { |
| 4896 | offsetof(RISCVRegisterClassStorage, Regs[2130]) - 134 * sizeof(MCRegisterClass), |
| 4897 | offsetof(RISCVRegisterClassStorage, BitSets[392]) - 134 * sizeof(MCRegisterClass), |
| 4898 | .NameIdx: 1427, |
| 4899 | .RegSizeInBits: 384, |
| 4900 | .RegsSize: 14, |
| 4901 | .RegSetBegin: 483, /* MinRegVal */ |
| 4902 | .RegSetSize: 14, /* RegSetSize */ |
| 4903 | .ID: RISCV::VRN3M2RegClassID, |
| 4904 | .CopyCost: 6, /* CopyCost */ |
| 4905 | .Allocatable: true, /* Allocatable */ |
| 4906 | .BaseClass: false, |
| 4907 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1930]) - 134 * sizeof(MCRegisterClass), |
| 4908 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[102]) - 134 * sizeof(MCRegisterClass), |
| 4909 | .LaneMask: LaneBitmask(0x000000000000007E), |
| 4910 | .AllocationPriority: 2, |
| 4911 | .GlobalPriority: false, |
| 4912 | .TSFlags: 0x13, /* TSFlags */ |
| 4913 | .SpillStackID: 0, /* SpillStackID */ |
| 4914 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4915 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4916 | offsetof(RISCVRegisterClassStorage, SuperClasses[633]) - 134 * sizeof(MCRegisterClass), |
| 4917 | .SuperClassesSize: 0 |
| 4918 | }, |
| 4919 | { |
| 4920 | offsetof(RISCVRegisterClassStorage, Regs[2144]) - 135 * sizeof(MCRegisterClass), |
| 4921 | offsetof(RISCVRegisterClassStorage, BitSets[394]) - 135 * sizeof(MCRegisterClass), |
| 4922 | .NameIdx: 596, |
| 4923 | .RegSizeInBits: 384, |
| 4924 | .RegsSize: 13, |
| 4925 | .RegSetBegin: 483, /* MinRegVal */ |
| 4926 | .RegSetSize: 13, /* RegSetSize */ |
| 4927 | .ID: RISCV::VRN3M2NoV0RegClassID, |
| 4928 | .CopyCost: 6, /* CopyCost */ |
| 4929 | .Allocatable: true, /* Allocatable */ |
| 4930 | .BaseClass: false, |
| 4931 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1945]) - 135 * sizeof(MCRegisterClass), |
| 4932 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[102]) - 135 * sizeof(MCRegisterClass), |
| 4933 | .LaneMask: LaneBitmask(0x000000000000007E), |
| 4934 | .AllocationPriority: 2, |
| 4935 | .GlobalPriority: false, |
| 4936 | .TSFlags: 0x13, /* TSFlags */ |
| 4937 | .SpillStackID: 0, /* SpillStackID */ |
| 4938 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4939 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4940 | offsetof(RISCVRegisterClassStorage, SuperClasses[633]) - 135 * sizeof(MCRegisterClass), |
| 4941 | .SuperClassesSize: 1 |
| 4942 | }, |
| 4943 | { |
| 4944 | offsetof(RISCVRegisterClassStorage, Regs[2157]) - 136 * sizeof(MCRegisterClass), |
| 4945 | offsetof(RISCVRegisterClassStorage, BitSets[396]) - 136 * sizeof(MCRegisterClass), |
| 4946 | .NameIdx: 276, |
| 4947 | .RegSizeInBits: 384, |
| 4948 | .RegsSize: 1, |
| 4949 | .RegSetBegin: 496, /* MinRegVal */ |
| 4950 | .RegSetSize: 1, /* RegSetSize */ |
| 4951 | .ID: RISCV::VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4952 | .CopyCost: 6, /* CopyCost */ |
| 4953 | .Allocatable: true, /* Allocatable */ |
| 4954 | .BaseClass: false, |
| 4955 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1960]) - 136 * sizeof(MCRegisterClass), |
| 4956 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[98]) - 136 * sizeof(MCRegisterClass), |
| 4957 | .LaneMask: LaneBitmask(0x000000000000007E), |
| 4958 | .AllocationPriority: 2, |
| 4959 | .GlobalPriority: false, |
| 4960 | .TSFlags: 0x13, /* TSFlags */ |
| 4961 | .SpillStackID: 0, /* SpillStackID */ |
| 4962 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4963 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4964 | offsetof(RISCVRegisterClassStorage, SuperClasses[634]) - 136 * sizeof(MCRegisterClass), |
| 4965 | .SuperClassesSize: 1 |
| 4966 | }, |
| 4967 | { |
| 4968 | offsetof(RISCVRegisterClassStorage, Regs[2158]) - 137 * sizeof(MCRegisterClass), |
| 4969 | offsetof(RISCVRegisterClassStorage, BitSets[397]) - 137 * sizeof(MCRegisterClass), |
| 4970 | .NameIdx: 128, |
| 4971 | .RegSizeInBits: 384, |
| 4972 | .RegsSize: 1, |
| 4973 | .RegSetBegin: 593, /* MinRegVal */ |
| 4974 | .RegSetSize: 1, /* RegSetSize */ |
| 4975 | .ID: RISCV::VRN6M1_with_sub_vrm1_0_in_VMV0RegClassID, |
| 4976 | .CopyCost: 6, /* CopyCost */ |
| 4977 | .Allocatable: true, /* Allocatable */ |
| 4978 | .BaseClass: false, |
| 4979 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1970]) - 137 * sizeof(MCRegisterClass), |
| 4980 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[57]) - 137 * sizeof(MCRegisterClass), |
| 4981 | .LaneMask: LaneBitmask(0x000000000000007E), |
| 4982 | .AllocationPriority: 0, |
| 4983 | .GlobalPriority: false, |
| 4984 | .TSFlags: 0x29, /* TSFlags */ |
| 4985 | .SpillStackID: 0, /* SpillStackID */ |
| 4986 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 4987 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 4988 | offsetof(RISCVRegisterClassStorage, SuperClasses[635]) - 137 * sizeof(MCRegisterClass), |
| 4989 | .SuperClassesSize: 1 |
| 4990 | }, |
| 4991 | { |
| 4992 | offsetof(RISCVRegisterClassStorage, Regs[2159]) - 138 * sizeof(MCRegisterClass), |
| 4993 | offsetof(RISCVRegisterClassStorage, BitSets[398]) - 138 * sizeof(MCRegisterClass), |
| 4994 | .NameIdx: 1351, |
| 4995 | .RegSizeInBits: 448, |
| 4996 | .RegsSize: 26, |
| 4997 | .RegSetBegin: 594, /* MinRegVal */ |
| 4998 | .RegSetSize: 26, /* RegSetSize */ |
| 4999 | .ID: RISCV::VRN7M1RegClassID, |
| 5000 | .CopyCost: 7, /* CopyCost */ |
| 5001 | .Allocatable: true, /* Allocatable */ |
| 5002 | .BaseClass: false, |
| 5003 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1980]) - 138 * sizeof(MCRegisterClass), |
| 5004 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[63]) - 138 * sizeof(MCRegisterClass), |
| 5005 | .LaneMask: LaneBitmask(0x00000000000000FE), |
| 5006 | .AllocationPriority: 0, |
| 5007 | .GlobalPriority: false, |
| 5008 | .TSFlags: 0x31, /* TSFlags */ |
| 5009 | .SpillStackID: 0, /* SpillStackID */ |
| 5010 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5011 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5012 | offsetof(RISCVRegisterClassStorage, SuperClasses[636]) - 138 * sizeof(MCRegisterClass), |
| 5013 | .SuperClassesSize: 0 |
| 5014 | }, |
| 5015 | { |
| 5016 | offsetof(RISCVRegisterClassStorage, Regs[2185]) - 139 * sizeof(MCRegisterClass), |
| 5017 | offsetof(RISCVRegisterClassStorage, BitSets[402]) - 139 * sizeof(MCRegisterClass), |
| 5018 | .NameIdx: 549, |
| 5019 | .RegSizeInBits: 448, |
| 5020 | .RegsSize: 25, |
| 5021 | .RegSetBegin: 594, /* MinRegVal */ |
| 5022 | .RegSetSize: 25, /* RegSetSize */ |
| 5023 | .ID: RISCV::VRN7M1NoV0RegClassID, |
| 5024 | .CopyCost: 7, /* CopyCost */ |
| 5025 | .Allocatable: true, /* Allocatable */ |
| 5026 | .BaseClass: false, |
| 5027 | offsetof(RISCVRegisterClassStorage, SubClassMasks[1995]) - 139 * sizeof(MCRegisterClass), |
| 5028 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[63]) - 139 * sizeof(MCRegisterClass), |
| 5029 | .LaneMask: LaneBitmask(0x00000000000000FE), |
| 5030 | .AllocationPriority: 0, |
| 5031 | .GlobalPriority: false, |
| 5032 | .TSFlags: 0x31, /* TSFlags */ |
| 5033 | .SpillStackID: 0, /* SpillStackID */ |
| 5034 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5035 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5036 | offsetof(RISCVRegisterClassStorage, SuperClasses[636]) - 139 * sizeof(MCRegisterClass), |
| 5037 | .SuperClassesSize: 1 |
| 5038 | }, |
| 5039 | { |
| 5040 | offsetof(RISCVRegisterClassStorage, Regs[2210]) - 140 * sizeof(MCRegisterClass), |
| 5041 | offsetof(RISCVRegisterClassStorage, BitSets[406]) - 140 * sizeof(MCRegisterClass), |
| 5042 | .NameIdx: 159, |
| 5043 | .RegSizeInBits: 448, |
| 5044 | .RegsSize: 1, |
| 5045 | .RegSetBegin: 619, /* MinRegVal */ |
| 5046 | .RegSetSize: 1, /* RegSetSize */ |
| 5047 | .ID: RISCV::VRN7M1_with_sub_vrm1_0_in_VMV0RegClassID, |
| 5048 | .CopyCost: 7, /* CopyCost */ |
| 5049 | .Allocatable: true, /* Allocatable */ |
| 5050 | .BaseClass: false, |
| 5051 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2010]) - 140 * sizeof(MCRegisterClass), |
| 5052 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[59]) - 140 * sizeof(MCRegisterClass), |
| 5053 | .LaneMask: LaneBitmask(0x00000000000000FE), |
| 5054 | .AllocationPriority: 0, |
| 5055 | .GlobalPriority: false, |
| 5056 | .TSFlags: 0x31, /* TSFlags */ |
| 5057 | .SpillStackID: 0, /* SpillStackID */ |
| 5058 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5059 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5060 | offsetof(RISCVRegisterClassStorage, SuperClasses[637]) - 140 * sizeof(MCRegisterClass), |
| 5061 | .SuperClassesSize: 1 |
| 5062 | }, |
| 5063 | { |
| 5064 | offsetof(RISCVRegisterClassStorage, Regs[2211]) - 141 * sizeof(MCRegisterClass), |
| 5065 | offsetof(RISCVRegisterClassStorage, BitSets[407]) - 141 * sizeof(MCRegisterClass), |
| 5066 | .NameIdx: 1358, |
| 5067 | .RegSizeInBits: 512, |
| 5068 | .RegsSize: 25, |
| 5069 | .RegSetBegin: 620, /* MinRegVal */ |
| 5070 | .RegSetSize: 25, /* RegSetSize */ |
| 5071 | .ID: RISCV::VRN8M1RegClassID, |
| 5072 | .CopyCost: 8, /* CopyCost */ |
| 5073 | .Allocatable: true, /* Allocatable */ |
| 5074 | .BaseClass: false, |
| 5075 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2020]) - 141 * sizeof(MCRegisterClass), |
| 5076 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[61]) - 141 * sizeof(MCRegisterClass), |
| 5077 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5078 | .AllocationPriority: 0, |
| 5079 | .GlobalPriority: false, |
| 5080 | .TSFlags: 0x39, /* TSFlags */ |
| 5081 | .SpillStackID: 0, /* SpillStackID */ |
| 5082 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5083 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5084 | offsetof(RISCVRegisterClassStorage, SuperClasses[638]) - 141 * sizeof(MCRegisterClass), |
| 5085 | .SuperClassesSize: 0 |
| 5086 | }, |
| 5087 | { |
| 5088 | offsetof(RISCVRegisterClassStorage, Regs[2236]) - 142 * sizeof(MCRegisterClass), |
| 5089 | offsetof(RISCVRegisterClassStorage, BitSets[411]) - 142 * sizeof(MCRegisterClass), |
| 5090 | .NameIdx: 560, |
| 5091 | .RegSizeInBits: 512, |
| 5092 | .RegsSize: 24, |
| 5093 | .RegSetBegin: 620, /* MinRegVal */ |
| 5094 | .RegSetSize: 24, /* RegSetSize */ |
| 5095 | .ID: RISCV::VRN8M1NoV0RegClassID, |
| 5096 | .CopyCost: 8, /* CopyCost */ |
| 5097 | .Allocatable: true, /* Allocatable */ |
| 5098 | .BaseClass: false, |
| 5099 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2030]) - 142 * sizeof(MCRegisterClass), |
| 5100 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[61]) - 142 * sizeof(MCRegisterClass), |
| 5101 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5102 | .AllocationPriority: 0, |
| 5103 | .GlobalPriority: false, |
| 5104 | .TSFlags: 0x39, /* TSFlags */ |
| 5105 | .SpillStackID: 0, /* SpillStackID */ |
| 5106 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5107 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5108 | offsetof(RISCVRegisterClassStorage, SuperClasses[638]) - 142 * sizeof(MCRegisterClass), |
| 5109 | .SuperClassesSize: 1 |
| 5110 | }, |
| 5111 | { |
| 5112 | offsetof(RISCVRegisterClassStorage, Regs[2260]) - 143 * sizeof(MCRegisterClass), |
| 5113 | offsetof(RISCVRegisterClassStorage, BitSets[414]) - 143 * sizeof(MCRegisterClass), |
| 5114 | .NameIdx: 1434, |
| 5115 | .RegSizeInBits: 512, |
| 5116 | .RegsSize: 13, |
| 5117 | .RegSetBegin: 526, /* MinRegVal */ |
| 5118 | .RegSetSize: 13, /* RegSetSize */ |
| 5119 | .ID: RISCV::VRN4M2RegClassID, |
| 5120 | .CopyCost: 8, /* CopyCost */ |
| 5121 | .Allocatable: true, /* Allocatable */ |
| 5122 | .BaseClass: false, |
| 5123 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2040]) - 143 * sizeof(MCRegisterClass), |
| 5124 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[100]) - 143 * sizeof(MCRegisterClass), |
| 5125 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5126 | .AllocationPriority: 2, |
| 5127 | .GlobalPriority: false, |
| 5128 | .TSFlags: 0x1b, /* TSFlags */ |
| 5129 | .SpillStackID: 0, /* SpillStackID */ |
| 5130 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5131 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5132 | offsetof(RISCVRegisterClassStorage, SuperClasses[639]) - 143 * sizeof(MCRegisterClass), |
| 5133 | .SuperClassesSize: 0 |
| 5134 | }, |
| 5135 | { |
| 5136 | offsetof(RISCVRegisterClassStorage, Regs[2273]) - 144 * sizeof(MCRegisterClass), |
| 5137 | offsetof(RISCVRegisterClassStorage, BitSets[416]) - 144 * sizeof(MCRegisterClass), |
| 5138 | .NameIdx: 607, |
| 5139 | .RegSizeInBits: 512, |
| 5140 | .RegsSize: 12, |
| 5141 | .RegSetBegin: 526, /* MinRegVal */ |
| 5142 | .RegSetSize: 12, /* RegSetSize */ |
| 5143 | .ID: RISCV::VRN4M2NoV0RegClassID, |
| 5144 | .CopyCost: 8, /* CopyCost */ |
| 5145 | .Allocatable: true, /* Allocatable */ |
| 5146 | .BaseClass: false, |
| 5147 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2050]) - 144 * sizeof(MCRegisterClass), |
| 5148 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[100]) - 144 * sizeof(MCRegisterClass), |
| 5149 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5150 | .AllocationPriority: 2, |
| 5151 | .GlobalPriority: false, |
| 5152 | .TSFlags: 0x1b, /* TSFlags */ |
| 5153 | .SpillStackID: 0, /* SpillStackID */ |
| 5154 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5155 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5156 | offsetof(RISCVRegisterClassStorage, SuperClasses[639]) - 144 * sizeof(MCRegisterClass), |
| 5157 | .SuperClassesSize: 1 |
| 5158 | }, |
| 5159 | { |
| 5160 | offsetof(RISCVRegisterClassStorage, Regs[2285]) - 145 * sizeof(MCRegisterClass), |
| 5161 | offsetof(RISCVRegisterClassStorage, BitSets[418]) - 145 * sizeof(MCRegisterClass), |
| 5162 | .NameIdx: 1613, |
| 5163 | .RegSizeInBits: 512, |
| 5164 | .RegsSize: 7, |
| 5165 | .RegSetBegin: 446, /* MinRegVal */ |
| 5166 | .RegSetSize: 7, /* RegSetSize */ |
| 5167 | .ID: RISCV::VRN2M4RegClassID, |
| 5168 | .CopyCost: 8, /* CopyCost */ |
| 5169 | .Allocatable: true, /* Allocatable */ |
| 5170 | .BaseClass: false, |
| 5171 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2060]) - 145 * sizeof(MCRegisterClass), |
| 5172 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 145 * sizeof(MCRegisterClass), |
| 5173 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5174 | .AllocationPriority: 4, |
| 5175 | .GlobalPriority: false, |
| 5176 | .TSFlags: 0x0d, /* TSFlags */ |
| 5177 | .SpillStackID: 0, /* SpillStackID */ |
| 5178 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5179 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5180 | offsetof(RISCVRegisterClassStorage, SuperClasses[640]) - 145 * sizeof(MCRegisterClass), |
| 5181 | .SuperClassesSize: 0 |
| 5182 | }, |
| 5183 | { |
| 5184 | offsetof(RISCVRegisterClassStorage, Regs[2292]) - 146 * sizeof(MCRegisterClass), |
| 5185 | offsetof(RISCVRegisterClassStorage, BitSets[419]) - 146 * sizeof(MCRegisterClass), |
| 5186 | .NameIdx: 641, |
| 5187 | .RegSizeInBits: 512, |
| 5188 | .RegsSize: 6, |
| 5189 | .RegSetBegin: 446, /* MinRegVal */ |
| 5190 | .RegSetSize: 6, /* RegSetSize */ |
| 5191 | .ID: RISCV::VRN2M4NoV0RegClassID, |
| 5192 | .CopyCost: 8, /* CopyCost */ |
| 5193 | .Allocatable: true, /* Allocatable */ |
| 5194 | .BaseClass: false, |
| 5195 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2065]) - 146 * sizeof(MCRegisterClass), |
| 5196 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 146 * sizeof(MCRegisterClass), |
| 5197 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5198 | .AllocationPriority: 4, |
| 5199 | .GlobalPriority: false, |
| 5200 | .TSFlags: 0x0d, /* TSFlags */ |
| 5201 | .SpillStackID: 0, /* SpillStackID */ |
| 5202 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5203 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5204 | offsetof(RISCVRegisterClassStorage, SuperClasses[640]) - 146 * sizeof(MCRegisterClass), |
| 5205 | .SuperClassesSize: 1 |
| 5206 | }, |
| 5207 | { |
| 5208 | offsetof(RISCVRegisterClassStorage, Regs[2298]) - 147 * sizeof(MCRegisterClass), |
| 5209 | offsetof(RISCVRegisterClassStorage, BitSets[420]) - 147 * sizeof(MCRegisterClass), |
| 5210 | .NameIdx: 2249, |
| 5211 | .RegSizeInBits: 512, |
| 5212 | .RegsSize: 4, |
| 5213 | .RegSetBegin: 359, /* MinRegVal */ |
| 5214 | .RegSetSize: 22, /* RegSetSize */ |
| 5215 | .ID: RISCV::VRM8RegClassID, |
| 5216 | .CopyCost: 8, /* CopyCost */ |
| 5217 | .Allocatable: true, /* Allocatable */ |
| 5218 | .BaseClass: false, |
| 5219 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2070]) - 147 * sizeof(MCRegisterClass), |
| 5220 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 147 * sizeof(MCRegisterClass), |
| 5221 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5222 | .AllocationPriority: 8, |
| 5223 | .GlobalPriority: false, |
| 5224 | .TSFlags: 0x07, /* TSFlags */ |
| 5225 | .SpillStackID: 0, /* SpillStackID */ |
| 5226 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5227 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 5228 | offsetof(RISCVRegisterClassStorage, SuperClasses[641]) - 147 * sizeof(MCRegisterClass), |
| 5229 | .SuperClassesSize: 0 |
| 5230 | }, |
| 5231 | { |
| 5232 | offsetof(RISCVRegisterClassStorage, Regs[2302]) - 148 * sizeof(MCRegisterClass), |
| 5233 | offsetof(RISCVRegisterClassStorage, BitSets[423]) - 148 * sizeof(MCRegisterClass), |
| 5234 | .NameIdx: 675, |
| 5235 | .RegSizeInBits: 512, |
| 5236 | .RegsSize: 3, |
| 5237 | .RegSetBegin: 366, /* MinRegVal */ |
| 5238 | .RegSetSize: 15, /* RegSetSize */ |
| 5239 | .ID: RISCV::VRM8NoV0RegClassID, |
| 5240 | .CopyCost: 8, /* CopyCost */ |
| 5241 | .Allocatable: true, /* Allocatable */ |
| 5242 | .BaseClass: false, |
| 5243 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2075]) - 148 * sizeof(MCRegisterClass), |
| 5244 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 148 * sizeof(MCRegisterClass), |
| 5245 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5246 | .AllocationPriority: 8, |
| 5247 | .GlobalPriority: false, |
| 5248 | .TSFlags: 0x07, /* TSFlags */ |
| 5249 | .SpillStackID: 0, /* SpillStackID */ |
| 5250 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5251 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 5252 | offsetof(RISCVRegisterClassStorage, SuperClasses[641]) - 148 * sizeof(MCRegisterClass), |
| 5253 | .SuperClassesSize: 1 |
| 5254 | }, |
| 5255 | { |
| 5256 | offsetof(RISCVRegisterClassStorage, Regs[2305]) - 149 * sizeof(MCRegisterClass), |
| 5257 | offsetof(RISCVRegisterClassStorage, BitSets[425]) - 149 * sizeof(MCRegisterClass), |
| 5258 | .NameIdx: 441, |
| 5259 | .RegSizeInBits: 512, |
| 5260 | .RegsSize: 1, |
| 5261 | .RegSetBegin: 359, /* MinRegVal */ |
| 5262 | .RegSetSize: 1, /* RegSetSize */ |
| 5263 | .ID: RISCV::VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID, |
| 5264 | .CopyCost: 8, /* CopyCost */ |
| 5265 | .Allocatable: true, /* Allocatable */ |
| 5266 | .BaseClass: false, |
| 5267 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2080]) - 149 * sizeof(MCRegisterClass), |
| 5268 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 149 * sizeof(MCRegisterClass), |
| 5269 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5270 | .AllocationPriority: 8, |
| 5271 | .GlobalPriority: false, |
| 5272 | .TSFlags: 0x07, /* TSFlags */ |
| 5273 | .SpillStackID: 0, /* SpillStackID */ |
| 5274 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5275 | .CoveredBySubRegs: false, /* CoveredBySubRegs */ |
| 5276 | offsetof(RISCVRegisterClassStorage, SuperClasses[642]) - 149 * sizeof(MCRegisterClass), |
| 5277 | .SuperClassesSize: 1 |
| 5278 | }, |
| 5279 | { |
| 5280 | offsetof(RISCVRegisterClassStorage, Regs[2306]) - 150 * sizeof(MCRegisterClass), |
| 5281 | offsetof(RISCVRegisterClassStorage, BitSets[426]) - 150 * sizeof(MCRegisterClass), |
| 5282 | .NameIdx: 386, |
| 5283 | .RegSizeInBits: 512, |
| 5284 | .RegsSize: 1, |
| 5285 | .RegSetBegin: 452, /* MinRegVal */ |
| 5286 | .RegSetSize: 1, /* RegSetSize */ |
| 5287 | .ID: RISCV::VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID, |
| 5288 | .CopyCost: 8, /* CopyCost */ |
| 5289 | .Allocatable: true, /* Allocatable */ |
| 5290 | .BaseClass: false, |
| 5291 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2085]) - 150 * sizeof(MCRegisterClass), |
| 5292 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[1]) - 150 * sizeof(MCRegisterClass), |
| 5293 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5294 | .AllocationPriority: 4, |
| 5295 | .GlobalPriority: false, |
| 5296 | .TSFlags: 0x0d, /* TSFlags */ |
| 5297 | .SpillStackID: 0, /* SpillStackID */ |
| 5298 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5299 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5300 | offsetof(RISCVRegisterClassStorage, SuperClasses[643]) - 150 * sizeof(MCRegisterClass), |
| 5301 | .SuperClassesSize: 1 |
| 5302 | }, |
| 5303 | { |
| 5304 | offsetof(RISCVRegisterClassStorage, Regs[2307]) - 151 * sizeof(MCRegisterClass), |
| 5305 | offsetof(RISCVRegisterClassStorage, BitSets[427]) - 151 * sizeof(MCRegisterClass), |
| 5306 | .NameIdx: 331, |
| 5307 | .RegSizeInBits: 512, |
| 5308 | .RegsSize: 1, |
| 5309 | .RegSetBegin: 538, /* MinRegVal */ |
| 5310 | .RegSetSize: 1, /* RegSetSize */ |
| 5311 | .ID: RISCV::VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0RegClassID, |
| 5312 | .CopyCost: 8, /* CopyCost */ |
| 5313 | .Allocatable: true, /* Allocatable */ |
| 5314 | .BaseClass: false, |
| 5315 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2090]) - 151 * sizeof(MCRegisterClass), |
| 5316 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[100]) - 151 * sizeof(MCRegisterClass), |
| 5317 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5318 | .AllocationPriority: 2, |
| 5319 | .GlobalPriority: false, |
| 5320 | .TSFlags: 0x1b, /* TSFlags */ |
| 5321 | .SpillStackID: 0, /* SpillStackID */ |
| 5322 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5323 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5324 | offsetof(RISCVRegisterClassStorage, SuperClasses[644]) - 151 * sizeof(MCRegisterClass), |
| 5325 | .SuperClassesSize: 1 |
| 5326 | }, |
| 5327 | { |
| 5328 | offsetof(RISCVRegisterClassStorage, Regs[2308]) - 152 * sizeof(MCRegisterClass), |
| 5329 | offsetof(RISCVRegisterClassStorage, BitSets[428]) - 152 * sizeof(MCRegisterClass), |
| 5330 | .NameIdx: 190, |
| 5331 | .RegSizeInBits: 512, |
| 5332 | .RegsSize: 1, |
| 5333 | .RegSetBegin: 644, /* MinRegVal */ |
| 5334 | .RegSetSize: 1, /* RegSetSize */ |
| 5335 | .ID: RISCV::VRN8M1_with_sub_vrm1_0_in_VMV0RegClassID, |
| 5336 | .CopyCost: 8, /* CopyCost */ |
| 5337 | .Allocatable: true, /* Allocatable */ |
| 5338 | .BaseClass: false, |
| 5339 | offsetof(RISCVRegisterClassStorage, SubClassMasks[2100]) - 152 * sizeof(MCRegisterClass), |
| 5340 | offsetof(RISCVRegisterClassStorage, SuperRegIdxSeqs[61]) - 152 * sizeof(MCRegisterClass), |
| 5341 | .LaneMask: LaneBitmask(0x00000000000001FE), |
| 5342 | .AllocationPriority: 0, |
| 5343 | .GlobalPriority: false, |
| 5344 | .TSFlags: 0x39, /* TSFlags */ |
| 5345 | .SpillStackID: 0, /* SpillStackID */ |
| 5346 | .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */ |
| 5347 | .CoveredBySubRegs: true, /* CoveredBySubRegs */ |
| 5348 | offsetof(RISCVRegisterClassStorage, SuperClasses[645]) - 152 * sizeof(MCRegisterClass), |
| 5349 | .SuperClassesSize: 1 |
| 5350 | }, |
| 5351 | }, |
| 5352 | .Regs: { |
| 5353 | /* 0 */ RISCV::M1, RISCV::M2, RISCV::M3, RISCV::M4, RISCV::M5, RISCV::M6, RISCV::M7, RISCV::M0, |
| 5354 | /* 8 */ RISCV::M0, |
| 5355 | /* 9 */ RISCV::F15_H, RISCV::F14_H, RISCV::F13_H, RISCV::F12_H, RISCV::F11_H, RISCV::F10_H, RISCV::F0_H, RISCV::F1_H, RISCV::F2_H, RISCV::F3_H, RISCV::F4_H, RISCV::F5_H, RISCV::F6_H, RISCV::F7_H, RISCV::F16_H, RISCV::F17_H, RISCV::F28_H, RISCV::F29_H, RISCV::F30_H, RISCV::F31_H, RISCV::F8_H, RISCV::F9_H, RISCV::F18_H, RISCV::F19_H, RISCV::F20_H, RISCV::F21_H, RISCV::F22_H, RISCV::F23_H, RISCV::F24_H, RISCV::F25_H, RISCV::F26_H, RISCV::F27_H, |
| 5356 | /* 41 */ RISCV::X10_H, RISCV::X11_H, RISCV::X12_H, RISCV::X13_H, RISCV::X14_H, RISCV::X15_H, RISCV::X16_H, RISCV::X17_H, RISCV::X5_H, RISCV::X6_H, RISCV::X7_H, RISCV::X28_H, RISCV::X29_H, RISCV::X30_H, RISCV::X31_H, RISCV::X8_H, RISCV::X9_H, RISCV::X18_H, RISCV::X19_H, RISCV::X20_H, RISCV::X21_H, RISCV::X22_H, RISCV::X23_H, RISCV::X24_H, RISCV::X25_H, RISCV::X26_H, RISCV::X27_H, RISCV::X0_H, RISCV::X1_H, RISCV::X2_H, RISCV::X3_H, RISCV::X4_H, |
| 5357 | /* 73 */ RISCV::X10_H, RISCV::X11_H, RISCV::X12_H, RISCV::X13_H, RISCV::X14_H, RISCV::X15_H, RISCV::X16_H, RISCV::X17_H, RISCV::X5_H, RISCV::X6_H, RISCV::X7_H, RISCV::X28_H, RISCV::X29_H, RISCV::X30_H, RISCV::X31_H, RISCV::X8_H, RISCV::X9_H, RISCV::X18_H, RISCV::X19_H, RISCV::X20_H, RISCV::X21_H, RISCV::X22_H, RISCV::X23_H, RISCV::X24_H, RISCV::X25_H, RISCV::X26_H, RISCV::X27_H, RISCV::X1_H, RISCV::X2_H, RISCV::X3_H, RISCV::X4_H, |
| 5358 | /* 104 */ RISCV::F15_H, RISCV::F14_H, RISCV::F13_H, RISCV::F12_H, RISCV::F11_H, RISCV::F10_H, RISCV::F8_H, RISCV::F9_H, |
| 5359 | /* 112 */ RISCV::X10_H, RISCV::X11_H, RISCV::X12_H, RISCV::X13_H, RISCV::X14_H, RISCV::X15_H, RISCV::X8_H, RISCV::X9_H, |
| 5360 | /* 120 */ RISCV::X0_H, |
| 5361 | /* 121 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, RISCV::DUMMY_REG_PAIR_WITH_X0, |
| 5362 | /* 154 */ RISCV::F15_F, RISCV::F14_F, RISCV::F13_F, RISCV::F12_F, RISCV::F11_F, RISCV::F10_F, RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F16_F, RISCV::F17_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, |
| 5363 | /* 186 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, |
| 5364 | /* 218 */ RISCV::X10_W, RISCV::X11_W, RISCV::X12_W, RISCV::X13_W, RISCV::X14_W, RISCV::X15_W, RISCV::X16_W, RISCV::X17_W, RISCV::X5_W, RISCV::X6_W, RISCV::X7_W, RISCV::X28_W, RISCV::X29_W, RISCV::X30_W, RISCV::X31_W, RISCV::X8_W, RISCV::X9_W, RISCV::X18_W, RISCV::X19_W, RISCV::X20_W, RISCV::X21_W, RISCV::X22_W, RISCV::X23_W, RISCV::X24_W, RISCV::X25_W, RISCV::X26_W, RISCV::X27_W, RISCV::X0_W, RISCV::X1_W, RISCV::X2_W, RISCV::X3_W, RISCV::X4_W, |
| 5365 | /* 250 */ RISCV::X10_W, RISCV::X11_W, RISCV::X12_W, RISCV::X13_W, RISCV::X14_W, RISCV::X15_W, RISCV::X16_W, RISCV::X17_W, RISCV::X5_W, RISCV::X6_W, RISCV::X7_W, RISCV::X28_W, RISCV::X29_W, RISCV::X30_W, RISCV::X31_W, RISCV::X8_W, RISCV::X9_W, RISCV::X18_W, RISCV::X19_W, RISCV::X20_W, RISCV::X21_W, RISCV::X22_W, RISCV::X23_W, RISCV::X24_W, RISCV::X25_W, RISCV::X26_W, RISCV::X27_W, RISCV::X1_W, RISCV::X2_W, RISCV::X3_W, RISCV::X4_W, |
| 5366 | /* 281 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, |
| 5367 | /* 312 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X3, RISCV::X4, |
| 5368 | /* 343 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, |
| 5369 | /* 374 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X3, RISCV::X4, |
| 5370 | /* 404 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, |
| 5371 | /* 434 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X3, RISCV::X4, |
| 5372 | /* 464 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X3, RISCV::X4, |
| 5373 | /* 493 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, |
| 5374 | /* 519 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, |
| 5375 | /* 544 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, |
| 5376 | /* 569 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, |
| 5377 | /* 593 */ RISCV::T0, RISCV::T1, RISCV::T2, RISCV::T3, RISCV::T4, RISCV::T5, RISCV::T6, RISCV::T7, RISCV::T8, RISCV::T9, RISCV::T10, RISCV::T11, RISCV::T12, RISCV::T13, RISCV::T14, RISCV::T15, |
| 5378 | /* 609 */ RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, |
| 5379 | /* 623 */ RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, |
| 5380 | /* 636 */ RISCV::X6, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, |
| 5381 | /* 649 */ RISCV::X6, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, |
| 5382 | /* 661 */ RISCV::F15_F, RISCV::F14_F, RISCV::F13_F, RISCV::F12_F, RISCV::F11_F, RISCV::F10_F, RISCV::F8_F, RISCV::F9_F, |
| 5383 | /* 669 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X8, RISCV::X9, |
| 5384 | /* 677 */ RISCV::X10_W, RISCV::X11_W, RISCV::X12_W, RISCV::X13_W, RISCV::X14_W, RISCV::X15_W, RISCV::X8_W, RISCV::X9_W, |
| 5385 | /* 685 */ RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, |
| 5386 | /* 693 */ RISCV::T0, RISCV::T2, RISCV::T4, RISCV::T6, RISCV::T8, RISCV::T10, RISCV::T12, RISCV::T14, |
| 5387 | /* 701 */ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, |
| 5388 | /* 707 */ RISCV::T0, RISCV::T4, RISCV::T8, RISCV::T12, |
| 5389 | /* 711 */ RISCV::VTYPE, RISCV::VL, RISCV::VLENB, |
| 5390 | /* 714 */ RISCV::X8, RISCV::X9, |
| 5391 | /* 716 */ RISCV::X1, RISCV::X5, |
| 5392 | /* 718 */ RISCV::X0_W, |
| 5393 | /* 719 */ RISCV::X0, |
| 5394 | /* 720 */ RISCV::X1, |
| 5395 | /* 721 */ RISCV::X5, |
| 5396 | /* 722 */ RISCV::X7, |
| 5397 | /* 723 */ RISCV::X2, |
| 5398 | /* 724 */ RISCV::SF_VCIX_STATE, |
| 5399 | /* 725 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X0_Pair, RISCV::X2_X3, RISCV::X4_X5, |
| 5400 | /* 741 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X2_X3, RISCV::X4_X5, |
| 5401 | /* 756 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X0_Pair, RISCV::X4_X5, |
| 5402 | /* 771 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X4_X5, |
| 5403 | /* 785 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X2_X3, RISCV::X4_X5, |
| 5404 | /* 799 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, |
| 5405 | /* 812 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X4_X5, |
| 5406 | /* 825 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, |
| 5407 | /* 837 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, |
| 5408 | /* 849 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X28_X29, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, |
| 5409 | /* 860 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, |
| 5410 | /* 867 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, |
| 5411 | /* 873 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X28_X29, RISCV::X30_X31, |
| 5412 | /* 879 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X28_X29, |
| 5413 | /* 884 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X8_X9, |
| 5414 | /* 888 */ RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, |
| 5415 | /* 892 */ RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, |
| 5416 | /* 895 */ RISCV::X0_Pair, |
| 5417 | /* 896 */ RISCV::X8_X9, |
| 5418 | /* 897 */ RISCV::X2_X3, |
| 5419 | /* 898 */ RISCV::X4_X5, |
| 5420 | /* 899 */ RISCV::X6_X7, |
| 5421 | /* 900 */ RISCV::F15_D, RISCV::F14_D, RISCV::F13_D, RISCV::F12_D, RISCV::F11_D, RISCV::F10_D, RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F16_D, RISCV::F17_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, |
| 5422 | /* 932 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 5423 | /* 964 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X0_Y, RISCV::X1_Y, RISCV::X2_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 5424 | /* 996 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 5425 | /* 1028 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 5426 | /* 1060 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 5427 | /* 1092 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 5428 | /* 1124 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 5429 | /* 1155 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X1_Y, RISCV::X2_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 5430 | /* 1186 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X0_Y, RISCV::X1_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 5431 | /* 1217 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X0_Y, RISCV::X1_Y, RISCV::X2_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 5432 | /* 1248 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 5433 | /* 1279 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 5434 | /* 1310 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 5435 | /* 1341 */ RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 5436 | /* 1372 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X1_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 5437 | /* 1402 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X1_Y, RISCV::X2_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 5438 | /* 1432 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X0_Y, RISCV::X1_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 5439 | /* 1462 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X1_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 5440 | /* 1491 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, |
| 5441 | /* 1517 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, |
| 5442 | /* 1542 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, |
| 5443 | /* 1567 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, |
| 5444 | /* 1591 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, |
| 5445 | /* 1605 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, |
| 5446 | /* 1618 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, |
| 5447 | /* 1631 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, |
| 5448 | /* 1643 */ RISCV::F15_D, RISCV::F14_D, RISCV::F13_D, RISCV::F12_D, RISCV::F11_D, RISCV::F10_D, RISCV::F8_D, RISCV::F9_D, |
| 5449 | /* 1651 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X8_Y, RISCV::X9_Y, |
| 5450 | /* 1659 */ RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, |
| 5451 | /* 1667 */ RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, |
| 5452 | /* 1673 */ RISCV::X8_Y, RISCV::X9_Y, |
| 5453 | /* 1675 */ RISCV::X5_Y, RISCV::X1_Y, |
| 5454 | /* 1677 */ RISCV::V0, |
| 5455 | /* 1678 */ RISCV::X0_Y, |
| 5456 | /* 1679 */ RISCV::X1_Y, |
| 5457 | /* 1680 */ RISCV::X5_Y, |
| 5458 | /* 1681 */ RISCV::X7_Y, |
| 5459 | /* 1682 */ RISCV::X2_Y, |
| 5460 | /* 1683 */ RISCV::V8_V9, RISCV::V9_V10, RISCV::V10_V11, RISCV::V11_V12, RISCV::V12_V13, RISCV::V13_V14, RISCV::V14_V15, RISCV::V15_V16, RISCV::V16_V17, RISCV::V17_V18, RISCV::V18_V19, RISCV::V19_V20, RISCV::V20_V21, RISCV::V21_V22, RISCV::V22_V23, RISCV::V23_V24, RISCV::V24_V25, RISCV::V25_V26, RISCV::V26_V27, RISCV::V27_V28, RISCV::V28_V29, RISCV::V29_V30, RISCV::V30_V31, RISCV::V1_V2, RISCV::V2_V3, RISCV::V3_V4, RISCV::V4_V5, RISCV::V5_V6, RISCV::V6_V7, RISCV::V7_V8, RISCV::V0_V1, |
| 5461 | /* 1714 */ RISCV::V8_V9, RISCV::V9_V10, RISCV::V10_V11, RISCV::V11_V12, RISCV::V12_V13, RISCV::V13_V14, RISCV::V14_V15, RISCV::V15_V16, RISCV::V16_V17, RISCV::V17_V18, RISCV::V18_V19, RISCV::V19_V20, RISCV::V20_V21, RISCV::V21_V22, RISCV::V22_V23, RISCV::V23_V24, RISCV::V24_V25, RISCV::V25_V26, RISCV::V26_V27, RISCV::V27_V28, RISCV::V28_V29, RISCV::V29_V30, RISCV::V30_V31, RISCV::V1_V2, RISCV::V2_V3, RISCV::V3_V4, RISCV::V4_V5, RISCV::V5_V6, RISCV::V6_V7, RISCV::V7_V8, |
| 5462 | /* 1744 */ RISCV::V8M2, RISCV::V10M2, RISCV::V12M2, RISCV::V14M2, RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2, RISCV::V24M2, RISCV::V26M2, RISCV::V28M2, RISCV::V30M2, RISCV::V6M2, RISCV::V4M2, RISCV::V2M2, RISCV::V0M2, |
| 5463 | /* 1760 */ RISCV::V8M2, RISCV::V10M2, RISCV::V12M2, RISCV::V14M2, RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2, RISCV::V24M2, RISCV::V26M2, RISCV::V28M2, RISCV::V30M2, RISCV::V6M2, RISCV::V4M2, RISCV::V2M2, |
| 5464 | /* 1775 */ RISCV::V0M2, |
| 5465 | /* 1776 */ RISCV::V0_V1, |
| 5466 | /* 1777 */ RISCV::F15_Q, RISCV::F14_Q, RISCV::F13_Q, RISCV::F12_Q, RISCV::F11_Q, RISCV::F10_Q, RISCV::F0_Q, RISCV::F1_Q, RISCV::F2_Q, RISCV::F3_Q, RISCV::F4_Q, RISCV::F5_Q, RISCV::F6_Q, RISCV::F7_Q, RISCV::F16_Q, RISCV::F17_Q, RISCV::F28_Q, RISCV::F29_Q, RISCV::F30_Q, RISCV::F31_Q, RISCV::F8_Q, RISCV::F9_Q, RISCV::F18_Q, RISCV::F19_Q, RISCV::F20_Q, RISCV::F21_Q, RISCV::F22_Q, RISCV::F23_Q, RISCV::F24_Q, RISCV::F25_Q, RISCV::F26_Q, RISCV::F27_Q, |
| 5467 | /* 1809 */ RISCV::F15_Q, RISCV::F14_Q, RISCV::F13_Q, RISCV::F12_Q, RISCV::F11_Q, RISCV::F10_Q, RISCV::F8_Q, RISCV::F9_Q, |
| 5468 | /* 1817 */ RISCV::V8_V9_V10, RISCV::V9_V10_V11, RISCV::V10_V11_V12, RISCV::V11_V12_V13, RISCV::V12_V13_V14, RISCV::V13_V14_V15, RISCV::V14_V15_V16, RISCV::V15_V16_V17, RISCV::V16_V17_V18, RISCV::V17_V18_V19, RISCV::V18_V19_V20, RISCV::V19_V20_V21, RISCV::V20_V21_V22, RISCV::V21_V22_V23, RISCV::V22_V23_V24, RISCV::V23_V24_V25, RISCV::V24_V25_V26, RISCV::V25_V26_V27, RISCV::V26_V27_V28, RISCV::V27_V28_V29, RISCV::V28_V29_V30, RISCV::V29_V30_V31, RISCV::V1_V2_V3, RISCV::V2_V3_V4, RISCV::V3_V4_V5, RISCV::V4_V5_V6, RISCV::V5_V6_V7, RISCV::V6_V7_V8, RISCV::V7_V8_V9, RISCV::V0_V1_V2, |
| 5469 | /* 1847 */ RISCV::V8_V9_V10, RISCV::V9_V10_V11, RISCV::V10_V11_V12, RISCV::V11_V12_V13, RISCV::V12_V13_V14, RISCV::V13_V14_V15, RISCV::V14_V15_V16, RISCV::V15_V16_V17, RISCV::V16_V17_V18, RISCV::V17_V18_V19, RISCV::V18_V19_V20, RISCV::V19_V20_V21, RISCV::V20_V21_V22, RISCV::V21_V22_V23, RISCV::V22_V23_V24, RISCV::V23_V24_V25, RISCV::V24_V25_V26, RISCV::V25_V26_V27, RISCV::V26_V27_V28, RISCV::V27_V28_V29, RISCV::V28_V29_V30, RISCV::V29_V30_V31, RISCV::V1_V2_V3, RISCV::V2_V3_V4, RISCV::V3_V4_V5, RISCV::V4_V5_V6, RISCV::V5_V6_V7, RISCV::V6_V7_V8, RISCV::V7_V8_V9, |
| 5470 | /* 1876 */ RISCV::V0_V1_V2, |
| 5471 | /* 1877 */ RISCV::V8_V9_V10_V11, RISCV::V9_V10_V11_V12, RISCV::V10_V11_V12_V13, RISCV::V11_V12_V13_V14, RISCV::V12_V13_V14_V15, RISCV::V13_V14_V15_V16, RISCV::V14_V15_V16_V17, RISCV::V15_V16_V17_V18, RISCV::V16_V17_V18_V19, RISCV::V17_V18_V19_V20, RISCV::V18_V19_V20_V21, RISCV::V19_V20_V21_V22, RISCV::V20_V21_V22_V23, RISCV::V21_V22_V23_V24, RISCV::V22_V23_V24_V25, RISCV::V23_V24_V25_V26, RISCV::V24_V25_V26_V27, RISCV::V25_V26_V27_V28, RISCV::V26_V27_V28_V29, RISCV::V27_V28_V29_V30, RISCV::V28_V29_V30_V31, RISCV::V1_V2_V3_V4, RISCV::V2_V3_V4_V5, RISCV::V3_V4_V5_V6, RISCV::V4_V5_V6_V7, RISCV::V5_V6_V7_V8, RISCV::V6_V7_V8_V9, RISCV::V7_V8_V9_V10, RISCV::V0_V1_V2_V3, |
| 5472 | /* 1906 */ RISCV::V8_V9_V10_V11, RISCV::V9_V10_V11_V12, RISCV::V10_V11_V12_V13, RISCV::V11_V12_V13_V14, RISCV::V12_V13_V14_V15, RISCV::V13_V14_V15_V16, RISCV::V14_V15_V16_V17, RISCV::V15_V16_V17_V18, RISCV::V16_V17_V18_V19, RISCV::V17_V18_V19_V20, RISCV::V18_V19_V20_V21, RISCV::V19_V20_V21_V22, RISCV::V20_V21_V22_V23, RISCV::V21_V22_V23_V24, RISCV::V22_V23_V24_V25, RISCV::V23_V24_V25_V26, RISCV::V24_V25_V26_V27, RISCV::V25_V26_V27_V28, RISCV::V26_V27_V28_V29, RISCV::V27_V28_V29_V30, RISCV::V28_V29_V30_V31, RISCV::V1_V2_V3_V4, RISCV::V2_V3_V4_V5, RISCV::V3_V4_V5_V6, RISCV::V4_V5_V6_V7, RISCV::V5_V6_V7_V8, RISCV::V6_V7_V8_V9, RISCV::V7_V8_V9_V10, |
| 5473 | /* 1934 */ RISCV::V8M2_V10M2, RISCV::V10M2_V12M2, RISCV::V12M2_V14M2, RISCV::V14M2_V16M2, RISCV::V16M2_V18M2, RISCV::V18M2_V20M2, RISCV::V20M2_V22M2, RISCV::V22M2_V24M2, RISCV::V24M2_V26M2, RISCV::V26M2_V28M2, RISCV::V28M2_V30M2, RISCV::V2M2_V4M2, RISCV::V4M2_V6M2, RISCV::V6M2_V8M2, RISCV::V0M2_V2M2, |
| 5474 | /* 1949 */ RISCV::V8M2_V10M2, RISCV::V10M2_V12M2, RISCV::V12M2_V14M2, RISCV::V14M2_V16M2, RISCV::V16M2_V18M2, RISCV::V18M2_V20M2, RISCV::V20M2_V22M2, RISCV::V22M2_V24M2, RISCV::V24M2_V26M2, RISCV::V26M2_V28M2, RISCV::V28M2_V30M2, RISCV::V2M2_V4M2, RISCV::V4M2_V6M2, RISCV::V6M2_V8M2, |
| 5475 | /* 1963 */ RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4, RISCV::V24M4, RISCV::V28M4, RISCV::V4M4, RISCV::V0M4, |
| 5476 | /* 1971 */ RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4, RISCV::V24M4, RISCV::V28M4, RISCV::V4M4, |
| 5477 | /* 1978 */ RISCV::V0M4, |
| 5478 | /* 1979 */ RISCV::V0M2_V2M2, |
| 5479 | /* 1980 */ RISCV::V0_V1_V2_V3, |
| 5480 | /* 1981 */ RISCV::F15_Q2, RISCV::F14_Q2, RISCV::F13_Q2, RISCV::F12_Q2, RISCV::F11_Q2, RISCV::F10_Q2, RISCV::F0_Q2, RISCV::F1_Q2, RISCV::F2_Q2, RISCV::F3_Q2, RISCV::F4_Q2, RISCV::F5_Q2, RISCV::F6_Q2, RISCV::F7_Q2, RISCV::F16_Q2, RISCV::F17_Q2, RISCV::F28_Q2, RISCV::F29_Q2, RISCV::F30_Q2, RISCV::F31_Q2, RISCV::F8_Q2, RISCV::F9_Q2, RISCV::F18_Q2, RISCV::F19_Q2, RISCV::F20_Q2, RISCV::F21_Q2, RISCV::F22_Q2, RISCV::F23_Q2, RISCV::F24_Q2, RISCV::F25_Q2, RISCV::F26_Q2, RISCV::F27_Q2, |
| 5481 | /* 2013 */ RISCV::F15_Q2, RISCV::F14_Q2, RISCV::F13_Q2, RISCV::F12_Q2, RISCV::F11_Q2, RISCV::F10_Q2, RISCV::F8_Q2, RISCV::F9_Q2, |
| 5482 | /* 2021 */ RISCV::V8_V9_V10_V11_V12, RISCV::V9_V10_V11_V12_V13, RISCV::V10_V11_V12_V13_V14, RISCV::V11_V12_V13_V14_V15, RISCV::V12_V13_V14_V15_V16, RISCV::V13_V14_V15_V16_V17, RISCV::V14_V15_V16_V17_V18, RISCV::V15_V16_V17_V18_V19, RISCV::V16_V17_V18_V19_V20, RISCV::V17_V18_V19_V20_V21, RISCV::V18_V19_V20_V21_V22, RISCV::V19_V20_V21_V22_V23, RISCV::V20_V21_V22_V23_V24, RISCV::V21_V22_V23_V24_V25, RISCV::V22_V23_V24_V25_V26, RISCV::V23_V24_V25_V26_V27, RISCV::V24_V25_V26_V27_V28, RISCV::V25_V26_V27_V28_V29, RISCV::V26_V27_V28_V29_V30, RISCV::V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5, RISCV::V2_V3_V4_V5_V6, RISCV::V3_V4_V5_V6_V7, RISCV::V4_V5_V6_V7_V8, RISCV::V5_V6_V7_V8_V9, RISCV::V6_V7_V8_V9_V10, RISCV::V7_V8_V9_V10_V11, RISCV::V0_V1_V2_V3_V4, |
| 5483 | /* 2049 */ RISCV::V8_V9_V10_V11_V12, RISCV::V9_V10_V11_V12_V13, RISCV::V10_V11_V12_V13_V14, RISCV::V11_V12_V13_V14_V15, RISCV::V12_V13_V14_V15_V16, RISCV::V13_V14_V15_V16_V17, RISCV::V14_V15_V16_V17_V18, RISCV::V15_V16_V17_V18_V19, RISCV::V16_V17_V18_V19_V20, RISCV::V17_V18_V19_V20_V21, RISCV::V18_V19_V20_V21_V22, RISCV::V19_V20_V21_V22_V23, RISCV::V20_V21_V22_V23_V24, RISCV::V21_V22_V23_V24_V25, RISCV::V22_V23_V24_V25_V26, RISCV::V23_V24_V25_V26_V27, RISCV::V24_V25_V26_V27_V28, RISCV::V25_V26_V27_V28_V29, RISCV::V26_V27_V28_V29_V30, RISCV::V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5, RISCV::V2_V3_V4_V5_V6, RISCV::V3_V4_V5_V6_V7, RISCV::V4_V5_V6_V7_V8, RISCV::V5_V6_V7_V8_V9, RISCV::V6_V7_V8_V9_V10, RISCV::V7_V8_V9_V10_V11, |
| 5484 | /* 2076 */ RISCV::V0_V1_V2_V3_V4, |
| 5485 | /* 2077 */ RISCV::V8_V9_V10_V11_V12_V13, RISCV::V9_V10_V11_V12_V13_V14, RISCV::V10_V11_V12_V13_V14_V15, RISCV::V11_V12_V13_V14_V15_V16, RISCV::V12_V13_V14_V15_V16_V17, RISCV::V13_V14_V15_V16_V17_V18, RISCV::V14_V15_V16_V17_V18_V19, RISCV::V15_V16_V17_V18_V19_V20, RISCV::V16_V17_V18_V19_V20_V21, RISCV::V17_V18_V19_V20_V21_V22, RISCV::V18_V19_V20_V21_V22_V23, RISCV::V19_V20_V21_V22_V23_V24, RISCV::V20_V21_V22_V23_V24_V25, RISCV::V21_V22_V23_V24_V25_V26, RISCV::V22_V23_V24_V25_V26_V27, RISCV::V23_V24_V25_V26_V27_V28, RISCV::V24_V25_V26_V27_V28_V29, RISCV::V25_V26_V27_V28_V29_V30, RISCV::V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6, RISCV::V2_V3_V4_V5_V6_V7, RISCV::V3_V4_V5_V6_V7_V8, RISCV::V4_V5_V6_V7_V8_V9, RISCV::V5_V6_V7_V8_V9_V10, RISCV::V6_V7_V8_V9_V10_V11, RISCV::V7_V8_V9_V10_V11_V12, RISCV::V0_V1_V2_V3_V4_V5, |
| 5486 | /* 2104 */ RISCV::V8_V9_V10_V11_V12_V13, RISCV::V9_V10_V11_V12_V13_V14, RISCV::V10_V11_V12_V13_V14_V15, RISCV::V11_V12_V13_V14_V15_V16, RISCV::V12_V13_V14_V15_V16_V17, RISCV::V13_V14_V15_V16_V17_V18, RISCV::V14_V15_V16_V17_V18_V19, RISCV::V15_V16_V17_V18_V19_V20, RISCV::V16_V17_V18_V19_V20_V21, RISCV::V17_V18_V19_V20_V21_V22, RISCV::V18_V19_V20_V21_V22_V23, RISCV::V19_V20_V21_V22_V23_V24, RISCV::V20_V21_V22_V23_V24_V25, RISCV::V21_V22_V23_V24_V25_V26, RISCV::V22_V23_V24_V25_V26_V27, RISCV::V23_V24_V25_V26_V27_V28, RISCV::V24_V25_V26_V27_V28_V29, RISCV::V25_V26_V27_V28_V29_V30, RISCV::V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6, RISCV::V2_V3_V4_V5_V6_V7, RISCV::V3_V4_V5_V6_V7_V8, RISCV::V4_V5_V6_V7_V8_V9, RISCV::V5_V6_V7_V8_V9_V10, RISCV::V6_V7_V8_V9_V10_V11, RISCV::V7_V8_V9_V10_V11_V12, |
| 5487 | /* 2130 */ RISCV::V8M2_V10M2_V12M2, RISCV::V10M2_V12M2_V14M2, RISCV::V12M2_V14M2_V16M2, RISCV::V14M2_V16M2_V18M2, RISCV::V16M2_V18M2_V20M2, RISCV::V18M2_V20M2_V22M2, RISCV::V20M2_V22M2_V24M2, RISCV::V22M2_V24M2_V26M2, RISCV::V24M2_V26M2_V28M2, RISCV::V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2, RISCV::V4M2_V6M2_V8M2, RISCV::V6M2_V8M2_V10M2, RISCV::V0M2_V2M2_V4M2, |
| 5488 | /* 2144 */ RISCV::V8M2_V10M2_V12M2, RISCV::V10M2_V12M2_V14M2, RISCV::V12M2_V14M2_V16M2, RISCV::V14M2_V16M2_V18M2, RISCV::V16M2_V18M2_V20M2, RISCV::V18M2_V20M2_V22M2, RISCV::V20M2_V22M2_V24M2, RISCV::V22M2_V24M2_V26M2, RISCV::V24M2_V26M2_V28M2, RISCV::V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2, RISCV::V4M2_V6M2_V8M2, RISCV::V6M2_V8M2_V10M2, |
| 5489 | /* 2157 */ RISCV::V0M2_V2M2_V4M2, |
| 5490 | /* 2158 */ RISCV::V0_V1_V2_V3_V4_V5, |
| 5491 | /* 2159 */ RISCV::V8_V9_V10_V11_V12_V13_V14, RISCV::V9_V10_V11_V12_V13_V14_V15, RISCV::V10_V11_V12_V13_V14_V15_V16, RISCV::V11_V12_V13_V14_V15_V16_V17, RISCV::V12_V13_V14_V15_V16_V17_V18, RISCV::V13_V14_V15_V16_V17_V18_V19, RISCV::V14_V15_V16_V17_V18_V19_V20, RISCV::V15_V16_V17_V18_V19_V20_V21, RISCV::V16_V17_V18_V19_V20_V21_V22, RISCV::V17_V18_V19_V20_V21_V22_V23, RISCV::V18_V19_V20_V21_V22_V23_V24, RISCV::V19_V20_V21_V22_V23_V24_V25, RISCV::V20_V21_V22_V23_V24_V25_V26, RISCV::V21_V22_V23_V24_V25_V26_V27, RISCV::V22_V23_V24_V25_V26_V27_V28, RISCV::V23_V24_V25_V26_V27_V28_V29, RISCV::V24_V25_V26_V27_V28_V29_V30, RISCV::V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7, RISCV::V2_V3_V4_V5_V6_V7_V8, RISCV::V3_V4_V5_V6_V7_V8_V9, RISCV::V4_V5_V6_V7_V8_V9_V10, RISCV::V5_V6_V7_V8_V9_V10_V11, RISCV::V6_V7_V8_V9_V10_V11_V12, RISCV::V7_V8_V9_V10_V11_V12_V13, RISCV::V0_V1_V2_V3_V4_V5_V6, |
| 5492 | /* 2185 */ RISCV::V8_V9_V10_V11_V12_V13_V14, RISCV::V9_V10_V11_V12_V13_V14_V15, RISCV::V10_V11_V12_V13_V14_V15_V16, RISCV::V11_V12_V13_V14_V15_V16_V17, RISCV::V12_V13_V14_V15_V16_V17_V18, RISCV::V13_V14_V15_V16_V17_V18_V19, RISCV::V14_V15_V16_V17_V18_V19_V20, RISCV::V15_V16_V17_V18_V19_V20_V21, RISCV::V16_V17_V18_V19_V20_V21_V22, RISCV::V17_V18_V19_V20_V21_V22_V23, RISCV::V18_V19_V20_V21_V22_V23_V24, RISCV::V19_V20_V21_V22_V23_V24_V25, RISCV::V20_V21_V22_V23_V24_V25_V26, RISCV::V21_V22_V23_V24_V25_V26_V27, RISCV::V22_V23_V24_V25_V26_V27_V28, RISCV::V23_V24_V25_V26_V27_V28_V29, RISCV::V24_V25_V26_V27_V28_V29_V30, RISCV::V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7, RISCV::V2_V3_V4_V5_V6_V7_V8, RISCV::V3_V4_V5_V6_V7_V8_V9, RISCV::V4_V5_V6_V7_V8_V9_V10, RISCV::V5_V6_V7_V8_V9_V10_V11, RISCV::V6_V7_V8_V9_V10_V11_V12, RISCV::V7_V8_V9_V10_V11_V12_V13, |
| 5493 | /* 2210 */ RISCV::V0_V1_V2_V3_V4_V5_V6, |
| 5494 | /* 2211 */ RISCV::V8_V9_V10_V11_V12_V13_V14_V15, RISCV::V9_V10_V11_V12_V13_V14_V15_V16, RISCV::V10_V11_V12_V13_V14_V15_V16_V17, RISCV::V11_V12_V13_V14_V15_V16_V17_V18, RISCV::V12_V13_V14_V15_V16_V17_V18_V19, RISCV::V13_V14_V15_V16_V17_V18_V19_V20, RISCV::V14_V15_V16_V17_V18_V19_V20_V21, RISCV::V15_V16_V17_V18_V19_V20_V21_V22, RISCV::V16_V17_V18_V19_V20_V21_V22_V23, RISCV::V17_V18_V19_V20_V21_V22_V23_V24, RISCV::V18_V19_V20_V21_V22_V23_V24_V25, RISCV::V19_V20_V21_V22_V23_V24_V25_V26, RISCV::V20_V21_V22_V23_V24_V25_V26_V27, RISCV::V21_V22_V23_V24_V25_V26_V27_V28, RISCV::V22_V23_V24_V25_V26_V27_V28_V29, RISCV::V23_V24_V25_V26_V27_V28_V29_V30, RISCV::V24_V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7_V8, RISCV::V2_V3_V4_V5_V6_V7_V8_V9, RISCV::V3_V4_V5_V6_V7_V8_V9_V10, RISCV::V4_V5_V6_V7_V8_V9_V10_V11, RISCV::V5_V6_V7_V8_V9_V10_V11_V12, RISCV::V6_V7_V8_V9_V10_V11_V12_V13, RISCV::V7_V8_V9_V10_V11_V12_V13_V14, RISCV::V0_V1_V2_V3_V4_V5_V6_V7, |
| 5495 | /* 2236 */ RISCV::V8_V9_V10_V11_V12_V13_V14_V15, RISCV::V9_V10_V11_V12_V13_V14_V15_V16, RISCV::V10_V11_V12_V13_V14_V15_V16_V17, RISCV::V11_V12_V13_V14_V15_V16_V17_V18, RISCV::V12_V13_V14_V15_V16_V17_V18_V19, RISCV::V13_V14_V15_V16_V17_V18_V19_V20, RISCV::V14_V15_V16_V17_V18_V19_V20_V21, RISCV::V15_V16_V17_V18_V19_V20_V21_V22, RISCV::V16_V17_V18_V19_V20_V21_V22_V23, RISCV::V17_V18_V19_V20_V21_V22_V23_V24, RISCV::V18_V19_V20_V21_V22_V23_V24_V25, RISCV::V19_V20_V21_V22_V23_V24_V25_V26, RISCV::V20_V21_V22_V23_V24_V25_V26_V27, RISCV::V21_V22_V23_V24_V25_V26_V27_V28, RISCV::V22_V23_V24_V25_V26_V27_V28_V29, RISCV::V23_V24_V25_V26_V27_V28_V29_V30, RISCV::V24_V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7_V8, RISCV::V2_V3_V4_V5_V6_V7_V8_V9, RISCV::V3_V4_V5_V6_V7_V8_V9_V10, RISCV::V4_V5_V6_V7_V8_V9_V10_V11, RISCV::V5_V6_V7_V8_V9_V10_V11_V12, RISCV::V6_V7_V8_V9_V10_V11_V12_V13, RISCV::V7_V8_V9_V10_V11_V12_V13_V14, |
| 5496 | /* 2260 */ RISCV::V8M2_V10M2_V12M2_V14M2, RISCV::V10M2_V12M2_V14M2_V16M2, RISCV::V12M2_V14M2_V16M2_V18M2, RISCV::V14M2_V16M2_V18M2_V20M2, RISCV::V16M2_V18M2_V20M2_V22M2, RISCV::V18M2_V20M2_V22M2_V24M2, RISCV::V20M2_V22M2_V24M2_V26M2, RISCV::V22M2_V24M2_V26M2_V28M2, RISCV::V24M2_V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2_V8M2, RISCV::V4M2_V6M2_V8M2_V10M2, RISCV::V6M2_V8M2_V10M2_V12M2, RISCV::V0M2_V2M2_V4M2_V6M2, |
| 5497 | /* 2273 */ RISCV::V8M2_V10M2_V12M2_V14M2, RISCV::V10M2_V12M2_V14M2_V16M2, RISCV::V12M2_V14M2_V16M2_V18M2, RISCV::V14M2_V16M2_V18M2_V20M2, RISCV::V16M2_V18M2_V20M2_V22M2, RISCV::V18M2_V20M2_V22M2_V24M2, RISCV::V20M2_V22M2_V24M2_V26M2, RISCV::V22M2_V24M2_V26M2_V28M2, RISCV::V24M2_V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2_V8M2, RISCV::V4M2_V6M2_V8M2_V10M2, RISCV::V6M2_V8M2_V10M2_V12M2, |
| 5498 | /* 2285 */ RISCV::V8M4_V12M4, RISCV::V12M4_V16M4, RISCV::V16M4_V20M4, RISCV::V20M4_V24M4, RISCV::V24M4_V28M4, RISCV::V4M4_V8M4, RISCV::V0M4_V4M4, |
| 5499 | /* 2292 */ RISCV::V8M4_V12M4, RISCV::V12M4_V16M4, RISCV::V16M4_V20M4, RISCV::V20M4_V24M4, RISCV::V24M4_V28M4, RISCV::V4M4_V8M4, |
| 5500 | /* 2298 */ RISCV::V8M8, RISCV::V16M8, RISCV::V24M8, RISCV::V0M8, |
| 5501 | /* 2302 */ RISCV::V8M8, RISCV::V16M8, RISCV::V24M8, |
| 5502 | /* 2305 */ RISCV::V0M8, |
| 5503 | /* 2306 */ RISCV::V0M4_V4M4, |
| 5504 | /* 2307 */ RISCV::V0M2_V2M2_V4M2_V6M2, |
| 5505 | /* 2308 */ RISCV::V0_V1_V2_V3_V4_V5_V6_V7, |
| 5506 | }, |
| 5507 | .BitSets: { |
| 5508 | /* 0 */ 0xff, |
| 5509 | /* 1 */ 0x01, |
| 5510 | /* 2 */ 0xff, 0xff, 0xff, 0xff, |
| 5511 | /* 6 */ 0xff, 0xff, 0xff, 0xff, |
| 5512 | /* 10 */ 0xff, 0xff, 0xff, 0x7f, |
| 5513 | /* 14 */ 0xff, |
| 5514 | /* 15 */ 0xff, |
| 5515 | /* 16 */ 0x01, |
| 5516 | /* 17 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, |
| 5517 | /* 29 */ 0xff, 0xff, 0xff, 0xff, |
| 5518 | /* 33 */ 0xff, 0xff, 0xff, 0xff, |
| 5519 | /* 37 */ 0xff, 0xff, 0xff, 0xff, |
| 5520 | /* 41 */ 0xff, 0xff, 0xff, 0x7f, |
| 5521 | /* 45 */ 0xff, 0xff, 0xff, 0x7f, |
| 5522 | /* 49 */ 0xfb, 0xff, 0xff, 0xff, |
| 5523 | /* 53 */ 0xff, 0xff, 0xff, 0x7f, |
| 5524 | /* 57 */ 0xfd, 0xff, 0xff, 0x7f, |
| 5525 | /* 61 */ 0xff, 0xff, 0xff, 0x3f, |
| 5526 | /* 65 */ 0xfb, 0xff, 0xff, 0x7f, |
| 5527 | /* 69 */ 0xfd, 0xff, 0xff, 0x3f, |
| 5528 | /* 73 */ 0xff, 0xff, 0xff, 0x03, |
| 5529 | /* 77 */ 0xfd, 0xff, 0xff, 0x03, |
| 5530 | /* 81 */ 0xff, 0xff, 0xff, 0x01, |
| 5531 | /* 85 */ 0xfd, 0xff, 0xff, 0x01, |
| 5532 | /* 89 */ 0xff, 0xff, |
| 5533 | /* 91 */ 0xf3, 0x0f, 0xc0, 0x03, |
| 5534 | /* 95 */ 0xf3, 0x0f, 0xc0, 0x01, |
| 5535 | /* 99 */ 0xf1, 0x0f, 0xc0, 0x03, |
| 5536 | /* 103 */ 0xf1, 0x0f, 0xc0, 0x01, |
| 5537 | /* 107 */ 0xff, |
| 5538 | /* 108 */ 0xff, |
| 5539 | /* 109 */ 0xff, |
| 5540 | /* 110 */ 0x03, 0xfc, |
| 5541 | /* 112 */ 0x55, 0x55, |
| 5542 | /* 114 */ 0x3f, |
| 5543 | /* 115 */ 0x11, 0x11, |
| 5544 | /* 117 */ 0x07, |
| 5545 | /* 118 */ 0x03, |
| 5546 | /* 119 */ 0x11, |
| 5547 | /* 120 */ 0x01, |
| 5548 | /* 121 */ 0x01, |
| 5549 | /* 122 */ 0x01, |
| 5550 | /* 123 */ 0x01, |
| 5551 | /* 124 */ 0x01, |
| 5552 | /* 125 */ 0x01, |
| 5553 | /* 126 */ 0x01, |
| 5554 | /* 127 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, |
| 5555 | /* 145 */ 0xff, 0x7f, |
| 5556 | /* 147 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, |
| 5557 | /* 165 */ 0xff, 0x3f, |
| 5558 | /* 167 */ 0xff, 0x3f, |
| 5559 | /* 169 */ 0xff, 0x1f, |
| 5560 | /* 171 */ 0xff, 0x1f, |
| 5561 | /* 173 */ 0xff, 0x0f, |
| 5562 | /* 175 */ 0xff, 0x0f, |
| 5563 | /* 177 */ 0xff, 0x07, |
| 5564 | /* 179 */ 0x3d, 0x18, |
| 5565 | /* 181 */ 0x3d, 0x08, |
| 5566 | /* 183 */ 0x0f, 0x06, |
| 5567 | /* 185 */ 0x0f, 0x02, |
| 5568 | /* 187 */ 0x0f, |
| 5569 | /* 188 */ 0xe1, |
| 5570 | /* 189 */ 0x07, |
| 5571 | /* 190 */ 0x01, |
| 5572 | /* 191 */ 0x01, |
| 5573 | /* 192 */ 0x01, |
| 5574 | /* 193 */ 0x01, |
| 5575 | /* 194 */ 0x01, |
| 5576 | /* 195 */ 0xff, 0xff, 0xff, 0xff, |
| 5577 | /* 199 */ 0xff, 0xff, 0xff, 0xff, |
| 5578 | /* 203 */ 0xff, 0xff, 0xff, 0xff, |
| 5579 | /* 207 */ 0xff, 0xff, 0xff, 0xff, |
| 5580 | /* 211 */ 0xff, 0xff, 0xff, 0xff, |
| 5581 | /* 215 */ 0xff, 0xff, 0xff, 0xff, |
| 5582 | /* 219 */ 0xff, 0xff, 0xff, 0xff, |
| 5583 | /* 223 */ 0xff, 0xff, 0xff, 0x7f, |
| 5584 | /* 227 */ 0xff, 0xff, 0xff, 0x7f, |
| 5585 | /* 231 */ 0xfb, 0xff, 0xff, 0xff, |
| 5586 | /* 235 */ 0xff, 0xff, 0xff, 0x7f, |
| 5587 | /* 239 */ 0xff, 0xff, 0xff, 0x7f, |
| 5588 | /* 243 */ 0xff, 0xff, 0xff, 0x7f, |
| 5589 | /* 247 */ 0xff, 0xff, 0xff, 0x7f, |
| 5590 | /* 251 */ 0xff, 0xff, 0xff, 0x7f, |
| 5591 | /* 255 */ 0xfd, 0xff, 0xff, 0x7f, |
| 5592 | /* 259 */ 0xff, 0xff, 0xff, 0x3f, |
| 5593 | /* 263 */ 0xfb, 0xff, 0xff, 0x7f, |
| 5594 | /* 267 */ 0xfd, 0xff, 0xff, 0x3f, |
| 5595 | /* 271 */ 0xff, 0xff, 0xff, 0x03, |
| 5596 | /* 275 */ 0xfd, 0xff, 0xff, 0x03, |
| 5597 | /* 279 */ 0xff, 0xff, 0xff, 0x01, |
| 5598 | /* 283 */ 0xfd, 0xff, 0xff, 0x01, |
| 5599 | /* 287 */ 0xf3, 0x0f, 0xc0, 0x03, |
| 5600 | /* 291 */ 0xf3, 0x0f, 0xc0, 0x01, |
| 5601 | /* 295 */ 0xf1, 0x0f, 0xc0, 0x03, |
| 5602 | /* 299 */ 0xf1, 0x0f, 0xc0, 0x01, |
| 5603 | /* 303 */ 0xff, |
| 5604 | /* 304 */ 0xff, |
| 5605 | /* 305 */ 0x03, 0xfc, |
| 5606 | /* 307 */ 0x3f, |
| 5607 | /* 308 */ 0x03, |
| 5608 | /* 309 */ 0x11, |
| 5609 | /* 310 */ 0x01, |
| 5610 | /* 311 */ 0x01, |
| 5611 | /* 312 */ 0x01, |
| 5612 | /* 313 */ 0x01, |
| 5613 | /* 314 */ 0x01, |
| 5614 | /* 315 */ 0x01, |
| 5615 | /* 316 */ 0xff, 0xff, 0xff, 0x7f, |
| 5616 | /* 320 */ 0xff, 0xff, 0xff, 0x3f, |
| 5617 | /* 324 */ 0xd9, 0x6c, 0x36, 0x0b, |
| 5618 | /* 328 */ 0x9b, 0xcd, 0x66, 0x01, |
| 5619 | /* 332 */ 0x01, |
| 5620 | /* 333 */ 0x01, |
| 5621 | /* 334 */ 0xff, 0xff, 0xff, 0xff, |
| 5622 | /* 338 */ 0xff, |
| 5623 | /* 339 */ 0xff, 0xff, 0xff, 0x3f, |
| 5624 | /* 343 */ 0xff, 0xff, 0xff, 0x1f, |
| 5625 | /* 347 */ 0x01, |
| 5626 | /* 348 */ 0xff, 0xff, 0xff, 0x1f, |
| 5627 | /* 352 */ 0xff, 0xff, 0xff, 0x0f, |
| 5628 | /* 356 */ 0xff, 0x7f, |
| 5629 | /* 358 */ 0xff, 0x3f, |
| 5630 | /* 360 */ 0x91, 0x48, 0x24, 0x02, |
| 5631 | /* 364 */ 0x89, 0x44, 0x22, |
| 5632 | /* 367 */ 0x01, |
| 5633 | /* 368 */ 0x01, |
| 5634 | /* 369 */ 0x01, |
| 5635 | /* 370 */ 0xff, 0xff, 0xff, 0xff, |
| 5636 | /* 374 */ 0xff, |
| 5637 | /* 375 */ 0xff, 0xff, 0xff, 0x0f, |
| 5638 | /* 379 */ 0xff, 0xff, 0xff, 0x07, |
| 5639 | /* 383 */ 0x01, |
| 5640 | /* 384 */ 0xff, 0xff, 0xff, 0x07, |
| 5641 | /* 388 */ 0xff, 0xff, 0xff, 0x03, |
| 5642 | /* 392 */ 0xff, 0x3f, |
| 5643 | /* 394 */ 0xff, 0x1f, |
| 5644 | /* 396 */ 0x01, |
| 5645 | /* 397 */ 0x01, |
| 5646 | /* 398 */ 0xff, 0xff, 0xff, 0x03, |
| 5647 | /* 402 */ 0xff, 0xff, 0xff, 0x01, |
| 5648 | /* 406 */ 0x01, |
| 5649 | /* 407 */ 0xff, 0xff, 0xff, 0x01, |
| 5650 | /* 411 */ 0xff, 0xff, 0xff, |
| 5651 | /* 414 */ 0xff, 0x1f, |
| 5652 | /* 416 */ 0xff, 0x0f, |
| 5653 | /* 418 */ 0x7f, |
| 5654 | /* 419 */ 0x3f, |
| 5655 | /* 420 */ 0x81, 0x40, 0x20, |
| 5656 | /* 423 */ 0x81, 0x40, |
| 5657 | /* 425 */ 0x01, |
| 5658 | /* 426 */ 0x01, |
| 5659 | /* 427 */ 0x01, |
| 5660 | /* 428 */ 0x01, |
| 5661 | }, |
| 5662 | .SubClassMasks: { |
| 5663 | // 0 MR |
| 5664 | 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5665 | // 5 MR0 |
| 5666 | 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5667 | // 10 FPR16 |
| 5668 | 0x00000024, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5669 | 0x20000200, 0x00000000, 0x80000010, 0x80060000, 0x00000001, // sub_16 |
| 5670 | // 20 GPRF16 |
| 5671 | 0x000000d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5672 | 0xdefffc00, 0xffffdfe5, 0x7ff8704f, 0x000007df, 0x00000000, // sub_16 |
| 5673 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd_then_sub_16 |
| 5674 | // 35 GPRF16NoX0 |
| 5675 | 0x00000050, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5676 | 0xdefb3000, 0x7ffe9e65, 0x7fd8100f, 0x0000079f, 0x00000000, // sub_16 |
| 5677 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd_then_sub_16 |
| 5678 | // 50 FPR16C |
| 5679 | 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5680 | 0x20000000, 0x00000000, 0x80000000, 0x00040000, 0x00000001, // sub_16 |
| 5681 | // 60 GPRF16C |
| 5682 | 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5683 | 0xc0000000, 0x50000024, 0x00000001, 0x0000000d, 0x00000000, // sub_16 |
| 5684 | 0x00000000, 0x50000000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_odd_then_sub_16 |
| 5685 | // 75 GPRF16X0 |
| 5686 | 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5687 | 0x00000000, 0x80000180, 0x00000000, 0x00000040, 0x00000000, // sub_16 |
| 5688 | // 85 GPRAll |
| 5689 | 0x5effe500, 0x00001f65, 0x00000000, 0x00000000, 0x00000000, |
| 5690 | 0x00000000, 0x00000000, 0x7ff87040, 0x000007df, 0x00000000, // sub_cap_addr |
| 5691 | 0x00000000, 0xffffc000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_even |
| 5692 | 0x00000000, 0xffffc000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5693 | // 105 FPR32 |
| 5694 | 0x20000200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5695 | 0x00000000, 0x00000000, 0x80000010, 0x80060000, 0x00000001, // sub_32 |
| 5696 | // 115 GPR |
| 5697 | 0x5effe400, 0x00001f65, 0x00000000, 0x00000000, 0x00000000, |
| 5698 | 0x00000000, 0x00000000, 0x7ff87040, 0x000007df, 0x00000000, // sub_cap_addr |
| 5699 | 0x00000000, 0xffffc000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_even |
| 5700 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5701 | // 135 GPRF32 |
| 5702 | 0x80001800, 0x00000080, 0x00000000, 0x00000000, 0x00000000, |
| 5703 | 0x5effe400, 0xffffdf65, 0x7ff8704f, 0x000007df, 0x00000000, // sub_32 |
| 5704 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd_then_sub_32 |
| 5705 | // 150 GPRF32NoX0 |
| 5706 | 0x80001000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5707 | 0x5efb2000, 0x7ffe9e65, 0x7fd8100f, 0x0000079f, 0x00000000, // sub_32 |
| 5708 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd_then_sub_32 |
| 5709 | // 165 GPRNoX0 |
| 5710 | 0x5efb2000, 0x00001e65, 0x00000000, 0x00000000, 0x00000000, |
| 5711 | 0x00000000, 0x00000000, 0x7fd81000, 0x0000079f, 0x00000000, // sub_cap_addr |
| 5712 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_even |
| 5713 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5714 | // 185 GPRNoX2 |
| 5715 | 0x5efd4000, 0x00000f65, 0x00000000, 0x00000000, 0x00000000, |
| 5716 | 0x00000000, 0x00000000, 0x7fe82000, 0x000003df, 0x00000000, // sub_cap_addr |
| 5717 | 0x00000000, 0xfffb0000, 0x0000000d, 0x00000000, 0x00000000, // sub_gpr_even |
| 5718 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5719 | // 205 GPRNoX31 |
| 5720 | 0x54ce8000, 0x00001f65, 0x00000000, 0x00000000, 0x00000000, |
| 5721 | 0x00000000, 0x00000000, 0x56704000, 0x000007df, 0x00000000, // sub_cap_addr |
| 5722 | 0x00000000, 0xffffc000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_even |
| 5723 | 0x00000000, 0x7ad40000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5724 | // 225 GPRNoX0X2 |
| 5725 | 0x5ef90000, 0x00000e65, 0x00000000, 0x00000000, 0x00000000, |
| 5726 | 0x00000000, 0x00000000, 0x7fc80000, 0x0000039f, 0x00000000, // sub_cap_addr |
| 5727 | 0x00000000, 0x7ffa0000, 0x0000000d, 0x00000000, 0x00000000, // sub_gpr_even |
| 5728 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5729 | // 245 GPRNoX0_and_GPRNoX31 |
| 5730 | 0x54ca0000, 0x00001e65, 0x00000000, 0x00000000, 0x00000000, |
| 5731 | 0x00000000, 0x00000000, 0x56500000, 0x0000079f, 0x00000000, // sub_cap_addr |
| 5732 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_even |
| 5733 | 0x00000000, 0x7ad40000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5734 | // 265 GPRNoX2_and_GPRNoX31 |
| 5735 | 0x54cc0000, 0x00000f65, 0x00000000, 0x00000000, 0x00000000, |
| 5736 | 0x00000000, 0x00000000, 0x56600000, 0x000003df, 0x00000000, // sub_cap_addr |
| 5737 | 0x00000000, 0xfffb0000, 0x0000000d, 0x00000000, 0x00000000, // sub_gpr_even |
| 5738 | 0x00000000, 0x7ad40000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5739 | // 285 GPRNoX0X2_and_GPRNoX31 |
| 5740 | 0x54c80000, 0x00000e65, 0x00000000, 0x00000000, 0x00000000, |
| 5741 | 0x00000000, 0x00000000, 0x56400000, 0x0000039f, 0x00000000, // sub_cap_addr |
| 5742 | 0x00000000, 0x7ffa0000, 0x0000000d, 0x00000000, 0x00000000, // sub_gpr_even |
| 5743 | 0x00000000, 0x7ad40000, 0x0000000f, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5744 | // 305 GPRJALR |
| 5745 | 0x5ef00000, 0x00000825, 0x00000000, 0x00000000, 0x00000000, |
| 5746 | 0x00000000, 0x00000000, 0x7f800000, 0x0000020f, 0x00000000, // sub_cap_addr |
| 5747 | 0x00000000, 0x7fe80000, 0x00000009, 0x00000000, 0x00000000, // sub_gpr_even |
| 5748 | 0x00000000, 0x7fe80000, 0x00000009, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5749 | // 325 GPRJALRNonX7 |
| 5750 | 0x58a00000, 0x00000025, 0x00000000, 0x00000000, 0x00000000, |
| 5751 | 0x00000000, 0x00000000, 0x65000000, 0x0000000f, 0x00000000, // sub_cap_addr |
| 5752 | 0x00000000, 0x7fe80000, 0x00000009, 0x00000000, 0x00000000, // sub_gpr_even |
| 5753 | 0x00000000, 0x7ca00000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5754 | // 345 GPRJALR_and_GPRNoX31 |
| 5755 | 0x54c00000, 0x00000825, 0x00000000, 0x00000000, 0x00000000, |
| 5756 | 0x00000000, 0x00000000, 0x56000000, 0x0000020f, 0x00000000, // sub_cap_addr |
| 5757 | 0x00000000, 0x7fe80000, 0x00000009, 0x00000000, 0x00000000, // sub_gpr_even |
| 5758 | 0x00000000, 0x7ac00000, 0x00000009, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5759 | // 365 GPRJALRNonX7_and_GPRNoX31 |
| 5760 | 0x50800000, 0x00000025, 0x00000000, 0x00000000, 0x00000000, |
| 5761 | 0x00000000, 0x00000000, 0x44000000, 0x0000000f, 0x00000000, // sub_cap_addr |
| 5762 | 0x00000000, 0x7fe80000, 0x00000009, 0x00000000, 0x00000000, // sub_gpr_even |
| 5763 | 0x00000000, 0x78800000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5764 | // 385 TR |
| 5765 | 0x01000000, 0x0000000a, 0x00000000, 0x00000000, 0x00000000, |
| 5766 | // 390 GPRTC |
| 5767 | 0x1e000000, 0x00000804, 0x00000000, 0x00000000, 0x00000000, |
| 5768 | 0x00000000, 0x00000000, 0x78000000, 0x00000204, 0x00000000, // sub_cap_addr |
| 5769 | 0x00000000, 0x4f000000, 0x00000008, 0x00000000, 0x00000000, // sub_gpr_even |
| 5770 | 0x00000000, 0x4f000000, 0x00000008, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5771 | // 410 GPRNoX31_and_GPRTC |
| 5772 | 0x14000000, 0x00000804, 0x00000000, 0x00000000, 0x00000000, |
| 5773 | 0x00000000, 0x00000000, 0x50000000, 0x00000204, 0x00000000, // sub_cap_addr |
| 5774 | 0x00000000, 0x4f000000, 0x00000008, 0x00000000, 0x00000000, // sub_gpr_even |
| 5775 | 0x00000000, 0x4a000000, 0x00000008, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5776 | // 430 GPRTCNonX7 |
| 5777 | 0x18000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000, |
| 5778 | 0x00000000, 0x00000000, 0x60000000, 0x00000004, 0x00000000, // sub_cap_addr |
| 5779 | 0x00000000, 0x4f000000, 0x00000008, 0x00000000, 0x00000000, // sub_gpr_even |
| 5780 | 0x00000000, 0x4c000000, 0x00000000, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5781 | // 450 GPRNoX31_and_GPRTCNonX7 |
| 5782 | 0x10000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000, |
| 5783 | 0x00000000, 0x00000000, 0x40000000, 0x00000004, 0x00000000, // sub_cap_addr |
| 5784 | 0x00000000, 0x4f000000, 0x00000008, 0x00000000, 0x00000000, // sub_gpr_even |
| 5785 | 0x00000000, 0x48000000, 0x00000000, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5786 | // 470 FPR32C |
| 5787 | 0x20000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5788 | 0x00000000, 0x00000000, 0x80000000, 0x00040000, 0x00000001, // sub_32 |
| 5789 | // 480 GPRC |
| 5790 | 0x40000000, 0x00000024, 0x00000000, 0x00000000, 0x00000000, |
| 5791 | 0x00000000, 0x00000000, 0x00000000, 0x0000000d, 0x00000000, // sub_cap_addr |
| 5792 | 0x00000000, 0x50000000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_even |
| 5793 | 0x00000000, 0x50000000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5794 | // 500 GPRF32C |
| 5795 | 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 5796 | 0x40000000, 0x50000024, 0x00000001, 0x0000000d, 0x00000000, // sub_32 |
| 5797 | 0x00000000, 0x50000000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_odd_then_sub_32 |
| 5798 | // 515 GPRS07 |
| 5799 | 0x00000000, 0x00000021, 0x00000000, 0x00000000, 0x00000000, |
| 5800 | 0x00000000, 0x00000000, 0x00000000, 0x0000000a, 0x00000000, // sub_cap_addr |
| 5801 | 0x00000000, 0x20000000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_even |
| 5802 | 0x00000000, 0x20000000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5803 | // 535 TRM2 |
| 5804 | 0x00000000, 0x0000000a, 0x00000000, 0x00000000, 0x00000000, |
| 5805 | // 540 GPRC_and_GPRTC |
| 5806 | 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000, |
| 5807 | 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000, // sub_cap_addr |
| 5808 | 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000, // sub_gpr_even |
| 5809 | 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5810 | // 560 TRM4 |
| 5811 | 0x00000000, 0x00000008, 0x00000000, 0x00000000, 0x00000000, |
| 5812 | // 565 VCSR |
| 5813 | 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, |
| 5814 | // 570 GPRC_and_GPRS07 |
| 5815 | 0x00000000, 0x00000020, 0x00000000, 0x00000000, 0x00000000, |
| 5816 | 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, // sub_cap_addr |
| 5817 | 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_even |
| 5818 | 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5819 | // 590 GPRX1X5 |
| 5820 | 0x00000000, 0x00000640, 0x00000000, 0x00000000, 0x00000000, |
| 5821 | 0x00000000, 0x00000000, 0x00000000, 0x00000190, 0x00000000, // sub_cap_addr |
| 5822 | 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5823 | // 605 GPRF32X0 |
| 5824 | 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, |
| 5825 | 0x00000000, 0x80000100, 0x00000000, 0x00000040, 0x00000000, // sub_32 |
| 5826 | // 615 GPRX0 |
| 5827 | 0x00000000, 0x00000100, 0x00000000, 0x00000000, 0x00000000, |
| 5828 | 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00000000, // sub_cap_addr |
| 5829 | 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, // sub_gpr_even |
| 5830 | // 630 GPRX1 |
| 5831 | 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000, |
| 5832 | 0x00000000, 0x00000000, 0x00000000, 0x00000080, 0x00000000, // sub_cap_addr |
| 5833 | // 640 GPRX5 |
| 5834 | 0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000, |
| 5835 | 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, // sub_cap_addr |
| 5836 | 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5837 | // 655 GPRX7 |
| 5838 | 0x00000000, 0x00000800, 0x00000000, 0x00000000, 0x00000000, |
| 5839 | 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x00000000, // sub_cap_addr |
| 5840 | 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000, // sub_gpr_odd |
| 5841 | // 670 SP |
| 5842 | 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000, |
| 5843 | 0x00000000, 0x00000000, 0x00000000, 0x00000400, 0x00000000, // sub_cap_addr |
| 5844 | 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, // sub_gpr_even |
| 5845 | // 685 anonymous_15061 |
| 5846 | 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000000, |
| 5847 | // 690 GPRPair |
| 5848 | 0x00000000, 0xffffc000, 0x0000000f, 0x00000000, 0x00000000, |
| 5849 | // 695 GPRPairNoX0 |
| 5850 | 0x00000000, 0x7ffe8000, 0x0000000f, 0x00000000, 0x00000000, |
| 5851 | // 700 GPRPair_with_sub_gpr_even_in_GPRNoX2 |
| 5852 | 0x00000000, 0xfffb0000, 0x0000000d, 0x00000000, 0x00000000, |
| 5853 | // 705 GPRPair_with_sub_gpr_even_in_GPRNoX0X2 |
| 5854 | 0x00000000, 0x7ffa0000, 0x0000000d, 0x00000000, 0x00000000, |
| 5855 | // 710 GPRPair_with_sub_gpr_odd_in_GPRNoX31 |
| 5856 | 0x00000000, 0x7ad40000, 0x0000000f, 0x00000000, 0x00000000, |
| 5857 | // 715 GPRPair_with_sub_gpr_even_in_GPRJALR |
| 5858 | 0x00000000, 0x7fe80000, 0x00000009, 0x00000000, 0x00000000, |
| 5859 | // 720 GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31 |
| 5860 | 0x00000000, 0x7ad00000, 0x0000000d, 0x00000000, 0x00000000, |
| 5861 | // 725 GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7 |
| 5862 | 0x00000000, 0x7ca00000, 0x00000001, 0x00000000, 0x00000000, |
| 5863 | // 730 GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31 |
| 5864 | 0x00000000, 0x7ac00000, 0x00000009, 0x00000000, 0x00000000, |
| 5865 | // 735 GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31 |
| 5866 | 0x00000000, 0x78800000, 0x00000001, 0x00000000, 0x00000000, |
| 5867 | // 740 GPRPair_with_sub_gpr_even_in_GPRTC |
| 5868 | 0x00000000, 0x4f000000, 0x00000008, 0x00000000, 0x00000000, |
| 5869 | // 745 GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTC |
| 5870 | 0x00000000, 0x4a000000, 0x00000008, 0x00000000, 0x00000000, |
| 5871 | // 750 GPRPair_with_sub_gpr_odd_in_GPRTCNonX7 |
| 5872 | 0x00000000, 0x4c000000, 0x00000000, 0x00000000, 0x00000000, |
| 5873 | // 755 GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7 |
| 5874 | 0x00000000, 0x48000000, 0x00000000, 0x00000000, 0x00000000, |
| 5875 | // 760 GPRPairC |
| 5876 | 0x00000000, 0x50000000, 0x00000001, 0x00000000, 0x00000000, |
| 5877 | // 765 GPRPair_with_sub_gpr_even_in_GPRS07 |
| 5878 | 0x00000000, 0x20000000, 0x00000001, 0x00000000, 0x00000000, |
| 5879 | // 770 GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC |
| 5880 | 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000, |
| 5881 | // 775 GPRPair_with_sub_16_in_GPRF16X0 |
| 5882 | 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, |
| 5883 | // 780 GPRPair_with_sub_gpr_even_in_GPRC_and_GPRS07 |
| 5884 | 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, |
| 5885 | // 785 GPRPair_with_sub_gpr_even_in_SP |
| 5886 | 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, |
| 5887 | // 790 GPRPair_with_sub_gpr_odd_in_GPRX1X5 |
| 5888 | 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, |
| 5889 | // 795 GPRPair_with_sub_gpr_odd_in_GPRX7 |
| 5890 | 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000, |
| 5891 | // 800 FPR64 |
| 5892 | 0x00000000, 0x00000000, 0x80000010, 0x00000000, 0x00000000, |
| 5893 | 0x00000000, 0x00000000, 0x00000000, 0x80060000, 0x00000001, // sub_64 |
| 5894 | // 810 VR |
| 5895 | 0x00000000, 0x00000000, 0x00078fa0, 0x00000020, 0x00000000, |
| 5896 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_0 |
| 5897 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5898 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5899 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5900 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5901 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5902 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5903 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5904 | // 855 YGPR |
| 5905 | 0x00000000, 0x00000000, 0x7ff87040, 0x000007df, 0x00000000, |
| 5906 | // 860 ZZZ_VM |
| 5907 | 0x00000000, 0x00000000, 0x00078f80, 0x00000020, 0x00000000, |
| 5908 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_0 |
| 5909 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5910 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5911 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5912 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5913 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5914 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5915 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5916 | // 905 ZZZ_VRMF2 |
| 5917 | 0x00000000, 0x00000000, 0x00078f80, 0x00000020, 0x00000000, |
| 5918 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_0 |
| 5919 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5920 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5921 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5922 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5923 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5924 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5925 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5926 | // 950 ZZZ_VRMF4 |
| 5927 | 0x00000000, 0x00000000, 0x00078f80, 0x00000020, 0x00000000, |
| 5928 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_0 |
| 5929 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5930 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5931 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5932 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5933 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5934 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5935 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5936 | // 995 ZZZ_VRMF8 |
| 5937 | 0x00000000, 0x00000000, 0x00078f80, 0x00000020, 0x00000000, |
| 5938 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_0 |
| 5939 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5940 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5941 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5942 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5943 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5944 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5945 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5946 | // 1040 VRNoV0 |
| 5947 | 0x00000000, 0x00000000, 0x00078800, 0x00000000, 0x00000000, |
| 5948 | 0x00000000, 0x00000000, 0x00000000, 0x0a905000, 0x001548a4, // sub_vrm1_0 |
| 5949 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5950 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5951 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5952 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5953 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5954 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5955 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5956 | // 1085 YGPR_with_sub_16_in_GPRF16NoX0 |
| 5957 | 0x00000000, 0x00000000, 0x7fd81000, 0x0000079f, 0x00000000, |
| 5958 | // 1090 YGPR_with_sub_cap_addr_in_GPRNoX2 |
| 5959 | 0x00000000, 0x00000000, 0x7fe82000, 0x000003df, 0x00000000, |
| 5960 | // 1095 YGPR_with_sub_cap_addr_in_GPRNoX31 |
| 5961 | 0x00000000, 0x00000000, 0x56704000, 0x000007df, 0x00000000, |
| 5962 | // 1100 ZZZ_VMNoV0 |
| 5963 | 0x00000000, 0x00000000, 0x00078000, 0x00000000, 0x00000000, |
| 5964 | 0x00000000, 0x00000000, 0x00000000, 0x0a905000, 0x001548a4, // sub_vrm1_0 |
| 5965 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5966 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5967 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5968 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5969 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5970 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5971 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5972 | // 1145 ZZZ_VRMF2NoV0 |
| 5973 | 0x00000000, 0x00000000, 0x00078000, 0x00000000, 0x00000000, |
| 5974 | 0x00000000, 0x00000000, 0x00000000, 0x0a905000, 0x001548a4, // sub_vrm1_0 |
| 5975 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5976 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5977 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5978 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5979 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5980 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5981 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5982 | // 1190 ZZZ_VRMF4NoV0 |
| 5983 | 0x00000000, 0x00000000, 0x00078000, 0x00000000, 0x00000000, |
| 5984 | 0x00000000, 0x00000000, 0x00000000, 0x0a905000, 0x001548a4, // sub_vrm1_0 |
| 5985 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5986 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5987 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5988 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5989 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 5990 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 5991 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 5992 | // 1235 ZZZ_VRMF8NoV0 |
| 5993 | 0x00000000, 0x00000000, 0x00078000, 0x00000000, 0x00000000, |
| 5994 | 0x00000000, 0x00000000, 0x00000000, 0x0a905000, 0x001548a4, // sub_vrm1_0 |
| 5995 | 0x00000000, 0x00000000, 0x00000000, 0x7ff9f800, 0x01fffffe, // sub_vrm1_1 |
| 5996 | 0x00000000, 0x00000000, 0x00000000, 0x7ff80000, 0x01fffffe, // sub_vrm1_2 |
| 5997 | 0x00000000, 0x00000000, 0x00000000, 0x7fc00000, 0x01fffffe, // sub_vrm1_3 |
| 5998 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffffe, // sub_vrm1_4 |
| 5999 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffff0, // sub_vrm1_5 |
| 6000 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01fffc00, // sub_vrm1_6 |
| 6001 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffe000, // sub_vrm1_7 |
| 6002 | // 1280 YGPR_with_sub_cap_addr_in_GPRNoX0X2 |
| 6003 | 0x00000000, 0x00000000, 0x7fc80000, 0x0000039f, 0x00000000, |
| 6004 | // 1285 YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31 |
| 6005 | 0x00000000, 0x00000000, 0x56500000, 0x0000079f, 0x00000000, |
| 6006 | // 1290 YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31 |
| 6007 | 0x00000000, 0x00000000, 0x56600000, 0x000003df, 0x00000000, |
| 6008 | // 1295 YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31 |
| 6009 | 0x00000000, 0x00000000, 0x56400000, 0x0000039f, 0x00000000, |
| 6010 | // 1300 YGPR_with_sub_cap_addr_in_GPRJALR |
| 6011 | 0x00000000, 0x00000000, 0x7f800000, 0x0000020f, 0x00000000, |
| 6012 | // 1305 YGPR_with_sub_cap_addr_in_GPRJALRNonX7 |
| 6013 | 0x00000000, 0x00000000, 0x65000000, 0x0000000f, 0x00000000, |
| 6014 | // 1310 YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31 |
| 6015 | 0x00000000, 0x00000000, 0x56000000, 0x0000020f, 0x00000000, |
| 6016 | // 1315 YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31 |
| 6017 | 0x00000000, 0x00000000, 0x44000000, 0x0000000f, 0x00000000, |
| 6018 | // 1320 YGPR_with_sub_cap_addr_in_GPRTC |
| 6019 | 0x00000000, 0x00000000, 0x78000000, 0x00000204, 0x00000000, |
| 6020 | // 1325 YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTC |
| 6021 | 0x00000000, 0x00000000, 0x50000000, 0x00000204, 0x00000000, |
| 6022 | // 1330 YGPR_with_sub_cap_addr_in_GPRTCNonX7 |
| 6023 | 0x00000000, 0x00000000, 0x60000000, 0x00000004, 0x00000000, |
| 6024 | // 1335 YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7 |
| 6025 | 0x00000000, 0x00000000, 0x40000000, 0x00000004, 0x00000000, |
| 6026 | // 1340 FPR64C |
| 6027 | 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, |
| 6028 | 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000001, // sub_64 |
| 6029 | // 1350 YGPR_with_sub_16_in_GPRF16C |
| 6030 | 0x00000000, 0x00000000, 0x00000000, 0x0000000d, 0x00000000, |
| 6031 | // 1355 YGPR_with_sub_cap_addr_in_GPRS07 |
| 6032 | 0x00000000, 0x00000000, 0x00000000, 0x0000000a, 0x00000000, |
| 6033 | // 1360 YGPR_with_sub_cap_addr_in_GPRC_and_GPRTC |
| 6034 | 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000, |
| 6035 | // 1365 YGPR_with_sub_cap_addr_in_GPRC_and_GPRS07 |
| 6036 | 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, |
| 6037 | // 1370 YGPR_with_sub_cap_addr_in_GPRX1X5 |
| 6038 | 0x00000000, 0x00000000, 0x00000000, 0x00000190, 0x00000000, |
| 6039 | // 1375 VMV0 |
| 6040 | 0x00000000, 0x00000000, 0x00000000, 0x00000020, 0x00000000, |
| 6041 | 0x00000000, 0x00000000, 0x00000000, 0x70218000, 0x01e01308, // sub_vrm1_0 |
| 6042 | // 1385 YGPR_with_sub_16_in_GPRF16X0 |
| 6043 | 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00000000, |
| 6044 | // 1390 YGPR_with_sub_cap_addr_in_GPRX1 |
| 6045 | 0x00000000, 0x00000000, 0x00000000, 0x00000080, 0x00000000, |
| 6046 | // 1395 YGPR_with_sub_cap_addr_in_GPRX5 |
| 6047 | 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, |
| 6048 | // 1400 YGPR_with_sub_cap_addr_in_GPRX7 |
| 6049 | 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x00000000, |
| 6050 | // 1405 YGPR_with_sub_cap_addr_in_SP |
| 6051 | 0x00000000, 0x00000000, 0x00000000, 0x00000400, 0x00000000, |
| 6052 | // 1410 VRN2M1 |
| 6053 | 0x00000000, 0x00000000, 0x00000000, 0x00011800, 0x00000000, |
| 6054 | 0x00000000, 0x00000000, 0x00000000, 0x63f80000, 0x01c7fffe, // sub_vrm1_0_sub_vrm1_1 |
| 6055 | 0x00000000, 0x00000000, 0x00000000, 0x63f80000, 0x01c7fffe, // sub_vrm1_1_sub_vrm1_2 |
| 6056 | 0x00000000, 0x00000000, 0x00000000, 0x63c00000, 0x01c7fffe, // sub_vrm1_2_sub_vrm1_3 |
| 6057 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fffe, // sub_vrm1_3_sub_vrm1_4 |
| 6058 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_4_sub_vrm1_5 |
| 6059 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_5_sub_vrm1_6 |
| 6060 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_6_sub_vrm1_7 |
| 6061 | // 1450 VRN2M1NoV0 |
| 6062 | 0x00000000, 0x00000000, 0x00000000, 0x00001000, 0x00000000, |
| 6063 | 0x00000000, 0x00000000, 0x00000000, 0x02900000, 0x000548a4, // sub_vrm1_0_sub_vrm1_1 |
| 6064 | 0x00000000, 0x00000000, 0x00000000, 0x63f80000, 0x01c7fffe, // sub_vrm1_1_sub_vrm1_2 |
| 6065 | 0x00000000, 0x00000000, 0x00000000, 0x63c00000, 0x01c7fffe, // sub_vrm1_2_sub_vrm1_3 |
| 6066 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fffe, // sub_vrm1_3_sub_vrm1_4 |
| 6067 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_4_sub_vrm1_5 |
| 6068 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_5_sub_vrm1_6 |
| 6069 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_6_sub_vrm1_7 |
| 6070 | // 1490 VRM2 |
| 6071 | 0x00000000, 0x00000000, 0x00000000, 0x0000e000, 0x00000000, |
| 6072 | 0x00000000, 0x00000000, 0x00000000, 0x3f000000, 0x00ff81c0, // sub_vrm2_0 |
| 6073 | 0x00000000, 0x00000000, 0x00000000, 0x3f000000, 0x00ff81c0, // sub_vrm2_1 |
| 6074 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ff81c0, // sub_vrm2_2 |
| 6075 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ff8000, // sub_vrm2_3 |
| 6076 | // 1515 VRM2NoV0 |
| 6077 | 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000, |
| 6078 | 0x00000000, 0x00000000, 0x00000000, 0x0a000000, 0x00150080, // sub_vrm2_0 |
| 6079 | 0x00000000, 0x00000000, 0x00000000, 0x3f000000, 0x00ff81c0, // sub_vrm2_1 |
| 6080 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ff81c0, // sub_vrm2_2 |
| 6081 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ff8000, // sub_vrm2_3 |
| 6082 | // 1540 VRM2_with_sub_vrm1_0_in_VMV0 |
| 6083 | 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000, |
| 6084 | 0x00000000, 0x00000000, 0x00000000, 0x30000000, 0x00e00100, // sub_vrm2_0 |
| 6085 | // 1550 VRN2M1_with_sub_vrm1_0_in_VMV0 |
| 6086 | 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, |
| 6087 | 0x00000000, 0x00000000, 0x00000000, 0x60200000, 0x01c01308, // sub_vrm1_0_sub_vrm1_1 |
| 6088 | // 1560 FPR128 |
| 6089 | 0x00000000, 0x00000000, 0x00000000, 0x00060000, 0x00000000, |
| 6090 | 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000001, // sub_128 |
| 6091 | // 1570 FPR128_with_sub_16_in_FPR16C |
| 6092 | 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000, |
| 6093 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, // sub_128 |
| 6094 | // 1580 VRN3M1 |
| 6095 | 0x00000000, 0x00000000, 0x00000000, 0x00380000, 0x00000000, |
| 6096 | 0x00000000, 0x00000000, 0x00000000, 0x63c00000, 0x01c7fffe, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 |
| 6097 | 0x00000000, 0x00000000, 0x00000000, 0x63c00000, 0x01c7fffe, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 |
| 6098 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fffe, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 |
| 6099 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6100 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6101 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6102 | // 1615 VRN3M1NoV0 |
| 6103 | 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000, |
| 6104 | 0x00000000, 0x00000000, 0x00000000, 0x02800000, 0x000548a4, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 |
| 6105 | 0x00000000, 0x00000000, 0x00000000, 0x63c00000, 0x01c7fffe, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 |
| 6106 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fffe, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 |
| 6107 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6108 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6109 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6110 | // 1650 VRN3M1_with_sub_vrm1_0_in_VMV0 |
| 6111 | 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000, |
| 6112 | 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0x01c01308, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 |
| 6113 | // 1660 VRN4M1 |
| 6114 | 0x00000000, 0x00000000, 0x00000000, 0x40c00000, 0x00000000, |
| 6115 | 0x00000000, 0x00000000, 0x00000000, 0x23000000, 0x01c7fffe, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 |
| 6116 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fffe, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 |
| 6117 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6118 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6119 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6120 | // 1690 VRN4M1NoV0 |
| 6121 | 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, |
| 6122 | 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x000548a4, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 |
| 6123 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fffe, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 |
| 6124 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6125 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6126 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6127 | // 1720 VRN2M2 |
| 6128 | 0x00000000, 0x00000000, 0x00000000, 0x23000000, 0x00000000, |
| 6129 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c781c0, // sub_vrm2_0_sub_vrm2_1 |
| 6130 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c781c0, // sub_vrm2_1_sub_vrm2_2 |
| 6131 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c78000, // sub_vrm2_2_sub_vrm2_3 |
| 6132 | // 1740 VRN2M2NoV0 |
| 6133 | 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000, |
| 6134 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00050080, // sub_vrm2_0_sub_vrm2_1 |
| 6135 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c781c0, // sub_vrm2_1_sub_vrm2_2 |
| 6136 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c78000, // sub_vrm2_2_sub_vrm2_3 |
| 6137 | // 1760 VRM4 |
| 6138 | 0x00000000, 0x00000000, 0x00000000, 0x1c000000, 0x00000000, |
| 6139 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x007e0000, // sub_vrm4_0 |
| 6140 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x007e0000, // sub_vrm4_1 |
| 6141 | // 1775 VRM4NoV0 |
| 6142 | 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, |
| 6143 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00140000, // sub_vrm4_0 |
| 6144 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x007e0000, // sub_vrm4_1 |
| 6145 | // 1790 VRM4_with_sub_vrm1_0_in_VMV0 |
| 6146 | 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000, |
| 6147 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00600000, // sub_vrm4_0 |
| 6148 | // 1800 VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 |
| 6149 | 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, |
| 6150 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00100, // sub_vrm2_0_sub_vrm2_1 |
| 6151 | // 1810 VRN4M1_with_sub_vrm1_0_in_VMV0 |
| 6152 | 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000, |
| 6153 | 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x01c01308, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 |
| 6154 | // 1820 FPR256 |
| 6155 | 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000001, |
| 6156 | // 1825 FPR256_with_sub_16_in_FPR16C |
| 6157 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, |
| 6158 | // 1830 VRN5M1 |
| 6159 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000e, |
| 6160 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 |
| 6161 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6162 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6163 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6164 | // 1855 VRN5M1NoV0 |
| 6165 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000004, |
| 6166 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000548a0, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 |
| 6167 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fff0, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6168 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6169 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6170 | // 1880 VRN5M1_with_sub_vrm1_0_in_VMV0 |
| 6171 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, |
| 6172 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c01300, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 |
| 6173 | // 1890 VRN6M1 |
| 6174 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000230, |
| 6175 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fdc0, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6176 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6177 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6178 | // 1910 VRN6M1NoV0 |
| 6179 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, |
| 6180 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00054880, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6181 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7fc00, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6182 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6183 | // 1930 VRN3M2 |
| 6184 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, |
| 6185 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c78000, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 |
| 6186 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c78000, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 |
| 6187 | // 1945 VRN3M2NoV0 |
| 6188 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000080, |
| 6189 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00050000, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 |
| 6190 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c78000, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 |
| 6191 | // 1960 VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 |
| 6192 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, |
| 6193 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 |
| 6194 | // 1970 VRN6M1_with_sub_vrm1_0_in_VMV0 |
| 6195 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200, |
| 6196 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c01100, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 |
| 6197 | // 1980 VRN7M1 |
| 6198 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001c00, |
| 6199 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6200 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6201 | // 1995 VRN7M1NoV0 |
| 6202 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000800, |
| 6203 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00054000, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6204 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c7e000, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6205 | // 2010 VRN7M1_with_sub_vrm1_0_in_VMV0 |
| 6206 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001000, |
| 6207 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c00000, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 |
| 6208 | // 2020 VRN8M1 |
| 6209 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01006000, |
| 6210 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c78000, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6211 | // 2030 VRN8M1NoV0 |
| 6212 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004000, |
| 6213 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00050000, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6214 | // 2040 VRN4M2 |
| 6215 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00818000, |
| 6216 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00460000, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 |
| 6217 | // 2050 VRN4M2NoV0 |
| 6218 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, |
| 6219 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 |
| 6220 | // 2060 VRN2M4 |
| 6221 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00460000, |
| 6222 | // 2065 VRN2M4NoV0 |
| 6223 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000, |
| 6224 | // 2070 VRM8 |
| 6225 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00380000, |
| 6226 | // 2075 VRM8NoV0 |
| 6227 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00100000, |
| 6228 | // 2080 VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0 |
| 6229 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00200000, |
| 6230 | // 2085 VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0 |
| 6231 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000, |
| 6232 | // 2090 VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 |
| 6233 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000, |
| 6234 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 |
| 6235 | // 2100 VRN8M1_with_sub_vrm1_0_in_VMV0 |
| 6236 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01000000, |
| 6237 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 |
| 6238 | }, |
| 6239 | .SuperRegIdxSeqs: { |
| 6240 | /* 0 */ 1, 0, |
| 6241 | /* 2 */ 2, 0, |
| 6242 | /* 4 */ 3, 0, |
| 6243 | /* 6 */ 4, 0, |
| 6244 | /* 8 */ 5, 0, |
| 6245 | /* 10 */ 5, 6, 0, |
| 6246 | /* 13 */ 5, 7, 0, |
| 6247 | /* 16 */ 5, 6, 7, 0, |
| 6248 | /* 20 */ 8, 0, |
| 6249 | /* 22 */ 8, 9, 10, 11, 12, 13, 14, 15, 0, |
| 6250 | /* 31 */ 16, 0, |
| 6251 | /* 33 */ 16, 17, 18, 19, 0, |
| 6252 | /* 38 */ 20, 0, |
| 6253 | /* 40 */ 20, 21, 0, |
| 6254 | /* 43 */ 1, 22, 0, |
| 6255 | /* 46 */ 2, 23, 0, |
| 6256 | /* 49 */ 24, 0, |
| 6257 | /* 51 */ 25, 0, |
| 6258 | /* 53 */ 26, 0, |
| 6259 | /* 55 */ 30, 0, |
| 6260 | /* 57 */ 31, 0, |
| 6261 | /* 59 */ 32, 0, |
| 6262 | /* 61 */ 33, 0, |
| 6263 | /* 63 */ 32, 37, 0, |
| 6264 | /* 66 */ 31, 36, 41, 0, |
| 6265 | /* 70 */ 30, 35, 40, 45, 0, |
| 6266 | /* 75 */ 26, 34, 39, 44, 48, 0, |
| 6267 | /* 81 */ 25, 28, 38, 43, 47, 50, 0, |
| 6268 | /* 88 */ 24, 27, 29, 42, 46, 49, 51, 0, |
| 6269 | /* 96 */ 52, 0, |
| 6270 | /* 98 */ 53, 0, |
| 6271 | /* 100 */ 54, 0, |
| 6272 | /* 102 */ 53, 56, 0, |
| 6273 | /* 105 */ 52, 55, 57, 0, |
| 6274 | }, |
| 6275 | .SuperClasses: { |
| 6276 | /* 0 MR */ |
| 6277 | /* 0 MR0 */ RISCV::MRRegClassID, |
| 6278 | /* 1 FPR16 */ |
| 6279 | /* 1 GPRF16 */ |
| 6280 | /* 1 GPRF16NoX0 */ RISCV::GPRF16RegClassID, |
| 6281 | /* 2 FPR16C */ RISCV::FPR16RegClassID, |
| 6282 | /* 3 GPRF16C */ RISCV::GPRF16RegClassID, RISCV::GPRF16NoX0RegClassID, |
| 6283 | /* 5 GPRF16X0 */ RISCV::GPRF16RegClassID, |
| 6284 | /* 6 GPRAll */ |
| 6285 | /* 6 FPR32 */ |
| 6286 | /* 6 GPR */ RISCV::GPRAllRegClassID, |
| 6287 | /* 7 GPRF32 */ |
| 6288 | /* 7 GPRF32NoX0 */ RISCV::GPRF32RegClassID, |
| 6289 | /* 8 GPRNoX0 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, |
| 6290 | /* 10 GPRNoX2 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, |
| 6291 | /* 12 GPRNoX31 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, |
| 6292 | /* 14 GPRNoX0X2 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, |
| 6293 | /* 18 GPRNoX0_and_GPRNoX31 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX31RegClassID, |
| 6294 | /* 22 GPRNoX2_and_GPRNoX31 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, |
| 6295 | /* 26 GPRNoX0X2_and_GPRNoX31 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, |
| 6296 | /* 34 GPRJALR */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX0X2RegClassID, |
| 6297 | /* 39 GPRJALRNonX7 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRJALRRegClassID, |
| 6298 | /* 45 GPRJALR_and_GPRNoX31 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, |
| 6299 | /* 55 GPRJALRNonX7_and_GPRNoX31 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALRNonX7RegClassID, RISCV::GPRJALR_and_GPRNoX31RegClassID, |
| 6300 | /* 67 TR */ |
| 6301 | /* 67 GPRTC */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRJALRRegClassID, |
| 6302 | /* 73 GPRNoX31_and_GPRTC */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRTCRegClassID, |
| 6303 | /* 85 GPRTCNonX7 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALRNonX7RegClassID, RISCV::GPRTCRegClassID, |
| 6304 | /* 93 GPRNoX31_and_GPRTCNonX7 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALRNonX7RegClassID, RISCV::GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::GPRTCRegClassID, RISCV::GPRNoX31_and_GPRTCRegClassID, RISCV::GPRTCNonX7RegClassID, |
| 6305 | /* 109 FPR32C */ RISCV::FPR32RegClassID, |
| 6306 | /* 110 GPRC */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALRNonX7RegClassID, RISCV::GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 6307 | /* 123 GPRF32C */ RISCV::GPRF32RegClassID, RISCV::GPRF32NoX0RegClassID, |
| 6308 | /* 125 GPRS07 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALRNonX7RegClassID, RISCV::GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 6309 | /* 138 TRM2 */ RISCV::TRRegClassID, |
| 6310 | /* 139 GPRC_and_GPRTC */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALRNonX7RegClassID, RISCV::GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::GPRTCRegClassID, RISCV::GPRNoX31_and_GPRTCRegClassID, RISCV::GPRTCNonX7RegClassID, RISCV::GPRNoX31_and_GPRTCNonX7RegClassID, RISCV::GPRCRegClassID, |
| 6311 | /* 157 TRM4 */ RISCV::TRRegClassID, RISCV::TRM2RegClassID, |
| 6312 | /* 159 VCSR */ |
| 6313 | /* 159 GPRC_and_GPRS07 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALRNonX7RegClassID, RISCV::GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::GPRCRegClassID, RISCV::GPRS07RegClassID, |
| 6314 | /* 174 GPRX1X5 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, |
| 6315 | /* 183 GPRF32X0 */ RISCV::GPRF32RegClassID, |
| 6316 | /* 184 GPRX0 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, |
| 6317 | /* 189 GPRX1 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRX1X5RegClassID, |
| 6318 | /* 199 GPRX5 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRX1X5RegClassID, |
| 6319 | /* 209 GPRX7 */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX2RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0X2RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, RISCV::GPRNoX2_and_GPRNoX31RegClassID, RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::GPRJALRRegClassID, RISCV::GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRTCRegClassID, RISCV::GPRNoX31_and_GPRTCRegClassID, |
| 6320 | /* 222 SP */ RISCV::GPRAllRegClassID, RISCV::GPRRegClassID, RISCV::GPRNoX0RegClassID, RISCV::GPRNoX31RegClassID, RISCV::GPRNoX0_and_GPRNoX31RegClassID, |
| 6321 | /* 227 anonymous_15061 */ |
| 6322 | /* 227 GPRPair */ |
| 6323 | /* 227 GPRPairNoX0 */ RISCV::GPRPairRegClassID, |
| 6324 | /* 228 GPRPair_with_sub_gpr_even_in_GPRNoX2 */ RISCV::GPRPairRegClassID, |
| 6325 | /* 229 GPRPair_with_sub_gpr_even_in_GPRNoX0X2 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, |
| 6326 | /* 232 GPRPair_with_sub_gpr_odd_in_GPRNoX31 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, |
| 6327 | /* 234 GPRPair_with_sub_gpr_even_in_GPRJALR */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, |
| 6328 | /* 238 GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, |
| 6329 | /* 243 GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, |
| 6330 | /* 248 GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, |
| 6331 | /* 255 GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, |
| 6332 | /* 264 GPRPair_with_sub_gpr_even_in_GPRTC */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, |
| 6333 | /* 269 GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTC */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID, |
| 6334 | /* 278 GPRPair_with_sub_gpr_odd_in_GPRTCNonX7 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID, |
| 6335 | /* 285 GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRTCNonX7RegClassID, |
| 6336 | /* 298 GPRPairC */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 6337 | /* 308 GPRPair_with_sub_gpr_even_in_GPRS07 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 6338 | /* 318 GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRTCNonX7RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7RegClassID, RISCV::GPRPairCRegClassID, |
| 6339 | /* 333 GPRPair_with_sub_16_in_GPRF16X0 */ RISCV::GPRPairRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, |
| 6340 | /* 335 GPRPair_with_sub_gpr_even_in_GPRC_and_GPRS07 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::GPRPairCRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRS07RegClassID, |
| 6341 | /* 347 GPRPair_with_sub_gpr_even_in_SP */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, |
| 6342 | /* 350 GPRPair_with_sub_gpr_odd_in_GPRX1X5 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, |
| 6343 | /* 356 GPRPair_with_sub_gpr_odd_in_GPRX7 */ RISCV::GPRPairRegClassID, RISCV::GPRPairNoX0RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID, RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID, |
| 6344 | /* 366 FPR64 */ |
| 6345 | /* 366 VR */ |
| 6346 | /* 366 YGPR */ |
| 6347 | /* 366 ZZZ_VM */ RISCV::VRRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF4RegClassID, RISCV::ZZZ_VRMF8RegClassID, |
| 6348 | /* 370 ZZZ_VRMF2 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF4RegClassID, RISCV::ZZZ_VRMF8RegClassID, |
| 6349 | /* 374 ZZZ_VRMF4 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF8RegClassID, |
| 6350 | /* 378 ZZZ_VRMF8 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF4RegClassID, |
| 6351 | /* 382 VRNoV0 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF4RegClassID, RISCV::ZZZ_VRMF8RegClassID, |
| 6352 | /* 387 YGPR_with_sub_16_in_GPRF16NoX0 */ RISCV::YGPRRegClassID, |
| 6353 | /* 388 YGPR_with_sub_cap_addr_in_GPRNoX2 */ RISCV::YGPRRegClassID, |
| 6354 | /* 389 YGPR_with_sub_cap_addr_in_GPRNoX31 */ RISCV::YGPRRegClassID, |
| 6355 | /* 390 ZZZ_VMNoV0 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF4RegClassID, RISCV::ZZZ_VRMF8RegClassID, RISCV::VRNoV0RegClassID, RISCV::ZZZ_VRMF2NoV0RegClassID, RISCV::ZZZ_VRMF4NoV0RegClassID, RISCV::ZZZ_VRMF8NoV0RegClassID, |
| 6356 | /* 399 ZZZ_VRMF2NoV0 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF4RegClassID, RISCV::ZZZ_VRMF8RegClassID, RISCV::VRNoV0RegClassID, RISCV::ZZZ_VMNoV0RegClassID, RISCV::ZZZ_VRMF4NoV0RegClassID, RISCV::ZZZ_VRMF8NoV0RegClassID, |
| 6357 | /* 408 ZZZ_VRMF4NoV0 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF4RegClassID, RISCV::ZZZ_VRMF8RegClassID, RISCV::VRNoV0RegClassID, RISCV::ZZZ_VMNoV0RegClassID, RISCV::ZZZ_VRMF2NoV0RegClassID, RISCV::ZZZ_VRMF8NoV0RegClassID, |
| 6358 | /* 417 ZZZ_VRMF8NoV0 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF4RegClassID, RISCV::ZZZ_VRMF8RegClassID, RISCV::VRNoV0RegClassID, RISCV::ZZZ_VMNoV0RegClassID, RISCV::ZZZ_VRMF2NoV0RegClassID, RISCV::ZZZ_VRMF4NoV0RegClassID, |
| 6359 | /* 426 YGPR_with_sub_cap_addr_in_GPRNoX0X2 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, |
| 6360 | /* 429 YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, |
| 6361 | /* 432 YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, |
| 6362 | /* 435 YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, |
| 6363 | /* 442 YGPR_with_sub_cap_addr_in_GPRJALR */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, |
| 6364 | /* 446 YGPR_with_sub_cap_addr_in_GPRJALRNonX7 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, |
| 6365 | /* 451 YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, |
| 6366 | /* 460 YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, |
| 6367 | /* 471 YGPR_with_sub_cap_addr_in_GPRTC */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, |
| 6368 | /* 476 YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTC */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRTCRegClassID, |
| 6369 | /* 487 YGPR_with_sub_cap_addr_in_GPRTCNonX7 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRTCRegClassID, |
| 6370 | /* 494 YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRTCRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRTCNonX7RegClassID, |
| 6371 | /* 509 FPR64C */ RISCV::FPR64RegClassID, |
| 6372 | /* 510 YGPR_with_sub_16_in_GPRF16C */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 6373 | /* 522 YGPR_with_sub_cap_addr_in_GPRS07 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31RegClassID, |
| 6374 | /* 534 YGPR_with_sub_cap_addr_in_GPRC_and_GPRTC */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRTCRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRTCNonX7RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7RegClassID, RISCV::YGPR_with_sub_16_in_GPRF16CRegClassID, |
| 6375 | /* 551 YGPR_with_sub_cap_addr_in_GPRC_and_GPRS07 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_16_in_GPRF16CRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRS07RegClassID, |
| 6376 | /* 565 YGPR_with_sub_cap_addr_in_GPRX1X5 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, |
| 6377 | /* 573 VMV0 */ RISCV::VRRegClassID, RISCV::ZZZ_VMRegClassID, RISCV::ZZZ_VRMF2RegClassID, RISCV::ZZZ_VRMF4RegClassID, RISCV::ZZZ_VRMF8RegClassID, |
| 6378 | /* 578 YGPR_with_sub_16_in_GPRF16X0 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, |
| 6379 | /* 582 YGPR_with_sub_cap_addr_in_GPRX1 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRX1X5RegClassID, |
| 6380 | /* 591 YGPR_with_sub_cap_addr_in_GPRX5 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRX1X5RegClassID, |
| 6381 | /* 600 YGPR_with_sub_cap_addr_in_GPRX7 */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRTCRegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCRegClassID, |
| 6382 | /* 612 YGPR_with_sub_cap_addr_in_SP */ RISCV::YGPRRegClassID, RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, |
| 6383 | /* 616 VRN2M1 */ |
| 6384 | /* 616 VRN2M1NoV0 */ RISCV::VRN2M1RegClassID, |
| 6385 | /* 617 VRM2 */ |
| 6386 | /* 617 VRM2NoV0 */ RISCV::VRM2RegClassID, |
| 6387 | /* 618 VRM2_with_sub_vrm1_0_in_VMV0 */ RISCV::VRM2RegClassID, |
| 6388 | /* 619 VRN2M1_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN2M1RegClassID, |
| 6389 | /* 620 FPR128 */ |
| 6390 | /* 620 FPR128_with_sub_16_in_FPR16C */ RISCV::FPR128RegClassID, |
| 6391 | /* 621 VRN3M1 */ |
| 6392 | /* 621 VRN3M1NoV0 */ RISCV::VRN3M1RegClassID, |
| 6393 | /* 622 VRN3M1_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN3M1RegClassID, |
| 6394 | /* 623 VRN4M1 */ |
| 6395 | /* 623 VRN4M1NoV0 */ RISCV::VRN4M1RegClassID, |
| 6396 | /* 624 VRN2M2 */ |
| 6397 | /* 624 VRN2M2NoV0 */ RISCV::VRN2M2RegClassID, |
| 6398 | /* 625 VRM4 */ |
| 6399 | /* 625 VRM4NoV0 */ RISCV::VRM4RegClassID, |
| 6400 | /* 626 VRM4_with_sub_vrm1_0_in_VMV0 */ RISCV::VRM4RegClassID, |
| 6401 | /* 627 VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN2M2RegClassID, |
| 6402 | /* 628 VRN4M1_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN4M1RegClassID, |
| 6403 | /* 629 FPR256 */ |
| 6404 | /* 629 FPR256_with_sub_16_in_FPR16C */ RISCV::FPR256RegClassID, |
| 6405 | /* 630 VRN5M1 */ |
| 6406 | /* 630 VRN5M1NoV0 */ RISCV::VRN5M1RegClassID, |
| 6407 | /* 631 VRN5M1_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN5M1RegClassID, |
| 6408 | /* 632 VRN6M1 */ |
| 6409 | /* 632 VRN6M1NoV0 */ RISCV::VRN6M1RegClassID, |
| 6410 | /* 633 VRN3M2 */ |
| 6411 | /* 633 VRN3M2NoV0 */ RISCV::VRN3M2RegClassID, |
| 6412 | /* 634 VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN3M2RegClassID, |
| 6413 | /* 635 VRN6M1_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN6M1RegClassID, |
| 6414 | /* 636 VRN7M1 */ |
| 6415 | /* 636 VRN7M1NoV0 */ RISCV::VRN7M1RegClassID, |
| 6416 | /* 637 VRN7M1_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN7M1RegClassID, |
| 6417 | /* 638 VRN8M1 */ |
| 6418 | /* 638 VRN8M1NoV0 */ RISCV::VRN8M1RegClassID, |
| 6419 | /* 639 VRN4M2 */ |
| 6420 | /* 639 VRN4M2NoV0 */ RISCV::VRN4M2RegClassID, |
| 6421 | /* 640 VRN2M4 */ |
| 6422 | /* 640 VRN2M4NoV0 */ RISCV::VRN2M4RegClassID, |
| 6423 | /* 641 VRM8 */ |
| 6424 | /* 641 VRM8NoV0 */ RISCV::VRM8RegClassID, |
| 6425 | /* 642 VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0 */ RISCV::VRM8RegClassID, |
| 6426 | /* 643 VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN2M4RegClassID, |
| 6427 | /* 644 VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN4M2RegClassID, |
| 6428 | /* 645 VRN8M1_with_sub_vrm1_0_in_VMV0 */ RISCV::VRN8M1RegClassID, |
| 6429 | } |
| 6430 | }; |
| 6431 | |
| 6432 | const MCRegisterClass &getRISCVMCRegisterClass(unsigned RC) { |
| 6433 | return RISCVMCRegisterClassStorage.Classes[RC]; |
| 6434 | } |
| 6435 | |
| 6436 | // RISCV Dwarf<->LLVM register mappings. |
| 6437 | extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[] = { |
| 6438 | { .FromReg: 0U, .ToReg: RISCV::X0 }, |
| 6439 | { .FromReg: 1U, .ToReg: RISCV::X1 }, |
| 6440 | { .FromReg: 2U, .ToReg: RISCV::X2 }, |
| 6441 | { .FromReg: 3U, .ToReg: RISCV::X3 }, |
| 6442 | { .FromReg: 4U, .ToReg: RISCV::X4 }, |
| 6443 | { .FromReg: 5U, .ToReg: RISCV::X5 }, |
| 6444 | { .FromReg: 6U, .ToReg: RISCV::X6 }, |
| 6445 | { .FromReg: 7U, .ToReg: RISCV::X7 }, |
| 6446 | { .FromReg: 8U, .ToReg: RISCV::X8 }, |
| 6447 | { .FromReg: 9U, .ToReg: RISCV::X9 }, |
| 6448 | { .FromReg: 10U, .ToReg: RISCV::X10 }, |
| 6449 | { .FromReg: 11U, .ToReg: RISCV::X11 }, |
| 6450 | { .FromReg: 12U, .ToReg: RISCV::X12 }, |
| 6451 | { .FromReg: 13U, .ToReg: RISCV::X13 }, |
| 6452 | { .FromReg: 14U, .ToReg: RISCV::X14 }, |
| 6453 | { .FromReg: 15U, .ToReg: RISCV::X15 }, |
| 6454 | { .FromReg: 16U, .ToReg: RISCV::X16 }, |
| 6455 | { .FromReg: 17U, .ToReg: RISCV::X17 }, |
| 6456 | { .FromReg: 18U, .ToReg: RISCV::X18 }, |
| 6457 | { .FromReg: 19U, .ToReg: RISCV::X19 }, |
| 6458 | { .FromReg: 20U, .ToReg: RISCV::X20 }, |
| 6459 | { .FromReg: 21U, .ToReg: RISCV::X21 }, |
| 6460 | { .FromReg: 22U, .ToReg: RISCV::X22 }, |
| 6461 | { .FromReg: 23U, .ToReg: RISCV::X23 }, |
| 6462 | { .FromReg: 24U, .ToReg: RISCV::X24 }, |
| 6463 | { .FromReg: 25U, .ToReg: RISCV::X25 }, |
| 6464 | { .FromReg: 26U, .ToReg: RISCV::X26 }, |
| 6465 | { .FromReg: 27U, .ToReg: RISCV::X27 }, |
| 6466 | { .FromReg: 28U, .ToReg: RISCV::X28 }, |
| 6467 | { .FromReg: 29U, .ToReg: RISCV::X29 }, |
| 6468 | { .FromReg: 30U, .ToReg: RISCV::X30 }, |
| 6469 | { .FromReg: 31U, .ToReg: RISCV::X31 }, |
| 6470 | { .FromReg: 32U, .ToReg: RISCV::F0_H }, |
| 6471 | { .FromReg: 33U, .ToReg: RISCV::F1_H }, |
| 6472 | { .FromReg: 34U, .ToReg: RISCV::F2_H }, |
| 6473 | { .FromReg: 35U, .ToReg: RISCV::F3_H }, |
| 6474 | { .FromReg: 36U, .ToReg: RISCV::F4_H }, |
| 6475 | { .FromReg: 37U, .ToReg: RISCV::F5_H }, |
| 6476 | { .FromReg: 38U, .ToReg: RISCV::F6_H }, |
| 6477 | { .FromReg: 39U, .ToReg: RISCV::F7_H }, |
| 6478 | { .FromReg: 40U, .ToReg: RISCV::F8_H }, |
| 6479 | { .FromReg: 41U, .ToReg: RISCV::F9_H }, |
| 6480 | { .FromReg: 42U, .ToReg: RISCV::F10_H }, |
| 6481 | { .FromReg: 43U, .ToReg: RISCV::F11_H }, |
| 6482 | { .FromReg: 44U, .ToReg: RISCV::F12_H }, |
| 6483 | { .FromReg: 45U, .ToReg: RISCV::F13_H }, |
| 6484 | { .FromReg: 46U, .ToReg: RISCV::F14_H }, |
| 6485 | { .FromReg: 47U, .ToReg: RISCV::F15_H }, |
| 6486 | { .FromReg: 48U, .ToReg: RISCV::F16_H }, |
| 6487 | { .FromReg: 49U, .ToReg: RISCV::F17_H }, |
| 6488 | { .FromReg: 50U, .ToReg: RISCV::F18_H }, |
| 6489 | { .FromReg: 51U, .ToReg: RISCV::F19_H }, |
| 6490 | { .FromReg: 52U, .ToReg: RISCV::F20_H }, |
| 6491 | { .FromReg: 53U, .ToReg: RISCV::F21_H }, |
| 6492 | { .FromReg: 54U, .ToReg: RISCV::F22_H }, |
| 6493 | { .FromReg: 55U, .ToReg: RISCV::F23_H }, |
| 6494 | { .FromReg: 56U, .ToReg: RISCV::F24_H }, |
| 6495 | { .FromReg: 57U, .ToReg: RISCV::F25_H }, |
| 6496 | { .FromReg: 58U, .ToReg: RISCV::F26_H }, |
| 6497 | { .FromReg: 59U, .ToReg: RISCV::F27_H }, |
| 6498 | { .FromReg: 60U, .ToReg: RISCV::F28_H }, |
| 6499 | { .FromReg: 61U, .ToReg: RISCV::F29_H }, |
| 6500 | { .FromReg: 62U, .ToReg: RISCV::F30_H }, |
| 6501 | { .FromReg: 63U, .ToReg: RISCV::F31_H }, |
| 6502 | { .FromReg: 96U, .ToReg: RISCV::V0 }, |
| 6503 | { .FromReg: 97U, .ToReg: RISCV::V1 }, |
| 6504 | { .FromReg: 98U, .ToReg: RISCV::V2 }, |
| 6505 | { .FromReg: 99U, .ToReg: RISCV::V3 }, |
| 6506 | { .FromReg: 100U, .ToReg: RISCV::V4 }, |
| 6507 | { .FromReg: 101U, .ToReg: RISCV::V5 }, |
| 6508 | { .FromReg: 102U, .ToReg: RISCV::V6 }, |
| 6509 | { .FromReg: 103U, .ToReg: RISCV::V7 }, |
| 6510 | { .FromReg: 104U, .ToReg: RISCV::V8 }, |
| 6511 | { .FromReg: 105U, .ToReg: RISCV::V9 }, |
| 6512 | { .FromReg: 106U, .ToReg: RISCV::V10 }, |
| 6513 | { .FromReg: 107U, .ToReg: RISCV::V11 }, |
| 6514 | { .FromReg: 108U, .ToReg: RISCV::V12 }, |
| 6515 | { .FromReg: 109U, .ToReg: RISCV::V13 }, |
| 6516 | { .FromReg: 110U, .ToReg: RISCV::V14 }, |
| 6517 | { .FromReg: 111U, .ToReg: RISCV::V15 }, |
| 6518 | { .FromReg: 112U, .ToReg: RISCV::V16 }, |
| 6519 | { .FromReg: 113U, .ToReg: RISCV::V17 }, |
| 6520 | { .FromReg: 114U, .ToReg: RISCV::V18 }, |
| 6521 | { .FromReg: 115U, .ToReg: RISCV::V19 }, |
| 6522 | { .FromReg: 116U, .ToReg: RISCV::V20 }, |
| 6523 | { .FromReg: 117U, .ToReg: RISCV::V21 }, |
| 6524 | { .FromReg: 118U, .ToReg: RISCV::V22 }, |
| 6525 | { .FromReg: 119U, .ToReg: RISCV::V23 }, |
| 6526 | { .FromReg: 120U, .ToReg: RISCV::V24 }, |
| 6527 | { .FromReg: 121U, .ToReg: RISCV::V25 }, |
| 6528 | { .FromReg: 122U, .ToReg: RISCV::V26 }, |
| 6529 | { .FromReg: 123U, .ToReg: RISCV::V27 }, |
| 6530 | { .FromReg: 124U, .ToReg: RISCV::V28 }, |
| 6531 | { .FromReg: 125U, .ToReg: RISCV::V29 }, |
| 6532 | { .FromReg: 126U, .ToReg: RISCV::V30 }, |
| 6533 | { .FromReg: 127U, .ToReg: RISCV::V31 }, |
| 6534 | { .FromReg: 3072U, .ToReg: RISCV::T0 }, |
| 6535 | { .FromReg: 3073U, .ToReg: RISCV::T1 }, |
| 6536 | { .FromReg: 3074U, .ToReg: RISCV::T2 }, |
| 6537 | { .FromReg: 3075U, .ToReg: RISCV::T3 }, |
| 6538 | { .FromReg: 3076U, .ToReg: RISCV::T4 }, |
| 6539 | { .FromReg: 3077U, .ToReg: RISCV::T5 }, |
| 6540 | { .FromReg: 3078U, .ToReg: RISCV::T6 }, |
| 6541 | { .FromReg: 3079U, .ToReg: RISCV::T7 }, |
| 6542 | { .FromReg: 3080U, .ToReg: RISCV::T8 }, |
| 6543 | { .FromReg: 3081U, .ToReg: RISCV::T9 }, |
| 6544 | { .FromReg: 3082U, .ToReg: RISCV::T10 }, |
| 6545 | { .FromReg: 3083U, .ToReg: RISCV::T11 }, |
| 6546 | { .FromReg: 3084U, .ToReg: RISCV::T12 }, |
| 6547 | { .FromReg: 3085U, .ToReg: RISCV::T13 }, |
| 6548 | { .FromReg: 3086U, .ToReg: RISCV::T14 }, |
| 6549 | { .FromReg: 3087U, .ToReg: RISCV::T15 }, |
| 6550 | { .FromReg: 3088U, .ToReg: RISCV::F0_Q2 }, |
| 6551 | { .FromReg: 3089U, .ToReg: RISCV::F1_Q2 }, |
| 6552 | { .FromReg: 3090U, .ToReg: RISCV::F2_Q2 }, |
| 6553 | { .FromReg: 3091U, .ToReg: RISCV::F3_Q2 }, |
| 6554 | { .FromReg: 3092U, .ToReg: RISCV::F4_Q2 }, |
| 6555 | { .FromReg: 3093U, .ToReg: RISCV::F5_Q2 }, |
| 6556 | { .FromReg: 3094U, .ToReg: RISCV::F6_Q2 }, |
| 6557 | { .FromReg: 3095U, .ToReg: RISCV::F7_Q2 }, |
| 6558 | { .FromReg: 3096U, .ToReg: RISCV::F8_Q2 }, |
| 6559 | { .FromReg: 3097U, .ToReg: RISCV::F9_Q2 }, |
| 6560 | { .FromReg: 3098U, .ToReg: RISCV::F10_Q2 }, |
| 6561 | { .FromReg: 3099U, .ToReg: RISCV::F11_Q2 }, |
| 6562 | { .FromReg: 3100U, .ToReg: RISCV::F12_Q2 }, |
| 6563 | { .FromReg: 3101U, .ToReg: RISCV::F13_Q2 }, |
| 6564 | { .FromReg: 3102U, .ToReg: RISCV::F14_Q2 }, |
| 6565 | { .FromReg: 3103U, .ToReg: RISCV::F15_Q2 }, |
| 6566 | { .FromReg: 3104U, .ToReg: RISCV::F16_Q2 }, |
| 6567 | { .FromReg: 3105U, .ToReg: RISCV::F17_Q2 }, |
| 6568 | { .FromReg: 3106U, .ToReg: RISCV::F18_Q2 }, |
| 6569 | { .FromReg: 3107U, .ToReg: RISCV::F19_Q2 }, |
| 6570 | { .FromReg: 3108U, .ToReg: RISCV::F20_Q2 }, |
| 6571 | { .FromReg: 3109U, .ToReg: RISCV::F21_Q2 }, |
| 6572 | { .FromReg: 3110U, .ToReg: RISCV::F22_Q2 }, |
| 6573 | { .FromReg: 3111U, .ToReg: RISCV::F23_Q2 }, |
| 6574 | { .FromReg: 3112U, .ToReg: RISCV::F24_Q2 }, |
| 6575 | { .FromReg: 3113U, .ToReg: RISCV::F25_Q2 }, |
| 6576 | { .FromReg: 3114U, .ToReg: RISCV::F26_Q2 }, |
| 6577 | { .FromReg: 3115U, .ToReg: RISCV::F27_Q2 }, |
| 6578 | { .FromReg: 3116U, .ToReg: RISCV::F28_Q2 }, |
| 6579 | { .FromReg: 3117U, .ToReg: RISCV::F29_Q2 }, |
| 6580 | { .FromReg: 3118U, .ToReg: RISCV::F30_Q2 }, |
| 6581 | { .FromReg: 3119U, .ToReg: RISCV::F31_Q2 }, |
| 6582 | { .FromReg: 4020U, .ToReg: RISCV::M0 }, |
| 6583 | { .FromReg: 4021U, .ToReg: RISCV::M1 }, |
| 6584 | { .FromReg: 4022U, .ToReg: RISCV::M2 }, |
| 6585 | { .FromReg: 4023U, .ToReg: RISCV::M3 }, |
| 6586 | { .FromReg: 4024U, .ToReg: RISCV::M4 }, |
| 6587 | { .FromReg: 4025U, .ToReg: RISCV::M5 }, |
| 6588 | { .FromReg: 4026U, .ToReg: RISCV::M6 }, |
| 6589 | { .FromReg: 4027U, .ToReg: RISCV::M7 }, |
| 6590 | { .FromReg: 7202U, .ToReg: RISCV::VLENB }, |
| 6591 | }; |
| 6592 | extern const unsigned RISCVDwarfFlavour0Dwarf2LSize = std::size(RISCVDwarfFlavour0Dwarf2L); |
| 6593 | |
| 6594 | extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[] = { |
| 6595 | { .FromReg: 0U, .ToReg: RISCV::X0 }, |
| 6596 | { .FromReg: 1U, .ToReg: RISCV::X1 }, |
| 6597 | { .FromReg: 2U, .ToReg: RISCV::X2 }, |
| 6598 | { .FromReg: 3U, .ToReg: RISCV::X3 }, |
| 6599 | { .FromReg: 4U, .ToReg: RISCV::X4 }, |
| 6600 | { .FromReg: 5U, .ToReg: RISCV::X5 }, |
| 6601 | { .FromReg: 6U, .ToReg: RISCV::X6 }, |
| 6602 | { .FromReg: 7U, .ToReg: RISCV::X7 }, |
| 6603 | { .FromReg: 8U, .ToReg: RISCV::X8 }, |
| 6604 | { .FromReg: 9U, .ToReg: RISCV::X9 }, |
| 6605 | { .FromReg: 10U, .ToReg: RISCV::X10 }, |
| 6606 | { .FromReg: 11U, .ToReg: RISCV::X11 }, |
| 6607 | { .FromReg: 12U, .ToReg: RISCV::X12 }, |
| 6608 | { .FromReg: 13U, .ToReg: RISCV::X13 }, |
| 6609 | { .FromReg: 14U, .ToReg: RISCV::X14 }, |
| 6610 | { .FromReg: 15U, .ToReg: RISCV::X15 }, |
| 6611 | { .FromReg: 16U, .ToReg: RISCV::X16 }, |
| 6612 | { .FromReg: 17U, .ToReg: RISCV::X17 }, |
| 6613 | { .FromReg: 18U, .ToReg: RISCV::X18 }, |
| 6614 | { .FromReg: 19U, .ToReg: RISCV::X19 }, |
| 6615 | { .FromReg: 20U, .ToReg: RISCV::X20 }, |
| 6616 | { .FromReg: 21U, .ToReg: RISCV::X21 }, |
| 6617 | { .FromReg: 22U, .ToReg: RISCV::X22 }, |
| 6618 | { .FromReg: 23U, .ToReg: RISCV::X23 }, |
| 6619 | { .FromReg: 24U, .ToReg: RISCV::X24 }, |
| 6620 | { .FromReg: 25U, .ToReg: RISCV::X25 }, |
| 6621 | { .FromReg: 26U, .ToReg: RISCV::X26 }, |
| 6622 | { .FromReg: 27U, .ToReg: RISCV::X27 }, |
| 6623 | { .FromReg: 28U, .ToReg: RISCV::X28 }, |
| 6624 | { .FromReg: 29U, .ToReg: RISCV::X29 }, |
| 6625 | { .FromReg: 30U, .ToReg: RISCV::X30 }, |
| 6626 | { .FromReg: 31U, .ToReg: RISCV::X31 }, |
| 6627 | { .FromReg: 32U, .ToReg: RISCV::F0_H }, |
| 6628 | { .FromReg: 33U, .ToReg: RISCV::F1_H }, |
| 6629 | { .FromReg: 34U, .ToReg: RISCV::F2_H }, |
| 6630 | { .FromReg: 35U, .ToReg: RISCV::F3_H }, |
| 6631 | { .FromReg: 36U, .ToReg: RISCV::F4_H }, |
| 6632 | { .FromReg: 37U, .ToReg: RISCV::F5_H }, |
| 6633 | { .FromReg: 38U, .ToReg: RISCV::F6_H }, |
| 6634 | { .FromReg: 39U, .ToReg: RISCV::F7_H }, |
| 6635 | { .FromReg: 40U, .ToReg: RISCV::F8_H }, |
| 6636 | { .FromReg: 41U, .ToReg: RISCV::F9_H }, |
| 6637 | { .FromReg: 42U, .ToReg: RISCV::F10_H }, |
| 6638 | { .FromReg: 43U, .ToReg: RISCV::F11_H }, |
| 6639 | { .FromReg: 44U, .ToReg: RISCV::F12_H }, |
| 6640 | { .FromReg: 45U, .ToReg: RISCV::F13_H }, |
| 6641 | { .FromReg: 46U, .ToReg: RISCV::F14_H }, |
| 6642 | { .FromReg: 47U, .ToReg: RISCV::F15_H }, |
| 6643 | { .FromReg: 48U, .ToReg: RISCV::F16_H }, |
| 6644 | { .FromReg: 49U, .ToReg: RISCV::F17_H }, |
| 6645 | { .FromReg: 50U, .ToReg: RISCV::F18_H }, |
| 6646 | { .FromReg: 51U, .ToReg: RISCV::F19_H }, |
| 6647 | { .FromReg: 52U, .ToReg: RISCV::F20_H }, |
| 6648 | { .FromReg: 53U, .ToReg: RISCV::F21_H }, |
| 6649 | { .FromReg: 54U, .ToReg: RISCV::F22_H }, |
| 6650 | { .FromReg: 55U, .ToReg: RISCV::F23_H }, |
| 6651 | { .FromReg: 56U, .ToReg: RISCV::F24_H }, |
| 6652 | { .FromReg: 57U, .ToReg: RISCV::F25_H }, |
| 6653 | { .FromReg: 58U, .ToReg: RISCV::F26_H }, |
| 6654 | { .FromReg: 59U, .ToReg: RISCV::F27_H }, |
| 6655 | { .FromReg: 60U, .ToReg: RISCV::F28_H }, |
| 6656 | { .FromReg: 61U, .ToReg: RISCV::F29_H }, |
| 6657 | { .FromReg: 62U, .ToReg: RISCV::F30_H }, |
| 6658 | { .FromReg: 63U, .ToReg: RISCV::F31_H }, |
| 6659 | { .FromReg: 96U, .ToReg: RISCV::V0 }, |
| 6660 | { .FromReg: 97U, .ToReg: RISCV::V1 }, |
| 6661 | { .FromReg: 98U, .ToReg: RISCV::V2 }, |
| 6662 | { .FromReg: 99U, .ToReg: RISCV::V3 }, |
| 6663 | { .FromReg: 100U, .ToReg: RISCV::V4 }, |
| 6664 | { .FromReg: 101U, .ToReg: RISCV::V5 }, |
| 6665 | { .FromReg: 102U, .ToReg: RISCV::V6 }, |
| 6666 | { .FromReg: 103U, .ToReg: RISCV::V7 }, |
| 6667 | { .FromReg: 104U, .ToReg: RISCV::V8 }, |
| 6668 | { .FromReg: 105U, .ToReg: RISCV::V9 }, |
| 6669 | { .FromReg: 106U, .ToReg: RISCV::V10 }, |
| 6670 | { .FromReg: 107U, .ToReg: RISCV::V11 }, |
| 6671 | { .FromReg: 108U, .ToReg: RISCV::V12 }, |
| 6672 | { .FromReg: 109U, .ToReg: RISCV::V13 }, |
| 6673 | { .FromReg: 110U, .ToReg: RISCV::V14 }, |
| 6674 | { .FromReg: 111U, .ToReg: RISCV::V15 }, |
| 6675 | { .FromReg: 112U, .ToReg: RISCV::V16 }, |
| 6676 | { .FromReg: 113U, .ToReg: RISCV::V17 }, |
| 6677 | { .FromReg: 114U, .ToReg: RISCV::V18 }, |
| 6678 | { .FromReg: 115U, .ToReg: RISCV::V19 }, |
| 6679 | { .FromReg: 116U, .ToReg: RISCV::V20 }, |
| 6680 | { .FromReg: 117U, .ToReg: RISCV::V21 }, |
| 6681 | { .FromReg: 118U, .ToReg: RISCV::V22 }, |
| 6682 | { .FromReg: 119U, .ToReg: RISCV::V23 }, |
| 6683 | { .FromReg: 120U, .ToReg: RISCV::V24 }, |
| 6684 | { .FromReg: 121U, .ToReg: RISCV::V25 }, |
| 6685 | { .FromReg: 122U, .ToReg: RISCV::V26 }, |
| 6686 | { .FromReg: 123U, .ToReg: RISCV::V27 }, |
| 6687 | { .FromReg: 124U, .ToReg: RISCV::V28 }, |
| 6688 | { .FromReg: 125U, .ToReg: RISCV::V29 }, |
| 6689 | { .FromReg: 126U, .ToReg: RISCV::V30 }, |
| 6690 | { .FromReg: 127U, .ToReg: RISCV::V31 }, |
| 6691 | { .FromReg: 3072U, .ToReg: RISCV::T0 }, |
| 6692 | { .FromReg: 3073U, .ToReg: RISCV::T1 }, |
| 6693 | { .FromReg: 3074U, .ToReg: RISCV::T2 }, |
| 6694 | { .FromReg: 3075U, .ToReg: RISCV::T3 }, |
| 6695 | { .FromReg: 3076U, .ToReg: RISCV::T4 }, |
| 6696 | { .FromReg: 3077U, .ToReg: RISCV::T5 }, |
| 6697 | { .FromReg: 3078U, .ToReg: RISCV::T6 }, |
| 6698 | { .FromReg: 3079U, .ToReg: RISCV::T7 }, |
| 6699 | { .FromReg: 3080U, .ToReg: RISCV::T8 }, |
| 6700 | { .FromReg: 3081U, .ToReg: RISCV::T9 }, |
| 6701 | { .FromReg: 3082U, .ToReg: RISCV::T10 }, |
| 6702 | { .FromReg: 3083U, .ToReg: RISCV::T11 }, |
| 6703 | { .FromReg: 3084U, .ToReg: RISCV::T12 }, |
| 6704 | { .FromReg: 3085U, .ToReg: RISCV::T13 }, |
| 6705 | { .FromReg: 3086U, .ToReg: RISCV::T14 }, |
| 6706 | { .FromReg: 3087U, .ToReg: RISCV::T15 }, |
| 6707 | { .FromReg: 3088U, .ToReg: RISCV::F0_Q2 }, |
| 6708 | { .FromReg: 3089U, .ToReg: RISCV::F1_Q2 }, |
| 6709 | { .FromReg: 3090U, .ToReg: RISCV::F2_Q2 }, |
| 6710 | { .FromReg: 3091U, .ToReg: RISCV::F3_Q2 }, |
| 6711 | { .FromReg: 3092U, .ToReg: RISCV::F4_Q2 }, |
| 6712 | { .FromReg: 3093U, .ToReg: RISCV::F5_Q2 }, |
| 6713 | { .FromReg: 3094U, .ToReg: RISCV::F6_Q2 }, |
| 6714 | { .FromReg: 3095U, .ToReg: RISCV::F7_Q2 }, |
| 6715 | { .FromReg: 3096U, .ToReg: RISCV::F8_Q2 }, |
| 6716 | { .FromReg: 3097U, .ToReg: RISCV::F9_Q2 }, |
| 6717 | { .FromReg: 3098U, .ToReg: RISCV::F10_Q2 }, |
| 6718 | { .FromReg: 3099U, .ToReg: RISCV::F11_Q2 }, |
| 6719 | { .FromReg: 3100U, .ToReg: RISCV::F12_Q2 }, |
| 6720 | { .FromReg: 3101U, .ToReg: RISCV::F13_Q2 }, |
| 6721 | { .FromReg: 3102U, .ToReg: RISCV::F14_Q2 }, |
| 6722 | { .FromReg: 3103U, .ToReg: RISCV::F15_Q2 }, |
| 6723 | { .FromReg: 3104U, .ToReg: RISCV::F16_Q2 }, |
| 6724 | { .FromReg: 3105U, .ToReg: RISCV::F17_Q2 }, |
| 6725 | { .FromReg: 3106U, .ToReg: RISCV::F18_Q2 }, |
| 6726 | { .FromReg: 3107U, .ToReg: RISCV::F19_Q2 }, |
| 6727 | { .FromReg: 3108U, .ToReg: RISCV::F20_Q2 }, |
| 6728 | { .FromReg: 3109U, .ToReg: RISCV::F21_Q2 }, |
| 6729 | { .FromReg: 3110U, .ToReg: RISCV::F22_Q2 }, |
| 6730 | { .FromReg: 3111U, .ToReg: RISCV::F23_Q2 }, |
| 6731 | { .FromReg: 3112U, .ToReg: RISCV::F24_Q2 }, |
| 6732 | { .FromReg: 3113U, .ToReg: RISCV::F25_Q2 }, |
| 6733 | { .FromReg: 3114U, .ToReg: RISCV::F26_Q2 }, |
| 6734 | { .FromReg: 3115U, .ToReg: RISCV::F27_Q2 }, |
| 6735 | { .FromReg: 3116U, .ToReg: RISCV::F28_Q2 }, |
| 6736 | { .FromReg: 3117U, .ToReg: RISCV::F29_Q2 }, |
| 6737 | { .FromReg: 3118U, .ToReg: RISCV::F30_Q2 }, |
| 6738 | { .FromReg: 3119U, .ToReg: RISCV::F31_Q2 }, |
| 6739 | { .FromReg: 4020U, .ToReg: RISCV::M0 }, |
| 6740 | { .FromReg: 4021U, .ToReg: RISCV::M1 }, |
| 6741 | { .FromReg: 4022U, .ToReg: RISCV::M2 }, |
| 6742 | { .FromReg: 4023U, .ToReg: RISCV::M3 }, |
| 6743 | { .FromReg: 4024U, .ToReg: RISCV::M4 }, |
| 6744 | { .FromReg: 4025U, .ToReg: RISCV::M5 }, |
| 6745 | { .FromReg: 4026U, .ToReg: RISCV::M6 }, |
| 6746 | { .FromReg: 4027U, .ToReg: RISCV::M7 }, |
| 6747 | { .FromReg: 7202U, .ToReg: RISCV::VLENB }, |
| 6748 | }; |
| 6749 | extern const unsigned RISCVEHFlavour0Dwarf2LSize = std::size(RISCVEHFlavour0Dwarf2L); |
| 6750 | |
| 6751 | extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[] = { |
| 6752 | { .FromReg: RISCV::VLENB, .ToReg: 7202U }, |
| 6753 | { .FromReg: RISCV::M0, .ToReg: 4020U }, |
| 6754 | { .FromReg: RISCV::M1, .ToReg: 4021U }, |
| 6755 | { .FromReg: RISCV::M2, .ToReg: 4022U }, |
| 6756 | { .FromReg: RISCV::M3, .ToReg: 4023U }, |
| 6757 | { .FromReg: RISCV::M4, .ToReg: 4024U }, |
| 6758 | { .FromReg: RISCV::M5, .ToReg: 4025U }, |
| 6759 | { .FromReg: RISCV::M6, .ToReg: 4026U }, |
| 6760 | { .FromReg: RISCV::M7, .ToReg: 4027U }, |
| 6761 | { .FromReg: RISCV::T0, .ToReg: 3072U }, |
| 6762 | { .FromReg: RISCV::T1, .ToReg: 3073U }, |
| 6763 | { .FromReg: RISCV::T2, .ToReg: 3074U }, |
| 6764 | { .FromReg: RISCV::T3, .ToReg: 3075U }, |
| 6765 | { .FromReg: RISCV::T4, .ToReg: 3076U }, |
| 6766 | { .FromReg: RISCV::T5, .ToReg: 3077U }, |
| 6767 | { .FromReg: RISCV::T6, .ToReg: 3078U }, |
| 6768 | { .FromReg: RISCV::T7, .ToReg: 3079U }, |
| 6769 | { .FromReg: RISCV::T8, .ToReg: 3080U }, |
| 6770 | { .FromReg: RISCV::T9, .ToReg: 3081U }, |
| 6771 | { .FromReg: RISCV::T10, .ToReg: 3082U }, |
| 6772 | { .FromReg: RISCV::T11, .ToReg: 3083U }, |
| 6773 | { .FromReg: RISCV::T12, .ToReg: 3084U }, |
| 6774 | { .FromReg: RISCV::T13, .ToReg: 3085U }, |
| 6775 | { .FromReg: RISCV::T14, .ToReg: 3086U }, |
| 6776 | { .FromReg: RISCV::T15, .ToReg: 3087U }, |
| 6777 | { .FromReg: RISCV::V0, .ToReg: 96U }, |
| 6778 | { .FromReg: RISCV::V1, .ToReg: 97U }, |
| 6779 | { .FromReg: RISCV::V2, .ToReg: 98U }, |
| 6780 | { .FromReg: RISCV::V3, .ToReg: 99U }, |
| 6781 | { .FromReg: RISCV::V4, .ToReg: 100U }, |
| 6782 | { .FromReg: RISCV::V5, .ToReg: 101U }, |
| 6783 | { .FromReg: RISCV::V6, .ToReg: 102U }, |
| 6784 | { .FromReg: RISCV::V7, .ToReg: 103U }, |
| 6785 | { .FromReg: RISCV::V8, .ToReg: 104U }, |
| 6786 | { .FromReg: RISCV::V9, .ToReg: 105U }, |
| 6787 | { .FromReg: RISCV::V10, .ToReg: 106U }, |
| 6788 | { .FromReg: RISCV::V11, .ToReg: 107U }, |
| 6789 | { .FromReg: RISCV::V12, .ToReg: 108U }, |
| 6790 | { .FromReg: RISCV::V13, .ToReg: 109U }, |
| 6791 | { .FromReg: RISCV::V14, .ToReg: 110U }, |
| 6792 | { .FromReg: RISCV::V15, .ToReg: 111U }, |
| 6793 | { .FromReg: RISCV::V16, .ToReg: 112U }, |
| 6794 | { .FromReg: RISCV::V17, .ToReg: 113U }, |
| 6795 | { .FromReg: RISCV::V18, .ToReg: 114U }, |
| 6796 | { .FromReg: RISCV::V19, .ToReg: 115U }, |
| 6797 | { .FromReg: RISCV::V20, .ToReg: 116U }, |
| 6798 | { .FromReg: RISCV::V21, .ToReg: 117U }, |
| 6799 | { .FromReg: RISCV::V22, .ToReg: 118U }, |
| 6800 | { .FromReg: RISCV::V23, .ToReg: 119U }, |
| 6801 | { .FromReg: RISCV::V24, .ToReg: 120U }, |
| 6802 | { .FromReg: RISCV::V25, .ToReg: 121U }, |
| 6803 | { .FromReg: RISCV::V26, .ToReg: 122U }, |
| 6804 | { .FromReg: RISCV::V27, .ToReg: 123U }, |
| 6805 | { .FromReg: RISCV::V28, .ToReg: 124U }, |
| 6806 | { .FromReg: RISCV::V29, .ToReg: 125U }, |
| 6807 | { .FromReg: RISCV::V30, .ToReg: 126U }, |
| 6808 | { .FromReg: RISCV::V31, .ToReg: 127U }, |
| 6809 | { .FromReg: RISCV::X0, .ToReg: 0U }, |
| 6810 | { .FromReg: RISCV::X1, .ToReg: 1U }, |
| 6811 | { .FromReg: RISCV::X2, .ToReg: 2U }, |
| 6812 | { .FromReg: RISCV::X3, .ToReg: 3U }, |
| 6813 | { .FromReg: RISCV::X4, .ToReg: 4U }, |
| 6814 | { .FromReg: RISCV::X5, .ToReg: 5U }, |
| 6815 | { .FromReg: RISCV::X6, .ToReg: 6U }, |
| 6816 | { .FromReg: RISCV::X7, .ToReg: 7U }, |
| 6817 | { .FromReg: RISCV::X8, .ToReg: 8U }, |
| 6818 | { .FromReg: RISCV::X9, .ToReg: 9U }, |
| 6819 | { .FromReg: RISCV::X10, .ToReg: 10U }, |
| 6820 | { .FromReg: RISCV::X11, .ToReg: 11U }, |
| 6821 | { .FromReg: RISCV::X12, .ToReg: 12U }, |
| 6822 | { .FromReg: RISCV::X13, .ToReg: 13U }, |
| 6823 | { .FromReg: RISCV::X14, .ToReg: 14U }, |
| 6824 | { .FromReg: RISCV::X15, .ToReg: 15U }, |
| 6825 | { .FromReg: RISCV::X16, .ToReg: 16U }, |
| 6826 | { .FromReg: RISCV::X17, .ToReg: 17U }, |
| 6827 | { .FromReg: RISCV::X18, .ToReg: 18U }, |
| 6828 | { .FromReg: RISCV::X19, .ToReg: 19U }, |
| 6829 | { .FromReg: RISCV::X20, .ToReg: 20U }, |
| 6830 | { .FromReg: RISCV::X21, .ToReg: 21U }, |
| 6831 | { .FromReg: RISCV::X22, .ToReg: 22U }, |
| 6832 | { .FromReg: RISCV::X23, .ToReg: 23U }, |
| 6833 | { .FromReg: RISCV::X24, .ToReg: 24U }, |
| 6834 | { .FromReg: RISCV::X25, .ToReg: 25U }, |
| 6835 | { .FromReg: RISCV::X26, .ToReg: 26U }, |
| 6836 | { .FromReg: RISCV::X27, .ToReg: 27U }, |
| 6837 | { .FromReg: RISCV::X28, .ToReg: 28U }, |
| 6838 | { .FromReg: RISCV::X29, .ToReg: 29U }, |
| 6839 | { .FromReg: RISCV::X30, .ToReg: 30U }, |
| 6840 | { .FromReg: RISCV::X31, .ToReg: 31U }, |
| 6841 | { .FromReg: RISCV::F0_D, .ToReg: 32U }, |
| 6842 | { .FromReg: RISCV::F1_D, .ToReg: 33U }, |
| 6843 | { .FromReg: RISCV::F2_D, .ToReg: 34U }, |
| 6844 | { .FromReg: RISCV::F3_D, .ToReg: 35U }, |
| 6845 | { .FromReg: RISCV::F4_D, .ToReg: 36U }, |
| 6846 | { .FromReg: RISCV::F5_D, .ToReg: 37U }, |
| 6847 | { .FromReg: RISCV::F6_D, .ToReg: 38U }, |
| 6848 | { .FromReg: RISCV::F7_D, .ToReg: 39U }, |
| 6849 | { .FromReg: RISCV::F8_D, .ToReg: 40U }, |
| 6850 | { .FromReg: RISCV::F9_D, .ToReg: 41U }, |
| 6851 | { .FromReg: RISCV::F10_D, .ToReg: 42U }, |
| 6852 | { .FromReg: RISCV::F11_D, .ToReg: 43U }, |
| 6853 | { .FromReg: RISCV::F12_D, .ToReg: 44U }, |
| 6854 | { .FromReg: RISCV::F13_D, .ToReg: 45U }, |
| 6855 | { .FromReg: RISCV::F14_D, .ToReg: 46U }, |
| 6856 | { .FromReg: RISCV::F15_D, .ToReg: 47U }, |
| 6857 | { .FromReg: RISCV::F16_D, .ToReg: 48U }, |
| 6858 | { .FromReg: RISCV::F17_D, .ToReg: 49U }, |
| 6859 | { .FromReg: RISCV::F18_D, .ToReg: 50U }, |
| 6860 | { .FromReg: RISCV::F19_D, .ToReg: 51U }, |
| 6861 | { .FromReg: RISCV::F20_D, .ToReg: 52U }, |
| 6862 | { .FromReg: RISCV::F21_D, .ToReg: 53U }, |
| 6863 | { .FromReg: RISCV::F22_D, .ToReg: 54U }, |
| 6864 | { .FromReg: RISCV::F23_D, .ToReg: 55U }, |
| 6865 | { .FromReg: RISCV::F24_D, .ToReg: 56U }, |
| 6866 | { .FromReg: RISCV::F25_D, .ToReg: 57U }, |
| 6867 | { .FromReg: RISCV::F26_D, .ToReg: 58U }, |
| 6868 | { .FromReg: RISCV::F27_D, .ToReg: 59U }, |
| 6869 | { .FromReg: RISCV::F28_D, .ToReg: 60U }, |
| 6870 | { .FromReg: RISCV::F29_D, .ToReg: 61U }, |
| 6871 | { .FromReg: RISCV::F30_D, .ToReg: 62U }, |
| 6872 | { .FromReg: RISCV::F31_D, .ToReg: 63U }, |
| 6873 | { .FromReg: RISCV::F0_F, .ToReg: 32U }, |
| 6874 | { .FromReg: RISCV::F1_F, .ToReg: 33U }, |
| 6875 | { .FromReg: RISCV::F2_F, .ToReg: 34U }, |
| 6876 | { .FromReg: RISCV::F3_F, .ToReg: 35U }, |
| 6877 | { .FromReg: RISCV::F4_F, .ToReg: 36U }, |
| 6878 | { .FromReg: RISCV::F5_F, .ToReg: 37U }, |
| 6879 | { .FromReg: RISCV::F6_F, .ToReg: 38U }, |
| 6880 | { .FromReg: RISCV::F7_F, .ToReg: 39U }, |
| 6881 | { .FromReg: RISCV::F8_F, .ToReg: 40U }, |
| 6882 | { .FromReg: RISCV::F9_F, .ToReg: 41U }, |
| 6883 | { .FromReg: RISCV::F10_F, .ToReg: 42U }, |
| 6884 | { .FromReg: RISCV::F11_F, .ToReg: 43U }, |
| 6885 | { .FromReg: RISCV::F12_F, .ToReg: 44U }, |
| 6886 | { .FromReg: RISCV::F13_F, .ToReg: 45U }, |
| 6887 | { .FromReg: RISCV::F14_F, .ToReg: 46U }, |
| 6888 | { .FromReg: RISCV::F15_F, .ToReg: 47U }, |
| 6889 | { .FromReg: RISCV::F16_F, .ToReg: 48U }, |
| 6890 | { .FromReg: RISCV::F17_F, .ToReg: 49U }, |
| 6891 | { .FromReg: RISCV::F18_F, .ToReg: 50U }, |
| 6892 | { .FromReg: RISCV::F19_F, .ToReg: 51U }, |
| 6893 | { .FromReg: RISCV::F20_F, .ToReg: 52U }, |
| 6894 | { .FromReg: RISCV::F21_F, .ToReg: 53U }, |
| 6895 | { .FromReg: RISCV::F22_F, .ToReg: 54U }, |
| 6896 | { .FromReg: RISCV::F23_F, .ToReg: 55U }, |
| 6897 | { .FromReg: RISCV::F24_F, .ToReg: 56U }, |
| 6898 | { .FromReg: RISCV::F25_F, .ToReg: 57U }, |
| 6899 | { .FromReg: RISCV::F26_F, .ToReg: 58U }, |
| 6900 | { .FromReg: RISCV::F27_F, .ToReg: 59U }, |
| 6901 | { .FromReg: RISCV::F28_F, .ToReg: 60U }, |
| 6902 | { .FromReg: RISCV::F29_F, .ToReg: 61U }, |
| 6903 | { .FromReg: RISCV::F30_F, .ToReg: 62U }, |
| 6904 | { .FromReg: RISCV::F31_F, .ToReg: 63U }, |
| 6905 | { .FromReg: RISCV::F0_H, .ToReg: 32U }, |
| 6906 | { .FromReg: RISCV::F1_H, .ToReg: 33U }, |
| 6907 | { .FromReg: RISCV::F2_H, .ToReg: 34U }, |
| 6908 | { .FromReg: RISCV::F3_H, .ToReg: 35U }, |
| 6909 | { .FromReg: RISCV::F4_H, .ToReg: 36U }, |
| 6910 | { .FromReg: RISCV::F5_H, .ToReg: 37U }, |
| 6911 | { .FromReg: RISCV::F6_H, .ToReg: 38U }, |
| 6912 | { .FromReg: RISCV::F7_H, .ToReg: 39U }, |
| 6913 | { .FromReg: RISCV::F8_H, .ToReg: 40U }, |
| 6914 | { .FromReg: RISCV::F9_H, .ToReg: 41U }, |
| 6915 | { .FromReg: RISCV::F10_H, .ToReg: 42U }, |
| 6916 | { .FromReg: RISCV::F11_H, .ToReg: 43U }, |
| 6917 | { .FromReg: RISCV::F12_H, .ToReg: 44U }, |
| 6918 | { .FromReg: RISCV::F13_H, .ToReg: 45U }, |
| 6919 | { .FromReg: RISCV::F14_H, .ToReg: 46U }, |
| 6920 | { .FromReg: RISCV::F15_H, .ToReg: 47U }, |
| 6921 | { .FromReg: RISCV::F16_H, .ToReg: 48U }, |
| 6922 | { .FromReg: RISCV::F17_H, .ToReg: 49U }, |
| 6923 | { .FromReg: RISCV::F18_H, .ToReg: 50U }, |
| 6924 | { .FromReg: RISCV::F19_H, .ToReg: 51U }, |
| 6925 | { .FromReg: RISCV::F20_H, .ToReg: 52U }, |
| 6926 | { .FromReg: RISCV::F21_H, .ToReg: 53U }, |
| 6927 | { .FromReg: RISCV::F22_H, .ToReg: 54U }, |
| 6928 | { .FromReg: RISCV::F23_H, .ToReg: 55U }, |
| 6929 | { .FromReg: RISCV::F24_H, .ToReg: 56U }, |
| 6930 | { .FromReg: RISCV::F25_H, .ToReg: 57U }, |
| 6931 | { .FromReg: RISCV::F26_H, .ToReg: 58U }, |
| 6932 | { .FromReg: RISCV::F27_H, .ToReg: 59U }, |
| 6933 | { .FromReg: RISCV::F28_H, .ToReg: 60U }, |
| 6934 | { .FromReg: RISCV::F29_H, .ToReg: 61U }, |
| 6935 | { .FromReg: RISCV::F30_H, .ToReg: 62U }, |
| 6936 | { .FromReg: RISCV::F31_H, .ToReg: 63U }, |
| 6937 | { .FromReg: RISCV::F0_Q, .ToReg: 32U }, |
| 6938 | { .FromReg: RISCV::F1_Q, .ToReg: 33U }, |
| 6939 | { .FromReg: RISCV::F2_Q, .ToReg: 34U }, |
| 6940 | { .FromReg: RISCV::F3_Q, .ToReg: 35U }, |
| 6941 | { .FromReg: RISCV::F4_Q, .ToReg: 36U }, |
| 6942 | { .FromReg: RISCV::F5_Q, .ToReg: 37U }, |
| 6943 | { .FromReg: RISCV::F6_Q, .ToReg: 38U }, |
| 6944 | { .FromReg: RISCV::F7_Q, .ToReg: 39U }, |
| 6945 | { .FromReg: RISCV::F8_Q, .ToReg: 40U }, |
| 6946 | { .FromReg: RISCV::F9_Q, .ToReg: 41U }, |
| 6947 | { .FromReg: RISCV::F10_Q, .ToReg: 42U }, |
| 6948 | { .FromReg: RISCV::F11_Q, .ToReg: 43U }, |
| 6949 | { .FromReg: RISCV::F12_Q, .ToReg: 44U }, |
| 6950 | { .FromReg: RISCV::F13_Q, .ToReg: 45U }, |
| 6951 | { .FromReg: RISCV::F14_Q, .ToReg: 46U }, |
| 6952 | { .FromReg: RISCV::F15_Q, .ToReg: 47U }, |
| 6953 | { .FromReg: RISCV::F16_Q, .ToReg: 48U }, |
| 6954 | { .FromReg: RISCV::F17_Q, .ToReg: 49U }, |
| 6955 | { .FromReg: RISCV::F18_Q, .ToReg: 50U }, |
| 6956 | { .FromReg: RISCV::F19_Q, .ToReg: 51U }, |
| 6957 | { .FromReg: RISCV::F20_Q, .ToReg: 52U }, |
| 6958 | { .FromReg: RISCV::F21_Q, .ToReg: 53U }, |
| 6959 | { .FromReg: RISCV::F22_Q, .ToReg: 54U }, |
| 6960 | { .FromReg: RISCV::F23_Q, .ToReg: 55U }, |
| 6961 | { .FromReg: RISCV::F24_Q, .ToReg: 56U }, |
| 6962 | { .FromReg: RISCV::F25_Q, .ToReg: 57U }, |
| 6963 | { .FromReg: RISCV::F26_Q, .ToReg: 58U }, |
| 6964 | { .FromReg: RISCV::F27_Q, .ToReg: 59U }, |
| 6965 | { .FromReg: RISCV::F28_Q, .ToReg: 60U }, |
| 6966 | { .FromReg: RISCV::F29_Q, .ToReg: 61U }, |
| 6967 | { .FromReg: RISCV::F30_Q, .ToReg: 62U }, |
| 6968 | { .FromReg: RISCV::F31_Q, .ToReg: 63U }, |
| 6969 | { .FromReg: RISCV::X0_Y, .ToReg: 0U }, |
| 6970 | { .FromReg: RISCV::X1_Y, .ToReg: 1U }, |
| 6971 | { .FromReg: RISCV::X2_Y, .ToReg: 2U }, |
| 6972 | { .FromReg: RISCV::X3_Y, .ToReg: 3U }, |
| 6973 | { .FromReg: RISCV::X4_Y, .ToReg: 4U }, |
| 6974 | { .FromReg: RISCV::X5_Y, .ToReg: 5U }, |
| 6975 | { .FromReg: RISCV::X6_Y, .ToReg: 6U }, |
| 6976 | { .FromReg: RISCV::X7_Y, .ToReg: 7U }, |
| 6977 | { .FromReg: RISCV::X8_Y, .ToReg: 8U }, |
| 6978 | { .FromReg: RISCV::X9_Y, .ToReg: 9U }, |
| 6979 | { .FromReg: RISCV::X10_Y, .ToReg: 10U }, |
| 6980 | { .FromReg: RISCV::X11_Y, .ToReg: 11U }, |
| 6981 | { .FromReg: RISCV::X12_Y, .ToReg: 12U }, |
| 6982 | { .FromReg: RISCV::X13_Y, .ToReg: 13U }, |
| 6983 | { .FromReg: RISCV::X14_Y, .ToReg: 14U }, |
| 6984 | { .FromReg: RISCV::X15_Y, .ToReg: 15U }, |
| 6985 | { .FromReg: RISCV::X16_Y, .ToReg: 16U }, |
| 6986 | { .FromReg: RISCV::X17_Y, .ToReg: 17U }, |
| 6987 | { .FromReg: RISCV::X18_Y, .ToReg: 18U }, |
| 6988 | { .FromReg: RISCV::X19_Y, .ToReg: 19U }, |
| 6989 | { .FromReg: RISCV::X20_Y, .ToReg: 20U }, |
| 6990 | { .FromReg: RISCV::X21_Y, .ToReg: 21U }, |
| 6991 | { .FromReg: RISCV::X22_Y, .ToReg: 22U }, |
| 6992 | { .FromReg: RISCV::X23_Y, .ToReg: 23U }, |
| 6993 | { .FromReg: RISCV::X24_Y, .ToReg: 24U }, |
| 6994 | { .FromReg: RISCV::X25_Y, .ToReg: 25U }, |
| 6995 | { .FromReg: RISCV::X26_Y, .ToReg: 26U }, |
| 6996 | { .FromReg: RISCV::X27_Y, .ToReg: 27U }, |
| 6997 | { .FromReg: RISCV::X28_Y, .ToReg: 28U }, |
| 6998 | { .FromReg: RISCV::X29_Y, .ToReg: 29U }, |
| 6999 | { .FromReg: RISCV::X30_Y, .ToReg: 30U }, |
| 7000 | { .FromReg: RISCV::X31_Y, .ToReg: 31U }, |
| 7001 | { .FromReg: RISCV::F0_Q2, .ToReg: 3088U }, |
| 7002 | { .FromReg: RISCV::F1_Q2, .ToReg: 3089U }, |
| 7003 | { .FromReg: RISCV::F2_Q2, .ToReg: 3090U }, |
| 7004 | { .FromReg: RISCV::F3_Q2, .ToReg: 3091U }, |
| 7005 | { .FromReg: RISCV::F4_Q2, .ToReg: 3092U }, |
| 7006 | { .FromReg: RISCV::F5_Q2, .ToReg: 3093U }, |
| 7007 | { .FromReg: RISCV::F6_Q2, .ToReg: 3094U }, |
| 7008 | { .FromReg: RISCV::F7_Q2, .ToReg: 3095U }, |
| 7009 | { .FromReg: RISCV::F8_Q2, .ToReg: 3096U }, |
| 7010 | { .FromReg: RISCV::F9_Q2, .ToReg: 3097U }, |
| 7011 | { .FromReg: RISCV::F10_Q2, .ToReg: 3098U }, |
| 7012 | { .FromReg: RISCV::F11_Q2, .ToReg: 3099U }, |
| 7013 | { .FromReg: RISCV::F12_Q2, .ToReg: 3100U }, |
| 7014 | { .FromReg: RISCV::F13_Q2, .ToReg: 3101U }, |
| 7015 | { .FromReg: RISCV::F14_Q2, .ToReg: 3102U }, |
| 7016 | { .FromReg: RISCV::F15_Q2, .ToReg: 3103U }, |
| 7017 | { .FromReg: RISCV::F16_Q2, .ToReg: 3104U }, |
| 7018 | { .FromReg: RISCV::F17_Q2, .ToReg: 3105U }, |
| 7019 | { .FromReg: RISCV::F18_Q2, .ToReg: 3106U }, |
| 7020 | { .FromReg: RISCV::F19_Q2, .ToReg: 3107U }, |
| 7021 | { .FromReg: RISCV::F20_Q2, .ToReg: 3108U }, |
| 7022 | { .FromReg: RISCV::F21_Q2, .ToReg: 3109U }, |
| 7023 | { .FromReg: RISCV::F22_Q2, .ToReg: 3110U }, |
| 7024 | { .FromReg: RISCV::F23_Q2, .ToReg: 3111U }, |
| 7025 | { .FromReg: RISCV::F24_Q2, .ToReg: 3112U }, |
| 7026 | { .FromReg: RISCV::F25_Q2, .ToReg: 3113U }, |
| 7027 | { .FromReg: RISCV::F26_Q2, .ToReg: 3114U }, |
| 7028 | { .FromReg: RISCV::F27_Q2, .ToReg: 3115U }, |
| 7029 | { .FromReg: RISCV::F28_Q2, .ToReg: 3116U }, |
| 7030 | { .FromReg: RISCV::F29_Q2, .ToReg: 3117U }, |
| 7031 | { .FromReg: RISCV::F30_Q2, .ToReg: 3118U }, |
| 7032 | { .FromReg: RISCV::F31_Q2, .ToReg: 3119U }, |
| 7033 | { .FromReg: RISCV::V0M2, .ToReg: 96U }, |
| 7034 | { .FromReg: RISCV::V0M4, .ToReg: 96U }, |
| 7035 | { .FromReg: RISCV::V0M8, .ToReg: 96U }, |
| 7036 | { .FromReg: RISCV::V2M2, .ToReg: 98U }, |
| 7037 | { .FromReg: RISCV::V4M2, .ToReg: 100U }, |
| 7038 | { .FromReg: RISCV::V4M4, .ToReg: 100U }, |
| 7039 | { .FromReg: RISCV::V6M2, .ToReg: 102U }, |
| 7040 | { .FromReg: RISCV::V8M2, .ToReg: 104U }, |
| 7041 | { .FromReg: RISCV::V8M4, .ToReg: 104U }, |
| 7042 | { .FromReg: RISCV::V8M8, .ToReg: 104U }, |
| 7043 | { .FromReg: RISCV::V10M2, .ToReg: 106U }, |
| 7044 | { .FromReg: RISCV::V12M2, .ToReg: 108U }, |
| 7045 | { .FromReg: RISCV::V12M4, .ToReg: 108U }, |
| 7046 | { .FromReg: RISCV::V14M2, .ToReg: 110U }, |
| 7047 | { .FromReg: RISCV::V16M2, .ToReg: 112U }, |
| 7048 | { .FromReg: RISCV::V16M4, .ToReg: 112U }, |
| 7049 | { .FromReg: RISCV::V16M8, .ToReg: 112U }, |
| 7050 | { .FromReg: RISCV::V18M2, .ToReg: 114U }, |
| 7051 | { .FromReg: RISCV::V20M2, .ToReg: 116U }, |
| 7052 | { .FromReg: RISCV::V20M4, .ToReg: 116U }, |
| 7053 | { .FromReg: RISCV::V22M2, .ToReg: 118U }, |
| 7054 | { .FromReg: RISCV::V24M2, .ToReg: 120U }, |
| 7055 | { .FromReg: RISCV::V24M4, .ToReg: 120U }, |
| 7056 | { .FromReg: RISCV::V24M8, .ToReg: 120U }, |
| 7057 | { .FromReg: RISCV::V26M2, .ToReg: 122U }, |
| 7058 | { .FromReg: RISCV::V28M2, .ToReg: 124U }, |
| 7059 | { .FromReg: RISCV::V28M4, .ToReg: 124U }, |
| 7060 | { .FromReg: RISCV::V30M2, .ToReg: 126U }, |
| 7061 | }; |
| 7062 | extern const unsigned RISCVDwarfFlavour0L2DwarfSize = std::size(RISCVDwarfFlavour0L2Dwarf); |
| 7063 | |
| 7064 | extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[] = { |
| 7065 | { .FromReg: RISCV::VLENB, .ToReg: 7202U }, |
| 7066 | { .FromReg: RISCV::M0, .ToReg: 4020U }, |
| 7067 | { .FromReg: RISCV::M1, .ToReg: 4021U }, |
| 7068 | { .FromReg: RISCV::M2, .ToReg: 4022U }, |
| 7069 | { .FromReg: RISCV::M3, .ToReg: 4023U }, |
| 7070 | { .FromReg: RISCV::M4, .ToReg: 4024U }, |
| 7071 | { .FromReg: RISCV::M5, .ToReg: 4025U }, |
| 7072 | { .FromReg: RISCV::M6, .ToReg: 4026U }, |
| 7073 | { .FromReg: RISCV::M7, .ToReg: 4027U }, |
| 7074 | { .FromReg: RISCV::T0, .ToReg: 3072U }, |
| 7075 | { .FromReg: RISCV::T1, .ToReg: 3073U }, |
| 7076 | { .FromReg: RISCV::T2, .ToReg: 3074U }, |
| 7077 | { .FromReg: RISCV::T3, .ToReg: 3075U }, |
| 7078 | { .FromReg: RISCV::T4, .ToReg: 3076U }, |
| 7079 | { .FromReg: RISCV::T5, .ToReg: 3077U }, |
| 7080 | { .FromReg: RISCV::T6, .ToReg: 3078U }, |
| 7081 | { .FromReg: RISCV::T7, .ToReg: 3079U }, |
| 7082 | { .FromReg: RISCV::T8, .ToReg: 3080U }, |
| 7083 | { .FromReg: RISCV::T9, .ToReg: 3081U }, |
| 7084 | { .FromReg: RISCV::T10, .ToReg: 3082U }, |
| 7085 | { .FromReg: RISCV::T11, .ToReg: 3083U }, |
| 7086 | { .FromReg: RISCV::T12, .ToReg: 3084U }, |
| 7087 | { .FromReg: RISCV::T13, .ToReg: 3085U }, |
| 7088 | { .FromReg: RISCV::T14, .ToReg: 3086U }, |
| 7089 | { .FromReg: RISCV::T15, .ToReg: 3087U }, |
| 7090 | { .FromReg: RISCV::V0, .ToReg: 96U }, |
| 7091 | { .FromReg: RISCV::V1, .ToReg: 97U }, |
| 7092 | { .FromReg: RISCV::V2, .ToReg: 98U }, |
| 7093 | { .FromReg: RISCV::V3, .ToReg: 99U }, |
| 7094 | { .FromReg: RISCV::V4, .ToReg: 100U }, |
| 7095 | { .FromReg: RISCV::V5, .ToReg: 101U }, |
| 7096 | { .FromReg: RISCV::V6, .ToReg: 102U }, |
| 7097 | { .FromReg: RISCV::V7, .ToReg: 103U }, |
| 7098 | { .FromReg: RISCV::V8, .ToReg: 104U }, |
| 7099 | { .FromReg: RISCV::V9, .ToReg: 105U }, |
| 7100 | { .FromReg: RISCV::V10, .ToReg: 106U }, |
| 7101 | { .FromReg: RISCV::V11, .ToReg: 107U }, |
| 7102 | { .FromReg: RISCV::V12, .ToReg: 108U }, |
| 7103 | { .FromReg: RISCV::V13, .ToReg: 109U }, |
| 7104 | { .FromReg: RISCV::V14, .ToReg: 110U }, |
| 7105 | { .FromReg: RISCV::V15, .ToReg: 111U }, |
| 7106 | { .FromReg: RISCV::V16, .ToReg: 112U }, |
| 7107 | { .FromReg: RISCV::V17, .ToReg: 113U }, |
| 7108 | { .FromReg: RISCV::V18, .ToReg: 114U }, |
| 7109 | { .FromReg: RISCV::V19, .ToReg: 115U }, |
| 7110 | { .FromReg: RISCV::V20, .ToReg: 116U }, |
| 7111 | { .FromReg: RISCV::V21, .ToReg: 117U }, |
| 7112 | { .FromReg: RISCV::V22, .ToReg: 118U }, |
| 7113 | { .FromReg: RISCV::V23, .ToReg: 119U }, |
| 7114 | { .FromReg: RISCV::V24, .ToReg: 120U }, |
| 7115 | { .FromReg: RISCV::V25, .ToReg: 121U }, |
| 7116 | { .FromReg: RISCV::V26, .ToReg: 122U }, |
| 7117 | { .FromReg: RISCV::V27, .ToReg: 123U }, |
| 7118 | { .FromReg: RISCV::V28, .ToReg: 124U }, |
| 7119 | { .FromReg: RISCV::V29, .ToReg: 125U }, |
| 7120 | { .FromReg: RISCV::V30, .ToReg: 126U }, |
| 7121 | { .FromReg: RISCV::V31, .ToReg: 127U }, |
| 7122 | { .FromReg: RISCV::X0, .ToReg: 0U }, |
| 7123 | { .FromReg: RISCV::X1, .ToReg: 1U }, |
| 7124 | { .FromReg: RISCV::X2, .ToReg: 2U }, |
| 7125 | { .FromReg: RISCV::X3, .ToReg: 3U }, |
| 7126 | { .FromReg: RISCV::X4, .ToReg: 4U }, |
| 7127 | { .FromReg: RISCV::X5, .ToReg: 5U }, |
| 7128 | { .FromReg: RISCV::X6, .ToReg: 6U }, |
| 7129 | { .FromReg: RISCV::X7, .ToReg: 7U }, |
| 7130 | { .FromReg: RISCV::X8, .ToReg: 8U }, |
| 7131 | { .FromReg: RISCV::X9, .ToReg: 9U }, |
| 7132 | { .FromReg: RISCV::X10, .ToReg: 10U }, |
| 7133 | { .FromReg: RISCV::X11, .ToReg: 11U }, |
| 7134 | { .FromReg: RISCV::X12, .ToReg: 12U }, |
| 7135 | { .FromReg: RISCV::X13, .ToReg: 13U }, |
| 7136 | { .FromReg: RISCV::X14, .ToReg: 14U }, |
| 7137 | { .FromReg: RISCV::X15, .ToReg: 15U }, |
| 7138 | { .FromReg: RISCV::X16, .ToReg: 16U }, |
| 7139 | { .FromReg: RISCV::X17, .ToReg: 17U }, |
| 7140 | { .FromReg: RISCV::X18, .ToReg: 18U }, |
| 7141 | { .FromReg: RISCV::X19, .ToReg: 19U }, |
| 7142 | { .FromReg: RISCV::X20, .ToReg: 20U }, |
| 7143 | { .FromReg: RISCV::X21, .ToReg: 21U }, |
| 7144 | { .FromReg: RISCV::X22, .ToReg: 22U }, |
| 7145 | { .FromReg: RISCV::X23, .ToReg: 23U }, |
| 7146 | { .FromReg: RISCV::X24, .ToReg: 24U }, |
| 7147 | { .FromReg: RISCV::X25, .ToReg: 25U }, |
| 7148 | { .FromReg: RISCV::X26, .ToReg: 26U }, |
| 7149 | { .FromReg: RISCV::X27, .ToReg: 27U }, |
| 7150 | { .FromReg: RISCV::X28, .ToReg: 28U }, |
| 7151 | { .FromReg: RISCV::X29, .ToReg: 29U }, |
| 7152 | { .FromReg: RISCV::X30, .ToReg: 30U }, |
| 7153 | { .FromReg: RISCV::X31, .ToReg: 31U }, |
| 7154 | { .FromReg: RISCV::F0_D, .ToReg: 32U }, |
| 7155 | { .FromReg: RISCV::F1_D, .ToReg: 33U }, |
| 7156 | { .FromReg: RISCV::F2_D, .ToReg: 34U }, |
| 7157 | { .FromReg: RISCV::F3_D, .ToReg: 35U }, |
| 7158 | { .FromReg: RISCV::F4_D, .ToReg: 36U }, |
| 7159 | { .FromReg: RISCV::F5_D, .ToReg: 37U }, |
| 7160 | { .FromReg: RISCV::F6_D, .ToReg: 38U }, |
| 7161 | { .FromReg: RISCV::F7_D, .ToReg: 39U }, |
| 7162 | { .FromReg: RISCV::F8_D, .ToReg: 40U }, |
| 7163 | { .FromReg: RISCV::F9_D, .ToReg: 41U }, |
| 7164 | { .FromReg: RISCV::F10_D, .ToReg: 42U }, |
| 7165 | { .FromReg: RISCV::F11_D, .ToReg: 43U }, |
| 7166 | { .FromReg: RISCV::F12_D, .ToReg: 44U }, |
| 7167 | { .FromReg: RISCV::F13_D, .ToReg: 45U }, |
| 7168 | { .FromReg: RISCV::F14_D, .ToReg: 46U }, |
| 7169 | { .FromReg: RISCV::F15_D, .ToReg: 47U }, |
| 7170 | { .FromReg: RISCV::F16_D, .ToReg: 48U }, |
| 7171 | { .FromReg: RISCV::F17_D, .ToReg: 49U }, |
| 7172 | { .FromReg: RISCV::F18_D, .ToReg: 50U }, |
| 7173 | { .FromReg: RISCV::F19_D, .ToReg: 51U }, |
| 7174 | { .FromReg: RISCV::F20_D, .ToReg: 52U }, |
| 7175 | { .FromReg: RISCV::F21_D, .ToReg: 53U }, |
| 7176 | { .FromReg: RISCV::F22_D, .ToReg: 54U }, |
| 7177 | { .FromReg: RISCV::F23_D, .ToReg: 55U }, |
| 7178 | { .FromReg: RISCV::F24_D, .ToReg: 56U }, |
| 7179 | { .FromReg: RISCV::F25_D, .ToReg: 57U }, |
| 7180 | { .FromReg: RISCV::F26_D, .ToReg: 58U }, |
| 7181 | { .FromReg: RISCV::F27_D, .ToReg: 59U }, |
| 7182 | { .FromReg: RISCV::F28_D, .ToReg: 60U }, |
| 7183 | { .FromReg: RISCV::F29_D, .ToReg: 61U }, |
| 7184 | { .FromReg: RISCV::F30_D, .ToReg: 62U }, |
| 7185 | { .FromReg: RISCV::F31_D, .ToReg: 63U }, |
| 7186 | { .FromReg: RISCV::F0_F, .ToReg: 32U }, |
| 7187 | { .FromReg: RISCV::F1_F, .ToReg: 33U }, |
| 7188 | { .FromReg: RISCV::F2_F, .ToReg: 34U }, |
| 7189 | { .FromReg: RISCV::F3_F, .ToReg: 35U }, |
| 7190 | { .FromReg: RISCV::F4_F, .ToReg: 36U }, |
| 7191 | { .FromReg: RISCV::F5_F, .ToReg: 37U }, |
| 7192 | { .FromReg: RISCV::F6_F, .ToReg: 38U }, |
| 7193 | { .FromReg: RISCV::F7_F, .ToReg: 39U }, |
| 7194 | { .FromReg: RISCV::F8_F, .ToReg: 40U }, |
| 7195 | { .FromReg: RISCV::F9_F, .ToReg: 41U }, |
| 7196 | { .FromReg: RISCV::F10_F, .ToReg: 42U }, |
| 7197 | { .FromReg: RISCV::F11_F, .ToReg: 43U }, |
| 7198 | { .FromReg: RISCV::F12_F, .ToReg: 44U }, |
| 7199 | { .FromReg: RISCV::F13_F, .ToReg: 45U }, |
| 7200 | { .FromReg: RISCV::F14_F, .ToReg: 46U }, |
| 7201 | { .FromReg: RISCV::F15_F, .ToReg: 47U }, |
| 7202 | { .FromReg: RISCV::F16_F, .ToReg: 48U }, |
| 7203 | { .FromReg: RISCV::F17_F, .ToReg: 49U }, |
| 7204 | { .FromReg: RISCV::F18_F, .ToReg: 50U }, |
| 7205 | { .FromReg: RISCV::F19_F, .ToReg: 51U }, |
| 7206 | { .FromReg: RISCV::F20_F, .ToReg: 52U }, |
| 7207 | { .FromReg: RISCV::F21_F, .ToReg: 53U }, |
| 7208 | { .FromReg: RISCV::F22_F, .ToReg: 54U }, |
| 7209 | { .FromReg: RISCV::F23_F, .ToReg: 55U }, |
| 7210 | { .FromReg: RISCV::F24_F, .ToReg: 56U }, |
| 7211 | { .FromReg: RISCV::F25_F, .ToReg: 57U }, |
| 7212 | { .FromReg: RISCV::F26_F, .ToReg: 58U }, |
| 7213 | { .FromReg: RISCV::F27_F, .ToReg: 59U }, |
| 7214 | { .FromReg: RISCV::F28_F, .ToReg: 60U }, |
| 7215 | { .FromReg: RISCV::F29_F, .ToReg: 61U }, |
| 7216 | { .FromReg: RISCV::F30_F, .ToReg: 62U }, |
| 7217 | { .FromReg: RISCV::F31_F, .ToReg: 63U }, |
| 7218 | { .FromReg: RISCV::F0_H, .ToReg: 32U }, |
| 7219 | { .FromReg: RISCV::F1_H, .ToReg: 33U }, |
| 7220 | { .FromReg: RISCV::F2_H, .ToReg: 34U }, |
| 7221 | { .FromReg: RISCV::F3_H, .ToReg: 35U }, |
| 7222 | { .FromReg: RISCV::F4_H, .ToReg: 36U }, |
| 7223 | { .FromReg: RISCV::F5_H, .ToReg: 37U }, |
| 7224 | { .FromReg: RISCV::F6_H, .ToReg: 38U }, |
| 7225 | { .FromReg: RISCV::F7_H, .ToReg: 39U }, |
| 7226 | { .FromReg: RISCV::F8_H, .ToReg: 40U }, |
| 7227 | { .FromReg: RISCV::F9_H, .ToReg: 41U }, |
| 7228 | { .FromReg: RISCV::F10_H, .ToReg: 42U }, |
| 7229 | { .FromReg: RISCV::F11_H, .ToReg: 43U }, |
| 7230 | { .FromReg: RISCV::F12_H, .ToReg: 44U }, |
| 7231 | { .FromReg: RISCV::F13_H, .ToReg: 45U }, |
| 7232 | { .FromReg: RISCV::F14_H, .ToReg: 46U }, |
| 7233 | { .FromReg: RISCV::F15_H, .ToReg: 47U }, |
| 7234 | { .FromReg: RISCV::F16_H, .ToReg: 48U }, |
| 7235 | { .FromReg: RISCV::F17_H, .ToReg: 49U }, |
| 7236 | { .FromReg: RISCV::F18_H, .ToReg: 50U }, |
| 7237 | { .FromReg: RISCV::F19_H, .ToReg: 51U }, |
| 7238 | { .FromReg: RISCV::F20_H, .ToReg: 52U }, |
| 7239 | { .FromReg: RISCV::F21_H, .ToReg: 53U }, |
| 7240 | { .FromReg: RISCV::F22_H, .ToReg: 54U }, |
| 7241 | { .FromReg: RISCV::F23_H, .ToReg: 55U }, |
| 7242 | { .FromReg: RISCV::F24_H, .ToReg: 56U }, |
| 7243 | { .FromReg: RISCV::F25_H, .ToReg: 57U }, |
| 7244 | { .FromReg: RISCV::F26_H, .ToReg: 58U }, |
| 7245 | { .FromReg: RISCV::F27_H, .ToReg: 59U }, |
| 7246 | { .FromReg: RISCV::F28_H, .ToReg: 60U }, |
| 7247 | { .FromReg: RISCV::F29_H, .ToReg: 61U }, |
| 7248 | { .FromReg: RISCV::F30_H, .ToReg: 62U }, |
| 7249 | { .FromReg: RISCV::F31_H, .ToReg: 63U }, |
| 7250 | { .FromReg: RISCV::F0_Q, .ToReg: 32U }, |
| 7251 | { .FromReg: RISCV::F1_Q, .ToReg: 33U }, |
| 7252 | { .FromReg: RISCV::F2_Q, .ToReg: 34U }, |
| 7253 | { .FromReg: RISCV::F3_Q, .ToReg: 35U }, |
| 7254 | { .FromReg: RISCV::F4_Q, .ToReg: 36U }, |
| 7255 | { .FromReg: RISCV::F5_Q, .ToReg: 37U }, |
| 7256 | { .FromReg: RISCV::F6_Q, .ToReg: 38U }, |
| 7257 | { .FromReg: RISCV::F7_Q, .ToReg: 39U }, |
| 7258 | { .FromReg: RISCV::F8_Q, .ToReg: 40U }, |
| 7259 | { .FromReg: RISCV::F9_Q, .ToReg: 41U }, |
| 7260 | { .FromReg: RISCV::F10_Q, .ToReg: 42U }, |
| 7261 | { .FromReg: RISCV::F11_Q, .ToReg: 43U }, |
| 7262 | { .FromReg: RISCV::F12_Q, .ToReg: 44U }, |
| 7263 | { .FromReg: RISCV::F13_Q, .ToReg: 45U }, |
| 7264 | { .FromReg: RISCV::F14_Q, .ToReg: 46U }, |
| 7265 | { .FromReg: RISCV::F15_Q, .ToReg: 47U }, |
| 7266 | { .FromReg: RISCV::F16_Q, .ToReg: 48U }, |
| 7267 | { .FromReg: RISCV::F17_Q, .ToReg: 49U }, |
| 7268 | { .FromReg: RISCV::F18_Q, .ToReg: 50U }, |
| 7269 | { .FromReg: RISCV::F19_Q, .ToReg: 51U }, |
| 7270 | { .FromReg: RISCV::F20_Q, .ToReg: 52U }, |
| 7271 | { .FromReg: RISCV::F21_Q, .ToReg: 53U }, |
| 7272 | { .FromReg: RISCV::F22_Q, .ToReg: 54U }, |
| 7273 | { .FromReg: RISCV::F23_Q, .ToReg: 55U }, |
| 7274 | { .FromReg: RISCV::F24_Q, .ToReg: 56U }, |
| 7275 | { .FromReg: RISCV::F25_Q, .ToReg: 57U }, |
| 7276 | { .FromReg: RISCV::F26_Q, .ToReg: 58U }, |
| 7277 | { .FromReg: RISCV::F27_Q, .ToReg: 59U }, |
| 7278 | { .FromReg: RISCV::F28_Q, .ToReg: 60U }, |
| 7279 | { .FromReg: RISCV::F29_Q, .ToReg: 61U }, |
| 7280 | { .FromReg: RISCV::F30_Q, .ToReg: 62U }, |
| 7281 | { .FromReg: RISCV::F31_Q, .ToReg: 63U }, |
| 7282 | { .FromReg: RISCV::X0_Y, .ToReg: 0U }, |
| 7283 | { .FromReg: RISCV::X1_Y, .ToReg: 1U }, |
| 7284 | { .FromReg: RISCV::X2_Y, .ToReg: 2U }, |
| 7285 | { .FromReg: RISCV::X3_Y, .ToReg: 3U }, |
| 7286 | { .FromReg: RISCV::X4_Y, .ToReg: 4U }, |
| 7287 | { .FromReg: RISCV::X5_Y, .ToReg: 5U }, |
| 7288 | { .FromReg: RISCV::X6_Y, .ToReg: 6U }, |
| 7289 | { .FromReg: RISCV::X7_Y, .ToReg: 7U }, |
| 7290 | { .FromReg: RISCV::X8_Y, .ToReg: 8U }, |
| 7291 | { .FromReg: RISCV::X9_Y, .ToReg: 9U }, |
| 7292 | { .FromReg: RISCV::X10_Y, .ToReg: 10U }, |
| 7293 | { .FromReg: RISCV::X11_Y, .ToReg: 11U }, |
| 7294 | { .FromReg: RISCV::X12_Y, .ToReg: 12U }, |
| 7295 | { .FromReg: RISCV::X13_Y, .ToReg: 13U }, |
| 7296 | { .FromReg: RISCV::X14_Y, .ToReg: 14U }, |
| 7297 | { .FromReg: RISCV::X15_Y, .ToReg: 15U }, |
| 7298 | { .FromReg: RISCV::X16_Y, .ToReg: 16U }, |
| 7299 | { .FromReg: RISCV::X17_Y, .ToReg: 17U }, |
| 7300 | { .FromReg: RISCV::X18_Y, .ToReg: 18U }, |
| 7301 | { .FromReg: RISCV::X19_Y, .ToReg: 19U }, |
| 7302 | { .FromReg: RISCV::X20_Y, .ToReg: 20U }, |
| 7303 | { .FromReg: RISCV::X21_Y, .ToReg: 21U }, |
| 7304 | { .FromReg: RISCV::X22_Y, .ToReg: 22U }, |
| 7305 | { .FromReg: RISCV::X23_Y, .ToReg: 23U }, |
| 7306 | { .FromReg: RISCV::X24_Y, .ToReg: 24U }, |
| 7307 | { .FromReg: RISCV::X25_Y, .ToReg: 25U }, |
| 7308 | { .FromReg: RISCV::X26_Y, .ToReg: 26U }, |
| 7309 | { .FromReg: RISCV::X27_Y, .ToReg: 27U }, |
| 7310 | { .FromReg: RISCV::X28_Y, .ToReg: 28U }, |
| 7311 | { .FromReg: RISCV::X29_Y, .ToReg: 29U }, |
| 7312 | { .FromReg: RISCV::X30_Y, .ToReg: 30U }, |
| 7313 | { .FromReg: RISCV::X31_Y, .ToReg: 31U }, |
| 7314 | { .FromReg: RISCV::F0_Q2, .ToReg: 3088U }, |
| 7315 | { .FromReg: RISCV::F1_Q2, .ToReg: 3089U }, |
| 7316 | { .FromReg: RISCV::F2_Q2, .ToReg: 3090U }, |
| 7317 | { .FromReg: RISCV::F3_Q2, .ToReg: 3091U }, |
| 7318 | { .FromReg: RISCV::F4_Q2, .ToReg: 3092U }, |
| 7319 | { .FromReg: RISCV::F5_Q2, .ToReg: 3093U }, |
| 7320 | { .FromReg: RISCV::F6_Q2, .ToReg: 3094U }, |
| 7321 | { .FromReg: RISCV::F7_Q2, .ToReg: 3095U }, |
| 7322 | { .FromReg: RISCV::F8_Q2, .ToReg: 3096U }, |
| 7323 | { .FromReg: RISCV::F9_Q2, .ToReg: 3097U }, |
| 7324 | { .FromReg: RISCV::F10_Q2, .ToReg: 3098U }, |
| 7325 | { .FromReg: RISCV::F11_Q2, .ToReg: 3099U }, |
| 7326 | { .FromReg: RISCV::F12_Q2, .ToReg: 3100U }, |
| 7327 | { .FromReg: RISCV::F13_Q2, .ToReg: 3101U }, |
| 7328 | { .FromReg: RISCV::F14_Q2, .ToReg: 3102U }, |
| 7329 | { .FromReg: RISCV::F15_Q2, .ToReg: 3103U }, |
| 7330 | { .FromReg: RISCV::F16_Q2, .ToReg: 3104U }, |
| 7331 | { .FromReg: RISCV::F17_Q2, .ToReg: 3105U }, |
| 7332 | { .FromReg: RISCV::F18_Q2, .ToReg: 3106U }, |
| 7333 | { .FromReg: RISCV::F19_Q2, .ToReg: 3107U }, |
| 7334 | { .FromReg: RISCV::F20_Q2, .ToReg: 3108U }, |
| 7335 | { .FromReg: RISCV::F21_Q2, .ToReg: 3109U }, |
| 7336 | { .FromReg: RISCV::F22_Q2, .ToReg: 3110U }, |
| 7337 | { .FromReg: RISCV::F23_Q2, .ToReg: 3111U }, |
| 7338 | { .FromReg: RISCV::F24_Q2, .ToReg: 3112U }, |
| 7339 | { .FromReg: RISCV::F25_Q2, .ToReg: 3113U }, |
| 7340 | { .FromReg: RISCV::F26_Q2, .ToReg: 3114U }, |
| 7341 | { .FromReg: RISCV::F27_Q2, .ToReg: 3115U }, |
| 7342 | { .FromReg: RISCV::F28_Q2, .ToReg: 3116U }, |
| 7343 | { .FromReg: RISCV::F29_Q2, .ToReg: 3117U }, |
| 7344 | { .FromReg: RISCV::F30_Q2, .ToReg: 3118U }, |
| 7345 | { .FromReg: RISCV::F31_Q2, .ToReg: 3119U }, |
| 7346 | { .FromReg: RISCV::V0M2, .ToReg: 96U }, |
| 7347 | { .FromReg: RISCV::V0M4, .ToReg: 96U }, |
| 7348 | { .FromReg: RISCV::V0M8, .ToReg: 96U }, |
| 7349 | { .FromReg: RISCV::V2M2, .ToReg: 98U }, |
| 7350 | { .FromReg: RISCV::V4M2, .ToReg: 100U }, |
| 7351 | { .FromReg: RISCV::V4M4, .ToReg: 100U }, |
| 7352 | { .FromReg: RISCV::V6M2, .ToReg: 102U }, |
| 7353 | { .FromReg: RISCV::V8M2, .ToReg: 104U }, |
| 7354 | { .FromReg: RISCV::V8M4, .ToReg: 104U }, |
| 7355 | { .FromReg: RISCV::V8M8, .ToReg: 104U }, |
| 7356 | { .FromReg: RISCV::V10M2, .ToReg: 106U }, |
| 7357 | { .FromReg: RISCV::V12M2, .ToReg: 108U }, |
| 7358 | { .FromReg: RISCV::V12M4, .ToReg: 108U }, |
| 7359 | { .FromReg: RISCV::V14M2, .ToReg: 110U }, |
| 7360 | { .FromReg: RISCV::V16M2, .ToReg: 112U }, |
| 7361 | { .FromReg: RISCV::V16M4, .ToReg: 112U }, |
| 7362 | { .FromReg: RISCV::V16M8, .ToReg: 112U }, |
| 7363 | { .FromReg: RISCV::V18M2, .ToReg: 114U }, |
| 7364 | { .FromReg: RISCV::V20M2, .ToReg: 116U }, |
| 7365 | { .FromReg: RISCV::V20M4, .ToReg: 116U }, |
| 7366 | { .FromReg: RISCV::V22M2, .ToReg: 118U }, |
| 7367 | { .FromReg: RISCV::V24M2, .ToReg: 120U }, |
| 7368 | { .FromReg: RISCV::V24M4, .ToReg: 120U }, |
| 7369 | { .FromReg: RISCV::V24M8, .ToReg: 120U }, |
| 7370 | { .FromReg: RISCV::V26M2, .ToReg: 122U }, |
| 7371 | { .FromReg: RISCV::V28M2, .ToReg: 124U }, |
| 7372 | { .FromReg: RISCV::V28M4, .ToReg: 124U }, |
| 7373 | { .FromReg: RISCV::V30M2, .ToReg: 126U }, |
| 7374 | }; |
| 7375 | extern const unsigned RISCVEHFlavour0L2DwarfSize = std::size(RISCVEHFlavour0L2Dwarf); |
| 7376 | |
| 7377 | extern const uint16_t RISCVRegEncodingTable[] = { |
| 7378 | 0, |
| 7379 | 0, |
| 7380 | 0, |
| 7381 | 0, |
| 7382 | 0, |
| 7383 | 0, |
| 7384 | 0, |
| 7385 | 0, |
| 7386 | 0, |
| 7387 | 0, |
| 7388 | 0, |
| 7389 | 0, |
| 7390 | 0, |
| 7391 | 1, |
| 7392 | 2, |
| 7393 | 3, |
| 7394 | 4, |
| 7395 | 5, |
| 7396 | 6, |
| 7397 | 7, |
| 7398 | 0, |
| 7399 | 1, |
| 7400 | 2, |
| 7401 | 3, |
| 7402 | 4, |
| 7403 | 5, |
| 7404 | 6, |
| 7405 | 7, |
| 7406 | 8, |
| 7407 | 9, |
| 7408 | 10, |
| 7409 | 11, |
| 7410 | 12, |
| 7411 | 13, |
| 7412 | 14, |
| 7413 | 15, |
| 7414 | 0, |
| 7415 | 1, |
| 7416 | 2, |
| 7417 | 3, |
| 7418 | 4, |
| 7419 | 5, |
| 7420 | 6, |
| 7421 | 7, |
| 7422 | 8, |
| 7423 | 9, |
| 7424 | 10, |
| 7425 | 11, |
| 7426 | 12, |
| 7427 | 13, |
| 7428 | 14, |
| 7429 | 15, |
| 7430 | 16, |
| 7431 | 17, |
| 7432 | 18, |
| 7433 | 19, |
| 7434 | 20, |
| 7435 | 21, |
| 7436 | 22, |
| 7437 | 23, |
| 7438 | 24, |
| 7439 | 25, |
| 7440 | 26, |
| 7441 | 27, |
| 7442 | 28, |
| 7443 | 29, |
| 7444 | 30, |
| 7445 | 31, |
| 7446 | 0, |
| 7447 | 1, |
| 7448 | 2, |
| 7449 | 3, |
| 7450 | 4, |
| 7451 | 5, |
| 7452 | 6, |
| 7453 | 7, |
| 7454 | 8, |
| 7455 | 9, |
| 7456 | 10, |
| 7457 | 11, |
| 7458 | 12, |
| 7459 | 13, |
| 7460 | 14, |
| 7461 | 15, |
| 7462 | 16, |
| 7463 | 17, |
| 7464 | 18, |
| 7465 | 19, |
| 7466 | 20, |
| 7467 | 21, |
| 7468 | 22, |
| 7469 | 23, |
| 7470 | 24, |
| 7471 | 25, |
| 7472 | 26, |
| 7473 | 27, |
| 7474 | 28, |
| 7475 | 29, |
| 7476 | 30, |
| 7477 | 31, |
| 7478 | 0, |
| 7479 | 1, |
| 7480 | 2, |
| 7481 | 3, |
| 7482 | 4, |
| 7483 | 5, |
| 7484 | 6, |
| 7485 | 7, |
| 7486 | 8, |
| 7487 | 9, |
| 7488 | 10, |
| 7489 | 11, |
| 7490 | 12, |
| 7491 | 13, |
| 7492 | 14, |
| 7493 | 15, |
| 7494 | 16, |
| 7495 | 17, |
| 7496 | 18, |
| 7497 | 19, |
| 7498 | 20, |
| 7499 | 21, |
| 7500 | 22, |
| 7501 | 23, |
| 7502 | 24, |
| 7503 | 25, |
| 7504 | 26, |
| 7505 | 27, |
| 7506 | 28, |
| 7507 | 29, |
| 7508 | 30, |
| 7509 | 31, |
| 7510 | 0, |
| 7511 | 1, |
| 7512 | 2, |
| 7513 | 3, |
| 7514 | 4, |
| 7515 | 5, |
| 7516 | 6, |
| 7517 | 7, |
| 7518 | 8, |
| 7519 | 9, |
| 7520 | 10, |
| 7521 | 11, |
| 7522 | 12, |
| 7523 | 13, |
| 7524 | 14, |
| 7525 | 15, |
| 7526 | 16, |
| 7527 | 17, |
| 7528 | 18, |
| 7529 | 19, |
| 7530 | 20, |
| 7531 | 21, |
| 7532 | 22, |
| 7533 | 23, |
| 7534 | 24, |
| 7535 | 25, |
| 7536 | 26, |
| 7537 | 27, |
| 7538 | 28, |
| 7539 | 29, |
| 7540 | 30, |
| 7541 | 31, |
| 7542 | 0, |
| 7543 | 1, |
| 7544 | 2, |
| 7545 | 3, |
| 7546 | 4, |
| 7547 | 5, |
| 7548 | 6, |
| 7549 | 7, |
| 7550 | 8, |
| 7551 | 9, |
| 7552 | 10, |
| 7553 | 11, |
| 7554 | 12, |
| 7555 | 13, |
| 7556 | 14, |
| 7557 | 15, |
| 7558 | 16, |
| 7559 | 17, |
| 7560 | 18, |
| 7561 | 19, |
| 7562 | 20, |
| 7563 | 21, |
| 7564 | 22, |
| 7565 | 23, |
| 7566 | 24, |
| 7567 | 25, |
| 7568 | 26, |
| 7569 | 27, |
| 7570 | 28, |
| 7571 | 29, |
| 7572 | 30, |
| 7573 | 31, |
| 7574 | 0, |
| 7575 | 1, |
| 7576 | 2, |
| 7577 | 3, |
| 7578 | 4, |
| 7579 | 5, |
| 7580 | 6, |
| 7581 | 7, |
| 7582 | 8, |
| 7583 | 9, |
| 7584 | 10, |
| 7585 | 11, |
| 7586 | 12, |
| 7587 | 13, |
| 7588 | 14, |
| 7589 | 15, |
| 7590 | 16, |
| 7591 | 17, |
| 7592 | 18, |
| 7593 | 19, |
| 7594 | 20, |
| 7595 | 21, |
| 7596 | 22, |
| 7597 | 23, |
| 7598 | 24, |
| 7599 | 25, |
| 7600 | 26, |
| 7601 | 27, |
| 7602 | 28, |
| 7603 | 29, |
| 7604 | 30, |
| 7605 | 31, |
| 7606 | 0, |
| 7607 | 1, |
| 7608 | 2, |
| 7609 | 3, |
| 7610 | 4, |
| 7611 | 5, |
| 7612 | 6, |
| 7613 | 7, |
| 7614 | 8, |
| 7615 | 9, |
| 7616 | 10, |
| 7617 | 11, |
| 7618 | 12, |
| 7619 | 13, |
| 7620 | 14, |
| 7621 | 15, |
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| 8022 | 0, |
| 8023 | }; |
| 8024 | static inline void InitRISCVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
| 8025 | RI->InitMCRegisterInfo(D: RISCVRegDesc, NR: 645, RA, PC, C: RISCVMCRegisterClassStorage.Classes, NC: 153, RURoots: RISCVRegUnitRoots, NRU: 131, DL: RISCVRegDiffLists, RUMS: RISCVLaneMaskLists, Strings: RISCVRegStrings, ClassStrings: RISCVRegClassStrings, SubIndices: RISCVSubRegIdxLists, NumIndices: 58, |
| 8026 | RET: RISCVRegEncodingTable, RUI: nullptr); |
| 8027 | |
| 8028 | switch (DwarfFlavour) { |
| 8029 | default: |
| 8030 | llvm_unreachable("Unknown DWARF flavour"); |
| 8031 | case 0: |
| 8032 | RI->mapDwarfRegsToLLVMRegs(Map: RISCVDwarfFlavour0Dwarf2L, Size: RISCVDwarfFlavour0Dwarf2LSize, isEH: false); |
| 8033 | break; |
| 8034 | } |
| 8035 | switch (EHFlavour) { |
| 8036 | default: |
| 8037 | llvm_unreachable("Unknown DWARF flavour"); |
| 8038 | case 0: |
| 8039 | RI->mapDwarfRegsToLLVMRegs(Map: RISCVEHFlavour0Dwarf2L, Size: RISCVEHFlavour0Dwarf2LSize, isEH: true); |
| 8040 | break; |
| 8041 | } |
| 8042 | switch (DwarfFlavour) { |
| 8043 | default: |
| 8044 | llvm_unreachable("Unknown DWARF flavour"); |
| 8045 | case 0: |
| 8046 | RI->mapLLVMRegsToDwarfRegs(Map: RISCVDwarfFlavour0L2Dwarf, Size: RISCVDwarfFlavour0L2DwarfSize, isEH: false); |
| 8047 | break; |
| 8048 | } |
| 8049 | switch (EHFlavour) { |
| 8050 | default: |
| 8051 | llvm_unreachable("Unknown DWARF flavour"); |
| 8052 | case 0: |
| 8053 | RI->mapLLVMRegsToDwarfRegs(Map: RISCVEHFlavour0L2Dwarf, Size: RISCVEHFlavour0L2DwarfSize, isEH: true); |
| 8054 | break; |
| 8055 | } |
| 8056 | } |
| 8057 | |
| 8058 | |
| 8059 | } // namespace llvm |
| 8060 |
Generated while processing llvm_projects/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
Generated on 2026-Aug-30 from project llvm_projects revision 868246f06
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