| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* MC Register Information *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | namespace llvm { |
| 10 | |
| 11 | extern const int16_t RISCVRegDiffLists[] = { |
| 12 | /* 0 */ -192, 193, -33, -217, 0, |
| 13 | /* 5 */ -105, 0, |
| 14 | /* 7 */ -103, 0, |
| 15 | /* 9 */ -101, 0, |
| 16 | /* 11 */ -99, 0, |
| 17 | /* 13 */ -97, 0, |
| 18 | /* 15 */ -95, 0, |
| 19 | /* 17 */ 25, -106, -86, 0, |
| 20 | /* 21 */ 317, -1, -3, 49, 52, 43, -80, 121, 27, 26, 25, -148, 42, -86, 0, |
| 21 | /* 36 */ 321, 1, 1, 71, 52, 43, -80, 121, 27, 26, 25, -148, 42, -86, 0, |
| 22 | /* 51 */ -1, -3, 64, 51, 42, -86, 0, |
| 23 | /* 58 */ 1, 1, 86, 51, 42, -86, 0, |
| 24 | /* 65 */ -104, -85, 0, |
| 25 | /* 68 */ -102, -84, 0, |
| 26 | /* 71 */ -100, -83, 0, |
| 27 | /* 74 */ -98, -82, 0, |
| 28 | /* 77 */ -96, -81, 0, |
| 29 | /* 80 */ -530, 1, 1, 1, 1, 390, 52, 43, -125, 53, -52, 96, -43, -52, 0, |
| 30 | /* 95 */ -502, 1, 1, 1, 1, 359, 53, 44, -96, 53, -52, 96, -43, -52, 0, |
| 31 | /* 110 */ -88, -321, 1, 323, -322, 1, 391, 52, 43, -125, 53, -52, 0, |
| 32 | /* 123 */ -557, 1, 1, 1, 1, 1, 389, 52, 43, -125, 53, -52, 165, -69, 42, -85, 44, -96, 53, -52, 0, |
| 33 | /* 144 */ -530, 1, 1, 1, 1, 1, 358, 53, 44, -96, 53, -52, 137, -41, 42, -85, 44, -96, 53, -52, 0, |
| 34 | /* 165 */ -583, 1, 1, 1, 1, 1, 1, 388, 52, 43, -125, 53, -52, 165, 27, -96, 42, 28, -113, 44, 42, -138, 53, 44, -96, 53, -52, 0, |
| 35 | /* 193 */ -557, 1, 1, 1, 1, 1, 1, 357, 53, 44, -96, 53, -52, 137, 28, -69, 42, 28, -113, 44, 42, -138, 53, 44, -96, 53, -52, 0, |
| 36 | /* 221 */ -608, 1, 1, 1, 1, 1, 1, 1, 387, 52, 43, -125, 53, -52, 165, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 0, |
| 37 | /* 257 */ -583, 1, 1, 1, 1, 1, 1, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, -96, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 0, |
| 38 | /* 293 */ -71, -322, 1, 322, -321, 1, 360, 53, 44, -96, 53, -52, 0, |
| 39 | /* 306 */ -71, -321, 1, 322, -321, 1, 360, 53, 44, -96, 53, -52, 0, |
| 40 | /* 319 */ -70, -320, 1, 322, -321, 1, 360, 53, 44, -96, 53, -52, 0, |
| 41 | /* 332 */ -70, -321, 1, 321, -320, 1, 360, 53, 44, -96, 53, -52, 0, |
| 42 | /* 345 */ -68, -321, 1, 321, -320, 1, 360, 53, 44, -96, 53, -52, 0, |
| 43 | /* 358 */ -68, -320, 1, 321, -320, 1, 360, 53, 44, -96, 53, -52, 0, |
| 44 | /* 371 */ -67, -319, 1, 321, -320, 1, 360, 53, 44, -96, 53, -52, 0, |
| 45 | /* 384 */ -67, -320, 1, 320, -319, 1, 360, 53, 44, -96, 53, -52, 0, |
| 46 | /* 397 */ -65, -320, 1, 320, -319, 1, 360, 53, 44, -96, 53, -52, 0, |
| 47 | /* 410 */ -65, -319, 1, 320, -319, 1, 360, 53, 44, -96, 53, -52, 0, |
| 48 | /* 423 */ -64, -318, 1, 320, -319, 1, 360, 53, 44, -96, 53, -52, 0, |
| 49 | /* 436 */ -64, -319, 1, 319, -318, 1, 360, 53, 44, -96, 53, -52, 0, |
| 50 | /* 449 */ -62, -319, 1, 319, -318, 1, 360, 53, 44, -96, 53, -52, 0, |
| 51 | /* 462 */ -62, -318, 1, 319, -318, 1, 360, 53, 44, -96, 53, -52, 0, |
| 52 | /* 475 */ -489, 1, 1, 1, 391, 52, -82, 53, -52, 0, |
| 53 | /* 485 */ -460, 1, 1, 1, 360, 53, -52, 53, -52, 0, |
| 54 | /* 495 */ -94, -1, -321, 1, 323, -322, 1, 323, -1, -321, 1, 322, -321, 1, 387, 52, 43, -125, 53, -52, 165, 27, 26, 25, -147, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 40, 51, 42, -107, 52, -51, 0, |
| 55 | /* 544 */ -72, -1, -318, 1, 320, -319, 1, 320, -1, -318, 1, 319, -318, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 13, 52, 43, -94, 52, -51, 0, |
| 56 | /* 593 */ -74, -1, -319, 1, 320, -319, 1, 320, -1, -318, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 15, 52, 43, -94, 52, -51, 0, |
| 57 | /* 642 */ -77, -1, -319, 1, 321, -320, 1, 321, -1, -319, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 17, 52, 43, -94, 52, -51, 0, |
| 58 | /* 691 */ -79, -1, -320, 1, 321, -320, 1, 321, -1, -319, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 19, 52, 43, -94, 52, -51, 0, |
| 59 | /* 740 */ -82, -1, -320, 1, 322, -321, 1, 322, -1, -320, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 21, 52, 43, -94, 52, -51, 0, |
| 60 | /* 789 */ -84, -1, -321, 1, 322, -321, 1, 322, -1, -320, 1, 322, -321, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 23, 52, 43, -94, 52, -51, 0, |
| 61 | /* 838 */ -181, -321, 1, 323, -322, 1, 322, -321, 1, 322, -321, 1, 387, 52, 43, -125, 53, -52, 165, 27, 26, 25, -147, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 40, 51, -65, 52, -51, 0, |
| 62 | /* 884 */ -159, -318, 1, 320, -319, 1, 319, -318, 1, 319, -318, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 13, 52, -51, 52, -51, 0, |
| 63 | /* 930 */ -159, -319, 1, 319, -318, 1, 320, -319, 1, 319, -318, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 14, 52, -51, 52, -51, 0, |
| 64 | /* 976 */ -160, -319, 1, 320, -319, 1, 319, -318, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 15, 52, -51, 52, -51, 0, |
| 65 | /* 1022 */ -160, -320, 1, 320, -319, 1, 320, -319, 1, 319, -318, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 16, 52, -51, 52, -51, 0, |
| 66 | /* 1068 */ -162, -319, 1, 321, -320, 1, 320, -319, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 17, 52, -51, 52, -51, 0, |
| 67 | /* 1114 */ -162, -320, 1, 320, -319, 1, 321, -320, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 18, 52, -51, 52, -51, 0, |
| 68 | /* 1160 */ -163, -320, 1, 321, -320, 1, 320, -319, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 19, 52, -51, 52, -51, 0, |
| 69 | /* 1206 */ -163, -321, 1, 321, -320, 1, 321, -320, 1, 320, -319, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 20, 52, -51, 52, -51, 0, |
| 70 | /* 1252 */ -165, -320, 1, 322, -321, 1, 321, -320, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 21, 52, -51, 52, -51, 0, |
| 71 | /* 1298 */ -165, -321, 1, 321, -320, 1, 322, -321, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 22, 52, -51, 52, -51, 0, |
| 72 | /* 1344 */ -166, -321, 1, 322, -321, 1, 321, -320, 1, 322, -321, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 23, 52, -51, 52, -51, 0, |
| 73 | /* 1390 */ -166, -322, 1, 322, -321, 1, 322, -321, 1, 321, -320, 1, 356, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 24, 52, -51, 52, -51, 0, |
| 74 | /* 1436 */ -225, 193, -33, 0, |
| 75 | /* 1440 */ -315, 193, -33, -159, 193, -33, 0, |
| 76 | /* 1447 */ -314, 193, -33, -159, 193, -33, 0, |
| 77 | /* 1454 */ -313, 193, -33, -159, 193, -33, 0, |
| 78 | /* 1461 */ -312, 193, -33, -159, 193, -33, 0, |
| 79 | /* 1468 */ -311, 193, -33, -159, 193, -33, 0, |
| 80 | /* 1475 */ -310, 193, -33, -159, 193, -33, 0, |
| 81 | /* 1482 */ -309, 193, -33, -159, 193, -33, 0, |
| 82 | /* 1489 */ -308, 193, -33, -159, 193, -33, 0, |
| 83 | /* 1496 */ -307, 193, -33, -159, 193, -33, 0, |
| 84 | /* 1503 */ -306, 193, -33, -159, 193, -33, 0, |
| 85 | /* 1510 */ -305, 193, -33, -159, 193, -33, 0, |
| 86 | /* 1517 */ -304, 193, -33, -159, 193, -33, 0, |
| 87 | /* 1524 */ -303, 193, -33, -159, 193, -33, 0, |
| 88 | /* 1531 */ -302, 193, -33, -159, 193, -33, 0, |
| 89 | /* 1538 */ -301, 193, -33, -159, 193, -33, 0, |
| 90 | /* 1545 */ -446, 1, 1, 392, -30, 0, |
| 91 | /* 1551 */ -139, -321, 1, 323, -322, 1, 322, -321, 1, 389, 52, 43, -125, 53, -52, 165, 27, -96, 42, -85, 44, -96, 53, -52, 42, -14, 0, |
| 92 | /* 1578 */ -394, 1, 0, |
| 93 | /* 1581 */ -363, 1, 0, |
| 94 | /* 1584 */ -1, -321, 1, 323, -322, 1, 0, |
| 95 | /* 1591 */ -1, -1, -321, 1, 323, -322, 1, 323, -1, -321, 1, 322, -321, 1, 0, |
| 96 | /* 1606 */ -1, -320, 1, 322, -321, 1, 0, |
| 97 | /* 1613 */ -1, -1, -320, 1, 322, -321, 1, 322, -1, -320, 1, 321, -320, 1, 0, |
| 98 | /* 1628 */ -1, -319, 1, 321, -320, 1, 0, |
| 99 | /* 1635 */ -1, -1, -319, 1, 321, -320, 1, 321, -1, -319, 1, 320, -319, 1, 0, |
| 100 | /* 1650 */ -1, -318, 1, 320, -319, 1, 0, |
| 101 | /* 1657 */ -1, -1, -318, 1, 320, -319, 1, 320, -1, -318, 1, 319, -318, 1, 0, |
| 102 | /* 1672 */ 1, 1, 1, 1, 1, 1, 1, 0, |
| 103 | /* 1680 */ -114, -319, 1, 319, -318, 1, 319, -318, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 14, 1, 0, |
| 104 | /* 1707 */ -116, -318, 1, 320, -319, 1, 319, -318, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 15, 1, 0, |
| 105 | /* 1734 */ -116, -319, 1, 319, -318, 1, 320, -319, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 16, 1, 0, |
| 106 | /* 1761 */ -117, -319, 1, 320, -319, 1, 319, -318, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 17, 1, 0, |
| 107 | /* 1788 */ -117, -320, 1, 320, -319, 1, 320, -319, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 18, 1, 0, |
| 108 | /* 1815 */ -119, -319, 1, 321, -320, 1, 320, -319, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 19, 1, 0, |
| 109 | /* 1842 */ -119, -320, 1, 320, -319, 1, 321, -320, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 20, 1, 0, |
| 110 | /* 1869 */ -120, -320, 1, 321, -320, 1, 320, -319, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 21, 1, 0, |
| 111 | /* 1896 */ -120, -321, 1, 321, -320, 1, 321, -320, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 22, 1, 0, |
| 112 | /* 1923 */ -122, -320, 1, 322, -321, 1, 321, -320, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 23, 1, 0, |
| 113 | /* 1950 */ -122, -321, 1, 321, -320, 1, 322, -321, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 24, 1, 0, |
| 114 | /* 1977 */ -123, -321, 1, 322, -321, 1, 321, -320, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 25, 1, 0, |
| 115 | /* 2004 */ -123, -322, 1, 322, -321, 1, 322, -321, 1, 358, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 26, 1, 0, |
| 116 | /* 2031 */ 1, 70, 1, 0, |
| 117 | /* 2035 */ 1, 75, 1, 0, |
| 118 | /* 2039 */ -3, 76, 1, 0, |
| 119 | /* 2043 */ 1, 80, 1, 0, |
| 120 | /* 2047 */ -3, 81, 1, 0, |
| 121 | /* 2051 */ -416, 1, 1, 361, 1, 0, |
| 122 | /* 2057 */ 321, -2, 1, 42, 1, 51, 1, 43, -70, 28, 44, -71, 68, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 92, 2, 2, 2, 0, |
| 123 | /* 2107 */ 320, -1, -3, 46, 1, 51, 43, -68, 26, 1, 43, -69, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0, |
| 124 | /* 2157 */ 320, 1, 1, 40, 1, 51, 1, 43, -69, 27, 44, -70, 67, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 100, 28, 27, 26, -141, 43, -82, 122, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0, |
| 125 | /* 2207 */ 52, 1, 43, -69, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 123, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0, |
| 126 | /* 2242 */ 320, -1, -3, 46, 1, 51, 1, 43, -72, 30, 44, -73, 70, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 94, 2, 2, 2, 0, |
| 127 | /* 2292 */ 320, 1, -3, 44, 1, 51, 1, 43, -71, 29, 44, -72, 69, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 103, 28, 27, 26, -143, 43, -83, 125, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0, |
| 128 | /* 2342 */ 320, -2, 1, 43, 1, 51, 43, -70, 28, 1, 43, -71, 110, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0, |
| 129 | /* 2392 */ 52, 1, 43, -71, 70, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0, |
| 130 | /* 2427 */ 319, 1, 1, 41, 1, 51, 43, -69, 27, 1, 43, -70, 109, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 149, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 2, 0, |
| 131 | /* 2477 */ 52, 1, 43, -70, 69, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 126, 26, 1, 25, -97, 94, 2, 2, 2, 0, |
| 132 | /* 2513 */ 320, -2, 1, 43, 1, 51, 1, 43, -74, 32, 44, -75, 72, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 96, 2, 2, 2, 0, |
| 133 | /* 2563 */ 319, 1, 1, 41, 1, 51, 1, 43, -73, 31, 44, -74, 71, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 106, 28, 27, 26, -145, 43, -84, 128, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0, |
| 134 | /* 2613 */ 319, -1, -3, 47, 1, 51, 43, -72, 30, 1, 43, -73, 112, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0, |
| 135 | /* 2663 */ 52, 1, 43, -73, 72, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0, |
| 136 | /* 2698 */ 319, 1, -3, 45, 1, 51, 43, -71, 29, 1, 43, -72, 111, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 152, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 2, 0, |
| 137 | /* 2748 */ 52, 1, 43, -72, 71, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 129, 26, 1, 25, -99, 96, 2, 2, 2, 0, |
| 138 | /* 2784 */ 319, -1, -3, 47, 1, 51, 1, 43, -76, 34, 44, -77, 74, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 98, 2, 2, 2, 0, |
| 139 | /* 2834 */ 319, 1, -3, 45, 1, 51, 1, 43, -75, 33, 44, -76, 73, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 109, 28, 27, 26, -147, 43, -85, 131, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0, |
| 140 | /* 2884 */ 319, -2, 1, 44, 1, 51, 43, -74, 32, 1, 43, -75, 114, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0, |
| 141 | /* 2934 */ 52, 1, 43, -75, 74, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0, |
| 142 | /* 2969 */ 318, 1, 1, 42, 1, 51, 43, -73, 31, 1, 43, -74, 113, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 155, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 2, 0, |
| 143 | /* 3019 */ 52, 1, 43, -74, 73, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 132, 26, 1, 25, -101, 98, 2, 2, 2, 0, |
| 144 | /* 3055 */ 318, 1, 1, 42, 1, 51, 1, 43, -77, 35, 44, -78, 75, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 112, 28, 27, 26, -149, 43, -86, 134, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0, |
| 145 | /* 3105 */ 318, -1, -3, 48, 1, 51, 43, -76, 34, 1, 43, -77, 116, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0, |
| 146 | /* 3155 */ 52, 1, 43, -77, 76, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0, |
| 147 | /* 3190 */ 318, 1, -3, 46, 1, 51, 43, -75, 33, 1, 43, -76, 115, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 158, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 2, 0, |
| 148 | /* 3240 */ 52, 1, 43, -76, 75, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 135, 26, 1, 25, -103, 100, 2, 2, 2, 0, |
| 149 | /* 3276 */ 321, -1, -3, 45, 1, 51, 1, 43, -68, 26, 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0, |
| 150 | /* 3325 */ 52, 43, -68, 26, 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0, |
| 151 | /* 3364 */ 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 123, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0, |
| 152 | /* 3392 */ 52, 43, -70, 28, 44, -71, 110, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 94, 2, 2, 0, |
| 153 | /* 3431 */ 44, -71, 70, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 94, 2, 2, 0, |
| 154 | /* 3459 */ 52, 43, -69, 27, 44, -70, 109, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 100, 28, 27, 26, -141, 43, -82, 149, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 0, |
| 155 | /* 3498 */ 43, -69, 110, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 150, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 0, |
| 156 | /* 3526 */ 44, -70, 69, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 100, 28, 27, 26, -141, 43, -82, 126, 26, 1, 25, -97, 94, 2, 2, 0, |
| 157 | /* 3555 */ 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 127, 26, 1, 25, -97, 94, 2, 2, 0, |
| 158 | /* 3574 */ 52, 1, 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0, |
| 159 | /* 3609 */ 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0, |
| 160 | /* 3638 */ 320, 1, -3, 44, 1, 51, 43, -67, 25, 1, 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 93, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0, |
| 161 | /* 3684 */ 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 123, 26, 1, 25, -95, 94, 2, 2, 0, |
| 162 | /* 3703 */ 52, 43, -72, 30, 44, -73, 112, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 96, 2, 2, 0, |
| 163 | /* 3742 */ 44, -73, 72, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 96, 2, 2, 0, |
| 164 | /* 3770 */ 52, 43, -71, 29, 44, -72, 111, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 103, 28, 27, 26, -143, 43, -83, 152, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 0, |
| 165 | /* 3809 */ 43, -71, 112, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 153, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 0, |
| 166 | /* 3837 */ 44, -72, 71, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 103, 28, 27, 26, -143, 43, -83, 129, 26, 1, 25, -99, 96, 2, 2, 0, |
| 167 | /* 3866 */ 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 130, 26, 1, 25, -99, 96, 2, 2, 0, |
| 168 | /* 3885 */ 43, -70, 111, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 126, 26, 1, 25, -97, 96, 2, 2, 0, |
| 169 | /* 3914 */ 52, 43, -74, 32, 44, -75, 114, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 98, 2, 2, 0, |
| 170 | /* 3953 */ 44, -75, 74, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 98, 2, 2, 0, |
| 171 | /* 3981 */ 52, 43, -73, 31, 44, -74, 113, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 106, 28, 27, 26, -145, 43, -84, 155, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 0, |
| 172 | /* 4020 */ 43, -73, 114, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 156, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 0, |
| 173 | /* 4048 */ 44, -74, 73, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 106, 28, 27, 26, -145, 43, -84, 132, 26, 1, 25, -101, 98, 2, 2, 0, |
| 174 | /* 4077 */ 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 133, 26, 1, 25, -101, 98, 2, 2, 0, |
| 175 | /* 4096 */ 43, -72, 113, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 129, 26, 1, 25, -99, 98, 2, 2, 0, |
| 176 | /* 4125 */ 52, 43, -76, 34, 44, -77, 116, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 100, 2, 2, 0, |
| 177 | /* 4164 */ 44, -77, 76, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 100, 2, 2, 0, |
| 178 | /* 4192 */ 52, 43, -75, 33, 44, -76, 115, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 109, 28, 27, 26, -147, 43, -85, 158, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 0, |
| 179 | /* 4231 */ 43, -75, 116, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 159, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 0, |
| 180 | /* 4259 */ 44, -76, 75, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 109, 28, 27, 26, -147, 43, -85, 135, 26, 1, 25, -103, 100, 2, 2, 0, |
| 181 | /* 4288 */ 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 136, 26, 1, 25, -103, 100, 2, 2, 0, |
| 182 | /* 4307 */ 43, -74, 115, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 132, 26, 1, 25, -101, 100, 2, 2, 0, |
| 183 | /* 4336 */ 317, 1, 1, 43, 1, 51, 43, -77, 35, 1, 43, -78, 117, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 161, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0, |
| 184 | /* 4385 */ 52, 43, -77, 35, 44, -78, 117, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 112, 28, 27, 26, -149, 43, -86, 161, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0, |
| 185 | /* 4424 */ 43, -77, 118, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 162, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0, |
| 186 | /* 4452 */ 319, -2, 1, 44, 1, 51, 1, 43, -78, 36, 44, -79, 76, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0, |
| 187 | /* 4498 */ 52, 1, 43, -78, 77, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0, |
| 188 | /* 4533 */ 44, -78, 77, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 112, 28, 27, 26, -149, 43, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0, |
| 189 | /* 4562 */ 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 139, 26, 1, 25, -105, 102, 2, 2, 0, |
| 190 | /* 4581 */ 43, -76, 117, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 135, 26, 1, 25, -103, 102, 2, 2, 0, |
| 191 | /* 4610 */ -1, -3, 73, 1, 51, 1, 42, -81, 37, 55, -86, 74, 2, 0, |
| 192 | /* 4624 */ 1, 1, 67, 1, 50, 1, 42, -81, 40, 43, -82, 79, 2, 0, |
| 193 | /* 4638 */ 1, -3, 69, 1, 50, 1, 42, -82, 41, 43, -83, 80, 2, 0, |
| 194 | /* 4652 */ 51, 1, 42, -81, 80, 2, 0, |
| 195 | /* 4659 */ 1, 1, 64, 1, 50, 1, 42, -83, 42, 43, -84, 81, 2, 0, |
| 196 | /* 4673 */ -2, 1, 68, 1, 50, 42, -81, 40, 1, 42, -82, 81, 2, 0, |
| 197 | /* 4687 */ 51, 1, 42, -82, 81, 2, 0, |
| 198 | /* 4694 */ 1, -3, 66, 1, 50, 1, 42, -84, 43, 43, -85, 82, 2, 0, |
| 199 | /* 4708 */ -1, -3, 70, 1, 50, 42, -82, 41, 1, 42, -83, 82, 2, 0, |
| 200 | /* 4722 */ 51, 1, 42, -83, 82, 2, 0, |
| 201 | /* 4729 */ 1, 1, 61, 1, 50, 1, 42, -85, 44, 43, -86, 83, 2, 0, |
| 202 | /* 4743 */ -2, 1, 65, 1, 50, 42, -83, 42, 1, 42, -84, 83, 2, 0, |
| 203 | /* 4757 */ 51, 1, 42, -84, 83, 2, 0, |
| 204 | /* 4764 */ -1, -3, 67, 1, 50, 42, -84, 43, 1, 42, -85, 84, 2, 0, |
| 205 | /* 4778 */ 51, 1, 42, -85, 84, 2, 0, |
| 206 | /* 4785 */ -69, 110, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 150, 25, -95, 73, 26, -97, 94, 2, 0, |
| 207 | /* 4807 */ 27, 26, -25, 26, 25, -138, 42, -81, 153, 26, -97, 94, 2, 0, |
| 208 | /* 4821 */ 44, -68, 110, 28, 27, 26, -139, 43, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 209 | /* 4849 */ -68, 110, 28, 27, 26, -139, 43, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 210 | /* 4872 */ 321, 1, -3, 43, 1, 51, 1, 43, -67, 25, 44, -68, 110, 28, 27, 26, -139, 43, -81, 51, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 211 | /* 4915 */ 321, -2, 1, 42, 1, 52, 1, 43, -67, 22, 72, -80, 52, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 212 | /* 4951 */ 52, 1, 43, -67, 66, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 213 | /* 4979 */ 52, 43, -67, 25, 44, -68, 110, 28, 27, 26, -139, 43, -81, 93, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 214 | /* 5014 */ 43, -67, 108, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0, |
| 215 | /* 5038 */ 28, 27, 26, -139, 43, -81, 123, 26, 1, 25, -95, 94, 2, 0, |
| 216 | /* 5052 */ -71, 112, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 153, 25, -97, 75, 26, -99, 96, 2, 0, |
| 217 | /* 5074 */ 27, 26, -25, 26, 25, -140, 42, -82, 156, 26, -99, 96, 2, 0, |
| 218 | /* 5088 */ -70, 111, 27, 26, 25, -138, 42, -81, 100, 28, 27, 26, -141, 43, -82, 126, 26, 1, 25, -97, 96, 2, 0, |
| 219 | /* 5111 */ 27, 26, 25, -138, 42, -81, 127, 26, 1, 25, -97, 96, 2, 0, |
| 220 | /* 5125 */ 27, 1, 26, 1, 25, -139, 43, -81, 150, 25, -95, 96, 2, 0, |
| 221 | /* 5139 */ -73, 114, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 156, 25, -99, 77, 26, -101, 98, 2, 0, |
| 222 | /* 5161 */ 27, 26, -25, 26, 25, -142, 42, -83, 159, 26, -101, 98, 2, 0, |
| 223 | /* 5175 */ -72, 113, 27, 26, 25, -140, 42, -82, 103, 28, 27, 26, -143, 43, -83, 129, 26, 1, 25, -99, 98, 2, 0, |
| 224 | /* 5198 */ 27, 26, 25, -140, 42, -82, 130, 26, 1, 25, -99, 98, 2, 0, |
| 225 | /* 5212 */ 27, 1, 26, 1, 25, -141, 43, -82, 153, 25, -97, 98, 2, 0, |
| 226 | /* 5226 */ -75, 116, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 159, 25, -101, 79, 26, -103, 100, 2, 0, |
| 227 | /* 5248 */ 27, 26, -25, 26, 25, -144, 42, -84, 162, 26, -103, 100, 2, 0, |
| 228 | /* 5262 */ -74, 115, 27, 26, 25, -142, 42, -83, 106, 28, 27, 26, -145, 43, -84, 132, 26, 1, 25, -101, 100, 2, 0, |
| 229 | /* 5285 */ 27, 26, 25, -142, 42, -83, 133, 26, 1, 25, -101, 100, 2, 0, |
| 230 | /* 5299 */ 27, 1, 26, 1, 25, -143, 43, -83, 156, 25, -99, 100, 2, 0, |
| 231 | /* 5313 */ -77, 118, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 162, 25, -103, 81, 26, -105, 102, 2, 0, |
| 232 | /* 5335 */ 27, 26, -25, 26, 25, -146, 42, -85, 165, 26, -105, 102, 2, 0, |
| 233 | /* 5349 */ -76, 117, 27, 26, 25, -144, 42, -84, 109, 28, 27, 26, -147, 43, -85, 135, 26, 1, 25, -103, 102, 2, 0, |
| 234 | /* 5372 */ 27, 26, 25, -144, 42, -84, 136, 26, 1, 25, -103, 102, 2, 0, |
| 235 | /* 5386 */ 27, 1, 26, 1, 25, -145, 43, -84, 159, 25, -101, 102, 2, 0, |
| 236 | /* 5400 */ 52, 43, -78, 36, 44, -79, 118, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 237 | /* 5435 */ 44, -79, 78, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 238 | /* 5459 */ 318, -2, 1, 45, 1, 51, 43, -78, 36, 1, 43, -79, 118, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 239 | /* 5502 */ 318, 1, -3, 46, 1, 51, 1, 43, -79, 37, 44, -80, 77, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 240 | /* 5538 */ 52, 1, 43, -79, 78, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 241 | /* 5566 */ 43, -78, 119, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 242 | /* 5594 */ -78, 119, 27, 26, 25, -146, 42, -85, 112, 28, 27, 26, -149, 43, -86, 138, 26, 1, 25, -105, 104, 2, 0, |
| 243 | /* 5617 */ 27, 26, 25, -146, 42, -85, 139, 26, 1, 25, -105, 104, 2, 0, |
| 244 | /* 5631 */ 27, 1, 26, 1, 25, -147, 43, -85, 162, 25, -103, 104, 2, 0, |
| 245 | /* 5645 */ 26, 1, 25, -96, -81, 176, 2, 0, |
| 246 | /* 5653 */ 26, 1, 25, -98, -82, 179, 2, 0, |
| 247 | /* 5661 */ 26, 1, 25, -100, -83, 182, 2, 0, |
| 248 | /* 5669 */ 26, 1, 25, -102, -84, 185, 2, 0, |
| 249 | /* 5677 */ 26, 1, 25, -104, -85, 188, 2, 0, |
| 250 | /* 5685 */ -3, 87, 6, 0, |
| 251 | /* 5689 */ -129, -96, 32, 32, 0, |
| 252 | /* 5694 */ 33, -193, 192, 33, 0, |
| 253 | /* 5699 */ 57, 0, |
| 254 | /* 5701 */ -3, 71, 0, |
| 255 | /* 5704 */ 1, -3, 72, 1, 52, 43, -81, 50, -13, 55, -86, 74, 0, |
| 256 | /* 5717 */ -2, 1, 72, 14, 51, -13, 55, -86, 74, 0, |
| 257 | /* 5727 */ 65, -13, 55, -86, 74, 0, |
| 258 | /* 5733 */ 52, 43, -81, 37, 55, -86, 74, 0, |
| 259 | /* 5741 */ 33, -193, 225, 75, 0, |
| 260 | /* 5746 */ 33, -193, 225, 76, 0, |
| 261 | /* 5751 */ 33, -193, 225, 77, 0, |
| 262 | /* 5756 */ 33, -193, 225, 78, 0, |
| 263 | /* 5761 */ 33, -193, 225, 79, 0, |
| 264 | /* 5766 */ 43, -81, 80, 0, |
| 265 | /* 5770 */ 33, -193, 225, 80, 0, |
| 266 | /* 5775 */ 51, 42, -81, 40, 43, -82, 81, 0, |
| 267 | /* 5783 */ 33, -193, 225, 81, 0, |
| 268 | /* 5788 */ 51, 42, -82, 41, 43, -83, 82, 0, |
| 269 | /* 5796 */ 42, -81, 82, 0, |
| 270 | /* 5800 */ 33, -193, 225, 82, 0, |
| 271 | /* 5805 */ 51, 42, -83, 42, 43, -84, 83, 0, |
| 272 | /* 5813 */ 42, -82, 83, 0, |
| 273 | /* 5817 */ 33, -193, 225, 83, 0, |
| 274 | /* 5822 */ 51, 42, -84, 43, 43, -85, 84, 0, |
| 275 | /* 5830 */ 42, -83, 84, 0, |
| 276 | /* 5834 */ 33, -193, 225, 84, 0, |
| 277 | /* 5839 */ -2, 1, 62, 1, 50, 42, -85, 44, 1, 42, -86, 85, 0, |
| 278 | /* 5852 */ 1, -3, 63, 1, 50, 1, 42, -86, 85, 0, |
| 279 | /* 5862 */ 51, 1, 42, -86, 85, 0, |
| 280 | /* 5868 */ 51, 42, -85, 44, 43, -86, 85, 0, |
| 281 | /* 5876 */ 42, -84, 85, 0, |
| 282 | /* 5880 */ 33, -193, 225, 85, 0, |
| 283 | /* 5885 */ 42, -85, 86, 0, |
| 284 | /* 5889 */ 33, -193, 225, 86, 0, |
| 285 | /* 5894 */ 33, -193, 225, 87, 0, |
| 286 | /* 5899 */ 33, -193, 225, 88, 0, |
| 287 | /* 5904 */ 33, -193, 225, 89, 0, |
| 288 | /* 5909 */ 33, -193, 225, 90, 0, |
| 289 | /* 5914 */ 1, 93, 0, |
| 290 | /* 5917 */ 27, 52, -51, 26, 50, -161, 55, -86, 143, 26, -95, 94, 0, |
| 291 | /* 5930 */ 322, -2, 1, 41, 1, 53, 44, -67, 51, -29, 72, -80, 52, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0, |
| 292 | /* 5961 */ 53, 44, -67, 22, 72, -80, 52, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0, |
| 293 | /* 5986 */ 44, -67, 66, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0, |
| 294 | /* 6007 */ -67, 108, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0, |
| 295 | /* 6025 */ 26, 25, -138, 42, -81, 153, 26, -97, 96, 0, |
| 296 | /* 6035 */ 27, 26, -139, 43, -81, 150, 25, -95, 96, 0, |
| 297 | /* 6045 */ 26, 25, -140, 42, -82, 156, 26, -99, 98, 0, |
| 298 | /* 6055 */ 27, 26, -141, 43, -82, 153, 25, -97, 98, 0, |
| 299 | /* 6065 */ 26, 25, -142, 42, -83, 159, 26, -101, 100, 0, |
| 300 | /* 6075 */ 27, 26, -143, 43, -83, 156, 25, -99, 100, 0, |
| 301 | /* 6085 */ 26, 25, -144, 42, -84, 162, 26, -103, 102, 0, |
| 302 | /* 6095 */ 27, 26, -145, 43, -84, 159, 25, -101, 102, 0, |
| 303 | /* 6105 */ 26, 25, -146, 42, -85, 165, 26, -105, 104, 0, |
| 304 | /* 6115 */ 27, 26, -147, 43, -85, 162, 25, -103, 104, 0, |
| 305 | /* 6125 */ -79, 120, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0, |
| 306 | /* 6143 */ 317, 1, -3, 47, 1, 51, 43, -79, 37, 1, 43, -80, 119, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0, |
| 307 | /* 6174 */ 52, 43, -79, 37, 44, -80, 119, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0, |
| 308 | /* 6199 */ 43, -79, 120, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0, |
| 309 | /* 6220 */ 27, 1, 26, 1, 25, -149, 43, -86, 165, 25, -105, 106, 0, |
| 310 | /* 6233 */ 27, 26, -149, 43, -86, 165, 25, -105, 106, 0, |
| 311 | /* 6243 */ -32, -32, 96, 129, 0, |
| 312 | /* 6248 */ 52, -25, 50, -106, -86, 168, 0, |
| 313 | /* 6255 */ 320, 1, 1, 41, 30, 52, -29, 72, -80, 52, 69, -27, 54, -26, 52, -25, 50, -148, 42, -86, 168, 0, |
| 314 | /* 6277 */ 82, -29, 72, -80, 52, 69, -27, 54, -26, 52, -25, 50, -148, 42, -86, 168, 0, |
| 315 | /* 6294 */ 26, -96, -81, 176, 0, |
| 316 | /* 6299 */ 25, -96, -81, 178, 0, |
| 317 | /* 6304 */ 26, -98, -82, 179, 0, |
| 318 | /* 6309 */ 25, -98, -82, 181, 0, |
| 319 | /* 6314 */ 26, -100, -83, 182, 0, |
| 320 | /* 6319 */ 25, -100, -83, 184, 0, |
| 321 | /* 6324 */ 26, -102, -84, 185, 0, |
| 322 | /* 6329 */ 25, -102, -84, 187, 0, |
| 323 | /* 6334 */ 26, -104, -85, 188, 0, |
| 324 | /* 6339 */ 25, -104, -85, 190, 0, |
| 325 | /* 6344 */ 26, 1, 25, -106, -86, 191, 0, |
| 326 | /* 6351 */ 26, -106, -86, 191, 0, |
| 327 | /* 6356 */ 27, 26, -25, 26, 25, -148, 42, -86, 191, 0, |
| 328 | /* 6366 */ 318, -1, -3, 48, 1, 51, 1, 43, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0, |
| 329 | /* 6388 */ 52, 1, 43, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0, |
| 330 | /* 6405 */ 44, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0, |
| 331 | /* 6420 */ 33, -193, 225, 0, |
| 332 | /* 6424 */ 249, 0, |
| 333 | }; |
| 334 | |
| 335 | extern const LaneBitmask RISCVLaneMaskLists[] = { |
| 336 | /* 0 */ LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000001), |
| 337 | /* 2 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), |
| 338 | /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), |
| 339 | /* 7 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), |
| 340 | /* 11 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), |
| 341 | /* 16 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), |
| 342 | /* 22 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), |
| 343 | /* 29 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), |
| 344 | /* 37 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000200), |
| 345 | /* 39 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), |
| 346 | }; |
| 347 | |
| 348 | extern const uint16_t RISCVSubRegIdxLists[] = { |
| 349 | /* 0 */ 4, 3, 2, 1, |
| 350 | /* 4 */ 5, 2, 1, |
| 351 | /* 7 */ 6, 2, 1, 7, |
| 352 | /* 11 */ 8, 9, |
| 353 | /* 13 */ 16, 8, 9, 17, 10, 11, |
| 354 | /* 19 */ 20, 16, 8, 9, 17, 10, 11, 21, 18, 12, 13, 19, 14, 15, |
| 355 | /* 33 */ 6, 2, 1, 7, 23, 22, |
| 356 | /* 39 */ 8, 9, 10, 24, 27, |
| 357 | /* 44 */ 8, 9, 10, 11, 24, 25, 27, 28, 29, |
| 358 | /* 53 */ 16, 8, 9, 17, 10, 11, 24, 25, 26, 27, 28, 29, |
| 359 | /* 65 */ 8, 9, 10, 11, 12, 24, 25, 26, 27, 28, 29, 34, 38, 42, |
| 360 | /* 79 */ 8, 9, 10, 11, 12, 13, 24, 25, 26, 27, 28, 29, 30, 34, 35, 38, 39, 42, 43, 46, |
| 361 | /* 99 */ 8, 9, 10, 11, 12, 13, 14, 24, 25, 26, 27, 28, 29, 30, 31, 34, 35, 36, 38, 39, 40, 42, 43, 44, 46, 47, 49, |
| 362 | /* 126 */ 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, |
| 363 | /* 161 */ 16, 8, 9, 17, 10, 11, 18, 12, 13, 24, 25, 26, 27, 28, 29, 30, 31, 34, 35, 38, 39, 42, 43, 46, 52, 55, |
| 364 | /* 187 */ 16, 8, 9, 17, 10, 11, 18, 12, 13, 19, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 55, 56, 57, |
| 365 | /* 232 */ 20, 16, 8, 9, 17, 10, 11, 21, 18, 12, 13, 19, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, |
| 366 | }; |
| 367 | |
| 368 | |
| 369 | #ifdef __GNUC__ |
| 370 | #pragma GCC diagnostic push |
| 371 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 372 | #endif |
| 373 | extern const char RISCVRegStrings[] = { |
| 374 | /* 0 */ "T10\000" |
| 375 | /* 4 */ "V3_V4_V5_V6_V7_V8_V9_V10\000" |
| 376 | /* 29 */ "X10\000" |
| 377 | /* 33 */ "V13_V14_V15_V16_V17_V18_V19_V20\000" |
| 378 | /* 65 */ "X20\000" |
| 379 | /* 69 */ "V23_V24_V25_V26_V27_V28_V29_V30\000" |
| 380 | /* 101 */ "X30\000" |
| 381 | /* 105 */ "M0\000" |
| 382 | /* 108 */ "T0\000" |
| 383 | /* 111 */ "V0\000" |
| 384 | /* 114 */ "DUMMY_REG_PAIR_WITH_X0\000" |
| 385 | /* 137 */ "T11\000" |
| 386 | /* 141 */ "V4_V5_V6_V7_V8_V9_V10_V11\000" |
| 387 | /* 167 */ "X10_X11\000" |
| 388 | /* 175 */ "V14_V15_V16_V17_V18_V19_V20_V21\000" |
| 389 | /* 207 */ "X20_X21\000" |
| 390 | /* 215 */ "V24_V25_V26_V27_V28_V29_V30_V31\000" |
| 391 | /* 247 */ "X30_X31\000" |
| 392 | /* 255 */ "M1\000" |
| 393 | /* 258 */ "T1\000" |
| 394 | /* 261 */ "V0_V1\000" |
| 395 | /* 267 */ "X1\000" |
| 396 | /* 270 */ "T12\000" |
| 397 | /* 274 */ "V5_V6_V7_V8_V9_V10_V11_V12\000" |
| 398 | /* 301 */ "X12\000" |
| 399 | /* 305 */ "V15_V16_V17_V18_V19_V20_V21_V22\000" |
| 400 | /* 337 */ "X22\000" |
| 401 | /* 341 */ "V4M2_V6M2_V8M2_V10M2\000" |
| 402 | /* 362 */ "V14M2_V16M2_V18M2_V20M2\000" |
| 403 | /* 386 */ "V24M2_V26M2_V28M2_V30M2\000" |
| 404 | /* 410 */ "V0M2\000" |
| 405 | /* 415 */ "V6M2_V8M2_V10M2_V12M2\000" |
| 406 | /* 437 */ "V16M2_V18M2_V20M2_V22M2\000" |
| 407 | /* 461 */ "V0M2_V2M2\000" |
| 408 | /* 471 */ "V8M2_V10M2_V12M2_V14M2\000" |
| 409 | /* 494 */ "V18M2_V20M2_V22M2_V24M2\000" |
| 410 | /* 518 */ "V0M2_V2M2_V4M2\000" |
| 411 | /* 533 */ "V10M2_V12M2_V14M2_V16M2\000" |
| 412 | /* 557 */ "V20M2_V22M2_V24M2_V26M2\000" |
| 413 | /* 581 */ "V0M2_V2M2_V4M2_V6M2\000" |
| 414 | /* 601 */ "V12M2_V14M2_V16M2_V18M2\000" |
| 415 | /* 625 */ "V22M2_V24M2_V26M2_V28M2\000" |
| 416 | /* 649 */ "V2M2_V4M2_V6M2_V8M2\000" |
| 417 | /* 669 */ "F10_Q2\000" |
| 418 | /* 676 */ "F20_Q2\000" |
| 419 | /* 683 */ "F30_Q2\000" |
| 420 | /* 690 */ "F0_Q2\000" |
| 421 | /* 696 */ "F11_Q2\000" |
| 422 | /* 703 */ "F21_Q2\000" |
| 423 | /* 710 */ "F31_Q2\000" |
| 424 | /* 717 */ "F1_Q2\000" |
| 425 | /* 723 */ "F12_Q2\000" |
| 426 | /* 730 */ "F22_Q2\000" |
| 427 | /* 737 */ "F2_Q2\000" |
| 428 | /* 743 */ "F13_Q2\000" |
| 429 | /* 750 */ "F23_Q2\000" |
| 430 | /* 757 */ "F3_Q2\000" |
| 431 | /* 763 */ "F14_Q2\000" |
| 432 | /* 770 */ "F24_Q2\000" |
| 433 | /* 777 */ "F4_Q2\000" |
| 434 | /* 783 */ "F15_Q2\000" |
| 435 | /* 790 */ "F25_Q2\000" |
| 436 | /* 797 */ "F5_Q2\000" |
| 437 | /* 803 */ "F16_Q2\000" |
| 438 | /* 810 */ "F26_Q2\000" |
| 439 | /* 817 */ "F6_Q2\000" |
| 440 | /* 823 */ "F17_Q2\000" |
| 441 | /* 830 */ "F27_Q2\000" |
| 442 | /* 837 */ "F7_Q2\000" |
| 443 | /* 843 */ "F18_Q2\000" |
| 444 | /* 850 */ "F28_Q2\000" |
| 445 | /* 857 */ "F8_Q2\000" |
| 446 | /* 863 */ "F19_Q2\000" |
| 447 | /* 870 */ "F29_Q2\000" |
| 448 | /* 877 */ "F9_Q2\000" |
| 449 | /* 883 */ "T2\000" |
| 450 | /* 886 */ "V0_V1_V2\000" |
| 451 | /* 895 */ "X2\000" |
| 452 | /* 898 */ "T13\000" |
| 453 | /* 902 */ "V6_V7_V8_V9_V10_V11_V12_V13\000" |
| 454 | /* 930 */ "X12_X13\000" |
| 455 | /* 938 */ "V16_V17_V18_V19_V20_V21_V22_V23\000" |
| 456 | /* 970 */ "X22_X23\000" |
| 457 | /* 978 */ "M3\000" |
| 458 | /* 981 */ "T3\000" |
| 459 | /* 984 */ "V0_V1_V2_V3\000" |
| 460 | /* 996 */ "X2_X3\000" |
| 461 | /* 1002 */ "T14\000" |
| 462 | /* 1006 */ "V7_V8_V9_V10_V11_V12_V13_V14\000" |
| 463 | /* 1035 */ "X14\000" |
| 464 | /* 1039 */ "V17_V18_V19_V20_V21_V22_V23_V24\000" |
| 465 | /* 1071 */ "X24\000" |
| 466 | /* 1075 */ "V16M4_V20M4\000" |
| 467 | /* 1087 */ "V0M4\000" |
| 468 | /* 1092 */ "V8M4_V12M4\000" |
| 469 | /* 1103 */ "V20M4_V24M4\000" |
| 470 | /* 1115 */ "V0M4_V4M4\000" |
| 471 | /* 1125 */ "V12M4_V16M4\000" |
| 472 | /* 1137 */ "V24M4_V28M4\000" |
| 473 | /* 1149 */ "V4M4_V8M4\000" |
| 474 | /* 1159 */ "T4\000" |
| 475 | /* 1162 */ "V0_V1_V2_V3_V4\000" |
| 476 | /* 1177 */ "X4\000" |
| 477 | /* 1180 */ "T15\000" |
| 478 | /* 1184 */ "V8_V9_V10_V11_V12_V13_V14_V15\000" |
| 479 | /* 1214 */ "X14_X15\000" |
| 480 | /* 1222 */ "V18_V19_V20_V21_V22_V23_V24_V25\000" |
| 481 | /* 1254 */ "X24_X25\000" |
| 482 | /* 1262 */ "M5\000" |
| 483 | /* 1265 */ "T5\000" |
| 484 | /* 1268 */ "V0_V1_V2_V3_V4_V5\000" |
| 485 | /* 1286 */ "X4_X5\000" |
| 486 | /* 1292 */ "V9_V10_V11_V12_V13_V14_V15_V16\000" |
| 487 | /* 1323 */ "X16\000" |
| 488 | /* 1327 */ "V19_V20_V21_V22_V23_V24_V25_V26\000" |
| 489 | /* 1359 */ "X26\000" |
| 490 | /* 1363 */ "M6\000" |
| 491 | /* 1366 */ "T6\000" |
| 492 | /* 1369 */ "V0_V1_V2_V3_V4_V5_V6\000" |
| 493 | /* 1390 */ "X6\000" |
| 494 | /* 1393 */ "V10_V11_V12_V13_V14_V15_V16_V17\000" |
| 495 | /* 1425 */ "X16_X17\000" |
| 496 | /* 1433 */ "V20_V21_V22_V23_V24_V25_V26_V27\000" |
| 497 | /* 1465 */ "X26_X27\000" |
| 498 | /* 1473 */ "M7\000" |
| 499 | /* 1476 */ "T7\000" |
| 500 | /* 1479 */ "V0_V1_V2_V3_V4_V5_V6_V7\000" |
| 501 | /* 1503 */ "X6_X7\000" |
| 502 | /* 1509 */ "V11_V12_V13_V14_V15_V16_V17_V18\000" |
| 503 | /* 1541 */ "X18\000" |
| 504 | /* 1545 */ "V21_V22_V23_V24_V25_V26_V27_V28\000" |
| 505 | /* 1577 */ "X28\000" |
| 506 | /* 1581 */ "V0M8\000" |
| 507 | /* 1586 */ "V24M8\000" |
| 508 | /* 1592 */ "V16M8\000" |
| 509 | /* 1598 */ "V8M8\000" |
| 510 | /* 1603 */ "T8\000" |
| 511 | /* 1606 */ "V1_V2_V3_V4_V5_V6_V7_V8\000" |
| 512 | /* 1630 */ "X8\000" |
| 513 | /* 1633 */ "V12_V13_V14_V15_V16_V17_V18_V19\000" |
| 514 | /* 1665 */ "X18_X19\000" |
| 515 | /* 1673 */ "V22_V23_V24_V25_V26_V27_V28_V29\000" |
| 516 | /* 1705 */ "X28_X29\000" |
| 517 | /* 1713 */ "T9\000" |
| 518 | /* 1716 */ "V2_V3_V4_V5_V6_V7_V8_V9\000" |
| 519 | /* 1740 */ "X8_X9\000" |
| 520 | /* 1746 */ "VLENB\000" |
| 521 | /* 1752 */ "F10_D\000" |
| 522 | /* 1758 */ "F20_D\000" |
| 523 | /* 1764 */ "F30_D\000" |
| 524 | /* 1770 */ "F0_D\000" |
| 525 | /* 1775 */ "F11_D\000" |
| 526 | /* 1781 */ "F21_D\000" |
| 527 | /* 1787 */ "F31_D\000" |
| 528 | /* 1793 */ "F1_D\000" |
| 529 | /* 1798 */ "F12_D\000" |
| 530 | /* 1804 */ "F22_D\000" |
| 531 | /* 1810 */ "F2_D\000" |
| 532 | /* 1815 */ "F13_D\000" |
| 533 | /* 1821 */ "F23_D\000" |
| 534 | /* 1827 */ "F3_D\000" |
| 535 | /* 1832 */ "F14_D\000" |
| 536 | /* 1838 */ "F24_D\000" |
| 537 | /* 1844 */ "F4_D\000" |
| 538 | /* 1849 */ "F15_D\000" |
| 539 | /* 1855 */ "F25_D\000" |
| 540 | /* 1861 */ "F5_D\000" |
| 541 | /* 1866 */ "F16_D\000" |
| 542 | /* 1872 */ "F26_D\000" |
| 543 | /* 1878 */ "F6_D\000" |
| 544 | /* 1883 */ "F17_D\000" |
| 545 | /* 1889 */ "F27_D\000" |
| 546 | /* 1895 */ "F7_D\000" |
| 547 | /* 1900 */ "F18_D\000" |
| 548 | /* 1906 */ "F28_D\000" |
| 549 | /* 1912 */ "F8_D\000" |
| 550 | /* 1917 */ "F19_D\000" |
| 551 | /* 1923 */ "F29_D\000" |
| 552 | /* 1929 */ "F9_D\000" |
| 553 | /* 1934 */ "VTYPE\000" |
| 554 | /* 1940 */ "SF_VCIX_STATE\000" |
| 555 | /* 1954 */ "F10_F\000" |
| 556 | /* 1960 */ "F20_F\000" |
| 557 | /* 1966 */ "F30_F\000" |
| 558 | /* 1972 */ "F0_F\000" |
| 559 | /* 1977 */ "F11_F\000" |
| 560 | /* 1983 */ "F21_F\000" |
| 561 | /* 1989 */ "F31_F\000" |
| 562 | /* 1995 */ "F1_F\000" |
| 563 | /* 2000 */ "F12_F\000" |
| 564 | /* 2006 */ "F22_F\000" |
| 565 | /* 2012 */ "F2_F\000" |
| 566 | /* 2017 */ "F13_F\000" |
| 567 | /* 2023 */ "F23_F\000" |
| 568 | /* 2029 */ "F3_F\000" |
| 569 | /* 2034 */ "F14_F\000" |
| 570 | /* 2040 */ "F24_F\000" |
| 571 | /* 2046 */ "F4_F\000" |
| 572 | /* 2051 */ "F15_F\000" |
| 573 | /* 2057 */ "F25_F\000" |
| 574 | /* 2063 */ "F5_F\000" |
| 575 | /* 2068 */ "F16_F\000" |
| 576 | /* 2074 */ "F26_F\000" |
| 577 | /* 2080 */ "F6_F\000" |
| 578 | /* 2085 */ "F17_F\000" |
| 579 | /* 2091 */ "F27_F\000" |
| 580 | /* 2097 */ "F7_F\000" |
| 581 | /* 2102 */ "F18_F\000" |
| 582 | /* 2108 */ "F28_F\000" |
| 583 | /* 2114 */ "F8_F\000" |
| 584 | /* 2119 */ "F19_F\000" |
| 585 | /* 2125 */ "F29_F\000" |
| 586 | /* 2131 */ "F9_F\000" |
| 587 | /* 2136 */ "F10_H\000" |
| 588 | /* 2142 */ "X10_H\000" |
| 589 | /* 2148 */ "F20_H\000" |
| 590 | /* 2154 */ "X20_H\000" |
| 591 | /* 2160 */ "F30_H\000" |
| 592 | /* 2166 */ "X30_H\000" |
| 593 | /* 2172 */ "F0_H\000" |
| 594 | /* 2177 */ "X0_H\000" |
| 595 | /* 2182 */ "F11_H\000" |
| 596 | /* 2188 */ "X11_H\000" |
| 597 | /* 2194 */ "F21_H\000" |
| 598 | /* 2200 */ "X21_H\000" |
| 599 | /* 2206 */ "F31_H\000" |
| 600 | /* 2212 */ "X31_H\000" |
| 601 | /* 2218 */ "F1_H\000" |
| 602 | /* 2223 */ "X1_H\000" |
| 603 | /* 2228 */ "F12_H\000" |
| 604 | /* 2234 */ "X12_H\000" |
| 605 | /* 2240 */ "F22_H\000" |
| 606 | /* 2246 */ "X22_H\000" |
| 607 | /* 2252 */ "F2_H\000" |
| 608 | /* 2257 */ "X2_H\000" |
| 609 | /* 2262 */ "F13_H\000" |
| 610 | /* 2268 */ "X13_H\000" |
| 611 | /* 2274 */ "F23_H\000" |
| 612 | /* 2280 */ "X23_H\000" |
| 613 | /* 2286 */ "F3_H\000" |
| 614 | /* 2291 */ "X3_H\000" |
| 615 | /* 2296 */ "F14_H\000" |
| 616 | /* 2302 */ "X14_H\000" |
| 617 | /* 2308 */ "F24_H\000" |
| 618 | /* 2314 */ "X24_H\000" |
| 619 | /* 2320 */ "F4_H\000" |
| 620 | /* 2325 */ "X4_H\000" |
| 621 | /* 2330 */ "F15_H\000" |
| 622 | /* 2336 */ "X15_H\000" |
| 623 | /* 2342 */ "F25_H\000" |
| 624 | /* 2348 */ "X25_H\000" |
| 625 | /* 2354 */ "F5_H\000" |
| 626 | /* 2359 */ "X5_H\000" |
| 627 | /* 2364 */ "F16_H\000" |
| 628 | /* 2370 */ "X16_H\000" |
| 629 | /* 2376 */ "F26_H\000" |
| 630 | /* 2382 */ "X26_H\000" |
| 631 | /* 2388 */ "F6_H\000" |
| 632 | /* 2393 */ "X6_H\000" |
| 633 | /* 2398 */ "F17_H\000" |
| 634 | /* 2404 */ "X17_H\000" |
| 635 | /* 2410 */ "F27_H\000" |
| 636 | /* 2416 */ "X27_H\000" |
| 637 | /* 2422 */ "F7_H\000" |
| 638 | /* 2427 */ "X7_H\000" |
| 639 | /* 2432 */ "F18_H\000" |
| 640 | /* 2438 */ "X18_H\000" |
| 641 | /* 2444 */ "F28_H\000" |
| 642 | /* 2450 */ "X28_H\000" |
| 643 | /* 2456 */ "F8_H\000" |
| 644 | /* 2461 */ "X8_H\000" |
| 645 | /* 2466 */ "F19_H\000" |
| 646 | /* 2472 */ "X19_H\000" |
| 647 | /* 2478 */ "F29_H\000" |
| 648 | /* 2484 */ "X29_H\000" |
| 649 | /* 2490 */ "F9_H\000" |
| 650 | /* 2495 */ "X9_H\000" |
| 651 | /* 2500 */ "VL\000" |
| 652 | /* 2503 */ "FRM\000" |
| 653 | /* 2507 */ "VXRM\000" |
| 654 | /* 2512 */ "SSP\000" |
| 655 | /* 2516 */ "F10_Q\000" |
| 656 | /* 2522 */ "F20_Q\000" |
| 657 | /* 2528 */ "F30_Q\000" |
| 658 | /* 2534 */ "F0_Q\000" |
| 659 | /* 2539 */ "F11_Q\000" |
| 660 | /* 2545 */ "F21_Q\000" |
| 661 | /* 2551 */ "F31_Q\000" |
| 662 | /* 2557 */ "F1_Q\000" |
| 663 | /* 2562 */ "F12_Q\000" |
| 664 | /* 2568 */ "F22_Q\000" |
| 665 | /* 2574 */ "F2_Q\000" |
| 666 | /* 2579 */ "F13_Q\000" |
| 667 | /* 2585 */ "F23_Q\000" |
| 668 | /* 2591 */ "F3_Q\000" |
| 669 | /* 2596 */ "F14_Q\000" |
| 670 | /* 2602 */ "F24_Q\000" |
| 671 | /* 2608 */ "F4_Q\000" |
| 672 | /* 2613 */ "F15_Q\000" |
| 673 | /* 2619 */ "F25_Q\000" |
| 674 | /* 2625 */ "F5_Q\000" |
| 675 | /* 2630 */ "F16_Q\000" |
| 676 | /* 2636 */ "F26_Q\000" |
| 677 | /* 2642 */ "F6_Q\000" |
| 678 | /* 2647 */ "F17_Q\000" |
| 679 | /* 2653 */ "F27_Q\000" |
| 680 | /* 2659 */ "F7_Q\000" |
| 681 | /* 2664 */ "F18_Q\000" |
| 682 | /* 2670 */ "F28_Q\000" |
| 683 | /* 2676 */ "F8_Q\000" |
| 684 | /* 2681 */ "F19_Q\000" |
| 685 | /* 2687 */ "F29_Q\000" |
| 686 | /* 2693 */ "F9_Q\000" |
| 687 | /* 2698 */ "FCSR\000" |
| 688 | /* 2703 */ "FFLAGS\000" |
| 689 | /* 2710 */ "VXSAT\000" |
| 690 | /* 2716 */ "X10_W\000" |
| 691 | /* 2722 */ "X20_W\000" |
| 692 | /* 2728 */ "X30_W\000" |
| 693 | /* 2734 */ "X0_W\000" |
| 694 | /* 2739 */ "X11_W\000" |
| 695 | /* 2745 */ "X21_W\000" |
| 696 | /* 2751 */ "X31_W\000" |
| 697 | /* 2757 */ "X1_W\000" |
| 698 | /* 2762 */ "X12_W\000" |
| 699 | /* 2768 */ "X22_W\000" |
| 700 | /* 2774 */ "X2_W\000" |
| 701 | /* 2779 */ "X13_W\000" |
| 702 | /* 2785 */ "X23_W\000" |
| 703 | /* 2791 */ "X3_W\000" |
| 704 | /* 2796 */ "X14_W\000" |
| 705 | /* 2802 */ "X24_W\000" |
| 706 | /* 2808 */ "X4_W\000" |
| 707 | /* 2813 */ "X15_W\000" |
| 708 | /* 2819 */ "X25_W\000" |
| 709 | /* 2825 */ "X5_W\000" |
| 710 | /* 2830 */ "X16_W\000" |
| 711 | /* 2836 */ "X26_W\000" |
| 712 | /* 2842 */ "X6_W\000" |
| 713 | /* 2847 */ "X17_W\000" |
| 714 | /* 2853 */ "X27_W\000" |
| 715 | /* 2859 */ "X7_W\000" |
| 716 | /* 2864 */ "X18_W\000" |
| 717 | /* 2870 */ "X28_W\000" |
| 718 | /* 2876 */ "X8_W\000" |
| 719 | /* 2881 */ "X19_W\000" |
| 720 | /* 2887 */ "X29_W\000" |
| 721 | /* 2893 */ "X9_W\000" |
| 722 | /* 2898 */ "X10_Y\000" |
| 723 | /* 2904 */ "X20_Y\000" |
| 724 | /* 2910 */ "X30_Y\000" |
| 725 | /* 2916 */ "X0_Y\000" |
| 726 | /* 2921 */ "X11_Y\000" |
| 727 | /* 2927 */ "X21_Y\000" |
| 728 | /* 2933 */ "X31_Y\000" |
| 729 | /* 2939 */ "X1_Y\000" |
| 730 | /* 2944 */ "X12_Y\000" |
| 731 | /* 2950 */ "X22_Y\000" |
| 732 | /* 2956 */ "X2_Y\000" |
| 733 | /* 2961 */ "X13_Y\000" |
| 734 | /* 2967 */ "X23_Y\000" |
| 735 | /* 2973 */ "X3_Y\000" |
| 736 | /* 2978 */ "X14_Y\000" |
| 737 | /* 2984 */ "X24_Y\000" |
| 738 | /* 2990 */ "X4_Y\000" |
| 739 | /* 2995 */ "X15_Y\000" |
| 740 | /* 3001 */ "X25_Y\000" |
| 741 | /* 3007 */ "X5_Y\000" |
| 742 | /* 3012 */ "X16_Y\000" |
| 743 | /* 3018 */ "X26_Y\000" |
| 744 | /* 3024 */ "X6_Y\000" |
| 745 | /* 3029 */ "X17_Y\000" |
| 746 | /* 3035 */ "X27_Y\000" |
| 747 | /* 3041 */ "X7_Y\000" |
| 748 | /* 3046 */ "X18_Y\000" |
| 749 | /* 3052 */ "X28_Y\000" |
| 750 | /* 3058 */ "X8_Y\000" |
| 751 | /* 3063 */ "X19_Y\000" |
| 752 | /* 3069 */ "X29_Y\000" |
| 753 | /* 3075 */ "X9_Y\000" |
| 754 | /* 3080 */ "X0_Pair\000" |
| 755 | }; |
| 756 | #ifdef __GNUC__ |
| 757 | #pragma GCC diagnostic pop |
| 758 | #endif |
| 759 | |
| 760 | extern const MCRegisterDesc RISCVRegDesc[] = { // Descriptors |
| 761 | { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 762 | { .Name: 2698, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16384, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 763 | { .Name: 2703, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16385, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 764 | { .Name: 2503, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16386, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 765 | { .Name: 1940, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16387, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 766 | { .Name: 2512, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16388, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 767 | { .Name: 2500, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16389, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 768 | { .Name: 1746, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16390, .RegUnitLaneMasks: 39, .IsConstant: 1, .IsArtificial: 0 }, |
| 769 | { .Name: 1934, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16391, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 770 | { .Name: 2507, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16392, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 771 | { .Name: 2710, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16393, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 772 | { .Name: 114, .SubRegs: 4, .SuperRegs: 6424, .SubRegIndices: 4, .RegUnits: 16394, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 773 | { .Name: 105, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16395, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 774 | { .Name: 255, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16396, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 775 | { .Name: 359, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16397, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 776 | { .Name: 978, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16398, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 777 | { .Name: 1084, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16399, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 778 | { .Name: 1262, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16400, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 779 | { .Name: 1363, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16401, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 780 | { .Name: 1473, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16402, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 781 | { .Name: 108, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16403, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 782 | { .Name: 258, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16404, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 783 | { .Name: 883, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16405, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 784 | { .Name: 981, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16406, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 785 | { .Name: 1159, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16407, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 786 | { .Name: 1265, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16408, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 787 | { .Name: 1366, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16409, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 788 | { .Name: 1476, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16410, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 789 | { .Name: 1603, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16411, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 790 | { .Name: 1713, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16412, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 791 | { .Name: 0, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16413, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 792 | { .Name: 137, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16414, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 793 | { .Name: 270, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16415, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 794 | { .Name: 898, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16416, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 795 | { .Name: 1002, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16417, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 796 | { .Name: 1180, .SubRegs: 4, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16418, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 797 | { .Name: 111, .SubRegs: 4, .SuperRegs: 36, .SubRegIndices: 4, .RegUnits: 16419, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 798 | { .Name: 264, .SubRegs: 4, .SuperRegs: 6255, .SubRegIndices: 4, .RegUnits: 16420, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 799 | { .Name: 892, .SubRegs: 4, .SuperRegs: 5930, .SubRegIndices: 4, .RegUnits: 16421, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 800 | { .Name: 993, .SubRegs: 4, .SuperRegs: 4915, .SubRegIndices: 4, .RegUnits: 16422, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 801 | { .Name: 1174, .SubRegs: 4, .SuperRegs: 4872, .SubRegIndices: 4, .RegUnits: 16423, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 802 | { .Name: 1283, .SubRegs: 4, .SuperRegs: 3638, .SubRegIndices: 4, .RegUnits: 16424, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 803 | { .Name: 1387, .SubRegs: 4, .SuperRegs: 3276, .SubRegIndices: 4, .RegUnits: 16425, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 804 | { .Name: 1500, .SubRegs: 4, .SuperRegs: 2107, .SubRegIndices: 4, .RegUnits: 16426, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 805 | { .Name: 1627, .SubRegs: 4, .SuperRegs: 2157, .SubRegIndices: 4, .RegUnits: 16427, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 806 | { .Name: 1737, .SubRegs: 4, .SuperRegs: 2427, .SubRegIndices: 4, .RegUnits: 16428, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 807 | { .Name: 25, .SubRegs: 4, .SuperRegs: 2057, .SubRegIndices: 4, .RegUnits: 16429, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 808 | { .Name: 163, .SubRegs: 4, .SuperRegs: 2342, .SubRegIndices: 4, .RegUnits: 16430, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 809 | { .Name: 297, .SubRegs: 4, .SuperRegs: 2292, .SubRegIndices: 4, .RegUnits: 16431, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 810 | { .Name: 926, .SubRegs: 4, .SuperRegs: 2698, .SubRegIndices: 4, .RegUnits: 16432, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 811 | { .Name: 1031, .SubRegs: 4, .SuperRegs: 2242, .SubRegIndices: 4, .RegUnits: 16433, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 812 | { .Name: 1210, .SubRegs: 4, .SuperRegs: 2613, .SubRegIndices: 4, .RegUnits: 16434, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 813 | { .Name: 1319, .SubRegs: 4, .SuperRegs: 2563, .SubRegIndices: 4, .RegUnits: 16435, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 814 | { .Name: 1421, .SubRegs: 4, .SuperRegs: 2969, .SubRegIndices: 4, .RegUnits: 16436, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 815 | { .Name: 1537, .SubRegs: 4, .SuperRegs: 2513, .SubRegIndices: 4, .RegUnits: 16437, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 816 | { .Name: 1661, .SubRegs: 4, .SuperRegs: 2884, .SubRegIndices: 4, .RegUnits: 16438, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 817 | { .Name: 61, .SubRegs: 4, .SuperRegs: 2834, .SubRegIndices: 4, .RegUnits: 16439, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 818 | { .Name: 203, .SubRegs: 4, .SuperRegs: 3190, .SubRegIndices: 4, .RegUnits: 16440, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 819 | { .Name: 333, .SubRegs: 4, .SuperRegs: 2784, .SubRegIndices: 4, .RegUnits: 16441, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 820 | { .Name: 966, .SubRegs: 4, .SuperRegs: 3105, .SubRegIndices: 4, .RegUnits: 16442, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 821 | { .Name: 1067, .SubRegs: 4, .SuperRegs: 3055, .SubRegIndices: 4, .RegUnits: 16443, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 822 | { .Name: 1250, .SubRegs: 4, .SuperRegs: 4336, .SubRegIndices: 4, .RegUnits: 16444, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 823 | { .Name: 1355, .SubRegs: 4, .SuperRegs: 4452, .SubRegIndices: 4, .RegUnits: 16445, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 824 | { .Name: 1461, .SubRegs: 4, .SuperRegs: 5459, .SubRegIndices: 4, .RegUnits: 16446, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 825 | { .Name: 1573, .SubRegs: 4, .SuperRegs: 5502, .SubRegIndices: 4, .RegUnits: 16447, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 826 | { .Name: 1701, .SubRegs: 4, .SuperRegs: 6143, .SubRegIndices: 4, .RegUnits: 16448, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 827 | { .Name: 97, .SubRegs: 4, .SuperRegs: 6366, .SubRegIndices: 4, .RegUnits: 16449, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 828 | { .Name: 243, .SubRegs: 4, .SuperRegs: 21, .SubRegIndices: 4, .RegUnits: 16450, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 829 | { .Name: 134, .SubRegs: 1437, .SuperRegs: 5696, .SubRegIndices: 2, .RegUnits: 16451, .RegUnitLaneMasks: 1, .IsConstant: 1, .IsArtificial: 0 }, |
| 830 | { .Name: 267, .SubRegs: 1437, .SuperRegs: 6422, .SubRegIndices: 2, .RegUnits: 16452, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 831 | { .Name: 895, .SubRegs: 1437, .SuperRegs: 5911, .SubRegIndices: 2, .RegUnits: 16453, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 832 | { .Name: 999, .SubRegs: 1437, .SuperRegs: 5906, .SubRegIndices: 2, .RegUnits: 16454, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 833 | { .Name: 1177, .SubRegs: 1437, .SuperRegs: 5906, .SubRegIndices: 2, .RegUnits: 16455, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 834 | { .Name: 1289, .SubRegs: 1437, .SuperRegs: 5901, .SubRegIndices: 2, .RegUnits: 16456, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 835 | { .Name: 1390, .SubRegs: 1437, .SuperRegs: 5901, .SubRegIndices: 2, .RegUnits: 16457, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 836 | { .Name: 1506, .SubRegs: 1437, .SuperRegs: 5896, .SubRegIndices: 2, .RegUnits: 16458, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 837 | { .Name: 1630, .SubRegs: 1437, .SuperRegs: 5896, .SubRegIndices: 2, .RegUnits: 16459, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 838 | { .Name: 1743, .SubRegs: 1437, .SuperRegs: 5891, .SubRegIndices: 2, .RegUnits: 16460, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 839 | { .Name: 29, .SubRegs: 1437, .SuperRegs: 5891, .SubRegIndices: 2, .RegUnits: 16461, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 840 | { .Name: 171, .SubRegs: 1437, .SuperRegs: 5882, .SubRegIndices: 2, .RegUnits: 16462, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 841 | { .Name: 301, .SubRegs: 1437, .SuperRegs: 5882, .SubRegIndices: 2, .RegUnits: 16463, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 842 | { .Name: 934, .SubRegs: 1437, .SuperRegs: 5836, .SubRegIndices: 2, .RegUnits: 16464, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 843 | { .Name: 1035, .SubRegs: 1437, .SuperRegs: 5836, .SubRegIndices: 2, .RegUnits: 16465, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 844 | { .Name: 1218, .SubRegs: 1437, .SuperRegs: 5819, .SubRegIndices: 2, .RegUnits: 16466, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 845 | { .Name: 1323, .SubRegs: 1437, .SuperRegs: 5819, .SubRegIndices: 2, .RegUnits: 16467, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 846 | { .Name: 1429, .SubRegs: 1437, .SuperRegs: 5802, .SubRegIndices: 2, .RegUnits: 16468, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 847 | { .Name: 1541, .SubRegs: 1437, .SuperRegs: 5802, .SubRegIndices: 2, .RegUnits: 16469, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 848 | { .Name: 1669, .SubRegs: 1437, .SuperRegs: 5785, .SubRegIndices: 2, .RegUnits: 16470, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 849 | { .Name: 65, .SubRegs: 1437, .SuperRegs: 5785, .SubRegIndices: 2, .RegUnits: 16471, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 850 | { .Name: 211, .SubRegs: 1437, .SuperRegs: 5772, .SubRegIndices: 2, .RegUnits: 16472, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 851 | { .Name: 337, .SubRegs: 1437, .SuperRegs: 5772, .SubRegIndices: 2, .RegUnits: 16473, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 852 | { .Name: 974, .SubRegs: 1437, .SuperRegs: 5763, .SubRegIndices: 2, .RegUnits: 16474, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 853 | { .Name: 1071, .SubRegs: 1437, .SuperRegs: 5763, .SubRegIndices: 2, .RegUnits: 16475, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 854 | { .Name: 1258, .SubRegs: 1437, .SuperRegs: 5758, .SubRegIndices: 2, .RegUnits: 16476, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 855 | { .Name: 1359, .SubRegs: 1437, .SuperRegs: 5758, .SubRegIndices: 2, .RegUnits: 16477, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 856 | { .Name: 1469, .SubRegs: 1437, .SuperRegs: 5753, .SubRegIndices: 2, .RegUnits: 16478, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 857 | { .Name: 1577, .SubRegs: 1437, .SuperRegs: 5753, .SubRegIndices: 2, .RegUnits: 16479, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 858 | { .Name: 1709, .SubRegs: 1437, .SuperRegs: 5748, .SubRegIndices: 2, .RegUnits: 16480, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 859 | { .Name: 101, .SubRegs: 1437, .SuperRegs: 5748, .SubRegIndices: 2, .RegUnits: 16481, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 860 | { .Name: 251, .SubRegs: 1437, .SuperRegs: 5743, .SubRegIndices: 2, .RegUnits: 16482, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 861 | { .Name: 1770, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16483, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 862 | { .Name: 1793, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16484, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 863 | { .Name: 1810, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16485, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 864 | { .Name: 1827, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16486, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 865 | { .Name: 1844, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16487, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 866 | { .Name: 1861, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16488, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 867 | { .Name: 1878, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16489, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 868 | { .Name: 1895, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16490, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 869 | { .Name: 1912, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16491, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 870 | { .Name: 1929, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16492, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 871 | { .Name: 1752, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16493, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 872 | { .Name: 1775, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16494, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 873 | { .Name: 1798, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16495, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 874 | { .Name: 1815, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16496, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 875 | { .Name: 1832, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16497, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 876 | { .Name: 1849, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16498, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 877 | { .Name: 1866, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16499, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 878 | { .Name: 1883, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16500, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 879 | { .Name: 1900, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16501, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 880 | { .Name: 1917, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16502, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 881 | { .Name: 1758, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16503, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 882 | { .Name: 1781, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16504, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 883 | { .Name: 1804, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16505, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 884 | { .Name: 1821, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16506, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 885 | { .Name: 1838, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16507, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 886 | { .Name: 1855, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16508, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 887 | { .Name: 1872, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16509, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 888 | { .Name: 1889, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16510, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 889 | { .Name: 1906, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16511, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 890 | { .Name: 1923, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16512, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 891 | { .Name: 1764, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16513, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 892 | { .Name: 1787, .SubRegs: 5691, .SuperRegs: 6245, .SubRegIndices: 2, .RegUnits: 16514, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 893 | { .Name: 1972, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16483, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 894 | { .Name: 1995, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16484, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 895 | { .Name: 2012, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16485, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 896 | { .Name: 2029, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16486, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 897 | { .Name: 2046, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16487, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 898 | { .Name: 2063, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16488, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 899 | { .Name: 2080, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16489, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 900 | { .Name: 2097, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16490, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 901 | { .Name: 2114, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16491, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 902 | { .Name: 2131, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16492, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 903 | { .Name: 1954, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16493, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 904 | { .Name: 1977, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16494, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 905 | { .Name: 2000, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16495, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 906 | { .Name: 2017, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16496, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 907 | { .Name: 2034, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16497, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 908 | { .Name: 2051, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16498, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 909 | { .Name: 2068, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16499, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 910 | { .Name: 2085, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16500, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 911 | { .Name: 2102, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16501, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 912 | { .Name: 2119, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16502, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 913 | { .Name: 1960, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16503, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 914 | { .Name: 1983, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16504, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 915 | { .Name: 2006, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16505, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 916 | { .Name: 2023, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16506, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 917 | { .Name: 2040, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16507, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 918 | { .Name: 2057, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16508, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 919 | { .Name: 2074, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16509, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 920 | { .Name: 2091, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16510, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 921 | { .Name: 2108, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16511, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 922 | { .Name: 2125, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16512, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 923 | { .Name: 1966, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16513, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 924 | { .Name: 1989, .SubRegs: 5692, .SuperRegs: 6244, .SubRegIndices: 3, .RegUnits: 16514, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 925 | { .Name: 2172, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16483, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 926 | { .Name: 2218, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16484, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 927 | { .Name: 2252, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16485, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 928 | { .Name: 2286, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16486, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 929 | { .Name: 2320, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16487, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 930 | { .Name: 2354, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16488, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 931 | { .Name: 2388, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16489, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 932 | { .Name: 2422, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16490, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 933 | { .Name: 2456, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16491, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 934 | { .Name: 2490, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16492, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 935 | { .Name: 2136, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16493, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 936 | { .Name: 2182, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16494, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 937 | { .Name: 2228, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16495, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 938 | { .Name: 2262, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16496, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 939 | { .Name: 2296, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16497, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 940 | { .Name: 2330, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16498, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 941 | { .Name: 2364, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16499, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 942 | { .Name: 2398, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16500, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 943 | { .Name: 2432, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16501, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 944 | { .Name: 2466, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16502, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 945 | { .Name: 2148, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16503, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 946 | { .Name: 2194, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16504, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 947 | { .Name: 2240, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16505, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 948 | { .Name: 2274, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16506, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 949 | { .Name: 2308, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16507, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 950 | { .Name: 2342, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16508, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 951 | { .Name: 2376, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16509, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 952 | { .Name: 2410, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16510, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 953 | { .Name: 2444, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16511, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 954 | { .Name: 2478, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16512, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 955 | { .Name: 2160, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16513, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 956 | { .Name: 2206, .SubRegs: 4, .SuperRegs: 6243, .SubRegIndices: 4, .RegUnits: 16514, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 957 | { .Name: 2534, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16483, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 958 | { .Name: 2557, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16484, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 959 | { .Name: 2574, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16485, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 960 | { .Name: 2591, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16486, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 961 | { .Name: 2608, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16487, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 962 | { .Name: 2625, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16488, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 963 | { .Name: 2642, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16489, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 964 | { .Name: 2659, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16490, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 965 | { .Name: 2676, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16491, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 966 | { .Name: 2693, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16492, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 967 | { .Name: 2516, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16493, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 968 | { .Name: 2539, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16494, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 969 | { .Name: 2562, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16495, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 970 | { .Name: 2579, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16496, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 971 | { .Name: 2596, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16497, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 972 | { .Name: 2613, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16498, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 973 | { .Name: 2630, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16499, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 974 | { .Name: 2647, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16500, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 975 | { .Name: 2664, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16501, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 976 | { .Name: 2681, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16502, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 977 | { .Name: 2522, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16503, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 978 | { .Name: 2545, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16504, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 979 | { .Name: 2568, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16505, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 980 | { .Name: 2585, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16506, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 981 | { .Name: 2602, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16507, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 982 | { .Name: 2619, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16508, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 983 | { .Name: 2636, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16509, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 984 | { .Name: 2653, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16510, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 985 | { .Name: 2670, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16511, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 986 | { .Name: 2687, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16512, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 987 | { .Name: 2528, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16513, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 988 | { .Name: 2551, .SubRegs: 5690, .SuperRegs: 6246, .SubRegIndices: 1, .RegUnits: 16514, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 989 | { .Name: 2177, .SubRegs: 4, .SuperRegs: 5694, .SubRegIndices: 4, .RegUnits: 16451, .RegUnitLaneMasks: 39, .IsConstant: 1, .IsArtificial: 0 }, |
| 990 | { .Name: 2223, .SubRegs: 4, .SuperRegs: 6420, .SubRegIndices: 4, .RegUnits: 16452, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 991 | { .Name: 2257, .SubRegs: 4, .SuperRegs: 5909, .SubRegIndices: 4, .RegUnits: 16453, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 992 | { .Name: 2291, .SubRegs: 4, .SuperRegs: 5904, .SubRegIndices: 4, .RegUnits: 16454, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 993 | { .Name: 2325, .SubRegs: 4, .SuperRegs: 5904, .SubRegIndices: 4, .RegUnits: 16455, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 994 | { .Name: 2359, .SubRegs: 4, .SuperRegs: 5899, .SubRegIndices: 4, .RegUnits: 16456, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 995 | { .Name: 2393, .SubRegs: 4, .SuperRegs: 5899, .SubRegIndices: 4, .RegUnits: 16457, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 996 | { .Name: 2427, .SubRegs: 4, .SuperRegs: 5894, .SubRegIndices: 4, .RegUnits: 16458, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 997 | { .Name: 2461, .SubRegs: 4, .SuperRegs: 5894, .SubRegIndices: 4, .RegUnits: 16459, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 998 | { .Name: 2495, .SubRegs: 4, .SuperRegs: 5889, .SubRegIndices: 4, .RegUnits: 16460, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 999 | { .Name: 2142, .SubRegs: 4, .SuperRegs: 5889, .SubRegIndices: 4, .RegUnits: 16461, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1000 | { .Name: 2188, .SubRegs: 4, .SuperRegs: 5880, .SubRegIndices: 4, .RegUnits: 16462, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1001 | { .Name: 2234, .SubRegs: 4, .SuperRegs: 5880, .SubRegIndices: 4, .RegUnits: 16463, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1002 | { .Name: 2268, .SubRegs: 4, .SuperRegs: 5834, .SubRegIndices: 4, .RegUnits: 16464, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1003 | { .Name: 2302, .SubRegs: 4, .SuperRegs: 5834, .SubRegIndices: 4, .RegUnits: 16465, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1004 | { .Name: 2336, .SubRegs: 4, .SuperRegs: 5817, .SubRegIndices: 4, .RegUnits: 16466, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1005 | { .Name: 2370, .SubRegs: 4, .SuperRegs: 5817, .SubRegIndices: 4, .RegUnits: 16467, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1006 | { .Name: 2404, .SubRegs: 4, .SuperRegs: 5800, .SubRegIndices: 4, .RegUnits: 16468, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1007 | { .Name: 2438, .SubRegs: 4, .SuperRegs: 5800, .SubRegIndices: 4, .RegUnits: 16469, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1008 | { .Name: 2472, .SubRegs: 4, .SuperRegs: 5783, .SubRegIndices: 4, .RegUnits: 16470, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1009 | { .Name: 2154, .SubRegs: 4, .SuperRegs: 5783, .SubRegIndices: 4, .RegUnits: 16471, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1010 | { .Name: 2200, .SubRegs: 4, .SuperRegs: 5770, .SubRegIndices: 4, .RegUnits: 16472, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1011 | { .Name: 2246, .SubRegs: 4, .SuperRegs: 5770, .SubRegIndices: 4, .RegUnits: 16473, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1012 | { .Name: 2280, .SubRegs: 4, .SuperRegs: 5761, .SubRegIndices: 4, .RegUnits: 16474, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1013 | { .Name: 2314, .SubRegs: 4, .SuperRegs: 5761, .SubRegIndices: 4, .RegUnits: 16475, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1014 | { .Name: 2348, .SubRegs: 4, .SuperRegs: 5756, .SubRegIndices: 4, .RegUnits: 16476, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1015 | { .Name: 2382, .SubRegs: 4, .SuperRegs: 5756, .SubRegIndices: 4, .RegUnits: 16477, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1016 | { .Name: 2416, .SubRegs: 4, .SuperRegs: 5751, .SubRegIndices: 4, .RegUnits: 16478, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1017 | { .Name: 2450, .SubRegs: 4, .SuperRegs: 5751, .SubRegIndices: 4, .RegUnits: 16479, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1018 | { .Name: 2484, .SubRegs: 4, .SuperRegs: 5746, .SubRegIndices: 4, .RegUnits: 16480, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1019 | { .Name: 2166, .SubRegs: 4, .SuperRegs: 5746, .SubRegIndices: 4, .RegUnits: 16481, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1020 | { .Name: 2212, .SubRegs: 4, .SuperRegs: 5741, .SubRegIndices: 4, .RegUnits: 16482, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 }, |
| 1021 | { .Name: 3080, .SubRegs: 0, .SuperRegs: 4, .SubRegIndices: 7, .RegUnits: 23343114, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 1022 | { .Name: 2734, .SubRegs: 1438, .SuperRegs: 5695, .SubRegIndices: 3, .RegUnits: 16451, .RegUnitLaneMasks: 1, .IsConstant: 1, .IsArtificial: 0 }, |
| 1023 | { .Name: 2757, .SubRegs: 1438, .SuperRegs: 6421, .SubRegIndices: 3, .RegUnits: 16452, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1024 | { .Name: 2774, .SubRegs: 1438, .SuperRegs: 5910, .SubRegIndices: 3, .RegUnits: 16453, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1025 | { .Name: 2791, .SubRegs: 1438, .SuperRegs: 5905, .SubRegIndices: 3, .RegUnits: 16454, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1026 | { .Name: 2808, .SubRegs: 1438, .SuperRegs: 5905, .SubRegIndices: 3, .RegUnits: 16455, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1027 | { .Name: 2825, .SubRegs: 1438, .SuperRegs: 5900, .SubRegIndices: 3, .RegUnits: 16456, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1028 | { .Name: 2842, .SubRegs: 1438, .SuperRegs: 5900, .SubRegIndices: 3, .RegUnits: 16457, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1029 | { .Name: 2859, .SubRegs: 1438, .SuperRegs: 5895, .SubRegIndices: 3, .RegUnits: 16458, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1030 | { .Name: 2876, .SubRegs: 1438, .SuperRegs: 5895, .SubRegIndices: 3, .RegUnits: 16459, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1031 | { .Name: 2893, .SubRegs: 1438, .SuperRegs: 5890, .SubRegIndices: 3, .RegUnits: 16460, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1032 | { .Name: 2716, .SubRegs: 1438, .SuperRegs: 5890, .SubRegIndices: 3, .RegUnits: 16461, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1033 | { .Name: 2739, .SubRegs: 1438, .SuperRegs: 5881, .SubRegIndices: 3, .RegUnits: 16462, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1034 | { .Name: 2762, .SubRegs: 1438, .SuperRegs: 5881, .SubRegIndices: 3, .RegUnits: 16463, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1035 | { .Name: 2779, .SubRegs: 1438, .SuperRegs: 5835, .SubRegIndices: 3, .RegUnits: 16464, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1036 | { .Name: 2796, .SubRegs: 1438, .SuperRegs: 5835, .SubRegIndices: 3, .RegUnits: 16465, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1037 | { .Name: 2813, .SubRegs: 1438, .SuperRegs: 5818, .SubRegIndices: 3, .RegUnits: 16466, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1038 | { .Name: 2830, .SubRegs: 1438, .SuperRegs: 5818, .SubRegIndices: 3, .RegUnits: 16467, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1039 | { .Name: 2847, .SubRegs: 1438, .SuperRegs: 5801, .SubRegIndices: 3, .RegUnits: 16468, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1040 | { .Name: 2864, .SubRegs: 1438, .SuperRegs: 5801, .SubRegIndices: 3, .RegUnits: 16469, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1041 | { .Name: 2881, .SubRegs: 1438, .SuperRegs: 5784, .SubRegIndices: 3, .RegUnits: 16470, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1042 | { .Name: 2722, .SubRegs: 1438, .SuperRegs: 5784, .SubRegIndices: 3, .RegUnits: 16471, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1043 | { .Name: 2745, .SubRegs: 1438, .SuperRegs: 5771, .SubRegIndices: 3, .RegUnits: 16472, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1044 | { .Name: 2768, .SubRegs: 1438, .SuperRegs: 5771, .SubRegIndices: 3, .RegUnits: 16473, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1045 | { .Name: 2785, .SubRegs: 1438, .SuperRegs: 5762, .SubRegIndices: 3, .RegUnits: 16474, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1046 | { .Name: 2802, .SubRegs: 1438, .SuperRegs: 5762, .SubRegIndices: 3, .RegUnits: 16475, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1047 | { .Name: 2819, .SubRegs: 1438, .SuperRegs: 5757, .SubRegIndices: 3, .RegUnits: 16476, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1048 | { .Name: 2836, .SubRegs: 1438, .SuperRegs: 5757, .SubRegIndices: 3, .RegUnits: 16477, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1049 | { .Name: 2853, .SubRegs: 1438, .SuperRegs: 5752, .SubRegIndices: 3, .RegUnits: 16478, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1050 | { .Name: 2870, .SubRegs: 1438, .SuperRegs: 5752, .SubRegIndices: 3, .RegUnits: 16479, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1051 | { .Name: 2887, .SubRegs: 1438, .SuperRegs: 5747, .SubRegIndices: 3, .RegUnits: 16480, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1052 | { .Name: 2728, .SubRegs: 1438, .SuperRegs: 5747, .SubRegIndices: 3, .RegUnits: 16481, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1053 | { .Name: 2751, .SubRegs: 1438, .SuperRegs: 5742, .SubRegIndices: 3, .RegUnits: 16482, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1054 | { .Name: 2916, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16451, .RegUnitLaneMasks: 1, .IsConstant: 1, .IsArtificial: 0 }, |
| 1055 | { .Name: 2939, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16452, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1056 | { .Name: 2956, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16453, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1057 | { .Name: 2973, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16454, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1058 | { .Name: 2990, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16455, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1059 | { .Name: 3007, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16456, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1060 | { .Name: 3024, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16457, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1061 | { .Name: 3041, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16458, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1062 | { .Name: 3058, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16459, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1063 | { .Name: 3075, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16460, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1064 | { .Name: 2898, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16461, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1065 | { .Name: 2921, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16462, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1066 | { .Name: 2944, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16463, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1067 | { .Name: 2961, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16464, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1068 | { .Name: 2978, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16465, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1069 | { .Name: 2995, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16466, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1070 | { .Name: 3012, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16467, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1071 | { .Name: 3029, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16468, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1072 | { .Name: 3046, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16469, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1073 | { .Name: 3063, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16470, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1074 | { .Name: 2904, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16471, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1075 | { .Name: 2927, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16472, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1076 | { .Name: 2950, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16473, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1077 | { .Name: 2967, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16474, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1078 | { .Name: 2984, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16475, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1079 | { .Name: 3001, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16476, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1080 | { .Name: 3018, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16477, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1081 | { .Name: 3035, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16478, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1082 | { .Name: 3052, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16479, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1083 | { .Name: 3069, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16480, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1084 | { .Name: 2910, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16481, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1085 | { .Name: 2933, .SubRegs: 1436, .SuperRegs: 4, .SubRegIndices: 4, .RegUnits: 16482, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1086 | { .Name: 690, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16483, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1087 | { .Name: 717, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16484, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1088 | { .Name: 737, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16485, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1089 | { .Name: 757, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16486, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1090 | { .Name: 777, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16487, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1091 | { .Name: 797, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16488, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1092 | { .Name: 817, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16489, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1093 | { .Name: 837, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16490, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1094 | { .Name: 857, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16491, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1095 | { .Name: 877, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16492, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1096 | { .Name: 669, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16493, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1097 | { .Name: 696, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16494, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1098 | { .Name: 723, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16495, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1099 | { .Name: 743, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16496, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1100 | { .Name: 763, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16497, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1101 | { .Name: 783, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16498, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1102 | { .Name: 803, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16499, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1103 | { .Name: 823, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16500, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1104 | { .Name: 843, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16501, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1105 | { .Name: 863, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16502, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1106 | { .Name: 676, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16503, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1107 | { .Name: 703, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16504, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1108 | { .Name: 730, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16505, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1109 | { .Name: 750, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16506, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1110 | { .Name: 770, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16507, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1111 | { .Name: 790, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16508, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1112 | { .Name: 810, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16509, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1113 | { .Name: 830, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16510, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1114 | { .Name: 850, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16511, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1115 | { .Name: 870, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16512, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1116 | { .Name: 683, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16513, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1117 | { .Name: 710, .SubRegs: 5689, .SuperRegs: 4, .SubRegIndices: 0, .RegUnits: 16514, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 }, |
| 1118 | { .Name: 410, .SubRegs: 1603, .SuperRegs: 58, .SubRegIndices: 11, .RegUnits: 6467619, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1119 | { .Name: 1087, .SubRegs: 1584, .SuperRegs: 5914, .SubRegIndices: 13, .RegUnits: 6864931, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1120 | { .Name: 1581, .SubRegs: 1591, .SuperRegs: 4, .SubRegIndices: 19, .RegUnits: 6848547, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1121 | { .Name: 466, .SubRegs: 1588, .SuperRegs: 5717, .SubRegIndices: 11, .RegUnits: 6467621, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1122 | { .Name: 528, .SubRegs: 1603, .SuperRegs: 5704, .SubRegIndices: 11, .RegUnits: 6467623, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1123 | { .Name: 1120, .SubRegs: 1599, .SuperRegs: 5685, .SubRegIndices: 13, .RegUnits: 6864935, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1124 | { .Name: 596, .SubRegs: 1603, .SuperRegs: 4610, .SubRegIndices: 11, .RegUnits: 6467625, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1125 | { .Name: 664, .SubRegs: 1625, .SuperRegs: 4624, .SubRegIndices: 11, .RegUnits: 6467627, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1126 | { .Name: 1154, .SubRegs: 1606, .SuperRegs: 2043, .SubRegIndices: 13, .RegUnits: 6864939, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1127 | { .Name: 1598, .SubRegs: 1613, .SuperRegs: 4, .SubRegIndices: 19, .RegUnits: 6848555, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1128 | { .Name: 356, .SubRegs: 1603, .SuperRegs: 4673, .SubRegIndices: 11, .RegUnits: 6467629, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1129 | { .Name: 431, .SubRegs: 1625, .SuperRegs: 4638, .SubRegIndices: 11, .RegUnits: 6467631, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1130 | { .Name: 1097, .SubRegs: 1621, .SuperRegs: 2047, .SubRegIndices: 13, .RegUnits: 6864943, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1131 | { .Name: 488, .SubRegs: 1625, .SuperRegs: 4708, .SubRegIndices: 11, .RegUnits: 6467633, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1132 | { .Name: 551, .SubRegs: 1647, .SuperRegs: 4659, .SubRegIndices: 11, .RegUnits: 6467635, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1133 | { .Name: 1131, .SubRegs: 1628, .SuperRegs: 2035, .SubRegIndices: 13, .RegUnits: 6864947, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1134 | { .Name: 1592, .SubRegs: 1635, .SuperRegs: 4, .SubRegIndices: 19, .RegUnits: 6848563, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1135 | { .Name: 619, .SubRegs: 1625, .SuperRegs: 4743, .SubRegIndices: 11, .RegUnits: 6467637, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1136 | { .Name: 380, .SubRegs: 1647, .SuperRegs: 4694, .SubRegIndices: 11, .RegUnits: 6467639, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1137 | { .Name: 1081, .SubRegs: 1643, .SuperRegs: 2039, .SubRegIndices: 13, .RegUnits: 6864951, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1138 | { .Name: 455, .SubRegs: 1647, .SuperRegs: 4764, .SubRegIndices: 11, .RegUnits: 6467641, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1139 | { .Name: 512, .SubRegs: 1669, .SuperRegs: 4729, .SubRegIndices: 11, .RegUnits: 6467643, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1140 | { .Name: 1109, .SubRegs: 1650, .SuperRegs: 2031, .SubRegIndices: 13, .RegUnits: 6864955, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1141 | { .Name: 1586, .SubRegs: 1657, .SuperRegs: 4, .SubRegIndices: 19, .RegUnits: 6848571, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1142 | { .Name: 575, .SubRegs: 1647, .SuperRegs: 5839, .SubRegIndices: 11, .RegUnits: 6467645, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1143 | { .Name: 643, .SubRegs: 1669, .SuperRegs: 5852, .SubRegIndices: 11, .RegUnits: 6467647, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1144 | { .Name: 1143, .SubRegs: 1665, .SuperRegs: 5701, .SubRegIndices: 13, .RegUnits: 6864959, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1145 | { .Name: 404, .SubRegs: 1669, .SuperRegs: 51, .SubRegIndices: 11, .RegUnits: 6467649, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1146 | { .Name: 996, .SubRegs: 1440, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467653, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1147 | { .Name: 1286, .SubRegs: 1447, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467655, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1148 | { .Name: 1503, .SubRegs: 1454, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467657, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1149 | { .Name: 1740, .SubRegs: 1461, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467659, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1150 | { .Name: 167, .SubRegs: 1468, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467661, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1151 | { .Name: 930, .SubRegs: 1475, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467663, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1152 | { .Name: 1214, .SubRegs: 1482, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467665, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1153 | { .Name: 1425, .SubRegs: 1489, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467667, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1154 | { .Name: 1665, .SubRegs: 1496, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467669, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1155 | { .Name: 207, .SubRegs: 1503, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467671, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1156 | { .Name: 970, .SubRegs: 1510, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467673, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1157 | { .Name: 1254, .SubRegs: 1517, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467675, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1158 | { .Name: 1465, .SubRegs: 1524, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467677, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1159 | { .Name: 1705, .SubRegs: 1531, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467679, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1160 | { .Name: 247, .SubRegs: 1538, .SuperRegs: 4, .SubRegIndices: 33, .RegUnits: 6467681, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 }, |
| 1161 | { .Name: 889, .SubRegs: 1581, .SuperRegs: 6277, .SubRegIndices: 11, .RegUnits: 6467620, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1162 | { .Name: 990, .SubRegs: 1581, .SuperRegs: 5961, .SubRegIndices: 11, .RegUnits: 6467621, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1163 | { .Name: 1171, .SubRegs: 1581, .SuperRegs: 4951, .SubRegIndices: 11, .RegUnits: 6467622, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1164 | { .Name: 1280, .SubRegs: 1581, .SuperRegs: 4979, .SubRegIndices: 11, .RegUnits: 6467623, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1165 | { .Name: 1384, .SubRegs: 1581, .SuperRegs: 3574, .SubRegIndices: 11, .RegUnits: 6467624, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1166 | { .Name: 1497, .SubRegs: 1581, .SuperRegs: 3325, .SubRegIndices: 11, .RegUnits: 6467625, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1167 | { .Name: 1624, .SubRegs: 1581, .SuperRegs: 2207, .SubRegIndices: 11, .RegUnits: 6467626, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1168 | { .Name: 1734, .SubRegs: 1581, .SuperRegs: 3459, .SubRegIndices: 11, .RegUnits: 6467627, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1169 | { .Name: 22, .SubRegs: 1581, .SuperRegs: 2477, .SubRegIndices: 11, .RegUnits: 6467628, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1170 | { .Name: 159, .SubRegs: 1581, .SuperRegs: 3392, .SubRegIndices: 11, .RegUnits: 6467629, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1171 | { .Name: 293, .SubRegs: 1581, .SuperRegs: 2392, .SubRegIndices: 11, .RegUnits: 6467630, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1172 | { .Name: 922, .SubRegs: 1581, .SuperRegs: 3770, .SubRegIndices: 11, .RegUnits: 6467631, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1173 | { .Name: 1027, .SubRegs: 1581, .SuperRegs: 2748, .SubRegIndices: 11, .RegUnits: 6467632, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1174 | { .Name: 1206, .SubRegs: 1581, .SuperRegs: 3703, .SubRegIndices: 11, .RegUnits: 6467633, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1175 | { .Name: 1315, .SubRegs: 1581, .SuperRegs: 2663, .SubRegIndices: 11, .RegUnits: 6467634, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1176 | { .Name: 1417, .SubRegs: 1581, .SuperRegs: 3981, .SubRegIndices: 11, .RegUnits: 6467635, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1177 | { .Name: 1533, .SubRegs: 1581, .SuperRegs: 3019, .SubRegIndices: 11, .RegUnits: 6467636, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1178 | { .Name: 1657, .SubRegs: 1581, .SuperRegs: 3914, .SubRegIndices: 11, .RegUnits: 6467637, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1179 | { .Name: 57, .SubRegs: 1581, .SuperRegs: 2934, .SubRegIndices: 11, .RegUnits: 6467638, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1180 | { .Name: 199, .SubRegs: 1581, .SuperRegs: 4192, .SubRegIndices: 11, .RegUnits: 6467639, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1181 | { .Name: 329, .SubRegs: 1581, .SuperRegs: 3240, .SubRegIndices: 11, .RegUnits: 6467640, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1182 | { .Name: 962, .SubRegs: 1581, .SuperRegs: 4125, .SubRegIndices: 11, .RegUnits: 6467641, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1183 | { .Name: 1063, .SubRegs: 1581, .SuperRegs: 3155, .SubRegIndices: 11, .RegUnits: 6467642, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1184 | { .Name: 1246, .SubRegs: 1581, .SuperRegs: 4385, .SubRegIndices: 11, .RegUnits: 6467643, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1185 | { .Name: 1351, .SubRegs: 1581, .SuperRegs: 4498, .SubRegIndices: 11, .RegUnits: 6467644, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1186 | { .Name: 1457, .SubRegs: 1581, .SuperRegs: 5400, .SubRegIndices: 11, .RegUnits: 6467645, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1187 | { .Name: 1569, .SubRegs: 1581, .SuperRegs: 5538, .SubRegIndices: 11, .RegUnits: 6467646, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1188 | { .Name: 1697, .SubRegs: 1581, .SuperRegs: 6174, .SubRegIndices: 11, .RegUnits: 6467647, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1189 | { .Name: 93, .SubRegs: 1581, .SuperRegs: 6388, .SubRegIndices: 11, .RegUnits: 6467648, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1190 | { .Name: 239, .SubRegs: 1581, .SuperRegs: 25, .SubRegIndices: 11, .RegUnits: 6467649, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1191 | { .Name: 261, .SubRegs: 1578, .SuperRegs: 25, .SubRegIndices: 11, .RegUnits: 6467619, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 }, |
| 1192 | { .Name: 523, .SubRegs: 293, .SuperRegs: 5727, .SubRegIndices: 53, .RegUnits: 6864933, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1193 | { .Name: 591, .SubRegs: 306, .SuperRegs: 5733, .SubRegIndices: 53, .RegUnits: 6864935, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1194 | { .Name: 659, .SubRegs: 332, .SuperRegs: 4652, .SubRegIndices: 53, .RegUnits: 6864937, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1195 | { .Name: 351, .SubRegs: 319, .SuperRegs: 5775, .SubRegIndices: 53, .RegUnits: 6864939, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1196 | { .Name: 425, .SubRegs: 345, .SuperRegs: 4687, .SubRegIndices: 53, .RegUnits: 6864941, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1197 | { .Name: 482, .SubRegs: 358, .SuperRegs: 5788, .SubRegIndices: 53, .RegUnits: 6864943, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1198 | { .Name: 545, .SubRegs: 384, .SuperRegs: 4722, .SubRegIndices: 53, .RegUnits: 6864945, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1199 | { .Name: 613, .SubRegs: 371, .SuperRegs: 5805, .SubRegIndices: 53, .RegUnits: 6864947, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1200 | { .Name: 374, .SubRegs: 397, .SuperRegs: 4757, .SubRegIndices: 53, .RegUnits: 6864949, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1201 | { .Name: 449, .SubRegs: 410, .SuperRegs: 5822, .SubRegIndices: 53, .RegUnits: 6864951, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1202 | { .Name: 506, .SubRegs: 436, .SuperRegs: 4778, .SubRegIndices: 53, .RegUnits: 6864953, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1203 | { .Name: 569, .SubRegs: 423, .SuperRegs: 5868, .SubRegIndices: 53, .RegUnits: 6864955, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1204 | { .Name: 637, .SubRegs: 449, .SuperRegs: 5862, .SubRegIndices: 53, .RegUnits: 6864957, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1205 | { .Name: 398, .SubRegs: 462, .SuperRegs: 54, .SubRegIndices: 53, .RegUnits: 6864959, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1206 | { .Name: 461, .SubRegs: 110, .SuperRegs: 54, .SubRegIndices: 53, .RegUnits: 6864931, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1207 | { .Name: 1149, .SubRegs: 789, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848551, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1208 | { .Name: 1092, .SubRegs: 740, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848555, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1209 | { .Name: 1125, .SubRegs: 691, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848559, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1210 | { .Name: 1075, .SubRegs: 642, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848563, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1211 | { .Name: 1103, .SubRegs: 593, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848567, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1212 | { .Name: 1137, .SubRegs: 544, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848571, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1213 | { .Name: 1115, .SubRegs: 495, .SuperRegs: 4, .SubRegIndices: 232, .RegUnits: 6848547, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1214 | { .Name: 987, .SubRegs: 2051, .SuperRegs: 6262, .SubRegIndices: 39, .RegUnits: 6869028, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1215 | { .Name: 1168, .SubRegs: 2051, .SuperRegs: 5986, .SubRegIndices: 39, .RegUnits: 6869029, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1216 | { .Name: 1277, .SubRegs: 2051, .SuperRegs: 5014, .SubRegIndices: 39, .RegUnits: 6869030, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1217 | { .Name: 1381, .SubRegs: 2051, .SuperRegs: 4821, .SubRegIndices: 39, .RegUnits: 6869031, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1218 | { .Name: 1494, .SubRegs: 2051, .SuperRegs: 3609, .SubRegIndices: 39, .RegUnits: 6869032, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1219 | { .Name: 1621, .SubRegs: 2051, .SuperRegs: 3364, .SubRegIndices: 39, .RegUnits: 6869033, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1220 | { .Name: 1731, .SubRegs: 2051, .SuperRegs: 3498, .SubRegIndices: 39, .RegUnits: 6869034, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1221 | { .Name: 19, .SubRegs: 2051, .SuperRegs: 3526, .SubRegIndices: 39, .RegUnits: 6869035, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1222 | { .Name: 156, .SubRegs: 2051, .SuperRegs: 3885, .SubRegIndices: 39, .RegUnits: 6869036, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1223 | { .Name: 289, .SubRegs: 2051, .SuperRegs: 3431, .SubRegIndices: 39, .RegUnits: 6869037, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1224 | { .Name: 918, .SubRegs: 2051, .SuperRegs: 3809, .SubRegIndices: 39, .RegUnits: 6869038, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1225 | { .Name: 1023, .SubRegs: 2051, .SuperRegs: 3837, .SubRegIndices: 39, .RegUnits: 6869039, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1226 | { .Name: 1202, .SubRegs: 2051, .SuperRegs: 4096, .SubRegIndices: 39, .RegUnits: 6869040, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1227 | { .Name: 1311, .SubRegs: 2051, .SuperRegs: 3742, .SubRegIndices: 39, .RegUnits: 6869041, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1228 | { .Name: 1413, .SubRegs: 2051, .SuperRegs: 4020, .SubRegIndices: 39, .RegUnits: 6869042, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1229 | { .Name: 1529, .SubRegs: 2051, .SuperRegs: 4048, .SubRegIndices: 39, .RegUnits: 6869043, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1230 | { .Name: 1653, .SubRegs: 2051, .SuperRegs: 4307, .SubRegIndices: 39, .RegUnits: 6869044, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1231 | { .Name: 53, .SubRegs: 2051, .SuperRegs: 3953, .SubRegIndices: 39, .RegUnits: 6869045, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1232 | { .Name: 195, .SubRegs: 2051, .SuperRegs: 4231, .SubRegIndices: 39, .RegUnits: 6869046, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1233 | { .Name: 325, .SubRegs: 2051, .SuperRegs: 4259, .SubRegIndices: 39, .RegUnits: 6869047, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1234 | { .Name: 958, .SubRegs: 2051, .SuperRegs: 4581, .SubRegIndices: 39, .RegUnits: 6869048, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1235 | { .Name: 1059, .SubRegs: 2051, .SuperRegs: 4164, .SubRegIndices: 39, .RegUnits: 6869049, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1236 | { .Name: 1242, .SubRegs: 2051, .SuperRegs: 4424, .SubRegIndices: 39, .RegUnits: 6869050, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1237 | { .Name: 1347, .SubRegs: 2051, .SuperRegs: 4533, .SubRegIndices: 39, .RegUnits: 6869051, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1238 | { .Name: 1453, .SubRegs: 2051, .SuperRegs: 5566, .SubRegIndices: 39, .RegUnits: 6869052, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1239 | { .Name: 1565, .SubRegs: 2051, .SuperRegs: 5435, .SubRegIndices: 39, .RegUnits: 6869053, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1240 | { .Name: 1693, .SubRegs: 2051, .SuperRegs: 6199, .SubRegIndices: 39, .RegUnits: 6869054, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1241 | { .Name: 89, .SubRegs: 2051, .SuperRegs: 6405, .SubRegIndices: 39, .RegUnits: 6869055, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1242 | { .Name: 235, .SubRegs: 2051, .SuperRegs: 26, .SubRegIndices: 39, .RegUnits: 6869056, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1243 | { .Name: 886, .SubRegs: 1545, .SuperRegs: 26, .SubRegIndices: 39, .RegUnits: 6869027, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 }, |
| 1244 | { .Name: 586, .SubRegs: 2004, .SuperRegs: 5713, .SubRegIndices: 161, .RegUnits: 6856741, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1245 | { .Name: 654, .SubRegs: 1977, .SuperRegs: 5766, .SubRegIndices: 161, .RegUnits: 6856743, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1246 | { .Name: 346, .SubRegs: 1950, .SuperRegs: 5796, .SubRegIndices: 161, .RegUnits: 6856745, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1247 | { .Name: 420, .SubRegs: 1923, .SuperRegs: 5779, .SubRegIndices: 161, .RegUnits: 6856747, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1248 | { .Name: 476, .SubRegs: 1896, .SuperRegs: 5813, .SubRegIndices: 161, .RegUnits: 6856749, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1249 | { .Name: 539, .SubRegs: 1869, .SuperRegs: 5792, .SubRegIndices: 161, .RegUnits: 6856751, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1250 | { .Name: 607, .SubRegs: 1842, .SuperRegs: 5830, .SubRegIndices: 161, .RegUnits: 6856753, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1251 | { .Name: 368, .SubRegs: 1815, .SuperRegs: 5809, .SubRegIndices: 161, .RegUnits: 6856755, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1252 | { .Name: 443, .SubRegs: 1788, .SuperRegs: 5876, .SubRegIndices: 161, .RegUnits: 6856757, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1253 | { .Name: 500, .SubRegs: 1761, .SuperRegs: 5826, .SubRegIndices: 161, .RegUnits: 6856759, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1254 | { .Name: 563, .SubRegs: 1734, .SuperRegs: 5885, .SubRegIndices: 161, .RegUnits: 6856761, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1255 | { .Name: 631, .SubRegs: 1707, .SuperRegs: 5872, .SubRegIndices: 161, .RegUnits: 6856763, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1256 | { .Name: 392, .SubRegs: 1680, .SuperRegs: 33, .SubRegIndices: 161, .RegUnits: 6856765, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1257 | { .Name: 518, .SubRegs: 1551, .SuperRegs: 33, .SubRegIndices: 161, .RegUnits: 6856739, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1258 | { .Name: 1165, .SubRegs: 485, .SuperRegs: 6265, .SubRegIndices: 44, .RegUnits: 6864932, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1259 | { .Name: 1274, .SubRegs: 485, .SuperRegs: 6007, .SubRegIndices: 44, .RegUnits: 6864933, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1260 | { .Name: 1378, .SubRegs: 485, .SuperRegs: 4831, .SubRegIndices: 44, .RegUnits: 6864934, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1261 | { .Name: 1491, .SubRegs: 485, .SuperRegs: 4849, .SubRegIndices: 44, .RegUnits: 6864935, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1262 | { .Name: 1618, .SubRegs: 485, .SuperRegs: 3684, .SubRegIndices: 44, .RegUnits: 6864936, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1263 | { .Name: 1728, .SubRegs: 485, .SuperRegs: 4785, .SubRegIndices: 44, .RegUnits: 6864937, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1264 | { .Name: 16, .SubRegs: 485, .SuperRegs: 3555, .SubRegIndices: 44, .RegUnits: 6864938, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1265 | { .Name: 153, .SubRegs: 485, .SuperRegs: 5088, .SubRegIndices: 44, .RegUnits: 6864939, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1266 | { .Name: 286, .SubRegs: 485, .SuperRegs: 3895, .SubRegIndices: 44, .RegUnits: 6864940, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1267 | { .Name: 914, .SubRegs: 485, .SuperRegs: 5052, .SubRegIndices: 44, .RegUnits: 6864941, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1268 | { .Name: 1019, .SubRegs: 485, .SuperRegs: 3866, .SubRegIndices: 44, .RegUnits: 6864942, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1269 | { .Name: 1198, .SubRegs: 485, .SuperRegs: 5175, .SubRegIndices: 44, .RegUnits: 6864943, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1270 | { .Name: 1307, .SubRegs: 485, .SuperRegs: 4106, .SubRegIndices: 44, .RegUnits: 6864944, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1271 | { .Name: 1409, .SubRegs: 485, .SuperRegs: 5139, .SubRegIndices: 44, .RegUnits: 6864945, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1272 | { .Name: 1525, .SubRegs: 485, .SuperRegs: 4077, .SubRegIndices: 44, .RegUnits: 6864946, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1273 | { .Name: 1649, .SubRegs: 485, .SuperRegs: 5262, .SubRegIndices: 44, .RegUnits: 6864947, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1274 | { .Name: 49, .SubRegs: 485, .SuperRegs: 4317, .SubRegIndices: 44, .RegUnits: 6864948, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1275 | { .Name: 191, .SubRegs: 485, .SuperRegs: 5226, .SubRegIndices: 44, .RegUnits: 6864949, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1276 | { .Name: 321, .SubRegs: 485, .SuperRegs: 4288, .SubRegIndices: 44, .RegUnits: 6864950, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1277 | { .Name: 954, .SubRegs: 485, .SuperRegs: 5349, .SubRegIndices: 44, .RegUnits: 6864951, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1278 | { .Name: 1055, .SubRegs: 485, .SuperRegs: 4591, .SubRegIndices: 44, .RegUnits: 6864952, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1279 | { .Name: 1238, .SubRegs: 485, .SuperRegs: 5313, .SubRegIndices: 44, .RegUnits: 6864953, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1280 | { .Name: 1343, .SubRegs: 485, .SuperRegs: 4562, .SubRegIndices: 44, .RegUnits: 6864954, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1281 | { .Name: 1449, .SubRegs: 485, .SuperRegs: 5594, .SubRegIndices: 44, .RegUnits: 6864955, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1282 | { .Name: 1561, .SubRegs: 485, .SuperRegs: 5576, .SubRegIndices: 44, .RegUnits: 6864956, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1283 | { .Name: 1689, .SubRegs: 485, .SuperRegs: 6125, .SubRegIndices: 44, .RegUnits: 6864957, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1284 | { .Name: 85, .SubRegs: 485, .SuperRegs: 6376, .SubRegIndices: 44, .RegUnits: 6864958, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1285 | { .Name: 231, .SubRegs: 485, .SuperRegs: 27, .SubRegIndices: 44, .RegUnits: 6864959, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1286 | { .Name: 984, .SubRegs: 475, .SuperRegs: 27, .SubRegIndices: 44, .RegUnits: 6864931, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 }, |
| 1287 | { .Name: 649, .SubRegs: 1390, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848549, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1288 | { .Name: 341, .SubRegs: 1344, .SuperRegs: 78, .SubRegIndices: 187, .RegUnits: 6848551, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1289 | { .Name: 415, .SubRegs: 1298, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848553, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1290 | { .Name: 471, .SubRegs: 1252, .SuperRegs: 75, .SubRegIndices: 187, .RegUnits: 6848555, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1291 | { .Name: 533, .SubRegs: 1206, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848557, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1292 | { .Name: 601, .SubRegs: 1160, .SuperRegs: 72, .SubRegIndices: 187, .RegUnits: 6848559, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1293 | { .Name: 362, .SubRegs: 1114, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848561, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1294 | { .Name: 437, .SubRegs: 1068, .SuperRegs: 69, .SubRegIndices: 187, .RegUnits: 6848563, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1295 | { .Name: 494, .SubRegs: 1022, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848565, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1296 | { .Name: 557, .SubRegs: 976, .SuperRegs: 66, .SubRegIndices: 187, .RegUnits: 6848567, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1297 | { .Name: 625, .SubRegs: 930, .SuperRegs: 4, .SubRegIndices: 187, .RegUnits: 6848569, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1298 | { .Name: 386, .SubRegs: 884, .SuperRegs: 19, .SubRegIndices: 187, .RegUnits: 6848571, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1299 | { .Name: 581, .SubRegs: 838, .SuperRegs: 19, .SubRegIndices: 187, .RegUnits: 6848547, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1300 | { .Name: 1271, .SubRegs: 95, .SuperRegs: 6267, .SubRegIndices: 65, .RegUnits: 6860836, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1301 | { .Name: 1375, .SubRegs: 95, .SuperRegs: 5917, .SubRegIndices: 65, .RegUnits: 6860837, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1302 | { .Name: 1488, .SubRegs: 95, .SuperRegs: 4835, .SubRegIndices: 65, .RegUnits: 6860838, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1303 | { .Name: 1615, .SubRegs: 95, .SuperRegs: 5038, .SubRegIndices: 65, .RegUnits: 6860839, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1304 | { .Name: 1725, .SubRegs: 95, .SuperRegs: 5125, .SubRegIndices: 65, .RegUnits: 6860840, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1305 | { .Name: 13, .SubRegs: 95, .SuperRegs: 4807, .SubRegIndices: 65, .RegUnits: 6860841, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1306 | { .Name: 150, .SubRegs: 95, .SuperRegs: 5111, .SubRegIndices: 65, .RegUnits: 6860842, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1307 | { .Name: 283, .SubRegs: 95, .SuperRegs: 5097, .SubRegIndices: 65, .RegUnits: 6860843, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1308 | { .Name: 911, .SubRegs: 95, .SuperRegs: 5212, .SubRegIndices: 65, .RegUnits: 6860844, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1309 | { .Name: 1015, .SubRegs: 95, .SuperRegs: 5074, .SubRegIndices: 65, .RegUnits: 6860845, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1310 | { .Name: 1194, .SubRegs: 95, .SuperRegs: 5198, .SubRegIndices: 65, .RegUnits: 6860846, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1311 | { .Name: 1303, .SubRegs: 95, .SuperRegs: 5184, .SubRegIndices: 65, .RegUnits: 6860847, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1312 | { .Name: 1405, .SubRegs: 95, .SuperRegs: 5299, .SubRegIndices: 65, .RegUnits: 6860848, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1313 | { .Name: 1521, .SubRegs: 95, .SuperRegs: 5161, .SubRegIndices: 65, .RegUnits: 6860849, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1314 | { .Name: 1645, .SubRegs: 95, .SuperRegs: 5285, .SubRegIndices: 65, .RegUnits: 6860850, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1315 | { .Name: 45, .SubRegs: 95, .SuperRegs: 5271, .SubRegIndices: 65, .RegUnits: 6860851, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1316 | { .Name: 187, .SubRegs: 95, .SuperRegs: 5386, .SubRegIndices: 65, .RegUnits: 6860852, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1317 | { .Name: 317, .SubRegs: 95, .SuperRegs: 5248, .SubRegIndices: 65, .RegUnits: 6860853, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1318 | { .Name: 950, .SubRegs: 95, .SuperRegs: 5372, .SubRegIndices: 65, .RegUnits: 6860854, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1319 | { .Name: 1051, .SubRegs: 95, .SuperRegs: 5358, .SubRegIndices: 65, .RegUnits: 6860855, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1320 | { .Name: 1234, .SubRegs: 95, .SuperRegs: 5631, .SubRegIndices: 65, .RegUnits: 6860856, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1321 | { .Name: 1339, .SubRegs: 95, .SuperRegs: 5335, .SubRegIndices: 65, .RegUnits: 6860857, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1322 | { .Name: 1445, .SubRegs: 95, .SuperRegs: 5617, .SubRegIndices: 65, .RegUnits: 6860858, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1323 | { .Name: 1557, .SubRegs: 95, .SuperRegs: 5603, .SubRegIndices: 65, .RegUnits: 6860859, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1324 | { .Name: 1685, .SubRegs: 95, .SuperRegs: 6220, .SubRegIndices: 65, .RegUnits: 6860860, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1325 | { .Name: 81, .SubRegs: 95, .SuperRegs: 6356, .SubRegIndices: 65, .RegUnits: 6860861, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1326 | { .Name: 227, .SubRegs: 95, .SuperRegs: 29, .SubRegIndices: 65, .RegUnits: 6860862, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1327 | { .Name: 1162, .SubRegs: 80, .SuperRegs: 29, .SubRegIndices: 65, .RegUnits: 6860835, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 1328 | { .Name: 1372, .SubRegs: 144, .SuperRegs: 6248, .SubRegIndices: 79, .RegUnits: 6856740, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1329 | { .Name: 1485, .SubRegs: 144, .SuperRegs: 5920, .SubRegIndices: 79, .RegUnits: 6856741, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1330 | { .Name: 1612, .SubRegs: 144, .SuperRegs: 4842, .SubRegIndices: 79, .RegUnits: 6856742, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1331 | { .Name: 1722, .SubRegs: 144, .SuperRegs: 6035, .SubRegIndices: 79, .RegUnits: 6856743, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1332 | { .Name: 10, .SubRegs: 144, .SuperRegs: 5645, .SubRegIndices: 79, .RegUnits: 6856744, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1333 | { .Name: 147, .SubRegs: 144, .SuperRegs: 6025, .SubRegIndices: 79, .RegUnits: 6856745, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1334 | { .Name: 280, .SubRegs: 144, .SuperRegs: 5104, .SubRegIndices: 79, .RegUnits: 6856746, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1335 | { .Name: 908, .SubRegs: 144, .SuperRegs: 6055, .SubRegIndices: 79, .RegUnits: 6856747, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1336 | { .Name: 1012, .SubRegs: 144, .SuperRegs: 5653, .SubRegIndices: 79, .RegUnits: 6856748, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1337 | { .Name: 1190, .SubRegs: 144, .SuperRegs: 6045, .SubRegIndices: 79, .RegUnits: 6856749, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1338 | { .Name: 1299, .SubRegs: 144, .SuperRegs: 5191, .SubRegIndices: 79, .RegUnits: 6856750, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1339 | { .Name: 1401, .SubRegs: 144, .SuperRegs: 6075, .SubRegIndices: 79, .RegUnits: 6856751, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1340 | { .Name: 1517, .SubRegs: 144, .SuperRegs: 5661, .SubRegIndices: 79, .RegUnits: 6856752, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1341 | { .Name: 1641, .SubRegs: 144, .SuperRegs: 6065, .SubRegIndices: 79, .RegUnits: 6856753, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1342 | { .Name: 41, .SubRegs: 144, .SuperRegs: 5278, .SubRegIndices: 79, .RegUnits: 6856754, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1343 | { .Name: 183, .SubRegs: 144, .SuperRegs: 6095, .SubRegIndices: 79, .RegUnits: 6856755, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1344 | { .Name: 313, .SubRegs: 144, .SuperRegs: 5669, .SubRegIndices: 79, .RegUnits: 6856756, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1345 | { .Name: 946, .SubRegs: 144, .SuperRegs: 6085, .SubRegIndices: 79, .RegUnits: 6856757, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1346 | { .Name: 1047, .SubRegs: 144, .SuperRegs: 5365, .SubRegIndices: 79, .RegUnits: 6856758, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1347 | { .Name: 1230, .SubRegs: 144, .SuperRegs: 6115, .SubRegIndices: 79, .RegUnits: 6856759, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1348 | { .Name: 1335, .SubRegs: 144, .SuperRegs: 5677, .SubRegIndices: 79, .RegUnits: 6856760, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1349 | { .Name: 1441, .SubRegs: 144, .SuperRegs: 6105, .SubRegIndices: 79, .RegUnits: 6856761, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1350 | { .Name: 1553, .SubRegs: 144, .SuperRegs: 5428, .SubRegIndices: 79, .RegUnits: 6856762, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1351 | { .Name: 1681, .SubRegs: 144, .SuperRegs: 6233, .SubRegIndices: 79, .RegUnits: 6856763, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1352 | { .Name: 77, .SubRegs: 144, .SuperRegs: 6344, .SubRegIndices: 79, .RegUnits: 6856764, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1353 | { .Name: 223, .SubRegs: 144, .SuperRegs: 30, .SubRegIndices: 79, .RegUnits: 6856765, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1354 | { .Name: 1268, .SubRegs: 123, .SuperRegs: 30, .SubRegIndices: 79, .RegUnits: 6856739, .RegUnitLaneMasks: 16, .IsConstant: 0, .IsArtificial: 0 }, |
| 1355 | { .Name: 1482, .SubRegs: 193, .SuperRegs: 6250, .SubRegIndices: 99, .RegUnits: 6852644, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1356 | { .Name: 1609, .SubRegs: 193, .SuperRegs: 5926, .SubRegIndices: 99, .RegUnits: 6852645, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1357 | { .Name: 1719, .SubRegs: 193, .SuperRegs: 6041, .SubRegIndices: 99, .RegUnits: 6852646, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1358 | { .Name: 7, .SubRegs: 193, .SuperRegs: 6294, .SubRegIndices: 99, .RegUnits: 6852647, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1359 | { .Name: 144, .SubRegs: 193, .SuperRegs: 6299, .SubRegIndices: 99, .RegUnits: 6852648, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1360 | { .Name: 277, .SubRegs: 193, .SuperRegs: 6031, .SubRegIndices: 99, .RegUnits: 6852649, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1361 | { .Name: 905, .SubRegs: 193, .SuperRegs: 6061, .SubRegIndices: 99, .RegUnits: 6852650, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1362 | { .Name: 1009, .SubRegs: 193, .SuperRegs: 6304, .SubRegIndices: 99, .RegUnits: 6852651, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1363 | { .Name: 1187, .SubRegs: 193, .SuperRegs: 6309, .SubRegIndices: 99, .RegUnits: 6852652, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1364 | { .Name: 1295, .SubRegs: 193, .SuperRegs: 6051, .SubRegIndices: 99, .RegUnits: 6852653, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1365 | { .Name: 1397, .SubRegs: 193, .SuperRegs: 6081, .SubRegIndices: 99, .RegUnits: 6852654, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1366 | { .Name: 1513, .SubRegs: 193, .SuperRegs: 6314, .SubRegIndices: 99, .RegUnits: 6852655, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1367 | { .Name: 1637, .SubRegs: 193, .SuperRegs: 6319, .SubRegIndices: 99, .RegUnits: 6852656, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1368 | { .Name: 37, .SubRegs: 193, .SuperRegs: 6071, .SubRegIndices: 99, .RegUnits: 6852657, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1369 | { .Name: 179, .SubRegs: 193, .SuperRegs: 6101, .SubRegIndices: 99, .RegUnits: 6852658, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1370 | { .Name: 309, .SubRegs: 193, .SuperRegs: 6324, .SubRegIndices: 99, .RegUnits: 6852659, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1371 | { .Name: 942, .SubRegs: 193, .SuperRegs: 6329, .SubRegIndices: 99, .RegUnits: 6852660, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1372 | { .Name: 1043, .SubRegs: 193, .SuperRegs: 6091, .SubRegIndices: 99, .RegUnits: 6852661, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1373 | { .Name: 1226, .SubRegs: 193, .SuperRegs: 6121, .SubRegIndices: 99, .RegUnits: 6852662, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1374 | { .Name: 1331, .SubRegs: 193, .SuperRegs: 6334, .SubRegIndices: 99, .RegUnits: 6852663, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1375 | { .Name: 1437, .SubRegs: 193, .SuperRegs: 6339, .SubRegIndices: 99, .RegUnits: 6852664, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1376 | { .Name: 1549, .SubRegs: 193, .SuperRegs: 6111, .SubRegIndices: 99, .RegUnits: 6852665, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1377 | { .Name: 1677, .SubRegs: 193, .SuperRegs: 6139, .SubRegIndices: 99, .RegUnits: 6852666, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1378 | { .Name: 73, .SubRegs: 193, .SuperRegs: 6351, .SubRegIndices: 99, .RegUnits: 6852667, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1379 | { .Name: 219, .SubRegs: 193, .SuperRegs: 17, .SubRegIndices: 99, .RegUnits: 6852668, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1380 | { .Name: 1369, .SubRegs: 165, .SuperRegs: 17, .SubRegIndices: 99, .RegUnits: 6852643, .RegUnitLaneMasks: 22, .IsConstant: 0, .IsArtificial: 0 }, |
| 1381 | { .Name: 1606, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848548, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1382 | { .Name: 1716, .SubRegs: 257, .SuperRegs: 15, .SubRegIndices: 126, .RegUnits: 6848549, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1383 | { .Name: 4, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848550, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1384 | { .Name: 141, .SubRegs: 257, .SuperRegs: 77, .SubRegIndices: 126, .RegUnits: 6848551, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1385 | { .Name: 274, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848552, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1386 | { .Name: 902, .SubRegs: 257, .SuperRegs: 13, .SubRegIndices: 126, .RegUnits: 6848553, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1387 | { .Name: 1006, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848554, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1388 | { .Name: 1184, .SubRegs: 257, .SuperRegs: 74, .SubRegIndices: 126, .RegUnits: 6848555, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1389 | { .Name: 1292, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848556, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1390 | { .Name: 1393, .SubRegs: 257, .SuperRegs: 11, .SubRegIndices: 126, .RegUnits: 6848557, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1391 | { .Name: 1509, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848558, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1392 | { .Name: 1633, .SubRegs: 257, .SuperRegs: 71, .SubRegIndices: 126, .RegUnits: 6848559, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1393 | { .Name: 33, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848560, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1394 | { .Name: 175, .SubRegs: 257, .SuperRegs: 9, .SubRegIndices: 126, .RegUnits: 6848561, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1395 | { .Name: 305, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848562, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1396 | { .Name: 938, .SubRegs: 257, .SuperRegs: 68, .SubRegIndices: 126, .RegUnits: 6848563, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1397 | { .Name: 1039, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848564, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1398 | { .Name: 1222, .SubRegs: 257, .SuperRegs: 7, .SubRegIndices: 126, .RegUnits: 6848565, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1399 | { .Name: 1327, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848566, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1400 | { .Name: 1433, .SubRegs: 257, .SuperRegs: 65, .SubRegIndices: 126, .RegUnits: 6848567, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1401 | { .Name: 1545, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848568, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1402 | { .Name: 1673, .SubRegs: 257, .SuperRegs: 5, .SubRegIndices: 126, .RegUnits: 6848569, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1403 | { .Name: 69, .SubRegs: 257, .SuperRegs: 4, .SubRegIndices: 126, .RegUnits: 6848570, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1404 | { .Name: 215, .SubRegs: 257, .SuperRegs: 18, .SubRegIndices: 126, .RegUnits: 6848571, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1405 | { .Name: 1479, .SubRegs: 221, .SuperRegs: 18, .SubRegIndices: 126, .RegUnits: 6848547, .RegUnitLaneMasks: 29, .IsConstant: 0, .IsArtificial: 0 }, |
| 1406 | }; |
| 1407 | |
| 1408 | extern const MCPhysReg RISCVRegUnitRoots[][2] = { |
| 1409 | { RISCV::FCSR }, |
| 1410 | { RISCV::FFLAGS }, |
| 1411 | { RISCV::FRM }, |
| 1412 | { RISCV::SF_VCIX_STATE }, |
| 1413 | { RISCV::SSP }, |
| 1414 | { RISCV::VL }, |
| 1415 | { RISCV::VLENB }, |
| 1416 | { RISCV::VTYPE }, |
| 1417 | { RISCV::VXRM }, |
| 1418 | { RISCV::VXSAT }, |
| 1419 | { RISCV::DUMMY_REG_PAIR_WITH_X0 }, |
| 1420 | { RISCV::M0 }, |
| 1421 | { RISCV::M1 }, |
| 1422 | { RISCV::M2 }, |
| 1423 | { RISCV::M3 }, |
| 1424 | { RISCV::M4 }, |
| 1425 | { RISCV::M5 }, |
| 1426 | { RISCV::M6 }, |
| 1427 | { RISCV::M7 }, |
| 1428 | { RISCV::T0 }, |
| 1429 | { RISCV::T1 }, |
| 1430 | { RISCV::T2 }, |
| 1431 | { RISCV::T3 }, |
| 1432 | { RISCV::T4 }, |
| 1433 | { RISCV::T5 }, |
| 1434 | { RISCV::T6 }, |
| 1435 | { RISCV::T7 }, |
| 1436 | { RISCV::T8 }, |
| 1437 | { RISCV::T9 }, |
| 1438 | { RISCV::T10 }, |
| 1439 | { RISCV::T11 }, |
| 1440 | { RISCV::T12 }, |
| 1441 | { RISCV::T13 }, |
| 1442 | { RISCV::T14 }, |
| 1443 | { RISCV::T15 }, |
| 1444 | { RISCV::V0 }, |
| 1445 | { RISCV::V1 }, |
| 1446 | { RISCV::V2 }, |
| 1447 | { RISCV::V3 }, |
| 1448 | { RISCV::V4 }, |
| 1449 | { RISCV::V5 }, |
| 1450 | { RISCV::V6 }, |
| 1451 | { RISCV::V7 }, |
| 1452 | { RISCV::V8 }, |
| 1453 | { RISCV::V9 }, |
| 1454 | { RISCV::V10 }, |
| 1455 | { RISCV::V11 }, |
| 1456 | { RISCV::V12 }, |
| 1457 | { RISCV::V13 }, |
| 1458 | { RISCV::V14 }, |
| 1459 | { RISCV::V15 }, |
| 1460 | { RISCV::V16 }, |
| 1461 | { RISCV::V17 }, |
| 1462 | { RISCV::V18 }, |
| 1463 | { RISCV::V19 }, |
| 1464 | { RISCV::V20 }, |
| 1465 | { RISCV::V21 }, |
| 1466 | { RISCV::V22 }, |
| 1467 | { RISCV::V23 }, |
| 1468 | { RISCV::V24 }, |
| 1469 | { RISCV::V25 }, |
| 1470 | { RISCV::V26 }, |
| 1471 | { RISCV::V27 }, |
| 1472 | { RISCV::V28 }, |
| 1473 | { RISCV::V29 }, |
| 1474 | { RISCV::V30 }, |
| 1475 | { RISCV::V31 }, |
| 1476 | { RISCV::X0_H }, |
| 1477 | { RISCV::X1_H }, |
| 1478 | { RISCV::X2_H }, |
| 1479 | { RISCV::X3_H }, |
| 1480 | { RISCV::X4_H }, |
| 1481 | { RISCV::X5_H }, |
| 1482 | { RISCV::X6_H }, |
| 1483 | { RISCV::X7_H }, |
| 1484 | { RISCV::X8_H }, |
| 1485 | { RISCV::X9_H }, |
| 1486 | { RISCV::X10_H }, |
| 1487 | { RISCV::X11_H }, |
| 1488 | { RISCV::X12_H }, |
| 1489 | { RISCV::X13_H }, |
| 1490 | { RISCV::X14_H }, |
| 1491 | { RISCV::X15_H }, |
| 1492 | { RISCV::X16_H }, |
| 1493 | { RISCV::X17_H }, |
| 1494 | { RISCV::X18_H }, |
| 1495 | { RISCV::X19_H }, |
| 1496 | { RISCV::X20_H }, |
| 1497 | { RISCV::X21_H }, |
| 1498 | { RISCV::X22_H }, |
| 1499 | { RISCV::X23_H }, |
| 1500 | { RISCV::X24_H }, |
| 1501 | { RISCV::X25_H }, |
| 1502 | { RISCV::X26_H }, |
| 1503 | { RISCV::X27_H }, |
| 1504 | { RISCV::X28_H }, |
| 1505 | { RISCV::X29_H }, |
| 1506 | { RISCV::X30_H }, |
| 1507 | { RISCV::X31_H }, |
| 1508 | { RISCV::F0_H }, |
| 1509 | { RISCV::F1_H }, |
| 1510 | { RISCV::F2_H }, |
| 1511 | { RISCV::F3_H }, |
| 1512 | { RISCV::F4_H }, |
| 1513 | { RISCV::F5_H }, |
| 1514 | { RISCV::F6_H }, |
| 1515 | { RISCV::F7_H }, |
| 1516 | { RISCV::F8_H }, |
| 1517 | { RISCV::F9_H }, |
| 1518 | { RISCV::F10_H }, |
| 1519 | { RISCV::F11_H }, |
| 1520 | { RISCV::F12_H }, |
| 1521 | { RISCV::F13_H }, |
| 1522 | { RISCV::F14_H }, |
| 1523 | { RISCV::F15_H }, |
| 1524 | { RISCV::F16_H }, |
| 1525 | { RISCV::F17_H }, |
| 1526 | { RISCV::F18_H }, |
| 1527 | { RISCV::F19_H }, |
| 1528 | { RISCV::F20_H }, |
| 1529 | { RISCV::F21_H }, |
| 1530 | { RISCV::F22_H }, |
| 1531 | { RISCV::F23_H }, |
| 1532 | { RISCV::F24_H }, |
| 1533 | { RISCV::F25_H }, |
| 1534 | { RISCV::F26_H }, |
| 1535 | { RISCV::F27_H }, |
| 1536 | { RISCV::F28_H }, |
| 1537 | { RISCV::F29_H }, |
| 1538 | { RISCV::F30_H }, |
| 1539 | { RISCV::F31_H }, |
| 1540 | }; |
| 1541 | |
| 1542 | namespace { // Register classes... |
| 1543 | // MR Register Class... |
| 1544 | const MCPhysReg MR[] = { |
| 1545 | RISCV::M1, RISCV::M2, RISCV::M3, RISCV::M4, RISCV::M5, RISCV::M6, RISCV::M7, RISCV::M0, |
| 1546 | }; |
| 1547 | |
| 1548 | // MR Bit set. |
| 1549 | const uint8_t MRBits[] = { |
| 1550 | 0x00, 0xf0, 0x0f, |
| 1551 | }; |
| 1552 | |
| 1553 | // MR0 Register Class... |
| 1554 | const MCPhysReg MR0[] = { |
| 1555 | RISCV::M0, |
| 1556 | }; |
| 1557 | |
| 1558 | // MR0 Bit set. |
| 1559 | const uint8_t MR0Bits[] = { |
| 1560 | 0x00, 0x10, |
| 1561 | }; |
| 1562 | |
| 1563 | // FPR16 Register Class... |
| 1564 | const MCPhysReg FPR16[] = { |
| 1565 | RISCV::F15_H, RISCV::F14_H, RISCV::F13_H, RISCV::F12_H, RISCV::F11_H, RISCV::F10_H, RISCV::F0_H, RISCV::F1_H, RISCV::F2_H, RISCV::F3_H, RISCV::F4_H, RISCV::F5_H, RISCV::F6_H, RISCV::F7_H, RISCV::F16_H, RISCV::F17_H, RISCV::F28_H, RISCV::F29_H, RISCV::F30_H, RISCV::F31_H, RISCV::F8_H, RISCV::F9_H, RISCV::F18_H, RISCV::F19_H, RISCV::F20_H, RISCV::F21_H, RISCV::F22_H, RISCV::F23_H, RISCV::F24_H, RISCV::F25_H, RISCV::F26_H, RISCV::F27_H, |
| 1566 | }; |
| 1567 | |
| 1568 | // FPR16 Bit set. |
| 1569 | const uint8_t FPR16Bits[] = { |
| 1570 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 1571 | }; |
| 1572 | |
| 1573 | // GPRF16 Register Class... |
| 1574 | const MCPhysReg GPRF16[] = { |
| 1575 | RISCV::X10_H, RISCV::X11_H, RISCV::X12_H, RISCV::X13_H, RISCV::X14_H, RISCV::X15_H, RISCV::X16_H, RISCV::X17_H, RISCV::X5_H, RISCV::X6_H, RISCV::X7_H, RISCV::X28_H, RISCV::X29_H, RISCV::X30_H, RISCV::X31_H, RISCV::X8_H, RISCV::X9_H, RISCV::X18_H, RISCV::X19_H, RISCV::X20_H, RISCV::X21_H, RISCV::X22_H, RISCV::X23_H, RISCV::X24_H, RISCV::X25_H, RISCV::X26_H, RISCV::X27_H, RISCV::X0_H, RISCV::X1_H, RISCV::X2_H, RISCV::X3_H, RISCV::X4_H, |
| 1576 | }; |
| 1577 | |
| 1578 | // GPRF16 Bit set. |
| 1579 | const uint8_t GPRF16Bits[] = { |
| 1580 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 1581 | }; |
| 1582 | |
| 1583 | // GPRF16NoX0 Register Class... |
| 1584 | const MCPhysReg GPRF16NoX0[] = { |
| 1585 | RISCV::X10_H, RISCV::X11_H, RISCV::X12_H, RISCV::X13_H, RISCV::X14_H, RISCV::X15_H, RISCV::X16_H, RISCV::X17_H, RISCV::X5_H, RISCV::X6_H, RISCV::X7_H, RISCV::X28_H, RISCV::X29_H, RISCV::X30_H, RISCV::X31_H, RISCV::X8_H, RISCV::X9_H, RISCV::X18_H, RISCV::X19_H, RISCV::X20_H, RISCV::X21_H, RISCV::X22_H, RISCV::X23_H, RISCV::X24_H, RISCV::X25_H, RISCV::X26_H, RISCV::X27_H, RISCV::X1_H, RISCV::X2_H, RISCV::X3_H, RISCV::X4_H, |
| 1586 | }; |
| 1587 | |
| 1588 | // GPRF16NoX0 Bit set. |
| 1589 | const uint8_t GPRF16NoX0Bits[] = { |
| 1590 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, |
| 1591 | }; |
| 1592 | |
| 1593 | // FPR16C Register Class... |
| 1594 | const MCPhysReg FPR16C[] = { |
| 1595 | RISCV::F15_H, RISCV::F14_H, RISCV::F13_H, RISCV::F12_H, RISCV::F11_H, RISCV::F10_H, RISCV::F8_H, RISCV::F9_H, |
| 1596 | }; |
| 1597 | |
| 1598 | // FPR16C Bit set. |
| 1599 | const uint8_t FPR16CBits[] = { |
| 1600 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| 1601 | }; |
| 1602 | |
| 1603 | // GPRF16C Register Class... |
| 1604 | const MCPhysReg GPRF16C[] = { |
| 1605 | RISCV::X10_H, RISCV::X11_H, RISCV::X12_H, RISCV::X13_H, RISCV::X14_H, RISCV::X15_H, RISCV::X8_H, RISCV::X9_H, |
| 1606 | }; |
| 1607 | |
| 1608 | // GPRF16C Bit set. |
| 1609 | const uint8_t GPRF16CBits[] = { |
| 1610 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| 1611 | }; |
| 1612 | |
| 1613 | // GPRAll Register Class... |
| 1614 | const MCPhysReg GPRAll[] = { |
| 1615 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, RISCV::DUMMY_REG_PAIR_WITH_X0, |
| 1616 | }; |
| 1617 | |
| 1618 | // GPRAll Bit set. |
| 1619 | const uint8_t GPRAllBits[] = { |
| 1620 | 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 1621 | }; |
| 1622 | |
| 1623 | // FPR32 Register Class... |
| 1624 | const MCPhysReg FPR32[] = { |
| 1625 | RISCV::F15_F, RISCV::F14_F, RISCV::F13_F, RISCV::F12_F, RISCV::F11_F, RISCV::F10_F, RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F16_F, RISCV::F17_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, |
| 1626 | }; |
| 1627 | |
| 1628 | // FPR32 Bit set. |
| 1629 | const uint8_t FPR32Bits[] = { |
| 1630 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 1631 | }; |
| 1632 | |
| 1633 | // GPR Register Class... |
| 1634 | const MCPhysReg GPR[] = { |
| 1635 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, |
| 1636 | }; |
| 1637 | |
| 1638 | // GPR Bit set. |
| 1639 | const uint8_t GPRBits[] = { |
| 1640 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 1641 | }; |
| 1642 | |
| 1643 | // GPRF32 Register Class... |
| 1644 | const MCPhysReg GPRF32[] = { |
| 1645 | RISCV::X10_W, RISCV::X11_W, RISCV::X12_W, RISCV::X13_W, RISCV::X14_W, RISCV::X15_W, RISCV::X16_W, RISCV::X17_W, RISCV::X5_W, RISCV::X6_W, RISCV::X7_W, RISCV::X28_W, RISCV::X29_W, RISCV::X30_W, RISCV::X31_W, RISCV::X8_W, RISCV::X9_W, RISCV::X18_W, RISCV::X19_W, RISCV::X20_W, RISCV::X21_W, RISCV::X22_W, RISCV::X23_W, RISCV::X24_W, RISCV::X25_W, RISCV::X26_W, RISCV::X27_W, RISCV::X0_W, RISCV::X1_W, RISCV::X2_W, RISCV::X3_W, RISCV::X4_W, |
| 1646 | }; |
| 1647 | |
| 1648 | // GPRF32 Bit set. |
| 1649 | const uint8_t GPRF32Bits[] = { |
| 1650 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, |
| 1651 | }; |
| 1652 | |
| 1653 | // GPRF32NoX0 Register Class... |
| 1654 | const MCPhysReg GPRF32NoX0[] = { |
| 1655 | RISCV::X10_W, RISCV::X11_W, RISCV::X12_W, RISCV::X13_W, RISCV::X14_W, RISCV::X15_W, RISCV::X16_W, RISCV::X17_W, RISCV::X5_W, RISCV::X6_W, RISCV::X7_W, RISCV::X28_W, RISCV::X29_W, RISCV::X30_W, RISCV::X31_W, RISCV::X8_W, RISCV::X9_W, RISCV::X18_W, RISCV::X19_W, RISCV::X20_W, RISCV::X21_W, RISCV::X22_W, RISCV::X23_W, RISCV::X24_W, RISCV::X25_W, RISCV::X26_W, RISCV::X27_W, RISCV::X1_W, RISCV::X2_W, RISCV::X3_W, RISCV::X4_W, |
| 1656 | }; |
| 1657 | |
| 1658 | // GPRF32NoX0 Bit set. |
| 1659 | const uint8_t GPRF32NoX0Bits[] = { |
| 1660 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, |
| 1661 | }; |
| 1662 | |
| 1663 | // GPRNoX0 Register Class... |
| 1664 | const MCPhysReg GPRNoX0[] = { |
| 1665 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, |
| 1666 | }; |
| 1667 | |
| 1668 | // GPRNoX0 Bit set. |
| 1669 | const uint8_t GPRNoX0Bits[] = { |
| 1670 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, |
| 1671 | }; |
| 1672 | |
| 1673 | // GPRNoX2 Register Class... |
| 1674 | const MCPhysReg GPRNoX2[] = { |
| 1675 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X3, RISCV::X4, |
| 1676 | }; |
| 1677 | |
| 1678 | // GPRNoX2 Bit set. |
| 1679 | const uint8_t GPRNoX2Bits[] = { |
| 1680 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0xff, 0xff, 0xff, 0x0f, |
| 1681 | }; |
| 1682 | |
| 1683 | // GPRNoX31 Register Class... |
| 1684 | const MCPhysReg GPRNoX31[] = { |
| 1685 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, |
| 1686 | }; |
| 1687 | |
| 1688 | // GPRNoX31 Bit set. |
| 1689 | const uint8_t GPRNoX31Bits[] = { |
| 1690 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07, |
| 1691 | }; |
| 1692 | |
| 1693 | // GPRNoX0X2 Register Class... |
| 1694 | const MCPhysReg GPRNoX0X2[] = { |
| 1695 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X3, RISCV::X4, |
| 1696 | }; |
| 1697 | |
| 1698 | // GPRNoX0X2 Bit set. |
| 1699 | const uint8_t GPRNoX0X2Bits[] = { |
| 1700 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x0f, |
| 1701 | }; |
| 1702 | |
| 1703 | // GPRNoX0_and_GPRNoX31 Register Class... |
| 1704 | const MCPhysReg GPRNoX0_and_GPRNoX31[] = { |
| 1705 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, |
| 1706 | }; |
| 1707 | |
| 1708 | // GPRNoX0_and_GPRNoX31 Bit set. |
| 1709 | const uint8_t GPRNoX0_and_GPRNoX31Bits[] = { |
| 1710 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x07, |
| 1711 | }; |
| 1712 | |
| 1713 | // GPRNoX2_and_GPRNoX31 Register Class... |
| 1714 | const MCPhysReg GPRNoX2_and_GPRNoX31[] = { |
| 1715 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X3, RISCV::X4, |
| 1716 | }; |
| 1717 | |
| 1718 | // GPRNoX2_and_GPRNoX31 Bit set. |
| 1719 | const uint8_t GPRNoX2_and_GPRNoX31Bits[] = { |
| 1720 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0xff, 0xff, 0xff, 0x07, |
| 1721 | }; |
| 1722 | |
| 1723 | // GPRNoX0X2_and_GPRNoX31 Register Class... |
| 1724 | const MCPhysReg GPRNoX0X2_and_GPRNoX31[] = { |
| 1725 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X3, RISCV::X4, |
| 1726 | }; |
| 1727 | |
| 1728 | // GPRNoX0X2_and_GPRNoX31 Bit set. |
| 1729 | const uint8_t GPRNoX0X2_and_GPRNoX31Bits[] = { |
| 1730 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x07, |
| 1731 | }; |
| 1732 | |
| 1733 | // GPRJALR Register Class... |
| 1734 | const MCPhysReg GPRJALR[] = { |
| 1735 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, |
| 1736 | }; |
| 1737 | |
| 1738 | // GPRJALR Bit set. |
| 1739 | const uint8_t GPRJALRBits[] = { |
| 1740 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x0f, |
| 1741 | }; |
| 1742 | |
| 1743 | // GPRJALRNonX7 Register Class... |
| 1744 | const MCPhysReg GPRJALRNonX7[] = { |
| 1745 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, |
| 1746 | }; |
| 1747 | |
| 1748 | // GPRJALRNonX7 Bit set. |
| 1749 | const uint8_t GPRJALRNonX7Bits[] = { |
| 1750 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf4, 0xff, 0xff, 0x0f, |
| 1751 | }; |
| 1752 | |
| 1753 | // GPRJALR_and_GPRNoX31 Register Class... |
| 1754 | const MCPhysReg GPRJALR_and_GPRNoX31[] = { |
| 1755 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, |
| 1756 | }; |
| 1757 | |
| 1758 | // GPRJALR_and_GPRNoX31 Bit set. |
| 1759 | const uint8_t GPRJALR_and_GPRNoX31Bits[] = { |
| 1760 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x07, |
| 1761 | }; |
| 1762 | |
| 1763 | // GPRJALRNonX7_and_GPRNoX31 Register Class... |
| 1764 | const MCPhysReg GPRJALRNonX7_and_GPRNoX31[] = { |
| 1765 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, |
| 1766 | }; |
| 1767 | |
| 1768 | // GPRJALRNonX7_and_GPRNoX31 Bit set. |
| 1769 | const uint8_t GPRJALRNonX7_and_GPRNoX31Bits[] = { |
| 1770 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf4, 0xff, 0xff, 0x07, |
| 1771 | }; |
| 1772 | |
| 1773 | // TR Register Class... |
| 1774 | const MCPhysReg TR[] = { |
| 1775 | RISCV::T0, RISCV::T1, RISCV::T2, RISCV::T3, RISCV::T4, RISCV::T5, RISCV::T6, RISCV::T7, RISCV::T8, RISCV::T9, RISCV::T10, RISCV::T11, RISCV::T12, RISCV::T13, RISCV::T14, RISCV::T15, |
| 1776 | }; |
| 1777 | |
| 1778 | // TR Bit set. |
| 1779 | const uint8_t TRBits[] = { |
| 1780 | 0x00, 0x00, 0xf0, 0xff, 0x0f, |
| 1781 | }; |
| 1782 | |
| 1783 | // GPRTC Register Class... |
| 1784 | const MCPhysReg GPRTC[] = { |
| 1785 | RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, |
| 1786 | }; |
| 1787 | |
| 1788 | // GPRTC Bit set. |
| 1789 | const uint8_t GPRTCBits[] = { |
| 1790 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x3f, 0x00, 0x0f, |
| 1791 | }; |
| 1792 | |
| 1793 | // GPRNoX31_and_GPRTC Register Class... |
| 1794 | const MCPhysReg GPRNoX31_and_GPRTC[] = { |
| 1795 | RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, |
| 1796 | }; |
| 1797 | |
| 1798 | // GPRNoX31_and_GPRTC Bit set. |
| 1799 | const uint8_t GPRNoX31_and_GPRTCBits[] = { |
| 1800 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x3f, 0x00, 0x07, |
| 1801 | }; |
| 1802 | |
| 1803 | // GPRTCNonX7 Register Class... |
| 1804 | const MCPhysReg GPRTCNonX7[] = { |
| 1805 | RISCV::X6, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, |
| 1806 | }; |
| 1807 | |
| 1808 | // GPRTCNonX7 Bit set. |
| 1809 | const uint8_t GPRTCNonX7Bits[] = { |
| 1810 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x3f, 0x00, 0x0f, |
| 1811 | }; |
| 1812 | |
| 1813 | // GPRNoX31_and_GPRTCNonX7 Register Class... |
| 1814 | const MCPhysReg GPRNoX31_and_GPRTCNonX7[] = { |
| 1815 | RISCV::X6, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, |
| 1816 | }; |
| 1817 | |
| 1818 | // GPRNoX31_and_GPRTCNonX7 Bit set. |
| 1819 | const uint8_t GPRNoX31_and_GPRTCNonX7Bits[] = { |
| 1820 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x3f, 0x00, 0x07, |
| 1821 | }; |
| 1822 | |
| 1823 | // FPR32C Register Class... |
| 1824 | const MCPhysReg FPR32C[] = { |
| 1825 | RISCV::F15_F, RISCV::F14_F, RISCV::F13_F, RISCV::F12_F, RISCV::F11_F, RISCV::F10_F, RISCV::F8_F, RISCV::F9_F, |
| 1826 | }; |
| 1827 | |
| 1828 | // FPR32C Bit set. |
| 1829 | const uint8_t FPR32CBits[] = { |
| 1830 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| 1831 | }; |
| 1832 | |
| 1833 | // GPRC Register Class... |
| 1834 | const MCPhysReg GPRC[] = { |
| 1835 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X8, RISCV::X9, |
| 1836 | }; |
| 1837 | |
| 1838 | // GPRC Bit set. |
| 1839 | const uint8_t GPRCBits[] = { |
| 1840 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| 1841 | }; |
| 1842 | |
| 1843 | // GPRF32C Register Class... |
| 1844 | const MCPhysReg GPRF32C[] = { |
| 1845 | RISCV::X10_W, RISCV::X11_W, RISCV::X12_W, RISCV::X13_W, RISCV::X14_W, RISCV::X15_W, RISCV::X8_W, RISCV::X9_W, |
| 1846 | }; |
| 1847 | |
| 1848 | // GPRF32C Bit set. |
| 1849 | const uint8_t GPRF32CBits[] = { |
| 1850 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, |
| 1851 | }; |
| 1852 | |
| 1853 | // SR07 Register Class... |
| 1854 | const MCPhysReg SR07[] = { |
| 1855 | RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, |
| 1856 | }; |
| 1857 | |
| 1858 | // SR07 Bit set. |
| 1859 | const uint8_t SR07Bits[] = { |
| 1860 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xc0, 0x0f, |
| 1861 | }; |
| 1862 | |
| 1863 | // TRM2 Register Class... |
| 1864 | const MCPhysReg TRM2[] = { |
| 1865 | RISCV::T0, RISCV::T2, RISCV::T4, RISCV::T6, RISCV::T8, RISCV::T10, RISCV::T12, RISCV::T14, |
| 1866 | }; |
| 1867 | |
| 1868 | // TRM2 Bit set. |
| 1869 | const uint8_t TRM2Bits[] = { |
| 1870 | 0x00, 0x00, 0x50, 0x55, 0x05, |
| 1871 | }; |
| 1872 | |
| 1873 | // GPRC_and_GPRTC Register Class... |
| 1874 | const MCPhysReg GPRC_and_GPRTC[] = { |
| 1875 | RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, |
| 1876 | }; |
| 1877 | |
| 1878 | // GPRC_and_GPRTC Bit set. |
| 1879 | const uint8_t GPRC_and_GPRTCBits[] = { |
| 1880 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, |
| 1881 | }; |
| 1882 | |
| 1883 | // TRM4 Register Class... |
| 1884 | const MCPhysReg TRM4[] = { |
| 1885 | RISCV::T0, RISCV::T4, RISCV::T8, RISCV::T12, |
| 1886 | }; |
| 1887 | |
| 1888 | // TRM4 Bit set. |
| 1889 | const uint8_t TRM4Bits[] = { |
| 1890 | 0x00, 0x00, 0x10, 0x11, 0x01, |
| 1891 | }; |
| 1892 | |
| 1893 | // VCSR Register Class... |
| 1894 | const MCPhysReg VCSR[] = { |
| 1895 | RISCV::VTYPE, RISCV::VL, RISCV::VLENB, |
| 1896 | }; |
| 1897 | |
| 1898 | // VCSR Bit set. |
| 1899 | const uint8_t VCSRBits[] = { |
| 1900 | 0xc0, 0x01, |
| 1901 | }; |
| 1902 | |
| 1903 | // GPRC_and_SR07 Register Class... |
| 1904 | const MCPhysReg GPRC_and_SR07[] = { |
| 1905 | RISCV::X8, RISCV::X9, |
| 1906 | }; |
| 1907 | |
| 1908 | // GPRC_and_SR07 Bit set. |
| 1909 | const uint8_t GPRC_and_SR07Bits[] = { |
| 1910 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, |
| 1911 | }; |
| 1912 | |
| 1913 | // GPRX1X5 Register Class... |
| 1914 | const MCPhysReg GPRX1X5[] = { |
| 1915 | RISCV::X1, RISCV::X5, |
| 1916 | }; |
| 1917 | |
| 1918 | // GPRX1X5 Bit set. |
| 1919 | const uint8_t GPRX1X5Bits[] = { |
| 1920 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x02, |
| 1921 | }; |
| 1922 | |
| 1923 | // GPRX0 Register Class... |
| 1924 | const MCPhysReg GPRX0[] = { |
| 1925 | RISCV::X0, |
| 1926 | }; |
| 1927 | |
| 1928 | // GPRX0 Bit set. |
| 1929 | const uint8_t GPRX0Bits[] = { |
| 1930 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 1931 | }; |
| 1932 | |
| 1933 | // GPRX1 Register Class... |
| 1934 | const MCPhysReg GPRX1[] = { |
| 1935 | RISCV::X1, |
| 1936 | }; |
| 1937 | |
| 1938 | // GPRX1 Bit set. |
| 1939 | const uint8_t GPRX1Bits[] = { |
| 1940 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| 1941 | }; |
| 1942 | |
| 1943 | // GPRX5 Register Class... |
| 1944 | const MCPhysReg GPRX5[] = { |
| 1945 | RISCV::X5, |
| 1946 | }; |
| 1947 | |
| 1948 | // GPRX5 Bit set. |
| 1949 | const uint8_t GPRX5Bits[] = { |
| 1950 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, |
| 1951 | }; |
| 1952 | |
| 1953 | // GPRX7 Register Class... |
| 1954 | const MCPhysReg GPRX7[] = { |
| 1955 | RISCV::X7, |
| 1956 | }; |
| 1957 | |
| 1958 | // GPRX7 Bit set. |
| 1959 | const uint8_t GPRX7Bits[] = { |
| 1960 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, |
| 1961 | }; |
| 1962 | |
| 1963 | // SP Register Class... |
| 1964 | const MCPhysReg SP[] = { |
| 1965 | RISCV::X2, |
| 1966 | }; |
| 1967 | |
| 1968 | // SP Bit set. |
| 1969 | const uint8_t SPBits[] = { |
| 1970 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| 1971 | }; |
| 1972 | |
| 1973 | // anonymous_15375 Register Class... |
| 1974 | const MCPhysReg anonymous_15375[] = { |
| 1975 | RISCV::SF_VCIX_STATE, |
| 1976 | }; |
| 1977 | |
| 1978 | // anonymous_15375 Bit set. |
| 1979 | const uint8_t anonymous_15375Bits[] = { |
| 1980 | 0x10, |
| 1981 | }; |
| 1982 | |
| 1983 | // GPRPair Register Class... |
| 1984 | const MCPhysReg GPRPair[] = { |
| 1985 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X0_Pair, RISCV::X2_X3, RISCV::X4_X5, |
| 1986 | }; |
| 1987 | |
| 1988 | // GPRPair Bit set. |
| 1989 | const uint8_t GPRPairBits[] = { |
| 1990 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, |
| 1991 | }; |
| 1992 | |
| 1993 | // GPRPairNoX0 Register Class... |
| 1994 | const MCPhysReg GPRPairNoX0[] = { |
| 1995 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X2_X3, RISCV::X4_X5, |
| 1996 | }; |
| 1997 | |
| 1998 | // GPRPairNoX0 Bit set. |
| 1999 | const uint8_t GPRPairNoX0Bits[] = { |
| 2000 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, |
| 2001 | }; |
| 2002 | |
| 2003 | // GPRPair_with_sub_gpr_even_in_GPRNoX2 Register Class... |
| 2004 | const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRNoX2[] = { |
| 2005 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X0_Pair, RISCV::X4_X5, |
| 2006 | }; |
| 2007 | |
| 2008 | // GPRPair_with_sub_gpr_even_in_GPRNoX2 Bit set. |
| 2009 | const uint8_t GPRPair_with_sub_gpr_even_in_GPRNoX2Bits[] = { |
| 2010 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, |
| 2011 | }; |
| 2012 | |
| 2013 | // GPRPair_with_sub_gpr_even_in_GPRNoX0X2 Register Class... |
| 2014 | const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRNoX0X2[] = { |
| 2015 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X4_X5, |
| 2016 | }; |
| 2017 | |
| 2018 | // GPRPair_with_sub_gpr_even_in_GPRNoX0X2 Bit set. |
| 2019 | const uint8_t GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits[] = { |
| 2020 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, |
| 2021 | }; |
| 2022 | |
| 2023 | // GPRPair_with_sub_gpr_odd_in_GPRNoX31 Register Class... |
| 2024 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRNoX31[] = { |
| 2025 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X2_X3, RISCV::X4_X5, |
| 2026 | }; |
| 2027 | |
| 2028 | // GPRPair_with_sub_gpr_odd_in_GPRNoX31 Bit set. |
| 2029 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRNoX31Bits[] = { |
| 2030 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, |
| 2031 | }; |
| 2032 | |
| 2033 | // GPRPair_with_sub_gpr_even_in_GPRJALR Register Class... |
| 2034 | const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRJALR[] = { |
| 2035 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, |
| 2036 | }; |
| 2037 | |
| 2038 | // GPRPair_with_sub_gpr_even_in_GPRJALR Bit set. |
| 2039 | const uint8_t GPRPair_with_sub_gpr_even_in_GPRJALRBits[] = { |
| 2040 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, |
| 2041 | }; |
| 2042 | |
| 2043 | // GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31 Register Class... |
| 2044 | const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31[] = { |
| 2045 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X4_X5, |
| 2046 | }; |
| 2047 | |
| 2048 | // GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31 Bit set. |
| 2049 | const uint8_t GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31Bits[] = { |
| 2050 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, |
| 2051 | }; |
| 2052 | |
| 2053 | // GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7 Register Class... |
| 2054 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7[] = { |
| 2055 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, |
| 2056 | }; |
| 2057 | |
| 2058 | // GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7 Bit set. |
| 2059 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7Bits[] = { |
| 2060 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, |
| 2061 | }; |
| 2062 | |
| 2063 | // GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31 Register Class... |
| 2064 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31[] = { |
| 2065 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, |
| 2066 | }; |
| 2067 | |
| 2068 | // GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31 Bit set. |
| 2069 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31Bits[] = { |
| 2070 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x7f, |
| 2071 | }; |
| 2072 | |
| 2073 | // GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31 Register Class... |
| 2074 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31[] = { |
| 2075 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X28_X29, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, |
| 2076 | }; |
| 2077 | |
| 2078 | // GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31 Bit set. |
| 2079 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31Bits[] = { |
| 2080 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x7f, |
| 2081 | }; |
| 2082 | |
| 2083 | // GPRPair_with_sub_gpr_even_in_GPRTC Register Class... |
| 2084 | const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRTC[] = { |
| 2085 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, |
| 2086 | }; |
| 2087 | |
| 2088 | // GPRPair_with_sub_gpr_even_in_GPRTC Bit set. |
| 2089 | const uint8_t GPRPair_with_sub_gpr_even_in_GPRTCBits[] = { |
| 2090 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0xc1, |
| 2091 | }; |
| 2092 | |
| 2093 | // GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTC Register Class... |
| 2094 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTC[] = { |
| 2095 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, |
| 2096 | }; |
| 2097 | |
| 2098 | // GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTC Bit set. |
| 2099 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCBits[] = { |
| 2100 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0x41, |
| 2101 | }; |
| 2102 | |
| 2103 | // GPRPair_with_sub_gpr_odd_in_GPRTCNonX7 Register Class... |
| 2104 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRTCNonX7[] = { |
| 2105 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X28_X29, RISCV::X30_X31, |
| 2106 | }; |
| 2107 | |
| 2108 | // GPRPair_with_sub_gpr_odd_in_GPRTCNonX7 Bit set. |
| 2109 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRTCNonX7Bits[] = { |
| 2110 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xc1, |
| 2111 | }; |
| 2112 | |
| 2113 | // GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7 Register Class... |
| 2114 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7[] = { |
| 2115 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X28_X29, |
| 2116 | }; |
| 2117 | |
| 2118 | // GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7 Bit set. |
| 2119 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7Bits[] = { |
| 2120 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x41, |
| 2121 | }; |
| 2122 | |
| 2123 | // GPRPairC Register Class... |
| 2124 | const MCPhysReg GPRPairC[] = { |
| 2125 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X8_X9, |
| 2126 | }; |
| 2127 | |
| 2128 | // GPRPairC Bit set. |
| 2129 | const uint8_t GPRPairCBits[] = { |
| 2130 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, |
| 2131 | }; |
| 2132 | |
| 2133 | // GPRPair_with_sub_gpr_even_in_SR07 Register Class... |
| 2134 | const MCPhysReg GPRPair_with_sub_gpr_even_in_SR07[] = { |
| 2135 | RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, |
| 2136 | }; |
| 2137 | |
| 2138 | // GPRPair_with_sub_gpr_even_in_SR07 Bit set. |
| 2139 | const uint8_t GPRPair_with_sub_gpr_even_in_SR07Bits[] = { |
| 2140 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, |
| 2141 | }; |
| 2142 | |
| 2143 | // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC Register Class... |
| 2144 | const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC[] = { |
| 2145 | RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, |
| 2146 | }; |
| 2147 | |
| 2148 | // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC Bit set. |
| 2149 | const uint8_t GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits[] = { |
| 2150 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, |
| 2151 | }; |
| 2152 | |
| 2153 | // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07 Register Class... |
| 2154 | const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRC_and_SR07[] = { |
| 2155 | RISCV::X8_X9, |
| 2156 | }; |
| 2157 | |
| 2158 | // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07 Bit set. |
| 2159 | const uint8_t GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits[] = { |
| 2160 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 2161 | }; |
| 2162 | |
| 2163 | // GPRPair_with_sub_gpr_even_in_GPRX0 Register Class... |
| 2164 | const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRX0[] = { |
| 2165 | RISCV::X0_Pair, |
| 2166 | }; |
| 2167 | |
| 2168 | // GPRPair_with_sub_gpr_even_in_GPRX0 Bit set. |
| 2169 | const uint8_t GPRPair_with_sub_gpr_even_in_GPRX0Bits[] = { |
| 2170 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 2171 | }; |
| 2172 | |
| 2173 | // GPRPair_with_sub_gpr_even_in_SP Register Class... |
| 2174 | const MCPhysReg GPRPair_with_sub_gpr_even_in_SP[] = { |
| 2175 | RISCV::X2_X3, |
| 2176 | }; |
| 2177 | |
| 2178 | // GPRPair_with_sub_gpr_even_in_SP Bit set. |
| 2179 | const uint8_t GPRPair_with_sub_gpr_even_in_SPBits[] = { |
| 2180 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, |
| 2181 | }; |
| 2182 | |
| 2183 | // GPRPair_with_sub_gpr_odd_in_GPRX1X5 Register Class... |
| 2184 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRX1X5[] = { |
| 2185 | RISCV::X4_X5, |
| 2186 | }; |
| 2187 | |
| 2188 | // GPRPair_with_sub_gpr_odd_in_GPRX1X5 Bit set. |
| 2189 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits[] = { |
| 2190 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, |
| 2191 | }; |
| 2192 | |
| 2193 | // GPRPair_with_sub_gpr_odd_in_GPRX7 Register Class... |
| 2194 | const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRX7[] = { |
| 2195 | RISCV::X6_X7, |
| 2196 | }; |
| 2197 | |
| 2198 | // GPRPair_with_sub_gpr_odd_in_GPRX7 Bit set. |
| 2199 | const uint8_t GPRPair_with_sub_gpr_odd_in_GPRX7Bits[] = { |
| 2200 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, |
| 2201 | }; |
| 2202 | |
| 2203 | // FPR64 Register Class... |
| 2204 | const MCPhysReg FPR64[] = { |
| 2205 | RISCV::F15_D, RISCV::F14_D, RISCV::F13_D, RISCV::F12_D, RISCV::F11_D, RISCV::F10_D, RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F16_D, RISCV::F17_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, |
| 2206 | }; |
| 2207 | |
| 2208 | // FPR64 Bit set. |
| 2209 | const uint8_t FPR64Bits[] = { |
| 2210 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 2211 | }; |
| 2212 | |
| 2213 | // VR Register Class... |
| 2214 | const MCPhysReg VR[] = { |
| 2215 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 2216 | }; |
| 2217 | |
| 2218 | // VR Bit set. |
| 2219 | const uint8_t VRBits[] = { |
| 2220 | 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 2221 | }; |
| 2222 | |
| 2223 | // YGPR Register Class... |
| 2224 | const MCPhysReg YGPR[] = { |
| 2225 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X0_Y, RISCV::X1_Y, RISCV::X2_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 2226 | }; |
| 2227 | |
| 2228 | // YGPR Bit set. |
| 2229 | const uint8_t YGPRBits[] = { |
| 2230 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, |
| 2231 | }; |
| 2232 | |
| 2233 | // ZZZ_VM Register Class... |
| 2234 | const MCPhysReg ZZZ_VM[] = { |
| 2235 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 2236 | }; |
| 2237 | |
| 2238 | // ZZZ_VM Bit set. |
| 2239 | const uint8_t ZZZ_VMBits[] = { |
| 2240 | 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 2241 | }; |
| 2242 | |
| 2243 | // ZZZ_VRMF2 Register Class... |
| 2244 | const MCPhysReg ZZZ_VRMF2[] = { |
| 2245 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 2246 | }; |
| 2247 | |
| 2248 | // ZZZ_VRMF2 Bit set. |
| 2249 | const uint8_t ZZZ_VRMF2Bits[] = { |
| 2250 | 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 2251 | }; |
| 2252 | |
| 2253 | // ZZZ_VRMF4 Register Class... |
| 2254 | const MCPhysReg ZZZ_VRMF4[] = { |
| 2255 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 2256 | }; |
| 2257 | |
| 2258 | // ZZZ_VRMF4 Bit set. |
| 2259 | const uint8_t ZZZ_VRMF4Bits[] = { |
| 2260 | 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 2261 | }; |
| 2262 | |
| 2263 | // ZZZ_VRMF8 Register Class... |
| 2264 | const MCPhysReg ZZZ_VRMF8[] = { |
| 2265 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, RISCV::V0, |
| 2266 | }; |
| 2267 | |
| 2268 | // ZZZ_VRMF8 Bit set. |
| 2269 | const uint8_t ZZZ_VRMF8Bits[] = { |
| 2270 | 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 2271 | }; |
| 2272 | |
| 2273 | // VRNoV0 Register Class... |
| 2274 | const MCPhysReg VRNoV0[] = { |
| 2275 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 2276 | }; |
| 2277 | |
| 2278 | // VRNoV0 Bit set. |
| 2279 | const uint8_t VRNoV0Bits[] = { |
| 2280 | 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, |
| 2281 | }; |
| 2282 | |
| 2283 | // YGPR_with_sub_16_in_GPRF16NoX0 Register Class... |
| 2284 | const MCPhysReg YGPR_with_sub_16_in_GPRF16NoX0[] = { |
| 2285 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X1_Y, RISCV::X2_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 2286 | }; |
| 2287 | |
| 2288 | // YGPR_with_sub_16_in_GPRF16NoX0 Bit set. |
| 2289 | const uint8_t YGPR_with_sub_16_in_GPRF16NoX0Bits[] = { |
| 2290 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, |
| 2291 | }; |
| 2292 | |
| 2293 | // YGPR_with_sub_cap_addr_in_GPRNoX2 Register Class... |
| 2294 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRNoX2[] = { |
| 2295 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X0_Y, RISCV::X1_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 2296 | }; |
| 2297 | |
| 2298 | // YGPR_with_sub_cap_addr_in_GPRNoX2 Bit set. |
| 2299 | const uint8_t YGPR_with_sub_cap_addr_in_GPRNoX2Bits[] = { |
| 2300 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f, |
| 2301 | }; |
| 2302 | |
| 2303 | // YGPR_with_sub_cap_addr_in_GPRNoX31 Register Class... |
| 2304 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRNoX31[] = { |
| 2305 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X0_Y, RISCV::X1_Y, RISCV::X2_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 2306 | }; |
| 2307 | |
| 2308 | // YGPR_with_sub_cap_addr_in_GPRNoX31 Bit set. |
| 2309 | const uint8_t YGPR_with_sub_cap_addr_in_GPRNoX31Bits[] = { |
| 2310 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, |
| 2311 | }; |
| 2312 | |
| 2313 | // ZZZ_VMNoV0 Register Class... |
| 2314 | const MCPhysReg ZZZ_VMNoV0[] = { |
| 2315 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 2316 | }; |
| 2317 | |
| 2318 | // ZZZ_VMNoV0 Bit set. |
| 2319 | const uint8_t ZZZ_VMNoV0Bits[] = { |
| 2320 | 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, |
| 2321 | }; |
| 2322 | |
| 2323 | // ZZZ_VRMF2NoV0 Register Class... |
| 2324 | const MCPhysReg ZZZ_VRMF2NoV0[] = { |
| 2325 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 2326 | }; |
| 2327 | |
| 2328 | // ZZZ_VRMF2NoV0 Bit set. |
| 2329 | const uint8_t ZZZ_VRMF2NoV0Bits[] = { |
| 2330 | 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, |
| 2331 | }; |
| 2332 | |
| 2333 | // ZZZ_VRMF4NoV0 Register Class... |
| 2334 | const MCPhysReg ZZZ_VRMF4NoV0[] = { |
| 2335 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 2336 | }; |
| 2337 | |
| 2338 | // ZZZ_VRMF4NoV0 Bit set. |
| 2339 | const uint8_t ZZZ_VRMF4NoV0Bits[] = { |
| 2340 | 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, |
| 2341 | }; |
| 2342 | |
| 2343 | // ZZZ_VRMF8NoV0 Register Class... |
| 2344 | const MCPhysReg ZZZ_VRMF8NoV0[] = { |
| 2345 | RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V7, RISCV::V6, RISCV::V5, RISCV::V4, RISCV::V3, RISCV::V2, RISCV::V1, |
| 2346 | }; |
| 2347 | |
| 2348 | // ZZZ_VRMF8NoV0 Bit set. |
| 2349 | const uint8_t ZZZ_VRMF8NoV0Bits[] = { |
| 2350 | 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, |
| 2351 | }; |
| 2352 | |
| 2353 | // YGPR_with_sub_cap_addr_in_GPRNoX0X2 Register Class... |
| 2354 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRNoX0X2[] = { |
| 2355 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X1_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 2356 | }; |
| 2357 | |
| 2358 | // YGPR_with_sub_cap_addr_in_GPRNoX0X2 Bit set. |
| 2359 | const uint8_t YGPR_with_sub_cap_addr_in_GPRNoX0X2Bits[] = { |
| 2360 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xff, 0xff, 0xff, 0x1f, |
| 2361 | }; |
| 2362 | |
| 2363 | // YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31 Register Class... |
| 2364 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31[] = { |
| 2365 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X1_Y, RISCV::X2_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 2366 | }; |
| 2367 | |
| 2368 | // YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31 Bit set. |
| 2369 | const uint8_t YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31Bits[] = { |
| 2370 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, |
| 2371 | }; |
| 2372 | |
| 2373 | // YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31 Register Class... |
| 2374 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31[] = { |
| 2375 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X0_Y, RISCV::X1_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 2376 | }; |
| 2377 | |
| 2378 | // YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31 Bit set. |
| 2379 | const uint8_t YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31Bits[] = { |
| 2380 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x0f, |
| 2381 | }; |
| 2382 | |
| 2383 | // YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31 Register Class... |
| 2384 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31[] = { |
| 2385 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X5_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, RISCV::X1_Y, RISCV::X3_Y, RISCV::X4_Y, |
| 2386 | }; |
| 2387 | |
| 2388 | // YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31 Bit set. |
| 2389 | const uint8_t YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31Bits[] = { |
| 2390 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xff, 0xff, 0xff, 0x0f, |
| 2391 | }; |
| 2392 | |
| 2393 | // YGPR_with_sub_cap_addr_in_GPRJALR Register Class... |
| 2394 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRJALR[] = { |
| 2395 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, |
| 2396 | }; |
| 2397 | |
| 2398 | // YGPR_with_sub_cap_addr_in_GPRJALR Bit set. |
| 2399 | const uint8_t YGPR_with_sub_cap_addr_in_GPRJALRBits[] = { |
| 2400 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x1f, |
| 2401 | }; |
| 2402 | |
| 2403 | // YGPR_with_sub_cap_addr_in_GPRJALRNonX7 Register Class... |
| 2404 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRJALRNonX7[] = { |
| 2405 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, |
| 2406 | }; |
| 2407 | |
| 2408 | // YGPR_with_sub_cap_addr_in_GPRJALRNonX7 Bit set. |
| 2409 | const uint8_t YGPR_with_sub_cap_addr_in_GPRJALRNonX7Bits[] = { |
| 2410 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0xff, 0xff, 0x1f, |
| 2411 | }; |
| 2412 | |
| 2413 | // YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31 Register Class... |
| 2414 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31[] = { |
| 2415 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, |
| 2416 | }; |
| 2417 | |
| 2418 | // YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31 Bit set. |
| 2419 | const uint8_t YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31Bits[] = { |
| 2420 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x0f, |
| 2421 | }; |
| 2422 | |
| 2423 | // YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31 Register Class... |
| 2424 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31[] = { |
| 2425 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, RISCV::X24_Y, RISCV::X25_Y, RISCV::X26_Y, RISCV::X27_Y, |
| 2426 | }; |
| 2427 | |
| 2428 | // YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31 Bit set. |
| 2429 | const uint8_t YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31Bits[] = { |
| 2430 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0xff, 0xff, 0x0f, |
| 2431 | }; |
| 2432 | |
| 2433 | // YGPR_with_sub_cap_addr_in_GPRTC Register Class... |
| 2434 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRTC[] = { |
| 2435 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, |
| 2436 | }; |
| 2437 | |
| 2438 | // YGPR_with_sub_cap_addr_in_GPRTC Bit set. |
| 2439 | const uint8_t YGPR_with_sub_cap_addr_in_GPRTCBits[] = { |
| 2440 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x7f, 0x00, 0x1e, |
| 2441 | }; |
| 2442 | |
| 2443 | // YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTC Register Class... |
| 2444 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTC[] = { |
| 2445 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X7_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, |
| 2446 | }; |
| 2447 | |
| 2448 | // YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTC Bit set. |
| 2449 | const uint8_t YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCBits[] = { |
| 2450 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x7f, 0x00, 0x0e, |
| 2451 | }; |
| 2452 | |
| 2453 | // YGPR_with_sub_cap_addr_in_GPRTCNonX7 Register Class... |
| 2454 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRTCNonX7[] = { |
| 2455 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y, |
| 2456 | }; |
| 2457 | |
| 2458 | // YGPR_with_sub_cap_addr_in_GPRTCNonX7 Bit set. |
| 2459 | const uint8_t YGPR_with_sub_cap_addr_in_GPRTCNonX7Bits[] = { |
| 2460 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x7f, 0x00, 0x1e, |
| 2461 | }; |
| 2462 | |
| 2463 | // YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7 Register Class... |
| 2464 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7[] = { |
| 2465 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X6_Y, RISCV::X28_Y, RISCV::X29_Y, RISCV::X30_Y, |
| 2466 | }; |
| 2467 | |
| 2468 | // YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7 Bit set. |
| 2469 | const uint8_t YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7Bits[] = { |
| 2470 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x7f, 0x00, 0x0e, |
| 2471 | }; |
| 2472 | |
| 2473 | // FPR64C Register Class... |
| 2474 | const MCPhysReg FPR64C[] = { |
| 2475 | RISCV::F15_D, RISCV::F14_D, RISCV::F13_D, RISCV::F12_D, RISCV::F11_D, RISCV::F10_D, RISCV::F8_D, RISCV::F9_D, |
| 2476 | }; |
| 2477 | |
| 2478 | // FPR64C Bit set. |
| 2479 | const uint8_t FPR64CBits[] = { |
| 2480 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| 2481 | }; |
| 2482 | |
| 2483 | // YGPR_with_sub_16_in_GPRF16C Register Class... |
| 2484 | const MCPhysReg YGPR_with_sub_16_in_GPRF16C[] = { |
| 2485 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, RISCV::X8_Y, RISCV::X9_Y, |
| 2486 | }; |
| 2487 | |
| 2488 | // YGPR_with_sub_16_in_GPRF16C Bit set. |
| 2489 | const uint8_t YGPR_with_sub_16_in_GPRF16CBits[] = { |
| 2490 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, |
| 2491 | }; |
| 2492 | |
| 2493 | // YGPR_with_sub_cap_addr_in_SR07 Register Class... |
| 2494 | const MCPhysReg YGPR_with_sub_cap_addr_in_SR07[] = { |
| 2495 | RISCV::X8_Y, RISCV::X9_Y, RISCV::X18_Y, RISCV::X19_Y, RISCV::X20_Y, RISCV::X21_Y, RISCV::X22_Y, RISCV::X23_Y, |
| 2496 | }; |
| 2497 | |
| 2498 | // YGPR_with_sub_cap_addr_in_SR07 Bit set. |
| 2499 | const uint8_t YGPR_with_sub_cap_addr_in_SR07Bits[] = { |
| 2500 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x80, 0x1f, |
| 2501 | }; |
| 2502 | |
| 2503 | // YGPR_with_sub_cap_addr_in_GPRC_and_GPRTC Register Class... |
| 2504 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRC_and_GPRTC[] = { |
| 2505 | RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y, RISCV::X15_Y, |
| 2506 | }; |
| 2507 | |
| 2508 | // YGPR_with_sub_cap_addr_in_GPRC_and_GPRTC Bit set. |
| 2509 | const uint8_t YGPR_with_sub_cap_addr_in_GPRC_and_GPRTCBits[] = { |
| 2510 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, |
| 2511 | }; |
| 2512 | |
| 2513 | // YGPR_with_sub_cap_addr_in_GPRC_and_SR07 Register Class... |
| 2514 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRC_and_SR07[] = { |
| 2515 | RISCV::X8_Y, RISCV::X9_Y, |
| 2516 | }; |
| 2517 | |
| 2518 | // YGPR_with_sub_cap_addr_in_GPRC_and_SR07 Bit set. |
| 2519 | const uint8_t YGPR_with_sub_cap_addr_in_GPRC_and_SR07Bits[] = { |
| 2520 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, |
| 2521 | }; |
| 2522 | |
| 2523 | // YGPR_with_sub_cap_addr_in_GPRX1X5 Register Class... |
| 2524 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRX1X5[] = { |
| 2525 | RISCV::X5_Y, RISCV::X1_Y, |
| 2526 | }; |
| 2527 | |
| 2528 | // YGPR_with_sub_cap_addr_in_GPRX1X5 Bit set. |
| 2529 | const uint8_t YGPR_with_sub_cap_addr_in_GPRX1X5Bits[] = { |
| 2530 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x04, |
| 2531 | }; |
| 2532 | |
| 2533 | // VMV0 Register Class... |
| 2534 | const MCPhysReg VMV0[] = { |
| 2535 | RISCV::V0, |
| 2536 | }; |
| 2537 | |
| 2538 | // VMV0 Bit set. |
| 2539 | const uint8_t VMV0Bits[] = { |
| 2540 | 0x00, 0x00, 0x00, 0x00, 0x10, |
| 2541 | }; |
| 2542 | |
| 2543 | // YGPR_with_sub_cap_addr_in_GPRX0 Register Class... |
| 2544 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRX0[] = { |
| 2545 | RISCV::X0_Y, |
| 2546 | }; |
| 2547 | |
| 2548 | // YGPR_with_sub_cap_addr_in_GPRX0 Bit set. |
| 2549 | const uint8_t YGPR_with_sub_cap_addr_in_GPRX0Bits[] = { |
| 2550 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| 2551 | }; |
| 2552 | |
| 2553 | // YGPR_with_sub_cap_addr_in_GPRX1 Register Class... |
| 2554 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRX1[] = { |
| 2555 | RISCV::X1_Y, |
| 2556 | }; |
| 2557 | |
| 2558 | // YGPR_with_sub_cap_addr_in_GPRX1 Bit set. |
| 2559 | const uint8_t YGPR_with_sub_cap_addr_in_GPRX1Bits[] = { |
| 2560 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| 2561 | }; |
| 2562 | |
| 2563 | // YGPR_with_sub_cap_addr_in_GPRX5 Register Class... |
| 2564 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRX5[] = { |
| 2565 | RISCV::X5_Y, |
| 2566 | }; |
| 2567 | |
| 2568 | // YGPR_with_sub_cap_addr_in_GPRX5 Bit set. |
| 2569 | const uint8_t YGPR_with_sub_cap_addr_in_GPRX5Bits[] = { |
| 2570 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, |
| 2571 | }; |
| 2572 | |
| 2573 | // YGPR_with_sub_cap_addr_in_GPRX7 Register Class... |
| 2574 | const MCPhysReg YGPR_with_sub_cap_addr_in_GPRX7[] = { |
| 2575 | RISCV::X7_Y, |
| 2576 | }; |
| 2577 | |
| 2578 | // YGPR_with_sub_cap_addr_in_GPRX7 Bit set. |
| 2579 | const uint8_t YGPR_with_sub_cap_addr_in_GPRX7Bits[] = { |
| 2580 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 2581 | }; |
| 2582 | |
| 2583 | // YGPR_with_sub_cap_addr_in_SP Register Class... |
| 2584 | const MCPhysReg YGPR_with_sub_cap_addr_in_SP[] = { |
| 2585 | RISCV::X2_Y, |
| 2586 | }; |
| 2587 | |
| 2588 | // YGPR_with_sub_cap_addr_in_SP Bit set. |
| 2589 | const uint8_t YGPR_with_sub_cap_addr_in_SPBits[] = { |
| 2590 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, |
| 2591 | }; |
| 2592 | |
| 2593 | // VRN2M1 Register Class... |
| 2594 | const MCPhysReg VRN2M1[] = { |
| 2595 | RISCV::V8_V9, RISCV::V9_V10, RISCV::V10_V11, RISCV::V11_V12, RISCV::V12_V13, RISCV::V13_V14, RISCV::V14_V15, RISCV::V15_V16, RISCV::V16_V17, RISCV::V17_V18, RISCV::V18_V19, RISCV::V19_V20, RISCV::V20_V21, RISCV::V21_V22, RISCV::V22_V23, RISCV::V23_V24, RISCV::V24_V25, RISCV::V25_V26, RISCV::V26_V27, RISCV::V27_V28, RISCV::V28_V29, RISCV::V29_V30, RISCV::V30_V31, RISCV::V1_V2, RISCV::V2_V3, RISCV::V3_V4, RISCV::V4_V5, RISCV::V5_V6, RISCV::V6_V7, RISCV::V7_V8, RISCV::V0_V1, |
| 2596 | }; |
| 2597 | |
| 2598 | // VRN2M1 Bit set. |
| 2599 | const uint8_t VRN2M1Bits[] = { |
| 2600 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, |
| 2601 | }; |
| 2602 | |
| 2603 | // VRN2M1NoV0 Register Class... |
| 2604 | const MCPhysReg VRN2M1NoV0[] = { |
| 2605 | RISCV::V8_V9, RISCV::V9_V10, RISCV::V10_V11, RISCV::V11_V12, RISCV::V12_V13, RISCV::V13_V14, RISCV::V14_V15, RISCV::V15_V16, RISCV::V16_V17, RISCV::V17_V18, RISCV::V18_V19, RISCV::V19_V20, RISCV::V20_V21, RISCV::V21_V22, RISCV::V22_V23, RISCV::V23_V24, RISCV::V24_V25, RISCV::V25_V26, RISCV::V26_V27, RISCV::V27_V28, RISCV::V28_V29, RISCV::V29_V30, RISCV::V30_V31, RISCV::V1_V2, RISCV::V2_V3, RISCV::V3_V4, RISCV::V4_V5, RISCV::V5_V6, RISCV::V6_V7, RISCV::V7_V8, |
| 2606 | }; |
| 2607 | |
| 2608 | // VRN2M1NoV0 Bit set. |
| 2609 | const uint8_t VRN2M1NoV0Bits[] = { |
| 2610 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, |
| 2611 | }; |
| 2612 | |
| 2613 | // VRM2 Register Class... |
| 2614 | const MCPhysReg VRM2[] = { |
| 2615 | RISCV::V8M2, RISCV::V10M2, RISCV::V12M2, RISCV::V14M2, RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2, RISCV::V24M2, RISCV::V26M2, RISCV::V28M2, RISCV::V30M2, RISCV::V6M2, RISCV::V4M2, RISCV::V2M2, RISCV::V0M2, |
| 2616 | }; |
| 2617 | |
| 2618 | // VRM2 Bit set. |
| 2619 | const uint8_t VRM2Bits[] = { |
| 2620 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x9b, 0xcd, 0x66, 0x01, |
| 2621 | }; |
| 2622 | |
| 2623 | // VRM2NoV0 Register Class... |
| 2624 | const MCPhysReg VRM2NoV0[] = { |
| 2625 | RISCV::V8M2, RISCV::V10M2, RISCV::V12M2, RISCV::V14M2, RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2, RISCV::V24M2, RISCV::V26M2, RISCV::V28M2, RISCV::V30M2, RISCV::V6M2, RISCV::V4M2, RISCV::V2M2, |
| 2626 | }; |
| 2627 | |
| 2628 | // VRM2NoV0 Bit set. |
| 2629 | const uint8_t VRM2NoV0Bits[] = { |
| 2630 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9b, 0xcd, 0x66, 0x01, |
| 2631 | }; |
| 2632 | |
| 2633 | // VRM2_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2634 | const MCPhysReg VRM2_with_sub_vrm1_0_in_VMV0[] = { |
| 2635 | RISCV::V0M2, |
| 2636 | }; |
| 2637 | |
| 2638 | // VRM2_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2639 | const uint8_t VRM2_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2640 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| 2641 | }; |
| 2642 | |
| 2643 | // VRN2M1_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2644 | const MCPhysReg VRN2M1_with_sub_vrm1_0_in_VMV0[] = { |
| 2645 | RISCV::V0_V1, |
| 2646 | }; |
| 2647 | |
| 2648 | // VRN2M1_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2649 | const uint8_t VRN2M1_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2650 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| 2651 | }; |
| 2652 | |
| 2653 | // FPR128 Register Class... |
| 2654 | const MCPhysReg FPR128[] = { |
| 2655 | RISCV::F15_Q, RISCV::F14_Q, RISCV::F13_Q, RISCV::F12_Q, RISCV::F11_Q, RISCV::F10_Q, RISCV::F0_Q, RISCV::F1_Q, RISCV::F2_Q, RISCV::F3_Q, RISCV::F4_Q, RISCV::F5_Q, RISCV::F6_Q, RISCV::F7_Q, RISCV::F16_Q, RISCV::F17_Q, RISCV::F28_Q, RISCV::F29_Q, RISCV::F30_Q, RISCV::F31_Q, RISCV::F8_Q, RISCV::F9_Q, RISCV::F18_Q, RISCV::F19_Q, RISCV::F20_Q, RISCV::F21_Q, RISCV::F22_Q, RISCV::F23_Q, RISCV::F24_Q, RISCV::F25_Q, RISCV::F26_Q, RISCV::F27_Q, |
| 2656 | }; |
| 2657 | |
| 2658 | // FPR128 Bit set. |
| 2659 | const uint8_t FPR128Bits[] = { |
| 2660 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| 2661 | }; |
| 2662 | |
| 2663 | // FPR128_with_sub_16_in_FPR16C Register Class... |
| 2664 | const MCPhysReg FPR128_with_sub_16_in_FPR16C[] = { |
| 2665 | RISCV::F15_Q, RISCV::F14_Q, RISCV::F13_Q, RISCV::F12_Q, RISCV::F11_Q, RISCV::F10_Q, RISCV::F8_Q, RISCV::F9_Q, |
| 2666 | }; |
| 2667 | |
| 2668 | // FPR128_with_sub_16_in_FPR16C Bit set. |
| 2669 | const uint8_t FPR128_with_sub_16_in_FPR16CBits[] = { |
| 2670 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| 2671 | }; |
| 2672 | |
| 2673 | // VRN3M1 Register Class... |
| 2674 | const MCPhysReg VRN3M1[] = { |
| 2675 | RISCV::V8_V9_V10, RISCV::V9_V10_V11, RISCV::V10_V11_V12, RISCV::V11_V12_V13, RISCV::V12_V13_V14, RISCV::V13_V14_V15, RISCV::V14_V15_V16, RISCV::V15_V16_V17, RISCV::V16_V17_V18, RISCV::V17_V18_V19, RISCV::V18_V19_V20, RISCV::V19_V20_V21, RISCV::V20_V21_V22, RISCV::V21_V22_V23, RISCV::V22_V23_V24, RISCV::V23_V24_V25, RISCV::V24_V25_V26, RISCV::V25_V26_V27, RISCV::V26_V27_V28, RISCV::V27_V28_V29, RISCV::V28_V29_V30, RISCV::V29_V30_V31, RISCV::V1_V2_V3, RISCV::V2_V3_V4, RISCV::V3_V4_V5, RISCV::V4_V5_V6, RISCV::V5_V6_V7, RISCV::V6_V7_V8, RISCV::V7_V8_V9, RISCV::V0_V1_V2, |
| 2676 | }; |
| 2677 | |
| 2678 | // VRN3M1 Bit set. |
| 2679 | const uint8_t VRN3M1Bits[] = { |
| 2680 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x07, |
| 2681 | }; |
| 2682 | |
| 2683 | // VRN3M1NoV0 Register Class... |
| 2684 | const MCPhysReg VRN3M1NoV0[] = { |
| 2685 | RISCV::V8_V9_V10, RISCV::V9_V10_V11, RISCV::V10_V11_V12, RISCV::V11_V12_V13, RISCV::V12_V13_V14, RISCV::V13_V14_V15, RISCV::V14_V15_V16, RISCV::V15_V16_V17, RISCV::V16_V17_V18, RISCV::V17_V18_V19, RISCV::V18_V19_V20, RISCV::V19_V20_V21, RISCV::V20_V21_V22, RISCV::V21_V22_V23, RISCV::V22_V23_V24, RISCV::V23_V24_V25, RISCV::V24_V25_V26, RISCV::V25_V26_V27, RISCV::V26_V27_V28, RISCV::V27_V28_V29, RISCV::V28_V29_V30, RISCV::V29_V30_V31, RISCV::V1_V2_V3, RISCV::V2_V3_V4, RISCV::V3_V4_V5, RISCV::V4_V5_V6, RISCV::V5_V6_V7, RISCV::V6_V7_V8, RISCV::V7_V8_V9, |
| 2686 | }; |
| 2687 | |
| 2688 | // VRN3M1NoV0 Bit set. |
| 2689 | const uint8_t VRN3M1NoV0Bits[] = { |
| 2690 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x03, |
| 2691 | }; |
| 2692 | |
| 2693 | // VRN3M1_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2694 | const MCPhysReg VRN3M1_with_sub_vrm1_0_in_VMV0[] = { |
| 2695 | RISCV::V0_V1_V2, |
| 2696 | }; |
| 2697 | |
| 2698 | // VRN3M1_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2699 | const uint8_t VRN3M1_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2700 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, |
| 2701 | }; |
| 2702 | |
| 2703 | // VRN4M1 Register Class... |
| 2704 | const MCPhysReg VRN4M1[] = { |
| 2705 | RISCV::V8_V9_V10_V11, RISCV::V9_V10_V11_V12, RISCV::V10_V11_V12_V13, RISCV::V11_V12_V13_V14, RISCV::V12_V13_V14_V15, RISCV::V13_V14_V15_V16, RISCV::V14_V15_V16_V17, RISCV::V15_V16_V17_V18, RISCV::V16_V17_V18_V19, RISCV::V17_V18_V19_V20, RISCV::V18_V19_V20_V21, RISCV::V19_V20_V21_V22, RISCV::V20_V21_V22_V23, RISCV::V21_V22_V23_V24, RISCV::V22_V23_V24_V25, RISCV::V23_V24_V25_V26, RISCV::V24_V25_V26_V27, RISCV::V25_V26_V27_V28, RISCV::V26_V27_V28_V29, RISCV::V27_V28_V29_V30, RISCV::V28_V29_V30_V31, RISCV::V1_V2_V3_V4, RISCV::V2_V3_V4_V5, RISCV::V3_V4_V5_V6, RISCV::V4_V5_V6_V7, RISCV::V5_V6_V7_V8, RISCV::V6_V7_V8_V9, RISCV::V7_V8_V9_V10, RISCV::V0_V1_V2_V3, |
| 2706 | }; |
| 2707 | |
| 2708 | // VRN4M1 Bit set. |
| 2709 | const uint8_t VRN4M1Bits[] = { |
| 2710 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x3f, |
| 2711 | }; |
| 2712 | |
| 2713 | // VRN4M1NoV0 Register Class... |
| 2714 | const MCPhysReg VRN4M1NoV0[] = { |
| 2715 | RISCV::V8_V9_V10_V11, RISCV::V9_V10_V11_V12, RISCV::V10_V11_V12_V13, RISCV::V11_V12_V13_V14, RISCV::V12_V13_V14_V15, RISCV::V13_V14_V15_V16, RISCV::V14_V15_V16_V17, RISCV::V15_V16_V17_V18, RISCV::V16_V17_V18_V19, RISCV::V17_V18_V19_V20, RISCV::V18_V19_V20_V21, RISCV::V19_V20_V21_V22, RISCV::V20_V21_V22_V23, RISCV::V21_V22_V23_V24, RISCV::V22_V23_V24_V25, RISCV::V23_V24_V25_V26, RISCV::V24_V25_V26_V27, RISCV::V25_V26_V27_V28, RISCV::V26_V27_V28_V29, RISCV::V27_V28_V29_V30, RISCV::V28_V29_V30_V31, RISCV::V1_V2_V3_V4, RISCV::V2_V3_V4_V5, RISCV::V3_V4_V5_V6, RISCV::V4_V5_V6_V7, RISCV::V5_V6_V7_V8, RISCV::V6_V7_V8_V9, RISCV::V7_V8_V9_V10, |
| 2716 | }; |
| 2717 | |
| 2718 | // VRN4M1NoV0 Bit set. |
| 2719 | const uint8_t VRN4M1NoV0Bits[] = { |
| 2720 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x1f, |
| 2721 | }; |
| 2722 | |
| 2723 | // VRN2M2 Register Class... |
| 2724 | const MCPhysReg VRN2M2[] = { |
| 2725 | RISCV::V8M2_V10M2, RISCV::V10M2_V12M2, RISCV::V12M2_V14M2, RISCV::V14M2_V16M2, RISCV::V16M2_V18M2, RISCV::V18M2_V20M2, RISCV::V20M2_V22M2, RISCV::V22M2_V24M2, RISCV::V24M2_V26M2, RISCV::V26M2_V28M2, RISCV::V28M2_V30M2, RISCV::V2M2_V4M2, RISCV::V4M2_V6M2, RISCV::V6M2_V8M2, RISCV::V0M2_V2M2, |
| 2726 | }; |
| 2727 | |
| 2728 | // VRN2M2 Bit set. |
| 2729 | const uint8_t VRN2M2Bits[] = { |
| 2730 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f, |
| 2731 | }; |
| 2732 | |
| 2733 | // VRN2M2NoV0 Register Class... |
| 2734 | const MCPhysReg VRN2M2NoV0[] = { |
| 2735 | RISCV::V8M2_V10M2, RISCV::V10M2_V12M2, RISCV::V12M2_V14M2, RISCV::V14M2_V16M2, RISCV::V16M2_V18M2, RISCV::V18M2_V20M2, RISCV::V20M2_V22M2, RISCV::V22M2_V24M2, RISCV::V24M2_V26M2, RISCV::V26M2_V28M2, RISCV::V28M2_V30M2, RISCV::V2M2_V4M2, RISCV::V4M2_V6M2, RISCV::V6M2_V8M2, |
| 2736 | }; |
| 2737 | |
| 2738 | // VRN2M2NoV0 Bit set. |
| 2739 | const uint8_t VRN2M2NoV0Bits[] = { |
| 2740 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, |
| 2741 | }; |
| 2742 | |
| 2743 | // VRM4 Register Class... |
| 2744 | const MCPhysReg VRM4[] = { |
| 2745 | RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4, RISCV::V24M4, RISCV::V28M4, RISCV::V4M4, RISCV::V0M4, |
| 2746 | }; |
| 2747 | |
| 2748 | // VRM4 Bit set. |
| 2749 | const uint8_t VRM4Bits[] = { |
| 2750 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x24, 0x12, 0x89, |
| 2751 | }; |
| 2752 | |
| 2753 | // VRM4NoV0 Register Class... |
| 2754 | const MCPhysReg VRM4NoV0[] = { |
| 2755 | RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4, RISCV::V24M4, RISCV::V28M4, RISCV::V4M4, |
| 2756 | }; |
| 2757 | |
| 2758 | // VRM4NoV0 Bit set. |
| 2759 | const uint8_t VRM4NoV0Bits[] = { |
| 2760 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x12, 0x89, |
| 2761 | }; |
| 2762 | |
| 2763 | // VRM4_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2764 | const MCPhysReg VRM4_with_sub_vrm1_0_in_VMV0[] = { |
| 2765 | RISCV::V0M4, |
| 2766 | }; |
| 2767 | |
| 2768 | // VRM4_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2769 | const uint8_t VRM4_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2770 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| 2771 | }; |
| 2772 | |
| 2773 | // VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2774 | const MCPhysReg VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0[] = { |
| 2775 | RISCV::V0M2_V2M2, |
| 2776 | }; |
| 2777 | |
| 2778 | // VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2779 | const uint8_t VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2780 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| 2781 | }; |
| 2782 | |
| 2783 | // VRN4M1_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2784 | const MCPhysReg VRN4M1_with_sub_vrm1_0_in_VMV0[] = { |
| 2785 | RISCV::V0_V1_V2_V3, |
| 2786 | }; |
| 2787 | |
| 2788 | // VRN4M1_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2789 | const uint8_t VRN4M1_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2790 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| 2791 | }; |
| 2792 | |
| 2793 | // FPR256 Register Class... |
| 2794 | const MCPhysReg FPR256[] = { |
| 2795 | RISCV::F15_Q2, RISCV::F14_Q2, RISCV::F13_Q2, RISCV::F12_Q2, RISCV::F11_Q2, RISCV::F10_Q2, RISCV::F0_Q2, RISCV::F1_Q2, RISCV::F2_Q2, RISCV::F3_Q2, RISCV::F4_Q2, RISCV::F5_Q2, RISCV::F6_Q2, RISCV::F7_Q2, RISCV::F16_Q2, RISCV::F17_Q2, RISCV::F28_Q2, RISCV::F29_Q2, RISCV::F30_Q2, RISCV::F31_Q2, RISCV::F8_Q2, RISCV::F9_Q2, RISCV::F18_Q2, RISCV::F19_Q2, RISCV::F20_Q2, RISCV::F21_Q2, RISCV::F22_Q2, RISCV::F23_Q2, RISCV::F24_Q2, RISCV::F25_Q2, RISCV::F26_Q2, RISCV::F27_Q2, |
| 2796 | }; |
| 2797 | |
| 2798 | // FPR256 Bit set. |
| 2799 | const uint8_t FPR256Bits[] = { |
| 2800 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, |
| 2801 | }; |
| 2802 | |
| 2803 | // FPR256_with_sub_16_in_FPR16C Register Class... |
| 2804 | const MCPhysReg FPR256_with_sub_16_in_FPR16C[] = { |
| 2805 | RISCV::F15_Q2, RISCV::F14_Q2, RISCV::F13_Q2, RISCV::F12_Q2, RISCV::F11_Q2, RISCV::F10_Q2, RISCV::F8_Q2, RISCV::F9_Q2, |
| 2806 | }; |
| 2807 | |
| 2808 | // FPR256_with_sub_16_in_FPR16C Bit set. |
| 2809 | const uint8_t FPR256_with_sub_16_in_FPR16CBits[] = { |
| 2810 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, |
| 2811 | }; |
| 2812 | |
| 2813 | // VRN5M1 Register Class... |
| 2814 | const MCPhysReg VRN5M1[] = { |
| 2815 | RISCV::V8_V9_V10_V11_V12, RISCV::V9_V10_V11_V12_V13, RISCV::V10_V11_V12_V13_V14, RISCV::V11_V12_V13_V14_V15, RISCV::V12_V13_V14_V15_V16, RISCV::V13_V14_V15_V16_V17, RISCV::V14_V15_V16_V17_V18, RISCV::V15_V16_V17_V18_V19, RISCV::V16_V17_V18_V19_V20, RISCV::V17_V18_V19_V20_V21, RISCV::V18_V19_V20_V21_V22, RISCV::V19_V20_V21_V22_V23, RISCV::V20_V21_V22_V23_V24, RISCV::V21_V22_V23_V24_V25, RISCV::V22_V23_V24_V25_V26, RISCV::V23_V24_V25_V26_V27, RISCV::V24_V25_V26_V27_V28, RISCV::V25_V26_V27_V28_V29, RISCV::V26_V27_V28_V29_V30, RISCV::V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5, RISCV::V2_V3_V4_V5_V6, RISCV::V3_V4_V5_V6_V7, RISCV::V4_V5_V6_V7_V8, RISCV::V5_V6_V7_V8_V9, RISCV::V6_V7_V8_V9_V10, RISCV::V7_V8_V9_V10_V11, RISCV::V0_V1_V2_V3_V4, |
| 2816 | }; |
| 2817 | |
| 2818 | // VRN5M1 Bit set. |
| 2819 | const uint8_t VRN5M1Bits[] = { |
| 2820 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x7f, |
| 2821 | }; |
| 2822 | |
| 2823 | // VRN5M1NoV0 Register Class... |
| 2824 | const MCPhysReg VRN5M1NoV0[] = { |
| 2825 | RISCV::V8_V9_V10_V11_V12, RISCV::V9_V10_V11_V12_V13, RISCV::V10_V11_V12_V13_V14, RISCV::V11_V12_V13_V14_V15, RISCV::V12_V13_V14_V15_V16, RISCV::V13_V14_V15_V16_V17, RISCV::V14_V15_V16_V17_V18, RISCV::V15_V16_V17_V18_V19, RISCV::V16_V17_V18_V19_V20, RISCV::V17_V18_V19_V20_V21, RISCV::V18_V19_V20_V21_V22, RISCV::V19_V20_V21_V22_V23, RISCV::V20_V21_V22_V23_V24, RISCV::V21_V22_V23_V24_V25, RISCV::V22_V23_V24_V25_V26, RISCV::V23_V24_V25_V26_V27, RISCV::V24_V25_V26_V27_V28, RISCV::V25_V26_V27_V28_V29, RISCV::V26_V27_V28_V29_V30, RISCV::V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5, RISCV::V2_V3_V4_V5_V6, RISCV::V3_V4_V5_V6_V7, RISCV::V4_V5_V6_V7_V8, RISCV::V5_V6_V7_V8_V9, RISCV::V6_V7_V8_V9_V10, RISCV::V7_V8_V9_V10_V11, |
| 2826 | }; |
| 2827 | |
| 2828 | // VRN5M1NoV0 Bit set. |
| 2829 | const uint8_t VRN5M1NoV0Bits[] = { |
| 2830 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x3f, |
| 2831 | }; |
| 2832 | |
| 2833 | // VRN5M1_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2834 | const MCPhysReg VRN5M1_with_sub_vrm1_0_in_VMV0[] = { |
| 2835 | RISCV::V0_V1_V2_V3_V4, |
| 2836 | }; |
| 2837 | |
| 2838 | // VRN5M1_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2839 | const uint8_t VRN5M1_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2840 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| 2841 | }; |
| 2842 | |
| 2843 | // VRN6M1 Register Class... |
| 2844 | const MCPhysReg VRN6M1[] = { |
| 2845 | RISCV::V8_V9_V10_V11_V12_V13, RISCV::V9_V10_V11_V12_V13_V14, RISCV::V10_V11_V12_V13_V14_V15, RISCV::V11_V12_V13_V14_V15_V16, RISCV::V12_V13_V14_V15_V16_V17, RISCV::V13_V14_V15_V16_V17_V18, RISCV::V14_V15_V16_V17_V18_V19, RISCV::V15_V16_V17_V18_V19_V20, RISCV::V16_V17_V18_V19_V20_V21, RISCV::V17_V18_V19_V20_V21_V22, RISCV::V18_V19_V20_V21_V22_V23, RISCV::V19_V20_V21_V22_V23_V24, RISCV::V20_V21_V22_V23_V24_V25, RISCV::V21_V22_V23_V24_V25_V26, RISCV::V22_V23_V24_V25_V26_V27, RISCV::V23_V24_V25_V26_V27_V28, RISCV::V24_V25_V26_V27_V28_V29, RISCV::V25_V26_V27_V28_V29_V30, RISCV::V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6, RISCV::V2_V3_V4_V5_V6_V7, RISCV::V3_V4_V5_V6_V7_V8, RISCV::V4_V5_V6_V7_V8_V9, RISCV::V5_V6_V7_V8_V9_V10, RISCV::V6_V7_V8_V9_V10_V11, RISCV::V7_V8_V9_V10_V11_V12, RISCV::V0_V1_V2_V3_V4_V5, |
| 2846 | }; |
| 2847 | |
| 2848 | // VRN6M1 Bit set. |
| 2849 | const uint8_t VRN6M1Bits[] = { |
| 2850 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x03, |
| 2851 | }; |
| 2852 | |
| 2853 | // VRN6M1NoV0 Register Class... |
| 2854 | const MCPhysReg VRN6M1NoV0[] = { |
| 2855 | RISCV::V8_V9_V10_V11_V12_V13, RISCV::V9_V10_V11_V12_V13_V14, RISCV::V10_V11_V12_V13_V14_V15, RISCV::V11_V12_V13_V14_V15_V16, RISCV::V12_V13_V14_V15_V16_V17, RISCV::V13_V14_V15_V16_V17_V18, RISCV::V14_V15_V16_V17_V18_V19, RISCV::V15_V16_V17_V18_V19_V20, RISCV::V16_V17_V18_V19_V20_V21, RISCV::V17_V18_V19_V20_V21_V22, RISCV::V18_V19_V20_V21_V22_V23, RISCV::V19_V20_V21_V22_V23_V24, RISCV::V20_V21_V22_V23_V24_V25, RISCV::V21_V22_V23_V24_V25_V26, RISCV::V22_V23_V24_V25_V26_V27, RISCV::V23_V24_V25_V26_V27_V28, RISCV::V24_V25_V26_V27_V28_V29, RISCV::V25_V26_V27_V28_V29_V30, RISCV::V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6, RISCV::V2_V3_V4_V5_V6_V7, RISCV::V3_V4_V5_V6_V7_V8, RISCV::V4_V5_V6_V7_V8_V9, RISCV::V5_V6_V7_V8_V9_V10, RISCV::V6_V7_V8_V9_V10_V11, RISCV::V7_V8_V9_V10_V11_V12, |
| 2856 | }; |
| 2857 | |
| 2858 | // VRN6M1NoV0 Bit set. |
| 2859 | const uint8_t VRN6M1NoV0Bits[] = { |
| 2860 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x01, |
| 2861 | }; |
| 2862 | |
| 2863 | // VRN3M2 Register Class... |
| 2864 | const MCPhysReg VRN3M2[] = { |
| 2865 | RISCV::V8M2_V10M2_V12M2, RISCV::V10M2_V12M2_V14M2, RISCV::V12M2_V14M2_V16M2, RISCV::V14M2_V16M2_V18M2, RISCV::V16M2_V18M2_V20M2, RISCV::V18M2_V20M2_V22M2, RISCV::V20M2_V22M2_V24M2, RISCV::V22M2_V24M2_V26M2, RISCV::V24M2_V26M2_V28M2, RISCV::V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2, RISCV::V4M2_V6M2_V8M2, RISCV::V6M2_V8M2_V10M2, RISCV::V0M2_V2M2_V4M2, |
| 2866 | }; |
| 2867 | |
| 2868 | // VRN3M2 Bit set. |
| 2869 | const uint8_t VRN3M2Bits[] = { |
| 2870 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, |
| 2871 | }; |
| 2872 | |
| 2873 | // VRN3M2NoV0 Register Class... |
| 2874 | const MCPhysReg VRN3M2NoV0[] = { |
| 2875 | RISCV::V8M2_V10M2_V12M2, RISCV::V10M2_V12M2_V14M2, RISCV::V12M2_V14M2_V16M2, RISCV::V14M2_V16M2_V18M2, RISCV::V16M2_V18M2_V20M2, RISCV::V18M2_V20M2_V22M2, RISCV::V20M2_V22M2_V24M2, RISCV::V22M2_V24M2_V26M2, RISCV::V24M2_V26M2_V28M2, RISCV::V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2, RISCV::V4M2_V6M2_V8M2, RISCV::V6M2_V8M2_V10M2, |
| 2876 | }; |
| 2877 | |
| 2878 | // VRN3M2NoV0 Bit set. |
| 2879 | const uint8_t VRN3M2NoV0Bits[] = { |
| 2880 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, |
| 2881 | }; |
| 2882 | |
| 2883 | // VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2884 | const MCPhysReg VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0[] = { |
| 2885 | RISCV::V0M2_V2M2_V4M2, |
| 2886 | }; |
| 2887 | |
| 2888 | // VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2889 | const uint8_t VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2890 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, |
| 2891 | }; |
| 2892 | |
| 2893 | // VRN6M1_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2894 | const MCPhysReg VRN6M1_with_sub_vrm1_0_in_VMV0[] = { |
| 2895 | RISCV::V0_V1_V2_V3_V4_V5, |
| 2896 | }; |
| 2897 | |
| 2898 | // VRN6M1_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2899 | const uint8_t VRN6M1_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2900 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, |
| 2901 | }; |
| 2902 | |
| 2903 | // VRN7M1 Register Class... |
| 2904 | const MCPhysReg VRN7M1[] = { |
| 2905 | RISCV::V8_V9_V10_V11_V12_V13_V14, RISCV::V9_V10_V11_V12_V13_V14_V15, RISCV::V10_V11_V12_V13_V14_V15_V16, RISCV::V11_V12_V13_V14_V15_V16_V17, RISCV::V12_V13_V14_V15_V16_V17_V18, RISCV::V13_V14_V15_V16_V17_V18_V19, RISCV::V14_V15_V16_V17_V18_V19_V20, RISCV::V15_V16_V17_V18_V19_V20_V21, RISCV::V16_V17_V18_V19_V20_V21_V22, RISCV::V17_V18_V19_V20_V21_V22_V23, RISCV::V18_V19_V20_V21_V22_V23_V24, RISCV::V19_V20_V21_V22_V23_V24_V25, RISCV::V20_V21_V22_V23_V24_V25_V26, RISCV::V21_V22_V23_V24_V25_V26_V27, RISCV::V22_V23_V24_V25_V26_V27_V28, RISCV::V23_V24_V25_V26_V27_V28_V29, RISCV::V24_V25_V26_V27_V28_V29_V30, RISCV::V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7, RISCV::V2_V3_V4_V5_V6_V7_V8, RISCV::V3_V4_V5_V6_V7_V8_V9, RISCV::V4_V5_V6_V7_V8_V9_V10, RISCV::V5_V6_V7_V8_V9_V10_V11, RISCV::V6_V7_V8_V9_V10_V11_V12, RISCV::V7_V8_V9_V10_V11_V12_V13, RISCV::V0_V1_V2_V3_V4_V5_V6, |
| 2906 | }; |
| 2907 | |
| 2908 | // VRN7M1 Bit set. |
| 2909 | const uint8_t VRN7M1Bits[] = { |
| 2910 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x0f, |
| 2911 | }; |
| 2912 | |
| 2913 | // VRN7M1NoV0 Register Class... |
| 2914 | const MCPhysReg VRN7M1NoV0[] = { |
| 2915 | RISCV::V8_V9_V10_V11_V12_V13_V14, RISCV::V9_V10_V11_V12_V13_V14_V15, RISCV::V10_V11_V12_V13_V14_V15_V16, RISCV::V11_V12_V13_V14_V15_V16_V17, RISCV::V12_V13_V14_V15_V16_V17_V18, RISCV::V13_V14_V15_V16_V17_V18_V19, RISCV::V14_V15_V16_V17_V18_V19_V20, RISCV::V15_V16_V17_V18_V19_V20_V21, RISCV::V16_V17_V18_V19_V20_V21_V22, RISCV::V17_V18_V19_V20_V21_V22_V23, RISCV::V18_V19_V20_V21_V22_V23_V24, RISCV::V19_V20_V21_V22_V23_V24_V25, RISCV::V20_V21_V22_V23_V24_V25_V26, RISCV::V21_V22_V23_V24_V25_V26_V27, RISCV::V22_V23_V24_V25_V26_V27_V28, RISCV::V23_V24_V25_V26_V27_V28_V29, RISCV::V24_V25_V26_V27_V28_V29_V30, RISCV::V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7, RISCV::V2_V3_V4_V5_V6_V7_V8, RISCV::V3_V4_V5_V6_V7_V8_V9, RISCV::V4_V5_V6_V7_V8_V9_V10, RISCV::V5_V6_V7_V8_V9_V10_V11, RISCV::V6_V7_V8_V9_V10_V11_V12, RISCV::V7_V8_V9_V10_V11_V12_V13, |
| 2916 | }; |
| 2917 | |
| 2918 | // VRN7M1NoV0 Bit set. |
| 2919 | const uint8_t VRN7M1NoV0Bits[] = { |
| 2920 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x07, |
| 2921 | }; |
| 2922 | |
| 2923 | // VRN7M1_with_sub_vrm1_0_in_VMV0 Register Class... |
| 2924 | const MCPhysReg VRN7M1_with_sub_vrm1_0_in_VMV0[] = { |
| 2925 | RISCV::V0_V1_V2_V3_V4_V5_V6, |
| 2926 | }; |
| 2927 | |
| 2928 | // VRN7M1_with_sub_vrm1_0_in_VMV0 Bit set. |
| 2929 | const uint8_t VRN7M1_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 2930 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, |
| 2931 | }; |
| 2932 | |
| 2933 | // VRN8M1 Register Class... |
| 2934 | const MCPhysReg VRN8M1[] = { |
| 2935 | RISCV::V8_V9_V10_V11_V12_V13_V14_V15, RISCV::V9_V10_V11_V12_V13_V14_V15_V16, RISCV::V10_V11_V12_V13_V14_V15_V16_V17, RISCV::V11_V12_V13_V14_V15_V16_V17_V18, RISCV::V12_V13_V14_V15_V16_V17_V18_V19, RISCV::V13_V14_V15_V16_V17_V18_V19_V20, RISCV::V14_V15_V16_V17_V18_V19_V20_V21, RISCV::V15_V16_V17_V18_V19_V20_V21_V22, RISCV::V16_V17_V18_V19_V20_V21_V22_V23, RISCV::V17_V18_V19_V20_V21_V22_V23_V24, RISCV::V18_V19_V20_V21_V22_V23_V24_V25, RISCV::V19_V20_V21_V22_V23_V24_V25_V26, RISCV::V20_V21_V22_V23_V24_V25_V26_V27, RISCV::V21_V22_V23_V24_V25_V26_V27_V28, RISCV::V22_V23_V24_V25_V26_V27_V28_V29, RISCV::V23_V24_V25_V26_V27_V28_V29_V30, RISCV::V24_V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7_V8, RISCV::V2_V3_V4_V5_V6_V7_V8_V9, RISCV::V3_V4_V5_V6_V7_V8_V9_V10, RISCV::V4_V5_V6_V7_V8_V9_V10_V11, RISCV::V5_V6_V7_V8_V9_V10_V11_V12, RISCV::V6_V7_V8_V9_V10_V11_V12_V13, RISCV::V7_V8_V9_V10_V11_V12_V13_V14, RISCV::V0_V1_V2_V3_V4_V5_V6_V7, |
| 2936 | }; |
| 2937 | |
| 2938 | // VRN8M1 Bit set. |
| 2939 | const uint8_t VRN8M1Bits[] = { |
| 2940 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0x1f, |
| 2941 | }; |
| 2942 | |
| 2943 | // VRN8M1NoV0 Register Class... |
| 2944 | const MCPhysReg VRN8M1NoV0[] = { |
| 2945 | RISCV::V8_V9_V10_V11_V12_V13_V14_V15, RISCV::V9_V10_V11_V12_V13_V14_V15_V16, RISCV::V10_V11_V12_V13_V14_V15_V16_V17, RISCV::V11_V12_V13_V14_V15_V16_V17_V18, RISCV::V12_V13_V14_V15_V16_V17_V18_V19, RISCV::V13_V14_V15_V16_V17_V18_V19_V20, RISCV::V14_V15_V16_V17_V18_V19_V20_V21, RISCV::V15_V16_V17_V18_V19_V20_V21_V22, RISCV::V16_V17_V18_V19_V20_V21_V22_V23, RISCV::V17_V18_V19_V20_V21_V22_V23_V24, RISCV::V18_V19_V20_V21_V22_V23_V24_V25, RISCV::V19_V20_V21_V22_V23_V24_V25_V26, RISCV::V20_V21_V22_V23_V24_V25_V26_V27, RISCV::V21_V22_V23_V24_V25_V26_V27_V28, RISCV::V22_V23_V24_V25_V26_V27_V28_V29, RISCV::V23_V24_V25_V26_V27_V28_V29_V30, RISCV::V24_V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7_V8, RISCV::V2_V3_V4_V5_V6_V7_V8_V9, RISCV::V3_V4_V5_V6_V7_V8_V9_V10, RISCV::V4_V5_V6_V7_V8_V9_V10_V11, RISCV::V5_V6_V7_V8_V9_V10_V11_V12, RISCV::V6_V7_V8_V9_V10_V11_V12_V13, RISCV::V7_V8_V9_V10_V11_V12_V13_V14, |
| 2946 | }; |
| 2947 | |
| 2948 | // VRN8M1NoV0 Bit set. |
| 2949 | const uint8_t VRN8M1NoV0Bits[] = { |
| 2950 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0x0f, |
| 2951 | }; |
| 2952 | |
| 2953 | // VRN4M2 Register Class... |
| 2954 | const MCPhysReg VRN4M2[] = { |
| 2955 | RISCV::V8M2_V10M2_V12M2_V14M2, RISCV::V10M2_V12M2_V14M2_V16M2, RISCV::V12M2_V14M2_V16M2_V18M2, RISCV::V14M2_V16M2_V18M2_V20M2, RISCV::V16M2_V18M2_V20M2_V22M2, RISCV::V18M2_V20M2_V22M2_V24M2, RISCV::V20M2_V22M2_V24M2_V26M2, RISCV::V22M2_V24M2_V26M2_V28M2, RISCV::V24M2_V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2_V8M2, RISCV::V4M2_V6M2_V8M2_V10M2, RISCV::V6M2_V8M2_V10M2_V12M2, RISCV::V0M2_V2M2_V4M2_V6M2, |
| 2956 | }; |
| 2957 | |
| 2958 | // VRN4M2 Bit set. |
| 2959 | const uint8_t VRN4M2Bits[] = { |
| 2960 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, |
| 2961 | }; |
| 2962 | |
| 2963 | // VRN4M2NoV0 Register Class... |
| 2964 | const MCPhysReg VRN4M2NoV0[] = { |
| 2965 | RISCV::V8M2_V10M2_V12M2_V14M2, RISCV::V10M2_V12M2_V14M2_V16M2, RISCV::V12M2_V14M2_V16M2_V18M2, RISCV::V14M2_V16M2_V18M2_V20M2, RISCV::V16M2_V18M2_V20M2_V22M2, RISCV::V18M2_V20M2_V22M2_V24M2, RISCV::V20M2_V22M2_V24M2_V26M2, RISCV::V22M2_V24M2_V26M2_V28M2, RISCV::V24M2_V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2_V8M2, RISCV::V4M2_V6M2_V8M2_V10M2, RISCV::V6M2_V8M2_V10M2_V12M2, |
| 2966 | }; |
| 2967 | |
| 2968 | // VRN4M2NoV0 Bit set. |
| 2969 | const uint8_t VRN4M2NoV0Bits[] = { |
| 2970 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, |
| 2971 | }; |
| 2972 | |
| 2973 | // VRN2M4 Register Class... |
| 2974 | const MCPhysReg VRN2M4[] = { |
| 2975 | RISCV::V8M4_V12M4, RISCV::V12M4_V16M4, RISCV::V16M4_V20M4, RISCV::V20M4_V24M4, RISCV::V24M4_V28M4, RISCV::V4M4_V8M4, RISCV::V0M4_V4M4, |
| 2976 | }; |
| 2977 | |
| 2978 | // VRN2M4 Bit set. |
| 2979 | const uint8_t VRN2M4Bits[] = { |
| 2980 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, |
| 2981 | }; |
| 2982 | |
| 2983 | // VRN2M4NoV0 Register Class... |
| 2984 | const MCPhysReg VRN2M4NoV0[] = { |
| 2985 | RISCV::V8M4_V12M4, RISCV::V12M4_V16M4, RISCV::V16M4_V20M4, RISCV::V20M4_V24M4, RISCV::V24M4_V28M4, RISCV::V4M4_V8M4, |
| 2986 | }; |
| 2987 | |
| 2988 | // VRN2M4NoV0 Bit set. |
| 2989 | const uint8_t VRN2M4NoV0Bits[] = { |
| 2990 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, |
| 2991 | }; |
| 2992 | |
| 2993 | // VRM8 Register Class... |
| 2994 | const MCPhysReg VRM8[] = { |
| 2995 | RISCV::V8M8, RISCV::V16M8, RISCV::V24M8, RISCV::V0M8, |
| 2996 | }; |
| 2997 | |
| 2998 | // VRM8 Bit set. |
| 2999 | const uint8_t VRM8Bits[] = { |
| 3000 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0x20, 0x10, |
| 3001 | }; |
| 3002 | |
| 3003 | // VRM8NoV0 Register Class... |
| 3004 | const MCPhysReg VRM8NoV0[] = { |
| 3005 | RISCV::V8M8, RISCV::V16M8, RISCV::V24M8, |
| 3006 | }; |
| 3007 | |
| 3008 | // VRM8NoV0 Bit set. |
| 3009 | const uint8_t VRM8NoV0Bits[] = { |
| 3010 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x20, 0x10, |
| 3011 | }; |
| 3012 | |
| 3013 | // VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0 Register Class... |
| 3014 | const MCPhysReg VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0[] = { |
| 3015 | RISCV::V0M8, |
| 3016 | }; |
| 3017 | |
| 3018 | // VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0 Bit set. |
| 3019 | const uint8_t VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 3020 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, |
| 3021 | }; |
| 3022 | |
| 3023 | // VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0 Register Class... |
| 3024 | const MCPhysReg VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0[] = { |
| 3025 | RISCV::V0M4_V4M4, |
| 3026 | }; |
| 3027 | |
| 3028 | // VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0 Bit set. |
| 3029 | const uint8_t VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 3030 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 3031 | }; |
| 3032 | |
| 3033 | // VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 Register Class... |
| 3034 | const MCPhysReg VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0[] = { |
| 3035 | RISCV::V0M2_V2M2_V4M2_V6M2, |
| 3036 | }; |
| 3037 | |
| 3038 | // VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0 Bit set. |
| 3039 | const uint8_t VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 3040 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, |
| 3041 | }; |
| 3042 | |
| 3043 | // VRN8M1_with_sub_vrm1_0_in_VMV0 Register Class... |
| 3044 | const MCPhysReg VRN8M1_with_sub_vrm1_0_in_VMV0[] = { |
| 3045 | RISCV::V0_V1_V2_V3_V4_V5_V6_V7, |
| 3046 | }; |
| 3047 | |
| 3048 | // VRN8M1_with_sub_vrm1_0_in_VMV0 Bit set. |
| 3049 | const uint8_t VRN8M1_with_sub_vrm1_0_in_VMV0Bits[] = { |
| 3050 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 3051 | }; |
| 3052 | |
| 3053 | } // end anonymous namespace |
| 3054 | |
| 3055 | |
| 3056 | #ifdef __GNUC__ |
| 3057 | #pragma GCC diagnostic push |
| 3058 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 3059 | #endif |
| 3060 | extern const char RISCVRegClassStrings[] = { |
| 3061 | /* 0 */ "MR0\000" |
| 3062 | /* 4 */ "VRN2M1_with_sub_vrm1_0_in_VMV0\000" |
| 3063 | /* 35 */ "VRN3M1_with_sub_vrm1_0_in_VMV0\000" |
| 3064 | /* 66 */ "VRN4M1_with_sub_vrm1_0_in_VMV0\000" |
| 3065 | /* 97 */ "VRN5M1_with_sub_vrm1_0_in_VMV0\000" |
| 3066 | /* 128 */ "VRN6M1_with_sub_vrm1_0_in_VMV0\000" |
| 3067 | /* 159 */ "VRN7M1_with_sub_vrm1_0_in_VMV0\000" |
| 3068 | /* 190 */ "VRN8M1_with_sub_vrm1_0_in_VMV0\000" |
| 3069 | /* 221 */ "VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0\000" |
| 3070 | /* 276 */ "VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0\000" |
| 3071 | /* 331 */ "VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0\000" |
| 3072 | /* 386 */ "VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0\000" |
| 3073 | /* 441 */ "VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0\000" |
| 3074 | /* 494 */ "VRN2M1NoV0\000" |
| 3075 | /* 505 */ "VRN3M1NoV0\000" |
| 3076 | /* 516 */ "VRN4M1NoV0\000" |
| 3077 | /* 527 */ "VRN5M1NoV0\000" |
| 3078 | /* 538 */ "VRN6M1NoV0\000" |
| 3079 | /* 549 */ "VRN7M1NoV0\000" |
| 3080 | /* 560 */ "VRN8M1NoV0\000" |
| 3081 | /* 571 */ "ZZZ_VRMF2NoV0\000" |
| 3082 | /* 585 */ "VRN2M2NoV0\000" |
| 3083 | /* 596 */ "VRN3M2NoV0\000" |
| 3084 | /* 607 */ "VRN4M2NoV0\000" |
| 3085 | /* 618 */ "VRM2NoV0\000" |
| 3086 | /* 627 */ "ZZZ_VRMF4NoV0\000" |
| 3087 | /* 641 */ "VRN2M4NoV0\000" |
| 3088 | /* 652 */ "VRM4NoV0\000" |
| 3089 | /* 661 */ "ZZZ_VRMF8NoV0\000" |
| 3090 | /* 675 */ "VRM8NoV0\000" |
| 3091 | /* 684 */ "ZZZ_VMNoV0\000" |
| 3092 | /* 695 */ "VRNoV0\000" |
| 3093 | /* 702 */ "GPRPair_with_sub_gpr_even_in_GPRX0\000" |
| 3094 | /* 737 */ "YGPR_with_sub_cap_addr_in_GPRX0\000" |
| 3095 | /* 769 */ "GPRF32NoX0\000" |
| 3096 | /* 780 */ "YGPR_with_sub_16_in_GPRF16NoX0\000" |
| 3097 | /* 811 */ "GPRNoX0\000" |
| 3098 | /* 819 */ "GPRPairNoX0\000" |
| 3099 | /* 831 */ "YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31\000" |
| 3100 | /* 878 */ "YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31\000" |
| 3101 | /* 927 */ "YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31\000" |
| 3102 | /* 974 */ "GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31\000" |
| 3103 | /* 1028 */ "YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31\000" |
| 3104 | /* 1080 */ "GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31\000" |
| 3105 | /* 1129 */ "YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31\000" |
| 3106 | /* 1176 */ "GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31\000" |
| 3107 | /* 1256 */ "YGPR_with_sub_cap_addr_in_GPRNoX31\000" |
| 3108 | /* 1291 */ "VRN2M1\000" |
| 3109 | /* 1298 */ "VRN3M1\000" |
| 3110 | /* 1305 */ "VRN4M1\000" |
| 3111 | /* 1312 */ "VRN5M1\000" |
| 3112 | /* 1319 */ "VRN6M1\000" |
| 3113 | /* 1326 */ "VRN7M1\000" |
| 3114 | /* 1333 */ "VRN8M1\000" |
| 3115 | /* 1340 */ "YGPR_with_sub_cap_addr_in_GPRX1\000" |
| 3116 | /* 1372 */ "GPRF32\000" |
| 3117 | /* 1379 */ "FPR32\000" |
| 3118 | /* 1385 */ "ZZZ_VRMF2\000" |
| 3119 | /* 1395 */ "VRN2M2\000" |
| 3120 | /* 1402 */ "VRN3M2\000" |
| 3121 | /* 1409 */ "VRN4M2\000" |
| 3122 | /* 1416 */ "TRM2\000" |
| 3123 | /* 1421 */ "VRM2\000" |
| 3124 | /* 1426 */ "GPRPair_with_sub_gpr_even_in_GPRNoX0X2\000" |
| 3125 | /* 1465 */ "YGPR_with_sub_cap_addr_in_GPRNoX0X2\000" |
| 3126 | /* 1501 */ "GPRPair_with_sub_gpr_even_in_GPRNoX2\000" |
| 3127 | /* 1538 */ "YGPR_with_sub_cap_addr_in_GPRNoX2\000" |
| 3128 | /* 1572 */ "FPR64\000" |
| 3129 | /* 1578 */ "ZZZ_VRMF4\000" |
| 3130 | /* 1588 */ "VRN2M4\000" |
| 3131 | /* 1595 */ "TRM4\000" |
| 3132 | /* 1600 */ "VRM4\000" |
| 3133 | /* 1605 */ "anonymous_15375\000" |
| 3134 | /* 1621 */ "GPRPair_with_sub_gpr_odd_in_GPRX1X5\000" |
| 3135 | /* 1657 */ "YGPR_with_sub_cap_addr_in_GPRX1X5\000" |
| 3136 | /* 1691 */ "YGPR_with_sub_cap_addr_in_GPRX5\000" |
| 3137 | /* 1723 */ "GPRF16\000" |
| 3138 | /* 1730 */ "FPR16\000" |
| 3139 | /* 1736 */ "FPR256\000" |
| 3140 | /* 1743 */ "GPRPair_with_sub_gpr_even_in_GPRC_and_SR07\000" |
| 3141 | /* 1786 */ "YGPR_with_sub_cap_addr_in_GPRC_and_SR07\000" |
| 3142 | /* 1826 */ "GPRPair_with_sub_gpr_even_in_SR07\000" |
| 3143 | /* 1860 */ "YGPR_with_sub_cap_addr_in_SR07\000" |
| 3144 | /* 1891 */ "GPRPair_with_sub_gpr_odd_in_GPRX7\000" |
| 3145 | /* 1925 */ "YGPR_with_sub_cap_addr_in_GPRX7\000" |
| 3146 | /* 1957 */ "GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7\000" |
| 3147 | /* 2009 */ "YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7\000" |
| 3148 | /* 2059 */ "GPRPair_with_sub_gpr_odd_in_GPRTCNonX7\000" |
| 3149 | /* 2098 */ "YGPR_with_sub_cap_addr_in_GPRTCNonX7\000" |
| 3150 | /* 2135 */ "GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7\000" |
| 3151 | /* 2176 */ "YGPR_with_sub_cap_addr_in_GPRJALRNonX7\000" |
| 3152 | /* 2215 */ "FPR128\000" |
| 3153 | /* 2222 */ "ZZZ_VRMF8\000" |
| 3154 | /* 2232 */ "VRM8\000" |
| 3155 | /* 2237 */ "GPRF32C\000" |
| 3156 | /* 2245 */ "FPR32C\000" |
| 3157 | /* 2252 */ "FPR64C\000" |
| 3158 | /* 2259 */ "YGPR_with_sub_16_in_GPRF16C\000" |
| 3159 | /* 2287 */ "FPR256_with_sub_16_in_FPR16C\000" |
| 3160 | /* 2316 */ "FPR128_with_sub_16_in_FPR16C\000" |
| 3161 | /* 2345 */ "GPRC\000" |
| 3162 | /* 2350 */ "GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTC\000" |
| 3163 | /* 2397 */ "YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTC\000" |
| 3164 | /* 2442 */ "GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC\000" |
| 3165 | /* 2486 */ "YGPR_with_sub_cap_addr_in_GPRC_and_GPRTC\000" |
| 3166 | /* 2527 */ "GPRPair_with_sub_gpr_even_in_GPRTC\000" |
| 3167 | /* 2562 */ "YGPR_with_sub_cap_addr_in_GPRTC\000" |
| 3168 | /* 2594 */ "GPRPairC\000" |
| 3169 | /* 2603 */ "ZZZ_VM\000" |
| 3170 | /* 2610 */ "GPRPair_with_sub_gpr_even_in_SP\000" |
| 3171 | /* 2642 */ "YGPR_with_sub_cap_addr_in_SP\000" |
| 3172 | /* 2671 */ "GPRPair_with_sub_gpr_even_in_GPRJALR\000" |
| 3173 | /* 2708 */ "YGPR_with_sub_cap_addr_in_GPRJALR\000" |
| 3174 | /* 2742 */ "MR\000" |
| 3175 | /* 2745 */ "YGPR\000" |
| 3176 | /* 2750 */ "VCSR\000" |
| 3177 | /* 2755 */ "TR\000" |
| 3178 | /* 2758 */ "VR\000" |
| 3179 | /* 2761 */ "GPRAll\000" |
| 3180 | /* 2768 */ "GPRPair\000" |
| 3181 | }; |
| 3182 | #ifdef __GNUC__ |
| 3183 | #pragma GCC diagnostic pop |
| 3184 | #endif |
| 3185 | |
| 3186 | extern const MCRegisterClass RISCVMCRegisterClasses[] = { |
| 3187 | { .RegsBegin: MR, .RegSet: MRBits, .NameIdx: 2742, .RegsSize: 8, .RegSetSize: sizeof(MRBits), .ID: RISCV::MRRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3188 | { .RegsBegin: MR0, .RegSet: MR0Bits, .NameIdx: 0, .RegsSize: 1, .RegSetSize: sizeof(MR0Bits), .ID: RISCV::MR0RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3189 | { .RegsBegin: FPR16, .RegSet: FPR16Bits, .NameIdx: 1730, .RegsSize: 32, .RegSetSize: sizeof(FPR16Bits), .ID: RISCV::FPR16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3190 | { .RegsBegin: GPRF16, .RegSet: GPRF16Bits, .NameIdx: 1723, .RegsSize: 32, .RegSetSize: sizeof(GPRF16Bits), .ID: RISCV::GPRF16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3191 | { .RegsBegin: GPRF16NoX0, .RegSet: GPRF16NoX0Bits, .NameIdx: 800, .RegsSize: 31, .RegSetSize: sizeof(GPRF16NoX0Bits), .ID: RISCV::GPRF16NoX0RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3192 | { .RegsBegin: FPR16C, .RegSet: FPR16CBits, .NameIdx: 2309, .RegsSize: 8, .RegSetSize: sizeof(FPR16CBits), .ID: RISCV::FPR16CRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3193 | { .RegsBegin: GPRF16C, .RegSet: GPRF16CBits, .NameIdx: 2279, .RegsSize: 8, .RegSetSize: sizeof(GPRF16CBits), .ID: RISCV::GPRF16CRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3194 | { .RegsBegin: GPRAll, .RegSet: GPRAllBits, .NameIdx: 2761, .RegsSize: 33, .RegSetSize: sizeof(GPRAllBits), .ID: RISCV::GPRAllRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3195 | { .RegsBegin: FPR32, .RegSet: FPR32Bits, .NameIdx: 1379, .RegsSize: 32, .RegSetSize: sizeof(FPR32Bits), .ID: RISCV::FPR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3196 | { .RegsBegin: GPR, .RegSet: GPRBits, .NameIdx: 2746, .RegsSize: 32, .RegSetSize: sizeof(GPRBits), .ID: RISCV::GPRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3197 | { .RegsBegin: GPRF32, .RegSet: GPRF32Bits, .NameIdx: 1372, .RegsSize: 32, .RegSetSize: sizeof(GPRF32Bits), .ID: RISCV::GPRF32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3198 | { .RegsBegin: GPRF32NoX0, .RegSet: GPRF32NoX0Bits, .NameIdx: 769, .RegsSize: 31, .RegSetSize: sizeof(GPRF32NoX0Bits), .ID: RISCV::GPRF32NoX0RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3199 | { .RegsBegin: GPRNoX0, .RegSet: GPRNoX0Bits, .NameIdx: 811, .RegsSize: 31, .RegSetSize: sizeof(GPRNoX0Bits), .ID: RISCV::GPRNoX0RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3200 | { .RegsBegin: GPRNoX2, .RegSet: GPRNoX2Bits, .NameIdx: 1530, .RegsSize: 31, .RegSetSize: sizeof(GPRNoX2Bits), .ID: RISCV::GPRNoX2RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3201 | { .RegsBegin: GPRNoX31, .RegSet: GPRNoX31Bits, .NameIdx: 869, .RegsSize: 31, .RegSetSize: sizeof(GPRNoX31Bits), .ID: RISCV::GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3202 | { .RegsBegin: GPRNoX0X2, .RegSet: GPRNoX0X2Bits, .NameIdx: 1455, .RegsSize: 30, .RegSetSize: sizeof(GPRNoX0X2Bits), .ID: RISCV::GPRNoX0X2RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3203 | { .RegsBegin: GPRNoX0_and_GPRNoX31, .RegSet: GPRNoX0_and_GPRNoX31Bits, .NameIdx: 857, .RegsSize: 30, .RegSetSize: sizeof(GPRNoX0_and_GPRNoX31Bits), .ID: RISCV::GPRNoX0_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3204 | { .RegsBegin: GPRNoX2_and_GPRNoX31, .RegSet: GPRNoX2_and_GPRNoX31Bits, .NameIdx: 953, .RegsSize: 30, .RegSetSize: sizeof(GPRNoX2_and_GPRNoX31Bits), .ID: RISCV::GPRNoX2_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3205 | { .RegsBegin: GPRNoX0X2_and_GPRNoX31, .RegSet: GPRNoX0X2_and_GPRNoX31Bits, .NameIdx: 904, .RegsSize: 29, .RegSetSize: sizeof(GPRNoX0X2_and_GPRNoX31Bits), .ID: RISCV::GPRNoX0X2_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3206 | { .RegsBegin: GPRJALR, .RegSet: GPRJALRBits, .NameIdx: 2700, .RegsSize: 26, .RegSetSize: sizeof(GPRJALRBits), .ID: RISCV::GPRJALRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3207 | { .RegsBegin: GPRJALRNonX7, .RegSet: GPRJALRNonX7Bits, .NameIdx: 2163, .RegsSize: 25, .RegSetSize: sizeof(GPRJALRNonX7Bits), .ID: RISCV::GPRJALRNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3208 | { .RegsBegin: GPRJALR_and_GPRNoX31, .RegSet: GPRJALR_and_GPRNoX31Bits, .NameIdx: 1108, .RegsSize: 25, .RegSetSize: sizeof(GPRJALR_and_GPRNoX31Bits), .ID: RISCV::GPRJALR_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3209 | { .RegsBegin: GPRJALRNonX7_and_GPRNoX31, .RegSet: GPRJALRNonX7_and_GPRNoX31Bits, .NameIdx: 1002, .RegsSize: 24, .RegSetSize: sizeof(GPRJALRNonX7_and_GPRNoX31Bits), .ID: RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3210 | { .RegsBegin: TR, .RegSet: TRBits, .NameIdx: 2755, .RegsSize: 16, .RegSetSize: sizeof(TRBits), .ID: RISCV::TRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3211 | { .RegsBegin: GPRTC, .RegSet: GPRTCBits, .NameIdx: 2391, .RegsSize: 14, .RegSetSize: sizeof(GPRTCBits), .ID: RISCV::GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3212 | { .RegsBegin: GPRNoX31_and_GPRTC, .RegSet: GPRNoX31_and_GPRTCBits, .NameIdx: 2378, .RegsSize: 13, .RegSetSize: sizeof(GPRNoX31_and_GPRTCBits), .ID: RISCV::GPRNoX31_and_GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3213 | { .RegsBegin: GPRTCNonX7, .RegSet: GPRTCNonX7Bits, .NameIdx: 1998, .RegsSize: 13, .RegSetSize: sizeof(GPRTCNonX7Bits), .ID: RISCV::GPRTCNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3214 | { .RegsBegin: GPRNoX31_and_GPRTCNonX7, .RegSet: GPRNoX31_and_GPRTCNonX7Bits, .NameIdx: 1985, .RegsSize: 12, .RegSetSize: sizeof(GPRNoX31_and_GPRTCNonX7Bits), .ID: RISCV::GPRNoX31_and_GPRTCNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3215 | { .RegsBegin: FPR32C, .RegSet: FPR32CBits, .NameIdx: 2245, .RegsSize: 8, .RegSetSize: sizeof(FPR32CBits), .ID: RISCV::FPR32CRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3216 | { .RegsBegin: GPRC, .RegSet: GPRCBits, .NameIdx: 2345, .RegsSize: 8, .RegSetSize: sizeof(GPRCBits), .ID: RISCV::GPRCRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3217 | { .RegsBegin: GPRF32C, .RegSet: GPRF32CBits, .NameIdx: 2237, .RegsSize: 8, .RegSetSize: sizeof(GPRF32CBits), .ID: RISCV::GPRF32CRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3218 | { .RegsBegin: SR07, .RegSet: SR07Bits, .NameIdx: 1781, .RegsSize: 8, .RegSetSize: sizeof(SR07Bits), .ID: RISCV::SR07RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3219 | { .RegsBegin: TRM2, .RegSet: TRM2Bits, .NameIdx: 1416, .RegsSize: 8, .RegSetSize: sizeof(TRM2Bits), .ID: RISCV::TRM2RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3220 | { .RegsBegin: GPRC_and_GPRTC, .RegSet: GPRC_and_GPRTCBits, .NameIdx: 2471, .RegsSize: 6, .RegSetSize: sizeof(GPRC_and_GPRTCBits), .ID: RISCV::GPRC_and_GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3221 | { .RegsBegin: TRM4, .RegSet: TRM4Bits, .NameIdx: 1595, .RegsSize: 4, .RegSetSize: sizeof(TRM4Bits), .ID: RISCV::TRM4RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3222 | { .RegsBegin: VCSR, .RegSet: VCSRBits, .NameIdx: 2750, .RegsSize: 3, .RegSetSize: sizeof(VCSRBits), .ID: RISCV::VCSRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: false, .BaseClass: false }, |
| 3223 | { .RegsBegin: GPRC_and_SR07, .RegSet: GPRC_and_SR07Bits, .NameIdx: 1772, .RegsSize: 2, .RegSetSize: sizeof(GPRC_and_SR07Bits), .ID: RISCV::GPRC_and_SR07RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3224 | { .RegsBegin: GPRX1X5, .RegSet: GPRX1X5Bits, .NameIdx: 1649, .RegsSize: 2, .RegSetSize: sizeof(GPRX1X5Bits), .ID: RISCV::GPRX1X5RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3225 | { .RegsBegin: GPRX0, .RegSet: GPRX0Bits, .NameIdx: 731, .RegsSize: 1, .RegSetSize: sizeof(GPRX0Bits), .ID: RISCV::GPRX0RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3226 | { .RegsBegin: GPRX1, .RegSet: GPRX1Bits, .NameIdx: 1366, .RegsSize: 1, .RegSetSize: sizeof(GPRX1Bits), .ID: RISCV::GPRX1RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3227 | { .RegsBegin: GPRX5, .RegSet: GPRX5Bits, .NameIdx: 1717, .RegsSize: 1, .RegSetSize: sizeof(GPRX5Bits), .ID: RISCV::GPRX5RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3228 | { .RegsBegin: GPRX7, .RegSet: GPRX7Bits, .NameIdx: 1919, .RegsSize: 1, .RegSetSize: sizeof(GPRX7Bits), .ID: RISCV::GPRX7RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3229 | { .RegsBegin: SP, .RegSet: SPBits, .NameIdx: 2639, .RegsSize: 1, .RegSetSize: sizeof(SPBits), .ID: RISCV::SPRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3230 | { .RegsBegin: anonymous_15375, .RegSet: anonymous_15375Bits, .NameIdx: 1605, .RegsSize: 1, .RegSetSize: sizeof(anonymous_15375Bits), .ID: RISCV::anonymous_15375RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: false, .BaseClass: false }, |
| 3231 | { .RegsBegin: GPRPair, .RegSet: GPRPairBits, .NameIdx: 2768, .RegsSize: 16, .RegSetSize: sizeof(GPRPairBits), .ID: RISCV::GPRPairRegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3232 | { .RegsBegin: GPRPairNoX0, .RegSet: GPRPairNoX0Bits, .NameIdx: 819, .RegsSize: 15, .RegSetSize: sizeof(GPRPairNoX0Bits), .ID: RISCV::GPRPairNoX0RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3233 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_GPRNoX2, .RegSet: GPRPair_with_sub_gpr_even_in_GPRNoX2Bits, .NameIdx: 1501, .RegsSize: 15, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_GPRNoX2Bits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX2RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3234 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_GPRNoX0X2, .RegSet: GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits, .NameIdx: 1426, .RegsSize: 14, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3235 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRNoX31, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRNoX31Bits, .NameIdx: 1219, .RegsSize: 14, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRNoX31Bits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3236 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_GPRJALR, .RegSet: GPRPair_with_sub_gpr_even_in_GPRJALRBits, .NameIdx: 2671, .RegsSize: 13, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_GPRJALRBits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3237 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31, .RegSet: GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31Bits, .NameIdx: 1176, .RegsSize: 13, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31Bits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2_and_GPRPair_with_sub_gpr_odd_in_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3238 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7Bits, .NameIdx: 2135, .RegsSize: 12, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7Bits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3239 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31Bits, .NameIdx: 1080, .RegsSize: 12, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31Bits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALR_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3240 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31Bits, .NameIdx: 974, .RegsSize: 11, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31Bits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRJALRNonX7_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3241 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_GPRTC, .RegSet: GPRPair_with_sub_gpr_even_in_GPRTCBits, .NameIdx: 2527, .RegsSize: 7, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_GPRTCBits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3242 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTC, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCBits, .NameIdx: 2350, .RegsSize: 6, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCBits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3243 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRTCNonX7, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRTCNonX7Bits, .NameIdx: 2059, .RegsSize: 6, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRTCNonX7Bits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRTCNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3244 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7Bits, .NameIdx: 1957, .RegsSize: 5, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7Bits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRNoX31_and_GPRTCNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3245 | { .RegsBegin: GPRPairC, .RegSet: GPRPairCBits, .NameIdx: 2594, .RegsSize: 4, .RegSetSize: sizeof(GPRPairCBits), .ID: RISCV::GPRPairCRegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3246 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_SR07, .RegSet: GPRPair_with_sub_gpr_even_in_SR07Bits, .NameIdx: 1826, .RegsSize: 4, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_SR07Bits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_SR07RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3247 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC, .RegSet: GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits, .NameIdx: 2442, .RegsSize: 3, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3248 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_GPRC_and_SR07, .RegSet: GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits, .NameIdx: 1743, .RegsSize: 1, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3249 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_GPRX0, .RegSet: GPRPair_with_sub_gpr_even_in_GPRX0Bits, .NameIdx: 702, .RegsSize: 1, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_GPRX0Bits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_GPRX0RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3250 | { .RegsBegin: GPRPair_with_sub_gpr_even_in_SP, .RegSet: GPRPair_with_sub_gpr_even_in_SPBits, .NameIdx: 2610, .RegsSize: 1, .RegSetSize: sizeof(GPRPair_with_sub_gpr_even_in_SPBits), .ID: RISCV::GPRPair_with_sub_gpr_even_in_SPRegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3251 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRX1X5, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits, .NameIdx: 1621, .RegsSize: 1, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3252 | { .RegsBegin: GPRPair_with_sub_gpr_odd_in_GPRX7, .RegSet: GPRPair_with_sub_gpr_odd_in_GPRX7Bits, .NameIdx: 1891, .RegsSize: 1, .RegSetSize: sizeof(GPRPair_with_sub_gpr_odd_in_GPRX7Bits), .ID: RISCV::GPRPair_with_sub_gpr_odd_in_GPRX7RegClassID, .RegSizeInBits: 0, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3253 | { .RegsBegin: FPR64, .RegSet: FPR64Bits, .NameIdx: 1572, .RegsSize: 32, .RegSetSize: sizeof(FPR64Bits), .ID: RISCV::FPR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3254 | { .RegsBegin: VR, .RegSet: VRBits, .NameIdx: 2758, .RegsSize: 32, .RegSetSize: sizeof(VRBits), .ID: RISCV::VRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3255 | { .RegsBegin: YGPR, .RegSet: YGPRBits, .NameIdx: 2745, .RegsSize: 32, .RegSetSize: sizeof(YGPRBits), .ID: RISCV::YGPRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3256 | { .RegsBegin: ZZZ_VM, .RegSet: ZZZ_VMBits, .NameIdx: 2603, .RegsSize: 32, .RegSetSize: sizeof(ZZZ_VMBits), .ID: RISCV::ZZZ_VMRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3257 | { .RegsBegin: ZZZ_VRMF2, .RegSet: ZZZ_VRMF2Bits, .NameIdx: 1385, .RegsSize: 32, .RegSetSize: sizeof(ZZZ_VRMF2Bits), .ID: RISCV::ZZZ_VRMF2RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3258 | { .RegsBegin: ZZZ_VRMF4, .RegSet: ZZZ_VRMF4Bits, .NameIdx: 1578, .RegsSize: 32, .RegSetSize: sizeof(ZZZ_VRMF4Bits), .ID: RISCV::ZZZ_VRMF4RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3259 | { .RegsBegin: ZZZ_VRMF8, .RegSet: ZZZ_VRMF8Bits, .NameIdx: 2222, .RegsSize: 32, .RegSetSize: sizeof(ZZZ_VRMF8Bits), .ID: RISCV::ZZZ_VRMF8RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3260 | { .RegsBegin: VRNoV0, .RegSet: VRNoV0Bits, .NameIdx: 695, .RegsSize: 31, .RegSetSize: sizeof(VRNoV0Bits), .ID: RISCV::VRNoV0RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3261 | { .RegsBegin: YGPR_with_sub_16_in_GPRF16NoX0, .RegSet: YGPR_with_sub_16_in_GPRF16NoX0Bits, .NameIdx: 780, .RegsSize: 31, .RegSetSize: sizeof(YGPR_with_sub_16_in_GPRF16NoX0Bits), .ID: RISCV::YGPR_with_sub_16_in_GPRF16NoX0RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3262 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRNoX2, .RegSet: YGPR_with_sub_cap_addr_in_GPRNoX2Bits, .NameIdx: 1538, .RegsSize: 31, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRNoX2Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3263 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRNoX31, .RegSet: YGPR_with_sub_cap_addr_in_GPRNoX31Bits, .NameIdx: 1256, .RegsSize: 31, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRNoX31Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3264 | { .RegsBegin: ZZZ_VMNoV0, .RegSet: ZZZ_VMNoV0Bits, .NameIdx: 684, .RegsSize: 31, .RegSetSize: sizeof(ZZZ_VMNoV0Bits), .ID: RISCV::ZZZ_VMNoV0RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3265 | { .RegsBegin: ZZZ_VRMF2NoV0, .RegSet: ZZZ_VRMF2NoV0Bits, .NameIdx: 571, .RegsSize: 31, .RegSetSize: sizeof(ZZZ_VRMF2NoV0Bits), .ID: RISCV::ZZZ_VRMF2NoV0RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3266 | { .RegsBegin: ZZZ_VRMF4NoV0, .RegSet: ZZZ_VRMF4NoV0Bits, .NameIdx: 627, .RegsSize: 31, .RegSetSize: sizeof(ZZZ_VRMF4NoV0Bits), .ID: RISCV::ZZZ_VRMF4NoV0RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3267 | { .RegsBegin: ZZZ_VRMF8NoV0, .RegSet: ZZZ_VRMF8NoV0Bits, .NameIdx: 661, .RegsSize: 31, .RegSetSize: sizeof(ZZZ_VRMF8NoV0Bits), .ID: RISCV::ZZZ_VRMF8NoV0RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3268 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRNoX0X2, .RegSet: YGPR_with_sub_cap_addr_in_GPRNoX0X2Bits, .NameIdx: 1465, .RegsSize: 30, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRNoX0X2Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3269 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31, .RegSet: YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31Bits, .NameIdx: 831, .RegsSize: 30, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3270 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31, .RegSet: YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31Bits, .NameIdx: 927, .RegsSize: 30, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX2_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3271 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31, .RegSet: YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31Bits, .NameIdx: 878, .RegsSize: 29, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX0X2_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3272 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRJALR, .RegSet: YGPR_with_sub_cap_addr_in_GPRJALRBits, .NameIdx: 2708, .RegsSize: 26, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRJALRBits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRJALRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3273 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRJALRNonX7, .RegSet: YGPR_with_sub_cap_addr_in_GPRJALRNonX7Bits, .NameIdx: 2176, .RegsSize: 25, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRJALRNonX7Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3274 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31, .RegSet: YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31Bits, .NameIdx: 1129, .RegsSize: 25, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRJALR_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3275 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31, .RegSet: YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31Bits, .NameIdx: 1028, .RegsSize: 24, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRJALRNonX7_and_GPRNoX31RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3276 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRTC, .RegSet: YGPR_with_sub_cap_addr_in_GPRTCBits, .NameIdx: 2562, .RegsSize: 14, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRTCBits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3277 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTC, .RegSet: YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCBits, .NameIdx: 2397, .RegsSize: 13, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCBits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3278 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRTCNonX7, .RegSet: YGPR_with_sub_cap_addr_in_GPRTCNonX7Bits, .NameIdx: 2098, .RegsSize: 13, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRTCNonX7Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRTCNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3279 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7, .RegSet: YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7Bits, .NameIdx: 2009, .RegsSize: 12, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRNoX31_and_GPRTCNonX7RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3280 | { .RegsBegin: FPR64C, .RegSet: FPR64CBits, .NameIdx: 2252, .RegsSize: 8, .RegSetSize: sizeof(FPR64CBits), .ID: RISCV::FPR64CRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3281 | { .RegsBegin: YGPR_with_sub_16_in_GPRF16C, .RegSet: YGPR_with_sub_16_in_GPRF16CBits, .NameIdx: 2259, .RegsSize: 8, .RegSetSize: sizeof(YGPR_with_sub_16_in_GPRF16CBits), .ID: RISCV::YGPR_with_sub_16_in_GPRF16CRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3282 | { .RegsBegin: YGPR_with_sub_cap_addr_in_SR07, .RegSet: YGPR_with_sub_cap_addr_in_SR07Bits, .NameIdx: 1860, .RegsSize: 8, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_SR07Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_SR07RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3283 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRC_and_GPRTC, .RegSet: YGPR_with_sub_cap_addr_in_GPRC_and_GPRTCBits, .NameIdx: 2486, .RegsSize: 6, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRC_and_GPRTCBits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRC_and_GPRTCRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3284 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRC_and_SR07, .RegSet: YGPR_with_sub_cap_addr_in_GPRC_and_SR07Bits, .NameIdx: 1786, .RegsSize: 2, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRC_and_SR07Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRC_and_SR07RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3285 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRX1X5, .RegSet: YGPR_with_sub_cap_addr_in_GPRX1X5Bits, .NameIdx: 1657, .RegsSize: 2, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRX1X5Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX1X5RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3286 | { .RegsBegin: VMV0, .RegSet: VMV0Bits, .NameIdx: 30, .RegsSize: 1, .RegSetSize: sizeof(VMV0Bits), .ID: RISCV::VMV0RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3287 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRX0, .RegSet: YGPR_with_sub_cap_addr_in_GPRX0Bits, .NameIdx: 737, .RegsSize: 1, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRX0Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX0RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3288 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRX1, .RegSet: YGPR_with_sub_cap_addr_in_GPRX1Bits, .NameIdx: 1340, .RegsSize: 1, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRX1Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX1RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3289 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRX5, .RegSet: YGPR_with_sub_cap_addr_in_GPRX5Bits, .NameIdx: 1691, .RegsSize: 1, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRX5Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX5RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3290 | { .RegsBegin: YGPR_with_sub_cap_addr_in_GPRX7, .RegSet: YGPR_with_sub_cap_addr_in_GPRX7Bits, .NameIdx: 1925, .RegsSize: 1, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_GPRX7Bits), .ID: RISCV::YGPR_with_sub_cap_addr_in_GPRX7RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3291 | { .RegsBegin: YGPR_with_sub_cap_addr_in_SP, .RegSet: YGPR_with_sub_cap_addr_in_SPBits, .NameIdx: 2642, .RegsSize: 1, .RegSetSize: sizeof(YGPR_with_sub_cap_addr_in_SPBits), .ID: RISCV::YGPR_with_sub_cap_addr_in_SPRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3292 | { .RegsBegin: VRN2M1, .RegSet: VRN2M1Bits, .NameIdx: 1291, .RegsSize: 31, .RegSetSize: sizeof(VRN2M1Bits), .ID: RISCV::VRN2M1RegClassID, .RegSizeInBits: 128, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3293 | { .RegsBegin: VRN2M1NoV0, .RegSet: VRN2M1NoV0Bits, .NameIdx: 494, .RegsSize: 30, .RegSetSize: sizeof(VRN2M1NoV0Bits), .ID: RISCV::VRN2M1NoV0RegClassID, .RegSizeInBits: 128, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3294 | { .RegsBegin: VRM2, .RegSet: VRM2Bits, .NameIdx: 1421, .RegsSize: 16, .RegSetSize: sizeof(VRM2Bits), .ID: RISCV::VRM2RegClassID, .RegSizeInBits: 128, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3295 | { .RegsBegin: VRM2NoV0, .RegSet: VRM2NoV0Bits, .NameIdx: 618, .RegsSize: 15, .RegSetSize: sizeof(VRM2NoV0Bits), .ID: RISCV::VRM2NoV0RegClassID, .RegSizeInBits: 128, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3296 | { .RegsBegin: VRM2_with_sub_vrm1_0_in_VMV0, .RegSet: VRM2_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 247, .RegsSize: 1, .RegSetSize: sizeof(VRM2_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 128, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3297 | { .RegsBegin: VRN2M1_with_sub_vrm1_0_in_VMV0, .RegSet: VRN2M1_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 4, .RegsSize: 1, .RegSetSize: sizeof(VRN2M1_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN2M1_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 128, .CopyCost: 2, .Allocatable: true, .BaseClass: false }, |
| 3298 | { .RegsBegin: FPR128, .RegSet: FPR128Bits, .NameIdx: 2215, .RegsSize: 32, .RegSetSize: sizeof(FPR128Bits), .ID: RISCV::FPR128RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3299 | { .RegsBegin: FPR128_with_sub_16_in_FPR16C, .RegSet: FPR128_with_sub_16_in_FPR16CBits, .NameIdx: 2316, .RegsSize: 8, .RegSetSize: sizeof(FPR128_with_sub_16_in_FPR16CBits), .ID: RISCV::FPR128_with_sub_16_in_FPR16CRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3300 | { .RegsBegin: VRN3M1, .RegSet: VRN3M1Bits, .NameIdx: 1298, .RegsSize: 30, .RegSetSize: sizeof(VRN3M1Bits), .ID: RISCV::VRN3M1RegClassID, .RegSizeInBits: 192, .CopyCost: 3, .Allocatable: true, .BaseClass: false }, |
| 3301 | { .RegsBegin: VRN3M1NoV0, .RegSet: VRN3M1NoV0Bits, .NameIdx: 505, .RegsSize: 29, .RegSetSize: sizeof(VRN3M1NoV0Bits), .ID: RISCV::VRN3M1NoV0RegClassID, .RegSizeInBits: 192, .CopyCost: 3, .Allocatable: true, .BaseClass: false }, |
| 3302 | { .RegsBegin: VRN3M1_with_sub_vrm1_0_in_VMV0, .RegSet: VRN3M1_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 35, .RegsSize: 1, .RegSetSize: sizeof(VRN3M1_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN3M1_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 192, .CopyCost: 3, .Allocatable: true, .BaseClass: false }, |
| 3303 | { .RegsBegin: VRN4M1, .RegSet: VRN4M1Bits, .NameIdx: 1305, .RegsSize: 29, .RegSetSize: sizeof(VRN4M1Bits), .ID: RISCV::VRN4M1RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3304 | { .RegsBegin: VRN4M1NoV0, .RegSet: VRN4M1NoV0Bits, .NameIdx: 516, .RegsSize: 28, .RegSetSize: sizeof(VRN4M1NoV0Bits), .ID: RISCV::VRN4M1NoV0RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3305 | { .RegsBegin: VRN2M2, .RegSet: VRN2M2Bits, .NameIdx: 1395, .RegsSize: 15, .RegSetSize: sizeof(VRN2M2Bits), .ID: RISCV::VRN2M2RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3306 | { .RegsBegin: VRN2M2NoV0, .RegSet: VRN2M2NoV0Bits, .NameIdx: 585, .RegsSize: 14, .RegSetSize: sizeof(VRN2M2NoV0Bits), .ID: RISCV::VRN2M2NoV0RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3307 | { .RegsBegin: VRM4, .RegSet: VRM4Bits, .NameIdx: 1600, .RegsSize: 8, .RegSetSize: sizeof(VRM4Bits), .ID: RISCV::VRM4RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3308 | { .RegsBegin: VRM4NoV0, .RegSet: VRM4NoV0Bits, .NameIdx: 652, .RegsSize: 7, .RegSetSize: sizeof(VRM4NoV0Bits), .ID: RISCV::VRM4NoV0RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3309 | { .RegsBegin: VRM4_with_sub_vrm1_0_in_VMV0, .RegSet: VRM4_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 412, .RegsSize: 1, .RegSetSize: sizeof(VRM4_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3310 | { .RegsBegin: VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0, .RegSet: VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 221, .RegsSize: 1, .RegSetSize: sizeof(VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN2M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3311 | { .RegsBegin: VRN4M1_with_sub_vrm1_0_in_VMV0, .RegSet: VRN4M1_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 66, .RegsSize: 1, .RegSetSize: sizeof(VRN4M1_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN4M1_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 256, .CopyCost: 4, .Allocatable: true, .BaseClass: false }, |
| 3312 | { .RegsBegin: FPR256, .RegSet: FPR256Bits, .NameIdx: 1736, .RegsSize: 32, .RegSetSize: sizeof(FPR256Bits), .ID: RISCV::FPR256RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3313 | { .RegsBegin: FPR256_with_sub_16_in_FPR16C, .RegSet: FPR256_with_sub_16_in_FPR16CBits, .NameIdx: 2287, .RegsSize: 8, .RegSetSize: sizeof(FPR256_with_sub_16_in_FPR16CBits), .ID: RISCV::FPR256_with_sub_16_in_FPR16CRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 3314 | { .RegsBegin: VRN5M1, .RegSet: VRN5M1Bits, .NameIdx: 1312, .RegsSize: 28, .RegSetSize: sizeof(VRN5M1Bits), .ID: RISCV::VRN5M1RegClassID, .RegSizeInBits: 320, .CopyCost: 5, .Allocatable: true, .BaseClass: false }, |
| 3315 | { .RegsBegin: VRN5M1NoV0, .RegSet: VRN5M1NoV0Bits, .NameIdx: 527, .RegsSize: 27, .RegSetSize: sizeof(VRN5M1NoV0Bits), .ID: RISCV::VRN5M1NoV0RegClassID, .RegSizeInBits: 320, .CopyCost: 5, .Allocatable: true, .BaseClass: false }, |
| 3316 | { .RegsBegin: VRN5M1_with_sub_vrm1_0_in_VMV0, .RegSet: VRN5M1_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 97, .RegsSize: 1, .RegSetSize: sizeof(VRN5M1_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN5M1_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 320, .CopyCost: 5, .Allocatable: true, .BaseClass: false }, |
| 3317 | { .RegsBegin: VRN6M1, .RegSet: VRN6M1Bits, .NameIdx: 1319, .RegsSize: 27, .RegSetSize: sizeof(VRN6M1Bits), .ID: RISCV::VRN6M1RegClassID, .RegSizeInBits: 384, .CopyCost: 6, .Allocatable: true, .BaseClass: false }, |
| 3318 | { .RegsBegin: VRN6M1NoV0, .RegSet: VRN6M1NoV0Bits, .NameIdx: 538, .RegsSize: 26, .RegSetSize: sizeof(VRN6M1NoV0Bits), .ID: RISCV::VRN6M1NoV0RegClassID, .RegSizeInBits: 384, .CopyCost: 6, .Allocatable: true, .BaseClass: false }, |
| 3319 | { .RegsBegin: VRN3M2, .RegSet: VRN3M2Bits, .NameIdx: 1402, .RegsSize: 14, .RegSetSize: sizeof(VRN3M2Bits), .ID: RISCV::VRN3M2RegClassID, .RegSizeInBits: 384, .CopyCost: 6, .Allocatable: true, .BaseClass: false }, |
| 3320 | { .RegsBegin: VRN3M2NoV0, .RegSet: VRN3M2NoV0Bits, .NameIdx: 596, .RegsSize: 13, .RegSetSize: sizeof(VRN3M2NoV0Bits), .ID: RISCV::VRN3M2NoV0RegClassID, .RegSizeInBits: 384, .CopyCost: 6, .Allocatable: true, .BaseClass: false }, |
| 3321 | { .RegsBegin: VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0, .RegSet: VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 276, .RegsSize: 1, .RegSetSize: sizeof(VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN3M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 384, .CopyCost: 6, .Allocatable: true, .BaseClass: false }, |
| 3322 | { .RegsBegin: VRN6M1_with_sub_vrm1_0_in_VMV0, .RegSet: VRN6M1_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 128, .RegsSize: 1, .RegSetSize: sizeof(VRN6M1_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN6M1_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 384, .CopyCost: 6, .Allocatable: true, .BaseClass: false }, |
| 3323 | { .RegsBegin: VRN7M1, .RegSet: VRN7M1Bits, .NameIdx: 1326, .RegsSize: 26, .RegSetSize: sizeof(VRN7M1Bits), .ID: RISCV::VRN7M1RegClassID, .RegSizeInBits: 448, .CopyCost: 7, .Allocatable: true, .BaseClass: false }, |
| 3324 | { .RegsBegin: VRN7M1NoV0, .RegSet: VRN7M1NoV0Bits, .NameIdx: 549, .RegsSize: 25, .RegSetSize: sizeof(VRN7M1NoV0Bits), .ID: RISCV::VRN7M1NoV0RegClassID, .RegSizeInBits: 448, .CopyCost: 7, .Allocatable: true, .BaseClass: false }, |
| 3325 | { .RegsBegin: VRN7M1_with_sub_vrm1_0_in_VMV0, .RegSet: VRN7M1_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 159, .RegsSize: 1, .RegSetSize: sizeof(VRN7M1_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN7M1_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 448, .CopyCost: 7, .Allocatable: true, .BaseClass: false }, |
| 3326 | { .RegsBegin: VRN8M1, .RegSet: VRN8M1Bits, .NameIdx: 1333, .RegsSize: 25, .RegSetSize: sizeof(VRN8M1Bits), .ID: RISCV::VRN8M1RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3327 | { .RegsBegin: VRN8M1NoV0, .RegSet: VRN8M1NoV0Bits, .NameIdx: 560, .RegsSize: 24, .RegSetSize: sizeof(VRN8M1NoV0Bits), .ID: RISCV::VRN8M1NoV0RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3328 | { .RegsBegin: VRN4M2, .RegSet: VRN4M2Bits, .NameIdx: 1409, .RegsSize: 13, .RegSetSize: sizeof(VRN4M2Bits), .ID: RISCV::VRN4M2RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3329 | { .RegsBegin: VRN4M2NoV0, .RegSet: VRN4M2NoV0Bits, .NameIdx: 607, .RegsSize: 12, .RegSetSize: sizeof(VRN4M2NoV0Bits), .ID: RISCV::VRN4M2NoV0RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3330 | { .RegsBegin: VRN2M4, .RegSet: VRN2M4Bits, .NameIdx: 1588, .RegsSize: 7, .RegSetSize: sizeof(VRN2M4Bits), .ID: RISCV::VRN2M4RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3331 | { .RegsBegin: VRN2M4NoV0, .RegSet: VRN2M4NoV0Bits, .NameIdx: 641, .RegsSize: 6, .RegSetSize: sizeof(VRN2M4NoV0Bits), .ID: RISCV::VRN2M4NoV0RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3332 | { .RegsBegin: VRM8, .RegSet: VRM8Bits, .NameIdx: 2232, .RegsSize: 4, .RegSetSize: sizeof(VRM8Bits), .ID: RISCV::VRM8RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3333 | { .RegsBegin: VRM8NoV0, .RegSet: VRM8NoV0Bits, .NameIdx: 675, .RegsSize: 3, .RegSetSize: sizeof(VRM8NoV0Bits), .ID: RISCV::VRM8NoV0RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3334 | { .RegsBegin: VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0, .RegSet: VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 441, .RegsSize: 1, .RegSetSize: sizeof(VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3335 | { .RegsBegin: VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0, .RegSet: VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 386, .RegsSize: 1, .RegSetSize: sizeof(VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN2M4_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3336 | { .RegsBegin: VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0, .RegSet: VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 331, .RegsSize: 1, .RegSetSize: sizeof(VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN4M2_with_sub_vrm2_0_in_VRM2_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3337 | { .RegsBegin: VRN8M1_with_sub_vrm1_0_in_VMV0, .RegSet: VRN8M1_with_sub_vrm1_0_in_VMV0Bits, .NameIdx: 190, .RegsSize: 1, .RegSetSize: sizeof(VRN8M1_with_sub_vrm1_0_in_VMV0Bits), .ID: RISCV::VRN8M1_with_sub_vrm1_0_in_VMV0RegClassID, .RegSizeInBits: 512, .CopyCost: 8, .Allocatable: true, .BaseClass: false }, |
| 3338 | }; |
| 3339 | |
| 3340 | // RISCV Dwarf<->LLVM register mappings. |
| 3341 | extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[] = { |
| 3342 | { .FromReg: 0U, .ToReg: RISCV::X0 }, |
| 3343 | { .FromReg: 1U, .ToReg: RISCV::X1 }, |
| 3344 | { .FromReg: 2U, .ToReg: RISCV::X2 }, |
| 3345 | { .FromReg: 3U, .ToReg: RISCV::X3 }, |
| 3346 | { .FromReg: 4U, .ToReg: RISCV::X4 }, |
| 3347 | { .FromReg: 5U, .ToReg: RISCV::X5 }, |
| 3348 | { .FromReg: 6U, .ToReg: RISCV::X6 }, |
| 3349 | { .FromReg: 7U, .ToReg: RISCV::X7 }, |
| 3350 | { .FromReg: 8U, .ToReg: RISCV::X8 }, |
| 3351 | { .FromReg: 9U, .ToReg: RISCV::X9 }, |
| 3352 | { .FromReg: 10U, .ToReg: RISCV::X10 }, |
| 3353 | { .FromReg: 11U, .ToReg: RISCV::X11 }, |
| 3354 | { .FromReg: 12U, .ToReg: RISCV::X12 }, |
| 3355 | { .FromReg: 13U, .ToReg: RISCV::X13 }, |
| 3356 | { .FromReg: 14U, .ToReg: RISCV::X14 }, |
| 3357 | { .FromReg: 15U, .ToReg: RISCV::X15 }, |
| 3358 | { .FromReg: 16U, .ToReg: RISCV::X16 }, |
| 3359 | { .FromReg: 17U, .ToReg: RISCV::X17 }, |
| 3360 | { .FromReg: 18U, .ToReg: RISCV::X18 }, |
| 3361 | { .FromReg: 19U, .ToReg: RISCV::X19 }, |
| 3362 | { .FromReg: 20U, .ToReg: RISCV::X20 }, |
| 3363 | { .FromReg: 21U, .ToReg: RISCV::X21 }, |
| 3364 | { .FromReg: 22U, .ToReg: RISCV::X22 }, |
| 3365 | { .FromReg: 23U, .ToReg: RISCV::X23 }, |
| 3366 | { .FromReg: 24U, .ToReg: RISCV::X24 }, |
| 3367 | { .FromReg: 25U, .ToReg: RISCV::X25 }, |
| 3368 | { .FromReg: 26U, .ToReg: RISCV::X26 }, |
| 3369 | { .FromReg: 27U, .ToReg: RISCV::X27 }, |
| 3370 | { .FromReg: 28U, .ToReg: RISCV::X28 }, |
| 3371 | { .FromReg: 29U, .ToReg: RISCV::X29 }, |
| 3372 | { .FromReg: 30U, .ToReg: RISCV::X30 }, |
| 3373 | { .FromReg: 31U, .ToReg: RISCV::X31 }, |
| 3374 | { .FromReg: 32U, .ToReg: RISCV::F0_H }, |
| 3375 | { .FromReg: 33U, .ToReg: RISCV::F1_H }, |
| 3376 | { .FromReg: 34U, .ToReg: RISCV::F2_H }, |
| 3377 | { .FromReg: 35U, .ToReg: RISCV::F3_H }, |
| 3378 | { .FromReg: 36U, .ToReg: RISCV::F4_H }, |
| 3379 | { .FromReg: 37U, .ToReg: RISCV::F5_H }, |
| 3380 | { .FromReg: 38U, .ToReg: RISCV::F6_H }, |
| 3381 | { .FromReg: 39U, .ToReg: RISCV::F7_H }, |
| 3382 | { .FromReg: 40U, .ToReg: RISCV::F8_H }, |
| 3383 | { .FromReg: 41U, .ToReg: RISCV::F9_H }, |
| 3384 | { .FromReg: 42U, .ToReg: RISCV::F10_H }, |
| 3385 | { .FromReg: 43U, .ToReg: RISCV::F11_H }, |
| 3386 | { .FromReg: 44U, .ToReg: RISCV::F12_H }, |
| 3387 | { .FromReg: 45U, .ToReg: RISCV::F13_H }, |
| 3388 | { .FromReg: 46U, .ToReg: RISCV::F14_H }, |
| 3389 | { .FromReg: 47U, .ToReg: RISCV::F15_H }, |
| 3390 | { .FromReg: 48U, .ToReg: RISCV::F16_H }, |
| 3391 | { .FromReg: 49U, .ToReg: RISCV::F17_H }, |
| 3392 | { .FromReg: 50U, .ToReg: RISCV::F18_H }, |
| 3393 | { .FromReg: 51U, .ToReg: RISCV::F19_H }, |
| 3394 | { .FromReg: 52U, .ToReg: RISCV::F20_H }, |
| 3395 | { .FromReg: 53U, .ToReg: RISCV::F21_H }, |
| 3396 | { .FromReg: 54U, .ToReg: RISCV::F22_H }, |
| 3397 | { .FromReg: 55U, .ToReg: RISCV::F23_H }, |
| 3398 | { .FromReg: 56U, .ToReg: RISCV::F24_H }, |
| 3399 | { .FromReg: 57U, .ToReg: RISCV::F25_H }, |
| 3400 | { .FromReg: 58U, .ToReg: RISCV::F26_H }, |
| 3401 | { .FromReg: 59U, .ToReg: RISCV::F27_H }, |
| 3402 | { .FromReg: 60U, .ToReg: RISCV::F28_H }, |
| 3403 | { .FromReg: 61U, .ToReg: RISCV::F29_H }, |
| 3404 | { .FromReg: 62U, .ToReg: RISCV::F30_H }, |
| 3405 | { .FromReg: 63U, .ToReg: RISCV::F31_H }, |
| 3406 | { .FromReg: 96U, .ToReg: RISCV::V0 }, |
| 3407 | { .FromReg: 97U, .ToReg: RISCV::V1 }, |
| 3408 | { .FromReg: 98U, .ToReg: RISCV::V2 }, |
| 3409 | { .FromReg: 99U, .ToReg: RISCV::V3 }, |
| 3410 | { .FromReg: 100U, .ToReg: RISCV::V4 }, |
| 3411 | { .FromReg: 101U, .ToReg: RISCV::V5 }, |
| 3412 | { .FromReg: 102U, .ToReg: RISCV::V6 }, |
| 3413 | { .FromReg: 103U, .ToReg: RISCV::V7 }, |
| 3414 | { .FromReg: 104U, .ToReg: RISCV::V8 }, |
| 3415 | { .FromReg: 105U, .ToReg: RISCV::V9 }, |
| 3416 | { .FromReg: 106U, .ToReg: RISCV::V10 }, |
| 3417 | { .FromReg: 107U, .ToReg: RISCV::V11 }, |
| 3418 | { .FromReg: 108U, .ToReg: RISCV::V12 }, |
| 3419 | { .FromReg: 109U, .ToReg: RISCV::V13 }, |
| 3420 | { .FromReg: 110U, .ToReg: RISCV::V14 }, |
| 3421 | { .FromReg: 111U, .ToReg: RISCV::V15 }, |
| 3422 | { .FromReg: 112U, .ToReg: RISCV::V16 }, |
| 3423 | { .FromReg: 113U, .ToReg: RISCV::V17 }, |
| 3424 | { .FromReg: 114U, .ToReg: RISCV::V18 }, |
| 3425 | { .FromReg: 115U, .ToReg: RISCV::V19 }, |
| 3426 | { .FromReg: 116U, .ToReg: RISCV::V20 }, |
| 3427 | { .FromReg: 117U, .ToReg: RISCV::V21 }, |
| 3428 | { .FromReg: 118U, .ToReg: RISCV::V22 }, |
| 3429 | { .FromReg: 119U, .ToReg: RISCV::V23 }, |
| 3430 | { .FromReg: 120U, .ToReg: RISCV::V24 }, |
| 3431 | { .FromReg: 121U, .ToReg: RISCV::V25 }, |
| 3432 | { .FromReg: 122U, .ToReg: RISCV::V26 }, |
| 3433 | { .FromReg: 123U, .ToReg: RISCV::V27 }, |
| 3434 | { .FromReg: 124U, .ToReg: RISCV::V28 }, |
| 3435 | { .FromReg: 125U, .ToReg: RISCV::V29 }, |
| 3436 | { .FromReg: 126U, .ToReg: RISCV::V30 }, |
| 3437 | { .FromReg: 127U, .ToReg: RISCV::V31 }, |
| 3438 | { .FromReg: 3072U, .ToReg: RISCV::T0 }, |
| 3439 | { .FromReg: 3073U, .ToReg: RISCV::T1 }, |
| 3440 | { .FromReg: 3074U, .ToReg: RISCV::T2 }, |
| 3441 | { .FromReg: 3075U, .ToReg: RISCV::T3 }, |
| 3442 | { .FromReg: 3076U, .ToReg: RISCV::T4 }, |
| 3443 | { .FromReg: 3077U, .ToReg: RISCV::T5 }, |
| 3444 | { .FromReg: 3078U, .ToReg: RISCV::T6 }, |
| 3445 | { .FromReg: 3079U, .ToReg: RISCV::T7 }, |
| 3446 | { .FromReg: 3080U, .ToReg: RISCV::T8 }, |
| 3447 | { .FromReg: 3081U, .ToReg: RISCV::T9 }, |
| 3448 | { .FromReg: 3082U, .ToReg: RISCV::T10 }, |
| 3449 | { .FromReg: 3083U, .ToReg: RISCV::T11 }, |
| 3450 | { .FromReg: 3084U, .ToReg: RISCV::T12 }, |
| 3451 | { .FromReg: 3085U, .ToReg: RISCV::T13 }, |
| 3452 | { .FromReg: 3086U, .ToReg: RISCV::T14 }, |
| 3453 | { .FromReg: 3087U, .ToReg: RISCV::T15 }, |
| 3454 | { .FromReg: 3088U, .ToReg: RISCV::F0_Q2 }, |
| 3455 | { .FromReg: 3089U, .ToReg: RISCV::F1_Q2 }, |
| 3456 | { .FromReg: 3090U, .ToReg: RISCV::F2_Q2 }, |
| 3457 | { .FromReg: 3091U, .ToReg: RISCV::F3_Q2 }, |
| 3458 | { .FromReg: 3092U, .ToReg: RISCV::F4_Q2 }, |
| 3459 | { .FromReg: 3093U, .ToReg: RISCV::F5_Q2 }, |
| 3460 | { .FromReg: 3094U, .ToReg: RISCV::F6_Q2 }, |
| 3461 | { .FromReg: 3095U, .ToReg: RISCV::F7_Q2 }, |
| 3462 | { .FromReg: 3096U, .ToReg: RISCV::F8_Q2 }, |
| 3463 | { .FromReg: 3097U, .ToReg: RISCV::F9_Q2 }, |
| 3464 | { .FromReg: 3098U, .ToReg: RISCV::F10_Q2 }, |
| 3465 | { .FromReg: 3099U, .ToReg: RISCV::F11_Q2 }, |
| 3466 | { .FromReg: 3100U, .ToReg: RISCV::F12_Q2 }, |
| 3467 | { .FromReg: 3101U, .ToReg: RISCV::F13_Q2 }, |
| 3468 | { .FromReg: 3102U, .ToReg: RISCV::F14_Q2 }, |
| 3469 | { .FromReg: 3103U, .ToReg: RISCV::F15_Q2 }, |
| 3470 | { .FromReg: 3104U, .ToReg: RISCV::F16_Q2 }, |
| 3471 | { .FromReg: 3105U, .ToReg: RISCV::F17_Q2 }, |
| 3472 | { .FromReg: 3106U, .ToReg: RISCV::F18_Q2 }, |
| 3473 | { .FromReg: 3107U, .ToReg: RISCV::F19_Q2 }, |
| 3474 | { .FromReg: 3108U, .ToReg: RISCV::F20_Q2 }, |
| 3475 | { .FromReg: 3109U, .ToReg: RISCV::F21_Q2 }, |
| 3476 | { .FromReg: 3110U, .ToReg: RISCV::F22_Q2 }, |
| 3477 | { .FromReg: 3111U, .ToReg: RISCV::F23_Q2 }, |
| 3478 | { .FromReg: 3112U, .ToReg: RISCV::F24_Q2 }, |
| 3479 | { .FromReg: 3113U, .ToReg: RISCV::F25_Q2 }, |
| 3480 | { .FromReg: 3114U, .ToReg: RISCV::F26_Q2 }, |
| 3481 | { .FromReg: 3115U, .ToReg: RISCV::F27_Q2 }, |
| 3482 | { .FromReg: 3116U, .ToReg: RISCV::F28_Q2 }, |
| 3483 | { .FromReg: 3117U, .ToReg: RISCV::F29_Q2 }, |
| 3484 | { .FromReg: 3118U, .ToReg: RISCV::F30_Q2 }, |
| 3485 | { .FromReg: 3119U, .ToReg: RISCV::F31_Q2 }, |
| 3486 | { .FromReg: 4020U, .ToReg: RISCV::M0 }, |
| 3487 | { .FromReg: 4021U, .ToReg: RISCV::M1 }, |
| 3488 | { .FromReg: 4022U, .ToReg: RISCV::M2 }, |
| 3489 | { .FromReg: 4023U, .ToReg: RISCV::M3 }, |
| 3490 | { .FromReg: 4024U, .ToReg: RISCV::M4 }, |
| 3491 | { .FromReg: 4025U, .ToReg: RISCV::M5 }, |
| 3492 | { .FromReg: 4026U, .ToReg: RISCV::M6 }, |
| 3493 | { .FromReg: 4027U, .ToReg: RISCV::M7 }, |
| 3494 | { .FromReg: 7202U, .ToReg: RISCV::VLENB }, |
| 3495 | }; |
| 3496 | extern const unsigned RISCVDwarfFlavour0Dwarf2LSize = std::size(RISCVDwarfFlavour0Dwarf2L); |
| 3497 | |
| 3498 | extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[] = { |
| 3499 | { .FromReg: 0U, .ToReg: RISCV::X0 }, |
| 3500 | { .FromReg: 1U, .ToReg: RISCV::X1 }, |
| 3501 | { .FromReg: 2U, .ToReg: RISCV::X2 }, |
| 3502 | { .FromReg: 3U, .ToReg: RISCV::X3 }, |
| 3503 | { .FromReg: 4U, .ToReg: RISCV::X4 }, |
| 3504 | { .FromReg: 5U, .ToReg: RISCV::X5 }, |
| 3505 | { .FromReg: 6U, .ToReg: RISCV::X6 }, |
| 3506 | { .FromReg: 7U, .ToReg: RISCV::X7 }, |
| 3507 | { .FromReg: 8U, .ToReg: RISCV::X8 }, |
| 3508 | { .FromReg: 9U, .ToReg: RISCV::X9 }, |
| 3509 | { .FromReg: 10U, .ToReg: RISCV::X10 }, |
| 3510 | { .FromReg: 11U, .ToReg: RISCV::X11 }, |
| 3511 | { .FromReg: 12U, .ToReg: RISCV::X12 }, |
| 3512 | { .FromReg: 13U, .ToReg: RISCV::X13 }, |
| 3513 | { .FromReg: 14U, .ToReg: RISCV::X14 }, |
| 3514 | { .FromReg: 15U, .ToReg: RISCV::X15 }, |
| 3515 | { .FromReg: 16U, .ToReg: RISCV::X16 }, |
| 3516 | { .FromReg: 17U, .ToReg: RISCV::X17 }, |
| 3517 | { .FromReg: 18U, .ToReg: RISCV::X18 }, |
| 3518 | { .FromReg: 19U, .ToReg: RISCV::X19 }, |
| 3519 | { .FromReg: 20U, .ToReg: RISCV::X20 }, |
| 3520 | { .FromReg: 21U, .ToReg: RISCV::X21 }, |
| 3521 | { .FromReg: 22U, .ToReg: RISCV::X22 }, |
| 3522 | { .FromReg: 23U, .ToReg: RISCV::X23 }, |
| 3523 | { .FromReg: 24U, .ToReg: RISCV::X24 }, |
| 3524 | { .FromReg: 25U, .ToReg: RISCV::X25 }, |
| 3525 | { .FromReg: 26U, .ToReg: RISCV::X26 }, |
| 3526 | { .FromReg: 27U, .ToReg: RISCV::X27 }, |
| 3527 | { .FromReg: 28U, .ToReg: RISCV::X28 }, |
| 3528 | { .FromReg: 29U, .ToReg: RISCV::X29 }, |
| 3529 | { .FromReg: 30U, .ToReg: RISCV::X30 }, |
| 3530 | { .FromReg: 31U, .ToReg: RISCV::X31 }, |
| 3531 | { .FromReg: 32U, .ToReg: RISCV::F0_H }, |
| 3532 | { .FromReg: 33U, .ToReg: RISCV::F1_H }, |
| 3533 | { .FromReg: 34U, .ToReg: RISCV::F2_H }, |
| 3534 | { .FromReg: 35U, .ToReg: RISCV::F3_H }, |
| 3535 | { .FromReg: 36U, .ToReg: RISCV::F4_H }, |
| 3536 | { .FromReg: 37U, .ToReg: RISCV::F5_H }, |
| 3537 | { .FromReg: 38U, .ToReg: RISCV::F6_H }, |
| 3538 | { .FromReg: 39U, .ToReg: RISCV::F7_H }, |
| 3539 | { .FromReg: 40U, .ToReg: RISCV::F8_H }, |
| 3540 | { .FromReg: 41U, .ToReg: RISCV::F9_H }, |
| 3541 | { .FromReg: 42U, .ToReg: RISCV::F10_H }, |
| 3542 | { .FromReg: 43U, .ToReg: RISCV::F11_H }, |
| 3543 | { .FromReg: 44U, .ToReg: RISCV::F12_H }, |
| 3544 | { .FromReg: 45U, .ToReg: RISCV::F13_H }, |
| 3545 | { .FromReg: 46U, .ToReg: RISCV::F14_H }, |
| 3546 | { .FromReg: 47U, .ToReg: RISCV::F15_H }, |
| 3547 | { .FromReg: 48U, .ToReg: RISCV::F16_H }, |
| 3548 | { .FromReg: 49U, .ToReg: RISCV::F17_H }, |
| 3549 | { .FromReg: 50U, .ToReg: RISCV::F18_H }, |
| 3550 | { .FromReg: 51U, .ToReg: RISCV::F19_H }, |
| 3551 | { .FromReg: 52U, .ToReg: RISCV::F20_H }, |
| 3552 | { .FromReg: 53U, .ToReg: RISCV::F21_H }, |
| 3553 | { .FromReg: 54U, .ToReg: RISCV::F22_H }, |
| 3554 | { .FromReg: 55U, .ToReg: RISCV::F23_H }, |
| 3555 | { .FromReg: 56U, .ToReg: RISCV::F24_H }, |
| 3556 | { .FromReg: 57U, .ToReg: RISCV::F25_H }, |
| 3557 | { .FromReg: 58U, .ToReg: RISCV::F26_H }, |
| 3558 | { .FromReg: 59U, .ToReg: RISCV::F27_H }, |
| 3559 | { .FromReg: 60U, .ToReg: RISCV::F28_H }, |
| 3560 | { .FromReg: 61U, .ToReg: RISCV::F29_H }, |
| 3561 | { .FromReg: 62U, .ToReg: RISCV::F30_H }, |
| 3562 | { .FromReg: 63U, .ToReg: RISCV::F31_H }, |
| 3563 | { .FromReg: 96U, .ToReg: RISCV::V0 }, |
| 3564 | { .FromReg: 97U, .ToReg: RISCV::V1 }, |
| 3565 | { .FromReg: 98U, .ToReg: RISCV::V2 }, |
| 3566 | { .FromReg: 99U, .ToReg: RISCV::V3 }, |
| 3567 | { .FromReg: 100U, .ToReg: RISCV::V4 }, |
| 3568 | { .FromReg: 101U, .ToReg: RISCV::V5 }, |
| 3569 | { .FromReg: 102U, .ToReg: RISCV::V6 }, |
| 3570 | { .FromReg: 103U, .ToReg: RISCV::V7 }, |
| 3571 | { .FromReg: 104U, .ToReg: RISCV::V8 }, |
| 3572 | { .FromReg: 105U, .ToReg: RISCV::V9 }, |
| 3573 | { .FromReg: 106U, .ToReg: RISCV::V10 }, |
| 3574 | { .FromReg: 107U, .ToReg: RISCV::V11 }, |
| 3575 | { .FromReg: 108U, .ToReg: RISCV::V12 }, |
| 3576 | { .FromReg: 109U, .ToReg: RISCV::V13 }, |
| 3577 | { .FromReg: 110U, .ToReg: RISCV::V14 }, |
| 3578 | { .FromReg: 111U, .ToReg: RISCV::V15 }, |
| 3579 | { .FromReg: 112U, .ToReg: RISCV::V16 }, |
| 3580 | { .FromReg: 113U, .ToReg: RISCV::V17 }, |
| 3581 | { .FromReg: 114U, .ToReg: RISCV::V18 }, |
| 3582 | { .FromReg: 115U, .ToReg: RISCV::V19 }, |
| 3583 | { .FromReg: 116U, .ToReg: RISCV::V20 }, |
| 3584 | { .FromReg: 117U, .ToReg: RISCV::V21 }, |
| 3585 | { .FromReg: 118U, .ToReg: RISCV::V22 }, |
| 3586 | { .FromReg: 119U, .ToReg: RISCV::V23 }, |
| 3587 | { .FromReg: 120U, .ToReg: RISCV::V24 }, |
| 3588 | { .FromReg: 121U, .ToReg: RISCV::V25 }, |
| 3589 | { .FromReg: 122U, .ToReg: RISCV::V26 }, |
| 3590 | { .FromReg: 123U, .ToReg: RISCV::V27 }, |
| 3591 | { .FromReg: 124U, .ToReg: RISCV::V28 }, |
| 3592 | { .FromReg: 125U, .ToReg: RISCV::V29 }, |
| 3593 | { .FromReg: 126U, .ToReg: RISCV::V30 }, |
| 3594 | { .FromReg: 127U, .ToReg: RISCV::V31 }, |
| 3595 | { .FromReg: 3072U, .ToReg: RISCV::T0 }, |
| 3596 | { .FromReg: 3073U, .ToReg: RISCV::T1 }, |
| 3597 | { .FromReg: 3074U, .ToReg: RISCV::T2 }, |
| 3598 | { .FromReg: 3075U, .ToReg: RISCV::T3 }, |
| 3599 | { .FromReg: 3076U, .ToReg: RISCV::T4 }, |
| 3600 | { .FromReg: 3077U, .ToReg: RISCV::T5 }, |
| 3601 | { .FromReg: 3078U, .ToReg: RISCV::T6 }, |
| 3602 | { .FromReg: 3079U, .ToReg: RISCV::T7 }, |
| 3603 | { .FromReg: 3080U, .ToReg: RISCV::T8 }, |
| 3604 | { .FromReg: 3081U, .ToReg: RISCV::T9 }, |
| 3605 | { .FromReg: 3082U, .ToReg: RISCV::T10 }, |
| 3606 | { .FromReg: 3083U, .ToReg: RISCV::T11 }, |
| 3607 | { .FromReg: 3084U, .ToReg: RISCV::T12 }, |
| 3608 | { .FromReg: 3085U, .ToReg: RISCV::T13 }, |
| 3609 | { .FromReg: 3086U, .ToReg: RISCV::T14 }, |
| 3610 | { .FromReg: 3087U, .ToReg: RISCV::T15 }, |
| 3611 | { .FromReg: 3088U, .ToReg: RISCV::F0_Q2 }, |
| 3612 | { .FromReg: 3089U, .ToReg: RISCV::F1_Q2 }, |
| 3613 | { .FromReg: 3090U, .ToReg: RISCV::F2_Q2 }, |
| 3614 | { .FromReg: 3091U, .ToReg: RISCV::F3_Q2 }, |
| 3615 | { .FromReg: 3092U, .ToReg: RISCV::F4_Q2 }, |
| 3616 | { .FromReg: 3093U, .ToReg: RISCV::F5_Q2 }, |
| 3617 | { .FromReg: 3094U, .ToReg: RISCV::F6_Q2 }, |
| 3618 | { .FromReg: 3095U, .ToReg: RISCV::F7_Q2 }, |
| 3619 | { .FromReg: 3096U, .ToReg: RISCV::F8_Q2 }, |
| 3620 | { .FromReg: 3097U, .ToReg: RISCV::F9_Q2 }, |
| 3621 | { .FromReg: 3098U, .ToReg: RISCV::F10_Q2 }, |
| 3622 | { .FromReg: 3099U, .ToReg: RISCV::F11_Q2 }, |
| 3623 | { .FromReg: 3100U, .ToReg: RISCV::F12_Q2 }, |
| 3624 | { .FromReg: 3101U, .ToReg: RISCV::F13_Q2 }, |
| 3625 | { .FromReg: 3102U, .ToReg: RISCV::F14_Q2 }, |
| 3626 | { .FromReg: 3103U, .ToReg: RISCV::F15_Q2 }, |
| 3627 | { .FromReg: 3104U, .ToReg: RISCV::F16_Q2 }, |
| 3628 | { .FromReg: 3105U, .ToReg: RISCV::F17_Q2 }, |
| 3629 | { .FromReg: 3106U, .ToReg: RISCV::F18_Q2 }, |
| 3630 | { .FromReg: 3107U, .ToReg: RISCV::F19_Q2 }, |
| 3631 | { .FromReg: 3108U, .ToReg: RISCV::F20_Q2 }, |
| 3632 | { .FromReg: 3109U, .ToReg: RISCV::F21_Q2 }, |
| 3633 | { .FromReg: 3110U, .ToReg: RISCV::F22_Q2 }, |
| 3634 | { .FromReg: 3111U, .ToReg: RISCV::F23_Q2 }, |
| 3635 | { .FromReg: 3112U, .ToReg: RISCV::F24_Q2 }, |
| 3636 | { .FromReg: 3113U, .ToReg: RISCV::F25_Q2 }, |
| 3637 | { .FromReg: 3114U, .ToReg: RISCV::F26_Q2 }, |
| 3638 | { .FromReg: 3115U, .ToReg: RISCV::F27_Q2 }, |
| 3639 | { .FromReg: 3116U, .ToReg: RISCV::F28_Q2 }, |
| 3640 | { .FromReg: 3117U, .ToReg: RISCV::F29_Q2 }, |
| 3641 | { .FromReg: 3118U, .ToReg: RISCV::F30_Q2 }, |
| 3642 | { .FromReg: 3119U, .ToReg: RISCV::F31_Q2 }, |
| 3643 | { .FromReg: 4020U, .ToReg: RISCV::M0 }, |
| 3644 | { .FromReg: 4021U, .ToReg: RISCV::M1 }, |
| 3645 | { .FromReg: 4022U, .ToReg: RISCV::M2 }, |
| 3646 | { .FromReg: 4023U, .ToReg: RISCV::M3 }, |
| 3647 | { .FromReg: 4024U, .ToReg: RISCV::M4 }, |
| 3648 | { .FromReg: 4025U, .ToReg: RISCV::M5 }, |
| 3649 | { .FromReg: 4026U, .ToReg: RISCV::M6 }, |
| 3650 | { .FromReg: 4027U, .ToReg: RISCV::M7 }, |
| 3651 | { .FromReg: 7202U, .ToReg: RISCV::VLENB }, |
| 3652 | }; |
| 3653 | extern const unsigned RISCVEHFlavour0Dwarf2LSize = std::size(RISCVEHFlavour0Dwarf2L); |
| 3654 | |
| 3655 | extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[] = { |
| 3656 | { .FromReg: RISCV::VLENB, .ToReg: 7202U }, |
| 3657 | { .FromReg: RISCV::M0, .ToReg: 4020U }, |
| 3658 | { .FromReg: RISCV::M1, .ToReg: 4021U }, |
| 3659 | { .FromReg: RISCV::M2, .ToReg: 4022U }, |
| 3660 | { .FromReg: RISCV::M3, .ToReg: 4023U }, |
| 3661 | { .FromReg: RISCV::M4, .ToReg: 4024U }, |
| 3662 | { .FromReg: RISCV::M5, .ToReg: 4025U }, |
| 3663 | { .FromReg: RISCV::M6, .ToReg: 4026U }, |
| 3664 | { .FromReg: RISCV::M7, .ToReg: 4027U }, |
| 3665 | { .FromReg: RISCV::T0, .ToReg: 3072U }, |
| 3666 | { .FromReg: RISCV::T1, .ToReg: 3073U }, |
| 3667 | { .FromReg: RISCV::T2, .ToReg: 3074U }, |
| 3668 | { .FromReg: RISCV::T3, .ToReg: 3075U }, |
| 3669 | { .FromReg: RISCV::T4, .ToReg: 3076U }, |
| 3670 | { .FromReg: RISCV::T5, .ToReg: 3077U }, |
| 3671 | { .FromReg: RISCV::T6, .ToReg: 3078U }, |
| 3672 | { .FromReg: RISCV::T7, .ToReg: 3079U }, |
| 3673 | { .FromReg: RISCV::T8, .ToReg: 3080U }, |
| 3674 | { .FromReg: RISCV::T9, .ToReg: 3081U }, |
| 3675 | { .FromReg: RISCV::T10, .ToReg: 3082U }, |
| 3676 | { .FromReg: RISCV::T11, .ToReg: 3083U }, |
| 3677 | { .FromReg: RISCV::T12, .ToReg: 3084U }, |
| 3678 | { .FromReg: RISCV::T13, .ToReg: 3085U }, |
| 3679 | { .FromReg: RISCV::T14, .ToReg: 3086U }, |
| 3680 | { .FromReg: RISCV::T15, .ToReg: 3087U }, |
| 3681 | { .FromReg: RISCV::V0, .ToReg: 96U }, |
| 3682 | { .FromReg: RISCV::V1, .ToReg: 97U }, |
| 3683 | { .FromReg: RISCV::V2, .ToReg: 98U }, |
| 3684 | { .FromReg: RISCV::V3, .ToReg: 99U }, |
| 3685 | { .FromReg: RISCV::V4, .ToReg: 100U }, |
| 3686 | { .FromReg: RISCV::V5, .ToReg: 101U }, |
| 3687 | { .FromReg: RISCV::V6, .ToReg: 102U }, |
| 3688 | { .FromReg: RISCV::V7, .ToReg: 103U }, |
| 3689 | { .FromReg: RISCV::V8, .ToReg: 104U }, |
| 3690 | { .FromReg: RISCV::V9, .ToReg: 105U }, |
| 3691 | { .FromReg: RISCV::V10, .ToReg: 106U }, |
| 3692 | { .FromReg: RISCV::V11, .ToReg: 107U }, |
| 3693 | { .FromReg: RISCV::V12, .ToReg: 108U }, |
| 3694 | { .FromReg: RISCV::V13, .ToReg: 109U }, |
| 3695 | { .FromReg: RISCV::V14, .ToReg: 110U }, |
| 3696 | { .FromReg: RISCV::V15, .ToReg: 111U }, |
| 3697 | { .FromReg: RISCV::V16, .ToReg: 112U }, |
| 3698 | { .FromReg: RISCV::V17, .ToReg: 113U }, |
| 3699 | { .FromReg: RISCV::V18, .ToReg: 114U }, |
| 3700 | { .FromReg: RISCV::V19, .ToReg: 115U }, |
| 3701 | { .FromReg: RISCV::V20, .ToReg: 116U }, |
| 3702 | { .FromReg: RISCV::V21, .ToReg: 117U }, |
| 3703 | { .FromReg: RISCV::V22, .ToReg: 118U }, |
| 3704 | { .FromReg: RISCV::V23, .ToReg: 119U }, |
| 3705 | { .FromReg: RISCV::V24, .ToReg: 120U }, |
| 3706 | { .FromReg: RISCV::V25, .ToReg: 121U }, |
| 3707 | { .FromReg: RISCV::V26, .ToReg: 122U }, |
| 3708 | { .FromReg: RISCV::V27, .ToReg: 123U }, |
| 3709 | { .FromReg: RISCV::V28, .ToReg: 124U }, |
| 3710 | { .FromReg: RISCV::V29, .ToReg: 125U }, |
| 3711 | { .FromReg: RISCV::V30, .ToReg: 126U }, |
| 3712 | { .FromReg: RISCV::V31, .ToReg: 127U }, |
| 3713 | { .FromReg: RISCV::X0, .ToReg: 0U }, |
| 3714 | { .FromReg: RISCV::X1, .ToReg: 1U }, |
| 3715 | { .FromReg: RISCV::X2, .ToReg: 2U }, |
| 3716 | { .FromReg: RISCV::X3, .ToReg: 3U }, |
| 3717 | { .FromReg: RISCV::X4, .ToReg: 4U }, |
| 3718 | { .FromReg: RISCV::X5, .ToReg: 5U }, |
| 3719 | { .FromReg: RISCV::X6, .ToReg: 6U }, |
| 3720 | { .FromReg: RISCV::X7, .ToReg: 7U }, |
| 3721 | { .FromReg: RISCV::X8, .ToReg: 8U }, |
| 3722 | { .FromReg: RISCV::X9, .ToReg: 9U }, |
| 3723 | { .FromReg: RISCV::X10, .ToReg: 10U }, |
| 3724 | { .FromReg: RISCV::X11, .ToReg: 11U }, |
| 3725 | { .FromReg: RISCV::X12, .ToReg: 12U }, |
| 3726 | { .FromReg: RISCV::X13, .ToReg: 13U }, |
| 3727 | { .FromReg: RISCV::X14, .ToReg: 14U }, |
| 3728 | { .FromReg: RISCV::X15, .ToReg: 15U }, |
| 3729 | { .FromReg: RISCV::X16, .ToReg: 16U }, |
| 3730 | { .FromReg: RISCV::X17, .ToReg: 17U }, |
| 3731 | { .FromReg: RISCV::X18, .ToReg: 18U }, |
| 3732 | { .FromReg: RISCV::X19, .ToReg: 19U }, |
| 3733 | { .FromReg: RISCV::X20, .ToReg: 20U }, |
| 3734 | { .FromReg: RISCV::X21, .ToReg: 21U }, |
| 3735 | { .FromReg: RISCV::X22, .ToReg: 22U }, |
| 3736 | { .FromReg: RISCV::X23, .ToReg: 23U }, |
| 3737 | { .FromReg: RISCV::X24, .ToReg: 24U }, |
| 3738 | { .FromReg: RISCV::X25, .ToReg: 25U }, |
| 3739 | { .FromReg: RISCV::X26, .ToReg: 26U }, |
| 3740 | { .FromReg: RISCV::X27, .ToReg: 27U }, |
| 3741 | { .FromReg: RISCV::X28, .ToReg: 28U }, |
| 3742 | { .FromReg: RISCV::X29, .ToReg: 29U }, |
| 3743 | { .FromReg: RISCV::X30, .ToReg: 30U }, |
| 3744 | { .FromReg: RISCV::X31, .ToReg: 31U }, |
| 3745 | { .FromReg: RISCV::F0_D, .ToReg: 32U }, |
| 3746 | { .FromReg: RISCV::F1_D, .ToReg: 33U }, |
| 3747 | { .FromReg: RISCV::F2_D, .ToReg: 34U }, |
| 3748 | { .FromReg: RISCV::F3_D, .ToReg: 35U }, |
| 3749 | { .FromReg: RISCV::F4_D, .ToReg: 36U }, |
| 3750 | { .FromReg: RISCV::F5_D, .ToReg: 37U }, |
| 3751 | { .FromReg: RISCV::F6_D, .ToReg: 38U }, |
| 3752 | { .FromReg: RISCV::F7_D, .ToReg: 39U }, |
| 3753 | { .FromReg: RISCV::F8_D, .ToReg: 40U }, |
| 3754 | { .FromReg: RISCV::F9_D, .ToReg: 41U }, |
| 3755 | { .FromReg: RISCV::F10_D, .ToReg: 42U }, |
| 3756 | { .FromReg: RISCV::F11_D, .ToReg: 43U }, |
| 3757 | { .FromReg: RISCV::F12_D, .ToReg: 44U }, |
| 3758 | { .FromReg: RISCV::F13_D, .ToReg: 45U }, |
| 3759 | { .FromReg: RISCV::F14_D, .ToReg: 46U }, |
| 3760 | { .FromReg: RISCV::F15_D, .ToReg: 47U }, |
| 3761 | { .FromReg: RISCV::F16_D, .ToReg: 48U }, |
| 3762 | { .FromReg: RISCV::F17_D, .ToReg: 49U }, |
| 3763 | { .FromReg: RISCV::F18_D, .ToReg: 50U }, |
| 3764 | { .FromReg: RISCV::F19_D, .ToReg: 51U }, |
| 3765 | { .FromReg: RISCV::F20_D, .ToReg: 52U }, |
| 3766 | { .FromReg: RISCV::F21_D, .ToReg: 53U }, |
| 3767 | { .FromReg: RISCV::F22_D, .ToReg: 54U }, |
| 3768 | { .FromReg: RISCV::F23_D, .ToReg: 55U }, |
| 3769 | { .FromReg: RISCV::F24_D, .ToReg: 56U }, |
| 3770 | { .FromReg: RISCV::F25_D, .ToReg: 57U }, |
| 3771 | { .FromReg: RISCV::F26_D, .ToReg: 58U }, |
| 3772 | { .FromReg: RISCV::F27_D, .ToReg: 59U }, |
| 3773 | { .FromReg: RISCV::F28_D, .ToReg: 60U }, |
| 3774 | { .FromReg: RISCV::F29_D, .ToReg: 61U }, |
| 3775 | { .FromReg: RISCV::F30_D, .ToReg: 62U }, |
| 3776 | { .FromReg: RISCV::F31_D, .ToReg: 63U }, |
| 3777 | { .FromReg: RISCV::F0_F, .ToReg: 32U }, |
| 3778 | { .FromReg: RISCV::F1_F, .ToReg: 33U }, |
| 3779 | { .FromReg: RISCV::F2_F, .ToReg: 34U }, |
| 3780 | { .FromReg: RISCV::F3_F, .ToReg: 35U }, |
| 3781 | { .FromReg: RISCV::F4_F, .ToReg: 36U }, |
| 3782 | { .FromReg: RISCV::F5_F, .ToReg: 37U }, |
| 3783 | { .FromReg: RISCV::F6_F, .ToReg: 38U }, |
| 3784 | { .FromReg: RISCV::F7_F, .ToReg: 39U }, |
| 3785 | { .FromReg: RISCV::F8_F, .ToReg: 40U }, |
| 3786 | { .FromReg: RISCV::F9_F, .ToReg: 41U }, |
| 3787 | { .FromReg: RISCV::F10_F, .ToReg: 42U }, |
| 3788 | { .FromReg: RISCV::F11_F, .ToReg: 43U }, |
| 3789 | { .FromReg: RISCV::F12_F, .ToReg: 44U }, |
| 3790 | { .FromReg: RISCV::F13_F, .ToReg: 45U }, |
| 3791 | { .FromReg: RISCV::F14_F, .ToReg: 46U }, |
| 3792 | { .FromReg: RISCV::F15_F, .ToReg: 47U }, |
| 3793 | { .FromReg: RISCV::F16_F, .ToReg: 48U }, |
| 3794 | { .FromReg: RISCV::F17_F, .ToReg: 49U }, |
| 3795 | { .FromReg: RISCV::F18_F, .ToReg: 50U }, |
| 3796 | { .FromReg: RISCV::F19_F, .ToReg: 51U }, |
| 3797 | { .FromReg: RISCV::F20_F, .ToReg: 52U }, |
| 3798 | { .FromReg: RISCV::F21_F, .ToReg: 53U }, |
| 3799 | { .FromReg: RISCV::F22_F, .ToReg: 54U }, |
| 3800 | { .FromReg: RISCV::F23_F, .ToReg: 55U }, |
| 3801 | { .FromReg: RISCV::F24_F, .ToReg: 56U }, |
| 3802 | { .FromReg: RISCV::F25_F, .ToReg: 57U }, |
| 3803 | { .FromReg: RISCV::F26_F, .ToReg: 58U }, |
| 3804 | { .FromReg: RISCV::F27_F, .ToReg: 59U }, |
| 3805 | { .FromReg: RISCV::F28_F, .ToReg: 60U }, |
| 3806 | { .FromReg: RISCV::F29_F, .ToReg: 61U }, |
| 3807 | { .FromReg: RISCV::F30_F, .ToReg: 62U }, |
| 3808 | { .FromReg: RISCV::F31_F, .ToReg: 63U }, |
| 3809 | { .FromReg: RISCV::F0_H, .ToReg: 32U }, |
| 3810 | { .FromReg: RISCV::F1_H, .ToReg: 33U }, |
| 3811 | { .FromReg: RISCV::F2_H, .ToReg: 34U }, |
| 3812 | { .FromReg: RISCV::F3_H, .ToReg: 35U }, |
| 3813 | { .FromReg: RISCV::F4_H, .ToReg: 36U }, |
| 3814 | { .FromReg: RISCV::F5_H, .ToReg: 37U }, |
| 3815 | { .FromReg: RISCV::F6_H, .ToReg: 38U }, |
| 3816 | { .FromReg: RISCV::F7_H, .ToReg: 39U }, |
| 3817 | { .FromReg: RISCV::F8_H, .ToReg: 40U }, |
| 3818 | { .FromReg: RISCV::F9_H, .ToReg: 41U }, |
| 3819 | { .FromReg: RISCV::F10_H, .ToReg: 42U }, |
| 3820 | { .FromReg: RISCV::F11_H, .ToReg: 43U }, |
| 3821 | { .FromReg: RISCV::F12_H, .ToReg: 44U }, |
| 3822 | { .FromReg: RISCV::F13_H, .ToReg: 45U }, |
| 3823 | { .FromReg: RISCV::F14_H, .ToReg: 46U }, |
| 3824 | { .FromReg: RISCV::F15_H, .ToReg: 47U }, |
| 3825 | { .FromReg: RISCV::F16_H, .ToReg: 48U }, |
| 3826 | { .FromReg: RISCV::F17_H, .ToReg: 49U }, |
| 3827 | { .FromReg: RISCV::F18_H, .ToReg: 50U }, |
| 3828 | { .FromReg: RISCV::F19_H, .ToReg: 51U }, |
| 3829 | { .FromReg: RISCV::F20_H, .ToReg: 52U }, |
| 3830 | { .FromReg: RISCV::F21_H, .ToReg: 53U }, |
| 3831 | { .FromReg: RISCV::F22_H, .ToReg: 54U }, |
| 3832 | { .FromReg: RISCV::F23_H, .ToReg: 55U }, |
| 3833 | { .FromReg: RISCV::F24_H, .ToReg: 56U }, |
| 3834 | { .FromReg: RISCV::F25_H, .ToReg: 57U }, |
| 3835 | { .FromReg: RISCV::F26_H, .ToReg: 58U }, |
| 3836 | { .FromReg: RISCV::F27_H, .ToReg: 59U }, |
| 3837 | { .FromReg: RISCV::F28_H, .ToReg: 60U }, |
| 3838 | { .FromReg: RISCV::F29_H, .ToReg: 61U }, |
| 3839 | { .FromReg: RISCV::F30_H, .ToReg: 62U }, |
| 3840 | { .FromReg: RISCV::F31_H, .ToReg: 63U }, |
| 3841 | { .FromReg: RISCV::F0_Q, .ToReg: 32U }, |
| 3842 | { .FromReg: RISCV::F1_Q, .ToReg: 33U }, |
| 3843 | { .FromReg: RISCV::F2_Q, .ToReg: 34U }, |
| 3844 | { .FromReg: RISCV::F3_Q, .ToReg: 35U }, |
| 3845 | { .FromReg: RISCV::F4_Q, .ToReg: 36U }, |
| 3846 | { .FromReg: RISCV::F5_Q, .ToReg: 37U }, |
| 3847 | { .FromReg: RISCV::F6_Q, .ToReg: 38U }, |
| 3848 | { .FromReg: RISCV::F7_Q, .ToReg: 39U }, |
| 3849 | { .FromReg: RISCV::F8_Q, .ToReg: 40U }, |
| 3850 | { .FromReg: RISCV::F9_Q, .ToReg: 41U }, |
| 3851 | { .FromReg: RISCV::F10_Q, .ToReg: 42U }, |
| 3852 | { .FromReg: RISCV::F11_Q, .ToReg: 43U }, |
| 3853 | { .FromReg: RISCV::F12_Q, .ToReg: 44U }, |
| 3854 | { .FromReg: RISCV::F13_Q, .ToReg: 45U }, |
| 3855 | { .FromReg: RISCV::F14_Q, .ToReg: 46U }, |
| 3856 | { .FromReg: RISCV::F15_Q, .ToReg: 47U }, |
| 3857 | { .FromReg: RISCV::F16_Q, .ToReg: 48U }, |
| 3858 | { .FromReg: RISCV::F17_Q, .ToReg: 49U }, |
| 3859 | { .FromReg: RISCV::F18_Q, .ToReg: 50U }, |
| 3860 | { .FromReg: RISCV::F19_Q, .ToReg: 51U }, |
| 3861 | { .FromReg: RISCV::F20_Q, .ToReg: 52U }, |
| 3862 | { .FromReg: RISCV::F21_Q, .ToReg: 53U }, |
| 3863 | { .FromReg: RISCV::F22_Q, .ToReg: 54U }, |
| 3864 | { .FromReg: RISCV::F23_Q, .ToReg: 55U }, |
| 3865 | { .FromReg: RISCV::F24_Q, .ToReg: 56U }, |
| 3866 | { .FromReg: RISCV::F25_Q, .ToReg: 57U }, |
| 3867 | { .FromReg: RISCV::F26_Q, .ToReg: 58U }, |
| 3868 | { .FromReg: RISCV::F27_Q, .ToReg: 59U }, |
| 3869 | { .FromReg: RISCV::F28_Q, .ToReg: 60U }, |
| 3870 | { .FromReg: RISCV::F29_Q, .ToReg: 61U }, |
| 3871 | { .FromReg: RISCV::F30_Q, .ToReg: 62U }, |
| 3872 | { .FromReg: RISCV::F31_Q, .ToReg: 63U }, |
| 3873 | { .FromReg: RISCV::X0_Y, .ToReg: 0U }, |
| 3874 | { .FromReg: RISCV::X1_Y, .ToReg: 1U }, |
| 3875 | { .FromReg: RISCV::X2_Y, .ToReg: 2U }, |
| 3876 | { .FromReg: RISCV::X3_Y, .ToReg: 3U }, |
| 3877 | { .FromReg: RISCV::X4_Y, .ToReg: 4U }, |
| 3878 | { .FromReg: RISCV::X5_Y, .ToReg: 5U }, |
| 3879 | { .FromReg: RISCV::X6_Y, .ToReg: 6U }, |
| 3880 | { .FromReg: RISCV::X7_Y, .ToReg: 7U }, |
| 3881 | { .FromReg: RISCV::X8_Y, .ToReg: 8U }, |
| 3882 | { .FromReg: RISCV::X9_Y, .ToReg: 9U }, |
| 3883 | { .FromReg: RISCV::X10_Y, .ToReg: 0U }, |
| 3884 | { .FromReg: RISCV::X11_Y, .ToReg: 1U }, |
| 3885 | { .FromReg: RISCV::X12_Y, .ToReg: 2U }, |
| 3886 | { .FromReg: RISCV::X13_Y, .ToReg: 3U }, |
| 3887 | { .FromReg: RISCV::X14_Y, .ToReg: 4U }, |
| 3888 | { .FromReg: RISCV::X15_Y, .ToReg: 5U }, |
| 3889 | { .FromReg: RISCV::X16_Y, .ToReg: 16U }, |
| 3890 | { .FromReg: RISCV::X17_Y, .ToReg: 17U }, |
| 3891 | { .FromReg: RISCV::X18_Y, .ToReg: 18U }, |
| 3892 | { .FromReg: RISCV::X19_Y, .ToReg: 19U }, |
| 3893 | { .FromReg: RISCV::X20_Y, .ToReg: 20U }, |
| 3894 | { .FromReg: RISCV::X21_Y, .ToReg: 21U }, |
| 3895 | { .FromReg: RISCV::X22_Y, .ToReg: 22U }, |
| 3896 | { .FromReg: RISCV::X23_Y, .ToReg: 23U }, |
| 3897 | { .FromReg: RISCV::X24_Y, .ToReg: 24U }, |
| 3898 | { .FromReg: RISCV::X25_Y, .ToReg: 25U }, |
| 3899 | { .FromReg: RISCV::X26_Y, .ToReg: 26U }, |
| 3900 | { .FromReg: RISCV::X27_Y, .ToReg: 27U }, |
| 3901 | { .FromReg: RISCV::X28_Y, .ToReg: 28U }, |
| 3902 | { .FromReg: RISCV::X29_Y, .ToReg: 29U }, |
| 3903 | { .FromReg: RISCV::X30_Y, .ToReg: 30U }, |
| 3904 | { .FromReg: RISCV::X31_Y, .ToReg: 31U }, |
| 3905 | { .FromReg: RISCV::F0_Q2, .ToReg: 3088U }, |
| 3906 | { .FromReg: RISCV::F1_Q2, .ToReg: 3089U }, |
| 3907 | { .FromReg: RISCV::F2_Q2, .ToReg: 3090U }, |
| 3908 | { .FromReg: RISCV::F3_Q2, .ToReg: 3091U }, |
| 3909 | { .FromReg: RISCV::F4_Q2, .ToReg: 3092U }, |
| 3910 | { .FromReg: RISCV::F5_Q2, .ToReg: 3093U }, |
| 3911 | { .FromReg: RISCV::F6_Q2, .ToReg: 3094U }, |
| 3912 | { .FromReg: RISCV::F7_Q2, .ToReg: 3095U }, |
| 3913 | { .FromReg: RISCV::F8_Q2, .ToReg: 3096U }, |
| 3914 | { .FromReg: RISCV::F9_Q2, .ToReg: 3097U }, |
| 3915 | { .FromReg: RISCV::F10_Q2, .ToReg: 3098U }, |
| 3916 | { .FromReg: RISCV::F11_Q2, .ToReg: 3099U }, |
| 3917 | { .FromReg: RISCV::F12_Q2, .ToReg: 3100U }, |
| 3918 | { .FromReg: RISCV::F13_Q2, .ToReg: 3101U }, |
| 3919 | { .FromReg: RISCV::F14_Q2, .ToReg: 3102U }, |
| 3920 | { .FromReg: RISCV::F15_Q2, .ToReg: 3103U }, |
| 3921 | { .FromReg: RISCV::F16_Q2, .ToReg: 3104U }, |
| 3922 | { .FromReg: RISCV::F17_Q2, .ToReg: 3105U }, |
| 3923 | { .FromReg: RISCV::F18_Q2, .ToReg: 3106U }, |
| 3924 | { .FromReg: RISCV::F19_Q2, .ToReg: 3107U }, |
| 3925 | { .FromReg: RISCV::F20_Q2, .ToReg: 3108U }, |
| 3926 | { .FromReg: RISCV::F21_Q2, .ToReg: 3109U }, |
| 3927 | { .FromReg: RISCV::F22_Q2, .ToReg: 3110U }, |
| 3928 | { .FromReg: RISCV::F23_Q2, .ToReg: 3111U }, |
| 3929 | { .FromReg: RISCV::F24_Q2, .ToReg: 3112U }, |
| 3930 | { .FromReg: RISCV::F25_Q2, .ToReg: 3113U }, |
| 3931 | { .FromReg: RISCV::F26_Q2, .ToReg: 3114U }, |
| 3932 | { .FromReg: RISCV::F27_Q2, .ToReg: 3115U }, |
| 3933 | { .FromReg: RISCV::F28_Q2, .ToReg: 3116U }, |
| 3934 | { .FromReg: RISCV::F29_Q2, .ToReg: 3117U }, |
| 3935 | { .FromReg: RISCV::F30_Q2, .ToReg: 3118U }, |
| 3936 | { .FromReg: RISCV::F31_Q2, .ToReg: 3119U }, |
| 3937 | { .FromReg: RISCV::V0M2, .ToReg: 96U }, |
| 3938 | { .FromReg: RISCV::V0M4, .ToReg: 96U }, |
| 3939 | { .FromReg: RISCV::V0M8, .ToReg: 96U }, |
| 3940 | { .FromReg: RISCV::V2M2, .ToReg: 98U }, |
| 3941 | { .FromReg: RISCV::V4M2, .ToReg: 100U }, |
| 3942 | { .FromReg: RISCV::V4M4, .ToReg: 100U }, |
| 3943 | { .FromReg: RISCV::V6M2, .ToReg: 102U }, |
| 3944 | { .FromReg: RISCV::V8M2, .ToReg: 104U }, |
| 3945 | { .FromReg: RISCV::V8M4, .ToReg: 104U }, |
| 3946 | { .FromReg: RISCV::V8M8, .ToReg: 104U }, |
| 3947 | { .FromReg: RISCV::V10M2, .ToReg: 106U }, |
| 3948 | { .FromReg: RISCV::V12M2, .ToReg: 108U }, |
| 3949 | { .FromReg: RISCV::V12M4, .ToReg: 108U }, |
| 3950 | { .FromReg: RISCV::V14M2, .ToReg: 110U }, |
| 3951 | { .FromReg: RISCV::V16M2, .ToReg: 112U }, |
| 3952 | { .FromReg: RISCV::V16M4, .ToReg: 112U }, |
| 3953 | { .FromReg: RISCV::V16M8, .ToReg: 112U }, |
| 3954 | { .FromReg: RISCV::V18M2, .ToReg: 114U }, |
| 3955 | { .FromReg: RISCV::V20M2, .ToReg: 116U }, |
| 3956 | { .FromReg: RISCV::V20M4, .ToReg: 116U }, |
| 3957 | { .FromReg: RISCV::V22M2, .ToReg: 118U }, |
| 3958 | { .FromReg: RISCV::V24M2, .ToReg: 120U }, |
| 3959 | { .FromReg: RISCV::V24M4, .ToReg: 120U }, |
| 3960 | { .FromReg: RISCV::V24M8, .ToReg: 120U }, |
| 3961 | { .FromReg: RISCV::V26M2, .ToReg: 122U }, |
| 3962 | { .FromReg: RISCV::V28M2, .ToReg: 124U }, |
| 3963 | { .FromReg: RISCV::V28M4, .ToReg: 124U }, |
| 3964 | { .FromReg: RISCV::V30M2, .ToReg: 126U }, |
| 3965 | }; |
| 3966 | extern const unsigned RISCVDwarfFlavour0L2DwarfSize = std::size(RISCVDwarfFlavour0L2Dwarf); |
| 3967 | |
| 3968 | extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[] = { |
| 3969 | { .FromReg: RISCV::VLENB, .ToReg: 7202U }, |
| 3970 | { .FromReg: RISCV::M0, .ToReg: 4020U }, |
| 3971 | { .FromReg: RISCV::M1, .ToReg: 4021U }, |
| 3972 | { .FromReg: RISCV::M2, .ToReg: 4022U }, |
| 3973 | { .FromReg: RISCV::M3, .ToReg: 4023U }, |
| 3974 | { .FromReg: RISCV::M4, .ToReg: 4024U }, |
| 3975 | { .FromReg: RISCV::M5, .ToReg: 4025U }, |
| 3976 | { .FromReg: RISCV::M6, .ToReg: 4026U }, |
| 3977 | { .FromReg: RISCV::M7, .ToReg: 4027U }, |
| 3978 | { .FromReg: RISCV::T0, .ToReg: 3072U }, |
| 3979 | { .FromReg: RISCV::T1, .ToReg: 3073U }, |
| 3980 | { .FromReg: RISCV::T2, .ToReg: 3074U }, |
| 3981 | { .FromReg: RISCV::T3, .ToReg: 3075U }, |
| 3982 | { .FromReg: RISCV::T4, .ToReg: 3076U }, |
| 3983 | { .FromReg: RISCV::T5, .ToReg: 3077U }, |
| 3984 | { .FromReg: RISCV::T6, .ToReg: 3078U }, |
| 3985 | { .FromReg: RISCV::T7, .ToReg: 3079U }, |
| 3986 | { .FromReg: RISCV::T8, .ToReg: 3080U }, |
| 3987 | { .FromReg: RISCV::T9, .ToReg: 3081U }, |
| 3988 | { .FromReg: RISCV::T10, .ToReg: 3082U }, |
| 3989 | { .FromReg: RISCV::T11, .ToReg: 3083U }, |
| 3990 | { .FromReg: RISCV::T12, .ToReg: 3084U }, |
| 3991 | { .FromReg: RISCV::T13, .ToReg: 3085U }, |
| 3992 | { .FromReg: RISCV::T14, .ToReg: 3086U }, |
| 3993 | { .FromReg: RISCV::T15, .ToReg: 3087U }, |
| 3994 | { .FromReg: RISCV::V0, .ToReg: 96U }, |
| 3995 | { .FromReg: RISCV::V1, .ToReg: 97U }, |
| 3996 | { .FromReg: RISCV::V2, .ToReg: 98U }, |
| 3997 | { .FromReg: RISCV::V3, .ToReg: 99U }, |
| 3998 | { .FromReg: RISCV::V4, .ToReg: 100U }, |
| 3999 | { .FromReg: RISCV::V5, .ToReg: 101U }, |
| 4000 | { .FromReg: RISCV::V6, .ToReg: 102U }, |
| 4001 | { .FromReg: RISCV::V7, .ToReg: 103U }, |
| 4002 | { .FromReg: RISCV::V8, .ToReg: 104U }, |
| 4003 | { .FromReg: RISCV::V9, .ToReg: 105U }, |
| 4004 | { .FromReg: RISCV::V10, .ToReg: 106U }, |
| 4005 | { .FromReg: RISCV::V11, .ToReg: 107U }, |
| 4006 | { .FromReg: RISCV::V12, .ToReg: 108U }, |
| 4007 | { .FromReg: RISCV::V13, .ToReg: 109U }, |
| 4008 | { .FromReg: RISCV::V14, .ToReg: 110U }, |
| 4009 | { .FromReg: RISCV::V15, .ToReg: 111U }, |
| 4010 | { .FromReg: RISCV::V16, .ToReg: 112U }, |
| 4011 | { .FromReg: RISCV::V17, .ToReg: 113U }, |
| 4012 | { .FromReg: RISCV::V18, .ToReg: 114U }, |
| 4013 | { .FromReg: RISCV::V19, .ToReg: 115U }, |
| 4014 | { .FromReg: RISCV::V20, .ToReg: 116U }, |
| 4015 | { .FromReg: RISCV::V21, .ToReg: 117U }, |
| 4016 | { .FromReg: RISCV::V22, .ToReg: 118U }, |
| 4017 | { .FromReg: RISCV::V23, .ToReg: 119U }, |
| 4018 | { .FromReg: RISCV::V24, .ToReg: 120U }, |
| 4019 | { .FromReg: RISCV::V25, .ToReg: 121U }, |
| 4020 | { .FromReg: RISCV::V26, .ToReg: 122U }, |
| 4021 | { .FromReg: RISCV::V27, .ToReg: 123U }, |
| 4022 | { .FromReg: RISCV::V28, .ToReg: 124U }, |
| 4023 | { .FromReg: RISCV::V29, .ToReg: 125U }, |
| 4024 | { .FromReg: RISCV::V30, .ToReg: 126U }, |
| 4025 | { .FromReg: RISCV::V31, .ToReg: 127U }, |
| 4026 | { .FromReg: RISCV::X0, .ToReg: 0U }, |
| 4027 | { .FromReg: RISCV::X1, .ToReg: 1U }, |
| 4028 | { .FromReg: RISCV::X2, .ToReg: 2U }, |
| 4029 | { .FromReg: RISCV::X3, .ToReg: 3U }, |
| 4030 | { .FromReg: RISCV::X4, .ToReg: 4U }, |
| 4031 | { .FromReg: RISCV::X5, .ToReg: 5U }, |
| 4032 | { .FromReg: RISCV::X6, .ToReg: 6U }, |
| 4033 | { .FromReg: RISCV::X7, .ToReg: 7U }, |
| 4034 | { .FromReg: RISCV::X8, .ToReg: 8U }, |
| 4035 | { .FromReg: RISCV::X9, .ToReg: 9U }, |
| 4036 | { .FromReg: RISCV::X10, .ToReg: 10U }, |
| 4037 | { .FromReg: RISCV::X11, .ToReg: 11U }, |
| 4038 | { .FromReg: RISCV::X12, .ToReg: 12U }, |
| 4039 | { .FromReg: RISCV::X13, .ToReg: 13U }, |
| 4040 | { .FromReg: RISCV::X14, .ToReg: 14U }, |
| 4041 | { .FromReg: RISCV::X15, .ToReg: 15U }, |
| 4042 | { .FromReg: RISCV::X16, .ToReg: 16U }, |
| 4043 | { .FromReg: RISCV::X17, .ToReg: 17U }, |
| 4044 | { .FromReg: RISCV::X18, .ToReg: 18U }, |
| 4045 | { .FromReg: RISCV::X19, .ToReg: 19U }, |
| 4046 | { .FromReg: RISCV::X20, .ToReg: 20U }, |
| 4047 | { .FromReg: RISCV::X21, .ToReg: 21U }, |
| 4048 | { .FromReg: RISCV::X22, .ToReg: 22U }, |
| 4049 | { .FromReg: RISCV::X23, .ToReg: 23U }, |
| 4050 | { .FromReg: RISCV::X24, .ToReg: 24U }, |
| 4051 | { .FromReg: RISCV::X25, .ToReg: 25U }, |
| 4052 | { .FromReg: RISCV::X26, .ToReg: 26U }, |
| 4053 | { .FromReg: RISCV::X27, .ToReg: 27U }, |
| 4054 | { .FromReg: RISCV::X28, .ToReg: 28U }, |
| 4055 | { .FromReg: RISCV::X29, .ToReg: 29U }, |
| 4056 | { .FromReg: RISCV::X30, .ToReg: 30U }, |
| 4057 | { .FromReg: RISCV::X31, .ToReg: 31U }, |
| 4058 | { .FromReg: RISCV::F0_D, .ToReg: 32U }, |
| 4059 | { .FromReg: RISCV::F1_D, .ToReg: 33U }, |
| 4060 | { .FromReg: RISCV::F2_D, .ToReg: 34U }, |
| 4061 | { .FromReg: RISCV::F3_D, .ToReg: 35U }, |
| 4062 | { .FromReg: RISCV::F4_D, .ToReg: 36U }, |
| 4063 | { .FromReg: RISCV::F5_D, .ToReg: 37U }, |
| 4064 | { .FromReg: RISCV::F6_D, .ToReg: 38U }, |
| 4065 | { .FromReg: RISCV::F7_D, .ToReg: 39U }, |
| 4066 | { .FromReg: RISCV::F8_D, .ToReg: 40U }, |
| 4067 | { .FromReg: RISCV::F9_D, .ToReg: 41U }, |
| 4068 | { .FromReg: RISCV::F10_D, .ToReg: 42U }, |
| 4069 | { .FromReg: RISCV::F11_D, .ToReg: 43U }, |
| 4070 | { .FromReg: RISCV::F12_D, .ToReg: 44U }, |
| 4071 | { .FromReg: RISCV::F13_D, .ToReg: 45U }, |
| 4072 | { .FromReg: RISCV::F14_D, .ToReg: 46U }, |
| 4073 | { .FromReg: RISCV::F15_D, .ToReg: 47U }, |
| 4074 | { .FromReg: RISCV::F16_D, .ToReg: 48U }, |
| 4075 | { .FromReg: RISCV::F17_D, .ToReg: 49U }, |
| 4076 | { .FromReg: RISCV::F18_D, .ToReg: 50U }, |
| 4077 | { .FromReg: RISCV::F19_D, .ToReg: 51U }, |
| 4078 | { .FromReg: RISCV::F20_D, .ToReg: 52U }, |
| 4079 | { .FromReg: RISCV::F21_D, .ToReg: 53U }, |
| 4080 | { .FromReg: RISCV::F22_D, .ToReg: 54U }, |
| 4081 | { .FromReg: RISCV::F23_D, .ToReg: 55U }, |
| 4082 | { .FromReg: RISCV::F24_D, .ToReg: 56U }, |
| 4083 | { .FromReg: RISCV::F25_D, .ToReg: 57U }, |
| 4084 | { .FromReg: RISCV::F26_D, .ToReg: 58U }, |
| 4085 | { .FromReg: RISCV::F27_D, .ToReg: 59U }, |
| 4086 | { .FromReg: RISCV::F28_D, .ToReg: 60U }, |
| 4087 | { .FromReg: RISCV::F29_D, .ToReg: 61U }, |
| 4088 | { .FromReg: RISCV::F30_D, .ToReg: 62U }, |
| 4089 | { .FromReg: RISCV::F31_D, .ToReg: 63U }, |
| 4090 | { .FromReg: RISCV::F0_F, .ToReg: 32U }, |
| 4091 | { .FromReg: RISCV::F1_F, .ToReg: 33U }, |
| 4092 | { .FromReg: RISCV::F2_F, .ToReg: 34U }, |
| 4093 | { .FromReg: RISCV::F3_F, .ToReg: 35U }, |
| 4094 | { .FromReg: RISCV::F4_F, .ToReg: 36U }, |
| 4095 | { .FromReg: RISCV::F5_F, .ToReg: 37U }, |
| 4096 | { .FromReg: RISCV::F6_F, .ToReg: 38U }, |
| 4097 | { .FromReg: RISCV::F7_F, .ToReg: 39U }, |
| 4098 | { .FromReg: RISCV::F8_F, .ToReg: 40U }, |
| 4099 | { .FromReg: RISCV::F9_F, .ToReg: 41U }, |
| 4100 | { .FromReg: RISCV::F10_F, .ToReg: 42U }, |
| 4101 | { .FromReg: RISCV::F11_F, .ToReg: 43U }, |
| 4102 | { .FromReg: RISCV::F12_F, .ToReg: 44U }, |
| 4103 | { .FromReg: RISCV::F13_F, .ToReg: 45U }, |
| 4104 | { .FromReg: RISCV::F14_F, .ToReg: 46U }, |
| 4105 | { .FromReg: RISCV::F15_F, .ToReg: 47U }, |
| 4106 | { .FromReg: RISCV::F16_F, .ToReg: 48U }, |
| 4107 | { .FromReg: RISCV::F17_F, .ToReg: 49U }, |
| 4108 | { .FromReg: RISCV::F18_F, .ToReg: 50U }, |
| 4109 | { .FromReg: RISCV::F19_F, .ToReg: 51U }, |
| 4110 | { .FromReg: RISCV::F20_F, .ToReg: 52U }, |
| 4111 | { .FromReg: RISCV::F21_F, .ToReg: 53U }, |
| 4112 | { .FromReg: RISCV::F22_F, .ToReg: 54U }, |
| 4113 | { .FromReg: RISCV::F23_F, .ToReg: 55U }, |
| 4114 | { .FromReg: RISCV::F24_F, .ToReg: 56U }, |
| 4115 | { .FromReg: RISCV::F25_F, .ToReg: 57U }, |
| 4116 | { .FromReg: RISCV::F26_F, .ToReg: 58U }, |
| 4117 | { .FromReg: RISCV::F27_F, .ToReg: 59U }, |
| 4118 | { .FromReg: RISCV::F28_F, .ToReg: 60U }, |
| 4119 | { .FromReg: RISCV::F29_F, .ToReg: 61U }, |
| 4120 | { .FromReg: RISCV::F30_F, .ToReg: 62U }, |
| 4121 | { .FromReg: RISCV::F31_F, .ToReg: 63U }, |
| 4122 | { .FromReg: RISCV::F0_H, .ToReg: 32U }, |
| 4123 | { .FromReg: RISCV::F1_H, .ToReg: 33U }, |
| 4124 | { .FromReg: RISCV::F2_H, .ToReg: 34U }, |
| 4125 | { .FromReg: RISCV::F3_H, .ToReg: 35U }, |
| 4126 | { .FromReg: RISCV::F4_H, .ToReg: 36U }, |
| 4127 | { .FromReg: RISCV::F5_H, .ToReg: 37U }, |
| 4128 | { .FromReg: RISCV::F6_H, .ToReg: 38U }, |
| 4129 | { .FromReg: RISCV::F7_H, .ToReg: 39U }, |
| 4130 | { .FromReg: RISCV::F8_H, .ToReg: 40U }, |
| 4131 | { .FromReg: RISCV::F9_H, .ToReg: 41U }, |
| 4132 | { .FromReg: RISCV::F10_H, .ToReg: 42U }, |
| 4133 | { .FromReg: RISCV::F11_H, .ToReg: 43U }, |
| 4134 | { .FromReg: RISCV::F12_H, .ToReg: 44U }, |
| 4135 | { .FromReg: RISCV::F13_H, .ToReg: 45U }, |
| 4136 | { .FromReg: RISCV::F14_H, .ToReg: 46U }, |
| 4137 | { .FromReg: RISCV::F15_H, .ToReg: 47U }, |
| 4138 | { .FromReg: RISCV::F16_H, .ToReg: 48U }, |
| 4139 | { .FromReg: RISCV::F17_H, .ToReg: 49U }, |
| 4140 | { .FromReg: RISCV::F18_H, .ToReg: 50U }, |
| 4141 | { .FromReg: RISCV::F19_H, .ToReg: 51U }, |
| 4142 | { .FromReg: RISCV::F20_H, .ToReg: 52U }, |
| 4143 | { .FromReg: RISCV::F21_H, .ToReg: 53U }, |
| 4144 | { .FromReg: RISCV::F22_H, .ToReg: 54U }, |
| 4145 | { .FromReg: RISCV::F23_H, .ToReg: 55U }, |
| 4146 | { .FromReg: RISCV::F24_H, .ToReg: 56U }, |
| 4147 | { .FromReg: RISCV::F25_H, .ToReg: 57U }, |
| 4148 | { .FromReg: RISCV::F26_H, .ToReg: 58U }, |
| 4149 | { .FromReg: RISCV::F27_H, .ToReg: 59U }, |
| 4150 | { .FromReg: RISCV::F28_H, .ToReg: 60U }, |
| 4151 | { .FromReg: RISCV::F29_H, .ToReg: 61U }, |
| 4152 | { .FromReg: RISCV::F30_H, .ToReg: 62U }, |
| 4153 | { .FromReg: RISCV::F31_H, .ToReg: 63U }, |
| 4154 | { .FromReg: RISCV::F0_Q, .ToReg: 32U }, |
| 4155 | { .FromReg: RISCV::F1_Q, .ToReg: 33U }, |
| 4156 | { .FromReg: RISCV::F2_Q, .ToReg: 34U }, |
| 4157 | { .FromReg: RISCV::F3_Q, .ToReg: 35U }, |
| 4158 | { .FromReg: RISCV::F4_Q, .ToReg: 36U }, |
| 4159 | { .FromReg: RISCV::F5_Q, .ToReg: 37U }, |
| 4160 | { .FromReg: RISCV::F6_Q, .ToReg: 38U }, |
| 4161 | { .FromReg: RISCV::F7_Q, .ToReg: 39U }, |
| 4162 | { .FromReg: RISCV::F8_Q, .ToReg: 40U }, |
| 4163 | { .FromReg: RISCV::F9_Q, .ToReg: 41U }, |
| 4164 | { .FromReg: RISCV::F10_Q, .ToReg: 42U }, |
| 4165 | { .FromReg: RISCV::F11_Q, .ToReg: 43U }, |
| 4166 | { .FromReg: RISCV::F12_Q, .ToReg: 44U }, |
| 4167 | { .FromReg: RISCV::F13_Q, .ToReg: 45U }, |
| 4168 | { .FromReg: RISCV::F14_Q, .ToReg: 46U }, |
| 4169 | { .FromReg: RISCV::F15_Q, .ToReg: 47U }, |
| 4170 | { .FromReg: RISCV::F16_Q, .ToReg: 48U }, |
| 4171 | { .FromReg: RISCV::F17_Q, .ToReg: 49U }, |
| 4172 | { .FromReg: RISCV::F18_Q, .ToReg: 50U }, |
| 4173 | { .FromReg: RISCV::F19_Q, .ToReg: 51U }, |
| 4174 | { .FromReg: RISCV::F20_Q, .ToReg: 52U }, |
| 4175 | { .FromReg: RISCV::F21_Q, .ToReg: 53U }, |
| 4176 | { .FromReg: RISCV::F22_Q, .ToReg: 54U }, |
| 4177 | { .FromReg: RISCV::F23_Q, .ToReg: 55U }, |
| 4178 | { .FromReg: RISCV::F24_Q, .ToReg: 56U }, |
| 4179 | { .FromReg: RISCV::F25_Q, .ToReg: 57U }, |
| 4180 | { .FromReg: RISCV::F26_Q, .ToReg: 58U }, |
| 4181 | { .FromReg: RISCV::F27_Q, .ToReg: 59U }, |
| 4182 | { .FromReg: RISCV::F28_Q, .ToReg: 60U }, |
| 4183 | { .FromReg: RISCV::F29_Q, .ToReg: 61U }, |
| 4184 | { .FromReg: RISCV::F30_Q, .ToReg: 62U }, |
| 4185 | { .FromReg: RISCV::F31_Q, .ToReg: 63U }, |
| 4186 | { .FromReg: RISCV::X0_Y, .ToReg: 0U }, |
| 4187 | { .FromReg: RISCV::X1_Y, .ToReg: 1U }, |
| 4188 | { .FromReg: RISCV::X2_Y, .ToReg: 2U }, |
| 4189 | { .FromReg: RISCV::X3_Y, .ToReg: 3U }, |
| 4190 | { .FromReg: RISCV::X4_Y, .ToReg: 4U }, |
| 4191 | { .FromReg: RISCV::X5_Y, .ToReg: 5U }, |
| 4192 | { .FromReg: RISCV::X6_Y, .ToReg: 6U }, |
| 4193 | { .FromReg: RISCV::X7_Y, .ToReg: 7U }, |
| 4194 | { .FromReg: RISCV::X8_Y, .ToReg: 8U }, |
| 4195 | { .FromReg: RISCV::X9_Y, .ToReg: 9U }, |
| 4196 | { .FromReg: RISCV::X10_Y, .ToReg: 0U }, |
| 4197 | { .FromReg: RISCV::X11_Y, .ToReg: 1U }, |
| 4198 | { .FromReg: RISCV::X12_Y, .ToReg: 2U }, |
| 4199 | { .FromReg: RISCV::X13_Y, .ToReg: 3U }, |
| 4200 | { .FromReg: RISCV::X14_Y, .ToReg: 4U }, |
| 4201 | { .FromReg: RISCV::X15_Y, .ToReg: 5U }, |
| 4202 | { .FromReg: RISCV::X16_Y, .ToReg: 16U }, |
| 4203 | { .FromReg: RISCV::X17_Y, .ToReg: 17U }, |
| 4204 | { .FromReg: RISCV::X18_Y, .ToReg: 18U }, |
| 4205 | { .FromReg: RISCV::X19_Y, .ToReg: 19U }, |
| 4206 | { .FromReg: RISCV::X20_Y, .ToReg: 20U }, |
| 4207 | { .FromReg: RISCV::X21_Y, .ToReg: 21U }, |
| 4208 | { .FromReg: RISCV::X22_Y, .ToReg: 22U }, |
| 4209 | { .FromReg: RISCV::X23_Y, .ToReg: 23U }, |
| 4210 | { .FromReg: RISCV::X24_Y, .ToReg: 24U }, |
| 4211 | { .FromReg: RISCV::X25_Y, .ToReg: 25U }, |
| 4212 | { .FromReg: RISCV::X26_Y, .ToReg: 26U }, |
| 4213 | { .FromReg: RISCV::X27_Y, .ToReg: 27U }, |
| 4214 | { .FromReg: RISCV::X28_Y, .ToReg: 28U }, |
| 4215 | { .FromReg: RISCV::X29_Y, .ToReg: 29U }, |
| 4216 | { .FromReg: RISCV::X30_Y, .ToReg: 30U }, |
| 4217 | { .FromReg: RISCV::X31_Y, .ToReg: 31U }, |
| 4218 | { .FromReg: RISCV::F0_Q2, .ToReg: 3088U }, |
| 4219 | { .FromReg: RISCV::F1_Q2, .ToReg: 3089U }, |
| 4220 | { .FromReg: RISCV::F2_Q2, .ToReg: 3090U }, |
| 4221 | { .FromReg: RISCV::F3_Q2, .ToReg: 3091U }, |
| 4222 | { .FromReg: RISCV::F4_Q2, .ToReg: 3092U }, |
| 4223 | { .FromReg: RISCV::F5_Q2, .ToReg: 3093U }, |
| 4224 | { .FromReg: RISCV::F6_Q2, .ToReg: 3094U }, |
| 4225 | { .FromReg: RISCV::F7_Q2, .ToReg: 3095U }, |
| 4226 | { .FromReg: RISCV::F8_Q2, .ToReg: 3096U }, |
| 4227 | { .FromReg: RISCV::F9_Q2, .ToReg: 3097U }, |
| 4228 | { .FromReg: RISCV::F10_Q2, .ToReg: 3098U }, |
| 4229 | { .FromReg: RISCV::F11_Q2, .ToReg: 3099U }, |
| 4230 | { .FromReg: RISCV::F12_Q2, .ToReg: 3100U }, |
| 4231 | { .FromReg: RISCV::F13_Q2, .ToReg: 3101U }, |
| 4232 | { .FromReg: RISCV::F14_Q2, .ToReg: 3102U }, |
| 4233 | { .FromReg: RISCV::F15_Q2, .ToReg: 3103U }, |
| 4234 | { .FromReg: RISCV::F16_Q2, .ToReg: 3104U }, |
| 4235 | { .FromReg: RISCV::F17_Q2, .ToReg: 3105U }, |
| 4236 | { .FromReg: RISCV::F18_Q2, .ToReg: 3106U }, |
| 4237 | { .FromReg: RISCV::F19_Q2, .ToReg: 3107U }, |
| 4238 | { .FromReg: RISCV::F20_Q2, .ToReg: 3108U }, |
| 4239 | { .FromReg: RISCV::F21_Q2, .ToReg: 3109U }, |
| 4240 | { .FromReg: RISCV::F22_Q2, .ToReg: 3110U }, |
| 4241 | { .FromReg: RISCV::F23_Q2, .ToReg: 3111U }, |
| 4242 | { .FromReg: RISCV::F24_Q2, .ToReg: 3112U }, |
| 4243 | { .FromReg: RISCV::F25_Q2, .ToReg: 3113U }, |
| 4244 | { .FromReg: RISCV::F26_Q2, .ToReg: 3114U }, |
| 4245 | { .FromReg: RISCV::F27_Q2, .ToReg: 3115U }, |
| 4246 | { .FromReg: RISCV::F28_Q2, .ToReg: 3116U }, |
| 4247 | { .FromReg: RISCV::F29_Q2, .ToReg: 3117U }, |
| 4248 | { .FromReg: RISCV::F30_Q2, .ToReg: 3118U }, |
| 4249 | { .FromReg: RISCV::F31_Q2, .ToReg: 3119U }, |
| 4250 | { .FromReg: RISCV::V0M2, .ToReg: 96U }, |
| 4251 | { .FromReg: RISCV::V0M4, .ToReg: 96U }, |
| 4252 | { .FromReg: RISCV::V0M8, .ToReg: 96U }, |
| 4253 | { .FromReg: RISCV::V2M2, .ToReg: 98U }, |
| 4254 | { .FromReg: RISCV::V4M2, .ToReg: 100U }, |
| 4255 | { .FromReg: RISCV::V4M4, .ToReg: 100U }, |
| 4256 | { .FromReg: RISCV::V6M2, .ToReg: 102U }, |
| 4257 | { .FromReg: RISCV::V8M2, .ToReg: 104U }, |
| 4258 | { .FromReg: RISCV::V8M4, .ToReg: 104U }, |
| 4259 | { .FromReg: RISCV::V8M8, .ToReg: 104U }, |
| 4260 | { .FromReg: RISCV::V10M2, .ToReg: 106U }, |
| 4261 | { .FromReg: RISCV::V12M2, .ToReg: 108U }, |
| 4262 | { .FromReg: RISCV::V12M4, .ToReg: 108U }, |
| 4263 | { .FromReg: RISCV::V14M2, .ToReg: 110U }, |
| 4264 | { .FromReg: RISCV::V16M2, .ToReg: 112U }, |
| 4265 | { .FromReg: RISCV::V16M4, .ToReg: 112U }, |
| 4266 | { .FromReg: RISCV::V16M8, .ToReg: 112U }, |
| 4267 | { .FromReg: RISCV::V18M2, .ToReg: 114U }, |
| 4268 | { .FromReg: RISCV::V20M2, .ToReg: 116U }, |
| 4269 | { .FromReg: RISCV::V20M4, .ToReg: 116U }, |
| 4270 | { .FromReg: RISCV::V22M2, .ToReg: 118U }, |
| 4271 | { .FromReg: RISCV::V24M2, .ToReg: 120U }, |
| 4272 | { .FromReg: RISCV::V24M4, .ToReg: 120U }, |
| 4273 | { .FromReg: RISCV::V24M8, .ToReg: 120U }, |
| 4274 | { .FromReg: RISCV::V26M2, .ToReg: 122U }, |
| 4275 | { .FromReg: RISCV::V28M2, .ToReg: 124U }, |
| 4276 | { .FromReg: RISCV::V28M4, .ToReg: 124U }, |
| 4277 | { .FromReg: RISCV::V30M2, .ToReg: 126U }, |
| 4278 | }; |
| 4279 | extern const unsigned RISCVEHFlavour0L2DwarfSize = std::size(RISCVEHFlavour0L2Dwarf); |
| 4280 | |
| 4281 | extern const uint16_t RISCVRegEncodingTable[] = { |
| 4282 | 0, |
| 4283 | 0, |
| 4284 | 0, |
| 4285 | 0, |
| 4286 | 0, |
| 4287 | 0, |
| 4288 | 0, |
| 4289 | 0, |
| 4290 | 0, |
| 4291 | 0, |
| 4292 | 0, |
| 4293 | 0, |
| 4294 | 0, |
| 4295 | 1, |
| 4296 | 2, |
| 4297 | 3, |
| 4298 | 4, |
| 4299 | 5, |
| 4300 | 6, |
| 4301 | 7, |
| 4302 | 0, |
| 4303 | 1, |
| 4304 | 2, |
| 4305 | 3, |
| 4306 | 4, |
| 4307 | 5, |
| 4308 | 6, |
| 4309 | 7, |
| 4310 | 8, |
| 4311 | 9, |
| 4312 | 10, |
| 4313 | 11, |
| 4314 | 12, |
| 4315 | 13, |
| 4316 | 14, |
| 4317 | 15, |
| 4318 | 0, |
| 4319 | 1, |
| 4320 | 2, |
| 4321 | 3, |
| 4322 | 4, |
| 4323 | 5, |
| 4324 | 6, |
| 4325 | 7, |
| 4326 | 8, |
| 4327 | 9, |
| 4328 | 10, |
| 4329 | 11, |
| 4330 | 12, |
| 4331 | 13, |
| 4332 | 14, |
| 4333 | 15, |
| 4334 | 16, |
| 4335 | 17, |
| 4336 | 18, |
| 4337 | 19, |
| 4338 | 20, |
| 4339 | 21, |
| 4340 | 22, |
| 4341 | 23, |
| 4342 | 24, |
| 4343 | 25, |
| 4344 | 26, |
| 4345 | 27, |
| 4346 | 28, |
| 4347 | 29, |
| 4348 | 30, |
| 4349 | 31, |
| 4350 | 0, |
| 4351 | 1, |
| 4352 | 2, |
| 4353 | 3, |
| 4354 | 4, |
| 4355 | 5, |
| 4356 | 6, |
| 4357 | 7, |
| 4358 | 8, |
| 4359 | 9, |
| 4360 | 10, |
| 4361 | 11, |
| 4362 | 12, |
| 4363 | 13, |
| 4364 | 14, |
| 4365 | 15, |
| 4366 | 16, |
| 4367 | 17, |
| 4368 | 18, |
| 4369 | 19, |
| 4370 | 20, |
| 4371 | 21, |
| 4372 | 22, |
| 4373 | 23, |
| 4374 | 24, |
| 4375 | 25, |
| 4376 | 26, |
| 4377 | 27, |
| 4378 | 28, |
| 4379 | 29, |
| 4380 | 30, |
| 4381 | 31, |
| 4382 | 0, |
| 4383 | 1, |
| 4384 | 2, |
| 4385 | 3, |
| 4386 | 4, |
| 4387 | 5, |
| 4388 | 6, |
| 4389 | 7, |
| 4390 | 8, |
| 4391 | 9, |
| 4392 | 10, |
| 4393 | 11, |
| 4394 | 12, |
| 4395 | 13, |
| 4396 | 14, |
| 4397 | 15, |
| 4398 | 16, |
| 4399 | 17, |
| 4400 | 18, |
| 4401 | 19, |
| 4402 | 20, |
| 4403 | 21, |
| 4404 | 22, |
| 4405 | 23, |
| 4406 | 24, |
| 4407 | 25, |
| 4408 | 26, |
| 4409 | 27, |
| 4410 | 28, |
| 4411 | 29, |
| 4412 | 30, |
| 4413 | 31, |
| 4414 | 0, |
| 4415 | 1, |
| 4416 | 2, |
| 4417 | 3, |
| 4418 | 4, |
| 4419 | 5, |
| 4420 | 6, |
| 4421 | 7, |
| 4422 | 8, |
| 4423 | 9, |
| 4424 | 10, |
| 4425 | 11, |
| 4426 | 12, |
| 4427 | 13, |
| 4428 | 14, |
| 4429 | 15, |
| 4430 | 16, |
| 4431 | 17, |
| 4432 | 18, |
| 4433 | 19, |
| 4434 | 20, |
| 4435 | 21, |
| 4436 | 22, |
| 4437 | 23, |
| 4438 | 24, |
| 4439 | 25, |
| 4440 | 26, |
| 4441 | 27, |
| 4442 | 28, |
| 4443 | 29, |
| 4444 | 30, |
| 4445 | 31, |
| 4446 | 0, |
| 4447 | 1, |
| 4448 | 2, |
| 4449 | 3, |
| 4450 | 4, |
| 4451 | 5, |
| 4452 | 6, |
| 4453 | 7, |
| 4454 | 8, |
| 4455 | 9, |
| 4456 | 10, |
| 4457 | 11, |
| 4458 | 12, |
| 4459 | 13, |
| 4460 | 14, |
| 4461 | 15, |
| 4462 | 16, |
| 4463 | 17, |
| 4464 | 18, |
| 4465 | 19, |
| 4466 | 20, |
| 4467 | 21, |
| 4468 | 22, |
| 4469 | 23, |
| 4470 | 24, |
| 4471 | 25, |
| 4472 | 26, |
| 4473 | 27, |
| 4474 | 28, |
| 4475 | 29, |
| 4476 | 30, |
| 4477 | 31, |
| 4478 | 0, |
| 4479 | 1, |
| 4480 | 2, |
| 4481 | 3, |
| 4482 | 4, |
| 4483 | 5, |
| 4484 | 6, |
| 4485 | 7, |
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| 4925 | 24, |
| 4926 | 0, |
| 4927 | }; |
| 4928 | static inline void InitRISCVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
| 4929 | RI->InitMCRegisterInfo(D: RISCVRegDesc, NR: 645, RA, PC, C: RISCVMCRegisterClasses, NC: 151, RURoots: RISCVRegUnitRoots, NRU: 131, DL: RISCVRegDiffLists, RUMS: RISCVLaneMaskLists, Strings: RISCVRegStrings, ClassStrings: RISCVRegClassStrings, SubIndices: RISCVSubRegIdxLists, NumIndices: 58, |
| 4930 | RET: RISCVRegEncodingTable); |
| 4931 | |
| 4932 | switch (DwarfFlavour) { |
| 4933 | default: |
| 4934 | llvm_unreachable("Unknown DWARF flavour"); |
| 4935 | case 0: |
| 4936 | RI->mapDwarfRegsToLLVMRegs(Map: RISCVDwarfFlavour0Dwarf2L, Size: RISCVDwarfFlavour0Dwarf2LSize, isEH: false); |
| 4937 | break; |
| 4938 | } |
| 4939 | switch (EHFlavour) { |
| 4940 | default: |
| 4941 | llvm_unreachable("Unknown DWARF flavour"); |
| 4942 | case 0: |
| 4943 | RI->mapDwarfRegsToLLVMRegs(Map: RISCVEHFlavour0Dwarf2L, Size: RISCVEHFlavour0Dwarf2LSize, isEH: true); |
| 4944 | break; |
| 4945 | } |
| 4946 | switch (DwarfFlavour) { |
| 4947 | default: |
| 4948 | llvm_unreachable("Unknown DWARF flavour"); |
| 4949 | case 0: |
| 4950 | RI->mapLLVMRegsToDwarfRegs(Map: RISCVDwarfFlavour0L2Dwarf, Size: RISCVDwarfFlavour0L2DwarfSize, isEH: false); |
| 4951 | break; |
| 4952 | } |
| 4953 | switch (EHFlavour) { |
| 4954 | default: |
| 4955 | llvm_unreachable("Unknown DWARF flavour"); |
| 4956 | case 0: |
| 4957 | RI->mapLLVMRegsToDwarfRegs(Map: RISCVEHFlavour0L2Dwarf, Size: RISCVEHFlavour0L2DwarfSize, isEH: true); |
| 4958 | break; |
| 4959 | } |
| 4960 | } |
| 4961 | |
| 4962 | } // end namespace llvm |
| 4963 | |
| 4964 |
Generated while processing llvm_projects/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
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