1//===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This file provides RISC-V specific target descriptions.
10///
11//===----------------------------------------------------------------------===//
12
13#include "RISCVMCTargetDesc.h"
14#include "RISCVELFStreamer.h"
15#include "RISCVInstPrinter.h"
16#include "RISCVMCAsmInfo.h"
17#include "RISCVMCObjectFileInfo.h"
18#include "RISCVTargetStreamer.h"
19#include "TargetInfo/RISCVTargetInfo.h"
20#include "llvm/MC/MCAsmBackend.h"
21#include "llvm/MC/MCAsmInfo.h"
22#include "llvm/MC/MCCodeEmitter.h"
23#include "llvm/MC/MCInstrAnalysis.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCObjectFileInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/MC/TargetRegistry.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include <bitset>
35
36#define GET_INSTRINFO_MC_DESC
37#define ENABLE_INSTR_PREDICATE_VERIFIER
38#include "RISCVGenInstrInfo.inc"
39
40#define GET_REGINFO_MC_DESC
41#include "RISCVGenRegisterInfo.inc"
42
43#define GET_SUBTARGETINFO_MC_DESC
44#include "RISCVGenSubtargetInfo.inc"
45
46using namespace llvm;
47
48static MCInstrInfo *createRISCVMCInstrInfo() {
49 MCInstrInfo *X = new MCInstrInfo();
50 InitRISCVMCInstrInfo(II: X);
51 return X;
52}
53
54static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
55 MCRegisterInfo *X = new MCRegisterInfo();
56 InitRISCVMCRegisterInfo(RI: X, RA: RISCV::X1);
57 return X;
58}
59
60static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
61 const Triple &TT,
62 const MCTargetOptions &Options) {
63 MCAsmInfo *MAI = nullptr;
64 if (TT.isOSBinFormatELF())
65 MAI = new RISCVMCAsmInfo(TT);
66 else if (TT.isOSBinFormatMachO())
67 MAI = new RISCVMCAsmInfoDarwin();
68 else
69 reportFatalUsageError(reason: "unsupported object format");
70
71 unsigned SP = MRI.getDwarfRegNum(Reg: RISCV::X2, isEH: true);
72 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: SP, Offset: 0);
73 MAI->addInitialFrameState(Inst);
74
75 return MAI;
76}
77
78static MCObjectFileInfo *
79createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC,
80 bool LargeCodeModel = false) {
81 MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo();
82 MOFI->initMCObjectFileInfo(MCCtx&: Ctx, PIC, LargeCodeModel);
83 return MOFI;
84}
85
86static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
87 StringRef CPU, StringRef FS) {
88 if (CPU.empty() || CPU == "generic")
89 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
90
91 MCSubtargetInfo *X =
92 createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
93
94 // If the CPU is "help" fill in 64 or 32 bit feature so we can pass
95 // RISCVFeatures::validate.
96 // FIXME: Why does llvm-mc still expect a source file with -mcpu=help?
97 if (CPU == "help") {
98 llvm::FeatureBitset Features = X->getFeatureBits();
99 if (TT.isArch64Bit())
100 Features.set(RISCV::Feature64Bit);
101 else
102 Features.set(RISCV::Feature32Bit);
103 X->setFeatureBits(Features);
104 }
105
106 return X;
107}
108
109static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
110 unsigned SyntaxVariant,
111 const MCAsmInfo &MAI,
112 const MCInstrInfo &MII,
113 const MCRegisterInfo &MRI) {
114 return new RISCVInstPrinter(MAI, MII, MRI);
115}
116
117static MCTargetStreamer *
118createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
119 const Triple &TT = STI.getTargetTriple();
120 if (TT.isOSBinFormatELF())
121 return new RISCVTargetELFStreamer(S, STI);
122 return new RISCVTargetStreamer(S);
123}
124
125static MCStreamer *
126createMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
127 std::unique_ptr<MCObjectWriter> &&OW,
128 std::unique_ptr<MCCodeEmitter> &&Emitter) {
129 return createMachOStreamer(Ctx, TAB: std::move(TAB), OW: std::move(OW),
130 CE: std::move(Emitter),
131 /*DWARFMustBeAtTheEnd*/ false,
132 /*LabelSections*/ true);
133}
134
135static MCTargetStreamer *
136createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
137 MCInstPrinter *InstPrint) {
138 return new RISCVTargetAsmStreamer(S, OS);
139}
140
141static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
142 return new RISCVTargetStreamer(S);
143}
144
145namespace {
146
147class RISCVMCInstrAnalysis : public MCInstrAnalysis {
148 int64_t GPRState[31] = {};
149 std::bitset<31> GPRValidMask;
150
151 static bool isGPR(MCRegister Reg) {
152 return Reg >= RISCV::X0 && Reg <= RISCV::X31;
153 }
154 static bool isYGPR(MCRegister Reg) {
155 return Reg >= RISCV::X0_Y && Reg <= RISCV::X31_Y;
156 }
157 static bool isZeroReg(MCRegister Reg) {
158 return Reg == RISCV::X0 || Reg == RISCV::X0_Y;
159 }
160
161 static unsigned getRegIndex(MCRegister Reg) {
162 if (isYGPR(Reg)) {
163 assert(Reg != RISCV::X0_Y && "Invalid GPR reg");
164 return Reg - RISCV::X1_Y;
165 }
166 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");
167 return Reg - RISCV::X1;
168 }
169
170 void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {
171 if (isZeroReg(Reg))
172 return;
173
174 auto Index = getRegIndex(Reg);
175
176 if (Value) {
177 GPRState[Index] = *Value;
178 GPRValidMask.set(position: Index);
179 } else {
180 GPRValidMask.reset(position: Index);
181 }
182 }
183
184 std::optional<int64_t> getGPRState(MCRegister Reg) const {
185 if (isZeroReg(Reg))
186 return 0;
187
188 auto Index = getRegIndex(Reg);
189
190 if (GPRValidMask.test(position: Index))
191 return GPRState[Index];
192 return std::nullopt;
193 }
194
195public:
196 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
197 : MCInstrAnalysis(Info) {}
198
199 void resetState() override { GPRValidMask.reset(); }
200
201 void updateState(const MCInst &Inst, uint64_t Addr) override {
202 // Terminators mark the end of a basic block which means the sequentially
203 // next instruction will be the first of another basic block and the current
204 // state will typically not be valid anymore. For calls, we assume all
205 // registers may be clobbered by the callee (TODO: should we take the
206 // calling convention into account?).
207 if (isTerminator(Inst) || isCall(Inst)) {
208 resetState();
209 return;
210 }
211
212 switch (Inst.getOpcode()) {
213 default: {
214 // Clear the state of all defined registers for instructions that we don't
215 // explicitly support.
216 auto NumDefs = Info->get(Opcode: Inst.getOpcode()).getNumDefs();
217 for (unsigned I = 0; I < NumDefs; ++I) {
218 auto DefReg = Inst.getOperand(i: I).getReg();
219 if (isGPR(Reg: DefReg))
220 setGPRState(Reg: DefReg, Value: std::nullopt);
221 }
222 break;
223 }
224 case RISCV::AUIPC:
225 setGPRState(Reg: Inst.getOperand(i: 0).getReg(),
226 Value: Addr + SignExtend64<32>(x: Inst.getOperand(i: 1).getImm() << 12));
227 break;
228 }
229 }
230
231 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
232 uint64_t &Target) const override {
233 if (isConditionalBranch(Inst)) {
234 int64_t Imm;
235 if (Size == 2)
236 Imm = Inst.getOperand(i: 1).getImm();
237 else
238 Imm = Inst.getOperand(i: 2).getImm();
239 Target = Addr + Imm;
240 return true;
241 }
242
243 switch (Inst.getOpcode()) {
244 case RISCV::C_J:
245 case RISCV::C_JAL:
246 case RISCV::QC_E_J:
247 case RISCV::QC_E_JAL:
248 Target = Addr + Inst.getOperand(i: 0).getImm();
249 return true;
250 case RISCV::JAL:
251 Target = Addr + Inst.getOperand(i: 1).getImm();
252 return true;
253 case RISCV::JALR: {
254 if (auto TargetRegState = getGPRState(Reg: Inst.getOperand(i: 1).getReg())) {
255 Target = *TargetRegState + Inst.getOperand(i: 2).getImm();
256 return true;
257 }
258 return false;
259 }
260 }
261
262 return false;
263 }
264
265 bool isTerminator(const MCInst &Inst) const override {
266 if (MCInstrAnalysis::isTerminator(Inst))
267 return true;
268
269 switch (Inst.getOpcode()) {
270 default:
271 return false;
272 case RISCV::JAL:
273 case RISCV::JALR:
274 return Inst.getOperand(i: 0).getReg() == RISCV::X0;
275 }
276 }
277
278 bool isCall(const MCInst &Inst) const override {
279 if (MCInstrAnalysis::isCall(Inst))
280 return true;
281
282 switch (Inst.getOpcode()) {
283 default:
284 return false;
285 case RISCV::JAL:
286 case RISCV::JALR:
287 return Inst.getOperand(i: 0).getReg() != RISCV::X0;
288 }
289 }
290
291 bool isReturn(const MCInst &Inst) const override {
292 if (MCInstrAnalysis::isReturn(Inst))
293 return true;
294
295 switch (Inst.getOpcode()) {
296 default:
297 return false;
298 case RISCV::JALR:
299 return Inst.getOperand(i: 0).getReg() == RISCV::X0 &&
300 maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg());
301 case RISCV::C_JR:
302 return maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg());
303 }
304 }
305
306 bool isBranch(const MCInst &Inst) const override {
307 if (MCInstrAnalysis::isBranch(Inst))
308 return true;
309
310 return isBranchImpl(Inst);
311 }
312
313 bool isUnconditionalBranch(const MCInst &Inst) const override {
314 if (MCInstrAnalysis::isUnconditionalBranch(Inst))
315 return true;
316
317 return isBranchImpl(Inst);
318 }
319
320 bool isIndirectBranch(const MCInst &Inst) const override {
321 if (MCInstrAnalysis::isIndirectBranch(Inst))
322 return true;
323
324 switch (Inst.getOpcode()) {
325 default:
326 return false;
327 case RISCV::JALR:
328 return Inst.getOperand(i: 0).getReg() == RISCV::X0 &&
329 !maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg());
330 case RISCV::C_JR:
331 return !maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg());
332 }
333 }
334
335 /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
336 std::vector<std::pair<uint64_t, uint64_t>>
337 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
338 const MCSubtargetInfo &STI) const override {
339 uint32_t LoadInsnOpCode;
340 if (const Triple &T = STI.getTargetTriple(); T.isRISCV64())
341 LoadInsnOpCode = 0x3003; // ld
342 else if (T.isRISCV32())
343 LoadInsnOpCode = 0x2003; // lw
344 else
345 return {};
346
347 constexpr uint64_t FirstEntryAt = 32, EntrySize = 16;
348 if (PltContents.size() < FirstEntryAt + EntrySize)
349 return {};
350
351 std::vector<std::pair<uint64_t, uint64_t>> Results;
352 for (uint64_t EntryStart = FirstEntryAt,
353 EntryStartEnd = PltContents.size() - EntrySize;
354 EntryStart <= EntryStartEnd; EntryStart += EntrySize) {
355 const uint32_t AuipcInsn =
356 support::endian::read32le(P: PltContents.data() + EntryStart);
357 const bool IsAuipc = (AuipcInsn & 0x7F) == 0x17;
358 if (!IsAuipc)
359 continue;
360
361 const uint32_t LoadInsn =
362 support::endian::read32le(P: PltContents.data() + EntryStart + 4);
363 const bool IsLoad = (LoadInsn & 0x707F) == LoadInsnOpCode;
364 if (!IsLoad)
365 continue;
366
367 const uint64_t GotPltSlotVA = PltSectionVA + EntryStart +
368 (AuipcInsn & 0xFFFFF000) +
369 SignExtend64<12>(x: LoadInsn >> 20);
370 Results.emplace_back(args: PltSectionVA + EntryStart, args: GotPltSlotVA);
371 }
372
373 return Results;
374 }
375
376private:
377 static bool maybeReturnAddress(MCRegister Reg) {
378 // X1 is used for normal returns, X5 for returns from outlined functions.
379 return Reg == RISCV::X1 || Reg == RISCV::X5;
380 }
381
382 static bool isBranchImpl(const MCInst &Inst) {
383 switch (Inst.getOpcode()) {
384 default:
385 return false;
386 case RISCV::JAL:
387 return Inst.getOperand(i: 0).getReg() == RISCV::X0;
388 case RISCV::JALR:
389 return Inst.getOperand(i: 0).getReg() == RISCV::X0 &&
390 !maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg());
391 case RISCV::C_JR:
392 return !maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg());
393 }
394 }
395};
396
397} // end anonymous namespace
398
399static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
400 return new RISCVMCInstrAnalysis(Info);
401}
402
403extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
404LLVMInitializeRISCVTargetMC() {
405 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target(),
406 &getTheRISCV32beTarget(), &getTheRISCV64beTarget()}) {
407 TargetRegistry::RegisterMCAsmInfo(T&: *T, Fn: createRISCVMCAsmInfo);
408 TargetRegistry::RegisterMCObjectFileInfo(T&: *T, Fn: createRISCVMCObjectFileInfo);
409 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createRISCVMCInstrInfo);
410 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createRISCVMCRegisterInfo);
411 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createRISCVAsmBackend);
412 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createRISCVMCCodeEmitter);
413 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createRISCVMCInstPrinter);
414 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createRISCVMCSubtargetInfo);
415 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createRISCVELFStreamer);
416 TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createMachOStreamer);
417 TargetRegistry::RegisterObjectTargetStreamer(
418 T&: *T, Fn: createRISCVObjectTargetStreamer);
419 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createRISCVInstrAnalysis);
420
421 // Register the asm target streamer.
422 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createRISCVAsmTargetStreamer);
423 // Register the null target streamer.
424 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
425 Fn: createRISCVNullTargetStreamer);
426 }
427}
428