1//===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This file provides RISC-V specific target descriptions.
10///
11//===----------------------------------------------------------------------===//
12
13#include "RISCVMCTargetDesc.h"
14#include "RISCVELFStreamer.h"
15#include "RISCVInstPrinter.h"
16#include "RISCVMCAsmInfo.h"
17#include "RISCVMCObjectFileInfo.h"
18#include "RISCVMCOptions.h"
19#include "RISCVTargetStreamer.h"
20#include "TargetInfo/RISCVTargetInfo.h"
21#include "llvm/MC/MCAsmBackend.h"
22#include "llvm/MC/MCAsmInfo.h"
23#include "llvm/MC/MCCodeEmitter.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCObjectFileInfo.h"
27#include "llvm/MC/MCObjectWriter.h"
28#include "llvm/MC/MCRegisterInfo.h"
29#include "llvm/MC/MCStreamer.h"
30#include "llvm/MC/MCSubtargetInfo.h"
31#include "llvm/MC/TargetRegistry.h"
32#include "llvm/Option/LibraryOptions.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/MathExtras.h"
36#include <bitset>
37
38#define GET_INSTRINFO_MC_DESC
39#define ENABLE_INSTR_PREDICATE_VERIFIER
40#define GET_INSTRINFO_NAMED_OPS
41#include "RISCVGenInstrInfo.inc"
42
43#define GET_REGINFO_MC_DESC
44#include "RISCVGenRegisterInfo.inc"
45
46#define GET_SUBTARGETINFO_MC_DESC
47#include "RISCVGenSubtargetInfo.inc"
48
49#define OPTIONS_STRUCT_DEFS
50#include "RISCVMCOptions.inc"
51
52using namespace llvm;
53
54static MCInstrInfo *createRISCVMCInstrInfo() {
55 MCInstrInfo *X = new MCInstrInfo();
56 InitRISCVMCInstrInfo(II: X);
57 return X;
58}
59
60static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
61 MCRegisterInfo *X = new MCRegisterInfo();
62 InitRISCVMCRegisterInfo(RI: X, RA: RISCV::X1);
63 return X;
64}
65
66static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
67 const Triple &TT,
68 const MCTargetOptions &Options) {
69 MCAsmInfo *MAI = nullptr;
70 if (TT.isOSBinFormatELF())
71 MAI = new RISCVMCAsmInfo(TT, Options);
72 else if (TT.isOSBinFormatMachO())
73 MAI = new RISCVMCAsmInfoDarwin(Options);
74 else
75 reportFatalUsageError(reason: "unsupported object format");
76
77 unsigned SP = MRI.getDwarfRegNum(Reg: RISCV::X2, isEH: true);
78 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: SP, Offset: 0);
79 MAI->addInitialFrameState(Inst);
80
81 return MAI;
82}
83
84static MCObjectFileInfo *
85createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC,
86 bool LargeCodeModel = false) {
87 MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo();
88 MOFI->initMCObjectFileInfo(MCCtx&: Ctx, PIC, LargeCodeModel);
89 return MOFI;
90}
91
92void RISCV::updateCZceFeatureImplications(MCSubtargetInfo &STI) {
93 // Add Zcd if C and D are enabled and we aren't targeting 64-bit RVY.
94 if (STI.hasFeature(Feature: RISCV::FeatureStdExtC) &&
95 STI.hasFeature(Feature: RISCV::FeatureStdExtD) &&
96 !STI.hasFeature(Feature: RISCV::FeatureStdExtZcd) &&
97 !(STI.hasFeature(Feature: RISCV::Feature64Bit) &&
98 STI.hasFeature(Feature: RISCV::FeatureStdExtY)))
99 STI.ToggleFeature(FB: RISCV::FeatureStdExtZcd);
100
101 // Add Zcf if F and C or Zce are enabled on RV32 and Y is not enabled.
102 if (!STI.hasFeature(Feature: RISCV::FeatureStdExtZcf) &&
103 !STI.hasFeature(Feature: RISCV::Feature64Bit) &&
104 !STI.hasFeature(Feature: RISCV::FeatureStdExtY) &&
105 STI.hasFeature(Feature: RISCV::FeatureStdExtF) &&
106 (STI.hasFeature(Feature: RISCV::FeatureStdExtC) ||
107 STI.hasFeature(Feature: RISCV::FeatureStdExtZce)))
108 STI.ToggleFeature(FB: RISCV::FeatureStdExtZcf);
109
110 // We don't infer C or Zce because no code should be looking at those
111 // subtarget feature flags and they can cause issues like #229758.
112}
113
114static MCSubtargetInfo *
115createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
116 if (CPU.empty() || CPU == "generic")
117 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
118
119 MCSubtargetInfo *X =
120 createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
121
122 // If the CPU is "help" fill in 64 or 32 bit feature so we can pass
123 // RISCVFeatures::validate.
124 // FIXME: Why does llvm-mc still expect a source file with -mcpu=help?
125 if (CPU == "help") {
126 llvm::FeatureBitset Features = X->getFeatureBits();
127 if (TT.isArch64Bit())
128 Features.set(RISCV::Feature64Bit);
129 else
130 Features.set(RISCV::Feature32Bit);
131 X->setFeatureBits(Features);
132 }
133
134 RISCV::updateCZceFeatureImplications(STI&: *X);
135
136 return X;
137}
138
139static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
140 unsigned SyntaxVariant,
141 const MCAsmInfo &MAI,
142 const MCInstrInfo &MII,
143 const MCRegisterInfo &MRI) {
144 return new RISCVInstPrinter(MAI, MII, MRI);
145}
146
147static MCTargetStreamer *
148createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
149 const Triple &TT = STI.getTargetTriple();
150 if (TT.isOSBinFormatELF())
151 return new RISCVTargetELFStreamer(S, STI);
152 return new RISCVTargetStreamer(S);
153}
154
155static MCStreamer *
156createMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
157 std::unique_ptr<MCObjectWriter> &&OW,
158 std::unique_ptr<MCCodeEmitter> &&Emitter) {
159 return createMachOStreamer(Ctx, TAB: std::move(TAB), OW: std::move(OW),
160 CE: std::move(Emitter),
161 /*DWARFMustBeAtTheEnd*/ false,
162 /*LabelSections*/ true);
163}
164
165static MCTargetStreamer *
166createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
167 MCInstPrinter *InstPrint) {
168 return new RISCVTargetAsmStreamer(S, OS);
169}
170
171static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
172 return new RISCVTargetStreamer(S);
173}
174
175namespace {
176
177class RISCVMCInstrAnalysis : public MCInstrAnalysis {
178 int64_t GPRState[31] = {};
179 std::bitset<31> GPRValidMask;
180
181 static bool isGPR(MCRegister Reg) {
182 return Reg >= RISCV::X0 && Reg <= RISCV::X31;
183 }
184 static bool isYGPR(MCRegister Reg) {
185 return Reg >= RISCV::X0_Y && Reg <= RISCV::X31_Y;
186 }
187 static bool isZeroReg(MCRegister Reg) {
188 return Reg == RISCV::X0 || Reg == RISCV::X0_Y;
189 }
190
191 static unsigned getRegIndex(MCRegister Reg) {
192 if (isYGPR(Reg)) {
193 assert(Reg != RISCV::X0_Y && "Invalid GPR reg");
194 return Reg - RISCV::X1_Y;
195 }
196 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");
197 return Reg - RISCV::X1;
198 }
199
200 void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {
201 if (isZeroReg(Reg))
202 return;
203
204 auto Index = getRegIndex(Reg);
205
206 if (Value) {
207 GPRState[Index] = *Value;
208 GPRValidMask.set(position: Index);
209 } else {
210 GPRValidMask.reset(position: Index);
211 }
212 }
213
214 std::optional<int64_t> getGPRState(MCRegister Reg) const {
215 if (isZeroReg(Reg))
216 return 0;
217
218 auto Index = getRegIndex(Reg);
219
220 if (GPRValidMask.test(position: Index))
221 return GPRState[Index];
222 return std::nullopt;
223 }
224
225public:
226 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
227 : MCInstrAnalysis(Info) {}
228
229 void resetState() override { GPRValidMask.reset(); }
230
231 void updateState(const MCInst &Inst, const MCSubtargetInfo *STI,
232 uint64_t Addr) override {
233 // Terminators mark the end of a basic block which means the sequentially
234 // next instruction will be the first of another basic block and the current
235 // state will typically not be valid anymore. For calls, we assume all
236 // registers may be clobbered by the callee (TODO: should we take the
237 // calling convention into account?).
238 if (isTerminator(Inst) || isCall(Inst)) {
239 resetState();
240 return;
241 }
242
243 switch (Inst.getOpcode()) {
244 default: {
245 // Clear the state of all defined registers for instructions that we don't
246 // explicitly support.
247 auto NumDefs = Info->get(Opcode: Inst.getOpcode()).getNumDefs();
248 for (unsigned I = 0; I < NumDefs; ++I) {
249 auto DefReg = Inst.getOperand(i: I).getReg();
250 if (isGPR(Reg: DefReg))
251 setGPRState(Reg: DefReg, Value: std::nullopt);
252 }
253 break;
254 }
255 case RISCV::AUIPC:
256 setGPRState(Reg: Inst.getOperand(i: 0).getReg(),
257 Value: Addr + SignExtend64<32>(x: Inst.getOperand(i: 1).getImm() << 12));
258 break;
259 }
260 }
261
262 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
263 uint64_t &Target) const override {
264 if (isConditionalBranch(Inst)) {
265 int64_t Imm;
266 if (Size == 2)
267 Imm = Inst.getOperand(i: 1).getImm();
268 else
269 Imm = Inst.getOperand(i: 2).getImm();
270 Target = Addr + Imm;
271 return true;
272 }
273
274 switch (Inst.getOpcode()) {
275 case RISCV::C_J:
276 case RISCV::C_JAL:
277 case RISCV::QC_E_J:
278 case RISCV::QC_E_JAL:
279 Target = Addr + Inst.getOperand(i: 0).getImm();
280 return true;
281 case RISCV::JAL:
282 Target = Addr + Inst.getOperand(i: 1).getImm();
283 return true;
284 case RISCV::JALR: {
285 if (auto TargetRegState = getGPRState(Reg: Inst.getOperand(i: 1).getReg())) {
286 Target = *TargetRegState + Inst.getOperand(i: 2).getImm();
287 return true;
288 }
289 return false;
290 }
291 }
292
293 return false;
294 }
295
296 bool isTerminator(const MCInst &Inst) const override {
297 if (MCInstrAnalysis::isTerminator(Inst))
298 return true;
299
300 switch (Inst.getOpcode()) {
301 default:
302 return false;
303 case RISCV::JAL:
304 case RISCV::JALR:
305 return Inst.getOperand(i: 0).getReg() == RISCV::X0;
306 }
307 }
308
309 bool isCall(const MCInst &Inst) const override {
310 if (MCInstrAnalysis::isCall(Inst))
311 return true;
312
313 switch (Inst.getOpcode()) {
314 default:
315 return false;
316 case RISCV::JAL:
317 case RISCV::JALR:
318 return Inst.getOperand(i: 0).getReg() != RISCV::X0;
319 }
320 }
321
322 bool isReturn(const MCInst &Inst) const override {
323 if (MCInstrAnalysis::isReturn(Inst))
324 return true;
325
326 switch (Inst.getOpcode()) {
327 default:
328 return false;
329 case RISCV::JALR:
330 return Inst.getOperand(i: 0).getReg() == RISCV::X0 &&
331 maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg());
332 case RISCV::C_JR:
333 return maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg());
334 }
335 }
336
337 bool isBranch(const MCInst &Inst) const override {
338 if (MCInstrAnalysis::isBranch(Inst))
339 return true;
340
341 return isBranchImpl(Inst);
342 }
343
344 bool isUnconditionalBranch(const MCInst &Inst) const override {
345 if (MCInstrAnalysis::isUnconditionalBranch(Inst))
346 return true;
347
348 return isBranchImpl(Inst);
349 }
350
351 bool isIndirectBranch(const MCInst &Inst) const override {
352 if (MCInstrAnalysis::isIndirectBranch(Inst))
353 return true;
354
355 switch (Inst.getOpcode()) {
356 default:
357 return false;
358 case RISCV::JALR:
359 return Inst.getOperand(i: 0).getReg() == RISCV::X0 &&
360 !maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg());
361 case RISCV::C_JR:
362 return !maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg());
363 }
364 }
365
366 /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
367 std::vector<std::pair<uint64_t, uint64_t>>
368 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
369 const MCSubtargetInfo &STI) const override {
370 uint32_t LoadInsnOpCode;
371 if (const Triple &T = STI.getTargetTriple(); T.isRISCV64())
372 LoadInsnOpCode = 0x3003; // ld
373 else if (T.isRISCV32())
374 LoadInsnOpCode = 0x2003; // lw
375 else
376 return {};
377
378 constexpr uint64_t FirstEntryAt = 32, EntrySize = 16;
379 if (PltContents.size() < FirstEntryAt + EntrySize)
380 return {};
381
382 std::vector<std::pair<uint64_t, uint64_t>> Results;
383 for (uint64_t EntryStart = FirstEntryAt,
384 EntryStartEnd = PltContents.size() - EntrySize;
385 EntryStart <= EntryStartEnd; EntryStart += EntrySize) {
386 const uint32_t AuipcInsn =
387 support::endian::read32le(P: PltContents.data() + EntryStart);
388 const bool IsAuipc = (AuipcInsn & 0x7F) == 0x17;
389 if (!IsAuipc)
390 continue;
391
392 const uint32_t LoadInsn =
393 support::endian::read32le(P: PltContents.data() + EntryStart + 4);
394 const bool IsLoad = (LoadInsn & 0x707F) == LoadInsnOpCode;
395 if (!IsLoad)
396 continue;
397
398 const uint64_t GotPltSlotVA = PltSectionVA + EntryStart +
399 (AuipcInsn & 0xFFFFF000) +
400 SignExtend64<12>(x: LoadInsn >> 20);
401 Results.emplace_back(args: PltSectionVA + EntryStart, args: GotPltSlotVA);
402 }
403
404 return Results;
405 }
406
407private:
408 static bool maybeReturnAddress(MCRegister Reg) {
409 // X1 is used for normal returns, X5 for returns from outlined functions.
410 return Reg == RISCV::X1 || Reg == RISCV::X5;
411 }
412
413 static bool isBranchImpl(const MCInst &Inst) {
414 switch (Inst.getOpcode()) {
415 default:
416 return false;
417 case RISCV::JAL:
418 return Inst.getOperand(i: 0).getReg() == RISCV::X0;
419 case RISCV::JALR:
420 return Inst.getOperand(i: 0).getReg() == RISCV::X0 &&
421 !maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg());
422 case RISCV::C_JR:
423 return !maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg());
424 }
425 }
426};
427
428} // end anonymous namespace
429
430static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
431 return new RISCVMCInstrAnalysis(Info);
432}
433
434extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
435LLVMInitializeRISCVTargetMC() {
436 static opt::RegisterLibraryOptions<RISCVMCOptions> O;
437 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target(),
438 &getTheRISCV32beTarget(), &getTheRISCV64beTarget()}) {
439 TargetRegistry::RegisterMCAsmInfo(T&: *T, Fn: createRISCVMCAsmInfo);
440 TargetRegistry::RegisterMCObjectFileInfo(T&: *T, Fn: createRISCVMCObjectFileInfo);
441 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createRISCVMCInstrInfo);
442 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createRISCVMCRegisterInfo);
443 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createRISCVAsmBackend);
444 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createRISCVMCCodeEmitter);
445 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createRISCVMCInstPrinter);
446 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createRISCVMCSubtargetInfo);
447 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createRISCVELFStreamer);
448 TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createMachOStreamer);
449 TargetRegistry::RegisterObjectTargetStreamer(
450 T&: *T, Fn: createRISCVObjectTargetStreamer);
451 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createRISCVInstrAnalysis);
452
453 // Register the asm target streamer.
454 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createRISCVAsmTargetStreamer);
455 // Register the null target streamer.
456 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
457 Fn: createRISCVNullTargetStreamer);
458 }
459}
460