| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* Option Parsing Definitions *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | ///////// |
| 10 | // Tables |
| 11 | |
| 12 | #if defined(OPTTABLE_CODE) || defined(OPTIONS_STRUCT_DEFS) |
| 13 | static llvm::opt::OptTable::Tables optionTables() { |
| 14 | using llvm::opt::DefaultVis, llvm::opt::HelpHidden, |
| 15 | llvm::opt::RenderAsInput, llvm::opt::RenderJoined, |
| 16 | llvm::opt::RenderSeparate; |
| 17 | |
| 18 | #ifdef __GNUC__ |
| 19 | #pragma GCC diagnostic push |
| 20 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 21 | #endif |
| 22 | static constexpr char OptionStrTableStorage[] = |
| 23 | "\0" |
| 24 | "-\0" |
| 25 | "--\0" |
| 26 | "<input>\0" |
| 27 | "<unknown>\0" |
| 28 | "-riscv-br-merging-base-cost\0" |
| 29 | "Sets the cost threshold for when multiple conditionals will be merged into one branch versus be split in multiple branches. Merging conditionals saves branches at the cost of additional instructions. This value sets the instruction cost limit, below which conditionals will be merged, and above which conditionals will be split. Set to -1 to never merge branches\0" |
| 30 | "-riscv-br-merging-likely-bias\0" |
| 31 | "Increases 'riscv-br-merging-base-cost' in cases that it is likely that all conditionals will be executed. For example for merging the conditionals (a == b && c > d), if its known that a == b is likely, then it is likely that if the conditionals are split both sides will be executed, so it may be desirable to increase the instruction cost threshold. Set to -1 to never merge likely branches\0" |
| 32 | "-riscv-br-merging-unlikely-bias\0" |
| 33 | "Decreases 'riscv-br-merging-base-cost' in cases that it is unlikely that all conditionals will be executed. For example for merging the conditionals (a == b && c > d), if its known that a == b is unlikely, then it is unlikely that if the conditionals are split both sides will be executed, so it may be desirable to decrease the instruction cost threshold. Set to -1 to never merge unlikely branches\0" |
| 34 | "-riscv-constant-pool-for-large-ints\0" |
| 35 | "Enable using constant pool for large integers\0" |
| 36 | "-riscv-cost-per-use\0" |
| 37 | "\0" |
| 38 | "\0" |
| 39 | "-riscv-enable-cfi-instr-inserter\0" |
| 40 | "Enable CFI Instruction Inserter for RISC-V\0" |
| 41 | "-riscv-enable-copy-propagation\0" |
| 42 | "Enable the copy propagation with RISC-V copy instr\0" |
| 43 | "-riscv-enable-copyelim\0" |
| 44 | "Enable the redundant copy elimination pass\0" |
| 45 | "-riscv-enable-dead-defs\0" |
| 46 | "Enable the pass that removes dead definitions and replaces stores to them with stores to x0\0" |
| 47 | "-riscv-enable-global-merge\0" |
| 48 | "Enable the global merge pass\0" |
| 49 | "-riscv-enable-loop-data-prefetch\0" |
| 50 | "Enable the loop data prefetch pass\0" |
| 51 | "-riscv-enable-machine-combiner\0" |
| 52 | "Enable the machine combiner pass\0" |
| 53 | "-riscv-enable-pipeliner\0" |
| 54 | "Enable Machine Pipeliner for RISC-V\0" |
| 55 | "-riscv-enable-sink-fold\0" |
| 56 | "Enable sinking and folding of instruction copies\0" |
| 57 | "-riscv-force-machine-combiner-strategy\0" |
| 58 | "Force machine combiner to use a specific strategy for machine trace metrics evaluation\0" |
| 59 | "<local|min-instr>\0" |
| 60 | "local,min-instr\0" |
| 61 | "-riscv-frm-insert-opt\0" |
| 62 | "Enable optimized frm insertion\0" |
| 63 | "-riscv-insert-vsetvli-whole-vector-register-move-valid-vtype\0" |
| 64 | "Insert vsetvlis before vmvNr.vs to ensure vtype is valid and vill is cleared\0" |
| 65 | "-riscv-landing-pad-label\0" |
| 66 | "Use preferred fixed label for all labels\0" |
| 67 | "-riscv-load-store-scan-limit\0" |
| 68 | "-riscv-lower-ext-max-web-size\0" |
| 69 | "Give the maximum size (in number of nodes) of the web of instructions that we will consider for VW expansion\0" |
| 70 | "-riscv-lower-form-vw-w-with-splat\0" |
| 71 | "Allow the formation of VW_W operations (e.g., VWADD_W) with splat constants\0" |
| 72 | "-riscv-lower-fp-repeated-divisors\0" |
| 73 | "Set the minimum number of repetitions of a divisor to allow transformation to multiplications by the reciprocal\0" |
| 74 | "-riscv-lower-fpimm-cost\0" |
| 75 | "Give the maximum number of instructions that we will use for creating a floating-point immediate value\0" |
| 76 | "-riscv-max-build-ints-cost\0" |
| 77 | "The maximum cost used for building integers\0" |
| 78 | "-riscv-min-jump-table-entries\0" |
| 79 | "Set minimum number of entries to use a jump table on RISCV\0" |
| 80 | "-riscv-mips-ccmov\0" |
| 81 | "Use 'mips.ccmov' instruction\0" |
| 82 | "-riscv-mips-load-store-pairs\0" |
| 83 | "Enable the load/store pair optimization pass\0" |
| 84 | "-riscv-or-like-select\0" |
| 85 | "-riscv-outliner-regsave\0" |
| 86 | "Enable RegSave strategy in machine outliner (save X5 to a temporary register when X5 is live across outlined calls)\0" |
| 87 | "-riscv-prefer-whole-register-move\0" |
| 88 | "Prefer whole register move for vector registers\0" |
| 89 | "-riscv-reassoc-shl-addi-add\0" |
| 90 | "Swap add and addi in cases where the add may be combined with a shift\0" |
| 91 | "-riscv-regalloc-hints\0" |
| 92 | "Enable two address hints for register allocation\0" |
| 93 | "-riscv-sched-load-latency\0" |
| 94 | "Override the load latency (in cycles) in the scheduler model. A non-negative value overrides the target default\0" |
| 95 | "-riscv-sched-mispredict-penalty\0" |
| 96 | "Override the mispredict penalty (in cycles) in the scheduler model. A non-negative value overrides the target default\0" |
| 97 | "-riscv-select-opt\0" |
| 98 | "Enable select to branch optimizations\0" |
| 99 | "-riscv-sextw-removal\0" |
| 100 | "Enable removal of sext.w\0" |
| 101 | "-riscv-strip-w-suffix\0" |
| 102 | "Enable strip W suffix\0" |
| 103 | "-riscv-use-aa\0" |
| 104 | "Enable the use of AA during codegen\0" |
| 105 | "-riscv-use-rematerializable-movimm\0" |
| 106 | "Use a rematerializable pseudoinstruction for 2 instruction constant materialization\0" |
| 107 | "-riscv-v-min-trip-count\0" |
| 108 | "Set the lower bound of a trip count to decide on vectorization while tail-folding\0" |
| 109 | "-riscv-v-register-bit-width-lmul\0" |
| 110 | "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used by autovectorized code. Fractional LMULs are not supported\0" |
| 111 | "-riscv-v-slp-max-vf\0" |
| 112 | "Overrides result used for getMaximumVF query which is used exclusively by SLP vectorizer\0" |
| 113 | "-riscv-v-vector-bits-max\0" |
| 114 | "Assume V extension vector registers are at most this big, with zero meaning no maximum size is assumed\0" |
| 115 | "-riscv-v-vector-bits-min\0" |
| 116 | "Assume V extension vector registers are at least this big, with zero meaning no minimum size is assumed. A value of -1 means use Zvl*b extension. This is primarily used to enable autovectorization with fixed width vectors\0" |
| 117 | "-riscv-vector-mask-mutation\0" |
| 118 | "Enable the vector mask scheduling mutation\0" |
| 119 | "-riscv-zilsd-max-reschedule-distance\0" |
| 120 | "Maximum distance for rescheduling load/store instructions\0" |
| 121 | "-riscv-zilsd-opt\0" |
| 122 | "Enable Zilsd load/store optimization\0" |
| 123 | ; |
| 124 | #ifdef __GNUC__ |
| 125 | #pragma GCC diagnostic pop |
| 126 | #endif |
| 127 | |
| 128 | static constexpr llvm::StringTable |
| 129 | OptionStrTable = OptionStrTableStorage; |
| 130 | |
| 131 | static constexpr llvm::StringTable::Offset OptionPrefixesTable[] = { |
| 132 | 0 /* prefixes */, |
| 133 | 2 /* prefixes */, 1 /* '-' */, 3 /* '--' */ |
| 134 | }; |
| 135 | |
| 136 | static constexpr llvm::opt::OptTable::HelpTextVariant OptionHelpTextVariantsTable[] = { |
| 137 | {0, 0}, |
| 138 | }; |
| 139 | |
| 140 | static constexpr unsigned OptionSubCommandIDsTable[] = { |
| 141 | 0 /* subcommands */ |
| 142 | }; |
| 143 | |
| 144 | static constexpr llvm::opt::OptTable::InfoExtra OptionInfoExtrasTable[] = { |
| 145 | {0, 0, 0, 0, 0, 0, 0, 0}, |
| 146 | {0, 0, 0, 0, static_cast<unsigned>(DefaultVis), 0, 0, 0}, |
| 147 | {2160, 0, 2178, 0, static_cast<unsigned>(DefaultVis), 0, 0, 0}, |
| 148 | }; |
| 149 | |
| 150 | static constexpr llvm::opt::OptTable::Info OptionInfoTable[] = { |
| 151 | {6 /* <input> */, 0, 0, 0, 1, 0, llvm::opt::Option::InputClass}, |
| 152 | {14 /* <unknown> */, 0, 0, 0, 1, 0, llvm::opt::Option::UnknownClass}, |
| 153 | {24 /* -riscv-br-merging-base-cost */, 52, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 154 | {415 /* -riscv-br-merging-likely-bias */, 445, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 155 | {837 /* -riscv-br-merging-unlikely-bias */, 869, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 156 | {1269 /* -riscv-constant-pool-for-large-ints */, 1305, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 157 | {1351 /* -riscv-cost-per-use */, 1371, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 158 | {1373 /* -riscv-enable-cfi-instr-inserter */, 1406, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 159 | {1449 /* -riscv-enable-copy-propagation */, 1480, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 160 | {1531 /* -riscv-enable-copyelim */, 1554, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 161 | {1597 /* -riscv-enable-dead-defs */, 1621, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 162 | {1713 /* -riscv-enable-global-merge */, 1740, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 163 | {1769 /* -riscv-enable-loop-data-prefetch */, 1802, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 164 | {1837 /* -riscv-enable-machine-combiner */, 1868, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 165 | {1901 /* -riscv-enable-pipeliner */, 1925, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 166 | {1961 /* -riscv-enable-sink-fold */, 1985, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 167 | {2034 /* -riscv-force-machine-combiner-strategy */, 2073, 0, 0, 2, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 168 | {2194 /* -riscv-frm-insert-opt */, 2216, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 169 | {2247 /* -riscv-insert-vsetvli-whole-vector-register-move-valid-vtype */, 2308, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 170 | {2385 /* -riscv-landing-pad-label */, 2410, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 171 | {2451 /* -riscv-load-store-scan-limit */, 1371, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 172 | {2480 /* -riscv-lower-ext-max-web-size */, 2510, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 173 | {2619 /* -riscv-lower-form-vw-w-with-splat */, 2653, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 174 | {2729 /* -riscv-lower-fp-repeated-divisors */, 2763, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 175 | {2875 /* -riscv-lower-fpimm-cost */, 2899, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 176 | {3002 /* -riscv-max-build-ints-cost */, 3029, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 177 | {3073 /* -riscv-min-jump-table-entries */, 3103, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 178 | {3162 /* -riscv-mips-ccmov */, 3180, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 179 | {3209 /* -riscv-mips-load-store-pairs */, 3238, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 180 | {3283 /* -riscv-or-like-select */, 1371, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 181 | {3305 /* -riscv-outliner-regsave */, 3329, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 182 | {3445 /* -riscv-prefer-whole-register-move */, 3479, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 183 | {3527 /* -riscv-reassoc-shl-addi-add */, 3555, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 184 | {3625 /* -riscv-regalloc-hints */, 3647, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 185 | {3696 /* -riscv-sched-load-latency */, 3722, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 186 | {3834 /* -riscv-sched-mispredict-penalty */, 3866, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 187 | {3984 /* -riscv-select-opt */, 4002, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 188 | {4040 /* -riscv-sextw-removal */, 4061, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 189 | {4086 /* -riscv-strip-w-suffix */, 4108, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 190 | {4130 /* -riscv-use-aa */, 4144, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 191 | {4180 /* -riscv-use-rematerializable-movimm */, 4215, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 192 | {4299 /* -riscv-v-min-trip-count */, 4323, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 193 | {4405 /* -riscv-v-register-bit-width-lmul */, 4438, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 194 | {4564 /* -riscv-v-slp-max-vf */, 4584, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 195 | {4673 /* -riscv-v-vector-bits-max */, 4698, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 196 | {4801 /* -riscv-v-vector-bits-min */, 4826, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 197 | {5048 /* -riscv-vector-mask-mutation */, 5076, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 198 | {5119 /* -riscv-zilsd-max-reschedule-distance */, 5156, 0, 0, 1, 1, llvm::opt::Option::SeparateOrEqClass}, |
| 199 | {5214 /* -riscv-zilsd-opt */, 5231, 0, 0, 1, 1, llvm::opt::Option::FlagOrEqClass}, |
| 200 | }; |
| 201 | |
| 202 | return {OptionStrTable, OptionPrefixesTable, |
| 203 | OptionInfoTable, OptionInfoExtrasTable, OptionHelpTextVariantsTable, {}, OptionSubCommandIDsTable}; |
| 204 | } |
| 205 | #undef OPTTABLE_CODE |
| 206 | #endif // OPTTABLE_CODE || OPTIONS_STRUCT_DEFS |
| 207 | |
| 208 | |
| 209 | #ifdef OPTIONS_STRUCT_DECL |
| 210 | #undef OPTIONS_STRUCT_DECL |
| 211 | #include "llvm/ADT/ArrayRef.h" |
| 212 | #include "llvm/ADT/BoolOrDefault.h" |
| 213 | #include "llvm/ADT/StringRef.h" |
| 214 | #include "llvm/Support/Allocator.h" |
| 215 | |
| 216 | namespace llvm { |
| 217 | namespace opt { |
| 218 | class Arg; |
| 219 | class OptTable; |
| 220 | } // namespace opt |
| 221 | } // namespace llvm |
| 222 | |
| 223 | namespace llvm { |
| 224 | struct RISCVOptions { |
| 225 | bool use_rematerializable_movimm{false}; |
| 226 | std::optional<int> br_merging_base_cost{std::nullopt}; |
| 227 | int br_merging_likely_bias{0}; |
| 228 | int br_merging_unlikely_bias{-1}; |
| 229 | unsigned lower_ext_max_web_size{18}; |
| 230 | bool lower_form_vw_w_with_splat{false}; |
| 231 | unsigned lower_fp_repeated_divisors{2}; |
| 232 | int lower_fpimm_cost{3}; |
| 233 | bool reassoc_shl_addi_add{true}; |
| 234 | std::optional<uint32_t> landing_pad_label{std::nullopt}; |
| 235 | bool frm_insert_opt{true}; |
| 236 | bool insert_vsetvli_whole_vector_register_move_valid_vtype{true}; |
| 237 | std::optional<MachineTraceStrategy> force_machine_combiner_strategy{std::nullopt}; |
| 238 | bool outliner_regsave{true}; |
| 239 | bool prefer_whole_register_move{false}; |
| 240 | unsigned load_store_scan_limit{128}; |
| 241 | bool sextw_removal{true}; |
| 242 | bool strip_w_suffix{true}; |
| 243 | bool cost_per_use{true}; |
| 244 | bool regalloc_hints{true}; |
| 245 | bool constant_pool_for_large_ints{true}; |
| 246 | unsigned max_build_ints_cost{0}; |
| 247 | std::optional<unsigned> min_jump_table_entries{std::nullopt}; |
| 248 | bool mips_ccmov{true}; |
| 249 | bool mips_load_store_pairs{false}; |
| 250 | std::optional<unsigned> sched_load_latency{std::nullopt}; |
| 251 | std::optional<unsigned> sched_mispredict_penalty{std::nullopt}; |
| 252 | bool use_aa{true}; |
| 253 | bool enable_cfi_instr_inserter{false}; |
| 254 | bool enable_copy_propagation{true}; |
| 255 | bool enable_copyelim{true}; |
| 256 | bool enable_dead_defs{true}; |
| 257 | llvm::BoolOrDefault enable_global_merge{llvm::BoolOrDefault::Default}; |
| 258 | bool enable_loop_data_prefetch{true}; |
| 259 | bool enable_machine_combiner{true}; |
| 260 | bool enable_pipeliner{false}; |
| 261 | bool enable_sink_fold{true}; |
| 262 | bool select_opt{true}; |
| 263 | std::optional<unsigned> v_vector_bits_max{std::nullopt}; |
| 264 | std::optional<int> v_vector_bits_min{std::nullopt}; |
| 265 | bool vector_mask_mutation{true}; |
| 266 | bool or_like_select{true}; |
| 267 | unsigned v_min_trip_count{5}; |
| 268 | unsigned v_register_bit_width_lmul{2}; |
| 269 | std::optional<unsigned> v_slp_max_vf{std::nullopt}; |
| 270 | unsigned zilsd_max_reschedule_distance{10}; |
| 271 | bool zilsd_opt{true}; |
| 272 | |
| 273 | /// The instance cl::ParseCommandLineOptions sets. |
| 274 | static RISCVOptions Global; |
| 275 | |
| 276 | static const llvm::opt::OptTable &optTable(); |
| 277 | /// Sets the member that \p A names, allocating a list from \p Alloc. |
| 278 | /// Returns false if the value is invalid. |
| 279 | bool apply(const llvm::opt::Arg &A, llvm::BumpPtrAllocator &Alloc); |
| 280 | }; |
| 281 | } // namespace llvm |
| 282 | #endif // OPTIONS_STRUCT_DECL |
| 283 | |
| 284 | #ifdef OPTIONS_STRUCT_DEFS |
| 285 | #undef OPTIONS_STRUCT_DEFS |
| 286 | llvm::RISCVOptions llvm::RISCVOptions::Global; |
| 287 | |
| 288 | namespace { |
| 289 | enum ID : unsigned { |
| 290 | OPT_INVALID = 0, |
| 291 | OPT_INPUT, |
| 292 | OPT_UNKNOWN, |
| 293 | OPT_riscv_br_merging_base_cost, |
| 294 | OPT_riscv_br_merging_likely_bias, |
| 295 | OPT_riscv_br_merging_unlikely_bias, |
| 296 | OPT_riscv_constant_pool_for_large_ints, |
| 297 | OPT_riscv_cost_per_use, |
| 298 | OPT_riscv_enable_cfi_instr_inserter, |
| 299 | OPT_riscv_enable_copy_propagation, |
| 300 | OPT_riscv_enable_copyelim, |
| 301 | OPT_riscv_enable_dead_defs, |
| 302 | OPT_riscv_enable_global_merge, |
| 303 | OPT_riscv_enable_loop_data_prefetch, |
| 304 | OPT_riscv_enable_machine_combiner, |
| 305 | OPT_riscv_enable_pipeliner, |
| 306 | OPT_riscv_enable_sink_fold, |
| 307 | OPT_riscv_force_machine_combiner_strategy, |
| 308 | OPT_riscv_frm_insert_opt, |
| 309 | OPT_riscv_insert_vsetvli_whole_vector_register_move_valid_vtype, |
| 310 | OPT_riscv_landing_pad_label, |
| 311 | OPT_riscv_load_store_scan_limit, |
| 312 | OPT_riscv_lower_ext_max_web_size, |
| 313 | OPT_riscv_lower_form_vw_w_with_splat, |
| 314 | OPT_riscv_lower_fp_repeated_divisors, |
| 315 | OPT_riscv_lower_fpimm_cost, |
| 316 | OPT_riscv_max_build_ints_cost, |
| 317 | OPT_riscv_min_jump_table_entries, |
| 318 | OPT_riscv_mips_ccmov, |
| 319 | OPT_riscv_mips_load_store_pairs, |
| 320 | OPT_riscv_or_like_select, |
| 321 | OPT_riscv_outliner_regsave, |
| 322 | OPT_riscv_prefer_whole_register_move, |
| 323 | OPT_riscv_reassoc_shl_addi_add, |
| 324 | OPT_riscv_regalloc_hints, |
| 325 | OPT_riscv_sched_load_latency, |
| 326 | OPT_riscv_sched_mispredict_penalty, |
| 327 | OPT_riscv_select_opt, |
| 328 | OPT_riscv_sextw_removal, |
| 329 | OPT_riscv_strip_w_suffix, |
| 330 | OPT_riscv_use_aa, |
| 331 | OPT_riscv_use_rematerializable_movimm, |
| 332 | OPT_riscv_v_min_trip_count, |
| 333 | OPT_riscv_v_register_bit_width_lmul, |
| 334 | OPT_riscv_v_slp_max_vf, |
| 335 | OPT_riscv_v_vector_bits_max, |
| 336 | OPT_riscv_v_vector_bits_min, |
| 337 | OPT_riscv_vector_mask_mutation, |
| 338 | OPT_riscv_zilsd_max_reschedule_distance, |
| 339 | OPT_riscv_zilsd_opt, |
| 340 | }; |
| 341 | } // namespace |
| 342 | |
| 343 | const llvm::opt::OptTable &llvm::RISCVOptions::optTable() { |
| 344 | static const llvm::opt::LibraryOptTable T(optionTables()); |
| 345 | return T; |
| 346 | } |
| 347 | |
| 348 | bool llvm::RISCVOptions::apply(const llvm::opt::Arg &A, llvm::BumpPtrAllocator &Alloc) { |
| 349 | switch (A.getOption().getID()) { |
| 350 | case OPT_riscv_br_merging_base_cost: |
| 351 | return llvm::opt::parseArgValue(A.getValue(), br_merging_base_cost, Alloc); |
| 352 | case OPT_riscv_br_merging_likely_bias: |
| 353 | return llvm::opt::parseArgValue(A.getValue(), br_merging_likely_bias, Alloc); |
| 354 | case OPT_riscv_br_merging_unlikely_bias: |
| 355 | return llvm::opt::parseArgValue(A.getValue(), br_merging_unlikely_bias, Alloc); |
| 356 | case OPT_riscv_constant_pool_for_large_ints: |
| 357 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , constant_pool_for_large_ints, Alloc); |
| 358 | case OPT_riscv_cost_per_use: |
| 359 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , cost_per_use, Alloc); |
| 360 | case OPT_riscv_enable_cfi_instr_inserter: |
| 361 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_cfi_instr_inserter, Alloc); |
| 362 | case OPT_riscv_enable_copy_propagation: |
| 363 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_copy_propagation, Alloc); |
| 364 | case OPT_riscv_enable_copyelim: |
| 365 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_copyelim, Alloc); |
| 366 | case OPT_riscv_enable_dead_defs: |
| 367 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_dead_defs, Alloc); |
| 368 | case OPT_riscv_enable_global_merge: |
| 369 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_global_merge, Alloc); |
| 370 | case OPT_riscv_enable_loop_data_prefetch: |
| 371 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_loop_data_prefetch, Alloc); |
| 372 | case OPT_riscv_enable_machine_combiner: |
| 373 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_machine_combiner, Alloc); |
| 374 | case OPT_riscv_enable_pipeliner: |
| 375 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_pipeliner, Alloc); |
| 376 | case OPT_riscv_enable_sink_fold: |
| 377 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , enable_sink_fold, Alloc); |
| 378 | case OPT_riscv_force_machine_combiner_strategy: |
| 379 | return llvm::opt::parseArgValue(A.getValue(), force_machine_combiner_strategy, Alloc, [](llvm::StringRef V, auto &X) { |
| 380 | if (V == "local" ) { |
| 381 | X = MachineTraceStrategy::TS_Local; |
| 382 | return true; |
| 383 | } |
| 384 | if (V == "min-instr" ) { |
| 385 | X = MachineTraceStrategy::TS_MinInstrCount; |
| 386 | return true; |
| 387 | } |
| 388 | return false; |
| 389 | }); |
| 390 | case OPT_riscv_frm_insert_opt: |
| 391 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , frm_insert_opt, Alloc); |
| 392 | case OPT_riscv_insert_vsetvli_whole_vector_register_move_valid_vtype: |
| 393 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , insert_vsetvli_whole_vector_register_move_valid_vtype, Alloc); |
| 394 | case OPT_riscv_landing_pad_label: |
| 395 | return llvm::opt::parseArgValue(A.getValue(), landing_pad_label, Alloc); |
| 396 | case OPT_riscv_load_store_scan_limit: |
| 397 | return llvm::opt::parseArgValue(A.getValue(), load_store_scan_limit, Alloc); |
| 398 | case OPT_riscv_lower_ext_max_web_size: |
| 399 | return llvm::opt::parseArgValue(A.getValue(), lower_ext_max_web_size, Alloc); |
| 400 | case OPT_riscv_lower_form_vw_w_with_splat: |
| 401 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , lower_form_vw_w_with_splat, Alloc); |
| 402 | case OPT_riscv_lower_fp_repeated_divisors: |
| 403 | return llvm::opt::parseArgValue(A.getValue(), lower_fp_repeated_divisors, Alloc); |
| 404 | case OPT_riscv_lower_fpimm_cost: |
| 405 | return llvm::opt::parseArgValue(A.getValue(), lower_fpimm_cost, Alloc); |
| 406 | case OPT_riscv_max_build_ints_cost: |
| 407 | return llvm::opt::parseArgValue(A.getValue(), max_build_ints_cost, Alloc); |
| 408 | case OPT_riscv_min_jump_table_entries: |
| 409 | return llvm::opt::parseArgValue(A.getValue(), min_jump_table_entries, Alloc); |
| 410 | case OPT_riscv_mips_ccmov: |
| 411 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , mips_ccmov, Alloc); |
| 412 | case OPT_riscv_mips_load_store_pairs: |
| 413 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , mips_load_store_pairs, Alloc); |
| 414 | case OPT_riscv_or_like_select: |
| 415 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , or_like_select, Alloc); |
| 416 | case OPT_riscv_outliner_regsave: |
| 417 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , outliner_regsave, Alloc); |
| 418 | case OPT_riscv_prefer_whole_register_move: |
| 419 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , prefer_whole_register_move, Alloc); |
| 420 | case OPT_riscv_reassoc_shl_addi_add: |
| 421 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , reassoc_shl_addi_add, Alloc); |
| 422 | case OPT_riscv_regalloc_hints: |
| 423 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , regalloc_hints, Alloc); |
| 424 | case OPT_riscv_sched_load_latency: |
| 425 | return llvm::opt::parseArgValue(A.getValue(), sched_load_latency, Alloc); |
| 426 | case OPT_riscv_sched_mispredict_penalty: |
| 427 | return llvm::opt::parseArgValue(A.getValue(), sched_mispredict_penalty, Alloc); |
| 428 | case OPT_riscv_select_opt: |
| 429 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , select_opt, Alloc); |
| 430 | case OPT_riscv_sextw_removal: |
| 431 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , sextw_removal, Alloc); |
| 432 | case OPT_riscv_strip_w_suffix: |
| 433 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , strip_w_suffix, Alloc); |
| 434 | case OPT_riscv_use_aa: |
| 435 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , use_aa, Alloc); |
| 436 | case OPT_riscv_use_rematerializable_movimm: |
| 437 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , use_rematerializable_movimm, Alloc); |
| 438 | case OPT_riscv_v_min_trip_count: |
| 439 | return llvm::opt::parseArgValue(A.getValue(), v_min_trip_count, Alloc); |
| 440 | case OPT_riscv_v_register_bit_width_lmul: |
| 441 | return llvm::opt::parseArgValue(A.getValue(), v_register_bit_width_lmul, Alloc); |
| 442 | case OPT_riscv_v_slp_max_vf: |
| 443 | return llvm::opt::parseArgValue(A.getValue(), v_slp_max_vf, Alloc); |
| 444 | case OPT_riscv_v_vector_bits_max: |
| 445 | return llvm::opt::parseArgValue(A.getValue(), v_vector_bits_max, Alloc); |
| 446 | case OPT_riscv_v_vector_bits_min: |
| 447 | return llvm::opt::parseArgValue(A.getValue(), v_vector_bits_min, Alloc); |
| 448 | case OPT_riscv_vector_mask_mutation: |
| 449 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , vector_mask_mutation, Alloc); |
| 450 | case OPT_riscv_zilsd_max_reschedule_distance: |
| 451 | return llvm::opt::parseArgValue(A.getValue(), zilsd_max_reschedule_distance, Alloc); |
| 452 | case OPT_riscv_zilsd_opt: |
| 453 | return llvm::opt::parseArgValue(A.getNumValues() ? A.getValue() : "true" , zilsd_opt, Alloc); |
| 454 | } |
| 455 | llvm_unreachable("option without a member" ); |
| 456 | } |
| 457 | #endif // OPTIONS_STRUCT_DEFS |
| 458 | ///////// |
| 459 | // ValuesCode |
| 460 | |
| 461 | #ifdef OPTTABLE_VALUES_CODE |
| 462 | static llvm::StringRef getOptionValuesCode(unsigned ID) { |
| 463 | switch (ID) { |
| 464 | } |
| 465 | return {}; |
| 466 | } |
| 467 | #undef OPTTABLE_VALUES_CODE |
| 468 | #endif // OPTTABLE_VALUES_CODE |
| 469 | ///////// |
| 470 | // Groups |
| 471 | |
| 472 | #ifdef OPTION |
| 473 | |
| 474 | ////////// |
| 475 | // Options |
| 476 | |
| 477 | OPTION(0, 6 /* <input> */, INPUT, Input, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 0, 0, 0, 0, 0) |
| 478 | OPTION(0, 14 /* <unknown> */, UNKNOWN, Unknown, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 0, 0, 0, 0, 0) |
| 479 | OPTION(1, 24 /* -riscv-br-merging-base-cost */, anonymous_1, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 52, 0, 0, 0, 0) |
| 480 | OPTION(1, 415 /* -riscv-br-merging-likely-bias */, anonymous_2, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 445, 0, 0, 0, 0) |
| 481 | OPTION(1, 837 /* -riscv-br-merging-unlikely-bias */, anonymous_3, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 869, 0, 0, 0, 0) |
| 482 | OPTION(1, 1269 /* -riscv-constant-pool-for-large-ints */, anonymous_20, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1305, 0, 0, 0, 0) |
| 483 | OPTION(1, 1351 /* -riscv-cost-per-use */, anonymous_18, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1371, 0, 0, 0, 0) |
| 484 | OPTION(1, 1373 /* -riscv-enable-cfi-instr-inserter */, anonymous_28, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1406, 0, 0, 0, 0) |
| 485 | OPTION(1, 1449 /* -riscv-enable-copy-propagation */, anonymous_29, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1480, 0, 0, 0, 0) |
| 486 | OPTION(1, 1531 /* -riscv-enable-copyelim */, anonymous_30, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1554, 0, 0, 0, 0) |
| 487 | OPTION(1, 1597 /* -riscv-enable-dead-defs */, anonymous_31, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1621, 0, 0, 0, 0) |
| 488 | OPTION(1, 1713 /* -riscv-enable-global-merge */, anonymous_32, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1740, 0, 0, 0, 0) |
| 489 | OPTION(1, 1769 /* -riscv-enable-loop-data-prefetch */, anonymous_33, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1802, 0, 0, 0, 0) |
| 490 | OPTION(1, 1837 /* -riscv-enable-machine-combiner */, anonymous_34, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1868, 0, 0, 0, 0) |
| 491 | OPTION(1, 1901 /* -riscv-enable-pipeliner */, anonymous_35, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1925, 0, 0, 0, 0) |
| 492 | OPTION(1, 1961 /* -riscv-enable-sink-fold */, anonymous_36, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1985, 0, 0, 0, 0) |
| 493 | OPTION(1, 2034 /* -riscv-force-machine-combiner-strategy */, anonymous_12, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 2073, 0, 2160, 2178, 0) |
| 494 | OPTION(1, 2194 /* -riscv-frm-insert-opt */, anonymous_10, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 2216, 0, 0, 0, 0) |
| 495 | OPTION(1, 2247 /* -riscv-insert-vsetvli-whole-vector-register-move-valid-vtype */, anonymous_11, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 2308, 0, 0, 0, 0) |
| 496 | OPTION(1, 2385 /* -riscv-landing-pad-label */, anonymous_9, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 2410, 0, 0, 0, 0) |
| 497 | OPTION(1, 2451 /* -riscv-load-store-scan-limit */, anonymous_15, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1371, 0, 0, 0, 0) |
| 498 | OPTION(1, 2480 /* -riscv-lower-ext-max-web-size */, anonymous_4, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 2510, 0, 0, 0, 0) |
| 499 | OPTION(1, 2619 /* -riscv-lower-form-vw-w-with-splat */, anonymous_5, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 2653, 0, 0, 0, 0) |
| 500 | OPTION(1, 2729 /* -riscv-lower-fp-repeated-divisors */, anonymous_6, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 2763, 0, 0, 0, 0) |
| 501 | OPTION(1, 2875 /* -riscv-lower-fpimm-cost */, anonymous_7, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 2899, 0, 0, 0, 0) |
| 502 | OPTION(1, 3002 /* -riscv-max-build-ints-cost */, anonymous_21, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3029, 0, 0, 0, 0) |
| 503 | OPTION(1, 3073 /* -riscv-min-jump-table-entries */, anonymous_22, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3103, 0, 0, 0, 0) |
| 504 | OPTION(1, 3162 /* -riscv-mips-ccmov */, anonymous_23, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3180, 0, 0, 0, 0) |
| 505 | OPTION(1, 3209 /* -riscv-mips-load-store-pairs */, anonymous_24, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3238, 0, 0, 0, 0) |
| 506 | OPTION(1, 3283 /* -riscv-or-like-select */, anonymous_41, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 1371, 0, 0, 0, 0) |
| 507 | OPTION(1, 3305 /* -riscv-outliner-regsave */, anonymous_13, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3329, 0, 0, 0, 0) |
| 508 | OPTION(1, 3445 /* -riscv-prefer-whole-register-move */, anonymous_14, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3479, 0, 0, 0, 0) |
| 509 | OPTION(1, 3527 /* -riscv-reassoc-shl-addi-add */, anonymous_8, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3555, 0, 0, 0, 0) |
| 510 | OPTION(1, 3625 /* -riscv-regalloc-hints */, anonymous_19, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3647, 0, 0, 0, 0) |
| 511 | OPTION(1, 3696 /* -riscv-sched-load-latency */, anonymous_25, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3722, 0, 0, 0, 0) |
| 512 | OPTION(1, 3834 /* -riscv-sched-mispredict-penalty */, anonymous_26, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 3866, 0, 0, 0, 0) |
| 513 | OPTION(1, 3984 /* -riscv-select-opt */, anonymous_37, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4002, 0, 0, 0, 0) |
| 514 | OPTION(1, 4040 /* -riscv-sextw-removal */, anonymous_16, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4061, 0, 0, 0, 0) |
| 515 | OPTION(1, 4086 /* -riscv-strip-w-suffix */, anonymous_17, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4108, 0, 0, 0, 0) |
| 516 | OPTION(1, 4130 /* -riscv-use-aa */, anonymous_27, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4144, 0, 0, 0, 0) |
| 517 | OPTION(1, 4180 /* -riscv-use-rematerializable-movimm */, anonymous_0, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4215, 0, 0, 0, 0) |
| 518 | OPTION(1, 4299 /* -riscv-v-min-trip-count */, anonymous_42, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4323, 0, 0, 0, 0) |
| 519 | OPTION(1, 4405 /* -riscv-v-register-bit-width-lmul */, anonymous_43, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4438, 0, 0, 0, 0) |
| 520 | OPTION(1, 4564 /* -riscv-v-slp-max-vf */, anonymous_44, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4584, 0, 0, 0, 0) |
| 521 | OPTION(1, 4673 /* -riscv-v-vector-bits-max */, anonymous_38, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4698, 0, 0, 0, 0) |
| 522 | OPTION(1, 4801 /* -riscv-v-vector-bits-min */, anonymous_39, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 4826, 0, 0, 0, 0) |
| 523 | OPTION(1, 5048 /* -riscv-vector-mask-mutation */, anonymous_40, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 5076, 0, 0, 0, 0) |
| 524 | OPTION(1, 5119 /* -riscv-zilsd-max-reschedule-distance */, anonymous_45, SeparateOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 5156, 0, 0, 0, 0) |
| 525 | OPTION(1, 5214 /* -riscv-zilsd-opt */, anonymous_46, FlagOrEq, INVALID, INVALID, 0, 0, static_cast<unsigned>(DefaultVis), 0, 5231, 0, 0, 0, 0) |
| 526 | #endif // OPTION |
| 527 | |
| 528 | #ifdef SIMPLE_ENUM_VALUE_TABLE |
| 529 | |
| 530 | struct SimpleEnumValue { |
| 531 | const char *Name; |
| 532 | unsigned Value; |
| 533 | }; |
| 534 | |
| 535 | struct SimpleEnumValueTable { |
| 536 | const SimpleEnumValue *Table; |
| 537 | unsigned Size; |
| 538 | }; |
| 539 | static const SimpleEnumValueTable SimpleEnumValueTables[] = {}; |
| 540 | static const unsigned SimpleEnumValueTablesSize = std::size(SimpleEnumValueTables); |
| 541 | #endif // SIMPLE_ENUM_VALUE_TABLE |
| 542 | |