1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t SPIRVRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask SPIRVLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t SPIRVSubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char SPIRVRegStrings[] = {
30 /* 0 */ "vfID0\000"
31 /* 6 */ "viID0\000"
32 /* 12 */ "vpID0\000"
33 /* 18 */ "TYPE0\000"
34};
35#ifdef __GNUC__
36#pragma GCC diagnostic pop
37#endif
38
39extern const MCRegisterDesc SPIRVRegDesc[] = { // Descriptors
40 { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
41 { .Name: 2, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
42 { .Name: 18, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
43 { .Name: 1, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
44 { .Name: 13, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
45 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
46 { .Name: 6, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
47 { .Name: 12, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
48};
49
50extern const MCPhysReg SPIRVRegUnitRoots[][2] = {
51 { SPIRV::ID0 },
52 { SPIRV::TYPE0 },
53 { SPIRV::fID0 },
54 { SPIRV::pID0 },
55 { SPIRV::vfID0 },
56 { SPIRV::viID0 },
57 { SPIRV::vpID0 },
58};
59
60namespace {
61
62// Register classes...
63 // ANY Register Class...
64 const MCPhysReg ANY[] = {
65 SPIRV::TYPE0, SPIRV::ID0, SPIRV::fID0, SPIRV::pID0, SPIRV::viID0, SPIRV::vfID0, SPIRV::vpID0,
66 };
67
68 // ANY Bit set.
69 const uint8_t ANYBits[] = {
70 0xfe,
71 };
72
73 // ID Register Class...
74 const MCPhysReg ID[] = {
75 SPIRV::ID0, SPIRV::fID0, SPIRV::pID0, SPIRV::viID0, SPIRV::vfID0, SPIRV::vpID0,
76 };
77
78 // ID Bit set.
79 const uint8_t IDBits[] = {
80 0xfa,
81 };
82
83 // TYPE Register Class...
84 const MCPhysReg TYPE[] = {
85 SPIRV::TYPE0,
86 };
87
88 // TYPE Bit set.
89 const uint8_t TYPEBits[] = {
90 0x04,
91 };
92
93 // fID Register Class...
94 const MCPhysReg fID[] = {
95 SPIRV::fID0,
96 };
97
98 // fID Bit set.
99 const uint8_t fIDBits[] = {
100 0x08,
101 };
102
103 // iID Register Class...
104 const MCPhysReg iID[] = {
105 SPIRV::ID0,
106 };
107
108 // iID Bit set.
109 const uint8_t iIDBits[] = {
110 0x02,
111 };
112
113 // pID Register Class...
114 const MCPhysReg pID[] = {
115 SPIRV::pID0,
116 };
117
118 // pID Bit set.
119 const uint8_t pIDBits[] = {
120 0x10,
121 };
122
123 // vpID Register Class...
124 const MCPhysReg vpID[] = {
125 SPIRV::vpID0,
126 };
127
128 // vpID Bit set.
129 const uint8_t vpIDBits[] = {
130 0x80,
131 };
132
133 // vfID Register Class...
134 const MCPhysReg vfID[] = {
135 SPIRV::vfID0,
136 };
137
138 // vfID Bit set.
139 const uint8_t vfIDBits[] = {
140 0x20,
141 };
142
143 // viID Register Class...
144 const MCPhysReg viID[] = {
145 SPIRV::viID0,
146 };
147
148 // viID Bit set.
149 const uint8_t viIDBits[] = {
150 0x40,
151 };
152
153} // namespace
154
155#ifdef __GNUC__
156#pragma GCC diagnostic push
157#pragma GCC diagnostic ignored "-Woverlength-strings"
158#endif
159extern const char SPIRVRegClassStrings[] = {
160 /* 0 */ "vfID\000"
161 /* 5 */ "viID\000"
162 /* 10 */ "vpID\000"
163 /* 15 */ "TYPE\000"
164 /* 20 */ "ANY\000"
165};
166#ifdef __GNUC__
167#pragma GCC diagnostic pop
168#endif
169
170extern const MCRegisterClass SPIRVMCRegisterClasses[] = {
171 { .RegsBegin: ANY, .RegSet: ANYBits, .NameIdx: 20, .RegSizeInBits: 64, .RegsSize: 7, .RegSetSize: sizeof(ANYBits), .ID: SPIRV::ANYRegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
172 { .RegsBegin: ID, .RegSet: IDBits, .NameIdx: 2, .RegSizeInBits: 64, .RegsSize: 6, .RegSetSize: sizeof(IDBits), .ID: SPIRV::IDRegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
173 { .RegsBegin: TYPE, .RegSet: TYPEBits, .NameIdx: 15, .RegSizeInBits: 64, .RegsSize: 1, .RegSetSize: sizeof(TYPEBits), .ID: SPIRV::TYPERegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
174 { .RegsBegin: fID, .RegSet: fIDBits, .NameIdx: 1, .RegSizeInBits: 64, .RegsSize: 1, .RegSetSize: sizeof(fIDBits), .ID: SPIRV::fIDRegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
175 { .RegsBegin: iID, .RegSet: iIDBits, .NameIdx: 6, .RegSizeInBits: 64, .RegsSize: 1, .RegSetSize: sizeof(iIDBits), .ID: SPIRV::iIDRegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
176 { .RegsBegin: pID, .RegSet: pIDBits, .NameIdx: 11, .RegSizeInBits: 64, .RegsSize: 1, .RegSetSize: sizeof(pIDBits), .ID: SPIRV::pIDRegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
177 { .RegsBegin: vpID, .RegSet: vpIDBits, .NameIdx: 10, .RegSizeInBits: 64, .RegsSize: 1, .RegSetSize: sizeof(vpIDBits), .ID: SPIRV::vpIDRegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
178 { .RegsBegin: vfID, .RegSet: vfIDBits, .NameIdx: 0, .RegSizeInBits: 128, .RegsSize: 1, .RegSetSize: sizeof(vfIDBits), .ID: SPIRV::vfIDRegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
179 { .RegsBegin: viID, .RegSet: viIDBits, .NameIdx: 5, .RegSizeInBits: 128, .RegsSize: 1, .RegSetSize: sizeof(viIDBits), .ID: SPIRV::viIDRegClassID, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
180};
181
182extern const uint16_t SPIRVRegEncodingTable[] = {
183 0,
184 0,
185 0,
186 0,
187 0,
188 0,
189 0,
190 0,
191};
192static inline void InitSPIRVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
193 RI->InitMCRegisterInfo(D: SPIRVRegDesc, NR: 8, RA, PC, C: SPIRVMCRegisterClasses, NC: 9, RURoots: SPIRVRegUnitRoots, NRU: 7, DL: SPIRVRegDiffLists, RUMS: SPIRVLaneMaskLists, Strings: SPIRVRegStrings, ClassStrings: SPIRVRegClassStrings, SubIndices: SPIRVSubRegIdxLists, NumIndices: 1,
194RET: SPIRVRegEncodingTable, RUI: nullptr);
195
196}
197
198
199} // namespace llvm
200