1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t SPIRVRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask SPIRVLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t SPIRVSubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char SPIRVRegStrings[] = {
30 /* 0 */ "vfID0\000"
31 /* 6 */ "viID0\000"
32 /* 12 */ "vpID0\000"
33 /* 18 */ "TYPE0\000"
34};
35#ifdef __GNUC__
36#pragma GCC diagnostic pop
37#endif
38
39extern const MCRegisterDesc SPIRVRegDesc[] = { // Descriptors
40 { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
41 { .Name: 2, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
42 { .Name: 18, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
43 { .Name: 1, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
44 { .Name: 13, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
45 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
46 { .Name: 6, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
47 { .Name: 12, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
48};
49
50extern const MCPhysReg SPIRVRegUnitRoots[][2] = {
51 { SPIRV::ID0 },
52 { SPIRV::TYPE0 },
53 { SPIRV::fID0 },
54 { SPIRV::pID0 },
55 { SPIRV::vfID0 },
56 { SPIRV::viID0 },
57 { SPIRV::vpID0 },
58};
59
60// Register classes...
61
62#ifdef __GNUC__
63#pragma GCC diagnostic push
64#pragma GCC diagnostic ignored "-Woverlength-strings"
65#endif
66extern const char SPIRVRegClassStrings[] = {
67 /* 0 */ "vfID\000"
68 /* 5 */ "viID\000"
69 /* 10 */ "vpID\000"
70 /* 15 */ "TYPE\000"
71 /* 20 */ "ANY\000"
72};
73#ifdef __GNUC__
74#pragma GCC diagnostic pop
75#endif
76
77using SPIRVRegisterClassStorage = MCRegisterClassStorage<9, 20, 9, 9, 1, 14>;
78extern const MCRegisterClassStorage<9, 20, 9, 9, 1, 14> SPIRVMCRegisterClassStorage = {
79 .Classes: {
80 {
81 offsetof(SPIRVRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
82 offsetof(SPIRVRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
83 .NameIdx: 20,
84 .RegSizeInBits: 64,
85 .RegsSize: 7,
86 .RegSetSize: 1,
87 .ID: SPIRV::ANYRegClassID,
88 .CopyCost: 1, /* CopyCost */
89 .Allocatable: true, /* Allocatable */
90 .BaseClass: false,
91 offsetof(SPIRVRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
92 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
93 .LaneMask: LaneBitmask(0x0000000000000001),
94 .AllocationPriority: 0,
95 .GlobalPriority: false,
96 .TSFlags: 0x00, /* TSFlags */
97 .SpillStackID: 0, /* SpillStackID */
98 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
99 .CoveredBySubRegs: false, /* CoveredBySubRegs */
100 offsetof(SPIRVRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
101 .SuperClassesSize: 0
102 },
103 {
104 offsetof(SPIRVRegisterClassStorage, Regs[7]) - 1 * sizeof(MCRegisterClass),
105 offsetof(SPIRVRegisterClassStorage, BitSets[1]) - 1 * sizeof(MCRegisterClass),
106 .NameIdx: 2,
107 .RegSizeInBits: 64,
108 .RegsSize: 6,
109 .RegSetSize: 1,
110 .ID: SPIRV::IDRegClassID,
111 .CopyCost: 1, /* CopyCost */
112 .Allocatable: true, /* Allocatable */
113 .BaseClass: false,
114 offsetof(SPIRVRegisterClassStorage, SubClassMasks[1]) - 1 * sizeof(MCRegisterClass),
115 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 1 * sizeof(MCRegisterClass),
116 .LaneMask: LaneBitmask(0x0000000000000001),
117 .AllocationPriority: 0,
118 .GlobalPriority: false,
119 .TSFlags: 0x00, /* TSFlags */
120 .SpillStackID: 0, /* SpillStackID */
121 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
122 .CoveredBySubRegs: false, /* CoveredBySubRegs */
123 offsetof(SPIRVRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
124 .SuperClassesSize: 1
125 },
126 {
127 offsetof(SPIRVRegisterClassStorage, Regs[13]) - 2 * sizeof(MCRegisterClass),
128 offsetof(SPIRVRegisterClassStorage, BitSets[2]) - 2 * sizeof(MCRegisterClass),
129 .NameIdx: 15,
130 .RegSizeInBits: 64,
131 .RegsSize: 1,
132 .RegSetSize: 1,
133 .ID: SPIRV::TYPERegClassID,
134 .CopyCost: 1, /* CopyCost */
135 .Allocatable: true, /* Allocatable */
136 .BaseClass: false,
137 offsetof(SPIRVRegisterClassStorage, SubClassMasks[2]) - 2 * sizeof(MCRegisterClass),
138 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 2 * sizeof(MCRegisterClass),
139 .LaneMask: LaneBitmask(0x0000000000000001),
140 .AllocationPriority: 0,
141 .GlobalPriority: false,
142 .TSFlags: 0x00, /* TSFlags */
143 .SpillStackID: 0, /* SpillStackID */
144 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
145 .CoveredBySubRegs: false, /* CoveredBySubRegs */
146 offsetof(SPIRVRegisterClassStorage, SuperClasses[1]) - 2 * sizeof(MCRegisterClass),
147 .SuperClassesSize: 1
148 },
149 {
150 offsetof(SPIRVRegisterClassStorage, Regs[14]) - 3 * sizeof(MCRegisterClass),
151 offsetof(SPIRVRegisterClassStorage, BitSets[3]) - 3 * sizeof(MCRegisterClass),
152 .NameIdx: 1,
153 .RegSizeInBits: 64,
154 .RegsSize: 1,
155 .RegSetSize: 1,
156 .ID: SPIRV::fIDRegClassID,
157 .CopyCost: 1, /* CopyCost */
158 .Allocatable: true, /* Allocatable */
159 .BaseClass: false,
160 offsetof(SPIRVRegisterClassStorage, SubClassMasks[3]) - 3 * sizeof(MCRegisterClass),
161 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 3 * sizeof(MCRegisterClass),
162 .LaneMask: LaneBitmask(0x0000000000000001),
163 .AllocationPriority: 0,
164 .GlobalPriority: false,
165 .TSFlags: 0x00, /* TSFlags */
166 .SpillStackID: 0, /* SpillStackID */
167 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
168 .CoveredBySubRegs: false, /* CoveredBySubRegs */
169 offsetof(SPIRVRegisterClassStorage, SuperClasses[2]) - 3 * sizeof(MCRegisterClass),
170 .SuperClassesSize: 2
171 },
172 {
173 offsetof(SPIRVRegisterClassStorage, Regs[15]) - 4 * sizeof(MCRegisterClass),
174 offsetof(SPIRVRegisterClassStorage, BitSets[4]) - 4 * sizeof(MCRegisterClass),
175 .NameIdx: 6,
176 .RegSizeInBits: 64,
177 .RegsSize: 1,
178 .RegSetSize: 1,
179 .ID: SPIRV::iIDRegClassID,
180 .CopyCost: 1, /* CopyCost */
181 .Allocatable: true, /* Allocatable */
182 .BaseClass: false,
183 offsetof(SPIRVRegisterClassStorage, SubClassMasks[4]) - 4 * sizeof(MCRegisterClass),
184 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 4 * sizeof(MCRegisterClass),
185 .LaneMask: LaneBitmask(0x0000000000000001),
186 .AllocationPriority: 0,
187 .GlobalPriority: false,
188 .TSFlags: 0x00, /* TSFlags */
189 .SpillStackID: 0, /* SpillStackID */
190 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
191 .CoveredBySubRegs: false, /* CoveredBySubRegs */
192 offsetof(SPIRVRegisterClassStorage, SuperClasses[4]) - 4 * sizeof(MCRegisterClass),
193 .SuperClassesSize: 2
194 },
195 {
196 offsetof(SPIRVRegisterClassStorage, Regs[16]) - 5 * sizeof(MCRegisterClass),
197 offsetof(SPIRVRegisterClassStorage, BitSets[5]) - 5 * sizeof(MCRegisterClass),
198 .NameIdx: 11,
199 .RegSizeInBits: 64,
200 .RegsSize: 1,
201 .RegSetSize: 1,
202 .ID: SPIRV::pIDRegClassID,
203 .CopyCost: 1, /* CopyCost */
204 .Allocatable: true, /* Allocatable */
205 .BaseClass: false,
206 offsetof(SPIRVRegisterClassStorage, SubClassMasks[5]) - 5 * sizeof(MCRegisterClass),
207 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass),
208 .LaneMask: LaneBitmask(0x0000000000000001),
209 .AllocationPriority: 0,
210 .GlobalPriority: false,
211 .TSFlags: 0x00, /* TSFlags */
212 .SpillStackID: 0, /* SpillStackID */
213 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
214 .CoveredBySubRegs: false, /* CoveredBySubRegs */
215 offsetof(SPIRVRegisterClassStorage, SuperClasses[6]) - 5 * sizeof(MCRegisterClass),
216 .SuperClassesSize: 2
217 },
218 {
219 offsetof(SPIRVRegisterClassStorage, Regs[17]) - 6 * sizeof(MCRegisterClass),
220 offsetof(SPIRVRegisterClassStorage, BitSets[6]) - 6 * sizeof(MCRegisterClass),
221 .NameIdx: 10,
222 .RegSizeInBits: 64,
223 .RegsSize: 1,
224 .RegSetSize: 1,
225 .ID: SPIRV::vpIDRegClassID,
226 .CopyCost: 1, /* CopyCost */
227 .Allocatable: true, /* Allocatable */
228 .BaseClass: false,
229 offsetof(SPIRVRegisterClassStorage, SubClassMasks[6]) - 6 * sizeof(MCRegisterClass),
230 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 6 * sizeof(MCRegisterClass),
231 .LaneMask: LaneBitmask(0x0000000000000001),
232 .AllocationPriority: 0,
233 .GlobalPriority: false,
234 .TSFlags: 0x00, /* TSFlags */
235 .SpillStackID: 0, /* SpillStackID */
236 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
237 .CoveredBySubRegs: false, /* CoveredBySubRegs */
238 offsetof(SPIRVRegisterClassStorage, SuperClasses[8]) - 6 * sizeof(MCRegisterClass),
239 .SuperClassesSize: 2
240 },
241 {
242 offsetof(SPIRVRegisterClassStorage, Regs[18]) - 7 * sizeof(MCRegisterClass),
243 offsetof(SPIRVRegisterClassStorage, BitSets[7]) - 7 * sizeof(MCRegisterClass),
244 .NameIdx: 0,
245 .RegSizeInBits: 128,
246 .RegsSize: 1,
247 .RegSetSize: 1,
248 .ID: SPIRV::vfIDRegClassID,
249 .CopyCost: 1, /* CopyCost */
250 .Allocatable: true, /* Allocatable */
251 .BaseClass: false,
252 offsetof(SPIRVRegisterClassStorage, SubClassMasks[7]) - 7 * sizeof(MCRegisterClass),
253 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 7 * sizeof(MCRegisterClass),
254 .LaneMask: LaneBitmask(0x0000000000000001),
255 .AllocationPriority: 0,
256 .GlobalPriority: false,
257 .TSFlags: 0x00, /* TSFlags */
258 .SpillStackID: 0, /* SpillStackID */
259 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
260 .CoveredBySubRegs: false, /* CoveredBySubRegs */
261 offsetof(SPIRVRegisterClassStorage, SuperClasses[10]) - 7 * sizeof(MCRegisterClass),
262 .SuperClassesSize: 2
263 },
264 {
265 offsetof(SPIRVRegisterClassStorage, Regs[19]) - 8 * sizeof(MCRegisterClass),
266 offsetof(SPIRVRegisterClassStorage, BitSets[8]) - 8 * sizeof(MCRegisterClass),
267 .NameIdx: 5,
268 .RegSizeInBits: 128,
269 .RegsSize: 1,
270 .RegSetSize: 1,
271 .ID: SPIRV::viIDRegClassID,
272 .CopyCost: 1, /* CopyCost */
273 .Allocatable: true, /* Allocatable */
274 .BaseClass: false,
275 offsetof(SPIRVRegisterClassStorage, SubClassMasks[8]) - 8 * sizeof(MCRegisterClass),
276 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 8 * sizeof(MCRegisterClass),
277 .LaneMask: LaneBitmask(0x0000000000000001),
278 .AllocationPriority: 0,
279 .GlobalPriority: false,
280 .TSFlags: 0x00, /* TSFlags */
281 .SpillStackID: 0, /* SpillStackID */
282 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
283 .CoveredBySubRegs: false, /* CoveredBySubRegs */
284 offsetof(SPIRVRegisterClassStorage, SuperClasses[12]) - 8 * sizeof(MCRegisterClass),
285 .SuperClassesSize: 2
286 },
287 },
288 .Regs: {
289 /* 0 */ SPIRV::TYPE0, SPIRV::ID0, SPIRV::fID0, SPIRV::pID0, SPIRV::viID0, SPIRV::vfID0, SPIRV::vpID0,
290 /* 7 */ SPIRV::ID0, SPIRV::fID0, SPIRV::pID0, SPIRV::viID0, SPIRV::vfID0, SPIRV::vpID0,
291 /* 13 */ SPIRV::TYPE0,
292 /* 14 */ SPIRV::fID0,
293 /* 15 */ SPIRV::ID0,
294 /* 16 */ SPIRV::pID0,
295 /* 17 */ SPIRV::vpID0,
296 /* 18 */ SPIRV::vfID0,
297 /* 19 */ SPIRV::viID0,
298 },
299 .BitSets: {
300 /* 0 */ 0xfe,
301 /* 1 */ 0xfa,
302 /* 2 */ 0x04,
303 /* 3 */ 0x08,
304 /* 4 */ 0x02,
305 /* 5 */ 0x10,
306 /* 6 */ 0x80,
307 /* 7 */ 0x20,
308 /* 8 */ 0x40,
309 },
310 .SubClassMasks: {
311 // 0 ANY
312 0x000001ff,
313 // 1 ID
314 0x000001fa,
315 // 2 TYPE
316 0x00000004,
317 // 3 fID
318 0x00000008,
319 // 4 iID
320 0x00000010,
321 // 5 pID
322 0x00000020,
323 // 6 vpID
324 0x00000040,
325 // 7 vfID
326 0x00000080,
327 // 8 viID
328 0x00000100,
329 },
330 .SuperRegIdxSeqs: {
331 /* 0 */ 0,
332 },
333 .SuperClasses: {
334 /* 0 ANY */
335 /* 0 ID */ SPIRV::ANYRegClassID,
336 /* 1 TYPE */ SPIRV::ANYRegClassID,
337 /* 2 fID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
338 /* 4 iID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
339 /* 6 pID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
340 /* 8 vpID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
341 /* 10 vfID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
342 /* 12 viID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
343 }
344};
345
346const MCRegisterClass &getSPIRVMCRegisterClass(unsigned RC) {
347 return SPIRVMCRegisterClassStorage.Classes[RC];
348}
349
350extern const uint16_t SPIRVRegEncodingTable[] = {
351 0,
352 0,
353 0,
354 0,
355 0,
356 0,
357 0,
358 0,
359};
360static inline void InitSPIRVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
361 RI->InitMCRegisterInfo(D: SPIRVRegDesc, NR: 8, RA, PC, C: SPIRVMCRegisterClassStorage.Classes, NC: 9, RURoots: SPIRVRegUnitRoots, NRU: 7, DL: SPIRVRegDiffLists, RUMS: SPIRVLaneMaskLists, Strings: SPIRVRegStrings, ClassStrings: SPIRVRegClassStrings, SubIndices: SPIRVSubRegIdxLists, NumIndices: 1,
362RET: SPIRVRegEncodingTable, RUI: nullptr);
363
364}
365
366
367} // namespace llvm
368