1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t SPIRVRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask SPIRVLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t SPIRVSubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char SPIRVRegStrings[] = {
30 /* 0 */ "vfID0\000"
31 /* 6 */ "viID0\000"
32 /* 12 */ "vpID0\000"
33 /* 18 */ "TYPE0\000"
34};
35#ifdef __GNUC__
36#pragma GCC diagnostic pop
37#endif
38
39extern const MCRegisterDesc SPIRVRegDesc[] = { // Descriptors
40 { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
41 { .Name: 2, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
42 { .Name: 18, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
43 { .Name: 1, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
44 { .Name: 13, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
45 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
46 { .Name: 6, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
47 { .Name: 12, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
48};
49
50extern const MCPhysReg SPIRVRegUnitRoots[][2] = {
51 { SPIRV::ID0 },
52 { SPIRV::TYPE0 },
53 { SPIRV::fID0 },
54 { SPIRV::pID0 },
55 { SPIRV::vfID0 },
56 { SPIRV::viID0 },
57 { SPIRV::vpID0 },
58};
59
60// Register classes...
61
62#ifdef __GNUC__
63#pragma GCC diagnostic push
64#pragma GCC diagnostic ignored "-Woverlength-strings"
65#endif
66extern const char SPIRVRegClassStrings[] = {
67 /* 0 */ "vfID\000"
68 /* 5 */ "viID\000"
69 /* 10 */ "vpID\000"
70 /* 15 */ "TYPE\000"
71 /* 20 */ "ANY\000"
72};
73#ifdef __GNUC__
74#pragma GCC diagnostic pop
75#endif
76
77using SPIRVRegisterClassStorage = MCRegisterClassStorage<9, 20, 9, 9, 1, 14>;
78extern const MCRegisterClassStorage<9, 20, 9, 9, 1, 14> SPIRVMCRegisterClassStorage = {
79 .Classes: {
80 {
81 offsetof(SPIRVRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
82 offsetof(SPIRVRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
83 .NameIdx: 20,
84 .RegSizeInBits: 64,
85 .RegsSize: 7,
86 .RegSetBegin: 1, /* MinRegVal */
87 .RegSetSize: 7, /* RegSetSize */
88 .ID: SPIRV::ANYRegClassID,
89 .CopyCost: 1, /* CopyCost */
90 .Allocatable: true, /* Allocatable */
91 .BaseClass: false,
92 offsetof(SPIRVRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
93 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
94 .LaneMask: LaneBitmask(0x0000000000000001),
95 .AllocationPriority: 0,
96 .GlobalPriority: false,
97 .TSFlags: 0x00, /* TSFlags */
98 .SpillStackID: 0, /* SpillStackID */
99 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
100 .CoveredBySubRegs: false, /* CoveredBySubRegs */
101 offsetof(SPIRVRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
102 .SuperClassesSize: 0
103 },
104 {
105 offsetof(SPIRVRegisterClassStorage, Regs[7]) - 1 * sizeof(MCRegisterClass),
106 offsetof(SPIRVRegisterClassStorage, BitSets[1]) - 1 * sizeof(MCRegisterClass),
107 .NameIdx: 2,
108 .RegSizeInBits: 64,
109 .RegsSize: 6,
110 .RegSetBegin: 1, /* MinRegVal */
111 .RegSetSize: 7, /* RegSetSize */
112 .ID: SPIRV::IDRegClassID,
113 .CopyCost: 1, /* CopyCost */
114 .Allocatable: true, /* Allocatable */
115 .BaseClass: false,
116 offsetof(SPIRVRegisterClassStorage, SubClassMasks[1]) - 1 * sizeof(MCRegisterClass),
117 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 1 * sizeof(MCRegisterClass),
118 .LaneMask: LaneBitmask(0x0000000000000001),
119 .AllocationPriority: 0,
120 .GlobalPriority: false,
121 .TSFlags: 0x00, /* TSFlags */
122 .SpillStackID: 0, /* SpillStackID */
123 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
124 .CoveredBySubRegs: false, /* CoveredBySubRegs */
125 offsetof(SPIRVRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
126 .SuperClassesSize: 1
127 },
128 {
129 offsetof(SPIRVRegisterClassStorage, Regs[13]) - 2 * sizeof(MCRegisterClass),
130 offsetof(SPIRVRegisterClassStorage, BitSets[2]) - 2 * sizeof(MCRegisterClass),
131 .NameIdx: 15,
132 .RegSizeInBits: 64,
133 .RegsSize: 1,
134 .RegSetBegin: 2, /* MinRegVal */
135 .RegSetSize: 1, /* RegSetSize */
136 .ID: SPIRV::TYPERegClassID,
137 .CopyCost: 1, /* CopyCost */
138 .Allocatable: true, /* Allocatable */
139 .BaseClass: false,
140 offsetof(SPIRVRegisterClassStorage, SubClassMasks[2]) - 2 * sizeof(MCRegisterClass),
141 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 2 * sizeof(MCRegisterClass),
142 .LaneMask: LaneBitmask(0x0000000000000001),
143 .AllocationPriority: 0,
144 .GlobalPriority: false,
145 .TSFlags: 0x00, /* TSFlags */
146 .SpillStackID: 0, /* SpillStackID */
147 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
148 .CoveredBySubRegs: false, /* CoveredBySubRegs */
149 offsetof(SPIRVRegisterClassStorage, SuperClasses[1]) - 2 * sizeof(MCRegisterClass),
150 .SuperClassesSize: 1
151 },
152 {
153 offsetof(SPIRVRegisterClassStorage, Regs[14]) - 3 * sizeof(MCRegisterClass),
154 offsetof(SPIRVRegisterClassStorage, BitSets[3]) - 3 * sizeof(MCRegisterClass),
155 .NameIdx: 1,
156 .RegSizeInBits: 64,
157 .RegsSize: 1,
158 .RegSetBegin: 3, /* MinRegVal */
159 .RegSetSize: 1, /* RegSetSize */
160 .ID: SPIRV::fIDRegClassID,
161 .CopyCost: 1, /* CopyCost */
162 .Allocatable: true, /* Allocatable */
163 .BaseClass: false,
164 offsetof(SPIRVRegisterClassStorage, SubClassMasks[3]) - 3 * sizeof(MCRegisterClass),
165 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 3 * sizeof(MCRegisterClass),
166 .LaneMask: LaneBitmask(0x0000000000000001),
167 .AllocationPriority: 0,
168 .GlobalPriority: false,
169 .TSFlags: 0x00, /* TSFlags */
170 .SpillStackID: 0, /* SpillStackID */
171 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
172 .CoveredBySubRegs: false, /* CoveredBySubRegs */
173 offsetof(SPIRVRegisterClassStorage, SuperClasses[2]) - 3 * sizeof(MCRegisterClass),
174 .SuperClassesSize: 2
175 },
176 {
177 offsetof(SPIRVRegisterClassStorage, Regs[15]) - 4 * sizeof(MCRegisterClass),
178 offsetof(SPIRVRegisterClassStorage, BitSets[4]) - 4 * sizeof(MCRegisterClass),
179 .NameIdx: 6,
180 .RegSizeInBits: 64,
181 .RegsSize: 1,
182 .RegSetBegin: 1, /* MinRegVal */
183 .RegSetSize: 1, /* RegSetSize */
184 .ID: SPIRV::iIDRegClassID,
185 .CopyCost: 1, /* CopyCost */
186 .Allocatable: true, /* Allocatable */
187 .BaseClass: false,
188 offsetof(SPIRVRegisterClassStorage, SubClassMasks[4]) - 4 * sizeof(MCRegisterClass),
189 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 4 * sizeof(MCRegisterClass),
190 .LaneMask: LaneBitmask(0x0000000000000001),
191 .AllocationPriority: 0,
192 .GlobalPriority: false,
193 .TSFlags: 0x00, /* TSFlags */
194 .SpillStackID: 0, /* SpillStackID */
195 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
196 .CoveredBySubRegs: false, /* CoveredBySubRegs */
197 offsetof(SPIRVRegisterClassStorage, SuperClasses[4]) - 4 * sizeof(MCRegisterClass),
198 .SuperClassesSize: 2
199 },
200 {
201 offsetof(SPIRVRegisterClassStorage, Regs[16]) - 5 * sizeof(MCRegisterClass),
202 offsetof(SPIRVRegisterClassStorage, BitSets[5]) - 5 * sizeof(MCRegisterClass),
203 .NameIdx: 11,
204 .RegSizeInBits: 64,
205 .RegsSize: 1,
206 .RegSetBegin: 4, /* MinRegVal */
207 .RegSetSize: 1, /* RegSetSize */
208 .ID: SPIRV::pIDRegClassID,
209 .CopyCost: 1, /* CopyCost */
210 .Allocatable: true, /* Allocatable */
211 .BaseClass: false,
212 offsetof(SPIRVRegisterClassStorage, SubClassMasks[5]) - 5 * sizeof(MCRegisterClass),
213 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass),
214 .LaneMask: LaneBitmask(0x0000000000000001),
215 .AllocationPriority: 0,
216 .GlobalPriority: false,
217 .TSFlags: 0x00, /* TSFlags */
218 .SpillStackID: 0, /* SpillStackID */
219 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
220 .CoveredBySubRegs: false, /* CoveredBySubRegs */
221 offsetof(SPIRVRegisterClassStorage, SuperClasses[6]) - 5 * sizeof(MCRegisterClass),
222 .SuperClassesSize: 2
223 },
224 {
225 offsetof(SPIRVRegisterClassStorage, Regs[17]) - 6 * sizeof(MCRegisterClass),
226 offsetof(SPIRVRegisterClassStorage, BitSets[6]) - 6 * sizeof(MCRegisterClass),
227 .NameIdx: 10,
228 .RegSizeInBits: 64,
229 .RegsSize: 1,
230 .RegSetBegin: 7, /* MinRegVal */
231 .RegSetSize: 1, /* RegSetSize */
232 .ID: SPIRV::vpIDRegClassID,
233 .CopyCost: 1, /* CopyCost */
234 .Allocatable: true, /* Allocatable */
235 .BaseClass: false,
236 offsetof(SPIRVRegisterClassStorage, SubClassMasks[6]) - 6 * sizeof(MCRegisterClass),
237 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 6 * sizeof(MCRegisterClass),
238 .LaneMask: LaneBitmask(0x0000000000000001),
239 .AllocationPriority: 0,
240 .GlobalPriority: false,
241 .TSFlags: 0x00, /* TSFlags */
242 .SpillStackID: 0, /* SpillStackID */
243 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
244 .CoveredBySubRegs: false, /* CoveredBySubRegs */
245 offsetof(SPIRVRegisterClassStorage, SuperClasses[8]) - 6 * sizeof(MCRegisterClass),
246 .SuperClassesSize: 2
247 },
248 {
249 offsetof(SPIRVRegisterClassStorage, Regs[18]) - 7 * sizeof(MCRegisterClass),
250 offsetof(SPIRVRegisterClassStorage, BitSets[7]) - 7 * sizeof(MCRegisterClass),
251 .NameIdx: 0,
252 .RegSizeInBits: 128,
253 .RegsSize: 1,
254 .RegSetBegin: 5, /* MinRegVal */
255 .RegSetSize: 1, /* RegSetSize */
256 .ID: SPIRV::vfIDRegClassID,
257 .CopyCost: 1, /* CopyCost */
258 .Allocatable: true, /* Allocatable */
259 .BaseClass: false,
260 offsetof(SPIRVRegisterClassStorage, SubClassMasks[7]) - 7 * sizeof(MCRegisterClass),
261 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 7 * sizeof(MCRegisterClass),
262 .LaneMask: LaneBitmask(0x0000000000000001),
263 .AllocationPriority: 0,
264 .GlobalPriority: false,
265 .TSFlags: 0x00, /* TSFlags */
266 .SpillStackID: 0, /* SpillStackID */
267 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
268 .CoveredBySubRegs: false, /* CoveredBySubRegs */
269 offsetof(SPIRVRegisterClassStorage, SuperClasses[10]) - 7 * sizeof(MCRegisterClass),
270 .SuperClassesSize: 2
271 },
272 {
273 offsetof(SPIRVRegisterClassStorage, Regs[19]) - 8 * sizeof(MCRegisterClass),
274 offsetof(SPIRVRegisterClassStorage, BitSets[8]) - 8 * sizeof(MCRegisterClass),
275 .NameIdx: 5,
276 .RegSizeInBits: 128,
277 .RegsSize: 1,
278 .RegSetBegin: 6, /* MinRegVal */
279 .RegSetSize: 1, /* RegSetSize */
280 .ID: SPIRV::viIDRegClassID,
281 .CopyCost: 1, /* CopyCost */
282 .Allocatable: true, /* Allocatable */
283 .BaseClass: false,
284 offsetof(SPIRVRegisterClassStorage, SubClassMasks[8]) - 8 * sizeof(MCRegisterClass),
285 offsetof(SPIRVRegisterClassStorage, SuperRegIdxSeqs[0]) - 8 * sizeof(MCRegisterClass),
286 .LaneMask: LaneBitmask(0x0000000000000001),
287 .AllocationPriority: 0,
288 .GlobalPriority: false,
289 .TSFlags: 0x00, /* TSFlags */
290 .SpillStackID: 0, /* SpillStackID */
291 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
292 .CoveredBySubRegs: false, /* CoveredBySubRegs */
293 offsetof(SPIRVRegisterClassStorage, SuperClasses[12]) - 8 * sizeof(MCRegisterClass),
294 .SuperClassesSize: 2
295 },
296 },
297 .Regs: {
298 /* 0 */ SPIRV::TYPE0, SPIRV::ID0, SPIRV::fID0, SPIRV::pID0, SPIRV::viID0, SPIRV::vfID0, SPIRV::vpID0,
299 /* 7 */ SPIRV::ID0, SPIRV::fID0, SPIRV::pID0, SPIRV::viID0, SPIRV::vfID0, SPIRV::vpID0,
300 /* 13 */ SPIRV::TYPE0,
301 /* 14 */ SPIRV::fID0,
302 /* 15 */ SPIRV::ID0,
303 /* 16 */ SPIRV::pID0,
304 /* 17 */ SPIRV::vpID0,
305 /* 18 */ SPIRV::vfID0,
306 /* 19 */ SPIRV::viID0,
307 },
308 .BitSets: {
309 /* 0 */ 0x7f,
310 /* 1 */ 0x7d,
311 /* 2 */ 0x01,
312 /* 3 */ 0x01,
313 /* 4 */ 0x01,
314 /* 5 */ 0x01,
315 /* 6 */ 0x01,
316 /* 7 */ 0x01,
317 /* 8 */ 0x01,
318 },
319 .SubClassMasks: {
320 // 0 ANY
321 0x000001ff,
322 // 1 ID
323 0x000001fa,
324 // 2 TYPE
325 0x00000004,
326 // 3 fID
327 0x00000008,
328 // 4 iID
329 0x00000010,
330 // 5 pID
331 0x00000020,
332 // 6 vpID
333 0x00000040,
334 // 7 vfID
335 0x00000080,
336 // 8 viID
337 0x00000100,
338 },
339 .SuperRegIdxSeqs: {
340 /* 0 */ 0,
341 },
342 .SuperClasses: {
343 /* 0 ANY */
344 /* 0 ID */ SPIRV::ANYRegClassID,
345 /* 1 TYPE */ SPIRV::ANYRegClassID,
346 /* 2 fID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
347 /* 4 iID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
348 /* 6 pID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
349 /* 8 vpID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
350 /* 10 vfID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
351 /* 12 viID */ SPIRV::ANYRegClassID, SPIRV::IDRegClassID,
352 }
353};
354
355const MCRegisterClass &getSPIRVMCRegisterClass(unsigned RC) {
356 return SPIRVMCRegisterClassStorage.Classes[RC];
357}
358
359extern const uint16_t SPIRVRegEncodingTable[] = {
360 0,
361 0,
362 0,
363 0,
364 0,
365 0,
366 0,
367 0,
368};
369static inline void InitSPIRVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
370 RI->InitMCRegisterInfo(D: SPIRVRegDesc, NR: 8, RA, PC, C: SPIRVMCRegisterClassStorage.Classes, NC: 9, RURoots: SPIRVRegUnitRoots, NRU: 7, DL: SPIRVRegDiffLists, RUMS: SPIRVLaneMaskLists, Strings: SPIRVRegStrings, ClassStrings: SPIRVRegClassStrings, SubIndices: SPIRVSubRegIdxLists, NumIndices: 1,
371RET: SPIRVRegEncodingTable, RUI: nullptr);
372
373}
374
375
376} // namespace llvm
377