1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<9, 20, 9, 9, 1, 14> SPIRVMCRegisterClassStorage;
12
13static const MVT::SimpleValueType SPIRVVTLists[] = {
14 /* 0 */ MVT::i64, MVT::f64, MVT::i64, MVT::v2i64, MVT::v2f64, MVT::i64, MVT::Other,
15 /* 7 */ MVT::f64, MVT::Other,
16 /* 9 */ MVT::v2i64, MVT::Other,
17 /* 11 */ MVT::v2f64, MVT::Other,
18};
19static constexpr char SPIRVSubRegIndexStrings[] = {
20 /* dummy */ 0
21};
22
23
24static constexpr uint32_t SPIRVSubRegIndexNameOffsets[] = {
25 /* dummy */ 0
26};
27
28static const TargetRegisterInfo::SubRegCoveredBits SPIRVSubRegIdxRangeTable[] = {
29 { .Offset: 4294967295, .Size: 4294967295 },
30};
31
32
33static const LaneBitmask SPIRVSubRegIndexLaneMaskTable[] = {
34 LaneBitmask::getAll(),
35 };
36
37
38
39static const TargetRegisterInfo::RegClassInfo SPIRVRegClassInfos[] = {
40 // Mode = 0 (DefaultMode)
41 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // ANY
42 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 0 }, // ID
43 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // TYPE
44 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 7 }, // fID
45 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // iID
46 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // pID
47 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // vpID
48 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 11 }, // vfID
49 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 9 }, // viID
50};
51
52static const uint8_t SPIRVCostPerUseTable[] = {
530, 0, 0, 0, 0, 0, 0, 0, };
54
55
56static const bool SPIRVInAllocatableClassTable[] = {
57false, true, true, true, true, true, true, true, };
58
59
60static const TargetRegisterInfoDesc SPIRVRegInfoDesc = { // Extra Descriptors
61.CostPerUse: SPIRVCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SPIRVInAllocatableClassTable};
62
63/// Get the weight in units of pressure for this register class.
64const RegClassWeight &SPIRVGenRegisterInfo::
65getRegClassWeight(const TargetRegisterClass *RC) const {
66 static const RegClassWeight RCWeightTable[] = {
67 {.RegWeight: 1, .WeightLimit: 7}, // ANY
68 {.RegWeight: 1, .WeightLimit: 6}, // ID
69 {.RegWeight: 1, .WeightLimit: 1}, // TYPE
70 {.RegWeight: 1, .WeightLimit: 1}, // fID
71 {.RegWeight: 1, .WeightLimit: 1}, // iID
72 {.RegWeight: 1, .WeightLimit: 1}, // pID
73 {.RegWeight: 1, .WeightLimit: 1}, // vpID
74 {.RegWeight: 1, .WeightLimit: 1}, // vfID
75 {.RegWeight: 1, .WeightLimit: 1}, // viID
76 };
77 return RCWeightTable[RC->getID()];
78}
79
80/// Get the weight in units of pressure for this register unit.
81unsigned SPIRVGenRegisterInfo::
82getRegUnitWeight(MCRegUnit RegUnit) const {
83 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
84 // All register units have unit weight.
85 return 1;
86}
87
88
89// Get the number of dimensions of register pressure.
90unsigned SPIRVGenRegisterInfo::getNumRegPressureSets() const {
91 return 8;
92}
93
94// Get the name of this register unit pressure set.
95const char *SPIRVGenRegisterInfo::
96getRegPressureSetName(unsigned Idx) const {
97 static const char *PressureNameTable[] = {
98 "TYPE",
99 "fID",
100 "iID",
101 "pID",
102 "vpID",
103 "vfID",
104 "viID",
105 "ID",
106 };
107 return PressureNameTable[Idx];
108}
109
110// Get the register unit pressure limit for this dimension.
111// This limit must be adjusted dynamically for reserved registers.
112unsigned SPIRVGenRegisterInfo::
113getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
114 static const uint8_t PressureLimitTable[] = {
115 1, // 0: TYPE
116 1, // 1: fID
117 1, // 2: iID
118 1, // 3: pID
119 1, // 4: vpID
120 1, // 5: vfID
121 1, // 6: viID
122 7, // 7: ID
123 };
124 return PressureLimitTable[Idx];
125}
126
127/// Get the register class for this pressure set with the largest
128/// `RegClassWeight::WeightLimit`.
129const TargetRegisterClass *SPIRVGenRegisterInfo::
130getLargestRegClassForRegPressureSet(unsigned Idx) const {
131 static const uint8_t PSetRegClassTable[] = {
132 SPIRV::TYPERegClassID, // 0: TYPE
133 SPIRV::fIDRegClassID, // 1: fID
134 SPIRV::iIDRegClassID, // 2: iID
135 SPIRV::pIDRegClassID, // 3: pID
136 SPIRV::vpIDRegClassID, // 4: vpID
137 SPIRV::vfIDRegClassID, // 5: vfID
138 SPIRV::viIDRegClassID, // 6: viID
139 SPIRV::ANYRegClassID, // 7: ID
140 };
141 return getRegClass(i: PSetRegClassTable[Idx]);
142}
143
144/// Table of pressure sets per register class or unit.
145static const int RCSetsTable[] = {
146 /* 0 */ 0, 7, -1,
147 /* 3 */ 1, 7, -1,
148 /* 6 */ 2, 7, -1,
149 /* 9 */ 3, 7, -1,
150 /* 12 */ 4, 7, -1,
151 /* 15 */ 5, 7, -1,
152 /* 18 */ 6, 7, -1,
153};
154
155/// Get the dimensions of register pressure impacted by this register class.
156/// Returns a -1 terminated array of pressure set IDs
157const int *SPIRVGenRegisterInfo::
158getRegClassPressureSets(const TargetRegisterClass *RC) const {
159 static const uint8_t RCSetStartTable[] = {
160 1,1,0,3,6,9,12,15,18,};
161 return &RCSetsTable[RCSetStartTable[RC->getID()]];
162}
163
164/// Get the dimensions of register pressure impacted by this register unit.
165/// Returns a -1 terminated array of pressure set IDs
166const int *SPIRVGenRegisterInfo::
167getRegUnitPressureSets(MCRegUnit RegUnit) const {
168 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
169 static const uint8_t RUSetStartTable[] = {
170 6,0,3,9,15,18,12,};
171 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
172}
173
174
175// Register to minimal register class mapping
176
177const TargetRegisterClass *SPIRVGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
178 static const uint16_t InvalidRegClassID = UINT16_MAX;
179
180 static const uint16_t Mapping[8] = {
181 InvalidRegClassID, // NoRegister
182 SPIRV::iIDRegClassID, // ID0
183 SPIRV::TYPERegClassID, // TYPE0
184 SPIRV::fIDRegClassID, // fID0
185 SPIRV::pIDRegClassID, // pID0
186 SPIRV::vfIDRegClassID, // vfID0
187 SPIRV::viIDRegClassID, // viID0
188 SPIRV::vpIDRegClassID, // vpID0
189 };
190
191 assert(Reg < ArrayRef(Mapping).size());
192 unsigned RCID = Mapping[Reg.id()];
193 if (RCID == InvalidRegClassID)
194 return nullptr;
195 return &SPIRVMCRegisterClassStorage.Classes[RCID];
196}
197extern const MCRegisterDesc SPIRVRegDesc[];
198extern const int16_t SPIRVRegDiffLists[];
199extern const LaneBitmask SPIRVLaneMaskLists[];
200extern const char SPIRVRegStrings[];
201extern const char SPIRVRegClassStrings[];
202extern const MCPhysReg SPIRVRegUnitRoots[][2];
203extern const uint16_t SPIRVSubRegIdxLists[];
204extern const uint16_t SPIRVRegEncodingTable[];
205
206SPIRVGenRegisterInfo::
207SPIRVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
208 unsigned PC, unsigned HwMode)
209 : TargetRegisterInfo(&SPIRVRegInfoDesc,
210 SPIRVSubRegIndexStrings, SPIRVSubRegIndexNameOffsets,
211 SPIRVSubRegIdxRangeTable, SPIRVSubRegIndexLaneMaskTable,
212
213 LaneBitmask(0xFFFFFFFFFFFFFFFF), SPIRVRegClassInfos, SPIRVVTLists, HwMode) {
214 InitMCRegisterInfo(D: SPIRVRegDesc, NR: 8, RA, PC,
215 C: &getSPIRVMCRegisterClass(RC: 0), NC: 9, RURoots: SPIRVRegUnitRoots, NRU: 7, DL: SPIRVRegDiffLists,
216 RUMS: SPIRVLaneMaskLists, Strings: SPIRVRegStrings, ClassStrings: SPIRVRegClassStrings, SubIndices: SPIRVSubRegIdxLists, NumIndices: 1,
217 RET: SPIRVRegEncodingTable, RUI: nullptr);
218
219}
220
221
222
223ArrayRef<const uint32_t *> SPIRVGenRegisterInfo::getRegMasks() const {
224 return {};
225}
226
227bool SPIRVGenRegisterInfo::
228isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
229 return
230 false;
231}
232
233bool SPIRVGenRegisterInfo::
234isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
235 return
236 false;
237}
238
239bool SPIRVGenRegisterInfo::
240isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
241 return
242 false;
243}
244
245bool SPIRVGenRegisterInfo::
246isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
247 return
248 false;
249}
250
251bool SPIRVGenRegisterInfo::
252isConstantPhysReg(MCRegister PhysReg) const {
253 return
254 false;
255}
256
257ArrayRef<const char *> SPIRVGenRegisterInfo::getRegMaskNames() const {
258 return {};
259}
260
261const SPIRVFrameLowering *
262SPIRVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
263 return static_cast<const SPIRVFrameLowering *>(
264 MF.getSubtarget().getFrameLowering());
265}
266
267
268} // namespace llvm
269