1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SPIRVMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i64, MVT::f64, MVT::i64, MVT::v2i64, MVT::v2f64, MVT::i64, MVT::Other,
15 /* 7 */ MVT::f64, MVT::Other,
16 /* 9 */ MVT::v2i64, MVT::Other,
17 /* 11 */ MVT::v2f64, MVT::Other,
18};
19
20static const char *SubRegIndexNameTable[] = { "" };
21
22static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
23 { .Offset: 65535, .Size: 65535 },
24};
25
26
27static const LaneBitmask SubRegIndexLaneMaskTable[] = {
28 LaneBitmask::getAll(),
29 };
30
31
32
33static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
34 // Mode = 0 (Default)
35 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // ANY
36 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 0 }, // ID
37 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // TYPE
38 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 7 }, // fID
39 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // iID
40 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // pID
41 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // vpID
42 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // vID
43 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 11 }, // vfID
44};
45static const uint32_t ANYSubClassMask[] = {
46 0x000001ff,
47};
48
49static const uint32_t IDSubClassMask[] = {
50 0x000001fa,
51};
52
53static const uint32_t TYPESubClassMask[] = {
54 0x00000004,
55};
56
57static const uint32_t fIDSubClassMask[] = {
58 0x00000008,
59};
60
61static const uint32_t iIDSubClassMask[] = {
62 0x00000010,
63};
64
65static const uint32_t pIDSubClassMask[] = {
66 0x00000020,
67};
68
69static const uint32_t vpIDSubClassMask[] = {
70 0x00000040,
71};
72
73static const uint32_t vIDSubClassMask[] = {
74 0x00000080,
75};
76
77static const uint32_t vfIDSubClassMask[] = {
78 0x00000100,
79};
80
81static const uint16_t SuperRegIdxSeqs[] = {
82 /* 0 */ 0,
83};
84
85static unsigned const IDSuperclasses[] = {
86 SPIRV::ANYRegClassID,
87};
88
89static unsigned const TYPESuperclasses[] = {
90 SPIRV::ANYRegClassID,
91};
92
93static unsigned const fIDSuperclasses[] = {
94 SPIRV::ANYRegClassID,
95 SPIRV::IDRegClassID,
96};
97
98static unsigned const iIDSuperclasses[] = {
99 SPIRV::ANYRegClassID,
100 SPIRV::IDRegClassID,
101};
102
103static unsigned const pIDSuperclasses[] = {
104 SPIRV::ANYRegClassID,
105 SPIRV::IDRegClassID,
106};
107
108static unsigned const vpIDSuperclasses[] = {
109 SPIRV::ANYRegClassID,
110 SPIRV::IDRegClassID,
111};
112
113static unsigned const vIDSuperclasses[] = {
114 SPIRV::ANYRegClassID,
115 SPIRV::IDRegClassID,
116};
117
118static unsigned const vfIDSuperclasses[] = {
119 SPIRV::ANYRegClassID,
120 SPIRV::IDRegClassID,
121};
122
123
124namespace SPIRV { // Register class instances
125 extern const TargetRegisterClass ANYRegClass = {
126 .MC: &SPIRVMCRegisterClasses[ANYRegClassID],
127 .SubClassMask: ANYSubClassMask,
128 .SuperRegIndices: SuperRegIdxSeqs + 0,
129 .LaneMask: LaneBitmask(0x0000000000000001),
130 .AllocationPriority: 0,
131 .GlobalPriority: false,
132 .TSFlags: 0x00, /* TSFlags */
133 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
134 .CoveredBySubRegs: false, /* CoveredBySubRegs */
135 .SuperClasses: nullptr, .SuperClassesSize: 0,
136 .OrderFunc: nullptr
137 };
138
139 extern const TargetRegisterClass IDRegClass = {
140 .MC: &SPIRVMCRegisterClasses[IDRegClassID],
141 .SubClassMask: IDSubClassMask,
142 .SuperRegIndices: SuperRegIdxSeqs + 0,
143 .LaneMask: LaneBitmask(0x0000000000000001),
144 .AllocationPriority: 0,
145 .GlobalPriority: false,
146 .TSFlags: 0x00, /* TSFlags */
147 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
148 .CoveredBySubRegs: false, /* CoveredBySubRegs */
149 .SuperClasses: IDSuperclasses, .SuperClassesSize: 1,
150 .OrderFunc: nullptr
151 };
152
153 extern const TargetRegisterClass TYPERegClass = {
154 .MC: &SPIRVMCRegisterClasses[TYPERegClassID],
155 .SubClassMask: TYPESubClassMask,
156 .SuperRegIndices: SuperRegIdxSeqs + 0,
157 .LaneMask: LaneBitmask(0x0000000000000001),
158 .AllocationPriority: 0,
159 .GlobalPriority: false,
160 .TSFlags: 0x00, /* TSFlags */
161 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
162 .CoveredBySubRegs: false, /* CoveredBySubRegs */
163 .SuperClasses: TYPESuperclasses, .SuperClassesSize: 1,
164 .OrderFunc: nullptr
165 };
166
167 extern const TargetRegisterClass fIDRegClass = {
168 .MC: &SPIRVMCRegisterClasses[fIDRegClassID],
169 .SubClassMask: fIDSubClassMask,
170 .SuperRegIndices: SuperRegIdxSeqs + 0,
171 .LaneMask: LaneBitmask(0x0000000000000001),
172 .AllocationPriority: 0,
173 .GlobalPriority: false,
174 .TSFlags: 0x00, /* TSFlags */
175 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
176 .CoveredBySubRegs: false, /* CoveredBySubRegs */
177 .SuperClasses: fIDSuperclasses, .SuperClassesSize: 2,
178 .OrderFunc: nullptr
179 };
180
181 extern const TargetRegisterClass iIDRegClass = {
182 .MC: &SPIRVMCRegisterClasses[iIDRegClassID],
183 .SubClassMask: iIDSubClassMask,
184 .SuperRegIndices: SuperRegIdxSeqs + 0,
185 .LaneMask: LaneBitmask(0x0000000000000001),
186 .AllocationPriority: 0,
187 .GlobalPriority: false,
188 .TSFlags: 0x00, /* TSFlags */
189 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
190 .CoveredBySubRegs: false, /* CoveredBySubRegs */
191 .SuperClasses: iIDSuperclasses, .SuperClassesSize: 2,
192 .OrderFunc: nullptr
193 };
194
195 extern const TargetRegisterClass pIDRegClass = {
196 .MC: &SPIRVMCRegisterClasses[pIDRegClassID],
197 .SubClassMask: pIDSubClassMask,
198 .SuperRegIndices: SuperRegIdxSeqs + 0,
199 .LaneMask: LaneBitmask(0x0000000000000001),
200 .AllocationPriority: 0,
201 .GlobalPriority: false,
202 .TSFlags: 0x00, /* TSFlags */
203 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
204 .CoveredBySubRegs: false, /* CoveredBySubRegs */
205 .SuperClasses: pIDSuperclasses, .SuperClassesSize: 2,
206 .OrderFunc: nullptr
207 };
208
209 extern const TargetRegisterClass vpIDRegClass = {
210 .MC: &SPIRVMCRegisterClasses[vpIDRegClassID],
211 .SubClassMask: vpIDSubClassMask,
212 .SuperRegIndices: SuperRegIdxSeqs + 0,
213 .LaneMask: LaneBitmask(0x0000000000000001),
214 .AllocationPriority: 0,
215 .GlobalPriority: false,
216 .TSFlags: 0x00, /* TSFlags */
217 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
218 .CoveredBySubRegs: false, /* CoveredBySubRegs */
219 .SuperClasses: vpIDSuperclasses, .SuperClassesSize: 2,
220 .OrderFunc: nullptr
221 };
222
223 extern const TargetRegisterClass vIDRegClass = {
224 .MC: &SPIRVMCRegisterClasses[vIDRegClassID],
225 .SubClassMask: vIDSubClassMask,
226 .SuperRegIndices: SuperRegIdxSeqs + 0,
227 .LaneMask: LaneBitmask(0x0000000000000001),
228 .AllocationPriority: 0,
229 .GlobalPriority: false,
230 .TSFlags: 0x00, /* TSFlags */
231 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
232 .CoveredBySubRegs: false, /* CoveredBySubRegs */
233 .SuperClasses: vIDSuperclasses, .SuperClassesSize: 2,
234 .OrderFunc: nullptr
235 };
236
237 extern const TargetRegisterClass vfIDRegClass = {
238 .MC: &SPIRVMCRegisterClasses[vfIDRegClassID],
239 .SubClassMask: vfIDSubClassMask,
240 .SuperRegIndices: SuperRegIdxSeqs + 0,
241 .LaneMask: LaneBitmask(0x0000000000000001),
242 .AllocationPriority: 0,
243 .GlobalPriority: false,
244 .TSFlags: 0x00, /* TSFlags */
245 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
246 .CoveredBySubRegs: false, /* CoveredBySubRegs */
247 .SuperClasses: vfIDSuperclasses, .SuperClassesSize: 2,
248 .OrderFunc: nullptr
249 };
250
251} // end namespace SPIRV
252
253namespace {
254 const TargetRegisterClass *const RegisterClasses[] = {
255 &SPIRV::ANYRegClass,
256 &SPIRV::IDRegClass,
257 &SPIRV::TYPERegClass,
258 &SPIRV::fIDRegClass,
259 &SPIRV::iIDRegClass,
260 &SPIRV::pIDRegClass,
261 &SPIRV::vpIDRegClass,
262 &SPIRV::vIDRegClass,
263 &SPIRV::vfIDRegClass,
264 };
265} // end anonymous namespace
266
267static const uint8_t CostPerUseTable[] = {
2680, 0, 0, 0, 0, 0, 0, 0, };
269
270
271static const bool InAllocatableClassTable[] = {
272false, true, true, true, true, true, true, true, };
273
274
275static const TargetRegisterInfoDesc SPIRVRegInfoDesc = { // Extra Descriptors
276.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
277
278/// Get the weight in units of pressure for this register class.
279const RegClassWeight &SPIRVGenRegisterInfo::
280getRegClassWeight(const TargetRegisterClass *RC) const {
281 static const RegClassWeight RCWeightTable[] = {
282 {.RegWeight: 1, .WeightLimit: 7}, // ANY
283 {.RegWeight: 1, .WeightLimit: 6}, // ID
284 {.RegWeight: 1, .WeightLimit: 1}, // TYPE
285 {.RegWeight: 1, .WeightLimit: 1}, // fID
286 {.RegWeight: 1, .WeightLimit: 1}, // iID
287 {.RegWeight: 1, .WeightLimit: 1}, // pID
288 {.RegWeight: 1, .WeightLimit: 1}, // vpID
289 {.RegWeight: 1, .WeightLimit: 1}, // vID
290 {.RegWeight: 1, .WeightLimit: 1}, // vfID
291 };
292 return RCWeightTable[RC->getID()];
293}
294
295/// Get the weight in units of pressure for this register unit.
296unsigned SPIRVGenRegisterInfo::
297getRegUnitWeight(MCRegUnit RegUnit) const {
298 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
299 // All register units have unit weight.
300 return 1;
301}
302
303
304// Get the number of dimensions of register pressure.
305unsigned SPIRVGenRegisterInfo::getNumRegPressureSets() const {
306 return 8;
307}
308
309// Get the name of this register unit pressure set.
310const char *SPIRVGenRegisterInfo::
311getRegPressureSetName(unsigned Idx) const {
312 static const char *PressureNameTable[] = {
313 "TYPE",
314 "fID",
315 "iID",
316 "pID",
317 "vpID",
318 "vID",
319 "vfID",
320 "ID",
321 };
322 return PressureNameTable[Idx];
323}
324
325// Get the register unit pressure limit for this dimension.
326// This limit must be adjusted dynamically for reserved registers.
327unsigned SPIRVGenRegisterInfo::
328getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
329 static const uint8_t PressureLimitTable[] = {
330 1, // 0: TYPE
331 1, // 1: fID
332 1, // 2: iID
333 1, // 3: pID
334 1, // 4: vpID
335 1, // 5: vID
336 1, // 6: vfID
337 7, // 7: ID
338 };
339 return PressureLimitTable[Idx];
340}
341
342/// Table of pressure sets per register class or unit.
343static const int RCSetsTable[] = {
344 /* 0 */ 0, 7, -1,
345 /* 3 */ 1, 7, -1,
346 /* 6 */ 2, 7, -1,
347 /* 9 */ 3, 7, -1,
348 /* 12 */ 4, 7, -1,
349 /* 15 */ 5, 7, -1,
350 /* 18 */ 6, 7, -1,
351};
352
353/// Get the dimensions of register pressure impacted by this register class.
354/// Returns a -1 terminated array of pressure set IDs
355const int *SPIRVGenRegisterInfo::
356getRegClassPressureSets(const TargetRegisterClass *RC) const {
357 static const uint8_t RCSetStartTable[] = {
358 1,1,0,3,6,9,12,15,18,};
359 return &RCSetsTable[RCSetStartTable[RC->getID()]];
360}
361
362/// Get the dimensions of register pressure impacted by this register unit.
363/// Returns a -1 terminated array of pressure set IDs
364const int *SPIRVGenRegisterInfo::
365getRegUnitPressureSets(MCRegUnit RegUnit) const {
366 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
367 static const uint8_t RUSetStartTable[] = {
368 6,0,3,9,15,18,12,};
369 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
370}
371
372extern const MCRegisterDesc SPIRVRegDesc[];
373extern const int16_t SPIRVRegDiffLists[];
374extern const LaneBitmask SPIRVLaneMaskLists[];
375extern const char SPIRVRegStrings[];
376extern const char SPIRVRegClassStrings[];
377extern const MCPhysReg SPIRVRegUnitRoots[][2];
378extern const uint16_t SPIRVSubRegIdxLists[];
379extern const uint16_t SPIRVRegEncodingTable[];
380SPIRVGenRegisterInfo::
381SPIRVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
382 unsigned PC, unsigned HwMode)
383 : TargetRegisterInfo(&SPIRVRegInfoDesc, RegisterClasses, RegisterClasses+9,
384 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
385 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
386 InitMCRegisterInfo(D: SPIRVRegDesc, NR: 8, RA, PC,
387 C: SPIRVMCRegisterClasses, NC: 9,
388 RURoots: SPIRVRegUnitRoots,
389 NRU: 7,
390 DL: SPIRVRegDiffLists,
391 RUMS: SPIRVLaneMaskLists,
392 Strings: SPIRVRegStrings,
393 ClassStrings: SPIRVRegClassStrings,
394 SubIndices: SPIRVSubRegIdxLists,
395 NumIndices: 1,
396 RET: SPIRVRegEncodingTable);
397
398}
399
400
401
402ArrayRef<const uint32_t *> SPIRVGenRegisterInfo::getRegMasks() const {
403 return {};
404}
405
406bool SPIRVGenRegisterInfo::
407isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
408 return
409 false;
410}
411
412bool SPIRVGenRegisterInfo::
413isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
414 return
415 false;
416}
417
418bool SPIRVGenRegisterInfo::
419isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
420 return
421 false;
422}
423
424bool SPIRVGenRegisterInfo::
425isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
426 return
427 false;
428}
429
430bool SPIRVGenRegisterInfo::
431isConstantPhysReg(MCRegister PhysReg) const {
432 return
433 false;
434}
435
436ArrayRef<const char *> SPIRVGenRegisterInfo::getRegMaskNames() const {
437 return {};
438}
439
440const SPIRVFrameLowering *
441SPIRVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
442 return static_cast<const SPIRVFrameLowering *>(
443 MF.getSubtarget().getFrameLowering());
444}
445
446} // end namespace llvm
447
448