1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<9, 20, 9, 9, 1, 14> SPIRVMCRegisterClassStorage;
12
13static const MVT::SimpleValueType SPIRVVTLists[] = {
14 /* 0 */ MVT::i64, MVT::f64, MVT::i64, MVT::v2i64, MVT::v2f64, MVT::i64, MVT::Other,
15 /* 7 */ MVT::f64, MVT::Other,
16 /* 9 */ MVT::v2i64, MVT::Other,
17 /* 11 */ MVT::v2f64, MVT::Other,
18};
19static constexpr char SPIRVSubRegIndexStrings[] = {
20 /* dummy */ 0
21};
22
23
24static constexpr uint32_t SPIRVSubRegIndexNameOffsets[] = {
25 /* dummy */ 0
26};
27
28static const TargetRegisterInfo::SubRegCoveredBits SPIRVSubRegIdxRangeTable[] = {
29 { .Offset: 4294967295, .Size: 4294967295 },
30};
31
32
33static const LaneBitmask SPIRVSubRegIndexLaneMaskTable[] = {
34 LaneBitmask::getAll(),
35 };
36
37
38
39static const TargetRegisterInfo::RegClassInfo SPIRVRegClassInfos[] = {
40 // Mode = 0 (DefaultMode)
41 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // ANY
42 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 0 }, // ID
43 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // TYPE
44 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 7 }, // fID
45 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // iID
46 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // pID
47 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // vpID
48 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 11 }, // vfID
49 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 9 }, // viID
50};
51
52static const uint8_t SPIRVCostPerUseTable[] = {
530, 0, 0, 0, 0, 0, 0, 0, };
54
55
56static const bool SPIRVInAllocatableClassTable[] = {
57false, true, true, true, true, true, true, true, };
58
59
60static const TargetRegisterInfoDesc SPIRVRegInfoDesc = { // Extra Descriptors
61.CostPerUse: SPIRVCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SPIRVInAllocatableClassTable};
62
63/// Get the weight in units of pressure for this register class.
64const RegClassWeight &SPIRVGenRegisterInfo::
65getRegClassWeight(const TargetRegisterClass *RC) const {
66 static const RegClassWeight RCWeightTable[] = {
67 {.RegWeight: 1, .WeightLimit: 7}, // ANY
68 {.RegWeight: 1, .WeightLimit: 6}, // ID
69 {.RegWeight: 1, .WeightLimit: 1}, // TYPE
70 {.RegWeight: 1, .WeightLimit: 1}, // fID
71 {.RegWeight: 1, .WeightLimit: 1}, // iID
72 {.RegWeight: 1, .WeightLimit: 1}, // pID
73 {.RegWeight: 1, .WeightLimit: 1}, // vpID
74 {.RegWeight: 1, .WeightLimit: 1}, // vfID
75 {.RegWeight: 1, .WeightLimit: 1}, // viID
76 };
77 return RCWeightTable[RC->getID()];
78}
79
80/// Get the weight in units of pressure for this register unit.
81unsigned SPIRVGenRegisterInfo::
82getRegUnitWeight(MCRegUnit RegUnit) const {
83 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
84 // All register units have unit weight.
85 return 1;
86}
87
88
89// Get the number of dimensions of register pressure.
90unsigned SPIRVGenRegisterInfo::getNumRegPressureSets() const {
91 return 8;
92}
93
94// Get the name of this register unit pressure set.
95const char *SPIRVGenRegisterInfo::
96getRegPressureSetName(unsigned Idx) const {
97 static const char *PressureNameTable[] = {
98 "TYPE",
99 "fID",
100 "iID",
101 "pID",
102 "vpID",
103 "vfID",
104 "viID",
105 "ID",
106 };
107 return PressureNameTable[Idx];
108}
109
110// Get the register unit pressure limit for this dimension.
111// This limit must be adjusted dynamically for reserved registers.
112unsigned SPIRVGenRegisterInfo::
113getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
114 static const uint8_t PressureLimitTable[] = {
115 1, // 0: TYPE
116 1, // 1: fID
117 1, // 2: iID
118 1, // 3: pID
119 1, // 4: vpID
120 1, // 5: vfID
121 1, // 6: viID
122 7, // 7: ID
123 };
124 return PressureLimitTable[Idx];
125}
126
127/// Table of pressure sets per register class or unit.
128static const int RCSetsTable[] = {
129 /* 0 */ 0, 7, -1,
130 /* 3 */ 1, 7, -1,
131 /* 6 */ 2, 7, -1,
132 /* 9 */ 3, 7, -1,
133 /* 12 */ 4, 7, -1,
134 /* 15 */ 5, 7, -1,
135 /* 18 */ 6, 7, -1,
136};
137
138/// Get the dimensions of register pressure impacted by this register class.
139/// Returns a -1 terminated array of pressure set IDs
140const int *SPIRVGenRegisterInfo::
141getRegClassPressureSets(const TargetRegisterClass *RC) const {
142 static const uint8_t RCSetStartTable[] = {
143 1,1,0,3,6,9,12,15,18,};
144 return &RCSetsTable[RCSetStartTable[RC->getID()]];
145}
146
147/// Get the dimensions of register pressure impacted by this register unit.
148/// Returns a -1 terminated array of pressure set IDs
149const int *SPIRVGenRegisterInfo::
150getRegUnitPressureSets(MCRegUnit RegUnit) const {
151 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
152 static const uint8_t RUSetStartTable[] = {
153 6,0,3,9,15,18,12,};
154 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
155}
156
157
158// Register to minimal register class mapping
159
160const TargetRegisterClass *SPIRVGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
161 static const uint16_t InvalidRegClassID = UINT16_MAX;
162
163 static const uint16_t Mapping[8] = {
164 InvalidRegClassID, // NoRegister
165 SPIRV::iIDRegClassID, // ID0
166 SPIRV::TYPERegClassID, // TYPE0
167 SPIRV::fIDRegClassID, // fID0
168 SPIRV::pIDRegClassID, // pID0
169 SPIRV::vfIDRegClassID, // vfID0
170 SPIRV::viIDRegClassID, // viID0
171 SPIRV::vpIDRegClassID, // vpID0
172 };
173
174 assert(Reg < ArrayRef(Mapping).size());
175 unsigned RCID = Mapping[Reg.id()];
176 if (RCID == InvalidRegClassID)
177 return nullptr;
178 return &SPIRVMCRegisterClassStorage.Classes[RCID];
179}
180extern const MCRegisterDesc SPIRVRegDesc[];
181extern const int16_t SPIRVRegDiffLists[];
182extern const LaneBitmask SPIRVLaneMaskLists[];
183extern const char SPIRVRegStrings[];
184extern const char SPIRVRegClassStrings[];
185extern const MCPhysReg SPIRVRegUnitRoots[][2];
186extern const uint16_t SPIRVSubRegIdxLists[];
187extern const uint16_t SPIRVRegEncodingTable[];
188
189SPIRVGenRegisterInfo::
190SPIRVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
191 unsigned PC, unsigned HwMode)
192 : TargetRegisterInfo(&SPIRVRegInfoDesc,
193 SPIRVSubRegIndexStrings, SPIRVSubRegIndexNameOffsets,
194 SPIRVSubRegIdxRangeTable, SPIRVSubRegIndexLaneMaskTable,
195
196 LaneBitmask(0xFFFFFFFFFFFFFFFF), SPIRVRegClassInfos, SPIRVVTLists, HwMode) {
197 InitMCRegisterInfo(D: SPIRVRegDesc, NR: 8, RA, PC,
198 C: &getSPIRVMCRegisterClass(RC: 0), NC: 9, RURoots: SPIRVRegUnitRoots, NRU: 7, DL: SPIRVRegDiffLists,
199 RUMS: SPIRVLaneMaskLists, Strings: SPIRVRegStrings, ClassStrings: SPIRVRegClassStrings, SubIndices: SPIRVSubRegIdxLists, NumIndices: 1,
200 RET: SPIRVRegEncodingTable, RUI: nullptr);
201
202}
203
204
205
206ArrayRef<const uint32_t *> SPIRVGenRegisterInfo::getRegMasks() const {
207 return {};
208}
209
210bool SPIRVGenRegisterInfo::
211isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
212 return
213 false;
214}
215
216bool SPIRVGenRegisterInfo::
217isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
218 return
219 false;
220}
221
222bool SPIRVGenRegisterInfo::
223isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
224 return
225 false;
226}
227
228bool SPIRVGenRegisterInfo::
229isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
230 return
231 false;
232}
233
234bool SPIRVGenRegisterInfo::
235isConstantPhysReg(MCRegister PhysReg) const {
236 return
237 false;
238}
239
240ArrayRef<const char *> SPIRVGenRegisterInfo::getRegMaskNames() const {
241 return {};
242}
243
244const SPIRVFrameLowering *
245SPIRVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
246 return static_cast<const SPIRVFrameLowering *>(
247 MF.getSubtarget().getFrameLowering());
248}
249
250
251} // namespace llvm
252