1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SPIRVMCRegisterClasses[];
12
13static const MVT::SimpleValueType SPIRVVTLists[] = {
14 /* 0 */ MVT::i64, MVT::f64, MVT::i64, MVT::v2i64, MVT::v2f64, MVT::i64, MVT::Other,
15 /* 7 */ MVT::f64, MVT::Other,
16 /* 9 */ MVT::v2i64, MVT::Other,
17 /* 11 */ MVT::v2f64, MVT::Other,
18};
19static constexpr char SPIRVSubRegIndexStrings[] = {
20 /* dummy */ 0
21};
22
23
24static constexpr uint32_t SPIRVSubRegIndexNameOffsets[] = {
25 /* dummy */ 0
26};
27
28static const TargetRegisterInfo::SubRegCoveredBits SPIRVSubRegIdxRangeTable[] = {
29 { .Offset: 65535, .Size: 65535 },
30};
31
32
33static const LaneBitmask SPIRVSubRegIndexLaneMaskTable[] = {
34 LaneBitmask::getAll(),
35 };
36
37
38
39static const TargetRegisterInfo::RegClassInfo SPIRVRegClassInfos[] = {
40 // Mode = 0 (DefaultMode)
41 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // ANY
42 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 0 }, // ID
43 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // TYPE
44 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 7 }, // fID
45 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // iID
46 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // pID
47 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // vpID
48 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 9 }, // vID
49 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 11 }, // vfID
50};
51static const uint32_t ANYSubClassMask[] = {
52 0x000001ff,
53};
54
55static const uint32_t IDSubClassMask[] = {
56 0x000001fa,
57};
58
59static const uint32_t TYPESubClassMask[] = {
60 0x00000004,
61};
62
63static const uint32_t fIDSubClassMask[] = {
64 0x00000008,
65};
66
67static const uint32_t iIDSubClassMask[] = {
68 0x00000010,
69};
70
71static const uint32_t pIDSubClassMask[] = {
72 0x00000020,
73};
74
75static const uint32_t vpIDSubClassMask[] = {
76 0x00000040,
77};
78
79static const uint32_t vIDSubClassMask[] = {
80 0x00000080,
81};
82
83static const uint32_t vfIDSubClassMask[] = {
84 0x00000100,
85};
86
87static const uint16_t SuperRegIdxSeqs[] = {
88 /* 0 */ 0,
89};
90
91static unsigned const IDSuperclasses[] = {
92 SPIRV::ANYRegClassID,
93};
94
95static unsigned const TYPESuperclasses[] = {
96 SPIRV::ANYRegClassID,
97};
98
99static unsigned const fIDSuperclasses[] = {
100 SPIRV::ANYRegClassID,
101 SPIRV::IDRegClassID,
102};
103
104static unsigned const iIDSuperclasses[] = {
105 SPIRV::ANYRegClassID,
106 SPIRV::IDRegClassID,
107};
108
109static unsigned const pIDSuperclasses[] = {
110 SPIRV::ANYRegClassID,
111 SPIRV::IDRegClassID,
112};
113
114static unsigned const vpIDSuperclasses[] = {
115 SPIRV::ANYRegClassID,
116 SPIRV::IDRegClassID,
117};
118
119static unsigned const vIDSuperclasses[] = {
120 SPIRV::ANYRegClassID,
121 SPIRV::IDRegClassID,
122};
123
124static unsigned const vfIDSuperclasses[] = {
125 SPIRV::ANYRegClassID,
126 SPIRV::IDRegClassID,
127};
128
129namespace SPIRV {
130
131// Register class instances.
132 extern const TargetRegisterClass ANYRegClass = {
133 .MC: &SPIRVMCRegisterClasses[ANYRegClassID],
134 .SubClassMask: ANYSubClassMask,
135 .SuperRegIndices: SuperRegIdxSeqs + 0,
136 .LaneMask: LaneBitmask(0x0000000000000001),
137 .AllocationPriority: 0,
138 .GlobalPriority: false,
139 .TSFlags: 0x00, /* TSFlags */
140 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
141 .CoveredBySubRegs: false, /* CoveredBySubRegs */
142 .SuperClasses: nullptr, .SuperClassesSize: 0,
143 .OrderFunc: nullptr
144 };
145
146 extern const TargetRegisterClass IDRegClass = {
147 .MC: &SPIRVMCRegisterClasses[IDRegClassID],
148 .SubClassMask: IDSubClassMask,
149 .SuperRegIndices: SuperRegIdxSeqs + 0,
150 .LaneMask: LaneBitmask(0x0000000000000001),
151 .AllocationPriority: 0,
152 .GlobalPriority: false,
153 .TSFlags: 0x00, /* TSFlags */
154 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
155 .CoveredBySubRegs: false, /* CoveredBySubRegs */
156 .SuperClasses: IDSuperclasses, .SuperClassesSize: 1,
157 .OrderFunc: nullptr
158 };
159
160 extern const TargetRegisterClass TYPERegClass = {
161 .MC: &SPIRVMCRegisterClasses[TYPERegClassID],
162 .SubClassMask: TYPESubClassMask,
163 .SuperRegIndices: SuperRegIdxSeqs + 0,
164 .LaneMask: LaneBitmask(0x0000000000000001),
165 .AllocationPriority: 0,
166 .GlobalPriority: false,
167 .TSFlags: 0x00, /* TSFlags */
168 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
169 .CoveredBySubRegs: false, /* CoveredBySubRegs */
170 .SuperClasses: TYPESuperclasses, .SuperClassesSize: 1,
171 .OrderFunc: nullptr
172 };
173
174 extern const TargetRegisterClass fIDRegClass = {
175 .MC: &SPIRVMCRegisterClasses[fIDRegClassID],
176 .SubClassMask: fIDSubClassMask,
177 .SuperRegIndices: SuperRegIdxSeqs + 0,
178 .LaneMask: LaneBitmask(0x0000000000000001),
179 .AllocationPriority: 0,
180 .GlobalPriority: false,
181 .TSFlags: 0x00, /* TSFlags */
182 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
183 .CoveredBySubRegs: false, /* CoveredBySubRegs */
184 .SuperClasses: fIDSuperclasses, .SuperClassesSize: 2,
185 .OrderFunc: nullptr
186 };
187
188 extern const TargetRegisterClass iIDRegClass = {
189 .MC: &SPIRVMCRegisterClasses[iIDRegClassID],
190 .SubClassMask: iIDSubClassMask,
191 .SuperRegIndices: SuperRegIdxSeqs + 0,
192 .LaneMask: LaneBitmask(0x0000000000000001),
193 .AllocationPriority: 0,
194 .GlobalPriority: false,
195 .TSFlags: 0x00, /* TSFlags */
196 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
197 .CoveredBySubRegs: false, /* CoveredBySubRegs */
198 .SuperClasses: iIDSuperclasses, .SuperClassesSize: 2,
199 .OrderFunc: nullptr
200 };
201
202 extern const TargetRegisterClass pIDRegClass = {
203 .MC: &SPIRVMCRegisterClasses[pIDRegClassID],
204 .SubClassMask: pIDSubClassMask,
205 .SuperRegIndices: SuperRegIdxSeqs + 0,
206 .LaneMask: LaneBitmask(0x0000000000000001),
207 .AllocationPriority: 0,
208 .GlobalPriority: false,
209 .TSFlags: 0x00, /* TSFlags */
210 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
211 .CoveredBySubRegs: false, /* CoveredBySubRegs */
212 .SuperClasses: pIDSuperclasses, .SuperClassesSize: 2,
213 .OrderFunc: nullptr
214 };
215
216 extern const TargetRegisterClass vpIDRegClass = {
217 .MC: &SPIRVMCRegisterClasses[vpIDRegClassID],
218 .SubClassMask: vpIDSubClassMask,
219 .SuperRegIndices: SuperRegIdxSeqs + 0,
220 .LaneMask: LaneBitmask(0x0000000000000001),
221 .AllocationPriority: 0,
222 .GlobalPriority: false,
223 .TSFlags: 0x00, /* TSFlags */
224 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
225 .CoveredBySubRegs: false, /* CoveredBySubRegs */
226 .SuperClasses: vpIDSuperclasses, .SuperClassesSize: 2,
227 .OrderFunc: nullptr
228 };
229
230 extern const TargetRegisterClass vIDRegClass = {
231 .MC: &SPIRVMCRegisterClasses[vIDRegClassID],
232 .SubClassMask: vIDSubClassMask,
233 .SuperRegIndices: SuperRegIdxSeqs + 0,
234 .LaneMask: LaneBitmask(0x0000000000000001),
235 .AllocationPriority: 0,
236 .GlobalPriority: false,
237 .TSFlags: 0x00, /* TSFlags */
238 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
239 .CoveredBySubRegs: false, /* CoveredBySubRegs */
240 .SuperClasses: vIDSuperclasses, .SuperClassesSize: 2,
241 .OrderFunc: nullptr
242 };
243
244 extern const TargetRegisterClass vfIDRegClass = {
245 .MC: &SPIRVMCRegisterClasses[vfIDRegClassID],
246 .SubClassMask: vfIDSubClassMask,
247 .SuperRegIndices: SuperRegIdxSeqs + 0,
248 .LaneMask: LaneBitmask(0x0000000000000001),
249 .AllocationPriority: 0,
250 .GlobalPriority: false,
251 .TSFlags: 0x00, /* TSFlags */
252 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
253 .CoveredBySubRegs: false, /* CoveredBySubRegs */
254 .SuperClasses: vfIDSuperclasses, .SuperClassesSize: 2,
255 .OrderFunc: nullptr
256 };
257
258
259} // namespace SPIRV
260static const TargetRegisterClass *const SPIRVRegisterClasses[] = {
261 &SPIRV::ANYRegClass,
262 &SPIRV::IDRegClass,
263 &SPIRV::TYPERegClass,
264 &SPIRV::fIDRegClass,
265 &SPIRV::iIDRegClass,
266 &SPIRV::pIDRegClass,
267 &SPIRV::vpIDRegClass,
268 &SPIRV::vIDRegClass,
269 &SPIRV::vfIDRegClass,
270 };
271
272static const uint8_t SPIRVCostPerUseTable[] = {
2730, 0, 0, 0, 0, 0, 0, 0, };
274
275
276static const bool SPIRVInAllocatableClassTable[] = {
277false, true, true, true, true, true, true, true, };
278
279
280static const TargetRegisterInfoDesc SPIRVRegInfoDesc = { // Extra Descriptors
281.CostPerUse: SPIRVCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SPIRVInAllocatableClassTable};
282
283/// Get the weight in units of pressure for this register class.
284const RegClassWeight &SPIRVGenRegisterInfo::
285getRegClassWeight(const TargetRegisterClass *RC) const {
286 static const RegClassWeight RCWeightTable[] = {
287 {.RegWeight: 1, .WeightLimit: 7}, // ANY
288 {.RegWeight: 1, .WeightLimit: 6}, // ID
289 {.RegWeight: 1, .WeightLimit: 1}, // TYPE
290 {.RegWeight: 1, .WeightLimit: 1}, // fID
291 {.RegWeight: 1, .WeightLimit: 1}, // iID
292 {.RegWeight: 1, .WeightLimit: 1}, // pID
293 {.RegWeight: 1, .WeightLimit: 1}, // vpID
294 {.RegWeight: 1, .WeightLimit: 1}, // vID
295 {.RegWeight: 1, .WeightLimit: 1}, // vfID
296 };
297 return RCWeightTable[RC->getID()];
298}
299
300/// Get the weight in units of pressure for this register unit.
301unsigned SPIRVGenRegisterInfo::
302getRegUnitWeight(MCRegUnit RegUnit) const {
303 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
304 // All register units have unit weight.
305 return 1;
306}
307
308
309// Get the number of dimensions of register pressure.
310unsigned SPIRVGenRegisterInfo::getNumRegPressureSets() const {
311 return 8;
312}
313
314// Get the name of this register unit pressure set.
315const char *SPIRVGenRegisterInfo::
316getRegPressureSetName(unsigned Idx) const {
317 static const char *PressureNameTable[] = {
318 "TYPE",
319 "fID",
320 "iID",
321 "pID",
322 "vpID",
323 "vID",
324 "vfID",
325 "ID",
326 };
327 return PressureNameTable[Idx];
328}
329
330// Get the register unit pressure limit for this dimension.
331// This limit must be adjusted dynamically for reserved registers.
332unsigned SPIRVGenRegisterInfo::
333getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
334 static const uint8_t PressureLimitTable[] = {
335 1, // 0: TYPE
336 1, // 1: fID
337 1, // 2: iID
338 1, // 3: pID
339 1, // 4: vpID
340 1, // 5: vID
341 1, // 6: vfID
342 7, // 7: ID
343 };
344 return PressureLimitTable[Idx];
345}
346
347/// Table of pressure sets per register class or unit.
348static const int RCSetsTable[] = {
349 /* 0 */ 0, 7, -1,
350 /* 3 */ 1, 7, -1,
351 /* 6 */ 2, 7, -1,
352 /* 9 */ 3, 7, -1,
353 /* 12 */ 4, 7, -1,
354 /* 15 */ 5, 7, -1,
355 /* 18 */ 6, 7, -1,
356};
357
358/// Get the dimensions of register pressure impacted by this register class.
359/// Returns a -1 terminated array of pressure set IDs
360const int *SPIRVGenRegisterInfo::
361getRegClassPressureSets(const TargetRegisterClass *RC) const {
362 static const uint8_t RCSetStartTable[] = {
363 1,1,0,3,6,9,12,15,18,};
364 return &RCSetsTable[RCSetStartTable[RC->getID()]];
365}
366
367/// Get the dimensions of register pressure impacted by this register unit.
368/// Returns a -1 terminated array of pressure set IDs
369const int *SPIRVGenRegisterInfo::
370getRegUnitPressureSets(MCRegUnit RegUnit) const {
371 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
372 static const uint8_t RUSetStartTable[] = {
373 6,0,3,9,15,18,12,};
374 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
375}
376
377extern const MCRegisterDesc SPIRVRegDesc[];
378extern const int16_t SPIRVRegDiffLists[];
379extern const LaneBitmask SPIRVLaneMaskLists[];
380extern const char SPIRVRegStrings[];
381extern const char SPIRVRegClassStrings[];
382extern const MCPhysReg SPIRVRegUnitRoots[][2];
383extern const uint16_t SPIRVSubRegIdxLists[];
384extern const uint16_t SPIRVRegEncodingTable[];
385
386SPIRVGenRegisterInfo::
387SPIRVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
388 unsigned PC, unsigned HwMode)
389 : TargetRegisterInfo(&SPIRVRegInfoDesc, SPIRVRegisterClasses,
390 SPIRVSubRegIndexStrings, SPIRVSubRegIndexNameOffsets,
391 SPIRVSubRegIdxRangeTable, SPIRVSubRegIndexLaneMaskTable,
392
393 LaneBitmask(0xFFFFFFFFFFFFFFFF), SPIRVRegClassInfos, SPIRVVTLists, HwMode) {
394 InitMCRegisterInfo(D: SPIRVRegDesc, NR: 8, RA, PC,
395 C: SPIRVMCRegisterClasses, NC: 9, RURoots: SPIRVRegUnitRoots, NRU: 7, DL: SPIRVRegDiffLists,
396 RUMS: SPIRVLaneMaskLists, Strings: SPIRVRegStrings, ClassStrings: SPIRVRegClassStrings, SubIndices: SPIRVSubRegIdxLists, NumIndices: 1,
397 RET: SPIRVRegEncodingTable, RUI: nullptr);
398
399}
400
401
402
403ArrayRef<const uint32_t *> SPIRVGenRegisterInfo::getRegMasks() const {
404 return {};
405}
406
407bool SPIRVGenRegisterInfo::
408isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
409 return
410 false;
411}
412
413bool SPIRVGenRegisterInfo::
414isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
415 return
416 false;
417}
418
419bool SPIRVGenRegisterInfo::
420isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
421 return
422 false;
423}
424
425bool SPIRVGenRegisterInfo::
426isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
427 return
428 false;
429}
430
431bool SPIRVGenRegisterInfo::
432isConstantPhysReg(MCRegister PhysReg) const {
433 return
434 false;
435}
436
437ArrayRef<const char *> SPIRVGenRegisterInfo::getRegMaskNames() const {
438 return {};
439}
440
441const SPIRVFrameLowering *
442SPIRVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
443 return static_cast<const SPIRVFrameLowering *>(
444 MF.getSubtarget().getFrameLowering());
445}
446
447
448} // namespace llvm
449