1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SPIRVMCRegisterClasses[];
12
13static const MVT::SimpleValueType SPIRVVTLists[] = {
14 /* 0 */ MVT::i64, MVT::f64, MVT::i64, MVT::v2i64, MVT::v2f64, MVT::i64, MVT::Other,
15 /* 7 */ MVT::f64, MVT::Other,
16 /* 9 */ MVT::v2i64, MVT::Other,
17 /* 11 */ MVT::v2f64, MVT::Other,
18};
19static constexpr char SPIRVSubRegIndexStrings[] = {
20 /* dummy */ 0
21};
22
23
24static constexpr uint32_t SPIRVSubRegIndexNameOffsets[] = {
25 /* dummy */ 0
26};
27
28static const TargetRegisterInfo::SubRegCoveredBits SPIRVSubRegIdxRangeTable[] = {
29 { .Offset: 4294967295, .Size: 4294967295 },
30};
31
32
33static const LaneBitmask SPIRVSubRegIndexLaneMaskTable[] = {
34 LaneBitmask::getAll(),
35 };
36
37
38
39static const TargetRegisterInfo::RegClassInfo SPIRVRegClassInfos[] = {
40 // Mode = 0 (DefaultMode)
41 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // ANY
42 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 0 }, // ID
43 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // TYPE
44 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 7 }, // fID
45 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // iID
46 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // pID
47 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 5 }, // vpID
48 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 11 }, // vfID
49 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 64, /*SPIRVVTLists+*/.VTListOffset: 9 }, // viID
50};
51static const uint32_t ANYSubClassMask[] = {
52 0x000001ff,
53};
54
55static const uint32_t IDSubClassMask[] = {
56 0x000001fa,
57};
58
59static const uint32_t TYPESubClassMask[] = {
60 0x00000004,
61};
62
63static const uint32_t fIDSubClassMask[] = {
64 0x00000008,
65};
66
67static const uint32_t iIDSubClassMask[] = {
68 0x00000010,
69};
70
71static const uint32_t pIDSubClassMask[] = {
72 0x00000020,
73};
74
75static const uint32_t vpIDSubClassMask[] = {
76 0x00000040,
77};
78
79static const uint32_t vfIDSubClassMask[] = {
80 0x00000080,
81};
82
83static const uint32_t viIDSubClassMask[] = {
84 0x00000100,
85};
86
87static const uint16_t SuperRegIdxSeqs[] = {
88 /* 0 */ 0,
89};
90
91static unsigned const IDSuperclasses[] = {
92 SPIRV::ANYRegClassID,
93};
94
95static unsigned const TYPESuperclasses[] = {
96 SPIRV::ANYRegClassID,
97};
98
99static unsigned const fIDSuperclasses[] = {
100 SPIRV::ANYRegClassID,
101 SPIRV::IDRegClassID,
102};
103
104static unsigned const iIDSuperclasses[] = {
105 SPIRV::ANYRegClassID,
106 SPIRV::IDRegClassID,
107};
108
109static unsigned const pIDSuperclasses[] = {
110 SPIRV::ANYRegClassID,
111 SPIRV::IDRegClassID,
112};
113
114static unsigned const vpIDSuperclasses[] = {
115 SPIRV::ANYRegClassID,
116 SPIRV::IDRegClassID,
117};
118
119static unsigned const vfIDSuperclasses[] = {
120 SPIRV::ANYRegClassID,
121 SPIRV::IDRegClassID,
122};
123
124static unsigned const viIDSuperclasses[] = {
125 SPIRV::ANYRegClassID,
126 SPIRV::IDRegClassID,
127};
128
129namespace SPIRV {
130
131// Register class instances.
132 extern const TargetRegisterClass ANYRegClass = {
133 .MC: &SPIRVMCRegisterClasses[ANYRegClassID],
134 .SubClassMask: ANYSubClassMask,
135 .SuperRegIndices: SuperRegIdxSeqs + 0,
136 .LaneMask: LaneBitmask(0x0000000000000001),
137 .AllocationPriority: 0,
138 .GlobalPriority: false,
139 .TSFlags: 0x00, /* TSFlags */
140 .SpillStackID: 0, /* SpillStackID */
141 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
142 .CoveredBySubRegs: false, /* CoveredBySubRegs */
143 .SuperClasses: nullptr, .SuperClassesSize: 0,
144 .OrderFunc: nullptr
145 };
146
147 extern const TargetRegisterClass IDRegClass = {
148 .MC: &SPIRVMCRegisterClasses[IDRegClassID],
149 .SubClassMask: IDSubClassMask,
150 .SuperRegIndices: SuperRegIdxSeqs + 0,
151 .LaneMask: LaneBitmask(0x0000000000000001),
152 .AllocationPriority: 0,
153 .GlobalPriority: false,
154 .TSFlags: 0x00, /* TSFlags */
155 .SpillStackID: 0, /* SpillStackID */
156 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
157 .CoveredBySubRegs: false, /* CoveredBySubRegs */
158 .SuperClasses: IDSuperclasses, .SuperClassesSize: 1,
159 .OrderFunc: nullptr
160 };
161
162 extern const TargetRegisterClass TYPERegClass = {
163 .MC: &SPIRVMCRegisterClasses[TYPERegClassID],
164 .SubClassMask: TYPESubClassMask,
165 .SuperRegIndices: SuperRegIdxSeqs + 0,
166 .LaneMask: LaneBitmask(0x0000000000000001),
167 .AllocationPriority: 0,
168 .GlobalPriority: false,
169 .TSFlags: 0x00, /* TSFlags */
170 .SpillStackID: 0, /* SpillStackID */
171 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
172 .CoveredBySubRegs: false, /* CoveredBySubRegs */
173 .SuperClasses: TYPESuperclasses, .SuperClassesSize: 1,
174 .OrderFunc: nullptr
175 };
176
177 extern const TargetRegisterClass fIDRegClass = {
178 .MC: &SPIRVMCRegisterClasses[fIDRegClassID],
179 .SubClassMask: fIDSubClassMask,
180 .SuperRegIndices: SuperRegIdxSeqs + 0,
181 .LaneMask: LaneBitmask(0x0000000000000001),
182 .AllocationPriority: 0,
183 .GlobalPriority: false,
184 .TSFlags: 0x00, /* TSFlags */
185 .SpillStackID: 0, /* SpillStackID */
186 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
187 .CoveredBySubRegs: false, /* CoveredBySubRegs */
188 .SuperClasses: fIDSuperclasses, .SuperClassesSize: 2,
189 .OrderFunc: nullptr
190 };
191
192 extern const TargetRegisterClass iIDRegClass = {
193 .MC: &SPIRVMCRegisterClasses[iIDRegClassID],
194 .SubClassMask: iIDSubClassMask,
195 .SuperRegIndices: SuperRegIdxSeqs + 0,
196 .LaneMask: LaneBitmask(0x0000000000000001),
197 .AllocationPriority: 0,
198 .GlobalPriority: false,
199 .TSFlags: 0x00, /* TSFlags */
200 .SpillStackID: 0, /* SpillStackID */
201 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
202 .CoveredBySubRegs: false, /* CoveredBySubRegs */
203 .SuperClasses: iIDSuperclasses, .SuperClassesSize: 2,
204 .OrderFunc: nullptr
205 };
206
207 extern const TargetRegisterClass pIDRegClass = {
208 .MC: &SPIRVMCRegisterClasses[pIDRegClassID],
209 .SubClassMask: pIDSubClassMask,
210 .SuperRegIndices: SuperRegIdxSeqs + 0,
211 .LaneMask: LaneBitmask(0x0000000000000001),
212 .AllocationPriority: 0,
213 .GlobalPriority: false,
214 .TSFlags: 0x00, /* TSFlags */
215 .SpillStackID: 0, /* SpillStackID */
216 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
217 .CoveredBySubRegs: false, /* CoveredBySubRegs */
218 .SuperClasses: pIDSuperclasses, .SuperClassesSize: 2,
219 .OrderFunc: nullptr
220 };
221
222 extern const TargetRegisterClass vpIDRegClass = {
223 .MC: &SPIRVMCRegisterClasses[vpIDRegClassID],
224 .SubClassMask: vpIDSubClassMask,
225 .SuperRegIndices: SuperRegIdxSeqs + 0,
226 .LaneMask: LaneBitmask(0x0000000000000001),
227 .AllocationPriority: 0,
228 .GlobalPriority: false,
229 .TSFlags: 0x00, /* TSFlags */
230 .SpillStackID: 0, /* SpillStackID */
231 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
232 .CoveredBySubRegs: false, /* CoveredBySubRegs */
233 .SuperClasses: vpIDSuperclasses, .SuperClassesSize: 2,
234 .OrderFunc: nullptr
235 };
236
237 extern const TargetRegisterClass vfIDRegClass = {
238 .MC: &SPIRVMCRegisterClasses[vfIDRegClassID],
239 .SubClassMask: vfIDSubClassMask,
240 .SuperRegIndices: SuperRegIdxSeqs + 0,
241 .LaneMask: LaneBitmask(0x0000000000000001),
242 .AllocationPriority: 0,
243 .GlobalPriority: false,
244 .TSFlags: 0x00, /* TSFlags */
245 .SpillStackID: 0, /* SpillStackID */
246 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
247 .CoveredBySubRegs: false, /* CoveredBySubRegs */
248 .SuperClasses: vfIDSuperclasses, .SuperClassesSize: 2,
249 .OrderFunc: nullptr
250 };
251
252 extern const TargetRegisterClass viIDRegClass = {
253 .MC: &SPIRVMCRegisterClasses[viIDRegClassID],
254 .SubClassMask: viIDSubClassMask,
255 .SuperRegIndices: SuperRegIdxSeqs + 0,
256 .LaneMask: LaneBitmask(0x0000000000000001),
257 .AllocationPriority: 0,
258 .GlobalPriority: false,
259 .TSFlags: 0x00, /* TSFlags */
260 .SpillStackID: 0, /* SpillStackID */
261 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
262 .CoveredBySubRegs: false, /* CoveredBySubRegs */
263 .SuperClasses: viIDSuperclasses, .SuperClassesSize: 2,
264 .OrderFunc: nullptr
265 };
266
267
268} // namespace SPIRV
269static const TargetRegisterClass *const SPIRVRegisterClasses[] = {
270 &SPIRV::ANYRegClass,
271 &SPIRV::IDRegClass,
272 &SPIRV::TYPERegClass,
273 &SPIRV::fIDRegClass,
274 &SPIRV::iIDRegClass,
275 &SPIRV::pIDRegClass,
276 &SPIRV::vpIDRegClass,
277 &SPIRV::vfIDRegClass,
278 &SPIRV::viIDRegClass,
279 };
280
281static const uint8_t SPIRVCostPerUseTable[] = {
2820, 0, 0, 0, 0, 0, 0, 0, };
283
284
285static const bool SPIRVInAllocatableClassTable[] = {
286false, true, true, true, true, true, true, true, };
287
288
289static const TargetRegisterInfoDesc SPIRVRegInfoDesc = { // Extra Descriptors
290.CostPerUse: SPIRVCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SPIRVInAllocatableClassTable};
291
292/// Get the weight in units of pressure for this register class.
293const RegClassWeight &SPIRVGenRegisterInfo::
294getRegClassWeight(const TargetRegisterClass *RC) const {
295 static const RegClassWeight RCWeightTable[] = {
296 {.RegWeight: 1, .WeightLimit: 7}, // ANY
297 {.RegWeight: 1, .WeightLimit: 6}, // ID
298 {.RegWeight: 1, .WeightLimit: 1}, // TYPE
299 {.RegWeight: 1, .WeightLimit: 1}, // fID
300 {.RegWeight: 1, .WeightLimit: 1}, // iID
301 {.RegWeight: 1, .WeightLimit: 1}, // pID
302 {.RegWeight: 1, .WeightLimit: 1}, // vpID
303 {.RegWeight: 1, .WeightLimit: 1}, // vfID
304 {.RegWeight: 1, .WeightLimit: 1}, // viID
305 };
306 return RCWeightTable[RC->getID()];
307}
308
309/// Get the weight in units of pressure for this register unit.
310unsigned SPIRVGenRegisterInfo::
311getRegUnitWeight(MCRegUnit RegUnit) const {
312 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
313 // All register units have unit weight.
314 return 1;
315}
316
317
318// Get the number of dimensions of register pressure.
319unsigned SPIRVGenRegisterInfo::getNumRegPressureSets() const {
320 return 8;
321}
322
323// Get the name of this register unit pressure set.
324const char *SPIRVGenRegisterInfo::
325getRegPressureSetName(unsigned Idx) const {
326 static const char *PressureNameTable[] = {
327 "TYPE",
328 "fID",
329 "iID",
330 "pID",
331 "vpID",
332 "vfID",
333 "viID",
334 "ID",
335 };
336 return PressureNameTable[Idx];
337}
338
339// Get the register unit pressure limit for this dimension.
340// This limit must be adjusted dynamically for reserved registers.
341unsigned SPIRVGenRegisterInfo::
342getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
343 static const uint8_t PressureLimitTable[] = {
344 1, // 0: TYPE
345 1, // 1: fID
346 1, // 2: iID
347 1, // 3: pID
348 1, // 4: vpID
349 1, // 5: vfID
350 1, // 6: viID
351 7, // 7: ID
352 };
353 return PressureLimitTable[Idx];
354}
355
356/// Table of pressure sets per register class or unit.
357static const int RCSetsTable[] = {
358 /* 0 */ 0, 7, -1,
359 /* 3 */ 1, 7, -1,
360 /* 6 */ 2, 7, -1,
361 /* 9 */ 3, 7, -1,
362 /* 12 */ 4, 7, -1,
363 /* 15 */ 5, 7, -1,
364 /* 18 */ 6, 7, -1,
365};
366
367/// Get the dimensions of register pressure impacted by this register class.
368/// Returns a -1 terminated array of pressure set IDs
369const int *SPIRVGenRegisterInfo::
370getRegClassPressureSets(const TargetRegisterClass *RC) const {
371 static const uint8_t RCSetStartTable[] = {
372 1,1,0,3,6,9,12,15,18,};
373 return &RCSetsTable[RCSetStartTable[RC->getID()]];
374}
375
376/// Get the dimensions of register pressure impacted by this register unit.
377/// Returns a -1 terminated array of pressure set IDs
378const int *SPIRVGenRegisterInfo::
379getRegUnitPressureSets(MCRegUnit RegUnit) const {
380 assert(static_cast<unsigned>(RegUnit) < 7 && "invalid register unit");
381 static const uint8_t RUSetStartTable[] = {
382 6,0,3,9,15,18,12,};
383 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
384}
385
386
387// Register to minimal register class mapping
388
389const TargetRegisterClass *SPIRVGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
390 static const uint16_t InvalidRegClassID = UINT16_MAX;
391
392 static const uint16_t Mapping[8] = {
393 InvalidRegClassID, // NoRegister
394 SPIRV::iIDRegClassID, // ID0
395 SPIRV::TYPERegClassID, // TYPE0
396 SPIRV::fIDRegClassID, // fID0
397 SPIRV::pIDRegClassID, // pID0
398 SPIRV::vfIDRegClassID, // vfID0
399 SPIRV::viIDRegClassID, // viID0
400 SPIRV::vpIDRegClassID, // vpID0
401 };
402
403 assert(Reg < ArrayRef(Mapping).size());
404 unsigned RCID = Mapping[Reg.id()];
405 if (RCID == InvalidRegClassID)
406 return nullptr;
407 return SPIRVRegisterClasses[RCID];
408}
409extern const MCRegisterDesc SPIRVRegDesc[];
410extern const int16_t SPIRVRegDiffLists[];
411extern const LaneBitmask SPIRVLaneMaskLists[];
412extern const char SPIRVRegStrings[];
413extern const char SPIRVRegClassStrings[];
414extern const MCPhysReg SPIRVRegUnitRoots[][2];
415extern const uint16_t SPIRVSubRegIdxLists[];
416extern const uint16_t SPIRVRegEncodingTable[];
417
418SPIRVGenRegisterInfo::
419SPIRVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
420 unsigned PC, unsigned HwMode)
421 : TargetRegisterInfo(&SPIRVRegInfoDesc, SPIRVRegisterClasses,
422 SPIRVSubRegIndexStrings, SPIRVSubRegIndexNameOffsets,
423 SPIRVSubRegIdxRangeTable, SPIRVSubRegIndexLaneMaskTable,
424
425 LaneBitmask(0xFFFFFFFFFFFFFFFF), SPIRVRegClassInfos, SPIRVVTLists, HwMode) {
426 InitMCRegisterInfo(D: SPIRVRegDesc, NR: 8, RA, PC,
427 C: SPIRVMCRegisterClasses, NC: 9, RURoots: SPIRVRegUnitRoots, NRU: 7, DL: SPIRVRegDiffLists,
428 RUMS: SPIRVLaneMaskLists, Strings: SPIRVRegStrings, ClassStrings: SPIRVRegClassStrings, SubIndices: SPIRVSubRegIdxLists, NumIndices: 1,
429 RET: SPIRVRegEncodingTable, RUI: nullptr);
430
431}
432
433
434
435ArrayRef<const uint32_t *> SPIRVGenRegisterInfo::getRegMasks() const {
436 return {};
437}
438
439bool SPIRVGenRegisterInfo::
440isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
441 return
442 false;
443}
444
445bool SPIRVGenRegisterInfo::
446isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
447 return
448 false;
449}
450
451bool SPIRVGenRegisterInfo::
452isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
453 return
454 false;
455}
456
457bool SPIRVGenRegisterInfo::
458isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
459 return
460 false;
461}
462
463bool SPIRVGenRegisterInfo::
464isConstantPhysReg(MCRegister PhysReg) const {
465 return
466 false;
467}
468
469ArrayRef<const char *> SPIRVGenRegisterInfo::getRegMaskNames() const {
470 return {};
471}
472
473const SPIRVFrameLowering *
474SPIRVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
475 return static_cast<const SPIRVFrameLowering *>(
476 MF.getSubtarget().getFrameLowering());
477}
478
479
480} // namespace llvm
481