1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* * Sparc Disassembler *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#include "llvm/MC/MCInst.h"
11#include "llvm/MC/MCSubtargetInfo.h"
12#include "llvm/Support/DataTypes.h"
13#include "llvm/Support/Debug.h"
14#include "llvm/Support/LEB128.h"
15#include "llvm/Support/raw_ostream.h"
16#include "llvm/TargetParser/SubtargetFeature.h"
17#include <assert.h>
18
19namespace {
20
21// InsnBitWidth is essentially a type trait used by the decoder emitter to query
22// the supported bitwidth for a given type. But default, the value is 0, making
23// it an invalid type for use as `InsnType` when instantiating the decoder.
24// Individual targets are expected to provide specializations for these based
25// on their usage.
26template <typename T> constexpr uint32_t InsnBitWidth = 0;
27
28[[maybe_unused]]
29static DecodeStatus Decodesparc_ptr_rcRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
30 switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) {
31 case 0: // DefaultMode
32 return DecodeIntRegsRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
33 case 1: // SPARC64
34 return DecodeI64RegsRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
35 default:
36 llvm_unreachable("no decoder for hwmode");
37 }
38}
39
40
41static const uint8_t DecoderTableSparc32[5292] = {
42 OPC_SwitchField, 30, 2, // 0: switch Inst[31:30] {
43 0, 225, 2, // 3: case 0x0: {
44 OPC_SwitchField, 22, 3, // 6: switch Inst[24:22] {
45 0, 8, // 9: case 0x0: {
46 OPC_CheckField, 25, 5, 0, // 11: check Inst[29:25] == 0x0
47 OPC_Decode, 222, 6, 0, // 15: decode to UNIMP using decoder 0
48 // 15: }
49 1, 87, // 19: case 0x1: {
50 OPC_SwitchField, 19, 3, // 21: switch Inst[21:19] {
51 0, 19, // 24: case 0x0: {
52 OPC_SwitchField, 29, 1, // 26: switch Inst[29] {
53 0, 6, // 29: case 0x0: {
54 OPC_CheckPredicate, 0, // 31: check predicate 0
55 OPC_Decode, 142, 3, 1, // 33: decode to BPICCNT using decoder 1
56 // 33: }
57 1, 0, // 37: case 0x1: {
58 OPC_CheckPredicate, 0, // 39: check predicate 0
59 OPC_Decode, 141, 3, 1, // 41: decode to BPICCANT using decoder 1
60 // 41: }
61 // 41: } // switch Inst[29]
62 // 41: }
63 1, 19, // 45: case 0x1: {
64 OPC_SwitchField, 29, 1, // 47: switch Inst[29] {
65 0, 6, // 50: case 0x0: {
66 OPC_CheckPredicate, 0, // 52: check predicate 0
67 OPC_Decode, 139, 3, 1, // 54: decode to BPICC using decoder 1
68 // 54: }
69 1, 0, // 58: case 0x1: {
70 OPC_CheckPredicate, 0, // 60: check predicate 0
71 OPC_Decode, 140, 3, 1, // 62: decode to BPICCA using decoder 1
72 // 62: }
73 // 62: } // switch Inst[29]
74 // 62: }
75 4, 19, // 66: case 0x4: {
76 OPC_SwitchField, 29, 1, // 68: switch Inst[29] {
77 0, 6, // 71: case 0x0: {
78 OPC_CheckPredicate, 1, // 73: check predicate 1
79 OPC_Decode, 150, 3, 1, // 75: decode to BPXCCNT using decoder 1
80 // 75: }
81 1, 0, // 79: case 0x1: {
82 OPC_CheckPredicate, 1, // 81: check predicate 1
83 OPC_Decode, 149, 3, 1, // 83: decode to BPXCCANT using decoder 1
84 // 83: }
85 // 83: } // switch Inst[29]
86 // 83: }
87 5, 0, // 87: case 0x5: {
88 OPC_SwitchField, 29, 1, // 89: switch Inst[29] {
89 0, 6, // 92: case 0x0: {
90 OPC_CheckPredicate, 1, // 94: check predicate 1
91 OPC_Decode, 147, 3, 1, // 96: decode to BPXCC using decoder 1
92 // 96: }
93 1, 0, // 100: case 0x1: {
94 OPC_CheckPredicate, 1, // 102: check predicate 1
95 OPC_Decode, 148, 3, 1, // 104: decode to BPXCCA using decoder 1
96 // 104: }
97 // 104: } // switch Inst[29]
98 // 104: }
99 // 104: } // switch Inst[21:19]
100 // 104: }
101 2, 25, // 108: case 0x2: {
102 OPC_SwitchField, 29, 1, // 110: switch Inst[29] {
103 0, 14, // 113: case 0x0: {
104 OPC_Scope, 8, // 115: try {
105 OPC_CheckField, 25, 4, 8, // 117: check Inst[28:25] == 0x8
106 OPC_Decode, 129, 3, 2, // 121: decode to BA using decoder 2
107 // 121: } else try {
108 OPC_Decode, 130, 3, 3, // 125: decode to BCOND using decoder 3
109 // 125: }
110 // 125: }
111 1, 0, // 129: case 0x1: {
112 OPC_Decode, 131, 3, 3, // 131: decode to BCONDA using decoder 3
113 // 131: }
114 // 131: } // switch Inst[29]
115 // 131: }
116 3, 97, // 135: case 0x3: {
117 OPC_SwitchField, 28, 1, // 137: switch Inst[28] {
118 0, 45, // 140: case 0x0: {
119 OPC_SwitchField, 19, 1, // 142: switch Inst[19] {
120 0, 19, // 145: case 0x0: {
121 OPC_SwitchField, 29, 1, // 147: switch Inst[29] {
122 0, 6, // 150: case 0x0: {
123 OPC_CheckPredicate, 0, // 152: check predicate 0
124 OPC_Decode, 146, 3, 4, // 154: decode to BPRNT using decoder 4
125 // 154: }
126 1, 0, // 158: case 0x1: {
127 OPC_CheckPredicate, 0, // 160: check predicate 0
128 OPC_Decode, 145, 3, 4, // 162: decode to BPRANT using decoder 4
129 // 162: }
130 // 162: } // switch Inst[29]
131 // 162: }
132 1, 0, // 166: case 0x1: {
133 OPC_SwitchField, 29, 1, // 168: switch Inst[29] {
134 0, 6, // 171: case 0x0: {
135 OPC_CheckPredicate, 0, // 173: check predicate 0
136 OPC_Decode, 143, 3, 4, // 175: decode to BPR using decoder 4
137 // 175: }
138 1, 0, // 179: case 0x1: {
139 OPC_CheckPredicate, 0, // 181: check predicate 0
140 OPC_Decode, 144, 3, 4, // 183: decode to BPRA using decoder 4
141 // 183: }
142 // 183: } // switch Inst[29]
143 // 183: }
144 // 183: } // switch Inst[19]
145 // 183: }
146 1, 0, // 187: case 0x1: {
147 OPC_SwitchField, 13, 1, // 189: switch Inst[13] {
148 0, 19, // 192: case 0x0: {
149 OPC_SwitchField, 21, 1, // 194: switch Inst[21] {
150 0, 6, // 197: case 0x0: {
151 OPC_CheckPredicate, 2, // 199: check predicate 2
152 OPC_Decode, 172, 3, 5, // 201: decode to CWBCONDrr using decoder 5
153 // 201: }
154 1, 0, // 205: case 0x1: {
155 OPC_CheckPredicate, 2, // 207: check predicate 2
156 OPC_Decode, 174, 3, 5, // 209: decode to CXBCONDrr using decoder 5
157 // 209: }
158 // 209: } // switch Inst[21]
159 // 209: }
160 1, 0, // 213: case 0x1: {
161 OPC_SwitchField, 21, 1, // 215: switch Inst[21] {
162 0, 6, // 218: case 0x0: {
163 OPC_CheckPredicate, 2, // 220: check predicate 2
164 OPC_Decode, 171, 3, 6, // 222: decode to CWBCONDri using decoder 6
165 // 222: }
166 1, 0, // 226: case 0x1: {
167 OPC_CheckPredicate, 2, // 228: check predicate 2
168 OPC_Decode, 173, 3, 6, // 230: decode to CXBCONDri using decoder 6
169 // 230: }
170 // 230: } // switch Inst[21]
171 // 230: }
172 // 230: } // switch Inst[13]
173 // 230: }
174 // 230: } // switch Inst[28]
175 // 230: }
176 4, 18, // 234: case 0x4: {
177 OPC_Scope, 12, // 236: try {
178 OPC_CheckField, 0, 22, 0, // 238: check Inst[21:0] == 0x0
179 OPC_CheckField, 25, 5, 0, // 242: check Inst[29:25] == 0x0
180 OPC_Decode, 187, 5, 7, // 246: decode to NOP using decoder 7
181 // 246: } else try {
182 OPC_Decode, 230, 5, 8, // 250: decode to SETHIi using decoder 8
183 // 250: }
184 // 250: }
185 5, 69, // 254: case 0x5: {
186 OPC_SwitchField, 19, 1, // 256: switch Inst[19] {
187 0, 19, // 259: case 0x0: {
188 OPC_SwitchField, 29, 1, // 261: switch Inst[29] {
189 0, 6, // 264: case 0x0: {
190 OPC_CheckPredicate, 0, // 266: check predicate 0
191 OPC_Decode, 138, 3, 9, // 268: decode to BPFCCNT using decoder 9
192 // 268: }
193 1, 0, // 272: case 0x1: {
194 OPC_CheckPredicate, 0, // 274: check predicate 0
195 OPC_Decode, 137, 3, 9, // 276: decode to BPFCCANT using decoder 9
196 // 276: }
197 // 276: } // switch Inst[29]
198 // 276: }
199 1, 0, // 280: case 0x1: {
200 OPC_SwitchField, 29, 1, // 282: switch Inst[29] {
201 0, 18, // 285: case 0x0: {
202 OPC_Scope, 10, // 287: try {
203 OPC_CheckField, 20, 2, 0, // 289: check Inst[21:20] == 0x0
204 OPC_CheckPredicate, 0, // 293: check predicate 0
205 OPC_Decode, 208, 3, 1, // 295: decode to FBCOND_V9 using decoder 1
206 // 295: } else try {
207 OPC_CheckPredicate, 0, // 299: check predicate 0
208 OPC_Decode, 135, 3, 9, // 301: decode to BPFCC using decoder 9
209 // 301: }
210 // 301: }
211 1, 0, // 305: case 0x1: {
212 OPC_Scope, 10, // 307: try {
213 OPC_CheckField, 20, 2, 0, // 309: check Inst[21:20] == 0x0
214 OPC_CheckPredicate, 0, // 313: check predicate 0
215 OPC_Decode, 207, 3, 1, // 315: decode to FBCONDA_V9 using decoder 1
216 // 315: } else try {
217 OPC_CheckPredicate, 0, // 319: check predicate 0
218 OPC_Decode, 136, 3, 9, // 321: decode to BPFCCA using decoder 9
219 // 321: }
220 // 321: }
221 // 321: } // switch Inst[29]
222 // 321: }
223 // 321: } // switch Inst[19]
224 // 321: }
225 6, 15, // 325: case 0x6: {
226 OPC_SwitchField, 29, 1, // 327: switch Inst[29] {
227 0, 4, // 330: case 0x0: {
228 OPC_Decode, 205, 3, 3, // 332: decode to FBCOND using decoder 3
229 // 332: }
230 1, 0, // 336: case 0x1: {
231 OPC_Decode, 206, 3, 3, // 338: decode to FBCONDA using decoder 3
232 // 338: }
233 // 338: } // switch Inst[29]
234 // 338: }
235 7, 0, // 342: case 0x7: {
236 OPC_SwitchField, 29, 1, // 344: switch Inst[29] {
237 0, 4, // 347: case 0x0: {
238 OPC_Decode, 168, 3, 3, // 349: decode to CPBCOND using decoder 3
239 // 349: }
240 1, 0, // 353: case 0x1: {
241 OPC_Decode, 169, 3, 3, // 355: decode to CPBCONDA using decoder 3
242 // 355: }
243 // 355: } // switch Inst[29]
244 // 355: }
245 // 355: } // switch Inst[24:22]
246 // 355: }
247 1, 4, // 359: case 0x1: {
248 OPC_Decode, 152, 3, 10, // 361: decode to CALL using decoder 10
249 // 361: }
250 2, 191, 30, // 365: case 0x2: {
251 OPC_SwitchField, 19, 6, // 368: switch Inst[24:19] {
252 0, 19, // 371: case 0x0: {
253 OPC_SwitchField, 13, 1, // 373: switch Inst[13] {
254 0, 8, // 376: case 0x0: {
255 OPC_CheckField, 5, 8, 0, // 378: check Inst[12:5] == 0x0
256 OPC_Decode, 231, 2, 11, // 382: decode to ADDrr using decoder 11
257 // 382: }
258 1, 0, // 386: case 0x1: {
259 OPC_Decode, 230, 2, 12, // 388: decode to ADDri using decoder 12
260 // 388: }
261 // 388: } // switch Inst[13]
262 // 388: }
263 1, 19, // 392: case 0x1: {
264 OPC_SwitchField, 13, 1, // 394: switch Inst[13] {
265 0, 8, // 397: case 0x0: {
266 OPC_CheckField, 5, 8, 0, // 399: check Inst[12:5] == 0x0
267 OPC_Decode, 253, 2, 11, // 403: decode to ANDrr using decoder 11
268 // 403: }
269 1, 0, // 407: case 0x1: {
270 OPC_Decode, 252, 2, 12, // 409: decode to ANDri using decoder 12
271 // 409: }
272 // 409: } // switch Inst[13]
273 // 409: }
274 2, 19, // 413: case 0x2: {
275 OPC_SwitchField, 13, 1, // 415: switch Inst[13] {
276 0, 8, // 418: case 0x0: {
277 OPC_CheckField, 5, 8, 0, // 420: check Inst[12:5] == 0x0
278 OPC_Decode, 196, 5, 11, // 424: decode to ORrr using decoder 11
279 // 424: }
280 1, 0, // 428: case 0x1: {
281 OPC_Decode, 195, 5, 12, // 430: decode to ORri using decoder 12
282 // 430: }
283 // 430: } // switch Inst[13]
284 // 430: }
285 3, 19, // 434: case 0x3: {
286 OPC_SwitchField, 13, 1, // 436: switch Inst[13] {
287 0, 8, // 439: case 0x0: {
288 OPC_CheckField, 5, 8, 0, // 441: check Inst[12:5] == 0x0
289 OPC_Decode, 253, 6, 11, // 445: decode to XORrr using decoder 11
290 // 445: }
291 1, 0, // 449: case 0x1: {
292 OPC_Decode, 252, 6, 12, // 451: decode to XORri using decoder 12
293 // 451: }
294 // 451: } // switch Inst[13]
295 // 451: }
296 4, 19, // 455: case 0x4: {
297 OPC_SwitchField, 13, 1, // 457: switch Inst[13] {
298 0, 8, // 460: case 0x0: {
299 OPC_CheckField, 5, 8, 0, // 462: check Inst[12:5] == 0x0
300 OPC_Decode, 181, 6, 11, // 466: decode to SUBrr using decoder 11
301 // 466: }
302 1, 0, // 470: case 0x1: {
303 OPC_Decode, 180, 6, 12, // 472: decode to SUBri using decoder 12
304 // 472: }
305 // 472: } // switch Inst[13]
306 // 472: }
307 5, 19, // 476: case 0x5: {
308 OPC_SwitchField, 13, 1, // 478: switch Inst[13] {
309 0, 8, // 481: case 0x0: {
310 OPC_CheckField, 5, 8, 0, // 483: check Inst[12:5] == 0x0
311 OPC_Decode, 251, 2, 11, // 487: decode to ANDNrr using decoder 11
312 // 487: }
313 1, 0, // 491: case 0x1: {
314 OPC_Decode, 250, 2, 12, // 493: decode to ANDNri using decoder 12
315 // 493: }
316 // 493: } // switch Inst[13]
317 // 493: }
318 6, 19, // 497: case 0x6: {
319 OPC_SwitchField, 13, 1, // 499: switch Inst[13] {
320 0, 8, // 502: case 0x0: {
321 OPC_CheckField, 5, 8, 0, // 504: check Inst[12:5] == 0x0
322 OPC_Decode, 194, 5, 11, // 508: decode to ORNrr using decoder 11
323 // 508: }
324 1, 0, // 512: case 0x1: {
325 OPC_Decode, 193, 5, 12, // 514: decode to ORNri using decoder 12
326 // 514: }
327 // 514: } // switch Inst[13]
328 // 514: }
329 7, 19, // 518: case 0x7: {
330 OPC_SwitchField, 13, 1, // 520: switch Inst[13] {
331 0, 8, // 523: case 0x0: {
332 OPC_CheckField, 5, 8, 0, // 525: check Inst[12:5] == 0x0
333 OPC_Decode, 249, 6, 11, // 529: decode to XNORrr using decoder 11
334 // 529: }
335 1, 0, // 533: case 0x1: {
336 OPC_Decode, 248, 6, 12, // 535: decode to XNORri using decoder 12
337 // 535: }
338 // 535: } // switch Inst[13]
339 // 535: }
340 8, 19, // 539: case 0x8: {
341 OPC_SwitchField, 13, 1, // 541: switch Inst[13] {
342 0, 8, // 544: case 0x0: {
343 OPC_CheckField, 5, 8, 0, // 546: check Inst[12:5] == 0x0
344 OPC_Decode, 225, 2, 11, // 550: decode to ADDCrr using decoder 11
345 // 550: }
346 1, 0, // 554: case 0x1: {
347 OPC_Decode, 224, 2, 12, // 556: decode to ADDCri using decoder 12
348 // 556: }
349 // 556: } // switch Inst[13]
350 // 556: }
351 9, 23, // 560: case 0x9: {
352 OPC_SwitchField, 13, 1, // 562: switch Inst[13] {
353 0, 10, // 565: case 0x0: {
354 OPC_CheckPredicate, 0, // 567: check predicate 0
355 OPC_CheckField, 5, 8, 0, // 569: check Inst[12:5] == 0x0
356 OPC_Decode, 186, 5, 13, // 573: decode to MULXrr using decoder 13
357 // 573: }
358 1, 0, // 577: case 0x1: {
359 OPC_CheckPredicate, 0, // 579: check predicate 0
360 OPC_Decode, 185, 5, 14, // 581: decode to MULXri using decoder 14
361 // 581: }
362 // 581: } // switch Inst[13]
363 // 581: }
364 10, 19, // 585: case 0xa: {
365 OPC_SwitchField, 13, 1, // 587: switch Inst[13] {
366 0, 8, // 590: case 0x0: {
367 OPC_CheckField, 5, 8, 0, // 592: check Inst[12:5] == 0x0
368 OPC_Decode, 221, 6, 11, // 596: decode to UMULrr using decoder 11
369 // 596: }
370 1, 0, // 600: case 0x1: {
371 OPC_Decode, 220, 6, 12, // 602: decode to UMULri using decoder 12
372 // 602: }
373 // 602: } // switch Inst[13]
374 // 602: }
375 11, 19, // 606: case 0xb: {
376 OPC_SwitchField, 13, 1, // 608: switch Inst[13] {
377 0, 8, // 611: case 0x0: {
378 OPC_CheckField, 5, 8, 0, // 613: check Inst[12:5] == 0x0
379 OPC_Decode, 246, 5, 11, // 617: decode to SMULrr using decoder 11
380 // 617: }
381 1, 0, // 621: case 0x1: {
382 OPC_Decode, 245, 5, 12, // 623: decode to SMULri using decoder 12
383 // 623: }
384 // 623: } // switch Inst[13]
385 // 623: }
386 12, 19, // 627: case 0xc: {
387 OPC_SwitchField, 13, 1, // 629: switch Inst[13] {
388 0, 8, // 632: case 0x0: {
389 OPC_CheckField, 5, 8, 0, // 634: check Inst[12:5] == 0x0
390 OPC_Decode, 177, 6, 11, // 638: decode to SUBCrr using decoder 11
391 // 638: }
392 1, 0, // 642: case 0x1: {
393 OPC_Decode, 176, 6, 12, // 644: decode to SUBCri using decoder 12
394 // 644: }
395 // 644: } // switch Inst[13]
396 // 644: }
397 13, 23, // 648: case 0xd: {
398 OPC_SwitchField, 13, 1, // 650: switch Inst[13] {
399 0, 10, // 653: case 0x0: {
400 OPC_CheckPredicate, 0, // 655: check predicate 0
401 OPC_CheckField, 5, 8, 0, // 657: check Inst[12:5] == 0x0
402 OPC_Decode, 212, 6, 13, // 661: decode to UDIVXrr using decoder 13
403 // 661: }
404 1, 0, // 665: case 0x1: {
405 OPC_CheckPredicate, 0, // 667: check predicate 0
406 OPC_Decode, 211, 6, 14, // 669: decode to UDIVXri using decoder 14
407 // 669: }
408 // 669: } // switch Inst[13]
409 // 669: }
410 14, 19, // 673: case 0xe: {
411 OPC_SwitchField, 13, 1, // 675: switch Inst[13] {
412 0, 8, // 678: case 0x0: {
413 OPC_CheckField, 5, 8, 0, // 680: check Inst[12:5] == 0x0
414 OPC_Decode, 214, 6, 11, // 684: decode to UDIVrr using decoder 11
415 // 684: }
416 1, 0, // 688: case 0x1: {
417 OPC_Decode, 213, 6, 12, // 690: decode to UDIVri using decoder 12
418 // 690: }
419 // 690: } // switch Inst[13]
420 // 690: }
421 15, 19, // 694: case 0xf: {
422 OPC_SwitchField, 13, 1, // 696: switch Inst[13] {
423 0, 8, // 699: case 0x0: {
424 OPC_CheckField, 5, 8, 0, // 701: check Inst[12:5] == 0x0
425 OPC_Decode, 229, 5, 11, // 705: decode to SDIVrr using decoder 11
426 // 705: }
427 1, 0, // 709: case 0x1: {
428 OPC_Decode, 228, 5, 12, // 711: decode to SDIVri using decoder 12
429 // 711: }
430 // 711: } // switch Inst[13]
431 // 711: }
432 16, 19, // 715: case 0x10: {
433 OPC_SwitchField, 13, 1, // 717: switch Inst[13] {
434 0, 8, // 720: case 0x0: {
435 OPC_CheckField, 5, 8, 0, // 722: check Inst[12:5] == 0x0
436 OPC_Decode, 223, 2, 11, // 726: decode to ADDCCrr using decoder 11
437 // 726: }
438 1, 0, // 730: case 0x1: {
439 OPC_Decode, 222, 2, 12, // 732: decode to ADDCCri using decoder 12
440 // 732: }
441 // 732: } // switch Inst[13]
442 // 732: }
443 17, 19, // 736: case 0x11: {
444 OPC_SwitchField, 13, 1, // 738: switch Inst[13] {
445 0, 8, // 741: case 0x0: {
446 OPC_CheckField, 5, 8, 0, // 743: check Inst[12:5] == 0x0
447 OPC_Decode, 247, 2, 11, // 747: decode to ANDCCrr using decoder 11
448 // 747: }
449 1, 0, // 751: case 0x1: {
450 OPC_Decode, 246, 2, 12, // 753: decode to ANDCCri using decoder 12
451 // 753: }
452 // 753: } // switch Inst[13]
453 // 753: }
454 18, 19, // 757: case 0x12: {
455 OPC_SwitchField, 13, 1, // 759: switch Inst[13] {
456 0, 8, // 762: case 0x0: {
457 OPC_CheckField, 5, 8, 0, // 764: check Inst[12:5] == 0x0
458 OPC_Decode, 190, 5, 11, // 768: decode to ORCCrr using decoder 11
459 // 768: }
460 1, 0, // 772: case 0x1: {
461 OPC_Decode, 189, 5, 12, // 774: decode to ORCCri using decoder 12
462 // 774: }
463 // 774: } // switch Inst[13]
464 // 774: }
465 19, 19, // 778: case 0x13: {
466 OPC_SwitchField, 13, 1, // 780: switch Inst[13] {
467 0, 8, // 783: case 0x0: {
468 OPC_CheckField, 5, 8, 0, // 785: check Inst[12:5] == 0x0
469 OPC_Decode, 251, 6, 11, // 789: decode to XORCCrr using decoder 11
470 // 789: }
471 1, 0, // 793: case 0x1: {
472 OPC_Decode, 250, 6, 12, // 795: decode to XORCCri using decoder 12
473 // 795: }
474 // 795: } // switch Inst[13]
475 // 795: }
476 20, 19, // 799: case 0x14: {
477 OPC_SwitchField, 13, 1, // 801: switch Inst[13] {
478 0, 8, // 804: case 0x0: {
479 OPC_CheckField, 5, 8, 0, // 806: check Inst[12:5] == 0x0
480 OPC_Decode, 175, 6, 11, // 810: decode to SUBCCrr using decoder 11
481 // 810: }
482 1, 0, // 814: case 0x1: {
483 OPC_Decode, 174, 6, 12, // 816: decode to SUBCCri using decoder 12
484 // 816: }
485 // 816: } // switch Inst[13]
486 // 816: }
487 21, 19, // 820: case 0x15: {
488 OPC_SwitchField, 13, 1, // 822: switch Inst[13] {
489 0, 8, // 825: case 0x0: {
490 OPC_CheckField, 5, 8, 0, // 827: check Inst[12:5] == 0x0
491 OPC_Decode, 249, 2, 11, // 831: decode to ANDNCCrr using decoder 11
492 // 831: }
493 1, 0, // 835: case 0x1: {
494 OPC_Decode, 248, 2, 12, // 837: decode to ANDNCCri using decoder 12
495 // 837: }
496 // 837: } // switch Inst[13]
497 // 837: }
498 22, 19, // 841: case 0x16: {
499 OPC_SwitchField, 13, 1, // 843: switch Inst[13] {
500 0, 8, // 846: case 0x0: {
501 OPC_CheckField, 5, 8, 0, // 848: check Inst[12:5] == 0x0
502 OPC_Decode, 192, 5, 11, // 852: decode to ORNCCrr using decoder 11
503 // 852: }
504 1, 0, // 856: case 0x1: {
505 OPC_Decode, 191, 5, 12, // 858: decode to ORNCCri using decoder 12
506 // 858: }
507 // 858: } // switch Inst[13]
508 // 858: }
509 23, 19, // 862: case 0x17: {
510 OPC_SwitchField, 13, 1, // 864: switch Inst[13] {
511 0, 8, // 867: case 0x0: {
512 OPC_CheckField, 5, 8, 0, // 869: check Inst[12:5] == 0x0
513 OPC_Decode, 247, 6, 11, // 873: decode to XNORCCrr using decoder 11
514 // 873: }
515 1, 0, // 877: case 0x1: {
516 OPC_Decode, 246, 6, 12, // 879: decode to XNORCCri using decoder 12
517 // 879: }
518 // 879: } // switch Inst[13]
519 // 879: }
520 24, 19, // 883: case 0x18: {
521 OPC_SwitchField, 13, 1, // 885: switch Inst[13] {
522 0, 8, // 888: case 0x0: {
523 OPC_CheckField, 5, 8, 0, // 890: check Inst[12:5] == 0x0
524 OPC_Decode, 227, 2, 11, // 894: decode to ADDErr using decoder 11
525 // 894: }
526 1, 0, // 898: case 0x1: {
527 OPC_Decode, 226, 2, 12, // 900: decode to ADDEri using decoder 12
528 // 900: }
529 // 900: } // switch Inst[13]
530 // 900: }
531 25, 91, // 904: case 0x19: {
532 OPC_SwitchField, 5, 4, // 906: switch Inst[8:5] {
533 0, 6, // 909: case 0x0: {
534 OPC_CheckPredicate, 3, // 911: check predicate 3
535 OPC_Decode, 236, 2, 15, // 913: decode to AES_EROUND01 using decoder 15
536 // 913: }
537 1, 6, // 917: case 0x1: {
538 OPC_CheckPredicate, 3, // 919: check predicate 3
539 OPC_Decode, 238, 2, 15, // 921: decode to AES_EROUND23 using decoder 15
540 // 921: }
541 2, 6, // 925: case 0x2: {
542 OPC_CheckPredicate, 3, // 927: check predicate 3
543 OPC_Decode, 232, 2, 15, // 929: decode to AES_DROUND01 using decoder 15
544 // 929: }
545 3, 6, // 933: case 0x3: {
546 OPC_CheckPredicate, 3, // 935: check predicate 3
547 OPC_Decode, 234, 2, 15, // 937: decode to AES_DROUND23 using decoder 15
548 // 937: }
549 4, 6, // 941: case 0x4: {
550 OPC_CheckPredicate, 3, // 943: check predicate 3
551 OPC_Decode, 237, 2, 15, // 945: decode to AES_EROUND01_LAST using decoder 15
552 // 945: }
553 5, 6, // 949: case 0x5: {
554 OPC_CheckPredicate, 3, // 951: check predicate 3
555 OPC_Decode, 239, 2, 15, // 953: decode to AES_EROUND23_LAST using decoder 15
556 // 953: }
557 6, 6, // 957: case 0x6: {
558 OPC_CheckPredicate, 3, // 959: check predicate 3
559 OPC_Decode, 233, 2, 15, // 961: decode to AES_DROUND01_LAST using decoder 15
560 // 961: }
561 7, 6, // 965: case 0x7: {
562 OPC_CheckPredicate, 3, // 967: check predicate 3
563 OPC_Decode, 235, 2, 15, // 969: decode to AES_DROUND23_LAST using decoder 15
564 // 969: }
565 8, 6, // 973: case 0x8: {
566 OPC_CheckPredicate, 3, // 975: check predicate 3
567 OPC_Decode, 241, 2, 16, // 977: decode to AES_KEXPAND1 using decoder 16
568 // 977: }
569 9, 6, // 981: case 0x9: {
570 OPC_CheckPredicate, 3, // 983: check predicate 3
571 OPC_Decode, 178, 3, 15, // 985: decode to DES_ROUND using decoder 15
572 // 985: }
573 12, 0, // 989: case 0xc: {
574 OPC_CheckPredicate, 3, // 991: check predicate 3
575 OPC_Decode, 158, 3, 15, // 993: decode to CAMELLIA_F using decoder 15
576 // 993: }
577 // 993: } // switch Inst[8:5]
578 // 993: }
579 26, 19, // 997: case 0x1a: {
580 OPC_SwitchField, 13, 1, // 999: switch Inst[13] {
581 0, 8, // 1002: case 0x0: {
582 OPC_CheckField, 5, 8, 0, // 1004: check Inst[12:5] == 0x0
583 OPC_Decode, 218, 6, 11, // 1008: decode to UMULCCrr using decoder 11
584 // 1008: }
585 1, 0, // 1012: case 0x1: {
586 OPC_Decode, 217, 6, 12, // 1014: decode to UMULCCri using decoder 12
587 // 1014: }
588 // 1014: } // switch Inst[13]
589 // 1014: }
590 27, 19, // 1018: case 0x1b: {
591 OPC_SwitchField, 13, 1, // 1020: switch Inst[13] {
592 0, 8, // 1023: case 0x0: {
593 OPC_CheckField, 5, 8, 0, // 1025: check Inst[12:5] == 0x0
594 OPC_Decode, 244, 5, 11, // 1029: decode to SMULCCrr using decoder 11
595 // 1029: }
596 1, 0, // 1033: case 0x1: {
597 OPC_Decode, 243, 5, 12, // 1035: decode to SMULCCri using decoder 12
598 // 1035: }
599 // 1035: } // switch Inst[13]
600 // 1035: }
601 28, 19, // 1039: case 0x1c: {
602 OPC_SwitchField, 13, 1, // 1041: switch Inst[13] {
603 0, 8, // 1044: case 0x0: {
604 OPC_CheckField, 5, 8, 0, // 1046: check Inst[12:5] == 0x0
605 OPC_Decode, 179, 6, 11, // 1050: decode to SUBErr using decoder 11
606 // 1050: }
607 1, 0, // 1054: case 0x1: {
608 OPC_Decode, 178, 6, 12, // 1056: decode to SUBEri using decoder 12
609 // 1056: }
610 // 1056: } // switch Inst[13]
611 // 1056: }
612 30, 19, // 1060: case 0x1e: {
613 OPC_SwitchField, 13, 1, // 1062: switch Inst[13] {
614 0, 8, // 1065: case 0x0: {
615 OPC_CheckField, 5, 8, 0, // 1067: check Inst[12:5] == 0x0
616 OPC_Decode, 210, 6, 11, // 1071: decode to UDIVCCrr using decoder 11
617 // 1071: }
618 1, 0, // 1075: case 0x1: {
619 OPC_Decode, 209, 6, 12, // 1077: decode to UDIVCCri using decoder 12
620 // 1077: }
621 // 1077: } // switch Inst[13]
622 // 1077: }
623 31, 19, // 1081: case 0x1f: {
624 OPC_SwitchField, 13, 1, // 1083: switch Inst[13] {
625 0, 8, // 1086: case 0x0: {
626 OPC_CheckField, 5, 8, 0, // 1088: check Inst[12:5] == 0x0
627 OPC_Decode, 225, 5, 11, // 1092: decode to SDIVCCrr using decoder 11
628 // 1092: }
629 1, 0, // 1096: case 0x1: {
630 OPC_Decode, 224, 5, 12, // 1098: decode to SDIVCCri using decoder 12
631 // 1098: }
632 // 1098: } // switch Inst[13]
633 // 1098: }
634 32, 19, // 1102: case 0x20: {
635 OPC_SwitchField, 13, 1, // 1104: switch Inst[13] {
636 0, 8, // 1107: case 0x0: {
637 OPC_CheckField, 5, 8, 0, // 1109: check Inst[12:5] == 0x0
638 OPC_Decode, 192, 6, 11, // 1113: decode to TADDCCrr using decoder 11
639 // 1113: }
640 1, 0, // 1117: case 0x1: {
641 OPC_Decode, 191, 6, 12, // 1119: decode to TADDCCri using decoder 12
642 // 1119: }
643 // 1119: } // switch Inst[13]
644 // 1119: }
645 33, 19, // 1123: case 0x21: {
646 OPC_SwitchField, 13, 1, // 1125: switch Inst[13] {
647 0, 8, // 1128: case 0x0: {
648 OPC_CheckField, 5, 8, 0, // 1130: check Inst[12:5] == 0x0
649 OPC_Decode, 206, 6, 11, // 1134: decode to TSUBCCrr using decoder 11
650 // 1134: }
651 1, 0, // 1138: case 0x1: {
652 OPC_Decode, 205, 6, 12, // 1140: decode to TSUBCCri using decoder 12
653 // 1140: }
654 // 1140: } // switch Inst[13]
655 // 1140: }
656 34, 19, // 1144: case 0x22: {
657 OPC_SwitchField, 13, 1, // 1146: switch Inst[13] {
658 0, 8, // 1149: case 0x0: {
659 OPC_CheckField, 5, 8, 0, // 1151: check Inst[12:5] == 0x0
660 OPC_Decode, 190, 6, 11, // 1155: decode to TADDCCTVrr using decoder 11
661 // 1155: }
662 1, 0, // 1159: case 0x1: {
663 OPC_Decode, 189, 6, 12, // 1161: decode to TADDCCTVri using decoder 12
664 // 1161: }
665 // 1161: } // switch Inst[13]
666 // 1161: }
667 35, 19, // 1165: case 0x23: {
668 OPC_SwitchField, 13, 1, // 1167: switch Inst[13] {
669 0, 8, // 1170: case 0x0: {
670 OPC_CheckField, 5, 8, 0, // 1172: check Inst[12:5] == 0x0
671 OPC_Decode, 204, 6, 11, // 1176: decode to TSUBCCTVrr using decoder 11
672 // 1176: }
673 1, 0, // 1180: case 0x1: {
674 OPC_Decode, 203, 6, 12, // 1182: decode to TSUBCCTVri using decoder 12
675 // 1182: }
676 // 1182: } // switch Inst[13]
677 // 1182: }
678 36, 19, // 1186: case 0x24: {
679 OPC_SwitchField, 13, 1, // 1188: switch Inst[13] {
680 0, 8, // 1191: case 0x0: {
681 OPC_CheckField, 5, 8, 0, // 1193: check Inst[12:5] == 0x0
682 OPC_Decode, 184, 5, 11, // 1197: decode to MULSCCrr using decoder 11
683 // 1197: }
684 1, 0, // 1201: case 0x1: {
685 OPC_Decode, 183, 5, 12, // 1203: decode to MULSCCri using decoder 12
686 // 1203: }
687 // 1203: } // switch Inst[13]
688 // 1203: }
689 37, 31, // 1207: case 0x25: {
690 OPC_SwitchField, 12, 2, // 1209: switch Inst[13:12] {
691 0, 4, // 1212: case 0x0: {
692 OPC_Decode, 240, 5, 11, // 1214: decode to SLLrr using decoder 11
693 // 1214: }
694 1, 6, // 1218: case 0x1: {
695 OPC_CheckPredicate, 0, // 1220: check predicate 0
696 OPC_Decode, 238, 5, 17, // 1222: decode to SLLXrr using decoder 17
697 // 1222: }
698 2, 4, // 1226: case 0x2: {
699 OPC_Decode, 239, 5, 18, // 1228: decode to SLLri using decoder 18
700 // 1228: }
701 3, 0, // 1232: case 0x3: {
702 OPC_CheckPredicate, 0, // 1234: check predicate 0
703 OPC_Decode, 237, 5, 19, // 1236: decode to SLLXri using decoder 19
704 // 1236: }
705 // 1236: } // switch Inst[13:12]
706 // 1236: }
707 38, 31, // 1240: case 0x26: {
708 OPC_SwitchField, 12, 2, // 1242: switch Inst[13:12] {
709 0, 4, // 1245: case 0x0: {
710 OPC_Decode, 254, 5, 11, // 1247: decode to SRLrr using decoder 11
711 // 1247: }
712 1, 6, // 1251: case 0x1: {
713 OPC_CheckPredicate, 0, // 1253: check predicate 0
714 OPC_Decode, 252, 5, 17, // 1255: decode to SRLXrr using decoder 17
715 // 1255: }
716 2, 4, // 1259: case 0x2: {
717 OPC_Decode, 253, 5, 18, // 1261: decode to SRLri using decoder 18
718 // 1261: }
719 3, 0, // 1265: case 0x3: {
720 OPC_CheckPredicate, 0, // 1267: check predicate 0
721 OPC_Decode, 251, 5, 19, // 1269: decode to SRLXri using decoder 19
722 // 1269: }
723 // 1269: } // switch Inst[13:12]
724 // 1269: }
725 39, 31, // 1273: case 0x27: {
726 OPC_SwitchField, 12, 2, // 1275: switch Inst[13:12] {
727 0, 4, // 1278: case 0x0: {
728 OPC_Decode, 250, 5, 11, // 1280: decode to SRArr using decoder 11
729 // 1280: }
730 1, 6, // 1284: case 0x1: {
731 OPC_CheckPredicate, 0, // 1286: check predicate 0
732 OPC_Decode, 248, 5, 17, // 1288: decode to SRAXrr using decoder 17
733 // 1288: }
734 2, 4, // 1292: case 0x2: {
735 OPC_Decode, 249, 5, 18, // 1294: decode to SRAri using decoder 18
736 // 1294: }
737 3, 0, // 1298: case 0x3: {
738 OPC_CheckPredicate, 0, // 1300: check predicate 0
739 OPC_Decode, 247, 5, 19, // 1302: decode to SRAXri using decoder 19
740 // 1302: }
741 // 1302: } // switch Inst[13:12]
742 // 1302: }
743 40, 43, // 1306: case 0x28: {
744 OPC_SwitchField, 13, 1, // 1308: switch Inst[13] {
745 0, 22, // 1311: case 0x0: {
746 OPC_CheckField, 0, 13, 0, // 1313: check Inst[12:0] == 0x0
747 OPC_Scope, 12, // 1317: try {
748 OPC_CheckField, 14, 5, 15, // 1319: check Inst[18:14] == 0xf
749 OPC_CheckField, 25, 5, 0, // 1323: check Inst[29:25] == 0x0
750 OPC_Decode, 129, 6, 7, // 1327: decode to STBAR using decoder 7
751 // 1327: } else try {
752 OPC_Decode, 207, 5, 20, // 1331: decode to RDASR using decoder 20
753 // 1331: }
754 // 1331: }
755 1, 0, // 1335: case 0x1: {
756 OPC_CheckPredicate, 0, // 1337: check predicate 0
757 OPC_CheckField, 25, 5, 0, // 1339: check Inst[29:25] == 0x0
758 OPC_CheckField, 14, 5, 15, // 1343: check Inst[18:14] == 0xf
759 OPC_Decode, 166, 5, 21, // 1347: decode to MEMBARi using decoder 21
760 // 1347: }
761 // 1347: } // switch Inst[13]
762 // 1347: }
763 41, 8, // 1351: case 0x29: {
764 OPC_CheckField, 0, 19, 0, // 1353: check Inst[18:0] == 0x0
765 OPC_Decode, 210, 5, 22, // 1357: decode to RDPSR using decoder 22
766 // 1357: }
767 42, 29, // 1361: case 0x2a: {
768 OPC_CheckField, 0, 14, 0, // 1363: check Inst[13:0] == 0x0
769 OPC_Scope, 17, // 1367: try {
770 OPC_SwitchField, 14, 5, // 1369: switch Inst[18:14] {
771 0, 4, // 1372: case 0x0: {
772 OPC_Decode, 212, 5, 22, // 1374: decode to RDWIM using decoder 22
773 // 1374: }
774 15, 0, // 1378: case 0xf: {
775 OPC_CheckPredicate, 0, // 1380: check predicate 0
776 OPC_Decode, 208, 5, 22, // 1382: decode to RDFQ using decoder 22
777 // 1382: }
778 // 1382: } // switch Inst[18:14]
779 // 1382: } else try {
780 OPC_CheckPredicate, 0, // 1386: check predicate 0
781 OPC_Decode, 209, 5, 23, // 1388: decode to RDPR using decoder 23
782 // 1388: }
783 // 1388: }
784 43, 20, // 1392: case 0x2b: {
785 OPC_CheckField, 0, 19, 0, // 1394: check Inst[18:0] == 0x0
786 OPC_Scope, 10, // 1398: try {
787 OPC_CheckField, 25, 5, 0, // 1400: check Inst[29:25] == 0x0
788 OPC_CheckPredicate, 0, // 1404: check predicate 0
789 OPC_Decode, 243, 3, 7, // 1406: decode to FLUSHW using decoder 7
790 // 1406: } else try {
791 OPC_Decode, 211, 5, 22, // 1410: decode to RDTBR using decoder 22
792 // 1410: }
793 // 1410: }
794 44, 95, // 1414: case 0x2c: {
795 OPC_SwitchField, 13, 1, // 1416: switch Inst[13] {
796 0, 44, // 1419: case 0x0: {
797 OPC_SwitchField, 18, 1, // 1421: switch Inst[18] {
798 0, 18, // 1424: case 0x0: {
799 OPC_Scope, 10, // 1426: try {
800 OPC_CheckField, 11, 2, 0, // 1428: check Inst[12:11] == 0x0
801 OPC_CheckPredicate, 0, // 1432: check predicate 0
802 OPC_Decode, 171, 5, 24, // 1434: decode to MOVFCCrr using decoder 24
803 // 1434: } else try {
804 OPC_CheckPredicate, 0, // 1438: check predicate 0
805 OPC_Decode, 233, 6, 25, // 1440: decode to V9MOVFCCrr using decoder 25
806 // 1440: }
807 // 1440: }
808 1, 0, // 1444: case 0x1: {
809 OPC_SwitchField, 11, 2, // 1446: switch Inst[12:11] {
810 0, 6, // 1449: case 0x0: {
811 OPC_CheckPredicate, 0, // 1451: check predicate 0
812 OPC_Decode, 173, 5, 24, // 1453: decode to MOVICCrr using decoder 24
813 // 1453: }
814 2, 0, // 1457: case 0x2: {
815 OPC_CheckPredicate, 1, // 1459: check predicate 1
816 OPC_Decode, 180, 5, 24, // 1461: decode to MOVXCCrr using decoder 24
817 // 1461: }
818 // 1461: } // switch Inst[12:11]
819 // 1461: }
820 // 1461: } // switch Inst[18]
821 // 1461: }
822 1, 0, // 1465: case 0x1: {
823 OPC_SwitchField, 18, 1, // 1467: switch Inst[18] {
824 0, 18, // 1470: case 0x0: {
825 OPC_Scope, 10, // 1472: try {
826 OPC_CheckField, 11, 2, 0, // 1474: check Inst[12:11] == 0x0
827 OPC_CheckPredicate, 0, // 1478: check predicate 0
828 OPC_Decode, 170, 5, 26, // 1480: decode to MOVFCCri using decoder 26
829 // 1480: } else try {
830 OPC_CheckPredicate, 0, // 1484: check predicate 0
831 OPC_Decode, 232, 6, 27, // 1486: decode to V9MOVFCCri using decoder 27
832 // 1486: }
833 // 1486: }
834 1, 0, // 1490: case 0x1: {
835 OPC_SwitchField, 11, 2, // 1492: switch Inst[12:11] {
836 0, 6, // 1495: case 0x0: {
837 OPC_CheckPredicate, 0, // 1497: check predicate 0
838 OPC_Decode, 172, 5, 26, // 1499: decode to MOVICCri using decoder 26
839 // 1499: }
840 2, 0, // 1503: case 0x2: {
841 OPC_CheckPredicate, 1, // 1505: check predicate 1
842 OPC_Decode, 179, 5, 26, // 1507: decode to MOVXCCri using decoder 26
843 // 1507: }
844 // 1507: } // switch Inst[12:11]
845 // 1507: }
846 // 1507: } // switch Inst[18]
847 // 1507: }
848 // 1507: } // switch Inst[13]
849 // 1507: }
850 45, 23, // 1511: case 0x2d: {
851 OPC_SwitchField, 13, 1, // 1513: switch Inst[13] {
852 0, 10, // 1516: case 0x0: {
853 OPC_CheckPredicate, 0, // 1518: check predicate 0
854 OPC_CheckField, 5, 8, 0, // 1520: check Inst[12:5] == 0x0
855 OPC_Decode, 227, 5, 13, // 1524: decode to SDIVXrr using decoder 13
856 // 1524: }
857 1, 0, // 1528: case 0x1: {
858 OPC_CheckPredicate, 0, // 1530: check predicate 0
859 OPC_Decode, 226, 5, 14, // 1532: decode to SDIVXri using decoder 14
860 // 1532: }
861 // 1532: } // switch Inst[13]
862 // 1532: }
863 46, 10, // 1536: case 0x2e: {
864 OPC_CheckPredicate, 0, // 1538: check predicate 0
865 OPC_CheckField, 5, 14, 0, // 1540: check Inst[18:5] == 0x0
866 OPC_Decode, 200, 5, 28, // 1544: decode to POPCrr using decoder 28
867 // 1544: }
868 47, 23, // 1548: case 0x2f: {
869 OPC_SwitchField, 13, 1, // 1550: switch Inst[13] {
870 0, 10, // 1553: case 0x0: {
871 OPC_CheckPredicate, 0, // 1555: check predicate 0
872 OPC_CheckField, 5, 5, 0, // 1557: check Inst[9:5] == 0x0
873 OPC_Decode, 175, 5, 29, // 1561: decode to MOVRrr using decoder 29
874 // 1561: }
875 1, 0, // 1565: case 0x1: {
876 OPC_CheckPredicate, 0, // 1567: check predicate 0
877 OPC_Decode, 174, 5, 30, // 1569: decode to MOVRri using decoder 30
878 // 1569: }
879 // 1569: } // switch Inst[13]
880 // 1569: }
881 48, 35, // 1573: case 0x30: {
882 OPC_SwitchField, 13, 1, // 1575: switch Inst[13] {
883 0, 8, // 1578: case 0x0: {
884 OPC_CheckField, 5, 8, 0, // 1580: check Inst[12:5] == 0x0
885 OPC_Decode, 235, 6, 31, // 1584: decode to WRASRrr using decoder 31
886 // 1584: }
887 1, 0, // 1588: case 0x1: {
888 OPC_Scope, 14, // 1590: try {
889 OPC_CheckField, 14, 5, 0, // 1592: check Inst[18:14] == 0x0
890 OPC_CheckPredicate, 0, // 1596: check predicate 0
891 OPC_CheckField, 25, 5, 15, // 1598: check Inst[29:25] == 0xf
892 OPC_Decode, 236, 5, 32, // 1602: decode to SIR using decoder 32
893 // 1602: } else try {
894 OPC_Decode, 234, 6, 33, // 1606: decode to WRASRri using decoder 33
895 // 1606: }
896 // 1606: }
897 // 1606: } // switch Inst[13]
898 // 1606: }
899 49, 129, 1, // 1610: case 0x31: {
900 OPC_SwitchField, 25, 5, // 1613: switch Inst[29:25] {
901 0, 35, // 1616: case 0x0: {
902 OPC_SwitchField, 13, 1, // 1618: switch Inst[13] {
903 0, 24, // 1621: case 0x0: {
904 OPC_CheckField, 5, 8, 0, // 1623: check Inst[12:5] == 0x0
905 OPC_Scope, 14, // 1627: try {
906 OPC_CheckField, 0, 5, 0, // 1629: check Inst[4:0] == 0x0
907 OPC_CheckPredicate, 0, // 1633: check predicate 0
908 OPC_CheckField, 14, 5, 0, // 1635: check Inst[18:14] == 0x0
909 OPC_Decode, 221, 5, 7, // 1639: decode to SAVED using decoder 7
910 // 1639: } else try {
911 OPC_Decode, 239, 6, 34, // 1643: decode to WRPSRrr using decoder 34
912 // 1643: }
913 // 1643: }
914 1, 0, // 1647: case 0x1: {
915 OPC_Decode, 238, 6, 35, // 1649: decode to WRPSRri using decoder 35
916 // 1649: }
917 // 1649: } // switch Inst[13]
918 // 1649: }
919 1, 39, // 1653: case 0x1: {
920 OPC_SwitchField, 13, 1, // 1655: switch Inst[13] {
921 0, 26, // 1658: case 0x0: {
922 OPC_CheckField, 5, 8, 0, // 1660: check Inst[12:5] == 0x0
923 OPC_Scope, 14, // 1664: try {
924 OPC_CheckField, 0, 5, 0, // 1666: check Inst[4:0] == 0x0
925 OPC_CheckPredicate, 0, // 1670: check predicate 0
926 OPC_CheckField, 14, 5, 0, // 1672: check Inst[18:14] == 0x0
927 OPC_Decode, 213, 5, 7, // 1676: decode to RESTORED using decoder 7
928 // 1676: } else try {
929 OPC_CheckPredicate, 4, // 1680: check predicate 4
930 OPC_Decode, 206, 5, 34, // 1682: decode to PWRPSRrr using decoder 34
931 // 1682: }
932 // 1682: }
933 1, 0, // 1686: case 0x1: {
934 OPC_CheckPredicate, 4, // 1688: check predicate 4
935 OPC_Decode, 205, 5, 35, // 1690: decode to PWRPSRri using decoder 35
936 // 1690: }
937 // 1690: } // switch Inst[13]
938 // 1690: }
939 2, 10, // 1694: case 0x2: {
940 OPC_CheckPredicate, 5, // 1696: check predicate 5
941 OPC_CheckField, 0, 19, 0, // 1698: check Inst[18:0] == 0x0
942 OPC_Decode, 245, 2, 7, // 1702: decode to ALLCLEAN using decoder 7
943 // 1702: }
944 3, 10, // 1706: case 0x3: {
945 OPC_CheckPredicate, 5, // 1708: check predicate 5
946 OPC_CheckField, 0, 19, 0, // 1710: check Inst[18:0] == 0x0
947 OPC_Decode, 197, 5, 7, // 1714: decode to OTHERW using decoder 7
948 // 1714: }
949 4, 10, // 1718: case 0x4: {
950 OPC_CheckPredicate, 5, // 1720: check predicate 5
951 OPC_CheckField, 0, 19, 0, // 1722: check Inst[18:0] == 0x0
952 OPC_Decode, 188, 5, 7, // 1726: decode to NORMALW using decoder 7
953 // 1726: }
954 5, 0, // 1730: case 0x5: {
955 OPC_CheckPredicate, 5, // 1732: check predicate 5
956 OPC_CheckField, 0, 19, 0, // 1734: check Inst[18:0] == 0x0
957 OPC_Decode, 231, 4, 7, // 1738: decode to INVALW using decoder 7
958 // 1738: }
959 // 1738: } // switch Inst[29:25]
960 // 1738: }
961 50, 43, // 1742: case 0x32: {
962 OPC_SwitchField, 13, 1, // 1744: switch Inst[13] {
963 0, 20, // 1747: case 0x0: {
964 OPC_CheckField, 5, 8, 0, // 1749: check Inst[12:5] == 0x0
965 OPC_Scope, 8, // 1753: try {
966 OPC_CheckField, 25, 5, 0, // 1755: check Inst[29:25] == 0x0
967 OPC_Decode, 243, 6, 34, // 1759: decode to WRWIMrr using decoder 34
968 // 1759: } else try {
969 OPC_CheckPredicate, 0, // 1763: check predicate 0
970 OPC_Decode, 237, 6, 36, // 1765: decode to WRPRrr using decoder 36
971 // 1765: }
972 // 1765: }
973 1, 0, // 1769: case 0x1: {
974 OPC_Scope, 8, // 1771: try {
975 OPC_CheckField, 25, 5, 0, // 1773: check Inst[29:25] == 0x0
976 OPC_Decode, 242, 6, 35, // 1777: decode to WRWIMri using decoder 35
977 // 1777: } else try {
978 OPC_CheckPredicate, 0, // 1781: check predicate 0
979 OPC_Decode, 236, 6, 37, // 1783: decode to WRPRri using decoder 37
980 // 1783: }
981 // 1783: }
982 // 1783: } // switch Inst[13]
983 // 1783: }
984 51, 27, // 1787: case 0x33: {
985 OPC_SwitchField, 13, 1, // 1789: switch Inst[13] {
986 0, 12, // 1792: case 0x0: {
987 OPC_CheckField, 25, 5, 0, // 1794: check Inst[29:25] == 0x0
988 OPC_CheckField, 5, 8, 0, // 1798: check Inst[12:5] == 0x0
989 OPC_Decode, 241, 6, 34, // 1802: decode to WRTBRrr using decoder 34
990 // 1802: }
991 1, 0, // 1806: case 0x1: {
992 OPC_CheckField, 25, 5, 0, // 1808: check Inst[29:25] == 0x0
993 OPC_Decode, 240, 6, 35, // 1812: decode to WRTBRri using decoder 35
994 // 1812: }
995 // 1812: } // switch Inst[13]
996 // 1812: }
997 52, 133, 4, // 1816: case 0x34: {
998 OPC_SwitchField, 5, 9, // 1819: switch Inst[13:5] {
999 1, 8, // 1822: case 0x1: {
1000 OPC_CheckField, 14, 5, 0, // 1824: check Inst[18:14] == 0x0
1001 OPC_Decode, 132, 4, 38, // 1828: decode to FMOVS using decoder 38
1002 // 1828: }
1003 2, 10, // 1832: case 0x2: {
1004 OPC_CheckPredicate, 0, // 1834: check predicate 0
1005 OPC_CheckField, 14, 5, 0, // 1836: check Inst[18:14] == 0x0
1006 OPC_Decode, 249, 3, 39, // 1840: decode to FMOVD using decoder 39
1007 // 1840: }
1008 3, 10, // 1844: case 0x3: {
1009 OPC_CheckPredicate, 0, // 1846: check predicate 0
1010 OPC_CheckField, 14, 5, 0, // 1848: check Inst[18:14] == 0x0
1011 OPC_Decode, 253, 3, 40, // 1852: decode to FMOVQ using decoder 40
1012 // 1852: }
1013 5, 8, // 1856: case 0x5: {
1014 OPC_CheckField, 14, 5, 0, // 1858: check Inst[18:14] == 0x0
1015 OPC_Decode, 154, 4, 38, // 1862: decode to FNEGS using decoder 38
1016 // 1862: }
1017 6, 10, // 1866: case 0x6: {
1018 OPC_CheckPredicate, 0, // 1868: check predicate 0
1019 OPC_CheckField, 14, 5, 0, // 1870: check Inst[18:14] == 0x0
1020 OPC_Decode, 152, 4, 39, // 1874: decode to FNEGD using decoder 39
1021 // 1874: }
1022 7, 10, // 1878: case 0x7: {
1023 OPC_CheckPredicate, 0, // 1880: check predicate 0
1024 OPC_CheckField, 14, 5, 0, // 1882: check Inst[18:14] == 0x0
1025 OPC_Decode, 153, 4, 40, // 1886: decode to FNEGQ using decoder 40
1026 // 1886: }
1027 9, 8, // 1890: case 0x9: {
1028 OPC_CheckField, 14, 5, 0, // 1892: check Inst[18:14] == 0x0
1029 OPC_Decode, 194, 3, 38, // 1896: decode to FABSS using decoder 38
1030 // 1896: }
1031 10, 10, // 1900: case 0xa: {
1032 OPC_CheckPredicate, 0, // 1902: check predicate 0
1033 OPC_CheckField, 14, 5, 0, // 1904: check Inst[18:14] == 0x0
1034 OPC_Decode, 192, 3, 39, // 1908: decode to FABSD using decoder 39
1035 // 1908: }
1036 11, 10, // 1912: case 0xb: {
1037 OPC_CheckPredicate, 0, // 1914: check predicate 0
1038 OPC_CheckField, 14, 5, 0, // 1916: check Inst[18:14] == 0x0
1039 OPC_Decode, 193, 3, 40, // 1920: decode to FABSQ using decoder 40
1040 // 1920: }
1041 41, 8, // 1924: case 0x29: {
1042 OPC_CheckField, 14, 5, 0, // 1926: check Inst[18:14] == 0x0
1043 OPC_Decode, 204, 4, 38, // 1930: decode to FSQRTS using decoder 38
1044 // 1930: }
1045 42, 8, // 1934: case 0x2a: {
1046 OPC_CheckField, 14, 5, 0, // 1936: check Inst[18:14] == 0x0
1047 OPC_Decode, 202, 4, 39, // 1940: decode to FSQRTD using decoder 39
1048 // 1940: }
1049 43, 8, // 1944: case 0x2b: {
1050 OPC_CheckField, 14, 5, 0, // 1946: check Inst[18:14] == 0x0
1051 OPC_Decode, 203, 4, 40, // 1950: decode to FSQRTQ using decoder 40
1052 // 1950: }
1053 65, 4, // 1954: case 0x41: {
1054 OPC_Decode, 197, 3, 41, // 1956: decode to FADDS using decoder 41
1055 // 1956: }
1056 66, 4, // 1960: case 0x42: {
1057 OPC_Decode, 195, 3, 42, // 1962: decode to FADDD using decoder 42
1058 // 1962: }
1059 67, 4, // 1966: case 0x43: {
1060 OPC_Decode, 196, 3, 43, // 1968: decode to FADDQ using decoder 43
1061 // 1968: }
1062 69, 4, // 1972: case 0x45: {
1063 OPC_Decode, 219, 4, 41, // 1974: decode to FSUBS using decoder 41
1064 // 1974: }
1065 70, 4, // 1978: case 0x46: {
1066 OPC_Decode, 217, 4, 42, // 1980: decode to FSUBD using decoder 42
1067 // 1980: }
1068 71, 4, // 1984: case 0x47: {
1069 OPC_Decode, 218, 4, 43, // 1986: decode to FSUBQ using decoder 43
1070 // 1986: }
1071 73, 4, // 1990: case 0x49: {
1072 OPC_Decode, 147, 4, 41, // 1992: decode to FMULS using decoder 41
1073 // 1992: }
1074 74, 4, // 1996: case 0x4a: {
1075 OPC_Decode, 143, 4, 42, // 1998: decode to FMULD using decoder 42
1076 // 1998: }
1077 75, 4, // 2002: case 0x4b: {
1078 OPC_Decode, 146, 4, 43, // 2004: decode to FMULQ using decoder 43
1079 // 2004: }
1080 77, 4, // 2008: case 0x4d: {
1081 OPC_Decode, 226, 3, 41, // 2010: decode to FDIVS using decoder 41
1082 // 2010: }
1083 78, 4, // 2014: case 0x4e: {
1084 OPC_Decode, 224, 3, 42, // 2016: decode to FDIVD using decoder 42
1085 // 2016: }
1086 79, 4, // 2020: case 0x4f: {
1087 OPC_Decode, 225, 3, 43, // 2022: decode to FDIVQ using decoder 43
1088 // 2022: }
1089 81, 6, // 2026: case 0x51: {
1090 OPC_CheckPredicate, 6, // 2028: check predicate 6
1091 OPC_Decode, 149, 4, 41, // 2030: decode to FNADDS using decoder 41
1092 // 2030: }
1093 82, 6, // 2034: case 0x52: {
1094 OPC_CheckPredicate, 6, // 2036: check predicate 6
1095 OPC_Decode, 148, 4, 42, // 2038: decode to FNADDD using decoder 42
1096 // 2038: }
1097 89, 6, // 2042: case 0x59: {
1098 OPC_CheckPredicate, 6, // 2044: check predicate 6
1099 OPC_Decode, 162, 4, 41, // 2046: decode to FNMULS using decoder 41
1100 // 2046: }
1101 90, 6, // 2050: case 0x5a: {
1102 OPC_CheckPredicate, 6, // 2052: check predicate 6
1103 OPC_Decode, 161, 4, 42, // 2054: decode to FNMULD using decoder 42
1104 // 2054: }
1105 97, 6, // 2058: case 0x61: {
1106 OPC_CheckPredicate, 6, // 2060: check predicate 6
1107 OPC_Decode, 234, 3, 41, // 2062: decode to FHADDS using decoder 41
1108 // 2062: }
1109 98, 6, // 2066: case 0x62: {
1110 OPC_CheckPredicate, 6, // 2068: check predicate 6
1111 OPC_Decode, 233, 3, 42, // 2070: decode to FHADDD using decoder 42
1112 // 2070: }
1113 101, 6, // 2074: case 0x65: {
1114 OPC_CheckPredicate, 6, // 2076: check predicate 6
1115 OPC_Decode, 236, 3, 41, // 2078: decode to FHSUBS using decoder 41
1116 // 2078: }
1117 102, 6, // 2082: case 0x66: {
1118 OPC_CheckPredicate, 6, // 2084: check predicate 6
1119 OPC_Decode, 235, 3, 42, // 2086: decode to FHSUBD using decoder 42
1120 // 2086: }
1121 105, 4, // 2090: case 0x69: {
1122 OPC_Decode, 201, 4, 44, // 2092: decode to FSMULD using decoder 44
1123 // 2092: }
1124 110, 4, // 2096: case 0x6e: {
1125 OPC_Decode, 227, 3, 45, // 2098: decode to FDMULQ using decoder 45
1126 // 2098: }
1127 113, 6, // 2102: case 0x71: {
1128 OPC_CheckPredicate, 6, // 2104: check predicate 6
1129 OPC_Decode, 156, 4, 41, // 2106: decode to FNHADDS using decoder 41
1130 // 2106: }
1131 114, 6, // 2110: case 0x72: {
1132 OPC_CheckPredicate, 6, // 2112: check predicate 6
1133 OPC_Decode, 155, 4, 42, // 2114: decode to FNHADDD using decoder 42
1134 // 2114: }
1135 121, 6, // 2118: case 0x79: {
1136 OPC_CheckPredicate, 6, // 2120: check predicate 6
1137 OPC_Decode, 169, 4, 44, // 2122: decode to FNSMULD using decoder 44
1138 // 2122: }
1139 129, 1, 10, // 2126: case 0x81: {
1140 OPC_CheckPredicate, 0, // 2129: check predicate 0
1141 OPC_CheckField, 14, 5, 0, // 2131: check Inst[18:14] == 0x0
1142 OPC_Decode, 216, 4, 46, // 2135: decode to FSTOX using decoder 46
1143 // 2135: }
1144 130, 1, 10, // 2139: case 0x82: {
1145 OPC_CheckPredicate, 0, // 2142: check predicate 0
1146 OPC_CheckField, 14, 5, 0, // 2144: check Inst[18:14] == 0x0
1147 OPC_Decode, 231, 3, 39, // 2148: decode to FDTOX using decoder 39
1148 // 2148: }
1149 131, 1, 10, // 2152: case 0x83: {
1150 OPC_CheckPredicate, 0, // 2155: check predicate 0
1151 OPC_CheckField, 14, 5, 0, // 2157: check Inst[18:14] == 0x0
1152 OPC_Decode, 196, 4, 47, // 2161: decode to FQTOX using decoder 47
1153 // 2161: }
1154 132, 1, 10, // 2165: case 0x84: {
1155 OPC_CheckPredicate, 0, // 2168: check predicate 0
1156 OPC_CheckField, 14, 5, 0, // 2170: check Inst[18:14] == 0x0
1157 OPC_Decode, 226, 4, 48, // 2174: decode to FXTOS using decoder 48
1158 // 2174: }
1159 136, 1, 10, // 2178: case 0x88: {
1160 OPC_CheckPredicate, 0, // 2181: check predicate 0
1161 OPC_CheckField, 14, 5, 0, // 2183: check Inst[18:14] == 0x0
1162 OPC_Decode, 224, 4, 39, // 2187: decode to FXTOD using decoder 39
1163 // 2187: }
1164 140, 1, 10, // 2191: case 0x8c: {
1165 OPC_CheckPredicate, 0, // 2194: check predicate 0
1166 OPC_CheckField, 14, 5, 0, // 2196: check Inst[18:14] == 0x0
1167 OPC_Decode, 225, 4, 49, // 2200: decode to FXTOQ using decoder 49
1168 // 2200: }
1169 196, 1, 8, // 2204: case 0xc4: {
1170 OPC_CheckField, 14, 5, 0, // 2207: check Inst[18:14] == 0x0
1171 OPC_Decode, 239, 3, 38, // 2211: decode to FITOS using decoder 38
1172 // 2211: }
1173 198, 1, 8, // 2215: case 0xc6: {
1174 OPC_CheckField, 14, 5, 0, // 2218: check Inst[18:14] == 0x0
1175 OPC_Decode, 230, 3, 48, // 2222: decode to FDTOS using decoder 48
1176 // 2222: }
1177 199, 1, 8, // 2226: case 0xc7: {
1178 OPC_CheckField, 14, 5, 0, // 2229: check Inst[18:14] == 0x0
1179 OPC_Decode, 195, 4, 50, // 2233: decode to FQTOS using decoder 50
1180 // 2233: }
1181 200, 1, 8, // 2237: case 0xc8: {
1182 OPC_CheckField, 14, 5, 0, // 2240: check Inst[18:14] == 0x0
1183 OPC_Decode, 237, 3, 46, // 2244: decode to FITOD using decoder 46
1184 // 2244: }
1185 201, 1, 8, // 2248: case 0xc9: {
1186 OPC_CheckField, 14, 5, 0, // 2251: check Inst[18:14] == 0x0
1187 OPC_Decode, 213, 4, 46, // 2255: decode to FSTOD using decoder 46
1188 // 2255: }
1189 203, 1, 8, // 2259: case 0xcb: {
1190 OPC_CheckField, 14, 5, 0, // 2262: check Inst[18:14] == 0x0
1191 OPC_Decode, 193, 4, 47, // 2266: decode to FQTOD using decoder 47
1192 // 2266: }
1193 204, 1, 8, // 2270: case 0xcc: {
1194 OPC_CheckField, 14, 5, 0, // 2273: check Inst[18:14] == 0x0
1195 OPC_Decode, 238, 3, 51, // 2277: decode to FITOQ using decoder 51
1196 // 2277: }
1197 205, 1, 8, // 2281: case 0xcd: {
1198 OPC_CheckField, 14, 5, 0, // 2284: check Inst[18:14] == 0x0
1199 OPC_Decode, 215, 4, 51, // 2288: decode to FSTOQ using decoder 51
1200 // 2288: }
1201 206, 1, 8, // 2292: case 0xce: {
1202 OPC_CheckField, 14, 5, 0, // 2295: check Inst[18:14] == 0x0
1203 OPC_Decode, 229, 3, 49, // 2299: decode to FDTOQ using decoder 49
1204 // 2299: }
1205 209, 1, 8, // 2303: case 0xd1: {
1206 OPC_CheckField, 14, 5, 0, // 2306: check Inst[18:14] == 0x0
1207 OPC_Decode, 214, 4, 38, // 2310: decode to FSTOI using decoder 38
1208 // 2310: }
1209 210, 1, 8, // 2314: case 0xd2: {
1210 OPC_CheckField, 14, 5, 0, // 2317: check Inst[18:14] == 0x0
1211 OPC_Decode, 228, 3, 48, // 2321: decode to FDTOI using decoder 48
1212 // 2321: }
1213 211, 1, 0, // 2325: case 0xd3: {
1214 OPC_CheckField, 14, 5, 0, // 2328: check Inst[18:14] == 0x0
1215 OPC_Decode, 194, 4, 50, // 2332: decode to FQTOI using decoder 50
1216 // 2332: }
1217 // 2332: } // switch Inst[13:5]
1218 // 2332: }
1219 53, 157, 2, // 2336: case 0x35: {
1220 OPC_SwitchField, 5, 5, // 2339: switch Inst[9:5] {
1221 1, 60, // 2342: case 0x1: {
1222 OPC_SwitchField, 13, 1, // 2344: switch Inst[13] {
1223 0, 26, // 2347: case 0x0: {
1224 OPC_CheckField, 10, 1, 0, // 2349: check Inst[10] == 0x0
1225 OPC_CheckField, 18, 1, 0, // 2353: check Inst[18] == 0x0
1226 OPC_Scope, 10, // 2357: try {
1227 OPC_CheckField, 11, 2, 0, // 2359: check Inst[12:11] == 0x0
1228 OPC_CheckPredicate, 0, // 2363: check predicate 0
1229 OPC_Decode, 133, 4, 52, // 2365: decode to FMOVS_FCC using decoder 52
1230 // 2365: } else try {
1231 OPC_CheckPredicate, 0, // 2369: check predicate 0
1232 OPC_Decode, 231, 6, 53, // 2371: decode to V9FMOVS_FCC using decoder 53
1233 // 2371: }
1234 // 2371: }
1235 1, 0, // 2375: case 0x1: {
1236 OPC_SwitchField, 10, 3, // 2377: switch Inst[12:10] {
1237 0, 10, // 2380: case 0x0: {
1238 OPC_CheckPredicate, 0, // 2382: check predicate 0
1239 OPC_CheckField, 18, 1, 0, // 2384: check Inst[18] == 0x0
1240 OPC_Decode, 134, 4, 52, // 2388: decode to FMOVS_ICC using decoder 52
1241 // 2388: }
1242 4, 0, // 2392: case 0x4: {
1243 OPC_CheckPredicate, 1, // 2394: check predicate 1
1244 OPC_CheckField, 18, 1, 0, // 2396: check Inst[18] == 0x0
1245 OPC_Decode, 135, 4, 52, // 2400: decode to FMOVS_XCC using decoder 52
1246 // 2400: }
1247 // 2400: } // switch Inst[12:10]
1248 // 2400: }
1249 // 2400: } // switch Inst[13]
1250 // 2400: }
1251 2, 60, // 2404: case 0x2: {
1252 OPC_SwitchField, 13, 1, // 2406: switch Inst[13] {
1253 0, 26, // 2409: case 0x0: {
1254 OPC_CheckField, 10, 1, 0, // 2411: check Inst[10] == 0x0
1255 OPC_CheckField, 18, 1, 0, // 2415: check Inst[18] == 0x0
1256 OPC_Scope, 10, // 2419: try {
1257 OPC_CheckField, 11, 2, 0, // 2421: check Inst[12:11] == 0x0
1258 OPC_CheckPredicate, 0, // 2425: check predicate 0
1259 OPC_Decode, 250, 3, 54, // 2427: decode to FMOVD_FCC using decoder 54
1260 // 2427: } else try {
1261 OPC_CheckPredicate, 0, // 2431: check predicate 0
1262 OPC_Decode, 229, 6, 55, // 2433: decode to V9FMOVD_FCC using decoder 55
1263 // 2433: }
1264 // 2433: }
1265 1, 0, // 2437: case 0x1: {
1266 OPC_SwitchField, 10, 3, // 2439: switch Inst[12:10] {
1267 0, 10, // 2442: case 0x0: {
1268 OPC_CheckPredicate, 0, // 2444: check predicate 0
1269 OPC_CheckField, 18, 1, 0, // 2446: check Inst[18] == 0x0
1270 OPC_Decode, 251, 3, 54, // 2450: decode to FMOVD_ICC using decoder 54
1271 // 2450: }
1272 4, 0, // 2454: case 0x4: {
1273 OPC_CheckPredicate, 1, // 2456: check predicate 1
1274 OPC_CheckField, 18, 1, 0, // 2458: check Inst[18] == 0x0
1275 OPC_Decode, 252, 3, 54, // 2462: decode to FMOVD_XCC using decoder 54
1276 // 2462: }
1277 // 2462: } // switch Inst[12:10]
1278 // 2462: }
1279 // 2462: } // switch Inst[13]
1280 // 2462: }
1281 3, 60, // 2466: case 0x3: {
1282 OPC_SwitchField, 13, 1, // 2468: switch Inst[13] {
1283 0, 26, // 2471: case 0x0: {
1284 OPC_CheckField, 10, 1, 0, // 2473: check Inst[10] == 0x0
1285 OPC_CheckField, 18, 1, 0, // 2477: check Inst[18] == 0x0
1286 OPC_Scope, 10, // 2481: try {
1287 OPC_CheckField, 11, 2, 0, // 2483: check Inst[12:11] == 0x0
1288 OPC_CheckPredicate, 0, // 2487: check predicate 0
1289 OPC_Decode, 254, 3, 56, // 2489: decode to FMOVQ_FCC using decoder 56
1290 // 2489: } else try {
1291 OPC_CheckPredicate, 0, // 2493: check predicate 0
1292 OPC_Decode, 230, 6, 57, // 2495: decode to V9FMOVQ_FCC using decoder 57
1293 // 2495: }
1294 // 2495: }
1295 1, 0, // 2499: case 0x1: {
1296 OPC_SwitchField, 10, 3, // 2501: switch Inst[12:10] {
1297 0, 10, // 2504: case 0x0: {
1298 OPC_CheckPredicate, 0, // 2506: check predicate 0
1299 OPC_CheckField, 18, 1, 0, // 2508: check Inst[18] == 0x0
1300 OPC_Decode, 255, 3, 56, // 2512: decode to FMOVQ_ICC using decoder 56
1301 // 2512: }
1302 4, 0, // 2516: case 0x4: {
1303 OPC_CheckPredicate, 1, // 2518: check predicate 1
1304 OPC_CheckField, 18, 1, 0, // 2520: check Inst[18] == 0x0
1305 OPC_Decode, 128, 4, 56, // 2524: decode to FMOVQ_XCC using decoder 56
1306 // 2524: }
1307 // 2524: } // switch Inst[12:10]
1308 // 2524: }
1309 // 2524: } // switch Inst[13]
1310 // 2524: }
1311 5, 10, // 2528: case 0x5: {
1312 OPC_CheckPredicate, 0, // 2530: check predicate 0
1313 OPC_CheckField, 13, 1, 0, // 2532: check Inst[13] == 0x0
1314 OPC_Decode, 131, 4, 58, // 2536: decode to FMOVRS using decoder 58
1315 // 2536: }
1316 6, 10, // 2540: case 0x6: {
1317 OPC_CheckPredicate, 0, // 2542: check predicate 0
1318 OPC_CheckField, 13, 1, 0, // 2544: check Inst[13] == 0x0
1319 OPC_Decode, 129, 4, 59, // 2548: decode to FMOVRD using decoder 59
1320 // 2548: }
1321 7, 10, // 2552: case 0x7: {
1322 OPC_CheckPredicate, 0, // 2554: check predicate 0
1323 OPC_CheckField, 13, 1, 0, // 2556: check Inst[13] == 0x0
1324 OPC_Decode, 130, 4, 60, // 2560: decode to FMOVRQ using decoder 60
1325 // 2560: }
1326 17, 8, // 2564: case 0x11: {
1327 OPC_CheckField, 10, 4, 2, // 2566: check Inst[13:10] == 0x2
1328 OPC_Decode, 228, 6, 61, // 2570: decode to V9FCMPS using decoder 61
1329 // 2570: }
1330 18, 8, // 2574: case 0x12: {
1331 OPC_CheckField, 10, 4, 2, // 2576: check Inst[13:10] == 0x2
1332 OPC_Decode, 223, 6, 62, // 2580: decode to V9FCMPD using decoder 62
1333 // 2580: }
1334 19, 8, // 2584: case 0x13: {
1335 OPC_CheckField, 10, 4, 2, // 2586: check Inst[13:10] == 0x2
1336 OPC_Decode, 227, 6, 63, // 2590: decode to V9FCMPQ using decoder 63
1337 // 2590: }
1338 21, 8, // 2594: case 0x15: {
1339 OPC_CheckField, 10, 4, 2, // 2596: check Inst[13:10] == 0x2
1340 OPC_Decode, 226, 6, 61, // 2600: decode to V9FCMPES using decoder 61
1341 // 2600: }
1342 22, 8, // 2604: case 0x16: {
1343 OPC_CheckField, 10, 4, 2, // 2606: check Inst[13:10] == 0x2
1344 OPC_Decode, 224, 6, 62, // 2610: decode to V9FCMPED using decoder 62
1345 // 2610: }
1346 23, 0, // 2614: case 0x17: {
1347 OPC_CheckField, 10, 4, 2, // 2616: check Inst[13:10] == 0x2
1348 OPC_Decode, 225, 6, 63, // 2620: decode to V9FCMPEQ using decoder 63
1349 // 2620: }
1350 // 2620: } // switch Inst[9:5]
1351 // 2620: }
1352 54, 241, 9, // 2624: case 0x36: {
1353 OPC_SwitchField, 5, 9, // 2627: switch Inst[13:5] {
1354 0, 6, // 2630: case 0x0: {
1355 OPC_CheckPredicate, 7, // 2632: check predicate 7
1356 OPC_Decode, 188, 3, 13, // 2634: decode to EDGE8 using decoder 13
1357 // 2634: }
1358 1, 6, // 2638: case 0x1: {
1359 OPC_CheckPredicate, 8, // 2640: check predicate 8
1360 OPC_Decode, 191, 3, 13, // 2642: decode to EDGE8N using decoder 13
1361 // 2642: }
1362 2, 6, // 2646: case 0x2: {
1363 OPC_CheckPredicate, 7, // 2648: check predicate 7
1364 OPC_Decode, 189, 3, 13, // 2650: decode to EDGE8L using decoder 13
1365 // 2650: }
1366 3, 6, // 2654: case 0x3: {
1367 OPC_CheckPredicate, 8, // 2656: check predicate 8
1368 OPC_Decode, 190, 3, 13, // 2658: decode to EDGE8LN using decoder 13
1369 // 2658: }
1370 4, 6, // 2662: case 0x4: {
1371 OPC_CheckPredicate, 7, // 2664: check predicate 7
1372 OPC_Decode, 180, 3, 13, // 2666: decode to EDGE16 using decoder 13
1373 // 2666: }
1374 5, 6, // 2670: case 0x5: {
1375 OPC_CheckPredicate, 8, // 2672: check predicate 8
1376 OPC_Decode, 183, 3, 13, // 2674: decode to EDGE16N using decoder 13
1377 // 2674: }
1378 6, 6, // 2678: case 0x6: {
1379 OPC_CheckPredicate, 7, // 2680: check predicate 7
1380 OPC_Decode, 181, 3, 13, // 2682: decode to EDGE16L using decoder 13
1381 // 2682: }
1382 7, 6, // 2686: case 0x7: {
1383 OPC_CheckPredicate, 8, // 2688: check predicate 8
1384 OPC_Decode, 182, 3, 13, // 2690: decode to EDGE16LN using decoder 13
1385 // 2690: }
1386 8, 6, // 2694: case 0x8: {
1387 OPC_CheckPredicate, 7, // 2696: check predicate 7
1388 OPC_Decode, 184, 3, 13, // 2698: decode to EDGE32 using decoder 13
1389 // 2698: }
1390 9, 6, // 2702: case 0x9: {
1391 OPC_CheckPredicate, 8, // 2704: check predicate 8
1392 OPC_Decode, 187, 3, 13, // 2706: decode to EDGE32N using decoder 13
1393 // 2706: }
1394 10, 6, // 2710: case 0xa: {
1395 OPC_CheckPredicate, 7, // 2712: check predicate 7
1396 OPC_Decode, 185, 3, 13, // 2714: decode to EDGE32L using decoder 13
1397 // 2714: }
1398 11, 6, // 2718: case 0xb: {
1399 OPC_CheckPredicate, 8, // 2720: check predicate 8
1400 OPC_Decode, 186, 3, 13, // 2722: decode to EDGE32LN using decoder 13
1401 // 2722: }
1402 16, 6, // 2726: case 0x10: {
1403 OPC_CheckPredicate, 7, // 2728: check predicate 7
1404 OPC_Decode, 128, 3, 13, // 2730: decode to ARRAY8 using decoder 13
1405 // 2730: }
1406 17, 6, // 2734: case 0x11: {
1407 OPC_CheckPredicate, 6, // 2736: check predicate 6
1408 OPC_Decode, 228, 2, 13, // 2738: decode to ADDXC using decoder 13
1409 // 2738: }
1410 18, 6, // 2742: case 0x12: {
1411 OPC_CheckPredicate, 7, // 2744: check predicate 7
1412 OPC_Decode, 254, 2, 13, // 2746: decode to ARRAY16 using decoder 13
1413 // 2746: }
1414 19, 6, // 2750: case 0x13: {
1415 OPC_CheckPredicate, 6, // 2752: check predicate 6
1416 OPC_Decode, 229, 2, 13, // 2754: decode to ADDXCCC using decoder 13
1417 // 2754: }
1418 20, 6, // 2758: case 0x14: {
1419 OPC_CheckPredicate, 7, // 2760: check predicate 7
1420 OPC_Decode, 255, 2, 13, // 2762: decode to ARRAY32 using decoder 13
1421 // 2762: }
1422 22, 6, // 2766: case 0x16: {
1423 OPC_CheckPredicate, 6, // 2768: check predicate 6
1424 OPC_Decode, 219, 6, 13, // 2770: decode to UMULXHI using decoder 13
1425 // 2770: }
1426 23, 10, // 2774: case 0x17: {
1427 OPC_CheckPredicate, 6, // 2776: check predicate 6
1428 OPC_CheckField, 14, 5, 0, // 2778: check Inst[18:14] == 0x0
1429 OPC_Decode, 164, 5, 64, // 2782: decode to LZCNT using decoder 64
1430 // 2782: }
1431 24, 6, // 2786: case 0x18: {
1432 OPC_CheckPredicate, 7, // 2788: check predicate 7
1433 OPC_Decode, 243, 2, 13, // 2790: decode to ALIGNADDR using decoder 13
1434 // 2790: }
1435 25, 6, // 2794: case 0x19: {
1436 OPC_CheckPredicate, 8, // 2796: check predicate 8
1437 OPC_Decode, 134, 3, 13, // 2798: decode to BMASK using decoder 13
1438 // 2798: }
1439 26, 6, // 2802: case 0x1a: {
1440 OPC_CheckPredicate, 7, // 2804: check predicate 7
1441 OPC_Decode, 244, 2, 13, // 2806: decode to ALIGNADDRL using decoder 13
1442 // 2806: }
1443 27, 14, // 2810: case 0x1b: {
1444 OPC_CheckPredicate, 6, // 2812: check predicate 6
1445 OPC_CheckField, 25, 5, 0, // 2814: check Inst[29:25] == 0x0
1446 OPC_CheckField, 14, 5, 0, // 2818: check Inst[18:14] == 0x0
1447 OPC_Decode, 167, 3, 65, // 2822: decode to CMASK8 using decoder 65
1448 // 2822: }
1449 29, 14, // 2826: case 0x1d: {
1450 OPC_CheckPredicate, 6, // 2828: check predicate 6
1451 OPC_CheckField, 25, 5, 0, // 2830: check Inst[29:25] == 0x0
1452 OPC_CheckField, 14, 5, 0, // 2834: check Inst[18:14] == 0x0
1453 OPC_Decode, 165, 3, 65, // 2838: decode to CMASK16 using decoder 65
1454 // 2838: }
1455 31, 14, // 2842: case 0x1f: {
1456 OPC_CheckPredicate, 6, // 2844: check predicate 6
1457 OPC_CheckField, 25, 5, 0, // 2846: check Inst[29:25] == 0x0
1458 OPC_CheckField, 14, 5, 0, // 2850: check Inst[18:14] == 0x0
1459 OPC_Decode, 166, 3, 65, // 2854: decode to CMASK32 using decoder 65
1460 // 2854: }
1461 32, 6, // 2858: case 0x20: {
1462 OPC_CheckPredicate, 7, // 2860: check predicate 7
1463 OPC_Decode, 216, 3, 66, // 2862: decode to FCMPLE16 using decoder 66
1464 // 2862: }
1465 33, 6, // 2866: case 0x21: {
1466 OPC_CheckPredicate, 6, // 2868: check predicate 6
1467 OPC_Decode, 199, 4, 42, // 2870: decode to FSLL16 using decoder 42
1468 // 2870: }
1469 34, 6, // 2874: case 0x22: {
1470 OPC_CheckPredicate, 7, // 2876: check predicate 7
1471 OPC_Decode, 218, 3, 66, // 2878: decode to FCMPNE16 using decoder 66
1472 // 2878: }
1473 35, 6, // 2882: case 0x23: {
1474 OPC_CheckPredicate, 6, // 2884: check predicate 6
1475 OPC_Decode, 211, 4, 42, // 2886: decode to FSRL16 using decoder 42
1476 // 2886: }
1477 36, 6, // 2890: case 0x24: {
1478 OPC_CheckPredicate, 7, // 2892: check predicate 7
1479 OPC_Decode, 217, 3, 66, // 2894: decode to FCMPLE32 using decoder 66
1480 // 2894: }
1481 37, 6, // 2898: case 0x25: {
1482 OPC_CheckPredicate, 6, // 2900: check predicate 6
1483 OPC_Decode, 200, 4, 42, // 2902: decode to FSLL32 using decoder 42
1484 // 2902: }
1485 38, 6, // 2906: case 0x26: {
1486 OPC_CheckPredicate, 7, // 2908: check predicate 7
1487 OPC_Decode, 219, 3, 66, // 2910: decode to FCMPNE32 using decoder 66
1488 // 2910: }
1489 39, 6, // 2914: case 0x27: {
1490 OPC_CheckPredicate, 6, // 2916: check predicate 6
1491 OPC_Decode, 212, 4, 42, // 2918: decode to FSRL32 using decoder 42
1492 // 2918: }
1493 40, 6, // 2922: case 0x28: {
1494 OPC_CheckPredicate, 7, // 2924: check predicate 7
1495 OPC_Decode, 214, 3, 66, // 2926: decode to FCMPGT16 using decoder 66
1496 // 2926: }
1497 41, 6, // 2930: case 0x29: {
1498 OPC_CheckPredicate, 6, // 2932: check predicate 6
1499 OPC_Decode, 197, 4, 42, // 2934: decode to FSLAS16 using decoder 42
1500 // 2934: }
1501 42, 6, // 2938: case 0x2a: {
1502 OPC_CheckPredicate, 7, // 2940: check predicate 7
1503 OPC_Decode, 212, 3, 66, // 2942: decode to FCMPEQ16 using decoder 66
1504 // 2942: }
1505 43, 6, // 2946: case 0x2b: {
1506 OPC_CheckPredicate, 6, // 2948: check predicate 6
1507 OPC_Decode, 205, 4, 42, // 2950: decode to FSRA16 using decoder 42
1508 // 2950: }
1509 44, 6, // 2954: case 0x2c: {
1510 OPC_CheckPredicate, 7, // 2956: check predicate 7
1511 OPC_Decode, 215, 3, 66, // 2958: decode to FCMPGT32 using decoder 66
1512 // 2958: }
1513 45, 6, // 2962: case 0x2d: {
1514 OPC_CheckPredicate, 6, // 2964: check predicate 6
1515 OPC_Decode, 198, 4, 42, // 2966: decode to FSLAS32 using decoder 42
1516 // 2966: }
1517 46, 6, // 2970: case 0x2e: {
1518 OPC_CheckPredicate, 7, // 2972: check predicate 7
1519 OPC_Decode, 213, 3, 66, // 2974: decode to FCMPEQ32 using decoder 66
1520 // 2974: }
1521 47, 6, // 2978: case 0x2f: {
1522 OPC_CheckPredicate, 6, // 2980: check predicate 6
1523 OPC_Decode, 206, 4, 42, // 2982: decode to FSRA32 using decoder 42
1524 // 2982: }
1525 49, 6, // 2986: case 0x31: {
1526 OPC_CheckPredicate, 7, // 2988: check predicate 7
1527 OPC_Decode, 140, 4, 67, // 2990: decode to FMUL8X16 using decoder 67
1528 // 2990: }
1529 51, 6, // 2994: case 0x33: {
1530 OPC_CheckPredicate, 7, // 2996: check predicate 7
1531 OPC_Decode, 142, 4, 44, // 2998: decode to FMUL8X16AU using decoder 44
1532 // 2998: }
1533 53, 6, // 3002: case 0x35: {
1534 OPC_CheckPredicate, 7, // 3004: check predicate 7
1535 OPC_Decode, 141, 4, 44, // 3006: decode to FMUL8X16AL using decoder 44
1536 // 3006: }
1537 54, 6, // 3010: case 0x36: {
1538 OPC_CheckPredicate, 7, // 3012: check predicate 7
1539 OPC_Decode, 138, 4, 42, // 3014: decode to FMUL8SUX16 using decoder 42
1540 // 3014: }
1541 55, 6, // 3018: case 0x37: {
1542 OPC_CheckPredicate, 7, // 3020: check predicate 7
1543 OPC_Decode, 139, 4, 42, // 3022: decode to FMUL8ULX16 using decoder 42
1544 // 3022: }
1545 56, 6, // 3026: case 0x38: {
1546 OPC_CheckPredicate, 7, // 3028: check predicate 7
1547 OPC_Decode, 144, 4, 44, // 3030: decode to FMULD8SUX16 using decoder 44
1548 // 3030: }
1549 57, 6, // 3034: case 0x39: {
1550 OPC_CheckPredicate, 7, // 3036: check predicate 7
1551 OPC_Decode, 145, 4, 44, // 3038: decode to FMULD8ULX16 using decoder 44
1552 // 3038: }
1553 58, 6, // 3042: case 0x3a: {
1554 OPC_CheckPredicate, 7, // 3044: check predicate 7
1555 OPC_Decode, 179, 4, 42, // 3046: decode to FPACK32 using decoder 42
1556 // 3046: }
1557 59, 10, // 3050: case 0x3b: {
1558 OPC_CheckPredicate, 7, // 3052: check predicate 7
1559 OPC_CheckField, 14, 5, 0, // 3054: check Inst[18:14] == 0x0
1560 OPC_Decode, 178, 4, 39, // 3058: decode to FPACK16 using decoder 39
1561 // 3058: }
1562 61, 10, // 3062: case 0x3d: {
1563 OPC_CheckPredicate, 7, // 3064: check predicate 7
1564 OPC_CheckField, 14, 5, 0, // 3066: check Inst[18:14] == 0x0
1565 OPC_Decode, 180, 4, 48, // 3070: decode to FPACKFIX using decoder 48
1566 // 3070: }
1567 62, 6, // 3074: case 0x3e: {
1568 OPC_CheckPredicate, 7, // 3076: check predicate 7
1569 OPC_Decode, 198, 5, 42, // 3078: decode to PDIST using decoder 42
1570 // 3078: }
1571 63, 6, // 3082: case 0x3f: {
1572 OPC_CheckPredicate, 6, // 3084: check predicate 6
1573 OPC_Decode, 199, 5, 66, // 3086: decode to PDISTN using decoder 66
1574 // 3086: }
1575 64, 6, // 3090: case 0x40: {
1576 OPC_CheckPredicate, 6, // 3092: check predicate 6
1577 OPC_Decode, 248, 3, 42, // 3094: decode to FMEAN16 using decoder 42
1578 // 3094: }
1579 66, 6, // 3098: case 0x42: {
1580 OPC_CheckPredicate, 6, // 3100: check predicate 6
1581 OPC_Decode, 185, 4, 42, // 3102: decode to FPADD64 using decoder 42
1582 // 3102: }
1583 68, 6, // 3106: case 0x44: {
1584 OPC_CheckPredicate, 6, // 3108: check predicate 6
1585 OPC_Decode, 209, 3, 42, // 3110: decode to FCHKSM16 using decoder 42
1586 // 3110: }
1587 72, 6, // 3114: case 0x48: {
1588 OPC_CheckPredicate, 7, // 3116: check predicate 7
1589 OPC_Decode, 198, 3, 42, // 3118: decode to FALIGNADATA using decoder 42
1590 // 3118: }
1591 75, 6, // 3122: case 0x4b: {
1592 OPC_CheckPredicate, 7, // 3124: check predicate 7
1593 OPC_Decode, 188, 4, 44, // 3126: decode to FPMERGE using decoder 44
1594 // 3126: }
1595 76, 6, // 3130: case 0x4c: {
1596 OPC_CheckPredicate, 8, // 3132: check predicate 8
1597 OPC_Decode, 151, 3, 42, // 3134: decode to BSHUFFLE using decoder 42
1598 // 3134: }
1599 77, 10, // 3138: case 0x4d: {
1600 OPC_CheckPredicate, 7, // 3140: check predicate 7
1601 OPC_CheckField, 14, 5, 0, // 3142: check Inst[18:14] == 0x0
1602 OPC_Decode, 232, 3, 46, // 3146: decode to FEXPAND using decoder 46
1603 // 3146: }
1604 80, 6, // 3150: case 0x50: {
1605 OPC_CheckPredicate, 7, // 3152: check predicate 7
1606 OPC_Decode, 181, 4, 42, // 3154: decode to FPADD16 using decoder 42
1607 // 3154: }
1608 81, 6, // 3158: case 0x51: {
1609 OPC_CheckPredicate, 7, // 3160: check predicate 7
1610 OPC_Decode, 182, 4, 41, // 3162: decode to FPADD16S using decoder 41
1611 // 3162: }
1612 82, 6, // 3166: case 0x52: {
1613 OPC_CheckPredicate, 7, // 3168: check predicate 7
1614 OPC_Decode, 183, 4, 42, // 3170: decode to FPADD32 using decoder 42
1615 // 3170: }
1616 83, 6, // 3174: case 0x53: {
1617 OPC_CheckPredicate, 7, // 3176: check predicate 7
1618 OPC_Decode, 184, 4, 41, // 3178: decode to FPADD32S using decoder 41
1619 // 3178: }
1620 84, 6, // 3182: case 0x54: {
1621 OPC_CheckPredicate, 7, // 3184: check predicate 7
1622 OPC_Decode, 189, 4, 42, // 3186: decode to FPSUB16 using decoder 42
1623 // 3186: }
1624 85, 6, // 3190: case 0x55: {
1625 OPC_CheckPredicate, 7, // 3192: check predicate 7
1626 OPC_Decode, 190, 4, 41, // 3194: decode to FPSUB16S using decoder 41
1627 // 3194: }
1628 86, 6, // 3198: case 0x56: {
1629 OPC_CheckPredicate, 7, // 3200: check predicate 7
1630 OPC_Decode, 191, 4, 42, // 3202: decode to FPSUB32 using decoder 42
1631 // 3202: }
1632 87, 6, // 3206: case 0x57: {
1633 OPC_CheckPredicate, 7, // 3208: check predicate 7
1634 OPC_Decode, 192, 4, 41, // 3210: decode to FPSUB32S using decoder 41
1635 // 3210: }
1636 96, 14, // 3214: case 0x60: {
1637 OPC_CheckPredicate, 7, // 3216: check predicate 7
1638 OPC_CheckField, 14, 5, 0, // 3218: check Inst[18:14] == 0x0
1639 OPC_CheckField, 0, 5, 0, // 3222: check Inst[4:0] == 0x0
1640 OPC_Decode, 227, 4, 68, // 3226: decode to FZERO using decoder 68
1641 // 3226: }
1642 97, 14, // 3230: case 0x61: {
1643 OPC_CheckPredicate, 7, // 3232: check predicate 7
1644 OPC_CheckField, 14, 5, 0, // 3234: check Inst[18:14] == 0x0
1645 OPC_CheckField, 0, 5, 0, // 3238: check Inst[4:0] == 0x0
1646 OPC_Decode, 228, 4, 69, // 3242: decode to FZEROS using decoder 69
1647 // 3242: }
1648 98, 6, // 3246: case 0x62: {
1649 OPC_CheckPredicate, 7, // 3248: check predicate 7
1650 OPC_Decode, 163, 4, 42, // 3250: decode to FNOR using decoder 42
1651 // 3250: }
1652 99, 6, // 3254: case 0x63: {
1653 OPC_CheckPredicate, 7, // 3256: check predicate 7
1654 OPC_Decode, 164, 4, 41, // 3258: decode to FNORS using decoder 41
1655 // 3258: }
1656 100, 6, // 3262: case 0x64: {
1657 OPC_CheckPredicate, 7, // 3264: check predicate 7
1658 OPC_Decode, 202, 3, 42, // 3266: decode to FANDNOT2 using decoder 42
1659 // 3266: }
1660 101, 6, // 3270: case 0x65: {
1661 OPC_CheckPredicate, 7, // 3272: check predicate 7
1662 OPC_Decode, 203, 3, 41, // 3274: decode to FANDNOT2S using decoder 41
1663 // 3274: }
1664 102, 10, // 3278: case 0x66: {
1665 OPC_CheckPredicate, 7, // 3280: check predicate 7
1666 OPC_CheckField, 14, 5, 0, // 3282: check Inst[18:14] == 0x0
1667 OPC_Decode, 167, 4, 39, // 3286: decode to FNOT2 using decoder 39
1668 // 3286: }
1669 103, 10, // 3290: case 0x67: {
1670 OPC_CheckPredicate, 7, // 3292: check predicate 7
1671 OPC_CheckField, 14, 5, 0, // 3294: check Inst[18:14] == 0x0
1672 OPC_Decode, 168, 4, 38, // 3298: decode to FNOT2S using decoder 38
1673 // 3298: }
1674 104, 6, // 3302: case 0x68: {
1675 OPC_CheckPredicate, 7, // 3304: check predicate 7
1676 OPC_Decode, 200, 3, 42, // 3306: decode to FANDNOT1 using decoder 42
1677 // 3306: }
1678 105, 6, // 3310: case 0x69: {
1679 OPC_CheckPredicate, 7, // 3312: check predicate 7
1680 OPC_Decode, 201, 3, 41, // 3314: decode to FANDNOT1S using decoder 41
1681 // 3314: }
1682 106, 10, // 3318: case 0x6a: {
1683 OPC_CheckPredicate, 7, // 3320: check predicate 7
1684 OPC_CheckField, 0, 5, 0, // 3322: check Inst[4:0] == 0x0
1685 OPC_Decode, 165, 4, 70, // 3326: decode to FNOT1 using decoder 70
1686 // 3326: }
1687 107, 10, // 3330: case 0x6b: {
1688 OPC_CheckPredicate, 7, // 3332: check predicate 7
1689 OPC_CheckField, 0, 5, 0, // 3334: check Inst[4:0] == 0x0
1690 OPC_Decode, 166, 4, 71, // 3338: decode to FNOT1S using decoder 71
1691 // 3338: }
1692 108, 6, // 3342: case 0x6c: {
1693 OPC_CheckPredicate, 7, // 3344: check predicate 7
1694 OPC_Decode, 222, 4, 42, // 3346: decode to FXOR using decoder 42
1695 // 3346: }
1696 109, 6, // 3350: case 0x6d: {
1697 OPC_CheckPredicate, 7, // 3352: check predicate 7
1698 OPC_Decode, 223, 4, 41, // 3354: decode to FXORS using decoder 41
1699 // 3354: }
1700 110, 6, // 3358: case 0x6e: {
1701 OPC_CheckPredicate, 7, // 3360: check predicate 7
1702 OPC_Decode, 150, 4, 42, // 3362: decode to FNAND using decoder 42
1703 // 3362: }
1704 111, 6, // 3366: case 0x6f: {
1705 OPC_CheckPredicate, 7, // 3368: check predicate 7
1706 OPC_Decode, 151, 4, 41, // 3370: decode to FNANDS using decoder 41
1707 // 3370: }
1708 112, 6, // 3374: case 0x70: {
1709 OPC_CheckPredicate, 7, // 3376: check predicate 7
1710 OPC_Decode, 199, 3, 42, // 3378: decode to FAND using decoder 42
1711 // 3378: }
1712 113, 6, // 3382: case 0x71: {
1713 OPC_CheckPredicate, 7, // 3384: check predicate 7
1714 OPC_Decode, 204, 3, 41, // 3386: decode to FANDS using decoder 41
1715 // 3386: }
1716 114, 6, // 3390: case 0x72: {
1717 OPC_CheckPredicate, 7, // 3392: check predicate 7
1718 OPC_Decode, 220, 4, 42, // 3394: decode to FXNOR using decoder 42
1719 // 3394: }
1720 115, 6, // 3398: case 0x73: {
1721 OPC_CheckPredicate, 7, // 3400: check predicate 7
1722 OPC_Decode, 221, 4, 41, // 3402: decode to FXNORS using decoder 41
1723 // 3402: }
1724 116, 10, // 3406: case 0x74: {
1725 OPC_CheckPredicate, 7, // 3408: check predicate 7
1726 OPC_CheckField, 0, 5, 0, // 3410: check Inst[4:0] == 0x0
1727 OPC_Decode, 207, 4, 70, // 3414: decode to FSRC1 using decoder 70
1728 // 3414: }
1729 117, 10, // 3418: case 0x75: {
1730 OPC_CheckPredicate, 7, // 3420: check predicate 7
1731 OPC_CheckField, 0, 5, 0, // 3422: check Inst[4:0] == 0x0
1732 OPC_Decode, 208, 4, 71, // 3426: decode to FSRC1S using decoder 71
1733 // 3426: }
1734 118, 6, // 3430: case 0x76: {
1735 OPC_CheckPredicate, 7, // 3432: check predicate 7
1736 OPC_Decode, 175, 4, 42, // 3434: decode to FORNOT2 using decoder 42
1737 // 3434: }
1738 119, 6, // 3438: case 0x77: {
1739 OPC_CheckPredicate, 7, // 3440: check predicate 7
1740 OPC_Decode, 176, 4, 41, // 3442: decode to FORNOT2S using decoder 41
1741 // 3442: }
1742 120, 10, // 3446: case 0x78: {
1743 OPC_CheckPredicate, 7, // 3448: check predicate 7
1744 OPC_CheckField, 14, 5, 0, // 3450: check Inst[18:14] == 0x0
1745 OPC_Decode, 209, 4, 39, // 3454: decode to FSRC2 using decoder 39
1746 // 3454: }
1747 121, 10, // 3458: case 0x79: {
1748 OPC_CheckPredicate, 7, // 3460: check predicate 7
1749 OPC_CheckField, 14, 5, 0, // 3462: check Inst[18:14] == 0x0
1750 OPC_Decode, 210, 4, 38, // 3466: decode to FSRC2S using decoder 38
1751 // 3466: }
1752 122, 6, // 3470: case 0x7a: {
1753 OPC_CheckPredicate, 7, // 3472: check predicate 7
1754 OPC_Decode, 173, 4, 42, // 3474: decode to FORNOT1 using decoder 42
1755 // 3474: }
1756 123, 6, // 3478: case 0x7b: {
1757 OPC_CheckPredicate, 7, // 3480: check predicate 7
1758 OPC_Decode, 174, 4, 41, // 3482: decode to FORNOT1S using decoder 41
1759 // 3482: }
1760 124, 6, // 3486: case 0x7c: {
1761 OPC_CheckPredicate, 7, // 3488: check predicate 7
1762 OPC_Decode, 172, 4, 42, // 3490: decode to FOR using decoder 42
1763 // 3490: }
1764 125, 6, // 3494: case 0x7d: {
1765 OPC_CheckPredicate, 7, // 3496: check predicate 7
1766 OPC_Decode, 177, 4, 41, // 3498: decode to FORS using decoder 41
1767 // 3498: }
1768 126, 14, // 3502: case 0x7e: {
1769 OPC_CheckPredicate, 7, // 3504: check predicate 7
1770 OPC_CheckField, 14, 5, 0, // 3506: check Inst[18:14] == 0x0
1771 OPC_CheckField, 0, 5, 0, // 3510: check Inst[4:0] == 0x0
1772 OPC_Decode, 170, 4, 68, // 3514: decode to FONE using decoder 68
1773 // 3514: }
1774 127, 14, // 3518: case 0x7f: {
1775 OPC_CheckPredicate, 7, // 3520: check predicate 7
1776 OPC_CheckField, 14, 5, 0, // 3522: check Inst[18:14] == 0x0
1777 OPC_CheckField, 0, 5, 0, // 3526: check Inst[4:0] == 0x0
1778 OPC_Decode, 171, 4, 69, // 3530: decode to FONES using decoder 69
1779 // 3530: }
1780 128, 1, 18, // 3534: case 0x80: {
1781 OPC_CheckPredicate, 7, // 3537: check predicate 7
1782 OPC_CheckField, 25, 5, 0, // 3539: check Inst[29:25] == 0x0
1783 OPC_CheckField, 14, 5, 0, // 3543: check Inst[18:14] == 0x0
1784 OPC_CheckField, 0, 5, 0, // 3547: check Inst[4:0] == 0x0
1785 OPC_Decode, 234, 5, 7, // 3551: decode to SHUTDOWN using decoder 7
1786 // 3551: }
1787 129, 1, 18, // 3555: case 0x81: {
1788 OPC_CheckPredicate, 8, // 3558: check predicate 8
1789 OPC_CheckField, 25, 5, 0, // 3560: check Inst[29:25] == 0x0
1790 OPC_CheckField, 14, 5, 0, // 3564: check Inst[18:14] == 0x0
1791 OPC_CheckField, 3, 2, 0, // 3568: check Inst[4:3] == 0x0
1792 OPC_Decode, 235, 5, 72, // 3572: decode to SIAM using decoder 72
1793 // 3572: }
1794 144, 2, 10, // 3576: case 0x110: {
1795 OPC_CheckPredicate, 6, // 3579: check predicate 6
1796 OPC_CheckField, 14, 5, 0, // 3581: check Inst[18:14] == 0x0
1797 OPC_Decode, 169, 5, 73, // 3585: decode to MOVDTOX using decoder 73
1798 // 3585: }
1799 145, 2, 10, // 3589: case 0x111: {
1800 OPC_CheckPredicate, 6, // 3592: check predicate 6
1801 OPC_CheckField, 14, 5, 0, // 3594: check Inst[18:14] == 0x0
1802 OPC_Decode, 177, 5, 74, // 3598: decode to MOVSTOUW using decoder 74
1803 // 3598: }
1804 147, 2, 10, // 3602: case 0x113: {
1805 OPC_CheckPredicate, 6, // 3605: check predicate 6
1806 OPC_CheckField, 14, 5, 0, // 3607: check Inst[18:14] == 0x0
1807 OPC_Decode, 176, 5, 74, // 3611: decode to MOVSTOSW using decoder 74
1808 // 3611: }
1809 149, 2, 6, // 3615: case 0x115: {
1810 OPC_CheckPredicate, 6, // 3618: check predicate 6
1811 OPC_Decode, 244, 6, 13, // 3620: decode to XMULX using decoder 13
1812 // 3620: }
1813 150, 2, 6, // 3624: case 0x116: {
1814 OPC_CheckPredicate, 6, // 3627: check predicate 6
1815 OPC_Decode, 245, 6, 13, // 3629: decode to XMULXHI using decoder 13
1816 // 3629: }
1817 152, 2, 10, // 3633: case 0x118: {
1818 OPC_CheckPredicate, 6, // 3636: check predicate 6
1819 OPC_CheckField, 14, 5, 0, // 3638: check Inst[18:14] == 0x0
1820 OPC_Decode, 181, 5, 75, // 3642: decode to MOVXTOD using decoder 75
1821 // 3642: }
1822 153, 2, 10, // 3646: case 0x119: {
1823 OPC_CheckPredicate, 6, // 3649: check predicate 6
1824 OPC_CheckField, 14, 5, 0, // 3651: check Inst[18:14] == 0x0
1825 OPC_Decode, 178, 5, 76, // 3655: decode to MOVWTOS using decoder 76
1826 // 3655: }
1827 176, 2, 6, // 3659: case 0x130: {
1828 OPC_CheckPredicate, 3, // 3662: check predicate 3
1829 OPC_Decode, 240, 2, 42, // 3664: decode to AES_KEXPAND0 using decoder 42
1830 // 3664: }
1831 177, 2, 6, // 3668: case 0x131: {
1832 OPC_CheckPredicate, 3, // 3671: check predicate 3
1833 OPC_Decode, 242, 2, 42, // 3673: decode to AES_KEXPAND2 using decoder 42
1834 // 3673: }
1835 180, 2, 10, // 3677: case 0x134: {
1836 OPC_CheckPredicate, 3, // 3680: check predicate 3
1837 OPC_CheckField, 0, 5, 0, // 3682: check Inst[4:0] == 0x0
1838 OPC_Decode, 176, 3, 70, // 3686: decode to DES_IP using decoder 70
1839 // 3686: }
1840 181, 2, 10, // 3690: case 0x135: {
1841 OPC_CheckPredicate, 3, // 3693: check predicate 3
1842 OPC_CheckField, 0, 5, 0, // 3695: check Inst[4:0] == 0x0
1843 OPC_Decode, 175, 3, 70, // 3699: decode to DES_IIP using decoder 70
1844 // 3699: }
1845 182, 2, 6, // 3703: case 0x136: {
1846 OPC_CheckPredicate, 3, // 3706: check predicate 3
1847 OPC_Decode, 177, 3, 77, // 3708: decode to DES_KEXPAND using decoder 77
1848 // 3708: }
1849 188, 2, 6, // 3712: case 0x13c: {
1850 OPC_CheckPredicate, 3, // 3715: check predicate 3
1851 OPC_Decode, 159, 3, 42, // 3717: decode to CAMELLIA_FL using decoder 42
1852 // 3717: }
1853 189, 2, 6, // 3721: case 0x13d: {
1854 OPC_CheckPredicate, 3, // 3724: check predicate 3
1855 OPC_Decode, 160, 3, 42, // 3726: decode to CAMELLIA_FLI using decoder 42
1856 // 3726: }
1857 192, 2, 18, // 3730: case 0x140: {
1858 OPC_CheckPredicate, 3, // 3733: check predicate 3
1859 OPC_CheckField, 25, 5, 0, // 3735: check Inst[29:25] == 0x0
1860 OPC_CheckField, 14, 5, 0, // 3739: check Inst[18:14] == 0x0
1861 OPC_CheckField, 0, 5, 0, // 3743: check Inst[4:0] == 0x0
1862 OPC_Decode, 165, 5, 7, // 3747: decode to MD5 using decoder 7
1863 // 3747: }
1864 193, 2, 18, // 3751: case 0x141: {
1865 OPC_CheckPredicate, 3, // 3754: check predicate 3
1866 OPC_CheckField, 25, 5, 0, // 3756: check Inst[29:25] == 0x0
1867 OPC_CheckField, 14, 5, 0, // 3760: check Inst[18:14] == 0x0
1868 OPC_CheckField, 0, 5, 0, // 3764: check Inst[4:0] == 0x0
1869 OPC_Decode, 231, 5, 7, // 3768: decode to SHA1 using decoder 7
1870 // 3768: }
1871 194, 2, 18, // 3772: case 0x142: {
1872 OPC_CheckPredicate, 3, // 3775: check predicate 3
1873 OPC_CheckField, 25, 5, 0, // 3777: check Inst[29:25] == 0x0
1874 OPC_CheckField, 14, 5, 0, // 3781: check Inst[18:14] == 0x0
1875 OPC_CheckField, 0, 5, 0, // 3785: check Inst[4:0] == 0x0
1876 OPC_Decode, 232, 5, 7, // 3789: decode to SHA256 using decoder 7
1877 // 3789: }
1878 195, 2, 18, // 3793: case 0x143: {
1879 OPC_CheckPredicate, 3, // 3796: check predicate 3
1880 OPC_CheckField, 25, 5, 0, // 3798: check Inst[29:25] == 0x0
1881 OPC_CheckField, 14, 5, 0, // 3802: check Inst[18:14] == 0x0
1882 OPC_CheckField, 0, 5, 0, // 3806: check Inst[4:0] == 0x0
1883 OPC_Decode, 233, 5, 7, // 3810: decode to SHA512 using decoder 7
1884 // 3810: }
1885 199, 2, 6, // 3814: case 0x147: {
1886 OPC_CheckPredicate, 3, // 3817: check predicate 3
1887 OPC_Decode, 170, 3, 42, // 3819: decode to CRC32C using decoder 42
1888 // 3819: }
1889 200, 2, 14, // 3823: case 0x148: {
1890 OPC_CheckPredicate, 3, // 3826: check predicate 3
1891 OPC_CheckField, 25, 5, 0, // 3828: check Inst[29:25] == 0x0
1892 OPC_CheckField, 14, 5, 0, // 3832: check Inst[18:14] == 0x0
1893 OPC_Decode, 182, 5, 78, // 3836: decode to MPMUL using decoder 78
1894 // 3836: }
1895 201, 2, 14, // 3840: case 0x149: {
1896 OPC_CheckPredicate, 3, // 3843: check predicate 3
1897 OPC_CheckField, 25, 5, 0, // 3845: check Inst[29:25] == 0x0
1898 OPC_CheckField, 14, 5, 0, // 3849: check Inst[18:14] == 0x0
1899 OPC_Decode, 167, 5, 78, // 3853: decode to MONTMUL using decoder 78
1900 // 3853: }
1901 202, 2, 14, // 3857: case 0x14a: {
1902 OPC_CheckPredicate, 3, // 3860: check predicate 3
1903 OPC_CheckField, 25, 5, 0, // 3862: check Inst[29:25] == 0x0
1904 OPC_CheckField, 14, 5, 0, // 3866: check Inst[18:14] == 0x0
1905 OPC_Decode, 168, 5, 78, // 3870: decode to MONTSQR using decoder 78
1906 // 3870: }
1907 209, 2, 6, // 3874: case 0x151: {
1908 OPC_CheckPredicate, 6, // 3877: check predicate 6
1909 OPC_Decode, 241, 3, 61, // 3879: decode to FLCMPS using decoder 61
1910 // 3879: }
1911 210, 2, 0, // 3883: case 0x152: {
1912 OPC_CheckPredicate, 6, // 3886: check predicate 6
1913 OPC_Decode, 240, 3, 62, // 3888: decode to FLCMPD using decoder 62
1914 // 3888: }
1915 // 3888: } // switch Inst[13:5]
1916 // 3888: }
1917 55, 83, // 3892: case 0x37: {
1918 OPC_SwitchField, 5, 4, // 3894: switch Inst[8:5] {
1919 0, 6, // 3897: case 0x0: {
1920 OPC_CheckPredicate, 2, // 3899: check predicate 2
1921 OPC_Decode, 186, 4, 15, // 3901: decode to FPMADDX using decoder 15
1922 // 3901: }
1923 1, 6, // 3905: case 0x1: {
1924 OPC_CheckPredicate, 9, // 3907: check predicate 9
1925 OPC_Decode, 247, 3, 79, // 3909: decode to FMADDS using decoder 79
1926 // 3909: }
1927 2, 6, // 3913: case 0x2: {
1928 OPC_CheckPredicate, 9, // 3915: check predicate 9
1929 OPC_Decode, 246, 3, 15, // 3917: decode to FMADDD using decoder 15
1930 // 3917: }
1931 4, 6, // 3921: case 0x4: {
1932 OPC_CheckPredicate, 2, // 3923: check predicate 2
1933 OPC_Decode, 187, 4, 15, // 3925: decode to FPMADDXHI using decoder 15
1934 // 3925: }
1935 5, 6, // 3929: case 0x5: {
1936 OPC_CheckPredicate, 9, // 3931: check predicate 9
1937 OPC_Decode, 137, 4, 79, // 3933: decode to FMSUBS using decoder 79
1938 // 3933: }
1939 6, 6, // 3937: case 0x6: {
1940 OPC_CheckPredicate, 9, // 3939: check predicate 9
1941 OPC_Decode, 136, 4, 15, // 3941: decode to FMSUBD using decoder 15
1942 // 3941: }
1943 9, 6, // 3945: case 0x9: {
1944 OPC_CheckPredicate, 9, // 3947: check predicate 9
1945 OPC_Decode, 160, 4, 79, // 3949: decode to FNMSUBS using decoder 79
1946 // 3949: }
1947 10, 6, // 3953: case 0xa: {
1948 OPC_CheckPredicate, 9, // 3955: check predicate 9
1949 OPC_Decode, 159, 4, 15, // 3957: decode to FNMSUBD using decoder 15
1950 // 3957: }
1951 13, 6, // 3961: case 0xd: {
1952 OPC_CheckPredicate, 9, // 3963: check predicate 9
1953 OPC_Decode, 158, 4, 79, // 3965: decode to FNMADDS using decoder 79
1954 // 3965: }
1955 14, 0, // 3969: case 0xe: {
1956 OPC_CheckPredicate, 9, // 3971: check predicate 9
1957 OPC_Decode, 157, 4, 15, // 3973: decode to FNMADDD using decoder 15
1958 // 3973: }
1959 // 3973: } // switch Inst[8:5]
1960 // 3973: }
1961 56, 19, // 3977: case 0x38: {
1962 OPC_SwitchField, 13, 1, // 3979: switch Inst[13] {
1963 0, 8, // 3982: case 0x0: {
1964 OPC_CheckField, 5, 8, 0, // 3984: check Inst[12:5] == 0x0
1965 OPC_Decode, 233, 4, 11, // 3988: decode to JMPLrr using decoder 11
1966 // 3988: }
1967 1, 0, // 3992: case 0x1: {
1968 OPC_Decode, 232, 4, 12, // 3994: decode to JMPLri using decoder 12
1969 // 3994: }
1970 // 3994: } // switch Inst[13]
1971 // 3994: }
1972 57, 27, // 3998: case 0x39: {
1973 OPC_SwitchField, 13, 1, // 4000: switch Inst[13] {
1974 0, 12, // 4003: case 0x0: {
1975 OPC_CheckField, 25, 5, 0, // 4005: check Inst[29:25] == 0x0
1976 OPC_CheckField, 5, 8, 0, // 4009: check Inst[12:5] == 0x0
1977 OPC_Decode, 220, 5, 34, // 4013: decode to RETTrr using decoder 34
1978 // 4013: }
1979 1, 0, // 4017: case 0x1: {
1980 OPC_CheckField, 25, 5, 0, // 4019: check Inst[29:25] == 0x0
1981 OPC_Decode, 219, 5, 35, // 4023: decode to RETTri using decoder 35
1982 // 4023: }
1983 // 4023: } // switch Inst[13]
1984 // 4023: }
1985 58, 78, // 4027: case 0x3a: {
1986 OPC_SwitchField, 8, 6, // 4029: switch Inst[13:8] {
1987 16, 14, // 4032: case 0x10: {
1988 OPC_CheckPredicate, 1, // 4034: check predicate 1
1989 OPC_CheckField, 29, 1, 0, // 4036: check Inst[29] == 0x0
1990 OPC_CheckField, 5, 3, 0, // 4040: check Inst[7:5] == 0x0
1991 OPC_Decode, 208, 6, 80, // 4044: decode to TXCCrr using decoder 80
1992 // 4044: }
1993 32, 45, // 4048: case 0x20: {
1994 OPC_SwitchField, 0, 8, // 4050: switch Inst[7:0] {
1995 1, 12, // 4053: case 0x1: {
1996 OPC_CheckField, 25, 5, 8, // 4055: check Inst[29:25] == 0x8
1997 OPC_CheckField, 14, 5, 0, // 4059: check Inst[18:14] == 0x0
1998 OPC_Decode, 186, 6, 7, // 4063: decode to TA1 using decoder 7
1999 // 4063: }
2000 3, 12, // 4067: case 0x3: {
2001 OPC_CheckField, 25, 5, 8, // 4069: check Inst[29:25] == 0x8
2002 OPC_CheckField, 14, 5, 0, // 4073: check Inst[18:14] == 0x0
2003 OPC_Decode, 187, 6, 7, // 4077: decode to TA3 using decoder 7
2004 // 4077: }
2005 5, 0, // 4081: case 0x5: {
2006 OPC_CheckField, 25, 5, 8, // 4083: check Inst[29:25] == 0x8
2007 OPC_CheckField, 14, 5, 0, // 4087: check Inst[18:14] == 0x0
2008 OPC_Decode, 188, 6, 7, // 4091: decode to TA5 using decoder 7
2009 // 4091: }
2010 // 4091: } // switch Inst[7:0]
2011 // 4091: }
2012 48, 0, // 4095: case 0x30: {
2013 OPC_CheckPredicate, 1, // 4097: check predicate 1
2014 OPC_CheckField, 29, 1, 0, // 4099: check Inst[29] == 0x0
2015 OPC_Decode, 207, 6, 81, // 4103: decode to TXCCri using decoder 81
2016 // 4103: }
2017 // 4103: } // switch Inst[13:8]
2018 // 4103: }
2019 59, 41, // 4107: case 0x3b: {
2020 OPC_SwitchField, 13, 1, // 4109: switch Inst[13] {
2021 0, 26, // 4112: case 0x0: {
2022 OPC_CheckField, 5, 8, 0, // 4114: check Inst[12:5] == 0x0
2023 OPC_CheckField, 25, 5, 0, // 4118: check Inst[29:25] == 0x0
2024 OPC_Scope, 12, // 4122: try {
2025 OPC_CheckField, 0, 5, 0, // 4124: check Inst[4:0] == 0x0
2026 OPC_CheckField, 14, 5, 0, // 4128: check Inst[18:14] == 0x0
2027 OPC_Decode, 242, 3, 7, // 4132: decode to FLUSH using decoder 7
2028 // 4132: } else try {
2029 OPC_Decode, 245, 3, 34, // 4136: decode to FLUSHrr using decoder 34
2030 // 4136: }
2031 // 4136: }
2032 1, 0, // 4140: case 0x1: {
2033 OPC_CheckField, 25, 5, 0, // 4142: check Inst[29:25] == 0x0
2034 OPC_Decode, 244, 3, 35, // 4146: decode to FLUSHri using decoder 35
2035 // 4146: }
2036 // 4146: } // switch Inst[13]
2037 // 4146: }
2038 60, 19, // 4150: case 0x3c: {
2039 OPC_SwitchField, 13, 1, // 4152: switch Inst[13] {
2040 0, 8, // 4155: case 0x0: {
2041 OPC_CheckField, 5, 8, 0, // 4157: check Inst[12:5] == 0x0
2042 OPC_Decode, 223, 5, 11, // 4161: decode to SAVErr using decoder 11
2043 // 4161: }
2044 1, 0, // 4165: case 0x1: {
2045 OPC_Decode, 222, 5, 12, // 4167: decode to SAVEri using decoder 12
2046 // 4167: }
2047 // 4167: } // switch Inst[13]
2048 // 4167: }
2049 61, 19, // 4171: case 0x3d: {
2050 OPC_SwitchField, 13, 1, // 4173: switch Inst[13] {
2051 0, 8, // 4176: case 0x0: {
2052 OPC_CheckField, 5, 8, 0, // 4178: check Inst[12:5] == 0x0
2053 OPC_Decode, 215, 5, 11, // 4182: decode to RESTORErr using decoder 11
2054 // 4182: }
2055 1, 0, // 4186: case 0x1: {
2056 OPC_Decode, 214, 5, 12, // 4188: decode to RESTOREri using decoder 12
2057 // 4188: }
2058 // 4188: } // switch Inst[13]
2059 // 4188: }
2060 62, 56, // 4192: case 0x3e: {
2061 OPC_SwitchField, 13, 1, // 4194: switch Inst[13] {
2062 0, 45, // 4197: case 0x0: {
2063 OPC_CheckField, 5, 8, 0, // 4199: check Inst[12:5] == 0x0
2064 OPC_Scope, 35, // 4203: try {
2065 OPC_SwitchField, 25, 5, // 4205: switch Inst[29:25] {
2066 0, 14, // 4208: case 0x0: {
2067 OPC_CheckPredicate, 0, // 4210: check predicate 0
2068 OPC_CheckField, 14, 5, 0, // 4212: check Inst[18:14] == 0x0
2069 OPC_CheckField, 0, 5, 0, // 4216: check Inst[4:0] == 0x0
2070 OPC_Decode, 179, 3, 7, // 4220: decode to DONE using decoder 7
2071 // 4220: }
2072 1, 0, // 4224: case 0x1: {
2073 OPC_CheckPredicate, 0, // 4226: check predicate 0
2074 OPC_CheckField, 14, 5, 0, // 4228: check Inst[18:14] == 0x0
2075 OPC_CheckField, 0, 5, 0, // 4232: check Inst[4:0] == 0x0
2076 OPC_Decode, 218, 5, 7, // 4236: decode to RETRY using decoder 7
2077 // 4236: }
2078 // 4236: } // switch Inst[29:25]
2079 // 4236: } else try {
2080 OPC_Decode, 216, 6, 11, // 4240: decode to UMACrr using decoder 11
2081 // 4240: }
2082 // 4240: }
2083 1, 0, // 4244: case 0x1: {
2084 OPC_Decode, 215, 6, 12, // 4246: decode to UMACri using decoder 12
2085 // 4246: }
2086 // 4246: } // switch Inst[13]
2087 // 4246: }
2088 63, 0, // 4250: case 0x3f: {
2089 OPC_SwitchField, 13, 1, // 4252: switch Inst[13] {
2090 0, 8, // 4255: case 0x0: {
2091 OPC_CheckField, 5, 8, 0, // 4257: check Inst[12:5] == 0x0
2092 OPC_Decode, 242, 5, 11, // 4261: decode to SMACrr using decoder 11
2093 // 4261: }
2094 1, 0, // 4265: case 0x1: {
2095 OPC_Decode, 241, 5, 12, // 4267: decode to SMACri using decoder 12
2096 // 4267: }
2097 // 4267: } // switch Inst[13]
2098 // 4267: }
2099 // 4267: } // switch Inst[24:19]
2100 // 4267: }
2101 3, 0, // 4271: case 0x3: {
2102 OPC_SwitchField, 19, 6, // 4273: switch Inst[24:19] {
2103 0, 19, // 4276: case 0x0: {
2104 OPC_SwitchField, 13, 1, // 4278: switch Inst[13] {
2105 0, 8, // 4281: case 0x0: {
2106 OPC_CheckField, 5, 8, 0, // 4283: check Inst[12:5] == 0x0
2107 OPC_Decode, 163, 5, 11, // 4287: decode to LDrr using decoder 11
2108 // 4287: }
2109 1, 0, // 4291: case 0x1: {
2110 OPC_Decode, 162, 5, 12, // 4293: decode to LDri using decoder 12
2111 // 4293: }
2112 // 4293: } // switch Inst[13]
2113 // 4293: }
2114 1, 19, // 4297: case 0x1: {
2115 OPC_SwitchField, 13, 1, // 4299: switch Inst[13] {
2116 0, 8, // 4302: case 0x0: {
2117 OPC_CheckField, 5, 8, 0, // 4304: check Inst[12:5] == 0x0
2118 OPC_Decode, 151, 5, 11, // 4308: decode to LDUBrr using decoder 11
2119 // 4308: }
2120 1, 0, // 4312: case 0x1: {
2121 OPC_Decode, 150, 5, 12, // 4314: decode to LDUBri using decoder 12
2122 // 4314: }
2123 // 4314: } // switch Inst[13]
2124 // 4314: }
2125 2, 19, // 4318: case 0x2: {
2126 OPC_SwitchField, 13, 1, // 4320: switch Inst[13] {
2127 0, 8, // 4323: case 0x0: {
2128 OPC_CheckField, 5, 8, 0, // 4325: check Inst[12:5] == 0x0
2129 OPC_Decode, 155, 5, 11, // 4329: decode to LDUHrr using decoder 11
2130 // 4329: }
2131 1, 0, // 4333: case 0x1: {
2132 OPC_Decode, 154, 5, 12, // 4335: decode to LDUHri using decoder 12
2133 // 4335: }
2134 // 4335: } // switch Inst[13]
2135 // 4335: }
2136 3, 19, // 4339: case 0x3: {
2137 OPC_SwitchField, 13, 1, // 4341: switch Inst[13] {
2138 0, 8, // 4344: case 0x0: {
2139 OPC_CheckField, 5, 8, 0, // 4346: check Inst[12:5] == 0x0
2140 OPC_Decode, 249, 4, 82, // 4350: decode to LDDrr using decoder 82
2141 // 4350: }
2142 1, 0, // 4354: case 0x1: {
2143 OPC_Decode, 248, 4, 83, // 4356: decode to LDDri using decoder 83
2144 // 4356: }
2145 // 4356: } // switch Inst[13]
2146 // 4356: }
2147 4, 19, // 4360: case 0x4: {
2148 OPC_SwitchField, 13, 1, // 4362: switch Inst[13] {
2149 0, 8, // 4365: case 0x0: {
2150 OPC_CheckField, 5, 8, 0, // 4367: check Inst[12:5] == 0x0
2151 OPC_Decode, 173, 6, 84, // 4371: decode to STrr using decoder 84
2152 // 4371: }
2153 1, 0, // 4375: case 0x1: {
2154 OPC_Decode, 172, 6, 85, // 4377: decode to STri using decoder 85
2155 // 4377: }
2156 // 4377: } // switch Inst[13]
2157 // 4377: }
2158 5, 19, // 4381: case 0x5: {
2159 OPC_SwitchField, 13, 1, // 4383: switch Inst[13] {
2160 0, 8, // 4386: case 0x0: {
2161 OPC_CheckField, 5, 8, 0, // 4388: check Inst[12:5] == 0x0
2162 OPC_Decode, 133, 6, 84, // 4392: decode to STBrr using decoder 84
2163 // 4392: }
2164 1, 0, // 4396: case 0x1: {
2165 OPC_Decode, 132, 6, 85, // 4398: decode to STBri using decoder 85
2166 // 4398: }
2167 // 4398: } // switch Inst[13]
2168 // 4398: }
2169 6, 19, // 4402: case 0x6: {
2170 OPC_SwitchField, 13, 1, // 4404: switch Inst[13] {
2171 0, 8, // 4407: case 0x0: {
2172 OPC_CheckField, 5, 8, 0, // 4409: check Inst[12:5] == 0x0
2173 OPC_Decode, 161, 6, 84, // 4413: decode to STHrr using decoder 84
2174 // 4413: }
2175 1, 0, // 4417: case 0x1: {
2176 OPC_Decode, 160, 6, 85, // 4419: decode to STHri using decoder 85
2177 // 4419: }
2178 // 4419: } // switch Inst[13]
2179 // 4419: }
2180 7, 19, // 4423: case 0x7: {
2181 OPC_SwitchField, 13, 1, // 4425: switch Inst[13] {
2182 0, 8, // 4428: case 0x0: {
2183 OPC_CheckField, 5, 8, 0, // 4430: check Inst[12:5] == 0x0
2184 OPC_Decode, 151, 6, 86, // 4434: decode to STDrr using decoder 86
2185 // 4434: }
2186 1, 0, // 4438: case 0x1: {
2187 OPC_Decode, 150, 6, 87, // 4440: decode to STDri using decoder 87
2188 // 4440: }
2189 // 4440: } // switch Inst[13]
2190 // 4440: }
2191 8, 23, // 4444: case 0x8: {
2192 OPC_SwitchField, 13, 1, // 4446: switch Inst[13] {
2193 0, 10, // 4449: case 0x0: {
2194 OPC_CheckPredicate, 0, // 4451: check predicate 0
2195 OPC_CheckField, 5, 8, 0, // 4453: check Inst[12:5] == 0x0
2196 OPC_Decode, 147, 5, 88, // 4457: decode to LDSWrr using decoder 88
2197 // 4457: }
2198 1, 0, // 4461: case 0x1: {
2199 OPC_CheckPredicate, 0, // 4463: check predicate 0
2200 OPC_Decode, 146, 5, 89, // 4465: decode to LDSWri using decoder 89
2201 // 4465: }
2202 // 4465: } // switch Inst[13]
2203 // 4465: }
2204 9, 19, // 4469: case 0x9: {
2205 OPC_SwitchField, 13, 1, // 4471: switch Inst[13] {
2206 0, 8, // 4474: case 0x0: {
2207 OPC_CheckField, 5, 8, 0, // 4476: check Inst[12:5] == 0x0
2208 OPC_Decode, 135, 5, 11, // 4480: decode to LDSBrr using decoder 11
2209 // 4480: }
2210 1, 0, // 4484: case 0x1: {
2211 OPC_Decode, 134, 5, 12, // 4486: decode to LDSBri using decoder 12
2212 // 4486: }
2213 // 4486: } // switch Inst[13]
2214 // 4486: }
2215 10, 19, // 4490: case 0xa: {
2216 OPC_SwitchField, 13, 1, // 4492: switch Inst[13] {
2217 0, 8, // 4495: case 0x0: {
2218 OPC_CheckField, 5, 8, 0, // 4497: check Inst[12:5] == 0x0
2219 OPC_Decode, 139, 5, 11, // 4501: decode to LDSHrr using decoder 11
2220 // 4501: }
2221 1, 0, // 4505: case 0x1: {
2222 OPC_Decode, 138, 5, 12, // 4507: decode to LDSHri using decoder 12
2223 // 4507: }
2224 // 4507: } // switch Inst[13]
2225 // 4507: }
2226 11, 23, // 4511: case 0xb: {
2227 OPC_SwitchField, 13, 1, // 4513: switch Inst[13] {
2228 0, 10, // 4516: case 0x0: {
2229 OPC_CheckPredicate, 0, // 4518: check predicate 0
2230 OPC_CheckField, 5, 8, 0, // 4520: check Inst[12:5] == 0x0
2231 OPC_Decode, 161, 5, 88, // 4524: decode to LDXrr using decoder 88
2232 // 4524: }
2233 1, 0, // 4528: case 0x1: {
2234 OPC_CheckPredicate, 0, // 4530: check predicate 0
2235 OPC_Decode, 160, 5, 89, // 4532: decode to LDXri using decoder 89
2236 // 4532: }
2237 // 4532: } // switch Inst[13]
2238 // 4532: }
2239 13, 19, // 4536: case 0xd: {
2240 OPC_SwitchField, 13, 1, // 4538: switch Inst[13] {
2241 0, 8, // 4541: case 0x0: {
2242 OPC_CheckField, 5, 8, 0, // 4543: check Inst[12:5] == 0x0
2243 OPC_Decode, 143, 5, 11, // 4547: decode to LDSTUBrr using decoder 11
2244 // 4547: }
2245 1, 0, // 4551: case 0x1: {
2246 OPC_Decode, 142, 5, 12, // 4553: decode to LDSTUBri using decoder 12
2247 // 4553: }
2248 // 4553: } // switch Inst[13]
2249 // 4553: }
2250 14, 23, // 4557: case 0xe: {
2251 OPC_SwitchField, 13, 1, // 4559: switch Inst[13] {
2252 0, 10, // 4562: case 0x0: {
2253 OPC_CheckPredicate, 0, // 4564: check predicate 0
2254 OPC_CheckField, 5, 8, 0, // 4566: check Inst[12:5] == 0x0
2255 OPC_Decode, 171, 6, 90, // 4570: decode to STXrr using decoder 90
2256 // 4570: }
2257 1, 0, // 4574: case 0x1: {
2258 OPC_CheckPredicate, 0, // 4576: check predicate 0
2259 OPC_Decode, 170, 6, 91, // 4578: decode to STXri using decoder 91
2260 // 4578: }
2261 // 4578: } // switch Inst[13]
2262 // 4578: }
2263 15, 19, // 4582: case 0xf: {
2264 OPC_SwitchField, 13, 1, // 4584: switch Inst[13] {
2265 0, 8, // 4587: case 0x0: {
2266 OPC_CheckField, 5, 8, 0, // 4589: check Inst[12:5] == 0x0
2267 OPC_Decode, 185, 6, 92, // 4593: decode to SWAPrr using decoder 92
2268 // 4593: }
2269 1, 0, // 4597: case 0x1: {
2270 OPC_Decode, 184, 6, 93, // 4599: decode to SWAPri using decoder 93
2271 // 4599: }
2272 // 4599: } // switch Inst[13]
2273 // 4599: }
2274 16, 17, // 4603: case 0x10: {
2275 OPC_SwitchField, 13, 1, // 4605: switch Inst[13] {
2276 0, 4, // 4608: case 0x0: {
2277 OPC_Decode, 235, 4, 94, // 4610: decode to LDArr using decoder 94
2278 // 4610: }
2279 1, 0, // 4614: case 0x1: {
2280 OPC_CheckPredicate, 0, // 4616: check predicate 0
2281 OPC_Decode, 234, 4, 12, // 4618: decode to LDAri using decoder 12
2282 // 4618: }
2283 // 4618: } // switch Inst[13]
2284 // 4618: }
2285 17, 17, // 4622: case 0x11: {
2286 OPC_SwitchField, 13, 1, // 4624: switch Inst[13] {
2287 0, 4, // 4627: case 0x0: {
2288 OPC_Decode, 149, 5, 94, // 4629: decode to LDUBArr using decoder 94
2289 // 4629: }
2290 1, 0, // 4633: case 0x1: {
2291 OPC_CheckPredicate, 0, // 4635: check predicate 0
2292 OPC_Decode, 148, 5, 12, // 4637: decode to LDUBAri using decoder 12
2293 // 4637: }
2294 // 4637: } // switch Inst[13]
2295 // 4637: }
2296 18, 17, // 4641: case 0x12: {
2297 OPC_SwitchField, 13, 1, // 4643: switch Inst[13] {
2298 0, 4, // 4646: case 0x0: {
2299 OPC_Decode, 153, 5, 94, // 4648: decode to LDUHArr using decoder 94
2300 // 4648: }
2301 1, 0, // 4652: case 0x1: {
2302 OPC_CheckPredicate, 0, // 4654: check predicate 0
2303 OPC_Decode, 152, 5, 12, // 4656: decode to LDUHAri using decoder 12
2304 // 4656: }
2305 // 4656: } // switch Inst[13]
2306 // 4656: }
2307 19, 17, // 4660: case 0x13: {
2308 OPC_SwitchField, 13, 1, // 4662: switch Inst[13] {
2309 0, 4, // 4665: case 0x0: {
2310 OPC_Decode, 241, 4, 95, // 4667: decode to LDDArr using decoder 95
2311 // 4667: }
2312 1, 0, // 4671: case 0x1: {
2313 OPC_CheckPredicate, 0, // 4673: check predicate 0
2314 OPC_Decode, 240, 4, 83, // 4675: decode to LDDAri using decoder 83
2315 // 4675: }
2316 // 4675: } // switch Inst[13]
2317 // 4675: }
2318 20, 17, // 4679: case 0x14: {
2319 OPC_SwitchField, 13, 1, // 4681: switch Inst[13] {
2320 0, 4, // 4684: case 0x0: {
2321 OPC_Decode, 128, 6, 96, // 4686: decode to STArr using decoder 96
2322 // 4686: }
2323 1, 0, // 4690: case 0x1: {
2324 OPC_CheckPredicate, 0, // 4692: check predicate 0
2325 OPC_Decode, 255, 5, 85, // 4694: decode to STAri using decoder 85
2326 // 4694: }
2327 // 4694: } // switch Inst[13]
2328 // 4694: }
2329 21, 17, // 4698: case 0x15: {
2330 OPC_SwitchField, 13, 1, // 4700: switch Inst[13] {
2331 0, 4, // 4703: case 0x0: {
2332 OPC_Decode, 131, 6, 96, // 4705: decode to STBArr using decoder 96
2333 // 4705: }
2334 1, 0, // 4709: case 0x1: {
2335 OPC_CheckPredicate, 0, // 4711: check predicate 0
2336 OPC_Decode, 130, 6, 85, // 4713: decode to STBAri using decoder 85
2337 // 4713: }
2338 // 4713: } // switch Inst[13]
2339 // 4713: }
2340 22, 17, // 4717: case 0x16: {
2341 OPC_SwitchField, 13, 1, // 4719: switch Inst[13] {
2342 0, 4, // 4722: case 0x0: {
2343 OPC_Decode, 159, 6, 96, // 4724: decode to STHArr using decoder 96
2344 // 4724: }
2345 1, 0, // 4728: case 0x1: {
2346 OPC_CheckPredicate, 0, // 4730: check predicate 0
2347 OPC_Decode, 158, 6, 85, // 4732: decode to STHAri using decoder 85
2348 // 4732: }
2349 // 4732: } // switch Inst[13]
2350 // 4732: }
2351 23, 17, // 4736: case 0x17: {
2352 OPC_SwitchField, 13, 1, // 4738: switch Inst[13] {
2353 0, 4, // 4741: case 0x0: {
2354 OPC_Decode, 139, 6, 97, // 4743: decode to STDArr using decoder 97
2355 // 4743: }
2356 1, 0, // 4747: case 0x1: {
2357 OPC_CheckPredicate, 0, // 4749: check predicate 0
2358 OPC_Decode, 138, 6, 87, // 4751: decode to STDAri using decoder 87
2359 // 4751: }
2360 // 4751: } // switch Inst[13]
2361 // 4751: }
2362 24, 19, // 4755: case 0x18: {
2363 OPC_SwitchField, 13, 1, // 4757: switch Inst[13] {
2364 0, 6, // 4760: case 0x0: {
2365 OPC_CheckPredicate, 0, // 4762: check predicate 0
2366 OPC_Decode, 145, 5, 98, // 4764: decode to LDSWArr using decoder 98
2367 // 4764: }
2368 1, 0, // 4768: case 0x1: {
2369 OPC_CheckPredicate, 0, // 4770: check predicate 0
2370 OPC_Decode, 144, 5, 89, // 4772: decode to LDSWAri using decoder 89
2371 // 4772: }
2372 // 4772: } // switch Inst[13]
2373 // 4772: }
2374 25, 17, // 4776: case 0x19: {
2375 OPC_SwitchField, 13, 1, // 4778: switch Inst[13] {
2376 0, 4, // 4781: case 0x0: {
2377 OPC_Decode, 133, 5, 94, // 4783: decode to LDSBArr using decoder 94
2378 // 4783: }
2379 1, 0, // 4787: case 0x1: {
2380 OPC_CheckPredicate, 0, // 4789: check predicate 0
2381 OPC_Decode, 132, 5, 12, // 4791: decode to LDSBAri using decoder 12
2382 // 4791: }
2383 // 4791: } // switch Inst[13]
2384 // 4791: }
2385 26, 17, // 4795: case 0x1a: {
2386 OPC_SwitchField, 13, 1, // 4797: switch Inst[13] {
2387 0, 4, // 4800: case 0x0: {
2388 OPC_Decode, 137, 5, 94, // 4802: decode to LDSHArr using decoder 94
2389 // 4802: }
2390 1, 0, // 4806: case 0x1: {
2391 OPC_CheckPredicate, 0, // 4808: check predicate 0
2392 OPC_Decode, 136, 5, 12, // 4810: decode to LDSHAri using decoder 12
2393 // 4810: }
2394 // 4810: } // switch Inst[13]
2395 // 4810: }
2396 27, 19, // 4814: case 0x1b: {
2397 OPC_SwitchField, 13, 1, // 4816: switch Inst[13] {
2398 0, 6, // 4819: case 0x0: {
2399 OPC_CheckPredicate, 0, // 4821: check predicate 0
2400 OPC_Decode, 157, 5, 98, // 4823: decode to LDXArr using decoder 98
2401 // 4823: }
2402 1, 0, // 4827: case 0x1: {
2403 OPC_CheckPredicate, 0, // 4829: check predicate 0
2404 OPC_Decode, 156, 5, 89, // 4831: decode to LDXAri using decoder 89
2405 // 4831: }
2406 // 4831: } // switch Inst[13]
2407 // 4831: }
2408 29, 17, // 4835: case 0x1d: {
2409 OPC_SwitchField, 13, 1, // 4837: switch Inst[13] {
2410 0, 4, // 4840: case 0x0: {
2411 OPC_Decode, 141, 5, 94, // 4842: decode to LDSTUBArr using decoder 94
2412 // 4842: }
2413 1, 0, // 4846: case 0x1: {
2414 OPC_CheckPredicate, 0, // 4848: check predicate 0
2415 OPC_Decode, 140, 5, 12, // 4850: decode to LDSTUBAri using decoder 12
2416 // 4850: }
2417 // 4850: } // switch Inst[13]
2418 // 4850: }
2419 30, 19, // 4854: case 0x1e: {
2420 OPC_SwitchField, 13, 1, // 4856: switch Inst[13] {
2421 0, 6, // 4859: case 0x0: {
2422 OPC_CheckPredicate, 0, // 4861: check predicate 0
2423 OPC_Decode, 167, 6, 99, // 4863: decode to STXArr using decoder 99
2424 // 4863: }
2425 1, 0, // 4867: case 0x1: {
2426 OPC_CheckPredicate, 0, // 4869: check predicate 0
2427 OPC_Decode, 166, 6, 91, // 4871: decode to STXAri using decoder 91
2428 // 4871: }
2429 // 4871: } // switch Inst[13]
2430 // 4871: }
2431 31, 17, // 4875: case 0x1f: {
2432 OPC_SwitchField, 13, 1, // 4877: switch Inst[13] {
2433 0, 4, // 4880: case 0x0: {
2434 OPC_Decode, 183, 6, 100, // 4882: decode to SWAPArr using decoder 100
2435 // 4882: }
2436 1, 0, // 4886: case 0x1: {
2437 OPC_CheckPredicate, 0, // 4888: check predicate 0
2438 OPC_Decode, 182, 6, 93, // 4890: decode to SWAPAri using decoder 93
2439 // 4890: }
2440 // 4890: } // switch Inst[13]
2441 // 4890: }
2442 32, 19, // 4894: case 0x20: {
2443 OPC_SwitchField, 13, 1, // 4896: switch Inst[13] {
2444 0, 8, // 4899: case 0x0: {
2445 OPC_CheckField, 5, 8, 0, // 4901: check Inst[12:5] == 0x0
2446 OPC_Decode, 255, 4, 101, // 4905: decode to LDFrr using decoder 101
2447 // 4905: }
2448 1, 0, // 4909: case 0x1: {
2449 OPC_Decode, 254, 4, 102, // 4911: decode to LDFri using decoder 102
2450 // 4911: }
2451 // 4911: } // switch Inst[13]
2452 // 4911: }
2453 33, 49, // 4915: case 0x21: {
2454 OPC_SwitchField, 13, 1, // 4917: switch Inst[13] {
2455 0, 25, // 4920: case 0x0: {
2456 OPC_SwitchField, 25, 5, // 4922: switch Inst[29:25] {
2457 0, 8, // 4925: case 0x0: {
2458 OPC_CheckField, 5, 8, 0, // 4927: check Inst[12:5] == 0x0
2459 OPC_Decode, 253, 4, 34, // 4931: decode to LDFSRrr using decoder 34
2460 // 4931: }
2461 1, 0, // 4935: case 0x1: {
2462 OPC_CheckPredicate, 0, // 4937: check predicate 0
2463 OPC_CheckField, 5, 8, 0, // 4939: check Inst[12:5] == 0x0
2464 OPC_Decode, 159, 5, 34, // 4943: decode to LDXFSRrr using decoder 34
2465 // 4943: }
2466 // 4943: } // switch Inst[29:25]
2467 // 4943: }
2468 1, 0, // 4947: case 0x1: {
2469 OPC_SwitchField, 25, 5, // 4949: switch Inst[29:25] {
2470 0, 4, // 4952: case 0x0: {
2471 OPC_Decode, 252, 4, 35, // 4954: decode to LDFSRri using decoder 35
2472 // 4954: }
2473 1, 0, // 4958: case 0x1: {
2474 OPC_CheckPredicate, 0, // 4960: check predicate 0
2475 OPC_Decode, 158, 5, 35, // 4962: decode to LDXFSRri using decoder 35
2476 // 4962: }
2477 // 4962: } // switch Inst[29:25]
2478 // 4962: }
2479 // 4962: } // switch Inst[13]
2480 // 4962: }
2481 35, 19, // 4966: case 0x23: {
2482 OPC_SwitchField, 13, 1, // 4968: switch Inst[13] {
2483 0, 8, // 4971: case 0x0: {
2484 OPC_CheckField, 5, 8, 0, // 4973: check Inst[12:5] == 0x0
2485 OPC_Decode, 247, 4, 103, // 4977: decode to LDDFrr using decoder 103
2486 // 4977: }
2487 1, 0, // 4981: case 0x1: {
2488 OPC_Decode, 246, 4, 104, // 4983: decode to LDDFri using decoder 104
2489 // 4983: }
2490 // 4983: } // switch Inst[13]
2491 // 4983: }
2492 36, 19, // 4987: case 0x24: {
2493 OPC_SwitchField, 13, 1, // 4989: switch Inst[13] {
2494 0, 8, // 4992: case 0x0: {
2495 OPC_CheckField, 5, 8, 0, // 4994: check Inst[12:5] == 0x0
2496 OPC_Decode, 157, 6, 105, // 4998: decode to STFrr using decoder 105
2497 // 4998: }
2498 1, 0, // 5002: case 0x1: {
2499 OPC_Decode, 156, 6, 106, // 5004: decode to STFri using decoder 106
2500 // 5004: }
2501 // 5004: } // switch Inst[13]
2502 // 5004: }
2503 37, 49, // 5008: case 0x25: {
2504 OPC_SwitchField, 13, 1, // 5010: switch Inst[13] {
2505 0, 25, // 5013: case 0x0: {
2506 OPC_SwitchField, 25, 5, // 5015: switch Inst[29:25] {
2507 0, 8, // 5018: case 0x0: {
2508 OPC_CheckField, 5, 8, 0, // 5020: check Inst[12:5] == 0x0
2509 OPC_Decode, 155, 6, 34, // 5024: decode to STFSRrr using decoder 34
2510 // 5024: }
2511 1, 0, // 5028: case 0x1: {
2512 OPC_CheckPredicate, 0, // 5030: check predicate 0
2513 OPC_CheckField, 5, 8, 0, // 5032: check Inst[12:5] == 0x0
2514 OPC_Decode, 169, 6, 34, // 5036: decode to STXFSRrr using decoder 34
2515 // 5036: }
2516 // 5036: } // switch Inst[29:25]
2517 // 5036: }
2518 1, 0, // 5040: case 0x1: {
2519 OPC_SwitchField, 25, 5, // 5042: switch Inst[29:25] {
2520 0, 4, // 5045: case 0x0: {
2521 OPC_Decode, 154, 6, 35, // 5047: decode to STFSRri using decoder 35
2522 // 5047: }
2523 1, 0, // 5051: case 0x1: {
2524 OPC_CheckPredicate, 0, // 5053: check predicate 0
2525 OPC_Decode, 168, 6, 35, // 5055: decode to STXFSRri using decoder 35
2526 // 5055: }
2527 // 5055: } // switch Inst[29:25]
2528 // 5055: }
2529 // 5055: } // switch Inst[13]
2530 // 5055: }
2531 38, 27, // 5059: case 0x26: {
2532 OPC_SwitchField, 13, 1, // 5061: switch Inst[13] {
2533 0, 12, // 5064: case 0x0: {
2534 OPC_CheckField, 25, 5, 0, // 5066: check Inst[29:25] == 0x0
2535 OPC_CheckField, 5, 8, 0, // 5070: check Inst[12:5] == 0x0
2536 OPC_Decode, 147, 6, 34, // 5074: decode to STDFQrr using decoder 34
2537 // 5074: }
2538 1, 0, // 5078: case 0x1: {
2539 OPC_CheckField, 25, 5, 0, // 5080: check Inst[29:25] == 0x0
2540 OPC_Decode, 146, 6, 35, // 5084: decode to STDFQri using decoder 35
2541 // 5084: }
2542 // 5084: } // switch Inst[13]
2543 // 5084: }
2544 39, 19, // 5088: case 0x27: {
2545 OPC_SwitchField, 13, 1, // 5090: switch Inst[13] {
2546 0, 8, // 5093: case 0x0: {
2547 OPC_CheckField, 5, 8, 0, // 5095: check Inst[12:5] == 0x0
2548 OPC_Decode, 149, 6, 107, // 5099: decode to STDFrr using decoder 107
2549 // 5099: }
2550 1, 0, // 5103: case 0x1: {
2551 OPC_Decode, 148, 6, 108, // 5105: decode to STDFri using decoder 108
2552 // 5105: }
2553 // 5105: } // switch Inst[13]
2554 // 5105: }
2555 45, 23, // 5109: case 0x2d: {
2556 OPC_SwitchField, 13, 1, // 5111: switch Inst[13] {
2557 0, 10, // 5114: case 0x0: {
2558 OPC_CheckPredicate, 0, // 5116: check predicate 0
2559 OPC_CheckField, 5, 8, 0, // 5118: check Inst[12:5] == 0x0
2560 OPC_Decode, 204, 5, 109, // 5122: decode to PREFETCHr using decoder 109
2561 // 5122: }
2562 1, 0, // 5126: case 0x1: {
2563 OPC_CheckPredicate, 0, // 5128: check predicate 0
2564 OPC_Decode, 203, 5, 110, // 5130: decode to PREFETCHi using decoder 110
2565 // 5130: }
2566 // 5130: } // switch Inst[13]
2567 // 5130: }
2568 49, 27, // 5134: case 0x31: {
2569 OPC_SwitchField, 13, 1, // 5136: switch Inst[13] {
2570 0, 12, // 5139: case 0x0: {
2571 OPC_CheckField, 25, 5, 0, // 5141: check Inst[29:25] == 0x0
2572 OPC_CheckField, 5, 8, 0, // 5145: check Inst[12:5] == 0x0
2573 OPC_Decode, 237, 4, 34, // 5149: decode to LDCSRrr using decoder 34
2574 // 5149: }
2575 1, 0, // 5153: case 0x1: {
2576 OPC_CheckField, 25, 5, 0, // 5155: check Inst[29:25] == 0x0
2577 OPC_Decode, 236, 4, 35, // 5159: decode to LDCSRri using decoder 35
2578 // 5159: }
2579 // 5159: } // switch Inst[13]
2580 // 5159: }
2581 53, 27, // 5163: case 0x35: {
2582 OPC_SwitchField, 13, 1, // 5165: switch Inst[13] {
2583 0, 12, // 5168: case 0x0: {
2584 OPC_CheckField, 25, 5, 0, // 5170: check Inst[29:25] == 0x0
2585 OPC_CheckField, 5, 8, 0, // 5174: check Inst[12:5] == 0x0
2586 OPC_Decode, 135, 6, 34, // 5178: decode to STCSRrr using decoder 34
2587 // 5178: }
2588 1, 0, // 5182: case 0x1: {
2589 OPC_CheckField, 25, 5, 0, // 5184: check Inst[29:25] == 0x0
2590 OPC_Decode, 134, 6, 35, // 5188: decode to STCSRri using decoder 35
2591 // 5188: }
2592 // 5188: } // switch Inst[13]
2593 // 5188: }
2594 54, 27, // 5192: case 0x36: {
2595 OPC_SwitchField, 13, 1, // 5194: switch Inst[13] {
2596 0, 12, // 5197: case 0x0: {
2597 OPC_CheckField, 25, 5, 0, // 5199: check Inst[29:25] == 0x0
2598 OPC_CheckField, 5, 8, 0, // 5203: check Inst[12:5] == 0x0
2599 OPC_Decode, 141, 6, 34, // 5207: decode to STDCQrr using decoder 34
2600 // 5207: }
2601 1, 0, // 5211: case 0x1: {
2602 OPC_CheckField, 25, 5, 0, // 5213: check Inst[29:25] == 0x0
2603 OPC_Decode, 140, 6, 35, // 5217: decode to STDCQri using decoder 35
2604 // 5217: }
2605 // 5217: } // switch Inst[13]
2606 // 5217: }
2607 60, 23, // 5221: case 0x3c: {
2608 OPC_SwitchField, 13, 1, // 5223: switch Inst[13] {
2609 0, 6, // 5226: case 0x0: {
2610 OPC_CheckPredicate, 10, // 5228: check predicate 10
2611 OPC_Decode, 162, 3, 111, // 5230: decode to CASArr using decoder 111
2612 // 5230: }
2613 1, 0, // 5234: case 0x1: {
2614 OPC_CheckPredicate, 0, // 5236: check predicate 0
2615 OPC_CheckField, 5, 8, 0, // 5238: check Inst[12:5] == 0x0
2616 OPC_Decode, 161, 3, 92, // 5242: decode to CASAri using decoder 92
2617 // 5242: }
2618 // 5242: } // switch Inst[13]
2619 // 5242: }
2620 61, 19, // 5246: case 0x3d: {
2621 OPC_SwitchField, 13, 1, // 5248: switch Inst[13] {
2622 0, 6, // 5251: case 0x0: {
2623 OPC_CheckPredicate, 0, // 5253: check predicate 0
2624 OPC_Decode, 202, 5, 112, // 5255: decode to PREFETCHAr using decoder 112
2625 // 5255: }
2626 1, 0, // 5259: case 0x1: {
2627 OPC_CheckPredicate, 0, // 5261: check predicate 0
2628 OPC_Decode, 201, 5, 110, // 5263: decode to PREFETCHAi using decoder 110
2629 // 5263: }
2630 // 5263: } // switch Inst[13]
2631 // 5263: }
2632 62, 0, // 5267: case 0x3e: {
2633 OPC_SwitchField, 13, 1, // 5269: switch Inst[13] {
2634 0, 6, // 5272: case 0x0: {
2635 OPC_CheckPredicate, 0, // 5274: check predicate 0
2636 OPC_Decode, 164, 3, 113, // 5276: decode to CASXArr using decoder 113
2637 // 5276: }
2638 1, 0, // 5280: case 0x1: {
2639 OPC_CheckPredicate, 0, // 5282: check predicate 0
2640 OPC_CheckField, 5, 8, 0, // 5284: check Inst[12:5] == 0x0
2641 OPC_Decode, 163, 3, 114, // 5288: decode to CASXAri using decoder 114
2642 // 5288: }
2643 // 5288: } // switch Inst[13]
2644 // 5288: }
2645 // 5288: } // switch Inst[24:19]
2646 // 5288: }
2647 // 5288: } // switch Inst[31:30]
2648};
2649static const uint8_t DecoderTableSparcV832[148] = {
2650 OPC_SwitchField, 19, 6, // 0: switch Inst[24:19] {
2651 48, 27, // 3: case 0x30: {
2652 OPC_SwitchField, 13, 1, // 5: switch Inst[13] {
2653 0, 12, // 8: case 0x0: {
2654 OPC_CheckField, 30, 2, 3, // 10: check Inst[31:30] == 0x3
2655 OPC_CheckField, 5, 8, 0, // 14: check Inst[12:5] == 0x0
2656 OPC_Decode, 239, 4, 115, // 18: decode to LDCrr using decoder 115
2657 // 18: }
2658 1, 0, // 22: case 0x1: {
2659 OPC_CheckField, 30, 2, 3, // 24: check Inst[31:30] == 0x3
2660 OPC_Decode, 238, 4, 116, // 28: decode to LDCri using decoder 116
2661 // 28: }
2662 // 28: } // switch Inst[13]
2663 // 28: }
2664 51, 27, // 32: case 0x33: {
2665 OPC_SwitchField, 13, 1, // 34: switch Inst[13] {
2666 0, 12, // 37: case 0x0: {
2667 OPC_CheckField, 30, 2, 3, // 39: check Inst[31:30] == 0x3
2668 OPC_CheckField, 5, 8, 0, // 43: check Inst[12:5] == 0x0
2669 OPC_Decode, 243, 4, 117, // 47: decode to LDDCrr using decoder 117
2670 // 47: }
2671 1, 0, // 51: case 0x1: {
2672 OPC_CheckField, 30, 2, 3, // 53: check Inst[31:30] == 0x3
2673 OPC_Decode, 242, 4, 118, // 57: decode to LDDCri using decoder 118
2674 // 57: }
2675 // 57: } // switch Inst[13]
2676 // 57: }
2677 52, 27, // 61: case 0x34: {
2678 OPC_SwitchField, 13, 1, // 63: switch Inst[13] {
2679 0, 12, // 66: case 0x0: {
2680 OPC_CheckField, 30, 2, 3, // 68: check Inst[31:30] == 0x3
2681 OPC_CheckField, 5, 8, 0, // 72: check Inst[12:5] == 0x0
2682 OPC_Decode, 137, 6, 119, // 76: decode to STCrr using decoder 119
2683 // 76: }
2684 1, 0, // 80: case 0x1: {
2685 OPC_CheckField, 30, 2, 3, // 82: check Inst[31:30] == 0x3
2686 OPC_Decode, 136, 6, 120, // 86: decode to STCri using decoder 120
2687 // 86: }
2688 // 86: } // switch Inst[13]
2689 // 86: }
2690 55, 27, // 90: case 0x37: {
2691 OPC_SwitchField, 13, 1, // 92: switch Inst[13] {
2692 0, 12, // 95: case 0x0: {
2693 OPC_CheckField, 30, 2, 3, // 97: check Inst[31:30] == 0x3
2694 OPC_CheckField, 5, 8, 0, // 101: check Inst[12:5] == 0x0
2695 OPC_Decode, 143, 6, 121, // 105: decode to STDCrr using decoder 121
2696 // 105: }
2697 1, 0, // 109: case 0x1: {
2698 OPC_CheckField, 30, 2, 3, // 111: check Inst[31:30] == 0x3
2699 OPC_Decode, 142, 6, 122, // 115: decode to STDCri using decoder 122
2700 // 115: }
2701 // 115: } // switch Inst[13]
2702 // 115: }
2703 58, 0, // 119: case 0x3a: {
2704 OPC_SwitchField, 8, 6, // 121: switch Inst[13:8] {
2705 0, 12, // 124: case 0x0: {
2706 OPC_CheckField, 29, 3, 4, // 126: check Inst[31:29] == 0x4
2707 OPC_CheckField, 5, 3, 0, // 130: check Inst[7:5] == 0x0
2708 OPC_Decode, 202, 6, 80, // 134: decode to TRAPrr using decoder 80
2709 // 134: }
2710 32, 0, // 138: case 0x20: {
2711 OPC_CheckField, 29, 3, 4, // 140: check Inst[31:29] == 0x4
2712 OPC_Decode, 201, 6, 81, // 144: decode to TRAPri using decoder 81
2713 // 144: }
2714 // 144: } // switch Inst[13:8]
2715 // 144: }
2716 // 144: } // switch Inst[24:19]
2717};
2718static const uint8_t DecoderTableSparcV932[281] = {
2719 OPC_SwitchField, 19, 6, // 0: switch Inst[24:19] {
2720 34, 31, // 3: case 0x22: {
2721 OPC_SwitchField, 13, 1, // 5: switch Inst[13] {
2722 0, 14, // 8: case 0x0: {
2723 OPC_CheckPredicate, 0, // 10: check predicate 0
2724 OPC_CheckField, 30, 2, 3, // 12: check Inst[31:30] == 0x3
2725 OPC_CheckField, 5, 8, 0, // 16: check Inst[12:5] == 0x0
2726 OPC_Decode, 131, 5, 123, // 20: decode to LDQFrr using decoder 123
2727 // 20: }
2728 1, 0, // 24: case 0x1: {
2729 OPC_CheckPredicate, 0, // 26: check predicate 0
2730 OPC_CheckField, 30, 2, 3, // 28: check Inst[31:30] == 0x3
2731 OPC_Decode, 130, 5, 124, // 32: decode to LDQFri using decoder 124
2732 // 32: }
2733 // 32: } // switch Inst[13]
2734 // 32: }
2735 38, 31, // 36: case 0x26: {
2736 OPC_SwitchField, 13, 1, // 38: switch Inst[13] {
2737 0, 14, // 41: case 0x0: {
2738 OPC_CheckPredicate, 0, // 43: check predicate 0
2739 OPC_CheckField, 30, 2, 3, // 45: check Inst[31:30] == 0x3
2740 OPC_CheckField, 5, 8, 0, // 49: check Inst[12:5] == 0x0
2741 OPC_Decode, 165, 6, 125, // 53: decode to STQFrr using decoder 125
2742 // 53: }
2743 1, 0, // 57: case 0x1: {
2744 OPC_CheckPredicate, 0, // 59: check predicate 0
2745 OPC_CheckField, 30, 2, 3, // 61: check Inst[31:30] == 0x3
2746 OPC_Decode, 164, 6, 126, // 65: decode to STQFri using decoder 126
2747 // 65: }
2748 // 65: } // switch Inst[13]
2749 // 65: }
2750 48, 27, // 69: case 0x30: {
2751 OPC_SwitchField, 13, 1, // 71: switch Inst[13] {
2752 0, 10, // 74: case 0x0: {
2753 OPC_CheckPredicate, 0, // 76: check predicate 0
2754 OPC_CheckField, 30, 2, 3, // 78: check Inst[31:30] == 0x3
2755 OPC_Decode, 251, 4, 127, // 82: decode to LDFArr using decoder 127
2756 // 82: }
2757 1, 0, // 86: case 0x1: {
2758 OPC_CheckPredicate, 0, // 88: check predicate 0
2759 OPC_CheckField, 30, 2, 3, // 90: check Inst[31:30] == 0x3
2760 OPC_Decode, 250, 4, 102, // 94: decode to LDFAri using decoder 102
2761 // 94: }
2762 // 94: } // switch Inst[13]
2763 // 94: }
2764 50, 28, // 98: case 0x32: {
2765 OPC_SwitchField, 13, 1, // 100: switch Inst[13] {
2766 0, 11, // 103: case 0x0: {
2767 OPC_CheckPredicate, 0, // 105: check predicate 0
2768 OPC_CheckField, 30, 2, 3, // 107: check Inst[31:30] == 0x3
2769 OPC_Decode, 129, 5, 128, 1, // 111: decode to LDQFArr using decoder 128
2770 // 111: }
2771 1, 0, // 116: case 0x1: {
2772 OPC_CheckPredicate, 0, // 118: check predicate 0
2773 OPC_CheckField, 30, 2, 3, // 120: check Inst[31:30] == 0x3
2774 OPC_Decode, 128, 5, 124, // 124: decode to LDQFAri using decoder 124
2775 // 124: }
2776 // 124: } // switch Inst[13]
2777 // 124: }
2778 51, 28, // 128: case 0x33: {
2779 OPC_SwitchField, 13, 1, // 130: switch Inst[13] {
2780 0, 11, // 133: case 0x0: {
2781 OPC_CheckPredicate, 0, // 135: check predicate 0
2782 OPC_CheckField, 30, 2, 3, // 137: check Inst[31:30] == 0x3
2783 OPC_Decode, 245, 4, 129, 1, // 141: decode to LDDFArr using decoder 129
2784 // 141: }
2785 1, 0, // 146: case 0x1: {
2786 OPC_CheckPredicate, 0, // 148: check predicate 0
2787 OPC_CheckField, 30, 2, 3, // 150: check Inst[31:30] == 0x3
2788 OPC_Decode, 244, 4, 104, // 154: decode to LDDFAri using decoder 104
2789 // 154: }
2790 // 154: } // switch Inst[13]
2791 // 154: }
2792 52, 28, // 158: case 0x34: {
2793 OPC_SwitchField, 13, 1, // 160: switch Inst[13] {
2794 0, 11, // 163: case 0x0: {
2795 OPC_CheckPredicate, 0, // 165: check predicate 0
2796 OPC_CheckField, 30, 2, 3, // 167: check Inst[31:30] == 0x3
2797 OPC_Decode, 153, 6, 130, 1, // 171: decode to STFArr using decoder 130
2798 // 171: }
2799 1, 0, // 176: case 0x1: {
2800 OPC_CheckPredicate, 0, // 178: check predicate 0
2801 OPC_CheckField, 30, 2, 3, // 180: check Inst[31:30] == 0x3
2802 OPC_Decode, 152, 6, 106, // 184: decode to STFAri using decoder 106
2803 // 184: }
2804 // 184: } // switch Inst[13]
2805 // 184: }
2806 54, 28, // 188: case 0x36: {
2807 OPC_SwitchField, 13, 1, // 190: switch Inst[13] {
2808 0, 11, // 193: case 0x0: {
2809 OPC_CheckPredicate, 0, // 195: check predicate 0
2810 OPC_CheckField, 30, 2, 3, // 197: check Inst[31:30] == 0x3
2811 OPC_Decode, 163, 6, 131, 1, // 201: decode to STQFArr using decoder 131
2812 // 201: }
2813 1, 0, // 206: case 0x1: {
2814 OPC_CheckPredicate, 0, // 208: check predicate 0
2815 OPC_CheckField, 30, 2, 3, // 210: check Inst[31:30] == 0x3
2816 OPC_Decode, 162, 6, 126, // 214: decode to STQFAri using decoder 126
2817 // 214: }
2818 // 214: } // switch Inst[13]
2819 // 214: }
2820 55, 28, // 218: case 0x37: {
2821 OPC_SwitchField, 13, 1, // 220: switch Inst[13] {
2822 0, 11, // 223: case 0x0: {
2823 OPC_CheckPredicate, 0, // 225: check predicate 0
2824 OPC_CheckField, 30, 2, 3, // 227: check Inst[31:30] == 0x3
2825 OPC_Decode, 145, 6, 132, 1, // 231: decode to STDFArr using decoder 132
2826 // 231: }
2827 1, 0, // 236: case 0x1: {
2828 OPC_CheckPredicate, 0, // 238: check predicate 0
2829 OPC_CheckField, 30, 2, 3, // 240: check Inst[31:30] == 0x3
2830 OPC_Decode, 144, 6, 108, // 244: decode to STDFAri using decoder 108
2831 // 244: }
2832 // 244: } // switch Inst[13]
2833 // 244: }
2834 58, 0, // 248: case 0x3a: {
2835 OPC_SwitchField, 8, 6, // 250: switch Inst[13:8] {
2836 0, 14, // 253: case 0x0: {
2837 OPC_CheckPredicate, 0, // 255: check predicate 0
2838 OPC_CheckField, 29, 3, 4, // 257: check Inst[31:29] == 0x4
2839 OPC_CheckField, 5, 3, 0, // 261: check Inst[7:5] == 0x0
2840 OPC_Decode, 196, 6, 80, // 265: decode to TICCrr using decoder 80
2841 // 265: }
2842 32, 0, // 269: case 0x20: {
2843 OPC_CheckPredicate, 0, // 271: check predicate 0
2844 OPC_CheckField, 29, 3, 4, // 273: check Inst[31:29] == 0x4
2845 OPC_Decode, 195, 6, 81, // 277: decode to TICCri using decoder 81
2846 // 277: }
2847 // 277: } // switch Inst[13:8]
2848 // 277: }
2849 // 277: } // switch Inst[24:19]
2850};
2851// Handling 133 cases.
2852template <typename InsnType>
2853static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
2854 DecodeComplete = true;
2855 using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
2856 TmpType tmp;
2857 switch (Idx) {
2858 default: llvm_unreachable("Invalid decoder index!");
2859 case 0:
2860 tmp = fieldFromInstruction(insn, 0, 22);
2861 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2862 return S;
2863 case 1:
2864 tmp = fieldFromInstruction(insn, 0, 19);
2865 if (!Check(S, DecodeDisp<19>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2866 tmp = fieldFromInstruction(insn, 25, 4);
2867 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2868 return S;
2869 case 2:
2870 tmp = fieldFromInstruction(insn, 0, 22);
2871 if (!Check(S, DecodeDisp<22>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2872 return S;
2873 case 3:
2874 tmp = fieldFromInstruction(insn, 0, 22);
2875 if (!Check(S, DecodeDisp<22>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2876 tmp = fieldFromInstruction(insn, 25, 4);
2877 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2878 return S;
2879 case 4:
2880 tmp = 0x0;
2881 tmp |= fieldFromInstruction(insn, 0, 14);
2882 tmp |= fieldFromInstruction(insn, 20, 2) << 14;
2883 if (!Check(S, DecodeDisp<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2884 tmp = fieldFromInstruction(insn, 25, 3);
2885 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2886 tmp = fieldFromInstruction(insn, 14, 5);
2887 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2888 return S;
2889 case 5:
2890 tmp = 0x0;
2891 tmp |= fieldFromInstruction(insn, 5, 8);
2892 tmp |= fieldFromInstruction(insn, 19, 2) << 8;
2893 if (!Check(S, DecodeDisp<10>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2894 tmp = 0x0;
2895 tmp |= fieldFromInstruction(insn, 25, 3);
2896 tmp |= fieldFromInstruction(insn, 29, 1) << 3;
2897 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2898 tmp = fieldFromInstruction(insn, 14, 5);
2899 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2900 tmp = fieldFromInstruction(insn, 0, 5);
2901 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2902 return S;
2903 case 6:
2904 tmp = 0x0;
2905 tmp |= fieldFromInstruction(insn, 5, 8);
2906 tmp |= fieldFromInstruction(insn, 19, 2) << 8;
2907 if (!Check(S, DecodeDisp<10>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2908 tmp = 0x0;
2909 tmp |= fieldFromInstruction(insn, 25, 3);
2910 tmp |= fieldFromInstruction(insn, 29, 1) << 3;
2911 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2912 tmp = fieldFromInstruction(insn, 14, 5);
2913 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2914 tmp = fieldFromInstruction(insn, 0, 5);
2915 if (!Check(S, DecodeSIMM5(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2916 return S;
2917 case 7:
2918 return S;
2919 case 8:
2920 tmp = fieldFromInstruction(insn, 25, 5);
2921 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2922 tmp = fieldFromInstruction(insn, 0, 22);
2923 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2924 return S;
2925 case 9:
2926 tmp = fieldFromInstruction(insn, 0, 19);
2927 if (!Check(S, DecodeDisp<19>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2928 tmp = fieldFromInstruction(insn, 25, 4);
2929 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2930 tmp = fieldFromInstruction(insn, 20, 2);
2931 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2932 return S;
2933 case 10:
2934 tmp = fieldFromInstruction(insn, 0, 30);
2935 if (!Check(S, DecodeCall(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2936 return S;
2937 case 11:
2938 tmp = fieldFromInstruction(insn, 25, 5);
2939 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2940 tmp = fieldFromInstruction(insn, 14, 5);
2941 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2942 tmp = fieldFromInstruction(insn, 0, 5);
2943 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2944 return S;
2945 case 12:
2946 tmp = fieldFromInstruction(insn, 25, 5);
2947 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2948 tmp = fieldFromInstruction(insn, 14, 5);
2949 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2950 tmp = fieldFromInstruction(insn, 0, 13);
2951 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2952 return S;
2953 case 13:
2954 tmp = fieldFromInstruction(insn, 25, 5);
2955 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2956 tmp = fieldFromInstruction(insn, 14, 5);
2957 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2958 tmp = fieldFromInstruction(insn, 0, 5);
2959 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2960 return S;
2961 case 14:
2962 tmp = fieldFromInstruction(insn, 25, 5);
2963 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2964 tmp = fieldFromInstruction(insn, 14, 5);
2965 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2966 tmp = fieldFromInstruction(insn, 0, 13);
2967 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2968 return S;
2969 case 15:
2970 tmp = fieldFromInstruction(insn, 25, 5);
2971 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2972 tmp = fieldFromInstruction(insn, 14, 5);
2973 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2974 tmp = fieldFromInstruction(insn, 0, 5);
2975 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2976 tmp = fieldFromInstruction(insn, 9, 5);
2977 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2978 return S;
2979 case 16:
2980 tmp = fieldFromInstruction(insn, 25, 5);
2981 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2982 tmp = fieldFromInstruction(insn, 14, 5);
2983 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2984 tmp = fieldFromInstruction(insn, 0, 5);
2985 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2986 tmp = fieldFromInstruction(insn, 9, 5);
2987 if (!Check(S, DecodeSIMM5(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2988 return S;
2989 case 17:
2990 tmp = fieldFromInstruction(insn, 25, 5);
2991 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2992 tmp = fieldFromInstruction(insn, 14, 5);
2993 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2994 tmp = fieldFromInstruction(insn, 0, 5);
2995 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2996 return S;
2997 case 18:
2998 tmp = fieldFromInstruction(insn, 25, 5);
2999 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3000 tmp = fieldFromInstruction(insn, 14, 5);
3001 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3002 tmp = fieldFromInstruction(insn, 0, 6);
3003 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3004 return S;
3005 case 19:
3006 tmp = fieldFromInstruction(insn, 25, 5);
3007 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3008 tmp = fieldFromInstruction(insn, 14, 5);
3009 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3010 tmp = fieldFromInstruction(insn, 0, 6);
3011 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3012 return S;
3013 case 20:
3014 tmp = fieldFromInstruction(insn, 25, 5);
3015 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3016 tmp = fieldFromInstruction(insn, 14, 5);
3017 if (!Check(S, DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3018 return S;
3019 case 21:
3020 tmp = fieldFromInstruction(insn, 0, 13);
3021 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3022 return S;
3023 case 22:
3024 tmp = fieldFromInstruction(insn, 25, 5);
3025 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3026 return S;
3027 case 23:
3028 tmp = fieldFromInstruction(insn, 25, 5);
3029 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3030 tmp = fieldFromInstruction(insn, 14, 5);
3031 if (!Check(S, DecodePRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3032 return S;
3033 case 24:
3034 tmp = fieldFromInstruction(insn, 25, 5);
3035 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3036 tmp = fieldFromInstruction(insn, 0, 5);
3037 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3038 tmp = fieldFromInstruction(insn, 25, 5);
3039 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3040 tmp = fieldFromInstruction(insn, 14, 4);
3041 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3042 return S;
3043 case 25:
3044 tmp = fieldFromInstruction(insn, 25, 5);
3045 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3046 tmp = fieldFromInstruction(insn, 11, 2);
3047 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3048 tmp = fieldFromInstruction(insn, 0, 5);
3049 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3050 tmp = fieldFromInstruction(insn, 25, 5);
3051 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3052 tmp = fieldFromInstruction(insn, 14, 4);
3053 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3054 return S;
3055 case 26:
3056 tmp = fieldFromInstruction(insn, 25, 5);
3057 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3058 tmp = fieldFromInstruction(insn, 0, 11);
3059 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3060 tmp = fieldFromInstruction(insn, 25, 5);
3061 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3062 tmp = fieldFromInstruction(insn, 14, 4);
3063 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3064 return S;
3065 case 27:
3066 tmp = fieldFromInstruction(insn, 25, 5);
3067 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3068 tmp = fieldFromInstruction(insn, 11, 2);
3069 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3070 tmp = fieldFromInstruction(insn, 0, 11);
3071 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3072 tmp = fieldFromInstruction(insn, 25, 5);
3073 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3074 tmp = fieldFromInstruction(insn, 14, 4);
3075 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3076 return S;
3077 case 28:
3078 tmp = fieldFromInstruction(insn, 25, 5);
3079 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3080 tmp = fieldFromInstruction(insn, 0, 5);
3081 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3082 return S;
3083 case 29:
3084 tmp = fieldFromInstruction(insn, 25, 5);
3085 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3086 tmp = fieldFromInstruction(insn, 14, 5);
3087 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3088 tmp = fieldFromInstruction(insn, 0, 5);
3089 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3090 tmp = fieldFromInstruction(insn, 25, 5);
3091 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3092 tmp = fieldFromInstruction(insn, 10, 3);
3093 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3094 return S;
3095 case 30:
3096 tmp = fieldFromInstruction(insn, 25, 5);
3097 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3098 tmp = fieldFromInstruction(insn, 14, 5);
3099 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3100 tmp = fieldFromInstruction(insn, 0, 10);
3101 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3102 tmp = fieldFromInstruction(insn, 25, 5);
3103 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3104 tmp = fieldFromInstruction(insn, 10, 3);
3105 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3106 return S;
3107 case 31:
3108 tmp = fieldFromInstruction(insn, 25, 5);
3109 if (!Check(S, DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3110 tmp = fieldFromInstruction(insn, 14, 5);
3111 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3112 tmp = fieldFromInstruction(insn, 0, 5);
3113 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3114 return S;
3115 case 32:
3116 tmp = fieldFromInstruction(insn, 0, 13);
3117 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3118 return S;
3119 case 33:
3120 tmp = fieldFromInstruction(insn, 25, 5);
3121 if (!Check(S, DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3122 tmp = fieldFromInstruction(insn, 14, 5);
3123 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3124 tmp = fieldFromInstruction(insn, 0, 13);
3125 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3126 return S;
3127 case 34:
3128 tmp = fieldFromInstruction(insn, 14, 5);
3129 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3130 tmp = fieldFromInstruction(insn, 0, 5);
3131 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3132 return S;
3133 case 35:
3134 tmp = fieldFromInstruction(insn, 14, 5);
3135 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3136 tmp = fieldFromInstruction(insn, 0, 13);
3137 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3138 return S;
3139 case 36:
3140 tmp = fieldFromInstruction(insn, 25, 5);
3141 if (!Check(S, DecodePRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3142 tmp = fieldFromInstruction(insn, 14, 5);
3143 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3144 tmp = fieldFromInstruction(insn, 0, 5);
3145 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3146 return S;
3147 case 37:
3148 tmp = fieldFromInstruction(insn, 25, 5);
3149 if (!Check(S, DecodePRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3150 tmp = fieldFromInstruction(insn, 14, 5);
3151 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3152 tmp = fieldFromInstruction(insn, 0, 13);
3153 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3154 return S;
3155 case 38:
3156 tmp = fieldFromInstruction(insn, 25, 5);
3157 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3158 tmp = fieldFromInstruction(insn, 0, 5);
3159 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3160 return S;
3161 case 39:
3162 tmp = fieldFromInstruction(insn, 25, 5);
3163 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3164 tmp = fieldFromInstruction(insn, 0, 5);
3165 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3166 return S;
3167 case 40:
3168 tmp = fieldFromInstruction(insn, 25, 5);
3169 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3170 tmp = fieldFromInstruction(insn, 0, 5);
3171 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3172 return S;
3173 case 41:
3174 tmp = fieldFromInstruction(insn, 25, 5);
3175 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3176 tmp = fieldFromInstruction(insn, 14, 5);
3177 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3178 tmp = fieldFromInstruction(insn, 0, 5);
3179 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3180 return S;
3181 case 42:
3182 tmp = fieldFromInstruction(insn, 25, 5);
3183 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3184 tmp = fieldFromInstruction(insn, 14, 5);
3185 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3186 tmp = fieldFromInstruction(insn, 0, 5);
3187 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3188 return S;
3189 case 43:
3190 tmp = fieldFromInstruction(insn, 25, 5);
3191 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3192 tmp = fieldFromInstruction(insn, 14, 5);
3193 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3194 tmp = fieldFromInstruction(insn, 0, 5);
3195 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3196 return S;
3197 case 44:
3198 tmp = fieldFromInstruction(insn, 25, 5);
3199 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3200 tmp = fieldFromInstruction(insn, 14, 5);
3201 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3202 tmp = fieldFromInstruction(insn, 0, 5);
3203 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3204 return S;
3205 case 45:
3206 tmp = fieldFromInstruction(insn, 25, 5);
3207 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3208 tmp = fieldFromInstruction(insn, 14, 5);
3209 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3210 tmp = fieldFromInstruction(insn, 0, 5);
3211 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3212 return S;
3213 case 46:
3214 tmp = fieldFromInstruction(insn, 25, 5);
3215 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3216 tmp = fieldFromInstruction(insn, 0, 5);
3217 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3218 return S;
3219 case 47:
3220 tmp = fieldFromInstruction(insn, 25, 5);
3221 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3222 tmp = fieldFromInstruction(insn, 0, 5);
3223 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3224 return S;
3225 case 48:
3226 tmp = fieldFromInstruction(insn, 25, 5);
3227 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3228 tmp = fieldFromInstruction(insn, 0, 5);
3229 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3230 return S;
3231 case 49:
3232 tmp = fieldFromInstruction(insn, 25, 5);
3233 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3234 tmp = fieldFromInstruction(insn, 0, 5);
3235 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3236 return S;
3237 case 50:
3238 tmp = fieldFromInstruction(insn, 25, 5);
3239 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3240 tmp = fieldFromInstruction(insn, 0, 5);
3241 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3242 return S;
3243 case 51:
3244 tmp = fieldFromInstruction(insn, 25, 5);
3245 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3246 tmp = fieldFromInstruction(insn, 0, 5);
3247 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3248 return S;
3249 case 52:
3250 tmp = fieldFromInstruction(insn, 25, 5);
3251 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3252 tmp = fieldFromInstruction(insn, 0, 5);
3253 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3254 tmp = fieldFromInstruction(insn, 25, 5);
3255 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3256 tmp = fieldFromInstruction(insn, 14, 4);
3257 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3258 return S;
3259 case 53:
3260 tmp = fieldFromInstruction(insn, 25, 5);
3261 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3262 tmp = fieldFromInstruction(insn, 11, 2);
3263 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3264 tmp = fieldFromInstruction(insn, 0, 5);
3265 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3266 tmp = fieldFromInstruction(insn, 25, 5);
3267 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3268 tmp = fieldFromInstruction(insn, 14, 4);
3269 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3270 return S;
3271 case 54:
3272 tmp = fieldFromInstruction(insn, 25, 5);
3273 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3274 tmp = fieldFromInstruction(insn, 0, 5);
3275 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3276 tmp = fieldFromInstruction(insn, 25, 5);
3277 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3278 tmp = fieldFromInstruction(insn, 14, 4);
3279 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3280 return S;
3281 case 55:
3282 tmp = fieldFromInstruction(insn, 25, 5);
3283 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3284 tmp = fieldFromInstruction(insn, 11, 2);
3285 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3286 tmp = fieldFromInstruction(insn, 0, 5);
3287 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3288 tmp = fieldFromInstruction(insn, 25, 5);
3289 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3290 tmp = fieldFromInstruction(insn, 14, 4);
3291 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3292 return S;
3293 case 56:
3294 tmp = fieldFromInstruction(insn, 25, 5);
3295 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3296 tmp = fieldFromInstruction(insn, 0, 5);
3297 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3298 tmp = fieldFromInstruction(insn, 25, 5);
3299 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3300 tmp = fieldFromInstruction(insn, 14, 4);
3301 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3302 return S;
3303 case 57:
3304 tmp = fieldFromInstruction(insn, 25, 5);
3305 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3306 tmp = fieldFromInstruction(insn, 11, 2);
3307 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3308 tmp = fieldFromInstruction(insn, 0, 5);
3309 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3310 tmp = fieldFromInstruction(insn, 25, 5);
3311 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3312 tmp = fieldFromInstruction(insn, 14, 4);
3313 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3314 return S;
3315 case 58:
3316 tmp = fieldFromInstruction(insn, 25, 5);
3317 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3318 tmp = fieldFromInstruction(insn, 14, 5);
3319 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3320 tmp = fieldFromInstruction(insn, 0, 5);
3321 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3322 tmp = fieldFromInstruction(insn, 25, 5);
3323 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3324 tmp = fieldFromInstruction(insn, 10, 3);
3325 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3326 return S;
3327 case 59:
3328 tmp = fieldFromInstruction(insn, 25, 5);
3329 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3330 tmp = fieldFromInstruction(insn, 14, 5);
3331 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3332 tmp = fieldFromInstruction(insn, 0, 5);
3333 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3334 tmp = fieldFromInstruction(insn, 25, 5);
3335 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3336 tmp = fieldFromInstruction(insn, 10, 3);
3337 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3338 return S;
3339 case 60:
3340 tmp = fieldFromInstruction(insn, 25, 5);
3341 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3342 tmp = fieldFromInstruction(insn, 14, 5);
3343 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3344 tmp = fieldFromInstruction(insn, 0, 5);
3345 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3346 tmp = fieldFromInstruction(insn, 25, 5);
3347 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3348 tmp = fieldFromInstruction(insn, 10, 3);
3349 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3350 return S;
3351 case 61:
3352 tmp = fieldFromInstruction(insn, 25, 5);
3353 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3354 tmp = fieldFromInstruction(insn, 14, 5);
3355 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3356 tmp = fieldFromInstruction(insn, 0, 5);
3357 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3358 return S;
3359 case 62:
3360 tmp = fieldFromInstruction(insn, 25, 5);
3361 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3362 tmp = fieldFromInstruction(insn, 14, 5);
3363 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3364 tmp = fieldFromInstruction(insn, 0, 5);
3365 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3366 return S;
3367 case 63:
3368 tmp = fieldFromInstruction(insn, 25, 5);
3369 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3370 tmp = fieldFromInstruction(insn, 14, 5);
3371 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3372 tmp = fieldFromInstruction(insn, 0, 5);
3373 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3374 return S;
3375 case 64:
3376 tmp = fieldFromInstruction(insn, 25, 5);
3377 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3378 tmp = fieldFromInstruction(insn, 0, 5);
3379 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3380 return S;
3381 case 65:
3382 tmp = fieldFromInstruction(insn, 0, 5);
3383 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3384 return S;
3385 case 66:
3386 tmp = fieldFromInstruction(insn, 25, 5);
3387 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3388 tmp = fieldFromInstruction(insn, 14, 5);
3389 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3390 tmp = fieldFromInstruction(insn, 0, 5);
3391 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3392 return S;
3393 case 67:
3394 tmp = fieldFromInstruction(insn, 25, 5);
3395 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3396 tmp = fieldFromInstruction(insn, 14, 5);
3397 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3398 tmp = fieldFromInstruction(insn, 0, 5);
3399 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3400 return S;
3401 case 68:
3402 tmp = fieldFromInstruction(insn, 25, 5);
3403 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3404 return S;
3405 case 69:
3406 tmp = fieldFromInstruction(insn, 25, 5);
3407 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3408 return S;
3409 case 70:
3410 tmp = fieldFromInstruction(insn, 25, 5);
3411 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3412 tmp = fieldFromInstruction(insn, 14, 5);
3413 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3414 return S;
3415 case 71:
3416 tmp = fieldFromInstruction(insn, 25, 5);
3417 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3418 tmp = fieldFromInstruction(insn, 14, 5);
3419 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3420 return S;
3421 case 72:
3422 tmp = fieldFromInstruction(insn, 0, 3);
3423 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3424 return S;
3425 case 73:
3426 tmp = fieldFromInstruction(insn, 25, 5);
3427 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3428 tmp = fieldFromInstruction(insn, 0, 5);
3429 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3430 return S;
3431 case 74:
3432 tmp = fieldFromInstruction(insn, 25, 5);
3433 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3434 tmp = fieldFromInstruction(insn, 0, 5);
3435 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3436 return S;
3437 case 75:
3438 tmp = fieldFromInstruction(insn, 25, 5);
3439 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3440 tmp = fieldFromInstruction(insn, 0, 5);
3441 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3442 return S;
3443 case 76:
3444 tmp = fieldFromInstruction(insn, 25, 5);
3445 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3446 tmp = fieldFromInstruction(insn, 0, 5);
3447 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3448 return S;
3449 case 77:
3450 tmp = fieldFromInstruction(insn, 25, 5);
3451 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3452 tmp = fieldFromInstruction(insn, 14, 5);
3453 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3454 tmp = fieldFromInstruction(insn, 0, 5);
3455 if (!Check(S, DecodeSIMM5(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3456 return S;
3457 case 78:
3458 tmp = fieldFromInstruction(insn, 0, 5);
3459 if (!Check(S, DecodeSIMM5(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3460 return S;
3461 case 79:
3462 tmp = fieldFromInstruction(insn, 25, 5);
3463 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3464 tmp = fieldFromInstruction(insn, 14, 5);
3465 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3466 tmp = fieldFromInstruction(insn, 0, 5);
3467 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3468 tmp = fieldFromInstruction(insn, 9, 5);
3469 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3470 return S;
3471 case 80:
3472 tmp = fieldFromInstruction(insn, 14, 5);
3473 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3474 tmp = fieldFromInstruction(insn, 0, 5);
3475 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3476 tmp = fieldFromInstruction(insn, 25, 4);
3477 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3478 return S;
3479 case 81:
3480 tmp = fieldFromInstruction(insn, 14, 5);
3481 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3482 tmp = fieldFromInstruction(insn, 0, 8);
3483 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3484 tmp = fieldFromInstruction(insn, 25, 4);
3485 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3486 return S;
3487 case 82:
3488 tmp = fieldFromInstruction(insn, 25, 5);
3489 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3490 tmp = fieldFromInstruction(insn, 14, 5);
3491 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3492 tmp = fieldFromInstruction(insn, 0, 5);
3493 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3494 return S;
3495 case 83:
3496 tmp = fieldFromInstruction(insn, 25, 5);
3497 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3498 tmp = fieldFromInstruction(insn, 14, 5);
3499 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3500 tmp = fieldFromInstruction(insn, 0, 13);
3501 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3502 return S;
3503 case 84:
3504 tmp = fieldFromInstruction(insn, 14, 5);
3505 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3506 tmp = fieldFromInstruction(insn, 0, 5);
3507 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3508 tmp = fieldFromInstruction(insn, 25, 5);
3509 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3510 return S;
3511 case 85:
3512 tmp = fieldFromInstruction(insn, 14, 5);
3513 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3514 tmp = fieldFromInstruction(insn, 0, 13);
3515 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3516 tmp = fieldFromInstruction(insn, 25, 5);
3517 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3518 return S;
3519 case 86:
3520 tmp = fieldFromInstruction(insn, 14, 5);
3521 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3522 tmp = fieldFromInstruction(insn, 0, 5);
3523 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3524 tmp = fieldFromInstruction(insn, 25, 5);
3525 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3526 return S;
3527 case 87:
3528 tmp = fieldFromInstruction(insn, 14, 5);
3529 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3530 tmp = fieldFromInstruction(insn, 0, 13);
3531 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3532 tmp = fieldFromInstruction(insn, 25, 5);
3533 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3534 return S;
3535 case 88:
3536 tmp = fieldFromInstruction(insn, 25, 5);
3537 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3538 tmp = fieldFromInstruction(insn, 14, 5);
3539 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3540 tmp = fieldFromInstruction(insn, 0, 5);
3541 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3542 return S;
3543 case 89:
3544 tmp = fieldFromInstruction(insn, 25, 5);
3545 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3546 tmp = fieldFromInstruction(insn, 14, 5);
3547 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3548 tmp = fieldFromInstruction(insn, 0, 13);
3549 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3550 return S;
3551 case 90:
3552 tmp = fieldFromInstruction(insn, 14, 5);
3553 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3554 tmp = fieldFromInstruction(insn, 0, 5);
3555 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3556 tmp = fieldFromInstruction(insn, 25, 5);
3557 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3558 return S;
3559 case 91:
3560 tmp = fieldFromInstruction(insn, 14, 5);
3561 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3562 tmp = fieldFromInstruction(insn, 0, 13);
3563 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3564 tmp = fieldFromInstruction(insn, 25, 5);
3565 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3566 return S;
3567 case 92:
3568 tmp = fieldFromInstruction(insn, 25, 5);
3569 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3570 tmp = fieldFromInstruction(insn, 14, 5);
3571 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3572 tmp = fieldFromInstruction(insn, 0, 5);
3573 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3574 tmp = fieldFromInstruction(insn, 25, 5);
3575 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3576 return S;
3577 case 93:
3578 tmp = fieldFromInstruction(insn, 25, 5);
3579 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3580 tmp = fieldFromInstruction(insn, 14, 5);
3581 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3582 tmp = fieldFromInstruction(insn, 0, 13);
3583 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3584 tmp = fieldFromInstruction(insn, 25, 5);
3585 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3586 return S;
3587 case 94:
3588 tmp = fieldFromInstruction(insn, 25, 5);
3589 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3590 tmp = fieldFromInstruction(insn, 14, 5);
3591 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3592 tmp = fieldFromInstruction(insn, 0, 5);
3593 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3594 tmp = fieldFromInstruction(insn, 5, 8);
3595 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3596 return S;
3597 case 95:
3598 tmp = fieldFromInstruction(insn, 25, 5);
3599 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3600 tmp = fieldFromInstruction(insn, 14, 5);
3601 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3602 tmp = fieldFromInstruction(insn, 0, 5);
3603 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3604 tmp = fieldFromInstruction(insn, 5, 8);
3605 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3606 return S;
3607 case 96:
3608 tmp = fieldFromInstruction(insn, 14, 5);
3609 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3610 tmp = fieldFromInstruction(insn, 0, 5);
3611 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3612 tmp = fieldFromInstruction(insn, 25, 5);
3613 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3614 tmp = fieldFromInstruction(insn, 5, 8);
3615 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3616 return S;
3617 case 97:
3618 tmp = fieldFromInstruction(insn, 14, 5);
3619 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3620 tmp = fieldFromInstruction(insn, 0, 5);
3621 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3622 tmp = fieldFromInstruction(insn, 25, 5);
3623 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3624 tmp = fieldFromInstruction(insn, 5, 8);
3625 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3626 return S;
3627 case 98:
3628 tmp = fieldFromInstruction(insn, 25, 5);
3629 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3630 tmp = fieldFromInstruction(insn, 14, 5);
3631 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3632 tmp = fieldFromInstruction(insn, 0, 5);
3633 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3634 tmp = fieldFromInstruction(insn, 5, 8);
3635 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3636 return S;
3637 case 99:
3638 tmp = fieldFromInstruction(insn, 14, 5);
3639 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3640 tmp = fieldFromInstruction(insn, 0, 5);
3641 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3642 tmp = fieldFromInstruction(insn, 25, 5);
3643 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3644 tmp = fieldFromInstruction(insn, 5, 8);
3645 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3646 return S;
3647 case 100:
3648 tmp = fieldFromInstruction(insn, 25, 5);
3649 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3650 tmp = fieldFromInstruction(insn, 14, 5);
3651 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3652 tmp = fieldFromInstruction(insn, 0, 5);
3653 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3654 tmp = fieldFromInstruction(insn, 5, 8);
3655 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3656 tmp = fieldFromInstruction(insn, 25, 5);
3657 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3658 return S;
3659 case 101:
3660 tmp = fieldFromInstruction(insn, 25, 5);
3661 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3662 tmp = fieldFromInstruction(insn, 14, 5);
3663 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3664 tmp = fieldFromInstruction(insn, 0, 5);
3665 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3666 return S;
3667 case 102:
3668 tmp = fieldFromInstruction(insn, 25, 5);
3669 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3670 tmp = fieldFromInstruction(insn, 14, 5);
3671 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3672 tmp = fieldFromInstruction(insn, 0, 13);
3673 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3674 return S;
3675 case 103:
3676 tmp = fieldFromInstruction(insn, 25, 5);
3677 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3678 tmp = fieldFromInstruction(insn, 14, 5);
3679 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3680 tmp = fieldFromInstruction(insn, 0, 5);
3681 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3682 return S;
3683 case 104:
3684 tmp = fieldFromInstruction(insn, 25, 5);
3685 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3686 tmp = fieldFromInstruction(insn, 14, 5);
3687 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3688 tmp = fieldFromInstruction(insn, 0, 13);
3689 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3690 return S;
3691 case 105:
3692 tmp = fieldFromInstruction(insn, 14, 5);
3693 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3694 tmp = fieldFromInstruction(insn, 0, 5);
3695 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3696 tmp = fieldFromInstruction(insn, 25, 5);
3697 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3698 return S;
3699 case 106:
3700 tmp = fieldFromInstruction(insn, 14, 5);
3701 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3702 tmp = fieldFromInstruction(insn, 0, 13);
3703 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3704 tmp = fieldFromInstruction(insn, 25, 5);
3705 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3706 return S;
3707 case 107:
3708 tmp = fieldFromInstruction(insn, 14, 5);
3709 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3710 tmp = fieldFromInstruction(insn, 0, 5);
3711 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3712 tmp = fieldFromInstruction(insn, 25, 5);
3713 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3714 return S;
3715 case 108:
3716 tmp = fieldFromInstruction(insn, 14, 5);
3717 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3718 tmp = fieldFromInstruction(insn, 0, 13);
3719 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3720 tmp = fieldFromInstruction(insn, 25, 5);
3721 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3722 return S;
3723 case 109:
3724 tmp = fieldFromInstruction(insn, 14, 5);
3725 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3726 tmp = fieldFromInstruction(insn, 0, 5);
3727 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3728 tmp = fieldFromInstruction(insn, 25, 5);
3729 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3730 return S;
3731 case 110:
3732 tmp = fieldFromInstruction(insn, 14, 5);
3733 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3734 tmp = fieldFromInstruction(insn, 0, 13);
3735 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3736 tmp = fieldFromInstruction(insn, 25, 5);
3737 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3738 return S;
3739 case 111:
3740 tmp = fieldFromInstruction(insn, 25, 5);
3741 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3742 tmp = fieldFromInstruction(insn, 14, 5);
3743 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3744 tmp = fieldFromInstruction(insn, 0, 5);
3745 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3746 tmp = fieldFromInstruction(insn, 25, 5);
3747 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3748 tmp = fieldFromInstruction(insn, 5, 8);
3749 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3750 return S;
3751 case 112:
3752 tmp = fieldFromInstruction(insn, 14, 5);
3753 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3754 tmp = fieldFromInstruction(insn, 0, 5);
3755 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3756 tmp = fieldFromInstruction(insn, 5, 8);
3757 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3758 tmp = fieldFromInstruction(insn, 25, 5);
3759 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3760 return S;
3761 case 113:
3762 tmp = fieldFromInstruction(insn, 25, 5);
3763 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3764 tmp = fieldFromInstruction(insn, 14, 5);
3765 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3766 tmp = fieldFromInstruction(insn, 0, 5);
3767 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3768 tmp = fieldFromInstruction(insn, 25, 5);
3769 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3770 tmp = fieldFromInstruction(insn, 5, 8);
3771 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3772 return S;
3773 case 114:
3774 tmp = fieldFromInstruction(insn, 25, 5);
3775 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3776 tmp = fieldFromInstruction(insn, 14, 5);
3777 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3778 tmp = fieldFromInstruction(insn, 0, 5);
3779 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3780 tmp = fieldFromInstruction(insn, 25, 5);
3781 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3782 return S;
3783 case 115:
3784 tmp = fieldFromInstruction(insn, 25, 5);
3785 if (!Check(S, DecodeCoprocRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3786 tmp = fieldFromInstruction(insn, 14, 5);
3787 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3788 tmp = fieldFromInstruction(insn, 0, 5);
3789 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3790 return S;
3791 case 116:
3792 tmp = fieldFromInstruction(insn, 25, 5);
3793 if (!Check(S, DecodeCoprocRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3794 tmp = fieldFromInstruction(insn, 14, 5);
3795 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3796 tmp = fieldFromInstruction(insn, 0, 13);
3797 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3798 return S;
3799 case 117:
3800 tmp = fieldFromInstruction(insn, 25, 5);
3801 if (!Check(S, DecodeCoprocPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3802 tmp = fieldFromInstruction(insn, 14, 5);
3803 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3804 tmp = fieldFromInstruction(insn, 0, 5);
3805 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3806 return S;
3807 case 118:
3808 tmp = fieldFromInstruction(insn, 25, 5);
3809 if (!Check(S, DecodeCoprocPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3810 tmp = fieldFromInstruction(insn, 14, 5);
3811 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3812 tmp = fieldFromInstruction(insn, 0, 13);
3813 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3814 return S;
3815 case 119:
3816 tmp = fieldFromInstruction(insn, 14, 5);
3817 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3818 tmp = fieldFromInstruction(insn, 0, 5);
3819 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3820 tmp = fieldFromInstruction(insn, 25, 5);
3821 if (!Check(S, DecodeCoprocRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3822 return S;
3823 case 120:
3824 tmp = fieldFromInstruction(insn, 14, 5);
3825 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3826 tmp = fieldFromInstruction(insn, 0, 13);
3827 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3828 tmp = fieldFromInstruction(insn, 25, 5);
3829 if (!Check(S, DecodeCoprocRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3830 return S;
3831 case 121:
3832 tmp = fieldFromInstruction(insn, 14, 5);
3833 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3834 tmp = fieldFromInstruction(insn, 0, 5);
3835 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3836 tmp = fieldFromInstruction(insn, 25, 5);
3837 if (!Check(S, DecodeCoprocPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3838 return S;
3839 case 122:
3840 tmp = fieldFromInstruction(insn, 14, 5);
3841 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3842 tmp = fieldFromInstruction(insn, 0, 13);
3843 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3844 tmp = fieldFromInstruction(insn, 25, 5);
3845 if (!Check(S, DecodeCoprocPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3846 return S;
3847 case 123:
3848 tmp = fieldFromInstruction(insn, 25, 5);
3849 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3850 tmp = fieldFromInstruction(insn, 14, 5);
3851 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3852 tmp = fieldFromInstruction(insn, 0, 5);
3853 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3854 return S;
3855 case 124:
3856 tmp = fieldFromInstruction(insn, 25, 5);
3857 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3858 tmp = fieldFromInstruction(insn, 14, 5);
3859 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3860 tmp = fieldFromInstruction(insn, 0, 13);
3861 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3862 return S;
3863 case 125:
3864 tmp = fieldFromInstruction(insn, 14, 5);
3865 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3866 tmp = fieldFromInstruction(insn, 0, 5);
3867 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3868 tmp = fieldFromInstruction(insn, 25, 5);
3869 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3870 return S;
3871 case 126:
3872 tmp = fieldFromInstruction(insn, 14, 5);
3873 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3874 tmp = fieldFromInstruction(insn, 0, 13);
3875 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3876 tmp = fieldFromInstruction(insn, 25, 5);
3877 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3878 return S;
3879 case 127:
3880 tmp = fieldFromInstruction(insn, 25, 5);
3881 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3882 tmp = fieldFromInstruction(insn, 14, 5);
3883 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3884 tmp = fieldFromInstruction(insn, 0, 5);
3885 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3886 tmp = fieldFromInstruction(insn, 5, 8);
3887 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3888 return S;
3889 case 128:
3890 tmp = fieldFromInstruction(insn, 25, 5);
3891 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3892 tmp = fieldFromInstruction(insn, 14, 5);
3893 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3894 tmp = fieldFromInstruction(insn, 0, 5);
3895 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3896 tmp = fieldFromInstruction(insn, 5, 8);
3897 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3898 return S;
3899 case 129:
3900 tmp = fieldFromInstruction(insn, 25, 5);
3901 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3902 tmp = fieldFromInstruction(insn, 14, 5);
3903 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3904 tmp = fieldFromInstruction(insn, 0, 5);
3905 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3906 tmp = fieldFromInstruction(insn, 5, 8);
3907 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3908 return S;
3909 case 130:
3910 tmp = fieldFromInstruction(insn, 14, 5);
3911 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3912 tmp = fieldFromInstruction(insn, 0, 5);
3913 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3914 tmp = fieldFromInstruction(insn, 25, 5);
3915 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3916 tmp = fieldFromInstruction(insn, 5, 8);
3917 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3918 return S;
3919 case 131:
3920 tmp = fieldFromInstruction(insn, 14, 5);
3921 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3922 tmp = fieldFromInstruction(insn, 0, 5);
3923 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3924 tmp = fieldFromInstruction(insn, 25, 5);
3925 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3926 tmp = fieldFromInstruction(insn, 5, 8);
3927 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3928 return S;
3929 case 132:
3930 tmp = fieldFromInstruction(insn, 14, 5);
3931 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3932 tmp = fieldFromInstruction(insn, 0, 5);
3933 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3934 tmp = fieldFromInstruction(insn, 25, 5);
3935 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3936 tmp = fieldFromInstruction(insn, 5, 8);
3937 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3938 return S;
3939 }
3940}
3941static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset &FB) {
3942 switch (Idx) {
3943 default: llvm_unreachable("Invalid index!");
3944 case 0:
3945 return FB[Sparc::FeatureV9];
3946 case 1:
3947 return FB[Sparc::Feature64Bit];
3948 case 2:
3949 return FB[Sparc::FeatureOSA2011];
3950 case 3:
3951 return FB[Sparc::FeatureCrypto];
3952 case 4:
3953 return FB[Sparc::FeaturePWRPSR];
3954 case 5:
3955 return FB[Sparc::FeatureUA2005];
3956 case 6:
3957 return FB[Sparc::FeatureVIS3];
3958 case 7:
3959 return FB[Sparc::FeatureVIS];
3960 case 8:
3961 return FB[Sparc::FeatureVIS2];
3962 case 9:
3963 return FB[Sparc::FeatureUA2007];
3964 case 10:
3965 return FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9];
3966 }
3967}
3968
3969
3970template <typename InsnType>
3971static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
3972 InsnType insn, uint64_t Address,
3973 const MCDisassembler *DisAsm,
3974 const MCSubtargetInfo &STI) {
3975 const FeatureBitset &Bits = STI.getFeatureBits();
3976 const uint8_t *Ptr = DecodeTable;
3977
3978 SmallVector<const uint8_t *, 8> ScopeStack;
3979 DecodeStatus S = MCDisassembler::Success;
3980 while (true) {
3981 ptrdiff_t Loc = Ptr - DecodeTable;
3982 const uint8_t DecoderOp = *Ptr++;
3983 switch (DecoderOp) {
3984 default:
3985 errs() << Loc << ": Unexpected decode table opcode: "
3986 << (int)DecoderOp << '\n';
3987 return MCDisassembler::Fail;
3988 case OPC_Scope: {
3989 unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr);
3990 const uint8_t *SkipTo = Ptr + NumToSkip;
3991 ScopeStack.push_back(Elt: SkipTo);
3992 LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
3993 << ")\n");
3994 continue;
3995 }
3996 case OPC_SwitchField: {
3997 // Decode the start value.
3998 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
3999 unsigned Len = *Ptr++;
4000 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
4001 uint64_t CaseValue;
4002 unsigned CaseSize;
4003 while (true) {
4004 CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr);
4005 CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr);
4006 if (FieldValue == CaseValue || !CaseSize)
4007 break;
4008 Ptr += CaseSize;
4009 }
4010 if (FieldValue == CaseValue) {
4011 LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
4012 << "): " << FieldValue << '\n');
4013 continue;
4014 }
4015 break;
4016 }
4017 case OPC_CheckField: {
4018 // Decode the start value.
4019 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
4020 unsigned Len = *Ptr;
4021 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
4022 // Decode the field value.
4023 unsigned PtrLen = 0;
4024 uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen);
4025 Ptr += PtrLen;
4026 bool Failed = ExpectedValue != FieldValue;
4027
4028 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
4029 << ", " << ExpectedValue << "): FieldValue = "
4030 << FieldValue << ", ExpectedValue = " << ExpectedValue
4031 << ": " << (Failed ? "FAIL, " : "PASS\n"););
4032 if (!Failed)
4033 continue;
4034 break;
4035 }
4036 case OPC_CheckPredicate: {
4037 // Decode the Predicate Index value.
4038 unsigned PIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
4039 // Check the predicate.
4040 bool Failed = !checkDecoderPredicate(Idx: PIdx, FB: Bits);
4041
4042 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate(" << PIdx << "): "
4043 << (Failed ? "FAIL, " : "PASS\n"););
4044 if (!Failed)
4045 continue;
4046 break;
4047 }
4048 case OPC_Decode: {
4049 // Decode the Opcode value.
4050 unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr);
4051 unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
4052
4053 MI.clear();
4054 MI.setOpcode(Opc);
4055 bool DecodeComplete;
4056 S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
4057 DecodeComplete);
4058 LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
4059 << ", using decoder " << DecodeIdx << ": "
4060 << (S ? "PASS, " : "FAIL, "));
4061
4062 if (DecodeComplete) {
4063 LLVM_DEBUG(dbgs() << "decoding complete\n");
4064 return S;
4065 }
4066 assert(S == MCDisassembler::Fail);
4067 // Reset decode status. This also drops a SoftFail status that could be
4068 // set before the decode attempt.
4069 S = MCDisassembler::Success;
4070 break;
4071 }
4072 }
4073 if (ScopeStack.empty()) {
4074 LLVM_DEBUG(dbgs() << "returning Fail\n");
4075 return MCDisassembler::Fail;
4076 }
4077 Ptr = ScopeStack.pop_back_val();
4078 LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
4079 }
4080 llvm_unreachable("bogosity detected in disassembler state machine!");
4081}
4082
4083
4084} // namespace
4085