1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* * Sparc Disassembler *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#include "llvm/MC/MCInst.h"
11#include "llvm/MC/MCSubtargetInfo.h"
12#include "llvm/Support/DataTypes.h"
13#include "llvm/Support/Debug.h"
14#include "llvm/Support/LEB128.h"
15#include "llvm/Support/raw_ostream.h"
16#include "llvm/TargetParser/SubtargetFeature.h"
17#include <assert.h>
18
19namespace {
20
21// InsnBitWidth is essentially a type trait used by the decoder emitter to query
22// the supported bitwidth for a given type. But default, the value is 0, making
23// it an invalid type for use as `InsnType` when instantiating the decoder.
24// Individual targets are expected to provide specializations for these based
25// on their usage.
26template <typename T> constexpr uint32_t InsnBitWidth = 0;
27
28[[maybe_unused]]
29static DecodeStatus Decodesparc_ptr_rcRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
30 switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) {
31 case 0: // DefaultMode
32 return DecodeIntRegsRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
33 case 1: // SPARC64
34 return DecodeI64RegsRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
35 default:
36 llvm_unreachable("no decoder for hwmode");
37 }
38}
39
40
41static const uint8_t DecoderTableSparc32[5290] = {
42 OPC_SwitchField, 30, 2, // 0: switch Inst[31:30] {
43 0, 225, 2, // 3: case 0x0: {
44 OPC_SwitchField, 22, 3, // 6: switch Inst[24:22] {
45 0, 8, // 9: case 0x0: {
46 OPC_CheckField, 25, 5, 0, // 11: check Inst[29:25] == 0x0
47 OPC_Decode, 214, 6, 0, // 15: decode to UNIMP using decoder 0
48 // 15: }
49 1, 87, // 19: case 0x1: {
50 OPC_SwitchField, 19, 3, // 21: switch Inst[21:19] {
51 0, 19, // 24: case 0x0: {
52 OPC_SwitchField, 29, 1, // 26: switch Inst[29] {
53 0, 6, // 29: case 0x0: {
54 OPC_CheckPredicate, 0, // 31: check predicate 0
55 OPC_Decode, 134, 3, 1, // 33: decode to BPICCNT using decoder 1
56 // 33: }
57 1, 0, // 37: case 0x1: {
58 OPC_CheckPredicate, 0, // 39: check predicate 0
59 OPC_Decode, 133, 3, 1, // 41: decode to BPICCANT using decoder 1
60 // 41: }
61 // 41: } // switch Inst[29]
62 // 41: }
63 1, 19, // 45: case 0x1: {
64 OPC_SwitchField, 29, 1, // 47: switch Inst[29] {
65 0, 6, // 50: case 0x0: {
66 OPC_CheckPredicate, 0, // 52: check predicate 0
67 OPC_Decode, 131, 3, 1, // 54: decode to BPICC using decoder 1
68 // 54: }
69 1, 0, // 58: case 0x1: {
70 OPC_CheckPredicate, 0, // 60: check predicate 0
71 OPC_Decode, 132, 3, 1, // 62: decode to BPICCA using decoder 1
72 // 62: }
73 // 62: } // switch Inst[29]
74 // 62: }
75 4, 19, // 66: case 0x4: {
76 OPC_SwitchField, 29, 1, // 68: switch Inst[29] {
77 0, 6, // 71: case 0x0: {
78 OPC_CheckPredicate, 1, // 73: check predicate 1
79 OPC_Decode, 142, 3, 1, // 75: decode to BPXCCNT using decoder 1
80 // 75: }
81 1, 0, // 79: case 0x1: {
82 OPC_CheckPredicate, 1, // 81: check predicate 1
83 OPC_Decode, 141, 3, 1, // 83: decode to BPXCCANT using decoder 1
84 // 83: }
85 // 83: } // switch Inst[29]
86 // 83: }
87 5, 0, // 87: case 0x5: {
88 OPC_SwitchField, 29, 1, // 89: switch Inst[29] {
89 0, 6, // 92: case 0x0: {
90 OPC_CheckPredicate, 1, // 94: check predicate 1
91 OPC_Decode, 139, 3, 1, // 96: decode to BPXCC using decoder 1
92 // 96: }
93 1, 0, // 100: case 0x1: {
94 OPC_CheckPredicate, 1, // 102: check predicate 1
95 OPC_Decode, 140, 3, 1, // 104: decode to BPXCCA using decoder 1
96 // 104: }
97 // 104: } // switch Inst[29]
98 // 104: }
99 // 104: } // switch Inst[21:19]
100 // 104: }
101 2, 25, // 108: case 0x2: {
102 OPC_SwitchField, 29, 1, // 110: switch Inst[29] {
103 0, 14, // 113: case 0x0: {
104 OPC_Scope, 8, // 115: try {
105 OPC_CheckField, 25, 4, 8, // 117: check Inst[28:25] == 0x8
106 OPC_Decode, 249, 2, 2, // 121: decode to BA using decoder 2
107 // 121: } else try {
108 OPC_Decode, 250, 2, 3, // 125: decode to BCOND using decoder 3
109 // 125: }
110 // 125: }
111 1, 0, // 129: case 0x1: {
112 OPC_Decode, 251, 2, 3, // 131: decode to BCONDA using decoder 3
113 // 131: }
114 // 131: } // switch Inst[29]
115 // 131: }
116 3, 97, // 135: case 0x3: {
117 OPC_SwitchField, 28, 1, // 137: switch Inst[28] {
118 0, 45, // 140: case 0x0: {
119 OPC_SwitchField, 19, 1, // 142: switch Inst[19] {
120 0, 19, // 145: case 0x0: {
121 OPC_SwitchField, 29, 1, // 147: switch Inst[29] {
122 0, 6, // 150: case 0x0: {
123 OPC_CheckPredicate, 1, // 152: check predicate 1
124 OPC_Decode, 138, 3, 4, // 154: decode to BPRNT using decoder 4
125 // 154: }
126 1, 0, // 158: case 0x1: {
127 OPC_CheckPredicate, 1, // 160: check predicate 1
128 OPC_Decode, 137, 3, 4, // 162: decode to BPRANT using decoder 4
129 // 162: }
130 // 162: } // switch Inst[29]
131 // 162: }
132 1, 0, // 166: case 0x1: {
133 OPC_SwitchField, 29, 1, // 168: switch Inst[29] {
134 0, 6, // 171: case 0x0: {
135 OPC_CheckPredicate, 1, // 173: check predicate 1
136 OPC_Decode, 135, 3, 4, // 175: decode to BPR using decoder 4
137 // 175: }
138 1, 0, // 179: case 0x1: {
139 OPC_CheckPredicate, 1, // 181: check predicate 1
140 OPC_Decode, 136, 3, 4, // 183: decode to BPRA using decoder 4
141 // 183: }
142 // 183: } // switch Inst[29]
143 // 183: }
144 // 183: } // switch Inst[19]
145 // 183: }
146 1, 0, // 187: case 0x1: {
147 OPC_SwitchField, 13, 1, // 189: switch Inst[13] {
148 0, 19, // 192: case 0x0: {
149 OPC_SwitchField, 21, 1, // 194: switch Inst[21] {
150 0, 6, // 197: case 0x0: {
151 OPC_CheckPredicate, 2, // 199: check predicate 2
152 OPC_Decode, 164, 3, 5, // 201: decode to CWBCONDrr using decoder 5
153 // 201: }
154 1, 0, // 205: case 0x1: {
155 OPC_CheckPredicate, 2, // 207: check predicate 2
156 OPC_Decode, 166, 3, 5, // 209: decode to CXBCONDrr using decoder 5
157 // 209: }
158 // 209: } // switch Inst[21]
159 // 209: }
160 1, 0, // 213: case 0x1: {
161 OPC_SwitchField, 21, 1, // 215: switch Inst[21] {
162 0, 6, // 218: case 0x0: {
163 OPC_CheckPredicate, 2, // 220: check predicate 2
164 OPC_Decode, 163, 3, 6, // 222: decode to CWBCONDri using decoder 6
165 // 222: }
166 1, 0, // 226: case 0x1: {
167 OPC_CheckPredicate, 2, // 228: check predicate 2
168 OPC_Decode, 165, 3, 6, // 230: decode to CXBCONDri using decoder 6
169 // 230: }
170 // 230: } // switch Inst[21]
171 // 230: }
172 // 230: } // switch Inst[13]
173 // 230: }
174 // 230: } // switch Inst[28]
175 // 230: }
176 4, 18, // 234: case 0x4: {
177 OPC_Scope, 12, // 236: try {
178 OPC_CheckField, 0, 22, 0, // 238: check Inst[21:0] == 0x0
179 OPC_CheckField, 25, 5, 0, // 242: check Inst[29:25] == 0x0
180 OPC_Decode, 179, 5, 7, // 246: decode to NOP using decoder 7
181 // 246: } else try {
182 OPC_Decode, 222, 5, 8, // 250: decode to SETHIi using decoder 8
183 // 250: }
184 // 250: }
185 5, 69, // 254: case 0x5: {
186 OPC_SwitchField, 19, 1, // 256: switch Inst[19] {
187 0, 19, // 259: case 0x0: {
188 OPC_SwitchField, 29, 1, // 261: switch Inst[29] {
189 0, 6, // 264: case 0x0: {
190 OPC_CheckPredicate, 0, // 266: check predicate 0
191 OPC_Decode, 130, 3, 9, // 268: decode to BPFCCNT using decoder 9
192 // 268: }
193 1, 0, // 272: case 0x1: {
194 OPC_CheckPredicate, 0, // 274: check predicate 0
195 OPC_Decode, 129, 3, 9, // 276: decode to BPFCCANT using decoder 9
196 // 276: }
197 // 276: } // switch Inst[29]
198 // 276: }
199 1, 0, // 280: case 0x1: {
200 OPC_SwitchField, 29, 1, // 282: switch Inst[29] {
201 0, 18, // 285: case 0x0: {
202 OPC_Scope, 10, // 287: try {
203 OPC_CheckField, 20, 2, 0, // 289: check Inst[21:20] == 0x0
204 OPC_CheckPredicate, 0, // 293: check predicate 0
205 OPC_Decode, 200, 3, 1, // 295: decode to FBCOND_V9 using decoder 1
206 // 295: } else try {
207 OPC_CheckPredicate, 0, // 299: check predicate 0
208 OPC_Decode, 255, 2, 9, // 301: decode to BPFCC using decoder 9
209 // 301: }
210 // 301: }
211 1, 0, // 305: case 0x1: {
212 OPC_Scope, 10, // 307: try {
213 OPC_CheckField, 20, 2, 0, // 309: check Inst[21:20] == 0x0
214 OPC_CheckPredicate, 0, // 313: check predicate 0
215 OPC_Decode, 199, 3, 1, // 315: decode to FBCONDA_V9 using decoder 1
216 // 315: } else try {
217 OPC_CheckPredicate, 0, // 319: check predicate 0
218 OPC_Decode, 128, 3, 9, // 321: decode to BPFCCA using decoder 9
219 // 321: }
220 // 321: }
221 // 321: } // switch Inst[29]
222 // 321: }
223 // 321: } // switch Inst[19]
224 // 321: }
225 6, 15, // 325: case 0x6: {
226 OPC_SwitchField, 29, 1, // 327: switch Inst[29] {
227 0, 4, // 330: case 0x0: {
228 OPC_Decode, 197, 3, 3, // 332: decode to FBCOND using decoder 3
229 // 332: }
230 1, 0, // 336: case 0x1: {
231 OPC_Decode, 198, 3, 3, // 338: decode to FBCONDA using decoder 3
232 // 338: }
233 // 338: } // switch Inst[29]
234 // 338: }
235 7, 0, // 342: case 0x7: {
236 OPC_SwitchField, 29, 1, // 344: switch Inst[29] {
237 0, 4, // 347: case 0x0: {
238 OPC_Decode, 160, 3, 3, // 349: decode to CPBCOND using decoder 3
239 // 349: }
240 1, 0, // 353: case 0x1: {
241 OPC_Decode, 161, 3, 3, // 355: decode to CPBCONDA using decoder 3
242 // 355: }
243 // 355: } // switch Inst[29]
244 // 355: }
245 // 355: } // switch Inst[24:22]
246 // 355: }
247 1, 4, // 359: case 0x1: {
248 OPC_Decode, 144, 3, 10, // 361: decode to CALL using decoder 10
249 // 361: }
250 2, 189, 30, // 365: case 0x2: {
251 OPC_SwitchField, 19, 6, // 368: switch Inst[24:19] {
252 0, 19, // 371: case 0x0: {
253 OPC_SwitchField, 13, 1, // 373: switch Inst[13] {
254 0, 8, // 376: case 0x0: {
255 OPC_CheckField, 5, 8, 0, // 378: check Inst[12:5] == 0x0
256 OPC_Decode, 223, 2, 11, // 382: decode to ADDrr using decoder 11
257 // 382: }
258 1, 0, // 386: case 0x1: {
259 OPC_Decode, 222, 2, 12, // 388: decode to ADDri using decoder 12
260 // 388: }
261 // 388: } // switch Inst[13]
262 // 388: }
263 1, 19, // 392: case 0x1: {
264 OPC_SwitchField, 13, 1, // 394: switch Inst[13] {
265 0, 8, // 397: case 0x0: {
266 OPC_CheckField, 5, 8, 0, // 399: check Inst[12:5] == 0x0
267 OPC_Decode, 245, 2, 11, // 403: decode to ANDrr using decoder 11
268 // 403: }
269 1, 0, // 407: case 0x1: {
270 OPC_Decode, 244, 2, 12, // 409: decode to ANDri using decoder 12
271 // 409: }
272 // 409: } // switch Inst[13]
273 // 409: }
274 2, 19, // 413: case 0x2: {
275 OPC_SwitchField, 13, 1, // 415: switch Inst[13] {
276 0, 8, // 418: case 0x0: {
277 OPC_CheckField, 5, 8, 0, // 420: check Inst[12:5] == 0x0
278 OPC_Decode, 188, 5, 11, // 424: decode to ORrr using decoder 11
279 // 424: }
280 1, 0, // 428: case 0x1: {
281 OPC_Decode, 187, 5, 12, // 430: decode to ORri using decoder 12
282 // 430: }
283 // 430: } // switch Inst[13]
284 // 430: }
285 3, 19, // 434: case 0x3: {
286 OPC_SwitchField, 13, 1, // 436: switch Inst[13] {
287 0, 8, // 439: case 0x0: {
288 OPC_CheckField, 5, 8, 0, // 441: check Inst[12:5] == 0x0
289 OPC_Decode, 245, 6, 11, // 445: decode to XORrr using decoder 11
290 // 445: }
291 1, 0, // 449: case 0x1: {
292 OPC_Decode, 244, 6, 12, // 451: decode to XORri using decoder 12
293 // 451: }
294 // 451: } // switch Inst[13]
295 // 451: }
296 4, 19, // 455: case 0x4: {
297 OPC_SwitchField, 13, 1, // 457: switch Inst[13] {
298 0, 8, // 460: case 0x0: {
299 OPC_CheckField, 5, 8, 0, // 462: check Inst[12:5] == 0x0
300 OPC_Decode, 173, 6, 11, // 466: decode to SUBrr using decoder 11
301 // 466: }
302 1, 0, // 470: case 0x1: {
303 OPC_Decode, 172, 6, 12, // 472: decode to SUBri using decoder 12
304 // 472: }
305 // 472: } // switch Inst[13]
306 // 472: }
307 5, 19, // 476: case 0x5: {
308 OPC_SwitchField, 13, 1, // 478: switch Inst[13] {
309 0, 8, // 481: case 0x0: {
310 OPC_CheckField, 5, 8, 0, // 483: check Inst[12:5] == 0x0
311 OPC_Decode, 243, 2, 11, // 487: decode to ANDNrr using decoder 11
312 // 487: }
313 1, 0, // 491: case 0x1: {
314 OPC_Decode, 242, 2, 12, // 493: decode to ANDNri using decoder 12
315 // 493: }
316 // 493: } // switch Inst[13]
317 // 493: }
318 6, 19, // 497: case 0x6: {
319 OPC_SwitchField, 13, 1, // 499: switch Inst[13] {
320 0, 8, // 502: case 0x0: {
321 OPC_CheckField, 5, 8, 0, // 504: check Inst[12:5] == 0x0
322 OPC_Decode, 186, 5, 11, // 508: decode to ORNrr using decoder 11
323 // 508: }
324 1, 0, // 512: case 0x1: {
325 OPC_Decode, 185, 5, 12, // 514: decode to ORNri using decoder 12
326 // 514: }
327 // 514: } // switch Inst[13]
328 // 514: }
329 7, 19, // 518: case 0x7: {
330 OPC_SwitchField, 13, 1, // 520: switch Inst[13] {
331 0, 8, // 523: case 0x0: {
332 OPC_CheckField, 5, 8, 0, // 525: check Inst[12:5] == 0x0
333 OPC_Decode, 241, 6, 11, // 529: decode to XNORrr using decoder 11
334 // 529: }
335 1, 0, // 533: case 0x1: {
336 OPC_Decode, 240, 6, 12, // 535: decode to XNORri using decoder 12
337 // 535: }
338 // 535: } // switch Inst[13]
339 // 535: }
340 8, 19, // 539: case 0x8: {
341 OPC_SwitchField, 13, 1, // 541: switch Inst[13] {
342 0, 8, // 544: case 0x0: {
343 OPC_CheckField, 5, 8, 0, // 546: check Inst[12:5] == 0x0
344 OPC_Decode, 217, 2, 11, // 550: decode to ADDCrr using decoder 11
345 // 550: }
346 1, 0, // 554: case 0x1: {
347 OPC_Decode, 216, 2, 12, // 556: decode to ADDCri using decoder 12
348 // 556: }
349 // 556: } // switch Inst[13]
350 // 556: }
351 9, 23, // 560: case 0x9: {
352 OPC_SwitchField, 13, 1, // 562: switch Inst[13] {
353 0, 10, // 565: case 0x0: {
354 OPC_CheckPredicate, 1, // 567: check predicate 1
355 OPC_CheckField, 5, 8, 0, // 569: check Inst[12:5] == 0x0
356 OPC_Decode, 178, 5, 13, // 573: decode to MULXrr using decoder 13
357 // 573: }
358 1, 0, // 577: case 0x1: {
359 OPC_CheckPredicate, 1, // 579: check predicate 1
360 OPC_Decode, 177, 5, 14, // 581: decode to MULXri using decoder 14
361 // 581: }
362 // 581: } // switch Inst[13]
363 // 581: }
364 10, 19, // 585: case 0xa: {
365 OPC_SwitchField, 13, 1, // 587: switch Inst[13] {
366 0, 8, // 590: case 0x0: {
367 OPC_CheckField, 5, 8, 0, // 592: check Inst[12:5] == 0x0
368 OPC_Decode, 213, 6, 11, // 596: decode to UMULrr using decoder 11
369 // 596: }
370 1, 0, // 600: case 0x1: {
371 OPC_Decode, 212, 6, 12, // 602: decode to UMULri using decoder 12
372 // 602: }
373 // 602: } // switch Inst[13]
374 // 602: }
375 11, 19, // 606: case 0xb: {
376 OPC_SwitchField, 13, 1, // 608: switch Inst[13] {
377 0, 8, // 611: case 0x0: {
378 OPC_CheckField, 5, 8, 0, // 613: check Inst[12:5] == 0x0
379 OPC_Decode, 238, 5, 11, // 617: decode to SMULrr using decoder 11
380 // 617: }
381 1, 0, // 621: case 0x1: {
382 OPC_Decode, 237, 5, 12, // 623: decode to SMULri using decoder 12
383 // 623: }
384 // 623: } // switch Inst[13]
385 // 623: }
386 12, 19, // 627: case 0xc: {
387 OPC_SwitchField, 13, 1, // 629: switch Inst[13] {
388 0, 8, // 632: case 0x0: {
389 OPC_CheckField, 5, 8, 0, // 634: check Inst[12:5] == 0x0
390 OPC_Decode, 169, 6, 11, // 638: decode to SUBCrr using decoder 11
391 // 638: }
392 1, 0, // 642: case 0x1: {
393 OPC_Decode, 168, 6, 12, // 644: decode to SUBCri using decoder 12
394 // 644: }
395 // 644: } // switch Inst[13]
396 // 644: }
397 13, 23, // 648: case 0xd: {
398 OPC_SwitchField, 13, 1, // 650: switch Inst[13] {
399 0, 10, // 653: case 0x0: {
400 OPC_CheckPredicate, 1, // 655: check predicate 1
401 OPC_CheckField, 5, 8, 0, // 657: check Inst[12:5] == 0x0
402 OPC_Decode, 204, 6, 13, // 661: decode to UDIVXrr using decoder 13
403 // 661: }
404 1, 0, // 665: case 0x1: {
405 OPC_CheckPredicate, 1, // 667: check predicate 1
406 OPC_Decode, 203, 6, 14, // 669: decode to UDIVXri using decoder 14
407 // 669: }
408 // 669: } // switch Inst[13]
409 // 669: }
410 14, 19, // 673: case 0xe: {
411 OPC_SwitchField, 13, 1, // 675: switch Inst[13] {
412 0, 8, // 678: case 0x0: {
413 OPC_CheckField, 5, 8, 0, // 680: check Inst[12:5] == 0x0
414 OPC_Decode, 206, 6, 11, // 684: decode to UDIVrr using decoder 11
415 // 684: }
416 1, 0, // 688: case 0x1: {
417 OPC_Decode, 205, 6, 12, // 690: decode to UDIVri using decoder 12
418 // 690: }
419 // 690: } // switch Inst[13]
420 // 690: }
421 15, 19, // 694: case 0xf: {
422 OPC_SwitchField, 13, 1, // 696: switch Inst[13] {
423 0, 8, // 699: case 0x0: {
424 OPC_CheckField, 5, 8, 0, // 701: check Inst[12:5] == 0x0
425 OPC_Decode, 221, 5, 11, // 705: decode to SDIVrr using decoder 11
426 // 705: }
427 1, 0, // 709: case 0x1: {
428 OPC_Decode, 220, 5, 12, // 711: decode to SDIVri using decoder 12
429 // 711: }
430 // 711: } // switch Inst[13]
431 // 711: }
432 16, 19, // 715: case 0x10: {
433 OPC_SwitchField, 13, 1, // 717: switch Inst[13] {
434 0, 8, // 720: case 0x0: {
435 OPC_CheckField, 5, 8, 0, // 722: check Inst[12:5] == 0x0
436 OPC_Decode, 215, 2, 11, // 726: decode to ADDCCrr using decoder 11
437 // 726: }
438 1, 0, // 730: case 0x1: {
439 OPC_Decode, 214, 2, 12, // 732: decode to ADDCCri using decoder 12
440 // 732: }
441 // 732: } // switch Inst[13]
442 // 732: }
443 17, 19, // 736: case 0x11: {
444 OPC_SwitchField, 13, 1, // 738: switch Inst[13] {
445 0, 8, // 741: case 0x0: {
446 OPC_CheckField, 5, 8, 0, // 743: check Inst[12:5] == 0x0
447 OPC_Decode, 239, 2, 11, // 747: decode to ANDCCrr using decoder 11
448 // 747: }
449 1, 0, // 751: case 0x1: {
450 OPC_Decode, 238, 2, 12, // 753: decode to ANDCCri using decoder 12
451 // 753: }
452 // 753: } // switch Inst[13]
453 // 753: }
454 18, 19, // 757: case 0x12: {
455 OPC_SwitchField, 13, 1, // 759: switch Inst[13] {
456 0, 8, // 762: case 0x0: {
457 OPC_CheckField, 5, 8, 0, // 764: check Inst[12:5] == 0x0
458 OPC_Decode, 182, 5, 11, // 768: decode to ORCCrr using decoder 11
459 // 768: }
460 1, 0, // 772: case 0x1: {
461 OPC_Decode, 181, 5, 12, // 774: decode to ORCCri using decoder 12
462 // 774: }
463 // 774: } // switch Inst[13]
464 // 774: }
465 19, 19, // 778: case 0x13: {
466 OPC_SwitchField, 13, 1, // 780: switch Inst[13] {
467 0, 8, // 783: case 0x0: {
468 OPC_CheckField, 5, 8, 0, // 785: check Inst[12:5] == 0x0
469 OPC_Decode, 243, 6, 11, // 789: decode to XORCCrr using decoder 11
470 // 789: }
471 1, 0, // 793: case 0x1: {
472 OPC_Decode, 242, 6, 12, // 795: decode to XORCCri using decoder 12
473 // 795: }
474 // 795: } // switch Inst[13]
475 // 795: }
476 20, 19, // 799: case 0x14: {
477 OPC_SwitchField, 13, 1, // 801: switch Inst[13] {
478 0, 8, // 804: case 0x0: {
479 OPC_CheckField, 5, 8, 0, // 806: check Inst[12:5] == 0x0
480 OPC_Decode, 167, 6, 11, // 810: decode to SUBCCrr using decoder 11
481 // 810: }
482 1, 0, // 814: case 0x1: {
483 OPC_Decode, 166, 6, 12, // 816: decode to SUBCCri using decoder 12
484 // 816: }
485 // 816: } // switch Inst[13]
486 // 816: }
487 21, 19, // 820: case 0x15: {
488 OPC_SwitchField, 13, 1, // 822: switch Inst[13] {
489 0, 8, // 825: case 0x0: {
490 OPC_CheckField, 5, 8, 0, // 827: check Inst[12:5] == 0x0
491 OPC_Decode, 241, 2, 11, // 831: decode to ANDNCCrr using decoder 11
492 // 831: }
493 1, 0, // 835: case 0x1: {
494 OPC_Decode, 240, 2, 12, // 837: decode to ANDNCCri using decoder 12
495 // 837: }
496 // 837: } // switch Inst[13]
497 // 837: }
498 22, 19, // 841: case 0x16: {
499 OPC_SwitchField, 13, 1, // 843: switch Inst[13] {
500 0, 8, // 846: case 0x0: {
501 OPC_CheckField, 5, 8, 0, // 848: check Inst[12:5] == 0x0
502 OPC_Decode, 184, 5, 11, // 852: decode to ORNCCrr using decoder 11
503 // 852: }
504 1, 0, // 856: case 0x1: {
505 OPC_Decode, 183, 5, 12, // 858: decode to ORNCCri using decoder 12
506 // 858: }
507 // 858: } // switch Inst[13]
508 // 858: }
509 23, 19, // 862: case 0x17: {
510 OPC_SwitchField, 13, 1, // 864: switch Inst[13] {
511 0, 8, // 867: case 0x0: {
512 OPC_CheckField, 5, 8, 0, // 869: check Inst[12:5] == 0x0
513 OPC_Decode, 239, 6, 11, // 873: decode to XNORCCrr using decoder 11
514 // 873: }
515 1, 0, // 877: case 0x1: {
516 OPC_Decode, 238, 6, 12, // 879: decode to XNORCCri using decoder 12
517 // 879: }
518 // 879: } // switch Inst[13]
519 // 879: }
520 24, 19, // 883: case 0x18: {
521 OPC_SwitchField, 13, 1, // 885: switch Inst[13] {
522 0, 8, // 888: case 0x0: {
523 OPC_CheckField, 5, 8, 0, // 890: check Inst[12:5] == 0x0
524 OPC_Decode, 219, 2, 11, // 894: decode to ADDErr using decoder 11
525 // 894: }
526 1, 0, // 898: case 0x1: {
527 OPC_Decode, 218, 2, 12, // 900: decode to ADDEri using decoder 12
528 // 900: }
529 // 900: } // switch Inst[13]
530 // 900: }
531 25, 91, // 904: case 0x19: {
532 OPC_SwitchField, 5, 4, // 906: switch Inst[8:5] {
533 0, 6, // 909: case 0x0: {
534 OPC_CheckPredicate, 3, // 911: check predicate 3
535 OPC_Decode, 228, 2, 15, // 913: decode to AES_EROUND01 using decoder 15
536 // 913: }
537 1, 6, // 917: case 0x1: {
538 OPC_CheckPredicate, 3, // 919: check predicate 3
539 OPC_Decode, 230, 2, 15, // 921: decode to AES_EROUND23 using decoder 15
540 // 921: }
541 2, 6, // 925: case 0x2: {
542 OPC_CheckPredicate, 3, // 927: check predicate 3
543 OPC_Decode, 224, 2, 15, // 929: decode to AES_DROUND01 using decoder 15
544 // 929: }
545 3, 6, // 933: case 0x3: {
546 OPC_CheckPredicate, 3, // 935: check predicate 3
547 OPC_Decode, 226, 2, 15, // 937: decode to AES_DROUND23 using decoder 15
548 // 937: }
549 4, 6, // 941: case 0x4: {
550 OPC_CheckPredicate, 3, // 943: check predicate 3
551 OPC_Decode, 229, 2, 15, // 945: decode to AES_EROUND01_LAST using decoder 15
552 // 945: }
553 5, 6, // 949: case 0x5: {
554 OPC_CheckPredicate, 3, // 951: check predicate 3
555 OPC_Decode, 231, 2, 15, // 953: decode to AES_EROUND23_LAST using decoder 15
556 // 953: }
557 6, 6, // 957: case 0x6: {
558 OPC_CheckPredicate, 3, // 959: check predicate 3
559 OPC_Decode, 225, 2, 15, // 961: decode to AES_DROUND01_LAST using decoder 15
560 // 961: }
561 7, 6, // 965: case 0x7: {
562 OPC_CheckPredicate, 3, // 967: check predicate 3
563 OPC_Decode, 227, 2, 15, // 969: decode to AES_DROUND23_LAST using decoder 15
564 // 969: }
565 8, 6, // 973: case 0x8: {
566 OPC_CheckPredicate, 3, // 975: check predicate 3
567 OPC_Decode, 233, 2, 16, // 977: decode to AES_KEXPAND1 using decoder 16
568 // 977: }
569 9, 6, // 981: case 0x9: {
570 OPC_CheckPredicate, 3, // 983: check predicate 3
571 OPC_Decode, 170, 3, 15, // 985: decode to DES_ROUND using decoder 15
572 // 985: }
573 12, 0, // 989: case 0xc: {
574 OPC_CheckPredicate, 3, // 991: check predicate 3
575 OPC_Decode, 150, 3, 15, // 993: decode to CAMELLIA_F using decoder 15
576 // 993: }
577 // 993: } // switch Inst[8:5]
578 // 993: }
579 26, 19, // 997: case 0x1a: {
580 OPC_SwitchField, 13, 1, // 999: switch Inst[13] {
581 0, 8, // 1002: case 0x0: {
582 OPC_CheckField, 5, 8, 0, // 1004: check Inst[12:5] == 0x0
583 OPC_Decode, 210, 6, 11, // 1008: decode to UMULCCrr using decoder 11
584 // 1008: }
585 1, 0, // 1012: case 0x1: {
586 OPC_Decode, 209, 6, 12, // 1014: decode to UMULCCri using decoder 12
587 // 1014: }
588 // 1014: } // switch Inst[13]
589 // 1014: }
590 27, 19, // 1018: case 0x1b: {
591 OPC_SwitchField, 13, 1, // 1020: switch Inst[13] {
592 0, 8, // 1023: case 0x0: {
593 OPC_CheckField, 5, 8, 0, // 1025: check Inst[12:5] == 0x0
594 OPC_Decode, 236, 5, 11, // 1029: decode to SMULCCrr using decoder 11
595 // 1029: }
596 1, 0, // 1033: case 0x1: {
597 OPC_Decode, 235, 5, 12, // 1035: decode to SMULCCri using decoder 12
598 // 1035: }
599 // 1035: } // switch Inst[13]
600 // 1035: }
601 28, 19, // 1039: case 0x1c: {
602 OPC_SwitchField, 13, 1, // 1041: switch Inst[13] {
603 0, 8, // 1044: case 0x0: {
604 OPC_CheckField, 5, 8, 0, // 1046: check Inst[12:5] == 0x0
605 OPC_Decode, 171, 6, 11, // 1050: decode to SUBErr using decoder 11
606 // 1050: }
607 1, 0, // 1054: case 0x1: {
608 OPC_Decode, 170, 6, 12, // 1056: decode to SUBEri using decoder 12
609 // 1056: }
610 // 1056: } // switch Inst[13]
611 // 1056: }
612 30, 19, // 1060: case 0x1e: {
613 OPC_SwitchField, 13, 1, // 1062: switch Inst[13] {
614 0, 8, // 1065: case 0x0: {
615 OPC_CheckField, 5, 8, 0, // 1067: check Inst[12:5] == 0x0
616 OPC_Decode, 202, 6, 11, // 1071: decode to UDIVCCrr using decoder 11
617 // 1071: }
618 1, 0, // 1075: case 0x1: {
619 OPC_Decode, 201, 6, 12, // 1077: decode to UDIVCCri using decoder 12
620 // 1077: }
621 // 1077: } // switch Inst[13]
622 // 1077: }
623 31, 19, // 1081: case 0x1f: {
624 OPC_SwitchField, 13, 1, // 1083: switch Inst[13] {
625 0, 8, // 1086: case 0x0: {
626 OPC_CheckField, 5, 8, 0, // 1088: check Inst[12:5] == 0x0
627 OPC_Decode, 217, 5, 11, // 1092: decode to SDIVCCrr using decoder 11
628 // 1092: }
629 1, 0, // 1096: case 0x1: {
630 OPC_Decode, 216, 5, 12, // 1098: decode to SDIVCCri using decoder 12
631 // 1098: }
632 // 1098: } // switch Inst[13]
633 // 1098: }
634 32, 19, // 1102: case 0x20: {
635 OPC_SwitchField, 13, 1, // 1104: switch Inst[13] {
636 0, 8, // 1107: case 0x0: {
637 OPC_CheckField, 5, 8, 0, // 1109: check Inst[12:5] == 0x0
638 OPC_Decode, 184, 6, 11, // 1113: decode to TADDCCrr using decoder 11
639 // 1113: }
640 1, 0, // 1117: case 0x1: {
641 OPC_Decode, 183, 6, 12, // 1119: decode to TADDCCri using decoder 12
642 // 1119: }
643 // 1119: } // switch Inst[13]
644 // 1119: }
645 33, 19, // 1123: case 0x21: {
646 OPC_SwitchField, 13, 1, // 1125: switch Inst[13] {
647 0, 8, // 1128: case 0x0: {
648 OPC_CheckField, 5, 8, 0, // 1130: check Inst[12:5] == 0x0
649 OPC_Decode, 198, 6, 11, // 1134: decode to TSUBCCrr using decoder 11
650 // 1134: }
651 1, 0, // 1138: case 0x1: {
652 OPC_Decode, 197, 6, 12, // 1140: decode to TSUBCCri using decoder 12
653 // 1140: }
654 // 1140: } // switch Inst[13]
655 // 1140: }
656 34, 19, // 1144: case 0x22: {
657 OPC_SwitchField, 13, 1, // 1146: switch Inst[13] {
658 0, 8, // 1149: case 0x0: {
659 OPC_CheckField, 5, 8, 0, // 1151: check Inst[12:5] == 0x0
660 OPC_Decode, 182, 6, 11, // 1155: decode to TADDCCTVrr using decoder 11
661 // 1155: }
662 1, 0, // 1159: case 0x1: {
663 OPC_Decode, 181, 6, 12, // 1161: decode to TADDCCTVri using decoder 12
664 // 1161: }
665 // 1161: } // switch Inst[13]
666 // 1161: }
667 35, 19, // 1165: case 0x23: {
668 OPC_SwitchField, 13, 1, // 1167: switch Inst[13] {
669 0, 8, // 1170: case 0x0: {
670 OPC_CheckField, 5, 8, 0, // 1172: check Inst[12:5] == 0x0
671 OPC_Decode, 196, 6, 11, // 1176: decode to TSUBCCTVrr using decoder 11
672 // 1176: }
673 1, 0, // 1180: case 0x1: {
674 OPC_Decode, 195, 6, 12, // 1182: decode to TSUBCCTVri using decoder 12
675 // 1182: }
676 // 1182: } // switch Inst[13]
677 // 1182: }
678 36, 19, // 1186: case 0x24: {
679 OPC_SwitchField, 13, 1, // 1188: switch Inst[13] {
680 0, 8, // 1191: case 0x0: {
681 OPC_CheckField, 5, 8, 0, // 1193: check Inst[12:5] == 0x0
682 OPC_Decode, 176, 5, 11, // 1197: decode to MULSCCrr using decoder 11
683 // 1197: }
684 1, 0, // 1201: case 0x1: {
685 OPC_Decode, 175, 5, 12, // 1203: decode to MULSCCri using decoder 12
686 // 1203: }
687 // 1203: } // switch Inst[13]
688 // 1203: }
689 37, 31, // 1207: case 0x25: {
690 OPC_SwitchField, 12, 2, // 1209: switch Inst[13:12] {
691 0, 4, // 1212: case 0x0: {
692 OPC_Decode, 232, 5, 11, // 1214: decode to SLLrr using decoder 11
693 // 1214: }
694 1, 6, // 1218: case 0x1: {
695 OPC_CheckPredicate, 1, // 1220: check predicate 1
696 OPC_Decode, 230, 5, 17, // 1222: decode to SLLXrr using decoder 17
697 // 1222: }
698 2, 4, // 1226: case 0x2: {
699 OPC_Decode, 231, 5, 18, // 1228: decode to SLLri using decoder 18
700 // 1228: }
701 3, 0, // 1232: case 0x3: {
702 OPC_CheckPredicate, 1, // 1234: check predicate 1
703 OPC_Decode, 229, 5, 19, // 1236: decode to SLLXri using decoder 19
704 // 1236: }
705 // 1236: } // switch Inst[13:12]
706 // 1236: }
707 38, 31, // 1240: case 0x26: {
708 OPC_SwitchField, 12, 2, // 1242: switch Inst[13:12] {
709 0, 4, // 1245: case 0x0: {
710 OPC_Decode, 246, 5, 11, // 1247: decode to SRLrr using decoder 11
711 // 1247: }
712 1, 6, // 1251: case 0x1: {
713 OPC_CheckPredicate, 1, // 1253: check predicate 1
714 OPC_Decode, 244, 5, 17, // 1255: decode to SRLXrr using decoder 17
715 // 1255: }
716 2, 4, // 1259: case 0x2: {
717 OPC_Decode, 245, 5, 18, // 1261: decode to SRLri using decoder 18
718 // 1261: }
719 3, 0, // 1265: case 0x3: {
720 OPC_CheckPredicate, 1, // 1267: check predicate 1
721 OPC_Decode, 243, 5, 19, // 1269: decode to SRLXri using decoder 19
722 // 1269: }
723 // 1269: } // switch Inst[13:12]
724 // 1269: }
725 39, 31, // 1273: case 0x27: {
726 OPC_SwitchField, 12, 2, // 1275: switch Inst[13:12] {
727 0, 4, // 1278: case 0x0: {
728 OPC_Decode, 242, 5, 11, // 1280: decode to SRArr using decoder 11
729 // 1280: }
730 1, 6, // 1284: case 0x1: {
731 OPC_CheckPredicate, 1, // 1286: check predicate 1
732 OPC_Decode, 240, 5, 17, // 1288: decode to SRAXrr using decoder 17
733 // 1288: }
734 2, 4, // 1292: case 0x2: {
735 OPC_Decode, 241, 5, 18, // 1294: decode to SRAri using decoder 18
736 // 1294: }
737 3, 0, // 1298: case 0x3: {
738 OPC_CheckPredicate, 1, // 1300: check predicate 1
739 OPC_Decode, 239, 5, 19, // 1302: decode to SRAXri using decoder 19
740 // 1302: }
741 // 1302: } // switch Inst[13:12]
742 // 1302: }
743 40, 43, // 1306: case 0x28: {
744 OPC_SwitchField, 13, 1, // 1308: switch Inst[13] {
745 0, 22, // 1311: case 0x0: {
746 OPC_CheckField, 0, 13, 0, // 1313: check Inst[12:0] == 0x0
747 OPC_Scope, 12, // 1317: try {
748 OPC_CheckField, 14, 5, 15, // 1319: check Inst[18:14] == 0xf
749 OPC_CheckField, 25, 5, 0, // 1323: check Inst[29:25] == 0x0
750 OPC_Decode, 249, 5, 7, // 1327: decode to STBAR using decoder 7
751 // 1327: } else try {
752 OPC_Decode, 199, 5, 20, // 1331: decode to RDASR using decoder 20
753 // 1331: }
754 // 1331: }
755 1, 0, // 1335: case 0x1: {
756 OPC_CheckPredicate, 0, // 1337: check predicate 0
757 OPC_CheckField, 25, 5, 0, // 1339: check Inst[29:25] == 0x0
758 OPC_CheckField, 14, 5, 15, // 1343: check Inst[18:14] == 0xf
759 OPC_Decode, 158, 5, 21, // 1347: decode to MEMBARi using decoder 21
760 // 1347: }
761 // 1347: } // switch Inst[13]
762 // 1347: }
763 41, 8, // 1351: case 0x29: {
764 OPC_CheckField, 0, 19, 0, // 1353: check Inst[18:0] == 0x0
765 OPC_Decode, 202, 5, 22, // 1357: decode to RDPSR using decoder 22
766 // 1357: }
767 42, 29, // 1361: case 0x2a: {
768 OPC_CheckField, 0, 14, 0, // 1363: check Inst[13:0] == 0x0
769 OPC_Scope, 17, // 1367: try {
770 OPC_SwitchField, 14, 5, // 1369: switch Inst[18:14] {
771 0, 4, // 1372: case 0x0: {
772 OPC_Decode, 204, 5, 22, // 1374: decode to RDWIM using decoder 22
773 // 1374: }
774 15, 0, // 1378: case 0xf: {
775 OPC_CheckPredicate, 0, // 1380: check predicate 0
776 OPC_Decode, 200, 5, 22, // 1382: decode to RDFQ using decoder 22
777 // 1382: }
778 // 1382: } // switch Inst[18:14]
779 // 1382: } else try {
780 OPC_CheckPredicate, 0, // 1386: check predicate 0
781 OPC_Decode, 201, 5, 23, // 1388: decode to RDPR using decoder 23
782 // 1388: }
783 // 1388: }
784 43, 20, // 1392: case 0x2b: {
785 OPC_CheckField, 0, 19, 0, // 1394: check Inst[18:0] == 0x0
786 OPC_Scope, 10, // 1398: try {
787 OPC_CheckField, 25, 5, 0, // 1400: check Inst[29:25] == 0x0
788 OPC_CheckPredicate, 0, // 1404: check predicate 0
789 OPC_Decode, 235, 3, 7, // 1406: decode to FLUSHW using decoder 7
790 // 1406: } else try {
791 OPC_Decode, 203, 5, 22, // 1410: decode to RDTBR using decoder 22
792 // 1410: }
793 // 1410: }
794 44, 95, // 1414: case 0x2c: {
795 OPC_SwitchField, 13, 1, // 1416: switch Inst[13] {
796 0, 44, // 1419: case 0x0: {
797 OPC_SwitchField, 18, 1, // 1421: switch Inst[18] {
798 0, 18, // 1424: case 0x0: {
799 OPC_Scope, 10, // 1426: try {
800 OPC_CheckField, 11, 2, 0, // 1428: check Inst[12:11] == 0x0
801 OPC_CheckPredicate, 0, // 1432: check predicate 0
802 OPC_Decode, 163, 5, 24, // 1434: decode to MOVFCCrr using decoder 24
803 // 1434: } else try {
804 OPC_CheckPredicate, 0, // 1438: check predicate 0
805 OPC_Decode, 225, 6, 25, // 1440: decode to V9MOVFCCrr using decoder 25
806 // 1440: }
807 // 1440: }
808 1, 0, // 1444: case 0x1: {
809 OPC_SwitchField, 11, 2, // 1446: switch Inst[12:11] {
810 0, 6, // 1449: case 0x0: {
811 OPC_CheckPredicate, 0, // 1451: check predicate 0
812 OPC_Decode, 165, 5, 24, // 1453: decode to MOVICCrr using decoder 24
813 // 1453: }
814 2, 0, // 1457: case 0x2: {
815 OPC_CheckPredicate, 1, // 1459: check predicate 1
816 OPC_Decode, 172, 5, 24, // 1461: decode to MOVXCCrr using decoder 24
817 // 1461: }
818 // 1461: } // switch Inst[12:11]
819 // 1461: }
820 // 1461: } // switch Inst[18]
821 // 1461: }
822 1, 0, // 1465: case 0x1: {
823 OPC_SwitchField, 18, 1, // 1467: switch Inst[18] {
824 0, 18, // 1470: case 0x0: {
825 OPC_Scope, 10, // 1472: try {
826 OPC_CheckField, 11, 2, 0, // 1474: check Inst[12:11] == 0x0
827 OPC_CheckPredicate, 0, // 1478: check predicate 0
828 OPC_Decode, 162, 5, 26, // 1480: decode to MOVFCCri using decoder 26
829 // 1480: } else try {
830 OPC_CheckPredicate, 0, // 1484: check predicate 0
831 OPC_Decode, 224, 6, 27, // 1486: decode to V9MOVFCCri using decoder 27
832 // 1486: }
833 // 1486: }
834 1, 0, // 1490: case 0x1: {
835 OPC_SwitchField, 11, 2, // 1492: switch Inst[12:11] {
836 0, 6, // 1495: case 0x0: {
837 OPC_CheckPredicate, 0, // 1497: check predicate 0
838 OPC_Decode, 164, 5, 26, // 1499: decode to MOVICCri using decoder 26
839 // 1499: }
840 2, 0, // 1503: case 0x2: {
841 OPC_CheckPredicate, 1, // 1505: check predicate 1
842 OPC_Decode, 171, 5, 26, // 1507: decode to MOVXCCri using decoder 26
843 // 1507: }
844 // 1507: } // switch Inst[12:11]
845 // 1507: }
846 // 1507: } // switch Inst[18]
847 // 1507: }
848 // 1507: } // switch Inst[13]
849 // 1507: }
850 45, 23, // 1511: case 0x2d: {
851 OPC_SwitchField, 13, 1, // 1513: switch Inst[13] {
852 0, 10, // 1516: case 0x0: {
853 OPC_CheckPredicate, 1, // 1518: check predicate 1
854 OPC_CheckField, 5, 8, 0, // 1520: check Inst[12:5] == 0x0
855 OPC_Decode, 219, 5, 13, // 1524: decode to SDIVXrr using decoder 13
856 // 1524: }
857 1, 0, // 1528: case 0x1: {
858 OPC_CheckPredicate, 1, // 1530: check predicate 1
859 OPC_Decode, 218, 5, 14, // 1532: decode to SDIVXri using decoder 14
860 // 1532: }
861 // 1532: } // switch Inst[13]
862 // 1532: }
863 46, 10, // 1536: case 0x2e: {
864 OPC_CheckPredicate, 0, // 1538: check predicate 0
865 OPC_CheckField, 5, 14, 0, // 1540: check Inst[18:5] == 0x0
866 OPC_Decode, 192, 5, 28, // 1544: decode to POPCrr using decoder 28
867 // 1544: }
868 47, 23, // 1548: case 0x2f: {
869 OPC_SwitchField, 13, 1, // 1550: switch Inst[13] {
870 0, 10, // 1553: case 0x0: {
871 OPC_CheckPredicate, 1, // 1555: check predicate 1
872 OPC_CheckField, 5, 5, 0, // 1557: check Inst[9:5] == 0x0
873 OPC_Decode, 167, 5, 29, // 1561: decode to MOVRrr using decoder 29
874 // 1561: }
875 1, 0, // 1565: case 0x1: {
876 OPC_CheckPredicate, 1, // 1567: check predicate 1
877 OPC_Decode, 166, 5, 30, // 1569: decode to MOVRri using decoder 30
878 // 1569: }
879 // 1569: } // switch Inst[13]
880 // 1569: }
881 48, 35, // 1573: case 0x30: {
882 OPC_SwitchField, 13, 1, // 1575: switch Inst[13] {
883 0, 8, // 1578: case 0x0: {
884 OPC_CheckField, 5, 8, 0, // 1580: check Inst[12:5] == 0x0
885 OPC_Decode, 227, 6, 31, // 1584: decode to WRASRrr using decoder 31
886 // 1584: }
887 1, 0, // 1588: case 0x1: {
888 OPC_Scope, 14, // 1590: try {
889 OPC_CheckField, 14, 5, 0, // 1592: check Inst[18:14] == 0x0
890 OPC_CheckPredicate, 0, // 1596: check predicate 0
891 OPC_CheckField, 25, 5, 15, // 1598: check Inst[29:25] == 0xf
892 OPC_Decode, 228, 5, 32, // 1602: decode to SIR using decoder 32
893 // 1602: } else try {
894 OPC_Decode, 226, 6, 33, // 1606: decode to WRASRri using decoder 33
895 // 1606: }
896 // 1606: }
897 // 1606: } // switch Inst[13]
898 // 1606: }
899 49, 129, 1, // 1610: case 0x31: {
900 OPC_SwitchField, 25, 5, // 1613: switch Inst[29:25] {
901 0, 35, // 1616: case 0x0: {
902 OPC_SwitchField, 13, 1, // 1618: switch Inst[13] {
903 0, 24, // 1621: case 0x0: {
904 OPC_CheckField, 5, 8, 0, // 1623: check Inst[12:5] == 0x0
905 OPC_Scope, 14, // 1627: try {
906 OPC_CheckField, 0, 5, 0, // 1629: check Inst[4:0] == 0x0
907 OPC_CheckPredicate, 0, // 1633: check predicate 0
908 OPC_CheckField, 14, 5, 0, // 1635: check Inst[18:14] == 0x0
909 OPC_Decode, 213, 5, 7, // 1639: decode to SAVED using decoder 7
910 // 1639: } else try {
911 OPC_Decode, 231, 6, 34, // 1643: decode to WRPSRrr using decoder 34
912 // 1643: }
913 // 1643: }
914 1, 0, // 1647: case 0x1: {
915 OPC_Decode, 230, 6, 35, // 1649: decode to WRPSRri using decoder 35
916 // 1649: }
917 // 1649: } // switch Inst[13]
918 // 1649: }
919 1, 39, // 1653: case 0x1: {
920 OPC_SwitchField, 13, 1, // 1655: switch Inst[13] {
921 0, 26, // 1658: case 0x0: {
922 OPC_CheckField, 5, 8, 0, // 1660: check Inst[12:5] == 0x0
923 OPC_Scope, 14, // 1664: try {
924 OPC_CheckField, 0, 5, 0, // 1666: check Inst[4:0] == 0x0
925 OPC_CheckPredicate, 0, // 1670: check predicate 0
926 OPC_CheckField, 14, 5, 0, // 1672: check Inst[18:14] == 0x0
927 OPC_Decode, 205, 5, 7, // 1676: decode to RESTORED using decoder 7
928 // 1676: } else try {
929 OPC_CheckPredicate, 4, // 1680: check predicate 4
930 OPC_Decode, 198, 5, 34, // 1682: decode to PWRPSRrr using decoder 34
931 // 1682: }
932 // 1682: }
933 1, 0, // 1686: case 0x1: {
934 OPC_CheckPredicate, 4, // 1688: check predicate 4
935 OPC_Decode, 197, 5, 35, // 1690: decode to PWRPSRri using decoder 35
936 // 1690: }
937 // 1690: } // switch Inst[13]
938 // 1690: }
939 2, 10, // 1694: case 0x2: {
940 OPC_CheckPredicate, 5, // 1696: check predicate 5
941 OPC_CheckField, 0, 19, 0, // 1698: check Inst[18:0] == 0x0
942 OPC_Decode, 237, 2, 7, // 1702: decode to ALLCLEAN using decoder 7
943 // 1702: }
944 3, 10, // 1706: case 0x3: {
945 OPC_CheckPredicate, 5, // 1708: check predicate 5
946 OPC_CheckField, 0, 19, 0, // 1710: check Inst[18:0] == 0x0
947 OPC_Decode, 189, 5, 7, // 1714: decode to OTHERW using decoder 7
948 // 1714: }
949 4, 10, // 1718: case 0x4: {
950 OPC_CheckPredicate, 5, // 1720: check predicate 5
951 OPC_CheckField, 0, 19, 0, // 1722: check Inst[18:0] == 0x0
952 OPC_Decode, 180, 5, 7, // 1726: decode to NORMALW using decoder 7
953 // 1726: }
954 5, 0, // 1730: case 0x5: {
955 OPC_CheckPredicate, 5, // 1732: check predicate 5
956 OPC_CheckField, 0, 19, 0, // 1734: check Inst[18:0] == 0x0
957 OPC_Decode, 223, 4, 7, // 1738: decode to INVALW using decoder 7
958 // 1738: }
959 // 1738: } // switch Inst[29:25]
960 // 1738: }
961 50, 43, // 1742: case 0x32: {
962 OPC_SwitchField, 13, 1, // 1744: switch Inst[13] {
963 0, 20, // 1747: case 0x0: {
964 OPC_CheckField, 5, 8, 0, // 1749: check Inst[12:5] == 0x0
965 OPC_Scope, 8, // 1753: try {
966 OPC_CheckField, 25, 5, 0, // 1755: check Inst[29:25] == 0x0
967 OPC_Decode, 235, 6, 34, // 1759: decode to WRWIMrr using decoder 34
968 // 1759: } else try {
969 OPC_CheckPredicate, 0, // 1763: check predicate 0
970 OPC_Decode, 229, 6, 36, // 1765: decode to WRPRrr using decoder 36
971 // 1765: }
972 // 1765: }
973 1, 0, // 1769: case 0x1: {
974 OPC_Scope, 8, // 1771: try {
975 OPC_CheckField, 25, 5, 0, // 1773: check Inst[29:25] == 0x0
976 OPC_Decode, 234, 6, 35, // 1777: decode to WRWIMri using decoder 35
977 // 1777: } else try {
978 OPC_CheckPredicate, 0, // 1781: check predicate 0
979 OPC_Decode, 228, 6, 37, // 1783: decode to WRPRri using decoder 37
980 // 1783: }
981 // 1783: }
982 // 1783: } // switch Inst[13]
983 // 1783: }
984 51, 27, // 1787: case 0x33: {
985 OPC_SwitchField, 13, 1, // 1789: switch Inst[13] {
986 0, 12, // 1792: case 0x0: {
987 OPC_CheckField, 25, 5, 0, // 1794: check Inst[29:25] == 0x0
988 OPC_CheckField, 5, 8, 0, // 1798: check Inst[12:5] == 0x0
989 OPC_Decode, 233, 6, 34, // 1802: decode to WRTBRrr using decoder 34
990 // 1802: }
991 1, 0, // 1806: case 0x1: {
992 OPC_CheckField, 25, 5, 0, // 1808: check Inst[29:25] == 0x0
993 OPC_Decode, 232, 6, 35, // 1812: decode to WRTBRri using decoder 35
994 // 1812: }
995 // 1812: } // switch Inst[13]
996 // 1812: }
997 52, 133, 4, // 1816: case 0x34: {
998 OPC_SwitchField, 5, 9, // 1819: switch Inst[13:5] {
999 1, 8, // 1822: case 0x1: {
1000 OPC_CheckField, 14, 5, 0, // 1824: check Inst[18:14] == 0x0
1001 OPC_Decode, 252, 3, 38, // 1828: decode to FMOVS using decoder 38
1002 // 1828: }
1003 2, 10, // 1832: case 0x2: {
1004 OPC_CheckPredicate, 0, // 1834: check predicate 0
1005 OPC_CheckField, 14, 5, 0, // 1836: check Inst[18:14] == 0x0
1006 OPC_Decode, 241, 3, 39, // 1840: decode to FMOVD using decoder 39
1007 // 1840: }
1008 3, 10, // 1844: case 0x3: {
1009 OPC_CheckPredicate, 0, // 1846: check predicate 0
1010 OPC_CheckField, 14, 5, 0, // 1848: check Inst[18:14] == 0x0
1011 OPC_Decode, 245, 3, 40, // 1852: decode to FMOVQ using decoder 40
1012 // 1852: }
1013 5, 8, // 1856: case 0x5: {
1014 OPC_CheckField, 14, 5, 0, // 1858: check Inst[18:14] == 0x0
1015 OPC_Decode, 146, 4, 38, // 1862: decode to FNEGS using decoder 38
1016 // 1862: }
1017 6, 10, // 1866: case 0x6: {
1018 OPC_CheckPredicate, 0, // 1868: check predicate 0
1019 OPC_CheckField, 14, 5, 0, // 1870: check Inst[18:14] == 0x0
1020 OPC_Decode, 144, 4, 39, // 1874: decode to FNEGD using decoder 39
1021 // 1874: }
1022 7, 10, // 1878: case 0x7: {
1023 OPC_CheckPredicate, 0, // 1880: check predicate 0
1024 OPC_CheckField, 14, 5, 0, // 1882: check Inst[18:14] == 0x0
1025 OPC_Decode, 145, 4, 40, // 1886: decode to FNEGQ using decoder 40
1026 // 1886: }
1027 9, 8, // 1890: case 0x9: {
1028 OPC_CheckField, 14, 5, 0, // 1892: check Inst[18:14] == 0x0
1029 OPC_Decode, 186, 3, 38, // 1896: decode to FABSS using decoder 38
1030 // 1896: }
1031 10, 10, // 1900: case 0xa: {
1032 OPC_CheckPredicate, 0, // 1902: check predicate 0
1033 OPC_CheckField, 14, 5, 0, // 1904: check Inst[18:14] == 0x0
1034 OPC_Decode, 184, 3, 39, // 1908: decode to FABSD using decoder 39
1035 // 1908: }
1036 11, 10, // 1912: case 0xb: {
1037 OPC_CheckPredicate, 0, // 1914: check predicate 0
1038 OPC_CheckField, 14, 5, 0, // 1916: check Inst[18:14] == 0x0
1039 OPC_Decode, 185, 3, 40, // 1920: decode to FABSQ using decoder 40
1040 // 1920: }
1041 41, 8, // 1924: case 0x29: {
1042 OPC_CheckField, 14, 5, 0, // 1926: check Inst[18:14] == 0x0
1043 OPC_Decode, 196, 4, 38, // 1930: decode to FSQRTS using decoder 38
1044 // 1930: }
1045 42, 8, // 1934: case 0x2a: {
1046 OPC_CheckField, 14, 5, 0, // 1936: check Inst[18:14] == 0x0
1047 OPC_Decode, 194, 4, 39, // 1940: decode to FSQRTD using decoder 39
1048 // 1940: }
1049 43, 8, // 1944: case 0x2b: {
1050 OPC_CheckField, 14, 5, 0, // 1946: check Inst[18:14] == 0x0
1051 OPC_Decode, 195, 4, 40, // 1950: decode to FSQRTQ using decoder 40
1052 // 1950: }
1053 65, 4, // 1954: case 0x41: {
1054 OPC_Decode, 189, 3, 41, // 1956: decode to FADDS using decoder 41
1055 // 1956: }
1056 66, 4, // 1960: case 0x42: {
1057 OPC_Decode, 187, 3, 42, // 1962: decode to FADDD using decoder 42
1058 // 1962: }
1059 67, 4, // 1966: case 0x43: {
1060 OPC_Decode, 188, 3, 43, // 1968: decode to FADDQ using decoder 43
1061 // 1968: }
1062 69, 4, // 1972: case 0x45: {
1063 OPC_Decode, 211, 4, 41, // 1974: decode to FSUBS using decoder 41
1064 // 1974: }
1065 70, 4, // 1978: case 0x46: {
1066 OPC_Decode, 209, 4, 42, // 1980: decode to FSUBD using decoder 42
1067 // 1980: }
1068 71, 4, // 1984: case 0x47: {
1069 OPC_Decode, 210, 4, 43, // 1986: decode to FSUBQ using decoder 43
1070 // 1986: }
1071 73, 4, // 1990: case 0x49: {
1072 OPC_Decode, 139, 4, 41, // 1992: decode to FMULS using decoder 41
1073 // 1992: }
1074 74, 4, // 1996: case 0x4a: {
1075 OPC_Decode, 135, 4, 42, // 1998: decode to FMULD using decoder 42
1076 // 1998: }
1077 75, 4, // 2002: case 0x4b: {
1078 OPC_Decode, 138, 4, 43, // 2004: decode to FMULQ using decoder 43
1079 // 2004: }
1080 77, 4, // 2008: case 0x4d: {
1081 OPC_Decode, 218, 3, 41, // 2010: decode to FDIVS using decoder 41
1082 // 2010: }
1083 78, 4, // 2014: case 0x4e: {
1084 OPC_Decode, 216, 3, 42, // 2016: decode to FDIVD using decoder 42
1085 // 2016: }
1086 79, 4, // 2020: case 0x4f: {
1087 OPC_Decode, 217, 3, 43, // 2022: decode to FDIVQ using decoder 43
1088 // 2022: }
1089 81, 6, // 2026: case 0x51: {
1090 OPC_CheckPredicate, 6, // 2028: check predicate 6
1091 OPC_Decode, 141, 4, 41, // 2030: decode to FNADDS using decoder 41
1092 // 2030: }
1093 82, 6, // 2034: case 0x52: {
1094 OPC_CheckPredicate, 6, // 2036: check predicate 6
1095 OPC_Decode, 140, 4, 42, // 2038: decode to FNADDD using decoder 42
1096 // 2038: }
1097 89, 6, // 2042: case 0x59: {
1098 OPC_CheckPredicate, 6, // 2044: check predicate 6
1099 OPC_Decode, 154, 4, 41, // 2046: decode to FNMULS using decoder 41
1100 // 2046: }
1101 90, 6, // 2050: case 0x5a: {
1102 OPC_CheckPredicate, 6, // 2052: check predicate 6
1103 OPC_Decode, 153, 4, 42, // 2054: decode to FNMULD using decoder 42
1104 // 2054: }
1105 97, 6, // 2058: case 0x61: {
1106 OPC_CheckPredicate, 6, // 2060: check predicate 6
1107 OPC_Decode, 226, 3, 41, // 2062: decode to FHADDS using decoder 41
1108 // 2062: }
1109 98, 6, // 2066: case 0x62: {
1110 OPC_CheckPredicate, 6, // 2068: check predicate 6
1111 OPC_Decode, 225, 3, 42, // 2070: decode to FHADDD using decoder 42
1112 // 2070: }
1113 101, 6, // 2074: case 0x65: {
1114 OPC_CheckPredicate, 6, // 2076: check predicate 6
1115 OPC_Decode, 228, 3, 41, // 2078: decode to FHSUBS using decoder 41
1116 // 2078: }
1117 102, 6, // 2082: case 0x66: {
1118 OPC_CheckPredicate, 6, // 2084: check predicate 6
1119 OPC_Decode, 227, 3, 42, // 2086: decode to FHSUBD using decoder 42
1120 // 2086: }
1121 105, 4, // 2090: case 0x69: {
1122 OPC_Decode, 193, 4, 44, // 2092: decode to FSMULD using decoder 44
1123 // 2092: }
1124 110, 4, // 2096: case 0x6e: {
1125 OPC_Decode, 219, 3, 45, // 2098: decode to FDMULQ using decoder 45
1126 // 2098: }
1127 113, 6, // 2102: case 0x71: {
1128 OPC_CheckPredicate, 6, // 2104: check predicate 6
1129 OPC_Decode, 148, 4, 41, // 2106: decode to FNHADDS using decoder 41
1130 // 2106: }
1131 114, 6, // 2110: case 0x72: {
1132 OPC_CheckPredicate, 6, // 2112: check predicate 6
1133 OPC_Decode, 147, 4, 42, // 2114: decode to FNHADDD using decoder 42
1134 // 2114: }
1135 121, 6, // 2118: case 0x79: {
1136 OPC_CheckPredicate, 6, // 2120: check predicate 6
1137 OPC_Decode, 161, 4, 44, // 2122: decode to FNSMULD using decoder 44
1138 // 2122: }
1139 129, 1, 10, // 2126: case 0x81: {
1140 OPC_CheckPredicate, 1, // 2129: check predicate 1
1141 OPC_CheckField, 14, 5, 0, // 2131: check Inst[18:14] == 0x0
1142 OPC_Decode, 208, 4, 46, // 2135: decode to FSTOX using decoder 46
1143 // 2135: }
1144 130, 1, 10, // 2139: case 0x82: {
1145 OPC_CheckPredicate, 1, // 2142: check predicate 1
1146 OPC_CheckField, 14, 5, 0, // 2144: check Inst[18:14] == 0x0
1147 OPC_Decode, 223, 3, 39, // 2148: decode to FDTOX using decoder 39
1148 // 2148: }
1149 131, 1, 10, // 2152: case 0x83: {
1150 OPC_CheckPredicate, 1, // 2155: check predicate 1
1151 OPC_CheckField, 14, 5, 0, // 2157: check Inst[18:14] == 0x0
1152 OPC_Decode, 188, 4, 47, // 2161: decode to FQTOX using decoder 47
1153 // 2161: }
1154 132, 1, 10, // 2165: case 0x84: {
1155 OPC_CheckPredicate, 1, // 2168: check predicate 1
1156 OPC_CheckField, 14, 5, 0, // 2170: check Inst[18:14] == 0x0
1157 OPC_Decode, 218, 4, 48, // 2174: decode to FXTOS using decoder 48
1158 // 2174: }
1159 136, 1, 10, // 2178: case 0x88: {
1160 OPC_CheckPredicate, 1, // 2181: check predicate 1
1161 OPC_CheckField, 14, 5, 0, // 2183: check Inst[18:14] == 0x0
1162 OPC_Decode, 216, 4, 39, // 2187: decode to FXTOD using decoder 39
1163 // 2187: }
1164 140, 1, 10, // 2191: case 0x8c: {
1165 OPC_CheckPredicate, 1, // 2194: check predicate 1
1166 OPC_CheckField, 14, 5, 0, // 2196: check Inst[18:14] == 0x0
1167 OPC_Decode, 217, 4, 49, // 2200: decode to FXTOQ using decoder 49
1168 // 2200: }
1169 196, 1, 8, // 2204: case 0xc4: {
1170 OPC_CheckField, 14, 5, 0, // 2207: check Inst[18:14] == 0x0
1171 OPC_Decode, 231, 3, 38, // 2211: decode to FITOS using decoder 38
1172 // 2211: }
1173 198, 1, 8, // 2215: case 0xc6: {
1174 OPC_CheckField, 14, 5, 0, // 2218: check Inst[18:14] == 0x0
1175 OPC_Decode, 222, 3, 48, // 2222: decode to FDTOS using decoder 48
1176 // 2222: }
1177 199, 1, 8, // 2226: case 0xc7: {
1178 OPC_CheckField, 14, 5, 0, // 2229: check Inst[18:14] == 0x0
1179 OPC_Decode, 187, 4, 50, // 2233: decode to FQTOS using decoder 50
1180 // 2233: }
1181 200, 1, 8, // 2237: case 0xc8: {
1182 OPC_CheckField, 14, 5, 0, // 2240: check Inst[18:14] == 0x0
1183 OPC_Decode, 229, 3, 46, // 2244: decode to FITOD using decoder 46
1184 // 2244: }
1185 201, 1, 8, // 2248: case 0xc9: {
1186 OPC_CheckField, 14, 5, 0, // 2251: check Inst[18:14] == 0x0
1187 OPC_Decode, 205, 4, 46, // 2255: decode to FSTOD using decoder 46
1188 // 2255: }
1189 203, 1, 8, // 2259: case 0xcb: {
1190 OPC_CheckField, 14, 5, 0, // 2262: check Inst[18:14] == 0x0
1191 OPC_Decode, 185, 4, 47, // 2266: decode to FQTOD using decoder 47
1192 // 2266: }
1193 204, 1, 8, // 2270: case 0xcc: {
1194 OPC_CheckField, 14, 5, 0, // 2273: check Inst[18:14] == 0x0
1195 OPC_Decode, 230, 3, 51, // 2277: decode to FITOQ using decoder 51
1196 // 2277: }
1197 205, 1, 8, // 2281: case 0xcd: {
1198 OPC_CheckField, 14, 5, 0, // 2284: check Inst[18:14] == 0x0
1199 OPC_Decode, 207, 4, 51, // 2288: decode to FSTOQ using decoder 51
1200 // 2288: }
1201 206, 1, 8, // 2292: case 0xce: {
1202 OPC_CheckField, 14, 5, 0, // 2295: check Inst[18:14] == 0x0
1203 OPC_Decode, 221, 3, 49, // 2299: decode to FDTOQ using decoder 49
1204 // 2299: }
1205 209, 1, 8, // 2303: case 0xd1: {
1206 OPC_CheckField, 14, 5, 0, // 2306: check Inst[18:14] == 0x0
1207 OPC_Decode, 206, 4, 38, // 2310: decode to FSTOI using decoder 38
1208 // 2310: }
1209 210, 1, 8, // 2314: case 0xd2: {
1210 OPC_CheckField, 14, 5, 0, // 2317: check Inst[18:14] == 0x0
1211 OPC_Decode, 220, 3, 48, // 2321: decode to FDTOI using decoder 48
1212 // 2321: }
1213 211, 1, 0, // 2325: case 0xd3: {
1214 OPC_CheckField, 14, 5, 0, // 2328: check Inst[18:14] == 0x0
1215 OPC_Decode, 186, 4, 50, // 2332: decode to FQTOI using decoder 50
1216 // 2332: }
1217 // 2332: } // switch Inst[13:5]
1218 // 2332: }
1219 53, 155, 2, // 2336: case 0x35: {
1220 OPC_SwitchField, 5, 5, // 2339: switch Inst[9:5] {
1221 1, 60, // 2342: case 0x1: {
1222 OPC_SwitchField, 13, 1, // 2344: switch Inst[13] {
1223 0, 26, // 2347: case 0x0: {
1224 OPC_CheckField, 10, 1, 0, // 2349: check Inst[10] == 0x0
1225 OPC_CheckField, 18, 1, 0, // 2353: check Inst[18] == 0x0
1226 OPC_Scope, 10, // 2357: try {
1227 OPC_CheckField, 11, 2, 0, // 2359: check Inst[12:11] == 0x0
1228 OPC_CheckPredicate, 0, // 2363: check predicate 0
1229 OPC_Decode, 253, 3, 52, // 2365: decode to FMOVS_FCC using decoder 52
1230 // 2365: } else try {
1231 OPC_CheckPredicate, 0, // 2369: check predicate 0
1232 OPC_Decode, 223, 6, 53, // 2371: decode to V9FMOVS_FCC using decoder 53
1233 // 2371: }
1234 // 2371: }
1235 1, 0, // 2375: case 0x1: {
1236 OPC_SwitchField, 10, 3, // 2377: switch Inst[12:10] {
1237 0, 10, // 2380: case 0x0: {
1238 OPC_CheckPredicate, 0, // 2382: check predicate 0
1239 OPC_CheckField, 18, 1, 0, // 2384: check Inst[18] == 0x0
1240 OPC_Decode, 254, 3, 52, // 2388: decode to FMOVS_ICC using decoder 52
1241 // 2388: }
1242 4, 0, // 2392: case 0x4: {
1243 OPC_CheckPredicate, 1, // 2394: check predicate 1
1244 OPC_CheckField, 18, 1, 0, // 2396: check Inst[18] == 0x0
1245 OPC_Decode, 255, 3, 52, // 2400: decode to FMOVS_XCC using decoder 52
1246 // 2400: }
1247 // 2400: } // switch Inst[12:10]
1248 // 2400: }
1249 // 2400: } // switch Inst[13]
1250 // 2400: }
1251 2, 60, // 2404: case 0x2: {
1252 OPC_SwitchField, 13, 1, // 2406: switch Inst[13] {
1253 0, 26, // 2409: case 0x0: {
1254 OPC_CheckField, 10, 1, 0, // 2411: check Inst[10] == 0x0
1255 OPC_CheckField, 18, 1, 0, // 2415: check Inst[18] == 0x0
1256 OPC_Scope, 10, // 2419: try {
1257 OPC_CheckField, 11, 2, 0, // 2421: check Inst[12:11] == 0x0
1258 OPC_CheckPredicate, 0, // 2425: check predicate 0
1259 OPC_Decode, 242, 3, 54, // 2427: decode to FMOVD_FCC using decoder 54
1260 // 2427: } else try {
1261 OPC_CheckPredicate, 0, // 2431: check predicate 0
1262 OPC_Decode, 221, 6, 55, // 2433: decode to V9FMOVD_FCC using decoder 55
1263 // 2433: }
1264 // 2433: }
1265 1, 0, // 2437: case 0x1: {
1266 OPC_SwitchField, 10, 3, // 2439: switch Inst[12:10] {
1267 0, 10, // 2442: case 0x0: {
1268 OPC_CheckPredicate, 0, // 2444: check predicate 0
1269 OPC_CheckField, 18, 1, 0, // 2446: check Inst[18] == 0x0
1270 OPC_Decode, 243, 3, 54, // 2450: decode to FMOVD_ICC using decoder 54
1271 // 2450: }
1272 4, 0, // 2454: case 0x4: {
1273 OPC_CheckPredicate, 1, // 2456: check predicate 1
1274 OPC_CheckField, 18, 1, 0, // 2458: check Inst[18] == 0x0
1275 OPC_Decode, 244, 3, 54, // 2462: decode to FMOVD_XCC using decoder 54
1276 // 2462: }
1277 // 2462: } // switch Inst[12:10]
1278 // 2462: }
1279 // 2462: } // switch Inst[13]
1280 // 2462: }
1281 3, 60, // 2466: case 0x3: {
1282 OPC_SwitchField, 13, 1, // 2468: switch Inst[13] {
1283 0, 26, // 2471: case 0x0: {
1284 OPC_CheckField, 10, 1, 0, // 2473: check Inst[10] == 0x0
1285 OPC_CheckField, 18, 1, 0, // 2477: check Inst[18] == 0x0
1286 OPC_Scope, 10, // 2481: try {
1287 OPC_CheckField, 11, 2, 0, // 2483: check Inst[12:11] == 0x0
1288 OPC_CheckPredicate, 0, // 2487: check predicate 0
1289 OPC_Decode, 246, 3, 56, // 2489: decode to FMOVQ_FCC using decoder 56
1290 // 2489: } else try {
1291 OPC_CheckPredicate, 0, // 2493: check predicate 0
1292 OPC_Decode, 222, 6, 57, // 2495: decode to V9FMOVQ_FCC using decoder 57
1293 // 2495: }
1294 // 2495: }
1295 1, 0, // 2499: case 0x1: {
1296 OPC_SwitchField, 10, 3, // 2501: switch Inst[12:10] {
1297 0, 10, // 2504: case 0x0: {
1298 OPC_CheckPredicate, 0, // 2506: check predicate 0
1299 OPC_CheckField, 18, 1, 0, // 2508: check Inst[18] == 0x0
1300 OPC_Decode, 247, 3, 56, // 2512: decode to FMOVQ_ICC using decoder 56
1301 // 2512: }
1302 4, 0, // 2516: case 0x4: {
1303 OPC_CheckPredicate, 1, // 2518: check predicate 1
1304 OPC_CheckField, 18, 1, 0, // 2520: check Inst[18] == 0x0
1305 OPC_Decode, 248, 3, 56, // 2524: decode to FMOVQ_XCC using decoder 56
1306 // 2524: }
1307 // 2524: } // switch Inst[12:10]
1308 // 2524: }
1309 // 2524: } // switch Inst[13]
1310 // 2524: }
1311 5, 10, // 2528: case 0x5: {
1312 OPC_CheckPredicate, 1, // 2530: check predicate 1
1313 OPC_CheckField, 13, 1, 0, // 2532: check Inst[13] == 0x0
1314 OPC_Decode, 251, 3, 58, // 2536: decode to FMOVRS using decoder 58
1315 // 2536: }
1316 6, 10, // 2540: case 0x6: {
1317 OPC_CheckPredicate, 1, // 2542: check predicate 1
1318 OPC_CheckField, 13, 1, 0, // 2544: check Inst[13] == 0x0
1319 OPC_Decode, 249, 3, 59, // 2548: decode to FMOVRD using decoder 59
1320 // 2548: }
1321 7, 8, // 2552: case 0x7: {
1322 OPC_CheckField, 13, 1, 0, // 2554: check Inst[13] == 0x0
1323 OPC_Decode, 250, 3, 60, // 2558: decode to FMOVRQ using decoder 60
1324 // 2558: }
1325 17, 8, // 2562: case 0x11: {
1326 OPC_CheckField, 10, 4, 2, // 2564: check Inst[13:10] == 0x2
1327 OPC_Decode, 220, 6, 61, // 2568: decode to V9FCMPS using decoder 61
1328 // 2568: }
1329 18, 8, // 2572: case 0x12: {
1330 OPC_CheckField, 10, 4, 2, // 2574: check Inst[13:10] == 0x2
1331 OPC_Decode, 215, 6, 62, // 2578: decode to V9FCMPD using decoder 62
1332 // 2578: }
1333 19, 8, // 2582: case 0x13: {
1334 OPC_CheckField, 10, 4, 2, // 2584: check Inst[13:10] == 0x2
1335 OPC_Decode, 219, 6, 63, // 2588: decode to V9FCMPQ using decoder 63
1336 // 2588: }
1337 21, 8, // 2592: case 0x15: {
1338 OPC_CheckField, 10, 4, 2, // 2594: check Inst[13:10] == 0x2
1339 OPC_Decode, 218, 6, 61, // 2598: decode to V9FCMPES using decoder 61
1340 // 2598: }
1341 22, 8, // 2602: case 0x16: {
1342 OPC_CheckField, 10, 4, 2, // 2604: check Inst[13:10] == 0x2
1343 OPC_Decode, 216, 6, 62, // 2608: decode to V9FCMPED using decoder 62
1344 // 2608: }
1345 23, 0, // 2612: case 0x17: {
1346 OPC_CheckField, 10, 4, 2, // 2614: check Inst[13:10] == 0x2
1347 OPC_Decode, 217, 6, 63, // 2618: decode to V9FCMPEQ using decoder 63
1348 // 2618: }
1349 // 2618: } // switch Inst[9:5]
1350 // 2618: }
1351 54, 241, 9, // 2622: case 0x36: {
1352 OPC_SwitchField, 5, 9, // 2625: switch Inst[13:5] {
1353 0, 6, // 2628: case 0x0: {
1354 OPC_CheckPredicate, 7, // 2630: check predicate 7
1355 OPC_Decode, 180, 3, 13, // 2632: decode to EDGE8 using decoder 13
1356 // 2632: }
1357 1, 6, // 2636: case 0x1: {
1358 OPC_CheckPredicate, 8, // 2638: check predicate 8
1359 OPC_Decode, 183, 3, 13, // 2640: decode to EDGE8N using decoder 13
1360 // 2640: }
1361 2, 6, // 2644: case 0x2: {
1362 OPC_CheckPredicate, 7, // 2646: check predicate 7
1363 OPC_Decode, 181, 3, 13, // 2648: decode to EDGE8L using decoder 13
1364 // 2648: }
1365 3, 6, // 2652: case 0x3: {
1366 OPC_CheckPredicate, 8, // 2654: check predicate 8
1367 OPC_Decode, 182, 3, 13, // 2656: decode to EDGE8LN using decoder 13
1368 // 2656: }
1369 4, 6, // 2660: case 0x4: {
1370 OPC_CheckPredicate, 7, // 2662: check predicate 7
1371 OPC_Decode, 172, 3, 13, // 2664: decode to EDGE16 using decoder 13
1372 // 2664: }
1373 5, 6, // 2668: case 0x5: {
1374 OPC_CheckPredicate, 8, // 2670: check predicate 8
1375 OPC_Decode, 175, 3, 13, // 2672: decode to EDGE16N using decoder 13
1376 // 2672: }
1377 6, 6, // 2676: case 0x6: {
1378 OPC_CheckPredicate, 7, // 2678: check predicate 7
1379 OPC_Decode, 173, 3, 13, // 2680: decode to EDGE16L using decoder 13
1380 // 2680: }
1381 7, 6, // 2684: case 0x7: {
1382 OPC_CheckPredicate, 8, // 2686: check predicate 8
1383 OPC_Decode, 174, 3, 13, // 2688: decode to EDGE16LN using decoder 13
1384 // 2688: }
1385 8, 6, // 2692: case 0x8: {
1386 OPC_CheckPredicate, 7, // 2694: check predicate 7
1387 OPC_Decode, 176, 3, 13, // 2696: decode to EDGE32 using decoder 13
1388 // 2696: }
1389 9, 6, // 2700: case 0x9: {
1390 OPC_CheckPredicate, 8, // 2702: check predicate 8
1391 OPC_Decode, 179, 3, 13, // 2704: decode to EDGE32N using decoder 13
1392 // 2704: }
1393 10, 6, // 2708: case 0xa: {
1394 OPC_CheckPredicate, 7, // 2710: check predicate 7
1395 OPC_Decode, 177, 3, 13, // 2712: decode to EDGE32L using decoder 13
1396 // 2712: }
1397 11, 6, // 2716: case 0xb: {
1398 OPC_CheckPredicate, 8, // 2718: check predicate 8
1399 OPC_Decode, 178, 3, 13, // 2720: decode to EDGE32LN using decoder 13
1400 // 2720: }
1401 16, 6, // 2724: case 0x10: {
1402 OPC_CheckPredicate, 7, // 2726: check predicate 7
1403 OPC_Decode, 248, 2, 13, // 2728: decode to ARRAY8 using decoder 13
1404 // 2728: }
1405 17, 6, // 2732: case 0x11: {
1406 OPC_CheckPredicate, 6, // 2734: check predicate 6
1407 OPC_Decode, 220, 2, 13, // 2736: decode to ADDXC using decoder 13
1408 // 2736: }
1409 18, 6, // 2740: case 0x12: {
1410 OPC_CheckPredicate, 7, // 2742: check predicate 7
1411 OPC_Decode, 246, 2, 13, // 2744: decode to ARRAY16 using decoder 13
1412 // 2744: }
1413 19, 6, // 2748: case 0x13: {
1414 OPC_CheckPredicate, 6, // 2750: check predicate 6
1415 OPC_Decode, 221, 2, 13, // 2752: decode to ADDXCCC using decoder 13
1416 // 2752: }
1417 20, 6, // 2756: case 0x14: {
1418 OPC_CheckPredicate, 7, // 2758: check predicate 7
1419 OPC_Decode, 247, 2, 13, // 2760: decode to ARRAY32 using decoder 13
1420 // 2760: }
1421 22, 6, // 2764: case 0x16: {
1422 OPC_CheckPredicate, 6, // 2766: check predicate 6
1423 OPC_Decode, 211, 6, 13, // 2768: decode to UMULXHI using decoder 13
1424 // 2768: }
1425 23, 10, // 2772: case 0x17: {
1426 OPC_CheckPredicate, 6, // 2774: check predicate 6
1427 OPC_CheckField, 14, 5, 0, // 2776: check Inst[18:14] == 0x0
1428 OPC_Decode, 156, 5, 64, // 2780: decode to LZCNT using decoder 64
1429 // 2780: }
1430 24, 6, // 2784: case 0x18: {
1431 OPC_CheckPredicate, 7, // 2786: check predicate 7
1432 OPC_Decode, 235, 2, 13, // 2788: decode to ALIGNADDR using decoder 13
1433 // 2788: }
1434 25, 6, // 2792: case 0x19: {
1435 OPC_CheckPredicate, 8, // 2794: check predicate 8
1436 OPC_Decode, 254, 2, 13, // 2796: decode to BMASK using decoder 13
1437 // 2796: }
1438 26, 6, // 2800: case 0x1a: {
1439 OPC_CheckPredicate, 7, // 2802: check predicate 7
1440 OPC_Decode, 236, 2, 13, // 2804: decode to ALIGNADDRL using decoder 13
1441 // 2804: }
1442 27, 14, // 2808: case 0x1b: {
1443 OPC_CheckPredicate, 6, // 2810: check predicate 6
1444 OPC_CheckField, 25, 5, 0, // 2812: check Inst[29:25] == 0x0
1445 OPC_CheckField, 14, 5, 0, // 2816: check Inst[18:14] == 0x0
1446 OPC_Decode, 159, 3, 65, // 2820: decode to CMASK8 using decoder 65
1447 // 2820: }
1448 29, 14, // 2824: case 0x1d: {
1449 OPC_CheckPredicate, 6, // 2826: check predicate 6
1450 OPC_CheckField, 25, 5, 0, // 2828: check Inst[29:25] == 0x0
1451 OPC_CheckField, 14, 5, 0, // 2832: check Inst[18:14] == 0x0
1452 OPC_Decode, 157, 3, 65, // 2836: decode to CMASK16 using decoder 65
1453 // 2836: }
1454 31, 14, // 2840: case 0x1f: {
1455 OPC_CheckPredicate, 6, // 2842: check predicate 6
1456 OPC_CheckField, 25, 5, 0, // 2844: check Inst[29:25] == 0x0
1457 OPC_CheckField, 14, 5, 0, // 2848: check Inst[18:14] == 0x0
1458 OPC_Decode, 158, 3, 65, // 2852: decode to CMASK32 using decoder 65
1459 // 2852: }
1460 32, 6, // 2856: case 0x20: {
1461 OPC_CheckPredicate, 7, // 2858: check predicate 7
1462 OPC_Decode, 208, 3, 66, // 2860: decode to FCMPLE16 using decoder 66
1463 // 2860: }
1464 33, 6, // 2864: case 0x21: {
1465 OPC_CheckPredicate, 6, // 2866: check predicate 6
1466 OPC_Decode, 191, 4, 42, // 2868: decode to FSLL16 using decoder 42
1467 // 2868: }
1468 34, 6, // 2872: case 0x22: {
1469 OPC_CheckPredicate, 7, // 2874: check predicate 7
1470 OPC_Decode, 210, 3, 66, // 2876: decode to FCMPNE16 using decoder 66
1471 // 2876: }
1472 35, 6, // 2880: case 0x23: {
1473 OPC_CheckPredicate, 6, // 2882: check predicate 6
1474 OPC_Decode, 203, 4, 42, // 2884: decode to FSRL16 using decoder 42
1475 // 2884: }
1476 36, 6, // 2888: case 0x24: {
1477 OPC_CheckPredicate, 7, // 2890: check predicate 7
1478 OPC_Decode, 209, 3, 66, // 2892: decode to FCMPLE32 using decoder 66
1479 // 2892: }
1480 37, 6, // 2896: case 0x25: {
1481 OPC_CheckPredicate, 6, // 2898: check predicate 6
1482 OPC_Decode, 192, 4, 42, // 2900: decode to FSLL32 using decoder 42
1483 // 2900: }
1484 38, 6, // 2904: case 0x26: {
1485 OPC_CheckPredicate, 7, // 2906: check predicate 7
1486 OPC_Decode, 211, 3, 66, // 2908: decode to FCMPNE32 using decoder 66
1487 // 2908: }
1488 39, 6, // 2912: case 0x27: {
1489 OPC_CheckPredicate, 6, // 2914: check predicate 6
1490 OPC_Decode, 204, 4, 42, // 2916: decode to FSRL32 using decoder 42
1491 // 2916: }
1492 40, 6, // 2920: case 0x28: {
1493 OPC_CheckPredicate, 7, // 2922: check predicate 7
1494 OPC_Decode, 206, 3, 66, // 2924: decode to FCMPGT16 using decoder 66
1495 // 2924: }
1496 41, 6, // 2928: case 0x29: {
1497 OPC_CheckPredicate, 6, // 2930: check predicate 6
1498 OPC_Decode, 189, 4, 42, // 2932: decode to FSLAS16 using decoder 42
1499 // 2932: }
1500 42, 6, // 2936: case 0x2a: {
1501 OPC_CheckPredicate, 7, // 2938: check predicate 7
1502 OPC_Decode, 204, 3, 66, // 2940: decode to FCMPEQ16 using decoder 66
1503 // 2940: }
1504 43, 6, // 2944: case 0x2b: {
1505 OPC_CheckPredicate, 6, // 2946: check predicate 6
1506 OPC_Decode, 197, 4, 42, // 2948: decode to FSRA16 using decoder 42
1507 // 2948: }
1508 44, 6, // 2952: case 0x2c: {
1509 OPC_CheckPredicate, 7, // 2954: check predicate 7
1510 OPC_Decode, 207, 3, 66, // 2956: decode to FCMPGT32 using decoder 66
1511 // 2956: }
1512 45, 6, // 2960: case 0x2d: {
1513 OPC_CheckPredicate, 6, // 2962: check predicate 6
1514 OPC_Decode, 190, 4, 42, // 2964: decode to FSLAS32 using decoder 42
1515 // 2964: }
1516 46, 6, // 2968: case 0x2e: {
1517 OPC_CheckPredicate, 7, // 2970: check predicate 7
1518 OPC_Decode, 205, 3, 66, // 2972: decode to FCMPEQ32 using decoder 66
1519 // 2972: }
1520 47, 6, // 2976: case 0x2f: {
1521 OPC_CheckPredicate, 6, // 2978: check predicate 6
1522 OPC_Decode, 198, 4, 42, // 2980: decode to FSRA32 using decoder 42
1523 // 2980: }
1524 49, 6, // 2984: case 0x31: {
1525 OPC_CheckPredicate, 7, // 2986: check predicate 7
1526 OPC_Decode, 132, 4, 67, // 2988: decode to FMUL8X16 using decoder 67
1527 // 2988: }
1528 51, 6, // 2992: case 0x33: {
1529 OPC_CheckPredicate, 7, // 2994: check predicate 7
1530 OPC_Decode, 134, 4, 44, // 2996: decode to FMUL8X16AU using decoder 44
1531 // 2996: }
1532 53, 6, // 3000: case 0x35: {
1533 OPC_CheckPredicate, 7, // 3002: check predicate 7
1534 OPC_Decode, 133, 4, 44, // 3004: decode to FMUL8X16AL using decoder 44
1535 // 3004: }
1536 54, 6, // 3008: case 0x36: {
1537 OPC_CheckPredicate, 7, // 3010: check predicate 7
1538 OPC_Decode, 130, 4, 42, // 3012: decode to FMUL8SUX16 using decoder 42
1539 // 3012: }
1540 55, 6, // 3016: case 0x37: {
1541 OPC_CheckPredicate, 7, // 3018: check predicate 7
1542 OPC_Decode, 131, 4, 42, // 3020: decode to FMUL8ULX16 using decoder 42
1543 // 3020: }
1544 56, 6, // 3024: case 0x38: {
1545 OPC_CheckPredicate, 7, // 3026: check predicate 7
1546 OPC_Decode, 136, 4, 44, // 3028: decode to FMULD8SUX16 using decoder 44
1547 // 3028: }
1548 57, 6, // 3032: case 0x39: {
1549 OPC_CheckPredicate, 7, // 3034: check predicate 7
1550 OPC_Decode, 137, 4, 44, // 3036: decode to FMULD8ULX16 using decoder 44
1551 // 3036: }
1552 58, 6, // 3040: case 0x3a: {
1553 OPC_CheckPredicate, 7, // 3042: check predicate 7
1554 OPC_Decode, 171, 4, 42, // 3044: decode to FPACK32 using decoder 42
1555 // 3044: }
1556 59, 10, // 3048: case 0x3b: {
1557 OPC_CheckPredicate, 7, // 3050: check predicate 7
1558 OPC_CheckField, 14, 5, 0, // 3052: check Inst[18:14] == 0x0
1559 OPC_Decode, 170, 4, 39, // 3056: decode to FPACK16 using decoder 39
1560 // 3056: }
1561 61, 10, // 3060: case 0x3d: {
1562 OPC_CheckPredicate, 7, // 3062: check predicate 7
1563 OPC_CheckField, 14, 5, 0, // 3064: check Inst[18:14] == 0x0
1564 OPC_Decode, 172, 4, 48, // 3068: decode to FPACKFIX using decoder 48
1565 // 3068: }
1566 62, 6, // 3072: case 0x3e: {
1567 OPC_CheckPredicate, 7, // 3074: check predicate 7
1568 OPC_Decode, 190, 5, 42, // 3076: decode to PDIST using decoder 42
1569 // 3076: }
1570 63, 6, // 3080: case 0x3f: {
1571 OPC_CheckPredicate, 6, // 3082: check predicate 6
1572 OPC_Decode, 191, 5, 66, // 3084: decode to PDISTN using decoder 66
1573 // 3084: }
1574 64, 6, // 3088: case 0x40: {
1575 OPC_CheckPredicate, 6, // 3090: check predicate 6
1576 OPC_Decode, 240, 3, 42, // 3092: decode to FMEAN16 using decoder 42
1577 // 3092: }
1578 66, 6, // 3096: case 0x42: {
1579 OPC_CheckPredicate, 6, // 3098: check predicate 6
1580 OPC_Decode, 177, 4, 42, // 3100: decode to FPADD64 using decoder 42
1581 // 3100: }
1582 68, 6, // 3104: case 0x44: {
1583 OPC_CheckPredicate, 6, // 3106: check predicate 6
1584 OPC_Decode, 201, 3, 42, // 3108: decode to FCHKSM16 using decoder 42
1585 // 3108: }
1586 72, 6, // 3112: case 0x48: {
1587 OPC_CheckPredicate, 7, // 3114: check predicate 7
1588 OPC_Decode, 190, 3, 42, // 3116: decode to FALIGNADATA using decoder 42
1589 // 3116: }
1590 75, 6, // 3120: case 0x4b: {
1591 OPC_CheckPredicate, 7, // 3122: check predicate 7
1592 OPC_Decode, 180, 4, 44, // 3124: decode to FPMERGE using decoder 44
1593 // 3124: }
1594 76, 6, // 3128: case 0x4c: {
1595 OPC_CheckPredicate, 8, // 3130: check predicate 8
1596 OPC_Decode, 143, 3, 42, // 3132: decode to BSHUFFLE using decoder 42
1597 // 3132: }
1598 77, 10, // 3136: case 0x4d: {
1599 OPC_CheckPredicate, 7, // 3138: check predicate 7
1600 OPC_CheckField, 14, 5, 0, // 3140: check Inst[18:14] == 0x0
1601 OPC_Decode, 224, 3, 46, // 3144: decode to FEXPAND using decoder 46
1602 // 3144: }
1603 80, 6, // 3148: case 0x50: {
1604 OPC_CheckPredicate, 7, // 3150: check predicate 7
1605 OPC_Decode, 173, 4, 42, // 3152: decode to FPADD16 using decoder 42
1606 // 3152: }
1607 81, 6, // 3156: case 0x51: {
1608 OPC_CheckPredicate, 7, // 3158: check predicate 7
1609 OPC_Decode, 174, 4, 41, // 3160: decode to FPADD16S using decoder 41
1610 // 3160: }
1611 82, 6, // 3164: case 0x52: {
1612 OPC_CheckPredicate, 7, // 3166: check predicate 7
1613 OPC_Decode, 175, 4, 42, // 3168: decode to FPADD32 using decoder 42
1614 // 3168: }
1615 83, 6, // 3172: case 0x53: {
1616 OPC_CheckPredicate, 7, // 3174: check predicate 7
1617 OPC_Decode, 176, 4, 41, // 3176: decode to FPADD32S using decoder 41
1618 // 3176: }
1619 84, 6, // 3180: case 0x54: {
1620 OPC_CheckPredicate, 7, // 3182: check predicate 7
1621 OPC_Decode, 181, 4, 42, // 3184: decode to FPSUB16 using decoder 42
1622 // 3184: }
1623 85, 6, // 3188: case 0x55: {
1624 OPC_CheckPredicate, 7, // 3190: check predicate 7
1625 OPC_Decode, 182, 4, 41, // 3192: decode to FPSUB16S using decoder 41
1626 // 3192: }
1627 86, 6, // 3196: case 0x56: {
1628 OPC_CheckPredicate, 7, // 3198: check predicate 7
1629 OPC_Decode, 183, 4, 42, // 3200: decode to FPSUB32 using decoder 42
1630 // 3200: }
1631 87, 6, // 3204: case 0x57: {
1632 OPC_CheckPredicate, 7, // 3206: check predicate 7
1633 OPC_Decode, 184, 4, 41, // 3208: decode to FPSUB32S using decoder 41
1634 // 3208: }
1635 96, 14, // 3212: case 0x60: {
1636 OPC_CheckPredicate, 7, // 3214: check predicate 7
1637 OPC_CheckField, 14, 5, 0, // 3216: check Inst[18:14] == 0x0
1638 OPC_CheckField, 0, 5, 0, // 3220: check Inst[4:0] == 0x0
1639 OPC_Decode, 219, 4, 68, // 3224: decode to FZERO using decoder 68
1640 // 3224: }
1641 97, 14, // 3228: case 0x61: {
1642 OPC_CheckPredicate, 7, // 3230: check predicate 7
1643 OPC_CheckField, 14, 5, 0, // 3232: check Inst[18:14] == 0x0
1644 OPC_CheckField, 0, 5, 0, // 3236: check Inst[4:0] == 0x0
1645 OPC_Decode, 220, 4, 69, // 3240: decode to FZEROS using decoder 69
1646 // 3240: }
1647 98, 6, // 3244: case 0x62: {
1648 OPC_CheckPredicate, 7, // 3246: check predicate 7
1649 OPC_Decode, 155, 4, 42, // 3248: decode to FNOR using decoder 42
1650 // 3248: }
1651 99, 6, // 3252: case 0x63: {
1652 OPC_CheckPredicate, 7, // 3254: check predicate 7
1653 OPC_Decode, 156, 4, 41, // 3256: decode to FNORS using decoder 41
1654 // 3256: }
1655 100, 6, // 3260: case 0x64: {
1656 OPC_CheckPredicate, 7, // 3262: check predicate 7
1657 OPC_Decode, 194, 3, 42, // 3264: decode to FANDNOT2 using decoder 42
1658 // 3264: }
1659 101, 6, // 3268: case 0x65: {
1660 OPC_CheckPredicate, 7, // 3270: check predicate 7
1661 OPC_Decode, 195, 3, 41, // 3272: decode to FANDNOT2S using decoder 41
1662 // 3272: }
1663 102, 10, // 3276: case 0x66: {
1664 OPC_CheckPredicate, 7, // 3278: check predicate 7
1665 OPC_CheckField, 14, 5, 0, // 3280: check Inst[18:14] == 0x0
1666 OPC_Decode, 159, 4, 39, // 3284: decode to FNOT2 using decoder 39
1667 // 3284: }
1668 103, 10, // 3288: case 0x67: {
1669 OPC_CheckPredicate, 7, // 3290: check predicate 7
1670 OPC_CheckField, 14, 5, 0, // 3292: check Inst[18:14] == 0x0
1671 OPC_Decode, 160, 4, 38, // 3296: decode to FNOT2S using decoder 38
1672 // 3296: }
1673 104, 6, // 3300: case 0x68: {
1674 OPC_CheckPredicate, 7, // 3302: check predicate 7
1675 OPC_Decode, 192, 3, 42, // 3304: decode to FANDNOT1 using decoder 42
1676 // 3304: }
1677 105, 6, // 3308: case 0x69: {
1678 OPC_CheckPredicate, 7, // 3310: check predicate 7
1679 OPC_Decode, 193, 3, 41, // 3312: decode to FANDNOT1S using decoder 41
1680 // 3312: }
1681 106, 10, // 3316: case 0x6a: {
1682 OPC_CheckPredicate, 7, // 3318: check predicate 7
1683 OPC_CheckField, 0, 5, 0, // 3320: check Inst[4:0] == 0x0
1684 OPC_Decode, 157, 4, 70, // 3324: decode to FNOT1 using decoder 70
1685 // 3324: }
1686 107, 10, // 3328: case 0x6b: {
1687 OPC_CheckPredicate, 7, // 3330: check predicate 7
1688 OPC_CheckField, 0, 5, 0, // 3332: check Inst[4:0] == 0x0
1689 OPC_Decode, 158, 4, 71, // 3336: decode to FNOT1S using decoder 71
1690 // 3336: }
1691 108, 6, // 3340: case 0x6c: {
1692 OPC_CheckPredicate, 7, // 3342: check predicate 7
1693 OPC_Decode, 214, 4, 42, // 3344: decode to FXOR using decoder 42
1694 // 3344: }
1695 109, 6, // 3348: case 0x6d: {
1696 OPC_CheckPredicate, 7, // 3350: check predicate 7
1697 OPC_Decode, 215, 4, 41, // 3352: decode to FXORS using decoder 41
1698 // 3352: }
1699 110, 6, // 3356: case 0x6e: {
1700 OPC_CheckPredicate, 7, // 3358: check predicate 7
1701 OPC_Decode, 142, 4, 42, // 3360: decode to FNAND using decoder 42
1702 // 3360: }
1703 111, 6, // 3364: case 0x6f: {
1704 OPC_CheckPredicate, 7, // 3366: check predicate 7
1705 OPC_Decode, 143, 4, 41, // 3368: decode to FNANDS using decoder 41
1706 // 3368: }
1707 112, 6, // 3372: case 0x70: {
1708 OPC_CheckPredicate, 7, // 3374: check predicate 7
1709 OPC_Decode, 191, 3, 42, // 3376: decode to FAND using decoder 42
1710 // 3376: }
1711 113, 6, // 3380: case 0x71: {
1712 OPC_CheckPredicate, 7, // 3382: check predicate 7
1713 OPC_Decode, 196, 3, 41, // 3384: decode to FANDS using decoder 41
1714 // 3384: }
1715 114, 6, // 3388: case 0x72: {
1716 OPC_CheckPredicate, 7, // 3390: check predicate 7
1717 OPC_Decode, 212, 4, 42, // 3392: decode to FXNOR using decoder 42
1718 // 3392: }
1719 115, 6, // 3396: case 0x73: {
1720 OPC_CheckPredicate, 7, // 3398: check predicate 7
1721 OPC_Decode, 213, 4, 41, // 3400: decode to FXNORS using decoder 41
1722 // 3400: }
1723 116, 10, // 3404: case 0x74: {
1724 OPC_CheckPredicate, 7, // 3406: check predicate 7
1725 OPC_CheckField, 0, 5, 0, // 3408: check Inst[4:0] == 0x0
1726 OPC_Decode, 199, 4, 70, // 3412: decode to FSRC1 using decoder 70
1727 // 3412: }
1728 117, 10, // 3416: case 0x75: {
1729 OPC_CheckPredicate, 7, // 3418: check predicate 7
1730 OPC_CheckField, 0, 5, 0, // 3420: check Inst[4:0] == 0x0
1731 OPC_Decode, 200, 4, 71, // 3424: decode to FSRC1S using decoder 71
1732 // 3424: }
1733 118, 6, // 3428: case 0x76: {
1734 OPC_CheckPredicate, 7, // 3430: check predicate 7
1735 OPC_Decode, 167, 4, 42, // 3432: decode to FORNOT2 using decoder 42
1736 // 3432: }
1737 119, 6, // 3436: case 0x77: {
1738 OPC_CheckPredicate, 7, // 3438: check predicate 7
1739 OPC_Decode, 168, 4, 41, // 3440: decode to FORNOT2S using decoder 41
1740 // 3440: }
1741 120, 10, // 3444: case 0x78: {
1742 OPC_CheckPredicate, 7, // 3446: check predicate 7
1743 OPC_CheckField, 14, 5, 0, // 3448: check Inst[18:14] == 0x0
1744 OPC_Decode, 201, 4, 39, // 3452: decode to FSRC2 using decoder 39
1745 // 3452: }
1746 121, 10, // 3456: case 0x79: {
1747 OPC_CheckPredicate, 7, // 3458: check predicate 7
1748 OPC_CheckField, 14, 5, 0, // 3460: check Inst[18:14] == 0x0
1749 OPC_Decode, 202, 4, 38, // 3464: decode to FSRC2S using decoder 38
1750 // 3464: }
1751 122, 6, // 3468: case 0x7a: {
1752 OPC_CheckPredicate, 7, // 3470: check predicate 7
1753 OPC_Decode, 165, 4, 42, // 3472: decode to FORNOT1 using decoder 42
1754 // 3472: }
1755 123, 6, // 3476: case 0x7b: {
1756 OPC_CheckPredicate, 7, // 3478: check predicate 7
1757 OPC_Decode, 166, 4, 41, // 3480: decode to FORNOT1S using decoder 41
1758 // 3480: }
1759 124, 6, // 3484: case 0x7c: {
1760 OPC_CheckPredicate, 7, // 3486: check predicate 7
1761 OPC_Decode, 164, 4, 42, // 3488: decode to FOR using decoder 42
1762 // 3488: }
1763 125, 6, // 3492: case 0x7d: {
1764 OPC_CheckPredicate, 7, // 3494: check predicate 7
1765 OPC_Decode, 169, 4, 41, // 3496: decode to FORS using decoder 41
1766 // 3496: }
1767 126, 14, // 3500: case 0x7e: {
1768 OPC_CheckPredicate, 7, // 3502: check predicate 7
1769 OPC_CheckField, 14, 5, 0, // 3504: check Inst[18:14] == 0x0
1770 OPC_CheckField, 0, 5, 0, // 3508: check Inst[4:0] == 0x0
1771 OPC_Decode, 162, 4, 68, // 3512: decode to FONE using decoder 68
1772 // 3512: }
1773 127, 14, // 3516: case 0x7f: {
1774 OPC_CheckPredicate, 7, // 3518: check predicate 7
1775 OPC_CheckField, 14, 5, 0, // 3520: check Inst[18:14] == 0x0
1776 OPC_CheckField, 0, 5, 0, // 3524: check Inst[4:0] == 0x0
1777 OPC_Decode, 163, 4, 69, // 3528: decode to FONES using decoder 69
1778 // 3528: }
1779 128, 1, 18, // 3532: case 0x80: {
1780 OPC_CheckPredicate, 7, // 3535: check predicate 7
1781 OPC_CheckField, 25, 5, 0, // 3537: check Inst[29:25] == 0x0
1782 OPC_CheckField, 14, 5, 0, // 3541: check Inst[18:14] == 0x0
1783 OPC_CheckField, 0, 5, 0, // 3545: check Inst[4:0] == 0x0
1784 OPC_Decode, 226, 5, 7, // 3549: decode to SHUTDOWN using decoder 7
1785 // 3549: }
1786 129, 1, 18, // 3553: case 0x81: {
1787 OPC_CheckPredicate, 8, // 3556: check predicate 8
1788 OPC_CheckField, 25, 5, 0, // 3558: check Inst[29:25] == 0x0
1789 OPC_CheckField, 14, 5, 0, // 3562: check Inst[18:14] == 0x0
1790 OPC_CheckField, 3, 2, 0, // 3566: check Inst[4:3] == 0x0
1791 OPC_Decode, 227, 5, 72, // 3570: decode to SIAM using decoder 72
1792 // 3570: }
1793 144, 2, 10, // 3574: case 0x110: {
1794 OPC_CheckPredicate, 6, // 3577: check predicate 6
1795 OPC_CheckField, 14, 5, 0, // 3579: check Inst[18:14] == 0x0
1796 OPC_Decode, 161, 5, 73, // 3583: decode to MOVDTOX using decoder 73
1797 // 3583: }
1798 145, 2, 10, // 3587: case 0x111: {
1799 OPC_CheckPredicate, 6, // 3590: check predicate 6
1800 OPC_CheckField, 14, 5, 0, // 3592: check Inst[18:14] == 0x0
1801 OPC_Decode, 169, 5, 74, // 3596: decode to MOVSTOUW using decoder 74
1802 // 3596: }
1803 147, 2, 10, // 3600: case 0x113: {
1804 OPC_CheckPredicate, 6, // 3603: check predicate 6
1805 OPC_CheckField, 14, 5, 0, // 3605: check Inst[18:14] == 0x0
1806 OPC_Decode, 168, 5, 74, // 3609: decode to MOVSTOSW using decoder 74
1807 // 3609: }
1808 149, 2, 6, // 3613: case 0x115: {
1809 OPC_CheckPredicate, 6, // 3616: check predicate 6
1810 OPC_Decode, 236, 6, 13, // 3618: decode to XMULX using decoder 13
1811 // 3618: }
1812 150, 2, 6, // 3622: case 0x116: {
1813 OPC_CheckPredicate, 6, // 3625: check predicate 6
1814 OPC_Decode, 237, 6, 13, // 3627: decode to XMULXHI using decoder 13
1815 // 3627: }
1816 152, 2, 10, // 3631: case 0x118: {
1817 OPC_CheckPredicate, 6, // 3634: check predicate 6
1818 OPC_CheckField, 14, 5, 0, // 3636: check Inst[18:14] == 0x0
1819 OPC_Decode, 173, 5, 75, // 3640: decode to MOVXTOD using decoder 75
1820 // 3640: }
1821 153, 2, 10, // 3644: case 0x119: {
1822 OPC_CheckPredicate, 6, // 3647: check predicate 6
1823 OPC_CheckField, 14, 5, 0, // 3649: check Inst[18:14] == 0x0
1824 OPC_Decode, 170, 5, 76, // 3653: decode to MOVWTOS using decoder 76
1825 // 3653: }
1826 176, 2, 6, // 3657: case 0x130: {
1827 OPC_CheckPredicate, 3, // 3660: check predicate 3
1828 OPC_Decode, 232, 2, 42, // 3662: decode to AES_KEXPAND0 using decoder 42
1829 // 3662: }
1830 177, 2, 6, // 3666: case 0x131: {
1831 OPC_CheckPredicate, 3, // 3669: check predicate 3
1832 OPC_Decode, 234, 2, 42, // 3671: decode to AES_KEXPAND2 using decoder 42
1833 // 3671: }
1834 180, 2, 10, // 3675: case 0x134: {
1835 OPC_CheckPredicate, 3, // 3678: check predicate 3
1836 OPC_CheckField, 0, 5, 0, // 3680: check Inst[4:0] == 0x0
1837 OPC_Decode, 168, 3, 70, // 3684: decode to DES_IP using decoder 70
1838 // 3684: }
1839 181, 2, 10, // 3688: case 0x135: {
1840 OPC_CheckPredicate, 3, // 3691: check predicate 3
1841 OPC_CheckField, 0, 5, 0, // 3693: check Inst[4:0] == 0x0
1842 OPC_Decode, 167, 3, 70, // 3697: decode to DES_IIP using decoder 70
1843 // 3697: }
1844 182, 2, 6, // 3701: case 0x136: {
1845 OPC_CheckPredicate, 3, // 3704: check predicate 3
1846 OPC_Decode, 169, 3, 77, // 3706: decode to DES_KEXPAND using decoder 77
1847 // 3706: }
1848 188, 2, 6, // 3710: case 0x13c: {
1849 OPC_CheckPredicate, 3, // 3713: check predicate 3
1850 OPC_Decode, 151, 3, 42, // 3715: decode to CAMELLIA_FL using decoder 42
1851 // 3715: }
1852 189, 2, 6, // 3719: case 0x13d: {
1853 OPC_CheckPredicate, 3, // 3722: check predicate 3
1854 OPC_Decode, 152, 3, 42, // 3724: decode to CAMELLIA_FLI using decoder 42
1855 // 3724: }
1856 192, 2, 18, // 3728: case 0x140: {
1857 OPC_CheckPredicate, 3, // 3731: check predicate 3
1858 OPC_CheckField, 25, 5, 0, // 3733: check Inst[29:25] == 0x0
1859 OPC_CheckField, 14, 5, 0, // 3737: check Inst[18:14] == 0x0
1860 OPC_CheckField, 0, 5, 0, // 3741: check Inst[4:0] == 0x0
1861 OPC_Decode, 157, 5, 7, // 3745: decode to MD5 using decoder 7
1862 // 3745: }
1863 193, 2, 18, // 3749: case 0x141: {
1864 OPC_CheckPredicate, 3, // 3752: check predicate 3
1865 OPC_CheckField, 25, 5, 0, // 3754: check Inst[29:25] == 0x0
1866 OPC_CheckField, 14, 5, 0, // 3758: check Inst[18:14] == 0x0
1867 OPC_CheckField, 0, 5, 0, // 3762: check Inst[4:0] == 0x0
1868 OPC_Decode, 223, 5, 7, // 3766: decode to SHA1 using decoder 7
1869 // 3766: }
1870 194, 2, 18, // 3770: case 0x142: {
1871 OPC_CheckPredicate, 3, // 3773: check predicate 3
1872 OPC_CheckField, 25, 5, 0, // 3775: check Inst[29:25] == 0x0
1873 OPC_CheckField, 14, 5, 0, // 3779: check Inst[18:14] == 0x0
1874 OPC_CheckField, 0, 5, 0, // 3783: check Inst[4:0] == 0x0
1875 OPC_Decode, 224, 5, 7, // 3787: decode to SHA256 using decoder 7
1876 // 3787: }
1877 195, 2, 18, // 3791: case 0x143: {
1878 OPC_CheckPredicate, 3, // 3794: check predicate 3
1879 OPC_CheckField, 25, 5, 0, // 3796: check Inst[29:25] == 0x0
1880 OPC_CheckField, 14, 5, 0, // 3800: check Inst[18:14] == 0x0
1881 OPC_CheckField, 0, 5, 0, // 3804: check Inst[4:0] == 0x0
1882 OPC_Decode, 225, 5, 7, // 3808: decode to SHA512 using decoder 7
1883 // 3808: }
1884 199, 2, 6, // 3812: case 0x147: {
1885 OPC_CheckPredicate, 3, // 3815: check predicate 3
1886 OPC_Decode, 162, 3, 42, // 3817: decode to CRC32C using decoder 42
1887 // 3817: }
1888 200, 2, 14, // 3821: case 0x148: {
1889 OPC_CheckPredicate, 3, // 3824: check predicate 3
1890 OPC_CheckField, 25, 5, 0, // 3826: check Inst[29:25] == 0x0
1891 OPC_CheckField, 14, 5, 0, // 3830: check Inst[18:14] == 0x0
1892 OPC_Decode, 174, 5, 78, // 3834: decode to MPMUL using decoder 78
1893 // 3834: }
1894 201, 2, 14, // 3838: case 0x149: {
1895 OPC_CheckPredicate, 3, // 3841: check predicate 3
1896 OPC_CheckField, 25, 5, 0, // 3843: check Inst[29:25] == 0x0
1897 OPC_CheckField, 14, 5, 0, // 3847: check Inst[18:14] == 0x0
1898 OPC_Decode, 159, 5, 78, // 3851: decode to MONTMUL using decoder 78
1899 // 3851: }
1900 202, 2, 14, // 3855: case 0x14a: {
1901 OPC_CheckPredicate, 3, // 3858: check predicate 3
1902 OPC_CheckField, 25, 5, 0, // 3860: check Inst[29:25] == 0x0
1903 OPC_CheckField, 14, 5, 0, // 3864: check Inst[18:14] == 0x0
1904 OPC_Decode, 160, 5, 78, // 3868: decode to MONTSQR using decoder 78
1905 // 3868: }
1906 209, 2, 6, // 3872: case 0x151: {
1907 OPC_CheckPredicate, 6, // 3875: check predicate 6
1908 OPC_Decode, 233, 3, 61, // 3877: decode to FLCMPS using decoder 61
1909 // 3877: }
1910 210, 2, 0, // 3881: case 0x152: {
1911 OPC_CheckPredicate, 6, // 3884: check predicate 6
1912 OPC_Decode, 232, 3, 62, // 3886: decode to FLCMPD using decoder 62
1913 // 3886: }
1914 // 3886: } // switch Inst[13:5]
1915 // 3886: }
1916 55, 83, // 3890: case 0x37: {
1917 OPC_SwitchField, 5, 4, // 3892: switch Inst[8:5] {
1918 0, 6, // 3895: case 0x0: {
1919 OPC_CheckPredicate, 2, // 3897: check predicate 2
1920 OPC_Decode, 178, 4, 15, // 3899: decode to FPMADDX using decoder 15
1921 // 3899: }
1922 1, 6, // 3903: case 0x1: {
1923 OPC_CheckPredicate, 9, // 3905: check predicate 9
1924 OPC_Decode, 239, 3, 79, // 3907: decode to FMADDS using decoder 79
1925 // 3907: }
1926 2, 6, // 3911: case 0x2: {
1927 OPC_CheckPredicate, 9, // 3913: check predicate 9
1928 OPC_Decode, 238, 3, 15, // 3915: decode to FMADDD using decoder 15
1929 // 3915: }
1930 4, 6, // 3919: case 0x4: {
1931 OPC_CheckPredicate, 2, // 3921: check predicate 2
1932 OPC_Decode, 179, 4, 15, // 3923: decode to FPMADDXHI using decoder 15
1933 // 3923: }
1934 5, 6, // 3927: case 0x5: {
1935 OPC_CheckPredicate, 9, // 3929: check predicate 9
1936 OPC_Decode, 129, 4, 79, // 3931: decode to FMSUBS using decoder 79
1937 // 3931: }
1938 6, 6, // 3935: case 0x6: {
1939 OPC_CheckPredicate, 9, // 3937: check predicate 9
1940 OPC_Decode, 128, 4, 15, // 3939: decode to FMSUBD using decoder 15
1941 // 3939: }
1942 9, 6, // 3943: case 0x9: {
1943 OPC_CheckPredicate, 9, // 3945: check predicate 9
1944 OPC_Decode, 152, 4, 79, // 3947: decode to FNMSUBS using decoder 79
1945 // 3947: }
1946 10, 6, // 3951: case 0xa: {
1947 OPC_CheckPredicate, 9, // 3953: check predicate 9
1948 OPC_Decode, 151, 4, 15, // 3955: decode to FNMSUBD using decoder 15
1949 // 3955: }
1950 13, 6, // 3959: case 0xd: {
1951 OPC_CheckPredicate, 9, // 3961: check predicate 9
1952 OPC_Decode, 150, 4, 79, // 3963: decode to FNMADDS using decoder 79
1953 // 3963: }
1954 14, 0, // 3967: case 0xe: {
1955 OPC_CheckPredicate, 9, // 3969: check predicate 9
1956 OPC_Decode, 149, 4, 15, // 3971: decode to FNMADDD using decoder 15
1957 // 3971: }
1958 // 3971: } // switch Inst[8:5]
1959 // 3971: }
1960 56, 19, // 3975: case 0x38: {
1961 OPC_SwitchField, 13, 1, // 3977: switch Inst[13] {
1962 0, 8, // 3980: case 0x0: {
1963 OPC_CheckField, 5, 8, 0, // 3982: check Inst[12:5] == 0x0
1964 OPC_Decode, 225, 4, 11, // 3986: decode to JMPLrr using decoder 11
1965 // 3986: }
1966 1, 0, // 3990: case 0x1: {
1967 OPC_Decode, 224, 4, 12, // 3992: decode to JMPLri using decoder 12
1968 // 3992: }
1969 // 3992: } // switch Inst[13]
1970 // 3992: }
1971 57, 27, // 3996: case 0x39: {
1972 OPC_SwitchField, 13, 1, // 3998: switch Inst[13] {
1973 0, 12, // 4001: case 0x0: {
1974 OPC_CheckField, 25, 5, 0, // 4003: check Inst[29:25] == 0x0
1975 OPC_CheckField, 5, 8, 0, // 4007: check Inst[12:5] == 0x0
1976 OPC_Decode, 212, 5, 34, // 4011: decode to RETTrr using decoder 34
1977 // 4011: }
1978 1, 0, // 4015: case 0x1: {
1979 OPC_CheckField, 25, 5, 0, // 4017: check Inst[29:25] == 0x0
1980 OPC_Decode, 211, 5, 35, // 4021: decode to RETTri using decoder 35
1981 // 4021: }
1982 // 4021: } // switch Inst[13]
1983 // 4021: }
1984 58, 78, // 4025: case 0x3a: {
1985 OPC_SwitchField, 8, 6, // 4027: switch Inst[13:8] {
1986 16, 14, // 4030: case 0x10: {
1987 OPC_CheckPredicate, 1, // 4032: check predicate 1
1988 OPC_CheckField, 29, 1, 0, // 4034: check Inst[29] == 0x0
1989 OPC_CheckField, 5, 3, 0, // 4038: check Inst[7:5] == 0x0
1990 OPC_Decode, 200, 6, 80, // 4042: decode to TXCCrr using decoder 80
1991 // 4042: }
1992 32, 45, // 4046: case 0x20: {
1993 OPC_SwitchField, 0, 8, // 4048: switch Inst[7:0] {
1994 1, 12, // 4051: case 0x1: {
1995 OPC_CheckField, 25, 5, 8, // 4053: check Inst[29:25] == 0x8
1996 OPC_CheckField, 14, 5, 0, // 4057: check Inst[18:14] == 0x0
1997 OPC_Decode, 178, 6, 7, // 4061: decode to TA1 using decoder 7
1998 // 4061: }
1999 3, 12, // 4065: case 0x3: {
2000 OPC_CheckField, 25, 5, 8, // 4067: check Inst[29:25] == 0x8
2001 OPC_CheckField, 14, 5, 0, // 4071: check Inst[18:14] == 0x0
2002 OPC_Decode, 179, 6, 7, // 4075: decode to TA3 using decoder 7
2003 // 4075: }
2004 5, 0, // 4079: case 0x5: {
2005 OPC_CheckField, 25, 5, 8, // 4081: check Inst[29:25] == 0x8
2006 OPC_CheckField, 14, 5, 0, // 4085: check Inst[18:14] == 0x0
2007 OPC_Decode, 180, 6, 7, // 4089: decode to TA5 using decoder 7
2008 // 4089: }
2009 // 4089: } // switch Inst[7:0]
2010 // 4089: }
2011 48, 0, // 4093: case 0x30: {
2012 OPC_CheckPredicate, 1, // 4095: check predicate 1
2013 OPC_CheckField, 29, 1, 0, // 4097: check Inst[29] == 0x0
2014 OPC_Decode, 199, 6, 81, // 4101: decode to TXCCri using decoder 81
2015 // 4101: }
2016 // 4101: } // switch Inst[13:8]
2017 // 4101: }
2018 59, 41, // 4105: case 0x3b: {
2019 OPC_SwitchField, 13, 1, // 4107: switch Inst[13] {
2020 0, 26, // 4110: case 0x0: {
2021 OPC_CheckField, 5, 8, 0, // 4112: check Inst[12:5] == 0x0
2022 OPC_CheckField, 25, 5, 0, // 4116: check Inst[29:25] == 0x0
2023 OPC_Scope, 12, // 4120: try {
2024 OPC_CheckField, 0, 5, 0, // 4122: check Inst[4:0] == 0x0
2025 OPC_CheckField, 14, 5, 0, // 4126: check Inst[18:14] == 0x0
2026 OPC_Decode, 234, 3, 7, // 4130: decode to FLUSH using decoder 7
2027 // 4130: } else try {
2028 OPC_Decode, 237, 3, 34, // 4134: decode to FLUSHrr using decoder 34
2029 // 4134: }
2030 // 4134: }
2031 1, 0, // 4138: case 0x1: {
2032 OPC_CheckField, 25, 5, 0, // 4140: check Inst[29:25] == 0x0
2033 OPC_Decode, 236, 3, 35, // 4144: decode to FLUSHri using decoder 35
2034 // 4144: }
2035 // 4144: } // switch Inst[13]
2036 // 4144: }
2037 60, 19, // 4148: case 0x3c: {
2038 OPC_SwitchField, 13, 1, // 4150: switch Inst[13] {
2039 0, 8, // 4153: case 0x0: {
2040 OPC_CheckField, 5, 8, 0, // 4155: check Inst[12:5] == 0x0
2041 OPC_Decode, 215, 5, 11, // 4159: decode to SAVErr using decoder 11
2042 // 4159: }
2043 1, 0, // 4163: case 0x1: {
2044 OPC_Decode, 214, 5, 12, // 4165: decode to SAVEri using decoder 12
2045 // 4165: }
2046 // 4165: } // switch Inst[13]
2047 // 4165: }
2048 61, 19, // 4169: case 0x3d: {
2049 OPC_SwitchField, 13, 1, // 4171: switch Inst[13] {
2050 0, 8, // 4174: case 0x0: {
2051 OPC_CheckField, 5, 8, 0, // 4176: check Inst[12:5] == 0x0
2052 OPC_Decode, 207, 5, 11, // 4180: decode to RESTORErr using decoder 11
2053 // 4180: }
2054 1, 0, // 4184: case 0x1: {
2055 OPC_Decode, 206, 5, 12, // 4186: decode to RESTOREri using decoder 12
2056 // 4186: }
2057 // 4186: } // switch Inst[13]
2058 // 4186: }
2059 62, 56, // 4190: case 0x3e: {
2060 OPC_SwitchField, 13, 1, // 4192: switch Inst[13] {
2061 0, 45, // 4195: case 0x0: {
2062 OPC_CheckField, 5, 8, 0, // 4197: check Inst[12:5] == 0x0
2063 OPC_Scope, 35, // 4201: try {
2064 OPC_SwitchField, 25, 5, // 4203: switch Inst[29:25] {
2065 0, 14, // 4206: case 0x0: {
2066 OPC_CheckPredicate, 0, // 4208: check predicate 0
2067 OPC_CheckField, 14, 5, 0, // 4210: check Inst[18:14] == 0x0
2068 OPC_CheckField, 0, 5, 0, // 4214: check Inst[4:0] == 0x0
2069 OPC_Decode, 171, 3, 7, // 4218: decode to DONE using decoder 7
2070 // 4218: }
2071 1, 0, // 4222: case 0x1: {
2072 OPC_CheckPredicate, 0, // 4224: check predicate 0
2073 OPC_CheckField, 14, 5, 0, // 4226: check Inst[18:14] == 0x0
2074 OPC_CheckField, 0, 5, 0, // 4230: check Inst[4:0] == 0x0
2075 OPC_Decode, 210, 5, 7, // 4234: decode to RETRY using decoder 7
2076 // 4234: }
2077 // 4234: } // switch Inst[29:25]
2078 // 4234: } else try {
2079 OPC_Decode, 208, 6, 11, // 4238: decode to UMACrr using decoder 11
2080 // 4238: }
2081 // 4238: }
2082 1, 0, // 4242: case 0x1: {
2083 OPC_Decode, 207, 6, 12, // 4244: decode to UMACri using decoder 12
2084 // 4244: }
2085 // 4244: } // switch Inst[13]
2086 // 4244: }
2087 63, 0, // 4248: case 0x3f: {
2088 OPC_SwitchField, 13, 1, // 4250: switch Inst[13] {
2089 0, 8, // 4253: case 0x0: {
2090 OPC_CheckField, 5, 8, 0, // 4255: check Inst[12:5] == 0x0
2091 OPC_Decode, 234, 5, 11, // 4259: decode to SMACrr using decoder 11
2092 // 4259: }
2093 1, 0, // 4263: case 0x1: {
2094 OPC_Decode, 233, 5, 12, // 4265: decode to SMACri using decoder 12
2095 // 4265: }
2096 // 4265: } // switch Inst[13]
2097 // 4265: }
2098 // 4265: } // switch Inst[24:19]
2099 // 4265: }
2100 3, 0, // 4269: case 0x3: {
2101 OPC_SwitchField, 19, 6, // 4271: switch Inst[24:19] {
2102 0, 19, // 4274: case 0x0: {
2103 OPC_SwitchField, 13, 1, // 4276: switch Inst[13] {
2104 0, 8, // 4279: case 0x0: {
2105 OPC_CheckField, 5, 8, 0, // 4281: check Inst[12:5] == 0x0
2106 OPC_Decode, 155, 5, 11, // 4285: decode to LDrr using decoder 11
2107 // 4285: }
2108 1, 0, // 4289: case 0x1: {
2109 OPC_Decode, 154, 5, 12, // 4291: decode to LDri using decoder 12
2110 // 4291: }
2111 // 4291: } // switch Inst[13]
2112 // 4291: }
2113 1, 19, // 4295: case 0x1: {
2114 OPC_SwitchField, 13, 1, // 4297: switch Inst[13] {
2115 0, 8, // 4300: case 0x0: {
2116 OPC_CheckField, 5, 8, 0, // 4302: check Inst[12:5] == 0x0
2117 OPC_Decode, 143, 5, 11, // 4306: decode to LDUBrr using decoder 11
2118 // 4306: }
2119 1, 0, // 4310: case 0x1: {
2120 OPC_Decode, 142, 5, 12, // 4312: decode to LDUBri using decoder 12
2121 // 4312: }
2122 // 4312: } // switch Inst[13]
2123 // 4312: }
2124 2, 19, // 4316: case 0x2: {
2125 OPC_SwitchField, 13, 1, // 4318: switch Inst[13] {
2126 0, 8, // 4321: case 0x0: {
2127 OPC_CheckField, 5, 8, 0, // 4323: check Inst[12:5] == 0x0
2128 OPC_Decode, 147, 5, 11, // 4327: decode to LDUHrr using decoder 11
2129 // 4327: }
2130 1, 0, // 4331: case 0x1: {
2131 OPC_Decode, 146, 5, 12, // 4333: decode to LDUHri using decoder 12
2132 // 4333: }
2133 // 4333: } // switch Inst[13]
2134 // 4333: }
2135 3, 19, // 4337: case 0x3: {
2136 OPC_SwitchField, 13, 1, // 4339: switch Inst[13] {
2137 0, 8, // 4342: case 0x0: {
2138 OPC_CheckField, 5, 8, 0, // 4344: check Inst[12:5] == 0x0
2139 OPC_Decode, 241, 4, 82, // 4348: decode to LDDrr using decoder 82
2140 // 4348: }
2141 1, 0, // 4352: case 0x1: {
2142 OPC_Decode, 240, 4, 83, // 4354: decode to LDDri using decoder 83
2143 // 4354: }
2144 // 4354: } // switch Inst[13]
2145 // 4354: }
2146 4, 19, // 4358: case 0x4: {
2147 OPC_SwitchField, 13, 1, // 4360: switch Inst[13] {
2148 0, 8, // 4363: case 0x0: {
2149 OPC_CheckField, 5, 8, 0, // 4365: check Inst[12:5] == 0x0
2150 OPC_Decode, 165, 6, 84, // 4369: decode to STrr using decoder 84
2151 // 4369: }
2152 1, 0, // 4373: case 0x1: {
2153 OPC_Decode, 164, 6, 85, // 4375: decode to STri using decoder 85
2154 // 4375: }
2155 // 4375: } // switch Inst[13]
2156 // 4375: }
2157 5, 19, // 4379: case 0x5: {
2158 OPC_SwitchField, 13, 1, // 4381: switch Inst[13] {
2159 0, 8, // 4384: case 0x0: {
2160 OPC_CheckField, 5, 8, 0, // 4386: check Inst[12:5] == 0x0
2161 OPC_Decode, 253, 5, 84, // 4390: decode to STBrr using decoder 84
2162 // 4390: }
2163 1, 0, // 4394: case 0x1: {
2164 OPC_Decode, 252, 5, 85, // 4396: decode to STBri using decoder 85
2165 // 4396: }
2166 // 4396: } // switch Inst[13]
2167 // 4396: }
2168 6, 19, // 4400: case 0x6: {
2169 OPC_SwitchField, 13, 1, // 4402: switch Inst[13] {
2170 0, 8, // 4405: case 0x0: {
2171 OPC_CheckField, 5, 8, 0, // 4407: check Inst[12:5] == 0x0
2172 OPC_Decode, 153, 6, 84, // 4411: decode to STHrr using decoder 84
2173 // 4411: }
2174 1, 0, // 4415: case 0x1: {
2175 OPC_Decode, 152, 6, 85, // 4417: decode to STHri using decoder 85
2176 // 4417: }
2177 // 4417: } // switch Inst[13]
2178 // 4417: }
2179 7, 19, // 4421: case 0x7: {
2180 OPC_SwitchField, 13, 1, // 4423: switch Inst[13] {
2181 0, 8, // 4426: case 0x0: {
2182 OPC_CheckField, 5, 8, 0, // 4428: check Inst[12:5] == 0x0
2183 OPC_Decode, 143, 6, 86, // 4432: decode to STDrr using decoder 86
2184 // 4432: }
2185 1, 0, // 4436: case 0x1: {
2186 OPC_Decode, 142, 6, 87, // 4438: decode to STDri using decoder 87
2187 // 4438: }
2188 // 4438: } // switch Inst[13]
2189 // 4438: }
2190 8, 23, // 4442: case 0x8: {
2191 OPC_SwitchField, 13, 1, // 4444: switch Inst[13] {
2192 0, 10, // 4447: case 0x0: {
2193 OPC_CheckPredicate, 1, // 4449: check predicate 1
2194 OPC_CheckField, 5, 8, 0, // 4451: check Inst[12:5] == 0x0
2195 OPC_Decode, 139, 5, 88, // 4455: decode to LDSWrr using decoder 88
2196 // 4455: }
2197 1, 0, // 4459: case 0x1: {
2198 OPC_CheckPredicate, 1, // 4461: check predicate 1
2199 OPC_Decode, 138, 5, 89, // 4463: decode to LDSWri using decoder 89
2200 // 4463: }
2201 // 4463: } // switch Inst[13]
2202 // 4463: }
2203 9, 19, // 4467: case 0x9: {
2204 OPC_SwitchField, 13, 1, // 4469: switch Inst[13] {
2205 0, 8, // 4472: case 0x0: {
2206 OPC_CheckField, 5, 8, 0, // 4474: check Inst[12:5] == 0x0
2207 OPC_Decode, 255, 4, 11, // 4478: decode to LDSBrr using decoder 11
2208 // 4478: }
2209 1, 0, // 4482: case 0x1: {
2210 OPC_Decode, 254, 4, 12, // 4484: decode to LDSBri using decoder 12
2211 // 4484: }
2212 // 4484: } // switch Inst[13]
2213 // 4484: }
2214 10, 19, // 4488: case 0xa: {
2215 OPC_SwitchField, 13, 1, // 4490: switch Inst[13] {
2216 0, 8, // 4493: case 0x0: {
2217 OPC_CheckField, 5, 8, 0, // 4495: check Inst[12:5] == 0x0
2218 OPC_Decode, 131, 5, 11, // 4499: decode to LDSHrr using decoder 11
2219 // 4499: }
2220 1, 0, // 4503: case 0x1: {
2221 OPC_Decode, 130, 5, 12, // 4505: decode to LDSHri using decoder 12
2222 // 4505: }
2223 // 4505: } // switch Inst[13]
2224 // 4505: }
2225 11, 23, // 4509: case 0xb: {
2226 OPC_SwitchField, 13, 1, // 4511: switch Inst[13] {
2227 0, 10, // 4514: case 0x0: {
2228 OPC_CheckPredicate, 1, // 4516: check predicate 1
2229 OPC_CheckField, 5, 8, 0, // 4518: check Inst[12:5] == 0x0
2230 OPC_Decode, 153, 5, 88, // 4522: decode to LDXrr using decoder 88
2231 // 4522: }
2232 1, 0, // 4526: case 0x1: {
2233 OPC_CheckPredicate, 1, // 4528: check predicate 1
2234 OPC_Decode, 152, 5, 89, // 4530: decode to LDXri using decoder 89
2235 // 4530: }
2236 // 4530: } // switch Inst[13]
2237 // 4530: }
2238 13, 19, // 4534: case 0xd: {
2239 OPC_SwitchField, 13, 1, // 4536: switch Inst[13] {
2240 0, 8, // 4539: case 0x0: {
2241 OPC_CheckField, 5, 8, 0, // 4541: check Inst[12:5] == 0x0
2242 OPC_Decode, 135, 5, 11, // 4545: decode to LDSTUBrr using decoder 11
2243 // 4545: }
2244 1, 0, // 4549: case 0x1: {
2245 OPC_Decode, 134, 5, 12, // 4551: decode to LDSTUBri using decoder 12
2246 // 4551: }
2247 // 4551: } // switch Inst[13]
2248 // 4551: }
2249 14, 23, // 4555: case 0xe: {
2250 OPC_SwitchField, 13, 1, // 4557: switch Inst[13] {
2251 0, 10, // 4560: case 0x0: {
2252 OPC_CheckPredicate, 1, // 4562: check predicate 1
2253 OPC_CheckField, 5, 8, 0, // 4564: check Inst[12:5] == 0x0
2254 OPC_Decode, 163, 6, 90, // 4568: decode to STXrr using decoder 90
2255 // 4568: }
2256 1, 0, // 4572: case 0x1: {
2257 OPC_CheckPredicate, 1, // 4574: check predicate 1
2258 OPC_Decode, 162, 6, 91, // 4576: decode to STXri using decoder 91
2259 // 4576: }
2260 // 4576: } // switch Inst[13]
2261 // 4576: }
2262 15, 19, // 4580: case 0xf: {
2263 OPC_SwitchField, 13, 1, // 4582: switch Inst[13] {
2264 0, 8, // 4585: case 0x0: {
2265 OPC_CheckField, 5, 8, 0, // 4587: check Inst[12:5] == 0x0
2266 OPC_Decode, 177, 6, 92, // 4591: decode to SWAPrr using decoder 92
2267 // 4591: }
2268 1, 0, // 4595: case 0x1: {
2269 OPC_Decode, 176, 6, 93, // 4597: decode to SWAPri using decoder 93
2270 // 4597: }
2271 // 4597: } // switch Inst[13]
2272 // 4597: }
2273 16, 17, // 4601: case 0x10: {
2274 OPC_SwitchField, 13, 1, // 4603: switch Inst[13] {
2275 0, 4, // 4606: case 0x0: {
2276 OPC_Decode, 227, 4, 94, // 4608: decode to LDArr using decoder 94
2277 // 4608: }
2278 1, 0, // 4612: case 0x1: {
2279 OPC_CheckPredicate, 0, // 4614: check predicate 0
2280 OPC_Decode, 226, 4, 12, // 4616: decode to LDAri using decoder 12
2281 // 4616: }
2282 // 4616: } // switch Inst[13]
2283 // 4616: }
2284 17, 17, // 4620: case 0x11: {
2285 OPC_SwitchField, 13, 1, // 4622: switch Inst[13] {
2286 0, 4, // 4625: case 0x0: {
2287 OPC_Decode, 141, 5, 94, // 4627: decode to LDUBArr using decoder 94
2288 // 4627: }
2289 1, 0, // 4631: case 0x1: {
2290 OPC_CheckPredicate, 0, // 4633: check predicate 0
2291 OPC_Decode, 140, 5, 12, // 4635: decode to LDUBAri using decoder 12
2292 // 4635: }
2293 // 4635: } // switch Inst[13]
2294 // 4635: }
2295 18, 17, // 4639: case 0x12: {
2296 OPC_SwitchField, 13, 1, // 4641: switch Inst[13] {
2297 0, 4, // 4644: case 0x0: {
2298 OPC_Decode, 145, 5, 94, // 4646: decode to LDUHArr using decoder 94
2299 // 4646: }
2300 1, 0, // 4650: case 0x1: {
2301 OPC_CheckPredicate, 0, // 4652: check predicate 0
2302 OPC_Decode, 144, 5, 12, // 4654: decode to LDUHAri using decoder 12
2303 // 4654: }
2304 // 4654: } // switch Inst[13]
2305 // 4654: }
2306 19, 17, // 4658: case 0x13: {
2307 OPC_SwitchField, 13, 1, // 4660: switch Inst[13] {
2308 0, 4, // 4663: case 0x0: {
2309 OPC_Decode, 233, 4, 95, // 4665: decode to LDDArr using decoder 95
2310 // 4665: }
2311 1, 0, // 4669: case 0x1: {
2312 OPC_CheckPredicate, 0, // 4671: check predicate 0
2313 OPC_Decode, 232, 4, 83, // 4673: decode to LDDAri using decoder 83
2314 // 4673: }
2315 // 4673: } // switch Inst[13]
2316 // 4673: }
2317 20, 17, // 4677: case 0x14: {
2318 OPC_SwitchField, 13, 1, // 4679: switch Inst[13] {
2319 0, 4, // 4682: case 0x0: {
2320 OPC_Decode, 248, 5, 96, // 4684: decode to STArr using decoder 96
2321 // 4684: }
2322 1, 0, // 4688: case 0x1: {
2323 OPC_CheckPredicate, 0, // 4690: check predicate 0
2324 OPC_Decode, 247, 5, 85, // 4692: decode to STAri using decoder 85
2325 // 4692: }
2326 // 4692: } // switch Inst[13]
2327 // 4692: }
2328 21, 17, // 4696: case 0x15: {
2329 OPC_SwitchField, 13, 1, // 4698: switch Inst[13] {
2330 0, 4, // 4701: case 0x0: {
2331 OPC_Decode, 251, 5, 96, // 4703: decode to STBArr using decoder 96
2332 // 4703: }
2333 1, 0, // 4707: case 0x1: {
2334 OPC_CheckPredicate, 0, // 4709: check predicate 0
2335 OPC_Decode, 250, 5, 85, // 4711: decode to STBAri using decoder 85
2336 // 4711: }
2337 // 4711: } // switch Inst[13]
2338 // 4711: }
2339 22, 17, // 4715: case 0x16: {
2340 OPC_SwitchField, 13, 1, // 4717: switch Inst[13] {
2341 0, 4, // 4720: case 0x0: {
2342 OPC_Decode, 151, 6, 96, // 4722: decode to STHArr using decoder 96
2343 // 4722: }
2344 1, 0, // 4726: case 0x1: {
2345 OPC_CheckPredicate, 0, // 4728: check predicate 0
2346 OPC_Decode, 150, 6, 85, // 4730: decode to STHAri using decoder 85
2347 // 4730: }
2348 // 4730: } // switch Inst[13]
2349 // 4730: }
2350 23, 17, // 4734: case 0x17: {
2351 OPC_SwitchField, 13, 1, // 4736: switch Inst[13] {
2352 0, 4, // 4739: case 0x0: {
2353 OPC_Decode, 131, 6, 97, // 4741: decode to STDArr using decoder 97
2354 // 4741: }
2355 1, 0, // 4745: case 0x1: {
2356 OPC_CheckPredicate, 0, // 4747: check predicate 0
2357 OPC_Decode, 130, 6, 87, // 4749: decode to STDAri using decoder 87
2358 // 4749: }
2359 // 4749: } // switch Inst[13]
2360 // 4749: }
2361 24, 19, // 4753: case 0x18: {
2362 OPC_SwitchField, 13, 1, // 4755: switch Inst[13] {
2363 0, 6, // 4758: case 0x0: {
2364 OPC_CheckPredicate, 1, // 4760: check predicate 1
2365 OPC_Decode, 137, 5, 98, // 4762: decode to LDSWArr using decoder 98
2366 // 4762: }
2367 1, 0, // 4766: case 0x1: {
2368 OPC_CheckPredicate, 1, // 4768: check predicate 1
2369 OPC_Decode, 136, 5, 89, // 4770: decode to LDSWAri using decoder 89
2370 // 4770: }
2371 // 4770: } // switch Inst[13]
2372 // 4770: }
2373 25, 17, // 4774: case 0x19: {
2374 OPC_SwitchField, 13, 1, // 4776: switch Inst[13] {
2375 0, 4, // 4779: case 0x0: {
2376 OPC_Decode, 253, 4, 94, // 4781: decode to LDSBArr using decoder 94
2377 // 4781: }
2378 1, 0, // 4785: case 0x1: {
2379 OPC_CheckPredicate, 0, // 4787: check predicate 0
2380 OPC_Decode, 252, 4, 12, // 4789: decode to LDSBAri using decoder 12
2381 // 4789: }
2382 // 4789: } // switch Inst[13]
2383 // 4789: }
2384 26, 17, // 4793: case 0x1a: {
2385 OPC_SwitchField, 13, 1, // 4795: switch Inst[13] {
2386 0, 4, // 4798: case 0x0: {
2387 OPC_Decode, 129, 5, 94, // 4800: decode to LDSHArr using decoder 94
2388 // 4800: }
2389 1, 0, // 4804: case 0x1: {
2390 OPC_CheckPredicate, 0, // 4806: check predicate 0
2391 OPC_Decode, 128, 5, 12, // 4808: decode to LDSHAri using decoder 12
2392 // 4808: }
2393 // 4808: } // switch Inst[13]
2394 // 4808: }
2395 27, 19, // 4812: case 0x1b: {
2396 OPC_SwitchField, 13, 1, // 4814: switch Inst[13] {
2397 0, 6, // 4817: case 0x0: {
2398 OPC_CheckPredicate, 1, // 4819: check predicate 1
2399 OPC_Decode, 149, 5, 98, // 4821: decode to LDXArr using decoder 98
2400 // 4821: }
2401 1, 0, // 4825: case 0x1: {
2402 OPC_CheckPredicate, 1, // 4827: check predicate 1
2403 OPC_Decode, 148, 5, 89, // 4829: decode to LDXAri using decoder 89
2404 // 4829: }
2405 // 4829: } // switch Inst[13]
2406 // 4829: }
2407 29, 17, // 4833: case 0x1d: {
2408 OPC_SwitchField, 13, 1, // 4835: switch Inst[13] {
2409 0, 4, // 4838: case 0x0: {
2410 OPC_Decode, 133, 5, 94, // 4840: decode to LDSTUBArr using decoder 94
2411 // 4840: }
2412 1, 0, // 4844: case 0x1: {
2413 OPC_CheckPredicate, 0, // 4846: check predicate 0
2414 OPC_Decode, 132, 5, 12, // 4848: decode to LDSTUBAri using decoder 12
2415 // 4848: }
2416 // 4848: } // switch Inst[13]
2417 // 4848: }
2418 30, 19, // 4852: case 0x1e: {
2419 OPC_SwitchField, 13, 1, // 4854: switch Inst[13] {
2420 0, 6, // 4857: case 0x0: {
2421 OPC_CheckPredicate, 1, // 4859: check predicate 1
2422 OPC_Decode, 159, 6, 99, // 4861: decode to STXArr using decoder 99
2423 // 4861: }
2424 1, 0, // 4865: case 0x1: {
2425 OPC_CheckPredicate, 1, // 4867: check predicate 1
2426 OPC_Decode, 158, 6, 91, // 4869: decode to STXAri using decoder 91
2427 // 4869: }
2428 // 4869: } // switch Inst[13]
2429 // 4869: }
2430 31, 17, // 4873: case 0x1f: {
2431 OPC_SwitchField, 13, 1, // 4875: switch Inst[13] {
2432 0, 4, // 4878: case 0x0: {
2433 OPC_Decode, 175, 6, 100, // 4880: decode to SWAPArr using decoder 100
2434 // 4880: }
2435 1, 0, // 4884: case 0x1: {
2436 OPC_CheckPredicate, 0, // 4886: check predicate 0
2437 OPC_Decode, 174, 6, 93, // 4888: decode to SWAPAri using decoder 93
2438 // 4888: }
2439 // 4888: } // switch Inst[13]
2440 // 4888: }
2441 32, 19, // 4892: case 0x20: {
2442 OPC_SwitchField, 13, 1, // 4894: switch Inst[13] {
2443 0, 8, // 4897: case 0x0: {
2444 OPC_CheckField, 5, 8, 0, // 4899: check Inst[12:5] == 0x0
2445 OPC_Decode, 247, 4, 101, // 4903: decode to LDFrr using decoder 101
2446 // 4903: }
2447 1, 0, // 4907: case 0x1: {
2448 OPC_Decode, 246, 4, 102, // 4909: decode to LDFri using decoder 102
2449 // 4909: }
2450 // 4909: } // switch Inst[13]
2451 // 4909: }
2452 33, 49, // 4913: case 0x21: {
2453 OPC_SwitchField, 13, 1, // 4915: switch Inst[13] {
2454 0, 25, // 4918: case 0x0: {
2455 OPC_SwitchField, 25, 5, // 4920: switch Inst[29:25] {
2456 0, 8, // 4923: case 0x0: {
2457 OPC_CheckField, 5, 8, 0, // 4925: check Inst[12:5] == 0x0
2458 OPC_Decode, 245, 4, 34, // 4929: decode to LDFSRrr using decoder 34
2459 // 4929: }
2460 1, 0, // 4933: case 0x1: {
2461 OPC_CheckPredicate, 0, // 4935: check predicate 0
2462 OPC_CheckField, 5, 8, 0, // 4937: check Inst[12:5] == 0x0
2463 OPC_Decode, 151, 5, 34, // 4941: decode to LDXFSRrr using decoder 34
2464 // 4941: }
2465 // 4941: } // switch Inst[29:25]
2466 // 4941: }
2467 1, 0, // 4945: case 0x1: {
2468 OPC_SwitchField, 25, 5, // 4947: switch Inst[29:25] {
2469 0, 4, // 4950: case 0x0: {
2470 OPC_Decode, 244, 4, 35, // 4952: decode to LDFSRri using decoder 35
2471 // 4952: }
2472 1, 0, // 4956: case 0x1: {
2473 OPC_CheckPredicate, 0, // 4958: check predicate 0
2474 OPC_Decode, 150, 5, 35, // 4960: decode to LDXFSRri using decoder 35
2475 // 4960: }
2476 // 4960: } // switch Inst[29:25]
2477 // 4960: }
2478 // 4960: } // switch Inst[13]
2479 // 4960: }
2480 35, 19, // 4964: case 0x23: {
2481 OPC_SwitchField, 13, 1, // 4966: switch Inst[13] {
2482 0, 8, // 4969: case 0x0: {
2483 OPC_CheckField, 5, 8, 0, // 4971: check Inst[12:5] == 0x0
2484 OPC_Decode, 239, 4, 103, // 4975: decode to LDDFrr using decoder 103
2485 // 4975: }
2486 1, 0, // 4979: case 0x1: {
2487 OPC_Decode, 238, 4, 104, // 4981: decode to LDDFri using decoder 104
2488 // 4981: }
2489 // 4981: } // switch Inst[13]
2490 // 4981: }
2491 36, 19, // 4985: case 0x24: {
2492 OPC_SwitchField, 13, 1, // 4987: switch Inst[13] {
2493 0, 8, // 4990: case 0x0: {
2494 OPC_CheckField, 5, 8, 0, // 4992: check Inst[12:5] == 0x0
2495 OPC_Decode, 149, 6, 105, // 4996: decode to STFrr using decoder 105
2496 // 4996: }
2497 1, 0, // 5000: case 0x1: {
2498 OPC_Decode, 148, 6, 106, // 5002: decode to STFri using decoder 106
2499 // 5002: }
2500 // 5002: } // switch Inst[13]
2501 // 5002: }
2502 37, 49, // 5006: case 0x25: {
2503 OPC_SwitchField, 13, 1, // 5008: switch Inst[13] {
2504 0, 25, // 5011: case 0x0: {
2505 OPC_SwitchField, 25, 5, // 5013: switch Inst[29:25] {
2506 0, 8, // 5016: case 0x0: {
2507 OPC_CheckField, 5, 8, 0, // 5018: check Inst[12:5] == 0x0
2508 OPC_Decode, 147, 6, 34, // 5022: decode to STFSRrr using decoder 34
2509 // 5022: }
2510 1, 0, // 5026: case 0x1: {
2511 OPC_CheckPredicate, 0, // 5028: check predicate 0
2512 OPC_CheckField, 5, 8, 0, // 5030: check Inst[12:5] == 0x0
2513 OPC_Decode, 161, 6, 34, // 5034: decode to STXFSRrr using decoder 34
2514 // 5034: }
2515 // 5034: } // switch Inst[29:25]
2516 // 5034: }
2517 1, 0, // 5038: case 0x1: {
2518 OPC_SwitchField, 25, 5, // 5040: switch Inst[29:25] {
2519 0, 4, // 5043: case 0x0: {
2520 OPC_Decode, 146, 6, 35, // 5045: decode to STFSRri using decoder 35
2521 // 5045: }
2522 1, 0, // 5049: case 0x1: {
2523 OPC_CheckPredicate, 0, // 5051: check predicate 0
2524 OPC_Decode, 160, 6, 35, // 5053: decode to STXFSRri using decoder 35
2525 // 5053: }
2526 // 5053: } // switch Inst[29:25]
2527 // 5053: }
2528 // 5053: } // switch Inst[13]
2529 // 5053: }
2530 38, 27, // 5057: case 0x26: {
2531 OPC_SwitchField, 13, 1, // 5059: switch Inst[13] {
2532 0, 12, // 5062: case 0x0: {
2533 OPC_CheckField, 25, 5, 0, // 5064: check Inst[29:25] == 0x0
2534 OPC_CheckField, 5, 8, 0, // 5068: check Inst[12:5] == 0x0
2535 OPC_Decode, 139, 6, 34, // 5072: decode to STDFQrr using decoder 34
2536 // 5072: }
2537 1, 0, // 5076: case 0x1: {
2538 OPC_CheckField, 25, 5, 0, // 5078: check Inst[29:25] == 0x0
2539 OPC_Decode, 138, 6, 35, // 5082: decode to STDFQri using decoder 35
2540 // 5082: }
2541 // 5082: } // switch Inst[13]
2542 // 5082: }
2543 39, 19, // 5086: case 0x27: {
2544 OPC_SwitchField, 13, 1, // 5088: switch Inst[13] {
2545 0, 8, // 5091: case 0x0: {
2546 OPC_CheckField, 5, 8, 0, // 5093: check Inst[12:5] == 0x0
2547 OPC_Decode, 141, 6, 107, // 5097: decode to STDFrr using decoder 107
2548 // 5097: }
2549 1, 0, // 5101: case 0x1: {
2550 OPC_Decode, 140, 6, 108, // 5103: decode to STDFri using decoder 108
2551 // 5103: }
2552 // 5103: } // switch Inst[13]
2553 // 5103: }
2554 45, 23, // 5107: case 0x2d: {
2555 OPC_SwitchField, 13, 1, // 5109: switch Inst[13] {
2556 0, 10, // 5112: case 0x0: {
2557 OPC_CheckPredicate, 0, // 5114: check predicate 0
2558 OPC_CheckField, 5, 8, 0, // 5116: check Inst[12:5] == 0x0
2559 OPC_Decode, 196, 5, 109, // 5120: decode to PREFETCHr using decoder 109
2560 // 5120: }
2561 1, 0, // 5124: case 0x1: {
2562 OPC_CheckPredicate, 0, // 5126: check predicate 0
2563 OPC_Decode, 195, 5, 110, // 5128: decode to PREFETCHi using decoder 110
2564 // 5128: }
2565 // 5128: } // switch Inst[13]
2566 // 5128: }
2567 49, 27, // 5132: case 0x31: {
2568 OPC_SwitchField, 13, 1, // 5134: switch Inst[13] {
2569 0, 12, // 5137: case 0x0: {
2570 OPC_CheckField, 25, 5, 0, // 5139: check Inst[29:25] == 0x0
2571 OPC_CheckField, 5, 8, 0, // 5143: check Inst[12:5] == 0x0
2572 OPC_Decode, 229, 4, 34, // 5147: decode to LDCSRrr using decoder 34
2573 // 5147: }
2574 1, 0, // 5151: case 0x1: {
2575 OPC_CheckField, 25, 5, 0, // 5153: check Inst[29:25] == 0x0
2576 OPC_Decode, 228, 4, 35, // 5157: decode to LDCSRri using decoder 35
2577 // 5157: }
2578 // 5157: } // switch Inst[13]
2579 // 5157: }
2580 53, 27, // 5161: case 0x35: {
2581 OPC_SwitchField, 13, 1, // 5163: switch Inst[13] {
2582 0, 12, // 5166: case 0x0: {
2583 OPC_CheckField, 25, 5, 0, // 5168: check Inst[29:25] == 0x0
2584 OPC_CheckField, 5, 8, 0, // 5172: check Inst[12:5] == 0x0
2585 OPC_Decode, 255, 5, 34, // 5176: decode to STCSRrr using decoder 34
2586 // 5176: }
2587 1, 0, // 5180: case 0x1: {
2588 OPC_CheckField, 25, 5, 0, // 5182: check Inst[29:25] == 0x0
2589 OPC_Decode, 254, 5, 35, // 5186: decode to STCSRri using decoder 35
2590 // 5186: }
2591 // 5186: } // switch Inst[13]
2592 // 5186: }
2593 54, 27, // 5190: case 0x36: {
2594 OPC_SwitchField, 13, 1, // 5192: switch Inst[13] {
2595 0, 12, // 5195: case 0x0: {
2596 OPC_CheckField, 25, 5, 0, // 5197: check Inst[29:25] == 0x0
2597 OPC_CheckField, 5, 8, 0, // 5201: check Inst[12:5] == 0x0
2598 OPC_Decode, 133, 6, 34, // 5205: decode to STDCQrr using decoder 34
2599 // 5205: }
2600 1, 0, // 5209: case 0x1: {
2601 OPC_CheckField, 25, 5, 0, // 5211: check Inst[29:25] == 0x0
2602 OPC_Decode, 132, 6, 35, // 5215: decode to STDCQri using decoder 35
2603 // 5215: }
2604 // 5215: } // switch Inst[13]
2605 // 5215: }
2606 60, 23, // 5219: case 0x3c: {
2607 OPC_SwitchField, 13, 1, // 5221: switch Inst[13] {
2608 0, 6, // 5224: case 0x0: {
2609 OPC_CheckPredicate, 10, // 5226: check predicate 10
2610 OPC_Decode, 154, 3, 111, // 5228: decode to CASArr using decoder 111
2611 // 5228: }
2612 1, 0, // 5232: case 0x1: {
2613 OPC_CheckPredicate, 0, // 5234: check predicate 0
2614 OPC_CheckField, 5, 8, 0, // 5236: check Inst[12:5] == 0x0
2615 OPC_Decode, 153, 3, 92, // 5240: decode to CASAri using decoder 92
2616 // 5240: }
2617 // 5240: } // switch Inst[13]
2618 // 5240: }
2619 61, 19, // 5244: case 0x3d: {
2620 OPC_SwitchField, 13, 1, // 5246: switch Inst[13] {
2621 0, 6, // 5249: case 0x0: {
2622 OPC_CheckPredicate, 0, // 5251: check predicate 0
2623 OPC_Decode, 194, 5, 112, // 5253: decode to PREFETCHAr using decoder 112
2624 // 5253: }
2625 1, 0, // 5257: case 0x1: {
2626 OPC_CheckPredicate, 0, // 5259: check predicate 0
2627 OPC_Decode, 193, 5, 110, // 5261: decode to PREFETCHAi using decoder 110
2628 // 5261: }
2629 // 5261: } // switch Inst[13]
2630 // 5261: }
2631 62, 0, // 5265: case 0x3e: {
2632 OPC_SwitchField, 13, 1, // 5267: switch Inst[13] {
2633 0, 6, // 5270: case 0x0: {
2634 OPC_CheckPredicate, 11, // 5272: check predicate 11
2635 OPC_Decode, 156, 3, 113, // 5274: decode to CASXArr using decoder 113
2636 // 5274: }
2637 1, 0, // 5278: case 0x1: {
2638 OPC_CheckPredicate, 11, // 5280: check predicate 11
2639 OPC_CheckField, 5, 8, 0, // 5282: check Inst[12:5] == 0x0
2640 OPC_Decode, 155, 3, 114, // 5286: decode to CASXAri using decoder 114
2641 // 5286: }
2642 // 5286: } // switch Inst[13]
2643 // 5286: }
2644 // 5286: } // switch Inst[24:19]
2645 // 5286: }
2646 // 5286: } // switch Inst[31:30]
2647};
2648static const uint8_t DecoderTableSparcV832[148] = {
2649 OPC_SwitchField, 19, 6, // 0: switch Inst[24:19] {
2650 48, 27, // 3: case 0x30: {
2651 OPC_SwitchField, 13, 1, // 5: switch Inst[13] {
2652 0, 12, // 8: case 0x0: {
2653 OPC_CheckField, 30, 2, 3, // 10: check Inst[31:30] == 0x3
2654 OPC_CheckField, 5, 8, 0, // 14: check Inst[12:5] == 0x0
2655 OPC_Decode, 231, 4, 115, // 18: decode to LDCrr using decoder 115
2656 // 18: }
2657 1, 0, // 22: case 0x1: {
2658 OPC_CheckField, 30, 2, 3, // 24: check Inst[31:30] == 0x3
2659 OPC_Decode, 230, 4, 116, // 28: decode to LDCri using decoder 116
2660 // 28: }
2661 // 28: } // switch Inst[13]
2662 // 28: }
2663 51, 27, // 32: case 0x33: {
2664 OPC_SwitchField, 13, 1, // 34: switch Inst[13] {
2665 0, 12, // 37: case 0x0: {
2666 OPC_CheckField, 30, 2, 3, // 39: check Inst[31:30] == 0x3
2667 OPC_CheckField, 5, 8, 0, // 43: check Inst[12:5] == 0x0
2668 OPC_Decode, 235, 4, 117, // 47: decode to LDDCrr using decoder 117
2669 // 47: }
2670 1, 0, // 51: case 0x1: {
2671 OPC_CheckField, 30, 2, 3, // 53: check Inst[31:30] == 0x3
2672 OPC_Decode, 234, 4, 118, // 57: decode to LDDCri using decoder 118
2673 // 57: }
2674 // 57: } // switch Inst[13]
2675 // 57: }
2676 52, 27, // 61: case 0x34: {
2677 OPC_SwitchField, 13, 1, // 63: switch Inst[13] {
2678 0, 12, // 66: case 0x0: {
2679 OPC_CheckField, 30, 2, 3, // 68: check Inst[31:30] == 0x3
2680 OPC_CheckField, 5, 8, 0, // 72: check Inst[12:5] == 0x0
2681 OPC_Decode, 129, 6, 119, // 76: decode to STCrr using decoder 119
2682 // 76: }
2683 1, 0, // 80: case 0x1: {
2684 OPC_CheckField, 30, 2, 3, // 82: check Inst[31:30] == 0x3
2685 OPC_Decode, 128, 6, 120, // 86: decode to STCri using decoder 120
2686 // 86: }
2687 // 86: } // switch Inst[13]
2688 // 86: }
2689 55, 27, // 90: case 0x37: {
2690 OPC_SwitchField, 13, 1, // 92: switch Inst[13] {
2691 0, 12, // 95: case 0x0: {
2692 OPC_CheckField, 30, 2, 3, // 97: check Inst[31:30] == 0x3
2693 OPC_CheckField, 5, 8, 0, // 101: check Inst[12:5] == 0x0
2694 OPC_Decode, 135, 6, 121, // 105: decode to STDCrr using decoder 121
2695 // 105: }
2696 1, 0, // 109: case 0x1: {
2697 OPC_CheckField, 30, 2, 3, // 111: check Inst[31:30] == 0x3
2698 OPC_Decode, 134, 6, 122, // 115: decode to STDCri using decoder 122
2699 // 115: }
2700 // 115: } // switch Inst[13]
2701 // 115: }
2702 58, 0, // 119: case 0x3a: {
2703 OPC_SwitchField, 8, 6, // 121: switch Inst[13:8] {
2704 0, 12, // 124: case 0x0: {
2705 OPC_CheckField, 29, 3, 4, // 126: check Inst[31:29] == 0x4
2706 OPC_CheckField, 5, 3, 0, // 130: check Inst[7:5] == 0x0
2707 OPC_Decode, 194, 6, 80, // 134: decode to TRAPrr using decoder 80
2708 // 134: }
2709 32, 0, // 138: case 0x20: {
2710 OPC_CheckField, 29, 3, 4, // 140: check Inst[31:29] == 0x4
2711 OPC_Decode, 193, 6, 81, // 144: decode to TRAPri using decoder 81
2712 // 144: }
2713 // 144: } // switch Inst[13:8]
2714 // 144: }
2715 // 144: } // switch Inst[24:19]
2716};
2717static const uint8_t DecoderTableSparcV932[281] = {
2718 OPC_SwitchField, 19, 6, // 0: switch Inst[24:19] {
2719 34, 31, // 3: case 0x22: {
2720 OPC_SwitchField, 13, 1, // 5: switch Inst[13] {
2721 0, 14, // 8: case 0x0: {
2722 OPC_CheckPredicate, 0, // 10: check predicate 0
2723 OPC_CheckField, 30, 2, 3, // 12: check Inst[31:30] == 0x3
2724 OPC_CheckField, 5, 8, 0, // 16: check Inst[12:5] == 0x0
2725 OPC_Decode, 251, 4, 123, // 20: decode to LDQFrr using decoder 123
2726 // 20: }
2727 1, 0, // 24: case 0x1: {
2728 OPC_CheckPredicate, 0, // 26: check predicate 0
2729 OPC_CheckField, 30, 2, 3, // 28: check Inst[31:30] == 0x3
2730 OPC_Decode, 250, 4, 124, // 32: decode to LDQFri using decoder 124
2731 // 32: }
2732 // 32: } // switch Inst[13]
2733 // 32: }
2734 38, 31, // 36: case 0x26: {
2735 OPC_SwitchField, 13, 1, // 38: switch Inst[13] {
2736 0, 14, // 41: case 0x0: {
2737 OPC_CheckPredicate, 0, // 43: check predicate 0
2738 OPC_CheckField, 30, 2, 3, // 45: check Inst[31:30] == 0x3
2739 OPC_CheckField, 5, 8, 0, // 49: check Inst[12:5] == 0x0
2740 OPC_Decode, 157, 6, 125, // 53: decode to STQFrr using decoder 125
2741 // 53: }
2742 1, 0, // 57: case 0x1: {
2743 OPC_CheckPredicate, 0, // 59: check predicate 0
2744 OPC_CheckField, 30, 2, 3, // 61: check Inst[31:30] == 0x3
2745 OPC_Decode, 156, 6, 126, // 65: decode to STQFri using decoder 126
2746 // 65: }
2747 // 65: } // switch Inst[13]
2748 // 65: }
2749 48, 27, // 69: case 0x30: {
2750 OPC_SwitchField, 13, 1, // 71: switch Inst[13] {
2751 0, 10, // 74: case 0x0: {
2752 OPC_CheckPredicate, 0, // 76: check predicate 0
2753 OPC_CheckField, 30, 2, 3, // 78: check Inst[31:30] == 0x3
2754 OPC_Decode, 243, 4, 127, // 82: decode to LDFArr using decoder 127
2755 // 82: }
2756 1, 0, // 86: case 0x1: {
2757 OPC_CheckPredicate, 0, // 88: check predicate 0
2758 OPC_CheckField, 30, 2, 3, // 90: check Inst[31:30] == 0x3
2759 OPC_Decode, 242, 4, 102, // 94: decode to LDFAri using decoder 102
2760 // 94: }
2761 // 94: } // switch Inst[13]
2762 // 94: }
2763 50, 28, // 98: case 0x32: {
2764 OPC_SwitchField, 13, 1, // 100: switch Inst[13] {
2765 0, 11, // 103: case 0x0: {
2766 OPC_CheckPredicate, 0, // 105: check predicate 0
2767 OPC_CheckField, 30, 2, 3, // 107: check Inst[31:30] == 0x3
2768 OPC_Decode, 249, 4, 128, 1, // 111: decode to LDQFArr using decoder 128
2769 // 111: }
2770 1, 0, // 116: case 0x1: {
2771 OPC_CheckPredicate, 0, // 118: check predicate 0
2772 OPC_CheckField, 30, 2, 3, // 120: check Inst[31:30] == 0x3
2773 OPC_Decode, 248, 4, 124, // 124: decode to LDQFAri using decoder 124
2774 // 124: }
2775 // 124: } // switch Inst[13]
2776 // 124: }
2777 51, 28, // 128: case 0x33: {
2778 OPC_SwitchField, 13, 1, // 130: switch Inst[13] {
2779 0, 11, // 133: case 0x0: {
2780 OPC_CheckPredicate, 0, // 135: check predicate 0
2781 OPC_CheckField, 30, 2, 3, // 137: check Inst[31:30] == 0x3
2782 OPC_Decode, 237, 4, 129, 1, // 141: decode to LDDFArr using decoder 129
2783 // 141: }
2784 1, 0, // 146: case 0x1: {
2785 OPC_CheckPredicate, 0, // 148: check predicate 0
2786 OPC_CheckField, 30, 2, 3, // 150: check Inst[31:30] == 0x3
2787 OPC_Decode, 236, 4, 104, // 154: decode to LDDFAri using decoder 104
2788 // 154: }
2789 // 154: } // switch Inst[13]
2790 // 154: }
2791 52, 28, // 158: case 0x34: {
2792 OPC_SwitchField, 13, 1, // 160: switch Inst[13] {
2793 0, 11, // 163: case 0x0: {
2794 OPC_CheckPredicate, 0, // 165: check predicate 0
2795 OPC_CheckField, 30, 2, 3, // 167: check Inst[31:30] == 0x3
2796 OPC_Decode, 145, 6, 130, 1, // 171: decode to STFArr using decoder 130
2797 // 171: }
2798 1, 0, // 176: case 0x1: {
2799 OPC_CheckPredicate, 0, // 178: check predicate 0
2800 OPC_CheckField, 30, 2, 3, // 180: check Inst[31:30] == 0x3
2801 OPC_Decode, 144, 6, 106, // 184: decode to STFAri using decoder 106
2802 // 184: }
2803 // 184: } // switch Inst[13]
2804 // 184: }
2805 54, 28, // 188: case 0x36: {
2806 OPC_SwitchField, 13, 1, // 190: switch Inst[13] {
2807 0, 11, // 193: case 0x0: {
2808 OPC_CheckPredicate, 0, // 195: check predicate 0
2809 OPC_CheckField, 30, 2, 3, // 197: check Inst[31:30] == 0x3
2810 OPC_Decode, 155, 6, 131, 1, // 201: decode to STQFArr using decoder 131
2811 // 201: }
2812 1, 0, // 206: case 0x1: {
2813 OPC_CheckPredicate, 0, // 208: check predicate 0
2814 OPC_CheckField, 30, 2, 3, // 210: check Inst[31:30] == 0x3
2815 OPC_Decode, 154, 6, 126, // 214: decode to STQFAri using decoder 126
2816 // 214: }
2817 // 214: } // switch Inst[13]
2818 // 214: }
2819 55, 28, // 218: case 0x37: {
2820 OPC_SwitchField, 13, 1, // 220: switch Inst[13] {
2821 0, 11, // 223: case 0x0: {
2822 OPC_CheckPredicate, 0, // 225: check predicate 0
2823 OPC_CheckField, 30, 2, 3, // 227: check Inst[31:30] == 0x3
2824 OPC_Decode, 137, 6, 132, 1, // 231: decode to STDFArr using decoder 132
2825 // 231: }
2826 1, 0, // 236: case 0x1: {
2827 OPC_CheckPredicate, 0, // 238: check predicate 0
2828 OPC_CheckField, 30, 2, 3, // 240: check Inst[31:30] == 0x3
2829 OPC_Decode, 136, 6, 108, // 244: decode to STDFAri using decoder 108
2830 // 244: }
2831 // 244: } // switch Inst[13]
2832 // 244: }
2833 58, 0, // 248: case 0x3a: {
2834 OPC_SwitchField, 8, 6, // 250: switch Inst[13:8] {
2835 0, 14, // 253: case 0x0: {
2836 OPC_CheckPredicate, 0, // 255: check predicate 0
2837 OPC_CheckField, 29, 3, 4, // 257: check Inst[31:29] == 0x4
2838 OPC_CheckField, 5, 3, 0, // 261: check Inst[7:5] == 0x0
2839 OPC_Decode, 188, 6, 80, // 265: decode to TICCrr using decoder 80
2840 // 265: }
2841 32, 0, // 269: case 0x20: {
2842 OPC_CheckPredicate, 0, // 271: check predicate 0
2843 OPC_CheckField, 29, 3, 4, // 273: check Inst[31:29] == 0x4
2844 OPC_Decode, 187, 6, 81, // 277: decode to TICCri using decoder 81
2845 // 277: }
2846 // 277: } // switch Inst[13:8]
2847 // 277: }
2848 // 277: } // switch Inst[24:19]
2849};
2850// Handling 133 cases.
2851template <typename InsnType>
2852static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
2853 DecodeComplete = true;
2854 using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
2855 TmpType tmp;
2856 switch (Idx) {
2857 default: llvm_unreachable("Invalid decoder index!");
2858 case 0:
2859 tmp = fieldFromInstruction(insn, 0, 22);
2860 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2861 return S;
2862 case 1:
2863 tmp = fieldFromInstruction(insn, 0, 19);
2864 if (!Check(S, DecodeDisp<19>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2865 tmp = fieldFromInstruction(insn, 25, 4);
2866 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2867 return S;
2868 case 2:
2869 tmp = fieldFromInstruction(insn, 0, 22);
2870 if (!Check(S, DecodeDisp<22>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2871 return S;
2872 case 3:
2873 tmp = fieldFromInstruction(insn, 0, 22);
2874 if (!Check(S, DecodeDisp<22>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2875 tmp = fieldFromInstruction(insn, 25, 4);
2876 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2877 return S;
2878 case 4:
2879 tmp = 0x0;
2880 tmp |= fieldFromInstruction(insn, 0, 14);
2881 tmp |= fieldFromInstruction(insn, 20, 2) << 14;
2882 if (!Check(S, DecodeDisp<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2883 tmp = fieldFromInstruction(insn, 25, 3);
2884 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2885 tmp = fieldFromInstruction(insn, 14, 5);
2886 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2887 return S;
2888 case 5:
2889 tmp = 0x0;
2890 tmp |= fieldFromInstruction(insn, 5, 8);
2891 tmp |= fieldFromInstruction(insn, 19, 2) << 8;
2892 if (!Check(S, DecodeDisp<10>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2893 tmp = 0x0;
2894 tmp |= fieldFromInstruction(insn, 25, 3);
2895 tmp |= fieldFromInstruction(insn, 29, 1) << 3;
2896 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2897 tmp = fieldFromInstruction(insn, 14, 5);
2898 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2899 tmp = fieldFromInstruction(insn, 0, 5);
2900 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2901 return S;
2902 case 6:
2903 tmp = 0x0;
2904 tmp |= fieldFromInstruction(insn, 5, 8);
2905 tmp |= fieldFromInstruction(insn, 19, 2) << 8;
2906 if (!Check(S, DecodeDisp<10>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2907 tmp = 0x0;
2908 tmp |= fieldFromInstruction(insn, 25, 3);
2909 tmp |= fieldFromInstruction(insn, 29, 1) << 3;
2910 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2911 tmp = fieldFromInstruction(insn, 14, 5);
2912 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2913 tmp = fieldFromInstruction(insn, 0, 5);
2914 if (!Check(S, DecodeSIMM5(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2915 return S;
2916 case 7:
2917 return S;
2918 case 8:
2919 tmp = fieldFromInstruction(insn, 25, 5);
2920 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2921 tmp = fieldFromInstruction(insn, 0, 22);
2922 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2923 return S;
2924 case 9:
2925 tmp = fieldFromInstruction(insn, 0, 19);
2926 if (!Check(S, DecodeDisp<19>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2927 tmp = fieldFromInstruction(insn, 25, 4);
2928 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2929 tmp = fieldFromInstruction(insn, 20, 2);
2930 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2931 return S;
2932 case 10:
2933 tmp = fieldFromInstruction(insn, 0, 30);
2934 if (!Check(S, DecodeCall(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2935 return S;
2936 case 11:
2937 tmp = fieldFromInstruction(insn, 25, 5);
2938 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2939 tmp = fieldFromInstruction(insn, 14, 5);
2940 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2941 tmp = fieldFromInstruction(insn, 0, 5);
2942 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2943 return S;
2944 case 12:
2945 tmp = fieldFromInstruction(insn, 25, 5);
2946 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2947 tmp = fieldFromInstruction(insn, 14, 5);
2948 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2949 tmp = fieldFromInstruction(insn, 0, 13);
2950 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2951 return S;
2952 case 13:
2953 tmp = fieldFromInstruction(insn, 25, 5);
2954 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2955 tmp = fieldFromInstruction(insn, 14, 5);
2956 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2957 tmp = fieldFromInstruction(insn, 0, 5);
2958 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2959 return S;
2960 case 14:
2961 tmp = fieldFromInstruction(insn, 25, 5);
2962 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2963 tmp = fieldFromInstruction(insn, 14, 5);
2964 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2965 tmp = fieldFromInstruction(insn, 0, 13);
2966 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
2967 return S;
2968 case 15:
2969 tmp = fieldFromInstruction(insn, 25, 5);
2970 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2971 tmp = fieldFromInstruction(insn, 14, 5);
2972 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2973 tmp = fieldFromInstruction(insn, 0, 5);
2974 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2975 tmp = fieldFromInstruction(insn, 9, 5);
2976 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2977 return S;
2978 case 16:
2979 tmp = fieldFromInstruction(insn, 25, 5);
2980 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2981 tmp = fieldFromInstruction(insn, 14, 5);
2982 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2983 tmp = fieldFromInstruction(insn, 0, 5);
2984 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2985 tmp = fieldFromInstruction(insn, 9, 5);
2986 if (!Check(S, DecodeSIMM5(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2987 return S;
2988 case 17:
2989 tmp = fieldFromInstruction(insn, 25, 5);
2990 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2991 tmp = fieldFromInstruction(insn, 14, 5);
2992 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2993 tmp = fieldFromInstruction(insn, 0, 5);
2994 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2995 return S;
2996 case 18:
2997 tmp = fieldFromInstruction(insn, 25, 5);
2998 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
2999 tmp = fieldFromInstruction(insn, 14, 5);
3000 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3001 tmp = fieldFromInstruction(insn, 0, 6);
3002 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3003 return S;
3004 case 19:
3005 tmp = fieldFromInstruction(insn, 25, 5);
3006 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3007 tmp = fieldFromInstruction(insn, 14, 5);
3008 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3009 tmp = fieldFromInstruction(insn, 0, 6);
3010 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3011 return S;
3012 case 20:
3013 tmp = fieldFromInstruction(insn, 25, 5);
3014 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3015 tmp = fieldFromInstruction(insn, 14, 5);
3016 if (!Check(S, DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3017 return S;
3018 case 21:
3019 tmp = fieldFromInstruction(insn, 0, 13);
3020 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3021 return S;
3022 case 22:
3023 tmp = fieldFromInstruction(insn, 25, 5);
3024 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3025 return S;
3026 case 23:
3027 tmp = fieldFromInstruction(insn, 25, 5);
3028 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3029 tmp = fieldFromInstruction(insn, 14, 5);
3030 if (!Check(S, DecodePRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3031 return S;
3032 case 24:
3033 tmp = fieldFromInstruction(insn, 25, 5);
3034 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3035 tmp = fieldFromInstruction(insn, 0, 5);
3036 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3037 tmp = fieldFromInstruction(insn, 25, 5);
3038 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3039 tmp = fieldFromInstruction(insn, 14, 4);
3040 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3041 return S;
3042 case 25:
3043 tmp = fieldFromInstruction(insn, 25, 5);
3044 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3045 tmp = fieldFromInstruction(insn, 11, 2);
3046 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3047 tmp = fieldFromInstruction(insn, 0, 5);
3048 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3049 tmp = fieldFromInstruction(insn, 25, 5);
3050 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3051 tmp = fieldFromInstruction(insn, 14, 4);
3052 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3053 return S;
3054 case 26:
3055 tmp = fieldFromInstruction(insn, 25, 5);
3056 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3057 tmp = fieldFromInstruction(insn, 0, 11);
3058 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3059 tmp = fieldFromInstruction(insn, 25, 5);
3060 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3061 tmp = fieldFromInstruction(insn, 14, 4);
3062 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3063 return S;
3064 case 27:
3065 tmp = fieldFromInstruction(insn, 25, 5);
3066 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3067 tmp = fieldFromInstruction(insn, 11, 2);
3068 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3069 tmp = fieldFromInstruction(insn, 0, 11);
3070 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3071 tmp = fieldFromInstruction(insn, 25, 5);
3072 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3073 tmp = fieldFromInstruction(insn, 14, 4);
3074 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3075 return S;
3076 case 28:
3077 tmp = fieldFromInstruction(insn, 25, 5);
3078 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3079 tmp = fieldFromInstruction(insn, 0, 5);
3080 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3081 return S;
3082 case 29:
3083 tmp = fieldFromInstruction(insn, 25, 5);
3084 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3085 tmp = fieldFromInstruction(insn, 14, 5);
3086 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3087 tmp = fieldFromInstruction(insn, 0, 5);
3088 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3089 tmp = fieldFromInstruction(insn, 25, 5);
3090 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3091 tmp = fieldFromInstruction(insn, 10, 3);
3092 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3093 return S;
3094 case 30:
3095 tmp = fieldFromInstruction(insn, 25, 5);
3096 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3097 tmp = fieldFromInstruction(insn, 14, 5);
3098 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3099 tmp = fieldFromInstruction(insn, 0, 10);
3100 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3101 tmp = fieldFromInstruction(insn, 25, 5);
3102 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3103 tmp = fieldFromInstruction(insn, 10, 3);
3104 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3105 return S;
3106 case 31:
3107 tmp = fieldFromInstruction(insn, 25, 5);
3108 if (!Check(S, DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3109 tmp = fieldFromInstruction(insn, 14, 5);
3110 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3111 tmp = fieldFromInstruction(insn, 0, 5);
3112 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3113 return S;
3114 case 32:
3115 tmp = fieldFromInstruction(insn, 0, 13);
3116 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3117 return S;
3118 case 33:
3119 tmp = fieldFromInstruction(insn, 25, 5);
3120 if (!Check(S, DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3121 tmp = fieldFromInstruction(insn, 14, 5);
3122 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3123 tmp = fieldFromInstruction(insn, 0, 13);
3124 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3125 return S;
3126 case 34:
3127 tmp = fieldFromInstruction(insn, 14, 5);
3128 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3129 tmp = fieldFromInstruction(insn, 0, 5);
3130 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3131 return S;
3132 case 35:
3133 tmp = fieldFromInstruction(insn, 14, 5);
3134 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3135 tmp = fieldFromInstruction(insn, 0, 13);
3136 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3137 return S;
3138 case 36:
3139 tmp = fieldFromInstruction(insn, 25, 5);
3140 if (!Check(S, DecodePRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3141 tmp = fieldFromInstruction(insn, 14, 5);
3142 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3143 tmp = fieldFromInstruction(insn, 0, 5);
3144 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3145 return S;
3146 case 37:
3147 tmp = fieldFromInstruction(insn, 25, 5);
3148 if (!Check(S, DecodePRRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3149 tmp = fieldFromInstruction(insn, 14, 5);
3150 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3151 tmp = fieldFromInstruction(insn, 0, 13);
3152 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3153 return S;
3154 case 38:
3155 tmp = fieldFromInstruction(insn, 25, 5);
3156 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3157 tmp = fieldFromInstruction(insn, 0, 5);
3158 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3159 return S;
3160 case 39:
3161 tmp = fieldFromInstruction(insn, 25, 5);
3162 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3163 tmp = fieldFromInstruction(insn, 0, 5);
3164 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3165 return S;
3166 case 40:
3167 tmp = fieldFromInstruction(insn, 25, 5);
3168 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3169 tmp = fieldFromInstruction(insn, 0, 5);
3170 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3171 return S;
3172 case 41:
3173 tmp = fieldFromInstruction(insn, 25, 5);
3174 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3175 tmp = fieldFromInstruction(insn, 14, 5);
3176 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3177 tmp = fieldFromInstruction(insn, 0, 5);
3178 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3179 return S;
3180 case 42:
3181 tmp = fieldFromInstruction(insn, 25, 5);
3182 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3183 tmp = fieldFromInstruction(insn, 14, 5);
3184 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3185 tmp = fieldFromInstruction(insn, 0, 5);
3186 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3187 return S;
3188 case 43:
3189 tmp = fieldFromInstruction(insn, 25, 5);
3190 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3191 tmp = fieldFromInstruction(insn, 14, 5);
3192 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3193 tmp = fieldFromInstruction(insn, 0, 5);
3194 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3195 return S;
3196 case 44:
3197 tmp = fieldFromInstruction(insn, 25, 5);
3198 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3199 tmp = fieldFromInstruction(insn, 14, 5);
3200 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3201 tmp = fieldFromInstruction(insn, 0, 5);
3202 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3203 return S;
3204 case 45:
3205 tmp = fieldFromInstruction(insn, 25, 5);
3206 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3207 tmp = fieldFromInstruction(insn, 14, 5);
3208 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3209 tmp = fieldFromInstruction(insn, 0, 5);
3210 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3211 return S;
3212 case 46:
3213 tmp = fieldFromInstruction(insn, 25, 5);
3214 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3215 tmp = fieldFromInstruction(insn, 0, 5);
3216 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3217 return S;
3218 case 47:
3219 tmp = fieldFromInstruction(insn, 25, 5);
3220 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3221 tmp = fieldFromInstruction(insn, 0, 5);
3222 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3223 return S;
3224 case 48:
3225 tmp = fieldFromInstruction(insn, 25, 5);
3226 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3227 tmp = fieldFromInstruction(insn, 0, 5);
3228 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3229 return S;
3230 case 49:
3231 tmp = fieldFromInstruction(insn, 25, 5);
3232 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3233 tmp = fieldFromInstruction(insn, 0, 5);
3234 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3235 return S;
3236 case 50:
3237 tmp = fieldFromInstruction(insn, 25, 5);
3238 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3239 tmp = fieldFromInstruction(insn, 0, 5);
3240 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3241 return S;
3242 case 51:
3243 tmp = fieldFromInstruction(insn, 25, 5);
3244 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3245 tmp = fieldFromInstruction(insn, 0, 5);
3246 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3247 return S;
3248 case 52:
3249 tmp = fieldFromInstruction(insn, 25, 5);
3250 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3251 tmp = fieldFromInstruction(insn, 0, 5);
3252 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3253 tmp = fieldFromInstruction(insn, 25, 5);
3254 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3255 tmp = fieldFromInstruction(insn, 14, 4);
3256 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3257 return S;
3258 case 53:
3259 tmp = fieldFromInstruction(insn, 25, 5);
3260 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3261 tmp = fieldFromInstruction(insn, 11, 2);
3262 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3263 tmp = fieldFromInstruction(insn, 0, 5);
3264 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3265 tmp = fieldFromInstruction(insn, 25, 5);
3266 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3267 tmp = fieldFromInstruction(insn, 14, 4);
3268 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3269 return S;
3270 case 54:
3271 tmp = fieldFromInstruction(insn, 25, 5);
3272 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3273 tmp = fieldFromInstruction(insn, 0, 5);
3274 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3275 tmp = fieldFromInstruction(insn, 25, 5);
3276 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3277 tmp = fieldFromInstruction(insn, 14, 4);
3278 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3279 return S;
3280 case 55:
3281 tmp = fieldFromInstruction(insn, 25, 5);
3282 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3283 tmp = fieldFromInstruction(insn, 11, 2);
3284 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3285 tmp = fieldFromInstruction(insn, 0, 5);
3286 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3287 tmp = fieldFromInstruction(insn, 25, 5);
3288 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3289 tmp = fieldFromInstruction(insn, 14, 4);
3290 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3291 return S;
3292 case 56:
3293 tmp = fieldFromInstruction(insn, 25, 5);
3294 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3295 tmp = fieldFromInstruction(insn, 0, 5);
3296 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3297 tmp = fieldFromInstruction(insn, 25, 5);
3298 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3299 tmp = fieldFromInstruction(insn, 14, 4);
3300 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3301 return S;
3302 case 57:
3303 tmp = fieldFromInstruction(insn, 25, 5);
3304 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3305 tmp = fieldFromInstruction(insn, 11, 2);
3306 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3307 tmp = fieldFromInstruction(insn, 0, 5);
3308 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3309 tmp = fieldFromInstruction(insn, 25, 5);
3310 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3311 tmp = fieldFromInstruction(insn, 14, 4);
3312 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3313 return S;
3314 case 58:
3315 tmp = fieldFromInstruction(insn, 25, 5);
3316 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3317 tmp = fieldFromInstruction(insn, 14, 5);
3318 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3319 tmp = fieldFromInstruction(insn, 0, 5);
3320 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3321 tmp = fieldFromInstruction(insn, 25, 5);
3322 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3323 tmp = fieldFromInstruction(insn, 10, 3);
3324 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3325 return S;
3326 case 59:
3327 tmp = fieldFromInstruction(insn, 25, 5);
3328 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3329 tmp = fieldFromInstruction(insn, 14, 5);
3330 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3331 tmp = fieldFromInstruction(insn, 0, 5);
3332 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3333 tmp = fieldFromInstruction(insn, 25, 5);
3334 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3335 tmp = fieldFromInstruction(insn, 10, 3);
3336 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3337 return S;
3338 case 60:
3339 tmp = fieldFromInstruction(insn, 25, 5);
3340 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3341 tmp = fieldFromInstruction(insn, 14, 5);
3342 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3343 tmp = fieldFromInstruction(insn, 0, 5);
3344 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3345 tmp = fieldFromInstruction(insn, 25, 5);
3346 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3347 tmp = fieldFromInstruction(insn, 10, 3);
3348 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3349 return S;
3350 case 61:
3351 tmp = fieldFromInstruction(insn, 25, 5);
3352 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3353 tmp = fieldFromInstruction(insn, 14, 5);
3354 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3355 tmp = fieldFromInstruction(insn, 0, 5);
3356 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3357 return S;
3358 case 62:
3359 tmp = fieldFromInstruction(insn, 25, 5);
3360 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3361 tmp = fieldFromInstruction(insn, 14, 5);
3362 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3363 tmp = fieldFromInstruction(insn, 0, 5);
3364 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3365 return S;
3366 case 63:
3367 tmp = fieldFromInstruction(insn, 25, 5);
3368 if (!Check(S, DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3369 tmp = fieldFromInstruction(insn, 14, 5);
3370 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3371 tmp = fieldFromInstruction(insn, 0, 5);
3372 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3373 return S;
3374 case 64:
3375 tmp = fieldFromInstruction(insn, 25, 5);
3376 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3377 tmp = fieldFromInstruction(insn, 0, 5);
3378 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3379 return S;
3380 case 65:
3381 tmp = fieldFromInstruction(insn, 0, 5);
3382 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3383 return S;
3384 case 66:
3385 tmp = fieldFromInstruction(insn, 25, 5);
3386 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3387 tmp = fieldFromInstruction(insn, 14, 5);
3388 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3389 tmp = fieldFromInstruction(insn, 0, 5);
3390 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3391 return S;
3392 case 67:
3393 tmp = fieldFromInstruction(insn, 25, 5);
3394 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3395 tmp = fieldFromInstruction(insn, 14, 5);
3396 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3397 tmp = fieldFromInstruction(insn, 0, 5);
3398 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3399 return S;
3400 case 68:
3401 tmp = fieldFromInstruction(insn, 25, 5);
3402 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3403 return S;
3404 case 69:
3405 tmp = fieldFromInstruction(insn, 25, 5);
3406 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3407 return S;
3408 case 70:
3409 tmp = fieldFromInstruction(insn, 25, 5);
3410 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3411 tmp = fieldFromInstruction(insn, 14, 5);
3412 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3413 return S;
3414 case 71:
3415 tmp = fieldFromInstruction(insn, 25, 5);
3416 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3417 tmp = fieldFromInstruction(insn, 14, 5);
3418 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3419 return S;
3420 case 72:
3421 tmp = fieldFromInstruction(insn, 0, 3);
3422 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3423 return S;
3424 case 73:
3425 tmp = fieldFromInstruction(insn, 25, 5);
3426 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3427 tmp = fieldFromInstruction(insn, 0, 5);
3428 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3429 return S;
3430 case 74:
3431 tmp = fieldFromInstruction(insn, 25, 5);
3432 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3433 tmp = fieldFromInstruction(insn, 0, 5);
3434 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3435 return S;
3436 case 75:
3437 tmp = fieldFromInstruction(insn, 25, 5);
3438 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3439 tmp = fieldFromInstruction(insn, 0, 5);
3440 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3441 return S;
3442 case 76:
3443 tmp = fieldFromInstruction(insn, 25, 5);
3444 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3445 tmp = fieldFromInstruction(insn, 0, 5);
3446 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3447 return S;
3448 case 77:
3449 tmp = fieldFromInstruction(insn, 25, 5);
3450 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3451 tmp = fieldFromInstruction(insn, 14, 5);
3452 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3453 tmp = fieldFromInstruction(insn, 0, 5);
3454 if (!Check(S, DecodeSIMM5(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3455 return S;
3456 case 78:
3457 tmp = fieldFromInstruction(insn, 0, 5);
3458 if (!Check(S, DecodeSIMM5(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3459 return S;
3460 case 79:
3461 tmp = fieldFromInstruction(insn, 25, 5);
3462 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3463 tmp = fieldFromInstruction(insn, 14, 5);
3464 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3465 tmp = fieldFromInstruction(insn, 0, 5);
3466 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3467 tmp = fieldFromInstruction(insn, 9, 5);
3468 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3469 return S;
3470 case 80:
3471 tmp = fieldFromInstruction(insn, 14, 5);
3472 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3473 tmp = fieldFromInstruction(insn, 0, 5);
3474 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3475 tmp = fieldFromInstruction(insn, 25, 4);
3476 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3477 return S;
3478 case 81:
3479 tmp = fieldFromInstruction(insn, 14, 5);
3480 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3481 tmp = fieldFromInstruction(insn, 0, 8);
3482 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3483 tmp = fieldFromInstruction(insn, 25, 4);
3484 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3485 return S;
3486 case 82:
3487 tmp = fieldFromInstruction(insn, 25, 5);
3488 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3489 tmp = fieldFromInstruction(insn, 14, 5);
3490 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3491 tmp = fieldFromInstruction(insn, 0, 5);
3492 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3493 return S;
3494 case 83:
3495 tmp = fieldFromInstruction(insn, 25, 5);
3496 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3497 tmp = fieldFromInstruction(insn, 14, 5);
3498 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3499 tmp = fieldFromInstruction(insn, 0, 13);
3500 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3501 return S;
3502 case 84:
3503 tmp = fieldFromInstruction(insn, 14, 5);
3504 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3505 tmp = fieldFromInstruction(insn, 0, 5);
3506 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3507 tmp = fieldFromInstruction(insn, 25, 5);
3508 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3509 return S;
3510 case 85:
3511 tmp = fieldFromInstruction(insn, 14, 5);
3512 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3513 tmp = fieldFromInstruction(insn, 0, 13);
3514 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3515 tmp = fieldFromInstruction(insn, 25, 5);
3516 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3517 return S;
3518 case 86:
3519 tmp = fieldFromInstruction(insn, 14, 5);
3520 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3521 tmp = fieldFromInstruction(insn, 0, 5);
3522 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3523 tmp = fieldFromInstruction(insn, 25, 5);
3524 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3525 return S;
3526 case 87:
3527 tmp = fieldFromInstruction(insn, 14, 5);
3528 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3529 tmp = fieldFromInstruction(insn, 0, 13);
3530 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3531 tmp = fieldFromInstruction(insn, 25, 5);
3532 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3533 return S;
3534 case 88:
3535 tmp = fieldFromInstruction(insn, 25, 5);
3536 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3537 tmp = fieldFromInstruction(insn, 14, 5);
3538 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3539 tmp = fieldFromInstruction(insn, 0, 5);
3540 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3541 return S;
3542 case 89:
3543 tmp = fieldFromInstruction(insn, 25, 5);
3544 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3545 tmp = fieldFromInstruction(insn, 14, 5);
3546 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3547 tmp = fieldFromInstruction(insn, 0, 13);
3548 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3549 return S;
3550 case 90:
3551 tmp = fieldFromInstruction(insn, 14, 5);
3552 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3553 tmp = fieldFromInstruction(insn, 0, 5);
3554 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3555 tmp = fieldFromInstruction(insn, 25, 5);
3556 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3557 return S;
3558 case 91:
3559 tmp = fieldFromInstruction(insn, 14, 5);
3560 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3561 tmp = fieldFromInstruction(insn, 0, 13);
3562 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3563 tmp = fieldFromInstruction(insn, 25, 5);
3564 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3565 return S;
3566 case 92:
3567 tmp = fieldFromInstruction(insn, 25, 5);
3568 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3569 tmp = fieldFromInstruction(insn, 14, 5);
3570 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3571 tmp = fieldFromInstruction(insn, 0, 5);
3572 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3573 tmp = fieldFromInstruction(insn, 25, 5);
3574 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3575 return S;
3576 case 93:
3577 tmp = fieldFromInstruction(insn, 25, 5);
3578 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3579 tmp = fieldFromInstruction(insn, 14, 5);
3580 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3581 tmp = fieldFromInstruction(insn, 0, 13);
3582 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3583 tmp = fieldFromInstruction(insn, 25, 5);
3584 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3585 return S;
3586 case 94:
3587 tmp = fieldFromInstruction(insn, 25, 5);
3588 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3589 tmp = fieldFromInstruction(insn, 14, 5);
3590 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3591 tmp = fieldFromInstruction(insn, 0, 5);
3592 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3593 tmp = fieldFromInstruction(insn, 5, 8);
3594 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3595 return S;
3596 case 95:
3597 tmp = fieldFromInstruction(insn, 25, 5);
3598 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3599 tmp = fieldFromInstruction(insn, 14, 5);
3600 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3601 tmp = fieldFromInstruction(insn, 0, 5);
3602 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3603 tmp = fieldFromInstruction(insn, 5, 8);
3604 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3605 return S;
3606 case 96:
3607 tmp = fieldFromInstruction(insn, 14, 5);
3608 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3609 tmp = fieldFromInstruction(insn, 0, 5);
3610 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3611 tmp = fieldFromInstruction(insn, 25, 5);
3612 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3613 tmp = fieldFromInstruction(insn, 5, 8);
3614 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3615 return S;
3616 case 97:
3617 tmp = fieldFromInstruction(insn, 14, 5);
3618 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3619 tmp = fieldFromInstruction(insn, 0, 5);
3620 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3621 tmp = fieldFromInstruction(insn, 25, 5);
3622 if (!Check(S, DecodeIntPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3623 tmp = fieldFromInstruction(insn, 5, 8);
3624 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3625 return S;
3626 case 98:
3627 tmp = fieldFromInstruction(insn, 25, 5);
3628 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3629 tmp = fieldFromInstruction(insn, 14, 5);
3630 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3631 tmp = fieldFromInstruction(insn, 0, 5);
3632 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3633 tmp = fieldFromInstruction(insn, 5, 8);
3634 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3635 return S;
3636 case 99:
3637 tmp = fieldFromInstruction(insn, 14, 5);
3638 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3639 tmp = fieldFromInstruction(insn, 0, 5);
3640 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3641 tmp = fieldFromInstruction(insn, 25, 5);
3642 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3643 tmp = fieldFromInstruction(insn, 5, 8);
3644 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3645 return S;
3646 case 100:
3647 tmp = fieldFromInstruction(insn, 25, 5);
3648 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3649 tmp = fieldFromInstruction(insn, 14, 5);
3650 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3651 tmp = fieldFromInstruction(insn, 0, 5);
3652 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3653 tmp = fieldFromInstruction(insn, 5, 8);
3654 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3655 tmp = fieldFromInstruction(insn, 25, 5);
3656 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3657 return S;
3658 case 101:
3659 tmp = fieldFromInstruction(insn, 25, 5);
3660 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3661 tmp = fieldFromInstruction(insn, 14, 5);
3662 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3663 tmp = fieldFromInstruction(insn, 0, 5);
3664 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3665 return S;
3666 case 102:
3667 tmp = fieldFromInstruction(insn, 25, 5);
3668 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3669 tmp = fieldFromInstruction(insn, 14, 5);
3670 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3671 tmp = fieldFromInstruction(insn, 0, 13);
3672 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3673 return S;
3674 case 103:
3675 tmp = fieldFromInstruction(insn, 25, 5);
3676 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3677 tmp = fieldFromInstruction(insn, 14, 5);
3678 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3679 tmp = fieldFromInstruction(insn, 0, 5);
3680 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3681 return S;
3682 case 104:
3683 tmp = fieldFromInstruction(insn, 25, 5);
3684 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3685 tmp = fieldFromInstruction(insn, 14, 5);
3686 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3687 tmp = fieldFromInstruction(insn, 0, 13);
3688 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3689 return S;
3690 case 105:
3691 tmp = fieldFromInstruction(insn, 14, 5);
3692 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3693 tmp = fieldFromInstruction(insn, 0, 5);
3694 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3695 tmp = fieldFromInstruction(insn, 25, 5);
3696 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3697 return S;
3698 case 106:
3699 tmp = fieldFromInstruction(insn, 14, 5);
3700 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3701 tmp = fieldFromInstruction(insn, 0, 13);
3702 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3703 tmp = fieldFromInstruction(insn, 25, 5);
3704 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3705 return S;
3706 case 107:
3707 tmp = fieldFromInstruction(insn, 14, 5);
3708 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3709 tmp = fieldFromInstruction(insn, 0, 5);
3710 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3711 tmp = fieldFromInstruction(insn, 25, 5);
3712 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3713 return S;
3714 case 108:
3715 tmp = fieldFromInstruction(insn, 14, 5);
3716 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3717 tmp = fieldFromInstruction(insn, 0, 13);
3718 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3719 tmp = fieldFromInstruction(insn, 25, 5);
3720 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3721 return S;
3722 case 109:
3723 tmp = fieldFromInstruction(insn, 14, 5);
3724 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3725 tmp = fieldFromInstruction(insn, 0, 5);
3726 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3727 tmp = fieldFromInstruction(insn, 25, 5);
3728 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3729 return S;
3730 case 110:
3731 tmp = fieldFromInstruction(insn, 14, 5);
3732 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3733 tmp = fieldFromInstruction(insn, 0, 13);
3734 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3735 tmp = fieldFromInstruction(insn, 25, 5);
3736 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3737 return S;
3738 case 111:
3739 tmp = fieldFromInstruction(insn, 25, 5);
3740 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3741 tmp = fieldFromInstruction(insn, 14, 5);
3742 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3743 tmp = fieldFromInstruction(insn, 0, 5);
3744 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3745 tmp = fieldFromInstruction(insn, 25, 5);
3746 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3747 tmp = fieldFromInstruction(insn, 5, 8);
3748 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3749 return S;
3750 case 112:
3751 tmp = fieldFromInstruction(insn, 14, 5);
3752 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3753 tmp = fieldFromInstruction(insn, 0, 5);
3754 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3755 tmp = fieldFromInstruction(insn, 5, 8);
3756 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3757 tmp = fieldFromInstruction(insn, 25, 5);
3758 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3759 return S;
3760 case 113:
3761 tmp = fieldFromInstruction(insn, 25, 5);
3762 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3763 tmp = fieldFromInstruction(insn, 14, 5);
3764 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3765 tmp = fieldFromInstruction(insn, 0, 5);
3766 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3767 tmp = fieldFromInstruction(insn, 25, 5);
3768 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3769 tmp = fieldFromInstruction(insn, 5, 8);
3770 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3771 return S;
3772 case 114:
3773 tmp = fieldFromInstruction(insn, 25, 5);
3774 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3775 tmp = fieldFromInstruction(insn, 14, 5);
3776 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3777 tmp = fieldFromInstruction(insn, 0, 5);
3778 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3779 tmp = fieldFromInstruction(insn, 25, 5);
3780 if (!Check(S, DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3781 return S;
3782 case 115:
3783 tmp = fieldFromInstruction(insn, 25, 5);
3784 if (!Check(S, DecodeCoprocRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3785 tmp = fieldFromInstruction(insn, 14, 5);
3786 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3787 tmp = fieldFromInstruction(insn, 0, 5);
3788 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3789 return S;
3790 case 116:
3791 tmp = fieldFromInstruction(insn, 25, 5);
3792 if (!Check(S, DecodeCoprocRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3793 tmp = fieldFromInstruction(insn, 14, 5);
3794 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3795 tmp = fieldFromInstruction(insn, 0, 13);
3796 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3797 return S;
3798 case 117:
3799 tmp = fieldFromInstruction(insn, 25, 5);
3800 if (!Check(S, DecodeCoprocPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3801 tmp = fieldFromInstruction(insn, 14, 5);
3802 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3803 tmp = fieldFromInstruction(insn, 0, 5);
3804 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3805 return S;
3806 case 118:
3807 tmp = fieldFromInstruction(insn, 25, 5);
3808 if (!Check(S, DecodeCoprocPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3809 tmp = fieldFromInstruction(insn, 14, 5);
3810 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3811 tmp = fieldFromInstruction(insn, 0, 13);
3812 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3813 return S;
3814 case 119:
3815 tmp = fieldFromInstruction(insn, 14, 5);
3816 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3817 tmp = fieldFromInstruction(insn, 0, 5);
3818 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3819 tmp = fieldFromInstruction(insn, 25, 5);
3820 if (!Check(S, DecodeCoprocRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3821 return S;
3822 case 120:
3823 tmp = fieldFromInstruction(insn, 14, 5);
3824 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3825 tmp = fieldFromInstruction(insn, 0, 13);
3826 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3827 tmp = fieldFromInstruction(insn, 25, 5);
3828 if (!Check(S, DecodeCoprocRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3829 return S;
3830 case 121:
3831 tmp = fieldFromInstruction(insn, 14, 5);
3832 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3833 tmp = fieldFromInstruction(insn, 0, 5);
3834 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3835 tmp = fieldFromInstruction(insn, 25, 5);
3836 if (!Check(S, DecodeCoprocPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3837 return S;
3838 case 122:
3839 tmp = fieldFromInstruction(insn, 14, 5);
3840 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3841 tmp = fieldFromInstruction(insn, 0, 13);
3842 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3843 tmp = fieldFromInstruction(insn, 25, 5);
3844 if (!Check(S, DecodeCoprocPairRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3845 return S;
3846 case 123:
3847 tmp = fieldFromInstruction(insn, 25, 5);
3848 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3849 tmp = fieldFromInstruction(insn, 14, 5);
3850 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3851 tmp = fieldFromInstruction(insn, 0, 5);
3852 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3853 return S;
3854 case 124:
3855 tmp = fieldFromInstruction(insn, 25, 5);
3856 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3857 tmp = fieldFromInstruction(insn, 14, 5);
3858 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3859 tmp = fieldFromInstruction(insn, 0, 13);
3860 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3861 return S;
3862 case 125:
3863 tmp = fieldFromInstruction(insn, 14, 5);
3864 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3865 tmp = fieldFromInstruction(insn, 0, 5);
3866 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3867 tmp = fieldFromInstruction(insn, 25, 5);
3868 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3869 return S;
3870 case 126:
3871 tmp = fieldFromInstruction(insn, 14, 5);
3872 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3873 tmp = fieldFromInstruction(insn, 0, 13);
3874 if (!Check(S, DecodeSIMM13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3875 tmp = fieldFromInstruction(insn, 25, 5);
3876 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3877 return S;
3878 case 127:
3879 tmp = fieldFromInstruction(insn, 25, 5);
3880 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3881 tmp = fieldFromInstruction(insn, 14, 5);
3882 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3883 tmp = fieldFromInstruction(insn, 0, 5);
3884 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3885 tmp = fieldFromInstruction(insn, 5, 8);
3886 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3887 return S;
3888 case 128:
3889 tmp = fieldFromInstruction(insn, 25, 5);
3890 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3891 tmp = fieldFromInstruction(insn, 14, 5);
3892 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3893 tmp = fieldFromInstruction(insn, 0, 5);
3894 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3895 tmp = fieldFromInstruction(insn, 5, 8);
3896 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3897 return S;
3898 case 129:
3899 tmp = fieldFromInstruction(insn, 25, 5);
3900 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3901 tmp = fieldFromInstruction(insn, 14, 5);
3902 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3903 tmp = fieldFromInstruction(insn, 0, 5);
3904 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3905 tmp = fieldFromInstruction(insn, 5, 8);
3906 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3907 return S;
3908 case 130:
3909 tmp = fieldFromInstruction(insn, 14, 5);
3910 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3911 tmp = fieldFromInstruction(insn, 0, 5);
3912 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3913 tmp = fieldFromInstruction(insn, 25, 5);
3914 if (!Check(S, DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3915 tmp = fieldFromInstruction(insn, 5, 8);
3916 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3917 return S;
3918 case 131:
3919 tmp = fieldFromInstruction(insn, 14, 5);
3920 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3921 tmp = fieldFromInstruction(insn, 0, 5);
3922 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3923 tmp = fieldFromInstruction(insn, 25, 5);
3924 if (!Check(S, DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3925 tmp = fieldFromInstruction(insn, 5, 8);
3926 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3927 return S;
3928 case 132:
3929 tmp = fieldFromInstruction(insn, 14, 5);
3930 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3931 tmp = fieldFromInstruction(insn, 0, 5);
3932 if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3933 tmp = fieldFromInstruction(insn, 25, 5);
3934 if (!Check(S, DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
3935 tmp = fieldFromInstruction(insn, 5, 8);
3936 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
3937 return S;
3938 }
3939}
3940static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset &FB) {
3941 switch (Idx) {
3942 default: llvm_unreachable("Invalid index!");
3943 case 0:
3944 return FB[Sparc::FeatureV9];
3945 case 1:
3946 return FB[Sparc::Feature64Bit];
3947 case 2:
3948 return FB[Sparc::FeatureOSA2011];
3949 case 3:
3950 return FB[Sparc::FeatureCrypto];
3951 case 4:
3952 return FB[Sparc::FeaturePWRPSR];
3953 case 5:
3954 return FB[Sparc::FeatureUA2005];
3955 case 6:
3956 return FB[Sparc::FeatureVIS3];
3957 case 7:
3958 return FB[Sparc::FeatureVIS];
3959 case 8:
3960 return FB[Sparc::FeatureVIS2];
3961 case 9:
3962 return FB[Sparc::FeatureUA2007];
3963 case 10:
3964 return FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9];
3965 case 11:
3966 return FB[Sparc::Feature64Bit] && FB[Sparc::FeatureV9];
3967 }
3968}
3969
3970
3971template <typename InsnType>
3972static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
3973 InsnType insn, uint64_t Address,
3974 const MCDisassembler *DisAsm,
3975 const MCSubtargetInfo &STI) {
3976 const FeatureBitset &Bits = STI.getFeatureBits();
3977 const uint8_t *Ptr = DecodeTable;
3978
3979 SmallVector<const uint8_t *, 8> ScopeStack;
3980 DecodeStatus S = MCDisassembler::Success;
3981 while (true) {
3982 ptrdiff_t Loc = Ptr - DecodeTable;
3983 const uint8_t DecoderOp = *Ptr++;
3984 switch (DecoderOp) {
3985 default:
3986 errs() << Loc << ": Unexpected decode table opcode: "
3987 << (int)DecoderOp << '\n';
3988 return MCDisassembler::Fail;
3989 case OPC_Scope: {
3990 unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr);
3991 const uint8_t *SkipTo = Ptr + NumToSkip;
3992 ScopeStack.push_back(Elt: SkipTo);
3993 LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
3994 << ")\n");
3995 continue;
3996 }
3997 case OPC_SwitchField: {
3998 // Decode the start value.
3999 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
4000 unsigned Len = *Ptr++;
4001 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
4002 uint64_t CaseValue;
4003 unsigned CaseSize;
4004 while (true) {
4005 CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr);
4006 CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr);
4007 if (FieldValue == CaseValue || !CaseSize)
4008 break;
4009 Ptr += CaseSize;
4010 }
4011 if (FieldValue == CaseValue) {
4012 LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
4013 << "): " << FieldValue << '\n');
4014 continue;
4015 }
4016 break;
4017 }
4018 case OPC_CheckField: {
4019 // Decode the start value.
4020 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
4021 unsigned Len = *Ptr;
4022 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
4023 // Decode the field value.
4024 unsigned PtrLen = 0;
4025 uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen);
4026 Ptr += PtrLen;
4027 bool Failed = ExpectedValue != FieldValue;
4028
4029 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
4030 << ", " << ExpectedValue << "): FieldValue = "
4031 << FieldValue << ", ExpectedValue = " << ExpectedValue
4032 << ": " << (Failed ? "FAIL, " : "PASS\n"););
4033 if (!Failed)
4034 continue;
4035 break;
4036 }
4037 case OPC_CheckPredicate: {
4038 // Decode the Predicate Index value.
4039 unsigned PIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
4040 // Check the predicate.
4041 bool Failed = !checkDecoderPredicate(Idx: PIdx, FB: Bits);
4042
4043 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate(" << PIdx << "): "
4044 << (Failed ? "FAIL, " : "PASS\n"););
4045 if (!Failed)
4046 continue;
4047 break;
4048 }
4049 case OPC_Decode: {
4050 // Decode the Opcode value.
4051 unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr);
4052 unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
4053
4054 MI.clear();
4055 MI.setOpcode(Opc);
4056 bool DecodeComplete;
4057 S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
4058 DecodeComplete);
4059 LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
4060 << ", using decoder " << DecodeIdx << ": "
4061 << (S ? "PASS, " : "FAIL, "));
4062
4063 if (DecodeComplete) {
4064 LLVM_DEBUG(dbgs() << "decoding complete\n");
4065 return S;
4066 }
4067 assert(S == MCDisassembler::Fail);
4068 // Reset decode status. This also drops a SoftFail status that could be
4069 // set before the decode attempt.
4070 S = MCDisassembler::Success;
4071 break;
4072 }
4073 }
4074 if (ScopeStack.empty()) {
4075 LLVM_DEBUG(dbgs() << "returning Fail\n");
4076 return MCDisassembler::Fail;
4077 }
4078 Ptr = ScopeStack.pop_back_val();
4079 LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
4080 }
4081 llvm_unreachable("bogosity detected in disassembler state machine!");
4082}
4083
4084
4085} // namespace
4086