1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t SparcMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(2155880448), // ADDCCri
14 UINT64_C(2155872256), // ADDCCrr
15 UINT64_C(2151686144), // ADDCri
16 UINT64_C(2151677952), // ADDCrr
17 UINT64_C(2160074752), // ADDEri
18 UINT64_C(2160066560), // ADDErr
19 UINT64_C(2175795744), // ADDXC
20 UINT64_C(2175795808), // ADDXCCC
21 UINT64_C(2147491840), // ADDri
22 UINT64_C(2147483648), // ADDrr
23 UINT64_C(2160590912), // AES_DROUND01
24 UINT64_C(2160591040), // AES_DROUND01_LAST
25 UINT64_C(2160590944), // AES_DROUND23
26 UINT64_C(2160591072), // AES_DROUND23_LAST
27 UINT64_C(2160590848), // AES_EROUND01
28 UINT64_C(2160590976), // AES_EROUND01_LAST
29 UINT64_C(2160590880), // AES_EROUND23
30 UINT64_C(2160591008), // AES_EROUND23_LAST
31 UINT64_C(2175804928), // AES_KEXPAND0
32 UINT64_C(2160591104), // AES_KEXPAND1
33 UINT64_C(2175804960), // AES_KEXPAND2
34 UINT64_C(2175795968), // ALIGNADDR
35 UINT64_C(2175796032), // ALIGNADDRL
36 UINT64_C(2240282624), // ALLCLEAN
37 UINT64_C(2156404736), // ANDCCri
38 UINT64_C(2156396544), // ANDCCrr
39 UINT64_C(2158501888), // ANDNCCri
40 UINT64_C(2158493696), // ANDNCCrr
41 UINT64_C(2150113280), // ANDNri
42 UINT64_C(2150105088), // ANDNrr
43 UINT64_C(2148016128), // ANDri
44 UINT64_C(2148007936), // ANDrr
45 UINT64_C(2175795776), // ARRAY16
46 UINT64_C(2175795840), // ARRAY32
47 UINT64_C(2175795712), // ARRAY8
48 UINT64_C(276824064), // BA
49 UINT64_C(8388608), // BCOND
50 UINT64_C(545259520), // BCONDA
51 UINT64_C(2176851968), // BINDri
52 UINT64_C(2176843776), // BINDrr
53 UINT64_C(2175796000), // BMASK
54 UINT64_C(21495808), // BPFCC
55 UINT64_C(558366720), // BPFCCA
56 UINT64_C(557842432), // BPFCCANT
57 UINT64_C(20971520), // BPFCCNT
58 UINT64_C(4718592), // BPICC
59 UINT64_C(541589504), // BPICCA
60 UINT64_C(541065216), // BPICCANT
61 UINT64_C(4194304), // BPICCNT
62 UINT64_C(13107200), // BPR
63 UINT64_C(549978112), // BPRA
64 UINT64_C(549453824), // BPRANT
65 UINT64_C(12582912), // BPRNT
66 UINT64_C(6815744), // BPXCC
67 UINT64_C(543686656), // BPXCCA
68 UINT64_C(543162368), // BPXCCANT
69 UINT64_C(6291456), // BPXCCNT
70 UINT64_C(2175797632), // BSHUFFLE
71 UINT64_C(1073741824), // CALL
72 UINT64_C(1073741824), // CALLi
73 UINT64_C(2680168448), // CALLri
74 UINT64_C(2680168448), // CALLrii
75 UINT64_C(2680160256), // CALLrr
76 UINT64_C(2680160256), // CALLrri
77 UINT64_C(2160591232), // CAMELLIA_F
78 UINT64_C(2175805312), // CAMELLIA_FL
79 UINT64_C(2175805344), // CAMELLIA_FLI
80 UINT64_C(3252690944), // CASAri
81 UINT64_C(3252682752), // CASArr
82 UINT64_C(3253739520), // CASXAri
83 UINT64_C(3253731328), // CASXArr
84 UINT64_C(2175796128), // CMASK16
85 UINT64_C(2175796192), // CMASK32
86 UINT64_C(2175796064), // CMASK8
87 UINT64_C(29360128), // CPBCOND
88 UINT64_C(566231040), // CPBCONDA
89 UINT64_C(2175805664), // CRC32C
90 UINT64_C(281026560), // CWBCONDri
91 UINT64_C(281018368), // CWBCONDrr
92 UINT64_C(283123712), // CXBCONDri
93 UINT64_C(283115520), // CXBCONDrr
94 UINT64_C(2175805088), // DES_IIP
95 UINT64_C(2175805056), // DES_IP
96 UINT64_C(2175805120), // DES_KEXPAND
97 UINT64_C(2160591136), // DES_ROUND
98 UINT64_C(2179989504), // DONE
99 UINT64_C(2175795328), // EDGE16
100 UINT64_C(2175795392), // EDGE16L
101 UINT64_C(2175795424), // EDGE16LN
102 UINT64_C(2175795360), // EDGE16N
103 UINT64_C(2175795456), // EDGE32
104 UINT64_C(2175795520), // EDGE32L
105 UINT64_C(2175795552), // EDGE32LN
106 UINT64_C(2175795488), // EDGE32N
107 UINT64_C(2175795200), // EDGE8
108 UINT64_C(2175795264), // EDGE8L
109 UINT64_C(2175795296), // EDGE8LN
110 UINT64_C(2175795232), // EDGE8N
111 UINT64_C(2174746944), // FABSD
112 UINT64_C(2174746976), // FABSQ
113 UINT64_C(2174746912), // FABSS
114 UINT64_C(2174748736), // FADDD
115 UINT64_C(2174748768), // FADDQ
116 UINT64_C(2174748704), // FADDS
117 UINT64_C(2175797504), // FALIGNADATA
118 UINT64_C(2175798784), // FAND
119 UINT64_C(2175798528), // FANDNOT1
120 UINT64_C(2175798560), // FANDNOT1S
121 UINT64_C(2175798400), // FANDNOT2
122 UINT64_C(2175798432), // FANDNOT2S
123 UINT64_C(2175798816), // FANDS
124 UINT64_C(25165824), // FBCOND
125 UINT64_C(562036736), // FBCONDA
126 UINT64_C(558366720), // FBCONDA_V9
127 UINT64_C(21495808), // FBCOND_V9
128 UINT64_C(2175797376), // FCHKSM16
129 UINT64_C(2175273536), // FCMPD
130 UINT64_C(2175273536), // FCMPD_V9
131 UINT64_C(2175796544), // FCMPEQ16
132 UINT64_C(2175796672), // FCMPEQ32
133 UINT64_C(2175796480), // FCMPGT16
134 UINT64_C(2175796608), // FCMPGT32
135 UINT64_C(2175796224), // FCMPLE16
136 UINT64_C(2175796352), // FCMPLE32
137 UINT64_C(2175796288), // FCMPNE16
138 UINT64_C(2175796416), // FCMPNE32
139 UINT64_C(2175273568), // FCMPQ
140 UINT64_C(2175273568), // FCMPQ_V9
141 UINT64_C(2175273504), // FCMPS
142 UINT64_C(2175273504), // FCMPS_V9
143 UINT64_C(2174749120), // FDIVD
144 UINT64_C(2174749152), // FDIVQ
145 UINT64_C(2174749088), // FDIVS
146 UINT64_C(2174750144), // FDMULQ
147 UINT64_C(2174753344), // FDTOI
148 UINT64_C(2174753216), // FDTOQ
149 UINT64_C(2174752960), // FDTOS
150 UINT64_C(2174750784), // FDTOX
151 UINT64_C(2175797664), // FEXPAND
152 UINT64_C(2174749760), // FHADDD
153 UINT64_C(2174749728), // FHADDS
154 UINT64_C(2174749888), // FHSUBD
155 UINT64_C(2174749856), // FHSUBS
156 UINT64_C(2174753024), // FITOD
157 UINT64_C(2174753152), // FITOQ
158 UINT64_C(2174752896), // FITOS
159 UINT64_C(2175806016), // FLCMPD
160 UINT64_C(2175805984), // FLCMPS
161 UINT64_C(2178416640), // FLUSH
162 UINT64_C(2170028032), // FLUSHW
163 UINT64_C(2178424832), // FLUSHri
164 UINT64_C(2178416640), // FLUSHrr
165 UINT64_C(2176319552), // FMADDD
166 UINT64_C(2176319520), // FMADDS
167 UINT64_C(2175797248), // FMEAN16
168 UINT64_C(2174746688), // FMOVD
169 UINT64_C(2175270976), // FMOVD_FCC
170 UINT64_C(2175279168), // FMOVD_ICC
171 UINT64_C(2175283264), // FMOVD_XCC
172 UINT64_C(2174746720), // FMOVQ
173 UINT64_C(2175271008), // FMOVQ_FCC
174 UINT64_C(2175279200), // FMOVQ_ICC
175 UINT64_C(2175283296), // FMOVQ_XCC
176 UINT64_C(2175271104), // FMOVRD
177 UINT64_C(2175271136), // FMOVRQ
178 UINT64_C(2175271072), // FMOVRS
179 UINT64_C(2174746656), // FMOVS
180 UINT64_C(2175270944), // FMOVS_FCC
181 UINT64_C(2175279136), // FMOVS_ICC
182 UINT64_C(2175283232), // FMOVS_XCC
183 UINT64_C(2176319680), // FMSUBD
184 UINT64_C(2176319648), // FMSUBS
185 UINT64_C(2175796928), // FMUL8SUX16
186 UINT64_C(2175796960), // FMUL8ULX16
187 UINT64_C(2175796768), // FMUL8X16
188 UINT64_C(2175796896), // FMUL8X16AL
189 UINT64_C(2175796832), // FMUL8X16AU
190 UINT64_C(2174748992), // FMULD
191 UINT64_C(2175796992), // FMULD8SUX16
192 UINT64_C(2175797024), // FMULD8ULX16
193 UINT64_C(2174749024), // FMULQ
194 UINT64_C(2174748960), // FMULS
195 UINT64_C(2174749248), // FNADDD
196 UINT64_C(2174749216), // FNADDS
197 UINT64_C(2175798720), // FNAND
198 UINT64_C(2175798752), // FNANDS
199 UINT64_C(2174746816), // FNEGD
200 UINT64_C(2174746848), // FNEGQ
201 UINT64_C(2174746784), // FNEGS
202 UINT64_C(2174750272), // FNHADDD
203 UINT64_C(2174750240), // FNHADDS
204 UINT64_C(2176319936), // FNMADDD
205 UINT64_C(2176319904), // FNMADDS
206 UINT64_C(2176319808), // FNMSUBD
207 UINT64_C(2176319776), // FNMSUBS
208 UINT64_C(2174749504), // FNMULD
209 UINT64_C(2174749472), // FNMULS
210 UINT64_C(2175798336), // FNOR
211 UINT64_C(2175798368), // FNORS
212 UINT64_C(2175798592), // FNOT1
213 UINT64_C(2175798624), // FNOT1S
214 UINT64_C(2175798464), // FNOT2
215 UINT64_C(2175798496), // FNOT2S
216 UINT64_C(2174750496), // FNSMULD
217 UINT64_C(2175799232), // FONE
218 UINT64_C(2175799264), // FONES
219 UINT64_C(2175799168), // FOR
220 UINT64_C(2175799104), // FORNOT1
221 UINT64_C(2175799136), // FORNOT1S
222 UINT64_C(2175798976), // FORNOT2
223 UINT64_C(2175799008), // FORNOT2S
224 UINT64_C(2175799200), // FORS
225 UINT64_C(2175797088), // FPACK16
226 UINT64_C(2175797056), // FPACK32
227 UINT64_C(2175797152), // FPACKFIX
228 UINT64_C(2175797760), // FPADD16
229 UINT64_C(2175797792), // FPADD16S
230 UINT64_C(2175797824), // FPADD32
231 UINT64_C(2175797856), // FPADD32S
232 UINT64_C(2175797312), // FPADD64
233 UINT64_C(2176319488), // FPMADDX
234 UINT64_C(2176319616), // FPMADDXHI
235 UINT64_C(2175797600), // FPMERGE
236 UINT64_C(2175797888), // FPSUB16
237 UINT64_C(2175797920), // FPSUB16S
238 UINT64_C(2175797952), // FPSUB32
239 UINT64_C(2175797984), // FPSUB32S
240 UINT64_C(2174753120), // FQTOD
241 UINT64_C(2174753376), // FQTOI
242 UINT64_C(2174752992), // FQTOS
243 UINT64_C(2174750816), // FQTOX
244 UINT64_C(2175796512), // FSLAS16
245 UINT64_C(2175796640), // FSLAS32
246 UINT64_C(2175796256), // FSLL16
247 UINT64_C(2175796384), // FSLL32
248 UINT64_C(2174749984), // FSMULD
249 UINT64_C(2174747968), // FSQRTD
250 UINT64_C(2174748000), // FSQRTQ
251 UINT64_C(2174747936), // FSQRTS
252 UINT64_C(2175796576), // FSRA16
253 UINT64_C(2175796704), // FSRA32
254 UINT64_C(2175798912), // FSRC1
255 UINT64_C(2175798944), // FSRC1S
256 UINT64_C(2175799040), // FSRC2
257 UINT64_C(2175799072), // FSRC2S
258 UINT64_C(2175796320), // FSRL16
259 UINT64_C(2175796448), // FSRL32
260 UINT64_C(2174753056), // FSTOD
261 UINT64_C(2174753312), // FSTOI
262 UINT64_C(2174753184), // FSTOQ
263 UINT64_C(2174750752), // FSTOX
264 UINT64_C(2174748864), // FSUBD
265 UINT64_C(2174748896), // FSUBQ
266 UINT64_C(2174748832), // FSUBS
267 UINT64_C(2175798848), // FXNOR
268 UINT64_C(2175798880), // FXNORS
269 UINT64_C(2175798656), // FXOR
270 UINT64_C(2175798688), // FXORS
271 UINT64_C(2174750976), // FXTOD
272 UINT64_C(2174751104), // FXTOQ
273 UINT64_C(2174750848), // FXTOS
274 UINT64_C(2175798272), // FZERO
275 UINT64_C(2175798304), // FZEROS
276 UINT64_C(3226992640), // GDOP_LDXrr
277 UINT64_C(3221225472), // GDOP_LDrr
278 UINT64_C(2340945920), // INVALW
279 UINT64_C(2176851968), // JMPLri
280 UINT64_C(2176843776), // JMPLrr
281 UINT64_C(3229622272), // LDAri
282 UINT64_C(3229614080), // LDArr
283 UINT64_C(3246923776), // LDCSRri
284 UINT64_C(3246915584), // LDCSRrr
285 UINT64_C(3246399488), // LDCri
286 UINT64_C(3246391296), // LDCrr
287 UINT64_C(3231195136), // LDDAri
288 UINT64_C(3231186944), // LDDArr
289 UINT64_C(3247972352), // LDDCri
290 UINT64_C(3247964160), // LDDCrr
291 UINT64_C(3247972352), // LDDFAri
292 UINT64_C(3247964160), // LDDFArr
293 UINT64_C(3239583744), // LDDFri
294 UINT64_C(3239575552), // LDDFrr
295 UINT64_C(3222806528), // LDDri
296 UINT64_C(3222798336), // LDDrr
297 UINT64_C(3246399488), // LDFAri
298 UINT64_C(3246391296), // LDFArr
299 UINT64_C(3238535168), // LDFSRri
300 UINT64_C(3238526976), // LDFSRrr
301 UINT64_C(3238010880), // LDFri
302 UINT64_C(3238002688), // LDFrr
303 UINT64_C(3247448064), // LDQFAri
304 UINT64_C(3247439872), // LDQFArr
305 UINT64_C(3239059456), // LDQFri
306 UINT64_C(3239051264), // LDQFrr
307 UINT64_C(3234340864), // LDSBAri
308 UINT64_C(3234332672), // LDSBArr
309 UINT64_C(3225952256), // LDSBri
310 UINT64_C(3225944064), // LDSBrr
311 UINT64_C(3234865152), // LDSHAri
312 UINT64_C(3234856960), // LDSHArr
313 UINT64_C(3226476544), // LDSHri
314 UINT64_C(3226468352), // LDSHrr
315 UINT64_C(3236438016), // LDSTUBAri
316 UINT64_C(3236429824), // LDSTUBArr
317 UINT64_C(3228049408), // LDSTUBri
318 UINT64_C(3228041216), // LDSTUBrr
319 UINT64_C(3233816576), // LDSWAri
320 UINT64_C(3233808384), // LDSWArr
321 UINT64_C(3225427968), // LDSWri
322 UINT64_C(3225419776), // LDSWrr
323 UINT64_C(3230146560), // LDUBAri
324 UINT64_C(3230138368), // LDUBArr
325 UINT64_C(3221757952), // LDUBri
326 UINT64_C(3221749760), // LDUBrr
327 UINT64_C(3230670848), // LDUHAri
328 UINT64_C(3230662656), // LDUHArr
329 UINT64_C(3222282240), // LDUHri
330 UINT64_C(3222274048), // LDUHrr
331 UINT64_C(3235389440), // LDXAri
332 UINT64_C(3235381248), // LDXArr
333 UINT64_C(3272089600), // LDXFSRri
334 UINT64_C(3272081408), // LDXFSRrr
335 UINT64_C(3227000832), // LDXri
336 UINT64_C(3226992640), // LDXrr
337 UINT64_C(3221233664), // LDri
338 UINT64_C(3221225472), // LDrr
339 UINT64_C(2175795936), // LZCNT
340 UINT64_C(2175805440), // MD5
341 UINT64_C(2168709120), // MEMBARi
342 UINT64_C(2175805728), // MONTMUL
343 UINT64_C(2175805760), // MONTSQR
344 UINT64_C(2175803904), // MOVDTOX
345 UINT64_C(2170560512), // MOVFCCri
346 UINT64_C(2170552320), // MOVFCCrr
347 UINT64_C(2170822656), // MOVICCri
348 UINT64_C(2170814464), // MOVICCrr
349 UINT64_C(2172133376), // MOVRri
350 UINT64_C(2172125184), // MOVRrr
351 UINT64_C(2175804000), // MOVSTOSW
352 UINT64_C(2175803936), // MOVSTOUW
353 UINT64_C(2175804192), // MOVWTOS
354 UINT64_C(2170826752), // MOVXCCri
355 UINT64_C(2170818560), // MOVXCCrr
356 UINT64_C(2175804160), // MOVXTOD
357 UINT64_C(2175805696), // MPMUL
358 UINT64_C(2166366208), // MULSCCri
359 UINT64_C(2166358016), // MULSCCrr
360 UINT64_C(2152210432), // MULXri
361 UINT64_C(2152202240), // MULXrr
362 UINT64_C(16777216), // NOP
363 UINT64_C(2307391488), // NORMALW
364 UINT64_C(2156929024), // ORCCri
365 UINT64_C(2156920832), // ORCCrr
366 UINT64_C(2159026176), // ORNCCri
367 UINT64_C(2159017984), // ORNCCrr
368 UINT64_C(2150637568), // ORNri
369 UINT64_C(2150629376), // ORNrr
370 UINT64_C(2148540416), // ORri
371 UINT64_C(2148532224), // ORrr
372 UINT64_C(2273837056), // OTHERW
373 UINT64_C(2175797184), // PDIST
374 UINT64_C(2175797216), // PDISTN
375 UINT64_C(2171600896), // POPCrr
376 UINT64_C(3253215232), // PREFETCHAi
377 UINT64_C(3253207040), // PREFETCHAr
378 UINT64_C(3244826624), // PREFETCHi
379 UINT64_C(3244818432), // PREFETCHr
380 UINT64_C(2206736384), // PWRPSRri
381 UINT64_C(2206728192), // PWRPSRrr
382 UINT64_C(2168455168), // RDASR
383 UINT64_C(2169749504), // RDFQ
384 UINT64_C(2169503744), // RDPR
385 UINT64_C(2168979456), // RDPSR
386 UINT64_C(2170028032), // RDTBR
387 UINT64_C(2169503744), // RDWIM
388 UINT64_C(2206728192), // RESTORED
389 UINT64_C(2179473408), // RESTOREri
390 UINT64_C(2179465216), // RESTORErr
391 UINT64_C(2177359872), // RET
392 UINT64_C(2177097728), // RETL
393 UINT64_C(2213543936), // RETRY
394 UINT64_C(2177376256), // RETTri
395 UINT64_C(2177368064), // RETTrr
396 UINT64_C(2173173760), // SAVED
397 UINT64_C(2178949120), // SAVEri
398 UINT64_C(2178940928), // SAVErr
399 UINT64_C(2163744768), // SDIVCCri
400 UINT64_C(2163736576), // SDIVCCrr
401 UINT64_C(2171084800), // SDIVXri
402 UINT64_C(2171076608), // SDIVXrr
403 UINT64_C(2155356160), // SDIVri
404 UINT64_C(2155347968), // SDIVrr
405 UINT64_C(16777216), // SETHIi
406 UINT64_C(2175805472), // SHA1
407 UINT64_C(2175805504), // SHA256
408 UINT64_C(2175805536), // SHA512
409 UINT64_C(2175799296), // SHUTDOWN
410 UINT64_C(2175799328), // SIAM
411 UINT64_C(2675974144), // SIR
412 UINT64_C(2166894592), // SLLXri
413 UINT64_C(2166886400), // SLLXrr
414 UINT64_C(2166890496), // SLLri
415 UINT64_C(2166882304), // SLLrr
416 UINT64_C(2180521984), // SMACri
417 UINT64_C(2180513792), // SMACrr
418 UINT64_C(2161647616), // SMULCCri
419 UINT64_C(2161639424), // SMULCCrr
420 UINT64_C(2153259008), // SMULri
421 UINT64_C(2153250816), // SMULrr
422 UINT64_C(2167943168), // SRAXri
423 UINT64_C(2167934976), // SRAXrr
424 UINT64_C(2167939072), // SRAri
425 UINT64_C(2167930880), // SRArr
426 UINT64_C(2167418880), // SRLXri
427 UINT64_C(2167410688), // SRLXrr
428 UINT64_C(2167414784), // SRLri
429 UINT64_C(2167406592), // SRLrr
430 UINT64_C(3231719424), // STAri
431 UINT64_C(3231711232), // STArr
432 UINT64_C(2168700928), // STBAR
433 UINT64_C(3232243712), // STBAri
434 UINT64_C(3232235520), // STBArr
435 UINT64_C(3223855104), // STBri
436 UINT64_C(3223846912), // STBrr
437 UINT64_C(3249020928), // STCSRri
438 UINT64_C(3249012736), // STCSRrr
439 UINT64_C(3248496640), // STCri
440 UINT64_C(3248488448), // STCrr
441 UINT64_C(3233292288), // STDAri
442 UINT64_C(3233284096), // STDArr
443 UINT64_C(3249545216), // STDCQri
444 UINT64_C(3249537024), // STDCQrr
445 UINT64_C(3250069504), // STDCri
446 UINT64_C(3250061312), // STDCrr
447 UINT64_C(3250069504), // STDFAri
448 UINT64_C(3250061312), // STDFArr
449 UINT64_C(3241156608), // STDFQri
450 UINT64_C(3241148416), // STDFQrr
451 UINT64_C(3241680896), // STDFri
452 UINT64_C(3241672704), // STDFrr
453 UINT64_C(3224903680), // STDri
454 UINT64_C(3224895488), // STDrr
455 UINT64_C(3248496640), // STFAri
456 UINT64_C(3248488448), // STFArr
457 UINT64_C(3240632320), // STFSRri
458 UINT64_C(3240624128), // STFSRrr
459 UINT64_C(3240108032), // STFri
460 UINT64_C(3240099840), // STFrr
461 UINT64_C(3232768000), // STHAri
462 UINT64_C(3232759808), // STHArr
463 UINT64_C(3224379392), // STHri
464 UINT64_C(3224371200), // STHrr
465 UINT64_C(3249545216), // STQFAri
466 UINT64_C(3249537024), // STQFArr
467 UINT64_C(3241156608), // STQFri
468 UINT64_C(3241148416), // STQFrr
469 UINT64_C(3236962304), // STXAri
470 UINT64_C(3236954112), // STXArr
471 UINT64_C(3274186752), // STXFSRri
472 UINT64_C(3274178560), // STXFSRrr
473 UINT64_C(3228573696), // STXri
474 UINT64_C(3228565504), // STXrr
475 UINT64_C(3223330816), // STri
476 UINT64_C(3223322624), // STrr
477 UINT64_C(2157977600), // SUBCCri
478 UINT64_C(2157969408), // SUBCCrr
479 UINT64_C(2153783296), // SUBCri
480 UINT64_C(2153775104), // SUBCrr
481 UINT64_C(2162171904), // SUBEri
482 UINT64_C(2162163712), // SUBErr
483 UINT64_C(2149588992), // SUBri
484 UINT64_C(2149580800), // SUBrr
485 UINT64_C(3237486592), // SWAPAri
486 UINT64_C(3237478400), // SWAPArr
487 UINT64_C(3229097984), // SWAPri
488 UINT64_C(3229089792), // SWAPrr
489 UINT64_C(2446336001), // TA1
490 UINT64_C(2446336003), // TA3
491 UINT64_C(2446336005), // TA5
492 UINT64_C(2165317632), // TADDCCTVri
493 UINT64_C(2165309440), // TADDCCTVrr
494 UINT64_C(2164269056), // TADDCCri
495 UINT64_C(2164260864), // TADDCCrr
496 UINT64_C(1073741824), // TAIL_CALL
497 UINT64_C(2176851968), // TAIL_CALLri
498 UINT64_C(2177900544), // TICCri
499 UINT64_C(2177892352), // TICCrr
500 UINT64_C(2147483648), // TLS_ADDrr
501 UINT64_C(1073741824), // TLS_CALL
502 UINT64_C(3226992640), // TLS_LDXrr
503 UINT64_C(3221225472), // TLS_LDrr
504 UINT64_C(2177900544), // TRAPri
505 UINT64_C(2177892352), // TRAPrr
506 UINT64_C(2165841920), // TSUBCCTVri
507 UINT64_C(2165833728), // TSUBCCTVrr
508 UINT64_C(2164793344), // TSUBCCri
509 UINT64_C(2164785152), // TSUBCCrr
510 UINT64_C(2177904640), // TXCCri
511 UINT64_C(2177896448), // TXCCrr
512 UINT64_C(2163220480), // UDIVCCri
513 UINT64_C(2163212288), // UDIVCCrr
514 UINT64_C(2154307584), // UDIVXri
515 UINT64_C(2154299392), // UDIVXrr
516 UINT64_C(2154831872), // UDIVri
517 UINT64_C(2154823680), // UDIVrr
518 UINT64_C(2179997696), // UMACri
519 UINT64_C(2179989504), // UMACrr
520 UINT64_C(2161123328), // UMULCCri
521 UINT64_C(2161115136), // UMULCCrr
522 UINT64_C(2175795904), // UMULXHI
523 UINT64_C(2152734720), // UMULri
524 UINT64_C(2152726528), // UMULrr
525 UINT64_C(0), // UNIMP
526 UINT64_C(2175273536), // V9FCMPD
527 UINT64_C(2175273664), // V9FCMPED
528 UINT64_C(2175273696), // V9FCMPEQ
529 UINT64_C(2175273632), // V9FCMPES
530 UINT64_C(2175273568), // V9FCMPQ
531 UINT64_C(2175273504), // V9FCMPS
532 UINT64_C(2175270976), // V9FMOVD_FCC
533 UINT64_C(2175271008), // V9FMOVQ_FCC
534 UINT64_C(2175270944), // V9FMOVS_FCC
535 UINT64_C(2170560512), // V9MOVFCCri
536 UINT64_C(2170552320), // V9MOVFCCrr
537 UINT64_C(2172657664), // WRASRri
538 UINT64_C(2172649472), // WRASRrr
539 UINT64_C(2173706240), // WRPRri
540 UINT64_C(2173698048), // WRPRrr
541 UINT64_C(2173181952), // WRPSRri
542 UINT64_C(2173173760), // WRPSRrr
543 UINT64_C(2174230528), // WRTBRri
544 UINT64_C(2174222336), // WRTBRrr
545 UINT64_C(2173706240), // WRWIMri
546 UINT64_C(2173698048), // WRWIMrr
547 UINT64_C(2175804064), // XMULX
548 UINT64_C(2175804096), // XMULXHI
549 UINT64_C(2159550464), // XNORCCri
550 UINT64_C(2159542272), // XNORCCrr
551 UINT64_C(2151161856), // XNORri
552 UINT64_C(2151153664), // XNORrr
553 UINT64_C(2157453312), // XORCCri
554 UINT64_C(2157445120), // XORCCrr
555 UINT64_C(2149064704), // XORri
556 UINT64_C(2149056512), // XORrr
557 };
558 constexpr unsigned FirstSupportedOpcode = 342;
559
560 const unsigned opcode = MI.getOpcode();
561 if (opcode < FirstSupportedOpcode)
562 reportUnsupportedInst(Inst: MI);
563 unsigned TableIndex = opcode - FirstSupportedOpcode;
564 uint64_t Value = InstBits[TableIndex];
565 uint64_t op = 0;
566 (void)op; // suppress warning
567 switch (opcode) {
568 case SP::ALLCLEAN:
569 case SP::DONE:
570 case SP::FLUSH:
571 case SP::FLUSHW:
572 case SP::INVALW:
573 case SP::MD5:
574 case SP::NOP:
575 case SP::NORMALW:
576 case SP::OTHERW:
577 case SP::RESTORED:
578 case SP::RETRY:
579 case SP::SAVED:
580 case SP::SHA1:
581 case SP::SHA256:
582 case SP::SHA512:
583 case SP::SHUTDOWN:
584 case SP::STBAR:
585 case SP::TA1:
586 case SP::TA3:
587 case SP::TA5: {
588 break;
589 }
590 case SP::BPFCC:
591 case SP::BPFCCA:
592 case SP::BPFCCANT:
593 case SP::BPFCCNT: {
594 // op: cc
595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
596 Value |= (op & 0x3) << 20;
597 // op: cond
598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
599 Value |= (op & 0xf) << 25;
600 // op: imm19
601 op = getBranchPredTargetOpValue(MI, OpNo: 0, Fixups, STI);
602 Value |= (op & 0x7ffff);
603 break;
604 }
605 case SP::BPICC:
606 case SP::BPICCA:
607 case SP::BPICCANT:
608 case SP::BPICCNT:
609 case SP::BPXCC:
610 case SP::BPXCCA:
611 case SP::BPXCCANT:
612 case SP::BPXCCNT:
613 case SP::FBCONDA_V9:
614 case SP::FBCOND_V9: {
615 // op: cond
616 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
617 Value |= (op & 0xf) << 25;
618 // op: imm19
619 op = getBranchPredTargetOpValue(MI, OpNo: 0, Fixups, STI);
620 Value |= (op & 0x7ffff);
621 break;
622 }
623 case SP::CALL:
624 case SP::CALLi:
625 case SP::TAIL_CALL:
626 case SP::TLS_CALL: {
627 // op: disp
628 op = getCallTargetOpValue(MI, OpNo: 0, Fixups, STI);
629 Value |= (op & 0x3fffffff);
630 break;
631 }
632 case SP::CWBCONDrr:
633 case SP::CXBCONDrr: {
634 // op: imm10
635 op = getCompareAndBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
636 Value |= (op & 0x300) << 11;
637 Value |= (op & 0xff) << 5;
638 // op: rs1
639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
640 Value |= (op & 0x1f) << 14;
641 // op: rs2
642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
643 Value |= (op & 0x1f);
644 // op: cond
645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
646 Value |= (op & 0x8) << 26;
647 Value |= (op & 0x7) << 25;
648 break;
649 }
650 case SP::CWBCONDri:
651 case SP::CXBCONDri: {
652 // op: imm10
653 op = getCompareAndBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
654 Value |= (op & 0x300) << 11;
655 Value |= (op & 0xff) << 5;
656 // op: rs1
657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
658 Value |= (op & 0x1f) << 14;
659 // op: simm5
660 op = getSImm5OpValue(MI, OpNo: 3, Fixups, STI);
661 Value |= (op & 0x1f);
662 // op: cond
663 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
664 Value |= (op & 0x8) << 26;
665 Value |= (op & 0x7) << 25;
666 break;
667 }
668 case SP::BPR:
669 case SP::BPRA:
670 case SP::BPRANT:
671 case SP::BPRNT: {
672 // op: imm16
673 op = getBranchOnRegTargetOpValue(MI, OpNo: 0, Fixups, STI);
674 Value |= (op & 0xc000) << 6;
675 Value |= (op & 0x3fff);
676 // op: rs1
677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
678 Value |= (op & 0x1f) << 14;
679 // op: rcond
680 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
681 Value |= (op & 0x7) << 25;
682 break;
683 }
684 case SP::BA: {
685 // op: imm22
686 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
687 Value |= (op & 0x3fffff);
688 break;
689 }
690 case SP::BCOND:
691 case SP::BCONDA:
692 case SP::CPBCOND:
693 case SP::CPBCONDA:
694 case SP::FBCOND:
695 case SP::FBCONDA: {
696 // op: imm22
697 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
698 Value |= (op & 0x3fffff);
699 // op: cond
700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
701 Value |= (op & 0xf) << 25;
702 break;
703 }
704 case SP::UNIMP: {
705 // op: imm22
706 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
707 Value |= (op & 0x3fffff);
708 break;
709 }
710 case SP::SETHIi: {
711 // op: imm22
712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
713 Value |= (op & 0x3fffff);
714 // op: rd
715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
716 Value |= (op & 0x1f) << 25;
717 break;
718 }
719 case SP::SIAM: {
720 // op: mode
721 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
722 Value |= (op & 0x7);
723 break;
724 }
725 case SP::FONE:
726 case SP::FONES:
727 case SP::FZERO:
728 case SP::FZEROS:
729 case SP::RDFQ:
730 case SP::RDPSR:
731 case SP::RDTBR:
732 case SP::RDWIM: {
733 // op: rd
734 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
735 Value |= (op & 0x1f) << 25;
736 break;
737 }
738 case SP::V9MOVFCCrr: {
739 // op: rd
740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
741 Value |= (op & 0x1f) << 25;
742 // op: cc
743 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
744 Value |= (op & 0x3) << 11;
745 // op: cond
746 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
747 Value |= (op & 0xf) << 14;
748 // op: rs2
749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
750 Value |= (op & 0x1f);
751 break;
752 }
753 case SP::V9MOVFCCri: {
754 // op: rd
755 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
756 Value |= (op & 0x1f) << 25;
757 // op: cc
758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
759 Value |= (op & 0x3) << 11;
760 // op: cond
761 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
762 Value |= (op & 0xf) << 14;
763 // op: simm11
764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
765 Value |= (op & 0x7ff);
766 break;
767 }
768 case SP::FMOVD_FCC:
769 case SP::FMOVD_ICC:
770 case SP::FMOVD_XCC:
771 case SP::FMOVQ_FCC:
772 case SP::FMOVQ_ICC:
773 case SP::FMOVQ_XCC:
774 case SP::FMOVS_FCC:
775 case SP::FMOVS_ICC:
776 case SP::FMOVS_XCC:
777 case SP::MOVFCCrr:
778 case SP::MOVICCrr:
779 case SP::MOVXCCrr: {
780 // op: rd
781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
782 Value |= (op & 0x1f) << 25;
783 // op: cond
784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
785 Value |= (op & 0xf) << 14;
786 // op: rs2
787 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
788 Value |= (op & 0x1f);
789 break;
790 }
791 case SP::MOVFCCri:
792 case SP::MOVICCri:
793 case SP::MOVXCCri: {
794 // op: rd
795 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
796 Value |= (op & 0x1f) << 25;
797 // op: cond
798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
799 Value |= (op & 0xf) << 14;
800 // op: simm11
801 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
802 Value |= (op & 0x7ff);
803 break;
804 }
805 case SP::V9FMOVD_FCC:
806 case SP::V9FMOVQ_FCC:
807 case SP::V9FMOVS_FCC: {
808 // op: rd
809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
810 Value |= (op & 0x1f) << 25;
811 // op: cond
812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
813 Value |= (op & 0xf) << 14;
814 // op: opf_cc
815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
816 Value |= (op & 0x3) << 11;
817 // op: rs2
818 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
819 Value |= (op & 0x1f);
820 break;
821 }
822 case SP::DES_IIP:
823 case SP::DES_IP:
824 case SP::FNOT1:
825 case SP::FNOT1S:
826 case SP::FSRC1:
827 case SP::FSRC1S:
828 case SP::RDASR:
829 case SP::RDPR: {
830 // op: rd
831 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
832 Value |= (op & 0x1f) << 25;
833 // op: rs1
834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
835 Value |= (op & 0x1f) << 14;
836 break;
837 }
838 case SP::LDArr:
839 case SP::LDDArr:
840 case SP::LDDFArr:
841 case SP::LDFArr:
842 case SP::LDQFArr:
843 case SP::LDSBArr:
844 case SP::LDSHArr:
845 case SP::LDSTUBArr:
846 case SP::LDSWArr:
847 case SP::LDUBArr:
848 case SP::LDUHArr:
849 case SP::LDXArr:
850 case SP::SWAPArr: {
851 // op: rd
852 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
853 Value |= (op & 0x1f) << 25;
854 // op: rs1
855 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
856 Value |= (op & 0x1f) << 14;
857 // op: asi
858 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
859 Value |= (op & 0xff) << 5;
860 // op: rs2
861 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
862 Value |= (op & 0x1f);
863 break;
864 }
865 case SP::CASArr:
866 case SP::CASXArr: {
867 // op: rd
868 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
869 Value |= (op & 0x1f) << 25;
870 // op: rs1
871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
872 Value |= (op & 0x1f) << 14;
873 // op: asi
874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
875 Value |= (op & 0xff) << 5;
876 // op: rs2
877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
878 Value |= (op & 0x1f);
879 break;
880 }
881 case SP::ADDCCrr:
882 case SP::ADDCrr:
883 case SP::ADDErr:
884 case SP::ADDXC:
885 case SP::ADDXCCC:
886 case SP::ADDrr:
887 case SP::AES_KEXPAND0:
888 case SP::AES_KEXPAND2:
889 case SP::ALIGNADDR:
890 case SP::ALIGNADDRL:
891 case SP::ANDCCrr:
892 case SP::ANDNCCrr:
893 case SP::ANDNrr:
894 case SP::ANDrr:
895 case SP::ARRAY16:
896 case SP::ARRAY32:
897 case SP::ARRAY8:
898 case SP::BMASK:
899 case SP::BSHUFFLE:
900 case SP::CAMELLIA_FL:
901 case SP::CAMELLIA_FLI:
902 case SP::CASAri:
903 case SP::CASXAri:
904 case SP::CRC32C:
905 case SP::EDGE16:
906 case SP::EDGE16L:
907 case SP::EDGE16LN:
908 case SP::EDGE16N:
909 case SP::EDGE32:
910 case SP::EDGE32L:
911 case SP::EDGE32LN:
912 case SP::EDGE32N:
913 case SP::EDGE8:
914 case SP::EDGE8L:
915 case SP::EDGE8LN:
916 case SP::EDGE8N:
917 case SP::FADDD:
918 case SP::FADDQ:
919 case SP::FADDS:
920 case SP::FALIGNADATA:
921 case SP::FAND:
922 case SP::FANDNOT1:
923 case SP::FANDNOT1S:
924 case SP::FANDNOT2:
925 case SP::FANDNOT2S:
926 case SP::FANDS:
927 case SP::FCHKSM16:
928 case SP::FCMPEQ16:
929 case SP::FCMPEQ32:
930 case SP::FCMPGT16:
931 case SP::FCMPGT32:
932 case SP::FCMPLE16:
933 case SP::FCMPLE32:
934 case SP::FCMPNE16:
935 case SP::FCMPNE32:
936 case SP::FDIVD:
937 case SP::FDIVQ:
938 case SP::FDIVS:
939 case SP::FDMULQ:
940 case SP::FHADDD:
941 case SP::FHADDS:
942 case SP::FHSUBD:
943 case SP::FHSUBS:
944 case SP::FLCMPD:
945 case SP::FLCMPS:
946 case SP::FMEAN16:
947 case SP::FMUL8SUX16:
948 case SP::FMUL8ULX16:
949 case SP::FMUL8X16:
950 case SP::FMUL8X16AL:
951 case SP::FMUL8X16AU:
952 case SP::FMULD:
953 case SP::FMULD8SUX16:
954 case SP::FMULD8ULX16:
955 case SP::FMULQ:
956 case SP::FMULS:
957 case SP::FNADDD:
958 case SP::FNADDS:
959 case SP::FNAND:
960 case SP::FNANDS:
961 case SP::FNHADDD:
962 case SP::FNHADDS:
963 case SP::FNMULD:
964 case SP::FNMULS:
965 case SP::FNOR:
966 case SP::FNORS:
967 case SP::FNSMULD:
968 case SP::FOR:
969 case SP::FORNOT1:
970 case SP::FORNOT1S:
971 case SP::FORNOT2:
972 case SP::FORNOT2S:
973 case SP::FORS:
974 case SP::FPACK32:
975 case SP::FPADD16:
976 case SP::FPADD16S:
977 case SP::FPADD32:
978 case SP::FPADD32S:
979 case SP::FPADD64:
980 case SP::FPMERGE:
981 case SP::FPSUB16:
982 case SP::FPSUB16S:
983 case SP::FPSUB32:
984 case SP::FPSUB32S:
985 case SP::FSLAS16:
986 case SP::FSLAS32:
987 case SP::FSLL16:
988 case SP::FSLL32:
989 case SP::FSMULD:
990 case SP::FSRA16:
991 case SP::FSRA32:
992 case SP::FSRL16:
993 case SP::FSRL32:
994 case SP::FSUBD:
995 case SP::FSUBQ:
996 case SP::FSUBS:
997 case SP::FXNOR:
998 case SP::FXNORS:
999 case SP::FXOR:
1000 case SP::FXORS:
1001 case SP::GDOP_LDXrr:
1002 case SP::GDOP_LDrr:
1003 case SP::JMPLrr:
1004 case SP::LDCrr:
1005 case SP::LDDCrr:
1006 case SP::LDDFrr:
1007 case SP::LDDrr:
1008 case SP::LDFrr:
1009 case SP::LDQFrr:
1010 case SP::LDSBrr:
1011 case SP::LDSHrr:
1012 case SP::LDSTUBrr:
1013 case SP::LDSWrr:
1014 case SP::LDUBrr:
1015 case SP::LDUHrr:
1016 case SP::LDXrr:
1017 case SP::LDrr:
1018 case SP::MULSCCrr:
1019 case SP::MULXrr:
1020 case SP::ORCCrr:
1021 case SP::ORNCCrr:
1022 case SP::ORNrr:
1023 case SP::ORrr:
1024 case SP::PDIST:
1025 case SP::PDISTN:
1026 case SP::RESTORErr:
1027 case SP::SAVErr:
1028 case SP::SDIVCCrr:
1029 case SP::SDIVXrr:
1030 case SP::SDIVrr:
1031 case SP::SLLXrr:
1032 case SP::SLLrr:
1033 case SP::SMACrr:
1034 case SP::SMULCCrr:
1035 case SP::SMULrr:
1036 case SP::SRAXrr:
1037 case SP::SRArr:
1038 case SP::SRLXrr:
1039 case SP::SRLrr:
1040 case SP::SUBCCrr:
1041 case SP::SUBCrr:
1042 case SP::SUBErr:
1043 case SP::SUBrr:
1044 case SP::SWAPrr:
1045 case SP::TADDCCTVrr:
1046 case SP::TADDCCrr:
1047 case SP::TLS_ADDrr:
1048 case SP::TLS_LDXrr:
1049 case SP::TLS_LDrr:
1050 case SP::TSUBCCTVrr:
1051 case SP::TSUBCCrr:
1052 case SP::UDIVCCrr:
1053 case SP::UDIVXrr:
1054 case SP::UDIVrr:
1055 case SP::UMACrr:
1056 case SP::UMULCCrr:
1057 case SP::UMULXHI:
1058 case SP::UMULrr:
1059 case SP::V9FCMPD:
1060 case SP::V9FCMPED:
1061 case SP::V9FCMPEQ:
1062 case SP::V9FCMPES:
1063 case SP::V9FCMPQ:
1064 case SP::V9FCMPS:
1065 case SP::WRASRrr:
1066 case SP::WRPRrr:
1067 case SP::XMULX:
1068 case SP::XMULXHI:
1069 case SP::XNORCCrr:
1070 case SP::XNORrr:
1071 case SP::XORCCrr:
1072 case SP::XORrr: {
1073 // op: rd
1074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1075 Value |= (op & 0x1f) << 25;
1076 // op: rs1
1077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1078 Value |= (op & 0x1f) << 14;
1079 // op: rs2
1080 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1081 Value |= (op & 0x1f);
1082 break;
1083 }
1084 case SP::FMOVRD:
1085 case SP::FMOVRQ:
1086 case SP::FMOVRS:
1087 case SP::MOVRrr: {
1088 // op: rd
1089 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1090 Value |= (op & 0x1f) << 25;
1091 // op: rs1
1092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1093 Value |= (op & 0x1f) << 14;
1094 // op: rs2
1095 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1096 Value |= (op & 0x1f);
1097 // op: rcond
1098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1099 Value |= (op & 0x7) << 10;
1100 break;
1101 }
1102 case SP::DES_KEXPAND: {
1103 // op: rd
1104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1105 Value |= (op & 0x1f) << 25;
1106 // op: rs1
1107 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1108 Value |= (op & 0x1f) << 14;
1109 // op: rs2
1110 op = getSImm5OpValue(MI, OpNo: 2, Fixups, STI);
1111 Value |= (op & 0x1f);
1112 break;
1113 }
1114 case SP::AES_DROUND01:
1115 case SP::AES_DROUND01_LAST:
1116 case SP::AES_DROUND23:
1117 case SP::AES_DROUND23_LAST:
1118 case SP::AES_EROUND01:
1119 case SP::AES_EROUND01_LAST:
1120 case SP::AES_EROUND23:
1121 case SP::AES_EROUND23_LAST:
1122 case SP::CAMELLIA_F:
1123 case SP::DES_ROUND:
1124 case SP::FMADDD:
1125 case SP::FMADDS:
1126 case SP::FMSUBD:
1127 case SP::FMSUBS:
1128 case SP::FNMADDD:
1129 case SP::FNMADDS:
1130 case SP::FNMSUBD:
1131 case SP::FNMSUBS:
1132 case SP::FPMADDX:
1133 case SP::FPMADDXHI: {
1134 // op: rd
1135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1136 Value |= (op & 0x1f) << 25;
1137 // op: rs1
1138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1139 Value |= (op & 0x1f) << 14;
1140 // op: rs3
1141 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1142 Value |= (op & 0x1f) << 9;
1143 // op: rs2
1144 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1145 Value |= (op & 0x1f);
1146 break;
1147 }
1148 case SP::AES_KEXPAND1: {
1149 // op: rd
1150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1151 Value |= (op & 0x1f) << 25;
1152 // op: rs1
1153 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1154 Value |= (op & 0x1f) << 14;
1155 // op: rs3
1156 op = getSImm5OpValue(MI, OpNo: 3, Fixups, STI);
1157 Value |= (op & 0x1f) << 9;
1158 // op: rs2
1159 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1160 Value |= (op & 0x1f);
1161 break;
1162 }
1163 case SP::SLLXri:
1164 case SP::SLLri:
1165 case SP::SRAXri:
1166 case SP::SRAri:
1167 case SP::SRLXri:
1168 case SP::SRLri: {
1169 // op: rd
1170 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1171 Value |= (op & 0x1f) << 25;
1172 // op: rs1
1173 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1174 Value |= (op & 0x1f) << 14;
1175 // op: shcnt
1176 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1177 Value |= (op & 0x3f);
1178 break;
1179 }
1180 case SP::MOVRri: {
1181 // op: rd
1182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1183 Value |= (op & 0x1f) << 25;
1184 // op: rs1
1185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1186 Value |= (op & 0x1f) << 14;
1187 // op: simm10
1188 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1189 Value |= (op & 0x3ff);
1190 // op: rcond
1191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1192 Value |= (op & 0x7) << 10;
1193 break;
1194 }
1195 case SP::MULXri:
1196 case SP::SDIVXri:
1197 case SP::UDIVXri: {
1198 // op: rd
1199 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1200 Value |= (op & 0x1f) << 25;
1201 // op: rs1
1202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1203 Value |= (op & 0x1f) << 14;
1204 // op: simm13
1205 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1206 Value |= (op & 0x1fff);
1207 break;
1208 }
1209 case SP::ADDCCri:
1210 case SP::ADDCri:
1211 case SP::ADDEri:
1212 case SP::ADDri:
1213 case SP::ANDCCri:
1214 case SP::ANDNCCri:
1215 case SP::ANDNri:
1216 case SP::ANDri:
1217 case SP::JMPLri:
1218 case SP::LDAri:
1219 case SP::LDCri:
1220 case SP::LDDAri:
1221 case SP::LDDCri:
1222 case SP::LDDFAri:
1223 case SP::LDDFri:
1224 case SP::LDDri:
1225 case SP::LDFAri:
1226 case SP::LDFri:
1227 case SP::LDQFAri:
1228 case SP::LDQFri:
1229 case SP::LDSBAri:
1230 case SP::LDSBri:
1231 case SP::LDSHAri:
1232 case SP::LDSHri:
1233 case SP::LDSTUBAri:
1234 case SP::LDSTUBri:
1235 case SP::LDSWAri:
1236 case SP::LDSWri:
1237 case SP::LDUBAri:
1238 case SP::LDUBri:
1239 case SP::LDUHAri:
1240 case SP::LDUHri:
1241 case SP::LDXAri:
1242 case SP::LDXri:
1243 case SP::LDri:
1244 case SP::MULSCCri:
1245 case SP::ORCCri:
1246 case SP::ORNCCri:
1247 case SP::ORNri:
1248 case SP::ORri:
1249 case SP::RESTOREri:
1250 case SP::SAVEri:
1251 case SP::SDIVCCri:
1252 case SP::SDIVri:
1253 case SP::SMACri:
1254 case SP::SMULCCri:
1255 case SP::SMULri:
1256 case SP::SUBCCri:
1257 case SP::SUBCri:
1258 case SP::SUBEri:
1259 case SP::SUBri:
1260 case SP::SWAPAri:
1261 case SP::SWAPri:
1262 case SP::TADDCCTVri:
1263 case SP::TADDCCri:
1264 case SP::TSUBCCTVri:
1265 case SP::TSUBCCri:
1266 case SP::UDIVCCri:
1267 case SP::UDIVri:
1268 case SP::UMACri:
1269 case SP::UMULCCri:
1270 case SP::UMULri:
1271 case SP::WRASRri:
1272 case SP::WRPRri:
1273 case SP::XNORCCri:
1274 case SP::XNORri:
1275 case SP::XORCCri:
1276 case SP::XORri: {
1277 // op: rd
1278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1279 Value |= (op & 0x1f) << 25;
1280 // op: rs1
1281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1282 Value |= (op & 0x1f) << 14;
1283 // op: simm13
1284 op = getSImm13OpValue(MI, OpNo: 2, Fixups, STI);
1285 Value |= (op & 0x1fff);
1286 break;
1287 }
1288 case SP::FABSD:
1289 case SP::FABSQ:
1290 case SP::FABSS:
1291 case SP::FDTOI:
1292 case SP::FDTOQ:
1293 case SP::FDTOS:
1294 case SP::FDTOX:
1295 case SP::FEXPAND:
1296 case SP::FITOD:
1297 case SP::FITOQ:
1298 case SP::FITOS:
1299 case SP::FMOVD:
1300 case SP::FMOVQ:
1301 case SP::FMOVS:
1302 case SP::FNEGD:
1303 case SP::FNEGQ:
1304 case SP::FNEGS:
1305 case SP::FNOT2:
1306 case SP::FNOT2S:
1307 case SP::FPACK16:
1308 case SP::FPACKFIX:
1309 case SP::FQTOD:
1310 case SP::FQTOI:
1311 case SP::FQTOS:
1312 case SP::FQTOX:
1313 case SP::FSQRTD:
1314 case SP::FSQRTQ:
1315 case SP::FSQRTS:
1316 case SP::FSRC2:
1317 case SP::FSRC2S:
1318 case SP::FSTOD:
1319 case SP::FSTOI:
1320 case SP::FSTOQ:
1321 case SP::FSTOX:
1322 case SP::FXTOD:
1323 case SP::FXTOQ:
1324 case SP::FXTOS:
1325 case SP::LZCNT:
1326 case SP::MOVDTOX:
1327 case SP::MOVSTOSW:
1328 case SP::MOVSTOUW:
1329 case SP::MOVWTOS:
1330 case SP::MOVXTOD:
1331 case SP::POPCrr: {
1332 // op: rd
1333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1334 Value |= (op & 0x1f) << 25;
1335 // op: rs2
1336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1337 Value |= (op & 0x1f);
1338 break;
1339 }
1340 case SP::STArr:
1341 case SP::STBArr:
1342 case SP::STDArr:
1343 case SP::STDFArr:
1344 case SP::STFArr:
1345 case SP::STHArr:
1346 case SP::STQFArr:
1347 case SP::STXArr: {
1348 // op: rd
1349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1350 Value |= (op & 0x1f) << 25;
1351 // op: rs1
1352 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1353 Value |= (op & 0x1f) << 14;
1354 // op: asi
1355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1356 Value |= (op & 0xff) << 5;
1357 // op: rs2
1358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1359 Value |= (op & 0x1f);
1360 break;
1361 }
1362 case SP::PREFETCHr:
1363 case SP::STBrr:
1364 case SP::STCrr:
1365 case SP::STDCrr:
1366 case SP::STDFrr:
1367 case SP::STDrr:
1368 case SP::STFrr:
1369 case SP::STHrr:
1370 case SP::STQFrr:
1371 case SP::STXrr:
1372 case SP::STrr: {
1373 // op: rd
1374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1375 Value |= (op & 0x1f) << 25;
1376 // op: rs1
1377 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1378 Value |= (op & 0x1f) << 14;
1379 // op: rs2
1380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1381 Value |= (op & 0x1f);
1382 break;
1383 }
1384 case SP::PREFETCHAi:
1385 case SP::PREFETCHi:
1386 case SP::STAri:
1387 case SP::STBAri:
1388 case SP::STBri:
1389 case SP::STCri:
1390 case SP::STDAri:
1391 case SP::STDCri:
1392 case SP::STDFAri:
1393 case SP::STDFri:
1394 case SP::STDri:
1395 case SP::STFAri:
1396 case SP::STFri:
1397 case SP::STHAri:
1398 case SP::STHri:
1399 case SP::STQFAri:
1400 case SP::STQFri:
1401 case SP::STXAri:
1402 case SP::STXri:
1403 case SP::STri: {
1404 // op: rd
1405 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1406 Value |= (op & 0x1f) << 25;
1407 // op: rs1
1408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1409 Value |= (op & 0x1f) << 14;
1410 // op: simm13
1411 op = getSImm13OpValue(MI, OpNo: 1, Fixups, STI);
1412 Value |= (op & 0x1fff);
1413 break;
1414 }
1415 case SP::PREFETCHAr: {
1416 // op: rd
1417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1418 Value |= (op & 0x1f) << 25;
1419 // op: rs1
1420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1421 Value |= (op & 0x1f) << 14;
1422 // op: asi
1423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1424 Value |= (op & 0xff) << 5;
1425 // op: rs2
1426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1427 Value |= (op & 0x1f);
1428 break;
1429 }
1430 case SP::TICCri:
1431 case SP::TRAPri:
1432 case SP::TXCCri: {
1433 // op: rs1
1434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1435 Value |= (op & 0x1f) << 14;
1436 // op: cond
1437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1438 Value |= (op & 0xf) << 25;
1439 // op: imm
1440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1441 Value |= (op & 0xff);
1442 break;
1443 }
1444 case SP::TICCrr:
1445 case SP::TRAPrr:
1446 case SP::TXCCrr: {
1447 // op: rs1
1448 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1449 Value |= (op & 0x1f) << 14;
1450 // op: cond
1451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1452 Value |= (op & 0xf) << 25;
1453 // op: rs2
1454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1455 Value |= (op & 0x1f);
1456 break;
1457 }
1458 case SP::BINDrr:
1459 case SP::CALLrr:
1460 case SP::CALLrri:
1461 case SP::FCMPD:
1462 case SP::FCMPD_V9:
1463 case SP::FCMPQ:
1464 case SP::FCMPQ_V9:
1465 case SP::FCMPS:
1466 case SP::FCMPS_V9:
1467 case SP::FLUSHrr:
1468 case SP::LDCSRrr:
1469 case SP::LDFSRrr:
1470 case SP::LDXFSRrr:
1471 case SP::PWRPSRrr:
1472 case SP::RETTrr:
1473 case SP::STCSRrr:
1474 case SP::STDCQrr:
1475 case SP::STDFQrr:
1476 case SP::STFSRrr:
1477 case SP::STXFSRrr:
1478 case SP::WRPSRrr:
1479 case SP::WRTBRrr:
1480 case SP::WRWIMrr: {
1481 // op: rs1
1482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1483 Value |= (op & 0x1f) << 14;
1484 // op: rs2
1485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1486 Value |= (op & 0x1f);
1487 break;
1488 }
1489 case SP::BINDri:
1490 case SP::CALLri:
1491 case SP::CALLrii:
1492 case SP::FLUSHri:
1493 case SP::LDCSRri:
1494 case SP::LDFSRri:
1495 case SP::LDXFSRri:
1496 case SP::PWRPSRri:
1497 case SP::RETTri:
1498 case SP::STCSRri:
1499 case SP::STDCQri:
1500 case SP::STDFQri:
1501 case SP::STFSRri:
1502 case SP::STXFSRri:
1503 case SP::TAIL_CALLri:
1504 case SP::WRPSRri:
1505 case SP::WRTBRri:
1506 case SP::WRWIMri: {
1507 // op: rs1
1508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1509 Value |= (op & 0x1f) << 14;
1510 // op: simm13
1511 op = getSImm13OpValue(MI, OpNo: 1, Fixups, STI);
1512 Value |= (op & 0x1fff);
1513 break;
1514 }
1515 case SP::CMASK16:
1516 case SP::CMASK32:
1517 case SP::CMASK8: {
1518 // op: rs2
1519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1520 Value |= (op & 0x1f);
1521 break;
1522 }
1523 case SP::MONTMUL:
1524 case SP::MONTSQR:
1525 case SP::MPMUL: {
1526 // op: rs2
1527 op = getSImm5OpValue(MI, OpNo: 0, Fixups, STI);
1528 Value |= (op & 0x1f);
1529 break;
1530 }
1531 case SP::MEMBARi:
1532 case SP::RET:
1533 case SP::RETL: {
1534 // op: simm13
1535 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1536 Value |= (op & 0x1fff);
1537 break;
1538 }
1539 case SP::SIR: {
1540 // op: simm13
1541 op = getSImm13OpValue(MI, OpNo: 0, Fixups, STI);
1542 Value |= (op & 0x1fff);
1543 break;
1544 }
1545 default:
1546 reportUnsupportedInst(Inst: MI);
1547 }
1548 return Value;
1549}
1550
1551#ifdef GET_OPERAND_BIT_OFFSET
1552#undef GET_OPERAND_BIT_OFFSET
1553
1554uint32_t SparcMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
1555 unsigned OpNum,
1556 const MCSubtargetInfo &STI) const {
1557 switch (MI.getOpcode()) {
1558 case SP::ALLCLEAN:
1559 case SP::DONE:
1560 case SP::FLUSH:
1561 case SP::FLUSHW:
1562 case SP::INVALW:
1563 case SP::MD5:
1564 case SP::NOP:
1565 case SP::NORMALW:
1566 case SP::OTHERW:
1567 case SP::RESTORED:
1568 case SP::RETRY:
1569 case SP::SAVED:
1570 case SP::SHA1:
1571 case SP::SHA256:
1572 case SP::SHA512:
1573 case SP::SHUTDOWN:
1574 case SP::STBAR:
1575 case SP::TA1:
1576 case SP::TA3:
1577 case SP::TA5: {
1578 break;
1579 }
1580 case SP::CALL:
1581 case SP::CALLi:
1582 case SP::TAIL_CALL:
1583 case SP::TLS_CALL: {
1584 switch (OpNum) {
1585 case 0:
1586 // op: disp
1587 return 0;
1588 }
1589 break;
1590 }
1591 case SP::CWBCONDrr:
1592 case SP::CXBCONDrr: {
1593 switch (OpNum) {
1594 case 0:
1595 // op: imm10
1596 return 5;
1597 case 2:
1598 // op: rs1
1599 return 14;
1600 case 3:
1601 // op: rs2
1602 return 0;
1603 case 1:
1604 // op: cond
1605 return 25;
1606 }
1607 break;
1608 }
1609 case SP::CWBCONDri:
1610 case SP::CXBCONDri: {
1611 switch (OpNum) {
1612 case 0:
1613 // op: imm10
1614 return 5;
1615 case 2:
1616 // op: rs1
1617 return 14;
1618 case 3:
1619 // op: simm5
1620 return 0;
1621 case 1:
1622 // op: cond
1623 return 25;
1624 }
1625 break;
1626 }
1627 case SP::BPR:
1628 case SP::BPRA:
1629 case SP::BPRANT:
1630 case SP::BPRNT: {
1631 switch (OpNum) {
1632 case 0:
1633 // op: imm16
1634 return 0;
1635 case 2:
1636 // op: rs1
1637 return 14;
1638 case 1:
1639 // op: rcond
1640 return 25;
1641 }
1642 break;
1643 }
1644 case SP::BCOND:
1645 case SP::BCONDA:
1646 case SP::CPBCOND:
1647 case SP::CPBCONDA:
1648 case SP::FBCOND:
1649 case SP::FBCONDA: {
1650 switch (OpNum) {
1651 case 0:
1652 // op: imm22
1653 return 0;
1654 case 1:
1655 // op: cond
1656 return 25;
1657 }
1658 break;
1659 }
1660 case SP::BA:
1661 case SP::UNIMP: {
1662 switch (OpNum) {
1663 case 0:
1664 // op: imm22
1665 return 0;
1666 }
1667 break;
1668 }
1669 case SP::SIAM: {
1670 switch (OpNum) {
1671 case 0:
1672 // op: mode
1673 return 0;
1674 }
1675 break;
1676 }
1677 case SP::V9MOVFCCrr: {
1678 switch (OpNum) {
1679 case 0:
1680 // op: rd
1681 return 25;
1682 case 1:
1683 // op: cc
1684 return 11;
1685 case 4:
1686 // op: cond
1687 return 14;
1688 case 2:
1689 // op: rs2
1690 return 0;
1691 }
1692 break;
1693 }
1694 case SP::V9MOVFCCri: {
1695 switch (OpNum) {
1696 case 0:
1697 // op: rd
1698 return 25;
1699 case 1:
1700 // op: cc
1701 return 11;
1702 case 4:
1703 // op: cond
1704 return 14;
1705 case 2:
1706 // op: simm11
1707 return 0;
1708 }
1709 break;
1710 }
1711 case SP::FMOVRD:
1712 case SP::FMOVRQ:
1713 case SP::FMOVRS:
1714 case SP::MOVRrr: {
1715 switch (OpNum) {
1716 case 0:
1717 // op: rd
1718 return 25;
1719 case 1:
1720 // op: rs1
1721 return 14;
1722 case 2:
1723 // op: rs2
1724 return 0;
1725 case 4:
1726 // op: rcond
1727 return 10;
1728 }
1729 break;
1730 }
1731 case SP::ADDCCrr:
1732 case SP::ADDCrr:
1733 case SP::ADDErr:
1734 case SP::ADDXC:
1735 case SP::ADDXCCC:
1736 case SP::ADDrr:
1737 case SP::AES_KEXPAND0:
1738 case SP::AES_KEXPAND2:
1739 case SP::ALIGNADDR:
1740 case SP::ALIGNADDRL:
1741 case SP::ANDCCrr:
1742 case SP::ANDNCCrr:
1743 case SP::ANDNrr:
1744 case SP::ANDrr:
1745 case SP::ARRAY16:
1746 case SP::ARRAY32:
1747 case SP::ARRAY8:
1748 case SP::BMASK:
1749 case SP::BSHUFFLE:
1750 case SP::CAMELLIA_FL:
1751 case SP::CAMELLIA_FLI:
1752 case SP::CASAri:
1753 case SP::CASXAri:
1754 case SP::CRC32C:
1755 case SP::DES_KEXPAND:
1756 case SP::EDGE16:
1757 case SP::EDGE16L:
1758 case SP::EDGE16LN:
1759 case SP::EDGE16N:
1760 case SP::EDGE32:
1761 case SP::EDGE32L:
1762 case SP::EDGE32LN:
1763 case SP::EDGE32N:
1764 case SP::EDGE8:
1765 case SP::EDGE8L:
1766 case SP::EDGE8LN:
1767 case SP::EDGE8N:
1768 case SP::FADDD:
1769 case SP::FADDQ:
1770 case SP::FADDS:
1771 case SP::FALIGNADATA:
1772 case SP::FAND:
1773 case SP::FANDNOT1:
1774 case SP::FANDNOT1S:
1775 case SP::FANDNOT2:
1776 case SP::FANDNOT2S:
1777 case SP::FANDS:
1778 case SP::FCHKSM16:
1779 case SP::FCMPEQ16:
1780 case SP::FCMPEQ32:
1781 case SP::FCMPGT16:
1782 case SP::FCMPGT32:
1783 case SP::FCMPLE16:
1784 case SP::FCMPLE32:
1785 case SP::FCMPNE16:
1786 case SP::FCMPNE32:
1787 case SP::FDIVD:
1788 case SP::FDIVQ:
1789 case SP::FDIVS:
1790 case SP::FDMULQ:
1791 case SP::FHADDD:
1792 case SP::FHADDS:
1793 case SP::FHSUBD:
1794 case SP::FHSUBS:
1795 case SP::FLCMPD:
1796 case SP::FLCMPS:
1797 case SP::FMEAN16:
1798 case SP::FMUL8SUX16:
1799 case SP::FMUL8ULX16:
1800 case SP::FMUL8X16:
1801 case SP::FMUL8X16AL:
1802 case SP::FMUL8X16AU:
1803 case SP::FMULD:
1804 case SP::FMULD8SUX16:
1805 case SP::FMULD8ULX16:
1806 case SP::FMULQ:
1807 case SP::FMULS:
1808 case SP::FNADDD:
1809 case SP::FNADDS:
1810 case SP::FNAND:
1811 case SP::FNANDS:
1812 case SP::FNHADDD:
1813 case SP::FNHADDS:
1814 case SP::FNMULD:
1815 case SP::FNMULS:
1816 case SP::FNOR:
1817 case SP::FNORS:
1818 case SP::FNSMULD:
1819 case SP::FOR:
1820 case SP::FORNOT1:
1821 case SP::FORNOT1S:
1822 case SP::FORNOT2:
1823 case SP::FORNOT2S:
1824 case SP::FORS:
1825 case SP::FPACK32:
1826 case SP::FPADD16:
1827 case SP::FPADD16S:
1828 case SP::FPADD32:
1829 case SP::FPADD32S:
1830 case SP::FPADD64:
1831 case SP::FPMERGE:
1832 case SP::FPSUB16:
1833 case SP::FPSUB16S:
1834 case SP::FPSUB32:
1835 case SP::FPSUB32S:
1836 case SP::FSLAS16:
1837 case SP::FSLAS32:
1838 case SP::FSLL16:
1839 case SP::FSLL32:
1840 case SP::FSMULD:
1841 case SP::FSRA16:
1842 case SP::FSRA32:
1843 case SP::FSRL16:
1844 case SP::FSRL32:
1845 case SP::FSUBD:
1846 case SP::FSUBQ:
1847 case SP::FSUBS:
1848 case SP::FXNOR:
1849 case SP::FXNORS:
1850 case SP::FXOR:
1851 case SP::FXORS:
1852 case SP::GDOP_LDXrr:
1853 case SP::GDOP_LDrr:
1854 case SP::JMPLrr:
1855 case SP::LDCrr:
1856 case SP::LDDCrr:
1857 case SP::LDDFrr:
1858 case SP::LDDrr:
1859 case SP::LDFrr:
1860 case SP::LDQFrr:
1861 case SP::LDSBrr:
1862 case SP::LDSHrr:
1863 case SP::LDSTUBrr:
1864 case SP::LDSWrr:
1865 case SP::LDUBrr:
1866 case SP::LDUHrr:
1867 case SP::LDXrr:
1868 case SP::LDrr:
1869 case SP::MULSCCrr:
1870 case SP::MULXrr:
1871 case SP::ORCCrr:
1872 case SP::ORNCCrr:
1873 case SP::ORNrr:
1874 case SP::ORrr:
1875 case SP::PDIST:
1876 case SP::PDISTN:
1877 case SP::RESTORErr:
1878 case SP::SAVErr:
1879 case SP::SDIVCCrr:
1880 case SP::SDIVXrr:
1881 case SP::SDIVrr:
1882 case SP::SLLXrr:
1883 case SP::SLLrr:
1884 case SP::SMACrr:
1885 case SP::SMULCCrr:
1886 case SP::SMULrr:
1887 case SP::SRAXrr:
1888 case SP::SRArr:
1889 case SP::SRLXrr:
1890 case SP::SRLrr:
1891 case SP::SUBCCrr:
1892 case SP::SUBCrr:
1893 case SP::SUBErr:
1894 case SP::SUBrr:
1895 case SP::SWAPrr:
1896 case SP::TADDCCTVrr:
1897 case SP::TADDCCrr:
1898 case SP::TLS_ADDrr:
1899 case SP::TLS_LDXrr:
1900 case SP::TLS_LDrr:
1901 case SP::TSUBCCTVrr:
1902 case SP::TSUBCCrr:
1903 case SP::UDIVCCrr:
1904 case SP::UDIVXrr:
1905 case SP::UDIVrr:
1906 case SP::UMACrr:
1907 case SP::UMULCCrr:
1908 case SP::UMULXHI:
1909 case SP::UMULrr:
1910 case SP::V9FCMPD:
1911 case SP::V9FCMPED:
1912 case SP::V9FCMPEQ:
1913 case SP::V9FCMPES:
1914 case SP::V9FCMPQ:
1915 case SP::V9FCMPS:
1916 case SP::WRASRrr:
1917 case SP::WRPRrr:
1918 case SP::XMULX:
1919 case SP::XMULXHI:
1920 case SP::XNORCCrr:
1921 case SP::XNORrr:
1922 case SP::XORCCrr:
1923 case SP::XORrr: {
1924 switch (OpNum) {
1925 case 0:
1926 // op: rd
1927 return 25;
1928 case 1:
1929 // op: rs1
1930 return 14;
1931 case 2:
1932 // op: rs2
1933 return 0;
1934 }
1935 break;
1936 }
1937 case SP::SLLXri:
1938 case SP::SLLri:
1939 case SP::SRAXri:
1940 case SP::SRAri:
1941 case SP::SRLXri:
1942 case SP::SRLri: {
1943 switch (OpNum) {
1944 case 0:
1945 // op: rd
1946 return 25;
1947 case 1:
1948 // op: rs1
1949 return 14;
1950 case 2:
1951 // op: shcnt
1952 return 0;
1953 }
1954 break;
1955 }
1956 case SP::MOVRri: {
1957 switch (OpNum) {
1958 case 0:
1959 // op: rd
1960 return 25;
1961 case 1:
1962 // op: rs1
1963 return 14;
1964 case 2:
1965 // op: simm10
1966 return 0;
1967 case 4:
1968 // op: rcond
1969 return 10;
1970 }
1971 break;
1972 }
1973 case SP::ADDCCri:
1974 case SP::ADDCri:
1975 case SP::ADDEri:
1976 case SP::ADDri:
1977 case SP::ANDCCri:
1978 case SP::ANDNCCri:
1979 case SP::ANDNri:
1980 case SP::ANDri:
1981 case SP::JMPLri:
1982 case SP::LDAri:
1983 case SP::LDCri:
1984 case SP::LDDAri:
1985 case SP::LDDCri:
1986 case SP::LDDFAri:
1987 case SP::LDDFri:
1988 case SP::LDDri:
1989 case SP::LDFAri:
1990 case SP::LDFri:
1991 case SP::LDQFAri:
1992 case SP::LDQFri:
1993 case SP::LDSBAri:
1994 case SP::LDSBri:
1995 case SP::LDSHAri:
1996 case SP::LDSHri:
1997 case SP::LDSTUBAri:
1998 case SP::LDSTUBri:
1999 case SP::LDSWAri:
2000 case SP::LDSWri:
2001 case SP::LDUBAri:
2002 case SP::LDUBri:
2003 case SP::LDUHAri:
2004 case SP::LDUHri:
2005 case SP::LDXAri:
2006 case SP::LDXri:
2007 case SP::LDri:
2008 case SP::MULSCCri:
2009 case SP::MULXri:
2010 case SP::ORCCri:
2011 case SP::ORNCCri:
2012 case SP::ORNri:
2013 case SP::ORri:
2014 case SP::RESTOREri:
2015 case SP::SAVEri:
2016 case SP::SDIVCCri:
2017 case SP::SDIVXri:
2018 case SP::SDIVri:
2019 case SP::SMACri:
2020 case SP::SMULCCri:
2021 case SP::SMULri:
2022 case SP::SUBCCri:
2023 case SP::SUBCri:
2024 case SP::SUBEri:
2025 case SP::SUBri:
2026 case SP::SWAPAri:
2027 case SP::SWAPri:
2028 case SP::TADDCCTVri:
2029 case SP::TADDCCri:
2030 case SP::TSUBCCTVri:
2031 case SP::TSUBCCri:
2032 case SP::UDIVCCri:
2033 case SP::UDIVXri:
2034 case SP::UDIVri:
2035 case SP::UMACri:
2036 case SP::UMULCCri:
2037 case SP::UMULri:
2038 case SP::WRASRri:
2039 case SP::WRPRri:
2040 case SP::XNORCCri:
2041 case SP::XNORri:
2042 case SP::XORCCri:
2043 case SP::XORri: {
2044 switch (OpNum) {
2045 case 0:
2046 // op: rd
2047 return 25;
2048 case 1:
2049 // op: rs1
2050 return 14;
2051 case 2:
2052 // op: simm13
2053 return 0;
2054 }
2055 break;
2056 }
2057 case SP::LDArr:
2058 case SP::LDDArr:
2059 case SP::LDDFArr:
2060 case SP::LDFArr:
2061 case SP::LDQFArr:
2062 case SP::LDSBArr:
2063 case SP::LDSHArr:
2064 case SP::LDSTUBArr:
2065 case SP::LDSWArr:
2066 case SP::LDUBArr:
2067 case SP::LDUHArr:
2068 case SP::LDXArr:
2069 case SP::SWAPArr: {
2070 switch (OpNum) {
2071 case 0:
2072 // op: rd
2073 return 25;
2074 case 1:
2075 // op: rs1
2076 return 14;
2077 case 3:
2078 // op: asi
2079 return 5;
2080 case 2:
2081 // op: rs2
2082 return 0;
2083 }
2084 break;
2085 }
2086 case SP::AES_DROUND01:
2087 case SP::AES_DROUND01_LAST:
2088 case SP::AES_DROUND23:
2089 case SP::AES_DROUND23_LAST:
2090 case SP::AES_EROUND01:
2091 case SP::AES_EROUND01_LAST:
2092 case SP::AES_EROUND23:
2093 case SP::AES_EROUND23_LAST:
2094 case SP::AES_KEXPAND1:
2095 case SP::CAMELLIA_F:
2096 case SP::DES_ROUND:
2097 case SP::FMADDD:
2098 case SP::FMADDS:
2099 case SP::FMSUBD:
2100 case SP::FMSUBS:
2101 case SP::FNMADDD:
2102 case SP::FNMADDS:
2103 case SP::FNMSUBD:
2104 case SP::FNMSUBS:
2105 case SP::FPMADDX:
2106 case SP::FPMADDXHI: {
2107 switch (OpNum) {
2108 case 0:
2109 // op: rd
2110 return 25;
2111 case 1:
2112 // op: rs1
2113 return 14;
2114 case 3:
2115 // op: rs3
2116 return 9;
2117 case 2:
2118 // op: rs2
2119 return 0;
2120 }
2121 break;
2122 }
2123 case SP::CASArr:
2124 case SP::CASXArr: {
2125 switch (OpNum) {
2126 case 0:
2127 // op: rd
2128 return 25;
2129 case 1:
2130 // op: rs1
2131 return 14;
2132 case 4:
2133 // op: asi
2134 return 5;
2135 case 2:
2136 // op: rs2
2137 return 0;
2138 }
2139 break;
2140 }
2141 case SP::DES_IIP:
2142 case SP::DES_IP:
2143 case SP::FNOT1:
2144 case SP::FNOT1S:
2145 case SP::FSRC1:
2146 case SP::FSRC1S:
2147 case SP::RDASR:
2148 case SP::RDPR: {
2149 switch (OpNum) {
2150 case 0:
2151 // op: rd
2152 return 25;
2153 case 1:
2154 // op: rs1
2155 return 14;
2156 }
2157 break;
2158 }
2159 case SP::FABSD:
2160 case SP::FABSQ:
2161 case SP::FABSS:
2162 case SP::FDTOI:
2163 case SP::FDTOQ:
2164 case SP::FDTOS:
2165 case SP::FDTOX:
2166 case SP::FEXPAND:
2167 case SP::FITOD:
2168 case SP::FITOQ:
2169 case SP::FITOS:
2170 case SP::FMOVD:
2171 case SP::FMOVQ:
2172 case SP::FMOVS:
2173 case SP::FNEGD:
2174 case SP::FNEGQ:
2175 case SP::FNEGS:
2176 case SP::FNOT2:
2177 case SP::FNOT2S:
2178 case SP::FPACK16:
2179 case SP::FPACKFIX:
2180 case SP::FQTOD:
2181 case SP::FQTOI:
2182 case SP::FQTOS:
2183 case SP::FQTOX:
2184 case SP::FSQRTD:
2185 case SP::FSQRTQ:
2186 case SP::FSQRTS:
2187 case SP::FSRC2:
2188 case SP::FSRC2S:
2189 case SP::FSTOD:
2190 case SP::FSTOI:
2191 case SP::FSTOQ:
2192 case SP::FSTOX:
2193 case SP::FXTOD:
2194 case SP::FXTOQ:
2195 case SP::FXTOS:
2196 case SP::LZCNT:
2197 case SP::MOVDTOX:
2198 case SP::MOVSTOSW:
2199 case SP::MOVSTOUW:
2200 case SP::MOVWTOS:
2201 case SP::MOVXTOD:
2202 case SP::POPCrr: {
2203 switch (OpNum) {
2204 case 0:
2205 // op: rd
2206 return 25;
2207 case 1:
2208 // op: rs2
2209 return 0;
2210 }
2211 break;
2212 }
2213 case SP::FMOVD_FCC:
2214 case SP::FMOVD_ICC:
2215 case SP::FMOVD_XCC:
2216 case SP::FMOVQ_FCC:
2217 case SP::FMOVQ_ICC:
2218 case SP::FMOVQ_XCC:
2219 case SP::FMOVS_FCC:
2220 case SP::FMOVS_ICC:
2221 case SP::FMOVS_XCC:
2222 case SP::MOVFCCrr:
2223 case SP::MOVICCrr:
2224 case SP::MOVXCCrr: {
2225 switch (OpNum) {
2226 case 0:
2227 // op: rd
2228 return 25;
2229 case 3:
2230 // op: cond
2231 return 14;
2232 case 1:
2233 // op: rs2
2234 return 0;
2235 }
2236 break;
2237 }
2238 case SP::MOVFCCri:
2239 case SP::MOVICCri:
2240 case SP::MOVXCCri: {
2241 switch (OpNum) {
2242 case 0:
2243 // op: rd
2244 return 25;
2245 case 3:
2246 // op: cond
2247 return 14;
2248 case 1:
2249 // op: simm11
2250 return 0;
2251 }
2252 break;
2253 }
2254 case SP::V9FMOVD_FCC:
2255 case SP::V9FMOVQ_FCC:
2256 case SP::V9FMOVS_FCC: {
2257 switch (OpNum) {
2258 case 0:
2259 // op: rd
2260 return 25;
2261 case 4:
2262 // op: cond
2263 return 14;
2264 case 1:
2265 // op: opf_cc
2266 return 11;
2267 case 2:
2268 // op: rs2
2269 return 0;
2270 }
2271 break;
2272 }
2273 case SP::FONE:
2274 case SP::FONES:
2275 case SP::FZERO:
2276 case SP::FZEROS:
2277 case SP::RDFQ:
2278 case SP::RDPSR:
2279 case SP::RDTBR:
2280 case SP::RDWIM: {
2281 switch (OpNum) {
2282 case 0:
2283 // op: rd
2284 return 25;
2285 }
2286 break;
2287 }
2288 case SP::BINDrr:
2289 case SP::CALLrr:
2290 case SP::CALLrri:
2291 case SP::FCMPD:
2292 case SP::FCMPD_V9:
2293 case SP::FCMPQ:
2294 case SP::FCMPQ_V9:
2295 case SP::FCMPS:
2296 case SP::FCMPS_V9:
2297 case SP::FLUSHrr:
2298 case SP::LDCSRrr:
2299 case SP::LDFSRrr:
2300 case SP::LDXFSRrr:
2301 case SP::PWRPSRrr:
2302 case SP::RETTrr:
2303 case SP::STCSRrr:
2304 case SP::STDCQrr:
2305 case SP::STDFQrr:
2306 case SP::STFSRrr:
2307 case SP::STXFSRrr:
2308 case SP::WRPSRrr:
2309 case SP::WRTBRrr:
2310 case SP::WRWIMrr: {
2311 switch (OpNum) {
2312 case 0:
2313 // op: rs1
2314 return 14;
2315 case 1:
2316 // op: rs2
2317 return 0;
2318 }
2319 break;
2320 }
2321 case SP::BINDri:
2322 case SP::CALLri:
2323 case SP::CALLrii:
2324 case SP::FLUSHri:
2325 case SP::LDCSRri:
2326 case SP::LDFSRri:
2327 case SP::LDXFSRri:
2328 case SP::PWRPSRri:
2329 case SP::RETTri:
2330 case SP::STCSRri:
2331 case SP::STDCQri:
2332 case SP::STDFQri:
2333 case SP::STFSRri:
2334 case SP::STXFSRri:
2335 case SP::TAIL_CALLri:
2336 case SP::WRPSRri:
2337 case SP::WRTBRri:
2338 case SP::WRWIMri: {
2339 switch (OpNum) {
2340 case 0:
2341 // op: rs1
2342 return 14;
2343 case 1:
2344 // op: simm13
2345 return 0;
2346 }
2347 break;
2348 }
2349 case SP::TICCri:
2350 case SP::TRAPri:
2351 case SP::TXCCri: {
2352 switch (OpNum) {
2353 case 0:
2354 // op: rs1
2355 return 14;
2356 case 2:
2357 // op: cond
2358 return 25;
2359 case 1:
2360 // op: imm
2361 return 0;
2362 }
2363 break;
2364 }
2365 case SP::TICCrr:
2366 case SP::TRAPrr:
2367 case SP::TXCCrr: {
2368 switch (OpNum) {
2369 case 0:
2370 // op: rs1
2371 return 14;
2372 case 2:
2373 // op: cond
2374 return 25;
2375 case 1:
2376 // op: rs2
2377 return 0;
2378 }
2379 break;
2380 }
2381 case SP::CMASK16:
2382 case SP::CMASK32:
2383 case SP::CMASK8:
2384 case SP::MONTMUL:
2385 case SP::MONTSQR:
2386 case SP::MPMUL: {
2387 switch (OpNum) {
2388 case 0:
2389 // op: rs2
2390 return 0;
2391 }
2392 break;
2393 }
2394 case SP::MEMBARi:
2395 case SP::RET:
2396 case SP::RETL:
2397 case SP::SIR: {
2398 switch (OpNum) {
2399 case 0:
2400 // op: simm13
2401 return 0;
2402 }
2403 break;
2404 }
2405 case SP::BPICC:
2406 case SP::BPICCA:
2407 case SP::BPICCANT:
2408 case SP::BPICCNT:
2409 case SP::BPXCC:
2410 case SP::BPXCCA:
2411 case SP::BPXCCANT:
2412 case SP::BPXCCNT:
2413 case SP::FBCONDA_V9:
2414 case SP::FBCOND_V9: {
2415 switch (OpNum) {
2416 case 1:
2417 // op: cond
2418 return 25;
2419 case 0:
2420 // op: imm19
2421 return 0;
2422 }
2423 break;
2424 }
2425 case SP::SETHIi: {
2426 switch (OpNum) {
2427 case 1:
2428 // op: imm22
2429 return 0;
2430 case 0:
2431 // op: rd
2432 return 25;
2433 }
2434 break;
2435 }
2436 case SP::BPFCC:
2437 case SP::BPFCCA:
2438 case SP::BPFCCANT:
2439 case SP::BPFCCNT: {
2440 switch (OpNum) {
2441 case 2:
2442 // op: cc
2443 return 20;
2444 case 1:
2445 // op: cond
2446 return 25;
2447 case 0:
2448 // op: imm19
2449 return 0;
2450 }
2451 break;
2452 }
2453 case SP::PREFETCHr:
2454 case SP::STBrr:
2455 case SP::STCrr:
2456 case SP::STDCrr:
2457 case SP::STDFrr:
2458 case SP::STDrr:
2459 case SP::STFrr:
2460 case SP::STHrr:
2461 case SP::STQFrr:
2462 case SP::STXrr:
2463 case SP::STrr: {
2464 switch (OpNum) {
2465 case 2:
2466 // op: rd
2467 return 25;
2468 case 0:
2469 // op: rs1
2470 return 14;
2471 case 1:
2472 // op: rs2
2473 return 0;
2474 }
2475 break;
2476 }
2477 case SP::PREFETCHAi:
2478 case SP::PREFETCHi:
2479 case SP::STAri:
2480 case SP::STBAri:
2481 case SP::STBri:
2482 case SP::STCri:
2483 case SP::STDAri:
2484 case SP::STDCri:
2485 case SP::STDFAri:
2486 case SP::STDFri:
2487 case SP::STDri:
2488 case SP::STFAri:
2489 case SP::STFri:
2490 case SP::STHAri:
2491 case SP::STHri:
2492 case SP::STQFAri:
2493 case SP::STQFri:
2494 case SP::STXAri:
2495 case SP::STXri:
2496 case SP::STri: {
2497 switch (OpNum) {
2498 case 2:
2499 // op: rd
2500 return 25;
2501 case 0:
2502 // op: rs1
2503 return 14;
2504 case 1:
2505 // op: simm13
2506 return 0;
2507 }
2508 break;
2509 }
2510 case SP::STArr:
2511 case SP::STBArr:
2512 case SP::STDArr:
2513 case SP::STDFArr:
2514 case SP::STFArr:
2515 case SP::STHArr:
2516 case SP::STQFArr:
2517 case SP::STXArr: {
2518 switch (OpNum) {
2519 case 2:
2520 // op: rd
2521 return 25;
2522 case 0:
2523 // op: rs1
2524 return 14;
2525 case 3:
2526 // op: asi
2527 return 5;
2528 case 1:
2529 // op: rs2
2530 return 0;
2531 }
2532 break;
2533 }
2534 case SP::PREFETCHAr: {
2535 switch (OpNum) {
2536 case 3:
2537 // op: rd
2538 return 25;
2539 case 0:
2540 // op: rs1
2541 return 14;
2542 case 2:
2543 // op: asi
2544 return 5;
2545 case 1:
2546 // op: rs2
2547 return 0;
2548 }
2549 break;
2550 }
2551 default:
2552 reportUnsupportedInst(MI);
2553 }
2554 reportUnsupportedOperand(MI, OpNum);
2555}
2556
2557#endif // GET_OPERAND_BIT_OFFSET
2558
2559