1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t SparcRegDiffLists[] = {
12 /* 0 */ -148, 1, 0,
13 /* 3 */ -147, 1, 0,
14 /* 6 */ -146, 1, 0,
15 /* 9 */ -145, 1, 0,
16 /* 12 */ -144, 1, 0,
17 /* 15 */ -143, 1, 0,
18 /* 18 */ -142, 1, 0,
19 /* 21 */ -141, 1, 0,
20 /* 24 */ -140, 1, 0,
21 /* 27 */ -139, 1, 0,
22 /* 30 */ -138, 1, 0,
23 /* 33 */ -137, 1, 0,
24 /* 36 */ -136, 1, 0,
25 /* 39 */ -135, 1, 0,
26 /* 42 */ -134, 1, 0,
27 /* 45 */ -133, 1, 0,
28 /* 48 */ -92, 1, 0,
29 /* 51 */ -91, 1, 0,
30 /* 54 */ -90, 1, 0,
31 /* 57 */ -89, 1, 0,
32 /* 60 */ -88, 1, 0,
33 /* 63 */ -87, 1, 0,
34 /* 66 */ -86, 1, 0,
35 /* 69 */ -85, 1, 0,
36 /* 72 */ -64, 1, 0,
37 /* 75 */ -63, 1, 0,
38 /* 78 */ -62, 1, 0,
39 /* 81 */ -61, 1, 0,
40 /* 84 */ -60, 1, 0,
41 /* 87 */ -59, 1, 0,
42 /* 90 */ -58, 1, 0,
43 /* 93 */ -57, 1, 0,
44 /* 96 */ -56, 1, 0,
45 /* 99 */ -55, 1, 0,
46 /* 102 */ -54, 1, 0,
47 /* 105 */ -53, 1, 0,
48 /* 108 */ -52, 1, 0,
49 /* 111 */ -51, 1, 0,
50 /* 114 */ -50, 1, 0,
51 /* 117 */ -49, 1, 0,
52 /* 120 */ 1, 1, 1, 0,
53 /* 124 */ 32, 1, 0,
54 /* 127 */ -100, 32, 1, -32, 33, 1, 0,
55 /* 134 */ 34, 1, 0,
56 /* 137 */ -99, 34, 1, -34, 35, 1, 0,
57 /* 144 */ 36, 1, 0,
58 /* 147 */ -98, 36, 1, -36, 37, 1, 0,
59 /* 154 */ 38, 1, 0,
60 /* 157 */ -97, 38, 1, -38, 39, 1, 0,
61 /* 164 */ 40, 1, 0,
62 /* 167 */ -96, 40, 1, -40, 41, 1, 0,
63 /* 174 */ 42, 1, 0,
64 /* 177 */ -95, 42, 1, -42, 43, 1, 0,
65 /* 184 */ 44, 1, 0,
66 /* 187 */ -94, 44, 1, -44, 45, 1, 0,
67 /* 194 */ 46, 1, 0,
68 /* 197 */ -93, 46, 1, -46, 47, 1, 0,
69 /* 204 */ 48, 0,
70 /* 206 */ 49, 0,
71 /* 208 */ 50, 0,
72 /* 210 */ 51, 0,
73 /* 212 */ 52, 0,
74 /* 214 */ 53, 0,
75 /* 216 */ 54, 0,
76 /* 218 */ 55, 0,
77 /* 220 */ 56, 0,
78 /* 222 */ 57, 0,
79 /* 224 */ 58, 0,
80 /* 226 */ 59, 0,
81 /* 228 */ 60, 0,
82 /* 230 */ 61, 0,
83 /* 232 */ 62, 0,
84 /* 234 */ 63, 0,
85 /* 236 */ 64, 0,
86 /* 238 */ 84, 0,
87 /* 240 */ 85, 0,
88 /* 242 */ 86, 0,
89 /* 244 */ 87, 0,
90 /* 246 */ 88, 0,
91 /* 248 */ 89, 0,
92 /* 250 */ 90, 0,
93 /* 252 */ 91, 0,
94 /* 254 */ -48, 92, 0,
95 /* 257 */ -47, 92, 0,
96 /* 260 */ -47, 93, 0,
97 /* 263 */ -46, 93, 0,
98 /* 266 */ -45, 93, 0,
99 /* 269 */ -45, 94, 0,
100 /* 272 */ -44, 94, 0,
101 /* 275 */ -43, 94, 0,
102 /* 278 */ -43, 95, 0,
103 /* 281 */ -42, 95, 0,
104 /* 284 */ -41, 95, 0,
105 /* 287 */ -41, 96, 0,
106 /* 290 */ -40, 96, 0,
107 /* 293 */ -39, 96, 0,
108 /* 296 */ -39, 97, 0,
109 /* 299 */ -38, 97, 0,
110 /* 302 */ -37, 97, 0,
111 /* 305 */ -37, 98, 0,
112 /* 308 */ -36, 98, 0,
113 /* 311 */ -35, 98, 0,
114 /* 314 */ -35, 99, 0,
115 /* 317 */ -34, 99, 0,
116 /* 320 */ -33, 99, 0,
117 /* 323 */ -33, 100, 0,
118 /* 326 */ -32, 100, 0,
119 /* 329 */ 132, 0,
120 /* 331 */ 133, 0,
121 /* 333 */ 134, 0,
122 /* 335 */ 135, 0,
123 /* 337 */ 136, 0,
124 /* 339 */ 137, 0,
125 /* 341 */ 138, 0,
126 /* 343 */ 139, 0,
127 /* 345 */ 140, 0,
128 /* 347 */ 141, 0,
129 /* 349 */ 142, 0,
130 /* 351 */ 143, 0,
131 /* 353 */ 144, 0,
132 /* 355 */ 145, 0,
133 /* 357 */ 146, 0,
134 /* 359 */ 147, 0,
135 /* 361 */ 148, 0,
136};
137
138extern const LaneBitmask SparcLaneMaskLists[] = {
139 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
140 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
141 /* 6 */ LaneBitmask(0x0000000000000003), LaneBitmask(0x000000000000000C),
142 /* 8 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
143};
144
145extern const uint16_t SparcSubRegIdxLists[] = {
146 /* 0 */ 1, 3,
147 /* 2 */ 2, 4,
148 /* 4 */ 2, 1, 3, 4, 5, 6,
149};
150
151
152#ifdef __GNUC__
153#pragma GCC diagnostic push
154#pragma GCC diagnostic ignored "-Woverlength-strings"
155#endif
156extern const char SparcRegStrings[] = {
157 /* 0 */ "C10\000"
158 /* 4 */ "D10\000"
159 /* 8 */ "F10\000"
160 /* 12 */ "Q10\000"
161 /* 16 */ "ASR10\000"
162 /* 22 */ "C20\000"
163 /* 26 */ "D20\000"
164 /* 30 */ "F20\000"
165 /* 34 */ "ASR20\000"
166 /* 40 */ "C30\000"
167 /* 44 */ "D30\000"
168 /* 48 */ "F30\000"
169 /* 52 */ "ASR30\000"
170 /* 58 */ "FCC0\000"
171 /* 63 */ "D0\000"
172 /* 66 */ "F0\000"
173 /* 69 */ "G0\000"
174 /* 72 */ "I0\000"
175 /* 75 */ "L0\000"
176 /* 78 */ "O0\000"
177 /* 81 */ "Q0\000"
178 /* 84 */ "C10_C11\000"
179 /* 92 */ "D11\000"
180 /* 96 */ "F11\000"
181 /* 100 */ "Q11\000"
182 /* 104 */ "ASR11\000"
183 /* 110 */ "C20_C21\000"
184 /* 118 */ "D21\000"
185 /* 122 */ "F21\000"
186 /* 126 */ "ASR21\000"
187 /* 132 */ "C30_C31\000"
188 /* 140 */ "D31\000"
189 /* 144 */ "F31\000"
190 /* 148 */ "ASR31\000"
191 /* 154 */ "FCC1\000"
192 /* 159 */ "C0_C1\000"
193 /* 165 */ "D1\000"
194 /* 168 */ "F1\000"
195 /* 171 */ "G0_G1\000"
196 /* 177 */ "I0_I1\000"
197 /* 183 */ "L0_L1\000"
198 /* 189 */ "O0_O1\000"
199 /* 195 */ "Q1\000"
200 /* 198 */ "ASR1\000"
201 /* 203 */ "C12\000"
202 /* 207 */ "D12\000"
203 /* 211 */ "F12\000"
204 /* 215 */ "Q12\000"
205 /* 219 */ "ASR12\000"
206 /* 225 */ "C22\000"
207 /* 229 */ "D22\000"
208 /* 233 */ "F22\000"
209 /* 237 */ "ASR22\000"
210 /* 243 */ "FCC2\000"
211 /* 248 */ "D2\000"
212 /* 251 */ "F2\000"
213 /* 254 */ "G2\000"
214 /* 257 */ "I2\000"
215 /* 260 */ "L2\000"
216 /* 263 */ "O2\000"
217 /* 266 */ "Q2\000"
218 /* 269 */ "ASR2\000"
219 /* 274 */ "C12_C13\000"
220 /* 282 */ "D13\000"
221 /* 286 */ "F13\000"
222 /* 290 */ "Q13\000"
223 /* 294 */ "ASR13\000"
224 /* 300 */ "C22_C23\000"
225 /* 308 */ "D23\000"
226 /* 312 */ "F23\000"
227 /* 316 */ "ASR23\000"
228 /* 322 */ "FCC3\000"
229 /* 327 */ "C2_C3\000"
230 /* 333 */ "D3\000"
231 /* 336 */ "F3\000"
232 /* 339 */ "G2_G3\000"
233 /* 345 */ "I2_I3\000"
234 /* 351 */ "L2_L3\000"
235 /* 357 */ "O2_O3\000"
236 /* 363 */ "Q3\000"
237 /* 366 */ "ASR3\000"
238 /* 371 */ "C14\000"
239 /* 375 */ "D14\000"
240 /* 379 */ "F14\000"
241 /* 383 */ "Q14\000"
242 /* 387 */ "ASR14\000"
243 /* 393 */ "C24\000"
244 /* 397 */ "D24\000"
245 /* 401 */ "F24\000"
246 /* 405 */ "ASR24\000"
247 /* 411 */ "C4\000"
248 /* 414 */ "D4\000"
249 /* 417 */ "F4\000"
250 /* 420 */ "G4\000"
251 /* 423 */ "I4\000"
252 /* 426 */ "L4\000"
253 /* 429 */ "O4\000"
254 /* 432 */ "Q4\000"
255 /* 435 */ "ASR4\000"
256 /* 440 */ "C14_C15\000"
257 /* 448 */ "D15\000"
258 /* 452 */ "F15\000"
259 /* 456 */ "Q15\000"
260 /* 460 */ "ASR15\000"
261 /* 466 */ "C24_C25\000"
262 /* 474 */ "D25\000"
263 /* 478 */ "F25\000"
264 /* 482 */ "ASR25\000"
265 /* 488 */ "C4_C5\000"
266 /* 494 */ "D5\000"
267 /* 497 */ "F5\000"
268 /* 500 */ "G4_G5\000"
269 /* 506 */ "I4_I5\000"
270 /* 512 */ "L4_L5\000"
271 /* 518 */ "O4_O5\000"
272 /* 524 */ "Q5\000"
273 /* 527 */ "ASR5\000"
274 /* 532 */ "C16\000"
275 /* 536 */ "D16\000"
276 /* 540 */ "F16\000"
277 /* 544 */ "ASR16\000"
278 /* 550 */ "C26\000"
279 /* 554 */ "D26\000"
280 /* 558 */ "F26\000"
281 /* 562 */ "ASR26\000"
282 /* 568 */ "C6\000"
283 /* 571 */ "D6\000"
284 /* 574 */ "F6\000"
285 /* 577 */ "G6\000"
286 /* 580 */ "I6\000"
287 /* 583 */ "L6\000"
288 /* 586 */ "O6\000"
289 /* 589 */ "Q6\000"
290 /* 592 */ "ASR6\000"
291 /* 597 */ "C16_C17\000"
292 /* 605 */ "D17\000"
293 /* 609 */ "F17\000"
294 /* 613 */ "ASR17\000"
295 /* 619 */ "C26_C27\000"
296 /* 627 */ "D27\000"
297 /* 631 */ "F27\000"
298 /* 635 */ "ASR27\000"
299 /* 641 */ "C6_C7\000"
300 /* 647 */ "D7\000"
301 /* 650 */ "F7\000"
302 /* 653 */ "G6_G7\000"
303 /* 659 */ "I6_I7\000"
304 /* 665 */ "L6_L7\000"
305 /* 671 */ "O6_O7\000"
306 /* 677 */ "Q7\000"
307 /* 680 */ "ASR7\000"
308 /* 685 */ "C18\000"
309 /* 689 */ "D18\000"
310 /* 693 */ "F18\000"
311 /* 697 */ "ASR18\000"
312 /* 703 */ "C28\000"
313 /* 707 */ "D28\000"
314 /* 711 */ "F28\000"
315 /* 715 */ "ASR28\000"
316 /* 721 */ "C8\000"
317 /* 724 */ "D8\000"
318 /* 727 */ "F8\000"
319 /* 730 */ "Q8\000"
320 /* 733 */ "ASR8\000"
321 /* 738 */ "C18_C19\000"
322 /* 746 */ "D19\000"
323 /* 750 */ "F19\000"
324 /* 754 */ "ASR19\000"
325 /* 760 */ "C28_C29\000"
326 /* 768 */ "D29\000"
327 /* 772 */ "F29\000"
328 /* 776 */ "ASR29\000"
329 /* 782 */ "C8_C9\000"
330 /* 788 */ "D9\000"
331 /* 791 */ "F9\000"
332 /* 794 */ "Q9\000"
333 /* 797 */ "ASR9\000"
334 /* 802 */ "TBA\000"
335 /* 806 */ "ICC\000"
336 /* 810 */ "TNPC\000"
337 /* 815 */ "TPC\000"
338 /* 819 */ "CANRESTORE\000"
339 /* 830 */ "PSTATE\000"
340 /* 837 */ "TSTATE\000"
341 /* 844 */ "WSTATE\000"
342 /* 851 */ "CANSAVE\000"
343 /* 859 */ "TICK\000"
344 /* 864 */ "GL\000"
345 /* 867 */ "PIL\000"
346 /* 871 */ "TL\000"
347 /* 874 */ "WIM\000"
348 /* 878 */ "CLEANWIN\000"
349 /* 887 */ "OTHERWIN\000"
350 /* 896 */ "CWP\000"
351 /* 900 */ "FQ\000"
352 /* 903 */ "CPQ\000"
353 /* 907 */ "TBR\000"
354 /* 911 */ "VER\000"
355 /* 915 */ "FSR\000"
356 /* 919 */ "CPSR\000"
357 /* 924 */ "TT\000"
358 /* 927 */ "Y\000"
359};
360#ifdef __GNUC__
361#pragma GCC diagnostic pop
362#endif
363
364extern const MCRegisterDesc SparcRegDesc[] = { // Descriptors
365 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
366 { .Name: 819, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8192, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
367 { .Name: 851, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8193, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
368 { .Name: 878, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8194, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
369 { .Name: 903, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8195, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
370 { .Name: 919, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8196, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
371 { .Name: 896, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8197, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
372 { .Name: 900, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8198, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
373 { .Name: 915, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8199, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
374 { .Name: 864, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8200, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
375 { .Name: 806, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8201, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
376 { .Name: 887, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8202, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
377 { .Name: 867, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8203, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
378 { .Name: 920, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8204, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
379 { .Name: 830, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8205, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
380 { .Name: 802, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8206, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
381 { .Name: 907, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8207, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
382 { .Name: 859, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8208, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
383 { .Name: 871, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8209, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
384 { .Name: 810, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8210, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
385 { .Name: 815, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8211, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
386 { .Name: 837, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8212, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
387 { .Name: 924, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8213, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
388 { .Name: 911, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8214, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
389 { .Name: 874, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8215, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
390 { .Name: 844, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8216, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
391 { .Name: 927, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8217, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
392 { .Name: 198, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8218, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
393 { .Name: 269, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8219, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
394 { .Name: 366, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8220, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
395 { .Name: 435, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8221, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
396 { .Name: 527, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8222, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
397 { .Name: 592, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8223, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
398 { .Name: 680, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8224, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
399 { .Name: 733, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8225, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
400 { .Name: 797, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8226, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
401 { .Name: 16, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8227, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
402 { .Name: 104, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8228, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
403 { .Name: 219, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8229, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
404 { .Name: 294, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8230, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
405 { .Name: 387, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8231, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
406 { .Name: 460, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8232, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
407 { .Name: 544, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8233, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
408 { .Name: 613, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8234, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
409 { .Name: 697, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8235, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
410 { .Name: 754, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8236, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
411 { .Name: 34, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8237, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
412 { .Name: 126, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8238, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
413 { .Name: 237, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8239, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
414 { .Name: 316, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8240, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
415 { .Name: 405, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8241, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
416 { .Name: 482, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8242, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
417 { .Name: 562, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8243, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
418 { .Name: 635, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8244, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
419 { .Name: 715, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8245, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
420 { .Name: 776, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8246, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
421 { .Name: 52, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8247, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
422 { .Name: 148, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8248, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
423 { .Name: 60, .SubRegs: 2, .SuperRegs: 361, .SubRegIndices: 2, .RegUnits: 8249, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
424 { .Name: 156, .SubRegs: 2, .SuperRegs: 359, .SubRegIndices: 2, .RegUnits: 8250, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
425 { .Name: 245, .SubRegs: 2, .SuperRegs: 359, .SubRegIndices: 2, .RegUnits: 8251, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
426 { .Name: 324, .SubRegs: 2, .SuperRegs: 357, .SubRegIndices: 2, .RegUnits: 8252, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
427 { .Name: 411, .SubRegs: 2, .SuperRegs: 357, .SubRegIndices: 2, .RegUnits: 8253, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
428 { .Name: 491, .SubRegs: 2, .SuperRegs: 355, .SubRegIndices: 2, .RegUnits: 8254, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
429 { .Name: 568, .SubRegs: 2, .SuperRegs: 355, .SubRegIndices: 2, .RegUnits: 8255, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
430 { .Name: 644, .SubRegs: 2, .SuperRegs: 353, .SubRegIndices: 2, .RegUnits: 8256, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
431 { .Name: 721, .SubRegs: 2, .SuperRegs: 353, .SubRegIndices: 2, .RegUnits: 8257, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
432 { .Name: 785, .SubRegs: 2, .SuperRegs: 351, .SubRegIndices: 2, .RegUnits: 8258, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
433 { .Name: 0, .SubRegs: 2, .SuperRegs: 351, .SubRegIndices: 2, .RegUnits: 8259, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
434 { .Name: 88, .SubRegs: 2, .SuperRegs: 349, .SubRegIndices: 2, .RegUnits: 8260, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
435 { .Name: 203, .SubRegs: 2, .SuperRegs: 349, .SubRegIndices: 2, .RegUnits: 8261, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
436 { .Name: 278, .SubRegs: 2, .SuperRegs: 347, .SubRegIndices: 2, .RegUnits: 8262, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
437 { .Name: 371, .SubRegs: 2, .SuperRegs: 347, .SubRegIndices: 2, .RegUnits: 8263, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
438 { .Name: 444, .SubRegs: 2, .SuperRegs: 345, .SubRegIndices: 2, .RegUnits: 8264, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
439 { .Name: 532, .SubRegs: 2, .SuperRegs: 345, .SubRegIndices: 2, .RegUnits: 8265, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
440 { .Name: 601, .SubRegs: 2, .SuperRegs: 343, .SubRegIndices: 2, .RegUnits: 8266, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
441 { .Name: 685, .SubRegs: 2, .SuperRegs: 343, .SubRegIndices: 2, .RegUnits: 8267, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
442 { .Name: 742, .SubRegs: 2, .SuperRegs: 341, .SubRegIndices: 2, .RegUnits: 8268, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
443 { .Name: 22, .SubRegs: 2, .SuperRegs: 341, .SubRegIndices: 2, .RegUnits: 8269, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
444 { .Name: 114, .SubRegs: 2, .SuperRegs: 339, .SubRegIndices: 2, .RegUnits: 8270, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
445 { .Name: 225, .SubRegs: 2, .SuperRegs: 339, .SubRegIndices: 2, .RegUnits: 8271, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
446 { .Name: 304, .SubRegs: 2, .SuperRegs: 337, .SubRegIndices: 2, .RegUnits: 8272, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
447 { .Name: 393, .SubRegs: 2, .SuperRegs: 337, .SubRegIndices: 2, .RegUnits: 8273, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
448 { .Name: 470, .SubRegs: 2, .SuperRegs: 335, .SubRegIndices: 2, .RegUnits: 8274, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
449 { .Name: 550, .SubRegs: 2, .SuperRegs: 335, .SubRegIndices: 2, .RegUnits: 8275, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
450 { .Name: 623, .SubRegs: 2, .SuperRegs: 333, .SubRegIndices: 2, .RegUnits: 8276, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
451 { .Name: 703, .SubRegs: 2, .SuperRegs: 333, .SubRegIndices: 2, .RegUnits: 8277, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
452 { .Name: 764, .SubRegs: 2, .SuperRegs: 331, .SubRegIndices: 2, .RegUnits: 8278, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
453 { .Name: 40, .SubRegs: 2, .SuperRegs: 331, .SubRegIndices: 2, .RegUnits: 8279, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
454 { .Name: 136, .SubRegs: 2, .SuperRegs: 329, .SubRegIndices: 2, .RegUnits: 8280, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
455 { .Name: 63, .SubRegs: 124, .SuperRegs: 324, .SubRegIndices: 0, .RegUnits: 4185, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
456 { .Name: 165, .SubRegs: 131, .SuperRegs: 315, .SubRegIndices: 0, .RegUnits: 4187, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
457 { .Name: 248, .SubRegs: 134, .SuperRegs: 315, .SubRegIndices: 0, .RegUnits: 4189, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
458 { .Name: 333, .SubRegs: 141, .SuperRegs: 306, .SubRegIndices: 0, .RegUnits: 4191, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
459 { .Name: 414, .SubRegs: 144, .SuperRegs: 306, .SubRegIndices: 0, .RegUnits: 4193, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
460 { .Name: 494, .SubRegs: 151, .SuperRegs: 297, .SubRegIndices: 0, .RegUnits: 4195, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
461 { .Name: 571, .SubRegs: 154, .SuperRegs: 297, .SubRegIndices: 0, .RegUnits: 4197, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
462 { .Name: 647, .SubRegs: 161, .SuperRegs: 288, .SubRegIndices: 0, .RegUnits: 4199, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
463 { .Name: 724, .SubRegs: 164, .SuperRegs: 288, .SubRegIndices: 0, .RegUnits: 4201, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
464 { .Name: 788, .SubRegs: 171, .SuperRegs: 279, .SubRegIndices: 0, .RegUnits: 4203, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
465 { .Name: 4, .SubRegs: 174, .SuperRegs: 279, .SubRegIndices: 0, .RegUnits: 4205, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
466 { .Name: 92, .SubRegs: 181, .SuperRegs: 270, .SubRegIndices: 0, .RegUnits: 4207, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
467 { .Name: 207, .SubRegs: 184, .SuperRegs: 270, .SubRegIndices: 0, .RegUnits: 4209, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
468 { .Name: 282, .SubRegs: 191, .SuperRegs: 261, .SubRegIndices: 0, .RegUnits: 4211, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
469 { .Name: 375, .SubRegs: 194, .SuperRegs: 261, .SubRegIndices: 0, .RegUnits: 4213, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
470 { .Name: 448, .SubRegs: 201, .SuperRegs: 255, .SubRegIndices: 0, .RegUnits: 4215, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
471 { .Name: 536, .SubRegs: 2, .SuperRegs: 255, .SubRegIndices: 2, .RegUnits: 8313, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
472 { .Name: 605, .SubRegs: 2, .SuperRegs: 252, .SubRegIndices: 2, .RegUnits: 8314, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
473 { .Name: 689, .SubRegs: 2, .SuperRegs: 252, .SubRegIndices: 2, .RegUnits: 8315, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
474 { .Name: 746, .SubRegs: 2, .SuperRegs: 250, .SubRegIndices: 2, .RegUnits: 8316, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
475 { .Name: 26, .SubRegs: 2, .SuperRegs: 250, .SubRegIndices: 2, .RegUnits: 8317, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
476 { .Name: 118, .SubRegs: 2, .SuperRegs: 248, .SubRegIndices: 2, .RegUnits: 8318, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
477 { .Name: 229, .SubRegs: 2, .SuperRegs: 248, .SubRegIndices: 2, .RegUnits: 8319, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
478 { .Name: 308, .SubRegs: 2, .SuperRegs: 246, .SubRegIndices: 2, .RegUnits: 8320, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
479 { .Name: 397, .SubRegs: 2, .SuperRegs: 246, .SubRegIndices: 2, .RegUnits: 8321, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
480 { .Name: 474, .SubRegs: 2, .SuperRegs: 244, .SubRegIndices: 2, .RegUnits: 8322, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
481 { .Name: 554, .SubRegs: 2, .SuperRegs: 244, .SubRegIndices: 2, .RegUnits: 8323, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
482 { .Name: 627, .SubRegs: 2, .SuperRegs: 242, .SubRegIndices: 2, .RegUnits: 8324, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
483 { .Name: 707, .SubRegs: 2, .SuperRegs: 242, .SubRegIndices: 2, .RegUnits: 8325, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
484 { .Name: 768, .SubRegs: 2, .SuperRegs: 240, .SubRegIndices: 2, .RegUnits: 8326, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
485 { .Name: 44, .SubRegs: 2, .SuperRegs: 240, .SubRegIndices: 2, .RegUnits: 8327, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
486 { .Name: 140, .SubRegs: 2, .SuperRegs: 238, .SubRegIndices: 2, .RegUnits: 8328, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
487 { .Name: 66, .SubRegs: 2, .SuperRegs: 326, .SubRegIndices: 2, .RegUnits: 8281, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
488 { .Name: 168, .SubRegs: 2, .SuperRegs: 323, .SubRegIndices: 2, .RegUnits: 8282, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
489 { .Name: 251, .SubRegs: 2, .SuperRegs: 320, .SubRegIndices: 2, .RegUnits: 8283, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
490 { .Name: 336, .SubRegs: 2, .SuperRegs: 317, .SubRegIndices: 2, .RegUnits: 8284, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
491 { .Name: 417, .SubRegs: 2, .SuperRegs: 317, .SubRegIndices: 2, .RegUnits: 8285, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
492 { .Name: 497, .SubRegs: 2, .SuperRegs: 314, .SubRegIndices: 2, .RegUnits: 8286, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
493 { .Name: 574, .SubRegs: 2, .SuperRegs: 311, .SubRegIndices: 2, .RegUnits: 8287, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
494 { .Name: 650, .SubRegs: 2, .SuperRegs: 308, .SubRegIndices: 2, .RegUnits: 8288, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
495 { .Name: 727, .SubRegs: 2, .SuperRegs: 308, .SubRegIndices: 2, .RegUnits: 8289, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
496 { .Name: 791, .SubRegs: 2, .SuperRegs: 305, .SubRegIndices: 2, .RegUnits: 8290, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
497 { .Name: 8, .SubRegs: 2, .SuperRegs: 302, .SubRegIndices: 2, .RegUnits: 8291, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
498 { .Name: 96, .SubRegs: 2, .SuperRegs: 299, .SubRegIndices: 2, .RegUnits: 8292, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
499 { .Name: 211, .SubRegs: 2, .SuperRegs: 299, .SubRegIndices: 2, .RegUnits: 8293, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
500 { .Name: 286, .SubRegs: 2, .SuperRegs: 296, .SubRegIndices: 2, .RegUnits: 8294, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
501 { .Name: 379, .SubRegs: 2, .SuperRegs: 293, .SubRegIndices: 2, .RegUnits: 8295, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
502 { .Name: 452, .SubRegs: 2, .SuperRegs: 290, .SubRegIndices: 2, .RegUnits: 8296, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
503 { .Name: 540, .SubRegs: 2, .SuperRegs: 290, .SubRegIndices: 2, .RegUnits: 8297, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
504 { .Name: 609, .SubRegs: 2, .SuperRegs: 287, .SubRegIndices: 2, .RegUnits: 8298, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
505 { .Name: 693, .SubRegs: 2, .SuperRegs: 284, .SubRegIndices: 2, .RegUnits: 8299, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
506 { .Name: 750, .SubRegs: 2, .SuperRegs: 281, .SubRegIndices: 2, .RegUnits: 8300, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
507 { .Name: 30, .SubRegs: 2, .SuperRegs: 281, .SubRegIndices: 2, .RegUnits: 8301, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
508 { .Name: 122, .SubRegs: 2, .SuperRegs: 278, .SubRegIndices: 2, .RegUnits: 8302, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
509 { .Name: 233, .SubRegs: 2, .SuperRegs: 275, .SubRegIndices: 2, .RegUnits: 8303, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
510 { .Name: 312, .SubRegs: 2, .SuperRegs: 272, .SubRegIndices: 2, .RegUnits: 8304, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
511 { .Name: 401, .SubRegs: 2, .SuperRegs: 272, .SubRegIndices: 2, .RegUnits: 8305, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
512 { .Name: 478, .SubRegs: 2, .SuperRegs: 269, .SubRegIndices: 2, .RegUnits: 8306, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
513 { .Name: 558, .SubRegs: 2, .SuperRegs: 266, .SubRegIndices: 2, .RegUnits: 8307, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
514 { .Name: 631, .SubRegs: 2, .SuperRegs: 263, .SubRegIndices: 2, .RegUnits: 8308, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
515 { .Name: 711, .SubRegs: 2, .SuperRegs: 263, .SubRegIndices: 2, .RegUnits: 8309, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
516 { .Name: 772, .SubRegs: 2, .SuperRegs: 260, .SubRegIndices: 2, .RegUnits: 8310, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
517 { .Name: 48, .SubRegs: 2, .SuperRegs: 257, .SubRegIndices: 2, .RegUnits: 8311, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
518 { .Name: 144, .SubRegs: 2, .SuperRegs: 254, .SubRegIndices: 2, .RegUnits: 8312, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
519 { .Name: 58, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8329, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
520 { .Name: 154, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8330, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
521 { .Name: 243, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8331, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
522 { .Name: 322, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8332, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
523 { .Name: 69, .SubRegs: 2, .SuperRegs: 236, .SubRegIndices: 2, .RegUnits: 8333, .RegUnitLaneMasks: 8, .IsConstant: 1, .IsArtificial: 0 },
524 { .Name: 174, .SubRegs: 2, .SuperRegs: 234, .SubRegIndices: 2, .RegUnits: 8334, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
525 { .Name: 254, .SubRegs: 2, .SuperRegs: 234, .SubRegIndices: 2, .RegUnits: 8335, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
526 { .Name: 342, .SubRegs: 2, .SuperRegs: 232, .SubRegIndices: 2, .RegUnits: 8336, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
527 { .Name: 420, .SubRegs: 2, .SuperRegs: 232, .SubRegIndices: 2, .RegUnits: 8337, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
528 { .Name: 503, .SubRegs: 2, .SuperRegs: 230, .SubRegIndices: 2, .RegUnits: 8338, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
529 { .Name: 577, .SubRegs: 2, .SuperRegs: 230, .SubRegIndices: 2, .RegUnits: 8339, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
530 { .Name: 656, .SubRegs: 2, .SuperRegs: 228, .SubRegIndices: 2, .RegUnits: 8340, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
531 { .Name: 72, .SubRegs: 2, .SuperRegs: 228, .SubRegIndices: 2, .RegUnits: 8341, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
532 { .Name: 180, .SubRegs: 2, .SuperRegs: 226, .SubRegIndices: 2, .RegUnits: 8342, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
533 { .Name: 257, .SubRegs: 2, .SuperRegs: 226, .SubRegIndices: 2, .RegUnits: 8343, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
534 { .Name: 348, .SubRegs: 2, .SuperRegs: 224, .SubRegIndices: 2, .RegUnits: 8344, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
535 { .Name: 423, .SubRegs: 2, .SuperRegs: 224, .SubRegIndices: 2, .RegUnits: 8345, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
536 { .Name: 509, .SubRegs: 2, .SuperRegs: 222, .SubRegIndices: 2, .RegUnits: 8346, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
537 { .Name: 580, .SubRegs: 2, .SuperRegs: 222, .SubRegIndices: 2, .RegUnits: 8347, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
538 { .Name: 662, .SubRegs: 2, .SuperRegs: 220, .SubRegIndices: 2, .RegUnits: 8348, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
539 { .Name: 75, .SubRegs: 2, .SuperRegs: 220, .SubRegIndices: 2, .RegUnits: 8349, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
540 { .Name: 186, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8350, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
541 { .Name: 260, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8351, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
542 { .Name: 354, .SubRegs: 2, .SuperRegs: 216, .SubRegIndices: 2, .RegUnits: 8352, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
543 { .Name: 426, .SubRegs: 2, .SuperRegs: 216, .SubRegIndices: 2, .RegUnits: 8353, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
544 { .Name: 515, .SubRegs: 2, .SuperRegs: 214, .SubRegIndices: 2, .RegUnits: 8354, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
545 { .Name: 583, .SubRegs: 2, .SuperRegs: 214, .SubRegIndices: 2, .RegUnits: 8355, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
546 { .Name: 668, .SubRegs: 2, .SuperRegs: 212, .SubRegIndices: 2, .RegUnits: 8356, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
547 { .Name: 78, .SubRegs: 2, .SuperRegs: 212, .SubRegIndices: 2, .RegUnits: 8357, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
548 { .Name: 192, .SubRegs: 2, .SuperRegs: 210, .SubRegIndices: 2, .RegUnits: 8358, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
549 { .Name: 263, .SubRegs: 2, .SuperRegs: 210, .SubRegIndices: 2, .RegUnits: 8359, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
550 { .Name: 360, .SubRegs: 2, .SuperRegs: 208, .SubRegIndices: 2, .RegUnits: 8360, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
551 { .Name: 429, .SubRegs: 2, .SuperRegs: 208, .SubRegIndices: 2, .RegUnits: 8361, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
552 { .Name: 521, .SubRegs: 2, .SuperRegs: 206, .SubRegIndices: 2, .RegUnits: 8362, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
553 { .Name: 586, .SubRegs: 2, .SuperRegs: 206, .SubRegIndices: 2, .RegUnits: 8363, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
554 { .Name: 674, .SubRegs: 2, .SuperRegs: 204, .SubRegIndices: 2, .RegUnits: 8364, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
555 { .Name: 81, .SubRegs: 127, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 491609, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
556 { .Name: 195, .SubRegs: 137, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 491613, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
557 { .Name: 266, .SubRegs: 147, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 491617, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
558 { .Name: 363, .SubRegs: 157, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 491621, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
559 { .Name: 432, .SubRegs: 167, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 491625, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
560 { .Name: 524, .SubRegs: 177, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 491629, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 589, .SubRegs: 187, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 491633, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 677, .SubRegs: 197, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 491637, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 730, .SubRegs: 48, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 4217, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 794, .SubRegs: 51, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 4219, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 12, .SubRegs: 54, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 4221, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 100, .SubRegs: 57, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 4223, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 215, .SubRegs: 60, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 4225, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 290, .SubRegs: 63, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 4227, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 383, .SubRegs: 66, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 4229, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 456, .SubRegs: 69, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 4231, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 159, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4153, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 327, .SubRegs: 3, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4155, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 488, .SubRegs: 6, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4157, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 641, .SubRegs: 9, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4159, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 782, .SubRegs: 12, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4161, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 84, .SubRegs: 15, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4163, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 274, .SubRegs: 18, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4165, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 440, .SubRegs: 21, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4167, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 597, .SubRegs: 24, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4169, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 738, .SubRegs: 27, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4171, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 110, .SubRegs: 30, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4173, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 300, .SubRegs: 33, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4175, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 466, .SubRegs: 36, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4177, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 619, .SubRegs: 39, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4179, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 760, .SubRegs: 42, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4181, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 132, .SubRegs: 45, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4183, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 171, .SubRegs: 72, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4237, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 339, .SubRegs: 75, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4239, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 500, .SubRegs: 78, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4241, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 653, .SubRegs: 81, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4243, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 177, .SubRegs: 84, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4245, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 345, .SubRegs: 87, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4247, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 506, .SubRegs: 90, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4249, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 659, .SubRegs: 93, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4251, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 183, .SubRegs: 96, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4253, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 351, .SubRegs: 99, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4255, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 512, .SubRegs: 102, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4257, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 665, .SubRegs: 105, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4259, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 189, .SubRegs: 108, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4261, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 357, .SubRegs: 111, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4263, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 518, .SubRegs: 114, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4265, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 671, .SubRegs: 117, .SuperRegs: 2, .SubRegIndices: 0, .RegUnits: 4267, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
603};
604
605extern const MCPhysReg SparcRegUnitRoots[][2] = {
606 { SP::CANRESTORE },
607 { SP::CANSAVE },
608 { SP::CLEANWIN },
609 { SP::CPQ },
610 { SP::CPSR },
611 { SP::CWP },
612 { SP::FQ },
613 { SP::FSR },
614 { SP::GL },
615 { SP::ICC },
616 { SP::OTHERWIN },
617 { SP::PIL },
618 { SP::PSR },
619 { SP::PSTATE },
620 { SP::TBA },
621 { SP::TBR },
622 { SP::TICK },
623 { SP::TL },
624 { SP::TNPC },
625 { SP::TPC },
626 { SP::TSTATE },
627 { SP::TT },
628 { SP::VER },
629 { SP::WIM },
630 { SP::WSTATE },
631 { SP::Y },
632 { SP::ASR1 },
633 { SP::ASR2 },
634 { SP::ASR3 },
635 { SP::ASR4 },
636 { SP::ASR5 },
637 { SP::ASR6 },
638 { SP::ASR7 },
639 { SP::ASR8 },
640 { SP::ASR9 },
641 { SP::ASR10 },
642 { SP::ASR11 },
643 { SP::ASR12 },
644 { SP::ASR13 },
645 { SP::ASR14 },
646 { SP::ASR15 },
647 { SP::ASR16 },
648 { SP::ASR17 },
649 { SP::ASR18 },
650 { SP::ASR19 },
651 { SP::ASR20 },
652 { SP::ASR21 },
653 { SP::ASR22 },
654 { SP::ASR23 },
655 { SP::ASR24 },
656 { SP::ASR25 },
657 { SP::ASR26 },
658 { SP::ASR27 },
659 { SP::ASR28 },
660 { SP::ASR29 },
661 { SP::ASR30 },
662 { SP::ASR31 },
663 { SP::C0 },
664 { SP::C1 },
665 { SP::C2 },
666 { SP::C3 },
667 { SP::C4 },
668 { SP::C5 },
669 { SP::C6 },
670 { SP::C7 },
671 { SP::C8 },
672 { SP::C9 },
673 { SP::C10 },
674 { SP::C11 },
675 { SP::C12 },
676 { SP::C13 },
677 { SP::C14 },
678 { SP::C15 },
679 { SP::C16 },
680 { SP::C17 },
681 { SP::C18 },
682 { SP::C19 },
683 { SP::C20 },
684 { SP::C21 },
685 { SP::C22 },
686 { SP::C23 },
687 { SP::C24 },
688 { SP::C25 },
689 { SP::C26 },
690 { SP::C27 },
691 { SP::C28 },
692 { SP::C29 },
693 { SP::C30 },
694 { SP::C31 },
695 { SP::F0 },
696 { SP::F1 },
697 { SP::F2 },
698 { SP::F3 },
699 { SP::F4 },
700 { SP::F5 },
701 { SP::F6 },
702 { SP::F7 },
703 { SP::F8 },
704 { SP::F9 },
705 { SP::F10 },
706 { SP::F11 },
707 { SP::F12 },
708 { SP::F13 },
709 { SP::F14 },
710 { SP::F15 },
711 { SP::F16 },
712 { SP::F17 },
713 { SP::F18 },
714 { SP::F19 },
715 { SP::F20 },
716 { SP::F21 },
717 { SP::F22 },
718 { SP::F23 },
719 { SP::F24 },
720 { SP::F25 },
721 { SP::F26 },
722 { SP::F27 },
723 { SP::F28 },
724 { SP::F29 },
725 { SP::F30 },
726 { SP::F31 },
727 { SP::D16 },
728 { SP::D17 },
729 { SP::D18 },
730 { SP::D19 },
731 { SP::D20 },
732 { SP::D21 },
733 { SP::D22 },
734 { SP::D23 },
735 { SP::D24 },
736 { SP::D25 },
737 { SP::D26 },
738 { SP::D27 },
739 { SP::D28 },
740 { SP::D29 },
741 { SP::D30 },
742 { SP::D31 },
743 { SP::FCC0 },
744 { SP::FCC1 },
745 { SP::FCC2 },
746 { SP::FCC3 },
747 { SP::G0 },
748 { SP::G1 },
749 { SP::G2 },
750 { SP::G3 },
751 { SP::G4 },
752 { SP::G5 },
753 { SP::G6 },
754 { SP::G7 },
755 { SP::I0 },
756 { SP::I1 },
757 { SP::I2 },
758 { SP::I3 },
759 { SP::I4 },
760 { SP::I5 },
761 { SP::I6 },
762 { SP::I7 },
763 { SP::L0 },
764 { SP::L1 },
765 { SP::L2 },
766 { SP::L3 },
767 { SP::L4 },
768 { SP::L5 },
769 { SP::L6 },
770 { SP::L7 },
771 { SP::O0 },
772 { SP::O1 },
773 { SP::O2 },
774 { SP::O3 },
775 { SP::O4 },
776 { SP::O5 },
777 { SP::O6 },
778 { SP::O7 },
779};
780
781// Register classes...
782
783#ifdef __GNUC__
784#pragma GCC diagnostic push
785#pragma GCC diagnostic ignored "-Woverlength-strings"
786#endif
787extern const char SparcRegClassStrings[] = {
788 /* 0 */ "I64Regs_and_GPRIncomingArg\000"
789 /* 27 */ "IntPair_with_sub_even_in_GPRIncomingArg\000"
790 /* 67 */ "I64Regs_and_GPROutgoingArg\000"
791 /* 94 */ "IntPair_with_sub_even_in_GPROutgoingArg\000"
792 /* 134 */ "CoprocPair\000"
793 /* 145 */ "IntPair\000"
794 /* 153 */ "I64Regs\000"
795 /* 161 */ "FCCRegs\000"
796 /* 169 */ "LowDFPRegs\000"
797 /* 180 */ "LowQFPRegs\000"
798 /* 191 */ "PRRegs\000"
799 /* 198 */ "PRRegs_and_ASRRegs\000"
800 /* 217 */ "CoprocRegs\000"
801 /* 228 */ "IntRegs\000"
802};
803#ifdef __GNUC__
804#pragma GCC diagnostic pop
805#endif
806
807using SparcRegisterClassStorage = MCRegisterClassStorage<20, 317, 405, 42, 11, 15>;
808extern const MCRegisterClassStorage<20, 317, 405, 42, 11, 15> SparcMCRegisterClassStorage = {
809 .Classes: {
810 {
811 offsetof(SparcRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
812 offsetof(SparcRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
813 .NameIdx: 161,
814 .RegSizeInBits: 1,
815 .RegsSize: 4,
816 .RegSetSize: 20,
817 .ID: SP::FCCRegsRegClassID,
818 .CopyCost: 1, /* CopyCost */
819 .Allocatable: true, /* Allocatable */
820 .BaseClass: false,
821 offsetof(SparcRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
822 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 0 * sizeof(MCRegisterClass),
823 .LaneMask: LaneBitmask(0x0000000000000001),
824 .AllocationPriority: 0,
825 .GlobalPriority: false,
826 .TSFlags: 0x00, /* TSFlags */
827 .SpillStackID: 0, /* SpillStackID */
828 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
829 .CoveredBySubRegs: false, /* CoveredBySubRegs */
830 offsetof(SparcRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
831 .SuperClassesSize: 0
832 },
833 {
834 offsetof(SparcRegisterClassStorage, Regs[4]) - 1 * sizeof(MCRegisterClass),
835 offsetof(SparcRegisterClassStorage, BitSets[20]) - 1 * sizeof(MCRegisterClass),
836 .NameIdx: 209,
837 .RegSizeInBits: 32,
838 .RegsSize: 33,
839 .RegSetSize: 8,
840 .ID: SP::ASRRegsRegClassID,
841 .CopyCost: 1, /* CopyCost */
842 .Allocatable: false, /* Allocatable */
843 .BaseClass: false,
844 offsetof(SparcRegisterClassStorage, SubClassMasks[1]) - 1 * sizeof(MCRegisterClass),
845 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 1 * sizeof(MCRegisterClass),
846 .LaneMask: LaneBitmask(0x0000000000000001),
847 .AllocationPriority: 0,
848 .GlobalPriority: false,
849 .TSFlags: 0x00, /* TSFlags */
850 .SpillStackID: 0, /* SpillStackID */
851 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
852 .CoveredBySubRegs: false, /* CoveredBySubRegs */
853 offsetof(SparcRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
854 .SuperClassesSize: 0
855 },
856 {
857 offsetof(SparcRegisterClassStorage, Regs[37]) - 2 * sizeof(MCRegisterClass),
858 offsetof(SparcRegisterClassStorage, BitSets[28]) - 2 * sizeof(MCRegisterClass),
859 .NameIdx: 217,
860 .RegSizeInBits: 32,
861 .RegsSize: 32,
862 .RegSetSize: 12,
863 .ID: SP::CoprocRegsRegClassID,
864 .CopyCost: 1, /* CopyCost */
865 .Allocatable: false, /* Allocatable */
866 .BaseClass: false,
867 offsetof(SparcRegisterClassStorage, SubClassMasks[2]) - 2 * sizeof(MCRegisterClass),
868 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[0]) - 2 * sizeof(MCRegisterClass),
869 .LaneMask: LaneBitmask(0x0000000000000001),
870 .AllocationPriority: 0,
871 .GlobalPriority: false,
872 .TSFlags: 0x00, /* TSFlags */
873 .SpillStackID: 0, /* SpillStackID */
874 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
875 .CoveredBySubRegs: false, /* CoveredBySubRegs */
876 offsetof(SparcRegisterClassStorage, SuperClasses[0]) - 2 * sizeof(MCRegisterClass),
877 .SuperClassesSize: 0
878 },
879 {
880 offsetof(SparcRegisterClassStorage, Regs[69]) - 3 * sizeof(MCRegisterClass),
881 offsetof(SparcRegisterClassStorage, BitSets[40]) - 3 * sizeof(MCRegisterClass),
882 .NameIdx: 173,
883 .RegSizeInBits: 32,
884 .RegsSize: 32,
885 .RegSetSize: 20,
886 .ID: SP::FPRegsRegClassID,
887 .CopyCost: 1, /* CopyCost */
888 .Allocatable: true, /* Allocatable */
889 .BaseClass: false,
890 offsetof(SparcRegisterClassStorage, SubClassMasks[5]) - 3 * sizeof(MCRegisterClass),
891 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[6]) - 3 * sizeof(MCRegisterClass),
892 .LaneMask: LaneBitmask(0x0000000000000001),
893 .AllocationPriority: 0,
894 .GlobalPriority: false,
895 .TSFlags: 0x00, /* TSFlags */
896 .SpillStackID: 0, /* SpillStackID */
897 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
898 .CoveredBySubRegs: false, /* CoveredBySubRegs */
899 offsetof(SparcRegisterClassStorage, SuperClasses[0]) - 3 * sizeof(MCRegisterClass),
900 .SuperClassesSize: 0
901 },
902 {
903 offsetof(SparcRegisterClassStorage, Regs[101]) - 4 * sizeof(MCRegisterClass),
904 offsetof(SparcRegisterClassStorage, BitSets[60]) - 4 * sizeof(MCRegisterClass),
905 .NameIdx: 228,
906 .RegSizeInBits: 32,
907 .RegsSize: 32,
908 .RegSetSize: 24,
909 .ID: SP::IntRegsRegClassID,
910 .CopyCost: 1, /* CopyCost */
911 .Allocatable: true, /* Allocatable */
912 .BaseClass: false,
913 offsetof(SparcRegisterClassStorage, SubClassMasks[10]) - 4 * sizeof(MCRegisterClass),
914 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[0]) - 4 * sizeof(MCRegisterClass),
915 .LaneMask: LaneBitmask(0x0000000000000001),
916 .AllocationPriority: 0,
917 .GlobalPriority: false,
918 .TSFlags: 0x00, /* TSFlags */
919 .SpillStackID: 0, /* SpillStackID */
920 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
921 .CoveredBySubRegs: false, /* CoveredBySubRegs */
922 offsetof(SparcRegisterClassStorage, SuperClasses[0]) - 4 * sizeof(MCRegisterClass),
923 .SuperClassesSize: 0
924 },
925 {
926 offsetof(SparcRegisterClassStorage, Regs[133]) - 5 * sizeof(MCRegisterClass),
927 offsetof(SparcRegisterClassStorage, BitSets[84]) - 5 * sizeof(MCRegisterClass),
928 .NameIdx: 12,
929 .RegSizeInBits: 32,
930 .RegsSize: 6,
931 .RegSetSize: 22,
932 .ID: SP::GPRIncomingArgRegClassID,
933 .CopyCost: 1, /* CopyCost */
934 .Allocatable: true, /* Allocatable */
935 .BaseClass: false,
936 offsetof(SparcRegisterClassStorage, SubClassMasks[13]) - 5 * sizeof(MCRegisterClass),
937 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass),
938 .LaneMask: LaneBitmask(0x0000000000000001),
939 .AllocationPriority: 0,
940 .GlobalPriority: false,
941 .TSFlags: 0x00, /* TSFlags */
942 .SpillStackID: 0, /* SpillStackID */
943 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
944 .CoveredBySubRegs: false, /* CoveredBySubRegs */
945 offsetof(SparcRegisterClassStorage, SuperClasses[0]) - 5 * sizeof(MCRegisterClass),
946 .SuperClassesSize: 1
947 },
948 {
949 offsetof(SparcRegisterClassStorage, Regs[139]) - 6 * sizeof(MCRegisterClass),
950 offsetof(SparcRegisterClassStorage, BitSets[106]) - 6 * sizeof(MCRegisterClass),
951 .NameIdx: 79,
952 .RegSizeInBits: 32,
953 .RegsSize: 6,
954 .RegSetSize: 24,
955 .ID: SP::GPROutgoingArgRegClassID,
956 .CopyCost: 1, /* CopyCost */
957 .Allocatable: true, /* Allocatable */
958 .BaseClass: false,
959 offsetof(SparcRegisterClassStorage, SubClassMasks[16]) - 6 * sizeof(MCRegisterClass),
960 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[0]) - 6 * sizeof(MCRegisterClass),
961 .LaneMask: LaneBitmask(0x0000000000000001),
962 .AllocationPriority: 0,
963 .GlobalPriority: false,
964 .TSFlags: 0x00, /* TSFlags */
965 .SpillStackID: 0, /* SpillStackID */
966 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
967 .CoveredBySubRegs: false, /* CoveredBySubRegs */
968 offsetof(SparcRegisterClassStorage, SuperClasses[1]) - 6 * sizeof(MCRegisterClass),
969 .SuperClassesSize: 1
970 },
971 {
972 offsetof(SparcRegisterClassStorage, Regs[145]) - 7 * sizeof(MCRegisterClass),
973 offsetof(SparcRegisterClassStorage, BitSets[130]) - 7 * sizeof(MCRegisterClass),
974 .NameIdx: 172,
975 .RegSizeInBits: 64,
976 .RegsSize: 32,
977 .RegSetSize: 16,
978 .ID: SP::DFPRegsRegClassID,
979 .CopyCost: 1, /* CopyCost */
980 .Allocatable: true, /* Allocatable */
981 .BaseClass: false,
982 offsetof(SparcRegisterClassStorage, SubClassMasks[19]) - 7 * sizeof(MCRegisterClass),
983 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[3]) - 7 * sizeof(MCRegisterClass),
984 .LaneMask: LaneBitmask(0x0000000000000003),
985 .AllocationPriority: 0,
986 .GlobalPriority: false,
987 .TSFlags: 0x00, /* TSFlags */
988 .SpillStackID: 0, /* SpillStackID */
989 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
990 .CoveredBySubRegs: false, /* CoveredBySubRegs */
991 offsetof(SparcRegisterClassStorage, SuperClasses[2]) - 7 * sizeof(MCRegisterClass),
992 .SuperClassesSize: 0
993 },
994 {
995 offsetof(SparcRegisterClassStorage, Regs[177]) - 8 * sizeof(MCRegisterClass),
996 offsetof(SparcRegisterClassStorage, BitSets[146]) - 8 * sizeof(MCRegisterClass),
997 .NameIdx: 153,
998 .RegSizeInBits: 64,
999 .RegsSize: 32,
1000 .RegSetSize: 24,
1001 .ID: SP::I64RegsRegClassID,
1002 .CopyCost: 1, /* CopyCost */
1003 .Allocatable: true, /* Allocatable */
1004 .BaseClass: false,
1005 offsetof(SparcRegisterClassStorage, SubClassMasks[22]) - 8 * sizeof(MCRegisterClass),
1006 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[0]) - 8 * sizeof(MCRegisterClass),
1007 .LaneMask: LaneBitmask(0x0000000000000001),
1008 .AllocationPriority: 0,
1009 .GlobalPriority: false,
1010 .TSFlags: 0x00, /* TSFlags */
1011 .SpillStackID: 0, /* SpillStackID */
1012 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1013 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1014 offsetof(SparcRegisterClassStorage, SuperClasses[2]) - 8 * sizeof(MCRegisterClass),
1015 .SuperClassesSize: 1
1016 },
1017 {
1018 offsetof(SparcRegisterClassStorage, Regs[209]) - 9 * sizeof(MCRegisterClass),
1019 offsetof(SparcRegisterClassStorage, BitSets[170]) - 9 * sizeof(MCRegisterClass),
1020 .NameIdx: 191,
1021 .RegSizeInBits: 64,
1022 .RegsSize: 17,
1023 .RegSetSize: 4,
1024 .ID: SP::PRRegsRegClassID,
1025 .CopyCost: 1, /* CopyCost */
1026 .Allocatable: true, /* Allocatable */
1027 .BaseClass: false,
1028 offsetof(SparcRegisterClassStorage, SubClassMasks[25]) - 9 * sizeof(MCRegisterClass),
1029 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 9 * sizeof(MCRegisterClass),
1030 .LaneMask: LaneBitmask(0x0000000000000001),
1031 .AllocationPriority: 0,
1032 .GlobalPriority: false,
1033 .TSFlags: 0x00, /* TSFlags */
1034 .SpillStackID: 0, /* SpillStackID */
1035 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1036 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1037 offsetof(SparcRegisterClassStorage, SuperClasses[3]) - 9 * sizeof(MCRegisterClass),
1038 .SuperClassesSize: 0
1039 },
1040 {
1041 offsetof(SparcRegisterClassStorage, Regs[226]) - 10 * sizeof(MCRegisterClass),
1042 offsetof(SparcRegisterClassStorage, BitSets[174]) - 10 * sizeof(MCRegisterClass),
1043 .NameIdx: 134,
1044 .RegSizeInBits: 64,
1045 .RegsSize: 16,
1046 .RegSetSize: 28,
1047 .ID: SP::CoprocPairRegClassID,
1048 .CopyCost: 1, /* CopyCost */
1049 .Allocatable: false, /* Allocatable */
1050 .BaseClass: false,
1051 offsetof(SparcRegisterClassStorage, SubClassMasks[26]) - 10 * sizeof(MCRegisterClass),
1052 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 10 * sizeof(MCRegisterClass),
1053 .LaneMask: LaneBitmask(0x0000000000000003),
1054 .AllocationPriority: 0,
1055 .GlobalPriority: false,
1056 .TSFlags: 0x00, /* TSFlags */
1057 .SpillStackID: 0, /* SpillStackID */
1058 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1059 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1060 offsetof(SparcRegisterClassStorage, SuperClasses[3]) - 10 * sizeof(MCRegisterClass),
1061 .SuperClassesSize: 0
1062 },
1063 {
1064 offsetof(SparcRegisterClassStorage, Regs[242]) - 11 * sizeof(MCRegisterClass),
1065 offsetof(SparcRegisterClassStorage, BitSets[202]) - 11 * sizeof(MCRegisterClass),
1066 .NameIdx: 145,
1067 .RegSizeInBits: 64,
1068 .RegsSize: 16,
1069 .RegSetSize: 30,
1070 .ID: SP::IntPairRegClassID,
1071 .CopyCost: 1, /* CopyCost */
1072 .Allocatable: true, /* Allocatable */
1073 .BaseClass: false,
1074 offsetof(SparcRegisterClassStorage, SubClassMasks[27]) - 11 * sizeof(MCRegisterClass),
1075 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 11 * sizeof(MCRegisterClass),
1076 .LaneMask: LaneBitmask(0x0000000000000003),
1077 .AllocationPriority: 0,
1078 .GlobalPriority: false,
1079 .TSFlags: 0x00, /* TSFlags */
1080 .SpillStackID: 0, /* SpillStackID */
1081 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1082 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1083 offsetof(SparcRegisterClassStorage, SuperClasses[3]) - 11 * sizeof(MCRegisterClass),
1084 .SuperClassesSize: 0
1085 },
1086 {
1087 offsetof(SparcRegisterClassStorage, Regs[258]) - 12 * sizeof(MCRegisterClass),
1088 offsetof(SparcRegisterClassStorage, BitSets[232]) - 12 * sizeof(MCRegisterClass),
1089 .NameIdx: 169,
1090 .RegSizeInBits: 64,
1091 .RegsSize: 16,
1092 .RegSetSize: 14,
1093 .ID: SP::LowDFPRegsRegClassID,
1094 .CopyCost: 1, /* CopyCost */
1095 .Allocatable: true, /* Allocatable */
1096 .BaseClass: false,
1097 offsetof(SparcRegisterClassStorage, SubClassMasks[28]) - 12 * sizeof(MCRegisterClass),
1098 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[3]) - 12 * sizeof(MCRegisterClass),
1099 .LaneMask: LaneBitmask(0x0000000000000003),
1100 .AllocationPriority: 0,
1101 .GlobalPriority: false,
1102 .TSFlags: 0x00, /* TSFlags */
1103 .SpillStackID: 0, /* SpillStackID */
1104 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1105 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1106 offsetof(SparcRegisterClassStorage, SuperClasses[3]) - 12 * sizeof(MCRegisterClass),
1107 .SuperClassesSize: 1
1108 },
1109 {
1110 offsetof(SparcRegisterClassStorage, Regs[274]) - 13 * sizeof(MCRegisterClass),
1111 offsetof(SparcRegisterClassStorage, BitSets[246]) - 13 * sizeof(MCRegisterClass),
1112 .NameIdx: 0,
1113 .RegSizeInBits: 64,
1114 .RegsSize: 6,
1115 .RegSetSize: 22,
1116 .ID: SP::I64Regs_and_GPRIncomingArgRegClassID,
1117 .CopyCost: 1, /* CopyCost */
1118 .Allocatable: true, /* Allocatable */
1119 .BaseClass: false,
1120 offsetof(SparcRegisterClassStorage, SubClassMasks[31]) - 13 * sizeof(MCRegisterClass),
1121 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[0]) - 13 * sizeof(MCRegisterClass),
1122 .LaneMask: LaneBitmask(0x0000000000000001),
1123 .AllocationPriority: 0,
1124 .GlobalPriority: false,
1125 .TSFlags: 0x00, /* TSFlags */
1126 .SpillStackID: 0, /* SpillStackID */
1127 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1128 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1129 offsetof(SparcRegisterClassStorage, SuperClasses[4]) - 13 * sizeof(MCRegisterClass),
1130 .SuperClassesSize: 3
1131 },
1132 {
1133 offsetof(SparcRegisterClassStorage, Regs[280]) - 14 * sizeof(MCRegisterClass),
1134 offsetof(SparcRegisterClassStorage, BitSets[268]) - 14 * sizeof(MCRegisterClass),
1135 .NameIdx: 67,
1136 .RegSizeInBits: 64,
1137 .RegsSize: 6,
1138 .RegSetSize: 24,
1139 .ID: SP::I64Regs_and_GPROutgoingArgRegClassID,
1140 .CopyCost: 1, /* CopyCost */
1141 .Allocatable: true, /* Allocatable */
1142 .BaseClass: false,
1143 offsetof(SparcRegisterClassStorage, SubClassMasks[34]) - 14 * sizeof(MCRegisterClass),
1144 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[0]) - 14 * sizeof(MCRegisterClass),
1145 .LaneMask: LaneBitmask(0x0000000000000001),
1146 .AllocationPriority: 0,
1147 .GlobalPriority: false,
1148 .TSFlags: 0x00, /* TSFlags */
1149 .SpillStackID: 0, /* SpillStackID */
1150 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1151 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1152 offsetof(SparcRegisterClassStorage, SuperClasses[7]) - 14 * sizeof(MCRegisterClass),
1153 .SuperClassesSize: 3
1154 },
1155 {
1156 offsetof(SparcRegisterClassStorage, Regs[286]) - 15 * sizeof(MCRegisterClass),
1157 offsetof(SparcRegisterClassStorage, BitSets[292]) - 15 * sizeof(MCRegisterClass),
1158 .NameIdx: 27,
1159 .RegSizeInBits: 64,
1160 .RegsSize: 3,
1161 .RegSetSize: 29,
1162 .ID: SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID,
1163 .CopyCost: 1, /* CopyCost */
1164 .Allocatable: true, /* Allocatable */
1165 .BaseClass: false,
1166 offsetof(SparcRegisterClassStorage, SubClassMasks[37]) - 15 * sizeof(MCRegisterClass),
1167 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 15 * sizeof(MCRegisterClass),
1168 .LaneMask: LaneBitmask(0x0000000000000003),
1169 .AllocationPriority: 0,
1170 .GlobalPriority: false,
1171 .TSFlags: 0x00, /* TSFlags */
1172 .SpillStackID: 0, /* SpillStackID */
1173 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1174 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1175 offsetof(SparcRegisterClassStorage, SuperClasses[10]) - 15 * sizeof(MCRegisterClass),
1176 .SuperClassesSize: 1
1177 },
1178 {
1179 offsetof(SparcRegisterClassStorage, Regs[289]) - 16 * sizeof(MCRegisterClass),
1180 offsetof(SparcRegisterClassStorage, BitSets[321]) - 16 * sizeof(MCRegisterClass),
1181 .NameIdx: 94,
1182 .RegSizeInBits: 64,
1183 .RegsSize: 3,
1184 .RegSetSize: 30,
1185 .ID: SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID,
1186 .CopyCost: 1, /* CopyCost */
1187 .Allocatable: true, /* Allocatable */
1188 .BaseClass: false,
1189 offsetof(SparcRegisterClassStorage, SubClassMasks[38]) - 16 * sizeof(MCRegisterClass),
1190 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 16 * sizeof(MCRegisterClass),
1191 .LaneMask: LaneBitmask(0x0000000000000003),
1192 .AllocationPriority: 0,
1193 .GlobalPriority: false,
1194 .TSFlags: 0x00, /* TSFlags */
1195 .SpillStackID: 0, /* SpillStackID */
1196 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1197 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1198 offsetof(SparcRegisterClassStorage, SuperClasses[11]) - 16 * sizeof(MCRegisterClass),
1199 .SuperClassesSize: 1
1200 },
1201 {
1202 offsetof(SparcRegisterClassStorage, Regs[292]) - 17 * sizeof(MCRegisterClass),
1203 offsetof(SparcRegisterClassStorage, BitSets[351]) - 17 * sizeof(MCRegisterClass),
1204 .NameIdx: 198,
1205 .RegSizeInBits: 64,
1206 .RegsSize: 1,
1207 .RegSetSize: 3,
1208 .ID: SP::PRRegs_and_ASRRegsRegClassID,
1209 .CopyCost: 1, /* CopyCost */
1210 .Allocatable: true, /* Allocatable */
1211 .BaseClass: false,
1212 offsetof(SparcRegisterClassStorage, SubClassMasks[39]) - 17 * sizeof(MCRegisterClass),
1213 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 17 * sizeof(MCRegisterClass),
1214 .LaneMask: LaneBitmask(0x0000000000000001),
1215 .AllocationPriority: 0,
1216 .GlobalPriority: false,
1217 .TSFlags: 0x00, /* TSFlags */
1218 .SpillStackID: 0, /* SpillStackID */
1219 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1220 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1221 offsetof(SparcRegisterClassStorage, SuperClasses[12]) - 17 * sizeof(MCRegisterClass),
1222 .SuperClassesSize: 2
1223 },
1224 {
1225 offsetof(SparcRegisterClassStorage, Regs[293]) - 18 * sizeof(MCRegisterClass),
1226 offsetof(SparcRegisterClassStorage, BitSets[354]) - 18 * sizeof(MCRegisterClass),
1227 .NameIdx: 183,
1228 .RegSizeInBits: 128,
1229 .RegsSize: 16,
1230 .RegSetSize: 26,
1231 .ID: SP::QFPRegsRegClassID,
1232 .CopyCost: 1, /* CopyCost */
1233 .Allocatable: true, /* Allocatable */
1234 .BaseClass: false,
1235 offsetof(SparcRegisterClassStorage, SubClassMasks[40]) - 18 * sizeof(MCRegisterClass),
1236 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 18 * sizeof(MCRegisterClass),
1237 .LaneMask: LaneBitmask(0x000000000000000F),
1238 .AllocationPriority: 0,
1239 .GlobalPriority: false,
1240 .TSFlags: 0x00, /* TSFlags */
1241 .SpillStackID: 0, /* SpillStackID */
1242 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1243 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1244 offsetof(SparcRegisterClassStorage, SuperClasses[14]) - 18 * sizeof(MCRegisterClass),
1245 .SuperClassesSize: 0
1246 },
1247 {
1248 offsetof(SparcRegisterClassStorage, Regs[309]) - 19 * sizeof(MCRegisterClass),
1249 offsetof(SparcRegisterClassStorage, BitSets[380]) - 19 * sizeof(MCRegisterClass),
1250 .NameIdx: 180,
1251 .RegSizeInBits: 128,
1252 .RegsSize: 8,
1253 .RegSetSize: 25,
1254 .ID: SP::LowQFPRegsRegClassID,
1255 .CopyCost: 1, /* CopyCost */
1256 .Allocatable: true, /* Allocatable */
1257 .BaseClass: false,
1258 offsetof(SparcRegisterClassStorage, SubClassMasks[41]) - 19 * sizeof(MCRegisterClass),
1259 offsetof(SparcRegisterClassStorage, SuperRegIdxSeqs[2]) - 19 * sizeof(MCRegisterClass),
1260 .LaneMask: LaneBitmask(0x000000000000000F),
1261 .AllocationPriority: 0,
1262 .GlobalPriority: false,
1263 .TSFlags: 0x00, /* TSFlags */
1264 .SpillStackID: 0, /* SpillStackID */
1265 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1266 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1267 offsetof(SparcRegisterClassStorage, SuperClasses[14]) - 19 * sizeof(MCRegisterClass),
1268 .SuperClassesSize: 1
1269 },
1270 },
1271 .Regs: {
1272 /* 0 */ SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3,
1273 /* 4 */ SP::Y, SP::TICK, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31,
1274 /* 37 */ SP::C0, SP::C1, SP::C2, SP::C3, SP::C4, SP::C5, SP::C6, SP::C7, SP::C8, SP::C9, SP::C10, SP::C11, SP::C12, SP::C13, SP::C14, SP::C15, SP::C16, SP::C17, SP::C18, SP::C19, SP::C20, SP::C21, SP::C22, SP::C23, SP::C24, SP::C25, SP::C26, SP::C27, SP::C28, SP::C29, SP::C30, SP::C31,
1275 /* 69 */ SP::F0, SP::F1, SP::F2, SP::F3, SP::F4, SP::F5, SP::F6, SP::F7, SP::F8, SP::F9, SP::F10, SP::F11, SP::F12, SP::F13, SP::F14, SP::F15, SP::F16, SP::F17, SP::F18, SP::F19, SP::F20, SP::F21, SP::F22, SP::F23, SP::F24, SP::F25, SP::F26, SP::F27, SP::F28, SP::F29, SP::F30, SP::F31,
1276 /* 101 */ SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1277 /* 133 */ SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1278 /* 139 */ SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5,
1279 /* 145 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31,
1280 /* 177 */ SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1281 /* 209 */ SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE, SP::GL, SP::VER,
1282 /* 226 */ SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31,
1283 /* 242 */ SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
1284 /* 258 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15,
1285 /* 274 */ SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1286 /* 280 */ SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5,
1287 /* 286 */ SP::I0_I1, SP::I2_I3, SP::I4_I5,
1288 /* 289 */ SP::O0_O1, SP::O2_O3, SP::O4_O5,
1289 /* 292 */ SP::TICK,
1290 /* 293 */ SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7, SP::Q8, SP::Q9, SP::Q10, SP::Q11, SP::Q12, SP::Q13, SP::Q14, SP::Q15,
1291 /* 309 */ SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7,
1292 },
1293 .BitSets: {
1294 /* 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1295 /* 20 */ 0x00, 0x00, 0x02, 0xfc, 0xff, 0xff, 0xff, 0x03,
1296 /* 28 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1297 /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1298 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1299 /* 84 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1300 /* 106 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1301 /* 130 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1302 /* 146 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1303 /* 170 */ 0x4e, 0xda, 0xfe, 0x02,
1304 /* 174 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1305 /* 202 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1306 /* 232 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
1307 /* 246 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1308 /* 268 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1309 /* 292 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
1310 /* 321 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
1311 /* 351 */ 0x00, 0x00, 0x02,
1312 /* 354 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1313 /* 380 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1314 },
1315 .SubClassMasks: {
1316 // 0 FCCRegs
1317 0x00000001,
1318 // 1 ASRRegs
1319 0x00020002,
1320 // 2 CoprocRegs
1321 0x00000004,
1322 0x00000400, // sub_even
1323 0x00000400, // sub_odd
1324 // 5 FPRegs
1325 0x00000008,
1326 0x00081000, // sub_even
1327 0x00081000, // sub_odd
1328 0x00080000, // sub_odd64_then_sub_even
1329 0x00080000, // sub_odd64_then_sub_odd
1330 // 10 IntRegs
1331 0x00006170,
1332 0x00018800, // sub_even
1333 0x00018800, // sub_odd
1334 // 13 GPRIncomingArg
1335 0x00002020,
1336 0x00008000, // sub_even
1337 0x00008000, // sub_odd
1338 // 16 GPROutgoingArg
1339 0x00004040,
1340 0x00010000, // sub_even
1341 0x00010000, // sub_odd
1342 // 19 DFPRegs
1343 0x00001080,
1344 0x000c0000, // sub_even64
1345 0x000c0000, // sub_odd64
1346 // 22 I64Regs
1347 0x00006100,
1348 0x00018800, // sub_even
1349 0x00018800, // sub_odd
1350 // 25 PRRegs
1351 0x00020200,
1352 // 26 CoprocPair
1353 0x00000400,
1354 // 27 IntPair
1355 0x00018800,
1356 // 28 LowDFPRegs
1357 0x00001000,
1358 0x00080000, // sub_even64
1359 0x00080000, // sub_odd64
1360 // 31 I64Regs_and_GPRIncomingArg
1361 0x00002000,
1362 0x00008000, // sub_even
1363 0x00008000, // sub_odd
1364 // 34 I64Regs_and_GPROutgoingArg
1365 0x00004000,
1366 0x00010000, // sub_even
1367 0x00010000, // sub_odd
1368 // 37 IntPair_with_sub_even_in_GPRIncomingArg
1369 0x00008000,
1370 // 38 IntPair_with_sub_even_in_GPROutgoingArg
1371 0x00010000,
1372 // 39 PRRegs_and_ASRRegs
1373 0x00020000,
1374 // 40 QFPRegs
1375 0x000c0000,
1376 // 41 LowQFPRegs
1377 0x00080000,
1378 },
1379 .SuperRegIdxSeqs: {
1380 /* 0 */ 1, 3, 0,
1381 /* 3 */ 2, 4, 0,
1382 /* 6 */ 1, 3, 5, 6, 0,
1383 },
1384 .SuperClasses: {
1385 /* 0 FCCRegs */
1386 /* 0 ASRRegs */
1387 /* 0 CoprocRegs */
1388 /* 0 FPRegs */
1389 /* 0 IntRegs */
1390 /* 0 GPRIncomingArg */ SP::IntRegsRegClassID,
1391 /* 1 GPROutgoingArg */ SP::IntRegsRegClassID,
1392 /* 2 DFPRegs */
1393 /* 2 I64Regs */ SP::IntRegsRegClassID,
1394 /* 3 PRRegs */
1395 /* 3 CoprocPair */
1396 /* 3 IntPair */
1397 /* 3 LowDFPRegs */ SP::DFPRegsRegClassID,
1398 /* 4 I64Regs_and_GPRIncomingArg */ SP::IntRegsRegClassID, SP::GPRIncomingArgRegClassID, SP::I64RegsRegClassID,
1399 /* 7 I64Regs_and_GPROutgoingArg */ SP::IntRegsRegClassID, SP::GPROutgoingArgRegClassID, SP::I64RegsRegClassID,
1400 /* 10 IntPair_with_sub_even_in_GPRIncomingArg */ SP::IntPairRegClassID,
1401 /* 11 IntPair_with_sub_even_in_GPROutgoingArg */ SP::IntPairRegClassID,
1402 /* 12 PRRegs_and_ASRRegs */ SP::ASRRegsRegClassID, SP::PRRegsRegClassID,
1403 /* 14 QFPRegs */
1404 /* 14 LowQFPRegs */ SP::QFPRegsRegClassID,
1405 }
1406};
1407
1408const MCRegisterClass &getSparcMCRegisterClass(unsigned RC) {
1409 return SparcMCRegisterClassStorage.Classes[RC];
1410}
1411
1412// SP Dwarf<->LLVM register mappings.
1413extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[] = {
1414 { .FromReg: 0U, .ToReg: SP::G0 },
1415 { .FromReg: 1U, .ToReg: SP::G1 },
1416 { .FromReg: 2U, .ToReg: SP::G2 },
1417 { .FromReg: 3U, .ToReg: SP::G3 },
1418 { .FromReg: 4U, .ToReg: SP::G4 },
1419 { .FromReg: 5U, .ToReg: SP::G5 },
1420 { .FromReg: 6U, .ToReg: SP::G6 },
1421 { .FromReg: 7U, .ToReg: SP::G7 },
1422 { .FromReg: 8U, .ToReg: SP::O0 },
1423 { .FromReg: 9U, .ToReg: SP::O1 },
1424 { .FromReg: 10U, .ToReg: SP::O2 },
1425 { .FromReg: 11U, .ToReg: SP::O3 },
1426 { .FromReg: 12U, .ToReg: SP::O4 },
1427 { .FromReg: 13U, .ToReg: SP::O5 },
1428 { .FromReg: 14U, .ToReg: SP::O6 },
1429 { .FromReg: 15U, .ToReg: SP::O7 },
1430 { .FromReg: 16U, .ToReg: SP::L0 },
1431 { .FromReg: 17U, .ToReg: SP::L1 },
1432 { .FromReg: 18U, .ToReg: SP::L2 },
1433 { .FromReg: 19U, .ToReg: SP::L3 },
1434 { .FromReg: 20U, .ToReg: SP::L4 },
1435 { .FromReg: 21U, .ToReg: SP::L5 },
1436 { .FromReg: 22U, .ToReg: SP::L6 },
1437 { .FromReg: 23U, .ToReg: SP::L7 },
1438 { .FromReg: 24U, .ToReg: SP::I0 },
1439 { .FromReg: 25U, .ToReg: SP::I1 },
1440 { .FromReg: 26U, .ToReg: SP::I2 },
1441 { .FromReg: 27U, .ToReg: SP::I3 },
1442 { .FromReg: 28U, .ToReg: SP::I4 },
1443 { .FromReg: 29U, .ToReg: SP::I5 },
1444 { .FromReg: 30U, .ToReg: SP::I6 },
1445 { .FromReg: 31U, .ToReg: SP::I7 },
1446 { .FromReg: 32U, .ToReg: SP::F0 },
1447 { .FromReg: 33U, .ToReg: SP::F1 },
1448 { .FromReg: 34U, .ToReg: SP::F2 },
1449 { .FromReg: 35U, .ToReg: SP::F3 },
1450 { .FromReg: 36U, .ToReg: SP::F4 },
1451 { .FromReg: 37U, .ToReg: SP::F5 },
1452 { .FromReg: 38U, .ToReg: SP::F6 },
1453 { .FromReg: 39U, .ToReg: SP::F7 },
1454 { .FromReg: 40U, .ToReg: SP::F8 },
1455 { .FromReg: 41U, .ToReg: SP::F9 },
1456 { .FromReg: 42U, .ToReg: SP::F10 },
1457 { .FromReg: 43U, .ToReg: SP::F11 },
1458 { .FromReg: 44U, .ToReg: SP::F12 },
1459 { .FromReg: 45U, .ToReg: SP::F13 },
1460 { .FromReg: 46U, .ToReg: SP::F14 },
1461 { .FromReg: 47U, .ToReg: SP::F15 },
1462 { .FromReg: 48U, .ToReg: SP::F16 },
1463 { .FromReg: 49U, .ToReg: SP::F17 },
1464 { .FromReg: 50U, .ToReg: SP::F18 },
1465 { .FromReg: 51U, .ToReg: SP::F19 },
1466 { .FromReg: 52U, .ToReg: SP::F20 },
1467 { .FromReg: 53U, .ToReg: SP::F21 },
1468 { .FromReg: 54U, .ToReg: SP::F22 },
1469 { .FromReg: 55U, .ToReg: SP::F23 },
1470 { .FromReg: 56U, .ToReg: SP::F24 },
1471 { .FromReg: 57U, .ToReg: SP::F25 },
1472 { .FromReg: 58U, .ToReg: SP::F26 },
1473 { .FromReg: 59U, .ToReg: SP::F27 },
1474 { .FromReg: 60U, .ToReg: SP::F28 },
1475 { .FromReg: 61U, .ToReg: SP::F29 },
1476 { .FromReg: 62U, .ToReg: SP::F30 },
1477 { .FromReg: 63U, .ToReg: SP::F31 },
1478 { .FromReg: 64U, .ToReg: SP::Y },
1479 { .FromReg: 72U, .ToReg: SP::D0 },
1480 { .FromReg: 73U, .ToReg: SP::D1 },
1481 { .FromReg: 74U, .ToReg: SP::D2 },
1482 { .FromReg: 75U, .ToReg: SP::D3 },
1483 { .FromReg: 76U, .ToReg: SP::D4 },
1484 { .FromReg: 77U, .ToReg: SP::D5 },
1485 { .FromReg: 78U, .ToReg: SP::D6 },
1486 { .FromReg: 79U, .ToReg: SP::D7 },
1487 { .FromReg: 80U, .ToReg: SP::D8 },
1488 { .FromReg: 81U, .ToReg: SP::D9 },
1489 { .FromReg: 82U, .ToReg: SP::D10 },
1490 { .FromReg: 83U, .ToReg: SP::D11 },
1491 { .FromReg: 84U, .ToReg: SP::D12 },
1492 { .FromReg: 85U, .ToReg: SP::D13 },
1493 { .FromReg: 86U, .ToReg: SP::D14 },
1494 { .FromReg: 87U, .ToReg: SP::D15 },
1495};
1496extern const unsigned SPDwarfFlavour0Dwarf2LSize = std::size(SPDwarfFlavour0Dwarf2L);
1497
1498extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[] = {
1499 { .FromReg: 0U, .ToReg: SP::G0 },
1500 { .FromReg: 1U, .ToReg: SP::G1 },
1501 { .FromReg: 2U, .ToReg: SP::G2 },
1502 { .FromReg: 3U, .ToReg: SP::G3 },
1503 { .FromReg: 4U, .ToReg: SP::G4 },
1504 { .FromReg: 5U, .ToReg: SP::G5 },
1505 { .FromReg: 6U, .ToReg: SP::G6 },
1506 { .FromReg: 7U, .ToReg: SP::G7 },
1507 { .FromReg: 8U, .ToReg: SP::O0 },
1508 { .FromReg: 9U, .ToReg: SP::O1 },
1509 { .FromReg: 10U, .ToReg: SP::O2 },
1510 { .FromReg: 11U, .ToReg: SP::O3 },
1511 { .FromReg: 12U, .ToReg: SP::O4 },
1512 { .FromReg: 13U, .ToReg: SP::O5 },
1513 { .FromReg: 14U, .ToReg: SP::O6 },
1514 { .FromReg: 15U, .ToReg: SP::O7 },
1515 { .FromReg: 16U, .ToReg: SP::L0 },
1516 { .FromReg: 17U, .ToReg: SP::L1 },
1517 { .FromReg: 18U, .ToReg: SP::L2 },
1518 { .FromReg: 19U, .ToReg: SP::L3 },
1519 { .FromReg: 20U, .ToReg: SP::L4 },
1520 { .FromReg: 21U, .ToReg: SP::L5 },
1521 { .FromReg: 22U, .ToReg: SP::L6 },
1522 { .FromReg: 23U, .ToReg: SP::L7 },
1523 { .FromReg: 24U, .ToReg: SP::I0 },
1524 { .FromReg: 25U, .ToReg: SP::I1 },
1525 { .FromReg: 26U, .ToReg: SP::I2 },
1526 { .FromReg: 27U, .ToReg: SP::I3 },
1527 { .FromReg: 28U, .ToReg: SP::I4 },
1528 { .FromReg: 29U, .ToReg: SP::I5 },
1529 { .FromReg: 30U, .ToReg: SP::I6 },
1530 { .FromReg: 31U, .ToReg: SP::I7 },
1531 { .FromReg: 32U, .ToReg: SP::F0 },
1532 { .FromReg: 33U, .ToReg: SP::F1 },
1533 { .FromReg: 34U, .ToReg: SP::F2 },
1534 { .FromReg: 35U, .ToReg: SP::F3 },
1535 { .FromReg: 36U, .ToReg: SP::F4 },
1536 { .FromReg: 37U, .ToReg: SP::F5 },
1537 { .FromReg: 38U, .ToReg: SP::F6 },
1538 { .FromReg: 39U, .ToReg: SP::F7 },
1539 { .FromReg: 40U, .ToReg: SP::F8 },
1540 { .FromReg: 41U, .ToReg: SP::F9 },
1541 { .FromReg: 42U, .ToReg: SP::F10 },
1542 { .FromReg: 43U, .ToReg: SP::F11 },
1543 { .FromReg: 44U, .ToReg: SP::F12 },
1544 { .FromReg: 45U, .ToReg: SP::F13 },
1545 { .FromReg: 46U, .ToReg: SP::F14 },
1546 { .FromReg: 47U, .ToReg: SP::F15 },
1547 { .FromReg: 48U, .ToReg: SP::F16 },
1548 { .FromReg: 49U, .ToReg: SP::F17 },
1549 { .FromReg: 50U, .ToReg: SP::F18 },
1550 { .FromReg: 51U, .ToReg: SP::F19 },
1551 { .FromReg: 52U, .ToReg: SP::F20 },
1552 { .FromReg: 53U, .ToReg: SP::F21 },
1553 { .FromReg: 54U, .ToReg: SP::F22 },
1554 { .FromReg: 55U, .ToReg: SP::F23 },
1555 { .FromReg: 56U, .ToReg: SP::F24 },
1556 { .FromReg: 57U, .ToReg: SP::F25 },
1557 { .FromReg: 58U, .ToReg: SP::F26 },
1558 { .FromReg: 59U, .ToReg: SP::F27 },
1559 { .FromReg: 60U, .ToReg: SP::F28 },
1560 { .FromReg: 61U, .ToReg: SP::F29 },
1561 { .FromReg: 62U, .ToReg: SP::F30 },
1562 { .FromReg: 63U, .ToReg: SP::F31 },
1563 { .FromReg: 64U, .ToReg: SP::Y },
1564 { .FromReg: 72U, .ToReg: SP::D0 },
1565 { .FromReg: 73U, .ToReg: SP::D1 },
1566 { .FromReg: 74U, .ToReg: SP::D2 },
1567 { .FromReg: 75U, .ToReg: SP::D3 },
1568 { .FromReg: 76U, .ToReg: SP::D4 },
1569 { .FromReg: 77U, .ToReg: SP::D5 },
1570 { .FromReg: 78U, .ToReg: SP::D6 },
1571 { .FromReg: 79U, .ToReg: SP::D7 },
1572 { .FromReg: 80U, .ToReg: SP::D8 },
1573 { .FromReg: 81U, .ToReg: SP::D9 },
1574 { .FromReg: 82U, .ToReg: SP::D10 },
1575 { .FromReg: 83U, .ToReg: SP::D11 },
1576 { .FromReg: 84U, .ToReg: SP::D12 },
1577 { .FromReg: 85U, .ToReg: SP::D13 },
1578 { .FromReg: 86U, .ToReg: SP::D14 },
1579 { .FromReg: 87U, .ToReg: SP::D15 },
1580};
1581extern const unsigned SPEHFlavour0Dwarf2LSize = std::size(SPEHFlavour0Dwarf2L);
1582
1583extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[] = {
1584 { .FromReg: SP::Y, .ToReg: 64U },
1585 { .FromReg: SP::D0, .ToReg: 72U },
1586 { .FromReg: SP::D1, .ToReg: 73U },
1587 { .FromReg: SP::D2, .ToReg: 74U },
1588 { .FromReg: SP::D3, .ToReg: 75U },
1589 { .FromReg: SP::D4, .ToReg: 76U },
1590 { .FromReg: SP::D5, .ToReg: 77U },
1591 { .FromReg: SP::D6, .ToReg: 78U },
1592 { .FromReg: SP::D7, .ToReg: 79U },
1593 { .FromReg: SP::D8, .ToReg: 80U },
1594 { .FromReg: SP::D9, .ToReg: 81U },
1595 { .FromReg: SP::D10, .ToReg: 82U },
1596 { .FromReg: SP::D11, .ToReg: 83U },
1597 { .FromReg: SP::D12, .ToReg: 84U },
1598 { .FromReg: SP::D13, .ToReg: 85U },
1599 { .FromReg: SP::D14, .ToReg: 86U },
1600 { .FromReg: SP::D15, .ToReg: 87U },
1601 { .FromReg: SP::F0, .ToReg: 32U },
1602 { .FromReg: SP::F1, .ToReg: 33U },
1603 { .FromReg: SP::F2, .ToReg: 34U },
1604 { .FromReg: SP::F3, .ToReg: 35U },
1605 { .FromReg: SP::F4, .ToReg: 36U },
1606 { .FromReg: SP::F5, .ToReg: 37U },
1607 { .FromReg: SP::F6, .ToReg: 38U },
1608 { .FromReg: SP::F7, .ToReg: 39U },
1609 { .FromReg: SP::F8, .ToReg: 40U },
1610 { .FromReg: SP::F9, .ToReg: 41U },
1611 { .FromReg: SP::F10, .ToReg: 42U },
1612 { .FromReg: SP::F11, .ToReg: 43U },
1613 { .FromReg: SP::F12, .ToReg: 44U },
1614 { .FromReg: SP::F13, .ToReg: 45U },
1615 { .FromReg: SP::F14, .ToReg: 46U },
1616 { .FromReg: SP::F15, .ToReg: 47U },
1617 { .FromReg: SP::F16, .ToReg: 48U },
1618 { .FromReg: SP::F17, .ToReg: 49U },
1619 { .FromReg: SP::F18, .ToReg: 50U },
1620 { .FromReg: SP::F19, .ToReg: 51U },
1621 { .FromReg: SP::F20, .ToReg: 52U },
1622 { .FromReg: SP::F21, .ToReg: 53U },
1623 { .FromReg: SP::F22, .ToReg: 54U },
1624 { .FromReg: SP::F23, .ToReg: 55U },
1625 { .FromReg: SP::F24, .ToReg: 56U },
1626 { .FromReg: SP::F25, .ToReg: 57U },
1627 { .FromReg: SP::F26, .ToReg: 58U },
1628 { .FromReg: SP::F27, .ToReg: 59U },
1629 { .FromReg: SP::F28, .ToReg: 60U },
1630 { .FromReg: SP::F29, .ToReg: 61U },
1631 { .FromReg: SP::F30, .ToReg: 62U },
1632 { .FromReg: SP::F31, .ToReg: 63U },
1633 { .FromReg: SP::G0, .ToReg: 0U },
1634 { .FromReg: SP::G1, .ToReg: 1U },
1635 { .FromReg: SP::G2, .ToReg: 2U },
1636 { .FromReg: SP::G3, .ToReg: 3U },
1637 { .FromReg: SP::G4, .ToReg: 4U },
1638 { .FromReg: SP::G5, .ToReg: 5U },
1639 { .FromReg: SP::G6, .ToReg: 6U },
1640 { .FromReg: SP::G7, .ToReg: 7U },
1641 { .FromReg: SP::I0, .ToReg: 24U },
1642 { .FromReg: SP::I1, .ToReg: 25U },
1643 { .FromReg: SP::I2, .ToReg: 26U },
1644 { .FromReg: SP::I3, .ToReg: 27U },
1645 { .FromReg: SP::I4, .ToReg: 28U },
1646 { .FromReg: SP::I5, .ToReg: 29U },
1647 { .FromReg: SP::I6, .ToReg: 30U },
1648 { .FromReg: SP::I7, .ToReg: 31U },
1649 { .FromReg: SP::L0, .ToReg: 16U },
1650 { .FromReg: SP::L1, .ToReg: 17U },
1651 { .FromReg: SP::L2, .ToReg: 18U },
1652 { .FromReg: SP::L3, .ToReg: 19U },
1653 { .FromReg: SP::L4, .ToReg: 20U },
1654 { .FromReg: SP::L5, .ToReg: 21U },
1655 { .FromReg: SP::L6, .ToReg: 22U },
1656 { .FromReg: SP::L7, .ToReg: 23U },
1657 { .FromReg: SP::O0, .ToReg: 8U },
1658 { .FromReg: SP::O1, .ToReg: 9U },
1659 { .FromReg: SP::O2, .ToReg: 10U },
1660 { .FromReg: SP::O3, .ToReg: 11U },
1661 { .FromReg: SP::O4, .ToReg: 12U },
1662 { .FromReg: SP::O5, .ToReg: 13U },
1663 { .FromReg: SP::O6, .ToReg: 14U },
1664 { .FromReg: SP::O7, .ToReg: 15U },
1665};
1666extern const unsigned SPDwarfFlavour0L2DwarfSize = std::size(SPDwarfFlavour0L2Dwarf);
1667
1668extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[] = {
1669 { .FromReg: SP::Y, .ToReg: 64U },
1670 { .FromReg: SP::D0, .ToReg: 72U },
1671 { .FromReg: SP::D1, .ToReg: 73U },
1672 { .FromReg: SP::D2, .ToReg: 74U },
1673 { .FromReg: SP::D3, .ToReg: 75U },
1674 { .FromReg: SP::D4, .ToReg: 76U },
1675 { .FromReg: SP::D5, .ToReg: 77U },
1676 { .FromReg: SP::D6, .ToReg: 78U },
1677 { .FromReg: SP::D7, .ToReg: 79U },
1678 { .FromReg: SP::D8, .ToReg: 80U },
1679 { .FromReg: SP::D9, .ToReg: 81U },
1680 { .FromReg: SP::D10, .ToReg: 82U },
1681 { .FromReg: SP::D11, .ToReg: 83U },
1682 { .FromReg: SP::D12, .ToReg: 84U },
1683 { .FromReg: SP::D13, .ToReg: 85U },
1684 { .FromReg: SP::D14, .ToReg: 86U },
1685 { .FromReg: SP::D15, .ToReg: 87U },
1686 { .FromReg: SP::F0, .ToReg: 32U },
1687 { .FromReg: SP::F1, .ToReg: 33U },
1688 { .FromReg: SP::F2, .ToReg: 34U },
1689 { .FromReg: SP::F3, .ToReg: 35U },
1690 { .FromReg: SP::F4, .ToReg: 36U },
1691 { .FromReg: SP::F5, .ToReg: 37U },
1692 { .FromReg: SP::F6, .ToReg: 38U },
1693 { .FromReg: SP::F7, .ToReg: 39U },
1694 { .FromReg: SP::F8, .ToReg: 40U },
1695 { .FromReg: SP::F9, .ToReg: 41U },
1696 { .FromReg: SP::F10, .ToReg: 42U },
1697 { .FromReg: SP::F11, .ToReg: 43U },
1698 { .FromReg: SP::F12, .ToReg: 44U },
1699 { .FromReg: SP::F13, .ToReg: 45U },
1700 { .FromReg: SP::F14, .ToReg: 46U },
1701 { .FromReg: SP::F15, .ToReg: 47U },
1702 { .FromReg: SP::F16, .ToReg: 48U },
1703 { .FromReg: SP::F17, .ToReg: 49U },
1704 { .FromReg: SP::F18, .ToReg: 50U },
1705 { .FromReg: SP::F19, .ToReg: 51U },
1706 { .FromReg: SP::F20, .ToReg: 52U },
1707 { .FromReg: SP::F21, .ToReg: 53U },
1708 { .FromReg: SP::F22, .ToReg: 54U },
1709 { .FromReg: SP::F23, .ToReg: 55U },
1710 { .FromReg: SP::F24, .ToReg: 56U },
1711 { .FromReg: SP::F25, .ToReg: 57U },
1712 { .FromReg: SP::F26, .ToReg: 58U },
1713 { .FromReg: SP::F27, .ToReg: 59U },
1714 { .FromReg: SP::F28, .ToReg: 60U },
1715 { .FromReg: SP::F29, .ToReg: 61U },
1716 { .FromReg: SP::F30, .ToReg: 62U },
1717 { .FromReg: SP::F31, .ToReg: 63U },
1718 { .FromReg: SP::G0, .ToReg: 0U },
1719 { .FromReg: SP::G1, .ToReg: 1U },
1720 { .FromReg: SP::G2, .ToReg: 2U },
1721 { .FromReg: SP::G3, .ToReg: 3U },
1722 { .FromReg: SP::G4, .ToReg: 4U },
1723 { .FromReg: SP::G5, .ToReg: 5U },
1724 { .FromReg: SP::G6, .ToReg: 6U },
1725 { .FromReg: SP::G7, .ToReg: 7U },
1726 { .FromReg: SP::I0, .ToReg: 24U },
1727 { .FromReg: SP::I1, .ToReg: 25U },
1728 { .FromReg: SP::I2, .ToReg: 26U },
1729 { .FromReg: SP::I3, .ToReg: 27U },
1730 { .FromReg: SP::I4, .ToReg: 28U },
1731 { .FromReg: SP::I5, .ToReg: 29U },
1732 { .FromReg: SP::I6, .ToReg: 30U },
1733 { .FromReg: SP::I7, .ToReg: 31U },
1734 { .FromReg: SP::L0, .ToReg: 16U },
1735 { .FromReg: SP::L1, .ToReg: 17U },
1736 { .FromReg: SP::L2, .ToReg: 18U },
1737 { .FromReg: SP::L3, .ToReg: 19U },
1738 { .FromReg: SP::L4, .ToReg: 20U },
1739 { .FromReg: SP::L5, .ToReg: 21U },
1740 { .FromReg: SP::L6, .ToReg: 22U },
1741 { .FromReg: SP::L7, .ToReg: 23U },
1742 { .FromReg: SP::O0, .ToReg: 8U },
1743 { .FromReg: SP::O1, .ToReg: 9U },
1744 { .FromReg: SP::O2, .ToReg: 10U },
1745 { .FromReg: SP::O3, .ToReg: 11U },
1746 { .FromReg: SP::O4, .ToReg: 12U },
1747 { .FromReg: SP::O5, .ToReg: 13U },
1748 { .FromReg: SP::O6, .ToReg: 14U },
1749 { .FromReg: SP::O7, .ToReg: 15U },
1750};
1751extern const unsigned SPEHFlavour0L2DwarfSize = std::size(SPEHFlavour0L2Dwarf);
1752
1753extern const uint16_t SparcRegEncodingTable[] = {
1754 0,
1755 11,
1756 10,
1757 12,
1758 0,
1759 0,
1760 9,
1761 0,
1762 0,
1763 16,
1764 0,
1765 13,
1766 8,
1767 0,
1768 6,
1769 5,
1770 0,
1771 4,
1772 7,
1773 1,
1774 0,
1775 2,
1776 3,
1777 31,
1778 0,
1779 14,
1780 0,
1781 1,
1782 2,
1783 3,
1784 4,
1785 5,
1786 6,
1787 7,
1788 8,
1789 9,
1790 10,
1791 11,
1792 12,
1793 13,
1794 14,
1795 15,
1796 16,
1797 17,
1798 18,
1799 19,
1800 20,
1801 21,
1802 22,
1803 23,
1804 24,
1805 25,
1806 26,
1807 27,
1808 28,
1809 29,
1810 30,
1811 31,
1812 0,
1813 1,
1814 2,
1815 3,
1816 4,
1817 5,
1818 6,
1819 7,
1820 8,
1821 9,
1822 10,
1823 11,
1824 12,
1825 13,
1826 14,
1827 15,
1828 16,
1829 17,
1830 18,
1831 19,
1832 20,
1833 21,
1834 22,
1835 23,
1836 24,
1837 25,
1838 26,
1839 27,
1840 28,
1841 29,
1842 30,
1843 31,
1844 0,
1845 2,
1846 4,
1847 6,
1848 8,
1849 10,
1850 12,
1851 14,
1852 16,
1853 18,
1854 20,
1855 22,
1856 24,
1857 26,
1858 28,
1859 30,
1860 1,
1861 3,
1862 5,
1863 7,
1864 9,
1865 11,
1866 13,
1867 15,
1868 17,
1869 19,
1870 21,
1871 23,
1872 25,
1873 27,
1874 29,
1875 31,
1876 0,
1877 1,
1878 2,
1879 3,
1880 4,
1881 5,
1882 6,
1883 7,
1884 8,
1885 9,
1886 10,
1887 11,
1888 12,
1889 13,
1890 14,
1891 15,
1892 16,
1893 17,
1894 18,
1895 19,
1896 20,
1897 21,
1898 22,
1899 23,
1900 24,
1901 25,
1902 26,
1903 27,
1904 28,
1905 29,
1906 30,
1907 31,
1908 0,
1909 1,
1910 2,
1911 3,
1912 0,
1913 1,
1914 2,
1915 3,
1916 4,
1917 5,
1918 6,
1919 7,
1920 24,
1921 25,
1922 26,
1923 27,
1924 28,
1925 29,
1926 30,
1927 31,
1928 16,
1929 17,
1930 18,
1931 19,
1932 20,
1933 21,
1934 22,
1935 23,
1936 8,
1937 9,
1938 10,
1939 11,
1940 12,
1941 13,
1942 14,
1943 15,
1944 0,
1945 4,
1946 8,
1947 12,
1948 16,
1949 20,
1950 24,
1951 28,
1952 1,
1953 5,
1954 9,
1955 13,
1956 17,
1957 21,
1958 25,
1959 29,
1960 0,
1961 2,
1962 4,
1963 6,
1964 8,
1965 10,
1966 12,
1967 14,
1968 16,
1969 18,
1970 20,
1971 22,
1972 24,
1973 26,
1974 28,
1975 30,
1976 0,
1977 2,
1978 4,
1979 6,
1980 24,
1981 26,
1982 28,
1983 30,
1984 16,
1985 18,
1986 20,
1987 22,
1988 8,
1989 10,
1990 12,
1991 14,
1992};
1993static inline void InitSparcMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1994 RI->InitMCRegisterInfo(D: SparcRegDesc, NR: 238, RA, PC, C: SparcMCRegisterClassStorage.Classes, NC: 20, RURoots: SparcRegUnitRoots, NRU: 173, DL: SparcRegDiffLists, RUMS: SparcLaneMaskLists, Strings: SparcRegStrings, ClassStrings: SparcRegClassStrings, SubIndices: SparcSubRegIdxLists, NumIndices: 7,
1995RET: SparcRegEncodingTable, RUI: nullptr);
1996
1997 switch (DwarfFlavour) {
1998 default:
1999 llvm_unreachable("Unknown DWARF flavour");
2000 case 0:
2001 RI->mapDwarfRegsToLLVMRegs(Map: SPDwarfFlavour0Dwarf2L, Size: SPDwarfFlavour0Dwarf2LSize, isEH: false);
2002 break;
2003 }
2004 switch (EHFlavour) {
2005 default:
2006 llvm_unreachable("Unknown DWARF flavour");
2007 case 0:
2008 RI->mapDwarfRegsToLLVMRegs(Map: SPEHFlavour0Dwarf2L, Size: SPEHFlavour0Dwarf2LSize, isEH: true);
2009 break;
2010 }
2011 switch (DwarfFlavour) {
2012 default:
2013 llvm_unreachable("Unknown DWARF flavour");
2014 case 0:
2015 RI->mapLLVMRegsToDwarfRegs(Map: SPDwarfFlavour0L2Dwarf, Size: SPDwarfFlavour0L2DwarfSize, isEH: false);
2016 break;
2017 }
2018 switch (EHFlavour) {
2019 default:
2020 llvm_unreachable("Unknown DWARF flavour");
2021 case 0:
2022 RI->mapLLVMRegsToDwarfRegs(Map: SPEHFlavour0L2Dwarf, Size: SPEHFlavour0L2DwarfSize, isEH: true);
2023 break;
2024 }
2025}
2026
2027
2028} // namespace llvm
2029