| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* MC Register Information *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | namespace llvm { |
| 10 | |
| 11 | extern const int16_t VERegDiffLists[] = { |
| 12 | /* 0 */ 64, -192, 0, |
| 13 | /* 3 */ 128, -192, 0, |
| 14 | /* 6 */ 64, -191, 0, |
| 15 | /* 9 */ 128, -191, 0, |
| 16 | /* 12 */ 64, -190, 0, |
| 17 | /* 15 */ 128, -190, 0, |
| 18 | /* 18 */ 64, -189, 0, |
| 19 | /* 21 */ 128, -189, 0, |
| 20 | /* 24 */ 64, -188, 0, |
| 21 | /* 27 */ 128, -188, 0, |
| 22 | /* 30 */ 64, -187, 0, |
| 23 | /* 33 */ 128, -187, 0, |
| 24 | /* 36 */ 64, -186, 0, |
| 25 | /* 39 */ 128, -186, 0, |
| 26 | /* 42 */ 64, -185, 0, |
| 27 | /* 45 */ 128, -185, 0, |
| 28 | /* 48 */ 64, -184, 0, |
| 29 | /* 51 */ 128, -184, 0, |
| 30 | /* 54 */ 64, -183, 0, |
| 31 | /* 57 */ 128, -183, 0, |
| 32 | /* 60 */ 64, -182, 0, |
| 33 | /* 63 */ 128, -182, 0, |
| 34 | /* 66 */ 64, -181, 0, |
| 35 | /* 69 */ 128, -181, 0, |
| 36 | /* 72 */ 64, -180, 0, |
| 37 | /* 75 */ 128, -180, 0, |
| 38 | /* 78 */ 64, -179, 0, |
| 39 | /* 81 */ 128, -179, 0, |
| 40 | /* 84 */ 64, -178, 0, |
| 41 | /* 87 */ 128, -178, 0, |
| 42 | /* 90 */ 64, -177, 0, |
| 43 | /* 93 */ 128, -177, 0, |
| 44 | /* 96 */ 64, -176, 0, |
| 45 | /* 99 */ 128, -176, 0, |
| 46 | /* 102 */ 64, -175, 0, |
| 47 | /* 105 */ 128, -175, 0, |
| 48 | /* 108 */ 64, -174, 0, |
| 49 | /* 111 */ 128, -174, 0, |
| 50 | /* 114 */ 64, -173, 0, |
| 51 | /* 117 */ 128, -173, 0, |
| 52 | /* 120 */ 64, -172, 0, |
| 53 | /* 123 */ 128, -172, 0, |
| 54 | /* 126 */ 64, -171, 0, |
| 55 | /* 129 */ 128, -171, 0, |
| 56 | /* 132 */ 64, -170, 0, |
| 57 | /* 135 */ 128, -170, 0, |
| 58 | /* 138 */ 64, -169, 0, |
| 59 | /* 141 */ 128, -169, 0, |
| 60 | /* 144 */ 64, -168, 0, |
| 61 | /* 147 */ 128, -168, 0, |
| 62 | /* 150 */ 64, -167, 0, |
| 63 | /* 153 */ 128, -167, 0, |
| 64 | /* 156 */ 64, -166, 0, |
| 65 | /* 159 */ 128, -166, 0, |
| 66 | /* 162 */ 64, -165, 0, |
| 67 | /* 165 */ 128, -165, 0, |
| 68 | /* 168 */ 64, -164, 0, |
| 69 | /* 171 */ 128, -164, 0, |
| 70 | /* 174 */ 64, -163, 0, |
| 71 | /* 177 */ 128, -163, 0, |
| 72 | /* 180 */ 64, -162, 0, |
| 73 | /* 183 */ 128, -162, 0, |
| 74 | /* 186 */ 64, -161, 0, |
| 75 | /* 189 */ 128, -161, 0, |
| 76 | /* 192 */ 64, -160, 0, |
| 77 | /* 195 */ 128, -160, 0, |
| 78 | /* 198 */ 160, -64, -64, 129, -64, -64, 0, |
| 79 | /* 205 */ 161, -64, -64, 129, -64, -64, 0, |
| 80 | /* 212 */ 162, -64, -64, 129, -64, -64, 0, |
| 81 | /* 219 */ 163, -64, -64, 129, -64, -64, 0, |
| 82 | /* 226 */ 164, -64, -64, 129, -64, -64, 0, |
| 83 | /* 233 */ 165, -64, -64, 129, -64, -64, 0, |
| 84 | /* 240 */ 166, -64, -64, 129, -64, -64, 0, |
| 85 | /* 247 */ 167, -64, -64, 129, -64, -64, 0, |
| 86 | /* 254 */ 168, -64, -64, 129, -64, -64, 0, |
| 87 | /* 261 */ 169, -64, -64, 129, -64, -64, 0, |
| 88 | /* 268 */ 170, -64, -64, 129, -64, -64, 0, |
| 89 | /* 275 */ 171, -64, -64, 129, -64, -64, 0, |
| 90 | /* 282 */ 172, -64, -64, 129, -64, -64, 0, |
| 91 | /* 289 */ 173, -64, -64, 129, -64, -64, 0, |
| 92 | /* 296 */ 174, -64, -64, 129, -64, -64, 0, |
| 93 | /* 303 */ 175, -64, -64, 129, -64, -64, 0, |
| 94 | /* 310 */ 176, -64, -64, 129, -64, -64, 0, |
| 95 | /* 317 */ 177, -64, -64, 129, -64, -64, 0, |
| 96 | /* 324 */ 178, -64, -64, 129, -64, -64, 0, |
| 97 | /* 331 */ 179, -64, -64, 129, -64, -64, 0, |
| 98 | /* 338 */ 180, -64, -64, 129, -64, -64, 0, |
| 99 | /* 345 */ 181, -64, -64, 129, -64, -64, 0, |
| 100 | /* 352 */ 182, -64, -64, 129, -64, -64, 0, |
| 101 | /* 359 */ 183, -64, -64, 129, -64, -64, 0, |
| 102 | /* 366 */ 184, -64, -64, 129, -64, -64, 0, |
| 103 | /* 373 */ 185, -64, -64, 129, -64, -64, 0, |
| 104 | /* 380 */ 186, -64, -64, 129, -64, -64, 0, |
| 105 | /* 387 */ 187, -64, -64, 129, -64, -64, 0, |
| 106 | /* 394 */ 188, -64, -64, 129, -64, -64, 0, |
| 107 | /* 401 */ 189, -64, -64, 129, -64, -64, 0, |
| 108 | /* 408 */ 190, -64, -64, 129, -64, -64, 0, |
| 109 | /* 415 */ 191, -64, -64, 129, -64, -64, 0, |
| 110 | /* 422 */ -15, 1, 0, |
| 111 | /* 425 */ -14, 1, 0, |
| 112 | /* 428 */ -13, 1, 0, |
| 113 | /* 431 */ -12, 1, 0, |
| 114 | /* 434 */ -11, 1, 0, |
| 115 | /* 437 */ -10, 1, 0, |
| 116 | /* 440 */ -9, 1, 0, |
| 117 | /* 443 */ 1, 1, 1, 1, 1, 0, |
| 118 | /* 449 */ 8, 0, |
| 119 | /* 451 */ 9, 0, |
| 120 | /* 453 */ 10, 0, |
| 121 | /* 455 */ 11, 0, |
| 122 | /* 457 */ 12, 0, |
| 123 | /* 459 */ 13, 0, |
| 124 | /* 461 */ 14, 0, |
| 125 | /* 463 */ 15, 0, |
| 126 | }; |
| 127 | |
| 128 | extern const LaneBitmask VELaneMaskLists[] = { |
| 129 | /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000000), LaneBitmask(0x0000000000000001), |
| 130 | /* 3 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), |
| 131 | /* 5 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000000), LaneBitmask(0x0000000000000010), |
| 132 | /* 11 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), |
| 133 | }; |
| 134 | |
| 135 | extern const uint16_t VESubRegIdxLists[] = { |
| 136 | /* 0 */ 3, 2, |
| 137 | /* 2 */ 5, 6, |
| 138 | /* 4 */ 1, 3, 2, 4, 8, 7, |
| 139 | }; |
| 140 | |
| 141 | |
| 142 | #ifdef __GNUC__ |
| 143 | #pragma GCC diagnostic push |
| 144 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 145 | #endif |
| 146 | extern const char VERegStrings[] = { |
| 147 | /* 0 */ "PMC10\000" |
| 148 | /* 6 */ "SF10\000" |
| 149 | /* 11 */ "VM10\000" |
| 150 | /* 16 */ "Q10\000" |
| 151 | /* 20 */ "V10\000" |
| 152 | /* 24 */ "SW10\000" |
| 153 | /* 29 */ "SX10\000" |
| 154 | /* 34 */ "SF20\000" |
| 155 | /* 39 */ "Q20\000" |
| 156 | /* 43 */ "V20\000" |
| 157 | /* 47 */ "SW20\000" |
| 158 | /* 52 */ "SX20\000" |
| 159 | /* 57 */ "SF30\000" |
| 160 | /* 62 */ "Q30\000" |
| 161 | /* 66 */ "V30\000" |
| 162 | /* 70 */ "SW30\000" |
| 163 | /* 75 */ "SX30\000" |
| 164 | /* 80 */ "SF40\000" |
| 165 | /* 85 */ "V40\000" |
| 166 | /* 89 */ "SW40\000" |
| 167 | /* 94 */ "SX40\000" |
| 168 | /* 99 */ "SF50\000" |
| 169 | /* 104 */ "V50\000" |
| 170 | /* 108 */ "SW50\000" |
| 171 | /* 113 */ "SX50\000" |
| 172 | /* 118 */ "SF60\000" |
| 173 | /* 123 */ "V60\000" |
| 174 | /* 127 */ "SW60\000" |
| 175 | /* 132 */ "SX60\000" |
| 176 | /* 137 */ "PMC0\000" |
| 177 | /* 142 */ "SF0\000" |
| 178 | /* 146 */ "VM0\000" |
| 179 | /* 150 */ "VMP0\000" |
| 180 | /* 155 */ "Q0\000" |
| 181 | /* 158 */ "PMCR0\000" |
| 182 | /* 164 */ "V0\000" |
| 183 | /* 167 */ "SW0\000" |
| 184 | /* 171 */ "SX0\000" |
| 185 | /* 175 */ "PMC11\000" |
| 186 | /* 181 */ "SF11\000" |
| 187 | /* 186 */ "VM11\000" |
| 188 | /* 191 */ "Q11\000" |
| 189 | /* 195 */ "V11\000" |
| 190 | /* 199 */ "SW11\000" |
| 191 | /* 204 */ "SX11\000" |
| 192 | /* 209 */ "SF21\000" |
| 193 | /* 214 */ "Q21\000" |
| 194 | /* 218 */ "V21\000" |
| 195 | /* 222 */ "SW21\000" |
| 196 | /* 227 */ "SX21\000" |
| 197 | /* 232 */ "SF31\000" |
| 198 | /* 237 */ "Q31\000" |
| 199 | /* 241 */ "V31\000" |
| 200 | /* 245 */ "SW31\000" |
| 201 | /* 250 */ "SX31\000" |
| 202 | /* 255 */ "SF41\000" |
| 203 | /* 260 */ "V41\000" |
| 204 | /* 264 */ "SW41\000" |
| 205 | /* 269 */ "SX41\000" |
| 206 | /* 274 */ "SF51\000" |
| 207 | /* 279 */ "V51\000" |
| 208 | /* 283 */ "SW51\000" |
| 209 | /* 288 */ "SX51\000" |
| 210 | /* 293 */ "SF61\000" |
| 211 | /* 298 */ "V61\000" |
| 212 | /* 302 */ "SW61\000" |
| 213 | /* 307 */ "SX61\000" |
| 214 | /* 312 */ "PMC1\000" |
| 215 | /* 317 */ "SF1\000" |
| 216 | /* 321 */ "VM1\000" |
| 217 | /* 325 */ "VMP1\000" |
| 218 | /* 330 */ "Q1\000" |
| 219 | /* 333 */ "PMCR1\000" |
| 220 | /* 339 */ "V1\000" |
| 221 | /* 342 */ "SW1\000" |
| 222 | /* 346 */ "SX1\000" |
| 223 | /* 350 */ "PMC12\000" |
| 224 | /* 356 */ "SF12\000" |
| 225 | /* 361 */ "VM12\000" |
| 226 | /* 366 */ "Q12\000" |
| 227 | /* 370 */ "V12\000" |
| 228 | /* 374 */ "SW12\000" |
| 229 | /* 379 */ "SX12\000" |
| 230 | /* 384 */ "SF22\000" |
| 231 | /* 389 */ "Q22\000" |
| 232 | /* 393 */ "V22\000" |
| 233 | /* 397 */ "SW22\000" |
| 234 | /* 402 */ "SX22\000" |
| 235 | /* 407 */ "SF32\000" |
| 236 | /* 412 */ "V32\000" |
| 237 | /* 416 */ "SW32\000" |
| 238 | /* 421 */ "SX32\000" |
| 239 | /* 426 */ "SF42\000" |
| 240 | /* 431 */ "V42\000" |
| 241 | /* 435 */ "SW42\000" |
| 242 | /* 440 */ "SX42\000" |
| 243 | /* 445 */ "SF52\000" |
| 244 | /* 450 */ "V52\000" |
| 245 | /* 454 */ "SW52\000" |
| 246 | /* 459 */ "SX52\000" |
| 247 | /* 464 */ "SF62\000" |
| 248 | /* 469 */ "V62\000" |
| 249 | /* 473 */ "SW62\000" |
| 250 | /* 478 */ "SX62\000" |
| 251 | /* 483 */ "PMC2\000" |
| 252 | /* 488 */ "SF2\000" |
| 253 | /* 492 */ "VM2\000" |
| 254 | /* 496 */ "VMP2\000" |
| 255 | /* 501 */ "Q2\000" |
| 256 | /* 504 */ "PMCR2\000" |
| 257 | /* 510 */ "V2\000" |
| 258 | /* 513 */ "SW2\000" |
| 259 | /* 517 */ "SX2\000" |
| 260 | /* 521 */ "PMC13\000" |
| 261 | /* 527 */ "SF13\000" |
| 262 | /* 532 */ "VM13\000" |
| 263 | /* 537 */ "Q13\000" |
| 264 | /* 541 */ "V13\000" |
| 265 | /* 545 */ "SW13\000" |
| 266 | /* 550 */ "SX13\000" |
| 267 | /* 555 */ "SF23\000" |
| 268 | /* 560 */ "Q23\000" |
| 269 | /* 564 */ "V23\000" |
| 270 | /* 568 */ "SW23\000" |
| 271 | /* 573 */ "SX23\000" |
| 272 | /* 578 */ "SF33\000" |
| 273 | /* 583 */ "V33\000" |
| 274 | /* 587 */ "SW33\000" |
| 275 | /* 592 */ "SX33\000" |
| 276 | /* 597 */ "SF43\000" |
| 277 | /* 602 */ "V43\000" |
| 278 | /* 606 */ "SW43\000" |
| 279 | /* 611 */ "SX43\000" |
| 280 | /* 616 */ "SF53\000" |
| 281 | /* 621 */ "V53\000" |
| 282 | /* 625 */ "SW53\000" |
| 283 | /* 630 */ "SX53\000" |
| 284 | /* 635 */ "SF63\000" |
| 285 | /* 640 */ "V63\000" |
| 286 | /* 644 */ "SW63\000" |
| 287 | /* 649 */ "SX63\000" |
| 288 | /* 654 */ "PMC3\000" |
| 289 | /* 659 */ "SF3\000" |
| 290 | /* 663 */ "VM3\000" |
| 291 | /* 667 */ "VMP3\000" |
| 292 | /* 672 */ "Q3\000" |
| 293 | /* 675 */ "PMCR3\000" |
| 294 | /* 681 */ "V3\000" |
| 295 | /* 684 */ "SW3\000" |
| 296 | /* 688 */ "SX3\000" |
| 297 | /* 692 */ "PMC14\000" |
| 298 | /* 698 */ "SF14\000" |
| 299 | /* 703 */ "VM14\000" |
| 300 | /* 708 */ "Q14\000" |
| 301 | /* 712 */ "V14\000" |
| 302 | /* 716 */ "SW14\000" |
| 303 | /* 721 */ "SX14\000" |
| 304 | /* 726 */ "SF24\000" |
| 305 | /* 731 */ "Q24\000" |
| 306 | /* 735 */ "V24\000" |
| 307 | /* 739 */ "SW24\000" |
| 308 | /* 744 */ "SX24\000" |
| 309 | /* 749 */ "SF34\000" |
| 310 | /* 754 */ "V34\000" |
| 311 | /* 758 */ "SW34\000" |
| 312 | /* 763 */ "SX34\000" |
| 313 | /* 768 */ "SF44\000" |
| 314 | /* 773 */ "V44\000" |
| 315 | /* 777 */ "SW44\000" |
| 316 | /* 782 */ "SX44\000" |
| 317 | /* 787 */ "SF54\000" |
| 318 | /* 792 */ "V54\000" |
| 319 | /* 796 */ "SW54\000" |
| 320 | /* 801 */ "SX54\000" |
| 321 | /* 806 */ "PMC4\000" |
| 322 | /* 811 */ "SF4\000" |
| 323 | /* 815 */ "VM4\000" |
| 324 | /* 819 */ "VMP4\000" |
| 325 | /* 824 */ "Q4\000" |
| 326 | /* 827 */ "V4\000" |
| 327 | /* 830 */ "SW4\000" |
| 328 | /* 834 */ "SX4\000" |
| 329 | /* 838 */ "SF15\000" |
| 330 | /* 843 */ "VM15\000" |
| 331 | /* 848 */ "Q15\000" |
| 332 | /* 852 */ "V15\000" |
| 333 | /* 856 */ "SW15\000" |
| 334 | /* 861 */ "SX15\000" |
| 335 | /* 866 */ "SF25\000" |
| 336 | /* 871 */ "Q25\000" |
| 337 | /* 875 */ "V25\000" |
| 338 | /* 879 */ "SW25\000" |
| 339 | /* 884 */ "SX25\000" |
| 340 | /* 889 */ "SF35\000" |
| 341 | /* 894 */ "V35\000" |
| 342 | /* 898 */ "SW35\000" |
| 343 | /* 903 */ "SX35\000" |
| 344 | /* 908 */ "SF45\000" |
| 345 | /* 913 */ "V45\000" |
| 346 | /* 917 */ "SW45\000" |
| 347 | /* 922 */ "SX45\000" |
| 348 | /* 927 */ "SF55\000" |
| 349 | /* 932 */ "V55\000" |
| 350 | /* 936 */ "SW55\000" |
| 351 | /* 941 */ "SX55\000" |
| 352 | /* 946 */ "PMC5\000" |
| 353 | /* 951 */ "SF5\000" |
| 354 | /* 955 */ "VM5\000" |
| 355 | /* 959 */ "VMP5\000" |
| 356 | /* 964 */ "Q5\000" |
| 357 | /* 967 */ "V5\000" |
| 358 | /* 970 */ "SW5\000" |
| 359 | /* 974 */ "SX5\000" |
| 360 | /* 978 */ "SF16\000" |
| 361 | /* 983 */ "Q16\000" |
| 362 | /* 987 */ "V16\000" |
| 363 | /* 991 */ "SW16\000" |
| 364 | /* 996 */ "SX16\000" |
| 365 | /* 1001 */ "SF26\000" |
| 366 | /* 1006 */ "Q26\000" |
| 367 | /* 1010 */ "V26\000" |
| 368 | /* 1014 */ "SW26\000" |
| 369 | /* 1019 */ "SX26\000" |
| 370 | /* 1024 */ "SF36\000" |
| 371 | /* 1029 */ "V36\000" |
| 372 | /* 1033 */ "SW36\000" |
| 373 | /* 1038 */ "SX36\000" |
| 374 | /* 1043 */ "SF46\000" |
| 375 | /* 1048 */ "V46\000" |
| 376 | /* 1052 */ "SW46\000" |
| 377 | /* 1057 */ "SX46\000" |
| 378 | /* 1062 */ "SF56\000" |
| 379 | /* 1067 */ "V56\000" |
| 380 | /* 1071 */ "SW56\000" |
| 381 | /* 1076 */ "SX56\000" |
| 382 | /* 1081 */ "PMC6\000" |
| 383 | /* 1086 */ "SF6\000" |
| 384 | /* 1090 */ "VM6\000" |
| 385 | /* 1094 */ "VMP6\000" |
| 386 | /* 1099 */ "Q6\000" |
| 387 | /* 1102 */ "V6\000" |
| 388 | /* 1105 */ "SW6\000" |
| 389 | /* 1109 */ "SX6\000" |
| 390 | /* 1113 */ "SF17\000" |
| 391 | /* 1118 */ "Q17\000" |
| 392 | /* 1122 */ "V17\000" |
| 393 | /* 1126 */ "SW17\000" |
| 394 | /* 1131 */ "SX17\000" |
| 395 | /* 1136 */ "SF27\000" |
| 396 | /* 1141 */ "Q27\000" |
| 397 | /* 1145 */ "V27\000" |
| 398 | /* 1149 */ "SW27\000" |
| 399 | /* 1154 */ "SX27\000" |
| 400 | /* 1159 */ "SF37\000" |
| 401 | /* 1164 */ "V37\000" |
| 402 | /* 1168 */ "SW37\000" |
| 403 | /* 1173 */ "SX37\000" |
| 404 | /* 1178 */ "SF47\000" |
| 405 | /* 1183 */ "V47\000" |
| 406 | /* 1187 */ "SW47\000" |
| 407 | /* 1192 */ "SX47\000" |
| 408 | /* 1197 */ "SF57\000" |
| 409 | /* 1202 */ "V57\000" |
| 410 | /* 1206 */ "SW57\000" |
| 411 | /* 1211 */ "SX57\000" |
| 412 | /* 1216 */ "PMC7\000" |
| 413 | /* 1221 */ "SF7\000" |
| 414 | /* 1225 */ "VM7\000" |
| 415 | /* 1229 */ "VMP7\000" |
| 416 | /* 1234 */ "Q7\000" |
| 417 | /* 1237 */ "V7\000" |
| 418 | /* 1240 */ "SW7\000" |
| 419 | /* 1244 */ "SX7\000" |
| 420 | /* 1248 */ "SF18\000" |
| 421 | /* 1253 */ "Q18\000" |
| 422 | /* 1257 */ "V18\000" |
| 423 | /* 1261 */ "SW18\000" |
| 424 | /* 1266 */ "SX18\000" |
| 425 | /* 1271 */ "SF28\000" |
| 426 | /* 1276 */ "Q28\000" |
| 427 | /* 1280 */ "V28\000" |
| 428 | /* 1284 */ "SW28\000" |
| 429 | /* 1289 */ "SX28\000" |
| 430 | /* 1294 */ "SF38\000" |
| 431 | /* 1299 */ "V38\000" |
| 432 | /* 1303 */ "SW38\000" |
| 433 | /* 1308 */ "SX38\000" |
| 434 | /* 1313 */ "SF48\000" |
| 435 | /* 1318 */ "V48\000" |
| 436 | /* 1322 */ "SW48\000" |
| 437 | /* 1327 */ "SX48\000" |
| 438 | /* 1332 */ "SF58\000" |
| 439 | /* 1337 */ "V58\000" |
| 440 | /* 1341 */ "SW58\000" |
| 441 | /* 1346 */ "SX58\000" |
| 442 | /* 1351 */ "PMC8\000" |
| 443 | /* 1356 */ "SF8\000" |
| 444 | /* 1360 */ "VM8\000" |
| 445 | /* 1364 */ "Q8\000" |
| 446 | /* 1367 */ "V8\000" |
| 447 | /* 1370 */ "SW8\000" |
| 448 | /* 1374 */ "SX8\000" |
| 449 | /* 1378 */ "SF19\000" |
| 450 | /* 1383 */ "Q19\000" |
| 451 | /* 1387 */ "V19\000" |
| 452 | /* 1391 */ "SW19\000" |
| 453 | /* 1396 */ "SX19\000" |
| 454 | /* 1401 */ "SF29\000" |
| 455 | /* 1406 */ "Q29\000" |
| 456 | /* 1410 */ "V29\000" |
| 457 | /* 1414 */ "SW29\000" |
| 458 | /* 1419 */ "SX29\000" |
| 459 | /* 1424 */ "SF39\000" |
| 460 | /* 1429 */ "V39\000" |
| 461 | /* 1433 */ "SW39\000" |
| 462 | /* 1438 */ "SX39\000" |
| 463 | /* 1443 */ "SF49\000" |
| 464 | /* 1448 */ "V49\000" |
| 465 | /* 1452 */ "SW49\000" |
| 466 | /* 1457 */ "SX49\000" |
| 467 | /* 1462 */ "SF59\000" |
| 468 | /* 1467 */ "V59\000" |
| 469 | /* 1471 */ "SW59\000" |
| 470 | /* 1476 */ "SX59\000" |
| 471 | /* 1481 */ "PMC9\000" |
| 472 | /* 1486 */ "SF9\000" |
| 473 | /* 1490 */ "VM9\000" |
| 474 | /* 1494 */ "Q9\000" |
| 475 | /* 1497 */ "V9\000" |
| 476 | /* 1500 */ "SW9\000" |
| 477 | /* 1504 */ "SX9\000" |
| 478 | /* 1508 */ "USRCC\000" |
| 479 | /* 1514 */ "IC\000" |
| 480 | /* 1517 */ "VL\000" |
| 481 | /* 1520 */ "SAR\000" |
| 482 | /* 1524 */ "PMMR\000" |
| 483 | /* 1529 */ "PSW\000" |
| 484 | /* 1533 */ "VIX\000" |
| 485 | }; |
| 486 | #ifdef __GNUC__ |
| 487 | #pragma GCC diagnostic pop |
| 488 | #endif |
| 489 | |
| 490 | extern const MCRegisterDesc VERegDesc[] = { // Descriptors |
| 491 | { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 492 | { .Name: 1514, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8192, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 493 | { .Name: 1524, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8193, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 494 | { .Name: 1529, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8194, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 495 | { .Name: 1520, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8195, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 496 | { .Name: 1508, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8196, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 497 | { .Name: 1533, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8197, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 498 | { .Name: 1517, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8198, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 499 | { .Name: 137, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8199, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 500 | { .Name: 312, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8200, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 501 | { .Name: 483, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8201, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 502 | { .Name: 654, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8202, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 503 | { .Name: 806, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8203, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 504 | { .Name: 946, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8204, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 505 | { .Name: 1081, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8205, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 506 | { .Name: 1216, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8206, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 507 | { .Name: 1351, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8207, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 508 | { .Name: 1481, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8208, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 509 | { .Name: 0, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8209, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 510 | { .Name: 175, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8210, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 511 | { .Name: 350, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8211, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 512 | { .Name: 521, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8212, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 513 | { .Name: 692, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8213, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 514 | { .Name: 158, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8214, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 515 | { .Name: 333, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8215, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 516 | { .Name: 504, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8216, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 517 | { .Name: 675, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8217, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 518 | { .Name: 155, .SubRegs: 198, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814554, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 519 | { .Name: 330, .SubRegs: 205, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814560, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 520 | { .Name: 501, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814566, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 521 | { .Name: 672, .SubRegs: 219, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814572, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 522 | { .Name: 824, .SubRegs: 226, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814578, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 523 | { .Name: 964, .SubRegs: 233, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814584, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 524 | { .Name: 1099, .SubRegs: 240, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814590, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 525 | { .Name: 1234, .SubRegs: 247, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814596, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 526 | { .Name: 1364, .SubRegs: 254, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814602, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 527 | { .Name: 1494, .SubRegs: 261, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814608, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 528 | { .Name: 16, .SubRegs: 268, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814614, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 529 | { .Name: 191, .SubRegs: 275, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814620, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 530 | { .Name: 366, .SubRegs: 282, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814626, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 531 | { .Name: 537, .SubRegs: 289, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814632, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 532 | { .Name: 708, .SubRegs: 296, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814638, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 533 | { .Name: 848, .SubRegs: 303, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814644, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 534 | { .Name: 983, .SubRegs: 310, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814650, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 535 | { .Name: 1118, .SubRegs: 317, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814656, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 536 | { .Name: 1253, .SubRegs: 324, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814662, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 537 | { .Name: 1383, .SubRegs: 331, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814668, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 538 | { .Name: 39, .SubRegs: 338, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814674, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 539 | { .Name: 214, .SubRegs: 345, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814680, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 540 | { .Name: 389, .SubRegs: 352, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814686, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 541 | { .Name: 560, .SubRegs: 359, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814692, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 542 | { .Name: 731, .SubRegs: 366, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814698, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 543 | { .Name: 871, .SubRegs: 373, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814704, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 544 | { .Name: 1006, .SubRegs: 380, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814710, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 545 | { .Name: 1141, .SubRegs: 387, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814716, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 546 | { .Name: 1276, .SubRegs: 394, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814722, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 547 | { .Name: 1406, .SubRegs: 401, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814728, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 548 | { .Name: 62, .SubRegs: 408, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814734, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 549 | { .Name: 237, .SubRegs: 415, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 1814740, .RegUnitLaneMasks: 5, .IsConstant: 0, .IsArtificial: 0 }, |
| 550 | { .Name: 142, .SubRegs: 2, .SuperRegs: 195, .SubRegIndices: 2, .RegUnits: 1732635, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 551 | { .Name: 317, .SubRegs: 2, .SuperRegs: 189, .SubRegIndices: 2, .RegUnits: 1732638, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 552 | { .Name: 488, .SubRegs: 2, .SuperRegs: 189, .SubRegIndices: 2, .RegUnits: 1732641, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 553 | { .Name: 659, .SubRegs: 2, .SuperRegs: 183, .SubRegIndices: 2, .RegUnits: 1732644, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 554 | { .Name: 811, .SubRegs: 2, .SuperRegs: 183, .SubRegIndices: 2, .RegUnits: 1732647, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 555 | { .Name: 951, .SubRegs: 2, .SuperRegs: 177, .SubRegIndices: 2, .RegUnits: 1732650, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 556 | { .Name: 1086, .SubRegs: 2, .SuperRegs: 177, .SubRegIndices: 2, .RegUnits: 1732653, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 557 | { .Name: 1221, .SubRegs: 2, .SuperRegs: 171, .SubRegIndices: 2, .RegUnits: 1732656, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 558 | { .Name: 1356, .SubRegs: 2, .SuperRegs: 171, .SubRegIndices: 2, .RegUnits: 1732659, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 559 | { .Name: 1486, .SubRegs: 2, .SuperRegs: 165, .SubRegIndices: 2, .RegUnits: 1732662, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 560 | { .Name: 6, .SubRegs: 2, .SuperRegs: 165, .SubRegIndices: 2, .RegUnits: 1732665, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 561 | { .Name: 181, .SubRegs: 2, .SuperRegs: 159, .SubRegIndices: 2, .RegUnits: 1732668, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 562 | { .Name: 356, .SubRegs: 2, .SuperRegs: 159, .SubRegIndices: 2, .RegUnits: 1732671, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 563 | { .Name: 527, .SubRegs: 2, .SuperRegs: 153, .SubRegIndices: 2, .RegUnits: 1732674, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 564 | { .Name: 698, .SubRegs: 2, .SuperRegs: 153, .SubRegIndices: 2, .RegUnits: 1732677, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 565 | { .Name: 838, .SubRegs: 2, .SuperRegs: 147, .SubRegIndices: 2, .RegUnits: 1732680, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 566 | { .Name: 978, .SubRegs: 2, .SuperRegs: 147, .SubRegIndices: 2, .RegUnits: 1732683, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 567 | { .Name: 1113, .SubRegs: 2, .SuperRegs: 141, .SubRegIndices: 2, .RegUnits: 1732686, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 568 | { .Name: 1248, .SubRegs: 2, .SuperRegs: 141, .SubRegIndices: 2, .RegUnits: 1732689, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 569 | { .Name: 1378, .SubRegs: 2, .SuperRegs: 135, .SubRegIndices: 2, .RegUnits: 1732692, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 570 | { .Name: 34, .SubRegs: 2, .SuperRegs: 135, .SubRegIndices: 2, .RegUnits: 1732695, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 571 | { .Name: 209, .SubRegs: 2, .SuperRegs: 129, .SubRegIndices: 2, .RegUnits: 1732698, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 572 | { .Name: 384, .SubRegs: 2, .SuperRegs: 129, .SubRegIndices: 2, .RegUnits: 1732701, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 573 | { .Name: 555, .SubRegs: 2, .SuperRegs: 123, .SubRegIndices: 2, .RegUnits: 1732704, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 574 | { .Name: 726, .SubRegs: 2, .SuperRegs: 123, .SubRegIndices: 2, .RegUnits: 1732707, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 575 | { .Name: 866, .SubRegs: 2, .SuperRegs: 117, .SubRegIndices: 2, .RegUnits: 1732710, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 576 | { .Name: 1001, .SubRegs: 2, .SuperRegs: 117, .SubRegIndices: 2, .RegUnits: 1732713, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 577 | { .Name: 1136, .SubRegs: 2, .SuperRegs: 111, .SubRegIndices: 2, .RegUnits: 1732716, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 578 | { .Name: 1271, .SubRegs: 2, .SuperRegs: 111, .SubRegIndices: 2, .RegUnits: 1732719, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 579 | { .Name: 1401, .SubRegs: 2, .SuperRegs: 105, .SubRegIndices: 2, .RegUnits: 1732722, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 580 | { .Name: 57, .SubRegs: 2, .SuperRegs: 105, .SubRegIndices: 2, .RegUnits: 1732725, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 581 | { .Name: 232, .SubRegs: 2, .SuperRegs: 99, .SubRegIndices: 2, .RegUnits: 1732728, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 582 | { .Name: 407, .SubRegs: 2, .SuperRegs: 99, .SubRegIndices: 2, .RegUnits: 1732731, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 583 | { .Name: 578, .SubRegs: 2, .SuperRegs: 93, .SubRegIndices: 2, .RegUnits: 1732734, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 584 | { .Name: 749, .SubRegs: 2, .SuperRegs: 93, .SubRegIndices: 2, .RegUnits: 1732737, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 585 | { .Name: 889, .SubRegs: 2, .SuperRegs: 87, .SubRegIndices: 2, .RegUnits: 1732740, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 586 | { .Name: 1024, .SubRegs: 2, .SuperRegs: 87, .SubRegIndices: 2, .RegUnits: 1732743, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 587 | { .Name: 1159, .SubRegs: 2, .SuperRegs: 81, .SubRegIndices: 2, .RegUnits: 1732746, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 588 | { .Name: 1294, .SubRegs: 2, .SuperRegs: 81, .SubRegIndices: 2, .RegUnits: 1732749, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 589 | { .Name: 1424, .SubRegs: 2, .SuperRegs: 75, .SubRegIndices: 2, .RegUnits: 1732752, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 590 | { .Name: 80, .SubRegs: 2, .SuperRegs: 75, .SubRegIndices: 2, .RegUnits: 1732755, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 591 | { .Name: 255, .SubRegs: 2, .SuperRegs: 69, .SubRegIndices: 2, .RegUnits: 1732758, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 592 | { .Name: 426, .SubRegs: 2, .SuperRegs: 69, .SubRegIndices: 2, .RegUnits: 1732761, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 593 | { .Name: 597, .SubRegs: 2, .SuperRegs: 63, .SubRegIndices: 2, .RegUnits: 1732764, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 594 | { .Name: 768, .SubRegs: 2, .SuperRegs: 63, .SubRegIndices: 2, .RegUnits: 1732767, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 595 | { .Name: 908, .SubRegs: 2, .SuperRegs: 57, .SubRegIndices: 2, .RegUnits: 1732770, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 596 | { .Name: 1043, .SubRegs: 2, .SuperRegs: 57, .SubRegIndices: 2, .RegUnits: 1732773, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 597 | { .Name: 1178, .SubRegs: 2, .SuperRegs: 51, .SubRegIndices: 2, .RegUnits: 1732776, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 598 | { .Name: 1313, .SubRegs: 2, .SuperRegs: 51, .SubRegIndices: 2, .RegUnits: 1732779, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 599 | { .Name: 1443, .SubRegs: 2, .SuperRegs: 45, .SubRegIndices: 2, .RegUnits: 1732782, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 600 | { .Name: 99, .SubRegs: 2, .SuperRegs: 45, .SubRegIndices: 2, .RegUnits: 1732785, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 601 | { .Name: 274, .SubRegs: 2, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 1732788, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 602 | { .Name: 445, .SubRegs: 2, .SuperRegs: 39, .SubRegIndices: 2, .RegUnits: 1732791, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 603 | { .Name: 616, .SubRegs: 2, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 1732794, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 604 | { .Name: 787, .SubRegs: 2, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 1732797, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 605 | { .Name: 927, .SubRegs: 2, .SuperRegs: 27, .SubRegIndices: 2, .RegUnits: 1732800, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 606 | { .Name: 1062, .SubRegs: 2, .SuperRegs: 27, .SubRegIndices: 2, .RegUnits: 1732803, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 607 | { .Name: 1197, .SubRegs: 2, .SuperRegs: 21, .SubRegIndices: 2, .RegUnits: 1732806, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 608 | { .Name: 1332, .SubRegs: 2, .SuperRegs: 21, .SubRegIndices: 2, .RegUnits: 1732809, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 609 | { .Name: 1462, .SubRegs: 2, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 1732812, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 610 | { .Name: 118, .SubRegs: 2, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 1732815, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 611 | { .Name: 293, .SubRegs: 2, .SuperRegs: 9, .SubRegIndices: 2, .RegUnits: 1732818, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 612 | { .Name: 464, .SubRegs: 2, .SuperRegs: 9, .SubRegIndices: 2, .RegUnits: 1732821, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 613 | { .Name: 635, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 1732824, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 614 | { .Name: 167, .SubRegs: 2, .SuperRegs: 192, .SubRegIndices: 2, .RegUnits: 1732634, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 615 | { .Name: 342, .SubRegs: 2, .SuperRegs: 186, .SubRegIndices: 2, .RegUnits: 1732637, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 616 | { .Name: 513, .SubRegs: 2, .SuperRegs: 186, .SubRegIndices: 2, .RegUnits: 1732640, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 617 | { .Name: 684, .SubRegs: 2, .SuperRegs: 180, .SubRegIndices: 2, .RegUnits: 1732643, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 618 | { .Name: 830, .SubRegs: 2, .SuperRegs: 180, .SubRegIndices: 2, .RegUnits: 1732646, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 619 | { .Name: 970, .SubRegs: 2, .SuperRegs: 174, .SubRegIndices: 2, .RegUnits: 1732649, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 620 | { .Name: 1105, .SubRegs: 2, .SuperRegs: 174, .SubRegIndices: 2, .RegUnits: 1732652, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 621 | { .Name: 1240, .SubRegs: 2, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 1732655, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 622 | { .Name: 1370, .SubRegs: 2, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 1732658, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 623 | { .Name: 1500, .SubRegs: 2, .SuperRegs: 162, .SubRegIndices: 2, .RegUnits: 1732661, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 624 | { .Name: 24, .SubRegs: 2, .SuperRegs: 162, .SubRegIndices: 2, .RegUnits: 1732664, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 625 | { .Name: 199, .SubRegs: 2, .SuperRegs: 156, .SubRegIndices: 2, .RegUnits: 1732667, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 626 | { .Name: 374, .SubRegs: 2, .SuperRegs: 156, .SubRegIndices: 2, .RegUnits: 1732670, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 627 | { .Name: 545, .SubRegs: 2, .SuperRegs: 150, .SubRegIndices: 2, .RegUnits: 1732673, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 628 | { .Name: 716, .SubRegs: 2, .SuperRegs: 150, .SubRegIndices: 2, .RegUnits: 1732676, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 629 | { .Name: 856, .SubRegs: 2, .SuperRegs: 144, .SubRegIndices: 2, .RegUnits: 1732679, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 630 | { .Name: 991, .SubRegs: 2, .SuperRegs: 144, .SubRegIndices: 2, .RegUnits: 1732682, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 631 | { .Name: 1126, .SubRegs: 2, .SuperRegs: 138, .SubRegIndices: 2, .RegUnits: 1732685, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 632 | { .Name: 1261, .SubRegs: 2, .SuperRegs: 138, .SubRegIndices: 2, .RegUnits: 1732688, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 633 | { .Name: 1391, .SubRegs: 2, .SuperRegs: 132, .SubRegIndices: 2, .RegUnits: 1732691, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 634 | { .Name: 47, .SubRegs: 2, .SuperRegs: 132, .SubRegIndices: 2, .RegUnits: 1732694, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 635 | { .Name: 222, .SubRegs: 2, .SuperRegs: 126, .SubRegIndices: 2, .RegUnits: 1732697, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 636 | { .Name: 397, .SubRegs: 2, .SuperRegs: 126, .SubRegIndices: 2, .RegUnits: 1732700, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 637 | { .Name: 568, .SubRegs: 2, .SuperRegs: 120, .SubRegIndices: 2, .RegUnits: 1732703, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 638 | { .Name: 739, .SubRegs: 2, .SuperRegs: 120, .SubRegIndices: 2, .RegUnits: 1732706, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 639 | { .Name: 879, .SubRegs: 2, .SuperRegs: 114, .SubRegIndices: 2, .RegUnits: 1732709, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 640 | { .Name: 1014, .SubRegs: 2, .SuperRegs: 114, .SubRegIndices: 2, .RegUnits: 1732712, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 641 | { .Name: 1149, .SubRegs: 2, .SuperRegs: 108, .SubRegIndices: 2, .RegUnits: 1732715, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 642 | { .Name: 1284, .SubRegs: 2, .SuperRegs: 108, .SubRegIndices: 2, .RegUnits: 1732718, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 643 | { .Name: 1414, .SubRegs: 2, .SuperRegs: 102, .SubRegIndices: 2, .RegUnits: 1732721, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 644 | { .Name: 70, .SubRegs: 2, .SuperRegs: 102, .SubRegIndices: 2, .RegUnits: 1732724, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 645 | { .Name: 245, .SubRegs: 2, .SuperRegs: 96, .SubRegIndices: 2, .RegUnits: 1732727, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 646 | { .Name: 416, .SubRegs: 2, .SuperRegs: 96, .SubRegIndices: 2, .RegUnits: 1732730, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 647 | { .Name: 587, .SubRegs: 2, .SuperRegs: 90, .SubRegIndices: 2, .RegUnits: 1732733, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 648 | { .Name: 758, .SubRegs: 2, .SuperRegs: 90, .SubRegIndices: 2, .RegUnits: 1732736, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 649 | { .Name: 898, .SubRegs: 2, .SuperRegs: 84, .SubRegIndices: 2, .RegUnits: 1732739, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 650 | { .Name: 1033, .SubRegs: 2, .SuperRegs: 84, .SubRegIndices: 2, .RegUnits: 1732742, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 651 | { .Name: 1168, .SubRegs: 2, .SuperRegs: 78, .SubRegIndices: 2, .RegUnits: 1732745, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 652 | { .Name: 1303, .SubRegs: 2, .SuperRegs: 78, .SubRegIndices: 2, .RegUnits: 1732748, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 653 | { .Name: 1433, .SubRegs: 2, .SuperRegs: 72, .SubRegIndices: 2, .RegUnits: 1732751, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 654 | { .Name: 89, .SubRegs: 2, .SuperRegs: 72, .SubRegIndices: 2, .RegUnits: 1732754, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 655 | { .Name: 264, .SubRegs: 2, .SuperRegs: 66, .SubRegIndices: 2, .RegUnits: 1732757, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 656 | { .Name: 435, .SubRegs: 2, .SuperRegs: 66, .SubRegIndices: 2, .RegUnits: 1732760, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 657 | { .Name: 606, .SubRegs: 2, .SuperRegs: 60, .SubRegIndices: 2, .RegUnits: 1732763, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 658 | { .Name: 777, .SubRegs: 2, .SuperRegs: 60, .SubRegIndices: 2, .RegUnits: 1732766, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 659 | { .Name: 917, .SubRegs: 2, .SuperRegs: 54, .SubRegIndices: 2, .RegUnits: 1732769, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 660 | { .Name: 1052, .SubRegs: 2, .SuperRegs: 54, .SubRegIndices: 2, .RegUnits: 1732772, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 661 | { .Name: 1187, .SubRegs: 2, .SuperRegs: 48, .SubRegIndices: 2, .RegUnits: 1732775, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 662 | { .Name: 1322, .SubRegs: 2, .SuperRegs: 48, .SubRegIndices: 2, .RegUnits: 1732778, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 663 | { .Name: 1452, .SubRegs: 2, .SuperRegs: 42, .SubRegIndices: 2, .RegUnits: 1732781, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 664 | { .Name: 108, .SubRegs: 2, .SuperRegs: 42, .SubRegIndices: 2, .RegUnits: 1732784, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 665 | { .Name: 283, .SubRegs: 2, .SuperRegs: 36, .SubRegIndices: 2, .RegUnits: 1732787, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 666 | { .Name: 454, .SubRegs: 2, .SuperRegs: 36, .SubRegIndices: 2, .RegUnits: 1732790, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 667 | { .Name: 625, .SubRegs: 2, .SuperRegs: 30, .SubRegIndices: 2, .RegUnits: 1732793, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 668 | { .Name: 796, .SubRegs: 2, .SuperRegs: 30, .SubRegIndices: 2, .RegUnits: 1732796, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 669 | { .Name: 936, .SubRegs: 2, .SuperRegs: 24, .SubRegIndices: 2, .RegUnits: 1732799, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 670 | { .Name: 1071, .SubRegs: 2, .SuperRegs: 24, .SubRegIndices: 2, .RegUnits: 1732802, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 671 | { .Name: 1206, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 1732805, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 672 | { .Name: 1341, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 1732808, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 673 | { .Name: 1471, .SubRegs: 2, .SuperRegs: 12, .SubRegIndices: 2, .RegUnits: 1732811, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 674 | { .Name: 127, .SubRegs: 2, .SuperRegs: 12, .SubRegIndices: 2, .RegUnits: 1732814, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 675 | { .Name: 302, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 1732817, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 676 | { .Name: 473, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 1732820, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 677 | { .Name: 644, .SubRegs: 2, .SuperRegs: 0, .SubRegIndices: 2, .RegUnits: 1732823, .RegUnitLaneMasks: 11, .IsConstant: 0, .IsArtificial: 0 }, |
| 678 | { .Name: 171, .SubRegs: 202, .SuperRegs: 193, .SubRegIndices: 0, .RegUnits: 1826842, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 679 | { .Name: 346, .SubRegs: 202, .SuperRegs: 187, .SubRegIndices: 0, .RegUnits: 1826845, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 680 | { .Name: 517, .SubRegs: 202, .SuperRegs: 187, .SubRegIndices: 0, .RegUnits: 1826848, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 681 | { .Name: 688, .SubRegs: 202, .SuperRegs: 181, .SubRegIndices: 0, .RegUnits: 1826851, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 682 | { .Name: 834, .SubRegs: 202, .SuperRegs: 181, .SubRegIndices: 0, .RegUnits: 1826854, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 683 | { .Name: 974, .SubRegs: 202, .SuperRegs: 175, .SubRegIndices: 0, .RegUnits: 1826857, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 684 | { .Name: 1109, .SubRegs: 202, .SuperRegs: 175, .SubRegIndices: 0, .RegUnits: 1826860, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 685 | { .Name: 1244, .SubRegs: 202, .SuperRegs: 169, .SubRegIndices: 0, .RegUnits: 1826863, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 686 | { .Name: 1374, .SubRegs: 202, .SuperRegs: 169, .SubRegIndices: 0, .RegUnits: 1826866, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 687 | { .Name: 1504, .SubRegs: 202, .SuperRegs: 163, .SubRegIndices: 0, .RegUnits: 1826869, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 688 | { .Name: 29, .SubRegs: 202, .SuperRegs: 163, .SubRegIndices: 0, .RegUnits: 1826872, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 689 | { .Name: 204, .SubRegs: 202, .SuperRegs: 157, .SubRegIndices: 0, .RegUnits: 1826875, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 690 | { .Name: 379, .SubRegs: 202, .SuperRegs: 157, .SubRegIndices: 0, .RegUnits: 1826878, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 691 | { .Name: 550, .SubRegs: 202, .SuperRegs: 151, .SubRegIndices: 0, .RegUnits: 1826881, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 692 | { .Name: 721, .SubRegs: 202, .SuperRegs: 151, .SubRegIndices: 0, .RegUnits: 1826884, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 693 | { .Name: 861, .SubRegs: 202, .SuperRegs: 145, .SubRegIndices: 0, .RegUnits: 1826887, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 694 | { .Name: 996, .SubRegs: 202, .SuperRegs: 145, .SubRegIndices: 0, .RegUnits: 1826890, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 695 | { .Name: 1131, .SubRegs: 202, .SuperRegs: 139, .SubRegIndices: 0, .RegUnits: 1826893, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 696 | { .Name: 1266, .SubRegs: 202, .SuperRegs: 139, .SubRegIndices: 0, .RegUnits: 1826896, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 697 | { .Name: 1396, .SubRegs: 202, .SuperRegs: 133, .SubRegIndices: 0, .RegUnits: 1826899, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 698 | { .Name: 52, .SubRegs: 202, .SuperRegs: 133, .SubRegIndices: 0, .RegUnits: 1826902, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 699 | { .Name: 227, .SubRegs: 202, .SuperRegs: 127, .SubRegIndices: 0, .RegUnits: 1826905, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 700 | { .Name: 402, .SubRegs: 202, .SuperRegs: 127, .SubRegIndices: 0, .RegUnits: 1826908, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 701 | { .Name: 573, .SubRegs: 202, .SuperRegs: 121, .SubRegIndices: 0, .RegUnits: 1826911, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 702 | { .Name: 744, .SubRegs: 202, .SuperRegs: 121, .SubRegIndices: 0, .RegUnits: 1826914, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 703 | { .Name: 884, .SubRegs: 202, .SuperRegs: 115, .SubRegIndices: 0, .RegUnits: 1826917, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 704 | { .Name: 1019, .SubRegs: 202, .SuperRegs: 115, .SubRegIndices: 0, .RegUnits: 1826920, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 705 | { .Name: 1154, .SubRegs: 202, .SuperRegs: 109, .SubRegIndices: 0, .RegUnits: 1826923, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 706 | { .Name: 1289, .SubRegs: 202, .SuperRegs: 109, .SubRegIndices: 0, .RegUnits: 1826926, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 707 | { .Name: 1419, .SubRegs: 202, .SuperRegs: 103, .SubRegIndices: 0, .RegUnits: 1826929, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 708 | { .Name: 75, .SubRegs: 202, .SuperRegs: 103, .SubRegIndices: 0, .RegUnits: 1826932, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 709 | { .Name: 250, .SubRegs: 202, .SuperRegs: 97, .SubRegIndices: 0, .RegUnits: 1826935, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 710 | { .Name: 421, .SubRegs: 202, .SuperRegs: 97, .SubRegIndices: 0, .RegUnits: 1826938, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 711 | { .Name: 592, .SubRegs: 202, .SuperRegs: 91, .SubRegIndices: 0, .RegUnits: 1826941, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 712 | { .Name: 763, .SubRegs: 202, .SuperRegs: 91, .SubRegIndices: 0, .RegUnits: 1826944, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 713 | { .Name: 903, .SubRegs: 202, .SuperRegs: 85, .SubRegIndices: 0, .RegUnits: 1826947, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 714 | { .Name: 1038, .SubRegs: 202, .SuperRegs: 85, .SubRegIndices: 0, .RegUnits: 1826950, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 715 | { .Name: 1173, .SubRegs: 202, .SuperRegs: 79, .SubRegIndices: 0, .RegUnits: 1826953, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 716 | { .Name: 1308, .SubRegs: 202, .SuperRegs: 79, .SubRegIndices: 0, .RegUnits: 1826956, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 717 | { .Name: 1438, .SubRegs: 202, .SuperRegs: 73, .SubRegIndices: 0, .RegUnits: 1826959, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 718 | { .Name: 94, .SubRegs: 202, .SuperRegs: 73, .SubRegIndices: 0, .RegUnits: 1826962, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 719 | { .Name: 269, .SubRegs: 202, .SuperRegs: 67, .SubRegIndices: 0, .RegUnits: 1826965, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 720 | { .Name: 440, .SubRegs: 202, .SuperRegs: 67, .SubRegIndices: 0, .RegUnits: 1826968, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 721 | { .Name: 611, .SubRegs: 202, .SuperRegs: 61, .SubRegIndices: 0, .RegUnits: 1826971, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 722 | { .Name: 782, .SubRegs: 202, .SuperRegs: 61, .SubRegIndices: 0, .RegUnits: 1826974, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 723 | { .Name: 922, .SubRegs: 202, .SuperRegs: 55, .SubRegIndices: 0, .RegUnits: 1826977, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 724 | { .Name: 1057, .SubRegs: 202, .SuperRegs: 55, .SubRegIndices: 0, .RegUnits: 1826980, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 725 | { .Name: 1192, .SubRegs: 202, .SuperRegs: 49, .SubRegIndices: 0, .RegUnits: 1826983, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 726 | { .Name: 1327, .SubRegs: 202, .SuperRegs: 49, .SubRegIndices: 0, .RegUnits: 1826986, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 727 | { .Name: 1457, .SubRegs: 202, .SuperRegs: 43, .SubRegIndices: 0, .RegUnits: 1826989, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 728 | { .Name: 113, .SubRegs: 202, .SuperRegs: 43, .SubRegIndices: 0, .RegUnits: 1826992, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 729 | { .Name: 288, .SubRegs: 202, .SuperRegs: 37, .SubRegIndices: 0, .RegUnits: 1826995, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 730 | { .Name: 459, .SubRegs: 202, .SuperRegs: 37, .SubRegIndices: 0, .RegUnits: 1826998, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 731 | { .Name: 630, .SubRegs: 202, .SuperRegs: 31, .SubRegIndices: 0, .RegUnits: 1827001, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 732 | { .Name: 801, .SubRegs: 202, .SuperRegs: 31, .SubRegIndices: 0, .RegUnits: 1827004, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 733 | { .Name: 941, .SubRegs: 202, .SuperRegs: 25, .SubRegIndices: 0, .RegUnits: 1827007, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 734 | { .Name: 1076, .SubRegs: 202, .SuperRegs: 25, .SubRegIndices: 0, .RegUnits: 1827010, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 735 | { .Name: 1211, .SubRegs: 202, .SuperRegs: 19, .SubRegIndices: 0, .RegUnits: 1827013, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 736 | { .Name: 1346, .SubRegs: 202, .SuperRegs: 19, .SubRegIndices: 0, .RegUnits: 1827016, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 737 | { .Name: 1476, .SubRegs: 202, .SuperRegs: 13, .SubRegIndices: 0, .RegUnits: 1827019, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 738 | { .Name: 132, .SubRegs: 202, .SuperRegs: 13, .SubRegIndices: 0, .RegUnits: 1827022, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 739 | { .Name: 307, .SubRegs: 202, .SuperRegs: 7, .SubRegIndices: 0, .RegUnits: 1827025, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 740 | { .Name: 478, .SubRegs: 202, .SuperRegs: 7, .SubRegIndices: 0, .RegUnits: 1827028, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 741 | { .Name: 649, .SubRegs: 202, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 1827031, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 }, |
| 742 | { .Name: 164, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8410, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 743 | { .Name: 339, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8411, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 744 | { .Name: 510, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8412, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 745 | { .Name: 681, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8413, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 746 | { .Name: 827, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8414, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 747 | { .Name: 967, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8415, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 748 | { .Name: 1102, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8416, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 749 | { .Name: 1237, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8417, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 750 | { .Name: 1367, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8418, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 751 | { .Name: 1497, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8419, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 752 | { .Name: 20, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8420, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 753 | { .Name: 195, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8421, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 754 | { .Name: 370, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8422, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 755 | { .Name: 541, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8423, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 756 | { .Name: 712, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8424, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 757 | { .Name: 852, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8425, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 758 | { .Name: 987, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8426, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 759 | { .Name: 1122, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8427, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 760 | { .Name: 1257, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8428, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 761 | { .Name: 1387, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8429, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 762 | { .Name: 43, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8430, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 763 | { .Name: 218, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8431, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 764 | { .Name: 393, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8432, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 765 | { .Name: 564, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8433, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 766 | { .Name: 735, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8434, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 767 | { .Name: 875, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8435, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 768 | { .Name: 1010, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8436, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 769 | { .Name: 1145, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8437, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 770 | { .Name: 1280, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8438, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 771 | { .Name: 1410, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8439, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 772 | { .Name: 66, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8440, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 773 | { .Name: 241, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8441, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 774 | { .Name: 412, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8442, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 775 | { .Name: 583, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8443, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 776 | { .Name: 754, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8444, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 777 | { .Name: 894, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8445, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 778 | { .Name: 1029, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8446, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 779 | { .Name: 1164, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8447, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 780 | { .Name: 1299, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8448, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 781 | { .Name: 1429, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8449, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 782 | { .Name: 85, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8450, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 783 | { .Name: 260, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8451, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 784 | { .Name: 431, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8452, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 785 | { .Name: 602, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8453, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 786 | { .Name: 773, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8454, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 787 | { .Name: 913, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8455, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 788 | { .Name: 1048, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8456, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 789 | { .Name: 1183, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8457, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 790 | { .Name: 1318, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8458, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 791 | { .Name: 1448, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8459, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 792 | { .Name: 104, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8460, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 793 | { .Name: 279, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8461, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 794 | { .Name: 450, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8462, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 795 | { .Name: 621, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8463, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 796 | { .Name: 792, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8464, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 797 | { .Name: 932, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8465, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 798 | { .Name: 1067, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8466, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 799 | { .Name: 1202, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8467, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 800 | { .Name: 1337, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8468, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 801 | { .Name: 1467, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8469, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 802 | { .Name: 123, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8470, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 803 | { .Name: 298, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8471, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 804 | { .Name: 469, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8472, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 805 | { .Name: 640, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8473, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 806 | { .Name: 146, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8474, .RegUnitLaneMasks: 12, .IsConstant: 1, .IsArtificial: 0 }, |
| 807 | { .Name: 321, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8475, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 808 | { .Name: 492, .SubRegs: 2, .SuperRegs: 463, .SubRegIndices: 2, .RegUnits: 8476, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 809 | { .Name: 663, .SubRegs: 2, .SuperRegs: 461, .SubRegIndices: 2, .RegUnits: 8477, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 810 | { .Name: 815, .SubRegs: 2, .SuperRegs: 461, .SubRegIndices: 2, .RegUnits: 8478, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 811 | { .Name: 955, .SubRegs: 2, .SuperRegs: 459, .SubRegIndices: 2, .RegUnits: 8479, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 812 | { .Name: 1090, .SubRegs: 2, .SuperRegs: 459, .SubRegIndices: 2, .RegUnits: 8480, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 813 | { .Name: 1225, .SubRegs: 2, .SuperRegs: 457, .SubRegIndices: 2, .RegUnits: 8481, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 814 | { .Name: 1360, .SubRegs: 2, .SuperRegs: 457, .SubRegIndices: 2, .RegUnits: 8482, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 815 | { .Name: 1490, .SubRegs: 2, .SuperRegs: 455, .SubRegIndices: 2, .RegUnits: 8483, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 816 | { .Name: 11, .SubRegs: 2, .SuperRegs: 455, .SubRegIndices: 2, .RegUnits: 8484, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 817 | { .Name: 186, .SubRegs: 2, .SuperRegs: 453, .SubRegIndices: 2, .RegUnits: 8485, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 818 | { .Name: 361, .SubRegs: 2, .SuperRegs: 453, .SubRegIndices: 2, .RegUnits: 8486, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 819 | { .Name: 532, .SubRegs: 2, .SuperRegs: 451, .SubRegIndices: 2, .RegUnits: 8487, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 820 | { .Name: 703, .SubRegs: 2, .SuperRegs: 451, .SubRegIndices: 2, .RegUnits: 8488, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 821 | { .Name: 843, .SubRegs: 2, .SuperRegs: 449, .SubRegIndices: 2, .RegUnits: 8489, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 }, |
| 822 | { .Name: 150, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8490, .RegUnitLaneMasks: 12, .IsConstant: 1, .IsArtificial: 0 }, |
| 823 | { .Name: 325, .SubRegs: 422, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 1732892, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 }, |
| 824 | { .Name: 496, .SubRegs: 425, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 1732894, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 }, |
| 825 | { .Name: 667, .SubRegs: 428, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 1732896, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 }, |
| 826 | { .Name: 819, .SubRegs: 431, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 1732898, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 }, |
| 827 | { .Name: 959, .SubRegs: 434, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 1732900, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 }, |
| 828 | { .Name: 1094, .SubRegs: 437, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 1732902, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 }, |
| 829 | { .Name: 1229, .SubRegs: 440, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 1732904, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 }, |
| 830 | }; |
| 831 | |
| 832 | extern const MCPhysReg VERegUnitRoots[][2] = { |
| 833 | { VE::IC }, |
| 834 | { VE::PMMR }, |
| 835 | { VE::PSW }, |
| 836 | { VE::SAR }, |
| 837 | { VE::USRCC }, |
| 838 | { VE::VIX }, |
| 839 | { VE::VL }, |
| 840 | { VE::PMC0 }, |
| 841 | { VE::PMC1 }, |
| 842 | { VE::PMC2 }, |
| 843 | { VE::PMC3 }, |
| 844 | { VE::PMC4 }, |
| 845 | { VE::PMC5 }, |
| 846 | { VE::PMC6 }, |
| 847 | { VE::PMC7 }, |
| 848 | { VE::PMC8 }, |
| 849 | { VE::PMC9 }, |
| 850 | { VE::PMC10 }, |
| 851 | { VE::PMC11 }, |
| 852 | { VE::PMC12 }, |
| 853 | { VE::PMC13 }, |
| 854 | { VE::PMC14 }, |
| 855 | { VE::PMCR0 }, |
| 856 | { VE::PMCR1 }, |
| 857 | { VE::PMCR2 }, |
| 858 | { VE::PMCR3 }, |
| 859 | { VE::SW0 }, |
| 860 | { VE::SW0, VE::SF0 }, |
| 861 | { VE::SF0 }, |
| 862 | { VE::SW1 }, |
| 863 | { VE::SW1, VE::SF1 }, |
| 864 | { VE::SF1 }, |
| 865 | { VE::SW2 }, |
| 866 | { VE::SW2, VE::SF2 }, |
| 867 | { VE::SF2 }, |
| 868 | { VE::SW3 }, |
| 869 | { VE::SW3, VE::SF3 }, |
| 870 | { VE::SF3 }, |
| 871 | { VE::SW4 }, |
| 872 | { VE::SW4, VE::SF4 }, |
| 873 | { VE::SF4 }, |
| 874 | { VE::SW5 }, |
| 875 | { VE::SW5, VE::SF5 }, |
| 876 | { VE::SF5 }, |
| 877 | { VE::SW6 }, |
| 878 | { VE::SW6, VE::SF6 }, |
| 879 | { VE::SF6 }, |
| 880 | { VE::SW7 }, |
| 881 | { VE::SW7, VE::SF7 }, |
| 882 | { VE::SF7 }, |
| 883 | { VE::SW8 }, |
| 884 | { VE::SW8, VE::SF8 }, |
| 885 | { VE::SF8 }, |
| 886 | { VE::SW9 }, |
| 887 | { VE::SW9, VE::SF9 }, |
| 888 | { VE::SF9 }, |
| 889 | { VE::SW10 }, |
| 890 | { VE::SW10, VE::SF10 }, |
| 891 | { VE::SF10 }, |
| 892 | { VE::SW11 }, |
| 893 | { VE::SW11, VE::SF11 }, |
| 894 | { VE::SF11 }, |
| 895 | { VE::SW12 }, |
| 896 | { VE::SW12, VE::SF12 }, |
| 897 | { VE::SF12 }, |
| 898 | { VE::SW13 }, |
| 899 | { VE::SW13, VE::SF13 }, |
| 900 | { VE::SF13 }, |
| 901 | { VE::SW14 }, |
| 902 | { VE::SW14, VE::SF14 }, |
| 903 | { VE::SF14 }, |
| 904 | { VE::SW15 }, |
| 905 | { VE::SW15, VE::SF15 }, |
| 906 | { VE::SF15 }, |
| 907 | { VE::SW16 }, |
| 908 | { VE::SW16, VE::SF16 }, |
| 909 | { VE::SF16 }, |
| 910 | { VE::SW17 }, |
| 911 | { VE::SW17, VE::SF17 }, |
| 912 | { VE::SF17 }, |
| 913 | { VE::SW18 }, |
| 914 | { VE::SW18, VE::SF18 }, |
| 915 | { VE::SF18 }, |
| 916 | { VE::SW19 }, |
| 917 | { VE::SW19, VE::SF19 }, |
| 918 | { VE::SF19 }, |
| 919 | { VE::SW20 }, |
| 920 | { VE::SW20, VE::SF20 }, |
| 921 | { VE::SF20 }, |
| 922 | { VE::SW21 }, |
| 923 | { VE::SW21, VE::SF21 }, |
| 924 | { VE::SF21 }, |
| 925 | { VE::SW22 }, |
| 926 | { VE::SW22, VE::SF22 }, |
| 927 | { VE::SF22 }, |
| 928 | { VE::SW23 }, |
| 929 | { VE::SW23, VE::SF23 }, |
| 930 | { VE::SF23 }, |
| 931 | { VE::SW24 }, |
| 932 | { VE::SW24, VE::SF24 }, |
| 933 | { VE::SF24 }, |
| 934 | { VE::SW25 }, |
| 935 | { VE::SW25, VE::SF25 }, |
| 936 | { VE::SF25 }, |
| 937 | { VE::SW26 }, |
| 938 | { VE::SW26, VE::SF26 }, |
| 939 | { VE::SF26 }, |
| 940 | { VE::SW27 }, |
| 941 | { VE::SW27, VE::SF27 }, |
| 942 | { VE::SF27 }, |
| 943 | { VE::SW28 }, |
| 944 | { VE::SW28, VE::SF28 }, |
| 945 | { VE::SF28 }, |
| 946 | { VE::SW29 }, |
| 947 | { VE::SW29, VE::SF29 }, |
| 948 | { VE::SF29 }, |
| 949 | { VE::SW30 }, |
| 950 | { VE::SW30, VE::SF30 }, |
| 951 | { VE::SF30 }, |
| 952 | { VE::SW31 }, |
| 953 | { VE::SW31, VE::SF31 }, |
| 954 | { VE::SF31 }, |
| 955 | { VE::SW32 }, |
| 956 | { VE::SW32, VE::SF32 }, |
| 957 | { VE::SF32 }, |
| 958 | { VE::SW33 }, |
| 959 | { VE::SW33, VE::SF33 }, |
| 960 | { VE::SF33 }, |
| 961 | { VE::SW34 }, |
| 962 | { VE::SW34, VE::SF34 }, |
| 963 | { VE::SF34 }, |
| 964 | { VE::SW35 }, |
| 965 | { VE::SW35, VE::SF35 }, |
| 966 | { VE::SF35 }, |
| 967 | { VE::SW36 }, |
| 968 | { VE::SW36, VE::SF36 }, |
| 969 | { VE::SF36 }, |
| 970 | { VE::SW37 }, |
| 971 | { VE::SW37, VE::SF37 }, |
| 972 | { VE::SF37 }, |
| 973 | { VE::SW38 }, |
| 974 | { VE::SW38, VE::SF38 }, |
| 975 | { VE::SF38 }, |
| 976 | { VE::SW39 }, |
| 977 | { VE::SW39, VE::SF39 }, |
| 978 | { VE::SF39 }, |
| 979 | { VE::SW40 }, |
| 980 | { VE::SW40, VE::SF40 }, |
| 981 | { VE::SF40 }, |
| 982 | { VE::SW41 }, |
| 983 | { VE::SW41, VE::SF41 }, |
| 984 | { VE::SF41 }, |
| 985 | { VE::SW42 }, |
| 986 | { VE::SW42, VE::SF42 }, |
| 987 | { VE::SF42 }, |
| 988 | { VE::SW43 }, |
| 989 | { VE::SW43, VE::SF43 }, |
| 990 | { VE::SF43 }, |
| 991 | { VE::SW44 }, |
| 992 | { VE::SW44, VE::SF44 }, |
| 993 | { VE::SF44 }, |
| 994 | { VE::SW45 }, |
| 995 | { VE::SW45, VE::SF45 }, |
| 996 | { VE::SF45 }, |
| 997 | { VE::SW46 }, |
| 998 | { VE::SW46, VE::SF46 }, |
| 999 | { VE::SF46 }, |
| 1000 | { VE::SW47 }, |
| 1001 | { VE::SW47, VE::SF47 }, |
| 1002 | { VE::SF47 }, |
| 1003 | { VE::SW48 }, |
| 1004 | { VE::SW48, VE::SF48 }, |
| 1005 | { VE::SF48 }, |
| 1006 | { VE::SW49 }, |
| 1007 | { VE::SW49, VE::SF49 }, |
| 1008 | { VE::SF49 }, |
| 1009 | { VE::SW50 }, |
| 1010 | { VE::SW50, VE::SF50 }, |
| 1011 | { VE::SF50 }, |
| 1012 | { VE::SW51 }, |
| 1013 | { VE::SW51, VE::SF51 }, |
| 1014 | { VE::SF51 }, |
| 1015 | { VE::SW52 }, |
| 1016 | { VE::SW52, VE::SF52 }, |
| 1017 | { VE::SF52 }, |
| 1018 | { VE::SW53 }, |
| 1019 | { VE::SW53, VE::SF53 }, |
| 1020 | { VE::SF53 }, |
| 1021 | { VE::SW54 }, |
| 1022 | { VE::SW54, VE::SF54 }, |
| 1023 | { VE::SF54 }, |
| 1024 | { VE::SW55 }, |
| 1025 | { VE::SW55, VE::SF55 }, |
| 1026 | { VE::SF55 }, |
| 1027 | { VE::SW56 }, |
| 1028 | { VE::SW56, VE::SF56 }, |
| 1029 | { VE::SF56 }, |
| 1030 | { VE::SW57 }, |
| 1031 | { VE::SW57, VE::SF57 }, |
| 1032 | { VE::SF57 }, |
| 1033 | { VE::SW58 }, |
| 1034 | { VE::SW58, VE::SF58 }, |
| 1035 | { VE::SF58 }, |
| 1036 | { VE::SW59 }, |
| 1037 | { VE::SW59, VE::SF59 }, |
| 1038 | { VE::SF59 }, |
| 1039 | { VE::SW60 }, |
| 1040 | { VE::SW60, VE::SF60 }, |
| 1041 | { VE::SF60 }, |
| 1042 | { VE::SW61 }, |
| 1043 | { VE::SW61, VE::SF61 }, |
| 1044 | { VE::SF61 }, |
| 1045 | { VE::SW62 }, |
| 1046 | { VE::SW62, VE::SF62 }, |
| 1047 | { VE::SF62 }, |
| 1048 | { VE::SW63 }, |
| 1049 | { VE::SW63, VE::SF63 }, |
| 1050 | { VE::SF63 }, |
| 1051 | { VE::V0 }, |
| 1052 | { VE::V1 }, |
| 1053 | { VE::V2 }, |
| 1054 | { VE::V3 }, |
| 1055 | { VE::V4 }, |
| 1056 | { VE::V5 }, |
| 1057 | { VE::V6 }, |
| 1058 | { VE::V7 }, |
| 1059 | { VE::V8 }, |
| 1060 | { VE::V9 }, |
| 1061 | { VE::V10 }, |
| 1062 | { VE::V11 }, |
| 1063 | { VE::V12 }, |
| 1064 | { VE::V13 }, |
| 1065 | { VE::V14 }, |
| 1066 | { VE::V15 }, |
| 1067 | { VE::V16 }, |
| 1068 | { VE::V17 }, |
| 1069 | { VE::V18 }, |
| 1070 | { VE::V19 }, |
| 1071 | { VE::V20 }, |
| 1072 | { VE::V21 }, |
| 1073 | { VE::V22 }, |
| 1074 | { VE::V23 }, |
| 1075 | { VE::V24 }, |
| 1076 | { VE::V25 }, |
| 1077 | { VE::V26 }, |
| 1078 | { VE::V27 }, |
| 1079 | { VE::V28 }, |
| 1080 | { VE::V29 }, |
| 1081 | { VE::V30 }, |
| 1082 | { VE::V31 }, |
| 1083 | { VE::V32 }, |
| 1084 | { VE::V33 }, |
| 1085 | { VE::V34 }, |
| 1086 | { VE::V35 }, |
| 1087 | { VE::V36 }, |
| 1088 | { VE::V37 }, |
| 1089 | { VE::V38 }, |
| 1090 | { VE::V39 }, |
| 1091 | { VE::V40 }, |
| 1092 | { VE::V41 }, |
| 1093 | { VE::V42 }, |
| 1094 | { VE::V43 }, |
| 1095 | { VE::V44 }, |
| 1096 | { VE::V45 }, |
| 1097 | { VE::V46 }, |
| 1098 | { VE::V47 }, |
| 1099 | { VE::V48 }, |
| 1100 | { VE::V49 }, |
| 1101 | { VE::V50 }, |
| 1102 | { VE::V51 }, |
| 1103 | { VE::V52 }, |
| 1104 | { VE::V53 }, |
| 1105 | { VE::V54 }, |
| 1106 | { VE::V55 }, |
| 1107 | { VE::V56 }, |
| 1108 | { VE::V57 }, |
| 1109 | { VE::V58 }, |
| 1110 | { VE::V59 }, |
| 1111 | { VE::V60 }, |
| 1112 | { VE::V61 }, |
| 1113 | { VE::V62 }, |
| 1114 | { VE::V63 }, |
| 1115 | { VE::VM0 }, |
| 1116 | { VE::VM1 }, |
| 1117 | { VE::VM2 }, |
| 1118 | { VE::VM3 }, |
| 1119 | { VE::VM4 }, |
| 1120 | { VE::VM5 }, |
| 1121 | { VE::VM6 }, |
| 1122 | { VE::VM7 }, |
| 1123 | { VE::VM8 }, |
| 1124 | { VE::VM9 }, |
| 1125 | { VE::VM10 }, |
| 1126 | { VE::VM11 }, |
| 1127 | { VE::VM12 }, |
| 1128 | { VE::VM13 }, |
| 1129 | { VE::VM14 }, |
| 1130 | { VE::VM15 }, |
| 1131 | { VE::VMP0 }, |
| 1132 | }; |
| 1133 | |
| 1134 | namespace { // Register classes... |
| 1135 | // F32 Register Class... |
| 1136 | const MCPhysReg F32[] = { |
| 1137 | VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, VE::SF7, VE::SF34, VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, VE::SF63, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, |
| 1138 | }; |
| 1139 | |
| 1140 | // F32 Bit set. |
| 1141 | const uint8_t F32Bits[] = { |
| 1142 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, |
| 1143 | }; |
| 1144 | |
| 1145 | // I32 Register Class... |
| 1146 | const MCPhysReg I32[] = { |
| 1147 | VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, VE::SW7, VE::SW34, VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, VE::SW63, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, |
| 1148 | }; |
| 1149 | |
| 1150 | // I32 Bit set. |
| 1151 | const uint8_t I32Bits[] = { |
| 1152 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, |
| 1153 | }; |
| 1154 | |
| 1155 | // VLS Register Class... |
| 1156 | const MCPhysReg VLS[] = { |
| 1157 | VE::VL, |
| 1158 | }; |
| 1159 | |
| 1160 | // VLS Bit set. |
| 1161 | const uint8_t VLSBits[] = { |
| 1162 | 0x80, |
| 1163 | }; |
| 1164 | |
| 1165 | // I64 Register Class... |
| 1166 | const MCPhysReg I64[] = { |
| 1167 | VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, VE::SX63, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, |
| 1168 | }; |
| 1169 | |
| 1170 | // I64 Bit set. |
| 1171 | const uint8_t I64Bits[] = { |
| 1172 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, |
| 1173 | }; |
| 1174 | |
| 1175 | // MISC Register Class... |
| 1176 | const MCPhysReg MISC[] = { |
| 1177 | VE::USRCC, VE::PSW, VE::SAR, VE::PMMR, VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, VE::PMC12, VE::PMC13, VE::PMC14, |
| 1178 | }; |
| 1179 | |
| 1180 | // MISC Bit set. |
| 1181 | const uint8_t MISCBits[] = { |
| 1182 | 0x3c, 0xff, 0xff, 0x07, |
| 1183 | }; |
| 1184 | |
| 1185 | // F128 Register Class... |
| 1186 | const MCPhysReg F128[] = { |
| 1187 | VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31, VE::Q4, VE::Q5, VE::Q6, VE::Q7, VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15, VE::Q16, |
| 1188 | }; |
| 1189 | |
| 1190 | // F128 Bit set. |
| 1191 | const uint8_t F128Bits[] = { |
| 1192 | 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| 1193 | }; |
| 1194 | |
| 1195 | // VM Register Class... |
| 1196 | const MCPhysReg VM[] = { |
| 1197 | VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, |
| 1198 | }; |
| 1199 | |
| 1200 | // VM Bit set. |
| 1201 | const uint8_t VMBits[] = { |
| 1202 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, |
| 1203 | }; |
| 1204 | |
| 1205 | // VM512 Register Class... |
| 1206 | const MCPhysReg VM512[] = { |
| 1207 | VE::VMP0, VE::VMP1, VE::VMP2, VE::VMP3, VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7, |
| 1208 | }; |
| 1209 | |
| 1210 | // VM512 Bit set. |
| 1211 | const uint8_t VM512Bits[] = { |
| 1212 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, |
| 1213 | }; |
| 1214 | |
| 1215 | // VM512_with_sub_vm_even Register Class... |
| 1216 | const MCPhysReg VM512_with_sub_vm_even[] = { |
| 1217 | VE::VMP1, VE::VMP2, VE::VMP3, VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7, |
| 1218 | }; |
| 1219 | |
| 1220 | // VM512_with_sub_vm_even Bit set. |
| 1221 | const uint8_t VM512_with_sub_vm_evenBits[] = { |
| 1222 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, |
| 1223 | }; |
| 1224 | |
| 1225 | // V64 Register Class... |
| 1226 | const MCPhysReg V64[] = { |
| 1227 | VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VIX, |
| 1228 | }; |
| 1229 | |
| 1230 | // V64 Bit set. |
| 1231 | const uint8_t V64Bits[] = { |
| 1232 | 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, |
| 1233 | }; |
| 1234 | |
| 1235 | } // end anonymous namespace |
| 1236 | |
| 1237 | |
| 1238 | #ifdef __GNUC__ |
| 1239 | #pragma GCC diagnostic push |
| 1240 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 1241 | #endif |
| 1242 | extern const char VERegClassStrings[] = { |
| 1243 | /* 0 */ "VM512\000" |
| 1244 | /* 6 */ "F32\000" |
| 1245 | /* 10 */ "I32\000" |
| 1246 | /* 14 */ "I64\000" |
| 1247 | /* 18 */ "V64\000" |
| 1248 | /* 22 */ "F128\000" |
| 1249 | /* 27 */ "MISC\000" |
| 1250 | /* 32 */ "VM\000" |
| 1251 | /* 35 */ "VLS\000" |
| 1252 | /* 39 */ "VM512_with_sub_vm_even\000" |
| 1253 | }; |
| 1254 | #ifdef __GNUC__ |
| 1255 | #pragma GCC diagnostic pop |
| 1256 | #endif |
| 1257 | |
| 1258 | extern const MCRegisterClass VEMCRegisterClasses[] = { |
| 1259 | { .RegsBegin: F32, .RegSet: F32Bits, .NameIdx: 6, .RegsSize: 64, .RegSetSize: sizeof(F32Bits), .ID: VE::F32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1260 | { .RegsBegin: I32, .RegSet: I32Bits, .NameIdx: 10, .RegsSize: 64, .RegSetSize: sizeof(I32Bits), .ID: VE::I32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1261 | { .RegsBegin: VLS, .RegSet: VLSBits, .NameIdx: 35, .RegsSize: 1, .RegSetSize: sizeof(VLSBits), .ID: VE::VLSRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1262 | { .RegsBegin: I64, .RegSet: I64Bits, .NameIdx: 14, .RegsSize: 64, .RegSetSize: sizeof(I64Bits), .ID: VE::I64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1263 | { .RegsBegin: MISC, .RegSet: MISCBits, .NameIdx: 27, .RegsSize: 23, .RegSetSize: sizeof(MISCBits), .ID: VE::MISCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1264 | { .RegsBegin: F128, .RegSet: F128Bits, .NameIdx: 22, .RegsSize: 32, .RegSetSize: sizeof(F128Bits), .ID: VE::F128RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1265 | { .RegsBegin: VM, .RegSet: VMBits, .NameIdx: 32, .RegsSize: 16, .RegSetSize: sizeof(VMBits), .ID: VE::VMRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1266 | { .RegsBegin: VM512, .RegSet: VM512Bits, .NameIdx: 0, .RegsSize: 8, .RegSetSize: sizeof(VM512Bits), .ID: VE::VM512RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1267 | { .RegsBegin: VM512_with_sub_vm_even, .RegSet: VM512_with_sub_vm_evenBits, .NameIdx: 39, .RegsSize: 7, .RegSetSize: sizeof(VM512_with_sub_vm_evenBits), .ID: VE::VM512_with_sub_vm_evenRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1268 | { .RegsBegin: V64, .RegSet: V64Bits, .NameIdx: 18, .RegsSize: 65, .RegSetSize: sizeof(V64Bits), .ID: VE::V64RegClassID, .RegSizeInBits: 16384, .CopyCost: 1, .Allocatable: true, .BaseClass: false }, |
| 1269 | }; |
| 1270 | |
| 1271 | // VE Dwarf<->LLVM register mappings. |
| 1272 | extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[] = { |
| 1273 | { .FromReg: 0U, .ToReg: VE::SX0 }, |
| 1274 | { .FromReg: 1U, .ToReg: VE::SX1 }, |
| 1275 | { .FromReg: 2U, .ToReg: VE::SX2 }, |
| 1276 | { .FromReg: 3U, .ToReg: VE::SX3 }, |
| 1277 | { .FromReg: 4U, .ToReg: VE::SX4 }, |
| 1278 | { .FromReg: 5U, .ToReg: VE::SX5 }, |
| 1279 | { .FromReg: 6U, .ToReg: VE::SX6 }, |
| 1280 | { .FromReg: 7U, .ToReg: VE::SX7 }, |
| 1281 | { .FromReg: 8U, .ToReg: VE::SX8 }, |
| 1282 | { .FromReg: 9U, .ToReg: VE::SX9 }, |
| 1283 | { .FromReg: 10U, .ToReg: VE::SX10 }, |
| 1284 | { .FromReg: 11U, .ToReg: VE::SX11 }, |
| 1285 | { .FromReg: 12U, .ToReg: VE::SX12 }, |
| 1286 | { .FromReg: 13U, .ToReg: VE::SX13 }, |
| 1287 | { .FromReg: 14U, .ToReg: VE::SX14 }, |
| 1288 | { .FromReg: 15U, .ToReg: VE::SX15 }, |
| 1289 | { .FromReg: 16U, .ToReg: VE::SX16 }, |
| 1290 | { .FromReg: 17U, .ToReg: VE::SX17 }, |
| 1291 | { .FromReg: 18U, .ToReg: VE::SX18 }, |
| 1292 | { .FromReg: 19U, .ToReg: VE::SX19 }, |
| 1293 | { .FromReg: 20U, .ToReg: VE::SX20 }, |
| 1294 | { .FromReg: 21U, .ToReg: VE::SX21 }, |
| 1295 | { .FromReg: 22U, .ToReg: VE::SX22 }, |
| 1296 | { .FromReg: 23U, .ToReg: VE::SX23 }, |
| 1297 | { .FromReg: 24U, .ToReg: VE::SX24 }, |
| 1298 | { .FromReg: 25U, .ToReg: VE::SX25 }, |
| 1299 | { .FromReg: 26U, .ToReg: VE::SX26 }, |
| 1300 | { .FromReg: 27U, .ToReg: VE::SX27 }, |
| 1301 | { .FromReg: 28U, .ToReg: VE::SX28 }, |
| 1302 | { .FromReg: 29U, .ToReg: VE::SX29 }, |
| 1303 | { .FromReg: 30U, .ToReg: VE::SX30 }, |
| 1304 | { .FromReg: 31U, .ToReg: VE::SX31 }, |
| 1305 | { .FromReg: 32U, .ToReg: VE::SX32 }, |
| 1306 | { .FromReg: 33U, .ToReg: VE::SX33 }, |
| 1307 | { .FromReg: 34U, .ToReg: VE::SX34 }, |
| 1308 | { .FromReg: 35U, .ToReg: VE::SX35 }, |
| 1309 | { .FromReg: 36U, .ToReg: VE::SX36 }, |
| 1310 | { .FromReg: 37U, .ToReg: VE::SX37 }, |
| 1311 | { .FromReg: 38U, .ToReg: VE::SX38 }, |
| 1312 | { .FromReg: 39U, .ToReg: VE::SX39 }, |
| 1313 | { .FromReg: 40U, .ToReg: VE::SX40 }, |
| 1314 | { .FromReg: 41U, .ToReg: VE::SX41 }, |
| 1315 | { .FromReg: 42U, .ToReg: VE::SX42 }, |
| 1316 | { .FromReg: 43U, .ToReg: VE::SX43 }, |
| 1317 | { .FromReg: 44U, .ToReg: VE::SX44 }, |
| 1318 | { .FromReg: 45U, .ToReg: VE::SX45 }, |
| 1319 | { .FromReg: 46U, .ToReg: VE::SX46 }, |
| 1320 | { .FromReg: 47U, .ToReg: VE::SX47 }, |
| 1321 | { .FromReg: 48U, .ToReg: VE::SX48 }, |
| 1322 | { .FromReg: 49U, .ToReg: VE::SX49 }, |
| 1323 | { .FromReg: 50U, .ToReg: VE::SX50 }, |
| 1324 | { .FromReg: 51U, .ToReg: VE::SX51 }, |
| 1325 | { .FromReg: 52U, .ToReg: VE::SX52 }, |
| 1326 | { .FromReg: 53U, .ToReg: VE::SX53 }, |
| 1327 | { .FromReg: 54U, .ToReg: VE::SX54 }, |
| 1328 | { .FromReg: 55U, .ToReg: VE::SX55 }, |
| 1329 | { .FromReg: 56U, .ToReg: VE::SX56 }, |
| 1330 | { .FromReg: 57U, .ToReg: VE::SX57 }, |
| 1331 | { .FromReg: 58U, .ToReg: VE::SX58 }, |
| 1332 | { .FromReg: 59U, .ToReg: VE::SX59 }, |
| 1333 | { .FromReg: 60U, .ToReg: VE::SX60 }, |
| 1334 | { .FromReg: 61U, .ToReg: VE::SX61 }, |
| 1335 | { .FromReg: 62U, .ToReg: VE::SX62 }, |
| 1336 | { .FromReg: 63U, .ToReg: VE::SX63 }, |
| 1337 | { .FromReg: 64U, .ToReg: VE::V0 }, |
| 1338 | { .FromReg: 65U, .ToReg: VE::V1 }, |
| 1339 | { .FromReg: 66U, .ToReg: VE::V2 }, |
| 1340 | { .FromReg: 67U, .ToReg: VE::V3 }, |
| 1341 | { .FromReg: 68U, .ToReg: VE::V4 }, |
| 1342 | { .FromReg: 69U, .ToReg: VE::V5 }, |
| 1343 | { .FromReg: 70U, .ToReg: VE::V6 }, |
| 1344 | { .FromReg: 71U, .ToReg: VE::V7 }, |
| 1345 | { .FromReg: 72U, .ToReg: VE::V8 }, |
| 1346 | { .FromReg: 73U, .ToReg: VE::V9 }, |
| 1347 | { .FromReg: 74U, .ToReg: VE::V10 }, |
| 1348 | { .FromReg: 75U, .ToReg: VE::V11 }, |
| 1349 | { .FromReg: 76U, .ToReg: VE::V12 }, |
| 1350 | { .FromReg: 77U, .ToReg: VE::V13 }, |
| 1351 | { .FromReg: 78U, .ToReg: VE::V14 }, |
| 1352 | { .FromReg: 79U, .ToReg: VE::V15 }, |
| 1353 | { .FromReg: 80U, .ToReg: VE::V16 }, |
| 1354 | { .FromReg: 81U, .ToReg: VE::V17 }, |
| 1355 | { .FromReg: 82U, .ToReg: VE::V18 }, |
| 1356 | { .FromReg: 83U, .ToReg: VE::V19 }, |
| 1357 | { .FromReg: 84U, .ToReg: VE::V20 }, |
| 1358 | { .FromReg: 85U, .ToReg: VE::V21 }, |
| 1359 | { .FromReg: 86U, .ToReg: VE::V22 }, |
| 1360 | { .FromReg: 87U, .ToReg: VE::V23 }, |
| 1361 | { .FromReg: 88U, .ToReg: VE::V24 }, |
| 1362 | { .FromReg: 89U, .ToReg: VE::V25 }, |
| 1363 | { .FromReg: 90U, .ToReg: VE::V26 }, |
| 1364 | { .FromReg: 91U, .ToReg: VE::V27 }, |
| 1365 | { .FromReg: 92U, .ToReg: VE::V28 }, |
| 1366 | { .FromReg: 93U, .ToReg: VE::V29 }, |
| 1367 | { .FromReg: 94U, .ToReg: VE::V30 }, |
| 1368 | { .FromReg: 95U, .ToReg: VE::V31 }, |
| 1369 | { .FromReg: 96U, .ToReg: VE::V32 }, |
| 1370 | { .FromReg: 97U, .ToReg: VE::V33 }, |
| 1371 | { .FromReg: 98U, .ToReg: VE::V34 }, |
| 1372 | { .FromReg: 99U, .ToReg: VE::V35 }, |
| 1373 | { .FromReg: 100U, .ToReg: VE::V36 }, |
| 1374 | { .FromReg: 101U, .ToReg: VE::V37 }, |
| 1375 | { .FromReg: 102U, .ToReg: VE::V38 }, |
| 1376 | { .FromReg: 103U, .ToReg: VE::V39 }, |
| 1377 | { .FromReg: 104U, .ToReg: VE::V40 }, |
| 1378 | { .FromReg: 105U, .ToReg: VE::V41 }, |
| 1379 | { .FromReg: 106U, .ToReg: VE::V42 }, |
| 1380 | { .FromReg: 107U, .ToReg: VE::V43 }, |
| 1381 | { .FromReg: 108U, .ToReg: VE::V44 }, |
| 1382 | { .FromReg: 109U, .ToReg: VE::V45 }, |
| 1383 | { .FromReg: 110U, .ToReg: VE::V46 }, |
| 1384 | { .FromReg: 111U, .ToReg: VE::V47 }, |
| 1385 | { .FromReg: 112U, .ToReg: VE::V48 }, |
| 1386 | { .FromReg: 113U, .ToReg: VE::V49 }, |
| 1387 | { .FromReg: 114U, .ToReg: VE::V50 }, |
| 1388 | { .FromReg: 115U, .ToReg: VE::V51 }, |
| 1389 | { .FromReg: 116U, .ToReg: VE::V52 }, |
| 1390 | { .FromReg: 117U, .ToReg: VE::V53 }, |
| 1391 | { .FromReg: 118U, .ToReg: VE::V54 }, |
| 1392 | { .FromReg: 119U, .ToReg: VE::V55 }, |
| 1393 | { .FromReg: 120U, .ToReg: VE::V56 }, |
| 1394 | { .FromReg: 121U, .ToReg: VE::V57 }, |
| 1395 | { .FromReg: 122U, .ToReg: VE::V58 }, |
| 1396 | { .FromReg: 123U, .ToReg: VE::V59 }, |
| 1397 | { .FromReg: 124U, .ToReg: VE::V60 }, |
| 1398 | { .FromReg: 125U, .ToReg: VE::V61 }, |
| 1399 | { .FromReg: 126U, .ToReg: VE::V62 }, |
| 1400 | { .FromReg: 127U, .ToReg: VE::V63 }, |
| 1401 | { .FromReg: 128U, .ToReg: VE::VM0 }, |
| 1402 | { .FromReg: 129U, .ToReg: VE::VM1 }, |
| 1403 | { .FromReg: 130U, .ToReg: VE::VM2 }, |
| 1404 | { .FromReg: 131U, .ToReg: VE::VM3 }, |
| 1405 | { .FromReg: 132U, .ToReg: VE::VM4 }, |
| 1406 | { .FromReg: 133U, .ToReg: VE::VM5 }, |
| 1407 | { .FromReg: 134U, .ToReg: VE::VM6 }, |
| 1408 | { .FromReg: 135U, .ToReg: VE::VM7 }, |
| 1409 | { .FromReg: 136U, .ToReg: VE::VM8 }, |
| 1410 | { .FromReg: 137U, .ToReg: VE::VM9 }, |
| 1411 | { .FromReg: 138U, .ToReg: VE::VM10 }, |
| 1412 | { .FromReg: 139U, .ToReg: VE::VM11 }, |
| 1413 | { .FromReg: 140U, .ToReg: VE::VM12 }, |
| 1414 | { .FromReg: 141U, .ToReg: VE::VM13 }, |
| 1415 | { .FromReg: 142U, .ToReg: VE::VM14 }, |
| 1416 | { .FromReg: 143U, .ToReg: VE::VM15 }, |
| 1417 | }; |
| 1418 | extern const unsigned VEDwarfFlavour0Dwarf2LSize = std::size(VEDwarfFlavour0Dwarf2L); |
| 1419 | |
| 1420 | extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[] = { |
| 1421 | { .FromReg: 0U, .ToReg: VE::SX0 }, |
| 1422 | { .FromReg: 1U, .ToReg: VE::SX1 }, |
| 1423 | { .FromReg: 2U, .ToReg: VE::SX2 }, |
| 1424 | { .FromReg: 3U, .ToReg: VE::SX3 }, |
| 1425 | { .FromReg: 4U, .ToReg: VE::SX4 }, |
| 1426 | { .FromReg: 5U, .ToReg: VE::SX5 }, |
| 1427 | { .FromReg: 6U, .ToReg: VE::SX6 }, |
| 1428 | { .FromReg: 7U, .ToReg: VE::SX7 }, |
| 1429 | { .FromReg: 8U, .ToReg: VE::SX8 }, |
| 1430 | { .FromReg: 9U, .ToReg: VE::SX9 }, |
| 1431 | { .FromReg: 10U, .ToReg: VE::SX10 }, |
| 1432 | { .FromReg: 11U, .ToReg: VE::SX11 }, |
| 1433 | { .FromReg: 12U, .ToReg: VE::SX12 }, |
| 1434 | { .FromReg: 13U, .ToReg: VE::SX13 }, |
| 1435 | { .FromReg: 14U, .ToReg: VE::SX14 }, |
| 1436 | { .FromReg: 15U, .ToReg: VE::SX15 }, |
| 1437 | { .FromReg: 16U, .ToReg: VE::SX16 }, |
| 1438 | { .FromReg: 17U, .ToReg: VE::SX17 }, |
| 1439 | { .FromReg: 18U, .ToReg: VE::SX18 }, |
| 1440 | { .FromReg: 19U, .ToReg: VE::SX19 }, |
| 1441 | { .FromReg: 20U, .ToReg: VE::SX20 }, |
| 1442 | { .FromReg: 21U, .ToReg: VE::SX21 }, |
| 1443 | { .FromReg: 22U, .ToReg: VE::SX22 }, |
| 1444 | { .FromReg: 23U, .ToReg: VE::SX23 }, |
| 1445 | { .FromReg: 24U, .ToReg: VE::SX24 }, |
| 1446 | { .FromReg: 25U, .ToReg: VE::SX25 }, |
| 1447 | { .FromReg: 26U, .ToReg: VE::SX26 }, |
| 1448 | { .FromReg: 27U, .ToReg: VE::SX27 }, |
| 1449 | { .FromReg: 28U, .ToReg: VE::SX28 }, |
| 1450 | { .FromReg: 29U, .ToReg: VE::SX29 }, |
| 1451 | { .FromReg: 30U, .ToReg: VE::SX30 }, |
| 1452 | { .FromReg: 31U, .ToReg: VE::SX31 }, |
| 1453 | { .FromReg: 32U, .ToReg: VE::SX32 }, |
| 1454 | { .FromReg: 33U, .ToReg: VE::SX33 }, |
| 1455 | { .FromReg: 34U, .ToReg: VE::SX34 }, |
| 1456 | { .FromReg: 35U, .ToReg: VE::SX35 }, |
| 1457 | { .FromReg: 36U, .ToReg: VE::SX36 }, |
| 1458 | { .FromReg: 37U, .ToReg: VE::SX37 }, |
| 1459 | { .FromReg: 38U, .ToReg: VE::SX38 }, |
| 1460 | { .FromReg: 39U, .ToReg: VE::SX39 }, |
| 1461 | { .FromReg: 40U, .ToReg: VE::SX40 }, |
| 1462 | { .FromReg: 41U, .ToReg: VE::SX41 }, |
| 1463 | { .FromReg: 42U, .ToReg: VE::SX42 }, |
| 1464 | { .FromReg: 43U, .ToReg: VE::SX43 }, |
| 1465 | { .FromReg: 44U, .ToReg: VE::SX44 }, |
| 1466 | { .FromReg: 45U, .ToReg: VE::SX45 }, |
| 1467 | { .FromReg: 46U, .ToReg: VE::SX46 }, |
| 1468 | { .FromReg: 47U, .ToReg: VE::SX47 }, |
| 1469 | { .FromReg: 48U, .ToReg: VE::SX48 }, |
| 1470 | { .FromReg: 49U, .ToReg: VE::SX49 }, |
| 1471 | { .FromReg: 50U, .ToReg: VE::SX50 }, |
| 1472 | { .FromReg: 51U, .ToReg: VE::SX51 }, |
| 1473 | { .FromReg: 52U, .ToReg: VE::SX52 }, |
| 1474 | { .FromReg: 53U, .ToReg: VE::SX53 }, |
| 1475 | { .FromReg: 54U, .ToReg: VE::SX54 }, |
| 1476 | { .FromReg: 55U, .ToReg: VE::SX55 }, |
| 1477 | { .FromReg: 56U, .ToReg: VE::SX56 }, |
| 1478 | { .FromReg: 57U, .ToReg: VE::SX57 }, |
| 1479 | { .FromReg: 58U, .ToReg: VE::SX58 }, |
| 1480 | { .FromReg: 59U, .ToReg: VE::SX59 }, |
| 1481 | { .FromReg: 60U, .ToReg: VE::SX60 }, |
| 1482 | { .FromReg: 61U, .ToReg: VE::SX61 }, |
| 1483 | { .FromReg: 62U, .ToReg: VE::SX62 }, |
| 1484 | { .FromReg: 63U, .ToReg: VE::SX63 }, |
| 1485 | { .FromReg: 64U, .ToReg: VE::V0 }, |
| 1486 | { .FromReg: 65U, .ToReg: VE::V1 }, |
| 1487 | { .FromReg: 66U, .ToReg: VE::V2 }, |
| 1488 | { .FromReg: 67U, .ToReg: VE::V3 }, |
| 1489 | { .FromReg: 68U, .ToReg: VE::V4 }, |
| 1490 | { .FromReg: 69U, .ToReg: VE::V5 }, |
| 1491 | { .FromReg: 70U, .ToReg: VE::V6 }, |
| 1492 | { .FromReg: 71U, .ToReg: VE::V7 }, |
| 1493 | { .FromReg: 72U, .ToReg: VE::V8 }, |
| 1494 | { .FromReg: 73U, .ToReg: VE::V9 }, |
| 1495 | { .FromReg: 74U, .ToReg: VE::V10 }, |
| 1496 | { .FromReg: 75U, .ToReg: VE::V11 }, |
| 1497 | { .FromReg: 76U, .ToReg: VE::V12 }, |
| 1498 | { .FromReg: 77U, .ToReg: VE::V13 }, |
| 1499 | { .FromReg: 78U, .ToReg: VE::V14 }, |
| 1500 | { .FromReg: 79U, .ToReg: VE::V15 }, |
| 1501 | { .FromReg: 80U, .ToReg: VE::V16 }, |
| 1502 | { .FromReg: 81U, .ToReg: VE::V17 }, |
| 1503 | { .FromReg: 82U, .ToReg: VE::V18 }, |
| 1504 | { .FromReg: 83U, .ToReg: VE::V19 }, |
| 1505 | { .FromReg: 84U, .ToReg: VE::V20 }, |
| 1506 | { .FromReg: 85U, .ToReg: VE::V21 }, |
| 1507 | { .FromReg: 86U, .ToReg: VE::V22 }, |
| 1508 | { .FromReg: 87U, .ToReg: VE::V23 }, |
| 1509 | { .FromReg: 88U, .ToReg: VE::V24 }, |
| 1510 | { .FromReg: 89U, .ToReg: VE::V25 }, |
| 1511 | { .FromReg: 90U, .ToReg: VE::V26 }, |
| 1512 | { .FromReg: 91U, .ToReg: VE::V27 }, |
| 1513 | { .FromReg: 92U, .ToReg: VE::V28 }, |
| 1514 | { .FromReg: 93U, .ToReg: VE::V29 }, |
| 1515 | { .FromReg: 94U, .ToReg: VE::V30 }, |
| 1516 | { .FromReg: 95U, .ToReg: VE::V31 }, |
| 1517 | { .FromReg: 96U, .ToReg: VE::V32 }, |
| 1518 | { .FromReg: 97U, .ToReg: VE::V33 }, |
| 1519 | { .FromReg: 98U, .ToReg: VE::V34 }, |
| 1520 | { .FromReg: 99U, .ToReg: VE::V35 }, |
| 1521 | { .FromReg: 100U, .ToReg: VE::V36 }, |
| 1522 | { .FromReg: 101U, .ToReg: VE::V37 }, |
| 1523 | { .FromReg: 102U, .ToReg: VE::V38 }, |
| 1524 | { .FromReg: 103U, .ToReg: VE::V39 }, |
| 1525 | { .FromReg: 104U, .ToReg: VE::V40 }, |
| 1526 | { .FromReg: 105U, .ToReg: VE::V41 }, |
| 1527 | { .FromReg: 106U, .ToReg: VE::V42 }, |
| 1528 | { .FromReg: 107U, .ToReg: VE::V43 }, |
| 1529 | { .FromReg: 108U, .ToReg: VE::V44 }, |
| 1530 | { .FromReg: 109U, .ToReg: VE::V45 }, |
| 1531 | { .FromReg: 110U, .ToReg: VE::V46 }, |
| 1532 | { .FromReg: 111U, .ToReg: VE::V47 }, |
| 1533 | { .FromReg: 112U, .ToReg: VE::V48 }, |
| 1534 | { .FromReg: 113U, .ToReg: VE::V49 }, |
| 1535 | { .FromReg: 114U, .ToReg: VE::V50 }, |
| 1536 | { .FromReg: 115U, .ToReg: VE::V51 }, |
| 1537 | { .FromReg: 116U, .ToReg: VE::V52 }, |
| 1538 | { .FromReg: 117U, .ToReg: VE::V53 }, |
| 1539 | { .FromReg: 118U, .ToReg: VE::V54 }, |
| 1540 | { .FromReg: 119U, .ToReg: VE::V55 }, |
| 1541 | { .FromReg: 120U, .ToReg: VE::V56 }, |
| 1542 | { .FromReg: 121U, .ToReg: VE::V57 }, |
| 1543 | { .FromReg: 122U, .ToReg: VE::V58 }, |
| 1544 | { .FromReg: 123U, .ToReg: VE::V59 }, |
| 1545 | { .FromReg: 124U, .ToReg: VE::V60 }, |
| 1546 | { .FromReg: 125U, .ToReg: VE::V61 }, |
| 1547 | { .FromReg: 126U, .ToReg: VE::V62 }, |
| 1548 | { .FromReg: 127U, .ToReg: VE::V63 }, |
| 1549 | { .FromReg: 128U, .ToReg: VE::VM0 }, |
| 1550 | { .FromReg: 129U, .ToReg: VE::VM1 }, |
| 1551 | { .FromReg: 130U, .ToReg: VE::VM2 }, |
| 1552 | { .FromReg: 131U, .ToReg: VE::VM3 }, |
| 1553 | { .FromReg: 132U, .ToReg: VE::VM4 }, |
| 1554 | { .FromReg: 133U, .ToReg: VE::VM5 }, |
| 1555 | { .FromReg: 134U, .ToReg: VE::VM6 }, |
| 1556 | { .FromReg: 135U, .ToReg: VE::VM7 }, |
| 1557 | { .FromReg: 136U, .ToReg: VE::VM8 }, |
| 1558 | { .FromReg: 137U, .ToReg: VE::VM9 }, |
| 1559 | { .FromReg: 138U, .ToReg: VE::VM10 }, |
| 1560 | { .FromReg: 139U, .ToReg: VE::VM11 }, |
| 1561 | { .FromReg: 140U, .ToReg: VE::VM12 }, |
| 1562 | { .FromReg: 141U, .ToReg: VE::VM13 }, |
| 1563 | { .FromReg: 142U, .ToReg: VE::VM14 }, |
| 1564 | { .FromReg: 143U, .ToReg: VE::VM15 }, |
| 1565 | }; |
| 1566 | extern const unsigned VEEHFlavour0Dwarf2LSize = std::size(VEEHFlavour0Dwarf2L); |
| 1567 | |
| 1568 | extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[] = { |
| 1569 | { .FromReg: VE::SF0, .ToReg: 0U }, |
| 1570 | { .FromReg: VE::SF1, .ToReg: 1U }, |
| 1571 | { .FromReg: VE::SF2, .ToReg: 2U }, |
| 1572 | { .FromReg: VE::SF3, .ToReg: 3U }, |
| 1573 | { .FromReg: VE::SF4, .ToReg: 4U }, |
| 1574 | { .FromReg: VE::SF5, .ToReg: 5U }, |
| 1575 | { .FromReg: VE::SF6, .ToReg: 6U }, |
| 1576 | { .FromReg: VE::SF7, .ToReg: 7U }, |
| 1577 | { .FromReg: VE::SF8, .ToReg: 8U }, |
| 1578 | { .FromReg: VE::SF9, .ToReg: 9U }, |
| 1579 | { .FromReg: VE::SF10, .ToReg: 10U }, |
| 1580 | { .FromReg: VE::SF11, .ToReg: 11U }, |
| 1581 | { .FromReg: VE::SF12, .ToReg: 12U }, |
| 1582 | { .FromReg: VE::SF13, .ToReg: 13U }, |
| 1583 | { .FromReg: VE::SF14, .ToReg: 14U }, |
| 1584 | { .FromReg: VE::SF15, .ToReg: 15U }, |
| 1585 | { .FromReg: VE::SF16, .ToReg: 16U }, |
| 1586 | { .FromReg: VE::SF17, .ToReg: 17U }, |
| 1587 | { .FromReg: VE::SF18, .ToReg: 18U }, |
| 1588 | { .FromReg: VE::SF19, .ToReg: 19U }, |
| 1589 | { .FromReg: VE::SF20, .ToReg: 20U }, |
| 1590 | { .FromReg: VE::SF21, .ToReg: 21U }, |
| 1591 | { .FromReg: VE::SF22, .ToReg: 22U }, |
| 1592 | { .FromReg: VE::SF23, .ToReg: 23U }, |
| 1593 | { .FromReg: VE::SF24, .ToReg: 24U }, |
| 1594 | { .FromReg: VE::SF25, .ToReg: 25U }, |
| 1595 | { .FromReg: VE::SF26, .ToReg: 26U }, |
| 1596 | { .FromReg: VE::SF27, .ToReg: 27U }, |
| 1597 | { .FromReg: VE::SF28, .ToReg: 28U }, |
| 1598 | { .FromReg: VE::SF29, .ToReg: 29U }, |
| 1599 | { .FromReg: VE::SF30, .ToReg: 30U }, |
| 1600 | { .FromReg: VE::SF31, .ToReg: 31U }, |
| 1601 | { .FromReg: VE::SF32, .ToReg: 32U }, |
| 1602 | { .FromReg: VE::SF33, .ToReg: 33U }, |
| 1603 | { .FromReg: VE::SF34, .ToReg: 34U }, |
| 1604 | { .FromReg: VE::SF35, .ToReg: 35U }, |
| 1605 | { .FromReg: VE::SF36, .ToReg: 36U }, |
| 1606 | { .FromReg: VE::SF37, .ToReg: 37U }, |
| 1607 | { .FromReg: VE::SF38, .ToReg: 38U }, |
| 1608 | { .FromReg: VE::SF39, .ToReg: 39U }, |
| 1609 | { .FromReg: VE::SF40, .ToReg: 40U }, |
| 1610 | { .FromReg: VE::SF41, .ToReg: 41U }, |
| 1611 | { .FromReg: VE::SF42, .ToReg: 42U }, |
| 1612 | { .FromReg: VE::SF43, .ToReg: 43U }, |
| 1613 | { .FromReg: VE::SF44, .ToReg: 44U }, |
| 1614 | { .FromReg: VE::SF45, .ToReg: 45U }, |
| 1615 | { .FromReg: VE::SF46, .ToReg: 46U }, |
| 1616 | { .FromReg: VE::SF47, .ToReg: 47U }, |
| 1617 | { .FromReg: VE::SF48, .ToReg: 48U }, |
| 1618 | { .FromReg: VE::SF49, .ToReg: 49U }, |
| 1619 | { .FromReg: VE::SF50, .ToReg: 50U }, |
| 1620 | { .FromReg: VE::SF51, .ToReg: 51U }, |
| 1621 | { .FromReg: VE::SF52, .ToReg: 52U }, |
| 1622 | { .FromReg: VE::SF53, .ToReg: 53U }, |
| 1623 | { .FromReg: VE::SF54, .ToReg: 54U }, |
| 1624 | { .FromReg: VE::SF55, .ToReg: 55U }, |
| 1625 | { .FromReg: VE::SF56, .ToReg: 56U }, |
| 1626 | { .FromReg: VE::SF57, .ToReg: 57U }, |
| 1627 | { .FromReg: VE::SF58, .ToReg: 58U }, |
| 1628 | { .FromReg: VE::SF59, .ToReg: 59U }, |
| 1629 | { .FromReg: VE::SF60, .ToReg: 60U }, |
| 1630 | { .FromReg: VE::SF61, .ToReg: 61U }, |
| 1631 | { .FromReg: VE::SF62, .ToReg: 62U }, |
| 1632 | { .FromReg: VE::SF63, .ToReg: 63U }, |
| 1633 | { .FromReg: VE::SW0, .ToReg: 0U }, |
| 1634 | { .FromReg: VE::SW1, .ToReg: 1U }, |
| 1635 | { .FromReg: VE::SW2, .ToReg: 2U }, |
| 1636 | { .FromReg: VE::SW3, .ToReg: 3U }, |
| 1637 | { .FromReg: VE::SW4, .ToReg: 4U }, |
| 1638 | { .FromReg: VE::SW5, .ToReg: 5U }, |
| 1639 | { .FromReg: VE::SW6, .ToReg: 6U }, |
| 1640 | { .FromReg: VE::SW7, .ToReg: 7U }, |
| 1641 | { .FromReg: VE::SW8, .ToReg: 8U }, |
| 1642 | { .FromReg: VE::SW9, .ToReg: 9U }, |
| 1643 | { .FromReg: VE::SW10, .ToReg: 10U }, |
| 1644 | { .FromReg: VE::SW11, .ToReg: 11U }, |
| 1645 | { .FromReg: VE::SW12, .ToReg: 12U }, |
| 1646 | { .FromReg: VE::SW13, .ToReg: 13U }, |
| 1647 | { .FromReg: VE::SW14, .ToReg: 14U }, |
| 1648 | { .FromReg: VE::SW15, .ToReg: 15U }, |
| 1649 | { .FromReg: VE::SW16, .ToReg: 16U }, |
| 1650 | { .FromReg: VE::SW17, .ToReg: 17U }, |
| 1651 | { .FromReg: VE::SW18, .ToReg: 18U }, |
| 1652 | { .FromReg: VE::SW19, .ToReg: 19U }, |
| 1653 | { .FromReg: VE::SW20, .ToReg: 20U }, |
| 1654 | { .FromReg: VE::SW21, .ToReg: 21U }, |
| 1655 | { .FromReg: VE::SW22, .ToReg: 22U }, |
| 1656 | { .FromReg: VE::SW23, .ToReg: 23U }, |
| 1657 | { .FromReg: VE::SW24, .ToReg: 24U }, |
| 1658 | { .FromReg: VE::SW25, .ToReg: 25U }, |
| 1659 | { .FromReg: VE::SW26, .ToReg: 26U }, |
| 1660 | { .FromReg: VE::SW27, .ToReg: 27U }, |
| 1661 | { .FromReg: VE::SW28, .ToReg: 28U }, |
| 1662 | { .FromReg: VE::SW29, .ToReg: 29U }, |
| 1663 | { .FromReg: VE::SW30, .ToReg: 30U }, |
| 1664 | { .FromReg: VE::SW31, .ToReg: 31U }, |
| 1665 | { .FromReg: VE::SW32, .ToReg: 32U }, |
| 1666 | { .FromReg: VE::SW33, .ToReg: 33U }, |
| 1667 | { .FromReg: VE::SW34, .ToReg: 34U }, |
| 1668 | { .FromReg: VE::SW35, .ToReg: 35U }, |
| 1669 | { .FromReg: VE::SW36, .ToReg: 36U }, |
| 1670 | { .FromReg: VE::SW37, .ToReg: 37U }, |
| 1671 | { .FromReg: VE::SW38, .ToReg: 38U }, |
| 1672 | { .FromReg: VE::SW39, .ToReg: 39U }, |
| 1673 | { .FromReg: VE::SW40, .ToReg: 40U }, |
| 1674 | { .FromReg: VE::SW41, .ToReg: 41U }, |
| 1675 | { .FromReg: VE::SW42, .ToReg: 42U }, |
| 1676 | { .FromReg: VE::SW43, .ToReg: 43U }, |
| 1677 | { .FromReg: VE::SW44, .ToReg: 44U }, |
| 1678 | { .FromReg: VE::SW45, .ToReg: 45U }, |
| 1679 | { .FromReg: VE::SW46, .ToReg: 46U }, |
| 1680 | { .FromReg: VE::SW47, .ToReg: 47U }, |
| 1681 | { .FromReg: VE::SW48, .ToReg: 48U }, |
| 1682 | { .FromReg: VE::SW49, .ToReg: 49U }, |
| 1683 | { .FromReg: VE::SW50, .ToReg: 50U }, |
| 1684 | { .FromReg: VE::SW51, .ToReg: 51U }, |
| 1685 | { .FromReg: VE::SW52, .ToReg: 52U }, |
| 1686 | { .FromReg: VE::SW53, .ToReg: 53U }, |
| 1687 | { .FromReg: VE::SW54, .ToReg: 54U }, |
| 1688 | { .FromReg: VE::SW55, .ToReg: 55U }, |
| 1689 | { .FromReg: VE::SW56, .ToReg: 56U }, |
| 1690 | { .FromReg: VE::SW57, .ToReg: 57U }, |
| 1691 | { .FromReg: VE::SW58, .ToReg: 58U }, |
| 1692 | { .FromReg: VE::SW59, .ToReg: 59U }, |
| 1693 | { .FromReg: VE::SW60, .ToReg: 60U }, |
| 1694 | { .FromReg: VE::SW61, .ToReg: 61U }, |
| 1695 | { .FromReg: VE::SW62, .ToReg: 62U }, |
| 1696 | { .FromReg: VE::SW63, .ToReg: 63U }, |
| 1697 | { .FromReg: VE::SX0, .ToReg: 0U }, |
| 1698 | { .FromReg: VE::SX1, .ToReg: 1U }, |
| 1699 | { .FromReg: VE::SX2, .ToReg: 2U }, |
| 1700 | { .FromReg: VE::SX3, .ToReg: 3U }, |
| 1701 | { .FromReg: VE::SX4, .ToReg: 4U }, |
| 1702 | { .FromReg: VE::SX5, .ToReg: 5U }, |
| 1703 | { .FromReg: VE::SX6, .ToReg: 6U }, |
| 1704 | { .FromReg: VE::SX7, .ToReg: 7U }, |
| 1705 | { .FromReg: VE::SX8, .ToReg: 8U }, |
| 1706 | { .FromReg: VE::SX9, .ToReg: 9U }, |
| 1707 | { .FromReg: VE::SX10, .ToReg: 10U }, |
| 1708 | { .FromReg: VE::SX11, .ToReg: 11U }, |
| 1709 | { .FromReg: VE::SX12, .ToReg: 12U }, |
| 1710 | { .FromReg: VE::SX13, .ToReg: 13U }, |
| 1711 | { .FromReg: VE::SX14, .ToReg: 14U }, |
| 1712 | { .FromReg: VE::SX15, .ToReg: 15U }, |
| 1713 | { .FromReg: VE::SX16, .ToReg: 16U }, |
| 1714 | { .FromReg: VE::SX17, .ToReg: 17U }, |
| 1715 | { .FromReg: VE::SX18, .ToReg: 18U }, |
| 1716 | { .FromReg: VE::SX19, .ToReg: 19U }, |
| 1717 | { .FromReg: VE::SX20, .ToReg: 20U }, |
| 1718 | { .FromReg: VE::SX21, .ToReg: 21U }, |
| 1719 | { .FromReg: VE::SX22, .ToReg: 22U }, |
| 1720 | { .FromReg: VE::SX23, .ToReg: 23U }, |
| 1721 | { .FromReg: VE::SX24, .ToReg: 24U }, |
| 1722 | { .FromReg: VE::SX25, .ToReg: 25U }, |
| 1723 | { .FromReg: VE::SX26, .ToReg: 26U }, |
| 1724 | { .FromReg: VE::SX27, .ToReg: 27U }, |
| 1725 | { .FromReg: VE::SX28, .ToReg: 28U }, |
| 1726 | { .FromReg: VE::SX29, .ToReg: 29U }, |
| 1727 | { .FromReg: VE::SX30, .ToReg: 30U }, |
| 1728 | { .FromReg: VE::SX31, .ToReg: 31U }, |
| 1729 | { .FromReg: VE::SX32, .ToReg: 32U }, |
| 1730 | { .FromReg: VE::SX33, .ToReg: 33U }, |
| 1731 | { .FromReg: VE::SX34, .ToReg: 34U }, |
| 1732 | { .FromReg: VE::SX35, .ToReg: 35U }, |
| 1733 | { .FromReg: VE::SX36, .ToReg: 36U }, |
| 1734 | { .FromReg: VE::SX37, .ToReg: 37U }, |
| 1735 | { .FromReg: VE::SX38, .ToReg: 38U }, |
| 1736 | { .FromReg: VE::SX39, .ToReg: 39U }, |
| 1737 | { .FromReg: VE::SX40, .ToReg: 40U }, |
| 1738 | { .FromReg: VE::SX41, .ToReg: 41U }, |
| 1739 | { .FromReg: VE::SX42, .ToReg: 42U }, |
| 1740 | { .FromReg: VE::SX43, .ToReg: 43U }, |
| 1741 | { .FromReg: VE::SX44, .ToReg: 44U }, |
| 1742 | { .FromReg: VE::SX45, .ToReg: 45U }, |
| 1743 | { .FromReg: VE::SX46, .ToReg: 46U }, |
| 1744 | { .FromReg: VE::SX47, .ToReg: 47U }, |
| 1745 | { .FromReg: VE::SX48, .ToReg: 48U }, |
| 1746 | { .FromReg: VE::SX49, .ToReg: 49U }, |
| 1747 | { .FromReg: VE::SX50, .ToReg: 50U }, |
| 1748 | { .FromReg: VE::SX51, .ToReg: 51U }, |
| 1749 | { .FromReg: VE::SX52, .ToReg: 52U }, |
| 1750 | { .FromReg: VE::SX53, .ToReg: 53U }, |
| 1751 | { .FromReg: VE::SX54, .ToReg: 54U }, |
| 1752 | { .FromReg: VE::SX55, .ToReg: 55U }, |
| 1753 | { .FromReg: VE::SX56, .ToReg: 56U }, |
| 1754 | { .FromReg: VE::SX57, .ToReg: 57U }, |
| 1755 | { .FromReg: VE::SX58, .ToReg: 58U }, |
| 1756 | { .FromReg: VE::SX59, .ToReg: 59U }, |
| 1757 | { .FromReg: VE::SX60, .ToReg: 60U }, |
| 1758 | { .FromReg: VE::SX61, .ToReg: 61U }, |
| 1759 | { .FromReg: VE::SX62, .ToReg: 62U }, |
| 1760 | { .FromReg: VE::SX63, .ToReg: 63U }, |
| 1761 | { .FromReg: VE::V0, .ToReg: 64U }, |
| 1762 | { .FromReg: VE::V1, .ToReg: 65U }, |
| 1763 | { .FromReg: VE::V2, .ToReg: 66U }, |
| 1764 | { .FromReg: VE::V3, .ToReg: 67U }, |
| 1765 | { .FromReg: VE::V4, .ToReg: 68U }, |
| 1766 | { .FromReg: VE::V5, .ToReg: 69U }, |
| 1767 | { .FromReg: VE::V6, .ToReg: 70U }, |
| 1768 | { .FromReg: VE::V7, .ToReg: 71U }, |
| 1769 | { .FromReg: VE::V8, .ToReg: 72U }, |
| 1770 | { .FromReg: VE::V9, .ToReg: 73U }, |
| 1771 | { .FromReg: VE::V10, .ToReg: 74U }, |
| 1772 | { .FromReg: VE::V11, .ToReg: 75U }, |
| 1773 | { .FromReg: VE::V12, .ToReg: 76U }, |
| 1774 | { .FromReg: VE::V13, .ToReg: 77U }, |
| 1775 | { .FromReg: VE::V14, .ToReg: 78U }, |
| 1776 | { .FromReg: VE::V15, .ToReg: 79U }, |
| 1777 | { .FromReg: VE::V16, .ToReg: 80U }, |
| 1778 | { .FromReg: VE::V17, .ToReg: 81U }, |
| 1779 | { .FromReg: VE::V18, .ToReg: 82U }, |
| 1780 | { .FromReg: VE::V19, .ToReg: 83U }, |
| 1781 | { .FromReg: VE::V20, .ToReg: 84U }, |
| 1782 | { .FromReg: VE::V21, .ToReg: 85U }, |
| 1783 | { .FromReg: VE::V22, .ToReg: 86U }, |
| 1784 | { .FromReg: VE::V23, .ToReg: 87U }, |
| 1785 | { .FromReg: VE::V24, .ToReg: 88U }, |
| 1786 | { .FromReg: VE::V25, .ToReg: 89U }, |
| 1787 | { .FromReg: VE::V26, .ToReg: 90U }, |
| 1788 | { .FromReg: VE::V27, .ToReg: 91U }, |
| 1789 | { .FromReg: VE::V28, .ToReg: 92U }, |
| 1790 | { .FromReg: VE::V29, .ToReg: 93U }, |
| 1791 | { .FromReg: VE::V30, .ToReg: 94U }, |
| 1792 | { .FromReg: VE::V31, .ToReg: 95U }, |
| 1793 | { .FromReg: VE::V32, .ToReg: 96U }, |
| 1794 | { .FromReg: VE::V33, .ToReg: 97U }, |
| 1795 | { .FromReg: VE::V34, .ToReg: 98U }, |
| 1796 | { .FromReg: VE::V35, .ToReg: 99U }, |
| 1797 | { .FromReg: VE::V36, .ToReg: 100U }, |
| 1798 | { .FromReg: VE::V37, .ToReg: 101U }, |
| 1799 | { .FromReg: VE::V38, .ToReg: 102U }, |
| 1800 | { .FromReg: VE::V39, .ToReg: 103U }, |
| 1801 | { .FromReg: VE::V40, .ToReg: 104U }, |
| 1802 | { .FromReg: VE::V41, .ToReg: 105U }, |
| 1803 | { .FromReg: VE::V42, .ToReg: 106U }, |
| 1804 | { .FromReg: VE::V43, .ToReg: 107U }, |
| 1805 | { .FromReg: VE::V44, .ToReg: 108U }, |
| 1806 | { .FromReg: VE::V45, .ToReg: 109U }, |
| 1807 | { .FromReg: VE::V46, .ToReg: 110U }, |
| 1808 | { .FromReg: VE::V47, .ToReg: 111U }, |
| 1809 | { .FromReg: VE::V48, .ToReg: 112U }, |
| 1810 | { .FromReg: VE::V49, .ToReg: 113U }, |
| 1811 | { .FromReg: VE::V50, .ToReg: 114U }, |
| 1812 | { .FromReg: VE::V51, .ToReg: 115U }, |
| 1813 | { .FromReg: VE::V52, .ToReg: 116U }, |
| 1814 | { .FromReg: VE::V53, .ToReg: 117U }, |
| 1815 | { .FromReg: VE::V54, .ToReg: 118U }, |
| 1816 | { .FromReg: VE::V55, .ToReg: 119U }, |
| 1817 | { .FromReg: VE::V56, .ToReg: 120U }, |
| 1818 | { .FromReg: VE::V57, .ToReg: 121U }, |
| 1819 | { .FromReg: VE::V58, .ToReg: 122U }, |
| 1820 | { .FromReg: VE::V59, .ToReg: 123U }, |
| 1821 | { .FromReg: VE::V60, .ToReg: 124U }, |
| 1822 | { .FromReg: VE::V61, .ToReg: 125U }, |
| 1823 | { .FromReg: VE::V62, .ToReg: 126U }, |
| 1824 | { .FromReg: VE::V63, .ToReg: 127U }, |
| 1825 | { .FromReg: VE::VM0, .ToReg: 128U }, |
| 1826 | { .FromReg: VE::VM1, .ToReg: 129U }, |
| 1827 | { .FromReg: VE::VM2, .ToReg: 130U }, |
| 1828 | { .FromReg: VE::VM3, .ToReg: 131U }, |
| 1829 | { .FromReg: VE::VM4, .ToReg: 132U }, |
| 1830 | { .FromReg: VE::VM5, .ToReg: 133U }, |
| 1831 | { .FromReg: VE::VM6, .ToReg: 134U }, |
| 1832 | { .FromReg: VE::VM7, .ToReg: 135U }, |
| 1833 | { .FromReg: VE::VM8, .ToReg: 136U }, |
| 1834 | { .FromReg: VE::VM9, .ToReg: 137U }, |
| 1835 | { .FromReg: VE::VM10, .ToReg: 138U }, |
| 1836 | { .FromReg: VE::VM11, .ToReg: 139U }, |
| 1837 | { .FromReg: VE::VM12, .ToReg: 140U }, |
| 1838 | { .FromReg: VE::VM13, .ToReg: 141U }, |
| 1839 | { .FromReg: VE::VM14, .ToReg: 142U }, |
| 1840 | { .FromReg: VE::VM15, .ToReg: 143U }, |
| 1841 | }; |
| 1842 | extern const unsigned VEDwarfFlavour0L2DwarfSize = std::size(VEDwarfFlavour0L2Dwarf); |
| 1843 | |
| 1844 | extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[] = { |
| 1845 | { .FromReg: VE::SF0, .ToReg: 0U }, |
| 1846 | { .FromReg: VE::SF1, .ToReg: 1U }, |
| 1847 | { .FromReg: VE::SF2, .ToReg: 2U }, |
| 1848 | { .FromReg: VE::SF3, .ToReg: 3U }, |
| 1849 | { .FromReg: VE::SF4, .ToReg: 4U }, |
| 1850 | { .FromReg: VE::SF5, .ToReg: 5U }, |
| 1851 | { .FromReg: VE::SF6, .ToReg: 6U }, |
| 1852 | { .FromReg: VE::SF7, .ToReg: 7U }, |
| 1853 | { .FromReg: VE::SF8, .ToReg: 8U }, |
| 1854 | { .FromReg: VE::SF9, .ToReg: 9U }, |
| 1855 | { .FromReg: VE::SF10, .ToReg: 10U }, |
| 1856 | { .FromReg: VE::SF11, .ToReg: 11U }, |
| 1857 | { .FromReg: VE::SF12, .ToReg: 12U }, |
| 1858 | { .FromReg: VE::SF13, .ToReg: 13U }, |
| 1859 | { .FromReg: VE::SF14, .ToReg: 14U }, |
| 1860 | { .FromReg: VE::SF15, .ToReg: 15U }, |
| 1861 | { .FromReg: VE::SF16, .ToReg: 16U }, |
| 1862 | { .FromReg: VE::SF17, .ToReg: 17U }, |
| 1863 | { .FromReg: VE::SF18, .ToReg: 18U }, |
| 1864 | { .FromReg: VE::SF19, .ToReg: 19U }, |
| 1865 | { .FromReg: VE::SF20, .ToReg: 20U }, |
| 1866 | { .FromReg: VE::SF21, .ToReg: 21U }, |
| 1867 | { .FromReg: VE::SF22, .ToReg: 22U }, |
| 1868 | { .FromReg: VE::SF23, .ToReg: 23U }, |
| 1869 | { .FromReg: VE::SF24, .ToReg: 24U }, |
| 1870 | { .FromReg: VE::SF25, .ToReg: 25U }, |
| 1871 | { .FromReg: VE::SF26, .ToReg: 26U }, |
| 1872 | { .FromReg: VE::SF27, .ToReg: 27U }, |
| 1873 | { .FromReg: VE::SF28, .ToReg: 28U }, |
| 1874 | { .FromReg: VE::SF29, .ToReg: 29U }, |
| 1875 | { .FromReg: VE::SF30, .ToReg: 30U }, |
| 1876 | { .FromReg: VE::SF31, .ToReg: 31U }, |
| 1877 | { .FromReg: VE::SF32, .ToReg: 32U }, |
| 1878 | { .FromReg: VE::SF33, .ToReg: 33U }, |
| 1879 | { .FromReg: VE::SF34, .ToReg: 34U }, |
| 1880 | { .FromReg: VE::SF35, .ToReg: 35U }, |
| 1881 | { .FromReg: VE::SF36, .ToReg: 36U }, |
| 1882 | { .FromReg: VE::SF37, .ToReg: 37U }, |
| 1883 | { .FromReg: VE::SF38, .ToReg: 38U }, |
| 1884 | { .FromReg: VE::SF39, .ToReg: 39U }, |
| 1885 | { .FromReg: VE::SF40, .ToReg: 40U }, |
| 1886 | { .FromReg: VE::SF41, .ToReg: 41U }, |
| 1887 | { .FromReg: VE::SF42, .ToReg: 42U }, |
| 1888 | { .FromReg: VE::SF43, .ToReg: 43U }, |
| 1889 | { .FromReg: VE::SF44, .ToReg: 44U }, |
| 1890 | { .FromReg: VE::SF45, .ToReg: 45U }, |
| 1891 | { .FromReg: VE::SF46, .ToReg: 46U }, |
| 1892 | { .FromReg: VE::SF47, .ToReg: 47U }, |
| 1893 | { .FromReg: VE::SF48, .ToReg: 48U }, |
| 1894 | { .FromReg: VE::SF49, .ToReg: 49U }, |
| 1895 | { .FromReg: VE::SF50, .ToReg: 50U }, |
| 1896 | { .FromReg: VE::SF51, .ToReg: 51U }, |
| 1897 | { .FromReg: VE::SF52, .ToReg: 52U }, |
| 1898 | { .FromReg: VE::SF53, .ToReg: 53U }, |
| 1899 | { .FromReg: VE::SF54, .ToReg: 54U }, |
| 1900 | { .FromReg: VE::SF55, .ToReg: 55U }, |
| 1901 | { .FromReg: VE::SF56, .ToReg: 56U }, |
| 1902 | { .FromReg: VE::SF57, .ToReg: 57U }, |
| 1903 | { .FromReg: VE::SF58, .ToReg: 58U }, |
| 1904 | { .FromReg: VE::SF59, .ToReg: 59U }, |
| 1905 | { .FromReg: VE::SF60, .ToReg: 60U }, |
| 1906 | { .FromReg: VE::SF61, .ToReg: 61U }, |
| 1907 | { .FromReg: VE::SF62, .ToReg: 62U }, |
| 1908 | { .FromReg: VE::SF63, .ToReg: 63U }, |
| 1909 | { .FromReg: VE::SW0, .ToReg: 0U }, |
| 1910 | { .FromReg: VE::SW1, .ToReg: 1U }, |
| 1911 | { .FromReg: VE::SW2, .ToReg: 2U }, |
| 1912 | { .FromReg: VE::SW3, .ToReg: 3U }, |
| 1913 | { .FromReg: VE::SW4, .ToReg: 4U }, |
| 1914 | { .FromReg: VE::SW5, .ToReg: 5U }, |
| 1915 | { .FromReg: VE::SW6, .ToReg: 6U }, |
| 1916 | { .FromReg: VE::SW7, .ToReg: 7U }, |
| 1917 | { .FromReg: VE::SW8, .ToReg: 8U }, |
| 1918 | { .FromReg: VE::SW9, .ToReg: 9U }, |
| 1919 | { .FromReg: VE::SW10, .ToReg: 10U }, |
| 1920 | { .FromReg: VE::SW11, .ToReg: 11U }, |
| 1921 | { .FromReg: VE::SW12, .ToReg: 12U }, |
| 1922 | { .FromReg: VE::SW13, .ToReg: 13U }, |
| 1923 | { .FromReg: VE::SW14, .ToReg: 14U }, |
| 1924 | { .FromReg: VE::SW15, .ToReg: 15U }, |
| 1925 | { .FromReg: VE::SW16, .ToReg: 16U }, |
| 1926 | { .FromReg: VE::SW17, .ToReg: 17U }, |
| 1927 | { .FromReg: VE::SW18, .ToReg: 18U }, |
| 1928 | { .FromReg: VE::SW19, .ToReg: 19U }, |
| 1929 | { .FromReg: VE::SW20, .ToReg: 20U }, |
| 1930 | { .FromReg: VE::SW21, .ToReg: 21U }, |
| 1931 | { .FromReg: VE::SW22, .ToReg: 22U }, |
| 1932 | { .FromReg: VE::SW23, .ToReg: 23U }, |
| 1933 | { .FromReg: VE::SW24, .ToReg: 24U }, |
| 1934 | { .FromReg: VE::SW25, .ToReg: 25U }, |
| 1935 | { .FromReg: VE::SW26, .ToReg: 26U }, |
| 1936 | { .FromReg: VE::SW27, .ToReg: 27U }, |
| 1937 | { .FromReg: VE::SW28, .ToReg: 28U }, |
| 1938 | { .FromReg: VE::SW29, .ToReg: 29U }, |
| 1939 | { .FromReg: VE::SW30, .ToReg: 30U }, |
| 1940 | { .FromReg: VE::SW31, .ToReg: 31U }, |
| 1941 | { .FromReg: VE::SW32, .ToReg: 32U }, |
| 1942 | { .FromReg: VE::SW33, .ToReg: 33U }, |
| 1943 | { .FromReg: VE::SW34, .ToReg: 34U }, |
| 1944 | { .FromReg: VE::SW35, .ToReg: 35U }, |
| 1945 | { .FromReg: VE::SW36, .ToReg: 36U }, |
| 1946 | { .FromReg: VE::SW37, .ToReg: 37U }, |
| 1947 | { .FromReg: VE::SW38, .ToReg: 38U }, |
| 1948 | { .FromReg: VE::SW39, .ToReg: 39U }, |
| 1949 | { .FromReg: VE::SW40, .ToReg: 40U }, |
| 1950 | { .FromReg: VE::SW41, .ToReg: 41U }, |
| 1951 | { .FromReg: VE::SW42, .ToReg: 42U }, |
| 1952 | { .FromReg: VE::SW43, .ToReg: 43U }, |
| 1953 | { .FromReg: VE::SW44, .ToReg: 44U }, |
| 1954 | { .FromReg: VE::SW45, .ToReg: 45U }, |
| 1955 | { .FromReg: VE::SW46, .ToReg: 46U }, |
| 1956 | { .FromReg: VE::SW47, .ToReg: 47U }, |
| 1957 | { .FromReg: VE::SW48, .ToReg: 48U }, |
| 1958 | { .FromReg: VE::SW49, .ToReg: 49U }, |
| 1959 | { .FromReg: VE::SW50, .ToReg: 50U }, |
| 1960 | { .FromReg: VE::SW51, .ToReg: 51U }, |
| 1961 | { .FromReg: VE::SW52, .ToReg: 52U }, |
| 1962 | { .FromReg: VE::SW53, .ToReg: 53U }, |
| 1963 | { .FromReg: VE::SW54, .ToReg: 54U }, |
| 1964 | { .FromReg: VE::SW55, .ToReg: 55U }, |
| 1965 | { .FromReg: VE::SW56, .ToReg: 56U }, |
| 1966 | { .FromReg: VE::SW57, .ToReg: 57U }, |
| 1967 | { .FromReg: VE::SW58, .ToReg: 58U }, |
| 1968 | { .FromReg: VE::SW59, .ToReg: 59U }, |
| 1969 | { .FromReg: VE::SW60, .ToReg: 60U }, |
| 1970 | { .FromReg: VE::SW61, .ToReg: 61U }, |
| 1971 | { .FromReg: VE::SW62, .ToReg: 62U }, |
| 1972 | { .FromReg: VE::SW63, .ToReg: 63U }, |
| 1973 | { .FromReg: VE::SX0, .ToReg: 0U }, |
| 1974 | { .FromReg: VE::SX1, .ToReg: 1U }, |
| 1975 | { .FromReg: VE::SX2, .ToReg: 2U }, |
| 1976 | { .FromReg: VE::SX3, .ToReg: 3U }, |
| 1977 | { .FromReg: VE::SX4, .ToReg: 4U }, |
| 1978 | { .FromReg: VE::SX5, .ToReg: 5U }, |
| 1979 | { .FromReg: VE::SX6, .ToReg: 6U }, |
| 1980 | { .FromReg: VE::SX7, .ToReg: 7U }, |
| 1981 | { .FromReg: VE::SX8, .ToReg: 8U }, |
| 1982 | { .FromReg: VE::SX9, .ToReg: 9U }, |
| 1983 | { .FromReg: VE::SX10, .ToReg: 10U }, |
| 1984 | { .FromReg: VE::SX11, .ToReg: 11U }, |
| 1985 | { .FromReg: VE::SX12, .ToReg: 12U }, |
| 1986 | { .FromReg: VE::SX13, .ToReg: 13U }, |
| 1987 | { .FromReg: VE::SX14, .ToReg: 14U }, |
| 1988 | { .FromReg: VE::SX15, .ToReg: 15U }, |
| 1989 | { .FromReg: VE::SX16, .ToReg: 16U }, |
| 1990 | { .FromReg: VE::SX17, .ToReg: 17U }, |
| 1991 | { .FromReg: VE::SX18, .ToReg: 18U }, |
| 1992 | { .FromReg: VE::SX19, .ToReg: 19U }, |
| 1993 | { .FromReg: VE::SX20, .ToReg: 20U }, |
| 1994 | { .FromReg: VE::SX21, .ToReg: 21U }, |
| 1995 | { .FromReg: VE::SX22, .ToReg: 22U }, |
| 1996 | { .FromReg: VE::SX23, .ToReg: 23U }, |
| 1997 | { .FromReg: VE::SX24, .ToReg: 24U }, |
| 1998 | { .FromReg: VE::SX25, .ToReg: 25U }, |
| 1999 | { .FromReg: VE::SX26, .ToReg: 26U }, |
| 2000 | { .FromReg: VE::SX27, .ToReg: 27U }, |
| 2001 | { .FromReg: VE::SX28, .ToReg: 28U }, |
| 2002 | { .FromReg: VE::SX29, .ToReg: 29U }, |
| 2003 | { .FromReg: VE::SX30, .ToReg: 30U }, |
| 2004 | { .FromReg: VE::SX31, .ToReg: 31U }, |
| 2005 | { .FromReg: VE::SX32, .ToReg: 32U }, |
| 2006 | { .FromReg: VE::SX33, .ToReg: 33U }, |
| 2007 | { .FromReg: VE::SX34, .ToReg: 34U }, |
| 2008 | { .FromReg: VE::SX35, .ToReg: 35U }, |
| 2009 | { .FromReg: VE::SX36, .ToReg: 36U }, |
| 2010 | { .FromReg: VE::SX37, .ToReg: 37U }, |
| 2011 | { .FromReg: VE::SX38, .ToReg: 38U }, |
| 2012 | { .FromReg: VE::SX39, .ToReg: 39U }, |
| 2013 | { .FromReg: VE::SX40, .ToReg: 40U }, |
| 2014 | { .FromReg: VE::SX41, .ToReg: 41U }, |
| 2015 | { .FromReg: VE::SX42, .ToReg: 42U }, |
| 2016 | { .FromReg: VE::SX43, .ToReg: 43U }, |
| 2017 | { .FromReg: VE::SX44, .ToReg: 44U }, |
| 2018 | { .FromReg: VE::SX45, .ToReg: 45U }, |
| 2019 | { .FromReg: VE::SX46, .ToReg: 46U }, |
| 2020 | { .FromReg: VE::SX47, .ToReg: 47U }, |
| 2021 | { .FromReg: VE::SX48, .ToReg: 48U }, |
| 2022 | { .FromReg: VE::SX49, .ToReg: 49U }, |
| 2023 | { .FromReg: VE::SX50, .ToReg: 50U }, |
| 2024 | { .FromReg: VE::SX51, .ToReg: 51U }, |
| 2025 | { .FromReg: VE::SX52, .ToReg: 52U }, |
| 2026 | { .FromReg: VE::SX53, .ToReg: 53U }, |
| 2027 | { .FromReg: VE::SX54, .ToReg: 54U }, |
| 2028 | { .FromReg: VE::SX55, .ToReg: 55U }, |
| 2029 | { .FromReg: VE::SX56, .ToReg: 56U }, |
| 2030 | { .FromReg: VE::SX57, .ToReg: 57U }, |
| 2031 | { .FromReg: VE::SX58, .ToReg: 58U }, |
| 2032 | { .FromReg: VE::SX59, .ToReg: 59U }, |
| 2033 | { .FromReg: VE::SX60, .ToReg: 60U }, |
| 2034 | { .FromReg: VE::SX61, .ToReg: 61U }, |
| 2035 | { .FromReg: VE::SX62, .ToReg: 62U }, |
| 2036 | { .FromReg: VE::SX63, .ToReg: 63U }, |
| 2037 | { .FromReg: VE::V0, .ToReg: 64U }, |
| 2038 | { .FromReg: VE::V1, .ToReg: 65U }, |
| 2039 | { .FromReg: VE::V2, .ToReg: 66U }, |
| 2040 | { .FromReg: VE::V3, .ToReg: 67U }, |
| 2041 | { .FromReg: VE::V4, .ToReg: 68U }, |
| 2042 | { .FromReg: VE::V5, .ToReg: 69U }, |
| 2043 | { .FromReg: VE::V6, .ToReg: 70U }, |
| 2044 | { .FromReg: VE::V7, .ToReg: 71U }, |
| 2045 | { .FromReg: VE::V8, .ToReg: 72U }, |
| 2046 | { .FromReg: VE::V9, .ToReg: 73U }, |
| 2047 | { .FromReg: VE::V10, .ToReg: 74U }, |
| 2048 | { .FromReg: VE::V11, .ToReg: 75U }, |
| 2049 | { .FromReg: VE::V12, .ToReg: 76U }, |
| 2050 | { .FromReg: VE::V13, .ToReg: 77U }, |
| 2051 | { .FromReg: VE::V14, .ToReg: 78U }, |
| 2052 | { .FromReg: VE::V15, .ToReg: 79U }, |
| 2053 | { .FromReg: VE::V16, .ToReg: 80U }, |
| 2054 | { .FromReg: VE::V17, .ToReg: 81U }, |
| 2055 | { .FromReg: VE::V18, .ToReg: 82U }, |
| 2056 | { .FromReg: VE::V19, .ToReg: 83U }, |
| 2057 | { .FromReg: VE::V20, .ToReg: 84U }, |
| 2058 | { .FromReg: VE::V21, .ToReg: 85U }, |
| 2059 | { .FromReg: VE::V22, .ToReg: 86U }, |
| 2060 | { .FromReg: VE::V23, .ToReg: 87U }, |
| 2061 | { .FromReg: VE::V24, .ToReg: 88U }, |
| 2062 | { .FromReg: VE::V25, .ToReg: 89U }, |
| 2063 | { .FromReg: VE::V26, .ToReg: 90U }, |
| 2064 | { .FromReg: VE::V27, .ToReg: 91U }, |
| 2065 | { .FromReg: VE::V28, .ToReg: 92U }, |
| 2066 | { .FromReg: VE::V29, .ToReg: 93U }, |
| 2067 | { .FromReg: VE::V30, .ToReg: 94U }, |
| 2068 | { .FromReg: VE::V31, .ToReg: 95U }, |
| 2069 | { .FromReg: VE::V32, .ToReg: 96U }, |
| 2070 | { .FromReg: VE::V33, .ToReg: 97U }, |
| 2071 | { .FromReg: VE::V34, .ToReg: 98U }, |
| 2072 | { .FromReg: VE::V35, .ToReg: 99U }, |
| 2073 | { .FromReg: VE::V36, .ToReg: 100U }, |
| 2074 | { .FromReg: VE::V37, .ToReg: 101U }, |
| 2075 | { .FromReg: VE::V38, .ToReg: 102U }, |
| 2076 | { .FromReg: VE::V39, .ToReg: 103U }, |
| 2077 | { .FromReg: VE::V40, .ToReg: 104U }, |
| 2078 | { .FromReg: VE::V41, .ToReg: 105U }, |
| 2079 | { .FromReg: VE::V42, .ToReg: 106U }, |
| 2080 | { .FromReg: VE::V43, .ToReg: 107U }, |
| 2081 | { .FromReg: VE::V44, .ToReg: 108U }, |
| 2082 | { .FromReg: VE::V45, .ToReg: 109U }, |
| 2083 | { .FromReg: VE::V46, .ToReg: 110U }, |
| 2084 | { .FromReg: VE::V47, .ToReg: 111U }, |
| 2085 | { .FromReg: VE::V48, .ToReg: 112U }, |
| 2086 | { .FromReg: VE::V49, .ToReg: 113U }, |
| 2087 | { .FromReg: VE::V50, .ToReg: 114U }, |
| 2088 | { .FromReg: VE::V51, .ToReg: 115U }, |
| 2089 | { .FromReg: VE::V52, .ToReg: 116U }, |
| 2090 | { .FromReg: VE::V53, .ToReg: 117U }, |
| 2091 | { .FromReg: VE::V54, .ToReg: 118U }, |
| 2092 | { .FromReg: VE::V55, .ToReg: 119U }, |
| 2093 | { .FromReg: VE::V56, .ToReg: 120U }, |
| 2094 | { .FromReg: VE::V57, .ToReg: 121U }, |
| 2095 | { .FromReg: VE::V58, .ToReg: 122U }, |
| 2096 | { .FromReg: VE::V59, .ToReg: 123U }, |
| 2097 | { .FromReg: VE::V60, .ToReg: 124U }, |
| 2098 | { .FromReg: VE::V61, .ToReg: 125U }, |
| 2099 | { .FromReg: VE::V62, .ToReg: 126U }, |
| 2100 | { .FromReg: VE::V63, .ToReg: 127U }, |
| 2101 | { .FromReg: VE::VM0, .ToReg: 128U }, |
| 2102 | { .FromReg: VE::VM1, .ToReg: 129U }, |
| 2103 | { .FromReg: VE::VM2, .ToReg: 130U }, |
| 2104 | { .FromReg: VE::VM3, .ToReg: 131U }, |
| 2105 | { .FromReg: VE::VM4, .ToReg: 132U }, |
| 2106 | { .FromReg: VE::VM5, .ToReg: 133U }, |
| 2107 | { .FromReg: VE::VM6, .ToReg: 134U }, |
| 2108 | { .FromReg: VE::VM7, .ToReg: 135U }, |
| 2109 | { .FromReg: VE::VM8, .ToReg: 136U }, |
| 2110 | { .FromReg: VE::VM9, .ToReg: 137U }, |
| 2111 | { .FromReg: VE::VM10, .ToReg: 138U }, |
| 2112 | { .FromReg: VE::VM11, .ToReg: 139U }, |
| 2113 | { .FromReg: VE::VM12, .ToReg: 140U }, |
| 2114 | { .FromReg: VE::VM13, .ToReg: 141U }, |
| 2115 | { .FromReg: VE::VM14, .ToReg: 142U }, |
| 2116 | { .FromReg: VE::VM15, .ToReg: 143U }, |
| 2117 | }; |
| 2118 | extern const unsigned VEEHFlavour0L2DwarfSize = std::size(VEEHFlavour0L2Dwarf); |
| 2119 | |
| 2120 | extern const uint16_t VERegEncodingTable[] = { |
| 2121 | 0, |
| 2122 | 62, |
| 2123 | 7, |
| 2124 | 1, |
| 2125 | 2, |
| 2126 | 0, |
| 2127 | 255, |
| 2128 | 63, |
| 2129 | 16, |
| 2130 | 17, |
| 2131 | 18, |
| 2132 | 19, |
| 2133 | 20, |
| 2134 | 21, |
| 2135 | 22, |
| 2136 | 23, |
| 2137 | 24, |
| 2138 | 25, |
| 2139 | 26, |
| 2140 | 27, |
| 2141 | 28, |
| 2142 | 29, |
| 2143 | 30, |
| 2144 | 8, |
| 2145 | 9, |
| 2146 | 10, |
| 2147 | 11, |
| 2148 | 0, |
| 2149 | 2, |
| 2150 | 4, |
| 2151 | 6, |
| 2152 | 8, |
| 2153 | 10, |
| 2154 | 12, |
| 2155 | 14, |
| 2156 | 16, |
| 2157 | 18, |
| 2158 | 20, |
| 2159 | 22, |
| 2160 | 24, |
| 2161 | 26, |
| 2162 | 28, |
| 2163 | 30, |
| 2164 | 32, |
| 2165 | 34, |
| 2166 | 36, |
| 2167 | 38, |
| 2168 | 40, |
| 2169 | 42, |
| 2170 | 44, |
| 2171 | 46, |
| 2172 | 48, |
| 2173 | 50, |
| 2174 | 52, |
| 2175 | 54, |
| 2176 | 56, |
| 2177 | 58, |
| 2178 | 60, |
| 2179 | 62, |
| 2180 | 0, |
| 2181 | 1, |
| 2182 | 2, |
| 2183 | 3, |
| 2184 | 4, |
| 2185 | 5, |
| 2186 | 6, |
| 2187 | 7, |
| 2188 | 8, |
| 2189 | 9, |
| 2190 | 10, |
| 2191 | 11, |
| 2192 | 12, |
| 2193 | 13, |
| 2194 | 14, |
| 2195 | 15, |
| 2196 | 16, |
| 2197 | 17, |
| 2198 | 18, |
| 2199 | 19, |
| 2200 | 20, |
| 2201 | 21, |
| 2202 | 22, |
| 2203 | 23, |
| 2204 | 24, |
| 2205 | 25, |
| 2206 | 26, |
| 2207 | 27, |
| 2208 | 28, |
| 2209 | 29, |
| 2210 | 30, |
| 2211 | 31, |
| 2212 | 32, |
| 2213 | 33, |
| 2214 | 34, |
| 2215 | 35, |
| 2216 | 36, |
| 2217 | 37, |
| 2218 | 38, |
| 2219 | 39, |
| 2220 | 40, |
| 2221 | 41, |
| 2222 | 42, |
| 2223 | 43, |
| 2224 | 44, |
| 2225 | 45, |
| 2226 | 46, |
| 2227 | 47, |
| 2228 | 48, |
| 2229 | 49, |
| 2230 | 50, |
| 2231 | 51, |
| 2232 | 52, |
| 2233 | 53, |
| 2234 | 54, |
| 2235 | 55, |
| 2236 | 56, |
| 2237 | 57, |
| 2238 | 58, |
| 2239 | 59, |
| 2240 | 60, |
| 2241 | 61, |
| 2242 | 62, |
| 2243 | 63, |
| 2244 | 0, |
| 2245 | 1, |
| 2246 | 2, |
| 2247 | 3, |
| 2248 | 4, |
| 2249 | 5, |
| 2250 | 6, |
| 2251 | 7, |
| 2252 | 8, |
| 2253 | 9, |
| 2254 | 10, |
| 2255 | 11, |
| 2256 | 12, |
| 2257 | 13, |
| 2258 | 14, |
| 2259 | 15, |
| 2260 | 16, |
| 2261 | 17, |
| 2262 | 18, |
| 2263 | 19, |
| 2264 | 20, |
| 2265 | 21, |
| 2266 | 22, |
| 2267 | 23, |
| 2268 | 24, |
| 2269 | 25, |
| 2270 | 26, |
| 2271 | 27, |
| 2272 | 28, |
| 2273 | 29, |
| 2274 | 30, |
| 2275 | 31, |
| 2276 | 32, |
| 2277 | 33, |
| 2278 | 34, |
| 2279 | 35, |
| 2280 | 36, |
| 2281 | 37, |
| 2282 | 38, |
| 2283 | 39, |
| 2284 | 40, |
| 2285 | 41, |
| 2286 | 42, |
| 2287 | 43, |
| 2288 | 44, |
| 2289 | 45, |
| 2290 | 46, |
| 2291 | 47, |
| 2292 | 48, |
| 2293 | 49, |
| 2294 | 50, |
| 2295 | 51, |
| 2296 | 52, |
| 2297 | 53, |
| 2298 | 54, |
| 2299 | 55, |
| 2300 | 56, |
| 2301 | 57, |
| 2302 | 58, |
| 2303 | 59, |
| 2304 | 60, |
| 2305 | 61, |
| 2306 | 62, |
| 2307 | 63, |
| 2308 | 0, |
| 2309 | 1, |
| 2310 | 2, |
| 2311 | 3, |
| 2312 | 4, |
| 2313 | 5, |
| 2314 | 6, |
| 2315 | 7, |
| 2316 | 8, |
| 2317 | 9, |
| 2318 | 10, |
| 2319 | 11, |
| 2320 | 12, |
| 2321 | 13, |
| 2322 | 14, |
| 2323 | 15, |
| 2324 | 16, |
| 2325 | 17, |
| 2326 | 18, |
| 2327 | 19, |
| 2328 | 20, |
| 2329 | 21, |
| 2330 | 22, |
| 2331 | 23, |
| 2332 | 24, |
| 2333 | 25, |
| 2334 | 26, |
| 2335 | 27, |
| 2336 | 28, |
| 2337 | 29, |
| 2338 | 30, |
| 2339 | 31, |
| 2340 | 32, |
| 2341 | 33, |
| 2342 | 34, |
| 2343 | 35, |
| 2344 | 36, |
| 2345 | 37, |
| 2346 | 38, |
| 2347 | 39, |
| 2348 | 40, |
| 2349 | 41, |
| 2350 | 42, |
| 2351 | 43, |
| 2352 | 44, |
| 2353 | 45, |
| 2354 | 46, |
| 2355 | 47, |
| 2356 | 48, |
| 2357 | 49, |
| 2358 | 50, |
| 2359 | 51, |
| 2360 | 52, |
| 2361 | 53, |
| 2362 | 54, |
| 2363 | 55, |
| 2364 | 56, |
| 2365 | 57, |
| 2366 | 58, |
| 2367 | 59, |
| 2368 | 60, |
| 2369 | 61, |
| 2370 | 62, |
| 2371 | 63, |
| 2372 | 0, |
| 2373 | 1, |
| 2374 | 2, |
| 2375 | 3, |
| 2376 | 4, |
| 2377 | 5, |
| 2378 | 6, |
| 2379 | 7, |
| 2380 | 8, |
| 2381 | 9, |
| 2382 | 10, |
| 2383 | 11, |
| 2384 | 12, |
| 2385 | 13, |
| 2386 | 14, |
| 2387 | 15, |
| 2388 | 16, |
| 2389 | 17, |
| 2390 | 18, |
| 2391 | 19, |
| 2392 | 20, |
| 2393 | 21, |
| 2394 | 22, |
| 2395 | 23, |
| 2396 | 24, |
| 2397 | 25, |
| 2398 | 26, |
| 2399 | 27, |
| 2400 | 28, |
| 2401 | 29, |
| 2402 | 30, |
| 2403 | 31, |
| 2404 | 32, |
| 2405 | 33, |
| 2406 | 34, |
| 2407 | 35, |
| 2408 | 36, |
| 2409 | 37, |
| 2410 | 38, |
| 2411 | 39, |
| 2412 | 40, |
| 2413 | 41, |
| 2414 | 42, |
| 2415 | 43, |
| 2416 | 44, |
| 2417 | 45, |
| 2418 | 46, |
| 2419 | 47, |
| 2420 | 48, |
| 2421 | 49, |
| 2422 | 50, |
| 2423 | 51, |
| 2424 | 52, |
| 2425 | 53, |
| 2426 | 54, |
| 2427 | 55, |
| 2428 | 56, |
| 2429 | 57, |
| 2430 | 58, |
| 2431 | 59, |
| 2432 | 60, |
| 2433 | 61, |
| 2434 | 62, |
| 2435 | 63, |
| 2436 | 0, |
| 2437 | 1, |
| 2438 | 2, |
| 2439 | 3, |
| 2440 | 4, |
| 2441 | 5, |
| 2442 | 6, |
| 2443 | 7, |
| 2444 | 8, |
| 2445 | 9, |
| 2446 | 10, |
| 2447 | 11, |
| 2448 | 12, |
| 2449 | 13, |
| 2450 | 14, |
| 2451 | 15, |
| 2452 | 0, |
| 2453 | 2, |
| 2454 | 4, |
| 2455 | 6, |
| 2456 | 8, |
| 2457 | 10, |
| 2458 | 12, |
| 2459 | 14, |
| 2460 | }; |
| 2461 | static inline void InitVEMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
| 2462 | RI->InitMCRegisterInfo(D: VERegDesc, NR: 339, RA, PC, C: VEMCRegisterClasses, NC: 10, RURoots: VERegUnitRoots, NRU: 299, DL: VERegDiffLists, RUMS: VELaneMaskLists, Strings: VERegStrings, ClassStrings: VERegClassStrings, SubIndices: VESubRegIdxLists, NumIndices: 9, |
| 2463 | RET: VERegEncodingTable); |
| 2464 | |
| 2465 | switch (DwarfFlavour) { |
| 2466 | default: |
| 2467 | llvm_unreachable("Unknown DWARF flavour" ); |
| 2468 | case 0: |
| 2469 | RI->mapDwarfRegsToLLVMRegs(Map: VEDwarfFlavour0Dwarf2L, Size: VEDwarfFlavour0Dwarf2LSize, isEH: false); |
| 2470 | break; |
| 2471 | } |
| 2472 | switch (EHFlavour) { |
| 2473 | default: |
| 2474 | llvm_unreachable("Unknown DWARF flavour" ); |
| 2475 | case 0: |
| 2476 | RI->mapDwarfRegsToLLVMRegs(Map: VEEHFlavour0Dwarf2L, Size: VEEHFlavour0Dwarf2LSize, isEH: true); |
| 2477 | break; |
| 2478 | } |
| 2479 | switch (DwarfFlavour) { |
| 2480 | default: |
| 2481 | llvm_unreachable("Unknown DWARF flavour" ); |
| 2482 | case 0: |
| 2483 | RI->mapLLVMRegsToDwarfRegs(Map: VEDwarfFlavour0L2Dwarf, Size: VEDwarfFlavour0L2DwarfSize, isEH: false); |
| 2484 | break; |
| 2485 | } |
| 2486 | switch (EHFlavour) { |
| 2487 | default: |
| 2488 | llvm_unreachable("Unknown DWARF flavour" ); |
| 2489 | case 0: |
| 2490 | RI->mapLLVMRegsToDwarfRegs(Map: VEEHFlavour0L2Dwarf, Size: VEEHFlavour0L2DwarfSize, isEH: true); |
| 2491 | break; |
| 2492 | } |
| 2493 | } |
| 2494 | |
| 2495 | } // end namespace llvm |
| 2496 | |
| 2497 | |